From chandlerc at gmail.com Mon Jan 10 01:19:38 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Mon, 10 Jan 2011 07:19:38 -0000 Subject: [llvm-commits] [llvm] r123161 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp test/Transforms/InstCombine/vec_demanded_elts.ll Message-ID: <20110110071938.1C0EC2A6C12C@llvm.org> Author: chandlerc Date: Mon Jan 10 01:19:37 2011 New Revision: 123161 URL: http://llvm.org/viewvc/llvm-project?rev=123161&view=rev Log: Teach instcombine about the rest of the SSE and SSE2 conversion intrinsics element dependencies. Reviewed by Nick. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=123161&r1=123160&r2=123161&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Mon Jan 10 01:19:37 2011 @@ -540,9 +540,16 @@ return new StoreInst(II->getArgOperand(1), Ptr); } break; - - case Intrinsic::x86_sse_cvttss2si: { - // These intrinsics only demands the 0th element of its input vector. If + + case Intrinsic::x86_sse_cvtss2si: + case Intrinsic::x86_sse_cvtss2si64: + case Intrinsic::x86_sse_cvttss2si: + case Intrinsic::x86_sse_cvttss2si64: + case Intrinsic::x86_sse2_cvtsd2si: + case Intrinsic::x86_sse2_cvtsd2si64: + case Intrinsic::x86_sse2_cvttsd2si: + case Intrinsic::x86_sse2_cvttsd2si64: { + // These intrinsics only demand the 0th element of their input vectors. If // we can simplify the input based on that, do so now. unsigned VWidth = cast(II->getArgOperand(0)->getType())->getNumElements(); @@ -555,7 +562,7 @@ } break; } - + case Intrinsic::ppc_altivec_vperm: // Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant. if (ConstantVector *Mask = dyn_cast(II->getArgOperand(2))) { Modified: llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts.ll?rev=123161&r1=123160&r2=123161&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts.ll Mon Jan 10 01:19:37 2011 @@ -36,6 +36,54 @@ ret i32 %tmp21 } +define i64 @test3(float %f, double %d) { +; CHECK: @test3 +; CHECK-NOT: insertelement {{.*}} 0.00 +; CHECK: ret +entry: + %v00 = insertelement <4 x float> undef, float %f, i32 0 + %v01 = insertelement <4 x float> %v00, float 0.000000e+00, i32 1 + %v02 = insertelement <4 x float> %v01, float 0.000000e+00, i32 2 + %v03 = insertelement <4 x float> %v02, float 0.000000e+00, i32 3 + %tmp0 = tail call i32 @llvm.x86.sse.cvtss2si(<4 x float> %v03) + %v10 = insertelement <4 x float> undef, float %f, i32 0 + %v11 = insertelement <4 x float> %v10, float 0.000000e+00, i32 1 + %v12 = insertelement <4 x float> %v11, float 0.000000e+00, i32 2 + %v13 = insertelement <4 x float> %v12, float 0.000000e+00, i32 3 + %tmp1 = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> %v13) + %v20 = insertelement <4 x float> undef, float %f, i32 0 + %v21 = insertelement <4 x float> %v20, float 0.000000e+00, i32 1 + %v22 = insertelement <4 x float> %v21, float 0.000000e+00, i32 2 + %v23 = insertelement <4 x float> %v22, float 0.000000e+00, i32 3 + %tmp2 = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> %v23) + %v30 = insertelement <4 x float> undef, float %f, i32 0 + %v31 = insertelement <4 x float> %v30, float 0.000000e+00, i32 1 + %v32 = insertelement <4 x float> %v31, float 0.000000e+00, i32 2 + %v33 = insertelement <4 x float> %v32, float 0.000000e+00, i32 3 + %tmp3 = tail call i64 @llvm.x86.sse.cvttss2si64(<4 x float> %v33) + %v40 = insertelement <2 x double> undef, double %d, i32 0 + %v41 = insertelement <2 x double> %v40, double 0.000000e+00, i32 1 + %tmp4 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %v41) + %v50 = insertelement <2 x double> undef, double %d, i32 0 + %v51 = insertelement <2 x double> %v50, double 0.000000e+00, i32 1 + %tmp5 = tail call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> %v51) + %v60 = insertelement <2 x double> undef, double %d, i32 0 + %v61 = insertelement <2 x double> %v60, double 0.000000e+00, i32 1 + %tmp6 = tail call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> %v61) + %v70 = insertelement <2 x double> undef, double %d, i32 0 + %v71 = insertelement <2 x double> %v70, double 0.000000e+00, i32 1 + %tmp7 = tail call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> %v71) + %tmp8 = add i32 %tmp0, %tmp2 + %tmp9 = add i32 %tmp4, %tmp6 + %tmp10 = add i32 %tmp8, %tmp9 + %tmp11 = sext i32 %tmp10 to i64 + %tmp12 = add i64 %tmp1, %tmp3 + %tmp13 = add i64 %tmp5, %tmp7 + %tmp14 = add i64 %tmp12, %tmp13 + %tmp15 = add i64 %tmp11, %tmp14 + ret i64 %tmp15 +} + define void @get_image() nounwind { ; CHECK: @get_image ; CHECK-NOT: extractelement @@ -80,4 +128,11 @@ declare <4 x float> @llvm.x86.sse.max.ss(<4 x float>, <4 x float>) +declare i32 @llvm.x86.sse.cvtss2si(<4 x float>) +declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) +declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) +declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) +declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) +declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) +declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) From fvbommel at gmail.com Mon Jan 10 01:35:50 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 10 Jan 2011 08:35:50 +0100 Subject: [llvm-commits] [llvm] r123105 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/nsw.ll In-Reply-To: <4D2A70A1.2060205@mxc.ca> References: <20110109022848.9FFDE2A6C12C@llvm.org> <4D2A70A1.2060205@mxc.ca> Message-ID: On Mon, Jan 10, 2011 at 3:36 AM, Nick Lewycky wrote: > Chris Lattner wrote: >> teach SCEV analysis of PHI nodes that PHI recurences formed >> with GEP instructions are always NUW, because PHIs cannot wrap >> the end of the address space. > > Aren't GEPs also NSW? I tried looking this up in the LangRef but wasn't > able to find it, but I've been coding under the impression that GEPs are > both nuw and nsw. On a 32-bit machine where the OS splits user/kernel memory as e.g. 3GB/1GB[1] there's no reason a pointer can't cross from 0x7fffffff to 0x80000000, so in general it's not a valid assumption. Of course, if you happen to be on x86-64 then that assumption is perfectly valid until some chip factory creates a CPU capable of mapping the full 64-bit address space. AFAIK no such chip exists yet. [1]: Also common: a 64-bit kernel running a 32-bit program, which can map almost 4GB for the program. From sabre at nondot.org Mon Jan 10 01:39:33 2011 From: sabre at nondot.org (Chris Lattner) Date: Sun, 9 Jan 2011 23:39:33 -0800 Subject: [llvm-commits] [llvm] r123105 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/nsw.ll In-Reply-To: <4D2A70A1.2060205@mxc.ca> References: <20110109022848.9FFDE2A6C12C@llvm.org> <4D2A70A1.2060205@mxc.ca> Message-ID: <9A52A810-099C-4CAB-8962-1E5AE910A8B9@nondot.org> On Jan 9, 2011, at 6:36 PM, Nick Lewycky wrote: > Chris Lattner wrote: >> Author: lattner >> Date: Sat Jan 8 20:28:48 2011 >> New Revision: 123105 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=123105&view=rev >> Log: >> teach SCEV analysis of PHI nodes that PHI recurences formed >> with GEP instructions are always NUW, because PHIs cannot wrap >> the end of the address space. > > Aren't GEPs also NSW? I tried looking this up in the LangRef but wasn't able to find it, but I've been coding under the impression that GEPs are both nuw and nsw. As Frits points out, on some architectures it is safe to assume that. However, since it isn't needed to prove any properties that I'm aware, it is not worth making it target parameterized. -Chris From clattner at apple.com Mon Jan 10 01:43:04 2011 From: clattner at apple.com (Chris Lattner) Date: Sun, 9 Jan 2011 23:43:04 -0800 Subject: [llvm-commits] [patch][8927] Add an unnamed_addr attribute In-Reply-To: <4D2A70F5.2010402@mxc.ca> References: <4D27E063.6060605@gmail.com> <4D2A70F5.2010402@mxc.ca> Message-ID: On Jan 9, 2011, at 6:37 PM, Nick Lewycky wrote: > Rafael ?vila de Esp?ndola wrote: >> This is the first step in fixing PR8927: >> >> The attached patch adds a unnamed_addr bit to global constants and >> functions. This will be used to indicate that the address is not >> significant and therefore the constant or function can be merged with >> others. >> >> If an optimization pass can show that an address is not used, it can set >> this. >> >> Examples of things that can have this set by the FE are globals created >> to hold string literals and C++ constructors. >> >> Aliases and non constant globals are not allowed to have unnamed_addr >> since I couldn't figure out any use for it. >> >> Comments? > > Silly idea, but we already have the concept of names in the IR. Why not > just make these anonymous? > > If you think that IR names shouldn't change semantics, consider that the > verifier already rejects global aliases without names. That's a clever idea. It would be fine for things like string constants (where ".str42" isn't super helpful), but for things like vtables, it really is helpful to have names, and they are required for linkage. -Chris From clattner at apple.com Mon Jan 10 01:44:07 2011 From: clattner at apple.com (Chris Lattner) Date: Sun, 9 Jan 2011 23:44:07 -0800 Subject: [llvm-commits] [llvm] r123161 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp test/Transforms/InstCombine/vec_demanded_elts.ll In-Reply-To: <20110110071938.1C0EC2A6C12C@llvm.org> References: <20110110071938.1C0EC2A6C12C@llvm.org> Message-ID: <2C39E74D-5BB5-4B81-AF8A-2BAAE909E098@apple.com> On Jan 9, 2011, at 11:19 PM, Chandler Carruth wrote: > Author: chandlerc > Date: Mon Jan 10 01:19:37 2011 > New Revision: 123161 > > URL: http://llvm.org/viewvc/llvm-project?rev=123161&view=rev > Log: > Teach instcombine about the rest of the SSE and SSE2 conversion > intrinsics element dependencies. Reviewed by Nick. Nice! Does this fix the readme entry? -Chris From clattner at apple.com Mon Jan 10 01:46:05 2011 From: clattner at apple.com (Chris Lattner) Date: Sun, 9 Jan 2011 23:46:05 -0800 Subject: [llvm-commits] [llvm] r123135 - /llvm/trunk/lib/Target/README.txt In-Reply-To: References: <20110109223618.D82902A6C12C@llvm.org> Message-ID: <83917870-38DA-4925-B924-6A14AB98ADF0@apple.com> On Jan 9, 2011, at 5:12 PM, Chandler Carruth wrote: > On Sun, Jan 9, 2011 at 4:39 PM, Chris Lattner wrote: > Chandler, I don't see what the issue is here. While it "would be nice" to have generic rounding mode support in the IR, there is no problem with having an intrinsic here. llvm.x86.sse2.cvtsd2si is a readnone function, so it should be optimized just about as well as fptosi. What specifically are we missing? > > If you're concerned about the extraneous mov + xor in: > + xorps %xmm1, %xmm1 > + movsd %xmm0, %xmm1 > + cvtsd2sil %xmm1, %eax > > The the right fix is to teach SimplifyDemandedVectorElts that llvm.x86.sse2.cvtsd2si does not demand a top element. This will allow the ir to be optimized to remove the insertion of the 0.0. > > Interesting. The other, and probably more important thing I was seeing is code like: > > int a() { return f(1.1) + g(2.2); } > > After inlining the 'g(2.2)' --> 2 constant folding works, but we're still left with an intrinsic call with a constant argument of 1.1: > > define i32 @_Z1av() nounwind readnone { > entry: > %0 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> ) nounwind > %add = add nsw i32 %0, 2 > ret i32 %add > } > > However, perhaps the right way to solve this is along the same lines: teach a pass to fold constant arguments to that intrinsic. I don't know how long a list of these types of transformations there will be however. If constant prop is enough, maybe this is the best way to go. We want intrinsics to be well optimized. In this case, constant folding should be added to lib/Analysis/ConstantFolding.cpp. Just grep for intrinsic to see how others are handled. -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110109/cc6bf1eb/attachment.html From sabre at nondot.org Mon Jan 10 01:51:32 2011 From: sabre at nondot.org (Chris Lattner) Date: Mon, 10 Jan 2011 07:51:32 -0000 Subject: [llvm-commits] [llvm] r123164 - /llvm/trunk/lib/CodeGen/MachineCSE.cpp Message-ID: <20110110075132.176DB2A6C12C@llvm.org> Author: lattner Date: Mon Jan 10 01:51:31 2011 New Revision: 123164 URL: http://llvm.org/viewvc/llvm-project?rev=123164&view=rev Log: fit in 80 cols and use MBB::isSuccessor instead of a hand rolled std::find. Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=123164&r1=123163&r2=123164&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Mon Jan 10 01:51:31 2011 @@ -284,14 +284,13 @@ MachineInstr *CSMI, MachineInstr *MI) { // FIXME: Heuristics that works around the lack the live range splitting. - // Heuristics #1: Don't cse "cheap" computating if the def is not local or in an - // immediate predecessor. We don't want to increase register pressure and end up - // causing other computation to be spilled. + // Heuristics #1: Don't CSE "cheap" computation if the def is not local or in + // an immediate predecessor. We don't want to increase register pressure and + // end up causing other computation to be spilled. if (MI->getDesc().isAsCheapAsAMove()) { MachineBasicBlock *CSBB = CSMI->getParent(); MachineBasicBlock *BB = MI->getParent(); - if (CSBB != BB && - find(CSBB->succ_begin(), CSBB->succ_end(), BB) == CSBB->succ_end()) + if (CSBB != BB && !CSBB->isSuccessor(BB)) return false; } From chandlerc at gmail.com Mon Jan 10 01:59:08 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Sun, 9 Jan 2011 23:59:08 -0800 Subject: [llvm-commits] [llvm] r123161 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp test/Transforms/InstCombine/vec_demanded_elts.ll In-Reply-To: <2C39E74D-5BB5-4B81-AF8A-2BAAE909E098@apple.com> References: <20110110071938.1C0EC2A6C12C@llvm.org> <2C39E74D-5BB5-4B81-AF8A-2BAAE909E098@apple.com> Message-ID: On Sun, Jan 9, 2011 at 11:44 PM, Chris Lattner wrote: > > On Jan 9, 2011, at 11:19 PM, Chandler Carruth wrote: > > > Author: chandlerc > > Date: Mon Jan 10 01:19:37 2011 > > New Revision: 123161 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=123161&view=rev > > Log: > > Teach instcombine about the rest of the SSE and SSE2 conversion > > intrinsics element dependencies. Reviewed by Nick. > > Nice! Does this fix the readme entry? > Not quite (for me). I'm looking at a few more steps... I'll update the README when I either get to them, or decide they're not worth it. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110109/5acbba03/attachment.html From chandlerc at gmail.com Mon Jan 10 03:02:58 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Mon, 10 Jan 2011 09:02:58 -0000 Subject: [llvm-commits] [llvm] r123165 - /llvm/trunk/lib/Analysis/ConstantFolding.cpp Message-ID: <20110110090258.41FA82A6C12D@llvm.org> Author: chandlerc Date: Mon Jan 10 03:02:58 2011 New Revision: 123165 URL: http://llvm.org/viewvc/llvm-project?rev=123165&view=rev Log: Cleanup some of the constant folding code to consistently test intrinsic IDs when available rather than using a mixture of IDs and textual name comparisons. Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=123165&r1=123164&r2=123165&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Mon Jan 10 03:02:58 2011 @@ -1127,7 +1127,7 @@ const Type *Ty = F->getReturnType(); if (NumOperands == 1) { if (ConstantFP *Op = dyn_cast(Operands[0])) { - if (Name == "llvm.convert.to.fp16") { + if (F->getIntrinsicID() == Intrinsic::convert_to_fp16) { APFloat Val(Op->getValueAPF()); bool lost = false; @@ -1185,8 +1185,8 @@ return ConstantFoldFP(log, V, Ty); else if (Name == "log10" && V > 0) return ConstantFoldFP(log10, V, Ty); - else if (Name == "llvm.sqrt.f32" || - Name == "llvm.sqrt.f64") { + else if (F->getIntrinsicID() == Intrinsic::sqrt && + (Ty->isFloatTy() || Ty->isDoubleTy())) { if (V >= -0.0) return ConstantFoldFP(sqrt, V, Ty); else // Undefined @@ -1216,18 +1216,18 @@ } return 0; } - - + if (ConstantInt *Op = dyn_cast(Operands[0])) { - if (Name.startswith("llvm.bswap")) + switch (F->getIntrinsicID()) { + case Intrinsic::bswap: return ConstantInt::get(F->getContext(), Op->getValue().byteSwap()); - else if (Name.startswith("llvm.ctpop")) + case Intrinsic::ctpop: return ConstantInt::get(Ty, Op->getValue().countPopulation()); - else if (Name.startswith("llvm.cttz")) + case Intrinsic::cttz: return ConstantInt::get(Ty, Op->getValue().countTrailingZeros()); - else if (Name.startswith("llvm.ctlz")) + case Intrinsic::ctlz: return ConstantInt::get(Ty, Op->getValue().countLeadingZeros()); - else if (Name == "llvm.convert.from.fp16") { + case Intrinsic::convert_from_fp16: { APFloat Val(Op->getValue()); bool lost = false; @@ -1241,18 +1241,20 @@ return ConstantFP::get(F->getContext(), Val); } - return 0; + default: + return 0; + } } - + if (isa(Operands[0])) { - if (Name.startswith("llvm.bswap")) + if (F->getIntrinsicID() == Intrinsic::bswap) return Operands[0]; return 0; } return 0; } - + if (NumOperands == 2) { if (ConstantFP *Op1 = dyn_cast(Operands[0])) { if (!Ty->isFloatTy() && !Ty->isDoubleTy()) @@ -1275,11 +1277,11 @@ if (Name == "atan2") return ConstantFoldBinaryFP(atan2, Op1V, Op2V, Ty); } else if (ConstantInt *Op2C = dyn_cast(Operands[1])) { - if (Name == "llvm.powi.f32") + if (F->getIntrinsicID() == Intrinsic::powi && Ty->isFloatTy()) return ConstantFP::get(F->getContext(), APFloat((float)std::pow((float)Op1V, (int)Op2C->getZExtValue()))); - if (Name == "llvm.powi.f64") + if (F->getIntrinsicID() == Intrinsic::powi && Ty->isDoubleTy()) return ConstantFP::get(F->getContext(), APFloat((double)std::pow((double)Op1V, (int)Op2C->getZExtValue()))); From chandlerc at google.com Mon Jan 10 03:18:41 2011 From: chandlerc at google.com (Chandler Carruth) Date: Mon, 10 Jan 2011 01:18:41 -0800 Subject: [llvm-commits] PATCH: Teach constant folding about SSE[2] conversion intrinsics Message-ID: This resolves the majority of what I've been able to spot actually happening due to my last README entry. I've been able to think of at least one more really trivial fold that we could do: (cvtsd2si (sitofp x)) -> x. However, I don't yet have any benchmark that shows this is useful. At the very least, my examples: #include int f(double x) { return _mm_cvtsd_si32(_mm_set_sd(x)); } int g(double x) { return _mm_cvttsd_si32(_mm_set_sd(x)); } int h() { return f(1.1) + g(2.2); } Now compiles to: define i32 @_Z1fd(double %x) nounwind readnone { entry: %vecinit.i = insertelement <2 x double> undef, double %x, i32 0 %0 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %vecinit.i) nounwind ret i32 %0 } define i32 @_Z1gd(double %x) nounwind readnone { entry: %conv.i = fptosi double %x to i32 ret i32 %conv.i } define i32 @_Z1av() nounwind readnone { entry: ret i32 3 } which looks pretty good to me. =] One question, where is the best place to test this? I couldn't find a direct test for ConstantFolding. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110110/e6802e45/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: fold_cvt_intrins.patch Type: application/octet-stream Size: 2791 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110110/e6802e45/attachment.obj From fvbommel at gmail.com Mon Jan 10 04:10:48 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 10 Jan 2011 11:10:48 +0100 Subject: [llvm-commits] PATCH: instcombine switch on select of constants to br In-Reply-To: <130DB463-EF73-40A2-8166-5D3A014D9D12@gmail.com> References: <893CFB3C-832C-4959-AE72-4186FCD61E99@gmail.com> <4D2A730F.2090207@mxc.ca> <130DB463-EF73-40A2-8166-5D3A014D9D12@gmail.com> Message-ID: On Mon, Jan 10, 2011 at 4:14 AM, Alistair Lynn wrote: > So done. Please don't top-post. > On 10 Jan 2011, at 02:46, Nick Lewycky wrote: > >> Alistair Lynn wrote: >>> The attached patch catches a previously missed optimisation on switches of the >>> form switch (select cond, A, B) where A and B are constants - the switch can be >>> folded to a conditional branch on cond. I wrote a similar optimization for indirectbr instead of switch. You're not updating PHI nodes in successors. You should call Succ->removePredecessor(BB) for each successor that is removed. Some edge cases: - The input values are different, and go to different successors. Fold into a conditional branch and keep exactly one copy of both successors. - The input values are different, but their successors are the same. Keep folding this into an unconditional branch, and remove all but one successor. In particular, note that the successor being jumped to will have multiple PHI entries for this predecessor, and only one of those may remain. - The input values are equal, or both are caught by the default case. Remove all other successors and keep folding into unconditional branch. - Some successor blocks that are the successor of multiple switch cases which are all removed. - Some successor blocks that are the successor of multiple switch cases, some (but not all) of which are removed. Ideally your test cases should test each of these, with other edges (not from the switch) going to the successors and (used) PHI nodes there. Since all of this may enlarge the code, you may want to factor it out into a static helper function. You could use SimplifyIndirectBrOnSelect() as an example, but note that that one has some different edge cases (for instance, the successors it tries to remove may not actually be present). Maybe you can even share some code between that and your SimplifySwitchOnSelect()? You could probably factor out all of the code SimplifyIndirectBrOnSelect() uses to update successors[1] to a separate helper function; the indirectbr-specific edge cases shouldn't be reachable for a switch so it won't generate incorrect code. [1]: which is everything after 'BasicBlock *FalseBB'. From fvbommel at gmail.com Mon Jan 10 04:29:11 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 10 Jan 2011 11:29:11 +0100 Subject: [llvm-commits] PATCH: Teach constant folding about SSE[2] conversion intrinsics In-Reply-To: References: Message-ID: On Mon, Jan 10, 2011 at 10:18 AM, Chandler Carruth wrote: > This resolves the majority of what I've been able to spot actually happening > due to my last README entry. I've been able to think of at least one more > really trivial fold that we could do: (cvtsd2si (sitofp x)) -> x. However, I > don't yet have any benchmark that shows this is useful. If anyone does want to implement that, remember to be careful with rounding if the full precision of the integer doesn't fit in the float. (i.e. it's not *completely* trivial) You could probably use APFloat to return a "rounded" x though. > One question, where is the best place to test this? I couldn't find a direct > test for ConstantFolding. test/Transforms/ConstProp/, either in call.ll or a new target-specific call-.ll file for target-specific intrinsics. From daniel at zuster.org Mon Jan 10 06:24:52 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 10 Jan 2011 12:24:52 -0000 Subject: [llvm-commits] [llvm] r123169 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110110122452.F04EE2A6C12C@llvm.org> Author: ddunbar Date: Mon Jan 10 06:24:52 2011 New Revision: 123169 URL: http://llvm.org/viewvc/llvm-project?rev=123169&view=rev Log: MC/ARM/AsmParser: Split out SplitMnemonicAndCC(). Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123169&r1=123168&r2=123169&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jan 10 06:24:52 2011 @@ -866,19 +866,20 @@ } } -/// Parse an arm instruction mnemonic followed by its operands. -bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, - SmallVectorImpl &Operands) { - // Create the leading tokens for the mnemonic, split by '.' characters. - size_t Start = 0, Next = Name.find('.'); - StringRef Head = Name.slice(Start, Next); +// FIXME: Would be nice to autogen this. +static unsigned SplitMnemonicAndCC(StringRef &Mnemonic) { + // Ignore some mnemonics we know aren't predicated forms. + if (Mnemonic == "movs" || + Mnemonic == "vmls" || + Mnemonic == "vnmls") + return ARMCC::AL; - // Determine the predicate, if any. + // Otherwise, determine the predicate. // // FIXME: We need a way to check whether a prefix supports predication, // otherwise we will end up with an ambiguity for instructions that happen to // end with a predicate name. - unsigned CC = StringSwitch(Head.substr(Head.size()-2)) + unsigned CC = StringSwitch(Mnemonic.substr(Mnemonic.size()-2)) .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) .Case("hs", ARMCC::HS) @@ -895,20 +896,31 @@ .Case("le", ARMCC::LE) .Case("al", ARMCC::AL) .Default(~0U); - - if (CC == ~0U || - (CC == ARMCC::LS && (Head == "vmls" || Head == "vnmls"))) { - CC = ARMCC::AL; - } else { - Head = Head.slice(0, Head.size() - 2); + if (CC != ~0U) { + Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); + return CC; } + return ARMCC::AL; +} + +/// Parse an arm instruction mnemonic followed by its operands. +bool ARMAsmParser::ParseInstruction(StringRef Name, SMLoc NameLoc, + SmallVectorImpl &Operands) { + // Create the leading tokens for the mnemonic, split by '.' characters. + size_t Start = 0, Next = Name.find('.'); + StringRef Head = Name.slice(Start, Next); + + // Determine the predicate, if any. + unsigned CC = SplitMnemonicAndCC(Head); + Operands.push_back(ARMOperand::CreateToken(Head, NameLoc)); - if (Head != "trap") - // FIXME: Should only add this operand for predicated instructions + // FIXME: Should only add this operand for predicated instructions + if (Head != "trap") { Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), NameLoc)); + } // Add the remaining tokens in the mnemonic. while (Next != StringRef::npos) { From asl at math.spbu.ru Mon Jan 10 06:39:04 2011 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 10 Jan 2011 12:39:04 -0000 Subject: [llvm-commits] [llvm] r123170 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/AsmPrinter/ lib/CodeGen/SelectionDAG/ lib/ExecutionEngine/JIT/ lib/MC/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ Message-ID: <20110110123906.CA85A2A6C12C@llvm.org> Author: asl Date: Mon Jan 10 06:39:04 2011 New Revision: 123170 URL: http://llvm.org/viewvc/llvm-project?rev=123170&view=rev Log: Rename TargetFrameInfo into TargetFrameLowering. Also, put couple of FIXMEs and fixes here and there. Added: llvm/trunk/include/llvm/Target/TargetFrameLowering.h - copied, changed from r123169, llvm/trunk/include/llvm/Target/TargetFrameInfo.h llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp llvm/trunk/lib/Target/ARM/ARMFrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/ARM/ARMFrameInfo.h llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.cpp llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.h llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.h llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.h llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.h llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.h llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/Mips/MipsFrameInfo.cpp llvm/trunk/lib/Target/Mips/MipsFrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/Mips/MipsFrameInfo.h llvm/trunk/lib/Target/PTX/PTXFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/PTX/PTXFrameInfo.cpp llvm/trunk/lib/Target/PTX/PTXFrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/PTX/PTXFrameInfo.h llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.h llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/Sparc/SparcFrameInfo.cpp llvm/trunk/lib/Target/Sparc/SparcFrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/Sparc/SparcFrameInfo.h llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.h llvm/trunk/lib/Target/TargetFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/TargetFrameInfo.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/X86/X86FrameInfo.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/X86/X86FrameInfo.h llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp - copied, changed from r123169, llvm/trunk/lib/Target/XCore/XCoreFrameInfo.cpp llvm/trunk/lib/Target/XCore/XCoreFrameLowering.h - copied, changed from r123169, llvm/trunk/lib/Target/XCore/XCoreFrameInfo.h Removed: llvm/trunk/include/llvm/Target/TargetFrameInfo.h llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp llvm/trunk/lib/Target/ARM/ARMFrameInfo.h llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.cpp llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.h llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.h llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.h llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.h llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.h llvm/trunk/lib/Target/Mips/MipsFrameInfo.cpp llvm/trunk/lib/Target/Mips/MipsFrameInfo.h llvm/trunk/lib/Target/PTX/PTXFrameInfo.cpp llvm/trunk/lib/Target/PTX/PTXFrameInfo.h llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.h llvm/trunk/lib/Target/Sparc/SparcFrameInfo.cpp llvm/trunk/lib/Target/Sparc/SparcFrameInfo.h llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.h llvm/trunk/lib/Target/TargetFrameInfo.cpp llvm/trunk/lib/Target/X86/X86FrameInfo.cpp llvm/trunk/lib/Target/X86/X86FrameInfo.h llvm/trunk/lib/Target/XCore/XCoreFrameInfo.cpp llvm/trunk/lib/Target/XCore/XCoreFrameInfo.h Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h llvm/trunk/include/llvm/Target/TargetAsmInfo.h llvm/trunk/include/llvm/Target/TargetMachine.h llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp llvm/trunk/lib/CodeGen/GCStrategy.cpp llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp llvm/trunk/lib/CodeGen/MachineFunction.cpp llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.h llvm/trunk/lib/MC/MCDwarf.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp llvm/trunk/lib/Target/ARM/ARMTargetMachine.h llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp llvm/trunk/lib/Target/Mips/MipsTargetMachine.h llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.h llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h llvm/trunk/lib/Target/TargetAsmInfo.cpp llvm/trunk/lib/Target/TargetRegisterInfo.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.td llvm/trunk/lib/Target/X86/X86TargetMachine.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.h llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h Mon Jan 10 06:39:04 2011 @@ -27,7 +27,7 @@ class Type; class MachineFunction; class MachineBasicBlock; -class TargetFrameInfo; +class TargetFrameLowering; class BitVector; /// The CalleeSavedInfo class tracks the information need to locate where a @@ -196,9 +196,9 @@ /// spill slots. SmallVector SpillObjects; - /// TargetFrameInfo - Target information about frame layout. + /// TargetFrameLowering - Target information about frame layout. /// - const TargetFrameInfo &TFI; + const TargetFrameLowering &TFI; /// LocalFrameObjects - References to frame indices which are mapped /// into the local frame allocation block. @@ -217,7 +217,7 @@ bool UseLocalStackAllocationBlock; public: - explicit MachineFrameInfo(const TargetFrameInfo &tfi) : TFI(tfi) { + explicit MachineFrameInfo(const TargetFrameLowering &tfi) : TFI(tfi) { StackSize = NumFixedObjects = OffsetAdjustment = MaxAlignment = 0; HasVarSizedObjects = false; FrameAddressTaken = false; Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Mon Jan 10 06:39:04 2011 @@ -16,7 +16,7 @@ #include "llvm/CodeGen/MachineLocation.h" #include "llvm/Target/TargetLoweringObjectFile.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetRegisterInfo.h" namespace llvm { @@ -28,7 +28,7 @@ class TargetAsmInfo { unsigned PointerSize; bool IsLittleEndian; - TargetFrameInfo::StackDirection StackDir; + TargetFrameLowering::StackDirection StackDir; const TargetRegisterInfo *TRI; std::vector InitialFrameState; const TargetLoweringObjectFile *TLOF; @@ -46,7 +46,7 @@ return IsLittleEndian; } - TargetFrameInfo::StackDirection getStackGrowthDirection() const { + TargetFrameLowering::StackDirection getStackGrowthDirection() const { return StackDir; } Removed: llvm/trunk/include/llvm/Target/TargetFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/include/llvm/Target/TargetFrameInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetFrameInfo.h (removed) @@ -1,196 +0,0 @@ -//===-- llvm/Target/TargetFrameInfo.h ---------------------------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Interface to describe the layout of a stack frame on the target machine. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TARGET_TARGETFRAMEINFO_H -#define LLVM_TARGET_TARGETFRAMEINFO_H - -#include "llvm/CodeGen/MachineBasicBlock.h" - -#include -#include - -namespace llvm { - class CalleeSavedInfo; - class MachineFunction; - class MachineBasicBlock; - class MachineMove; - class RegScavenger; - -/// Information about stack frame layout on the target. It holds the direction -/// of stack growth, the known stack alignment on entry to each function, and -/// the offset to the locals area. -/// -/// The offset to the local area is the offset from the stack pointer on -/// function entry to the first location where function data (local variables, -/// spill locations) can be stored. -class TargetFrameInfo { -public: - enum StackDirection { - StackGrowsUp, // Adding to the stack increases the stack address - StackGrowsDown // Adding to the stack decreases the stack address - }; - - // Maps a callee saved register to a stack slot with a fixed offset. - struct SpillSlot { - unsigned Reg; - int Offset; // Offset relative to stack pointer on function entry. - }; -private: - StackDirection StackDir; - unsigned StackAlignment; - unsigned TransientStackAlignment; - int LocalAreaOffset; -public: - TargetFrameInfo(StackDirection D, unsigned StackAl, int LAO, - unsigned TransAl = 1) - : StackDir(D), StackAlignment(StackAl), TransientStackAlignment(TransAl), - LocalAreaOffset(LAO) {} - - virtual ~TargetFrameInfo(); - - // These methods return information that describes the abstract stack layout - // of the target machine. - - /// getStackGrowthDirection - Return the direction the stack grows - /// - StackDirection getStackGrowthDirection() const { return StackDir; } - - /// getStackAlignment - This method returns the number of bytes to which the - /// stack pointer must be aligned on entry to a function. Typically, this - /// is the largest alignment for any data object in the target. - /// - unsigned getStackAlignment() const { return StackAlignment; } - - /// getTransientStackAlignment - This method returns the number of bytes to - /// which the stack pointer must be aligned at all times, even between - /// calls. - /// - unsigned getTransientStackAlignment() const { - return TransientStackAlignment; - } - - /// getOffsetOfLocalArea - This method returns the offset of the local area - /// from the stack pointer on entrance to a function. - /// - int getOffsetOfLocalArea() const { return LocalAreaOffset; } - - /// getCalleeSavedSpillSlots - This method returns a pointer to an array of - /// pairs, that contains an entry for each callee saved register that must be - /// spilled to a particular stack location if it is spilled. - /// - /// Each entry in this array contains a pair, indicating the - /// fixed offset from the incoming stack pointer that each register should be - /// spilled at. If a register is not listed here, the code generator is - /// allowed to spill it anywhere it chooses. - /// - virtual const SpillSlot * - getCalleeSavedSpillSlots(unsigned &NumEntries) const { - NumEntries = 0; - return 0; - } - - /// targetHandlesStackFrameRounding - Returns true if the target is - /// responsible for rounding up the stack frame (probably at emitPrologue - /// time). - virtual bool targetHandlesStackFrameRounding() const { - return false; - } - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - virtual void emitPrologue(MachineFunction &MF) const = 0; - virtual void emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const = 0; - - /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee - /// saved registers and returns true if it isn't possible / profitable to do - /// so by issuing a series of store instructions via - /// storeRegToStackSlot(). Returns false otherwise. - virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - return false; - } - - /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee - /// saved registers and returns true if it isn't possible / profitable to do - /// so by issuing a series of load instructions via loadRegToStackSlot(). - /// Returns false otherwise. - virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - return false; - } - - /// hasFP - Return true if the specified function should have a dedicated - /// frame pointer register. For most targets this is true only if the function - /// has variable sized allocas or if frame pointer elimination is disabled. - virtual bool hasFP(const MachineFunction &MF) const = 0; - - /// hasReservedCallFrame - Under normal circumstances, when a frame pointer is - /// not required, we reserve argument space for call sites in the function - /// immediately on entry to the current function. This eliminates the need for - /// add/sub sp brackets around call sites. Returns true if the call frame is - /// included as part of the stack frame. - virtual bool hasReservedCallFrame(const MachineFunction &MF) const { - return !hasFP(MF); - } - - /// canSimplifyCallFramePseudos - When possible, it's best to simplify the - /// call frame pseudo ops before doing frame index elimination. This is - /// possible only when frame index references between the pseudos won't - /// need adjusting for the call frame adjustments. Normally, that's true - /// if the function has a reserved call frame or a frame pointer. Some - /// targets (Thumb2, for example) may have more complicated criteria, - /// however, and can override this behavior. - virtual bool canSimplifyCallFramePseudos(const MachineFunction &MF) const { - return hasReservedCallFrame(MF) || hasFP(MF); - } - - /// getInitialFrameState - Returns a list of machine moves that are assumed - /// on entry to all functions. Note that LabelID is ignored (assumed to be - /// the beginning of the function.) - virtual void getInitialFrameState(std::vector &Moves) const; - - /// getFrameIndexOffset - Returns the displacement from the frame register to - /// the stack frame of the specified index. - virtual int getFrameIndexOffset(const MachineFunction &MF, int FI) const; - - /// getFrameIndexReference - This method should return the base register - /// and offset used to reference a frame index location. The offset is - /// returned directly, and the base register is returned via FrameReg. - virtual int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const; - - /// processFunctionBeforeCalleeSavedScan - This method is called immediately - /// before PrologEpilogInserter scans the physical registers used to determine - /// what callee saved registers should be spilled. This method is optional. - virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS = NULL) const { - - } - - /// processFunctionBeforeFrameFinalized - This method is called immediately - /// before the specified function's frame layout (MF.getFrameInfo()) is - /// finalized. Once the frame is finalized, MO_FrameIndex operands are - /// replaced with direct constants. This method is optional. - /// - virtual void processFunctionBeforeFrameFinalized(MachineFunction &MF) const { - } -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/include/llvm/Target/TargetFrameLowering.h (from r123169, llvm/trunk/include/llvm/Target/TargetFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetFrameLowering.h?p2=llvm/trunk/include/llvm/Target/TargetFrameLowering.h&p1=llvm/trunk/include/llvm/Target/TargetFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetFrameInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===-- llvm/Target/TargetFrameInfo.h ---------------------------*- C++ -*-===// +//===-- llvm/Target/TargetFrameLowering.h ---------------------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -11,8 +11,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_TARGETFRAMEINFO_H -#define LLVM_TARGET_TARGETFRAMEINFO_H +#ifndef LLVM_TARGET_TARGETFRAMELOWERING_H +#define LLVM_TARGET_TARGETFRAMELOWERING_H #include "llvm/CodeGen/MachineBasicBlock.h" @@ -33,7 +33,7 @@ /// The offset to the local area is the offset from the stack pointer on /// function entry to the first location where function data (local variables, /// spill locations) can be stored. -class TargetFrameInfo { +class TargetFrameLowering { public: enum StackDirection { StackGrowsUp, // Adding to the stack increases the stack address @@ -51,12 +51,12 @@ unsigned TransientStackAlignment; int LocalAreaOffset; public: - TargetFrameInfo(StackDirection D, unsigned StackAl, int LAO, - unsigned TransAl = 1) + TargetFrameLowering(StackDirection D, unsigned StackAl, int LAO, + unsigned TransAl = 1) : StackDir(D), StackAlignment(StackAl), TransientStackAlignment(TransAl), LocalAreaOffset(LAO) {} - virtual ~TargetFrameInfo(); + virtual ~TargetFrameLowering(); // These methods return information that describes the abstract stack layout // of the target machine. Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Mon Jan 10 06:39:04 2011 @@ -29,7 +29,7 @@ class TargetJITInfo; class TargetLowering; class TargetSelectionDAGInfo; -class TargetFrameInfo; +class TargetFrameLowering; class JITCodeEmitter; class MCContext; class TargetRegisterInfo; @@ -117,11 +117,11 @@ // -- Stack frame information // -- Selection DAG lowering information // - virtual const TargetInstrInfo *getInstrInfo() const { return 0; } - virtual const TargetFrameInfo *getFrameInfo() const { return 0; } + virtual const TargetInstrInfo *getInstrInfo() const { return 0; } + virtual const TargetFrameLowering *getFrameLowering() const { return 0; } virtual const TargetLowering *getTargetLowering() const { return 0; } virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const{ return 0; } - virtual const TargetData *getTargetData() const { return 0; } + virtual const TargetData *getTargetData() const { return 0; } /// getMCAsmInfo - Return target specific asm information. /// Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp Mon Jan 10 06:39:04 2011 @@ -19,7 +19,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" @@ -214,8 +214,8 @@ const TargetRegisterInfo *RI = TM.getRegisterInfo(); int stackGrowth = TM.getTargetData()->getPointerSize(); - if (TM.getFrameInfo()->getStackGrowthDirection() != - TargetFrameInfo::StackGrowsUp) + if (TM.getFrameLowering()->getStackGrowthDirection() != + TargetFrameLowering::StackGrowsUp) stackGrowth *= -1; for (unsigned i = 0, N = Moves.size(); i < N; ++i) { Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Mon Jan 10 06:39:04 2011 @@ -24,7 +24,7 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" @@ -594,7 +594,7 @@ void DwarfDebug::addVariableAddress(DbgVariable *&DV, DIE *Die, int64_t FI) { MachineLocation Location; unsigned FrameReg; - const TargetFrameInfo *TFI = Asm->TM.getFrameInfo(); + const TargetFrameLowering *TFI = Asm->TM.getFrameLowering(); int Offset = TFI->getFrameIndexReference(*Asm->MF, FI, FrameReg); Location.set(FrameReg, Offset); @@ -3294,8 +3294,8 @@ return; int stackGrowth = Asm->getTargetData().getPointerSize(); - if (Asm->TM.getFrameInfo()->getStackGrowthDirection() == - TargetFrameInfo::StackGrowsDown) + if (Asm->TM.getFrameLowering()->getStackGrowthDirection() == + TargetFrameLowering::StackGrowsDown) stackGrowth *= -1; // Start the dwarf frame section. @@ -3318,7 +3318,7 @@ Asm->EmitSLEB128(stackGrowth, "CIE Data Alignment Factor"); Asm->OutStreamer.AddComment("CIE RA Column"); const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo(); - const TargetFrameInfo *TFI = Asm->TM.getFrameInfo(); + const TargetFrameLowering *TFI = Asm->TM.getFrameLowering(); Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), false)); std::vector Moves; Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Mon Jan 10 06:39:04 2011 @@ -26,7 +26,7 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/Target/Mangler.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetLoweringObjectFile.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -50,8 +50,8 @@ void DwarfException::EmitCIE(const Function *PersonalityFn, unsigned Index) { // Size and sign of stack growth. int stackGrowth = Asm->getTargetData().getPointerSize(); - if (Asm->TM.getFrameInfo()->getStackGrowthDirection() == - TargetFrameInfo::StackGrowsDown) + if (Asm->TM.getFrameLowering()->getStackGrowthDirection() == + TargetFrameLowering::StackGrowsDown) stackGrowth *= -1; const TargetLoweringObjectFile &TLOF = Asm->getObjFileLowering(); @@ -127,7 +127,7 @@ Asm->OutStreamer.AddComment("CIE Return Address Column"); const TargetRegisterInfo *RI = Asm->TM.getRegisterInfo(); - const TargetFrameInfo *TFI = Asm->TM.getFrameInfo(); + const TargetFrameLowering *TFI = Asm->TM.getFrameLowering(); Asm->EmitInt8(RI->getDwarfRegNum(RI->getRARegister(), true)); if (Augmentation[0]) { Modified: llvm/trunk/lib/CodeGen/GCStrategy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GCStrategy.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/GCStrategy.cpp (original) +++ llvm/trunk/lib/CodeGen/GCStrategy.cpp Mon Jan 10 06:39:04 2011 @@ -24,7 +24,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" @@ -382,7 +382,7 @@ } void MachineCodeAnalysis::FindStackOffsets(MachineFunction &MF) { - const TargetFrameInfo *TFI = TM->getFrameInfo(); + const TargetFrameLowering *TFI = TM->getFrameLowering(); assert(TFI && "TargetRegisterInfo not available!"); for (GCFunctionInfo::roots_iterator RI = FI->roots_begin(), Modified: llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp (original) +++ llvm/trunk/lib/CodeGen/LocalStackSlotAllocation.cpp Mon Jan 10 06:39:04 2011 @@ -34,7 +34,7 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" using namespace llvm; @@ -152,9 +152,9 @@ void LocalStackSlotPass::calculateFrameObjectOffsets(MachineFunction &Fn) { // Loop over all of the stack objects, assigning sequential addresses... MachineFrameInfo *MFI = Fn.getFrameInfo(); - const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo(); + const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering(); bool StackGrowsDown = - TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown; + TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown; int64_t Offset = 0; unsigned MaxAlign = 0; @@ -227,9 +227,9 @@ MachineFrameInfo *MFI = Fn.getFrameInfo(); const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); - const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo(); + const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering(); bool StackGrowsDown = - TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown; + TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown; // Collect all of the instructions in the block that reference // a frame index. Also store the frame index referenced to ease later Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Mon Jan 10 06:39:04 2011 @@ -33,7 +33,7 @@ #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/ADT/SmallString.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/GraphWriter.h" @@ -60,7 +60,7 @@ else RegInfo = 0; MFInfo = 0; - FrameInfo = new (Allocator) MachineFrameInfo(*TM.getFrameInfo()); + FrameInfo = new (Allocator) MachineFrameInfo(*TM.getFrameLowering()); if (Fn->hasFnAttr(Attribute::StackAlignment)) FrameInfo->setMaxAlignment(Attribute::getStackAlignmentFromAttrs( Fn->getAttributes().getFnAttributes())); @@ -492,7 +492,7 @@ void MachineFrameInfo::print(const MachineFunction &MF, raw_ostream &OS) const{ if (Objects.empty()) return; - const TargetFrameInfo *FI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *FI = MF.getTarget().getFrameLowering(); int ValOffset = (FI ? FI->getOffsetOfLocalArea() : 0); OS << "Frame Objects:\n"; Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Mon Jan 10 06:39:04 2011 @@ -30,7 +30,7 @@ #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Compiler.h" @@ -66,7 +66,7 @@ bool PEI::runOnMachineFunction(MachineFunction &Fn) { const Function* F = Fn.getFunction(); const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); - const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering(); RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL; FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn); @@ -145,7 +145,7 @@ /// pseudo instructions. void PEI::calculateCallsInformation(MachineFunction &Fn) { const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); - const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering(); MachineFrameInfo *MFI = Fn.getFrameInfo(); unsigned MaxCallFrameSize = 0; @@ -199,7 +199,7 @@ /// registers. void PEI::calculateCalleeSavedRegisters(MachineFunction &Fn) { const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); - const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering(); MachineFrameInfo *MFI = Fn.getFrameInfo(); // Get the callee saved register list... @@ -238,7 +238,7 @@ return; // Early exit if no callee saved registers are modified! unsigned NumFixedSpillSlots; - const TargetFrameInfo::SpillSlot *FixedSpillSlots = + const TargetFrameLowering::SpillSlot *FixedSpillSlots = TFI->getCalleeSavedSpillSlots(NumFixedSpillSlots); // Now that we know which registers need to be saved and restored, allocate @@ -256,7 +256,7 @@ // Check to see if this physreg must be spilled to a particular stack slot // on this target. - const TargetFrameInfo::SpillSlot *FixedSlot = FixedSpillSlots; + const TargetFrameLowering::SpillSlot *FixedSlot = FixedSpillSlots; while (FixedSlot != FixedSpillSlots+NumFixedSpillSlots && FixedSlot->Reg != Reg) ++FixedSlot; @@ -299,7 +299,7 @@ return; const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); - const TargetFrameInfo *TFI = Fn.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering(); const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); MachineBasicBlock::iterator I; @@ -490,10 +490,10 @@ /// abstract stack objects. /// void PEI::calculateFrameObjectOffsets(MachineFunction &Fn) { - const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo(); + const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering(); bool StackGrowsDown = - TFI.getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown; + TFI.getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown; // Loop over all of the stack objects, assigning sequential addresses... MachineFrameInfo *MFI = Fn.getFrameInfo(); @@ -682,7 +682,7 @@ /// prolog and epilog code to the function. /// void PEI::insertPrologEpilogCode(MachineFunction &Fn) { - const TargetFrameInfo &TFI = *Fn.getTarget().getFrameInfo(); + const TargetFrameLowering &TFI = *Fn.getTarget().getFrameLowering(); // Add prologue to the function... TFI.emitPrologue(Fn); @@ -704,9 +704,9 @@ const TargetMachine &TM = Fn.getTarget(); assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!"); const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); bool StackGrowsDown = - TFI->getStackGrowthDirection() == TargetFrameInfo::StackGrowsDown; + TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown; int FrameSetupOpcode = TRI.getCallFrameSetupOpcode(); int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Mon Jan 10 06:39:04 2011 @@ -25,7 +25,6 @@ #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp Mon Jan 10 06:39:04 2011 @@ -29,7 +29,6 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetOptions.h" Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jan 10 06:39:04 2011 @@ -19,7 +19,7 @@ #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/SelectionDAG.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" @@ -1719,7 +1719,7 @@ SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); Chain = SP.getValue(1); unsigned Align = cast(Tmp3)->getZExtValue(); - unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); + unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); if (Align > StackAlign) SP = DAG.getNode(ISD::AND, dl, VT, SP, DAG.getConstant(-(uint64_t)Align, VT)); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Jan 10 06:39:04 2011 @@ -31,7 +31,6 @@ #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetSelectionDAGInfo.h" #include "llvm/Target/TargetOptions.h" Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Jan 10 06:39:04 2011 @@ -45,7 +45,7 @@ #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Analysis/DebugInfo.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetIntrinsicInfo.h" #include "llvm/Target/TargetLowering.h" @@ -2974,7 +2974,7 @@ // Handle alignment. If the requested alignment is less than or equal to // the stack alignment, ignore it. If the size is greater than or equal to // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. - unsigned StackAlign = TM.getFrameInfo()->getStackAlignment(); + unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); if (Align <= StackAlign) Align = 0; Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.cpp Mon Jan 10 06:39:04 2011 @@ -26,7 +26,7 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" using namespace llvm; @@ -43,9 +43,9 @@ const TargetMachine& TM = F.getTarget(); TD = TM.getTargetData(); - stackGrowthDirection = TM.getFrameInfo()->getStackGrowthDirection(); + stackGrowthDirection = TM.getFrameLowering()->getStackGrowthDirection(); RI = TM.getRegisterInfo(); - TFI = TM.getFrameInfo(); + TFI = TM.getFrameLowering(); JCE = &jce; unsigned char* ExceptionTable = EmitExceptionTable(&F, StartFunction, @@ -67,7 +67,7 @@ JITDwarfEmitter::EmitFrameMoves(intptr_t BaseLabelPtr, const std::vector &Moves) const { unsigned PointerSize = TD->getPointerSize(); - int stackGrowth = stackGrowthDirection == TargetFrameInfo::StackGrowsUp ? + int stackGrowth = stackGrowthDirection == TargetFrameLowering::StackGrowsUp ? PointerSize : -PointerSize; MCSymbol *BaseLabel = 0; @@ -482,7 +482,7 @@ unsigned char* JITDwarfEmitter::EmitCommonEHFrame(const Function* Personality) const { unsigned PointerSize = TD->getPointerSize(); - int stackGrowth = stackGrowthDirection == TargetFrameInfo::StackGrowsUp ? + int stackGrowth = stackGrowthDirection == TargetFrameLowering::StackGrowsUp ? PointerSize : -PointerSize; unsigned char* StartCommonPtr = (unsigned char*)JCE->getCurrentPCValue(); Modified: llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.h (original) +++ llvm/trunk/lib/ExecutionEngine/JIT/JITDwarfEmitter.h Mon Jan 10 06:39:04 2011 @@ -23,7 +23,7 @@ class MachineModuleInfo; class MachineMove; class TargetData; -class TargetFrameInfo; +class TargetFrameLowering; class TargetMachine; class TargetRegisterInfo; @@ -31,7 +31,7 @@ const TargetData* TD; JITCodeEmitter* JCE; const TargetRegisterInfo* RI; - const TargetFrameInfo *TFI; + const TargetFrameLowering *TFI; MachineModuleInfo* MMI; JIT& Jit; bool stackGrowthDirection; Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Mon Jan 10 06:39:04 2011 @@ -433,7 +433,7 @@ MCContext &context = streamer.getContext(); const TargetAsmInfo &asmInfo = context.getTargetAsmInfo(); int size = asmInfo.getPointerSize(); - if (asmInfo.getStackGrowthDirection() == TargetFrameInfo::StackGrowsUp) + if (asmInfo.getStackGrowthDirection() == TargetFrameLowering::StackGrowsUp) return size; else return -size; Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -15,7 +15,7 @@ #include "ARMAddressingModes.h" #include "ARMBaseInstrInfo.h" #include "ARMBaseRegisterInfo.h" -#include "ARMFrameInfo.h" +#include "ARMFrameLowering.h" #include "ARMInstrInfo.h" #include "ARMMachineFunctionInfo.h" #include "ARMSubtarget.h" @@ -33,7 +33,7 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" @@ -86,7 +86,7 @@ BitVector ARMBaseRegisterInfo:: getReservedRegs(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); // FIXME: avoid re-calculating this everytime. BitVector Reserved(getNumRegs()); @@ -105,7 +105,7 @@ bool ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); switch (Reg) { default: break; @@ -354,7 +354,7 @@ ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC, unsigned HintType, unsigned HintReg, const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); // Alternative register allocation orders when favoring even / odd registers // of register pairs. @@ -575,7 +575,7 @@ needsStackRealignment(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *F = MF.getFunction(); - unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned StackAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); bool requiresRealignment = ((MFI->getLocalFrameMaxAlign() > StackAlign) || F->hasFnAttr(Attribute::StackAlignment)); @@ -597,7 +597,7 @@ unsigned ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (TFI->hasFP(MF)) return FramePtr; @@ -852,7 +852,7 @@ void ARMBaseRegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (!TFI->hasReservedCallFrame(MF)) { // If we have alloca, convert as follows: // ADJCALLSTACKDOWN -> sub, sp, sp, amount @@ -864,7 +864,7 @@ // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next // alignment boundary. - unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned Align = TFI->getStackAlignment(); Amount = (Amount+Align-1)/Align*Align; ARMFunctionInfo *AFI = MF.getInfo(); @@ -984,7 +984,7 @@ // Note that the incoming offset is based on the SP value at function entry, // so it'll be negative. MachineFunction &MF = *MI->getParent()->getParent(); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); MachineFrameInfo *MFI = MF.getFrameInfo(); ARMFunctionInfo *AFI = MF.getInfo(); @@ -1011,7 +1011,7 @@ // The FP is only available if there is no dynamic realignment. We // don't know for sure yet whether we'll need that, so we guess based // on whether there are any local variables that would trigger it. - unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned StackAlign = TFI->getStackAlignment(); if (TFI->hasFP(MF) && !((MFI->getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) { if (isFrameOffsetLegal(MI, FPOffset)) @@ -1155,8 +1155,8 @@ MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const ARMFrameInfo *TFI = - static_cast(MF.getTarget().getFrameInfo()); + const ARMFrameLowering *TFI = + static_cast(MF.getTarget().getFrameLowering()); ARMFunctionInfo *AFI = MF.getInfo(); assert(!AFI->isThumb1OnlyFunction() && "This eliminateFrameIndex does not support Thumb1!"); Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Mon Jan 10 06:39:04 2011 @@ -24,7 +24,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove! using namespace llvm; @@ -639,7 +639,7 @@ ARMFunctionInfo *AFI = MF.getInfo(); int32_t NumBytes = AFI->getFramePtrSpillOffset(); unsigned FramePtr = RI.getFrameRegister(MF); - assert(MF.getTarget().getFrameInfo()->hasFP(MF) && + assert(MF.getTarget().getFrameLowering()->hasFP(MF) && "base pointer without frame pointer?"); if (AFI->isThumb2Function()) { Removed: llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp (removed) @@ -1,1012 +0,0 @@ -//=======- ARMFrameInfo.cpp - ARM Frame Information ------------*- C++ -*-====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the ARM implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#include "ARMFrameInfo.h" -#include "ARMAddressingModes.h" -#include "ARMBaseInstrInfo.h" -#include "ARMMachineFunctionInfo.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/RegisterScavenging.h" -#include "llvm/Target/TargetOptions.h" - -using namespace llvm; - -/// hasFP - Return true if the specified function should have a dedicated frame -/// pointer register. This is true if the function has variable sized allocas -/// or if frame pointer elimination is disabled. -/// -bool ARMFrameInfo::hasFP(const MachineFunction &MF) const { - const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); - - // Mac OS X requires FP not to be clobbered for backtracing purpose. - if (STI.isTargetDarwin()) - return true; - - const MachineFrameInfo *MFI = MF.getFrameInfo(); - // Always eliminate non-leaf frame pointers. - return ((DisableFramePointerElim(MF) && MFI->hasCalls()) || - RegInfo->needsStackRealignment(MF) || - MFI->hasVarSizedObjects() || - MFI->isFrameAddressTaken()); -} - -// hasReservedCallFrame - Under normal circumstances, when a frame pointer is -// not required, we reserve argument space for call sites in the function -// immediately on entry to the current function. This eliminates the need for -// add/sub sp brackets around call sites. Returns true if the call frame is -// included as part of the stack frame. -bool ARMFrameInfo::hasReservedCallFrame(const MachineFunction &MF) const { - const MachineFrameInfo *FFI = MF.getFrameInfo(); - unsigned CFSize = FFI->getMaxCallFrameSize(); - // It's not always a good idea to include the call frame as part of the - // stack frame. ARM (especially Thumb) has small immediate offset to - // address the stack frame. So a large call frame can cause poor codegen - // and may even makes it impossible to scavenge a register. - if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12 - return false; - - return !MF.getFrameInfo()->hasVarSizedObjects(); -} - -// canSimplifyCallFramePseudos - If there is a reserved call frame, the -// call frame pseudos can be simplified. Unlike most targets, having a FP -// is not sufficient here since we still may reference some objects via SP -// even when FP is available in Thumb2 mode. -bool ARMFrameInfo::canSimplifyCallFramePseudos(const MachineFunction &MF)const { - return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); -} - -static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { - for (unsigned i = 0; CSRegs[i]; ++i) - if (Reg == CSRegs[i]) - return true; - return false; -} - -static bool isCSRestore(MachineInstr *MI, - const ARMBaseInstrInfo &TII, - const unsigned *CSRegs) { - // Integer spill area is handled with "pop". - if (MI->getOpcode() == ARM::LDMIA_RET || - MI->getOpcode() == ARM::t2LDMIA_RET || - MI->getOpcode() == ARM::LDMIA_UPD || - MI->getOpcode() == ARM::t2LDMIA_UPD || - MI->getOpcode() == ARM::VLDMDIA_UPD) { - // The first two operands are predicates. The last two are - // imp-def and imp-use of SP. Check everything in between. - for (int i = 5, e = MI->getNumOperands(); i != e; ++i) - if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) - return false; - return true; - } - if ((MI->getOpcode() == ARM::LDR_POST || - MI->getOpcode() == ARM::t2LDR_POST) && - isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs) && - MI->getOperand(1).getReg() == ARM::SP) - return true; - - return false; -} - -static void -emitSPUpdate(bool isARM, - MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - DebugLoc dl, const ARMBaseInstrInfo &TII, - int NumBytes, - ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { - if (isARM) - emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, - Pred, PredReg, TII); - else - emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::SP, ARM::SP, NumBytes, - Pred, PredReg, TII); -} - -void ARMFrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); - MachineBasicBlock::iterator MBBI = MBB.begin(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - ARMFunctionInfo *AFI = MF.getInfo(); - const ARMBaseRegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); - const ARMBaseInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - assert(!AFI->isThumb1OnlyFunction() && - "This emitPrologue does not support Thumb1!"); - bool isARM = !AFI->isThumbFunction(); - unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); - unsigned NumBytes = MFI->getStackSize(); - const std::vector &CSI = MFI->getCalleeSavedInfo(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - unsigned FramePtr = RegInfo->getFrameRegister(MF); - - // Determine the sizes of each callee-save spill areas and record which frame - // belongs to which callee-save spill areas. - unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; - int FramePtrSpillFI = 0; - - // Allocate the vararg register save area. This is not counted in NumBytes. - if (VARegSaveSize) - emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize); - - if (!AFI->hasStackFrame()) { - if (NumBytes != 0) - emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); - return; - } - - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - int FI = CSI[i].getFrameIdx(); - switch (Reg) { - case ARM::R4: - case ARM::R5: - case ARM::R6: - case ARM::R7: - case ARM::LR: - if (Reg == FramePtr) - FramePtrSpillFI = FI; - AFI->addGPRCalleeSavedArea1Frame(FI); - GPRCS1Size += 4; - break; - case ARM::R8: - case ARM::R9: - case ARM::R10: - case ARM::R11: - if (Reg == FramePtr) - FramePtrSpillFI = FI; - if (STI.isTargetDarwin()) { - AFI->addGPRCalleeSavedArea2Frame(FI); - GPRCS2Size += 4; - } else { - AFI->addGPRCalleeSavedArea1Frame(FI); - GPRCS1Size += 4; - } - break; - default: - AFI->addDPRCalleeSavedAreaFrame(FI); - DPRCSSize += 8; - } - } - - // Move past area 1. - if (GPRCS1Size > 0) MBBI++; - - // Set FP to point to the stack slot that contains the previous FP. - // For Darwin, FP is R7, which has now been stored in spill area 1. - // Otherwise, if this is not Darwin, all the callee-saved registers go - // into spill area 1, including the FP in R11. In either case, it is - // now safe to emit this assignment. - bool HasFP = hasFP(MF); - if (HasFP) { - unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri : ARM::t2ADDri; - MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, dl, TII.get(ADDriOpc), FramePtr) - .addFrameIndex(FramePtrSpillFI).addImm(0); - AddDefaultCC(AddDefaultPred(MIB)); - } - - // Move past area 2. - if (GPRCS2Size > 0) MBBI++; - - // Determine starting offsets of spill areas. - unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); - unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; - unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; - if (HasFP) - AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + - NumBytes); - AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); - AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); - AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); - - // Move past area 3. - if (DPRCSSize > 0) MBBI++; - - NumBytes = DPRCSOffset; - if (NumBytes) { - // Adjust SP after all the callee-save spills. - emitSPUpdate(isARM, MBB, MBBI, dl, TII, -NumBytes); - if (HasFP && isARM) - // Restore from fp only in ARM mode: e.g. sub sp, r7, #24 - // Note it's not safe to do this in Thumb2 mode because it would have - // taken two instructions: - // mov sp, r7 - // sub sp, #24 - // If an interrupt is taken between the two instructions, then sp is in - // an inconsistent state (pointing to the middle of callee-saved area). - // The interrupt handler can end up clobbering the registers. - AFI->setShouldRestoreSPFromFP(true); - } - - if (STI.isTargetELF() && hasFP(MF)) - MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - - AFI->getFramePtrSpillOffset()); - - AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); - AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); - AFI->setDPRCalleeSavedAreaSize(DPRCSSize); - - // If we need dynamic stack realignment, do it here. Be paranoid and make - // sure if we also have VLAs, we have a base pointer for frame access. - if (RegInfo->needsStackRealignment(MF)) { - unsigned MaxAlign = MFI->getMaxAlignment(); - assert (!AFI->isThumb1OnlyFunction()); - if (!AFI->isThumbFunction()) { - // Emit bic sp, sp, MaxAlign - AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, - TII.get(ARM::BICri), ARM::SP) - .addReg(ARM::SP, RegState::Kill) - .addImm(MaxAlign-1))); - } else { - // We cannot use sp as source/dest register here, thus we're emitting the - // following sequence: - // mov r4, sp - // bic r4, r4, MaxAlign - // mov sp, r4 - // FIXME: It will be better just to find spare register here. - BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4) - .addReg(ARM::SP, RegState::Kill); - AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl, - TII.get(ARM::t2BICri), ARM::R4) - .addReg(ARM::R4, RegState::Kill) - .addImm(MaxAlign-1))); - BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP) - .addReg(ARM::R4, RegState::Kill); - } - - AFI->setShouldRestoreSPFromFP(true); - } - - // If we need a base pointer, set it up here. It's whatever the value - // of the stack pointer is at this point. Any variable size objects - // will be allocated after this, so we can still use the base pointer - // to reference locals. - if (RegInfo->hasBasePointer(MF)) { - if (isARM) - BuildMI(MBB, MBBI, dl, - TII.get(ARM::MOVr), RegInfo->getBaseRegister()) - .addReg(ARM::SP) - .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); - else - BuildMI(MBB, MBBI, dl, - TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister()) - .addReg(ARM::SP); - } - - // If the frame has variable sized objects then the epilogue must restore - // the sp from fp. - if (MFI->hasVarSizedObjects()) - AFI->setShouldRestoreSPFromFP(true); -} - -void ARMFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - assert(MBBI->getDesc().isReturn() && - "Can only insert epilog into returning blocks"); - unsigned RetOpcode = MBBI->getOpcode(); - DebugLoc dl = MBBI->getDebugLoc(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - ARMFunctionInfo *AFI = MF.getInfo(); - const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); - const ARMBaseInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - assert(!AFI->isThumb1OnlyFunction() && - "This emitEpilogue does not support Thumb1!"); - bool isARM = !AFI->isThumbFunction(); - - unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); - int NumBytes = (int)MFI->getStackSize(); - unsigned FramePtr = RegInfo->getFrameRegister(MF); - - if (!AFI->hasStackFrame()) { - if (NumBytes != 0) - emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); - } else { - // Unwind MBBI to point to first LDR / VLDRD. - const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(); - if (MBBI != MBB.begin()) { - do - --MBBI; - while (MBBI != MBB.begin() && isCSRestore(MBBI, TII, CSRegs)); - if (!isCSRestore(MBBI, TII, CSRegs)) - ++MBBI; - } - - // Move SP to start of FP callee save spill area. - NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + - AFI->getGPRCalleeSavedArea2Size() + - AFI->getDPRCalleeSavedAreaSize()); - - // Reset SP based on frame pointer only if the stack frame extends beyond - // frame pointer stack slot or target is ELF and the function has FP. - if (AFI->shouldRestoreSPFromFP()) { - NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; - if (NumBytes) { - if (isARM) - emitARMRegPlusImmediate(MBB, MBBI, dl, ARM::SP, FramePtr, -NumBytes, - ARMCC::AL, 0, TII); - else { - // It's not possible to restore SP from FP in a single instruction. - // For Darwin, this looks like: - // mov sp, r7 - // sub sp, #24 - // This is bad, if an interrupt is taken after the mov, sp is in an - // inconsistent state. - // Use the first callee-saved register as a scratch register. - assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && - "No scratch register to restore SP from FP!"); - emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes, - ARMCC::AL, 0, TII); - BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) - .addReg(ARM::R4); - } - } else { - // Thumb2 or ARM. - if (isARM) - BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP) - .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0); - else - BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP) - .addReg(FramePtr); - } - } else if (NumBytes) - emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes); - - // Increment past our save areas. - if (AFI->getDPRCalleeSavedAreaSize()) MBBI++; - if (AFI->getGPRCalleeSavedArea2Size()) MBBI++; - if (AFI->getGPRCalleeSavedArea1Size()) MBBI++; - } - - if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || - RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) { - // Tail call return: adjust the stack pointer and jump to callee. - MBBI = prior(MBB.end()); - MachineOperand &JumpTarget = MBBI->getOperand(0); - - // Jump to label or value in register. - if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND) { - unsigned TCOpcode = (RetOpcode == ARM::TCRETURNdi) - ? (STI.isThumb() ? ARM::TAILJMPdt : ARM::TAILJMPd) - : (STI.isThumb() ? ARM::TAILJMPdNDt : ARM::TAILJMPdND); - MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); - if (JumpTarget.isGlobal()) - MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), - JumpTarget.getTargetFlags()); - else { - assert(JumpTarget.isSymbol()); - MIB.addExternalSymbol(JumpTarget.getSymbolName(), - JumpTarget.getTargetFlags()); - } - } else if (RetOpcode == ARM::TCRETURNri) { - BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPr)). - addReg(JumpTarget.getReg(), RegState::Kill); - } else if (RetOpcode == ARM::TCRETURNriND) { - BuildMI(MBB, MBBI, dl, TII.get(ARM::TAILJMPrND)). - addReg(JumpTarget.getReg(), RegState::Kill); - } - - MachineInstr *NewMI = prior(MBBI); - for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i) - NewMI->addOperand(MBBI->getOperand(i)); - - // Delete the pseudo instruction TCRETURN. - MBB.erase(MBBI); - } - - if (VARegSaveSize) - emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); -} - -// Provide a base+offset reference to an FI slot for debug info. It's the -// same as what we use for resolving the code-gen references for now. -// FIXME: This can go wrong when references are SP-relative and simple call -// frames aren't used. -int -ARMFrameInfo::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { - return ResolveFrameIndexReference(MF, FI, FrameReg, 0); -} - -int -ARMFrameInfo::ResolveFrameIndexReference(const MachineFunction &MF, - int FI, - unsigned &FrameReg, - int SPAdj) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - const ARMBaseRegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); - const ARMFunctionInfo *AFI = MF.getInfo(); - int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); - int FPOffset = Offset - AFI->getFramePtrSpillOffset(); - bool isFixed = MFI->isFixedObjectIndex(FI); - - FrameReg = ARM::SP; - Offset += SPAdj; - if (AFI->isGPRCalleeSavedArea1Frame(FI)) - return Offset - AFI->getGPRCalleeSavedArea1Offset(); - else if (AFI->isGPRCalleeSavedArea2Frame(FI)) - return Offset - AFI->getGPRCalleeSavedArea2Offset(); - else if (AFI->isDPRCalleeSavedAreaFrame(FI)) - return Offset - AFI->getDPRCalleeSavedAreaOffset(); - - // When dynamically realigning the stack, use the frame pointer for - // parameters, and the stack/base pointer for locals. - if (RegInfo->needsStackRealignment(MF)) { - assert (hasFP(MF) && "dynamic stack realignment without a FP!"); - if (isFixed) { - FrameReg = RegInfo->getFrameRegister(MF); - Offset = FPOffset; - } else if (MFI->hasVarSizedObjects()) { - assert(RegInfo->hasBasePointer(MF) && - "VLAs and dynamic stack alignment, but missing base pointer!"); - FrameReg = RegInfo->getBaseRegister(); - } - return Offset; - } - - // If there is a frame pointer, use it when we can. - if (hasFP(MF) && AFI->hasStackFrame()) { - // Use frame pointer to reference fixed objects. Use it for locals if - // there are VLAs (and thus the SP isn't reliable as a base). - if (isFixed || (MFI->hasVarSizedObjects() && - !RegInfo->hasBasePointer(MF))) { - FrameReg = RegInfo->getFrameRegister(MF); - return FPOffset; - } else if (MFI->hasVarSizedObjects()) { - assert(RegInfo->hasBasePointer(MF) && "missing base pointer!"); - // Try to use the frame pointer if we can, else use the base pointer - // since it's available. This is handy for the emergency spill slot, in - // particular. - if (AFI->isThumb2Function()) { - if (FPOffset >= -255 && FPOffset < 0) { - FrameReg = RegInfo->getFrameRegister(MF); - return FPOffset; - } - } else - FrameReg = RegInfo->getBaseRegister(); - } else if (AFI->isThumb2Function()) { - // In Thumb2 mode, the negative offset is very limited. Try to avoid - // out of range references. - if (FPOffset >= -255 && FPOffset < 0) { - FrameReg = RegInfo->getFrameRegister(MF); - return FPOffset; - } - } else if (Offset > (FPOffset < 0 ? -FPOffset : FPOffset)) { - // Otherwise, use SP or FP, whichever is closer to the stack slot. - FrameReg = RegInfo->getFrameRegister(MF); - return FPOffset; - } - } - // Use the base pointer if we have one. - if (RegInfo->hasBasePointer(MF)) - FrameReg = RegInfo->getBaseRegister(); - return Offset; -} - -int ARMFrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const { - unsigned FrameReg; - return getFrameIndexReference(MF, FI, FrameReg); -} - -void ARMFrameInfo::emitPushInst(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - unsigned StmOpc, unsigned StrOpc, bool NoGap, - bool(*Func)(unsigned, bool)) const { - MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - - DebugLoc DL; - if (MI != MBB.end()) DL = MI->getDebugLoc(); - - SmallVector, 4> Regs; - unsigned i = CSI.size(); - while (i != 0) { - unsigned LastReg = 0; - for (; i != 0; --i) { - unsigned Reg = CSI[i-1].getReg(); - if (!(Func)(Reg, STI.isTargetDarwin())) continue; - - // Add the callee-saved register as live-in unless it's LR and - // @llvm.returnaddress is called. If LR is returned for - // @llvm.returnaddress then it's already added to the function and - // entry block live-in sets. - bool isKill = true; - if (Reg == ARM::LR) { - if (MF.getFrameInfo()->isReturnAddressTaken() && - MF.getRegInfo().isLiveIn(Reg)) - isKill = false; - } - - if (isKill) - MBB.addLiveIn(Reg); - - // If NoGap is true, push consecutive registers and then leave the rest - // for other instructions. e.g. - // vpush {d8, d10, d11} -> vpush {d8}, vpush {d10, d11} - if (NoGap && LastReg && LastReg != Reg-1) - break; - LastReg = Reg; - Regs.push_back(std::make_pair(Reg, isKill)); - } - - if (Regs.empty()) - continue; - if (Regs.size() > 1 || StrOpc== 0) { - MachineInstrBuilder MIB = - AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP) - .addReg(ARM::SP)); - for (unsigned i = 0, e = Regs.size(); i < e; ++i) - MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second)); - } else if (Regs.size() == 1) { - MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), - ARM::SP) - .addReg(Regs[0].first, getKillRegState(Regs[0].second)) - .addReg(ARM::SP); - // ARM mode needs an extra reg0 here due to addrmode2. Will go away once - // that refactoring is complete (eventually). - if (StrOpc == ARM::STR_PRE) { - MIB.addReg(0); - MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::sub, 4, ARM_AM::no_shift)); - } else - MIB.addImm(-4); - AddDefaultPred(MIB); - } - Regs.clear(); - } -} - -void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - unsigned LdmOpc, unsigned LdrOpc, - bool isVarArg, bool NoGap, - bool(*Func)(unsigned, bool)) const { - MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - ARMFunctionInfo *AFI = MF.getInfo(); - DebugLoc DL = MI->getDebugLoc(); - - SmallVector Regs; - unsigned i = CSI.size(); - while (i != 0) { - unsigned LastReg = 0; - bool DeleteRet = false; - for (; i != 0; --i) { - unsigned Reg = CSI[i-1].getReg(); - if (!(Func)(Reg, STI.isTargetDarwin())) continue; - - if (Reg == ARM::LR && !isVarArg && STI.hasV5TOps()) { - Reg = ARM::PC; - LdmOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_RET : ARM::LDMIA_RET; - // Fold the return instruction into the LDM. - DeleteRet = true; - } - - // If NoGap is true, pop consecutive registers and then leave the rest - // for other instructions. e.g. - // vpop {d8, d10, d11} -> vpop {d8}, vpop {d10, d11} - if (NoGap && LastReg && LastReg != Reg-1) - break; - - LastReg = Reg; - Regs.push_back(Reg); - } - - if (Regs.empty()) - continue; - if (Regs.size() > 1 || LdrOpc == 0) { - MachineInstrBuilder MIB = - AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP) - .addReg(ARM::SP)); - for (unsigned i = 0, e = Regs.size(); i < e; ++i) - MIB.addReg(Regs[i], getDefRegState(true)); - if (DeleteRet) - MI->eraseFromParent(); - MI = MIB; - } else if (Regs.size() == 1) { - // If we adjusted the reg to PC from LR above, switch it back here. We - // only do that for LDM. - if (Regs[0] == ARM::PC) - Regs[0] = ARM::LR; - MachineInstrBuilder MIB = - BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0]) - .addReg(ARM::SP, RegState::Define) - .addReg(ARM::SP); - // ARM mode needs an extra reg0 here due to addrmode2. Will go away once - // that refactoring is complete (eventually). - if (LdrOpc == ARM::LDR_POST) { - MIB.addReg(0); - MIB.addImm(ARM_AM::getAM2Opc(ARM_AM::add, 4, ARM_AM::no_shift)); - } else - MIB.addImm(4); - AddDefaultPred(MIB); - } - Regs.clear(); - } -} - -bool ARMFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - MachineFunction &MF = *MBB.getParent(); - ARMFunctionInfo *AFI = MF.getInfo(); - DebugLoc DL = MI->getDebugLoc(); - - unsigned PushOpc = AFI->isThumbFunction() ? ARM::t2STMDB_UPD : ARM::STMDB_UPD; - unsigned PushOneOpc = AFI->isThumbFunction() ? ARM::t2STR_PRE : ARM::STR_PRE; - unsigned FltOpc = ARM::VSTMDDB_UPD; - emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea1Register); - emitPushInst(MBB, MI, CSI, PushOpc, PushOneOpc, false, &isARMArea2Register); - emitPushInst(MBB, MI, CSI, FltOpc, 0, true, &isARMArea3Register); - - return true; -} - -bool ARMFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - MachineFunction &MF = *MBB.getParent(); - ARMFunctionInfo *AFI = MF.getInfo(); - bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; - DebugLoc DL = MI->getDebugLoc(); - - unsigned PopOpc = AFI->isThumbFunction() ? ARM::t2LDMIA_UPD : ARM::LDMIA_UPD; - unsigned LdrOpc = AFI->isThumbFunction() ? ARM::t2LDR_POST : ARM::LDR_POST; - unsigned FltOpc = ARM::VLDMDIA_UPD; - emitPopInst(MBB, MI, CSI, FltOpc, 0, isVarArg, true, &isARMArea3Register); - emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, - &isARMArea2Register); - emitPopInst(MBB, MI, CSI, PopOpc, LdrOpc, isVarArg, false, - &isARMArea1Register); - - return true; -} - -// FIXME: Make generic? -static unsigned GetFunctionSizeInBytes(const MachineFunction &MF, - const ARMBaseInstrInfo &TII) { - unsigned FnSize = 0; - for (MachineFunction::const_iterator MBBI = MF.begin(), E = MF.end(); - MBBI != E; ++MBBI) { - const MachineBasicBlock &MBB = *MBBI; - for (MachineBasicBlock::const_iterator I = MBB.begin(),E = MBB.end(); - I != E; ++I) - FnSize += TII.GetInstSizeInBytes(I); - } - return FnSize; -} - -/// estimateStackSize - Estimate and return the size of the frame. -/// FIXME: Make generic? -static unsigned estimateStackSize(MachineFunction &MF) { - const MachineFrameInfo *FFI = MF.getFrameInfo(); - int Offset = 0; - for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) { - int FixedOff = -FFI->getObjectOffset(i); - if (FixedOff > Offset) Offset = FixedOff; - } - for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) { - if (FFI->isDeadObjectIndex(i)) - continue; - Offset += FFI->getObjectSize(i); - unsigned Align = FFI->getObjectAlignment(i); - // Adjust to alignment boundary - Offset = (Offset+Align-1)/Align*Align; - } - return (unsigned)Offset; -} - -/// estimateRSStackSizeLimit - Look at each instruction that references stack -/// frames and return the stack size limit beyond which some of these -/// instructions will require a scratch register during their expansion later. -// FIXME: Move to TII? -static unsigned estimateRSStackSizeLimit(MachineFunction &MF, - const TargetFrameInfo *TFI) { - const ARMFunctionInfo *AFI = MF.getInfo(); - unsigned Limit = (1 << 12) - 1; - for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { - for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); - I != E; ++I) { - for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i) { - if (!I->getOperand(i).isFI()) continue; - - // When using ADDri to get the address of a stack object, 255 is the - // largest offset guaranteed to fit in the immediate offset. - if (I->getOpcode() == ARM::ADDri) { - Limit = std::min(Limit, (1U << 8) - 1); - break; - } - - // Otherwise check the addressing mode. - switch (I->getDesc().TSFlags & ARMII::AddrModeMask) { - case ARMII::AddrMode3: - case ARMII::AddrModeT2_i8: - Limit = std::min(Limit, (1U << 8) - 1); - break; - case ARMII::AddrMode5: - case ARMII::AddrModeT2_i8s4: - Limit = std::min(Limit, ((1U << 8) - 1) * 4); - break; - case ARMII::AddrModeT2_i12: - // i12 supports only positive offset so these will be converted to - // i8 opcodes. See llvm::rewriteT2FrameIndex. - if (TFI->hasFP(MF) && AFI->hasStackFrame()) - Limit = std::min(Limit, (1U << 8) - 1); - break; - case ARMII::AddrMode4: - case ARMII::AddrMode6: - // Addressing modes 4 & 6 (load/store) instructions can't encode an - // immediate offset for stack references. - return 0; - default: - break; - } - break; // At most one FI per instruction - } - } - } - - return Limit; -} - -void -ARMFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const { - // This tells PEI to spill the FP as if it is any other callee-save register - // to take advantage the eliminateFrameIndex machinery. This also ensures it - // is spilled in the order specified by getCalleeSavedRegs() to make it easier - // to combine multiple loads / stores. - bool CanEliminateFrame = true; - bool CS1Spilled = false; - bool LRSpilled = false; - unsigned NumGPRSpills = 0; - SmallVector UnspilledCS1GPRs; - SmallVector UnspilledCS2GPRs; - const ARMBaseRegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); - const ARMBaseInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - ARMFunctionInfo *AFI = MF.getInfo(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - unsigned FramePtr = RegInfo->getFrameRegister(MF); - - // Spill R4 if Thumb2 function requires stack realignment - it will be used as - // scratch register. Also spill R4 if Thumb2 function has varsized objects, - // since it's always posible to restore sp from fp in a single instruction. - // FIXME: It will be better just to find spare register here. - if (AFI->isThumb2Function() && - (MFI->hasVarSizedObjects() || RegInfo->needsStackRealignment(MF))) - MF.getRegInfo().setPhysRegUsed(ARM::R4); - - // Spill LR if Thumb1 function uses variable length argument lists. - if (AFI->isThumb1OnlyFunction() && AFI->getVarArgsRegSaveSize() > 0) - MF.getRegInfo().setPhysRegUsed(ARM::LR); - - // Spill the BasePtr if it's used. - if (RegInfo->hasBasePointer(MF)) - MF.getRegInfo().setPhysRegUsed(RegInfo->getBaseRegister()); - - // Don't spill FP if the frame can be eliminated. This is determined - // by scanning the callee-save registers to see if any is used. - const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(); - for (unsigned i = 0; CSRegs[i]; ++i) { - unsigned Reg = CSRegs[i]; - bool Spilled = false; - if (MF.getRegInfo().isPhysRegUsed(Reg)) { - AFI->setCSRegisterIsSpilled(Reg); - Spilled = true; - CanEliminateFrame = false; - } else { - // Check alias registers too. - for (const unsigned *Aliases = - RegInfo->getAliasSet(Reg); *Aliases; ++Aliases) { - if (MF.getRegInfo().isPhysRegUsed(*Aliases)) { - Spilled = true; - CanEliminateFrame = false; - } - } - } - - if (!ARM::GPRRegisterClass->contains(Reg)) - continue; - - if (Spilled) { - NumGPRSpills++; - - if (!STI.isTargetDarwin()) { - if (Reg == ARM::LR) - LRSpilled = true; - CS1Spilled = true; - continue; - } - - // Keep track if LR and any of R4, R5, R6, and R7 is spilled. - switch (Reg) { - case ARM::LR: - LRSpilled = true; - // Fallthrough - case ARM::R4: case ARM::R5: - case ARM::R6: case ARM::R7: - CS1Spilled = true; - break; - default: - break; - } - } else { - if (!STI.isTargetDarwin()) { - UnspilledCS1GPRs.push_back(Reg); - continue; - } - - switch (Reg) { - case ARM::R4: case ARM::R5: - case ARM::R6: case ARM::R7: - case ARM::LR: - UnspilledCS1GPRs.push_back(Reg); - break; - default: - UnspilledCS2GPRs.push_back(Reg); - break; - } - } - } - - bool ForceLRSpill = false; - if (!LRSpilled && AFI->isThumb1OnlyFunction()) { - unsigned FnSize = GetFunctionSizeInBytes(MF, TII); - // Force LR to be spilled if the Thumb function size is > 2048. This enables - // use of BL to implement far jump. If it turns out that it's not needed - // then the branch fix up path will undo it. - if (FnSize >= (1 << 11)) { - CanEliminateFrame = false; - ForceLRSpill = true; - } - } - - // If any of the stack slot references may be out of range of an immediate - // offset, make sure a register (or a spill slot) is available for the - // register scavenger. Note that if we're indexing off the frame pointer, the - // effective stack size is 4 bytes larger since the FP points to the stack - // slot of the previous FP. Also, if we have variable sized objects in the - // function, stack slot references will often be negative, and some of - // our instructions are positive-offset only, so conservatively consider - // that case to want a spill slot (or register) as well. Similarly, if - // the function adjusts the stack pointer during execution and the - // adjustments aren't already part of our stack size estimate, our offset - // calculations may be off, so be conservative. - // FIXME: We could add logic to be more precise about negative offsets - // and which instructions will need a scratch register for them. Is it - // worth the effort and added fragility? - bool BigStack = - (RS && - (estimateStackSize(MF) + ((hasFP(MF) && AFI->hasStackFrame()) ? 4:0) >= - estimateRSStackSizeLimit(MF, this))) - || MFI->hasVarSizedObjects() - || (MFI->adjustsStack() && !canSimplifyCallFramePseudos(MF)); - - bool ExtraCSSpill = false; - if (BigStack || !CanEliminateFrame || RegInfo->cannotEliminateFrame(MF)) { - AFI->setHasStackFrame(true); - - // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled. - // Spill LR as well so we can fold BX_RET to the registers restore (LDM). - if (!LRSpilled && CS1Spilled) { - MF.getRegInfo().setPhysRegUsed(ARM::LR); - AFI->setCSRegisterIsSpilled(ARM::LR); - NumGPRSpills++; - UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(), - UnspilledCS1GPRs.end(), (unsigned)ARM::LR)); - ForceLRSpill = false; - ExtraCSSpill = true; - } - - if (hasFP(MF)) { - MF.getRegInfo().setPhysRegUsed(FramePtr); - NumGPRSpills++; - } - - // If stack and double are 8-byte aligned and we are spilling an odd number - // of GPRs, spill one extra callee save GPR so we won't have to pad between - // the integer and double callee save areas. - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - if (TargetAlign == 8 && (NumGPRSpills & 1)) { - if (CS1Spilled && !UnspilledCS1GPRs.empty()) { - for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { - unsigned Reg = UnspilledCS1GPRs[i]; - // Don't spill high register if the function is thumb1 - if (!AFI->isThumb1OnlyFunction() || - isARMLowRegister(Reg) || Reg == ARM::LR) { - MF.getRegInfo().setPhysRegUsed(Reg); - AFI->setCSRegisterIsSpilled(Reg); - if (!RegInfo->isReservedReg(MF, Reg)) - ExtraCSSpill = true; - break; - } - } - } else if (!UnspilledCS2GPRs.empty() && !AFI->isThumb1OnlyFunction()) { - unsigned Reg = UnspilledCS2GPRs.front(); - MF.getRegInfo().setPhysRegUsed(Reg); - AFI->setCSRegisterIsSpilled(Reg); - if (!RegInfo->isReservedReg(MF, Reg)) - ExtraCSSpill = true; - } - } - - // Estimate if we might need to scavenge a register at some point in order - // to materialize a stack offset. If so, either spill one additional - // callee-saved register or reserve a special spill slot to facilitate - // register scavenging. Thumb1 needs a spill slot for stack pointer - // adjustments also, even when the frame itself is small. - if (BigStack && !ExtraCSSpill) { - // If any non-reserved CS register isn't spilled, just spill one or two - // extra. That should take care of it! - unsigned NumExtras = TargetAlign / 4; - SmallVector Extras; - while (NumExtras && !UnspilledCS1GPRs.empty()) { - unsigned Reg = UnspilledCS1GPRs.back(); - UnspilledCS1GPRs.pop_back(); - if (!RegInfo->isReservedReg(MF, Reg) && - (!AFI->isThumb1OnlyFunction() || isARMLowRegister(Reg) || - Reg == ARM::LR)) { - Extras.push_back(Reg); - NumExtras--; - } - } - // For non-Thumb1 functions, also check for hi-reg CS registers - if (!AFI->isThumb1OnlyFunction()) { - while (NumExtras && !UnspilledCS2GPRs.empty()) { - unsigned Reg = UnspilledCS2GPRs.back(); - UnspilledCS2GPRs.pop_back(); - if (!RegInfo->isReservedReg(MF, Reg)) { - Extras.push_back(Reg); - NumExtras--; - } - } - } - if (Extras.size() && NumExtras == 0) { - for (unsigned i = 0, e = Extras.size(); i != e; ++i) { - MF.getRegInfo().setPhysRegUsed(Extras[i]); - AFI->setCSRegisterIsSpilled(Extras[i]); - } - } else if (!AFI->isThumb1OnlyFunction()) { - // note: Thumb1 functions spill to R12, not the stack. Reserve a slot - // closest to SP or frame pointer. - const TargetRegisterClass *RC = ARM::GPRRegisterClass; - RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), - RC->getAlignment(), - false)); - } - } - } - - if (ForceLRSpill) { - MF.getRegInfo().setPhysRegUsed(ARM::LR); - AFI->setCSRegisterIsSpilled(ARM::LR); - AFI->setLRIsSpilledForFarJump(true); - } -} Removed: llvm/trunk/lib/Target/ARM/ARMFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameInfo.h (removed) @@ -1,73 +0,0 @@ -//===-- ARMTargetFrameInfo.h - Define TargetFrameInfo for ARM ---*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -// -//===----------------------------------------------------------------------===// - -#ifndef ARM_FRAMEINFO_H -#define ARM_FRAMEINFO_H - -#include "ARM.h" -#include "ARMSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" - -namespace llvm { - class ARMSubtarget; - -class ARMFrameInfo : public TargetFrameInfo { -protected: - const ARMSubtarget &STI; - -public: - explicit ARMFrameInfo(const ARMSubtarget &sti) - : TargetFrameInfo(StackGrowsDown, sti.getStackAlignment(), 0, 4), STI(sti) { - } - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - - bool hasFP(const MachineFunction &MF) const; - bool hasReservedCallFrame(const MachineFunction &MF) const; - bool canSimplifyCallFramePseudos(const MachineFunction &MF) const; - int getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const; - int ResolveFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg, int SPAdj) const; - int getFrameIndexOffset(const MachineFunction &MF, int FI) const; - - void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const; - - private: - void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - const std::vector &CSI, unsigned StmOpc, - unsigned StrOpc, bool NoGap, - bool(*Func)(unsigned, bool)) const; - void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - const std::vector &CSI, unsigned LdmOpc, - unsigned LdrOpc, bool isVarArg, bool NoGap, - bool(*Func)(unsigned, bool)) const; -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?p2=llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp&p1=llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=======- ARMFrameInfo.cpp - ARM Frame Information ------------*- C++ -*-====// +//=======- ARMFrameLowering.cpp - ARM Frame Information --------*- C++ -*-====// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file contains the ARM implementation of TargetFrameInfo class. +// This file contains the ARM implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "ARMFrameInfo.h" +#include "ARMFrameLowering.h" #include "ARMAddressingModes.h" #include "ARMBaseInstrInfo.h" #include "ARMMachineFunctionInfo.h" @@ -28,7 +28,7 @@ /// pointer register. This is true if the function has variable sized allocas /// or if frame pointer elimination is disabled. /// -bool ARMFrameInfo::hasFP(const MachineFunction &MF) const { +bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); // Mac OS X requires FP not to be clobbered for backtracing purpose. @@ -48,7 +48,7 @@ // immediately on entry to the current function. This eliminates the need for // add/sub sp brackets around call sites. Returns true if the call frame is // included as part of the stack frame. -bool ARMFrameInfo::hasReservedCallFrame(const MachineFunction &MF) const { +bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { const MachineFrameInfo *FFI = MF.getFrameInfo(); unsigned CFSize = FFI->getMaxCallFrameSize(); // It's not always a good idea to include the call frame as part of the @@ -65,7 +65,7 @@ // call frame pseudos can be simplified. Unlike most targets, having a FP // is not sufficient here since we still may reference some objects via SP // even when FP is available in Thumb2 mode. -bool ARMFrameInfo::canSimplifyCallFramePseudos(const MachineFunction &MF)const { +bool ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF)const { return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); } @@ -115,7 +115,7 @@ Pred, PredReg, TII); } -void ARMFrameInfo::emitPrologue(MachineFunction &MF) const { +void ARMFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -293,7 +293,7 @@ AFI->setShouldRestoreSPFromFP(true); } -void ARMFrameInfo::emitEpilogue(MachineFunction &MF, +void ARMFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); assert(MBBI->getDesc().isReturn() && @@ -418,13 +418,13 @@ // FIXME: This can go wrong when references are SP-relative and simple call // frames aren't used. int -ARMFrameInfo::getFrameIndexReference(const MachineFunction &MF, int FI, +ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg) const { return ResolveFrameIndexReference(MF, FI, FrameReg, 0); } int -ARMFrameInfo::ResolveFrameIndexReference(const MachineFunction &MF, +ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, int FI, unsigned &FrameReg, int SPAdj) const { @@ -499,12 +499,12 @@ return Offset; } -int ARMFrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const { +int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { unsigned FrameReg; return getFrameIndexReference(MF, FI, FrameReg); } -void ARMFrameInfo::emitPushInst(MachineBasicBlock &MBB, +void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, unsigned StmOpc, unsigned StrOpc, bool NoGap, @@ -572,7 +572,7 @@ } } -void ARMFrameInfo::emitPopInst(MachineBasicBlock &MBB, +void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, unsigned LdmOpc, unsigned LdrOpc, @@ -642,7 +642,7 @@ } } -bool ARMFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, +bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const { @@ -663,7 +663,7 @@ return true; } -bool ARMFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, +bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const { @@ -726,7 +726,7 @@ /// instructions will require a scratch register during their expansion later. // FIXME: Move to TII? static unsigned estimateRSStackSizeLimit(MachineFunction &MF, - const TargetFrameInfo *TFI) { + const TargetFrameLowering *TFI) { const ARMFunctionInfo *AFI = MF.getInfo(); unsigned Limit = (1 << 12) - 1; for (MachineFunction::iterator BB = MF.begin(),E = MF.end(); BB != E; ++BB) { @@ -775,7 +775,7 @@ } void -ARMFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, +ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { // This tells PEI to spill the FP as if it is any other callee-save register // to take advantage the eliminateFrameIndex machinery. This also ensures it @@ -933,7 +933,7 @@ // If stack and double are 8-byte aligned and we are spilling an odd number // of GPRs, spill one extra callee save GPR so we won't have to pad between // the integer and double callee save areas. - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned TargetAlign = getStackAlignment(); if (TargetAlign == 8 && (NumGPRSpills & 1)) { if (CS1Spilled && !UnspilledCS1GPRs.empty()) { for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) { Copied: llvm/trunk/lib/Target/ARM/ARMFrameLowering.h (from r123169, llvm/trunk/lib/Target/ARM/ARMFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.h?p2=llvm/trunk/lib/Target/ARM/ARMFrameLowering.h&p1=llvm/trunk/lib/Target/ARM/ARMFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===-- ARMTargetFrameInfo.h - Define TargetFrameInfo for ARM ---*- C++ -*-===// +//==-- ARMTargetFrameLowering.h - Define frame lowering for ARM --*- C++ -*-==// // // The LLVM Compiler Infrastructure // @@ -16,18 +16,19 @@ #include "ARM.h" #include "ARMSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class ARMSubtarget; -class ARMFrameInfo : public TargetFrameInfo { +class ARMFrameLowering : public TargetFrameLowering { protected: const ARMSubtarget &STI; public: - explicit ARMFrameInfo(const ARMSubtarget &sti) - : TargetFrameInfo(StackGrowsDown, sti.getStackAlignment(), 0, 4), STI(sti) { + explicit ARMFrameLowering(const ARMSubtarget &sti) + : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), 0, 4), + STI(sti) { } /// emitProlog/emitEpilog - These methods insert prolog and epilog code into Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Jan 10 06:39:04 2011 @@ -902,10 +902,11 @@ return Sched::RegPressure; } +// FIXME: Move to RegInfo unsigned ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); switch (RC->getID()) { default: @@ -2317,7 +2318,7 @@ unsigned NumGPRs = CCInfo.getFirstUnallocated (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0])); - unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned Align = MF.getTarget().getFrameLowering()->getStackAlignment(); unsigned VARegSize = (4 - NumGPRs) * 4; unsigned VARegSaveSize = (VARegSize + Align - 1) & ~(Align - 1); unsigned ArgOffset = CCInfo.getNextStackOffset(); Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -28,7 +28,6 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -12,7 +12,7 @@ #include "ARMTargetMachine.h" #include "ARMMCAsmInfo.h" -#include "ARMFrameInfo.h" +#include "ARMFrameLowering.h" #include "ARM.h" #include "llvm/PassManager.h" #include "llvm/CodeGen/Passes.h" @@ -102,7 +102,7 @@ ELFWriterInfo(*this), TLInfo(*this), TSInfo(*this), - FrameInfo(Subtarget) { + FrameLowering(Subtarget) { if (!Subtarget.hasARMOps()) report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not " "support ARM mode execution!"); @@ -124,9 +124,9 @@ ELFWriterInfo(*this), TLInfo(*this), TSInfo(*this), - FrameInfo(Subtarget.hasThumb2() - ? new ARMFrameInfo(Subtarget) - : (ARMFrameInfo*)new Thumb1FrameInfo(Subtarget)) { + FrameLowering(Subtarget.hasThumb2() + ? new ARMFrameLowering(Subtarget) + : (ARMFrameLowering*)new Thumb1FrameLowering(Subtarget)) { } // Pass Pipeline Configuration Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Mon Jan 10 06:39:04 2011 @@ -16,13 +16,13 @@ #include "ARMInstrInfo.h" #include "ARMELFWriterInfo.h" -#include "ARMFrameInfo.h" +#include "ARMFrameLowering.h" #include "ARMJITInfo.h" #include "ARMSubtarget.h" #include "ARMISelLowering.h" #include "ARMSelectionDAGInfo.h" #include "Thumb1InstrInfo.h" -#include "Thumb1FrameInfo.h" +#include "Thumb1FrameLowering.h" #include "Thumb2InstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetData.h" @@ -67,7 +67,7 @@ ARMELFWriterInfo ELFWriterInfo; ARMTargetLowering TLInfo; ARMSelectionDAGInfo TSInfo; - ARMFrameInfo FrameInfo; + ARMFrameLowering FrameLowering; public: ARMTargetMachine(const Target &T, const std::string &TT, const std::string &FS); @@ -83,7 +83,9 @@ virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const { return &TSInfo; } - virtual const ARMFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const ARMFrameLowering *getFrameLowering() const { + return &FrameLowering; + } virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetData *getTargetData() const { return &DataLayout; } @@ -103,8 +105,8 @@ ARMELFWriterInfo ELFWriterInfo; ARMTargetLowering TLInfo; ARMSelectionDAGInfo TSInfo; - // Either Thumb1FrameInfo or ARMFrameInfo. - OwningPtr FrameInfo; + // Either Thumb1FrameLowering or ARMFrameLowering. + OwningPtr FrameLowering; public: ThumbTargetMachine(const Target &T, const std::string &TT, const std::string &FS); @@ -126,9 +128,9 @@ virtual const ARMBaseInstrInfo *getInstrInfo() const { return InstrInfo.get(); } - /// returns either Thumb1FrameInfo or ARMFrameInfo - virtual const ARMFrameInfo *getFrameInfo() const { - return FrameInfo.get(); + /// returns either Thumb1FrameLowering or ARMFrameLowering + virtual const ARMFrameLowering *getFrameLowering() const { + return FrameLowering.get(); } virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const ARMELFWriterInfo *getELFWriterInfo() const { Removed: llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.cpp (removed) @@ -1,345 +0,0 @@ -//=======- Thumb1FrameInfo.cpp - Thumb1 Frame Information ------*- C++ -*-====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the Thumb1 implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#include "Thumb1FrameInfo.h" -#include "ARMBaseInstrInfo.h" -#include "ARMMachineFunctionInfo.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" - -using namespace llvm; - -bool Thumb1FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const { - const MachineFrameInfo *FFI = MF.getFrameInfo(); - unsigned CFSize = FFI->getMaxCallFrameSize(); - // It's not always a good idea to include the call frame as part of the - // stack frame. ARM (especially Thumb) has small immediate offset to - // address the stack frame. So a large call frame can cause poor codegen - // and may even makes it impossible to scavenge a register. - if (CFSize >= ((1 << 8) - 1) * 4 / 2) // Half of imm8 * 4 - return false; - - return !MF.getFrameInfo()->hasVarSizedObjects(); -} - -static void emitSPUpdate(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - const TargetInstrInfo &TII, DebugLoc dl, - const Thumb1RegisterInfo &MRI, - int NumBytes) { - emitThumbRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes, TII, - MRI, dl); -} - -void Thumb1FrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); - MachineBasicBlock::iterator MBBI = MBB.begin(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - ARMFunctionInfo *AFI = MF.getInfo(); - const Thumb1RegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); - const Thumb1InstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - - unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); - unsigned NumBytes = MFI->getStackSize(); - const std::vector &CSI = MFI->getCalleeSavedInfo(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - unsigned FramePtr = RegInfo->getFrameRegister(MF); - unsigned BasePtr = RegInfo->getBaseRegister(); - - // Thumb add/sub sp, imm8 instructions implicitly multiply the offset by 4. - NumBytes = (NumBytes + 3) & ~3; - MFI->setStackSize(NumBytes); - - // Determine the sizes of each callee-save spill areas and record which frame - // belongs to which callee-save spill areas. - unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0; - int FramePtrSpillFI = 0; - - if (VARegSaveSize) - emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -VARegSaveSize); - - if (!AFI->hasStackFrame()) { - if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes); - return; - } - - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - int FI = CSI[i].getFrameIdx(); - switch (Reg) { - case ARM::R4: - case ARM::R5: - case ARM::R6: - case ARM::R7: - case ARM::LR: - if (Reg == FramePtr) - FramePtrSpillFI = FI; - AFI->addGPRCalleeSavedArea1Frame(FI); - GPRCS1Size += 4; - break; - case ARM::R8: - case ARM::R9: - case ARM::R10: - case ARM::R11: - if (Reg == FramePtr) - FramePtrSpillFI = FI; - if (STI.isTargetDarwin()) { - AFI->addGPRCalleeSavedArea2Frame(FI); - GPRCS2Size += 4; - } else { - AFI->addGPRCalleeSavedArea1Frame(FI); - GPRCS1Size += 4; - } - break; - default: - AFI->addDPRCalleeSavedAreaFrame(FI); - DPRCSSize += 8; - } - } - - if (MBBI != MBB.end() && MBBI->getOpcode() == ARM::tPUSH) { - ++MBBI; - if (MBBI != MBB.end()) - dl = MBBI->getDebugLoc(); - } - - // Determine starting offsets of spill areas. - unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize); - unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize; - unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size; - AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes); - AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset); - AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset); - AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset); - NumBytes = DPRCSOffset; - - // Adjust FP so it point to the stack slot that contains the previous FP. - if (hasFP(MF)) { - BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr) - .addFrameIndex(FramePtrSpillFI).addImm(0); - if (NumBytes > 7) - // If offset is > 7 then sp cannot be adjusted in a single instruction, - // try restoring from fp instead. - AFI->setShouldRestoreSPFromFP(true); - } - - if (NumBytes) - // Insert it after all the callee-save spills. - emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, -NumBytes); - - if (STI.isTargetELF() && hasFP(MF)) - MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() - - AFI->getFramePtrSpillOffset()); - - AFI->setGPRCalleeSavedArea1Size(GPRCS1Size); - AFI->setGPRCalleeSavedArea2Size(GPRCS2Size); - AFI->setDPRCalleeSavedAreaSize(DPRCSSize); - - // If we need a base pointer, set it up here. It's whatever the value - // of the stack pointer is at this point. Any variable size objects - // will be allocated after this, so we can still use the base pointer - // to reference locals. - if (RegInfo->hasBasePointer(MF)) - BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr).addReg(ARM::SP); -} - -static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { - for (unsigned i = 0; CSRegs[i]; ++i) - if (Reg == CSRegs[i]) - return true; - return false; -} - -static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { - if (MI->getOpcode() == ARM::tRestore && - MI->getOperand(1).isFI() && - isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)) - return true; - else if (MI->getOpcode() == ARM::tPOP) { - // The first two operands are predicates. The last two are - // imp-def and imp-use of SP. Check everything in between. - for (int i = 2, e = MI->getNumOperands() - 2; i != e; ++i) - if (!isCalleeSavedRegister(MI->getOperand(i).getReg(), CSRegs)) - return false; - return true; - } - return false; -} - -void Thumb1FrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - assert((MBBI->getOpcode() == ARM::tBX_RET || - MBBI->getOpcode() == ARM::tPOP_RET) && - "Can only insert epilog into returning blocks"); - DebugLoc dl = MBBI->getDebugLoc(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - ARMFunctionInfo *AFI = MF.getInfo(); - const Thumb1RegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); - const Thumb1InstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - - unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize(); - int NumBytes = (int)MFI->getStackSize(); - const unsigned *CSRegs = RegInfo->getCalleeSavedRegs(); - unsigned FramePtr = RegInfo->getFrameRegister(MF); - - if (!AFI->hasStackFrame()) { - if (NumBytes != 0) - emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes); - } else { - // Unwind MBBI to point to first LDR / VLDRD. - if (MBBI != MBB.begin()) { - do - --MBBI; - while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs)); - if (!isCSRestore(MBBI, CSRegs)) - ++MBBI; - } - - // Move SP to start of FP callee save spill area. - NumBytes -= (AFI->getGPRCalleeSavedArea1Size() + - AFI->getGPRCalleeSavedArea2Size() + - AFI->getDPRCalleeSavedAreaSize()); - - if (AFI->shouldRestoreSPFromFP()) { - NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; - // Reset SP based on frame pointer only if the stack frame extends beyond - // frame pointer stack slot or target is ELF and the function has FP. - if (NumBytes) { - assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && - "No scratch register to restore SP from FP!"); - emitThumbRegPlusImmediate(MBB, MBBI, ARM::R4, FramePtr, -NumBytes, - TII, *RegInfo, dl); - BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP) - .addReg(ARM::R4); - } else - BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP) - .addReg(FramePtr); - } else { - if (MBBI->getOpcode() == ARM::tBX_RET && - &MBB.front() != MBBI && - prior(MBBI)->getOpcode() == ARM::tPOP) { - MachineBasicBlock::iterator PMBBI = prior(MBBI); - emitSPUpdate(MBB, PMBBI, TII, dl, *RegInfo, NumBytes); - } else - emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, NumBytes); - } - } - - if (VARegSaveSize) { - // Unlike T2 and ARM mode, the T1 pop instruction cannot restore - // to LR, and we can't pop the value directly to the PC since - // we need to update the SP after popping the value. Therefore, we - // pop the old LR into R3 as a temporary. - - // Move back past the callee-saved register restoration - while (MBBI != MBB.end() && isCSRestore(MBBI, CSRegs)) - ++MBBI; - // Epilogue for vararg functions: pop LR to R3 and branch off it. - AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tPOP))) - .addReg(ARM::R3, RegState::Define); - - emitSPUpdate(MBB, MBBI, TII, dl, *RegInfo, VARegSaveSize); - - BuildMI(MBB, MBBI, dl, TII.get(ARM::tBX_RET_vararg)) - .addReg(ARM::R3, RegState::Kill); - // erase the old tBX_RET instruction - MBB.erase(MBBI); - } -} - -bool Thumb1FrameInfo:: -spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - DebugLoc DL; - MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - - if (MI != MBB.end()) DL = MI->getDebugLoc(); - - MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); - AddDefaultPred(MIB); - for (unsigned i = CSI.size(); i != 0; --i) { - unsigned Reg = CSI[i-1].getReg(); - bool isKill = true; - - // Add the callee-saved register as live-in unless it's LR and - // @llvm.returnaddress is called. If LR is returned for @llvm.returnaddress - // then it's already added to the function and entry block live-in sets. - if (Reg == ARM::LR) { - MachineFunction &MF = *MBB.getParent(); - if (MF.getFrameInfo()->isReturnAddressTaken() && - MF.getRegInfo().isLiveIn(Reg)) - isKill = false; - } - - if (isKill) - MBB.addLiveIn(Reg); - - MIB.addReg(Reg, getKillRegState(isKill)); - } - return true; -} - -bool Thumb1FrameInfo:: -restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - MachineFunction &MF = *MBB.getParent(); - ARMFunctionInfo *AFI = MF.getInfo(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - - bool isVarArg = AFI->getVarArgsRegSaveSize() > 0; - DebugLoc DL = MI->getDebugLoc(); - MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP)); - AddDefaultPred(MIB); - - bool NumRegs = false; - for (unsigned i = CSI.size(); i != 0; --i) { - unsigned Reg = CSI[i-1].getReg(); - if (Reg == ARM::LR) { - // Special epilogue for vararg functions. See emitEpilogue - if (isVarArg) - continue; - Reg = ARM::PC; - (*MIB).setDesc(TII.get(ARM::tPOP_RET)); - MI = MBB.erase(MI); - } - MIB.addReg(Reg, getDefRegState(true)); - NumRegs = true; - } - - // It's illegal to emit pop instruction without operands. - if (NumRegs) - MBB.insert(MI, &*MIB); - else - MF.DeleteMachineInstr(MIB); - - return true; -} Removed: llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.h (original) +++ llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.h (removed) @@ -1,52 +0,0 @@ -//===-- Thumb1FrameInfo.h - Thumb1-specific frame info stuff ----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -// -//===----------------------------------------------------------------------===// - -#ifndef __THUMB_FRAMEINFO_H_ -#define __THUMM_FRAMEINFO_H_ - -#include "ARM.h" -#include "ARMFrameInfo.h" -#include "ARMSubtarget.h" -#include "Thumb1InstrInfo.h" -#include "Thumb1RegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" - -namespace llvm { - class ARMSubtarget; - -class Thumb1FrameInfo : public ARMFrameInfo { -public: - explicit Thumb1FrameInfo(const ARMSubtarget &sti) - : ARMFrameInfo(sti) { - } - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - - bool hasReservedCallFrame(const MachineFunction &MF) const; -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (from r123169, llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?p2=llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp&p1=llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=======- Thumb1FrameInfo.cpp - Thumb1 Frame Information ------*- C++ -*-====// +//======- Thumb1FrameLowering.cpp - Thumb1 Frame Information ---*- C++ -*-====// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Thumb1 implementation of TargetFrameInfo class. +// This file contains the Thumb1 implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "Thumb1FrameInfo.h" +#include "Thumb1FrameLowering.h" #include "ARMBaseInstrInfo.h" #include "ARMMachineFunctionInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h" @@ -21,7 +21,7 @@ using namespace llvm; -bool Thumb1FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const { +bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { const MachineFrameInfo *FFI = MF.getFrameInfo(); unsigned CFSize = FFI->getMaxCallFrameSize(); // It's not always a good idea to include the call frame as part of the @@ -43,7 +43,7 @@ MRI, dl); } -void Thumb1FrameInfo::emitPrologue(MachineFunction &MF) const { +void Thumb1FrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -181,7 +181,7 @@ return false; } -void Thumb1FrameInfo::emitEpilogue(MachineFunction &MF, +void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); assert((MBBI->getOpcode() == ARM::tBX_RET || @@ -265,7 +265,7 @@ } } -bool Thumb1FrameInfo:: +bool Thumb1FrameLowering:: spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, @@ -303,7 +303,7 @@ return true; } -bool Thumb1FrameInfo:: +bool Thumb1FrameLowering:: restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, Copied: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.h (from r123169, llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.h?p2=llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.h&p1=llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1FrameInfo.h (original) +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===-- Thumb1FrameInfo.h - Thumb1-specific frame info stuff ----*- C++ -*-===// +//===-- Thumb1FrameLowering.h - Thumb1-specific frame info stuff --*- C++ -*-=// // // The LLVM Compiler Infrastructure // @@ -15,19 +15,19 @@ #define __THUMM_FRAMEINFO_H_ #include "ARM.h" -#include "ARMFrameInfo.h" +#include "ARMFrameLowering.h" #include "ARMSubtarget.h" #include "Thumb1InstrInfo.h" #include "Thumb1RegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class ARMSubtarget; -class Thumb1FrameInfo : public ARMFrameInfo { +class Thumb1FrameLowering : public ARMFrameLowering { public: - explicit Thumb1FrameInfo(const ARMSubtarget &sti) - : ARMFrameInfo(sti) { + explicit Thumb1FrameLowering(const ARMSubtarget &sti) + : ARMFrameLowering(sti) { } /// emitProlog/emitEpilog - These methods insert prolog and epilog code into Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -29,7 +29,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLocation.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallVector.h" @@ -290,7 +290,7 @@ void Thumb1RegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (!TFI->hasReservedCallFrame(MF)) { // If we have alloca, convert as follows: @@ -303,7 +303,7 @@ // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next // alignment boundary. - unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned Align = TFI->getStackAlignment(); Amount = (Amount+Align-1)/Align*Align; // Replace the pseudo instruction with a new instruction... @@ -602,7 +602,7 @@ else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex)) Offset -= AFI->getGPRCalleeSavedArea2Offset(); else if (MF.getFrameInfo()->hasVarSizedObjects()) { - assert(SPAdj == 0 && MF.getTarget().getFrameInfo()->hasFP(MF) && + assert(SPAdj == 0 && MF.getTarget().getFrameLowering()->hasFP(MF) && "Unexpected"); // There are alloca()'s in this function, must reference off the frame // pointer or base pointer instead. Modified: llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2RegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -29,7 +29,6 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineLocation.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallVector.h" Removed: llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.cpp (removed) @@ -1,143 +0,0 @@ -//=====- AlphaFrameInfo.cpp - Alpha Frame Information ----------*- C++ -*-====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the Alpha implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#include "AlphaFrameInfo.h" -#include "AlphaInstrInfo.h" -#include "AlphaMachineFunctionInfo.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/ADT/Twine.h" - -using namespace llvm; - -static long getUpper16(long l) { - long y = l / Alpha::IMM_MULT; - if (l % Alpha::IMM_MULT > Alpha::IMM_HIGH) - ++y; - return y; -} - -static long getLower16(long l) { - long h = getUpper16(l); - return l - h * Alpha::IMM_MULT; -} - -// hasFP - Return true if the specified function should have a dedicated frame -// pointer register. This is true if the function has variable sized allocas or -// if frame pointer elimination is disabled. -// -bool AlphaFrameInfo::hasFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - return MFI->hasVarSizedObjects(); -} - -void AlphaFrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB - MachineBasicBlock::iterator MBBI = MBB.begin(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - - DebugLoc dl = (MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc()); - bool FP = hasFP(MF); - - // Handle GOP offset - BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAHg), Alpha::R29) - .addGlobalAddress(MF.getFunction()).addReg(Alpha::R27).addImm(++curgpdist); - BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAg), Alpha::R29) - .addGlobalAddress(MF.getFunction()).addReg(Alpha::R29).addImm(curgpdist); - - BuildMI(MBB, MBBI, dl, TII.get(Alpha::ALTENT)) - .addGlobalAddress(MF.getFunction()); - - // Get the number of bytes to allocate from the FrameInfo - long NumBytes = MFI->getStackSize(); - - if (FP) - NumBytes += 8; //reserve space for the old FP - - // Do we need to allocate space on the stack? - if (NumBytes == 0) return; - - unsigned Align = getStackAlignment(); - NumBytes = (NumBytes+Align-1)/Align*Align; - - // Update frame info to pretend that this is part of the stack... - MFI->setStackSize(NumBytes); - - // adjust stack pointer: r30 -= numbytes - NumBytes = -NumBytes; - if (NumBytes >= Alpha::IMM_LOW) { - BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) - .addReg(Alpha::R30); - } else if (getUpper16(NumBytes) >= Alpha::IMM_LOW) { - BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) - .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); - BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) - .addImm(getLower16(NumBytes)).addReg(Alpha::R30); - } else { - report_fatal_error("Too big a stack frame at " + Twine(NumBytes)); - } - - // Now if we need to, save the old FP and set the new - if (FP) { - BuildMI(MBB, MBBI, dl, TII.get(Alpha::STQ)) - .addReg(Alpha::R15).addImm(0).addReg(Alpha::R30); - // This must be the last instr in the prolog - BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R15) - .addReg(Alpha::R30).addReg(Alpha::R30); - } - -} - -void AlphaFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - - assert((MBBI->getOpcode() == Alpha::RETDAG || - MBBI->getOpcode() == Alpha::RETDAGp) - && "Can only insert epilog into returning blocks"); - DebugLoc dl = MBBI->getDebugLoc(); - - bool FP = hasFP(MF); - - // Get the number of bytes allocated from the FrameInfo... - long NumBytes = MFI->getStackSize(); - - //now if we need to, restore the old FP - if (FP) { - //copy the FP into the SP (discards allocas) - BuildMI(MBB, MBBI, dl, TII.get(Alpha::BISr), Alpha::R30).addReg(Alpha::R15) - .addReg(Alpha::R15); - //restore the FP - BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDQ), Alpha::R15) - .addImm(0).addReg(Alpha::R15); - } - - if (NumBytes != 0) { - if (NumBytes <= Alpha::IMM_HIGH) { - BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30).addImm(NumBytes) - .addReg(Alpha::R30); - } else if (getUpper16(NumBytes) <= Alpha::IMM_HIGH) { - BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDAH), Alpha::R30) - .addImm(getUpper16(NumBytes)).addReg(Alpha::R30); - BuildMI(MBB, MBBI, dl, TII.get(Alpha::LDA), Alpha::R30) - .addImm(getLower16(NumBytes)).addReg(Alpha::R30); - } else { - report_fatal_error("Too big a stack frame at " + Twine(NumBytes)); - } - } -} Removed: llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.h (removed) @@ -1,43 +0,0 @@ -//===--- AlphaFrameInfo.h - Define TargetFrameInfo for Alpha --*- C++ -*---===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -// -//===----------------------------------------------------------------------===// - -#ifndef ALPHA_FRAMEINFO_H -#define ALPHA_FRAMEINFO_H - -#include "Alpha.h" -#include "AlphaSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" - -namespace llvm { - class AlphaSubtarget; - -class AlphaFrameInfo : public TargetFrameInfo { - const AlphaSubtarget &STI; - // FIXME: This should end in MachineFunctionInfo, not here! - mutable int curgpdist; -public: - explicit AlphaFrameInfo(const AlphaSubtarget &sti) - : TargetFrameInfo(StackGrowsDown, 16, 0), STI(sti), curgpdist(0) { - } - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool hasFP(const MachineFunction &MF) const; -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.cpp?p2=llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.cpp&p1=llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=====- AlphaFrameInfo.cpp - Alpha Frame Information ----------*- C++ -*-====// +//=====- AlphaFrameLowering.cpp - Alpha Frame Information ------*- C++ -*-====// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Alpha implementation of TargetFrameInfo class. +// This file contains the Alpha implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "AlphaFrameInfo.h" +#include "AlphaFrameLowering.h" #include "AlphaInstrInfo.h" #include "AlphaMachineFunctionInfo.h" #include "llvm/Function.h" @@ -38,12 +38,12 @@ // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. // -bool AlphaFrameInfo::hasFP(const MachineFunction &MF) const { +bool AlphaFrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->hasVarSizedObjects(); } -void AlphaFrameInfo::emitPrologue(MachineFunction &MF) const { +void AlphaFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -101,7 +101,7 @@ } -void AlphaFrameInfo::emitEpilogue(MachineFunction &MF, +void AlphaFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); Copied: llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.h (from r123169, llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.h?p2=llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.h&p1=llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaFrameInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===--- AlphaFrameInfo.h - Define TargetFrameInfo for Alpha --*- C++ -*---===// +//==-- AlphaFrameLowering.h - Define frame lowering for Alpha --*- C++ -*---==// // // The LLVM Compiler Infrastructure // @@ -16,18 +16,18 @@ #include "Alpha.h" #include "AlphaSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class AlphaSubtarget; -class AlphaFrameInfo : public TargetFrameInfo { +class AlphaFrameLowering : public TargetFrameLowering { const AlphaSubtarget &STI; // FIXME: This should end in MachineFunctionInfo, not here! mutable int curgpdist; public: - explicit AlphaFrameInfo(const AlphaSubtarget &sti) - : TargetFrameInfo(StackGrowsDown, 16, 0), STI(sti), curgpdist(0) { + explicit AlphaFrameLowering(const AlphaSubtarget &sti) + : TargetFrameLowering(StackGrowsDown, 16, 0), STI(sti), curgpdist(0) { } /// emitProlog/emitEpilog - These methods insert prolog and epilog code into Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -22,7 +22,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetInstrInfo.h" @@ -81,7 +81,7 @@ void AlphaRegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (TFI->hasFP(MF)) { // If we have a frame pointer, turn the adjcallstackup instruction into a @@ -93,7 +93,7 @@ // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next // alignment boundary. - unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned Align = TFI->getStackAlignment(); Amount = (Amount+Align-1)/Align*Align; MachineInstr *New; @@ -131,7 +131,7 @@ MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); bool FP = TFI->hasFP(MF); @@ -178,7 +178,7 @@ } unsigned AlphaRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); return TFI->hasFP(MF) ? Alpha::R15 : Alpha::R30; } Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -28,7 +28,7 @@ const std::string &FS) : LLVMTargetMachine(T, TT), DataLayout("e-f128:128:128-n64"), - FrameInfo(Subtarget), + FrameLowering(Subtarget), Subtarget(TT, FS), TLInfo(*this), TSInfo(*this) { Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Mon Jan 10 06:39:04 2011 @@ -16,12 +16,12 @@ #include "AlphaInstrInfo.h" #include "AlphaISelLowering.h" -#include "AlphaFrameInfo.h" +#include "AlphaFrameLowering.h" #include "AlphaSelectionDAGInfo.h" #include "AlphaSubtarget.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { @@ -30,7 +30,7 @@ class AlphaTargetMachine : public LLVMTargetMachine { const TargetData DataLayout; // Calculates type size & alignment AlphaInstrInfo InstrInfo; - AlphaFrameInfo FrameInfo; + AlphaFrameLowering FrameLowering; AlphaSubtarget Subtarget; AlphaTargetLowering TLInfo; AlphaSelectionDAGInfo TSInfo; @@ -40,7 +40,9 @@ const std::string &FS); virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const TargetFrameLowering *getFrameLowering() const { + return &FrameLowering; + } virtual const AlphaSubtarget *getSubtargetImpl() const{ return &Subtarget; } virtual const AlphaRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); Removed: llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.cpp (removed) @@ -1,124 +0,0 @@ -//====- BlackfinFrameInfo.cpp - Blackfin Frame Information ------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the Blackfin implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#include "BlackfinFrameInfo.h" -#include "BlackfinInstrInfo.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/RegisterScavenging.h" -#include "llvm/Target/TargetOptions.h" - -using namespace llvm; - - -// hasFP - Return true if the specified function should have a dedicated frame -// pointer register. This is true if the function has variable sized allocas or -// if frame pointer elimination is disabled. -bool BlackfinFrameInfo::hasFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - return DisableFramePointerElim(MF) || - MFI->adjustsStack() || MFI->hasVarSizedObjects(); -} - -// Emit a prologue that sets up a stack frame. -// On function entry, R0-R2 and P0 may hold arguments. -// R3, P1, and P2 may be used as scratch registers -void BlackfinFrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB - MachineBasicBlock::iterator MBBI = MBB.begin(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - const BlackfinRegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); - const BlackfinInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - int FrameSize = MFI->getStackSize(); - if (FrameSize%4) { - FrameSize = (FrameSize+3) & ~3; - MFI->setStackSize(FrameSize); - } - - if (!hasFP(MF)) { - assert(!MFI->adjustsStack() && - "FP elimination on a non-leaf function is not supported"); - RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, -FrameSize); - return; - } - - // emit a LINK instruction - if (FrameSize <= 0x3ffff) { - BuildMI(MBB, MBBI, dl, TII.get(BF::LINK)).addImm(FrameSize); - return; - } - - // Frame is too big, do a manual LINK: - // [--SP] = RETS; - // [--SP] = FP; - // FP = SP; - // P1 = -FrameSize; - // SP = SP + P1; - BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH)) - .addReg(BF::RETS, RegState::Kill); - BuildMI(MBB, MBBI, dl, TII.get(BF::PUSH)) - .addReg(BF::FP, RegState::Kill); - BuildMI(MBB, MBBI, dl, TII.get(BF::MOVE), BF::FP) - .addReg(BF::SP); - RegInfo->loadConstant(MBB, MBBI, dl, BF::P1, -FrameSize); - BuildMI(MBB, MBBI, dl, TII.get(BF::ADDpp), BF::SP) - .addReg(BF::SP, RegState::Kill) - .addReg(BF::P1, RegState::Kill); - -} - -void BlackfinFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - const BlackfinRegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); - const BlackfinInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - DebugLoc dl = MBBI->getDebugLoc(); - - int FrameSize = MFI->getStackSize(); - assert(FrameSize%4 == 0 && "Misaligned frame size"); - - if (!hasFP(MF)) { - assert(!MFI->adjustsStack() && - "FP elimination on a non-leaf function is not supported"); - RegInfo->adjustRegister(MBB, MBBI, dl, BF::SP, BF::P1, FrameSize); - return; - } - - // emit an UNLINK instruction - BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK)); -} - -void BlackfinFrameInfo:: -processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - const BlackfinRegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); - const TargetRegisterClass *RC = BF::DPRegisterClass; - - if (RegInfo->requiresRegisterScavenging(MF)) { - // Reserve a slot close to SP or frame pointer. - RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), - RC->getAlignment(), - false)); - } -} Removed: llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.h (removed) @@ -1,46 +0,0 @@ -//=- BlackfinFrameInfo.h - Define TargetFrameInfo for Blackfin --*- C++ -*--==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -// -//===----------------------------------------------------------------------===// - -#ifndef ALPHA_FRAMEINFO_H -#define ALPHA_FRAMEINFO_H - -#include "Blackfin.h" -#include "BlackfinSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" - -namespace llvm { - class BlackfinSubtarget; - -class BlackfinFrameInfo : public TargetFrameInfo { -protected: - const BlackfinSubtarget &STI; - -public: - explicit BlackfinFrameInfo(const BlackfinSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 4, 0), STI(sti) { - } - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool hasFP(const MachineFunction &MF) const; - - void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const; -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp?p2=llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp&p1=llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//====- BlackfinFrameInfo.cpp - Blackfin Frame Information ------*- C++ -*-===// +//====- BlackfinFrameLowering.cpp - Blackfin Frame Information --*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Blackfin implementation of TargetFrameInfo class. +// This file contains the Blackfin implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "BlackfinFrameInfo.h" +#include "BlackfinFrameLowering.h" #include "BlackfinInstrInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -25,7 +25,7 @@ // hasFP - Return true if the specified function should have a dedicated frame // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. -bool BlackfinFrameInfo::hasFP(const MachineFunction &MF) const { +bool BlackfinFrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); return DisableFramePointerElim(MF) || MFI->adjustsStack() || MFI->hasVarSizedObjects(); @@ -34,7 +34,7 @@ // Emit a prologue that sets up a stack frame. // On function entry, R0-R2 and P0 may hold arguments. // R3, P1, and P2 may be used as scratch registers -void BlackfinFrameInfo::emitPrologue(MachineFunction &MF) const { +void BlackfinFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -83,7 +83,7 @@ } -void BlackfinFrameInfo::emitEpilogue(MachineFunction &MF, +void BlackfinFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineFrameInfo *MFI = MF.getFrameInfo(); const BlackfinRegisterInfo *RegInfo = @@ -107,7 +107,7 @@ BuildMI(MBB, MBBI, dl, TII.get(BF::UNLINK)); } -void BlackfinFrameInfo:: +void BlackfinFrameLowering:: processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { MachineFrameInfo *MFI = MF.getFrameInfo(); Copied: llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h (from r123169, llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h?p2=llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h&p1=llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinFrameInfo.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=- BlackfinFrameInfo.h - Define TargetFrameInfo for Blackfin --*- C++ -*--==// +//=- BlackfinFrameLowering.h - Define frame lowering for Blackfin -*- C++ -*-=// // // The LLVM Compiler Infrastructure // @@ -16,18 +16,18 @@ #include "Blackfin.h" #include "BlackfinSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class BlackfinSubtarget; -class BlackfinFrameInfo : public TargetFrameInfo { +class BlackfinFrameLowering : public TargetFrameLowering { protected: const BlackfinSubtarget &STI; public: - explicit BlackfinFrameInfo(const BlackfinSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 4, 0), STI(sti) { + explicit BlackfinFrameLowering(const BlackfinSubtarget &sti) + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0), STI(sti) { } /// emitProlog/emitEpilog - These methods insert prolog and epilog code into Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -22,7 +22,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" #include "llvm/CodeGen/RegisterScavenging.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetInstrInfo.h" @@ -50,7 +50,7 @@ BitVector BlackfinRegisterInfo::getReservedRegs(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); using namespace BF; BitVector Reserved(getNumRegs()); @@ -154,7 +154,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (!TFI->hasReservedCallFrame(MF)) { int64_t Amount = I->getOperand(0).getImm(); @@ -191,7 +191,7 @@ MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); DebugLoc DL = MI.getDebugLoc(); unsigned FIPos; @@ -331,7 +331,7 @@ unsigned BlackfinRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); return TFI->hasFP(MF) ? BF::FP : BF::SP; } Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td Mon Jan 10 06:39:04 2011 @@ -252,7 +252,7 @@ PClass::iterator PClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); return allocation_order_begin(MF) + (TFI->hasFP(MF) ? 7 : 6); } @@ -275,7 +275,7 @@ DPClass::iterator DPClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); return allocation_order_begin(MF) + (TFI->hasFP(MF) ? 15 : 14); } @@ -295,7 +295,7 @@ GRClass::iterator GRClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); return allocation_order_begin(MF) + (TFI->hasFP(MF) ? 31 : 30); } @@ -318,7 +318,7 @@ ALLClass::iterator ALLClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); return allocation_order_begin(MF) + (TFI->hasFP(MF) ? 31 : 30); } @@ -334,7 +334,7 @@ PIClass::iterator PIClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); return allocation_order_begin(MF) + (TFI->hasFP(MF) ? 11 : 10); } Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -33,7 +33,7 @@ TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), - FrameInfo(Subtarget) { + FrameLowering(Subtarget) { } bool BlackfinTargetMachine::addInstSelector(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h Mon Jan 10 06:39:04 2011 @@ -17,12 +17,12 @@ #include "BlackfinInstrInfo.h" #include "BlackfinIntrinsicInfo.h" #include "BlackfinISelLowering.h" -#include "BlackfinFrameInfo.h" +#include "BlackfinFrameLowering.h" #include "BlackfinSubtarget.h" #include "BlackfinSelectionDAGInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { @@ -32,14 +32,16 @@ BlackfinTargetLowering TLInfo; BlackfinSelectionDAGInfo TSInfo; BlackfinInstrInfo InstrInfo; - BlackfinFrameInfo FrameInfo; + BlackfinFrameLowering FrameLowering; BlackfinIntrinsicInfo IntrinsicInfo; public: BlackfinTargetMachine(const Target &T, const std::string &TT, const std::string &FS); virtual const BlackfinInstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const TargetFrameLowering *getFrameLowering() const { + return &FrameLowering; + } virtual const BlackfinSubtarget *getSubtargetImpl() const { return &Subtarget; } Removed: llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.cpp (removed) @@ -1,275 +0,0 @@ -//===-- SPUTargetMachine.cpp - Define TargetMachine for Cell SPU ----------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Top-level implementation for the Cell SPU target. -// -//===----------------------------------------------------------------------===// - -#include "SPU.h" -#include "SPUFrameInfo.h" -#include "SPURegisterNames.h" -#include "SPUInstrBuilder.h" -#include "SPUInstrInfo.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/RegisterScavenging.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Support/CommandLine.h" -using namespace llvm; - -//===----------------------------------------------------------------------===// -// SPUFrameInfo: -//===----------------------------------------------------------------------===// - -SPUFrameInfo::SPUFrameInfo(const SPUSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), - Subtarget(sti) { - LR[0].first = SPU::R0; - LR[0].second = 16; -} - - -//-------------------------------------------------------------------------- -// hasFP - Return true if the specified function actually has a dedicated frame -// pointer register. This is true if the function needs a frame pointer and has -// a non-zero stack size. -bool SPUFrameInfo::hasFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - - return MFI->getStackSize() && - (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()); -} - - -/// determineFrameLayout - Determine the size of the frame and maximum call -/// frame size. -void SPUFrameInfo::determineFrameLayout(MachineFunction &MF) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - - // Get the number of bytes to allocate from the FrameInfo - unsigned FrameSize = MFI->getStackSize(); - - // Get the alignments provided by the target, and the maximum alignment - // (if any) of the fixed frame objects. - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment()); - assert(isPowerOf2_32(Align) && "Alignment is not power of 2"); - unsigned AlignMask = Align - 1; - - // Get the maximum call frame size of all the calls. - unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); - - // If we have dynamic alloca then maxCallFrameSize needs to be aligned so - // that allocations will be aligned. - if (MFI->hasVarSizedObjects()) - maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; - - // Update maximum call frame size. - MFI->setMaxCallFrameSize(maxCallFrameSize); - - // Include call frame size in total. - FrameSize += maxCallFrameSize; - - // Make sure the frame is aligned. - FrameSize = (FrameSize + AlignMask) & ~AlignMask; - - // Update frame info. - MFI->setStackSize(FrameSize); -} - -void SPUFrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB - MachineBasicBlock::iterator MBBI = MBB.begin(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - const SPUInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - MachineModuleInfo &MMI = MF.getMMI(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - // Prepare for debug frame info. - bool hasDebugInfo = MMI.hasDebugInfo(); - MCSymbol *FrameLabel = 0; - - // Move MBBI back to the beginning of the function. - MBBI = MBB.begin(); - - // Work out frame sizes. - determineFrameLayout(MF); - int FrameSize = MFI->getStackSize(); - - assert((FrameSize & 0xf) == 0 - && "SPURegisterInfo::emitPrologue: FrameSize not aligned"); - - // the "empty" frame size is 16 - just the register scavenger spill slot - if (FrameSize > 16 || MFI->adjustsStack()) { - FrameSize = -(FrameSize + SPUFrameInfo::minStackSize()); - if (hasDebugInfo) { - // Mark effective beginning of when frame pointer becomes valid. - FrameLabel = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(FrameLabel); - } - - // Adjust stack pointer, spilling $lr -> 16($sp) and $sp -> -FrameSize($sp) - // for the ABI - BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R0).addImm(16) - .addReg(SPU::R1); - if (isInt<10>(FrameSize)) { - // Spill $sp to adjusted $sp - BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr32), SPU::R1).addImm(FrameSize) - .addReg(SPU::R1); - // Adjust $sp by required amout - BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1).addReg(SPU::R1) - .addImm(FrameSize); - } else if (isInt<16>(FrameSize)) { - // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use - // $r2 to adjust $sp: - BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2) - .addImm(-16) - .addReg(SPU::R1); - BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2) - .addImm(FrameSize); - BuildMI(MBB, MBBI, dl, TII.get(SPU::STQXr32), SPU::R1) - .addReg(SPU::R2) - .addReg(SPU::R1); - BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1) - .addReg(SPU::R1) - .addReg(SPU::R2); - BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2) - .addReg(SPU::R2) - .addImm(16); - BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2) - .addReg(SPU::R2) - .addReg(SPU::R1); - } else { - report_fatal_error("Unhandled frame size: " + Twine(FrameSize)); - } - - if (hasDebugInfo) { - std::vector &Moves = MMI.getFrameMoves(); - - // Show update of SP. - MachineLocation SPDst(MachineLocation::VirtualFP); - MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize); - Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); - - // Add callee saved registers to move list. - const std::vector &CSI = MFI->getCalleeSavedInfo(); - for (unsigned I = 0, E = CSI.size(); I != E; ++I) { - int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); - unsigned Reg = CSI[I].getReg(); - if (Reg == SPU::R0) continue; - MachineLocation CSDst(MachineLocation::VirtualFP, Offset); - MachineLocation CSSrc(Reg); - Moves.push_back(MachineMove(FrameLabel, CSDst, CSSrc)); - } - - // Mark effective beginning of when frame pointer is ready. - MCSymbol *ReadyLabel = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)).addSym(ReadyLabel); - - MachineLocation FPDst(SPU::R1); - MachineLocation FPSrc(MachineLocation::VirtualFP); - Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); - } - } else { - // This is a leaf function -- insert a branch hint iff there are - // sufficient number instructions in the basic block. Note that - // this is just a best guess based on the basic block's size. - if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - dl = MBBI->getDebugLoc(); - - // Insert terminator label - BuildMI(MBB, MBBI, dl, TII.get(SPU::PROLOG_LABEL)) - .addSym(MMI.getContext().CreateTempSymbol()); - } - } -} - -void SPUFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - const SPUInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - const MachineFrameInfo *MFI = MF.getFrameInfo(); - int FrameSize = MFI->getStackSize(); - int LinkSlotOffset = SPUFrameInfo::stackSlotSize(); - DebugLoc dl = MBBI->getDebugLoc(); - - assert(MBBI->getOpcode() == SPU::RET && - "Can only insert epilog into returning blocks"); - assert((FrameSize & 0xf) == 0 && "FrameSize not aligned"); - - // the "empty" frame size is 16 - just the register scavenger spill slot - if (FrameSize > 16 || MFI->adjustsStack()) { - FrameSize = FrameSize + SPUFrameInfo::minStackSize(); - if (isInt<10>(FrameSize + LinkSlotOffset)) { - // Reload $lr, adjust $sp by required amount - // Note: We do this to slightly improve dual issue -- not by much, but it - // is an opportunity for dual issue. - BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0) - .addImm(FrameSize + LinkSlotOffset) - .addReg(SPU::R1); - BuildMI(MBB, MBBI, dl, TII.get(SPU::AIr32), SPU::R1) - .addReg(SPU::R1) - .addImm(FrameSize); - } else if (FrameSize <= (1 << 16) - 1 && FrameSize >= -(1 << 16)) { - // Frame size can be loaded into ILr32n, so temporarily spill $r2 and use - // $r2 to adjust $sp: - BuildMI(MBB, MBBI, dl, TII.get(SPU::STQDr128), SPU::R2) - .addImm(16) - .addReg(SPU::R1); - BuildMI(MBB, MBBI, dl, TII.get(SPU::ILr32), SPU::R2) - .addImm(FrameSize); - BuildMI(MBB, MBBI, dl, TII.get(SPU::Ar32), SPU::R1) - .addReg(SPU::R1) - .addReg(SPU::R2); - BuildMI(MBB, MBBI, dl, TII.get(SPU::LQDr128), SPU::R0) - .addImm(16) - .addReg(SPU::R1); - BuildMI(MBB, MBBI, dl, TII.get(SPU::SFIr32), SPU::R2). - addReg(SPU::R2) - .addImm(16); - BuildMI(MBB, MBBI, dl, TII.get(SPU::LQXr128), SPU::R2) - .addReg(SPU::R2) - .addReg(SPU::R1); - } else { - report_fatal_error("Unhandled frame size: " + Twine(FrameSize)); - } - } -} - -void SPUFrameInfo::getInitialFrameState(std::vector &Moves) const { - // Initial state of the frame pointer is R1. - MachineLocation Dst(MachineLocation::VirtualFP); - MachineLocation Src(SPU::R1, 0); - Moves.push_back(MachineMove(0, Dst, Src)); -} - -void SPUFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const{ - // Mark LR and SP unused, since the prolog spills them to stack and - // we don't want anyone else to spill them for us. - // - // Also, unless R2 is really used someday, don't spill it automatically. - MF.getRegInfo().setPhysRegUnused(SPU::R0); - MF.getRegInfo().setPhysRegUnused(SPU::R1); - MF.getRegInfo().setPhysRegUnused(SPU::R2); - - MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetRegisterClass *RC = &SPU::R32CRegClass; - RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), - RC->getAlignment(), - false)); -} Removed: llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h (removed) @@ -1,94 +0,0 @@ -//===-- SPUFrameInfo.h - Top-level interface for Cell SPU Target -*- C++ -*-==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains CellSPU frame information that doesn't fit anywhere else -// cleanly... -// -//===----------------------------------------------------------------------===// - -#ifndef SPU_FRAMEINFO_H -#define SPU_FRAMEINFO_H - -#include "SPURegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" -#include "llvm/Target/TargetMachine.h" - -namespace llvm { - class SPUSubtarget; - - class SPUFrameInfo: public TargetFrameInfo { - const SPUSubtarget &Subtarget; - std::pair LR[1]; - - public: - SPUFrameInfo(const SPUSubtarget &sti); - - //! Determine the frame's layour - void determineFrameLayout(MachineFunction &MF) const; - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - //! Prediate: Target has dedicated frame pointer - bool hasFP(const MachineFunction &MF) const; - - void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS = NULL) const; - - //! Perform target-specific stack frame setup. - void getInitialFrameState(std::vector &Moves) const; - - //! Return a function's saved spill slots - /*! - For CellSPU, a function's saved spill slots is just the link register. - */ - const std::pair * - getCalleeSaveSpillSlots(unsigned &NumEntries) const; - - //! Stack slot size (16 bytes) - static int stackSlotSize() { - return 16; - } - //! Maximum frame offset representable by a signed 10-bit integer - /*! - This is the maximum frame offset that can be expressed as a 10-bit - integer, used in D-form addresses. - */ - static int maxFrameOffset() { - return ((1 << 9) - 1) * stackSlotSize(); - } - //! Minimum frame offset representable by a signed 10-bit integer - static int minFrameOffset() { - return -(1 << 9) * stackSlotSize(); - } - //! Minimum frame size (enough to spill LR + SP) - static int minStackSize() { - return (2 * stackSlotSize()); - } - //! Convert frame index to stack offset - static int FItoStackOffset(int frame_index) { - return frame_index * stackSlotSize(); - } - //! Number of instructions required to overcome hint-for-branch latency - /*! - HBR (hint-for-branch) instructions can be inserted when, for example, - we know that a given function is going to be called, such as printf(), - in the control flow graph. HBRs are only inserted if a sufficient number - of instructions occurs between the HBR and the target. Currently, HBRs - take 6 cycles, ergo, the magic number 6. - */ - static int branchHintPenalty() { - return 6; - } - }; -} - -#endif Copied: llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp?p2=llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp&p1=llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -12,7 +12,7 @@ //===----------------------------------------------------------------------===// #include "SPU.h" -#include "SPUFrameInfo.h" +#include "SPUFrameLowering.h" #include "SPURegisterNames.h" #include "SPUInstrBuilder.h" #include "SPUInstrInfo.h" @@ -29,11 +29,11 @@ using namespace llvm; //===----------------------------------------------------------------------===// -// SPUFrameInfo: +// SPUFrameLowering: //===----------------------------------------------------------------------===// -SPUFrameInfo::SPUFrameInfo(const SPUSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), +SPUFrameLowering::SPUFrameLowering(const SPUSubtarget &sti) + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 16, 0), Subtarget(sti) { LR[0].first = SPU::R0; LR[0].second = 16; @@ -44,7 +44,7 @@ // hasFP - Return true if the specified function actually has a dedicated frame // pointer register. This is true if the function needs a frame pointer and has // a non-zero stack size. -bool SPUFrameInfo::hasFP(const MachineFunction &MF) const { +bool SPUFrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->getStackSize() && @@ -54,7 +54,7 @@ /// determineFrameLayout - Determine the size of the frame and maximum call /// frame size. -void SPUFrameInfo::determineFrameLayout(MachineFunction &MF) const { +void SPUFrameLowering::determineFrameLayout(MachineFunction &MF) const { MachineFrameInfo *MFI = MF.getFrameInfo(); // Get the number of bytes to allocate from the FrameInfo @@ -62,7 +62,7 @@ // Get the alignments provided by the target, and the maximum alignment // (if any) of the fixed frame objects. - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned TargetAlign = getStackAlignment(); unsigned Align = std::max(TargetAlign, MFI->getMaxAlignment()); assert(isPowerOf2_32(Align) && "Alignment is not power of 2"); unsigned AlignMask = Align - 1; @@ -88,7 +88,7 @@ MFI->setStackSize(FrameSize); } -void SPUFrameInfo::emitPrologue(MachineFunction &MF) const { +void SPUFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -113,7 +113,7 @@ // the "empty" frame size is 16 - just the register scavenger spill slot if (FrameSize > 16 || MFI->adjustsStack()) { - FrameSize = -(FrameSize + SPUFrameInfo::minStackSize()); + FrameSize = -(FrameSize + SPUFrameLowering::minStackSize()); if (hasDebugInfo) { // Mark effective beginning of when frame pointer becomes valid. FrameLabel = MMI.getContext().CreateTempSymbol(); @@ -186,7 +186,7 @@ // This is a leaf function -- insert a branch hint iff there are // sufficient number instructions in the basic block. Note that // this is just a best guess based on the basic block's size. - if (MBB.size() >= (unsigned) SPUFrameInfo::branchHintPenalty()) { + if (MBB.size() >= (unsigned) SPUFrameLowering::branchHintPenalty()) { MachineBasicBlock::iterator MBBI = prior(MBB.end()); dl = MBBI->getDebugLoc(); @@ -197,14 +197,14 @@ } } -void SPUFrameInfo::emitEpilogue(MachineFunction &MF, +void SPUFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); const SPUInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); const MachineFrameInfo *MFI = MF.getFrameInfo(); int FrameSize = MFI->getStackSize(); - int LinkSlotOffset = SPUFrameInfo::stackSlotSize(); + int LinkSlotOffset = SPUFrameLowering::stackSlotSize(); DebugLoc dl = MBBI->getDebugLoc(); assert(MBBI->getOpcode() == SPU::RET && @@ -213,7 +213,7 @@ // the "empty" frame size is 16 - just the register scavenger spill slot if (FrameSize > 16 || MFI->adjustsStack()) { - FrameSize = FrameSize + SPUFrameInfo::minStackSize(); + FrameSize = FrameSize + SPUFrameLowering::minStackSize(); if (isInt<10>(FrameSize + LinkSlotOffset)) { // Reload $lr, adjust $sp by required amount // Note: We do this to slightly improve dual issue -- not by much, but it @@ -250,14 +250,15 @@ } } -void SPUFrameInfo::getInitialFrameState(std::vector &Moves) const { +void SPUFrameLowering::getInitialFrameState(std::vector &Moves) + const { // Initial state of the frame pointer is R1. MachineLocation Dst(MachineLocation::VirtualFP); MachineLocation Src(SPU::R1, 0); Moves.push_back(MachineMove(0, Dst, Src)); } -void SPUFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, +void SPUFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const{ // Mark LR and SP unused, since the prolog spills them to stack and // we don't want anyone else to spill them for us. Copied: llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.h (from r123169, llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.h?p2=llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.h&p1=llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUFrameInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===-- SPUFrameInfo.h - Top-level interface for Cell SPU Target -*- C++ -*-==// +//=====-- SPUFrameLowering.h - SPU Frame Lowering stuff -*- C++ -*----========// // // The LLVM Compiler Infrastructure // @@ -16,18 +16,18 @@ #define SPU_FRAMEINFO_H #include "SPURegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" namespace llvm { class SPUSubtarget; - class SPUFrameInfo: public TargetFrameInfo { + class SPUFrameLowering: public TargetFrameLowering { const SPUSubtarget &Subtarget; std::pair LR[1]; public: - SPUFrameInfo(const SPUSubtarget &sti); + SPUFrameLowering(const SPUSubtarget &sti); //! Determine the frame's layour void determineFrameLayout(MachineFunction &MF) const; Modified: llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelDAGToDAG.cpp Mon Jan 10 06:39:04 2011 @@ -15,7 +15,7 @@ #include "SPU.h" #include "SPUTargetMachine.h" #include "SPUHazardRecognizers.h" -#include "SPUFrameInfo.h" +#include "SPUFrameLowering.h" #include "SPURegisterNames.h" #include "SPUTargetMachine.h" #include "llvm/CodeGen/MachineConstantPool.h" @@ -390,8 +390,8 @@ SPUDAGToDAGISel::SelectDFormAddr(SDNode *Op, SDValue N, SDValue &Base, SDValue &Index) { return DFormAddressPredicate(Op, N, Base, Index, - SPUFrameInfo::minFrameOffset(), - SPUFrameInfo::maxFrameOffset()); + SPUFrameLowering::minFrameOffset(), + SPUFrameLowering::maxFrameOffset()); } bool @@ -407,7 +407,7 @@ int FI = int(FIN->getIndex()); DEBUG(errs() << "SelectDFormAddr: ISD::FrameIndex = " << FI << "\n"); - if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) { + if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) { Base = CurDAG->getTargetConstant(0, PtrTy); Index = CurDAG->getTargetFrameIndex(FI, PtrTy); return true; @@ -433,7 +433,7 @@ DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset << " frame index = " << FI << "\n"); - if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) { + if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) { Base = CurDAG->getTargetConstant(offset, PtrTy); Index = CurDAG->getTargetFrameIndex(FI, PtrTy); return true; @@ -454,7 +454,7 @@ DEBUG(errs() << "SelectDFormAddr: ISD::ADD offset = " << offset << " frame index = " << FI << "\n"); - if (SPUFrameInfo::FItoStackOffset(FI) < maxOffset) { + if (SPUFrameLowering::FItoStackOffset(FI) < maxOffset) { Base = CurDAG->getTargetConstant(offset, PtrTy); Index = CurDAG->getTargetFrameIndex(FI, PtrTy); return true; Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,3 @@ -// //===-- SPUISelLowering.cpp - Cell SPU DAG Lowering Implementation --------===// // The LLVM Compiler Infrastructure // @@ -14,7 +13,7 @@ #include "SPURegisterNames.h" #include "SPUISelLowering.h" #include "SPUTargetMachine.h" -#include "SPUFrameInfo.h" +#include "SPUFrameLowering.h" #include "SPUMachineFunction.h" #include "llvm/Constants.h" #include "llvm/Function.h" @@ -1123,9 +1122,9 @@ MachineRegisterInfo &RegInfo = MF.getRegInfo(); SPUFunctionInfo *FuncInfo = MF.getInfo(); - unsigned ArgOffset = SPUFrameInfo::minStackSize(); + unsigned ArgOffset = SPUFrameLowering::minStackSize(); unsigned ArgRegIdx = 0; - unsigned StackSlotSize = SPUFrameInfo::stackSlotSize(); + unsigned StackSlotSize = SPUFrameLowering::stackSlotSize(); EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); @@ -1274,7 +1273,7 @@ const SPUSubtarget *ST = SPUTM.getSubtargetImpl(); unsigned NumOps = Outs.size(); - unsigned StackSlotSize = SPUFrameInfo::stackSlotSize(); + unsigned StackSlotSize = SPUFrameLowering::stackSlotSize(); SmallVector ArgLocs; CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, @@ -1295,7 +1294,7 @@ // Figure out which arguments are going to go in registers, and which in // memory. - unsigned ArgOffset = SPUFrameInfo::minStackSize(); // Just below [LR] + unsigned ArgOffset = SPUFrameLowering::minStackSize(); // Just below [LR] unsigned ArgRegIdx = 0; // Keep track of registers passing arguments @@ -1342,7 +1341,7 @@ // Accumulate how many bytes are to be pushed on the stack, including the // linkage area, and parameter passing area. According to the SPU ABI, // we minimally need space for [LR] and [SP]. - unsigned NumStackBytes = ArgOffset - SPUFrameInfo::minStackSize(); + unsigned NumStackBytes = ArgOffset - SPUFrameLowering::minStackSize(); // Insert a call sequence start Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumStackBytes, Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Mon Jan 10 06:39:04 2011 @@ -140,7 +140,7 @@ const TargetRegisterInfo *TRI) const { unsigned opc; - bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset()); + bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset()); if (RC == SPU::GPRCRegisterClass) { opc = (isValidFrameIdx ? SPU::STQDr128 : SPU::STQXr128); } else if (RC == SPU::R64CRegisterClass) { @@ -175,7 +175,7 @@ const TargetRegisterInfo *TRI) const { unsigned opc; - bool isValidFrameIdx = (FrameIdx < SPUFrameInfo::maxFrameOffset()); + bool isValidFrameIdx = (FrameIdx < SPUFrameLowering::maxFrameOffset()); if (RC == SPU::GPRCRegisterClass) { opc = (isValidFrameIdx ? SPU::LQDr128 : SPU::LQXr128); } else if (RC == SPU::R64CRegisterClass) { Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -18,7 +18,7 @@ #include "SPUInstrBuilder.h" #include "SPUSubtarget.h" #include "SPUMachineFunction.h" -#include "SPUFrameInfo.h" +#include "SPUFrameLowering.h" #include "llvm/Constants.h" #include "llvm/Type.h" #include "llvm/CodeGen/ValueTypes.h" @@ -30,7 +30,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" #include "llvm/CodeGen/ValueTypes.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -283,7 +283,7 @@ MachineOperand &MO = MI.getOperand(OpNo); // Offset is biased by $lr's slot at the bottom. - Offset += MO.getImm() + MFI->getStackSize() + SPUFrameInfo::minStackSize(); + Offset += MO.getImm() + MFI->getStackSize() + SPUFrameLowering::minStackSize(); assert((Offset & 0xf) == 0 && "16-byte alignment violated in eliminateFrameIndex"); Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -29,7 +29,7 @@ } const std::pair * -SPUFrameInfo::getCalleeSaveSpillSlots(unsigned &NumEntries) const { +SPUFrameLowering::getCalleeSaveSpillSlots(unsigned &NumEntries) const { NumEntries = 1; return &LR[0]; } @@ -40,7 +40,7 @@ Subtarget(TT, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), - FrameInfo(Subtarget), + FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Mon Jan 10 06:39:04 2011 @@ -18,14 +18,14 @@ #include "SPUInstrInfo.h" #include "SPUISelLowering.h" #include "SPUSelectionDAGInfo.h" -#include "SPUFrameInfo.h" +#include "SPUFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetData.h" namespace llvm { class PassManager; class GlobalValue; -class TargetFrameInfo; +class TargetFrameLowering; /// SPUTargetMachine /// @@ -33,7 +33,7 @@ SPUSubtarget Subtarget; const TargetData DataLayout; SPUInstrInfo InstrInfo; - SPUFrameInfo FrameInfo; + SPUFrameLowering FrameLowering; SPUTargetLowering TLInfo; SPUSelectionDAGInfo TSInfo; InstrItineraryData InstrItins; @@ -48,8 +48,8 @@ virtual const SPUInstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const SPUFrameInfo *getFrameInfo() const { - return &FrameInfo; + virtual const SPUFrameLowering *getFrameLowering() const { + return &FrameLowering; } /*! \note Cell SPU does not support JIT today. It could support JIT at some Modified: llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeAsmPrinter.cpp Mon Jan 10 06:39:04 2011 @@ -125,7 +125,7 @@ // Create a bitmask with all callee saved registers for CPU or Floating Point // registers. For CPU registers consider RA, GP and FP for saving if necessary. void MBlazeAsmPrinter::printSavedRegsBitmask() { - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const TargetRegisterInfo &RI = *TM.getRegisterInfo(); // CPU Saved Registers Bitmasks Removed: llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp (removed) @@ -1,449 +0,0 @@ -//=======- MBlazeFrameInfo.cpp - MBlaze Frame Information ------*- C++ -*-====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the MBlaze implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "mblaze-frame-info" - -#include "MBlazeFrameInfo.h" -#include "MBlazeInstrInfo.h" -#include "MBlazeMachineFunction.h" -#include "InstPrinter/MBlazeInstPrinter.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/raw_ostream.h" - -using namespace llvm; - -namespace llvm { - cl::opt DisableStackAdjust( - "disable-mblaze-stack-adjust", - cl::init(false), - cl::desc("Disable MBlaze stack layout adjustment."), - cl::Hidden); -} - -static void replaceFrameIndexes(MachineFunction &MF, - SmallVector, 16> &FR) { - MachineFrameInfo *MFI = MF.getFrameInfo(); - MBlazeFunctionInfo *MBlazeFI = MF.getInfo(); - const SmallVector, 16>::iterator FRB = FR.begin(); - const SmallVector, 16>::iterator FRE = FR.end(); - - SmallVector, 16>::iterator FRI = FRB; - for (; FRI != FRE; ++FRI) { - MFI->RemoveStackObject(FRI->first); - int NFI = MFI->CreateFixedObject(4, FRI->second, true); - MBlazeFI->recordReplacement(FRI->first, NFI); - - for (MachineFunction::iterator MB=MF.begin(), ME=MF.end(); MB!=ME; ++MB) { - MachineBasicBlock::iterator MBB = MB->begin(); - const MachineBasicBlock::iterator MBE = MB->end(); - - for (; MBB != MBE; ++MBB) { - MachineInstr::mop_iterator MIB = MBB->operands_begin(); - const MachineInstr::mop_iterator MIE = MBB->operands_end(); - - for (MachineInstr::mop_iterator MII = MIB; MII != MIE; ++MII) { - if (!MII->isFI() || MII->getIndex() != FRI->first) continue; - DEBUG(dbgs() << "FOUND FI#" << MII->getIndex() << "\n"); - MII->setIndex(NFI); - } - } - } - } -} - -//===----------------------------------------------------------------------===// -// -// Stack Frame Processing methods -// +----------------------------+ -// -// The stack is allocated decrementing the stack pointer on -// the first instruction of a function prologue. Once decremented, -// all stack references are are done through a positive offset -// from the stack/frame pointer, so the stack is considered -// to grow up. -// -//===----------------------------------------------------------------------===// - -static void analyzeFrameIndexes(MachineFunction &MF) { - if (DisableStackAdjust) return; - - MachineFrameInfo *MFI = MF.getFrameInfo(); - MBlazeFunctionInfo *MBlazeFI = MF.getInfo(); - const MachineRegisterInfo &MRI = MF.getRegInfo(); - - MachineRegisterInfo::livein_iterator LII = MRI.livein_begin(); - MachineRegisterInfo::livein_iterator LIE = MRI.livein_end(); - const SmallVector &LiveInFI = MBlazeFI->getLiveIn(); - SmallVector EraseInstr; - SmallVector, 16> FrameRelocate; - - MachineBasicBlock *MBB = MF.getBlockNumbered(0); - MachineBasicBlock::iterator MIB = MBB->begin(); - MachineBasicBlock::iterator MIE = MBB->end(); - - int StackAdjust = 0; - int StackOffset = -28; - - // In this loop we are searching frame indexes that corrospond to incoming - // arguments that are already in the stack. We look for instruction sequences - // like the following: - // - // LWI REG, FI1, 0 - // ... - // SWI REG, FI2, 0 - // - // As long as there are no defs of REG in the ... part, we can eliminate - // the SWI instruction because the value has already been stored to the - // stack by the caller. All we need to do is locate FI at the correct - // stack location according to the calling convensions. - // - // Additionally, if the SWI operation kills the def of REG then we don't - // need the LWI operation so we can erase it as well. - for (unsigned i = 0, e = LiveInFI.size(); i < e; ++i) { - for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) { - if (I->getOpcode() != MBlaze::LWI || I->getNumOperands() != 3 || - !I->getOperand(1).isFI() || !I->getOperand(0).isReg() || - I->getOperand(1).getIndex() != LiveInFI[i]) continue; - - unsigned FIReg = I->getOperand(0).getReg(); - MachineBasicBlock::iterator SI = I; - for (SI++; SI != MIE; ++SI) { - if (!SI->getOperand(0).isReg() || - !SI->getOperand(1).isFI() || - SI->getOpcode() != MBlaze::SWI) continue; - - int FI = SI->getOperand(1).getIndex(); - if (SI->getOperand(0).getReg() != FIReg || - MFI->isFixedObjectIndex(FI) || - MFI->getObjectSize(FI) != 4) continue; - - if (SI->getOperand(0).isDef()) break; - - if (SI->getOperand(0).isKill()) { - DEBUG(dbgs() << "LWI for FI#" << I->getOperand(1).getIndex() - << " removed\n"); - EraseInstr.push_back(I); - } - - EraseInstr.push_back(SI); - DEBUG(dbgs() << "SWI for FI#" << FI << " removed\n"); - - FrameRelocate.push_back(std::make_pair(FI,StackOffset)); - DEBUG(dbgs() << "FI#" << FI << " relocated to " << StackOffset << "\n"); - - StackOffset -= 4; - StackAdjust += 4; - break; - } - } - } - - // In this loop we are searching for frame indexes that corrospond to - // incoming arguments that are in registers. We look for instruction - // sequences like the following: - // - // ... SWI REG, FI, 0 - // - // As long as the ... part does not define REG and if REG is an incoming - // parameter register then we know that, according to ABI convensions, the - // caller has allocated stack space for it already. Instead of allocating - // stack space on our frame, we record the correct location in the callers - // frame. - for (MachineRegisterInfo::livein_iterator LI = LII; LI != LIE; ++LI) { - for (MachineBasicBlock::iterator I=MIB; I != MIE; ++I) { - if (I->definesRegister(LI->first)) - break; - - if (I->getOpcode() != MBlaze::SWI || I->getNumOperands() != 3 || - !I->getOperand(1).isFI() || !I->getOperand(0).isReg() || - I->getOperand(1).getIndex() < 0) continue; - - if (I->getOperand(0).getReg() == LI->first) { - int FI = I->getOperand(1).getIndex(); - MBlazeFI->recordLiveIn(FI); - - int FILoc = 0; - switch (LI->first) { - default: llvm_unreachable("invalid incoming parameter!"); - case MBlaze::R5: FILoc = -4; break; - case MBlaze::R6: FILoc = -8; break; - case MBlaze::R7: FILoc = -12; break; - case MBlaze::R8: FILoc = -16; break; - case MBlaze::R9: FILoc = -20; break; - case MBlaze::R10: FILoc = -24; break; - } - - StackAdjust += 4; - FrameRelocate.push_back(std::make_pair(FI,FILoc)); - DEBUG(dbgs() << "FI#" << FI << " relocated to " << FILoc << "\n"); - break; - } - } - } - - // Go ahead and erase all of the instructions that we determined were - // no longer needed. - for (int i = 0, e = EraseInstr.size(); i < e; ++i) - MBB->erase(EraseInstr[i]); - - // Replace all of the frame indexes that we have relocated with new - // fixed object frame indexes. - replaceFrameIndexes(MF, FrameRelocate); -} - -static void interruptFrameLayout(MachineFunction &MF) { - const Function *F = MF.getFunction(); - llvm::CallingConv::ID CallConv = F->getCallingConv(); - - // If this function is not using either the interrupt_handler - // calling convention or the save_volatiles calling convention - // then we don't need to do any additional frame layout. - if (CallConv != llvm::CallingConv::MBLAZE_INTR && - CallConv != llvm::CallingConv::MBLAZE_SVOL) - return; - - MachineFrameInfo *MFI = MF.getFrameInfo(); - const MachineRegisterInfo &MRI = MF.getRegInfo(); - const MBlazeInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - - // Determine if the calling convention is the interrupt_handler - // calling convention. Some pieces of the prologue and epilogue - // only need to be emitted if we are lowering and interrupt handler. - bool isIntr = CallConv == llvm::CallingConv::MBLAZE_INTR; - - // Determine where to put prologue and epilogue additions - MachineBasicBlock &MENT = MF.front(); - MachineBasicBlock &MEXT = MF.back(); - - MachineBasicBlock::iterator MENTI = MENT.begin(); - MachineBasicBlock::iterator MEXTI = prior(MEXT.end()); - - DebugLoc ENTDL = MENTI != MENT.end() ? MENTI->getDebugLoc() : DebugLoc(); - DebugLoc EXTDL = MEXTI != MEXT.end() ? MEXTI->getDebugLoc() : DebugLoc(); - - // Store the frame indexes generated during prologue additions for use - // when we are generating the epilogue additions. - SmallVector VFI; - - // Build the prologue SWI for R3 - R12 if needed. Note that R11 must - // always have a SWI because it is used when processing RMSR. - for (unsigned r = MBlaze::R3; r <= MBlaze::R12; ++r) { - if (!MRI.isPhysRegUsed(r) && !(isIntr && r == MBlaze::R11)) continue; - - int FI = MFI->CreateStackObject(4,4,false,false); - VFI.push_back(FI); - - BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), r) - .addFrameIndex(FI).addImm(0); - } - - // Build the prologue SWI for R17, R18 - int R17FI = MFI->CreateStackObject(4,4,false,false); - int R18FI = MFI->CreateStackObject(4,4,false,false); - - BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R17) - .addFrameIndex(R17FI).addImm(0); - - BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R18) - .addFrameIndex(R18FI).addImm(0); - - // Buid the prologue SWI and the epilogue LWI for RMSR if needed - if (isIntr) { - int MSRFI = MFI->CreateStackObject(4,4,false,false); - BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::MFS), MBlaze::R11) - .addReg(MBlaze::RMSR); - BuildMI(MENT, MENTI, ENTDL, TII.get(MBlaze::SWI), MBlaze::R11) - .addFrameIndex(MSRFI).addImm(0); - - BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R11) - .addFrameIndex(MSRFI).addImm(0); - BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::MTS), MBlaze::RMSR) - .addReg(MBlaze::R11); - } - - // Build the epilogue LWI for R17, R18 - BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R18) - .addFrameIndex(R18FI).addImm(0); - - BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), MBlaze::R17) - .addFrameIndex(R17FI).addImm(0); - - // Build the epilogue LWI for R3 - R12 if needed - for (unsigned r = MBlaze::R12, i = VFI.size(); r >= MBlaze::R3; --r) { - if (!MRI.isPhysRegUsed(r)) continue; - BuildMI(MEXT, MEXTI, EXTDL, TII.get(MBlaze::LWI), r) - .addFrameIndex(VFI[--i]).addImm(0); - } -} - -static void determineFrameLayout(MachineFunction &MF) { - MachineFrameInfo *MFI = MF.getFrameInfo(); - MBlazeFunctionInfo *MBlazeFI = MF.getInfo(); - - // Replace the dummy '0' SPOffset by the negative offsets, as explained on - // LowerFORMAL_ARGUMENTS. Leaving '0' for while is necessary to avoid - // the approach done by calculateFrameObjectOffsets to the stack frame. - MBlazeFI->adjustLoadArgsFI(MFI); - MBlazeFI->adjustStoreVarArgsFI(MFI); - - // Get the number of bytes to allocate from the FrameInfo - unsigned FrameSize = MFI->getStackSize(); - DEBUG(dbgs() << "Original Frame Size: " << FrameSize << "\n" ); - - // Get the alignments provided by the target, and the maximum alignment - // (if any) of the fixed frame objects. - // unsigned MaxAlign = MFI->getMaxAlignment(); - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - unsigned AlignMask = TargetAlign - 1; - - // Make sure the frame is aligned. - FrameSize = (FrameSize + AlignMask) & ~AlignMask; - MFI->setStackSize(FrameSize); - DEBUG(dbgs() << "Aligned Frame Size: " << FrameSize << "\n" ); -} - -int MBlazeFrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) - const { - const MBlazeFunctionInfo *MBlazeFI = MF.getInfo(); - if (MBlazeFI->hasReplacement(FI)) - FI = MBlazeFI->getReplacement(FI); - return TargetFrameInfo::getFrameIndexOffset(MF,FI); -} - -// hasFP - Return true if the specified function should have a dedicated frame -// pointer register. This is true if the function has variable sized allocas or -// if frame pointer elimination is disabled. -bool MBlazeFrameInfo::hasFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects(); -} - -void MBlazeFrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - const MBlazeInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - MBlazeFunctionInfo *MBlazeFI = MF.getInfo(); - MachineBasicBlock::iterator MBBI = MBB.begin(); - DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - llvm::CallingConv::ID CallConv = MF.getFunction()->getCallingConv(); - bool requiresRA = CallConv == llvm::CallingConv::MBLAZE_INTR; - - // Determine the correct frame layout - determineFrameLayout(MF); - - // Get the number of bytes to allocate from the FrameInfo. - unsigned StackSize = MFI->getStackSize(); - - // No need to allocate space on the stack. - if (StackSize == 0 && !MFI->adjustsStack() && !requiresRA) return; - - int FPOffset = MBlazeFI->getFPStackOffset(); - int RAOffset = MBlazeFI->getRAStackOffset(); - - // Adjust stack : addi R1, R1, -imm - BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADDIK), MBlaze::R1) - .addReg(MBlaze::R1).addImm(-StackSize); - - // swi R15, R1, stack_loc - if (MFI->adjustsStack() || requiresRA) { - BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI)) - .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset); - } - - if (hasFP(MF)) { - // swi R19, R1, stack_loc - BuildMI(MBB, MBBI, DL, TII.get(MBlaze::SWI)) - .addReg(MBlaze::R19).addReg(MBlaze::R1).addImm(FPOffset); - - // add R19, R1, R0 - BuildMI(MBB, MBBI, DL, TII.get(MBlaze::ADD), MBlaze::R19) - .addReg(MBlaze::R1).addReg(MBlaze::R0); - } -} - -void MBlazeFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - MachineFrameInfo *MFI = MF.getFrameInfo(); - MBlazeFunctionInfo *MBlazeFI = MF.getInfo(); - const MBlazeInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - - DebugLoc dl = MBBI->getDebugLoc(); - - llvm::CallingConv::ID CallConv = MF.getFunction()->getCallingConv(); - bool requiresRA = CallConv == llvm::CallingConv::MBLAZE_INTR; - - // Get the FI's where RA and FP are saved. - int FPOffset = MBlazeFI->getFPStackOffset(); - int RAOffset = MBlazeFI->getRAStackOffset(); - - if (hasFP(MF)) { - // add R1, R19, R0 - BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADD), MBlaze::R1) - .addReg(MBlaze::R19).addReg(MBlaze::R0); - - // lwi R19, R1, stack_loc - BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R19) - .addReg(MBlaze::R1).addImm(FPOffset); - } - - // lwi R15, R1, stack_loc - if (MFI->adjustsStack() || requiresRA) { - BuildMI(MBB, MBBI, dl, TII.get(MBlaze::LWI), MBlaze::R15) - .addReg(MBlaze::R1).addImm(RAOffset); - } - - // Get the number of bytes from FrameInfo - int StackSize = (int) MFI->getStackSize(); - - // addi R1, R1, imm - if (StackSize) { - BuildMI(MBB, MBBI, dl, TII.get(MBlaze::ADDIK), MBlaze::R1) - .addReg(MBlaze::R1).addImm(StackSize); - } -} - -void MBlazeFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) - const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - MBlazeFunctionInfo *MBlazeFI = MF.getInfo(); - llvm::CallingConv::ID CallConv = MF.getFunction()->getCallingConv(); - bool requiresRA = CallConv == llvm::CallingConv::MBLAZE_INTR; - - if (MFI->adjustsStack() || requiresRA) { - MBlazeFI->setRAStackOffset(0); - MFI->CreateFixedObject(4,0,true); - } - - if (hasFP(MF)) { - MBlazeFI->setFPStackOffset(4); - MFI->CreateFixedObject(4,4,true); - } - - interruptFrameLayout(MF); - analyzeFrameIndexes(MF); -} Removed: llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.h (removed) @@ -1,53 +0,0 @@ -//=-- MBlazeFrameInfo.h - Define TargetFrameInfo for MicroBlaze --*- C++ -*--=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -// -//===----------------------------------------------------------------------===// - -#ifndef MBLAZE_FRAMEINFO_H -#define MBLAZE_FRAMEINFO_H - -#include "MBlaze.h" -#include "MBlazeSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" - -namespace llvm { - class MBlazeSubtarget; - -class MBlazeFrameInfo : public TargetFrameInfo { -protected: - const MBlazeSubtarget &STI; - -public: - explicit MBlazeFrameInfo(const MBlazeSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsUp, 4, 0), STI(sti) { - } - - /// targetHandlesStackFrameRounding - Returns true if the target is - /// responsible for rounding up the stack frame (probably at emitPrologue - /// time). - bool targetHandlesStackFrameRounding() const { return true; } - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool hasFP(const MachineFunction &MF) const; - - int getFrameIndexOffset(const MachineFunction &MF, int FI) const; - - virtual void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const; -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp?p2=llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp&p1=llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=======- MBlazeFrameInfo.cpp - MBlaze Frame Information ------*- C++ -*-====// +//=======- MBlazeFrameLowering.cpp - MBlaze Frame Information ------*- C++ -*-====// // // The LLVM Compiler Infrastructure // @@ -7,13 +7,13 @@ // //===----------------------------------------------------------------------===// // -// This file contains the MBlaze implementation of TargetFrameInfo class. +// This file contains the MBlaze implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#define DEBUG_TYPE "mblaze-frame-info" +#define DEBUG_TYPE "mblaze-frame-lowering" -#include "MBlazeFrameInfo.h" +#include "MBlazeFrameLowering.h" #include "MBlazeInstrInfo.h" #include "MBlazeMachineFunction.h" #include "InstPrinter/MBlazeInstPrinter.h" @@ -314,7 +314,7 @@ // Get the alignments provided by the target, and the maximum alignment // (if any) of the fixed frame objects. // unsigned MaxAlign = MFI->getMaxAlignment(); - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); unsigned AlignMask = TargetAlign - 1; // Make sure the frame is aligned. @@ -334,12 +334,12 @@ // hasFP - Return true if the specified function should have a dedicated frame // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. -bool MBlazeFrameInfo::hasFP(const MachineFunction &MF) const { +bool MBlazeFrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects(); } -void MBlazeFrameInfo::emitPrologue(MachineFunction &MF) const { +void MBlazeFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); const MBlazeInstrInfo &TII = @@ -384,7 +384,7 @@ } } -void MBlazeFrameInfo::emitEpilogue(MachineFunction &MF, +void MBlazeFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -427,8 +427,9 @@ } } -void MBlazeFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) - const { +void MBlazeFrameLowering:: +processFunctionBeforeCalleeSavedScan(MachineFunction &MF, + RegScavenger *RS) const { MachineFrameInfo *MFI = MF.getFrameInfo(); MBlazeFunctionInfo *MBlazeFI = MF.getInfo(); llvm::CallingConv::ID CallConv = MF.getFunction()->getCallingConv(); Copied: llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.h (from r123169, llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.h?p2=llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.h&p1=llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeFrameInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=-- MBlazeFrameInfo.h - Define TargetFrameInfo for MicroBlaze --*- C++ -*--=// +//=- MBlazeFrameLowering.h - Define frame lowering for MicroBlaze -*- C++ -*-=// // // The LLVM Compiler Infrastructure // @@ -16,18 +16,18 @@ #include "MBlaze.h" #include "MBlazeSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class MBlazeSubtarget; -class MBlazeFrameInfo : public TargetFrameInfo { +class MBlazeFrameLowering : public TargetFrameLowering { protected: const MBlazeSubtarget &STI; public: - explicit MBlazeFrameInfo(const MBlazeSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsUp, 4, 0), STI(sti) { + explicit MBlazeFrameLowering(const MBlazeSubtarget &sti) + : TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 4, 0), STI(sti) { } /// targetHandlesStackFrameRounding - Returns true if the target is Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Mon Jan 10 06:39:04 2011 @@ -697,7 +697,7 @@ MachineFunction &MF = DAG.getMachineFunction(); MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); + const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering(); // Analyze operands of the call, assigning locations to each operand. SmallVector ArgLocs; Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -1,5 +1,5 @@ //===- MBlazeRegisterInfo.cpp - MBlaze Register Information -== -*- C++ -*-===// -//DJ +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source @@ -26,7 +26,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetInstrInfo.h" @@ -223,7 +223,7 @@ void MBlazeRegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (!TFI->hasReservedCallFrame(MF)) { // If we have a frame pointer, turn the adjcallstackup instruction into a @@ -235,7 +235,7 @@ // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next // alignment boundary. - unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned Align = TFI->getStackAlignment(); Amount = (Amount+Align-1)/Align*Align; MachineInstr *New; @@ -317,7 +317,7 @@ } unsigned MBlazeRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); return TFI->hasFP(MF) ? MBlaze::R19 : MBlaze::R1; } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -85,7 +85,7 @@ Subtarget(TT, FS), DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), InstrInfo(*this), - FrameInfo(Subtarget), + FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this), ELFWriterInfo(*this) { if (getRelocationModel() == Reloc::Default) { setRelocationModel(Reloc::Static); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h Mon Jan 10 06:39:04 2011 @@ -19,24 +19,24 @@ #include "MBlazeISelLowering.h" #include "MBlazeSelectionDAGInfo.h" #include "MBlazeIntrinsicInfo.h" -#include "MBlazeFrameInfo.h" +#include "MBlazeFrameLowering.h" #include "MBlazeELFWriterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class formatted_raw_ostream; class MBlazeTargetMachine : public LLVMTargetMachine { - MBlazeSubtarget Subtarget; - const TargetData DataLayout; // Calculates type size & alignment - MBlazeInstrInfo InstrInfo; - MBlazeFrameInfo FrameInfo; - MBlazeTargetLowering TLInfo; + MBlazeSubtarget Subtarget; + const TargetData DataLayout; // Calculates type size & alignment + MBlazeInstrInfo InstrInfo; + MBlazeFrameLowering FrameLowering; + MBlazeTargetLowering TLInfo; MBlazeSelectionDAGInfo TSInfo; - MBlazeIntrinsicInfo IntrinsicInfo; + MBlazeIntrinsicInfo IntrinsicInfo; MBlazeELFWriterInfo ELFWriterInfo; public: MBlazeTargetMachine(const Target &T, const std::string &TT, @@ -45,8 +45,8 @@ virtual const MBlazeInstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const TargetFrameInfo *getFrameInfo() const - { return &FrameInfo; } + virtual const TargetFrameLowering *getFrameLowering() const + { return &FrameLowering; } virtual const MBlazeSubtarget *getSubtargetImpl() const { return &Subtarget; } Removed: llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.cpp (removed) @@ -1,223 +0,0 @@ -//=======- MSP430FrameInfo.cpp - MSP430 Frame Information ------*- C++ -*-====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the MSP430 implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#include "MSP430FrameInfo.h" -#include "MSP430InstrInfo.h" -#include "MSP430MachineFunctionInfo.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Support/CommandLine.h" - -using namespace llvm; - -bool MSP430FrameInfo::hasFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - - return (DisableFramePointerElim(MF) || - MF.getFrameInfo()->hasVarSizedObjects() || - MFI->isFrameAddressTaken()); -} - -bool MSP430FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const { - return !MF.getFrameInfo()->hasVarSizedObjects(); -} - -void MSP430FrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB - MachineFrameInfo *MFI = MF.getFrameInfo(); - MSP430MachineFunctionInfo *MSP430FI = MF.getInfo(); - const MSP430InstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - - MachineBasicBlock::iterator MBBI = MBB.begin(); - DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - // Get the number of bytes to allocate from the FrameInfo. - uint64_t StackSize = MFI->getStackSize(); - - uint64_t NumBytes = 0; - if (hasFP(MF)) { - // Calculate required stack adjustment - uint64_t FrameSize = StackSize - 2; - NumBytes = FrameSize - MSP430FI->getCalleeSavedFrameSize(); - - // Get the offset of the stack slot for the EBP register... which is - // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. - // Update the frame offset adjustment. - MFI->setOffsetAdjustment(-NumBytes); - - // Save FPW into the appropriate stack slot... - BuildMI(MBB, MBBI, DL, TII.get(MSP430::PUSH16r)) - .addReg(MSP430::FPW, RegState::Kill); - - // Update FPW with the new base value... - BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FPW) - .addReg(MSP430::SPW); - - // Mark the FramePtr as live-in in every block except the entry. - for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end(); - I != E; ++I) - I->addLiveIn(MSP430::FPW); - - } else - NumBytes = StackSize - MSP430FI->getCalleeSavedFrameSize(); - - // Skip the callee-saved push instructions. - while (MBBI != MBB.end() && (MBBI->getOpcode() == MSP430::PUSH16r)) - ++MBBI; - - if (MBBI != MBB.end()) - DL = MBBI->getDebugLoc(); - - if (NumBytes) { // adjust stack pointer: SPW -= numbytes - // If there is an SUB16ri of SPW immediately before this instruction, merge - // the two. - //NumBytes -= mergeSPUpdates(MBB, MBBI, true); - // If there is an ADD16ri or SUB16ri of SPW immediately after this - // instruction, merge the two instructions. - // mergeSPUpdatesDown(MBB, MBBI, &NumBytes); - - if (NumBytes) { - MachineInstr *MI = - BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SPW) - .addReg(MSP430::SPW).addImm(NumBytes); - // The SRW implicit def is dead. - MI->getOperand(3).setIsDead(); - } - } -} - -void MSP430FrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - MSP430MachineFunctionInfo *MSP430FI = MF.getInfo(); - const MSP430InstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - unsigned RetOpcode = MBBI->getOpcode(); - DebugLoc DL = MBBI->getDebugLoc(); - - switch (RetOpcode) { - case MSP430::RET: - case MSP430::RETI: break; // These are ok - default: - llvm_unreachable("Can only insert epilog into returning blocks"); - } - - // Get the number of bytes to allocate from the FrameInfo - uint64_t StackSize = MFI->getStackSize(); - unsigned CSSize = MSP430FI->getCalleeSavedFrameSize(); - uint64_t NumBytes = 0; - - if (hasFP(MF)) { - // Calculate required stack adjustment - uint64_t FrameSize = StackSize - 2; - NumBytes = FrameSize - CSSize; - - // pop FPW. - BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FPW); - } else - NumBytes = StackSize - CSSize; - - // Skip the callee-saved pop instructions. - while (MBBI != MBB.begin()) { - MachineBasicBlock::iterator PI = prior(MBBI); - unsigned Opc = PI->getOpcode(); - if (Opc != MSP430::POP16r && !PI->getDesc().isTerminator()) - break; - --MBBI; - } - - DL = MBBI->getDebugLoc(); - - // If there is an ADD16ri or SUB16ri of SPW immediately before this - // instruction, merge the two instructions. - //if (NumBytes || MFI->hasVarSizedObjects()) - // mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); - - if (MFI->hasVarSizedObjects()) { - BuildMI(MBB, MBBI, DL, - TII.get(MSP430::MOV16rr), MSP430::SPW).addReg(MSP430::FPW); - if (CSSize) { - MachineInstr *MI = - BuildMI(MBB, MBBI, DL, - TII.get(MSP430::SUB16ri), MSP430::SPW) - .addReg(MSP430::SPW).addImm(CSSize); - // The SRW implicit def is dead. - MI->getOperand(3).setIsDead(); - } - } else { - // adjust stack pointer back: SPW += numbytes - if (NumBytes) { - MachineInstr *MI = - BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SPW) - .addReg(MSP430::SPW).addImm(NumBytes); - // The SRW implicit def is dead. - MI->getOperand(3).setIsDead(); - } - } -} - -// FIXME: Can we eleminate these in favour of generic code? -bool -MSP430FrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - DebugLoc DL; - if (MI != MBB.end()) DL = MI->getDebugLoc(); - - MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - MSP430MachineFunctionInfo *MFI = MF.getInfo(); - MFI->setCalleeSavedFrameSize(CSI.size() * 2); - - for (unsigned i = CSI.size(); i != 0; --i) { - unsigned Reg = CSI[i-1].getReg(); - // Add the callee-saved register as live-in. It's killed at the spill. - MBB.addLiveIn(Reg); - BuildMI(MBB, MI, DL, TII.get(MSP430::PUSH16r)) - .addReg(Reg, RegState::Kill); - } - return true; -} - -bool -MSP430FrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - DebugLoc DL; - if (MI != MBB.end()) DL = MI->getDebugLoc(); - - MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - - for (unsigned i = 0, e = CSI.size(); i != e; ++i) - BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg()); - - return true; -} Removed: llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.h (removed) @@ -1,53 +0,0 @@ -//===-- MSP430FrameInfo.h - Define TargetFrameInfo for MSP430 --*- C++ -*--===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -// -//===----------------------------------------------------------------------===// - -#ifndef MSP430_FRAMEINFO_H -#define MSP430_FRAMEINFO_H - -#include "MSP430.h" -#include "MSP430Subtarget.h" -#include "llvm/Target/TargetFrameInfo.h" - -namespace llvm { - class MSP430Subtarget; - -class MSP430FrameInfo : public TargetFrameInfo { -protected: - const MSP430Subtarget &STI; - -public: - explicit MSP430FrameInfo(const MSP430Subtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 2, -2), STI(sti) { - } - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - - bool hasFP(const MachineFunction &MF) const; - bool hasReservedCallFrame(const MachineFunction &MF) const; -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp (from r123169, llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp?p2=llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp&p1=llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=======- MSP430FrameInfo.cpp - MSP430 Frame Information ------*- C++ -*-====// +//======-- MSP430FrameLowering.cpp - MSP430 Frame Information -------=========// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file contains the MSP430 implementation of TargetFrameInfo class. +// This file contains the MSP430 implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "MSP430FrameInfo.h" +#include "MSP430FrameLowering.h" #include "MSP430InstrInfo.h" #include "MSP430MachineFunctionInfo.h" #include "llvm/Function.h" @@ -26,7 +26,7 @@ using namespace llvm; -bool MSP430FrameInfo::hasFP(const MachineFunction &MF) const { +bool MSP430FrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); return (DisableFramePointerElim(MF) || @@ -34,11 +34,11 @@ MFI->isFrameAddressTaken()); } -bool MSP430FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const { +bool MSP430FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { return !MF.getFrameInfo()->hasVarSizedObjects(); } -void MSP430FrameInfo::emitPrologue(MachineFunction &MF) const { +void MSP430FrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineFrameInfo *MFI = MF.getFrameInfo(); MSP430MachineFunctionInfo *MSP430FI = MF.getInfo(); @@ -103,8 +103,8 @@ } } -void MSP430FrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { +void MSP430FrameLowering::emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); MSP430MachineFunctionInfo *MSP430FI = MF.getInfo(); const MSP430InstrInfo &TII = @@ -177,7 +177,7 @@ // FIXME: Can we eleminate these in favour of generic code? bool -MSP430FrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, +MSP430FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const { @@ -203,8 +203,8 @@ } bool -MSP430FrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, +MSP430FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const { if (CSI.empty()) Copied: llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.h (from r123169, llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.h?p2=llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.h&p1=llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430FrameInfo.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===-- MSP430FrameInfo.h - Define TargetFrameInfo for MSP430 --*- C++ -*--===// +//==- MSP430FrameLowering.h - Define frame lowering for MSP430 --*- C++ -*--==// // // The LLVM Compiler Infrastructure // @@ -16,18 +16,18 @@ #include "MSP430.h" #include "MSP430Subtarget.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class MSP430Subtarget; -class MSP430FrameInfo : public TargetFrameInfo { +class MSP430FrameLowering : public TargetFrameLowering { protected: const MSP430Subtarget &STI; public: - explicit MSP430FrameInfo(const MSP430Subtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 2, -2), STI(sti) { + explicit MSP430FrameLowering(const MSP430Subtarget &sti) + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) { } /// emitProlog/emitEpilog - These methods insert prolog and epilog code into Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -33,12 +33,12 @@ const TargetInstrInfo &tii) : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP), TM(tm), TII(tii) { - StackAlign = TM.getFrameInfo()->getStackAlignment(); + StackAlign = TM.getFrameLowering()->getStackAlignment(); } const unsigned* MSP430RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { - const TargetFrameInfo *TFI = MF->getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF->getTarget().getFrameLowering(); const Function* F = MF->getFunction(); static const unsigned CalleeSavedRegs[] = { MSP430::FPW, MSP430::R5W, MSP430::R6W, MSP430::R7W, @@ -74,7 +74,7 @@ BitVector MSP430RegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); // Mark 4 special registers as reserved. Reserved.set(MSP430::PCW); @@ -97,7 +97,7 @@ void MSP430RegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (!TFI->hasReservedCallFrame(MF)) { // If the stack pointer can be changed after prologue, turn the @@ -163,7 +163,7 @@ MachineInstr &MI = *II; MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); DebugLoc dl = MI.getDebugLoc(); while (!MI.getOperand(i).isFI()) { ++i; @@ -216,7 +216,7 @@ void MSP430RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); // Create a frame entry for the FPW register that must be saved. if (TFI->hasFP(MF)) { @@ -232,7 +232,7 @@ } unsigned MSP430RegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); return TFI->hasFP(MF) ? MSP430::FPW : MSP430::SPW; } Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td (original) +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.td Mon Jan 10 06:39:04 2011 @@ -79,7 +79,7 @@ GR8Class::iterator GR8Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); // Depending on whether the function uses frame pointer or not, last 5 or 4 // registers on the list above are reserved if (TFI->hasFP(MF)) @@ -106,7 +106,7 @@ GR16Class::iterator GR16Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); // Depending on whether the function uses frame pointer or not, last 5 or 4 // registers on the list above are reserved if (TFI->hasFP(MF)) Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -34,7 +34,7 @@ // FIXME: Check TargetData string. DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), InstrInfo(*this), TLInfo(*this), TSInfo(*this), - FrameInfo(Subtarget) { } + FrameLowering(Subtarget) { } bool MSP430TargetMachine::addInstSelector(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h Mon Jan 10 06:39:04 2011 @@ -17,12 +17,12 @@ #include "MSP430InstrInfo.h" #include "MSP430ISelLowering.h" -#include "MSP430FrameInfo.h" +#include "MSP430FrameLowering.h" #include "MSP430SelectionDAGInfo.h" #include "MSP430RegisterInfo.h" #include "MSP430Subtarget.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -35,13 +35,15 @@ MSP430InstrInfo InstrInfo; MSP430TargetLowering TLInfo; MSP430SelectionDAGInfo TSInfo; - MSP430FrameInfo FrameInfo; + MSP430FrameLowering FrameLowering; public: MSP430TargetMachine(const Target &T, const std::string &TT, const std::string &FS); - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const TargetFrameLowering *getFrameLowering() const { + return &FrameLowering; + } virtual const MSP430InstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetData *getTargetData() const { return &DataLayout;} virtual const MSP430Subtarget *getSubtargetImpl() const { return &Subtarget; } Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Mon Jan 10 06:39:04 2011 @@ -125,7 +125,7 @@ // Create a bitmask with all callee saved registers for CPU or Floating Point // registers. For CPU registers consider RA, GP and FP for saving if necessary. void MipsAsmPrinter::printSavedRegsBitmask(raw_ostream &O) { - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const TargetRegisterInfo *RI = TM.getRegisterInfo(); const MipsFunctionInfo *MipsFI = MF->getInfo(); @@ -146,6 +146,8 @@ } // Return Address and Frame registers must also be set in CPUBitmask. + // FIXME: Do we really need hasFP() call here? When no FP is present SP is + // just returned -- will it be ok? if (TFI->hasFP(*MF)) CPUBitmask |= (1 << MipsRegisterInfo:: getRegisterNumbering(RI->getFrameRegister(*MF))); Removed: llvm/trunk/lib/Target/Mips/MipsFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsFrameInfo.cpp (removed) @@ -1,307 +0,0 @@ -//=======- MipsFrameInfo.cpp - Mips Frame Information ----------*- C++ -*-====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the Mips implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#include "MipsFrameInfo.h" -#include "MipsInstrInfo.h" -#include "MipsMachineFunction.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Support/CommandLine.h" - -using namespace llvm; - - -//===----------------------------------------------------------------------===// -// -// Stack Frame Processing methods -// +----------------------------+ -// -// The stack is allocated decrementing the stack pointer on -// the first instruction of a function prologue. Once decremented, -// all stack references are done thought a positive offset -// from the stack/frame pointer, so the stack is considering -// to grow up! Otherwise terrible hacks would have to be made -// to get this stack ABI compliant :) -// -// The stack frame required by the ABI (after call): -// Offset -// -// 0 ---------- -// 4 Args to pass -// . saved $GP (used in PIC) -// . Alloca allocations -// . Local Area -// . CPU "Callee Saved" Registers -// . saved FP -// . saved RA -// . FPU "Callee Saved" Registers -// StackSize ----------- -// -// Offset - offset from sp after stack allocation on function prologue -// -// The sp is the stack pointer subtracted/added from the stack size -// at the Prologue/Epilogue -// -// References to the previous stack (to obtain arguments) are done -// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1)) -// -// Examples: -// - reference to the actual stack frame -// for any local area var there is smt like : FI >= 0, StackOffset: 4 -// sw REGX, 4(SP) -// -// - reference to previous stack frame -// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16. -// The emitted instruction will be something like: -// lw REGX, 16+StackSize(SP) -// -// Since the total stack size is unknown on LowerFormalArguments, all -// stack references (ObjectOffset) created to reference the function -// arguments, are negative numbers. This way, on eliminateFrameIndex it's -// possible to detect those references and the offsets are adjusted to -// their real location. -// -//===----------------------------------------------------------------------===// - -// hasFP - Return true if the specified function should have a dedicated frame -// pointer register. This is true if the function has variable sized allocas or -// if frame pointer elimination is disabled. -bool MipsFrameInfo::hasFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects(); -} - -void MipsFrameInfo::adjustMipsStackFrame(MachineFunction &MF) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - MipsFunctionInfo *MipsFI = MF.getInfo(); - const std::vector &CSI = MFI->getCalleeSavedInfo(); - unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - unsigned RegSize = STI.isGP32bit() ? 4 : 8; - bool HasGP = MipsFI->needGPSaveRestore(); - - // Min and Max CSI FrameIndex. - int MinCSFI = -1, MaxCSFI = -1; - - // See the description at MipsMachineFunction.h - int TopCPUSavedRegOff = -1, TopFPUSavedRegOff = -1; - - // Replace the dummy '0' SPOffset by the negative offsets, as explained on - // LowerFormalArguments. Leaving '0' for while is necessary to avoid the - // approach done by calculateFrameObjectOffsets to the stack frame. - MipsFI->adjustLoadArgsFI(MFI); - MipsFI->adjustStoreVarArgsFI(MFI); - - // It happens that the default stack frame allocation order does not directly - // map to the convention used for mips. So we must fix it. We move the callee - // save register slots after the local variables area, as described in the - // stack frame above. - unsigned CalleeSavedAreaSize = 0; - if (!CSI.empty()) { - MinCSFI = CSI[0].getFrameIdx(); - MaxCSFI = CSI[CSI.size()-1].getFrameIdx(); - } - for (unsigned i = 0, e = CSI.size(); i != e; ++i) - CalleeSavedAreaSize += MFI->getObjectAlignment(CSI[i].getFrameIdx()); - - unsigned StackOffset = HasGP ? (MipsFI->getGPStackOffset()+RegSize) - : (STI.isABI_O32() ? 16 : 0); - - // Adjust local variables. They should come on the stack right - // after the arguments. - int LastOffsetFI = -1; - for (int i = 0, e = MFI->getObjectIndexEnd(); i != e; ++i) { - if (i >= MinCSFI && i <= MaxCSFI) - continue; - if (MFI->isDeadObjectIndex(i)) - continue; - unsigned Offset = - StackOffset + MFI->getObjectOffset(i) - CalleeSavedAreaSize; - if (LastOffsetFI == -1) - LastOffsetFI = i; - if (Offset > MFI->getObjectOffset(LastOffsetFI)) - LastOffsetFI = i; - MFI->setObjectOffset(i, Offset); - } - - // Adjust CPU Callee Saved Registers Area. Registers RA and FP must - // be saved in this CPU Area. This whole area must be aligned to the - // default Stack Alignment requirements. - if (LastOffsetFI >= 0) - StackOffset = MFI->getObjectOffset(LastOffsetFI)+ - MFI->getObjectSize(LastOffsetFI); - StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign); - - for (unsigned i = 0, e = CSI.size(); i != e ; ++i) { - unsigned Reg = CSI[i].getReg(); - if (!Mips::CPURegsRegisterClass->contains(Reg)) - break; - MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset); - TopCPUSavedRegOff = StackOffset; - StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx()); - } - - // Stack locations for FP and RA. If only one of them is used, - // the space must be allocated for both, otherwise no space at all. - if (hasFP(MF) || MFI->adjustsStack()) { - // FP stack location - MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true), - StackOffset); - MipsFI->setFPStackOffset(StackOffset); - TopCPUSavedRegOff = StackOffset; - StackOffset += RegSize; - - // SP stack location - MFI->setObjectOffset(MFI->CreateStackObject(RegSize, RegSize, true), - StackOffset); - MipsFI->setRAStackOffset(StackOffset); - StackOffset += RegSize; - - if (MFI->adjustsStack()) - TopCPUSavedRegOff += RegSize; - } - - StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign); - - // Adjust FPU Callee Saved Registers Area. This Area must be - // aligned to the default Stack Alignment requirements. - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - if (Mips::CPURegsRegisterClass->contains(Reg)) - continue; - MFI->setObjectOffset(CSI[i].getFrameIdx(), StackOffset); - TopFPUSavedRegOff = StackOffset; - StackOffset += MFI->getObjectAlignment(CSI[i].getFrameIdx()); - } - StackOffset = ((StackOffset+StackAlign-1)/StackAlign*StackAlign); - - // Update frame info - MFI->setStackSize(StackOffset); - - // Recalculate the final tops offset. The final values must be '0' - // if there isn't a callee saved register for CPU or FPU, otherwise - // a negative offset is needed. - if (TopCPUSavedRegOff >= 0) - MipsFI->setCPUTopSavedRegOff(TopCPUSavedRegOff-StackOffset); - - if (TopFPUSavedRegOff >= 0) - MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset); -} - -void MipsFrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - MipsFunctionInfo *MipsFI = MF.getInfo(); - const MipsRegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); - const MipsInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - MachineBasicBlock::iterator MBBI = MBB.begin(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - bool isPIC = (MF.getTarget().getRelocationModel() == Reloc::PIC_); - - // Get the right frame order for Mips. - adjustMipsStackFrame(MF); - - // Get the number of bytes to allocate from the FrameInfo. - unsigned StackSize = MFI->getStackSize(); - - // No need to allocate space on the stack. - if (StackSize == 0 && !MFI->adjustsStack()) return; - - int FPOffset = MipsFI->getFPStackOffset(); - int RAOffset = MipsFI->getRAStackOffset(); - - BuildMI(MBB, MBBI, dl, TII.get(Mips::NOREORDER)); - - // TODO: check need from GP here. - if (isPIC && STI.isABI_O32()) - BuildMI(MBB, MBBI, dl, TII.get(Mips::CPLOAD)) - .addReg(RegInfo->getPICCallReg()); - BuildMI(MBB, MBBI, dl, TII.get(Mips::NOMACRO)); - - // Adjust stack : addi sp, sp, (-imm) - BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) - .addReg(Mips::SP).addImm(-StackSize); - - // Save the return address only if the function isnt a leaf one. - // sw $ra, stack_loc($sp) - if (MFI->adjustsStack()) { - BuildMI(MBB, MBBI, dl, TII.get(Mips::SW)) - .addReg(Mips::RA).addImm(RAOffset).addReg(Mips::SP); - } - - // if framepointer enabled, save it and set it - // to point to the stack pointer - if (hasFP(MF)) { - // sw $fp,stack_loc($sp) - BuildMI(MBB, MBBI, dl, TII.get(Mips::SW)) - .addReg(Mips::FP).addImm(FPOffset).addReg(Mips::SP); - - // move $fp, $sp - BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::FP) - .addReg(Mips::SP).addReg(Mips::ZERO); - } - - // Restore GP from the saved stack location - if (MipsFI->needGPSaveRestore()) - BuildMI(MBB, MBBI, dl, TII.get(Mips::CPRESTORE)) - .addImm(MipsFI->getGPStackOffset()); -} - -void MipsFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - MachineFrameInfo *MFI = MF.getFrameInfo(); - MipsFunctionInfo *MipsFI = MF.getInfo(); - const MipsInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - DebugLoc dl = MBBI->getDebugLoc(); - - // Get the number of bytes from FrameInfo - int NumBytes = (int) MFI->getStackSize(); - - // Get the FI's where RA and FP are saved. - int FPOffset = MipsFI->getFPStackOffset(); - int RAOffset = MipsFI->getRAStackOffset(); - - // if framepointer enabled, restore it and restore the - // stack pointer - if (hasFP(MF)) { - // move $sp, $fp - BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDu), Mips::SP) - .addReg(Mips::FP).addReg(Mips::ZERO); - - // lw $fp,stack_loc($sp) - BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::FP) - .addImm(FPOffset).addReg(Mips::SP); - } - - // Restore the return address only if the function isnt a leaf one. - // lw $ra, stack_loc($sp) - if (MFI->adjustsStack()) { - BuildMI(MBB, MBBI, dl, TII.get(Mips::LW), Mips::RA) - .addImm(RAOffset).addReg(Mips::SP); - } - - // adjust stack : insert addi sp, sp, (imm) - if (NumBytes) { - BuildMI(MBB, MBBI, dl, TII.get(Mips::ADDiu), Mips::SP) - .addReg(Mips::SP).addImm(NumBytes); - } -} Removed: llvm/trunk/lib/Target/Mips/MipsFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsFrameInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsFrameInfo.h (removed) @@ -1,46 +0,0 @@ -//====--- MipsFrameInfo.h - Define TargetFrameInfo for Mips --*- C++ -*---====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -// -//===----------------------------------------------------------------------===// - -#ifndef ALPHA_FRAMEINFO_H -#define ALPHA_FRAMEINFO_H - -#include "Mips.h" -#include "MipsSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" - -namespace llvm { - class MipsSubtarget; - -class MipsFrameInfo : public TargetFrameInfo { -protected: - const MipsSubtarget &STI; - -public: - explicit MipsFrameInfo(const MipsSubtarget &sti) - // FIXME: Is this correct at all? - : TargetFrameInfo(StackGrowsUp, 8, 0), STI(sti) { - } - - void adjustMipsStackFrame(MachineFunction &MF) const; - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool hasFP(const MachineFunction &MF) const; -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/Mips/MipsFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?p2=llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp&p1=llvm/trunk/lib/Target/Mips/MipsFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=======- MipsFrameInfo.cpp - Mips Frame Information ----------*- C++ -*-====// +//=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Mips implementation of TargetFrameInfo class. +// This file contains the Mips implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "MipsFrameInfo.h" +#include "MipsFrameLowering.h" #include "MipsInstrInfo.h" #include "MipsMachineFunction.h" #include "llvm/Function.h" @@ -82,16 +82,16 @@ // hasFP - Return true if the specified function should have a dedicated frame // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. -bool MipsFrameInfo::hasFP(const MachineFunction &MF) const { +bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects(); } -void MipsFrameInfo::adjustMipsStackFrame(MachineFunction &MF) const { +void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const { MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); const std::vector &CSI = MFI->getCalleeSavedInfo(); - unsigned StackAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned StackAlign = getStackAlignment(); unsigned RegSize = STI.isGP32bit() ? 4 : 8; bool HasGP = MipsFI->needGPSaveRestore(); @@ -203,7 +203,7 @@ MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset); } -void MipsFrameInfo::emitPrologue(MachineFunction &MF) const { +void MipsFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); @@ -264,7 +264,7 @@ .addImm(MipsFI->getGPStackOffset()); } -void MipsFrameInfo::emitEpilogue(MachineFunction &MF, +void MipsFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); MachineFrameInfo *MFI = MF.getFrameInfo(); Copied: llvm/trunk/lib/Target/Mips/MipsFrameLowering.h (from r123169, llvm/trunk/lib/Target/Mips/MipsFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.h?p2=llvm/trunk/lib/Target/Mips/MipsFrameLowering.h&p1=llvm/trunk/lib/Target/Mips/MipsFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsFrameInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//====--- MipsFrameInfo.h - Define TargetFrameInfo for Mips --*- C++ -*---====// +//==--- MipsFrameLowering.h - Define frame lowering for Mips --*- C++ -*---===// // // The LLVM Compiler Infrastructure // @@ -16,19 +16,19 @@ #include "Mips.h" #include "MipsSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class MipsSubtarget; -class MipsFrameInfo : public TargetFrameInfo { +class MipsFrameLowering : public TargetFrameLowering { protected: const MipsSubtarget &STI; public: - explicit MipsFrameInfo(const MipsSubtarget &sti) + explicit MipsFrameLowering(const MipsSubtarget &sti) // FIXME: Is this correct at all? - : TargetFrameInfo(StackGrowsUp, 8, 0), STI(sti) { + : TargetFrameLowering(StackGrowsUp, 8, 0), STI(sti) { } void adjustMipsStackFrame(MachineFunction &MF) const; Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -25,7 +25,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetInstrInfo.h" @@ -199,7 +199,7 @@ unsigned MipsRegisterInfo:: getFrameRegister(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); return TFI->hasFP(MF) ? Mips::FP : Mips::SP; } Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -41,7 +41,7 @@ DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-n32") : std::string("E-p:32:32:32-i8:8:32-i16:16:32-n32")), InstrInfo(*this), - FrameInfo(Subtarget), + FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this) { // Abicall enables PIC by default if (getRelocationModel() == Reloc::Default) { Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Mon Jan 10 06:39:04 2011 @@ -17,11 +17,11 @@ #include "MipsSubtarget.h" #include "MipsInstrInfo.h" #include "MipsISelLowering.h" -#include "MipsFrameInfo.h" +#include "MipsFrameLowering.h" #include "MipsSelectionDAGInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class formatted_raw_ostream; @@ -30,7 +30,7 @@ MipsSubtarget Subtarget; const TargetData DataLayout; // Calculates type size & alignment MipsInstrInfo InstrInfo; - MipsFrameInfo FrameInfo; + MipsFrameLowering FrameLowering; MipsTargetLowering TLInfo; MipsSelectionDAGInfo TSInfo; public: @@ -39,8 +39,8 @@ virtual const MipsInstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const TargetFrameInfo *getFrameInfo() const - { return &FrameInfo; } + virtual const TargetFrameLowering *getFrameLowering() const + { return &FrameLowering; } virtual const MipsSubtarget *getSubtargetImpl() const { return &Subtarget; } virtual const TargetData *getTargetData() const Removed: llvm/trunk/lib/Target/PTX/PTXFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXFrameInfo.cpp (removed) @@ -1,24 +0,0 @@ -//=======- PTXFrameInfo.cpp - PTX Frame Information -----------*- C++ -*-=====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the PTX implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#include "PTXFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" - -using namespace llvm; - -void PTXFrameInfo::emitPrologue(MachineFunction &MF) const { -} - -void PTXFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { -} Removed: llvm/trunk/lib/Target/PTX/PTXFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXFrameInfo.h (original) +++ llvm/trunk/lib/Target/PTX/PTXFrameInfo.h (removed) @@ -1,43 +0,0 @@ -//====---- PTXFrameInfo.h - Define TargetFrameInfo for PTX --*- C++ -*----====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -// -//===----------------------------------------------------------------------===// - -#ifndef PTX_FRAMEINFO_H -#define PTX_FRAMEINFO_H - -#include "PTX.h" -#include "PTXSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" - -namespace llvm { - class PTXSubtarget; - -class PTXFrameInfo : public TargetFrameInfo { -protected: - const PTXSubtarget &STI; - -public: - explicit PTXFrameInfo(const PTXSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 2, -2), STI(sti) { - } - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool hasFP(const MachineFunction &MF) const { return false; } -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/PTX/PTXFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/PTX/PTXFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXFrameLowering.cpp?p2=llvm/trunk/lib/Target/PTX/PTXFrameLowering.cpp&p1=llvm/trunk/lib/Target/PTX/PTXFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=======- PTXFrameInfo.cpp - PTX Frame Information -----------*- C++ -*-=====// +//=======- PTXFrameLowering.cpp - PTX Frame Information -------*- C++ -*-=====// // // The LLVM Compiler Infrastructure // @@ -7,18 +7,18 @@ // //===----------------------------------------------------------------------===// // -// This file contains the PTX implementation of TargetFrameInfo class. +// This file contains the PTX implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "PTXFrameInfo.h" +#include "PTXFrameLowering.h" #include "llvm/CodeGen/MachineFunction.h" using namespace llvm; -void PTXFrameInfo::emitPrologue(MachineFunction &MF) const { +void PTXFrameLowering::emitPrologue(MachineFunction &MF) const { } -void PTXFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { +void PTXFrameLowering::emitEpilogue(MachineFunction &MF, + MachineBasicBlock &MBB) const { } Copied: llvm/trunk/lib/Target/PTX/PTXFrameLowering.h (from r123169, llvm/trunk/lib/Target/PTX/PTXFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXFrameLowering.h?p2=llvm/trunk/lib/Target/PTX/PTXFrameLowering.h&p1=llvm/trunk/lib/Target/PTX/PTXFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXFrameInfo.h (original) +++ llvm/trunk/lib/Target/PTX/PTXFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//====---- PTXFrameInfo.h - Define TargetFrameInfo for PTX --*- C++ -*----====// +//===--- PTXFrameLowering.h - Define frame lowering for PTX --*- C++ -*----===// // // The LLVM Compiler Infrastructure // @@ -16,18 +16,18 @@ #include "PTX.h" #include "PTXSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class PTXSubtarget; -class PTXFrameInfo : public TargetFrameInfo { +class PTXFrameLowering : public TargetFrameLowering { protected: const PTXSubtarget &STI; public: - explicit PTXFrameInfo(const PTXSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 2, -2), STI(sti) { + explicit PTXFrameLowering(const PTXSubtarget &sti) + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 2, -2), STI(sti) { } /// emitProlog/emitEpilog - These methods insert prolog and epilog code into Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -34,13 +34,13 @@ TargetRegistry::RegisterAsmStreamer(ThePTXTarget, createPTXAsmStreamer); } -// DataLayout and FrameInfo are filled with dummy data +// DataLayout and FrameLowering are filled with dummy data PTXTargetMachine::PTXTargetMachine(const Target &T, const std::string &TT, const std::string &FS) : LLVMTargetMachine(T, TT), DataLayout("e-p:32:32-i64:32:32-f64:32:32-v128:32:128-v64:32:64-n32:64"), - FrameInfo(Subtarget), + FrameLowering(Subtarget), InstrInfo(*this), TLInfo(*this), Subtarget(TT, FS) { Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.h (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.h Mon Jan 10 06:39:04 2011 @@ -16,17 +16,17 @@ #include "PTXISelLowering.h" #include "PTXInstrInfo.h" -#include "PTXFrameInfo.h" +#include "PTXFrameLowering.h" #include "PTXSubtarget.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" namespace llvm { class PTXTargetMachine : public LLVMTargetMachine { private: const TargetData DataLayout; - PTXFrameInfo FrameInfo; + PTXFrameLowering FrameLowering; PTXInstrInfo InstrInfo; PTXTargetLowering TLInfo; PTXSubtarget Subtarget; @@ -37,7 +37,9 @@ virtual const TargetData *getTargetData() const { return &DataLayout; } - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const TargetFrameLowering *getFrameLowering() const { + return &FrameLowering; + } virtual const PTXInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetRegisterInfo *getRegisterInfo() const { Removed: llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.cpp (removed) @@ -1,970 +0,0 @@ -//=======- PPCFrameInfo.cpp - PPC Frame Information ------------*- C++ -*-====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the PPC implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#include "PPCFrameInfo.h" -#include "PPCInstrInfo.h" -#include "PPCMachineFunctionInfo.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/RegisterScavenging.h" -#include "llvm/Target/TargetOptions.h" - -using namespace llvm; - -// FIXME This disables some code that aligns the stack to a boundary bigger than -// the default (16 bytes on Darwin) when there is a stack local of greater -// alignment. This does not currently work, because the delta between old and -// new stack pointers is added to offsets that reference incoming parameters -// after the prolog is generated, and the code that does that doesn't handle a -// variable delta. You don't want to do that anyway; a better approach is to -// reserve another register that retains to the incoming stack pointer, and -// reference parameters relative to that. -#define ALIGN_STACK 0 - - -/// VRRegNo - Map from a numbered VR register to its enum value. -/// -static const unsigned short VRRegNo[] = { - PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , - PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, - PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, - PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 -}; - -/// RemoveVRSaveCode - We have found that this function does not need any code -/// to manipulate the VRSAVE register, even though it uses vector registers. -/// This can happen when the only registers used are known to be live in or out -/// of the function. Remove all of the VRSAVE related code from the function. -static void RemoveVRSaveCode(MachineInstr *MI) { - MachineBasicBlock *Entry = MI->getParent(); - MachineFunction *MF = Entry->getParent(); - - // We know that the MTVRSAVE instruction immediately follows MI. Remove it. - MachineBasicBlock::iterator MBBI = MI; - ++MBBI; - assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); - MBBI->eraseFromParent(); - - bool RemovedAllMTVRSAVEs = true; - // See if we can find and remove the MTVRSAVE instruction from all of the - // epilog blocks. - for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { - // If last instruction is a return instruction, add an epilogue - if (!I->empty() && I->back().getDesc().isReturn()) { - bool FoundIt = false; - for (MBBI = I->end(); MBBI != I->begin(); ) { - --MBBI; - if (MBBI->getOpcode() == PPC::MTVRSAVE) { - MBBI->eraseFromParent(); // remove it. - FoundIt = true; - break; - } - } - RemovedAllMTVRSAVEs &= FoundIt; - } - } - - // If we found and removed all MTVRSAVE instructions, remove the read of - // VRSAVE as well. - if (RemovedAllMTVRSAVEs) { - MBBI = MI; - assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); - --MBBI; - assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); - MBBI->eraseFromParent(); - } - - // Finally, nuke the UPDATE_VRSAVE. - MI->eraseFromParent(); -} - -// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the -// instruction selector. Based on the vector registers that have been used, -// transform this into the appropriate ORI instruction. -static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { - MachineFunction *MF = MI->getParent()->getParent(); - DebugLoc dl = MI->getDebugLoc(); - - unsigned UsedRegMask = 0; - for (unsigned i = 0; i != 32; ++i) - if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) - UsedRegMask |= 1 << (31-i); - - // Live in and live out values already must be in the mask, so don't bother - // marking them. - for (MachineRegisterInfo::livein_iterator - I = MF->getRegInfo().livein_begin(), - E = MF->getRegInfo().livein_end(); I != E; ++I) { - unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(I->first); - if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. - UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. - } - for (MachineRegisterInfo::liveout_iterator - I = MF->getRegInfo().liveout_begin(), - E = MF->getRegInfo().liveout_end(); I != E; ++I) { - unsigned RegNo = PPCRegisterInfo::getRegisterNumbering(*I); - if (VRRegNo[RegNo] == *I) // If this really is a vector reg. - UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. - } - - // If no registers are used, turn this into a copy. - if (UsedRegMask == 0) { - // Remove all VRSAVE code. - RemoveVRSaveCode(MI); - return; - } - - unsigned SrcReg = MI->getOperand(1).getReg(); - unsigned DstReg = MI->getOperand(0).getReg(); - - if ((UsedRegMask & 0xFFFF) == UsedRegMask) { - if (DstReg != SrcReg) - BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) - .addReg(SrcReg) - .addImm(UsedRegMask); - else - BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) - .addReg(SrcReg, RegState::Kill) - .addImm(UsedRegMask); - } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { - if (DstReg != SrcReg) - BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg) - .addImm(UsedRegMask >> 16); - else - BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg, RegState::Kill) - .addImm(UsedRegMask >> 16); - } else { - if (DstReg != SrcReg) - BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg) - .addImm(UsedRegMask >> 16); - else - BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) - .addReg(SrcReg, RegState::Kill) - .addImm(UsedRegMask >> 16); - - BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) - .addReg(DstReg, RegState::Kill) - .addImm(UsedRegMask & 0xFFFF); - } - - // Remove the old UPDATE_VRSAVE instruction. - MI->eraseFromParent(); -} - -/// determineFrameLayout - Determine the size of the frame and maximum call -/// frame size. -void PPCFrameInfo::determineFrameLayout(MachineFunction &MF) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - - // Get the number of bytes to allocate from the FrameInfo - unsigned FrameSize = MFI->getStackSize(); - - // Get the alignments provided by the target, and the maximum alignment - // (if any) of the fixed frame objects. - unsigned MaxAlign = MFI->getMaxAlignment(); - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - unsigned AlignMask = TargetAlign - 1; // - - // If we are a leaf function, and use up to 224 bytes of stack space, - // don't have a frame pointer, calls, or dynamic alloca then we do not need - // to adjust the stack pointer (we fit in the Red Zone). - bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone); - // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. - if (!DisableRedZone && - FrameSize <= 224 && // Fits in red zone. - !MFI->hasVarSizedObjects() && // No dynamic alloca. - !MFI->adjustsStack() && // No calls. - (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. - // No need for frame - MFI->setStackSize(0); - return; - } - - // Get the maximum call frame size of all the calls. - unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); - - // Maximum call frame needs to be at least big enough for linkage and 8 args. - unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), - Subtarget.isDarwinABI()); - maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); - - // If we have dynamic alloca then maxCallFrameSize needs to be aligned so - // that allocations will be aligned. - if (MFI->hasVarSizedObjects()) - maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; - - // Update maximum call frame size. - MFI->setMaxCallFrameSize(maxCallFrameSize); - - // Include call frame size in total. - FrameSize += maxCallFrameSize; - - // Make sure the frame is aligned. - FrameSize = (FrameSize + AlignMask) & ~AlignMask; - - // Update frame info. - MFI->setStackSize(FrameSize); -} - -// hasFP - Return true if the specified function actually has a dedicated frame -// pointer register. -bool PPCFrameInfo::hasFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - // FIXME: This is pretty much broken by design: hasFP() might be called really - // early, before the stack layout was calculated and thus hasFP() might return - // true or false here depending on the time of call. - return (MFI->getStackSize()) && needsFP(MF); -} - -// needsFP - Return true if the specified function should have a dedicated frame -// pointer register. This is true if the function has variable sized allocas or -// if frame pointer elimination is disabled. -bool PPCFrameInfo::needsFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - - // Naked functions have no stack frame pushed, so we don't have a frame - // pointer. - if (MF.getFunction()->hasFnAttr(Attribute::Naked)) - return false; - - return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() || - (GuaranteedTailCallOpt && MF.getInfo()->hasFastCall()); -} - - -void PPCFrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB - MachineBasicBlock::iterator MBBI = MBB.begin(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - const PPCInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - - MachineModuleInfo &MMI = MF.getMMI(); - DebugLoc dl; - bool needsFrameMoves = MMI.hasDebugInfo() || - !MF.getFunction()->doesNotThrow() || - UnwindTablesMandatory; - - // Prepare for frame info. - MCSymbol *FrameLabel = 0; - - // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, - // process it. - for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { - if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { - HandleVRSaveUpdate(MBBI, TII); - break; - } - } - - // Move MBBI back to the beginning of the function. - MBBI = MBB.begin(); - - // Work out frame sizes. - // FIXME: determineFrameLayout() may change the frame size. This should be - // moved upper, to some hook. - determineFrameLayout(MF); - unsigned FrameSize = MFI->getStackSize(); - - int NegFrameSize = -FrameSize; - - // Get processor type. - bool isPPC64 = Subtarget.isPPC64(); - // Get operating system - bool isDarwinABI = Subtarget.isDarwinABI(); - // Check if the link register (LR) must be saved. - PPCFunctionInfo *FI = MF.getInfo(); - bool MustSaveLR = FI->mustSaveLR(); - // Do we have a frame pointer for this function? - bool HasFP = hasFP(MF); - - int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); - - int FPOffset = 0; - if (HasFP) { - if (Subtarget.isSVR4ABI()) { - MachineFrameInfo *FFI = MF.getFrameInfo(); - int FPIndex = FI->getFramePointerSaveIndex(); - assert(FPIndex && "No Frame Pointer Save Slot!"); - FPOffset = FFI->getObjectOffset(FPIndex); - } else { - FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); - } - } - - if (isPPC64) { - if (MustSaveLR) - BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); - - if (HasFP) - BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) - .addReg(PPC::X31) - .addImm(FPOffset/4) - .addReg(PPC::X1); - - if (MustSaveLR) - BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) - .addReg(PPC::X0) - .addImm(LROffset / 4) - .addReg(PPC::X1); - } else { - if (MustSaveLR) - BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); - - if (HasFP) - BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) - .addReg(PPC::R31) - .addImm(FPOffset) - .addReg(PPC::R1); - - if (MustSaveLR) - BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) - .addReg(PPC::R0) - .addImm(LROffset) - .addReg(PPC::R1); - } - - // Skip if a leaf routine. - if (!FrameSize) return; - - // Get stack alignments. - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - unsigned MaxAlign = MFI->getMaxAlignment(); - - // Adjust stack pointer: r1 += NegFrameSize. - // If there is a preferred stack alignment, align R1 now - if (!isPPC64) { - // PPC32. - if (ALIGN_STACK && MaxAlign > TargetAlign) { - assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && - "Invalid alignment!"); - assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); - - BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) - .addReg(PPC::R1) - .addImm(0) - .addImm(32 - Log2_32(MaxAlign)) - .addImm(31); - BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) - .addReg(PPC::R0, RegState::Kill) - .addImm(NegFrameSize); - BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) - .addReg(PPC::R1) - .addReg(PPC::R1) - .addReg(PPC::R0); - } else if (isInt<16>(NegFrameSize)) { - BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) - .addReg(PPC::R1) - .addImm(NegFrameSize) - .addReg(PPC::R1); - } else { - BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) - .addImm(NegFrameSize >> 16); - BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) - .addReg(PPC::R0, RegState::Kill) - .addImm(NegFrameSize & 0xFFFF); - BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX)) - .addReg(PPC::R1) - .addReg(PPC::R1) - .addReg(PPC::R0); - } - } else { // PPC64. - if (ALIGN_STACK && MaxAlign > TargetAlign) { - assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && - "Invalid alignment!"); - assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); - - BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) - .addReg(PPC::X1) - .addImm(0) - .addImm(64 - Log2_32(MaxAlign)); - BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) - .addReg(PPC::X0) - .addImm(NegFrameSize); - BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) - .addReg(PPC::X1) - .addReg(PPC::X1) - .addReg(PPC::X0); - } else if (isInt<16>(NegFrameSize)) { - BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) - .addReg(PPC::X1) - .addImm(NegFrameSize / 4) - .addReg(PPC::X1); - } else { - BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) - .addImm(NegFrameSize >> 16); - BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) - .addReg(PPC::X0, RegState::Kill) - .addImm(NegFrameSize & 0xFFFF); - BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX)) - .addReg(PPC::X1) - .addReg(PPC::X1) - .addReg(PPC::X0); - } - } - - std::vector &Moves = MMI.getFrameMoves(); - - // Add the "machine moves" for the instructions we generated above, but in - // reverse order. - if (needsFrameMoves) { - // Mark effective beginning of when frame pointer becomes valid. - FrameLabel = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); - - // Show update of SP. - if (NegFrameSize) { - MachineLocation SPDst(MachineLocation::VirtualFP); - MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); - Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); - } else { - MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); - Moves.push_back(MachineMove(FrameLabel, SP, SP)); - } - - if (HasFP) { - MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); - MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); - Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); - } - - if (MustSaveLR) { - MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); - MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); - Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); - } - } - - MCSymbol *ReadyLabel = 0; - - // If there is a frame pointer, copy R1 into R31 - if (HasFP) { - if (!isPPC64) { - BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) - .addReg(PPC::R1) - .addReg(PPC::R1); - } else { - BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) - .addReg(PPC::X1) - .addReg(PPC::X1); - } - - if (needsFrameMoves) { - ReadyLabel = MMI.getContext().CreateTempSymbol(); - - // Mark effective beginning of when frame pointer is ready. - BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); - - MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : - (isPPC64 ? PPC::X1 : PPC::R1)); - MachineLocation FPSrc(MachineLocation::VirtualFP); - Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); - } - } - - if (needsFrameMoves) { - MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; - - // Add callee saved registers to move list. - const std::vector &CSI = MFI->getCalleeSavedInfo(); - for (unsigned I = 0, E = CSI.size(); I != E; ++I) { - int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); - unsigned Reg = CSI[I].getReg(); - if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; - MachineLocation CSDst(MachineLocation::VirtualFP, Offset); - MachineLocation CSSrc(Reg); - Moves.push_back(MachineMove(Label, CSDst, CSSrc)); - } - } -} - -void PPCFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - const PPCInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - - unsigned RetOpcode = MBBI->getOpcode(); - DebugLoc dl; - - assert((RetOpcode == PPC::BLR || - RetOpcode == PPC::TCRETURNri || - RetOpcode == PPC::TCRETURNdi || - RetOpcode == PPC::TCRETURNai || - RetOpcode == PPC::TCRETURNri8 || - RetOpcode == PPC::TCRETURNdi8 || - RetOpcode == PPC::TCRETURNai8) && - "Can only insert epilog into returning blocks"); - - // Get alignment info so we know how to restore r1 - const MachineFrameInfo *MFI = MF.getFrameInfo(); - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); - unsigned MaxAlign = MFI->getMaxAlignment(); - - // Get the number of bytes allocated from the FrameInfo. - int FrameSize = MFI->getStackSize(); - - // Get processor type. - bool isPPC64 = Subtarget.isPPC64(); - // Get operating system - bool isDarwinABI = Subtarget.isDarwinABI(); - // Check if the link register (LR) has been saved. - PPCFunctionInfo *FI = MF.getInfo(); - bool MustSaveLR = FI->mustSaveLR(); - // Do we have a frame pointer for this function? - bool HasFP = hasFP(MF); - - int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); - - int FPOffset = 0; - if (HasFP) { - if (Subtarget.isSVR4ABI()) { - MachineFrameInfo *FFI = MF.getFrameInfo(); - int FPIndex = FI->getFramePointerSaveIndex(); - assert(FPIndex && "No Frame Pointer Save Slot!"); - FPOffset = FFI->getObjectOffset(FPIndex); - } else { - FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); - } - } - - bool UsesTCRet = RetOpcode == PPC::TCRETURNri || - RetOpcode == PPC::TCRETURNdi || - RetOpcode == PPC::TCRETURNai || - RetOpcode == PPC::TCRETURNri8 || - RetOpcode == PPC::TCRETURNdi8 || - RetOpcode == PPC::TCRETURNai8; - - if (UsesTCRet) { - int MaxTCRetDelta = FI->getTailCallSPDelta(); - MachineOperand &StackAdjust = MBBI->getOperand(1); - assert(StackAdjust.isImm() && "Expecting immediate value."); - // Adjust stack pointer. - int StackAdj = StackAdjust.getImm(); - int Delta = StackAdj - MaxTCRetDelta; - assert((Delta >= 0) && "Delta must be positive"); - if (MaxTCRetDelta>0) - FrameSize += (StackAdj +Delta); - else - FrameSize += StackAdj; - } - - if (FrameSize) { - // The loaded (or persistent) stack pointer value is offset by the 'stwu' - // on entry to the function. Add this offset back now. - if (!isPPC64) { - // If this function contained a fastcc call and GuaranteedTailCallOpt is - // enabled (=> hasFastCall()==true) the fastcc call might contain a tail - // call which invalidates the stack pointer value in SP(0). So we use the - // value of R31 in this case. - if (FI->hasFastCall() && isInt<16>(FrameSize)) { - assert(hasFP(MF) && "Expecting a valid the frame pointer."); - BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) - .addReg(PPC::R31).addImm(FrameSize); - } else if(FI->hasFastCall()) { - BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) - .addImm(FrameSize >> 16); - BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) - .addReg(PPC::R0, RegState::Kill) - .addImm(FrameSize & 0xFFFF); - BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) - .addReg(PPC::R1) - .addReg(PPC::R31) - .addReg(PPC::R0); - } else if (isInt<16>(FrameSize) && - (!ALIGN_STACK || TargetAlign >= MaxAlign) && - !MFI->hasVarSizedObjects()) { - BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) - .addReg(PPC::R1).addImm(FrameSize); - } else { - BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) - .addImm(0).addReg(PPC::R1); - } - } else { - if (FI->hasFastCall() && isInt<16>(FrameSize)) { - assert(hasFP(MF) && "Expecting a valid the frame pointer."); - BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) - .addReg(PPC::X31).addImm(FrameSize); - } else if(FI->hasFastCall()) { - BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) - .addImm(FrameSize >> 16); - BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) - .addReg(PPC::X0, RegState::Kill) - .addImm(FrameSize & 0xFFFF); - BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) - .addReg(PPC::X1) - .addReg(PPC::X31) - .addReg(PPC::X0); - } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && - !MFI->hasVarSizedObjects()) { - BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) - .addReg(PPC::X1).addImm(FrameSize); - } else { - BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) - .addImm(0).addReg(PPC::X1); - } - } - } - - if (isPPC64) { - if (MustSaveLR) - BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) - .addImm(LROffset/4).addReg(PPC::X1); - - if (HasFP) - BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) - .addImm(FPOffset/4).addReg(PPC::X1); - - if (MustSaveLR) - BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); - } else { - if (MustSaveLR) - BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) - .addImm(LROffset).addReg(PPC::R1); - - if (HasFP) - BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) - .addImm(FPOffset).addReg(PPC::R1); - - if (MustSaveLR) - BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); - } - - // Callee pop calling convention. Pop parameter/linkage area. Used for tail - // call optimization - if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR && - MF.getFunction()->getCallingConv() == CallingConv::Fast) { - PPCFunctionInfo *FI = MF.getInfo(); - unsigned CallerAllocatedAmt = FI->getMinReservedArea(); - unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; - unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; - unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; - unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; - unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; - unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; - unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; - - if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { - BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) - .addReg(StackReg).addImm(CallerAllocatedAmt); - } else { - BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) - .addImm(CallerAllocatedAmt >> 16); - BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) - .addReg(TmpReg, RegState::Kill) - .addImm(CallerAllocatedAmt & 0xFFFF); - BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) - .addReg(StackReg) - .addReg(FPReg) - .addReg(TmpReg); - } - } else if (RetOpcode == PPC::TCRETURNdi) { - MBBI = prior(MBB.end()); - MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). - addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); - } else if (RetOpcode == PPC::TCRETURNri) { - MBBI = prior(MBB.end()); - assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); - BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); - } else if (RetOpcode == PPC::TCRETURNai) { - MBBI = prior(MBB.end()); - MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); - } else if (RetOpcode == PPC::TCRETURNdi8) { - MBBI = prior(MBB.end()); - MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). - addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); - } else if (RetOpcode == PPC::TCRETURNri8) { - MBBI = prior(MBB.end()); - assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); - BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); - } else if (RetOpcode == PPC::TCRETURNai8) { - MBBI = prior(MBB.end()); - MachineOperand &JumpTarget = MBBI->getOperand(0); - BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); - } -} - -void PPCFrameInfo::getInitialFrameState(std::vector &Moves) const { - // Initial state of the frame pointer is R1. - MachineLocation Dst(MachineLocation::VirtualFP); - MachineLocation Src(PPC::R1, 0); - Moves.push_back(MachineMove(0, Dst, Src)); -} - -static bool spillsCR(const MachineFunction &MF) { - const PPCFunctionInfo *FuncInfo = MF.getInfo(); - return FuncInfo->isCRSpilled(); -} - -/// MustSaveLR - Return true if this function requires that we save the LR -/// register onto the stack in the prolog and restore it in the epilog of the -/// function. -static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { - const PPCFunctionInfo *MFI = MF.getInfo(); - - // We need a save/restore of LR if there is any def of LR (which is - // defined by calls, including the PIC setup sequence), or if there is - // some use of the LR stack slot (e.g. for builtin_return_address). - // (LR comes in 32 and 64 bit versions.) - MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); - return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); -} - -void -PPCFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const { - const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); - - // Save and clear the LR state. - PPCFunctionInfo *FI = MF.getInfo(); - unsigned LR = RegInfo->getRARegister(); - FI->setMustSaveLR(MustSaveLR(MF, LR)); - MF.getRegInfo().setPhysRegUnused(LR); - - // Save R31 if necessary - int FPSI = FI->getFramePointerSaveIndex(); - bool isPPC64 = Subtarget.isPPC64(); - bool isDarwinABI = Subtarget.isDarwinABI(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - - // If the frame pointer save index hasn't been defined yet. - if (!FPSI && needsFP(MF)) { - // Find out what the fix offset of the frame pointer save area. - int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); - // Allocate the frame index for frame pointer save area. - FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); - // Save the result. - FI->setFramePointerSaveIndex(FPSI); - } - - // Reserve stack space to move the linkage area to in case of a tail call. - int TCSPDelta = 0; - if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) { - MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); - } - - // Reserve a slot closest to SP or frame pointer if we have a dynalloc or - // a large stack, which will require scavenging a register to materialize a - // large offset. - // FIXME: this doesn't actually check stack size, so is a bit pessimistic - // FIXME: doesn't detect whether or not we need to spill vXX, which requires - // r0 for now. - - if (RegInfo->requiresRegisterScavenging(MF)) // FIXME (64-bit): Enable. - if (needsFP(MF) || spillsCR(MF)) { - const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; - const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; - const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; - RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), - RC->getAlignment(), - false)); - } -} - -void PPCFrameInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) - const { - // Early exit if not using the SVR4 ABI. - if (!Subtarget.isSVR4ABI()) - return; - - // Get callee saved register information. - MachineFrameInfo *FFI = MF.getFrameInfo(); - const std::vector &CSI = FFI->getCalleeSavedInfo(); - - // Early exit if no callee saved registers are modified! - if (CSI.empty() && !needsFP(MF)) { - return; - } - - unsigned MinGPR = PPC::R31; - unsigned MinG8R = PPC::X31; - unsigned MinFPR = PPC::F31; - unsigned MinVR = PPC::V31; - - bool HasGPSaveArea = false; - bool HasG8SaveArea = false; - bool HasFPSaveArea = false; - bool HasCRSaveArea = false; - bool HasVRSAVESaveArea = false; - bool HasVRSaveArea = false; - - SmallVector GPRegs; - SmallVector G8Regs; - SmallVector FPRegs; - SmallVector VRegs; - - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - if (PPC::GPRCRegisterClass->contains(Reg)) { - HasGPSaveArea = true; - - GPRegs.push_back(CSI[i]); - - if (Reg < MinGPR) { - MinGPR = Reg; - } - } else if (PPC::G8RCRegisterClass->contains(Reg)) { - HasG8SaveArea = true; - - G8Regs.push_back(CSI[i]); - - if (Reg < MinG8R) { - MinG8R = Reg; - } - } else if (PPC::F8RCRegisterClass->contains(Reg)) { - HasFPSaveArea = true; - - FPRegs.push_back(CSI[i]); - - if (Reg < MinFPR) { - MinFPR = Reg; - } -// FIXME SVR4: Disable CR save area for now. - } else if (PPC::CRBITRCRegisterClass->contains(Reg) - || PPC::CRRCRegisterClass->contains(Reg)) { -// HasCRSaveArea = true; - } else if (PPC::VRSAVERCRegisterClass->contains(Reg)) { - HasVRSAVESaveArea = true; - } else if (PPC::VRRCRegisterClass->contains(Reg)) { - HasVRSaveArea = true; - - VRegs.push_back(CSI[i]); - - if (Reg < MinVR) { - MinVR = Reg; - } - } else { - llvm_unreachable("Unknown RegisterClass!"); - } - } - - PPCFunctionInfo *PFI = MF.getInfo(); - - int64_t LowerBound = 0; - - // Take into account stack space reserved for tail calls. - int TCSPDelta = 0; - if (GuaranteedTailCallOpt && (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { - LowerBound = TCSPDelta; - } - - // The Floating-point register save area is right below the back chain word - // of the previous stack frame. - if (HasFPSaveArea) { - for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { - int FI = FPRegs[i].getFrameIdx(); - - FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); - } - - LowerBound -= (31 - PPCRegisterInfo::getRegisterNumbering(MinFPR) + 1) * 8; - } - - // Check whether the frame pointer register is allocated. If so, make sure it - // is spilled to the correct offset. - if (needsFP(MF)) { - HasGPSaveArea = true; - - int FI = PFI->getFramePointerSaveIndex(); - assert(FI && "No Frame Pointer Save Slot!"); - - FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); - } - - // General register save area starts right below the Floating-point - // register save area. - if (HasGPSaveArea || HasG8SaveArea) { - // Move general register save area spill slots down, taking into account - // the size of the Floating-point register save area. - for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { - int FI = GPRegs[i].getFrameIdx(); - - FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); - } - - // Move general register save area spill slots down, taking into account - // the size of the Floating-point register save area. - for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { - int FI = G8Regs[i].getFrameIdx(); - - FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); - } - - unsigned MinReg = - std::min(PPCRegisterInfo::getRegisterNumbering(MinGPR), - PPCRegisterInfo::getRegisterNumbering(MinG8R)); - - if (Subtarget.isPPC64()) { - LowerBound -= (31 - MinReg + 1) * 8; - } else { - LowerBound -= (31 - MinReg + 1) * 4; - } - } - - // The CR save area is below the general register save area. - if (HasCRSaveArea) { - // FIXME SVR4: Is it actually possible to have multiple elements in CSI - // which have the CR/CRBIT register class? - // Adjust the frame index of the CR spill slot. - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - - if (PPC::CRBITRCRegisterClass->contains(Reg) || - PPC::CRRCRegisterClass->contains(Reg)) { - int FI = CSI[i].getFrameIdx(); - - FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); - } - } - - LowerBound -= 4; // The CR save area is always 4 bytes long. - } - - if (HasVRSAVESaveArea) { - // FIXME SVR4: Is it actually possible to have multiple elements in CSI - // which have the VRSAVE register class? - // Adjust the frame index of the VRSAVE spill slot. - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - - if (PPC::VRSAVERCRegisterClass->contains(Reg)) { - int FI = CSI[i].getFrameIdx(); - - FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); - } - } - - LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. - } - - if (HasVRSaveArea) { - // Insert alignment padding, we need 16-byte alignment. - LowerBound = (LowerBound - 15) & ~(15); - - for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { - int FI = VRegs[i].getFrameIdx(); - - FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); - } - } -} Removed: llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.h (removed) @@ -1,321 +0,0 @@ -//===-- PPCFrameInfo.h - Define TargetFrameInfo for PowerPC -----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -//===----------------------------------------------------------------------===// - -#ifndef POWERPC_FRAMEINFO_H -#define POWERPC_FRAMEINFO_H - -#include "PPC.h" -#include "PPCSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/ADT/STLExtras.h" - -namespace llvm { - class PPCSubtarget; - -class PPCFrameInfo: public TargetFrameInfo { - const PPCSubtarget &Subtarget; - -public: - PPCFrameInfo(const PPCSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), Subtarget(sti) { - } - - void determineFrameLayout(MachineFunction &MF) const; - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool hasFP(const MachineFunction &MF) const; - bool needsFP(const MachineFunction &MF) const; - void getInitialFrameState(std::vector &Moves) const; - - void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS = NULL) const; - void processFunctionBeforeFrameFinalized(MachineFunction &MF) const; - - /// targetHandlesStackFrameRounding - Returns true if the target is - /// responsible for rounding up the stack frame (probably at emitPrologue - /// time). - bool targetHandlesStackFrameRounding() const { return true; } - - /// getReturnSaveOffset - Return the previous frame offset to save the - /// return address. - static unsigned getReturnSaveOffset(bool isPPC64, bool isDarwinABI) { - if (isDarwinABI) - return isPPC64 ? 16 : 8; - // SVR4 ABI: - return isPPC64 ? 16 : 4; - } - - /// getFramePointerSaveOffset - Return the previous frame offset to save the - /// frame pointer. - static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) { - // For the Darwin ABI: - // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area - // for saving the frame pointer (if needed.) While the published ABI has - // not used this slot since at least MacOSX 10.2, there is older code - // around that does use it, and that needs to continue to work. - if (isDarwinABI) - return isPPC64 ? -8U : -4U; - - // SVR4 ABI: First slot in the general register save area. - return isPPC64 ? -8U : -4U; - } - - /// getLinkageSize - Return the size of the PowerPC ABI linkage area. - /// - static unsigned getLinkageSize(bool isPPC64, bool isDarwinABI) { - if (isDarwinABI || isPPC64) - return 6 * (isPPC64 ? 8 : 4); - - // SVR4 ABI: - return 8; - } - - /// getMinCallArgumentsSize - Return the size of the minium PowerPC ABI - /// argument area. - static unsigned getMinCallArgumentsSize(bool isPPC64, bool isDarwinABI) { - // For the Darwin ABI / 64-bit SVR4 ABI: - // The prolog code of the callee may store up to 8 GPR argument registers to - // the stack, allowing va_start to index over them in memory if its varargs. - // Because we cannot tell if this is needed on the caller side, we have to - // conservatively assume that it is needed. As such, make sure we have at - // least enough stack space for the caller to store the 8 GPRs. - if (isDarwinABI || isPPC64) - return 8 * (isPPC64 ? 8 : 4); - - // 32-bit SVR4 ABI: - // There is no default stack allocated for the 8 first GPR arguments. - return 0; - } - - /// getMinCallFrameSize - Return the minimum size a call frame can be using - /// the PowerPC ABI. - static unsigned getMinCallFrameSize(bool isPPC64, bool isDarwinABI) { - // The call frame needs to be at least big enough for linkage and 8 args. - return getLinkageSize(isPPC64, isDarwinABI) + - getMinCallArgumentsSize(isPPC64, isDarwinABI); - } - - // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. - const SpillSlot * - getCalleeSavedSpillSlots(unsigned &NumEntries) const { - if (Subtarget.isDarwinABI()) { - NumEntries = 1; - if (Subtarget.isPPC64()) { - static const SpillSlot darwin64Offsets = {PPC::X31, -8}; - return &darwin64Offsets; - } else { - static const SpillSlot darwinOffsets = {PPC::R31, -4}; - return &darwinOffsets; - } - } - - // Early exit if not using the SVR4 ABI. - if (!Subtarget.isSVR4ABI()) { - NumEntries = 0; - return 0; - } - - static const SpillSlot Offsets[] = { - // Floating-point register save area offsets. - {PPC::F31, -8}, - {PPC::F30, -16}, - {PPC::F29, -24}, - {PPC::F28, -32}, - {PPC::F27, -40}, - {PPC::F26, -48}, - {PPC::F25, -56}, - {PPC::F24, -64}, - {PPC::F23, -72}, - {PPC::F22, -80}, - {PPC::F21, -88}, - {PPC::F20, -96}, - {PPC::F19, -104}, - {PPC::F18, -112}, - {PPC::F17, -120}, - {PPC::F16, -128}, - {PPC::F15, -136}, - {PPC::F14, -144}, - - // General register save area offsets. - {PPC::R31, -4}, - {PPC::R30, -8}, - {PPC::R29, -12}, - {PPC::R28, -16}, - {PPC::R27, -20}, - {PPC::R26, -24}, - {PPC::R25, -28}, - {PPC::R24, -32}, - {PPC::R23, -36}, - {PPC::R22, -40}, - {PPC::R21, -44}, - {PPC::R20, -48}, - {PPC::R19, -52}, - {PPC::R18, -56}, - {PPC::R17, -60}, - {PPC::R16, -64}, - {PPC::R15, -68}, - {PPC::R14, -72}, - - // CR save area offset. - // FIXME SVR4: Disable CR save area for now. -// {PPC::CR2, -4}, -// {PPC::CR3, -4}, -// {PPC::CR4, -4}, -// {PPC::CR2LT, -4}, -// {PPC::CR2GT, -4}, -// {PPC::CR2EQ, -4}, -// {PPC::CR2UN, -4}, -// {PPC::CR3LT, -4}, -// {PPC::CR3GT, -4}, -// {PPC::CR3EQ, -4}, -// {PPC::CR3UN, -4}, -// {PPC::CR4LT, -4}, -// {PPC::CR4GT, -4}, -// {PPC::CR4EQ, -4}, -// {PPC::CR4UN, -4}, - - // VRSAVE save area offset. - {PPC::VRSAVE, -4}, - - // Vector register save area - {PPC::V31, -16}, - {PPC::V30, -32}, - {PPC::V29, -48}, - {PPC::V28, -64}, - {PPC::V27, -80}, - {PPC::V26, -96}, - {PPC::V25, -112}, - {PPC::V24, -128}, - {PPC::V23, -144}, - {PPC::V22, -160}, - {PPC::V21, -176}, - {PPC::V20, -192} - }; - - static const SpillSlot Offsets64[] = { - // Floating-point register save area offsets. - {PPC::F31, -8}, - {PPC::F30, -16}, - {PPC::F29, -24}, - {PPC::F28, -32}, - {PPC::F27, -40}, - {PPC::F26, -48}, - {PPC::F25, -56}, - {PPC::F24, -64}, - {PPC::F23, -72}, - {PPC::F22, -80}, - {PPC::F21, -88}, - {PPC::F20, -96}, - {PPC::F19, -104}, - {PPC::F18, -112}, - {PPC::F17, -120}, - {PPC::F16, -128}, - {PPC::F15, -136}, - {PPC::F14, -144}, - - // General register save area offsets. - // FIXME 64-bit SVR4: Are 32-bit registers actually allocated in 64-bit - // mode? - {PPC::R31, -4}, - {PPC::R30, -12}, - {PPC::R29, -20}, - {PPC::R28, -28}, - {PPC::R27, -36}, - {PPC::R26, -44}, - {PPC::R25, -52}, - {PPC::R24, -60}, - {PPC::R23, -68}, - {PPC::R22, -76}, - {PPC::R21, -84}, - {PPC::R20, -92}, - {PPC::R19, -100}, - {PPC::R18, -108}, - {PPC::R17, -116}, - {PPC::R16, -124}, - {PPC::R15, -132}, - {PPC::R14, -140}, - - {PPC::X31, -8}, - {PPC::X30, -16}, - {PPC::X29, -24}, - {PPC::X28, -32}, - {PPC::X27, -40}, - {PPC::X26, -48}, - {PPC::X25, -56}, - {PPC::X24, -64}, - {PPC::X23, -72}, - {PPC::X22, -80}, - {PPC::X21, -88}, - {PPC::X20, -96}, - {PPC::X19, -104}, - {PPC::X18, -112}, - {PPC::X17, -120}, - {PPC::X16, -128}, - {PPC::X15, -136}, - {PPC::X14, -144}, - - // CR save area offset. - // FIXME SVR4: Disable CR save area for now. -// {PPC::CR2, -4}, -// {PPC::CR3, -4}, -// {PPC::CR4, -4}, -// {PPC::CR2LT, -4}, -// {PPC::CR2GT, -4}, -// {PPC::CR2EQ, -4}, -// {PPC::CR2UN, -4}, -// {PPC::CR3LT, -4}, -// {PPC::CR3GT, -4}, -// {PPC::CR3EQ, -4}, -// {PPC::CR3UN, -4}, -// {PPC::CR4LT, -4}, -// {PPC::CR4GT, -4}, -// {PPC::CR4EQ, -4}, -// {PPC::CR4UN, -4}, - - // VRSAVE save area offset. - {PPC::VRSAVE, -4}, - - // Vector register save area - {PPC::V31, -16}, - {PPC::V30, -32}, - {PPC::V29, -48}, - {PPC::V28, -64}, - {PPC::V27, -80}, - {PPC::V26, -96}, - {PPC::V25, -112}, - {PPC::V24, -128}, - {PPC::V23, -144}, - {PPC::V22, -160}, - {PPC::V21, -176}, - {PPC::V20, -192} - }; - - if (Subtarget.isPPC64()) { - NumEntries = array_lengthof(Offsets64); - - return Offsets64; - } else { - NumEntries = array_lengthof(Offsets); - - return Offsets; - } - } -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?p2=llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp&p1=llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=======- PPCFrameInfo.cpp - PPC Frame Information ------------*- C++ -*-====// +//=====- PPCFrameLowering.cpp - PPC Frame Information -----------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file contains the PPC implementation of TargetFrameInfo class. +// This file contains the PPC implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "PPCFrameInfo.h" +#include "PPCFrameLowering.h" #include "PPCInstrInfo.h" #include "PPCMachineFunctionInfo.h" #include "llvm/Function.h" @@ -170,7 +170,7 @@ /// determineFrameLayout - Determine the size of the frame and maximum call /// frame size. -void PPCFrameInfo::determineFrameLayout(MachineFunction &MF) const { +void PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const { MachineFrameInfo *MFI = MF.getFrameInfo(); // Get the number of bytes to allocate from the FrameInfo @@ -179,7 +179,7 @@ // Get the alignments provided by the target, and the maximum alignment // (if any) of the fixed frame objects. unsigned MaxAlign = MFI->getMaxAlignment(); - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned TargetAlign = getStackAlignment(); unsigned AlignMask = TargetAlign - 1; // // If we are a leaf function, and use up to 224 bytes of stack space, @@ -225,7 +225,7 @@ // hasFP - Return true if the specified function actually has a dedicated frame // pointer register. -bool PPCFrameInfo::hasFP(const MachineFunction &MF) const { +bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); // FIXME: This is pretty much broken by design: hasFP() might be called really // early, before the stack layout was calculated and thus hasFP() might return @@ -236,7 +236,7 @@ // needsFP - Return true if the specified function should have a dedicated frame // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. -bool PPCFrameInfo::needsFP(const MachineFunction &MF) const { +bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); // Naked functions have no stack frame pushed, so we don't have a frame @@ -249,7 +249,7 @@ } -void PPCFrameInfo::emitPrologue(MachineFunction &MF) const { +void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -295,7 +295,7 @@ // Do we have a frame pointer for this function? bool HasFP = hasFP(MF); - int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); + int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); int FPOffset = 0; if (HasFP) { @@ -305,7 +305,7 @@ assert(FPIndex && "No Frame Pointer Save Slot!"); FPOffset = FFI->getObjectOffset(FPIndex); } else { - FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); + FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); } } @@ -345,7 +345,7 @@ if (!FrameSize) return; // Get stack alignments. - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned TargetAlign = getStackAlignment(); unsigned MaxAlign = MFI->getMaxAlignment(); // Adjust stack pointer: r1 += NegFrameSize. @@ -495,7 +495,7 @@ } } -void PPCFrameInfo::emitEpilogue(MachineFunction &MF, +void PPCFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); const PPCInstrInfo &TII = @@ -515,7 +515,7 @@ // Get alignment info so we know how to restore r1 const MachineFrameInfo *MFI = MF.getFrameInfo(); - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned TargetAlign = getStackAlignment(); unsigned MaxAlign = MFI->getMaxAlignment(); // Get the number of bytes allocated from the FrameInfo. @@ -531,7 +531,7 @@ // Do we have a frame pointer for this function? bool HasFP = hasFP(MF); - int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); + int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); int FPOffset = 0; if (HasFP) { @@ -541,7 +541,7 @@ assert(FPIndex && "No Frame Pointer Save Slot!"); FPOffset = FFI->getObjectOffset(FPIndex); } else { - FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); + FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); } } @@ -704,7 +704,7 @@ } } -void PPCFrameInfo::getInitialFrameState(std::vector &Moves) const { +void PPCFrameLowering::getInitialFrameState(std::vector &Moves) const { // Initial state of the frame pointer is R1. MachineLocation Dst(MachineLocation::VirtualFP); MachineLocation Src(PPC::R1, 0); @@ -731,7 +731,7 @@ } void -PPCFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, +PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); @@ -752,7 +752,7 @@ // Find out what the fix offset of the frame pointer save area. int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); // Allocate the frame index for frame pointer save area. - FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); + FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); // Save the result. FI->setFramePointerSaveIndex(FPSI); } @@ -760,7 +760,7 @@ // Reserve stack space to move the linkage area to in case of a tail call. int TCSPDelta = 0; if (GuaranteedTailCallOpt && (TCSPDelta = FI->getTailCallSPDelta()) < 0) { - MF.getFrameInfo()->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); + MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); } // Reserve a slot closest to SP or frame pointer if we have a dynalloc or @@ -781,7 +781,7 @@ } } -void PPCFrameInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) +void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF) const { // Early exit if not using the SVR4 ABI. if (!Subtarget.isSVR4ABI()) Copied: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.h (from r123169, llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.h?p2=llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.h&p1=llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCFrameInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===-- PPCFrameInfo.h - Define TargetFrameInfo for PowerPC -----*- C++ -*-===// +//==-- PPCFrameLowering.h - Define frame lowering for PowerPC ----*- C++ -*-==// // // The LLVM Compiler Infrastructure // @@ -15,19 +15,20 @@ #include "PPC.h" #include "PPCSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/ADT/STLExtras.h" namespace llvm { class PPCSubtarget; -class PPCFrameInfo: public TargetFrameInfo { +class PPCFrameLowering: public TargetFrameLowering { const PPCSubtarget &Subtarget; public: - PPCFrameInfo(const PPCSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 16, 0), Subtarget(sti) { + PPCFrameLowering(const PPCSubtarget &sti) + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 16, 0), + Subtarget(sti) { } void determineFrameLayout(MachineFunction &MF) const; Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1565,7 +1565,7 @@ *DAG.getContext()); // Reserve space for the linkage area on the stack. - CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); + CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4); @@ -1641,9 +1641,9 @@ MinReservedArea = std::max(MinReservedArea, - PPCFrameInfo::getMinCallFrameSize(false, false)); + PPCFrameLowering::getMinCallFrameSize(false, false)); - unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> + unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> getStackAlignment(); unsigned AlignMask = TargetAlign-1; MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; @@ -1749,7 +1749,7 @@ bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast)); unsigned PtrByteSize = isPPC64 ? 8 : 4; - unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); + unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); // Area that is at least reserved in caller of this function. unsigned MinReservedArea = ArgOffset; @@ -2041,8 +2041,8 @@ } MinReservedArea = std::max(MinReservedArea, - PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); - unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> + PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); + unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> getStackAlignment(); unsigned AlignMask = TargetAlign-1; MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask; @@ -2100,7 +2100,7 @@ // Count how many bytes are to be pushed on the stack, including the linkage // area, and parameter passing area. We start with 24/48 bytes, which is // prereserved space for [SP][CR][LR][3 x unused]. - unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true); + unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true); unsigned NumOps = Outs.size(); unsigned PtrByteSize = isPPC64 ? 8 : 4; @@ -2141,11 +2141,11 @@ // conservatively assume that it is needed. As such, make sure we have at // least enough stack space for the caller to store the 8 GPRs. NumBytes = std::max(NumBytes, - PPCFrameInfo::getMinCallFrameSize(isPPC64, true)); + PPCFrameLowering::getMinCallFrameSize(isPPC64, true)); // Tail call needs the stack to be aligned. if (CC==CallingConv::Fast && GuaranteedTailCallOpt) { - unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()-> + unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()-> getStackAlignment(); unsigned AlignMask = TargetAlign-1; NumBytes = (NumBytes + AlignMask) & ~AlignMask; @@ -2269,7 +2269,7 @@ if (SPDiff) { // Calculate the new stack slot for the return address. int SlotSize = isPPC64 ? 8 : 4; - int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64, + int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewRetAddrLoc, true); @@ -2283,7 +2283,7 @@ // slot as the FP is never overwritten. if (isDarwinABI) { int NewFPLoc = - SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); + SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc, true); SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT); @@ -2760,7 +2760,7 @@ ArgLocs, *DAG.getContext()); // Reserve space for the linkage area on the stack. - CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize); + CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize); if (isVarArg) { // Handle fixed and variable vector arguments differently. @@ -2997,7 +2997,7 @@ // memory. Also, if this is a vararg function, floating point operations // must be stored to our stack, and loaded into integer regs as well, if // any integer regs are available for argument passing. - unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true); + unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true); unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0; static const unsigned GPR_32[] = { // 32-bit registers. @@ -3379,7 +3379,7 @@ // If the frame pointer save index hasn't been defined yet. if (!RASI) { // Find out what the fix offset of the frame pointer save area. - int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI); + int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); // Allocate the frame index for frame pointer save area. RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true); // Save the result. @@ -3403,7 +3403,7 @@ // If the frame pointer save index hasn't been defined yet. if (!FPSI) { // Find out what the fix offset of the frame pointer save area. - int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, + int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); // Allocate the frame index for frame pointer save area. @@ -5567,7 +5567,7 @@ SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); SDValue Offset = - DAG.getConstant(PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI), + DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI), isPPC64? MVT::i64 : MVT::i32); return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), DAG.getNode(ISD::ADD, dl, getPointerTy(), Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -17,7 +17,7 @@ #include "PPCInstrBuilder.h" #include "PPCMachineFunctionInfo.h" #include "PPCRegisterInfo.h" -#include "PPCFrameInfo.h" +#include "PPCFrameLowering.h" #include "PPCSubtarget.h" #include "llvm/CallingConv.h" #include "llvm/Constants.h" @@ -31,7 +31,7 @@ #include "llvm/CodeGen/MachineLocation.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -258,8 +258,8 @@ BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - const PPCFrameInfo *PPCFI = - static_cast(MF.getTarget().getFrameInfo()); + const PPCFrameLowering *PPCFI = + static_cast(MF.getTarget().getFrameLowering()); Reserved.set(PPC::R0); Reserved.set(PPC::R1); @@ -395,7 +395,7 @@ unsigned FrameSize = MFI->getStackSize(); // Get stack alignments. - unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned TargetAlign = MF.getTarget().getFrameLowering()->getStackAlignment(); unsigned MaxAlign = MFI->getMaxAlignment(); if (MaxAlign > TargetAlign) report_fatal_error("Dynamic alloca with large aligns not supported"); @@ -541,7 +541,7 @@ MachineFunction &MF = *MBB.getParent(); // Get the frame info. MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); DebugLoc dl = MI.getDebugLoc(); // Find out which operand is the frame index. @@ -670,7 +670,7 @@ } unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (!Subtarget.isPPC64()) return TFI->hasFP(MF) ? PPC::R31 : PPC::R1; Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Mon Jan 10 06:39:04 2011 @@ -301,8 +301,8 @@ // When using the 32-bit SVR4 ABI, r13 is reserved for the Small Data Area // pointer. const PPCSubtarget &Subtarget = MF.getTarget().getSubtarget(); - const PPCFrameInfo *PPCFI = - static_cast(MF.getTarget().getFrameInfo()); + const PPCFrameLowering *PPCFI = + static_cast(MF.getTarget().getFrameLowering()); if (Subtarget.isPPC64() || Subtarget.isSVR4ABI()) return end()-5; // don't allocate R13, R31, R0, R1, LR @@ -332,8 +332,8 @@ } G8RCClass::iterator G8RCClass::allocation_order_end(const MachineFunction &MF) const { - const PPCFrameInfo *PPCFI = - static_cast(MF.getTarget().getFrameInfo()); + const PPCFrameLowering *PPCFI = + static_cast(MF.getTarget().getFrameLowering()); if (PPCFI->needsFP(MF)) return end()-5; else Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -72,7 +72,7 @@ : LLVMTargetMachine(T, TT), Subtarget(TT, FS, is64Bit), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), - FrameInfo(Subtarget), JITInfo(*this, is64Bit), + FrameLowering(Subtarget), JITInfo(*this, is64Bit), TLInfo(*this), TSInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) { Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Mon Jan 10 06:39:04 2011 @@ -14,7 +14,7 @@ #ifndef PPC_TARGETMACHINE_H #define PPC_TARGETMACHINE_H -#include "PPCFrameInfo.h" +#include "PPCFrameLowering.h" #include "PPCSubtarget.h" #include "PPCJITInfo.h" #include "PPCInstrInfo.h" @@ -33,7 +33,7 @@ PPCSubtarget Subtarget; const TargetData DataLayout; // Calculates type size & alignment PPCInstrInfo InstrInfo; - PPCFrameInfo FrameInfo; + PPCFrameLowering FrameLowering; PPCJITInfo JITInfo; PPCTargetLowering TLInfo; PPCSelectionDAGInfo TSInfo; @@ -43,16 +43,18 @@ PPCTargetMachine(const Target &T, const std::string &TT, const std::string &FS, bool is64Bit); - virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const PPCFrameInfo *getFrameInfo() const { return &FrameInfo; } - virtual PPCJITInfo *getJITInfo() { return &JITInfo; } + virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; } + virtual const PPCFrameLowering *getFrameLowering() const { + return &FrameLowering; + } + virtual PPCJITInfo *getJITInfo() { return &JITInfo; } virtual const PPCTargetLowering *getTargetLowering() const { return &TLInfo; } virtual const PPCSelectionDAGInfo* getSelectionDAGInfo() const { return &TSInfo; } - virtual const PPCRegisterInfo *getRegisterInfo() const { + virtual const PPCRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); } Removed: llvm/trunk/lib/Target/Sparc/SparcFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcFrameInfo.cpp (removed) @@ -1,80 +0,0 @@ -//=======- SparcFrameInfo.cpp - Sparc Frame Information --------*- C++ -*-====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the Sparc implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#include "SparcFrameInfo.h" -#include "SparcInstrInfo.h" -#include "SparcMachineFunctionInfo.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Support/CommandLine.h" - -using namespace llvm; - -void SparcFrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - const SparcInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - MachineBasicBlock::iterator MBBI = MBB.begin(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - // Get the number of bytes to allocate from the FrameInfo - int NumBytes = (int) MFI->getStackSize(); - - // Emit the correct save instruction based on the number of bytes in - // the frame. Minimum stack frame size according to V8 ABI is: - // 16 words for register window spill - // 1 word for address of returned aggregate-value - // + 6 words for passing parameters on the stack - // ---------- - // 23 words * 4 bytes per word = 92 bytes - NumBytes += 92; - - // Round up to next doubleword boundary -- a double-word boundary - // is required by the ABI. - NumBytes = (NumBytes + 7) & ~7; - NumBytes = -NumBytes; - - if (NumBytes >= -4096) { - BuildMI(MBB, MBBI, dl, TII.get(SP::SAVEri), SP::O6) - .addReg(SP::O6).addImm(NumBytes); - } else { - // Emit this the hard way. This clobbers G1 which we always know is - // available here. - unsigned OffHi = (unsigned)NumBytes >> 10U; - BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi); - // Emit G1 = G1 + I6 - BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1) - .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1)); - BuildMI(MBB, MBBI, dl, TII.get(SP::SAVErr), SP::O6) - .addReg(SP::O6).addReg(SP::G1); - } -} - -void SparcFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - const SparcInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - DebugLoc dl = MBBI->getDebugLoc(); - assert(MBBI->getOpcode() == SP::RETL && - "Can only put epilog before 'retl' instruction!"); - BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0) - .addReg(SP::G0); -} Removed: llvm/trunk/lib/Target/Sparc/SparcFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcFrameInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcFrameInfo.h (removed) @@ -1,41 +0,0 @@ -//===--- SparcFrameInfo.h - Define TargetFrameInfo for Sparc --*- C++ -*---===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -// -//===----------------------------------------------------------------------===// - -#ifndef SPARC_FRAMEINFO_H -#define SPARC_FRAMEINFO_H - -#include "Sparc.h" -#include "SparcSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" - -namespace llvm { - class SparcSubtarget; - -class SparcFrameInfo : public TargetFrameInfo { - const SparcSubtarget &STI; -public: - explicit SparcFrameInfo(const SparcSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), STI(sti) { - } - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool hasFP(const MachineFunction &MF) const { return false; } -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/Sparc/SparcFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp?p2=llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp&p1=llvm/trunk/lib/Target/Sparc/SparcFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=======- SparcFrameInfo.cpp - Sparc Frame Information --------*- C++ -*-====// +//====- SparcFrameLowering.cpp - Sparc Frame Information -------*- C++ -*-====// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file contains the Sparc implementation of TargetFrameInfo class. +// This file contains the Sparc implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "SparcFrameInfo.h" +#include "SparcFrameLowering.h" #include "SparcInstrInfo.h" #include "SparcMachineFunctionInfo.h" #include "llvm/Function.h" @@ -26,7 +26,7 @@ using namespace llvm; -void SparcFrameInfo::emitPrologue(MachineFunction &MF) const { +void SparcFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); MachineFrameInfo *MFI = MF.getFrameInfo(); const SparcInstrInfo &TII = @@ -67,7 +67,7 @@ } } -void SparcFrameInfo::emitEpilogue(MachineFunction &MF, +void SparcFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); const SparcInstrInfo &TII = Copied: llvm/trunk/lib/Target/Sparc/SparcFrameLowering.h (from r123169, llvm/trunk/lib/Target/Sparc/SparcFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcFrameLowering.h?p2=llvm/trunk/lib/Target/Sparc/SparcFrameLowering.h&p1=llvm/trunk/lib/Target/Sparc/SparcFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcFrameInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===--- SparcFrameInfo.h - Define TargetFrameInfo for Sparc --*- C++ -*---===// +//===- SparcFrameLowering.h - Define frame lowering for Sparc --*- C++ -*--===// // // The LLVM Compiler Infrastructure // @@ -16,16 +16,16 @@ #include "Sparc.h" #include "SparcSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class SparcSubtarget; -class SparcFrameInfo : public TargetFrameInfo { +class SparcFrameLowering : public TargetFrameLowering { const SparcSubtarget &STI; public: - explicit SparcFrameInfo(const SparcSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), STI(sti) { + explicit SparcFrameLowering(const SparcSubtarget &sti) + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8, 0), STI(sti) { } /// emitProlog/emitEpilog - These methods insert prolog and epilog code into Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -35,7 +35,7 @@ Subtarget(TT, FS, is64bit), DataLayout(Subtarget.getDataLayout()), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), - FrameInfo(Subtarget) { + FrameLowering(Subtarget) { } bool SparcTargetMachine::addInstSelector(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Mon Jan 10 06:39:04 2011 @@ -16,12 +16,12 @@ #include "SparcInstrInfo.h" #include "SparcISelLowering.h" -#include "SparcFrameInfo.h" +#include "SparcFrameLowering.h" #include "SparcSelectionDAGInfo.h" #include "SparcSubtarget.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { @@ -31,13 +31,15 @@ SparcTargetLowering TLInfo; SparcSelectionDAGInfo TSInfo; SparcInstrInfo InstrInfo; - SparcFrameInfo FrameInfo; + SparcFrameLowering FrameLowering; public: SparcTargetMachine(const Target &T, const std::string &TT, const std::string &FS, bool is64bit); virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const TargetFrameLowering *getFrameLowering() const { + return &FrameLowering; + } virtual const SparcSubtarget *getSubtargetImpl() const{ return &Subtarget; } virtual const SparcRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); Removed: llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.cpp (removed) @@ -1,388 +0,0 @@ -//=====- SystemZFrameInfo.cpp - SystemZ Frame Information ------*- C++ -*-====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the SystemZ implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#include "SystemZFrameInfo.h" -#include "SystemZInstrBuilder.h" -#include "SystemZInstrInfo.h" -#include "SystemZMachineFunctionInfo.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Support/CommandLine.h" - -using namespace llvm; - -SystemZFrameInfo::SystemZFrameInfo(const SystemZSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 8, -160), STI(sti) { - // Fill the spill offsets map - static const unsigned SpillOffsTab[][2] = { - { SystemZ::R2D, 0x10 }, - { SystemZ::R3D, 0x18 }, - { SystemZ::R4D, 0x20 }, - { SystemZ::R5D, 0x28 }, - { SystemZ::R6D, 0x30 }, - { SystemZ::R7D, 0x38 }, - { SystemZ::R8D, 0x40 }, - { SystemZ::R9D, 0x48 }, - { SystemZ::R10D, 0x50 }, - { SystemZ::R11D, 0x58 }, - { SystemZ::R12D, 0x60 }, - { SystemZ::R13D, 0x68 }, - { SystemZ::R14D, 0x70 }, - { SystemZ::R15D, 0x78 } - }; - - RegSpillOffsets.grow(SystemZ::NUM_TARGET_REGS); - - for (unsigned i = 0, e = array_lengthof(SpillOffsTab); i != e; ++i) - RegSpillOffsets[SpillOffsTab[i][0]] = SpillOffsTab[i][1]; -} - -/// needsFP - Return true if the specified function should have a dedicated -/// frame pointer register. This is true if the function has variable sized -/// allocas or if frame pointer elimination is disabled. -bool SystemZFrameInfo::hasFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects(); -} - -/// emitSPUpdate - Emit a series of instructions to increment / decrement the -/// stack pointer by a constant value. -static -void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - int64_t NumBytes, const TargetInstrInfo &TII) { - unsigned Opc; uint64_t Chunk; - bool isSub = NumBytes < 0; - uint64_t Offset = isSub ? -NumBytes : NumBytes; - - if (Offset >= (1LL << 15) - 1) { - Opc = SystemZ::ADD64ri32; - Chunk = (1LL << 31) - 1; - } else { - Opc = SystemZ::ADD64ri16; - Chunk = (1LL << 15) - 1; - } - - DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - while (Offset) { - uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; - MachineInstr *MI = - BuildMI(MBB, MBBI, DL, TII.get(Opc), SystemZ::R15D) - .addReg(SystemZ::R15D).addImm(isSub ? -ThisVal : ThisVal); - // The PSW implicit def is dead. - MI->getOperand(3).setIsDead(); - Offset -= ThisVal; - } -} - -void SystemZFrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - const SystemZInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - SystemZMachineFunctionInfo *SystemZMFI = - MF.getInfo(); - MachineBasicBlock::iterator MBBI = MBB.begin(); - DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - // Get the number of bytes to allocate from the FrameInfo. - // Note that area for callee-saved stuff is already allocated, thus we need to - // 'undo' the stack movement. - uint64_t StackSize = MFI->getStackSize(); - StackSize -= SystemZMFI->getCalleeSavedFrameSize(); - - uint64_t NumBytes = StackSize - TFI.getOffsetOfLocalArea(); - - // Skip the callee-saved push instructions. - while (MBBI != MBB.end() && - (MBBI->getOpcode() == SystemZ::MOV64mr || - MBBI->getOpcode() == SystemZ::MOV64mrm)) - ++MBBI; - - if (MBBI != MBB.end()) - DL = MBBI->getDebugLoc(); - - // adjust stack pointer: R15 -= numbytes - if (StackSize || MFI->hasCalls()) { - assert(MF.getRegInfo().isPhysRegUsed(SystemZ::R15D) && - "Invalid stack frame calculation!"); - emitSPUpdate(MBB, MBBI, -(int64_t)NumBytes, TII); - } - - if (hasFP(MF)) { - // Update R11 with the new base value... - BuildMI(MBB, MBBI, DL, TII.get(SystemZ::MOV64rr), SystemZ::R11D) - .addReg(SystemZ::R15D); - - // Mark the FramePtr as live-in in every block except the entry. - for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end(); - I != E; ++I) - I->addLiveIn(SystemZ::R11D); - - } -} - -void SystemZFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - const SystemZInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - SystemZMachineFunctionInfo *SystemZMFI = - MF.getInfo(); - unsigned RetOpcode = MBBI->getOpcode(); - - switch (RetOpcode) { - case SystemZ::RET: break; // These are ok - default: - assert(0 && "Can only insert epilog into returning blocks"); - } - - // Get the number of bytes to allocate from the FrameInfo - // Note that area for callee-saved stuff is already allocated, thus we need to - // 'undo' the stack movement. - uint64_t StackSize = - MFI->getStackSize() - SystemZMFI->getCalleeSavedFrameSize(); - uint64_t NumBytes = StackSize - TFI.getOffsetOfLocalArea(); - - // Skip the final terminator instruction. - while (MBBI != MBB.begin()) { - MachineBasicBlock::iterator PI = prior(MBBI); - --MBBI; - if (!PI->getDesc().isTerminator()) - break; - } - - // During callee-saved restores emission stack frame was not yet finialized - // (and thus - the stack size was unknown). Tune the offset having full stack - // size in hands. - if (StackSize || MFI->hasCalls()) { - assert((MBBI->getOpcode() == SystemZ::MOV64rmm || - MBBI->getOpcode() == SystemZ::MOV64rm) && - "Expected to see callee-save register restore code"); - assert(MF.getRegInfo().isPhysRegUsed(SystemZ::R15D) && - "Invalid stack frame calculation!"); - - unsigned i = 0; - MachineInstr &MI = *MBBI; - while (!MI.getOperand(i).isImm()) { - ++i; - assert(i < MI.getNumOperands() && "Unexpected restore code!"); - } - - uint64_t Offset = NumBytes + MI.getOperand(i).getImm(); - // If Offset does not fit into 20-bit signed displacement field we need to - // emit some additional code... - if (Offset > 524287) { - // Fold the displacement into load instruction as much as possible. - NumBytes = Offset - 524287; - Offset = 524287; - emitSPUpdate(MBB, MBBI, NumBytes, TII); - } - - MI.getOperand(i).ChangeToImmediate(Offset); - } -} - -int SystemZFrameInfo::getFrameIndexOffset(const MachineFunction &MF, - int FI) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - const SystemZMachineFunctionInfo *SystemZMFI = - MF.getInfo(); - int Offset = MFI->getObjectOffset(FI) + MFI->getOffsetAdjustment(); - uint64_t StackSize = MFI->getStackSize(); - - // Fixed objects are really located in the "previous" frame. - if (FI < 0) - StackSize -= SystemZMFI->getCalleeSavedFrameSize(); - - Offset += StackSize - getOffsetOfLocalArea(); - - // Skip the register save area if we generated the stack frame. - if (StackSize || MFI->hasCalls()) - Offset -= getOffsetOfLocalArea(); - - return Offset; -} - -bool -SystemZFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - DebugLoc DL; - if (MI != MBB.end()) DL = MI->getDebugLoc(); - - MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - SystemZMachineFunctionInfo *MFI = MF.getInfo(); - unsigned CalleeFrameSize = 0; - - // Scan the callee-saved and find the bounds of register spill area. - unsigned LowReg = 0, HighReg = 0, StartOffset = -1U, EndOffset = 0; - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - if (!SystemZ::FP64RegClass.contains(Reg)) { - unsigned Offset = RegSpillOffsets[Reg]; - CalleeFrameSize += 8; - if (StartOffset > Offset) { - LowReg = Reg; StartOffset = Offset; - } - if (EndOffset < Offset) { - HighReg = Reg; EndOffset = RegSpillOffsets[Reg]; - } - } - } - - // Save information for epilogue inserter. - MFI->setCalleeSavedFrameSize(CalleeFrameSize); - MFI->setLowReg(LowReg); MFI->setHighReg(HighReg); - - // Save GPRs - if (StartOffset) { - // Build a store instruction. Use STORE MULTIPLE instruction if there are many - // registers to store, otherwise - just STORE. - MachineInstrBuilder MIB = - BuildMI(MBB, MI, DL, TII.get((LowReg == HighReg ? - SystemZ::MOV64mr : SystemZ::MOV64mrm))); - - // Add store operands. - MIB.addReg(SystemZ::R15D).addImm(StartOffset); - if (LowReg == HighReg) - MIB.addReg(0); - MIB.addReg(LowReg, RegState::Kill); - if (LowReg != HighReg) - MIB.addReg(HighReg, RegState::Kill); - - // Do a second scan adding regs as being killed by instruction - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - // Add the callee-saved register as live-in. It's killed at the spill. - MBB.addLiveIn(Reg); - if (Reg != LowReg && Reg != HighReg) - MIB.addReg(Reg, RegState::ImplicitKill); - } - } - - // Save FPRs - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - if (SystemZ::FP64RegClass.contains(Reg)) { - MBB.addLiveIn(Reg); - TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i].getFrameIdx(), - &SystemZ::FP64RegClass, TRI); - } - } - - return true; -} - -bool -SystemZFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - DebugLoc DL; - if (MI != MBB.end()) DL = MI->getDebugLoc(); - - MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - SystemZMachineFunctionInfo *MFI = MF.getInfo(); - - // Restore FP registers - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - if (SystemZ::FP64RegClass.contains(Reg)) - TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), - &SystemZ::FP64RegClass, TRI); - } - - // Restore GP registers - unsigned LowReg = MFI->getLowReg(), HighReg = MFI->getHighReg(); - unsigned StartOffset = RegSpillOffsets[LowReg]; - - if (StartOffset) { - // Build a load instruction. Use LOAD MULTIPLE instruction if there are many - // registers to load, otherwise - just LOAD. - MachineInstrBuilder MIB = - BuildMI(MBB, MI, DL, TII.get((LowReg == HighReg ? - SystemZ::MOV64rm : SystemZ::MOV64rmm))); - // Add store operands. - MIB.addReg(LowReg, RegState::Define); - if (LowReg != HighReg) - MIB.addReg(HighReg, RegState::Define); - - MIB.addReg(hasFP(MF) ? SystemZ::R11D : SystemZ::R15D); - MIB.addImm(StartOffset); - if (LowReg == HighReg) - MIB.addReg(0); - - // Do a second scan adding regs as being defined by instruction - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - if (Reg != LowReg && Reg != HighReg) - MIB.addReg(Reg, RegState::ImplicitDefine); - } - } - - return true; -} - -void -SystemZFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const { - // Determine whether R15/R14 will ever be clobbered inside the function. And - // if yes - mark it as 'callee' saved. - MachineFrameInfo *FFI = MF.getFrameInfo(); - MachineRegisterInfo &MRI = MF.getRegInfo(); - - // Check whether high FPRs are ever used, if yes - we need to save R15 as - // well. - static const unsigned HighFPRs[] = { - SystemZ::F8L, SystemZ::F9L, SystemZ::F10L, SystemZ::F11L, - SystemZ::F12L, SystemZ::F13L, SystemZ::F14L, SystemZ::F15L, - SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S, - SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S, - }; - - bool HighFPRsUsed = false; - for (unsigned i = 0, e = array_lengthof(HighFPRs); i != e; ++i) - HighFPRsUsed |= MRI.isPhysRegUsed(HighFPRs[i]); - - if (FFI->hasCalls()) - /* FIXME: function is varargs */ - /* FIXME: function grabs RA */ - /* FIXME: function calls eh_return */ - MRI.setPhysRegUsed(SystemZ::R14D); - - if (HighFPRsUsed || - FFI->hasCalls() || - FFI->getObjectIndexEnd() != 0 || // Contains automatic variables - FFI->hasVarSizedObjects() // Function calls dynamic alloca's - /* FIXME: function is varargs */) - MRI.setPhysRegUsed(SystemZ::R15D); -} Removed: llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.h (removed) @@ -1,57 +0,0 @@ -//==- SystemZFrameInfo.h - Define TargetFrameInfo for z/System --*- C++ -*--==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -// -//===----------------------------------------------------------------------===// - -#ifndef SYSTEMZ_FRAMEINFO_H -#define SYSTEMZ_FRAMEINFO_H - -#include "SystemZ.h" -#include "SystemZSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" -#include "llvm/ADT/IndexedMap.h" - -namespace llvm { - class SystemZSubtarget; - -class SystemZFrameInfo : public TargetFrameInfo { - IndexedMap RegSpillOffsets; -protected: - const SystemZSubtarget &STI; - -public: - explicit SystemZFrameInfo(const SystemZSubtarget &sti); - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - - void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const; - - bool hasReservedCallFrame(const MachineFunction &MF) const { return true; } - bool hasFP(const MachineFunction &MF) const; - int getFrameIndexOffset(const MachineFunction &MF, int FI) const; -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp?p2=llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp&p1=llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=====- SystemZFrameInfo.cpp - SystemZ Frame Information ------*- C++ -*-====// +//=====- SystemZFrameLowering.cpp - SystemZ Frame Information ------*- C++ -*-====// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file contains the SystemZ implementation of TargetFrameInfo class. +// This file contains the SystemZ implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "SystemZFrameInfo.h" +#include "SystemZFrameLowering.h" #include "SystemZInstrBuilder.h" #include "SystemZInstrInfo.h" #include "SystemZMachineFunctionInfo.h" @@ -27,8 +27,8 @@ using namespace llvm; -SystemZFrameInfo::SystemZFrameInfo(const SystemZSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 8, -160), STI(sti) { +SystemZFrameLowering::SystemZFrameLowering(const SystemZSubtarget &sti) + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8, -160), STI(sti) { // Fill the spill offsets map static const unsigned SpillOffsTab[][2] = { { SystemZ::R2D, 0x10 }, @@ -56,7 +56,7 @@ /// needsFP - Return true if the specified function should have a dedicated /// frame pointer register. This is true if the function has variable sized /// allocas or if frame pointer elimination is disabled. -bool SystemZFrameInfo::hasFP(const MachineFunction &MF) const { +bool SystemZFrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects(); } @@ -91,9 +91,8 @@ } } -void SystemZFrameInfo::emitPrologue(MachineFunction &MF) const { +void SystemZFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo(); const SystemZInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); @@ -108,7 +107,7 @@ uint64_t StackSize = MFI->getStackSize(); StackSize -= SystemZMFI->getCalleeSavedFrameSize(); - uint64_t NumBytes = StackSize - TFI.getOffsetOfLocalArea(); + uint64_t NumBytes = StackSize - getOffsetOfLocalArea(); // Skip the callee-saved push instructions. while (MBBI != MBB.end() && @@ -139,10 +138,9 @@ } } -void SystemZFrameInfo::emitEpilogue(MachineFunction &MF, +void SystemZFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); const SystemZInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); @@ -161,7 +159,7 @@ // 'undo' the stack movement. uint64_t StackSize = MFI->getStackSize() - SystemZMFI->getCalleeSavedFrameSize(); - uint64_t NumBytes = StackSize - TFI.getOffsetOfLocalArea(); + uint64_t NumBytes = StackSize - getOffsetOfLocalArea(); // Skip the final terminator instruction. while (MBBI != MBB.begin()) { @@ -202,7 +200,7 @@ } } -int SystemZFrameInfo::getFrameIndexOffset(const MachineFunction &MF, +int SystemZFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const SystemZMachineFunctionInfo *SystemZMFI = @@ -224,7 +222,7 @@ } bool -SystemZFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, +SystemZFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const { @@ -299,7 +297,7 @@ } bool -SystemZFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, +SystemZFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const { @@ -353,7 +351,7 @@ } void -SystemZFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, +SystemZFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { // Determine whether R15/R14 will ever be clobbered inside the function. And // if yes - mark it as 'callee' saved. Copied: llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.h (from r123169, llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.h?p2=llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.h&p1=llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZFrameInfo.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//==- SystemZFrameInfo.h - Define TargetFrameInfo for z/System --*- C++ -*--==// +//=- SystemZFrameLowering.h - Define frame lowering for z/System -*- C++ -*--=// // // The LLVM Compiler Infrastructure // @@ -16,19 +16,19 @@ #include "SystemZ.h" #include "SystemZSubtarget.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/ADT/IndexedMap.h" namespace llvm { class SystemZSubtarget; -class SystemZFrameInfo : public TargetFrameInfo { +class SystemZFrameLowering : public TargetFrameLowering { IndexedMap RegSpillOffsets; protected: const SystemZSubtarget &STI; public: - explicit SystemZFrameInfo(const SystemZSubtarget &sti); + explicit SystemZFrameLowering(const SystemZSubtarget &sti); /// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// the function. Modified: llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZISelLowering.cpp Mon Jan 10 06:39:04 2011 @@ -378,7 +378,7 @@ DebugLoc dl, SelectionDAG &DAG, SmallVectorImpl &InVals) const { MachineFunction &MF = DAG.getMachineFunction(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); // Offset to first argument stack slot. const unsigned FirstArgOffset = 160; Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -20,7 +20,7 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -49,7 +49,7 @@ BitVector SystemZRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (TFI->hasFP(MF)) Reserved.set(SystemZ::R11D); @@ -72,7 +72,7 @@ unsigned i = 0; MachineInstr &MI = *II; MachineFunction &MF = *MI.getParent()->getParent(); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); while (!MI.getOperand(i).isFI()) { ++i; Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td Mon Jan 10 06:39:04 2011 @@ -190,7 +190,7 @@ GR32Class::iterator GR32Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_REG32_nofp; else @@ -199,7 +199,7 @@ GR32Class::iterator GR32Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_REG32_nofp + (sizeof(SystemZ_REG32_nofp) / sizeof(unsigned)); else @@ -237,7 +237,7 @@ ADDR32Class::iterator ADDR32Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_ADDR32_nofp; else @@ -246,7 +246,7 @@ ADDR32Class::iterator ADDR32Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_ADDR32_nofp + (sizeof(SystemZ_ADDR32_nofp) / sizeof(unsigned)); else @@ -284,7 +284,7 @@ GR64Class::iterator GR64Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_REG64_nofp; else @@ -293,7 +293,7 @@ GR64Class::iterator GR64Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_REG64_nofp + (sizeof(SystemZ_REG64_nofp) / sizeof(unsigned)); else @@ -331,7 +331,7 @@ ADDR64Class::iterator ADDR64Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_ADDR64_nofp; else @@ -340,7 +340,7 @@ ADDR64Class::iterator ADDR64Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_ADDR64_nofp + (sizeof(SystemZ_ADDR64_nofp) / sizeof(unsigned)); else @@ -368,7 +368,7 @@ GR64PClass::iterator GR64PClass::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_REG64P_nofp; else @@ -377,7 +377,7 @@ GR64PClass::iterator GR64PClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_REG64P_nofp + (sizeof(SystemZ_REG64P_nofp) / sizeof(unsigned)); else @@ -405,7 +405,7 @@ GR128Class::iterator GR128Class::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_REG128_nofp; else @@ -414,7 +414,7 @@ GR128Class::iterator GR128Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return SystemZ_REG128_nofp + (sizeof(SystemZ_REG128_nofp) / sizeof(unsigned)); else Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -30,7 +30,7 @@ DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32" "-f64:64:64-f128:128:128-a0:16:16-n32:64"), InstrInfo(*this), TLInfo(*this), TSInfo(*this), - FrameInfo(Subtarget) { + FrameLowering(Subtarget) { if (getRelocationModel() == Reloc::Default) setRelocationModel(Reloc::Static); Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h Mon Jan 10 06:39:04 2011 @@ -17,12 +17,12 @@ #include "SystemZInstrInfo.h" #include "SystemZISelLowering.h" -#include "SystemZFrameInfo.h" +#include "SystemZFrameLowering.h" #include "SystemZSelectionDAGInfo.h" #include "SystemZRegisterInfo.h" #include "SystemZSubtarget.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" namespace llvm { @@ -35,12 +35,14 @@ SystemZInstrInfo InstrInfo; SystemZTargetLowering TLInfo; SystemZSelectionDAGInfo TSInfo; - SystemZFrameInfo FrameInfo; + SystemZFrameLowering FrameLowering; public: SystemZTargetMachine(const Target &T, const std::string &TT, const std::string &FS); - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const TargetFrameLowering *getFrameLowering() const { + return &FrameLowering; + } virtual const SystemZInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetData *getTargetData() const { return &DataLayout;} virtual const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; } Modified: llvm/trunk/lib/Target/TargetAsmInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetAsmInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetAsmInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetAsmInfo.cpp Mon Jan 10 06:39:04 2011 @@ -20,7 +20,7 @@ const TargetData &TD = *TM.getTargetData(); IsLittleEndian = TD.isLittleEndian(); PointerSize = TD.getPointerSize(); - const TargetFrameInfo &TFI = *TM.getFrameInfo(); + const TargetFrameLowering &TFI = *TM.getFrameLowering(); StackDir = TFI.getStackGrowthDirection(); TRI = TM.getRegisterInfo(); TFI.getInitialFrameState(InitialFrameState); Removed: llvm/trunk/lib/Target/TargetFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/TargetFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetFrameInfo.cpp (removed) @@ -1,52 +0,0 @@ -//===-- TargetFrameInfo.cpp - Implement machine frame interface -*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// Implements the layout of a stack frame on the target machine. -// -//===----------------------------------------------------------------------===// - -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/TargetFrameInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetRegisterInfo.h" - -#include -using namespace llvm; - -TargetFrameInfo::~TargetFrameInfo() { -} - -/// getInitialFrameState - Returns a list of machine moves that are assumed -/// on entry to a function. -void -TargetFrameInfo::getInitialFrameState(std::vector &Moves) const { - // Default is to do nothing. -} - -/// getFrameIndexOffset - Returns the displacement from the frame register to -/// the stack frame of the specified index. This is the default implementation -/// which is overridden for some targets. -int TargetFrameInfo::getFrameIndexOffset(const MachineFunction &MF, - int FI) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - return MFI->getObjectOffset(FI) + MFI->getStackSize() - - getOffsetOfLocalArea() + MFI->getOffsetAdjustment(); -} - -int TargetFrameInfo::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { - const TargetRegisterInfo *RI = MF.getTarget().getRegisterInfo(); - - // By default, assume all frame indices are referenced via whatever - // getFrameRegister() says. The target can override this if it's doing - // something different. - FrameReg = RI->getFrameRegister(MF); - return getFrameIndexOffset(MF, FI); -} Copied: llvm/trunk/lib/Target/TargetFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/TargetFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetFrameLowering.cpp?p2=llvm/trunk/lib/Target/TargetFrameLowering.cpp&p1=llvm/trunk/lib/Target/TargetFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===-- TargetFrameInfo.cpp - Implement machine frame interface -*- C++ -*-===// +//===----- TargetFrameLowering.cpp - Implement target frame interface ------==// // // The LLVM Compiler Infrastructure // @@ -13,35 +13,36 @@ #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" #include using namespace llvm; -TargetFrameInfo::~TargetFrameInfo() { +TargetFrameLowering::~TargetFrameLowering() { } /// getInitialFrameState - Returns a list of machine moves that are assumed /// on entry to a function. void -TargetFrameInfo::getInitialFrameState(std::vector &Moves) const { +TargetFrameLowering::getInitialFrameState(std::vector &Moves) + const { // Default is to do nothing. } /// getFrameIndexOffset - Returns the displacement from the frame register to /// the stack frame of the specified index. This is the default implementation /// which is overridden for some targets. -int TargetFrameInfo::getFrameIndexOffset(const MachineFunction &MF, +int TargetFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); return MFI->getObjectOffset(FI) + MFI->getStackSize() - getOffsetOfLocalArea() + MFI->getOffsetAdjustment(); } -int TargetFrameInfo::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { +int TargetFrameLowering::getFrameIndexReference(const MachineFunction &MF, + int FI, unsigned &FrameReg) const { const TargetRegisterInfo *RI = MF.getTarget().getRegisterInfo(); // By default, assume all frame indices are referenced via whatever Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -13,7 +13,6 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Target/TargetFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/ADT/BitVector.h" Removed: llvm/trunk/lib/Target/X86/X86FrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameInfo.cpp (removed) @@ -1,999 +0,0 @@ -//=======- X86FrameInfo.cpp - X86 Frame Information ------------*- C++ -*-====// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains the X86 implementation of TargetFrameInfo class. -// -//===----------------------------------------------------------------------===// - -#include "X86FrameInfo.h" -#include "X86InstrBuilder.h" -#include "X86InstrInfo.h" -#include "X86MachineFunctionInfo.h" -#include "X86TargetMachine.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/ADT/SmallSet.h" - -using namespace llvm; - -// FIXME: completely move here. -extern cl::opt ForceStackAlign; - -bool X86FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const { - return !MF.getFrameInfo()->hasVarSizedObjects(); -} - -/// hasFP - Return true if the specified function should have a dedicated frame -/// pointer register. This is true if the function has variable sized allocas -/// or if frame pointer elimination is disabled. -bool X86FrameInfo::hasFP(const MachineFunction &MF) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - const MachineModuleInfo &MMI = MF.getMMI(); - const TargetRegisterInfo *RI = TM.getRegisterInfo(); - - return (DisableFramePointerElim(MF) || - RI->needsStackRealignment(MF) || - MFI->hasVarSizedObjects() || - MFI->isFrameAddressTaken() || - MF.getInfo()->getForceFramePointer() || - MMI.callsUnwindInit()); -} - -static unsigned getSUBriOpcode(unsigned is64Bit, int64_t Imm) { - if (is64Bit) { - if (isInt<8>(Imm)) - return X86::SUB64ri8; - return X86::SUB64ri32; - } else { - if (isInt<8>(Imm)) - return X86::SUB32ri8; - return X86::SUB32ri; - } -} - -static unsigned getADDriOpcode(unsigned is64Bit, int64_t Imm) { - if (is64Bit) { - if (isInt<8>(Imm)) - return X86::ADD64ri8; - return X86::ADD64ri32; - } else { - if (isInt<8>(Imm)) - return X86::ADD32ri8; - return X86::ADD32ri; - } -} - -/// findDeadCallerSavedReg - Return a caller-saved register that isn't live -/// when it reaches the "return" instruction. We can then pop a stack object -/// to this register without worry about clobbering it. -static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - const TargetRegisterInfo &TRI, - bool Is64Bit) { - const MachineFunction *MF = MBB.getParent(); - const Function *F = MF->getFunction(); - if (!F || MF->getMMI().callsEHReturn()) - return 0; - - static const unsigned CallerSavedRegs32Bit[] = { - X86::EAX, X86::EDX, X86::ECX - }; - - static const unsigned CallerSavedRegs64Bit[] = { - X86::RAX, X86::RDX, X86::RCX, X86::RSI, X86::RDI, - X86::R8, X86::R9, X86::R10, X86::R11 - }; - - unsigned Opc = MBBI->getOpcode(); - switch (Opc) { - default: return 0; - case X86::RET: - case X86::RETI: - case X86::TCRETURNdi: - case X86::TCRETURNri: - case X86::TCRETURNmi: - case X86::TCRETURNdi64: - case X86::TCRETURNri64: - case X86::TCRETURNmi64: - case X86::EH_RETURN: - case X86::EH_RETURN64: { - SmallSet Uses; - for (unsigned i = 0, e = MBBI->getNumOperands(); i != e; ++i) { - MachineOperand &MO = MBBI->getOperand(i); - if (!MO.isReg() || MO.isDef()) - continue; - unsigned Reg = MO.getReg(); - if (!Reg) - continue; - for (const unsigned *AsI = TRI.getOverlaps(Reg); *AsI; ++AsI) - Uses.insert(*AsI); - } - - const unsigned *CS = Is64Bit ? CallerSavedRegs64Bit : CallerSavedRegs32Bit; - for (; *CS; ++CS) - if (!Uses.count(*CS)) - return *CS; - } - } - - return 0; -} - - -/// emitSPUpdate - Emit a series of instructions to increment / decrement the -/// stack pointer by a constant value. -static -void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - unsigned StackPtr, int64_t NumBytes, - bool Is64Bit, const TargetInstrInfo &TII, - const TargetRegisterInfo &TRI) { - bool isSub = NumBytes < 0; - uint64_t Offset = isSub ? -NumBytes : NumBytes; - unsigned Opc = isSub ? - getSUBriOpcode(Is64Bit, Offset) : - getADDriOpcode(Is64Bit, Offset); - uint64_t Chunk = (1LL << 31) - 1; - DebugLoc DL = MBB.findDebugLoc(MBBI); - - while (Offset) { - uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; - if (ThisVal == (Is64Bit ? 8 : 4)) { - // Use push / pop instead. - unsigned Reg = isSub - ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) - : findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit); - if (Reg) { - Opc = isSub - ? (Is64Bit ? X86::PUSH64r : X86::PUSH32r) - : (Is64Bit ? X86::POP64r : X86::POP32r); - BuildMI(MBB, MBBI, DL, TII.get(Opc)) - .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)); - Offset -= ThisVal; - continue; - } - } - - MachineInstr *MI = - BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) - .addReg(StackPtr) - .addImm(ThisVal); - MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. - Offset -= ThisVal; - } -} - -/// mergeSPUpdatesUp - Merge two stack-manipulating instructions upper iterator. -static -void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - unsigned StackPtr, uint64_t *NumBytes = NULL) { - if (MBBI == MBB.begin()) return; - - MachineBasicBlock::iterator PI = prior(MBBI); - unsigned Opc = PI->getOpcode(); - if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || - Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && - PI->getOperand(0).getReg() == StackPtr) { - if (NumBytes) - *NumBytes += PI->getOperand(2).getImm(); - MBB.erase(PI); - } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || - Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && - PI->getOperand(0).getReg() == StackPtr) { - if (NumBytes) - *NumBytes -= PI->getOperand(2).getImm(); - MBB.erase(PI); - } -} - -/// mergeSPUpdatesDown - Merge two stack-manipulating instructions lower iterator. -static -void mergeSPUpdatesDown(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned StackPtr, uint64_t *NumBytes = NULL) { - // FIXME: THIS ISN'T RUN!!! - return; - - if (MBBI == MBB.end()) return; - - MachineBasicBlock::iterator NI = llvm::next(MBBI); - if (NI == MBB.end()) return; - - unsigned Opc = NI->getOpcode(); - if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || - Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && - NI->getOperand(0).getReg() == StackPtr) { - if (NumBytes) - *NumBytes -= NI->getOperand(2).getImm(); - MBB.erase(NI); - MBBI = NI; - } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || - Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && - NI->getOperand(0).getReg() == StackPtr) { - if (NumBytes) - *NumBytes += NI->getOperand(2).getImm(); - MBB.erase(NI); - MBBI = NI; - } -} - -/// mergeSPUpdates - Checks the instruction before/after the passed -/// instruction. If it is an ADD/SUB instruction it is deleted argument and the -/// stack adjustment is returned as a positive value for ADD and a negative for -/// SUB. -static int mergeSPUpdates(MachineBasicBlock &MBB, - MachineBasicBlock::iterator &MBBI, - unsigned StackPtr, - bool doMergeWithPrevious) { - if ((doMergeWithPrevious && MBBI == MBB.begin()) || - (!doMergeWithPrevious && MBBI == MBB.end())) - return 0; - - MachineBasicBlock::iterator PI = doMergeWithPrevious ? prior(MBBI) : MBBI; - MachineBasicBlock::iterator NI = doMergeWithPrevious ? 0 : llvm::next(MBBI); - unsigned Opc = PI->getOpcode(); - int Offset = 0; - - if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || - Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && - PI->getOperand(0).getReg() == StackPtr){ - Offset += PI->getOperand(2).getImm(); - MBB.erase(PI); - if (!doMergeWithPrevious) MBBI = NI; - } else if ((Opc == X86::SUB64ri32 || Opc == X86::SUB64ri8 || - Opc == X86::SUB32ri || Opc == X86::SUB32ri8) && - PI->getOperand(0).getReg() == StackPtr) { - Offset -= PI->getOperand(2).getImm(); - MBB.erase(PI); - if (!doMergeWithPrevious) MBBI = NI; - } - - return Offset; -} - -static bool isEAXLiveIn(MachineFunction &MF) { - for (MachineRegisterInfo::livein_iterator II = MF.getRegInfo().livein_begin(), - EE = MF.getRegInfo().livein_end(); II != EE; ++II) { - unsigned Reg = II->first; - - if (Reg == X86::EAX || Reg == X86::AX || - Reg == X86::AH || Reg == X86::AL) - return true; - } - - return false; -} - -void X86FrameInfo::emitCalleeSavedFrameMoves(MachineFunction &MF, - MCSymbol *Label, - unsigned FramePtr) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineModuleInfo &MMI = MF.getMMI(); - - // Add callee saved registers to move list. - const std::vector &CSI = MFI->getCalleeSavedInfo(); - if (CSI.empty()) return; - - std::vector &Moves = MMI.getFrameMoves(); - const TargetData *TD = TM.getTargetData(); - bool HasFP = hasFP(MF); - - // Calculate amount of bytes used for return address storing. - int stackGrowth = - (TM.getFrameInfo()->getStackGrowthDirection() == - TargetFrameInfo::StackGrowsUp ? - TD->getPointerSize() : -TD->getPointerSize()); - - // FIXME: This is dirty hack. The code itself is pretty mess right now. - // It should be rewritten from scratch and generalized sometimes. - - // Determine maximum offset (minumum due to stack growth). - int64_t MaxOffset = 0; - for (std::vector::const_iterator - I = CSI.begin(), E = CSI.end(); I != E; ++I) - MaxOffset = std::min(MaxOffset, - MFI->getObjectOffset(I->getFrameIdx())); - - // Calculate offsets. - int64_t saveAreaOffset = (HasFP ? 3 : 2) * stackGrowth; - for (std::vector::const_iterator - I = CSI.begin(), E = CSI.end(); I != E; ++I) { - int64_t Offset = MFI->getObjectOffset(I->getFrameIdx()); - unsigned Reg = I->getReg(); - Offset = MaxOffset - Offset + saveAreaOffset; - - // Don't output a new machine move if we're re-saving the frame - // pointer. This happens when the PrologEpilogInserter has inserted an extra - // "PUSH" of the frame pointer -- the "emitPrologue" method automatically - // generates one when frame pointers are used. If we generate a "machine - // move" for this extra "PUSH", the linker will lose track of the fact that - // the frame pointer should have the value of the first "PUSH" when it's - // trying to unwind. - // - // FIXME: This looks inelegant. It's possibly correct, but it's covering up - // another bug. I.e., one where we generate a prolog like this: - // - // pushl %ebp - // movl %esp, %ebp - // pushl %ebp - // pushl %esi - // ... - // - // The immediate re-push of EBP is unnecessary. At the least, it's an - // optimization bug. EBP can be used as a scratch register in certain - // cases, but probably not when we have a frame pointer. - if (HasFP && FramePtr == Reg) - continue; - - MachineLocation CSDst(MachineLocation::VirtualFP, Offset); - MachineLocation CSSrc(Reg); - Moves.push_back(MachineMove(Label, CSDst, CSSrc)); - } -} - -/// emitPrologue - Push callee-saved registers onto the stack, which -/// automatically adjust the stack pointer. Adjust the stack pointer to allocate -/// space for local variables. Also emit labels used by the exception handler to -/// generate the exception handling frames. -void X86FrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB. - MachineBasicBlock::iterator MBBI = MBB.begin(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - const Function *Fn = MF.getFunction(); - const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); - const X86InstrInfo &TII = *TM.getInstrInfo(); - MachineModuleInfo &MMI = MF.getMMI(); - X86MachineFunctionInfo *X86FI = MF.getInfo(); - bool needsFrameMoves = MMI.hasDebugInfo() || - !Fn->doesNotThrow() || UnwindTablesMandatory; - uint64_t MaxAlign = MFI->getMaxAlignment(); // Desired stack alignment. - uint64_t StackSize = MFI->getStackSize(); // Number of bytes to allocate. - bool HasFP = hasFP(MF); - bool Is64Bit = STI.is64Bit(); - bool IsWin64 = STI.isTargetWin64(); - unsigned StackAlign = getStackAlignment(); - unsigned SlotSize = RegInfo->getSlotSize(); - unsigned FramePtr = RegInfo->getFrameRegister(MF); - unsigned StackPtr = RegInfo->getStackRegister(); - - DebugLoc DL; - - // If we're forcing a stack realignment we can't rely on just the frame - // info, we need to know the ABI stack alignment as well in case we - // have a call out. Otherwise just make sure we have some alignment - we'll - // go with the minimum SlotSize. - if (ForceStackAlign) { - if (MFI->hasCalls()) - MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign; - else if (MaxAlign < SlotSize) - MaxAlign = SlotSize; - } - - // Add RETADDR move area to callee saved frame size. - int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); - if (TailCallReturnAddrDelta < 0) - X86FI->setCalleeSavedFrameSize( - X86FI->getCalleeSavedFrameSize() - TailCallReturnAddrDelta); - - // If this is x86-64 and the Red Zone is not disabled, if we are a leaf - // function, and use up to 128 bytes of stack space, don't have a frame - // pointer, calls, or dynamic alloca then we do not need to adjust the - // stack pointer (we fit in the Red Zone). - if (Is64Bit && !Fn->hasFnAttr(Attribute::NoRedZone) && - !RegInfo->needsStackRealignment(MF) && - !MFI->hasVarSizedObjects() && // No dynamic alloca. - !MFI->adjustsStack() && // No calls. - !IsWin64) { // Win64 has no Red Zone - uint64_t MinSize = X86FI->getCalleeSavedFrameSize(); - if (HasFP) MinSize += SlotSize; - StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0); - MFI->setStackSize(StackSize); - } else if (IsWin64) { - // We need to always allocate 32 bytes as register spill area. - // FIXME: We might reuse these 32 bytes for leaf functions. - StackSize += 32; - MFI->setStackSize(StackSize); - } - - // Insert stack pointer adjustment for later moving of return addr. Only - // applies to tail call optimized functions where the callee argument stack - // size is bigger than the callers. - if (TailCallReturnAddrDelta < 0) { - MachineInstr *MI = - BuildMI(MBB, MBBI, DL, - TII.get(getSUBriOpcode(Is64Bit, -TailCallReturnAddrDelta)), - StackPtr) - .addReg(StackPtr) - .addImm(-TailCallReturnAddrDelta); - MI->getOperand(3).setIsDead(); // The EFLAGS implicit def is dead. - } - - // Mapping for machine moves: - // - // DST: VirtualFP AND - // SRC: VirtualFP => DW_CFA_def_cfa_offset - // ELSE => DW_CFA_def_cfa - // - // SRC: VirtualFP AND - // DST: Register => DW_CFA_def_cfa_register - // - // ELSE - // OFFSET < 0 => DW_CFA_offset_extended_sf - // REG < 64 => DW_CFA_offset + Reg - // ELSE => DW_CFA_offset_extended - - std::vector &Moves = MMI.getFrameMoves(); - const TargetData *TD = MF.getTarget().getTargetData(); - uint64_t NumBytes = 0; - int stackGrowth = -TD->getPointerSize(); - - if (HasFP) { - // Calculate required stack adjustment. - uint64_t FrameSize = StackSize - SlotSize; - if (RegInfo->needsStackRealignment(MF)) - FrameSize = (FrameSize + MaxAlign - 1) / MaxAlign * MaxAlign; - - NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize(); - - // Get the offset of the stack slot for the EBP register, which is - // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. - // Update the frame offset adjustment. - MFI->setOffsetAdjustment(-NumBytes); - - // Save EBP/RBP into the appropriate stack slot. - BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) - .addReg(FramePtr, RegState::Kill); - - if (needsFrameMoves) { - // Mark the place where EBP/RBP was saved. - MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel); - - // Define the current CFA rule to use the provided offset. - if (StackSize) { - MachineLocation SPDst(MachineLocation::VirtualFP); - MachineLocation SPSrc(MachineLocation::VirtualFP, 2 * stackGrowth); - Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); - } else { - // FIXME: Verify & implement for FP - MachineLocation SPDst(StackPtr); - MachineLocation SPSrc(StackPtr, stackGrowth); - Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); - } - - // Change the rule for the FramePtr to be an "offset" rule. - MachineLocation FPDst(MachineLocation::VirtualFP, 2 * stackGrowth); - MachineLocation FPSrc(FramePtr); - Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); - } - - // Update EBP with the new base value... - BuildMI(MBB, MBBI, DL, - TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) - .addReg(StackPtr); - - if (needsFrameMoves) { - // Mark effective beginning of when frame pointer becomes valid. - MCSymbol *FrameLabel = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(FrameLabel); - - // Define the current CFA to use the EBP/RBP register. - MachineLocation FPDst(FramePtr); - MachineLocation FPSrc(MachineLocation::VirtualFP); - Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); - } - - // Mark the FramePtr as live-in in every block except the entry. - for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end(); - I != E; ++I) - I->addLiveIn(FramePtr); - - // Realign stack - if (RegInfo->needsStackRealignment(MF)) { - MachineInstr *MI = - BuildMI(MBB, MBBI, DL, - TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), - StackPtr).addReg(StackPtr).addImm(-MaxAlign); - - // The EFLAGS implicit def is dead. - MI->getOperand(3).setIsDead(); - } - } else { - NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); - } - - // Skip the callee-saved push instructions. - bool PushedRegs = false; - int StackOffset = 2 * stackGrowth; - - while (MBBI != MBB.end() && - (MBBI->getOpcode() == X86::PUSH32r || - MBBI->getOpcode() == X86::PUSH64r)) { - PushedRegs = true; - ++MBBI; - - if (!HasFP && needsFrameMoves) { - // Mark callee-saved push instruction. - MCSymbol *Label = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label); - - // Define the current CFA rule to use the provided offset. - unsigned Ptr = StackSize ? - MachineLocation::VirtualFP : StackPtr; - MachineLocation SPDst(Ptr); - MachineLocation SPSrc(Ptr, StackOffset); - Moves.push_back(MachineMove(Label, SPDst, SPSrc)); - StackOffset += stackGrowth; - } - } - - DL = MBB.findDebugLoc(MBBI); - - // If there is an SUB32ri of ESP immediately before this instruction, merge - // the two. This can be the case when tail call elimination is enabled and - // the callee has more arguments then the caller. - NumBytes -= mergeSPUpdates(MBB, MBBI, StackPtr, true); - - // If there is an ADD32ri or SUB32ri of ESP immediately after this - // instruction, merge the two instructions. - mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes); - - // Adjust stack pointer: ESP -= numbytes. - - // Windows and cygwin/mingw require a prologue helper routine when allocating - // more than 4K bytes on the stack. Windows uses __chkstk and cygwin/mingw - // uses __alloca. __alloca and the 32-bit version of __chkstk will probe the - // stack and adjust the stack pointer in one go. The 64-bit version of - // __chkstk is only responsible for probing the stack. The 64-bit prologue is - // responsible for adjusting the stack pointer. Touching the stack at 4K - // increments is necessary to ensure that the guard pages used by the OS - // virtual memory manager are allocated in correct sequence. - if (NumBytes >= 4096 && (STI.isTargetCygMing() || STI.isTargetWin32())) { - // Check whether EAX is livein for this function. - bool isEAXAlive = isEAXLiveIn(MF); - - const char *StackProbeSymbol = - STI.isTargetWindows() ? "_chkstk" : "_alloca"; - if (Is64Bit && STI.isTargetCygMing()) - StackProbeSymbol = "__chkstk"; - unsigned CallOp = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32; - if (!isEAXAlive) { - BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) - .addImm(NumBytes); - BuildMI(MBB, MBBI, DL, TII.get(CallOp)) - .addExternalSymbol(StackProbeSymbol) - .addReg(StackPtr, RegState::Define | RegState::Implicit) - .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); - } else { - // Save EAX - BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r)) - .addReg(X86::EAX, RegState::Kill); - - // Allocate NumBytes-4 bytes on stack. We'll also use 4 already - // allocated bytes for EAX. - BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) - .addImm(NumBytes - 4); - BuildMI(MBB, MBBI, DL, TII.get(CallOp)) - .addExternalSymbol(StackProbeSymbol) - .addReg(StackPtr, RegState::Define | RegState::Implicit) - .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); - - // Restore EAX - MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), - X86::EAX), - StackPtr, false, NumBytes - 4); - MBB.insert(MBBI, MI); - } - } else if (NumBytes >= 4096 && STI.isTargetWin64()) { - // Sanity check that EAX is not livein for this function. It should - // should not be, so throw an assert. - assert(!isEAXLiveIn(MF) && "EAX is livein in the Win64 case!"); - - // Handle the 64-bit Windows ABI case where we need to call __chkstk. - // Function prologue is responsible for adjusting the stack pointer. - BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) - .addImm(NumBytes); - BuildMI(MBB, MBBI, DL, TII.get(X86::WINCALL64pcrel32)) - .addExternalSymbol("__chkstk") - .addReg(StackPtr, RegState::Define | RegState::Implicit); - emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, - TII, *RegInfo); - } else if (NumBytes) - emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, - TII, *RegInfo); - - if ((NumBytes || PushedRegs) && needsFrameMoves) { - // Mark end of stack pointer adjustment. - MCSymbol *Label = MMI.getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, DL, TII.get(X86::PROLOG_LABEL)).addSym(Label); - - if (!HasFP && NumBytes) { - // Define the current CFA rule to use the provided offset. - if (StackSize) { - MachineLocation SPDst(MachineLocation::VirtualFP); - MachineLocation SPSrc(MachineLocation::VirtualFP, - -StackSize + stackGrowth); - Moves.push_back(MachineMove(Label, SPDst, SPSrc)); - } else { - // FIXME: Verify & implement for FP - MachineLocation SPDst(StackPtr); - MachineLocation SPSrc(StackPtr, stackGrowth); - Moves.push_back(MachineMove(Label, SPDst, SPSrc)); - } - } - - // Emit DWARF info specifying the offsets of the callee-saved registers. - if (PushedRegs) - emitCalleeSavedFrameMoves(MF, Label, HasFP ? FramePtr : StackPtr); - } -} - -void X86FrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - const MachineFrameInfo *MFI = MF.getFrameInfo(); - X86MachineFunctionInfo *X86FI = MF.getInfo(); - const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); - const X86InstrInfo &TII = *TM.getInstrInfo(); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - unsigned RetOpcode = MBBI->getOpcode(); - DebugLoc DL = MBBI->getDebugLoc(); - bool Is64Bit = STI.is64Bit(); - unsigned StackAlign = getStackAlignment(); - unsigned SlotSize = RegInfo->getSlotSize(); - unsigned FramePtr = RegInfo->getFrameRegister(MF); - unsigned StackPtr = RegInfo->getStackRegister(); - - switch (RetOpcode) { - default: - llvm_unreachable("Can only insert epilog into returning blocks"); - case X86::RET: - case X86::RETI: - case X86::TCRETURNdi: - case X86::TCRETURNri: - case X86::TCRETURNmi: - case X86::TCRETURNdi64: - case X86::TCRETURNri64: - case X86::TCRETURNmi64: - case X86::EH_RETURN: - case X86::EH_RETURN64: - break; // These are ok - } - - // Get the number of bytes to allocate from the FrameInfo. - uint64_t StackSize = MFI->getStackSize(); - uint64_t MaxAlign = MFI->getMaxAlignment(); - unsigned CSSize = X86FI->getCalleeSavedFrameSize(); - uint64_t NumBytes = 0; - - // If we're forcing a stack realignment we can't rely on just the frame - // info, we need to know the ABI stack alignment as well in case we - // have a call out. Otherwise just make sure we have some alignment - we'll - // go with the minimum. - if (ForceStackAlign) { - if (MFI->hasCalls()) - MaxAlign = (StackAlign > MaxAlign) ? StackAlign : MaxAlign; - else - MaxAlign = MaxAlign ? MaxAlign : 4; - } - - if (hasFP(MF)) { - // Calculate required stack adjustment. - uint64_t FrameSize = StackSize - SlotSize; - if (RegInfo->needsStackRealignment(MF)) - FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign; - - NumBytes = FrameSize - CSSize; - - // Pop EBP. - BuildMI(MBB, MBBI, DL, - TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); - } else { - NumBytes = StackSize - CSSize; - } - - // Skip the callee-saved pop instructions. - MachineBasicBlock::iterator LastCSPop = MBBI; - while (MBBI != MBB.begin()) { - MachineBasicBlock::iterator PI = prior(MBBI); - unsigned Opc = PI->getOpcode(); - - if (Opc != X86::POP32r && Opc != X86::POP64r && - !PI->getDesc().isTerminator()) - break; - - --MBBI; - } - - DL = MBBI->getDebugLoc(); - - // If there is an ADD32ri or SUB32ri of ESP immediately before this - // instruction, merge the two instructions. - if (NumBytes || MFI->hasVarSizedObjects()) - mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); - - // If dynamic alloca is used, then reset esp to point to the last callee-saved - // slot before popping them off! Same applies for the case, when stack was - // realigned. - if (RegInfo->needsStackRealignment(MF)) { - // We cannot use LEA here, because stack pointer was realigned. We need to - // deallocate local frame back. - if (CSSize) { - emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII, *RegInfo); - MBBI = prior(LastCSPop); - } - - BuildMI(MBB, MBBI, DL, - TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), - StackPtr).addReg(FramePtr); - } else if (MFI->hasVarSizedObjects()) { - if (CSSize) { - unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r; - MachineInstr *MI = - addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr), - FramePtr, false, -CSSize); - MBB.insert(MBBI, MI); - } else { - BuildMI(MBB, MBBI, DL, - TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr) - .addReg(FramePtr); - } - } else if (NumBytes) { - // Adjust stack pointer back: ESP += numbytes. - emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII, *RegInfo); - } - - // We're returning from function via eh_return. - if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) { - MBBI = prior(MBB.end()); - MachineOperand &DestAddr = MBBI->getOperand(0); - assert(DestAddr.isReg() && "Offset should be in register!"); - BuildMI(MBB, MBBI, DL, - TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), - StackPtr).addReg(DestAddr.getReg()); - } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi || - RetOpcode == X86::TCRETURNmi || - RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 || - RetOpcode == X86::TCRETURNmi64) { - bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64; - // Tail call return: adjust the stack pointer and jump to callee. - MBBI = prior(MBB.end()); - MachineOperand &JumpTarget = MBBI->getOperand(0); - MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1); - assert(StackAdjust.isImm() && "Expecting immediate value."); - - // Adjust stack pointer. - int StackAdj = StackAdjust.getImm(); - int MaxTCDelta = X86FI->getTCReturnAddrDelta(); - int Offset = 0; - assert(MaxTCDelta <= 0 && "MaxTCDelta should never be positive"); - - // Incoporate the retaddr area. - Offset = StackAdj-MaxTCDelta; - assert(Offset >= 0 && "Offset should never be negative"); - - if (Offset) { - // Check for possible merge with preceeding ADD instruction. - Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true); - emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII, *RegInfo); - } - - // Jump to label or value in register. - if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) { - MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi) - ? X86::TAILJMPd : X86::TAILJMPd64)); - if (JumpTarget.isGlobal()) - MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), - JumpTarget.getTargetFlags()); - else { - assert(JumpTarget.isSymbol()); - MIB.addExternalSymbol(JumpTarget.getSymbolName(), - JumpTarget.getTargetFlags()); - } - } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) { - MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi) - ? X86::TAILJMPm : X86::TAILJMPm64)); - for (unsigned i = 0; i != 5; ++i) - MIB.addOperand(MBBI->getOperand(i)); - } else if (RetOpcode == X86::TCRETURNri64) { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)). - addReg(JumpTarget.getReg(), RegState::Kill); - } else { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)). - addReg(JumpTarget.getReg(), RegState::Kill); - } - - MachineInstr *NewMI = prior(MBBI); - for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i) - NewMI->addOperand(MBBI->getOperand(i)); - - // Delete the pseudo instruction TCRETURN. - MBB.erase(MBBI); - } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) && - (X86FI->getTCReturnAddrDelta() < 0)) { - // Add the return addr area delta back since we are not tail calling. - int delta = -1*X86FI->getTCReturnAddrDelta(); - MBBI = prior(MBB.end()); - - // Check for possible merge with preceeding ADD instruction. - delta += mergeSPUpdates(MBB, MBBI, StackPtr, true); - emitSPUpdate(MBB, MBBI, StackPtr, delta, Is64Bit, TII, *RegInfo); - } -} - -void -X86FrameInfo::getInitialFrameState(std::vector &Moves) const { - // Calculate amount of bytes used for return address storing - int stackGrowth = (STI.is64Bit() ? -8 : -4); - const X86RegisterInfo *RI = TM.getRegisterInfo(); - - // Initial state of the frame pointer is esp+stackGrowth. - MachineLocation Dst(MachineLocation::VirtualFP); - MachineLocation Src(RI->getStackRegister(), stackGrowth); - Moves.push_back(MachineMove(0, Dst, Src)); - - // Add return address to move list - MachineLocation CSDst(RI->getStackRegister(), stackGrowth); - MachineLocation CSSrc(RI->getRARegister()); - Moves.push_back(MachineMove(0, CSDst, CSSrc)); -} - -int X86FrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const { - const X86RegisterInfo *RI = - static_cast(MF.getTarget().getRegisterInfo()); - const MachineFrameInfo *MFI = MF.getFrameInfo(); - int Offset = MFI->getObjectOffset(FI) - getOffsetOfLocalArea(); - uint64_t StackSize = MFI->getStackSize(); - - if (RI->needsStackRealignment(MF)) { - if (FI < 0) { - // Skip the saved EBP. - Offset += RI->getSlotSize(); - } else { - unsigned Align = MFI->getObjectAlignment(FI); - assert((-(Offset + StackSize)) % Align == 0); - Align = 0; - return Offset + StackSize; - } - // FIXME: Support tail calls - } else { - if (!hasFP(MF)) - return Offset + StackSize; - - // Skip the saved EBP. - Offset += RI->getSlotSize(); - - // Skip the RETADDR move area - const X86MachineFunctionInfo *X86FI = MF.getInfo(); - int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); - if (TailCallReturnAddrDelta < 0) - Offset -= TailCallReturnAddrDelta; - } - - return Offset; -} - -bool X86FrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - DebugLoc DL = MBB.findDebugLoc(MI); - - MachineFunction &MF = *MBB.getParent(); - - bool isWin64 = STI.isTargetWin64(); - unsigned SlotSize = STI.is64Bit() ? 8 : 4; - unsigned FPReg = TRI->getFrameRegister(MF); - unsigned CalleeFrameSize = 0; - - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - X86MachineFunctionInfo *X86FI = MF.getInfo(); - - unsigned Opc = STI.is64Bit() ? X86::PUSH64r : X86::PUSH32r; - for (unsigned i = CSI.size(); i != 0; --i) { - unsigned Reg = CSI[i-1].getReg(); - // Add the callee-saved register as live-in. It's killed at the spill. - MBB.addLiveIn(Reg); - if (Reg == FPReg) - // X86RegisterInfo::emitPrologue will handle spilling of frame register. - continue; - if (!X86::VR128RegClass.contains(Reg) && !isWin64) { - CalleeFrameSize += SlotSize; - BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, RegState::Kill); - } else { - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII.storeRegToStackSlot(MBB, MI, Reg, true, CSI[i-1].getFrameIdx(), - RC, TRI); - } - } - - X86FI->setCalleeSavedFrameSize(CalleeFrameSize); - return true; -} - -bool X86FrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return false; - - DebugLoc DL = MBB.findDebugLoc(MI); - - MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); - unsigned FPReg = TRI->getFrameRegister(MF); - bool isWin64 = STI.isTargetWin64(); - unsigned Opc = STI.is64Bit() ? X86::POP64r : X86::POP32r; - for (unsigned i = 0, e = CSI.size(); i != e; ++i) { - unsigned Reg = CSI[i].getReg(); - if (Reg == FPReg) - // X86RegisterInfo::emitEpilogue will handle restoring of frame register. - continue; - if (!X86::VR128RegClass.contains(Reg) && !isWin64) { - BuildMI(MBB, MI, DL, TII.get(Opc), Reg); - } else { - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII.loadRegFromStackSlot(MBB, MI, Reg, CSI[i].getFrameIdx(), - RC, TRI); - } - } - return true; -} - -void -X86FrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); - unsigned SlotSize = RegInfo->getSlotSize(); - - X86MachineFunctionInfo *X86FI = MF.getInfo(); - int32_t TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); - - if (TailCallReturnAddrDelta < 0) { - // create RETURNADDR area - // arg - // arg - // RETADDR - // { ... - // RETADDR area - // ... - // } - // [EBP] - MFI->CreateFixedObject(-TailCallReturnAddrDelta, - (-1U*SlotSize)+TailCallReturnAddrDelta, true); - } - - if (hasFP(MF)) { - assert((TailCallReturnAddrDelta <= 0) && - "The Delta should always be zero or negative"); - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); - - // Create a frame entry for the EBP register that must be saved. - int FrameIdx = MFI->CreateFixedObject(SlotSize, - -(int)SlotSize + - TFI.getOffsetOfLocalArea() + - TailCallReturnAddrDelta, - true); - assert(FrameIdx == MFI->getObjectIndexBegin() && - "Slot for EBP register must be last in order to be found!"); - FrameIdx = 0; - } -} Removed: llvm/trunk/lib/Target/X86/X86FrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86FrameInfo.h (removed) @@ -1,65 +0,0 @@ -//===-- X86TargetFrameInfo.h - Define TargetFrameInfo for X86 ---*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// -// -//===----------------------------------------------------------------------===// - -#ifndef X86_FRAMEINFO_H -#define X86_FRAMEINFO_H - -#include "X86Subtarget.h" -#include "llvm/Target/TargetFrameInfo.h" - -namespace llvm { - class MCSymbol; - class X86TargetMachine; - -class X86FrameInfo : public TargetFrameInfo { - const X86TargetMachine &TM; - const X86Subtarget &STI; -public: - explicit X86FrameInfo(const X86TargetMachine &tm, const X86Subtarget &sti) - : TargetFrameInfo(StackGrowsDown, - sti.getStackAlignment(), - (sti.isTargetWin64() ? -40 : (sti.is64Bit() ? -8 : -4))), - TM(tm), STI(sti) { - } - - void emitCalleeSavedFrameMoves(MachineFunction &MF, MCSymbol *Label, - unsigned FramePtr) const; - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS = NULL) const; - - bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - - bool hasFP(const MachineFunction &MF) const; - bool hasReservedCallFrame(const MachineFunction &MF) const; - - void getInitialFrameState(std::vector &Moves) const; - int getFrameIndexOffset(const MachineFunction &MF, int FI) const; -}; - -} // End llvm namespace - -#endif Copied: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (from r123169, llvm/trunk/lib/Target/X86/X86FrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?p2=llvm/trunk/lib/Target/X86/X86FrameLowering.cpp&p1=llvm/trunk/lib/Target/X86/X86FrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//=======- X86FrameInfo.cpp - X86 Frame Information ------------*- C++ -*-====// +//=======- X86FrameLowering.cpp - X86 Frame Information ------------*- C++ -*-====// // // The LLVM Compiler Infrastructure // @@ -7,11 +7,11 @@ // //===----------------------------------------------------------------------===// // -// This file contains the X86 implementation of TargetFrameInfo class. +// This file contains the X86 implementation of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#include "X86FrameInfo.h" +#include "X86FrameLowering.h" #include "X86InstrBuilder.h" #include "X86InstrInfo.h" #include "X86MachineFunctionInfo.h" @@ -32,14 +32,14 @@ // FIXME: completely move here. extern cl::opt ForceStackAlign; -bool X86FrameInfo::hasReservedCallFrame(const MachineFunction &MF) const { +bool X86FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { return !MF.getFrameInfo()->hasVarSizedObjects(); } /// hasFP - Return true if the specified function should have a dedicated frame /// pointer register. This is true if the function has variable sized allocas /// or if frame pointer elimination is disabled. -bool X86FrameInfo::hasFP(const MachineFunction &MF) const { +bool X86FrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const MachineModuleInfo &MMI = MF.getMMI(); const TargetRegisterInfo *RI = TM.getRegisterInfo(); @@ -276,7 +276,7 @@ return false; } -void X86FrameInfo::emitCalleeSavedFrameMoves(MachineFunction &MF, +void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF, MCSymbol *Label, unsigned FramePtr) const { MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -292,8 +292,8 @@ // Calculate amount of bytes used for return address storing. int stackGrowth = - (TM.getFrameInfo()->getStackGrowthDirection() == - TargetFrameInfo::StackGrowsUp ? + (TM.getFrameLowering()->getStackGrowthDirection() == + TargetFrameLowering::StackGrowsUp ? TD->getPointerSize() : -TD->getPointerSize()); // FIXME: This is dirty hack. The code itself is pretty mess right now. @@ -347,7 +347,7 @@ /// automatically adjust the stack pointer. Adjust the stack pointer to allocate /// space for local variables. Also emit labels used by the exception handler to /// generate the exception handling frames. -void X86FrameInfo::emitPrologue(MachineFunction &MF) const { +void X86FrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prologue goes in entry BB. MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -640,7 +640,7 @@ } } -void X86FrameInfo::emitEpilogue(MachineFunction &MF, +void X86FrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); X86MachineFunctionInfo *X86FI = MF.getInfo(); @@ -835,7 +835,7 @@ } void -X86FrameInfo::getInitialFrameState(std::vector &Moves) const { +X86FrameLowering::getInitialFrameState(std::vector &Moves) const { // Calculate amount of bytes used for return address storing int stackGrowth = (STI.is64Bit() ? -8 : -4); const X86RegisterInfo *RI = TM.getRegisterInfo(); @@ -851,7 +851,7 @@ Moves.push_back(MachineMove(0, CSDst, CSSrc)); } -int X86FrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) const { +int X86FrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { const X86RegisterInfo *RI = static_cast(MF.getTarget().getRegisterInfo()); const MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -886,7 +886,7 @@ return Offset; } -bool X86FrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, +bool X86FrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const { @@ -927,7 +927,7 @@ return true; } -bool X86FrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, +bool X86FrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const { @@ -958,7 +958,7 @@ } void -X86FrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, +X86FrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { MachineFrameInfo *MFI = MF.getFrameInfo(); const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); @@ -984,7 +984,7 @@ if (hasFP(MF)) { assert((TailCallReturnAddrDelta <= 0) && "The Delta should always be zero or negative"); - const TargetFrameInfo &TFI = *MF.getTarget().getFrameInfo(); + const TargetFrameLowering &TFI = *MF.getTarget().getFrameLowering(); // Create a frame entry for the EBP register that must be saved. int FrameIdx = MFI->CreateFixedObject(SlotSize, Copied: llvm/trunk/lib/Target/X86/X86FrameLowering.h (from r123169, llvm/trunk/lib/Target/X86/X86FrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.h?p2=llvm/trunk/lib/Target/X86/X86FrameLowering.h&p1=llvm/trunk/lib/Target/X86/X86FrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===-- X86TargetFrameInfo.h - Define TargetFrameInfo for X86 ---*- C++ -*-===// +//=-- X86TargetFrameLowering.h - Define frame lowering for X86 ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -7,28 +7,29 @@ // //===----------------------------------------------------------------------===// // -// +// This class implements X86-specific bits of TargetFrameLowering class. // //===----------------------------------------------------------------------===// -#ifndef X86_FRAMEINFO_H -#define X86_FRAMEINFO_H +#ifndef X86_FRAMELOWERING_H +#define X86_FRAMELOWERING_H #include "X86Subtarget.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { class MCSymbol; class X86TargetMachine; -class X86FrameInfo : public TargetFrameInfo { +class X86FrameLowering : public TargetFrameLowering { const X86TargetMachine &TM; const X86Subtarget &STI; public: - explicit X86FrameInfo(const X86TargetMachine &tm, const X86Subtarget &sti) - : TargetFrameInfo(StackGrowsDown, - sti.getStackAlignment(), - (sti.isTargetWin64() ? -40 : (sti.is64Bit() ? -8 : -4))), + explicit X86FrameLowering(const X86TargetMachine &tm, const X86Subtarget &sti) + : TargetFrameLowering(StackGrowsDown, + sti.getStackAlignment(), + (sti.isTargetWin64() ? -40 : + (sti.is64Bit() ? -8 : -4))), TM(tm), STI(sti) { } Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1145,6 +1145,7 @@ return F->hasFnAttr(Attribute::OptimizeForSize) ? 0 : 4; } +// FIXME: Why this routine is here? Move to RegInfo! std::pair X86TargetLowering::findRepresentativeClass(EVT VT) const{ const TargetRegisterClass *RRC = 0; @@ -1170,10 +1171,11 @@ return std::make_pair(RRC, Cost); } +// FIXME: Why this routine is here? Move to RegInfo! unsigned X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0; switch (RC->getID()) { @@ -1704,7 +1706,7 @@ TotalNumXMMRegs = 0; if (IsWin64) { - const TargetFrameInfo &TFI = *getTargetMachine().getFrameInfo(); + const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); // Get to the caller-allocated home save location. Add 8 to account // for the return address. int HomeOffset = TFI.getOffsetOfLocalArea() + 8; @@ -2296,7 +2298,7 @@ SelectionDAG& DAG) const { MachineFunction &MF = DAG.getMachineFunction(); const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo &TFI = *TM.getFrameInfo(); + const TargetFrameLowering &TFI = *TM.getFrameLowering(); unsigned StackAlignment = TFI.getStackAlignment(); uint64_t AlignMask = StackAlignment - 1; int64_t Offset = StackSize; @@ -8216,7 +8218,7 @@ MachineFunction &MF = DAG.getMachineFunction(); const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo &TFI = *TM.getFrameInfo(); + const TargetFrameLowering &TFI = *TM.getFrameLowering(); unsigned StackAlignment = TFI.getStackAlignment(); EVT VT = Op.getValueType(); DebugLoc DL = Op.getDebugLoc(); Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -31,7 +31,7 @@ #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/MC/MCAsmInfo.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" @@ -60,7 +60,7 @@ const X86Subtarget *Subtarget = &TM.getSubtarget(); Is64Bit = Subtarget->is64Bit(); IsWin64 = Subtarget->isTargetWin64(); - StackAlign = TM.getFrameInfo()->getStackAlignment(); + StackAlign = TM.getFrameLowering()->getStackAlignment(); if (Is64Bit) { SlotSize = 8; @@ -388,7 +388,7 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); // Set the stack-pointer register and its aliases as reserved. Reserved.set(X86::RSP); @@ -455,7 +455,7 @@ bool X86RegisterInfo::hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (Reg == FramePtr && TFI->hasFP(MF)) { FrameIdx = MF.getFrameInfo()->getObjectIndexBegin(); @@ -491,7 +491,7 @@ void X86RegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); bool reseveCallFrame = TFI->hasReservedCallFrame(MF); int Opcode = I->getOpcode(); bool isDestroy = Opcode == getCallFrameDestroyOpcode(); @@ -565,7 +565,7 @@ unsigned i = 0; MachineInstr &MI = *II; MachineFunction &MF = *MI.getParent()->getParent(); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); while (!MI.getOperand(i).isFI()) { ++i; @@ -614,7 +614,7 @@ } unsigned X86RegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); return TFI->hasFP(MF) ? FramePtr : StackPtr; } Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Mon Jan 10 06:39:04 2011 @@ -299,7 +299,7 @@ GR8Class::iterator GR8Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const X86Subtarget &Subtarget = TM.getSubtarget(); const X86MachineFunctionInfo *MFI = MF.getInfo(); // Does the function dedicate RBP / EBP to being a frame ptr? @@ -344,7 +344,7 @@ GR16Class::iterator GR16Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const X86Subtarget &Subtarget = TM.getSubtarget(); const X86MachineFunctionInfo *MFI = MF.getInfo(); if (Subtarget.is64Bit()) { @@ -396,7 +396,7 @@ GR32Class::iterator GR32Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const X86Subtarget &Subtarget = TM.getSubtarget(); const X86MachineFunctionInfo *MFI = MF.getInfo(); if (Subtarget.is64Bit()) { @@ -436,7 +436,7 @@ GR64Class::iterator GR64Class::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const X86Subtarget &Subtarget = TM.getSubtarget(); const X86MachineFunctionInfo *MFI = MF.getInfo(); if (!Subtarget.is64Bit()) @@ -541,7 +541,7 @@ GR16_NOREXClass::iterator GR16_NOREXClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const X86MachineFunctionInfo *MFI = MF.getInfo(); // Does the function dedicate RBP / EBP to being a frame ptr? if (TFI->hasFP(MF) || MFI->getReserveFP()) @@ -565,7 +565,7 @@ GR32_NOREXClass::iterator GR32_NOREXClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const X86MachineFunctionInfo *MFI = MF.getInfo(); // Does the function dedicate RBP / EBP to being a frame ptr? if (TFI->hasFP(MF) || MFI->getReserveFP()) @@ -590,7 +590,7 @@ GR64_NOREXClass::iterator GR64_NOREXClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const X86MachineFunctionInfo *MFI = MF.getInfo(); // Does the function dedicate RBP to being a frame ptr? if (TFI->hasFP(MF) || MFI->getReserveFP()) @@ -632,7 +632,7 @@ GR32_NOSPClass::iterator GR32_NOSPClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const X86Subtarget &Subtarget = TM.getSubtarget(); const X86MachineFunctionInfo *MFI = MF.getInfo(); if (Subtarget.is64Bit()) { @@ -670,7 +670,7 @@ GR64_NOSPClass::iterator GR64_NOSPClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const X86Subtarget &Subtarget = TM.getSubtarget(); const X86MachineFunctionInfo *MFI = MF.getInfo(); if (!Subtarget.is64Bit()) @@ -698,7 +698,7 @@ GR64_NOREX_NOSPClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); const X86MachineFunctionInfo *MFI = MF.getInfo(); // Does the function dedicate RBP to being a frame ptr? if (TFI->hasFP(MF) || MFI->getReserveFP()) Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -119,7 +119,7 @@ const std::string &FS, bool is64Bit) : LLVMTargetMachine(T, TT), Subtarget(TT, FS, is64Bit), - FrameInfo(*this, Subtarget), + FrameLowering(*this, Subtarget), ELFWriterInfo(is64Bit, true) { DefRelocModel = getRelocationModel(); Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Mon Jan 10 06:39:04 2011 @@ -18,13 +18,13 @@ #include "X86ELFWriterInfo.h" #include "X86InstrInfo.h" #include "X86ISelLowering.h" -#include "X86FrameInfo.h" +#include "X86FrameLowering.h" #include "X86JITInfo.h" #include "X86SelectionDAGInfo.h" #include "X86Subtarget.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" namespace llvm { @@ -32,7 +32,7 @@ class X86TargetMachine : public LLVMTargetMachine { X86Subtarget Subtarget; - X86FrameInfo FrameInfo; + X86FrameLowering FrameLowering; X86ELFWriterInfo ELFWriterInfo; Reloc::Model DefRelocModel; // Reloc model before it's overridden. @@ -48,7 +48,9 @@ virtual const X86InstrInfo *getInstrInfo() const { llvm_unreachable("getInstrInfo not implemented"); } - virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const TargetFrameLowering *getFrameLowering() const { + return &FrameLowering; + } virtual X86JITInfo *getJITInfo() { llvm_unreachable("getJITInfo not implemented"); } Removed: llvm/trunk/lib/Target/XCore/XCoreFrameInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreFrameInfo.cpp?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreFrameInfo.cpp (removed) @@ -1,382 +0,0 @@ -//===-- XCoreFrameInfo.cpp - Frame info for XCore Target ---------*- C++ -*-==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains XCore frame information that doesn't fit anywhere else -// cleanly... -// -//===----------------------------------------------------------------------===// - -#include "XCore.h" -#include "XCoreFrameInfo.h" -#include "XCoreInstrInfo.h" -#include "XCoreMachineFunctionInfo.h" -#include "llvm/Function.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineInstrBuilder.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/RegisterScavenging.h" -#include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Support/ErrorHandling.h" - -using namespace llvm; - -// helper functions. FIXME: Eliminate. -static inline bool isImmUs(unsigned val) { - return val <= 11; -} - -static inline bool isImmU6(unsigned val) { - return val < (1 << 6); -} - -static inline bool isImmU16(unsigned val) { - return val < (1 << 16); -} - -static void loadFromStack(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DstReg, int Offset, DebugLoc dl, - const TargetInstrInfo &TII) { - assert(Offset%4 == 0 && "Misaligned stack offset"); - Offset/=4; - bool isU6 = isImmU6(Offset); - if (!isU6 && !isImmU16(Offset)) - report_fatal_error("loadFromStack offset too big " + Twine(Offset)); - int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6; - BuildMI(MBB, I, dl, TII.get(Opcode), DstReg) - .addImm(Offset); -} - - -static void storeToStack(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned SrcReg, int Offset, DebugLoc dl, - const TargetInstrInfo &TII) { - assert(Offset%4 == 0 && "Misaligned stack offset"); - Offset/=4; - bool isU6 = isImmU6(Offset); - if (!isU6 && !isImmU16(Offset)) - report_fatal_error("storeToStack offset too big " + Twine(Offset)); - int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6; - BuildMI(MBB, I, dl, TII.get(Opcode)) - .addReg(SrcReg) - .addImm(Offset); -} - - -//===----------------------------------------------------------------------===// -// XCoreFrameInfo: -//===----------------------------------------------------------------------===// - -XCoreFrameInfo::XCoreFrameInfo(const XCoreSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 4, 0), - STI(sti) { - // Do nothing -} - -bool XCoreFrameInfo::hasFP(const MachineFunction &MF) const { - return DisableFramePointerElim(MF) || MF.getFrameInfo()->hasVarSizedObjects(); -} - -void XCoreFrameInfo::emitPrologue(MachineFunction &MF) const { - MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB - MachineBasicBlock::iterator MBBI = MBB.begin(); - MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineModuleInfo *MMI = &MF.getMMI(); - const XCoreRegisterInfo *RegInfo = - static_cast(MF.getTarget().getRegisterInfo()); - const XCoreInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - XCoreFunctionInfo *XFI = MF.getInfo(); - DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); - - bool FP = hasFP(MF); - - // Work out frame sizes. - int FrameSize = MFI->getStackSize(); - assert(FrameSize%4 == 0 && "Misaligned frame size"); - FrameSize/=4; - - bool isU6 = isImmU6(FrameSize); - - if (!isU6 && !isImmU16(FrameSize)) { - // FIXME could emit multiple instructions. - report_fatal_error("emitPrologue Frame size too big: " + Twine(FrameSize)); - } - bool emitFrameMoves = RegInfo->needsFrameMoves(MF); - - // Do we need to allocate space on the stack? - if (FrameSize) { - bool saveLR = XFI->getUsesLR(); - bool LRSavedOnEntry = false; - int Opcode; - if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) { - Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6; - MBB.addLiveIn(XCore::LR); - saveLR = false; - LRSavedOnEntry = true; - } else { - Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6; - } - BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); - - if (emitFrameMoves) { - std::vector &Moves = MMI->getFrameMoves(); - - // Show update of SP. - MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel); - - MachineLocation SPDst(MachineLocation::VirtualFP); - MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4); - Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); - - if (LRSavedOnEntry) { - MachineLocation CSDst(MachineLocation::VirtualFP, 0); - MachineLocation CSSrc(XCore::LR); - Moves.push_back(MachineMove(FrameLabel, CSDst, CSSrc)); - } - } - if (saveLR) { - int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot()); - storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII); - MBB.addLiveIn(XCore::LR); - - if (emitFrameMoves) { - MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel); - MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset); - MachineLocation CSSrc(XCore::LR); - MMI->getFrameMoves().push_back(MachineMove(SaveLRLabel, CSDst, CSSrc)); - } - } - } - - if (FP) { - // Save R10 to the stack. - int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot()); - storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII); - // R10 is live-in. It is killed at the spill. - MBB.addLiveIn(XCore::R10); - if (emitFrameMoves) { - MCSymbol *SaveR10Label = MMI->getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label); - MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset); - MachineLocation CSSrc(XCore::R10); - MMI->getFrameMoves().push_back(MachineMove(SaveR10Label, CSDst, CSSrc)); - } - // Set the FP from the SP. - unsigned FramePtr = XCore::R10; - BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr) - .addImm(0); - if (emitFrameMoves) { - // Show FP is now valid. - MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol(); - BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel); - MachineLocation SPDst(FramePtr); - MachineLocation SPSrc(MachineLocation::VirtualFP); - MMI->getFrameMoves().push_back(MachineMove(FrameLabel, SPDst, SPSrc)); - } - } - - if (emitFrameMoves) { - // Frame moves for callee saved. - std::vector &Moves = MMI->getFrameMoves(); - std::vector >&SpillLabels = - XFI->getSpillLabels(); - for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) { - MCSymbol *SpillLabel = SpillLabels[I].first; - CalleeSavedInfo &CSI = SpillLabels[I].second; - int Offset = MFI->getObjectOffset(CSI.getFrameIdx()); - unsigned Reg = CSI.getReg(); - MachineLocation CSDst(MachineLocation::VirtualFP, Offset); - MachineLocation CSSrc(Reg); - Moves.push_back(MachineMove(SpillLabel, CSDst, CSSrc)); - } - } -} - -void XCoreFrameInfo::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); - const XCoreInstrInfo &TII = - *static_cast(MF.getTarget().getInstrInfo()); - DebugLoc dl = MBBI->getDebugLoc(); - - bool FP = hasFP(MF); - if (FP) { - // Restore the stack pointer. - unsigned FramePtr = XCore::R10; - BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)) - .addReg(FramePtr); - } - - // Work out frame sizes. - int FrameSize = MFI->getStackSize(); - - assert(FrameSize%4 == 0 && "Misaligned frame size"); - - FrameSize/=4; - - bool isU6 = isImmU6(FrameSize); - - if (!isU6 && !isImmU16(FrameSize)) { - // FIXME could emit multiple instructions. - report_fatal_error("emitEpilogue Frame size too big: " + Twine(FrameSize)); - } - - if (FrameSize) { - XCoreFunctionInfo *XFI = MF.getInfo(); - - if (FP) { - // Restore R10 - int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot()); - FPSpillOffset += FrameSize*4; - loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII); - } - bool restoreLR = XFI->getUsesLR(); - if (restoreLR && MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0) { - int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot()); - LRSpillOffset += FrameSize*4; - loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl, TII); - restoreLR = false; - } - if (restoreLR) { - // Fold prologue into return instruction - assert(MBBI->getOpcode() == XCore::RETSP_u6 - || MBBI->getOpcode() == XCore::RETSP_lu6); - int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6; - BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize); - MBB.erase(MBBI); - } else { - int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs; - BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize); - } - } -} - -void XCoreFrameInfo::getInitialFrameState(std::vector &Moves) - const { - // Initial state of the frame pointer is SP. - MachineLocation Dst(MachineLocation::VirtualFP); - MachineLocation Src(XCore::SP, 0); - Moves.push_back(MachineMove(0, Dst, Src)); -} - -bool XCoreFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { - if (CSI.empty()) - return true; - - MachineFunction *MF = MBB.getParent(); - const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); - - XCoreFunctionInfo *XFI = MF->getInfo(); - bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF); - - DebugLoc DL; - if (MI != MBB.end()) DL = MI->getDebugLoc(); - - for (std::vector::const_iterator it = CSI.begin(); - it != CSI.end(); ++it) { - // Add the callee-saved register as live-in. It's killed at the spill. - MBB.addLiveIn(it->getReg()); - - unsigned Reg = it->getReg(); - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII.storeRegToStackSlot(MBB, MI, Reg, true, - it->getFrameIdx(), RC, TRI); - if (emitFrameMoves) { - MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol(); - BuildMI(MBB, MI, DL, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLabel); - XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it)); - } - } - return true; -} - -bool XCoreFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const{ - MachineFunction *MF = MBB.getParent(); - const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo(); - - bool AtStart = MI == MBB.begin(); - MachineBasicBlock::iterator BeforeI = MI; - if (!AtStart) - --BeforeI; - for (std::vector::const_iterator it = CSI.begin(); - it != CSI.end(); ++it) { - unsigned Reg = it->getReg(); - const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); - TII.loadRegFromStackSlot(MBB, MI, it->getReg(), it->getFrameIdx(), - RC, TRI); - assert(MI != MBB.begin() && - "loadRegFromStackSlot didn't insert any code!"); - // Insert in reverse order. loadRegFromStackSlot can insert multiple - // instructions. - if (AtStart) - MI = MBB.begin(); - else { - MI = BeforeI; - ++MI; - } - } - return true; -} - -void -XCoreFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); - bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR); - const TargetRegisterClass *RC = XCore::GRRegsRegisterClass; - XCoreFunctionInfo *XFI = MF.getInfo(); - if (LRUsed) { - MF.getRegInfo().setPhysRegUnused(XCore::LR); - - bool isVarArg = MF.getFunction()->isVarArg(); - int FrameIdx; - if (! isVarArg) { - // A fixed offset of 0 allows us to save / restore LR using entsp / retsp. - FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true); - } else { - FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(), - false); - } - XFI->setUsesLR(FrameIdx); - XFI->setLRSpillSlot(FrameIdx); - } - if (RegInfo->requiresRegisterScavenging(MF)) { - // Reserve a slot close to SP or frame pointer. - RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), - RC->getAlignment(), - false)); - } - if (hasFP(MF)) { - // A callee save register is used to hold the FP. - // This needs saving / restoring in the epilogue / prologue. - XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(), - RC->getAlignment(), - false)); - } -} - -void XCoreFrameInfo:: -processFunctionBeforeFrameFinalized(MachineFunction &MF) const { - -} Removed: llvm/trunk/lib/Target/XCore/XCoreFrameInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreFrameInfo.h?rev=123169&view=auto ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreFrameInfo.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreFrameInfo.h (removed) @@ -1,59 +0,0 @@ -//===-- XCoreFrameInfo.h - Frame info for XCore Target -----------*- C++ -*-==// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file contains XCore frame information that doesn't fit anywhere else -// cleanly... -// -//===----------------------------------------------------------------------===// - -#ifndef XCOREFRAMEINFO_H -#define XCOREFRAMEINFO_H - -#include "llvm/Target/TargetFrameInfo.h" -#include "llvm/Target/TargetMachine.h" - -namespace llvm { - class XCoreSubtarget; - - class XCoreFrameInfo: public TargetFrameInfo { - const XCoreSubtarget &STI; - public: - XCoreFrameInfo(const XCoreSubtarget &STI); - - /// emitProlog/emitEpilog - These methods insert prolog and epilog code into - /// the function. - void emitPrologue(MachineFunction &MF) const; - void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; - - bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const; - - bool hasFP(const MachineFunction &MF) const; - - void getInitialFrameState(std::vector &Moves) const; - - void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS = NULL) const; - - void processFunctionBeforeFrameFinalized(MachineFunction &MF) const; - - //! Stack slot size (4 bytes) - static int stackSlotSize() { - return 4; - } - }; -} - -#endif // XCOREFRAMEINFO_H Copied: llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp (from r123169, llvm/trunk/lib/Target/XCore/XCoreFrameInfo.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp?p2=llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp&p1=llvm/trunk/lib/Target/XCore/XCoreFrameInfo.cpp&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreFrameInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===-- XCoreFrameInfo.cpp - Frame info for XCore Target ---------*- C++ -*-==// +//===-- XCoreFrameLowering.cpp - Frame info for XCore Target -----*- C++ -*-==// // // The LLVM Compiler Infrastructure // @@ -13,7 +13,7 @@ //===----------------------------------------------------------------------===// #include "XCore.h" -#include "XCoreFrameInfo.h" +#include "XCoreFrameLowering.h" #include "XCoreInstrInfo.h" #include "XCoreMachineFunctionInfo.h" #include "llvm/Function.h" @@ -74,20 +74,20 @@ //===----------------------------------------------------------------------===// -// XCoreFrameInfo: +// XCoreFrameLowering: //===----------------------------------------------------------------------===// -XCoreFrameInfo::XCoreFrameInfo(const XCoreSubtarget &sti) - : TargetFrameInfo(TargetFrameInfo::StackGrowsDown, 4, 0), +XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti) + : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0), STI(sti) { // Do nothing } -bool XCoreFrameInfo::hasFP(const MachineFunction &MF) const { +bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const { return DisableFramePointerElim(MF) || MF.getFrameInfo()->hasVarSizedObjects(); } -void XCoreFrameInfo::emitPrologue(MachineFunction &MF) const { +void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineBasicBlock::iterator MBBI = MBB.begin(); MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -205,7 +205,7 @@ } } -void XCoreFrameInfo::emitEpilogue(MachineFunction &MF, +void XCoreFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineFrameInfo *MFI = MF.getFrameInfo(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); @@ -265,7 +265,7 @@ } } -void XCoreFrameInfo::getInitialFrameState(std::vector &Moves) +void XCoreFrameLowering::getInitialFrameState(std::vector &Moves) const { // Initial state of the frame pointer is SP. MachineLocation Dst(MachineLocation::VirtualFP); @@ -273,7 +273,7 @@ Moves.push_back(MachineMove(0, Dst, Src)); } -bool XCoreFrameInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB, +bool XCoreFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const { @@ -307,7 +307,7 @@ return true; } -bool XCoreFrameInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, +bool XCoreFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const std::vector &CSI, const TargetRegisterInfo *TRI) const{ @@ -339,7 +339,7 @@ } void -XCoreFrameInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, +XCoreFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const { MachineFrameInfo *MFI = MF.getFrameInfo(); const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); @@ -376,7 +376,7 @@ } } -void XCoreFrameInfo:: +void XCoreFrameLowering:: processFunctionBeforeFrameFinalized(MachineFunction &MF) const { } Copied: llvm/trunk/lib/Target/XCore/XCoreFrameLowering.h (from r123169, llvm/trunk/lib/Target/XCore/XCoreFrameInfo.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreFrameLowering.h?p2=llvm/trunk/lib/Target/XCore/XCoreFrameLowering.h&p1=llvm/trunk/lib/Target/XCore/XCoreFrameInfo.h&r1=123169&r2=123170&rev=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreFrameInfo.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreFrameLowering.h Mon Jan 10 06:39:04 2011 @@ -1,4 +1,4 @@ -//===-- XCoreFrameInfo.h - Frame info for XCore Target -----------*- C++ -*-==// +//===-- XCoreFrameLowering.h - Frame info for XCore Target -------*- C++ -*-==// // // The LLVM Compiler Infrastructure // @@ -15,16 +15,16 @@ #ifndef XCOREFRAMEINFO_H #define XCOREFRAMEINFO_H -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" namespace llvm { class XCoreSubtarget; - class XCoreFrameInfo: public TargetFrameInfo { + class XCoreFrameLowering: public TargetFrameLowering { const XCoreSubtarget &STI; public: - XCoreFrameInfo(const XCoreSubtarget &STI); + XCoreFrameLowering(const XCoreSubtarget &STI); /// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// the function. Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Mon Jan 10 06:39:04 2011 @@ -1033,7 +1033,7 @@ CCInfo.AnalyzeFormalArguments(Ins, CC_XCore); - unsigned StackSlotSize = XCoreFrameInfo::stackSlotSize(); + unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize(); unsigned LRSaveSize = StackSlotSize; Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Mon Jan 10 06:39:04 2011 @@ -21,7 +21,7 @@ #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/RegisterScavenging.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetInstrInfo.h" @@ -84,7 +84,7 @@ BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); Reserved.set(XCore::CP); Reserved.set(XCore::DP); @@ -98,7 +98,7 @@ bool XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); // TODO can we estimate stack size? return TFI->hasFP(MF); @@ -109,7 +109,7 @@ void XCoreRegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); if (!TFI->hasReservedCallFrame(MF)) { // Turn the adjcallstackdown instruction into 'extsp ' and the @@ -120,14 +120,13 @@ // We need to keep the stack aligned properly. To do this, we round the // amount of space needed for the outgoing arguments up to the next // alignment boundary. - unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment(); + unsigned Align = TFI->getStackAlignment(); Amount = (Amount+Align-1)/Align*Align; assert(Amount%4 == 0); Amount /= 4; - + bool isU6 = isImmU6(Amount); - if (!isU6 && !isImmU16(Amount)) { // FIX could emit multiple instructions in this case. #ifndef NDEBUG @@ -174,7 +173,7 @@ int FrameIndex = FrameOp.getIndex(); MachineFunction &MF = *MI.getParent()->getParent(); - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex); int StackSize = MF.getFrameInfo()->getStackSize(); @@ -312,7 +311,7 @@ } unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameInfo *TFI = MF.getTarget().getFrameInfo(); + const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); return TFI->hasFP(MF) ? XCore::R10 : XCore::SP; } Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td Mon Jan 10 06:39:04 2011 @@ -61,7 +61,7 @@ GRRegsClass::iterator GRRegsClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); - const TargetFrameInfo *TFI = TM.getFrameInfo(); + const TargetFrameLowering *TFI = TM.getFrameLowering(); if (TFI->hasFP(MF)) return end()-1; // don't allocate R10 else Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Mon Jan 10 06:39:04 2011 @@ -27,7 +27,7 @@ DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" "i16:16:32-i32:32:32-i64:32:32-n32"), InstrInfo(), - FrameInfo(Subtarget), + FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this) { } Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=123170&r1=123169&r2=123170&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Mon Jan 10 06:39:04 2011 @@ -16,7 +16,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetData.h" -#include "XCoreFrameInfo.h" +#include "XCoreFrameLowering.h" #include "XCoreSubtarget.h" #include "XCoreInstrInfo.h" #include "XCoreISelLowering.h" @@ -28,7 +28,7 @@ XCoreSubtarget Subtarget; const TargetData DataLayout; // Calculates type size & alignment XCoreInstrInfo InstrInfo; - XCoreFrameInfo FrameInfo; + XCoreFrameLowering FrameLowering; XCoreTargetLowering TLInfo; XCoreSelectionDAGInfo TSInfo; public: @@ -36,7 +36,9 @@ const std::string &FS); virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; } - virtual const XCoreFrameInfo *getFrameInfo() const { return &FrameInfo; } + virtual const XCoreFrameLowering *getFrameLowering() const { + return &FrameLowering; + } virtual const XCoreSubtarget *getSubtargetImpl() const { return &Subtarget; } virtual const XCoreTargetLowering *getTargetLowering() const { return &TLInfo; From asl at math.spbu.ru Mon Jan 10 06:39:23 2011 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 10 Jan 2011 12:39:23 -0000 Subject: [llvm-commits] [llvm] r123171 - in /llvm/trunk/lib/Target: ARM/CMakeLists.txt Alpha/CMakeLists.txt Blackfin/CMakeLists.txt CMakeLists.txt CellSPU/CMakeLists.txt MBlaze/CMakeLists.txt MSP430/CMakeLists.txt Mips/CMakeLists.txt PTX/CMakeLists.txt PowerPC/CMakeLists.txt Sparc/CMakeLists.txt SystemZ/CMakeLists.txt X86/CMakeLists.txt XCore/CMakeLists.txt Message-ID: <20110110123923.8BBBF2A6C12C@llvm.org> Author: asl Date: Mon Jan 10 06:39:23 2011 New Revision: 123171 URL: http://llvm.org/viewvc/llvm-project?rev=123171&view=rev Log: Update CMake stuff Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/lib/Target/Alpha/CMakeLists.txt llvm/trunk/lib/Target/Blackfin/CMakeLists.txt llvm/trunk/lib/Target/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/CMakeLists.txt llvm/trunk/lib/Target/MSP430/CMakeLists.txt llvm/trunk/lib/Target/Mips/CMakeLists.txt llvm/trunk/lib/Target/PTX/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/CMakeLists.txt llvm/trunk/lib/Target/Sparc/CMakeLists.txt llvm/trunk/lib/Target/SystemZ/CMakeLists.txt llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/XCore/CMakeLists.txt Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -27,7 +27,7 @@ ARMELFWriterInfo.cpp ARMExpandPseudoInsts.cpp ARMFastISel.cpp - ARMFrameInfo.cpp + ARMFrameLowering.cpp ARMGlobalMerge.cpp ARMHazardRecognizer.cpp ARMISelDAGToDAG.cpp @@ -46,7 +46,7 @@ MLxExpansionPass.cpp NEONMoveFix.cpp Thumb1InstrInfo.cpp - Thumb1FrameInfo.cpp + Thumb1FrameLowering.cpp Thumb1RegisterInfo.cpp Thumb2ITBlockPass.cpp Thumb2InstrInfo.cpp Modified: llvm/trunk/lib/Target/Alpha/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Alpha/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -16,7 +16,7 @@ AlphaInstrInfo.cpp AlphaISelDAGToDAG.cpp AlphaISelLowering.cpp - AlphaFrameInfo.cpp + AlphaFrameLowering.cpp AlphaLLRP.cpp AlphaMCAsmInfo.cpp AlphaRegisterInfo.cpp Modified: llvm/trunk/lib/Target/Blackfin/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Blackfin/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -17,7 +17,7 @@ BlackfinIntrinsicInfo.cpp BlackfinISelDAGToDAG.cpp BlackfinISelLowering.cpp - BlackfinFrameInfo.cpp + BlackfinFrameLowering.cpp BlackfinMCAsmInfo.cpp BlackfinRegisterInfo.cpp BlackfinSubtarget.cpp Modified: llvm/trunk/lib/Target/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -6,7 +6,7 @@ TargetAsmLexer.cpp TargetData.cpp TargetELFWriterInfo.cpp - TargetFrameInfo.cpp + TargetFrameLowering.cpp TargetInstrInfo.cpp TargetIntrinsicInfo.cpp TargetLoweringObjectFile.cpp Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CellSPU/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -13,12 +13,11 @@ add_llvm_target(CellSPUCodeGen SPUAsmPrinter.cpp - SPUFrameInfo.cpp SPUHazardRecognizers.cpp SPUInstrInfo.cpp SPUISelDAGToDAG.cpp SPUISelLowering.cpp - SPUFrameInfo.cpp + SPUFrameLowering.cpp SPUMCAsmInfo.cpp SPURegisterInfo.cpp SPUSubtarget.cpp Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -19,7 +19,7 @@ MBlazeInstrInfo.cpp MBlazeISelDAGToDAG.cpp MBlazeISelLowering.cpp - MBlazeFrameInfo.cpp + MBlazeFrameLowering.cpp MBlazeMCAsmInfo.cpp MBlazeRegisterInfo.cpp MBlazeSubtarget.cpp Modified: llvm/trunk/lib/Target/MSP430/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MSP430/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -15,7 +15,7 @@ MSP430ISelDAGToDAG.cpp MSP430ISelLowering.cpp MSP430InstrInfo.cpp - MSP430FrameInfo.cpp + MSP430FrameLowering.cpp MSP430MCAsmInfo.cpp MSP430RegisterInfo.cpp MSP430Subtarget.cpp Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -16,7 +16,7 @@ MipsInstrInfo.cpp MipsISelDAGToDAG.cpp MipsISelLowering.cpp - MipsFrameInfo.cpp + MipsFrameLowering.cpp MipsMCAsmInfo.cpp MipsRegisterInfo.cpp MipsSubtarget.cpp Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -14,7 +14,7 @@ PTXISelDAGToDAG.cpp PTXISelLowering.cpp PTXInstrInfo.cpp - PTXFrameInfo.cpp + PTXFrameLowering.cpp PTXMCAsmInfo.cpp PTXMCAsmStreamer.cpp PTXMFInfoExtract.cpp Modified: llvm/trunk/lib/Target/PowerPC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -21,7 +21,7 @@ PPCInstrInfo.cpp PPCISelDAGToDAG.cpp PPCISelLowering.cpp - PPCFrameInfo.cpp + PPCFrameLowering.cpp PPCJITInfo.cpp PPCMCAsmInfo.cpp PPCMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/Sparc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Sparc/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -17,7 +17,7 @@ SparcInstrInfo.cpp SparcISelDAGToDAG.cpp SparcISelLowering.cpp - SparcFrameInfo.cpp + SparcFrameLowering.cpp SparcMCAsmInfo.cpp SparcRegisterInfo.cpp SparcSubtarget.cpp Modified: llvm/trunk/lib/Target/SystemZ/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/SystemZ/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -15,7 +15,7 @@ SystemZISelDAGToDAG.cpp SystemZISelLowering.cpp SystemZInstrInfo.cpp - SystemZFrameInfo.cpp + SystemZFrameLowering.cpp SystemZMCAsmInfo.cpp SystemZRegisterInfo.cpp SystemZSubtarget.cpp Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -24,7 +24,7 @@ X86ELFWriterInfo.cpp X86FastISel.cpp X86FloatingPoint.cpp - X86FrameInfo.cpp + X86FrameLowering.cpp X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InstrInfo.cpp Modified: llvm/trunk/lib/Target/XCore/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/CMakeLists.txt?rev=123171&r1=123170&r2=123171&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/XCore/CMakeLists.txt Mon Jan 10 06:39:23 2011 @@ -12,7 +12,7 @@ add_llvm_target(XCoreCodeGen XCoreAsmPrinter.cpp - XCoreFrameInfo.cpp + XCoreFrameLowering.cpp XCoreInstrInfo.cpp XCoreISelDAGToDAG.cpp XCoreISelLowering.cpp From asl at math.spbu.ru Mon Jan 10 06:56:18 2011 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 10 Jan 2011 12:56:18 -0000 Subject: [llvm-commits] [llvm] r123172 - /llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp Message-ID: <20110110125618.385982A6C12C@llvm.org> Author: asl Date: Mon Jan 10 06:56:18 2011 New Revision: 123172 URL: http://llvm.org/viewvc/llvm-project?rev=123172&view=rev Log: Fix merge fallout Modified: llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp Modified: llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp?rev=123172&r1=123171&r2=123172&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp Mon Jan 10 06:56:18 2011 @@ -323,12 +323,12 @@ DEBUG(dbgs() << "Aligned Frame Size: " << FrameSize << "\n" ); } -int MBlazeFrameInfo::getFrameIndexOffset(const MachineFunction &MF, int FI) +int MBlazeFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { const MBlazeFunctionInfo *MBlazeFI = MF.getInfo(); if (MBlazeFI->hasReplacement(FI)) FI = MBlazeFI->getReplacement(FI); - return TargetFrameInfo::getFrameIndexOffset(MF,FI); + return TargetFrameLowering::getFrameIndexOffset(MF,FI); } // hasFP - Return true if the specified function should have a dedicated frame From asl at math.spbu.ru Mon Jan 10 07:21:50 2011 From: asl at math.spbu.ru (Anton Korobeynikov) Date: Mon, 10 Jan 2011 13:21:50 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r123173 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20110110132150.E45302A6C12C@llvm.org> Author: asl Date: Mon Jan 10 07:21:50 2011 New Revision: 123173 URL: http://llvm.org/viewvc/llvm-project?rev=123173&view=rev Log: Update llvm-gcc due to recent FrameInfo => FrameLowering rename Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=123173&r1=123172&r2=123173&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Mon Jan 10 07:21:50 2011 @@ -39,7 +39,7 @@ #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetFrameInfo.h" +#include "llvm/Target/TargetFrameLowering.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/DenseMap.h" @@ -185,7 +185,7 @@ } AllocaInsertionPoint = 0; - GreatestAlignment = TheTarget->getFrameInfo()->getStackAlignment(); + GreatestAlignment = TheTarget->getFrameLowering()->getStackAlignment(); SeenVLA = NULL; CatchAll = 0; @@ -862,7 +862,7 @@ // alignment, output a warning. This is here so we don't warn every time // we see a variable. if (SeenVLA && - GreatestAlignment > TheTarget->getFrameInfo()->getStackAlignment()) + GreatestAlignment > TheTarget->getFrameLowering()->getStackAlignment()) warning (0, "alignment for %q+D conflicts with a dynamically realigned " "stack", SeenVLA); #endif From daniel at zuster.org Mon Jan 10 09:26:11 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 10 Jan 2011 15:26:11 -0000 Subject: [llvm-commits] [llvm] r123174 - /llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Message-ID: <20110110152611.C55D42A6C12C@llvm.org> Author: ddunbar Date: Mon Jan 10 09:26:11 2011 New Revision: 123174 URL: http://llvm.org/viewvc/llvm-project?rev=123174&view=rev Log: MC/AsmMatcher: Fix indirect 80-col viola. Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=123174&r1=123173&r2=123174&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Jan 10 09:26:11 2011 @@ -1802,14 +1802,11 @@ OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n"; OS << " Match_MissingFeature\n"; OS << " };\n"; - OS << " MatchResultTy MatchInstructionImpl(const " - << "SmallVectorImpl" - << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n"; + OS << " MatchResultTy MatchInstructionImpl(\n"; + OS << " const SmallVectorImpl &Operands,\n"; + OS << " MCInst &Inst, unsigned &ErrorInfo);\n\n"; OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n"; - - - OS << "\n#ifdef GET_REGISTER_MATCHER\n"; OS << "#undef GET_REGISTER_MATCHER\n\n"; From daniel at zuster.org Mon Jan 10 09:26:21 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 10 Jan 2011 15:26:21 -0000 Subject: [llvm-commits] [llvm] r123175 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110110152621.B29742A6C12C@llvm.org> Author: ddunbar Date: Mon Jan 10 09:26:21 2011 New Revision: 123175 URL: http://llvm.org/viewvc/llvm-project?rev=123175&view=rev Log: MC/ARM/AsmParser: Minor nitty fixes. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123175&r1=123174&r2=123175&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jan 10 09:26:21 2011 @@ -26,7 +26,7 @@ #include "llvm/ADT/Twine.h" using namespace llvm; -// The shift types for register controlled shifts in arm memory addressing +/// Shift types used for register controlled shifts in ARM memory addressing. enum ShiftType { Lsl, Lsr, @@ -134,7 +134,7 @@ const MCExpr *Val; } Imm; - // This is for all forms of ARM address expressions + /// Combined record for all forms of ARM address expressions. struct { unsigned BaseRegNum; unsigned OffsetRegNum; // used when OffsetIsReg is true @@ -436,7 +436,7 @@ void ARMOperand::dump(raw_ostream &OS) const { switch (Kind) { case CondCode: - OS << ARMCondCodeToString(getCondCode()); + OS << ""; break; case CCOut: OS << ""; From daniel at zuster.org Mon Jan 10 09:26:35 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 10 Jan 2011 15:26:35 -0000 Subject: [llvm-commits] [llvm] r123176 - /llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Message-ID: <20110110152635.BC2E72A6C12C@llvm.org> Author: ddunbar Date: Mon Jan 10 09:26:35 2011 New Revision: 123176 URL: http://llvm.org/viewvc/llvm-project?rev=123176&view=rev Log: ARM/MC: Mark several '...S' instructions as codegen only, they aren't real instructions but are restricted pseudo forms. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=123176&r1=123175&r2=123176&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jan 10 09:26:35 2011 @@ -617,7 +617,7 @@ /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the /// instruction modifies the CPSR register. -let Defs = [CPSR] in { +let isCodeGenOnly = 1, Defs = [CPSR] in { multiclass AI1_bin_s_irs opcod, string opc, InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, PatFrag opnode, bit Commutable = 0> { @@ -852,7 +852,7 @@ } } // Carry setting variants -let Defs = [CPSR] in { +let isCodeGenOnly = 1, Defs = [CPSR] in { multiclass AI1_adde_sube_s_irs opcod, string opc, PatFrag opnode, bit Commutable = 0> { def Sri : AXI1, 1>; defm SBC : AI1_adde_sube_irs<0b0110, "sbc", BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>; + +// ADC and SUBC with 's' bit set. defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs", BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>; defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs", @@ -2112,7 +2114,7 @@ } // RSB with 's' bit set. -let Defs = [CPSR] in { +let isCodeGenOnly = 1, Defs = [CPSR] in { def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm", [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> { @@ -2181,7 +2183,7 @@ } // FIXME: Allow these to be predicated. -let Defs = [CPSR], Uses = [CPSR] in { +let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in { def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm", [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>, From daniel at zuster.org Mon Jan 10 09:26:39 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 10 Jan 2011 15:26:39 -0000 Subject: [llvm-commits] [llvm] r123177 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20110110152639.BC06F2A6C12D@llvm.org> Author: ddunbar Date: Mon Jan 10 09:26:39 2011 New Revision: 123177 URL: http://llvm.org/viewvc/llvm-project?rev=123177&view=rev Log: McARM: Mark some T2 ...s instructions as codegen only, they aren't real instructions but are restricted pseudo forms. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=123177&r1=123176&r2=123177&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Jan 10 09:26:39 2011 @@ -553,7 +553,7 @@ /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the /// instruction modifies the CPSR register. -let Defs = [CPSR] in { +let isCodeGenOnly = 1, Defs = [CPSR] in { multiclass T2I_bin_s_irs opcod, string opc, InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, PatFrag opnode, bit Commutable = 0> { @@ -700,7 +700,7 @@ } // Carry setting variants -let Defs = [CPSR] in { +let isCodeGenOnly = 1, Defs = [CPSR] in { multiclass T2I_adde_sube_s_irs opcod, string opc, PatFrag opnode, bit Commutable = 0> { // shifted imm @@ -746,7 +746,7 @@ /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register /// version is not needed since this is only for codegen. -let Defs = [CPSR] in { +let isCodeGenOnly = 1, Defs = [CPSR] in { multiclass T2I_rbin_s_is opcod, string opc, PatFrag opnode> { // shifted imm def ri : T2TwoRegImm< @@ -2035,7 +2035,7 @@ } } -let Defs = [CPSR] in { +let isCodeGenOnly = 1, Defs = [CPSR] in { def t2MOVsrl_flag : T2TwoRegShiftImm< (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, "lsrs", ".w\t$Rd, $Rm, #1", From kubastaszak at gmail.com Mon Jan 10 10:00:42 2011 From: kubastaszak at gmail.com (Jakub Staszak) Date: Mon, 10 Jan 2011 17:00:42 +0100 Subject: [llvm-commits] PR8932 Message-ID: Hi, This is my proposed patch for pr8932. -- Jakub Staszak -------------- next part -------------- A non-text attachment was scrubbed... Name: pr8932.patch Type: text/x-patch Size: 1092 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110110/ff092f20/attachment.bin From baldrick at free.fr Mon Jan 10 11:31:29 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 10 Jan 2011 17:31:29 -0000 Subject: [llvm-commits] [dragonegg] r123178 - in /dragonegg/trunk/freebsd: ./ llvm-os.h Message-ID: <20110110173129.1976C2A6C12C@llvm.org> Author: baldrick Date: Mon Jan 10 11:31:28 2011 New Revision: 123178 URL: http://llvm.org/viewvc/llvm-project?rev=123178&view=rev Log: Apparently dragonegg works more or less with FreeBSD. Added: dragonegg/trunk/freebsd/ dragonegg/trunk/freebsd/llvm-os.h Added: dragonegg/trunk/freebsd/llvm-os.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/freebsd/llvm-os.h?rev=123178&view=auto ============================================================================== --- dragonegg/trunk/freebsd/llvm-os.h (added) +++ dragonegg/trunk/freebsd/llvm-os.h Mon Jan 10 11:31:28 2011 @@ -0,0 +1,26 @@ +//===--------- llvm-os.h - FreeBSD specific definitions ---------*- C++ -*-===// +// +// Copyright (C) 2009, 2010 Duncan Sands et al. +// +// This file is part of DragonEgg. +// +// DragonEgg is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free Software +// Foundation; either version 2, or (at your option) any later version. +// +// DragonEgg is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along with +// DragonEgg; see the file COPYING. If not, write to the Free Software +// Foundation, 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA. +// +//===----------------------------------------------------------------------===// +// This file provides FreeBSD specific declarations. +//===----------------------------------------------------------------------===// + +#ifndef LLVM_OS_H +#define LLVM_OS_H + +#endif /* LLVM_OS_H */ From baldrick at free.fr Mon Jan 10 11:32:59 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 10 Jan 2011 17:32:59 -0000 Subject: [llvm-commits] [dragonegg] r123179 - /dragonegg/trunk/www/index.html Message-ID: <20110110173259.E2F8F2A6C12C@llvm.org> Author: baldrick Date: Mon Jan 10 11:32:59 2011 New Revision: 123179 URL: http://llvm.org/viewvc/llvm-project?rev=123179&view=rev Log: Claim to support FreeBSD, though this is somewhat exagerated. Modified: dragonegg/trunk/www/index.html Modified: dragonegg/trunk/www/index.html URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/www/index.html?rev=123179&r1=123178&r2=123179&view=diff ============================================================================== --- dragonegg/trunk/www/index.html (original) +++ dragonegg/trunk/www/index.html Mon Jan 10 11:32:59 2011 @@ -50,8 +50,8 @@
  • Limited debug info
  • Requires patching gcc
  • Only supports x86-32 and x86-64
  • -
  • Only supports linux and darwin (additional gcc patches may be needed on - darwin, see the README file). +
  • Only supports linux, darwin and freebsd (additional gcc patches may be + needed on darwin, see the README file).

    DragonEgg is not mature - while it works quite well, it should not be From bob.wilson at apple.com Mon Jan 10 11:36:36 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 10 Jan 2011 09:36:36 -0800 Subject: [llvm-commits] PR8932 In-Reply-To: References: Message-ID: <91D0D8C8-0F35-4046-952F-DFB03C9345E6@apple.com> On Jan 10, 2011, at 8:00 AM, Jakub Staszak wrote: > Hi, > > This is my proposed patch for pr8932. Could you please include some context in future messages like this? Most of us can't remember PR numbers and it would be nice to tell if the patch is relevant to me without having to open the attachment and take a look at the code. Thanks! From bruno.cardoso at gmail.com Mon Jan 10 11:54:18 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Mon, 10 Jan 2011 15:54:18 -0200 Subject: [llvm-commits] [PATCH] ARM bkpt instruction! Message-ID: This patch fix the asm parsing for the thumb1 bkpt instruction! Ok to commit? Thanks! -- Bruno Cardoso Lopes http://www.brunocardoso.cc -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110110/c5c1b266/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: arm-bkpt-encoding.patch Type: application/octet-stream Size: 1409 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110110/c5c1b266/attachment.obj From fvbommel at gmail.com Mon Jan 10 12:13:32 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 10 Jan 2011 19:13:32 +0100 Subject: [llvm-commits] PR8932 In-Reply-To: References: Message-ID: On Mon, Jan 10, 2011 at 5:00 PM, Jakub Staszak wrote: > This is my proposed patch for pr8932. It doesn't look very generic to me. It only checks for cases like %0 = type { %0* } What about %0 = type %0* or %0 = type [1 x %0*] ? Nor does it catch cases like %0 = type { %1*, i32 } %1 = type { %0*, i8 } I think what you really want to be looking for is recursion in the types. One alternative approach might be to introduce a limit on the number of times a function can have its arguments promoted? Are there any cases where more than, say, 10 iterations on the same function is useful in practice? (The actual limit could be a command-line parameter defaulting to something reasonable) Though now that I think about it the limit would still cause the runOnSCC() to return true even if nothing actually changed, which may be undesirable. Yet another option might be to keep a set of types a function has had, and stop trying if the function has already had (or currently has) the type you're about to give it. Though that wouldn't catch the "recursive type with extra fields" case, I suppose... From anton at korobeynikov.info Mon Jan 10 13:39:19 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Mon, 10 Jan 2011 22:39:19 +0300 Subject: [llvm-commits] [PATCH] ARM bkpt instruction! In-Reply-To: References: Message-ID: Hi Bruno, > This patch fix the asm parsing for the thumb1 bkpt instruction! > Ok to commit? Is it possible to make patch more generic somehow, e.g. for other non-predicable instructions (if any)? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From clattner at apple.com Mon Jan 10 14:57:24 2011 From: clattner at apple.com (Chris Lattner) Date: Mon, 10 Jan 2011 12:57:24 -0800 Subject: [llvm-commits] PATCH: Teach constant folding about SSE[2] conversion intrinsics In-Reply-To: References: Message-ID: <1FCF6A3D-5486-420E-AE1A-D5DD3CE761F3@apple.com> On Jan 10, 2011, at 1:18 AM, Chandler Carruth wrote: > define i32 @_Z1av() nounwind readnone { > entry: > ret i32 3 > } > > which looks pretty good to me. =] > > One question, where is the best place to test this? I couldn't find a direct test for ConstantFolding. Very nice! test/Transforms/ConstProp is the best place for constant folding tests. The patch looks reasonable to me, please add a doxygen comment to ConstantFoldConvertToInt though. Thanks Chandler! -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110110/25e43364/attachment.html From daniel at zuster.org Mon Jan 10 15:01:03 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 10 Jan 2011 21:01:03 -0000 Subject: [llvm-commits] [llvm] r123189 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/neon-absdiff-encoding.s test/MC/ARM/neon-bitcount-encoding.s test/MC/ARM/neon-pairwise-encoding.s Message-ID: <20110110210103.62F922A6C12C@llvm.org> Author: ddunbar Date: Mon Jan 10 15:01:03 2011 New Revision: 123189 URL: http://llvm.org/viewvc/llvm-project?rev=123189&view=rev Log: McARM: Flush out hard coded known non-predicated mnemonic list. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123189&r1=123188&r2=123189&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jan 10 15:01:03 2011 @@ -869,9 +869,18 @@ // FIXME: Would be nice to autogen this. static unsigned SplitMnemonicAndCC(StringRef &Mnemonic) { // Ignore some mnemonics we know aren't predicated forms. - if (Mnemonic == "movs" || - Mnemonic == "vmls" || - Mnemonic == "vnmls") + if (Mnemonic == "teq" || Mnemonic == "vceq" || + Mnemonic == "movs" || + Mnemonic == "svc" || + (Mnemonic == "mls" || Mnemonic == "smmls" || Mnemonic == "vcls" || + Mnemonic == "vmls" || Mnemonic == "vnmls") || + Mnemonic == "vacge" || Mnemonic == "vcge" || + Mnemonic == "vclt" || + Mnemonic == "vacgt" || Mnemonic == "vcgt" || + Mnemonic == "vcle" || + (Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" || + Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" || + Mnemonic == "vqdmlal")) return ARMCC::AL; // Otherwise, determine the predicate. Modified: llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s?rev=123189&r1=123188&r2=123189&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-absdiff-encoding.s Mon Jan 10 15:01:03 2011 @@ -1,6 +1,4 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * -@ NOTE: This currently fails because the ASM parser doesn't parse vabal. @ CHECK: vabd.s8 d16, d16, d17 @ encoding: [0xa1,0x07,0x40,0xf2] vabd.s8 d16, d16, d17 Modified: llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s?rev=123189&r1=123188&r2=123189&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-bitcount-encoding.s Mon Jan 10 15:01:03 2011 @@ -1,5 +1,4 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * @ CHECK: vcnt.8 d16, d16 @ encoding: [0x20,0x05,0xf0,0xf3] vcnt.8 d16, d16 Modified: llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s?rev=123189&r1=123188&r2=123189&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s (original) +++ llvm/trunk/test/MC/ARM/neon-pairwise-encoding.s Mon Jan 10 15:01:03 2011 @@ -1,5 +1,4 @@ @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s -@ XFAIL: * @ CHECK: vpadd.i8 d16, d17, d16 @ encoding: [0xb0,0x0b,0x41,0xf2] vpadd.i8 d16, d17, d16 From sabre at nondot.org Mon Jan 10 15:01:17 2011 From: sabre at nondot.org (Chris Lattner) Date: Mon, 10 Jan 2011 21:01:17 -0000 Subject: [llvm-commits] [llvm] r123190 - /llvm/trunk/lib/Target/README.txt Message-ID: <20110110210117.CF98E2A6C12C@llvm.org> Author: lattner Date: Mon Jan 10 15:01:17 2011 New Revision: 123190 URL: http://llvm.org/viewvc/llvm-project?rev=123190&view=rev Log: +0.0 vs -0.0 differences can be handled by looking at the user of the operation in some cases. Modified: llvm/trunk/lib/Target/README.txt Modified: llvm/trunk/lib/Target/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=123190&r1=123189&r2=123190&view=diff ============================================================================== --- llvm/trunk/lib/Target/README.txt (original) +++ llvm/trunk/lib/Target/README.txt Mon Jan 10 15:01:17 2011 @@ -2109,7 +2109,7 @@ //===---------------------------------------------------------------------===// -clang -03 doesn't optimize this: +clang -O3 doesn't optimize this: void f1(int* begin, int* end) { std::fill(begin, end, 0); @@ -2253,12 +2253,28 @@ extended to support general "fpclassify" operations that can return yes/no/unknown for each of these predicates. -In this predicate, we know that [us]itofp is trivially never NaN or -0.0, and +In this predicate, we know that uitofp is trivially never NaN or -0.0, and we know that it isn't +/-Inf if the floating point type has enough exponent bits to represent the largest integer value as < inf. //===---------------------------------------------------------------------===// +When optimizing a transformation that can change the sign of 0.0 (such as the +0.0*val -> 0.0 transformation above), it might be provable that the sign of the +expression doesn't matter. For example, by the above rules, we can't transform +fmul(sitofp(x), 0.0) into 0.0, because x might be -1 and the result of the +expression is defined to be -0.0. + +If we look at the uses of the fmul for example, we might be able to prove that +all uses don't care about the sign of zero. For example, if we have: + + fadd(fmul(sitofp(x), 0.0), 2.0) + +Since we know that x+2.0 doesn't care about the sign of any zeros in X, we can +transform the fmul to 0.0, and then the fadd to 2.0. + +//===---------------------------------------------------------------------===// + clang -O3 currently compiles this code: #include @@ -2270,7 +2286,7 @@ define i32 @_Z1fd(double %x) nounwind readnone { entry: %vecinit.i = insertelement <2 x double> undef, double %x, i32 0 - %vecinit1.i = insertelement <2 x double> %vecinit.i, double 0.000000e+00, i32 1 + %vecinit1.i = insertelement <2 x double> %vecinit.i, double 0.000000e+00,i32 1 %0 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %vecinit1.i) nounwind ret i32 %0 } From jasonwkim at google.com Mon Jan 10 15:40:21 2011 From: jasonwkim at google.com (Jason Kim) Date: Mon, 10 Jan 2011 13:40:21 -0800 Subject: [llvm-commits] [LLVMdev] PR 8199 - Can we get patches reviewed? In-Reply-To: References: Message-ID: On Tue, Dec 21, 2010 at 8:35 AM, David A. Greene wrote: > greened at obbligato.org (David A. Greene) writes: > >> Jason Kim writes: >> >>> Hi David. >>> >>> Feedback below: > > Here is the patch in final form. ?All LLVM tests pass for multiple build > types (debug, release, etc.). ?I'll commit it shortly. > > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? -Dave Great! Thanks! -jason > > From dalej at apple.com Mon Jan 10 15:53:07 2011 From: dalej at apple.com (Dale Johannesen) Date: Mon, 10 Jan 2011 21:53:07 -0000 Subject: [llvm-commits] [llvm] r123191 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/X86/2011-01-10-DagCombineHang.ll Message-ID: <20110110215307.78C5B2A6C12C@llvm.org> Author: johannes Date: Mon Jan 10 15:53:07 2011 New Revision: 123191 URL: http://llvm.org/viewvc/llvm-project?rev=123191&view=rev Log: Fix PR 8916 (qv for analysis), at least the immediate problem. There's an inherent tension in DAGCombine between assuming that things will be put in canonical form, and the Depth mechanism that disables transformations when recursion gets too deep. It would not surprise me if there's a lot of little bugs like this one waiting to be discovered. The mechanism seems fragile and I'd suggest looking at it from a design viewpoint. Added: llvm/trunk/test/CodeGen/X86/2011-01-10-DagCombineHang.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=123191&r1=123190&r2=123191&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Jan 10 15:53:07 2011 @@ -1176,8 +1176,9 @@ // the RHS. if (ConstantSDNode *RHSC = dyn_cast(Op.getOperand(1))) { APInt LHSZero, LHSOne; + // Do not increment Depth here; that can cause an infinite loop. TLO.DAG.ComputeMaskedBits(Op.getOperand(0), NewMask, - LHSZero, LHSOne, Depth+1); + LHSZero, LHSOne, Depth); // If the LHS already has zeros where RHSC does, this and is dead. if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) return TLO.CombineTo(Op, Op.getOperand(0)); Added: llvm/trunk/test/CodeGen/X86/2011-01-10-DagCombineHang.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-01-10-DagCombineHang.ll?rev=123191&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-01-10-DagCombineHang.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-01-10-DagCombineHang.ll Mon Jan 10 15:53:07 2011 @@ -0,0 +1,15 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin10 +; This formerly got DagCombine into a loop, PR 8916. + +define i32 @foo(i64 %x, i64 %y, i64 %z, i32 %a, i32 %b) { +entry: + %"alloca point" = bitcast i32 0 to i32 ; [#uses=0] + %t1 = shl i64 %x, 15 + %t2 = and i64 %t1, 4294934528 + %t3 = or i64 %t2, %y + %t4 = xor i64 %z, %t3 + %t5 = trunc i64 %t4 to i32 + %t6 = add i32 %a, %t5 + %t7 = add i32 %t6, %b + ret i32 %t7 +} From gohman at apple.com Mon Jan 10 15:58:09 2011 From: gohman at apple.com (Dan Gohman) Date: Mon, 10 Jan 2011 13:58:09 -0800 Subject: [llvm-commits] [llvm] r123105 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/nsw.ll In-Reply-To: <20110109022848.9FFDE2A6C12C@llvm.org> References: <20110109022848.9FFDE2A6C12C@llvm.org> Message-ID: On Jan 8, 2011, at 6:28 PM, Chris Lattner wrote: > Author: lattner > Date: Sat Jan 8 20:28:48 2011 > New Revision: 123105 > > URL: http://llvm.org/viewvc/llvm-project?rev=123105&view=rev > Log: > teach SCEV analysis of PHI nodes that PHI recurences formed > with GEP instructions are always NUW, because PHIs cannot wrap > the end of the address space. > > Modified: > llvm/trunk/lib/Analysis/ScalarEvolution.cpp > llvm/trunk/test/Analysis/ScalarEvolution/nsw.ll > > Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=123105&r1=123104&r2=123105&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) > +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Sat Jan 8 20:28:48 2011 > @@ -2719,6 +2719,11 @@ > HasNUW = true; > if (OBO->hasNoSignedWrap()) > HasNSW = true; > + } else if (isa(BEValueV)) { > + // If the increment is a GEP, then we know it won't perform an > + // unsigned overflow, because the address space cannot be > + // wrapped around. > + HasNUW = true; Hi Chris, this isn't safe unless the GEP has the inbounds flag. inbounds is to GEP very nearly what nuw and nsw are to add and sub. Dan From gohman at apple.com Mon Jan 10 16:07:50 2011 From: gohman at apple.com (Dan Gohman) Date: Mon, 10 Jan 2011 14:07:50 -0800 Subject: [llvm-commits] [llvm] r123131 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp In-Reply-To: <20110109222635.527042A6C12C@llvm.org> References: <20110109222635.527042A6C12C@llvm.org> Message-ID: <9F4529E4-DEDD-44EE-8EE8-16DE3C7E5113@apple.com> On Jan 9, 2011, at 2:26 PM, Chris Lattner wrote: > @@ -2448,22 +2448,21 @@ > > /// getMinusSCEV - Return a SCEV corresponding to LHS - RHS. > /// > -const SCEV *ScalarEvolution::getMinusSCEV(const SCEV *LHS, > - const SCEV *RHS) { > +const SCEV *ScalarEvolution::getMinusSCEV(const SCEV *LHS, const SCEV *RHS, > + bool HasNUW, bool HasNSW) { > // Fast path: X - X --> 0. > if (LHS == RHS) > return getConstant(LHS->getType(), 0); > > // X - Y --> X + -Y > - return getAddExpr(LHS, getNegativeSCEV(RHS)); > + return getAddExpr(LHS, getNegativeSCEV(RHS), HasNUW, HasNSW); This isn't safe. For example, suppose X and Y are bot INT_MIN (dynamically). Then X - Y does not overflow, but X + -Y does. > +static const SCEVAddRecExpr * > +isSimpleUnwrappingAddRec(const SCEV *S, const Loop *L) { > + const SCEVAddRecExpr *SA = dyn_cast(S); > + > + // The SCEV must be an addrec of this loop. > + if (!SA || SA->getLoop() != L || !SA->isAffine()) > + return 0; > + > + // The SCEV must be known to not wrap in some way to be interesting. > + if (!SA->hasNoUnsignedWrap() && !SA->hasNoSignedWrap()) > + return 0; It's suspicious that this code doesn't care which of nsw or nuw the instruction has. > > + > + // If the strides are equal, then this is just a (complex) loop invariant > + // comparison of a/b. > + if (LHSStride == RHSStride) > + return SE.getMinusSCEV(LHSA->getStart(), RHSA->getStart()); The comment should say a-b, not a/b. > + > + // If the signs of the strides differ, then the negative stride is counting > + // down to the positive stride. > + if (LHSStride->getValue().isNegative() != RHSStride->getValue().isNegative()){ > + if (RHSStride->getValue().isNegative()) > + std::swap(LHS, RHS); > + } else { > + // If LHS's stride is smaller than RHS's stride, then "b" must be less than > + // "a" and "b" is RHS is counting up (catching up) to LHS. This is true > + // whether the strides are positive or negative. > + if (RHSStride->getValue().slt(LHSStride->getValue())) > + std::swap(LHS, RHS); > + } > + > + return SE.getMinusSCEV(LHS, RHS, true /*HasNUW*/); This isn't safe if the addrecs are nsw but not nuw (following the suspicion above). Dan From kubastaszak at gmail.com Mon Jan 10 16:32:03 2011 From: kubastaszak at gmail.com (Jakub Staszak) Date: Mon, 10 Jan 2011 23:32:03 +0100 Subject: [llvm-commits] PR8932 In-Reply-To: References: Message-ID: You are right. I didn't test it well, sorry :( Looking for the recursion in the types might be very time-consuming. Checking for the number of iterations however, might increase size of the code without any performance benefits. On Jan 10, 2011, at 7:13 PM, Frits van Bommel wrote: > On Mon, Jan 10, 2011 at 5:00 PM, Jakub Staszak wrote: >> This is my proposed patch for pr8932. > > It doesn't look very generic to me. > It only checks for cases like > %0 = type { %0* } > What about > %0 = type %0* > or > %0 = type [1 x %0*] > ? > > Nor does it catch cases like > %0 = type { %1*, i32 } > %1 = type { %0*, i8 } > > > I think what you really want to be looking for is recursion in the types. > > One alternative approach might be to introduce a limit on the number > of times a function can have its arguments promoted? Are there any > cases where more than, say, 10 iterations on the same function is > useful in practice? (The actual limit could be a command-line > parameter defaulting to something reasonable) > Though now that I think about it the limit would still cause the > runOnSCC() to return true even if nothing actually changed, which may > be undesirable. > > Yet another option might be to keep a set of types a function has had, > and stop trying if the function has already had (or currently has) the > type you're about to give it. Though that wouldn't catch the > "recursive type with extra fields" case, I suppose... From jasonwkim at google.com Mon Jan 10 16:59:19 2011 From: jasonwkim at google.com (Jason Kim) Date: Mon, 10 Jan 2011 14:59:19 -0800 Subject: [llvm-commits] ARM/MC/ELF Support for pcrel movw/movt coming soon Message-ID: Hi everyone, happy new year. This note is to announce that support for PC relative reloc tags for movw/movt is nearing completion (hopefully <48hrs!). This work is is from Jan Voung, David Meyer and myself. Unfortunately, to test this change, we need to patch ARM/AsmParser to address http://llvm.org/bugs/show_bug.cgi?id=8721 Locally, we have hacked up a solution to 8721, but its not ideal since VK_ARM_HI16 and VK_ARM_LO16 should apply to any MCExpr, not just MCSymbolRef like it is now. The proper fix to 8721 looks to be nontrivial, so what I will do is commit the "hack" patch to 8721 separately, and then the main patch, as 8721 is blocking the testing. The interim hack for 8721 can then be rolled back separately once someone (ddunbar? pdox? me? :) get around to refactoring MCExpr so that :lower16: and :upper16: can apply to arbitrary expressions. Thanks -jason From echristo at apple.com Mon Jan 10 17:10:59 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 10 Jan 2011 23:10:59 -0000 Subject: [llvm-commits] [llvm] r123193 - /llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Message-ID: <20110110231059.43A0C2A6C12C@llvm.org> Author: echristo Date: Mon Jan 10 17:10:59 2011 New Revision: 123193 URL: http://llvm.org/viewvc/llvm-project?rev=123193&view=rev Log: Expand on the safeness of restoring the sp from the fp a bit more. Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=123193&r1=123192&r2=123193&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Mon Jan 10 17:10:59 2011 @@ -288,7 +288,8 @@ } // If the frame has variable sized objects then the epilogue must restore - // the sp from fp. + // the sp from fp. We can assume there's an FP here since hasFP already + // checks for hasVarSizedObjects. if (MFI->hasVarSizedObjects()) AFI->setShouldRestoreSPFromFP(true); } From renato.golin at arm.com Mon Jan 10 17:21:37 2011 From: renato.golin at arm.com (Renato Golin) Date: Mon, 10 Jan 2011 23:21:37 +0000 Subject: [llvm-commits] [LLVMdev] ARM/MC/ELF Support for pcrel movw/movt coming soon In-Reply-To: References: Message-ID: On 10 January 2011 22:59, Jason Kim wrote: > Hi everyone, happy new year. > > This note is to announce that support for PC relative reloc tags for > movw/movt is nearing completion (hopefully <48hrs!). This work is is > from Jan Voung, David Meyer and myself. Hi Jason, Happy new year! That seems a long patch... with many changes... can't wait for it. ;) Btw, I know this is for ELF printing, but can the same infrastructure you're using to print the hi/lo be used to print relocation in Asm output? Or is this a completely separate subject? cheers, --renato From clattner at apple.com Mon Jan 10 17:43:31 2011 From: clattner at apple.com (Chris Lattner) Date: Mon, 10 Jan 2011 15:43:31 -0800 Subject: [llvm-commits] [llvm] r123105 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Analysis/ScalarEvolution/nsw.ll In-Reply-To: References: <20110109022848.9FFDE2A6C12C@llvm.org> Message-ID: <22CAA0B7-280D-4C9F-9154-087AB29E885D@apple.com> On Jan 10, 2011, at 1:58 PM, Dan Gohman wrote: >> +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Sat Jan 8 20:28:48 2011 >> @@ -2719,6 +2719,11 @@ >> HasNUW = true; >> if (OBO->hasNoSignedWrap()) >> HasNSW = true; >> + } else if (isa(BEValueV)) { >> + // If the increment is a GEP, then we know it won't perform an >> + // unsigned overflow, because the address space cannot be >> + // wrapped around. >> + HasNUW = true; > > > Hi Chris, this isn't safe unless the GEP has the inbounds flag. > inbounds is to GEP very nearly what nuw and nsw are to add and sub. I don't really understand the issue, but I'm happy to defer to your expertise here, should I add the check for the flag? -Chris From arplynn at gmail.com Mon Jan 10 17:44:36 2011 From: arplynn at gmail.com (Alistair Lynn) Date: Mon, 10 Jan 2011 23:44:36 +0000 Subject: [llvm-commits] PATCH: instcombine switch on select of constants to br In-Reply-To: References: <893CFB3C-832C-4959-AE72-4186FCD61E99@gmail.com> <4D2A730F.2090207@mxc.ca> <130DB463-EF73-40A2-8166-5D3A014D9D12@gmail.com> Message-ID: Hi- On 10 Jan 2011, at 10:10, Frits van Bommel wrote: > Please don't top-post. My apologies. > You're not updating PHI nodes in successors. You should call > Succ->removePredecessor(BB) for each successor that is removed. Done. > Some edge cases: > - The input values are different, and go to different successors. > Fold into a conditional branch and keep exactly one copy of both > successors. > - The input values are different, but their successors are the same. > Keep folding this into an unconditional branch, and remove all but one > successor. In particular, note that the successor being jumped to will > have multiple PHI entries for this predecessor, and only one of those > may remain. I'm confused about that last point - the verifier claims that phi nodes should have one and only one entry for each predecessor? > - The input values are equal, or both are caught by the default case. > Remove all other successors and keep folding into unconditional > branch. > - Some successor blocks that are the successor of multiple switch > cases which are all removed. > - Some successor blocks that are the successor of multiple switch > cases, some (but not all) of which are removed. > > Ideally your test cases should test each of these, with other edges > (not from the switch) going to the successors and (used) PHI nodes > there. Okay, tests updated. > Since all of this may enlarge the code, you may want to factor it out > into a static helper function. You could use > SimplifyIndirectBrOnSelect() as an example, but note that that one has > some different edge cases (for instance, the successors it tries to > remove may not actually be present). > Maybe you can even share some code between that and your > SimplifySwitchOnSelect()? You could probably factor out all of the > code SimplifyIndirectBrOnSelect() uses to update successors[1] to a > separate helper function; the indirectbr-specific edge cases shouldn't > be reachable for a switch so it won't generate incorrect code. I've factored it out into a separate helper function, but it really didn't inflate the code that much. Due to the many differences between switch and indirectbr (I don't believe duplicate entries are allowed in the successors list for indirectbr), I haven't factored out common code between SimplifySwitchOnSelect and SimplifyIndirectBrOnSelect, because there really isn't much. Alistair -------------- next part -------------- A non-text attachment was scrubbed... Name: switch-patch-take-3.diff Type: application/octet-stream Size: 5854 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110110/ceffb646/attachment.obj -------------- next part -------------- From echristo at apple.com Mon Jan 10 18:16:04 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 11 Jan 2011 00:16:04 -0000 Subject: [llvm-commits] [llvm] r123196 - in /llvm/trunk: lib/Target/ARM/Thumb1FrameLowering.cpp test/CodeGen/ARM/thumb1-varalloc.ll Message-ID: <20110111001604.627E72A6C12C@llvm.org> Author: echristo Date: Mon Jan 10 18:16:04 2011 New Revision: 123196 URL: http://llvm.org/viewvc/llvm-project?rev=123196&view=rev Log: Even if we don't have 7 bytes of stack space we may need to save and restore the stack pointer from the frame pointer on thumbv6. Fixes rdar://8819685 Added: llvm/trunk/test/CodeGen/ARM/thumb1-varalloc.ll Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=123196&r1=123195&r2=123196&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Mon Jan 10 18:16:04 2011 @@ -156,6 +156,12 @@ // to reference locals. if (RegInfo->hasBasePointer(MF)) BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr).addReg(ARM::SP); + + // If the frame has variable sized objects then the epilogue must restore + // the sp from fp. We can assume there's an FP here since hasFP already + // checks for hasVarSizedObjects. + if (MFI->hasVarSizedObjects()) + AFI->setShouldRestoreSPFromFP(true); } static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) { @@ -221,7 +227,8 @@ if (AFI->shouldRestoreSPFromFP()) { NumBytes = AFI->getFramePtrSpillOffset() - NumBytes; // Reset SP based on frame pointer only if the stack frame extends beyond - // frame pointer stack slot or target is ELF and the function has FP. + // frame pointer stack slot, the target is ELF and the function has FP, or + // the target uses var sized objects. if (NumBytes) { assert(MF.getRegInfo().isPhysRegUsed(ARM::R4) && "No scratch register to restore SP from FP!"); Added: llvm/trunk/test/CodeGen/ARM/thumb1-varalloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/thumb1-varalloc.ll?rev=123196&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/thumb1-varalloc.ll (added) +++ llvm/trunk/test/CodeGen/ARM/thumb1-varalloc.ll Mon Jan 10 18:16:04 2011 @@ -0,0 +1,40 @@ +; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s +; rdar://8819685 + + at __bar = external hidden global i8* + at __baz = external hidden global i8* + +define i8* @_foo() { +entry: +; CHECK: foo: + + %size = alloca i32, align 4 + %0 = load i8** @__bar, align 4 + %1 = icmp eq i8* %0, null + br i1 %1, label %bb1, label %bb3 + +bb1: + store i32 1026, i32* %size, align 4 + %2 = alloca [1026 x i8], align 1 +; CHECK: mov r0, sp +; CHECK: adds r4, r0, r4 + %3 = getelementptr inbounds [1026 x i8]* %2, i32 0, i32 0 + %4 = call i32 @_called_func(i8* %3, i32* %size) nounwind + %5 = icmp eq i32 %4, 0 + br i1 %5, label %bb2, label %bb3 + +bb2: + %6 = call i8* @strdup(i8* %3) nounwind + store i8* %6, i8** @__baz, align 4 + br label %bb3 + +bb3: + %.0 = phi i8* [ %0, %entry ], [ %6, %bb2 ], [ %3, %bb1 ] +; CHECK: subs r4, #5 +; CHECK-NEXT: mov sp, r4 +; CHECK-NEXT: pop {r4, r5, r6, r7, pc} + ret i8* %.0 +} + +declare noalias i8* @strdup(i8* nocapture) nounwind +declare i32 @_called_func(i8*, i32*) nounwind \ No newline at end of file From dpatel at apple.com Mon Jan 10 18:31:01 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 11 Jan 2011 00:31:01 -0000 Subject: [llvm-commits] [debuginfo-tests] r123200 - /debuginfo-tests/trunk/block_var.m Message-ID: <20110111003101.4A3062A6C12C@llvm.org> Author: dpatel Date: Mon Jan 10 18:31:01 2011 New Revision: 123200 URL: http://llvm.org/viewvc/llvm-project?rev=123200&view=rev Log: Test case for r123199. Added: debuginfo-tests/trunk/block_var.m Added: debuginfo-tests/trunk/block_var.m URL: http://llvm.org/viewvc/llvm-project/debuginfo-tests/trunk/block_var.m?rev=123200&view=auto ============================================================================== --- debuginfo-tests/trunk/block_var.m (added) +++ debuginfo-tests/trunk/block_var.m Mon Jan 10 18:31:01 2011 @@ -0,0 +1,30 @@ +// RUN: %clang -O0 -g %s -c -o %t.o +// RUN: %clang %t.o -o %t.out -framework Foundation +// RUN: %test_debuginfo %s %t.out + +// DEBUGGER: break 22 +// DEBUGGER: r +// DEBUGGER: p result +// CHECK: $1 = 42 + +void doBlock(void (^block)(void)) +{ + block(); +} + +int I(int n) +{ + __block int result; + int i = 2; + doBlock(^{ + result = n; + }); + return result + i; /* Check value of 'result' */ +} + + +int main (int argc, const char * argv[]) { + return I(42); +} + + From echristo at apple.com Mon Jan 10 18:36:08 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 11 Jan 2011 00:36:08 -0000 Subject: [llvm-commits] [llvm] r123202 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeIntegerTypes.cpp LegalizeTypes.cpp Message-ID: <20110111003608.AC3982A6C12D@llvm.org> Author: echristo Date: Mon Jan 10 18:36:08 2011 New Revision: 123202 URL: http://llvm.org/viewvc/llvm-project?rev=123202&view=rev Log: Move ExpandAtomic into the integer expansion routines - it's only used there. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=123202&r1=123201&r2=123202&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Jan 10 18:36:08 2011 @@ -1065,6 +1065,93 @@ SetExpandedInteger(SDValue(N, ResNo), Lo, Hi); } +/// Lower an atomic node to the appropriate builtin call. +std::pair DAGTypeLegalizer::ExpandAtomic(SDNode *Node) { + unsigned Opc = Node->getOpcode(); + MVT VT = cast(Node)->getMemoryVT().getSimpleVT(); + RTLIB::Libcall LC; + + switch (Opc) { + default: + llvm_unreachable("Unhandled atomic intrinsic Expand!"); + break; + case ISD::ATOMIC_SWAP: + switch (VT.SimpleTy) { + default: llvm_unreachable("Unexpected value type for atomic!"); + case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; + case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; + case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; + case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; + } + break; + case ISD::ATOMIC_CMP_SWAP: + switch (VT.SimpleTy) { + default: llvm_unreachable("Unexpected value type for atomic!"); + case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; + case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; + case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; + case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; + } + break; + case ISD::ATOMIC_LOAD_ADD: + switch (VT.SimpleTy) { + default: llvm_unreachable("Unexpected value type for atomic!"); + case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; + case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; + case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; + case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; + } + break; + case ISD::ATOMIC_LOAD_SUB: + switch (VT.SimpleTy) { + default: llvm_unreachable("Unexpected value type for atomic!"); + case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; + case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; + case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; + case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; + } + break; + case ISD::ATOMIC_LOAD_AND: + switch (VT.SimpleTy) { + default: llvm_unreachable("Unexpected value type for atomic!"); + case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; + case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; + case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; + case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; + } + break; + case ISD::ATOMIC_LOAD_OR: + switch (VT.SimpleTy) { + default: llvm_unreachable("Unexpected value type for atomic!"); + case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; + case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; + case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; + case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; + } + break; + case ISD::ATOMIC_LOAD_XOR: + switch (VT.SimpleTy) { + default: llvm_unreachable("Unexpected value type for atomic!"); + case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; + case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; + case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; + case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; + } + break; + case ISD::ATOMIC_LOAD_NAND: + switch (VT.SimpleTy) { + default: llvm_unreachable("Unexpected value type for atomic!"); + case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; + case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; + case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; + case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; + } + break; + } + + return ExpandChainLibCall(LC, Node, false); +} + /// ExpandShiftByConstant - N is a shift by a value that needs to be expanded, /// and the shift amount is a constant 'Amt'. Expand the operation. void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, unsigned Amt, Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=123202&r1=123201&r2=123202&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Mon Jan 10 18:36:08 2011 @@ -1088,92 +1088,6 @@ return CallInfo; } -std::pair DAGTypeLegalizer::ExpandAtomic(SDNode *Node) { - unsigned Opc = Node->getOpcode(); - MVT VT = cast(Node)->getMemoryVT().getSimpleVT(); - RTLIB::Libcall LC; - - switch (Opc) { - default: - llvm_unreachable("Unhandled atomic intrinsic Expand!"); - break; - case ISD::ATOMIC_SWAP: - switch (VT.SimpleTy) { - default: llvm_unreachable("Unexpected value type for atomic!"); - case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; - case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; - case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; - case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; - } - break; - case ISD::ATOMIC_CMP_SWAP: - switch (VT.SimpleTy) { - default: llvm_unreachable("Unexpected value type for atomic!"); - case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; - case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; - case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; - case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; - } - break; - case ISD::ATOMIC_LOAD_ADD: - switch (VT.SimpleTy) { - default: llvm_unreachable("Unexpected value type for atomic!"); - case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; - case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; - case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; - case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; - } - break; - case ISD::ATOMIC_LOAD_SUB: - switch (VT.SimpleTy) { - default: llvm_unreachable("Unexpected value type for atomic!"); - case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; - case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; - case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; - case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; - } - break; - case ISD::ATOMIC_LOAD_AND: - switch (VT.SimpleTy) { - default: llvm_unreachable("Unexpected value type for atomic!"); - case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; - case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; - case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; - case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; - } - break; - case ISD::ATOMIC_LOAD_OR: - switch (VT.SimpleTy) { - default: llvm_unreachable("Unexpected value type for atomic!"); - case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; - case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; - case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; - case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; - } - break; - case ISD::ATOMIC_LOAD_XOR: - switch (VT.SimpleTy) { - default: llvm_unreachable("Unexpected value type for atomic!"); - case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; - case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; - case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; - case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; - } - break; - case ISD::ATOMIC_LOAD_NAND: - switch (VT.SimpleTy) { - default: llvm_unreachable("Unexpected value type for atomic!"); - case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; - case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; - case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; - case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; - } - break; - } - - return ExpandChainLibCall(LC, Node, false); -} - /// PromoteTargetBoolean - Promote the given target boolean to a target boolean /// of the given type. A target boolean is an integer value, not necessarily of /// type i1, the bits of which conform to getBooleanContents. From resistor at mac.com Mon Jan 10 18:36:45 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 11 Jan 2011 00:36:45 -0000 Subject: [llvm-commits] [llvm] r123203 - in /llvm/trunk: lib/Target/README.txt lib/Transforms/InstCombine/InstCombineCompares.cpp test/Transforms/InstCombine/icmp.ll Message-ID: <20110111003645.CBDD12A6C12D@llvm.org> Author: resistor Date: Mon Jan 10 18:36:45 2011 New Revision: 123203 URL: http://llvm.org/viewvc/llvm-project?rev=123203&view=rev Log: Fix a random missed optimization by making InstCombine more aggressive when determining which bits are demanded by a comparison against a constant. Modified: llvm/trunk/lib/Target/README.txt llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp llvm/trunk/test/Transforms/InstCombine/icmp.ll Modified: llvm/trunk/lib/Target/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=123203&r1=123202&r2=123203&view=diff ============================================================================== --- llvm/trunk/lib/Target/README.txt (original) +++ llvm/trunk/lib/Target/README.txt Mon Jan 10 18:36:45 2011 @@ -1627,21 +1627,6 @@ //===---------------------------------------------------------------------===// -InstCombine should use SimplifyDemandedBits to remove the or instruction: - -define i1 @test(i8 %x, i8 %y) { - %A = or i8 %x, 1 - %B = icmp ugt i8 %A, 3 - ret i1 %B -} - -Currently instcombine calls SimplifyDemandedBits with either all bits or just -the sign bit, if the comparison is obviously a sign test. In this case, we only -need all but the bottom two bits from %A, and if we gave that mask to SDB it -would delete the or instruction for us. - -//===---------------------------------------------------------------------===// - functionattrs doesn't know much about memcpy/memset. This function should be marked readnone rather than readonly, since it only twiddles local memory, but functionattrs doesn't handle memset/memcpy/memmove aggressively: Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=123203&r1=123202&r2=123203&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Mon Jan 10 18:36:45 2011 @@ -1693,6 +1693,45 @@ return ExtractValueInst::Create(Call, 1, "uadd.overflow"); } +// DemandedBitsLHSMask - When performing a comparison against a constant, +// it is possible that not all the bits in the LHS are demanded. This helper +// method computes the mask that IS demanded. +static APInt DemandedBitsLHSMask(ICmpInst &I, + unsigned BitWidth, bool isSignCheck) { + if (isSignCheck) + return APInt::getSignBit(BitWidth); + + ConstantInt *CI = dyn_cast(I.getOperand(1)); + if (!CI) return APInt::getAllOnesValue(BitWidth); + + APInt RHS = CI->getValue(); + APInt Mask(BitWidth, 0); + + switch (I.getPredicate()) { + // For a UGT comparison, we don't care about any bits that + // correspond to the trailing ones of the comparand. The value of these + // bits doesn't impact the outcome of the comparison, because any value + // greater than the RHS must differ in a bit higher than these due to carry. + case ICmpInst::ICMP_UGT: { + unsigned trailingOnes = RHS.countTrailingOnes(); + APInt lowBitsSet = APInt::getLowBitsSet(BitWidth, trailingOnes); + return ~lowBitsSet; + } + + // Similarly, for a ULT comparison, we don't care about the trailing zeros. + // Any value less than the RHS must differ in a higher bit because of carries. + case ICmpInst::ICMP_ULT: { + unsigned trailingZeros = RHS.countTrailingZeros(); + APInt lowBitsSet = APInt::getLowBitsSet(BitWidth, trailingZeros); + return ~lowBitsSet; + } + + default: + return APInt::getAllOnesValue(BitWidth); + } + + return Mask; +} Instruction *InstCombiner::visitICmpInst(ICmpInst &I) { bool Changed = false; @@ -1830,8 +1869,7 @@ APInt Op1KnownZero(BitWidth, 0), Op1KnownOne(BitWidth, 0); if (SimplifyDemandedBits(I.getOperandUse(0), - isSignBit ? APInt::getSignBit(BitWidth) - : APInt::getAllOnesValue(BitWidth), + DemandedBitsLHSMask(I, BitWidth, isSignBit), Op0KnownZero, Op0KnownOne, 0)) return &I; if (SimplifyDemandedBits(I.getOperandUse(1), Modified: llvm/trunk/test/Transforms/InstCombine/icmp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/icmp.ll?rev=123203&r1=123202&r2=123203&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/icmp.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/icmp.ll Mon Jan 10 18:36:45 2011 @@ -192,3 +192,20 @@ ; CHECK-NEXT: %cmp = icmp eq i32 %x, 3 } +define i1 @test21(i8 %x, i8 %y) { +; CHECK: @test21 +; CHECK-NOT: or i8 +; CHECK: icmp ugt + %A = or i8 %x, 1 + %B = icmp ugt i8 %A, 3 + ret i1 %B +} + +define i1 @test22(i8 %x, i8 %y) { +; CHECK: @test22 +; CHECK-NOT: or i8 +; CHECK: icmp ult + %A = or i8 %x, 1 + %B = icmp ult i8 %A, 4 + ret i1 %B +} From echristo at apple.com Mon Jan 10 18:40:20 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 10 Jan 2011 16:40:20 -0800 Subject: [llvm-commits] [llvm] r122979 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeIntegerTypes.cpp LegalizeTypes.cpp LegalizeTypes.h In-Reply-To: <4D2645F6.1020301@free.fr> References: <20110106222856.3C5A92A6C12C@llvm.org> <4D2645F6.1020301@free.fr> Message-ID: <15FE0BCB-D699-4EB1-8116-8D65DCAD8483@apple.com> On Jan 6, 2011, at 2:45 PM, Duncan Sands wrote: > Hi Eric, > >> +std::pair DAGTypeLegalizer::ExpandAtomic(SDNode *Node) { > > why not put this function in LegalizeIntegerTypes? It doesn't seem to be of > general utility. Are you planning to use it from some other LegalizeXYZTypes > file? > >> + std::pair ExpandAtomic(SDNode *Node); >> + > > Then you wouldn't need this declaration either. OK, I just moved the function and didn't pull it out of the class, otherwise I'd have needed to forward declare a few things and pass in a into ExpandAtomic for a single use? ick. It is moved now though :) -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110110/7ffc2183/attachment.html From chandlerc at gmail.com Mon Jan 10 19:07:20 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 11 Jan 2011 01:07:20 -0000 Subject: [llvm-commits] [llvm] r123205 - in /llvm/trunk/test/Transforms/ConstProp: basictest.ll calls.ll Message-ID: <20110111010720.31DFE2A6C12D@llvm.org> Author: chandlerc Date: Mon Jan 10 19:07:20 2011 New Revision: 123205 URL: http://llvm.org/viewvc/llvm-project?rev=123205&view=rev Log: FileCheck-ize a test, and move a no-longer calling test case to another file and make it actually test something... Modified: llvm/trunk/test/Transforms/ConstProp/basictest.ll llvm/trunk/test/Transforms/ConstProp/calls.ll Modified: llvm/trunk/test/Transforms/ConstProp/basictest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstProp/basictest.ll?rev=123205&r1=123204&r2=123205&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ConstProp/basictest.ll (original) +++ llvm/trunk/test/Transforms/ConstProp/basictest.ll Mon Jan 10 19:07:20 2011 @@ -31,3 +31,12 @@ ; CHECK: @test2 ; CHECK: ret i1 true } + +define i1 @TNAN() { +; CHECK: @TNAN +; CHECK: ret i1 true + %A = fcmp uno double 0x7FF8000000000000, 1.000000e+00 + %B = fcmp uno double 1.230000e+02, 1.000000e+00 + %C = or i1 %A, %B + ret i1 %C +} Modified: llvm/trunk/test/Transforms/ConstProp/calls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstProp/calls.ll?rev=123205&r1=123204&r2=123205&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ConstProp/calls.ll (original) +++ llvm/trunk/test/Transforms/ConstProp/calls.ll Mon Jan 10 19:07:20 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -constprop -S | not grep call +; RUN: opt < %s -constprop -S | FileCheck %s declare double @cos(double) @@ -8,23 +8,16 @@ declare double @sqrt(double) -declare i1 @llvm.isunordered.f64(double, double) - define double @T() { - %A = call double @cos( double 0.000000e+00 ) ; [#uses=1] - %B = call double @sin( double 0.000000e+00 ) ; [#uses=1] - %a = fadd double %A, %B ; [#uses=1] - %C = call double @tan( double 0.000000e+00 ) ; [#uses=1] - %b = fadd double %a, %C ; [#uses=1] - %D = call double @sqrt( double 4.000000e+00 ) ; [#uses=1] - %c = fadd double %b, %D ; [#uses=1] - ret double %c -} - -define i1 @TNAN() { - %A = fcmp uno double 0x7FF8000000000000, 1.000000e+00 ; [#uses=1] - %B = fcmp uno double 1.230000e+02, 1.000000e+00 ; [#uses=1] - %C = or i1 %A, %B ; [#uses=1] - ret i1 %C +; CHECK: @T +; CHECK-NOT: call +; CHECK: ret + %A = call double @cos(double 0.000000e+00) + %B = call double @sin(double 0.000000e+00) + %a = fadd double %A, %B + %C = call double @tan(double 0.000000e+00) + %b = fadd double %a, %C + %D = call double @sqrt(double 4.000000e+00) + %c = fadd double %b, %D + ret double %c } - From chandlerc at gmail.com Mon Jan 10 19:07:24 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 11 Jan 2011 01:07:24 -0000 Subject: [llvm-commits] [llvm] r123206 - in /llvm/trunk: lib/Analysis/ConstantFolding.cpp lib/Target/README.txt test/Transforms/ConstProp/calls.ll Message-ID: <20110111010724.C388C2A6C12E@llvm.org> Author: chandlerc Date: Mon Jan 10 19:07:24 2011 New Revision: 123206 URL: http://llvm.org/viewvc/llvm-project?rev=123206&view=rev Log: Teach constant folding to perform conversions from constant floating point values to their integer representation through the SSE intrinsic calls. This is the last part of a README.txt entry for which I have real world examples. Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp llvm/trunk/lib/Target/README.txt llvm/trunk/test/Transforms/ConstProp/calls.ll Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=123206&r1=123205&r2=123206&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original) +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Mon Jan 10 19:07:24 2011 @@ -1047,6 +1047,14 @@ case Intrinsic::smul_with_overflow: case Intrinsic::convert_from_fp16: case Intrinsic::convert_to_fp16: + case Intrinsic::x86_sse_cvtss2si: + case Intrinsic::x86_sse_cvtss2si64: + case Intrinsic::x86_sse_cvttss2si: + case Intrinsic::x86_sse_cvttss2si64: + case Intrinsic::x86_sse2_cvtsd2si: + case Intrinsic::x86_sse2_cvtsd2si64: + case Intrinsic::x86_sse2_cvttsd2si: + case Intrinsic::x86_sse2_cvttsd2si64: return true; default: return false; @@ -1116,6 +1124,36 @@ return 0; // dummy return to suppress warning } +/// ConstantFoldConvertToInt - Attempt to an SSE floating point to integer +/// conversion of a constant floating point. If roundTowardZero is false, the +/// default IEEE rounding is used (toward nearest, ties to even). This matches +/// the behavior of the non-truncating SSE instructions in the default rounding +/// mode. The desired integer type Ty is used to select how many bits are +/// available for the result. Returns null if the conversion cannot be +/// performed, otherwise returns the Constant value resulting from the +/// conversion. +static Constant *ConstantFoldConvertToInt(ConstantFP *Op, bool roundTowardZero, + const Type *Ty) { + assert(Op && "Called with NULL operand"); + APFloat Val(Op->getValueAPF()); + + // All of these conversion intrinsics form an integer of at most 64bits. + unsigned ResultWidth = cast(Ty)->getBitWidth(); + assert(ResultWidth <= 64 && + "Can only constant fold conversions to 64 and 32 bit ints"); + + uint64_t UIntVal; + bool isExact = false; + APFloat::roundingMode mode = roundTowardZero? APFloat::rmTowardZero + : APFloat::rmNearestTiesToEven; + APFloat::opStatus status = Val.convertToInteger(&UIntVal, ResultWidth, + /*isSigned=*/true, mode, + &isExact); + if (status != APFloat::opOK && status != APFloat::opInexact) + return 0; + return ConstantInt::get(Ty, UIntVal, /*isSigned=*/true); +} + /// ConstantFoldCall - Attempt to constant fold a call to the specified function /// with the specified arguments, returning null if unsuccessful. Constant * @@ -1246,6 +1284,24 @@ } } + if (ConstantVector *Op = dyn_cast(Operands[0])) { + switch (F->getIntrinsicID()) { + default: break; + case Intrinsic::x86_sse_cvtss2si: + case Intrinsic::x86_sse_cvtss2si64: + case Intrinsic::x86_sse2_cvtsd2si: + case Intrinsic::x86_sse2_cvtsd2si64: + if (ConstantFP *FPOp = dyn_cast(Op->getOperand(0))) + return ConstantFoldConvertToInt(FPOp, /*roundTowardZero=*/false, Ty); + case Intrinsic::x86_sse_cvttss2si: + case Intrinsic::x86_sse_cvttss2si64: + case Intrinsic::x86_sse2_cvttsd2si: + case Intrinsic::x86_sse2_cvttsd2si64: + if (ConstantFP *FPOp = dyn_cast(Op->getOperand(0))) + return ConstantFoldConvertToInt(FPOp, /*roundTowardZero=*/true, Ty); + } + } + if (isa(Operands[0])) { if (F->getIntrinsicID() == Intrinsic::bswap) return Operands[0]; Modified: llvm/trunk/lib/Target/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=123206&r1=123205&r2=123206&view=diff ============================================================================== --- llvm/trunk/lib/Target/README.txt (original) +++ llvm/trunk/lib/Target/README.txt Mon Jan 10 19:07:24 2011 @@ -2259,58 +2259,3 @@ transform the fmul to 0.0, and then the fadd to 2.0. //===---------------------------------------------------------------------===// - -clang -O3 currently compiles this code: - -#include -int f(double x) { return _mm_cvtsd_si32(_mm_set_sd(x)); } -int g(double x) { return _mm_cvttsd_si32(_mm_set_sd(x)); } - -into - -define i32 @_Z1fd(double %x) nounwind readnone { -entry: - %vecinit.i = insertelement <2 x double> undef, double %x, i32 0 - %vecinit1.i = insertelement <2 x double> %vecinit.i, double 0.000000e+00,i32 1 - %0 = tail call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> %vecinit1.i) nounwind - ret i32 %0 -} - -define i32 @_Z1gd(double %x) nounwind readnone { -entry: - %conv.i = fptosi double %x to i32 - ret i32 %conv.i -} - -This difference carries over to the assmebly produced, resulting in: - -_Z1fd: # @_Z1fd -# BB#0: # %entry - pushq %rbp - movq %rsp, %rbp - xorps %xmm1, %xmm1 - movsd %xmm0, %xmm1 - cvtsd2sil %xmm1, %eax - popq %rbp - ret - -_Z1gd: # @_Z1gd -# BB#0: # %entry - pushq %rbp - movq %rsp, %rbp - cvttsd2si %xmm0, %eax - popq %rbp - ret - -The problem is that we can't see through the intrinsic call used for cvtsd2si, -and fold away the unnecessary manipulation of the function parameter. When -these functions are inlined, it forms a barrier preventing many further -optimizations. LLVM IR doesn't have a good way to model the logic of -'cvtsd2si', its only FP -> int conversion path forces truncation. We should add -a rounding flag onto fptosi so that it can represent this type of rounding -naturally in the IR rather than using intrinsics. We might need to use a -'system_rounding_mode' flag to encode that the semantics of the rounding mode -can be changed by the program, but ideally we could just say that isn't -supported, and hard code the rounding. - -//===---------------------------------------------------------------------===// Modified: llvm/trunk/test/Transforms/ConstProp/calls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ConstProp/calls.ll?rev=123206&r1=123205&r2=123206&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ConstProp/calls.ll (original) +++ llvm/trunk/test/Transforms/ConstProp/calls.ll Mon Jan 10 19:07:24 2011 @@ -21,3 +21,36 @@ %c = fadd double %b, %D ret double %c } + +define i1 @test_sse_cvt() nounwind readnone { +; CHECK: @test_sse_cvt +; CHECK-NOT: call +; CHECK: ret i1 true +entry: + %i0 = tail call i32 @llvm.x86.sse.cvtss2si(<4 x float> ) nounwind + %i1 = tail call i32 @llvm.x86.sse.cvttss2si(<4 x float> ) nounwind + %i2 = tail call i64 @llvm.x86.sse.cvtss2si64(<4 x float> ) nounwind + %i3 = tail call i64 @llvm.x86.sse.cvttss2si64(<4 x float> ) nounwind + %i4 = call i32 @llvm.x86.sse2.cvtsd2si(<2 x double> ) nounwind + %i5 = call i32 @llvm.x86.sse2.cvttsd2si(<2 x double> ) nounwind + %i6 = call i64 @llvm.x86.sse2.cvtsd2si64(<2 x double> ) nounwind + %i7 = call i64 @llvm.x86.sse2.cvttsd2si64(<2 x double> ) nounwind + %sum11 = add i32 %i0, %i1 + %sum12 = add i32 %i4, %i5 + %sum1 = add i32 %sum11, %sum12 + %sum21 = add i64 %i2, %i3 + %sum22 = add i64 %i6, %i7 + %sum2 = add i64 %sum21, %sum22 + %sum1.sext = sext i32 %sum1 to i64 + %b = icmp eq i64 %sum1.sext, %sum2 + ret i1 %b +} + +declare i32 @llvm.x86.sse.cvtss2si(<4 x float>) nounwind readnone +declare i32 @llvm.x86.sse.cvttss2si(<4 x float>) nounwind readnone +declare i64 @llvm.x86.sse.cvtss2si64(<4 x float>) nounwind readnone +declare i64 @llvm.x86.sse.cvttss2si64(<4 x float>) nounwind readnone +declare i32 @llvm.x86.sse2.cvtsd2si(<2 x double>) nounwind readnone +declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) nounwind readnone +declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) nounwind readnone +declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) nounwind readnone From stoklund at 2pi.dk Mon Jan 10 19:18:03 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 11 Jan 2011 01:18:03 -0000 Subject: [llvm-commits] [llvm] r123207 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <20110111011803.383182A6C12C@llvm.org> Author: stoklund Date: Mon Jan 10 19:18:03 2011 New Revision: 123207 URL: http://llvm.org/viewvc/llvm-project?rev=123207&view=rev Log: Turn on memdep's verifyRemoved() in an attempt to smoke out the cause of our gcc bootstrap miscompare. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=123207&r1=123206&r2=123207&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Mon Jan 10 19:18:03 2011 @@ -1262,7 +1262,9 @@ assert(!NonLocalDeps.count(RemInst) && "RemInst got reinserted?"); AA->deleteValue(RemInst); - DEBUG(verifyRemoved(RemInst)); +#ifndef NDEBUG + verifyRemoved(RemInst); +#endif } /// verifyRemoved - Verify that the specified instruction does not occur /// in our internal data structures. From bigcheesegs at gmail.com Mon Jan 10 19:21:55 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Tue, 11 Jan 2011 01:21:55 -0000 Subject: [llvm-commits] [llvm] r123209 - in /llvm/trunk: include/llvm/Support/PathV1.h lib/Support/PathV2.cpp lib/Support/Unix/Path.inc lib/Support/Windows/Path.inc Message-ID: <20110111012155.B36FB2A6C12C@llvm.org> Author: mspencer Date: Mon Jan 10 19:21:55 2011 New Revision: 123209 URL: http://llvm.org/viewvc/llvm-project?rev=123209&view=rev Log: Support/Path: Deprecate PathV1::isDirectory and replace all uses with PathV2::is_directory. Modified: llvm/trunk/include/llvm/Support/PathV1.h llvm/trunk/lib/Support/PathV2.cpp llvm/trunk/lib/Support/Unix/Path.inc llvm/trunk/lib/Support/Windows/Path.inc Modified: llvm/trunk/include/llvm/Support/PathV1.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/PathV1.h?rev=123209&r1=123208&r2=123209&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/PathV1.h (original) +++ llvm/trunk/include/llvm/Support/PathV1.h Mon Jan 10 19:21:55 2011 @@ -387,7 +387,8 @@ /// existing directory. /// @returns true if the pathname references an existing directory. /// @brief Determines if the path is a directory in the file system. - bool isDirectory() const; + LLVM_ATTRIBUTE_DEPRECATED(bool isDirectory() const, + LLVM_PATH_DEPRECATED_MSG(fs::is_directory)); /// This function determines if the path name references an /// existing symbolic link. Modified: llvm/trunk/lib/Support/PathV2.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/PathV2.cpp?rev=123209&r1=123208&r2=123209&view=diff ============================================================================== --- llvm/trunk/lib/Support/PathV2.cpp (original) +++ llvm/trunk/lib/Support/PathV2.cpp Mon Jan 10 19:21:55 2011 @@ -636,10 +636,26 @@ return status.type() == file_type::directory_file; } +error_code is_directory(const Twine &path, bool &result) { + file_status st; + if (error_code ec = status(path, st)) + return ec; + result = is_directory(st); + return success; +} + bool is_regular_file(file_status status) { return status.type() == file_type::regular_file; } +error_code is_regular_file(const Twine &path, bool &result) { + file_status st; + if (error_code ec = status(path, st)) + return ec; + result = is_regular_file(st); + return success; +} + bool is_symlink(file_status status) { return status.type() == file_type::symlink_file; } Modified: llvm/trunk/lib/Support/Unix/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Unix/Path.inc?rev=123209&r1=123208&r2=123209&view=diff ============================================================================== --- llvm/trunk/lib/Support/Unix/Path.inc (original) +++ llvm/trunk/lib/Support/Unix/Path.inc Mon Jan 10 19:21:55 2011 @@ -823,7 +823,8 @@ Buf.resize(path.size()+8); char *FNBuffer = &Buf[0]; path.copy(FNBuffer,path.size()); - if (isDirectory()) + bool isdir; + if (!fs::is_directory(path, isdir) && isdir) strcpy(FNBuffer+path.size(), "/XXXXXX"); else strcpy(FNBuffer+path.size(), "-XXXXXX"); Modified: llvm/trunk/lib/Support/Windows/Path.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Windows/Path.inc?rev=123209&r1=123208&r2=123209&view=diff ============================================================================== --- llvm/trunk/lib/Support/Windows/Path.inc (original) +++ llvm/trunk/lib/Support/Windows/Path.inc Mon Jan 10 19:21:55 2011 @@ -410,9 +410,10 @@ bool Path::isRegularFile() const { - if (isDirectory()) + bool res; + if (fs::is_regular_file(path, res)) return false; - return true; + return res; } StringRef From stoklund at 2pi.dk Mon Jan 10 22:05:39 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 11 Jan 2011 04:05:39 -0000 Subject: [llvm-commits] [llvm] r123215 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <20110111040539.944C82A6C12C@llvm.org> Author: stoklund Date: Mon Jan 10 22:05:39 2011 New Revision: 123215 URL: http://llvm.org/viewvc/llvm-project?rev=123215&view=rev Log: Revert r123207: "Turn on memdep's verifyRemoved() in an attempt to smoke out the cause of our gcc bootstrap miscompare." It didn't. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=123215&r1=123214&r2=123215&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Mon Jan 10 22:05:39 2011 @@ -1262,9 +1262,7 @@ assert(!NonLocalDeps.count(RemInst) && "RemInst got reinserted?"); AA->deleteValue(RemInst); -#ifndef NDEBUG - verifyRemoved(RemInst); -#endif + DEBUG(verifyRemoved(RemInst)); } /// verifyRemoved - Verify that the specified instruction does not occur /// in our internal data structures. From nicholas at mxc.ca Mon Jan 10 22:47:28 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 10 Jan 2011 20:47:28 -0800 Subject: [llvm-commits] PATCH: instcombine switch on select of constants to br In-Reply-To: References: <893CFB3C-832C-4959-AE72-4186FCD61E99@gmail.com> <4D2A730F.2090207@mxc.ca> <130DB463-EF73-40A2-8166-5D3A014D9D12@gmail.com> Message-ID: <4D2BE0E0.7080006@mxc.ca> Alistair Lynn wrote: > Hi- > > On 10 Jan 2011, at 10:10, Frits van Bommel wrote: >> Please don't top-post. > > My apologies. > >> You're not updating PHI nodes in successors. You should call >> Succ->removePredecessor(BB) for each successor that is removed. > > Done. > >> Some edge cases: >> - The input values are different, and go to different successors. >> Fold into a conditional branch and keep exactly one copy of both >> successors. >> - The input values are different, but their successors are the same. >> Keep folding this into an unconditional branch, and remove all but one >> successor. In particular, note that the successor being jumped to will >> have multiple PHI entries for this predecessor, and only one of those >> may remain. > > I'm confused about that last point - the verifier claims that phi nodes > should have one and only one entry for each predecessor? Yes, but you can have the same block as a predecessor multiple times, in which case there must be one entry in the phi node for each edge from that pred. And yes, the verifier checks that all incoming values for a given pred match for the same pred block. :) Nick >> - The input values are equal, or both are caught by the default case. >> Remove all other successors and keep folding into unconditional >> branch. >> - Some successor blocks that are the successor of multiple switch >> cases which are all removed. >> - Some successor blocks that are the successor of multiple switch >> cases, some (but not all) of which are removed. >> >> Ideally your test cases should test each of these, with other edges >> (not from the switch) going to the successors and (used) PHI nodes >> there. > > Okay, tests updated. > >> Since all of this may enlarge the code, you may want to factor it out >> into a static helper function. You could use >> SimplifyIndirectBrOnSelect() as an example, but note that that one has >> some different edge cases (for instance, the successors it tries to >> remove may not actually be present). >> Maybe you can even share some code between that and your >> SimplifySwitchOnSelect()? You could probably factor out all of the >> code SimplifyIndirectBrOnSelect() uses to update successors[1] to a >> separate helper function; the indirectbr-specific edge cases shouldn't >> be reachable for a switch so it won't generate incorrect code. > > I've factored it out into a separate helper function, but it really didn't > inflate the code that much. Due to the many differences between > switch and indirectbr (I don't believe duplicate entries are allowed > in the successors list for indirectbr), I haven't factored out common > code between SimplifySwitchOnSelect and > SimplifyIndirectBrOnSelect, because there really isn't much. > > Alistair > > > > > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Tue Jan 11 00:44:41 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Jan 2011 06:44:41 -0000 Subject: [llvm-commits] [llvm] r123218 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <20110111064442.1BC002A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 00:44:41 2011 New Revision: 123218 URL: http://llvm.org/viewvc/llvm-project?rev=123218&view=rev Log: the GEP faq says that only inbounds geps are guaranteed to not overflow. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=123218&r1=123217&r2=123218&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jan 11 00:44:41 2011 @@ -2722,11 +2722,12 @@ HasNUW = true; if (OBO->hasNoSignedWrap()) HasNSW = true; - } else if (isa(BEValueV)) { + } else if (const GEPOperator *GEP = + dyn_cast(BEValueV)) { // If the increment is a GEP, then we know it won't perform an // unsigned overflow, because the address space cannot be // wrapped around. - HasNUW = true; + HasNUW |= GEP->isInBounds(); } const SCEV *StartVal = getSCEV(StartValueV); From fvbommel at gmail.com Tue Jan 11 01:36:25 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Tue, 11 Jan 2011 08:36:25 +0100 Subject: [llvm-commits] [llvm] r123218 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp In-Reply-To: <20110111064442.1BC002A6C12C@llvm.org> References: <20110111064442.1BC002A6C12C@llvm.org> Message-ID: On Tue, Jan 11, 2011 at 7:44 AM, Chris Lattner wrote: > the GEP faq says that only inbounds geps are guaranteed to not overflow. > - ? ? ? ? ? ? ?} else if (isa(BEValueV)) { > + ? ? ? ? ? ? ?} else if (const GEPOperator *GEP = > + ? ? ? ? ? ? ? ? ? ? ? ? ? ?dyn_cast(BEValueV)) { > ? ? ? ? ? ? ? ? // If the increment is a GEP, then we know it won't perform an s/a GEP/an inbounds GEP/ > ? ? ? ? ? ? ? ? // unsigned overflow, because the address space cannot be > ? ? ? ? ? ? ? ? // wrapped around. > - ? ? ? ? ? ? ? ?HasNUW = true; > + ? ? ? ? ? ? ? ?HasNUW |= GEP->isInBounds(); > ? ? ? ? ? ? ? } From geek4civic at gmail.com Tue Jan 11 01:44:05 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 11 Jan 2011 16:44:05 +0900 Subject: [llvm-commits] [Review request] Tweaking Win64 Codegen Message-ID: Hello, guys! I can build Win64 clang (by w64-clang selfhost) with my local patches. For my attempt, I found some issues on llvm; - stack allocation - shadow area - allocating stack beyond page boundary - allocating variable alloca(n) - varargs (caller and callee) - tailcall Essential patches are here; They just work, though, I am dubious of their style. Please please let me know any feedbacks. Next, I will propose w64-clang patches and 57 of CodeGen/X86 tests. Thank you, ...Takumi * 0001-Target-X86-Fix-whitespace.patch.txt * 0002-test-CodeGen-X86-Fix-whitespace.patch.txt Cosmetic changes. * 0003-lib-Target-X86-X86ISelLowering.cpp-Introduce-a-n.patch.txt No functional changes. for 0004. It introduces a new variable "IsWin64" instead of Subtarget->isWin64(). * 0004-Target-X86-Tweak-allocating-shadow-area-aka-home.patch.txt Let caller provide at least 4 x i64 allocation for callee(s). On leaf functions, shadow area is not allocated, to save stack usage. FIXME: I wonder if CCState had knowledge for minimum stack allocation. It resolves also PR8922, though, emitted code would not be optimal. * 0005-Target-X86-Tweak-alloca-and-add-a-testcase-for-m.patch.txt [PR8777][PR8778][PR8919] Introduce W64ALLOCA and emit one for w64. It reverts PR8919 and r122934. I assume mingw64 distro and FSF sources. * 0006-Target-X86-Tweak-va_arg-for-Win64-not-to-miss-ta.patch.txt When fixed args > 4, va_ptr(ap) would be missed. It just works but must be dirty, I think. * 0007-X86FrameInfo.cpp-X86RegisterInfo.cpp-Re-indent.-.patch.txt Cosmetic changes to apply 0009 easily. No functional changes. * 0008-TableGen-EDEmitter.cpp-Add-TCW64.patch.txt Let tablegen recognize new class GR_TCW64. * 0009-Target-X86-Tweak-win64-s-tailcall.patch.txt [PR8743] Introduce tailcall-w64 stuff. FIXME: eligibility of w64's tailcall might be loosen. -------------- next part -------------- From 949c925274e0e8a40238553c638335fd330c0c96 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Thu, 9 Dec 2010 20:15:03 +0900 Subject: [PATCH 1/9] Target/X86: Fix whitespace. --- lib/Target/X86/X86FrameLowering.cpp | 2 +- lib/Target/X86/X86ISelLowering.cpp | 94 +++++++++++++++++----------------- lib/Target/X86/X86InstrCompiler.td | 17 +++--- lib/Target/X86/X86InstrControl.td | 39 +++++++------- lib/Target/X86/X86InstrInfo.cpp | 84 +++++++++++++++--------------- lib/Target/X86/X86InstrInfo.td | 3 +- lib/Target/X86/X86MCInstLower.cpp | 65 ++++++++++++------------ lib/Target/X86/X86RegisterInfo.cpp | 6 +- lib/Target/X86/X86RegisterInfo.td | 24 +++++----- 9 files changed, 165 insertions(+), 169 deletions(-) diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index 7c7b4f3..cbf1b59 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -321,7 +321,7 @@ void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF, // move" for this extra "PUSH", the linker will lose track of the fact that // the frame pointer should have the value of the first "PUSH" when it's // trying to unwind. - // + // // FIXME: This looks inelegant. It's possibly correct, but it's covering up // another bug. I.e., one where we generate a prolog like this: // diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 1a4bb97..2268823 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -69,7 +69,7 @@ static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { return new X8664_MachoTargetObjectFile(); return new TargetLoweringObjectFileMachO(); } - + if (TM.getSubtarget().isTargetELF() ){ if (is64Bit) return new X8664_ELFTargetObjectFile(TM); @@ -256,7 +256,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::UDIV, VT, Expand); setOperationAction(ISD::SREM, VT, Expand); setOperationAction(ISD::UREM, VT, Expand); - + // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. setOperationAction(ISD::ADDC, VT, Custom); setOperationAction(ISD::ADDE, VT, Custom); @@ -369,7 +369,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); } - + if (!Subtarget->is64Bit()) { setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); @@ -931,7 +931,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // We want to custom lower some of our intrinsics. setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); - + // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't // handle type legalization for these operations here. // @@ -948,7 +948,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::SMULO, VT, Custom); setOperationAction(ISD::UMULO, VT, Custom); } - + // There are no 8-bit 3-address imul/mul instructions setOperationAction(ISD::SMULO, MVT::i8, Expand); setOperationAction(ISD::UMULO, MVT::i8, Expand); @@ -6198,7 +6198,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MFI->setAdjustsStack(true); - + // And our return value (tls address) is in the standard call return value // location. unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; @@ -7047,7 +7047,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { (cast(Op1)->getZExtValue() == 1 || cast(Op1)->isNullValue()) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { - + // If the input is a setcc, then reuse the input setcc or use a new one with // the inverted condition. if (Op0.getOpcode() == X86ISD::SETCC) { @@ -7055,7 +7055,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { bool Invert = (CC == ISD::SETNE) ^ cast(Op1)->isNullValue(); if (!Invert) return Op0; - + CCode = X86::GetOppositeBranchCondition(CCode); return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); @@ -7206,7 +7206,7 @@ static bool isX86LogicalCmp(SDValue Op) { if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) return true; - + return false; } @@ -7242,24 +7242,24 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { Cond.getOperand(1).getOpcode() == X86ISD::CMP && isZero(Cond.getOperand(1).getOperand(1))) { SDValue Cmp = Cond.getOperand(1); - + unsigned CondCode =cast(Cond.getOperand(0))->getZExtValue(); - - if ((isAllOnes(Op1) || isAllOnes(Op2)) && + + if ((isAllOnes(Op1) || isAllOnes(Op2)) && (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { SDValue Y = isAllOnes(Op2) ? Op1 : Op2; SDValue CmpOp0 = Cmp.getOperand(0); Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); - + SDValue Res = // Res = 0 or -1. DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), DAG.getConstant(X86::COND_B, MVT::i8), Cmp); - + if (isAllOnes(Op1) != (CondCode == X86::COND_E)) Res = DAG.getNOT(DL, Res, Res.getValueType()); - + ConstantSDNode *N2C = dyn_cast(Op2); if (N2C == 0 || !N2C->isNullValue()) Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); @@ -8443,7 +8443,7 @@ SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const { Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); // return pblendv(r, r+r, a); - R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, + R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op); return R; } @@ -8503,12 +8503,12 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), MVT::i32); SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); - + SDValue SetCC = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, DAG.getConstant(X86::COND_O, MVT::i32), SDValue(Sum.getNode(), 2)); - + DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); return Sum; } @@ -8663,9 +8663,9 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { // Let legalize expand this if it isn't a legal type yet. if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) return SDValue(); - + SDVTList VTs = DAG.getVTList(VT, MVT::i32); - + unsigned Opc; bool ExtraOp = false; switch (Op.getOpcode()) { @@ -8675,7 +8675,7 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { case ISD::SUBC: Opc = X86ISD::SUB; break; case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; } - + if (!ExtraOp) return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), Op.getOperand(1)); @@ -9555,14 +9555,14 @@ MachineBasicBlock * X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { DebugLoc dl = MI->getDebugLoc(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - + // Address into RAX/EAX, other two args into ECX, EDX. unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); for (int i = 0; i < X86::AddrNumOperands; ++i) MIB.addOperand(MI->getOperand(i)); - + unsigned ValOps = X86::AddrNumOperands; BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) .addReg(MI->getOperand(ValOps).getReg()); @@ -9571,7 +9571,7 @@ X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { // The instruction doesn't actually take any operands though. BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); - + MI->eraseFromParent(); // The pseudo is gone now. return BB; } @@ -9580,16 +9580,16 @@ MachineBasicBlock * X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { DebugLoc dl = MI->getDebugLoc(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - + // First arg in ECX, the second in EAX. BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) .addReg(MI->getOperand(0).getReg()); BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) .addReg(MI->getOperand(1).getReg()); - + // The instruction doesn't actually take any operands though. BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); - + MI->eraseFromParent(); // The pseudo is gone now. return BB; } @@ -10195,7 +10195,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // Thread synchronization. case X86::MONITOR: - return EmitMonitor(MI, BB); + return EmitMonitor(MI, BB); case X86::MWAIT: return EmitMwait(MI, BB); @@ -11116,19 +11116,19 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) { if (DCI.isBeforeLegalizeOps()) return SDValue(); - + // Want to form PANDN nodes, in the hopes of then easily combining them with // OR and AND nodes to form PBLEND/PSIGN. EVT VT = N->getValueType(0); if (VT != MVT::v2i64) return SDValue(); - + SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); DebugLoc DL = N->getDebugLoc(); - + // Check LHS for vnot - if (N0.getOpcode() == ISD::XOR && + if (N0.getOpcode() == ISD::XOR && ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) return DAG.getNode(X86ISD::PANDN, DL, VT, N0.getOperand(0), N1); @@ -11136,7 +11136,7 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, if (N1.getOpcode() == ISD::XOR && ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) return DAG.getNode(X86ISD::PANDN, DL, VT, N1.getOperand(0), N0); - + return SDValue(); } @@ -11152,7 +11152,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); - + // look for psign/blend if (Subtarget->hasSSSE3()) { if (VT == MVT::v2i64) { @@ -11168,17 +11168,17 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, Y = N0.getOperand(1); if (N0.getOperand(1) == Mask) Y = N0.getOperand(0); - + // Check to see if the mask appeared in both the AND and PANDN and if (!Y.getNode()) return SDValue(); - + // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. if (Mask.getOpcode() != ISD::BITCAST || X.getOpcode() != ISD::BITCAST || Y.getOpcode() != ISD::BITCAST) return SDValue(); - + // Look through mask bitcast. Mask = Mask.getOperand(0); EVT MaskVT = Mask.getValueType(); @@ -11187,7 +11187,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, // will be an intrinsic. if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) return SDValue(); - + // FIXME: what to do for bytes, since there is a psignb/pblendvb, but // there is no psrai.b switch (cast(Mask.getOperand(0))->getZExtValue()) { @@ -11196,14 +11196,14 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, break; default: return SDValue(); } - + // Check that the SRA is all signbits. SDValue SraC = Mask.getOperand(2); unsigned SraAmt = cast(SraC)->getZExtValue(); unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); if ((SraAmt + 1) != EltBits) return SDValue(); - + DebugLoc DL = N->getDebugLoc(); // Now we know we at least have a plendvb with the mask val. See if @@ -11229,7 +11229,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, // PBLENDVB only available on SSE 4.1 if (!Subtarget->hasSSE41()) return SDValue(); - + X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X); Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y); Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask); @@ -11238,7 +11238,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, } } } - + // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) std::swap(N0, N1); @@ -11290,7 +11290,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ShAmt0)); } - + return SDValue(); } @@ -11500,7 +11500,7 @@ static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { unsigned X86CC = N->getConstantOperandVal(0); SDValue EFLAG = N->getOperand(1); DebugLoc DL = N->getDebugLoc(); - + // Materialize "setb reg" as "sbb reg,reg", since it can be extended without // a zext and produces an all-ones bit which is more useful than 0/1 in some // cases. @@ -11509,10 +11509,10 @@ static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, DAG.getConstant(X86CC, MVT::i8), EFLAG), DAG.getConstant(1, MVT::i8)); - + return SDValue(); } - + // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, X86TargetLowering::DAGCombinerInfo &DCI) { @@ -11544,7 +11544,7 @@ static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, // (sub (setne X, 0), Y) -> adc -1, Y static SDValue OptimizeConditonalInDecrement(SDNode *N, SelectionDAG &DAG) { DebugLoc DL = N->getDebugLoc(); - + // Look through ZExts. SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td index da5e05a..d2c5763 100644 --- a/lib/Target/X86/X86InstrCompiler.td +++ b/lib/Target/X86/X86InstrCompiler.td @@ -849,38 +849,38 @@ def : Pat<(X86call (i64 texternalsym:$dst)), // tailcall stuff def : Pat<(X86tcret GR32_TC:$dst, imm:$off), (TCRETURNri GR32_TC:$dst, imm:$off)>, - Requires<[In32BitMode]>; + Requires<[In32BitMode]>; // FIXME: This is disabled for 32-bit PIC mode because the global base // register which is part of the address mode may be assigned a // callee-saved register. def : Pat<(X86tcret (load addr:$dst), imm:$off), (TCRETURNmi addr:$dst, imm:$off)>, - Requires<[In32BitMode, IsNotPIC]>; + Requires<[In32BitMode, IsNotPIC]>; def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), (TCRETURNdi texternalsym:$dst, imm:$off)>, - Requires<[In32BitMode]>; + Requires<[In32BitMode]>; def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), (TCRETURNdi texternalsym:$dst, imm:$off)>, - Requires<[In32BitMode]>; + Requires<[In32BitMode]>; def : Pat<(X86tcret GR64_TC:$dst, imm:$off), (TCRETURNri64 GR64_TC:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode]>; def : Pat<(X86tcret (load addr:$dst), imm:$off), (TCRETURNmi64 addr:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode]>; def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode]>; def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), (TCRETURNdi64 texternalsym:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode]>; // Normal calls, with various flavors of addresses. def : Pat<(X86call (i32 tglobaladdr:$dst)), @@ -1661,4 +1661,3 @@ def : Pat<(and GR64:$src1, i64immSExt8:$src2), (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; def : Pat<(and GR64:$src1, i64immSExt32:$src2), (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; - diff --git a/lib/Target/X86/X86InstrControl.td b/lib/Target/X86/X86InstrControl.td index 62ab53e..4d1c5f7 100644 --- a/lib/Target/X86/X86InstrControl.td +++ b/lib/Target/X86/X86InstrControl.td @@ -1,10 +1,10 @@ //===- X86InstrControl.td - Control Flow Instructions ------*- tablegen -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file describes the X86 jump, return, call, and related instructions. @@ -43,7 +43,7 @@ let isBarrier = 1, isBranch = 1, isTerminator = 1 in { "jmp\t$dst", [(br bb:$dst)]>; def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), "jmp\t$dst", []>; - def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst), + def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst), "jmp{q}\t$dst", []>; } @@ -108,16 +108,16 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>; - def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), + def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), (ins i16imm:$off, i16imm:$seg), "ljmp{w}\t{$seg, $off|$off, $seg}", []>, OpSize; def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), (ins i32imm:$off, i16imm:$seg), - "ljmp{l}\t{$seg, $off|$off, $seg}", []>; + "ljmp{l}\t{$seg, $off|$off, $seg}", []>; def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst), "ljmp{q}\t{*}$dst", []>; - def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), + def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), "ljmp{w}\t{*}$dst", []>, OpSize; def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst), "ljmp{l}\t{*}$dst", []>; @@ -152,14 +152,14 @@ let isCall = 1 in def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops), "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>, Requires<[In32BitMode]>; - - def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), + + def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), (ins i16imm:$off, i16imm:$seg), "lcall{w}\t{$seg, $off|$off, $seg}", []>, OpSize; def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), (ins i32imm:$off, i16imm:$seg), "lcall{l}\t{$seg, $off|$off, $seg}", []>; - + def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst), "lcall{w}\t{*}$dst", []>, OpSize; def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst), @@ -182,12 +182,12 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], Uses = [ESP] in { - def TCRETURNdi : PseudoI<(outs), + def TCRETURNdi : PseudoI<(outs), (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops), []>; - def TCRETURNri : PseudoI<(outs), + def TCRETURNri : PseudoI<(outs), (ins GR32_TC:$dst, i32imm:$offset, variable_ops), []>; let mayLoad = 1 in - def TCRETURNmi : PseudoI<(outs), + def TCRETURNmi : PseudoI<(outs), (ins i32mem_TC:$dst, i32imm:$offset, variable_ops), []>; // FIXME: The should be pseudo instructions that are lowered when going to @@ -196,7 +196,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, (ins i32imm_pcrel:$dst, variable_ops), "jmp\t$dst # TAILCALL", []>; - def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops), + def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops), "", []>; // FIXME: Remove encoding when JIT is dead. let mayLoad = 1 in def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops), @@ -218,7 +218,7 @@ let isCall = 1 in XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], Uses = [RSP] in { - + // NOTE: this pattern doesn't match "X86call imm", because we do not know // that the offset between an arbitrary immediate and the call will fit in // the 32-bit pcrel field that we have. @@ -232,12 +232,12 @@ let isCall = 1 in def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops), "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>, Requires<[In64BitMode, NotWin64]>; - + def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst), "lcall{q}\t{*}$dst", []>; } - // FIXME: We need to teach codegen about single list of call-clobbered + // FIXME: We need to teach codegen about single list of call-clobbered // registers. let isCall = 1, isCodeGenOnly = 1 in // All calls clobber the non-callee saved registers. RSP is marked as @@ -256,10 +256,10 @@ let isCall = 1, isCodeGenOnly = 1 in def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops), "call{q}\t{*}$dst", [(X86call GR64:$dst)]>, Requires<[IsWin64]>; - def WINCALL64m : I<0xFF, MRM2m, (outs), + def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst,variable_ops), "call{q}\t{*}$dst", - [(X86call (loadi64 addr:$dst))]>, + [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>; } @@ -278,7 +278,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, def TCRETURNri64 : PseudoI<(outs), (ins GR64_TC:$dst, i32imm:$offset, variable_ops), []>; let mayLoad = 1 in - def TCRETURNmi64 : PseudoI<(outs), + def TCRETURNmi64 : PseudoI<(outs), (ins i64mem_TC:$dst, i32imm:$offset, variable_ops), []>; def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), @@ -291,4 +291,3 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops), "jmp{q}\t{*}$dst # TAILCALL", []>; } - diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 73654d3..63dcd14 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -58,7 +58,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) TB_NOT_REVERSABLE = 1U << 31, TB_FLAGS = TB_NOT_REVERSABLE }; - + static const unsigned OpTbl2Addr[][2] = { { X86::ADC32ri, X86::ADC32mi }, { X86::ADC32ri8, X86::ADC32mi8 }, @@ -231,16 +231,16 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) unsigned MemOp = OpTbl2Addr[i][1] & ~TB_FLAGS; assert(!RegOp2MemOpTable2Addr.count(RegOp) && "Duplicated entries?"); RegOp2MemOpTable2Addr[RegOp] = std::make_pair(MemOp, 0U); - + // If this is not a reversable operation (because there is a many->one) // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. if (OpTbl2Addr[i][1] & TB_NOT_REVERSABLE) continue; - + // Index 0, folded load and store, no alignment requirement. unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); - - assert(!MemOp2RegOpTable.count(MemOp) && + + assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries in unfolding maps?"); MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo); } @@ -334,12 +334,12 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) unsigned Align = OpTbl0[i][3]; assert(!RegOp2MemOpTable0.count(RegOp) && "Duplicated entries?"); RegOp2MemOpTable0[RegOp] = std::make_pair(MemOp, Align); - + // If this is not a reversable operation (because there is a many->one) // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. if (OpTbl0[i][1] & TB_NOT_REVERSABLE) continue; - + // Index 0, folded load or store. unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries?"); @@ -461,12 +461,12 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) unsigned Align = OpTbl1[i][2]; assert(!RegOp2MemOpTable1.count(RegOp) && "Duplicate entries"); RegOp2MemOpTable1[RegOp] = std::make_pair(MemOp, Align); - + // If this is not a reversable operation (because there is a many->one) // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. if (OpTbl1[i][1] & TB_NOT_REVERSABLE) continue; - + // Index 1, folded load unsigned AuxInfo = 1 | (1 << 4); assert(!MemOp2RegOpTable.count(MemOp) && "Duplicate entries"); @@ -678,15 +678,15 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) unsigned RegOp = OpTbl2[i][0]; unsigned MemOp = OpTbl2[i][1] & ~TB_FLAGS; unsigned Align = OpTbl2[i][2]; - + assert(!RegOp2MemOpTable2.count(RegOp) && "Duplicate entry!"); RegOp2MemOpTable2[RegOp] = std::make_pair(MemOp, Align); - + // If this is not a reversable operation (because there is a many->one) // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. if (OpTbl2[i][1] & TB_NOT_REVERSABLE) continue; - + // Index 2, folded load unsigned AuxInfo = 2 | (1 << 4); assert(!MemOp2RegOpTable.count(MemOp) && @@ -808,7 +808,7 @@ static bool isFrameStoreOpcode(int Opcode) { return false; } -unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, +unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { if (isFrameLoadOpcode(MI->getOpcode())) if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) @@ -816,7 +816,7 @@ unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, return 0; } -unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, +unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const { if (isFrameLoadOpcode(MI->getOpcode())) { unsigned Reg; @@ -946,10 +946,10 @@ X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, isPICBase = true; } return isPICBase; - } + } return false; } - + case X86::LEA32r: case X86::LEA64r: { if (MI->getOperand(2).isImm() && @@ -1124,9 +1124,9 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); - + // Build and insert into an implicit UNDEF value. This is OK because - // well be shifting and then extracting the lower 16-bits. + // well be shifting and then extracting the lower 16-bits. // This has the potential to cause partial register stall. e.g. // movw (%rbp,%rcx,2), %dx // leal -65(%rdx), %esi @@ -1162,7 +1162,7 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, case X86::ADD16ri8: case X86::ADD16ri_DB: case X86::ADD16ri8_DB: - addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); + addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); break; case X86::ADD16rr: case X86::ADD16rr_DB: { @@ -1177,7 +1177,7 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, } else { leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); // Build and insert into an implicit UNDEF value. This is OK because - // well be shifting and then extracting the lower 16-bits. + // well be shifting and then extracting the lower 16-bits. BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2); InsMI2 = BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) @@ -1244,7 +1244,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, case X86::SHUFPSrri: { assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); if (!TM.getSubtarget().hasSSE2()) return 0; - + unsigned B = MI->getOperand(1).getReg(); unsigned C = MI->getOperand(2).getReg(); if (B != C) return 0; @@ -1392,7 +1392,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, RC = X86::GR32_NOSPRegisterClass; } - + unsigned Src2 = MI->getOperand(2).getReg(); bool isKill2 = MI->getOperand(2).isKill(); @@ -1471,7 +1471,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, LV->replaceKillInstruction(Dest, MI, NewMI); } - MFI->insert(MBBI, NewMI); // Insert the new inst + MFI->insert(MBBI, NewMI); // Insert the new inst return NewMI; } @@ -1692,7 +1692,7 @@ X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { const TargetInstrDesc &TID = MI->getDesc(); if (!TID.isTerminator()) return false; - + // Conditional branch is a special case. if (TID.isBranch() && !TID.isBarrier()) return true; @@ -1701,7 +1701,7 @@ bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { return !isPredicated(MI); } -bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, @@ -1862,7 +1862,7 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { I = MBB.end(); ++Count; } - + return Count; } @@ -2177,7 +2177,7 @@ static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, MIB.addOperand(MOs[i]); if (NumAddrOps < 4) // FrameIndex only addOffset(MIB, 0); - + // Loop over the rest of the ri operands, converting them over. unsigned NumOps = MI->getDesc().getNumOperands()-2; for (unsigned i = 0; i != NumOps; ++i) { @@ -2198,7 +2198,7 @@ static MachineInstr *FuseInst(MachineFunction &MF, MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), MI->getDebugLoc(), true); MachineInstrBuilder MIB(NewMI); - + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (i == OpNo) { @@ -2247,7 +2247,7 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (isTwoAddr && NumOps >= 2 && i < 2 && MI->getOperand(0).isReg() && MI->getOperand(1).isReg() && - MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { + MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { OpcodeTablePtr = &RegOp2MemOpTable2Addr; isTwoAddrFold = true; } else if (i == 0) { // If operand 0 @@ -2261,14 +2261,14 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); if (NewMI) return NewMI; - + OpcodeTablePtr = &RegOp2MemOpTable0; } else if (i == 1) { OpcodeTablePtr = &RegOp2MemOpTable1; } else if (i == 2) { OpcodeTablePtr = &RegOp2MemOpTable2; } - + // If table selected... if (OpcodeTablePtr) { // Find the Opcode to fuse @@ -2316,8 +2316,8 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, return NewMI; } } - - // No fusion + + // No fusion if (PrintFailedFusing && !MI->isCopy()) dbgs() << "We failed to fuse operand " << i << " in " << *MI; return NULL; @@ -2328,7 +2328,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl &Ops, int FrameIndex) const { - // Check switch flag + // Check switch flag if (NoFusing) return NULL; if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) @@ -2380,7 +2380,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl &Ops, MachineInstr *LoadMI) const { - // Check switch flag + // Check switch flag if (NoFusing) return NULL; if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) @@ -2523,13 +2523,13 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl &Ops) const { - // Check switch flag + // Check switch flag if (NoFusing) return 0; if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { switch (MI->getOpcode()) { default: return false; - case X86::TEST8rr: + case X86::TEST8rr: case X86::TEST16rr: case X86::TEST32rr: case X86::TEST64rr: @@ -2550,7 +2550,7 @@ bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, // instruction is different than folding it other places. It requires // replacing the *two* registers with the memory location. const DenseMap > *OpcodeTablePtr = 0; - if (isTwoAddr && NumOps >= 2 && OpNum < 2) { + if (isTwoAddr && NumOps >= 2 && OpNum < 2) { OpcodeTablePtr = &RegOp2MemOpTable2Addr; } else if (OpNum == 0) { // If operand 0 switch (Opc) { @@ -2566,7 +2566,7 @@ bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, } else if (OpNum == 2) { OpcodeTablePtr = &RegOp2MemOpTable2; } - + if (OpcodeTablePtr && OpcodeTablePtr->count(Opc)) return true; return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops); @@ -2636,7 +2636,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, // Emit the data processing instruction. MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true); MachineInstrBuilder MIB(DataMI); - + if (FoldedStore) MIB.addReg(Reg, RegState::Define); for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) @@ -3156,11 +3156,11 @@ namespace { PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); else PC = GlobalBaseReg; - + // Operand of MovePCtoStack is completely ignored by asm printer. It's // only used in JIT code emission as displacement to pc. BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); - + // If we're using vanilla 'GOT' PIC style, we should use relative addressing // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. if (TM->getSubtarget().isPICStyleGOT()) { diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index f9c0a7b..4748f13 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -36,7 +36,7 @@ def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, SDTCisSameAs<0, 3>, SDTCisInt<0>, SDTCisVT<1, i32>]>; -// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS +// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, @@ -1612,4 +1612,3 @@ def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>; def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>; def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>; def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>; - diff --git a/lib/Target/X86/X86MCInstLower.cpp b/lib/Target/X86/X86MCInstLower.cpp index cbe6db2..4159af1 100644 --- a/lib/Target/X86/X86MCInstLower.cpp +++ b/lib/Target/X86/X86MCInstLower.cpp @@ -46,12 +46,12 @@ GetSymbolFromOperand(const MachineOperand &MO) const { assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference"); SmallString<128> Name; - + if (!MO.isGlobal()) { assert(MO.isSymbol()); Name += MAI.getGlobalPrefix(); Name += MO.getSymbolName(); - } else { + } else { const GlobalValue *GV = MO.getGlobal(); bool isImplicitlyPrivate = false; if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB || @@ -59,7 +59,7 @@ GetSymbolFromOperand(const MachineOperand &MO) const { MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE || MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE) isImplicitlyPrivate = true; - + Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate); } @@ -110,7 +110,7 @@ GetSymbolFromOperand(const MachineOperand &MO) const { getMachOMMI().getFnStubEntry(Sym); if (StubSym.getPointer()) return Sym; - + if (MO.isGlobal()) { StubSym = MachineModuleInfoImpl:: @@ -135,7 +135,7 @@ MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, // lot of extra uniquing. const MCExpr *Expr = 0; MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; - + switch (MO.getTargetFlags()) { default: llvm_unreachable("Unknown target flag on GV operand"); case X86II::MO_NO_FLAG: // No flag. @@ -144,7 +144,7 @@ MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, case X86II::MO_DLLIMPORT: case X86II::MO_DARWIN_STUB: break; - + case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break; case X86II::MO_TLVP_PIC_BASE: Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); @@ -168,7 +168,7 @@ MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: Expr = MCSymbolRefExpr::Create(Sym, Ctx); // Subtract the pic base. - Expr = MCBinaryExpr::CreateSub(Expr, + Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx), Ctx); if (MO.isJTI() && MAI.hasSetDirective()) { @@ -182,10 +182,10 @@ MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, } break; } - + if (Expr == 0) Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx); - + if (!MO.isJTI() && MO.getOffset()) Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(MO.getOffset(), Ctx), @@ -206,10 +206,10 @@ static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) { // Convert registers in the addr mode according to subreg64. for (unsigned i = 0; i != 4; ++i) { if (!MI->getOperand(OpNo+i).isReg()) continue; - + unsigned Reg = MI->getOperand(OpNo+i).getReg(); if (Reg == 0) continue; - + MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64)); } } @@ -274,7 +274,7 @@ static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, return; // Check whether this is an absolute address. - // FIXME: We know TLVP symbol refs aren't, but there should be a better way + // FIXME: We know TLVP symbol refs aren't, but there should be a better way // to do this here. bool Absolute = true; if (Inst.getOperand(AddrOp).isExpr()) { @@ -283,7 +283,7 @@ static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) Absolute = false; } - + if (Absolute && (Inst.getOperand(AddrBase + 0).getReg() != 0 || Inst.getOperand(AddrBase + 2).getReg() != 0 || @@ -300,10 +300,10 @@ static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { OutMI.setOpcode(MI->getOpcode()); - + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - + MCOperand MCOp; switch (MO.getType()) { default: @@ -336,10 +336,10 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); break; } - + OutMI.addOperand(MCOp); } - + // Handle a few special cases to eliminate operand modifiers. ReSimplify: switch (OutMI.getOpcode()) { @@ -429,7 +429,7 @@ ReSimplify: case X86::TAILJMPd: case X86::TAILJMPd64: Opcode = X86::JMP_1; break; } - + MCOperand Saved = OutMI.getOperand(0); OutMI = MCInst(); OutMI.setOpcode(Opcode); @@ -449,7 +449,7 @@ ReSimplify: case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; - + // The assembler backend wants to see branches in their small form and relax // them to their large form. The JIT can only handle the large form because // it does not do relaxation. For now, translate the large form to the @@ -605,7 +605,7 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { if (OutStreamer.hasRawTextSupport()) OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER")); return; - + case X86::EH_RETURN: case X86::EH_RETURN64: { @@ -633,7 +633,7 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { // call "L1$pb" // "L1$pb": // popl %esi - + // Emit the call. MCSymbol *PICBase = MF->getPICBaseSymbol(); TmpInst.setOpcode(X86::CALLpcrel32); @@ -642,43 +642,43 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase, OutContext))); OutStreamer.EmitInstruction(TmpInst); - + // Emit the label. OutStreamer.EmitLabel(PICBase); - + // popl $reg TmpInst.setOpcode(X86::POP32r); TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg()); OutStreamer.EmitInstruction(TmpInst); return; } - + case X86::ADD32ri: { // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) break; - + // Okay, we have something like: // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) - + // For this, we want to print something like: // MYGLOBAL + (. - PICBASE) // However, we can't generate a ".", so just emit a new label here and refer // to it. MCSymbol *DotSym = OutContext.CreateTempSymbol(); OutStreamer.EmitLabel(DotSym); - + // Now that we have emitted the label, lower the complex operand expression. MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); - + const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); const MCExpr *PICBase = MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext); DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext); - - DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext), + + DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext), DotExpr, OutContext); - + MCInst TmpInst; TmpInst.setOpcode(X86::ADD32ri); TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); @@ -688,9 +688,8 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } } - + MCInst TmpInst; MCInstLowering.Lower(MI, TmpInst); OutStreamer.EmitInstruction(TmpInst); } - diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 1faf6d9..06c671b 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -445,11 +445,11 @@ bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const { if (0 && requiresRealignment && MFI->hasVarSizedObjects()) report_fatal_error( "Stack realignment in presense of dynamic allocas is not supported"); - + // If we've requested that we force align the stack do so now. if (ForceStackAlign) return canRealignStack(MF); - + return requiresRealignment && canRealignStack(MF); } @@ -524,7 +524,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, // Factor out the amount the callee already popped. Amount -= CalleeAmt; - + if (Amount) { unsigned Opc = getADDriOpcode(Is64Bit, Amount); New = BuildMI(MF, DL, TII.get(Opc), StackPtr) diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index dc4c042..45bb989 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -1,10 +1,10 @@ //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file describes the X86 Register file, defining the registers themselves, @@ -34,8 +34,8 @@ let Namespace = "X86" in { // because the register file generator is smart enough to figure out that // AL aliases AX if we tell it that AX aliased AL (for example). - // Dwarf numbering is different for 32-bit and 64-bit, and there are - // variations by target as well. Currently the first entry is for X86-64, + // Dwarf numbering is different for 32-bit and 64-bit, and there are + // variations by target as well. Currently the first entry is for X86-64, // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux // and debug information on X86-32/Darwin) @@ -81,7 +81,7 @@ let Namespace = "X86" in { def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>; } def IP : Register<"ip">, DwarfRegNum<[16]>; - + // X86-64 only let SubRegIndices = [sub_8bit] in { def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>; @@ -103,8 +103,8 @@ let Namespace = "X86" in { def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>; def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>; def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>; - def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>; - + def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>; + // X86-64 only def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>; def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>; @@ -208,7 +208,7 @@ let Namespace = "X86" in { def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>; def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>; def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>; - def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>; + def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>; // Status flags register def EFLAGS : Register<"flags">; @@ -220,7 +220,7 @@ let Namespace = "X86" in { def ES : Register<"es">; def FS : Register<"fs">; def GS : Register<"gs">; - + // Debug registers def DR0 : Register<"dr0">; def DR1 : Register<"dr1">; @@ -230,7 +230,7 @@ let Namespace = "X86" in { def DR5 : Register<"dr5">; def DR6 : Register<"dr6">; def DR7 : Register<"dr7">; - + // Control registers def CR0 : Register<"cr0">; def CR1 : Register<"cr1">; @@ -261,10 +261,10 @@ let Namespace = "X86" in { // implicitly defined to be the register allocation order. // -// List call-clobbered registers before callee-save registers. RBX, RBP, (and +// List call-clobbered registers before callee-save registers. RBX, RBP, (and // R12, R13, R14, and R15 for X86-64) are callee-save registers. // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and -// R8B, ... R15B. +// R8B, ... R15B. // Allocate R12 and R13 last, as these require an extra byte when // encoded in x86_64 instructions. // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in -- 1.7.1.GIT -------------- next part -------------- From ed62d827ef015cb8abdb58ae4606ae6b03bff481 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Fri, 7 Jan 2011 10:58:30 +0900 Subject: [PATCH 2/9] test/CodeGen/X86: Fix whitespace. --- test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll | 5 ++--- test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll | 5 ++--- test/CodeGen/X86/tailcallstack64.ll | 1 - test/CodeGen/X86/win64_vararg.ll | 10 +++++----- 4 files changed, 9 insertions(+), 12 deletions(-) diff --git a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll index c598228..c5d3ac1 100644 --- a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll +++ b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll @@ -3,7 +3,6 @@ target triple = "x86_64-pc-mingw64" define x86_fp80 @a(i64 %x) nounwind readnone { entry: - %conv = sitofp i64 %x to x86_fp80 ; [#uses=1] - ret x86_fp80 %conv + %conv = sitofp i64 %x to x86_fp80 ; [#uses=1] + ret x86_fp80 %conv } - diff --git a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll index 810a6f4..b722589 100644 --- a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll +++ b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll @@ -6,7 +6,6 @@ target triple = "x86_64-pc-mingw64" define i32 @a() nounwind { entry: - tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind - ret i32 undef + tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind + ret i32 undef } - diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll index 107bdf9..52b074d 100644 --- a/test/CodeGen/X86/tailcallstack64.ll +++ b/test/CodeGen/X86/tailcallstack64.ll @@ -22,4 +22,3 @@ entry: %retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp) ret i32 %retval } - diff --git a/test/CodeGen/X86/win64_vararg.ll b/test/CodeGen/X86/win64_vararg.ll index 072f36a..71b2fa1 100644 --- a/test/CodeGen/X86/win64_vararg.ll +++ b/test/CodeGen/X86/win64_vararg.ll @@ -5,11 +5,11 @@ ; calculated. define void @average_va(i32 %count, ...) nounwind { entry: -; CHECK: subq $40, %rsp -; CHECK: movq %r9, 72(%rsp) -; CHECK: movq %r8, 64(%rsp) -; CHECK: movq %rdx, 56(%rsp) -; CHECK: leaq 56(%rsp), %rax +; CHECK: subq $40, %rsp +; CHECK: movq %r9, 72(%rsp) +; CHECK: movq %r8, 64(%rsp) +; CHECK: movq %rdx, 56(%rsp) +; CHECK: leaq 56(%rsp), %rax %ap = alloca i8*, align 8 ; [#uses=1] %ap1 = bitcast i8** %ap to i8* ; [#uses=1] -- 1.7.1.GIT -------------- next part -------------- From 1bca7c8f8b750651827b9e045c93ff66afed4bdf Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Mon, 10 Jan 2011 13:19:04 +0900 Subject: [PATCH 3/9] lib/Target/X86/X86ISelLowering.cpp: Introduce a new variable "IsWin64". No functional changes. --- lib/Target/X86/X86ISelLowering.cpp | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 2268823..3f1bed1 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1863,6 +1863,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, SmallVectorImpl &InVals) const { MachineFunction &MF = DAG.getMachineFunction(); bool Is64Bit = Subtarget->is64Bit(); + bool IsWin64 = Subtarget->isTargetWin64(); bool IsStructRet = CallIsStructReturn(Outs); bool IsSibcall = false; @@ -1970,7 +1971,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); - if (isVarArg && Subtarget->isTargetWin64()) { + if (isVarArg && IsWin64) { // Win64 ABI requires argument XMM reg to be copied to the corresponding // shadow reg if callee is a varargs function. unsigned ShadowReg = 0; @@ -2036,7 +2037,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, } } - if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) { + if (Is64Bit && isVarArg && !IsWin64) { // From AMD64 ABI document: // For calls that may call functions that use varargs or stdargs // (prototype-less calls or calls to functions containing ellipsis (...) in @@ -2211,7 +2212,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. - if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) + if (Is64Bit && isVarArg && !IsWin64) Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); if (InFlag.getNode()) -- 1.7.1.GIT -------------- next part -------------- From 674c32b4785d1bbc146b032735bdc021475cfef0 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Mon, 13 Dec 2010 17:59:20 +0900 Subject: [PATCH 4/9] Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be enough for caller to allocate one. --- lib/Target/X86/X86FrameLowering.cpp | 5 ---- lib/Target/X86/X86FrameLowering.h | 3 +- lib/Target/X86/X86ISelLowering.cpp | 21 ++++++++++++++++++- test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll | 4 +- test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll | 9 +++---- test/CodeGen/X86/win64_params.ll | 4 +- test/CodeGen/X86/win64_vararg.ll | 10 ++++---- 7 files changed, 33 insertions(+), 23 deletions(-) diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index cbf1b59..71fd8d1 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -400,11 +400,6 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const { if (HasFP) MinSize += SlotSize; StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0); MFI->setStackSize(StackSize); - } else if (IsWin64) { - // We need to always allocate 32 bytes as register spill area. - // FIXME: We might reuse these 32 bytes for leaf functions. - StackSize += 32; - MFI->setStackSize(StackSize); } // Insert stack pointer adjustment for later moving of return addr. Only diff --git a/lib/Target/X86/X86FrameLowering.h b/lib/Target/X86/X86FrameLowering.h index c067e64..d71108c 100644 --- a/lib/Target/X86/X86FrameLowering.h +++ b/lib/Target/X86/X86FrameLowering.h @@ -28,8 +28,7 @@ public: explicit X86FrameLowering(const X86TargetMachine &tm, const X86Subtarget &sti) : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), - (sti.isTargetWin64() ? -40 : - (sti.is64Bit() ? -8 : -4))), + (sti.is64Bit() ? -8 : -4)), TM(tm), STI(sti) { } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 3f1bed1..d3213de 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1569,6 +1569,12 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, SmallVector ArgLocs; CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); + + // Allocate shadow area for Win64 + if (IsWin64) { + CCInfo.AllocateStack(32, 8); + } + CCInfo.AnalyzeFormalArguments(Ins, CC_X86); unsigned LastVal = ~0U; @@ -1803,8 +1809,7 @@ X86TargetLowering::LowerMemOpCallTo(SDValue Chain, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const { - const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); - unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); + unsigned LocMemOffset = VA.getLocMemOffset(); SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); if (Flags.isByVal()) @@ -1889,6 +1894,12 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, SmallVector ArgLocs; CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); + + // Allocate shadow area for Win64 + if (IsWin64) { + CCInfo.AllocateStack(32, 8); + } + CCInfo.AnalyzeCallOperands(Outs, CC_X86); // Get a count of how many bytes are to be pushed on the stack. @@ -2472,6 +2483,12 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, SmallVector ArgLocs; CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); + + // Allocate shadow area for Win64 + if (Subtarget->isTargetWin64()) { + CCInfo.AllocateStack(32, 8); + } + CCInfo.AnalyzeCallOperands(Outs, CC_X86); if (CCInfo.getNextStackOffset()) { MachineFunction &MF = DAG.getMachineFunction(); diff --git a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll index c5d3ac1..9d06a9e 100644 --- a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll +++ b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s | grep "subq.*\\\$40, \\\%rsp" -target triple = "x86_64-pc-mingw64" +; RUN: llc -mtriple=x86_64-pc-mingw64 < %s | FileCheck %s +; CHECK-NOT: -{{[1-9][0-9]*}}(%rsp) define x86_fp80 @a(i64 %x) nounwind readnone { entry: diff --git a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll index b722589..6e8d9a9 100644 --- a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll +++ b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll @@ -1,8 +1,7 @@ -; RUN: llc < %s -o %t1 -; RUN: grep "subq.*\\\$72, \\\%rsp" %t1 -; RUN: grep "movaps \\\%xmm8, 32\\\(\\\%rsp\\\)" %t1 -; RUN: grep "movaps \\\%xmm7, 48\\\(\\\%rsp\\\)" %t1 -target triple = "x86_64-pc-mingw64" +; RUN: llc -mtriple=x86_64-pc-mingw64 < %s | FileCheck %s +; CHECK: subq $40, %rsp +; CHECK: movaps %xmm8, (%rsp) +; CHECK: movaps %xmm7, 16(%rsp) define i32 @a() nounwind { entry: diff --git a/test/CodeGen/X86/win64_params.ll b/test/CodeGen/X86/win64_params.ll index 0b67368..f9d4bf9 100644 --- a/test/CodeGen/X86/win64_params.ll +++ b/test/CodeGen/X86/win64_params.ll @@ -4,8 +4,8 @@ ; on the stack. define i32 @f6(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind readnone optsize { entry: -; CHECK: movl 80(%rsp), %eax -; CHECK: addl 72(%rsp), %eax +; CHECK: movl 48(%rsp), %eax +; CHECK: addl 40(%rsp), %eax %add = add nsw i32 %p6, %p5 ret i32 %add } diff --git a/test/CodeGen/X86/win64_vararg.ll b/test/CodeGen/X86/win64_vararg.ll index 71b2fa1..a451318 100644 --- a/test/CodeGen/X86/win64_vararg.ll +++ b/test/CodeGen/X86/win64_vararg.ll @@ -5,11 +5,11 @@ ; calculated. define void @average_va(i32 %count, ...) nounwind { entry: -; CHECK: subq $40, %rsp -; CHECK: movq %r9, 72(%rsp) -; CHECK: movq %r8, 64(%rsp) -; CHECK: movq %rdx, 56(%rsp) -; CHECK: leaq 56(%rsp), %rax +; CHECK: pushq +; CHECK: movq %r9, 40(%rsp) +; CHECK: movq %r8, 32(%rsp) +; CHECK: movq %rdx, 24(%rsp) +; CHECK: leaq 24(%rsp), %rax %ap = alloca i8*, align 8 ; [#uses=1] %ap1 = bitcast i8** %ap to i8* ; [#uses=1] -- 1.7.1.GIT -------------- next part -------------- From 6d3c586594c36faa5244c982c7068dac18931a63 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Mon, 13 Dec 2010 18:11:31 +0900 Subject: [PATCH 5/9] Target/X86: Tweak alloca and add a testcase for mingw64 and msvcrt on Win64. [PR8778] --- lib/Target/X86/X86FrameLowering.cpp | 19 +++++++-- lib/Target/X86/X86ISelLowering.cpp | 57 +++++++++++++++++++-------- lib/Target/X86/X86InstrControl.td | 10 +++++ test/CodeGen/X86/win64_alloca_dynalloca.ll | 56 +++++++++++++++++++++++++++ test/CodeGen/X86/win_chkstk.ll | 2 +- 5 files changed, 121 insertions(+), 23 deletions(-) create mode 100644 test/CodeGen/X86/win64_alloca_dynalloca.ll diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index 71fd8d1..ce88169 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -555,14 +555,23 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const { // responsible for adjusting the stack pointer. Touching the stack at 4K // increments is necessary to ensure that the guard pages used by the OS // virtual memory manager are allocated in correct sequence. - if (NumBytes >= 4096 && (STI.isTargetCygMing() || STI.isTargetWin32())) { + if (NumBytes >= 4096 && Is64Bit && STI.isTargetCygMing()) { + // Sanity check that EAX is not livein for this function. It should + // should not be, so throw an assert. + assert(!isEAXLiveIn(MF) && "EAX is livein in the Cygming64 case!"); + + BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) + .addImm(NumBytes); + BuildMI(MBB, MBBI, DL, TII.get(X86::W64ALLOCA)) + .addExternalSymbol("___chkstk") + .addReg(StackPtr, RegState::Define | RegState::Implicit); + // Cygming's ___chkstk adjusts %rsp. + } else if (NumBytes >= 4096 && (STI.isTargetCygMing() || STI.isTargetWin32())) { // Check whether EAX is livein for this function. bool isEAXAlive = isEAXLiveIn(MF); const char *StackProbeSymbol = STI.isTargetWindows() ? "_chkstk" : "_alloca"; - if (Is64Bit && STI.isTargetCygMing()) - StackProbeSymbol = "__chkstk"; unsigned CallOp = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32; if (!isEAXAlive) { BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) @@ -598,9 +607,9 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const { // Handle the 64-bit Windows ABI case where we need to call __chkstk. // Function prologue is responsible for adjusting the stack pointer. - BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) + BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) .addImm(NumBytes); - BuildMI(MBB, MBBI, DL, TII.get(X86::WINCALL64pcrel32)) + BuildMI(MBB, MBBI, DL, TII.get(X86::W64ALLOCA)) .addExternalSymbol("__chkstk") .addReg(StackPtr, RegState::Define | RegState::Implicit); emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d3213de..a012ae2 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -418,12 +418,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); - if (Subtarget->is64Bit()) - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); - if (Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); - else - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, + (Subtarget->is64Bit() ? MVT::i64 : MVT::i32), + (Subtarget->isTargetCOFF() ? Custom : Expand)); if (!UseSoftFloat && X86ScalarSSEf64) { // f32 and f64 use SSE. @@ -7553,8 +7550,9 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SDValue Flag; EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; + unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); - Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); + Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); Flag = Chain.getValue(1); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); @@ -10022,19 +10020,44 @@ X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, // The lowering is pretty easy: we're just emitting the call to _alloca. The // non-trivial part is impdef of ESP. - // FIXME: The code should be tweaked as soon as we'll try to do codegen for - // mingw-w64. - const char *StackProbeSymbol = + if (Subtarget->isTargetWin64()) { + if (Subtarget->isTargetCygMing()) { + // ___chkstk(Mingw64): + // Clobbers R10, R11, RAX and EFLAGS. + // Updates RSP. + BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) + .addExternalSymbol("___chkstk") + .addReg(X86::RAX, RegState::Implicit) + .addReg(X86::RSP, RegState::Implicit) + .addReg(X86::RAX, RegState::Define | RegState::Implicit) + .addReg(X86::RSP, RegState::Define | RegState::Implicit) + .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); + } else { + // __chkstk(MSVCRT): does not update stack pointer. + // Clobbers R10, R11 and EFLAGS. + // FIXME: RAX(allocated size) might be reused and not killed. + BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) + .addExternalSymbol("__chkstk") + .addReg(X86::RAX, RegState::Implicit) + .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); + // RAX has the offset to subtracted from RSP. + BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) + .addReg(X86::RSP) + .addReg(X86::RAX); + } + } else { + const char *StackProbeSymbol = Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; - BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) - .addExternalSymbol(StackProbeSymbol) - .addReg(X86::EAX, RegState::Implicit) - .addReg(X86::ESP, RegState::Implicit) - .addReg(X86::EAX, RegState::Define | RegState::Implicit) - .addReg(X86::ESP, RegState::Define | RegState::Implicit) - .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); + BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) + .addExternalSymbol(StackProbeSymbol) + .addReg(X86::EAX, RegState::Implicit) + .addReg(X86::ESP, RegState::Implicit) + .addReg(X86::EAX, RegState::Define | RegState::Implicit) + .addReg(X86::ESP, RegState::Define | RegState::Implicit) + .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); + } MI->eraseFromParent(); // The pseudo instruction is gone now. return BB; diff --git a/lib/Target/X86/X86InstrControl.td b/lib/Target/X86/X86InstrControl.td index 4d1c5f7..31f2832 100644 --- a/lib/Target/X86/X86InstrControl.td +++ b/lib/Target/X86/X86InstrControl.td @@ -263,6 +263,16 @@ let isCall = 1, isCodeGenOnly = 1 in Requires<[IsWin64]>; } +let isCall = 1, isCodeGenOnly = 1 in + // __chkstk(MSVC): clobber R10, R11 and EFLAGS. + // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP. + let Defs = [RAX, R10, R11, RSP, EFLAGS], + Uses = [RSP] in { + def W64ALLOCA : Ii32PCRel<0xE8, RawFrm, + (outs), (ins i64i32imm_pcrel:$dst, variable_ops), + "call{q}\t$dst", []>, + Requires<[IsWin64]>; + } let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, isCodeGenOnly = 1 in diff --git a/test/CodeGen/X86/win64_alloca_dynalloca.ll b/test/CodeGen/X86/win64_alloca_dynalloca.ll new file mode 100644 index 0000000..bb43608 --- /dev/null +++ b/test/CodeGen/X86/win64_alloca_dynalloca.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -mtriple=x86_64-mingw32 | FileCheck %s -check-prefix=M64 +; RUN: llc < %s -mtriple=x86_64-mingw64 | FileCheck %s -check-prefix=M64 +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=W64 +; PR8777 +; PR8778 + +define i64 @foo(i64 %n, i64 %x) nounwind { +entry: + + %buf0 = alloca i8, i64 4096, align 1 + +; M64: movq %rsp, %rbp +; M64: $4096, %rax +; M64: callq ___chkstk +; M64-NOT: %rsp + +; W64: movq %rsp, %rbp +; W64: $4096, %rax +; W64: callq __chkstk +; W64: subq $4096, %rsp + + %buf1 = alloca i8, i64 %n, align 1 + +; M64: leaq 15(%rcx), %rax +; M64: andq $-16, %rax +; M64: callq ___chkstk +; M64-NOT: %rsp +; M64: movq %rsp, %rax + +; W64: leaq 15(%rcx), %rax +; W64: andq $-16, %rax +; W64: callq __chkstk +; W64: subq %rax, %rsp +; W64: movq %rsp, %rax + + %r = call i64 @bar(i64 %n, i64 %x, i64 %n, i8* %buf0, i8* %buf1) nounwind + +; M64: subq $48, %rsp +; M64: movq %rax, 32(%rsp) +; M64: leaq -4096(%rbp), %r9 +; M64: callq bar + +; W64: subq $48, %rsp +; W64: movq %rax, 32(%rsp) +; W64: leaq -4096(%rbp), %r9 +; W64: callq bar + + ret i64 %r + +; M64: movq %rbp, %rsp + +; W64: movq %rbp, %rsp + +} + +declare i64 @bar(i64, i64, i64, i8* nocapture, i8* nocapture) nounwind diff --git a/test/CodeGen/X86/win_chkstk.ll b/test/CodeGen/X86/win_chkstk.ll index 82ce81d..ae7591d 100644 --- a/test/CodeGen/X86/win_chkstk.ll +++ b/test/CodeGen/X86/win_chkstk.ll @@ -16,7 +16,7 @@ entry: ; WIN_X32: calll __chkstk ; WIN_X64: callq __chkstk ; MINGW_X32: calll __alloca -; MINGW_X64: callq __chkstk +; MINGW_X64: callq ___chkstk ; LINUX-NOT: call __chkstk %array4096 = alloca [4096 x i8], align 16 ; <[4096 x i8]*> [#uses=0] ret i32 0 -- 1.7.1.GIT -------------- next part -------------- From 7d88296c8b870f9685f833a882a68bbf2fdad864 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Wed, 15 Dec 2010 13:07:12 +0900 Subject: [PATCH 6/9] Target/X86: Tweak va_arg for Win64 not to miss taking va_start when number of fixed args > 4. --- lib/Target/X86/X86ISelLowering.cpp | 8 +++++--- test/CodeGen/X86/win64_vararg.ll | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index a012ae2..588c3bb 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1662,8 +1662,8 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, // If the function takes variable number of arguments, make a frame index for // the start of the first vararg value... for expansion of llvm.va_start. if (isVarArg) { - if (!IsWin64 && (Is64Bit || (CallConv != CallingConv::X86_FastCall && - CallConv != CallingConv::X86_ThisCall))) { + if (Is64Bit || (CallConv != CallingConv::X86_FastCall && + CallConv != CallingConv::X86_ThisCall)) { FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); } if (Is64Bit) { @@ -1715,7 +1715,9 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, int HomeOffset = TFI.getOffsetOfLocalArea() + 8; FuncInfo->setRegSaveFrameIndex( MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); - FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); + // FIXME: It is dirty hack but works. + if (NumIntRegs < 4) + FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); } else { // For X86-64, if there are vararg parameters that are passed via // registers, then we must store them to their spots on the stack so they diff --git a/test/CodeGen/X86/win64_vararg.ll b/test/CodeGen/X86/win64_vararg.ll index a451318..efe8bca 100644 --- a/test/CodeGen/X86/win64_vararg.ll +++ b/test/CodeGen/X86/win64_vararg.ll @@ -18,3 +18,36 @@ entry: } declare void @llvm.va_start(i8*) nounwind + +; CHECK: f5: +; CHECK: pushq +; CHECK: leaq 56(%rsp), +define i8* @f5(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, ...) nounwind { +entry: + %ap = alloca i8*, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + ret i8* %ap1 +} + +; CHECK: f4: +; CHECK: pushq +; CHECK: leaq 48(%rsp), +define i8* @f4(i64 %a0, i64 %a1, i64 %a2, i64 %a3, ...) nounwind { +entry: + %ap = alloca i8*, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + ret i8* %ap1 +} + +; CHECK: f3: +; CHECK: pushq +; CHECK: leaq 40(%rsp), +define i8* @f3(i64 %a0, i64 %a1, i64 %a2, ...) nounwind { +entry: + %ap = alloca i8*, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + ret i8* %ap1 +} -- 1.7.1.GIT -------------- next part -------------- From f1b50f241f8346d7888caacd50c9767f5afe6d4a Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Tue, 28 Dec 2010 19:05:25 +0900 Subject: [PATCH 7/9] X86FrameInfo.cpp, X86RegisterInfo.cpp: Re-indent. No functional changes. --- lib/Target/X86/X86FrameLowering.cpp | 35 ++++++++++++++++++++--------------- lib/Target/X86/X86RegisterInfo.cpp | 3 ++- 2 files changed, 22 insertions(+), 16 deletions(-) diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index ce88169..d636105 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -759,6 +759,12 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, } // We're returning from function via eh_return. + bool isRel = (RetOpcode == X86::TCRETURNdi || + RetOpcode == X86::TCRETURNdi64); + bool isMem = (RetOpcode == X86::TCRETURNmi || + RetOpcode == X86::TCRETURNmi64); + bool isReg = (RetOpcode == X86::TCRETURNri || + RetOpcode == X86::TCRETURNri64); if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) { MBBI = prior(MBB.end()); MachineOperand &DestAddr = MBBI->getOperand(0); @@ -766,11 +772,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr).addReg(DestAddr.getReg()); - } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi || - RetOpcode == X86::TCRETURNmi || - RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 || - RetOpcode == X86::TCRETURNmi64) { - bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64; + } else if (isReg || isRel || isMem) { // Tail call return: adjust the stack pointer and jump to callee. MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); @@ -794,10 +796,11 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, } // Jump to label or value in register. - if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) { + if (isRel) { MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi) - ? X86::TAILJMPd : X86::TAILJMPd64)); + BuildMI(MBB, MBBI, DL, + TII.get(RetOpcode == X86::TCRETURNdi ? X86::TAILJMPd + : X86::TAILJMPd64)); if (JumpTarget.isGlobal()) MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), JumpTarget.getTargetFlags()); @@ -806,18 +809,20 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, MIB.addExternalSymbol(JumpTarget.getSymbolName(), JumpTarget.getTargetFlags()); } - } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) { + } else if (isMem) { MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi) - ? X86::TAILJMPm : X86::TAILJMPm64)); + BuildMI(MBB, MBBI, DL, + TII.get(RetOpcode == X86::TCRETURNmi ? X86::TAILJMPm + : X86::TAILJMPm64)); for (unsigned i = 0; i != 5; ++i) MIB.addOperand(MBBI->getOperand(i)); - } else if (RetOpcode == X86::TCRETURNri64) { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)). + } else if (isReg) { + BuildMI(MBB, MBBI, DL, + TII.get(RetOpcode == X86::TCRETURNri64 ? X86::TAILJMPr64 + : X86::TAILJMPr)). addReg(JumpTarget.getReg(), RegState::Kill); } else { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)). - addReg(JumpTarget.getReg(), RegState::Kill); + llvm_unreachable("What could I select for TCRETURN?"); } MachineInstr *NewMI = prior(MBBI); diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 06c671b..9260f1d 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -576,7 +576,8 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned BasePtr; unsigned Opc = MI.getOpcode(); - bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm; + bool AfterFPPop = (Opc == X86::TAILJMPm64 || + Opc == X86::TAILJMPm); if (needsStackRealignment(MF)) BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); else if (AfterFPPop) -- 1.7.1.GIT -------------- next part -------------- From 27857943a0cbd919b1f60ac8eb562b6a01bb8ef9 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Thu, 6 Jan 2011 09:09:52 +0900 Subject: [PATCH 8/9] TableGen/EDEmitter.cpp: Add TCW64. --- utils/TableGen/EDEmitter.cpp | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp index 7ee1019..b3e442d 100644 --- a/utils/TableGen/EDEmitter.cpp +++ b/utils/TableGen/EDEmitter.cpp @@ -264,6 +264,7 @@ static int X86TypeFromOpName(LiteralConstantEmitter *type, REG("RFP32"); REG("GR64"); REG("GR64_TC"); + REG("GR64_TCW64"); REG("FR64"); REG("VR64"); REG("RFP64"); @@ -297,6 +298,7 @@ static int X86TypeFromOpName(LiteralConstantEmitter *type, MEM("opaque48mem"); MEM("i64mem"); MEM("i64mem_TC"); + MEM("i64mem_TCW64"); MEM("f64mem"); MEM("sdmem"); MEM("f80mem"); -- 1.7.1.GIT -------------- next part -------------- From ff6e72615a2a6bf8549c76550b618d6aafdaeefd Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Thu, 6 Jan 2011 06:59:35 +0900 Subject: [PATCH 9/9] Target/X86: Tweak win64's tailcall. --- lib/Target/X86/X86FrameLowering.cpp | 12 ++++++++++++ lib/Target/X86/X86InstrCompiler.td | 24 ++++++++++++++++++++---- lib/Target/X86/X86InstrControl.td | 33 +++++++++++++++++++++++++++++++++ lib/Target/X86/X86InstrInfo.cpp | 2 ++ lib/Target/X86/X86InstrInfo.td | 6 ++++++ lib/Target/X86/X86MCInstLower.cpp | 4 ++++ lib/Target/X86/X86RegisterInfo.cpp | 1 + lib/Target/X86/X86RegisterInfo.td | 3 +++ test/CodeGen/X86/tailcallstack64.ll | 16 ++++++++++------ 9 files changed, 91 insertions(+), 10 deletions(-) diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index d636105..712eded 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -108,6 +108,9 @@ static unsigned findDeadCallerSavedReg(MachineBasicBlock &MBB, case X86::TCRETURNdi64: case X86::TCRETURNri64: case X86::TCRETURNmi64: + case X86::TCRETURNdiW64: + case X86::TCRETURNriW64: + case X86::TCRETURNmiW64: case X86::EH_RETURN: case X86::EH_RETURN64: { SmallSet Uses; @@ -670,6 +673,9 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, case X86::TCRETURNdi64: case X86::TCRETURNri64: case X86::TCRETURNmi64: + case X86::TCRETURNdiW64: + case X86::TCRETURNriW64: + case X86::TCRETURNmiW64: case X86::EH_RETURN: case X86::EH_RETURN64: break; // These are ok @@ -760,10 +766,13 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, // We're returning from function via eh_return. bool isRel = (RetOpcode == X86::TCRETURNdi || + RetOpcode == X86::TCRETURNdiW64 || RetOpcode == X86::TCRETURNdi64); bool isMem = (RetOpcode == X86::TCRETURNmi || + RetOpcode == X86::TCRETURNmiW64 || RetOpcode == X86::TCRETURNmi64); bool isReg = (RetOpcode == X86::TCRETURNri || + RetOpcode == X86::TCRETURNriW64 || RetOpcode == X86::TCRETURNri64); if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) { MBBI = prior(MBB.end()); @@ -800,6 +809,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII.get(RetOpcode == X86::TCRETURNdi ? X86::TAILJMPd + : RetOpcode == X86::TCRETURNdiW64 ? X86::TAILJMPdW64 : X86::TAILJMPd64)); if (JumpTarget.isGlobal()) MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), @@ -813,12 +823,14 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII.get(RetOpcode == X86::TCRETURNmi ? X86::TAILJMPm + : RetOpcode == X86::TCRETURNmiW64 ? X86::TAILJMPmW64 : X86::TAILJMPm64)); for (unsigned i = 0; i != 5; ++i) MIB.addOperand(MBBI->getOperand(i)); } else if (isReg) { BuildMI(MBB, MBBI, DL, TII.get(RetOpcode == X86::TCRETURNri64 ? X86::TAILJMPr64 + : RetOpcode == X86::TCRETURNriW64 ? X86::TAILJMPrW64 : X86::TAILJMPr)). addReg(JumpTarget.getReg(), RegState::Kill); } else { diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td index d2c5763..5d55fa6 100644 --- a/lib/Target/X86/X86InstrCompiler.td +++ b/lib/Target/X86/X86InstrCompiler.td @@ -868,19 +868,35 @@ def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), def : Pat<(X86tcret GR64_TC:$dst, imm:$off), (TCRETURNri64 GR64_TC:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode, NotWin64]>; def : Pat<(X86tcret (load addr:$dst), imm:$off), (TCRETURNmi64 addr:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode, NotWin64]>; def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode, NotWin64]>; def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), (TCRETURNdi64 texternalsym:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode, NotWin64]>; + +def : Pat<(X86tcret GR64_TCW64:$dst, imm:$off), + (TCRETURNriW64 GR64_TCW64:$dst, imm:$off)>, + Requires<[IsWin64]>; + +def : Pat<(X86tcret (load addr:$dst), imm:$off), + (TCRETURNmiW64 addr:$dst, imm:$off)>, + Requires<[IsWin64]>; + +def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), + (TCRETURNdiW64 tglobaladdr:$dst, imm:$off)>, + Requires<[IsWin64]>; + +def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), + (TCRETURNdiW64 texternalsym:$dst, imm:$off)>, + Requires<[IsWin64]>; // Normal calls, with various flavors of addresses. def : Pat<(X86call (i32 tglobaladdr:$dst)), diff --git a/lib/Target/X86/X86InstrControl.td b/lib/Target/X86/X86InstrControl.td index 31f2832..c4939a8 100644 --- a/lib/Target/X86/X86InstrControl.td +++ b/lib/Target/X86/X86InstrControl.td @@ -301,3 +301,36 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops), "jmp{q}\t{*}$dst # TAILCALL", []>; } + +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, + isCodeGenOnly = 1 in + let Defs = [RAX, RCX, RDX, R8, R9, R10, R11, + FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1, + MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, + XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS], + Uses = [RSP] in { + def TCRETURNdiW64 : PseudoI<(outs), + (ins i64i32imm_pcrel:$dst, i32imm:$offset, variable_ops), + []>, + Requires<[IsWin64]>; + def TCRETURNriW64 : PseudoI<(outs), + (ins GR64_TCW64:$dst, i32imm:$offset, variable_ops), []>, + Requires<[IsWin64]>; + let mayLoad = 1 in + def TCRETURNmiW64 : PseudoI<(outs), + (ins i64mem_TCW64:$dst, i32imm:$offset, variable_ops), []>, + Requires<[IsWin64]>; + + def TAILJMPdW64 : Ii32PCRel<0xE9, RawFrm, (outs), + (ins i64i32imm_pcrel:$dst, variable_ops), + "jmp\t$dst # TAILCALL", []>, + Requires<[IsWin64]>; + def TAILJMPrW64 : I<0xFF, MRM4r, (outs), (ins GR64_TCW64:$dst, variable_ops), + "jmp{q}\t{*}$dst # TAILCALL", []>, + Requires<[IsWin64]>; + + let mayLoad = 1 in + def TAILJMPmW64 : I<0xFF, MRM4m, (outs), (ins i64mem_TCW64:$dst, variable_ops), + "jmp{q}\t{*}$dst # TAILCALL", []>, + Requires<[IsWin64]>; +} diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 63dcd14..c3c3b8c 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -321,6 +321,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) { X86::SETSr, X86::SETSm, 0, 0 }, { X86::TAILJMPr, X86::TAILJMPm, 1, 0 }, { X86::TAILJMPr64, X86::TAILJMPm64, 1, 0 }, + { X86::TAILJMPrW64, X86::TAILJMPmW64, 1, 0 }, { X86::TEST16ri, X86::TEST16mi, 1, 0 }, { X86::TEST32ri, X86::TEST32mi, 1, 0 }, { X86::TEST64ri32, X86::TEST64mi32, 1, 0 }, @@ -2025,6 +2026,7 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg, case X86::GR64_NOREX_NOSPRegClassID: case X86::GR64_NOSPRegClassID: case X86::GR64_TCRegClassID: + case X86::GR64_TCW64RegClassID: return load ? X86::MOV64rm : X86::MOV64mr; case X86::GR32RegClassID: case X86::GR32_ABCDRegClassID: diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 4748f13..78847a8 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -291,6 +291,12 @@ def i64mem_TC : Operand { let ParserMatchClass = X86MemAsmOperand; } +def i64mem_TCW64 : Operand { + let PrintMethod = "printi64mem"; + let MIOperandInfo = (ops GR64_TCW64, i8imm, GR64_TCW64, i32imm, i8imm); + let ParserMatchClass = X86MemAsmOperand; +} + let ParserMatchClass = X86AbsMemAsmOperand, PrintMethod = "print_pcrel_imm" in { def i32imm_pcrel : Operand; diff --git a/lib/Target/X86/X86MCInstLower.cpp b/lib/Target/X86/X86MCInstLower.cpp index 4159af1..0b9679e 100644 --- a/lib/Target/X86/X86MCInstLower.cpp +++ b/lib/Target/X86/X86MCInstLower.cpp @@ -399,6 +399,7 @@ ReSimplify: // register inputs modeled as normal uses instead of implicit uses. As such, // truncate off all but the first operand (the callee). FIXME: Change isel. case X86::TAILJMPr64: + case X86::TAILJMPrW64: case X86::CALL64r: case X86::CALL64pcrel32: case X86::WINCALL64r: @@ -421,12 +422,14 @@ ReSimplify: // TAILJMPd, TAILJMPd64 - Lower to the correct jump instructions. case X86::TAILJMPr: case X86::TAILJMPd: + case X86::TAILJMPdW64: case X86::TAILJMPd64: { unsigned Opcode; switch (OutMI.getOpcode()) { default: assert(0 && "Invalid opcode"); case X86::TAILJMPr: Opcode = X86::JMP32r; break; case X86::TAILJMPd: + case X86::TAILJMPdW64: case X86::TAILJMPd64: Opcode = X86::JMP_1; break; } @@ -618,6 +621,7 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { case X86::TAILJMPr: case X86::TAILJMPd: case X86::TAILJMPd64: + case X86::TAILJMPdW64: // Lower these as normal, but add some comments. OutStreamer.AddComment("TAILCALL"); break; diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 9260f1d..e1eaa4b 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -577,6 +577,7 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned Opc = MI.getOpcode(); bool AfterFPPop = (Opc == X86::TAILJMPm64 || + Opc == X86::TAILJMPmW64 || Opc == X86::TAILJMPm); if (needsStackRealignment(MF)) BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index 45bb989..dd35d62 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -496,6 +496,9 @@ def GR64_TC : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI, (GR32_TC sub_32bit)]; } +def GR64_TCW64 : RegisterClass<"X86", [i64], 64, [RAX, R11, R10, + R9, R8, RDX, RCX]>; + // GR8_NOREX - GR8 registers which do not require a REX prefix. def GR8_NOREX : RegisterClass<"X86", [i8], 8, [AL, CL, DL, AH, CH, DH, BL, BH]> { diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll index 52b074d..0c732d5 100644 --- a/test/CodeGen/X86/tailcallstack64.ll +++ b/test/CodeGen/X86/tailcallstack64.ll @@ -1,16 +1,20 @@ -; RUN: llc < %s -tailcallopt -march=x86-64 -post-RA-scheduler=true | FileCheck %s +; RUN: llc < %s -tailcallopt -mtriple=x86_64-linux -post-RA-scheduler=true | FileCheck %s +; RUN: llc < %s -tailcallopt -mtriple=x86_64-win32 -post-RA-scheduler=true | FileCheck %s + +; FIXME: Redundant unused stack allocation could be eliminated. +; CHECK: subq ${{24|88}}, %rsp ; Check that lowered arguments on the stack do not overwrite each other. ; Add %in1 %p1 to a different temporary register (%eax). -; CHECK: movl 32(%rsp), %eax +; CHECK: movl [[A1:32|144]](%rsp), %eax ; Move param %in1 to temp register (%r10d). -; CHECK: movl 40(%rsp), %r10d +; CHECK: movl [[A2:40|152]](%rsp), %r10d ; Add %in1 %p1 to a different temporary register (%eax). -; CHECK: addl %edi, %eax +; CHECK: addl {{%edi|%ecx}}, %eax ; Move param %in2 to stack. -; CHECK: movl %r10d, 32(%rsp) +; CHECK: movl %r10d, [[A1]](%rsp) ; Move result of addition to stack. -; CHECK: movl %eax, 40(%rsp) +; CHECK: movl %eax, [[A2]](%rsp) ; Eventually, do a TAILCALL ; CHECK: TAILCALL -- 1.7.1.GIT From sabre at nondot.org Tue Jan 11 01:47:59 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Jan 2011 07:47:59 -0000 Subject: [llvm-commits] [llvm] r123219 - in /llvm/trunk: lib/Transforms/Scalar/LoopRotation.cpp test/Transforms/LoopRotate/crash.ll Message-ID: <20110111074759.BBD6C2A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 01:47:59 2011 New Revision: 123219 URL: http://llvm.org/viewvc/llvm-project?rev=123219&view=rev Log: remove a bogus assertion: the latch block of a loop is not neccesarily an uncond branch to the header. This fixes PR8955 (the assertion tripping). Added: llvm/trunk/test/Transforms/LoopRotate/crash.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp?rev=123219&r1=123218&r2=123219&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Tue Jan 11 01:47:59 2011 @@ -335,12 +335,11 @@ assert(L->getLoopPreheader() && "Invalid loop preheader after loop rotation"); assert(L->getLoopLatch() && "Invalid loop latch after loop rotation"); - // Now that the CFG and DomTree are in a consistent state again, merge the - // OrigHeader block into OrigLatch. We know that they are joined by an - // unconditional branch. This is just a cleanup so the emitted code isn't - // too gross. - bool DidIt = MergeBlockIntoPredecessor(OrigHeader, this); - assert(DidIt && "Block merge failed??"); (void)DidIt; + // Now that the CFG and DomTree are in a consistent state again, try to merge + // the OrigHeader block into OrigLatch. This will succeed if they are + // connected by an unconditional branch. This is just a cleanup so the + // emitted code isn't too gross in this common case. + MergeBlockIntoPredecessor(OrigHeader, this); ++NumRotated; return true; Added: llvm/trunk/test/Transforms/LoopRotate/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopRotate/crash.ll?rev=123219&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopRotate/crash.ll (added) +++ llvm/trunk/test/Transforms/LoopRotate/crash.ll Tue Jan 11 01:47:59 2011 @@ -0,0 +1,31 @@ +; RUN: opt -loop-rotate %s -disable-output + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-darwin10.0.0" + +; PR8955 - Rotating an outer loop that has a condbr for a latch block. +define void @test1() nounwind ssp { +entry: + br label %lbl_283 + +lbl_283: ; preds = %if.end, %entry + br i1 undef, label %if.else, label %if.then + +if.then: ; preds = %lbl_283 + br i1 undef, label %if.end, label %for.condthread-pre-split + +for.condthread-pre-split: ; preds = %if.then + br label %for.cond + +for.cond: ; preds = %for.cond, %for.condthread-pre-split + br i1 undef, label %lbl_281, label %for.cond + +lbl_281: ; preds = %if.end, %for.cond + br label %if.end + +if.end: ; preds = %lbl_281, %if.then + br i1 undef, label %lbl_283, label %lbl_281 + +if.else: ; preds = %lbl_283 + ret void +} From sabre at nondot.org Tue Jan 11 01:50:07 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Jan 2011 07:50:07 -0000 Subject: [llvm-commits] [llvm] r123220 - in /llvm/trunk/test/Transforms/LoopRotate: LRCrash-1.ll LRCrash-2.ll LRCrash-3.ll LRCrash-4.ll LRCrash-5.ll crash.ll Message-ID: <20110111075007.453A72A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 01:50:07 2011 New Revision: 123220 URL: http://llvm.org/viewvc/llvm-project?rev=123220&view=rev Log: merge tests into one crash.ll test. Removed: llvm/trunk/test/Transforms/LoopRotate/LRCrash-1.ll llvm/trunk/test/Transforms/LoopRotate/LRCrash-2.ll llvm/trunk/test/Transforms/LoopRotate/LRCrash-3.ll llvm/trunk/test/Transforms/LoopRotate/LRCrash-4.ll llvm/trunk/test/Transforms/LoopRotate/LRCrash-5.ll Modified: llvm/trunk/test/Transforms/LoopRotate/crash.ll Removed: llvm/trunk/test/Transforms/LoopRotate/LRCrash-1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopRotate/LRCrash-1.ll?rev=123219&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopRotate/LRCrash-1.ll (original) +++ llvm/trunk/test/Transforms/LoopRotate/LRCrash-1.ll (removed) @@ -1,18 +0,0 @@ -; RUN: opt < %s -loop-rotate -verify-dom-info -verify-loop-info -disable-output - - %struct.relation = type { [4 x i16], i32, [4 x i16], i32, i32 } - -define void @findAllPairs() { -entry: - br i1 false, label %bb139, label %bb10.i44 -bb10.i44: ; preds = %entry - ret void -bb127: ; preds = %bb139 - br label %bb139 -bb139: ; preds = %bb127, %entry - br i1 false, label %bb127, label %bb142 -bb142: ; preds = %bb139 - %r91.0.lcssa = phi %struct.relation* [ null, %bb139 ] ; <%struct.relation*> [#uses=0] - ret void -} - Removed: llvm/trunk/test/Transforms/LoopRotate/LRCrash-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopRotate/LRCrash-2.ll?rev=123219&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopRotate/LRCrash-2.ll (original) +++ llvm/trunk/test/Transforms/LoopRotate/LRCrash-2.ll (removed) @@ -1,24 +0,0 @@ -; RUN: opt < %s -loop-rotate -verify-dom-info -verify-loop-info -disable-output - -define void @findAllPairs() { -entry: - br i1 false, label %bb139, label %cond_true -cond_true: ; preds = %entry - ret void -bb90: ; preds = %bb139 - br i1 false, label %bb136, label %cond_next121 -cond_next121: ; preds = %bb90 - br i1 false, label %bb136, label %bb127 -bb127: ; preds = %cond_next121 - br label %bb136 -bb136: ; preds = %bb127, %cond_next121, %bb90 - %changes.1 = phi i32 [ %changes.2, %bb90 ], [ %changes.2, %cond_next121 ], [ 1, %bb127 ] ; [#uses=1] - br label %bb139 -bb139: ; preds = %bb136, %entry - %changes.2 = phi i32 [ %changes.1, %bb136 ], [ 0, %entry ] ; [#uses=3] - br i1 false, label %bb90, label %bb142 -bb142: ; preds = %bb139 - %changes.2.lcssa = phi i32 [ %changes.2, %bb139 ] ; [#uses=0] - ret void -} - Removed: llvm/trunk/test/Transforms/LoopRotate/LRCrash-3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopRotate/LRCrash-3.ll?rev=123219&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopRotate/LRCrash-3.ll (original) +++ llvm/trunk/test/Transforms/LoopRotate/LRCrash-3.ll (removed) @@ -1,29 +0,0 @@ -; RUN: opt < %s -loop-rotate -verify-dom-info -verify-loop-info -disable-output - -define void @_ZN9Classfile4readEv() { -entry: - br i1 false, label %cond_false485, label %bb405 -bb405: ; preds = %entry - ret void -cond_false485: ; preds = %entry - br label %bb830 -bb511: ; preds = %bb830 - br i1 false, label %bb816, label %bb830 -cond_next667: ; preds = %bb816 - br i1 false, label %cond_next695, label %bb680 -bb676: ; preds = %bb680 - br label %bb680 -bb680: ; preds = %bb676, %cond_next667 - %iftmp.68.0 = zext i1 false to i8 ; [#uses=1] - br i1 false, label %bb676, label %cond_next695 -cond_next695: ; preds = %bb680, %cond_next667 - %iftmp.68.2 = phi i8 [ %iftmp.68.0, %bb680 ], [ undef, %cond_next667 ] ; [#uses=0] - ret void -bb816: ; preds = %bb816, %bb511 - br i1 false, label %cond_next667, label %bb816 -bb830: ; preds = %bb511, %cond_false485 - br i1 false, label %bb511, label %bb835 -bb835: ; preds = %bb830 - ret void -} - Removed: llvm/trunk/test/Transforms/LoopRotate/LRCrash-4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopRotate/LRCrash-4.ll?rev=123219&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopRotate/LRCrash-4.ll (original) +++ llvm/trunk/test/Transforms/LoopRotate/LRCrash-4.ll (removed) @@ -1,18 +0,0 @@ -; RUN: opt < %s -loop-rotate -verify-dom-info -verify-loop-info -disable-output - -define void @InterpretSEIMessage(i8* %msg) { -entry: - br label %bb15 -bb6: ; preds = %bb15 - %gep.upgrd.1 = zext i32 %offset.1 to i64 ; [#uses=1] - %tmp11 = getelementptr i8* %msg, i64 %gep.upgrd.1 ; [#uses=0] - br label %bb15 -bb15: ; preds = %bb6, %entry - %offset.1 = add i32 0, 1 ; [#uses=2] - br i1 false, label %bb6, label %bb17 -bb17: ; preds = %bb15 - %offset.1.lcssa = phi i32 [ %offset.1, %bb15 ] ; [#uses=0] - %payload_type.1.lcssa = phi i32 [ 0, %bb15 ] ; [#uses=0] - ret void -} - Removed: llvm/trunk/test/Transforms/LoopRotate/LRCrash-5.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopRotate/LRCrash-5.ll?rev=123219&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopRotate/LRCrash-5.ll (original) +++ llvm/trunk/test/Transforms/LoopRotate/LRCrash-5.ll (removed) @@ -1,26 +0,0 @@ -; RUN: opt < %s -loop-rotate -verify-dom-info -verify-loop-info -disable-output -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" -target triple = "x86_64-apple-darwin9" - %struct.NSArray = type { %struct.NSObject } - %struct.NSObject = type { %struct.objc_class* } - %struct.NSRange = type { i64, i64 } - %struct._message_ref_t = type { %struct.NSObject* (%struct.NSObject*, %struct._message_ref_t*, ...)*, %struct.objc_selector* } - %struct.objc_class = type opaque - %struct.objc_selector = type opaque -@"\01L_OBJC_MESSAGE_REF_26" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=1] - -define %struct.NSArray* @"-[NSString(DocSetPrivateAddition) _dsa_stringAsPathComponent]"(%struct.NSArray* %self, %struct._message_ref_t* %_cmd) { -entry: - br label %bb116 - -bb116: ; preds = %bb131, %entry - %tmp123 = call %struct.NSRange null( %struct.NSObject* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_26", %struct.NSArray* null ) ; <%struct.NSRange> [#uses=1] - br i1 false, label %bb141, label %bb131 - -bb131: ; preds = %bb116 - %mrv_gr125 = getresult %struct.NSRange %tmp123, 1 ; [#uses=0] - br label %bb116 - -bb141: ; preds = %bb116 - ret %struct.NSArray* null -} Modified: llvm/trunk/test/Transforms/LoopRotate/crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopRotate/crash.ll?rev=123220&r1=123219&r2=123220&view=diff ============================================================================== --- llvm/trunk/test/Transforms/LoopRotate/crash.ll (original) +++ llvm/trunk/test/Transforms/LoopRotate/crash.ll Tue Jan 11 01:50:07 2011 @@ -1,4 +1,4 @@ -; RUN: opt -loop-rotate %s -disable-output +; RUN: opt -loop-rotate %s -disable-output -verify-dom-info -verify-loop-info target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" target triple = "x86_64-apple-darwin10.0.0" @@ -29,3 +29,111 @@ if.else: ; preds = %lbl_283 ret void } + + %struct.relation = type { [4 x i16], i32, [4 x i16], i32, i32 } + +define void @test2() { +entry: + br i1 false, label %bb139, label %bb10.i44 +bb10.i44: ; preds = %entry + ret void +bb127: ; preds = %bb139 + br label %bb139 +bb139: ; preds = %bb127, %entry + br i1 false, label %bb127, label %bb142 +bb142: ; preds = %bb139 + %r91.0.lcssa = phi %struct.relation* [ null, %bb139 ] ; <%struct.relation*> [#uses=0] + ret void +} + + +define void @test3() { +entry: + br i1 false, label %bb139, label %cond_true +cond_true: ; preds = %entry + ret void +bb90: ; preds = %bb139 + br i1 false, label %bb136, label %cond_next121 +cond_next121: ; preds = %bb90 + br i1 false, label %bb136, label %bb127 +bb127: ; preds = %cond_next121 + br label %bb136 +bb136: ; preds = %bb127, %cond_next121, %bb90 + %changes.1 = phi i32 [ %changes.2, %bb90 ], [ %changes.2, %cond_next121 ], [ 1, %bb127 ] ; [#uses=1] + br label %bb139 +bb139: ; preds = %bb136, %entry + %changes.2 = phi i32 [ %changes.1, %bb136 ], [ 0, %entry ] ; [#uses=3] + br i1 false, label %bb90, label %bb142 +bb142: ; preds = %bb139 + %changes.2.lcssa = phi i32 [ %changes.2, %bb139 ] ; [#uses=0] + ret void +} + +define void @test4() { +entry: + br i1 false, label %cond_false485, label %bb405 +bb405: ; preds = %entry + ret void +cond_false485: ; preds = %entry + br label %bb830 +bb511: ; preds = %bb830 + br i1 false, label %bb816, label %bb830 +cond_next667: ; preds = %bb816 + br i1 false, label %cond_next695, label %bb680 +bb676: ; preds = %bb680 + br label %bb680 +bb680: ; preds = %bb676, %cond_next667 + %iftmp.68.0 = zext i1 false to i8 ; [#uses=1] + br i1 false, label %bb676, label %cond_next695 +cond_next695: ; preds = %bb680, %cond_next667 + %iftmp.68.2 = phi i8 [ %iftmp.68.0, %bb680 ], [ undef, %cond_next667 ] ; [#uses=0] + ret void +bb816: ; preds = %bb816, %bb511 + br i1 false, label %cond_next667, label %bb816 +bb830: ; preds = %bb511, %cond_false485 + br i1 false, label %bb511, label %bb835 +bb835: ; preds = %bb830 + ret void +} + + %struct.NSArray = type { %struct.NSObject } + %struct.NSObject = type { %struct.objc_class* } + %struct.NSRange = type { i64, i64 } + %struct._message_ref_t = type { %struct.NSObject* (%struct.NSObject*, %struct._message_ref_t*, ...)*, %struct.objc_selector* } + %struct.objc_class = type opaque + %struct.objc_selector = type opaque +@"\01L_OBJC_MESSAGE_REF_26" = external global %struct._message_ref_t ; <%struct._message_ref_t*> [#uses=1] + +define %struct.NSArray* @test5(%struct.NSArray* %self, %struct._message_ref_t* %_cmd) { +entry: + br label %bb116 + +bb116: ; preds = %bb131, %entry + %tmp123 = call %struct.NSRange null( %struct.NSObject* null, %struct._message_ref_t* @"\01L_OBJC_MESSAGE_REF_26", %struct.NSArray* null ) ; <%struct.NSRange> [#uses=1] + br i1 false, label %bb141, label %bb131 + +bb131: ; preds = %bb116 + %mrv_gr125 = getresult %struct.NSRange %tmp123, 1 ; [#uses=0] + br label %bb116 + +bb141: ; preds = %bb116 + ret %struct.NSArray* null +} + +define void @test6(i8* %msg) { +entry: + br label %bb15 +bb6: ; preds = %bb15 + %gep.upgrd.1 = zext i32 %offset.1 to i64 ; [#uses=1] + %tmp11 = getelementptr i8* %msg, i64 %gep.upgrd.1 ; [#uses=0] + br label %bb15 +bb15: ; preds = %bb6, %entry + %offset.1 = add i32 0, 1 ; [#uses=2] + br i1 false, label %bb6, label %bb17 +bb17: ; preds = %bb15 + %offset.1.lcssa = phi i32 [ %offset.1, %bb15 ] ; [#uses=0] + %payload_type.1.lcssa = phi i32 [ 0, %bb15 ] ; [#uses=0] + ret void +} + + From sabre at nondot.org Tue Jan 11 02:00:40 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Jan 2011 08:00:40 -0000 Subject: [llvm-commits] [llvm] r123221 - in /llvm/trunk/lib/Transforms: Scalar/LoopUnrollPass.cpp Utils/LoopUnroll.cpp Message-ID: <20110111080040.C25BE2A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 02:00:40 2011 New Revision: 123221 URL: http://llvm.org/viewvc/llvm-project?rev=123221&view=rev Log: random cleanups Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp?rev=123221&r1=123220&r2=123221&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnrollPass.cpp Tue Jan 11 02:00:40 2011 @@ -123,7 +123,6 @@ } bool LoopUnroll::runOnLoop(Loop *L, LPPassManager &LPM) { - LoopInfo *LI = &getAnalysis(); BasicBlock *Header = L->getHeader(); Modified: llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp?rev=123221&r1=123220&r2=123221&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp Tue Jan 11 02:00:40 2011 @@ -16,6 +16,7 @@ // // The process of unrolling can produce extraneous basic blocks linked with // unconditional branches. This will be corrected in the future. +// //===----------------------------------------------------------------------===// #define DEBUG_TYPE "loop-unroll" @@ -30,12 +31,11 @@ #include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/Cloning.h" #include "llvm/Transforms/Utils/Local.h" - using namespace llvm; // TODO: Should these be here or in LoopUnroll? STATISTIC(NumCompletelyUnrolled, "Number of loops completely unrolled"); -STATISTIC(NumUnrolled, "Number of loops unrolled (completely or otherwise)"); +STATISTIC(NumUnrolled, "Number of loops unrolled (completely or otherwise)"); /// RemapInstruction - Convert the instruction operands from referencing the /// current values into those specified by VMap. From stoklund at 2pi.dk Tue Jan 11 02:14:21 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 11 Jan 2011 00:14:21 -0800 Subject: [llvm-commits] [Review request] Tweaking Win64 Codegen In-Reply-To: References: Message-ID: <6C9AA982-EFB8-4020-AEA2-273C6C1C721C@2pi.dk> On Jan 10, 2011, at 11:44 PM, NAKAMURA Takumi wrote: > * 0009-Target-X86-Tweak-win64-s-tailcall.patch.txt > > [PR8743] Introduce tailcall-w64 stuff. Hi Takumi, I don't think adding more TCRETURN instructions is the right solution. Instead, you should add a new kind of dynamic pointer register class to X86RegisterInfo::getPointerRegClass() and use that for the TCRETURN operand: def ptr_rc_tailcall : PointerLikeRegClass<2>; /jakob -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110111/e28dfade/attachment.bin From sabre at nondot.org Tue Jan 11 02:13:40 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Jan 2011 08:13:40 -0000 Subject: [llvm-commits] [llvm] r123222 - in /llvm/trunk: include/llvm/Transforms/Utils/BasicBlockUtils.h lib/Transforms/Scalar/GVN.cpp lib/Transforms/Utils/BasicBlockUtils.cpp Message-ID: <20110111081340.788DC2A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 02:13:40 2011 New Revision: 123222 URL: http://llvm.org/viewvc/llvm-project?rev=123222&view=rev Log: Fix FoldSingleEntryPHINodes to update memdep and AA when it deletes phi nodes. It is called from MergeBlockIntoPredecessor which is called from GVN, which claims to preserve these. I'm skeptical that this is the actual problem behind PR8954, but this is a stab in the right direction. Modified: llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h llvm/trunk/lib/Transforms/Scalar/GVN.cpp llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Modified: llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h?rev=123222&r1=123221&r2=123222&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h (original) +++ llvm/trunk/include/llvm/Transforms/Utils/BasicBlockUtils.h Tue Jan 11 02:13:40 2011 @@ -35,7 +35,7 @@ /// any single-entry PHI nodes in it, fold them away. This handles the case /// when all entries to the PHI nodes in a block are guaranteed equal, such as /// when the block has exactly one predecessor. -void FoldSingleEntryPHINodes(BasicBlock *BB); +void FoldSingleEntryPHINodes(BasicBlock *BB, Pass *P = 0); /// DeleteDeadPHIs - Examine each PHI in the given block and delete it if it /// is dead. Also recursively delete any operands that become dead as @@ -46,7 +46,7 @@ /// MergeBlockIntoPredecessor - Attempts to merge a block into its predecessor, /// if possible. The return value indicates success or failure. -bool MergeBlockIntoPredecessor(BasicBlock* BB, Pass* P = 0); +bool MergeBlockIntoPredecessor(BasicBlock *BB, Pass *P = 0); // ReplaceInstWithValue - Replace all uses of an instruction (specified by BI) // with a value, then remove and delete the original instruction. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=123222&r1=123221&r2=123222&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue Jan 11 02:13:40 2011 @@ -1741,8 +1741,8 @@ // Merge unconditional branches, allowing PRE to catch more // optimization opportunities. for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ) { - BasicBlock *BB = FI; - ++FI; + BasicBlock *BB = FI++; + bool removedBlock = MergeBlockIntoPredecessor(BB, this); if (removedBlock) ++NumGVNBlocks; Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=123222&r1=123221&r2=123222&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Tue Jan 11 02:13:40 2011 @@ -19,8 +19,9 @@ #include "llvm/Constant.h" #include "llvm/Type.h" #include "llvm/Analysis/AliasAnalysis.h" -#include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/DominanceFrontier.h" +#include "llvm/Analysis/LoopInfo.h" +#include "llvm/Analysis/MemoryDependenceAnalysis.h" #include "llvm/Target/TargetData.h" #include "llvm/Transforms/Utils/Local.h" #include "llvm/Transforms/Scalar.h" @@ -63,12 +64,27 @@ /// any single-entry PHI nodes in it, fold them away. This handles the case /// when all entries to the PHI nodes in a block are guaranteed equal, such as /// when the block has exactly one predecessor. -void llvm::FoldSingleEntryPHINodes(BasicBlock *BB) { +void llvm::FoldSingleEntryPHINodes(BasicBlock *BB, Pass *P) { + if (!isa(BB->begin())) return; + + AliasAnalysis *AA = 0; + MemoryDependenceAnalysis *MemDep = 0; + if (P) { + AA = P->getAnalysisIfAvailable(); + MemDep = P->getAnalysisIfAvailable(); + } + while (PHINode *PN = dyn_cast(BB->begin())) { if (PN->getIncomingValue(0) != PN) PN->replaceAllUsesWith(PN->getIncomingValue(0)); else PN->replaceAllUsesWith(UndefValue::get(PN->getType())); + + if (MemDep) + MemDep->removeInstruction(PN); // Memdep updates AA itself. + else if (AA && isa(PN->getType())) + AA->deleteValue(PN); + PN->eraseFromParent(); } } @@ -132,7 +148,7 @@ // Begin by getting rid of unneeded PHIs. if (isa(BB->front())) - FoldSingleEntryPHINodes(BB); + FoldSingleEntryPHINodes(BB, P); // Delete the unconditional branch from the predecessor... PredBB->getInstList().pop_back(); From sabre at nondot.org Tue Jan 11 02:16:49 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Jan 2011 08:16:49 -0000 Subject: [llvm-commits] [llvm] r123223 - /llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Message-ID: <20110111081649.CA2762A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 02:16:49 2011 New Revision: 123223 URL: http://llvm.org/viewvc/llvm-project?rev=123223&view=rev Log: when MergeBlockIntoPredecessor merges two blocks, update MemDep if it is floating around in the ether. Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=123223&r1=123222&r2=123223&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Tue Jan 11 02:16:49 2011 @@ -179,6 +179,10 @@ if (LoopInfo *LI = P->getAnalysisIfAvailable()) LI->removeBlock(BB); + + if (MemoryDependenceAnalysis *MD = + P->getAnalysisIfAvailable()) + MD->invalidateCachedPredecessors(); } } From sabre at nondot.org Tue Jan 11 02:19:16 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Jan 2011 08:19:16 -0000 Subject: [llvm-commits] [llvm] r123224 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp Message-ID: <20110111081916.DE2F02A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 02:19:16 2011 New Revision: 123224 URL: http://llvm.org/viewvc/llvm-project?rev=123224&view=rev Log: update memdep when an instruction is deleted. This code isn't actually reached in the testcase in PR8954, but it's safe and good practice. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=123224&r1=123223&r2=123224&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue Jan 11 02:19:16 2011 @@ -1383,8 +1383,11 @@ } if (!CanDoPRE) { - while (!NewInsts.empty()) - NewInsts.pop_back_val()->eraseFromParent(); + while (!NewInsts.empty()) { + Instruction *I = NewInsts.pop_back_val(); + if (MD) MD->removeInstruction(I); + I->eraseFromParent(); + } return false; } From fvbommel at gmail.com Tue Jan 11 02:36:01 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Tue, 11 Jan 2011 09:36:01 +0100 Subject: [llvm-commits] PATCH: instcombine switch on select of constants to br In-Reply-To: References: <893CFB3C-832C-4959-AE72-4186FCD61E99@gmail.com> <4D2A730F.2090207@mxc.ca> <130DB463-EF73-40A2-8166-5D3A014D9D12@gmail.com> Message-ID: On Tue, Jan 11, 2011 at 12:44 AM, Alistair Lynn wrote: >> You're not updating PHI nodes in successors. You should call >> Succ->removePredecessor(BB) for each successor that is removed. > > Done. You're not handling duplicate successors correctly. You should call removePredecessor() once for each time it is removed. >> Some edge cases: >> - The input values are different, and go to different successors. >> Fold into a conditional branch and keep exactly one copy of both >> successors. >> - The input values are different, but their successors are the same. >> Keep folding this into an unconditional branch, and remove all but one >> successor. In particular, note that the successor being jumped to will >> have multiple PHI entries for this predecessor, and only one of those >> may remain. > > I'm confused about that last point - the verifier claims that phi nodes > should have one and only one entry for each predecessor? Duplicate predecessors should have duplicate entries. Note that it doesn't say "for each *unique* predecessor". Each predecessor should have as many entries in PHIs as the number of times it's block has the PHI's block as a successor. It also checks that all entries for the same predecessor must have the same incoming value. (In other words: "What Nick said") Note that the indirectbr code handles "duplicate successors one of which is kept" by nulling out the variable it used to check for that successor, so that if it comes across any duplicates of it they are still removed as successors. (To make sure it's correct for equal destinations of select operands, it pre-nulls the "false" destination if it would be the same as the "true" destination because the unconditional branch used in this case only has one succcessor) >> - The input values are equal, or both are caught by the default case. >> Remove all other successors and keep folding into unconditional >> branch. >> - Some successor blocks that are the successor of multiple switch >> cases which are all removed. >> - Some successor blocks that are the successor of multiple switch >> cases, some (but not all) of which are removed. >> >> Ideally your test cases should test each of these, with other edges >> (not from the switch) going to the successors and (used) PHI nodes >> there. > > Okay, tests updated. Only one test actually has a PHI node. To make sure you're doing the right thing, it's best if all successors of the switch you're removing have a PHI node. That way you can see when you e.g. forget to remove duplicate entries. (Keeping multiple PHIs alive is easily done by having the entry block contain a switch too) Also, IIRC opt will by default run the verifier at the end, so it will make the test fail if you generate incorrect code like that. However, it can probably only detect this if there are PHI nodes. >> Since all of this may enlarge the code, you may want to factor it out >> into a static helper function. You could use >> SimplifyIndirectBrOnSelect() as an example, but note that that one has >> some different edge cases (for instance, the successors it tries to >> remove may not actually be present). >> Maybe you can even share some code between that and your >> SimplifySwitchOnSelect()? You could probably factor out all of the >> code SimplifyIndirectBrOnSelect() uses to update successors[1] to a >> separate helper function; the indirectbr-specific edge cases shouldn't >> be reachable for a switch so it won't generate incorrect code. > > I've factored it out into a separate helper function, but it really didn't > inflate the code that much. Due to the many differences between > switch and indirectbr (I don't believe duplicate entries are allowed > in the successors list for indirectbr), I haven't factored out common indirectbr allows duplicate entries. LangRef.html says "Blocks are allowed to occur multiple times in the destination list, though this isn't particularly useful". > code between SimplifySwitchOnSelect and > SimplifyIndirectBrOnSelect, because there really isn't much. Actually, I think the only difference is that in the case of indirectbr the successors you want to preserve may not actually be present (and we need to handle this case). This special case will simply not occur for switches, but using a helper function which checks for this possibility shouldn't harm anything. I still think turning the end of SimplifyIndirectBrOnSelect into a separate helper function is the easiest way to make sure you're not missing anything. A stylistic issue: most of the code in your helper function is in an if (TrueVal && FalseVal). You can reduce indentation and increase clarity by using if (!TrueVal || !FalseVal) return false; instead. From echristo at apple.com Tue Jan 11 03:02:09 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 11 Jan 2011 09:02:09 -0000 Subject: [llvm-commits] [llvm] r123225 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <20110111090210.153802A6C12D@llvm.org> Author: echristo Date: Tue Jan 11 03:02:09 2011 New Revision: 123225 URL: http://llvm.org/viewvc/llvm-project?rev=123225&view=rev Log: Temporarily revert 123133, it's causing some regressions and I'm trying to get a testcase. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=123225&r1=123224&r2=123225&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jan 11 03:02:09 2011 @@ -1560,14 +1560,10 @@ AddRecOps[0] = getAddExpr(LIOps); // Build the new addrec. Propagate the NUW and NSW flags if both the - // outer add and the inner addrec are guaranteed to have no overflow or if - // there is no outer part. - if (Ops.size() != 1) { - HasNUW &= AddRec->hasNoUnsignedWrap(); - HasNSW &= AddRec->hasNoSignedWrap(); - } - - const SCEV *NewRec = getAddRecExpr(AddRecOps, AddRecLoop, HasNUW, HasNSW); + // outer add and the inner addrec are guaranteed to have no overflow. + const SCEV *NewRec = getAddRecExpr(AddRecOps, AddRecLoop, + HasNUW && AddRec->hasNoUnsignedWrap(), + HasNSW && AddRec->hasNoSignedWrap()); // If all of the other operands were loop invariant, we are done. if (Ops.size() == 1) return NewRec; From kalle.raiskila at nokia.com Tue Jan 11 03:07:54 2011 From: kalle.raiskila at nokia.com (Kalle Raiskila) Date: Tue, 11 Jan 2011 09:07:54 -0000 Subject: [llvm-commits] [llvm] r123226 - in /llvm/trunk/lib/Target/CellSPU: CMakeLists.txt SPU.h SPUInstrInfo.td SPUNopFiller.cpp SPUTargetMachine.cpp SPUTargetMachine.h Message-ID: <20110111090754.498EF2A6C12D@llvm.org> Author: kraiskil Date: Tue Jan 11 03:07:54 2011 New Revision: 123226 URL: http://llvm.org/viewvc/llvm-project?rev=123226&view=rev Log: Add a "nop filler" pass to SPU. Filling no-ops is done just before emitting of assembly, when the instruction stream is final. No-ops are inserted to align the instructions so the dual-issue of the pipeline is utilized. This speeds up generated code with a minimum of 1% on a select set of algorithms. This pass may be redundant if the instruction scheduler and all subsequent passes that modify the instruction stream (prolog+epilog inserter, register scavenger, are there others?) are made aware of the instruction alignments. Added: llvm/trunk/lib/Target/CellSPU/SPUNopFiller.cpp Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/SPU.h llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt?rev=123226&r1=123225&r2=123226&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CellSPU/CMakeLists.txt Tue Jan 11 03:07:54 2011 @@ -23,4 +23,5 @@ SPUSubtarget.cpp SPUTargetMachine.cpp SPUSelectionDAGInfo.cpp + SPUNopFiller.cpp ) Modified: llvm/trunk/lib/Target/CellSPU/SPU.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPU.h?rev=123226&r1=123225&r2=123226&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPU.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPU.h Tue Jan 11 03:07:54 2011 @@ -23,6 +23,7 @@ class formatted_raw_ostream; FunctionPass *createSPUISelDag(SPUTargetMachine &TM); + FunctionPass *createSPUNopFillerPass(SPUTargetMachine &tm); extern Target TheCellSPUTarget; } Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td?rev=123226&r1=123225&r2=123226&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.td Tue Jan 11 03:07:54 2011 @@ -4216,7 +4216,7 @@ // in the odd pipeline) //===----------------------------------------------------------------------===// -def ENOP : SPUInstr<(outs), (ins), "enop", ExecNOP> { +def ENOP : SPUInstr<(outs), (ins), "nop", ExecNOP> { let Pattern = []; let Inst{0-10} = 0b10000000010; Added: llvm/trunk/lib/Target/CellSPU/SPUNopFiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUNopFiller.cpp?rev=123226&view=auto ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUNopFiller.cpp (added) +++ llvm/trunk/lib/Target/CellSPU/SPUNopFiller.cpp Tue Jan 11 03:07:54 2011 @@ -0,0 +1,153 @@ +//===-- SPUNopFiller.cpp - Add nops/lnops to align the pipelines---===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// The final pass just before assembly printing. This pass is the last +// checkpoint where nops and lnops are added to the instruction stream to +// satisfy the dual issue requirements. The actual dual issue scheduling is +// done (TODO: nowhere, currently) +// +//===----------------------------------------------------------------------===// + +#include "SPU.h" +#include "SPUTargetMachine.h" +#include "llvm/CodeGen/MachineFunctionPass.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" +#include "llvm/Target/TargetInstrInfo.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +namespace { + struct SPUNopFiller : public MachineFunctionPass { + + TargetMachine &TM; + const TargetInstrInfo *TII; + const InstrItineraryData *IID; + bool isEvenPlace; // the instruction slot (mem address) at hand is even/odd + + static char ID; + SPUNopFiller(TargetMachine &tm) + : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()), + IID(tm.getInstrItineraryData()) + { + DEBUG( dbgs() << "********** SPU Nop filler **********\n" ; ); + } + + virtual const char *getPassName() const { + return "SPU nop/lnop Filler"; + } + + void runOnMachineBasicBlock(MachineBasicBlock &MBB); + + bool runOnMachineFunction(MachineFunction &F) { + isEvenPlace = true; //all functions get an .align 3 directive at start + for (MachineFunction::iterator FI = F.begin(), FE = F.end(); + FI != FE; ++FI) + runOnMachineBasicBlock(*FI); + return true; //never-ever do any more modifications, just print it! + } + + typedef enum { none = 0, // no more instructions in this function / BB + pseudo = 1, // this does not get executed + even = 2, + odd = 3 } SPUOpPlace; + SPUOpPlace getOpPlacement( MachineInstr &instr ); + + }; + char SPUNopFiller::ID = 0; + +} + +// Fill a BasicBlock to alignment. +// In the assebly we align the functions to 'even' adresses, but +// basic blocks have an implicit alignmnet. We hereby define +// basic blocks to have the same, even, alignment. +void SPUNopFiller:: +runOnMachineBasicBlock(MachineBasicBlock &MBB) +{ + assert( isEvenPlace && "basic block start from odd address"); + for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) + { + SPUOpPlace this_optype, next_optype; + MachineBasicBlock::iterator J = I; + J++; + + this_optype = getOpPlacement( *I ); + next_optype = none; + while (J!=MBB.end()){ + next_optype = getOpPlacement( *J ); + ++J; + if (next_optype != pseudo ) + break; + } + + // padd: odd(wrong), even(wrong), ... + // to: nop(corr), odd(corr), even(corr)... + if( isEvenPlace && this_optype == odd && next_optype == even ) { + DEBUG( dbgs() <<"Adding NOP before: "; ); + DEBUG( I->dump(); ); + BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::ENOP)); + isEvenPlace=false; + } + + // padd: even(wrong), odd(wrong), ... + // to: lnop(corr), even(corr), odd(corr)... + else if ( !isEvenPlace && this_optype == even && next_optype == odd){ + DEBUG( dbgs() <<"Adding LNOP before: "; ); + DEBUG( I->dump(); ); + BuildMI(MBB, I, I->getDebugLoc(), TII->get(SPU::LNOP)); + isEvenPlace=true; + } + + // now go to next mem slot + if( this_optype != pseudo ) + isEvenPlace = !isEvenPlace; + + } + + // padd basicblock end + if( !isEvenPlace ){ + MachineBasicBlock::iterator J = MBB.end(); + J--; + if (getOpPlacement( *J ) == odd) { + DEBUG( dbgs() <<"Padding basic block with NOP\n"; ); + BuildMI(MBB, J, J->getDebugLoc(), TII->get(SPU::ENOP)); + } + else { + J++; + DEBUG( dbgs() <<"Padding basic block with LNOP\n"; ); + BuildMI(MBB, J, J->getDebugLoc(), TII->get(SPU::LNOP)); + } + isEvenPlace=true; + } +} + +FunctionPass *llvm::createSPUNopFillerPass(SPUTargetMachine &tm) { + return new SPUNopFiller(tm); +} + +// Figure out if 'instr' is executed in the even or odd pipeline +SPUNopFiller::SPUOpPlace +SPUNopFiller::getOpPlacement( MachineInstr &instr ) { + int sc = instr.getDesc().getSchedClass(); + const InstrStage *stage = IID->beginStage(sc); + unsigned FUs = stage->getUnits(); + SPUOpPlace retval; + + switch( FUs ) { + case 0: retval = pseudo; break; + case 1: retval = odd; break; + case 2: retval = even; break; + default: retval= pseudo; + assert( false && "got unknown FuncUnit\n"); + break; + }; + return retval; +} Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=123226&r1=123225&r2=123226&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Tue Jan 11 03:07:54 2011 @@ -59,3 +59,12 @@ PM.add(createSPUISelDag(*this)); return false; } + +// passes to run just before printing the assembly +bool SPUTargetMachine:: +addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) +{ + //align instructions with nops/lnops for dual issue + PM.add(createSPUNopFillerPass(*this)); + return true; +} Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=123226&r1=123225&r2=123226&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Tue Jan 11 03:07:54 2011 @@ -82,6 +82,7 @@ // Pass Pipeline Configuration virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel); + virtual bool addPreEmitPass(PassManagerBase &, CodeGenOpt::Level); }; } // end namespace llvm From echristo at apple.com Tue Jan 11 03:20:44 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 11 Jan 2011 09:20:44 -0000 Subject: [llvm-commits] [llvm] r123227 - /llvm/trunk/test/Analysis/ScalarEvolution/nsw.ll Message-ID: <20110111092044.5EC0C2A6C12D@llvm.org> Author: echristo Date: Tue Jan 11 03:20:44 2011 New Revision: 123227 URL: http://llvm.org/viewvc/llvm-project?rev=123227&view=rev Log: Revert the testcase from the previous reverted commit. Modified: llvm/trunk/test/Analysis/ScalarEvolution/nsw.ll Modified: llvm/trunk/test/Analysis/ScalarEvolution/nsw.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/ScalarEvolution/nsw.ll?rev=123227&r1=123226&r2=123227&view=diff ============================================================================== --- llvm/trunk/test/Analysis/ScalarEvolution/nsw.ll (original) +++ llvm/trunk/test/Analysis/ScalarEvolution/nsw.ll Tue Jan 11 03:20:44 2011 @@ -75,6 +75,4 @@ _ZSt4fillIPiiEvT_S1_RKT0_.exit: ; preds = %entry, %for.cond.for.end_crit_edge.i.i ret void - -; CHECK: Loop %for.body.i.i: backedge-taken count is ((-4 + (-1 * %begin) + %end) /u 4) } From kalle.raiskila at nokia.com Tue Jan 11 05:27:56 2011 From: kalle.raiskila at nokia.com (Kalle Raiskila) Date: Tue, 11 Jan 2011 11:27:56 -0000 Subject: [llvm-commits] [llvm] r123229 - /llvm/trunk/lib/Target/CellSPU/SPUNopFiller.cpp Message-ID: <20110111112756.40ABD2A6C12D@llvm.org> Author: kraiskil Date: Tue Jan 11 05:27:56 2011 New Revision: 123229 URL: http://llvm.org/viewvc/llvm-project?rev=123229&view=rev Log: Fix a thinko in 123226 that caused test failures on "other" platforms. Modified: llvm/trunk/lib/Target/CellSPU/SPUNopFiller.cpp Modified: llvm/trunk/lib/Target/CellSPU/SPUNopFiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUNopFiller.cpp?rev=123229&r1=123228&r2=123229&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUNopFiller.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUNopFiller.cpp Tue Jan 11 05:27:56 2011 @@ -123,7 +123,7 @@ else { J++; DEBUG( dbgs() <<"Padding basic block with LNOP\n"; ); - BuildMI(MBB, J, J->getDebugLoc(), TII->get(SPU::LNOP)); + BuildMI(MBB, J, DebugLoc(), TII->get(SPU::LNOP)); } isEvenPlace=true; } From ofv at wanadoo.es Tue Jan 11 06:31:35 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Tue, 11 Jan 2011 12:31:35 -0000 Subject: [llvm-commits] [llvm] r123232 - /llvm/trunk/cmake/modules/LLVMProcessSources.cmake Message-ID: <20110111123135.14E992A6C12F@llvm.org> Author: ofv Date: Tue Jan 11 06:31:34 2011 New Revision: 123232 URL: http://llvm.org/viewvc/llvm-project?rev=123232&view=rev Log: Made llvm_replace_compiler_option more robust. Use it on llvm_process_sources. Modified: llvm/trunk/cmake/modules/LLVMProcessSources.cmake Modified: llvm/trunk/cmake/modules/LLVMProcessSources.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMProcessSources.cmake?rev=123232&r1=123231&r2=123232&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMProcessSources.cmake (original) +++ llvm/trunk/cmake/modules/LLVMProcessSources.cmake Tue Jan 11 06:31:34 2011 @@ -1,15 +1,22 @@ include(AddFileDependencies) -macro(llvm_replace_compiler_option var old new) +function(llvm_replace_compiler_option var old new) # Replaces a compiler option or switch `old' in `var' by `new'. # If `old' is not in `var', appends `new' to `var'. # Example: llvm_replace_compiler_option(CMAKE_CXX_FLAGS_RELEASE "-O3" "-O2") + # If the option already is on the variable, don't add it: + if( "${${var}}" MATCHES "(^| )${new}($| )" ) + set(n "") + else() + set(n "${new}") + endif() if( "${${var}}" MATCHES "(^| )${old}($| )" ) - string( REGEX REPLACE "(^| )${old}($| )" " ${new} " ${var} "${${var}}" ) + string( REGEX REPLACE "(^| )${old}($| )" " ${n} " ${var} "${${var}}" ) else() - set( ${var} "${${var}} ${new}" ) + set( ${var} "${${var}} ${n}" ) endif() -endmacro(llvm_replace_compiler_option) + set( ${var} "${${var}}" PARENT_SCOPE ) +endfunction(llvm_replace_compiler_option) macro(add_td_sources srcs) file(GLOB tds *.td) @@ -52,15 +59,15 @@ if( CMAKE_COMPILER_IS_GNUCXX ) add_definitions( -fno-exceptions ) elseif( MSVC ) - string( REGEX REPLACE "[ ^]/EHsc ?" " /EHs-c- " CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS}" ) + llvm_replace_compiler_option(CMAKE_CXX_FLAGS "/EHsc" "/EHs-c-") add_definitions( /D_HAS_EXCEPTIONS=0 ) endif() endif() if( NOT LLVM_REQUIRES_RTTI ) if( CMAKE_COMPILER_IS_GNUCXX ) - add_definitions( -fno-rtti ) + llvm_replace_compiler_option(CMAKE_CXX_FLAGS "-frtti" "-fno-rtti") elseif( MSVC ) - string( REGEX REPLACE "[ ^]/GR ?" " /GR- " CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS}" ) + llvm_replace_compiler_option(CMAKE_CXX_FLAGS "/GR" "/GR-") endif() endif() From ofv at wanadoo.es Tue Jan 11 06:31:54 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Tue, 11 Jan 2011 12:31:54 -0000 Subject: [llvm-commits] [llvm] r123233 - in /llvm/trunk: CMakeLists.txt cmake/config-ix.cmake include/llvm/Config/config.h.cmake Message-ID: <20110111123154.A71AA2A6C12F@llvm.org> Author: ofv Date: Tue Jan 11 06:31:54 2011 New Revision: 123233 URL: http://llvm.org/viewvc/llvm-project?rev=123233&view=rev Log: Add to the CMake build some options and platform tests supported by the traditional build. Patch by arrowdodger! Modified: llvm/trunk/CMakeLists.txt llvm/trunk/cmake/config-ix.cmake llvm/trunk/include/llvm/Config/config.h.cmake Modified: llvm/trunk/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/CMakeLists.txt?rev=123233&r1=123232&r2=123233&view=diff ============================================================================== --- llvm/trunk/CMakeLists.txt (original) +++ llvm/trunk/CMakeLists.txt Tue Jan 11 06:31:54 2011 @@ -104,6 +104,16 @@ set(CLANG_RESOURCE_DIR "" CACHE STRING "Relative directory from the Clang binary to its resource files.") +option(LLVM_ENABLE_CBE_PRINTF_A "Set to ON if CBE is enabled for printf %a output" ON) +if(LLVM_ENABLE_CBE_PRINTF_A) + set(ENABLE_CBE_PRINTF_A 1) +endif() + +option(LLVM_ENABLE_TIMESTAMPS "Enable embedding timestamp information in build" ON) +if(LLVM_ENABLE_TIMESTAMPS) + set(ENABLE_TIMESTAMPS 1) +endif() + set(C_INCLUDE_DIRS "" CACHE STRING "Colon separated list of directories clang will search for headers.") Modified: llvm/trunk/cmake/config-ix.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=123233&r1=123232&r2=123233&view=diff ============================================================================== --- llvm/trunk/cmake/config-ix.cmake (original) +++ llvm/trunk/cmake/config-ix.cmake Tue Jan 11 06:31:54 2011 @@ -31,6 +31,7 @@ # include checks check_include_file(argz.h HAVE_ARGZ_H) check_include_file(assert.h HAVE_ASSERT_H) +check_include_file(ctype.h HAVE_CTYPE_H) check_include_file(dirent.h HAVE_DIRENT_H) check_include_file(dl.h HAVE_DL_H) check_include_file(dld.h HAVE_DLD_H) @@ -92,6 +93,7 @@ check_symbol_exists(isnan math.h HAVE_ISNAN_IN_MATH_H) check_symbol_exists(ceilf math.h HAVE_CEILF) check_symbol_exists(floorf math.h HAVE_FLOORF) +check_symbol_exists(fmodf math.h HAVE_FMODF) check_symbol_exists(nearbyintf math.h HAVE_NEARBYINTF) check_symbol_exists(mallinfo malloc.h HAVE_MALLINFO) check_symbol_exists(malloc_zone_statistics malloc/malloc.h @@ -135,6 +137,7 @@ set(headers ${headers} "stdint.h") endif() +check_type_exists(int64_t "${headers}" HAVE_INT64_T) check_type_exists(uint64_t "${headers}" HAVE_UINT64_T) check_type_exists(u_int64_t "${headers}" HAVE_U_INT64_T) Modified: llvm/trunk/include/llvm/Config/config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=123233&r1=123232&r2=123233&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/config.h.cmake Tue Jan 11 06:31:54 2011 @@ -6,11 +6,8 @@ #ifndef CONFIG_H #define CONFIG_H -/* Define if dlopen(0) will open the symbols of the program */ -#undef CAN_DLOPEN_SELF - /* Define if CBE is enabled for printf %a output */ -#undef ENABLE_CBE_PRINTF_A +#cmakedefine ENABLE_CBE_PRINTF_A ${ENABLE_CBE_PRINTF_A} /* Relative directory for resource files */ #define CLANG_RESOURCE_DIR "${CLANG_RESOURCE_DIR}" @@ -33,6 +30,9 @@ /* Define if position independent code is enabled */ #cmakedefine ENABLE_PIC +/* Define if timestamp information (e.g., __DATE___) is allowed */ +#cmakedefine ENABLE_TIMESTAMPS ${ENABLE_TIMESTAMPS} + /* Define if threads enabled */ #cmakedefine ENABLE_THREADS ${ENABLE_THREADS} @@ -76,7 +76,7 @@ #undef HAVE_CLOSEDIR /* Define to 1 if you have the header file. */ -#undef HAVE_CTYPE_H +#cmakedefine HAVE_CTYPE_H ${HAVE_CTYPE_H} /* Define to 1 if you have the header file, and it defines `DIR'. */ @@ -130,6 +130,9 @@ /* Define to 1 if you have the `floorf' function. */ #cmakedefine HAVE_FLOORF ${HAVE_FLOORF} +/* Define to 1 if you have the `fmodf' function. */ +#cmakedefine HAVE_FMODF ${HAVE_FMODF} + /* Does not have forward iterator */ #undef HAVE_FWD_ITERATOR @@ -170,7 +173,7 @@ #undef HAVE_INDEX /* Define to 1 if the system has the type `int64_t'. */ -#undef HAVE_INT64_T +#cmakedefine HAVE_INT64_T ${HAVE_INT64_T} /* Define to 1 if you have the header file. */ #cmakedefine HAVE_INTTYPES_H ${HAVE_INTTYPES_H} @@ -450,7 +453,7 @@ #cmakedefine HAVE_TWOPI ${HAVE_TWOPI} /* Define to 1 if the system has the type `uint64_t'. */ -#undef HAVE_UINT64_T +#cmakedefine HAVE_UINT64_T ${HAVE_UINT64_T} /* Define to 1 if you have the header file. */ #cmakedefine HAVE_TERMIOS_H ${HAVE_TERMIOS_H} @@ -462,7 +465,7 @@ #cmakedefine HAVE_UTIME_H ${HAVE_UTIME_H} /* Define to 1 if the system has the type `u_int64_t'. */ -#undef HAVE_U_INT64_T +#cmakedefine HAVE_U_INT64_T ${HAVE_U_INT64_T} /* Define to 1 if you have the header file. */ #cmakedefine HAVE_VALGRIND_VALGRIND_H ${HAVE_VALGRIND_VALGRIND_H} From fvbommel at gmail.com Tue Jan 11 06:52:11 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Tue, 11 Jan 2011 12:52:11 -0000 Subject: [llvm-commits] [llvm] r123234 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110111125211.761852A6C12D@llvm.org> Author: fvbommel Date: Tue Jan 11 06:52:11 2011 New Revision: 123234 URL: http://llvm.org/viewvc/llvm-project?rev=123234&view=rev Log: Factor the actual simplification out of SimplifyIndirectBrOnSelect and into a new helper function so it can be reused in e.g. an upcoming SimplifySwitchOnSelect. No functional change. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=123234&r1=123233&r2=123234&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue Jan 11 06:52:11 2011 @@ -1728,22 +1728,13 @@ return true; } -// SimplifyIndirectBrOnSelect - Replaces -// (indirectbr (select cond, blockaddress(@fn, BlockA), -// blockaddress(@fn, BlockB))) -// with -// (br cond, BlockA, BlockB). -static bool SimplifyIndirectBrOnSelect(IndirectBrInst *IBI, SelectInst *SI) { - // Check that both operands of the select are block addresses. - BlockAddress *TBA = dyn_cast(SI->getTrueValue()); - BlockAddress *FBA = dyn_cast(SI->getFalseValue()); - if (!TBA || !FBA) - return false; - - // Extract the actual blocks. - BasicBlock *TrueBB = TBA->getBasicBlock(); - BasicBlock *FalseBB = FBA->getBasicBlock(); - +// SimplifyTerminatorOnSelect - Simplifies a terminator by replacing it with a +// branch to TrueBB if Cond is true or to FalseBB if Cond is false. +// Takes care of updating the successors and removing the old terminator. +// Also makes sure not to introduce new successors by assuming that edges to +// non-successor TrueBBs and FalseBBs aren't reachable. +static bool SimplifyTerminatorOnSelect(TerminatorInst *OldTerm, Value *Cond, + BasicBlock *TrueBB, BasicBlock *FalseBB){ // Remove any superfluous successor edges from the CFG. // First, figure out which successors to preserve. // If TrueBB and FalseBB are equal, only try to preserve one copy of that @@ -1752,15 +1743,15 @@ BasicBlock *KeepEdge2 = TrueBB != FalseBB ? FalseBB : 0; // Then remove the rest. - for (unsigned I = 0, E = IBI->getNumSuccessors(); I != E; ++I) { - BasicBlock *Succ = IBI->getSuccessor(I); + for (unsigned I = 0, E = OldTerm->getNumSuccessors(); I != E; ++I) { + BasicBlock *Succ = OldTerm->getSuccessor(I); // Make sure only to keep exactly one copy of each edge. if (Succ == KeepEdge1) KeepEdge1 = 0; else if (Succ == KeepEdge2) KeepEdge2 = 0; else - Succ->removePredecessor(IBI->getParent()); + Succ->removePredecessor(OldTerm->getParent()); } // Insert an appropriate new terminator. @@ -1768,31 +1759,51 @@ if (TrueBB == FalseBB) // We were only looking for one successor, and it was present. // Create an unconditional branch to it. - BranchInst::Create(TrueBB, IBI); + BranchInst::Create(TrueBB, OldTerm); else // We found both of the successors we were looking for. // Create a conditional branch sharing the condition of the select. - BranchInst::Create(TrueBB, FalseBB, SI->getCondition(), IBI); + BranchInst::Create(TrueBB, FalseBB, Cond, OldTerm); } else if (KeepEdge1 && (KeepEdge2 || TrueBB == FalseBB)) { // Neither of the selected blocks were successors, so this - // indirectbr must be unreachable. - new UnreachableInst(IBI->getContext(), IBI); + // terminator must be unreachable. + new UnreachableInst(OldTerm->getContext(), OldTerm); } else { // One of the selected values was a successor, but the other wasn't. // Insert an unconditional branch to the one that was found; // the edge to the one that wasn't must be unreachable. if (KeepEdge1 == 0) // Only TrueBB was found. - BranchInst::Create(TrueBB, IBI); + BranchInst::Create(TrueBB, OldTerm); else // Only FalseBB was found. - BranchInst::Create(FalseBB, IBI); + BranchInst::Create(FalseBB, OldTerm); } - EraseTerminatorInstAndDCECond(IBI); + EraseTerminatorInstAndDCECond(OldTerm); return true; } +// SimplifyIndirectBrOnSelect - Replaces +// (indirectbr (select cond, blockaddress(@fn, BlockA), +// blockaddress(@fn, BlockB))) +// with +// (br cond, BlockA, BlockB). +static bool SimplifyIndirectBrOnSelect(IndirectBrInst *IBI, SelectInst *SI) { + // Check that both operands of the select are block addresses. + BlockAddress *TBA = dyn_cast(SI->getTrueValue()); + BlockAddress *FBA = dyn_cast(SI->getFalseValue()); + if (!TBA || !FBA) + return false; + + // Extract the actual blocks. + BasicBlock *TrueBB = TBA->getBasicBlock(); + BasicBlock *FalseBB = FBA->getBasicBlock(); + + // Perform the actual simplification. + return SimplifyTerminatorOnSelect(IBI, SI->getCondition(), TrueBB, FalseBB); +} + /// TryToSimplifyUncondBranchWithICmpInIt - This is called when we find an icmp /// instruction (a seteq/setne with a constant) as the only instruction in a /// block that ends with an uncond branch. We are looking for a very specific From fvbommel at gmail.com Tue Jan 11 07:02:28 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Tue, 11 Jan 2011 14:02:28 +0100 Subject: [llvm-commits] PATCH: instcombine switch on select of constants to br In-Reply-To: References: <893CFB3C-832C-4959-AE72-4186FCD61E99@gmail.com> <4D2A730F.2090207@mxc.ca> <130DB463-EF73-40A2-8166-5D3A014D9D12@gmail.com> Message-ID: On Tue, Jan 11, 2011 at 9:36 AM, Frits van Bommel wrote: > I still think turning the end of SimplifyIndirectBrOnSelect into a > separate helper function is the easiest way to make sure you're not > missing anything. I just did this myself (r123234). Instead of rolling your own updating code, just substitute return SimplifyTerminatorOnSelect(SI, Select->getCondition(), TrueBB, FalseBB); for it and it should Just Work. This replaces everything in your last patch after the declaration of FalseBB to the end of the if block. From jay.foad at gmail.com Tue Jan 11 09:07:38 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 11 Jan 2011 15:07:38 -0000 Subject: [llvm-commits] [llvm] r123235 - in /llvm/trunk: include/llvm/Constants.h include/llvm/GlobalAlias.h include/llvm/GlobalVariable.h include/llvm/InstrTypes.h include/llvm/Instructions.h include/llvm/OperandTraits.h lib/Bitcode/Reader/BitcodeReader.cpp lib/VMCore/ConstantsContext.h Message-ID: <20110111150738.F03272A6C12C@llvm.org> Author: foad Date: Tue Jan 11 09:07:38 2011 New Revision: 123235 URL: http://llvm.org/viewvc/llvm-project?rev=123235&view=rev Log: FixedNumOperandTraits and VariadicOperandTraits assumed that, given a "this" pointer for any subclass of User, you could static_cast it to User* and then reinterpret_cast that to Use* to get the end of the operand list. This isn't a safe assumption in general, because the static_cast might adjust the "this" pointer. Fixed by having these OperandTraits classes take an extra template parameter, which is the subclass of User. This is groundwork for PR889. Modified: llvm/trunk/include/llvm/Constants.h llvm/trunk/include/llvm/GlobalAlias.h llvm/trunk/include/llvm/GlobalVariable.h llvm/trunk/include/llvm/InstrTypes.h llvm/trunk/include/llvm/Instructions.h llvm/trunk/include/llvm/OperandTraits.h llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/VMCore/ConstantsContext.h Modified: llvm/trunk/include/llvm/Constants.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=123235&r1=123234&r2=123235&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constants.h (original) +++ llvm/trunk/include/llvm/Constants.h Tue Jan 11 09:07:38 2011 @@ -405,7 +405,8 @@ }; template <> -struct OperandTraits : public VariadicOperandTraits<> { +struct OperandTraits : + public VariadicOperandTraits { }; DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantArray, Constant) @@ -454,7 +455,8 @@ }; template <> -struct OperandTraits : public VariadicOperandTraits<> { +struct OperandTraits : + public VariadicOperandTraits { }; DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantStruct, Constant) @@ -511,7 +513,8 @@ }; template <> -struct OperandTraits : public VariadicOperandTraits<> { +struct OperandTraits : + public VariadicOperandTraits { }; DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantVector, Constant) @@ -592,7 +595,8 @@ }; template <> -struct OperandTraits : public FixedNumOperandTraits<2> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(BlockAddress, Value) @@ -871,7 +875,8 @@ }; template <> -struct OperandTraits : public VariadicOperandTraits<1> { +struct OperandTraits : + public VariadicOperandTraits { }; DEFINE_TRANSPARENT_CASTED_OPERAND_ACCESSORS(ConstantExpr, Constant) Modified: llvm/trunk/include/llvm/GlobalAlias.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalAlias.h?rev=123235&r1=123234&r2=123235&view=diff ============================================================================== --- llvm/trunk/include/llvm/GlobalAlias.h (original) +++ llvm/trunk/include/llvm/GlobalAlias.h Tue Jan 11 09:07:38 2011 @@ -89,7 +89,8 @@ }; template <> -struct OperandTraits : public FixedNumOperandTraits<1> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GlobalAlias, Value) Modified: llvm/trunk/include/llvm/GlobalVariable.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/GlobalVariable.h?rev=123235&r1=123234&r2=123235&view=diff ============================================================================== --- llvm/trunk/include/llvm/GlobalVariable.h (original) +++ llvm/trunk/include/llvm/GlobalVariable.h Tue Jan 11 09:07:38 2011 @@ -169,7 +169,8 @@ }; template <> -struct OperandTraits : public OptionalOperandTraits<> { +struct OperandTraits : + public OptionalOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GlobalVariable, Value) Modified: llvm/trunk/include/llvm/InstrTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InstrTypes.h?rev=123235&r1=123234&r2=123235&view=diff ============================================================================== --- llvm/trunk/include/llvm/InstrTypes.h (original) +++ llvm/trunk/include/llvm/InstrTypes.h Tue Jan 11 09:07:38 2011 @@ -128,7 +128,8 @@ }; template <> -struct OperandTraits : public FixedNumOperandTraits<1> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(UnaryInstruction, Value) @@ -432,7 +433,8 @@ }; template <> -struct OperandTraits : public FixedNumOperandTraits<2> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BinaryOperator, Value) @@ -903,7 +905,7 @@ // FIXME: these are redundant if CmpInst < BinaryOperator template <> -struct OperandTraits : public FixedNumOperandTraits<2> { +struct OperandTraits : public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CmpInst, Value) Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=123235&r1=123234&r2=123235&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Tue Jan 11 09:07:38 2011 @@ -262,7 +262,7 @@ }; template <> -struct OperandTraits : public FixedNumOperandTraits<2> { +struct OperandTraits : public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(StoreInst, Value) @@ -524,7 +524,8 @@ }; template <> -struct OperandTraits : public VariadicOperandTraits<1> { +struct OperandTraits : + public VariadicOperandTraits { }; template @@ -1087,7 +1088,7 @@ }; template <> -struct OperandTraits : public VariadicOperandTraits<1> { +struct OperandTraits : public VariadicOperandTraits { }; template @@ -1195,7 +1196,7 @@ }; template <> -struct OperandTraits : public FixedNumOperandTraits<3> { +struct OperandTraits : public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SelectInst, Value) @@ -1292,7 +1293,8 @@ }; template <> -struct OperandTraits : public FixedNumOperandTraits<2> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ExtractElementInst, Value) @@ -1350,7 +1352,8 @@ }; template <> -struct OperandTraits : public FixedNumOperandTraits<3> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InsertElementInst, Value) @@ -1407,7 +1410,8 @@ }; template <> -struct OperandTraits : public FixedNumOperandTraits<3> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ShuffleVectorInst, Value) @@ -1751,7 +1755,8 @@ }; template <> -struct OperandTraits : public FixedNumOperandTraits<2> { +struct OperandTraits : + public FixedNumOperandTraits { }; template @@ -2032,7 +2037,7 @@ }; template <> -struct OperandTraits : public VariadicOperandTraits<> { +struct OperandTraits : public VariadicOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ReturnInst, Value) @@ -2125,7 +2130,8 @@ }; template <> -struct OperandTraits : public VariadicOperandTraits<1> {}; +struct OperandTraits : public VariadicOperandTraits { +}; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BranchInst, Value) @@ -2616,7 +2622,7 @@ }; template <> -struct OperandTraits : public VariadicOperandTraits<3> { +struct OperandTraits : public VariadicOperandTraits { }; template Modified: llvm/trunk/include/llvm/OperandTraits.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/OperandTraits.h?rev=123235&r1=123234&r2=123235&view=diff ============================================================================== --- llvm/trunk/include/llvm/OperandTraits.h (original) +++ llvm/trunk/include/llvm/OperandTraits.h Tue Jan 11 09:07:38 2011 @@ -27,12 +27,12 @@ /// when it is a prefix to the User object, and the number of Use objects is /// known at compile time. -template +template struct FixedNumOperandTraits { - static Use *op_begin(User* U) { + static Use *op_begin(SubClass* U) { return reinterpret_cast(U) - ARITY; } - static Use *op_end(User* U) { + static Use *op_end(SubClass* U) { return reinterpret_cast(U); } static unsigned operands(const User*) { @@ -57,8 +57,8 @@ /// OptionalOperandTraits - when the number of operands may change at runtime. /// Naturally it may only decrease, because the allocations may not change. -template -struct OptionalOperandTraits : public FixedNumOperandTraits { +template +struct OptionalOperandTraits : public FixedNumOperandTraits { static unsigned operands(const User *U) { return U->getNumOperands(); } @@ -72,12 +72,12 @@ /// when it is a prefix to the User object, and the number of Use objects is /// only known at allocation time. -template +template struct VariadicOperandTraits { - static Use *op_begin(User* U) { - return reinterpret_cast(U) - U->getNumOperands(); + static Use *op_begin(SubClass* U) { + return reinterpret_cast(U) - static_cast(U)->getNumOperands(); } - static Use *op_end(User* U) { + static Use *op_end(SubClass* U) { return reinterpret_cast(U); } static unsigned operands(const User *U) { Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=123235&r1=123234&r2=123235&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Tue Jan 11 09:07:38 2011 @@ -162,7 +162,8 @@ // FIXME: can we inherit this from ConstantExpr? template <> -struct OperandTraits : public FixedNumOperandTraits<1> { +struct OperandTraits : + public FixedNumOperandTraits { }; } Modified: llvm/trunk/lib/VMCore/ConstantsContext.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantsContext.h?rev=123235&r1=123234&r2=123235&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantsContext.h (original) +++ llvm/trunk/lib/VMCore/ConstantsContext.h Tue Jan 11 09:07:38 2011 @@ -239,54 +239,64 @@ }; template <> -struct OperandTraits : public FixedNumOperandTraits<1> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(UnaryConstantExpr, Value) template <> -struct OperandTraits : public FixedNumOperandTraits<2> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BinaryConstantExpr, Value) template <> -struct OperandTraits : public FixedNumOperandTraits<3> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SelectConstantExpr, Value) template <> -struct OperandTraits : public FixedNumOperandTraits<2> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ExtractElementConstantExpr, Value) template <> -struct OperandTraits : public FixedNumOperandTraits<3> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InsertElementConstantExpr, Value) template <> -struct OperandTraits : public FixedNumOperandTraits<3> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ShuffleVectorConstantExpr, Value) template <> -struct OperandTraits : public FixedNumOperandTraits<1> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ExtractValueConstantExpr, Value) template <> -struct OperandTraits : public FixedNumOperandTraits<2> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InsertValueConstantExpr, Value) template <> -struct OperandTraits : public VariadicOperandTraits<1> { +struct OperandTraits : + public VariadicOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GetElementPtrConstantExpr, Value) template <> -struct OperandTraits : public FixedNumOperandTraits<2> { +struct OperandTraits : + public FixedNumOperandTraits { }; DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CompareConstantExpr, Value) From daniel at zuster.org Tue Jan 11 09:59:50 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 11 Jan 2011 15:59:50 -0000 Subject: [llvm-commits] [llvm] r123238 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/arm_instructions.s Message-ID: <20110111155950.4CE322A6C12C@llvm.org> Author: ddunbar Date: Tue Jan 11 09:59:50 2011 New Revision: 123238 URL: http://llvm.org/viewvc/llvm-project?rev=123238&view=rev Log: McARM: Add more hard coded logic to SplitMnemonicAndCC to also split out the carry setting flag from the mnemonic. Note that this currently involves me disabling a number of working cases in arm_instructions.s, this is a hopefully short term evil which will be rapidly fixed (and greatly surpassed), assuming my current approach flies. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/arm_instructions.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123238&r1=123237&r2=123238&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jan 11 09:59:50 2011 @@ -866,9 +866,19 @@ } } +/// \brief Given a mnemonic, split out possible predication code and carry +/// setting letters to form a canonical mnemonic and flags. +// // FIXME: Would be nice to autogen this. -static unsigned SplitMnemonicAndCC(StringRef &Mnemonic) { +static StringRef SplitMnemonicAndCC(StringRef Mnemonic, + unsigned &PredicationCode, + bool &CarrySetting) { + PredicationCode = ARMCC::AL; + CarrySetting = false; + // Ignore some mnemonics we know aren't predicated forms. + // + // FIXME: Would be nice to autogen this. if (Mnemonic == "teq" || Mnemonic == "vceq" || Mnemonic == "movs" || Mnemonic == "svc" || @@ -881,13 +891,9 @@ (Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" || Mnemonic == "vqdmlal")) - return ARMCC::AL; + return Mnemonic; - // Otherwise, determine the predicate. - // - // FIXME: We need a way to check whether a prefix supports predication, - // otherwise we will end up with an ambiguity for instructions that happen to - // end with a predicate name. + // First, split out any predication code. unsigned CC = StringSwitch(Mnemonic.substr(Mnemonic.size()-2)) .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) @@ -907,10 +913,23 @@ .Default(~0U); if (CC != ~0U) { Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 2); - return CC; + PredicationCode = CC; } - return ARMCC::AL; + // Next, determine if we have a carry setting bit. We explicitly ignore all + // the instructions we know end in 's'. + if (Mnemonic.endswith("s") && + !(Mnemonic == "asrs" || Mnemonic == "cps" || Mnemonic == "mls" || + Mnemonic == "movs" || Mnemonic == "mrs" || Mnemonic == "smmls" || + Mnemonic == "vabs" || Mnemonic == "vcls" || Mnemonic == "vmls" || + Mnemonic == "vmrs" || Mnemonic == "vnmls" || Mnemonic == "vqabs" || + Mnemonic == "vrecps" || Mnemonic == "vrsqrts")) { + Mnemonic = Mnemonic.slice(0, Mnemonic.size() - 1); + CarrySetting = true; + } + + return Mnemonic; +} } /// Parse an arm instruction mnemonic followed by its operands. @@ -920,8 +939,10 @@ size_t Start = 0, Next = Name.find('.'); StringRef Head = Name.slice(Start, Next); - // Determine the predicate, if any. - unsigned CC = SplitMnemonicAndCC(Head); + // Split out the predication code and carry setting flag from the mnemonic. + unsigned PredicationCode; + bool CarrySetting; + Head = SplitMnemonicAndCC(Head, PredicationCode, CarrySetting); Operands.push_back(ARMOperand::CreateToken(Head, NameLoc)); Modified: llvm/trunk/test/MC/ARM/arm_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=123238&r1=123237&r2=123238&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) +++ llvm/trunk/test/MC/ARM/arm_instructions.s Tue Jan 11 09:59:50 2011 @@ -59,25 +59,29 @@ @ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0] and r1,r2,r3 -@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0] +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0] ands r1,r2,r3 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0] eor r1,r2,r3 -@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0] +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0] eors r1,r2,r3 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0] sub r1,r2,r3 -@ CHECK: subs r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0] +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: subs r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0] subs r1,r2,r3 @ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0] add r1,r2,r3 -@ CHECK: adds r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0] +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: adds r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0] adds r1,r2,r3 @ CHECK: adc r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0] @@ -89,13 +93,15 @@ @ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1] orr r1,r2,r3 -@ CHECK: orrs r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1] +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: orrs r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe1] orrs r1,r2,r3 @ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1] bic r1,r2,r3 -@ CHECK: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1] +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1] bics r1,r2,r3 @ CHECK: mov r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1] @@ -104,7 +110,8 @@ @ CHECK: mvn r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1] mvn r1,r2 -@ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1] +@ FIXME: This is wrong, we are dropping the 's' for now. +@ CHECK-FIXME: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1] mvns r1,r2 @ CHECK: rsb r1, r2, r3 @ encoding: [0x03,0x10,0x62,0xe0] @@ -113,5 +120,7 @@ @ CHECK: rsc r1, r2, r3 @ encoding: [0x03,0x10,0xe2,0xe0] rsc r1,r2,r3 -@ CHECK: mlas r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0] - mlas r1,r2,r3,r4 +@ FIXME: This is broken, CCOut operands don't work correctly when their presence +@ may depend on flags. +@ CHECK-FIXME:: mlas r1, r2, r3, r4 @ encoding: [0x92,0x43,0x31,0xe0] +@ mlas r1,r2,r3,r4 From daniel at zuster.org Tue Jan 11 09:59:53 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 11 Jan 2011 15:59:53 -0000 Subject: [llvm-commits] [llvm] r123239 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110111155953.E37CD2A6C12D@llvm.org> Author: ddunbar Date: Tue Jan 11 09:59:53 2011 New Revision: 123239 URL: http://llvm.org/viewvc/llvm-project?rev=123239&view=rev Log: McARM: Sketch some logic for determining when to add carry set and predication code operands based on the "canonical mnemonic". Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123239&r1=123238&r2=123239&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jan 11 09:59:53 2011 @@ -930,6 +930,20 @@ return Mnemonic; } + +/// \brief Given a canonical mnemonic, determine if the instruction ever allows +/// inclusion of carry set or predication code operands. +// +// FIXME: It would be nice to autogen this. +static void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, + bool &CanAcceptPredicationCode) { + CanAcceptCarrySet = false; + + if (Mnemonic == "trap") { + CanAcceptPredicationCode = false; + } else { + CanAcceptPredicationCode = true; + } } /// Parse an arm instruction mnemonic followed by its operands. @@ -946,10 +960,40 @@ Operands.push_back(ARMOperand::CreateToken(Head, NameLoc)); - // FIXME: Should only add this operand for predicated instructions - if (Head != "trap") { - Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), - NameLoc)); + // Next, add the CCOut and ConditionCode operands, if needed. + // + // For mnemonics which can ever incorporate a carry setting bit or predication + // code, our matching model involves us always generating CCOut and + // ConditionCode operands to match the mnemonic "as written" and then we let + // the matcher deal with finding the right instruction or generating an + // appropriate error. + bool CanAcceptCarrySet, CanAcceptPredicationCode; + GetMnemonicAcceptInfo(Head, CanAcceptCarrySet, CanAcceptPredicationCode); + + // Add the carry setting operand, if necessary. + // + // FIXME: It would be awesome if we could somehow invent a location such that + // match errors on this operand would print a nice diagnostic about how the + // 's' character in the mnemonic resulted in a CCOut operand. + if (CanAcceptCarrySet) { + Operands.push_back(ARMOperand::CreateCCOut(CarrySetting ? ARM::CPSR : 0, + NameLoc)); + } else { + // This mnemonic can't ever accept a carry set, but the user wrote one (or + // misspelled another mnemonic). + + // FIXME: Issue a nice error. + } + + // Add the predication code operand, if necessary. + if (CanAcceptPredicationCode) { + Operands.push_back(ARMOperand::CreateCondCode( + ARMCC::CondCodes(PredicationCode), NameLoc)); + } else { + // This mnemonic can't ever accept a predication code, but the user wrote + // one (or misspelled another mnemonic). + + // FIXME: Issue a nice error. } // Add the remaining tokens in the mnemonic. From simbuerg at googlemail.com Tue Jan 11 05:12:19 2011 From: simbuerg at googlemail.com (Andreas Simbuerger) Date: Tue, 11 Jan 2011 12:12:19 +0100 Subject: [llvm-commits] PATCH: Add single entry / single exit accessors Message-ID: <4D2C3B13.30500@googlemail.com> Hi, the attached patch adds accessors for single entry / single exit edges to the regions. The implementation(s) are copied from Region::isSimple(). A later patch will change Region::isSimple() to use the accessors instead. If a single edge cannot be found, null is returned. Cheers, Andreas -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Add-single-entry-single-exit-accessors.patch Type: text/x-patch Size: 1794 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110111/2c659ca4/attachment.bin From fvbommel at gmail.com Tue Jan 11 10:52:20 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Tue, 11 Jan 2011 17:52:20 +0100 Subject: [llvm-commits] PATCH: Add single entry / single exit accessors In-Reply-To: <4D2C3B13.30500@googlemail.com> References: <4D2C3B13.30500@googlemail.com> Message-ID: + for (pred_iterator PI = pred_begin(entry), PE = pred_end(entry); PI != PE; + ++PI) { + Pred = *PI; + if (DT->getNode(Pred) && !contains(Pred)) { + if (EE) { + EE = 0; + break; + } + + EE = new RegionEdge(Pred, entry); + } + } You seem to be leaking memory when a second edge is found. (Occurs in both getSingleEntryEdge() and getSingleExitEdge()) From clattner at apple.com Tue Jan 11 10:52:29 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 11 Jan 2011 08:52:29 -0800 Subject: [llvm-commits] [llvm] r123203 - in /llvm/trunk: lib/Target/README.txt lib/Transforms/InstCombine/InstCombineCompares.cpp test/Transforms/InstCombine/icmp.ll In-Reply-To: <20110111003645.CBDD12A6C12D@llvm.org> References: <20110111003645.CBDD12A6C12D@llvm.org> Message-ID: On Jan 10, 2011, at 4:36 PM, Owen Anderson wrote: > Author: resistor > Date: Mon Jan 10 18:36:45 2011 > New Revision: 123203 > > URL: http://llvm.org/viewvc/llvm-project?rev=123203&view=rev > Log: > Fix a random missed optimization by making InstCombine more aggressive when determining which bits are demanded by > a comparison against a constant. Very nice, thanks Owen! This is a great generalization. > + APInt RHS = CI->getValue(); I think RHS can be a const&. > + APInt Mask(BitWidth, 0); Mask is dead, please remove it and the code after the switch. -Chris > > + switch (I.getPredicate()) { > + // For a UGT comparison, we don't care about any bits that > + // correspond to the trailing ones of the comparand. The value of these > + // bits doesn't impact the outcome of the comparison, because any value > + // greater than the RHS must differ in a bit higher than these due to carry. > + case ICmpInst::ICMP_UGT: { > + unsigned trailingOnes = RHS.countTrailingOnes(); > + APInt lowBitsSet = APInt::getLowBitsSet(BitWidth, trailingOnes); > + return ~lowBitsSet; > + } > + > + // Similarly, for a ULT comparison, we don't care about the trailing zeros. > + // Any value less than the RHS must differ in a higher bit because of carries. > + case ICmpInst::ICMP_ULT: { > + unsigned trailingZeros = RHS.countTrailingZeros(); > + APInt lowBitsSet = APInt::getLowBitsSet(BitWidth, trailingZeros); > + return ~lowBitsSet; > + } > + > + default: > + return APInt::getAllOnesValue(BitWidth); > + } > + > + return Mask; > +} > > Instruction *InstCombiner::visitICmpInst(ICmpInst &I) { > bool Changed = false; > @@ -1830,8 +1869,7 @@ > APInt Op1KnownZero(BitWidth, 0), Op1KnownOne(BitWidth, 0); > > if (SimplifyDemandedBits(I.getOperandUse(0), > - isSignBit ? APInt::getSignBit(BitWidth) > - : APInt::getAllOnesValue(BitWidth), > + DemandedBitsLHSMask(I, BitWidth, isSignBit), > Op0KnownZero, Op0KnownOne, 0)) > return &I; > if (SimplifyDemandedBits(I.getOperandUse(1), > > Modified: llvm/trunk/test/Transforms/InstCombine/icmp.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/icmp.ll?rev=123203&r1=123202&r2=123203&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/InstCombine/icmp.ll (original) > +++ llvm/trunk/test/Transforms/InstCombine/icmp.ll Mon Jan 10 18:36:45 2011 > @@ -192,3 +192,20 @@ > ; CHECK-NEXT: %cmp = icmp eq i32 %x, 3 > } > > +define i1 @test21(i8 %x, i8 %y) { > +; CHECK: @test21 > +; CHECK-NOT: or i8 > +; CHECK: icmp ugt > + %A = or i8 %x, 1 > + %B = icmp ugt i8 %A, 3 > + ret i1 %B > +} > + > +define i1 @test22(i8 %x, i8 %y) { > +; CHECK: @test22 > +; CHECK-NOT: or i8 > +; CHECK: icmp ult > + %A = or i8 %x, 1 > + %B = icmp ult i8 %A, 4 > + ret i1 %B > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From sabre at nondot.org Tue Jan 11 11:04:55 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Jan 2011 17:04:55 -0000 Subject: [llvm-commits] [llvm] r123242 - in /llvm/trunk: lib/Target/X86/X86InstrSSE.td test/MC/X86/x86-64.s Message-ID: <20110111170455.764B42A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 11:04:55 2011 New Revision: 123242 URL: http://llvm.org/viewvc/llvm-project?rev=123242&view=rev Log: Fix PR8946, a missing reg/reg form of movdqu. Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/MC/X86/x86-64.s Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=123242&r1=123241&r2=123242&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jan 11 11:04:55 2011 @@ -2201,6 +2201,10 @@ def MOVDQArr : PDI<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "movdqa\t{$src, $dst|$dst, $src}", []>; +def MOVDQUrr : I<0x6F, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), + "movdqu\t{$src, $dst|$dst, $src}", + []>, XS, Requires<[HasSSE2]>; + let canFoldAsLoad = 1, mayLoad = 1 in { def MOVDQArm : PDI<0x6F, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src), "movdqa\t{$src, $dst|$dst, $src}", Modified: llvm/trunk/test/MC/X86/x86-64.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=123242&r1=123241&r2=123242&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/x86-64.s (original) +++ llvm/trunk/test/MC/X86/x86-64.s Tue Jan 11 11:04:55 2011 @@ -924,3 +924,5 @@ // PR8855 movq 18446744073709551615,%rbx // CHECK: movq -1, %rbx +// PR8946 +movdqu %xmm0, %xmm1 // CHECK: movdqu %xmm0, %xmm1 # encoding: [0xf3,0x0f,0x6f,0xc8] From sabre at nondot.org Tue Jan 11 11:12:00 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Jan 2011 17:12:00 -0000 Subject: [llvm-commits] [llvm] r123243 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp Message-ID: <20110111171200.36F612A6C12D@llvm.org> Author: lattner Date: Tue Jan 11 11:11:59 2011 New Revision: 123243 URL: http://llvm.org/viewvc/llvm-project?rev=123243&view=rev Log: some comment improvements. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolution.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolution.h?rev=123243&r1=123242&r2=123243&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolution.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolution.h Tue Jan 11 11:11:59 2011 @@ -537,8 +537,9 @@ /// const SCEV *getNotSCEV(const SCEV *V); - /// getMinusSCEV - Return LHS-RHS. - /// + /// getMinusSCEV - Return LHS-RHS. Minus is represented in SCEV as A+B*-1, + /// and thus the HasNUW and HasNSW bits apply to the resultant add, not + /// whether the sub would have overflowed. const SCEV *getMinusSCEV(const SCEV *LHS, const SCEV *RHS, bool HasNUW = false, bool HasNSW = false); Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=123243&r1=123242&r2=123243&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue Jan 11 11:11:59 2011 @@ -2446,8 +2446,9 @@ return getMinusSCEV(AllOnes, V); } -/// getMinusSCEV - Return a SCEV corresponding to LHS - RHS. -/// +/// getMinusSCEV - Return LHS-RHS. Minus is represented in SCEV as A+B*-1, +/// and thus the HasNUW and HasNSW bits apply to the resultant add, not +/// whether the sub would have overflowed. const SCEV *ScalarEvolution::getMinusSCEV(const SCEV *LHS, const SCEV *RHS, bool HasNUW, bool HasNSW) { // Fast path: X - X --> 0. @@ -4021,7 +4022,7 @@ cast(RHSA->getOperand(1))->getValue(); // If the strides are equal, then this is just a (complex) loop invariant - // comparison of a/b. + // comparison of a and b. if (LHSStride == RHSStride) return SE.getMinusSCEV(LHSA->getStart(), RHSA->getStart()); From sabre at nondot.org Tue Jan 11 11:16:35 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Jan 2011 09:16:35 -0800 Subject: [llvm-commits] [llvm] r123131 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp In-Reply-To: <9F4529E4-DEDD-44EE-8EE8-16DE3C7E5113@apple.com> References: <20110109222635.527042A6C12C@llvm.org> <9F4529E4-DEDD-44EE-8EE8-16DE3C7E5113@apple.com> Message-ID: <34473955-0F55-4763-9702-2AF0212E3534@nondot.org> On Jan 10, 2011, at 2:07 PM, Dan Gohman wrote: > On Jan 9, 2011, at 2:26 PM, Chris Lattner wrote: >> /// getMinusSCEV - Return a SCEV corresponding to LHS - RHS. >> /// >> -const SCEV *ScalarEvolution::getMinusSCEV(const SCEV *LHS, >> - const SCEV *RHS) { >> +const SCEV *ScalarEvolution::getMinusSCEV(const SCEV *LHS, const SCEV *RHS, >> + bool HasNUW, bool HasNSW) { >> // Fast path: X - X --> 0. >> if (LHS == RHS) >> return getConstant(LHS->getType(), 0); >> >> // X - Y --> X + -Y >> - return getAddExpr(LHS, getNegativeSCEV(RHS)); >> + return getAddExpr(LHS, getNegativeSCEV(RHS), HasNUW, HasNSW); > > This isn't safe. For example, suppose X and Y are bot INT_MIN (dynamically). > Then X - Y does not overflow, but X + -Y does. Ok, the only current client of this is reasoning about the generated add, not the hypothetical subtract. You're right that this is confusing, I added a clarifying comment in r123243. >> +static const SCEVAddRecExpr * >> +isSimpleUnwrappingAddRec(const SCEV *S, const Loop *L) { >> + const SCEVAddRecExpr *SA = dyn_cast(S); >> + >> + // The SCEV must be an addrec of this loop. >> + if (!SA || SA->getLoop() != L || !SA->isAffine()) >> + return 0; >> + >> + // The SCEV must be known to not wrap in some way to be interesting. >> + if (!SA->hasNoUnsignedWrap() && !SA->hasNoSignedWrap()) >> + return 0; > > It's suspicious that this code doesn't care which of nsw or nuw > the instruction has. NSW is enough to know that the bounds is limited to (e.g.) 2^32, just in a different coordinate space. It means you can't "stride past" a value. > >> >> + >> + // If the strides are equal, then this is just a (complex) loop invariant >> + // comparison of a/b. >> + if (LHSStride == RHSStride) >> + return SE.getMinusSCEV(LHSA->getStart(), RHSA->getStart()); > > The comment should say a-b, not a/b. Ok, I didn't actually mean divide, I tweaked the wording. >> + // If the signs of the strides differ, then the negative stride is counting >> + // down to the positive stride. >> + if (LHSStride->getValue().isNegative() != RHSStride->getValue().isNegative()){ >> + if (RHSStride->getValue().isNegative()) >> + std::swap(LHS, RHS); >> + } else { >> + // If LHS's stride is smaller than RHS's stride, then "b" must be less than >> + // "a" and "b" is RHS is counting up (catching up) to LHS. This is true >> + // whether the strides are positive or negative. >> + if (RHSStride->getValue().slt(LHSStride->getValue())) >> + std::swap(LHS, RHS); >> + } >> + >> + return SE.getMinusSCEV(LHS, RHS, true /*HasNUW*/); > > This isn't safe if the addrecs are nsw but not nuw (following the suspicion > above). How so? Thanks for the review!! -Chris From bob.wilson at apple.com Tue Jan 11 11:56:41 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 11 Jan 2011 17:56:41 -0000 Subject: [llvm-commits] [llvm] r123246 - /llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Message-ID: <20110111175641.5162C2A6C12D@llvm.org> Author: bwilson Date: Tue Jan 11 11:56:41 2011 New Revision: 123246 URL: http://llvm.org/viewvc/llvm-project?rev=123246&view=rev Log: Fix a comment: We now have intrinsics for vcvtr. Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=123246&r1=123245&r2=123246&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Tue Jan 11 11:56:41 2011 @@ -615,7 +615,6 @@ } // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR. -// For disassembly only. let Uses = [FPSCR] in { // FIXME: Verify encoding after integrated assembler is working. def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011, From sabre at nondot.org Tue Jan 11 12:14:50 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 11 Jan 2011 18:14:50 -0000 Subject: [llvm-commits] [llvm] r123247 - /llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Message-ID: <20110111181450.F33702A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 12:14:50 2011 New Revision: 123247 URL: http://llvm.org/viewvc/llvm-project?rev=123247&view=rev Log: this pass claims to preserve scev, make sure to tell it about deletions. Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Modified: llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp?rev=123247&r1=123246&r2=123247&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LoopSimplify.cpp Tue Jan 11 12:14:50 2011 @@ -268,6 +268,7 @@ (PN = dyn_cast(I++)); ) if (Value *V = SimplifyInstruction(PN, 0, DT)) { if (AA) AA->deleteValue(PN); + if (SE) SE->forgetValue(PN); PN->replaceAllUsesWith(V); PN->eraseFromParent(); } From resistor at mac.com Tue Jan 11 12:26:37 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 11 Jan 2011 18:26:37 -0000 Subject: [llvm-commits] [llvm] r123248 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Message-ID: <20110111182637.B722E2A6C12C@llvm.org> Author: resistor Date: Tue Jan 11 12:26:37 2011 New Revision: 123248 URL: http://llvm.org/viewvc/llvm-project?rev=123248&view=rev Log: Remove dead variable, const-ref-ize an APInt. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=123248&r1=123247&r2=123248&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Tue Jan 11 12:26:37 2011 @@ -1703,9 +1703,7 @@ ConstantInt *CI = dyn_cast(I.getOperand(1)); if (!CI) return APInt::getAllOnesValue(BitWidth); - - APInt RHS = CI->getValue(); - APInt Mask(BitWidth, 0); + const APInt &RHS = CI->getValue(); switch (I.getPredicate()) { // For a UGT comparison, we don't care about any bits that @@ -1730,7 +1728,6 @@ return APInt::getAllOnesValue(BitWidth); } - return Mask; } Instruction *InstCombiner::visitICmpInst(ICmpInst &I) { From daniel at zuster.org Tue Jan 11 13:06:26 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 11 Jan 2011 19:06:26 -0000 Subject: [llvm-commits] [llvm] r123252 - in /llvm/trunk/utils/Target: ./ ARM/ ARM/analyze-match-table.py Message-ID: <20110111190626.89A092A6C12C@llvm.org> Author: ddunbar Date: Tue Jan 11 13:06:26 2011 New Revision: 123252 URL: http://llvm.org/viewvc/llvm-project?rev=123252&view=rev Log: McARM: Write a silly Python script to compute some hard coded info from the generated ARM match table, which is substantially more efficient than dealing with tblgen. Added: llvm/trunk/utils/Target/ llvm/trunk/utils/Target/ARM/ llvm/trunk/utils/Target/ARM/analyze-match-table.py Added: llvm/trunk/utils/Target/ARM/analyze-match-table.py URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/Target/ARM/analyze-match-table.py?rev=123252&view=auto ============================================================================== --- llvm/trunk/utils/Target/ARM/analyze-match-table.py (added) +++ llvm/trunk/utils/Target/ARM/analyze-match-table.py Tue Jan 11 13:06:26 2011 @@ -0,0 +1,61 @@ +#!/usr/bin/env python + +def analyze_match_table(path): + # Extract the instruction table. + data = open(path).read() + start = data.index("static const MatchEntry MatchTable") + end = data.index("\n};\n", start) + lines = data[start:end].split("\n")[1:] + + # Parse the instructions. + insns = [] + for ln in lines: + ln = ln.split("{", 1)[1] + ln = ln.rsplit("}", 1)[0] + a,bc = ln.split("{", 1) + b,c = bc.split("}", 1) + code, string, converter, _ = [s.strip() + for s in a.split(",")] + items = [s.strip() for s in b.split(",")] + _,features = [s.strip() for s in c.split(",")] + assert string[0] == string[-1] == '"' + string = string[1:-1] + insns.append((code,string,converter,items,features)) + + # For every mnemonic, compute whether or not it can have a carry setting + # operand and whether or not it can have a predication code. + mnemonic_flags = {} + for insn in insns: + mnemonic = insn[1] + items = insn[3] + flags = mnemonic_flags[mnemonic] = mnemonic_flags.get(mnemonic, set()) + flags.update(items) + + mnemonics = set(mnemonic_flags) + ccout_mnemonics = set(m for m in mnemonics + if 'MCK_CCOut' in mnemonic_flags[m]) + condcode_mnemonics = set(m for m in mnemonics + if 'MCK_CondCode' in mnemonic_flags[m]) + noncondcode_mnemonics = mnemonics - condcode_mnemonics + print ' || '.join('Mnemonic == "%s"' % m + for m in ccout_mnemonics) + print ' || '.join('Mnemonic == "%s"' % m + for m in noncondcode_mnemonics) + +def main(): + import sys + if len(sys.argv) == 1: + import os + from lit.Util import capture + llvm_obj_root = capture(["llvm-config", "--obj-root"]) + file = os.path.join(llvm_obj_root, + "lib/Target/ARM/ARMGenAsmMatcher.inc") + elif len(sys.argv) == 2: + file = sys.argv[1] + else: + raise NotImplementedError + + analyze_match_table(file) + +if __name__ == '__main__': + main() From daniel at zuster.org Tue Jan 11 13:06:29 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 11 Jan 2011 19:06:29 -0000 Subject: [llvm-commits] [llvm] r123253 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110111190629.D25252A6C12D@llvm.org> Author: ddunbar Date: Tue Jan 11 13:06:29 2011 New Revision: 123253 URL: http://llvm.org/viewvc/llvm-project?rev=123253&view=rev Log: McARM: Fill in GetMnemonicAcceptInfo(). Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123253&r1=123252&r2=123253&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jan 11 13:06:29 2011 @@ -937,9 +937,24 @@ // FIXME: It would be nice to autogen this. static void GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) { - CanAcceptCarrySet = false; + if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || + Mnemonic == "rrx" || Mnemonic == "ror" || Mnemonic == "sub" || + Mnemonic == "smull" || Mnemonic == "add" || Mnemonic == "adc" || + Mnemonic == "mul" || Mnemonic == "bic" || Mnemonic == "asr" || + Mnemonic == "umlal" || Mnemonic == "orr" || Mnemonic == "mov" || + Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || + Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || + Mnemonic == "eor" || Mnemonic == "smlal" || Mnemonic == "mvn") { + CanAcceptCarrySet = true; + } else { + CanAcceptCarrySet = false; + } - if (Mnemonic == "trap") { + if (Mnemonic == "cbnz" || Mnemonic == "setend" || Mnemonic == "dmb" || + Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" || + Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" || + Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" || + Mnemonic == "dsb" || Mnemonic == "movs") { CanAcceptPredicationCode = false; } else { CanAcceptPredicationCode = true; From stoklund at 2pi.dk Tue Jan 11 13:26:30 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 11 Jan 2011 19:26:30 -0000 Subject: [llvm-commits] [llvm] r123254 - in /llvm/trunk/include/llvm/Analysis: DominatorInternals.h Dominators.h Message-ID: <20110111192630.C96CF2A6C12C@llvm.org> Author: stoklund Date: Tue Jan 11 13:26:30 2011 New Revision: 123254 URL: http://llvm.org/viewvc/llvm-project?rev=123254&view=rev Log: Speculatively revert the recent improvements to Dominators.h in an attempt to track down the gcc bootstrap miscompare. Modified: llvm/trunk/include/llvm/Analysis/DominatorInternals.h llvm/trunk/include/llvm/Analysis/Dominators.h Modified: llvm/trunk/include/llvm/Analysis/DominatorInternals.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DominatorInternals.h?rev=123254&r1=123253&r2=123254&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DominatorInternals.h (original) +++ llvm/trunk/include/llvm/Analysis/DominatorInternals.h Tue Jan 11 13:26:30 2011 @@ -22,9 +22,13 @@ // A Fast Algorithm for Finding Dominators in a Flowgraph // T. Lengauer & R. Tarjan, ACM TOPLAS July 1979, pgs 121-141. // -// This implements the O(n*log(n)) versions of EVAL and LINK, because it turns -// out that the theoretically slower O(n*log(n)) implementation is actually -// faster than the almost-linear O(n*alpha(n)) version, even for large CFGs. +// This implements both the O(n*ack(n)) and the O(n*log(n)) versions of EVAL and +// LINK, but it turns out that the theoretically slower O(n*log(n)) +// implementation is actually faster than the "efficient" algorithm (even for +// large CFGs) because the constant overheads are substantially smaller. The +// lower-complexity version can be enabled with the following #define: +// +#define BALANCE_IDOM_TREE 0 // //===----------------------------------------------------------------------===// @@ -54,7 +58,7 @@ } } #else - bool IsChildOfArtificialExit = (N != 0); + bool IsChilOfArtificialExit = (N != 0); std::vector > Worklist; @@ -76,10 +80,10 @@ //BBInfo[V].Child = 0; // Child[v] = 0 BBInfo.Size = 1; // Size[v] = 1 - if (IsChildOfArtificialExit) + if (IsChilOfArtificialExit) BBInfo.Parent = 1; - IsChildOfArtificialExit = false; + IsChilOfArtificialExit = false; } // store the DFS number of the current BB - the reference to BBInfo might @@ -153,17 +157,75 @@ typename GraphT::NodeType *V) { typename DominatorTreeBase::InfoRec &VInfo = DT.Info[V]; +#if !BALANCE_IDOM_TREE + // Higher-complexity but faster implementation if (VInfo.Ancestor == 0) return V; Compress(DT, V); return VInfo.Label; +#else + // Lower-complexity but slower implementation + if (VInfo.Ancestor == 0) + return VInfo.Label; + Compress(DT, V); + GraphT::NodeType* VLabel = VInfo.Label; + + GraphT::NodeType* VAncestorLabel = DT.Info[VInfo.Ancestor].Label; + if (DT.Info[VAncestorLabel].Semi >= DT.Info[VLabel].Semi) + return VLabel; + else + return VAncestorLabel; +#endif } template void Link(DominatorTreeBase& DT, unsigned DFSNumV, typename GraphT::NodeType* W, typename DominatorTreeBase::InfoRec &WInfo) { +#if !BALANCE_IDOM_TREE + // Higher-complexity but faster implementation WInfo.Ancestor = DFSNumV; +#else + // Lower-complexity but slower implementation + GraphT::NodeType* WLabel = WInfo.Label; + unsigned WLabelSemi = DT.Info[WLabel].Semi; + GraphT::NodeType* S = W; + InfoRec *SInfo = &DT.Info[S]; + + GraphT::NodeType* SChild = SInfo->Child; + InfoRec *SChildInfo = &DT.Info[SChild]; + + while (WLabelSemi < DT.Info[SChildInfo->Label].Semi) { + GraphT::NodeType* SChildChild = SChildInfo->Child; + if (SInfo->Size+DT.Info[SChildChild].Size >= 2*SChildInfo->Size) { + SChildInfo->Ancestor = S; + SInfo->Child = SChild = SChildChild; + SChildInfo = &DT.Info[SChild]; + } else { + SChildInfo->Size = SInfo->Size; + S = SInfo->Ancestor = SChild; + SInfo = SChildInfo; + SChild = SChildChild; + SChildInfo = &DT.Info[SChild]; + } + } + + DominatorTreeBase::InfoRec &VInfo = DT.Info[V]; + SInfo->Label = WLabel; + + assert(V != W && "The optimization here will not work in this case!"); + unsigned WSize = WInfo.Size; + unsigned VSize = (VInfo.Size += WSize); + + if (VSize < 2*WSize) + std::swap(S, VInfo.Child); + + while (S) { + SInfo = &DT.Info[S]; + SInfo->Ancestor = V; + S = SInfo->Child; + } +#endif } template @@ -195,34 +257,12 @@ // infinite loops). In these cases an artificial exit node is required. MultipleRoots |= (DT.isPostDominator() && N != F.size()); - // When naively implemented, the Lengauer-Tarjan algorithm requires a separate - // bucket for each vertex. However, this is unnecessary, because each vertex - // is only placed into a single bucket (that of its semidominator), and each - // vertex's bucket is processed before it is added to any bucket itself. - // - // Instead of using a bucket per vertex, we use a single array Buckets that - // has two purposes. Before the vertex V with preorder number i is processed, - // Buckets[i] stores the index of the first element in V's bucket. After V's - // bucket is processed, Buckets[i] stores the index of the next element in the - // bucket containing V, if any. - std::vector Buckets; - Buckets.resize(N + 1); - for (unsigned i = 1; i <= N; ++i) - Buckets[i] = i; - for (unsigned i = N; i >= 2; --i) { typename GraphT::NodeType* W = DT.Vertex[i]; typename DominatorTreeBase::InfoRec &WInfo = DT.Info[W]; - // Step #2: Implicitly define the immediate dominator of vertices - for (unsigned j = i; Buckets[j] != i; j = Buckets[j]) { - typename GraphT::NodeType* V = DT.Vertex[Buckets[j]]; - typename GraphT::NodeType* U = Eval(DT, V); - DT.IDoms[V] = DT.Info[U].Semi < i ? U : W; - } - - // Step #3: Calculate the semidominators of all vertices + // Step #2: Calculate the semidominators of all vertices // initialize the semi dominator to point to the parent node WInfo.Semi = WInfo.Parent; @@ -238,24 +278,26 @@ } } + typename GraphT::NodeType* WParent = DT.Vertex[WInfo.Parent]; + // If V is a non-root vertex and sdom(V) = parent(V), then idom(V) is // necessarily parent(V). In this case, set idom(V) here and avoid placing // V into a bucket. - if (WInfo.Semi == WInfo.Parent) { - DT.IDoms[W] = DT.Vertex[WInfo.Parent]; - } else { - Buckets[i] = Buckets[WInfo.Semi]; - Buckets[WInfo.Semi] = i; - } + if (WInfo.Semi == WInfo.Parent) + DT.IDoms[W] = WParent; + else + DT.Info[DT.Vertex[WInfo.Semi]].Bucket.push_back(W); Link(DT, WInfo.Parent, W, WInfo); - } - if (N >= 1) { - typename GraphT::NodeType* Root = DT.Vertex[1]; - for (unsigned j = 1; Buckets[j] != 1; j = Buckets[j]) { - typename GraphT::NodeType* V = DT.Vertex[Buckets[j]]; - DT.IDoms[V] = Root; + // Step #3: Implicitly define the immediate dominator of vertices + std::vector &WParentBucket = + DT.Info[WParent].Bucket; + while (!WParentBucket.empty()) { + typename GraphT::NodeType* V = WParentBucket.back(); + WParentBucket.pop_back(); + typename GraphT::NodeType* U = Eval(DT, V); + DT.IDoms[V] = DT.Info[U].Semi < DT.Info[V].Semi ? U : WParent; } } Modified: llvm/trunk/include/llvm/Analysis/Dominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=123254&r1=123253&r2=123254&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/Dominators.h (original) +++ llvm/trunk/include/llvm/Analysis/Dominators.h Tue Jan 11 13:26:30 2011 @@ -200,6 +200,8 @@ NodeT *Label, *Child; unsigned Parent, Ancestor; + std::vector Bucket; + InfoRec() : DFSNum(0), Semi(0), Size(0), Label(0), Child(0), Parent(0), Ancestor(0) {} }; @@ -291,6 +293,9 @@ : DominatorBase(isPostDom), DFSInfoValid(false), SlowQueries(0) {} virtual ~DominatorTreeBase() { reset(); } + // FIXME: Should remove this + virtual bool runOnFunction(Function &F) { return false; } + /// compare - Return false if the other dominator tree base matches this /// dominator tree base. Otherwise return true. bool compare(DominatorTreeBase &Other) const { From gohman at apple.com Tue Jan 11 13:36:10 2011 From: gohman at apple.com (Dan Gohman) Date: Tue, 11 Jan 2011 11:36:10 -0800 Subject: [llvm-commits] [llvm] r123131 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolution.h lib/Analysis/ScalarEvolution.cpp In-Reply-To: <34473955-0F55-4763-9702-2AF0212E3534@nondot.org> References: <20110109222635.527042A6C12C@llvm.org> <9F4529E4-DEDD-44EE-8EE8-16DE3C7E5113@apple.com> <34473955-0F55-4763-9702-2AF0212E3534@nondot.org> Message-ID: <27D0D229-AF31-4314-B451-40B81E43D2DA@apple.com> On Jan 11, 2011, at 9:16 AM, Chris Lattner wrote: > On Jan 10, 2011, at 2:07 PM, Dan Gohman wrote: >> On Jan 9, 2011, at 2:26 PM, Chris Lattner wrote: >>> /// getMinusSCEV - Return a SCEV corresponding to LHS - RHS. >>> /// >>> -const SCEV *ScalarEvolution::getMinusSCEV(const SCEV *LHS, >>> - const SCEV *RHS) { >>> +const SCEV *ScalarEvolution::getMinusSCEV(const SCEV *LHS, const SCEV *RHS, >>> + bool HasNUW, bool HasNSW) { >>> // Fast path: X - X --> 0. >>> if (LHS == RHS) >>> return getConstant(LHS->getType(), 0); >>> >>> // X - Y --> X + -Y >>> - return getAddExpr(LHS, getNegativeSCEV(RHS)); >>> + return getAddExpr(LHS, getNegativeSCEV(RHS), HasNUW, HasNSW); >> >> This isn't safe. For example, suppose X and Y are bot INT_MIN (dynamically). >> Then X - Y does not overflow, but X + -Y does. > > Ok, the only current client of this is reasoning about the generated add, not the hypothetical subtract. You're right that this is confusing, I added a clarifying comment in r123243. For the unsigned case, this is still really confusing. Take the most innocent- looking expression like "X - 1" for example. This turns into X + UINT_MAX, which has unsigned overflow. For the signed case, setting HasNSW requires proving that the RHS is not UINT_MIN. A side note here is that the nsw and nuw concepts don't cover every interesting kind of overflow. There are many situations where one operand of an add is unsigned and the other operand is signed, but these are hard to represent since they're asymmetric. > >>> +static const SCEVAddRecExpr * >>> +isSimpleUnwrappingAddRec(const SCEV *S, const Loop *L) { >>> + const SCEVAddRecExpr *SA = dyn_cast(S); >>> + >>> + // The SCEV must be an addrec of this loop. >>> + if (!SA || SA->getLoop() != L || !SA->isAffine()) >>> + return 0; >>> + >>> + // The SCEV must be known to not wrap in some way to be interesting. >>> + if (!SA->hasNoUnsignedWrap() && !SA->hasNoSignedWrap()) >>> + return 0; >> >> It's suspicious that this code doesn't care which of nsw or nuw >> the instruction has. > > NSW is enough to know that the bounds is limited to (e.g.) 2^32, just in a different coordinate space. It means you can't "stride past" a value. Unsigned overflow happens in the middle of the signed range. Signed overflow happens at two points along the unsigned range. It's quite possible to have a well-behaved stride pattern in one range that doesn't "stride past" its destination, but does happen to cross over the overflow point of the other range. >>> + // If the signs of the strides differ, then the negative stride is counting >>> + // down to the positive stride. >>> + if (LHSStride->getValue().isNegative() != RHSStride->getValue().isNegative()){ >>> + if (RHSStride->getValue().isNegative()) >>> + std::swap(LHS, RHS); >>> + } else { >>> + // If LHS's stride is smaller than RHS's stride, then "b" must be less than >>> + // "a" and "b" is RHS is counting up (catching up) to LHS. This is true >>> + // whether the strides are positive or negative. >>> + if (RHSStride->getValue().slt(LHSStride->getValue())) >>> + std::swap(LHS, RHS); >>> + } >>> + >>> + return SE.getMinusSCEV(LHS, RHS, true /*HasNUW*/); >> >> This isn't safe if the addrecs are nsw but not nuw (following the suspicion >> above). > > How so? Suppose LHS is {X,+,-1} and RHS is {-4,+,1}. Both could legitimately have NSW and not NUW. In the sixth iteration of the loop, LHS is X-6 and RHS is 1. X-6 - 1 => X-6 + -1 => X-6 + UINT_MAX, which has unsigned overflow if X != 6. Dan From rafael.espindola at gmail.com Tue Jan 11 14:15:28 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 11 Jan 2011 15:15:28 -0500 Subject: [llvm-commits] [llvm] r123254 - in /llvm/trunk/include/llvm/Analysis: DominatorInternals.h Dominators.h In-Reply-To: <20110111192630.C96CF2A6C12C@llvm.org> References: <20110111192630.C96CF2A6C12C@llvm.org> Message-ID: <4D2CBA60.7010601@gmail.com> On 11-01-11 2:26 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Tue Jan 11 13:26:30 2011 > New Revision: 123254 > > URL: http://llvm.org/viewvc/llvm-project?rev=123254&view=rev > Log: > Speculatively revert the recent improvements to Dominators.h in an attempt to track down the gcc bootstrap miscompare. Sorry, still causes a bootstrap failure on linux x86-64 :-( Cheers, Rafael From zwarich at apple.com Tue Jan 11 14:23:34 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Tue, 11 Jan 2011 20:23:34 -0000 Subject: [llvm-commits] [llvm] r123270 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp Message-ID: <20110111202334.3A8E82A6C12C@llvm.org> Author: zwarich Date: Tue Jan 11 14:23:34 2011 New Revision: 123270 URL: http://llvm.org/viewvc/llvm-project?rev=123270&view=rev Log: Attempt to fix the bootstrap buildbot. Rafael says this works for him on x86-64 Linux. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=123270&r1=123269&r2=123270&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue Jan 11 14:23:34 2011 @@ -2011,6 +2011,7 @@ RE = RPOT.end(); RI != RE; ++RI) Changed |= processBlock(*RI); #else + DT->DT->recalculate(F); for (df_iterator DI = df_begin(DT->getRootNode()), DE = df_end(DT->getRootNode()); DI != DE; ++DI) Changed |= processBlock(DI->getBlock()); From stoklund at 2pi.dk Tue Jan 11 15:23:09 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 11 Jan 2011 21:23:09 -0000 Subject: [llvm-commits] [llvm] r123273 - in /llvm/trunk/include/llvm/Analysis: DominatorInternals.h Dominators.h Message-ID: <20110111212309.B5EC42A6C12C@llvm.org> Author: stoklund Date: Tue Jan 11 15:23:09 2011 New Revision: 123273 URL: http://llvm.org/viewvc/llvm-project?rev=123273&view=rev Log: Put the Dominator improvements back in. They were not the cause of bootstrap miscomparisons. Modified: llvm/trunk/include/llvm/Analysis/DominatorInternals.h llvm/trunk/include/llvm/Analysis/Dominators.h Modified: llvm/trunk/include/llvm/Analysis/DominatorInternals.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DominatorInternals.h?rev=123273&r1=123272&r2=123273&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DominatorInternals.h (original) +++ llvm/trunk/include/llvm/Analysis/DominatorInternals.h Tue Jan 11 15:23:09 2011 @@ -22,13 +22,9 @@ // A Fast Algorithm for Finding Dominators in a Flowgraph // T. Lengauer & R. Tarjan, ACM TOPLAS July 1979, pgs 121-141. // -// This implements both the O(n*ack(n)) and the O(n*log(n)) versions of EVAL and -// LINK, but it turns out that the theoretically slower O(n*log(n)) -// implementation is actually faster than the "efficient" algorithm (even for -// large CFGs) because the constant overheads are substantially smaller. The -// lower-complexity version can be enabled with the following #define: -// -#define BALANCE_IDOM_TREE 0 +// This implements the O(n*log(n)) versions of EVAL and LINK, because it turns +// out that the theoretically slower O(n*log(n)) implementation is actually +// faster than the almost-linear O(n*alpha(n)) version, even for large CFGs. // //===----------------------------------------------------------------------===// @@ -58,7 +54,7 @@ } } #else - bool IsChilOfArtificialExit = (N != 0); + bool IsChildOfArtificialExit = (N != 0); std::vector > Worklist; @@ -80,10 +76,10 @@ //BBInfo[V].Child = 0; // Child[v] = 0 BBInfo.Size = 1; // Size[v] = 1 - if (IsChilOfArtificialExit) + if (IsChildOfArtificialExit) BBInfo.Parent = 1; - IsChilOfArtificialExit = false; + IsChildOfArtificialExit = false; } // store the DFS number of the current BB - the reference to BBInfo might @@ -157,75 +153,17 @@ typename GraphT::NodeType *V) { typename DominatorTreeBase::InfoRec &VInfo = DT.Info[V]; -#if !BALANCE_IDOM_TREE - // Higher-complexity but faster implementation if (VInfo.Ancestor == 0) return V; Compress(DT, V); return VInfo.Label; -#else - // Lower-complexity but slower implementation - if (VInfo.Ancestor == 0) - return VInfo.Label; - Compress(DT, V); - GraphT::NodeType* VLabel = VInfo.Label; - - GraphT::NodeType* VAncestorLabel = DT.Info[VInfo.Ancestor].Label; - if (DT.Info[VAncestorLabel].Semi >= DT.Info[VLabel].Semi) - return VLabel; - else - return VAncestorLabel; -#endif } template void Link(DominatorTreeBase& DT, unsigned DFSNumV, typename GraphT::NodeType* W, typename DominatorTreeBase::InfoRec &WInfo) { -#if !BALANCE_IDOM_TREE - // Higher-complexity but faster implementation WInfo.Ancestor = DFSNumV; -#else - // Lower-complexity but slower implementation - GraphT::NodeType* WLabel = WInfo.Label; - unsigned WLabelSemi = DT.Info[WLabel].Semi; - GraphT::NodeType* S = W; - InfoRec *SInfo = &DT.Info[S]; - - GraphT::NodeType* SChild = SInfo->Child; - InfoRec *SChildInfo = &DT.Info[SChild]; - - while (WLabelSemi < DT.Info[SChildInfo->Label].Semi) { - GraphT::NodeType* SChildChild = SChildInfo->Child; - if (SInfo->Size+DT.Info[SChildChild].Size >= 2*SChildInfo->Size) { - SChildInfo->Ancestor = S; - SInfo->Child = SChild = SChildChild; - SChildInfo = &DT.Info[SChild]; - } else { - SChildInfo->Size = SInfo->Size; - S = SInfo->Ancestor = SChild; - SInfo = SChildInfo; - SChild = SChildChild; - SChildInfo = &DT.Info[SChild]; - } - } - - DominatorTreeBase::InfoRec &VInfo = DT.Info[V]; - SInfo->Label = WLabel; - - assert(V != W && "The optimization here will not work in this case!"); - unsigned WSize = WInfo.Size; - unsigned VSize = (VInfo.Size += WSize); - - if (VSize < 2*WSize) - std::swap(S, VInfo.Child); - - while (S) { - SInfo = &DT.Info[S]; - SInfo->Ancestor = V; - S = SInfo->Child; - } -#endif } template @@ -257,12 +195,34 @@ // infinite loops). In these cases an artificial exit node is required. MultipleRoots |= (DT.isPostDominator() && N != F.size()); + // When naively implemented, the Lengauer-Tarjan algorithm requires a separate + // bucket for each vertex. However, this is unnecessary, because each vertex + // is only placed into a single bucket (that of its semidominator), and each + // vertex's bucket is processed before it is added to any bucket itself. + // + // Instead of using a bucket per vertex, we use a single array Buckets that + // has two purposes. Before the vertex V with preorder number i is processed, + // Buckets[i] stores the index of the first element in V's bucket. After V's + // bucket is processed, Buckets[i] stores the index of the next element in the + // bucket containing V, if any. + std::vector Buckets; + Buckets.resize(N + 1); + for (unsigned i = 1; i <= N; ++i) + Buckets[i] = i; + for (unsigned i = N; i >= 2; --i) { typename GraphT::NodeType* W = DT.Vertex[i]; typename DominatorTreeBase::InfoRec &WInfo = DT.Info[W]; - // Step #2: Calculate the semidominators of all vertices + // Step #2: Implicitly define the immediate dominator of vertices + for (unsigned j = i; Buckets[j] != i; j = Buckets[j]) { + typename GraphT::NodeType* V = DT.Vertex[Buckets[j]]; + typename GraphT::NodeType* U = Eval(DT, V); + DT.IDoms[V] = DT.Info[U].Semi < i ? U : W; + } + + // Step #3: Calculate the semidominators of all vertices // initialize the semi dominator to point to the parent node WInfo.Semi = WInfo.Parent; @@ -278,26 +238,24 @@ } } - typename GraphT::NodeType* WParent = DT.Vertex[WInfo.Parent]; - // If V is a non-root vertex and sdom(V) = parent(V), then idom(V) is // necessarily parent(V). In this case, set idom(V) here and avoid placing // V into a bucket. - if (WInfo.Semi == WInfo.Parent) - DT.IDoms[W] = WParent; - else - DT.Info[DT.Vertex[WInfo.Semi]].Bucket.push_back(W); + if (WInfo.Semi == WInfo.Parent) { + DT.IDoms[W] = DT.Vertex[WInfo.Parent]; + } else { + Buckets[i] = Buckets[WInfo.Semi]; + Buckets[WInfo.Semi] = i; + } Link(DT, WInfo.Parent, W, WInfo); + } - // Step #3: Implicitly define the immediate dominator of vertices - std::vector &WParentBucket = - DT.Info[WParent].Bucket; - while (!WParentBucket.empty()) { - typename GraphT::NodeType* V = WParentBucket.back(); - WParentBucket.pop_back(); - typename GraphT::NodeType* U = Eval(DT, V); - DT.IDoms[V] = DT.Info[U].Semi < DT.Info[V].Semi ? U : WParent; + if (N >= 1) { + typename GraphT::NodeType* Root = DT.Vertex[1]; + for (unsigned j = 1; Buckets[j] != 1; j = Buckets[j]) { + typename GraphT::NodeType* V = DT.Vertex[Buckets[j]]; + DT.IDoms[V] = Root; } } Modified: llvm/trunk/include/llvm/Analysis/Dominators.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/Dominators.h?rev=123273&r1=123272&r2=123273&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/Dominators.h (original) +++ llvm/trunk/include/llvm/Analysis/Dominators.h Tue Jan 11 15:23:09 2011 @@ -200,8 +200,6 @@ NodeT *Label, *Child; unsigned Parent, Ancestor; - std::vector Bucket; - InfoRec() : DFSNum(0), Semi(0), Size(0), Label(0), Child(0), Parent(0), Ancestor(0) {} }; @@ -293,9 +291,6 @@ : DominatorBase(isPostDom), DFSInfoValid(false), SlowQueries(0) {} virtual ~DominatorTreeBase() { reset(); } - // FIXME: Should remove this - virtual bool runOnFunction(Function &F) { return false; } - /// compare - Return false if the other dominator tree base matches this /// dominator tree base. Otherwise return true. bool compare(DominatorTreeBase &Other) const { From dpatel at apple.com Tue Jan 11 15:42:10 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 11 Jan 2011 21:42:10 -0000 Subject: [llvm-commits] [llvm] r123274 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20110111214210.89D702A6C12C@llvm.org> Author: dpatel Date: Tue Jan 11 15:42:10 2011 New Revision: 123274 URL: http://llvm.org/viewvc/llvm-project?rev=123274&view=rev Log: Appropriately truncate debug info range in dwarf output. This is not yet completely enabled. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=123274&r1=123273&r2=123274&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Jan 11 15:42:10 2011 @@ -2257,15 +2257,6 @@ } } -/// isDbgValueInUndefinedReg - Return true if debug value, encoded by -/// DBG_VALUE instruction, is in undefined reg. -static bool isDbgValueInUndefinedReg(const MachineInstr *MI) { - assert (MI->isDebugValue() && "Invalid DBG_VALUE machine instruction!"); - if (MI->getOperand(0).isReg() && !MI->getOperand(0).getReg()) - return true; - return false; -} - /// isDbgValueInDefinedReg - Return true if debug value, encoded by /// DBG_VALUE instruction, is in a defined reg. static bool isDbgValueInDefinedReg(const MachineInstr *MI) { @@ -2290,7 +2281,7 @@ for (MachineBasicBlock::const_iterator II = I->begin(), IE = I->end(); II != IE; ++II) { const MachineInstr *MInsn = II; - if (!MInsn->isDebugValue() || isDbgValueInUndefinedReg(MInsn)) + if (!MInsn->isDebugValue()) continue; DbgValues.push_back(MInsn); } @@ -2312,19 +2303,18 @@ ME = DbgValues.end(); MI != ME; ++MI) { const MDNode *Var = (*MI)->getOperand((*MI)->getNumOperands()-1).getMetadata(); - if (Var == DV && isDbgValueInDefinedReg(*MI) && + if (Var == DV && !PrevMI->isIdenticalTo(*MI)) MultipleValues.push_back(*MI); PrevMI = *MI; } - DbgScope *Scope = findDbgScope(MInsn); - bool CurFnArg = false; + DbgScope *Scope = NULL; if (DV.getTag() == dwarf::DW_TAG_arg_variable && DISubprogram(DV.getContext()).describes(MF->getFunction())) - CurFnArg = true; - if (!Scope && CurFnArg) Scope = CurrentFnDbgScope; + else + Scope = findDbgScope(MInsn); // If variable scope is not found then skip this variable. if (!Scope) continue; From evan.cheng at apple.com Tue Jan 11 15:46:47 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Jan 2011 21:46:47 -0000 Subject: [llvm-commits] [llvm] r123276 - in /llvm/trunk/lib/Target/ARM: ARMAsmPrinter.cpp ARMFrameLowering.cpp ARMHazardRecognizer.cpp ARMSubtarget.cpp ARMSubtarget.h AsmParser/ARMAsmParser.cpp Message-ID: <20110111214647.3BA632A6C12C@llvm.org> Author: evancheng Date: Tue Jan 11 15:46:47 2011 New Revision: 123276 URL: http://llvm.org/viewvc/llvm-project?rev=123276&view=rev Log: Clean up ARM subtarget code by using Triple ADT. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=123276&r1=123275&r2=123276&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Jan 11 15:46:47 2011 @@ -14,14 +14,15 @@ #define DEBUG_TYPE "asm-printer" #include "ARM.h" -#include "ARMBuildAttrs.h" +#include "ARMAsmPrinter.h" #include "ARMAddressingModes.h" +#include "ARMBuildAttrs.h" +#include "ARMBaseRegisterInfo.h" #include "ARMConstantPoolValue.h" -#include "InstPrinter/ARMInstPrinter.h" -#include "ARMAsmPrinter.h" #include "ARMMachineFunctionInfo.h" #include "ARMTargetMachine.h" #include "ARMTargetObjectFile.h" +#include "InstPrinter/ARMInstPrinter.h" #include "llvm/Analysis/DebugInfo.h" #include "llvm/Constants.h" #include "llvm/Module.h" Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=123276&r1=123275&r2=123276&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Tue Jan 11 15:46:47 2011 @@ -14,6 +14,7 @@ #include "ARMFrameLowering.h" #include "ARMAddressingModes.h" #include "ARMBaseInstrInfo.h" +#include "ARMBaseRegisterInfo.h" #include "ARMMachineFunctionInfo.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" Modified: llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp?rev=123276&r1=123275&r2=123276&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp Tue Jan 11 15:46:47 2011 @@ -9,6 +9,7 @@ #include "ARMHazardRecognizer.h" #include "ARMBaseInstrInfo.h" +#include "ARMBaseRegisterInfo.h" #include "ARMSubtarget.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/ScheduleDAG.h" Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=123276&r1=123275&r2=123276&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Tue Jan 11 15:46:47 2011 @@ -13,6 +13,7 @@ #include "ARMSubtarget.h" #include "ARMGenSubtarget.inc" +#include "ARMBaseRegisterInfo.h" #include "llvm/GlobalValue.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Support/CommandLine.h" @@ -56,7 +57,7 @@ , AllowsUnalignedMem(false) , stackAlignment(4) , CPUString("generic") - , TargetType(isELF) // Default to ELF unless otherwise specified. + , TargetTriple(TT) , TargetABI(ARM_ABI_APCS) { // Default to soft float ABI if (FloatABIType == FloatABI::Default) @@ -118,12 +119,6 @@ } } - if (Len >= 10) { - if (TT.find("-darwin") != std::string::npos) - // arm-darwin - TargetType = isDarwin; - } - if (TT.find("eabi") != std::string::npos) TargetABI = ARM_ABI_AAPCS; Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=123276&r1=123275&r2=123276&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Jan 11 15:46:47 2011 @@ -17,7 +17,7 @@ #include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetSubtarget.h" -#include "ARMBaseRegisterInfo.h" +#include "llvm/ADT/Triple.h" #include namespace llvm { @@ -126,6 +126,9 @@ /// CPUString - String name of used CPU. std::string CPUString; + /// TargetTriple - What processor and OS we're targeting. + Triple TargetTriple; + /// Selected instruction itineraries (one entry per itinerary class.) InstrItineraryData InstrItins; @@ -187,8 +190,8 @@ bool hasFP16() const { return HasFP16; } bool hasD16() const { return HasD16; } - bool isTargetDarwin() const { return TargetType == isDarwin; } - bool isTargetELF() const { return TargetType == isELF; } + bool isTargetDarwin() const { return TargetTriple.getOS() == Triple::Darwin; } + bool isTargetELF() const { return !isTargetDarwin(); } bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; } bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123276&r1=123275&r2=123276&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jan 11 15:46:47 2011 @@ -9,6 +9,7 @@ #include "ARM.h" #include "ARMAddressingModes.h" +#include "ARMBaseRegisterInfo.h" #include "ARMSubtarget.h" #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" From stoklund at 2pi.dk Tue Jan 11 16:11:16 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 11 Jan 2011 22:11:16 -0000 Subject: [llvm-commits] [llvm] r123277 - /llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Message-ID: <20110111221116.8A5062A6C12C@llvm.org> Author: stoklund Date: Tue Jan 11 16:11:16 2011 New Revision: 123277 URL: http://llvm.org/viewvc/llvm-project?rev=123277&view=rev Log: Don't insert DBG_VALUE instructions after the first terminator. For one, MachineBasicBlock::getFirstTerminator() doesn't understand what is happening, and it also makes sense to have all control flow run through the DBG_VALUE. Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=123277&r1=123276&r2=123277&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Tue Jan 11 16:11:16 2011 @@ -587,6 +587,13 @@ SlotIndex Start = LIS.getMBBStartIdx(MBB); Idx = Idx.getBaseIndex(); + // Don't insert anything after the first terminator. + MachineBasicBlock::iterator Term = MBB->getFirstTerminator(); + if (Term != MBB->end() && Idx >= LIS.getInstructionIndex(Term)) { + DL = Term->getDebugLoc(); + return Term; + } + // Try to find an insert location by going backwards from Idx. MachineInstr *MI; while (!(MI = LIS.getInstructionFromIndex(Idx))) { From zwarich at apple.com Tue Jan 11 16:14:42 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Tue, 11 Jan 2011 22:14:42 -0000 Subject: [llvm-commits] [llvm] r123278 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp Message-ID: <20110111221442.42B672A6C12C@llvm.org> Author: zwarich Date: Tue Jan 11 16:14:42 2011 New Revision: 123278 URL: http://llvm.org/viewvc/llvm-project?rev=123278&view=rev Log: Dial back the speculative fix for PR8954 a bit, so that we only recompute dominators once at the beginning of GVN instead of once per iteration. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=123278&r1=123277&r2=123278&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue Jan 11 16:14:42 2011 @@ -1754,6 +1754,9 @@ unsigned Iteration = 0; + // FIXME: Remove this when PR8954 is fixed. + DT->DT->recalculate(F); + while (ShouldContinue) { DEBUG(dbgs() << "GVN iteration: " << Iteration << "\n"); ShouldContinue = iterateOnFunction(F); @@ -2011,7 +2014,6 @@ RE = RPOT.end(); RI != RE; ++RI) Changed |= processBlock(*RI); #else - DT->DT->recalculate(F); for (df_iterator DI = df_begin(DT->getRootNode()), DE = df_end(DT->getRootNode()); DI != DE; ++DI) Changed |= processBlock(DI->getBlock()); From venkatra at cs.wisc.edu Tue Jan 11 16:38:28 2011 From: venkatra at cs.wisc.edu (Venkatraman Govindaraju) Date: Tue, 11 Jan 2011 22:38:28 -0000 Subject: [llvm-commits] [llvm] r123281 - in /llvm/trunk: lib/Target/Sparc/SparcInstrInfo.td test/CodeGen/SPARC/2011-01-11-CC.ll Message-ID: <20110111223828.BFA212A6C12C@llvm.org> Author: venkatra Date: Tue Jan 11 16:38:28 2011 New Revision: 123281 URL: http://llvm.org/viewvc/llvm-project?rev=123281&view=rev Log: SPARC backend: correct ICC/FCC uses for ADDX and SELECT_CC Added: llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll (with props) Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=123281&r1=123280&r2=123281&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Tue Jan 11 16:38:28 2011 @@ -233,36 +233,39 @@ // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after // instruction selection into a branch sequence. This has to handle all // permutations of selection between i32/f32/f64 on ICC and FCC. -let Uses = [ICC], - usesCustomInserter = 1 in { // Expanded after instruction selection. + // Expanded after instruction selection. +let Uses = [ICC], usesCustomInserter = 1 in { def SELECT_CC_Int_ICC : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), "; SELECT_CC_Int_ICC PSEUDO!", [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F, imm:$Cond))]>; + def SELECT_CC_FP_ICC + : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), + "; SELECT_CC_FP_ICC PSEUDO!", + [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, + imm:$Cond))]>; + + def SELECT_CC_DFP_ICC + : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), + "; SELECT_CC_DFP_ICC PSEUDO!", + [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, + imm:$Cond))]>; +} + +let usesCustomInserter = 1, Uses = [FCC] in { + def SELECT_CC_Int_FCC : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond), "; SELECT_CC_Int_FCC PSEUDO!", [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F, imm:$Cond))]>; -} -let usesCustomInserter = 1, Uses = [FCC] in { - def SELECT_CC_FP_ICC - : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), - "; SELECT_CC_FP_ICC PSEUDO!", - [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F, - imm:$Cond))]>; def SELECT_CC_FP_FCC : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond), "; SELECT_CC_FP_FCC PSEUDO!", [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F, imm:$Cond))]>; - def SELECT_CC_DFP_ICC - : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), - "; SELECT_CC_DFP_ICC PSEUDO!", - [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F, - imm:$Cond))]>; def SELECT_CC_DFP_FCC : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond), "; SELECT_CC_DFP_FCC PSEUDO!", @@ -440,7 +443,8 @@ let Defs = [ICC] in defm ADDCC : F3_12<"addcc", 0b010000, addc>; -defm ADDX : F3_12<"addx", 0b001000, adde>; +let Uses = [ICC] in + defm ADDX : F3_12<"addx", 0b001000, adde>; // Section B.15 - Subtract Instructions, p. 110 defm SUB : F3_12 <"sub" , 0b000100, sub>; Added: llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll?rev=123281&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll (added) +++ llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll Tue Jan 11 16:38:28 2011 @@ -0,0 +1,76 @@ +; RUN: llc -march=sparc <%s | FileCheck %s + + +define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind readnone noinline { +entry: +; CHECK: addcc +; CHECK-NOT: subcc +; CHECK: addx + %0 = add i64 %a, %b + %1 = icmp ugt i64 %0, %c + %2 = zext i1 %1 to i32 + ret i32 %2 +} + + +define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline { +entry: +; CHECK: test_select_int_icc +; CHECK: subcc +; CHECK: be + %0 = icmp eq i32 %a, 0 + %1 = select i1 %0, i32 %b, i32 %c + ret i32 %1 +} + + +define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline { +entry: +; CHECK: test_select_fp_icc +; CHECK: subcc +; CHECK: be + %0 = icmp eq i32 %a, 0 + %1 = select i1 %0, float %f1, float %f2 + ret float %1 +} + +define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline { +entry: +; CHECK: test_select_fp_icc +; CHECK: subcc +; CHECK: be + %0 = icmp eq i32 %a, 0 + %1 = select i1 %0, double %f1, double %f2 + ret double %1 +} + +define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline { +entry: +;CHECK: test_select_int_fcc +;CHECK: fcmps +;CHECK: fbne + %0 = fcmp une float %f, 0.000000e+00 + %a.b = select i1 %0, i32 %a, i32 %b + ret i32 %a.b +} + + +define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline { +entry: +;CHECK: test_select_fp_fcc +;CHECK: fcmps +;CHECK: fbne + %0 = fcmp une float %f, 0.000000e+00 + %1 = select i1 %0, float %f1, float %f2 + ret float %1 +} + +define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline { +entry: +;CHECK: test_select_dfp_fcc +;CHECK: fcmpd +;CHECK: fbne + %0 = fcmp une double %f, 0.000000e+00 + %1 = select i1 %0, double %f1, double %f2 + ret double %1 +} Propchange: llvm/trunk/test/CodeGen/SPARC/2011-01-11-CC.ll ------------------------------------------------------------------------------ svn:executable = * From stoklund at 2pi.dk Tue Jan 11 16:45:28 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 11 Jan 2011 22:45:28 -0000 Subject: [llvm-commits] [llvm] r123282 - in /llvm/trunk: lib/CodeGen/LiveDebugVariables.cpp test/CodeGen/X86/2010-05-26-DotDebugLoc.ll test/CodeGen/X86/2010-05-28-Crash.ll test/CodeGen/X86/dbg-value-range.ll Message-ID: <20110111224528.E17182A6C12C@llvm.org> Author: stoklund Date: Tue Jan 11 16:45:28 2011 New Revision: 123282 URL: http://llvm.org/viewvc/llvm-project?rev=123282&view=rev Log: Enable LiveDebugVariables by default. Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll llvm/trunk/test/CodeGen/X86/dbg-value-range.ll Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=123282&r1=123281&r2=123282&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Tue Jan 11 16:45:28 2011 @@ -40,7 +40,7 @@ using namespace llvm; static cl::opt -EnableLDV("live-debug-variables", +EnableLDV("live-debug-variables", cl::init(true), cl::desc("Enable the live debug variables pass"), cl::Hidden); char LiveDebugVariables::ID = 0; Modified: llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll?rev=123282&r1=123281&r2=123282&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll Tue Jan 11 16:45:28 2011 @@ -61,6 +61,6 @@ ; CHECK-NEXT: .short 1 ; CHECK-NEXT: .byte 85 ; CHECK-NEXT: .quad Ltmp3 -; CHECK-NEXT: .quad Lfunc_end +; CHECK-NEXT: .quad Ltmp6 ; CHECK-NEXT: .short 1 ; CHECK-NEXT: .byte 83 Modified: llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll?rev=123282&r1=123281&r2=123282&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll Tue Jan 11 16:45:28 2011 @@ -39,6 +39,6 @@ !13 = metadata !{i32 7, i32 0, metadata !14, null} !14 = metadata !{i32 524299, metadata !8, i32 6, i32 0} ; [ DW_TAG_lexical_block ] -;CHECK: DEBUG_VALUE: bar:x <- EBX+0 -;CHECK-NEXT:Ltmp -;CHECK-NEXT: DEBUG_VALUE: foo:y <- 1+0 +;CHECK: DEBUG_VALUE: bar:x <- E +;CHECK: Ltmp +;CHECK: DEBUG_VALUE: foo:y <- 1+0 Modified: llvm/trunk/test/CodeGen/X86/dbg-value-range.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-range.ll?rev=123282&r1=123281&r2=123282&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-value-range.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-value-range.ll Tue Jan 11 16:45:28 2011 @@ -1,5 +1,4 @@ ; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s -; XFAIL: * %struct.a = type { i32 } From stoklund at 2pi.dk Tue Jan 11 16:54:38 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 11 Jan 2011 22:54:38 -0000 Subject: [llvm-commits] [llvm] r123286 - /llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Message-ID: <20110111225438.882BC2A6C12C@llvm.org> Author: stoklund Date: Tue Jan 11 16:54:38 2011 New Revision: 123286 URL: http://llvm.org/viewvc/llvm-project?rev=123286&view=rev Log: Fix a non-deterministic loop in llvm::MergeBlockIntoPredecessor. DT->changeImmediateDominator() trivially ignores identity updates, so there is really no need for the uniqueing provided by SmallPtrSet. I expect this to fix PR8954. Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=123286&r1=123285&r2=123286&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Tue Jan 11 16:54:38 2011 @@ -169,8 +169,8 @@ if (DominatorTree *DT = P->getAnalysisIfAvailable()) { if (DomTreeNode *DTN = DT->getNode(BB)) { DomTreeNode *PredDTN = DT->getNode(PredBB); - SmallPtrSet Children(DTN->begin(), DTN->end()); - for (SmallPtrSet::iterator DI = Children.begin(), + SmallVector Children(DTN->begin(), DTN->end()); + for (SmallVector::iterator DI = Children.begin(), DE = Children.end(); DI != DE; ++DI) DT->changeImmediateDominator(*DI, PredDTN); From stoklund at 2pi.dk Tue Jan 11 16:56:41 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 11 Jan 2011 22:56:41 -0000 Subject: [llvm-commits] [llvm] r123288 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp Message-ID: <20110111225641.2EC412A6C12C@llvm.org> Author: stoklund Date: Tue Jan 11 16:56:41 2011 New Revision: 123288 URL: http://llvm.org/viewvc/llvm-project?rev=123288&view=rev Log: Remove the PR8954 workaround. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=123288&r1=123287&r2=123288&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue Jan 11 16:56:41 2011 @@ -1753,10 +1753,6 @@ } unsigned Iteration = 0; - - // FIXME: Remove this when PR8954 is fixed. - DT->DT->recalculate(F); - while (ShouldContinue) { DEBUG(dbgs() << "GVN iteration: " << Iteration << "\n"); ShouldContinue = iterateOnFunction(F); From stoklund at 2pi.dk Tue Jan 11 17:20:33 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 11 Jan 2011 23:20:33 -0000 Subject: [llvm-commits] [llvm] r123290 - in /llvm/trunk: lib/CodeGen/LiveDebugVariables.cpp test/CodeGen/X86/2010-05-26-DotDebugLoc.ll test/CodeGen/X86/2010-05-28-Crash.ll test/CodeGen/X86/dbg-value-range.ll Message-ID: <20110111232034.0DFDC2A6C12C@llvm.org> Author: stoklund Date: Tue Jan 11 17:20:33 2011 New Revision: 123290 URL: http://llvm.org/viewvc/llvm-project?rev=123290&view=rev Log: The world is not ready for LiveDebugVariables yet. Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll llvm/trunk/test/CodeGen/X86/dbg-value-range.ll Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=123290&r1=123289&r2=123290&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Tue Jan 11 17:20:33 2011 @@ -40,7 +40,7 @@ using namespace llvm; static cl::opt -EnableLDV("live-debug-variables", cl::init(true), +EnableLDV("live-debug-variables", cl::desc("Enable the live debug variables pass"), cl::Hidden); char LiveDebugVariables::ID = 0; Modified: llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll?rev=123290&r1=123289&r2=123290&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll Tue Jan 11 17:20:33 2011 @@ -61,6 +61,6 @@ ; CHECK-NEXT: .short 1 ; CHECK-NEXT: .byte 85 ; CHECK-NEXT: .quad Ltmp3 -; CHECK-NEXT: .quad Ltmp6 +; CHECK-NEXT: .quad Lfunc_end ; CHECK-NEXT: .short 1 ; CHECK-NEXT: .byte 83 Modified: llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll?rev=123290&r1=123289&r2=123290&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll Tue Jan 11 17:20:33 2011 @@ -39,6 +39,6 @@ !13 = metadata !{i32 7, i32 0, metadata !14, null} !14 = metadata !{i32 524299, metadata !8, i32 6, i32 0} ; [ DW_TAG_lexical_block ] -;CHECK: DEBUG_VALUE: bar:x <- E -;CHECK: Ltmp -;CHECK: DEBUG_VALUE: foo:y <- 1+0 +;CHECK: DEBUG_VALUE: bar:x <- EBX+0 +;CHECK-NEXT:Ltmp +;CHECK-NEXT: DEBUG_VALUE: foo:y <- 1+0 Modified: llvm/trunk/test/CodeGen/X86/dbg-value-range.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-range.ll?rev=123290&r1=123289&r2=123290&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-value-range.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-value-range.ll Tue Jan 11 17:20:33 2011 @@ -1,4 +1,5 @@ ; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s +; XFAIL: * %struct.a = type { i32 } From jason.w.kim.2009 at gmail.com Tue Jan 11 17:53:41 2011 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Tue, 11 Jan 2011 23:53:41 -0000 Subject: [llvm-commits] [llvm] r123292 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/elf-movt.s Message-ID: <20110111235341.A4A2E2A6C12C@llvm.org> Author: jasonwkim Date: Tue Jan 11 17:53:41 2011 New Revision: 123292 URL: http://llvm.org/viewvc/llvm-project?rev=123292&view=rev Log: Workaround for bug 8721. .s Test added. Added: llvm/trunk/test/MC/ARM/elf-movt.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123292&r1=123291&r2=123292&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jan 11 17:53:41 2011 @@ -55,6 +55,10 @@ bool ParseRegisterList(SmallVectorImpl &); bool ParseMemory(SmallVectorImpl &); bool ParseOperand(SmallVectorImpl &); + bool ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind); + const MCExpr *ApplyPrefixToExpr(const MCExpr *E, + MCSymbolRefExpr::VariantKind Variant); + bool ParseMemoryOffsetReg(bool &Negative, bool &OffsetRegShifted, @@ -864,9 +868,111 @@ E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); return false; + case AsmToken::Colon: { + // ":lower16:" and ":upper16:" expression prefixes + MCSymbolRefExpr::VariantKind RefKind; + if (ParsePrefix(RefKind)) + return true; + + const MCExpr *ExprVal; + if (getParser().ParseExpression(ExprVal)) + return true; + + // TODO: Attach the prefix to the entire expression + // instead of just the first symbol. + const MCExpr *ModExprVal = ApplyPrefixToExpr(ExprVal, RefKind); + if (!ModExprVal) { + return TokError("invalid modifier '" + getTok().getIdentifier() + + "' (no symbols present)"); + } + + E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); + Operands.push_back(ARMOperand::CreateImm(ModExprVal, S, E)); + return false; + } } } +// FIXME: The next 2 routines are hacks to get ARMAsmParser to understand +// :lower16: and :upper16: +// It still attaches VK_ARM_HI/LO16 to MCSymbolRefExpr, but it really +// should be attached to the entire MCExpr as a whole - perhaps using +// MCTargetExpr? +bool ARMAsmParser::ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind) { + RefKind = MCSymbolRefExpr::VK_None; + + // :lower16: and :upper16: modifiers + if (getLexer().isNot(AsmToken::Colon)) { + Error(Parser.getTok().getLoc(), "expected :"); + return true; + } + Parser.Lex(); // Eat ':' + + if (getLexer().isNot(AsmToken::Identifier)) { + Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); + return true; + } + + StringRef IDVal = Parser.getTok().getIdentifier(); + if (IDVal == "lower16") { + RefKind = MCSymbolRefExpr::VK_ARM_LO16; + } else if (IDVal == "upper16") { + RefKind = MCSymbolRefExpr::VK_ARM_HI16; + } else { + Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); + return true; + } + Parser.Lex(); + + if (getLexer().isNot(AsmToken::Colon)) { + Error(Parser.getTok().getLoc(), "unexpected token after prefix"); + return true; + } + Parser.Lex(); // Eat the last ':' + return false; +} + +const MCExpr * +ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E, + MCSymbolRefExpr::VariantKind Variant) { + // Recurse over the given expression, rebuilding it to apply the given variant + // to the leftmost symbol. + if (Variant == MCSymbolRefExpr::VK_None) + return E; + + switch (E->getKind()) { + case MCExpr::Target: + llvm_unreachable("Can't handle target expr yet"); + case MCExpr::Constant: + llvm_unreachable("Can't handle lower16/upper16 of constant yet"); + + case MCExpr::SymbolRef: { + const MCSymbolRefExpr *SRE = cast(E); + + if (SRE->getKind() != MCSymbolRefExpr::VK_None) + return 0; + + return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); + } + + case MCExpr::Unary: + llvm_unreachable("Can't handle unary expressions yet"); + + case MCExpr::Binary: { + const MCBinaryExpr *BE = cast(E); + const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant); + const MCExpr *RHS = BE->getRHS(); + if (!LHS) + return 0; + + return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); + } + } + + assert(0 && "Invalid expression kind!"); + return 0; +} + /// \brief Given a mnemonic, split out possible predication code and carry /// setting letters to form a canonical mnemonic and flags. // Added: llvm/trunk/test/MC/ARM/elf-movt.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123292&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/elf-movt.s (added) +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 17:53:41 2011 @@ -0,0 +1,14 @@ +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s + .syntax unified + .text + .globl barf + .align 2 + .type barf,%function +barf: @ @barf +@ BB#0: @ %entry + movw r0, :lower16:GOT-(.LPC0_2+8) + movt r0, :upper16:GOT-(.LPC0_2+16) +.LPC0_2: +@ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) +@ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) + From jasonwkim at google.com Tue Jan 11 18:12:05 2011 From: jasonwkim at google.com (Jason Kim) Date: Tue, 11 Jan 2011 16:12:05 -0800 Subject: [llvm-commits] [llvm] r123292 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/elf-movt.s In-Reply-To: <20110111235341.A4A2E2A6C12C@llvm.org> References: <20110111235341.A4A2E2A6C12C@llvm.org> Message-ID: original patch by David Meyer Thanks David! -jason On Tue, Jan 11, 2011 at 3:53 PM, Jason W Kim wrote: > Author: jasonwkim > Date: Tue Jan 11 17:53:41 2011 > New Revision: 123292 > > URL: http://llvm.org/viewvc/llvm-project?rev=123292&view=rev > Log: > Workaround for bug 8721. > .s Test added. > > > Added: > ? ?llvm/trunk/test/MC/ARM/elf-movt.s > Modified: > ? ?llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > > Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123292&r1=123291&r2=123292&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jan 11 17:53:41 2011 > @@ -55,6 +55,10 @@ > ? bool ParseRegisterList(SmallVectorImpl &); > ? bool ParseMemory(SmallVectorImpl &); > ? bool ParseOperand(SmallVectorImpl &); > + ?bool ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind); > + ?const MCExpr *ApplyPrefixToExpr(const MCExpr *E, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MCSymbolRefExpr::VariantKind Variant); > + > > ? bool ParseMemoryOffsetReg(bool &Negative, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool &OffsetRegShifted, > @@ -864,9 +868,111 @@ > ? ? E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); > ? ? Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); > ? ? return false; > + ?case AsmToken::Colon: { > + ? ?// ":lower16:" and ":upper16:" expression prefixes > + ? ?MCSymbolRefExpr::VariantKind RefKind; > + ? ?if (ParsePrefix(RefKind)) > + ? ? ?return true; > + > + ? ?const MCExpr *ExprVal; > + ? ?if (getParser().ParseExpression(ExprVal)) > + ? ? ?return true; > + > + ? ?// TODO: Attach the prefix to the entire expression > + ? ?// instead of just the first symbol. > + ? ?const MCExpr *ModExprVal = ApplyPrefixToExpr(ExprVal, RefKind); > + ? ?if (!ModExprVal) { > + ? ? ?return TokError("invalid modifier '" + getTok().getIdentifier() + > + ? ? ? ? ? ? ? ? ? ? ?"' (no symbols present)"); > + ? ?} > + > + ? ?E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); > + ? ?Operands.push_back(ARMOperand::CreateImm(ModExprVal, S, E)); > + ? ?return false; > + ?} > ? } > ?} > > +// FIXME: The next 2 routines are hacks to get ARMAsmParser to understand > +// :lower16: and :upper16: > +// It still attaches VK_ARM_HI/LO16 to MCSymbolRefExpr, but it really > +// should be attached to the entire MCExpr as a whole - perhaps using > +// MCTargetExpr? > +bool ARMAsmParser::ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind) { > + ?RefKind = MCSymbolRefExpr::VK_None; > + > + ?// :lower16: and :upper16: modifiers > + ?if (getLexer().isNot(AsmToken::Colon)) { > + ? ?Error(Parser.getTok().getLoc(), "expected :"); > + ? ?return true; > + ?} > + ?Parser.Lex(); // Eat ':' > + > + ?if (getLexer().isNot(AsmToken::Identifier)) { > + ? ?Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); > + ? ?return true; > + ?} > + > + ?StringRef IDVal = Parser.getTok().getIdentifier(); > + ?if (IDVal == "lower16") { > + ? ?RefKind = MCSymbolRefExpr::VK_ARM_LO16; > + ?} else if (IDVal == "upper16") { > + ? ?RefKind = MCSymbolRefExpr::VK_ARM_HI16; > + ?} else { > + ? ?Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); > + ? ?return true; > + ?} > + ?Parser.Lex(); > + > + ?if (getLexer().isNot(AsmToken::Colon)) { > + ? ?Error(Parser.getTok().getLoc(), "unexpected token after prefix"); > + ? ?return true; > + ?} > + ?Parser.Lex(); // Eat the last ':' > + ?return false; > +} > + > +const MCExpr * > +ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MCSymbolRefExpr::VariantKind Variant) { > + ?// Recurse over the given expression, rebuilding it to apply the given variant > + ?// to the leftmost symbol. > + ?if (Variant == MCSymbolRefExpr::VK_None) > + ? ?return E; > + > + ?switch (E->getKind()) { > + ?case MCExpr::Target: > + ? ?llvm_unreachable("Can't handle target expr yet"); > + ?case MCExpr::Constant: > + ? ?llvm_unreachable("Can't handle lower16/upper16 of constant yet"); > + > + ?case MCExpr::SymbolRef: { > + ? ?const MCSymbolRefExpr *SRE = cast(E); > + > + ? ?if (SRE->getKind() != MCSymbolRefExpr::VK_None) > + ? ? ?return 0; > + > + ? ?return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); > + ?} > + > + ?case MCExpr::Unary: > + ? ?llvm_unreachable("Can't handle unary expressions yet"); > + > + ?case MCExpr::Binary: { > + ? ?const MCBinaryExpr *BE = cast(E); > + ? ?const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant); > + ? ?const MCExpr *RHS = BE->getRHS(); > + ? ?if (!LHS) > + ? ? ?return 0; > + > + ? ?return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); > + ?} > + ?} > + > + ?assert(0 && "Invalid expression kind!"); > + ?return 0; > +} > + > ?/// \brief Given a mnemonic, split out possible predication code and carry > ?/// setting letters to form a canonical mnemonic and flags. > ?// > > Added: llvm/trunk/test/MC/ARM/elf-movt.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123292&view=auto > ============================================================================== > --- llvm/trunk/test/MC/ARM/elf-movt.s (added) > +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 17:53:41 2011 > @@ -0,0 +1,14 @@ > +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s > + ? ? ? .syntax unified > + ? ? ? .text > + ? ? ? .globl ?barf > + ? ? ? .align ?2 > + ? ? ? .type ? barf,%function > +barf: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ @barf > +@ BB#0: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ %entry > + ? ? ? movw ? ?r0, :lower16:GOT-(.LPC0_2+8) > + ? ? ? movt ? ?r0, :upper16:GOT-(.LPC0_2+16) > +.LPC0_2: > +@ ASM: ? ? ? ? ?movw ? ?r0, :lower16:GOT-(.LPC0_2+8) > +@ ASM-NEXT: ? ? movt ? ?r0, :upper16:GOT-(.LPC0_2+16) > + > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From jason.w.kim.2009 at gmail.com Tue Jan 11 18:19:25 2011 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Wed, 12 Jan 2011 00:19:25 -0000 Subject: [llvm-commits] [llvm] r123294 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/elf-movt.s Message-ID: <20110112001925.8DE2B2A6C12C@llvm.org> Author: jasonwkim Date: Tue Jan 11 18:19:25 2011 New Revision: 123294 URL: http://llvm.org/viewvc/llvm-project?rev=123294&view=rev Log: 1. Support ELF pcrel relocations for movw/movt: R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC. 2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum. 3. Add support for 3 new elf section types (no-ops) Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMFixupKinds.h llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/elf-movt.s Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=123294&r1=123293&r2=123294&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Tue Jan 11 18:19:25 2011 @@ -1268,6 +1268,9 @@ case ELF::SHT_NOTE: case ELF::SHT_NULL: case ELF::SHT_ARM_ATTRIBUTES: + case ELF::SHT_INIT_ARRAY: + case ELF::SHT_FINI_ARRAY: + case ELF::SHT_PREINIT_ARRAY: // Nothing to do. break; @@ -1490,6 +1493,13 @@ default: Type = ELF::R_ARM_CALL; break; } break; + case ARM::fixup_arm_movt_hi16: + case ARM::fixup_arm_movt_hi16_pcrel: + Type = ELF::R_ARM_MOVT_PREL; break; + case ARM::fixup_arm_movw_lo16: + case ARM::fixup_arm_movw_lo16_pcrel: + Type = ELF::R_ARM_MOVW_PREL_NC; break; + } } else { switch ((unsigned)Fixup.getKind()) { Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=123294&r1=123293&r2=123294&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Tue Jan 11 18:19:25 2011 @@ -78,6 +78,8 @@ { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_movt_hi16", 0, 16, 0 }, { "fixup_arm_movw_lo16", 0, 16, 0 }, +{ "fixup_arm_movt_hi16_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_arm_movw_lo16_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, }; if (Kind < FirstTargetFixupKind) @@ -156,7 +158,9 @@ case FK_Data_4: return Value; case ARM::fixup_arm_movt_hi16: - case ARM::fixup_arm_movw_lo16: { + case ARM::fixup_arm_movw_lo16: + case ARM::fixup_arm_movt_hi16_pcrel: + case ARM::fixup_arm_movw_lo16_pcrel: { unsigned Hi4 = (Value & 0xF000) >> 12; unsigned Lo12 = Value & 0x0FFF; // inst{19-16} = Hi4; Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=123294&r1=123293&r2=123294&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Jan 11 18:19:25 2011 @@ -189,10 +189,10 @@ int64_t Imm = MO.getImm(); O << '#'; if ((Modifier && strcmp(Modifier, "lo16") == 0) || - (TF == ARMII::MO_LO16)) + (TF & ARMII::MO_LO16)) O << ":lower16:"; else if ((Modifier && strcmp(Modifier, "hi16") == 0) || - (TF == ARMII::MO_HI16)) + (TF & ARMII::MO_HI16)) O << ":upper16:"; O << Imm; break; Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=123294&r1=123293&r2=123294&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original) +++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Tue Jan 11 18:19:25 2011 @@ -74,6 +74,11 @@ fixup_arm_movt_hi16, // :upper16: fixup_arm_movw_lo16, // :lower16: + // It is possible to create an "immediate" that happens to be pcrel. + // Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC + fixup_arm_movt_hi16_pcrel, // :upper16: + fixup_arm_movw_lo16_pcrel, // :lower16: + // Marker LastTargetFixupKind, NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123294&r1=123293&r2=123294&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Jan 11 18:19:25 2011 @@ -626,6 +626,32 @@ return Binary; } +// FIXME: This routine needs to handle more MCExpr types +static const MCSymbolRefExpr *FindLHSymExpr(const MCExpr *E) { + // recurse left child until finding a MCSymbolRefExpr + switch (E->getKind()) { + case MCExpr::SymbolRef: + return cast(E); + case MCExpr::Binary: + return FindLHSymExpr(cast(E)->getLHS()); + default: + return NULL; + } +} + +// FIXME: This routine assumes that a binary +// expression will always result in a PCRel expression +// In reality, its only true if one or more subexpressions +// is itself a PCRel (i.e. "." in asm or some other pcrel construct) +// but this is good enough for now. +static bool EvaluateAsPCRel(const MCExpr *Expr) { + switch (Expr->getKind()) { + case MCExpr::SymbolRef: return false; + case MCExpr::Binary: return true; + default: assert(0 && "Unexpected expression type"); + } +} + uint32_t ARMMCCodeEmitter:: getMovtImmOpValue(const MCInst &MI, unsigned OpIdx, SmallVectorImpl &Fixups) const { @@ -635,18 +661,27 @@ if (MO.isImm()) { return static_cast(MO.getImm()); } else if (const MCSymbolRefExpr *Expr = - dyn_cast(MO.getExpr())) { + FindLHSymExpr(MO.getExpr())) { + // FIXME: :lower16: and :upper16: should be applicable to + // to whole expression, not just symbolrefs + // Until that change takes place, this hack is required to + // generate working code. + const MCExpr *OrigExpr = MO.getExpr(); MCFixupKind Kind; switch (Expr->getKind()) { default: assert(0 && "Unsupported ARMFixup"); case MCSymbolRefExpr::VK_ARM_HI16: Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); + if (EvaluateAsPCRel(OrigExpr)) + Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel); break; case MCSymbolRefExpr::VK_ARM_LO16: Kind = MCFixupKind(ARM::fixup_arm_movw_lo16); + if (EvaluateAsPCRel(OrigExpr)) + Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel); break; } - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); + Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind)); return 0; }; llvm_unreachable("Unsupported MCExpr type in MCOperand!"); Modified: llvm/trunk/test/MC/ARM/elf-movt.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123294&r1=123293&r2=123294&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/elf-movt.s (original) +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 18:19:25 2011 @@ -1,4 +1,6 @@ @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ +@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s .syntax unified .text .globl barf @@ -12,3 +14,26 @@ @ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) @ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) +@@ make sure that the text section fixups are sane too +@ OBJ: '.text' +@ OBJ-NEXT: 'sh_type', 0x00000001 +@ OBJ-NEXT: 'sh_flags', 0x00000006 +@ OBJ-NEXT: 'sh_addr', 0x00000000 +@ OBJ-NEXT: 'sh_offset', 0x00000034 +@ OBJ-NEXT: 'sh_size', 0x00000008 +@ OBJ-NEXT: 'sh_link', 0x00000000 +@ OBJ-NEXT: 'sh_info', 0x00000000 +@ OBJ-NEXT: 'sh_addralign', 0x00000004 +@ OBJ-NEXT: 'sh_entsize', 0x00000000 +@ OBJ-NEXT: '_section_data', 'f00f0fe3 ec0f4fe3' + +@ OBJ: Relocation 0x00000000 +@ OBJ-NEXT: 'r_offset', 0x00000000 +@ OBJ-NEXT: 'r_sym' +@ OBJ-NEXT: 'r_type', 0x0000002d + +@ OBJ: Relocation 0x00000001 +@ OBJ-NEXT: 'r_offset', 0x00000004 +@ OBJ-NEXT: 'r_sym' +@ OBJ-NEXT: 'r_type', 0x0000002e + From bruno.cardoso at gmail.com Tue Jan 11 18:28:12 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 11 Jan 2011 22:28:12 -0200 Subject: [llvm-commits] [PATCH] ARM bkpt instruction! In-Reply-To: References: Message-ID: Hi Anton, On Mon, Jan 10, 2011 at 5:39 PM, Anton Korobeynikov wrote: > Hi Bruno, > >> This patch fix the asm parsing for the thumb1 bkpt instruction! >> Ok to commit? > Is it possible to make patch more generic somehow, e.g. for other > non-predicable instructions (if any)? The problem here is that the cond code operand is created during ParseInstruction, while any MI info will only be available in MatchAndEmitInstruction. With MI info we would be able to do something better, for example: creating a TSFlag for Encoding16 or mark instructions with a NonPredicable bit, but that's not possible. I'm not aware of a more generic solution right now, but I'm open to ideas :) -- Bruno Cardoso Lopes http://www.brunocardoso.cc From clattner at apple.com Tue Jan 11 19:43:33 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 11 Jan 2011 17:43:33 -0800 Subject: [llvm-commits] [llvm] r123252 - in /llvm/trunk/utils/Target: ./ ARM/ ARM/analyze-match-table.py In-Reply-To: <20110111190626.89A092A6C12C@llvm.org> References: <20110111190626.89A092A6C12C@llvm.org> Message-ID: <708EBAEE-3546-49F9-AA17-049C4CBC5938@apple.com> On Jan 11, 2011, at 11:06 AM, Daniel Dunbar wrote: > Author: ddunbar > Date: Tue Jan 11 13:06:26 2011 > New Revision: 123252 > > URL: http://llvm.org/viewvc/llvm-project?rev=123252&view=rev > Log: > McARM: Write a silly Python script to compute some hard coded info from the > generated ARM match table, which is substantially more efficient than dealing > with tblgen. Is this a short term hack? This is really gross. -Chris > > Added: > llvm/trunk/utils/Target/ > llvm/trunk/utils/Target/ARM/ > llvm/trunk/utils/Target/ARM/analyze-match-table.py > > Added: llvm/trunk/utils/Target/ARM/analyze-match-table.py > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/Target/ARM/analyze-match-table.py?rev=123252&view=auto > ============================================================================== > --- llvm/trunk/utils/Target/ARM/analyze-match-table.py (added) > +++ llvm/trunk/utils/Target/ARM/analyze-match-table.py Tue Jan 11 13:06:26 2011 > @@ -0,0 +1,61 @@ > +#!/usr/bin/env python > + > +def analyze_match_table(path): > + # Extract the instruction table. > + data = open(path).read() > + start = data.index("static const MatchEntry MatchTable") > + end = data.index("\n};\n", start) > + lines = data[start:end].split("\n")[1:] > + > + # Parse the instructions. > + insns = [] > + for ln in lines: > + ln = ln.split("{", 1)[1] > + ln = ln.rsplit("}", 1)[0] > + a,bc = ln.split("{", 1) > + b,c = bc.split("}", 1) > + code, string, converter, _ = [s.strip() > + for s in a.split(",")] > + items = [s.strip() for s in b.split(",")] > + _,features = [s.strip() for s in c.split(",")] > + assert string[0] == string[-1] == '"' > + string = string[1:-1] > + insns.append((code,string,converter,items,features)) > + > + # For every mnemonic, compute whether or not it can have a carry setting > + # operand and whether or not it can have a predication code. > + mnemonic_flags = {} > + for insn in insns: > + mnemonic = insn[1] > + items = insn[3] > + flags = mnemonic_flags[mnemonic] = mnemonic_flags.get(mnemonic, set()) > + flags.update(items) > + > + mnemonics = set(mnemonic_flags) > + ccout_mnemonics = set(m for m in mnemonics > + if 'MCK_CCOut' in mnemonic_flags[m]) > + condcode_mnemonics = set(m for m in mnemonics > + if 'MCK_CondCode' in mnemonic_flags[m]) > + noncondcode_mnemonics = mnemonics - condcode_mnemonics > + print ' || '.join('Mnemonic == "%s"' % m > + for m in ccout_mnemonics) > + print ' || '.join('Mnemonic == "%s"' % m > + for m in noncondcode_mnemonics) > + > +def main(): > + import sys > + if len(sys.argv) == 1: > + import os > + from lit.Util import capture > + llvm_obj_root = capture(["llvm-config", "--obj-root"]) > + file = os.path.join(llvm_obj_root, > + "lib/Target/ARM/ARMGenAsmMatcher.inc") > + elif len(sys.argv) == 2: > + file = sys.argv[1] > + else: > + raise NotImplementedError > + > + analyze_match_table(file) > + > +if __name__ == '__main__': > + main() > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Tue Jan 11 19:44:57 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 11 Jan 2011 17:44:57 -0800 Subject: [llvm-commits] [llvm] r123286 - /llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp In-Reply-To: <20110111225438.882BC2A6C12C@llvm.org> References: <20110111225438.882BC2A6C12C@llvm.org> Message-ID: <81336F9B-351E-4835-BA1D-1FAFD5CF3BA2@apple.com> On Jan 11, 2011, at 2:54 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Tue Jan 11 16:54:38 2011 > New Revision: 123286 > > URL: http://llvm.org/viewvc/llvm-project?rev=123286&view=rev > Log: > Fix a non-deterministic loop in llvm::MergeBlockIntoPredecessor. > > DT->changeImmediateDominator() trivially ignores identity updates, so there is > really no need for the uniqueing provided by SmallPtrSet. > > I expect this to fix PR8954. My hero! -Chris From matthewbg at google.com Tue Jan 11 19:42:42 2011 From: matthewbg at google.com (Matt Beaumont-Gay) Date: Wed, 12 Jan 2011 01:42:42 -0000 Subject: [llvm-commits] [llvm] r123297 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20110112014242.E4A352A6C12C@llvm.org> Author: matthewbg Date: Tue Jan 11 19:42:42 2011 New Revision: 123297 URL: http://llvm.org/viewvc/llvm-project?rev=123297&view=rev Log: Prefer llvm_unreachable to assert(0) Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123297&r1=123296&r2=123297&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Jan 11 19:42:42 2011 @@ -129,7 +129,7 @@ SmallVectorImpl &Fixups) const { ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); switch (Mode) { - default: assert(0 && "Unknown addressing sub-mode!"); + default: llvm_unreachable("Unknown addressing sub-mode!"); case ARM_AM::da: return 0; case ARM_AM::ia: return 1; case ARM_AM::db: return 2; @@ -648,7 +648,7 @@ switch (Expr->getKind()) { case MCExpr::SymbolRef: return false; case MCExpr::Binary: return true; - default: assert(0 && "Unexpected expression type"); + default: llvm_unreachable("Unexpected expression type"); } } @@ -669,7 +669,7 @@ const MCExpr *OrigExpr = MO.getExpr(); MCFixupKind Kind; switch (Expr->getKind()) { - default: assert(0 && "Unsupported ARMFixup"); + default: llvm_unreachable("Unsupported ARMFixup"); case MCSymbolRefExpr::VK_ARM_HI16: Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); if (EvaluateAsPCRel(OrigExpr)) From sabre at nondot.org Tue Jan 11 19:43:46 2011 From: sabre at nondot.org (Chris Lattner) Date: Wed, 12 Jan 2011 01:43:46 -0000 Subject: [llvm-commits] [llvm] r123298 - /llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Message-ID: <20110112014347.0516F2A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 19:43:46 2011 New Revision: 123298 URL: http://llvm.org/viewvc/llvm-project?rev=123298&view=rev Log: revert r123149, reenabling an improvement to memcpyopt that wasn't the source of the bootstrap problem. Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=123298&r1=123297&r2=123298&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Tue Jan 11 19:43:46 2011 @@ -71,14 +71,13 @@ /// be &A[42], and Ptr2 might be &A[40]. In this case offset would be -8. static bool IsPointerOffset(Value *Ptr1, Value *Ptr2, int64_t &Offset, const TargetData &TD) { - //Ptr1 = Ptr1->stripPointerCasts(); - //Ptr2 = Ptr2->stripPointerCasts(); + Ptr1 = Ptr1->stripPointerCasts(); + Ptr2 = Ptr2->stripPointerCasts(); GetElementPtrInst *GEP1 = dyn_cast(Ptr1); GetElementPtrInst *GEP2 = dyn_cast(Ptr2); bool VariableIdxFound = false; -#if 0 // If one pointer is a GEP and the other isn't, then see if the GEP is a // constant offset from the base, as in "P" and "gep P, 1". if (GEP1 && GEP2 == 0 && GEP1->getOperand(0)->stripPointerCasts() == Ptr2) { @@ -90,7 +89,6 @@ Offset = GetOffsetFromIndex(GEP2, 1, VariableIdxFound, TD); return !VariableIdxFound; } -#endif // Right now we handle the case when Ptr1/Ptr2 are both GEPs with an identical // base. After that base, they may have some number of common (and From clattner at apple.com Tue Jan 11 19:47:49 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 11 Jan 2011 17:47:49 -0800 Subject: [llvm-commits] [llvm] r123297 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp In-Reply-To: <20110112014242.E4A352A6C12C@llvm.org> References: <20110112014242.E4A352A6C12C@llvm.org> Message-ID: <8FD2091A-A314-4786-91EC-C41603BB135B@apple.com> On Jan 11, 2011, at 5:42 PM, Matt Beaumont-Gay wrote: > Author: matthewbg > Date: Tue Jan 11 19:42:42 2011 > New Revision: 123297 > > URL: http://llvm.org/viewvc/llvm-project?rev=123297&view=rev > Log: > Prefer llvm_unreachable to assert(0) Hi Matt, Please use assert(0) unless we need the "does not fallthrough" behavior of llvm_unreachable. -Chris > > Modified: > llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123297&r1=123296&r2=123297&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Jan 11 19:42:42 2011 > @@ -129,7 +129,7 @@ > SmallVectorImpl &Fixups) const { > ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); > switch (Mode) { > - default: assert(0 && "Unknown addressing sub-mode!"); > + default: llvm_unreachable("Unknown addressing sub-mode!"); > case ARM_AM::da: return 0; > case ARM_AM::ia: return 1; > case ARM_AM::db: return 2; > @@ -648,7 +648,7 @@ > switch (Expr->getKind()) { > case MCExpr::SymbolRef: return false; > case MCExpr::Binary: return true; > - default: assert(0 && "Unexpected expression type"); > + default: llvm_unreachable("Unexpected expression type"); > } > } > > @@ -669,7 +669,7 @@ > const MCExpr *OrigExpr = MO.getExpr(); > MCFixupKind Kind; > switch (Expr->getKind()) { > - default: assert(0 && "Unsupported ARMFixup"); > + default: llvm_unreachable("Unsupported ARMFixup"); > case MCSymbolRefExpr::VK_ARM_HI16: > Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); > if (EvaluateAsPCRel(OrigExpr)) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From rafael.espindola at gmail.com Tue Jan 11 19:53:52 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 11 Jan 2011 20:53:52 -0500 Subject: [llvm-commits] [llvm] r123286 - /llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp In-Reply-To: <20110111225438.882BC2A6C12C@llvm.org> References: <20110111225438.882BC2A6C12C@llvm.org> Message-ID: <4D2D09B0.4060406@gmail.com> On 2011-01-11 17:54, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Tue Jan 11 16:54:38 2011 > New Revision: 123286 > > URL: http://llvm.org/viewvc/llvm-project?rev=123286&view=rev > Log: > Fix a non-deterministic loop in llvm::MergeBlockIntoPredecessor. > > DT->changeImmediateDominator() trivially ignores identity updates, so there is > really no need for the uniqueing provided by SmallPtrSet. > > I expect this to fix PR8954. Thanks! Cheers, Rafael From sabre at nondot.org Tue Jan 11 19:52:23 2011 From: sabre at nondot.org (Chris Lattner) Date: Wed, 12 Jan 2011 01:52:23 -0000 Subject: [llvm-commits] [llvm] r123299 - in /llvm/trunk: lib/Transforms/Scalar/MemCpyOptimizer.cpp test/Transforms/MemCpyOpt/form-memset.ll Message-ID: <20110112015223.C961F2A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 19:52:23 2011 New Revision: 123299 URL: http://llvm.org/viewvc/llvm-project?rev=123299&view=rev Log: revert r123146 which disabled code that wasn't the root cause of the bootstrap miscompare issue. Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=123299&r1=123298&r2=123299&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Tue Jan 11 19:52:23 2011 @@ -391,8 +391,6 @@ Ranges.addStore(Offset, NextStore); } else { - break; - MemSetInst *MSI = cast(BI); if (MSI->isVolatile() || ByteVal != MSI->getValue() || Modified: llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll?rev=123299&r1=123298&r2=123299&view=diff ============================================================================== --- llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll (original) +++ llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll Tue Jan 11 19:52:23 2011 @@ -173,24 +173,22 @@ %0 = bitcast i32* %add.ptr to i8* tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i32 1, i1 false) ret void - ;; DISABLED ; CHECK: @test3 -; HECK-NOT: store -; CHECK-NOT: call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 15, i32 4, i1 false) +; CHECK-NOT: store +; CHECK: call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 15, i32 4, i1 false) } ; store followed by memset, different offset scenario define void @test4(i32* nocapture %P) nounwind ssp { entry: - ;; DISABLED store i32 0, i32* %P, align 4 %add.ptr = getelementptr inbounds i32* %P, i64 1 %0 = bitcast i32* %add.ptr to i8* tail call void @llvm.memset.p0i8.i64(i8* %0, i8 0, i64 11, i32 1, i1 false) ret void ; CHECK: @test4 -; HECK-NOT: store -; CHECK-NOT: call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 15, i32 4, i1 false) +; CHECK-NOT: store +; CHECK: call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 15, i32 4, i1 false) } declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i32, i1) nounwind From nlewycky at google.com Tue Jan 11 20:13:38 2011 From: nlewycky at google.com (Nick Lewycky) Date: Tue, 11 Jan 2011 18:13:38 -0800 Subject: [llvm-commits] [llvm] r123297 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp In-Reply-To: <8FD2091A-A314-4786-91EC-C41603BB135B@apple.com> References: <20110112014242.E4A352A6C12C@llvm.org> <8FD2091A-A314-4786-91EC-C41603BB135B@apple.com> Message-ID: On 11 January 2011 17:47, Chris Lattner wrote: > > On Jan 11, 2011, at 5:42 PM, Matt Beaumont-Gay wrote: > > > Author: matthewbg > > Date: Tue Jan 11 19:42:42 2011 > > New Revision: 123297 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=123297&view=rev > > Log: > > Prefer llvm_unreachable to assert(0) > > Hi Matt, > > Please use assert(0) unless we need the "does not fallthrough" behavior of > llvm_unreachable. > The difference is that llvm_unreachable still generates code in a Release build while assert() doesn't, right? Matt made this commit because we were seeing: llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp:653: error: control reaches end of non-void function [-Wreturn-type] so it sounds like llvm_unreachable isn't the right tool, but we'd like to fix this that doesn't generate warnings in release builds. Nick > > -Chris > > > > > Modified: > > llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp > > > > Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp > > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123297&r1=123296&r2=123297&view=diff > > > ============================================================================== > > --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) > > +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Jan 11 19:42:42 > 2011 > > @@ -129,7 +129,7 @@ > > SmallVectorImpl &Fixups) const { > > ARM_AM::AMSubMode Mode = > (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); > > switch (Mode) { > > - default: assert(0 && "Unknown addressing sub-mode!"); > > + default: llvm_unreachable("Unknown addressing sub-mode!"); > > case ARM_AM::da: return 0; > > case ARM_AM::ia: return 1; > > case ARM_AM::db: return 2; > > @@ -648,7 +648,7 @@ > > switch (Expr->getKind()) { > > case MCExpr::SymbolRef: return false; > > case MCExpr::Binary: return true; > > - default: assert(0 && "Unexpected expression type"); > > + default: llvm_unreachable("Unexpected expression type"); > > } > > } > > > > @@ -669,7 +669,7 @@ > > const MCExpr *OrigExpr = MO.getExpr(); > > MCFixupKind Kind; > > switch (Expr->getKind()) { > > - default: assert(0 && "Unsupported ARMFixup"); > > + default: llvm_unreachable("Unsupported ARMFixup"); > > case MCSymbolRefExpr::VK_ARM_HI16: > > Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); > > if (EvaluateAsPCRel(OrigExpr)) > > > > > > _______________________________________________ > > llvm-commits mailing list > > llvm-commits at cs.uiuc.edu > > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110111/005c5160/attachment.html From venkatra at cs.wisc.edu Tue Jan 11 21:18:22 2011 From: venkatra at cs.wisc.edu (Venkatraman Govindaraju) Date: Wed, 12 Jan 2011 03:18:22 -0000 Subject: [llvm-commits] [llvm] r123301 - in /llvm/trunk: lib/Target/Sparc/SparcISelLowering.cpp lib/Target/Sparc/SparcInstrInfo.td test/CodeGen/SPARC/2011-01-11-Call.ll Message-ID: <20110112031822.219EA2A6C12C@llvm.org> Author: venkatra Date: Tue Jan 11 21:18:21 2011 New Revision: 123301 URL: http://llvm.org/viewvc/llvm-project?rev=123301&view=rev Log: Fix SPARC backend call instruction so that arguments passed through registers are correctly marked as used instead of passing all possible argument registers as used. Added: llvm/trunk/test/CodeGen/SPARC/2011-01-11-Call.ll Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=123301&r1=123300&r2=123301&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Tue Jan 11 21:18:21 2011 @@ -1,3 +1,4 @@ + //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// // // The LLVM Compiler Infrastructure @@ -514,11 +515,22 @@ else if (ExternalSymbolSDNode *E = dyn_cast(Callee)) Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); - std::vector NodeTys; - NodeTys.push_back(MVT::Other); // Returns a chain - NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use. - SDValue Ops[] = { Chain, Callee, InFlag }; - Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, Ops, InFlag.getNode() ? 3 : 2); + // Returns a chain & a flag for retval copy to use + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + SmallVector Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { + unsigned Reg = RegsToPass[i].first; + if (Reg >= SP::I0 && Reg <= SP::I7) + Reg = Reg-SP::I0+SP::O0; + + Ops.push_back(DAG.getRegister(Reg, RegsToPass[i].second.getValueType())); + } + if (InFlag.getNode()) + Ops.push_back(InFlag); + + Chain = DAG.getNode(SPISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); InFlag = Chain.getValue(1); Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(ArgsSize, true), Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=123301&r1=123300&r2=123301&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Tue Jan 11 21:18:21 2011 @@ -119,9 +119,10 @@ def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; -def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; +def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; def call : SDNode<"SPISD::CALL", SDT_SPCall, - [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; + [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, + SDNPVariadic]>; def retflag : SDNode<"SPISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; @@ -517,11 +518,11 @@ // Section B.24 - Call and Link Instruction, p. 125 // This is the only Format 1 instruction -let Uses = [O0, O1, O2, O3, O4, O5], +let Uses = [O6], hasDelaySlot = 1, isCall = 1, Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in { - def CALL : InstSP<(outs), (ins calltarget:$dst), + def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops), "call $dst", []> { bits<30> disp; let op = 1; @@ -530,11 +531,11 @@ // indirect calls def JMPLrr : F3_1<2, 0b111000, - (outs), (ins MEMrr:$ptr), + (outs), (ins MEMrr:$ptr, variable_ops), "call $ptr", [(call ADDRrr:$ptr)]>; def JMPLri : F3_2<2, 0b111000, - (outs), (ins MEMri:$ptr), + (outs), (ins MEMri:$ptr, variable_ops), "call $ptr", [(call ADDRri:$ptr)]>; } Added: llvm/trunk/test/CodeGen/SPARC/2011-01-11-Call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-11-Call.ll?rev=123301&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/SPARC/2011-01-11-Call.ll (added) +++ llvm/trunk/test/CodeGen/SPARC/2011-01-11-Call.ll Tue Jan 11 21:18:21 2011 @@ -0,0 +1,13 @@ +; RUN: llc -march=sparc -O0 <%s + +define void @test() nounwind { +entry: + %0 = tail call i32 (...)* @foo() nounwind + tail call void (...)* @bar() nounwind + ret void +} + +declare i32 @foo(...) + +declare void @bar(...) + From sabre at nondot.org Tue Jan 11 21:25:15 2011 From: sabre at nondot.org (Chris Lattner) Date: Wed, 12 Jan 2011 03:25:15 -0000 Subject: [llvm-commits] [llvm] r123302 - in /llvm/trunk: lib/Transforms/Scalar/MemCpyOptimizer.cpp test/Transforms/MemCpyOpt/form-memset.ll Message-ID: <20110112032515.52B342A6C12C@llvm.org> Author: lattner Date: Tue Jan 11 21:25:15 2011 New Revision: 123302 URL: http://llvm.org/viewvc/llvm-project?rev=123302&view=rev Log: revert 123144, reenabling the rest of memset formation. Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=123302&r1=123301&r2=123302&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Tue Jan 11 21:25:15 2011 @@ -517,9 +517,6 @@ } bool MemCpyOpt::processMemSet(MemSetInst *MSI, BasicBlock::iterator &BBI) { - // Temporarily disable this. - return false; - // See if there is another memset or store neighboring this memset which // allows us to widen out the memset to do a single larger store. if (isa(MSI->getLength()) && !MSI->isVolatile()) Modified: llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll?rev=123302&r1=123301&r2=123302&view=diff ============================================================================== --- llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll (original) +++ llvm/trunk/test/Transforms/MemCpyOpt/form-memset.ll Tue Jan 11 21:25:15 2011 @@ -202,10 +202,9 @@ %arrayidx = getelementptr inbounds i32* %P, i64 1 store i32 0, i32* %arrayidx, align 4 ret void - ; FIXME: Disabled. ; CHECK: @test5 -; CHECK: store -; CHECK-NOT: call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 15, i32 4, i1 false) +; CHECK-NOT: store +; CHECK: call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 15, i32 4, i1 false) } ;; Memset followed by memset. @@ -218,6 +217,6 @@ tail call void @llvm.memset.p0i8.i64(i8* %1, i8 0, i64 12, i32 1, i1 false) ret void ; CHECK: @test6 -; CHECK-NOT: call void @llvm.memset.p0i8.i64(i8* %2, i8 0, i64 24, i32 1, i1 false) +; CHECK: call void @llvm.memset.p0i8.i64(i8* %2, i8 0, i64 24, i32 1, i1 false) } From venkatra at cs.wisc.edu Tue Jan 11 21:52:59 2011 From: venkatra at cs.wisc.edu (Venkatraman Govindaraju) Date: Wed, 12 Jan 2011 03:52:59 -0000 Subject: [llvm-commits] [llvm] r123304 - in /llvm/trunk/lib/Target/Sparc: SparcAsmPrinter.cpp SparcInstrInfo.td Message-ID: <20110112035259.67A992A6C12C@llvm.org> Author: venkatra Date: Tue Jan 11 21:52:59 2011 New Revision: 123304 URL: http://llvm.org/viewvc/llvm-project?rev=123304&view=rev Log: Remove SPARC backend getpcx instruction's Uses. Also, insert an assert to ensure %o7 is not assigned as the destination of getpcx instruction. Modified: llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Modified: llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp?rev=123304&r1=123303&r2=123304&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcAsmPrinter.cpp Tue Jan 11 21:52:59 2011 @@ -145,6 +145,8 @@ case MachineOperand::MO_Register: assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) && "Operand is not a physical register "); + assert(MO.getReg() != SP::O7 && + "%o7 is assigned as destination for getpcx!"); operand = "%" + LowercaseString(getRegisterName(MO.getReg())); break; } @@ -156,8 +158,8 @@ O << "\tcall\t.LLGETPC" << mfNum << '_' << bbNum << '\n' ; O << "\t sethi\t" - << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum << ")), " - << operand << '\n' ; + << "%hi(_GLOBAL_OFFSET_TABLE_+(.-.LLGETPCH" << mfNum << '_' << bbNum + << ")), " << operand << '\n' ; O << ".LLGETPC" << mfNum << '_' << bbNum << ":\n" ; O << "\tor\t" << operand Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=123304&r1=123303&r2=123304&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Tue Jan 11 21:52:59 2011 @@ -205,7 +205,7 @@ : InstSP; // GETPCX for PIC -let Defs = [O7], Uses = [O7] in { +let Defs = [O7] in { def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >; } From venkatra at cs.wisc.edu Tue Jan 11 23:08:36 2011 From: venkatra at cs.wisc.edu (Venkatraman Govindaraju) Date: Wed, 12 Jan 2011 05:08:36 -0000 Subject: [llvm-commits] [llvm] r123310 - in /llvm/trunk: lib/Target/Sparc/SparcISelLowering.cpp lib/Target/Sparc/SparcISelLowering.h lib/Target/Sparc/SparcInstrInfo.td test/CodeGen/SPARC/2011-01-11-FrameAddr.ll Message-ID: <20110112050836.4F9A32A6C12C@llvm.org> Author: venkatra Date: Tue Jan 11 23:08:36 2011 New Revision: 123310 URL: http://llvm.org/viewvc/llvm-project?rev=123310&view=rev Log: Implement RETURNADDR and FRAMEADDR lowering in SPARC backend. Added: llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.h llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=123310&r1=123309&r2=123310&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Tue Jan 11 23:08:36 2011 @@ -743,6 +743,8 @@ case SPISD::ITOF: return "SPISD::ITOF"; case SPISD::CALL: return "SPISD::CALL"; case SPISD::RET_FLAG: return "SPISD::RET_FLAG"; + case SPISD::GLOBAL_BASE_REG: return "SPISD::GLOBAL_BASE_REG"; + case SPISD::FLUSH: return "SPISD::FLUSH"; } } @@ -990,13 +992,82 @@ } +static SDValue getFLUSH(SDValue Op, SelectionDAG &DAG) { + DebugLoc dl = Op.getDebugLoc(); + SDValue Chain = DAG.getNode(SPISD::FLUSH, + dl, MVT::Other, DAG.getEntryNode()); + return Chain; +} + +static SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) { + MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); + MFI->setFrameAddressIsTaken(true); + + EVT VT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); + unsigned FrameReg = SP::I6; + + uint64_t depth = Op.getConstantOperandVal(0); + + SDValue FrameAddr; + if (depth == 0) + FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); + else { + // flush first to make sure the windowed registers' values are in stack + SDValue Chain = getFLUSH(Op, DAG); + FrameAddr = DAG.getCopyFromReg(Chain, dl, FrameReg, VT); + + for (uint64_t i = 0; i != depth; ++i) { + SDValue Ptr = DAG.getNode(ISD::ADD, + dl, MVT::i32, + FrameAddr, DAG.getIntPtrConstant(56)); + FrameAddr = DAG.getLoad(MVT::i32, dl, + Chain, + Ptr, + MachinePointerInfo(), false, false, 0); + } + } + return FrameAddr; +} + +static SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) { + MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); + MFI->setReturnAddressIsTaken(true); + + EVT VT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); + unsigned RetReg = SP::I7; + + uint64_t depth = Op.getConstantOperandVal(0); + + SDValue RetAddr; + if (depth == 0) + RetAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, RetReg, VT); + else { + // flush first to make sure the windowed registers' values are in stack + SDValue Chain = getFLUSH(Op, DAG); + RetAddr = DAG.getCopyFromReg(Chain, dl, SP::I6, VT); + + for (uint64_t i = 0; i != depth; ++i) { + SDValue Ptr = DAG.getNode(ISD::ADD, + dl, MVT::i32, + RetAddr, + DAG.getIntPtrConstant((i == depth-1)?60:56)); + RetAddr = DAG.getLoad(MVT::i32, dl, + Chain, + Ptr, + MachinePointerInfo(), false, false, 0); + } + } + return RetAddr; +} + SDValue SparcTargetLowering:: LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { default: llvm_unreachable("Should not custom lower this!"); - // Frame & Return address. Currently unimplemented - case ISD::RETURNADDR: return SDValue(); - case ISD::FRAMEADDR: return SDValue(); + case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); + case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for Sparc."); case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.h?rev=123310&r1=123309&r2=123310&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.h Tue Jan 11 23:08:36 2011 @@ -36,7 +36,8 @@ CALL, // A call instruction. RET_FLAG, // Return with a flag operand. - GLOBAL_BASE_REG // Global base reg for PIC + GLOBAL_BASE_REG, // Global base reg for PIC + FLUSH // FLUSH registers to stack }; } Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td?rev=123310&r1=123309&r2=123310&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.td Tue Jan 11 23:08:36 2011 @@ -127,6 +127,9 @@ def retflag : SDNode<"SPISD::RET_FLAG", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; +def flush : SDNode<"SPISD::FLUSH", SDTNone, + [SDNPHasChain]>; + def getPCX : Operand { let PrintMethod = "printGetPCX"; } @@ -218,6 +221,12 @@ [(callseq_end timm:$amt1, timm:$amt2)]>; } +let hasSideEffects = 1, mayStore = 1 in + let rs2 = 0 in + def FLUSH : F3_1<0b10, 0b101011, (outs), (ins), + "flushw", + [(flush)]>; + // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the // fpmover pass. let Predicates = [HasNoV9] in { // Only emit these in V8 mode. Added: llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll?rev=123310&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll (added) +++ llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll Tue Jan 11 23:08:36 2011 @@ -0,0 +1,46 @@ +;RUN: llc -march=sparc < %s | FileCheck %s + + +define i8* @frameaddr() nounwind readnone { +entry: +;CHECK: frameaddr +;CHECK: or %g0, %fp, {{.+}} + %0 = tail call i8* @llvm.frameaddress(i32 0) + ret i8* %0 +} + +define i8* @frameaddr2() nounwind readnone { +entry: +;CHECK: frameaddr2 +;CHECK: flushw +;CHECK: ld [%fp+56], {{.+}} +;CHECK: ld [{{.+}}+56], {{.+}} +;CHECK: ld [{{.+}}+56], {{.+}} + %0 = tail call i8* @llvm.frameaddress(i32 3) + ret i8* %0 +} + +declare i8* @llvm.frameaddress(i32) nounwind readnone + + + +define i8* @retaddr() nounwind readnone { +entry: +;CHECK: retaddr +;CHECK: or %g0, %i7, {{.+}} + %0 = tail call i8* @llvm.returnaddress(i32 0) + ret i8* %0 +} + +define i8* @retaddr2() nounwind readnone { +entry: +;CHECK: retaddr2 +;CHECK: flushw +;CHECK: ld [%fp+56], {{.+}} +;CHECK: ld [{{.+}}+56], {{.+}} +;CHECK: ld [{{.+}}+60], {{.+}} + %0 = tail call i8* @llvm.returnaddress(i32 3) + ret i8* %0 +} + +declare i8* @llvm.returnaddress(i32) nounwind readnone From bruno.cardoso at gmail.com Tue Jan 11 23:34:35 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Wed, 12 Jan 2011 03:34:35 -0200 Subject: [llvm-commits] [PATCH] arm BFI instruction! Message-ID: The ARM GNU as only supports a 4 parameter version of the bfi instruction: bfi r0, r0, #5, #7 This patch adds the parsing/encoding support for it. -- Bruno Cardoso Lopes http://www.brunocardoso.cc -------------- next part -------------- A non-text attachment was scrubbed... Name: arm-bfi.patch Type: application/octet-stream Size: 7453 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110112/b0a4eecd/attachment.obj From aggarwa4 at illinois.edu Tue Jan 11 23:45:52 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 12 Jan 2011 05:45:52 -0000 Subject: [llvm-commits] [poolalloc] r123311 - in /poolalloc/trunk/lib: DSA/StdLibPass.cpp PoolAllocate/AllNodesHeuristic.cpp Message-ID: <20110112054552.6A1752A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jan 11 23:45:52 2011 New Revision: 123311 URL: http://llvm.org/viewvc/llvm-project?rev=123311&view=rev Log: Formatting changes. Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp poolalloc/trunk/lib/PoolAllocate/AllNodesHeuristic.cpp Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=123311&r1=123310&r2=123311&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Tue Jan 11 23:45:52 2011 @@ -105,7 +105,7 @@ {"valloc", {NRET_NARGS, YRET_NARGS, YRET_NARGS, false, false, false}}, {"memalign", {NRET_NARGS, YRET_NARGS, YRET_NARGS, false, false, false}}, {"realloc", {NRET_NARGS, YRET_NARGS, YRET_YNARGS, false, true, true}}, - {"free", {NRET_NARGS, NRET_NARGS, NRET_YNARGS, false, false, false}}, + {"free", {NRET_NARGS, NRET_NARGS, NRET_YNARGS, false, false, false}}, {"strdup", {NRET_YARGS, YRET_NARGS, YRET_NARGS, false, true, false}}, {"wcsdup", {NRET_YARGS, YRET_NARGS, YRET_NARGS, false, true, false}}, Modified: poolalloc/trunk/lib/PoolAllocate/AllNodesHeuristic.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/AllNodesHeuristic.cpp?rev=123311&r1=123310&r2=123311&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/AllNodesHeuristic.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/AllNodesHeuristic.cpp Tue Jan 11 23:45:52 2011 @@ -72,6 +72,7 @@ // // Remove those global nodes which we know will never be pool allocated. // + /*std::vector toRemove; for (DenseSet::iterator I = NodesFromGlobals.begin(), E = NodesFromGlobals.end(); I != E; ) { @@ -167,23 +168,23 @@ DSGraph* G = Graphs->getDSGraph(*F); DSGraph::NodeMapTy NodeMap; G->computeGToGGMapping (NodeMap); - // - // Scan through all DSNodes in the local graph. If a local DSNode has a - // corresponding DSNode in the globals graph that is reachable from a - // global, then add the local DSNode to the set of DSNodes reachable from - // a global. - // - DSGraph::node_iterator ni = G->node_begin(); - for (; ni != G->node_end(); ++ni) { - DSNode * N = ni; - DSNode * GGN = NodeMap[N].getNode(); - - //assert (!GGN || GlobalHeapNodes.count (GGN)); - if (GGN && GlobalHeapNodes.count (GGN)) - PoolMap[GGN].NodesInPool.push_back (N); - } - - + // + // Scan through all DSNodes in the local graph. If a local DSNode has a + // corresponding DSNode in the globals graph that is reachable from a + // global, then add the local DSNode to the set of DSNodes reachable from + // a global. + // + DSGraph::node_iterator ni = G->node_begin(); + for (; ni != G->node_end(); ++ni) { + DSNode * N = ni; + DSNode * GGN = NodeMap[N].getNode(); + + //assert (!GGN || GlobalHeapNodes.count (GGN)); + if (GGN && GlobalHeapNodes.count (GGN)) + PoolMap[GGN].NodesInPool.push_back (N); + } + + } } From evan.cheng at apple.com Wed Jan 12 00:29:34 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Jan 2011 22:29:34 -0800 Subject: [llvm-commits] [llvm] r123292 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/elf-movt.s In-Reply-To: <20110111235341.A4A2E2A6C12C@llvm.org> References: <20110111235341.A4A2E2A6C12C@llvm.org> Message-ID: <046003E3-325D-40EF-BDE1-DB37795BAFEB@apple.com> On Jan 11, 2011, at 3:53 PM, Jason W Kim wrote: > Author: jasonwkim > Date: Tue Jan 11 17:53:41 2011 > New Revision: 123292 > > URL: http://llvm.org/viewvc/llvm-project?rev=123292&view=rev > Log: > Workaround for bug 8721. > .s Test added. > > > Added: > llvm/trunk/test/MC/ARM/elf-movt.s > Modified: > llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > > Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123292&r1=123291&r2=123292&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jan 11 17:53:41 2011 > @@ -55,6 +55,10 @@ > bool ParseRegisterList(SmallVectorImpl &); > bool ParseMemory(SmallVectorImpl &); > bool ParseOperand(SmallVectorImpl &); > + bool ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind); > + const MCExpr *ApplyPrefixToExpr(const MCExpr *E, > + MCSymbolRefExpr::VariantKind Variant); > + > > bool ParseMemoryOffsetReg(bool &Negative, > bool &OffsetRegShifted, > @@ -864,9 +868,111 @@ > E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); > Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); > return false; > + case AsmToken::Colon: { > + // ":lower16:" and ":upper16:" expression prefixes > + MCSymbolRefExpr::VariantKind RefKind; > + if (ParsePrefix(RefKind)) > + return true; > + > + const MCExpr *ExprVal; > + if (getParser().ParseExpression(ExprVal)) > + return true; > + > + // TODO: Attach the prefix to the entire expression > + // instead of just the first symbol. I plan to fix this in the next couple of days. Evan > + const MCExpr *ModExprVal = ApplyPrefixToExpr(ExprVal, RefKind); > + if (!ModExprVal) { > + return TokError("invalid modifier '" + getTok().getIdentifier() + > + "' (no symbols present)"); > + } > + > + E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); > + Operands.push_back(ARMOperand::CreateImm(ModExprVal, S, E)); > + return false; > + } > } > } > > +// FIXME: The next 2 routines are hacks to get ARMAsmParser to understand > +// :lower16: and :upper16: > +// It still attaches VK_ARM_HI/LO16 to MCSymbolRefExpr, but it really > +// should be attached to the entire MCExpr as a whole - perhaps using > +// MCTargetExpr? > +bool ARMAsmParser::ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind) { > + RefKind = MCSymbolRefExpr::VK_None; > + > + // :lower16: and :upper16: modifiers > + if (getLexer().isNot(AsmToken::Colon)) { > + Error(Parser.getTok().getLoc(), "expected :"); > + return true; > + } > + Parser.Lex(); // Eat ':' > + > + if (getLexer().isNot(AsmToken::Identifier)) { > + Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); > + return true; > + } > + > + StringRef IDVal = Parser.getTok().getIdentifier(); > + if (IDVal == "lower16") { > + RefKind = MCSymbolRefExpr::VK_ARM_LO16; > + } else if (IDVal == "upper16") { > + RefKind = MCSymbolRefExpr::VK_ARM_HI16; > + } else { > + Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); > + return true; > + } > + Parser.Lex(); > + > + if (getLexer().isNot(AsmToken::Colon)) { > + Error(Parser.getTok().getLoc(), "unexpected token after prefix"); > + return true; > + } > + Parser.Lex(); // Eat the last ':' > + return false; > +} > + > +const MCExpr * > +ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E, > + MCSymbolRefExpr::VariantKind Variant) { > + // Recurse over the given expression, rebuilding it to apply the given variant > + // to the leftmost symbol. > + if (Variant == MCSymbolRefExpr::VK_None) > + return E; > + > + switch (E->getKind()) { > + case MCExpr::Target: > + llvm_unreachable("Can't handle target expr yet"); > + case MCExpr::Constant: > + llvm_unreachable("Can't handle lower16/upper16 of constant yet"); > + > + case MCExpr::SymbolRef: { > + const MCSymbolRefExpr *SRE = cast(E); > + > + if (SRE->getKind() != MCSymbolRefExpr::VK_None) > + return 0; > + > + return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); > + } > + > + case MCExpr::Unary: > + llvm_unreachable("Can't handle unary expressions yet"); > + > + case MCExpr::Binary: { > + const MCBinaryExpr *BE = cast(E); > + const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant); > + const MCExpr *RHS = BE->getRHS(); > + if (!LHS) > + return 0; > + > + return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); > + } > + } > + > + assert(0 && "Invalid expression kind!"); > + return 0; > +} > + > /// \brief Given a mnemonic, split out possible predication code and carry > /// setting letters to form a canonical mnemonic and flags. > // > > Added: llvm/trunk/test/MC/ARM/elf-movt.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123292&view=auto > ============================================================================== > --- llvm/trunk/test/MC/ARM/elf-movt.s (added) > +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 17:53:41 2011 > @@ -0,0 +1,14 @@ > +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s > + .syntax unified > + .text > + .globl barf > + .align 2 > + .type barf,%function > +barf: @ @barf > +@ BB#0: @ %entry > + movw r0, :lower16:GOT-(.LPC0_2+8) > + movt r0, :upper16:GOT-(.LPC0_2+16) > +.LPC0_2: > +@ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) > +@ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) > + > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Wed Jan 12 00:44:23 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 11 Jan 2011 22:44:23 -0800 Subject: [llvm-commits] [llvm] r123292 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/elf-movt.s In-Reply-To: <20110111235341.A4A2E2A6C12C@llvm.org> References: <20110111235341.A4A2E2A6C12C@llvm.org> Message-ID: <8B43FD90-C019-4EEB-BD7D-6AF9BA973EBC@apple.com> On Jan 11, 2011, at 3:53 PM, Jason W Kim wrote: > Author: jasonwkim > Date: Tue Jan 11 17:53:41 2011 > New Revision: 123292 > > URL: http://llvm.org/viewvc/llvm-project?rev=123292&view=rev > Log: > Workaround for bug 8721. > .s Test added. > > > Added: > llvm/trunk/test/MC/ARM/elf-movt.s > Modified: > llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > > Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123292&r1=123291&r2=123292&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jan 11 17:53:41 2011 > @@ -55,6 +55,10 @@ > bool ParseRegisterList(SmallVectorImpl &); > bool ParseMemory(SmallVectorImpl &); > bool ParseOperand(SmallVectorImpl &); > + bool ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind); > + const MCExpr *ApplyPrefixToExpr(const MCExpr *E, > + MCSymbolRefExpr::VariantKind Variant); > + > > bool ParseMemoryOffsetReg(bool &Negative, > bool &OffsetRegShifted, > @@ -864,9 +868,111 @@ > E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); > Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); > return false; > + case AsmToken::Colon: { > + // ":lower16:" and ":upper16:" expression prefixes > + MCSymbolRefExpr::VariantKind RefKind; > + if (ParsePrefix(RefKind)) > + return true; > + > + const MCExpr *ExprVal; > + if (getParser().ParseExpression(ExprVal)) > + return true; > + > + // TODO: Attach the prefix to the entire expression > + // instead of just the first symbol. > + const MCExpr *ModExprVal = ApplyPrefixToExpr(ExprVal, RefKind); > + if (!ModExprVal) { > + return TokError("invalid modifier '" + getTok().getIdentifier() + > + "' (no symbols present)"); > + } > + > + E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); > + Operands.push_back(ARMOperand::CreateImm(ModExprVal, S, E)); > + return false; > + } > } > } > > +// FIXME: The next 2 routines are hacks to get ARMAsmParser to understand > +// :lower16: and :upper16: > +// It still attaches VK_ARM_HI/LO16 to MCSymbolRefExpr, but it really > +// should be attached to the entire MCExpr as a whole - perhaps using > +// MCTargetExpr? > +bool ARMAsmParser::ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind) { > + RefKind = MCSymbolRefExpr::VK_None; > + > + // :lower16: and :upper16: modifiers > + if (getLexer().isNot(AsmToken::Colon)) { > + Error(Parser.getTok().getLoc(), "expected :"); > + return true; > + } > + Parser.Lex(); // Eat ':' > + > + if (getLexer().isNot(AsmToken::Identifier)) { > + Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); > + return true; > + } > + > + StringRef IDVal = Parser.getTok().getIdentifier(); > + if (IDVal == "lower16") { > + RefKind = MCSymbolRefExpr::VK_ARM_LO16; > + } else if (IDVal == "upper16") { > + RefKind = MCSymbolRefExpr::VK_ARM_HI16; > + } else { > + Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); > + return true; > + } > + Parser.Lex(); > + > + if (getLexer().isNot(AsmToken::Colon)) { > + Error(Parser.getTok().getLoc(), "unexpected token after prefix"); > + return true; > + } > + Parser.Lex(); // Eat the last ':' > + return false; > +} > + > +const MCExpr * > +ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E, > + MCSymbolRefExpr::VariantKind Variant) { > + // Recurse over the given expression, rebuilding it to apply the given variant > + // to the leftmost symbol. > + if (Variant == MCSymbolRefExpr::VK_None) > + return E; > + > + switch (E->getKind()) { > + case MCExpr::Target: > + llvm_unreachable("Can't handle target expr yet"); > + case MCExpr::Constant: > + llvm_unreachable("Can't handle lower16/upper16 of constant yet"); > + > + case MCExpr::SymbolRef: { > + const MCSymbolRefExpr *SRE = cast(E); > + > + if (SRE->getKind() != MCSymbolRefExpr::VK_None) > + return 0; > + > + return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); > + } > + > + case MCExpr::Unary: > + llvm_unreachable("Can't handle unary expressions yet"); > + > + case MCExpr::Binary: { > + const MCBinaryExpr *BE = cast(E); > + const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant); > + const MCExpr *RHS = BE->getRHS(); > + if (!LHS) > + return 0; > + > + return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); > + } > + } > + > + assert(0 && "Invalid expression kind!"); > + return 0; > +} > + > /// \brief Given a mnemonic, split out possible predication code and carry > /// setting letters to form a canonical mnemonic and flags. > // > > Added: llvm/trunk/test/MC/ARM/elf-movt.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123292&view=auto > ============================================================================== > --- llvm/trunk/test/MC/ARM/elf-movt.s (added) > +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 17:53:41 2011 > @@ -0,0 +1,14 @@ > +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s > + .syntax unified > + .text > + .globl barf > + .align 2 > + .type barf,%function > +barf: @ @barf > +@ BB#0: @ %entry > + movw r0, :lower16:GOT-(.LPC0_2+8) Should it be movw r0, :lower16:(GOT-(.LC0_2+8)) instead? > + movt r0, :upper16:GOT-(.LPC0_2+16) Why is it +16, not +8? Evan > +.LPC0_2: > +@ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) > +@ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) > + > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Wed Jan 12 01:42:11 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 11 Jan 2011 23:42:11 -0800 Subject: [llvm-commits] [llvm] r123297 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp In-Reply-To: References: <20110112014242.E4A352A6C12C@llvm.org> <8FD2091A-A314-4786-91EC-C41603BB135B@apple.com> Message-ID: On Jan 11, 2011, at 6:13 PM, Nick Lewycky wrote: > On 11 January 2011 17:47, Chris Lattner wrote: > > On Jan 11, 2011, at 5:42 PM, Matt Beaumont-Gay wrote: > > > Author: matthewbg > > Date: Tue Jan 11 19:42:42 2011 > > New Revision: 123297 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=123297&view=rev > > Log: > > Prefer llvm_unreachable to assert(0) > > Hi Matt, > > Please use assert(0) unless we need the "does not fallthrough" behavior of llvm_unreachable. > > The difference is that llvm_unreachable still generates code in a Release build while assert() doesn't, right? > > Matt made this commit because we were seeing: > > llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp:653: error: control reaches end of non-void function [-Wreturn-type] > > so it sounds like llvm_unreachable isn't the right tool, but we'd like to fix this that doesn't generate warnings in release builds. Please move the default case to the first part of the switch statement: switch (whatever) { default: assert(0 && ... case 0: that way, in non-assert builds, the compiler still thinks everything is great. -Chris -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110111/b647d62d/attachment.html From nicholas at mxc.ca Wed Jan 12 03:06:19 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 12 Jan 2011 09:06:19 -0000 Subject: [llvm-commits] [llvm] r123315 - /llvm/trunk/lib/Target/ARM/README-Thumb.txt Message-ID: <20110112090619.AB9822A6C12D@llvm.org> Author: nicholas Date: Wed Jan 12 03:06:19 2011 New Revision: 123315 URL: http://llvm.org/viewvc/llvm-project?rev=123315&view=rev Log: Add another note taken from the gcc bugzilla. Modified: llvm/trunk/lib/Target/ARM/README-Thumb.txt Modified: llvm/trunk/lib/Target/ARM/README-Thumb.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/README-Thumb.txt?rev=123315&r1=123314&r2=123315&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/README-Thumb.txt (original) +++ llvm/trunk/lib/Target/ARM/README-Thumb.txt Wed Jan 12 03:06:19 2011 @@ -68,7 +68,7 @@ //===---------------------------------------------------------------------===// -We compiles the following: +We compile the following: define i16 @func_entry_2E_ce(i32 %i) { switch i32 %i, label %bb12.exitStub [ @@ -246,3 +246,22 @@ Rather than having tBR_JTr print a ".align 2" and constant island pass pad it, add a target specific ALIGN instruction instead. That way, GetInstSizeInBytes won't have to over-estimate. It can also be used for loop alignment pass. + +//===---------------------------------------------------------------------===// + +We generate conditional code for icmp when we don't need to. This code: + + int foo(int s) { + return s == 1; + } + +produces: + +foo: + cmp r0, #1 + mov.w r0, #0 + it eq + moveq r0, #1 + bx lr + +when it could use subs + adcs. This is GCC PR46975. From Renato.Golin at arm.com Wed Jan 12 03:19:18 2011 From: Renato.Golin at arm.com (Renato Golin) Date: Wed, 12 Jan 2011 09:19:18 +0000 Subject: [llvm-commits] [llvm] r123252 - in /llvm/trunk/utils/Target: ./ ARM/ ARM/analyze-match-table.py In-Reply-To: <708EBAEE-3546-49F9-AA17-049C4CBC5938@apple.com> References: <20110111190626.89A092A6C12C@llvm.org> <708EBAEE-3546-49F9-AA17-049C4CBC5938@apple.com> Message-ID: <4D2D7216.1050605@arm.com> On 01/12/11 01:43, Chris Lattner wrote: >> McARM: Write a silly Python script to compute some hard coded info from the >> generated ARM match table, which is substantially more efficient than dealing >> with tblgen. > > Is this a short term hack? This is really gross. I agree. It's not clear what the script does, how it is used, if it is intended to replace tablegen magic just because it's faster/easier or because it has features tablegen don't, or because it's faster to develop in python than tablegen, how long will this script be in use and what are the steps to replace it one day, if any. Not to mention that it creates a precedence for further hacks, which might not be temporary themselves... ;) cheers, --renato -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. From nicholas at mxc.ca Wed Jan 12 03:22:24 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 12 Jan 2011 01:22:24 -0800 Subject: [llvm-commits] [llvm] r123203 - in /llvm/trunk: lib/Target/README.txt lib/Transforms/InstCombine/InstCombineCompares.cpp test/Transforms/InstCombine/icmp.ll In-Reply-To: <20110111003645.CBDD12A6C12D@llvm.org> References: <20110111003645.CBDD12A6C12D@llvm.org> Message-ID: <4D2D72D0.1020604@mxc.ca> Owen Anderson wrote: > Author: resistor > Date: Mon Jan 10 18:36:45 2011 > New Revision: 123203 > > URL: http://llvm.org/viewvc/llvm-project?rev=123203&view=rev > Log: > Fix a random missed optimization by making InstCombine more aggressive when determining which bits are demanded by > a comparison against a constant. > > Modified: > llvm/trunk/lib/Target/README.txt > llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp > llvm/trunk/test/Transforms/InstCombine/icmp.ll > > Modified: llvm/trunk/lib/Target/README.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=123203&r1=123202&r2=123203&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/README.txt (original) > +++ llvm/trunk/lib/Target/README.txt Mon Jan 10 18:36:45 2011 > @@ -1627,21 +1627,6 @@ > > //===---------------------------------------------------------------------===// > > -InstCombine should use SimplifyDemandedBits to remove the or instruction: > - > -define i1 @test(i8 %x, i8 %y) { > - %A = or i8 %x, 1 > - %B = icmp ugt i8 %A, 3 > - ret i1 %B > -} > - > -Currently instcombine calls SimplifyDemandedBits with either all bits or just > -the sign bit, if the comparison is obviously a sign test. In this case, we only > -need all but the bottom two bits from %A, and if we gave that mask to SDB it > -would delete the or instruction for us. > - > -//===---------------------------------------------------------------------===// > - > functionattrs doesn't know much about memcpy/memset. This function should be > marked readnone rather than readonly, since it only twiddles local memory, but > functionattrs doesn't handle memset/memcpy/memmove aggressively: > > Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=123203&r1=123202&r2=123203&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original) > +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Mon Jan 10 18:36:45 2011 > @@ -1693,6 +1693,45 @@ > return ExtractValueInst::Create(Call, 1, "uadd.overflow"); > } > > +// DemandedBitsLHSMask - When performing a comparison against a constant, > +// it is possible that not all the bits in the LHS are demanded. This helper > +// method computes the mask that IS demanded. Is the capital IS for emphasis? It looks like a typo. > +static APInt DemandedBitsLHSMask(ICmpInst&I, > + unsigned BitWidth, bool isSignCheck) { > + if (isSignCheck) > + return APInt::getSignBit(BitWidth); > + > + ConstantInt *CI = dyn_cast(I.getOperand(1)); > + if (!CI) return APInt::getAllOnesValue(BitWidth); > + > + APInt RHS = CI->getValue(); > + APInt Mask(BitWidth, 0); > + > + switch (I.getPredicate()) { > + // For a UGT comparison, we don't care about any bits that > + // correspond to the trailing ones of the comparand. The value of these > + // bits doesn't impact the outcome of the comparison, because any value > + // greater than the RHS must differ in a bit higher than these due to carry. > + case ICmpInst::ICMP_UGT: { > + unsigned trailingOnes = RHS.countTrailingOnes(); > + APInt lowBitsSet = APInt::getLowBitsSet(BitWidth, trailingOnes); > + return ~lowBitsSet; > + } > + > + // Similarly, for a ULT comparison, we don't care about the trailing zeros. > + // Any value less than the RHS must differ in a higher bit because of carries. > + case ICmpInst::ICMP_ULT: { > + unsigned trailingZeros = RHS.countTrailingZeros(); > + APInt lowBitsSet = APInt::getLowBitsSet(BitWidth, trailingZeros); > + return ~lowBitsSet; > + } > + > + default: > + return APInt::getAllOnesValue(BitWidth); > + } > + > + return Mask; > +} > > Instruction *InstCombiner::visitICmpInst(ICmpInst&I) { > bool Changed = false; > @@ -1830,8 +1869,7 @@ > APInt Op1KnownZero(BitWidth, 0), Op1KnownOne(BitWidth, 0); > > if (SimplifyDemandedBits(I.getOperandUse(0), > - isSignBit ? APInt::getSignBit(BitWidth) > - : APInt::getAllOnesValue(BitWidth), > + DemandedBitsLHSMask(I, BitWidth, isSignBit), I think you can generalize DemandedBitsLHSMask to handle SGT/SLT well enough that isSignBit can be removed here. Nick > Op0KnownZero, Op0KnownOne, 0)) > return&I; > if (SimplifyDemandedBits(I.getOperandUse(1), > > Modified: llvm/trunk/test/Transforms/InstCombine/icmp.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/icmp.ll?rev=123203&r1=123202&r2=123203&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/InstCombine/icmp.ll (original) > +++ llvm/trunk/test/Transforms/InstCombine/icmp.ll Mon Jan 10 18:36:45 2011 > @@ -192,3 +192,20 @@ > ; CHECK-NEXT: %cmp = icmp eq i32 %x, 3 > } > > +define i1 @test21(i8 %x, i8 %y) { > +; CHECK: @test21 > +; CHECK-NOT: or i8 > +; CHECK: icmp ugt > + %A = or i8 %x, 1 > + %B = icmp ugt i8 %A, 3 > + ret i1 %B > +} > + > +define i1 @test22(i8 %x, i8 %y) { > +; CHECK: @test22 > +; CHECK-NOT: or i8 > +; CHECK: icmp ult > + %A = or i8 %x, 1 > + %B = icmp ult i8 %A, 4 > + ret i1 %B > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From nicholas at mxc.ca Wed Jan 12 03:33:17 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Wed, 12 Jan 2011 01:33:17 -0800 Subject: [llvm-commits] [PATCH] Fix llvm.invariant support In-Reply-To: References: <0C0069DC-258D-45D1-877E-3921693D2221@apple.com> <4CFC16E0.1050103@mxc.ca> Message-ID: <4D2D755D.3080608@mxc.ca> Kenneth Uildriks wrote: > On Sun, Dec 5, 2010 at 4:49 PM, Nick Lewycky wrote: >> Kenneth Uildriks wrote: >>> >>> Here's the updated version. >> >> Firstly, could you please reduce your tests? Try writing tests as .ll files >> by hand; they should be absolutely minimal to expose the optimization (or >> verify that we don't do an unsafe transformation). >> >> + DEBUG(errs()<< "Invariant value is ("<< *(BI->first)<< "," >> +<< BI->second.Size<< ")\n"); >> + DEBUG(errs()<< "Target is ("<< *MemLoc.Ptr<< ", "<< MemLoc.Size >> +<< ")\n"); >> >> These should be DEBUG(dbgs()<< ...) not errs(). Please check all of them. >> >> Nick >> > After reducing the tests, I found cases that it missed, so I reworked > the algorithm. Now it recognizes invariant regions as regions of code > dominated by an llvm.invariant.begin that aren't reachable from the > matching llvm.invariant.end without going back through the > llvm.invariant.begin. It brings in the DominatorTree and > DominanceFrontier analyses to figure this out more quickly and > cleanly. > > In MemDepPrereqs.patch, there are changes to DominanceFrontier and > BreakCritical edges that were needed for my MemoryDependenceAnalysis > changes to pass all the nightly tests. Since DominanceFrontier is > really a cache of frontier analysis results, it seems to me that it > shouldn't be asserting that an add attempt isn't redundant (and a > later pass was trying to add something that my algorithm had already > looked up in a few cases). Also, there was a latent bug in > BreakCriticalEdges that allows an llvm_unreachable assertion to > occasionally hit if DominanceFrontier is in play and a block is > unreachable. Let's do this one piece at a time. What's the bug in critical edges splitting? Can you produce a .ll file that fails "opt -break-crit-edges"? Broadly, I'm not happy about the domtree changes. I don't see why clients should need to query about blocks that don't exist, or add blocks that are already added. This indicates that extra work is going on at the callers side at the very least, and real problems some of the time. Adding DomTree as a dependency of MemDep is something that should be agreed upon with its maintainers first, but I'm for it. I've wanted to add other enhancements to memdep before and stopped due to a lack of domtree, and we know that domtree is preserved by almost every pass in the tree. Nick From jay.foad at gmail.com Wed Jan 12 09:54:47 2011 From: jay.foad at gmail.com (Jay Foad) Date: Wed, 12 Jan 2011 15:54:47 +0000 Subject: [llvm-commits] [PATCH] Bug 889: clean up dodgy casts between Value** and Constant** Message-ID: http://llvm.org/bugs/show_bug.cgi?id=889 This bug is about removing virtual methods from Value and its subclasses. While playing with fixes for this bug, I found a few C-style casts from Value** to Constant** or vice versa. This works at the moment, because a static_cast from Constant* to Value* doesn't have to adjust the "this" pointer, but it's not safe in general. In particular, it won't work if Constant has virtual methods but Value doesn't. The reason for the casts' existence is that there are various methods to do with creating getElementPtrs which take either an array of Values or an array of Constants, but there isn't much consistency -- some methods can only take an array of Values, and some can only take an array of Constants. This patch ensures that there are two overloads for each such method: one taking an array of Values, and one taking an array of Constants. By calling the appropriate version in each case, we can avoid the casts. Tested with "make check". OK to commit? Thanks, Jay. -------------- next part -------------- A non-text attachment was scrubbed... Name: fix-dodgy-casts Type: application/octet-stream Size: 13170 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110112/97490b28/attachment.obj From rafael.espindola at gmail.com Wed Jan 12 10:59:01 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Wed, 12 Jan 2011 11:59:01 -0500 Subject: [llvm-commits] [patch] Only allow unnamed_addr in definitions Message-ID: <4D2DDDD5.60808@gmail.com> The attached patches changes llvm to only accept unnamed_addr in definitions and clang to not produce them in declarations. I am not entirely convinced that we should do it. The reasons so far are *) There is nothing for LLVM to do with the knowledge that a declaration might be merged in the future *) It would require us to define what the linker should do on mismatched declarations and definitions. The correct answer would probably be "ignore the bit in the declaration and keep the definition one", which also suggest that we shouldn't have this in declarations. OK? Cheers, Rafael -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: clang.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110112/5e5daed7/attachment.pl -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: llvm.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110112/5e5daed7/attachment-0001.pl From matthewbg at google.com Wed Jan 12 12:02:55 2011 From: matthewbg at google.com (Matt Beaumont-Gay) Date: Wed, 12 Jan 2011 18:02:55 -0000 Subject: [llvm-commits] [llvm] r123317 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Message-ID: <20110112180255.BD5DA2A6C12C@llvm.org> Author: matthewbg Date: Wed Jan 12 12:02:55 2011 New Revision: 123317 URL: http://llvm.org/viewvc/llvm-project?rev=123317&view=rev Log: Mostly undo r123297, but move the default case in EvaluateAsPCRel to the top of the switch block to appease GCC. Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123317&r1=123316&r2=123317&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Wed Jan 12 12:02:55 2011 @@ -129,7 +129,7 @@ SmallVectorImpl &Fixups) const { ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); switch (Mode) { - default: llvm_unreachable("Unknown addressing sub-mode!"); + default: assert(0 && "Unknown addressing sub-mode!"); case ARM_AM::da: return 0; case ARM_AM::ia: return 1; case ARM_AM::db: return 2; @@ -646,9 +646,9 @@ // but this is good enough for now. static bool EvaluateAsPCRel(const MCExpr *Expr) { switch (Expr->getKind()) { + default: assert(0 && "Unexpected expression type"); case MCExpr::SymbolRef: return false; case MCExpr::Binary: return true; - default: llvm_unreachable("Unexpected expression type"); } } @@ -669,7 +669,7 @@ const MCExpr *OrigExpr = MO.getExpr(); MCFixupKind Kind; switch (Expr->getKind()) { - default: llvm_unreachable("Unsupported ARMFixup"); + default: assert(0 && "Unsupported ARMFixup"); case MCSymbolRefExpr::VK_ARM_HI16: Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); if (EvaluateAsPCRel(OrigExpr)) From matthewbg at google.com Wed Jan 12 12:06:52 2011 From: matthewbg at google.com (Matt Beaumont-Gay) Date: Wed, 12 Jan 2011 10:06:52 -0800 Subject: [llvm-commits] [llvm] r123297 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp In-Reply-To: References: <20110112014242.E4A352A6C12C@llvm.org> <8FD2091A-A314-4786-91EC-C41603BB135B@apple.com> Message-ID: On Tue, Jan 11, 2011 at 23:42, Chris Lattner wrote: > > On Jan 11, 2011, at 6:13 PM, Nick Lewycky wrote: > > On 11 January 2011 17:47, Chris Lattner wrote: >> >> On Jan 11, 2011, at 5:42 PM, Matt Beaumont-Gay wrote: >> >> > Author: matthewbg >> > Date: Tue Jan 11 19:42:42 2011 >> > New Revision: 123297 >> > >> > URL: http://llvm.org/viewvc/llvm-project?rev=123297&view=rev >> > Log: >> > Prefer llvm_unreachable to assert(0) >> >> Hi Matt, >> >> Please use assert(0) unless we need the "does not fallthrough" behavior of >> llvm_unreachable. > > The difference is that llvm_unreachable still generates code in a Release > build while assert() doesn't, right? > Matt made this commit because we were seeing: > ??llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp:653: error: control reaches end > of non-void function [-Wreturn-type] > so it sounds like llvm_unreachable isn't the right tool, but we'd like to > fix this that doesn't generate warnings in release builds. > > Please move the default case to the first part of the switch statement: > switch (whatever) { > default: ?assert(0 && ... > case 0: > that way, in non-assert builds, the compiler still thinks everything is > great. Got it, done in r123317. Is it worth mentioning this in the coding style docs? -Matt From evan.cheng at apple.com Wed Jan 12 12:49:45 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Jan 2011 10:49:45 -0800 Subject: [llvm-commits] [llvm] r123294 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/elf-movt.s In-Reply-To: <20110112001925.8DE2B2A6C12C@llvm.org> References: <20110112001925.8DE2B2A6C12C@llvm.org> Message-ID: On Jan 11, 2011, at 4:19 PM, Jason W Kim wrote: > > Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=123294&r1=123293&r2=123294&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Jan 11 18:19:25 2011 > @@ -189,10 +189,10 @@ > int64_t Imm = MO.getImm(); > O << '#'; > if ((Modifier && strcmp(Modifier, "lo16") == 0) || > - (TF == ARMII::MO_LO16)) > + (TF & ARMII::MO_LO16)) > O << ":lower16:"; > else if ((Modifier && strcmp(Modifier, "hi16") == 0) || > - (TF == ARMII::MO_HI16)) > + (TF & ARMII::MO_HI16)) > O << ":upper16:"; > O << Imm; > break; Are these modifiers still being used? I don't see them. Evan > > Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=123294&r1=123293&r2=123294&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Tue Jan 11 18:19:25 2011 > @@ -74,6 +74,11 @@ > fixup_arm_movt_hi16, // :upper16: > fixup_arm_movw_lo16, // :lower16: > > + // It is possible to create an "immediate" that happens to be pcrel. > + // Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC > + fixup_arm_movt_hi16_pcrel, // :upper16: > + fixup_arm_movw_lo16_pcrel, // :lower16: > + > // Marker > LastTargetFixupKind, > NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind > > Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123294&r1=123293&r2=123294&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Jan 11 18:19:25 2011 > @@ -626,6 +626,32 @@ > return Binary; > } > > +// FIXME: This routine needs to handle more MCExpr types > +static const MCSymbolRefExpr *FindLHSymExpr(const MCExpr *E) { > + // recurse left child until finding a MCSymbolRefExpr > + switch (E->getKind()) { > + case MCExpr::SymbolRef: > + return cast(E); > + case MCExpr::Binary: > + return FindLHSymExpr(cast(E)->getLHS()); > + default: > + return NULL; > + } > +} > + > +// FIXME: This routine assumes that a binary > +// expression will always result in a PCRel expression > +// In reality, its only true if one or more subexpressions > +// is itself a PCRel (i.e. "." in asm or some other pcrel construct) > +// but this is good enough for now. > +static bool EvaluateAsPCRel(const MCExpr *Expr) { > + switch (Expr->getKind()) { > + case MCExpr::SymbolRef: return false; > + case MCExpr::Binary: return true; > + default: assert(0 && "Unexpected expression type"); > + } > +} > + > uint32_t ARMMCCodeEmitter:: > getMovtImmOpValue(const MCInst &MI, unsigned OpIdx, > SmallVectorImpl &Fixups) const { > @@ -635,18 +661,27 @@ > if (MO.isImm()) { > return static_cast(MO.getImm()); > } else if (const MCSymbolRefExpr *Expr = > - dyn_cast(MO.getExpr())) { > + FindLHSymExpr(MO.getExpr())) { > + // FIXME: :lower16: and :upper16: should be applicable to > + // to whole expression, not just symbolrefs > + // Until that change takes place, this hack is required to > + // generate working code. > + const MCExpr *OrigExpr = MO.getExpr(); > MCFixupKind Kind; > switch (Expr->getKind()) { > default: assert(0 && "Unsupported ARMFixup"); > case MCSymbolRefExpr::VK_ARM_HI16: > Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); > + if (EvaluateAsPCRel(OrigExpr)) > + Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel); > break; > case MCSymbolRefExpr::VK_ARM_LO16: > Kind = MCFixupKind(ARM::fixup_arm_movw_lo16); > + if (EvaluateAsPCRel(OrigExpr)) > + Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel); > break; > } > - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); > + Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind)); > return 0; > }; > llvm_unreachable("Unsupported MCExpr type in MCOperand!"); > > Modified: llvm/trunk/test/MC/ARM/elf-movt.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123294&r1=123293&r2=123294&view=diff > ============================================================================== > --- llvm/trunk/test/MC/ARM/elf-movt.s (original) > +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 18:19:25 2011 > @@ -1,4 +1,6 @@ > @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s > +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ > +@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s > .syntax unified > .text > .globl barf > @@ -12,3 +14,26 @@ > @ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) > @ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) > > +@@ make sure that the text section fixups are sane too > +@ OBJ: '.text' > +@ OBJ-NEXT: 'sh_type', 0x00000001 > +@ OBJ-NEXT: 'sh_flags', 0x00000006 > +@ OBJ-NEXT: 'sh_addr', 0x00000000 > +@ OBJ-NEXT: 'sh_offset', 0x00000034 > +@ OBJ-NEXT: 'sh_size', 0x00000008 > +@ OBJ-NEXT: 'sh_link', 0x00000000 > +@ OBJ-NEXT: 'sh_info', 0x00000000 > +@ OBJ-NEXT: 'sh_addralign', 0x00000004 > +@ OBJ-NEXT: 'sh_entsize', 0x00000000 > +@ OBJ-NEXT: '_section_data', 'f00f0fe3 ec0f4fe3' > + > +@ OBJ: Relocation 0x00000000 > +@ OBJ-NEXT: 'r_offset', 0x00000000 > +@ OBJ-NEXT: 'r_sym' > +@ OBJ-NEXT: 'r_type', 0x0000002d > + > +@ OBJ: Relocation 0x00000001 > +@ OBJ-NEXT: 'r_offset', 0x00000004 > +@ OBJ-NEXT: 'r_sym' > +@ OBJ-NEXT: 'r_type', 0x0000002e > + > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Wed Jan 12 12:59:40 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 12 Jan 2011 10:59:40 -0800 Subject: [llvm-commits] [llvm] r123294 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/elf-movt.s In-Reply-To: References: <20110112001925.8DE2B2A6C12C@llvm.org> Message-ID: <6A606348-4C03-4706-90FF-F555BCFE2F6F@apple.com> On Jan 12, 2011, at 10:49 AM, Evan Cheng wrote: > > On Jan 11, 2011, at 4:19 PM, Jason W Kim wrote: > >> >> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=123294&r1=123293&r2=123294&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Jan 11 18:19:25 2011 >> @@ -189,10 +189,10 @@ >> int64_t Imm = MO.getImm(); >> O << '#'; >> if ((Modifier && strcmp(Modifier, "lo16") == 0) || >> - (TF == ARMII::MO_LO16)) >> + (TF & ARMII::MO_LO16)) >> O << ":lower16:"; >> else if ((Modifier && strcmp(Modifier, "hi16") == 0) || >> - (TF == ARMII::MO_HI16)) >> + (TF & ARMII::MO_HI16)) >> O << ":upper16:"; >> O << Imm; >> break; > > Are these modifiers still being used? I don't see them. > There shouldn't be any uses of the Modifier string left in the ARM backend. If there are, we should fix it. :) -Jim > >> >> Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=123294&r1=123293&r2=123294&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original) >> +++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Tue Jan 11 18:19:25 2011 >> @@ -74,6 +74,11 @@ >> fixup_arm_movt_hi16, // :upper16: >> fixup_arm_movw_lo16, // :lower16: >> >> + // It is possible to create an "immediate" that happens to be pcrel. >> + // Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC >> + fixup_arm_movt_hi16_pcrel, // :upper16: >> + fixup_arm_movw_lo16_pcrel, // :lower16: >> + >> // Marker >> LastTargetFixupKind, >> NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind >> >> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123294&r1=123293&r2=123294&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Jan 11 18:19:25 2011 >> @@ -626,6 +626,32 @@ >> return Binary; >> } >> >> +// FIXME: This routine needs to handle more MCExpr types >> +static const MCSymbolRefExpr *FindLHSymExpr(const MCExpr *E) { >> + // recurse left child until finding a MCSymbolRefExpr >> + switch (E->getKind()) { >> + case MCExpr::SymbolRef: >> + return cast(E); >> + case MCExpr::Binary: >> + return FindLHSymExpr(cast(E)->getLHS()); >> + default: >> + return NULL; >> + } >> +} >> + >> +// FIXME: This routine assumes that a binary >> +// expression will always result in a PCRel expression >> +// In reality, its only true if one or more subexpressions >> +// is itself a PCRel (i.e. "." in asm or some other pcrel construct) >> +// but this is good enough for now. >> +static bool EvaluateAsPCRel(const MCExpr *Expr) { >> + switch (Expr->getKind()) { >> + case MCExpr::SymbolRef: return false; >> + case MCExpr::Binary: return true; >> + default: assert(0 && "Unexpected expression type"); >> + } >> +} >> + >> uint32_t ARMMCCodeEmitter:: >> getMovtImmOpValue(const MCInst &MI, unsigned OpIdx, >> SmallVectorImpl &Fixups) const { >> @@ -635,18 +661,27 @@ >> if (MO.isImm()) { >> return static_cast(MO.getImm()); >> } else if (const MCSymbolRefExpr *Expr = >> - dyn_cast(MO.getExpr())) { >> + FindLHSymExpr(MO.getExpr())) { >> + // FIXME: :lower16: and :upper16: should be applicable to >> + // to whole expression, not just symbolrefs >> + // Until that change takes place, this hack is required to >> + // generate working code. >> + const MCExpr *OrigExpr = MO.getExpr(); >> MCFixupKind Kind; >> switch (Expr->getKind()) { >> default: assert(0 && "Unsupported ARMFixup"); >> case MCSymbolRefExpr::VK_ARM_HI16: >> Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); >> + if (EvaluateAsPCRel(OrigExpr)) >> + Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel); >> break; >> case MCSymbolRefExpr::VK_ARM_LO16: >> Kind = MCFixupKind(ARM::fixup_arm_movw_lo16); >> + if (EvaluateAsPCRel(OrigExpr)) >> + Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel); >> break; >> } >> - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); >> + Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind)); >> return 0; >> }; >> llvm_unreachable("Unsupported MCExpr type in MCOperand!"); >> >> Modified: llvm/trunk/test/MC/ARM/elf-movt.s >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123294&r1=123293&r2=123294&view=diff >> ============================================================================== >> --- llvm/trunk/test/MC/ARM/elf-movt.s (original) >> +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 18:19:25 2011 >> @@ -1,4 +1,6 @@ >> @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s >> +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ >> +@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s >> .syntax unified >> .text >> .globl barf >> @@ -12,3 +14,26 @@ >> @ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) >> @ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) >> >> +@@ make sure that the text section fixups are sane too >> +@ OBJ: '.text' >> +@ OBJ-NEXT: 'sh_type', 0x00000001 >> +@ OBJ-NEXT: 'sh_flags', 0x00000006 >> +@ OBJ-NEXT: 'sh_addr', 0x00000000 >> +@ OBJ-NEXT: 'sh_offset', 0x00000034 >> +@ OBJ-NEXT: 'sh_size', 0x00000008 >> +@ OBJ-NEXT: 'sh_link', 0x00000000 >> +@ OBJ-NEXT: 'sh_info', 0x00000000 >> +@ OBJ-NEXT: 'sh_addralign', 0x00000004 >> +@ OBJ-NEXT: 'sh_entsize', 0x00000000 >> +@ OBJ-NEXT: '_section_data', 'f00f0fe3 ec0f4fe3' >> + >> +@ OBJ: Relocation 0x00000000 >> +@ OBJ-NEXT: 'r_offset', 0x00000000 >> +@ OBJ-NEXT: 'r_sym' >> +@ OBJ-NEXT: 'r_type', 0x0000002d >> + >> +@ OBJ: Relocation 0x00000001 >> +@ OBJ-NEXT: 'r_offset', 0x00000004 >> +@ OBJ-NEXT: 'r_sym' >> +@ OBJ-NEXT: 'r_type', 0x0000002e >> + >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Wed Jan 12 13:12:45 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 12 Jan 2011 19:12:45 -0000 Subject: [llvm-commits] [llvm] r123318 - /llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp Message-ID: <20110112191245.703722A6C12C@llvm.org> Author: dpatel Date: Wed Jan 12 13:12:45 2011 New Revision: 123318 URL: http://llvm.org/viewvc/llvm-project?rev=123318&view=rev Log: Use SmallVector instead of SmallPtrSet and avoid non-deterministic behavior. Modified: llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp?rev=123318&r1=123317&r2=123318&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp Wed Jan 12 13:12:45 2011 @@ -194,13 +194,13 @@ // be deleted from the reference counting scheme. DominatorTree& DT = getAnalysis(); DominanceFrontier* DF = getAnalysisIfAvailable(); - SmallPtrSet ChildNodes; + SmallVector ChildNodes; for (Loop::block_iterator LI = L->block_begin(), LE = L->block_end(); LI != LE; ++LI) { // Move all of the block's children to be children of the preheader, which // allows us to remove the domtree entry for the block. - ChildNodes.insert(DT[*LI]->begin(), DT[*LI]->end()); - for (SmallPtrSet::iterator DI = ChildNodes.begin(), + ChildNodes.insert(ChildNodes.begin(), DT[*LI]->begin(), DT[*LI]->end()); + for (SmallVector::iterator DI = ChildNodes.begin(), DE = ChildNodes.end(); DI != DE; ++DI) { DT.changeImmediateDominator(*DI, DT[preheader]); if (DF) DF->changeImmediateDominator((*DI)->getBlock(), preheader, &DT); From isanbard at gmail.com Wed Jan 12 15:20:59 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 12 Jan 2011 21:20:59 -0000 Subject: [llvm-commits] [llvm] r123321 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/reg-list.s Message-ID: <20110112212059.CD9662A6C12C@llvm.org> Author: void Date: Wed Jan 12 15:20:59 2011 New Revision: 123321 URL: http://llvm.org/viewvc/llvm-project?rev=123321&view=rev Log: Sort the register list based on the *actual* register numbers rather than the enum values we give to them. Added: llvm/trunk/test/MC/ARM/reg-list.s Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123321&r1=123320&r2=123321&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jan 12 15:20:59 2011 @@ -583,15 +583,15 @@ SmallVectorImpl >::const_iterator RI = Registers.begin(), RE = Registers.end(); - DenseMap RegMap; - RegMap[RI->first] = true; - - unsigned HighRegNum = RI->first; + unsigned HighRegNum = getARMRegisterNumbering(RI->first); bool EmittedWarning = false; + DenseMap RegMap; + RegMap[HighRegNum] = true; + for (++RI; RI != RE; ++RI) { const std::pair &RegInfo = *RI; - unsigned Reg = RegInfo.first; + unsigned Reg = getARMRegisterNumbering(RegInfo.first); if (RegMap[Reg]) { Error(RegInfo.second, "register duplicated in register list"); Added: llvm/trunk/test/MC/ARM/reg-list.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/reg-list.s?rev=123321&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/reg-list.s (added) +++ llvm/trunk/test/MC/ARM/reg-list.s Wed Jan 12 15:20:59 2011 @@ -0,0 +1,8 @@ +@ RUN: llvm-mc -triple thumb-apple-darwin10 -show-encoding < %s 2> %t | FileCheck %s +@ RUN: FileCheck --check-prefix=CHECK-WARNINGS < %t %s + + push {r7, lr} +@ CHECK-WARNINGS: register not in ascending order in register list + + push {lr, r7} +@ CHECK: push {lr, r7} From stoklund at 2pi.dk Wed Jan 12 15:27:41 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 12 Jan 2011 21:27:41 -0000 Subject: [llvm-commits] [llvm] r123322 - /llvm/trunk/lib/CodeGen/MachineVerifier.cpp Message-ID: <20110112212741.E03892A6C12C@llvm.org> Author: stoklund Date: Wed Jan 12 15:27:41 2011 New Revision: 123322 URL: http://llvm.org/viewvc/llvm-project?rev=123322&view=rev Log: Verify that machine instruction parent pointers are consistent. Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=123322&r1=123321&r2=123322&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Wed Jan 12 15:27:41 2011 @@ -273,6 +273,11 @@ visitMachineBasicBlockBefore(MFI); for (MachineBasicBlock::const_iterator MBBI = MFI->begin(), MBBE = MFI->end(); MBBI != MBBE; ++MBBI) { + if (MBBI->getParent() != MFI) { + report("Bad instruction parent pointer", MFI); + *OS << "Instruction: " << *MBBI; + continue; + } visitMachineInstrBefore(MBBI); for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) visitMachineOperand(&MBBI->getOperand(I), I); From stoklund at 2pi.dk Wed Jan 12 15:27:45 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 12 Jan 2011 21:27:45 -0000 Subject: [llvm-commits] [llvm] r123323 - /llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Message-ID: <20110112212745.B58372A6C12D@llvm.org> Author: stoklund Date: Wed Jan 12 15:27:45 2011 New Revision: 123323 URL: http://llvm.org/viewvc/llvm-project?rev=123323&view=rev Log: Assert if anybody tries to put a slot index on a DBG_VALUE instruction. Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=123323&r1=123322&r2=123323&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original) +++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Wed Jan 12 15:27:45 2011 @@ -625,6 +625,9 @@ SlotIndex insertMachineInstrInMaps(MachineInstr *mi, bool *deferredRenumber = 0) { assert(mi2iMap.find(mi) == mi2iMap.end() && "Instr already indexed."); + // Numbering DBG_VALUE instructions could cause code generation to be + // affected by debug information. + assert(!mi->isDebugValue() && "Cannot number DBG_VALUE instructions."); MachineBasicBlock *mbb = mi->getParent(); From stoklund at 2pi.dk Wed Jan 12 15:27:48 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 12 Jan 2011 21:27:48 -0000 Subject: [llvm-commits] [llvm] r123324 - /llvm/trunk/lib/CodeGen/MachineVerifier.cpp Message-ID: <20110112212748.4C88B2A6C12E@llvm.org> Author: stoklund Date: Wed Jan 12 15:27:48 2011 New Revision: 123324 URL: http://llvm.org/viewvc/llvm-project?rev=123324&view=rev Log: Verify slot index ordering. The slot indexes must be monotonically increasing through the function. Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=123324&r1=123323&r2=123324&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Wed Jan 12 15:27:48 2011 @@ -74,6 +74,8 @@ RegVector regsDefined, regsDead, regsKilled; RegSet regsLiveInButUnused; + SlotIndex lastIndex; + // Add Reg and any sub-registers to RV void addRegWithSubRegs(RegVector &RV, unsigned Reg) { RV.push_back(Reg); @@ -356,6 +358,7 @@ } void MachineVerifier::visitMachineFunctionBefore() { + lastIndex = SlotIndex(); regsReserved = TRI->getReservedRegs(*MF); // A sub-register of a reserved register is also reserved @@ -524,6 +527,9 @@ regsKilled.clear(); regsDefined.clear(); + + if (Indexes) + lastIndex = Indexes->getMBBStartIdx(MBB); } void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { @@ -793,12 +799,31 @@ set_subtract(regsLive, regsKilled); regsKilled.clear(); set_subtract(regsLive, regsDead); regsDead.clear(); set_union(regsLive, regsDefined); regsDefined.clear(); + + if (Indexes && Indexes->hasIndex(MI)) { + SlotIndex idx = Indexes->getInstructionIndex(MI); + if (!(idx > lastIndex)) { + report("Instruction index out of order", MI); + *OS << "Last instruction was at " << lastIndex << '\n'; + } + lastIndex = idx; + } } void MachineVerifier::visitMachineBasicBlockAfter(const MachineBasicBlock *MBB) { MBBInfoMap[MBB].regsLiveOut = regsLive; regsLive.clear(); + + if (Indexes) { + SlotIndex stop = Indexes->getMBBEndIdx(MBB); + if (!(stop > lastIndex)) { + report("Block ends before last instruction index", MBB); + *OS << "Block ends at " << stop + << " last instruction was at " << lastIndex << '\n'; + } + lastIndex = stop; + } } // Calculate the largest possible vregsPassed sets. These are the registers that From dpatel at apple.com Wed Jan 12 15:38:56 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 12 Jan 2011 21:38:56 -0000 Subject: [llvm-commits] [test-suite] r123325 - /test-suite/trunk/TEST.dbg.Makefile Message-ID: <20110112213856.172C62A6C12C@llvm.org> Author: dpatel Date: Wed Jan 12 15:38:55 2011 New Revision: 123325 URL: http://llvm.org/viewvc/llvm-project?rev=123325&view=rev Log: Handle c++ and objective-c files. Modified: test-suite/trunk/TEST.dbg.Makefile Modified: test-suite/trunk/TEST.dbg.Makefile URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/TEST.dbg.Makefile?rev=123325&r1=123324&r2=123325&view=diff ============================================================================== --- test-suite/trunk/TEST.dbg.Makefile (original) +++ test-suite/trunk/TEST.dbg.Makefile Wed Jan 12 15:38:55 2011 @@ -23,6 +23,18 @@ $(LCC) $(CPPFLAGS) $(CFLAGS) -g -c -emit-llvm $< -o $@.bc $(LOPT) -print-breakpoints-for-testing $@.bc -o $@ +Output/%.bp: %.cpp Output/.dir + $(LCXX) $(CPPFLAGS) $(CFLAGS) -g -c -emit-llvm $< -o $@.bc + $(LOPT) -print-breakpoints-for-testing $@.bc -o $@ + +Output/%.bp: %.m Output/.dir + $(LCC) $(CPPFLAGS) $(CFLAGS) -g -c -emit-llvm $< -o $@.bc + $(LOPT) -print-breakpoints-for-testing $@.bc -o $@ + +Output/%.bp: %.mm Output/.dir + $(LCXX) $(CPPFLAGS) $(CFLAGS) -g -c -emit-llvm $< -o $@.bc + $(LOPT) -print-breakpoints-for-testing $@.bc -o $@ + $(PROGRAMS_TO_TEST:%=test.$(TEST).%): \ test.$(TEST).%: Output/%.bp Output/%.dbg Output/%.dbg.opt echo $@ From grosbach at apple.com Wed Jan 12 15:44:36 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 12 Jan 2011 13:44:36 -0800 Subject: [llvm-commits] [llvm] r123292 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/elf-movt.s In-Reply-To: <20110111235341.A4A2E2A6C12C@llvm.org> References: <20110111235341.A4A2E2A6C12C@llvm.org> Message-ID: Leaving aside most architectural questions as they're be subsumed by the changes to have the variantkind stuff apply to more than just symbolref expressions. A few comments below. On Jan 11, 2011, at 3:53 PM, Jason W Kim wrote: > Author: jasonwkim > Date: Tue Jan 11 17:53:41 2011 > New Revision: 123292 > > URL: http://llvm.org/viewvc/llvm-project?rev=123292&view=rev > Log: > Workaround for bug 8721. > .s Test added. > > > Added: > llvm/trunk/test/MC/ARM/elf-movt.s > Modified: > llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > > Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123292&r1=123291&r2=123292&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) > +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jan 11 17:53:41 2011 > @@ -55,6 +55,10 @@ > bool ParseRegisterList(SmallVectorImpl &); > bool ParseMemory(SmallVectorImpl &); > bool ParseOperand(SmallVectorImpl &); > + bool ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind); > + const MCExpr *ApplyPrefixToExpr(const MCExpr *E, > + MCSymbolRefExpr::VariantKind Variant); > + > > bool ParseMemoryOffsetReg(bool &Negative, > bool &OffsetRegShifted, > @@ -864,9 +868,111 @@ > E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); > Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); > return false; > + case AsmToken::Colon: { > + // ":lower16:" and ":upper16:" expression prefixes > + MCSymbolRefExpr::VariantKind RefKind; > + if (ParsePrefix(RefKind)) > + return true; > + > + const MCExpr *ExprVal; > + if (getParser().ParseExpression(ExprVal)) > + return true; > + > + // TODO: Attach the prefix to the entire expression > + // instead of just the first symbol. > + const MCExpr *ModExprVal = ApplyPrefixToExpr(ExprVal, RefKind); > + if (!ModExprVal) { > + return TokError("invalid modifier '" + getTok().getIdentifier() + > + "' (no symbols present)"); > + } > + > + E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); > + Operands.push_back(ARMOperand::CreateImm(ModExprVal, S, E)); > + return false; > + } > } > } > > +// FIXME: The next 2 routines are hacks to get ARMAsmParser to understand > +// :lower16: and :upper16: > +// It still attaches VK_ARM_HI/LO16 to MCSymbolRefExpr, but it really > +// should be attached to the entire MCExpr as a whole - perhaps using > +// MCTargetExpr? > +bool ARMAsmParser::ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind) { > + RefKind = MCSymbolRefExpr::VK_None; > + > + // :lower16: and :upper16: modifiers > + if (getLexer().isNot(AsmToken::Colon)) { > + Error(Parser.getTok().getLoc(), "expected :"); > + return true; > + } This can just be an assert(), not an error. This is only called when a ':' token has been detected, else we have a parser bug and want to abort. > + Parser.Lex(); // Eat ':' > + > + if (getLexer().isNot(AsmToken::Identifier)) { > + Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); > + return true; > + } > + > + StringRef IDVal = Parser.getTok().getIdentifier(); > + if (IDVal == "lower16") { > + RefKind = MCSymbolRefExpr::VK_ARM_LO16; > + } else if (IDVal == "upper16") { > + RefKind = MCSymbolRefExpr::VK_ARM_HI16; > + } else { > + Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); > + return true; > + } > + Parser.Lex(); > + > + if (getLexer().isNot(AsmToken::Colon)) { > + Error(Parser.getTok().getLoc(), "unexpected token after prefix"); > + return true; > + } > + Parser.Lex(); // Eat the last ':' > + return false; > +} > + > +const MCExpr * > +ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E, > + MCSymbolRefExpr::VariantKind Variant) { > + // Recurse over the given expression, rebuilding it to apply the given variant > + // to the leftmost symbol. > + if (Variant == MCSymbolRefExpr::VK_None) > + return E; > + > + switch (E->getKind()) { > + case MCExpr::Target: > + llvm_unreachable("Can't handle target expr yet"); > + case MCExpr::Constant: > + llvm_unreachable("Can't handle lower16/upper16 of constant yet"); > + > + case MCExpr::SymbolRef: { > + const MCSymbolRefExpr *SRE = cast(E); > + > + if (SRE->getKind() != MCSymbolRefExpr::VK_None) > + return 0; > + > + return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); > + } > + > + case MCExpr::Unary: > + llvm_unreachable("Can't handle unary expressions yet"); > + > + case MCExpr::Binary: { > + const MCBinaryExpr *BE = cast(E); > + const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant); > + const MCExpr *RHS = BE->getRHS(); > + if (!LHS) > + return 0; > + > + return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); > + } > + } > + > + assert(0 && "Invalid expression kind!"); > + return 0; > +} > + > /// \brief Given a mnemonic, split out possible predication code and carry > /// setting letters to form a canonical mnemonic and flags. > // > > Added: llvm/trunk/test/MC/ARM/elf-movt.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123292&view=auto > ============================================================================== > --- llvm/trunk/test/MC/ARM/elf-movt.s (added) > +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 17:53:41 2011 > @@ -0,0 +1,14 @@ > +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s > + .syntax unified > + .text > + .globl barf > + .align 2 > + .type barf,%function > +barf: @ @barf > +@ BB#0: @ %entry > + movw r0, :lower16:GOT-(.LPC0_2+8) > + movt r0, :upper16:GOT-(.LPC0_2+16) > +.LPC0_2: > +@ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) > +@ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) > + > Ditto Evan's comments on the test case values. > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From grosbach at apple.com Wed Jan 12 15:56:57 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 12 Jan 2011 13:56:57 -0800 Subject: [llvm-commits] [llvm] r123294 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/elf-movt.s In-Reply-To: <20110112001925.8DE2B2A6C12C@llvm.org> References: <20110112001925.8DE2B2A6C12C@llvm.org> Message-ID: <2F658FEE-4AD7-4075-B9AB-F2E2F4743F93@apple.com> Observations below. On Jan 11, 2011, at 4:19 PM, Jason W Kim wrote: > Author: jasonwkim > Date: Tue Jan 11 18:19:25 2011 > New Revision: 123294 > > URL: http://llvm.org/viewvc/llvm-project?rev=123294&view=rev > Log: > 1. Support ELF pcrel relocations for movw/movt: > R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC. > 2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum. > 3. Add support for 3 new elf section types (no-ops) > > > > Modified: > llvm/trunk/lib/MC/ELFObjectWriter.cpp > llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp > llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > llvm/trunk/lib/Target/ARM/ARMFixupKinds.h > llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp > llvm/trunk/test/MC/ARM/elf-movt.s > > Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=123294&r1=123293&r2=123294&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) > +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Tue Jan 11 18:19:25 2011 > @@ -1268,6 +1268,9 @@ > case ELF::SHT_NOTE: > case ELF::SHT_NULL: > case ELF::SHT_ARM_ATTRIBUTES: > + case ELF::SHT_INIT_ARRAY: > + case ELF::SHT_FINI_ARRAY: > + case ELF::SHT_PREINIT_ARRAY: > // Nothing to do. > break; > > @@ -1490,6 +1493,13 @@ > default: > Type = ELF::R_ARM_CALL; break; > } break; > + case ARM::fixup_arm_movt_hi16: > + case ARM::fixup_arm_movt_hi16_pcrel: > + Type = ELF::R_ARM_MOVT_PREL; break; > + case ARM::fixup_arm_movw_lo16: > + case ARM::fixup_arm_movw_lo16_pcrel: > + Type = ELF::R_ARM_MOVW_PREL_NC; break; > + Should the pc-rel and non-pc-rel fixups really both map to the same relocation? That doesn't seem right. If they're the same, they shouldn't need distinct fixups. If they're different, they should map differently. The "break" statement should be on the following line, not the same line as the assignment. As a style thing, keeping the break on the same line is fine when the whole thing (including the case label) is on the same line for simple stuff. Once there's already multiple lines, please separate them. The code above this gets very confusing due to this with nested switch statements and multiple breaks and such. > } > } else { > switch ((unsigned)Fixup.getKind()) { > > Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=123294&r1=123293&r2=123294&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Tue Jan 11 18:19:25 2011 > @@ -78,6 +78,8 @@ > { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, > { "fixup_arm_movt_hi16", 0, 16, 0 }, > { "fixup_arm_movw_lo16", 0, 16, 0 }, > +{ "fixup_arm_movt_hi16_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, > +{ "fixup_arm_movw_lo16_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, > }; > > if (Kind < FirstTargetFixupKind) > @@ -156,7 +158,9 @@ > case FK_Data_4: > return Value; > case ARM::fixup_arm_movt_hi16: > - case ARM::fixup_arm_movw_lo16: { > + case ARM::fixup_arm_movw_lo16: > + case ARM::fixup_arm_movt_hi16_pcrel: > + case ARM::fixup_arm_movw_lo16_pcrel: { > unsigned Hi4 = (Value & 0xF000) >> 12; > unsigned Lo12 = Value & 0x0FFF; > // inst{19-16} = Hi4; > > Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=123294&r1=123293&r2=123294&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Jan 11 18:19:25 2011 > @@ -189,10 +189,10 @@ > int64_t Imm = MO.getImm(); > O << '#'; > if ((Modifier && strcmp(Modifier, "lo16") == 0) || > - (TF == ARMII::MO_LO16)) > + (TF & ARMII::MO_LO16)) > O << ":lower16:"; > else if ((Modifier && strcmp(Modifier, "hi16") == 0) || > - (TF == ARMII::MO_HI16)) > + (TF & ARMII::MO_HI16)) As previously mentioned, you can just nuke the "Modifier" string compare. It's obsolete. The value-kinds look like masks, but they're not consistently used that way, unfortunately. If you want to change them to work additively instead of a one-variant-kind-per-symbolref, that's great and I completely agree it's worth doing, but it really should be a separate patch. Until then, this isn't correct. Please revert this bit. > O << ":upper16:"; > O << Imm; > break; > > Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=123294&r1=123293&r2=123294&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Tue Jan 11 18:19:25 2011 > @@ -74,6 +74,11 @@ > fixup_arm_movt_hi16, // :upper16: > fixup_arm_movw_lo16, // :lower16: > > + // It is possible to create an "immediate" that happens to be pcrel. I don't follow. Can you add an example? > + // Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC > + fixup_arm_movt_hi16_pcrel, // :upper16: > + fixup_arm_movw_lo16_pcrel, // :lower16: > + > // Marker > LastTargetFixupKind, > NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind > > Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123294&r1=123293&r2=123294&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Jan 11 18:19:25 2011 > @@ -626,6 +626,32 @@ > return Binary; > } > > +// FIXME: This routine needs to handle more MCExpr types > +static const MCSymbolRefExpr *FindLHSymExpr(const MCExpr *E) { > + // recurse left child until finding a MCSymbolRefExpr > + switch (E->getKind()) { > + case MCExpr::SymbolRef: > + return cast(E); > + case MCExpr::Binary: > + return FindLHSymExpr(cast(E)->getLHS()); > + default: > + return NULL; > + } > +} > + > +// FIXME: This routine assumes that a binary > +// expression will always result in a PCRel expression > +// In reality, its only true if one or more subexpressions > +// is itself a PCRel (i.e. "." in asm or some other pcrel construct) > +// but this is good enough for now. This comment makes me very, very nervous. LLVM isn't always compiling ARM code as PIC. Can you help me understand why this is indeed good enough for now? > +static bool EvaluateAsPCRel(const MCExpr *Expr) { > + switch (Expr->getKind()) { > + case MCExpr::SymbolRef: return false; > + case MCExpr::Binary: return true; > + default: assert(0 && "Unexpected expression type"); > + } > +} > + > uint32_t ARMMCCodeEmitter:: > getMovtImmOpValue(const MCInst &MI, unsigned OpIdx, > SmallVectorImpl &Fixups) const { > @@ -635,18 +661,27 @@ > if (MO.isImm()) { > return static_cast(MO.getImm()); > } else if (const MCSymbolRefExpr *Expr = > - dyn_cast(MO.getExpr())) { > + FindLHSymExpr(MO.getExpr())) { > + // FIXME: :lower16: and :upper16: should be applicable to > + // to whole expression, not just symbolrefs > + // Until that change takes place, this hack is required to > + // generate working code. > + const MCExpr *OrigExpr = MO.getExpr(); > MCFixupKind Kind; > switch (Expr->getKind()) { > default: assert(0 && "Unsupported ARMFixup"); > case MCSymbolRefExpr::VK_ARM_HI16: > Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); > + if (EvaluateAsPCRel(OrigExpr)) > + Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel); > break; > case MCSymbolRefExpr::VK_ARM_LO16: > Kind = MCFixupKind(ARM::fixup_arm_movw_lo16); > + if (EvaluateAsPCRel(OrigExpr)) > + Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel); > break; > } > - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); > + Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind)); > return 0; > }; > llvm_unreachable("Unsupported MCExpr type in MCOperand!"); > > Modified: llvm/trunk/test/MC/ARM/elf-movt.s > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123294&r1=123293&r2=123294&view=diff > ============================================================================== > --- llvm/trunk/test/MC/ARM/elf-movt.s (original) > +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 18:19:25 2011 > @@ -1,4 +1,6 @@ > @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s > +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ > +@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s > .syntax unified > .text > .globl barf > @@ -12,3 +14,26 @@ > @ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) > @ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) > > +@@ make sure that the text section fixups are sane too > +@ OBJ: '.text' > +@ OBJ-NEXT: 'sh_type', 0x00000001 > +@ OBJ-NEXT: 'sh_flags', 0x00000006 > +@ OBJ-NEXT: 'sh_addr', 0x00000000 > +@ OBJ-NEXT: 'sh_offset', 0x00000034 > +@ OBJ-NEXT: 'sh_size', 0x00000008 > +@ OBJ-NEXT: 'sh_link', 0x00000000 > +@ OBJ-NEXT: 'sh_info', 0x00000000 > +@ OBJ-NEXT: 'sh_addralign', 0x00000004 > +@ OBJ-NEXT: 'sh_entsize', 0x00000000 > +@ OBJ-NEXT: '_section_data', 'f00f0fe3 ec0f4fe3' > + > +@ OBJ: Relocation 0x00000000 > +@ OBJ-NEXT: 'r_offset', 0x00000000 > +@ OBJ-NEXT: 'r_sym' > +@ OBJ-NEXT: 'r_type', 0x0000002d > + > +@ OBJ: Relocation 0x00000001 > +@ OBJ-NEXT: 'r_offset', 0x00000004 > +@ OBJ-NEXT: 'r_sym' > +@ OBJ-NEXT: 'r_type', 0x0000002e > + > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From jasonwkim at google.com Wed Jan 12 16:04:19 2011 From: jasonwkim at google.com (Jason Kim) Date: Wed, 12 Jan 2011 14:04:19 -0800 Subject: [llvm-commits] [llvm] r123292 - in /llvm/trunk: lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/elf-movt.s In-Reply-To: References: <20110111235341.A4A2E2A6C12C@llvm.org> Message-ID: On Wed, Jan 12, 2011 at 1:44 PM, Jim Grosbach wrote: > Leaving aside most architectural questions as they're be subsumed by the changes to have the variantkind stuff apply to more than just symbolref expressions. A few comments below. > > > On Jan 11, 2011, at 3:53 PM, Jason W Kim wrote: > >> Author: jasonwkim >> Date: Tue Jan 11 17:53:41 2011 >> New Revision: 123292 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=123292&view=rev >> Log: >> Workaround for bug 8721. >> .s Test added. >> >> >> Added: >> ? ?llvm/trunk/test/MC/ARM/elf-movt.s >> Modified: >> ? ?llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp >> >> Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123292&r1=123291&r2=123292&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Tue Jan 11 17:53:41 2011 >> @@ -55,6 +55,10 @@ >> ? bool ParseRegisterList(SmallVectorImpl &); >> ? bool ParseMemory(SmallVectorImpl &); >> ? bool ParseOperand(SmallVectorImpl &); >> + ?bool ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind); >> + ?const MCExpr *ApplyPrefixToExpr(const MCExpr *E, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MCSymbolRefExpr::VariantKind Variant); >> + >> >> ? bool ParseMemoryOffsetReg(bool &Negative, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool &OffsetRegShifted, >> @@ -864,9 +868,111 @@ >> ? ? E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); >> ? ? Operands.push_back(ARMOperand::CreateImm(ImmVal, S, E)); >> ? ? return false; >> + ?case AsmToken::Colon: { >> + ? ?// ":lower16:" and ":upper16:" expression prefixes >> + ? ?MCSymbolRefExpr::VariantKind RefKind; >> + ? ?if (ParsePrefix(RefKind)) >> + ? ? ?return true; >> + >> + ? ?const MCExpr *ExprVal; >> + ? ?if (getParser().ParseExpression(ExprVal)) >> + ? ? ?return true; >> + >> + ? ?// TODO: Attach the prefix to the entire expression >> + ? ?// instead of just the first symbol. >> + ? ?const MCExpr *ModExprVal = ApplyPrefixToExpr(ExprVal, RefKind); >> + ? ?if (!ModExprVal) { >> + ? ? ?return TokError("invalid modifier '" + getTok().getIdentifier() + >> + ? ? ? ? ? ? ? ? ? ? ?"' (no symbols present)"); >> + ? ?} >> + >> + ? ?E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); >> + ? ?Operands.push_back(ARMOperand::CreateImm(ModExprVal, S, E)); >> + ? ?return false; >> + ?} >> ? } >> } >> >> +// FIXME: The next 2 routines are hacks to get ARMAsmParser to understand >> +// :lower16: and :upper16: >> +// It still attaches VK_ARM_HI/LO16 to MCSymbolRefExpr, but it really >> +// should be attached to the entire MCExpr as a whole - perhaps using >> +// MCTargetExpr? >> +bool ARMAsmParser::ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind) { >> + ?RefKind = MCSymbolRefExpr::VK_None; >> + >> + ?// :lower16: and :upper16: modifiers >> + ?if (getLexer().isNot(AsmToken::Colon)) { >> + ? ?Error(Parser.getTok().getLoc(), "expected :"); >> + ? ?return true; >> + ?} > > This can just be an assert(), not an error. This is only called when a ':' token has been detected, else we have a parser bug and want to abort. Okay. I will fix this. > >> + ?Parser.Lex(); // Eat ':' >> + >> + ?if (getLexer().isNot(AsmToken::Identifier)) { >> + ? ?Error(Parser.getTok().getLoc(), "expected prefix identifier in operand"); >> + ? ?return true; >> + ?} >> + >> + ?StringRef IDVal = Parser.getTok().getIdentifier(); >> + ?if (IDVal == "lower16") { >> + ? ?RefKind = MCSymbolRefExpr::VK_ARM_LO16; >> + ?} else if (IDVal == "upper16") { >> + ? ?RefKind = MCSymbolRefExpr::VK_ARM_HI16; >> + ?} else { >> + ? ?Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); >> + ? ?return true; >> + ?} >> + ?Parser.Lex(); >> + >> + ?if (getLexer().isNot(AsmToken::Colon)) { >> + ? ?Error(Parser.getTok().getLoc(), "unexpected token after prefix"); >> + ? ?return true; >> + ?} >> + ?Parser.Lex(); // Eat the last ':' >> + ?return false; >> +} >> + >> +const MCExpr * >> +ARMAsmParser::ApplyPrefixToExpr(const MCExpr *E, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MCSymbolRefExpr::VariantKind Variant) { >> + ?// Recurse over the given expression, rebuilding it to apply the given variant >> + ?// to the leftmost symbol. >> + ?if (Variant == MCSymbolRefExpr::VK_None) >> + ? ?return E; >> + >> + ?switch (E->getKind()) { >> + ?case MCExpr::Target: >> + ? ?llvm_unreachable("Can't handle target expr yet"); >> + ?case MCExpr::Constant: >> + ? ?llvm_unreachable("Can't handle lower16/upper16 of constant yet"); >> + >> + ?case MCExpr::SymbolRef: { >> + ? ?const MCSymbolRefExpr *SRE = cast(E); >> + >> + ? ?if (SRE->getKind() != MCSymbolRefExpr::VK_None) >> + ? ? ?return 0; >> + >> + ? ?return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, getContext()); >> + ?} >> + >> + ?case MCExpr::Unary: >> + ? ?llvm_unreachable("Can't handle unary expressions yet"); >> + >> + ?case MCExpr::Binary: { >> + ? ?const MCBinaryExpr *BE = cast(E); >> + ? ?const MCExpr *LHS = ApplyPrefixToExpr(BE->getLHS(), Variant); >> + ? ?const MCExpr *RHS = BE->getRHS(); >> + ? ?if (!LHS) >> + ? ? ?return 0; >> + >> + ? ?return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, getContext()); >> + ?} >> + ?} >> + >> + ?assert(0 && "Invalid expression kind!"); >> + ?return 0; >> +} >> + >> /// \brief Given a mnemonic, split out possible predication code and carry >> /// setting letters to form a canonical mnemonic and flags. >> // >> >> Added: llvm/trunk/test/MC/ARM/elf-movt.s >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123292&view=auto >> ============================================================================== >> --- llvm/trunk/test/MC/ARM/elf-movt.s (added) >> +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 17:53:41 2011 >> @@ -0,0 +1,14 @@ >> +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s >> + ? ? .syntax unified >> + ? ? .text >> + ? ? .globl ?barf >> + ? ? .align ?2 >> + ? ? .type ? barf,%function >> +barf: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ @barf >> +@ BB#0: ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? @ %entry >> + ? ? movw ? ?r0, :lower16:GOT-(.LPC0_2+8) >> + ? ? movt ? ?r0, :upper16:GOT-(.LPC0_2+16) >> +.LPC0_2: >> +@ ASM: ? ? ? ? ?movw ? ?r0, :lower16:GOT-(.LPC0_2+8) >> +@ ASM-NEXT: ? ? movt ? ?r0, :upper16:GOT-(.LPC0_2+16) >> + >> > > Ditto Evan's comments on the test case values. LOL :-) Looks like I did a reply, not a reply-all to Evan's review Reproduced here: The 16 was there just to verify that the fixup on the text worked as well. Yes, in real code, it would be +8 :-) > Evan Wrote: > I'd like to change :lower16: so it would become a MCExpr unary operator. However, that means the followings have different semantics: > > :lower16:GOT-(.LPC0_2+8) > and > :lower16:(GOT-(.LPC0_2+8)) > > So your example should look like the second case, right? Yes. That is correct. FYI, There is some fragility in the AsmParser - For example: inputing this sequence movw r0, :lower16:(GOT-(.LPC0_2+8)) movt r0, :upper16:GOT-.LPC0_2+8 produces this: movw r0, :lower16:GOT-(.LPC0_2+8) movt r0, (:upper16:GOT-.LPC0_2)+8 Ideally the :lower16: should be a lower precedence operator :-) -- Thanks again for review, Jim and Evan! Much appreciated! -jason > > >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From gohman at apple.com Wed Jan 12 16:12:21 2011 From: gohman at apple.com (Dan Gohman) Date: Wed, 12 Jan 2011 14:12:21 -0800 Subject: [llvm-commits] [patch] Only allow unnamed_addr in definitions In-Reply-To: <4D2DDDD5.60808@gmail.com> References: <4D2DDDD5.60808@gmail.com> Message-ID: <3B1982A0-9D4D-4226-984D-C505CE649A4F@apple.com> On Jan 12, 2011, at 8:59 AM, Rafael ?vila de Esp?ndola wrote: > The attached patches changes llvm to only accept unnamed_addr in definitions and clang to not produce them in declarations. > > I am not entirely convinced that we should do it. The reasons so far are > > *) There is nothing for LLVM to do with the knowledge that a declaration might be merged in the future > *) It would require us to define what the linker should do on mismatched declarations and definitions. The correct answer would probably be "ignore the bit in the declaration and keep the definition one", which also suggest that we shouldn't have this in declarations. LLVM optimizes this code to 0: extern const int x; extern const int y; int foo(void) { return &x == &y; } I guess this optimization would be invalid if the variables had the unnamed_addr attribute. So it would seem to apply to declarations as well as definitions. Dan From stoklund at 2pi.dk Wed Jan 12 16:28:48 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 12 Jan 2011 22:28:48 -0000 Subject: [llvm-commits] [llvm] r123333 - in /llvm/trunk: include/llvm/CodeGen/LiveIntervalAnalysis.h lib/CodeGen/VirtRegRewriter.cpp Message-ID: <20110112222848.C248A2A6C12C@llvm.org> Author: stoklund Date: Wed Jan 12 16:28:48 2011 New Revision: 123333 URL: http://llvm.org/viewvc/llvm-project?rev=123333&view=rev Log: Annotate VirtRegRewriter debug output with slot indexes. Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=123333&r1=123332&r2=123333&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Wed Jan 12 16:28:48 2011 @@ -171,6 +171,10 @@ r2iMap_.erase(I); } + SlotIndexes *getSlotIndexes() const { + return indexes_; + } + SlotIndex getZeroIndex() const { return indexes_->getZeroIndex(); } Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=123333&r1=123332&r2=123333&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Wed Jan 12 16:28:48 2011 @@ -1133,7 +1133,7 @@ << MF.getFunction()->getName() << "':\n"); DEBUG(dbgs() << "**** Machine Instrs (NOTE! Does not include spills and" " reloads!) ****\n"); - DEBUG(MF.dump()); + DEBUG(MF.print(dbgs(), LIs->getSlotIndexes())); // Spills - Keep track of which spilled values are available in physregs // so that we can choose to reuse the physregs instead of emitting @@ -1184,7 +1184,7 @@ } DEBUG(dbgs() << "**** Post Machine Instrs ****\n"); - DEBUG(MF.dump()); + DEBUG(MF.print(dbgs(), LIs->getSlotIndexes())); // Mark unused spill slots. MachineFrameInfo *MFI = MF.getFrameInfo(); From stoklund at 2pi.dk Wed Jan 12 16:28:51 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 12 Jan 2011 22:28:51 -0000 Subject: [llvm-commits] [llvm] r123334 - /llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Message-ID: <20110112222851.73ADE2A6C12D@llvm.org> Author: stoklund Date: Wed Jan 12 16:28:51 2011 New Revision: 123334 URL: http://llvm.org/viewvc/llvm-project?rev=123334&view=rev Log: Teach VirtRegRewriter to update slot indexes when erasing instructions. It was leaving dangling pointers in the slot index maps. Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=123334&r1=123333&r2=123334&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Wed Jan 12 16:28:51 2011 @@ -1056,6 +1056,7 @@ const TargetRegisterInfo *TRI; const TargetInstrInfo *TII; VirtRegMap *VRM; + LiveIntervals *LIs; BitVector AllocatableRegs; DenseMap DistanceMap; DenseMap > Slot2DbgValues; @@ -1068,6 +1069,11 @@ LiveIntervals* LIs); private: + void EraseInstr(MachineInstr *MI) { + VRM->RemoveMachineInstrFromMaps(MI); + LIs->RemoveMachineInstrFromMaps(MI); + MI->eraseFromParent(); + } bool OptimizeByUnfold2(unsigned VirtReg, int SS, MachineBasicBlock::iterator &MII, @@ -1123,11 +1129,12 @@ } bool LocalRewriter::runOnMachineFunction(MachineFunction &MF, VirtRegMap &vrm, - LiveIntervals* LIs) { + LiveIntervals* lis) { MRI = &MF.getRegInfo(); TRI = MF.getTarget().getRegisterInfo(); TII = MF.getTarget().getInstrInfo(); VRM = &vrm; + LIs = lis; AllocatableRegs = TRI->getAllocatableSet(MF); DEBUG(dbgs() << "\n**** Local spiller rewriting function '" << MF.getFunction()->getName() << "':\n"); @@ -1196,10 +1203,8 @@ MFI->RemoveStackObject(SS); for (unsigned j = 0, ee = DbgValues.size(); j != ee; ++j) { MachineInstr *DVMI = DbgValues[j]; - MachineBasicBlock *DVMBB = DVMI->getParent(); DEBUG(dbgs() << "Removing debug info referencing FI#" << SS << '\n'); - VRM->RemoveMachineInstrFromMaps(DVMI); - DVMBB->erase(DVMI); + EraseInstr(DVMI); } ++NumDSS; } @@ -1279,8 +1284,7 @@ VRM->transferRestorePts(&MI, NewMIs[0]); MII = MBB->insert(MII, NewMIs[0]); InvalidateKills(MI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(&MI); - MBB->erase(&MI); + EraseInstr(&MI); ++NumModRefUnfold; // Unfold next instructions that fold the same SS. @@ -1295,8 +1299,7 @@ VRM->transferRestorePts(&NextMI, NewMIs[0]); MBB->insert(NextMII, NewMIs[0]); InvalidateKills(NextMI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(&NextMI); - MBB->erase(&NextMI); + EraseInstr(&NextMI); ++NumModRefUnfold; // Skip over dbg_value instructions. while (NextMII != MBB->end() && NextMII->isDebugValue()) @@ -1423,8 +1426,7 @@ VRM->virtFolded(VirtReg, FoldedMI, VirtRegMap::isRef); MII = FoldedMI; InvalidateKills(MI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(&MI); - MBB->erase(&MI); + EraseInstr(&MI); return true; } } @@ -1530,14 +1532,11 @@ // Delete all 3 old instructions. InvalidateKills(*ReloadMI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(ReloadMI); - MBB->erase(ReloadMI); + EraseInstr(ReloadMI); InvalidateKills(*DefMI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(DefMI); - MBB->erase(DefMI); + EraseInstr(DefMI); InvalidateKills(MI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(&MI); - MBB->erase(&MI); + EraseInstr(&MI); // If NewReg was previously holding value of some SS, it's now clobbered. // This has to be done now because it's a physical register. When this @@ -1580,8 +1579,7 @@ bool CheckDef = PrevMII != MBB->begin(); if (CheckDef) --PrevMII; - VRM->RemoveMachineInstrFromMaps(LastStore); - MBB->erase(LastStore); + EraseInstr(LastStore); if (CheckDef) { // Look at defs of killed registers on the store. Mark the defs // as dead since the store has been deleted and they aren't @@ -1592,8 +1590,7 @@ MachineInstr *DeadDef = PrevMII; if (ReMatDefs.count(DeadDef) && !HasOtherDef) { // FIXME: This assumes a remat def does not have side effects. - VRM->RemoveMachineInstrFromMaps(DeadDef); - MBB->erase(DeadDef); + EraseInstr(DeadDef); ++NumDRM; } } @@ -1689,8 +1686,7 @@ LastUD->setIsDead(); break; } - VRM->RemoveMachineInstrFromMaps(LastUDMI); - MBB->erase(LastUDMI); + EraseInstr(LastUDMI); } else { LastUD->setIsKill(); RegKills.set(Reg); @@ -2203,8 +2199,7 @@ if (DeadStore) { DEBUG(dbgs() << "Removed dead store:\t" << *DeadStore); InvalidateKills(*DeadStore, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(DeadStore); - MBB->erase(DeadStore); + EraseInstr(DeadStore); MaybeDeadStores[PDSSlot] = NULL; ++NumDSE; } @@ -2332,8 +2327,7 @@ } InvalidateKills(MI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(&MI); - MBB->erase(&MI); + EraseInstr(&MI); Erased = true; goto ProcessNextInst; } @@ -2344,8 +2338,7 @@ TII->unfoldMemoryOperand(MF, &MI, PhysReg, false, false, NewMIs)){ MBB->insert(MII, NewMIs[0]); InvalidateKills(MI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(&MI); - MBB->erase(&MI); + EraseInstr(&MI); Erased = true; --NextMII; // backtrack to the unfolded instruction. BackTracked = true; @@ -2381,8 +2374,7 @@ MBB->insert(MII, NewStore); VRM->addSpillSlotUse(SS, NewStore); InvalidateKills(MI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(&MI); - MBB->erase(&MI); + EraseInstr(&MI); Erased = true; --NextMII; --NextMII; // backtrack to the unfolded instruction. @@ -2397,8 +2389,7 @@ // If we get here, the store is dead, nuke it now. DEBUG(dbgs() << "Removed dead store:\t" << *DeadStore); InvalidateKills(*DeadStore, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(DeadStore); - MBB->erase(DeadStore); + EraseInstr(DeadStore); if (!NewStore) ++NumDSE; } @@ -2475,8 +2466,7 @@ // Last def is now dead. TransferDeadness(MI.getOperand(1).getReg(), RegKills, KillOps); } - VRM->RemoveMachineInstrFromMaps(&MI); - MBB->erase(&MI); + EraseInstr(&MI); Erased = true; Spills.disallowClobberPhysReg(VirtReg); goto ProcessNextInst; @@ -2552,8 +2542,7 @@ ++NumDCE; DEBUG(dbgs() << "Removing now-noop copy: " << MI); InvalidateKills(MI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(&MI); - MBB->erase(&MI); + EraseInstr(&MI); Erased = true; UpdateKills(*LastStore, TRI, RegKills, KillOps); goto ProcessNextInst; @@ -2564,8 +2553,7 @@ // Delete dead instructions without side effects. if (!Erased && !BackTracked && isSafeToDelete(MI)) { InvalidateKills(MI, TRI, RegKills, KillOps); - VRM->RemoveMachineInstrFromMaps(&MI); - MBB->erase(&MI); + EraseInstr(&MI); Erased = true; } if (!Erased) From rafael.espindola at gmail.com Wed Jan 12 16:34:02 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Wed, 12 Jan 2011 17:34:02 -0500 Subject: [llvm-commits] [patch] Only allow unnamed_addr in definitions In-Reply-To: <3B1982A0-9D4D-4226-984D-C505CE649A4F@apple.com> References: <4D2DDDD5.60808@gmail.com> <3B1982A0-9D4D-4226-984D-C505CE649A4F@apple.com> Message-ID: <4D2E2C5A.4060604@gmail.com> On 11-01-12 5:12 PM, Dan Gohman wrote: > > On Jan 12, 2011, at 8:59 AM, Rafael ?vila de Esp?ndola wrote: > >> The attached patches changes llvm to only accept unnamed_addr in definitions and clang to not produce them in declarations. >> >> I am not entirely convinced that we should do it. The reasons so far are >> >> *) There is nothing for LLVM to do with the knowledge that a declaration might be merged in the future >> *) It would require us to define what the linker should do on mismatched declarations and definitions. The correct answer would probably be "ignore the bit in the declaration and keep the definition one", which also suggest that we shouldn't have this in declarations. > > LLVM optimizes this code to 0: > > extern const int x; > extern const int y; > > int foo(void) { > return&x ==&y; > } > > I guess this optimization would be invalid if the variables > had the unnamed_addr attribute. So it would seem to apply to > declarations as well as definitions. No, the optimization would be valid. The attribute says that the address is not relevant. If the code actually depends on the address, the code is invalid. > Dan > Cheers, Rafael From jasonwkim at google.com Wed Jan 12 16:34:48 2011 From: jasonwkim at google.com (Jason Kim) Date: Wed, 12 Jan 2011 14:34:48 -0800 Subject: [llvm-commits] [llvm] r123294 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/elf-movt.s In-Reply-To: <2F658FEE-4AD7-4075-B9AB-F2E2F4743F93@apple.com> References: <20110112001925.8DE2B2A6C12C@llvm.org> <2F658FEE-4AD7-4075-B9AB-F2E2F4743F93@apple.com> Message-ID: On Wed, Jan 12, 2011 at 1:56 PM, Jim Grosbach wrote: > Observations below. > > On Jan 11, 2011, at 4:19 PM, Jason W Kim wrote: > >> Author: jasonwkim >> Date: Tue Jan 11 18:19:25 2011 >> New Revision: 123294 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=123294&view=rev >> Log: >> 1. Support ELF pcrel relocations for movw/movt: >> ?R_ARM_MOVT_PREL and R_ARM_MOVW_PREL_NC. >> 2. Fix minor bug in ARMAsmPrinter - treat bitfield flag as a bitfield, not an enum. >> 3. Add support for 3 new elf section types (no-ops) >> >> >> >> Modified: >> ? ?llvm/trunk/lib/MC/ELFObjectWriter.cpp >> ? ?llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp >> ? ?llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp >> ? ?llvm/trunk/lib/Target/ARM/ARMFixupKinds.h >> ? ?llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp >> ? ?llvm/trunk/test/MC/ARM/elf-movt.s >> >> Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=123294&r1=123293&r2=123294&view=diff >> ============================================================================== >> --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) >> +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Tue Jan 11 18:19:25 2011 >> @@ -1268,6 +1268,9 @@ >> ? case ELF::SHT_NOTE: >> ? case ELF::SHT_NULL: >> ? case ELF::SHT_ARM_ATTRIBUTES: >> + ?case ELF::SHT_INIT_ARRAY: >> + ?case ELF::SHT_FINI_ARRAY: >> + ?case ELF::SHT_PREINIT_ARRAY: >> ? ? // Nothing to do. >> ? ? break; >> >> @@ -1490,6 +1493,13 @@ >> ? ? ? default: >> ? ? ? ? Type = ELF::R_ARM_CALL; break; >> ? ? ? } break; >> + ? ?case ARM::fixup_arm_movt_hi16: >> + ? ?case ARM::fixup_arm_movt_hi16_pcrel: >> + ? ? ?Type = ELF::R_ARM_MOVT_PREL; break; >> + ? ?case ARM::fixup_arm_movw_lo16: >> + ? ?case ARM::fixup_arm_movw_lo16_pcrel: >> + ? ? ?Type = ELF::R_ARM_MOVW_PREL_NC; break; >> + > > Should the pc-rel and non-pc-rel fixups really both map to the same relocation? That doesn't seem right. If they're the same, they shouldn't need distinct fixups. If they're different, they should map differently. Hmm, it does look funny - I have to track down the local test cases that caused me to code it thus - I'll look into it now. I fear it may be an artifact of emulating GNU as :-( > > The "break" statement should be on the following line, not the same line as the assignment. As a style thing, keeping the break on the same line is fine when the whole thing (including the case label) is on the same line for simple stuff. Once > there's already multiple lines, please separate them. The code above this gets very confusing due to this with nested switch statements and multiple breaks and such. Yes. Will do! > > >> ? ? } >> ? } else { >> ? ? switch ((unsigned)Fixup.getKind()) { >> >> Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=123294&r1=123293&r2=123294&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Tue Jan 11 18:19:25 2011 >> @@ -78,6 +78,8 @@ >> { "fixup_arm_thumb_bcc", ? ? 1, ? ? ? ? ? ? 8, ?MCFixupKindInfo::FKF_IsPCRel }, >> { "fixup_arm_movt_hi16", ? ? 0, ? ? ? ? ? ?16, ?0 }, >> { "fixup_arm_movw_lo16", ? ? 0, ? ? ? ? ? ?16, ?0 }, >> +{ "fixup_arm_movt_hi16_pcrel", 0, ? ? ? ? ?16, ?MCFixupKindInfo::FKF_IsPCRel }, >> +{ "fixup_arm_movw_lo16_pcrel", 0, ? ? ? ? ?16, ?MCFixupKindInfo::FKF_IsPCRel }, >> ? ? }; >> >> ? ? if (Kind < FirstTargetFixupKind) >> @@ -156,7 +158,9 @@ >> ? case FK_Data_4: >> ? ? return Value; >> ? case ARM::fixup_arm_movt_hi16: >> - ?case ARM::fixup_arm_movw_lo16: { >> + ?case ARM::fixup_arm_movw_lo16: >> + ?case ARM::fixup_arm_movt_hi16_pcrel: >> + ?case ARM::fixup_arm_movw_lo16_pcrel: { >> ? ? unsigned Hi4 = (Value & 0xF000) >> 12; >> ? ? unsigned Lo12 = Value & 0x0FFF; >> ? ? // inst{19-16} = Hi4; >> >> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=123294&r1=123293&r2=123294&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Tue Jan 11 18:19:25 2011 >> @@ -189,10 +189,10 @@ >> ? ? int64_t Imm = MO.getImm(); >> ? ? O << '#'; >> ? ? if ((Modifier && strcmp(Modifier, "lo16") == 0) || >> - ? ? ? ?(TF == ARMII::MO_LO16)) >> + ? ? ? ?(TF & ARMII::MO_LO16)) >> ? ? ? O << ":lower16:"; >> ? ? else if ((Modifier && strcmp(Modifier, "hi16") == 0) || >> - ? ? ? ? ? ? (TF == ARMII::MO_HI16)) >> + ? ? ? ? ? ? (TF & ARMII::MO_HI16)) > > As previously mentioned, you can just nuke the "Modifier" string compare. It's obsolete. > > The value-kinds look like masks, but they're not consistently used that way, unfortunately. If you want to change them to work additively instead of a one-variant-kind-per-symbolref, that's great and I completely agree it's worth doing, but it really should be a separate patch. Until then, this isn't correct. Please revert this bit. > >> ? ? ? O << ":upper16:"; >> ? ? O << Imm; >> ? ? break; >> >> Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=123294&r1=123293&r2=123294&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original) >> +++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Tue Jan 11 18:19:25 2011 >> @@ -74,6 +74,11 @@ >> ? fixup_arm_movt_hi16, // :upper16: >> ? fixup_arm_movw_lo16, // :lower16: >> >> + ?// It is possible to create an "immediate" that happens to be pcrel. > > I don't follow. Can you add an example? See below. > >> + ?// Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC >> + ?fixup_arm_movt_hi16_pcrel, // :upper16: >> + ?fixup_arm_movw_lo16_pcrel, // :lower16: >> + >> ? // Marker >> ? LastTargetFixupKind, >> ? NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind >> >> Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123294&r1=123293&r2=123294&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Jan 11 18:19:25 2011 >> @@ -626,6 +626,32 @@ >> ? return Binary; >> } >> >> +// FIXME: This routine needs to handle more MCExpr types >> +static const MCSymbolRefExpr *FindLHSymExpr(const MCExpr *E) { >> + ?// recurse left child until finding a MCSymbolRefExpr >> + ?switch (E->getKind()) { >> + ?case MCExpr::SymbolRef: >> + ? ?return cast(E); >> + ?case MCExpr::Binary: >> + ? ?return FindLHSymExpr(cast(E)->getLHS()); >> + ?default: >> + ? ?return NULL; >> + ?} >> +} >> + >> +// FIXME: This routine assumes that a binary >> +// expression will always result in a PCRel expression >> +// In reality, its only true if one or more subexpressions >> +// is itself a PCRel (i.e. "." in asm or some other pcrel construct) >> +// but this is good enough for now. > > This comment makes me very, very nervous. LLVM isn't always compiling ARM code as PIC. Can you help me understand why this is indeed good enough for now? The long story is quite convoluted, but the simple answer is that when the "immediate value" being loaded to a register via movw/movt is itself an expression that evaluates to a PCrelative value, GNU as creates two different relocation values for the MOVW/MOVT. This patch is to address that case. It just so happens that some 99.999% of such addresses, the expressions are of the form: movw r0, :lower16:Foo-(Bar+8) movt r0, :upper16:Foo-(Bar+8) For such expressions, GNU as creates two different relocations with the reloc tags R_ARM_MOVW_PREL_NC and R_ARM_MOVT_PREL, In normal cases where the expression is not a pcrel value, GNU as creates R_ARM_MOVT_ABS and R_ARM_MOVW_ABS_NC The reason why that hack routine works is because in nearly all cases, the expression winds up being a highly constrained Binary expression - LLVM also constrains this because MCValue has room for exactly two symbols (but in reality, the pcrel expression can be hairy beasts like Foo+Bar-Baz + 8 etc... but llvm doesn't seem to support this directly) > >> +static bool EvaluateAsPCRel(const MCExpr *Expr) { >> + ?switch (Expr->getKind()) { >> + ?case MCExpr::SymbolRef: return false; >> + ?case MCExpr::Binary: return true; >> + ?default: assert(0 && "Unexpected expression type"); >> + ?} >> +} >> + >> uint32_t ARMMCCodeEmitter:: >> getMovtImmOpValue(const MCInst &MI, unsigned OpIdx, >> ? ? ? ? ? ? ? ? ? SmallVectorImpl &Fixups) const { >> @@ -635,18 +661,27 @@ >> ? if (MO.isImm()) { >> ? ? return static_cast(MO.getImm()); >> ? } else if (const MCSymbolRefExpr *Expr = >> - ? ? ? ? ? ? dyn_cast(MO.getExpr())) { >> + ? ? ? ? ? ? FindLHSymExpr(MO.getExpr())) { >> + ? ?// FIXME: :lower16: and :upper16: should be applicable to >> + ? ?// to whole expression, not just symbolrefs >> + ? ?// Until that change takes place, this hack is required to >> + ? ?// generate working code. >> + ? ?const MCExpr *OrigExpr = MO.getExpr(); >> ? ? MCFixupKind Kind; >> ? ? switch (Expr->getKind()) { >> ? ? default: assert(0 && "Unsupported ARMFixup"); >> ? ? case MCSymbolRefExpr::VK_ARM_HI16: >> ? ? ? Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); >> + ? ? ?if (EvaluateAsPCRel(OrigExpr)) >> + ? ? ? ?Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel); >> ? ? ? break; >> ? ? case MCSymbolRefExpr::VK_ARM_LO16: >> ? ? ? Kind = MCFixupKind(ARM::fixup_arm_movw_lo16); >> + ? ? ?if (EvaluateAsPCRel(OrigExpr)) >> + ? ? ? ?Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel); >> ? ? ? break; >> ? ? } >> - ? ?Fixups.push_back(MCFixup::Create(0, Expr, Kind)); >> + ? ?Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind)); >> ? ? return 0; >> ? }; >> ? llvm_unreachable("Unsupported MCExpr type in MCOperand!"); >> >> Modified: llvm/trunk/test/MC/ARM/elf-movt.s >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123294&r1=123293&r2=123294&view=diff >> ============================================================================== >> --- llvm/trunk/test/MC/ARM/elf-movt.s (original) >> +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 18:19:25 2011 >> @@ -1,4 +1,6 @@ >> @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s >> +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ >> +@ RUN: ? ?elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s >> ? ? ? .syntax unified >> ? ? ? .text >> ? ? ? .globl ?barf >> @@ -12,3 +14,26 @@ >> @ ASM: ? ? ? ? ?movw ? ?r0, :lower16:GOT-(.LPC0_2+8) >> @ ASM-NEXT: ? ? movt ? ?r0, :upper16:GOT-(.LPC0_2+16) >> >> +@@ make sure that the text section fixups are sane too >> +@ OBJ: ? ? ? ? ? ? ? ? '.text' >> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_type', 0x00000001 >> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_flags', 0x00000006 >> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_addr', 0x00000000 >> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_offset', 0x00000034 >> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_size', 0x00000008 >> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_link', 0x00000000 >> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_info', 0x00000000 >> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_addralign', 0x00000004 >> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_entsize', 0x00000000 >> +@ OBJ-NEXT: ? ? ? ? ? ?'_section_data', 'f00f0fe3 ec0f4fe3' >> + >> +@ OBJ: ? ? ? ? ? ? ?Relocation 0x00000000 >> +@ OBJ-NEXT: ? ? ? ? 'r_offset', 0x00000000 >> +@ OBJ-NEXT: ? ? ? ? 'r_sym' >> +@ OBJ-NEXT: ? ? ? ? 'r_type', 0x0000002d >> + >> +@ OBJ: ? ? ? ? ? ? ?Relocation 0x00000001 >> +@ OBJ-NEXT: ? ? ? ? 'r_offset', 0x00000004 >> +@ OBJ-NEXT: ? ? ? ? 'r_sym' >> +@ OBJ-NEXT: ? ? ? ? 'r_type', 0x0000002e >> + >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From stoklund at 2pi.dk Wed Jan 12 16:37:49 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 12 Jan 2011 22:37:49 -0000 Subject: [llvm-commits] [llvm] r123335 - /llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Message-ID: <20110112223749.886102A6C12C@llvm.org> Author: stoklund Date: Wed Jan 12 16:37:49 2011 New Revision: 123335 URL: http://llvm.org/viewvc/llvm-project?rev=123335&view=rev Log: Sometimes, old virtual registers can linger on DBG_VALUE instructions. Make sure we don't crash in that case, but simply turn them into %noreg instead. Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=123335&r1=123334&r2=123335&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Wed Jan 12 16:37:49 2011 @@ -565,7 +565,8 @@ !TargetRegisterInfo::isVirtualRegister(Loc.getReg())) continue; unsigned VirtReg = Loc.getReg(); - if (VRM.isAssignedReg(VirtReg)) { + if (VRM.isAssignedReg(VirtReg) && + TargetRegisterInfo::isPhysicalRegister(VRM.getPhys(VirtReg))) { Loc.substPhysReg(VRM.getPhys(VirtReg), TRI); } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT) { // FIXME: Translate SubIdx to a stackslot offset. From stoklund at 2pi.dk Wed Jan 12 17:14:04 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 12 Jan 2011 23:14:04 -0000 Subject: [llvm-commits] [llvm] r123338 - /llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Message-ID: <20110112231404.96AD62A6C12C@llvm.org> Author: stoklund Date: Wed Jan 12 17:14:04 2011 New Revision: 123338 URL: http://llvm.org/viewvc/llvm-project?rev=123338&view=rev Log: Fix braino in dominator tree walk. Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=123338&r1=123337&r2=123338&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Wed Jan 12 17:14:04 2011 @@ -405,7 +405,7 @@ SlotIndex Start = Todo.pop_back_val(); MachineBasicBlock *MBB = LIS.getMBBFromIndex(Start); SlotIndex Stop = LIS.getMBBEndIdx(MBB); - LocMap::iterator I = locInts.find(Idx); + LocMap::iterator I = locInts.find(Start); // Limit to VNI's live range. bool ToEnd = true; From stoklund at 2pi.dk Wed Jan 12 17:14:07 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 12 Jan 2011 23:14:07 -0000 Subject: [llvm-commits] [llvm] r123339 - /llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Message-ID: <20110112231407.498682A6C12D@llvm.org> Author: stoklund Date: Wed Jan 12 17:14:07 2011 New Revision: 123339 URL: http://llvm.org/viewvc/llvm-project?rev=123339&view=rev Log: Don't emit a DBG_VALUE for a spill slot that the rewriter decided not to use after all. Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=123339&r1=123338&r2=123339&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Wed Jan 12 17:14:07 2011 @@ -568,7 +568,8 @@ if (VRM.isAssignedReg(VirtReg) && TargetRegisterInfo::isPhysicalRegister(VRM.getPhys(VirtReg))) { Loc.substPhysReg(VRM.getPhys(VirtReg), TRI); - } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT) { + } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT && + VRM.isSpillSlotUsed(VRM.getStackSlot(VirtReg))) { // FIXME: Translate SubIdx to a stackslot offset. Loc = MachineOperand::CreateFI(VRM.getStackSlot(VirtReg)); } else { From jason.w.kim.2009 at gmail.com Wed Jan 12 17:21:49 2011 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Wed, 12 Jan 2011 23:21:49 -0000 Subject: [llvm-commits] [llvm] r123340 - /llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Message-ID: <20110112232149.D28712A6C12C@llvm.org> Author: jasonwkim Date: Wed Jan 12 17:21:49 2011 New Revision: 123340 URL: http://llvm.org/viewvc/llvm-project?rev=123340&view=rev Log: JimG sez: "The value-kinds look like masks, but they're not consistently used that way, unfortunately. If you want to change them to work additively instead of a one-variant-kind-per-symbolref, that's great and I completely agree it's worth doing, but it really should be a separate patch. Until then, this isn't correct." So I am reverting this bit until a more opportune time. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=123340&r1=123339&r2=123340&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Jan 12 17:21:49 2011 @@ -189,10 +189,10 @@ int64_t Imm = MO.getImm(); O << '#'; if ((Modifier && strcmp(Modifier, "lo16") == 0) || - (TF & ARMII::MO_LO16)) + (TF == ARMII::MO_LO16)) O << ":lower16:"; else if ((Modifier && strcmp(Modifier, "hi16") == 0) || - (TF & ARMII::MO_HI16)) + (TF == ARMII::MO_HI16)) O << ":upper16:"; O << Imm; break; From jason.w.kim.2009 at gmail.com Wed Jan 12 17:25:02 2011 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Wed, 12 Jan 2011 23:25:02 -0000 Subject: [llvm-commits] [llvm] r123341 - /llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Message-ID: <20110112232502.D8A272A6C12C@llvm.org> Author: jasonwkim Date: Wed Jan 12 17:25:02 2011 New Revision: 123341 URL: http://llvm.org/viewvc/llvm-project?rev=123341&view=rev Log: Added clarifying comment Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=123341&r1=123340&r2=123341&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original) +++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Wed Jan 12 17:25:02 2011 @@ -75,6 +75,8 @@ fixup_arm_movw_lo16, // :lower16: // It is possible to create an "immediate" that happens to be pcrel. + // movw r0, :lower16:Foo-(Bar+8) and movt r0, :upper16:Foo-(Bar+8) + // result in different reloc tags than the above two. // Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC fixup_arm_movt_hi16_pcrel, // :upper16: fixup_arm_movw_lo16_pcrel, // :lower16: From gohman at apple.com Wed Jan 12 17:30:00 2011 From: gohman at apple.com (Dan Gohman) Date: Wed, 12 Jan 2011 15:30:00 -0800 Subject: [llvm-commits] [patch] Only allow unnamed_addr in definitions In-Reply-To: <4D2E2C5A.4060604@gmail.com> References: <4D2DDDD5.60808@gmail.com> <3B1982A0-9D4D-4226-984D-C505CE649A4F@apple.com> <4D2E2C5A.4060604@gmail.com> Message-ID: <1D24D20A-B50C-4E6D-AF18-F5E48C405DA4@apple.com> On Jan 12, 2011, at 2:34 PM, Rafael ?vila de Esp?ndola wrote: > On 11-01-12 5:12 PM, Dan Gohman wrote: >> >> On Jan 12, 2011, at 8:59 AM, Rafael ?vila de Esp?ndola wrote: >> >>> The attached patches changes llvm to only accept unnamed_addr in definitions and clang to not produce them in declarations. >>> >>> I am not entirely convinced that we should do it. The reasons so far are >>> >>> *) There is nothing for LLVM to do with the knowledge that a declaration might be merged in the future >>> *) It would require us to define what the linker should do on mismatched declarations and definitions. The correct answer would probably be "ignore the bit in the declaration and keep the definition one", which also suggest that we shouldn't have this in declarations. >> >> LLVM optimizes this code to 0: >> >> extern const int x; >> extern const int y; >> >> int foo(void) { >> return&x ==&y; >> } >> >> I guess this optimization would be invalid if the variables >> had the unnamed_addr attribute. So it would seem to apply to >> declarations as well as definitions. > > No, the optimization would be valid. The attribute says that the address is not relevant. If the code actually depends on the address, the code is invalid. Ok, I see now. I agree that it makes sense to put the flag on definitions only. Dan From stoklund at 2pi.dk Wed Jan 12 17:36:22 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 12 Jan 2011 23:36:22 -0000 Subject: [llvm-commits] [llvm] r123342 - in /llvm/trunk: lib/CodeGen/LiveDebugVariables.cpp test/CodeGen/X86/2010-05-26-DotDebugLoc.ll test/CodeGen/X86/2010-05-28-Crash.ll test/CodeGen/X86/dbg-value-range.ll Message-ID: <20110112233622.327C02A6C12C@llvm.org> Author: stoklund Date: Wed Jan 12 17:36:21 2011 New Revision: 123342 URL: http://llvm.org/viewvc/llvm-project?rev=123342&view=rev Log: Try again enabling LiveDebugVariables. Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll llvm/trunk/test/CodeGen/X86/dbg-value-range.ll Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=123342&r1=123341&r2=123342&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Wed Jan 12 17:36:21 2011 @@ -40,7 +40,7 @@ using namespace llvm; static cl::opt -EnableLDV("live-debug-variables", +EnableLDV("live-debug-variables", cl::init(true), cl::desc("Enable the live debug variables pass"), cl::Hidden); char LiveDebugVariables::ID = 0; Modified: llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll?rev=123342&r1=123341&r2=123342&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll Wed Jan 12 17:36:21 2011 @@ -61,6 +61,6 @@ ; CHECK-NEXT: .short 1 ; CHECK-NEXT: .byte 85 ; CHECK-NEXT: .quad Ltmp3 -; CHECK-NEXT: .quad Lfunc_end +; CHECK-NEXT: .quad Ltmp6 ; CHECK-NEXT: .short 1 ; CHECK-NEXT: .byte 83 Modified: llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll?rev=123342&r1=123341&r2=123342&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll (original) +++ llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll Wed Jan 12 17:36:21 2011 @@ -39,6 +39,6 @@ !13 = metadata !{i32 7, i32 0, metadata !14, null} !14 = metadata !{i32 524299, metadata !8, i32 6, i32 0} ; [ DW_TAG_lexical_block ] -;CHECK: DEBUG_VALUE: bar:x <- EBX+0 -;CHECK-NEXT:Ltmp -;CHECK-NEXT: DEBUG_VALUE: foo:y <- 1+0 +;CHECK: DEBUG_VALUE: bar:x <- E +;CHECK: Ltmp +;CHECK: DEBUG_VALUE: foo:y <- 1+0 Modified: llvm/trunk/test/CodeGen/X86/dbg-value-range.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-range.ll?rev=123342&r1=123341&r2=123342&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-value-range.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-value-range.ll Wed Jan 12 17:36:21 2011 @@ -1,5 +1,4 @@ ; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s -; XFAIL: * %struct.a = type { i32 } From jasonwkim at google.com Wed Jan 12 17:50:02 2011 From: jasonwkim at google.com (Jason Kim) Date: Wed, 12 Jan 2011 15:50:02 -0800 Subject: [llvm-commits] [llvm] r123294 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/elf-movt.s In-Reply-To: <2F658FEE-4AD7-4075-B9AB-F2E2F4743F93@apple.com> References: <20110112001925.8DE2B2A6C12C@llvm.org> <2F658FEE-4AD7-4075-B9AB-F2E2F4743F93@apple.com> Message-ID: On Wed, Jan 12, 2011 at 1:56 PM, Jim Grosbach wrote: > The value-kinds look like masks, but they're not consistently used that way, unfortunately. If you want to change them to work additively instead of a one-variant-kind-per-symbolref, that's great and I completely agree it's worth doing, but it really should be a separate patch. Until then, this isn't correct. Please revert this bit. Ah. It turns out that I left out a part of the patch that gives explicit value to the enums - I'll update the enum decls and fix. Thanks for catching this. Yikes! -jason From evan.cheng at apple.com Wed Jan 12 17:56:34 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Jan 2011 15:56:34 -0800 Subject: [llvm-commits] [llvm] r123294 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/elf-movt.s In-Reply-To: References: <20110112001925.8DE2B2A6C12C@llvm.org> <2F658FEE-4AD7-4075-B9AB-F2E2F4743F93@apple.com> Message-ID: On Jan 12, 2011, at 2:34 PM, Jason Kim wrote: >> > > The long story is quite convoluted, but the simple answer is that when > the "immediate value" being loaded to a register via movw/movt is > itself an expression that evaluates to a PCrelative value, > GNU as creates two different relocation values for the MOVW/MOVT. This > patch is to address that case. > It just so happens that some 99.999% of such addresses, the > expressions are of the form: > > movw r0, :lower16:Foo-(Bar+8) > movt r0, :upper16:Foo-(Bar+8) Is this what gcc generates? That can't be right. movw r0, :lower16:Foo-(Bar+8) shouldn't be mean movw r0, :lower16:(Foo-(Bar+8)) Evan > > For such expressions, GNU as creates two different relocations with > the reloc tags > R_ARM_MOVW_PREL_NC and R_ARM_MOVT_PREL, > In normal cases where the expression is not a pcrel value, GNU as > creates R_ARM_MOVT_ABS and R_ARM_MOVW_ABS_NC > > The reason why that hack routine works is because in nearly all cases, > the expression winds up being a highly constrained Binary expression - > LLVM also constrains this because MCValue has room for exactly two > symbols (but in reality, the pcrel expression can be hairy beasts like > Foo+Bar-Baz + 8 etc... but llvm doesn't seem to support this directly) > >> >>> +static bool EvaluateAsPCRel(const MCExpr *Expr) { >>> + switch (Expr->getKind()) { >>> + case MCExpr::SymbolRef: return false; >>> + case MCExpr::Binary: return true; >>> + default: assert(0 && "Unexpected expression type"); >>> + } >>> +} >>> + >>> uint32_t ARMMCCodeEmitter:: >>> getMovtImmOpValue(const MCInst &MI, unsigned OpIdx, >>> SmallVectorImpl &Fixups) const { >>> @@ -635,18 +661,27 @@ >>> if (MO.isImm()) { >>> return static_cast(MO.getImm()); >>> } else if (const MCSymbolRefExpr *Expr = >>> - dyn_cast(MO.getExpr())) { >>> + FindLHSymExpr(MO.getExpr())) { >>> + // FIXME: :lower16: and :upper16: should be applicable to >>> + // to whole expression, not just symbolrefs >>> + // Until that change takes place, this hack is required to >>> + // generate working code. >>> + const MCExpr *OrigExpr = MO.getExpr(); >>> MCFixupKind Kind; >>> switch (Expr->getKind()) { >>> default: assert(0 && "Unsupported ARMFixup"); >>> case MCSymbolRefExpr::VK_ARM_HI16: >>> Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); >>> + if (EvaluateAsPCRel(OrigExpr)) >>> + Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel); >>> break; >>> case MCSymbolRefExpr::VK_ARM_LO16: >>> Kind = MCFixupKind(ARM::fixup_arm_movw_lo16); >>> + if (EvaluateAsPCRel(OrigExpr)) >>> + Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel); >>> break; >>> } >>> - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); >>> + Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind)); >>> return 0; >>> }; >>> llvm_unreachable("Unsupported MCExpr type in MCOperand!"); >>> >>> Modified: llvm/trunk/test/MC/ARM/elf-movt.s >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123294&r1=123293&r2=123294&view=diff >>> ============================================================================== >>> --- llvm/trunk/test/MC/ARM/elf-movt.s (original) >>> +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 18:19:25 2011 >>> @@ -1,4 +1,6 @@ >>> @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s >>> +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ >>> +@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s >>> .syntax unified >>> .text >>> .globl barf >>> @@ -12,3 +14,26 @@ >>> @ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) >>> @ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) >>> >>> +@@ make sure that the text section fixups are sane too >>> +@ OBJ: '.text' >>> +@ OBJ-NEXT: 'sh_type', 0x00000001 >>> +@ OBJ-NEXT: 'sh_flags', 0x00000006 >>> +@ OBJ-NEXT: 'sh_addr', 0x00000000 >>> +@ OBJ-NEXT: 'sh_offset', 0x00000034 >>> +@ OBJ-NEXT: 'sh_size', 0x00000008 >>> +@ OBJ-NEXT: 'sh_link', 0x00000000 >>> +@ OBJ-NEXT: 'sh_info', 0x00000000 >>> +@ OBJ-NEXT: 'sh_addralign', 0x00000004 >>> +@ OBJ-NEXT: 'sh_entsize', 0x00000000 >>> +@ OBJ-NEXT: '_section_data', 'f00f0fe3 ec0f4fe3' >>> + >>> +@ OBJ: Relocation 0x00000000 >>> +@ OBJ-NEXT: 'r_offset', 0x00000000 >>> +@ OBJ-NEXT: 'r_sym' >>> +@ OBJ-NEXT: 'r_type', 0x0000002d >>> + >>> +@ OBJ: Relocation 0x00000001 >>> +@ OBJ-NEXT: 'r_offset', 0x00000004 >>> +@ OBJ-NEXT: 'r_sym' >>> +@ OBJ-NEXT: 'r_type', 0x0000002e >>> + >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From bigcheesegs at gmail.com Wed Jan 12 17:55:06 2011 From: bigcheesegs at gmail.com (Michael J. Spencer) Date: Wed, 12 Jan 2011 23:55:06 -0000 Subject: [llvm-commits] [llvm] r123345 - in /llvm/trunk: include/llvm/Support/PathV1.h lib/Support/PathV2.cpp Message-ID: <20110112235506.4C0122A6C12C@llvm.org> Author: mspencer Date: Wed Jan 12 17:55:06 2011 New Revision: 123345 URL: http://llvm.org/viewvc/llvm-project?rev=123345&view=rev Log: Support/Path: Deprecate PathV1::IsSymlink and replace all uses with PathV2::is_symlink. Modified: llvm/trunk/include/llvm/Support/PathV1.h llvm/trunk/lib/Support/PathV2.cpp Modified: llvm/trunk/include/llvm/Support/PathV1.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/PathV1.h?rev=123345&r1=123344&r2=123345&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/PathV1.h (original) +++ llvm/trunk/include/llvm/Support/PathV1.h Wed Jan 12 17:55:06 2011 @@ -394,7 +394,8 @@ /// existing symbolic link. /// @returns true if the pathname references an existing symlink. /// @brief Determines if the path is a symlink in the file system. - bool isSymLink() const; + LLVM_ATTRIBUTE_DEPRECATED(bool isSymLink() const, + LLVM_PATH_DEPRECATED_MSG(fs::is_symlink)); /// This function determines if the path name references a readable file /// or directory in the file system. This function checks for Modified: llvm/trunk/lib/Support/PathV2.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/PathV2.cpp?rev=123345&r1=123344&r2=123345&view=diff ============================================================================== --- llvm/trunk/lib/Support/PathV2.cpp (original) +++ llvm/trunk/lib/Support/PathV2.cpp Wed Jan 12 17:55:06 2011 @@ -660,6 +660,14 @@ return status.type() == file_type::symlink_file; } +error_code is_symlink(const Twine &path, bool &result) { + file_status st; + if (error_code ec = status(path, st)) + return ec; + result = is_symlink(st); + return success; +} + bool is_other(file_status status) { return exists(status) && !is_regular_file(status) && From gohman at apple.com Wed Jan 12 17:56:26 2011 From: gohman at apple.com (Dan Gohman) Date: Wed, 12 Jan 2011 23:56:26 -0000 Subject: [llvm-commits] [llvm] r123346 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20110112235626.D49B12A6C12C@llvm.org> Author: djg Date: Wed Jan 12 17:56:26 2011 New Revision: 123346 URL: http://llvm.org/viewvc/llvm-project?rev=123346&view=rev Log: Apply the patch from PR8958, which allows llc to get slightly further on the associated testcase before aborting. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=123346&r1=123345&r2=123346&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 12 17:56:26 2011 @@ -1378,7 +1378,8 @@ Result.getValueType(), Result, DAG.getValueType(SrcVT)); else - ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT); + ValRes = DAG.getZeroExtendInReg(Result, dl, + SrcVT.getVectorElementType()); Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. break; From jason.w.kim.2009 at gmail.com Wed Jan 12 18:07:51 2011 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Thu, 13 Jan 2011 00:07:51 -0000 Subject: [llvm-commits] [llvm] r123347 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20110113000752.0AC6D2A6C12C@llvm.org> Author: jasonwkim Date: Wed Jan 12 18:07:51 2011 New Revision: 123347 URL: http://llvm.org/viewvc/llvm-project?rev=123347&view=rev Log: Style clean up - break up the breaks. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=123347&r1=123346&r2=123347&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed Jan 12 18:07:51 2011 @@ -1480,26 +1480,34 @@ switch (Modifier) { default: llvm_unreachable("Unsupported Modifier"); case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_BASE_PREL; break; + Type = ELF::R_ARM_BASE_PREL; + break; case MCSymbolRefExpr::VK_ARM_TLSGD: - assert(0 && "unimplemented"); break; + assert(0 && "unimplemented"); + break; case MCSymbolRefExpr::VK_ARM_GOTTPOFF: Type = ELF::R_ARM_TLS_IE32; - } break; + break; + } + break; case ARM::fixup_arm_branch: switch (Modifier) { case MCSymbolRefExpr::VK_ARM_PLT: - Type = ELF::R_ARM_PLT32; break; + Type = ELF::R_ARM_PLT32; + break; default: - Type = ELF::R_ARM_CALL; break; - } break; + Type = ELF::R_ARM_CALL; + break; + } + break; case ARM::fixup_arm_movt_hi16: case ARM::fixup_arm_movt_hi16_pcrel: - Type = ELF::R_ARM_MOVT_PREL; break; + Type = ELF::R_ARM_MOVT_PREL; + break; case ARM::fixup_arm_movw_lo16: case ARM::fixup_arm_movw_lo16_pcrel: - Type = ELF::R_ARM_MOVW_PREL_NC; break; - + Type = ELF::R_ARM_MOVW_PREL_NC; + break; } } else { switch ((unsigned)Fixup.getKind()) { @@ -1508,18 +1516,25 @@ switch (Modifier) { default: llvm_unreachable("Unsupported Modifier"); break; case MCSymbolRefExpr::VK_ARM_GOT: - Type = ELF::R_ARM_GOT_BREL; break; + Type = ELF::R_ARM_GOT_BREL; + break; case MCSymbolRefExpr::VK_ARM_TLSGD: - Type = ELF::R_ARM_TLS_GD32; break; + Type = ELF::R_ARM_TLS_GD32; + break; case MCSymbolRefExpr::VK_ARM_TPOFF: - Type = ELF::R_ARM_TLS_LE32; break; + Type = ELF::R_ARM_TLS_LE32; + break; case MCSymbolRefExpr::VK_ARM_GOTTPOFF: - Type = ELF::R_ARM_TLS_IE32; break; + Type = ELF::R_ARM_TLS_IE32; + break; case MCSymbolRefExpr::VK_None: - Type = ELF::R_ARM_ABS32; break; + Type = ELF::R_ARM_ABS32; + break; case MCSymbolRefExpr::VK_ARM_GOTOFF: - Type = ELF::R_ARM_GOTOFF32; break; - } break; + Type = ELF::R_ARM_GOTOFF32; + break; + } + break; case ARM::fixup_arm_ldst_pcrel_12: case ARM::fixup_arm_pcrel_10: case ARM::fixup_arm_adr_pcrel_12: @@ -1527,15 +1542,19 @@ case ARM::fixup_arm_thumb_cb: case ARM::fixup_arm_thumb_cp: case ARM::fixup_arm_thumb_br: - assert(0 && "Unimplemented"); break; + assert(0 && "Unimplemented"); + break; case ARM::fixup_arm_branch: // FIXME: Differentiate between R_ARM_CALL and // R_ARM_JUMP24 (latter used for conditional jumps) - Type = ELF::R_ARM_CALL; break; - case ARM::fixup_arm_movt_hi16: - Type = ELF::R_ARM_MOVT_ABS; break; + Type = ELF::R_ARM_CALL; + break; + case ARM::fixup_arm_movt_hi16: + Type = ELF::R_ARM_MOVT_ABS; + break; case ARM::fixup_arm_movw_lo16: - Type = ELF::R_ARM_MOVW_ABS_NC; break; + Type = ELF::R_ARM_MOVW_ABS_NC; + break; } } From jasonwkim at google.com Wed Jan 12 18:23:59 2011 From: jasonwkim at google.com (Jason Kim) Date: Wed, 12 Jan 2011 16:23:59 -0800 Subject: [llvm-commits] [llvm] r123294 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/elf-movt.s In-Reply-To: References: <20110112001925.8DE2B2A6C12C@llvm.org> <2F658FEE-4AD7-4075-B9AB-F2E2F4743F93@apple.com> Message-ID: On Wed, Jan 12, 2011 at 3:56 PM, Evan Cheng wrote: > > On Jan 12, 2011, at 2:34 PM, Jason Kim wrote: > >>> >> >> The long story is quite convoluted, but the simple answer is that when >> the "immediate value" being loaded to a register via movw/movt is >> itself an expression that evaluates to a PCrelative value, >> GNU as creates two different relocation values for the MOVW/MOVT. This >> patch is to address that case. >> It just so happens that some 99.999% of such addresses, the >> expressions are of the form: >> >> movw r0, :lower16:Foo-(Bar+8) >> movt ?r0, :upper16:Foo-(Bar+8) > > Is this what gcc generates? That can't be right. > > movw r0, :lower16:Foo-(Bar+8) > shouldn't be mean > movw r0, :lower16:(Foo-(Bar+8)) Yes canonically speaking the latter is the least confusing of the two - GNU as accepts both AFAIK. -Jason > > Evan > >> >> For such expressions, GNU as creates two different relocations with >> the reloc tags >> R_ARM_MOVW_PREL_NC and ?R_ARM_MOVT_PREL, >> In normal cases where the expression is not a pcrel value, GNU as >> creates R_ARM_MOVT_ABS and R_ARM_MOVW_ABS_NC >> >> The reason why that hack routine works is because in nearly all cases, >> the expression winds up being a highly constrained Binary expression - >> LLVM also constrains this because MCValue has room for exactly two >> symbols (but in reality, the pcrel expression can be hairy beasts like >> Foo+Bar-Baz + 8 etc... but llvm doesn't seem to support this directly) >> >>> >>>> +static bool EvaluateAsPCRel(const MCExpr *Expr) { >>>> + ?switch (Expr->getKind()) { >>>> + ?case MCExpr::SymbolRef: return false; >>>> + ?case MCExpr::Binary: return true; >>>> + ?default: assert(0 && "Unexpected expression type"); >>>> + ?} >>>> +} >>>> + >>>> uint32_t ARMMCCodeEmitter:: >>>> getMovtImmOpValue(const MCInst &MI, unsigned OpIdx, >>>> ? ? ? ? ? ? ? ? ? SmallVectorImpl &Fixups) const { >>>> @@ -635,18 +661,27 @@ >>>> ? if (MO.isImm()) { >>>> ? ? return static_cast(MO.getImm()); >>>> ? } else if (const MCSymbolRefExpr *Expr = >>>> - ? ? ? ? ? ? dyn_cast(MO.getExpr())) { >>>> + ? ? ? ? ? ? FindLHSymExpr(MO.getExpr())) { >>>> + ? ?// FIXME: :lower16: and :upper16: should be applicable to >>>> + ? ?// to whole expression, not just symbolrefs >>>> + ? ?// Until that change takes place, this hack is required to >>>> + ? ?// generate working code. >>>> + ? ?const MCExpr *OrigExpr = MO.getExpr(); >>>> ? ? MCFixupKind Kind; >>>> ? ? switch (Expr->getKind()) { >>>> ? ? default: assert(0 && "Unsupported ARMFixup"); >>>> ? ? case MCSymbolRefExpr::VK_ARM_HI16: >>>> ? ? ? Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); >>>> + ? ? ?if (EvaluateAsPCRel(OrigExpr)) >>>> + ? ? ? ?Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel); >>>> ? ? ? break; >>>> ? ? case MCSymbolRefExpr::VK_ARM_LO16: >>>> ? ? ? Kind = MCFixupKind(ARM::fixup_arm_movw_lo16); >>>> + ? ? ?if (EvaluateAsPCRel(OrigExpr)) >>>> + ? ? ? ?Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel); >>>> ? ? ? break; >>>> ? ? } >>>> - ? ?Fixups.push_back(MCFixup::Create(0, Expr, Kind)); >>>> + ? ?Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind)); >>>> ? ? return 0; >>>> ? }; >>>> ? llvm_unreachable("Unsupported MCExpr type in MCOperand!"); >>>> >>>> Modified: llvm/trunk/test/MC/ARM/elf-movt.s >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123294&r1=123293&r2=123294&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/test/MC/ARM/elf-movt.s (original) >>>> +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 18:19:25 2011 >>>> @@ -1,4 +1,6 @@ >>>> @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s >>>> +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ >>>> +@ RUN: ? ?elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s >>>> ? ? ? .syntax unified >>>> ? ? ? .text >>>> ? ? ? .globl ?barf >>>> @@ -12,3 +14,26 @@ >>>> @ ASM: ? ? ? ? ?movw ? ?r0, :lower16:GOT-(.LPC0_2+8) >>>> @ ASM-NEXT: ? ? movt ? ?r0, :upper16:GOT-(.LPC0_2+16) >>>> >>>> +@@ make sure that the text section fixups are sane too >>>> +@ OBJ: ? ? ? ? ? ? ? ? '.text' >>>> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_type', 0x00000001 >>>> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_flags', 0x00000006 >>>> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_addr', 0x00000000 >>>> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_offset', 0x00000034 >>>> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_size', 0x00000008 >>>> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_link', 0x00000000 >>>> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_info', 0x00000000 >>>> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_addralign', 0x00000004 >>>> +@ OBJ-NEXT: ? ? ? ? ? ?'sh_entsize', 0x00000000 >>>> +@ OBJ-NEXT: ? ? ? ? ? ?'_section_data', 'f00f0fe3 ec0f4fe3' >>>> + >>>> +@ OBJ: ? ? ? ? ? ? ?Relocation 0x00000000 >>>> +@ OBJ-NEXT: ? ? ? ? 'r_offset', 0x00000000 >>>> +@ OBJ-NEXT: ? ? ? ? 'r_sym' >>>> +@ OBJ-NEXT: ? ? ? ? 'r_type', 0x0000002d >>>> + >>>> +@ OBJ: ? ? ? ? ? ? ?Relocation 0x00000001 >>>> +@ OBJ-NEXT: ? ? ? ? 'r_offset', 0x00000004 >>>> +@ OBJ-NEXT: ? ? ? ? 'r_sym' >>>> +@ OBJ-NEXT: ? ? ? ? 'r_type', 0x0000002e >>>> + >>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From jason.w.kim.2009 at gmail.com Wed Jan 12 18:27:00 2011 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Thu, 13 Jan 2011 00:27:00 -0000 Subject: [llvm-commits] [llvm] r123350 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110113002700.3950F2A6C12C@llvm.org> Author: jasonwkim Date: Wed Jan 12 18:27:00 2011 New Revision: 123350 URL: http://llvm.org/viewvc/llvm-project?rev=123350&view=rev Log: Change call to Error() to assert() Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123350&r1=123349&r2=123350&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jan 12 18:27:00 2011 @@ -902,10 +902,7 @@ RefKind = MCSymbolRefExpr::VK_None; // :lower16: and :upper16: modifiers - if (getLexer().isNot(AsmToken::Colon)) { - Error(Parser.getTok().getLoc(), "expected :"); - return true; - } + assert(getLexer().is(AsmToken::Colon) && "expected a :"); Parser.Lex(); // Eat ':' if (getLexer().isNot(AsmToken::Identifier)) { From stoklund at 2pi.dk Wed Jan 12 18:57:35 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 13 Jan 2011 00:57:35 -0000 Subject: [llvm-commits] [llvm] r123351 - /llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Message-ID: <20110113005735.CE4DE2A6C12C@llvm.org> Author: stoklund Date: Wed Jan 12 18:57:35 2011 New Revision: 123351 URL: http://llvm.org/viewvc/llvm-project?rev=123351&view=rev Log: Add missing space in debug output Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=123351&r1=123350&r2=123351&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Wed Jan 12 18:57:35 2011 @@ -203,7 +203,7 @@ if (Indexes) OS << '\t'; OS << " Live Ins:"; for (livein_iterator I = livein_begin(),E = livein_end(); I != E; ++I) - OS << PrintReg(*I, TRI); + OS << ' ' << PrintReg(*I, TRI); OS << '\n'; } // Print the preds of this block according to the CFG. From evan.cheng at apple.com Wed Jan 12 19:08:08 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Jan 2011 17:08:08 -0800 Subject: [llvm-commits] [llvm] r123294 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/elf-movt.s In-Reply-To: References: <20110112001925.8DE2B2A6C12C@llvm.org> <2F658FEE-4AD7-4075-B9AB-F2E2F4743F93@apple.com> Message-ID: <01884B9F-8311-4254-AB9D-EE0C86707835@apple.com> On Jan 12, 2011, at 4:23 PM, Jason Kim wrote: > On Wed, Jan 12, 2011 at 3:56 PM, Evan Cheng wrote: >> >> On Jan 12, 2011, at 2:34 PM, Jason Kim wrote: >> >>>> >>> >>> The long story is quite convoluted, but the simple answer is that when >>> the "immediate value" being loaded to a register via movw/movt is >>> itself an expression that evaluates to a PCrelative value, >>> GNU as creates two different relocation values for the MOVW/MOVT. This >>> patch is to address that case. >>> It just so happens that some 99.999% of such addresses, the >>> expressions are of the form: >>> >>> movw r0, :lower16:Foo-(Bar+8) >>> movt r0, :upper16:Foo-(Bar+8) >> >> Is this what gcc generates? That can't be right. >> >> movw r0, :lower16:Foo-(Bar+8) >> shouldn't be mean >> movw r0, :lower16:(Foo-(Bar+8)) > > Yes canonically speaking the latter is the least confusing of the two ok > - GNU as accepts both AFAIK. I hope it generates different code for the two cases. Otherwise, it's a bug in my opinion. Evan > -Jason > >> >> Evan >> >>> >>> For such expressions, GNU as creates two different relocations with >>> the reloc tags >>> R_ARM_MOVW_PREL_NC and R_ARM_MOVT_PREL, >>> In normal cases where the expression is not a pcrel value, GNU as >>> creates R_ARM_MOVT_ABS and R_ARM_MOVW_ABS_NC >>> >>> The reason why that hack routine works is because in nearly all cases, >>> the expression winds up being a highly constrained Binary expression - >>> LLVM also constrains this because MCValue has room for exactly two >>> symbols (but in reality, the pcrel expression can be hairy beasts like >>> Foo+Bar-Baz + 8 etc... but llvm doesn't seem to support this directly) >>> >>>> >>>>> +static bool EvaluateAsPCRel(const MCExpr *Expr) { >>>>> + switch (Expr->getKind()) { >>>>> + case MCExpr::SymbolRef: return false; >>>>> + case MCExpr::Binary: return true; >>>>> + default: assert(0 && "Unexpected expression type"); >>>>> + } >>>>> +} >>>>> + >>>>> uint32_t ARMMCCodeEmitter:: >>>>> getMovtImmOpValue(const MCInst &MI, unsigned OpIdx, >>>>> SmallVectorImpl &Fixups) const { >>>>> @@ -635,18 +661,27 @@ >>>>> if (MO.isImm()) { >>>>> return static_cast(MO.getImm()); >>>>> } else if (const MCSymbolRefExpr *Expr = >>>>> - dyn_cast(MO.getExpr())) { >>>>> + FindLHSymExpr(MO.getExpr())) { >>>>> + // FIXME: :lower16: and :upper16: should be applicable to >>>>> + // to whole expression, not just symbolrefs >>>>> + // Until that change takes place, this hack is required to >>>>> + // generate working code. >>>>> + const MCExpr *OrigExpr = MO.getExpr(); >>>>> MCFixupKind Kind; >>>>> switch (Expr->getKind()) { >>>>> default: assert(0 && "Unsupported ARMFixup"); >>>>> case MCSymbolRefExpr::VK_ARM_HI16: >>>>> Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); >>>>> + if (EvaluateAsPCRel(OrigExpr)) >>>>> + Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel); >>>>> break; >>>>> case MCSymbolRefExpr::VK_ARM_LO16: >>>>> Kind = MCFixupKind(ARM::fixup_arm_movw_lo16); >>>>> + if (EvaluateAsPCRel(OrigExpr)) >>>>> + Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel); >>>>> break; >>>>> } >>>>> - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); >>>>> + Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind)); >>>>> return 0; >>>>> }; >>>>> llvm_unreachable("Unsupported MCExpr type in MCOperand!"); >>>>> >>>>> Modified: llvm/trunk/test/MC/ARM/elf-movt.s >>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123294&r1=123293&r2=123294&view=diff >>>>> ============================================================================== >>>>> --- llvm/trunk/test/MC/ARM/elf-movt.s (original) >>>>> +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 18:19:25 2011 >>>>> @@ -1,4 +1,6 @@ >>>>> @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s >>>>> +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ >>>>> +@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s >>>>> .syntax unified >>>>> .text >>>>> .globl barf >>>>> @@ -12,3 +14,26 @@ >>>>> @ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) >>>>> @ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) >>>>> >>>>> +@@ make sure that the text section fixups are sane too >>>>> +@ OBJ: '.text' >>>>> +@ OBJ-NEXT: 'sh_type', 0x00000001 >>>>> +@ OBJ-NEXT: 'sh_flags', 0x00000006 >>>>> +@ OBJ-NEXT: 'sh_addr', 0x00000000 >>>>> +@ OBJ-NEXT: 'sh_offset', 0x00000034 >>>>> +@ OBJ-NEXT: 'sh_size', 0x00000008 >>>>> +@ OBJ-NEXT: 'sh_link', 0x00000000 >>>>> +@ OBJ-NEXT: 'sh_info', 0x00000000 >>>>> +@ OBJ-NEXT: 'sh_addralign', 0x00000004 >>>>> +@ OBJ-NEXT: 'sh_entsize', 0x00000000 >>>>> +@ OBJ-NEXT: '_section_data', 'f00f0fe3 ec0f4fe3' >>>>> + >>>>> +@ OBJ: Relocation 0x00000000 >>>>> +@ OBJ-NEXT: 'r_offset', 0x00000000 >>>>> +@ OBJ-NEXT: 'r_sym' >>>>> +@ OBJ-NEXT: 'r_type', 0x0000002d >>>>> + >>>>> +@ OBJ: Relocation 0x00000001 >>>>> +@ OBJ-NEXT: 'r_offset', 0x00000004 >>>>> +@ OBJ-NEXT: 'r_sym' >>>>> +@ OBJ-NEXT: 'r_type', 0x0000002e >>>>> + >>>>> >>>>> >>>>> _______________________________________________ >>>>> llvm-commits mailing list >>>>> llvm-commits at cs.uiuc.edu >>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>> >>>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> From gohman at apple.com Wed Jan 12 19:06:51 2011 From: gohman at apple.com (Dan Gohman) Date: Thu, 13 Jan 2011 01:06:51 -0000 Subject: [llvm-commits] [llvm] r123352 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20110113010651.DCFB12A6C12C@llvm.org> Author: djg Date: Wed Jan 12 19:06:51 2011 New Revision: 123352 URL: http://llvm.org/viewvc/llvm-project?rev=123352&view=rev Log: Fix r123346 to handle scalar types too. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=123352&r1=123351&r2=123352&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Jan 12 19:06:51 2011 @@ -1378,8 +1378,7 @@ Result.getValueType(), Result, DAG.getValueType(SrcVT)); else - ValRes = DAG.getZeroExtendInReg(Result, dl, - SrcVT.getVectorElementType()); + ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes. Tmp2 = LegalizeOp(Result.getValue(1)); // Relegalize new nodes. break; From enderby at apple.com Wed Jan 12 19:07:01 2011 From: enderby at apple.com (Kevin Enderby) Date: Thu, 13 Jan 2011 01:07:01 -0000 Subject: [llvm-commits] [llvm] r123353 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110113010701.561972A6C12C@llvm.org> Author: enderby Date: Wed Jan 12 19:07:01 2011 New Revision: 123353 URL: http://llvm.org/viewvc/llvm-project?rev=123353&view=rev Log: Add a FIXME and two asserts for now in the ARMAsmParser when it sees .code 16 or .code 32 if the TargetMachine's isThumb() boolean does not match. The correct fix is to switch ARM subtargets at that point and is tracked by rdar://8856789 which is bigger task. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123353&r1=123352&r2=123353&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Wed Jan 12 19:07:01 2011 @@ -1351,10 +1351,20 @@ return Error(Parser.getTok().getLoc(), "unexpected token in directive"); Parser.Lex(); - if (Val == 16) + // FIXME: We need to be able switch subtargets at this point so that + // MatchInstructionImpl() will work when it gets the AvailableFeatures which + // includes Feature_IsThumb or not to match the right instructions. This is + // blocked on the FIXME in llvm-mc.cpp when creating the TargetMachine. + if (Val == 16){ + assert(TM.getSubtarget().isThumb() && + "switching between arm/thumb not yet suppported via .code 16)"); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16); - else + } + else{ + assert(!TM.getSubtarget().isThumb() && + "switching between thumb/arm not yet suppported via .code 32)"); getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32); + } return false; } From rafael.espindola at gmail.com Wed Jan 12 19:30:31 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 13 Jan 2011 01:30:31 -0000 Subject: [llvm-commits] [llvm] r123358 - in /llvm/trunk: lib/AsmParser/LLParser.cpp lib/AsmParser/LLParser.h lib/VMCore/Verifier.cpp test/Assembler/declare-unnamed-addr.ll test/Assembler/external-unnamed-addr.ll unittests/VMCore/VerifierTest.cpp Message-ID: <20110113013031.25F2A2A6C12C@llvm.org> Author: rafael Date: Wed Jan 12 19:30:30 2011 New Revision: 123358 URL: http://llvm.org/viewvc/llvm-project?rev=123358&view=rev Log: Reject uses of unnamed_addr in declarations. Added: llvm/trunk/test/Assembler/declare-unnamed-addr.ll llvm/trunk/test/Assembler/external-unnamed-addr.ll Modified: llvm/trunk/lib/AsmParser/LLParser.cpp llvm/trunk/lib/AsmParser/LLParser.h llvm/trunk/lib/VMCore/Verifier.cpp llvm/trunk/unittests/VMCore/VerifierTest.cpp Modified: llvm/trunk/lib/AsmParser/LLParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=123358&r1=123357&r2=123358&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.cpp (original) +++ llvm/trunk/lib/AsmParser/LLParser.cpp Wed Jan 12 19:30:30 2011 @@ -694,12 +694,14 @@ unsigned Visibility) { unsigned AddrSpace; bool ThreadLocal, IsConstant, UnnamedAddr; + LocTy UnnamedAddrLoc; LocTy TyLoc; PATypeHolder Ty(Type::getVoidTy(Context)); if (ParseOptionalToken(lltok::kw_thread_local, ThreadLocal) || ParseOptionalAddrSpace(AddrSpace) || - ParseOptionalToken(lltok::kw_unnamed_addr, UnnamedAddr) || + ParseOptionalToken(lltok::kw_unnamed_addr, UnnamedAddr, + &UnnamedAddrLoc) || ParseGlobalType(IsConstant) || ParseType(Ty, TyLoc)) return true; @@ -714,6 +716,9 @@ return true; } + if (!Init && UnnamedAddr) + return Error(UnnamedAddrLoc, "only definitions can have unnamed_addr"); + if (Ty->isFunctionTy() || Ty->isLabelTy()) return Error(TyLoc, "invalid type for global variable"); @@ -2669,6 +2674,7 @@ unsigned Visibility, RetAttrs; bool UnnamedAddr; + LocTy UnnamedAddrLoc; CallingConv::ID CC; PATypeHolder RetType(Type::getVoidTy(Context)); LocTy RetTypeLoc = Lex.getLoc(); @@ -2676,10 +2682,14 @@ ParseOptionalVisibility(Visibility) || ParseOptionalCallingConv(CC) || ParseOptionalAttrs(RetAttrs, 1) || - ParseOptionalToken(lltok::kw_unnamed_addr, UnnamedAddr) || + ParseOptionalToken(lltok::kw_unnamed_addr, UnnamedAddr, + &UnnamedAddrLoc) || ParseType(RetType, RetTypeLoc, true /*void allowed*/)) return true; + if (!isDefine && UnnamedAddr) + return Error(UnnamedAddrLoc, "only definitions can have unnamed_addr"); + // Verify that the linkage is ok. switch ((GlobalValue::LinkageTypes)Linkage) { case GlobalValue::ExternalLinkage: Modified: llvm/trunk/lib/AsmParser/LLParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.h?rev=123358&r1=123357&r2=123358&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLParser.h (original) +++ llvm/trunk/lib/AsmParser/LLParser.h Wed Jan 12 19:30:30 2011 @@ -162,10 +162,12 @@ Lex.Lex(); return true; } - bool ParseOptionalToken(lltok::Kind T, bool &Present) { + bool ParseOptionalToken(lltok::Kind T, bool &Present, LocTy *Loc = 0) { if (Lex.getKind() != T) { Present = false; } else { + if (Loc) + *Loc = Lex.getLoc(); Lex.Lex(); Present = true; } Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=123358&r1=123357&r2=123358&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Wed Jan 12 19:30:30 2011 @@ -469,6 +469,8 @@ Assert1(GV.hasExternalLinkage() || GV.hasDLLImportLinkage() || GV.hasExternalWeakLinkage(), "invalid linkage type for global declaration", &GV); + Assert1(!GV.hasUnnamedAddr(), "only definitions can have unnamed_addr", + &GV); } visitGlobalValue(GV); @@ -725,6 +727,7 @@ Assert1(F.hasExternalLinkage() || F.hasDLLImportLinkage() || F.hasExternalWeakLinkage(), "invalid linkage type for function declaration", &F); + Assert1(!F.hasUnnamedAddr(), "only definitions can have unnamed_addr", &F); } else { // Verify that this function (which has a body) is not named "llvm.*". It // is not legal to define intrinsics. Added: llvm/trunk/test/Assembler/declare-unnamed-addr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/declare-unnamed-addr.ll?rev=123358&view=auto ============================================================================== --- llvm/trunk/test/Assembler/declare-unnamed-addr.ll (added) +++ llvm/trunk/test/Assembler/declare-unnamed-addr.ll Wed Jan 12 19:30:30 2011 @@ -0,0 +1,8 @@ +; RUN: not llvm-as %s -o /dev/null 2>%t +; RUN: FileCheck -input-file=%t %s + +declare unnamed_addr i32 @zed() + +// CHECK: error: only definitions can have unnamed_addr +// CHECK: declare unnamed_addr i32 @zed() +// CHECK: ^ Added: llvm/trunk/test/Assembler/external-unnamed-addr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/external-unnamed-addr.ll?rev=123358&view=auto ============================================================================== --- llvm/trunk/test/Assembler/external-unnamed-addr.ll (added) +++ llvm/trunk/test/Assembler/external-unnamed-addr.ll Wed Jan 12 19:30:30 2011 @@ -0,0 +1,8 @@ +; RUN: not llvm-as %s -o /dev/null 2>%t +; RUN: FileCheck -input-file=%t %s + + at foo = external unnamed_addr global i8* + +// CHECK: error: only definitions can have unnamed_addr +// CHECK: @foo = external unnamed_addr global i8* +// CHECK: ^ Modified: llvm/trunk/unittests/VMCore/VerifierTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/VerifierTest.cpp?rev=123358&r1=123357&r2=123358&view=diff ============================================================================== --- llvm/trunk/unittests/VMCore/VerifierTest.cpp (original) +++ llvm/trunk/unittests/VMCore/VerifierTest.cpp Wed Jan 12 19:30:30 2011 @@ -61,5 +61,31 @@ EXPECT_TRUE(StringRef(Error).startswith("Alias cannot have unnamed_addr")); } +TEST(VerifierTest, ExternalUnnamedAddr) { + LLVMContext &C = getGlobalContext(); + Module M("M", C); + const Type *Ty = Type::getInt8Ty(C); + GlobalVariable *GV = new GlobalVariable(M, Ty, true, + GlobalValue::ExternalLinkage, + NULL, "foo"); + GV->setUnnamedAddr(true); + std::string Error; + EXPECT_TRUE(verifyModule(M, ReturnStatusAction, &Error)); + EXPECT_TRUE(StringRef(Error) + .startswith("only definitions can have unnamed_addr")); +} + +TEST(VerifierTest, DeclarationUnnamedAddr) { + LLVMContext &C = getGlobalContext(); + Module M("M", C); + FunctionType *FTy = FunctionType::get(Type::getVoidTy(C), /*isVarArg=*/false); + Function *F = Function::Create(FTy, GlobalValue::ExternalLinkage, + "foo", &M); + F->setUnnamedAddr(true); + std::string Error; + EXPECT_TRUE(verifyModule(M, ReturnStatusAction, &Error)); + EXPECT_TRUE(StringRef(Error) + .startswith("only definitions can have unnamed_addr")); +} } } From evan.cheng at apple.com Wed Jan 12 21:14:26 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 12 Jan 2011 19:14:26 -0800 Subject: [llvm-commits] [llvm] r123294 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/elf-movt.s In-Reply-To: <01884B9F-8311-4254-AB9D-EE0C86707835@apple.com> References: <20110112001925.8DE2B2A6C12C@llvm.org> <2F658FEE-4AD7-4075-B9AB-F2E2F4743F93@apple.com> <01884B9F-8311-4254-AB9D-EE0C86707835@apple.com> Message-ID: <851733C9-09DF-4DB9-96A2-81CB5D7A7C08@apple.com> On Jan 12, 2011, at 5:08 PM, Evan Cheng wrote: > > On Jan 12, 2011, at 4:23 PM, Jason Kim wrote: > >> On Wed, Jan 12, 2011 at 3:56 PM, Evan Cheng wrote: >>> >>> On Jan 12, 2011, at 2:34 PM, Jason Kim wrote: >>> >>>>> >>>> >>>> The long story is quite convoluted, but the simple answer is that when >>>> the "immediate value" being loaded to a register via movw/movt is >>>> itself an expression that evaluates to a PCrelative value, >>>> GNU as creates two different relocation values for the MOVW/MOVT. This >>>> patch is to address that case. >>>> It just so happens that some 99.999% of such addresses, the >>>> expressions are of the form: >>>> >>>> movw r0, :lower16:Foo-(Bar+8) >>>> movt r0, :upper16:Foo-(Bar+8) >>> >>> Is this what gcc generates? That can't be right. >>> >>> movw r0, :lower16:Foo-(Bar+8) >>> shouldn't be mean >>> movw r0, :lower16:(Foo-(Bar+8)) >> >> Yes canonically speaking the latter is the least confusing of the two > > ok > >> - GNU as accepts both AFAIK. > > I hope it generates different code for the two cases. Otherwise, it's a bug in my opinion. Nevermind. They are identical. Evan > > Evan > >> -Jason >> >>> >>> Evan >>> >>>> >>>> For such expressions, GNU as creates two different relocations with >>>> the reloc tags >>>> R_ARM_MOVW_PREL_NC and R_ARM_MOVT_PREL, >>>> In normal cases where the expression is not a pcrel value, GNU as >>>> creates R_ARM_MOVT_ABS and R_ARM_MOVW_ABS_NC >>>> >>>> The reason why that hack routine works is because in nearly all cases, >>>> the expression winds up being a highly constrained Binary expression - >>>> LLVM also constrains this because MCValue has room for exactly two >>>> symbols (but in reality, the pcrel expression can be hairy beasts like >>>> Foo+Bar-Baz + 8 etc... but llvm doesn't seem to support this directly) >>>> >>>>> >>>>>> +static bool EvaluateAsPCRel(const MCExpr *Expr) { >>>>>> + switch (Expr->getKind()) { >>>>>> + case MCExpr::SymbolRef: return false; >>>>>> + case MCExpr::Binary: return true; >>>>>> + default: assert(0 && "Unexpected expression type"); >>>>>> + } >>>>>> +} >>>>>> + >>>>>> uint32_t ARMMCCodeEmitter:: >>>>>> getMovtImmOpValue(const MCInst &MI, unsigned OpIdx, >>>>>> SmallVectorImpl &Fixups) const { >>>>>> @@ -635,18 +661,27 @@ >>>>>> if (MO.isImm()) { >>>>>> return static_cast(MO.getImm()); >>>>>> } else if (const MCSymbolRefExpr *Expr = >>>>>> - dyn_cast(MO.getExpr())) { >>>>>> + FindLHSymExpr(MO.getExpr())) { >>>>>> + // FIXME: :lower16: and :upper16: should be applicable to >>>>>> + // to whole expression, not just symbolrefs >>>>>> + // Until that change takes place, this hack is required to >>>>>> + // generate working code. >>>>>> + const MCExpr *OrigExpr = MO.getExpr(); >>>>>> MCFixupKind Kind; >>>>>> switch (Expr->getKind()) { >>>>>> default: assert(0 && "Unsupported ARMFixup"); >>>>>> case MCSymbolRefExpr::VK_ARM_HI16: >>>>>> Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); >>>>>> + if (EvaluateAsPCRel(OrigExpr)) >>>>>> + Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel); >>>>>> break; >>>>>> case MCSymbolRefExpr::VK_ARM_LO16: >>>>>> Kind = MCFixupKind(ARM::fixup_arm_movw_lo16); >>>>>> + if (EvaluateAsPCRel(OrigExpr)) >>>>>> + Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel); >>>>>> break; >>>>>> } >>>>>> - Fixups.push_back(MCFixup::Create(0, Expr, Kind)); >>>>>> + Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind)); >>>>>> return 0; >>>>>> }; >>>>>> llvm_unreachable("Unsupported MCExpr type in MCOperand!"); >>>>>> >>>>>> Modified: llvm/trunk/test/MC/ARM/elf-movt.s >>>>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123294&r1=123293&r2=123294&view=diff >>>>>> ============================================================================== >>>>>> --- llvm/trunk/test/MC/ARM/elf-movt.s (original) >>>>>> +++ llvm/trunk/test/MC/ARM/elf-movt.s Tue Jan 11 18:19:25 2011 >>>>>> @@ -1,4 +1,6 @@ >>>>>> @ RUN: llvm-mc %s -triple=armv7-linux-gnueabi | FileCheck -check-prefix=ASM %s >>>>>> +@ RUN: llvm-mc %s -triple=armv7-linux-gnueabi -filetype=obj -o - | \ >>>>>> +@ RUN: elf-dump --dump-section-data | FileCheck -check-prefix=OBJ %s >>>>>> .syntax unified >>>>>> .text >>>>>> .globl barf >>>>>> @@ -12,3 +14,26 @@ >>>>>> @ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) >>>>>> @ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) >>>>>> >>>>>> +@@ make sure that the text section fixups are sane too >>>>>> +@ OBJ: '.text' >>>>>> +@ OBJ-NEXT: 'sh_type', 0x00000001 >>>>>> +@ OBJ-NEXT: 'sh_flags', 0x00000006 >>>>>> +@ OBJ-NEXT: 'sh_addr', 0x00000000 >>>>>> +@ OBJ-NEXT: 'sh_offset', 0x00000034 >>>>>> +@ OBJ-NEXT: 'sh_size', 0x00000008 >>>>>> +@ OBJ-NEXT: 'sh_link', 0x00000000 >>>>>> +@ OBJ-NEXT: 'sh_info', 0x00000000 >>>>>> +@ OBJ-NEXT: 'sh_addralign', 0x00000004 >>>>>> +@ OBJ-NEXT: 'sh_entsize', 0x00000000 >>>>>> +@ OBJ-NEXT: '_section_data', 'f00f0fe3 ec0f4fe3' >>>>>> + >>>>>> +@ OBJ: Relocation 0x00000000 >>>>>> +@ OBJ-NEXT: 'r_offset', 0x00000000 >>>>>> +@ OBJ-NEXT: 'r_sym' >>>>>> +@ OBJ-NEXT: 'r_type', 0x0000002d >>>>>> + >>>>>> +@ OBJ: Relocation 0x00000001 >>>>>> +@ OBJ-NEXT: 'r_offset', 0x00000004 >>>>>> +@ OBJ-NEXT: 'r_sym' >>>>>> +@ OBJ-NEXT: 'r_type', 0x0000002e >>>>>> + >>>>>> >>>>>> >>>>>> _______________________________________________ >>>>>> llvm-commits mailing list >>>>>> llvm-commits at cs.uiuc.edu >>>>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>>>> >>>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >>> > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From rafael.espindola at gmail.com Wed Jan 12 23:12:34 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 13 Jan 2011 05:12:34 -0000 Subject: [llvm-commits] [llvm] r123364 - in /llvm/trunk: lib/Linker/LinkModules.cpp test/Linker/unnamed-addr1-a.ll test/Linker/unnamed-addr1-b.ll test/Linker/unnamed-addr2-a.ll test/Linker/unnamed-addr2-b.ll Message-ID: <20110113051234.626642A6C12C@llvm.org> Author: rafael Date: Wed Jan 12 23:12:34 2011 New Revision: 123364 URL: http://llvm.org/viewvc/llvm-project?rev=123364&view=rev Log: Keep unnamed_addr when linking. Added: llvm/trunk/test/Linker/unnamed-addr1-a.ll llvm/trunk/test/Linker/unnamed-addr1-b.ll llvm/trunk/test/Linker/unnamed-addr2-a.ll llvm/trunk/test/Linker/unnamed-addr2-b.ll Modified: llvm/trunk/lib/Linker/LinkModules.cpp Modified: llvm/trunk/lib/Linker/LinkModules.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Linker/LinkModules.cpp?rev=123364&r1=123363&r2=123364&view=diff ============================================================================== --- llvm/trunk/lib/Linker/LinkModules.cpp (original) +++ llvm/trunk/lib/Linker/LinkModules.cpp Wed Jan 12 23:12:34 2011 @@ -352,6 +352,8 @@ unsigned Alignment = std::max(DestGV->getAlignment(), SrcGV->getAlignment()); DestGV->copyAttributesFrom(SrcGV); DestGV->setAlignment(Alignment); + if (SrcGV->hasUnnamedAddr()) + DestGV->setUnnamedAddr(true); } /// GetLinkageResult - This analyzes the two global values and determines what Added: llvm/trunk/test/Linker/unnamed-addr1-a.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/unnamed-addr1-a.ll?rev=123364&view=auto ============================================================================== --- llvm/trunk/test/Linker/unnamed-addr1-a.ll (added) +++ llvm/trunk/test/Linker/unnamed-addr1-a.ll Wed Jan 12 23:12:34 2011 @@ -0,0 +1,11 @@ +; RUN: llvm-link %s %p/unnamed-addr1-b.ll -S -o - | FileCheck %s + + at foo = external global i32 + +define i32 @bar() { +entry: + %tmp = load i32* @foo, align 4 + ret i32 %tmp +} + +; CHECK: @foo = common unnamed_addr global i32 0, align 4 Added: llvm/trunk/test/Linker/unnamed-addr1-b.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/unnamed-addr1-b.ll?rev=123364&view=auto ============================================================================== --- llvm/trunk/test/Linker/unnamed-addr1-b.ll (added) +++ llvm/trunk/test/Linker/unnamed-addr1-b.ll Wed Jan 12 23:12:34 2011 @@ -0,0 +1,4 @@ +; This file is for use with unnamed-addr1-a.ll +; RUN: true + + at foo = common unnamed_addr global i32 0, align 4 Added: llvm/trunk/test/Linker/unnamed-addr2-a.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/unnamed-addr2-a.ll?rev=123364&view=auto ============================================================================== --- llvm/trunk/test/Linker/unnamed-addr2-a.ll (added) +++ llvm/trunk/test/Linker/unnamed-addr2-a.ll Wed Jan 12 23:12:34 2011 @@ -0,0 +1,11 @@ +; RUN: llvm-link %s %p/unnamed-addr2-b.ll -S -o - | FileCheck %s + +define i32 @bar() { +entry: + %call = tail call i32 @foo() + ret i32 %call +} + +declare i32 @foo() + +; CHECK: define unnamed_addr i32 @foo() Added: llvm/trunk/test/Linker/unnamed-addr2-b.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Linker/unnamed-addr2-b.ll?rev=123364&view=auto ============================================================================== --- llvm/trunk/test/Linker/unnamed-addr2-b.ll (added) +++ llvm/trunk/test/Linker/unnamed-addr2-b.ll Wed Jan 12 23:12:34 2011 @@ -0,0 +1,7 @@ +; This file is for use with unnamed-addr2-a.ll +; RUN: true + +define unnamed_addr i32 @foo() { +entry: + ret i32 42 +} From sabre at nondot.org Wed Jan 12 23:41:23 2011 From: sabre at nondot.org (Chris Lattner) Date: Thu, 13 Jan 2011 05:41:23 -0000 Subject: [llvm-commits] [www] r123365 - /www/trunk/OpenProjects.html Message-ID: <20110113054124.0272E2A6C12C@llvm.org> Author: lattner Date: Wed Jan 12 23:41:23 2011 New Revision: 123365 URL: http://llvm.org/viewvc/llvm-project?rev=123365&view=rev Log: loopidiom is rumored to exist Modified: www/trunk/OpenProjects.html Modified: www/trunk/OpenProjects.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/OpenProjects.html?rev=123365&r1=123364&r2=123365&view=diff ============================================================================== --- www/trunk/OpenProjects.html (original) +++ www/trunk/OpenProjects.html Wed Jan 12 23:41:23 2011 @@ -312,10 +312,6 @@ href="http://llvm.org/PR452">improve handling of memcpy/memset.

  • -
  • We need a LoopPass that replaces loops with scalar stores in them -into memset/memcpy calls. This dramatically speeds up programs like -'viterbi' in the testsuite, as well as some SPEC benchmarks.
  • - From aggarwa4 at illinois.edu Wed Jan 12 23:51:13 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 13 Jan 2011 05:51:13 -0000 Subject: [llvm-commits] [poolalloc] r123366 - /poolalloc/trunk/lib/PoolAllocate/AllNodesHeuristic.cpp Message-ID: <20110113055113.68A5D2A6C12C@llvm.org> Author: aggarwa4 Date: Wed Jan 12 23:51:13 2011 New Revision: 123366 URL: http://llvm.org/viewvc/llvm-project?rev=123366&view=rev Log: We must assume that any heap pointer that is cast to int, can escape and hence, must be allocated a global pool. Modified: poolalloc/trunk/lib/PoolAllocate/AllNodesHeuristic.cpp Modified: poolalloc/trunk/lib/PoolAllocate/AllNodesHeuristic.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/AllNodesHeuristic.cpp?rev=123366&r1=123365&r2=123366&view=diff ============================================================================== --- poolalloc/trunk/lib/PoolAllocate/AllNodesHeuristic.cpp (original) +++ poolalloc/trunk/lib/PoolAllocate/AllNodesHeuristic.cpp Wed Jan 12 23:51:13 2011 @@ -73,7 +73,7 @@ // Remove those global nodes which we know will never be pool allocated. // - /*std::vector toRemove; + std::vector toRemove; for (DenseSet::iterator I = NodesFromGlobals.begin(), E = NodesFromGlobals.end(); I != E; ) { DenseSet::iterator Last = I; ++I; @@ -92,7 +92,7 @@ // for (unsigned index = 0; index < toRemove.size(); ++index) { NodesFromGlobals.erase(toRemove[index]); - }*/ + } // // Now the fun part. Find DSNodes in the local graph that correspond to @@ -182,9 +182,15 @@ //assert (!GGN || GlobalHeapNodes.count (GGN)); if (GGN && GlobalHeapNodes.count (GGN)) PoolMap[GGN].NodesInPool.push_back (N); + else if (N->isHeapNode() && N->isPtrToIntNode()){ + //FIXME: This is needed to fix failures in 164.gzip and + // 197.parser. I am not fully sure this is the right fix. + if( !N->isAllocaNode() && !N->isUnknownNode()) { + PoolMap[N]= OnePool(N); + GlobalHeapNodes.insert(N); + } + } } - - } } @@ -239,7 +245,6 @@ ResultPools.push_back(PoolMap[NodesToPA[i]]); else ResultPools.push_back (OnePool(NodesToPA[i])); -// ResultPools.push_back(OnePool(NodesToPA[i])); } } From echristo at apple.com Thu Jan 13 00:47:10 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 13 Jan 2011 06:47:10 -0000 Subject: [llvm-commits] [llvm] r123367 - in /llvm/trunk: lib/Target/X86/X86Subtarget.cpp test/CodeGen/X86/2008-07-19-movups-spills.ll test/CodeGen/X86/2008-10-27-StackRealignment.ll test/CodeGen/X86/2009-08-06-inlineasm.ll test/CodeGen/X86/abi-isel.ll test/CodeGen/X86/sse-align-11.ll Message-ID: <20110113064710.C6CA42A6C12C@llvm.org> Author: echristo Date: Thu Jan 13 00:47:10 2011 New Revision: 123367 URL: http://llvm.org/viewvc/llvm-project?rev=123367&view=rev Log: Experiment with changing the default 32-bit linux stack alignment to 16 bytes for PR8969. Update all testcases accordingly. Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp llvm/trunk/test/CodeGen/X86/2008-07-19-movups-spills.ll llvm/trunk/test/CodeGen/X86/2008-10-27-StackRealignment.ll llvm/trunk/test/CodeGen/X86/2009-08-06-inlineasm.ll llvm/trunk/test/CodeGen/X86/abi-isel.ll llvm/trunk/test/CodeGen/X86/sse-align-11.ll Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=123367&r1=123366&r2=123367&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jan 13 00:47:10 2011 @@ -342,9 +342,9 @@ assert((!Is64Bit || HasX86_64) && "64-bit code requested on a subtarget that doesn't support it!"); - // Stack alignment is 16 bytes on Darwin (both 32 and 64 bit) and for all 64 - // bit targets. - if (isTargetDarwin() || Is64Bit) + // Stack alignment is 16 bytes on Darwin and Linux (both 32 and 64 bit) and + // for all 64-bit targets. + if (isTargetDarwin() || isTargetLinux() || Is64Bit) stackAlignment = 16; if (StackAlignment) Modified: llvm/trunk/test/CodeGen/X86/2008-07-19-movups-spills.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-07-19-movups-spills.ll?rev=123367&r1=123366&r2=123367&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-07-19-movups-spills.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-07-19-movups-spills.ll Thu Jan 13 00:47:10 2011 @@ -1,6 +1,7 @@ ; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=1 -mattr=sse2 | grep movaps | count 75 -; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=0 -mattr=sse2 | grep movaps | count 1 +; RUN: llc < %s -mtriple=i686-pc-linux -realign-stack=0 -mattr=sse2 | grep movaps | count 75 ; PR2539 +; PR8969 - make 32-bit linux have a 16-byte aligned stack external global <4 x float>, align 1 ; <<4 x float>*>:0 [#uses=2] external global <4 x float>, align 1 ; <<4 x float>*>:1 [#uses=1] Modified: llvm/trunk/test/CodeGen/X86/2008-10-27-StackRealignment.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-10-27-StackRealignment.ll?rev=123367&r1=123366&r2=123367&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-10-27-StackRealignment.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-10-27-StackRealignment.ll Thu Jan 13 00:47:10 2011 @@ -1,8 +1,8 @@ ; Linux doesn't support stack realignment for functions with allocas (PR2888). ; Until it does, we shouldn't use movaps to access the stack. On targets with ; sufficiently aligned stack (e.g. darwin) we should. - -; RUN: llc < %s -mtriple=i386-pc-linux-gnu -mcpu=yonah | not grep movaps +; PR8969 - make 32-bit linux have a 16-byte aligned stack +; RUN: llc < %s -mtriple=i386-pc-linux-gnu -mcpu=yonah | grep movaps | count 2 ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mcpu=yonah | grep movaps | count 2 Modified: llvm/trunk/test/CodeGen/X86/2009-08-06-inlineasm.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-08-06-inlineasm.ll?rev=123367&r1=123366&r2=123367&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2009-08-06-inlineasm.ll (original) +++ llvm/trunk/test/CodeGen/X86/2009-08-06-inlineasm.ll Thu Jan 13 00:47:10 2011 @@ -1,10 +1,12 @@ -; RUN: llc -mtriple=i386-pc-linux-gnu < %s +; RUN: false +; XRUN: llc -mtriple=i386-pc-linux-gnu < %s ; PR4668 ; XFAIL: * ; FIXME: If the coalescer happens to coalesce %level.1 with the copy to EAX ; (for ret) then this will fail to compile. The fundamental problem is ; once the coalescer fixes a virtual register to physical register we can't -; evict it. +; evict it. This started passing again due to the changes for PR8969 +; so I've disabled it with a bigger stick. define i32 @x(i32 %qscale) nounwind { entry: Modified: llvm/trunk/test/CodeGen/X86/abi-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/abi-isel.ll?rev=123367&r1=123366&r2=123367&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/abi-isel.ll (original) +++ llvm/trunk/test/CodeGen/X86/abi-isel.ll Thu Jan 13 00:47:10 2011 @@ -8375,7 +8375,7 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: lcallee: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll x ; LINUX-32-STATIC-NEXT: calll x ; LINUX-32-STATIC-NEXT: calll x @@ -8383,11 +8383,11 @@ ; LINUX-32-STATIC-NEXT: calll x ; LINUX-32-STATIC-NEXT: calll x ; LINUX-32-STATIC-NEXT: calll x -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: lcallee: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll x ; LINUX-32-PIC-NEXT: calll x ; LINUX-32-PIC-NEXT: calll x @@ -8395,7 +8395,8 @@ ; LINUX-32-PIC-NEXT: calll x ; LINUX-32-PIC-NEXT: calll x ; LINUX-32-PIC-NEXT: calll x -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: lcallee: @@ -8506,7 +8507,7 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: dcallee: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll y ; LINUX-32-STATIC-NEXT: calll y ; LINUX-32-STATIC-NEXT: calll y @@ -8514,11 +8515,11 @@ ; LINUX-32-STATIC-NEXT: calll y ; LINUX-32-STATIC-NEXT: calll y ; LINUX-32-STATIC-NEXT: calll y -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: dcallee: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll y ; LINUX-32-PIC-NEXT: calll y ; LINUX-32-PIC-NEXT: calll y @@ -8526,7 +8527,8 @@ ; LINUX-32-PIC-NEXT: calll y ; LINUX-32-PIC-NEXT: calll y ; LINUX-32-PIC-NEXT: calll y -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: dcallee: @@ -8770,17 +8772,18 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: caller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll callee ; LINUX-32-STATIC-NEXT: calll callee -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: caller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll callee ; LINUX-32-PIC-NEXT: calll callee -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: caller: @@ -8844,17 +8847,18 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: dcaller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll dcallee ; LINUX-32-STATIC-NEXT: calll dcallee -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: dcaller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll dcallee ; LINUX-32-PIC-NEXT: calll dcallee -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: dcaller: @@ -8918,17 +8922,18 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: lcaller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll lcallee ; LINUX-32-STATIC-NEXT: calll lcallee -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: lcaller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll lcallee ; LINUX-32-PIC-NEXT: calll lcallee -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: lcaller: @@ -8990,15 +8995,16 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: tailcaller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll callee -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: tailcaller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll callee -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: tailcaller: @@ -9053,15 +9059,16 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: dtailcaller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll dcallee -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: dtailcaller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll dcallee -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: dtailcaller: @@ -9116,15 +9123,16 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ltailcaller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll lcallee -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ltailcaller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll lcallee -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ltailcaller: @@ -9183,17 +9191,18 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: icaller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll *ifunc ; LINUX-32-STATIC-NEXT: calll *ifunc -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: icaller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll *ifunc ; LINUX-32-PIC-NEXT: calll *ifunc -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: icaller: @@ -9272,17 +9281,18 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: dicaller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll *difunc ; LINUX-32-STATIC-NEXT: calll *difunc -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: dicaller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll *difunc ; LINUX-32-PIC-NEXT: calll *difunc -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: dicaller: @@ -9354,17 +9364,18 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: licaller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll *lifunc ; LINUX-32-STATIC-NEXT: calll *lifunc -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: licaller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll *lifunc ; LINUX-32-PIC-NEXT: calll *lifunc -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: licaller: @@ -9435,17 +9446,18 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: itailcaller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll *ifunc ; LINUX-32-STATIC-NEXT: calll *ifunc -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: itailcaller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll *ifunc ; LINUX-32-PIC-NEXT: calll *ifunc -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: itailcaller: @@ -9521,15 +9533,16 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: ditailcaller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll *difunc -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: ditailcaller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll *difunc -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: ditailcaller: @@ -9588,15 +9601,16 @@ ; LINUX-64-STATIC: ret ; LINUX-32-STATIC: litailcaller: -; LINUX-32-STATIC: pushl +; LINUX-32-STATIC: subl ; LINUX-32-STATIC-NEXT: calll *lifunc -; LINUX-32-STATIC-NEXT: popl +; LINUX-32-STATIC-NEXT: addl ; LINUX-32-STATIC-NEXT: ret ; LINUX-32-PIC: litailcaller: -; LINUX-32-PIC: pushl +; LINUX-32-PIC: subl ; LINUX-32-PIC-NEXT: calll *lifunc -; LINUX-32-PIC-NEXT: popl +; LINUX-32-PIC-NEXT: addl + ; LINUX-32-PIC-NEXT: ret ; LINUX-64-PIC: litailcaller: Modified: llvm/trunk/test/CodeGen/X86/sse-align-11.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse-align-11.ll?rev=123367&r1=123366&r2=123367&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sse-align-11.ll (original) +++ llvm/trunk/test/CodeGen/X86/sse-align-11.ll Thu Jan 13 00:47:10 2011 @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=i686-apple-darwin8 | grep movaps -; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=i686-linux-gnu | grep movups +; RUN: llc < %s -march=x86 -mcpu=yonah -mtriple=i686-linux-gnu | grep movaps +; PR8969 - make 32-bit linux have a 16-byte aligned stack define <4 x float> @foo(float %a, float %b, float %c, float %d) nounwind { entry: From evan.cheng at apple.com Thu Jan 13 01:58:56 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Jan 2011 07:58:56 -0000 Subject: [llvm-commits] [llvm] r123369 - in /llvm/trunk: include/llvm/MC/MCExpr.h lib/MC/MCExpr.cpp lib/MC/MCObjectStreamer.cpp lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMMCCodeEmitter.cpp lib/Target/ARM/ARMMCExpr.cpp lib/Target/ARM/ARMMCExpr.h lib/Target/ARM/ARMMCInstLower.cpp lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/CMakeLists.txt test/MC/ARM/elf-movt.s test/MC/ARM/hilo-16bit-relocations.s utils/TableGen/EDEmitter.cpp Message-ID: <20110113075856.BAD2C2A6C12C@llvm.org> Author: evancheng Date: Thu Jan 13 01:58:56 2011 New Revision: 123369 URL: http://llvm.org/viewvc/llvm-project?rev=123369&view=rev Log: Model :upper16: and :lower16: as ARM specific MCTargetExpr. This is a step in the right direction. It eliminated some hacks and will unblock codegen work. But it's far from being done. It doesn't reject illegal expressions, e.g. (FOO - :lower16:BAR). It also doesn't work in Thumb2 mode at all. Added: llvm/trunk/lib/Target/ARM/ARMMCExpr.cpp llvm/trunk/lib/Target/ARM/ARMMCExpr.h llvm/trunk/test/MC/ARM/hilo-16bit-relocations.s Modified: llvm/trunk/include/llvm/MC/MCExpr.h llvm/trunk/lib/MC/MCExpr.cpp llvm/trunk/lib/MC/MCObjectStreamer.cpp llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/test/MC/ARM/elf-movt.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/include/llvm/MC/MCExpr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCExpr.h?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCExpr.h (original) +++ llvm/trunk/include/llvm/MC/MCExpr.h Thu Jan 13 01:58:56 2011 @@ -155,8 +155,6 @@ VK_TPOFF, VK_DTPOFF, VK_TLVP, // Mach-O thread local variable relocation - VK_ARM_HI16, // The R_ARM_MOVT_ABS relocation (:upper16: in the .s file) - VK_ARM_LO16, // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the .w file) // FIXME: We'd really like to use the generic Kinds listed above for these. VK_ARM_PLT, // ARM-style PLT references. i.e., (PLT) instead of @PLT VK_ARM_TLSGD, // ditto for TLSGD, GOT, GOTOFF, TPOFF and GOTTPOFF @@ -421,7 +419,7 @@ virtual void PrintImpl(raw_ostream &OS) const = 0; virtual bool EvaluateAsRelocatableImpl(MCValue &Res, const MCAsmLayout *Layout) const = 0; - + virtual void AddValueSymbols(MCAssembler *) const = 0; static bool classof(const MCExpr *E) { return E->getKind() == MCExpr::Target; Modified: llvm/trunk/lib/MC/MCExpr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCExpr.cpp?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCExpr.cpp (original) +++ llvm/trunk/lib/MC/MCExpr.cpp Thu Jan 13 01:58:56 2011 @@ -42,10 +42,6 @@ // absolute names. bool UseParens = Sym.getName()[0] == '$'; - if (SRE.getKind() == MCSymbolRefExpr::VK_ARM_HI16 || - SRE.getKind() == MCSymbolRefExpr::VK_ARM_LO16) - OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind()); - if (SRE.getKind() == MCSymbolRefExpr::VK_PPC_HA16 || SRE.getKind() == MCSymbolRefExpr::VK_PPC_LO16) { OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind()); @@ -65,8 +61,6 @@ SRE.getKind() == MCSymbolRefExpr::VK_ARM_GOTTPOFF) OS << MCSymbolRefExpr::getVariantKindName(SRE.getKind()); else if (SRE.getKind() != MCSymbolRefExpr::VK_None && - SRE.getKind() != MCSymbolRefExpr::VK_ARM_HI16 && - SRE.getKind() != MCSymbolRefExpr::VK_ARM_LO16 && SRE.getKind() != MCSymbolRefExpr::VK_PPC_HA16 && SRE.getKind() != MCSymbolRefExpr::VK_PPC_LO16) OS << '@' << MCSymbolRefExpr::getVariantKindName(SRE.getKind()); @@ -196,8 +190,6 @@ case VK_TPOFF: return "TPOFF"; case VK_DTPOFF: return "DTPOFF"; case VK_TLVP: return "TLVP"; - case VK_ARM_HI16: return ":upper16:"; - case VK_ARM_LO16: return ":lower16:"; case VK_ARM_PLT: return "(PLT)"; case VK_ARM_GOT: return "(GOT)"; case VK_ARM_GOTOFF: return "(GOTOFF)"; Modified: llvm/trunk/lib/MC/MCObjectStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCObjectStreamer.cpp?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCObjectStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCObjectStreamer.cpp Thu Jan 13 01:58:56 2011 @@ -56,7 +56,10 @@ const MCExpr *MCObjectStreamer::AddValueSymbols(const MCExpr *Value) { switch (Value->getKind()) { - case MCExpr::Target: llvm_unreachable("Can't handle target exprs yet!"); + case MCExpr::Target: + cast(Value)->AddValueSymbols(Assembler); + break; + case MCExpr::Constant: break; Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Thu Jan 13 01:58:56 2011 @@ -251,7 +251,7 @@ return Binary; } - unsigned getMovtImmOpValue(const MachineInstr &MI, unsigned Op) const { + unsigned getHiLo16ImmOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jan 13 01:58:56 2011 @@ -425,11 +425,11 @@ let EncoderMethod = "getImmMinusOneOpValue"; } -// For movt/movw - sets the MC Encoder method. +// i32imm_hilo16 - For movt/movw - sets the MC Encoder method. // The imm is split into imm{15-12}, imm{11-0} // -def movt_imm : Operand { - let EncoderMethod = "getMovtImmOpValue"; +def i32imm_hilo16 : Operand { + let EncoderMethod = "getHiLo16ImmOpValue"; } /// bf_inv_mask_imm predicate - An AND mask to clear an arbitrary width bitfield @@ -1907,7 +1907,7 @@ } let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in -def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins movt_imm:$imm), +def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins i32imm_hilo16:$imm), DPFrm, IIC_iMOVi, "movw", "\t$Rd, $imm", [(set GPR:$Rd, imm0_65535:$imm)]>, @@ -1922,7 +1922,7 @@ } let Constraints = "$src = $Rd" in -def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, movt_imm:$imm), +def MOVTi16 : AI1<0b1010, (outs GPR:$Rd), (ins GPR:$src, i32imm_hilo16:$imm), DPFrm, IIC_iMOVi, "movt", "\t$Rd, $imm", [(set GPR:$Rd, @@ -3050,7 +3050,7 @@ } let isMoveImm = 1 in -def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, movt_imm:$imm), +def MOVCCi16 : AI1<0b1000, (outs GPR:$Rd), (ins GPR:$false, i32imm_hilo16:$imm), DPFrm, IIC_iMOVi, "movw", "\t$Rd, $imm", []>, Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Jan 13 01:58:56 2011 @@ -1677,7 +1677,7 @@ } let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in -def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm:$imm), IIC_iMOVi, +def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm_hilo16:$imm), IIC_iMOVi, "movw", "\t$Rd, $imm", [(set rGPR:$Rd, imm0_65535:$imm)]> { let Inst{31-27} = 0b11110; @@ -1697,7 +1697,8 @@ } let Constraints = "$src = $Rd" in -def t2MOVTi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$src, i32imm:$imm), IIC_iMOVi, +def t2MOVTi16 : T2I<(outs rGPR:$Rd), + (ins rGPR:$src, i32imm_hilo16:$imm), IIC_iMOVi, "movt", "\t$Rd, $imm", [(set rGPR:$Rd, (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> { @@ -2684,7 +2685,7 @@ } let isMoveImm = 1 in -def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm:$imm), +def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm_hilo16:$imm), IIC_iCMOVi, "movw", "\t$Rd, $imm", []>, RegConstraint<"$false = $Rd"> { Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Jan 13 01:58:56 2011 @@ -16,6 +16,7 @@ #include "ARMAddressingModes.h" #include "ARMFixupKinds.h" #include "ARMInstrInfo.h" +#include "ARMMCExpr.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" @@ -53,9 +54,11 @@ unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, SmallVectorImpl &Fixups) const; - /// getMovtImmOpValue - Return the encoding for the movw/movt pair - uint32_t getMovtImmOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const; + /// getHiLo16ImmOpValue - Return the encoding for the hi / low 16-bit of + /// the specified operand. This is used for operands with :lower16: and + /// :upper16: prefixes. + uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const; bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx, unsigned &Reg, unsigned &Imm, @@ -626,19 +629,6 @@ return Binary; } -// FIXME: This routine needs to handle more MCExpr types -static const MCSymbolRefExpr *FindLHSymExpr(const MCExpr *E) { - // recurse left child until finding a MCSymbolRefExpr - switch (E->getKind()) { - case MCExpr::SymbolRef: - return cast(E); - case MCExpr::Binary: - return FindLHSymExpr(cast(E)->getLHS()); - default: - return NULL; - } -} - // FIXME: This routine assumes that a binary // expression will always result in a PCRel expression // In reality, its only true if one or more subexpressions @@ -652,38 +642,40 @@ } } -uint32_t ARMMCCodeEmitter:: -getMovtImmOpValue(const MCInst &MI, unsigned OpIdx, - SmallVectorImpl &Fixups) const { +uint32_t +ARMMCCodeEmitter::getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx, + SmallVectorImpl &Fixups) const { // {20-16} = imm{15-12} // {11-0} = imm{11-0} const MCOperand &MO = MI.getOperand(OpIdx); - if (MO.isImm()) { + if (MO.isImm()) + // Hi / lo 16 bits already extracted during earlier passes. return static_cast(MO.getImm()); - } else if (const MCSymbolRefExpr *Expr = - FindLHSymExpr(MO.getExpr())) { - // FIXME: :lower16: and :upper16: should be applicable to - // to whole expression, not just symbolrefs - // Until that change takes place, this hack is required to - // generate working code. - const MCExpr *OrigExpr = MO.getExpr(); + + // Handle :upper16: and :lower16: assembly prefixes. + const MCExpr *E = MO.getExpr(); + if (E->getKind() == MCExpr::Target) { + const ARMMCExpr *ARM16Expr = cast(E); + E = ARM16Expr->getSubExpr(); + MCFixupKind Kind; - switch (Expr->getKind()) { + switch (ARM16Expr->getKind()) { default: assert(0 && "Unsupported ARMFixup"); - case MCSymbolRefExpr::VK_ARM_HI16: + case ARMMCExpr::VK_ARM_HI16: Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); - if (EvaluateAsPCRel(OrigExpr)) + if (EvaluateAsPCRel(E)) Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel); break; - case MCSymbolRefExpr::VK_ARM_LO16: + case ARMMCExpr::VK_ARM_LO16: Kind = MCFixupKind(ARM::fixup_arm_movw_lo16); - if (EvaluateAsPCRel(OrigExpr)) + if (EvaluateAsPCRel(E)) Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel); break; } - Fixups.push_back(MCFixup::Create(0, OrigExpr, Kind)); + Fixups.push_back(MCFixup::Create(0, E, Kind)); return 0; }; + llvm_unreachable("Unsupported MCExpr type in MCOperand!"); return 0; } @@ -1173,8 +1165,8 @@ case ARMII::Size4Bytes: Size = 4; break; } uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); - // Thumb 32-bit wide instructions need to be have the high order halfword - // emitted first. + // Thumb 32-bit wide instructions need to emit the high order halfword + // first. if (Subtarget.isThumb() && Size == 4) { EmitConstant(Binary >> 16, 2, OS); EmitConstant(Binary & 0xffff, 2, OS); Added: llvm/trunk/lib/Target/ARM/ARMMCExpr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCExpr.cpp?rev=123369&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCExpr.cpp (added) +++ llvm/trunk/lib/Target/ARM/ARMMCExpr.cpp Thu Jan 13 01:58:56 2011 @@ -0,0 +1,73 @@ +//===-- ARMMCExpr.cpp - ARM specific MC expression classes ----------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "armmcexpr" +#include "ARMMCExpr.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCAssembler.h" +using namespace llvm; + +const ARMMCExpr* +ARMMCExpr::Create(VariantKind Kind, const MCExpr *Expr, + MCContext &Ctx) { + return new (Ctx) ARMMCExpr(Kind, Expr); +} + +void ARMMCExpr::PrintImpl(raw_ostream &OS) const { + switch (Kind) { + default: assert(0 && "Invalid kind!"); + case VK_ARM_HI16: OS << ":upper16:"; break; + case VK_ARM_LO16: OS << ":lower16:"; break; + } + + const MCExpr *Expr = getSubExpr(); + if (Expr->getKind() != MCExpr::SymbolRef) + OS << '('; + Expr->print(OS); + if (Expr->getKind() != MCExpr::SymbolRef) + OS << ')'; +} + +bool +ARMMCExpr::EvaluateAsRelocatableImpl(MCValue &Res, + const MCAsmLayout *Layout) const { + return false; +} + +// FIXME: This basically copies MCObjectStreamer::AddValueSymbols. Perhaps +// that method should be made public? +static void AddValueSymbols_(const MCExpr *Value, MCAssembler *Asm) { + switch (Value->getKind()) { + case MCExpr::Target: + assert(0 && "Can't handle nested target expr!"); + break; + + case MCExpr::Constant: + break; + + case MCExpr::Binary: { + const MCBinaryExpr *BE = cast(Value); + AddValueSymbols_(BE->getLHS(), Asm); + AddValueSymbols_(BE->getRHS(), Asm); + break; + } + + case MCExpr::SymbolRef: + Asm->getOrCreateSymbolData(cast(Value)->getSymbol()); + break; + + case MCExpr::Unary: + AddValueSymbols_(cast(Value)->getSubExpr(), Asm); + break; + } +} + +void ARMMCExpr::AddValueSymbols(MCAssembler *Asm) const { + AddValueSymbols_(getSubExpr(), Asm); +} Added: llvm/trunk/lib/Target/ARM/ARMMCExpr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCExpr.h?rev=123369&view=auto ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCExpr.h (added) +++ llvm/trunk/lib/Target/ARM/ARMMCExpr.h Thu Jan 13 01:58:56 2011 @@ -0,0 +1,73 @@ +//===-- ARMMCExpr.h - ARM specific MC expression classes ------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#ifndef ARMMCEXPR_H +#define ARMMCEXPR_H + +#include "llvm/MC/MCExpr.h" + +namespace llvm { + +class ARMMCExpr : public MCTargetExpr { +public: + enum VariantKind { + VK_ARM_None, + VK_ARM_HI16, // The R_ARM_MOVT_ABS relocation (:upper16: in the .s file) + VK_ARM_LO16 // The R_ARM_MOVW_ABS_NC relocation (:lower16: in the .s file) + }; + +private: + const VariantKind Kind; + const MCExpr *Expr; + + explicit ARMMCExpr(VariantKind _Kind, const MCExpr *_Expr) + : Kind(_Kind), Expr(_Expr) {} + +public: + /// @name Construction + /// @{ + + static const ARMMCExpr *Create(VariantKind Kind, const MCExpr *Expr, + MCContext &Ctx); + + static const ARMMCExpr *CreateUpper16(const MCExpr *Expr, MCContext &Ctx) { + return Create(VK_ARM_HI16, Expr, Ctx); + } + + static const ARMMCExpr *CreateLower16(const MCExpr *Expr, MCContext &Ctx) { + return Create(VK_ARM_LO16, Expr, Ctx); + } + + /// @} + /// @name Accessors + /// @{ + + /// getOpcode - Get the kind of this expression. + VariantKind getKind() const { return Kind; } + + /// getSubExpr - Get the child of this expression. + const MCExpr *getSubExpr() const { return Expr; } + + /// @} + + void PrintImpl(raw_ostream &OS) const; + bool EvaluateAsRelocatableImpl(MCValue &Res, + const MCAsmLayout *Layout) const; + void AddValueSymbols(MCAssembler *) const; + + static bool classof(const MCExpr *E) { + return E->getKind() == MCExpr::Target; + } + + static bool classof(const ARMMCExpr *) { return true; } + +}; +} // end namespace llvm + +#endif Modified: llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCInstLower.cpp Thu Jan 13 01:58:56 2011 @@ -14,6 +14,7 @@ #include "ARM.h" #include "ARMAsmPrinter.h" +#include "ARMMCExpr.h" #include "llvm/Constants.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/MC/MCExpr.h" @@ -27,16 +28,25 @@ MCContext &Ctx = Printer.OutContext; const MCExpr *Expr; switch (MO.getTargetFlags()) { - default: assert(0 && "Unknown target flag on symbol operand"); - case 0: + default: { Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx); + switch (MO.getTargetFlags()) { + default: + assert(0 && "Unknown target flag on symbol operand"); + case 0: + break; + case ARMII::MO_LO16: + Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx); + Expr = ARMMCExpr::CreateLower16(Expr, Ctx); + break; + case ARMII::MO_HI16: + Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_None, Ctx); + Expr = ARMMCExpr::CreateUpper16(Expr, Ctx); + break; + } break; - case ARMII::MO_LO16: - Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_LO16, Ctx); - break; - case ARMII::MO_HI16: - Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_HI16, Ctx); - break; + } + case ARMII::MO_PLT: Expr = MCSymbolRefExpr::Create(Symbol, MCSymbolRefExpr::VK_ARM_PLT, Ctx); break; Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jan 13 01:58:56 2011 @@ -9,6 +9,7 @@ #include "ARM.h" #include "ARMAddressingModes.h" +#include "ARMMCExpr.h" #include "ARMBaseRegisterInfo.h" #include "ARMSubtarget.h" #include "llvm/MC/MCParser/MCAsmLexer.h" @@ -55,7 +56,7 @@ bool ParseRegisterList(SmallVectorImpl &); bool ParseMemory(SmallVectorImpl &); bool ParseOperand(SmallVectorImpl &); - bool ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind); + bool ParsePrefix(ARMMCExpr::VariantKind &RefKind); const MCExpr *ApplyPrefixToExpr(const MCExpr *E, MCSymbolRefExpr::VariantKind Variant); @@ -870,36 +871,29 @@ return false; case AsmToken::Colon: { // ":lower16:" and ":upper16:" expression prefixes - MCSymbolRefExpr::VariantKind RefKind; + // FIXME: Check it's an expression prefix, + // e.g. (FOO - :lower16:BAR) isn't legal. + ARMMCExpr::VariantKind RefKind; if (ParsePrefix(RefKind)) return true; - const MCExpr *ExprVal; - if (getParser().ParseExpression(ExprVal)) + const MCExpr *SubExprVal; + if (getParser().ParseExpression(SubExprVal)) return true; - // TODO: Attach the prefix to the entire expression - // instead of just the first symbol. - const MCExpr *ModExprVal = ApplyPrefixToExpr(ExprVal, RefKind); - if (!ModExprVal) { - return TokError("invalid modifier '" + getTok().getIdentifier() + - "' (no symbols present)"); - } - + const MCExpr *ExprVal = ARMMCExpr::Create(RefKind, SubExprVal, + getContext()); E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); - Operands.push_back(ARMOperand::CreateImm(ModExprVal, S, E)); + Operands.push_back(ARMOperand::CreateImm(ExprVal, S, E)); return false; } } } -// FIXME: The next 2 routines are hacks to get ARMAsmParser to understand -// :lower16: and :upper16: -// It still attaches VK_ARM_HI/LO16 to MCSymbolRefExpr, but it really -// should be attached to the entire MCExpr as a whole - perhaps using -// MCTargetExpr? -bool ARMAsmParser::ParsePrefix(MCSymbolRefExpr::VariantKind &RefKind) { - RefKind = MCSymbolRefExpr::VK_None; +// ParsePrefix - Parse ARM 16-bit relocations expression prefix, i.e. +// :lower16: and :upper16:. +bool ARMAsmParser::ParsePrefix(ARMMCExpr::VariantKind &RefKind) { + RefKind = ARMMCExpr::VK_ARM_None; // :lower16: and :upper16: modifiers assert(getLexer().is(AsmToken::Colon) && "expected a :"); @@ -912,9 +906,9 @@ StringRef IDVal = Parser.getTok().getIdentifier(); if (IDVal == "lower16") { - RefKind = MCSymbolRefExpr::VK_ARM_LO16; + RefKind = ARMMCExpr::VK_ARM_LO16; } else if (IDVal == "upper16") { - RefKind = MCSymbolRefExpr::VK_ARM_HI16; + RefKind = ARMMCExpr::VK_ARM_HI16; } else { Error(Parser.getTok().getLoc(), "unexpected prefix in operand"); return true; Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Thu Jan 13 01:58:56 2011 @@ -35,6 +35,7 @@ ARMInstrInfo.cpp ARMJITInfo.cpp ARMMCCodeEmitter.cpp + ARMMCExpr.cpp ARMLoadStoreOptimizer.cpp ARMMCAsmInfo.cpp ARMMCInstLower.cpp Modified: llvm/trunk/test/MC/ARM/elf-movt.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/elf-movt.s (original) +++ llvm/trunk/test/MC/ARM/elf-movt.s Thu Jan 13 01:58:56 2011 @@ -11,8 +11,8 @@ movw r0, :lower16:GOT-(.LPC0_2+8) movt r0, :upper16:GOT-(.LPC0_2+16) .LPC0_2: -@ ASM: movw r0, :lower16:GOT-(.LPC0_2+8) -@ ASM-NEXT: movt r0, :upper16:GOT-(.LPC0_2+16) +@ ASM: movw r0, :lower16:(GOT-(.LPC0_2+8)) +@ ASM-NEXT: movt r0, :upper16:(GOT-(.LPC0_2+16)) @@ make sure that the text section fixups are sane too @ OBJ: '.text' Added: llvm/trunk/test/MC/ARM/hilo-16bit-relocations.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/hilo-16bit-relocations.s?rev=123369&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/hilo-16bit-relocations.s (added) +++ llvm/trunk/test/MC/ARM/hilo-16bit-relocations.s Thu Jan 13 01:58:56 2011 @@ -0,0 +1,21 @@ +@ RUN: llvm-mc %s -triple armv7-apple-darwin -show-encoding | FileCheck %s + +_t: + movw r0, :lower16:(L_foo$non_lazy_ptr - (L1 + 8)) + movt r0, :upper16:(L_foo$non_lazy_ptr - (L1 + 8)) +L1: + +@ CHECK: movw r0, :lower16:(L_foo$non_lazy_ptr-(L1+8)) @ encoding: [A,A,0x00,0xe3] +@ CHECK: @ fixup A - offset: 0, value: L_foo$non_lazy_ptr-(L1+8), kind: fixup_arm_movw_lo16_pcrel +@ CHECK: movt r0, :upper16:(L_foo$non_lazy_ptr-(L1+8)) @ encoding: [A,A,0x40,0xe3] +@ CHECK: @ fixup A - offset: 0, value: L_foo$non_lazy_ptr-(L1+8), kind: fixup_arm_movt_hi16_pcrel + + .comm _foo,4,2 + + .section __DATA,__nl_symbol_ptr,non_lazy_symbol_pointers + .align 2 +L_foo$non_lazy_ptr: + .indirect_symbol _foo + .long 0 + +.subsections_via_symbols Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=123369&r1=123368&r2=123369&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Thu Jan 13 01:58:56 2011 @@ -564,7 +564,7 @@ REG("QQQQPR"); IMM("i32imm"); - IMM("movt_imm"); + IMM("i32imm_hilo16"); IMM("bf_inv_mask_imm"); IMM("jtblock_operand"); IMM("nohash_imm"); From baldrick at free.fr Thu Jan 13 02:56:29 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 13 Jan 2011 08:56:29 -0000 Subject: [llvm-commits] [llvm] r123372 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll Message-ID: <20110113085629.B95662A6C12D@llvm.org> Author: baldrick Date: Thu Jan 13 02:56:29 2011 New Revision: 123372 URL: http://llvm.org/viewvc/llvm-project?rev=123372&view=rev Log: The most common simplification missed by instsimplify in unoptimized bitcode is "X != 0 -> X" when X is a boolean. This occurs a lot because of the way llvm-gcc converts gcc's conditional expressions. Add this, and a few other similar transforms for completeness. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=123372&r1=123371&r2=123372&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Jan 13 02:56:29 2011 @@ -938,8 +938,8 @@ Pred = CmpInst::getSwappedPredicate(Pred); } - // ITy - This is the return type of the compare we're considering. - const Type *ITy = GetCompareTy(LHS); + const Type *ITy = GetCompareTy(LHS); // The return type. + const Type *OpTy = LHS->getType(); // The operand type. // icmp X, X -> true/false // X icmp undef -> true/false. For example, icmp ugt %X, undef -> false @@ -947,40 +947,91 @@ if (LHS == RHS || isa(RHS)) return ConstantInt::get(ITy, CmpInst::isTrueWhenEqual(Pred)); - // icmp , - Global/Stack value - // addresses never equal each other! We already know that Op0 != Op1. - if ((isa(LHS) || isa(LHS) || - isa(LHS)) && - (isa(RHS) || isa(RHS) || - isa(RHS))) - return ConstantInt::get(ITy, CmpInst::isFalseWhenEqual(Pred)); + // Special case logic when the operands have i1 type. + if (OpTy->isIntegerTy(1) || (OpTy->isVectorTy() && + cast(OpTy)->getElementType()->isIntegerTy(1))) { + switch (Pred) { + default: break; + case ICmpInst::ICMP_EQ: + // X == 1 -> X + if (match(RHS, m_One())) + return LHS; + break; + case ICmpInst::ICMP_NE: + // X != 0 -> X + if (match(RHS, m_Zero())) + return LHS; + break; + case ICmpInst::ICMP_UGT: + // X >u 0 -> X + if (match(RHS, m_Zero())) + return LHS; + break; + case ICmpInst::ICMP_UGE: + // X >=u 1 -> X + if (match(RHS, m_One())) + return LHS; + break; + case ICmpInst::ICMP_SLT: + // X X + if (match(RHS, m_Zero())) + return LHS; + break; + case ICmpInst::ICMP_SLE: + // X <=s -1 -> X + if (match(RHS, m_One())) + return LHS; + break; + } + } // See if we are doing a comparison with a constant. if (ConstantInt *CI = dyn_cast(RHS)) { - // If we have an icmp le or icmp ge instruction, turn it into the - // appropriate icmp lt or icmp gt instruction. This allows us to rely on - // them being folded in the code below. switch (Pred) { default: break; - case ICmpInst::ICMP_ULE: - if (CI->isMaxValue(false)) // A <=u MAX -> TRUE - return ConstantInt::getTrue(CI->getContext()); - break; - case ICmpInst::ICMP_SLE: - if (CI->isMaxValue(true)) // A <=s MAX -> TRUE - return ConstantInt::getTrue(CI->getContext()); + case ICmpInst::ICMP_UGT: + if (CI->isMaxValue(false)) // A >u MAX -> FALSE + return ConstantInt::getFalse(CI->getContext()); break; case ICmpInst::ICMP_UGE: if (CI->isMinValue(false)) // A >=u MIN -> TRUE return ConstantInt::getTrue(CI->getContext()); break; + case ICmpInst::ICMP_ULT: + if (CI->isMinValue(false)) // A FALSE + return ConstantInt::getFalse(CI->getContext()); + break; + case ICmpInst::ICMP_ULE: + if (CI->isMaxValue(false)) // A <=u MAX -> TRUE + return ConstantInt::getTrue(CI->getContext()); + break; + case ICmpInst::ICMP_SGT: + if (CI->isMaxValue(true)) // A >s MAX -> FALSE + return ConstantInt::getFalse(CI->getContext()); + break; case ICmpInst::ICMP_SGE: if (CI->isMinValue(true)) // A >=s MIN -> TRUE return ConstantInt::getTrue(CI->getContext()); break; + case ICmpInst::ICMP_SLT: + if (CI->isMinValue(true)) // A FALSE + return ConstantInt::getFalse(CI->getContext()); + break; + case ICmpInst::ICMP_SLE: + if (CI->isMaxValue(true)) // A <=s MAX -> TRUE + return ConstantInt::getTrue(CI->getContext()); + break; } } + // icmp , - Global/Stack value + // addresses never equal each other! We already know that Op0 != Op1. + if ((isa(LHS) || isa(LHS) || + isa(LHS)) && + (isa(RHS) || isa(RHS) || + isa(RHS))) + return ConstantInt::get(ITy, CmpInst::isFalseWhenEqual(Pred)); + // If the comparison is with the result of a select instruction, check whether // comparing with either branch of the select always yields the same value. if (isa(LHS) || isa(RHS)) Modified: llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll?rev=123372&r1=123371&r2=123372&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll (original) +++ llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll Thu Jan 13 02:56:29 2011 @@ -20,3 +20,10 @@ ret i1 %z ; CHECK: ret i1 %x } + +define i1 @ne(i1 %x) { +; CHECK: @ne + %z = icmp ne i1 %x, 0 + ret i1 %z +; CHECK: ret i1 %x +} From fvbommel at gmail.com Thu Jan 13 04:09:57 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Thu, 13 Jan 2011 11:09:57 +0100 Subject: [llvm-commits] [llvm] r123372 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll In-Reply-To: <20110113085629.B95662A6C12D@llvm.org> References: <20110113085629.B95662A6C12D@llvm.org> Message-ID: On Thu, Jan 13, 2011 at 9:56 AM, Duncan Sands wrote: > + ?// icmp , - Global/Stack value > + ?// addresses never equal each other! ?We already know that Op0 != Op1. > + ?if ((isa(LHS) || isa(LHS) || > + ? ? ? isa(LHS)) && > + ? ? ?(isa(RHS) || isa(RHS) || > + ? ? ? isa(RHS))) > + ? ?return ConstantInt::get(ITy, CmpInst::isFalseWhenEqual(Pred)); This is pre-existing code you only moved, but it looks buggy: some globals may be null. In particular, 'extern_weak' declarations may be null at run time if no definition is ever linked in. I guess it probably dates from before extern_weak was introduced (possibly by way of -instcombine). Luckily, after trying it out, it seems that those cases are caught by constant folding (which seems to do the right thing) before this code is reached. Still, a note in the comment that this code depends on that might be in order. From 6yearold at gmail.com Thu Jan 13 04:09:50 2011 From: 6yearold at gmail.com (arrowdodger) Date: Thu, 13 Jan 2011 13:09:50 +0300 Subject: [llvm-commits] [patch][cmake] Fix check for Message-ID: Here is patch, that fixes checking for argz.h header file in CMake build. I decided, that if argz.h is found, then it's safe to suggest, that we have all argz_* functions. So, i'm not checking every function' existance. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/4cdfd11a/attachment.html From baldrick at free.fr Thu Jan 13 04:43:08 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 13 Jan 2011 10:43:08 -0000 Subject: [llvm-commits] [llvm] r123373 - /llvm/trunk/lib/Analysis/InstructionSimplify.cpp Message-ID: <20110113104308.9FCEC2A6C12C@llvm.org> Author: baldrick Date: Thu Jan 13 04:43:08 2011 New Revision: 123373 URL: http://llvm.org/viewvc/llvm-project?rev=123373&view=rev Log: Remove some wrong code which fortunately was never executed (as explained in the comment I added): an extern weak global may have a null address. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=123373&r1=123372&r2=123373&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Jan 13 04:43:08 2011 @@ -1024,12 +1024,15 @@ } } - // icmp , - Global/Stack value - // addresses never equal each other! We already know that Op0 != Op1. - if ((isa(LHS) || isa(LHS) || - isa(LHS)) && - (isa(RHS) || isa(RHS) || - isa(RHS))) + // icmp , - Different stack variables have + // different addresses, and what's more the address of a stack variable is + // never null or equal to the address of a global. Note that generalizing + // to the case where LHS is a global variable address or null is pointless, + // since if both LHS and RHS are constants then we already constant folded + // the compare, and if only one of them is then we moved it to RHS already. + if (isa(LHS) && (isa(RHS) || isa(RHS) || + isa(RHS))) + // We already know that LHS != LHS. return ConstantInt::get(ITy, CmpInst::isFalseWhenEqual(Pred)); // If the comparison is with the result of a select instruction, check whether From baldrick at free.fr Thu Jan 13 04:46:51 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 13 Jan 2011 11:46:51 +0100 Subject: [llvm-commits] [llvm] r123372 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll In-Reply-To: References: <20110113085629.B95662A6C12D@llvm.org> Message-ID: <4D2ED81B.3060807@free.fr> Hi Frits, > On Thu, Jan 13, 2011 at 9:56 AM, Duncan Sands wrote: >> + // icmp, - Global/Stack value >> + // addresses never equal each other! We already know that Op0 != Op1. >> + if ((isa(LHS) || isa(LHS) || >> + isa(LHS))&& >> + (isa(RHS) || isa(RHS) || >> + isa(RHS))) >> + return ConstantInt::get(ITy, CmpInst::isFalseWhenEqual(Pred)); > > This is pre-existing code you only moved, but it looks buggy: some > globals may be null. In particular, 'extern_weak' declarations may be > null at run time if no definition is ever linked in. I guess it > probably dates from before extern_weak was introduced (possibly by way > of -instcombine). > > Luckily, after trying it out, it seems that those cases are caught by > constant folding (which seems to do the right thing) before this code > is reached. Still, a note in the comment that this code depends on > that might be in order. I removed the wrong cases, which as you noted were never executed anyway. Ciao, Duncan. From ofv at wanadoo.es Thu Jan 13 07:21:00 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Thu, 13 Jan 2011 14:21:00 +0100 Subject: [llvm-commits] [patch][cmake] Fix check for References: Message-ID: <87d3o1ey83.fsf@wanadoo.es> arrowdodger <6yearold at gmail.com> writes: > Here is patch, that fixes checking for argz.h header file in CMake build. > I decided, that if argz.h is found, then it's safe to suggest, that we have > all argz_* functions. So, i'm not checking every function' existance. You forgot to attach the patch, but anyways what you describe does not seem right to me. The existence of a header does not imply the existence of the functions that *usuallay* that header declares. For the specific case of argz_*, I guess that there is a good reason why the configure script tests for their existence. In any case, your change should target cmake and `configure', not just cmake. Eric? From ofv at wanadoo.es Thu Jan 13 08:09:39 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Thu, 13 Jan 2011 15:09:39 +0100 Subject: [llvm-commits] [patch][cmake] Fix check for In-Reply-To: (arrowdodger's message of "Thu, 13 Jan 2011 16:58:27 +0300") References: <87d3o1ey83.fsf@wanadoo.es> Message-ID: <877he8gajg.fsf@wanadoo.es> arrowdodger <6yearold at gmail.com> writes: >> but anyways what you describe does not >> seem right to me. The existence of a header does not imply the existence >> of the functions that *usuallay* that header declares. For the specific >> case of argz_*, I guess that there is a good reason why the configure >> script tests for their existence. In any case, your change should target >> cmake and `configure', not just cmake. >> > Now i looked into configure.ac and haven't find any argz checks. But these > defines appear both in config.h.in and config.h.cmake. The configure script tests for the presence of the argz_* functions: checking for argz_append... yes checking for argz_create_sep... yes checking for argz_insert... yes checking for argz_next... yes checking for argz_stringify... yes > So, should i just delete all these checks and defines from both builds or > tweak my current patch as you suggested? As mentioned above, IMO it is not correct to remove the argz_* tests just because argz.h exists, unless we know for sure that all platforms with argz.h have those functions defined. From fvbommel at gmail.com Thu Jan 13 08:37:17 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Thu, 13 Jan 2011 15:37:17 +0100 Subject: [llvm-commits] [PATCH] CMake unittests should compile without RTTI Message-ID: It seems that when the CMake build is configured to compile with unittests it does so with RTTI information enabled, which causes linker errors because it tries to link them to an RTTI-less LLVM. This is a recent problem by the way, it worked just fine last week. The attached patch is a quick and dirty fix for this, but I'm not sure if it's the right approach. Since I couldn't find any way to *enable* RTTI for LLVM in the cmake configuration, I just assumed it should always be off. By the way, are there no buildbots running CMake with unittests enabled? None of them seem to have failed over this... -------------- next part -------------- A non-text attachment was scrubbed... Name: 001-cmake-unittests-no-rtti.patch Type: text/x-diff Size: 482 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/87b84d68/attachment.bin From 6yearold at gmail.com Thu Jan 13 08:57:21 2011 From: 6yearold at gmail.com (arrowdodger) Date: Thu, 13 Jan 2011 17:57:21 +0300 Subject: [llvm-commits] [patch][cmake] Fix check for In-Reply-To: <877he8gajg.fsf@wanadoo.es> References: <87d3o1ey83.fsf@wanadoo.es> <877he8gajg.fsf@wanadoo.es> Message-ID: On Thu, Jan 13, 2011 at 5:09 PM, ?scar Fuentes wrote: > The configure script tests for the presence of the argz_* functions: > > checking for argz_append... yes > checking for argz_create_sep... yes > checking for argz_insert... yes > checking for argz_next... yes > checking for argz_stringify... yes > Oh, right. It's only present in configure script itself. Okay, here is updated patch. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/52e698a7/attachment-0001.html -------------- next part -------------- A non-text attachment was scrubbed... Name: argz.cmake.patch Type: text/x-patch Size: 1907 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/52e698a7/attachment-0001.bin From geek4civic at gmail.com Thu Jan 13 09:05:19 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 14 Jan 2011 00:05:19 +0900 Subject: [llvm-commits] [PATCH] CMake unittests should compile without RTTI In-Reply-To: References: Message-ID: Hello Frits and Oscar, I have yet another patch for the issue. Attached. 2011/1/13 Frits van Bommel : > By the way, are there no buildbots running CMake with unittests > enabled? None of them seem to have failed over this... Indeed, we might have at least one cmake-based buildbot on posix. ...Takumi -------------- next part -------------- --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -178,6 +178,11 @@ set(llvm_builded_incs_dir ${LLVM_BINARY_DIR}/include/llvm) include(AddLLVMDefinitions) +# Add appropriate flags for GCC +if (CMAKE_COMPILER_IS_GNUCXX) + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-common -Woverloaded-virtual -Wcast-qual -fno-strict-aliasing -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings") +endif () + if(WIN32) if(CYGWIN) set(LLVM_ON_WIN32 0) diff --git a/unittests/CMakeLists.txt b/unittests/CMakeLists.txt index 61ea1ee..7ec7a21 100644 --- a/unittests/CMakeLists.txt +++ b/unittests/CMakeLists.txt @@ -12,6 +12,7 @@ function(add_llvm_unittest test_dirname) endif() add_llvm_executable(${test_name}Tests ${ARGN}) add_dependencies(UnitTests ${test_name}Tests) + set( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS}" PARENT_SCOPE ) endfunction() add_custom_target(UnitTests) From ofv at wanadoo.es Thu Jan 13 09:06:32 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Thu, 13 Jan 2011 15:06:32 -0000 Subject: [llvm-commits] [llvm] r123376 - in /llvm/trunk: cmake/config-ix.cmake include/llvm/Config/config.h.cmake Message-ID: <20110113150632.42D292A6C12C@llvm.org> Author: ofv Date: Thu Jan 13 09:06:32 2011 New Revision: 123376 URL: http://llvm.org/viewvc/llvm-project?rev=123376&view=rev Log: Platform tests for argz_* functions. Patch by arrowdodger! Modified: llvm/trunk/cmake/config-ix.cmake llvm/trunk/include/llvm/Config/config.h.cmake Modified: llvm/trunk/cmake/config-ix.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=123376&r1=123375&r2=123376&view=diff ============================================================================== --- llvm/trunk/cmake/config-ix.cmake (original) +++ llvm/trunk/cmake/config-ix.cmake Thu Jan 13 09:06:32 2011 @@ -113,6 +113,13 @@ if ( LLVM_ON_WIN32 ) check_symbol_exists(_chsize_s io.h HAVE__CHSIZE_S) endif() +if( HAVE_ARGZ_H ) + check_symbol_exists(argz_append argz.h HAVE_ARGZ_APPEND) + check_symbol_exists(argz_create_sep argz.h HAVE_ARGZ_CREATE_SEP) + check_symbol_exists(argz_insert argz.h HAVE_ARGZ_INSERT) + check_symbol_exists(argz_next argz.h HAVE_ARGZ_NEXT) + check_symbol_exists(argz_stringify argz.h HAVE_ARGZ_STRINGIFY) +endif() check_symbol_exists(__GLIBC__ stdio.h LLVM_USING_GLIBC) if( LLVM_USING_GLIBC ) Modified: llvm/trunk/include/llvm/Config/config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=123376&r1=123375&r2=123376&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/config.h.cmake Thu Jan 13 09:06:32 2011 @@ -37,22 +37,22 @@ #cmakedefine ENABLE_THREADS ${ENABLE_THREADS} /* Define to 1 if you have the `argz_append' function. */ -#undef HAVE_ARGZ_APPEND +#cmakedefine HAVE_ARGZ_APPEND ${HAVE_ARGZ_APPEND} /* Define to 1 if you have the `argz_create_sep' function. */ -#undef HAVE_ARGZ_CREATE_SEP +#cmakedefine HAVE_ARGZ_CREATE_SEP ${HAVE_ARGZ_CREATE_SEP} /* Define to 1 if you have the header file. */ #cmakedefine HAVE_ARGZ_H ${HAVE_ARGZ_H} /* Define to 1 if you have the `argz_insert' function. */ -#undef HAVE_ARGZ_INSERT +#cmakedefine HAVE_ARGZ_INSERT ${HAVE_ARGZ_INSERT} /* Define to 1 if you have the `argz_next' function. */ -#undef HAVE_ARGZ_NEXT +#cmakedefine HAVE_ARGZ_NEXT ${HAVE_ARGZ_NEXT} /* Define to 1 if you have the `argz_stringify' function. */ -#undef HAVE_ARGZ_STRINGIFY +#cmakedefine HAVE_ARGZ_STRINGIFY ${HAVE_ARGZ_STRINGIFY} /* Define to 1 if you have the header file. */ #cmakedefine HAVE_ASSERT_H ${HAVE_ASSERT_H} From ofv at wanadoo.es Thu Jan 13 09:12:31 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Thu, 13 Jan 2011 16:12:31 +0100 Subject: [llvm-commits] [patch][cmake] Fix check for In-Reply-To: (arrowdodger's message of "Thu, 13 Jan 2011 17:57:21 +0300") References: <87d3o1ey83.fsf@wanadoo.es> <877he8gajg.fsf@wanadoo.es> Message-ID: <8739owg7mo.fsf@wanadoo.es> arrowdodger <6yearold at gmail.com> writes: > Oh, right. It's only present in configure script itself. > > Okay, here is updated patch. That's quite right. Committed as r123376. Thanks! From grosser at fim.uni-passau.de Thu Jan 13 09:29:29 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 13 Jan 2011 10:29:29 -0500 Subject: [llvm-commits] [PATCH] Add single entry / single exit accessors. In-Reply-To: <4D2EE1B9.6020408@fim.uni-passau.de> References: <4D2EE1B9.6020408@fim.uni-passau.de> Message-ID: <4D2F1A59.3020305@fim.uni-passau.de> On 01/13/2011 06:27 AM, Andreas Simbuerger wrote: > Hi, > > this time from the correct mail-address;-) > This patch adds support for single entry / single exit edge > accessors to regions. Thanks, Andreas. Just some small comments inline. > A (refined) region that has only 2 transition edges (1 entry, 1 exit) > to its parent region is defined as a simple region. > > Both methods added, return null if there is more than one entry/exit edge. > > Cheers, > Andreas > > > > 0001-Add-single-entry-single-exit-accessors.patch > > > diff --git include/llvm/Analysis/RegionInfo.h include/llvm/Analysis/RegionInfo.h > index 737d46c..4c06ec0 100644 > --- include/llvm/Analysis/RegionInfo.h > +++ include/llvm/Analysis/RegionInfo.h > @@ -305,6 +305,20 @@ public: > /// NULL if such a basic block does not exist. > Region *getExpandedRegion() const; > > + /// @brief Return the first block of this region's single entry edge, > + /// if existing. > + /// > + /// @return The BasicBlock starting this region's single entry edge, > + /// else NULL. > + BasicBlock *getSingleEntryBlock() const; I would call this getEnteringBlock() following LoopInfo in this case. > + > + /// @brief Return the first block of this region's single exit edge, > + /// if existing. > + /// > + /// @return The BasicBlock starting this region's single exit edge, > + /// else NULL. > + BasicBlock *getSingleExitBlock() const; getExitingBlock() would follow LoopInfo probably. > /// @brief Is this a simple region? > /// > /// A region is simple if it has exactly one exit and one entry edge. > diff --git lib/Analysis/RegionInfo.cpp lib/Analysis/RegionInfo.cpp > index cf48a71..22e822b 100644 > --- lib/Analysis/RegionInfo.cpp > +++ lib/Analysis/RegionInfo.cpp > @@ -131,43 +131,55 @@ Loop *Region::outermostLoopInRegion(Loop *L) const { > Loop*Region::outermostLoopInRegion(LoopInfo *LI, BasicBlock* BB) const { > assert(LI&& BB&& "LI and BB cannot be null!"); > Loop *L = LI->getLoopFor(BB); > + > return outermostLoopInRegion(L); > } > > -bool Region::isSimple() const { > - bool isSimple = true; > - bool found = false; > - > - BasicBlock *entry = getEntry(), *exit = getExit(); > - > - if (isTopLevelRegion()) > - return false; > +BasicBlock *Region::getSingleEntryBlock() const { > + BasicBlock *entry = getEntry(); > + BasicBlock *Pred; > + BasicBlock *ee = 0; > > for (pred_iterator PI = pred_begin(entry), PE = pred_end(entry); PI != PE; > ++PI) { > - BasicBlock *Pred = *PI; > + Pred = *PI; > if (DT->getNode(Pred)&& !contains(Pred)) { > - if (found) { > - isSimple = false; > - break; > - } > - found = true; > + if (ee) > + return 0; > + > + ee = Pred; Can you combine the two if conditions? > } > } > > - found = false; > + return ee; > +} Maybe use a more expressive variable name instead of 'ee'. Maybe something like 'enteringBlock'? > +BasicBlock *Region::getSingleExitBlock() const { > + BasicBlock *exit = getExit(); > + BasicBlock *Pred; > + BasicBlock *ee = 0; > + > + if (!exit) > + return 0; > > for (pred_iterator PI = pred_begin(exit), PE = pred_end(exit); PI != PE; > - ++PI) > - if (contains(*PI)) { > - if (found) { > - isSimple = false; > - break; > - } > - found = true; > + ++PI) { > + Pred = *PI; > + if (contains(Pred)) { > + if (ee) > + return 0; > + > + ee = Pred; > } > + } > > - return isSimple; > + return ee; > +} Same comments apply here. > +bool Region::isSimple() const { > + return !(isTopLevelRegion()) > +&& (getSingleEntryBlock() != 0) > +&& (getSingleExitBlock() != 0); I am not sure if my email has removed some spaces/tabs. But please recheck indentation. Thanks Tobi From ofv at wanadoo.es Thu Jan 13 09:31:45 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Thu, 13 Jan 2011 15:31:45 -0000 Subject: [llvm-commits] [llvm] r123377 - /llvm/trunk/unittests/CMakeLists.txt Message-ID: <20110113153145.6E2852A6C12C@llvm.org> Author: ofv Date: Thu Jan 13 09:31:45 2011 New Revision: 123377 URL: http://llvm.org/viewvc/llvm-project?rev=123377&view=rev Log: Disable RTTI when building unit tests. This avoids errors at link time. Modified: llvm/trunk/unittests/CMakeLists.txt Modified: llvm/trunk/unittests/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/CMakeLists.txt?rev=123377&r1=123376&r2=123377&view=diff ============================================================================== --- llvm/trunk/unittests/CMakeLists.txt (original) +++ llvm/trunk/unittests/CMakeLists.txt Thu Jan 13 09:31:45 2011 @@ -18,6 +18,12 @@ include_directories(${LLVM_MAIN_SRC_DIR}/utils/unittest/googletest/include) add_definitions(-DGTEST_HAS_RTTI=0) +if( CMAKE_COMPILER_IS_GNUCXX ) + llvm_replace_compiler_option(CMAKE_CXX_FLAGS "-frtti" "-fno-rtti") +elseif( MSVC ) + llvm_replace_compiler_option(CMAKE_CXX_FLAGS "/GR" "/GR-") +endif() + if (NOT LLVM_ENABLE_THREADS) add_definitions(-DGTEST_HAS_PTHREAD=0) endif() From ofv at wanadoo.es Thu Jan 13 09:36:22 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Thu, 13 Jan 2011 16:36:22 +0100 Subject: [llvm-commits] [PATCH] CMake unittests should compile without RTTI In-Reply-To: (NAKAMURA Takumi's message of "Fri, 14 Jan 2011 00:05:19 +0900") References: Message-ID: <87y66oeryh.fsf@wanadoo.es> NAKAMURA Takumi writes: > I have yet another patch for the issue. Attached. I just committed a fix based on Frits' proposal. Comments on yours follow. > 2011/1/13 Frits van Bommel : >> By the way, are there no buildbots running CMake with unittests >> enabled? None of them seem to have failed over this... > > Indeed, we might have at least one cmake-based buildbot on posix. AFAIK the Windows cmake buildbot does not do tests. > --- a/CMakeLists.txt > +++ b/CMakeLists.txt > @@ -178,6 +178,11 @@ set(llvm_builded_incs_dir ${LLVM_BINARY_DIR}/include/llvm) > > include(AddLLVMDefinitions) > > +# Add appropriate flags for GCC > +if (CMAKE_COMPILER_IS_GNUCXX) > + set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-common -Woverloaded-virtual -Wcast-qual -fno-strict-aliasing -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings") > +endif () > + -pentantic and -Wno-long-long are controlled by the option LLVM_ENABLE_PEDANTIC. See the top level CMakeLists.txt > if(WIN32) > if(CYGWIN) > set(LLVM_ON_WIN32 0) > diff --git a/unittests/CMakeLists.txt b/unittests/CMakeLists.txt > index 61ea1ee..7ec7a21 100644 > --- a/unittests/CMakeLists.txt > +++ b/unittests/CMakeLists.txt > @@ -12,6 +12,7 @@ function(add_llvm_unittest test_dirname) > endif() > add_llvm_executable(${test_name}Tests ${ARGN}) > add_dependencies(UnitTests ${test_name}Tests) > + set( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS}" PARENT_SCOPE ) Why do you need this? From geek4civic at gmail.com Thu Jan 13 09:54:00 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 14 Jan 2011 00:54:00 +0900 Subject: [llvm-commits] [PATCH] CMake unittests should compile without RTTI In-Reply-To: <87y66oeryh.fsf@wanadoo.es> References: <87y66oeryh.fsf@wanadoo.es> Message-ID: Good midnight, Oscar! 2011/1/14 ?scar Fuentes : > AFAIK the Windows cmake buildbot does not do tests. IIRC, just before clang-msvc had died, Daniel had enabled llvm's "check". Then it reported several (and I expected then) failures. Unittests might be executed then. I am working for Windows x64. It is because I would like to brush up llvm win64 tests. >> +# Add appropriate flags for GCC >> +if (CMAKE_COMPILER_IS_GNUCXX) >> + ?set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-common -Woverloaded-virtual -Wcast-qual -fno-strict-aliasing -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings") >> +endif () >> + > > -pentantic and -Wno-long-long are controlled by the option > LLVM_ENABLE_PEDANTIC. See the top level CMakeLists.txt Oh excuse me! It was copypasted from clang/CMakeLists.txt! It would not needed for this issue. I forgot to exclude it. Then I tried tweaking unittest issue. >> --- a/unittests/CMakeLists.txt >> +++ b/unittests/CMakeLists.txt >> @@ -12,6 +12,7 @@ function(add_llvm_unittest test_dirname) >> ? ?endif() >> ? ?add_llvm_executable(${test_name}Tests ${ARGN}) >> ? ?add_dependencies(UnitTests ${test_name}Tests) >> + ?set( CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS}" PARENT_SCOPE ) > > Why do you need this? I don't know reason why. :( Without this hack, I had seen several "-fno-exceptions -fno-exceptions -fno-exceptions ..." and CMake would not add "-fno-rtti", on (homebrew) cmake-2.8.2 on linux. I have not yet evaluated this patch on Visual Studio. (IIRC, cmake/mingw did not affected regardless of this patch, for me) Thank you! ...Takumi From jay.foad at gmail.com Thu Jan 13 10:13:00 2011 From: jay.foad at gmail.com (Jay Foad) Date: Thu, 13 Jan 2011 16:13:00 +0000 Subject: [llvm-commits] [PATCH] simplify construction and destruction of Uses Message-ID: This patch makes sure that we consistently use placement new to construct Uses, and that we destroy them before the memory is deallocated. There should be no change in behaviour (because Use's constructor did nothing, and its destructor was equivalent to Use::set(0)) but I think it is more correct. The patch also simplifies User::dropHungOffUses() and its callers. OK to commit? Thanks, Jay. -------------- next part -------------- A non-text attachment was scrubbed... Name: use-ctor-dtor Type: application/octet-stream Size: 5401 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/14308064/attachment.obj From geek4civic at gmail.com Thu Jan 13 10:17:37 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 14 Jan 2011 01:17:37 +0900 Subject: [llvm-commits] [PATCH] CMake unittests should compile without RTTI In-Reply-To: References: <87y66oeryh.fsf@wanadoo.es> Message-ID: Doh! 2011/1/14 NAKAMURA Takumi : > Without this hack, I had seen several > "-fno-exceptions -fno-exceptions -fno-exceptions ..." and CMake would > not add "-fno-rtti", Regardless of my last patch, I can see several of "-fno-exceptions"s. I know why but I have not touched it because I would be satisfied with "just work". ...Takumi From bob.wilson at apple.com Thu Jan 13 11:45:08 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 13 Jan 2011 17:45:08 -0000 Subject: [llvm-commits] [llvm] r123380 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/copy-aggregate.ll Message-ID: <20110113174508.6BBA02A6C12C@llvm.org> Author: bwilson Date: Thu Jan 13 11:45:08 2011 New Revision: 123380 URL: http://llvm.org/viewvc/llvm-project?rev=123380&view=rev Log: Make SROA more aggressive with allocas containing padding. SROA only split up structs and arrays one level at a time, so padding can only cause trouble if it is located in between the struct or array elements. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/test/Transforms/ScalarRepl/copy-aggregate.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=123380&r1=123379&r2=123380&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Thu Jan 13 11:45:08 2011 @@ -1676,46 +1676,39 @@ } /// HasPadding - Return true if the specified type has any structure or -/// alignment padding, false otherwise. +/// alignment padding in between the elements that would be split apart +/// by SROA; return false otherwise. static bool HasPadding(const Type *Ty, const TargetData &TD) { - if (const ArrayType *ATy = dyn_cast(Ty)) - return HasPadding(ATy->getElementType(), TD); - - if (const VectorType *VTy = dyn_cast(Ty)) - return HasPadding(VTy->getElementType(), TD); - - if (const StructType *STy = dyn_cast(Ty)) { - const StructLayout *SL = TD.getStructLayout(STy); - unsigned PrevFieldBitOffset = 0; - for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { - unsigned FieldBitOffset = SL->getElementOffsetInBits(i); - - // Padding in sub-elements? - if (HasPadding(STy->getElementType(i), TD)) - return true; + if (const ArrayType *ATy = dyn_cast(Ty)) { + Ty = ATy->getElementType(); + return TD.getTypeSizeInBits(Ty) != TD.getTypeAllocSizeInBits(Ty); + } - // Check to see if there is any padding between this element and the - // previous one. - if (i) { - unsigned PrevFieldEnd = + // SROA currently handles only Arrays and Structs. + const StructType *STy = cast(Ty); + const StructLayout *SL = TD.getStructLayout(STy); + unsigned PrevFieldBitOffset = 0; + for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { + unsigned FieldBitOffset = SL->getElementOffsetInBits(i); + + // Check to see if there is any padding between this element and the + // previous one. + if (i) { + unsigned PrevFieldEnd = PrevFieldBitOffset+TD.getTypeSizeInBits(STy->getElementType(i-1)); - if (PrevFieldEnd < FieldBitOffset) - return true; - } - - PrevFieldBitOffset = FieldBitOffset; - } - - // Check for tail padding. - if (unsigned EltCount = STy->getNumElements()) { - unsigned PrevFieldEnd = PrevFieldBitOffset + - TD.getTypeSizeInBits(STy->getElementType(EltCount-1)); - if (PrevFieldEnd < SL->getSizeInBits()) + if (PrevFieldEnd < FieldBitOffset) return true; } + PrevFieldBitOffset = FieldBitOffset; } - - return TD.getTypeSizeInBits(Ty) != TD.getTypeAllocSizeInBits(Ty); + // Check for tail padding. + if (unsigned EltCount = STy->getNumElements()) { + unsigned PrevFieldEnd = PrevFieldBitOffset + + TD.getTypeSizeInBits(STy->getElementType(EltCount-1)); + if (PrevFieldEnd < SL->getSizeInBits()) + return true; + } + return false; } /// isSafeStructAllocaToScalarRepl - Check to see if the specified allocation of Modified: llvm/trunk/test/Transforms/ScalarRepl/copy-aggregate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/copy-aggregate.ll?rev=123380&r1=123379&r2=123380&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/copy-aggregate.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/copy-aggregate.ll Thu Jan 13 11:45:08 2011 @@ -1,9 +1,11 @@ -; RUN: opt < %s -scalarrepl -S | not grep alloca +; RUN: opt < %s -scalarrepl -S | FileCheck %s ; PR3290 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64" ;; Store of integer to whole alloca struct. define i32 @test1(i64 %V) nounwind { +; CHECK: test1 +; CHECK-NOT: alloca %X = alloca {{i32, i32}} %Y = bitcast {{i32,i32}}* %X to i64* store i64 %V, i64* %Y @@ -18,6 +20,8 @@ ;; Store of integer to whole struct/array alloca. define float @test2(i128 %V) nounwind { +; CHECK: test2 +; CHECK-NOT: alloca %X = alloca {[4 x float]} %Y = bitcast {[4 x float]}* %X to i128* store i128 %V, i128* %Y @@ -32,6 +36,8 @@ ;; Load of whole alloca struct as integer define i64 @test3(i32 %a, i32 %b) nounwind { +; CHECK: test3 +; CHECK-NOT: alloca %X = alloca {{i32, i32}} %A = getelementptr {{i32,i32}}* %X, i32 0, i32 0, i32 0 @@ -46,6 +52,8 @@ ;; load of integer from whole struct/array alloca. define i128 @test4(float %a, float %b) nounwind { +; CHECK: test4 +; CHECK-NOT: alloca %X = alloca {[4 x float]} %A = getelementptr {[4 x float]}* %X, i32 0, i32 0, i32 0 %B = getelementptr {[4 x float]}* %X, i32 0, i32 0, i32 3 @@ -56,3 +64,22 @@ %V = load i128* %Y ret i128 %V } + +;; If the elements of a struct or array alloca contain padding, SROA can still +;; split up the alloca as long as there is no padding between the elements. +%padded = type { i16, i8 } +%arr = type [4 x %padded] +define void @test5(%arr* %p, %arr* %q) { +entry: +; CHECK: test5 +; CHECK-NOT: i128 + %var = alloca %arr, align 4 + %vari8 = bitcast %arr* %var to i8* + %pi8 = bitcast %arr* %p to i8* + call void @llvm.memcpy.i32(i8* %vari8, i8* %pi8, i32 16, i32 4) + %qi8 = bitcast %arr* %q to i8* + call void @llvm.memcpy.i32(i8* %qi8, i8* %vari8, i32 16, i32 4) + ret void +} + +declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind From bob.wilson at apple.com Thu Jan 13 11:45:12 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 13 Jan 2011 17:45:12 -0000 Subject: [llvm-commits] [llvm] r123381 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/copy-aggregate.ll Message-ID: <20110113174512.2866C2A6C12D@llvm.org> Author: bwilson Date: Thu Jan 13 11:45:11 2011 New Revision: 123381 URL: http://llvm.org/viewvc/llvm-project?rev=123381&view=rev Log: Extend SROA to handle arrays accessed as homogeneous structs and vice versa. This is a minor extension of SROA to handle a special case that is important for some ARM NEON operations. Some of the NEON intrinsics return multiple values, which are handled as struct types containing multiple elements of the same vector type. The corresponding return types declared in the arm_neon.h header have equivalent arrays. We need SROA to recognize that it can split up those arrays and structs into separate vectors, even though they are not always accessed with the same type. SROA already handles loads and stores of an entire alloca by using insertvalue/extractvalue to access the individual pieces, and that code works the same regardless of whether the type is a struct or an array. So, all that needs to be done is to check for compatible arrays and homogeneous structs. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/test/Transforms/ScalarRepl/copy-aggregate.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=123381&r1=123380&r2=123381&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Thu Jan 13 11:45:11 2011 @@ -1076,6 +1076,46 @@ MarkUnsafe(Info); } +/// isHomogeneousAggregate - Check if type T is a struct or array containing +/// elements of the same type (which is always true for arrays). If so, +/// return true with NumElts and EltTy set to the number of elements and the +/// element type, respectively. +static bool isHomogeneousAggregate(const Type *T, unsigned &NumElts, + const Type *&EltTy) { + if (const ArrayType *AT = dyn_cast(T)) { + NumElts = AT->getNumElements(); + EltTy = AT->getElementType(); + return true; + } + if (const StructType *ST = dyn_cast(T)) { + NumElts = ST->getNumContainedTypes(); + EltTy = ST->getContainedType(0); + for (unsigned n = 1; n < NumElts; ++n) { + if (ST->getContainedType(n) != EltTy) + return false; + } + return true; + } + return false; +} + +/// isCompatibleAggregate - Check if T1 and T2 are either the same type or are +/// "homogeneous" aggregates with the same element type and number of elements. +static bool isCompatibleAggregate(const Type *T1, const Type *T2) { + if (T1 == T2) + return true; + + unsigned NumElts1, NumElts2; + const Type *EltTy1, *EltTy2; + if (isHomogeneousAggregate(T1, NumElts1, EltTy1) && + isHomogeneousAggregate(T2, NumElts2, EltTy2) && + NumElts1 == NumElts2 && + EltTy1 == EltTy2) + return true; + + return false; +} + /// isSafeMemAccess - Check if a load/store/memcpy operates on the entire AI /// alloca or has an offset and size that corresponds to a component element /// within it. The offset checked here may have been formed from a GEP with a @@ -1085,20 +1125,23 @@ AllocaInfo &Info) { // Check if this is a load/store of the entire alloca. if (Offset == 0 && MemSize == TD->getTypeAllocSize(AI->getAllocatedType())) { - bool UsesAggregateType = (MemOpType == AI->getAllocatedType()); - // This is safe for MemIntrinsics (where MemOpType is 0), integer types - // (which are essentially the same as the MemIntrinsics, especially with - // regard to copying padding between elements), or references using the - // aggregate type of the alloca. - if (!MemOpType || MemOpType->isIntegerTy() || UsesAggregateType) { - if (!UsesAggregateType) { - if (isStore) - Info.isMemCpyDst = true; - else - Info.isMemCpySrc = true; - } + // This can be safe for MemIntrinsics (where MemOpType is 0) and integer + // loads/stores (which are essentially the same as the MemIntrinsics with + // regard to copying padding between elements). But, if an alloca is + // flagged as both a source and destination of such operations, we'll need + // to check later for padding between elements. + if (!MemOpType || MemOpType->isIntegerTy()) { + if (isStore) + Info.isMemCpyDst = true; + else + Info.isMemCpySrc = true; return; } + // This is also safe for references using a type that is compatible with + // the type of the alloca, so that loads/stores can be rewritten using + // insertvalue/extractvalue. + if (isCompatibleAggregate(MemOpType, AI->getAllocatedType())) + return; } // Check if the offset/size correspond to a component within the alloca type. const Type *T = AI->getAllocatedType(); @@ -1159,7 +1202,7 @@ // address operand will be updated, so nothing else needs to be done. } else if (LoadInst *LI = dyn_cast(User)) { const Type *LIType = LI->getType(); - if (LIType == AI->getAllocatedType()) { + if (isCompatibleAggregate(LIType, AI->getAllocatedType())) { // Replace: // %res = load { i32, i32 }* %alloc // with: @@ -1184,7 +1227,7 @@ } else if (StoreInst *SI = dyn_cast(User)) { Value *Val = SI->getOperand(0); const Type *SIType = Val->getType(); - if (SIType == AI->getAllocatedType()) { + if (isCompatibleAggregate(SIType, AI->getAllocatedType())) { // Replace: // store { i32, i32 } %val, { i32, i32 }* %alloc // with: Modified: llvm/trunk/test/Transforms/ScalarRepl/copy-aggregate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/copy-aggregate.ll?rev=123381&r1=123380&r2=123381&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/copy-aggregate.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/copy-aggregate.ll Thu Jan 13 11:45:11 2011 @@ -76,10 +76,33 @@ %var = alloca %arr, align 4 %vari8 = bitcast %arr* %var to i8* %pi8 = bitcast %arr* %p to i8* - call void @llvm.memcpy.i32(i8* %vari8, i8* %pi8, i32 16, i32 4) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %vari8, i8* %pi8, i32 16, i32 4, i1 false) %qi8 = bitcast %arr* %q to i8* - call void @llvm.memcpy.i32(i8* %qi8, i8* %vari8, i32 16, i32 4) + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %qi8, i8* %vari8, i32 16, i32 4, i1 false) ret void } -declare void @llvm.memcpy.i32(i8* nocapture, i8* nocapture, i32, i32) nounwind +;; Check that an array alloca can be split up when it is also accessed with +;; a load or store as a homogeneous structure with the same element type and +;; number of elements as the array. +%homogeneous = type { <8 x i16>, <8 x i16>, <8 x i16> } +%wrapped_array = type { [3 x <8 x i16>] } +define void @test6(i8* %p, %wrapped_array* %arr) { +entry: +; CHECK: test6 +; CHECK: store <8 x i16> +; CHECK: store <8 x i16> +; CHECK: store <8 x i16> + %var = alloca %wrapped_array, align 16 + %res = call %homogeneous @test6callee(i8* %p) + %varcast = bitcast %wrapped_array* %var to %homogeneous* + store %homogeneous %res, %homogeneous* %varcast + %tmp1 = bitcast %wrapped_array* %arr to i8* + %tmp2 = bitcast %wrapped_array* %var to i8* + call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp1, i8* %tmp2, i32 48, i32 16, i1 false) + ret void +} + +declare %homogeneous @test6callee(i8* nocapture) nounwind + +declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind From simbuerg at fim.uni-passau.de Thu Jan 13 05:27:53 2011 From: simbuerg at fim.uni-passau.de (Andreas Simbuerger) Date: Thu, 13 Jan 2011 12:27:53 +0100 Subject: [llvm-commits] [PATCH] Add single entry / single exit accessors. Message-ID: <4D2EE1B9.6020408@fim.uni-passau.de> Hi, this time from the correct mail-address ;-) This patch adds support for single entry / single exit edge accessors to regions. A (refined) region that has only 2 transition edges (1 entry, 1 exit) to its parent region is defined as a simple region. Both methods added, return null if there is more than one entry/exit edge. Cheers, Andreas -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Add-single-entry-single-exit-accessors.patch Type: text/x-patch Size: 2800 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/efb671ab/attachment.bin From fvbommel at gmail.com Thu Jan 13 12:18:47 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Thu, 13 Jan 2011 19:18:47 +0100 Subject: [llvm-commits] [llvm] r123381 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/copy-aggregate.ll In-Reply-To: <20110113174512.2866C2A6C12D@llvm.org> References: <20110113174512.2866C2A6C12D@llvm.org> Message-ID: On Thu, Jan 13, 2011 at 6:45 PM, Bob Wilson wrote: > +/// isHomogeneousAggregate - Check if type T is a struct or array containing > +/// elements of the same type (which is always true for arrays). ?If so, > +/// return true with NumElts and EltTy set to the number of elements and the > +/// element type, respectively. > +static bool isHomogeneousAggregate(const Type *T, unsigned &NumElts, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const Type *&EltTy) { > + ?if (const ArrayType *AT = dyn_cast(T)) { > + ? ?NumElts = AT->getNumElements(); > + ? ?EltTy = AT->getElementType(); > + ? ?return true; > + ?} > + ?if (const StructType *ST = dyn_cast(T)) { > + ? ?NumElts = ST->getNumContainedTypes(); > + ? ?EltTy = ST->getContainedType(0); I don't think that works for empty structs... > + ? ?for (unsigned n = 1; n < NumElts; ++n) { > + ? ? ?if (ST->getContainedType(n) != EltTy) > + ? ? ? ?return false; > + ? ?} > + ? ?return true; > + ?} > + ?return false; > +} From bob.wilson at apple.com Thu Jan 13 12:26:59 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 13 Jan 2011 18:26:59 -0000 Subject: [llvm-commits] [llvm] r123383 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <20110113182659.9D0AF2A6C12C@llvm.org> Author: bwilson Date: Thu Jan 13 12:26:59 2011 New Revision: 123383 URL: http://llvm.org/viewvc/llvm-project?rev=123383&view=rev Log: Check for empty structs, and for consistency, zero-element arrays. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=123383&r1=123382&r2=123383&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Thu Jan 13 12:26:59 2011 @@ -1084,12 +1084,12 @@ const Type *&EltTy) { if (const ArrayType *AT = dyn_cast(T)) { NumElts = AT->getNumElements(); - EltTy = AT->getElementType(); + EltTy = (NumElts == 0 ? 0 : AT->getElementType()); return true; } if (const StructType *ST = dyn_cast(T)) { NumElts = ST->getNumContainedTypes(); - EltTy = ST->getContainedType(0); + EltTy = (NumElts == 0 ? 0 : ST->getContainedType(0)); for (unsigned n = 1; n < NumElts; ++n) { if (ST->getContainedType(n) != EltTy) return false; From bob.wilson at apple.com Thu Jan 13 12:30:26 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 13 Jan 2011 10:30:26 -0800 Subject: [llvm-commits] [llvm] r123381 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/copy-aggregate.ll In-Reply-To: References: <20110113174512.2866C2A6C12D@llvm.org> Message-ID: <1D8CF8A5-E04B-4355-96A5-347391340C2F@apple.com> On Jan 13, 2011, at 10:18 AM, Frits van Bommel wrote: > On Thu, Jan 13, 2011 at 6:45 PM, Bob Wilson wrote: >> +/// isHomogeneousAggregate - Check if type T is a struct or array containing >> +/// elements of the same type (which is always true for arrays). If so, >> +/// return true with NumElts and EltTy set to the number of elements and the >> +/// element type, respectively. >> +static bool isHomogeneousAggregate(const Type *T, unsigned &NumElts, >> + const Type *&EltTy) { >> + if (const ArrayType *AT = dyn_cast(T)) { >> + NumElts = AT->getNumElements(); >> + EltTy = AT->getElementType(); >> + return true; >> + } >> + if (const StructType *ST = dyn_cast(T)) { >> + NumElts = ST->getNumContainedTypes(); >> + EltTy = ST->getContainedType(0); > > I don't think that works for empty structs... Right. Fixed in r123383. Thanks! From stoklund at 2pi.dk Thu Jan 13 12:41:05 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 13 Jan 2011 18:41:05 -0000 Subject: [llvm-commits] [llvm] r123384 - in /llvm/trunk/lib/CodeGen: MachineBasicBlock.cpp PHIElimination.cpp Message-ID: <20110113184105.758CC2A6C12D@llvm.org> Author: stoklund Date: Thu Jan 13 12:41:05 2011 New Revision: 123384 URL: http://llvm.org/viewvc/llvm-project?rev=123384&view=rev Log: Teach MachineBasicBlock::getFirstTerminator to ignore debug values. It will still return an iterator that points to the first terminator or end(), but there may be DBG_VALUE instructions following the first terminator. Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=123384&r1=123383&r2=123384&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Thu Jan 13 12:41:05 2011 @@ -155,11 +155,22 @@ } MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() { - iterator I = end(); - while (I != begin() && (--I)->getDesc().isTerminator()) - ; /*noop */ - if (I != end() && !I->getDesc().isTerminator()) ++I; - return I; + iterator B = begin(), I = end(); + iterator Term = I; + while (I != B) { + --I; + // Ignore any debug values after the first terminator. + if (I->isDebugValue()) + continue; + // Stop once we see a non-debug non-terminator. + if (!I->getDesc().isTerminator()) + break; + // Earliest terminator so far. + Term = I; + } + // Return the first terminator, or end(). + // Everything after Term is terminators and debug values. + return Term; } void MachineBasicBlock::dump() const { Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=123384&r1=123383&r2=123384&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Thu Jan 13 12:41:05 2011 @@ -339,6 +339,8 @@ #ifndef NDEBUG for (MachineBasicBlock::iterator TI = llvm::next(Term); TI != opBlock.end(); ++TI) { + if (TI->isDebugValue()) + continue; assert(!TI->readsRegister(SrcReg) && "Terminator instructions cannot use virtual registers unless" "they are the first terminator in a block!"); From 6yearold at gmail.com Thu Jan 13 12:48:33 2011 From: 6yearold at gmail.com (arrowdodger) Date: Thu, 13 Jan 2011 21:48:33 +0300 Subject: [llvm-commits] [PATCH][CMake] More symbols checks. Message-ID: This patch enables checks for various functions. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/2bcc1ca2/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: symbols.cmake.patch Type: text/x-patch Size: 3196 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/2bcc1ca2/attachment.bin From grosbach at apple.com Thu Jan 13 13:16:48 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 13 Jan 2011 19:16:48 -0000 Subject: [llvm-commits] [llvm] r123387 - /llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Message-ID: <20110113191648.B39B92A6C12C@llvm.org> Author: grosbach Date: Thu Jan 13 13:16:48 2011 New Revision: 123387 URL: http://llvm.org/viewvc/llvm-project?rev=123387&view=rev Log: When updating a tSpill/tRestore instruction to be a tSTRr/tLDRr, correctly set up the source operands. The original instr has an immediate operand that should be replaced with the frame reg operand rather than just adding the reg operand. Previously, the instruction ended up with too many operands causing an assert() when adding the default predicate. rdar://8825456 Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=123387&r1=123386&r2=123387&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Thu Jan 13 13:16:48 2011 @@ -659,8 +659,9 @@ MI.setDesc(TII.get(UseRR ? ARM::tLDRr : ARM::tLDRi)); MI.getOperand(i).ChangeToRegister(TmpReg, false, false, true); if (UseRR) - // Use [reg, reg] addrmode. - MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); + // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame + // register. The offset is already handled in the vreg value. + MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false); } else if (Desc.mayStore()) { VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass); bool UseRR = false; @@ -678,8 +679,10 @@ *this, dl); MI.setDesc(TII.get(UseRR ? ARM::tSTRr : ARM::tSTRi)); MI.getOperand(i).ChangeToRegister(VReg, false, false, true); - if (UseRR) // Use [reg, reg] addrmode. - MI.addOperand(MachineOperand::CreateReg(FrameReg, false)); + if (UseRR) + // Use [reg, reg] addrmode. Replace the immediate operand w/ the frame + // register. The offset is already handled in the vreg value. + MI.getOperand(i+1).ChangeToRegister(FrameReg, false, false, false); } else { assert(false && "Unexpected opcode!"); } From ofv at wanadoo.es Thu Jan 13 13:17:28 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Thu, 13 Jan 2011 19:17:28 -0000 Subject: [llvm-commits] [llvm] r123388 - in /llvm/trunk: cmake/config-ix.cmake include/llvm/Config/config.h.cmake Message-ID: <20110113191728.D3EE82A6C12C@llvm.org> Author: ofv Date: Thu Jan 13 13:17:28 2011 New Revision: 123388 URL: http://llvm.org/viewvc/llvm-project?rev=123388&view=rev Log: Add some platform tests. Patch by arrowdodger! Modified: llvm/trunk/cmake/config-ix.cmake llvm/trunk/include/llvm/Config/config.h.cmake Modified: llvm/trunk/cmake/config-ix.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=123388&r1=123387&r2=123388&view=diff ============================================================================== --- llvm/trunk/cmake/config-ix.cmake (original) +++ llvm/trunk/cmake/config-ix.cmake Thu Jan 13 13:17:28 2011 @@ -101,6 +101,11 @@ check_symbol_exists(mkdtemp "stdlib.h;unistd.h" HAVE_MKDTEMP) check_symbol_exists(mkstemp "stdlib.h;unistd.h" HAVE_MKSTEMP) check_symbol_exists(mktemp "stdlib.h;unistd.h" HAVE_MKTEMP) +check_symbol_exists(closedir "sys/types.h;dirent.h" HAVE_CLOSEDIR) +check_symbol_exists(opendir "sys/types.h;dirent.h" HAVE_OPENDIR) +check_symbol_exists(getcwd unistd.h HAVE_GETCWD) +check_symbol_exists(gettimeofday sys/time.h HAVE_GETTIMEOFDAY) +check_symbol_exists(getrlimit "sys/types.h;sys/time.h;sys/resource.h" HAVE_GETRLIMIT) if( NOT LLVM_ON_WIN32 ) check_symbol_exists(pthread_mutex_lock pthread.h HAVE_PTHREAD_MUTEX_LOCK) endif() @@ -109,6 +114,8 @@ check_symbol_exists(strerror string.h HAVE_STRERROR) check_symbol_exists(strerror_r string.h HAVE_STRERROR_R) check_symbol_exists(strerror_s string.h HAVE_STRERROR_S) +check_symbol_exists(memcpy string.h HAVE_MEMCPY) +check_symbol_exists(memmove string.h HAVE_MEMMOVE) check_symbol_exists(setenv stdlib.h HAVE_SETENV) if ( LLVM_ON_WIN32 ) check_symbol_exists(_chsize_s io.h HAVE__CHSIZE_S) Modified: llvm/trunk/include/llvm/Config/config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=123388&r1=123387&r2=123388&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/config.h.cmake Thu Jan 13 13:17:28 2011 @@ -73,7 +73,7 @@ #cmakedefine HAVE_CIRCO ${HAVE_CIRCO} /* Define to 1 if you have the `closedir' function. */ -#undef HAVE_CLOSEDIR +#cmakedefine HAVE_CLOSEDIR ${HAVE_CLOSEDIR} /* Define to 1 if you have the header file. */ #cmakedefine HAVE_CTYPE_H ${HAVE_CTYPE_H} @@ -137,19 +137,19 @@ #undef HAVE_FWD_ITERATOR /* Define to 1 if you have the `getcwd' function. */ -#undef HAVE_GETCWD +#cmakedefine HAVE_GETCWD ${HAVE_GETCWD} /* Define to 1 if you have the `getpagesize' function. */ #cmakedefine HAVE_GETPAGESIZE ${HAVE_GETPAGESIZE} /* Define to 1 if you have the `getrlimit' function. */ -#undef HAVE_GETRLIMIT +#cmakedefine HAVE_GETRLIMIT ${HAVE_GETRLIMIT} /* Define to 1 if you have the `getrusage' function. */ #cmakedefine HAVE_GETRUSAGE ${HAVE_GETRUSAGE} /* Define to 1 if you have the `gettimeofday' function. */ -#undef HAVE_GETTIMEOFDAY +#cmakedefine HAVE_GETTIMEOFDAY ${HAVE_GETTIMEOFDAY} /* Does not have */ #undef HAVE_GLOBAL_HASH_MAP @@ -243,10 +243,10 @@ #cmakedefine HAVE_MALLOC_ZONE_STATISTICS ${HAVE_MALLOC_ZONE_STATISTICS} /* Define to 1 if you have the `memcpy' function. */ -#undef HAVE_MEMCPY +#cmakedefine HAVE_MEMCPY ${HAVE_MEMCPY} /* Define to 1 if you have the `memmove' function. */ -#undef HAVE_MEMMOVE +#cmakedefine HAVE_MEMMOVE ${HAVE_MEMMOVE} /* Define to 1 if you have the header file. */ #cmakedefine HAVE_MEMORY_H ${HAVE_MEMORY_H} @@ -283,7 +283,7 @@ #cmakedefine HAVE_NEATO ${HAVE_NEATO} /* Define to 1 if you have the `opendir' function. */ -#undef HAVE_OPENDIR +#cmakedefine HAVE_OPENDIR ${HAVE_OPENDIR} /* Define if libtool can extract symbol lists from object files. */ #undef HAVE_PRELOADED_SYMBOLS From simbuerg at googlemail.com Thu Jan 13 13:21:13 2011 From: simbuerg at googlemail.com (Andreas Simbuerger) Date: Thu, 13 Jan 2011 20:21:13 +0100 Subject: [llvm-commits] [PATCH] Add single entry / single exit accessors. In-Reply-To: <4D2F1A59.3020305@fim.uni-passau.de> References: <4D2EE1B9.6020408@fim.uni-passau.de> <4D2F1A59.3020305@fim.uni-passau.de> Message-ID: <4D2F50A9.2090803@googlemail.com> Am 13.01.2011 16:29, schrieb Tobias Grosser: > On 01/13/2011 06:27 AM, Andreas Simbuerger wrote: >> Hi, >> >> this time from the correct mail-address;-) >> This patch adds support for single entry / single exit edge >> accessors to regions. > > Thanks, Andreas. Just some small comments inline. > >> A (refined) region that has only 2 transition edges (1 entry, 1 exit) >> to its parent region is defined as a simple region. >> >> Both methods added, return null if there is more than one entry/exit >> edge. >> >> Cheers, >> Andreas >> >> >> >> 0001-Add-single-entry-single-exit-accessors.patch >> >> >> diff --git include/llvm/Analysis/RegionInfo.h >> include/llvm/Analysis/RegionInfo.h >> index 737d46c..4c06ec0 100644 >> --- include/llvm/Analysis/RegionInfo.h >> +++ include/llvm/Analysis/RegionInfo.h >> @@ -305,6 +305,20 @@ public: >> /// NULL if such a basic block does not exist. >> Region *getExpandedRegion() const; >> >> + /// @brief Return the first block of this region's single entry edge, >> + /// if existing. >> + /// >> + /// @return The BasicBlock starting this region's single entry edge, >> + /// else NULL. >> + BasicBlock *getSingleEntryBlock() const; > I would call this getEnteringBlock() following LoopInfo in this case. Ok :-) > > >> + >> + /// @brief Return the first block of this region's single exit edge, >> + /// if existing. >> + /// >> + /// @return The BasicBlock starting this region's single exit edge, >> + /// else NULL. >> + BasicBlock *getSingleExitBlock() const; > getExitingBlock() would follow LoopInfo probably. Done. > > >> /// @brief Is this a simple region? >> /// >> /// A region is simple if it has exactly one exit and one entry edge. >> diff --git lib/Analysis/RegionInfo.cpp lib/Analysis/RegionInfo.cpp >> index cf48a71..22e822b 100644 >> --- lib/Analysis/RegionInfo.cpp >> +++ lib/Analysis/RegionInfo.cpp >> @@ -131,43 +131,55 @@ Loop *Region::outermostLoopInRegion(Loop *L) >> const { >> Loop*Region::outermostLoopInRegion(LoopInfo *LI, BasicBlock* BB) >> const { >> assert(LI&& BB&& "LI and BB cannot be null!"); >> Loop *L = LI->getLoopFor(BB); >> + I just noticed that this does not belong to the patch, removed. >> return outermostLoopInRegion(L); >> } >> >> -bool Region::isSimple() const { >> - bool isSimple = true; >> - bool found = false; >> - >> - BasicBlock *entry = getEntry(), *exit = getExit(); >> - >> - if (isTopLevelRegion()) >> - return false; >> +BasicBlock *Region::getSingleEntryBlock() const { >> + BasicBlock *entry = getEntry(); >> + BasicBlock *Pred; >> + BasicBlock *ee = 0; >> >> for (pred_iterator PI = pred_begin(entry), PE = pred_end(entry); >> PI != PE; >> ++PI) { >> - BasicBlock *Pred = *PI; >> + Pred = *PI; >> if (DT->getNode(Pred)&& !contains(Pred)) { >> - if (found) { >> - isSimple = false; >> - break; >> - } >> - found = true; >> + if (ee) >> + return 0; >> + >> + ee = Pred; > Can you combine the two if conditions? I don't understand, as the predicate (DT->getNode(Pred) && !contains(Pred)) has to be valid for both statements inside the block, so I would have to recheck that in an else branch after merging both if's? Perhaps I'm just not thinking clearly, it's a bit late ;-) > >> } >> } >> >> - found = false; >> + return ee; >> +} > Maybe use a more expressive variable name instead of 'ee'. Maybe > something like 'enteringBlock'? Done. > >> +BasicBlock *Region::getSingleExitBlock() const { >> + BasicBlock *exit = getExit(); >> + BasicBlock *Pred; >> + BasicBlock *ee = 0; >> + >> + if (!exit) >> + return 0; >> >> for (pred_iterator PI = pred_begin(exit), PE = pred_end(exit); PI >> != PE; >> - ++PI) >> - if (contains(*PI)) { >> - if (found) { >> - isSimple = false; >> - break; >> - } >> - found = true; >> + ++PI) { >> + Pred = *PI; >> + if (contains(Pred)) { >> + if (ee) >> + return 0; >> + >> + ee = Pred; >> } >> + } >> >> - return isSimple; >> + return ee; >> +} > Same comments apply here. Done. > > >> +bool Region::isSimple() const { >> + return !(isTopLevelRegion()) >> +&& (getSingleEntryBlock() != 0) >> +&& (getSingleExitBlock() != 0); > I am not sure if my email has removed some spaces/tabs. But please > recheck indentation. I think so, the indentation is correct within my mail client. I attached two versions of the patch without *.svn.patch was generated using git diff --no-prefix ... and the other one was generated using git format-patch. > > Thanks > > Tobi > Cheers, Andreas -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Add-single-entry-single-exit-accessors.patch Type: text/x-patch Size: 3432 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/af962547/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Add-single-entry-single-exit-accessors.svn.patch Type: text/x-patch Size: 2730 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/af962547/attachment-0001.bin From ofv at wanadoo.es Thu Jan 13 13:22:18 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Thu, 13 Jan 2011 20:22:18 +0100 Subject: [llvm-commits] [PATCH][CMake] More symbols checks. In-Reply-To: (arrowdodger's message of "Thu, 13 Jan 2011 21:48:33 +0300") References: Message-ID: <87pqs0ehhx.fsf@wanadoo.es> arrowdodger <6yearold at gmail.com> writes: > This patch enables checks for various functions. Applied. Thanks. From dpatel at apple.com Thu Jan 13 13:27:50 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 13 Jan 2011 19:27:50 -0000 Subject: [llvm-commits] [llvm] r123389 - in /llvm/trunk/lib/CodeGen: MachineBasicBlock.cpp PHIElimination.cpp Message-ID: <20110113192750.AB9272A6C12C@llvm.org> Author: dpatel Date: Thu Jan 13 13:27:50 2011 New Revision: 123389 URL: http://llvm.org/viewvc/llvm-project?rev=123389&view=rev Log: Speculatively revert r123384 to make llvm-gcc-i386-linux-selfhost buildbot happy. Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=123389&r1=123388&r2=123389&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Thu Jan 13 13:27:50 2011 @@ -155,22 +155,11 @@ } MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() { - iterator B = begin(), I = end(); - iterator Term = I; - while (I != B) { - --I; - // Ignore any debug values after the first terminator. - if (I->isDebugValue()) - continue; - // Stop once we see a non-debug non-terminator. - if (!I->getDesc().isTerminator()) - break; - // Earliest terminator so far. - Term = I; - } - // Return the first terminator, or end(). - // Everything after Term is terminators and debug values. - return Term; + iterator I = end(); + while (I != begin() && (--I)->getDesc().isTerminator()) + ; /*noop */ + if (I != end() && !I->getDesc().isTerminator()) ++I; + return I; } void MachineBasicBlock::dump() const { Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=123389&r1=123388&r2=123389&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Thu Jan 13 13:27:50 2011 @@ -339,8 +339,6 @@ #ifndef NDEBUG for (MachineBasicBlock::iterator TI = llvm::next(Term); TI != opBlock.end(); ++TI) { - if (TI->isDebugValue()) - continue; assert(!TI->readsRegister(SrcReg) && "Terminator instructions cannot use virtual registers unless" "they are the first terminator in a block!"); From dpatel at apple.com Thu Jan 13 13:48:54 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 13 Jan 2011 19:48:54 -0000 Subject: [llvm-commits] [llvm] r123390 - /llvm/trunk/tools/bugpoint/bugpoint.cpp Message-ID: <20110113194854.804912A6C12C@llvm.org> Author: dpatel Date: Thu Jan 13 13:48:54 2011 New Revision: 123390 URL: http://llvm.org/viewvc/llvm-project?rev=123390&view=rev Log: Little help to debug the bugpoint itself. Patch by Bob Wilson. Modified: llvm/trunk/tools/bugpoint/bugpoint.cpp Modified: llvm/trunk/tools/bugpoint/bugpoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/bugpoint.cpp?rev=123390&r1=123389&r2=123390&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/bugpoint.cpp (original) +++ llvm/trunk/tools/bugpoint/bugpoint.cpp Thu Jan 13 13:48:54 2011 @@ -27,6 +27,10 @@ #include "llvm/Support/Signals.h" #include "llvm/Support/Valgrind.h" #include "llvm/LinkAllVMCore.h" + +// Enable this macro to debug bugpoint itself. +#define DEBUG_BUGPOINT 0 + using namespace llvm; static cl::opt @@ -71,9 +75,11 @@ /// BugpointIsInterrupted - Set to true when the user presses ctrl-c. bool llvm::BugpointIsInterrupted = false; +#ifndef DEBUG_BUGPOINT static void BugpointInterruptFunction() { BugpointIsInterrupted = true; } +#endif // Hack to capture a pass list. namespace { @@ -91,9 +97,11 @@ } int main(int argc, char **argv) { +#ifndef DEBUG_BUGPOINT llvm::sys::PrintStackTraceOnErrorSignal(); llvm::PrettyStackTraceProgram X(argc, argv); llvm_shutdown_obj Y; // Call llvm_shutdown() on exit. +#endif // Initialize passes PassRegistry &Registry = *PassRegistry::getPassRegistry(); @@ -111,7 +119,9 @@ "LLVM automatic testcase reducer. See\nhttp://" "llvm.org/cmds/bugpoint.html" " for more information.\n"); +#ifndef DEBUG_BUGPOINT sys::SetInterruptFunction(BugpointInterruptFunction); +#endif LLVMContext& Context = getGlobalContext(); // If we have an override, set it and then track the triple we want Modules @@ -160,7 +170,9 @@ // Bugpoint has the ability of generating a plethora of core files, so to // avoid filling up the disk, we prevent it +#ifndef DEBUG_BUGPOINT sys::Process::PreventCoreFiles(); +#endif std::string Error; bool Failure = D.run(Error); From enderby at apple.com Thu Jan 13 14:32:36 2011 From: enderby at apple.com (Kevin Enderby) Date: Thu, 13 Jan 2011 20:32:36 -0000 Subject: [llvm-commits] [llvm] r123393 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110113203236.ECC062A6C12C@llvm.org> Author: enderby Date: Thu Jan 13 14:32:36 2011 New Revision: 123393 URL: http://llvm.org/viewvc/llvm-project?rev=123393&view=rev Log: Fix ARMAsmParser::ParseOperand() to allow it to parse . as a branch target and directional local labels like 1f and 2b. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123393&r1=123392&r2=123393&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jan 13 14:32:36 2011 @@ -840,10 +840,12 @@ default: Error(Parser.getTok().getLoc(), "unexpected token in operand"); return true; - case AsmToken::Identifier: { + case AsmToken::Identifier: if (!TryParseRegisterWithWriteBack(Operands)) return false; - + // Fall though for the Identifier case that is not a register + case AsmToken::Integer: // things like 1f and 2b as a branch targets + case AsmToken::Dot: { // . as a branch target // This was not a register so parse other operands that start with an // identifier (like labels) as expressions and create them as immediates. const MCExpr *IdVal; From bob.wilson at apple.com Thu Jan 13 14:59:44 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 13 Jan 2011 20:59:44 -0000 Subject: [llvm-commits] [llvm] r123396 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <20110113205944.E361F2A6C12C@llvm.org> Author: bwilson Date: Thu Jan 13 14:59:44 2011 New Revision: 123396 URL: http://llvm.org/viewvc/llvm-project?rev=123396&view=rev Log: Fix whitespace. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=123396&r1=123395&r2=123396&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Thu Jan 13 14:59:44 2011 @@ -77,7 +77,7 @@ private: TargetData *TD; - + /// DeadInsts - Keep track of instructions we have made dead, so that /// we can remove them after we are done working. SmallVector DeadInsts; @@ -88,7 +88,7 @@ struct AllocaInfo { /// isUnsafe - This is set to true if the alloca cannot be SROA'd. bool isUnsafe : 1; - + /// isMemCpySrc - This is true if this aggregate is memcpy'd from. bool isMemCpySrc : 1; @@ -98,7 +98,7 @@ AllocaInfo() : isUnsafe(false), isMemCpySrc(false), isMemCpyDst(false) {} }; - + unsigned SRThreshold; void MarkUnsafe(AllocaInfo &I) { I.isUnsafe = true; } @@ -114,11 +114,11 @@ bool TypeHasComponent(const Type *T, uint64_t Offset, uint64_t Size); uint64_t FindElementAndOffset(const Type *&T, uint64_t &Offset, const Type *&IdxTy); - - void DoScalarReplacement(AllocaInst *AI, + + void DoScalarReplacement(AllocaInst *AI, std::vector &WorkList); void DeleteDeadInstructions(); - + void RewriteForScalarRepl(Instruction *I, AllocaInst *AI, uint64_t Offset, SmallVector &NewElts); void RewriteBitCast(BitCastInst *BC, AllocaInst *AI, uint64_t Offset, @@ -132,7 +132,7 @@ SmallVector &NewElts); void RewriteLoadUserOfWholeAlloca(LoadInst *LI, AllocaInst *AI, SmallVector &NewElts); - + static MemTransferInst *isOnlyCopiedFromConstantGlobal(AllocaInst *AI); }; } @@ -146,7 +146,7 @@ "Scalar Replacement of Aggregates", false, false) // Public interface to the ScalarReplAggregates pass -FunctionPass *llvm::createScalarReplAggregatesPass(signed int Threshold) { +FunctionPass *llvm::createScalarReplAggregatesPass(signed int Threshold) { return new SROA(Threshold); } @@ -163,16 +163,16 @@ /// AllocaSize - The size of the alloca being considered. unsigned AllocaSize; const TargetData &TD; - + /// IsNotTrivial - This is set to true if there is some access to the object /// which means that mem2reg can't promote it. bool IsNotTrivial; - + /// VectorTy - This tracks the type that we should promote the vector to if /// it is possible to turn it into a vector. This starts out null, and if it /// isn't possible to turn into a vector type, it gets set to VoidTy. const Type *VectorTy; - + /// HadAVector - True if there is at least one vector access to the alloca. /// We don't want to turn random arrays into vectors and use vector element /// insert/extract, but if there are element accesses to something that is @@ -186,14 +186,14 @@ VectorTy = 0; HadAVector = false; } - + AllocaInst *TryConvert(AllocaInst *AI); - + private: bool CanConvertToScalar(Value *V, uint64_t Offset); void MergeInType(const Type *In, uint64_t Offset); void ConvertUsesToScalar(Value *Ptr, AllocaInst *NewAI, uint64_t Offset); - + Value *ConvertScalar_ExtractValue(Value *NV, const Type *ToType, uint64_t Offset, IRBuilder<> &Builder); Value *ConvertScalar_InsertValue(Value *StoredVal, Value *ExistingVal, @@ -210,7 +210,7 @@ if (!Triple.startswith("i386") && !Triple.startswith("x86_64")) return false; - + // Reject all the MMX vector types. switch (VTy->getNumElements()) { default: return false; @@ -230,7 +230,7 @@ // out. if (!CanConvertToScalar(AI, 0) || !IsNotTrivial) return 0; - + // If we were able to find a vector type that can handle this with // insert/extract elements, and if there was at least one use that had // a vector type, promote this to a vector. We don't want to promote @@ -270,7 +270,7 @@ // nothing to be done. if (VectorTy && VectorTy->isVoidTy()) return; - + // If this could be contributing to a vector, analyze it. // If the In type is a vector that is the same size as the alloca, see if it @@ -278,7 +278,7 @@ if (const VectorType *VInTy = dyn_cast(In)) { // Remember if we saw a vector type. HadAVector = true; - + if (VInTy->getBitWidth()/8 == AllocaSize && Offset == 0) { // If we're storing/loading a vector of the right size, allow it as a // vector. If this the first vector we see, remember the type so that @@ -297,7 +297,7 @@ // compatible with it. unsigned EltSize = In->getPrimitiveSizeInBits()/8; if (Offset % EltSize == 0 && AllocaSize % EltSize == 0 && - (VectorTy == 0 || + (VectorTy == 0 || cast(VectorTy)->getElementType() ->getPrimitiveSizeInBits()/8 == EltSize)) { if (VectorTy == 0) @@ -305,7 +305,7 @@ return; } } - + // Otherwise, we have a case that we can't handle with an optimized vector // form. We can still turn this into a large integer. VectorTy = Type::getVoidTy(In->getContext()); @@ -323,7 +323,7 @@ bool ConvertToScalarInfo::CanConvertToScalar(Value *V, uint64_t Offset) { for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI!=E; ++UI) { Instruction *User = cast(*UI); - + if (LoadInst *LI = dyn_cast(User)) { // Don't break volatile loads. if (LI->isVolatile()) @@ -334,7 +334,7 @@ MergeInType(LI->getType(), Offset); continue; } - + if (StoreInst *SI = dyn_cast(User)) { // Storing the pointer, not into the value? if (SI->getOperand(0) == V || SI->isVolatile()) return false; @@ -344,7 +344,7 @@ MergeInType(SI->getOperand(0)->getType(), Offset); continue; } - + if (BitCastInst *BCI = dyn_cast(User)) { IsNotTrivial = true; // Can't be mem2reg'd. if (!CanConvertToScalar(BCI, Offset)) @@ -356,7 +356,7 @@ // If this is a GEP with a variable indices, we can't handle it. if (!GEP->hasAllConstantIndices()) return false; - + // Compute the offset that this GEP adds to the pointer. SmallVector Indices(GEP->op_begin()+1, GEP->op_end()); uint64_t GEPOffset = TD.getIndexedOffset(GEP->getPointerOperandType(), @@ -385,15 +385,15 @@ ConstantInt *Len = dyn_cast(MTI->getLength()); if (Len == 0 || Len->getZExtValue() != AllocaSize || Offset != 0) return false; - + IsNotTrivial = true; // Can't be mem2reg'd. continue; } - + // Otherwise, we cannot handle this! return false; } - + return true; } @@ -424,9 +424,9 @@ GEP->eraseFromParent(); continue; } - + IRBuilder<> Builder(User); - + if (LoadInst *LI = dyn_cast(User)) { // The load is a bit extract from NewAI shifted right by Offset bits. Value *LoadedVal = Builder.CreateLoad(NewAI, "tmp"); @@ -436,7 +436,7 @@ LI->eraseFromParent(); continue; } - + if (StoreInst *SI = dyn_cast(User)) { assert(SI->getOperand(0) != Ptr && "Consistency error!"); Instruction *Old = Builder.CreateLoad(NewAI, NewAI->getName()+".in"); @@ -444,14 +444,14 @@ Builder); Builder.CreateStore(New, NewAI); SI->eraseFromParent(); - + // If the load we just inserted is now dead, then the inserted store // overwrote the entire thing. if (Old->use_empty()) Old->eraseFromParent(); continue; } - + // If this is a constant sized memset of a constant value (e.g. 0) we can // transform it into a store of the expanded constant value. if (MemSetInst *MSI = dyn_cast(User)) { @@ -459,7 +459,7 @@ unsigned NumBytes = cast(MSI->getLength())->getZExtValue(); if (NumBytes != 0) { unsigned Val = cast(MSI->getValue())->getZExtValue(); - + // Compute the value replicated the right number of times. APInt APVal(NumBytes*8, Val); @@ -467,17 +467,17 @@ if (Val) for (unsigned i = 1; i != NumBytes; ++i) APVal |= APVal << 8; - + Instruction *Old = Builder.CreateLoad(NewAI, NewAI->getName()+".in"); Value *New = ConvertScalar_InsertValue( ConstantInt::get(User->getContext(), APVal), Old, Offset, Builder); Builder.CreateStore(New, NewAI); - + // If the load we just inserted is now dead, then the memset overwrote // the entire thing. if (Old->use_empty()) - Old->eraseFromParent(); + Old->eraseFromParent(); } MSI->eraseFromParent(); continue; @@ -487,12 +487,12 @@ // can handle it like a load or store of the scalar type. if (MemTransferInst *MTI = dyn_cast(User)) { assert(Offset == 0 && "must be store to start of alloca"); - + // If the source and destination are both to the same alloca, then this is // a noop copy-to-self, just delete it. Otherwise, emit a load and store // as appropriate. AllocaInst *OrigAI = cast(GetUnderlyingObject(Ptr, 0)); - + if (GetUnderlyingObject(MTI->getSource(), 0) != OrigAI) { // Dest must be OrigAI, change this to be a load from the original // pointer (bitcasted), then a store to our new alloca. @@ -532,7 +532,7 @@ MTI->eraseFromParent(); continue; } - + llvm_unreachable("Unsupported operation!"); } } @@ -574,7 +574,7 @@ V = Builder.CreateBitCast(V, ToType, "tmp"); return V; } - + // If ToType is a first class aggregate, extract out each of the pieces and // use insertvalue's to form the FCA. if (const StructType *ST = dyn_cast(ToType)) { @@ -588,7 +588,7 @@ } return Res; } - + if (const ArrayType *AT = dyn_cast(ToType)) { uint64_t EltSize = TD.getTypeAllocSizeInBits(AT->getElementType()); Value *Res = UndefValue::get(AT); @@ -624,7 +624,7 @@ ConstantInt::get(FromVal->getType(), ShAmt), "tmp"); else if (ShAmt < 0 && (unsigned)-ShAmt < NTy->getBitWidth()) - FromVal = Builder.CreateShl(FromVal, + FromVal = Builder.CreateShl(FromVal, ConstantInt::get(FromVal->getType(), -ShAmt), "tmp"); @@ -632,11 +632,11 @@ unsigned LIBitWidth = TD.getTypeSizeInBits(ToType); if (LIBitWidth < NTy->getBitWidth()) FromVal = - Builder.CreateTrunc(FromVal, IntegerType::get(FromVal->getContext(), + Builder.CreateTrunc(FromVal, IntegerType::get(FromVal->getContext(), LIBitWidth), "tmp"); else if (LIBitWidth > NTy->getBitWidth()) FromVal = - Builder.CreateZExt(FromVal, IntegerType::get(FromVal->getContext(), + Builder.CreateZExt(FromVal, IntegerType::get(FromVal->getContext(), LIBitWidth), "tmp"); // If the result is an integer, this is a trunc or bitcast. @@ -673,7 +673,7 @@ if (const VectorType *VTy = dyn_cast(AllocaType)) { uint64_t VecSize = TD.getTypeAllocSizeInBits(VTy); uint64_t ValSize = TD.getTypeAllocSizeInBits(SV->getType()); - + // Changing the whole vector with memset or with an access of a different // vector type? if (ValSize == VecSize) @@ -683,28 +683,28 @@ // Must be an element insertion. unsigned Elt = Offset/EltSize; - + if (SV->getType() != VTy->getElementType()) SV = Builder.CreateBitCast(SV, VTy->getElementType(), "tmp"); - - SV = Builder.CreateInsertElement(Old, SV, + + SV = Builder.CreateInsertElement(Old, SV, ConstantInt::get(Type::getInt32Ty(SV->getContext()), Elt), "tmp"); return SV; } - + // If SV is a first-class aggregate value, insert each value recursively. if (const StructType *ST = dyn_cast(SV->getType())) { const StructLayout &Layout = *TD.getStructLayout(ST); for (unsigned i = 0, e = ST->getNumElements(); i != e; ++i) { Value *Elt = Builder.CreateExtractValue(SV, i, "tmp"); - Old = ConvertScalar_InsertValue(Elt, Old, + Old = ConvertScalar_InsertValue(Elt, Old, Offset+Layout.getElementOffsetInBits(i), Builder); } return Old; } - + if (const ArrayType *AT = dyn_cast(SV->getType())) { uint64_t EltSize = TD.getTypeAllocSizeInBits(AT->getElementType()); for (unsigned i = 0, e = AT->getNumElements(); i != e; ++i) { @@ -868,7 +868,7 @@ while (!WorkList.empty()) { AllocaInst *AI = WorkList.back(); WorkList.pop_back(); - + // Handle dead allocas trivially. These can be formed by SROA'ing arrays // with unused elements. if (AI->use_empty()) { @@ -880,7 +880,7 @@ // If this alloca is impossible for us to promote, reject it early. if (AI->isArrayAllocation() || !AI->getAllocatedType()->isSized()) continue; - + // Check to see if this allocation is only modified by a memcpy/memmove from // a constant global. If this is the case, we can change all users to use // the constant global instead. This is commonly produced by the CFE by @@ -897,7 +897,7 @@ Changed = true; continue; } - + // Check to see if we can perform the core SROA transformation. We cannot // transform the allocation instruction if it is an array allocation // (allocations OF arrays are ok though), and an allocation of a scalar @@ -906,10 +906,10 @@ // Do not promote [0 x %struct]. if (AllocaSize == 0) continue; - + // Do not promote any struct whose size is too big. if (AllocaSize > SRThreshold) continue; - + // If the alloca looks like a good candidate for scalar replacement, and if // all its users can be transformed, then split up the aggregate into its // separate elements. @@ -932,8 +932,8 @@ ++NumConverted; Changed = true; continue; - } - + } + // Otherwise, couldn't process this alloca. } @@ -942,14 +942,14 @@ /// DoScalarReplacement - This alloca satisfied the isSafeAllocaToScalarRepl /// predicate, do SROA now. -void SROA::DoScalarReplacement(AllocaInst *AI, +void SROA::DoScalarReplacement(AllocaInst *AI, std::vector &WorkList) { DEBUG(dbgs() << "Found inst to SROA: " << *AI << '\n'); SmallVector ElementAllocas; if (const StructType *ST = dyn_cast(AI->getAllocatedType())) { ElementAllocas.reserve(ST->getNumContainedTypes()); for (unsigned i = 0, e = ST->getNumContainedTypes(); i != e; ++i) { - AllocaInst *NA = new AllocaInst(ST->getContainedType(i), 0, + AllocaInst *NA = new AllocaInst(ST->getContainedType(i), 0, AI->getAlignment(), AI->getName() + "." + Twine(i), AI); ElementAllocas.push_back(NA); @@ -997,7 +997,7 @@ I->eraseFromParent(); } } - + /// isSafeForScalarRepl - Check if instruction I is a safe use with regard to /// performing scalar replacement of alloca AI. The results are flagged in /// the Info parameter. Offset indicates the position within AI that is @@ -1374,7 +1374,7 @@ // function is only called for mem intrinsics that access the whole // aggregate, so non-zero GEPs are not an issue here.) OtherPtr = OtherPtr->stripPointerCasts(); - + // Copying the alloca to itself is a no-op: just delete it. if (OtherPtr == AI || OtherPtr == NewElts[0]) { // This code will run twice for a no-op memcpy -- once for each operand. @@ -1385,26 +1385,26 @@ DeadInsts.push_back(MI); return; } - + // If the pointer is not the right type, insert a bitcast to the right // type. const Type *NewTy = PointerType::get(AI->getType()->getElementType(), AddrSpace); - + if (OtherPtr->getType() != NewTy) OtherPtr = new BitCastInst(OtherPtr, NewTy, OtherPtr->getName(), MI); } - + // Process each element of the aggregate. bool SROADest = MI->getRawDest() == Inst; - + Constant *Zero = Constant::getNullValue(Type::getInt32Ty(MI->getContext())); for (unsigned i = 0, e = NewElts.size(); i != e; ++i) { // If this is a memcpy/memmove, emit a GEP of the other element address. Value *OtherElt = 0; unsigned OtherEltAlign = MemAlignment; - + if (OtherPtr) { Value *Idx[2] = { Zero, ConstantInt::get(Type::getInt32Ty(MI->getContext()), i) }; @@ -1420,7 +1420,7 @@ const Type *EltTy = cast(OtherTy)->getElementType(); EltOffset = TD->getTypeAllocSize(EltTy)*i; } - + // The alignment of the other pointer is the guaranteed alignment of the // element, which is affected by both the known alignment of the whole // mem intrinsic and the alignment of the element. If the alignment of @@ -1428,10 +1428,10 @@ // known alignment is just 4 bytes. OtherEltAlign = (unsigned)MinAlign(OtherEltAlign, EltOffset); } - + Value *EltPtr = NewElts[i]; const Type *EltTy = cast(EltPtr->getType())->getElementType(); - + // If we got down to a scalar, insert a load or store as appropriate. if (EltTy->isSingleValueType()) { if (isa(MI)) { @@ -1447,7 +1447,7 @@ continue; } assert(isa(MI)); - + // If the stored element is zero (common case), just store a null // constant. Constant *StoreVal; @@ -1467,7 +1467,7 @@ TotalVal = TotalVal.shl(8); TotalVal |= OneVal; } - + // Convert the integer value to the appropriate type. StoreVal = ConstantInt::get(CI->getContext(), TotalVal); if (ValTy->isPointerTy()) @@ -1475,7 +1475,7 @@ else if (ValTy->isFloatingPointTy()) StoreVal = ConstantExpr::getBitCast(StoreVal, ValTy); assert(StoreVal->getType() == ValTy && "Type mismatch!"); - + // If the requested value was a vector constant, create it. if (EltTy != ValTy) { unsigned NumElts = cast(ValTy)->getNumElements(); @@ -1489,11 +1489,11 @@ // Otherwise, if we're storing a byte variable, use a memset call for // this element. } - + unsigned EltSize = TD->getTypeAllocSize(EltTy); - + IRBuilder<> Builder(MI); - + // Finally, insert the meminst for this element. if (isa(MI)) { Builder.CreateMemSet(EltPtr, MI->getArgOperand(1), EltSize, @@ -1502,7 +1502,7 @@ assert(isa(MI)); Value *Dst = SROADest ? EltPtr : OtherElt; // Dest ptr Value *Src = SROADest ? OtherElt : EltPtr; // Src ptr - + if (isa(MI)) Builder.CreateMemCpy(Dst, Src, EltSize, OtherEltAlign,MI->isVolatile()); else @@ -1522,11 +1522,11 @@ Value *SrcVal = SI->getOperand(0); const Type *AllocaEltTy = AI->getAllocatedType(); uint64_t AllocaSizeBits = TD->getTypeAllocSizeInBits(AllocaEltTy); - + // Handle tail padding by extending the operand if (TD->getTypeSizeInBits(SrcVal->getType()) != AllocaSizeBits) SrcVal = new ZExtInst(SrcVal, - IntegerType::get(SI->getContext(), AllocaSizeBits), + IntegerType::get(SI->getContext(), AllocaSizeBits), "", SI); DEBUG(dbgs() << "PROMOTING STORE TO WHOLE ALLOCA: " << *AI << '\n' << *SI @@ -1536,28 +1536,28 @@ // have different ways to compute the element offset. if (const StructType *EltSTy = dyn_cast(AllocaEltTy)) { const StructLayout *Layout = TD->getStructLayout(EltSTy); - + for (unsigned i = 0, e = NewElts.size(); i != e; ++i) { // Get the number of bits to shift SrcVal to get the value. const Type *FieldTy = EltSTy->getElementType(i); uint64_t Shift = Layout->getElementOffsetInBits(i); - + if (TD->isBigEndian()) Shift = AllocaSizeBits-Shift-TD->getTypeAllocSizeInBits(FieldTy); - + Value *EltVal = SrcVal; if (Shift) { Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); EltVal = BinaryOperator::CreateLShr(EltVal, ShiftVal, "sroa.store.elt", SI); } - + // Truncate down to an integer of the right size. uint64_t FieldSizeBits = TD->getTypeSizeInBits(FieldTy); - + // Ignore zero sized fields like {}, they obviously contain no data. if (FieldSizeBits == 0) continue; - + if (FieldSizeBits != AllocaSizeBits) EltVal = new TruncInst(EltVal, IntegerType::get(SI->getContext(), FieldSizeBits), @@ -1576,7 +1576,7 @@ } new StoreInst(EltVal, DestField, SI); } - + } else { const ArrayType *ATy = cast(AllocaEltTy); const Type *ArrayEltTy = ATy->getElementType(); @@ -1584,28 +1584,28 @@ uint64_t ElementSizeBits = TD->getTypeSizeInBits(ArrayEltTy); uint64_t Shift; - + if (TD->isBigEndian()) Shift = AllocaSizeBits-ElementOffset; - else + else Shift = 0; - + for (unsigned i = 0, e = NewElts.size(); i != e; ++i) { // Ignore zero sized fields like {}, they obviously contain no data. if (ElementSizeBits == 0) continue; - + Value *EltVal = SrcVal; if (Shift) { Value *ShiftVal = ConstantInt::get(EltVal->getType(), Shift); EltVal = BinaryOperator::CreateLShr(EltVal, ShiftVal, "sroa.store.elt", SI); } - + // Truncate down to an integer of the right size. if (ElementSizeBits != AllocaSizeBits) - EltVal = new TruncInst(EltVal, - IntegerType::get(SI->getContext(), - ElementSizeBits),"",SI); + EltVal = new TruncInst(EltVal, + IntegerType::get(SI->getContext(), + ElementSizeBits), "", SI); Value *DestField = NewElts[i]; if (EltVal->getType() == ArrayEltTy) { // Storing to an integer field of this size, just do it. @@ -1620,14 +1620,14 @@ "", SI); } new StoreInst(EltVal, DestField, SI); - + if (TD->isBigEndian()) Shift -= ElementOffset; - else + else Shift += ElementOffset; } } - + DeadInsts.push_back(SI); } @@ -1639,10 +1639,10 @@ // and form the result value. const Type *AllocaEltTy = AI->getAllocatedType(); uint64_t AllocaSizeBits = TD->getTypeAllocSizeInBits(AllocaEltTy); - + DEBUG(dbgs() << "PROMOTING LOAD OF WHOLE ALLOCA: " << *AI << '\n' << *LI << '\n'); - + // There are two forms here: AI could be an array or struct. Both cases // have different ways to compute the element offset. const StructLayout *Layout = 0; @@ -1652,11 +1652,11 @@ } else { const Type *ArrayEltTy = cast(AllocaEltTy)->getElementType(); ArrayEltBitOffset = TD->getTypeAllocSizeInBits(ArrayEltTy); - } - - Value *ResultVal = + } + + Value *ResultVal = Constant::getNullValue(IntegerType::get(LI->getContext(), AllocaSizeBits)); - + for (unsigned i = 0, e = NewElts.size(); i != e; ++i) { // Load the value from the alloca. If the NewElt is an aggregate, cast // the pointer to an integer of the same size before doing the load. @@ -1664,11 +1664,11 @@ const Type *FieldTy = cast(SrcField->getType())->getElementType(); uint64_t FieldSizeBits = TD->getTypeSizeInBits(FieldTy); - + // Ignore zero sized fields like {}, they obviously contain no data. if (FieldSizeBits == 0) continue; - - const IntegerType *FieldIntTy = IntegerType::get(LI->getContext(), + + const IntegerType *FieldIntTy = IntegerType::get(LI->getContext(), FieldSizeBits); if (!FieldTy->isIntegerTy() && !FieldTy->isFloatingPointTy() && !FieldTy->isVectorTy()) @@ -1686,17 +1686,17 @@ // we can shift and insert it. if (SrcField->getType() != ResultVal->getType()) SrcField = new ZExtInst(SrcField, ResultVal->getType(), "", LI); - + // Determine the number of bits to shift SrcField. uint64_t Shift; if (Layout) // Struct case. Shift = Layout->getElementOffsetInBits(i); else // Array case. Shift = i*ArrayEltBitOffset; - + if (TD->isBigEndian()) Shift = AllocaSizeBits-Shift-FieldIntTy->getBitWidth(); - + if (Shift) { Value *ShiftVal = ConstantInt::get(SrcField->getType(), Shift); SrcField = BinaryOperator::CreateShl(SrcField, ShiftVal, "", LI); @@ -1761,13 +1761,13 @@ // Loop over the use list of the alloca. We can only transform it if all of // the users are safe to transform. AllocaInfo Info; - + isSafeForScalarRepl(AI, AI, 0, Info); if (Info.isUnsafe) { DEBUG(dbgs() << "Cannot transform: " << *AI << '\n'); return false; } - + // Okay, we know all the users are promotable. If the aggregate is a memcpy // source and destination, we have to be careful. In particular, the memcpy // could be moving around elements that live in structure padding of the LLVM @@ -1789,7 +1789,7 @@ if (GlobalVariable *GV = dyn_cast(V)) return GV->isConstant(); if (ConstantExpr *CE = dyn_cast(V)) - if (CE->getOpcode() == Instruction::BitCast || + if (CE->getOpcode() == Instruction::BitCast || CE->getOpcode() == Instruction::GetElementPtr) return PointsToConstantGlobal(CE->getOperand(0)); return false; @@ -1812,7 +1812,7 @@ if (LI->isVolatile()) return false; continue; } - + if (BitCastInst *BCI = dyn_cast(U)) { // If uses of the bitcast are ok, we are ok. if (!isOnlyCopiedFromConstantGlobal(BCI, TheCopy, isOffset)) @@ -1827,7 +1827,7 @@ return false; continue; } - + if (CallSite CS = U) { // If this is a readonly/readnone call site, then we know it is just a // load and we can ignore it. @@ -1838,20 +1838,20 @@ // ignore it. if (CS.isCallee(UI)) continue; - + // If this is being passed as a byval argument, the caller is making a // copy, so it is only a read of the alloca. unsigned ArgNo = CS.getArgumentNo(UI); if (CS.paramHasAttr(ArgNo+1, Attribute::ByVal)) continue; } - + // If this is isn't our memcpy/memmove, reject it as something we can't // handle. MemTransferInst *MI = dyn_cast(U); if (MI == 0) return false; - + // If the transfer is using the alloca as a source of the transfer, then // ignore it since it is a load (unless the transfer is volatile). if (UI.getOperandNo() == 1) { @@ -1861,18 +1861,18 @@ // If we already have seen a copy, reject the second one. if (TheCopy) return false; - + // If the pointer has been offset from the start of the alloca, we can't // safely handle this. if (isOffset) return false; // If the memintrinsic isn't using the alloca as the dest, reject it. if (UI.getOperandNo() != 0) return false; - + // If the source of the memcpy/move is not a constant global, reject it. if (!PointsToConstantGlobal(MI->getSource())) return false; - + // Otherwise, the transform is safe. Remember the copy instruction. TheCopy = MI; } From bob.wilson at apple.com Thu Jan 13 15:10:12 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Thu, 13 Jan 2011 21:10:12 -0000 Subject: [llvm-commits] [llvm] r123397 - /llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Message-ID: <20110113211012.593722A6C12C@llvm.org> Author: bwilson Date: Thu Jan 13 15:10:12 2011 New Revision: 123397 URL: http://llvm.org/viewvc/llvm-project?rev=123397&view=rev Log: Tidy comments, indentation, and 80-column violations. Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=123397&r1=123396&r2=123397&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Jan 13 15:10:12 2011 @@ -28,7 +28,6 @@ /// hasFP - Return true if the specified function should have a dedicated frame /// pointer register. This is true if the function has variable sized allocas /// or if frame pointer elimination is disabled. -/// bool ARMFrameLowering::hasFP(const MachineFunction &MF) const { const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); @@ -44,11 +43,11 @@ MFI->isFrameAddressTaken()); } -// hasReservedCallFrame - Under normal circumstances, when a frame pointer is -// not required, we reserve argument space for call sites in the function -// immediately on entry to the current function. This eliminates the need for -// add/sub sp brackets around call sites. Returns true if the call frame is -// included as part of the stack frame. +/// hasReservedCallFrame - Under normal circumstances, when a frame pointer is +/// not required, we reserve argument space for call sites in the function +/// immediately on entry to the current function. This eliminates the need for +/// add/sub sp brackets around call sites. Returns true if the call frame is +/// included as part of the stack frame. bool ARMFrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { const MachineFrameInfo *FFI = MF.getFrameInfo(); unsigned CFSize = FFI->getMaxCallFrameSize(); @@ -62,11 +61,12 @@ return !MF.getFrameInfo()->hasVarSizedObjects(); } -// canSimplifyCallFramePseudos - If there is a reserved call frame, the -// call frame pseudos can be simplified. Unlike most targets, having a FP -// is not sufficient here since we still may reference some objects via SP -// even when FP is available in Thumb2 mode. -bool ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF)const { +/// canSimplifyCallFramePseudos - If there is a reserved call frame, the +/// call frame pseudos can be simplified. Unlike most targets, having a FP +/// is not sufficient here since we still may reference some objects via SP +/// even when FP is available in Thumb2 mode. +bool +ARMFrameLowering::canSimplifyCallFramePseudos(const MachineFunction &MF) const { return hasReservedCallFrame(MF) || MF.getFrameInfo()->hasVarSizedObjects(); } @@ -296,7 +296,7 @@ } void ARMFrameLowering::emitEpilogue(MachineFunction &MF, - MachineBasicBlock &MBB) const { + MachineBasicBlock &MBB) const { MachineBasicBlock::iterator MBBI = prior(MBB.end()); assert(MBBI->getDesc().isReturn() && "Can only insert epilog into returning blocks"); @@ -415,21 +415,21 @@ emitSPUpdate(isARM, MBB, MBBI, dl, TII, VARegSaveSize); } -// Provide a base+offset reference to an FI slot for debug info. It's the -// same as what we use for resolving the code-gen references for now. -// FIXME: This can go wrong when references are SP-relative and simple call -// frames aren't used. +/// getFrameIndexReference - Provide a base+offset reference to an FI slot for +/// debug info. It's the same as what we use for resolving the code-gen +/// references for now. FIXME: This can go wrong when references are +/// SP-relative and simple call frames aren't used. int ARMFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI, - unsigned &FrameReg) const { + unsigned &FrameReg) const { return ResolveFrameIndexReference(MF, FI, FrameReg, 0); } int ARMFrameLowering::ResolveFrameIndexReference(const MachineFunction &MF, - int FI, - unsigned &FrameReg, - int SPAdj) const { + int FI, + unsigned &FrameReg, + int SPAdj) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const ARMBaseRegisterInfo *RegInfo = static_cast(MF.getTarget().getRegisterInfo()); @@ -501,16 +501,18 @@ return Offset; } -int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF, int FI) const { +int ARMFrameLowering::getFrameIndexOffset(const MachineFunction &MF, + int FI) const { unsigned FrameReg; return getFrameIndexReference(MF, FI, FrameReg); } void ARMFrameLowering::emitPushInst(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - unsigned StmOpc, unsigned StrOpc, bool NoGap, - bool(*Func)(unsigned, bool)) const { + MachineBasicBlock::iterator MI, + const std::vector &CSI, + unsigned StmOpc, unsigned StrOpc, + bool NoGap, + bool(*Func)(unsigned, bool)) const { MachineFunction &MF = *MBB.getParent(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); @@ -575,11 +577,11 @@ } void ARMFrameLowering::emitPopInst(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - unsigned LdmOpc, unsigned LdrOpc, - bool isVarArg, bool NoGap, - bool(*Func)(unsigned, bool)) const { + MachineBasicBlock::iterator MI, + const std::vector &CSI, + unsigned LdmOpc, unsigned LdrOpc, + bool isVarArg, bool NoGap, + bool(*Func)(unsigned, bool)) const { MachineFunction &MF = *MBB.getParent(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); ARMFunctionInfo *AFI = MF.getInfo(); @@ -645,9 +647,9 @@ } bool ARMFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { + MachineBasicBlock::iterator MI, + const std::vector &CSI, + const TargetRegisterInfo *TRI) const { if (CSI.empty()) return false; @@ -666,9 +668,9 @@ } bool ARMFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI, - const TargetRegisterInfo *TRI) const { + MachineBasicBlock::iterator MI, + const std::vector &CSI, + const TargetRegisterInfo *TRI) const { if (CSI.empty()) return false; @@ -778,7 +780,7 @@ void ARMFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, - RegScavenger *RS) const { + RegScavenger *RS) const { // This tells PEI to spill the FP as if it is any other callee-save register // to take advantage the eliminateFrameIndex machinery. This also ensures it // is spilled in the order specified by getCalleeSavedRegs() to make it easier From clattner at apple.com Thu Jan 13 15:25:17 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 13 Jan 2011 13:25:17 -0800 Subject: [llvm-commits] [PATCH] simplify construction and destruction of Uses In-Reply-To: References: Message-ID: <7ACFFD0D-6837-48E8-8D7B-BC3C9DEF5EDA@apple.com> On Jan 13, 2011, at 8:13 AM, Jay Foad wrote: > This patch makes sure that we consistently use placement new to > construct Uses, and that we destroy them before the memory is > deallocated. There should be no change in behaviour (because Use's > constructor did nothing, and its destructor was equivalent to > Use::set(0)) but I think it is more correct. > > The patch also simplifies User::dropHungOffUses() and its callers. This patch looks good to me. Gabor, can you look at this too? -Chris From clattner at apple.com Thu Jan 13 15:26:29 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 13 Jan 2011 13:26:29 -0800 Subject: [llvm-commits] [llvm] r123372 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll In-Reply-To: <20110113085629.B95662A6C12D@llvm.org> References: <20110113085629.B95662A6C12D@llvm.org> Message-ID: <0E8DEDA5-D30C-4832-98A9-EE9E3420B4CD@apple.com> On Jan 13, 2011, at 12:56 AM, Duncan Sands wrote: > Author: baldrick > Date: Thu Jan 13 02:56:29 2011 > New Revision: 123372 > > URL: http://llvm.org/viewvc/llvm-project?rev=123372&view=rev > Log: > The most common simplification missed by instsimplify in unoptimized bitcode > is "X != 0 -> X" when X is a boolean. This occurs a lot because of the way > llvm-gcc converts gcc's conditional expressions. Add this, and a few other > similar transforms for completeness. Hi Duncan, I don't really understand the motivation here: unoptimized code has lots of missed stuff, and instsimplify doesn't run for it, no? In any case, this looks very familiar to code already in instcombine. Can the instcombine code be zapped now? -Chris > > Modified: > llvm/trunk/lib/Analysis/InstructionSimplify.cpp > llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll > > Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=123372&r1=123371&r2=123372&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) > +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Jan 13 02:56:29 2011 > @@ -938,8 +938,8 @@ > Pred = CmpInst::getSwappedPredicate(Pred); > } > > - // ITy - This is the return type of the compare we're considering. > - const Type *ITy = GetCompareTy(LHS); > + const Type *ITy = GetCompareTy(LHS); // The return type. > + const Type *OpTy = LHS->getType(); // The operand type. > > // icmp X, X -> true/false > // X icmp undef -> true/false. For example, icmp ugt %X, undef -> false > @@ -947,40 +947,91 @@ > if (LHS == RHS || isa(RHS)) > return ConstantInt::get(ITy, CmpInst::isTrueWhenEqual(Pred)); > > - // icmp , - Global/Stack value > - // addresses never equal each other! We already know that Op0 != Op1. > - if ((isa(LHS) || isa(LHS) || > - isa(LHS)) && > - (isa(RHS) || isa(RHS) || > - isa(RHS))) > - return ConstantInt::get(ITy, CmpInst::isFalseWhenEqual(Pred)); > + // Special case logic when the operands have i1 type. > + if (OpTy->isIntegerTy(1) || (OpTy->isVectorTy() && > + cast(OpTy)->getElementType()->isIntegerTy(1))) { > + switch (Pred) { > + default: break; > + case ICmpInst::ICMP_EQ: > + // X == 1 -> X > + if (match(RHS, m_One())) > + return LHS; > + break; > + case ICmpInst::ICMP_NE: > + // X != 0 -> X > + if (match(RHS, m_Zero())) > + return LHS; > + break; > + case ICmpInst::ICMP_UGT: > + // X >u 0 -> X > + if (match(RHS, m_Zero())) > + return LHS; > + break; > + case ICmpInst::ICMP_UGE: > + // X >=u 1 -> X > + if (match(RHS, m_One())) > + return LHS; > + break; > + case ICmpInst::ICMP_SLT: > + // X X > + if (match(RHS, m_Zero())) > + return LHS; > + break; > + case ICmpInst::ICMP_SLE: > + // X <=s -1 -> X > + if (match(RHS, m_One())) > + return LHS; > + break; > + } > + } > > // See if we are doing a comparison with a constant. > if (ConstantInt *CI = dyn_cast(RHS)) { > - // If we have an icmp le or icmp ge instruction, turn it into the > - // appropriate icmp lt or icmp gt instruction. This allows us to rely on > - // them being folded in the code below. > switch (Pred) { > default: break; > - case ICmpInst::ICMP_ULE: > - if (CI->isMaxValue(false)) // A <=u MAX -> TRUE > - return ConstantInt::getTrue(CI->getContext()); > - break; > - case ICmpInst::ICMP_SLE: > - if (CI->isMaxValue(true)) // A <=s MAX -> TRUE > - return ConstantInt::getTrue(CI->getContext()); > + case ICmpInst::ICMP_UGT: > + if (CI->isMaxValue(false)) // A >u MAX -> FALSE > + return ConstantInt::getFalse(CI->getContext()); > break; > case ICmpInst::ICMP_UGE: > if (CI->isMinValue(false)) // A >=u MIN -> TRUE > return ConstantInt::getTrue(CI->getContext()); > break; > + case ICmpInst::ICMP_ULT: > + if (CI->isMinValue(false)) // A FALSE > + return ConstantInt::getFalse(CI->getContext()); > + break; > + case ICmpInst::ICMP_ULE: > + if (CI->isMaxValue(false)) // A <=u MAX -> TRUE > + return ConstantInt::getTrue(CI->getContext()); > + break; > + case ICmpInst::ICMP_SGT: > + if (CI->isMaxValue(true)) // A >s MAX -> FALSE > + return ConstantInt::getFalse(CI->getContext()); > + break; > case ICmpInst::ICMP_SGE: > if (CI->isMinValue(true)) // A >=s MIN -> TRUE > return ConstantInt::getTrue(CI->getContext()); > break; > + case ICmpInst::ICMP_SLT: > + if (CI->isMinValue(true)) // A FALSE > + return ConstantInt::getFalse(CI->getContext()); > + break; > + case ICmpInst::ICMP_SLE: > + if (CI->isMaxValue(true)) // A <=s MAX -> TRUE > + return ConstantInt::getTrue(CI->getContext()); > + break; > } > } > > + // icmp , - Global/Stack value > + // addresses never equal each other! We already know that Op0 != Op1. > + if ((isa(LHS) || isa(LHS) || > + isa(LHS)) && > + (isa(RHS) || isa(RHS) || > + isa(RHS))) > + return ConstantInt::get(ITy, CmpInst::isFalseWhenEqual(Pred)); > + > // If the comparison is with the result of a select instruction, check whether > // comparing with either branch of the select always yields the same value. > if (isa(LHS) || isa(RHS)) > > Modified: llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll?rev=123372&r1=123371&r2=123372&view=diff > ============================================================================== > --- llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll (original) > +++ llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll Thu Jan 13 02:56:29 2011 > @@ -20,3 +20,10 @@ > ret i1 %z > ; CHECK: ret i1 %x > } > + > +define i1 @ne(i1 %x) { > +; CHECK: @ne > + %z = icmp ne i1 %x, 0 > + ret i1 %z > +; CHECK: ret i1 %x > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Thu Jan 13 15:28:52 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 13 Jan 2011 21:28:52 -0000 Subject: [llvm-commits] [llvm] r123399 - in /llvm/trunk: include/llvm/CodeGen/ lib/CodeGen/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ Message-ID: <20110113212852.678472A6C12C@llvm.org> Author: stoklund Date: Thu Jan 13 15:28:52 2011 New Revision: 123399 URL: http://llvm.org/viewvc/llvm-project?rev=123399&view=rev Log: Teach frame lowering to ignore debug values after the terminators. Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.cpp llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Thu Jan 13 15:28:52 2011 @@ -300,6 +300,10 @@ /// it returns end() iterator getFirstTerminator(); + /// getLastNonDebugInstr - returns an iterator to the last non-debug + /// instruction in the basic block, or end() + iterator getLastNonDebugInstr(); + /// SplitCriticalEdge - Split the critical edge from this block to the /// given successor block, and return the newly created block, or null /// if splitting is not possible. Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Thu Jan 13 15:28:52 2011 @@ -162,6 +162,18 @@ return I; } +MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() { + iterator B = begin(), I = end(); + while (I != B) { + --I; + if (I->isDebugValue()) + continue; + return I; + } + // The block is all debug values. + return end(); +} + void MachineBasicBlock::dump() const { print(dbgs()); } Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -297,7 +297,7 @@ void ARMFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); assert(MBBI->getDesc().isReturn() && "Can only insert epilog into returning blocks"); unsigned RetOpcode = MBBI->getOpcode(); @@ -378,7 +378,7 @@ if (RetOpcode == ARM::TCRETURNdi || RetOpcode == ARM::TCRETURNdiND || RetOpcode == ARM::TCRETURNri || RetOpcode == ARM::TCRETURNriND) { // Tail call return: adjust the stack pointer and jump to callee. - MBBI = prior(MBB.end()); + MBBI = MBB.getLastNonDebugInstr(); MachineOperand &JumpTarget = MBBI->getOperand(0); // Jump to label or value in register. Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -189,7 +189,7 @@ void Thumb1FrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); assert((MBBI->getOpcode() == ARM::tBX_RET || MBBI->getOpcode() == ARM::tPOP_RET) && "Can only insert epilog into returning blocks"); Modified: llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaFrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -104,7 +104,7 @@ void AlphaFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo(); assert((MBBI->getOpcode() == Alpha::RETDAG || Modified: llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -90,7 +90,7 @@ static_cast(MF.getTarget().getRegisterInfo()); const BlackfinInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); DebugLoc dl = MBBI->getDebugLoc(); int FrameSize = MFI->getStackSize(); Modified: llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUFrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -187,7 +187,7 @@ // sufficient number instructions in the basic block. Note that // this is just a best guess based on the basic block's size. if (MBB.size() >= (unsigned) SPUFrameLowering::branchHintPenalty()) { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); dl = MBBI->getDebugLoc(); // Insert terminator label @@ -199,7 +199,7 @@ void SPUFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const SPUInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); const MachineFrameInfo *MFI = MF.getFrameInfo(); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeFrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -386,7 +386,7 @@ void MBlazeFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); MachineFrameInfo *MFI = MF.getFrameInfo(); MBlazeFunctionInfo *MBlazeFI = MF.getInfo(); const MBlazeInstrInfo &TII = Modified: llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430FrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -110,7 +110,7 @@ const MSP430InstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); unsigned RetOpcode = MBBI->getOpcode(); DebugLoc DL = MBBI->getDebugLoc(); Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -266,7 +266,7 @@ void MipsFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); MachineFrameInfo *MFI = MF.getFrameInfo(); MipsFunctionInfo *MipsFI = MF.getInfo(); const MipsInstrInfo &TII = Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -497,7 +497,8 @@ void PPCFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); + assert(MBBI != MBB.end() && "Returning block has no terminator"); const PPCInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); @@ -676,29 +677,29 @@ .addReg(TmpReg); } } else if (RetOpcode == PPC::TCRETURNdi) { - MBBI = prior(MBB.end()); + MBBI = MBB.getLastNonDebugInstr(); MachineOperand &JumpTarget = MBBI->getOperand(0); BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); } else if (RetOpcode == PPC::TCRETURNri) { - MBBI = prior(MBB.end()); + MBBI = MBB.getLastNonDebugInstr(); assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); } else if (RetOpcode == PPC::TCRETURNai) { - MBBI = prior(MBB.end()); + MBBI = MBB.getLastNonDebugInstr(); MachineOperand &JumpTarget = MBBI->getOperand(0); BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); } else if (RetOpcode == PPC::TCRETURNdi8) { - MBBI = prior(MBB.end()); + MBBI = MBB.getLastNonDebugInstr(); MachineOperand &JumpTarget = MBBI->getOperand(0); BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); } else if (RetOpcode == PPC::TCRETURNri8) { - MBBI = prior(MBB.end()); + MBBI = MBB.getLastNonDebugInstr(); assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); } else if (RetOpcode == PPC::TCRETURNai8) { - MBBI = prior(MBB.end()); + MBBI = MBB.getLastNonDebugInstr(); MachineOperand &JumpTarget = MBBI->getOperand(0); BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); } Modified: llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcFrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -69,7 +69,7 @@ void SparcFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const SparcInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); DebugLoc dl = MBBI->getDebugLoc(); Modified: llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZFrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -141,7 +141,7 @@ void SystemZFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const SystemZInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); SystemZMachineFunctionInfo *SystemZMFI = Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=123399&r1=123398&r2=123399&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Thu Jan 13 15:28:52 2011 @@ -646,7 +646,8 @@ X86MachineFunctionInfo *X86FI = MF.getInfo(); const X86RegisterInfo *RegInfo = TM.getRegisterInfo(); const X86InstrInfo &TII = *TM.getInstrInfo(); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); + assert(MBBI != MBB.end() && "Returning block has no instructions"); unsigned RetOpcode = MBBI->getOpcode(); DebugLoc DL = MBBI->getDebugLoc(); bool Is64Bit = STI.is64Bit(); @@ -709,7 +710,7 @@ MachineBasicBlock::iterator PI = prior(MBBI); unsigned Opc = PI->getOpcode(); - if (Opc != X86::POP32r && Opc != X86::POP64r && + if (Opc != X86::POP32r && Opc != X86::POP64r && Opc != X86::DBG_VALUE && !PI->getDesc().isTerminator()) break; @@ -756,7 +757,7 @@ // We're returning from function via eh_return. if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) { - MBBI = prior(MBB.end()); + MBBI = MBB.getLastNonDebugInstr(); MachineOperand &DestAddr = MBBI->getOperand(0); assert(DestAddr.isReg() && "Offset should be in register!"); BuildMI(MBB, MBBI, DL, @@ -768,7 +769,7 @@ RetOpcode == X86::TCRETURNmi64) { bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64; // Tail call return: adjust the stack pointer and jump to callee. - MBBI = prior(MBB.end()); + MBBI = MBB.getFirstTerminator(); MachineOperand &JumpTarget = MBBI->getOperand(0); MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1); assert(StackAdjust.isImm() && "Expecting immediate value."); @@ -826,7 +827,7 @@ (X86FI->getTCReturnAddrDelta() < 0)) { // Add the return addr area delta back since we are not tail calling. int delta = -1*X86FI->getTCReturnAddrDelta(); - MBBI = prior(MBB.end()); + MBBI = MBB.getLastNonDebugInstr(); // Check for possible merge with preceeding ADD instruction. delta += mergeSPUpdates(MBB, MBBI, StackPtr, true); From stoklund at 2pi.dk Thu Jan 13 15:28:55 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 13 Jan 2011 21:28:55 -0000 Subject: [llvm-commits] [llvm] r123400 - /llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Message-ID: <20110113212855.8B4E42A6C12D@llvm.org> Author: stoklund Date: Thu Jan 13 15:28:55 2011 New Revision: 123400 URL: http://llvm.org/viewvc/llvm-project?rev=123400&view=rev Log: Temporary workaround for an i386 crash in LiveDebugVariables. Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=123400&r1=123399&r2=123400&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Thu Jan 13 15:28:55 2011 @@ -591,7 +591,8 @@ // Don't insert anything after the first terminator. MachineBasicBlock::iterator Term = MBB->getFirstTerminator(); - if (Term != MBB->end() && Idx >= LIS.getInstructionIndex(Term)) { + if (Term != MBB->end() && !LIS.isNotInMIMap(Term) && + Idx >= LIS.getInstructionIndex(Term)) { DL = Term->getDebugLoc(); return Term; } From sabre at nondot.org Thu Jan 13 15:36:25 2011 From: sabre at nondot.org (Chris Lattner) Date: Thu, 13 Jan 2011 21:36:25 -0000 Subject: [llvm-commits] [www] r123402 - /www/trunk/index.html Message-ID: <20110113213625.A1C182A6C12C@llvm.org> Author: lattner Date: Thu Jan 13 15:36:25 2011 New Revision: 123402 URL: http://llvm.org/viewvc/llvm-project?rev=123402&view=rev Log: move dragonegg before llvm-gcc. Modified: www/trunk/index.html Modified: www/trunk/index.html URL: http://llvm.org/viewvc/llvm-project/www/trunk/index.html?rev=123402&r1=123401&r2=123402&view=diff ============================================================================== --- www/trunk/index.html (original) +++ www/trunk/index.html Thu Jan 13 15:36:25 2011 @@ -49,10 +49,11 @@ sort of tool that can be built using the Clang frontend as a library to parse C/C++ code.

    -
  • llvm-gcc 4.2 and - dragonegg integrate the LLVM - optimizers and code generator with the GCC 4.2 (which is GPL2) and GCC 4.5 - (which is GPL3) parsers, respectively. This allows LLVM to compile Ada, +

  • dragonegg and + llvm-gcc 4.2 + integrate the LLVM + optimizers and code generator with the GCC 4.5 (which is GPL3) and GCC 4.2 + (which is GPL2) parsers, respectively. This allows LLVM to compile Ada, Fortran, and other languages supported by the GCC compiler frontends, and provides high-fidelity drop-in compatibility with their respective versions of GCC.

  • From clattner at apple.com Thu Jan 13 15:47:01 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 13 Jan 2011 13:47:01 -0800 Subject: [llvm-commits] [PATCH] Bug 889: clean up dodgy casts between Value** and Constant** In-Reply-To: References: Message-ID: <07C1A51B-72AF-4E2C-A226-305B097C9798@apple.com> On Jan 12, 2011, at 7:54 AM, Jay Foad wrote: > http://llvm.org/bugs/show_bug.cgi?id=889 > > This bug is about removing virtual methods from Value and its subclasses. looks great to me! -Chris > > While playing with fixes for this bug, I found a few C-style casts > from Value** to Constant** or vice versa. This works at the moment, > because a static_cast from Constant* to Value* doesn't have to adjust > the "this" pointer, but it's not safe in general. In particular, it > won't work if Constant has virtual methods but Value doesn't. > > The reason for the casts' existence is that there are various methods > to do with creating getElementPtrs which take either an array of > Values or an array of Constants, but there isn't much consistency -- > some methods can only take an array of Values, and some can only take > an array of Constants. > > This patch ensures that there are two overloads for each such method: > one taking an array of Values, and one taking an array of Constants. > By calling the appropriate version in each case, we can avoid the > casts. > > Tested with "make check". OK to commit? > > Thanks, > Jay. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Thu Jan 13 15:45:26 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Jan 2011 21:45:26 -0000 Subject: [llvm-commits] [llvm] r123403 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp Message-ID: <20110113214526.D7CBD2A6C12C@llvm.org> Author: evancheng Date: Thu Jan 13 15:45:26 2011 New Revision: 123403 URL: http://llvm.org/viewvc/llvm-project?rev=123403&view=rev Log: Relax an assertion. On archs like ARM, an immediate field may be scattered. So it's possible for some bits of every 8 bits to be encoded already, and the rest still needs to be fixed up. Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=123403&r1=123402&r2=123403&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Thu Jan 13 15:45:26 2011 @@ -824,8 +824,12 @@ if (MapEntry == 0) { OS << format("0x%02x", uint8_t(Code[i])); } else { - assert(Code[i] == 0 && "Encoder wrote into fixed up bit!"); - OS << char('A' + MapEntry - 1); + if (Code[i]) { + // some of the 8 bits require fix up. + OS << format("0x%02x", uint8_t(Code[i])) << '\'' + << char('A' + MapEntry - 1) << '\''; + } else + OS << char('A' + MapEntry - 1); } } else { // Otherwise, write out in binary. From resistor at mac.com Thu Jan 13 15:46:02 2011 From: resistor at mac.com (Owen Anderson) Date: Thu, 13 Jan 2011 21:46:02 -0000 Subject: [llvm-commits] [llvm] r123404 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h utils/TableGen/EDEmitter.cpp Message-ID: <20110113214602.B50DF2A6C12C@llvm.org> Author: resistor Date: Thu Jan 13 15:46:02 2011 New Revision: 123404 URL: http://llvm.org/viewvc/llvm-project?rev=123404&view=rev Log: Add support to the ARM MC infrastructure to support mcr and friends. This requires supporting the symbolic immediate names used for these instructions, fixing their pretty-printers, and adding proper encoding information for them. With this, we can properly pretty-print and encode assembly like: mrc p15, #0, r3, c13, c0, #3 Fixes . Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=123404&r1=123403&r2=123404&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Thu Jan 13 15:46:02 2011 @@ -561,6 +561,14 @@ let PrintMethod = "printNoHashImmediate"; } +def p_imm : Operand { + let PrintMethod = "printPImmediate"; +} + +def c_imm : Operand { + let PrintMethod = "printCImmediate"; +} + //===----------------------------------------------------------------------===// include "ARMInstrFormats.td" @@ -3598,68 +3606,172 @@ defm STC : LdStCop<{?,?,?,?}, 0, "stc">; defm STC2 : LdStCop<0b1111, 0, "stc2">; -def MCR : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, - GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), - NoItinerary, "mcr", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", +def MCR : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1, + GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), + NoItinerary, "mcr", "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", [/* For disassembly only; pattern left blank */]> { let Inst{20} = 0; let Inst{4} = 1; + + bits<4> Rt; + bits<4> cop; + bits<3> opc1; + bits<3> opc2; + bits<4> CRm; + bits<4> CRn; + + let Inst{15-12} = Rt; + let Inst{11-8} = cop; + let Inst{23-21} = opc1; + let Inst{7-5} = opc2; + let Inst{3-0} = CRm; + let Inst{19-16} = CRn; } -def MCR2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, - GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), - NoItinerary, "mcr2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", +def MCR2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1, + GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), + NoItinerary, "mcr2\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", [/* For disassembly only; pattern left blank */]> { let Inst{31-28} = 0b1111; let Inst{20} = 0; let Inst{4} = 1; + + bits<4> Rt; + bits<4> cop; + bits<3> opc1; + bits<3> opc2; + bits<4> CRm; + bits<4> CRn; + + let Inst{15-12} = Rt; + let Inst{11-8} = cop; + let Inst{23-21} = opc1; + let Inst{7-5} = opc2; + let Inst{3-0} = CRm; + let Inst{19-16} = CRn; } -def MRC : ABI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, - GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), - NoItinerary, "mrc", "\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", +def MRC : ABI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1, + GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), + NoItinerary, "mrc", "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", [/* For disassembly only; pattern left blank */]> { let Inst{20} = 1; let Inst{4} = 1; + + bits<4> Rt; + bits<4> cop; + bits<3> opc1; + bits<3> opc2; + bits<4> CRm; + bits<4> CRn; + + let Inst{15-12} = Rt; + let Inst{11-8} = cop; + let Inst{23-21} = opc1; + let Inst{7-5} = opc2; + let Inst{3-0} = CRm; + let Inst{19-16} = CRn; } -def MRC2 : ABXI<0b1110, (outs), (ins nohash_imm:$cop, i32imm:$opc1, - GPR:$Rt, nohash_imm:$CRn, nohash_imm:$CRm, i32imm:$opc2), - NoItinerary, "mrc2\tp$cop, $opc1, $Rt, cr$CRn, cr$CRm, $opc2", +def MRC2 : ABXI<0b1110, (outs), (ins p_imm:$cop, i32imm:$opc1, + GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), + NoItinerary, "mrc2\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2", [/* For disassembly only; pattern left blank */]> { let Inst{31-28} = 0b1111; let Inst{20} = 1; let Inst{4} = 1; + + bits<4> Rt; + bits<4> cop; + bits<3> opc1; + bits<3> opc2; + bits<4> CRm; + bits<4> CRn; + + let Inst{15-12} = Rt; + let Inst{11-8} = cop; + let Inst{23-21} = opc1; + let Inst{7-5} = opc2; + let Inst{3-0} = CRm; + let Inst{19-16} = CRn; } -def MCRR : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, - GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), - NoItinerary, "mcrr", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm", +def MCRR : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc, + GPR:$Rt, GPR:$Rt2, c_imm:$CRm), + NoItinerary, "mcrr", "\t$cop, $opc, $Rt, $Rt2, $CRm", [/* For disassembly only; pattern left blank */]> { let Inst{23-20} = 0b0100; + + bits<4> Rt; + bits<4> Rt2; + bits<4> cop; + bits<3> opc1; + bits<4> CRm; + + let Inst{15-12} = Rt; + let Inst{19-16} = Rt2; + let Inst{11-8} = cop; + let Inst{7-5} = opc1; + let Inst{3-0} = CRm; } -def MCRR2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, - GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), - NoItinerary, "mcrr2\tp$cop, $opc, $Rt, $Rt2, cr$CRm", +def MCRR2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc, + GPR:$Rt, GPR:$Rt2, c_imm:$CRm), + NoItinerary, "mcrr2\t$cop, $opc, $Rt, $Rt2, $CRm", [/* For disassembly only; pattern left blank */]> { let Inst{31-28} = 0b1111; let Inst{23-20} = 0b0100; + + bits<4> Rt; + bits<4> Rt2; + bits<4> cop; + bits<3> opc1; + bits<4> CRm; + + let Inst{15-12} = Rt; + let Inst{19-16} = Rt2; + let Inst{11-8} = cop; + let Inst{7-5} = opc1; + let Inst{3-0} = CRm; } -def MRRC : ABI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, - GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), - NoItinerary, "mrrc", "\tp$cop, $opc, $Rt, $Rt2, cr$CRm", +def MRRC : ABI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc, + GPR:$Rt, GPR:$Rt2, c_imm:$CRm), + NoItinerary, "mrrc", "\t$cop, $opc, $Rt, $Rt2, $CRm", [/* For disassembly only; pattern left blank */]> { let Inst{23-20} = 0b0101; + + bits<4> Rt; + bits<4> Rt2; + bits<4> cop; + bits<3> opc1; + bits<4> CRm; + + let Inst{15-12} = Rt; + let Inst{19-16} = Rt2; + let Inst{11-8} = cop; + let Inst{7-5} = opc1; + let Inst{3-0} = CRm; } -def MRRC2 : ABXI<0b1100, (outs), (ins nohash_imm:$cop, i32imm:$opc, - GPR:$Rt, GPR:$Rt2, nohash_imm:$CRm), - NoItinerary, "mrrc2\tp$cop, $opc, $Rt, $Rt2, cr$CRm", +def MRRC2 : ABXI<0b1100, (outs), (ins p_imm:$cop, i32imm:$opc, + GPR:$Rt, GPR:$Rt2, c_imm:$CRm), + NoItinerary, "mrrc2\t$cop, $opc, $Rt, $Rt2, $CRm", [/* For disassembly only; pattern left blank */]> { let Inst{31-28} = 0b1111; let Inst{23-20} = 0b0101; + + bits<4> Rt; + bits<4> Rt2; + bits<4> cop; + bits<3> opc1; + bits<4> CRm; + + let Inst{15-12} = Rt; + let Inst{19-16} = Rt2; + let Inst{11-8} = cop; + let Inst{7-5} = opc1; + let Inst{3-0} = CRm; } //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123404&r1=123403&r2=123404&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jan 13 15:46:02 2011 @@ -52,10 +52,11 @@ bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } int TryParseRegister(); + bool TryParseMCRName(SmallVectorImpl&); bool TryParseRegisterWithWriteBack(SmallVectorImpl &); bool ParseRegisterList(SmallVectorImpl &); bool ParseMemory(SmallVectorImpl &); - bool ParseOperand(SmallVectorImpl &); + bool ParseOperand(SmallVectorImpl &, bool isMCR); bool ParsePrefix(ARMMCExpr::VariantKind &RefKind); const MCExpr *ApplyPrefixToExpr(const MCExpr *E, MCSymbolRefExpr::VariantKind Variant); @@ -527,6 +528,67 @@ return false; } +static int MatchMCRName(StringRef Name) { + // Use the same layout as the tablegen'erated register name matcher. Ugly, + // but efficient. + switch (Name.size()) { + default: break; + case 2: + if (Name[0] != 'p' && Name[0] != 'c') + return -1; + switch (Name[1]) { + default: return -1; + case '0': return 0; + case '1': return 1; + case '2': return 2; + case '3': return 3; + case '4': return 4; + case '5': return 5; + case '6': return 6; + case '7': return 7; + case '8': return 8; + case '9': return 9; + } + break; + case 3: + if ((Name[0] != 'p' && Name[0] != 'c') || Name[1] != '1') + return -1; + switch (Name[2]) { + default: return -1; + case '0': return 10; + case '1': return 11; + case '2': return 12; + case '3': return 13; + case '4': return 14; + case '5': return 15; + } + break; + } + + llvm_unreachable("Unhandled coprocessor operand string!"); + return -1; +} + +/// TryParseMCRName - Try to parse an MCR/MRC symbolic operand +/// name. The token must be an Identifier when called, and if it is a MCR +/// operand name, the token is eaten and the operand is added to the +/// operand list. +bool ARMAsmParser:: +TryParseMCRName(SmallVectorImpl &Operands) { + SMLoc S = Parser.getTok().getLoc(); + const AsmToken &Tok = Parser.getTok(); + assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier"); + + int Num = MatchMCRName(Tok.getString()); + if (Num == -1) + return true; + + Parser.Lex(); // Eat identifier token. + Operands.push_back(ARMOperand::CreateImm( + MCConstantExpr::Create(Num, getContext()), S, Parser.getTok().getLoc())); + return false; +} + /// Parse a register list, return it if successful else return null. The first /// token must be a '{' when called. bool ARMAsmParser:: @@ -834,7 +896,8 @@ /// Parse a arm instruction operand. For now this parses the operand regardless /// of the mnemonic. -bool ARMAsmParser::ParseOperand(SmallVectorImpl &Operands){ +bool ARMAsmParser::ParseOperand(SmallVectorImpl &Operands, + bool isMCR){ SMLoc S, E; switch (getLexer().getKind()) { default: @@ -843,7 +906,11 @@ case AsmToken::Identifier: if (!TryParseRegisterWithWriteBack(Operands)) return false; - // Fall though for the Identifier case that is not a register + if (isMCR && !TryParseMCRName(Operands)) + return false; + + // Fall though for the Identifier case that is not a register or a + // special name. case AsmToken::Integer: // things like 1f and 2b as a branch targets case AsmToken::Dot: { // . as a branch target // This was not a register so parse other operands that start with an @@ -1120,10 +1187,15 @@ Operands.push_back(ARMOperand::CreateToken(Head, NameLoc)); } + bool isMCR = (Head == "mcr" || Head == "mcr2" || + Head == "mcrr" || Head == "mcrr2" || + Head == "mrc" || Head == "mrc2" || + Head == "mrrc" || Head == "mrrc2"); + // Read the remaining operands. if (getLexer().isNot(AsmToken::EndOfStatement)) { // Read the first operand. - if (ParseOperand(Operands)) { + if (ParseOperand(Operands, isMCR)) { Parser.EatToEndOfStatement(); return true; } @@ -1132,7 +1204,7 @@ Parser.Lex(); // Eat the comma. // Parse and remember the operand. - if (ParseOperand(Operands)) { + if (ParseOperand(Operands, isMCR)) { Parser.EatToEndOfStatement(); return true; } Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=123404&r1=123403&r2=123404&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Thu Jan 13 15:46:02 2011 @@ -453,6 +453,16 @@ O << MI->getOperand(OpNum).getImm(); } +void ARMInstPrinter::printPImmediate(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { + O << "p" << MI->getOperand(OpNum).getImm(); +} + +void ARMInstPrinter::printCImmediate(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { + O << "c" << MI->getOperand(OpNum).getImm(); +} + void ARMInstPrinter::printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O) { llvm_unreachable("Unhandled PC-relative pseudo-instruction!"); Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=123404&r1=123403&r2=123404&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Thu Jan 13 15:46:02 2011 @@ -95,6 +95,8 @@ raw_ostream &O); void printRegisterList(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printNoHashImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printPImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printCImmediate(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printVFPf32ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printVFPf64ImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=123404&r1=123403&r2=123404&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Thu Jan 13 15:46:02 2011 @@ -568,6 +568,8 @@ IMM("bf_inv_mask_imm"); IMM("jtblock_operand"); IMM("nohash_imm"); + IMM("p_imm"); + IMM("c_imm"); IMM("cpinst_operand"); IMM("setend_op"); IMM("cps_opt"); From clattner at apple.com Thu Jan 13 15:53:01 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 13 Jan 2011 13:53:01 -0800 Subject: [llvm-commits] [llvm] r123297 - /llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp In-Reply-To: References: <20110112014242.E4A352A6C12C@llvm.org> <8FD2091A-A314-4786-91EC-C41603BB135B@apple.com> Message-ID: <99E34CD6-6414-4CD3-94C8-7794EB8F56AD@apple.com> >> >> Please move the default case to the first part of the switch statement: >> switch (whatever) { >> default: assert(0 && ... >> case 0: >> that way, in non-assert builds, the compiler still thinks everything is >> great. > > Got it, done in r123317. Is it worth mentioning this in the coding style docs? I went to go do this, but I can't think of a single case that llvm_unreachable is the right answer for. I filed PR 8973 to track its removal. Thanks! -Chris From sabre at nondot.org Thu Jan 13 16:08:15 2011 From: sabre at nondot.org (Chris Lattner) Date: Thu, 13 Jan 2011 22:08:15 -0000 Subject: [llvm-commits] [llvm] r123405 - /llvm/trunk/lib/Target/README.txt Message-ID: <20110113220815.5EA392A6C12C@llvm.org> Author: lattner Date: Thu Jan 13 16:08:15 2011 New Revision: 123405 URL: http://llvm.org/viewvc/llvm-project?rev=123405&view=rev Log: memcpy + metadata = bliss :) Modified: llvm/trunk/lib/Target/README.txt Modified: llvm/trunk/lib/Target/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=123405&r1=123404&r2=123405&view=diff ============================================================================== --- llvm/trunk/lib/Target/README.txt (original) +++ llvm/trunk/lib/Target/README.txt Thu Jan 13 16:08:15 2011 @@ -2259,3 +2259,51 @@ transform the fmul to 0.0, and then the fadd to 2.0. //===---------------------------------------------------------------------===// + +We should enhance memcpy/memcpy/memset to allow a metadata node on them +indicating that some bytes of the transfer are undefined. This is useful for +frontends like clang when lowering struct lowering, when some elements of the +struct are undefined. Consider something like this: + +struct x { + char a; + int b[4]; +}; +void foo(struct x*P); +struct x testfunc() { + struct x V1, V2; + foo(&V1); + V2 = V1; + + return V2; +} + +We currently compile this to: +$ clang t.c -S -o - -O0 -emit-llvm | opt -scalarrepl -S + + +%struct.x = type { i8, [4 x i32] } + +define void @testfunc(%struct.x* sret %agg.result) nounwind ssp { +entry: + %V1 = alloca %struct.x, align 4 + call void @foo(%struct.x* %V1) + %tmp1 = bitcast %struct.x* %V1 to i8* + %0 = bitcast %struct.x* %V1 to i160* + %srcval1 = load i160* %0, align 4 + %tmp2 = bitcast %struct.x* %agg.result to i8* + %1 = bitcast %struct.x* %agg.result to i160* + store i160 %srcval1, i160* %1, align 4 + ret void +} + +This happens because SRoA sees that the temp alloca has is being memcpy'd into +and out of and it has holes and it has to be conservative. If we knew about the +holes, then this could be much much better. + +Having information about these holes would also improve memcpy (etc) lowering at +llc time when it gets inlined, because we can use smaller transfers. This also +avoids partial register stalls in some important cases. + +//===---------------------------------------------------------------------===// + From clattner at apple.com Thu Jan 13 16:11:56 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 13 Jan 2011 14:11:56 -0800 Subject: [llvm-commits] [llvm] r123380 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/copy-aggregate.ll In-Reply-To: <20110113174508.6BBA02A6C12C@llvm.org> References: <20110113174508.6BBA02A6C12C@llvm.org> Message-ID: <6C4B7DDE-6976-4403-9C2C-EDCAD539CE52@apple.com> On Jan 13, 2011, at 9:45 AM, Bob Wilson wrote: > Author: bwilson > Date: Thu Jan 13 11:45:08 2011 > New Revision: 123380 > > URL: http://llvm.org/viewvc/llvm-project?rev=123380&view=rev > Log: > Make SROA more aggressive with allocas containing padding. Nice! If you are generally interested in improving the "hole case", we should really handle this by sprinkling some metadata on the problem. I added some notes to Target/README.txt in r123405. -Chris From sabre at nondot.org Thu Jan 13 16:11:56 2011 From: sabre at nondot.org (Chris Lattner) Date: Thu, 13 Jan 2011 22:11:56 -0000 Subject: [llvm-commits] [llvm] r123406 - /llvm/trunk/lib/Target/README.txt Message-ID: <20110113221156.E944D2A6C12C@llvm.org> Author: lattner Date: Thu Jan 13 16:11:56 2011 New Revision: 123406 URL: http://llvm.org/viewvc/llvm-project?rev=123406&view=rev Log: typo Modified: llvm/trunk/lib/Target/README.txt Modified: llvm/trunk/lib/Target/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=123406&r1=123405&r2=123406&view=diff ============================================================================== --- llvm/trunk/lib/Target/README.txt (original) +++ llvm/trunk/lib/Target/README.txt Thu Jan 13 16:11:56 2011 @@ -2262,7 +2262,7 @@ We should enhance memcpy/memcpy/memset to allow a metadata node on them indicating that some bytes of the transfer are undefined. This is useful for -frontends like clang when lowering struct lowering, when some elements of the +frontends like clang when lowering struct copies, when some elements of the struct are undefined. Consider something like this: struct x { From resistor at mac.com Thu Jan 13 16:38:16 2011 From: resistor at mac.com (Owen Anderson) Date: Thu, 13 Jan 2011 22:38:16 -0000 Subject: [llvm-commits] [llvm] r123407 - /llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Message-ID: <20110113223816.BE21A2A6C12C@llvm.org> Author: resistor Date: Thu Jan 13 16:38:16 2011 New Revision: 123407 URL: http://llvm.org/viewvc/llvm-project?rev=123407&view=rev Log: As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr and friends. Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=123407&r1=123406&r2=123407&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Thu Jan 13 16:38:16 2011 @@ -45,7 +45,7 @@ # CHECK: lsls r0, r2, #31 0x82 0x0f 0xb0 0xe1 -# CHECK: mcr2 p0, #0, r2, cr1, cr0, #7 +# CHECK: mcr2 p0, #0, r2, c1, c0, #7 0xf0 0x20 0x01 0xfe # CHECK: movt r8, #65535 From stoklund at 2pi.dk Thu Jan 13 16:47:44 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 13 Jan 2011 22:47:44 -0000 Subject: [llvm-commits] [llvm] r123408 - in /llvm/trunk/lib/Target: ARM/ARMLoadStoreOptimizer.cpp X86/X86FrameLowering.cpp XCore/XCoreFrameLowering.cpp Message-ID: <20110113224744.206C02A6C12C@llvm.org> Author: stoklund Date: Thu Jan 13 16:47:43 2011 New Revision: 123408 URL: http://llvm.org/viewvc/llvm-project?rev=123408&view=rev Log: Fix a few more places that should use MBB::getLastNonDebugInstr(). Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/trunk/lib/Target/X86/X86FrameLowering.cpp llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=123408&r1=123407&r2=123408&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Thu Jan 13 16:47:43 2011 @@ -1351,7 +1351,7 @@ bool ARMLoadStoreOpt::MergeReturnIntoLDM(MachineBasicBlock &MBB) { if (MBB.empty()) return false; - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); if (MBBI != MBB.begin() && (MBBI->getOpcode() == ARM::BX_RET || MBBI->getOpcode() == ARM::tBX_RET || Modified: llvm/trunk/lib/Target/X86/X86FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FrameLowering.cpp?rev=123408&r1=123407&r2=123408&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FrameLowering.cpp Thu Jan 13 16:47:43 2011 @@ -769,7 +769,7 @@ RetOpcode == X86::TCRETURNmi64) { bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64; // Tail call return: adjust the stack pointer and jump to callee. - MBBI = MBB.getFirstTerminator(); + MBBI = MBB.getLastNonDebugInstr(); MachineOperand &JumpTarget = MBBI->getOperand(0); MachineOperand &StackAdjust = MBBI->getOperand(isMem ? 5 : 1); assert(StackAdjust.isImm() && "Expecting immediate value."); Modified: llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp?rev=123408&r1=123407&r2=123408&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreFrameLowering.cpp Thu Jan 13 16:47:43 2011 @@ -208,7 +208,7 @@ void XCoreFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineBasicBlock::iterator MBBI = prior(MBB.end()); + MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); const XCoreInstrInfo &TII = *static_cast(MF.getTarget().getInstrInfo()); DebugLoc dl = MBBI->getDebugLoc(); From resistor at mac.com Thu Jan 13 16:50:37 2011 From: resistor at mac.com (Owen Anderson) Date: Thu, 13 Jan 2011 22:50:37 -0000 Subject: [llvm-commits] [llvm] r123409 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110113225037.219452A6C12C@llvm.org> Author: resistor Date: Thu Jan 13 16:50:36 2011 New Revision: 123409 URL: http://llvm.org/viewvc/llvm-project?rev=123409&view=rev Log: Recognize alternative register names like ip -> r12. Fixes . Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=123409&r1=123408&r2=123409&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jan 13 16:50:36 2011 @@ -24,6 +24,7 @@ #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/ADT/Twine.h" using namespace llvm; @@ -495,9 +496,19 @@ // FIXME: Validate register for the current architecture; we have to do // validation later, so maybe there is no need for this here. - unsigned RegNum = MatchRegisterName(Tok.getString()); - if (RegNum == 0) - return -1; + std::string upperCase = Tok.getString().str(); + std::string lowerCase = LowercaseString(upperCase); + unsigned RegNum = MatchRegisterName(lowerCase); + if (!RegNum) { + RegNum = StringSwitch(lowerCase) + .Case("r13", ARM::SP) + .Case("r14", ARM::LR) + .Case("r15", ARM::PC) + .Case("ip", ARM::R12) + .Default(0); + } + if (!RegNum) return -1; + Parser.Lex(); // Eat identifier token. return RegNum; } From grosser at fim.uni-passau.de Thu Jan 13 17:18:04 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 13 Jan 2011 23:18:04 -0000 Subject: [llvm-commits] [llvm] r123410 - in /llvm/trunk: include/llvm/Analysis/RegionInfo.h lib/Analysis/RegionInfo.cpp Message-ID: <20110113231804.DA8DE2A6C12C@llvm.org> Author: grosser Date: Thu Jan 13 17:18:04 2011 New Revision: 123410 URL: http://llvm.org/viewvc/llvm-project?rev=123410&view=rev Log: Add single entry / single exit accessors. Add methods for accessing the (single) entry / exit edge of a region. If no such edge exists, null is returned. Both accessors return the start block of the corresponding edge. The edge can finally be formed by utilizing Region::getEntry() or Region::getExit(); Contributed by: Andreas Simbuerger Modified: llvm/trunk/include/llvm/Analysis/RegionInfo.h llvm/trunk/lib/Analysis/RegionInfo.cpp Modified: llvm/trunk/include/llvm/Analysis/RegionInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/RegionInfo.h?rev=123410&r1=123409&r2=123410&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/RegionInfo.h (original) +++ llvm/trunk/include/llvm/Analysis/RegionInfo.h Thu Jan 13 17:18:04 2011 @@ -305,6 +305,20 @@ /// NULL if such a basic block does not exist. Region *getExpandedRegion() const; + /// @brief Return the first block of this region's single entry edge, + /// if existing. + /// + /// @return The BasicBlock starting this region's single entry edge, + /// else NULL. + BasicBlock *getEnteringBlock() const; + + /// @brief Return the first block of this region's single exit edge, + /// if existing. + /// + /// @return The BasicBlock starting this region's single exit edge, + /// else NULL. + BasicBlock *getExitingBlock() const; + /// @brief Is this a simple region? /// /// A region is simple if it has exactly one exit and one entry edge. Modified: llvm/trunk/lib/Analysis/RegionInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/RegionInfo.cpp?rev=123410&r1=123409&r2=123410&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/RegionInfo.cpp (original) +++ llvm/trunk/lib/Analysis/RegionInfo.cpp Thu Jan 13 17:18:04 2011 @@ -134,40 +134,49 @@ return outermostLoopInRegion(L); } -bool Region::isSimple() const { - bool isSimple = true; - bool found = false; - - BasicBlock *entry = getEntry(), *exit = getExit(); - - if (isTopLevelRegion()) - return false; +BasicBlock *Region::getEnteringBlock() const { + BasicBlock *entry = getEntry(); + BasicBlock *Pred; + BasicBlock *enteringBlock = 0; for (pred_iterator PI = pred_begin(entry), PE = pred_end(entry); PI != PE; ++PI) { - BasicBlock *Pred = *PI; + Pred = *PI; if (DT->getNode(Pred) && !contains(Pred)) { - if (found) { - isSimple = false; - break; - } - found = true; + if (enteringBlock) + return 0; + + enteringBlock = Pred; } } - found = false; + return enteringBlock; +} + +BasicBlock *Region::getExitingBlock() const { + BasicBlock *exit = getExit(); + BasicBlock *Pred; + BasicBlock *exitingBlock = 0; + + if (!exit) + return 0; for (pred_iterator PI = pred_begin(exit), PE = pred_end(exit); PI != PE; - ++PI) - if (contains(*PI)) { - if (found) { - isSimple = false; - break; - } - found = true; + ++PI) { + Pred = *PI; + if (contains(Pred)) { + if (exitingBlock) + return 0; + + exitingBlock = Pred; } + } + + return exitingBlock; +} - return isSimple; +bool Region::isSimple() const { + return !isTopLevelRegion() && getEnteringBlock() && getExitingBlock(); } std::string Region::getNameStr() const { From baldrick at free.fr Thu Jan 13 17:22:20 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 14 Jan 2011 00:22:20 +0100 Subject: [llvm-commits] [llvm] r123372 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll In-Reply-To: <0E8DEDA5-D30C-4832-98A9-EE9E3420B4CD@apple.com> References: <20110113085629.B95662A6C12D@llvm.org> <0E8DEDA5-D30C-4832-98A9-EE9E3420B4CD@apple.com> Message-ID: <4D2F892C.2060206@free.fr> Hi Chris, >> The most common simplification missed by instsimplify in unoptimized bitcode >> is "X != 0 -> X" when X is a boolean. This occurs a lot because of the way >> llvm-gcc converts gcc's conditional expressions. Add this, and a few other >> similar transforms for completeness. > > Hi Duncan, > > I don't really understand the motivation here: unoptimized code has lots of missed stuff, and instsimplify doesn't run for it, no? by unoptimized I mean just before the first instcombine run. Since instcombine first sees if SimplifyInstruction can mulch each instruction before working on it itself, catching missing simplifies on "unoptimized code" basically means finding stuff that could have been moved from instcombine to SimplifyInstruction but wasn't. In the case in question I didn't remove stuff from instcombine but it is still a win: if instcombine sees an ICmp with i1 operands it turns it into a logical operation, for example case ICmpInst::ICMP_NE: // icmp eq i1 A, B -> A^B return BinaryOperator::CreateXor(Op0, Op1); By catching cases in SimplifyInstruction you avoid creating a new instruction, revisiting it etc. This change reduced the number of instructions combined by 1% without any impact on final bitcode. > In any case, this looks very familiar to code already in instcombine. Can the instcombine code be zapped now? Unfortunately not because the instcombine logic is too general, see above. Ciao, Duncan. PS: My program that automatically finds simplifications finds all kinds of interesting ones [*] in optimized code, this unoptimized code one was just a warm up you might say :) [*] Interesting = occurs a lot. The program first harvests IR sequences from the test-suite, and orders them by how often they occur, before looking for simplifications in them. From evan.cheng at apple.com Thu Jan 13 17:27:39 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 13 Jan 2011 23:27:39 -0000 Subject: [llvm-commits] [llvm] r123411 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp Message-ID: <20110113232739.C93C42A6C12C@llvm.org> Author: evancheng Date: Thu Jan 13 17:27:39 2011 New Revision: 123411 URL: http://llvm.org/viewvc/llvm-project?rev=123411&view=rev Log: Add comment about Thumb2 fixup comments being completely bogus. Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=123411&r1=123410&r2=123411&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Thu Jan 13 17:27:39 2011 @@ -805,6 +805,8 @@ } } + // FIXME: Node the fixup comments for Thumb2 are completely bogus since the + // high order halfword of a 32-bit Thumb2 instruction is emitted first. OS << "encoding: ["; for (unsigned i = 0, e = Code.size(); i != e; ++i) { if (i) @@ -825,7 +827,7 @@ OS << format("0x%02x", uint8_t(Code[i])); } else { if (Code[i]) { - // some of the 8 bits require fix up. + // FIXME: Some of the 8 bits require fix up. OS << format("0x%02x", uint8_t(Code[i])) << '\'' << char('A' + MapEntry - 1) << '\''; } else From stoklund at 2pi.dk Thu Jan 13 17:35:53 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 13 Jan 2011 23:35:53 -0000 Subject: [llvm-commits] [llvm] r123413 - /llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Message-ID: <20110113233553.8C6C82A6C12C@llvm.org> Author: stoklund Date: Thu Jan 13 17:35:53 2011 New Revision: 123413 URL: http://llvm.org/viewvc/llvm-project?rev=123413&view=rev Log: Better terminator avoidance. This approach also works when the terminator doesn't have a slot index. (Which can happen??) Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Modified: llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp?rev=123413&r1=123412&r2=123413&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp (original) +++ llvm/trunk/lib/CodeGen/LiveDebugVariables.cpp Thu Jan 13 17:35:53 2011 @@ -589,14 +589,6 @@ SlotIndex Start = LIS.getMBBStartIdx(MBB); Idx = Idx.getBaseIndex(); - // Don't insert anything after the first terminator. - MachineBasicBlock::iterator Term = MBB->getFirstTerminator(); - if (Term != MBB->end() && !LIS.isNotInMIMap(Term) && - Idx >= LIS.getInstructionIndex(Term)) { - DL = Term->getDebugLoc(); - return Term; - } - // Try to find an insert location by going backwards from Idx. MachineInstr *MI; while (!(MI = LIS.getInstructionFromIndex(Idx))) { @@ -611,7 +603,9 @@ } // We found an instruction. The insert point is after the instr. DL = MI->getDebugLoc(); - return llvm::next(MachineBasicBlock::iterator(MI)); + // Don't insert anything after the first terminator, though. + return MI->getDesc().isTerminator() ? MBB->getFirstTerminator() : + llvm::next(MachineBasicBlock::iterator(MI)); } void UserValue::insertDebugValue(MachineBasicBlock *MBB, SlotIndex Idx, From grosser at fim.uni-passau.de Thu Jan 13 18:00:40 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 13 Jan 2011 19:00:40 -0500 Subject: [llvm-commits] [PATCH] Add single entry / single exit accessors. In-Reply-To: <4D2F50A9.2090803@googlemail.com> References: <4D2EE1B9.6020408@fim.uni-passau.de> <4D2F1A59.3020305@fim.uni-passau.de> <4D2F50A9.2090803@googlemail.com> Message-ID: <4D2F9228.6030706@fim.uni-passau.de> >>> >> - BasicBlock *Pred = *PI; >>> >> + Pred = *PI; >>> >> if (DT->getNode(Pred)&& !contains(Pred)) { >>> >> - if (found) { >>> >> - isSimple = false; >>> >> - break; >>> >> - } >>> >> - found = true; >>> >> + if (ee) >>> >> + return 0; >>> >> + >>> >> + ee = Pred; >> > Can you combine the two if conditions? > I don't understand, as the predicate > (DT->getNode(Pred)&& !contains(Pred)) has to be valid for > both statements inside the block, so I would have to recheck that in > an else branch after merging both if's? Perhaps I'm just not thinking > clearly, it's a bit late;-) Don't mind. I just looked at the patch and did not see the assignment. >>> >> +bool Region::isSimple() const { >>> >> + return !(isTopLevelRegion()) >>> >> +&& (getSingleEntryBlock() != 0) >>> >> +&& (getSingleExitBlock() != 0); >> > I am not sure if my email has removed some spaces/tabs. But please >> > recheck indentation. > I think so, the indentation is correct within my mail client. I attached > two versions of the patch > > without *.svn.patch was generated using git diff --no-prefix ... and > the other one was generated using git format-patch. The format-patch one is fine. I changed this slightly to fit into one line. I believe this makes it more readable. > + /// @brief Return the first block of this region's single entry edge, > + /// if existing. > + /// > + /// @return The BasicBlock starting this region's single entry edge, > + /// else NULL. > + BasicBlock *getSingleEntryBlock() const; > + > + /// @brief Return the first block of this region's single exit edge, > + /// if existing. > + /// > + /// @return The BasicBlock starting this region's single exit edge, > + /// else NULL. > + BasicBlock *getSingleExitBlock() const; You forgot to rename the functions in the header file. I committed the patch after fixing two items mentioned above: http://llvm.org/viewvc/llvm-project/?view=rev&revision=123410 Thanks for your contribution Tobi From sabre at nondot.org Thu Jan 13 18:01:01 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 14 Jan 2011 00:01:01 -0000 Subject: [llvm-commits] [llvm] r123414 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-gep.ll Message-ID: <20110114000101.DAFAF2A6C12C@llvm.org> Author: lattner Date: Thu Jan 13 18:01:01 2011 New Revision: 123414 URL: http://llvm.org/viewvc/llvm-project?rev=123414&view=rev Log: fix PR8961 - a fast isel miscompilation where we'd insert a new instruction after sext's generated for addressing that got folded. Previously we compiled test5 into: _test5: ## @test5 ## BB#0: movq -8(%rsp), %rax ## 8-byte Reload movq (%rdi,%rax), %rdi addq %rdx, %rdi movslq %esi, %rax movq %rax, -8(%rsp) ## 8-byte Spill movq %rdi, %rax ret which is insane and wrong. Now we produce: _test5: ## @test5 ## BB#0: movslq %esi, %rax movq (%rdi,%rax), %rax addq %rdx, %rax ret Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=123414&r1=123413&r2=123414&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Jan 13 18:01:01 2011 @@ -1933,7 +1933,7 @@ XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment); if (Result == 0) return false; - MI->getParent()->insert(MI, Result); + FuncInfo.MBB->insert(FuncInfo.InsertPt, Result); MI->eraseFromParent(); return true; } Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll?rev=123414&r1=123413&r2=123414&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Thu Jan 13 18:01:01 2011 @@ -70,3 +70,20 @@ ; X64: test4: ; X64: 128(%r{{.*}},%r{{.*}},8) } + +; PR8961 - Make sure the sext for the GEP addressing comes before the load that +; is folded. +define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind { + %v8 = getelementptr i8* %A, i32 %I + %v9 = bitcast i8* %v8 to i64* + %v10 = load i64* %v9 + %v11 = add i64 %B, %v10 + ret i64 %v11 +; X64: test5: +; X64: movslq %esi, %rax +; X64-NEXT: movq (%rdi,%rax), %rax +; X64-NEXT: addq %rdx, %rax +; X64-NEXT: ret +} + + From resistor at mac.com Thu Jan 13 18:36:41 2011 From: resistor at mac.com (Owen Anderson) Date: Fri, 14 Jan 2011 00:36:41 -0000 Subject: [llvm-commits] [llvm] r123416 - /llvm/trunk/include/llvm/Support/StandardPasses.h Message-ID: <20110114003641.15FD62A6C12C@llvm.org> Author: resistor Date: Thu Jan 13 18:36:40 2011 New Revision: 123416 URL: http://llvm.org/viewvc/llvm-project?rev=123416&view=rev Log: Don't bother conditionalizing the use of SROA in -O1 mode. We're already running it unconditionally later in the pipeline. Modified: llvm/trunk/include/llvm/Support/StandardPasses.h Modified: llvm/trunk/include/llvm/Support/StandardPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=123416&r1=123415&r2=123416&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) +++ llvm/trunk/include/llvm/Support/StandardPasses.h Thu Jan 13 18:36:40 2011 @@ -82,10 +82,7 @@ if (OptimizationLevel > 0) { createStandardAliasAnalysisPasses(PM); PM->add(createCFGSimplificationPass()); - if (OptimizationLevel == 1) - PM->add(createPromoteMemoryToRegisterPass()); - else - PM->add(createScalarReplAggregatesPass()); + PM->add(createScalarReplAggregatesPass()); PM->add(createInstructionCombiningPass()); } } From baldrick at free.fr Thu Jan 13 18:37:46 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 14 Jan 2011 00:37:46 -0000 Subject: [llvm-commits] [llvm] r123417 - in /llvm/trunk: include/llvm/Analysis/InstructionSimplify.h lib/Analysis/InstructionSimplify.cpp lib/Transforms/InstCombine/InstCombineShifts.cpp lib/VMCore/ConstantFold.cpp test/Transforms/InstCombine/shift.ll Message-ID: <20110114003746.1FD0F2A6C12C@llvm.org> Author: baldrick Date: Thu Jan 13 18:37:45 2011 New Revision: 123417 URL: http://llvm.org/viewvc/llvm-project?rev=123417&view=rev Log: Move some shift transforms out of instcombine and into InstructionSimplify. While there, I noticed that the transform "undef >>a X -> undef" was wrong. For example if X is 2 then the top two bits must be equal, so the result can not be anything. I fixed this in the constant folder as well. Also, I made the transform for "X << undef" stronger: it now folds to undef always, even though X might be zero. This is in accordance with the LangRef, but I must admit that it is fairly aggressive. Also, I added "i32 X << 32 -> undef" following the LangRef and the constant folder, likewise fairly aggressive. Modified: llvm/trunk/include/llvm/Analysis/InstructionSimplify.h llvm/trunk/lib/Analysis/InstructionSimplify.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp llvm/trunk/lib/VMCore/ConstantFold.cpp llvm/trunk/test/Transforms/InstCombine/shift.ll Modified: llvm/trunk/include/llvm/Analysis/InstructionSimplify.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/InstructionSimplify.h?rev=123417&r1=123416&r2=123417&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/InstructionSimplify.h (original) +++ llvm/trunk/include/llvm/Analysis/InstructionSimplify.h Thu Jan 13 18:37:45 2011 @@ -35,14 +35,29 @@ Value *SimplifySubInst(Value *LHS, Value *RHS, bool isNSW, bool isNUW, const TargetData *TD = 0, const DominatorTree *DT = 0); - /// SimplifyAndInst - Given operands for an And, see if we can + /// SimplifyMulInst - Given operands for a Mul, see if we can /// fold the result. If not, this returns null. - Value *SimplifyAndInst(Value *LHS, Value *RHS, const TargetData *TD = 0, + Value *SimplifyMulInst(Value *LHS, Value *RHS, const TargetData *TD = 0, const DominatorTree *DT = 0); - /// SimplifyMulInst - Given operands for a Mul, see if we can + /// SimplifyShlInst - Given operands for a Shl, see if we can /// fold the result. If not, this returns null. - Value *SimplifyMulInst(Value *LHS, Value *RHS, const TargetData *TD = 0, + Value *SimplifyShlInst(Value *Op0, Value *Op1, const TargetData *TD = 0, + const DominatorTree *DT = 0); + + /// SimplifyLShrInst - Given operands for a LShr, see if we can + /// fold the result. If not, this returns null. + Value *SimplifyLShrInst(Value *Op0, Value *Op1, const TargetData *TD = 0, + const DominatorTree *DT = 0); + + /// SimplifyAShrInst - Given operands for a AShr, see if we can + /// fold the result. If not, this returns null. + Value *SimplifyAShrInst(Value *Op0, Value *Op1, const TargetData *TD = 0, + const DominatorTree *DT = 0); + + /// SimplifyAndInst - Given operands for an And, see if we can + /// fold the result. If not, this returns null. + Value *SimplifyAndInst(Value *LHS, Value *RHS, const TargetData *TD = 0, const DominatorTree *DT = 0); /// SimplifyOrInst - Given operands for an Or, see if we can Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=123417&r1=123416&r2=123417&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Jan 13 18:37:45 2011 @@ -684,6 +684,136 @@ return ::SimplifyMulInst(Op0, Op1, TD, DT, RecursionLimit); } +/// SimplifyShlInst - Given operands for an Shl, see if we can +/// fold the result. If not, this returns null. +static Value *SimplifyShlInst(Value *Op0, Value *Op1, const TargetData *TD, + const DominatorTree *DT, unsigned MaxRecurse) { + if (Constant *C0 = dyn_cast(Op0)) { + if (Constant *C1 = dyn_cast(Op1)) { + Constant *Ops[] = { C0, C1 }; + return ConstantFoldInstOperands(Instruction::Shl, C0->getType(), Ops, 2, + TD); + } + } + + // 0 << X -> 0 + if (match(Op0, m_Zero())) + return Op0; + + // X << 0 -> X + if (match(Op1, m_Zero())) + return Op0; + + // undef << X -> 0 + if (isa(Op0)) + return Constant::getNullValue(Op0->getType()); + + // X << undef -> undef because it may shift by the bitwidth. + if (isa(Op1)) + return Op1; + + // Shifting by the bitwidth or more is undefined. + if (ConstantInt *CI = dyn_cast(Op1)) + if (CI->getValue().getLimitedValue() >= + Op0->getType()->getScalarSizeInBits()) + return UndefValue::get(Op0->getType()); + + return 0; +} + +Value *llvm::SimplifyShlInst(Value *Op0, Value *Op1, const TargetData *TD, + const DominatorTree *DT) { + return ::SimplifyShlInst(Op0, Op1, TD, DT, RecursionLimit); +} + +/// SimplifyLShrInst - Given operands for an LShr, see if we can +/// fold the result. If not, this returns null. +static Value *SimplifyLShrInst(Value *Op0, Value *Op1, const TargetData *TD, + const DominatorTree *DT, unsigned MaxRecurse) { + if (Constant *C0 = dyn_cast(Op0)) { + if (Constant *C1 = dyn_cast(Op1)) { + Constant *Ops[] = { C0, C1 }; + return ConstantFoldInstOperands(Instruction::LShr, C0->getType(), Ops, 2, + TD); + } + } + + // 0 >> X -> 0 + if (match(Op0, m_Zero())) + return Op0; + + // undef >>l X -> 0 + if (isa(Op0)) + return Constant::getNullValue(Op0->getType()); + + // X >> 0 -> X + if (match(Op1, m_Zero())) + return Op0; + + // X >> undef -> undef because it may shift by the bitwidth. + if (isa(Op1)) + return Op1; + + // Shifting by the bitwidth or more is undefined. + if (ConstantInt *CI = dyn_cast(Op1)) + if (CI->getValue().getLimitedValue() >= + Op0->getType()->getScalarSizeInBits()) + return UndefValue::get(Op0->getType()); + + return 0; +} + +Value *llvm::SimplifyLShrInst(Value *Op0, Value *Op1, const TargetData *TD, + const DominatorTree *DT) { + return ::SimplifyLShrInst(Op0, Op1, TD, DT, RecursionLimit); +} + +/// SimplifyAShrInst - Given operands for an AShr, see if we can +/// fold the result. If not, this returns null. +static Value *SimplifyAShrInst(Value *Op0, Value *Op1, const TargetData *TD, + const DominatorTree *DT, unsigned MaxRecurse) { + if (Constant *C0 = dyn_cast(Op0)) { + if (Constant *C1 = dyn_cast(Op1)) { + Constant *Ops[] = { C0, C1 }; + return ConstantFoldInstOperands(Instruction::AShr, C0->getType(), Ops, 2, + TD); + } + } + + // 0 >> X -> 0 + if (match(Op0, m_Zero())) + return Op0; + + // all ones >>a X -> all ones + if (match(Op0, m_AllOnes())) + return Op0; + + // undef >>a X -> all ones + if (isa(Op0)) + return Constant::getAllOnesValue(Op0->getType()); + + // X >> 0 -> X + if (match(Op1, m_Zero())) + return Op0; + + // X >> undef -> undef because it may shift by the bitwidth. + if (isa(Op1)) + return Op1; + + // Shifting by the bitwidth or more is undefined. + if (ConstantInt *CI = dyn_cast(Op1)) + if (CI->getValue().getLimitedValue() >= + Op0->getType()->getScalarSizeInBits()) + return UndefValue::get(Op0->getType()); + + return 0; +} + +Value *llvm::SimplifyAShrInst(Value *Op0, Value *Op1, const TargetData *TD, + const DominatorTree *DT) { + return ::SimplifyAShrInst(Op0, Op1, TD, DT, RecursionLimit); +} + /// SimplifyAndInst - Given operands for an And, see if we can /// fold the result. If not, this returns null. static Value *SimplifyAndInst(Value *Op0, Value *Op1, const TargetData *TD, @@ -1267,6 +1397,9 @@ /* isNUW */ false, TD, DT, MaxRecurse); case Instruction::Mul: return SimplifyMulInst(LHS, RHS, TD, DT, MaxRecurse); + case Instruction::Shl: return SimplifyShlInst(LHS, RHS, TD, DT, MaxRecurse); + case Instruction::LShr: return SimplifyLShrInst(LHS, RHS, TD, DT, MaxRecurse); + case Instruction::AShr: return SimplifyAShrInst(LHS, RHS, TD, DT, MaxRecurse); case Instruction::And: return SimplifyAndInst(LHS, RHS, TD, DT, MaxRecurse); case Instruction::Or: return SimplifyOrInst(LHS, RHS, TD, DT, MaxRecurse); case Instruction::Xor: return SimplifyXorInst(LHS, RHS, TD, DT, MaxRecurse); @@ -1345,6 +1478,15 @@ case Instruction::Mul: Result = SimplifyMulInst(I->getOperand(0), I->getOperand(1), TD, DT); break; + case Instruction::Shl: + Result = SimplifyShlInst(I->getOperand(0), I->getOperand(1), TD, DT); + break; + case Instruction::LShr: + Result = SimplifyLShrInst(I->getOperand(0), I->getOperand(1), TD, DT); + break; + case Instruction::AShr: + Result = SimplifyAShrInst(I->getOperand(0), I->getOperand(1), TD, DT); + break; case Instruction::And: Result = SimplifyAndInst(I->getOperand(0), I->getOperand(1), TD, DT); break; Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp?rev=123417&r1=123416&r2=123417&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineShifts.cpp Thu Jan 13 18:37:45 2011 @@ -13,6 +13,7 @@ #include "InstCombine.h" #include "llvm/IntrinsicInst.h" +#include "llvm/Analysis/InstructionSimplify.h" #include "llvm/Support/PatternMatch.h" using namespace llvm; using namespace PatternMatch; @@ -21,25 +22,6 @@ assert(I.getOperand(1)->getType() == I.getOperand(0)->getType()); Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); - // shl X, 0 == X and shr X, 0 == X - // shl 0, X == 0 and shr 0, X == 0 - if (Op1 == Constant::getNullValue(Op1->getType()) || - Op0 == Constant::getNullValue(Op0->getType())) - return ReplaceInstUsesWith(I, Op0); - - if (isa(Op0)) { - if (I.getOpcode() == Instruction::AShr) // undef >>s X -> undef - return ReplaceInstUsesWith(I, Op0); - else // undef << X -> 0, undef >>u X -> 0 - return ReplaceInstUsesWith(I, Constant::getNullValue(I.getType())); - } - if (isa(Op1)) { - if (I.getOpcode() == Instruction::AShr) // X >>s undef -> X - return ReplaceInstUsesWith(I, Op0); - else // X << undef, X >>u undef -> 0 - return ReplaceInstUsesWith(I, Constant::getNullValue(I.getType())); - } - // See if we can fold away this shift. if (SimplifyDemandedInstructionBits(I)) return &I; @@ -635,10 +617,15 @@ } Instruction *InstCombiner::visitShl(BinaryOperator &I) { + if (Value *V = SimplifyShlInst(I.getOperand(0), I.getOperand(1), TD)) + return ReplaceInstUsesWith(I, V); return commonShiftTransforms(I); } Instruction *InstCombiner::visitLShr(BinaryOperator &I) { + if (Value *V = SimplifyLShrInst(I.getOperand(0), I.getOperand(1), TD)) + return ReplaceInstUsesWith(I, V); + if (Instruction *R = commonShiftTransforms(I)) return R; @@ -665,17 +652,14 @@ } Instruction *InstCombiner::visitAShr(BinaryOperator &I) { + if (Value *V = SimplifyAShrInst(I.getOperand(0), I.getOperand(1), TD)) + return ReplaceInstUsesWith(I, V); + if (Instruction *R = commonShiftTransforms(I)) return R; Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); - - if (ConstantInt *CSI = dyn_cast(Op0)) { - // ashr int -1, X = -1 (for any arithmetic shift rights of ~0) - if (CSI->isAllOnesValue()) - return ReplaceInstUsesWith(I, CSI); - } - + if (ConstantInt *Op1C = dyn_cast(Op1)) { // If the input is a SHL by the same constant (ashr (shl X, C), C), then we // have a sign-extend idiom. Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=123417&r1=123416&r2=123417&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantFold.cpp (original) +++ llvm/trunk/lib/VMCore/ConstantFold.cpp Thu Jan 13 18:37:45 2011 @@ -977,8 +977,8 @@ return Constant::getNullValue(C1->getType()); // X lshr undef -> 0 // undef lshr X -> 0 case Instruction::AShr: - if (!isa(C2)) - return C1; // undef ashr X --> undef + if (!isa(C2)) // undef ashr X --> all ones + return Constant::getAllOnesValue(C1->getType()); else if (isa(C1)) return C1; // undef ashr undef -> undef else Modified: llvm/trunk/test/Transforms/InstCombine/shift.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/shift.ll?rev=123417&r1=123416&r2=123417&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/shift.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/shift.ll Thu Jan 13 18:37:45 2011 @@ -35,18 +35,32 @@ define i32 @test5(i32 %A) { ; CHECK: @test5 -; CHECK: ret i32 0 +; CHECK: ret i32 undef %B = lshr i32 %A, 32 ;; shift all bits out ret i32 %B } define i32 @test5a(i32 %A) { ; CHECK: @test5a -; CHECK: ret i32 0 +; CHECK: ret i32 undef %B = shl i32 %A, 32 ;; shift all bits out ret i32 %B } +define i32 @test5b() { +; CHECK: @test5b +; CHECK: ret i32 -1 + %B = ashr i32 undef, 2 ;; top two bits must be equal, so not undef + ret i32 %B +} + +define i32 @test5b2(i32 %A) { +; CHECK: @test5b2 +; CHECK: ret i32 -1 + %B = ashr i32 undef, %A ;; top %A bits must be equal, so not undef + ret i32 %B +} + define i32 @test6(i32 %A) { ; CHECK: @test6 ; CHECK-NEXT: mul i32 %A, 6 From resistor at mac.com Thu Jan 13 18:41:11 2011 From: resistor at mac.com (Owen Anderson) Date: Fri, 14 Jan 2011 00:41:11 -0000 Subject: [llvm-commits] [llvm] r123418 - /llvm/trunk/include/llvm/Support/StandardPasses.h Message-ID: <20110114004111.A94922A6C12C@llvm.org> Author: resistor Date: Thu Jan 13 18:41:11 2011 New Revision: 123418 URL: http://llvm.org/viewvc/llvm-project?rev=123418&view=rev Log: Rather than doing early instcombine, try doing early CSE instead. This should still handle most important simplifications, as well as resolving phase ordering issues where instcombine would inhibit important CSE'ing opportunities, for instance on BitBench/drop3. Modified: llvm/trunk/include/llvm/Support/StandardPasses.h Modified: llvm/trunk/include/llvm/Support/StandardPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=123418&r1=123417&r2=123418&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) +++ llvm/trunk/include/llvm/Support/StandardPasses.h Thu Jan 13 18:41:11 2011 @@ -83,7 +83,7 @@ createStandardAliasAnalysisPasses(PM); PM->add(createCFGSimplificationPass()); PM->add(createScalarReplAggregatesPass()); - PM->add(createInstructionCombiningPass()); + PM->add(createEarlyCSEPass()); } } From stoklund at 2pi.dk Thu Jan 13 19:17:54 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 14 Jan 2011 01:17:54 -0000 Subject: [llvm-commits] [llvm] r123419 - in /llvm/trunk/lib/CodeGen: MachineBasicBlock.cpp PHIElimination.cpp Message-ID: <20110114011754.16CE32A6C12C@llvm.org> Author: stoklund Date: Thu Jan 13 19:17:53 2011 New Revision: 123419 URL: http://llvm.org/viewvc/llvm-project?rev=123419&view=rev Log: Try again to teach getFirstTerminator() about debug values. Fix some callers to better deal with debug values. Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=123419&r1=123418&r2=123419&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Thu Jan 13 19:17:53 2011 @@ -155,11 +155,22 @@ } MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() { - iterator I = end(); - while (I != begin() && (--I)->getDesc().isTerminator()) - ; /*noop */ - if (I != end() && !I->getDesc().isTerminator()) ++I; - return I; + iterator B = begin(), I = end(); + iterator Term = I; + while (I != B) { + --I; + // Ignore any debug values after the first terminator. + if (I->isDebugValue()) + continue; + // Stop once we see a non-debug non-terminator. + if (!I->getDesc().isTerminator()) + break; + // Earliest terminator so far. + Term = I; + } + // Return the first terminator, or end(). + // Everything after Term is terminators and debug values. + return Term; } MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() { Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=123419&r1=123418&r2=123419&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Thu Jan 13 19:17:53 2011 @@ -339,6 +339,8 @@ #ifndef NDEBUG for (MachineBasicBlock::iterator TI = llvm::next(Term); TI != opBlock.end(); ++TI) { + if (TI->isDebugValue()) + continue; assert(!TI->readsRegister(SrcReg) && "Terminator instructions cannot use virtual registers unless" "they are the first terminator in a block!"); @@ -347,9 +349,13 @@ } else if (reusedIncoming || !IncomingReg) { // We may have to rewind a bit if we didn't insert a copy this time. KillInst = Term; - while (KillInst != opBlock.begin()) - if ((--KillInst)->readsRegister(SrcReg)) + while (KillInst != opBlock.begin()) { + --KillInst; + if (KillInst->isDebugValue()) + continue; + if (KillInst->readsRegister(SrcReg)) break; + } } else { // We just inserted this copy. KillInst = prior(InsertPos); From sabre at nondot.org Thu Jan 13 19:33:40 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 14 Jan 2011 01:33:40 -0000 Subject: [llvm-commits] [llvm] r123420 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <20110114013340.B61B52A6C12C@llvm.org> Author: lattner Date: Thu Jan 13 19:33:40 2011 New Revision: 123420 URL: http://llvm.org/viewvc/llvm-project?rev=123420&view=rev Log: Set the insertion point correctly for instructions generated by load folding: they should go *before* the new instruction not after it. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=123420&r1=123419&r2=123420&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Thu Jan 13 19:33:40 2011 @@ -890,10 +890,10 @@ if (Inst != Begin) BeforeInst = llvm::prior(llvm::prior(BI)); if (BeforeInst && isa(BeforeInst) && - BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst && - TryToFoldFastISelLoad(cast(BeforeInst), FastIS)) { - // If we succeeded, don't re-select the load. - --BI; + BeforeInst->hasOneUse() && *BeforeInst->use_begin() == Inst) { + FastIS->recomputeInsertPt(); + if (TryToFoldFastISelLoad(cast(BeforeInst), FastIS)) + --BI; // If we succeeded, don't re-select the load. } continue; } From echristo at apple.com Thu Jan 13 20:09:23 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 13 Jan 2011 18:09:23 -0800 Subject: [llvm-commits] [llvm] r123420 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp In-Reply-To: <20110114013340.B61B52A6C12C@llvm.org> References: <20110114013340.B61B52A6C12C@llvm.org> Message-ID: <87CD7864-C3F9-494F-8BE6-E5030C06F4D4@apple.com> On Jan 13, 2011, at 5:33 PM, Chris Lattner wrote: > Author: lattner > Date: Thu Jan 13 19:33:40 2011 > New Revision: 123420 > > URL: http://llvm.org/viewvc/llvm-project?rev=123420&view=rev > Log: > Set the insertion point correctly for instructions generated by load folding: > they should go *before* the new instruction not after it. Thanks! This fixed a miscompilation in llvm-gcc that I'd just run into! -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/6628c8db/attachment.html From sabre at nondot.org Thu Jan 13 20:07:32 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 14 Jan 2011 02:07:32 -0000 Subject: [llvm-commits] [llvm] r123422 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-gep.ll Message-ID: <20110114020732.660022A6C12C@llvm.org> Author: lattner Date: Thu Jan 13 20:07:32 2011 New Revision: 123422 URL: http://llvm.org/viewvc/llvm-project?rev=123422&view=rev Log: r123414 broke llvm-gcc bootstrap apparently, revert Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=123422&r1=123421&r2=123422&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Jan 13 20:07:32 2011 @@ -1933,7 +1933,7 @@ XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment); if (Result == 0) return false; - FuncInfo.MBB->insert(FuncInfo.InsertPt, Result); + MI->getParent()->insert(MI, Result); MI->eraseFromParent(); return true; } Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll?rev=123422&r1=123421&r2=123422&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Thu Jan 13 20:07:32 2011 @@ -70,20 +70,3 @@ ; X64: test4: ; X64: 128(%r{{.*}},%r{{.*}},8) } - -; PR8961 - Make sure the sext for the GEP addressing comes before the load that -; is folded. -define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind { - %v8 = getelementptr i8* %A, i32 %I - %v9 = bitcast i8* %v8 to i64* - %v10 = load i64* %v9 - %v11 = add i64 %B, %v10 - ret i64 %v11 -; X64: test5: -; X64: movslq %esi, %rax -; X64-NEXT: movq (%rdi,%rax), %rax -; X64-NEXT: addq %rdx, %rax -; X64-NEXT: ret -} - - From stoklund at 2pi.dk Thu Jan 13 20:12:54 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 14 Jan 2011 02:12:54 -0000 Subject: [llvm-commits] [llvm] r123423 - in /llvm/trunk/lib/CodeGen: MachineBasicBlock.cpp PHIElimination.cpp Message-ID: <20110114021254.EDE362A6C12C@llvm.org> Author: stoklund Date: Thu Jan 13 20:12:54 2011 New Revision: 123423 URL: http://llvm.org/viewvc/llvm-project?rev=123423&view=rev Log: Revert r123419. It still breaks llvm-gcc-i386-linux-selfhost. Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=123423&r1=123422&r2=123423&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Thu Jan 13 20:12:54 2011 @@ -155,22 +155,11 @@ } MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() { - iterator B = begin(), I = end(); - iterator Term = I; - while (I != B) { - --I; - // Ignore any debug values after the first terminator. - if (I->isDebugValue()) - continue; - // Stop once we see a non-debug non-terminator. - if (!I->getDesc().isTerminator()) - break; - // Earliest terminator so far. - Term = I; - } - // Return the first terminator, or end(). - // Everything after Term is terminators and debug values. - return Term; + iterator I = end(); + while (I != begin() && (--I)->getDesc().isTerminator()) + ; /*noop */ + if (I != end() && !I->getDesc().isTerminator()) ++I; + return I; } MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() { Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=123423&r1=123422&r2=123423&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Thu Jan 13 20:12:54 2011 @@ -339,8 +339,6 @@ #ifndef NDEBUG for (MachineBasicBlock::iterator TI = llvm::next(Term); TI != opBlock.end(); ++TI) { - if (TI->isDebugValue()) - continue; assert(!TI->readsRegister(SrcReg) && "Terminator instructions cannot use virtual registers unless" "they are the first terminator in a block!"); @@ -349,13 +347,9 @@ } else if (reusedIncoming || !IncomingReg) { // We may have to rewind a bit if we didn't insert a copy this time. KillInst = Term; - while (KillInst != opBlock.begin()) { - --KillInst; - if (KillInst->isDebugValue()) - continue; - if (KillInst->readsRegister(SrcReg)) + while (KillInst != opBlock.begin()) + if ((--KillInst)->readsRegister(SrcReg)) break; - } } else { // We just inserted this copy. KillInst = prior(InsertPos); From evan.cheng at apple.com Thu Jan 13 20:38:49 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Fri, 14 Jan 2011 02:38:49 -0000 Subject: [llvm-commits] [llvm] r123424 - in /llvm/trunk: include/llvm/Object/MachOFormat.h lib/MC/ELFObjectWriter.cpp lib/MC/MachObjectWriter.cpp lib/Target/ARM/ARMAsmBackend.cpp lib/Target/ARM/ARMFixupKinds.h lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/elf-movt.s test/MC/ARM/hilo-16bit-relocations.s Message-ID: <20110114023849.90EF02A6C12C@llvm.org> Author: evancheng Date: Thu Jan 13 20:38:49 2011 New Revision: 123424 URL: http://llvm.org/viewvc/llvm-project?rev=123424&view=rev Log: Completed :lower16: / :upper16: support for movw / movt pairs on Darwin. - Fixed :upper16: fix up routine. It should be shifting down the top 16 bits first. - Added support for Thumb2 :lower16: and :upper16: fix up. - Added :upper16: and :lower16: relocation support to mach-o object writer. Modified: llvm/trunk/include/llvm/Object/MachOFormat.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MachObjectWriter.cpp llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp llvm/trunk/lib/Target/ARM/ARMFixupKinds.h llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/elf-movt.s llvm/trunk/test/MC/ARM/hilo-16bit-relocations.s Modified: llvm/trunk/include/llvm/Object/MachOFormat.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/MachOFormat.h?rev=123424&r1=123423&r2=123424&view=diff ============================================================================== --- llvm/trunk/include/llvm/Object/MachOFormat.h (original) +++ llvm/trunk/include/llvm/Object/MachOFormat.h Thu Jan 13 20:38:49 2011 @@ -353,7 +353,10 @@ RIT_ARM_PreboundLazyPointer = 4, RIT_ARM_Branch24Bit = 5, RIT_ARM_ThumbBranch22Bit = 6, - RIT_ARM_ThumbBranch32Bit = 7 + RIT_ARM_ThumbBranch32Bit = 7, + RIT_ARM_Half = 8, + RIT_ARM_HalfDifference = 9 + }; } // end namespace macho Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=123424&r1=123423&r2=123424&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Thu Jan 13 20:38:49 2011 @@ -1508,6 +1508,14 @@ case ARM::fixup_arm_movw_lo16_pcrel: Type = ELF::R_ARM_MOVW_PREL_NC; break; + case ARM::fixup_t2_movt_hi16: + case ARM::fixup_t2_movt_hi16_pcrel: + Type = ELF::R_ARM_THM_MOVT_PREL; + break; + case ARM::fixup_t2_movw_lo16: + case ARM::fixup_t2_movw_lo16_pcrel: + Type = ELF::R_ARM_THM_MOVW_PREL_NC; + break; } } else { switch ((unsigned)Fixup.getKind()) { @@ -1555,6 +1563,12 @@ case ARM::fixup_arm_movw_lo16: Type = ELF::R_ARM_MOVW_ABS_NC; break; + case ARM::fixup_t2_movt_hi16: + Type = ELF::R_ARM_THM_MOVT_ABS; + break; + case ARM::fixup_t2_movw_lo16: + Type = ELF::R_ARM_THM_MOVW_ABS_NC; + break; } } Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=123424&r1=123423&r2=123424&view=diff ============================================================================== --- llvm/trunk/lib/MC/MachObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Jan 13 20:38:49 2011 @@ -656,10 +656,10 @@ const MCAsmLayout &Layout, const MCFragment *Fragment, const MCFixup &Fixup, MCValue Target, + unsigned Log2Size, uint64_t &FixedValue) { uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset(); unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind()); - unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind()); unsigned Type = macho::RIT_Vanilla; // See . @@ -720,10 +720,10 @@ const MCAsmLayout &Layout, const MCFragment *Fragment, const MCFixup &Fixup, MCValue Target, + unsigned Log2Size, uint64_t &FixedValue) { uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset(); unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind()); - unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind()); unsigned Type = macho::RIT_Vanilla; // See . @@ -775,6 +775,100 @@ Relocations[Fragment->getParent()].push_back(MRE); } + void RecordARMMovwMovtRelocation(const MCAssembler &Asm, + const MCAsmLayout &Layout, + const MCFragment *Fragment, + const MCFixup &Fixup, MCValue Target, + uint64_t &FixedValue) { + uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset(); + unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind()); + unsigned Type = macho::RIT_ARM_Half; + + // See . + const MCSymbol *A = &Target.getSymA()->getSymbol(); + MCSymbolData *A_SD = &Asm.getSymbolData(*A); + + if (!A_SD->getFragment()) + report_fatal_error("symbol '" + A->getName() + + "' can not be undefined in a subtraction expression"); + + uint32_t Value = getSymbolAddress(A_SD, Layout); + uint32_t Value2 = 0; + uint64_t SecAddr = getSectionAddress(A_SD->getFragment()->getParent()); + FixedValue += SecAddr; + + if (const MCSymbolRefExpr *B = Target.getSymB()) { + MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol()); + + if (!B_SD->getFragment()) + report_fatal_error("symbol '" + B->getSymbol().getName() + + "' can not be undefined in a subtraction expression"); + + // Select the appropriate difference relocation type. + Type = macho::RIT_ARM_HalfDifference; + Value2 = getSymbolAddress(B_SD, Layout); + FixedValue -= getSectionAddress(B_SD->getFragment()->getParent()); + } + + // Relocations are written out in reverse order, so the PAIR comes first. + // ARM_RELOC_HALF and ARM_RELOC_HALF_SECTDIFF abuse the r_length field: + // + // For these two r_type relocations they always have a pair following them + // and the r_length bits are used differently. The encoding of the + // r_length is as follows: + // low bit of r_length: + // 0 - :lower16: for movw instructions + // 1 - :upper16: for movt instructions + // high bit of r_length: + // 0 - arm instructions + // 1 - thumb instructions + // the other half of the relocated expression is in the following pair + // relocation entry in the the low 16 bits of r_address field. + unsigned ThumbBit = 0; + unsigned MovtBit = 0; + switch (Fixup.getKind()) { + default: break; + case ARM::fixup_arm_movt_hi16: + case ARM::fixup_arm_movt_hi16_pcrel: + MovtBit = 1; + break; + case ARM::fixup_t2_movt_hi16: + case ARM::fixup_t2_movt_hi16_pcrel: + MovtBit = 1; + // Fallthrough + case ARM::fixup_t2_movw_lo16: + case ARM::fixup_t2_movw_lo16_pcrel: + ThumbBit = 1; + break; + } + + + if (Type == macho::RIT_ARM_HalfDifference) { + uint32_t OtherHalf = MovtBit + ? (FixedValue & 0xffff) : ((FixedValue & 0xffff0000) >> 16); + + macho::RelocationEntry MRE; + MRE.Word0 = ((OtherHalf << 0) | + (macho::RIT_Pair << 24) | + (MovtBit << 28) | + (ThumbBit << 29) | + (IsPCRel << 30) | + macho::RF_Scattered); + MRE.Word1 = Value2; + Relocations[Fragment->getParent()].push_back(MRE); + } + + macho::RelocationEntry MRE; + MRE.Word0 = ((FixupOffset << 0) | + (Type << 24) | + (MovtBit << 28) | + (ThumbBit << 29) | + (IsPCRel << 30) | + macho::RF_Scattered); + MRE.Word1 = Value; + Relocations[Fragment->getParent()].push_back(MRE); + } + void RecordTLVPRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout, const MCFragment *Fragment, @@ -868,6 +962,24 @@ // Report as 'long', even though that is not quite accurate. Log2Size = llvm::Log2_32(4); return true; + + case ARM::fixup_arm_movt_hi16: + case ARM::fixup_arm_movt_hi16_pcrel: + case ARM::fixup_t2_movt_hi16: + case ARM::fixup_t2_movt_hi16_pcrel: + RelocType = unsigned(macho::RIT_ARM_HalfDifference); + // Report as 'long', even though that is not quite accurate. + Log2Size = llvm::Log2_32(4); + return true; + + case ARM::fixup_arm_movw_lo16: + case ARM::fixup_arm_movw_lo16_pcrel: + case ARM::fixup_t2_movw_lo16: + case ARM::fixup_t2_movw_lo16_pcrel: + RelocType = unsigned(macho::RIT_ARM_Half); + // Report as 'long', even though that is not quite accurate. + Log2Size = llvm::Log2_32(4); + return true; } } void RecordARMRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout, @@ -884,9 +996,14 @@ // If this is a difference or a defined symbol plus an offset, then we need // a scattered relocation entry. Differences always require scattered // relocations. - if (Target.getSymB()) - return RecordARMScatteredRelocation(Asm, Layout, Fragment, Fixup, - Target, FixedValue); + if (Target.getSymB()) { + if (RelocType == macho::RIT_ARM_Half || + RelocType == macho::RIT_ARM_HalfDifference) + return RecordARMMovwMovtRelocation(Asm, Layout, Fragment, Fixup, + Target, FixedValue); + return RecordARMScatteredRelocation(Asm, Layout, Fragment, Fixup, + Target, Log2Size, FixedValue); + } // Get the symbol data, if any. MCSymbolData *SD = 0; @@ -902,8 +1019,8 @@ if (IsPCRel && RelocType == macho::RIT_Vanilla) Offset += 1 << Log2Size; if (Offset && SD && !doesSymbolRequireExternRelocation(SD)) - return RecordARMScatteredRelocation(Asm, Layout, Fragment, Fixup, - Target, FixedValue); + return RecordARMScatteredRelocation(Asm, Layout, Fragment, Fixup, Target, + Log2Size, FixedValue); // See . uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset(); @@ -986,7 +1103,7 @@ // Differences always require scattered relocations. if (Target.getSymB()) return RecordScatteredRelocation(Asm, Layout, Fragment, Fixup, - Target, FixedValue); + Target, Log2Size, FixedValue); // Get the symbol data, if any. MCSymbolData *SD = 0; @@ -1000,7 +1117,7 @@ Offset += 1 << Log2Size; if (Offset && SD && !doesSymbolRequireExternRelocation(SD)) return RecordScatteredRelocation(Asm, Layout, Fragment, Fixup, - Target, FixedValue); + Target, Log2Size, FixedValue); // See . uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset(); Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=123424&r1=123423&r2=123424&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Thu Jan 13 20:38:49 2011 @@ -76,10 +76,15 @@ { "fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_cp", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, { "fixup_arm_thumb_bcc", 1, 8, MCFixupKindInfo::FKF_IsPCRel }, -{ "fixup_arm_movt_hi16", 0, 16, 0 }, -{ "fixup_arm_movw_lo16", 0, 16, 0 }, -{ "fixup_arm_movt_hi16_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, -{ "fixup_arm_movw_lo16_pcrel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }, +// movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 - 19. +{ "fixup_arm_movt_hi16", 0, 20, 0 }, +{ "fixup_arm_movw_lo16", 0, 20, 0 }, +{ "fixup_t2_movt_hi16", 0, 20, 0 }, +{ "fixup_t2_movw_lo16", 0, 20, 0 }, +{ "fixup_arm_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_arm_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_t2_movt_hi16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, +{ "fixup_t2_movw_lo16_pcrel", 0, 20, MCFixupKindInfo::FKF_IsPCRel }, }; if (Kind < FirstTargetFixupKind) @@ -158,8 +163,10 @@ case FK_Data_4: return Value; case ARM::fixup_arm_movt_hi16: - case ARM::fixup_arm_movw_lo16: case ARM::fixup_arm_movt_hi16_pcrel: + Value >>= 16; + // Fallthrough + case ARM::fixup_arm_movw_lo16: case ARM::fixup_arm_movw_lo16_pcrel: { unsigned Hi4 = (Value & 0xF000) >> 12; unsigned Lo12 = Value & 0x0FFF; @@ -168,6 +175,26 @@ Value = (Hi4 << 16) | (Lo12); return Value; } + case ARM::fixup_t2_movt_hi16: + case ARM::fixup_t2_movt_hi16_pcrel: + Value >>= 16; + // Fallthrough + case ARM::fixup_t2_movw_lo16: + case ARM::fixup_t2_movw_lo16_pcrel: { + unsigned Hi4 = (Value & 0xF000) >> 12; + unsigned i = (Value & 0x800) >> 11; + unsigned Mid3 = (Value & 0x700) >> 8; + unsigned Lo8 = Value & 0x0FF; + // inst{19-16} = Hi4; + // inst{26} = i; + // inst{14-12} = Mid3; + // inst{7-0} = Lo8; + Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); + + uint64_t swapped = (Value & 0xFFFF0000) >> 16; + swapped |= (Value & 0x0000FFFF) << 16; + return swapped; + } case ARM::fixup_arm_ldst_pcrel_12: // ARM PC-relative values are offset by 8. Value -= 4; @@ -438,6 +465,14 @@ case ARM::fixup_t2_adr_pcrel_12: case ARM::fixup_arm_thumb_bl: case ARM::fixup_arm_thumb_blx: + case ARM::fixup_arm_movt_hi16: + case ARM::fixup_arm_movw_lo16: + case ARM::fixup_arm_movt_hi16_pcrel: + case ARM::fixup_arm_movw_lo16_pcrel: + case ARM::fixup_t2_movt_hi16: + case ARM::fixup_t2_movw_lo16: + case ARM::fixup_t2_movt_hi16_pcrel: + case ARM::fixup_t2_movw_lo16_pcrel: return 4; } } Modified: llvm/trunk/lib/Target/ARM/ARMFixupKinds.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFixupKinds.h?rev=123424&r1=123423&r2=123424&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFixupKinds.h (original) +++ llvm/trunk/lib/Target/ARM/ARMFixupKinds.h Thu Jan 13 20:38:49 2011 @@ -70,9 +70,10 @@ // The next two are for the movt/movw pair // the 16bit imm field are split into imm{15-12} and imm{11-0} - // Fixme: We need new ones for Thumb. fixup_arm_movt_hi16, // :upper16: fixup_arm_movw_lo16, // :lower16: + fixup_t2_movt_hi16, // :upper16: + fixup_t2_movw_lo16, // :lower16: // It is possible to create an "immediate" that happens to be pcrel. // movw r0, :lower16:Foo-(Bar+8) and movt r0, :upper16:Foo-(Bar+8) @@ -80,6 +81,8 @@ // Needed to support ELF::R_ARM_MOVT_PREL and ELF::R_ARM_MOVW_PREL_NC fixup_arm_movt_hi16_pcrel, // :upper16: fixup_arm_movw_lo16_pcrel, // :lower16: + fixup_t2_movt_hi16_pcrel, // :upper16: + fixup_t2_movw_lo16_pcrel, // :lower16: // Marker LastTargetFixupKind, Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=123424&r1=123423&r2=123424&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Thu Jan 13 20:38:49 2011 @@ -17,6 +17,7 @@ #include "ARMFixupKinds.h" #include "ARMInstrInfo.h" #include "ARMMCExpr.h" +#include "ARMSubtarget.h" #include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCExpr.h" #include "llvm/MC/MCInst.h" @@ -33,11 +34,13 @@ void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT const TargetMachine &TM; const TargetInstrInfo &TII; + const ARMSubtarget *Subtarget; MCContext &Ctx; public: ARMMCCodeEmitter(TargetMachine &tm, MCContext &ctx) - : TM(tm), TII(*TM.getInstrInfo()), Ctx(ctx) { + : TM(tm), TII(*TM.getInstrInfo()), + Subtarget(&TM.getSubtarget()), Ctx(ctx) { } ~ARMMCCodeEmitter() {} @@ -306,8 +309,7 @@ /// Thumb2 mode. unsigned ARMMCCodeEmitter::NEONThumb2DataIPostEncoder(const MCInst &MI, unsigned EncodedValue) const { - const ARMSubtarget &Subtarget = TM.getSubtarget(); - if (Subtarget.isThumb2()) { + if (Subtarget->isThumb2()) { // NEON Thumb2 data-processsing encodings are very simple: bit 24 is moved // to bit 12 of the high half-word (i.e. bit 28), and bits 27-24 are // set to 1111. @@ -326,8 +328,7 @@ /// Thumb2 mode. unsigned ARMMCCodeEmitter::NEONThumb2LoadStorePostEncoder(const MCInst &MI, unsigned EncodedValue) const { - const ARMSubtarget &Subtarget = TM.getSubtarget(); - if (Subtarget.isThumb2()) { + if (Subtarget->isThumb2()) { EncodedValue &= 0xF0FFFFFF; EncodedValue |= 0x09000000; } @@ -340,8 +341,7 @@ /// Thumb2 mode. unsigned ARMMCCodeEmitter::NEONThumb2DupPostEncoder(const MCInst &MI, unsigned EncodedValue) const { - const ARMSubtarget &Subtarget = TM.getSubtarget(); - if (Subtarget.isThumb2()) { + if (Subtarget->isThumb2()) { EncodedValue &= 0x00FFFFFF; EncodedValue |= 0xEE000000; } @@ -353,7 +353,7 @@ /// them to their Thumb2 form if we are currently in Thumb2 mode. unsigned ARMMCCodeEmitter:: VFPThumb2PostEncoder(const MCInst &MI, unsigned EncodedValue) const { - if (TM.getSubtarget().isThumb2()) { + if (Subtarget->isThumb2()) { EncodedValue &= 0x0FFFFFFF; EncodedValue |= 0xE0000000; } @@ -477,8 +477,7 @@ SmallVectorImpl &Fixups) const { // FIXME: This really, really shouldn't use TargetMachine. We don't want // coupling between MC and TM anywhere we can help it. - const ARMSubtarget &Subtarget = TM.getSubtarget(); - if (Subtarget.isThumb2()) + if (Subtarget->isThumb2()) return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_condbranch, Fixups); return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_arm_branch, Fixups); @@ -575,9 +574,8 @@ else Expr = MO2.getExpr(); - const ARMSubtarget &Subtarget = TM.getSubtarget(); MCFixupKind Kind; - if (Subtarget.isThumb2()) + if (Subtarget->isThumb2()) Kind = MCFixupKind(ARM::fixup_t2_ldst_pcrel_12); else Kind = MCFixupKind(ARM::fixup_arm_ldst_pcrel_12); @@ -662,14 +660,24 @@ switch (ARM16Expr->getKind()) { default: assert(0 && "Unsupported ARMFixup"); case ARMMCExpr::VK_ARM_HI16: - Kind = MCFixupKind(ARM::fixup_arm_movt_hi16); - if (EvaluateAsPCRel(E)) - Kind = MCFixupKind(ARM::fixup_arm_movt_hi16_pcrel); + if (!Subtarget->isTargetDarwin() && EvaluateAsPCRel(E)) + Kind = MCFixupKind(Subtarget->isThumb2() + ? ARM::fixup_t2_movt_hi16_pcrel + : ARM::fixup_arm_movt_hi16_pcrel); + else + Kind = MCFixupKind(Subtarget->isThumb2() + ? ARM::fixup_t2_movt_hi16 + : ARM::fixup_arm_movt_hi16); break; case ARMMCExpr::VK_ARM_LO16: - Kind = MCFixupKind(ARM::fixup_arm_movw_lo16); - if (EvaluateAsPCRel(E)) - Kind = MCFixupKind(ARM::fixup_arm_movw_lo16_pcrel); + if (!Subtarget->isTargetDarwin() && EvaluateAsPCRel(E)) + Kind = MCFixupKind(Subtarget->isThumb2() + ? ARM::fixup_t2_movw_lo16_pcrel + : ARM::fixup_arm_movw_lo16_pcrel); + else + Kind = MCFixupKind(Subtarget->isThumb2() + ? ARM::fixup_t2_movw_lo16 + : ARM::fixup_arm_movw_lo16); break; } Fixups.push_back(MCFixup::Create(0, E, Kind)); @@ -841,8 +849,7 @@ assert(MO.isExpr() && "Unexpected machine operand type!"); const MCExpr *Expr = MO.getExpr(); MCFixupKind Kind; - const ARMSubtarget &Subtarget = TM.getSubtarget(); - if (Subtarget.isThumb2()) + if (Subtarget->isThumb2()) Kind = MCFixupKind(ARM::fixup_t2_pcrel_10); else Kind = MCFixupKind(ARM::fixup_arm_pcrel_10); @@ -1151,7 +1158,6 @@ void ARMMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups) const { - const ARMSubtarget &Subtarget = TM.getSubtarget(); // Pseudo instructions don't get encoded. const TargetInstrDesc &Desc = TII.get(MI.getOpcode()); uint64_t TSFlags = Desc.TSFlags; @@ -1167,7 +1173,7 @@ uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); // Thumb 32-bit wide instructions need to emit the high order halfword // first. - if (Subtarget.isThumb() && Size == 4) { + if (Subtarget->isThumb() && Size == 4) { EmitConstant(Binary >> 16, 2, OS); EmitConstant(Binary & 0xffff, 2, OS); } else Modified: llvm/trunk/test/MC/ARM/elf-movt.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/elf-movt.s?rev=123424&r1=123423&r2=123424&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/elf-movt.s (original) +++ llvm/trunk/test/MC/ARM/elf-movt.s Thu Jan 13 20:38:49 2011 @@ -25,7 +25,7 @@ @ OBJ-NEXT: 'sh_info', 0x00000000 @ OBJ-NEXT: 'sh_addralign', 0x00000004 @ OBJ-NEXT: 'sh_entsize', 0x00000000 -@ OBJ-NEXT: '_section_data', 'f00f0fe3 ec0f4fe3' +@ OBJ-NEXT: '_section_data', 'f00f0fe3 ff0f4fe3' @ OBJ: Relocation 0x00000000 @ OBJ-NEXT: 'r_offset', 0x00000000 Modified: llvm/trunk/test/MC/ARM/hilo-16bit-relocations.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/hilo-16bit-relocations.s?rev=123424&r1=123423&r2=123424&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/hilo-16bit-relocations.s (original) +++ llvm/trunk/test/MC/ARM/hilo-16bit-relocations.s Thu Jan 13 20:38:49 2011 @@ -1,14 +1,13 @@ -@ RUN: llvm-mc %s -triple armv7-apple-darwin -show-encoding | FileCheck %s +@ RUN: llvm-mc %s -triple armv7-apple-darwin | FileCheck %s +@ RUN: llvm-mc %s -triple armv7-apple-darwin | FileCheck %s _t: movw r0, :lower16:(L_foo$non_lazy_ptr - (L1 + 8)) movt r0, :upper16:(L_foo$non_lazy_ptr - (L1 + 8)) L1: -@ CHECK: movw r0, :lower16:(L_foo$non_lazy_ptr-(L1+8)) @ encoding: [A,A,0x00,0xe3] -@ CHECK: @ fixup A - offset: 0, value: L_foo$non_lazy_ptr-(L1+8), kind: fixup_arm_movw_lo16_pcrel -@ CHECK: movt r0, :upper16:(L_foo$non_lazy_ptr-(L1+8)) @ encoding: [A,A,0x40,0xe3] -@ CHECK: @ fixup A - offset: 0, value: L_foo$non_lazy_ptr-(L1+8), kind: fixup_arm_movt_hi16_pcrel +@ CHECK: movw r0, :lower16:(L_foo$non_lazy_ptr-(L1+8)) +@ CHECK: movt r0, :upper16:(L_foo$non_lazy_ptr-(L1+8)) .comm _foo,4,2 From sabre at nondot.org Thu Jan 13 22:23:53 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 14 Jan 2011 04:23:53 -0000 Subject: [llvm-commits] [llvm] r123426 - /llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Message-ID: <20110114042353.636A12A6C12C@llvm.org> Author: lattner Date: Thu Jan 13 22:23:53 2011 New Revision: 123426 URL: http://llvm.org/viewvc/llvm-project?rev=123426&view=rev Log: indentation Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=123426&r1=123425&r2=123426&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Thu Jan 13 22:23:53 2011 @@ -283,7 +283,7 @@ I != E; ++I) { BasicBlock *P = *I; if (P != NewBB) - OtherPreds.push_back(P); + OtherPreds.push_back(P); } } From sabre at nondot.org Thu Jan 13 22:24:28 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 14 Jan 2011 04:24:28 -0000 Subject: [llvm-commits] [llvm] r123427 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-gep.ll Message-ID: <20110114042428.94FD82A6C12C@llvm.org> Author: lattner Date: Thu Jan 13 22:24:28 2011 New Revision: 123427 URL: http://llvm.org/viewvc/llvm-project?rev=123427&view=rev Log: reapply r123414 now that the botz are calmed down and the fix is already in. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=123427&r1=123426&r2=123427&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Jan 13 22:24:28 2011 @@ -1933,7 +1933,7 @@ XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment); if (Result == 0) return false; - MI->getParent()->insert(MI, Result); + FuncInfo.MBB->insert(FuncInfo.InsertPt, Result); MI->eraseFromParent(); return true; } Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll?rev=123427&r1=123426&r2=123427&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Thu Jan 13 22:24:28 2011 @@ -70,3 +70,20 @@ ; X64: test4: ; X64: 128(%r{{.*}},%r{{.*}},8) } + +; PR8961 - Make sure the sext for the GEP addressing comes before the load that +; is folded. +define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind { + %v8 = getelementptr i8* %A, i32 %I + %v9 = bitcast i8* %v8 to i64* + %v10 = load i64* %v9 + %v11 = add i64 %B, %v10 + ret i64 %v11 +; X64: test5: +; X64: movslq %esi, %rax +; X64-NEXT: movq (%rdi,%rax), %rax +; X64-NEXT: addq %rdx, %rax +; X64-NEXT: ret +} + + From geek4civic at gmail.com Thu Jan 13 22:41:59 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Fri, 14 Jan 2011 13:41:59 +0900 Subject: [llvm-commits] [Review request] Tweaking Win64 Codegen In-Reply-To: <6C9AA982-EFB8-4020-AEA2-273C6C1C721C@2pi.dk> References: <6C9AA982-EFB8-4020-AEA2-273C6C1C721C@2pi.dk> Message-ID: Hello Jakob and all. 2011/1/11 Jakob Stoklund Olesen : > I don't think adding more TCRETURN instructions is the right solution. > > Instead, you should add a new kind of dynamic pointer register class to X86RegisterInfo::getPointerRegClass() and use that for the TCRETURN operand: > > def ptr_rc_tailcall : PointerLikeRegClass<2>; Thank you to point the way! I have wandered around codegen and I might get a way! Two of my last patches are withdrawn; - 0008-TableGen-EDEmitter.cpp-Add-TCW64.patch.txt - 0009-Target-X86-Tweak-win64-s-tailcall.patch.txt And I will show two new patches. (Other attached patches are regenerated. I saw merge in some point.) * 0008-TableGen-PointerLikeRegClass-can-be-accepted-to-.patch.txt For example, it was invalid on ToT; def TCRETURNri64 : PseudoI<(outs), (ins ptr_rc_tailcall:$dst, i32imm:$offset, variable_ops), []>; When I looked into CodeGen, I got confidence I might let it valid, and I did. * 0009-Target-X86-Tweak-win64-s-tailcall.patch.txt I got rid of instructions "TAIL****W64". I can specify input register class with ptr_rc_tailcall, but I wonder how to specify alternative Defs to instructions. Let me know if there were a way without "custom expand". I could not find tests for TCRETURNri64 (jmpq *GPR) and I added one. I have checked on all platforms I have. Please take a look, thank you. ...Takumi -------------- next part -------------- From e83dbf3cd2c9facb6838c2c18e92d869135a0246 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Thu, 9 Dec 2010 20:15:03 +0900 Subject: [PATCH 1/9] Target/X86: Fix whitespace. --- lib/Target/X86/X86FrameLowering.cpp | 2 +- lib/Target/X86/X86ISelLowering.cpp | 94 +++++++++++++++++----------------- lib/Target/X86/X86InstrCompiler.td | 17 +++--- lib/Target/X86/X86InstrControl.td | 39 +++++++------- lib/Target/X86/X86InstrInfo.cpp | 84 +++++++++++++++--------------- lib/Target/X86/X86InstrInfo.td | 3 +- lib/Target/X86/X86MCInstLower.cpp | 65 ++++++++++++------------ lib/Target/X86/X86RegisterInfo.cpp | 6 +- lib/Target/X86/X86RegisterInfo.td | 24 +++++----- 9 files changed, 165 insertions(+), 169 deletions(-) diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index 21ca3e7..5982520 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -321,7 +321,7 @@ void X86FrameLowering::emitCalleeSavedFrameMoves(MachineFunction &MF, // move" for this extra "PUSH", the linker will lose track of the fact that // the frame pointer should have the value of the first "PUSH" when it's // trying to unwind. - // + // // FIXME: This looks inelegant. It's possibly correct, but it's covering up // another bug. I.e., one where we generate a prolog like this: // diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 1a4bb97..2268823 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -69,7 +69,7 @@ static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { return new X8664_MachoTargetObjectFile(); return new TargetLoweringObjectFileMachO(); } - + if (TM.getSubtarget().isTargetELF() ){ if (is64Bit) return new X8664_ELFTargetObjectFile(TM); @@ -256,7 +256,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::UDIV, VT, Expand); setOperationAction(ISD::SREM, VT, Expand); setOperationAction(ISD::UREM, VT, Expand); - + // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. setOperationAction(ISD::ADDC, VT, Custom); setOperationAction(ISD::ADDE, VT, Custom); @@ -369,7 +369,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); } - + if (!Subtarget->is64Bit()) { setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); @@ -931,7 +931,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) // We want to custom lower some of our intrinsics. setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); - + // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't // handle type legalization for these operations here. // @@ -948,7 +948,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::SMULO, VT, Custom); setOperationAction(ISD::UMULO, VT, Custom); } - + // There are no 8-bit 3-address imul/mul instructions setOperationAction(ISD::SMULO, MVT::i8, Expand); setOperationAction(ISD::UMULO, MVT::i8, Expand); @@ -6198,7 +6198,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); MFI->setAdjustsStack(true); - + // And our return value (tls address) is in the standard call return value // location. unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; @@ -7047,7 +7047,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { (cast(Op1)->getZExtValue() == 1 || cast(Op1)->isNullValue()) && (CC == ISD::SETEQ || CC == ISD::SETNE)) { - + // If the input is a setcc, then reuse the input setcc or use a new one with // the inverted condition. if (Op0.getOpcode() == X86ISD::SETCC) { @@ -7055,7 +7055,7 @@ SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { bool Invert = (CC == ISD::SETNE) ^ cast(Op1)->isNullValue(); if (!Invert) return Op0; - + CCode = X86::GetOppositeBranchCondition(CCode); return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); @@ -7206,7 +7206,7 @@ static bool isX86LogicalCmp(SDValue Op) { if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) return true; - + return false; } @@ -7242,24 +7242,24 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { Cond.getOperand(1).getOpcode() == X86ISD::CMP && isZero(Cond.getOperand(1).getOperand(1))) { SDValue Cmp = Cond.getOperand(1); - + unsigned CondCode =cast(Cond.getOperand(0))->getZExtValue(); - - if ((isAllOnes(Op1) || isAllOnes(Op2)) && + + if ((isAllOnes(Op1) || isAllOnes(Op2)) && (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { SDValue Y = isAllOnes(Op2) ? Op1 : Op2; SDValue CmpOp0 = Cmp.getOperand(0); Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); - + SDValue Res = // Res = 0 or -1. DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), DAG.getConstant(X86::COND_B, MVT::i8), Cmp); - + if (isAllOnes(Op1) != (CondCode == X86::COND_E)) Res = DAG.getNOT(DL, Res, Res.getValueType()); - + ConstantSDNode *N2C = dyn_cast(Op2); if (N2C == 0 || !N2C->isNullValue()) Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); @@ -8443,7 +8443,7 @@ SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const { Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); // return pblendv(r, r+r, a); - R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, + R = DAG.getNode(X86ISD::PBLENDVB, dl, VT, R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op); return R; } @@ -8503,12 +8503,12 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), MVT::i32); SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); - + SDValue SetCC = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, DAG.getConstant(X86::COND_O, MVT::i32), SDValue(Sum.getNode(), 2)); - + DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), SetCC); return Sum; } @@ -8663,9 +8663,9 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { // Let legalize expand this if it isn't a legal type yet. if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) return SDValue(); - + SDVTList VTs = DAG.getVTList(VT, MVT::i32); - + unsigned Opc; bool ExtraOp = false; switch (Op.getOpcode()) { @@ -8675,7 +8675,7 @@ static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { case ISD::SUBC: Opc = X86ISD::SUB; break; case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; } - + if (!ExtraOp) return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), Op.getOperand(1)); @@ -9555,14 +9555,14 @@ MachineBasicBlock * X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { DebugLoc dl = MI->getDebugLoc(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - + // Address into RAX/EAX, other two args into ECX, EDX. unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); for (int i = 0; i < X86::AddrNumOperands; ++i) MIB.addOperand(MI->getOperand(i)); - + unsigned ValOps = X86::AddrNumOperands; BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) .addReg(MI->getOperand(ValOps).getReg()); @@ -9571,7 +9571,7 @@ X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { // The instruction doesn't actually take any operands though. BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); - + MI->eraseFromParent(); // The pseudo is gone now. return BB; } @@ -9580,16 +9580,16 @@ MachineBasicBlock * X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { DebugLoc dl = MI->getDebugLoc(); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - + // First arg in ECX, the second in EAX. BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) .addReg(MI->getOperand(0).getReg()); BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) .addReg(MI->getOperand(1).getReg()); - + // The instruction doesn't actually take any operands though. BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); - + MI->eraseFromParent(); // The pseudo is gone now. return BB; } @@ -10195,7 +10195,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, // Thread synchronization. case X86::MONITOR: - return EmitMonitor(MI, BB); + return EmitMonitor(MI, BB); case X86::MWAIT: return EmitMwait(MI, BB); @@ -11116,19 +11116,19 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) { if (DCI.isBeforeLegalizeOps()) return SDValue(); - + // Want to form PANDN nodes, in the hopes of then easily combining them with // OR and AND nodes to form PBLEND/PSIGN. EVT VT = N->getValueType(0); if (VT != MVT::v2i64) return SDValue(); - + SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); DebugLoc DL = N->getDebugLoc(); - + // Check LHS for vnot - if (N0.getOpcode() == ISD::XOR && + if (N0.getOpcode() == ISD::XOR && ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) return DAG.getNode(X86ISD::PANDN, DL, VT, N0.getOperand(0), N1); @@ -11136,7 +11136,7 @@ static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, if (N1.getOpcode() == ISD::XOR && ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) return DAG.getNode(X86ISD::PANDN, DL, VT, N1.getOperand(0), N0); - + return SDValue(); } @@ -11152,7 +11152,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); - + // look for psign/blend if (Subtarget->hasSSSE3()) { if (VT == MVT::v2i64) { @@ -11168,17 +11168,17 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, Y = N0.getOperand(1); if (N0.getOperand(1) == Mask) Y = N0.getOperand(0); - + // Check to see if the mask appeared in both the AND and PANDN and if (!Y.getNode()) return SDValue(); - + // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. if (Mask.getOpcode() != ISD::BITCAST || X.getOpcode() != ISD::BITCAST || Y.getOpcode() != ISD::BITCAST) return SDValue(); - + // Look through mask bitcast. Mask = Mask.getOperand(0); EVT MaskVT = Mask.getValueType(); @@ -11187,7 +11187,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, // will be an intrinsic. if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) return SDValue(); - + // FIXME: what to do for bytes, since there is a psignb/pblendvb, but // there is no psrai.b switch (cast(Mask.getOperand(0))->getZExtValue()) { @@ -11196,14 +11196,14 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, break; default: return SDValue(); } - + // Check that the SRA is all signbits. SDValue SraC = Mask.getOperand(2); unsigned SraAmt = cast(SraC)->getZExtValue(); unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); if ((SraAmt + 1) != EltBits) return SDValue(); - + DebugLoc DL = N->getDebugLoc(); // Now we know we at least have a plendvb with the mask val. See if @@ -11229,7 +11229,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, // PBLENDVB only available on SSE 4.1 if (!Subtarget->hasSSE41()) return SDValue(); - + X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X); Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y); Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask); @@ -11238,7 +11238,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, } } } - + // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) std::swap(N0, N1); @@ -11290,7 +11290,7 @@ static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ShAmt0)); } - + return SDValue(); } @@ -11500,7 +11500,7 @@ static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { unsigned X86CC = N->getConstantOperandVal(0); SDValue EFLAG = N->getOperand(1); DebugLoc DL = N->getDebugLoc(); - + // Materialize "setb reg" as "sbb reg,reg", since it can be extended without // a zext and produces an all-ones bit which is more useful than 0/1 in some // cases. @@ -11509,10 +11509,10 @@ static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, DAG.getConstant(X86CC, MVT::i8), EFLAG), DAG.getConstant(1, MVT::i8)); - + return SDValue(); } - + // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, X86TargetLowering::DAGCombinerInfo &DCI) { @@ -11544,7 +11544,7 @@ static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, // (sub (setne X, 0), Y) -> adc -1, Y static SDValue OptimizeConditonalInDecrement(SDNode *N, SelectionDAG &DAG) { DebugLoc DL = N->getDebugLoc(); - + // Look through ZExts. SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td index da5e05a..d2c5763 100644 --- a/lib/Target/X86/X86InstrCompiler.td +++ b/lib/Target/X86/X86InstrCompiler.td @@ -849,38 +849,38 @@ def : Pat<(X86call (i64 texternalsym:$dst)), // tailcall stuff def : Pat<(X86tcret GR32_TC:$dst, imm:$off), (TCRETURNri GR32_TC:$dst, imm:$off)>, - Requires<[In32BitMode]>; + Requires<[In32BitMode]>; // FIXME: This is disabled for 32-bit PIC mode because the global base // register which is part of the address mode may be assigned a // callee-saved register. def : Pat<(X86tcret (load addr:$dst), imm:$off), (TCRETURNmi addr:$dst, imm:$off)>, - Requires<[In32BitMode, IsNotPIC]>; + Requires<[In32BitMode, IsNotPIC]>; def : Pat<(X86tcret (i32 tglobaladdr:$dst), imm:$off), (TCRETURNdi texternalsym:$dst, imm:$off)>, - Requires<[In32BitMode]>; + Requires<[In32BitMode]>; def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), (TCRETURNdi texternalsym:$dst, imm:$off)>, - Requires<[In32BitMode]>; + Requires<[In32BitMode]>; def : Pat<(X86tcret GR64_TC:$dst, imm:$off), (TCRETURNri64 GR64_TC:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode]>; def : Pat<(X86tcret (load addr:$dst), imm:$off), (TCRETURNmi64 addr:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode]>; def : Pat<(X86tcret (i64 tglobaladdr:$dst), imm:$off), (TCRETURNdi64 tglobaladdr:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode]>; def : Pat<(X86tcret (i64 texternalsym:$dst), imm:$off), (TCRETURNdi64 texternalsym:$dst, imm:$off)>, - Requires<[In64BitMode]>; + Requires<[In64BitMode]>; // Normal calls, with various flavors of addresses. def : Pat<(X86call (i32 tglobaladdr:$dst)), @@ -1661,4 +1661,3 @@ def : Pat<(and GR64:$src1, i64immSExt8:$src2), (AND64ri8 GR64:$src1, i64immSExt8:$src2)>; def : Pat<(and GR64:$src1, i64immSExt32:$src2), (AND64ri32 GR64:$src1, i64immSExt32:$src2)>; - diff --git a/lib/Target/X86/X86InstrControl.td b/lib/Target/X86/X86InstrControl.td index 62ab53e..4d1c5f7 100644 --- a/lib/Target/X86/X86InstrControl.td +++ b/lib/Target/X86/X86InstrControl.td @@ -1,10 +1,10 @@ //===- X86InstrControl.td - Control Flow Instructions ------*- tablegen -*-===// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file describes the X86 jump, return, call, and related instructions. @@ -43,7 +43,7 @@ let isBarrier = 1, isBranch = 1, isTerminator = 1 in { "jmp\t$dst", [(br bb:$dst)]>; def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst), "jmp\t$dst", []>; - def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst), + def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst), "jmp{q}\t$dst", []>; } @@ -108,16 +108,16 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst", [(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>; - def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), + def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs), (ins i16imm:$off, i16imm:$seg), "ljmp{w}\t{$seg, $off|$off, $seg}", []>, OpSize; def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs), (ins i32imm:$off, i16imm:$seg), - "ljmp{l}\t{$seg, $off|$off, $seg}", []>; + "ljmp{l}\t{$seg, $off|$off, $seg}", []>; def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst), "ljmp{q}\t{*}$dst", []>; - def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), + def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst), "ljmp{w}\t{*}$dst", []>, OpSize; def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst), "ljmp{l}\t{*}$dst", []>; @@ -152,14 +152,14 @@ let isCall = 1 in def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst, variable_ops), "call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>, Requires<[In32BitMode]>; - - def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), + + def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs), (ins i16imm:$off, i16imm:$seg), "lcall{w}\t{$seg, $off|$off, $seg}", []>, OpSize; def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs), (ins i32imm:$off, i16imm:$seg), "lcall{l}\t{$seg, $off|$off, $seg}", []>; - + def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst), "lcall{w}\t{*}$dst", []>, OpSize; def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst), @@ -182,12 +182,12 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], Uses = [ESP] in { - def TCRETURNdi : PseudoI<(outs), + def TCRETURNdi : PseudoI<(outs), (ins i32imm_pcrel:$dst, i32imm:$offset, variable_ops), []>; - def TCRETURNri : PseudoI<(outs), + def TCRETURNri : PseudoI<(outs), (ins GR32_TC:$dst, i32imm:$offset, variable_ops), []>; let mayLoad = 1 in - def TCRETURNmi : PseudoI<(outs), + def TCRETURNmi : PseudoI<(outs), (ins i32mem_TC:$dst, i32imm:$offset, variable_ops), []>; // FIXME: The should be pseudo instructions that are lowered when going to @@ -196,7 +196,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, (ins i32imm_pcrel:$dst, variable_ops), "jmp\t$dst # TAILCALL", []>; - def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops), + def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32_TC:$dst, variable_ops), "", []>; // FIXME: Remove encoding when JIT is dead. let mayLoad = 1 in def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem_TC:$dst, variable_ops), @@ -218,7 +218,7 @@ let isCall = 1 in XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], Uses = [RSP] in { - + // NOTE: this pattern doesn't match "X86call imm", because we do not know // that the offset between an arbitrary immediate and the call will fit in // the 32-bit pcrel field that we have. @@ -232,12 +232,12 @@ let isCall = 1 in def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst, variable_ops), "call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>, Requires<[In64BitMode, NotWin64]>; - + def FARCALL64 : RI<0xFF, MRM3m, (outs), (ins opaque80mem:$dst), "lcall{q}\t{*}$dst", []>; } - // FIXME: We need to teach codegen about single list of call-clobbered + // FIXME: We need to teach codegen about single list of call-clobbered // registers. let isCall = 1, isCodeGenOnly = 1 in // All calls clobber the non-callee saved registers. RSP is marked as @@ -256,10 +256,10 @@ let isCall = 1, isCodeGenOnly = 1 in def WINCALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst, variable_ops), "call{q}\t{*}$dst", [(X86call GR64:$dst)]>, Requires<[IsWin64]>; - def WINCALL64m : I<0xFF, MRM2m, (outs), + def WINCALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst,variable_ops), "call{q}\t{*}$dst", - [(X86call (loadi64 addr:$dst))]>, + [(X86call (loadi64 addr:$dst))]>, Requires<[IsWin64]>; } @@ -278,7 +278,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, def TCRETURNri64 : PseudoI<(outs), (ins GR64_TC:$dst, i32imm:$offset, variable_ops), []>; let mayLoad = 1 in - def TCRETURNmi64 : PseudoI<(outs), + def TCRETURNmi64 : PseudoI<(outs), (ins i64mem_TC:$dst, i32imm:$offset, variable_ops), []>; def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), @@ -291,4 +291,3 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, def TAILJMPm64 : I<0xFF, MRM4m, (outs), (ins i64mem_TC:$dst, variable_ops), "jmp{q}\t{*}$dst # TAILCALL", []>; } - diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 73654d3..63dcd14 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -58,7 +58,7 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) TB_NOT_REVERSABLE = 1U << 31, TB_FLAGS = TB_NOT_REVERSABLE }; - + static const unsigned OpTbl2Addr[][2] = { { X86::ADC32ri, X86::ADC32mi }, { X86::ADC32ri8, X86::ADC32mi8 }, @@ -231,16 +231,16 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) unsigned MemOp = OpTbl2Addr[i][1] & ~TB_FLAGS; assert(!RegOp2MemOpTable2Addr.count(RegOp) && "Duplicated entries?"); RegOp2MemOpTable2Addr[RegOp] = std::make_pair(MemOp, 0U); - + // If this is not a reversable operation (because there is a many->one) // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. if (OpTbl2Addr[i][1] & TB_NOT_REVERSABLE) continue; - + // Index 0, folded load and store, no alignment requirement. unsigned AuxInfo = 0 | (1 << 4) | (1 << 5); - - assert(!MemOp2RegOpTable.count(MemOp) && + + assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries in unfolding maps?"); MemOp2RegOpTable[MemOp] = std::make_pair(RegOp, AuxInfo); } @@ -334,12 +334,12 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) unsigned Align = OpTbl0[i][3]; assert(!RegOp2MemOpTable0.count(RegOp) && "Duplicated entries?"); RegOp2MemOpTable0[RegOp] = std::make_pair(MemOp, Align); - + // If this is not a reversable operation (because there is a many->one) // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. if (OpTbl0[i][1] & TB_NOT_REVERSABLE) continue; - + // Index 0, folded load or store. unsigned AuxInfo = 0 | (FoldedLoad << 4) | ((FoldedLoad^1) << 5); assert(!MemOp2RegOpTable.count(MemOp) && "Duplicated entries?"); @@ -461,12 +461,12 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) unsigned Align = OpTbl1[i][2]; assert(!RegOp2MemOpTable1.count(RegOp) && "Duplicate entries"); RegOp2MemOpTable1[RegOp] = std::make_pair(MemOp, Align); - + // If this is not a reversable operation (because there is a many->one) // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. if (OpTbl1[i][1] & TB_NOT_REVERSABLE) continue; - + // Index 1, folded load unsigned AuxInfo = 1 | (1 << 4); assert(!MemOp2RegOpTable.count(MemOp) && "Duplicate entries"); @@ -678,15 +678,15 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) unsigned RegOp = OpTbl2[i][0]; unsigned MemOp = OpTbl2[i][1] & ~TB_FLAGS; unsigned Align = OpTbl2[i][2]; - + assert(!RegOp2MemOpTable2.count(RegOp) && "Duplicate entry!"); RegOp2MemOpTable2[RegOp] = std::make_pair(MemOp, Align); - + // If this is not a reversable operation (because there is a many->one) // mapping, don't insert the reverse of the operation into MemOp2RegOpTable. if (OpTbl2[i][1] & TB_NOT_REVERSABLE) continue; - + // Index 2, folded load unsigned AuxInfo = 2 | (1 << 4); assert(!MemOp2RegOpTable.count(MemOp) && @@ -808,7 +808,7 @@ static bool isFrameStoreOpcode(int Opcode) { return false; } -unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, +unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { if (isFrameLoadOpcode(MI->getOpcode())) if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex)) @@ -816,7 +816,7 @@ unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI, return 0; } -unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, +unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI, int &FrameIndex) const { if (isFrameLoadOpcode(MI->getOpcode())) { unsigned Reg; @@ -946,10 +946,10 @@ X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI, isPICBase = true; } return isPICBase; - } + } return false; } - + case X86::LEA32r: case X86::LEA64r: { if (MI->getOperand(2).isImm() && @@ -1124,9 +1124,9 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo(); unsigned leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass); - + // Build and insert into an implicit UNDEF value. This is OK because - // well be shifting and then extracting the lower 16-bits. + // well be shifting and then extracting the lower 16-bits. // This has the potential to cause partial register stall. e.g. // movw (%rbp,%rcx,2), %dx // leal -65(%rdx), %esi @@ -1162,7 +1162,7 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, case X86::ADD16ri8: case X86::ADD16ri_DB: case X86::ADD16ri8_DB: - addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); + addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm()); break; case X86::ADD16rr: case X86::ADD16rr_DB: { @@ -1177,7 +1177,7 @@ X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc, } else { leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass); // Build and insert into an implicit UNDEF value. This is OK because - // well be shifting and then extracting the lower 16-bits. + // well be shifting and then extracting the lower 16-bits. BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2); InsMI2 = BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY)) @@ -1244,7 +1244,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, case X86::SHUFPSrri: { assert(MI->getNumOperands() == 4 && "Unknown shufps instruction!"); if (!TM.getSubtarget().hasSSE2()) return 0; - + unsigned B = MI->getOperand(1).getReg(); unsigned C = MI->getOperand(2).getReg(); if (B != C) return 0; @@ -1392,7 +1392,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, RC = X86::GR32_NOSPRegisterClass; } - + unsigned Src2 = MI->getOperand(2).getReg(); bool isKill2 = MI->getOperand(2).isKill(); @@ -1471,7 +1471,7 @@ X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI, LV->replaceKillInstruction(Dest, MI, NewMI); } - MFI->insert(MBBI, NewMI); // Insert the new inst + MFI->insert(MBBI, NewMI); // Insert the new inst return NewMI; } @@ -1692,7 +1692,7 @@ X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { const TargetInstrDesc &TID = MI->getDesc(); if (!TID.isTerminator()) return false; - + // Conditional branch is a special case. if (TID.isBranch() && !TID.isBarrier()) return true; @@ -1701,7 +1701,7 @@ bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { return !isPredicated(MI); } -bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, @@ -1862,7 +1862,7 @@ unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const { I = MBB.end(); ++Count; } - + return Count; } @@ -2177,7 +2177,7 @@ static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode, MIB.addOperand(MOs[i]); if (NumAddrOps < 4) // FrameIndex only addOffset(MIB, 0); - + // Loop over the rest of the ri operands, converting them over. unsigned NumOps = MI->getDesc().getNumOperands()-2; for (unsigned i = 0; i != NumOps; ++i) { @@ -2198,7 +2198,7 @@ static MachineInstr *FuseInst(MachineFunction &MF, MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode), MI->getDebugLoc(), true); MachineInstrBuilder MIB(NewMI); - + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &MO = MI->getOperand(i); if (i == OpNo) { @@ -2247,7 +2247,7 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, if (isTwoAddr && NumOps >= 2 && i < 2 && MI->getOperand(0).isReg() && MI->getOperand(1).isReg() && - MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { + MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) { OpcodeTablePtr = &RegOp2MemOpTable2Addr; isTwoAddrFold = true; } else if (i == 0) { // If operand 0 @@ -2261,14 +2261,14 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, NewMI = MakeM0Inst(*this, X86::MOV8mi, MOs, MI); if (NewMI) return NewMI; - + OpcodeTablePtr = &RegOp2MemOpTable0; } else if (i == 1) { OpcodeTablePtr = &RegOp2MemOpTable1; } else if (i == 2) { OpcodeTablePtr = &RegOp2MemOpTable2; } - + // If table selected... if (OpcodeTablePtr) { // Find the Opcode to fuse @@ -2316,8 +2316,8 @@ X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, return NewMI; } } - - // No fusion + + // No fusion if (PrintFailedFusing && !MI->isCopy()) dbgs() << "We failed to fuse operand " << i << " in " << *MI; return NULL; @@ -2328,7 +2328,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl &Ops, int FrameIndex) const { - // Check switch flag + // Check switch flag if (NoFusing) return NULL; if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) @@ -2380,7 +2380,7 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI, const SmallVectorImpl &Ops, MachineInstr *LoadMI) const { - // Check switch flag + // Check switch flag if (NoFusing) return NULL; if (!MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize)) @@ -2523,13 +2523,13 @@ MachineInstr* X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, const SmallVectorImpl &Ops) const { - // Check switch flag + // Check switch flag if (NoFusing) return 0; if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) { switch (MI->getOpcode()) { default: return false; - case X86::TEST8rr: + case X86::TEST8rr: case X86::TEST16rr: case X86::TEST32rr: case X86::TEST64rr: @@ -2550,7 +2550,7 @@ bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, // instruction is different than folding it other places. It requires // replacing the *two* registers with the memory location. const DenseMap > *OpcodeTablePtr = 0; - if (isTwoAddr && NumOps >= 2 && OpNum < 2) { + if (isTwoAddr && NumOps >= 2 && OpNum < 2) { OpcodeTablePtr = &RegOp2MemOpTable2Addr; } else if (OpNum == 0) { // If operand 0 switch (Opc) { @@ -2566,7 +2566,7 @@ bool X86InstrInfo::canFoldMemoryOperand(const MachineInstr *MI, } else if (OpNum == 2) { OpcodeTablePtr = &RegOp2MemOpTable2; } - + if (OpcodeTablePtr && OpcodeTablePtr->count(Opc)) return true; return TargetInstrInfoImpl::canFoldMemoryOperand(MI, Ops); @@ -2636,7 +2636,7 @@ bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, // Emit the data processing instruction. MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true); MachineInstrBuilder MIB(DataMI); - + if (FoldedStore) MIB.addReg(Reg, RegState::Define); for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i) @@ -3156,11 +3156,11 @@ namespace { PC = RegInfo.createVirtualRegister(X86::GR32RegisterClass); else PC = GlobalBaseReg; - + // Operand of MovePCtoStack is completely ignored by asm printer. It's // only used in JIT code emission as displacement to pc. BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0); - + // If we're using vanilla 'GOT' PIC style, we should use relative addressing // not to pc, but to _GLOBAL_OFFSET_TABLE_ external. if (TM->getSubtarget().isPICStyleGOT()) { diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index f9c0a7b..4748f13 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -36,7 +36,7 @@ def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, SDTCisSameAs<0, 3>, SDTCisInt<0>, SDTCisVT<1, i32>]>; -// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS +// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, [SDTCisSameAs<0, 2>, SDTCisSameAs<0, 3>, @@ -1612,4 +1612,3 @@ def : InstAlias<"xchgb $mem, $val", (XCHG8rm GR8 :$val, i8mem :$mem)>; def : InstAlias<"xchgw $mem, $val", (XCHG16rm GR16:$val, i16mem:$mem)>; def : InstAlias<"xchgl $mem, $val", (XCHG32rm GR32:$val, i32mem:$mem)>; def : InstAlias<"xchgq $mem, $val", (XCHG64rm GR64:$val, i64mem:$mem)>; - diff --git a/lib/Target/X86/X86MCInstLower.cpp b/lib/Target/X86/X86MCInstLower.cpp index cbe6db2..4159af1 100644 --- a/lib/Target/X86/X86MCInstLower.cpp +++ b/lib/Target/X86/X86MCInstLower.cpp @@ -46,12 +46,12 @@ GetSymbolFromOperand(const MachineOperand &MO) const { assert((MO.isGlobal() || MO.isSymbol()) && "Isn't a symbol reference"); SmallString<128> Name; - + if (!MO.isGlobal()) { assert(MO.isSymbol()); Name += MAI.getGlobalPrefix(); Name += MO.getSymbolName(); - } else { + } else { const GlobalValue *GV = MO.getGlobal(); bool isImplicitlyPrivate = false; if (MO.getTargetFlags() == X86II::MO_DARWIN_STUB || @@ -59,7 +59,7 @@ GetSymbolFromOperand(const MachineOperand &MO) const { MO.getTargetFlags() == X86II::MO_DARWIN_NONLAZY_PIC_BASE || MO.getTargetFlags() == X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE) isImplicitlyPrivate = true; - + Mang->getNameWithPrefix(Name, GV, isImplicitlyPrivate); } @@ -110,7 +110,7 @@ GetSymbolFromOperand(const MachineOperand &MO) const { getMachOMMI().getFnStubEntry(Sym); if (StubSym.getPointer()) return Sym; - + if (MO.isGlobal()) { StubSym = MachineModuleInfoImpl:: @@ -135,7 +135,7 @@ MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, // lot of extra uniquing. const MCExpr *Expr = 0; MCSymbolRefExpr::VariantKind RefKind = MCSymbolRefExpr::VK_None; - + switch (MO.getTargetFlags()) { default: llvm_unreachable("Unknown target flag on GV operand"); case X86II::MO_NO_FLAG: // No flag. @@ -144,7 +144,7 @@ MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, case X86II::MO_DLLIMPORT: case X86II::MO_DARWIN_STUB: break; - + case X86II::MO_TLVP: RefKind = MCSymbolRefExpr::VK_TLVP; break; case X86II::MO_TLVP_PIC_BASE: Expr = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_TLVP, Ctx); @@ -168,7 +168,7 @@ MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, case X86II::MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE: Expr = MCSymbolRefExpr::Create(Sym, Ctx); // Subtract the pic base. - Expr = MCBinaryExpr::CreateSub(Expr, + Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(MF.getPICBaseSymbol(), Ctx), Ctx); if (MO.isJTI() && MAI.hasSetDirective()) { @@ -182,10 +182,10 @@ MCOperand X86MCInstLower::LowerSymbolOperand(const MachineOperand &MO, } break; } - + if (Expr == 0) Expr = MCSymbolRefExpr::Create(Sym, RefKind, Ctx); - + if (!MO.isJTI() && MO.getOffset()) Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(MO.getOffset(), Ctx), @@ -206,10 +206,10 @@ static void lower_lea64_32mem(MCInst *MI, unsigned OpNo) { // Convert registers in the addr mode according to subreg64. for (unsigned i = 0; i != 4; ++i) { if (!MI->getOperand(OpNo+i).isReg()) continue; - + unsigned Reg = MI->getOperand(OpNo+i).getReg(); if (Reg == 0) continue; - + MI->getOperand(OpNo+i).setReg(getX86SubSuperRegister(Reg, MVT::i64)); } } @@ -274,7 +274,7 @@ static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, return; // Check whether this is an absolute address. - // FIXME: We know TLVP symbol refs aren't, but there should be a better way + // FIXME: We know TLVP symbol refs aren't, but there should be a better way // to do this here. bool Absolute = true; if (Inst.getOperand(AddrOp).isExpr()) { @@ -283,7 +283,7 @@ static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, if (SRE->getKind() == MCSymbolRefExpr::VK_TLVP) Absolute = false; } - + if (Absolute && (Inst.getOperand(AddrBase + 0).getReg() != 0 || Inst.getOperand(AddrBase + 2).getReg() != 0 || @@ -300,10 +300,10 @@ static void SimplifyShortMoveForm(X86AsmPrinter &Printer, MCInst &Inst, void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { OutMI.setOpcode(MI->getOpcode()); - + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); - + MCOperand MCOp; switch (MO.getType()) { default: @@ -336,10 +336,10 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { AsmPrinter.GetBlockAddressSymbol(MO.getBlockAddress())); break; } - + OutMI.addOperand(MCOp); } - + // Handle a few special cases to eliminate operand modifiers. ReSimplify: switch (OutMI.getOpcode()) { @@ -429,7 +429,7 @@ ReSimplify: case X86::TAILJMPd: case X86::TAILJMPd64: Opcode = X86::JMP_1; break; } - + MCOperand Saved = OutMI.getOperand(0); OutMI = MCInst(); OutMI.setOpcode(Opcode); @@ -449,7 +449,7 @@ ReSimplify: case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; - + // The assembler backend wants to see branches in their small form and relax // them to their large form. The JIT can only handle the large form because // it does not do relaxation. For now, translate the large form to the @@ -605,7 +605,7 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { if (OutStreamer.hasRawTextSupport()) OutStreamer.EmitRawText(StringRef("\t#MEMBARRIER")); return; - + case X86::EH_RETURN: case X86::EH_RETURN64: { @@ -633,7 +633,7 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { // call "L1$pb" // "L1$pb": // popl %esi - + // Emit the call. MCSymbol *PICBase = MF->getPICBaseSymbol(); TmpInst.setOpcode(X86::CALLpcrel32); @@ -642,43 +642,43 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { TmpInst.addOperand(MCOperand::CreateExpr(MCSymbolRefExpr::Create(PICBase, OutContext))); OutStreamer.EmitInstruction(TmpInst); - + // Emit the label. OutStreamer.EmitLabel(PICBase); - + // popl $reg TmpInst.setOpcode(X86::POP32r); TmpInst.getOperand(0) = MCOperand::CreateReg(MI->getOperand(0).getReg()); OutStreamer.EmitInstruction(TmpInst); return; } - + case X86::ADD32ri: { // Lower the MO_GOT_ABSOLUTE_ADDRESS form of ADD32ri. if (MI->getOperand(2).getTargetFlags() != X86II::MO_GOT_ABSOLUTE_ADDRESS) break; - + // Okay, we have something like: // EAX = ADD32ri EAX, MO_GOT_ABSOLUTE_ADDRESS(@MYGLOBAL) - + // For this, we want to print something like: // MYGLOBAL + (. - PICBASE) // However, we can't generate a ".", so just emit a new label here and refer // to it. MCSymbol *DotSym = OutContext.CreateTempSymbol(); OutStreamer.EmitLabel(DotSym); - + // Now that we have emitted the label, lower the complex operand expression. MCSymbol *OpSym = MCInstLowering.GetSymbolFromOperand(MI->getOperand(2)); - + const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext); const MCExpr *PICBase = MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), OutContext); DotExpr = MCBinaryExpr::CreateSub(DotExpr, PICBase, OutContext); - - DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext), + + DotExpr = MCBinaryExpr::CreateAdd(MCSymbolRefExpr::Create(OpSym,OutContext), DotExpr, OutContext); - + MCInst TmpInst; TmpInst.setOpcode(X86::ADD32ri); TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg())); @@ -688,9 +688,8 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) { return; } } - + MCInst TmpInst; MCInstLowering.Lower(MI, TmpInst); OutStreamer.EmitInstruction(TmpInst); } - diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 1faf6d9..06c671b 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -445,11 +445,11 @@ bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const { if (0 && requiresRealignment && MFI->hasVarSizedObjects()) report_fatal_error( "Stack realignment in presense of dynamic allocas is not supported"); - + // If we've requested that we force align the stack do so now. if (ForceStackAlign) return canRealignStack(MF); - + return requiresRealignment && canRealignStack(MF); } @@ -524,7 +524,7 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, // Factor out the amount the callee already popped. Amount -= CalleeAmt; - + if (Amount) { unsigned Opc = getADDriOpcode(Is64Bit, Amount); New = BuildMI(MF, DL, TII.get(Opc), StackPtr) diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index dc4c042..45bb989 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -1,10 +1,10 @@ //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==// -// +// // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. -// +// //===----------------------------------------------------------------------===// // // This file describes the X86 Register file, defining the registers themselves, @@ -34,8 +34,8 @@ let Namespace = "X86" in { // because the register file generator is smart enough to figure out that // AL aliases AX if we tell it that AX aliased AL (for example). - // Dwarf numbering is different for 32-bit and 64-bit, and there are - // variations by target as well. Currently the first entry is for X86-64, + // Dwarf numbering is different for 32-bit and 64-bit, and there are + // variations by target as well. Currently the first entry is for X86-64, // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux // and debug information on X86-32/Darwin) @@ -81,7 +81,7 @@ let Namespace = "X86" in { def SP : RegisterWithSubRegs<"sp", [SPL]>, DwarfRegNum<[7, 5, 4]>; } def IP : Register<"ip">, DwarfRegNum<[16]>; - + // X86-64 only let SubRegIndices = [sub_8bit] in { def R8W : RegisterWithSubRegs<"r8w", [R8B]>, DwarfRegNum<[8, -2, -2]>; @@ -103,8 +103,8 @@ let Namespace = "X86" in { def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>; def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>; def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>; - def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>; - + def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>; + // X86-64 only def R8D : RegisterWithSubRegs<"r8d", [R8W]>, DwarfRegNum<[8, -2, -2]>; def R9D : RegisterWithSubRegs<"r9d", [R9W]>, DwarfRegNum<[9, -2, -2]>; @@ -208,7 +208,7 @@ let Namespace = "X86" in { def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>; def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>; def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>; - def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>; + def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>; // Status flags register def EFLAGS : Register<"flags">; @@ -220,7 +220,7 @@ let Namespace = "X86" in { def ES : Register<"es">; def FS : Register<"fs">; def GS : Register<"gs">; - + // Debug registers def DR0 : Register<"dr0">; def DR1 : Register<"dr1">; @@ -230,7 +230,7 @@ let Namespace = "X86" in { def DR5 : Register<"dr5">; def DR6 : Register<"dr6">; def DR7 : Register<"dr7">; - + // Control registers def CR0 : Register<"cr0">; def CR1 : Register<"cr1">; @@ -261,10 +261,10 @@ let Namespace = "X86" in { // implicitly defined to be the register allocation order. // -// List call-clobbered registers before callee-save registers. RBX, RBP, (and +// List call-clobbered registers before callee-save registers. RBX, RBP, (and // R12, R13, R14, and R15 for X86-64) are callee-save registers. // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and -// R8B, ... R15B. +// R8B, ... R15B. // Allocate R12 and R13 last, as these require an extra byte when // encoded in x86_64 instructions. // FIXME: Allow AH, CH, DH, BH to be used as general-purpose registers in -- 1.7.1.GIT -------------- next part -------------- From 97cd074a055b94930a9940fd68bb25ce2c477dbe Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Fri, 7 Jan 2011 10:58:30 +0900 Subject: [PATCH 2/9] test/CodeGen/X86: Fix whitespace. --- test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll | 5 ++--- test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll | 5 ++--- test/CodeGen/X86/tailcallstack64.ll | 1 - test/CodeGen/X86/win64_vararg.ll | 10 +++++----- 4 files changed, 9 insertions(+), 12 deletions(-) diff --git a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll index c598228..c5d3ac1 100644 --- a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll +++ b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll @@ -3,7 +3,6 @@ target triple = "x86_64-pc-mingw64" define x86_fp80 @a(i64 %x) nounwind readnone { entry: - %conv = sitofp i64 %x to x86_fp80 ; [#uses=1] - ret x86_fp80 %conv + %conv = sitofp i64 %x to x86_fp80 ; [#uses=1] + ret x86_fp80 %conv } - diff --git a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll index 810a6f4..b722589 100644 --- a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll +++ b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll @@ -6,7 +6,6 @@ target triple = "x86_64-pc-mingw64" define i32 @a() nounwind { entry: - tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind - ret i32 undef + tail call void asm sideeffect "", "~{xmm7},~{xmm8},~{dirflag},~{fpsr},~{flags}"() nounwind + ret i32 undef } - diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll index 107bdf9..52b074d 100644 --- a/test/CodeGen/X86/tailcallstack64.ll +++ b/test/CodeGen/X86/tailcallstack64.ll @@ -22,4 +22,3 @@ entry: %retval = tail call fastcc i32 @tailcallee(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6, i32 %in2,i32 %tmp) ret i32 %retval } - diff --git a/test/CodeGen/X86/win64_vararg.ll b/test/CodeGen/X86/win64_vararg.ll index 072f36a..71b2fa1 100644 --- a/test/CodeGen/X86/win64_vararg.ll +++ b/test/CodeGen/X86/win64_vararg.ll @@ -5,11 +5,11 @@ ; calculated. define void @average_va(i32 %count, ...) nounwind { entry: -; CHECK: subq $40, %rsp -; CHECK: movq %r9, 72(%rsp) -; CHECK: movq %r8, 64(%rsp) -; CHECK: movq %rdx, 56(%rsp) -; CHECK: leaq 56(%rsp), %rax +; CHECK: subq $40, %rsp +; CHECK: movq %r9, 72(%rsp) +; CHECK: movq %r8, 64(%rsp) +; CHECK: movq %rdx, 56(%rsp) +; CHECK: leaq 56(%rsp), %rax %ap = alloca i8*, align 8 ; [#uses=1] %ap1 = bitcast i8** %ap to i8* ; [#uses=1] -- 1.7.1.GIT -------------- next part -------------- From b258a23e020cebe5b4b77061d3f889ca3b0416bf Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Mon, 10 Jan 2011 13:19:04 +0900 Subject: [PATCH 3/9] lib/Target/X86/X86ISelLowering.cpp: Introduce a new variable "IsWin64". No functional changes. --- lib/Target/X86/X86ISelLowering.cpp | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 2268823..3f1bed1 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1863,6 +1863,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, SmallVectorImpl &InVals) const { MachineFunction &MF = DAG.getMachineFunction(); bool Is64Bit = Subtarget->is64Bit(); + bool IsWin64 = Subtarget->isTargetWin64(); bool IsStructRet = CallIsStructReturn(Outs); bool IsSibcall = false; @@ -1970,7 +1971,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, if (VA.isRegLoc()) { RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); - if (isVarArg && Subtarget->isTargetWin64()) { + if (isVarArg && IsWin64) { // Win64 ABI requires argument XMM reg to be copied to the corresponding // shadow reg if callee is a varargs function. unsigned ShadowReg = 0; @@ -2036,7 +2037,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, } } - if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) { + if (Is64Bit && isVarArg && !IsWin64) { // From AMD64 ABI document: // For calls that may call functions that use varargs or stdargs // (prototype-less calls or calls to functions containing ellipsis (...) in @@ -2211,7 +2212,7 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. - if (Is64Bit && isVarArg && !Subtarget->isTargetWin64()) + if (Is64Bit && isVarArg && !IsWin64) Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); if (InFlag.getNode()) -- 1.7.1.GIT -------------- next part -------------- From 107dacb4c6e87a8fe7d4352742d575702976530c Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Mon, 13 Dec 2010 17:59:20 +0900 Subject: [PATCH 4/9] Target/X86: Tweak allocating shadow area (aka home) on Win64. It must be enough for caller to allocate one. --- lib/Target/X86/X86FrameLowering.cpp | 5 ---- lib/Target/X86/X86FrameLowering.h | 3 +- lib/Target/X86/X86ISelLowering.cpp | 21 ++++++++++++++++++- test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll | 4 +- test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll | 9 +++---- test/CodeGen/X86/win64_params.ll | 4 +- test/CodeGen/X86/win64_vararg.ll | 10 ++++---- 7 files changed, 33 insertions(+), 23 deletions(-) diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index 5982520..5f04f8d 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -400,11 +400,6 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const { if (HasFP) MinSize += SlotSize; StackSize = std::max(MinSize, StackSize > 128 ? StackSize - 128 : 0); MFI->setStackSize(StackSize); - } else if (IsWin64) { - // We need to always allocate 32 bytes as register spill area. - // FIXME: We might reuse these 32 bytes for leaf functions. - StackSize += 32; - MFI->setStackSize(StackSize); } // Insert stack pointer adjustment for later moving of return addr. Only diff --git a/lib/Target/X86/X86FrameLowering.h b/lib/Target/X86/X86FrameLowering.h index c067e64..d71108c 100644 --- a/lib/Target/X86/X86FrameLowering.h +++ b/lib/Target/X86/X86FrameLowering.h @@ -28,8 +28,7 @@ public: explicit X86FrameLowering(const X86TargetMachine &tm, const X86Subtarget &sti) : TargetFrameLowering(StackGrowsDown, sti.getStackAlignment(), - (sti.isTargetWin64() ? -40 : - (sti.is64Bit() ? -8 : -4))), + (sti.is64Bit() ? -8 : -4)), TM(tm), STI(sti) { } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 3f1bed1..d3213de 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1569,6 +1569,12 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, SmallVector ArgLocs; CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); + + // Allocate shadow area for Win64 + if (IsWin64) { + CCInfo.AllocateStack(32, 8); + } + CCInfo.AnalyzeFormalArguments(Ins, CC_X86); unsigned LastVal = ~0U; @@ -1803,8 +1809,7 @@ X86TargetLowering::LowerMemOpCallTo(SDValue Chain, DebugLoc dl, SelectionDAG &DAG, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const { - const unsigned FirstStackArgOffset = (Subtarget->isTargetWin64() ? 32 : 0); - unsigned LocMemOffset = FirstStackArgOffset + VA.getLocMemOffset(); + unsigned LocMemOffset = VA.getLocMemOffset(); SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); if (Flags.isByVal()) @@ -1889,6 +1894,12 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, SmallVector ArgLocs; CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); + + // Allocate shadow area for Win64 + if (IsWin64) { + CCInfo.AllocateStack(32, 8); + } + CCInfo.AnalyzeCallOperands(Outs, CC_X86); // Get a count of how many bytes are to be pushed on the stack. @@ -2472,6 +2483,12 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, SmallVector ArgLocs; CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), ArgLocs, *DAG.getContext()); + + // Allocate shadow area for Win64 + if (Subtarget->isTargetWin64()) { + CCInfo.AllocateStack(32, 8); + } + CCInfo.AnalyzeCallOperands(Outs, CC_X86); if (CCInfo.getNextStackOffset()) { MachineFunction &MF = DAG.getMachineFunction(); diff --git a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll index c5d3ac1..9d06a9e 100644 --- a/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll +++ b/test/CodeGen/X86/2009-06-03-Win64DisableRedZone.ll @@ -1,5 +1,5 @@ -; RUN: llc < %s | grep "subq.*\\\$40, \\\%rsp" -target triple = "x86_64-pc-mingw64" +; RUN: llc -mtriple=x86_64-pc-mingw64 < %s | FileCheck %s +; CHECK-NOT: -{{[1-9][0-9]*}}(%rsp) define x86_fp80 @a(i64 %x) nounwind readnone { entry: diff --git a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll index b722589..6e8d9a9 100644 --- a/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll +++ b/test/CodeGen/X86/2009-06-03-Win64SpillXMM.ll @@ -1,8 +1,7 @@ -; RUN: llc < %s -o %t1 -; RUN: grep "subq.*\\\$72, \\\%rsp" %t1 -; RUN: grep "movaps \\\%xmm8, 32\\\(\\\%rsp\\\)" %t1 -; RUN: grep "movaps \\\%xmm7, 48\\\(\\\%rsp\\\)" %t1 -target triple = "x86_64-pc-mingw64" +; RUN: llc -mtriple=x86_64-pc-mingw64 < %s | FileCheck %s +; CHECK: subq $40, %rsp +; CHECK: movaps %xmm8, (%rsp) +; CHECK: movaps %xmm7, 16(%rsp) define i32 @a() nounwind { entry: diff --git a/test/CodeGen/X86/win64_params.ll b/test/CodeGen/X86/win64_params.ll index 0b67368..f9d4bf9 100644 --- a/test/CodeGen/X86/win64_params.ll +++ b/test/CodeGen/X86/win64_params.ll @@ -4,8 +4,8 @@ ; on the stack. define i32 @f6(i32 %p1, i32 %p2, i32 %p3, i32 %p4, i32 %p5, i32 %p6) nounwind readnone optsize { entry: -; CHECK: movl 80(%rsp), %eax -; CHECK: addl 72(%rsp), %eax +; CHECK: movl 48(%rsp), %eax +; CHECK: addl 40(%rsp), %eax %add = add nsw i32 %p6, %p5 ret i32 %add } diff --git a/test/CodeGen/X86/win64_vararg.ll b/test/CodeGen/X86/win64_vararg.ll index 71b2fa1..a451318 100644 --- a/test/CodeGen/X86/win64_vararg.ll +++ b/test/CodeGen/X86/win64_vararg.ll @@ -5,11 +5,11 @@ ; calculated. define void @average_va(i32 %count, ...) nounwind { entry: -; CHECK: subq $40, %rsp -; CHECK: movq %r9, 72(%rsp) -; CHECK: movq %r8, 64(%rsp) -; CHECK: movq %rdx, 56(%rsp) -; CHECK: leaq 56(%rsp), %rax +; CHECK: pushq +; CHECK: movq %r9, 40(%rsp) +; CHECK: movq %r8, 32(%rsp) +; CHECK: movq %rdx, 24(%rsp) +; CHECK: leaq 24(%rsp), %rax %ap = alloca i8*, align 8 ; [#uses=1] %ap1 = bitcast i8** %ap to i8* ; [#uses=1] -- 1.7.1.GIT -------------- next part -------------- From 20a4544adf5d73ae80e44c98eb692819a60c9bcc Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Mon, 13 Dec 2010 18:11:31 +0900 Subject: [PATCH 5/9] Target/X86: Tweak alloca and add a testcase for mingw64 and msvcrt on Win64. [PR8778] --- lib/Target/X86/X86FrameLowering.cpp | 19 +++++++-- lib/Target/X86/X86ISelLowering.cpp | 57 +++++++++++++++++++-------- lib/Target/X86/X86InstrControl.td | 10 +++++ test/CodeGen/X86/win64_alloca_dynalloca.ll | 56 +++++++++++++++++++++++++++ test/CodeGen/X86/win_chkstk.ll | 2 +- 5 files changed, 121 insertions(+), 23 deletions(-) create mode 100644 test/CodeGen/X86/win64_alloca_dynalloca.ll diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index 5f04f8d..f316727 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -555,14 +555,23 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const { // responsible for adjusting the stack pointer. Touching the stack at 4K // increments is necessary to ensure that the guard pages used by the OS // virtual memory manager are allocated in correct sequence. - if (NumBytes >= 4096 && (STI.isTargetCygMing() || STI.isTargetWin32())) { + if (NumBytes >= 4096 && Is64Bit && STI.isTargetCygMing()) { + // Sanity check that EAX is not livein for this function. It should + // should not be, so throw an assert. + assert(!isEAXLiveIn(MF) && "EAX is livein in the Cygming64 case!"); + + BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) + .addImm(NumBytes); + BuildMI(MBB, MBBI, DL, TII.get(X86::W64ALLOCA)) + .addExternalSymbol("___chkstk") + .addReg(StackPtr, RegState::Define | RegState::Implicit); + // Cygming's ___chkstk adjusts %rsp. + } else if (NumBytes >= 4096 && (STI.isTargetCygMing() || STI.isTargetWin32())) { // Check whether EAX is livein for this function. bool isEAXAlive = isEAXLiveIn(MF); const char *StackProbeSymbol = STI.isTargetWindows() ? "_chkstk" : "_alloca"; - if (Is64Bit && STI.isTargetCygMing()) - StackProbeSymbol = "__chkstk"; unsigned CallOp = Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32; if (!isEAXAlive) { BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) @@ -598,9 +607,9 @@ void X86FrameLowering::emitPrologue(MachineFunction &MF) const { // Handle the 64-bit Windows ABI case where we need to call __chkstk. // Function prologue is responsible for adjusting the stack pointer. - BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) + BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX) .addImm(NumBytes); - BuildMI(MBB, MBBI, DL, TII.get(X86::WINCALL64pcrel32)) + BuildMI(MBB, MBBI, DL, TII.get(X86::W64ALLOCA)) .addExternalSymbol("__chkstk") .addReg(StackPtr, RegState::Define | RegState::Implicit); emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index d3213de..a012ae2 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -418,12 +418,9 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); - if (Subtarget->is64Bit()) - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); - if (Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); - else - setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand); + setOperationAction(ISD::DYNAMIC_STACKALLOC, + (Subtarget->is64Bit() ? MVT::i64 : MVT::i32), + (Subtarget->isTargetCOFF() ? Custom : Expand)); if (!UseSoftFloat && X86ScalarSSEf64) { // f32 and f64 use SSE. @@ -7553,8 +7550,9 @@ X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SDValue Flag; EVT SPTy = Subtarget->is64Bit() ? MVT::i64 : MVT::i32; + unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); - Chain = DAG.getCopyToReg(Chain, dl, X86::EAX, Size, Flag); + Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); Flag = Chain.getValue(1); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); @@ -10022,19 +10020,44 @@ X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, // The lowering is pretty easy: we're just emitting the call to _alloca. The // non-trivial part is impdef of ESP. - // FIXME: The code should be tweaked as soon as we'll try to do codegen for - // mingw-w64. - const char *StackProbeSymbol = + if (Subtarget->isTargetWin64()) { + if (Subtarget->isTargetCygMing()) { + // ___chkstk(Mingw64): + // Clobbers R10, R11, RAX and EFLAGS. + // Updates RSP. + BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) + .addExternalSymbol("___chkstk") + .addReg(X86::RAX, RegState::Implicit) + .addReg(X86::RSP, RegState::Implicit) + .addReg(X86::RAX, RegState::Define | RegState::Implicit) + .addReg(X86::RSP, RegState::Define | RegState::Implicit) + .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); + } else { + // __chkstk(MSVCRT): does not update stack pointer. + // Clobbers R10, R11 and EFLAGS. + // FIXME: RAX(allocated size) might be reused and not killed. + BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) + .addExternalSymbol("__chkstk") + .addReg(X86::RAX, RegState::Implicit) + .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); + // RAX has the offset to subtracted from RSP. + BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) + .addReg(X86::RSP) + .addReg(X86::RAX); + } + } else { + const char *StackProbeSymbol = Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; - BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) - .addExternalSymbol(StackProbeSymbol) - .addReg(X86::EAX, RegState::Implicit) - .addReg(X86::ESP, RegState::Implicit) - .addReg(X86::EAX, RegState::Define | RegState::Implicit) - .addReg(X86::ESP, RegState::Define | RegState::Implicit) - .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); + BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) + .addExternalSymbol(StackProbeSymbol) + .addReg(X86::EAX, RegState::Implicit) + .addReg(X86::ESP, RegState::Implicit) + .addReg(X86::EAX, RegState::Define | RegState::Implicit) + .addReg(X86::ESP, RegState::Define | RegState::Implicit) + .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); + } MI->eraseFromParent(); // The pseudo instruction is gone now. return BB; diff --git a/lib/Target/X86/X86InstrControl.td b/lib/Target/X86/X86InstrControl.td index 4d1c5f7..31f2832 100644 --- a/lib/Target/X86/X86InstrControl.td +++ b/lib/Target/X86/X86InstrControl.td @@ -263,6 +263,16 @@ let isCall = 1, isCodeGenOnly = 1 in Requires<[IsWin64]>; } +let isCall = 1, isCodeGenOnly = 1 in + // __chkstk(MSVC): clobber R10, R11 and EFLAGS. + // ___chkstk(Mingw64): clobber R10, R11, RAX and EFLAGS, and update RSP. + let Defs = [RAX, R10, R11, RSP, EFLAGS], + Uses = [RSP] in { + def W64ALLOCA : Ii32PCRel<0xE8, RawFrm, + (outs), (ins i64i32imm_pcrel:$dst, variable_ops), + "call{q}\t$dst", []>, + Requires<[IsWin64]>; + } let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, isCodeGenOnly = 1 in diff --git a/test/CodeGen/X86/win64_alloca_dynalloca.ll b/test/CodeGen/X86/win64_alloca_dynalloca.ll new file mode 100644 index 0000000..bb43608 --- /dev/null +++ b/test/CodeGen/X86/win64_alloca_dynalloca.ll @@ -0,0 +1,56 @@ +; RUN: llc < %s -mtriple=x86_64-mingw32 | FileCheck %s -check-prefix=M64 +; RUN: llc < %s -mtriple=x86_64-mingw64 | FileCheck %s -check-prefix=M64 +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=W64 +; PR8777 +; PR8778 + +define i64 @foo(i64 %n, i64 %x) nounwind { +entry: + + %buf0 = alloca i8, i64 4096, align 1 + +; M64: movq %rsp, %rbp +; M64: $4096, %rax +; M64: callq ___chkstk +; M64-NOT: %rsp + +; W64: movq %rsp, %rbp +; W64: $4096, %rax +; W64: callq __chkstk +; W64: subq $4096, %rsp + + %buf1 = alloca i8, i64 %n, align 1 + +; M64: leaq 15(%rcx), %rax +; M64: andq $-16, %rax +; M64: callq ___chkstk +; M64-NOT: %rsp +; M64: movq %rsp, %rax + +; W64: leaq 15(%rcx), %rax +; W64: andq $-16, %rax +; W64: callq __chkstk +; W64: subq %rax, %rsp +; W64: movq %rsp, %rax + + %r = call i64 @bar(i64 %n, i64 %x, i64 %n, i8* %buf0, i8* %buf1) nounwind + +; M64: subq $48, %rsp +; M64: movq %rax, 32(%rsp) +; M64: leaq -4096(%rbp), %r9 +; M64: callq bar + +; W64: subq $48, %rsp +; W64: movq %rax, 32(%rsp) +; W64: leaq -4096(%rbp), %r9 +; W64: callq bar + + ret i64 %r + +; M64: movq %rbp, %rsp + +; W64: movq %rbp, %rsp + +} + +declare i64 @bar(i64, i64, i64, i8* nocapture, i8* nocapture) nounwind diff --git a/test/CodeGen/X86/win_chkstk.ll b/test/CodeGen/X86/win_chkstk.ll index 82ce81d..ae7591d 100644 --- a/test/CodeGen/X86/win_chkstk.ll +++ b/test/CodeGen/X86/win_chkstk.ll @@ -16,7 +16,7 @@ entry: ; WIN_X32: calll __chkstk ; WIN_X64: callq __chkstk ; MINGW_X32: calll __alloca -; MINGW_X64: callq __chkstk +; MINGW_X64: callq ___chkstk ; LINUX-NOT: call __chkstk %array4096 = alloca [4096 x i8], align 16 ; <[4096 x i8]*> [#uses=0] ret i32 0 -- 1.7.1.GIT -------------- next part -------------- From 93116cbbd8f258bada8636c52ea6f4b82aaef82b Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Wed, 15 Dec 2010 13:07:12 +0900 Subject: [PATCH 6/9] Target/X86: Tweak va_arg for Win64 not to miss taking va_start when number of fixed args > 4. --- lib/Target/X86/X86ISelLowering.cpp | 8 +++++--- test/CodeGen/X86/win64_vararg.ll | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+), 3 deletions(-) diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index a012ae2..588c3bb 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1662,8 +1662,8 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, // If the function takes variable number of arguments, make a frame index for // the start of the first vararg value... for expansion of llvm.va_start. if (isVarArg) { - if (!IsWin64 && (Is64Bit || (CallConv != CallingConv::X86_FastCall && - CallConv != CallingConv::X86_ThisCall))) { + if (Is64Bit || (CallConv != CallingConv::X86_FastCall && + CallConv != CallingConv::X86_ThisCall)) { FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); } if (Is64Bit) { @@ -1715,7 +1715,9 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain, int HomeOffset = TFI.getOffsetOfLocalArea() + 8; FuncInfo->setRegSaveFrameIndex( MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); - FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); + // FIXME: It is dirty hack but works. + if (NumIntRegs < 4) + FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); } else { // For X86-64, if there are vararg parameters that are passed via // registers, then we must store them to their spots on the stack so they diff --git a/test/CodeGen/X86/win64_vararg.ll b/test/CodeGen/X86/win64_vararg.ll index a451318..efe8bca 100644 --- a/test/CodeGen/X86/win64_vararg.ll +++ b/test/CodeGen/X86/win64_vararg.ll @@ -18,3 +18,36 @@ entry: } declare void @llvm.va_start(i8*) nounwind + +; CHECK: f5: +; CHECK: pushq +; CHECK: leaq 56(%rsp), +define i8* @f5(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, ...) nounwind { +entry: + %ap = alloca i8*, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + ret i8* %ap1 +} + +; CHECK: f4: +; CHECK: pushq +; CHECK: leaq 48(%rsp), +define i8* @f4(i64 %a0, i64 %a1, i64 %a2, i64 %a3, ...) nounwind { +entry: + %ap = alloca i8*, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + ret i8* %ap1 +} + +; CHECK: f3: +; CHECK: pushq +; CHECK: leaq 40(%rsp), +define i8* @f3(i64 %a0, i64 %a1, i64 %a2, ...) nounwind { +entry: + %ap = alloca i8*, align 8 + %ap1 = bitcast i8** %ap to i8* + call void @llvm.va_start(i8* %ap1) + ret i8* %ap1 +} -- 1.7.1.GIT -------------- next part -------------- From c9cff6d17df9a0df2ea66f6f30f88f61c27bcd3b Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Tue, 28 Dec 2010 19:05:25 +0900 Subject: [PATCH 7/9] X86FrameInfo.cpp, X86RegisterInfo.cpp: Re-indent. No functional changes. --- lib/Target/X86/X86FrameLowering.cpp | 35 ++++++++++++++++++++--------------- lib/Target/X86/X86RegisterInfo.cpp | 3 ++- 2 files changed, 22 insertions(+), 16 deletions(-) diff --git a/lib/Target/X86/X86FrameLowering.cpp b/lib/Target/X86/X86FrameLowering.cpp index f316727..a9fc4fa 100644 --- a/lib/Target/X86/X86FrameLowering.cpp +++ b/lib/Target/X86/X86FrameLowering.cpp @@ -760,6 +760,12 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, } // We're returning from function via eh_return. + bool isRel = (RetOpcode == X86::TCRETURNdi || + RetOpcode == X86::TCRETURNdi64); + bool isMem = (RetOpcode == X86::TCRETURNmi || + RetOpcode == X86::TCRETURNmi64); + bool isReg = (RetOpcode == X86::TCRETURNri || + RetOpcode == X86::TCRETURNri64); if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) { MBBI = MBB.getLastNonDebugInstr(); MachineOperand &DestAddr = MBBI->getOperand(0); @@ -767,11 +773,7 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), StackPtr).addReg(DestAddr.getReg()); - } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi || - RetOpcode == X86::TCRETURNmi || - RetOpcode == X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64 || - RetOpcode == X86::TCRETURNmi64) { - bool isMem = RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64; + } else if (isReg || isRel || isMem) { // Tail call return: adjust the stack pointer and jump to callee. MBBI = MBB.getLastNonDebugInstr(); MachineOperand &JumpTarget = MBBI->getOperand(0); @@ -795,10 +797,11 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, } // Jump to label or value in register. - if (RetOpcode == X86::TCRETURNdi || RetOpcode == X86::TCRETURNdi64) { + if (isRel) { MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNdi) - ? X86::TAILJMPd : X86::TAILJMPd64)); + BuildMI(MBB, MBBI, DL, + TII.get(RetOpcode == X86::TCRETURNdi ? X86::TAILJMPd + : X86::TAILJMPd64)); if (JumpTarget.isGlobal()) MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(), JumpTarget.getTargetFlags()); @@ -807,18 +810,20 @@ void X86FrameLowering::emitEpilogue(MachineFunction &MF, MIB.addExternalSymbol(JumpTarget.getSymbolName(), JumpTarget.getTargetFlags()); } - } else if (RetOpcode == X86::TCRETURNmi || RetOpcode == X86::TCRETURNmi64) { + } else if (isMem) { MachineInstrBuilder MIB = - BuildMI(MBB, MBBI, DL, TII.get((RetOpcode == X86::TCRETURNmi) - ? X86::TAILJMPm : X86::TAILJMPm64)); + BuildMI(MBB, MBBI, DL, + TII.get(RetOpcode == X86::TCRETURNmi ? X86::TAILJMPm + : X86::TAILJMPm64)); for (unsigned i = 0; i != 5; ++i) MIB.addOperand(MBBI->getOperand(i)); - } else if (RetOpcode == X86::TCRETURNri64) { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64)). + } else if (isReg) { + BuildMI(MBB, MBBI, DL, + TII.get(RetOpcode == X86::TCRETURNri64 ? X86::TAILJMPr64 + : X86::TAILJMPr)). addReg(JumpTarget.getReg(), RegState::Kill); } else { - BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr)). - addReg(JumpTarget.getReg(), RegState::Kill); + llvm_unreachable("What could I select for TCRETURN?"); } MachineInstr *NewMI = prior(MBBI); diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 06c671b..9260f1d 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -576,7 +576,8 @@ X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned BasePtr; unsigned Opc = MI.getOpcode(); - bool AfterFPPop = Opc == X86::TAILJMPm64 || Opc == X86::TAILJMPm; + bool AfterFPPop = (Opc == X86::TAILJMPm64 || + Opc == X86::TAILJMPm); if (needsStackRealignment(MF)) BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); else if (AfterFPPop) -- 1.7.1.GIT -------------- next part -------------- From 16a88d8c6658347177da15123cb678df371e874f Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Thu, 6 Jan 2011 09:09:52 +0900 Subject: [PATCH 8/9] TableGen: PointerLikeRegClass can be accepted to operand. --- utils/TableGen/CodeGenInstruction.cpp | 3 ++- utils/TableGen/EDEmitter.cpp | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/utils/TableGen/CodeGenInstruction.cpp b/utils/TableGen/CodeGenInstruction.cpp index a28b1d5..241cee2 100644 --- a/utils/TableGen/CodeGenInstruction.cpp +++ b/utils/TableGen/CodeGenInstruction.cpp @@ -94,7 +94,8 @@ CGIOperandList::CGIOperandList(Record *R) : TheDef(R) { isVariadic = true; continue; } else if (!Rec->isSubClassOf("RegisterClass") && - Rec->getName() != "ptr_rc" && Rec->getName() != "unknown") + !Rec->isSubClassOf("PointerLikeRegClass") && + Rec->getName() != "unknown") throw "Unknown operand class '" + Rec->getName() + "' in '" + R->getName() + "' instruction!"; diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp index c439143..8e59157 100644 --- a/utils/TableGen/EDEmitter.cpp +++ b/utils/TableGen/EDEmitter.cpp @@ -354,7 +354,8 @@ static void X86PopulateOperands( const CGIOperandList::OperandInfo &operandInfo = inst.Operands[index]; Record &rec = *operandInfo.Rec; - if (X86TypeFromOpName(operandTypes[index], rec.getName())) { + if (X86TypeFromOpName(operandTypes[index], rec.getName()) && + !rec.isSubClassOf("PointerLikeRegClass")) { errs() << "Operand type: " << rec.getName().c_str() << "\n"; errs() << "Operand name: " << operandInfo.Name.c_str() << "\n"; errs() << "Instruction name: " << inst.TheDef->getName().c_str() << "\n"; -- 1.7.1.GIT -------------- next part -------------- From 73291fb5d48647b8235c1c4c31514d26bdeae244 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Wed, 12 Jan 2011 15:55:03 +0900 Subject: [PATCH 9/9] Target/X86: Tweak win64's tailcall. --- lib/Target/X86/X86ISelLowering.cpp | 27 ++++++++++++++++++++++++--- lib/Target/X86/X86InstrCompiler.td | 4 ++-- lib/Target/X86/X86InstrControl.td | 13 +++++++------ lib/Target/X86/X86InstrInfo.cpp | 1 + lib/Target/X86/X86InstrInfo.td | 7 ++++++- lib/Target/X86/X86RegisterInfo.cpp | 6 ++++++ lib/Target/X86/X86RegisterInfo.td | 3 +++ test/CodeGen/X86/tailcall-ri64.ll | 24 ++++++++++++++++++++++++ test/CodeGen/X86/tailcallstack64.ll | 16 ++++++++++------ 9 files changed, 83 insertions(+), 18 deletions(-) create mode 100644 test/CodeGen/X86/tailcall-ri64.ll diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 588c3bb..775a5f6 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -2493,9 +2493,6 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, MachineFunction &MF = DAG.getMachineFunction(); if (MF.getInfo()->getBytesToPopOnReturn()) return false; - if (Subtarget->isTargetWin64()) - // Win64 ABI has additional complications. - return false; // Check if the arguments are already laid out in the right way as // the caller's fixed stack objects. @@ -10121,6 +10118,30 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); + case X86::TAILJMPd64: + case X86::TAILJMPr64: + case X86::TAILJMPm64: + assert(!"TAILJMP64 would not be touched here."); + case X86::TCRETURNdi64: + case X86::TCRETURNri64: + case X86::TCRETURNmi64: + // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. + // On AMD64, additional defs should be added before register allocation. + if (!Subtarget->isTargetWin64()) { + MI->addRegisterDefined(X86::RSI); + MI->addRegisterDefined(X86::RDI); + MI->addRegisterDefined(X86::XMM6); + MI->addRegisterDefined(X86::XMM7); + MI->addRegisterDefined(X86::XMM8); + MI->addRegisterDefined(X86::XMM9); + MI->addRegisterDefined(X86::XMM10); + MI->addRegisterDefined(X86::XMM11); + MI->addRegisterDefined(X86::XMM12); + MI->addRegisterDefined(X86::XMM13); + MI->addRegisterDefined(X86::XMM14); + MI->addRegisterDefined(X86::XMM15); + } + return BB; case X86::WIN_ALLOCA: return EmitLoweredWinAlloca(MI, BB); case X86::TLSCall_32: diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td index d2c5763..65cbcc7 100644 --- a/lib/Target/X86/X86InstrCompiler.td +++ b/lib/Target/X86/X86InstrCompiler.td @@ -866,8 +866,8 @@ def : Pat<(X86tcret (i32 texternalsym:$dst), imm:$off), (TCRETURNdi texternalsym:$dst, imm:$off)>, Requires<[In32BitMode]>; -def : Pat<(X86tcret GR64_TC:$dst, imm:$off), - (TCRETURNri64 GR64_TC:$dst, imm:$off)>, +def : Pat<(X86tcret ptr_rc_tailcall:$dst, imm:$off), + (TCRETURNri64 ptr_rc_tailcall:$dst, imm:$off)>, Requires<[In64BitMode]>; def : Pat<(X86tcret (load addr:$dst), imm:$off), diff --git a/lib/Target/X86/X86InstrControl.td b/lib/Target/X86/X86InstrControl.td index 31f2832..c228a0a 100644 --- a/lib/Target/X86/X86InstrControl.td +++ b/lib/Target/X86/X86InstrControl.td @@ -276,17 +276,18 @@ let isCall = 1, isCodeGenOnly = 1 in let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, isCodeGenOnly = 1 in - let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, + // AMD64 cc clobbers RSI, RDI, XMM6-XMM15. + let Defs = [RAX, RCX, RDX, R8, R9, R10, R11, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, ST1, MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7, - XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7, - XMM8, XMM9, XMM10, XMM11, XMM12, XMM13, XMM14, XMM15, EFLAGS], - Uses = [RSP] in { + XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, EFLAGS], + Uses = [RSP], + usesCustomInserter = 1 in { def TCRETURNdi64 : PseudoI<(outs), (ins i64i32imm_pcrel:$dst, i32imm:$offset, variable_ops), []>; def TCRETURNri64 : PseudoI<(outs), - (ins GR64_TC:$dst, i32imm:$offset, variable_ops), []>; + (ins ptr_rc_tailcall:$dst, i32imm:$offset, variable_ops), []>; let mayLoad = 1 in def TCRETURNmi64 : PseudoI<(outs), (ins i64mem_TC:$dst, i32imm:$offset, variable_ops), []>; @@ -294,7 +295,7 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, def TAILJMPd64 : Ii32PCRel<0xE9, RawFrm, (outs), (ins i64i32imm_pcrel:$dst, variable_ops), "jmp\t$dst # TAILCALL", []>; - def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins GR64_TC:$dst, variable_ops), + def TAILJMPr64 : I<0xFF, MRM4r, (outs), (ins ptr_rc_tailcall:$dst, variable_ops), "jmp{q}\t{*}$dst # TAILCALL", []>; let mayLoad = 1 in diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 63dcd14..ceb1b65 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -2025,6 +2025,7 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg, case X86::GR64_NOREX_NOSPRegClassID: case X86::GR64_NOSPRegClassID: case X86::GR64_TCRegClassID: + case X86::GR64_TCW64RegClassID: return load ? X86::MOV64rm : X86::MOV64mr; case X86::GR32RegClassID: case X86::GR32_ABCDRegClassID: diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 4748f13..14c9066 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -273,6 +273,10 @@ def i8mem_NOREX : Operand { let ParserMatchClass = X86MemAsmOperand; } +// GPRs available for tailcall. +// It represents GR64_TC or GR64_TCW64. +def ptr_rc_tailcall : PointerLikeRegClass<2>; + // Special i32mem for addresses of load folding tail calls. These are not // allowed to use callee-saved registers since they must be scheduled // after callee-saved register are popped. @@ -287,7 +291,8 @@ def i32mem_TC : Operand { // after callee-saved register are popped. def i64mem_TC : Operand { let PrintMethod = "printi64mem"; - let MIOperandInfo = (ops GR64_TC, i8imm, GR64_TC, i32imm, i8imm); + let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, + ptr_rc_tailcall, i32imm, i8imm); let ParserMatchClass = X86MemAsmOperand; } diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 9260f1d..67e60fe 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -320,6 +320,12 @@ X86RegisterInfo::getPointerRegClass(unsigned Kind) const { if (TM.getSubtarget().is64Bit()) return &X86::GR64_NOSPRegClass; return &X86::GR32_NOSPRegClass; + case 2: // Available for tailcall (not callee-saved GPRs). + if (TM.getSubtarget().isTargetWin64()) + return &X86::GR64_TCW64RegClass; + if (TM.getSubtarget().is64Bit()) + return &X86::GR64_TCRegClass; + return &X86::GR32_TCRegClass; } } diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td index 45bb989..612fac2 100644 --- a/lib/Target/X86/X86RegisterInfo.td +++ b/lib/Target/X86/X86RegisterInfo.td @@ -496,6 +496,9 @@ def GR64_TC : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RSI, RDI, (GR32_TC sub_32bit)]; } +def GR64_TCW64 : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, + R8, R9, R11]>; + // GR8_NOREX - GR8 registers which do not require a REX prefix. def GR8_NOREX : RegisterClass<"X86", [i8], 8, [AL, CL, DL, AH, CH, DH, BL, BH]> { diff --git a/test/CodeGen/X86/tailcall-ri64.ll b/test/CodeGen/X86/tailcall-ri64.ll new file mode 100644 index 0000000..914d8f7 --- /dev/null +++ b/test/CodeGen/X86/tailcall-ri64.ll @@ -0,0 +1,24 @@ +; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s -check-prefix=AMD64 +; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s -check-prefix=WIN64 +; PR8743 +; TAILJMPri64 should not receive "callee-saved" registers beyond epilogue. + +; AMD64: jmpq +; AMD64-NOT: %{{e[a-z]|rbx|rbp|r10|r12|r13|r14|r15}} + +; WIN64: jmpq +; WIN64-NOT: %{{e[a-z]|rbx|rsi|rdi|rbp|r12|r13|r14|r15}} + +%class = type { [8 x i8] } +%vt = type { i32 (...)** } + +define %vt* @_ZN4llvm9UnsetInit20convertInitializerToEPNS_5RecTyE(%class* +%this, %vt* %Ty) align 2 { +entry: + %0 = bitcast %vt* %Ty to %vt* (%vt*, %class*)*** + %vtable = load %vt* (%vt*, %class*)*** %0, align 8 + %vfn = getelementptr inbounds %vt* (%vt*, %class*)** %vtable, i64 4 + %1 = load %vt* (%vt*, %class*)** %vfn, align 8 + %call = tail call %vt* %1(%vt* %Ty, %class* %this) + ret %vt* %call +} diff --git a/test/CodeGen/X86/tailcallstack64.ll b/test/CodeGen/X86/tailcallstack64.ll index 52b074d..0c732d5 100644 --- a/test/CodeGen/X86/tailcallstack64.ll +++ b/test/CodeGen/X86/tailcallstack64.ll @@ -1,16 +1,20 @@ -; RUN: llc < %s -tailcallopt -march=x86-64 -post-RA-scheduler=true | FileCheck %s +; RUN: llc < %s -tailcallopt -mtriple=x86_64-linux -post-RA-scheduler=true | FileCheck %s +; RUN: llc < %s -tailcallopt -mtriple=x86_64-win32 -post-RA-scheduler=true | FileCheck %s + +; FIXME: Redundant unused stack allocation could be eliminated. +; CHECK: subq ${{24|88}}, %rsp ; Check that lowered arguments on the stack do not overwrite each other. ; Add %in1 %p1 to a different temporary register (%eax). -; CHECK: movl 32(%rsp), %eax +; CHECK: movl [[A1:32|144]](%rsp), %eax ; Move param %in1 to temp register (%r10d). -; CHECK: movl 40(%rsp), %r10d +; CHECK: movl [[A2:40|152]](%rsp), %r10d ; Add %in1 %p1 to a different temporary register (%eax). -; CHECK: addl %edi, %eax +; CHECK: addl {{%edi|%ecx}}, %eax ; Move param %in2 to stack. -; CHECK: movl %r10d, 32(%rsp) +; CHECK: movl %r10d, [[A1]](%rsp) ; Move result of addition to stack. -; CHECK: movl %eax, 40(%rsp) +; CHECK: movl %eax, [[A2]](%rsp) ; Eventually, do a TAILCALL ; CHECK: TAILCALL -- 1.7.1.GIT From stoklund at 2pi.dk Thu Jan 13 23:29:59 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 13 Jan 2011 21:29:59 -0800 Subject: [llvm-commits] [Review request] Tweaking Win64 Codegen In-Reply-To: References: <6C9AA982-EFB8-4020-AEA2-273C6C1C721C@2pi.dk> Message-ID: <705B073D-541C-499B-B33C-3FCE2A1A965A@2pi.dk> On Jan 13, 2011, at 8:41 PM, NAKAMURA Takumi wrote: > And I will show two new patches. > (Other attached patches are regenerated. I saw merge in some point.) > > * 0008-TableGen-PointerLikeRegClass-can-be-accepted-to-.patch.txt > > For example, it was invalid on ToT; > > def TCRETURNri64 : PseudoI<(outs), > (ins ptr_rc_tailcall:$dst, i32imm:$offset, > variable_ops), []>; > > When I looked into CodeGen, I got confidence I might let it valid, and I did. Yes, that looks fine. > * 0009-Target-X86-Tweak-win64-s-tailcall.patch.txt > > I got rid of instructions "TAIL****W64". > I can specify input register class with ptr_rc_tailcall, Very nice! > but I wonder how to specify alternative Defs to instructions. > Let me know if there were a way without "custom expand". Your custom inserter is correct, but I don't think it is necessary. Since these are return instructions, there isn't going to be any live registers across them, and only the call arguments will be live into the return instructions. That means it is OK to have too many registers in "Defs = [...]" for win64. You can just keep the lists as they are. > Please take a look, thank you. Your patches #8 and #9 look good to me. /jakob -------------- next part -------------- A non-text attachment was scrubbed... Name: smime.p7s Type: application/pkcs7-signature Size: 1929 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110113/2f71bc3f/attachment.bin From sabre at nondot.org Fri Jan 14 00:14:33 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 14 Jan 2011 06:14:33 -0000 Subject: [llvm-commits] [llvm] r123431 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-gep.ll Message-ID: <20110114061434.03A992A6C12C@llvm.org> Author: lattner Date: Fri Jan 14 00:14:33 2011 New Revision: 123431 URL: http://llvm.org/viewvc/llvm-project?rev=123431&view=rev Log: revert my fastisel patch again which apparently still gives the llvm-gcc-i386-linux-selfhost buildbot heartburn... Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=123431&r1=123430&r2=123431&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Fri Jan 14 00:14:33 2011 @@ -1933,7 +1933,7 @@ XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment); if (Result == 0) return false; - FuncInfo.MBB->insert(FuncInfo.InsertPt, Result); + MI->getParent()->insert(MI, Result); MI->eraseFromParent(); return true; } Modified: llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll?rev=123431&r1=123430&r2=123431&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-gep.ll Fri Jan 14 00:14:33 2011 @@ -70,20 +70,3 @@ ; X64: test4: ; X64: 128(%r{{.*}},%r{{.*}},8) } - -; PR8961 - Make sure the sext for the GEP addressing comes before the load that -; is folded. -define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind { - %v8 = getelementptr i8* %A, i32 %I - %v9 = bitcast i8* %v8 to i64* - %v10 = load i64* %v9 - %v11 = add i64 %B, %v10 - ret i64 %v11 -; X64: test5: -; X64: movslq %esi, %rax -; X64-NEXT: movq (%rdi,%rax), %rax -; X64-NEXT: addq %rdx, %rax -; X64-NEXT: ret -} - - From stoklund at 2pi.dk Fri Jan 14 00:33:46 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 14 Jan 2011 06:33:46 -0000 Subject: [llvm-commits] [llvm] r123432 - in /llvm/trunk/lib/CodeGen: MachineBasicBlock.cpp PHIElimination.cpp Message-ID: <20110114063346.1A2AF2A6C12C@llvm.org> Author: stoklund Date: Fri Jan 14 00:33:45 2011 New Revision: 123432 URL: http://llvm.org/viewvc/llvm-project?rev=123432&view=rev Log: Try for the third time to teach getFirstTerminator() about debug values. This time let's rephrase to trick gcc-4.3 into not miscompiling. Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/PHIElimination.cpp Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=123432&r1=123431&r2=123432&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Fri Jan 14 00:33:45 2011 @@ -156,9 +156,10 @@ MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() { iterator I = end(); - while (I != begin() && (--I)->getDesc().isTerminator()) + while (I != begin() && ((--I)->getDesc().isTerminator() || I->isDebugValue())) ; /*noop */ - if (I != end() && !I->getDesc().isTerminator()) ++I; + while (I != end() && !I->getDesc().isTerminator()) + ++I; return I; } Modified: llvm/trunk/lib/CodeGen/PHIElimination.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PHIElimination.cpp?rev=123432&r1=123431&r2=123432&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PHIElimination.cpp (original) +++ llvm/trunk/lib/CodeGen/PHIElimination.cpp Fri Jan 14 00:33:45 2011 @@ -339,6 +339,8 @@ #ifndef NDEBUG for (MachineBasicBlock::iterator TI = llvm::next(Term); TI != opBlock.end(); ++TI) { + if (TI->isDebugValue()) + continue; assert(!TI->readsRegister(SrcReg) && "Terminator instructions cannot use virtual registers unless" "they are the first terminator in a block!"); @@ -347,9 +349,13 @@ } else if (reusedIncoming || !IncomingReg) { // We may have to rewind a bit if we didn't insert a copy this time. KillInst = Term; - while (KillInst != opBlock.begin()) - if ((--KillInst)->readsRegister(SrcReg)) + while (KillInst != opBlock.begin()) { + --KillInst; + if (KillInst->isDebugValue()) + continue; + if (KillInst->readsRegister(SrcReg)) break; + } } else { // We just inserted this copy. KillInst = prior(InsertPos); From sabre at nondot.org Fri Jan 14 01:46:33 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 14 Jan 2011 07:46:33 -0000 Subject: [llvm-commits] [llvm] r123433 - /llvm/trunk/test/Transforms/Inline/basictest.ll Message-ID: <20110114074633.ED40C2A6C12C@llvm.org> Author: lattner Date: Fri Jan 14 01:46:33 2011 New Revision: 123433 URL: http://llvm.org/viewvc/llvm-project?rev=123433&view=rev Log: relax testcase a bit. Modified: llvm/trunk/test/Transforms/Inline/basictest.ll Modified: llvm/trunk/test/Transforms/Inline/basictest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/basictest.ll?rev=123433&r1=123432&r2=123433&view=diff ============================================================================== --- llvm/trunk/test/Transforms/Inline/basictest.ll (original) +++ llvm/trunk/test/Transforms/Inline/basictest.ll Fri Jan 14 01:46:33 2011 @@ -43,5 +43,5 @@ ; CHECK: @test2( ; CHECK-NOT: = alloca -; CHECK: ret i32 42 +; CHECK: ret i32 } From sabre at nondot.org Fri Jan 14 01:50:47 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 14 Jan 2011 07:50:47 -0000 Subject: [llvm-commits] [llvm] r123434 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <20110114075047.BDCB72A6C12C@llvm.org> Author: lattner Date: Fri Jan 14 01:50:47 2011 New Revision: 123434 URL: http://llvm.org/viewvc/llvm-project?rev=123434&view=rev Log: Implement full support for promoting allocas to registers using SSAUpdater instead of DomTree/DomFrontier. This may be interesting for reducing compile time. This is currently disabled, but seems to work just fine. When this is enabled, we eliminate two runs of dominator frontier, one in the "early per-function" optimizations and one in the "interlaced with inliner" function passes. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=123434&r1=123433&r2=123434&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Fri Jan 14 01:50:47 2011 @@ -35,6 +35,7 @@ #include "llvm/Target/TargetData.h" #include "llvm/Transforms/Utils/PromoteMemToReg.h" #include "llvm/Transforms/Utils/Local.h" +#include "llvm/Transforms/Utils/SSAUpdater.h" #include "llvm/Support/CallSite.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" @@ -51,6 +52,10 @@ STATISTIC(NumConverted, "Number of aggregates converted to scalar"); STATISTIC(NumGlobals, "Number of allocas copied from constant global"); +enum { + UsePromoteMemToReg = 1 +}; + namespace { struct SROA : public FunctionPass { static char ID; // Pass identification, replacement for typeid @@ -70,8 +75,10 @@ // getAnalysisUsage - This pass does not require any passes, but we know it // will not alter the CFG, so say so. virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequired(); - AU.addRequired(); + if (UsePromoteMemToReg) { + AU.addRequired(); + AU.addRequired(); + } AU.setPreservesCFG(); } @@ -804,11 +811,153 @@ return Changed; } +/// PromoteAlloca - Promote an alloca to registers, using SSAUpdater. +static void PromoteAlloca(AllocaInst *AI, SSAUpdater &SSA) { + SSA.Initialize(AI->getType()->getElementType(), AI->getName()); + + // First step: bucket up uses of the alloca by the block they occur in. + // This is important because we have to handle multiple defs/uses in a block + // ourselves: SSAUpdater is purely for cross-block references. + // FIXME: Want a TinyVector since there is often 0/1 element. + DenseMap > UsesByBlock; + + for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); + UI != E; ++UI) { + Instruction *User = cast(*UI); + UsesByBlock[User->getParent()].push_back(User); + } + + // Okay, now we can iterate over all the blocks in the function with uses, + // processing them. Keep track of which loads are loading a live-in value. + // Walk the uses in the use-list order to be determinstic. + SmallVector LiveInLoads; + DenseMap ReplacedLoads; + + for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); + UI != E; ++UI) { + Instruction *User = cast(*UI); + BasicBlock *BB = User->getParent(); + std::vector &BlockUses = UsesByBlock[BB]; + + // If this block has already been processed, ignore this repeat use. + if (BlockUses.empty()) continue; + + // Okay, this is the first use in the block. If this block just has a + // single user in it, we can rewrite it trivially. + if (BlockUses.size() == 1) { + // If it is a store, it is a trivial def of the value in the block. + if (StoreInst *SI = dyn_cast(User)) + SSA.AddAvailableValue(BB, SI->getOperand(0)); + else + // Otherwise it is a load, queue it to rewrite as a live-in load. + LiveInLoads.push_back(cast(User)); + BlockUses.clear(); + continue; + } + + // Otherwise, check to see if this block is all loads. + bool HasStore = false; + for (unsigned i = 0, e = BlockUses.size(); i != e; ++i) { + if (isa(BlockUses[i])) { + HasStore = true; + break; + } + } + + // If so, we can queue them all as live in loads. We don't have an + // efficient way to tell which on is first in the block and don't want to + // scan large blocks, so just add all loads as live ins. + if (!HasStore) { + for (unsigned i = 0, e = BlockUses.size(); i != e; ++i) + LiveInLoads.push_back(cast(BlockUses[i])); + BlockUses.clear(); + continue; + } + + // Otherwise, we have mixed loads and stores (or just a bunch of stores). + // Since SSAUpdater is purely for cross-block values, we need to determine + // the order of these instructions in the block. If the first use in the + // block is a load, then it uses the live in value. The last store defines + // the live out value. We handle this by doing a linear scan of the block. + Value *StoredValue = 0; + for (BasicBlock::iterator II = BB->begin(), E = BB->end(); II != E; ++II) { + if (LoadInst *L = dyn_cast(II)) { + // If this is a load from an unrelated pointer, ignore it. + if (L->getOperand(0) != AI) continue; + + // If we haven't seen a store yet, this is a live in use, otherwise + // use the stored value. + if (StoredValue) { + L->replaceAllUsesWith(StoredValue); + ReplacedLoads[L] = StoredValue; + } else { + LiveInLoads.push_back(L); + } + continue; + } + + if (StoreInst *S = dyn_cast(II)) { + // If this is a store to an unrelated pointer, ignore it. + if (S->getPointerOperand() != AI) continue; + + // Remember that this is the active value in the block. + StoredValue = S->getOperand(0); + } + } + + // The last stored value that happened is the live-out for the block. + assert(StoredValue && "Already checked that there is a store in block"); + SSA.AddAvailableValue(BB, StoredValue); + BlockUses.clear(); + } + + // Okay, now we rewrite all loads that use live-in values in the loop, + // inserting PHI nodes as necessary. + for (unsigned i = 0, e = LiveInLoads.size(); i != e; ++i) { + LoadInst *ALoad = LiveInLoads[i]; + Value *NewVal = SSA.GetValueInMiddleOfBlock(ALoad->getParent()); + ALoad->replaceAllUsesWith(NewVal); + ReplacedLoads[ALoad] = NewVal; + } + + // Now that everything is rewritten, delete the old instructions from the + // function. They should all be dead now. + for (Value::use_iterator UI = AI->use_begin(), E = AI->use_end(); UI != E; ) { + Instruction *User = cast(*UI++); + + // If this is a load that still has uses, then the load must have been added + // as a live value in the SSAUpdate data structure for a block (e.g. because + // the loaded value was stored later). In this case, we need to recursively + // propagate the updates until we get to the real value. + if (!User->use_empty()) { + Value *NewVal = ReplacedLoads[User]; + assert(NewVal && "not a replaced load?"); + + // Propagate down to the ultimate replacee. The intermediately loads + // could theoretically already have been deleted, so we don't want to + // dereference the Value*'s. + DenseMap::iterator RLI = ReplacedLoads.find(NewVal); + while (RLI != ReplacedLoads.end()) { + NewVal = RLI->second; + RLI = ReplacedLoads.find(NewVal); + } + + User->replaceAllUsesWith(NewVal); + } + + User->eraseFromParent(); + } +} + bool SROA::performPromotion(Function &F) { std::vector Allocas; - DominatorTree &DT = getAnalysis(); - DominanceFrontier &DF = getAnalysis(); + DominatorTree *DT = 0; + DominanceFrontier *DF = 0; + if (UsePromoteMemToReg) { + DT = &getAnalysis(); + DF = &getAnalysis(); + } BasicBlock &BB = F.getEntryBlock(); // Get the entry node for the function @@ -826,7 +975,15 @@ if (Allocas.empty()) break; - PromoteMemToReg(Allocas, DT, DF); + if (UsePromoteMemToReg) + PromoteMemToReg(Allocas, *DT, *DF); + else { + SSAUpdater SSA; + for (unsigned i = 0, e = Allocas.size(); i != e; ++i) { + PromoteAlloca(Allocas[i], SSA); + Allocas[i]->eraseFromParent(); + } + } NumPromoted += Allocas.size(); Changed = true; } From jay.foad at gmail.com Fri Jan 14 02:07:43 2011 From: jay.foad at gmail.com (Jay Foad) Date: Fri, 14 Jan 2011 08:07:43 -0000 Subject: [llvm-commits] [llvm] r123435 - in /llvm/trunk: include/llvm/Constants.h include/llvm/Instructions.h lib/VMCore/ConstantFold.cpp lib/VMCore/ConstantFold.h lib/VMCore/Constants.cpp lib/VMCore/Instructions.cpp Message-ID: <20110114080743.6D4DF2A6C12C@llvm.org> Author: foad Date: Fri Jan 14 02:07:43 2011 New Revision: 123435 URL: http://llvm.org/viewvc/llvm-project?rev=123435&view=rev Log: Remove casts between Value** and Constant**, which won't work if a static_cast from Constant* to Value* has to adjust the "this" pointer. This is groundwork for PR889. Modified: llvm/trunk/include/llvm/Constants.h llvm/trunk/include/llvm/Instructions.h llvm/trunk/lib/VMCore/ConstantFold.cpp llvm/trunk/lib/VMCore/ConstantFold.h llvm/trunk/lib/VMCore/Constants.cpp llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/include/llvm/Constants.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=123435&r1=123434&r2=123435&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constants.h (original) +++ llvm/trunk/include/llvm/Constants.h Fri Jan 14 02:07:43 2011 @@ -629,10 +629,12 @@ Constant *C2); static Constant *getSelectTy(const Type *Ty, Constant *C1, Constant *C2, Constant *C3); + template static Constant *getGetElementPtrTy(const Type *Ty, Constant *C, - Value* const *Idxs, unsigned NumIdxs); + IndexTy const *Idxs, unsigned NumIdxs); + template static Constant *getInBoundsGetElementPtrTy(const Type *Ty, Constant *C, - Value* const *Idxs, + IndexTy const *Idxs, unsigned NumIdxs); static Constant *getExtractElementTy(const Type *Ty, Constant *Val, Constant *Idx); @@ -645,6 +647,14 @@ static Constant *getInsertValueTy(const Type *Ty, Constant *Agg, Constant *Val, const unsigned *Idxs, unsigned NumIdxs); + template + static Constant *getGetElementPtrImpl(Constant *C, + IndexTy const *IdxList, + unsigned NumIdx); + template + static Constant *getInBoundsGetElementPtrImpl(Constant *C, + IndexTy const *IdxList, + unsigned NumIdx); public: // Static methods to construct a ConstantExpr of different kinds. Note that Modified: llvm/trunk/include/llvm/Instructions.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=123435&r1=123434&r2=123435&view=diff ============================================================================== --- llvm/trunk/include/llvm/Instructions.h (original) +++ llvm/trunk/include/llvm/Instructions.h Fri Jan 14 02:07:43 2011 @@ -458,6 +458,9 @@ Value* const *Idx, unsigned NumIdx); static const Type *getIndexedType(const Type *Ptr, + Constant* const *Idx, unsigned NumIdx); + + static const Type *getIndexedType(const Type *Ptr, uint64_t const *Idx, unsigned NumIdx); static const Type *getIndexedType(const Type *Ptr, Value *Idx); Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=123435&r1=123434&r2=123435&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantFold.cpp (original) +++ llvm/trunk/lib/VMCore/ConstantFold.cpp Fri Jan 14 02:07:43 2011 @@ -2067,53 +2067,52 @@ /// isInBoundsIndices - Test whether the given sequence of *normalized* indices /// is "inbounds". -static bool isInBoundsIndices(Constant *const *Idxs, size_t NumIdx) { +template +static bool isInBoundsIndices(IndexTy const *Idxs, size_t NumIdx) { // No indices means nothing that could be out of bounds. if (NumIdx == 0) return true; // If the first index is zero, it's in bounds. - if (Idxs[0]->isNullValue()) return true; + if (cast(Idxs[0])->isNullValue()) return true; // If the first index is one and all the rest are zero, it's in bounds, // by the one-past-the-end rule. if (!cast(Idxs[0])->isOne()) return false; for (unsigned i = 1, e = NumIdx; i != e; ++i) - if (!Idxs[i]->isNullValue()) + if (!cast(Idxs[i])->isNullValue()) return false; return true; } -Constant *llvm::ConstantFoldGetElementPtr(Constant *C, - bool inBounds, - Constant* const *Idxs, - unsigned NumIdx) { +template +static Constant *ConstantFoldGetElementPtrImpl(Constant *C, + bool inBounds, + IndexTy const *Idxs, + unsigned NumIdx) { + Constant *Idx0 = cast(Idxs[0]); if (NumIdx == 0 || - (NumIdx == 1 && Idxs[0]->isNullValue())) + (NumIdx == 1 && Idx0->isNullValue())) return C; if (isa(C)) { const PointerType *Ptr = cast(C->getType()); - const Type *Ty = GetElementPtrInst::getIndexedType(Ptr, - (Value **)Idxs, - (Value **)Idxs+NumIdx); + const Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs, Idxs+NumIdx); assert(Ty != 0 && "Invalid indices for GEP!"); return UndefValue::get(PointerType::get(Ty, Ptr->getAddressSpace())); } - Constant *Idx0 = Idxs[0]; if (C->isNullValue()) { bool isNull = true; for (unsigned i = 0, e = NumIdx; i != e; ++i) - if (!Idxs[i]->isNullValue()) { + if (!cast(Idxs[i])->isNullValue()) { isNull = false; break; } if (isNull) { const PointerType *Ptr = cast(C->getType()); - const Type *Ty = GetElementPtrInst::getIndexedType(Ptr, - (Value**)Idxs, - (Value**)Idxs+NumIdx); + const Type *Ty = GetElementPtrInst::getIndexedType(Ptr, Idxs, + Idxs+NumIdx); assert(Ty != 0 && "Invalid indices for GEP!"); return ConstantPointerNull::get( PointerType::get(Ty,Ptr->getAddressSpace())); @@ -2208,7 +2207,7 @@ ATy->getNumElements()); NewIdxs[i] = ConstantExpr::getSRem(CI, Factor); - Constant *PrevIdx = Idxs[i-1]; + Constant *PrevIdx = cast(Idxs[i-1]); Constant *Div = ConstantExpr::getSDiv(CI, Factor); // Before adding, extend both operands to i64 to avoid @@ -2236,7 +2235,7 @@ // If we did any factoring, start over with the adjusted indices. if (!NewIdxs.empty()) { for (unsigned i = 0; i != NumIdx; ++i) - if (!NewIdxs[i]) NewIdxs[i] = Idxs[i]; + if (!NewIdxs[i]) NewIdxs[i] = cast(Idxs[i]); return inBounds ? ConstantExpr::getInBoundsGetElementPtr(C, NewIdxs.data(), NewIdxs.size()) : @@ -2251,3 +2250,17 @@ return 0; } + +Constant *llvm::ConstantFoldGetElementPtr(Constant *C, + bool inBounds, + Constant* const *Idxs, + unsigned NumIdx) { + return ConstantFoldGetElementPtrImpl(C, inBounds, Idxs, NumIdx); +} + +Constant *llvm::ConstantFoldGetElementPtr(Constant *C, + bool inBounds, + Value* const *Idxs, + unsigned NumIdx) { + return ConstantFoldGetElementPtrImpl(C, inBounds, Idxs, NumIdx); +} Modified: llvm/trunk/lib/VMCore/ConstantFold.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.h?rev=123435&r1=123434&r2=123435&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/ConstantFold.h (original) +++ llvm/trunk/lib/VMCore/ConstantFold.h Fri Jan 14 02:07:43 2011 @@ -49,6 +49,8 @@ Constant *C1, Constant *C2); Constant *ConstantFoldGetElementPtr(Constant *C, bool inBounds, Constant* const *Idxs, unsigned NumIdx); + Constant *ConstantFoldGetElementPtr(Constant *C, bool inBounds, + Value* const *Idxs, unsigned NumIdx); } // End llvm namespace #endif Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=123435&r1=123434&r2=123435&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Fri Jan 14 02:07:43 2011 @@ -1546,8 +1546,9 @@ return pImpl->ExprConstants.getOrCreate(ReqTy, Key); } +template Constant *ConstantExpr::getGetElementPtrTy(const Type *ReqTy, Constant *C, - Value* const *Idxs, + IndexTy const *Idxs, unsigned NumIdx) { assert(GetElementPtrInst::getIndexedType(C->getType(), Idxs, Idxs+NumIdx) == @@ -1555,7 +1556,7 @@ "GEP indices invalid!"); if (Constant *FC = ConstantFoldGetElementPtr(C, /*inBounds=*/false, - (Constant**)Idxs, NumIdx)) + Idxs, NumIdx)) return FC; // Fold a few common cases... assert(C->getType()->isPointerTy() && @@ -1572,9 +1573,10 @@ return pImpl->ExprConstants.getOrCreate(ReqTy, Key); } +template Constant *ConstantExpr::getInBoundsGetElementPtrTy(const Type *ReqTy, Constant *C, - Value *const *Idxs, + IndexTy const *Idxs, unsigned NumIdx) { assert(GetElementPtrInst::getIndexedType(C->getType(), Idxs, Idxs+NumIdx) == @@ -1582,7 +1584,7 @@ "GEP indices invalid!"); if (Constant *FC = ConstantFoldGetElementPtr(C, /*inBounds=*/true, - (Constant**)Idxs, NumIdx)) + Idxs, NumIdx)) return FC; // Fold a few common cases... assert(C->getType()->isPointerTy() && @@ -1600,8 +1602,9 @@ return pImpl->ExprConstants.getOrCreate(ReqTy, Key); } -Constant *ConstantExpr::getGetElementPtr(Constant *C, Value* const *Idxs, - unsigned NumIdx) { +template +Constant *ConstantExpr::getGetElementPtrImpl(Constant *C, IndexTy const *Idxs, + unsigned NumIdx) { // Get the result type of the getelementptr! const Type *Ty = GetElementPtrInst::getIndexedType(C->getType(), Idxs, Idxs+NumIdx); @@ -1610,9 +1613,10 @@ return getGetElementPtrTy(PointerType::get(Ty, As), C, Idxs, NumIdx); } -Constant *ConstantExpr::getInBoundsGetElementPtr(Constant *C, - Value* const *Idxs, - unsigned NumIdx) { +template +Constant *ConstantExpr::getInBoundsGetElementPtrImpl(Constant *C, + IndexTy const *Idxs, + unsigned NumIdx) { // Get the result type of the getelementptr! const Type *Ty = GetElementPtrInst::getIndexedType(C->getType(), Idxs, Idxs+NumIdx); @@ -1621,15 +1625,26 @@ return getInBoundsGetElementPtrTy(PointerType::get(Ty, As), C, Idxs, NumIdx); } -Constant *ConstantExpr::getGetElementPtr(Constant *C, Constant* const *Idxs, +Constant *ConstantExpr::getGetElementPtr(Constant *C, Value* const *Idxs, + unsigned NumIdx) { + return getGetElementPtrImpl(C, Idxs, NumIdx); +} + +Constant *ConstantExpr::getGetElementPtr(Constant *C, Constant *const *Idxs, unsigned NumIdx) { - return getGetElementPtr(C, (Value* const *)Idxs, NumIdx); + return getGetElementPtrImpl(C, Idxs, NumIdx); +} + +Constant *ConstantExpr::getInBoundsGetElementPtr(Constant *C, + Value* const *Idxs, + unsigned NumIdx) { + return getInBoundsGetElementPtrImpl(C, Idxs, NumIdx); } Constant *ConstantExpr::getInBoundsGetElementPtr(Constant *C, - Constant* const *Idxs, + Constant *const *Idxs, unsigned NumIdx) { - return getInBoundsGetElementPtr(C, (Value* const *)Idxs, NumIdx); + return getInBoundsGetElementPtrImpl(C, Idxs, NumIdx); } Constant * Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=123435&r1=123434&r2=123435&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Fri Jan 14 02:07:43 2011 @@ -1174,6 +1174,12 @@ } const Type* GetElementPtrInst::getIndexedType(const Type *Ptr, + Constant* const *Idxs, + unsigned NumIdx) { + return getIndexedTypeInternal(Ptr, Idxs, NumIdx); +} + +const Type* GetElementPtrInst::getIndexedType(const Type *Ptr, uint64_t const *Idxs, unsigned NumIdx) { return getIndexedTypeInternal(Ptr, Idxs, NumIdx); From sabre at nondot.org Fri Jan 14 02:13:00 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 14 Jan 2011 08:13:00 -0000 Subject: [llvm-commits] [llvm] r123436 - in /llvm/trunk: include/llvm/InitializePasses.h include/llvm/Transforms/Scalar.h lib/Transforms/Scalar/Scalar.cpp lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <20110114081300.5E3A52A6C12C@llvm.org> Author: lattner Date: Fri Jan 14 02:13:00 2011 New Revision: 123436 URL: http://llvm.org/viewvc/llvm-project?rev=123436&view=rev Log: split SROA into two passes: one that uses DomFrontiers (-scalarrepl) and one that uses SSAUpdater (-scalarrepl-ssa) Modified: llvm/trunk/include/llvm/InitializePasses.h llvm/trunk/include/llvm/Transforms/Scalar.h llvm/trunk/lib/Transforms/Scalar/Scalar.cpp llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/include/llvm/InitializePasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=123436&r1=123435&r2=123436&view=diff ============================================================================== --- llvm/trunk/include/llvm/InitializePasses.h (original) +++ llvm/trunk/include/llvm/InitializePasses.h Fri Jan 14 02:13:00 2011 @@ -193,7 +193,8 @@ void initializeRenderMachineFunctionPass(PassRegistry&); void initializeSCCPPass(PassRegistry&); void initializeSRETPromotionPass(PassRegistry&); -void initializeSROAPass(PassRegistry&); +void initializeSROA_DFPass(PassRegistry&); +void initializeSROA_SSAUpPass(PassRegistry&); void initializeScalarEvolutionAliasAnalysisPass(PassRegistry&); void initializeScalarEvolutionPass(PassRegistry&); void initializeSimpleInlinerPass(PassRegistry&); Modified: llvm/trunk/include/llvm/Transforms/Scalar.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Scalar.h?rev=123436&r1=123435&r2=123436&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Scalar.h (original) +++ llvm/trunk/include/llvm/Transforms/Scalar.h Fri Jan 14 02:13:00 2011 @@ -73,7 +73,8 @@ // ScalarReplAggregates - Break up alloca's of aggregates into multiple allocas // if possible. // -FunctionPass *createScalarReplAggregatesPass(signed Threshold = -1); +FunctionPass *createScalarReplAggregatesPass(signed Threshold = -1, + bool UseDomFrontier = true); //===----------------------------------------------------------------------===// // Modified: llvm/trunk/lib/Transforms/Scalar/Scalar.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/Scalar.cpp?rev=123436&r1=123435&r2=123436&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/Scalar.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/Scalar.cpp Fri Jan 14 02:13:00 2011 @@ -53,7 +53,8 @@ initializeRegToMemPass(Registry); initializeSCCPPass(Registry); initializeIPSCCPPass(Registry); - initializeSROAPass(Registry); + initializeSROA_DFPass(Registry); + initializeSROA_SSAUpPass(Registry); initializeCFGSimplifyPassPass(Registry); initializeSimplifyHalfPowrLibCallsPass(Registry); initializeSimplifyLibCallsPass(Registry); Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=123436&r1=123435&r2=123436&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Fri Jan 14 02:13:00 2011 @@ -52,15 +52,10 @@ STATISTIC(NumConverted, "Number of aggregates converted to scalar"); STATISTIC(NumGlobals, "Number of allocas copied from constant global"); -enum { - UsePromoteMemToReg = 1 -}; - namespace { struct SROA : public FunctionPass { - static char ID; // Pass identification, replacement for typeid - explicit SROA(signed T = -1) : FunctionPass(ID) { - initializeSROAPass(*PassRegistry::getPassRegistry()); + SROA(int T, bool hasDF, char &ID) + : FunctionPass(ID), HasDomFrontiers(hasDF) { if (T == -1) SRThreshold = 128; else @@ -72,17 +67,8 @@ bool performScalarRepl(Function &F); bool performPromotion(Function &F); - // getAnalysisUsage - This pass does not require any passes, but we know it - // will not alter the CFG, so say so. - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - if (UsePromoteMemToReg) { - AU.addRequired(); - AU.addRequired(); - } - AU.setPreservesCFG(); - } - private: + bool HasDomFrontiers; TargetData *TD; /// DeadInsts - Keep track of instructions we have made dead, so that @@ -142,19 +128,62 @@ static MemTransferInst *isOnlyCopiedFromConstantGlobal(AllocaInst *AI); }; + + // SROA_DF - SROA that uses DominanceFrontier. + struct SROA_DF : public SROA { + static char ID; + public: + SROA_DF(int T = -1) : SROA(T, true, ID) { + initializeSROA_DFPass(*PassRegistry::getPassRegistry()); + } + + // getAnalysisUsage - This pass does not require any passes, but we know it + // will not alter the CFG, so say so. + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + AU.addRequired(); + AU.setPreservesCFG(); + } + }; + + // SROA_SSAUp - SROA that uses SSAUpdater. + struct SROA_SSAUp : public SROA { + static char ID; + public: + SROA_SSAUp(int T = -1) : SROA(T, false, ID) { + initializeSROA_SSAUpPass(*PassRegistry::getPassRegistry()); + } + + // getAnalysisUsage - This pass does not require any passes, but we know it + // will not alter the CFG, so say so. + virtual void getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesCFG(); + } + }; + } -char SROA::ID = 0; -INITIALIZE_PASS_BEGIN(SROA, "scalarrepl", - "Scalar Replacement of Aggregates", false, false) +char SROA_DF::ID = 0; +char SROA_SSAUp::ID = 0; + +INITIALIZE_PASS_BEGIN(SROA_DF, "scalarrepl", + "Scalar Replacement of Aggregates (DF)", false, false) INITIALIZE_PASS_DEPENDENCY(DominatorTree) INITIALIZE_PASS_DEPENDENCY(DominanceFrontier) -INITIALIZE_PASS_END(SROA, "scalarrepl", - "Scalar Replacement of Aggregates", false, false) +INITIALIZE_PASS_END(SROA_DF, "scalarrepl", + "Scalar Replacement of Aggregates (DF)", false, false) + +INITIALIZE_PASS_BEGIN(SROA_SSAUp, "scalarrepl-ssa", + "Scalar Replacement of Aggregates (SSAUp)", false, false) +INITIALIZE_PASS_END(SROA_SSAUp, "scalarrepl-ssa", + "Scalar Replacement of Aggregates (SSAUp)", false, false) // Public interface to the ScalarReplAggregates pass -FunctionPass *llvm::createScalarReplAggregatesPass(signed int Threshold) { - return new SROA(Threshold); +FunctionPass *llvm::createScalarReplAggregatesPass(int Threshold, + bool UseDomFrontier) { + if (UseDomFrontier) + return new SROA_DF(Threshold); + return new SROA_SSAUp(Threshold); } @@ -954,7 +983,7 @@ std::vector Allocas; DominatorTree *DT = 0; DominanceFrontier *DF = 0; - if (UsePromoteMemToReg) { + if (HasDomFrontiers) { DT = &getAnalysis(); DF = &getAnalysis(); } @@ -975,7 +1004,7 @@ if (Allocas.empty()) break; - if (UsePromoteMemToReg) + if (HasDomFrontiers) PromoteMemToReg(Allocas, *DT, *DF); else { SSAUpdater SSA; From sabre at nondot.org Fri Jan 14 02:21:08 2011 From: sabre at nondot.org (Chris Lattner) Date: Fri, 14 Jan 2011 08:21:08 -0000 Subject: [llvm-commits] [llvm] r123437 - /llvm/trunk/include/llvm/Support/StandardPasses.h Message-ID: <20110114082108.A46552A6C12C@llvm.org> Author: lattner Date: Fri Jan 14 02:21:08 2011 New Revision: 123437 URL: http://llvm.org/viewvc/llvm-project?rev=123437&view=rev Log: switch the second scalarrepl pass to use SSAUpdater. We run two scalarrepl passes: one early in the cleanup code and one late interlaced with the inliner. The second one is important because inlining and other scalar optzns can unpin allocas, allowing them to be split up and promoted. While important for performance, this is also relatively rare, and we would previously force a (non-lazy) computation of DomFrontiers, which happened even if nothing became unpinned. With this patch, the first pass of scalarrepl still promotes the vast bulk of allocas in programs, but hte second pass has changed to use SSAUpdater, which is more "sparse" and lazy. This speeds up opt -O3 time on kimwitu++ (a c++ app) by about 1%. The numbers are interesting: the first pass promotes ~17500 allocas. The second pass promotes about 1600. For non-C++ codes, the compile time win should be greater, because the second pass of scalarrepl does less. Modified: llvm/trunk/include/llvm/Support/StandardPasses.h Modified: llvm/trunk/include/llvm/Support/StandardPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=123437&r1=123436&r2=123437&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) +++ llvm/trunk/include/llvm/Support/StandardPasses.h Fri Jan 14 02:21:08 2011 @@ -125,7 +125,8 @@ PM->add(createArgumentPromotionPass()); // Scalarize uninlined fn args // Start of function pass. - PM->add(createScalarReplAggregatesPass()); // Break up aggregate allocas + // Break up aggregate allocas, using SSAUpdater. + PM->add(createScalarReplAggregatesPass(-1, false)); PM->add(createEarlyCSEPass()); // Catch trivial redundancies if (OptimizeBuiltins) PM->add(createSimplifyLibCallsPass()); // Library Call Optimizations From simbuerg at googlemail.com Fri Jan 14 02:49:50 2011 From: simbuerg at googlemail.com (Andreas Simbuerger) Date: Fri, 14 Jan 2011 09:49:50 +0100 Subject: [llvm-commits] [PATCH] Add single entry / single exit accessors. In-Reply-To: <4D2F9228.6030706@fim.uni-passau.de> References: <4D2EE1B9.6020408@fim.uni-passau.de> <4D2F1A59.3020305@fim.uni-passau.de> <4D2F50A9.2090803@googlemail.com> <4D2F9228.6030706@fim.uni-passau.de> Message-ID: <4D300E2E.7060401@googlemail.com> Am 14.01.2011 01:00, schrieb Tobias Grosser: >>>> >> - BasicBlock *Pred = *PI; >>>> >> + Pred = *PI; >>>> >> if (DT->getNode(Pred)&& !contains(Pred)) { >>>> >> - if (found) { >>>> >> - isSimple = false; >>>> >> - break; >>>> >> - } >>>> >> - found = true; >>>> >> + if (ee) >>>> >> + return 0; >>>> >> + >>>> >> + ee = Pred; >>> > Can you combine the two if conditions? >> I don't understand, as the predicate >> (DT->getNode(Pred)&& !contains(Pred)) has to be valid for >> both statements inside the block, so I would have to recheck that in >> an else branch after merging both if's? Perhaps I'm just not thinking >> clearly, it's a bit late;-) > > Don't mind. I just looked at the patch and did not see the assignment. > >>>> >> +bool Region::isSimple() const { >>>> >> + return !(isTopLevelRegion()) >>>> >> +&& (getSingleEntryBlock() != 0) >>>> >> +&& (getSingleExitBlock() != 0); >>> > I am not sure if my email has removed some spaces/tabs. But please >>> > recheck indentation. >> I think so, the indentation is correct within my mail client. I attached >> two versions of the patch >> >> without *.svn.patch was generated using git diff --no-prefix ... and >> the other one was generated using git format-patch. > The format-patch one is fine. I changed this slightly to fit into one > line. I believe this makes it more readable. > >> + /// @brief Return the first block of this region's single entry edge, >> + /// if existing. >> + /// >> + /// @return The BasicBlock starting this region's single entry edge, >> + /// else NULL. >> + BasicBlock *getSingleEntryBlock() const; >> + >> + /// @brief Return the first block of this region's single exit edge, >> + /// if existing. >> + /// >> + /// @return The BasicBlock starting this region's single exit edge, >> + /// else NULL. >> + BasicBlock *getSingleExitBlock() const; > > You forgot to rename the functions in the header file. > > I committed the patch after fixing two items mentioned above: > > http://llvm.org/viewvc/llvm-project/?view=rev&revision=123410 > Sorry, they were changed but it seems they got mixed up while switching branches :/ Thanks for fixing. Shouldn't format patches when it's late :-). > Thanks for your contribution > > Tobi From simbuerg at fim.uni-passau.de Fri Jan 14 06:06:34 2011 From: simbuerg at fim.uni-passau.de (Andreas Simbuerger) Date: Fri, 14 Jan 2011 13:06:34 +0100 Subject: [llvm-commits] [PATCH] Add SeSeRegionInfo transform pass Message-ID: <4D303C4A.6070605@fim.uni-passau.de> Hi, this patch adds a small transform pass that converts a refined region into a simple region by adding the required edges at the region entry / exit. Basically it should update the RegionInfo analysis correctly, but sometimes it fails to do so. This requires some work on the RegionInfo::splitBlock methods. I'll try to figure it out and send a patch for that at a later time. Test cases will follow in a separate patch. Cheers, Andreas -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Add-SeSeRegionInfo-transform-pass.patch Type: text/x-patch Size: 8917 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110114/f9cadfd5/attachment.bin From baldrick at free.fr Fri Jan 14 08:16:33 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 14 Jan 2011 14:16:33 -0000 Subject: [llvm-commits] [llvm] r123440 - in /llvm/trunk/test/Transforms/InstSimplify: 2010-12-20-Boolean.ll 2010-12-20-I1Arithmetic.ll Message-ID: <20110114141633.325E52A6C12C@llvm.org> Author: baldrick Date: Fri Jan 14 08:16:33 2011 New Revision: 123440 URL: http://llvm.org/viewvc/llvm-project?rev=123440&view=rev Log: Rename this test. Added: llvm/trunk/test/Transforms/InstSimplify/2010-12-20-Boolean.ll - copied unchanged from r123439, llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll Removed: llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll Removed: llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll?rev=123439&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll (original) +++ llvm/trunk/test/Transforms/InstSimplify/2010-12-20-I1Arithmetic.ll (removed) @@ -1,29 +0,0 @@ -; RUN: opt < %s -instsimplify -S | FileCheck %s - -define i1 @add(i1 %x) { -; CHECK: @add - %z = add i1 %x, %x - ret i1 %z -; CHECK: ret i1 false -} - -define i1 @sub(i1 %x) { -; CHECK: @sub - %z = sub i1 false, %x - ret i1 %z -; CHECK: ret i1 %x -} - -define i1 @mul(i1 %x) { -; CHECK: @mul - %z = mul i1 %x, %x - ret i1 %z -; CHECK: ret i1 %x -} - -define i1 @ne(i1 %x) { -; CHECK: @ne - %z = icmp ne i1 %x, 0 - ret i1 %z -; CHECK: ret i1 %x -} From baldrick at free.fr Fri Jan 14 08:44:13 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 14 Jan 2011 14:44:13 -0000 Subject: [llvm-commits] [llvm] r123441 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/InstSimplify/2011-01-14-Thread.ll Message-ID: <20110114144413.283B12A6C12C@llvm.org> Author: baldrick Date: Fri Jan 14 08:44:12 2011 New Revision: 123441 URL: http://llvm.org/viewvc/llvm-project?rev=123441&view=rev Log: Factorize common code out of the InstructionSimplify shift logic. Add in threading of shifts over selects and phis while there. This fires here and there in the testsuite, to not much effect. For example when compiling spirit it fires 5 times, during early-cse, resulting in 6 more cse simplifications, and 3 more terminators being folded by jump threading, but the final bitcode doesn't change in any interesting way: other optimizations would have caught the opportunity anyway, only later. Added: llvm/trunk/test/Transforms/InstSimplify/2011-01-14-Thread.ll Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=123441&r1=123440&r2=123441&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Fri Jan 14 08:44:12 2011 @@ -684,31 +684,27 @@ return ::SimplifyMulInst(Op0, Op1, TD, DT, RecursionLimit); } -/// SimplifyShlInst - Given operands for an Shl, see if we can +/// SimplifyShift - Given operands for an Shl, LShr or AShr, see if we can /// fold the result. If not, this returns null. -static Value *SimplifyShlInst(Value *Op0, Value *Op1, const TargetData *TD, - const DominatorTree *DT, unsigned MaxRecurse) { +static Value *SimplifyShift(unsigned Opcode, Value *Op0, Value *Op1, + const TargetData *TD, const DominatorTree *DT, + unsigned MaxRecurse) { if (Constant *C0 = dyn_cast(Op0)) { if (Constant *C1 = dyn_cast(Op1)) { Constant *Ops[] = { C0, C1 }; - return ConstantFoldInstOperands(Instruction::Shl, C0->getType(), Ops, 2, - TD); + return ConstantFoldInstOperands(Opcode, C0->getType(), Ops, 2, TD); } } - // 0 << X -> 0 + // 0 shift by X -> 0 if (match(Op0, m_Zero())) return Op0; - // X << 0 -> X + // X shift by 0 -> X if (match(Op1, m_Zero())) return Op0; - // undef << X -> 0 - if (isa(Op0)) - return Constant::getNullValue(Op0->getType()); - - // X << undef -> undef because it may shift by the bitwidth. + // X shift by undef -> undef because it may shift by the bitwidth. if (isa(Op1)) return Op1; @@ -718,6 +714,32 @@ Op0->getType()->getScalarSizeInBits()) return UndefValue::get(Op0->getType()); + // If the operation is with the result of a select instruction, check whether + // operating on either branch of the select always yields the same value. + if (isa(Op0) || isa(Op1)) + if (Value *V = ThreadBinOpOverSelect(Opcode, Op0, Op1, TD, DT, MaxRecurse)) + return V; + + // If the operation is with the result of a phi instruction, check whether + // operating on all incoming values of the phi always yields the same value. + if (isa(Op0) || isa(Op1)) + if (Value *V = ThreadBinOpOverPHI(Opcode, Op0, Op1, TD, DT, MaxRecurse)) + return V; + + return 0; +} + +/// SimplifyShlInst - Given operands for an Shl, see if we can +/// fold the result. If not, this returns null. +static Value *SimplifyShlInst(Value *Op0, Value *Op1, const TargetData *TD, + const DominatorTree *DT, unsigned MaxRecurse) { + if (Value *V = SimplifyShift(Instruction::Shl, Op0, Op1, TD, DT, MaxRecurse)) + return V; + + // undef << X -> 0 + if (isa(Op0)) + return Constant::getNullValue(Op0->getType()); + return 0; } @@ -730,36 +752,13 @@ /// fold the result. If not, this returns null. static Value *SimplifyLShrInst(Value *Op0, Value *Op1, const TargetData *TD, const DominatorTree *DT, unsigned MaxRecurse) { - if (Constant *C0 = dyn_cast(Op0)) { - if (Constant *C1 = dyn_cast(Op1)) { - Constant *Ops[] = { C0, C1 }; - return ConstantFoldInstOperands(Instruction::LShr, C0->getType(), Ops, 2, - TD); - } - } - - // 0 >> X -> 0 - if (match(Op0, m_Zero())) - return Op0; + if (Value *V = SimplifyShift(Instruction::LShr, Op0, Op1, TD, DT, MaxRecurse)) + return V; // undef >>l X -> 0 if (isa(Op0)) return Constant::getNullValue(Op0->getType()); - // X >> 0 -> X - if (match(Op1, m_Zero())) - return Op0; - - // X >> undef -> undef because it may shift by the bitwidth. - if (isa(Op1)) - return Op1; - - // Shifting by the bitwidth or more is undefined. - if (ConstantInt *CI = dyn_cast(Op1)) - if (CI->getValue().getLimitedValue() >= - Op0->getType()->getScalarSizeInBits()) - return UndefValue::get(Op0->getType()); - return 0; } @@ -772,17 +771,8 @@ /// fold the result. If not, this returns null. static Value *SimplifyAShrInst(Value *Op0, Value *Op1, const TargetData *TD, const DominatorTree *DT, unsigned MaxRecurse) { - if (Constant *C0 = dyn_cast(Op0)) { - if (Constant *C1 = dyn_cast(Op1)) { - Constant *Ops[] = { C0, C1 }; - return ConstantFoldInstOperands(Instruction::AShr, C0->getType(), Ops, 2, - TD); - } - } - - // 0 >> X -> 0 - if (match(Op0, m_Zero())) - return Op0; + if (Value *V = SimplifyShift(Instruction::AShr, Op0, Op1, TD, DT, MaxRecurse)) + return V; // all ones >>a X -> all ones if (match(Op0, m_AllOnes())) @@ -792,20 +782,6 @@ if (isa(Op0)) return Constant::getAllOnesValue(Op0->getType()); - // X >> 0 -> X - if (match(Op1, m_Zero())) - return Op0; - - // X >> undef -> undef because it may shift by the bitwidth. - if (isa(Op1)) - return Op1; - - // Shifting by the bitwidth or more is undefined. - if (ConstantInt *CI = dyn_cast(Op1)) - if (CI->getValue().getLimitedValue() >= - Op0->getType()->getScalarSizeInBits()) - return UndefValue::get(Op0->getType()); - return 0; } Added: llvm/trunk/test/Transforms/InstSimplify/2011-01-14-Thread.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/2011-01-14-Thread.ll?rev=123441&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstSimplify/2011-01-14-Thread.ll (added) +++ llvm/trunk/test/Transforms/InstSimplify/2011-01-14-Thread.ll Fri Jan 14 08:44:12 2011 @@ -0,0 +1,9 @@ +; RUN: opt < %s -instsimplify -S | FileCheck %s + +define i32 @shift_select(i1 %cond) { +; CHECK: @shift_select + %s = select i1 %cond, i32 0, i32 1 + %r = lshr i32 %s, 1 + ret i32 %r +; CHECK: ret i32 0 +} From benny.kra at googlemail.com Fri Jan 14 09:23:29 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Fri, 14 Jan 2011 16:23:29 +0100 Subject: [llvm-commits] [llvm] r123390 - /llvm/trunk/tools/bugpoint/bugpoint.cpp In-Reply-To: <20110113194854.804912A6C12C@llvm.org> References: <20110113194854.804912A6C12C@llvm.org> Message-ID: <3ACD5B91-3F05-474F-8668-6088BC1EFC0A@gmail.com> On 13.01.2011, at 20:48, Devang Patel wrote: > Author: dpatel > Date: Thu Jan 13 13:48:54 2011 > New Revision: 123390 > > URL: http://llvm.org/viewvc/llvm-project?rev=123390&view=rev > Log: > Little help to debug the bugpoint itself. > Patch by Bob Wilson. > > Modified: > llvm/trunk/tools/bugpoint/bugpoint.cpp > > Modified: llvm/trunk/tools/bugpoint/bugpoint.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/bugpoint.cpp?rev=123390&r1=123389&r2=123390&view=diff > ============================================================================== > --- llvm/trunk/tools/bugpoint/bugpoint.cpp (original) > +++ llvm/trunk/tools/bugpoint/bugpoint.cpp Thu Jan 13 13:48:54 2011 > @@ -27,6 +27,10 @@ > #include "llvm/Support/Signals.h" > #include "llvm/Support/Valgrind.h" > #include "llvm/LinkAllVMCore.h" > + > +// Enable this macro to debug bugpoint itself. > +#define DEBUG_BUGPOINT 0 > + > using namespace llvm; > > static cl::opt > @@ -71,9 +75,11 @@ > /// BugpointIsInterrupted - Set to true when the user presses ctrl-c. > bool llvm::BugpointIsInterrupted = false; > > +#ifndef DEBUG_BUGPOINT > static void BugpointInterruptFunction() { > BugpointIsInterrupted = true; > } > +#endif > > // Hack to capture a pass list. > namespace { > @@ -91,9 +97,11 @@ > } > > int main(int argc, char **argv) { > +#ifndef DEBUG_BUGPOINT > llvm::sys::PrintStackTraceOnErrorSignal(); > llvm::PrettyStackTraceProgram X(argc, argv); > llvm_shutdown_obj Y; // Call llvm_shutdown() on exit. > +#endif > > // Initialize passes > PassRegistry &Registry = *PassRegistry::getPassRegistry(); > @@ -111,7 +119,9 @@ > "LLVM automatic testcase reducer. See\nhttp://" > "llvm.org/cmds/bugpoint.html" > " for more information.\n"); > +#ifndef DEBUG_BUGPOINT > sys::SetInterruptFunction(BugpointInterruptFunction); > +#endif > > LLVMContext& Context = getGlobalContext(); > // If we have an override, set it and then track the triple we want Modules > @@ -160,7 +170,9 @@ > > // Bugpoint has the ability of generating a plethora of core files, so to > // avoid filling up the disk, we prevent it > +#ifndef DEBUG_BUGPOINT > sys::Process::PreventCoreFiles(); > +#endif > > std::string Error; > bool Failure = D.run(Error); "#ifndef" checks whether a macro is not defined by the preprocessor. "#define DEBUG_BUGPOINT 0" is a definition so the debug mode is always enabled now. From baldrick at free.fr Fri Jan 14 09:26:10 2011 From: baldrick at free.fr (Duncan Sands) Date: Fri, 14 Jan 2011 15:26:10 -0000 Subject: [llvm-commits] [llvm] r123442 - in /llvm/trunk: lib/Analysis/InstructionSimplify.cpp test/Transforms/InstSimplify/2010-12-20-Reassociate.ll Message-ID: <20110114152610.D33822A6C12C@llvm.org> Author: baldrick Date: Fri Jan 14 09:26:10 2011 New Revision: 123442 URL: http://llvm.org/viewvc/llvm-project?rev=123442&view=rev Log: Turn X-(X-Y) into Y. According to my auto-simplifier this is the most common simplification present in fully optimized code (I think instcombine fails to transform some of these when "X-Y" has more than one use). Fires here and there all over the test-suite, for example it eliminates 8 subtractions in the final IR for 445.gobmk, 2 subs in 447.dealII, 2 in paq8p etc. Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp llvm/trunk/test/Transforms/InstSimplify/2010-12-20-Reassociate.ll Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=123442&r1=123441&r2=123442&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original) +++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Fri Jan 14 09:26:10 2011 @@ -593,11 +593,25 @@ match(Op0, m_Add(m_Specific(Op1), m_Value(X)))) return X; - /// i1 sub -> xor. + // i1 sub -> xor. if (MaxRecurse && Op0->getType()->isIntegerTy(1)) if (Value *V = SimplifyXorInst(Op0, Op1, TD, DT, MaxRecurse-1)) return V; + // X - (X - Y) -> Y. More generally Z - (X - Y) -> (Z - X) + Y if everything + // simplifies. + Value *Y = 0, *Z = Op0; + if (MaxRecurse && match(Op1, m_Sub(m_Value(X), m_Value(Y)))) // Z - (X - Y) + // See if "V === Z - X" simplifies. + if (Value *V = SimplifyBinOp(Instruction::Sub, Z, X, TD, DT, MaxRecurse-1)) + // It does! Now see if "W === V + Y" simplifies. + if (Value *W = SimplifyBinOp(Instruction::Add, V, Y, TD, DT, + MaxRecurse-1)) { + // It does, we successfully reassociated! + ++NumReassoc; + return W; + } + // Mul distributes over Sub. Try some generic simplifications based on this. if (Value *V = FactorizeBinOp(Instruction::Sub, Op0, Op1, Instruction::Mul, TD, DT, MaxRecurse)) Modified: llvm/trunk/test/Transforms/InstSimplify/2010-12-20-Reassociate.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/2010-12-20-Reassociate.ll?rev=123442&r1=123441&r2=123442&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstSimplify/2010-12-20-Reassociate.ll (original) +++ llvm/trunk/test/Transforms/InstSimplify/2010-12-20-Reassociate.ll Fri Jan 14 09:26:10 2011 @@ -62,3 +62,11 @@ ret i32 %l ; CHECK: ret i32 %y } + +define i32 @sub1(i32 %x, i32 %y) { +; CHECK: @sub1 + %d = sub i32 %x, %y + %r = sub i32 %x, %d + ret i32 %r +; CHECK: ret i32 %y +} From rafael.espindola at gmail.com Fri Jan 14 09:34:28 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Fri, 14 Jan 2011 10:34:28 -0500 Subject: [llvm-commits] [llvm] r123405 - /llvm/trunk/lib/Target/README.txt In-Reply-To: <20110113220815.5EA392A6C12C@llvm.org> References: <20110113220815.5EA392A6C12C@llvm.org> Message-ID: <4D306D04.8020205@gmail.com> On 11-01-13 5:08 PM, Chris Lattner wrote: > Author: lattner > Date: Thu Jan 13 16:08:15 2011 > New Revision: 123405 > > URL: http://llvm.org/viewvc/llvm-project?rev=123405&view=rev > Log: > memcpy + metadata = bliss :) Would adding stores of undefs to the holes have the same effect? > > Modified: > llvm/trunk/lib/Target/README.txt > > Modified: llvm/trunk/lib/Target/README.txt > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/README.txt?rev=123405&r1=123404&r2=123405&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/README.txt (original) > +++ llvm/trunk/lib/Target/README.txt Thu Jan 13 16:08:15 2011 > @@ -2259,3 +2259,51 @@ > transform the fmul to 0.0, and then the fadd to 2.0. > > //===---------------------------------------------------------------------===// > + > +We should enhance memcpy/memcpy/memset to allow a metadata node on them > +indicating that some bytes of the transfer are undefined. This is useful for > +frontends like clang when lowering struct lowering, when some elements of the > +struct are undefined. Consider something like this: > + > +struct x { > + char a; > + int b[4]; > +}; > +void foo(struct x*P); > +struct x testfunc() { > + struct x V1, V2; > + foo(&V1); > + V2 = V1; > + > + return V2; > +} > + > +We currently compile this to: > +$ clang t.c -S -o - -O0 -emit-llvm | opt -scalarrepl -S > + > + > +%struct.x = type { i8, [4 x i32] } > + > +define void @testfunc(%struct.x* sret %agg.result) nounwind ssp { > +entry: > + %V1 = alloca %struct.x, align 4 > + call void @foo(%struct.x* %V1) > + %tmp1 = bitcast %struct.x* %V1 to i8* > + %0 = bitcast %struct.x* %V1 to i160* > + %srcval1 = load i160* %0, align 4 > + %tmp2 = bitcast %struct.x* %agg.result to i8* > + %1 = bitcast %struct.x* %agg.result to i160* > + store i160 %srcval1, i160* %1, align 4 > + ret void > +} > + > +This happens because SRoA sees that the temp alloca has is being memcpy'd into > +and out of and it has holes and it has to be conservative. If we knew about the > +holes, then this could be much much better. > + > +Having information about these holes would also improve memcpy (etc) lowering at > +llc time when it gets inlined, because we can use smaller transfers. This also > +avoids partial register stalls in some important cases. > + > +//===---------------------------------------------------------------------===// > + > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From dpatel at apple.com Fri Jan 14 09:55:50 2011 From: dpatel at apple.com (Devang Patel) Date: Fri, 14 Jan 2011 15:55:50 -0000 Subject: [llvm-commits] [llvm] r123443 - /llvm/trunk/tools/bugpoint/bugpoint.cpp Message-ID: <20110114155550.9629A2A6C12C@llvm.org> Author: dpatel Date: Fri Jan 14 09:55:50 2011 New Revision: 123443 URL: http://llvm.org/viewvc/llvm-project?rev=123443&view=rev Log: Disable debug mode. Modified: llvm/trunk/tools/bugpoint/bugpoint.cpp Modified: llvm/trunk/tools/bugpoint/bugpoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/bugpoint.cpp?rev=123443&r1=123442&r2=123443&view=diff ============================================================================== --- llvm/trunk/tools/bugpoint/bugpoint.cpp (original) +++ llvm/trunk/tools/bugpoint/bugpoint.cpp Fri Jan 14 09:55:50 2011 @@ -28,8 +28,8 @@ #include "llvm/Support/Valgrind.h" #include "llvm/LinkAllVMCore.h" -// Enable this macro to debug bugpoint itself. -#define DEBUG_BUGPOINT 0 +//Enable this macro to debug bugpoint itself. +//#define DEBUG_BUGPOINT 1 using namespace llvm; From dpatel at apple.com Fri Jan 14 09:59:02 2011 From: dpatel at apple.com (Devang Patel) Date: Fri, 14 Jan 2011 07:59:02 -0800 Subject: [llvm-commits] [llvm] r123390 - /llvm/trunk/tools/bugpoint/bugpoint.cpp In-Reply-To: <3ACD5B91-3F05-474F-8668-6088BC1EFC0A@gmail.com> References: <20110113194854.804912A6C12C@llvm.org> <3ACD5B91-3F05-474F-8668-6088BC1EFC0A@gmail.com> Message-ID: On Jan 14, 2011, at 7:23 AM, Benjamin Kramer wrote: > > On 13.01.2011, at 20:48, Devang Patel wrote: > >> Author: dpatel >> Date: Thu Jan 13 13:48:54 2011 >> New Revision: 123390 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=123390&view=rev >> Log: >> Little help to debug the bugpoint itself. >> Patch by Bob Wilson. >> >> Modified: >> llvm/trunk/tools/bugpoint/bugpoint.cpp >> >> Modified: llvm/trunk/tools/bugpoint/bugpoint.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/bugpoint/bugpoint.cpp?rev=123390&r1=123389&r2=123390&view=diff >> ============================================================================== >> --- llvm/trunk/tools/bugpoint/bugpoint.cpp (original) >> +++ llvm/trunk/tools/bugpoint/bugpoint.cpp Thu Jan 13 13:48:54 2011 >> @@ -27,6 +27,10 @@ >> #include "llvm/Support/Signals.h" >> #include "llvm/Support/Valgrind.h" >> #include "llvm/LinkAllVMCore.h" >> + >> +// Enable this macro to debug bugpoint itself. >> +#define DEBUG_BUGPOINT 0 >> + >> using namespace llvm; >> >> static cl::opt >> @@ -71,9 +75,11 @@ >> /// BugpointIsInterrupted - Set to true when the user presses ctrl-c. >> bool llvm::BugpointIsInterrupted = false; >> >> +#ifndef DEBUG_BUGPOINT >> static void BugpointInterruptFunction() { >> BugpointIsInterrupted = true; >> } >> +#endif >> >> // Hack to capture a pass list. >> namespace { >> @@ -91,9 +97,11 @@ >> } >> >> int main(int argc, char **argv) { >> +#ifndef DEBUG_BUGPOINT >> llvm::sys::PrintStackTraceOnErrorSignal(); >> llvm::PrettyStackTraceProgram X(argc, argv); >> llvm_shutdown_obj Y; // Call llvm_shutdown() on exit. >> +#endif >> >> // Initialize passes >> PassRegistry &Registry = *PassRegistry::getPassRegistry(); >> @@ -111,7 +119,9 @@ >> "LLVM automatic testcase reducer. See\nhttp://" >> "llvm.org/cmds/bugpoint.html" >> " for more information.\n"); >> +#ifndef DEBUG_BUGPOINT >> sys::SetInterruptFunction(BugpointInterruptFunction); >> +#endif >> >> LLVMContext& Context = getGlobalContext(); >> // If we have an override, set it and then track the triple we want Modules >> @@ -160,7 +170,9 @@ >> >> // Bugpoint has the ability of generating a plethora of core files, so to >> // avoid filling up the disk, we prevent it >> +#ifndef DEBUG_BUGPOINT >> sys::Process::PreventCoreFiles(); >> +#endif >> >> std::string Error; >> bool Failure = D.run(Error); > > "#ifndef" checks whether a macro is not defined by the preprocessor. > "#define DEBUG_BUGPOINT 0" is a definition so the debug mode is always enabled now. oops. FIxed. - Devang From 6yearold at gmail.com Fri Jan 14 10:08:14 2011 From: 6yearold at gmail.com (arrowdodger) Date: Fri, 14 Jan 2011 19:08:14 +0300 Subject: [llvm-commits] [PATCH][CMake] include/Config/config.h.cmake reorganization. Message-ID: Here is first part of patch, which reorders defines in CMake-generated config.h to match with autotools-generated one. This is done for easer diff'ing and finding discrepancies between files generated by CMake and autoools. I've checked my patch 3 times, so it shouldn't break anything. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110114/7609ec1b/attachment.html From ofv at wanadoo.es Fri Jan 14 10:13:50 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Fri, 14 Jan 2011 17:13:50 +0100 Subject: [llvm-commits] [PATCH][CMake] include/Config/config.h.cmake reorganization. References: Message-ID: <87lj2ncvk1.fsf@wanadoo.es> arrowdodger <6yearold at gmail.com> writes: > Here is first part of patch, No, it isn't ;-) [snip] From jay.foad at gmail.com Fri Jan 14 10:15:46 2011 From: jay.foad at gmail.com (Jay Foad) Date: Fri, 14 Jan 2011 16:15:46 +0000 Subject: [llvm-commits] [PATCH] remove OperandTraits<>::Layout Message-ID: OperandTraits<>::Layout doesn't seem to be used for anything. How about removing it? Tested with "make check". OK to commit? Thanks, Jay. -------------- next part -------------- A non-text attachment was scrubbed... Name: remove-operandtraits-layout Type: application/octet-stream Size: 1024 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110114/86c84a49/attachment.obj From 6yearold at gmail.com Fri Jan 14 10:20:18 2011 From: 6yearold at gmail.com (arrowdodger) Date: Fri, 14 Jan 2011 19:20:18 +0300 Subject: [llvm-commits] [PATCH][CMake] include/Config/config.h.cmake reorganization. In-Reply-To: <87lj2ncvk1.fsf@wanadoo.es> References: <87lj2ncvk1.fsf@wanadoo.es> Message-ID: On Fri, Jan 14, 2011 at 7:13 PM, ?scar Fuentes wrote: > The following message is a courtesy copy of an article > that has been posted to gmane.comp.compilers.llvm.cvs as well. > > arrowdodger <6yearold-Re5JQEeQqe8AvxtiuMwx3w at public.gmane.org> writes: > > > Here is first part of patch, > > No, it isn't ;-) > > [snip] > I need to put a big red sticker with caption "DO NOT FORGET A PATCH ITSELF!!" on my monitor. Sorry. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110114/868afdf4/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: config.h.cmake.patch Type: text/x-patch Size: 8246 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110114/868afdf4/attachment.bin From rafael.espindola at gmail.com Fri Jan 14 10:36:59 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Fri, 14 Jan 2011 16:36:59 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r123444 - in /llvm-gcc-4.2/trunk/gcc: llvm-backend.cpp llvm-convert.cpp llvm-types.cpp Message-ID: <20110114163659.56BC52A6C12C@llvm.org> Author: rafael Date: Fri Jan 14 10:36:59 2011 New Revision: 123444 URL: http://llvm.org/viewvc/llvm-project?rev=123444&view=rev Log: Add unnamed_addr to as many global variables as possible. This makes sure that llvm-gcc will not be affected by future changes to constant merging. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=123444&r1=123443&r2=123444&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Fri Jan 14 10:36:59 2011 @@ -311,10 +311,11 @@ Constant *LLVMValuesTable = ConstantStruct::get(Context, ValuesForPCH, false); // Create variable to hold this string table. - new GlobalVariable(*TheModule, LLVMValuesTable->getType(), true, - GlobalValue::ExternalLinkage, - LLVMValuesTable, - "llvm.pch.values"); + GlobalVariable *GV = new GlobalVariable(*TheModule, LLVMValuesTable->getType(), + true, GlobalValue::ExternalLinkage, + LLVMValuesTable, + "llvm.pch.values"); + GV->setUnnamedAddr(true); if (TheDebugInfo && TheDebugInfo->getCU().Verify()) { NamedMDNode *NMD = TheModule->getOrInsertNamedMetadata("llvm.dbg.pch.cu"); @@ -866,9 +867,10 @@ } Constant *Array = ConstantArray::get( ArrayType::get(InitList[0]->getType(), InitList.size()), InitList); - new GlobalVariable(*TheModule, Array->getType(), false, - GlobalValue::AppendingLinkage, - Array, Name); + GlobalVariable *GV = new GlobalVariable(*TheModule, Array->getType(), false, + GlobalValue::AppendingLinkage, + Array, Name); + GV->setUnnamedAddr(true); } /// llvm_asm_file_end - Finish the .s file. @@ -948,6 +950,7 @@ GlobalValue *gv = new GlobalVariable(*TheModule, AT, false, GlobalValue::AppendingLinkage, Init, "llvm.used"); + gv->setUnnamedAddr(true); gv->setSection("llvm.metadata"); AttributeUsedGlobals.clear(); } @@ -967,6 +970,7 @@ GlobalValue *gv = new GlobalVariable(*TheModule, AT, false, GlobalValue::AppendingLinkage, Init, "llvm.compiler.used"); + gv->setUnnamedAddr(true); gv->setSection("llvm.metadata"); AttributeCompilerUsedGlobals.clear(); } @@ -980,6 +984,7 @@ GlobalValue *gv = new GlobalVariable(*TheModule, Array->getType(), false, GlobalValue::AppendingLinkage, Array, "llvm.global.annotations"); + gv->setUnnamedAddr(true); gv->setSection("llvm.metadata"); AttributeAnnotateGlobals.clear(); } @@ -1235,6 +1240,7 @@ GlobalVariable::PrivateLinkage, Init, ".str"); GV->setSection("llvm.metadata"); + GV->setUnnamedAddr(true); Slot = GV; return GV; @@ -1313,6 +1319,7 @@ // Set the initializer. GV->setInitializer(Init); + GV->setUnnamedAddr(true); } /// reset_type_and_initializer_llvm - Change the type and initializer for @@ -1333,6 +1340,7 @@ // Temporary to avoid infinite recursion (see comments emit_global_to_llvm) GV->setInitializer(UndefValue::get(GV->getType()->getElementType())); + GV->setUnnamedAddr(true); // Convert the initializer over. Constant *Init = TreeConstantToLLVM::Convert(DECL_INITIAL(decl)); @@ -1347,6 +1355,7 @@ GV->isConstant(), GV->getLinkage(), 0, GV->getName()); + NGV->setUnnamedAddr(true); NGV->setVisibility(GV->getVisibility()); NGV->setSection(GV->getSection()); NGV->setAlignment(GV->getAlignment()); @@ -1360,6 +1369,7 @@ // Set the initializer. GV->setInitializer(Init); + GV->setUnnamedAddr(true); } /// emit_global_to_llvm - Emit the specified VAR_DECL or aggregate CONST_DECL to @@ -1411,6 +1421,7 @@ // this can happen for things like void *G = &G; // GV->setInitializer(UndefValue::get(GV->getType()->getElementType())); + GV->setUnnamedAddr(true); Init = TreeConstantToLLVM::Convert(DECL_INITIAL(decl)); } @@ -1424,6 +1435,7 @@ GV->isConstant(), GlobalValue::ExternalLinkage, 0, GV->getName()); + NGV->setUnnamedAddr(true); GV->replaceAllUsesWith(TheFolder->CreateBitCast(NGV, GV->getType())); changeLLVMConstant(GV, NGV); delete GV; @@ -1433,6 +1445,7 @@ // Set the initializer. GV->setInitializer(Init); + GV->setUnnamedAddr(true); // Set thread local (TLS) if (TREE_CODE(decl) == VAR_DECL && DECL_THREAD_LOCAL_P(decl)) @@ -1734,6 +1747,7 @@ if (Name[0] == 0) { // Global has no name. GV = new GlobalVariable(*TheModule, Ty, false, GlobalValue::ExternalLinkage, 0, ""); + GV->setUnnamedAddr(true); // Check for external weak linkage. if (DECL_EXTERNAL(decl) && DECL_WEAK(decl)) Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=123444&r1=123443&r2=123444&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Fri Jan 14 10:36:59 2011 @@ -2174,6 +2174,7 @@ CatchAll = new GlobalVariable(*TheModule, Init->getType(), true, GlobalVariable::LinkOnceAnyLinkage, Init, "llvm.eh.catch.all.value"); + CatchAll->setUnnamedAddr(true); CatchAll->setSection("llvm.metadata"); AttributeUsedGlobals.insert(CatchAll); } @@ -8747,6 +8748,7 @@ // Create a new complex global. Slot = new GlobalVariable(*TheModule, Init->getType(), true, GlobalVariable::PrivateLinkage, Init, ".cpx"); + Slot->setUnnamedAddr(true); return Slot; } @@ -8781,6 +8783,7 @@ GlobalVariable *GV = new GlobalVariable(*TheModule, Init->getType(), StringIsConstant, Linkage, Init, ".str"); + GV->setUnnamedAddr(true); GV->setAlignment(get_constant_alignment(exp) / 8); if (SlotP) *SlotP = GV; Modified: llvm-gcc-4.2/trunk/gcc/llvm-types.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-types.cpp?rev=123444&r1=123443&r2=123444&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-types.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-types.cpp Fri Jan 14 10:36:59 2011 @@ -208,6 +208,7 @@ GlobalValue::ExternalLinkage, LTypesNameTable, "llvm.pch.types"); + GV->setUnnamedAddr(true); } //===----------------------------------------------------------------------===// From ofv at wanadoo.es Fri Jan 14 10:41:03 2011 From: ofv at wanadoo.es (Oscar Fuentes) Date: Fri, 14 Jan 2011 16:41:03 -0000 Subject: [llvm-commits] [llvm] r123445 - /llvm/trunk/include/llvm/Config/config.h.cmake Message-ID: <20110114164103.38D5D2A6C12C@llvm.org> Author: ofv Date: Fri Jan 14 10:41:03 2011 New Revision: 123445 URL: http://llvm.org/viewvc/llvm-project?rev=123445&view=rev Log: Reorder macros on config.h.cmake to easily compare it against config.h.in. Patch by arrowdodger! Modified: llvm/trunk/include/llvm/Config/config.h.cmake Modified: llvm/trunk/include/llvm/Config/config.h.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=123445&r1=123444&r2=123445&view=diff ============================================================================== --- llvm/trunk/include/llvm/Config/config.h.cmake (original) +++ llvm/trunk/include/llvm/Config/config.h.cmake Fri Jan 14 10:41:03 2011 @@ -1,4 +1,3 @@ - /************************************** ** Created by Kevin from config.h.in ** ***************************************/ @@ -6,36 +5,36 @@ #ifndef CONFIG_H #define CONFIG_H -/* Define if CBE is enabled for printf %a output */ -#cmakedefine ENABLE_CBE_PRINTF_A ${ENABLE_CBE_PRINTF_A} - /* Relative directory for resource files */ #define CLANG_RESOURCE_DIR "${CLANG_RESOURCE_DIR}" -/* Directories clang will search for headers */ -#define C_INCLUDE_DIRS "${C_INCLUDE_DIRS}" +/* 32 bit multilib directory */ +#define CXX_INCLUDE_32BIT_DIR "${CXX_INCLUDE_32BIT_DIR}" -/* Directory clang will search for libstdc++ headers */ -#define CXX_INCLUDE_ROOT "${CXX_INCLUDE_ROOT}" +/* 64 bit multilib directory */ +#define CXX_INCLUDE_64BIT_DIR "${CXX_INCLUDE_64BIT_DIR}" /* Architecture of libstdc++ headers */ #define CXX_INCLUDE_ARCH "${CXX_INCLUDE_ARCH}" -/* 32 bit multilib directory */ -#define CXX_INCLUDE_32BIT_DIR "${CXX_INCLUDE_32BIT_DIR}" +/* Directory clang will search for libstdc++ headers */ +#define CXX_INCLUDE_ROOT "${CXX_INCLUDE_ROOT}" -/* 64 bit multilib directory */ -#define CXX_INCLUDE_64BIT_DIR "${CXX_INCLUDE_64BIT_DIR}" +/* Directories clang will search for headers */ +#define C_INCLUDE_DIRS "${C_INCLUDE_DIRS}" + +/* Define if CBE is enabled for printf %a output */ +#cmakedefine ENABLE_CBE_PRINTF_A ${ENABLE_CBE_PRINTF_A} /* Define if position independent code is enabled */ #cmakedefine ENABLE_PIC -/* Define if timestamp information (e.g., __DATE___) is allowed */ -#cmakedefine ENABLE_TIMESTAMPS ${ENABLE_TIMESTAMPS} - /* Define if threads enabled */ #cmakedefine ENABLE_THREADS ${ENABLE_THREADS} +/* Define if timestamp information (e.g., __DATE___) is allowed */ +#cmakedefine ENABLE_TIMESTAMPS ${ENABLE_TIMESTAMPS} + /* Define to 1 if you have the `argz_append' function. */ #cmakedefine HAVE_ARGZ_APPEND ${HAVE_ARGZ_APPEND} @@ -63,9 +62,6 @@ /* Define to 1 if you have the `bcopy' function. */ #undef HAVE_BCOPY -/* Does not have bi-directional iterator */ -#undef HAVE_BI_ITERATOR - /* Define to 1 if you have the `ceilf' function. */ #cmakedefine HAVE_CEILF ${HAVE_CEILF} @@ -75,6 +71,12 @@ /* Define to 1 if you have the `closedir' function. */ #cmakedefine HAVE_CLOSEDIR ${HAVE_CLOSEDIR} +/* Define to 1 if you have the header file. */ +#undef HAVE_CRASHREPORTERCLIENT_H + +/* Define if __crashreporter_info__ exists. */ +#undef HAVE_CRASHREPORTER_INFO + /* Define to 1 if you have the header file. */ #cmakedefine HAVE_CTYPE_H ${HAVE_CTYPE_H} @@ -124,6 +126,18 @@ /* Define if the neat program is available */ #cmakedefine HAVE_FDP ${HAVE_FDP} +/* Define to 1 if you have the header file. */ +#cmakedefine HAVE_FENV_H ${HAVE_FENV_H} + +/* Define if libffi is available on this platform. */ +#undef HAVE_FFI_CALL + +/* Define to 1 if you have the header file. */ +#undef HAVE_FFI_FFI_H + +/* Define to 1 if you have the header file. */ +#undef HAVE_FFI_H + /* Set to 1 if the finite function is found in */ #cmakedefine HAVE_FINITE_IN_IEEEFP_H ${HAVE_FINITE_IN_IEEEFP_H} @@ -133,9 +147,6 @@ /* Define to 1 if you have the `fmodf' function. */ #cmakedefine HAVE_FMODF ${HAVE_FMODF} -/* Does not have forward iterator */ -#undef HAVE_FWD_ITERATOR - /* Define to 1 if you have the `getcwd' function. */ #cmakedefine HAVE_GETCWD ${HAVE_GETCWD} @@ -151,18 +162,6 @@ /* Define to 1 if you have the `gettimeofday' function. */ #cmakedefine HAVE_GETTIMEOFDAY ${HAVE_GETTIMEOFDAY} -/* Does not have */ -#undef HAVE_GLOBAL_HASH_MAP - -/* Does not have hash_set in global namespace */ -#undef HAVE_GLOBAL_HASH_SET - -/* Does not have ext/hash_map */ -#undef HAVE_GNU_EXT_HASH_MAP - -/* Does not have hash_set in gnu namespace */ -#undef HAVE_GNU_EXT_HASH_SET - /* Define if the Graphviz program is available */ #undef HAVE_GRAPHVIZ @@ -214,6 +213,9 @@ /* Define to 1 if you have the header file. */ #cmakedefine HAVE_LIMITS_H ${HAVE_LIMITS_H} +/* Define if you can use -Wl,-export-dynamic. */ +#define HAVE_LINK_EXPORT_DYNAMIC 1 + /* Define to 1 if you have the header file. */ #cmakedefine HAVE_LINK_H ${HAVE_LINK_H} @@ -270,9 +272,6 @@ /* Define if mmap() can map files into memory */ #undef HAVE_MMAP_FILE -/* define if the compiler implements namespaces */ -#undef HAVE_NAMESPACES - /* Define to 1 if you have the header file, and it defines `DIR'. */ #cmakedefine HAVE_NDIR_H ${HAVE_NDIR_H} @@ -285,12 +284,21 @@ /* Define to 1 if you have the `opendir' function. */ #cmakedefine HAVE_OPENDIR ${HAVE_OPENDIR} +/* Define to 1 if you have the `posix_spawn' function. */ +#cmakedefine HAVE_POSIX_SPAWN ${HAVE_POSIX_SPAWN} + +/* Define to 1 if you have the `powf' function. */ +#cmakedefine HAVE_POWF ${HAVE_POWF} + /* Define if libtool can extract symbol lists from object files. */ #undef HAVE_PRELOADED_SYMBOLS /* Define to have the %a format string */ #undef HAVE_PRINTF_A +/* Have pthread_getspecific */ +#cmakedefine HAVE_PTHREAD_GETSPECIFIC ${HAVE_PTHREAD_GETSPECIFIC} + /* Have pthread.h */ #cmakedefine HAVE_PTHREAD_H ${HAVE_PTHREAD_H} @@ -300,9 +308,6 @@ /* Have pthread_rwlock_init */ #cmakedefine HAVE_PTHREAD_RWLOCK_INIT ${HAVE_PTHREAD_RWLOCK_INIT} -/* Have pthread_getspecific */ -#cmakedefine HAVE_PTHREAD_GETSPECIFIC ${HAVE_PTHREAD_GETSPECIFIC} - /* Define to 1 if srand48/lrand48/drand48 exist in */ #undef HAVE_RAND48 @@ -318,21 +323,18 @@ /* Define to 1 if you have the `rintf' function. */ #undef HAVE_RINTF -/* Define to 1 if you have the `roundf' function. */ -#undef HAVE_ROUNDF - /* Define to 1 if you have the `round' function. */ #cmakedefine HAVE_ROUND ${HAVE_ROUND} +/* Define to 1 if you have the `roundf' function. */ +#undef HAVE_ROUNDF + /* Define to 1 if you have the `sbrk' function. */ #cmakedefine HAVE_SBRK ${HAVE_SBRK} /* Define to 1 if you have the `setenv' function. */ #cmakedefine HAVE_SETENV ${HAVE_SETENV} -/* Define to 1 if you have the `_chsize_s' function. */ -#cmakedefine HAVE__CHSIZE_S ${HAVE__CHSIZE_S} - /* Define to 1 if you have the `setjmp' function. */ #undef HAVE_SETJMP @@ -363,15 +365,15 @@ /* Define to 1 if you have the header file. */ #cmakedefine HAVE_STDLIB_H ${HAVE_STDLIB_H} -/* Does not have ext/hash_map> */ -#undef HAVE_STD_EXT_HASH_MAP - -/* Does not have hash_set in std namespace */ -#undef HAVE_STD_EXT_HASH_SET - /* Set to 1 if the std::isinf function is found in */ #undef HAVE_STD_ISINF_IN_CMATH +/* Define to 1 if you have the `_chsize_s' function. */ +#cmakedefine HAVE__CHSIZE_S ${HAVE__CHSIZE_S} + +/* define if the compiler implements namespaces */ +#undef HAVE_NAMESPACES + /* Set to 1 if the std::isnan function is found in */ #undef HAVE_STD_ISNAN_IN_CMATH @@ -414,6 +416,30 @@ /* Define to 1 if you have the `sysconf' function. */ #undef HAVE_SYSCONF +/* Does not have forward iterator */ +#undef HAVE_FWD_ITERATOR + +/* Does not have bi-directional iterator */ +#undef HAVE_BI_ITERATOR + +/* Does not have */ +#undef HAVE_GLOBAL_HASH_MAP + +/* Does not have hash_set in global namespace */ +#undef HAVE_GLOBAL_HASH_SET + +/* Does not have ext/hash_map */ +#undef HAVE_GNU_EXT_HASH_MAP + +/* Does not have hash_set in gnu namespace */ +#undef HAVE_GNU_EXT_HASH_SET + +/* Does not have ext/hash_map> */ +#undef HAVE_STD_EXT_HASH_MAP + +/* Does not have hash_set in std namespace */ +#undef HAVE_STD_EXT_HASH_SET + /* Define to 1 if you have the header file, and it defines `DIR'. */ #cmakedefine HAVE_SYS_DIR_H ${HAVE_SYS_DIR_H} @@ -470,9 +496,6 @@ /* Define to 1 if you have the header file. */ #cmakedefine HAVE_VALGRIND_VALGRIND_H ${HAVE_VALGRIND_VALGRIND_H} -/* Define to 1 if you have the header file. */ -#cmakedefine HAVE_FENV_H ${HAVE_FENV_H} - /* Define to 1 if you have the header file. */ #cmakedefine HAVE_WINDOWS_H ${HAVE_WINDOWS_H} From ofv at wanadoo.es Fri Jan 14 10:44:44 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Fri, 14 Jan 2011 17:44:44 +0100 Subject: [llvm-commits] [PATCH][CMake] include/Config/config.h.cmake reorganization. In-Reply-To: (arrowdodger's message of "Fri, 14 Jan 2011 19:20:18 +0300") References: <87lj2ncvk1.fsf@wanadoo.es> Message-ID: <87fwsvcu4j.fsf@wanadoo.es> arrowdodger <6yearold at gmail.com> writes: >> > Here is first part of patch, Committed. Thanks. From criswell at cs.uiuc.edu Fri Jan 14 10:58:25 2011 From: criswell at cs.uiuc.edu (John Criswell) Date: Fri, 14 Jan 2011 10:58:25 -0600 Subject: [llvm-commits] CVS: llvm-www/safecode/funding.html people.html Message-ID: <201101141658.p0EGwPvL009584@zion.cs.uiuc.edu> Changes in directory llvm-www/safecode: funding.html updated: 1.1 -> 1.2 people.html updated: 1.6 -> 1.7 --- Log message: Updated the people working on the project. Updated the list of funding. --- Diffs of the changes: (+25 -8) funding.html | 12 ++++++++---- people.html | 21 +++++++++++++++++---- 2 files changed, 25 insertions(+), 8 deletions(-) Index: llvm-www/safecode/funding.html diff -u llvm-www/safecode/funding.html:1.1 llvm-www/safecode/funding.html:1.2 --- llvm-www/safecode/funding.html:1.1 Thu Jun 17 15:14:17 2010 +++ llvm-www/safecode/funding.html Fri Jan 14 10:57:15 2011 @@ -59,15 +59,19 @@
  • + A gift from Apple Computer, Inc. +
  • + +
  • DoD MURI AF Subcontract UCB 00006769: "Hardware, Languages, and Architectures for Defense Against Hostile Operating Systems"
  • - -

    -

    - Thank you for your support! +

  • + IARPA/AFRL Contract# FA8650-10-C-7022 +
  • +


    Index: llvm-www/safecode/people.html diff -u llvm-www/safecode/people.html:1.6 llvm-www/safecode/people.html:1.7 --- llvm-www/safecode/people.html:1.6 Mon May 17 12:22:38 2010 +++ llvm-www/safecode/people.html Fri Jan 14 10:57:15 2011 @@ -56,16 +56,17 @@

    Graduate Students

    • - John Criswell + Arushi Aggarwal
    • - Andrew Lenharth + John Criswell
    • - Haohui Mai + Will Dietz
    • +

    Undergraduate Students

    @@ -73,6 +74,10 @@
  • Brice Lin
  • + +
  • + Matthew Wala +
  • Graduate Student Alumni

    @@ -93,6 +98,14 @@
  • Chris Lattner
  • + +
  • + Andrew Lenharth +
  • + +
  • + Haohui Mai +
  • Undergraduate Student Alumni

    @@ -120,7 +133,7 @@