$ svn mkdir https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_XY $ svn copy https://llvm.org/svn/llvm-project/llvm/branches/release_XY \ - https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_XY/RC1 + https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_XY/rc1 $ svn mkdir https://llvm.org/svn/llvm-project/llvm-gcc-4.2/tags/RELEASE_XY $ svn copy https://llvm.org/svn/llvm-project/llvm-gcc-4.2/branches/release_XY \ - https://llvm.org/svn/llvm-project/llvm-gcc-4.2/tags/RELEASE_XY/RC1 + https://llvm.org/svn/llvm-project/llvm-gcc-4.2/tags/RELEASE_XY/rc1 $ svn mkdir https://llvm.org/svn/llvm-project/test-suite/tags/RELEASE_XY $ svn copy https://llvm.org/svn/llvm-project/test-suite/branches/release_XY \ - https://llvm.org/svn/llvm-project/test-suite/tags/RELEASE_XY/RC1 + https://llvm.org/svn/llvm-project/test-suite/tags/RELEASE_XY/rc1 $ svn mkdir https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_XY $ svn copy https://llvm.org/svn/llvm-project/cfe/branches/release_XY \ - https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_XY/RC1 + https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_XY/rc1@@ -251,10 +251,10 @@
-$ svn export https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_XY/RC1 llvm-X.Yrc1
-$ svn export https://llvm.org/svn/llvm-project/llvm-gcc-4.2/tags/RELEASE_XY/RC1 llvm-gcc4.2-X.Yrc1
-$ svn export https://llvm.org/svn/llvm-project/test-suite/tags/RELEASE_XY/RC1 llvm-test-X.Yrc1
-$ svn export https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_XY/RC1 clang-X.Yrc1
+$ svn export https://llvm.org/svn/llvm-project/llvm/tags/RELEASE_XY/rc1 llvm-X.Yrc1
+$ svn export https://llvm.org/svn/llvm-project/llvm-gcc-4.2/tags/RELEASE_XY/rc1 llvm-gcc4.2-X.Yrc1
+$ svn export https://llvm.org/svn/llvm-project/test-suite/tags/RELEASE_XY/rc1 llvm-test-X.Yrc1
+$ svn export https://llvm.org/svn/llvm-project/cfe/tags/RELEASE_XY/rc1 clang-X.Yrc1
$ tar -czvf - llvm-X.Yrc1 | gzip > llvm-X.Yrc1.src.tar.gz
$ tar -czvf - llvm-test-X.Yrc1 | gzip > llvm-test-X.Yrc1.src.tar.gz
From isanbard at gmail.com Mon Mar 7 01:37:37 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 07 Mar 2011 07:37:37 -0000
Subject: [llvm-commits] [llvm] r127155 -
/llvm/trunk/utils/release/test-release.sh
Message-ID: <20110307073737.62E252A6C12C@llvm.org>
Author: void
Date: Mon Mar 7 01:37:37 2011
New Revision: 127155
URL: http://llvm.org/viewvc/llvm-project?rev=127155&view=rev
Log:
Don't keep the log files around. Just pipe to a log file instead.
Modified:
llvm/trunk/utils/release/test-release.sh
Modified: llvm/trunk/utils/release/test-release.sh
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/release/test-release.sh?rev=127155&r1=127154&r2=127155&view=diff
==============================================================================
--- llvm/trunk/utils/release/test-release.sh (original)
+++ llvm/trunk/utils/release/test-release.sh Mon Mar 7 01:37:37 2011
@@ -12,7 +12,8 @@
#
#===------------------------------------------------------------------------===#
-set -e
+set -e # Exit if any command fails
+set -x # Show commands as they are executed
Release=""
Release_no_dot=""
@@ -33,9 +34,9 @@
echo " -build-dir DIR Directory to perform testing in. [default: pwd]"
echo " -no-checkout Don't checkout the sources from SVN."
echo " -no-64bit Don't test the 64-bit version. [default: yes]"
- echo " -ada Build Ada. [default: no]"
- echo " -disable-objc Disable ObjC build. [default: build]"
- echo " -disable-fortran Disable Fortran build. [default: build]"
+ echo " -enable-ada Build Ada. [default: disable]"
+ echo " -disable-objc Disable ObjC build. [default: enable]"
+ echo " -disable-fortran Disable Fortran build. [default: enable]"
}
while [ $# -gt 0 ]; do
@@ -66,7 +67,7 @@
-no-64bit | --no-64bit )
do_64bit="no"
;;
- -ada | --ada )
+ -enable-ada | --enable-ada )
do_ada="yes"
;;
-disable-objc | --disable-objc )
@@ -118,11 +119,6 @@
llvmCore_srcdir=$BuildDir/llvmCore-$Release-rc$RC.src
llvmgcc42_srcdir=$BuildDir/llvmgcc42-$Release-rc$RC.src
-# Location of log files.
-LogDirName="$Release-rc$RC.logs"
-LogDir=$BuildDir/$LogDirName
-mkdir -p $LogDir
-
# SVN URLs for the sources.
Base_url="http://llvm.org/svn/llvm-project"
llvmCore_RC_url="$Base_url/llvm/tags/RELEASE_$Release_no_dot/rc$RC"
@@ -201,8 +197,7 @@
$llvmCore_srcdir/configure --prefix=$InstallDir \
--enable-optimized=$Optimized \
--enable-assertions=$Assertions \
- --with-llvmgccdir=$llvmgccDir \
- > $LogDir/llvm.configure.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1
+ --with-llvmgccdir=$llvmgccDir
cd -
}
@@ -223,13 +218,11 @@
cd $ObjDir
echo "# Compiling llvm $Release-rc$RC $Flavor"
echo "# make -j $NumJobs VERBOSE=1 $ExtraOpts"
- make -j $NumJobs VERBOSE=1 $ExtraOpts $CompilerFlags \
- > $LogDir/llvm.make.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1
+ make -j $NumJobs VERBOSE=1 $ExtraOpts $CompilerFlags
echo "# Installing llvm $Release-rc$RC $Flavor"
echo "# make install"
- make install \
- > $LogDir/llvm.install.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1
+ make install
cd -
}
@@ -239,12 +232,9 @@
ObjDir="$3"
cd $ObjDir
- make check \
- > $LogDir/llvm.check.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1
- make -C tools/clang test \
- > $LogDir/clang.check.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1
- make unittests \
- > $LogDir/llvm.unittests.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1
+ make check
+ make -C tools/clang test
+ make unittests
cd -
}
@@ -273,8 +263,7 @@
--enable-languages=$languages"
$llvmgcc42_srcdir/configure --prefix=$InstallDir \
--program-prefix=llvm- --enable-llvm=$llvmObjDir \
- --enable-languages=$languages \
- > $LogDir/llvm-gcc.configure.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1
+ --enable-languages=$languages
cd -
}
@@ -292,13 +281,11 @@
cd $ObjDir
echo "# Compiling llvm-gcc $Release-rc$RC $Flavor"
echo "# make -j $NumJobs bootstrap LLVM_VERSION_INFO=$Release"
- make -j $NumJobs bootstrap LLVM_VERSION_INFO=$Release $CompilerFlags \
- > $LogDir/llvm-gcc.make.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1
+ make -j $NumJobs bootstrap LLVM_VERSION_INFO=$Release $CompilerFlags
echo "# Installing llvm-gcc $Release-rc$RC $Flavor"
echo "# make install"
- make install \
- > $LogDir/llvm-gcc.install.$Release-rc$RC-Phase$Phase-$Flavor.log 2>&1
+ make install
cd -
}
@@ -306,7 +293,6 @@
export_sources
fi
-(
Flavors="Debug Release Release+Asserts"
if [ "$do_64bit" = "yes" ]; then
Flavors="$Flavors Release-64"
@@ -390,9 +376,7 @@
echo "# Testing - built with llvmgcc42"
test_llvmCore 2 $Flavor $llvmCore_phase2_objdir
done
-) 2>&1 | tee $LogDir/testing.$Release-rc$RC.log
# Woo hoo!
echo "### Testing Finished ###"
-echo "### Logs: $LogDir"
exit 0
From baldrick at free.fr Mon Mar 7 03:04:01 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 07 Mar 2011 10:04:01 +0100
Subject: [llvm-commits] [llvm] r127138
- /llvm/trunk/lib/Transforms/IPO/Internalize.cpp
In-Reply-To: <20110306234134.4C3A32A6C12C@llvm.org>
References: <20110306234134.4C3A32A6C12C@llvm.org>
Message-ID: <4D749F81.6020908@free.fr>
Hi Rafael,
> Don't internalize available_externally functions. We already did the right
> thing for variables.
testcase?
Ciao, Duncan.
From baldrick at free.fr Mon Mar 7 03:12:24 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 07 Mar 2011 09:12:24 -0000
Subject: [llvm-commits] [llvm] r127156 - /llvm/trunk/docs/LangRef.html
Message-ID: <20110307091224.9C0212A6C12D@llvm.org>
Author: baldrick
Date: Mon Mar 7 03:12:24 2011
New Revision: 127156
URL: http://llvm.org/viewvc/llvm-project?rev=127156&view=rev
Log:
Clarify that the result of an srem is only guaranteed to have the same sign as the
left-hand-side if the result is non-zero.
Modified:
llvm/trunk/docs/LangRef.html
Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=127156&r1=127155&r2=127156&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Mon Mar 7 03:12:24 2011
@@ -3611,9 +3611,10 @@
Semantics:
This instruction returns the remainder of a division (where the result
- has the same sign as the dividend, op1), not the modulo
- operator (where the result has the same sign as the divisor, op2) of
- a value. For more information about the difference,
+ is either zero or has the same sign as the dividend, op1), not the
+ modulo operator (where the result is either zero or has the same sign
+ as the divisor, op2) of a value.
+ For more information about the difference,
see The
Math Forum. For a table of how this is implemented in various languages,
please see
From baldrick at free.fr Mon Mar 7 03:25:12 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 07 Mar 2011 10:25:12 +0100
Subject: [llvm-commits] [llvm] r127063 - in /llvm/trunk:
lib/Transforms/InstCombine/InstCombineCompares.cpp
test/Transforms/InstCombine/icmp.ll
In-Reply-To: <20110305042849.290962A6C12C@llvm.org>
References: <20110305042849.290962A6C12C@llvm.org>
Message-ID: <4D74A478.2010104@free.fr>
Hi Nick,
> + BinaryOperator *SRem = NULL;
> + // icmp Y, (srem X, Y)
> + if (BO0&& BO0->getOpcode() == Instruction::SRem&&
> + Op1 == BO0->getOperand(1))
> + SRem = BO0;
> + // icmp (srem X, Y), Y
> + else if (BO1&& BO1->getOpcode() == Instruction::SRem&&
> + Op0 == BO1->getOperand(1))
> + SRem = BO1;
the two comments seem to be the wrong way round.
Ciao, Duncan.
From justin.holewinski at gmail.com Mon Mar 7 08:32:30 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Mon, 07 Mar 2011 14:32:30 -0000
Subject: [llvm-commits] [llvm] r127157 - /llvm/trunk/lib/VMCore/AsmWriter.cpp
Message-ID: <20110307143230.DDC552A6C12C@llvm.org>
Author: jholewinski
Date: Mon Mar 7 08:32:30 2011
New Revision: 127157
URL: http://llvm.org/viewvc/llvm-project?rev=127157&view=rev
Log:
ptx: Fix calling convention printing in AsmWriter.cpp
This allows LLVM IR using ptx_kernel or ptx_device calling
conventions to be properly printed when emitted in text form.
Modified:
llvm/trunk/lib/VMCore/AsmWriter.cpp
Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=127157&r1=127156&r2=127157&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Mar 7 08:32:30 2011
@@ -1584,8 +1584,8 @@
case CallingConv::ARM_AAPCS: Out << "arm_aapcscc "; break;
case CallingConv::ARM_AAPCS_VFP:Out << "arm_aapcs_vfpcc "; break;
case CallingConv::MSP430_INTR: Out << "msp430_intrcc "; break;
- case CallingConv::PTX_Kernel: Out << "ptx_kernel"; break;
- case CallingConv::PTX_Device: Out << "ptx_device"; break;
+ case CallingConv::PTX_Kernel: Out << "ptx_kernel "; break;
+ case CallingConv::PTX_Device: Out << "ptx_device "; break;
default: Out << "cc" << F->getCallingConv() << " "; break;
}
From baldrick at free.fr Mon Mar 7 08:51:33 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 07 Mar 2011 14:51:33 -0000
Subject: [llvm-commits] [dragonegg] r127158 - /dragonegg/trunk/llvm-types.cpp
Message-ID: <20110307145133.80E9C2A6C12C@llvm.org>
Author: baldrick
Date: Mon Mar 7 08:51:33 2011
New Revision: 127158
URL: http://llvm.org/viewvc/llvm-project?rev=127158&view=rev
Log:
Turn __float128 into fp128 on linux. Giving this a whirl through the
buildbots to see if it breaks the self-host.
Modified:
dragonegg/trunk/llvm-types.cpp
Modified: dragonegg/trunk/llvm-types.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-types.cpp?rev=127158&r1=127157&r2=127158&view=diff
==============================================================================
--- dragonegg/trunk/llvm-types.cpp (original)
+++ dragonegg/trunk/llvm-types.cpp Mon Mar 7 08:51:33 2011
@@ -706,14 +706,9 @@
case 128:
#ifdef TARGET_POWERPC
Ty = SET_TYPE_LLVM(type, Type::getPPC_FP128Ty(Context));
-#elif defined(TARGET_ZARCH) || defined(TARGET_CPU_sparc) // FIXME: Use some generic define.
- // This is for IEEE double extended, e.g. Sparc
- Ty = SET_TYPE_LLVM(type, Type::getFP128Ty(Context));
#else
- // 128-bit long doubles map onto { double, double }.
- Ty = SET_TYPE_LLVM(type,
- StructType::get(Context, Type::getDoubleTy(Context),
- Type::getDoubleTy(Context), NULL));
+ // IEEE quad precision.
+ Ty = SET_TYPE_LLVM(type, Type::getFP128Ty(Context));
#endif
break;
}
From baldrick at free.fr Mon Mar 7 09:56:08 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 07 Mar 2011 15:56:08 -0000
Subject: [llvm-commits] [dragonegg] r127161 - in /dragonegg/trunk:
llvm-convert.cpp llvm-internal.h
Message-ID: <20110307155608.828022A6C12C@llvm.org>
Author: baldrick
Date: Mon Mar 7 09:56:08 2011
New Revision: 127161
URL: http://llvm.org/viewvc/llvm-project?rev=127161&view=rev
Log:
Add a separate routine for turning INTEGER_CST into a constant of register
type. This results in duplicated code, but I plan to transmogrify the
original version into something completely different.
Modified:
dragonegg/trunk/llvm-convert.cpp
dragonegg/trunk/llvm-internal.h
Modified: dragonegg/trunk/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-convert.cpp?rev=127161&r1=127160&r2=127161&view=diff
==============================================================================
--- dragonegg/trunk/llvm-convert.cpp (original)
+++ dragonegg/trunk/llvm-convert.cpp Mon Mar 7 09:56:08 2011
@@ -5881,8 +5881,7 @@
llvm_unreachable("Unhandled GIMPLE constant!");
case INTEGER_CST:
- C = TreeConstantToLLVM::ConvertINTEGER_CST(reg);
- break;
+ return EmitRegisterIntegerConstant(reg);
case REAL_CST:
C = TreeConstantToLLVM::ConvertREAL_CST(reg);
break;
@@ -5905,6 +5904,34 @@
return Mem2Reg(C, TREE_TYPE(reg), *TheFolder);
}
+/// EmitRegisterIntegerConstant - Turn the given INTEGER_CST into an LLVM
+/// constant of the corresponding register type.
+Constant *TreeToLLVM::EmitRegisterIntegerConstant(tree reg) {
+ unsigned Precision = TYPE_PRECISION(TREE_TYPE(reg));
+
+ ConstantInt *CI;
+ if (HOST_BITS_PER_WIDE_INT < integerPartWidth) {
+ assert(2 * HOST_BITS_PER_WIDE_INT <= integerPartWidth &&
+ "Unsupported host integer precision!");
+ unsigned ShiftAmt = HOST_BITS_PER_WIDE_INT;
+ integerPart Val = (integerPart)(unsigned HOST_WIDE_INT)TREE_INT_CST_LOW(reg)
+ + ((integerPart)(unsigned HOST_WIDE_INT)TREE_INT_CST_HIGH(reg) << ShiftAmt);
+ CI = ConstantInt::get(Context, APInt(Precision, Val));
+ } else {
+ assert(HOST_BITS_PER_WIDE_INT == integerPartWidth &&
+ "The engines cannae' take it captain!");
+ integerPart Parts[] = { TREE_INT_CST_LOW(reg), TREE_INT_CST_HIGH(reg) };
+ CI = ConstantInt::get(Context, APInt(Precision, 2, Parts));
+ }
+
+ // The destination can be a pointer, integer or floating point type so we need
+ // a generalized cast here
+ const Type *Ty = GetRegType(TREE_TYPE(reg));
+ Instruction::CastOps opcode = CastInst::getCastOpcode(CI, false, Ty,
+ !TYPE_UNSIGNED(TREE_TYPE(reg)));
+ return TheFolder->CreateCast(opcode, CI, Ty);
+}
+
/// Mem2Reg - Convert a value of in-memory type (that given by ConvertType)
/// to in-register type (that given by GetRegType).
Value *TreeToLLVM::Mem2Reg(Value *V, tree_node *type, LLVMBuilder &Builder) {
Modified: dragonegg/trunk/llvm-internal.h
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/llvm-internal.h?rev=127161&r1=127160&r2=127161&view=diff
==============================================================================
--- dragonegg/trunk/llvm-internal.h (original)
+++ dragonegg/trunk/llvm-internal.h Mon Mar 7 09:56:08 2011
@@ -782,6 +782,10 @@
/// to an LLVM constant. Creates no code, only constants.
Constant *EmitRegisterConstant(tree_node *reg);
+ /// EmitRegisterIntegerConstant - Turn the given INTEGER_CST into an LLVM
+ /// constant of the corresponding register type.
+ Constant *EmitRegisterIntegerConstant(tree_node *reg);
+
/// Mem2Reg - Convert a value of in-memory type (that given by ConvertType)
/// to in-register type (that given by GetRegType). TODO: Eliminate these
/// methods: "memory" values should never be held in registers. Currently
From justin.holewinski at gmail.com Mon Mar 7 10:41:34 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Mon, 7 Mar 2011 11:41:34 -0500
Subject: [llvm-commits] [PATCH] PTX: Add preliminary branch support,
including integer comparison operations involving unsigned integers.
Message-ID:
This patch adds preliminary branch support for the PTX backend. Unsigned
integer comparison is supported, and predicated branches are emitted for
conditional branches.
Che-Liang,
Is this patch okay to commit?
--
Thanks,
Justin Holewinski
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From justin.holewinski at gmail.com Mon Mar 7 11:08:33 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Mon, 7 Mar 2011 12:08:33 -0500
Subject: [llvm-commits] [PATCH] PTX: Add intrinsic support for ntid, ctaid,
and nctaid registers
Message-ID:
This patch adds support for the ntid, ctaid, and nctaid special registers in
the PTX backend.
Che-Liang,
Is this patch okay to commit?
--
Thanks,
Justin Holewinski
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From echristo at apple.com Mon Mar 7 12:26:08 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 7 Mar 2011 10:26:08 -0800
Subject: [llvm-commits] [PATCH] Makefile.rules: [PR9321] "make install"
may install include files along explicit pattern.
In-Reply-To:
References:
Message-ID: <52707747-2CB1-4E5D-A0A4-6D57A2E50047@apple.com>
On Feb 27, 2011, at 8:53 PM, NAKAMURA Takumi wrote:
> ---
> Makefile.rules | 23 ++++++++++++++++++++---
> 1 files changed, 20 insertions(+), 3 deletions(-)
>
> I prefer adding explicit patterns rather than adding exclusive
> patterns, to suppress installing *.cmake.
>
> ...Takumi
> <0002-Makefile.rules-PR9321-make-install-may-install-i.patch.txt>
Can you give me a list of differences in the install before and after this patch please?
-eric
From echristo at apple.com Mon Mar 7 12:26:33 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 7 Mar 2011 10:26:33 -0800
Subject: [llvm-commits] [PATCH] Makefile.rules: [PR9321] "make install"
may install include files along explicit pattern.
In-Reply-To:
References:
Message-ID: <851BA812-CA38-4370-98D1-3BCF941341E7@apple.com>
On Mar 6, 2011, at 8:56 PM, NAKAMURA Takumi wrote:
> Ping.
Responded to the original :)
-eric
From resistor at mac.com Mon Mar 7 12:29:47 2011
From: resistor at mac.com (Owen Anderson)
Date: Mon, 07 Mar 2011 18:29:47 -0000
Subject: [llvm-commits] [llvm] r127163 - in /llvm/trunk:
include/llvm/CodeGen/SelectionDAG.h
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Message-ID: <20110307182947.E3CF22A6C12C@llvm.org>
Author: resistor
Date: Mon Mar 7 12:29:47 2011
New Revision: 127163
URL: http://llvm.org/viewvc/llvm-project?rev=127163&view=rev
Log:
Use the correct LHS type when determining the legalization of a shift's RHS type.
Modified:
llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=127163&r1=127162&r2=127163&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon Mar 7 12:29:47 2011
@@ -438,12 +438,12 @@
SDValue getConvertRndSat(EVT VT, DebugLoc dl, SDValue Val, SDValue DTy,
SDValue STy,
SDValue Rnd, SDValue Sat, ISD::CvtCode Code);
-
+
/// getVectorShuffle - Return an ISD::VECTOR_SHUFFLE node. The number of
/// elements in VT, which must be a vector type, must match the number of
/// mask elements NumElts. A integer mask element equal to -1 is treated as
/// undefined.
- SDValue getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1, SDValue N2,
+ SDValue getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1, SDValue N2,
const int *MaskElts);
/// getSExtOrTrunc - Convert Op, which must be of integer type, to the
@@ -671,10 +671,10 @@
/// getMDNode - Return an MDNodeSDNode which holds an MDNode.
SDValue getMDNode(const MDNode *MD);
-
+
/// getShiftAmountOperand - Return the specified value casted to
/// the target's desired shift amount type.
- SDValue getShiftAmountOperand(SDValue Op);
+ SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op);
/// UpdateNodeOperands - *Mutate* the specified node in-place to have the
/// specified operands. If the resultant node already exists in the DAG,
@@ -901,7 +901,7 @@
SmallVector &GetDbgValues(const SDNode* SD) {
return DbgInfo->getSDDbgValues(SD);
}
-
+
/// TransferDbgValues - Transfer SDDbgValues.
void TransferDbgValues(SDValue From, SDValue To);
@@ -911,11 +911,11 @@
SDDbgInfo::DbgIterator DbgBegin() { return DbgInfo->DbgBegin(); }
SDDbgInfo::DbgIterator DbgEnd() { return DbgInfo->DbgEnd(); }
- SDDbgInfo::DbgIterator ByvalParmDbgBegin() {
- return DbgInfo->ByvalParmDbgBegin();
+ SDDbgInfo::DbgIterator ByvalParmDbgBegin() {
+ return DbgInfo->ByvalParmDbgBegin();
}
- SDDbgInfo::DbgIterator ByvalParmDbgEnd() {
- return DbgInfo->ByvalParmDbgEnd();
+ SDDbgInfo::DbgIterator ByvalParmDbgEnd() {
+ return DbgInfo->ByvalParmDbgEnd();
}
void dump() const;
@@ -972,7 +972,7 @@
/// semantics as an ADD. This handles the equivalence:
/// X|Cst == X+Cst iff X&Cst = 0.
bool isBaseWithConstantOffset(SDValue Op) const;
-
+
/// isKnownNeverNan - Test whether the given SDValue is known to never be NaN.
bool isKnownNeverNaN(SDValue Op) const;
@@ -997,8 +997,8 @@
/// vector op and fill the end of the resulting vector with UNDEFS.
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE = 0);
- /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a
- /// location that is 'Dist' units away from the location that the 'Base' load
+ /// isConsecutiveLoad - Return true if LD is loading 'Bytes' bytes from a
+ /// location that is 'Dist' units away from the location that the 'Base' load
/// is loading from.
bool isConsecutiveLoad(LoadSDNode *LD, LoadSDNode *Base,
unsigned Bytes, int Dist) const;
@@ -1032,7 +1032,7 @@
std::vector ValueTypeNodes;
std::map ExtendedValueTypeNodes;
StringMap ExternalSymbols;
-
+
std::map,SDNode*> TargetExternalSymbols;
};
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=127163&r1=127162&r2=127163&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Mar 7 12:29:47 2011
@@ -948,7 +948,8 @@
// Legalizing shifts/rotates requires adjusting the shift amount
// to the appropriate width.
if (!Ops[1].getValueType().isVector())
- Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[1]));
+ Ops[1] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
+ Ops[1]));
break;
case ISD::SRL_PARTS:
case ISD::SRA_PARTS:
@@ -956,7 +957,8 @@
// Legalizing shifts/rotates requires adjusting the shift amount
// to the appropriate width.
if (!Ops[2].getValueType().isVector())
- Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[2]));
+ Ops[2] = LegalizeOp(DAG.getShiftAmountOperand(Ops[0].getValueType(),
+ Ops[2]));
break;
}
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=127163&r1=127162&r2=127163&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Mon Mar 7 12:29:47 2011
@@ -1418,9 +1418,9 @@
/// getShiftAmountOperand - Return the specified value casted to
/// the target's desired shift amount type.
-SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) {
+SDValue SelectionDAG::getShiftAmountOperand(EVT LHSTy, SDValue Op) {
EVT OpTy = Op.getValueType();
- MVT ShTy = TLI.getShiftAmountTy(OpTy);
+ MVT ShTy = TLI.getShiftAmountTy(LHSTy);
if (OpTy == ShTy || OpTy.isVector()) return Op;
ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
@@ -6314,7 +6314,8 @@
case ISD::ROTL:
case ISD::ROTR:
Scalars.push_back(getNode(N->getOpcode(), dl, EltVT, Operands[0],
- getShiftAmountOperand(Operands[1])));
+ getShiftAmountOperand(Operands[0].getValueType(),
+ Operands[1])));
break;
case ISD::SIGN_EXTEND_INREG:
case ISD::FP_ROUND_INREG: {
From stoklund at 2pi.dk Mon Mar 7 12:56:16 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 07 Mar 2011 18:56:16 -0000
Subject: [llvm-commits] [llvm] r127167 -
/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
Message-ID: <20110307185616.C4B0F2A6C12C@llvm.org>
Author: stoklund
Date: Mon Mar 7 12:56:16 2011
New Revision: 127167
URL: http://llvm.org/viewvc/llvm-project?rev=127167&view=rev
Log:
Handle the special case of registers begin redefined by early-clobber defs.
In this case, the value need to be available at the load index instead of the
normal use index.
Modified:
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=127167&r1=127166&r2=127167&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Mon Mar 7 12:56:16 2011
@@ -779,6 +779,13 @@
if (VNI->isUnused())
continue;
NewLI.addRange(LiveRange(VNI->def, VNI->def.getNextSlot(), VNI));
+
+ // A use tied to an early-clobber def ends at the load slot and isn't caught
+ // above. Catch it here instead. This probably only ever happens for inline
+ // assembly.
+ if (VNI->def.isUse())
+ if (VNInfo *UVNI = li->getVNInfoAt(VNI->def.getLoadIndex()))
+ WorkList.push_back(std::make_pair(VNI->def.getLoadIndex(), UVNI));
}
// Keep track of the PHIs that are in use.
From kledzik at apple.com Mon Mar 7 13:15:15 2011
From: kledzik at apple.com (Nick Kledzik)
Date: Mon, 07 Mar 2011 19:15:15 -0000
Subject: [llvm-commits] [compiler-rt] r127168 -
/compiler-rt/tags/Apple/Libcompiler_rt-11/
Message-ID: <20110307191515.BA7D72A6C12C@llvm.org>
Author: kledzik
Date: Mon Mar 7 13:15:15 2011
New Revision: 127168
URL: http://llvm.org/viewvc/llvm-project?rev=127168&view=rev
Log:
Libcompiler_rt-11
Added:
compiler-rt/tags/Apple/Libcompiler_rt-11/
- copied from r127167, compiler-rt/trunk/
From grosbach at apple.com Mon Mar 7 13:28:43 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 07 Mar 2011 19:28:43 -0000
Subject: [llvm-commits] [llvm] r127169 -
/llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h
Message-ID: <20110307192844.095E82A6C12C@llvm.org>
Author: grosbach
Date: Mon Mar 7 13:28:43 2011
New Revision: 127169
URL: http://llvm.org/viewvc/llvm-project?rev=127169&view=rev
Log:
Tidy up.
Modified:
llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h
Modified: llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h?rev=127169&r1=127168&r2=127169&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineFrameInfo.h Mon Mar 7 13:28:43 2011
@@ -15,7 +15,6 @@
#define LLVM_CODEGEN_MACHINEFRAMEINFO_H
#include "llvm/ADT/SmallVector.h"
-//#include "llvm/ADT/IndexedMap.h"
#include "llvm/Support/DataTypes.h"
#include
#include
From baldrick at free.fr Mon Mar 7 13:38:39 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 07 Mar 2011 19:38:39 -0000
Subject: [llvm-commits] [llvm] r127170 -
/llvm/trunk/include/llvm/ADT/DenseMap.h
Message-ID: <20110307193839.25BA32A6C12C@llvm.org>
Author: baldrick
Date: Mon Mar 7 13:38:38 2011
New Revision: 127170
URL: http://llvm.org/viewvc/llvm-project?rev=127170&view=rev
Log:
Often GCC can see that NumBuckets is zero here, resulting in a warning
about possibly swapped memset parameters. Avoid the warning.
Modified:
llvm/trunk/include/llvm/ADT/DenseMap.h
Modified: llvm/trunk/include/llvm/ADT/DenseMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/DenseMap.h?rev=127170&r1=127169&r2=127170&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/DenseMap.h (original)
+++ llvm/trunk/include/llvm/ADT/DenseMap.h Mon Mar 7 13:38:38 2011
@@ -72,7 +72,8 @@
P->first.~KeyT();
}
#ifndef NDEBUG
- memset(Buckets, 0x5a, sizeof(BucketT)*NumBuckets);
+ if (NumBuckets)
+ memset(Buckets, 0x5a, sizeof(BucketT)*NumBuckets);
#endif
operator delete(Buckets);
}
From rafael.espindola at gmail.com Mon Mar 7 15:28:14 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Mon, 07 Mar 2011 21:28:14 -0000
Subject: [llvm-commits] [llvm] r127172 -
/llvm/trunk/test/Transforms/Internalize/available_externally.ll
Message-ID: <20110307212814.7FC862A6C12C@llvm.org>
Author: rafael
Date: Mon Mar 7 15:28:14 2011
New Revision: 127172
URL: http://llvm.org/viewvc/llvm-project?rev=127172&view=rev
Log:
Add test for r127138.
Added:
llvm/trunk/test/Transforms/Internalize/available_externally.ll
Added: llvm/trunk/test/Transforms/Internalize/available_externally.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Internalize/available_externally.ll?rev=127172&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/Internalize/available_externally.ll (added)
+++ llvm/trunk/test/Transforms/Internalize/available_externally.ll Mon Mar 7 15:28:14 2011
@@ -0,0 +1,16 @@
+; RUN: opt < %s -internalize -internalize-public-api-list foo -S | FileCheck %s
+
+; CHECK: define void @foo
+define void @foo() {
+ ret void
+}
+
+; CHECK: define internal void @zed
+define void @zed() {
+ ret void
+}
+
+; CHECK: define available_externally void @bar
+define available_externally void @bar() {
+ ret void
+}
From rafael.espindola at gmail.com Mon Mar 7 15:39:38 2011
From: rafael.espindola at gmail.com (Rafael Avila de Espindola)
Date: Mon, 07 Mar 2011 16:39:38 -0500
Subject: [llvm-commits] [llvm] r127138
- /llvm/trunk/lib/Transforms/IPO/Internalize.cpp
In-Reply-To: <4D749F81.6020908@free.fr>
References: <20110306234134.4C3A32A6C12C@llvm.org> <4D749F81.6020908@free.fr>
Message-ID: <4D75509A.5020707@gmail.com>
On 11-03-07 04:04 AM, Duncan Sands wrote:
> Hi Rafael,
>
>> Don't internalize available_externally functions. We already did the right
>> thing for variables.
>
> testcase?
Added one in 127172.
> Ciao, Duncan.
Cheers,
Rafael
From zwarich at apple.com Mon Mar 7 15:56:36 2011
From: zwarich at apple.com (Cameron Zwarich)
Date: Mon, 07 Mar 2011 21:56:36 -0000
Subject: [llvm-commits] [llvm] r127175 - in /llvm/trunk:
include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ARM/
lib/Target/CellSPU/ lib/Target/X86/
Message-ID: <20110307215636.CC6822A6C12C@llvm.org>
Author: zwarich
Date: Mon Mar 7 15:56:36 2011
New Revision: 127175
URL: http://llvm.org/viewvc/llvm-project?rev=127175&view=rev
Log:
Move getRegPressureLimit() from TargetLoweringInfo to TargetRegisterInfo.
Modified:
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/lib/CodeGen/MachineLICM.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.h
llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
llvm/trunk/lib/Target/X86/X86RegisterInfo.h
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Mar 7 15:56:36 2011
@@ -190,14 +190,6 @@
return RepRegClassCostForVT[VT.getSimpleVT().SimpleTy];
}
- /// getRegPressureLimit - Return the register pressure "high water mark" for
- /// the specific register class. The scheduler is in high register pressure
- /// mode (for the specific register class) if it goes over the limit.
- virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
- MachineFunction &MF) const {
- return 0;
- }
-
/// isTypeLegal - Return true if the target has native support for the
/// specified value type. This means that it has a register that directly
/// holds it without promotions or expansions.
Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Mon Mar 7 15:56:36 2011
@@ -595,6 +595,14 @@
return NULL;
}
+ /// getRegPressureLimit - Return the register pressure "high water mark" for
+ /// the specific register class. The scheduler is in high register pressure
+ /// mode (for the specific register class) if it goes over the limit.
+ virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const {
+ return 0;
+ }
+
/// getAllocationOrder - Returns the register allocation order for a specified
/// register class in the form of a pair of TargetRegisterClass iterators.
virtual std::pair
Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Mon Mar 7 15:56:36 2011
@@ -294,7 +294,7 @@
RegLimit.resize(NumRC);
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
E = TRI->regclass_end(); I != E; ++I)
- RegLimit[(*I)->getID()] = TLI->getRegPressureLimit(*I, MF);
+ RegLimit[(*I)->getID()] = TRI->getRegPressureLimit(*I, MF);
}
// Get our Loop information...
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Mar 7 15:56:36 2011
@@ -1458,7 +1458,7 @@
std::fill(RegPressure.begin(), RegPressure.end(), 0);
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
E = TRI->regclass_end(); I != E; ++I)
- RegLimit[(*I)->getID()] = tli->getRegPressureLimit(*I, MF);
+ RegLimit[(*I)->getID()] = tri->getRegPressureLimit(*I, MF);
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Mar 7 15:56:36 2011
@@ -348,6 +348,26 @@
return ARM::GPRRegisterClass;
}
+unsigned
+ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const {
+ const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
+
+ switch (RC->getID()) {
+ default:
+ return 0;
+ case ARM::tGPRRegClassID:
+ return TFI->hasFP(MF) ? 4 : 5;
+ case ARM::GPRRegClassID: {
+ unsigned FP = TFI->hasFP(MF) ? 1 : 0;
+ return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
+ }
+ case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
+ case ARM::DPRRegClassID:
+ return 32 - 10;
+ }
+}
+
/// getAllocationOrder - Returns the register allocation order for a specified
/// register class in the form of a pair of TargetRegisterClass iterators.
std::pair
Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Mon Mar 7 15:56:36 2011
@@ -128,6 +128,9 @@
const TargetRegisterClass *getPointerRegClass(unsigned Kind = 0) const;
+ unsigned getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const;
+
std::pair
getAllocationOrder(const TargetRegisterClass *RC,
unsigned HintType, unsigned HintReg,
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Mar 7 15:56:36 2011
@@ -945,27 +945,6 @@
return Sched::RegPressure;
}
-// FIXME: Move to RegInfo
-unsigned
-ARMTargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
- MachineFunction &MF) const {
- const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
-
- switch (RC->getID()) {
- default:
- return 0;
- case ARM::tGPRRegClassID:
- return TFI->hasFP(MF) ? 4 : 5;
- case ARM::GPRRegClassID: {
- unsigned FP = TFI->hasFP(MF) ? 1 : 0;
- return 10 - FP - (Subtarget->isR9Reserved() ? 1 : 0);
- }
- case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
- case ARM::DPRRegClassID:
- return 32 - 10;
- }
-}
-
//===----------------------------------------------------------------------===//
// Lowering Code
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Mar 7 15:56:36 2011
@@ -329,9 +329,6 @@
Sched::Preference getSchedulingPreference(SDNode *N) const;
- unsigned getRegPressureLimit(const TargetRegisterClass *RC,
- MachineFunction &MF) const;
-
bool isShuffleMaskLegal(const SmallVectorImpl &M, EVT VT) const;
bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Mon Mar 7 15:56:36 2011
@@ -183,14 +183,6 @@
virtual bool isLegalAddressingMode(const AddrMode &AM,
const Type *Ty) const;
-
- /// After allocating this many registers, the allocator should feel
- /// register pressure. The value is a somewhat random guess, based on the
- /// number of non callee saved registers in the C calling convention.
- virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC,
- MachineFunction &MF) const{
- return 50;
- }
};
}
Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h Mon Mar 7 15:56:36 2011
@@ -46,6 +46,14 @@
virtual const TargetRegisterClass *
getPointerRegClass(unsigned Kind = 0) const;
+ /// After allocating this many registers, the allocator should feel
+ /// register pressure. The value is a somewhat random guess, based on the
+ /// number of non callee saved registers in the C calling convention.
+ virtual unsigned getRegPressureLimit( const TargetRegisterClass *RC,
+ MachineFunction &MF) const{
+ return 50;
+ }
+
//! Return the array of callee-saved registers
virtual const unsigned* getCalleeSavedRegs(const MachineFunction *MF) const;
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Mar 7 15:56:36 2011
@@ -1271,27 +1271,6 @@
return std::make_pair(RRC, Cost);
}
-// FIXME: Why this routine is here? Move to RegInfo!
-unsigned
-X86TargetLowering::getRegPressureLimit(const TargetRegisterClass *RC,
- MachineFunction &MF) const {
- const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
-
- unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
- switch (RC->getID()) {
- default:
- return 0;
- case X86::GR32RegClassID:
- return 4 - FPDiff;
- case X86::GR64RegClassID:
- return 12 - FPDiff;
- case X86::VR128RegClassID:
- return Subtarget->is64Bit() ? 10 : 4;
- case X86::VR64RegClassID:
- return 4;
- }
-}
-
bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
unsigned &Offset) const {
if (!Subtarget->isTargetLinux())
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Mon Mar 7 15:56:36 2011
@@ -677,9 +677,6 @@
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;
- unsigned getRegPressureLimit(const TargetRegisterClass *RC,
- MachineFunction &MF) const;
-
/// getStackCookieLocation - Return true if the target stores stack
/// protector cookies at a fixed offset in some non-standard address
/// space, and populates the address space and offset as
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Mar 7 15:56:36 2011
@@ -340,6 +340,26 @@
return NULL;
}
+unsigned
+X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const {
+ const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
+
+ unsigned FPDiff = TFI->hasFP(MF) ? 1 : 0;
+ switch (RC->getID()) {
+ default:
+ return 0;
+ case X86::GR32RegClassID:
+ return 4 - FPDiff;
+ case X86::GR64RegClassID:
+ return 12 - FPDiff;
+ case X86::VR128RegClassID:
+ return TM.getSubtarget().is64Bit() ? 10 : 4;
+ case X86::VR64RegClassID:
+ return 4;
+ }
+}
+
const unsigned *
X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
bool callsEHReturn = false;
Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=127175&r1=127174&r2=127175&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Mon Mar 7 15:56:36 2011
@@ -101,6 +101,9 @@
const TargetRegisterClass *
getCrossCopyRegClass(const TargetRegisterClass *RC) const;
+ unsigned getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const;
+
/// getCalleeSavedRegs - Return a null-terminated list of all of the
/// callee-save registers on this target.
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
From aggarwa4 at illinois.edu Mon Mar 7 16:25:46 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 07 Mar 2011 22:25:46 -0000
Subject: [llvm-commits] [poolalloc] r127178 -
/poolalloc/trunk/test/dsa/types/mrv.ll
Message-ID: <20110307222546.CD9072A6C12C@llvm.org>
Author: aggarwa4
Date: Mon Mar 7 16:25:46 2011
New Revision: 127178
URL: http://llvm.org/viewvc/llvm-project?rev=127178&view=rev
Log:
An example of a case where we loose type information,
due to calling conventions.
Added:
poolalloc/trunk/test/dsa/types/mrv.ll
Added: poolalloc/trunk/test/dsa/types/mrv.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/mrv.ll?rev=127178&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/types/mrv.ll (added)
+++ poolalloc/trunk/test/dsa/types/mrv.ll Mon Mar 7 16:25:46 2011
@@ -0,0 +1,60 @@
+; ModuleID = 'mrv.o'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:s:0,0:float|double::4:float::8:float
+
+; Function foo, actually accepts an object of struct S. But as
+; per calling conventions, the value is passed in registers, after
+; conversion to a float and a double.
+; See http://lists.cs.uiuc.edu/pipermail/llvmdev/2010-January/028986.html
+
+%0 = type { double, float }
+%struct.S = type { float, float, float }
+
+define void @_Z3foo1S(double %obj.0, float %obj.1) nounwind {
+entry:
+ %obj_addr = alloca %struct.S ; <%struct.S*> [#uses=3]
+ %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
+ %0 = bitcast %struct.S* %obj_addr to %0* ; <%0*> [#uses=1]
+ %1 = getelementptr inbounds %0* %0, i32 0, i32 0 ; [#uses=1]
+ store double %obj.0, double* %1
+ %2 = bitcast %struct.S* %obj_addr to %0* ; <%0*> [#uses=1]
+ %3 = getelementptr inbounds %0* %2, i32 0, i32 1 ; [#uses=1]
+ store float %obj.1, float* %3
+ %4 = getelementptr inbounds %struct.S* %obj_addr, i32 0, i32 0 ; [#uses=1]
+ store float 0x3FF3333340000000, float* %4, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define i32 @main() nounwind {
+entry:
+ %retval = alloca i32 ; [#uses=2]
+ %0 = alloca i32 ; [#uses=2]
+ %s = alloca %struct.S ; <%struct.S*> [#uses=5]
+ %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
+ %1 = getelementptr inbounds %struct.S* %s, i32 0, i32 0 ; [#uses=1]
+ store float 1.000000e+00, float* %1, align 4
+ %2 = getelementptr inbounds %struct.S* %s, i32 0, i32 1 ; [#uses=1]
+ store float 1.000000e+00, float* %2, align 4
+ %3 = getelementptr inbounds %struct.S* %s, i32 0, i32 2 ; [#uses=1]
+ store float 1.000000e+00, float* %3, align 4
+ %4 = bitcast %struct.S* %s to %0* ; <%0*> [#uses=1]
+ %elt = getelementptr inbounds %0* %4, i32 0, i32 0 ; [#uses=1]
+ %val = load double* %elt ; [#uses=1]
+ %5 = bitcast %struct.S* %s to %0* ; <%0*> [#uses=1]
+ %elt1 = getelementptr inbounds %0* %5, i32 0, i32 1 ; [#uses=1]
+ %val2 = load float* %elt1 ; [#uses=1]
+ call void @_Z3foo1S(double %val, float %val2) nounwind
+ store i32 0, i32* %0, align 4
+ %6 = load i32* %0, align 4 ; [#uses=1]
+ store i32 %6, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %entry
+ %retval3 = load i32* %retval ; [#uses=1]
+ ret i32 %retval3
+}
From aggarwa4 at illinois.edu Mon Mar 7 16:42:08 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 07 Mar 2011 22:42:08 -0000
Subject: [llvm-commits] [poolalloc] r127180 -
/poolalloc/trunk/test/dsa/types/mrv1.ll
Message-ID: <20110307224208.B94892A6C12C@llvm.org>
Author: aggarwa4
Date: Mon Mar 7 16:42:08 2011
New Revision: 127180
URL: http://llvm.org/viewvc/llvm-project?rev=127180&view=rev
Log:
Similiar to mrv, but shows transform for a return
value.
Added:
poolalloc/trunk/test/dsa/types/mrv1.ll
Added: poolalloc/trunk/test/dsa/types/mrv1.ll
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/types/mrv1.ll?rev=127180&view=auto
==============================================================================
--- poolalloc/trunk/test/dsa/types/mrv1.ll (added)
+++ poolalloc/trunk/test/dsa/types/mrv1.ll Mon Mar 7 16:42:08 2011
@@ -0,0 +1,125 @@
+;similiar to mrv.ll. Also shows conversion for return values.
+
+; ModuleID = 'mrv.o'
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-unknown-linux-gnu"
+
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:s:0,0:float|double::4:float::8:float
+;RUN: dsaopt %s -dsa-local -analyze -check-type=main:s1:0,0:float::4:float::8:float
+
+%0 = type { double, float }
+%struct.S = type { float, float, float }
+
+define void @_Z3foo1S(double %obj.0, float %obj.1) nounwind {
+entry:
+ %obj_addr = alloca %struct.S ; <%struct.S*> [#uses=3]
+ %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
+ %0 = bitcast %struct.S* %obj_addr to %0* ; <%0*> [#uses=1]
+ %1 = getelementptr inbounds %0* %0, i32 0, i32 0 ; [#uses=1]
+ store double %obj.0, double* %1
+ %2 = bitcast %struct.S* %obj_addr to %0* ; <%0*> [#uses=1]
+ %3 = getelementptr inbounds %0* %2, i32 0, i32 1 ; [#uses=1]
+ store float %obj.1, float* %3
+ %4 = getelementptr inbounds %struct.S* %obj_addr, i32 0, i32 0 ; [#uses=1]
+ store float 0x3FF3333340000000, float* %4, align 4
+ br label %return
+
+return: ; preds = %entry
+ ret void
+}
+
+define %0 @_Z3barv() nounwind {
+entry:
+ %retval = alloca %struct.S ; <%struct.S*> [#uses=4]
+ %0 = alloca %struct.S ; <%struct.S*> [#uses=6]
+ %obj = alloca %struct.S ; <%struct.S*> [#uses=4]
+ %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
+ %1 = getelementptr inbounds %struct.S* %obj, i32 0, i32 0 ; [#uses=1]
+ store float 0x3FF3333340000000, float* %1, align 4
+ %2 = getelementptr inbounds %struct.S* %0, i32 0, i32 0 ; [#uses=1]
+ %3 = getelementptr inbounds %struct.S* %obj, i32 0, i32 0 ; [#uses=1]
+ %4 = load float* %3, align 4 ; [#uses=1]
+ store float %4, float* %2, align 4
+ %5 = getelementptr inbounds %struct.S* %0, i32 0, i32 1 ; [#uses=1]
+ %6 = getelementptr inbounds %struct.S* %obj, i32 0, i32 1 ; [#uses=1]
+ %7 = load float* %6, align 4 ; [#uses=1]
+ store float %7, float* %5, align 4
+ %8 = getelementptr inbounds %struct.S* %0, i32 0, i32 2 ; [#uses=1]
+ %9 = getelementptr inbounds %struct.S* %obj, i32 0, i32 2 ; [#uses=1]
+ %10 = load float* %9, align 4 ; [#uses=1]
+ store float %10, float* %8, align 4
+ %11 = getelementptr inbounds %struct.S* %retval, i32 0, i32 0 ; [#uses=1]
+ %12 = getelementptr inbounds %struct.S* %0, i32 0, i32 0 ; [#uses=1]
+ %13 = load float* %12, align 4 ; [#uses=1]
+ store float %13, float* %11, align 4
+ %14 = getelementptr inbounds %struct.S* %retval, i32 0, i32 1 ; [#uses=1]
+ %15 = getelementptr inbounds %struct.S* %0, i32 0, i32 1 ; [#uses=1]
+ %16 = load float* %15, align 4 ; [#uses=1]
+ store float %16, float* %14, align 4
+ %17 = getelementptr inbounds %struct.S* %retval, i32 0, i32 2 ; [#uses=1]
+ %18 = getelementptr inbounds %struct.S* %0, i32 0, i32 2 ; [#uses=1]
+ %19 = load float* %18, align 4 ; [#uses=1]
+ store float %19, float* %17, align 4
+ br label %return
+
+return: ; preds = %entry
+ %retval1 = bitcast %struct.S* %retval to %0* ; <%0*> [#uses=2]
+ %mrv_gep = getelementptr %0* %retval1, i32 0, i32 0 ; [#uses=1]
+ %mrv = load double* %mrv_gep ; [#uses=1]
+ %mrv_gep2 = getelementptr %0* %retval1, i32 0, i32 1 ; [#uses=1]
+ %mrv3 = load float* %mrv_gep2 ; [#uses=1]
+ %mrv4 = insertvalue %0 undef, double %mrv, 0 ; <%0> [#uses=1]
+ %mrv5 = insertvalue %0 %mrv4, float %mrv3, 1 ; <%0> [#uses=1]
+ ret %0 %mrv5
+}
+
+define i32 @main() nounwind {
+entry:
+ %retval = alloca i32 ; [#uses=2]
+ %0 = alloca i32 ; [#uses=2]
+ %s = alloca %struct.S ; <%struct.S*> [#uses=5]
+ %s1 = alloca %struct.S ; <%struct.S*> [#uses=3]
+ %memtmp = alloca %0 ; <%0*> [#uses=3]
+ %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
+ %1 = getelementptr inbounds %struct.S* %s, i32 0, i32 0 ; [#uses=1]
+ store float 1.000000e+00, float* %1, align 4
+ %2 = getelementptr inbounds %struct.S* %s, i32 0, i32 1 ; [#uses=1]
+ store float 1.000000e+00, float* %2, align 4
+ %3 = getelementptr inbounds %struct.S* %s, i32 0, i32 2 ; [#uses=1]
+ store float 1.000000e+00, float* %3, align 4
+ %4 = bitcast %struct.S* %s to %0* ; <%0*> [#uses=1]
+ %elt = getelementptr inbounds %0* %4, i32 0, i32 0 ; [#uses=1]
+ %val = load double* %elt ; [#uses=1]
+ %5 = bitcast %struct.S* %s to %0* ; <%0*> [#uses=1]
+ %elt1 = getelementptr inbounds %0* %5, i32 0, i32 1 ; [#uses=1]
+ %val2 = load float* %elt1 ; [#uses=1]
+ call void @_Z3foo1S(double %val, float %val2) nounwind
+ %6 = call %0 @_Z3barv() nounwind ; <%0> [#uses=2]
+ %mrv_gep = getelementptr inbounds %0* %memtmp, i32 0, i32 0 ; [#uses=1]
+ %mrv_gr = extractvalue %0 %6, 0 ; [#uses=1]
+ store double %mrv_gr, double* %mrv_gep
+ %mrv_gep3 = getelementptr inbounds %0* %memtmp, i32 0, i32 1 ; [#uses=1]
+ %mrv_gr4 = extractvalue %0 %6, 1 ; [#uses=1]
+ store float %mrv_gr4, float* %mrv_gep3
+ %memtmp5 = bitcast %0* %memtmp to %struct.S* ; <%struct.S*> [#uses=3]
+ %7 = getelementptr inbounds %struct.S* %s1, i32 0, i32 0 ; [#uses=1]
+ %8 = getelementptr inbounds %struct.S* %memtmp5, i32 0, i32 0 ; [#uses=1]
+ %9 = load float* %8, align 4 ; [#uses=1]
+ store float %9, float* %7, align 4
+ %10 = getelementptr inbounds %struct.S* %s1, i32 0, i32 1 ; [#uses=1]
+ %11 = getelementptr inbounds %struct.S* %memtmp5, i32 0, i32 1 ; [#uses=1]
+ %12 = load float* %11, align 4 ; [#uses=1]
+ store float %12, float* %10, align 4
+ %13 = getelementptr inbounds %struct.S* %s1, i32 0, i32 2 ; [#uses=1]
+ %14 = getelementptr inbounds %struct.S* %memtmp5, i32 0, i32 2 ; [#uses=1]
+ %15 = load float* %14, align 4 ; [#uses=1]
+ store float %15, float* %13, align 4
+ store i32 0, i32* %0, align 4
+ %16 = load i32* %0, align 4 ; [#uses=1]
+ store i32 %16, i32* %retval, align 4
+ br label %return
+
+return: ; preds = %entry
+ %retval6 = load i32* %retval ; [#uses=1]
+ ret i32 %retval6
+}
From stoklund at 2pi.dk Mon Mar 7 16:42:16 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 07 Mar 2011 22:42:16 -0000
Subject: [llvm-commits] [llvm] r127181 - in /llvm/trunk/lib/CodeGen:
InlineSpiller.cpp LiveRangeEdit.cpp LiveRangeEdit.h RegAllocGreedy.cpp
Message-ID: <20110307224216.651802A6C12C@llvm.org>
Author: stoklund
Date: Mon Mar 7 16:42:16 2011
New Revision: 127181
URL: http://llvm.org/viewvc/llvm-project?rev=127181&view=rev
Log:
Make the UselessRegs argument optional in the LiveRangeEdit constructor.
Modified:
llvm/trunk/lib/CodeGen/InlineSpiller.cpp
llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
llvm/trunk/lib/CodeGen/LiveRangeEdit.h
llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=127181&r1=127180&r2=127181&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Mon Mar 7 16:42:16 2011
@@ -333,7 +333,7 @@
void InlineSpiller::spill(LiveInterval *li,
SmallVectorImpl &newIntervals,
const SmallVectorImpl &spillIs) {
- LiveRangeEdit edit(*li, newIntervals, spillIs);
+ LiveRangeEdit edit(*li, newIntervals, &spillIs);
spill(edit);
if (VerifySpills)
mf_.verify(&pass_, "After inline spill");
Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp?rev=127181&r1=127180&r2=127181&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp Mon Mar 7 16:42:16 2011
@@ -75,9 +75,10 @@
if (MO.isDef())
return false;
// We cannot depend on virtual registers in uselessRegs_.
- for (unsigned ui = 0, ue = uselessRegs_.size(); ui != ue; ++ui)
- if (uselessRegs_[ui]->reg == MO.getReg())
- return false;
+ if (uselessRegs_)
+ for (unsigned ui = 0, ue = uselessRegs_->size(); ui != ue; ++ui)
+ if ((*uselessRegs_)[ui]->reg == MO.getReg())
+ return false;
LiveInterval &li = lis.getInterval(MO.getReg());
const VNInfo *OVNI = li.getVNInfoAt(OrigIdx);
Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.h?rev=127181&r1=127180&r2=127181&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeEdit.h (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeEdit.h Mon Mar 7 16:42:16 2011
@@ -31,7 +31,7 @@
class LiveRangeEdit {
LiveInterval &parent_;
SmallVectorImpl &newRegs_;
- const SmallVectorImpl &uselessRegs_;
+ const SmallVectorImpl *uselessRegs_;
/// firstNew_ - Index of the first register added to newRegs_.
const unsigned firstNew_;
@@ -66,7 +66,7 @@
/// rematerializing values because they are about to be removed.
LiveRangeEdit(LiveInterval &parent,
SmallVectorImpl &newRegs,
- const SmallVectorImpl &uselessRegs)
+ const SmallVectorImpl *uselessRegs = 0)
: parent_(parent), newRegs_(newRegs), uselessRegs_(uselessRegs),
firstNew_(newRegs.size()), scannedRemattable_(false) {}
@@ -87,7 +87,7 @@
/// anyRematerializable - Return true if any parent values may be
/// rematerializable.
- /// This function must be called before ny rematerialization is attempted.
+ /// This function must be called before any rematerialization is attempted.
bool anyRematerializable(LiveIntervals&, const TargetInstrInfo&,
AliasAnalysis*);
Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=127181&r1=127180&r2=127181&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Mar 7 16:42:16 2011
@@ -601,8 +601,7 @@
SmallVector InterferenceRanges;
mapGlobalInterference(PhysReg, InterferenceRanges);
- SmallVector SpillRegs;
- LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
+ LiveRangeEdit LREdit(VirtReg, NewVRegs);
SE->reset(LREdit);
// Create the main cross-block interval.
@@ -1130,8 +1129,7 @@
<< '-' << Uses[BestAfter] << ", " << BestDiff
<< ", " << (BestAfter - BestBefore + 1) << " instrs\n");
- SmallVector SpillRegs;
- LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
+ LiveRangeEdit LREdit(VirtReg, NewVRegs);
SE->reset(LREdit);
SE->openIntv();
@@ -1183,8 +1181,7 @@
if (Stage < RS_Block) {
SplitAnalysis::BlockPtrSet Blocks;
if (SA->getMultiUseBlocks(Blocks)) {
- SmallVector SpillRegs;
- LiveRangeEdit LREdit(VirtReg, NewVRegs, SpillRegs);
+ LiveRangeEdit LREdit(VirtReg, NewVRegs);
SE->reset(LREdit);
SE->splitSingleBlocks(Blocks);
setStage(NewVRegs.begin(), NewVRegs.end(), RS_Block);
From dpatel at apple.com Mon Mar 7 16:43:45 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 07 Mar 2011 22:43:45 -0000
Subject: [llvm-commits] [llvm] r127182 - in /llvm/trunk:
lib/Transforms/Scalar/LoopIdiomRecognize.cpp
test/Transforms/LoopIdiom/debug-line.ll
Message-ID: <20110307224345.99C852A6C12C@llvm.org>
Author: dpatel
Date: Mon Mar 7 16:43:45 2011
New Revision: 127182
URL: http://llvm.org/viewvc/llvm-project?rev=127182&view=rev
Log:
Preserve line no. info.
Radar 9097659
Added:
llvm/trunk/test/Transforms/LoopIdiom/debug-line.ll
Modified:
llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp?rev=127182&r1=127181&r2=127182&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp Mon Mar 7 16:43:45 2011
@@ -493,7 +493,7 @@
Value *NumBytes =
Expander.expandCodeFor(NumBytesS, IntPtr, Preheader->getTerminator());
- Value *NewCall;
+ CallInst *NewCall;
if (SplatValue)
NewCall = Builder.CreateMemSet(BasePtr, SplatValue,NumBytes,StoreAlignment);
else {
@@ -517,7 +517,7 @@
DEBUG(dbgs() << " Formed memset: " << *NewCall << "\n"
<< " from store to: " << *Ev << " at: " << *TheStore << "\n");
- (void)NewCall;
+ NewCall->setDebugLoc(TheStore->getDebugLoc());
// Okay, the memset has been formed. Zap the original store and anything that
// feeds into it.
Added: llvm/trunk/test/Transforms/LoopIdiom/debug-line.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopIdiom/debug-line.ll?rev=127182&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopIdiom/debug-line.ll (added)
+++ llvm/trunk/test/Transforms/LoopIdiom/debug-line.ll Mon Mar 7 16:43:45 2011
@@ -0,0 +1,49 @@
+; RUN: opt -loop-idiom < %s -S | FileCheck %s
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+target triple = "x86_64-apple-darwin10.0.0"
+
+
+define void @foo(double* nocapture %a) nounwind ssp {
+entry:
+ tail call void @llvm.dbg.value(metadata !{double* %a}, i64 0, metadata !5), !dbg !8
+ tail call void @llvm.dbg.value(metadata !9, i64 0, metadata !10), !dbg !14
+ br label %for.body
+
+for.body: ; preds = %entry, %for.body
+ %indvar = phi i64 [ 0, %entry ], [ %indvar.next, %for.body ]
+ %arrayidx = getelementptr double* %a, i64 %indvar
+; CHECK: call void @llvm.memset{{.+}} !dbg
+ store double 0.000000e+00, double* %arrayidx, align 8, !dbg !15
+ %indvar.next = add i64 %indvar, 1
+ %exitcond = icmp ne i64 %indvar.next, 1000
+ br i1 %exitcond, label %for.body, label %for.end, !dbg !14
+
+for.end: ; preds = %for.body
+ tail call void @llvm.dbg.value(metadata !{null}, i64 0, metadata !10), !dbg !16
+ ret void, !dbg !17
+}
+
+declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
+
+declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
+
+!llvm.dbg.sp = !{!0}
+
+!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (double*)* @foo} ; [ DW_TAG_subprogram ]
+!1 = metadata !{i32 589865, metadata !"li.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ]
+!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"li.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 127165:127174)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!4 = metadata !{null}
+!5 = metadata !{i32 590081, metadata !0, metadata !"a", metadata !1, i32 16777218, metadata !6, i32 0} ; [ DW_TAG_arg_variable ]
+!6 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ]
+!7 = metadata !{i32 589860, metadata !2, metadata !"double", null, i32 0, i64 64, i64 64, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ]
+!8 = metadata !{i32 2, i32 18, metadata !0, null}
+!9 = metadata !{i32 0}
+!10 = metadata !{i32 590080, metadata !11, metadata !"i", metadata !1, i32 3, metadata !13, i32 0} ; [ DW_TAG_auto_variable ]
+!11 = metadata !{i32 589835, metadata !12, i32 3, i32 3, metadata !1, i32 1} ; [ DW_TAG_lexical_block ]
+!12 = metadata !{i32 589835, metadata !0, i32 2, i32 21, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
+!13 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!14 = metadata !{i32 3, i32 3, metadata !12, null}
+!15 = metadata !{i32 4, i32 5, metadata !11, null}
+!16 = metadata !{i32 3, i32 29, metadata !11, null}
+!17 = metadata !{i32 5, i32 1, metadata !12, null}
From echristo at apple.com Mon Mar 7 16:48:16 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 07 Mar 2011 22:48:16 -0000
Subject: [llvm-commits] [llvm] r127186 -
/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
Message-ID: <20110307224816.D9B322A6C12C@llvm.org>
Author: echristo
Date: Mon Mar 7 16:48:16 2011
New Revision: 127186
URL: http://llvm.org/viewvc/llvm-project?rev=127186&view=rev
Log:
Typos.
Modified:
llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=127186&r1=127185&r2=127186&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Mon Mar 7 16:48:16 2011
@@ -356,7 +356,7 @@
void removePred(const SDep &D);
/// getDepth - Return the depth of this node, which is the length of the
- /// maximum path up to any node with has no predecessors.
+ /// maximum path up to any node which has no predecessors.
unsigned getDepth() const {
if (!isDepthCurrent)
const_cast(this)->ComputeDepth();
@@ -364,7 +364,7 @@
}
/// getHeight - Return the height of this node, which is the length of the
- /// maximum path down to any node with has no successors.
+ /// maximum path down to any node which has no successors.
unsigned getHeight() const {
if (!isHeightCurrent)
const_cast(this)->ComputeHeight();
From isanbard at gmail.com Mon Mar 7 16:49:03 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 07 Mar 2011 22:49:03 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r127187 -
/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
Message-ID: <20110307224903.8C2872A6C12C@llvm.org>
Author: void
Date: Mon Mar 7 16:49:03 2011
New Revision: 127187
URL: http://llvm.org/viewvc/llvm-project?rev=127187&view=rev
Log:
When we adjust the inline ASM type, we need to take into account an early
clobber with the 'y' constraint. Otherwise, we get the wrong return type and an
assert, because it created a '<1 x i64>' vector type instead of the x86_mmx
type.
Modified:
llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=127187&r1=127186&r2=127187&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Mon Mar 7 16:49:03 2011
@@ -45,10 +45,11 @@
/* For parameters to an asm, check the constraint and use X86_mmx if an MMX
register is called for. "y" means an MMX register. */
-#define LLVM_ADJUST_MMX_INLINE_PARAMETER_TYPE(Constraint, LLVMTy) \
- ((TARGET_MMX && \
- StringRef(Constraint).equals(StringRef(std::string("y")))) ? \
- Type::getX86_MMXTy(Context) : LLVMTy)
+#define LLVM_ADJUST_MMX_INLINE_PARAMETER_TYPE(Constraint, LLVMTy) \
+ ((TARGET_MMX && \
+ (StringRef(Constraint).equals(StringRef(std::string("y"))) || \
+ StringRef(Constraint).equals(StringRef(std::string("&y"))))) ? \
+ Type::getX86_MMXTy(Context) : LLVMTy)
/* LLVM specific stuff for supporting calling convention output */
#define TARGET_ADJUST_LLVM_CC(CC, type) \
From fvbommel at gmail.com Mon Mar 7 17:04:12 2011
From: fvbommel at gmail.com (Frits van Bommel)
Date: Tue, 8 Mar 2011 00:04:12 +0100
Subject: [llvm-commits] [llvm-gcc-4.2] r127187 -
/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
In-Reply-To: <20110307224903.8C2872A6C12C@llvm.org>
References: <20110307224903.8C2872A6C12C@llvm.org>
Message-ID:
On Mon, Mar 7, 2011 at 11:49 PM, Bill Wendling wrote:
> ?/* For parameters to an asm, check the constraint and use X86_mmx if an MMX
> ? ?register is called for. ?"y" means an MMX register. */
> -#define LLVM_ADJUST_MMX_INLINE_PARAMETER_TYPE(Constraint, LLVMTy) \
> - ?((TARGET_MMX && ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> - ? ?StringRef(Constraint).equals(StringRef(std::string("y")))) ? ?\
> - ? ?Type::getX86_MMXTy(Context) : LLVMTy)
> +#define LLVM_ADJUST_MMX_INLINE_PARAMETER_TYPE(Constraint, LLVMTy) ? ? ? \
> + ?((TARGET_MMX && ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? \
> + ? ?(StringRef(Constraint).equals(StringRef(std::string("y"))) || ? ? ? \
> + ? ? StringRef(Constraint).equals(StringRef(std::string("&y"))))) ? ? ? \
> + ? Type::getX86_MMXTy(Context) : LLVMTy)
What's the point of using horrible expressions like
'(StringRef(Constraint).equals(StringRef(std::string("y")))' instead
of, say, '(StringRef(Constraint) == "y")'?
From isanbard at gmail.com Mon Mar 7 17:06:24 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 7 Mar 2011 15:06:24 -0800
Subject: [llvm-commits] [llvm-gcc-4.2] r127187 -
/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
In-Reply-To:
References: <20110307224903.8C2872A6C12C@llvm.org>
Message-ID:
On Mar 7, 2011, at 3:04 PM, Frits van Bommel wrote:
> On Mon, Mar 7, 2011 at 11:49 PM, Bill Wendling wrote:
>> /* For parameters to an asm, check the constraint and use X86_mmx if an MMX
>> register is called for. "y" means an MMX register. */
>> -#define LLVM_ADJUST_MMX_INLINE_PARAMETER_TYPE(Constraint, LLVMTy) \
>> - ((TARGET_MMX && \
>> - StringRef(Constraint).equals(StringRef(std::string("y")))) ? \
>> - Type::getX86_MMXTy(Context) : LLVMTy)
>> +#define LLVM_ADJUST_MMX_INLINE_PARAMETER_TYPE(Constraint, LLVMTy) \
>> + ((TARGET_MMX && \
>> + (StringRef(Constraint).equals(StringRef(std::string("y"))) || \
>> + StringRef(Constraint).equals(StringRef(std::string("&y"))))) ? \
>> + Type::getX86_MMXTy(Context) : LLVMTy)
>
> What's the point of using horrible expressions like
> '(StringRef(Constraint).equals(StringRef(std::string("y")))' instead
> of, say, '(StringRef(Constraint) == "y")'?
Obfuscation? :-)
I'll change it.
-bw
From david_dean at apple.com Mon Mar 7 17:12:59 2011
From: david_dean at apple.com (David Dean)
Date: Mon, 07 Mar 2011 23:12:59 -0000
Subject: [llvm-commits] [zorg] r127189 -
/zorg/trunk/zorg/buildbot/builders/LLVMGCCBuilder.py
Message-ID: <20110307231259.437182A6C12C@llvm.org>
Author: ddean
Date: Mon Mar 7 17:12:59 2011
New Revision: 127189
URL: http://llvm.org/viewvc/llvm-project?rev=127189&view=rev
Log:
Final tweak/fix for uploading artifacts in LLVMGCCBuilder.py
Modified:
zorg/trunk/zorg/buildbot/builders/LLVMGCCBuilder.py
Modified: zorg/trunk/zorg/buildbot/builders/LLVMGCCBuilder.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/zorg/buildbot/builders/LLVMGCCBuilder.py?rev=127189&r1=127188&r2=127189&view=diff
==============================================================================
--- zorg/trunk/zorg/buildbot/builders/LLVMGCCBuilder.py (original)
+++ zorg/trunk/zorg/buildbot/builders/LLVMGCCBuilder.py Mon Mar 7 17:12:59 2011
@@ -277,8 +277,7 @@
f.addStep(ShellCommand(name='pkg.tar',
description="tar root",
command=["tar", "zcvf", name, "./"],
- workdir=WithProperties(os.path.join(obj_path, "%s.roots" % project,
- "%s~dst" % project)),
+ workdir=obj_path,
warnOnFailure=True,
flunkOnFailure=False,
haltOnFailure=False))
From isanbard at gmail.com Mon Mar 7 17:20:37 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 07 Mar 2011 23:20:37 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r127190 -
/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
Message-ID: <20110307232038.025A02A6C12C@llvm.org>
Author: void
Date: Mon Mar 7 17:20:37 2011
New Revision: 127190
URL: http://llvm.org/viewvc/llvm-project?rev=127190&view=rev
Log:
Simplification that Fritz pointed out.
Modified:
llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
Modified: llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h?rev=127190&r1=127189&r2=127190&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h (original)
+++ llvm-gcc-4.2/trunk/gcc/config/i386/llvm-i386-target.h Mon Mar 7 17:20:37 2011
@@ -45,10 +45,9 @@
/* For parameters to an asm, check the constraint and use X86_mmx if an MMX
register is called for. "y" means an MMX register. */
-#define LLVM_ADJUST_MMX_INLINE_PARAMETER_TYPE(Constraint, LLVMTy) \
- ((TARGET_MMX && \
- (StringRef(Constraint).equals(StringRef(std::string("y"))) || \
- StringRef(Constraint).equals(StringRef(std::string("&y"))))) ? \
+#define LLVM_ADJUST_MMX_INLINE_PARAMETER_TYPE(Constraint, LLVMTy) \
+ ((TARGET_MMX && \
+ (StringRef(Constraint) == "y" || StringRef(Constraint) == "&y")) ? \
Type::getX86_MMXTy(Context) : LLVMTy)
/* LLVM specific stuff for supporting calling convention output */
From stoklund at 2pi.dk Mon Mar 7 17:29:10 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 07 Mar 2011 23:29:10 -0000
Subject: [llvm-commits] [llvm] r127192 - in /llvm/trunk:
include/llvm/CodeGen/LiveIntervalAnalysis.h
lib/CodeGen/LiveIntervalAnalysis.cpp
Message-ID: <20110307232910.4376C2A6C12C@llvm.org>
Author: stoklund
Date: Mon Mar 7 17:29:10 2011
New Revision: 127192
URL: http://llvm.org/viewvc/llvm-project?rev=127192&view=rev
Log:
Let shrinkToUses optionally return a list of now dead machine instructions.
Modified:
llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
Modified: llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h?rev=127192&r1=127191&r2=127192&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h (original)
+++ llvm/trunk/include/llvm/CodeGen/LiveIntervalAnalysis.h Mon Mar 7 17:29:10 2011
@@ -159,7 +159,9 @@
/// range to just the remaining uses. This method does not compute reaching
/// defs for new uses, and it doesn't remove dead defs.
/// Dead PHIDef values are marked as unused.
- void shrinkToUses(LiveInterval *li);
+ /// New dead machine instructions are added to the dead vector.
+ void shrinkToUses(LiveInterval *li,
+ SmallVectorImpl *dead = 0);
// Interval removal
Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=127192&r1=127191&r2=127192&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Mon Mar 7 17:29:10 2011
@@ -746,7 +746,8 @@
/// shrinkToUses - After removing some uses of a register, shrink its live
/// range to just the remaining uses. This method does not compute reaching
/// defs for new uses, and it doesn't remove dead defs.
-void LiveIntervals::shrinkToUses(LiveInterval *li) {
+void LiveIntervals::shrinkToUses(LiveInterval *li,
+ SmallVectorImpl *dead) {
DEBUG(dbgs() << "Shrink: " << *li << '\n');
assert(TargetRegisterInfo::isVirtualRegister(li->reg)
&& "Can't only shrink physical registers");
@@ -852,6 +853,10 @@
MachineInstr *MI = getInstructionFromIndex(VNI->def);
assert(MI && "No instruction defining live value");
MI->addRegisterDead(li->reg, tri_);
+ if (dead && MI->allDefsAreDead()) {
+ DEBUG(dbgs() << "All defs dead: " << *MI);
+ dead->push_back(MI);
+ }
}
}
From isanbard at gmail.com Mon Mar 7 17:38:41 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 07 Mar 2011 23:38:41 -0000
Subject: [llvm-commits] [llvm] r127193 - in /llvm/trunk:
lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrFormats.td
lib/Target/ARM/ARMInstrNEON.td lib/Target/ARM/ARMMCCodeEmitter.cpp
test/MC/ARM/neon-shift-encoding.s utils/TableGen/EDEmitter.cpp
Message-ID: <20110307233841.8C6BE2A6C12C@llvm.org>
Author: void
Date: Mon Mar 7 17:38:41 2011
New Revision: 127193
URL: http://llvm.org/viewvc/llvm-project?rev=127193&view=rev
Log:
Rename the narrow shift right immediate operands to "shr_imm*" operands. Also
expand the testing of the narrowing shift right instructions.
No functionality change.
Modified:
llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
llvm/trunk/test/MC/ARM/neon-shift-encoding.s
llvm/trunk/utils/TableGen/EDEmitter.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=127193&r1=127192&r2=127193&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon Mar 7 17:38:41 2011
@@ -312,11 +312,13 @@
unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
- unsigned getNarrowShiftRight16Imm(const MachineInstr &MI, unsigned Op)
+ unsigned getShiftRight8Imm(const MachineInstr &MI, unsigned Op)
const { return 0; }
- unsigned getNarrowShiftRight32Imm(const MachineInstr &MI, unsigned Op)
+ unsigned getShiftRight16Imm(const MachineInstr &MI, unsigned Op)
const { return 0; }
- unsigned getNarrowShiftRight64Imm(const MachineInstr &MI, unsigned Op)
+ unsigned getShiftRight32Imm(const MachineInstr &MI, unsigned Op)
+ const { return 0; }
+ unsigned getShiftRight64Imm(const MachineInstr &MI, unsigned Op)
const { return 0; }
/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=127193&r1=127192&r2=127193&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Mar 7 17:38:41 2011
@@ -221,20 +221,25 @@
let PrintMethod = "printNegZeroOperand";
}
-// Narrow Shift Right Immediate - A narrow shift right immediate is encoded
-// differently from other shift immediates. The imm6 field is encoded like so:
+// Shift Right Immediate - A shift right immediate is encoded differently from
+// other shift immediates. The imm6 field is encoded like so:
//
-// 16-bit: imm6<5:3> = '001', 8 - is encded in imm6<2:0>
-// 32-bit: imm6<5:4> = '01',16 - is encded in imm6<3:0>
-// 64-bit: imm6<5> = '1', 32 - is encded in imm6<4:0>
-def nsr16_imm : Operand {
- let EncoderMethod = "getNarrowShiftRight16Imm";
+// Offset Encoding
+// 8 imm6<5:3> = '001', 8 - is encoded in imm6<2:0>
+// 16 imm6<5:4> = '01', 16 - is encoded in imm6<3:0>
+// 32 imm6<5> = '1', 32 - is encoded in imm6<4:0>
+// 64 64 - is encoded in imm6<5:0>
+def shr_imm8 : Operand {
+ let EncoderMethod = "getShiftRight8Imm";
}
-def nsr32_imm : Operand {
- let EncoderMethod = "getNarrowShiftRight32Imm";
+def shr_imm16 : Operand {
+ let EncoderMethod = "getShiftRight16Imm";
}
-def nsr64_imm : Operand {
- let EncoderMethod = "getNarrowShiftRight64Imm";
+def shr_imm32 : Operand {
+ let EncoderMethod = "getShiftRight32Imm";
+}
+def shr_imm64 : Operand {
+ let EncoderMethod = "getShiftRight64Imm";
}
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=127193&r1=127192&r2=127193&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Mon Mar 7 17:38:41 2011
@@ -3154,17 +3154,17 @@
SDNode OpNode> {
def v8i8 : N2VNSh {
+ v8i8, v8i16, shr_imm8, OpNode> {
let Inst{21-19} = 0b001; // imm6 = 001xxx
}
def v4i16 : N2VNSh {
+ v4i16, v4i32, shr_imm16, OpNode> {
let Inst{21-20} = 0b01; // imm6 = 01xxxx
}
def v2i32 : N2VNSh {
+ v2i32, v2i64, shr_imm32, OpNode> {
let Inst{21} = 0b1; // imm6 = 1xxxxx
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=127193&r1=127192&r2=127193&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon Mar 7 17:38:41 2011
@@ -278,12 +278,14 @@
unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op,
SmallVectorImpl &Fixups) const;
- unsigned getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl &Fixups) const;
- unsigned getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl &Fixups) const;
- unsigned getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl &Fixups) const;
+ unsigned getShiftRight8Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl &Fixups) const;
+ unsigned getShiftRight16Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl &Fixups) const;
+ unsigned getShiftRight32Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl &Fixups) const;
+ unsigned getShiftRight64Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl &Fixups) const;
unsigned NEONThumb2DataIPostEncoder(const MCInst &MI,
unsigned EncodedValue) const;
@@ -1209,23 +1211,29 @@
}
unsigned ARMMCCodeEmitter::
-getNarrowShiftRight16Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl &Fixups) const {
+getShiftRight8Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl &Fixups) const {
return 8 - MI.getOperand(Op).getImm();
}
unsigned ARMMCCodeEmitter::
-getNarrowShiftRight32Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl &Fixups) const {
+getShiftRight16Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl &Fixups) const {
return 16 - MI.getOperand(Op).getImm();
}
unsigned ARMMCCodeEmitter::
-getNarrowShiftRight64Imm(const MCInst &MI, unsigned Op,
- SmallVectorImpl &Fixups) const {
+getShiftRight32Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl &Fixups) const {
return 32 - MI.getOperand(Op).getImm();
}
+unsigned ARMMCCodeEmitter::
+getShiftRight64Imm(const MCInst &MI, unsigned Op,
+ SmallVectorImpl &Fixups) const {
+ return 64 - MI.getOperand(Op).getImm();
+}
+
void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl &Fixups) const {
Modified: llvm/trunk/test/MC/ARM/neon-shift-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/neon-shift-encoding.s?rev=127193&r1=127192&r2=127193&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/neon-shift-encoding.s (original)
+++ llvm/trunk/test/MC/ARM/neon-shift-encoding.s Mon Mar 7 17:38:41 2011
@@ -158,5 +158,10 @@
vrshrn.i32 d16, q8, #16
@ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2]
vrshrn.i64 d16, q8, #32
+
+@ CHECK: vqrshrn.s16 d16, q8, #4 @ encoding: [0x70,0x09,0xcc,0xf2]
+ vqrshrn.s16 d16, q8, #4
@ CHECK: vqrshrn.s32 d16, q8, #13 @ encoding: [0x70,0x09,0xd3,0xf2]
vqrshrn.s32 d16, q8, #13
+@ CHECK: vqrshrn.s64 d16, q8, #13 @ encoding: [0x70,0x09,0xf3,0xf2]
+ vqrshrn.s64 d16, q8, #13
Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=127193&r1=127192&r2=127193&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/EDEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Mar 7 17:38:41 2011
@@ -598,9 +598,10 @@
IMM("t2adrlabel");
IMM("shift_imm");
IMM("neon_vcvt_imm32");
- IMM("nsr16_imm");
- IMM("nsr32_imm");
- IMM("nsr64_imm");
+ IMM("shr_imm8");
+ IMM("shr_imm16");
+ IMM("shr_imm32");
+ IMM("shr_imm64");
MISC("brtarget", "kOperandTypeARMBranchTarget"); // ?
MISC("uncondbrtarget", "kOperandTypeARMBranchTarget"); // ?
From geek4civic at gmail.com Mon Mar 7 18:16:49 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 8 Mar 2011 09:16:49 +0900
Subject: [llvm-commits] [PATCH] Makefile.rules: [PR9321] "make install"
may install include files along explicit pattern.
In-Reply-To: <52707747-2CB1-4E5D-A0A4-6D57A2E50047@apple.com>
References:
<52707747-2CB1-4E5D-A0A4-6D57A2E50047@apple.com>
Message-ID:
Eric,
> Can you give me a list of differences in the install before and after this patch please?
It suppresses installing 4 files below;
include/llvm/CMakeLists.txt
include/llvm/Config/config.h.cmake
include/llvm/Config/llvm-config.h.cmake
include/llvm/Support/DataTypes.h.cmake
It is rather an issue PR2928 than PR9321.
Bug 2928 - make install shall ignore *.cmake files. (edit)
...Takumi
From echristo at apple.com Mon Mar 7 18:42:51 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 7 Mar 2011 16:42:51 -0800
Subject: [llvm-commits] [PATCH] Makefile.rules: [PR9321] "make install"
may install include files along explicit pattern.
In-Reply-To:
References:
<52707747-2CB1-4E5D-A0A4-6D57A2E50047@apple.com>
Message-ID: <1F5D2477-118D-406A-A70D-BB78E8CE0DC6@apple.com>
On Mar 7, 2011, at 4:16 PM, NAKAMURA Takumi wrote:
> Eric,
>
>> Can you give me a list of differences in the install before and after this patch please?
>
> It suppresses installing 4 files below;
> include/llvm/CMakeLists.txt
> include/llvm/Config/config.h.cmake
> include/llvm/Config/llvm-config.h.cmake
> include/llvm/Support/DataTypes.h.cmake
>
> It is rather an issue PR2928 than PR9321.
> Bug 2928 - make install shall ignore *.cmake files. (edit)
OK then. Just wanted to make sure you did a find -print and diffed the results between the two runs.
-eric
From joerg at britannica.bec.de Mon Mar 7 18:56:18 2011
From: joerg at britannica.bec.de (Joerg Sonnenberger)
Date: Tue, 8 Mar 2011 01:56:18 +0100
Subject: [llvm-commits] [PATCH] Makefile.rules: [PR9321] "make install"
may install include files along explicit pattern.
In-Reply-To:
References:
Message-ID: <20110308005618.GA30857@britannica.bec.de>
On Mon, Feb 28, 2011 at 01:53:07PM +0900, NAKAMURA Takumi wrote:
> diff --git a/Makefile.rules b/Makefile.rules
> index c0a9112..94d2e2c 100644
> --- a/Makefile.rules
> +++ b/Makefile.rules
> @@ -2139,8 +2139,13 @@ install-local::
> $(Verb) $(MKDIR) $(DESTDIR)$(PROJ_includedir)
> $(Verb) if test -d "$(PROJ_SRC_ROOT)/include" ; then \
> cd $(PROJ_SRC_ROOT)/include && \
> - for hdr in `find . -type f '!' '(' -name '*~' \
> - -o -name '.#*' -o -name '*.in' ')' -print | grep -v CVS | \
> + for hdr in `find . -type f '(' \
> + -name LICENSE.TXT \
> + -or -name '*.def' \
> + -or -name '*.h' \
> + -or -name '*.inc' \
> + -or -name '*.td' \
> + ')' -print | grep -v CVS | \
> grep -v .svn` ; do \
> instdir=`dirname "$(DESTDIR)$(PROJ_includedir)/$$hdr"` ; \
> if test \! -d "$$instdir" ; then \
> @@ -2153,7 +2158,19 @@ install-local::
> ifneq ($(PROJ_SRC_ROOT),$(PROJ_OBJ_ROOT))
> $(Verb) if test -d "$(PROJ_OBJ_ROOT)/include" ; then \
> cd $(PROJ_OBJ_ROOT)/include && \
> - for hdr in `find . -type f -print | grep -v CVS` ; do \
> + for hdr in `find . -type f '(' \
> + -name LICENSE.TXT \
> + -or -name '*.def' \
> + -or -name '*.h' \
> + -or -name '*.inc' \
> + -or -name '*.td' \
> + ')' -print | grep -v CVS | \
> + grep -v .svn` ; do \
> + instdir=`dirname "$(DESTDIR)$(PROJ_includedir)/$$hdr"` ; \
> + if test \! -d "$$instdir" ; then \
> + $(EchoCmd) Making install directory $$instdir ; \
> + $(MKDIR) $$instdir ;\
> + fi ; \
> $(DataInstall) $$hdr $(DESTDIR)$(PROJ_includedir)/$$hdr ; \
> done ; \
> fi
Same here too -- SUS says the syntax is "-o", not "-or". Please also
merge the grep calls using ! '(' -path '*/CVS/*' -o -path '*/.svn/*'
')'. The find ... | while read hdr ideom is IMO more readable too and
doesn't force the shell to read all names at once.
Joerg
From aggarwa4 at illinois.edu Mon Mar 7 19:10:47 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 08 Mar 2011 01:10:47 -0000
Subject: [llvm-commits] [poolalloc] r127196 -
/poolalloc/trunk/lib/DSA/DataStructureStats.cpp
Message-ID: <20110308011047.A9DB52A6C12C@llvm.org>
Author: aggarwa4
Date: Mon Mar 7 19:10:47 2011
New Revision: 127196
URL: http://llvm.org/viewvc/llvm-project?rev=127196&view=rev
Log:
We must also count InsesrtValue and ExtractValue Instructions
in evaluation of DS Statistics.
Modified:
poolalloc/trunk/lib/DSA/DataStructureStats.cpp
Modified: poolalloc/trunk/lib/DSA/DataStructureStats.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructureStats.cpp?rev=127196&r1=127195&r2=127196&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructureStats.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructureStats.cpp Mon Mar 7 19:10:47 2011
@@ -74,6 +74,8 @@
void visitLoad(LoadInst &LI);
void visitStore(StoreInst &SI);
+ void visitInsertValue(InsertValueInst &I);
+ void visitExtractValue(ExtractValueInst &I);
/// Debugging support methods
void print(llvm::raw_ostream &O, const Module* = 0) const { }
@@ -215,6 +217,21 @@
}
}
+void DSGraphStats::visitInsertValue(InsertValueInst &I) {
+ if (isNodeForValueUntyped(I.getAggregateOperand(), I.getParent()->getParent())) {
+ NumUntypedMemAccesses++;
+ } else {
+ NumTypedMemAccesses++;
+ }
+}
+
+void DSGraphStats::visitExtractValue(ExtractValueInst &I) {
+ if (isNodeForValueUntyped(I.getAggregateOperand(), I.getParent()->getParent())) {
+ NumUntypedMemAccesses++;
+ } else {
+ NumTypedMemAccesses++;
+ }
+}
bool DSGraphStats::runOnFunction(Function& F) {
From geek4civic at gmail.com Mon Mar 7 19:17:32 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 8 Mar 2011 10:17:32 +0900
Subject: [llvm-commits] [PATCH] Makefile.rules: [PR9321] "make install"
may install include files along explicit pattern.
In-Reply-To: <20110308005618.GA30857@britannica.bec.de>
References:
<20110308005618.GA30857@britannica.bec.de>
Message-ID:
Good morning, Joerg.
On Tue, Mar 8, 2011 at 9:56 AM, Joerg Sonnenberger
wrote:
> Same here too -- SUS says the syntax is "-o", not "-or".
I know, I will commit the stuff to modify "-or" to "-o", thank you. :)
> Please also
> merge the grep calls using ! '(' -path '*/CVS/*' -o -path '*/.svn/*'
> ')'. The find ... | while read hdr ideom is IMO more readable too and
> doesn't force the shell to read all names at once.
I prefer your suggestion, though, I would not be confident to modify
these scheme.
...Takumi
From bob.wilson at apple.com Mon Mar 7 19:17:16 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 08 Mar 2011 01:17:16 -0000
Subject: [llvm-commits] [llvm] r127197 -
/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20110308011716.95FB12A6C12C@llvm.org>
Author: bwilson
Date: Mon Mar 7 19:17:16 2011
New Revision: 127197
URL: http://llvm.org/viewvc/llvm-project?rev=127197&view=rev
Log:
Fix comment typos.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=127197&r1=127196&r2=127197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Mar 7 19:17:16 2011
@@ -2691,8 +2691,8 @@
// If one of the operand is zero, it's safe to ignore the NaN case since
// we only care about equality comparisons.
(SeenZero || (DAG.isKnownNeverNaN(LHS) && DAG.isKnownNeverNaN(RHS)))) {
- // If unsafe fp math optimization is enabled and there are no othter uses of
- // the CMP operands, and the condition code is EQ oe NE, we can optimize it
+ // If unsafe fp math optimization is enabled and there are no other uses of
+ // the CMP operands, and the condition code is EQ or NE, we can optimize it
// to an integer comparison.
if (CC == ISD::SETOEQ)
CC = ISD::SETEQ;
From bob.wilson at apple.com Mon Mar 7 19:17:20 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 08 Mar 2011 01:17:20 -0000
Subject: [llvm-commits] [llvm] r127198 - in /llvm/trunk:
lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h
test/CodeGen/ARM/select.ll
Message-ID: <20110308011720.97FD02A6C12D@llvm.org>
Author: bwilson
Date: Mon Mar 7 19:17:20 2011
New Revision: 127198
URL: http://llvm.org/viewvc/llvm-project?rev=127198&view=rev
Log:
Fix a compiler crash where a Glue value had multiple uses. Radar 9049552.
Modified:
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.h
llvm/trunk/test/CodeGen/ARM/select.ll
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=127198&r1=127197&r2=127198&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Mar 7 19:17:20 2011
@@ -2527,6 +2527,27 @@
return DAG.getNode(ARMISD::FMSTAT, dl, MVT::Glue, Cmp);
}
+/// duplicateCmp - Glue values can have only one use, so this function
+/// duplicates a comparison node.
+SDValue
+ARMTargetLowering::duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const {
+ unsigned Opc = Cmp.getOpcode();
+ DebugLoc DL = Cmp.getDebugLoc();
+ if (Opc == ARMISD::CMP || Opc == ARMISD::CMPZ)
+ return DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
+
+ assert(Opc == ARMISD::FMSTAT && "unexpected comparison operation");
+ Cmp = Cmp.getOperand(0);
+ Opc = Cmp.getOpcode();
+ if (Opc == ARMISD::CMPFP)
+ Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0),Cmp.getOperand(1));
+ else {
+ assert(Opc == ARMISD::CMPFPw0 && "unexpected operand of FMSTAT");
+ Cmp = DAG.getNode(Opc, DL, MVT::Glue, Cmp.getOperand(0));
+ }
+ return DAG.getNode(ARMISD::FMSTAT, DL, MVT::Glue, Cmp);
+}
+
SDValue ARMTargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
SDValue Cond = Op.getOperand(0);
SDValue SelectTrue = Op.getOperand(1);
@@ -2562,7 +2583,7 @@
EVT VT = Cond.getValueType();
SDValue ARMcc = Cond.getOperand(2);
SDValue CCR = Cond.getOperand(3);
- SDValue Cmp = Cond.getOperand(4);
+ SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG);
return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp);
}
}
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=127198&r1=127197&r2=127198&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Mon Mar 7 19:17:20 2011
@@ -459,6 +459,7 @@
SDValue &ARMcc, SelectionDAG &DAG, DebugLoc dl) const;
SDValue getVFPCmp(SDValue LHS, SDValue RHS,
SelectionDAG &DAG, DebugLoc dl) const;
+ SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Modified: llvm/trunk/test/CodeGen/ARM/select.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select.ll?rev=127198&r1=127197&r2=127198&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select.ll Mon Mar 7 19:17:20 2011
@@ -90,3 +90,26 @@
%tmp1 = select i1 %tmp, float 0x3FF3BE76C0000000, float 0x40030E9A20000000
ret float %tmp1
}
+
+;
+; Glue values can only have a single use, but the following test exposed a
+; case where a SELECT was lowered with 2 uses of a comparison, causing the
+; scheduler to assert.
+; CHECK-VFP: f9:
+
+declare i8* @objc_msgSend(i8*, i8*, ...)
+define void @f9() optsize {
+entry:
+ %cmp = icmp eq i8* undef, inttoptr (i32 4 to i8*)
+ %conv191 = select i1 %cmp, float -3.000000e+00, float 0.000000e+00
+ %conv195 = select i1 %cmp, double -1.000000e+00, double 0.000000e+00
+ %add = fadd double %conv195, 1.100000e+01
+ %conv196 = fptrunc double %add to float
+ %add201 = fadd float undef, %conv191
+ %tmp484 = bitcast float %conv196 to i32
+ %tmp478 = bitcast float %add201 to i32
+ %tmp490 = insertvalue [2 x i32] undef, i32 %tmp484, 0
+ %tmp493 = insertvalue [2 x i32] %tmp490, i32 %tmp478, 1
+ call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, [2 x i32], i32, float)*)(i8* undef, i8* undef, [2 x i32] %tmp493, i32 0, float 1.000000e+00) optsize
+ ret void
+}
From aggarwa4 at illinois.edu Mon Mar 7 19:27:06 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 08 Mar 2011 01:27:06 -0000
Subject: [llvm-commits] [poolalloc] r127199 - in /poolalloc/trunk:
include/dsa/DSNode.h lib/DSA/DataStructure.cpp
Message-ID: <20110308012706.4B07E2A6C12C@llvm.org>
Author: aggarwa4
Date: Mon Mar 7 19:27:06 2011
New Revision: 127199
URL: http://llvm.org/viewvc/llvm-project?rev=127199&view=rev
Log:
Added a utility function to get all the values
associated with a DSNode.
Removed dead code.
Modified:
poolalloc/trunk/include/dsa/DSNode.h
poolalloc/trunk/lib/DSA/DataStructure.cpp
Modified: poolalloc/trunk/include/dsa/DSNode.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/DSNode.h?rev=127199&r1=127198&r2=127199&view=diff
==============================================================================
--- poolalloc/trunk/include/dsa/DSNode.h (original)
+++ poolalloc/trunk/include/dsa/DSNode.h Mon Mar 7 19:27:06 2011
@@ -241,7 +241,6 @@
void mergeTypeInfo(const Type *Ty, unsigned Offset);
void mergeTypeInfo(const TyMapTy::mapped_type TyIt, unsigned Offset);
void mergeTypeInfo(const DSNode* D, unsigned Offset);
- void mergeArrayTypeInfo(const DSNode* D);
// Types records might exist without types in them
bool hasNoType() {
@@ -328,6 +327,9 @@
globals_iterator globals_begin() const { return Globals.begin(); }
globals_iterator globals_end() const { return Globals.end(); }
+ /// addValueList - Compute a full set of values that are represented by
+ /// this node. High overhead method.
+ void addValueList(std::vector &List) const;
/// maskNodeTypes - Apply a mask to the node types bitfield.
///
Modified: poolalloc/trunk/lib/DSA/DataStructure.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructure.cpp?rev=127199&r1=127198&r2=127199&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructure.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructure.cpp Mon Mar 7 19:27:06 2011
@@ -272,6 +272,15 @@
return isCollapsedNode();
}
+void DSNode::addValueList(std::vector &List) const {
+ DSScalarMap &SN = getParentGraph()->getScalarMap();
+ for(DSScalarMap::const_iterator I = SN.begin(), E = SN.end(); I!= E; I++) {
+ if(SN[I->first].getNode() == this){
+ //I->first->dump();
+ }
+
+ }
+}
/// addFullGlobalsList - Compute the full set of global values that are
/// represented by this node. Unlike getGlobalsList(), this requires fair
/// amount of work to compute, so don't treat this method call as free.
@@ -446,13 +455,6 @@
mergeTypeInfo(ii->second, ii->first + Offset);
}
-void DSNode::mergeArrayTypeInfo(const DSNode* DN) {
- unsigned Offset = 0;
- while(Offset < getSize()) {
- mergeTypeInfo(DN, Offset);
- Offset += DN->getSize();
- }
-}
/// addEdgeTo - Add an edge from the current node to the specified node. This
/// can cause merging of nodes in the graph.
///
From aggarwa4 at illinois.edu Mon Mar 7 19:33:09 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 08 Mar 2011 01:33:09 -0000
Subject: [llvm-commits] [poolalloc] r127200 - in /poolalloc/trunk/test:
TEST.types.Makefile TEST.types.report
Message-ID: <20110308013309.B16A32A6C12C@llvm.org>
Author: aggarwa4
Date: Mon Mar 7 19:33:09 2011
New Revision: 127200
URL: http://llvm.org/viewvc/llvm-project?rev=127200&view=rev
Log:
Remove scalarrepl from set of safe optimization passes.
Modified:
poolalloc/trunk/test/TEST.types.Makefile
poolalloc/trunk/test/TEST.types.report
Modified: poolalloc/trunk/test/TEST.types.Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.types.Makefile?rev=127200&r1=127199&r2=127200&view=diff
==============================================================================
--- poolalloc/trunk/test/TEST.types.Makefile (original)
+++ poolalloc/trunk/test/TEST.types.Makefile Mon Mar 7 19:33:09 2011
@@ -31,7 +31,8 @@
ANALYZE_OPTS += -instcount -disable-verify
MEM := -track-memory -time-passes -disable-output
-SAFE_OPTS := -internalize -scalarrepl -deadargelim -globaldce -basiccg -inline
+#SAFE_OPTS := -internalize -scalarrepl -deadargelim -globaldce -basiccg -inline
+SAFE_OPTS := -internalize -deadargelim -globaldce -basiccg -inline
$(PROGRAMS_TO_TEST:%=Output/%.linked1.bc): \
Output/%.linked1.bc: Output/%.linked.rbc $(LOPT)
@@ -44,14 +45,13 @@
$(PROGRAMS_TO_TEST:%=Output/%.temp1.bc): \
Output/%.temp1.bc: Output/%.llvm1.bc
-$(RUNTOOLSAFELY) $(LLVMLD) -disable-opt $(SAFE_OPTS) -link-as-library $< $(PA_PRE_RT) -o $@
-
$(PROGRAMS_TO_TEST:%=Output/%.opt1.bc): \
Output/%.opt1.bc: Output/%.llvm1.bc $(LOPT) $(ASSIST_SO)
- -$(RUNOPT) -load $(ASSIST_SO) -disable-opt -info-output-file=$(CURDIR)/$@.info -instnamer -internalize -varargsfunc -indclone -funcspec -ipsccp -deadargelim -simplifygep -die -mergegep -mergearrgep -die -globaldce -simplifycfg -deadargelim -arg-simplify -varargsfunc -indclone -funcspec -deadargelim -globaldce -die -simplifycfg -gep-args -deadargelim -die -mergegep -die -globaldce -stats -time-passes $< -f -o $@
+ -$(RUNOPT) -load $(ASSIST_SO) -disable-opt -info-output-file=$(CURDIR)/$@.info -instnamer -internalize -varargsfunc -indclone -funcspec -ipsccp -deadargelim -simplifygep -die -mergegep -mergearrgep -die -globaldce -simplifycfg -deadargelim -arg-simplify -varargsfunc -indclone -funcspec -deadargelim -globaldce -die -simplifycfg -gep-args -deadargelim -die -mergegep -die -dce -globaldce -stats -time-passes $< -f -o $@
$(PROGRAMS_TO_TEST:%=Output/%.opt.bc): \
Output/%.opt.bc: Output/%.llvm1.bc $(LOPT) $(ASSIST_SO)
- -$(RUNOPT) -load $(ASSIST_SO) -disable-opt -info-output-file=$(CURDIR)/$@.info -instnamer -internalize -varargsfunc -indclone -funcspec -ipsccp -deadargelim -simplifygep -die -mergegep -die -mergearrgep -die -globaldce -simplifycfg -deadargelim -arg-simplify -die -varargsfunc -die -simplifycfg -globaldce -indclone -funcspec -deadargelim -globaldce -die -simplifycfg -gep-args -deadargelim -die -mergegep -die -mergearrgep -die -globaldce -stats -time-passes $< -f -o $@
+ -$(RUNOPT) -load $(ASSIST_SO) -disable-opt -info-output-file=$(CURDIR)/$@.info -instnamer -internalize -varargsfunc -indclone -funcspec -ipsccp -deadargelim -simplifygep -die -mergegep -die -mergearrgep -die -globaldce -simplifycfg -deadargelim -arg-simplify -die -varargsfunc -die -simplifycfg -globaldce -indclone -funcspec -deadargelim -globaldce -die -simplifycfg -gep-args -deadargelim -die -mergefunc -die -mergegep -die -mergearrgep -die -globaldce -int2ptrcmp -die -dce -stats -time-passes $< -f -o $@
$(PROGRAMS_TO_TEST:%=Output/%.temp2.bc): \
Output/%.temp2.bc: Output/%.temp1.bc $(LOPT) $(ASSIST_SO)
@@ -201,15 +201,15 @@
@/bin/echo -n "VARARGS_CALLS: " >> $@
- at grep 'Number of Calls Simplified' $<.info >> $@
@echo >> $@
+ @/bin/echo -n "GEP_CALLS: " >> $@
+ - at grep 'Number of Calls Modified' $<.info >> $@
+ @echo >> $@
@/bin/echo -n "ARG_SMPL: " >> $@
- at grep 'Number of Args changeable' $<.info >> $@
@echo >> $@
- @/bin/echo -n "CALLS1: " >> $@
- - at grep 'Number of calls that could not be resolved' $@.time.1 >> $@
+ @/bin/echo -n "INDCALLS: " >> $@
+ - at grep 'Number of unresolved IndCalls' $@.time.1 >> $@
@echo >> $@
- @-if test -f Output/$*.opt.diff-nat; then \
- printf "RUN: 1" >> $@;\
- fi
$(PROGRAMS_TO_TEST:%=test.$(TEST).%): \
Modified: poolalloc/trunk/test/TEST.types.report
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.types.report?rev=127200&r1=127199&r2=127200&view=diff
==============================================================================
--- poolalloc/trunk/test/TEST.types.report (original)
+++ poolalloc/trunk/test/TEST.types.report Mon Mar 7 19:33:09 2011
@@ -159,11 +159,12 @@
# Nodes Folded
[],
["VAFUNC", "VARARGS_CALLS: *([0-9]+)"],
+ ["GEPFUNC", "GEP_CALLS: *([0-9]+)"],
["ARGSMPL", "ARG_SMPL: *([0-9]+)"],
["FUNCSPEC", "CLONED_FUNCSPEC: *([0-9]+)"],
["INDCLONE", "CLONED_INDCLONE: *([0-9]+)"],
["StdLibFold", "STD_LIB_FOLD: *([0-9]+)"],
["I2PB", "I2PB: *([0-9]+)"],
["I2PS", "I2PS: *([0-9]+)"],
- ["Calls", "CALLS1: *([0-9]+)"],
+ ["Calls", "INDCALLS: *([0-9]+)"],
);
From atrick at apple.com Mon Mar 7 19:51:56 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 08 Mar 2011 01:51:56 -0000
Subject: [llvm-commits] [llvm] r127203 -
/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Message-ID: <20110308015156.6453F2A6C12C@llvm.org>
Author: atrick
Date: Mon Mar 7 19:51:56 2011
New Revision: 127203
URL: http://llvm.org/viewvc/llvm-project?rev=127203&view=rev
Log:
Further improvements to pre-RA-sched=list-ilp.
This change uses the MaxReorderWindow for both height and depth, which
tends to limit the negative effects of high register pressure.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=127203&r1=127202&r2=127203&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Mar 7 19:51:56 2011
@@ -99,11 +99,11 @@
#ifndef NDEBUG
namespace {
// For sched=list-ilp, Count the number of times each factor comes into play.
- enum { FactPressureDiff, FactRegUses, FactHeight, FactDepth, FactUllman,
- NumFactors };
+ enum { FactPressureDiff, FactRegUses, FactHeight, FactDepth, FactStatic,
+ FactOther, NumFactors };
}
static const char *FactorName[NumFactors] =
-{"PressureDiff", "RegUses", "Height", "Depth","Ullman"};
+{"PressureDiff", "RegUses", "Height", "Depth","Static", "Other"};
static int FactorCount[NumFactors];
#endif //!NDEBUG
@@ -2103,9 +2103,11 @@
unsigned LPriority = SPQ->getNodePriority(left);
unsigned RPriority = SPQ->getNodePriority(right);
if (LPriority != RPriority) {
- DEBUG(++FactorCount[FactUllman]);
+ DEBUG(++FactorCount[FactStatic]);
return LPriority > RPriority;
}
+ DEBUG(++FactorCount[FactOther]);
+
// Try schedule def + use closer when Sethi-Ullman numbers are the same.
// e.g.
// t1 = op t2, c1
@@ -2228,6 +2230,28 @@
return true;
}
+bool canEnableCoaelscing(SUnit *SU) {
+ unsigned Opc = SU->getNode() ? SU->getNode()->getOpcode() : 0;
+ if (Opc == ISD::TokenFactor || Opc == ISD::CopyToReg)
+ // CopyToReg should be close to its uses to facilitate coalescing and
+ // avoid spilling.
+ return true;
+
+ if (Opc == TargetOpcode::EXTRACT_SUBREG ||
+ Opc == TargetOpcode::SUBREG_TO_REG ||
+ Opc == TargetOpcode::INSERT_SUBREG)
+ // EXTRACT_SUBREG, INSERT_SUBREG, and SUBREG_TO_REG nodes should be
+ // close to their uses to facilitate coalescing.
+ return true;
+
+ if (SU->NumPreds == 0 && SU->NumSuccs != 0)
+ // If SU does not have a register def, schedule it close to its uses
+ // because it does not lengthen any live ranges.
+ return true;
+
+ return false;
+}
+
// list-ilp is currently an experimental scheduler that allows various
// heuristics to be enabled prior to the normal register reduction logic.
bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
@@ -2235,39 +2259,60 @@
// No way to compute latency of calls.
return BURRSort(left, right, SPQ);
- unsigned LLiveUses, RLiveUses;
- int LPDiff = SPQ->RegPressureDiff(left, LLiveUses);
- int RPDiff = SPQ->RegPressureDiff(right, RLiveUses);
+ unsigned LLiveUses = 0, RLiveUses = 0;
+ int LPDiff = 0, RPDiff = 0;
+ if (!DisableSchedRegPressure || !DisableSchedLiveUses) {
+ LPDiff = SPQ->RegPressureDiff(left, LLiveUses);
+ RPDiff = SPQ->RegPressureDiff(right, RLiveUses);
+ }
if (!DisableSchedRegPressure && LPDiff != RPDiff) {
DEBUG(++FactorCount[FactPressureDiff]);
+ DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum << "): " << LPDiff
+ << " != SU(" << right->NodeNum << "): " << RPDiff << "\n");
return LPDiff > RPDiff;
}
- if (!DisableSchedLiveUses && LLiveUses != RLiveUses) {
- DEBUG(dbgs() << "Live uses " << left->NodeNum << " = " << LLiveUses
- << " != " << right->NodeNum << " = " << RLiveUses << "\n");
+ if (!DisableSchedRegPressure && (LPDiff > 0 || RPDiff > 0)) {
+ bool LReduce = canEnableCoaelscing(left);
+ bool RReduce = canEnableCoaelscing(right);
+ DEBUG(if (LReduce != RReduce) ++FactorCount[FactPressureDiff]);
+ if (LReduce && !RReduce) return false;
+ if (RReduce && !LReduce) return true;
+ }
+
+ if (!DisableSchedLiveUses && (LLiveUses != RLiveUses)) {
+ DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses
+ << " != SU(" << right->NodeNum << "): " << RLiveUses << "\n");
DEBUG(++FactorCount[FactRegUses]);
return LLiveUses < RLiveUses;
}
- bool LStall = BUHasStall(left, left->getHeight(), SPQ);
- bool RStall = BUHasStall(right, right->getHeight(), SPQ);
- if (!DisableSchedStalls && LStall != RStall) {
- DEBUG(++FactorCount[FactHeight]);
- return left->getHeight() > right->getHeight();
+ if (!DisableSchedStalls) {
+ bool LStall = BUHasStall(left, left->getHeight(), SPQ);
+ bool RStall = BUHasStall(right, right->getHeight(), SPQ);
+ if (LStall != RStall) {
+ DEBUG(++FactorCount[FactHeight]);
+ return left->getHeight() > right->getHeight();
+ }
}
if (!DisableSchedCriticalPath) {
int spread = (int)left->getDepth() - (int)right->getDepth();
if (std::abs(spread) > MaxReorderWindow) {
+ DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): "
+ << left->getDepth() << " != SU(" << right->NodeNum << "): "
+ << right->getDepth() << "\n");
DEBUG(++FactorCount[FactDepth]);
return left->getDepth() < right->getDepth();
}
}
if (!DisableSchedHeight && left->getHeight() != right->getHeight()) {
- DEBUG(++FactorCount[FactHeight]);
- return left->getHeight() > right->getHeight();
+ int spread = (int)left->getHeight() - (int)right->getHeight();
+ if (std::abs(spread) > MaxReorderWindow) {
+ DEBUG(++FactorCount[FactHeight]);
+ return left->getHeight() > right->getHeight();
+ }
}
return BURRSort(left, right, SPQ);
From ajclinto at gmail.com Mon Mar 7 20:28:37 2011
From: ajclinto at gmail.com (Andrew Clinton)
Date: Mon, 7 Mar 2011 21:28:37 -0500
Subject: [llvm-commits] Patch to improve loop-simplify
In-Reply-To: <51245ABE-9F40-445A-BA2F-EE40A61D2454@apple.com>
References:
<51245ABE-9F40-445A-BA2F-EE40A61D2454@apple.com>
Message-ID:
I've run a few more tests based on the IR listed below. It appears
that regardless of whether my patch is present, llc will generate code
without the extra "jmp" for the old .ll and with the extra "jmp" with
the new .ll. So it appears that the patch is not responsible for this
difference in the generated x86 assembly code. I'm guessing that the
blocks happen to fall in a nicer pattern for codegen in this
particular case, when an outer loop is split out. Could you commit
the patch?
Andrew
On Thu, Mar 3, 2011 at 5:59 PM, Cameron Zwarich wrote:
> That is a bit strange. There is another run of LoopSimplify in the backend for LoopStrengthReduce. Perhaps a problem is reintroduced there that is not cleaned up.
>
> Cameron
>
> On Mar 3, 2011, at 8:10 AM, Andrew Clinton wrote:
>
>> I'm not sure why the code generator is synthesizing an additional
>> unconditional branch. ?The IR is certainly simpler with this patch.
>>
>> --------------------------------
>> With patch:
>>> opt -O3 not-nested-loop.ll -S
>>
>> ; ModuleID = 'not-nested-loop.ll'
>>
>> define i32 @_Z4testv() {
>> ;