From grosser at fim.uni-passau.de  Mon Apr  4 01:53:29 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Mon, 04 Apr 2011 02:53:29 -0400
Subject: [llvm-commits] [PATCH 1/2] Region: Check the exit region before
 use it when expanding a region.
In-Reply-To: <BANLkTimv+KNxQDpCGtZ84kkWE8g4qgoN4w@mail.gmail.com>
References: <BANLkTimv+KNxQDpCGtZ84kkWE8g4qgoN4w@mail.gmail.com>
Message-ID: <4D996AE9.5000005@fim.uni-passau.de>

On 04/03/2011 11:27 PM, ether zhhb wrote:
>> From 0c43ee6358a05b19b6b9924e5de3074216b7bcd5 Mon Sep 17 00:00:00 2001
> From: ether<etherzhhb at gmail.com>
> Date: Mon, 4 Apr 2011 11:24:37 +0800
> Subject: [PATCH 1/2] Region: Check the exit region before use it when
> expanding a region.
>
> ---
>   lib/Analysis/RegionInfo.cpp |    3 +++
>   1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/lib/Analysis/RegionInfo.cpp b/lib/Analysis/RegionInfo.cpp
> index e2f6a8b..a5250cf 100644
> --- a/lib/Analysis/RegionInfo.cpp
> +++ b/lib/Analysis/RegionInfo.cpp
> @@ -394,6 +394,9 @@ Region *Region::getExpandedRegion() const {
>
>     Region *R = RI->getRegionFor(exit);
>
> +  if (!R)
> +    llvm_unreachable(("Can not find exit for region: " +
> getNameStr()).c_str());


Hey ether,

can you use an assert() here?

Cheers
Tobi

From grosser at fim.uni-passau.de  Mon Apr  4 02:19:18 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Mon, 04 Apr 2011 07:19:18 -0000
Subject: [llvm-commits] [llvm] r128808 - in /llvm/trunk:
 include/llvm/Analysis/RegionInfo.h lib/Analysis/RegionInfo.cpp
Message-ID: <20110404071918.BACEA2A6C12C@llvm.org>

Author: grosser
Date: Mon Apr  4 02:19:18 2011
New Revision: 128808

URL: http://llvm.org/viewvc/llvm-project?rev=128808&view=rev
Log:
Region: Allow user control the printing style of the print function.

Contributed by: etherzhhb at gmail.com

Modified:
    llvm/trunk/include/llvm/Analysis/RegionInfo.h
    llvm/trunk/lib/Analysis/RegionInfo.cpp

Modified: llvm/trunk/include/llvm/Analysis/RegionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/RegionInfo.h?rev=128808&r1=128807&r2=128808&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/RegionInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/RegionInfo.h Mon Apr  4 02:19:18 2011
@@ -335,12 +335,16 @@
     return RI;
   }
 
+  /// PrintStyle - Print region in difference ways.
+  enum PrintStyle { PrintNone, PrintBB, PrintRN  };
+
   /// @brief Print the region.
   ///
   /// @param OS The output stream the Region is printed to.
   /// @param printTree Print also the tree of subregions.
   /// @param level The indentation level used for printing.
-  void print(raw_ostream& OS, bool printTree = true, unsigned level = 0) const;
+  void print(raw_ostream& OS, bool printTree = true, unsigned level = 0,
+             enum PrintStyle Style = PrintNone) const;
 
   /// @brief Print the region to stderr.
   void dump() const;

Modified: llvm/trunk/lib/Analysis/RegionInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/RegionInfo.cpp?rev=128808&r1=128807&r2=128808&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/RegionInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/RegionInfo.cpp Mon Apr  4 02:19:18 2011
@@ -41,16 +41,15 @@
 STATISTIC(numRegions,       "The # of regions");
 STATISTIC(numSimpleRegions, "The # of simple regions");
 
-//===----------------------------------------------------------------------===//
-/// PrintStyle - Print region in difference ways.
-enum PrintStyle { PrintNone, PrintBB, PrintRN  };
-
-static cl::opt<enum PrintStyle> printStyle("print-region-style", cl::Hidden,
+static cl::opt<enum Region::PrintStyle> printStyle("print-region-style",
+  cl::Hidden,
   cl::desc("style of printing regions"),
   cl::values(
-    clEnumValN(PrintNone, "none",  "print no details"),
-    clEnumValN(PrintBB, "bb",  "print regions in detail with block_iterator"),
-    clEnumValN(PrintRN, "rn",  "print regions in detail with element_iterator"),
+    clEnumValN(Region::PrintNone, "none",  "print no details"),
+    clEnumValN(Region::PrintBB, "bb",
+               "print regions in detail with block_iterator"),
+    clEnumValN(Region::PrintRN, "rn",
+               "print regions in detail with element_iterator"),
     clEnumValEnd));
 //===----------------------------------------------------------------------===//
 /// Region Implementation
@@ -413,7 +412,8 @@
   return new Region(getEntry(), R->getExit(), RI, DT);
 }
 
-void Region::print(raw_ostream &OS, bool print_tree, unsigned level) const {
+void Region::print(raw_ostream &OS, bool print_tree, unsigned level,
+                   enum PrintStyle Style) const {
   if (print_tree)
     OS.indent(level*2) << "[" << level << "] " << getNameStr();
   else
@@ -422,14 +422,14 @@
   OS << "\n";
 
 
-  if (printStyle != PrintNone) {
+  if (Style != PrintNone) {
     OS.indent(level*2) << "{\n";
     OS.indent(level*2 + 2);
 
-    if (printStyle == PrintBB) {
+    if (Style == PrintBB) {
       for (const_block_iterator I = block_begin(), E = block_end(); I!=E; ++I)
         OS << **I << ", "; // TODO: remove the last ","
-    } else if (printStyle == PrintRN) {
+    } else if (Style == PrintRN) {
       for (const_element_iterator I = element_begin(), E = element_end(); I!=E; ++I)
         OS << **I << ", "; // TODO: remove the last ",
     }
@@ -439,14 +439,14 @@
 
   if (print_tree)
     for (const_iterator RI = begin(), RE = end(); RI != RE; ++RI)
-      (*RI)->print(OS, print_tree, level+1);
+      (*RI)->print(OS, print_tree, level+1, Style);
 
-  if (printStyle != PrintNone)
+  if (Style != PrintNone)
     OS.indent(level*2) << "} \n";
 }
 
 void Region::dump() const {
-  print(dbgs(), true, getDepth());
+  print(dbgs(), true, getDepth(), printStyle.getValue());
 }
 
 void Region::clearNodeCache() {
@@ -714,7 +714,7 @@
 
 void RegionInfo::print(raw_ostream &OS, const Module *) const {
   OS << "Region tree:\n";
-  TopLevelRegion->print(OS, true, 0);
+  TopLevelRegion->print(OS, true, 0, printStyle.getValue());
   OS << "End region tree\n";
 }
 



From grosser at fim.uni-passau.de  Mon Apr  4 02:25:38 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Mon, 04 Apr 2011 03:25:38 -0400
Subject: [llvm-commits] Subject: [PATCH 2/2] Region: Allow user control
 the printing style of the print function.
In-Reply-To: <BANLkTikR_kL2xEz3Cj1_1JO9B2KOhNaY4Q@mail.gmail.com>
References: <BANLkTikR_kL2xEz3Cj1_1JO9B2KOhNaY4Q@mail.gmail.com>
Message-ID: <4D997272.2040906@fim.uni-passau.de>

On 04/03/2011 11:31 PM, ether zhhb wrote:
> hi,
>
> This patch allow user to control the printing style of the Region's
> print method by calling it with a PrintStyle parameter like:
>
> R->print(dbgs(), true, 0, Region::PrintRN/*Print the region with
> hireachy style*/);
>
> best regards
> ether

Committed in: 128808

Thanks
Tobi

From jay.foad at gmail.com  Mon Apr  4 02:44:02 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Mon, 04 Apr 2011 07:44:02 -0000
Subject: [llvm-commits] [llvm] r128810 - in /llvm/trunk:
 lib/Target/CBackend/CBackend.cpp
 lib/Transforms/IPO/IPConstantPropagation.cpp lib/VMCore/Verifier.cpp
 test/Assembler/aggregate-return-single-value.ll
Message-ID: <20110404074403.0F01E2A6C12D@llvm.org>

Author: foad
Date: Mon Apr  4 02:44:02 2011
New Revision: 128810

URL: http://llvm.org/viewvc/llvm-project?rev=128810&view=rev
Log:
Remove some support for ReturnInsts with multiple operands, and for
returning a scalar value in a function whose return type is a single-
element structure or array.

Modified:
    llvm/trunk/lib/Target/CBackend/CBackend.cpp
    llvm/trunk/lib/Transforms/IPO/IPConstantPropagation.cpp
    llvm/trunk/lib/VMCore/Verifier.cpp
    llvm/trunk/test/Assembler/aggregate-return-single-value.ll

Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=128810&r1=128809&r2=128810&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
+++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Mon Apr  4 02:44:02 2011
@@ -2440,24 +2440,6 @@
     return;
   }
 
-  if (I.getNumOperands() > 1) {
-    Out << "  {\n";
-    Out << "    ";
-    printType(Out, I.getParent()->getParent()->getReturnType());
-    Out << "   llvm_cbe_mrv_temp = {\n";
-    for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
-      Out << "      ";
-      writeOperand(I.getOperand(i));
-      if (i != e - 1)
-        Out << ",";
-      Out << "\n";
-    }
-    Out << "    };\n";
-    Out << "    return llvm_cbe_mrv_temp;\n";
-    Out << "  }\n";
-    return;
-  }
-
   Out << "  return";
   if (I.getNumOperands()) {
     Out << ' ';

Modified: llvm/trunk/lib/Transforms/IPO/IPConstantPropagation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/IPO/IPConstantPropagation.cpp?rev=128810&r1=128809&r2=128810&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/IPO/IPConstantPropagation.cpp (original)
+++ llvm/trunk/lib/Transforms/IPO/IPConstantPropagation.cpp Mon Apr  4 02:44:02 2011
@@ -186,7 +186,7 @@
         // Find the returned value
         Value *V;
         if (!STy)
-          V = RI->getOperand(i);
+          V = RI->getOperand(0);
         else
           V = FindInsertedValue(RI->getOperand(0), i);
 

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=128810&r1=128809&r2=128810&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Apr  4 02:44:02 2011
@@ -826,30 +826,10 @@
     Assert2(N == 0,
             "Found return instr that returns non-void in Function of void "
             "return type!", &RI, F->getReturnType());
-  else if (N == 1 && F->getReturnType() == RI.getOperand(0)->getType()) {
-    // Exactly one return value and it matches the return type. Good.
-  } else if (const StructType *STy = dyn_cast<StructType>(F->getReturnType())) {
-    // The return type is a struct; check for multiple return values.
-    Assert2(STy->getNumElements() == N,
-            "Incorrect number of return values in ret instruction!",
-            &RI, F->getReturnType());
-    for (unsigned i = 0; i != N; ++i)
-      Assert2(STy->getElementType(i) == RI.getOperand(i)->getType(),
-              "Function return type does not match operand "
-              "type of return inst!", &RI, F->getReturnType());
-  } else if (const ArrayType *ATy = dyn_cast<ArrayType>(F->getReturnType())) {
-    // The return type is an array; check for multiple return values.
-    Assert2(ATy->getNumElements() == N,
-            "Incorrect number of return values in ret instruction!",
-            &RI, F->getReturnType());
-    for (unsigned i = 0; i != N; ++i)
-      Assert2(ATy->getElementType() == RI.getOperand(i)->getType(),
-              "Function return type does not match operand "
-              "type of return inst!", &RI, F->getReturnType());
-  } else {
-    CheckFailed("Function return type does not match operand "
-                "type of return inst!", &RI, F->getReturnType());
-  }
+  else
+    Assert2(N == 1 && F->getReturnType() == RI.getOperand(0)->getType(),
+            "Function return type does not match operand "
+            "type of return inst!", &RI, F->getReturnType());
 
   // Check to make sure that the return value has necessary properties for
   // terminators...

Modified: llvm/trunk/test/Assembler/aggregate-return-single-value.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/aggregate-return-single-value.ll?rev=128810&r1=128809&r2=128810&view=diff
==============================================================================
--- llvm/trunk/test/Assembler/aggregate-return-single-value.ll (original)
+++ llvm/trunk/test/Assembler/aggregate-return-single-value.ll Mon Apr  4 02:44:02 2011
@@ -1,14 +1,8 @@
 ; RUN: llvm-as < %s | llvm-dis
 
-define { i32 } @fooa() nounwind {
-  ret i32 0
-}
 define { i32 } @foob() nounwind {
   ret {i32}{ i32 0 }
 }
-define [1 x i32] @fooc() nounwind {
-  ret i32 0
-}
 define [1 x i32] @food() nounwind {
   ret [1 x i32][ i32 0 ]
 }



From etherzhhb at gmail.com  Mon Apr  4 04:12:56 2011
From: etherzhhb at gmail.com (ether zhhb)
Date: Mon, 4 Apr 2011 17:12:56 +0800
Subject: [llvm-commits] [PATCH 1/2] Region: Check the exit region before
 use it when expanding a region.
In-Reply-To: <4D996AE9.5000005@fim.uni-passau.de>
References: <BANLkTimv+KNxQDpCGtZ84kkWE8g4qgoN4w@mail.gmail.com>
	<4D996AE9.5000005@fim.uni-passau.de>
Message-ID: <BANLkTikmHdrPevzydR297Z3uozagasK1cw@mail.gmail.com>

>
> can you use an assert() here?
sure

---
 lib/Analysis/RegionInfo.cpp |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/lib/Analysis/RegionInfo.cpp b/lib/Analysis/RegionInfo.cpp
index e2f6a8b..a374ef9 100644
--- a/lib/Analysis/RegionInfo.cpp
+++ b/lib/Analysis/RegionInfo.cpp
@@ -394,6 +394,7 @@ Region *Region::getExpandedRegion() const {

   Region *R = RI->getRegionFor(exit);

+  assert(R && "Can not find a region for exit!");
   if (R->getEntry() != exit) {
     if (exit->getTerminator()->getNumSuccessors() == 1)
       return new Region(getEntry(), *succ_begin(exit), RI, DT);
-- 
1.7.3.3
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From fvbommel at gmail.com  Mon Apr  4 04:27:51 2011
From: fvbommel at gmail.com (Frits van Bommel)
Date: Mon, 4 Apr 2011 11:27:51 +0200
Subject: [llvm-commits] [llvm] r128801 - in /llvm/trunk:
 include/llvm/Object/MachOObject.h lib/Object/MachOObject.cpp
 tools/macho-dump/macho-dump.cpp
In-Reply-To: <20110403235148.145CA2A6C12C@llvm.org>
References: <20110403235148.145CA2A6C12C@llvm.org>
Message-ID: <BANLkTinHMAcd5--sgJuQYVXXwGLXMKRVOw@mail.gmail.com>

On Mon, Apr 4, 2011 at 1:51 AM, Eric Christopher <echristo at apple.com> wrote:
> - ?if (int Res = DumpHeader(*InputObject))
> - ? ?return Res;

This was the only use of that static function:

../trunk/tools/macho-dump/macho-dump.cpp:52:12: warning: unused
function 'DumpHeader' [-Wunused-function]
static int DumpHeader(MachOObject &Obj) {
           ^
1 warning generated.


From jay.foad at gmail.com  Mon Apr  4 04:40:20 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Mon, 4 Apr 2011 10:40:20 +0100
Subject: [llvm-commits] [PATCH 1/2] Region: Check the exit region before
 use it when expanding a region.
In-Reply-To: <BANLkTikmHdrPevzydR297Z3uozagasK1cw@mail.gmail.com>
References: <BANLkTimv+KNxQDpCGtZ84kkWE8g4qgoN4w@mail.gmail.com>
	<4D996AE9.5000005@fim.uni-passau.de>
	<BANLkTikmHdrPevzydR297Z3uozagasK1cw@mail.gmail.com>
Message-ID: <BANLkTi=3_a2Fd65EGD2kw14_UViWY6NA3w@mail.gmail.com>

On 4 April 2011 10:12, ether zhhb <etherzhhb at gmail.com> wrote:
> + ?assert(R && "Can not find a region for exit!");

"Cannot" is one word.

Jay.


From baldrick at free.fr  Mon Apr  4 04:49:20 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 04 Apr 2011 09:49:20 -0000
Subject: [llvm-commits] [dragonegg] r128811 - /dragonegg/trunk/Constants.cpp
Message-ID: <20110404094920.B97E22A6C12C@llvm.org>

Author: baldrick
Date: Mon Apr  4 04:49:20 2011
New Revision: 128811

URL: http://llvm.org/viewvc/llvm-project?rev=128811&view=rev
Log:
Map constants to the global variable realizing them using a DenseMap
rather than a std::map.

Modified:
    dragonegg/trunk/Constants.cpp

Modified: dragonegg/trunk/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/Constants.cpp?rev=128811&r1=128810&r2=128811&view=diff
==============================================================================
--- dragonegg/trunk/Constants.cpp (original)
+++ dragonegg/trunk/Constants.cpp Mon Apr  4 04:49:20 2011
@@ -35,7 +35,6 @@
 
 // System headers
 #include <gmp.h>
-#include <map>
 
 // GCC headers
 extern "C" {
@@ -1164,7 +1163,7 @@
 
   // Cache the constants to avoid making obvious duplicates that have to be
   // folded by the optimizer.
-  static std::map<Constant*, GlobalVariable*> CSTCache;
+  static DenseMap<Constant*, GlobalVariable*> CSTCache;
   GlobalVariable *&Slot = CSTCache[Init];
   if (Slot)
     return Slot;



From etherzhhb at gmail.com  Mon Apr  4 05:20:12 2011
From: etherzhhb at gmail.com (ether zhhb)
Date: Mon, 4 Apr 2011 18:20:12 +0800
Subject: [llvm-commits] [PATCH 1/2] Region: Check the exit region before
 use it when expanding a region.
In-Reply-To: <BANLkTi=3_a2Fd65EGD2kw14_UViWY6NA3w@mail.gmail.com>
References: <BANLkTimv+KNxQDpCGtZ84kkWE8g4qgoN4w@mail.gmail.com>
	<4D996AE9.5000005@fim.uni-passau.de>
	<BANLkTikmHdrPevzydR297Z3uozagasK1cw@mail.gmail.com>
	<BANLkTi=3_a2Fd65EGD2kw14_UViWY6NA3w@mail.gmail.com>
Message-ID: <BANLkTi=t3AYSLKc-uPMd2JROt4eenkmt7Q@mail.gmail.com>

hi,

On Mon, Apr 4, 2011 at 5:40 PM, Jay Foad <jay.foad at gmail.com> wrote:
> On 4 April 2011 10:12, ether zhhb <etherzhhb at gmail.com> wrote:
>> + ?assert(R && "Can not find a region for exit!");
>
> "Cannot" is one word.
fixed
>
> Jay.
>
best regards
ether
---
 lib/Analysis/RegionInfo.cpp |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/lib/Analysis/RegionInfo.cpp b/lib/Analysis/RegionInfo.cpp
index e2f6a8b..36a4156 100644
--- a/lib/Analysis/RegionInfo.cpp
+++ b/lib/Analysis/RegionInfo.cpp
@@ -394,6 +394,7 @@ Region *Region::getExpandedRegion() const {

   Region *R = RI->getRegionFor(exit);

+  assert(R && "Cannot find a region for exit!");
   if (R->getEntry() != exit) {
     if (exit->getTerminator()->getNumSuccessors() == 1)
       return new Region(getEntry(), *succ_begin(exit), RI, DT);
-- 
1.7.3.3
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From baldrick at free.fr  Mon Apr  4 06:09:08 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 04 Apr 2011 11:09:08 -0000
Subject: [llvm-commits] [llvm] r128812 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20110404110909.1C2FD2A6C12C@llvm.org>

Author: baldrick
Date: Mon Apr  4 06:09:08 2011
New Revision: 128812

URL: http://llvm.org/viewvc/llvm-project?rev=128812&view=rev
Log:
Dragonegg release notes.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128812&r1=128811&r2=128812&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Mon Apr  4 06:09:08 2011
@@ -138,32 +138,32 @@
 
 <!--=========================================================================-->
 <div class="doc_subsection">
-<a name="dragonegg">DragonEgg: llvm-gcc ported to gcc-4.5</a>
+<a name="dragonegg">DragonEgg: GCC front-ends, LLVM back-end</a>
 </div>
 
 <div class="doc_text">
-NOTE: This should be written to be self-contained without referencing llvm-gcc.
-
-<p>
-<a href="http://dragonegg.llvm.org/">DragonEgg</a> is a port of llvm-gcc to
-gcc-4.5.  Unlike llvm-gcc, dragonegg in theory does not require any gcc-4.5
-modifications whatsoever (currently one small patch is needed) thanks to the
-new <a href="http://gcc.gnu.org/wiki/plugins">gcc plugin architecture</a>.
-DragonEgg is a gcc plugin that makes gcc-4.5 use the LLVM optimizers and code
-generators instead of gcc's, just like with llvm-gcc.
-</p>
-
 <p>
-DragonEgg is still a work in progress, but it is able to compile a lot of code,
-for example all of gcc, LLVM and clang.  Currently Ada, C, C++ and Fortran work
-well, while all other languages either don't work at all or only work poorly.
-For the moment only the x86-32 and x86-64 targets are supported, and only on
-linux and darwin (darwin may need additional gcc patches).
+<a href="http://dragonegg.llvm.org/">DragonEgg</a> is a
+<a href="http://gcc.gnu.org/wiki/plugins">gcc plugin</a> that replaces GCC's
+optimizers and code generators with LLVM's.
+Currently it requires a patched version of gcc-4.5.
+The plugin can target the x86-32 and x86-64 processor families and has been
+used successfully on the Darwin, FreeBSD and Linux platforms.
+The Ada, C, C++ and Fortran languages work well.
+The plugin is capable of compiling plenty of Obj-C, Obj-C++ and Java but it is
+not known whether the compiled code actually works or not!
 </p>
 
 <p>
 The 2.9 release has the following notable changes:
 <ul>
+<li>The plugin is much more stable when compiling Fortran.</li>
+<li>Inline asm where an asm output is tied to an input of a different size is
+now supported in many more cases.</li>
+<li>Basic support for the __float128 type was added.  It is now possible to
+generate LLVM IR from programs using __float128 but code generation does not
+work yet.</li>
+<li>Compiling Java programs no longer systematically crashes the plugin.</li>
 </ul>
 
 </div>



From baldrick at free.fr  Mon Apr  4 07:48:47 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 04 Apr 2011 12:48:47 -0000
Subject: [llvm-commits] [dragonegg] r128813 - /dragonegg/trunk/Constants.cpp
Message-ID: <20110404124847.986EA2A6C12E@llvm.org>

Author: baldrick
Date: Mon Apr  4 07:48:47 2011
New Revision: 128813

URL: http://llvm.org/viewvc/llvm-project?rev=128813&view=rev
Log:
Mostly cosmetic changes.  The only functionality change is that when
compiling Ada an empty constructor results in an undefined initial
value being used rather than an initial value of zero.

Modified:
    dragonegg/trunk/Constants.cpp

Modified: dragonegg/trunk/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/Constants.cpp?rev=128813&r1=128812&r2=128813&view=diff
==============================================================================
--- dragonegg/trunk/Constants.cpp (original)
+++ dragonegg/trunk/Constants.cpp Mon Apr  4 07:48:47 2011
@@ -133,7 +133,8 @@
   /// bits is undefined.
   BitSlice ExtendRange(SignedRange r) const;
 
-  /// ReduceRange - Reduce the slice to a smaller range.
+  /// ReduceRange - Reduce the slice to a smaller range discarding any bits that
+  /// do not belong to the new range.
   BitSlice ReduceRange(SignedRange r) const;
 
   /// Merge - Join the slice with another (which must be disjoint), forming the
@@ -239,7 +240,8 @@
   *this = BitSlice(Hull, TheFolder->CreateOr(ThisPart, OtherPart));
 }
 
-/// ReduceRange - Reduce the slice to a smaller range.
+/// ReduceRange - Reduce the slice to a smaller range discarding any bits that
+/// do not belong to the new range.
 BitSlice BitSlice::ReduceRange(SignedRange r) const {
   assert(R.contains(r) && "Not a reduction!");
   // Quick exit if the range did not actually decrease.
@@ -687,7 +689,7 @@
 
   // Zero length array.
   if (ResultElts.empty())
-    return Constant::getNullValue(ConvertType(TREE_TYPE(exp)));
+    return getDefaultValue(ConvertType(TREE_TYPE(exp)));
   assert(SomeVal && "If we had some initializer, we should have some value!");
 
   // Do a post-pass over all of the elements.  We're taking care of two things
@@ -808,7 +810,7 @@
     if (R.empty()) {
       // Return an empty array.  Remember the returned value as an optimization
       // in case we are called again.
-      C = Constant::getNullValue(GetUnitType(Context, 0));
+      C = UndefValue::get(GetUnitType(Context, 0));
       assert(isSafeToReturnContentsDirectly(TD) && "Unit over aligned?");
       return C;
     }
@@ -1007,17 +1009,15 @@
 }
 
 static Constant *ConvertCONSTRUCTOR(tree exp) {
-  // Please note, that we can have empty ctor, even if array is non-trivial (has
-  // nonzero number of entries). This situation is typical for static ctors,
-  // when array is filled during program initialization.
-  if (CONSTRUCTOR_ELTS(exp) == 0 ||
-      VEC_length(constructor_elt, CONSTRUCTOR_ELTS(exp)) == 0)  // All zeros?
-    return Constant::getNullValue(ConvertType(TREE_TYPE(exp)));
+  // If the constructor is empty then default initialize all components.  It is
+  // safe to use the LLVM type here as it covers every part of the GCC type that
+  // can be default initialized.
+  if (CONSTRUCTOR_NELTS(exp) == 0)
+    return getDefaultValue(ConvertType(TREE_TYPE(exp)));
 
   switch (TREE_CODE(TREE_TYPE(exp))) {
   default:
-    debug_tree(exp);
-    assert(0 && "Unknown ctor!");
+    DieAbjectly("Unknown constructor!", exp);
   case VECTOR_TYPE:
   case ARRAY_TYPE:  return ConvertArrayCONSTRUCTOR(exp);
   case QUAL_UNION_TYPE:



From aggarwa4 at illinois.edu  Mon Apr  4 09:23:16 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 04 Apr 2011 14:23:16 -0000
Subject: [llvm-commits] [poolalloc] r128814 -
	/poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp
Message-ID: <20110404142316.71B712A6C12C@llvm.org>

Author: aggarwa4
Date: Mon Apr  4 09:23:16 2011
New Revision: 128814

URL: http://llvm.org/viewvc/llvm-project?rev=128814&view=rev
Log:
DoesNotReturn attribute has the wrong meaning here.
I wanted to imply that this call instruction has
no return value. 

Modified:
    poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp

Modified: poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp?rev=128814&r1=128813&r2=128814&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp Mon Apr  4 09:23:16 2011
@@ -87,9 +87,7 @@
               Args.push_back(CI->getOperand(j));
             }
             CallInst *CINew = CallInst::Create(F, Args.begin(), Args.end(), "", CI);
-            if(F->getReturnType() != CI->getType()){ // means no uses
-              CINew->setDoesNotReturn();
-            } else {
+            if(F->getReturnType() == CI->getType()){ // else means no uses
               CI->replaceAllUsesWith(CINew);
             }
             CI->eraseFromParent();



From aggarwa4 at illinois.edu  Mon Apr  4 09:26:22 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 04 Apr 2011 14:26:22 -0000
Subject: [llvm-commits] [poolalloc] r128815 - in /poolalloc/trunk:
 include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp
 lib/AssistDS/TypeChecks.h
Message-ID: <20110404142622.40CEB2A6C12C@llvm.org>

Author: aggarwa4
Date: Mon Apr  4 09:26:22 2011
New Revision: 128815

URL: http://llvm.org/viewvc/llvm-project?rev=128815&view=rev
Log:
Move header file to the include folder.

Added:
    poolalloc/trunk/include/assistDS/TypeChecks.h
Removed:
    poolalloc/trunk/lib/AssistDS/TypeChecks.h
Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp

Added: poolalloc/trunk/include/assistDS/TypeChecks.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=128815&view=auto
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecks.h (added)
+++ poolalloc/trunk/include/assistDS/TypeChecks.h Mon Apr  4 09:26:22 2011
@@ -0,0 +1,62 @@
+//===------------- TypeChecks.h - Insert runtime type checks --------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file was developed by the LLVM research group and is distributed under
+// the University of Illinois Open Source License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This pass inserts checks to enforce type safety during runtime.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef TYPE_CHECKS_H
+#define TYPE_CHECKS_H
+
+#include "llvm/Instructions.h"
+#include "llvm/Pass.h"
+
+#include <map>
+
+namespace llvm {
+
+class Type;
+class Value;
+
+class TypeChecks : public ModulePass {
+private:
+  unsigned int maxType;
+  std::map<const Type *, unsigned int> UsedTypes;
+  std::map<const Value *, const Type *> UsedValues;
+
+  // Incorporate one type and all of its subtypes into the collection of used types.
+  void IncorporateType(const Type *Ty);
+
+  // Incorporate all of the types used by this value.
+  void IncorporateValue(const Value *V);
+
+public:
+  static char ID;
+  TypeChecks() : ModulePass(&ID) {}
+  virtual bool runOnModule(Module &M);
+  virtual void print(raw_ostream &OS, const Module *M) const;
+
+  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
+  }
+
+  bool initShadow(Module &M, StoreInst &SI);
+  bool initShadowLI(Module &M, LoadInst &LI);
+  bool unmapShadow(Module &M, Instruction &I);
+  bool visitLoadInst(Module &M, LoadInst &LI);
+  bool visitStoreInst(Module &M, StoreInst &SI);
+
+  // Return the map containing all of the types used in the module.
+  const std::map<const Type *, unsigned int> &getTypes() const {
+    return UsedTypes;
+  }
+};
+
+} // End llvm namespace
+
+#endif

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=128815&r1=128814&r2=128815&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Mon Apr  4 09:26:22 2011
@@ -11,7 +11,7 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "TypeChecks.h"
+#include "assistDS/TypeChecks.h"
 #include "llvm/Constants.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/Module.h"

Removed: poolalloc/trunk/lib/AssistDS/TypeChecks.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.h?rev=128814&view=auto
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.h (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.h (removed)
@@ -1,62 +0,0 @@
-//===------------- TypeChecks.h - Insert runtime type checks --------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This pass inserts checks to enforce type safety during runtime.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef TYPE_CHECKS_H
-#define TYPE_CHECKS_H
-
-#include "llvm/Instructions.h"
-#include "llvm/Pass.h"
-
-#include <map>
-
-namespace llvm {
-
-class Type;
-class Value;
-
-class TypeChecks : public ModulePass {
-private:
-  unsigned int maxType;
-  std::map<const Type *, unsigned int> UsedTypes;
-  std::map<const Value *, const Type *> UsedValues;
-
-  // Incorporate one type and all of its subtypes into the collection of used types.
-  void IncorporateType(const Type *Ty);
-
-  // Incorporate all of the types used by this value.
-  void IncorporateValue(const Value *V);
-
-public:
-  static char ID;
-  TypeChecks() : ModulePass(&ID) {}
-  virtual bool runOnModule(Module &M);
-  virtual void print(raw_ostream &OS, const Module *M) const;
-
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-  }
-
-  bool initShadow(Module &M, StoreInst &SI);
-  bool initShadowLI(Module &M, LoadInst &LI);
-  bool unmapShadow(Module &M, Instruction &I);
-  bool visitLoadInst(Module &M, LoadInst &LI);
-  bool visitStoreInst(Module &M, StoreInst &SI);
-
-  // Return the map containing all of the types used in the module.
-  const std::map<const Type *, unsigned int> &getTypes() const {
-    return UsedTypes;
-  }
-};
-
-} // End llvm namespace
-
-#endif



From aggarwa4 at illinois.edu  Mon Apr  4 09:32:53 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 04 Apr 2011 14:32:53 -0000
Subject: [llvm-commits] [poolalloc] r128816 -
	/poolalloc/trunk/lib/DSA/DSTest.cpp
Message-ID: <20110404143253.A26882A6C12C@llvm.org>

Author: aggarwa4
Date: Mon Apr  4 09:32:53 2011
New Revision: 128816

URL: http://llvm.org/viewvc/llvm-project?rev=128816&view=rev
Log:
Keep a reference to the module, instead of going 
through the function pointer. This is needed for
globals.

Modified:
    poolalloc/trunk/lib/DSA/DSTest.cpp

Modified: poolalloc/trunk/lib/DSA/DSTest.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DSTest.cpp?rev=128816&r1=128815&r2=128816&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DSTest.cpp (original)
+++ poolalloc/trunk/lib/DSA/DSTest.cpp Mon Apr  4 09:32:53 2011
@@ -80,6 +80,7 @@
 class NodeValue {
   // Containing Function, if applicable.
   Function *F;
+  Module *ParentM;
   // Value in that graph's scalarmap that we base off of
   // (note that the NH we have below could be indexed a few times
   // from this value, only corresponds directly if no offsets)
@@ -188,6 +189,7 @@
 
       // First, find the function
       F = M->getFunction(func);
+      ParentM = const_cast<Module*>(M);
       assert(F && "Unable to find function specified!");
 
       // Now we try to find the value...
@@ -229,6 +231,7 @@
   // are a bit confusing in the context of offsets.  Make this not lame.
   Value    * getValue()     { return V;                           }
   Function * getFunction()  { return F;                           }
+  Module * getParentModule()  { return ParentM;                           }
 
   /// Helper to fetch the node from the nodehandle
   DSNode * getNode() {
@@ -273,7 +276,7 @@
 // (meant to be called as a helper)
 static void printTypesForNode(llvm::raw_ostream &O, NodeValue &NV) {
   DSNode *N = NV.getNode();
-  Module *M = NV.getFunction()->getParent();
+  Module *M = NV.getParentModule();
 
   if (N->isNodeCompletelyFolded()) {
     O << "Folded";



From aggarwa4 at illinois.edu  Mon Apr  4 09:34:12 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 04 Apr 2011 14:34:12 -0000
Subject: [llvm-commits] [poolalloc] r128817 -
	/poolalloc/trunk/lib/DSA/DataStructureStats.cpp
Message-ID: <20110404143412.604792A6C12C@llvm.org>

Author: aggarwa4
Date: Mon Apr  4 09:34:12 2011
New Revision: 128817

URL: http://llvm.org/viewvc/llvm-project?rev=128817&view=rev
Log:
Minor formatting changes.

Modified:
    poolalloc/trunk/lib/DSA/DataStructureStats.cpp

Modified: poolalloc/trunk/lib/DSA/DataStructureStats.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/DataStructureStats.cpp?rev=128817&r1=128816&r2=128817&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/DataStructureStats.cpp (original)
+++ poolalloc/trunk/lib/DSA/DataStructureStats.cpp Mon Apr  4 09:34:12 2011
@@ -26,8 +26,10 @@
 using namespace llvm;
 
 namespace {
-  STATISTIC (TotalNumCallees, "Total number of callee functions at all indirect call sites");
-  STATISTIC (NumIndirectCalls, "Total number of indirect call sites in the program");
+  STATISTIC (TotalNumCallees, 
+             "Total number of callee functions at all indirect call sites");
+  STATISTIC (NumIndirectCalls, 
+             "Total number of indirect call sites in the program");
 
   // Typed/Untyped memory accesses: If DSA can infer that the types the loads
   // and stores are accessing are correct (ie, the node has not been collapsed),
@@ -130,7 +132,7 @@
         ++numIndirectCalls;
       } else {
         DEBUG(errs() << "WARNING: No callee in Function '" 
-              << F.getNameStr() << "' at call: \n"
+              << F.getNameStr() << " at call: \n"
               << *I->getCallSite().getInstruction());
       }
     }



From joerg at bec.de  Mon Apr  4 09:42:22 2011
From: joerg at bec.de (Joerg Sonnenberger)
Date: Mon, 04 Apr 2011 14:42:22 -0000
Subject: [llvm-commits] [llvm] r128818 -
	/llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
Message-ID: <20110404144222.BD56E2A6C12C@llvm.org>

Author: joerg
Date: Mon Apr  4 09:42:22 2011
New Revision: 128818

URL: http://llvm.org/viewvc/llvm-project?rev=128818&view=rev
Log:
Change loops to derive the number of tables automatically

Modified:
    llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp

Modified: llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp?rev=128818&r1=128817&r2=128818&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp (original)
+++ llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp Mon Apr  4 09:42:22 2011
@@ -267,7 +267,7 @@
 DisassemblerTables::DisassemblerTables() {
   unsigned i;
   
-  for (i = 0; i < 4; i++) {
+  for (i = 0; i < sizeof(Tables) / sizeof(Tables[0]); i++) {
     Tables[i] = new ContextDecision;
     memset(Tables[i], 0, sizeof(ContextDecision));
   }
@@ -278,7 +278,7 @@
 DisassemblerTables::~DisassemblerTables() {
   unsigned i;
   
-  for (i = 0; i < 4; i++)
+  for (i = 0; i < sizeof(Tables) / sizeof(Tables[0]); i++)
     delete Tables[i];
 }
   



From baldrick at free.fr  Mon Apr  4 09:52:32 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 04 Apr 2011 16:52:32 +0200
Subject: [llvm-commits] [llvm] r128818
	-	/llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
In-Reply-To: <20110404144222.BD56E2A6C12C@llvm.org>
References: <20110404144222.BD56E2A6C12C@llvm.org>
Message-ID: <4D99DB30.9040407@free.fr>

Hi Joerg,

> -  for (i = 0; i<  4; i++) {
> +  for (i = 0; i<  sizeof(Tables) / sizeof(Tables[0]); i++) {

maybe you can use array_lengthof from STLExtras.h instead.

Ciao, Duncan.

From stoklund at 2pi.dk  Mon Apr  4 10:32:11 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 04 Apr 2011 15:32:11 -0000
Subject: [llvm-commits] [llvm] r128820 - /llvm/trunk/lib/CodeGen/SplitKit.h
Message-ID: <20110404153211.619052A6C12C@llvm.org>

Author: stoklund
Date: Mon Apr  4 10:32:11 2011
New Revision: 128820

URL: http://llvm.org/viewvc/llvm-project?rev=128820&view=rev
Log:
Delete leftover data members.

Modified:
    llvm/trunk/lib/CodeGen/SplitKit.h

Modified: llvm/trunk/lib/CodeGen/SplitKit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=128820&r1=128819&r2=128820&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.h (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.h Mon Apr  4 10:32:11 2011
@@ -85,10 +85,6 @@
     bool LiveThrough;     ///< Live in whole block (Templ 5. or 6. above).
     bool LiveIn;          ///< Current reg is live in.
     bool LiveOut;         ///< Current reg is live out.
-
-    // Per-interference pattern scratch data.
-    bool OverlapEntry;    ///< Interference overlaps entering interval.
-    bool OverlapExit;     ///< Interference overlaps exiting interval.
   };
 
   /// Basic blocks where var is live. This array is parallel to



From stoklund at 2pi.dk  Mon Apr  4 10:32:15 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 04 Apr 2011 15:32:15 -0000
Subject: [llvm-commits] [llvm] r128821 - in /llvm/trunk:
 include/llvm/CodeGen/SlotIndexes.h lib/CodeGen/RegAllocGreedy.cpp
 lib/CodeGen/SplitKit.cpp lib/CodeGen/SplitKit.h
Message-ID: <20110404153215.376352A6C12D@llvm.org>

Author: stoklund
Date: Mon Apr  4 10:32:15 2011
New Revision: 128821

URL: http://llvm.org/viewvc/llvm-project?rev=128821&view=rev
Log:
Stop caching basic block index ranges now that SlotIndexes can keep up.

Modified:
    llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/CodeGen/SplitKit.h

Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=128821&r1=128820&r2=128821&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Mon Apr  4 10:32:15 2011
@@ -518,11 +518,21 @@
       return getMBBRange(MBB->getNumber());
     }
 
+    /// Returns the first index in the given basic block number.
+    SlotIndex getMBBStartIdx(unsigned Num) const {
+      return getMBBRange(Num).first;
+    }
+
     /// Returns the first index in the given basic block.
     SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
       return getMBBRange(mbb).first;
     }
 
+    /// Returns the last index in the given basic block number.
+    SlotIndex getMBBEndIdx(unsigned Num) const {
+      return getMBBRange(Num).second;
+    }
+
     /// Returns the last index in the given basic block.
     SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
       return getMBBRange(mbb).second;

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=128821&r1=128820&r2=128821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Apr  4 10:32:15 2011
@@ -433,7 +433,7 @@
 
     // Interference for the live-in value.
     if (BI.LiveIn) {
-      if (Intf.first() <= BI.Start)
+      if (Intf.first() <= Indexes->getMBBStartIdx(BC.Number))
         BC.Entry = SpillPlacement::MustSpill, Ins += BI.Uses;
       else if (!BI.Uses)
         BC.Entry = SpillPlacement::PrefSpill;
@@ -525,17 +525,19 @@
     if (!BI.LiveOut || !RegOut)
       continue;
 
+    SlotIndex Start, Stop;
+    tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
     Intf.moveToBlock(BI.MBB->getNumber());
     DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
                  << Bundles->getBundle(BI.MBB->getNumber(), 1)
-                 << " [" << BI.Start << ';' << BI.LastSplitPoint << '-'
-                 << BI.Stop << ") intf [" << Intf.first() << ';' << Intf.last()
+                 << " [" << Start << ';' << BI.LastSplitPoint << '-'
+                 << Stop << ") intf [" << Intf.first() << ';' << Intf.last()
                  << ')');
 
     // The interference interval should either be invalid or overlap MBB.
-    assert((!Intf.hasInterference() || Intf.first() < BI.Stop)
+    assert((!Intf.hasInterference() || Intf.first() < Stop)
            && "Bad interference");
-    assert((!Intf.hasInterference() || Intf.last() > BI.Start)
+    assert((!Intf.hasInterference() || Intf.last() > Start)
            && "Bad interference");
 
     // Check interference leaving the block.
@@ -553,14 +555,14 @@
       }
       if (!BI.LiveThrough) {
         DEBUG(dbgs() << ", not live-through.\n");
-        SE->useIntv(SE->enterIntvBefore(BI.Def), BI.Stop);
+        SE->useIntv(SE->enterIntvBefore(BI.Def), Stop);
         continue;
       }
       if (!RegIn) {
         // Block is live-through, but entry bundle is on the stack.
         // Reload just before the first use.
         DEBUG(dbgs() << ", not live-in, enter before first use.\n");
-        SE->useIntv(SE->enterIntvBefore(BI.FirstUse), BI.Stop);
+        SE->useIntv(SE->enterIntvBefore(BI.FirstUse), Stop);
         continue;
       }
       DEBUG(dbgs() << ", live-through.\n");
@@ -573,7 +575,7 @@
     if (!BI.LiveThrough && Intf.last() <= BI.Def) {
       // The interference doesn't reach the outgoing segment.
       DEBUG(dbgs() << " doesn't affect def from " << BI.Def << '\n');
-      SE->useIntv(BI.Def, BI.Stop);
+      SE->useIntv(BI.Def, Stop);
       continue;
     }
 
@@ -601,7 +603,7 @@
         SlotIndex SegStart = SE->enterIntvBefore(Use);
         assert(SegStart >= Intf.last() && "Couldn't avoid interference");
         assert(SegStart < BI.LastSplitPoint && "Impossible split point");
-        SE->useIntv(SegStart, BI.Stop);
+        SE->useIntv(SegStart, Stop);
         continue;
       }
     }
@@ -623,10 +625,12 @@
       continue;
 
     // We have an incoming register. Check for interference.
+    SlotIndex Start, Stop;
+    tie(Start, Stop) = Indexes->getMBBRange(BI.MBB);
     Intf.moveToBlock(BI.MBB->getNumber());
     DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
-                 << " -> BB#" << BI.MBB->getNumber() << " [" << BI.Start << ';'
-                 << BI.LastSplitPoint << '-' << BI.Stop << ')');
+                 << " -> BB#" << BI.MBB->getNumber() << " [" << Start << ';'
+                 << BI.LastSplitPoint << '-' << Stop << ')');
 
     // Check interference entering the block.
     if (!Intf.hasInterference()) {
@@ -637,7 +641,7 @@
         // Block is live-through without interference.
         if (RegOut) {
           DEBUG(dbgs() << ", no uses, live-through.\n");
-          SE->useIntv(BI.Start, BI.Stop);
+          SE->useIntv(Start, Stop);
         } else {
           DEBUG(dbgs() << ", no uses, stack-out.\n");
           SE->leaveIntvAtTop(*BI.MBB);
@@ -646,7 +650,7 @@
       }
       if (!BI.LiveThrough) {
         DEBUG(dbgs() << ", killed in block.\n");
-        SE->useIntv(BI.Start, SE->leaveIntvAfter(BI.Kill));
+        SE->useIntv(Start, SE->leaveIntvAfter(BI.Kill));
         continue;
       }
       if (!RegOut) {
@@ -654,7 +658,7 @@
         // Spill immediately after the last use.
         if (BI.LastUse < BI.LastSplitPoint) {
           DEBUG(dbgs() << ", uses, stack-out.\n");
-          SE->useIntv(BI.Start, SE->leaveIntvAfter(BI.LastUse));
+          SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse));
           continue;
         }
         // The last use is after the last split point, it is probably an
@@ -662,7 +666,7 @@
         DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point "
                      << BI.LastSplitPoint << ", stack-out.\n");
         SlotIndex SegEnd = SE->leaveIntvBefore(BI.LastSplitPoint);
-        SE->useIntv(BI.Start, SegEnd);
+        SE->useIntv(Start, SegEnd);
         // Run a double interval from the split to the last use.
         // This makes it possible to spill the complement without affecting the
         // indirect branch.
@@ -671,7 +675,7 @@
       }
       // Register is live-through.
       DEBUG(dbgs() << ", uses, live-through.\n");
-      SE->useIntv(BI.Start, BI.Stop);
+      SE->useIntv(Start, Stop);
       continue;
     }
 
@@ -681,7 +685,7 @@
     if (!BI.LiveThrough && Intf.first() >= BI.Kill) {
       // The interference doesn't reach the outgoing segment.
       DEBUG(dbgs() << " doesn't affect kill at " << BI.Kill << '\n');
-      SE->useIntv(BI.Start, BI.Kill);
+      SE->useIntv(Start, BI.Kill);
       continue;
     }
 
@@ -703,7 +707,7 @@
       DEBUG(dbgs() << ", free use at " << *UI << ".\n");
       SlotIndex SegEnd = SE->leaveIntvAfter(Use);
       assert(SegEnd <= Intf.first() && "Couldn't avoid interference");
-      SE->useIntv(BI.Start, SegEnd);
+      SE->useIntv(Start, SegEnd);
       continue;
     }
 

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=128821&r1=128820&r2=128821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Mon Apr  4 10:32:15 2011
@@ -118,7 +118,8 @@
   for (;;) {
     BlockInfo BI;
     BI.MBB = MFI;
-    tie(BI.Start, BI.Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
+    SlotIndex Start, Stop;
+    tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
 
     // The last split point is the latest possible insertion point that dominates
     // all successor blocks. If interference reaches LastSplitPoint, it is not
@@ -126,12 +127,12 @@
     // outgoing bundle.
     MachineBasicBlock::iterator LSP = LIS.getLastSplitPoint(*CurLI, BI.MBB);
     if (LSP == BI.MBB->end())
-      BI.LastSplitPoint = BI.Stop;
+      BI.LastSplitPoint = Stop;
     else
       BI.LastSplitPoint = LIS.getInstructionIndex(LSP);
 
     // LVI is the first live segment overlapping MBB.
-    BI.LiveIn = LVI->start <= BI.Start;
+    BI.LiveIn = LVI->start <= Start;
     if (!BI.LiveIn)
       BI.Def = LVI->start;
 
@@ -139,19 +140,19 @@
     BI.Uses = hasUses(MFI);
     if (BI.Uses && UseI != UseE) {
       BI.FirstUse = *UseI;
-      assert(BI.FirstUse >= BI.Start);
+      assert(BI.FirstUse >= Start);
       do ++UseI;
-      while (UseI != UseE && *UseI < BI.Stop);
+      while (UseI != UseE && *UseI < Stop);
       BI.LastUse = UseI[-1];
-      assert(BI.LastUse < BI.Stop);
+      assert(BI.LastUse < Stop);
     }
 
     // Look for gaps in the live range.
     bool hasGap = false;
     BI.LiveOut = true;
-    while (LVI->end < BI.Stop) {
+    while (LVI->end < Stop) {
       SlotIndex LastStop = LVI->end;
-      if (++LVI == LVE || LVI->start >= BI.Stop) {
+      if (++LVI == LVE || LVI->start >= Stop) {
         BI.Kill = LastStop;
         BI.LiveOut = false;
         break;
@@ -177,11 +178,11 @@
       break;
 
     // Live segment ends exactly at Stop. Move to the next segment.
-    if (LVI->end == BI.Stop && ++LVI == LVE)
+    if (LVI->end == Stop && ++LVI == LVE)
       break;
 
     // Pick the next basic block.
-    if (LVI->start < BI.Stop)
+    if (LVI->start < Stop)
       ++MFI;
     else
       MFI = LIS.getMBBFromIndex(LVI->start);

Modified: llvm/trunk/lib/CodeGen/SplitKit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=128821&r1=128820&r2=128821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.h (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.h Mon Apr  4 10:32:15 2011
@@ -73,8 +73,6 @@
   ///
   struct BlockInfo {
     MachineBasicBlock *MBB;
-    SlotIndex Start;      ///< Beginining of block.
-    SlotIndex Stop;       ///< End of block.
     SlotIndex FirstUse;   ///< First instr using current reg.
     SlotIndex LastUse;    ///< Last instr using current reg.
     SlotIndex Kill;       ///< Interval end point inside block.



From joerg at bec.de  Mon Apr  4 10:58:30 2011
From: joerg at bec.de (Joerg Sonnenberger)
Date: Mon, 04 Apr 2011 15:58:30 -0000
Subject: [llvm-commits] [llvm] r128822 - in /llvm/trunk/lib/Target/X86:
 X86InstrFormats.td X86InstrInfo.h X86MCCodeEmitter.cpp
Message-ID: <20110404155830.C21862A6C12C@llvm.org>

Author: joerg
Date: Mon Apr  4 10:58:30 2011
New Revision: 128822

URL: http://llvm.org/viewvc/llvm-project?rev=128822&view=rev
Log:
Expand Op0Mask by one bit in preparation for the PadLock prefixes.
Define most shift masks incrementally to reduce the redundant
hard-coding. Introduce new shift for the VEX flags to replace the
magic constant 32 in various places.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrFormats.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=128822&r1=128821&r2=128822&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Apr  4 10:58:30 2011
@@ -91,21 +91,21 @@
 class LOCK   { bit hasLockPrefix = 1; }
 class SegFS  { bits<2> SegOvrBits = 1; }
 class SegGS  { bits<2> SegOvrBits = 2; }
-class TB     { bits<4> Prefix = 1; }
-class REP    { bits<4> Prefix = 2; }
-class D8     { bits<4> Prefix = 3; }
-class D9     { bits<4> Prefix = 4; }
-class DA     { bits<4> Prefix = 5; }
-class DB     { bits<4> Prefix = 6; }
-class DC     { bits<4> Prefix = 7; }
-class DD     { bits<4> Prefix = 8; }
-class DE     { bits<4> Prefix = 9; }
-class DF     { bits<4> Prefix = 10; }
-class XD     { bits<4> Prefix = 11; }
-class XS     { bits<4> Prefix = 12; }
-class T8     { bits<4> Prefix = 13; }
-class TA     { bits<4> Prefix = 14; }
-class TF     { bits<4> Prefix = 15; }
+class TB     { bits<5> Prefix = 1; }
+class REP    { bits<5> Prefix = 2; }
+class D8     { bits<5> Prefix = 3; }
+class D9     { bits<5> Prefix = 4; }
+class DA     { bits<5> Prefix = 5; }
+class DB     { bits<5> Prefix = 6; }
+class DC     { bits<5> Prefix = 7; }
+class DD     { bits<5> Prefix = 8; }
+class DE     { bits<5> Prefix = 9; }
+class DF     { bits<5> Prefix = 10; }
+class XD     { bits<5> Prefix = 11; }
+class XS     { bits<5> Prefix = 12; }
+class T8     { bits<5> Prefix = 13; }
+class TA     { bits<5> Prefix = 14; }
+class TF     { bits<5> Prefix = 15; }
 class VEX    { bit hasVEXPrefix = 1; }
 class VEX_W  { bit hasVEX_WPrefix = 1; }
 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
@@ -136,7 +136,7 @@
   bit hasOpSizePrefix = 0;  // Does this inst have a 0x66 prefix?
   bit hasAdSizePrefix = 0;  // Does this inst have a 0x67 prefix?
 
-  bits<4> Prefix = 0;       // Which prefix byte does this inst have?
+  bits<5> Prefix = 0;       // Which prefix byte does this inst have?
   bit hasREX_WPrefix  = 0;  // Does this inst require the REX.W prefix?
   FPFormat FPForm = NotFP;  // What flavor of FP instruction is this?
   bit hasLockPrefix = 0;    // Does this inst have a 0xF0 prefix?
@@ -154,20 +154,20 @@
   let TSFlags{5-0}   = FormBits;
   let TSFlags{6}     = hasOpSizePrefix;
   let TSFlags{7}     = hasAdSizePrefix;
-  let TSFlags{11-8}  = Prefix;
-  let TSFlags{12}    = hasREX_WPrefix;
-  let TSFlags{15-13} = ImmT.Value;
-  let TSFlags{18-16} = FPForm.Value;
-  let TSFlags{19}    = hasLockPrefix;
-  let TSFlags{21-20} = SegOvrBits;
-  let TSFlags{23-22} = ExeDomain.Value;
-  let TSFlags{31-24} = Opcode;
-  let TSFlags{32}    = hasVEXPrefix;
-  let TSFlags{33}    = hasVEX_WPrefix;
-  let TSFlags{34}    = hasVEX_4VPrefix;
-  let TSFlags{35}    = hasVEX_i8ImmReg;
-  let TSFlags{36}    = hasVEX_L;
-  let TSFlags{37}    = has3DNow0F0FOpcode;
+  let TSFlags{12-8}  = Prefix;
+  let TSFlags{13}    = hasREX_WPrefix;
+  let TSFlags{16-14} = ImmT.Value;
+  let TSFlags{19-17} = FPForm.Value;
+  let TSFlags{20}    = hasLockPrefix;
+  let TSFlags{22-21} = SegOvrBits;
+  let TSFlags{24-23} = ExeDomain.Value;
+  let TSFlags{32-25} = Opcode;
+  let TSFlags{33}    = hasVEXPrefix;
+  let TSFlags{34}    = hasVEX_WPrefix;
+  let TSFlags{35}    = hasVEX_4VPrefix;
+  let TSFlags{36}    = hasVEX_i8ImmReg;
+  let TSFlags{37}    = hasVEX_L;
+  let TSFlags{38}    = has3DNow0F0FOpcode;
 }
 
 class PseudoI<dag oops, dag iops, list<dag> pattern>

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=128822&r1=128821&r2=128822&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Mon Apr  4 10:58:30 2011
@@ -347,7 +347,7 @@
     // set, there is no prefix byte for obtaining a multibyte opcode.
     //
     Op0Shift    = 8,
-    Op0Mask     = 0xF << Op0Shift,
+    Op0Mask     = 0x1F << Op0Shift,
 
     // TB - TwoByte - Set if this instruction has a two byte opcode, which
     // starts with a 0x0F byte before the real opcode.
@@ -380,13 +380,13 @@
     // etc. We only cares about REX.W and REX.R bits and only the former is
     // statically determined.
     //
-    REXShift    = 12,
+    REXShift    = Op0Shift + 5,
     REX_W       = 1 << REXShift,
 
     //===------------------------------------------------------------------===//
     // This three-bit field describes the size of an immediate operand.  Zero is
     // unused so that we can tell if we forgot to set a value.
-    ImmShift = 13,
+    ImmShift = REXShift + 1,
     ImmMask    = 7 << ImmShift,
     Imm8       = 1 << ImmShift,
     Imm8PCRel  = 2 << ImmShift,
@@ -400,7 +400,7 @@
     // FP Instruction Classification...  Zero is non-fp instruction.
 
     // FPTypeMask - Mask for all of the FP types...
-    FPTypeShift = 16,
+    FPTypeShift = ImmShift + 3,
     FPTypeMask  = 7 << FPTypeShift,
 
     // NotFP - The default, set for instructions that do not use FP registers.
@@ -433,25 +433,26 @@
     SpecialFP  = 7 << FPTypeShift,
 
     // Lock prefix
-    LOCKShift = 19,
+    LOCKShift = FPTypeShift + 3,
     LOCK = 1 << LOCKShift,
 
     // Segment override prefixes. Currently we just need ability to address
     // stuff in gs and fs segments.
-    SegOvrShift = 20,
+    SegOvrShift = LOCKShift + 1,
     SegOvrMask  = 3 << SegOvrShift,
     FS          = 1 << SegOvrShift,
     GS          = 2 << SegOvrShift,
 
-    // Execution domain for SSE instructions in bits 22, 23.
-    // 0 in bits 22-23 means normal, non-SSE instruction.
-    SSEDomainShift = 22,
+    // Execution domain for SSE instructions in bits 23, 24.
+    // 0 in bits 23-24 means normal, non-SSE instruction.
+    SSEDomainShift = SegOvrShift + 2,
 
-    OpcodeShift   = 24,
+    OpcodeShift   = SSEDomainShift + 2,
     OpcodeMask    = 0xFF << OpcodeShift,
 
     //===------------------------------------------------------------------===//
     /// VEX - The opcode prefix used by AVX instructions
+    VEXShift = OpcodeShift + 8,
     VEX         = 1U << 0,
 
     /// VEX_W - Has a opcode specific functionality, but is used in the same
@@ -549,7 +550,7 @@
     case X86II::MRMDestMem:
       return 0;
     case X86II::MRMSrcMem: {
-      bool HasVEX_4V = (TSFlags >> 32) & X86II::VEX_4V;
+      bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V;
       unsigned FirstMemOp = 1;
       if (HasVEX_4V)
         ++FirstMemOp;// Skip the register source (which is encoded in VEX_VVVV).

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=128822&r1=128821&r2=128822&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Mon Apr  4 10:58:30 2011
@@ -382,7 +382,7 @@
                                            const TargetInstrDesc &Desc,
                                            raw_ostream &OS) const {
   bool HasVEX_4V = false;
-  if ((TSFlags >> 32) & X86II::VEX_4V)
+  if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
     HasVEX_4V = true;
 
   // VEX_R: opcode externsion equivalent to REX.R in
@@ -446,10 +446,10 @@
   if (TSFlags & X86II::OpSize)
     VEX_PP = 0x01;
 
-  if ((TSFlags >> 32) & X86II::VEX_W)
+  if ((TSFlags >> X86II::VEXShift) & X86II::VEX_W)
     VEX_W = 1;
 
-  if ((TSFlags >> 32) & X86II::VEX_L)
+  if ((TSFlags >> X86II::VEXShift) & X86II::VEX_L)
     VEX_L = 1;
 
   switch (TSFlags & X86II::Op0Mask) {
@@ -518,7 +518,7 @@
 
     // If the last register should be encoded in the immediate field
     // do not use any bit from VEX prefix to this register, ignore it
-    if ((TSFlags >> 32) & X86II::VEX_I8IMM)
+    if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM)
       NumOps--;
 
     for (; CurOp != NumOps; ++CurOp) {
@@ -819,9 +819,9 @@
   // It uses the VEX.VVVV field?
   bool HasVEX_4V = false;
 
-  if ((TSFlags >> 32) & X86II::VEX)
+  if ((TSFlags >> X86II::VEXShift) & X86II::VEX)
     HasVEXPrefix = true;
-  if ((TSFlags >> 32) & X86II::VEX_4V)
+  if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V)
     HasVEX_4V = true;
 
   
@@ -837,7 +837,7 @@
   
   unsigned char BaseOpcode = X86II::getBaseOpcodeFor(TSFlags);
   
-  if ((TSFlags >> 32) & X86II::Has3DNow0F0FOpcode)
+  if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
     BaseOpcode = 0x0F;   // Weird 3DNow! encoding.
   
   unsigned SrcRegNum = 0;
@@ -994,7 +994,7 @@
   if (CurOp != NumOps) {
     // The last source register of a 4 operand instruction in AVX is encoded
     // in bits[7:4] of a immediate byte, and bits[3:0] are ignored.
-    if ((TSFlags >> 32) & X86II::VEX_I8IMM) {
+    if ((TSFlags >> X86II::VEXShift) & X86II::VEX_I8IMM) {
       const MCOperand &MO = MI.getOperand(CurOp++);
       bool IsExtReg =
         X86InstrInfo::isX86_64ExtendedReg(MO.getReg());
@@ -1017,7 +1017,7 @@
     }
   }
 
-  if ((TSFlags >> 32) & X86II::Has3DNow0F0FOpcode)
+  if ((TSFlags >> X86II::VEXShift) & X86II::Has3DNow0F0FOpcode)
     EmitByte(X86II::getBaseOpcodeFor(TSFlags), CurByte, OS);
   
 



From joerg at bec.de  Mon Apr  4 11:25:38 2011
From: joerg at bec.de (Joerg Sonnenberger)
Date: Mon, 04 Apr 2011 16:25:38 -0000
Subject: [llvm-commits] [llvm] r128823 -
	/llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
Message-ID: <20110404162538.D33A72A6C12C@llvm.org>

Author: joerg
Date: Mon Apr  4 11:25:38 2011
New Revision: 128823

URL: http://llvm.org/viewvc/llvm-project?rev=128823&view=rev
Log:
Use array_lengthof

Modified:
    llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp

Modified: llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp?rev=128823&r1=128822&r2=128823&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp (original)
+++ llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp Mon Apr  4 11:25:38 2011
@@ -18,6 +18,7 @@
 #include "X86DisassemblerTables.h"
 
 #include "TableGenBackend.h"
+#include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Format.h"
 
@@ -267,7 +268,7 @@
 DisassemblerTables::DisassemblerTables() {
   unsigned i;
   
-  for (i = 0; i < sizeof(Tables) / sizeof(Tables[0]); i++) {
+  for (i = 0; i < array_lengthof(Tables); i++) {
     Tables[i] = new ContextDecision;
     memset(Tables[i], 0, sizeof(ContextDecision));
   }
@@ -278,7 +279,7 @@
 DisassemblerTables::~DisassemblerTables() {
   unsigned i;
   
-  for (i = 0; i < sizeof(Tables) / sizeof(Tables[0]); i++)
+  for (i = 0; i < array_lengthof(Tables); i++)
     delete Tables[i];
 }
   



From baldrick at free.fr  Mon Apr  4 11:48:17 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 04 Apr 2011 16:48:17 -0000
Subject: [llvm-commits] [dragonegg] r128824 - /dragonegg/trunk/Convert.cpp
Message-ID: <20110404164817.655AA2A6C12C@llvm.org>

Author: baldrick
Date: Mon Apr  4 11:48:17 2011
New Revision: 128824

URL: http://llvm.org/viewvc/llvm-project?rev=128824&view=rev
Log:
Fix another class of Fortran failures: when passing 2D arrays with
unknown size two parameters are declared: a pointer to the array
and an integer holding the stride.  If the Fortran front-end knows
that the stride is not used then it doesn't bother to provide a
value for it in calls.  As far as I can see GCC doesn't try to pass
anything special (like zero) in this case: the callee just gets some
random value.  Emulate this by passing 'undef' for the missing call
argument(s).

Modified:
    dragonegg/trunk/Convert.cpp

Modified: dragonegg/trunk/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/Convert.cpp?rev=128824&r1=128823&r2=128824&view=diff
==============================================================================
--- dragonegg/trunk/Convert.cpp (original)
+++ dragonegg/trunk/Convert.cpp Mon Apr  4 11:48:17 2011
@@ -2871,6 +2871,15 @@
     }
   }
 
+  // Unlike LLVM, GCC does not require that call statements provide a value for
+  // every function argument (it passes rubbish for arguments with no value).
+  // To get the same effect we pass 'undef' for any unspecified arguments.
+  PFTy = cast<PointerType>(Callee->getType());
+  FTy = cast<FunctionType>(PFTy->getElementType());
+  if (CallOperands.size() < FTy->getNumParams())
+    for (unsigned i = CallOperands.size(), e = FTy->getNumParams(); i !=e; ++i)
+      CallOperands.push_back(UndefValue::get(FTy->getParamType(i)));
+
   Value *Call;
   if (!LandingPad) {
     Call = Builder.CreateCall(Callee, CallOperands.begin(), CallOperands.end());



From joerg at bec.de  Mon Apr  4 11:58:14 2011
From: joerg at bec.de (Joerg Sonnenberger)
Date: Mon, 04 Apr 2011 16:58:14 -0000
Subject: [llvm-commits] [llvm] r128826 - in /llvm/trunk:
 lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
 lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
 lib/Target/X86/X86CodeEmitter.cpp lib/Target/X86/X86InstrFormats.td
 lib/Target/X86/X86InstrInfo.h lib/Target/X86/X86InstrSystem.td
 lib/Target/X86/X86MCCodeEmitter.cpp test/MC/X86/padlock.s
 utils/TableGen/DisassemblerEmitter.cpp
 utils/TableGen/X86DisassemblerTables.cpp
 utils/TableGen/X86DisassemblerTables.h
 utils/TableGen/X86RecognizableInstr.cpp
Message-ID: <20110404165814.212962A6C12C@llvm.org>

Author: joerg
Date: Mon Apr  4 11:58:13 2011
New Revision: 128826

URL: http://llvm.org/viewvc/llvm-project?rev=128826&view=rev
Log:
Add support for the VIA PadLock instructions.

Added:
    llvm/trunk/test/MC/X86/padlock.s
Modified:
    llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
    llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
    llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
    llvm/trunk/lib/Target/X86/X86InstrFormats.td
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/lib/Target/X86/X86InstrSystem.td
    llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
    llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
    llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
    llvm/trunk/utils/TableGen/X86DisassemblerTables.h
    llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp

Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c?rev=128826&r1=128825&r2=128826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.c Mon Apr  4 11:58:13 2011
@@ -75,6 +75,12 @@
   case THREEBYTE_3A:
     decision = &THREEBYTE3A_SYM;
     break;
+  case THREEBYTE_A6:
+    decision = &THREEBYTEA6_SYM;
+    break;
+  case THREEBYTE_A7:
+    decision = &THREEBYTEA7_SYM;
+    break;
   }
   
   return decision->opcodeDecisions[insnContext].modRMDecisions[opcode].
@@ -115,6 +121,12 @@
   case THREEBYTE_3A:
     dec = &THREEBYTE3A_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
     break;
+  case THREEBYTE_A6:
+    dec = &THREEBYTEA6_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
+    break;
+  case THREEBYTE_A7:
+    dec = &THREEBYTEA7_SYM.opcodeDecisions[insnContext].modRMDecisions[opcode];
+    break;
   }
   
   switch (dec->modrm_type) {
@@ -580,6 +592,24 @@
         return -1;
       
       insn->opcodeType = THREEBYTE_3A;
+    } else if (current == 0xa6) {
+      dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
+      
+      insn->threeByteEscape = current;
+      
+      if (consumeByte(insn, &current))
+        return -1;
+      
+      insn->opcodeType = THREEBYTE_A6;
+    } else if (current == 0xa7) {
+      dbgprintf(insn, "Found a three-byte escape prefix (0x%hhx)", current);
+      
+      insn->threeByteEscape = current;
+      
+      if (consumeByte(insn, &current))
+        return -1;
+      
+      insn->opcodeType = THREEBYTE_A7;
     } else {
       dbgprintf(insn, "Didn't find a three-byte escape prefix");
       

Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h?rev=128826&r1=128825&r2=128826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoderCommon.h Mon Apr  4 11:58:13 2011
@@ -30,6 +30,8 @@
 #define TWOBYTE_SYM       x86DisassemblerTwoByteOpcodes
 #define THREEBYTE38_SYM   x86DisassemblerThreeByte38Opcodes
 #define THREEBYTE3A_SYM   x86DisassemblerThreeByte3AOpcodes
+#define THREEBYTEA6_SYM   x86DisassemblerThreeByteA6Opcodes
+#define THREEBYTEA7_SYM   x86DisassemblerThreeByteA7Opcodes
 
 #define INSTRUCTIONS_STR  "x86DisassemblerInstrSpecifiers"
 #define CONTEXTS_STR      "x86DisassemblerContexts"
@@ -37,6 +39,8 @@
 #define TWOBYTE_STR       "x86DisassemblerTwoByteOpcodes"
 #define THREEBYTE38_STR   "x86DisassemblerThreeByte38Opcodes"
 #define THREEBYTE3A_STR   "x86DisassemblerThreeByte3AOpcodes"
+#define THREEBYTEA6_STR   "x86DisassemblerThreeByteA6Opcodes"
+#define THREEBYTEA7_STR   "x86DisassemblerThreeByteA7Opcodes"
 
 /*
  * Attributes of an instruction that must be known before the opcode can be
@@ -119,7 +123,9 @@
   ONEBYTE       = 0,
   TWOBYTE       = 1,
   THREEBYTE_38  = 2,
-  THREEBYTE_3A  = 3
+  THREEBYTE_3A  = 3,
+  THREEBYTE_A6  = 4,
+  THREEBYTE_A7  = 5
 } OpcodeType;
 
 /*

Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=128826&r1=128825&r2=128826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Mon Apr  4 11:58:13 2011
@@ -652,6 +652,8 @@
   case X86II::TB:  // Two-byte opcode prefix
   case X86II::T8:  // 0F 38
   case X86II::TA:  // 0F 3A
+  case X86II::A6:  // 0F A6
+  case X86II::A7:  // 0F A7
     Need0FPrefix = true;
     break;
   case X86II::TF: // F2 0F 38
@@ -695,6 +697,12 @@
   case X86II::TA:    // 0F 3A
     MCE.emitByte(0x3A);
     break;
+  case X86II::A6:    // 0F A6
+    MCE.emitByte(0xA6);
+    break;
+  case X86II::A7:    // 0F A7
+    MCE.emitByte(0xA7);
+    break;
   }
 
   // If this is a two-address instruction, skip one of the register operands.

Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=128826&r1=128825&r2=128826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Apr  4 11:58:13 2011
@@ -105,7 +105,9 @@
 class XS     { bits<5> Prefix = 12; }
 class T8     { bits<5> Prefix = 13; }
 class TA     { bits<5> Prefix = 14; }
-class TF     { bits<5> Prefix = 15; }
+class A6     { bits<5> Prefix = 15; }
+class A7     { bits<5> Prefix = 16; }
+class TF     { bits<5> Prefix = 17; }
 class VEX    { bit hasVEXPrefix = 1; }
 class VEX_W  { bit hasVEX_WPrefix = 1; }
 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=128826&r1=128825&r2=128826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Mon Apr  4 11:58:13 2011
@@ -368,11 +368,12 @@
     // floating point operations performed in the SSE registers.
     XD = 11 << Op0Shift,  XS = 12 << Op0Shift,
 
-    // T8, TA - Prefix after the 0x0F prefix.
+    // T8, TA, A6, A7 - Prefix after the 0x0F prefix.
     T8 = 13 << Op0Shift,  TA = 14 << Op0Shift,
+    A6 = 15 << Op0Shift,  A7 = 16 << Op0Shift,
 
     // TF - Prefix before and after 0x0F
-    TF = 15 << Op0Shift,
+    TF = 17 << Op0Shift,
 
     //===------------------------------------------------------------------===//
     // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.

Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=128826&r1=128825&r2=128826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Mon Apr  4 11:58:13 2011
@@ -398,3 +398,23 @@
 
 let Uses = [RDX, RAX, RCX] in
   def XSETBV : I<0x01, MRM_D1, (outs), (ins), "xsetbv", []>, TB;
+
+//===----------------------------------------------------------------------===//
+// VIA PadLock crypto instructions
+let Defs = [RAX, RDI], Uses = [RDX, RDI] in
+  def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7;
+
+let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in {
+  def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7;
+  def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7;
+  def XCRYPTCTR : I<0xd8, RawFrm, (outs), (ins), "xcryptctr", []>, A7;
+  def XCRYPTCFB : I<0xe0, RawFrm, (outs), (ins), "xcryptcfb", []>, A7;
+  def XCRYPTOFB : I<0xe8, RawFrm, (outs), (ins), "xcryptofb", []>, A7;
+}
+
+let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
+  def XSHA1 : I<0xc8, RawFrm, (outs), (ins), "xsha1", []>, A6;
+  def XSHA256 : I<0xd0, RawFrm, (outs), (ins), "xsha256", []>, A6;
+}
+let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
+  def MONTMUL : I<0xc0, RawFrm, (outs), (ins), "montmul", []>, A6;

Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=128826&r1=128825&r2=128826&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Mon Apr  4 11:58:13 2011
@@ -470,6 +470,8 @@
   case X86II::XD:  // F2 0F
     VEX_PP = 0x3;
     break;
+  case X86II::A6:  // Bypass: Not used by VEX
+  case X86II::A7:  // Bypass: Not used by VEX
   case X86II::TB:  // Bypass: Not used by VEX
   case 0:
     break;  // No prefix!
@@ -742,6 +744,8 @@
   case X86II::TB:  // Two-byte opcode prefix
   case X86II::T8:  // 0F 38
   case X86II::TA:  // 0F 3A
+  case X86II::A6:  // 0F A6
+  case X86II::A7:  // 0F A7
     Need0FPrefix = true;
     break;
   case X86II::TF: // F2 0F 38
@@ -786,6 +790,12 @@
   case X86II::TA:    // 0F 3A
     EmitByte(0x3A, CurByte, OS);
     break;
+  case X86II::A6:    // 0F A6
+    EmitByte(0xA6, CurByte, OS);
+    break;
+  case X86II::A7:    // 0F A7
+    EmitByte(0xA7, CurByte, OS);
+    break;
   }
 }
 

Added: llvm/trunk/test/MC/X86/padlock.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/padlock.s?rev=128826&view=auto
==============================================================================
--- llvm/trunk/test/MC/X86/padlock.s (added)
+++ llvm/trunk/test/MC/X86/padlock.s Mon Apr  4 11:58:13 2011
@@ -0,0 +1,53 @@
+// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
+
+	xstore
+// CHECK: xstore
+// CHECK: encoding: [0x0f,0xa7,0xc0]
+
+	rep xcryptecb
+// CHECK: rep
+// CHECK: encoding: [0xf3]
+// CHECK: xcryptecb
+// CHECK: encoding: [0x0f,0xa7,0xc8]
+
+	rep xcryptcbc
+// CHECK: rep
+// CHECK: encoding: [0xf3]
+// CHECK: xcryptcbc
+// CHECK: encoding: [0x0f,0xa7,0xd0]
+
+	rep xcryptctr
+// CHECK: rep
+// CHECK: encoding: [0xf3]
+// CHECK: xcryptctr
+// CHECK: encoding: [0x0f,0xa7,0xd8]
+
+	rep xcryptcfb
+// CHECK: rep
+// CHECK: encoding: [0xf3]
+// CHECK: xcryptcfb
+// CHECK: encoding: [0x0f,0xa7,0xe0]
+
+	rep xcryptofb
+// CHECK: rep
+// CHECK: encoding: [0xf3]
+// CHECK: xcryptofb
+// CHECK: encoding: [0x0f,0xa7,0xe8]
+
+	rep xsha1
+// CHECK: rep
+// CHECK: encoding: [0xf3]
+// CHECK: xsha1
+// CHECK: encoding: [0x0f,0xa6,0xc8]
+
+	rep xsha256
+// CHECK: rep
+// CHECK: encoding: [0xf3]
+// CHECK: xsha256
+// CHECK: encoding: [0x0f,0xa6,0xd0]
+
+	rep montmul
+// CHECK: rep
+// CHECK: encoding: [0xf3]
+// CHECK: montmul
+// CHECK: encoding: [0x0f,0xa6,0xc0]

Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=128826&r1=128825&r2=128826&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp Mon Apr  4 11:58:13 2011
@@ -40,12 +40,12 @@
 ///   all cases as a 64-bit instruction with only OPSIZE set.  (The XS prefix
 ///   may have effects on its execution, but does not change the instruction
 ///   returned.)  This allows considerable space savings in other tables.
-/// - Four tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, and
-///   THREEBYTE3A_SYM) contain the hierarchy that the decoder traverses while
-///   decoding an instruction.  At the lowest level of this hierarchy are
-///   instruction UIDs, 16-bit integers that can be used to uniquely identify
-///   the instruction and correspond exactly to its position in the list of
-///   CodeGenInstructions for the target.
+/// - Six tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM,
+///   THREEBYTEA6_SYM, and THREEBYTEA7_SYM contain the hierarchy that the
+///   decoder traverses while decoding an instruction.  At the lowest level of
+///   this hierarchy are instruction UIDs, 16-bit integers that can be used to
+///   uniquely identify the instruction and correspond exactly to its position
+///   in the list of CodeGenInstructions for the target.
 /// - One table (INSTRUCTIONS_SYM) contains information about the operands of
 ///   each instruction and how to decode them.
 ///

Modified: llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp?rev=128826&r1=128825&r2=128826&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp (original)
+++ llvm/trunk/utils/TableGen/X86DisassemblerTables.cpp Mon Apr  4 11:58:13 2011
@@ -566,6 +566,8 @@
   emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
   emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
   emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
+  emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
+  emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
 }
 
 void DisassemblerTables::emit(raw_ostream &o) const {

Modified: llvm/trunk/utils/TableGen/X86DisassemblerTables.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86DisassemblerTables.h?rev=128826&r1=128825&r2=128826&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86DisassemblerTables.h (original)
+++ llvm/trunk/utils/TableGen/X86DisassemblerTables.h Mon Apr  4 11:58:13 2011
@@ -39,7 +39,9 @@
   /// [1] two-byte opcodes of the form 0f __
   /// [2] three-byte opcodes of the form 0f 38 __
   /// [3] three-byte opcodes of the form 0f 3a __
-  ContextDecision* Tables[4];
+  /// [4] three-byte opcodes of the form 0f a6 __
+  /// [5] three-byte opcodes of the form 0f a7 __
+  ContextDecision* Tables[6];
   
   /// The instruction information table
   std::vector<InstructionSpecifier> InstructionSpecifiers;
@@ -141,8 +143,9 @@
   ///     }
   ///   }
   ///
-  ///   NAME is the name of the ContextDecision (typically one of the four names 
-  ///   ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, and THREEBYTE3A_SYM from
+  ///   NAME is the name of the ContextDecision (typically one of the four names
+  ///   ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM,
+  ///   THREEBYTEA6_SYM, and THREEBYTEA7_SYM from
   ///   X86DisassemblerDecoderCommon.h).
   ///   IC is one of the contexts in InstructionContext.  There is an opcode
   ///   decision for each possible context.

Modified: llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp?rev=128826&r1=128825&r2=128826&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp (original)
+++ llvm/trunk/utils/TableGen/X86RecognizableInstr.cpp Mon Apr  4 11:58:13 2011
@@ -68,7 +68,7 @@
     DC = 7, DD = 8, DE = 9, DF = 10,
     XD = 11,  XS = 12,
     T8 = 13,  P_TA = 14,
-    P_0F_AE = 16, P_0F_01 = 17
+    A6 = 15,  A7 = 16
   };
 }
 
@@ -796,6 +796,22 @@
       filter = new DumbFilter();
     opcodeToSet = Opcode;
     break;
+  case X86Local::A6:
+    opcodeType = THREEBYTE_A6;
+    if (needsModRMForDecode(Form))
+      filter = new ModFilter(isRegFormat(Form));
+    else
+      filter = new DumbFilter();
+    opcodeToSet = Opcode;
+    break;
+  case X86Local::A7:
+    opcodeType = THREEBYTE_A7;
+    if (needsModRMForDecode(Form))
+      filter = new ModFilter(isRegFormat(Form));
+    else
+      filter = new DumbFilter();
+    opcodeToSet = Opcode;
+    break;
   case X86Local::D8:
   case X86Local::D9:
   case X86Local::DA:



From stoklund at 2pi.dk  Mon Apr  4 12:07:03 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 04 Apr 2011 17:07:03 -0000
Subject: [llvm-commits] [llvm] r128827 - in
 /llvm/trunk/test/CodeGen/PowerPC: 2010-05-03-retaddr1.ll indirectbr.ll
Message-ID: <20110404170703.E0F762A6C12C@llvm.org>

Author: stoklund
Date: Mon Apr  4 12:07:03 2011
New Revision: 128827

URL: http://llvm.org/viewvc/llvm-project?rev=128827&view=rev
Log:
Fix PowerPC tests to be register allocator independent.

Modified:
    llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
    llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll

Modified: llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll?rev=128827&r1=128826&r2=128827&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll Mon Apr  4 12:07:03 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 -regalloc=linearscan | FileCheck %s
 
 declare i8* @llvm.frameaddress(i32) nounwind readnone
 

Modified: llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll?rev=128827&r1=128826&r2=128827&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll Mon Apr  4 12:07:03 2011
@@ -43,13 +43,13 @@
 
 L1:                                               ; preds = %L2, %bb2
   %res.3 = phi i32 [ %phitmp, %L2 ], [ 2, %bb2 ]  ; <i32> [#uses=1]
-; PIC: addis r4, r4, ha16(Ltmp0-L0$pb)
-; PIC: li r6, lo16(Ltmp0-L0$pb)
-; PIC: add r4, r4, r6
-; PIC: stw r4
-; STATIC: li r5, lo16(Ltmp0)
-; STATIC: addis r5, r5, ha16(Ltmp0)
-; STATIC: stw r5
+; PIC: addis r[[R0:[0-9]+]], r{{[0-9]+}}, ha16(Ltmp0-L0$pb)
+; PIC: li r[[R1:[0-9]+]], lo16(Ltmp0-L0$pb)
+; PIC: add r[[R2:[0-9]+]], r[[R0]], r[[R1]]
+; PIC: stw r[[R2]]
+; STATIC: li r[[R0:[0-9]+]], lo16(Ltmp0)
+; STATIC: addis r[[R0]], r[[R0]], ha16(Ltmp0)
+; STATIC: stw r[[R0]]
   store i8* blockaddress(@foo, %L5), i8** @nextaddr, align 4
   ret i32 %res.3
 }



From stoklund at 2pi.dk  Mon Apr  4 12:07:06 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 04 Apr 2011 17:07:06 -0000
Subject: [llvm-commits] [llvm] r128828 -
	/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
Message-ID: <20110404170706.AD75A2A6C12D@llvm.org>

Author: stoklund
Date: Mon Apr  4 12:07:06 2011
New Revision: 128828

URL: http://llvm.org/viewvc/llvm-project?rev=128828&view=rev
Log:
Use X0 instead of R0 for the zero register on ppc64.

The 32-bit R0 cannot be used where a 64-bit register is expected.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=128828&r1=128827&r2=128828&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr  4 12:07:06 2011
@@ -899,7 +899,8 @@
     short Imm;
     if (isIntS16Immediate(CN, Imm)) {
       Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
-      Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
+      Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
+                             CN->getValueType(0));
       return true;
     }
 
@@ -947,7 +948,8 @@
   }
 
   // Otherwise, do it the hard way, using R0 as the base register.
-  Base = DAG.getRegister(PPC::R0, N.getValueType());
+  Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
+                         N.getValueType());
   Index = N;
   return true;
 }
@@ -4571,6 +4573,7 @@
   // registers without caring whether they're 32 or 64, but here we're
   // doing actual arithmetic on the addresses.
   bool is64bit = PPCSubTarget.isPPC64();
+  unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
 
   const BasicBlock *LLVM_BB = BB->getBasicBlock();
   MachineFunction *F = BB->getParent();
@@ -4634,8 +4637,7 @@
   //   bne- loopMBB
   //   fallthrough --> exitMBB
   //   srw dest, tmpDest, shift
-
-  if (ptrA!=PPC::R0) {
+  if (ptrA != ZeroReg) {
     Ptr1Reg = RegInfo.createVirtualRegister(RC);
     BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
       .addReg(ptrA).addReg(ptrB);
@@ -4665,7 +4667,7 @@
 
   BB = loopMBB;
   BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
-    .addReg(PPC::R0).addReg(PtrReg);
+    .addReg(ZeroReg).addReg(PtrReg);
   if (BinOpcode)
     BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
       .addReg(Incr2Reg).addReg(TmpDestReg);
@@ -4676,7 +4678,7 @@
   BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
     .addReg(Tmp3Reg).addReg(Tmp2Reg);
   BuildMI(BB, dl, TII->get(PPC::STWCX))
-    .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
+    .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
   BuildMI(BB, dl, TII->get(PPC::BCC))
     .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
   BB->addSuccessor(loopMBB);
@@ -4933,6 +4935,7 @@
     unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
     unsigned Ptr1Reg;
     unsigned TmpReg = RegInfo.createVirtualRegister(RC);
+    unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
     //  thisMBB:
     //   ...
     //   fallthrough --> loopMBB
@@ -4965,7 +4968,7 @@
     //   stwcx. tmpDest, ptr
     // exitBB:
     //   srw dest, tmpDest, shift
-    if (ptrA!=PPC::R0) {
+    if (ptrA != ZeroReg) {
       Ptr1Reg = RegInfo.createVirtualRegister(RC);
       BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
         .addReg(ptrA).addReg(ptrB);
@@ -5002,7 +5005,7 @@
 
     BB = loop1MBB;
     BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
-        .addReg(PPC::R0).addReg(PtrReg);
+        .addReg(ZeroReg).addReg(PtrReg);
     BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
         .addReg(TmpDestReg).addReg(MaskReg);
     BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
@@ -5018,7 +5021,7 @@
     BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
         .addReg(Tmp2Reg).addReg(NewVal3Reg);
     BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
-        .addReg(PPC::R0).addReg(PtrReg);
+        .addReg(ZeroReg).addReg(PtrReg);
     BuildMI(BB, dl, TII->get(PPC::BCC))
       .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
     BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
@@ -5027,7 +5030,7 @@
 
     BB = midMBB;
     BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
-      .addReg(PPC::R0).addReg(PtrReg);
+      .addReg(ZeroReg).addReg(PtrReg);
     BB->addSuccessor(exitMBB);
 
     //  exitMBB:



From stoklund at 2pi.dk  Mon Apr  4 12:07:09 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 04 Apr 2011 17:07:09 -0000
Subject: [llvm-commits] [llvm] r128829 - in /llvm/trunk/lib/Target/PowerPC:
 PPCInstr64Bit.td PPCInstrInfo.td
Message-ID: <20110404170709.582CF2A6C12E@llvm.org>

Author: stoklund
Date: Mon Apr  4 12:07:09 2011
New Revision: 128829

URL: http://llvm.org/viewvc/llvm-project?rev=128829&view=rev
Log:
PowerPC atomic pseudos clobber CR0, they don't read it.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=128829&r1=128828&r2=128829&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Mon Apr  4 12:07:09 2011
@@ -130,7 +130,7 @@
 
 // Atomic operations
 let usesCustomInserter = 1 in {
-  let Uses = [CR0] in {
+  let Defs = [CR0] in {
     def ATOMIC_LOAD_ADD_I64 : Pseudo<
       (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
       [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=128829&r1=128828&r2=128829&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Mon Apr  4 12:07:09 2011
@@ -550,7 +550,7 @@
 
 // Atomic operations
 let usesCustomInserter = 1 in {
-  let Uses = [CR0] in {
+  let Defs = [CR0] in {
     def ATOMIC_LOAD_ADD_I8 : Pseudo<
       (outs GPRC:$dst), (ins memrr:$ptr, GPRC:$incr), "",
       [(set GPRC:$dst, (atomic_load_add_8 xoaddr:$ptr, GPRC:$incr))]>;



From ahatanak at gmail.com  Mon Apr  4 12:11:07 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Mon, 04 Apr 2011 17:11:07 -0000
Subject: [llvm-commits] [llvm] r128830 - in /llvm/trunk/lib/Target/Mips:
 MipsISelDAGToDAG.cpp MipsISelLowering.cpp
Message-ID: <20110404171107.9FF322A6C12C@llvm.org>

Author: ahatanak
Date: Mon Apr  4 12:11:07 2011
New Revision: 128830

URL: http://llvm.org/viewvc/llvm-project?rev=128830&view=rev
Log:
Move transformation of JmpLink and related nodes done during instruction selection to Legalize phase.

Modified:
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=128830&r1=128829&r2=128830&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Mon Apr  4 12:11:07 2011
@@ -122,7 +122,8 @@
     if ((Addr.getOpcode() == ISD::TargetGlobalAddress) ||
         (Addr.getOpcode() == ISD::TargetConstantPool) ||
         (Addr.getOpcode() == ISD::TargetJumpTable) ||
-        (Addr.getOpcode() == ISD::TargetBlockAddress)) {
+        (Addr.getOpcode() == ISD::TargetBlockAddress) ||
+        (Addr.getOpcode() == ISD::TargetExternalSymbol)) {
       Base   = CurDAG->getRegister(Mips::GP, MVT::i32);
       Offset = Addr;
       return true;
@@ -444,61 +445,6 @@
         return ResNode;
       // Other cases are autogenerated.
       break;
-
-    /// Handle direct and indirect calls when using PIC. On PIC, when
-    /// GOT is smaller than about 64k (small code) the GA target is
-    /// loaded with only one instruction. Otherwise GA's target must
-    /// be loaded with 3 instructions.
-    case MipsISD::JmpLink: {
-      if (TM.getRelocationModel() == Reloc::PIC_) {
-        unsigned LastOpNum = Node->getNumOperands()-1;
-
-        SDValue Chain  = Node->getOperand(0);
-        SDValue Callee = Node->getOperand(1);
-        SDValue InFlag;
-
-        // Skip the incomming flag if present
-        if (Node->getOperand(LastOpNum).getValueType() == MVT::Glue)
-          LastOpNum--;
-
-        if ( (isa<GlobalAddressSDNode>(Callee)) ||
-             (isa<ExternalSymbolSDNode>(Callee)) )
-        {
-          /// Direct call for global addresses and external symbols
-          SDValue GPReg = CurDAG->getRegister(Mips::GP, MVT::i32);
-
-          // Use load to get GOT target
-          SDValue Ops[] = { Callee, GPReg, Chain };
-          SDValue Load = SDValue(CurDAG->getMachineNode(Mips::LW, dl, MVT::i32,
-                                     MVT::Other, Ops, 3), 0);
-          Chain = Load.getValue(1);
-
-          // Call target must be on T9
-          Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Load, InFlag);
-        } else
-          /// Indirect call
-          Chain = CurDAG->getCopyToReg(Chain, dl, Mips::T9, Callee, InFlag);
-
-        // Map the JmpLink operands to JALR
-        SDVTList NodeTys = CurDAG->getVTList(MVT::Other, MVT::Glue);
-        SmallVector<SDValue, 8> Ops;
-        Ops.push_back(CurDAG->getRegister(Mips::T9, MVT::i32));
-
-        for (unsigned i = 2, e = LastOpNum+1; i != e; ++i)
-          Ops.push_back(Node->getOperand(i));
-        Ops.push_back(Chain);
-        Ops.push_back(Chain.getValue(1));
-
-        // Emit Jump and Link Register
-        SDNode *ResNode = CurDAG->getMachineNode(Mips::JALR, dl, NodeTys,
-                                  &Ops[0], Ops.size());
-
-        // Replace Chain and InFlag
-        ReplaceUses(SDValue(Node, 0), SDValue(ResNode, 0));
-        ReplaceUses(SDValue(Node, 1), SDValue(ResNode, 1));
-        return ResNode;
-      }
-    }
   }
 
   // Select the default instruction

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=128830&r1=128829&r2=128830&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Apr  4 12:11:07 2011
@@ -1201,12 +1201,34 @@
   // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
   // node so that legalize doesn't hack it.
   unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
-  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
+  bool LoadSymAddr = false;
+
+  if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
     Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
-                                getPointerTy(), 0, OpFlag);
-  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
+                                        getPointerTy(), 0, OpFlag);
+    LoadSymAddr = true;
+  }
+  else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
     Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
                                 getPointerTy(), OpFlag);
+    LoadSymAddr = true;
+  }
+
+  // Create nodes that load address of callee and copy it to T9
+  if (IsPIC) {
+    if (LoadSymAddr) {
+      // load callee address
+      Callee = DAG.getLoad(MVT::i32, dl, Chain, Callee,
+                           MachinePointerInfo::getGOT(),
+                           false, false, 0);
+      Chain = Callee.getValue(1);
+    }
+
+    // copy to T9
+    Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0));
+    InFlag = Chain.getValue(1);
+    Callee = DAG.getRegister(Mips::T9, MVT::i32);
+  }
 
   // MipsJmpLink = #chain, #target_address, #opt_in_flags...
   //             = Chain, Callee, Reg#1, Reg#2, ...



From sabre at nondot.org  Mon Apr  4 12:17:57 2011
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 04 Apr 2011 17:17:57 -0000
Subject: [llvm-commits] [llvm] r128831 -
	/llvm/trunk/tools/macho-dump/macho-dump.cpp
Message-ID: <20110404171757.B4F522A6C12C@llvm.org>

Author: lattner
Date: Mon Apr  4 12:17:57 2011
New Revision: 128831

URL: http://llvm.org/viewvc/llvm-project?rev=128831&view=rev
Log:
silence an unused function warning.

Modified:
    llvm/trunk/tools/macho-dump/macho-dump.cpp

Modified: llvm/trunk/tools/macho-dump/macho-dump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/macho-dump/macho-dump.cpp?rev=128831&r1=128830&r2=128831&view=diff
==============================================================================
--- llvm/trunk/tools/macho-dump/macho-dump.cpp (original)
+++ llvm/trunk/tools/macho-dump/macho-dump.cpp Mon Apr  4 12:17:57 2011
@@ -49,6 +49,7 @@
 
 ///
 
+#if 0
 static int DumpHeader(MachOObject &Obj) {
   // Read the header.
   const macho::Header &Hdr = Obj.getHeader();
@@ -67,6 +68,7 @@
 
   return 0;
 }
+#endif
 
 static void DumpSegmentCommandData(StringRef Name,
                                    uint64_t VMAddr, uint64_t VMSize,



From bruno.cardoso at gmail.com  Mon Apr  4 12:18:19 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Mon, 04 Apr 2011 17:18:19 -0000
Subject: [llvm-commits] [llvm] r128832 - in /llvm/trunk:
 lib/Target/ARM/ARMAddressingModes.h lib/Target/ARM/ARMInstrFormats.td
 lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
 lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
 lib/Target/ARM/InstPrinter/ARMInstPrinter.h test/MC/ARM/arm_addrmode3.s
Message-ID: <20110404171819.6B84C2A6C12C@llvm.org>

Author: bruno
Date: Mon Apr  4 12:18:19 2011
New Revision: 128832

URL: http://llvm.org/viewvc/llvm-project?rev=128832&view=rev
Log:
- Implement asm parsing support for LDRSBT, LDRHT, LDRSHT and STRHT
  also fix the encoding of the later.
- Add a new encoding bit to describe the index mode used in AM3.
- Teach printAddrMode3Operand to check by the addressing mode which
  index mode to print.
- Testcases.

Added:
    llvm/trunk/test/MC/ARM/arm_addrmode3.s
Modified:
    llvm/trunk/lib/Target/ARM/ARMAddressingModes.h
    llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h

Modified: llvm/trunk/lib/Target/ARM/ARMAddressingModes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAddressingModes.h?rev=128832&r1=128831&r2=128832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAddressingModes.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMAddressingModes.h Mon Apr  4 12:18:19 2011
@@ -409,7 +409,7 @@
   // The first operand is always a Reg.  The second operand is a reg if in
   // reg/reg form, otherwise it's reg#0.  The third field encodes the operation
   // in bit 12, the immediate in bits 0-11, and the shift op in 13-15. The
-  // forth operand 16-17 encodes the index mode.
+  // fourth operand 16-17 encodes the index mode.
   //
   // If this addressing mode is a frame index (before prolog/epilog insertion
   // and code rewriting), this operand will have the form:  FI#, reg0, <offs>
@@ -446,12 +446,14 @@
   //
   // The first operand is always a Reg.  The second operand is a reg if in
   // reg/reg form, otherwise it's reg#0.  The third field encodes the operation
-  // in bit 8, the immediate in bits 0-7.
+  // in bit 8, the immediate in bits 0-7. The fourth operand 9-10 encodes the
+  // index mode.
 
   /// getAM3Opc - This function encodes the addrmode3 opc field.
-  static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset) {
+  static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset,
+                                   unsigned IdxMode = 0) {
     bool isSub = Opc == sub;
-    return ((int)isSub << 8) | Offset;
+    return ((int)isSub << 8) | Offset | (IdxMode << 9);
   }
   static inline unsigned char getAM3Offset(unsigned AM3Opc) {
     return AM3Opc & 0xFF;
@@ -459,6 +461,9 @@
   static inline AddrOpc getAM3Op(unsigned AM3Opc) {
     return ((AM3Opc >> 8) & 1) ? sub : add;
   }
+  static inline unsigned getAM3IdxMode(unsigned AM3Opc) {
+    return (AM3Opc >> 9);
+  }
 
   //===--------------------------------------------------------------------===//
   // Addressing Mode #4

Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=128832&r1=128831&r2=128832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Mon Apr  4 12:18:19 2011
@@ -577,6 +577,34 @@
   let Inst{15-12} = Rt;           // Rt
   let Inst{7-4}   = op;
 }
+
+// FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
+// but for now use this class for LDRSBT, LDRHT, LDSHT.
+class AI3ldstidxT<bits<4> op, bit op20, bit isLd, bit isPre, dag oops, dag iops,
+                  IndexMode im, Format f, InstrItinClass itin, string opc,
+                  string asm, string cstr, list<dag> pattern>
+  : I<oops, iops, AddrMode3, Size4Bytes, im, f, itin,
+      opc, asm, cstr, pattern> {
+  // {13}     1 == imm8, 0 == Rm
+  // {12-9}   Rn
+  // {8}      isAdd
+  // {7-4}    imm7_4/zero
+  // {3-0}    imm3_0/Rm
+  bits<14> addr;
+  bits<4> Rt;
+  let Inst{27-25} = 0b000;
+  let Inst{24}    = isPre;        // P bit
+  let Inst{23}    = addr{8};      // U bit
+  let Inst{22}    = addr{13};     // 1 == imm8, 0 == Rm
+  let Inst{20}    = op20;         // L bit
+  let Inst{19-16} = addr{12-9};   // Rn
+  let Inst{15-12} = Rt;           // Rt
+  let Inst{11-8}  = addr{7-4};    // imm7_4/zero
+  let Inst{7-4}   = op;
+  let Inst{3-0}   = addr{3-0};    // imm3_0/Rm
+  let AsmMatchConverter = "CvtLdWriteBackRegAddrMode3";
+}
+
 class AI3stridx<bits<4> op, bit isByte, bit isPre, dag oops, dag iops,
                 IndexMode im, Format f, InstrItinClass itin, string opc,
                 string asm, string cstr, list<dag> pattern>
@@ -649,12 +677,25 @@
                string opc, string asm, string cstr, list<dag> pattern>
   : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, itin,
       opc, asm, cstr,pattern> {
+  // {13}     1 == imm8, 0 == Rm
+  // {12-9}   Rn
+  // {8}      isAdd
+  // {7-4}    imm7_4/zero
+  // {3-0}    imm3_0/Rm
+  bits<14> addr;
+  bits<4> Rt;
+  let Inst{3-0}   = addr{3-0};    // imm3_0/Rm
   let Inst{4}     = 1;
   let Inst{5}     = 1; // H bit
   let Inst{6}     = 0; // S bit
   let Inst{7}     = 1;
+  let Inst{11-8}  = addr{7-4};    // imm7_4/zero
+  let Inst{15-12} = Rt;           // Rt
+  let Inst{19-16} = addr{12-9};   // Rn
   let Inst{20}    = 0; // L bit
   let Inst{21}    = 0; // W bit
+  let Inst{22}    = addr{13};     // 1 == imm8, 0 == Rm
+  let Inst{23}    = addr{8};      // U bit
   let Inst{24}    = 0; // P bit
   let Inst{27-25} = 0b000;
 }

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128832&r1=128831&r2=128832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Apr  4 12:18:19 2011
@@ -475,6 +475,17 @@
 
 // Define ARM specific addressing modes.
 
+def MemMode2AsmOperand : AsmOperandClass {
+  let Name = "MemMode2";
+  let SuperClasses = [];
+  let ParserMethod = "tryParseMemMode2Operand";
+}
+
+def MemMode3AsmOperand : AsmOperandClass {
+  let Name = "MemMode3";
+  let SuperClasses = [];
+  let ParserMethod = "tryParseMemMode3Operand";
+}
 
 // addrmode_imm12 := reg +/- imm12
 //
@@ -498,12 +509,6 @@
   let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
 }
 
-def MemMode2AsmOperand : AsmOperandClass {
-  let Name = "MemMode2";
-  let SuperClasses = [];
-  let ParserMethod = "tryParseMemMode2Operand";
-}
-
 // addrmode2 := reg +/- imm12
 //           := reg +/- reg shop imm
 //
@@ -530,6 +535,7 @@
                 ComplexPattern<i32, 3, "SelectAddrMode3", []> {
   let EncoderMethod = "getAddrMode3OpValue";
   let PrintMethod = "printAddrMode3Operand";
+  let ParserMatchClass = MemMode3AsmOperand;
   let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
 }
 
@@ -1763,22 +1769,19 @@
   let Inst{11-0} = addr{11-0};
   let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
 }
-def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
-                 (ins GPR:$base, am3offset:$offset), IndexModePost,
-                 LdMiscFrm, IIC_iLoad_bh_ru,
-                 "ldrsbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
+def LDRSBT : AI3ldstidxT<0b1101, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
+             (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
+             "ldrsbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
   let Inst{21} = 1; // overwrite
 }
-def LDRHT : AI3ldstidx<0b1011, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
-                 (ins GPR:$base, am3offset:$offset), IndexModePost,
-                 LdMiscFrm, IIC_iLoad_bh_ru,
-                 "ldrht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
+def LDRHT  : AI3ldstidxT<0b1011, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
+             (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
+             "ldrht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
   let Inst{21} = 1; // overwrite
 }
-def LDRSHT : AI3ldstidx<0b1111, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
-                 (ins GPR:$base, am3offset:$offset), IndexModePost,
-                 LdMiscFrm, IIC_iLoad_bh_ru,
-                 "ldrsht", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
+def LDRSHT : AI3ldstidxT<0b1111, 1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
+             (ins addrmode3:$addr), IndexModePost, LdMiscFrm, IIC_iLoad_bh_ru,
+             "ldrsht", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
   let Inst{21} = 1; // overwrite
 }
 }
@@ -1870,12 +1873,12 @@
   let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
 }
 
-def STRHT: AI3sthpo<(outs GPR:$base_wb),
-                    (ins GPR:$src, GPR:$base,am3offset:$offset),
+def STRHT: AI3sthpo<(outs GPR:$base_wb), (ins GPR:$Rt, addrmode3:$addr),
                     StMiscFrm, IIC_iStore_bh_ru,
-                    "strht", "\t$src, [$base], $offset", "$base = $base_wb",
+                    "strht", "\t$Rt, $addr", "$addr.base = $base_wb",
                     [/* For disassembly only; pattern left blank */]> {
   let Inst{21} = 1; // overwrite
+  let AsmMatchConverter = "CvtStWriteBackRegAddrMode3";
 }
 
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=128832&r1=128831&r2=128832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Apr  4 12:18:19 2011
@@ -98,12 +98,18 @@
     SmallVectorImpl<MCParsedAsmOperand*>&);
   OperandMatchResultTy tryParseMemMode2Operand(
     SmallVectorImpl<MCParsedAsmOperand*>&);
+  OperandMatchResultTy tryParseMemMode3Operand(
+    SmallVectorImpl<MCParsedAsmOperand*>&);
 
   // Asm Match Converter Methods
   bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
   bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
                                   const SmallVectorImpl<MCParsedAsmOperand*> &);
+  bool CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
+                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
+  bool CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
+                                  const SmallVectorImpl<MCParsedAsmOperand*> &);
 
 public:
   ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
@@ -371,6 +377,30 @@
 
     return true;
   }
+  bool isMemMode3() const {
+    if (getMemAddrMode() != ARMII::AddrMode3)
+      return false;
+
+    if (getMemOffsetIsReg()) {
+      if (getMemOffsetRegShifted())
+        return false; // No shift with offset reg allowed
+      return true;
+    }
+
+    if (getMemNegative() &&
+        !(getMemPostindexed() || getMemPreindexed()))
+      return false;
+
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
+    if (!CE) return false;
+    int64_t Value = CE->getValue();
+
+    // The offset must be in the range 0-255 (imm8).
+    if (Value > 255 || Value < -255)
+      return false;
+
+    return true;
+  }
   bool isMemMode5() const {
     if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
         getMemNegative())
@@ -539,6 +569,37 @@
                                           -Offset, ARM_AM::no_shift, IdxMode)));
   }
 
+  void addMemMode3Operands(MCInst &Inst, unsigned N) const {
+    assert(isMemMode3() && "Invalid mode or number of operands!");
+    Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
+    unsigned IdxMode = (getMemPreindexed() | getMemPostindexed() << 1);
+
+    if (getMemOffsetIsReg()) {
+      Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
+
+      ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
+      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(AMOpc, 0,
+                                                             IdxMode)));
+      return;
+    }
+
+    // Create a operand placeholder to always yield the same number of operands.
+    Inst.addOperand(MCOperand::CreateReg(0));
+
+    // FIXME: #-0 is encoded differently than #0. Does the parser preserve
+    // the difference?
+    const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemOffset());
+    assert(CE && "Non-constant mode 3 offset operand!");
+    int64_t Offset = CE->getValue();
+
+    if (Offset >= 0)
+      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::add,
+                                           Offset, IdxMode)));
+    else
+      Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM3Opc(ARM_AM::sub,
+                                           -Offset, IdxMode)));
+  }
+
   void addMemMode5Operands(MCInst &Inst, unsigned N) const {
     assert(N == 2 && isMemMode5() && "Invalid number of operands!");
 
@@ -1219,6 +1280,17 @@
   return MatchOperand_Success;
 }
 
+/// tryParseMemMode3Operand - Try to parse memory addressing mode 3 operand.
+ARMAsmParser::OperandMatchResultTy ARMAsmParser::
+tryParseMemMode3Operand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  assert(Parser.getTok().is(AsmToken::LBrac) && "Token is not a \"[\"");
+
+  if (ParseMemory(Operands, ARMII::AddrMode3))
+    return MatchOperand_NoMatch;
+
+  return MatchOperand_Success;
+}
+
 /// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
 /// when they refer multiple MIOperands inside a single one.
@@ -1249,6 +1321,36 @@
   return true;
 }
 
+/// CvtLdWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
+/// Needed here because the Asm Gen Matcher can't handle properly tied operands
+/// when they refer multiple MIOperands inside a single one.
+bool ARMAsmParser::
+CvtLdWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
+                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
+
+  // Create a writeback register dummy placeholder.
+  Inst.addOperand(MCOperand::CreateImm(0));
+
+  ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
+  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
+  return true;
+}
+
+/// CvtStWriteBackRegAddrMode3 - Convert parsed operands to MCInst.
+/// Needed here because the Asm Gen Matcher can't handle properly tied operands
+/// when they refer multiple MIOperands inside a single one.
+bool ARMAsmParser::
+CvtStWriteBackRegAddrMode3(MCInst &Inst, unsigned Opcode,
+                         const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
+  // Create a writeback register dummy placeholder.
+  Inst.addOperand(MCOperand::CreateImm(0));
+  ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
+  ((ARMOperand*)Operands[3])->addMemMode3Operands(Inst, 3);
+  ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
+  return true;
+}
+
 /// Parse an ARM memory expression, return false if successful else return true
 /// or an error.  The first token must be a '[' when called.
 ///
@@ -1310,6 +1412,10 @@
 
     const AsmToken &ExclaimTok = Parser.getTok();
     if (ExclaimTok.is(AsmToken::Exclaim)) {
+      // None of addrmode3 instruction uses "!"
+      if (AddrMode == ARMII::AddrMode3)
+        return true;
+
       WBOp = ARMOperand::CreateToken(ExclaimTok.getString(),
                                      ExclaimTok.getLoc());
       Writeback = true;
@@ -1350,6 +1456,11 @@
   if (!OffsetIsReg) {
     if (!Offset)
       Offset = MCConstantExpr::Create(0, getContext());
+  } else {
+    if (AddrMode == ARMII::AddrMode3 && OffsetRegShifted) {
+      Error(E, "shift amount not supported");
+      return true;
+    }
   }
 
   Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128832&r1=128831&r2=128832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Mon Apr  4 12:18:19 2011
@@ -1237,19 +1237,22 @@
          "Expect 1 reg operand followed by 1 imm operand");
 
   ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub;
+  unsigned IndexMode =
+                  (TID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
   if (getAM3IBit(insn) == 1) {
     MI.addOperand(MCOperand::CreateReg(0));
 
     // Disassemble the 8-bit immediate offset.
     unsigned Imm4H = (insn >> ARMII::ImmHiShift) & 0xF;
     unsigned Imm4L = insn & 0xF;
-    unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, (Imm4H << 4) | Imm4L);
+    unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, (Imm4H << 4) | Imm4L,
+                                        IndexMode);
     MI.addOperand(MCOperand::CreateImm(Offset));
   } else {
     // Disassemble the offset reg (Rm).
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        decodeRm(insn))));
-    unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0);
+    unsigned Offset = ARM_AM::getAM3Opc(AddrOpcode, 0, IndexMode);
     MI.addOperand(MCOperand::CreateImm(Offset));
   }
   OpIdx += 2;

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=128832&r1=128831&r2=128832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Mon Apr  4 12:18:19 2011
@@ -181,6 +181,10 @@
   }
 }
 
+//===--------------------------------------------------------------------===//
+// Addressing Mode #2
+//===--------------------------------------------------------------------===//
+
 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
                                                 raw_ostream &O) {
   const MCOperand &MO1 = MI->getOperand(Op);
@@ -276,11 +280,35 @@
     << " #" << ShImm;
 }
 
-void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned OpNum,
-                                           raw_ostream &O) {
-  const MCOperand &MO1 = MI->getOperand(OpNum);
-  const MCOperand &MO2 = MI->getOperand(OpNum+1);
-  const MCOperand &MO3 = MI->getOperand(OpNum+2);
+//===--------------------------------------------------------------------===//
+// Addressing Mode #3
+//===--------------------------------------------------------------------===//
+
+void ARMInstPrinter::printAM3PostIndexOp(const MCInst *MI, unsigned Op,
+                                         raw_ostream &O) {
+  const MCOperand &MO1 = MI->getOperand(Op);
+  const MCOperand &MO2 = MI->getOperand(Op+1);
+  const MCOperand &MO3 = MI->getOperand(Op+2);
+
+  O << "[" << getRegisterName(MO1.getReg()) << "], ";
+
+  if (MO2.getReg()) {
+    O << (char)ARM_AM::getAM3Op(MO3.getImm())
+    << getRegisterName(MO2.getReg());
+    return;
+  }
+
+  unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
+  O << '#'
+    << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
+    << ImmOffs;
+}
+
+void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
+                                                raw_ostream &O) {
+  const MCOperand &MO1 = MI->getOperand(Op);
+  const MCOperand &MO2 = MI->getOperand(Op+1);
+  const MCOperand &MO3 = MI->getOperand(Op+2);
 
   O << '[' << getRegisterName(MO1.getReg());
 
@@ -297,6 +325,18 @@
   O << ']';
 }
 
+void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
+                                           raw_ostream &O) {
+  const MCOperand &MO3 = MI->getOperand(Op+2);
+  unsigned IdxMode = ARM_AM::getAM3IdxMode(MO3.getImm());
+
+  if (IdxMode == ARMII::IndexModePost) {
+    printAM3PostIndexOp(MI, Op, O);
+    return;
+  }
+  printAM3PreOrOffsetIndexOp(MI, Op, O);
+}
+
 void ARMInstPrinter::printAddrMode3OffsetOperand(const MCInst *MI,
                                                  unsigned OpNum,
                                                  raw_ostream &O) {

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=128832&r1=128831&r2=128832&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Mon Apr  4 12:18:19 2011
@@ -49,9 +49,14 @@
                                   raw_ostream &O);
   void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
                                    raw_ostream &O);
+
   void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+  void printAM3PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+  void printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
+                                  raw_ostream &O);
   void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum,
                                    raw_ostream &O);
+
   void printLdStmModeOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printAddrMode5Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
   void printAddrMode6Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);

Added: llvm/trunk/test/MC/ARM/arm_addrmode3.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_addrmode3.s?rev=128832&view=auto
==============================================================================
--- llvm/trunk/test/MC/ARM/arm_addrmode3.s (added)
+++ llvm/trunk/test/MC/ARM/arm_addrmode3.s Mon Apr  4 12:18:19 2011
@@ -0,0 +1,18 @@
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
+
+@ CHECK: ldrsbt  r1, [r0], +r2 @ encoding: [0xd2,0x10,0xb0,0xe0]
+@ CHECK: ldrsbt  r1, [r0], #4 @ encoding: [0xd4,0x10,0xf0,0xe0]
+@ CHECK: ldrsht  r1, [r0], +r2 @ encoding: [0xf2,0x10,0xb0,0xe0]
+@ CHECK: ldrsht  r1, [r0], #4 @ encoding: [0xf4,0x10,0xf0,0xe0]
+@ CHECK: ldrht  r1, [r0], +r2 @ encoding: [0xb2,0x10,0xb0,0xe0]
+@ CHECK: ldrht  r1, [r0], #4 @ encoding: [0xb4,0x10,0xf0,0xe0]
+@ CHECK: strht  r1, [r0], +r2 @ encoding: [0xb2,0x10,0xa0,0xe0]
+@ CHECK: strht  r1, [r0], #4 @ encoding: [0xb4,0x10,0xe0,0xe0]
+        ldrsbt  r1, [r0], r2
+        ldrsbt  r1, [r0], #4
+        ldrsht  r1, [r0], r2
+        ldrsht  r1, [r0], #4
+        ldrht  r1, [r0], r2
+        ldrht  r1, [r0], #4
+        strht  r1, [r0], r2
+        strht  r1, [r0], #4



From echristo at apple.com  Mon Apr  4 12:36:11 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 04 Apr 2011 17:36:11 -0000
Subject: [llvm-commits] [llvm] r128834 -
	/llvm/trunk/tools/macho-dump/macho-dump.cpp
Message-ID: <20110404173611.566A62A6C12C@llvm.org>

Author: echristo
Date: Mon Apr  4 12:36:11 2011
New Revision: 128834

URL: http://llvm.org/viewvc/llvm-project?rev=128834&view=rev
Log:
Remove unused function.

Modified:
    llvm/trunk/tools/macho-dump/macho-dump.cpp

Modified: llvm/trunk/tools/macho-dump/macho-dump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/macho-dump/macho-dump.cpp?rev=128834&r1=128833&r2=128834&view=diff
==============================================================================
--- llvm/trunk/tools/macho-dump/macho-dump.cpp (original)
+++ llvm/trunk/tools/macho-dump/macho-dump.cpp Mon Apr  4 12:36:11 2011
@@ -49,27 +49,6 @@
 
 ///
 
-#if 0
-static int DumpHeader(MachOObject &Obj) {
-  // Read the header.
-  const macho::Header &Hdr = Obj.getHeader();
-  outs() << "('cputype', " << Hdr.CPUType << ")\n";
-  outs() << "('cpusubtype', " << Hdr.CPUSubtype << ")\n";
-  outs() << "('filetype', " << Hdr.FileType << ")\n";
-  outs() << "('num_load_commands', " << Hdr.NumLoadCommands << ")\n";
-  outs() << "('load_commands_size', " << Hdr.SizeOfLoadCommands << ")\n";
-  outs() << "('flag', " << Hdr.Flags << ")\n";
-
-  // Print extended header if 64-bit.
-  if (Obj.is64Bit()) {
-    const macho::Header64Ext &Hdr64 = Obj.getHeader64Ext();
-    outs() << "('reserved', " << Hdr64.Reserved << ")\n";
-  }
-
-  return 0;
-}
-#endif
-
 static void DumpSegmentCommandData(StringRef Name,
                                    uint64_t VMAddr, uint64_t VMSize,
                                    uint64_t FileOffset, uint64_t FileSize,



From echristo at apple.com  Mon Apr  4 12:41:04 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 04 Apr 2011 10:41:04 -0700
Subject: [llvm-commits] [llvm] r128831 -
 /llvm/trunk/tools/macho-dump/macho-dump.cpp
In-Reply-To: <20110404171757.B4F522A6C12C@llvm.org>
References: <20110404171757.B4F522A6C12C@llvm.org>
Message-ID: <83413884-FCB3-4907-AA69-5C39448CC62B@apple.com>


On Apr 4, 2011, at 10:17 AM, Chris Lattner wrote:

> Author: lattner
> Date: Mon Apr  4 12:17:57 2011
> New Revision: 128831
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=128831&view=rev
> Log:
> silence an unused function warning.

Thanks :)

I've removed the function in r128834.

-eric

From echristo at apple.com  Mon Apr  4 12:41:37 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 04 Apr 2011 10:41:37 -0700
Subject: [llvm-commits] [llvm] r128801 - in /llvm/trunk:
 include/llvm/Object/MachOObject.h lib/Object/MachOObject.cpp
 tools/macho-dump/macho-dump.cpp
In-Reply-To: <BANLkTinHMAcd5--sgJuQYVXXwGLXMKRVOw@mail.gmail.com>
References: <20110403235148.145CA2A6C12C@llvm.org>
	<BANLkTinHMAcd5--sgJuQYVXXwGLXMKRVOw@mail.gmail.com>
Message-ID: <83CA3D7A-4984-4542-9E17-FAEA492DA9DB@apple.com>


On Apr 4, 2011, at 2:27 AM, Frits van Bommel wrote:

> On Mon, Apr 4, 2011 at 1:51 AM, Eric Christopher <echristo at apple.com> wrote:
>> -  if (int Res = DumpHeader(*InputObject))
>> -    return Res;
> 
> This was the only use of that static function:
> 
> ../trunk/tools/macho-dump/macho-dump.cpp:52:12: warning: unused
> function 'DumpHeader' [-Wunused-function]
> static int DumpHeader(MachOObject &Obj) {
>           ^
> 1 warning generated.

Sorry about that. Fixed in r128834.

-eric

From stoklund at 2pi.dk  Mon Apr  4 12:57:26 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 04 Apr 2011 17:57:26 -0000
Subject: [llvm-commits] [llvm] r128835 -
	/llvm/trunk/test/CodeGen/PowerPC/Atomics-64.ll
Message-ID: <20110404175726.CAB492A6C12C@llvm.org>

Author: stoklund
Date: Mon Apr  4 12:57:26 2011
New Revision: 128835

URL: http://llvm.org/viewvc/llvm-project?rev=128835&view=rev
Log:
Disable the PowerPC/Atomics-64 test.

The code inserted by PPCTargetLowering::EmitInstrWithCustomInserter for ppc64 is
wrong, and I don't know how to fix it. It seems to be using the correct register
classes for pointers, but it inserts all 32-bit instructions.

Modified:
    llvm/trunk/test/CodeGen/PowerPC/Atomics-64.ll

Modified: llvm/trunk/test/CodeGen/PowerPC/Atomics-64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/Atomics-64.ll?rev=128835&r1=128834&r2=128835&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/Atomics-64.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/Atomics-64.ll Mon Apr  4 12:57:26 2011
@@ -1,5 +1,11 @@
-; RUN: llc < %s -march=ppc64
-; ModuleID = 'Atomics.c'
+; RUN: llc < %s -march=ppc64 -verify-machineinstrs
+;
+; This test is disabled until PPCISelLowering learns to insert proper 64-bit
+; code for ATOMIC_CMP_SWAP. Currently, it is inserting 32-bit instructions with
+; 64-bit operands which causes the machine code verifier to throw a tantrum.
+;
+; XFAIL: *
+
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128"
 target triple = "powerpc64-apple-darwin9"
 @sc = common global i8 0		; <i8*> [#uses=52]



From stoklund at 2pi.dk  Mon Apr  4 12:57:29 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 04 Apr 2011 17:57:29 -0000
Subject: [llvm-commits] [llvm] r128836 -
	/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
Message-ID: <20110404175729.8DB192A6C12D@llvm.org>

Author: stoklund
Date: Mon Apr  4 12:57:29 2011
New Revision: 128836

URL: http://llvm.org/viewvc/llvm-project?rev=128836&view=rev
Log:
Insert code in the right location when lowering PowerPC atomics.

This causes defs to dominate uses, no instructions after terminators, and other
goodness.

Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=128836&r1=128835&r2=128836&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr  4 12:57:29 2011
@@ -4687,7 +4687,8 @@
   //  exitMBB:
   //   ...
   BB = exitMBB;
-  BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
+  BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
+    .addReg(ShiftReg);
   return BB;
 }
 
@@ -5036,7 +5037,8 @@
     //  exitMBB:
     //   ...
     BB = exitMBB;
-    BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
+    BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
+      .addReg(ShiftReg);
   } else {
     llvm_unreachable("Unexpected instr type to insert");
   }



From dpatel at apple.com  Mon Apr  4 14:51:17 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 04 Apr 2011 19:51:17 -0000
Subject: [llvm-commits] [llvm] r128839 - /llvm/trunk/tools/opt/opt.cpp
Message-ID: <20110404195117.56EC22A6C12C@llvm.org>

Author: dpatel
Date: Mon Apr  4 14:51:17 2011
New Revision: 128839

URL: http://llvm.org/viewvc/llvm-project?rev=128839&view=rev
Log:
Update BreakpointPrinter to emit original function names only. 

Modified:
    llvm/trunk/tools/opt/opt.cpp

Modified: llvm/trunk/tools/opt/opt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=128839&r1=128838&r2=128839&view=diff
==============================================================================
--- llvm/trunk/tools/opt/opt.cpp (original)
+++ llvm/trunk/tools/opt/opt.cpp Mon Apr  4 14:51:17 2011
@@ -26,6 +26,7 @@
 #include "llvm/Target/TargetData.h"
 #include "llvm/Target/TargetLibraryInfo.h"
 #include "llvm/Target/TargetMachine.h"
+#include "llvm/ADT/StringSet.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Support/PassNameParser.h"
 #include "llvm/Support/Signals.h"
@@ -342,28 +343,43 @@
 
 char BasicBlockPassPrinter::ID = 0;
 
-struct BreakpointPrinter : public FunctionPass {
+struct BreakpointPrinter : public ModulePass {
   raw_ostream &Out;
   static char ID;
 
   BreakpointPrinter(raw_ostream &out)
-    : FunctionPass(ID), Out(out) {
+    : ModulePass(ID), Out(out) {
     }
 
-  virtual bool runOnFunction(Function &F) {
-    BasicBlock &EntryBB = F.getEntryBlock();
-    BasicBlock::const_iterator BI = EntryBB.end();
-    --BI;
-    do {
-      const Instruction *In = BI;
-      const DebugLoc DL = In->getDebugLoc();
-      if (!DL.isUnknown()) {
-        DIScope S(DL.getScope(getGlobalContext()));
-        Out << S.getFilename() << " " << DL.getLine() << "\n";
-        break;
+  void getContextName(DIDescriptor Context, std::string &N) {
+    if (Context.isNameSpace()) {
+      DINameSpace NS(Context);
+      if (!NS.getName().empty()) {
+        getContextName(NS.getContext(), N);
+        N = N + NS.getName().str() + "::";
+      }
+    } else if (Context.isType()) {
+      DIType TY(Context);
+      if (!TY.getName().empty()) {
+        getContextName(TY.getContext(), N);
+        N = N + TY.getName().str() + "::";
+      }
+    }
+  }
+
+  virtual bool runOnModule(Module &M) {
+    StringSet<> Processed;
+    if (NamedMDNode *NMD = M.getNamedMetadata("llvm.dbg.sp"))
+      for (unsigned i = 0, e = NMD->getNumOperands(); i != e; ++i) {
+        std::string Name;
+        DISubprogram SP(NMD->getOperand(i));
+        if (SP.Verify())
+          getContextName(SP.getContext(), Name);
+        Name = Name + SP.getDisplayName().str();
+        if (!Name.empty() && Processed.insert(Name)) {
+          Out << Name << "\n";
+        }
       }
-      --BI;
-    } while (BI != EntryBB.begin());
     return false;
   }
 



From nadav.rotem at intel.com  Mon Apr  4 15:06:18 2011
From: nadav.rotem at intel.com (Rotem, Nadav)
Date: Mon, 4 Apr 2011 23:06:18 +0300
Subject: [llvm-commits] [patch] Instcombine bug - transforms GEP/Bitcast on
 different address spaces
Message-ID: <6594DDFF12B03D4E89690887C248699402787A62CF@hasmsx504.ger.corp.intel.com>

Hi,

Please review the attached patch.

The attached patch fixes a bug in InstCombine. The pass optimizes gep(bitcast ) even when the bitcasts casts away address space info. We crash with an assert in this case.

The attached patch checks that the address space of the bitcasted pointer is the same as the gep ptr.

Nadav
---------------------------------------------------------------------
Intel Israel (74) Limited

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by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
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From johnny.chen at apple.com  Mon Apr  4 15:35:31 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Mon, 04 Apr 2011 20:35:31 -0000
Subject: [llvm-commits] [llvm] r128841 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
 test/MC/Disassembler/ARM/neon-tests.txt
Message-ID: <20110404203531.CD5492A6C12C@llvm.org>

Author: johnny
Date: Mon Apr  4 15:35:31 2011
New Revision: 128841

URL: http://llvm.org/viewvc/llvm-project?rev=128841&view=rev
Log:
Fix incorrect alignment for NEON VST2b32_UPD.

rdar://problem/9225433

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128841&r1=128840&r2=128841&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Mon Apr  4 15:35:31 2011
@@ -2167,7 +2167,7 @@
 // Correctly set VLD*/VST*'s TIED_TO GPR, as the asm printer needs it.
 static bool DisassembleNLdSt0(MCInst &MI, unsigned Opcode, uint32_t insn,
     unsigned short NumOps, unsigned &NumOpsAdded, bool Store, bool DblSpaced,
-    BO B) {
+    unsigned alignment, BO B) {
 
   const TargetInstrDesc &TID = ARMInsts[Opcode];
   const TargetOperandInfo *OpInfo = TID.OpInfo;
@@ -2211,9 +2211,10 @@
 
     assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
            OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
+    // addrmode6 := (ops GPR:$addr, i32imm)
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        Rn)));
-    MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
+    MI.addOperand(MCOperand::CreateImm(alignment)); // Alignment
     OpIdx += 2;
 
     if (WB) {
@@ -2261,9 +2262,10 @@
 
     assert((OpIdx+1) < NumOps && OpInfo[OpIdx].RegClass == ARM::GPRRegClassID &&
            OpInfo[OpIdx + 1].RegClass < 0 && "Addrmode #6 Operands expected");
+    // addrmode6 := (ops GPR:$addr, i32imm)
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        Rn)));
-    MI.addOperand(MCOperand::CreateImm(0)); // Alignment ignored?
+    MI.addOperand(MCOperand::CreateImm(alignment)); // Alignment
     OpIdx += 2;
 
     if (WB) {
@@ -2294,6 +2296,92 @@
   return true;
 }
 
+// A8.6.308, A8.6.311, A8.6.314, A8.6.317.
+static bool Align4OneLaneInst(unsigned elem, unsigned size,
+    unsigned index_align, unsigned & alignment) {
+  unsigned bits = 0;
+  switch (elem) {
+  default:
+    return false;
+  case 1:
+    // A8.6.308
+    if (size == 0)
+      return slice(index_align, 0, 0) == 0;
+    else if (size == 1) {
+      bits = slice(index_align, 1, 0);
+      if (bits != 0 && bits != 1)
+        return false;
+      if (bits == 1)
+        alignment = 16;
+      return true;
+    } else if (size == 2) {
+      bits = slice(index_align, 2, 0);
+      if (bits != 0 && bits != 3)
+        return false;
+      if (bits == 3)
+        alignment = 32;
+      return true;;
+    }
+    return true;
+  case 2:
+    // A8.6.311
+    if (size == 0) {
+      if (slice(index_align, 0, 0) == 1)
+        alignment = 16;
+      return true;
+    } if (size == 1) {
+      if (slice(index_align, 0, 0) == 1)
+        alignment = 32;
+      return true;
+    } else if (size == 2) {
+      if (slice(index_align, 1, 1) != 0)
+        return false;
+      if (slice(index_align, 0, 0) == 1)
+        alignment = 64;
+      return true;;
+    }
+    return true;
+  case 3:
+    // A8.6.314
+    if (size == 0) {
+      if (slice(index_align, 0, 0) != 0)
+        return false;
+      return true;
+    } if (size == 1) {
+      if (slice(index_align, 0, 0) != 0)
+        return false;
+      return true;
+      return true;
+    } else if (size == 2) {
+      if (slice(index_align, 1, 0) != 0)
+        return false;
+      return true;;
+    }
+    return true;
+  case 4:
+    // A8.6.317
+    if (size == 0) {
+      if (slice(index_align, 0, 0) == 1)
+        alignment = 32;
+      return true;
+    } if (size == 1) {
+      if (slice(index_align, 0, 0) == 1)
+        alignment = 64;
+      return true;
+    } else if (size == 2) {
+      bits = slice(index_align, 1, 0);
+      if (bits == 3)
+        return false;
+      if (bits == 1)
+        alignment = 64;
+      else if (bits == 2)
+        alignment = 128;
+      return true;;
+    }
+    return true;
+  }
+}
+
 // A7.7
 // If L (Inst{21}) == 0, store instructions.
 // Find out about double-spaced-ness of the Opcode and pass it on to
@@ -2303,11 +2391,33 @@
 
   const StringRef Name = ARMInsts[Opcode].Name;
   bool DblSpaced = false;
+  // 0 represents standard alignment, i.e., unaligned data access.
+  unsigned alignment = 0;
 
   if (Name.find("LN") != std::string::npos) {
     // To one lane instructions.
     // See, for example, 8.6.317 VLD4 (single 4-element structure to one lane).
 
+    unsigned elem = 0; // legal values: {1, 2, 3, 4}
+    if (Name.startswith("VST1") || Name.startswith("VLD1"))
+      elem = 1;
+
+    if (Name.startswith("VST2") || Name.startswith("VLD2"))
+      elem = 2;
+
+    if (Name.startswith("VST3") || Name.startswith("VLD3"))
+      elem = 3;
+
+    if (Name.startswith("VST4") || Name.startswith("VLD4"))
+      elem = 4;
+
+    // Utility function takes number of elements, size, and index_align.
+    if (!Align4OneLaneInst(elem,
+                           slice(insn, 11, 10),
+                           slice(insn, 7, 4),
+                           alignment))
+      return false;
+
     // <size> == 16 && Inst{5} == 1 --> DblSpaced = true
     if (Name.endswith("16") || Name.endswith("16_UPD"))
       DblSpaced = slice(insn, 5, 5) == 1;
@@ -2315,26 +2425,41 @@
     // <size> == 32 && Inst{6} == 1 --> DblSpaced = true
     if (Name.endswith("32") || Name.endswith("32_UPD"))
       DblSpaced = slice(insn, 6, 6) == 1;
-
   } else {
     // Multiple n-element structures with type encoded as Inst{11-8}.
     // See, for example, A8.6.316 VLD4 (multiple 4-element structures).
 
+    // Inst{5-4} encodes alignment.
+    switch (slice(insn, 5, 4)) {
+    default:
+      break;
+    case 1:
+      alignment = 64; break;
+    case 2:
+      alignment = 128; break;
+    case 3:
+      alignment = 256; break;
+    }
+
     // n == 2 && type == 0b1001 -> DblSpaced = true
     if (Name.startswith("VST2") || Name.startswith("VLD2"))
       DblSpaced = slice(insn, 11, 8) == 9;
 
     // n == 3 && type == 0b0101 -> DblSpaced = true
-    if (Name.startswith("VST3") || Name.startswith("VLD3"))
+    if (Name.startswith("VST3") || Name.startswith("VLD3")) {
+      // A8.6.313 & A8.6.395
+      if (slice(insn, 7, 6) == 3 && slice(insn, 5, 5) == 1)
+        return false;
+
       DblSpaced = slice(insn, 11, 8) == 5;
+    }
 
     // n == 4 && type == 0b0001 -> DblSpaced = true
     if (Name.startswith("VST4") || Name.startswith("VLD4"))
       DblSpaced = slice(insn, 11, 8) == 1;
-
   }
   return DisassembleNLdSt0(MI, Opcode, insn, NumOps, NumOpsAdded,
-                           slice(insn, 21, 21) == 0, DblSpaced, B);
+                           slice(insn, 21, 21) == 0, DblSpaced, alignment/8, B);
 }
 
 // VMOV (immediate)

Modified: llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt?rev=128841&r1=128840&r2=128841&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt Mon Apr  4 15:35:31 2011
@@ -68,3 +68,6 @@
 
 # CHECK:	vbic.i32	q2, #0xA900
 0x79 0x53 0x82 0xf3
+
+# CHECK:	vst2.32	{d16, d18}, [r2, :64], r2
+0x92 0x9 0x42 0xf4



From ahatanak at gmail.com  Mon Apr  4 16:00:10 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Mon, 4 Apr 2011 14:00:10 -0700
Subject: [llvm-commits] MIPS patch
In-Reply-To: <BANLkTi=4kbTWqgOgKBBBrmoBZDmFo5uyYw@mail.gmail.com>
References: <BANLkTi=4kbTWqgOgKBBBrmoBZDmFo5uyYw@mail.gmail.com>
Message-ID: <BANLkTi=-=4eOnSxQUSSyq_DhroxhutbRew@mail.gmail.com>

This patch fixes handling of functions with internal linkage.
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From stoklund at 2pi.dk  Mon Apr  4 16:00:00 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 04 Apr 2011 21:00:00 -0000
Subject: [llvm-commits] [llvm] r128844 - in /llvm/trunk/lib/CodeGen:
 SimpleRegisterCoalescing.cpp SimpleRegisterCoalescing.h
Message-ID: <20110404210000.1038C2A6C12C@llvm.org>

Author: stoklund
Date: Mon Apr  4 15:59:59 2011
New Revision: 128844

URL: http://llvm.org/viewvc/llvm-project?rev=128844&view=rev
Log:
Extract physreg joining policy to a separate method.

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=128844&r1=128843&r2=128844&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Apr  4 15:59:59 2011
@@ -913,6 +913,50 @@
   return removeIntervalIfEmpty(li, li_, tri_);
 }
 
+/// shouldJoinPhys - Return true if a copy involving a physreg should be joined.
+/// We need to be careful about coalescing a source physical register with a
+/// virtual register. Once the coalescing is done, it cannot be broken and these
+/// are not spillable! If the destination interval uses are far away, think
+/// twice about coalescing them!
+bool SimpleRegisterCoalescing::shouldJoinPhys(CoalescerPair &CP) {
+  if (DisablePhysicalJoin) {
+    DEBUG(dbgs() << "\tPhysreg joins disabled.\n");
+    return false;
+  }
+
+  // Only coalesce to allocatable physreg.
+  if (!li_->isAllocatable(CP.getDstReg())) {
+    DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
+    return false;  // Not coalescable.
+  }
+
+  // Don't join with physregs that have a ridiculous number of live
+  // ranges. The data structure performance is really bad when that
+  // happens.
+  if (li_->hasInterval(CP.getDstReg()) &&
+      li_->getInterval(CP.getDstReg()).ranges.size() > 1000) {
+    ++numAborts;
+    DEBUG(dbgs()
+          << "\tPhysical register live interval too complicated, abort!\n");
+    return false;
+  }
+
+  // FIXME: Why are we skipping this test for partial copies?
+  //        CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
+  if (!CP.isPartial()) {
+    LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg());
+
+    const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
+    unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
+    unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
+    if (Length > Threshold) {
+      ++numAborts;
+      DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
+      return false;
+    }
+  }
+  return true;
+}
 
 /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
 /// two virtual registers from different register classes.
@@ -985,27 +1029,25 @@
     return false;  // Not coalescable.
   }
 
-  if (DisablePhysicalJoin && CP.isPhys()) {
-    DEBUG(dbgs() << "\tPhysical joins disabled.\n");
-    return false;
-  }
-
-  DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), tri_));
+  DEBUG(dbgs() << "\tConsidering merging " << PrintReg(CP.getSrcReg(), tri_)
+               << " with " << PrintReg(CP.getDstReg(), tri_, CP.getSubIdx())
+               << "\n");
 
   // Enforce policies.
   if (CP.isPhys()) {
-    DEBUG(dbgs() <<" with physreg " << PrintReg(CP.getDstReg(), tri_) << "\n");
-    // Only coalesce to allocatable physreg.
-    if (!li_->isAllocatable(CP.getDstReg())) {
-      DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
-      return false;  // Not coalescable.
+    if (!shouldJoinPhys(CP)) {
+      // Before giving up coalescing, if definition of source is defined by
+      // trivial computation, try rematerializing it.
+      if (!CP.isFlipped() &&
+          ReMaterializeTrivialDef(li_->getInterval(CP.getSrcReg()), true,
+                                  CP.getDstReg(), 0, CopyMI))
+        return true;
+      return false;
     }
   } else {
-    DEBUG(dbgs() << " with " << PrintReg(CP.getDstReg(), tri_, CP.getSubIdx())
-                 << " to " << CP.getNewRC()->getName() << "\n");
-
     // Avoid constraining virtual register regclass too much.
     if (CP.isCrossClass()) {
+      DEBUG(dbgs() << "\tCross-class to " << CP.getNewRC()->getName() << ".\n");
       if (DisableCrossClassJoin) {
         DEBUG(dbgs() << "\tCross-class joins disabled.\n");
         return false;
@@ -1014,8 +1056,7 @@
                                  mri_->getRegClass(CP.getSrcReg()),
                                  mri_->getRegClass(CP.getDstReg()),
                                  CP.getNewRC())) {
-        DEBUG(dbgs() << "\tAvoid coalescing to constrained register class: "
-                     << CP.getNewRC()->getName() << ".\n");
+        DEBUG(dbgs() << "\tAvoid coalescing to constrained register class.\n");
         Again = true;  // May be possible to coalesce later.
         return false;
       }
@@ -1027,43 +1068,6 @@
       CP.flip();
   }
 
-  // We need to be careful about coalescing a source physical register with a
-  // virtual register. Once the coalescing is done, it cannot be broken and
-  // these are not spillable! If the destination interval uses are far away,
-  // think twice about coalescing them!
-  // FIXME: Why are we skipping this test for partial copies?
-  //        CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
-  if (!CP.isPartial() && CP.isPhys()) {
-    LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg());
-
-    // Don't join with physregs that have a ridiculous number of live
-    // ranges. The data structure performance is really bad when that
-    // happens.
-    if (li_->hasInterval(CP.getDstReg()) &&
-        li_->getInterval(CP.getDstReg()).ranges.size() > 1000) {
-      ++numAborts;
-      DEBUG(dbgs()
-           << "\tPhysical register live interval too complicated, abort!\n");
-      return false;
-    }
-
-    const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
-    unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
-    unsigned Length = li_->getApproximateInstructionCount(JoinVInt);
-    if (Length > Threshold) {
-      // Before giving up coalescing, if definition of source is defined by
-      // trivial computation, try rematerializing it.
-      if (!CP.isFlipped() &&
-          ReMaterializeTrivialDef(JoinVInt, true, CP.getDstReg(), 0, CopyMI))
-        return true;
-
-      ++numAborts;
-      DEBUG(dbgs() << "\tMay tie down a physical register, abort!\n");
-      Again = true;  // May be possible to coalesce later.
-      return false;
-    }
-  }
-
   // Okay, attempt to join these two intervals.  On failure, this returns false.
   // Otherwise, if one of the intervals being joined is a physreg, this method
   // always canonicalizes DstInt to be it.  The output "SrcInt" will not have

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=128844&r1=128843&r2=128844&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Mon Apr  4 15:59:59 2011
@@ -138,6 +138,9 @@
                                  unsigned DstReg, unsigned DstSubIdx,
                                  MachineInstr *CopyMI);
 
+    /// shouldJoinPhys - Return true if a physreg copy should be joined.
+    bool shouldJoinPhys(CoalescerPair &CP);
+
     /// isWinToJoinCrossClass - Return true if it's profitable to coalesce
     /// two virtual registers from different register classes.
     bool isWinToJoinCrossClass(unsigned SrcReg,



From stoklund at 2pi.dk  Mon Apr  4 16:00:03 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 04 Apr 2011 21:00:03 -0000
Subject: [llvm-commits] [llvm] r128845 - in /llvm/trunk:
 lib/CodeGen/LiveIntervalAnalysis.cpp lib/CodeGen/RegAllocLinearScan.cpp
 lib/CodeGen/SimpleRegisterCoalescing.cpp
 test/CodeGen/X86/2008-08-05-SpillerBug.ll
 test/CodeGen/X86/mcinst-lowering-cmp0.ll
Message-ID: <20110404210003.981302A6C12D@llvm.org>

Author: stoklund
Date: Mon Apr  4 16:00:03 2011
New Revision: 128845

URL: http://llvm.org/viewvc/llvm-project?rev=128845&view=rev
Log:
Allow coalescing with reserved physregs in certain cases:

When a virtual register has a single value that is defined as a copy of a
reserved register, permit that copy to be joined. These virtual register are
usually copies of the stack pointer:

  %vreg75<def> = COPY %ESP; GR32:%vreg75
  MOV32mr %vreg75, 1, %noreg, 0, %noreg, %vreg74<kill>
  MOV32mi %vreg75, 1, %noreg, 8, %noreg, 0
  MOV32mi %vreg75<kill>, 1, %noreg, 4, %noreg, 0
  CALLpcrel32 ...

Coalescing these virtual registers early decreases register pressure.
Previously, they were coalesced by RALinScan::attemptTrivialCoalescing after
register allocation was completed.

The lower register pressure causes the mcinst-lowering-cmp0.ll test case to fail
because it depends on linear scan spilling a particular register.

I am deleting 2008-08-05-SpillerBug.ll because it is counting the number of
instructions emitted, and its revision history shows the 'correct' count being
edited many times.

Removed:
    llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll
    llvm/trunk/test/CodeGen/X86/mcinst-lowering-cmp0.ll
Modified:
    llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp

Modified: llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp?rev=128845&r1=128844&r2=128845&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveIntervalAnalysis.cpp Mon Apr  4 16:00:03 2011
@@ -572,7 +572,7 @@
   if (TargetRegisterInfo::isVirtualRegister(MO.getReg()))
     handleVirtualRegisterDef(MBB, MI, MIIdx, MO, MOIdx,
                              getOrCreateInterval(MO.getReg()));
-  else if (allocatableRegs_[MO.getReg()]) {
+  else {
     MachineInstr *CopyMI = NULL;
     if (MI->isCopyLike())
       CopyMI = MI;

Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=128845&r1=128844&r2=128845&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Mon Apr  4 16:00:03 2011
@@ -572,7 +572,7 @@
 
   for (LiveIntervals::iterator i = li_->begin(), e = li_->end(); i != e; ++i) {
     if (TargetRegisterInfo::isPhysicalRegister(i->second->reg)) {
-      if (!i->second->empty()) {
+      if (!i->second->empty() && allocatableRegs_.test(i->second->reg)) {
         mri_->setPhysRegUsed(i->second->reg);
         fixed_.push_back(std::make_pair(i->second, i->second->begin()));
       }

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=128845&r1=128844&r2=128845&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Mon Apr  4 16:00:03 2011
@@ -919,13 +919,23 @@
 /// are not spillable! If the destination interval uses are far away, think
 /// twice about coalescing them!
 bool SimpleRegisterCoalescing::shouldJoinPhys(CoalescerPair &CP) {
+  bool Allocatable = li_->isAllocatable(CP.getDstReg());
+  LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg());
+
+  /// Always join simple intervals that are defined by a single copy from a
+  /// reserved register. This doesn't increase register pressure, so it is
+  /// always beneficial.
+  if (!Allocatable && CP.isFlipped() && JoinVInt.containsOneValue())
+    return true;
+
   if (DisablePhysicalJoin) {
     DEBUG(dbgs() << "\tPhysreg joins disabled.\n");
     return false;
   }
 
-  // Only coalesce to allocatable physreg.
-  if (!li_->isAllocatable(CP.getDstReg())) {
+  // Only coalesce to allocatable physreg, we don't want to risk modifying
+  // reserved registers.
+  if (!Allocatable) {
     DEBUG(dbgs() << "\tRegister is an unallocatable physreg.\n");
     return false;  // Not coalescable.
   }
@@ -944,8 +954,6 @@
   // FIXME: Why are we skipping this test for partial copies?
   //        CodeGen/X86/phys_subreg_coalesce-3.ll needs it.
   if (!CP.isPartial()) {
-    LiveInterval &JoinVInt = li_->getInterval(CP.getSrcReg());
-
     const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg());
     unsigned Threshold = allocatableRCRegs_[RC].count() * 2;
     unsigned Length = li_->getApproximateInstructionCount(JoinVInt);

Removed: llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll?rev=128844&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-08-05-SpillerBug.ll (removed)
@@ -1,44 +0,0 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -pre-RA-sched=list-burr -disable-fp-elim -stats |& grep asm-printer | grep 55
-; PR2568
-
- at g_3 = external global i16		; <i16*> [#uses=1]
- at g_5 = external global i32		; <i32*> [#uses=3]
-
-declare i32 @func_15(i16 signext , i16 signext , i32) nounwind 
-
-define void @func_9_entry_2E_ce(i8 %p_11) nounwind {
-newFuncRoot:
-	br label %entry.ce
-
-entry.ce.ret.exitStub:		; preds = %entry.ce
-	ret void
-
-entry.ce:		; preds = %newFuncRoot
-	load i16* @g_3, align 2		; <i16>:0 [#uses=1]
-	icmp sgt i16 %0, 0		; <i1>:1 [#uses=1]
-	zext i1 %1 to i32		; <i32>:2 [#uses=1]
-	load i32* @g_5, align 4		; <i32>:3 [#uses=4]
-	icmp ugt i32 %2, %3		; <i1>:4 [#uses=1]
-	zext i1 %4 to i32		; <i32>:5 [#uses=1]
-	icmp eq i32 %3, 0		; <i1>:6 [#uses=1]
-	%.0 = select i1 %6, i32 1, i32 %3		; <i32> [#uses=1]
-	urem i32 1, %.0		; <i32>:7 [#uses=2]
-	sext i8 %p_11 to i16		; <i16>:8 [#uses=1]
-	trunc i32 %3 to i16		; <i16>:9 [#uses=1]
-	tail call i32 @func_15( i16 signext  %8, i16 signext  %9, i32 1 ) nounwind 		; <i32>:10 [#uses=0]
-	load i32* @g_5, align 4		; <i32>:11 [#uses=1]
-	trunc i32 %11 to i16		; <i16>:12 [#uses=1]
-	tail call i32 @func_15( i16 signext  %12, i16 signext  1, i32 %7 ) nounwind 		; <i32>:13 [#uses=0]
-	sext i8 %p_11 to i32		; <i32>:14 [#uses=1]
-	%p_11.lobit = lshr i8 %p_11, 7		; <i8> [#uses=1]
-	%tmp = zext i8 %p_11.lobit to i32		; <i32> [#uses=1]
-	%tmp.not = xor i32 %tmp, 1		; <i32> [#uses=1]
-	%.015 = ashr i32 %14, %tmp.not		; <i32> [#uses=2]
-	icmp eq i32 %.015, 0		; <i1>:15 [#uses=1]
-	%.016 = select i1 %15, i32 1, i32 %.015		; <i32> [#uses=1]
-	udiv i32 %7, %.016		; <i32>:16 [#uses=1]
-	icmp ult i32 %5, %16		; <i1>:17 [#uses=1]
-	zext i1 %17 to i32		; <i32>:18 [#uses=1]
-	store i32 %18, i32* @g_5, align 4
-	br label %entry.ce.ret.exitStub
-}

Removed: llvm/trunk/test/CodeGen/X86/mcinst-lowering-cmp0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mcinst-lowering-cmp0.ll?rev=128844&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mcinst-lowering-cmp0.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mcinst-lowering-cmp0.ll (removed)
@@ -1,68 +0,0 @@
-; RUN: llc --show-mc-encoding -relocation-model=pic -disable-fp-elim -O3 < %s | FileCheck %s
-
-target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
-target triple = "i386-apple-darwin10.0.0"
-
-%struct.NSConstantString = type { i32*, i32, i8*, i32 }
-%struct._objc_module = type { i32, i32, i8*, %struct._objc_symtab* }
-%struct._objc_symtab = type { i32, i8*, i16, i16, [0 x i8*] }
-
-@"\01L_OBJC_IMAGE_INFO" = internal constant [2 x i32] [i32 0, i32 16], section "__OBJC, __image_info,regular" ; <[2 x i32]*> [#uses=1]
-@"\01L_OBJC_METH_VAR_NAME_" = internal global [4 x i8] c"foo\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[4 x i8]*> [#uses=1]
-@"\01L_OBJC_SELECTOR_REFERENCES_" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), section "__OBJC,__message_refs,literal_pointers,no_dead_strip", align 4 ; <i8**> [#uses=3]
- at __CFConstantStringClassReference = external global [0 x i32] ; <[0 x i32]*> [#uses=1]
- at .str = private constant [3 x i8] c"||\00"        ; <[3 x i8]*> [#uses=1]
- at _unnamed_cfstring_ = private constant %struct.NSConstantString { i32* getelementptr inbounds ([0 x i32]* @__CFConstantStringClassReference, i32 0, i32 0), i32 1992, i8* getelementptr inbounds ([3 x i8]* @.str, i32 0, i32 0), i32 2 }, section "__DATA,__cfstring" ; <%struct.NSConstantString*> [#uses=1]
-@"\01L_OBJC_METH_VAR_NAME_1" = internal global [5 x i8] c"baz:\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[5 x i8]*> [#uses=1]
-@"\01L_OBJC_SELECTOR_REFERENCES_2" = internal global i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), section "__OBJC,__message_refs,literal_pointers,no_dead_strip", align 4 ; <i8**> [#uses=2]
-@"\01L_OBJC_METH_VAR_NAME_3" = internal global [4 x i8] c"bar\00", section "__TEXT,__cstring,cstring_literals", align 1 ; <[4 x i8]*> [#uses=1]
-@"\01L_OBJC_SELECTOR_REFERENCES_4" = internal global i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_3", i32 0, i32 0), section "__OBJC,__message_refs,literal_pointers,no_dead_strip", align 4 ; <i8**> [#uses=2]
-@"\01L_OBJC_CLASS_NAME_" = internal global [1 x i8] zeroinitializer, section "__TEXT,__cstring,cstring_literals", align 1 ; <[1 x i8]*> [#uses=1]
-@"\01L_OBJC_MODULES" = internal global %struct._objc_module { i32 7, i32 16, i8* getelementptr inbounds ([1 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), %struct._objc_symtab* null }, section "__OBJC,__module_info,regular,no_dead_strip", align 4 ; <%struct._objc_module*> [#uses=1]
- at llvm.used = appending global [9 x i8*] [i8* bitcast ([2 x i32]* @"\01L_OBJC_IMAGE_INFO" to i8*), i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_" to i8*), i8* getelementptr inbounds ([5 x i8]* @"\01L_OBJC_METH_VAR_NAME_1", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_2" to i8*), i8* getelementptr inbounds ([4 x i8]* @"\01L_OBJC_METH_VAR_NAME_3", i32 0, i32 0), i8* bitcast (i8** @"\01L_OBJC_SELECTOR_REFERENCES_4" to i8*), i8* getelementptr inbounds ([1 x i8]* @"\01L_OBJC_CLASS_NAME_", i32 0, i32 0), i8* bitcast (%struct._objc_module* @"\01L_OBJC_MODULES" to i8*)], section "llvm.metadata" ; <[9 x i8*]*> [#uses=0]
-
-define void @f0(i8* nocapture %a, i8* nocapture %b) nounwind optsize ssp {
-entry:
-  %call = tail call i32 (...)* @get_name() nounwind optsize ; <i32> [#uses=2]
-  %conv = inttoptr i32 %call to i8*               ; <i8*> [#uses=1]
-  %call1 = tail call i32 (...)* @get_dict() nounwind optsize ; <i32> [#uses=2]
-  %conv2 = inttoptr i32 %call1 to i8*             ; <i8*> [#uses=2]
-
-; Check that we lower to the short form of cmpl, which has an 8-bit immediate.
-;
-; CHECK: cmpl  $0, -16(%ebp)           ## 4-byte Folded Reload
-; CHECK:                               ## encoding: [0x83,0x7d,0xf0,0x00]
-; rdar://7999130
-  %cmp = icmp eq i32 %call1, 0                    ; <i1> [#uses=1]
-  br i1 %cmp, label %if.end, label %if.then
-
-if.then:                                          ; preds = %entry
-  %tmp5 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_" ; <i8*> [#uses=1]
-  %call6 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %conv2, i8* %tmp5) nounwind optsize ; <i8*> [#uses=1]
-  %tmp7 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_2" ; <i8*> [#uses=1]
-  %call820 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call6, i8* %tmp7, i8* bitcast (%struct.NSConstantString* @_unnamed_cfstring_ to i8*)) nounwind optsize ; <i8*> [#uses=0]
-  br label %if.end
-
-if.end:                                           ; preds = %entry, %if.then
-  %tmp10 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_" ; <i8*> [#uses=1]
-  %call11 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %conv2, i8* %tmp10) nounwind optsize ; <i8*> [#uses=1]
-  %tmp12 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_4" ; <i8*> [#uses=1]
-  %call13 = tail call i8* (i8*, i8*, ...)* @objc_msgSend(i8* %call11, i8* %tmp12) nounwind optsize ; <i8*> [#uses=0]
-  %cmp15 = icmp eq i32 %call, 0                   ; <i1> [#uses=1]
-  br i1 %cmp15, label %if.end19, label %if.then17
-
-if.then17:                                        ; preds = %if.end
-  tail call void (...)* @f1(i8* %conv) nounwind optsize
-  ret void
-
-if.end19:                                         ; preds = %if.end
-  ret void
-}
-
-declare i32 @get_name(...) optsize
-
-declare i32 @get_dict(...) optsize
-
-declare i8* @objc_msgSend(i8*, i8*, ...)
-
-declare void @f1(...) optsize



From stoklund at 2pi.dk  Mon Apr  4 16:07:46 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 04 Apr 2011 14:07:46 -0700
Subject: [llvm-commits] [llvm] r128822 - in /llvm/trunk/lib/Target/X86:
 X86InstrFormats.td X86InstrInfo.h X86MCCodeEmitter.cpp
In-Reply-To: <20110404155830.C21862A6C12C@llvm.org>
References: <20110404155830.C21862A6C12C@llvm.org>
Message-ID: <74E52A33-43D2-4E7D-BBF5-7CF75C486C3A@2pi.dk>


On Apr 4, 2011, at 8:58 AM, Joerg Sonnenberger wrote:

> -    OpcodeShift   = 24,
> +    OpcodeShift   = SSEDomainShift + 2,
>     OpcodeMask    = 0xFF << OpcodeShift,

This shift now overflows an unsigned. Please use a 64-bit immediate.

/jakob


From joerg at bec.de  Mon Apr  4 16:38:17 2011
From: joerg at bec.de (Joerg Sonnenberger)
Date: Mon, 04 Apr 2011 21:38:17 -0000
Subject: [llvm-commits] [llvm] r128847 -
	/llvm/trunk/lib/Target/X86/X86InstrInfo.h
Message-ID: <20110404213817.C8C942A6C12C@llvm.org>

Author: joerg
Date: Mon Apr  4 16:38:17 2011
New Revision: 128847

URL: http://llvm.org/viewvc/llvm-project?rev=128847&view=rev
Log:
Make OpcodeMask an unsigned long long literal to deal with overflow.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.h

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=128847&r1=128846&r2=128847&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Mon Apr  4 16:38:17 2011
@@ -449,7 +449,7 @@
     SSEDomainShift = SegOvrShift + 2,
 
     OpcodeShift   = SSEDomainShift + 2,
-    OpcodeMask    = 0xFF << OpcodeShift,
+    OpcodeMask    = 0xFFULL << OpcodeShift,
 
     //===------------------------------------------------------------------===//
     /// VEX - The opcode prefix used by AVX instructions



From jgu222 at gmail.com  Mon Apr  4 15:47:23 2011
From: jgu222 at gmail.com (Junjie Gu)
Date: Mon, 4 Apr 2011 13:47:23 -0700
Subject: [llvm-commits] Minor change to LoopUnroll's ctor
Message-ID: <BANLkTikLEQpmn+pGGGFn-DaEDMfys3BxDA@mail.gmail.com>

I'd like to change the loop unroll so that the
threshold/count/allowpartial can be passed as parameters to
LoopUnroll's ctor. The reason for doing so is that static options
(-unroll-threshold, -unroll-count, -unroll-allow-partial) are not good
for an environment (OpenCL) in which multiple llvm context may be
present at the same time. And each llvm context may have its own
optimization options, and thus options cannot be shared.

With this patch, a user can create a loop unroll by the following:

          createLoopUnrollPass(Threshold, Count, AllowPartial);

And the previous API
          createLoopUnrollPass()
will work as before.

Please review it. I do have commit access so I can check in by myself
after reviewing.

Thanks
Junjie
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From grosbach at apple.com  Mon Apr  4 18:04:39 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 04 Apr 2011 23:04:39 -0000
Subject: [llvm-commits] [llvm] r128851 - in /llvm/trunk:
 include/llvm/ExecutionEngine/RuntimeDyld.h
 lib/ExecutionEngine/MCJIT/MCJIT.cpp lib/ExecutionEngine/MCJIT/MCJIT.h
 lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
 tools/llvm-rtdyld/llvm-rtdyld.cpp
Message-ID: <20110404230440.101662A6C12C@llvm.org>

Author: grosbach
Date: Mon Apr  4 18:04:39 2011
New Revision: 128851

URL: http://llvm.org/viewvc/llvm-project?rev=128851&view=rev
Log:
Layer the memory manager between the JIT and the runtime Dyld.

The JITMemory manager references LLVM IR constructs directly, while the
runtime Dyld works at a lower level and can handle objects which may not
originate from LLVM IR. Introduce a new layer for the memory manager to
handle the interface between them. For the MCJIT, this layer will be almost
entirely simply a call-through w/ translation between the IR objects and
symbol names.

Modified:
    llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
    llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp
    llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h
    llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
    llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp

Modified: llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h?rev=128851&r1=128850&r2=128851&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h (original)
+++ llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h Mon Apr  4 18:04:39 2011
@@ -21,7 +21,29 @@
 
 class RuntimeDyldImpl;
 class MemoryBuffer;
-class JITMemoryManager;
+
+// RuntimeDyld clients often want to handle the memory management of
+// what gets placed where. For JIT clients, this is an abstraction layer
+// over the JITMemoryManager, which references objects by their source
+// representations in LLVM IR.
+// FIXME: As the RuntimeDyld fills out, additional routines will be needed
+//        for the varying types of objects to be allocated.
+class RTDyldMemoryManager {
+  RTDyldMemoryManager(const RTDyldMemoryManager&);  // DO NOT IMPLEMENT
+  void operator=(const RTDyldMemoryManager&);       // DO NOT IMPLEMENT
+public:
+  RTDyldMemoryManager() {}
+
+  // Allocate ActualSize bytes, or more, for the named function. Return
+  // a pointer to the allocated memory and update Size to reflect how much
+  // memory was acutally allocated.
+  virtual uint64_t startFunctionBody(const char *Name, uintptr_t &Size) = 0;
+
+  // Mark the end of the function, including how much of the allocated
+  // memory was actually used.
+  virtual void endFunctionBody(const char *Name, uint64_t FunctionStart,
+                               uint64_t FunctionEnd) = 0;
+};
 
 class RuntimeDyld {
   RuntimeDyld(const RuntimeDyld &);     // DO NOT IMPLEMENT
@@ -31,11 +53,12 @@
   // interface.
   RuntimeDyldImpl *Dyld;
 public:
-  RuntimeDyld(JITMemoryManager*);
+  RuntimeDyld(RTDyldMemoryManager*);
   ~RuntimeDyld();
 
   bool loadObject(MemoryBuffer *InputBuffer);
-  void *getSymbolAddress(StringRef Name);
+  uint64_t getSymbolAddress(StringRef Name);
+  void reassignSymbolAddress(StringRef Name, uint64_t Addr);
   // FIXME: Should be parameterized to get the memory block associated with
   // a particular loaded object.
   sys::MemoryBlock getMemoryBlock();

Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp?rev=128851&r1=128850&r2=128851&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Mon Apr  4 18:04:39 2011
@@ -8,6 +8,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "MCJIT.h"
+#include "MCJITMemoryManager.h"
 #include "llvm/DerivedTypes.h"
 #include "llvm/Function.h"
 #include "llvm/ExecutionEngine/GenericValue.h"
@@ -57,7 +58,8 @@
 
   // If the target supports JIT code generation, create the JIT.
   if (TargetJITInfo *TJ = TM->getJITInfo())
-    return new MCJIT(M, TM, *TJ, JMM, OptLevel, GVsWithCode);
+    return new MCJIT(M, TM, *TJ, new MCJITMemoryManager(JMM), OptLevel,
+                     GVsWithCode);
 
   if (ErrorStr)
     *ErrorStr = "target does not support JIT code generation";
@@ -65,9 +67,9 @@
 }
 
 MCJIT::MCJIT(Module *m, TargetMachine *tm, TargetJITInfo &tji,
-             JITMemoryManager *JMM, CodeGenOpt::Level OptLevel,
+             RTDyldMemoryManager *MM, CodeGenOpt::Level OptLevel,
              bool AllocateGVsWithCode)
-  : ExecutionEngine(m), TM(tm), M(m), OS(Buffer), Dyld(JMM) {
+  : ExecutionEngine(m), TM(tm), MemMgr(MM), M(m), OS(Buffer), Dyld(MM) {
 
   PM.add(new TargetData(*TM->getTargetData()));
 
@@ -94,6 +96,7 @@
 }
 
 MCJIT::~MCJIT() {
+  delete MemMgr;
 }
 
 void *MCJIT::getPointerToBasicBlock(BasicBlock *BB) {
@@ -110,7 +113,7 @@
   }
 
   Twine Name = TM->getMCAsmInfo()->getGlobalPrefix() + F->getName();
-  return Dyld.getSymbolAddress(Name.str());
+  return (void*)Dyld.getSymbolAddress(Name.str());
 }
 
 void *MCJIT::recompileAndRelinkFunction(Function *F) {

Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h?rev=128851&r1=128850&r2=128851&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h (original)
+++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h Mon Apr  4 18:04:39 2011
@@ -24,11 +24,12 @@
 
 class MCJIT : public ExecutionEngine {
   MCJIT(Module *M, TargetMachine *tm, TargetJITInfo &tji,
-        JITMemoryManager *JMM, CodeGenOpt::Level OptLevel,
+        RTDyldMemoryManager *MemMgr, CodeGenOpt::Level OptLevel,
         bool AllocateGVsWithCode);
 
   TargetMachine *TM;
   MCContext *Ctx;
+  RTDyldMemoryManager *MemMgr;
 
   // FIXME: These may need moved to a separate 'jitstate' member like the
   // non-MC JIT does for multithreading and such. Just keep them here for now.

Modified: llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp?rev=128851&r1=128850&r2=128851&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp Mon Apr  4 18:04:39 2011
@@ -18,7 +18,6 @@
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/ExecutionEngine/RuntimeDyld.h"
-#include "llvm/ExecutionEngine/JITMemoryManager.h"
 #include "llvm/Object/MachOObject.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -35,12 +34,12 @@
   unsigned CPUType;
   unsigned CPUSubtype;
 
-  // The JITMemoryManager to load objects into.
-  JITMemoryManager *JMM;
+  // The MemoryManager to load objects into.
+  RTDyldMemoryManager *MemMgr;
 
   // Master symbol table. As modules are loaded and external symbols are
   // resolved, their addresses are stored here.
-  StringMap<void*> SymbolTable;
+  StringMap<uint64_t> SymbolTable;
 
   // FIXME: Should have multiple data blocks, one for each loaded chunk of
   //        compiled code.
@@ -72,11 +71,11 @@
                      const InMemoryStruct<macho::SymtabLoadCommand> &SymtabLC);
 
 public:
-  RuntimeDyldImpl(JITMemoryManager *jmm) : JMM(jmm), HasError(false) {}
+  RuntimeDyldImpl(RTDyldMemoryManager *mm) : MemMgr(mm), HasError(false) {}
 
   bool loadObject(MemoryBuffer *InputBuffer);
 
-  void *getSymbolAddress(StringRef Name) {
+  uint64_t getSymbolAddress(StringRef Name) {
     // Use lookup() rather than [] because we don't want to add an entry
     // if there isn't one already, which the [] operator does.
     return SymbolTable.lookup(Name);
@@ -314,7 +313,7 @@
     void *SectionBase = SectionBases[Index];
 
     // Get the symbol address.
-    void *Address = (char*) SectionBase + STE->Value;
+    uint64_t Address = (uint64_t)SectionBase + STE->Value;
 
     // FIXME: Check the symbol type and flags.
     if (STE->Type != 0xF)
@@ -335,7 +334,7 @@
   }
 
   // We've loaded the section; now mark the functions in it as executable.
-  // FIXME: We really should use the JITMemoryManager for this.
+  // FIXME: We really should use the MemoryManager for this.
   sys::Memory::setRangeExecutable(Data.base(), Data.size());
 
   return false;
@@ -414,7 +413,7 @@
     void *SectionBase = SectionBases[Index];
 
     // Get the symbol address.
-    void *Address = (char*) SectionBase + STE->Value;
+    uint64_t Address = (uint64_t) SectionBase + STE->Value;
 
     // FIXME: Check the symbol type and flags.
     if (STE->Type != 0xF)
@@ -434,7 +433,7 @@
   }
 
   // We've loaded the section; now mark the functions in it as executable.
-  // FIXME: We really should use the JITMemoryManager for this.
+  // FIXME: We really should use the MemoryManager for this.
   sys::Memory::setRangeExecutable(Data.base(), Data.size());
 
   return false;
@@ -530,8 +529,8 @@
 
 //===----------------------------------------------------------------------===//
 // RuntimeDyld class implementation
-RuntimeDyld::RuntimeDyld(JITMemoryManager *JMM) {
-  Dyld = new RuntimeDyldImpl(JMM);
+RuntimeDyld::RuntimeDyld(RTDyldMemoryManager *MM) {
+  Dyld = new RuntimeDyldImpl(MM);
 }
 
 RuntimeDyld::~RuntimeDyld() {
@@ -542,7 +541,7 @@
   return Dyld->loadObject(InputBuffer);
 }
 
-void *RuntimeDyld::getSymbolAddress(StringRef Name) {
+uint64_t RuntimeDyld::getSymbolAddress(StringRef Name) {
   return Dyld->getSymbolAddress(Name);
 }
 

Modified: llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp?rev=128851&r1=128850&r2=128851&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp (original)
+++ llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp Mon Apr  4 18:04:39 2011
@@ -13,7 +13,6 @@
 
 #include "llvm/ADT/StringMap.h"
 #include "llvm/ADT/OwningPtr.h"
-#include "llvm/ExecutionEngine/JITMemoryManager.h"
 #include "llvm/ExecutionEngine/RuntimeDyld.h"
 #include "llvm/Object/MachOObject.h"
 #include "llvm/Support/CommandLine.h"
@@ -41,6 +40,20 @@
 
 /* *** */
 
+// A trivial memory manager that doesn't do anything fancy, just uses the
+// support library allocation routines directly.
+class TrivialMemoryManager : public RTDyldMemoryManager {
+public:
+  uint64_t startFunctionBody(const char *Name, uintptr_t &Size);
+  void endFunctionBody(const char *Name, uint64_t FunctionStart,
+                       uint64_t FunctionEnd) {}
+};
+
+uint64_t TrivialMemoryManager::startFunctionBody(const char *Name,
+                                                 uintptr_t &Size) {
+  return (uint64_t)sys::Memory::AllocateRWX(Size, 0, 0).base();
+}
+
 static const char *ProgramName;
 
 static void Message(const char *Type, const Twine &Msg) {
@@ -61,7 +74,7 @@
     return Error("unable to read input: '" + ec.message() + "'");
 
   // Instantiate a dynamic linker.
-  RuntimeDyld Dyld(JITMemoryManager::CreateDefaultMemManager());
+  RuntimeDyld Dyld(new TrivialMemoryManager);
 
   // Load the object file into it.
   if (Dyld.loadObject(InputBuffer.take())) {
@@ -69,7 +82,7 @@
   }
 
   // Get the address of "_main".
-  void *MainAddress = Dyld.getSymbolAddress("_main");
+  uint64_t MainAddress = Dyld.getSymbolAddress("_main");
   if (MainAddress == 0)
     return Error("no definition for '_main'");
 
@@ -83,7 +96,7 @@
     return Error("unable to mark function executable: '" + ErrorStr + "'");
 
   // Dispatch to _main().
-  errs() << "loaded '_main' at: " << MainAddress << "\n";
+  errs() << "loaded '_main' at: " << (void*)MainAddress << "\n";
 
   int (*Main)(int, const char**) =
     (int(*)(int,const char**)) uintptr_t(MainAddress);



From grosbach at apple.com  Mon Apr  4 18:20:40 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 04 Apr 2011 23:20:40 -0000
Subject: [llvm-commits] [llvm] r128856 -
	/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h
Message-ID: <20110404232040.BC03C2A6C12C@llvm.org>

Author: grosbach
Date: Mon Apr  4 18:20:40 2011
New Revision: 128856

URL: http://llvm.org/viewvc/llvm-project?rev=128856&view=rev
Log:
Add missing file from r128851.

Added:
    llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h

Added: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h?rev=128856&view=auto
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h (added)
+++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h Mon Apr  4 18:20:40 2011
@@ -0,0 +1,58 @@
+//===-- MCJITMemoryManager.h - Definition for the Memory Manager ---C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_EXECUTIONENGINE_MCJITMEMORYMANAGER_H
+#define LLVM_LIB_EXECUTIONENGINE_MCJITMEMORYMANAGER_H
+
+#include "llvm/Module.h"
+#include "llvm/ExecutionEngine/JITMemoryManager.h"
+#include "llvm/ExecutionEngine/RuntimeDyld.h"
+#include <assert.h>
+
+namespace llvm {
+
+// The MCJIT memory manager is a layer between the standard JITMemoryManager
+// and the RuntimeDyld interface that maps objects, by name, onto their
+// matching LLVM IR counterparts in the module(s) being compiled.
+class MCJITMemoryManager : public RTDyldMemoryManager {
+  JITMemoryManager *JMM;
+
+  // FIXME: Multiple modules.
+  Module *M;
+public:
+  MCJITMemoryManager(JITMemoryManager *jmm) : JMM(jmm) {}
+
+  // Allocate ActualSize bytes, or more, for the named function. Return
+  // a pointer to the allocated memory and update Size to reflect how much
+  // memory was acutally allocated.
+  uint64_t startFunctionBody(const char *Name, uintptr_t &Size) {
+    Function *F = M->getFunction(Name);
+    assert(F && "No matching function in JIT IR Module!");
+    return (uint64_t)JMM->startFunctionBody(F, Size);
+  }
+
+  // Mark the end of the function, including how much of the allocated
+  // memory was actually used.
+  void endFunctionBody(const char *Name, uint64_t FunctionStart,
+                       uint64_t FunctionEnd) {
+    Function *F = M->getFunction(Name);
+    assert(F && "No matching function in JIT IR Module!");
+    // The JITMemoryManager interface makes the unfortunate assumption that
+    // the address space/sizes we're compiling on are the same as what we're
+    // compiling for, so it uses pointer types for its addresses. Explicit
+    // casts between them to deal with that.
+    return JMM->endFunctionBody(F, (uint8_t*)FunctionStart,
+                                (uint8_t*)FunctionEnd);
+  }
+
+};
+
+} // End llvm namespace
+
+#endif



From pichet2000 at gmail.com  Mon Apr  4 18:29:48 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Mon, 4 Apr 2011 19:29:48 -0400
Subject: [llvm-commits] [llvm] r128851 - in /llvm/trunk:
 include/llvm/ExecutionEngine/RuntimeDyld.h
 lib/ExecutionEngine/MCJIT/MCJIT.cpp lib/ExecutionEngine/MCJIT/MCJIT.h
 lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
 tools/llvm-rtdyld/llvm-rtdyld.cpp
In-Reply-To: <20110404230440.101662A6C12C@llvm.org>
References: <20110404230440.101662A6C12C@llvm.org>
Message-ID: <BANLkTin=KvLSvQunEgrZ8NKomic=p2rp9g@mail.gmail.com>

On Mon, Apr 4, 2011 at 7:04 PM, Jim Grosbach <grosbach at apple.com> wrote:
> Author: grosbach
> Date: Mon Apr ?4 18:04:39 2011
> New Revision: 128851
>
> URL: http://llvm.org/viewvc/llvm-project?rev=128851&view=rev
> Log:
> Layer the memory manager between the JIT and the runtime Dyld.
>
> The JITMemory manager references LLVM IR constructs directly, while the
> runtime Dyld works at a lower level and can handle objects which may not
> originate from LLVM IR. Introduce a new layer for the memory manager to
> handle the interface between them. For the MCJIT, this layer will be almost
> entirely simply a call-through w/ translation between the IR objects and
> symbol names.
>
> Modified:
> ? ?llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
> ? ?llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp
> ? ?llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h
> ? ?llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
> ? ?llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp
>


where is MCJITMemoryManager.h?


From grosbach at apple.com  Mon Apr  4 18:31:44 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Mon, 04 Apr 2011 16:31:44 -0700
Subject: [llvm-commits] [llvm] r128851 - in /llvm/trunk:
 include/llvm/ExecutionEngine/RuntimeDyld.h
 lib/ExecutionEngine/MCJIT/MCJIT.cpp lib/ExecutionEngine/MCJIT/MCJIT.h
 lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
 tools/llvm-rtdyld/llvm-rtdyld.cpp
In-Reply-To: <BANLkTin=KvLSvQunEgrZ8NKomic=p2rp9g@mail.gmail.com>
References: <20110404230440.101662A6C12C@llvm.org>
	<BANLkTin=KvLSvQunEgrZ8NKomic=p2rp9g@mail.gmail.com>
Message-ID: <428F67B7-2917-417B-B311-847B2266ED1D@apple.com>


On Apr 4, 2011, at 4:29 PM, Francois Pichet wrote:

> On Mon, Apr 4, 2011 at 7:04 PM, Jim Grosbach <grosbach at apple.com> wrote:
>> Author: grosbach
>> Date: Mon Apr  4 18:04:39 2011
>> New Revision: 128851
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=128851&view=rev
>> Log:
>> Layer the memory manager between the JIT and the runtime Dyld.
>> 
>> The JITMemory manager references LLVM IR constructs directly, while the
>> runtime Dyld works at a lower level and can handle objects which may not
>> originate from LLVM IR. Introduce a new layer for the memory manager to
>> handle the interface between them. For the MCJIT, this layer will be almost
>> entirely simply a call-through w/ translation between the IR objects and
>> symbol names.
>> 
>> Modified:
>>    llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
>>    llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp
>>    llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.h
>>    llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
>>    llvm/trunk/tools/llvm-rtdyld/llvm-rtdyld.cpp
>> 
> 
> 
> where is MCJITMemoryManager.h?

Running late to the party due to suffering from my moving back and forth between git and svn.

i.e., I forgot to "svn add" it before hitting commit.  Fixed in 128856.

From johnny.chen at apple.com  Mon Apr  4 18:39:08 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Mon, 04 Apr 2011 23:39:08 -0000
Subject: [llvm-commits] [llvm] r128859 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrInfo.td Disassembler/ARMDisassemblerCore.cpp
 Disassembler/ARMDisassemblerCore.h
Message-ID: <20110404233908.CFBD72A6C12C@llvm.org>

Author: johnny
Date: Mon Apr  4 18:39:08 2011
New Revision: 128859

URL: http://llvm.org/viewvc/llvm-project?rev=128859&view=rev
Log:
RFE encoding should also specify the "should be" encoding bits.

rdar://problem/9229922 ARM disassembler discrepancy: erroneously accepting RFE

Also LDC/STC instructions are predicated while LDC2/STC2 instructions are not, fixed while
doing regression testings.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128859&r1=128858&r2=128859&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Apr  4 18:39:08 2011
@@ -1604,6 +1604,7 @@
                 [/* For disassembly only; pattern left blank */]> {
   let Inst{31-28} = 0b1111;
   let Inst{22-20} = 0b011; // W = 1
+  let Inst{15-0} = 0x0a00;
 }
 
 def RFE  : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, GPR:$base),
@@ -1611,6 +1612,7 @@
                 [/* For disassembly only; pattern left blank */]> {
   let Inst{31-28} = 0b1111;
   let Inst{22-20} = 0b001; // W = 0
+  let Inst{15-0} = 0x0a00;
 }
 } // isCodeGenOnly = 1
 
@@ -3434,16 +3436,16 @@
 
 class ACI<dag oops, dag iops, string opc, string asm,
           IndexMode im = IndexModeNone>
-  : I<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
-      opc, asm, "", [/* For disassembly only; pattern left blank */]> {
+  : InoP<oops, iops, AddrModeNone, Size4Bytes, im, BrFrm, NoItinerary,
+         opc, asm, "", [/* For disassembly only; pattern left blank */]> {
   let Inst{27-25} = 0b110;
 }
 
-multiclass LdStCop<bits<4> op31_28, bit load, string opc> {
+multiclass LdStCop<bits<4> op31_28, bit load, dag ops, string opc, string cond>{
 
   def _OFFSET : ACI<(outs),
-      (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
-      opc, "\tp$cop, cr$CRd, $addr"> {
+      !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
+      !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr"> {
     let Inst{31-28} = op31_28;
     let Inst{24} = 1; // P = 1
     let Inst{21} = 0; // W = 0
@@ -3452,8 +3454,8 @@
   }
 
   def _PRE : ACI<(outs),
-      (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
-      opc, "\tp$cop, cr$CRd, $addr!", IndexModePre> {
+      !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
+      !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
     let Inst{31-28} = op31_28;
     let Inst{24} = 1; // P = 1
     let Inst{21} = 1; // W = 1
@@ -3462,8 +3464,8 @@
   }
 
   def _POST : ACI<(outs),
-      (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
-      opc, "\tp$cop, cr$CRd, $addr", IndexModePost> {
+      !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
+      !strconcat(opc, cond), "\tp$cop, cr$CRd, $addr", IndexModePost> {
     let Inst{31-28} = op31_28;
     let Inst{24} = 0; // P = 0
     let Inst{21} = 1; // W = 1
@@ -3472,8 +3474,9 @@
   }
 
   def _OPTION : ACI<(outs),
-      (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
-      opc, "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
+      !con((ins nohash_imm:$cop,nohash_imm:$CRd,GPR:$base, nohash_imm:$option),
+            ops),
+      !strconcat(opc, cond), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
     let Inst{31-28} = op31_28;
     let Inst{24} = 0; // P = 0
     let Inst{23} = 1; // U = 1
@@ -3483,8 +3486,8 @@
   }
 
   def L_OFFSET : ACI<(outs),
-      (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
-      !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr"> {
+      !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
+      !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr"> {
     let Inst{31-28} = op31_28;
     let Inst{24} = 1; // P = 1
     let Inst{21} = 0; // W = 0
@@ -3493,8 +3496,9 @@
   }
 
   def L_PRE : ACI<(outs),
-      (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
-      !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
+      !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
+      !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr!",
+      IndexModePre> {
     let Inst{31-28} = op31_28;
     let Inst{24} = 1; // P = 1
     let Inst{21} = 1; // W = 1
@@ -3503,8 +3507,9 @@
   }
 
   def L_POST : ACI<(outs),
-      (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
-      !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr", IndexModePost> {
+      !con((ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr), ops),
+      !strconcat(!strconcat(opc, "l"), cond), "\tp$cop, cr$CRd, $addr",
+      IndexModePost> {
     let Inst{31-28} = op31_28;
     let Inst{24} = 0; // P = 0
     let Inst{21} = 1; // W = 1
@@ -3513,8 +3518,10 @@
   }
 
   def L_OPTION : ACI<(outs),
-      (ins nohash_imm:$cop, nohash_imm:$CRd, GPR:$base, nohash_imm:$option),
-      !strconcat(opc, "l"), "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
+      !con((ins nohash_imm:$cop, nohash_imm:$CRd,GPR:$base,nohash_imm:$option),
+            ops),
+      !strconcat(!strconcat(opc, "l"), cond),
+      "\tp$cop, cr$CRd, [$base], \\{$option\\}"> {
     let Inst{31-28} = op31_28;
     let Inst{24} = 0; // P = 0
     let Inst{23} = 1; // U = 1
@@ -3524,10 +3531,10 @@
   }
 }
 
-defm LDC  : LdStCop<{?,?,?,?}, 1, "ldc">;
-defm LDC2 : LdStCop<0b1111,    1, "ldc2">;
-defm STC  : LdStCop<{?,?,?,?}, 0, "stc">;
-defm STC2 : LdStCop<0b1111,    0, "stc2">;
+defm LDC  : LdStCop<{?,?,?,?}, 1, (ins pred:$p), "ldc",  "${p}">;
+defm LDC2 : LdStCop<0b1111,    1, (ins),         "ldc2", "">;
+defm STC  : LdStCop<{?,?,?,?}, 0, (ins pred:$p), "stc",  "${p}">;
+defm STC2 : LdStCop<0b1111,    0, (ins),         "stc2", "">;
 
 //===----------------------------------------------------------------------===//
 // Move between coprocessor and ARM core register -- for disassembly only

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128859&r1=128858&r2=128859&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Mon Apr  4 18:39:08 2011
@@ -618,7 +618,7 @@
 static bool DisassembleCoprocessor(MCInst &MI, unsigned Opcode, uint32_t insn,
     unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
 
-  assert(NumOps >= 5 && "Num of operands >= 5 for coprocessor instr");
+  assert(NumOps >= 4 && "Num of operands >= 4 for coprocessor instr");
 
   unsigned &OpIdx = NumOpsAdded;
   bool OneCopOpc = (Opcode == ARM::MCRR || Opcode == ARM::MCRR2 ||
@@ -1296,8 +1296,10 @@
   MI.addOperand(MCOperand::CreateReg(Base));
 
   // Handling the two predicate operands before the reglist.
-  int64_t CondVal = insn >> ARMII::CondShift;
-  MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
+  int64_t CondVal = getCondField(insn);
+  if (CondVal == 0xF)
+    return false;
+  MI.addOperand(MCOperand::CreateImm(CondVal));
   MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
 
   NumOpsAdded += 3;
@@ -1863,8 +1865,10 @@
   MI.addOperand(MCOperand::CreateReg(Base));
 
   // Handling the two predicate operands before the reglist.
-  int64_t CondVal = insn >> ARMII::CondShift;
-  MI.addOperand(MCOperand::CreateImm(CondVal == 0xF ? 0xE : CondVal));
+  int64_t CondVal = getCondField(insn);
+  if (CondVal == 0xF)
+    return false;
+  MI.addOperand(MCOperand::CreateImm(CondVal));
   MI.addOperand(MCOperand::CreateReg(ARM::CPSR));
 
   OpIdx += 3;
@@ -3357,6 +3361,7 @@
   const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo;
   const std::string &Name = ARMInsts[Opcode].Name;
   unsigned Idx = MI.getNumOperands();
+  uint64_t TSFlags = ARMInsts[Opcode].TSFlags;
 
   // First, we check whether this instr specifies the PredicateOperand through
   // a pair of TargetOperandInfos with isPredicate() property.
@@ -3384,6 +3389,9 @@
           MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
       } else {
         // ARM instructions get their condition field from Inst{31-28}.
+        // We should reject Inst{31-28} = 0b1111 as invalid encoding.
+        if (!isNEONDomain(TSFlags) && getCondField(insn) == 0xF)
+          return false;
         MI.addOperand(MCOperand::CreateImm(CondCode(getCondField(insn))));
       }
     }

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h?rev=128859&r1=128858&r2=128859&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.h Mon Apr  4 18:39:08 2011
@@ -141,6 +141,12 @@
   return (TSFlags & ARMII::UnaryDP);
 }
 
+/// A NEON Domain instruction has cond field (Inst{31-28}) as 0b1111.
+static inline bool isNEONDomain(uint64_t TSFlags) {
+  return (TSFlags & ARMII::DomainNEON) ||
+         (TSFlags & ARMII::DomainNEONA8);
+}
+
 /// This four-bit field describes the addressing mode used.
 /// See also ARMBaseInstrInfo.h.
 static inline unsigned getAddrMode(uint64_t TSFlags) {



From isanbard at gmail.com  Mon Apr  4 18:42:51 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 04 Apr 2011 23:42:51 -0000
Subject: [llvm-commits] [llvm] r128860 - /llvm/trunk/docs/GettingStarted.html
Message-ID: <20110404234251.B5C012A6C12C@llvm.org>

Author: void
Date: Mon Apr  4 18:42:51 2011
New Revision: 128860

URL: http://llvm.org/viewvc/llvm-project?rev=128860&view=rev
Log:
Add info on where to get 2.9 final svn sources.

Modified:
    llvm/trunk/docs/GettingStarted.html

Modified: llvm/trunk/docs/GettingStarted.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=128860&r1=128859&r2=128860&view=diff
==============================================================================
--- llvm/trunk/docs/GettingStarted.html (original)
+++ llvm/trunk/docs/GettingStarted.html Mon Apr  4 18:42:51 2011
@@ -743,6 +743,7 @@
 subdirectories of the '<tt>tags</tt>' directory:</p>
 
 <ul>
+<li>Release 2.9: <b>RELEASE_29/final</b></li>
 <li>Release 2.8: <b>RELEASE_28</b></li>
 <li>Release 2.7: <b>RELEASE_27</b></li>
 <li>Release 2.6: <b>RELEASE_26</b></li>



From johnny.chen at apple.com  Mon Apr  4 18:57:05 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Mon, 04 Apr 2011 23:57:05 -0000
Subject: [llvm-commits] [llvm] r128862 -
	/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20110404235705.6D3A22A6C12C@llvm.org>

Author: johnny
Date: Mon Apr  4 18:57:05 2011
New Revision: 128862

URL: http://llvm.org/viewvc/llvm-project?rev=128862&view=rev
Log:
A8.6.105 MUL
Inst{15-12} should be specified as 0b0000.

rdar://problem/9231168 ARM disassembler discrepancy: erroneously accepting MUL

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128862&r1=128861&r2=128862&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Apr  4 18:57:05 2011
@@ -2687,7 +2687,9 @@
 def MUL  : AsMul1I32<0b0000000, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
                    IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm",
                    [(set GPR:$Rd, (mul GPR:$Rn, GPR:$Rm))]>,
-                   Requires<[IsARM, HasV6]>;
+                   Requires<[IsARM, HasV6]> {
+  let Inst{15-12} = 0b0000;
+}
 }
 
 let Constraints = "@earlyclobber $Rd" in



From nlewycky at google.com  Mon Apr  4 19:16:01 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Mon, 4 Apr 2011 17:16:01 -0700
Subject: [llvm-commits] [llvm] r123704 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
In-Reply-To: <20110118000928.2D35C2A6C12C@llvm.org>
References: <20110118000928.2D35C2A6C12C@llvm.org>
Message-ID: <BANLkTimWE1eNZU+cuCtqfcyix_GMyhjH+Q@mail.gmail.com>

On 17 January 2011 16:09, Stuart Hastings <stuart at apple.com> wrote:

> Author: stuart
> Date: Mon Jan 17 18:09:27 2011
> New Revision: 123704
>
> URL: http://llvm.org/viewvc/llvm-project?rev=123704&view=rev
> Log:
> Remove checking that prevented overlapping CALLSEQ_START/CALLSEQ_END
> ranges, add legalizer support for nested calls.  Necessary for ARM
> byval support.  Radar 7662569.
>
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
>
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=123704&r1=123703&r2=123704&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jan 17 18:09:27
> 2011
> @@ -66,11 +66,6 @@
>   /// against each other, including inserted libcalls.
>   SDValue LastCALLSEQ_END;
>
> -  /// IsLegalizingCall - This member is used *only* for purposes of
> providing
> -  /// helpful assertions that a libcall isn't created while another call
> is
> -  /// being legalized (which could lead to non-serialized call sequences).
> -  bool IsLegalizingCall;
> -
>   enum LegalizeAction {
>     Legal,      // The target natively supports this operation.
>     Promote,    // This operation should be executed in a larger type.
> @@ -225,7 +220,6 @@
>
>  void SelectionDAGLegalize::LegalizeDAG() {
>   LastCALLSEQ_END = DAG.getEntryNode();
> -  IsLegalizingCall = false;
>
>   // The legalize process is inherently a bottom-up recursive process
> (users
>   // legalize their uses before themselves).  Given infinite stack space,
> we
> @@ -1024,6 +1018,7 @@
>     }
>     break;
>   case ISD::CALLSEQ_START: {
> +    static int depth = 0;
>

Hi Stuart, this breaks using llvm from multiple threads. Please don't use
non-constant statics.

Nick


>     SDNode *CallEnd = FindCallEndFromCallStart(Node);
>
>     // Recursively Legalize all of the inputs of the call end that do not
> lead
> @@ -1041,7 +1036,7 @@
>
>     // Merge in the last call to ensure that this call starts after the
> last
>     // call ended.
> -    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
> +    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken && depth == 0) {
>       Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
>                          Tmp1, LastCALLSEQ_END);
>       Tmp1 = LegalizeOp(Tmp1);
> @@ -1064,14 +1059,18 @@
>     // sequence have been legalized, legalize the call itself.  During this
>     // process, no libcalls can/will be inserted, guaranteeing that no
> calls
>     // can overlap.
> -    assert(!IsLegalizingCall && "Inconsistent sequentialization of
> calls!");
> +
> +    SDValue Saved_LastCALLSEQ_END = LastCALLSEQ_END ;
>     // Note that we are selecting this call!
>     LastCALLSEQ_END = SDValue(CallEnd, 0);
> -    IsLegalizingCall = true;
>
> +    depth++;
>     // Legalize the call, starting from the CALLSEQ_END.
>     LegalizeOp(LastCALLSEQ_END);
> -    assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
> +    depth--;
> +    assert(depth >= 0 && "Un-matched CALLSEQ_START?");
> +    if (depth > 0)
> +      LastCALLSEQ_END = Saved_LastCALLSEQ_END;
>     return Result;
>   }
>   case ISD::CALLSEQ_END:
> @@ -1110,10 +1109,7 @@
>                          Result.getResNo());
>       }
>     }
> -    assert(IsLegalizingCall && "Call sequence imbalance between
> start/end?");
>     // This finishes up call legalization.
> -    IsLegalizingCall = false;
> -
>     // If the CALLSEQ_END node has a flag, remember that we legalized it.
>     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
>     if (Node->getNumValues() == 2)
> @@ -1949,7 +1945,6 @@
>  // and leave the Hi part unset.
>  SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode
> *Node,
>                                             bool isSigned) {
> -  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
>   // The input chain to this libcall is the entry node of the function.
>   // Legalizing the call will automatically add the previous call to the
>   // dependence.
> @@ -1997,7 +1992,6 @@
>  SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
>                                          SDNode *Node,
>                                          bool isSigned) {
> -  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
>   SDValue InChain = Node->getOperand(0);
>
>   TargetLowering::ArgListTy Args;
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From johnny.chen at apple.com  Mon Apr  4 19:16:18 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 00:16:18 -0000
Subject: [llvm-commits] [llvm] r128864 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrInfo.td
 test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt
 test/MC/Disassembler/ARM/invalid-SRS-arm.txt
Message-ID: <20110405001618.4F4262A6C12C@llvm.org>

Author: johnny
Date: Mon Apr  4 19:16:18 2011
New Revision: 128864

URL: http://llvm.org/viewvc/llvm-project?rev=128864&view=rev
Log:
Fix SRS/SRSW encoding bits.
rdar://problem/9230801 ARM disassembler discrepancy: erroneously accepting SRS

Plus add invalid-RFEorLDMIA-arm.txt test which should have been checked in with
http://llvm.org/viewvc/llvm-project?view=rev&revision=128859.

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt
    llvm/trunk/test/MC/Disassembler/ARM/invalid-SRS-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128864&r1=128863&r2=128864&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Apr  4 19:16:18 2011
@@ -1589,6 +1589,8 @@
                 [/* For disassembly only; pattern left blank */]> {
   let Inst{31-28} = 0b1111;
   let Inst{22-20} = 0b110; // W = 1
+  let Inst{19-8} = 0xd05;
+  let Inst{7-5} = 0b000;
 }
 
 def SRS  : ABXI<{1,0,0,?}, (outs), (ins ldstm_mode:$amode, i32imm:$mode),
@@ -1596,6 +1598,8 @@
                 [/* For disassembly only; pattern left blank */]> {
   let Inst{31-28} = 0b1111;
   let Inst{22-20} = 0b100; // W = 0
+  let Inst{19-8} = 0xd05;
+  let Inst{7-5} = 0b000;
 }
 
 // Return From Exception is a system instruction -- for disassembly only

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt?rev=128864&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-RFEorLDMIA-arm.txt Mon Apr  4 19:16:18 2011
@@ -0,0 +1,11 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=134 Name=LDMIA Format=ARM_FORMAT_LDSTMULFRM(10)
+# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 0: 1| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 0: 1| 0: 0: 1: 1| 0: 0: 1: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# B6.1.8 RFE has Inst{15-0} as 0x0a00 ==> Not an RFE instruction
+# A8.6.53 LDM/LDMIA/LDMFD is predicated with Inst{31-28} as cond ==> Not an LDMIA instruction
+0x32 0xb1 0x99 0xf8

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-SRS-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-SRS-arm.txt?rev=128864&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-SRS-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-SRS-arm.txt Mon Apr  4 19:16:18 2011
@@ -0,0 +1,13 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=0 Name=PHI Format=(42)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 1: 0: 0: 0| 1: 1: 0: 0| 0: 1: 0: 1| 0: 0: 0: 1| 1: 1: 0: 0| 1: 0: 0: 0| 0: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+# Unknown format
+#
+# B6.1.10 SRS
+# Inst{19-8} = 0xd05
+# Inst{7-5} = 0b000
+0x83 0x1c 0xc5 0xf8



From echristo at apple.com  Mon Apr  4 19:30:54 2011
From: echristo at apple.com (Eric Christopher)
Date: Mon, 04 Apr 2011 17:30:54 -0700
Subject: [llvm-commits] [PATCH] Use predicates more often when
	optimizing	for size
In-Reply-To: <20110403045626.GA27536@flcl.lan>
References: <20110403045626.GA27536@flcl.lan>
Message-ID: <A69A404A-D4E6-4FAE-8257-F1B5428BA665@apple.com>


On Apr 2, 2011, at 9:56 PM, Sean Bartell wrote:

> When optimizing for size, we want to use predicates instead of branches
> to save a few instructions. Predicates are used when the resulting code
> is at least 1/2 as fast as with branching; this includes almost all
> cases where predicates can be used. There are, of course, other
> heuristics--I think GCC just uses a limit of 8 instructions.
> 
> Tested with make check in LLVM. I'd appreciate any feedback, since if
> I'm accepted into GSoC I'll be doing this much more often :).

Right now optimizing for size in llvm is generally "optimize for size
without penalizing performance" instead of "optimize for size at all
costs".

Otherwise the patch itself looked just fine :)

-eric

From stoklund at 2pi.dk  Mon Apr  4 19:32:44 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 00:32:44 -0000
Subject: [llvm-commits] [llvm] r128867 - /llvm/trunk/test/CodeGen/X86/
Message-ID: <20110405003244.AAAB02A6C12C@llvm.org>

Author: stoklund
Date: Mon Apr  4 19:32:44 2011
New Revision: 128867

URL: http://llvm.org/viewvc/llvm-project?rev=128867&view=rev
Log:
Fix register-dependent X86 tests.

Modified:
    llvm/trunk/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
    llvm/trunk/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll
    llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
    llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll
    llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-2.ll
    llvm/trunk/test/CodeGen/X86/isel-sink3.ll
    llvm/trunk/test/CodeGen/X86/loop-strength-reduce4.ll
    llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll
    llvm/trunk/test/CodeGen/X86/mmx-copy-gprs.ll
    llvm/trunk/test/CodeGen/X86/optimize-max-3.ll
    llvm/trunk/test/CodeGen/X86/or-address.ll
    llvm/trunk/test/CodeGen/X86/postra-licm.ll
    llvm/trunk/test/CodeGen/X86/pr3495-2.ll
    llvm/trunk/test/CodeGen/X86/pr3495.ll
    llvm/trunk/test/CodeGen/X86/pre-split1.ll
    llvm/trunk/test/CodeGen/X86/pre-split10.ll
    llvm/trunk/test/CodeGen/X86/pre-split11.ll
    llvm/trunk/test/CodeGen/X86/pre-split2.ll
    llvm/trunk/test/CodeGen/X86/pre-split3.ll
    llvm/trunk/test/CodeGen/X86/pre-split4.ll
    llvm/trunk/test/CodeGen/X86/pre-split5.ll
    llvm/trunk/test/CodeGen/X86/pre-split6.ll
    llvm/trunk/test/CodeGen/X86/pre-split7.ll
    llvm/trunk/test/CodeGen/X86/pre-split8.ll
    llvm/trunk/test/CodeGen/X86/pre-split9.ll
    llvm/trunk/test/CodeGen/X86/sse2.ll
    llvm/trunk/test/CodeGen/X86/sse3.ll
    llvm/trunk/test/CodeGen/X86/tail-opts.ll
    llvm/trunk/test/CodeGen/X86/tailcallstack64.ll
    llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll

Modified: llvm/trunk/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2007-07-03-GR64ToVR64.ll Mon Apr  4 19:32:44 2011
@@ -1,6 +1,8 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {movd	%rsi, %mm0}
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {movd	%rdi, %mm1}
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | grep {paddusw	%mm0, %mm1}
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+mmx | FileCheck %s
+
+; CHECK: movd %rsi, [[MM0:%mm[0-9]+]]
+; CHECK: movd %rdi, [[MM1:%mm[0-9]+]]
+; CHECK: paddusw [[MM0]], [[MM1]]
 
 @R = external global x86_mmx		; <x86_mmx*> [#uses=1]
 

Modified: llvm/trunk/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-02-20-PreAllocSplit-Crash.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin8 -pre-alloc-split
+; RUN: llc < %s -march=x86 -mtriple=i386-apple-darwin8 -pre-alloc-split -regalloc=linearscan
 
 define i32 @main() nounwind {
 bb4.i.thread:

Modified: llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-04-21-NoReloadImpDef.ll Mon Apr  4 19:32:44 2011
@@ -1,5 +1,5 @@
 ; RUN: llc -mtriple=i386-apple-darwin10.0 -relocation-model=pic -asm-verbose=false \
-; RUN:     -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false < %s | \
+; RUN:     -disable-fp-elim -mattr=-sse41,-sse3,+sse2 -post-RA-scheduler=false -regalloc=linearscan < %s | \
 ; RUN:   FileCheck %s
 ; rdar://6808032
 

Modified: llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-0.ll Mon Apr  4 19:32:44 2011
@@ -1,11 +1,21 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah  | not grep pcmpeqd
-; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah  | grep orps | grep CPI0_2  | count 2
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep pcmpeqd | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=linearscan | FileCheck --check-prefix=I386 %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck --check-prefix=X86-64 %s
 
 ; This testcase shouldn't need to spill the -1 value,
 ; so it should just use pcmpeqd to materialize an all-ones vector.
 ; For i386, cp load of -1 are folded.
 
+; With -regalloc=greedy, the live range is split before spilling, so the first
+; pcmpeq doesn't get folded as a constant pool load.
+
+; I386-NOT: pcmpeqd
+; I386: orps LCPI0_2, %xmm
+; I386-NOT: pcmpeqd
+; I386: orps LCPI0_2, %xmm
+
+; X86-64: pcmpeqd
+; X86-64-NOT: pcmpeqd
+
 	%struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }>
 	%struct._cl_image_format_t = type <{ i32, i32, i32 }>
 	%struct._image2d_t = type <{ i8*, %struct._cl_image_format_t, i32, i32, i32, i32, i32, i32 }>

Modified: llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-2.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/fold-pcmpeqd-2.ll Mon Apr  4 19:32:44 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah | FileCheck %s
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=yonah -regalloc=linearscan | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -regalloc=linearscan | FileCheck %s
 
 ; This testcase should need to spill the -1 value on both x86-32 and x86-64,
 ; so it shouldn't use pcmpeqd to materialize an all-ones vector; it

Modified: llvm/trunk/test/CodeGen/X86/isel-sink3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/isel-sink3.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/isel-sink3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/isel-sink3.ll Mon Apr  4 19:32:44 2011
@@ -1,9 +1,11 @@
-; RUN: llc < %s | grep {addl.\$4, %ecx}
-; RUN: llc < %s | not grep leal
+; RUN: llc < %s | FileCheck %s
 ; this should not sink %1 into bb1, that would increase reg pressure.
 
 ; rdar://6399178
 
+; CHECK: addl $4,
+; CHECK-NOT: leal
+
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i386-apple-darwin7"
 

Modified: llvm/trunk/test/CodeGen/X86/loop-strength-reduce4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/loop-strength-reduce4.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/loop-strength-reduce4.ll (original)
+++ llvm/trunk/test/CodeGen/X86/loop-strength-reduce4.ll Mon Apr  4 19:32:44 2011
@@ -4,10 +4,10 @@
 ; By starting the IV at -64 instead of 0, a cmp is eliminated,
 ; as the flags from the add can be used directly.
 
-; STATIC: movl    $-64, %ecx
+; STATIC: movl    $-64, [[ECX:%e..]]
 
-; STATIC: movl    %eax, _state+76(%ecx)
-; STATIC: addl    $16, %ecx
+; STATIC: movl    [[EAX:%e..]], _state+76([[ECX]])
+; STATIC: addl    $16, [[ECX]]
 ; STATIC: jne
 
 ; In PIC mode the symbol can't be folded, so the change-compare-stride

Modified: llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lsr-reuse-trunc.ll Mon Apr  4 19:32:44 2011
@@ -4,8 +4,9 @@
 ; Full strength reduction wouldn't reduce register pressure, so LSR should
 ; stick with indexing here.
 
-; CHECK: movaps        (%{{rsi|rdx}},%rax,4), %xmm3
-; CHECK: movaps        %xmm3, (%{{rdi|rcx}},%rax,4)
+; CHECK: movaps        (%{{rsi|rdx}},%rax,4), [[X3:%xmm[0-9]+]]
+; CHECK: movaps
+; CHECK:        [[X3]], (%{{rdi|rcx}},%rax,4)
 ; CHECK: addq  $4, %rax
 ; CHECK: cmpl  %eax, (%{{rdx|r8}})
 ; CHECK-NEXT: jg

Modified: llvm/trunk/test/CodeGen/X86/mmx-copy-gprs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mmx-copy-gprs.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mmx-copy-gprs.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mmx-copy-gprs.ll Mon Apr  4 19:32:44 2011
@@ -1,14 +1,12 @@
-; RUN: llc < %s -mtriple=x86_64-linux   | FileCheck %s -check-prefix=X64
-; RUN: llc < %s -mtriple=x86_64-win32   | FileCheck %s -check-prefix=X64
-; X64: movq ({{%rsi|%rdx}}), %rax
-; RUN: llc < %s -march=x86 -mattr=-sse2 | FileCheck %s -check-prefix=X32
-; X32: movl 4(%eax),
-; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=XMM
-; XMM: movsd (%eax),
+; RUN: llc < %s -mtriple=x86_64-linux   | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-win32   | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=-sse2 | FileCheck %s
+; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
 
 ; This test should use GPRs to copy the mmx value, not MMX regs.  Using mmx regs,
 ; increases the places that need to use emms.
-
+; CHECK-NOT: %mm
+; CHECK-NOT: emms
 ; rdar://5741668
 
 define void @foo(<1 x i64>* %x, <1 x i64>* %y) nounwind  {

Modified: llvm/trunk/test/CodeGen/X86/optimize-max-3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/optimize-max-3.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/optimize-max-3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/optimize-max-3.ll Mon Apr  4 19:32:44 2011
@@ -45,8 +45,8 @@
 ; CHECK-NEXT:         align
 ; CHECK-NEXT: BB1_2:
 ; CHECK-NEXT:         callq
-; CHECK-NEXT:         incl    [[BX:%ebx|%esi]]
-; CHECK-NEXT:         cmpl    [[R14:%r14d|%edi]], [[BX]]
+; CHECK-NEXT:         incl    [[BX:%[a-z0-9]+]]
+; CHECK-NEXT:         cmpl    [[R14:%[a-z0-9]+]], [[BX]]
 ; CHECK-NEXT:         movq    %rax, %r{{di|cx}}
 ; CHECK-NEXT:         jl
 

Modified: llvm/trunk/test/CodeGen/X86/or-address.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/or-address.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/or-address.ll (original)
+++ llvm/trunk/test/CodeGen/X86/or-address.ll Mon Apr  4 19:32:44 2011
@@ -4,10 +4,10 @@
 target triple = "x86_64-apple-darwin10.3"
 
 
-; CHECK: 	movl	%{{.*}},   (%rdi,%rdx,4)
-; CHECK:	movl	%{{.*}},  8(%rdi,%rdx,4)
-; CHECK:	movl	%{{.*}},  4(%rdi,%rdx,4)
-; CHECK:	movl	%{{.*}}, 12(%rdi,%rdx,4)
+; CHECK: 	movl	%{{.*}},   (%rdi,[[R0:.+]],4)
+; CHECK:	movl	%{{.*}},  8(%rdi,[[R0]],4)
+; CHECK:	movl	%{{.*}},  4(%rdi,[[R0]],4)
+; CHECK:	movl	%{{.*}}, 12(%rdi,[[R0]],4)
 
 define void @test(i32* nocapture %array, i32 %r0) nounwind ssp noredzone {
 bb.nph:

Modified: llvm/trunk/test/CodeGen/X86/postra-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/postra-licm.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/postra-licm.ll (original)
+++ llvm/trunk/test/CodeGen/X86/postra-licm.ll Mon Apr  4 19:32:44 2011
@@ -2,6 +2,7 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s -check-prefix=X86-64
 
 ; MachineLICM should be able to hoist loop invariant reload out of the loop.
+; Only linear scan needs this, -regalloc=greedy sinks the spill instead.
 ; rdar://7233099
 
 %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
@@ -68,10 +69,12 @@
 
 bb23:                                             ; preds = %imix_test.exit
   unreachable
+; Verify that there are no loads inside the loop.
 ; X86-32: %bb26.preheader
-; X86-32: movl -16(%ebp),
-; X86-32-NEXT: .align 4
-; X86-32-NEXT: %bb28
+; X86-32: .align 4
+; X86-32-NOT: (%esp),
+; X86-32-NOT: (%ebp),
+; X86-32: jmp
 
 bb28:                                             ; preds = %bb28, %bb26.preheader
   %counter.035 = phi i32 [ %3, %bb28 ], [ 0, %bb26.preheader ] ; <i32> [#uses=2]

Modified: llvm/trunk/test/CodeGen/X86/pr3495-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr3495-2.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr3495-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr3495-2.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -relocation-model=pic -disable-fp-elim -stats |& grep {Number of loads added} | grep 1
+; RUN: llc < %s -march=x86 -relocation-model=pic -disable-fp-elim -stats -regalloc=linearscan |& grep {Number of loads added} | grep 1
 ; PR3495
 ;
 ; This test may not be testing what it was supposed to test.

Modified: llvm/trunk/test/CodeGen/X86/pr3495.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr3495.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr3495.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr3495.ll Mon Apr  4 19:32:44 2011
@@ -1,6 +1,6 @@
-; RUN: llc < %s -march=x86 -stats |& grep {Number of loads added} | grep 2
-; RUN: llc < %s -march=x86 -stats |& grep {Number of register spills} | grep 1
-; RUN: llc < %s -march=x86 -stats |& grep {Number of machine instrs printed} | grep 34
+; RUN: llc < %s -march=x86 -stats -regalloc=linearscan |& grep {Number of loads added} | grep 2
+; RUN: llc < %s -march=x86 -stats -regalloc=linearscan |& grep {Number of register spills} | grep 1
+; RUN: llc < %s -march=x86 -stats -regalloc=linearscan |& grep {Number of machine instrs printed} | grep 34
 ; PR3495
 
 target triple = "i386-pc-linux-gnu"

Modified: llvm/trunk/test/CodeGen/X86/pre-split1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split1.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split1.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split1.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \
 ; RUN:   grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
 ; XFAIL: *
 

Modified: llvm/trunk/test/CodeGen/X86/pre-split10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split10.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split10.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split10.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan
 
 define i32 @main(i32 %argc, i8** %argv) nounwind {
 entry:

Modified: llvm/trunk/test/CodeGen/X86/pre-split11.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split11.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split11.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split11.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 -pre-alloc-split | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 -pre-alloc-split -regalloc=linearscan | FileCheck %s
 
 @.str = private constant [28 x i8] c"\0A\0ADOUBLE            D = %f\0A\00", align 1 ; <[28 x i8]*> [#uses=1]
 @.str1 = private constant [37 x i8] c"double to long    l1 = %ld\09\09(0x%lx)\0A\00", align 8 ; <[37 x i8]*> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/pre-split2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split2.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split2.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats -regalloc=linearscan |& \
 ; RUN:   grep {pre-alloc-split} | count 2
 
 define i32 @t(i32 %arg) {

Modified: llvm/trunk/test/CodeGen/X86/pre-split3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split3.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split3.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \
 ; RUN:   grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
 
 define i32 @t(i32 %arg) {

Modified: llvm/trunk/test/CodeGen/X86/pre-split4.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split4.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split4.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split4.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \
 ; RUN:   grep {pre-alloc-split} | grep {Number of intervals split} | grep 2
 
 define i32 @main(i32 %argc, i8** %argv) nounwind {

Modified: llvm/trunk/test/CodeGen/X86/pre-split5.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split5.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split5.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split5.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan
 
 target triple = "i386-apple-darwin9.5"
 	%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }

Modified: llvm/trunk/test/CodeGen/X86/pre-split6.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split6.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split6.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split6.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -pre-alloc-split | grep {divsd	24} | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -pre-alloc-split -regalloc=linearscan | grep {divsd	24} | count 1
 
 @current_surfaces.b = external global i1		; <i1*> [#uses=1]
 

Modified: llvm/trunk/test/CodeGen/X86/pre-split7.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split7.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split7.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split7.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan
 
 @object_distance = external global double, align 8		; <double*> [#uses=1]
 @axis_slope_angle = external global double, align 8		; <double*> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/pre-split8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split8.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split8.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \
 ; RUN:   grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
 
 @current_surfaces.b = external global i1		; <i1*> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/pre-split9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split9.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pre-split9.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pre-split9.ll Mon Apr  4 19:32:44 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -stats |& \
+; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \
 ; RUN:   grep {pre-alloc-split} | grep {Number of intervals split} | grep 1
 
 @current_surfaces.b = external global i1		; <i1*> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/sse2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse2.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse2.ll Mon Apr  4 19:32:44 2011
@@ -178,9 +178,9 @@
         %tmp27 = shufflevector <4 x float> %tmp9, <4 x float> %tmp21, <4 x i32> < i32 0, i32 1, i32 4, i32 5 >                ; <<4 x float>> [#uses=1]
         ret <4 x float> %tmp27
 ; CHECK: test14:
-; CHECK: 	addps	%xmm1, %xmm0
-; CHECK: 	subps	%xmm1, %xmm2
-; CHECK: 	movlhps	%xmm2, %xmm0
+; CHECK: 	addps	[[X1:%xmm[0-9]+]], [[X0:%xmm[0-9]+]]
+; CHECK: 	subps	[[X1]], [[X2:%xmm[0-9]+]]
+; CHECK: 	movlhps	[[X2]], [[X0]]
 }
 
 define <4 x float> @test15(<4 x float>* %x, <4 x float>* %y) nounwind {

Modified: llvm/trunk/test/CodeGen/X86/sse3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sse3.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sse3.ll (original)
+++ llvm/trunk/test/CodeGen/X86/sse3.ll Mon Apr  4 19:32:44 2011
@@ -168,12 +168,12 @@
         store <4 x i16> %6, <4 x i16>* @g2, align 8
         ret void
 ; X64: 	t10:
-; X64: 		pextrw	$4, %xmm0, %eax
-; X64: 		unpcklpd %xmm1, %xmm1
-; X64: 		pshuflw	$8, %xmm1, %xmm1
-; X64: 		pinsrw	$2, %eax, %xmm1
-; X64: 		pextrw	$6, %xmm0, %eax
-; X64: 		pinsrw	$3, %eax, %xmm1
+; X64: 		pextrw	$4, [[X0:%xmm[0-9]+]], %eax
+; X64: 		unpcklpd [[X1:%xmm[0-9]+]]
+; X64: 		pshuflw	$8, [[X1]], [[X1]]
+; X64: 		pinsrw	$2, %eax, [[X1]]
+; X64: 		pextrw	$6, [[X0]], %eax
+; X64: 		pinsrw	$3, %eax, [[X1]]
 }
 
 

Modified: llvm/trunk/test/CodeGen/X86/tail-opts.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-opts.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-opts.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tail-opts.ll Mon Apr  4 19:32:44 2011
@@ -153,16 +153,20 @@
 ; an unconditional jump to complete a two-way conditional branch.
 
 ; CHECK: c_expand_expr_stmt:
-; CHECK:        jmp .LBB3_11
-; CHECK-NEXT: .LBB3_9:
-; CHECK-NEXT:   movq 8(%rax), %rax
-; CHECK-NEXT:   xorb %dl, %dl
-; CHECK-NEXT:   movb 16(%rax), %al
-; CHECK-NEXT:   cmpb $16, %al
-; CHECK-NEXT:   je .LBB3_11
-; CHECK-NEXT:   cmpb $23, %al
-; CHECK-NEXT:   jne .LBB3_14
-; CHECK-NEXT: .LBB3_11:
+;
+; This test only works when register allocation happens to use %rax for both
+; load addresses.
+;
+; CHE:        jmp .LBB3_11
+; CHE-NEXT: .LBB3_9:
+; CHE-NEXT:   movq 8(%rax), %rax
+; CHE-NEXT:   xorb %dl, %dl
+; CHE-NEXT:   movb 16(%rax), %al
+; CHE-NEXT:   cmpb $16, %al
+; CHE-NEXT:   je .LBB3_11
+; CHE-NEXT:   cmpb $23, %al
+; CHE-NEXT:   jne .LBB3_14
+; CHE-NEXT: .LBB3_11:
 
 %0 = type { %struct.rtx_def* }
 %struct.lang_decl = type opaque

Modified: llvm/trunk/test/CodeGen/X86/tailcallstack64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tailcallstack64.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tailcallstack64.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tailcallstack64.ll Mon Apr  4 19:32:44 2011
@@ -6,15 +6,15 @@
 
 ; Check that lowered arguments on the stack do not overwrite each other.
 ; Add %in1 %p1 to a different temporary register (%eax).
-; CHECK: movl  [[A1:32|144]](%rsp), %eax
+; CHECK: movl  [[A1:32|144]](%rsp), [[R1:%e..]]
 ; Move param %in1 to temp register (%r10d).
-; CHECK: movl  [[A2:40|152]](%rsp), %r10d
+; CHECK: movl  [[A2:40|152]](%rsp), [[R2:%[a-z0-9]+]]
 ; Add %in1 %p1 to a different temporary register (%eax).
-; CHECK: addl {{%edi|%ecx}}, %eax
+; CHECK: addl {{%edi|%ecx}}, [[R1]]
 ; Move param %in2 to stack.
-; CHECK: movl  %r10d, [[A1]](%rsp)
+; CHECK: movl  [[R2]], [[A1]](%rsp)
 ; Move result of addition to stack.
-; CHECK: movl  %eax, [[A2]](%rsp)
+; CHECK: movl  [[R1]], [[A2]](%rsp)
 ; Eventually, do a TAILCALL
 ; CHECK: TAILCALL
 

Modified: llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll?rev=128867&r1=128866&r2=128867&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll (original)
+++ llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll Mon Apr  4 19:32:44 2011
@@ -40,10 +40,10 @@
 ; W64: subq  %rax, %rsp
 ; W64: movq  %rsp, %rax
 
-; EFI: leaq  15(%rcx), %rax
-; EFI: andq  $-16, %rax
+; EFI: leaq  15(%rcx), [[R1:%r..]]
+; EFI: andq  $-16, [[R1]]
 ; EFI: movq  %rsp, [[R64:%r..]]
-; EFI: subq  %rax, [[R64]]
+; EFI: subq  [[R1]], [[R64]]
 ; EFI: movq  [[R64]], %rsp
 
   %r = call i64 @bar(i64 %n, i64 %x, i64 %n, i8* %buf0, i8* %buf1) nounwind



From stuart at apple.com  Mon Apr  4 19:37:28 2011
From: stuart at apple.com (Stuart Hastings)
Date: Tue, 05 Apr 2011 00:37:28 -0000
Subject: [llvm-commits] [llvm] r128868 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Message-ID: <20110405003728.98F5F2A6C12C@llvm.org>

Author: stuart
Date: Mon Apr  4 19:37:28 2011
New Revision: 128868

URL: http://llvm.org/viewvc/llvm-project?rev=128868&view=rev
Log:
Revert 123704; it broke threaded LLVM.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=128868&r1=128867&r2=128868&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Apr  4 19:37:28 2011
@@ -66,6 +66,11 @@
   /// against each other, including inserted libcalls.
   SDValue LastCALLSEQ_END;
 
+  /// IsLegalizingCall - This member is used *only* for purposes of providing
+  /// helpful assertions that a libcall isn't created while another call is
+  /// being legalized (which could lead to non-serialized call sequences).
+  bool IsLegalizingCall;
+
   enum LegalizeAction {
     Legal,      // The target natively supports this operation.
     Promote,    // This operation should be executed in a larger type.
@@ -225,6 +230,7 @@
 
 void SelectionDAGLegalize::LegalizeDAG() {
   LastCALLSEQ_END = DAG.getEntryNode();
+  IsLegalizingCall = false;
 
   // The legalize process is inherently a bottom-up recursive process (users
   // legalize their uses before themselves).  Given infinite stack space, we
@@ -1027,7 +1033,6 @@
     }
     break;
   case ISD::CALLSEQ_START: {
-    static int depth = 0;
     SDNode *CallEnd = FindCallEndFromCallStart(Node);
 
     // Recursively Legalize all of the inputs of the call end that do not lead
@@ -1045,7 +1050,7 @@
 
     // Merge in the last call to ensure that this call starts after the last
     // call ended.
-    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken && depth == 0) {
+    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
       Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
                          Tmp1, LastCALLSEQ_END);
       Tmp1 = LegalizeOp(Tmp1);
@@ -1068,18 +1073,14 @@
     // sequence have been legalized, legalize the call itself.  During this
     // process, no libcalls can/will be inserted, guaranteeing that no calls
     // can overlap.
-
-    SDValue Saved_LastCALLSEQ_END = LastCALLSEQ_END ;
+    assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
     // Note that we are selecting this call!
     LastCALLSEQ_END = SDValue(CallEnd, 0);
+    IsLegalizingCall = true;
 
-    depth++;
     // Legalize the call, starting from the CALLSEQ_END.
     LegalizeOp(LastCALLSEQ_END);
-    depth--;
-    assert(depth >= 0 && "Un-matched CALLSEQ_START?");
-    if (depth > 0)
-      LastCALLSEQ_END = Saved_LastCALLSEQ_END;
+    assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
     return Result;
   }
   case ISD::CALLSEQ_END:
@@ -1118,7 +1119,10 @@
                          Result.getResNo());
       }
     }
+    assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
     // This finishes up call legalization.
+    IsLegalizingCall = false;
+
     // If the CALLSEQ_END node has a flag, remember that we legalized it.
     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
     if (Node->getNumValues() == 2)
@@ -2003,6 +2007,7 @@
 // and leave the Hi part unset.
 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
                                             bool isSigned) {
+  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
   // The input chain to this libcall is the entry node of the function.
   // Legalizing the call will automatically add the previous call to the
   // dependence.
@@ -2050,6 +2055,7 @@
 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
                                          SDNode *Node,
                                          bool isSigned) {
+  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
   SDValue InChain = Node->getOperand(0);
 
   TargetLowering::ArgListTy Args;



From stuart at apple.com  Mon Apr  4 19:43:12 2011
From: stuart at apple.com (Stuart Hastings)
Date: Mon, 04 Apr 2011 17:43:12 -0700
Subject: [llvm-commits] [llvm] r123704 -
 /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
In-Reply-To: <BANLkTimWE1eNZU+cuCtqfcyix_GMyhjH+Q@mail.gmail.com>
References: <20110118000928.2D35C2A6C12C@llvm.org>
	<BANLkTimWE1eNZU+cuCtqfcyix_GMyhjH+Q@mail.gmail.com>
Message-ID: <19ECF639-A131-4947-8331-EF5CE7921E5E@apple.com>


On Apr 4, 2011, at 5:16 PM, Nick Lewycky wrote:

> On 17 January 2011 16:09, Stuart Hastings <stuart at apple.com> wrote:
> Author: stuart
> Date: Mon Jan 17 18:09:27 2011
> New Revision: 123704
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=123704&view=rev
> Log:
> Remove checking that prevented overlapping CALLSEQ_START/CALLSEQ_END
> ranges, add legalizer support for nested calls.  Necessary for ARM
> byval support.  Radar 7662569.
> 
> Modified:
>    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=123704&r1=123703&r2=123704&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
> +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon Jan 17 18:09:27 2011
> @@ -66,11 +66,6 @@
>   /// against each other, including inserted libcalls.
>   SDValue LastCALLSEQ_END;
> 
> -  /// IsLegalizingCall - This member is used *only* for purposes of providing
> -  /// helpful assertions that a libcall isn't created while another call is
> -  /// being legalized (which could lead to non-serialized call sequences).
> -  bool IsLegalizingCall;
> -
>   enum LegalizeAction {
>     Legal,      // The target natively supports this operation.
>     Promote,    // This operation should be executed in a larger type.
> @@ -225,7 +220,6 @@
> 
>  void SelectionDAGLegalize::LegalizeDAG() {
>   LastCALLSEQ_END = DAG.getEntryNode();
> -  IsLegalizingCall = false;
> 
>   // The legalize process is inherently a bottom-up recursive process (users
>   // legalize their uses before themselves).  Given infinite stack space, we
> @@ -1024,6 +1018,7 @@
>     }
>     break;
>   case ISD::CALLSEQ_START: {
> +    static int depth = 0;
> 
> Hi Stuart, this breaks using llvm from multiple threads. Please don't use non-constant statics.

Reverted at 128868.

Sorry for your trouble,

stuart

> 
> Nick
>  
>     SDNode *CallEnd = FindCallEndFromCallStart(Node);
> 
>     // Recursively Legalize all of the inputs of the call end that do not lead
> @@ -1041,7 +1036,7 @@
> 
>     // Merge in the last call to ensure that this call starts after the last
>     // call ended.
> -    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
> +    if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken && depth == 0) {
>       Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
>                          Tmp1, LastCALLSEQ_END);
>       Tmp1 = LegalizeOp(Tmp1);
> @@ -1064,14 +1059,18 @@
>     // sequence have been legalized, legalize the call itself.  During this
>     // process, no libcalls can/will be inserted, guaranteeing that no calls
>     // can overlap.
> -    assert(!IsLegalizingCall && "Inconsistent sequentialization of calls!");
> +
> +    SDValue Saved_LastCALLSEQ_END = LastCALLSEQ_END ;
>     // Note that we are selecting this call!
>     LastCALLSEQ_END = SDValue(CallEnd, 0);
> -    IsLegalizingCall = true;
> 
> +    depth++;
>     // Legalize the call, starting from the CALLSEQ_END.
>     LegalizeOp(LastCALLSEQ_END);
> -    assert(!IsLegalizingCall && "CALLSEQ_END should have cleared this!");
> +    depth--;
> +    assert(depth >= 0 && "Un-matched CALLSEQ_START?");
> +    if (depth > 0)
> +      LastCALLSEQ_END = Saved_LastCALLSEQ_END;
>     return Result;
>   }
>   case ISD::CALLSEQ_END:
> @@ -1110,10 +1109,7 @@
>                          Result.getResNo());
>       }
>     }
> -    assert(IsLegalizingCall && "Call sequence imbalance between start/end?");
>     // This finishes up call legalization.
> -    IsLegalizingCall = false;
> -
>     // If the CALLSEQ_END node has a flag, remember that we legalized it.
>     AddLegalizedOperand(SDValue(Node, 0), Result.getValue(0));
>     if (Node->getNumValues() == 2)
> @@ -1949,7 +1945,6 @@
>  // and leave the Hi part unset.
>  SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
>                                             bool isSigned) {
> -  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
>   // The input chain to this libcall is the entry node of the function.
>   // Legalizing the call will automatically add the previous call to the
>   // dependence.
> @@ -1997,7 +1992,6 @@
>  SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
>                                          SDNode *Node,
>                                          bool isSigned) {
> -  assert(!IsLegalizingCall && "Cannot overlap legalization of calls!");
>   SDValue InChain = Node->getOperand(0);
> 
>   TargetLowering::ArgListTy Args;
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 

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From echristo at apple.com  Mon Apr  4 19:39:26 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 05 Apr 2011 00:39:26 -0000
Subject: [llvm-commits] [llvm] r128869 -
	/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
Message-ID: <20110405003926.A97DD2A6C12C@llvm.org>

Author: echristo
Date: Mon Apr  4 19:39:26 2011
New Revision: 128869

URL: http://llvm.org/viewvc/llvm-project?rev=128869&view=rev
Log:
Just use BL all the time. It's safer that way.

Fixes rdar://9184526

Modified:
    llvm/trunk/lib/Target/ARM/ARMFastISel.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=128869&r1=128868&r2=128869&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon Apr  4 19:39:26 2011
@@ -1690,17 +1690,9 @@
 
 unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) {
 
-  // Depend our opcode for thumb on whether or not we're targeting an
-  // externally callable function. For libcalls we'll just pass a NULL GV
-  // in here.
-  bool isExternal = false;
-  if (!GV || GV->hasExternalLinkage()) isExternal = true;
-  
   // Darwin needs the r9 versions of the opcodes.
   bool isDarwin = Subtarget->isTargetDarwin();
-  if (isThumb && isExternal) {
-    return isDarwin ? ARM::tBLXi_r9 : ARM::tBLXi;
-  } else if (isThumb) {
+  if (isThumb) {
     return isDarwin ? ARM::tBLr9 : ARM::tBL;
   } else  {
     return isDarwin ? ARM::BLr9 : ARM::BL;



From echristo at apple.com  Mon Apr  4 19:56:01 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 05 Apr 2011 00:56:01 -0000
Subject: [llvm-commits] [llvm] r128870 -
	/llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll
Message-ID: <20110405005601.6315E2A6C12C@llvm.org>

Author: echristo
Date: Mon Apr  4 19:56:01 2011
New Revision: 128870

URL: http://llvm.org/viewvc/llvm-project?rev=128870&view=rev
Log:
Fix up testcase for previous commit.

Modified:
    llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll

Modified: llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll?rev=128870&r1=128869&r2=128870&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fast-isel-static.ll Mon Apr  4 19:56:01 2011
@@ -24,7 +24,7 @@
   store float 0.000000e+00, float* %ztot, align 4
   store float 1.000000e+00, float* %z, align 4
 ; CHECK-LONG: blx     r2
-; CHECK-NORM: blx     _myadd
+; CHECK-NORM: bl      _myadd
   call void @myadd(float* %ztot, float* %z)
   ret i32 0
 }



From aggarwa4 at illinois.edu  Mon Apr  4 20:36:02 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 05 Apr 2011 01:36:02 -0000
Subject: [llvm-commits] [poolalloc] r128872 -
	/poolalloc/trunk/lib/AssistDS/ArgSimplify.cpp
Message-ID: <20110405013602.3F8B42A6C12C@llvm.org>

Author: aggarwa4
Date: Mon Apr  4 20:36:02 2011
New Revision: 128872

URL: http://llvm.org/viewvc/llvm-project?rev=128872&view=rev
Log:
Handle cases where the Type to cast from is an integer.

Modified:
    poolalloc/trunk/lib/AssistDS/ArgSimplify.cpp

Modified: poolalloc/trunk/lib/AssistDS/ArgSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/ArgSimplify.cpp?rev=128872&r1=128871&r2=128872&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/ArgSimplify.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/ArgSimplify.cpp Mon Apr  4 20:36:02 2011
@@ -93,14 +93,16 @@
                           Value *CastedVal;
                           BasicBlock* entryBB = BasicBlock::
                             Create (M->getContext(), "entry", NewF);
-                        
-                          if(type->isIntegerTy()){
-                            CastedVal = new PtrToIntInst(fargs.at(arg_count), 
+                       
+                          const Type *FromTy = fargs.at(arg_count)->getType();
+                          if(FromTy->isPointerTy()) {
+                            CastedVal = CastInst::CreatePointerCast(fargs.at(arg_count), 
                                                          type, "castd", entryBB);
                           } else {
-                            CastedVal = new BitCastInst(fargs.at(arg_count), 
-                                                        type, "castd", entryBB);
+                            CastedVal = CastInst::CreateIntegerCast(fargs.at(arg_count), 
+                                                                    type, false, "casted", entryBB);
                           }
+
                           SmallVector<Value*, 8> Args;
                           for(Function::arg_iterator ai = NewF->arg_begin(),
                               ae= NewF->arg_end(); ai != ae; ++ai) {
@@ -109,14 +111,14 @@
                             else 
                               Args.push_back(ai);
                           }
-                          
+
                           CallInst * CallI = CallInst::Create(F,Args.begin(), 
                                                               Args.end(),"", entryBB);
                           if(CallI->getType()->isVoidTy())
                             ReturnInst::Create(M->getContext(), entryBB);
                           else 
                             ReturnInst::Create(M->getContext(), CallI, entryBB);
-                          
+
                           CI->setCalledFunction(NewF);
                           numTransformable++;
                         }
@@ -131,14 +133,14 @@
       }
     }
   }
-  
+
   class ArgSimplify : public ModulePass {
   public:
     static char ID;
     ArgSimplify() : ModulePass(&ID) {}
 
     bool runOnModule(Module& M) {
-    
+
       for (Module::iterator I = M.begin(); I != M.end(); ++I) 
         if (!I->isDeclaration() && !I->mayBeOverridden()) {
           if(I->getNameStr() == "main")
@@ -162,7 +164,7 @@
             }
           }
         }
-      
+
 
       return true;
     }



From isanbard at gmail.com  Mon Apr  4 20:37:43 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 05 Apr 2011 01:37:43 -0000
Subject: [llvm-commits] [llvm] r128873 - in /llvm/trunk:
 include/llvm/Intrinsics.td lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 lib/CodeGen/SjLjEHPrepare.cpp lib/Target/ARM/ARMISelLowering.cpp
 lib/Target/ARM/ARMInstrInfo.td
Message-ID: <20110405013743.DEBED2A6C12C@llvm.org>

Author: void
Date: Mon Apr  4 20:37:43 2011
New Revision: 128873

URL: http://llvm.org/viewvc/llvm-project?rev=128873&view=rev
Log:
Revamp the SjLj "dispatch setup" intrinsic.

It needed to be moved closer to the setjmp statement, because the code directly
after the setjmp needs to know about values that are on the stack. Also, the
'bitcast' of the function context was causing a dead load. This wouldn't be too
horrible, except that at -O0 it wasn't optimized out, and because it wasn't
using the correct base pointer (if there is a VLA), it would try to access a
value from a garbage address.
<rdar://problem/9130540>

Modified:
    llvm/trunk/include/llvm/Intrinsics.td
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=128873&r1=128872&r2=128873&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Mon Apr  4 20:37:43 2011
@@ -307,7 +307,7 @@
   def int_eh_sjlj_lsda    : Intrinsic<[llvm_ptr_ty]>;
   def int_eh_sjlj_callsite: Intrinsic<[], [llvm_i32_ty]>;
 }
-def int_eh_sjlj_dispatch_setup : Intrinsic<[], [llvm_ptr_ty]>;
+def int_eh_sjlj_dispatch_setup : Intrinsic<[], []>;
 def int_eh_sjlj_setjmp  : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
 def int_eh_sjlj_longjmp : Intrinsic<[], [llvm_ptr_ty]>;
 

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=128873&r1=128872&r2=128873&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Apr  4 20:37:43 2011
@@ -4403,7 +4403,7 @@
   }
   case Intrinsic::eh_sjlj_dispatch_setup: {
     DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
-                            getRoot(), getValue(I.getArgOperand(0))));
+                            getRoot()));
     return 0;
   }
 

Modified: llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp?rev=128873&r1=128872&r2=128873&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp (original)
+++ llvm/trunk/lib/CodeGen/SjLjEHPrepare.cpp Mon Apr  4 20:37:43 2011
@@ -442,14 +442,6 @@
   BasicBlock *DispatchBlock =
     BasicBlock::Create(F.getContext(), "eh.sjlj.setjmp.catch", &F);
 
-  // Add a call to dispatch_setup at the start of the dispatch block. This is
-  // expanded to any target-specific setup that needs to be done.
-  Value *SetupArg =
-    CastInst::Create(Instruction::BitCast, FunctionContext,
-                     Type::getInt8PtrTy(F.getContext()), "",
-                     DispatchBlock);
-  CallInst::Create(DispatchSetupFn, SetupArg, "", DispatchBlock);
-
   // Insert a load of the callsite in the dispatch block, and a switch on its
   // value.  By default, we go to a block that just does an unwind (which is the
   // correct action for a standard call).
@@ -524,6 +516,11 @@
   Value *DispatchVal = CallInst::Create(BuiltinSetjmpFn, SetjmpArg,
                                         "dispatch",
                                         EntryBB->getTerminator());
+
+  // Add a call to dispatch_setup after the setjmp call. This is expanded to any
+  // target-specific setup that needs to be done.
+  CallInst::Create(DispatchSetupFn, "", EntryBB->getTerminator());
+
   // check the return value of the setjmp. non-zero goes to dispatcher.
   Value *IsNormal = new ICmpInst(EntryBB->getTerminator(),
                                  ICmpInst::ICMP_EQ, DispatchVal, Zero,

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=128873&r1=128872&r2=128873&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Apr  4 20:37:43 2011
@@ -2113,7 +2113,7 @@
   const {
   DebugLoc dl = Op.getDebugLoc();
   return DAG.getNode(ARMISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other,
-                     Op.getOperand(0), Op.getOperand(1));
+                     Op.getOperand(0));
 }
 
 SDValue

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128873&r1=128872&r2=128873&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Apr  4 20:37:43 2011
@@ -58,7 +58,7 @@
                                                  SDTCisInt<2>]>;
 def SDT_ARMEH_SJLJ_Longjmp: SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisInt<1>]>;
 
-def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
+def SDT_ARMEH_SJLJ_DispatchSetup: SDTypeProfile<0, 0, []>;
 
 def SDT_ARMMEMBARRIER     : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
 
@@ -3777,8 +3777,8 @@
 // that need the instruction size).
 let isBarrier = 1, hasSideEffects = 1 in
 def Int_eh_sjlj_dispatchsetup :
- PseudoInst<(outs), (ins GPR:$src), NoItinerary,
-            [(ARMeh_sjlj_dispatchsetup GPR:$src)]>,
+ PseudoInst<(outs), (ins), NoItinerary,
+            [(ARMeh_sjlj_dispatchsetup)]>,
               Requires<[IsDarwin]>;
 
 //===----------------------------------------------------------------------===//



From stoklund at 2pi.dk  Mon Apr  4 23:20:27 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 04:20:27 -0000
Subject: [llvm-commits] [llvm] r128874 - in /llvm/trunk:
 include/llvm/CodeGen/MachineBasicBlock.h lib/CodeGen/SplitKit.cpp
 lib/CodeGen/SplitKit.h
Message-ID: <20110405042027.458722A6C12C@llvm.org>

Author: stoklund
Date: Mon Apr  4 23:20:27 2011
New Revision: 128874

URL: http://llvm.org/viewvc/llvm-project?rev=128874&view=rev
Log:
Cache the fairly expensive last split point computation and provide a fast
inlined path for the common case.

Most basic blocks don't contain a call that may throw, so the last split point
os simply the first terminator.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/CodeGen/SplitKit.h

Modified: llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h?rev=128874&r1=128873&r2=128874&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineBasicBlock.h Mon Apr  4 23:20:27 2011
@@ -305,6 +305,10 @@
   /// it returns end()
   iterator getFirstTerminator();
 
+  const_iterator getFirstTerminator() const {
+    return const_cast<MachineBasicBlock*>(this)->getFirstTerminator();
+  }
+
   /// getLastNonDebugInstr - returns an iterator to the last non-debug
   /// instruction in the basic block, or end()
   iterator getLastNonDebugInstr();

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=128874&r1=128873&r2=128874&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Mon Apr  4 23:20:27 2011
@@ -48,7 +48,8 @@
     LIS(lis),
     Loops(mli),
     TII(*MF.getTarget().getInstrInfo()),
-    CurLI(0) {}
+    CurLI(0),
+    LastSplitPoint(MF.getNumBlockIDs()) {}
 
 void SplitAnalysis::clear() {
   UseSlots.clear();
@@ -58,10 +59,39 @@
   CurLI = 0;
 }
 
-bool SplitAnalysis::canAnalyzeBranch(const MachineBasicBlock *MBB) {
-  MachineBasicBlock *T, *F;
-  SmallVector<MachineOperand, 4> Cond;
-  return !TII.AnalyzeBranch(const_cast<MachineBasicBlock&>(*MBB), T, F, Cond);
+SlotIndex SplitAnalysis::computeLastSplitPoint(unsigned Num) {
+  const MachineBasicBlock *MBB = MF.getBlockNumbered(Num);
+  const MachineBasicBlock *LPad = MBB->getLandingPadSuccessor();
+  std::pair<SlotIndex, SlotIndex> &LSP = LastSplitPoint[Num];
+
+  // Compute split points on the first call. The pair is independent of the
+  // current live interval.
+  if (!LSP.first.isValid()) {
+    MachineBasicBlock::const_iterator FirstTerm = MBB->getFirstTerminator();
+    if (FirstTerm == MBB->end())
+      LSP.first = LIS.getMBBEndIdx(MBB);
+    else
+      LSP.first = LIS.getInstructionIndex(FirstTerm);
+
+    // If there is a landing pad successor, also find the call instruction.
+    if (!LPad)
+      return LSP.first;
+    // There may not be a call instruction (?) in which case we ignore LPad.
+    LSP.second = LSP.first;
+    for (MachineBasicBlock::const_iterator I = FirstTerm, E = MBB->begin();
+         I != E; --I)
+      if (I->getDesc().isCall()) {
+        LSP.second = LIS.getInstructionIndex(I);
+        break;
+      }
+  }
+
+  // If CurLI is live into a landing pad successor, move the last split point
+  // back to the call that may throw.
+  if (LPad && LSP.second.isValid() && !LIS.isLiveInToMBB(*CurLI, LPad))
+    return LSP.second;
+  else
+    return LSP.first;
 }
 
 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
@@ -125,11 +155,7 @@
     // all successor blocks. If interference reaches LastSplitPoint, it is not
     // possible to insert a split or reload that makes CurLI live in the
     // outgoing bundle.
-    MachineBasicBlock::iterator LSP = LIS.getLastSplitPoint(*CurLI, BI.MBB);
-    if (LSP == BI.MBB->end())
-      BI.LastSplitPoint = Stop;
-    else
-      BI.LastSplitPoint = LIS.getInstructionIndex(LSP);
+    BI.LastSplitPoint = getLastSplitPoint(BI.MBB->getNumber());
 
     // LVI is the first live segment overlapping MBB.
     BI.LiveIn = LVI->start <= Start;

Modified: llvm/trunk/lib/CodeGen/SplitKit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=128874&r1=128873&r2=128874&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.h (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.h Mon Apr  4 23:20:27 2011
@@ -93,16 +93,20 @@
   // Current live interval.
   const LiveInterval *CurLI;
 
+  /// LastSplitPoint - Last legal split point in each basic block in the current
+  /// function. The first entry is the first terminator, the second entry is the
+  /// last valid split point for a variable that is live in to a landing pad
+  /// successor.
+  SmallVector<std::pair<SlotIndex, SlotIndex>, 8> LastSplitPoint;
+
+  SlotIndex computeLastSplitPoint(unsigned Num);
+
   // Sumarize statistics by counting instructions using CurLI.
   void analyzeUses();
 
   /// calcLiveBlockInfo - Compute per-block information about CurLI.
   bool calcLiveBlockInfo();
 
-  /// canAnalyzeBranch - Return true if MBB ends in a branch that can be
-  /// analyzed.
-  bool canAnalyzeBranch(const MachineBasicBlock *MBB);
-
 public:
   SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
                 const MachineLoopInfo &mli);
@@ -118,6 +122,16 @@
   /// getParent - Return the last analyzed interval.
   const LiveInterval &getParent() const { return *CurLI; }
 
+  /// getLastSplitPoint - Return that base index of the last valid split point
+  /// in the basic block numbered Num.
+  SlotIndex getLastSplitPoint(unsigned Num) {
+    // Inline the common simple case.
+    if (LastSplitPoint[Num].first.isValid() &&
+        !LastSplitPoint[Num].second.isValid())
+      return LastSplitPoint[Num].first;
+    return computeLastSplitPoint(Num);
+  }
+
   /// hasUses - Return true if MBB has any uses of CurLI.
   bool hasUses(const MachineBasicBlock *MBB) const {
     return UsingBlocks.lookup(MBB);



From stoklund at 2pi.dk  Mon Apr  4 23:20:29 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 04:20:29 -0000
Subject: [llvm-commits] [llvm] r128875 - in /llvm/trunk/lib/CodeGen:
 RegAllocGreedy.cpp SplitKit.cpp SplitKit.h
Message-ID: <20110405042030.0A16F2A6C12D@llvm.org>

Author: stoklund
Date: Mon Apr  4 23:20:29 2011
New Revision: 128875

URL: http://llvm.org/viewvc/llvm-project?rev=128875&view=rev
Log:
Stop precomputing last split points, query the SplitAnalysis cache on demand.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/CodeGen/SplitKit.h

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=128875&r1=128874&r2=128875&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Mon Apr  4 23:20:29 2011
@@ -445,7 +445,7 @@
 
     // Interference for the live-out value.
     if (BI.LiveOut) {
-      if (Intf.last() >= BI.LastSplitPoint)
+      if (Intf.last() >= SA->getLastSplitPoint(BC.Number))
         BC.Exit = SpillPlacement::MustSpill, Ins += BI.Uses;
       else if (!BI.Uses)
         BC.Exit = SpillPlacement::PrefSpill;
@@ -530,9 +530,9 @@
     Intf.moveToBlock(BI.MBB->getNumber());
     DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#"
                  << Bundles->getBundle(BI.MBB->getNumber(), 1)
-                 << " [" << Start << ';' << BI.LastSplitPoint << '-'
-                 << Stop << ") intf [" << Intf.first() << ';' << Intf.last()
-                 << ')');
+                 << " [" << Start << ';'
+                 << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop
+                 << ") intf [" << Intf.first() << ';' << Intf.last() << ')');
 
     // The interference interval should either be invalid or overlap MBB.
     assert((!Intf.hasInterference() || Intf.first() < Stop)
@@ -588,6 +588,7 @@
       continue;
     }
 
+    SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber());
     if (Intf.last().getBoundaryIndex() < BI.LastUse) {
       // There are interference-free uses at the end of the block.
       // Find the first use that can get the live-out register.
@@ -598,11 +599,11 @@
       SlotIndex Use = *UI;
       assert(Use <= BI.LastUse && "Couldn't find last use");
       // Only attempt a split befroe the last split point.
-      if (Use.getBaseIndex() <= BI.LastSplitPoint) {
+      if (Use.getBaseIndex() <= LastSplitPoint) {
         DEBUG(dbgs() << ", free use at " << Use << ".\n");
         SlotIndex SegStart = SE->enterIntvBefore(Use);
         assert(SegStart >= Intf.last() && "Couldn't avoid interference");
-        assert(SegStart < BI.LastSplitPoint && "Impossible split point");
+        assert(SegStart < LastSplitPoint && "Impossible split point");
         SE->useIntv(SegStart, Stop);
         continue;
       }
@@ -630,7 +631,8 @@
     Intf.moveToBlock(BI.MBB->getNumber());
     DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0)
                  << " -> BB#" << BI.MBB->getNumber() << " [" << Start << ';'
-                 << BI.LastSplitPoint << '-' << Stop << ')');
+                 << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop
+                 << ')');
 
     // Check interference entering the block.
     if (!Intf.hasInterference()) {
@@ -654,9 +656,10 @@
         continue;
       }
       if (!RegOut) {
+        SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber());
         // Block is live-through, but exit bundle is on the stack.
         // Spill immediately after the last use.
-        if (BI.LastUse < BI.LastSplitPoint) {
+        if (BI.LastUse < LastSplitPoint) {
           DEBUG(dbgs() << ", uses, stack-out.\n");
           SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse));
           continue;
@@ -664,8 +667,8 @@
         // The last use is after the last split point, it is probably an
         // indirect jump.
         DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point "
-                     << BI.LastSplitPoint << ", stack-out.\n");
-        SlotIndex SegEnd = SE->leaveIntvBefore(BI.LastSplitPoint);
+                     << LastSplitPoint << ", stack-out.\n");
+        SlotIndex SegEnd = SE->leaveIntvBefore(LastSplitPoint);
         SE->useIntv(Start, SegEnd);
         // Run a double interval from the split to the last use.
         // This makes it possible to spill the complement without affecting the

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=128875&r1=128874&r2=128875&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Mon Apr  4 23:20:29 2011
@@ -151,12 +151,6 @@
     SlotIndex Start, Stop;
     tie(Start, Stop) = LIS.getSlotIndexes()->getMBBRange(BI.MBB);
 
-    // The last split point is the latest possible insertion point that dominates
-    // all successor blocks. If interference reaches LastSplitPoint, it is not
-    // possible to insert a split or reload that makes CurLI live in the
-    // outgoing bundle.
-    BI.LastSplitPoint = getLastSplitPoint(BI.MBB->getNumber());
-
     // LVI is the first live segment overlapping MBB.
     BI.LiveIn = LVI->start <= Start;
     if (!BI.LiveIn)
@@ -947,13 +941,14 @@
       continue;
 
     openIntv();
+    SlotIndex LastSplitPoint = SA.getLastSplitPoint(BI.MBB->getNumber());
     SlotIndex SegStart = enterIntvBefore(std::min(BI.FirstUse,
-                                                  BI.LastSplitPoint));
-    if (!BI.LiveOut || BI.LastUse < BI.LastSplitPoint) {
+                                                  LastSplitPoint));
+    if (!BI.LiveOut || BI.LastUse < LastSplitPoint) {
       useIntv(SegStart, leaveIntvAfter(BI.LastUse));
     } else {
       // The last use is after the last valid split point.
-      SlotIndex SegStop = leaveIntvBefore(BI.LastSplitPoint);
+      SlotIndex SegStop = leaveIntvBefore(LastSplitPoint);
       useIntv(SegStart, SegStop);
       overlapIntv(SegStop, BI.LastUse);
     }

Modified: llvm/trunk/lib/CodeGen/SplitKit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=128875&r1=128874&r2=128875&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.h (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.h Mon Apr  4 23:20:29 2011
@@ -77,8 +77,6 @@
     SlotIndex LastUse;    ///< Last instr using current reg.
     SlotIndex Kill;       ///< Interval end point inside block.
     SlotIndex Def;        ///< Interval start point inside block.
-    /// Last possible point for splitting live ranges.
-    SlotIndex LastSplitPoint;
     bool Uses;            ///< Current reg has uses or defs in block.
     bool LiveThrough;     ///< Live in whole block (Templ 5. or 6. above).
     bool LiveIn;          ///< Current reg is live in.



From sabre at nondot.org  Tue Apr  5 02:19:28 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 05 Apr 2011 07:19:28 -0000
Subject: [llvm-commits] [llvm] r128879 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20110405071928.42F822A6C12C@llvm.org>

Author: lattner
Date: Tue Apr  5 02:19:28 2011
New Revision: 128879

URL: http://llvm.org/viewvc/llvm-project?rev=128879&view=rev
Log:
add a bunch of notes to myself, this is not intended to be gramatic or
make sense to anyone else.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128879&r1=128878&r2=128879&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Apr  5 02:19:28 2011
@@ -61,8 +61,6 @@
 
 </div>
 
-<!-- NOTE: last release for llvm-gcc --> 
-
 <!--
 Almost dead code.
   lib/Transforms/IPO/MergeFunctions.cpp => consider for 3.0.
@@ -73,7 +71,6 @@
   combiner-aa?
   strong phi elim
   loop dependence analysis
-  TBAA
   CorrelatedValuePropagation
  -->
  
@@ -111,7 +108,18 @@
 production-quality compiler for C, Objective-C, C++ and Objective-C++ on x86
 (32- and 64-bit), and for darwin-arm targets.</p>
 
-<p>In the LLVM 2.9 time-frame, the Clang team has made many improvements:</p>
+<p>In the LLVM 2.9 time-frame, the Clang team has made many improvements in C,
+C++ and Objective-C support.  C++ support is now generally rock solid, has
+been exercised on a broad variety of code, and has several new C++'0x features
+implemented (such as rvalue references and variadic templates).  LLVM 2.9 has
+also brought in a large range of bug fixes and minor features (e.g. __label__
+support), and is much more compatible with the Linux Kernel.</p>  
+  
+<p>If Clang rejects your code that is built with another compiler, please take a
+look at the <a href="http://clang.llvm.org/compatibility.html">language
+compatibility</a> guide to make sure the issue isn't intentional or a known
+issue.
+</p>
 
 <ul>
 </ul>
@@ -119,25 +127,6 @@
 
 <!--=========================================================================-->
 <div class="doc_subsection">
-<a name="clangsa">Clang Static Analyzer</a>
-</div>
-
-<div class="doc_text">
-
-<p>The <a href="http://clang-analyzer.llvm.org/">Clang Static Analyzer</a>
-   project is an effort to use static source code analysis techniques to
-   automatically find bugs in C and Objective-C programs (and hopefully <a
-   href="http://clang-analyzer.llvm.org/dev_cxx.html">C++ in the
-   future</a>!).  The tool is very good at finding bugs that occur on specific
-   paths through code, such as on error conditions.</p>
-
-<p>The LLVM 2.9 release... 
-</p>
-
-</div>
-
-<!--=========================================================================-->
-<div class="doc_subsection">
 <a name="dragonegg">DragonEgg: GCC front-ends, LLVM back-end</a>
 </div>
 
@@ -170,21 +159,6 @@
 
 <!--=========================================================================-->
 <div class="doc_subsection">
-<a name="vmkit">VMKit: JVM Virtual Machine Implementation</a>
-</div>
-
-<div class="doc_text">
-<p>
-The <a href="http://vmkit.llvm.org/">VMKit project</a> is an implementation of
-a Java Virtual Machine (Java VM or JVM) that uses LLVM for static and
-just-in-time compilation.
-
-UPDATE.
-</p>
-</div>
-
-<!--=========================================================================-->
-<div class="doc_subsection">
 <a name="compiler-rt">compiler-rt: Compiler Runtime Library</a>
 </div>
 
@@ -203,7 +177,9 @@
 All of the code in the compiler-rt project is available under the standard LLVM
 License, a "BSD-style" license.  
 
-NEW: MIT License as well.
+compiler_rt is now dual licensed under MIT and UIUC license
+  
+Several minor changes for better ARM support.
 
 New in LLVM 2.9,  UPDATE</p>
 
@@ -224,8 +200,9 @@
 
 <p>
 LLDB is in early development and not included as part of the LLVM 2.9 release,
-UPDATE!
 
+  
+  
 <!--
 but is mature enough to support basic debugging scenarios on Mac OS X in C,
 Objective-C and C++.  We'd really like help extending and expanding LLDB to 
@@ -249,6 +226,8 @@
 <p>
 As of the LLVM 2.9 release, UPDATE!
 
+libc++ is now dual licensed under MIT and UIUC license
+  
 <!--libc++ is virtually feature complete, but would
 benefit from more testing and better integration with Clang++.  It is also
 looking forward to the C++ committee finalizing the C++'0x standard.-->
@@ -318,7 +297,70 @@
 <p>LLVM 2.9 includes several major new capabilities:</p>
 
 <ul>
+  last release for llvm-gcc
+TBAA
+Triple::normalize is new, llvm triples are always stored in normalized form internally.
+
+MC Assembler: X86 now generates much better diagnostics for common errors,
+    is much faster at matching instructions, is much more bug-compatible with
+    the GAS assembler, and is now generally useful for a broad range of X86
+    assembly.
+  
+New Nvidia PTX backend, not generally useful in 2.9 though.
+
+Much better debug info generated, particularly in optimized code situations.
+
+ARM Fast ISel
+
+ELF MC support
+
+X86: Reimplemented all of MMX to introduce a new LLVM IR x86_mmx type.  Now
+  random types like &lt;2 x i32&gt; are not iseld to mmx without emms.
+
+Some basic <a href="CodeGenerator.html#mc">internals documentation</a> for MC. 
+  
+MC Assembler support for .file and .loc.
+  
+  
+inline asm multiple alternative constraint support.
+  
+LoopIdiom: memset/memcpy formation
+  
+  
+X86 support for FS/GS relative loads and stores using address space 256/257 are
+  reliable now.
+  
+ARM: New code placement pass.
+  
+  
+PointerTracking has been removed from mainline, moved to ClamAV.
+  
+EarlyCSE pass.
+
+
+ARM: Improved code generation for Cortex-A8 and Cortex-A9 CPUs.
+  
+Scheduler now models operand latency and pipeline forwarding.
+  
+Major regalloc rewrite, not on by default for 2.9.
+MC assembler support for 3dNow! and 3DNowA instructions.
+  
+LoopIndexSplit pass was removed, unmaintained.
+  
+ 
+COFF support in the MC assembler has made a lot of progress in the 2.9
+  timeframe, but is still not generally useful.  Please see 
+  "http://llvm.org/bugs/showdependencytree.cgi?id=9100&amp;hide_resolved=1" for open bugs"?
+
+New <a href="WritingAnLLVMPass.html#RegionPass">RegionPass</a> infrastructure
+  for region-based optimizations.
+  
+MicroBlaze: major updates for aggressive delay slot filler, MC-based assembly
+   printing, assembly instruction parsing, ELF .o file emission, and MC
+   instruction disassembler.
 </ul>
+  
+Still todo: [101025-110228]
 
 </div>
 



From geek4civic at gmail.com  Tue Apr  5 03:24:16 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 05 Apr 2011 08:24:16 -0000
Subject: [llvm-commits] [llvm] r128881 - /llvm/trunk/docs/GettingStarted.html
Message-ID: <20110405082416.5A7C92A6C12D@llvm.org>

Author: chapuni
Date: Tue Apr  5 03:24:15 2011
New Revision: 128881

URL: http://llvm.org/viewvc/llvm-project?rev=128881&view=rev
Log:
docs/GettingStarted.html: FIXME: dg, lit, and source tree layout.

Modified:
    llvm/trunk/docs/GettingStarted.html

Modified: llvm/trunk/docs/GettingStarted.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/GettingStarted.html?rev=128881&r1=128880&r2=128881&view=diff
==============================================================================
--- llvm/trunk/docs/GettingStarted.html (original)
+++ llvm/trunk/docs/GettingStarted.html Tue Apr  5 03:24:15 2011
@@ -404,6 +404,11 @@
       <td>Subversion access to LLVM<sup><a href="#sf2">2</a></sup></td>
     </tr>
 
+    <!-- FIXME:
+    Do we support dg?
+    Are DejaGnu and expect obsolete?
+    Shall we mention Python? -->
+
     <tr>
       <td><a href="http://savannah.gnu.org/projects/dejagnu">DejaGnu</a></td>
       <td>1.4.2</td>
@@ -1335,6 +1340,10 @@
   <dd> This directory contains the major parts of the code generator: Instruction 
   Selector, Instruction Scheduling, and Register Allocation.</dd>
 
+  <dt><tt><b>llvm/lib/MC/</b></tt></dt>
+  <dd>(FIXME: T.B.D.)</dd>
+
+  <!--FIXME: obsoleted -->
   <dt><tt><b>llvm/lib/Debugger/</b></tt></dt>
   <dd> This directory contains the source level debugger library that makes 
   it possible to instrument LLVM programs so that a debugger could identify 
@@ -1348,6 +1357,7 @@
   <dd> This directory contains the source code that corresponds to the header 
   files located in <tt>llvm/include/Support/</tt>.</dd>
 
+  <!--FIXME: obsoleted -->
   <dt><tt><b>llvm/lib/System/</b></tt></dt>
   <dd>This directory contains the operating system abstraction layer that
   shields LLVM from platform-specific coding.</dd>



From geek4civic at gmail.com  Tue Apr  5 03:24:22 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 05 Apr 2011 08:24:22 -0000
Subject: [llvm-commits] [llvm] r128882 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20110405082422.AFD6A2A6C12E@llvm.org>

Author: chapuni
Date: Tue Apr  5 03:24:22 2011
New Revision: 128882

URL: http://llvm.org/viewvc/llvm-project?rev=128882&view=rev
Log:
docs/ReleaseNotes.html: Add a few notes to MCCOFF and x64. FIXME: fixme!

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128882&r1=128881&r2=128882&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Apr  5 03:24:22 2011
@@ -297,10 +297,13 @@
 <p>LLVM 2.9 includes several major new capabilities:</p>
 
 <ul>
+<li><pre>
   last release for llvm-gcc
 TBAA
 Triple::normalize is new, llvm triples are always stored in normalized form internally.
 
+Triple x86_64--mingw64 is obsoleted. Use x86_64--mingw32 instead.
+
 MC Assembler: X86 now generates much better diagnostics for common errors,
     is much faster at matching instructions, is much more bug-compatible with
     the GAS assembler, and is now generally useful for a broad range of X86
@@ -348,9 +351,9 @@
 LoopIndexSplit pass was removed, unmaintained.
   
  
-COFF support in the MC assembler has made a lot of progress in the 2.9
+Win32 PE-COFF support in the MC assembler has made a lot of progress in the 2.9
   timeframe, but is still not generally useful.  Please see 
-  "http://llvm.org/bugs/showdependencytree.cgi?id=9100&amp;hide_resolved=1" for open bugs"?
+  "http://llvm.org/bugs/showdependencytree.cgi?id=9100&amp;hide_resolved=1" for open bugs?
 
 New <a href="WritingAnLLVMPass.html#RegionPass">RegionPass</a> infrastructure
   for region-based optimizations.
@@ -358,6 +361,7 @@
 MicroBlaze: major updates for aggressive delay slot filler, MC-based assembly
    printing, assembly instruction parsing, ELF .o file emission, and MC
    instruction disassembler.
+</pre></li>
 </ul>
   
 Still todo: [101025-110228]
@@ -431,8 +435,7 @@
 LLVM MC Project Blog Post</a>.
 </p>
 
-</div>	
-
+</div>
 
 <!--=========================================================================-->
 <div class="doc_subsection">
@@ -461,6 +464,7 @@
 </p>
 
 <ul>
+  <li>Several bugs have been fixed for Windows x64 code generator.</li>
 </ul>
 
 </div>
@@ -569,13 +573,23 @@
     all <a href="http://llvm.org/PR879">inline assembly that uses the X86
     floating point stack</a>.  It supports the 'f' and 't' constraints, but not
     'u'.</li>
-  <li>Win64 code generation wasn't widely tested. Everything should work, but we
-    expect small issues to happen. Also, llvm-gcc cannot build the mingw64
-    runtime currently due to lack of support for the 'u' inline assembly
-    constraint and for X87 floating point inline assembly.</li>
   <li>The X86-64 backend does not yet support the LLVM IR instruction
       <tt>va_arg</tt>. Currently, front-ends support variadic
       argument constructs on X86-64 by lowering them manually.</li>
+  <li>Windows x64 (aka Win64) code generator has a few issues.
+    <ul>
+      <li>llvm-gcc cannot build the mingw-w64 runtime currently
+       due to lack of support for the 'u' inline assembly
+       constraint and for X87 floating point inline assembly.</li>
+      <li>On mingw-w64, you will see unresolved symbol <tt>__chkstk</tt>
+       due to <a href="http://llvm.org/bugs/show_bug.cgi?id=8919">Bug 8919</a>.
+       It is fixed in <a href="http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110321/118499.html">r128206</a>.</li>
+      <li>Miss-aligned MOVDQA might crash your program. It is due to
+       <a href="http://llvm.org/bugs/show_bug.cgi?id=9483">Bug 9483</a>,
+       lack of handling aligned internal globals.</li>
+      </ul>
+  </li>
+
 </ul>
 
 </div>



From geek4civic at gmail.com  Tue Apr  5 04:29:57 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 5 Apr 2011 18:29:57 +0900
Subject: [llvm-commits] [PATCH] docs/ReleaseNotes.html: Please use proper
 *Heading* elements instead of classified div.
Message-ID: <BANLkTik-eNUpXP_ahaNOVa3X349tieZKwg@mail.gmail.com>

It would be better to browse without stylesheet. (eg. on ViewVC)
---
 docs/ReleaseNotes.html |  122 ++++++++++++++++++++++++------------------------
 1 files changed, 61 insertions(+), 61 deletions(-)
-------------- next part --------------
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From baldrick at free.fr  Tue Apr  5 05:56:02 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 05 Apr 2011 10:56:02 -0000
Subject: [llvm-commits] [dragonegg] r128883 -
	/dragonegg/trunk/gcc_revision_tested_with
Message-ID: <20110405105602.592892A6C12C@llvm.org>

Author: baldrick
Date: Tue Apr  5 05:56:02 2011
New Revision: 128883

URL: http://llvm.org/viewvc/llvm-project?rev=128883&view=rev
Log:
Move the builders to a more recent gcc-4.5 revision.

Modified:
    dragonegg/trunk/gcc_revision_tested_with

Modified: dragonegg/trunk/gcc_revision_tested_with
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/gcc_revision_tested_with?rev=128883&r1=128882&r2=128883&view=diff
==============================================================================
--- dragonegg/trunk/gcc_revision_tested_with (original)
+++ dragonegg/trunk/gcc_revision_tested_with Tue Apr  5 05:56:02 2011
@@ -1 +1 @@
-168940
+171979



From baldrick at free.fr  Tue Apr  5 09:17:40 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 05 Apr 2011 16:17:40 +0200
Subject: [llvm-commits] [patch] Instcombine bug - transforms GEP/Bitcast
 on different address spaces
In-Reply-To: <6594DDFF12B03D4E89690887C248699402787A62CF@hasmsx504.ger.corp.intel.com>
References: <6594DDFF12B03D4E89690887C248699402787A62CF@hasmsx504.ger.corp.intel.com>
Message-ID: <4D9B2484.7050102@free.fr>

Hi Nadav,

> Index: test/Transforms/InstCombine/gep-addrspace.ll
> ===================================================================
> --- test/Transforms/InstCombine/gep-addrspace.ll	(revision 0)
> +++ test/Transforms/InstCombine/gep-addrspace.ll	(revision 0)
> @@ -0,0 +1,18 @@
> +; RUN: opt < %s -instcombine -S | FileCheck %s

piping to FileCheck is not needed.

> +
> +%myStruct = type { float, [3 x float], [4 x float], i32 }
> +
> +; make sure that we are not crashing when creating an illegal type
> +; CHECK:   @func

This CHECK line is pointless.

Otherwise it looks OK to me.

Ciao, Duncan.

From nadav.rotem at intel.com  Tue Apr  5 09:29:52 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Tue, 05 Apr 2011 14:29:52 -0000
Subject: [llvm-commits] [llvm] r128884 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstructionCombining.cpp
 test/Transforms/InstCombine/gep-addrspace.ll
Message-ID: <20110405142952.A548C2A6C12C@llvm.org>

Author: nadav
Date: Tue Apr  5 09:29:52 2011
New Revision: 128884

URL: http://llvm.org/viewvc/llvm-project?rev=128884&view=rev
Log:
InstCombine optimizes gep(bitcast(x)) even when the bitcasts casts away address
space info. We crash with an assert in this case. This change checks that the
address space of the bitcasted pointer is the same as the gep ptr.


Added:
    llvm/trunk/test/Transforms/InstCombine/gep-addrspace.ll
Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp

Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=128884&r1=128883&r2=128884&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Tue Apr  5 09:29:52 2011
@@ -849,22 +849,23 @@
         GetElementPtrInst::Create(Src->getOperand(0), Indices.begin(),
                                   Indices.end(), GEP.getName());
   }
-  
+
   // Handle gep(bitcast x) and gep(gep x, 0, 0, 0).
   Value *StrippedPtr = PtrOp->stripPointerCasts();
-  if (StrippedPtr != PtrOp) {
-    const PointerType *StrippedPtrTy =cast<PointerType>(StrippedPtr->getType());
+  const PointerType *StrippedPtrTy =cast<PointerType>(StrippedPtr->getType());
+  if (StrippedPtr != PtrOp &&
+    StrippedPtrTy->getAddressSpace() == GEP.getPointerAddressSpace()) {
 
     bool HasZeroPointerIndex = false;
     if (ConstantInt *C = dyn_cast<ConstantInt>(GEP.getOperand(1)))
       HasZeroPointerIndex = C->isZero();
-    
+
     // Transform: GEP (bitcast [10 x i8]* X to [0 x i8]*), i32 0, ...
     // into     : GEP [10 x i8]* X, i32 0, ...
     //
     // Likewise, transform: GEP (bitcast i8* X to [0 x i8]*), i32 0, ...
     //           into     : GEP i8* X, ...
-    // 
+    //
     // This occurs when the program declares an array extern like "int X[];"
     if (HasZeroPointerIndex) {
       const PointerType *CPTy = cast<PointerType>(PtrOp->getType());
@@ -975,7 +976,7 @@
       }
     }
   }
-  
+
   /// See if we can simplify:
   ///   X = bitcast A* to B*
   ///   Y = gep X, <...constant indices...>
@@ -983,12 +984,14 @@
   /// analysis of unions.  If "A" is also a bitcast, wait for A/X to be merged.
   if (BitCastInst *BCI = dyn_cast<BitCastInst>(PtrOp)) {
     if (TD &&
-        !isa<BitCastInst>(BCI->getOperand(0)) && GEP.hasAllConstantIndices()) {
+        !isa<BitCastInst>(BCI->getOperand(0)) && GEP.hasAllConstantIndices() &&
+        StrippedPtrTy->getAddressSpace() == GEP.getPointerAddressSpace()) {
+
       // Determine how much the GEP moves the pointer.  We are guaranteed to get
       // a constant back from EmitGEPOffset.
       ConstantInt *OffsetV = cast<ConstantInt>(EmitGEPOffset(&GEP));
       int64_t Offset = OffsetV->getSExtValue();
-      
+
       // If this GEP instruction doesn't move the pointer, just replace the GEP
       // with a bitcast of the real input to the dest type.
       if (Offset == 0) {

Added: llvm/trunk/test/Transforms/InstCombine/gep-addrspace.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/gep-addrspace.ll?rev=128884&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/gep-addrspace.ll (added)
+++ llvm/trunk/test/Transforms/InstCombine/gep-addrspace.ll Tue Apr  5 09:29:52 2011
@@ -0,0 +1,16 @@
+; RUN: opt < %s -instcombine -S
+
+%myStruct = type { float, [3 x float], [4 x float], i32 }
+
+; make sure that we are not crashing when creating an illegal type
+define void @func(%myStruct addrspace(1)* nocapture %p) nounwind {
+ST:
+  %A = getelementptr inbounds %myStruct addrspace(1)* %p, i64 0
+  %B = bitcast %myStruct addrspace(1)* %A to %myStruct*
+  %C = getelementptr inbounds %myStruct* %B, i32 0, i32 1
+  %D = getelementptr inbounds [3 x float]* %C, i32 0, i32 2
+  %E = load float* %D, align 4
+  %F = fsub float %E, undef
+  ret void
+}
+



From stoklund at 2pi.dk  Tue Apr  5 10:18:18 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 15:18:18 -0000
Subject: [llvm-commits] [llvm] r128886 - in /llvm/trunk:
 include/llvm/CodeGen/SlotIndexes.h lib/CodeGen/SplitKit.cpp
 lib/CodeGen/SplitKit.h
Message-ID: <20110405151818.D22052A6C12C@llvm.org>

Author: stoklund
Date: Tue Apr  5 10:18:18 2011
New Revision: 128886

URL: http://llvm.org/viewvc/llvm-project?rev=128886&view=rev
Log:
Use std::unique instead of a SmallPtrSet to ensure unique instructions in UseSlots.

This allows us to always keep the smaller slot for an instruction which is what
we want when a register has early clobber defines.

Drop the UsingInstrs set and the UsingBlocks map. They are no longer needed.

Modified:
    llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
    llvm/trunk/lib/CodeGen/SplitKit.cpp
    llvm/trunk/lib/CodeGen/SplitKit.h

Modified: llvm/trunk/include/llvm/CodeGen/SlotIndexes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SlotIndexes.h?rev=128886&r1=128885&r2=128886&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/SlotIndexes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/SlotIndexes.h Tue Apr  5 10:18:18 2011
@@ -178,6 +178,11 @@
       return getIndex() >= other.getIndex();
     }
 
+    /// isSameInstr - Return true if A and B refer to the same instruction.
+    static bool isSameInstr(SlotIndex A, SlotIndex B) {
+      return A.lie.getPointer() == B.lie.getPointer();
+    }
+
     /// Return the distance from this index to the given one.
     int distance(SlotIndex other) const {
       return other.getIndex() - getIndex();

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=128886&r1=128885&r2=128886&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Apr  5 10:18:18 2011
@@ -21,7 +21,6 @@
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetInstrInfo.h"
@@ -29,10 +28,6 @@
 
 using namespace llvm;
 
-static cl::opt<bool>
-AllowSplit("spiller-splits-edges",
-           cl::desc("Allow critical edge splitting during spilling"));
-
 STATISTIC(NumFinished, "Number of splits finished");
 STATISTIC(NumSimple,   "Number of splits that were simple");
 
@@ -53,8 +48,6 @@
 
 void SplitAnalysis::clear() {
   UseSlots.clear();
-  UsingInstrs.clear();
-  UsingBlocks.clear();
   LiveBlocks.clear();
   CurLI = 0;
 }
@@ -96,21 +89,31 @@
 
 /// analyzeUses - Count instructions, basic blocks, and loops using CurLI.
 void SplitAnalysis::analyzeUses() {
+  assert(UseSlots.empty() && "Call clear first");
+
+  // First get all the defs from the interval values. This provides the correct
+  // slots for early clobbers.
+  for (LiveInterval::const_vni_iterator I = CurLI->vni_begin(),
+       E = CurLI->vni_end(); I != E; ++I)
+    if (!(*I)->isPHIDef() && !(*I)->isUnused())
+      UseSlots.push_back((*I)->def);
+
+  // Get use slots form the use-def chain.
   const MachineRegisterInfo &MRI = MF.getRegInfo();
-  for (MachineRegisterInfo::reg_iterator I = MRI.reg_begin(CurLI->reg),
-       E = MRI.reg_end(); I != E; ++I) {
-    MachineOperand &MO = I.getOperand();
-    if (MO.isUse() && MO.isUndef())
-      continue;
-    MachineInstr *MI = MO.getParent();
-    if (MI->isDebugValue() || !UsingInstrs.insert(MI))
-      continue;
-    UseSlots.push_back(LIS.getInstructionIndex(MI).getDefIndex());
-    MachineBasicBlock *MBB = MI->getParent();
-    UsingBlocks[MBB]++;
-  }
+  for (MachineRegisterInfo::use_nodbg_iterator
+       I = MRI.use_nodbg_begin(CurLI->reg), E = MRI.use_nodbg_end(); I != E;
+       ++I)
+    if (!I.getOperand().isUndef())
+      UseSlots.push_back(LIS.getInstructionIndex(&*I).getDefIndex());
+
   array_pod_sort(UseSlots.begin(), UseSlots.end());
 
+  // Remove duplicates, keeping the smaller slot for each instruction.
+  // That is what we want for early clobbers.
+  UseSlots.erase(std::unique(UseSlots.begin(), UseSlots.end(),
+                             SlotIndex::isSameInstr),
+                 UseSlots.end());
+
   // Compute per-live block info.
   if (!calcLiveBlockInfo()) {
     // FIXME: calcLiveBlockInfo found inconsistencies in the live range.
@@ -125,8 +128,7 @@
   }
 
   DEBUG(dbgs() << "Analyze counted "
-               << UsingInstrs.size() << " instrs, "
-               << UsingBlocks.size() << " blocks, "
+               << UseSlots.size() << " instrs, "
                << LiveBlocks.size() << " spanned.\n");
 }
 
@@ -157,8 +159,8 @@
       BI.Def = LVI->start;
 
     // Find the first and last uses in the block.
-    BI.Uses = hasUses(MFI);
-    if (BI.Uses && UseI != UseE) {
+    BI.Uses = UseI != UseE && *UseI < Stop;
+    if (BI.Uses) {
       BI.FirstUse = *UseI;
       assert(BI.FirstUse >= Start);
       do ++UseI;
@@ -224,15 +226,6 @@
   return I != Orig.begin() && (--I)->end == Idx;
 }
 
-void SplitAnalysis::print(const BlockPtrSet &B, raw_ostream &OS) const {
-  for (BlockPtrSet::const_iterator I = B.begin(), E = B.end(); I != E; ++I) {
-    unsigned count = UsingBlocks.lookup(*I);
-    OS << " BB#" << (*I)->getNumber();
-    if (count)
-      OS << '(' << count << ')';
-  }
-}
-
 void SplitAnalysis::analyze(const LiveInterval *li) {
   clear();
   CurLI = li;
@@ -918,12 +911,7 @@
   // Add blocks with multiple uses.
   for (unsigned i = 0, e = LiveBlocks.size(); i != e; ++i) {
     const BlockInfo &BI = LiveBlocks[i];
-    if (!BI.Uses)
-      continue;
-    unsigned Instrs = UsingBlocks.lookup(BI.MBB);
-    if (Instrs <= 1)
-      continue;
-    if (Instrs == 2 && BI.LiveIn && BI.LiveOut && !BI.LiveThrough)
+    if (!BI.Uses || BI.FirstUse == BI.LastUse)
       continue;
     Blocks.insert(BI.MBB);
   }

Modified: llvm/trunk/lib/CodeGen/SplitKit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=128886&r1=128885&r2=128886&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.h (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.h Tue Apr  5 10:18:18 2011
@@ -50,17 +50,9 @@
   const MachineLoopInfo &Loops;
   const TargetInstrInfo &TII;
 
-  // Instructions using the the current register.
-  typedef SmallPtrSet<const MachineInstr*, 16> InstrPtrSet;
-  InstrPtrSet UsingInstrs;
-
   // Sorted slot indexes of using instructions.
   SmallVector<SlotIndex, 8> UseSlots;
 
-  // The number of instructions using CurLI in each basic block.
-  typedef DenseMap<const MachineBasicBlock*, unsigned> BlockCountMap;
-  BlockCountMap UsingBlocks;
-
   /// Additional information about basic blocks where the current variable is
   /// live. Such a block will look like one of these templates:
   ///
@@ -130,11 +122,6 @@
     return computeLastSplitPoint(Num);
   }
 
-  /// hasUses - Return true if MBB has any uses of CurLI.
-  bool hasUses(const MachineBasicBlock *MBB) const {
-    return UsingBlocks.lookup(MBB);
-  }
-
   /// isOriginalEndpoint - Return true if the original live range was killed or
   /// (re-)defined at Idx. Idx should be the 'def' slot for a normal kill/def,
   /// and 'use' for an early-clobber def.
@@ -144,9 +131,6 @@
 
   typedef SmallPtrSet<const MachineBasicBlock*, 16> BlockPtrSet;
 
-  // Print a set of blocks with use counts.
-  void print(const BlockPtrSet&, raw_ostream&) const;
-
   /// getMultiUseBlocks - Add basic blocks to Blocks that may benefit from
   /// having CurLI split to a new live interval. Return true if Blocks can be
   /// passed to SplitEditor::splitSingleBlocks.



From rafael.espindola at gmail.com  Tue Apr  5 10:51:32 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 05 Apr 2011 15:51:32 -0000
Subject: [llvm-commits] [llvm] r128887 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/X86/visibility.ll
Message-ID: <20110405155132.B34D92A6C12C@llvm.org>

Author: rafael
Date: Tue Apr  5 10:51:32 2011
New Revision: 128887

URL: http://llvm.org/viewvc/llvm-project?rev=128887&view=rev
Log:
Print visibility info for external variables.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/test/CodeGen/X86/visibility.ll

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=128887&r1=128886&r2=128887&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Apr  5 10:51:32 2011
@@ -253,22 +253,24 @@
 
 /// EmitGlobalVariable - Emit the specified global variable to the .s file.
 void AsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
-  if (!GV->hasInitializer())   // External globals require no code.
-    return;
-
-  // Check to see if this is a special global used by LLVM, if so, emit it.
-  if (EmitSpecialLLVMGlobal(GV))
-    return;
+  if (GV->hasInitializer()) {
+    // Check to see if this is a special global used by LLVM, if so, emit it.
+    if (EmitSpecialLLVMGlobal(GV))
+      return;
 
-  if (isVerbose()) {
-    WriteAsOperand(OutStreamer.GetCommentOS(), GV,
-                   /*PrintType=*/false, GV->getParent());
-    OutStreamer.GetCommentOS() << '\n';
+    if (isVerbose()) {
+      WriteAsOperand(OutStreamer.GetCommentOS(), GV,
+                     /*PrintType=*/false, GV->getParent());
+      OutStreamer.GetCommentOS() << '\n';
+    }
   }
 
   MCSymbol *GVSym = Mang->getSymbol(GV);
   EmitVisibility(GVSym, GV->getVisibility());
 
+  if (!GV->hasInitializer())   // External globals require no extra code.
+    return;
+
   if (MAI->hasDotTypeDotSizeDirective())
     OutStreamer.EmitSymbolAttribute(GVSym, MCSA_ELF_TypeObject);
 

Modified: llvm/trunk/test/CodeGen/X86/visibility.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/visibility.ll?rev=128887&r1=128886&r2=128887&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/visibility.ll (original)
+++ llvm/trunk/test/CodeGen/X86/visibility.ll Tue Apr  5 10:51:32 2011
@@ -1,11 +1,14 @@
 ; RUN: llc -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s
 
+ at zed = external hidden constant i32
+
 define hidden void @foo() nounwind {
 entry:
-  call void @bar()
+  call void @bar(i32* @zed)
   ret void
 }
 
-declare hidden void @bar()
+declare hidden void @bar(i32*)
 
+;CHECK: .hidden	zed
 ;CHECK: .hidden	bar



From stoklund at 2pi.dk  Tue Apr  5 11:53:50 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 16:53:50 -0000
Subject: [llvm-commits] [llvm] r128888 - in /llvm/trunk:
 lib/CodeGen/MachineInstr.cpp test/CodeGen/X86/coalescer-cross.ll
Message-ID: <20110405165350.B9E8C2A6C12C@llvm.org>

Author: stoklund
Date: Tue Apr  5 11:53:50 2011
New Revision: 128888

URL: http://llvm.org/viewvc/llvm-project?rev=128888&view=rev
Log:
Ensure all defs referring to a virtual register are marked dead by addRegisterDead().

There can be multiple defs for a single virtual register when they are defining
sub-registers.

The missing <dead> flag was stopping the inline spiller from eliminating dead
code after rematerialization.

Modified:
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/test/CodeGen/X86/coalescer-cross.ll

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=128888&r1=128887&r2=128888&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Apr  5 11:53:50 2011
@@ -1543,13 +1543,8 @@
       continue;
 
     if (Reg == IncomingReg) {
-      if (!Found) {
-        if (MO.isDead())
-          // The register is already marked dead.
-          return true;
-        MO.setIsDead();
-        Found = true;
-      }
+      MO.setIsDead();
+      Found = true;
     } else if (hasAliases && MO.isDead() &&
                TargetRegisterInfo::isPhysicalRegister(Reg)) {
       // There exists a super-register that's marked dead.

Modified: llvm/trunk/test/CodeGen/X86/coalescer-cross.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/coalescer-cross.ll?rev=128888&r1=128887&r2=128888&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/coalescer-cross.ll (original)
+++ llvm/trunk/test/CodeGen/X86/coalescer-cross.ll Tue Apr  5 11:53:50 2011
@@ -1,6 +1,10 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin10 | not grep movaps
+; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin10 -regalloc=basic | FileCheck %s
 ; rdar://6509240
 
+; CHECK: os_clock
+; CHECK-NOT: movaps
+
 	type { %struct.TValue }		; type %0
 	type { %struct.L_Umaxalign, i32, %struct.Node* }		; type %1
 	%struct.CallInfo = type { %struct.TValue*, %struct.TValue*, %struct.TValue*, i32*, i32, i32 }



From ofv at wanadoo.es  Tue Apr  5 12:02:48 2011
From: ofv at wanadoo.es (Oscar Fuentes)
Date: Tue, 05 Apr 2011 17:02:48 -0000
Subject: [llvm-commits] [llvm] r128889 - in /llvm/trunk:
 cmake/modules/AddLLVM.cmake cmake/modules/CMakeLists.txt
 cmake/modules/LLVM-Config.cmake cmake/modules/LLVM.cmake
 cmake/modules/LLVMConfig.cmake tools/llvm-config/CMakeLists.txt
Message-ID: <20110405170248.483032A6C12C@llvm.org>

Author: ofv
Date: Tue Apr  5 12:02:48 2011
New Revision: 128889

URL: http://llvm.org/viewvc/llvm-project?rev=128889&view=rev
Log:
Rename LLVMConfig.cmake to LLVM-Config.cmake. The *Config.cmake naming
scheme is used by the functionality related to find_package.

Added:
    llvm/trunk/cmake/modules/LLVM-Config.cmake
      - copied, changed from r128887, llvm/trunk/cmake/modules/LLVMConfig.cmake
Removed:
    llvm/trunk/cmake/modules/LLVMConfig.cmake
Modified:
    llvm/trunk/cmake/modules/AddLLVM.cmake
    llvm/trunk/cmake/modules/CMakeLists.txt
    llvm/trunk/cmake/modules/LLVM.cmake
    llvm/trunk/tools/llvm-config/CMakeLists.txt

Modified: llvm/trunk/cmake/modules/AddLLVM.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/AddLLVM.cmake?rev=128889&r1=128888&r2=128889&view=diff
==============================================================================
--- llvm/trunk/cmake/modules/AddLLVM.cmake (original)
+++ llvm/trunk/cmake/modules/AddLLVM.cmake Tue Apr  5 12:02:48 2011
@@ -1,5 +1,5 @@
 include(LLVMProcessSources)
-include(LLVMConfig)
+include(LLVM-Config)
 
 macro(add_llvm_library name)
   llvm_process_sources( ALL_FILES ${ARGN} )

Modified: llvm/trunk/cmake/modules/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/CMakeLists.txt?rev=128889&r1=128888&r2=128889&view=diff
==============================================================================
--- llvm/trunk/cmake/modules/CMakeLists.txt (original)
+++ llvm/trunk/cmake/modules/CMakeLists.txt Tue Apr  5 12:02:48 2011
@@ -9,7 +9,7 @@
 
 install(FILES
   ${llvm_cmake_builddir}/LLVM.cmake
-  LLVMConfig.cmake
+  LLVM-Config.cmake
   LLVMLibDeps.cmake
   DESTINATION share/llvm/cmake)
 
@@ -18,7 +18,7 @@
   FILES_MATCHING PATTERN *.cmake
   PATTERN .svn EXCLUDE
   PATTERN LLVM.cmake EXCLUDE
-  PATTERN LLVMConfig.cmake EXCLUDE
+  PATTERN LLVM-Config.cmake EXCLUDE
   PATTERN LLVMLibDeps.cmake EXCLUDE
   PATTERN FindBison.cmake EXCLUDE
   PATTERN GetTargetTriple.cmake EXCLUDE
@@ -27,6 +27,6 @@
 
 install(FILES
   ${llvm_cmake_builddir}/LLVM.cmake
-  LLVMConfig.cmake
+  LLVM-Config.cmake
   LLVMLibDeps.cmake
   DESTINATION share/llvm/cmake)

Copied: llvm/trunk/cmake/modules/LLVM-Config.cmake (from r128887, llvm/trunk/cmake/modules/LLVMConfig.cmake)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVM-Config.cmake?p2=llvm/trunk/cmake/modules/LLVM-Config.cmake&p1=llvm/trunk/cmake/modules/LLVMConfig.cmake&r1=128887&r2=128889&rev=128889&view=diff
==============================================================================
    (empty)

Modified: llvm/trunk/cmake/modules/LLVM.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVM.cmake?rev=128889&r1=128888&r2=128889&view=diff
==============================================================================
--- llvm/trunk/cmake/modules/LLVM.cmake (original)
+++ llvm/trunk/cmake/modules/LLVM.cmake Tue Apr  5 12:02:48 2011
@@ -28,13 +28,13 @@
 # We try to include using the current setting of CMAKE_MODULE_PATH,
 # which suppossedly was filled by the user with the directory where
 # this file was installed:
-include( LLVMConfig OPTIONAL RESULT_VARIABLE LLVMCONFIG_INCLUDED )
+include( LLVM-Config OPTIONAL RESULT_VARIABLE LLVMCONFIG_INCLUDED )
 
 # If failed, we assume that this is an un-installed build:
 if( NOT LLVMCONFIG_INCLUDED )
   set(CMAKE_MODULE_PATH
     ${CMAKE_MODULE_PATH}
     "@LLVM_SOURCE_DIR@/cmake/modules")
-  include( LLVMConfig )
+  include( LLVM-Config )
 endif()
 

Removed: llvm/trunk/cmake/modules/LLVMConfig.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMConfig.cmake?rev=128888&view=auto
==============================================================================
--- llvm/trunk/cmake/modules/LLVMConfig.cmake (original)
+++ llvm/trunk/cmake/modules/LLVMConfig.cmake (removed)
@@ -1,203 +0,0 @@
-function(get_system_libs return_var)
-  # Returns in `return_var' a list of system libraries used by LLVM.
-  if( NOT MSVC )
-    if( MINGW )
-      set(system_libs ${system_libs} imagehlp psapi)
-    elseif( CMAKE_HOST_UNIX )
-      if( HAVE_LIBDL )
-	set(system_libs ${system_libs} ${CMAKE_DL_LIBS})
-      endif()
-      if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD )
-	set(system_libs ${system_libs} pthread)
-      endif()
-    endif( MINGW )
-  endif( NOT MSVC )
-  set(${return_var} ${system_libs} PARENT_SCOPE)
-endfunction(get_system_libs)
-
-
-function(link_system_libs target)
-  get_system_libs(llvm_system_libs)
-  target_link_libraries(${target} ${llvm_system_libs})
-endfunction(link_system_libs)
-
-
-function(is_llvm_target_library library return_var)
-  # Sets variable `return_var' to ON if `library' corresponds to a
-  # LLVM supported target. To OFF if it doesn't.
-  set(${return_var} OFF PARENT_SCOPE)
-  string(TOUPPER "${library}" capitalized_lib)
-  string(TOUPPER "${LLVM_ALL_TARGETS}" targets)
-  foreach(t ${targets})
-    if( capitalized_lib STREQUAL t OR
-	capitalized_lib STREQUAL "LLVM${t}" OR
-	capitalized_lib STREQUAL "LLVM${t}CODEGEN" OR
-	capitalized_lib STREQUAL "LLVM${t}ASMPARSER" OR
-	capitalized_lib STREQUAL "LLVM${t}ASMPRINTER" OR
-	capitalized_lib STREQUAL "LLVM${t}DISASSEMBLER" OR
-	capitalized_lib STREQUAL "LLVM${t}INFO" )
-      set(${return_var} ON PARENT_SCOPE)
-      break()
-    endif()
-  endforeach()
-endfunction(is_llvm_target_library)
-
-
-macro(llvm_config executable)
-  explicit_llvm_config(${executable} ${ARGN})
-endmacro(llvm_config)
-
-
-function(explicit_llvm_config executable)
-  set( link_components ${ARGN} )
-
-  explicit_map_components_to_libraries(LIBRARIES ${link_components})
-  target_link_libraries(${executable} ${LIBRARIES})
-endfunction(explicit_llvm_config)
-
-
-# This is a variant intended for the final user:
-function(llvm_map_components_to_libraries OUT_VAR)
-  explicit_map_components_to_libraries(result ${ARGN})
-  get_system_libs(sys_result)
-  set( ${OUT_VAR} ${result} ${sys_result} PARENT_SCOPE )
-endfunction(llvm_map_components_to_libraries)
-
-
-function(explicit_map_components_to_libraries out_libs)
-  set( link_components ${ARGN} )
-  get_property(llvm_libs GLOBAL PROPERTY LLVM_LIBS)
-  string(TOUPPER "${llvm_libs}" capitalized_libs)
-
-  # Expand some keywords:
-  list(FIND LLVM_TARGETS_TO_BUILD "${LLVM_NATIVE_ARCH}" have_native_backend)
-  list(FIND link_components "engine" engine_required)
-  if( NOT engine_required EQUAL -1 )
-    list(FIND LLVM_TARGETS_WITH_JIT "${LLVM_NATIVE_ARCH}" have_jit)
-    if( NOT have_native_backend EQUAL -1 AND NOT have_jit EQUAL -1 )
-      list(APPEND link_components "jit")
-      list(APPEND link_components "native")
-    else()
-      list(APPEND link_components "interpreter")
-    endif()
-  endif()
-  list(FIND link_components "native" native_required)
-  if( NOT native_required EQUAL -1 )
-    if( NOT have_native_backend EQUAL -1 )
-      list(APPEND link_components ${LLVM_NATIVE_ARCH})
-    endif()
-  endif()
-
-  # Translate symbolic component names to real libraries:
-  foreach(c ${link_components})
-    # add codegen, asmprinter, asmparser, disassembler
-    list(FIND LLVM_TARGETS_TO_BUILD ${c} idx)
-    if( NOT idx LESS 0 )
-      list(FIND llvm_libs "LLVM${c}CodeGen" idx)
-      if( NOT idx LESS 0 )
-	list(APPEND expanded_components "LLVM${c}CodeGen")
-      else()
-	list(FIND llvm_libs "LLVM${c}" idx)
-	if( NOT idx LESS 0 )
-	  list(APPEND expanded_components "LLVM${c}")
-	else()
-	  message(FATAL_ERROR "Target ${c} is not in the set of libraries.")
-	endif()
-      endif()
-      list(FIND llvm_libs "LLVM${c}AsmPrinter" asmidx)
-      if( NOT asmidx LESS 0 )
-        list(APPEND expanded_components "LLVM${c}AsmPrinter")
-      endif()
-      list(FIND llvm_libs "LLVM${c}AsmParser" asmidx)
-      if( NOT asmidx LESS 0 )
-        list(APPEND expanded_components "LLVM${c}AsmParser")
-      endif()
-      list(FIND llvm_libs "LLVM${c}Info" asmidx)
-      if( NOT asmidx LESS 0 )
-        list(APPEND expanded_components "LLVM${c}Info")
-      endif()
-      list(FIND llvm_libs "LLVM${c}Disassembler" asmidx)
-      if( NOT asmidx LESS 0 )
-        list(APPEND expanded_components "LLVM${c}Disassembler")
-      endif()
-    elseif( c STREQUAL "native" )
-      # already processed
-    elseif( c STREQUAL "nativecodegen" )
-      list(APPEND expanded_components "LLVM${LLVM_NATIVE_ARCH}CodeGen")
-    elseif( c STREQUAL "backend" )
-      # same case as in `native'.
-    elseif( c STREQUAL "engine" )
-      # already processed
-    elseif( c STREQUAL "all" )
-      list(APPEND expanded_components ${llvm_libs})
-    else( NOT idx LESS 0 )
-      # Canonize the component name:
-      string(TOUPPER "${c}" capitalized)
-      list(FIND capitalized_libs LLVM${capitalized} lib_idx)
-      if( lib_idx LESS 0 )
-	# The component is unkown. Maybe is an ommitted target?
-	is_llvm_target_library(${c} iltl_result)
-	if( NOT iltl_result )
-	  message(FATAL_ERROR "Library `${c}' not found in list of llvm libraries.")
-	endif()
-      else( lib_idx LESS 0 )
-	list(GET llvm_libs ${lib_idx} canonical_lib)
-	list(APPEND expanded_components ${canonical_lib})
-      endif( lib_idx LESS 0 )
-    endif( NOT idx LESS 0 )
-  endforeach(c)
-  # Expand dependencies while topologically sorting the list of libraries:
-  list(LENGTH expanded_components lst_size)
-  set(cursor 0)
-  set(processed)
-  while( cursor LESS lst_size )
-    list(GET expanded_components ${cursor} lib)
-    list(APPEND expanded_components ${MSVC_LIB_DEPS_${lib}})
-    # Remove duplicates at the front:
-    list(REVERSE expanded_components)
-    list(REMOVE_DUPLICATES expanded_components)
-    list(REVERSE expanded_components)
-    list(APPEND processed ${lib})
-    # Find the maximum index that doesn't have to be re-processed:
-    while(NOT "${expanded_components}" MATCHES "^${processed}.*" )
-      list(REMOVE_AT processed -1)
-    endwhile()
-    list(LENGTH processed cursor)
-    list(LENGTH expanded_components lst_size)
-  endwhile( cursor LESS lst_size )
-  # Return just the libraries included in this build:
-  set(result)
-  foreach(c ${expanded_components})
-    list(FIND llvm_libs ${c} lib_idx)
-    if( NOT lib_idx LESS 0 )
-      set(result ${result} ${c})
-    endif()
-  endforeach(c)
-  set(${out_libs} ${result} PARENT_SCOPE)
-endfunction(explicit_map_components_to_libraries)
-
-
-# The library dependency data is contained in the file
-# LLVMLibDeps.cmake on this directory. It is automatically generated
-# by tools/llvm-config/CMakeLists.txt when the build comprises all the
-# targets and we are on a environment Posix enough to build the
-# llvm-config script. This, in practice, just excludes MSVC.
-
-# When you remove or rename a library from the build, be sure to
-# remove its file from lib/ as well, or the GenLibDeps.pl script will
-# include it on its analysis!
-
-# The format generated by GenLibDeps.pl
-
-# LLVMARMAsmPrinter.o: LLVMARMCodeGen.o libLLVMAsmPrinter.a libLLVMCodeGen.a libLLVMCore.a libLLVMSupport.a libLLVMTarget.a
-
-# is translated to:
-
-# set(MSVC_LIB_DEPS_LLVMARMAsmPrinter LLVMARMCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMSupport LLVMTarget)
-
-# It is necessary to remove the `lib' prefix and the `.a'.
-
-# This 'sed' script should do the trick:
-# sed -e s'#\.a##g' -e 's#libLLVM#LLVM#g' -e 's#: # #' -e 's#\(.*\)#set(MSVC_LIB_DEPS_\1)#' ~/llvm/tools/llvm-config/LibDeps.txt
-
-include(LLVMLibDeps)

Modified: llvm/trunk/tools/llvm-config/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-config/CMakeLists.txt?rev=128889&r1=128888&r2=128889&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-config/CMakeLists.txt (original)
+++ llvm/trunk/tools/llvm-config/CMakeLists.txt Tue Apr  5 12:02:48 2011
@@ -142,7 +142,7 @@
 
 # Regeneration of library dependencies.
 
-# See the comments at the end of cmake/modules/LLVMConfig.cmake for
+# See the comments at the end of cmake/modules/LLVM-Config.cmake for
 # notes and guidelines.
 
 set(LLVMLibDeps ${LLVM_MAIN_SRC_DIR}/cmake/modules/LLVMLibDeps.cmake)



From clattner at apple.com  Tue Apr  5 12:11:01 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 05 Apr 2011 10:11:01 -0700
Subject: [llvm-commits] [PATCH] docs/ReleaseNotes.html: Please use
 proper *Heading* elements instead of classified div.
In-Reply-To: <BANLkTik-eNUpXP_ahaNOVa3X349tieZKwg@mail.gmail.com>
References: <BANLkTik-eNUpXP_ahaNOVa3X349tieZKwg@mail.gmail.com>
Message-ID: <4B9D9A41-EE99-4B4E-B054-51FAE437AA45@apple.com>

Sure, go for it!

-Chris

On Apr 5, 2011, at 2:29 AM, NAKAMURA Takumi wrote:

> It would be better to browse without stylesheet. (eg. on ViewVC)
> ---
> docs/ReleaseNotes.html |  122 ++++++++++++++++++++++++------------------------
> 1 files changed, 61 insertions(+), 61 deletions(-)
> <0001-docs-ReleaseNotes.html-Please-use-proper-Heading.patch.txt>_______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From stuart at apple.com  Tue Apr  5 12:16:21 2011
From: stuart at apple.com (Stuart Hastings)
Date: Tue, 05 Apr 2011 17:16:21 -0000
Subject: [llvm-commits] [llvm] r128891 -
	/llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll
Message-ID: <20110405171621.8A1A42A6C12C@llvm.org>

Author: stuart
Date: Tue Apr  5 12:16:21 2011
New Revision: 128891

URL: http://llvm.org/viewvc/llvm-project?rev=128891&view=rev
Log:
ARM doesn't support byval yet.  XFAIL this test until it does.

Modified:
    llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll

Modified: llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll?rev=128891&r1=128890&r2=128891&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/2010-11-04-BigByval.ll Tue Apr  5 12:16:21 2011
@@ -1,5 +1,6 @@
 ; RUN: llc < %s
 ; PR7170
+; XFAIL: arm
 
 %big = type [131072 x i8]
 



From gohman at apple.com  Tue Apr  5 12:26:30 2011
From: gohman at apple.com (Dan Gohman)
Date: Tue, 05 Apr 2011 10:26:30 -0700
Subject: [llvm-commits] [llvm] r128884 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstructionCombining.cpp
 test/Transforms/InstCombine/gep-addrspace.ll
In-Reply-To: <20110405142952.A548C2A6C12C@llvm.org>
References: <20110405142952.A548C2A6C12C@llvm.org>
Message-ID: <011C9916-CAA2-4F38-84BB-2E2AC1378B3C@apple.com>

On Apr 5, 2011, at 7:29 AM, Nadav Rotem wrote:
> 
> --- llvm/trunk/test/Transforms/InstCombine/gep-addrspace.ll (added)
> +++ llvm/trunk/test/Transforms/InstCombine/gep-addrspace.ll Tue Apr  5 09:29:52 2011
> @@ -0,0 +1,16 @@
> +; RUN: opt < %s -instcombine -S
> +
> +%myStruct = type { float, [3 x float], [4 x float], i32 }
> +
> +; make sure that we are not crashing when creating an illegal type
> +define void @func(%myStruct addrspace(1)* nocapture %p) nounwind {
> +ST:
> +  %A = getelementptr inbounds %myStruct addrspace(1)* %p, i64 0
> +  %B = bitcast %myStruct addrspace(1)* %A to %myStruct*
> +  %C = getelementptr inbounds %myStruct* %B, i32 0, i32 1
> +  %D = getelementptr inbounds [3 x float]* %C, i32 0, i32 2
> +  %E = load float* %D, align 4
> +  %F = fsub float %E, undef
> +  ret void
> +}

Hello,

This testcase passes without the fix.

Dan

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From resistor at mac.com  Tue Apr  5 12:24:25 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 05 Apr 2011 17:24:25 -0000
Subject: [llvm-commits] [llvm] r128892 - in /llvm/trunk/lib/Target/ARM:
 ARMExpandPseudoInsts.cpp ARMInstrInfo.td
Message-ID: <20110405172425.4B26D2A6C12C@llvm.org>

Author: resistor
Date: Tue Apr  5 12:24:25 2011
New Revision: 128892

URL: http://llvm.org/viewvc/llvm-project?rev=128892&view=rev
Log:
Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.

Modified:
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=128892&r1=128891&r2=128892&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Tue Apr  5 12:24:25 2011
@@ -55,6 +55,7 @@
     void ExpandVLD(MachineBasicBlock::iterator &MBBI);
     void ExpandVST(MachineBasicBlock::iterator &MBBI);
     void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
+    void ExpandSBitOp(MachineBasicBlock::iterator &MBBI);
     void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
                     unsigned Opc, bool IsExt, unsigned NumRegs);
     void ExpandMOV32BitImm(MachineBasicBlock &MBB,
@@ -629,6 +630,43 @@
   MI.eraseFromParent();
 }
 
+void ARMExpandPseudo::ExpandSBitOp(MachineBasicBlock::iterator &MBBI) {
+  MachineInstr &MI = *MBBI;
+  MachineBasicBlock &MBB = *MI.getParent();
+  unsigned OldOpc = MI.getOpcode();
+  unsigned Opc = 0;
+  switch (OldOpc) {
+    case ARM::ADCSSrr:
+      Opc = ARM::ADCrr;
+      break;
+    case ARM::ADCSSri:
+      Opc = ARM::ADCri;
+      break;
+    case ARM::ADCSSrs:
+      Opc = ARM::ADCrs;
+      break;
+    case ARM::SBCSSrr:
+      Opc = ARM::SBCrr;
+      break;
+    case ARM::SBCSSri:
+      Opc = ARM::SBCri;
+      break;
+    case ARM::SBCSSrs:
+      Opc = ARM::SBCrs;
+      break;
+    default:
+      llvm_unreachable("Unknown opcode?");
+  }
+
+  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
+  MIB.addOperand(MachineOperand::CreateImm(0)); // Predicate
+  MIB.addOperand(MachineOperand::CreateImm(0)); // S bit
+  for (unsigned i = 0; i < MI.getNumOperands(); ++i)
+    MIB.addOperand(MI.getOperand(i));
+  TransferImpOps(MI, MIB, MIB);
+  MI.eraseFromParent();
+}
+
 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator &MBBI) {
   MachineInstr &MI = *MBBI;
@@ -941,6 +979,15 @@
       ExpandMOV32BitImm(MBB, MBBI);
       return true;
 
+    case ARM::ADCSSri:
+    case ARM::ADCSSrr:
+    case ARM::ADCSSrs:
+    case ARM::SBCSSri:
+    case ARM::SBCSSrr:
+    case ARM::SBCSSrs:
+      ExpandSBitOp(MBBI);
+      return true;
+
     case ARM::VMOVQQ: {
       unsigned DstReg = MI.getOperand(0).getReg();
       bool DstIsDead = MI.getOperand(0).isDead();

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128892&r1=128891&r2=128892&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Apr  5 12:24:25 2011
@@ -938,50 +938,18 @@
 let isCodeGenOnly = 1, Defs = [CPSR] in {
 multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
                              bit Commutable = 0> {
-  def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
-                DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
+  def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
+                Size4Bytes, IIC_iALUi,
                [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
-               Requires<[IsARM]> {
-    bits<4> Rd;
-    bits<4> Rn;
-    bits<12> imm;
-    let Inst{31-27} = 0b1110; // non-predicated
-    let Inst{15-12} = Rd;
-    let Inst{19-16} = Rn;
-    let Inst{11-0} = imm;
-    let Inst{20} = 1;
-    let Inst{25} = 1;
-  }
-  def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
-                DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
+               Requires<[IsARM]>;
+  def Srr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
+                Size4Bytes, IIC_iALUr,
                [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
-               Requires<[IsARM]> {
-    bits<4> Rd;
-    bits<4> Rn;
-    bits<4> Rm;
-    let Inst{31-27} = 0b1110; // non-predicated
-    let Inst{11-4} = 0b00000000;
-    let isCommutable = Commutable;
-    let Inst{3-0} = Rm;
-    let Inst{15-12} = Rd;
-    let Inst{19-16} = Rn;
-    let Inst{20} = 1;
-    let Inst{25} = 0;
-  }
-  def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
-                DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
+               Requires<[IsARM]>;
+  def Srs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+                Size4Bytes, IIC_iALUsr,
                [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
-               Requires<[IsARM]> {
-    bits<4> Rd;
-    bits<4> Rn;
-    bits<12> shift;
-    let Inst{31-27} = 0b1110; // non-predicated
-    let Inst{11-0} = shift;
-    let Inst{15-12} = Rd;
-    let Inst{19-16} = Rn;
-    let Inst{20} = 1;
-    let Inst{25} = 0;
-  }
+               Requires<[IsARM]>;
 }
 }
 }



From johnny.chen at apple.com  Tue Apr  5 12:43:10 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 17:43:10 -0000
Subject: [llvm-commits] [llvm] r128895 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
 test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt
Message-ID: <20110405174310.904252A6C12C@llvm.org>

Author: johnny
Date: Tue Apr  5 12:43:10 2011
New Revision: 128895

URL: http://llvm.org/viewvc/llvm-project?rev=128895&view=rev
Log:
Check for invalid register encodings for UMAAL and friends where:
    if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
    if dHi == dLo then UNPREDICTABLE;

rdar://problem/9230202

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128895&r1=128894&r2=128895&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Apr  5 12:43:10 2011
@@ -497,14 +497,57 @@
   return false;
 }
 
+// A8.6.94 MLA
+// if d == 15 || n == 15 || m == 15 || a == 15 then UNPREDICTABLE;
+//
+// A8.6.105 MUL
+// if d == 15 || n == 15 || m == 15 then UNPREDICTABLE;
+//
+// A8.6.246 UMULL
+// if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
+// if dHi == dLo then UNPREDICTABLE;
+static bool BadRegsMulFrm(unsigned Opcode, uint32_t insn) {
+  unsigned R19_16 = slice(insn, 19, 16);
+  unsigned R15_12 = slice(insn, 15, 12);
+  unsigned R11_8  = slice(insn, 11, 8);
+  unsigned R3_0   = slice(insn, 3, 0);
+  switch (Opcode) {
+  default:
+    // Did we miss an opcode?
+    assert(0 && "Unexpected opcode!");
+    return false;
+  case ARM::MLA:     case ARM::MLS:     case ARM::SMLABB:  case ARM::SMLABT:
+  case ARM::SMLATB:  case ARM::SMLATT:  case ARM::SMLAWB:  case ARM::SMLAWT:
+  case ARM::SMMLA:   case ARM::SMMLS:   case ARM::SMLSD:   case ARM::SMLSDX:
+    if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15)
+      return true;
+    return false;
+  case ARM::MUL:     case ARM::SMMUL:   case ARM::SMULBB:  case ARM::SMULBT:
+  case ARM::SMULTB:  case ARM::SMULTT:  case ARM::SMULWB:  case ARM::SMULWT:
+    if (R19_16 == 15 || R11_8 == 15 || R3_0 == 15)
+      return true;
+    return false;
+  case ARM::SMLAL:   case ARM::SMULL:   case ARM::UMAAL:   case ARM::UMLAL:
+  case ARM::UMULL:   case ARM::SMLALBB: case ARM::SMLALBT: case ARM::SMLALTB:
+  case ARM::SMLALTT: case ARM::SMLSLD:
+    if (R19_16 == 15 || R15_12 == 15 || R11_8 == 15 || R3_0 == 15)
+      return true;
+    if (R19_16 == R15_12)
+      return true;
+    return false;;
+  }
+}
+
 // Multiply Instructions.
-// MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS:
+// MLA, MLS, SMLABB, SMLABT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMMLA, SMMLS,
+// SMLSD, SMLSDX:
 //     Rd{19-16} Rn{3-0} Rm{11-8} Ra{15-12}
 //
 // MUL, SMMUL, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT:
 //     Rd{19-16} Rn{3-0} Rm{11-8}
 //
-// SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT:
+// SMLAL, SMULL, UMAAL, UMLAL, UMULL, SMLALBB, SMLALBT, SMLALTB, SMLALTT,
+// SMLSLD
 //     RdLo{15-12} RdHi{19-16} Rn{3-0} Rm{11-8}
 //
 // The mapping of the multiply registers to the "regular" ARM registers, where
@@ -531,6 +574,10 @@
          && OpInfo[2].RegClass == ARM::GPRRegClassID
          && "Expect three register operands");
 
+  // Sanity check for the register encodings.
+  if (BadRegsMulFrm(Opcode, insn))
+    return false;
+
   // Instructions with two destination registers have RdLo{15-12} first.
   if (NumDefs == 2) {
     assert(NumOps >= 4 && OpInfo[3].RegClass == ARM::GPRRegClassID &&

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt?rev=128895&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-UMAAL-arm.txt Tue Apr  5 12:43:10 2011
@@ -0,0 +1,11 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=419 Name=UMAAL Format=ARM_FORMAT_MULFRM(1)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 0: 0: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 1: 1| 1: 1: 1: 1| 1: 0: 0: 1| 1: 0: 0: 0|
+# -------------------------------------------------------------------------------------------------
+#
+# A8.6.244 UMAAL
+# if dLo == 15 || dHi == 15 || n == 15 || m == 15 then UNPREDICTABLE;
+0x98 0xbf 0x4f 0xf0 



From johnny.chen at apple.com  Tue Apr  5 13:02:46 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 18:02:46 -0000
Subject: [llvm-commits] [llvm] r128897 - in /llvm/trunk:
 lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
 test/MC/ARM/simple-encoding.ll test/MC/Disassembler/ARM/arm-tests.txt
Message-ID: <20110405180246.D92582A6C12C@llvm.org>

Author: johnny
Date: Tue Apr  5 13:02:46 2011
New Revision: 128897

URL: http://llvm.org/viewvc/llvm-project?rev=128897&view=rev
Log:
Constants with multiple encodings (ARM):
An alternative syntax is available for a modified immediate constant that permits the programmer to specify
the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:

    <byte> is the numeric value of abcdefgh, in the range 0-255
    <rot> is twice the numeric value of rotation, an even number in the range 0-30.

Modified:
    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
    llvm/trunk/test/MC/ARM/simple-encoding.ll
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=128897&r1=128896&r2=128897&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Apr  5 13:02:46 2011
@@ -136,9 +136,10 @@
   unsigned Rot = ARM_AM::getSOImmValRot(V);
 
   // Print low-level immediate formation info, per
-  // A5.1.3: "Data-processing operands - Immediate".
+  // A5.2.3: Data-processing (immediate), and
+  // A5.2.4: Modified immediate constants in ARM instructions
   if (Rot) {
-    O << "#" << Imm << ", " << Rot;
+    O << "#" << Imm << ", #" << Rot;
     // Pretty printed version.
     if (CommentStream)
       *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";

Modified: llvm/trunk/test/MC/ARM/simple-encoding.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-encoding.ll?rev=128897&r1=128896&r2=128897&view=diff
==============================================================================
--- llvm/trunk/test/MC/ARM/simple-encoding.ll (original)
+++ llvm/trunk/test/MC/ARM/simple-encoding.ll Tue Apr  5 13:02:46 2011
@@ -39,7 +39,7 @@
 
 define i32 @f4(i32 %a, i32 %b) {
 ; CHECK: f4
-; CHECK: add r0, r0, #254, 28         @ encoding: [0xfe,0x0e,0x80,0xe2]
+; CHECK: add r0, r0, #254, #28        @ encoding: [0xfe,0x0e,0x80,0xe2]
 ; CHECK:                              @ 4064
 ; CHECK: bx lr                        @ encoding: [0x1e,0xff,0x2f,0xe1]
   %add = add nsw i32 %a, 4064
@@ -118,7 +118,7 @@
 define i64 @f13() {
 ; CHECK: f13:
 ; CHECK: mvn r0, #0                   @ encoding: [0x00,0x00,0xe0,0xe3]
-; CHECK: mvn r1, #2, 2                @ encoding: [0x02,0x11,0xe0,0xe3]
+; CHECK: mvn r1, #2, #2               @ encoding: [0x02,0x11,0xe0,0xe3]
         ret i64 9223372036854775807
 }
 
@@ -229,7 +229,7 @@
 
 define void @f24(i32 %a) {
 ; CHECK: f24
-; CHECK: cmp r0, #1, 16               @ encoding: [0x01,0x08,0x50,0xe3]
+; CHECK: cmp r0, #1, #16               @ encoding: [0x01,0x08,0x50,0xe3]
         %b = icmp ugt i32 %a, 65536
         br i1 %b, label %r, label %r
 r:

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=128897&r1=128896&r2=128897&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Tue Apr  5 13:02:46 2011
@@ -1,6 +1,6 @@
 # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s
 
-# CHECK:	addpl	r4, pc, #19, 8
+# CHECK:	addpl	r4, pc, #19, #8
 0x4c 0x45 0x8f 0x52
 
 # CHECK:	b	#0
@@ -66,7 +66,7 @@
 # CHECK:	movt	r8, #65535
 0xff 0x8f 0x4f 0xe3
 
-# CHECK:	mvnspl	r7, #245, 2
+# CHECK:	mvnspl	r7, #245, #2
 0xf5 0x71 0xf0 0x53
 
 # CHECK-NOT:	orr	r7, r8, r7, rrx #0
@@ -143,7 +143,7 @@
 # CHECK: msr cpsr_fc, r0
 0x00 0xf0 0x29 0xe1
 
-# CHECK:	msrmi	cpsr_c, #241, 8
+# CHECK:	msrmi	cpsr_c, #241, #8
 0xf1 0xf4 0x21 0x43
 
 # CHECK: rsbs r6, r7, r8



From grosbach at apple.com  Tue Apr  5 13:13:53 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 05 Apr 2011 11:13:53 -0700
Subject: [llvm-commits] [llvm] r128892 - in /llvm/trunk/lib/Target/ARM:
 ARMExpandPseudoInsts.cpp ARMInstrInfo.td
In-Reply-To: <20110405172425.4B26D2A6C12C@llvm.org>
References: <20110405172425.4B26D2A6C12C@llvm.org>
Message-ID: <EFC241F3-4B2D-48E7-AF79-12F8D3F4E820@apple.com>

Nice! Thanks for doing this.

Couple of comments inline.

On Apr 5, 2011, at 10:24 AM, Owen Anderson wrote:

> Author: resistor
> Date: Tue Apr  5 12:24:25 2011
> New Revision: 128892
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=128892&view=rev
> Log:
> Convert ADCS and SBCS instructions into pseudos that are expanded to the ADC/ABC with the appropriate S-bit input value.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp

Would it perhaps be better to handle these via a custom inserter instead of in the expansion pass? That way the real instruction is added earlier in translation and all of the machine instr passes will see them, not the pseudos. The expand-pseudos pass is a post-regalloc lowering.

This should have the added benefit of exposing these instructions to the if-conversion pass since they are predicable (and the pseudos are not).

>    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=128892&r1=128891&r2=128892&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Tue Apr  5 12:24:25 2011
> @@ -55,6 +55,7 @@
>     void ExpandVLD(MachineBasicBlock::iterator &MBBI);
>     void ExpandVST(MachineBasicBlock::iterator &MBBI);
>     void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
> +    void ExpandSBitOp(MachineBasicBlock::iterator &MBBI);
>     void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
>                     unsigned Opc, bool IsExt, unsigned NumRegs);
>     void ExpandMOV32BitImm(MachineBasicBlock &MBB,
> @@ -629,6 +630,43 @@
>   MI.eraseFromParent();
> }
> 
> +void ARMExpandPseudo::ExpandSBitOp(MachineBasicBlock::iterator &MBBI) {
> +  MachineInstr &MI = *MBBI;
> +  MachineBasicBlock &MBB = *MI.getParent();
> +  unsigned OldOpc = MI.getOpcode();
> +  unsigned Opc = 0;
> +  switch (OldOpc) {
> +    case ARM::ADCSSrr:
> +      Opc = ARM::ADCrr;
> +      break;
> +    case ARM::ADCSSri:
> +      Opc = ARM::ADCri;
> +      break;
> +    case ARM::ADCSSrs:
> +      Opc = ARM::ADCrs;
> +      break;
> +    case ARM::SBCSSrr:
> +      Opc = ARM::SBCrr;
> +      break;
> +    case ARM::SBCSSri:
> +      Opc = ARM::SBCri;
> +      break;
> +    case ARM::SBCSSrs:
> +      Opc = ARM::SBCrs;
> +      break;
> +    default:
> +      llvm_unreachable("Unknown opcode?");
> +  }
> +
> +  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
> +  MIB.addOperand(MachineOperand::CreateImm(0)); // Predicate

The predicate operand is actually two operands, a immediate (the condition code) and a register (either reg0 for unpredicated or CPSR for predicated).

> +  MIB.addOperand(MachineOperand::CreateImm(0)); // S bit

Likewise, the 's' bit operand is a register operand of reg0 or CPSR.


> +  for (unsigned i = 0; i < MI.getNumOperands(); ++i)
> +    MIB.addOperand(MI.getOperand(i));

The predicate and 's' bit operands come at the end of the operand list, not the beginning, right? So this should happen before adding the predicate and 's' bit operands.

> +  TransferImpOps(MI, MIB, MIB);
> +  MI.eraseFromParent();
> +}
> +
> void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
>                                         MachineBasicBlock::iterator &MBBI) {
>   MachineInstr &MI = *MBBI;
> @@ -941,6 +979,15 @@
>       ExpandMOV32BitImm(MBB, MBBI);
>       return true;
> 
> +    case ARM::ADCSSri:
> +    case ARM::ADCSSrr:
> +    case ARM::ADCSSrs:
> +    case ARM::SBCSSri:
> +    case ARM::SBCSSrr:
> +    case ARM::SBCSSrs:
> +      ExpandSBitOp(MBBI);
> +      return true;
> +
>     case ARM::VMOVQQ: {
>       unsigned DstReg = MI.getOperand(0).getReg();
>       bool DstIsDead = MI.getOperand(0).isDead();
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128892&r1=128891&r2=128892&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Apr  5 12:24:25 2011
> @@ -938,50 +938,18 @@
> let isCodeGenOnly = 1, Defs = [CPSR] in {
> multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
>                              bit Commutable = 0> {
> -  def Sri : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
> -                DPFrm, IIC_iALUi, !strconcat(opc, "\t$Rd, $Rn, $imm"),
> +  def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
> +                Size4Bytes, IIC_iALUi,
>                [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
> -               Requires<[IsARM]> {
> -    bits<4> Rd;
> -    bits<4> Rn;
> -    bits<12> imm;
> -    let Inst{31-27} = 0b1110; // non-predicated
> -    let Inst{15-12} = Rd;
> -    let Inst{19-16} = Rn;
> -    let Inst{11-0} = imm;
> -    let Inst{20} = 1;
> -    let Inst{25} = 1;
> -  }
> -  def Srr : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
> -                DPFrm, IIC_iALUr, !strconcat(opc, "\t$Rd, $Rn, $Rm"),
> +               Requires<[IsARM]>;
> +  def Srr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
> +                Size4Bytes, IIC_iALUr,
>                [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]>,
> -               Requires<[IsARM]> {
> -    bits<4> Rd;
> -    bits<4> Rn;
> -    bits<4> Rm;
> -    let Inst{31-27} = 0b1110; // non-predicated
> -    let Inst{11-4} = 0b00000000;
> -    let isCommutable = Commutable;
> -    let Inst{3-0} = Rm;
> -    let Inst{15-12} = Rd;
> -    let Inst{19-16} = Rn;
> -    let Inst{20} = 1;
> -    let Inst{25} = 0;
> -  }
> -  def Srs : AXI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> -                DPSoRegFrm, IIC_iALUsr, !strconcat(opc, "\t$Rd, $Rn, $shift"),
> +               Requires<[IsARM]>;
> +  def Srs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> +                Size4Bytes, IIC_iALUsr,
>                [(set GPR:$Rd, (opnode GPR:$Rn, so_reg:$shift))]>,
> -               Requires<[IsARM]> {
> -    bits<4> Rd;
> -    bits<4> Rn;
> -    bits<12> shift;
> -    let Inst{31-27} = 0b1110; // non-predicated
> -    let Inst{11-0} = shift;
> -    let Inst{15-12} = Rd;
> -    let Inst{19-16} = Rn;
> -    let Inst{20} = 1;
> -    let Inst{25} = 0;
> -  }
> +               Requires<[IsARM]>;
> }
> }
> }
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From daniel at zuster.org  Tue Apr  5 13:23:18 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 05 Apr 2011 18:23:18 -0000
Subject: [llvm-commits] [test-suite] r128900 -
	/test-suite/trunk/tools/get-report-time
Message-ID: <20110405182318.61F462A6C12C@llvm.org>

Author: ddunbar
Date: Tue Apr  5 13:23:18 2011
New Revision: 128900

URL: http://llvm.org/viewvc/llvm-project?rev=128900&view=rev
Log:
Add a trivial script to extract the times from *.report.txt files.

Added:
    test-suite/trunk/tools/get-report-time   (with props)

Added: test-suite/trunk/tools/get-report-time
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/tools/get-report-time?rev=128900&view=auto
==============================================================================
--- test-suite/trunk/tools/get-report-time (added)
+++ test-suite/trunk/tools/get-report-time Tue Apr  5 13:23:18 2011
@@ -0,0 +1,27 @@
+#!/usr/bin/env python
+
+import re
+import optparse
+
+def main():
+    parser = optparse.OptionParser("""\
+usage: %prog [options] <path>
+
+Reads the file at the given path and extracts any "program times" as used by the
+LLVM test-suite Makefiles.""")
+    opts,args = parser.parse_args()
+    if len(args) != 1:
+        parser.error('invalid number of arguments')
+       
+    file = open(args[0])
+    try:
+       re_pattern = re.compile(r"program ([0-9]+\.[0-9]+)")
+
+       data = file.read()
+       for match in re_pattern.finditer(data):
+          print match.group(1)
+    finally:
+       file.close()
+
+if __name__ == '__main__':
+   main()

Propchange: test-suite/trunk/tools/get-report-time
------------------------------------------------------------------------------
    svn:executable = *



From sabre at nondot.org  Tue Apr  5 13:38:45 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 05 Apr 2011 18:38:45 -0000
Subject: [llvm-commits] [llvm] r128902 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20110405183845.DFA1C2A6C12C@llvm.org>

Author: lattner
Date: Tue Apr  5 13:38:45 2011
New Revision: 128902

URL: http://llvm.org/viewvc/llvm-project?rev=128902&view=rev
Log:
more notes to self.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128902&r1=128901&r2=128902&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Apr  5 13:38:45 2011
@@ -238,6 +238,7 @@
 
 
 <!--=========================================================================-->
+<!--
 <div class="doc_subsection">
 <a name="klee">KLEE: A Symbolic Execution Virtual Machine</a>
 </div>
@@ -252,8 +253,7 @@
 </p>
 
 <p>UPDATE!</p>
-
-</div>
+</div>-->
 
 
 <!-- *********************************************************************** -->
@@ -299,7 +299,9 @@
 <ul>
 <li><pre>
   last release for llvm-gcc
-TBAA
+TBAA: On by default in clang.  Disable it with -fno-strict-aliasing.
+  Could be more aggressive for structs.
+  
 Triple::normalize is new, llvm triples are always stored in normalized form internally.
 
 Triple x86_64--mingw64 is obsoleted. Use x86_64--mingw32 instead.
@@ -315,7 +317,8 @@
 
 ARM Fast ISel
 
-ELF MC support
+ELF MC support: on by default in clang.  There are still known missing features
+  for human written assembly.
 
 X86: Reimplemented all of MMX to introduce a new LLVM IR x86_mmx type.  Now
   random types like &lt;2 x i32&gt; are not iseld to mmx without emms.
@@ -340,16 +343,57 @@
   
 EarlyCSE pass.
 
+- DIBuilder provides simpler interface for front ends like Clang to encode debug info in LLVM IR.
+  - This interface hides implementation details (e.g. DIDerivedType, existence of compile unit etc..) that any front end should not know about.
+  For example,
+  Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type,
+  findRegion(TYPE_CONTEXT(type)),
+  StringRef(),
+  getOrCreateFile(main_input_filename),
+  0 /*line no*/,
+  NodeSizeInBits(type),
+  NodeAlignInBits(type),
+  0 /*offset */,
+  0 /* flags */,
+  MainTy);
+  can be replaced by
+  DbgTy = DBuilder.createQualifiedType(DW_TAG_volatile_type, MainTy); 
+  
+PPC: Switched to MCInstPrinter, and MCCodeEmitter.  Ready to implement support
+  for directly writing out mach-o object files, but noone seems interested.
 
 ARM: Improved code generation for Cortex-A8 and Cortex-A9 CPUs.
   
 Scheduler now models operand latency and pipeline forwarding.
   
-Major regalloc rewrite, not on by default for 2.9.
+error_code + libsystem + PathV2 changes
+
+new macho-dump tool
+
+Major regalloc rewrite, not on by default for 2.9 and not advised to use it.
+ * New basic register allocator that can be used as a safe fallback when
+   debugging. Enable with -regalloc=basic.
+ * New infrastructure for live range splitting. SplitKit can break a live
+   interval into smaller pieces while preserving SSA form, and SpillPlacement
+   can help find the best split points. This is a work in progress so the API
+   is changing quickly.
+ * The inline spiller has learned to clean up after live range splitting. It
+   can hoist spills out of loops, and it can eliminate redundant spills.
+   Rematerialization works with live range splitting.
+ * New greedy register allocator using live range splitting. This will be the
+   default register allocator in the next LLVM release, but it is not turned on
+   by default in 2.9.
+
+ARM: __builtin_prefetch turns into prefetch instructions.
+  
 MC assembler support for 3dNow! and 3DNowA instructions.
   
+tblgen support for assembler aliases: <a 
+  href="CodeGenerator.html#na_instparsing">MnemonicAlias and InstAlias</a>
+  
 LoopIndexSplit pass was removed, unmaintained.
   
+include/llvm/System merged into include/llvm/Support.
  
 Win32 PE-COFF support in the MC assembler has made a lot of progress in the 2.9
   timeframe, but is still not generally useful.  Please see 
@@ -361,10 +405,19 @@
 MicroBlaze: major updates for aggressive delay slot filler, MC-based assembly
    printing, assembly instruction parsing, ELF .o file emission, and MC
    instruction disassembler.
+  
+Countless ARM microoptimizations.
+
+Speedups to various mid-level passes:
+  GVN is much faster on functions with deep dominator trees / lots of BBs.
+  DomTree and DominatorFrontier are much faster to compute.
+  
+  
+new 'hotpatch' attribute: LangRef.html#fnattrs
 </pre></li>
 </ul>
   
-Still todo: [101025-110228]
+Still todo: [101129-110228]
 
 </div>
 



From grosbach at apple.com  Tue Apr  5 13:40:13 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 05 Apr 2011 18:40:13 -0000
Subject: [llvm-commits] [llvm] r128903 - in /llvm/trunk/lib/Target/ARM:
 ARMInstrInfo.td Disassembler/ARMDisassemblerCore.cpp
Message-ID: <20110405184013.66EFC2A6C12C@llvm.org>

Author: grosbach
Date: Tue Apr  5 13:40:13 2011
New Revision: 128903

URL: http://llvm.org/viewvc/llvm-project?rev=128903&view=rev
Log:
Make second source operand of LDRD pre/post explicit.

Finish what r128736 started.


Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128903&r1=128902&r2=128903&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Apr  5 13:40:13 2011
@@ -1632,7 +1632,7 @@
                    IIC_iLoad_bh_r, "ldrsb", "\t$Rt, $addr",
                    [(set GPR:$Rt, (sextloadi8 addrmode3:$addr))]>;
 
-let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
+let mayLoad = 1, neverHasSideEffects = 1 in {
 // Load doubleword
 def LDRD : AI3ld<0b1101, 0, (outs GPR:$Rd, GPR:$dst2),
                  (ins addrmode3:$addr), LdMiscFrm,
@@ -1707,8 +1707,31 @@
 defm LDRH  : AI3_ldridx<0b1011, 1, "ldrh", IIC_iLoad_bh_ru>;
 defm LDRSH : AI3_ldridx<0b1111, 1, "ldrsh", IIC_iLoad_bh_ru>;
 defm LDRSB : AI3_ldridx<0b1101, 1, "ldrsb", IIC_iLoad_bh_ru>;
-let hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
-defm LDRD :  AI3_ldridx<0b1101, 0, "ldrd", IIC_iLoad_d_ru>;
+def LDRD_PRE : AI3ldstidx<0b1101, 0, 1, 1, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
+                          (ins addrmode3:$addr), IndexModePre,
+                          LdMiscFrm, IIC_iLoad_d_ru,
+                          "ldrd", "\t$Rt, $Rt2, $addr!",
+                          "$addr.base = $Rn_wb", []> {
+  bits<14> addr;
+  let Inst{23}    = addr{8};      // U bit
+  let Inst{22}    = addr{13};     // 1 == imm8, 0 == Rm
+  let Inst{19-16} = addr{12-9};   // Rn
+  let Inst{11-8}  = addr{7-4};    // imm7_4/zero
+  let Inst{3-0}   = addr{3-0};    // imm3_0/Rm
+}
+def LDRD_POST: AI3ldstidx<0b1101, 0, 1, 0, (outs GPR:$Rt, GPR:$Rt2, GPR:$Rn_wb),
+                          (ins GPR:$Rn, am3offset:$offset), IndexModePost,
+                          LdMiscFrm, IIC_iLoad_d_ru,
+                          "ldrd", "\t$Rt, $Rt2, [$Rn], $offset",
+                          "$Rn = $Rn_wb", []> {
+  bits<10> offset;
+  bits<4> Rn;
+  let Inst{23}    = offset{8};      // U bit
+  let Inst{22}    = offset{9};      // 1 == imm8, 0 == Rm
+  let Inst{19-16} = Rn;
+  let Inst{11-8}  = offset{7-4};    // imm7_4/zero
+  let Inst{3-0}   = offset{3-0};    // imm3_0/Rm
+}
 } // mayLoad = 1, neverHasSideEffects = 1
 
 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128903&r1=128902&r2=128903&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Apr  5 13:40:13 2011
@@ -1232,8 +1232,6 @@
     ++OpIdx;
   }
 
-  bool DualReg = HasDualReg(Opcode);
-
   // Disassemble the dst/src operand.
   if (OpIdx >= NumOps)
     return false;
@@ -1244,9 +1242,8 @@
                                                      decodeRd(insn))));
   ++OpIdx;
 
-  // Fill in LDRD and STRD's second operand, but only if it's offset mode OR we
-  // have a pre-or-post-indexed store operation.
-  if (DualReg && (!isPrePost || isStore)) {
+  // Fill in LDRD and STRD's second operand Rt operand.
+  if (HasDualReg(Opcode)) {
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        decodeRd(insn) + 1)));
     ++OpIdx;



From ssen at apple.com  Tue Apr  5 13:40:45 2011
From: ssen at apple.com (Shantonu Sen)
Date: Tue, 05 Apr 2011 18:40:45 -0000
Subject: [llvm-commits] [llvm] r128904 -
	/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp
Message-ID: <20110405184045.68D762A6C12C@llvm.org>

Author: ssen
Date: Tue Apr  5 13:40:45 2011
New Revision: 128904

URL: http://llvm.org/viewvc/llvm-project?rev=128904&view=rev
Log:
An MCDisassembler has the option to not implement
getEDInfo(), in which case this code would dereference
NULL. EDInst can already handle NULL info, so avoid
the dereference and pass NULL through.

Reviewed by Sean Callanan

Modified:
    llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp

Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=128904&r1=128903&r2=128904&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original)
+++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Tue Apr  5 13:40:45 2011
@@ -254,9 +254,11 @@
     delete inst;
     return NULL;
   } else {
-    const llvm::EDInstInfo *thisInstInfo;
+    const llvm::EDInstInfo *thisInstInfo = NULL;
 
-    thisInstInfo = &InstInfos[inst->getOpcode()];
+    if (InstInfos) {
+      thisInstInfo = &InstInfos[inst->getOpcode()];
+    }
     
     EDInst* sdInst = new EDInst(inst, byteSize, *this, thisInstInfo);
     return sdInst;



From atrick at apple.com  Tue Apr  5 13:41:31 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 05 Apr 2011 18:41:31 -0000
Subject: [llvm-commits] [llvm] r128905 - in /llvm/trunk/tools: llc/llc.cpp
	opt/opt.cpp
Message-ID: <20110405184131.5CDA12A6C12C@llvm.org>

Author: atrick
Date: Tue Apr  5 13:41:31 2011
New Revision: 128905

URL: http://llvm.org/viewvc/llvm-project?rev=128905&view=rev
Log:
whitespace

Modified:
    llvm/trunk/tools/llc/llc.cpp
    llvm/trunk/tools/opt/opt.cpp

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=128905&r1=128904&r2=128905&view=diff
==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Tue Apr  5 13:41:31 2011
@@ -207,7 +207,7 @@
   InitializeAllAsmParsers();
 
   cl::ParseCommandLineOptions(argc, argv, "llvm system compiler\n");
-  
+
   // Load the module to be compiled...
   SMDiagnostic Err;
   std::auto_ptr<Module> M;
@@ -271,7 +271,7 @@
     FeaturesStr = Features.getString();
   }
 
-  std::auto_ptr<TargetMachine> 
+  std::auto_ptr<TargetMachine>
     target(TheTarget->createTargetMachine(TheTriple.getTriple(), FeaturesStr));
   assert(target.get() && "Could not allocate target machine!");
   TargetMachine &Target = *target.get();

Modified: llvm/trunk/tools/opt/opt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=128905&r1=128904&r2=128905&view=diff
==============================================================================
--- llvm/trunk/tools/opt/opt.cpp (original)
+++ llvm/trunk/tools/opt/opt.cpp Tue Apr  5 13:41:31 2011
@@ -133,11 +133,11 @@
 AnalyzeOnly("analyze", cl::desc("Only perform analysis, no optimization"));
 
 static cl::opt<bool>
-PrintBreakpoints("print-breakpoints-for-testing", 
+PrintBreakpoints("print-breakpoints-for-testing",
                  cl::desc("Print select breakpoints location for testing"));
 
 static cl::opt<std::string>
-DefaultDataLayout("default-data-layout", 
+DefaultDataLayout("default-data-layout",
           cl::desc("data layout string to use if not specified by module"),
           cl::value_desc("layout-string"), cl::init(""));
 
@@ -328,7 +328,7 @@
           << "': Pass " << PassToPrint->getPassName() << ":\n";
 
     // Get and print pass...
-    getAnalysisID<Pass>(PassToPrint->getTypeInfo()).print(Out, 
+    getAnalysisID<Pass>(PassToPrint->getTypeInfo()).print(Out,
             BB.getParent()->getParent());
     return false;
   }
@@ -479,7 +479,7 @@
 
   llvm_shutdown_obj Y;  // Call llvm_shutdown() on exit.
   LLVMContext &Context = getGlobalContext();
-  
+
   // Initialize passes
   PassRegistry &Registry = *PassRegistry::getPassRegistry();
   initializeCore(Registry);
@@ -491,7 +491,7 @@
   initializeInstCombine(Registry);
   initializeInstrumentation(Registry);
   initializeTarget(Registry);
-  
+
   cl::ParseCommandLineOptions(argc, argv,
     "llvm .bc -> .bc modular optimizer and analysis printer\n");
 
@@ -549,12 +549,12 @@
 
   // Add an appropriate TargetLibraryInfo pass for the module's triple.
   TargetLibraryInfo *TLI = new TargetLibraryInfo(Triple(M->getTargetTriple()));
-  
+
   // The -disable-simplify-libcalls flag actually disables all builtin optzns.
   if (DisableSimplifyLibCalls)
     TLI->disableAllFunctions();
   Passes.add(TLI);
-  
+
   // Add an appropriate TargetData instance for this module.
   TargetData *TD = 0;
   const std::string &ModuleDataLayout = M.get()->getDataLayout();
@@ -578,7 +578,7 @@
     if (!Out) {
       if (OutputFilename.empty())
         OutputFilename = "-";
-      
+
       std::string ErrorInfo;
       Out.reset(new tool_output_file(OutputFilename.c_str(), ErrorInfo,
                                      raw_fd_ostream::F_Binary));



From johnny.chen at apple.com  Tue Apr  5 13:41:40 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 18:41:40 -0000
Subject: [llvm-commits] [llvm] r128906 - in /llvm/trunk/test/CodeGen/ARM:
 constants.ll fp.ll long.ll select-imm.ll select_xform.ll sub.ll
Message-ID: <20110405184141.0AD492A6C12C@llvm.org>

Author: johnny
Date: Tue Apr  5 13:41:40 2011
New Revision: 128906

URL: http://llvm.org/viewvc/llvm-project?rev=128906&view=rev
Log:
Fix test-llvm failures.

Modified:
    llvm/trunk/test/CodeGen/ARM/constants.ll
    llvm/trunk/test/CodeGen/ARM/fp.ll
    llvm/trunk/test/CodeGen/ARM/long.ll
    llvm/trunk/test/CodeGen/ARM/select-imm.ll
    llvm/trunk/test/CodeGen/ARM/select_xform.ll
    llvm/trunk/test/CodeGen/ARM/sub.ll

Modified: llvm/trunk/test/CodeGen/ARM/constants.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/constants.ll?rev=128906&r1=128905&r2=128906&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/constants.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/constants.ll Tue Apr  5 13:41:40 2011
@@ -14,31 +14,31 @@
 
 define i32 @f3() {
 ; CHECK: f3
-; CHECK: mov r0, #1, 24
+; CHECK: mov r0, #1, #24
         ret i32 256
 }
 
 define i32 @f4() {
 ; CHECK: f4
-; CHECK: orr{{.*}}#1, 24
+; CHECK: orr{{.*}}#1, #24
         ret i32 257
 }
 
 define i32 @f5() {
 ; CHECK: f5
-; CHECK: mov r0, #255, 2
+; CHECK: mov r0, #255, #2
         ret i32 -1073741761
 }
 
 define i32 @f6() {
 ; CHECK: f6
-; CHECK: mov r0, #63, 28
+; CHECK: mov r0, #63, #28
         ret i32 1008
 }
 
 define void @f7(i32 %a) {
 ; CHECK: f7
-; CHECK: cmp r0, #1, 16
+; CHECK: cmp r0, #1, #16
         %b = icmp ugt i32 %a, 65536
         br i1 %b, label %r, label %r
 r:

Modified: llvm/trunk/test/CodeGen/ARM/fp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fp.ll?rev=128906&r1=128905&r2=128906&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/fp.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/fp.ll Tue Apr  5 13:41:40 2011
@@ -51,7 +51,7 @@
 
 define float @h2() {
 ;CHECK: h2:
-;CHECK: mov r0, #254, 10
+;CHECK: mov r0, #254, #10
 entry:
         ret float 1.000000e+00
 }

Modified: llvm/trunk/test/CodeGen/ARM/long.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/long.ll?rev=128906&r1=128905&r2=128906&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/long.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/long.ll Tue Apr  5 13:41:40 2011
@@ -14,14 +14,14 @@
 
 define i64 @f3() {
 ; CHECK: f3:
-; CHECK: mvn r0, #2, 2
+; CHECK: mvn r0, #2, #2
 entry:
         ret i64 2147483647
 }
 
 define i64 @f4() {
 ; CHECK: f4:
-; CHECK: mov r0, #2, 2
+; CHECK: mov r0, #2, #2
 entry:
         ret i64 2147483648
 }
@@ -29,7 +29,7 @@
 define i64 @f5() {
 ; CHECK: f5:
 ; CHECK: mvn r0, #0
-; CHECK: mvn r1, #2, 2
+; CHECK: mvn r1, #2, #2
 entry:
         ret i64 9223372036854775807
 }

Modified: llvm/trunk/test/CodeGen/ARM/select-imm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select-imm.ll?rev=128906&r1=128905&r2=128906&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select-imm.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select-imm.ll Tue Apr  5 13:41:40 2011
@@ -6,7 +6,7 @@
 entry:
 ; ARM: t1:
 ; ARM: mov r1, #101
-; ARM: orr r1, r1, #1, 24
+; ARM: orr r1, r1, #1, #24
 ; ARM: movgt r0, #123
 
 ; ARMT2: t1:
@@ -27,7 +27,7 @@
 ; ARM: t2:
 ; ARM: mov r0, #123
 ; ARM: movgt r0, #101
-; ARM: orrgt r0, r0, #1, 24
+; ARM: orrgt r0, r0, #1, #24
 
 ; ARMT2: t2:
 ; ARMT2: mov r0, #123

Modified: llvm/trunk/test/CodeGen/ARM/select_xform.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/select_xform.ll?rev=128906&r1=128905&r2=128906&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/select_xform.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/select_xform.ll Tue Apr  5 13:41:40 2011
@@ -4,7 +4,7 @@
 
 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
 ; ARM: t1:
-; ARM: sub r0, r1, #6, 2
+; ARM: sub r0, r1, #6, #2
 ; ARM: movgt r0, r1
 
 ; T2: t1:

Modified: llvm/trunk/test/CodeGen/ARM/sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/sub.ll?rev=128906&r1=128905&r2=128906&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/sub.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/sub.ll Tue Apr  5 13:41:40 2011
@@ -12,7 +12,7 @@
 ; 66846720 = 0x03fc0000
 define i64 @f2(i64 %a) {
 ; CHECK: f2
-; CHECK: subs r0, r0, #255, 14
+; CHECK: subs r0, r0, #255, #14
 ; CHECK: sbc r1, r1, #0
     %tmp = sub i64 %a, 66846720
     ret i64 %tmp



From bob.wilson at apple.com  Tue Apr  5 13:54:52 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 05 Apr 2011 11:54:52 -0700
Subject: [llvm-commits] [llvm] r128897 - in /llvm/trunk:
 lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
 test/MC/ARM/simple-encoding.ll test/MC/Disassembler/ARM/arm-tests.txt
In-Reply-To: <20110405180246.D92582A6C12C@llvm.org>
References: <20110405180246.D92582A6C12C@llvm.org>
Message-ID: <5CB8B13B-E6F1-4C6F-9DD8-2D3B3FE68C36@apple.com>

This is breaking a bunch of tests for me:

Failing Tests (6):
    LLVM :: CodeGen/ARM/constants.ll
    LLVM :: CodeGen/ARM/fp.ll
    LLVM :: CodeGen/ARM/long.ll
    LLVM :: CodeGen/ARM/select-imm.ll
    LLVM :: CodeGen/ARM/select_xform.ll
    LLVM :: CodeGen/ARM/sub.ll

Please fix or revert ASAP.

On Apr 5, 2011, at 11:02 AM, Johnny Chen wrote:

> Author: johnny
> Date: Tue Apr  5 13:02:46 2011
> New Revision: 128897
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=128897&view=rev
> Log:
> Constants with multiple encodings (ARM):
> An alternative syntax is available for a modified immediate constant that permits the programmer to specify
> the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
> 
>    <byte> is the numeric value of abcdefgh, in the range 0-255
>    <rot> is twice the numeric value of rotation, an even number in the range 0-30.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>    llvm/trunk/test/MC/ARM/simple-encoding.ll
>    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
> 
> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=128897&r1=128896&r2=128897&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Apr  5 13:02:46 2011
> @@ -136,9 +136,10 @@
>   unsigned Rot = ARM_AM::getSOImmValRot(V);
> 
>   // Print low-level immediate formation info, per
> -  // A5.1.3: "Data-processing operands - Immediate".
> +  // A5.2.3: Data-processing (immediate), and
> +  // A5.2.4: Modified immediate constants in ARM instructions
>   if (Rot) {
> -    O << "#" << Imm << ", " << Rot;
> +    O << "#" << Imm << ", #" << Rot;
>     // Pretty printed version.
>     if (CommentStream)
>       *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
> 
> Modified: llvm/trunk/test/MC/ARM/simple-encoding.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-encoding.ll?rev=128897&r1=128896&r2=128897&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/ARM/simple-encoding.ll (original)
> +++ llvm/trunk/test/MC/ARM/simple-encoding.ll Tue Apr  5 13:02:46 2011
> @@ -39,7 +39,7 @@
> 
> define i32 @f4(i32 %a, i32 %b) {
> ; CHECK: f4
> -; CHECK: add r0, r0, #254, 28         @ encoding: [0xfe,0x0e,0x80,0xe2]
> +; CHECK: add r0, r0, #254, #28        @ encoding: [0xfe,0x0e,0x80,0xe2]
> ; CHECK:                              @ 4064
> ; CHECK: bx lr                        @ encoding: [0x1e,0xff,0x2f,0xe1]
>   %add = add nsw i32 %a, 4064
> @@ -118,7 +118,7 @@
> define i64 @f13() {
> ; CHECK: f13:
> ; CHECK: mvn r0, #0                   @ encoding: [0x00,0x00,0xe0,0xe3]
> -; CHECK: mvn r1, #2, 2                @ encoding: [0x02,0x11,0xe0,0xe3]
> +; CHECK: mvn r1, #2, #2               @ encoding: [0x02,0x11,0xe0,0xe3]
>         ret i64 9223372036854775807
> }
> 
> @@ -229,7 +229,7 @@
> 
> define void @f24(i32 %a) {
> ; CHECK: f24
> -; CHECK: cmp r0, #1, 16               @ encoding: [0x01,0x08,0x50,0xe3]
> +; CHECK: cmp r0, #1, #16               @ encoding: [0x01,0x08,0x50,0xe3]
>         %b = icmp ugt i32 %a, 65536
>         br i1 %b, label %r, label %r
> r:
> 
> Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=128897&r1=128896&r2=128897&view=diff
> ==============================================================================
> --- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
> +++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Tue Apr  5 13:02:46 2011
> @@ -1,6 +1,6 @@
> # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s
> 
> -# CHECK:	addpl	r4, pc, #19, 8
> +# CHECK:	addpl	r4, pc, #19, #8
> 0x4c 0x45 0x8f 0x52
> 
> # CHECK:	b	#0
> @@ -66,7 +66,7 @@
> # CHECK:	movt	r8, #65535
> 0xff 0x8f 0x4f 0xe3
> 
> -# CHECK:	mvnspl	r7, #245, 2
> +# CHECK:	mvnspl	r7, #245, #2
> 0xf5 0x71 0xf0 0x53
> 
> # CHECK-NOT:	orr	r7, r8, r7, rrx #0
> @@ -143,7 +143,7 @@
> # CHECK: msr cpsr_fc, r0
> 0x00 0xf0 0x29 0xe1
> 
> -# CHECK:	msrmi	cpsr_c, #241, 8
> +# CHECK:	msrmi	cpsr_c, #241, #8
> 0xf1 0xf4 0x21 0x43
> 
> # CHECK: rsbs r6, r7, r8
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From johnny.chen at apple.com  Tue Apr  5 13:53:14 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 18:53:14 -0000
Subject: [llvm-commits] [llvm] r128909 -
	/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
Message-ID: <20110405185314.6F89A2A6C12C@llvm.org>

Author: johnny
Date: Tue Apr  5 13:53:14 2011
New Revision: 128909

URL: http://llvm.org/viewvc/llvm-project?rev=128909&view=rev
Log:
LDRD now prints out two dst registers.

Modified:
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=128909&r1=128908&r2=128909&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Tue Apr  5 13:53:14 2011
@@ -179,7 +179,7 @@
 # CHECK:	strdeq	r2, r3, [r0], -r8
 0xf8 0x24 0x00 0x00
 
-# CHECK:	ldrdeq	r2, [r0], -r12
+# CHECK:	ldrdeq	r2, r3, [r0], -r12
 0xdc 0x24 0x00 0x00
 
 # CHECK:	ldrbt	r3, [r4], -r5, lsl #12



From atrick at apple.com  Tue Apr  5 13:54:36 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 05 Apr 2011 18:54:36 -0000
Subject: [llvm-commits] [llvm] r128910 - in /llvm/trunk:
 include/llvm/Support/CommandLine.h lib/Support/CommandLine.cpp
 tools/llc/llc.cpp tools/opt/opt.cpp
Message-ID: <20110405185436.B29042A6C12C@llvm.org>

Author: atrick
Date: Tue Apr  5 13:54:36 2011
New Revision: 128910

URL: http://llvm.org/viewvc/llvm-project?rev=128910&view=rev
Log:
Added *hidden* flags -print-options and -print-all-options so
developers can see if their driver changed any cl::Option's. The
current implementation isn't perfect but handles most kinds of
options. This is nice to have when decomposing the stages of
compilation and moving between different drivers. It's also a good
sanity check when comparing results produced by different command line
invocations that are expected to produce the comparable results.

Note: This is not an attempt to prolong the life of cl::Option. On the
contrary, it's a placeholder for a feature that must exist when
cl::Option is replaced by a more appropriate framework. A new
framework needs: a central option registry, dynamic name lookup,
non-global containers of option values (e.g. per-module,
per-function), *and* the ability to print options values and their defaults at
any point during compilation.

Modified:
    llvm/trunk/include/llvm/Support/CommandLine.h
    llvm/trunk/lib/Support/CommandLine.cpp
    llvm/trunk/tools/llc/llc.cpp
    llvm/trunk/tools/opt/opt.cpp

Modified: llvm/trunk/include/llvm/Support/CommandLine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CommandLine.h?rev=128910&r1=128909&r2=128910&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CommandLine.h (original)
+++ llvm/trunk/include/llvm/Support/CommandLine.h Tue Apr  5 13:54:36 2011
@@ -60,6 +60,12 @@
 void SetVersionPrinter(void (*func)());
 
 
+// PrintOptionValues - Print option values.
+// With -print-options print the difference between option values and defaults.
+// With -print-all-options print all option values.
+// (Currently not perfect, but best-effort.)
+void PrintOptionValues();
+
 // MarkOptionsChanged - Internal helper function.
 void MarkOptionsChanged();
 
@@ -230,6 +236,8 @@
   //
   virtual void printOptionInfo(size_t GlobalWidth) const = 0;
 
+  virtual void printOptionValue(size_t GlobalWidth, bool Force) const = 0;
+
   virtual void getExtraOptionNames(SmallVectorImpl<const char*> &) {}
 
   // addOccurrence - Wrapper around handleOccurrence that enforces Flags.
@@ -303,6 +311,120 @@
 
 
 //===----------------------------------------------------------------------===//
+// OptionValue class
+
+// Support value comparison outside the template.
+struct GenericOptionValue {
+  virtual ~GenericOptionValue() {}
+  virtual bool compare(const GenericOptionValue &V) const = 0;
+};
+
+template<class DataType> struct OptionValue;
+
+// The default value safely does nothing. Option value printing is only
+// best-effort.
+template<class DataType, bool isClass>
+struct OptionValueBase : public GenericOptionValue {
+  // Temporary storage for argument passing.
+  typedef OptionValue<DataType> WrapperType;
+
+  bool hasValue() const { return false; }
+
+  const DataType &getValue() const { assert(false && "no default value"); }
+
+  // Some options may take their value from a different data type.
+  template<class DT>
+  void setValue(const DT& V) {}
+
+  bool compare(const DataType &V) const { return false; }
+
+  virtual bool compare(const GenericOptionValue& V) const { return false; }
+};
+
+// Simple copy of the option value.
+template<class DataType>
+class OptionValueCopy : public GenericOptionValue {
+  DataType Value;
+  bool Valid;
+public:
+  OptionValueCopy() : Valid(false) {}
+
+  bool hasValue() const { return Valid; }
+
+  const DataType &getValue() const {
+    assert(Valid && "invalid option value");
+    return Value;
+  }
+
+  void setValue(const DataType &V) { Valid = true; Value = V; }
+
+  bool compare(const DataType &V) const {
+    return Valid && (Value != V);
+  }
+
+  virtual bool compare(const GenericOptionValue &V) const {
+    const OptionValueCopy<DataType> &VC =
+      static_cast< const OptionValueCopy<DataType>& >(V);
+    if (!VC.hasValue) return false;
+    return compare(VC.getValue());
+  }
+};
+
+// Non-class option values.
+template<class DataType>
+struct OptionValueBase<DataType, false> : OptionValueCopy<DataType> {
+  typedef DataType WrapperType;
+};
+
+// Top-level option class.
+template<class DataType>
+struct OptionValue : OptionValueBase<DataType, is_class<DataType>::value> {
+  OptionValue() {}
+
+  OptionValue(const DataType& V) {
+    this->setValue(V);
+  }
+  // Some options may take their value from a different data type.
+  template<class DT>
+  OptionValue<DataType> &operator=(const DT& V) {
+    this->setValue(V);
+    return *this;
+  }
+};
+
+// Other safe-to-copy-by-value common option types.
+enum boolOrDefault { BOU_UNSET, BOU_TRUE, BOU_FALSE };
+template<>
+struct OptionValue<cl::boolOrDefault> : OptionValueCopy<cl::boolOrDefault> {
+  typedef cl::boolOrDefault WrapperType;
+
+  OptionValue() {}
+
+  OptionValue(const cl::boolOrDefault& V) {
+    this->setValue(V);
+  }
+  OptionValue<cl::boolOrDefault> &operator=(const cl::boolOrDefault& V) {
+    setValue(V);
+    return *this;
+  }
+};
+
+template<>
+struct OptionValue<std::string> : OptionValueCopy<std::string> {
+  typedef StringRef WrapperType;
+
+  OptionValue() {}
+
+  OptionValue(const std::string& V) {
+    this->setValue(V);
+  }
+  OptionValue<std::string> &operator=(const std::string& V) {
+    setValue(V);
+    return *this;
+  }
+};
+
+//===----------------------------------------------------------------------===//
 // Enum valued command line option
 //
 #define clEnumVal(ENUMVAL, DESC) #ENUMVAL, int(ENUMVAL), DESC
@@ -355,7 +477,6 @@
     return Vals;
 }
 
-
 //===----------------------------------------------------------------------===//
 // parser class - Parameterizable parser for different data types.  By default,
 // known data types (string, int, bool) have specialized parsers, that do what
@@ -368,7 +489,16 @@
 // not need replicated for every instance of the generic parser.  This also
 // allows us to put stuff into CommandLine.cpp
 //
-struct generic_parser_base {
+class generic_parser_base {
+protected:
+  class GenericOptionInfo {
+  public:
+    GenericOptionInfo(const char *name, const char *helpStr) :
+      Name(name), HelpStr(helpStr) {}
+    const char *Name;
+    const char *HelpStr;
+  };
+public:
   virtual ~generic_parser_base() {}  // Base class should have virtual-dtor
 
   // getNumOptions - Virtual function implemented by generic subclass to
@@ -385,11 +515,28 @@
   // Return the width of the option tag for printing...
   virtual size_t getOptionWidth(const Option &O) const;
 
+  virtual const GenericOptionValue &getOptionValue(unsigned N) const = 0;
+
   // printOptionInfo - Print out information about this option.  The
   // to-be-maintained width is specified.
   //
   virtual void printOptionInfo(const Option &O, size_t GlobalWidth) const;
 
+  void printGenericOptionDiff(const Option &O, const GenericOptionValue &V,
+                              const GenericOptionValue &Default,
+                              size_t GlobalWidth) const;
+
+  // printOptionDiff - print the value of an option and it's default.
+  //
+  // Template definition ensures that the option and default have the same
+  // DataType (via the same AnyOptionValue).
+  template<class AnyOptionValue>
+  void printOptionDiff(const Option &O, const AnyOptionValue &V,
+                       const AnyOptionValue &Default,
+                       size_t GlobalWidth) const {
+    printGenericOptionDiff(O, V, Default, GlobalWidth);
+  }
+
   void initialize(Option &O) {
     // All of the modifiers for the option have been processed by now, so the
     // argstr field should be stable, copy it down now.
@@ -443,13 +590,11 @@
 template <class DataType>
 class parser : public generic_parser_base {
 protected:
-  class OptionInfo {
+  class OptionInfo : public GenericOptionInfo {
   public:
     OptionInfo(const char *name, DataType v, const char *helpStr) :
-      Name(name), V(v), HelpStr(helpStr) {}
-    const char *Name;
-    DataType V;
-    const char *HelpStr;
+      GenericOptionInfo(name, helpStr), V(v) {}
+    OptionValue<DataType> V;
   };
   SmallVector<OptionInfo, 8> Values;
 public:
@@ -462,6 +607,11 @@
     return Values[N].HelpStr;
   }
 
+  // getOptionValue - Return the value of option name N.
+  virtual const GenericOptionValue &getOptionValue(unsigned N) const {
+    return Values[N].V;
+  }
+
   // parse - Return true on error.
   bool parse(Option &O, StringRef ArgName, StringRef Arg, DataType &V) {
     StringRef ArgVal;
@@ -473,7 +623,7 @@
     for (unsigned i = 0, e = static_cast<unsigned>(Values.size());
          i != e; ++i)
       if (Values[i].Name == ArgVal) {
-        V = Values[i].V;
+        V = Values[i].V.getValue();
         return false;
       }
 
@@ -522,11 +672,19 @@
   //
   void printOptionInfo(const Option &O, size_t GlobalWidth) const;
 
+  // printOptionNoValue - Print a placeholder for options that don't yet support
+  // printOptionDiff().
+  void printOptionNoValue(const Option &O, size_t GlobalWidth) const;
+
   // getValueName - Overload in subclass to provide a better default value.
   virtual const char *getValueName() const { return "value"; }
 
   // An out-of-line virtual method to provide a 'home' for this class.
   virtual void anchor();
+
+protected:
+  // A helper for basic_parser::printOptionDiff.
+  void printOptionName(const Option &O, size_t GlobalWidth) const;
 };
 
 // basic_parser - The real basic parser is just a template wrapper that provides
@@ -536,6 +694,7 @@
 class basic_parser : public basic_parser_impl {
 public:
   typedef DataType parser_data_type;
+  typedef OptionValue<DataType> OptVal;
 };
 
 //--------------------------------------------------
@@ -561,6 +720,9 @@
   // getValueName - Do not print =<value> at all.
   virtual const char *getValueName() const { return 0; }
 
+  void printOptionDiff(const Option &O, bool V, OptVal Default,
+                       size_t GlobalWidth) const;
+
   // An out-of-line virtual method to provide a 'home' for this class.
   virtual void anchor();
 };
@@ -569,7 +731,6 @@
 
 //--------------------------------------------------
 // parser<boolOrDefault>
-enum boolOrDefault { BOU_UNSET, BOU_TRUE, BOU_FALSE };
 template<>
 class parser<boolOrDefault> : public basic_parser<boolOrDefault> {
 public:
@@ -583,6 +744,9 @@
   // getValueName - Do not print =<value> at all.
   virtual const char *getValueName() const { return 0; }
 
+  void printOptionDiff(const Option &O, boolOrDefault V, OptVal Default,
+                       size_t GlobalWidth) const;
+
   // An out-of-line virtual method to provide a 'home' for this class.
   virtual void anchor();
 };
@@ -601,6 +765,9 @@
   // getValueName - Overload in subclass to provide a better default value.
   virtual const char *getValueName() const { return "int"; }
 
+  void printOptionDiff(const Option &O, int V, OptVal Default,
+                       size_t GlobalWidth) const;
+
   // An out-of-line virtual method to provide a 'home' for this class.
   virtual void anchor();
 };
@@ -620,6 +787,9 @@
   // getValueName - Overload in subclass to provide a better default value.
   virtual const char *getValueName() const { return "uint"; }
 
+  void printOptionDiff(const Option &O, unsigned V, OptVal Default,
+                       size_t GlobalWidth) const;
+
   // An out-of-line virtual method to provide a 'home' for this class.
   virtual void anchor();
 };
@@ -638,6 +808,9 @@
   // getValueName - Overload in subclass to provide a better default value.
   virtual const char *getValueName() const { return "number"; }
 
+  void printOptionDiff(const Option &O, double V, OptVal Default,
+                       size_t GlobalWidth) const;
+
   // An out-of-line virtual method to provide a 'home' for this class.
   virtual void anchor();
 };
@@ -656,6 +829,9 @@
   // getValueName - Overload in subclass to provide a better default value.
   virtual const char *getValueName() const { return "number"; }
 
+  void printOptionDiff(const Option &O, float V, OptVal Default,
+                       size_t GlobalWidth) const;
+
   // An out-of-line virtual method to provide a 'home' for this class.
   virtual void anchor();
 };
@@ -677,6 +853,9 @@
   // getValueName - Overload in subclass to provide a better default value.
   virtual const char *getValueName() const { return "string"; }
 
+  void printOptionDiff(const Option &O, StringRef V, OptVal Default,
+                       size_t GlobalWidth) const;
+
   // An out-of-line virtual method to provide a 'home' for this class.
   virtual void anchor();
 };
@@ -698,12 +877,63 @@
   // getValueName - Overload in subclass to provide a better default value.
   virtual const char *getValueName() const { return "char"; }
 
+  void printOptionDiff(const Option &O, char V, OptVal Default,
+                       size_t GlobalWidth) const;
+
   // An out-of-line virtual method to provide a 'home' for this class.
   virtual void anchor();
 };
 
 EXTERN_TEMPLATE_INSTANTIATION(class basic_parser<char>);
 
+//--------------------------------------------------
+// PrintOptionDiff
+//
+// This collection of wrappers is the intermediary between class opt and class
+// parser to handle all the template nastiness.
+
+// This overloaded function is selected by the generic parser.
+template<class ParserClass, class DT>
+void printOptionDiff(const Option &O, const generic_parser_base &P, const DT &V,
+                     const OptionValue<DT> &Default, size_t GlobalWidth) {
+  OptionValue<DT> OV = V;
+  P.printOptionDiff(O, OV, Default, GlobalWidth);
+}
+
+// This is instantiated for basic parsers when the parsed value has a different
+// type than the option value. e.g. HelpPrinter.
+template<class ParserDT, class ValDT>
+struct OptionDiffPrinter {
+  void print(const Option &O, const parser<ParserDT> P, const ValDT &V,
+             const OptionValue<ValDT> &Default, size_t GlobalWidth) {
+    P.printOptionNoValue(O, GlobalWidth);
+  }
+};
+
+// This is instantiated for basic parsers when the parsed value has the same
+// type as the option value.
+template<class DT>
+struct OptionDiffPrinter<DT, DT> {
+  void print(const Option &O, const parser<DT> P, const DT &V,
+             const OptionValue<DT> &Default, size_t GlobalWidth) {
+    P.printOptionDiff(O, V, Default, GlobalWidth);
+  }
+};
+
+// This overloaded function is selected by the basic parser, which may parse a
+// different type than the option type.
+template<class ParserClass, class ValDT>
+void printOptionDiff(
+  const Option &O,
+  const basic_parser<typename ParserClass::parser_data_type> &P,
+  const ValDT &V, const OptionValue<ValDT> &Default,
+  size_t GlobalWidth) {
+
+  OptionDiffPrinter<typename ParserClass::parser_data_type, ValDT> printer;
+  printer.print(O, static_cast<const ParserClass&>(P), V, Default,
+                GlobalWidth);
+}
+
 //===----------------------------------------------------------------------===//
 // applicator class - This class is used because we must use partial
 // specialization to handle literal string arguments specially (const char* does
@@ -753,7 +983,6 @@
   applicator<Mod>::opt(M, *O);
 }
 
-
 //===----------------------------------------------------------------------===//
 // opt_storage class
 
@@ -764,6 +993,7 @@
 template<class DataType, bool ExternalStorage, bool isClass>
 class opt_storage {
   DataType *Location;   // Where to store the object...
+  OptionValue<DataType> Default;
 
   void check() const {
     assert(Location != 0 && "cl::location(...) not specified for a command "
@@ -777,21 +1007,25 @@
     if (Location)
       return O.error("cl::location(x) specified more than once!");
     Location = &L;
+    Default = L;
     return false;
   }
 
   template<class T>
-  void setValue(const T &V) {
+  void setValue(const T &V, bool initial = false) {
     check();
     *Location = V;
+    if (initial)
+      Default = V;
   }
 
   DataType &getValue() { check(); return *Location; }
   const DataType &getValue() const { check(); return *Location; }
 
   operator DataType() const { return this->getValue(); }
-};
 
+  const OptionValue<DataType> &getDefault() const { return Default; }
+};
 
 // Define how to hold a class type object, such as a string.  Since we can
 // inherit from a class, we do so.  This makes us exactly compatible with the
@@ -800,11 +1034,19 @@
 template<class DataType>
 class opt_storage<DataType,false,true> : public DataType {
 public:
+  OptionValue<DataType> Default;
+
   template<class T>
-  void setValue(const T &V) { DataType::operator=(V); }
+  void setValue(const T &V, bool initial = false) {
+    DataType::operator=(V);
+    if (initial)
+      Default = V;
+  }
 
   DataType &getValue() { return *this; }
   const DataType &getValue() const { return *this; }
+
+  const OptionValue<DataType> &getDefault() const { return Default; }
 };
 
 // Define a partial specialization to handle things we cannot inherit from.  In
@@ -815,16 +1057,23 @@
 class opt_storage<DataType, false, false> {
 public:
   DataType Value;
+  OptionValue<DataType> Default;
 
   // Make sure we initialize the value with the default constructor for the
   // type.
   opt_storage() : Value(DataType()) {}
 
   template<class T>
-  void setValue(const T &V) { Value = V; }
+  void setValue(const T &V, bool initial = false) {
+    Value = V;
+    if (initial)
+      Default = V;
+  }
   DataType &getValue() { return Value; }
   DataType getValue() const { return Value; }
 
+  const OptionValue<DataType> &getDefault() const { return Default; }
+
   operator DataType() const { return getValue(); }
 
   // If the datatype is a pointer, support -> on it.
@@ -866,13 +1115,20 @@
     Parser.printOptionInfo(*this, GlobalWidth);
   }
 
+  virtual void printOptionValue(size_t GlobalWidth, bool Force) const {
+    if (Force || this->getDefault().compare(this->getValue())) {
+      cl::printOptionDiff<ParserClass>(
+        *this, Parser, this->getValue(), this->getDefault(), GlobalWidth);
+    }
+  }
+
   void done() {
     addArgument();
     Parser.initialize(*this);
   }
 public:
   // setInitialValue - Used by the cl::init modifier...
-  void setInitialValue(const DataType &V) { this->setValue(V); }
+  void setInitialValue(const DataType &V) { this->setValue(V, true); }
 
   ParserClass &getParser() { return Parser; }
 
@@ -1030,6 +1286,9 @@
     Parser.printOptionInfo(*this, GlobalWidth);
   }
 
+  // Unimplemented: list options don't currently store their default value.
+  virtual void printOptionValue(size_t GlobalWidth, bool Force) const {}
+
   void done() {
     addArgument();
     Parser.initialize(*this);
@@ -1229,6 +1488,9 @@
     Parser.printOptionInfo(*this, GlobalWidth);
   }
 
+  // Unimplemented: bits options don't currently store their default values.
+  virtual void printOptionValue(size_t GlobalWidth, bool Force) const {}
+
   void done() {
     addArgument();
     Parser.initialize(*this);
@@ -1320,6 +1582,9 @@
   virtual size_t getOptionWidth() const;
   virtual void printOptionInfo(size_t GlobalWidth) const;
 
+  // Aliases do not need to print their values.
+  virtual void printOptionValue(size_t GlobalWidth, bool Force) const {}
+
   void done() {
     if (!hasArgStr())
       error("cl::alias must have argument name specified!");

Modified: llvm/trunk/lib/Support/CommandLine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CommandLine.cpp?rev=128910&r1=128909&r2=128910&view=diff
==============================================================================
--- llvm/trunk/lib/Support/CommandLine.cpp (original)
+++ llvm/trunk/lib/Support/CommandLine.cpp Tue Apr  5 13:54:36 2011
@@ -908,8 +908,6 @@
   errs().indent(GlobalWidth-L-6) << " - " << HelpStr << "\n";
 }
 
-
-
 //===----------------------------------------------------------------------===//
 // Parser Implementation code...
 //
@@ -939,7 +937,11 @@
   outs().indent(GlobalWidth-getOptionWidth(O)) << " - " << O.HelpStr << '\n';
 }
 
-
+void basic_parser_impl::printOptionName(const Option &O,
+                                        size_t GlobalWidth) const {
+  outs() << "  -" << O.ArgStr;
+  outs().indent(GlobalWidth-std::strlen(O.ArgStr));
+}
 
 
 // parser<bool> implementation
@@ -1083,6 +1085,89 @@
   }
 }
 
+static const size_t MaxOptWidth = 8; // arbitrary spacing for printOptionDiff
+
+// printGenericOptionDiff - Print the value of this option and it's default.
+//
+// "Generic" options have each value mapped to a name.
+void generic_parser_base::
+printGenericOptionDiff(const Option &O, const GenericOptionValue &Value,
+                       const GenericOptionValue &Default,
+                       size_t GlobalWidth) const {
+  outs() << "  -" << O.ArgStr;
+  outs().indent(GlobalWidth-std::strlen(O.ArgStr));
+
+  unsigned NumOpts = getNumOptions();
+  for (unsigned i = 0; i != NumOpts; ++i) {
+    if (Value.compare(getOptionValue(i)))
+      continue;
+
+    outs() << "= " << getOption(i);
+    size_t L = std::strlen(getOption(i));
+    size_t NumSpaces = MaxOptWidth > L ? MaxOptWidth - L : 0;
+    outs().indent(NumSpaces) << " (default: ";
+    for (unsigned j = 0; j != NumOpts; ++j) {
+      if (Default.compare(getOptionValue(j)))
+        continue;
+      outs() << getOption(j);
+      break;
+    }
+    outs() << ")\n";
+    return;
+  }
+  outs() << "= *unknown option value*\n";
+}
+
+// printOptionDiff - Specializations for printing basic value types.
+//
+#define PRINT_OPT_DIFF(T)                                               \
+  void parser<T>::                                                      \
+  printOptionDiff(const Option &O, T V, OptionValue<T> D,               \
+                  size_t GlobalWidth) const {                           \
+    printOptionName(O, GlobalWidth);                                    \
+    std::string Str;                                                    \
+    {                                                                   \
+      raw_string_ostream SS(Str);                                       \
+      SS << V;                                                          \
+    }                                                                   \
+    outs() << "= " << Str;                                              \
+    size_t NumSpaces = MaxOptWidth > Str.size() ? MaxOptWidth - Str.size() : 0;\
+    outs().indent(NumSpaces) << " (default: ";                          \
+    if (D.hasValue())                                                   \
+      outs() << D.getValue();                                           \
+    else                                                                \
+      outs() << "*no default*";                                         \
+    outs() << ")\n";                                                    \
+  }                                                                     \
+
+PRINT_OPT_DIFF(bool);
+PRINT_OPT_DIFF(boolOrDefault);
+PRINT_OPT_DIFF(int);
+PRINT_OPT_DIFF(unsigned);
+PRINT_OPT_DIFF(double);
+PRINT_OPT_DIFF(float);
+PRINT_OPT_DIFF(char);
+
+void parser<std::string>::
+printOptionDiff(const Option &O, StringRef V, OptionValue<std::string> D,
+                size_t GlobalWidth) const {
+  printOptionName(O, GlobalWidth);
+  outs() << "= " << V;
+  size_t NumSpaces = MaxOptWidth > V.size() ? MaxOptWidth - V.size() : 0;
+  outs().indent(NumSpaces) << " (default: ";
+  if (D.hasValue())
+    outs() << D.getValue();
+  else
+    outs() << "*no default*";
+  outs() << ")\n";
+}
+
+// Print a placeholder for options that don't yet support printOptionDiff().
+void basic_parser_impl::
+printOptionNoValue(const Option &O, size_t GlobalWidth) const {
+  printOptionName(O, GlobalWidth);
+  outs() << "= *cannot print option value*\n";
+}
 
 //===----------------------------------------------------------------------===//
 // -help and -help-hidden option implementation
@@ -1094,6 +1179,35 @@
   return strcmp(((pair_ty*)LHS)->first, ((pair_ty*)RHS)->first);
 }
 
+// Copy Options into a vector so we can sort them as we like.
+static void
+sortOpts(StringMap<Option*> &OptMap,
+         SmallVectorImpl< std::pair<const char *, Option*> > &Opts,
+         bool ShowHidden) {
+  SmallPtrSet<Option*, 128> OptionSet;  // Duplicate option detection.
+
+  for (StringMap<Option*>::iterator I = OptMap.begin(), E = OptMap.end();
+       I != E; ++I) {
+    // Ignore really-hidden options.
+    if (I->second->getOptionHiddenFlag() == ReallyHidden)
+      continue;
+
+    // Unless showhidden is set, ignore hidden flags.
+    if (I->second->getOptionHiddenFlag() == Hidden && !ShowHidden)
+      continue;
+
+    // If we've already seen this option, don't add it to the list again.
+    if (!OptionSet.insert(I->second))
+      continue;
+
+    Opts.push_back(std::pair<const char *, Option*>(I->getKey().data(),
+                                                    I->second));
+  }
+
+  // Sort the options list alphabetically.
+  qsort(Opts.data(), Opts.size(), sizeof(Opts[0]), OptNameCompare);
+}
+
 namespace {
 
 class HelpPrinter {
@@ -1115,30 +1229,8 @@
     StringMap<Option*> OptMap;
     GetOptionInfo(PositionalOpts, SinkOpts, OptMap);
 
-    // Copy Options into a vector so we can sort them as we like.
     SmallVector<std::pair<const char *, Option*>, 128> Opts;
-    SmallPtrSet<Option*, 128> OptionSet;  // Duplicate option detection.
-
-    for (StringMap<Option*>::iterator I = OptMap.begin(), E = OptMap.end();
-         I != E; ++I) {
-      // Ignore really-hidden options.
-      if (I->second->getOptionHiddenFlag() == ReallyHidden)
-        continue;
-
-      // Unless showhidden is set, ignore hidden flags.
-      if (I->second->getOptionHiddenFlag() == Hidden && !ShowHidden)
-        continue;
-
-      // If we've already seen this option, don't add it to the list again.
-      if (!OptionSet.insert(I->second))
-        continue;
-
-      Opts.push_back(std::pair<const char *, Option*>(I->getKey().data(),
-                                                      I->second));
-    }
-
-    // Sort the options list alphabetically.
-    qsort(Opts.data(), Opts.size(), sizeof(Opts[0]), OptNameCompare);
+    sortOpts(OptMap, Opts, ShowHidden);
 
     if (ProgramOverview)
       outs() << "OVERVIEW: " << ProgramOverview << "\n";
@@ -1197,6 +1289,38 @@
 HHOp("help-hidden", cl::desc("Display all available options"),
      cl::location(HiddenPrinter), cl::Hidden, cl::ValueDisallowed);
 
+static cl::opt<bool>
+PrintOptions("print-options",
+             cl::desc("Print non-default options after command line parsing"),
+             cl::Hidden, cl::init(false));
+
+static cl::opt<bool>
+PrintAllOptions("print-all-options",
+                cl::desc("Print all option values after command line parsing"),
+                cl::Hidden, cl::init(false));
+
+// Print the value of each option.
+void cl::PrintOptionValues() {
+  if (!PrintOptions && !PrintAllOptions) return;
+
+  // Get all the options.
+  SmallVector<Option*, 4> PositionalOpts;
+  SmallVector<Option*, 4> SinkOpts;
+  StringMap<Option*> OptMap;
+  GetOptionInfo(PositionalOpts, SinkOpts, OptMap);
+
+  SmallVector<std::pair<const char *, Option*>, 128> Opts;
+  sortOpts(OptMap, Opts, /*ShowHidden*/true);
+
+  // Compute the maximum argument length...
+  size_t MaxArgLen = 0;
+  for (size_t i = 0, e = Opts.size(); i != e; ++i)
+    MaxArgLen = std::max(MaxArgLen, Opts[i].second->getOptionWidth());
+
+  for (size_t i = 0, e = Opts.size(); i != e; ++i)
+    Opts[i].second->printOptionValue(MaxArgLen, PrintAllOptions);
+}
+
 static void (*OverrideVersionPrinter)() = 0;
 
 static int TargetArraySortFn(const void *LHS, const void *RHS) {

Modified: llvm/trunk/tools/llc/llc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=128910&r1=128909&r2=128910&view=diff
==============================================================================
--- llvm/trunk/tools/llc/llc.cpp (original)
+++ llvm/trunk/tools/llc/llc.cpp Tue Apr  5 13:54:36 2011
@@ -338,6 +338,9 @@
       return 1;
     }
 
+    // Before executing passes, print the final values of the LLVM options.
+    cl::PrintOptionValues();
+
     PM.run(mod);
   }
 

Modified: llvm/trunk/tools/opt/opt.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/opt.cpp?rev=128910&r1=128909&r2=128910&view=diff
==============================================================================
--- llvm/trunk/tools/opt/opt.cpp (original)
+++ llvm/trunk/tools/opt/opt.cpp Tue Apr  5 13:54:36 2011
@@ -701,6 +701,9 @@
       Passes.add(createBitcodeWriterPass(Out->os()));
   }
 
+  // Before executing passes, print the final values of the LLVM options.
+  cl::PrintOptionValues();
+
   // Now that we have all of the passes ready, run them.
   Passes.run(*M.get());
 



From johnny.chen at apple.com  Tue Apr  5 14:09:07 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 12:09:07 -0700
Subject: [llvm-commits] [llvm] r128897 - in /llvm/trunk:
 lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
 test/MC/ARM/simple-encoding.ll test/MC/Disassembler/ARM/arm-tests.txt
In-Reply-To: <5CB8B13B-E6F1-4C6F-9DD8-2D3B3FE68C36@apple.com>
References: <20110405180246.D92582A6C12C@llvm.org>
	<5CB8B13B-E6F1-4C6F-9DD8-2D3B3FE68C36@apple.com>
Message-ID: <8E8EDE1F-0A82-4C29-BCB9-FBB0880F77C2@apple.com>

Fixed in http://llvm.org/viewvc/llvm-project?view=rev&revision=128906.
Sorry about that.
On Apr 5, 2011, at 11:54 AM, Bob Wilson wrote:

> This is breaking a bunch of tests for me:
> 
> Failing Tests (6):
>    LLVM :: CodeGen/ARM/constants.ll
>    LLVM :: CodeGen/ARM/fp.ll
>    LLVM :: CodeGen/ARM/long.ll
>    LLVM :: CodeGen/ARM/select-imm.ll
>    LLVM :: CodeGen/ARM/select_xform.ll
>    LLVM :: CodeGen/ARM/sub.ll
> 
> Please fix or revert ASAP.
> 
> On Apr 5, 2011, at 11:02 AM, Johnny Chen wrote:
> 
>> Author: johnny
>> Date: Tue Apr  5 13:02:46 2011
>> New Revision: 128897
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=128897&view=rev
>> Log:
>> Constants with multiple encodings (ARM):
>> An alternative syntax is available for a modified immediate constant that permits the programmer to specify
>> the encoding directly. In this syntax, #<const> is instead written as #<byte>,#<rot>, where:
>> 
>>   <byte> is the numeric value of abcdefgh, in the range 0-255
>>   <rot> is twice the numeric value of rotation, an even number in the range 0-30.
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>>   llvm/trunk/test/MC/ARM/simple-encoding.ll
>>   llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
>> 
>> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=128897&r1=128896&r2=128897&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Tue Apr  5 13:02:46 2011
>> @@ -136,9 +136,10 @@
>>  unsigned Rot = ARM_AM::getSOImmValRot(V);
>> 
>>  // Print low-level immediate formation info, per
>> -  // A5.1.3: "Data-processing operands - Immediate".
>> +  // A5.2.3: Data-processing (immediate), and
>> +  // A5.2.4: Modified immediate constants in ARM instructions
>>  if (Rot) {
>> -    O << "#" << Imm << ", " << Rot;
>> +    O << "#" << Imm << ", #" << Rot;
>>    // Pretty printed version.
>>    if (CommentStream)
>>      *CommentStream << (int)ARM_AM::rotr32(Imm, Rot) << "\n";
>> 
>> Modified: llvm/trunk/test/MC/ARM/simple-encoding.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/simple-encoding.ll?rev=128897&r1=128896&r2=128897&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/MC/ARM/simple-encoding.ll (original)
>> +++ llvm/trunk/test/MC/ARM/simple-encoding.ll Tue Apr  5 13:02:46 2011
>> @@ -39,7 +39,7 @@
>> 
>> define i32 @f4(i32 %a, i32 %b) {
>> ; CHECK: f4
>> -; CHECK: add r0, r0, #254, 28         @ encoding: [0xfe,0x0e,0x80,0xe2]
>> +; CHECK: add r0, r0, #254, #28        @ encoding: [0xfe,0x0e,0x80,0xe2]
>> ; CHECK:                              @ 4064
>> ; CHECK: bx lr                        @ encoding: [0x1e,0xff,0x2f,0xe1]
>>  %add = add nsw i32 %a, 4064
>> @@ -118,7 +118,7 @@
>> define i64 @f13() {
>> ; CHECK: f13:
>> ; CHECK: mvn r0, #0                   @ encoding: [0x00,0x00,0xe0,0xe3]
>> -; CHECK: mvn r1, #2, 2                @ encoding: [0x02,0x11,0xe0,0xe3]
>> +; CHECK: mvn r1, #2, #2               @ encoding: [0x02,0x11,0xe0,0xe3]
>>        ret i64 9223372036854775807
>> }
>> 
>> @@ -229,7 +229,7 @@
>> 
>> define void @f24(i32 %a) {
>> ; CHECK: f24
>> -; CHECK: cmp r0, #1, 16               @ encoding: [0x01,0x08,0x50,0xe3]
>> +; CHECK: cmp r0, #1, #16               @ encoding: [0x01,0x08,0x50,0xe3]
>>        %b = icmp ugt i32 %a, 65536
>>        br i1 %b, label %r, label %r
>> r:
>> 
>> Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=128897&r1=128896&r2=128897&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
>> +++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Tue Apr  5 13:02:46 2011
>> @@ -1,6 +1,6 @@
>> # RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 | FileCheck %s
>> 
>> -# CHECK:	addpl	r4, pc, #19, 8
>> +# CHECK:	addpl	r4, pc, #19, #8
>> 0x4c 0x45 0x8f 0x52
>> 
>> # CHECK:	b	#0
>> @@ -66,7 +66,7 @@
>> # CHECK:	movt	r8, #65535
>> 0xff 0x8f 0x4f 0xe3
>> 
>> -# CHECK:	mvnspl	r7, #245, 2
>> +# CHECK:	mvnspl	r7, #245, #2
>> 0xf5 0x71 0xf0 0x53
>> 
>> # CHECK-NOT:	orr	r7, r8, r7, rrx #0
>> @@ -143,7 +143,7 @@
>> # CHECK: msr cpsr_fc, r0
>> 0x00 0xf0 0x29 0xe1
>> 
>> -# CHECK:	msrmi	cpsr_c, #241, 8
>> +# CHECK:	msrmi	cpsr_c, #241, #8
>> 0xf1 0xf4 0x21 0x43
>> 
>> # CHECK: rsbs r6, r7, r8
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 


From atrick at apple.com  Tue Apr  5 14:13:11 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 05 Apr 2011 19:13:11 -0000
Subject: [llvm-commits] [llvm] r128912 -
	/llvm/trunk/include/llvm/Support/CommandLine.h
Message-ID: <20110405191311.3A6542A6C12C@llvm.org>

Author: atrick
Date: Tue Apr  5 14:13:11 2011
New Revision: 128912

URL: http://llvm.org/viewvc/llvm-project?rev=128912&view=rev
Log:
Fix a typo.

Modified:
    llvm/trunk/include/llvm/Support/CommandLine.h

Modified: llvm/trunk/include/llvm/Support/CommandLine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CommandLine.h?rev=128912&r1=128911&r2=128912&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CommandLine.h (original)
+++ llvm/trunk/include/llvm/Support/CommandLine.h Tue Apr  5 14:13:11 2011
@@ -365,7 +365,7 @@
   virtual bool compare(const GenericOptionValue &V) const {
     const OptionValueCopy<DataType> &VC =
       static_cast< const OptionValueCopy<DataType>& >(V);
-    if (!VC.hasValue) return false;
+    if (!VC.hasValue()) return false;
     return compare(VC.getValue());
   }
 };



From johnny.chen at apple.com  Tue Apr  5 14:42:11 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 19:42:11 -0000
Subject: [llvm-commits] [llvm] r128913 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
 test/MC/Disassembler/ARM/thumb-printf.txt
 test/MC/Disassembler/ARM/thumb-tests.txt
Message-ID: <20110405194211.728E72A6C12C@llvm.org>

Author: johnny
Date: Tue Apr  5 14:42:11 2011
New Revision: 128913

URL: http://llvm.org/viewvc/llvm-project?rev=128913&view=rev
Log:
ARM disassembler should flag (rGPRRegClassID, r13|r15) as an error.

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
    llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128913&r1=128912&r2=128913&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Apr  5 14:42:11 2011
@@ -82,8 +82,16 @@
 // FIXME: Auto-gened?
 static unsigned
 getRegisterEnum(BO B, unsigned RegClassID, unsigned RawRegister) {
-  // For this purpose, we can treat rGPR as if it were GPR.
-  if (RegClassID == ARM::rGPRRegClassID) RegClassID = ARM::GPRRegClassID;
+  if (RegClassID == ARM::rGPRRegClassID) {
+    // Check for The register numbers 13 and 15 that are not permitted for many
+    // Thumb register specifiers.
+    if (RawRegister == 13 || RawRegister == 15) {
+      B->SetErr(-1);
+      return 0;
+    }
+    // For this purpose, we can treat rGPR as if it were GPR.
+    RegClassID = ARM::GPRRegClassID;
+  }
 
   // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
   unsigned RegNum =

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt?rev=128913&r1=128912&r2=128913&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-printf.txt Tue Apr  5 14:42:11 2011
@@ -26,7 +26,8 @@
 # CHECK-NEXT:	mov	r2, r5
 # CHECK-NEXT:	ldr	r3, [sp]
 # CHECK-NEXT:	bl	#-8390
-# CHECK-NEXT:	sub.w	sp, r7, #8
+# Data bytes (corresponds to an invalid instruction)
+# But not:	sub.w	sp, r7, #8
 # CHECK-NEXT:	pop.w	{r4, r5, r7, lr}
 # CHECK-NEXT:	add	sp, #16
 # CHECK-NEXT:	bx	lr
@@ -63,7 +64,7 @@
 0x2a	0x46
 0x00	0x9b
 0xfd	0xf7	0x9d	0xff
-0xa7	0xf1	0x08	0x0d
+# 0xa7	0xf1	0x08	0x0d
 0xbd	0xe8	0xb0	0x40
 0x04	0xb0
 0x70	0x47

Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=128913&r1=128912&r2=128913&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Tue Apr  5 14:42:11 2011
@@ -42,8 +42,8 @@
 # CHECK:	ldrd	r0, r1, [r7, #64]!
 0xf7 0xe9 0x10 0x01
 
-# CHECK:	lsls.w	r0, pc, #1
-0x5f 0xea 0x4f 0x00
+# CHECK:	lsls.w	r0, r5, #1
+0x5f 0xea 0x45 0x00
 
 # CHECK:	mov	r11, r7
 0xbb 0x46



From rdivacky at freebsd.org  Tue Apr  5 15:14:21 2011
From: rdivacky at freebsd.org (Roman Divacky)
Date: Tue, 5 Apr 2011 22:14:21 +0200
Subject: [llvm-commits] [PATCH]: SandyBridge detection
Message-ID: <20110405201421.GA39134@freebsd.org>

ok to commit?

Index: lib/Support/Host.cpp
===================================================================
--- lib/Support/Host.cpp	(revision 128883)
+++ lib/Support/Host.cpp	(working copy)
@@ -214,6 +214,8 @@
                // As found in a Summer 2010 model iMac.
       case 37: // Intel Core i7, laptop version.
         return "corei7";
+      case 42: // SandyBridge
+        return "sandybridge";
 
       case 28: // Intel Atom processor. All processors are manufactured using
                // the 45 nm process

From dpatel at apple.com  Tue Apr  5 15:14:13 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 05 Apr 2011 20:14:13 -0000
Subject: [llvm-commits] [llvm] r128914 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20110405201413.D2D382A6C12C@llvm.org>

Author: dpatel
Date: Tue Apr  5 15:14:13 2011
New Revision: 128914

URL: http://llvm.org/viewvc/llvm-project?rev=128914&view=rev
Log:
Do not emit empty name.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=128914&r1=128913&r2=128914&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Apr  5 15:14:13 2011
@@ -1225,7 +1225,8 @@
 
   ParamDIE = new DIE(dwarf::DW_TAG_template_value_parameter);
   addType(ParamDIE, TPV.getType());
-  addString(ParamDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string, TPV.getName());
+  if (!TPV.getName().empty())
+    addString(ParamDIE, dwarf::DW_AT_name, dwarf::DW_FORM_string, TPV.getName());
   addUInt(ParamDIE, dwarf::DW_AT_const_value, dwarf::DW_FORM_udata, 
           TPV.getValue());
   return ParamDIE;



From clattner at apple.com  Tue Apr  5 15:23:54 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 05 Apr 2011 13:23:54 -0700
Subject: [llvm-commits] [PATCH]: SandyBridge detection
In-Reply-To: <20110405201421.GA39134@freebsd.org>
References: <20110405201421.GA39134@freebsd.org>
Message-ID: <AE14ABC6-06E6-483C-ACC4-AEFEDEF3540C@apple.com>

Yes, please do.

-Chris

On Apr 5, 2011, at 1:14 PM, Roman Divacky wrote:

> ok to commit?
> 
> Index: lib/Support/Host.cpp
> ===================================================================
> --- lib/Support/Host.cpp	(revision 128883)
> +++ lib/Support/Host.cpp	(working copy)
> @@ -214,6 +214,8 @@
>                // As found in a Summer 2010 model iMac.
>       case 37: // Intel Core i7, laptop version.
>         return "corei7";
> +      case 42: // SandyBridge
> +        return "sandybridge";
> 
>       case 28: // Intel Atom processor. All processors are manufactured using
>                // the 45 nm process
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From stoklund at 2pi.dk  Tue Apr  5 15:20:26 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 20:20:26 -0000
Subject: [llvm-commits] [llvm] r128918 - in /llvm/trunk:
 lib/CodeGen/LiveRangeEdit.cpp lib/CodeGen/LiveRangeEdit.h
 test/CodeGen/X86/constant-pool-remat-0.ll
Message-ID: <20110405202026.3D2B22A6C12D@llvm.org>

Author: stoklund
Date: Tue Apr  5 15:20:26 2011
New Revision: 128918

URL: http://llvm.org/viewvc/llvm-project?rev=128918&view=rev
Log:
When dead code elimination removes all but one use, try to fold the single def into the remaining use.

Rematerialization can leave single-use loads behind that we might as well fold whenever possible.

Modified:
    llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
    llvm/trunk/lib/CodeGen/LiveRangeEdit.h
    llvm/trunk/test/CodeGen/X86/constant-pool-remat-0.ll

Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp?rev=128918&r1=128917&r2=128918&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeEdit.cpp Tue Apr  5 15:20:26 2011
@@ -149,6 +149,54 @@
     LIS.removeInterval(Reg);
 }
 
+bool LiveRangeEdit::foldAsLoad(LiveInterval *LI,
+                               SmallVectorImpl<MachineInstr*> &Dead,
+                               MachineRegisterInfo &MRI,
+                               LiveIntervals &LIS,
+                               const TargetInstrInfo &TII) {
+  MachineInstr *DefMI = 0, *UseMI = 0;
+
+  // Check that there is a single def and a single use.
+  for (MachineRegisterInfo::reg_nodbg_iterator I = MRI.reg_nodbg_begin(LI->reg),
+       E = MRI.reg_nodbg_end(); I != E; ++I) {
+    MachineOperand &MO = I.getOperand();
+    MachineInstr *MI = MO.getParent();
+    if (MO.isDef()) {
+      if (DefMI && DefMI != MI)
+        return false;
+      if (!MI->getDesc().canFoldAsLoad())
+        return false;
+      DefMI = MI;
+    } else if (!MO.isUndef()) {
+      if (UseMI && UseMI != MI)
+        return false;
+      // FIXME: Targets don't know how to fold subreg uses.
+      if (MO.getSubReg())
+        return false;
+      UseMI = MI;
+    }
+  }
+  if (!DefMI || !UseMI)
+    return false;
+
+  DEBUG(dbgs() << "Try to fold single def: " << *DefMI
+               << "       into single use: " << *UseMI);
+
+  SmallVector<unsigned, 8> Ops;
+  if (UseMI->readsWritesVirtualRegister(LI->reg, &Ops).second)
+    return false;
+
+  MachineInstr *FoldMI = TII.foldMemoryOperand(UseMI, Ops, DefMI);
+  if (!FoldMI)
+    return false;
+  DEBUG(dbgs() << "                folded: " << *FoldMI);
+  LIS.ReplaceMachineInstrInMaps(UseMI, FoldMI);
+  UseMI->eraseFromParent();
+  DefMI->addRegisterDead(LI->reg, 0);
+  Dead.push_back(DefMI);
+  return true;
+}
+
 void LiveRangeEdit::eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
                                       LiveIntervals &LIS, VirtRegMap &VRM,
                                       const TargetInstrInfo &TII) {
@@ -218,6 +266,8 @@
     // Shrink just one live interval. Then delete new dead defs.
     LiveInterval *LI = ToShrink.back();
     ToShrink.pop_back();
+    if (foldAsLoad(LI, Dead, VRM.getRegInfo(), LIS, TII))
+      continue;
     if (delegate_)
       delegate_->LRE_WillShrinkVirtReg(LI->reg);
     if (!LIS.shrinkToUses(LI, &Dead))

Modified: llvm/trunk/lib/CodeGen/LiveRangeEdit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/LiveRangeEdit.h?rev=128918&r1=128917&r2=128918&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/LiveRangeEdit.h (original)
+++ llvm/trunk/lib/CodeGen/LiveRangeEdit.h Tue Apr  5 15:20:26 2011
@@ -80,6 +80,11 @@
   bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
                           SlotIndex UseIdx, LiveIntervals &lis);
 
+  /// foldAsLoad - If LI has a single use and a single def that can be folded as
+  /// a load, eliminate the register by folding the def into the use.
+  bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead,
+                  MachineRegisterInfo&, LiveIntervals&, const TargetInstrInfo&);
+
 public:
   /// Create a LiveRangeEdit for breaking down parent into smaller pieces.
   /// @param parent The register being spilled or split.

Modified: llvm/trunk/test/CodeGen/X86/constant-pool-remat-0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/constant-pool-remat-0.ll?rev=128918&r1=128917&r2=128918&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/constant-pool-remat-0.ll (original)
+++ llvm/trunk/test/CodeGen/X86/constant-pool-remat-0.ll Tue Apr  5 15:20:26 2011
@@ -1,4 +1,5 @@
 ; RUN: llc < %s -mtriple=x86_64-linux   | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-linux -regalloc=greedy | FileCheck %s
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s
 ; CHECK:     LCPI
 ; CHECK:     LCPI



From stoklund at 2pi.dk  Tue Apr  5 15:20:30 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 20:20:30 -0000
Subject: [llvm-commits] [llvm] r128919 - in /llvm/trunk/test/CodeGen/X86:
 2008-02-22-ReMatBug.ll 2008-03-18-CoalescerBug.ll
 2008-09-18-inline-asm-2.ll 2009-03-16-SpillerBug.ll
 2010-02-19-TailCallRetAddrBug.ll 2010-04-23-mmx-movdq2q.ll
 2010-05-03-CoalescerSubRegClobber.ll 2010-09-17-SideEffectsInChain.ll
 abi-isel.ll
Message-ID: <20110405202030.78AD22A6C12E@llvm.org>

Author: stoklund
Date: Tue Apr  5 15:20:30 2011
New Revision: 128919

URL: http://llvm.org/viewvc/llvm-project?rev=128919&view=rev
Log:
Fix one more batch of X86 tests to be register allocation dependent.

Modified:
    llvm/trunk/test/CodeGen/X86/2008-02-22-ReMatBug.ll
    llvm/trunk/test/CodeGen/X86/2008-03-18-CoalescerBug.ll
    llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
    llvm/trunk/test/CodeGen/X86/2009-03-16-SpillerBug.ll
    llvm/trunk/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll
    llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll
    llvm/trunk/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll
    llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll
    llvm/trunk/test/CodeGen/X86/abi-isel.ll

Modified: llvm/trunk/test/CodeGen/X86/2008-02-22-ReMatBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-02-22-ReMatBug.ll?rev=128919&r1=128918&r2=128919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-02-22-ReMatBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-02-22-ReMatBug.ll Tue Apr  5 15:20:30 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86 -stats |& grep {Number of re-materialization} | grep 2
+; RUN: llc < %s -march=x86 -stats -regalloc=linearscan |& grep {Number of re-materialization} | grep 2
 ; rdar://5761454
 
 	%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }

Modified: llvm/trunk/test/CodeGen/X86/2008-03-18-CoalescerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-03-18-CoalescerBug.ll?rev=128919&r1=128918&r2=128919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-03-18-CoalescerBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-03-18-CoalescerBug.ll Tue Apr  5 15:20:30 2011
@@ -1,5 +1,5 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim | grep movss | count 1
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -stats |& grep {Number of re-materialization} | grep 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -regalloc=linearscan | grep movss | count 1
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -disable-fp-elim -regalloc=linearscan -stats |& grep {Number of re-materialization} | grep 1
 
 	%struct..0objc_object = type opaque
 	%struct.OhBoy = type {  }

Modified: llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll?rev=128919&r1=128918&r2=128919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll Tue Apr  5 15:20:30 2011
@@ -1,5 +1,7 @@
-; RUN: llc < %s -march=x86 | grep "#%ebp %edi %ebx 8(%esi) %eax %dl"
-; RUN: llc < %s -march=x86 -regalloc=fast  | grep "#%ebx %esi %edi 8(%ebp) %eax %dl"
+; RUN: llc < %s -march=x86 -regalloc=linearscan | grep "#%ebp %edi %ebx 8(%esi) %eax %dl"
+; RUN: llc < %s -march=x86 -regalloc=fast       | grep "#%ebx %esi %edi 8(%ebp) %eax %dl"
+; RUN: llc < %s -march=x86 -regalloc=basic      | grep "#%ebp %esi %edx 8(%edi) %eax %bl"
+; RUN: llc < %s -march=x86 -regalloc=greedy     | grep "#%edx %edi %ebp 8(%esi) %eax %bl"
 
 ; The 1st, 2nd, 3rd and 5th registers above must all be different.  The registers
 ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th

Modified: llvm/trunk/test/CodeGen/X86/2009-03-16-SpillerBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2009-03-16-SpillerBug.ll?rev=128919&r1=128918&r2=128919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2009-03-16-SpillerBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2009-03-16-SpillerBug.ll Tue Apr  5 15:20:30 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -stats |& grep virtregrewriter | not grep {stores unfolded}
+; RUN: llc < %s -mtriple=i386-apple-darwin -regalloc=linearscan -stats |& grep virtregrewriter | not grep {stores unfolded}
 ; rdar://6682365
 
 ; Do not clobber a register if another spill slot is available in it and it's marked "do not clobber".

Modified: llvm/trunk/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll?rev=128919&r1=128918&r2=128919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll Tue Apr  5 15:20:30 2011
@@ -11,7 +11,7 @@
 ; Move return address (76(%esp)) to a temporary register (%ebp)
 ; CHECK: movl 76(%esp), [[REGISTER:%[a-z]+]]
 ; Overwrite return addresss
-; CHECK: movl %ebx, 76(%esp)
+; CHECK: movl [[EBX:%[a-z]+]], 76(%esp)
 ; Move return address from temporary register (%ebp) to new stack location (60(%esp))
 ; CHECK: movl [[REGISTER]], 60(%esp)
 

Modified: llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll?rev=128919&r1=128918&r2=128919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-04-23-mmx-movdq2q.ll Tue Apr  5 15:20:30 2011
@@ -31,18 +31,19 @@
         ret void
 }
 
+; CHECK: ti64
 define void @ti64(double %a, double %b) nounwind {
 entry:
         %tmp1 = bitcast double %a to <1 x i64>
         %tmp2 = bitcast double %b to <1 x i64>
         %tmp3 = add <1 x i64> %tmp1, %tmp2
-; CHECK:  addq  %rax, %rcx
+; CHECK:  addq
         store <1 x i64> %tmp3, <1 x i64>* null
         ret void
 }
 
 ; MMX intrinsics calls get us MMX instructions.
-
+; CHECK: ti8a
 define void @ti8a(double %a, double %b) nounwind {
 entry:
         %tmp1 = bitcast double %a to x86_mmx

Modified: llvm/trunk/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll?rev=128919&r1=128918&r2=128919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-05-03-CoalescerSubRegClobber.ll Tue Apr  5 15:20:30 2011
@@ -22,8 +22,8 @@
   %conv = zext i32 %v to i64                      ; <i64> [#uses=1]
   %conv14 = zext i32 %div11 to i64                ; <i64> [#uses=1]
 ; Verify that we don't clobber %eax after putting the imulq result in %rax
-; CHECK: imulq	%r{{.}}x, %r[[RES:.]]x
-; CHECK-NOT: movl	{{.*}}, %e[[RES]]x
+; CHECK: imulq	%r{{.}}x, %r[[RES:..]]
+; CHECK-NOT: movl	{{.*}}, %e[[RES]]
 ; CHECK: div
   %mul = mul i64 %conv14, %conv                   ; <i64> [#uses=1]
   %conv16 = zext i32 %div to i64                  ; <i64> [#uses=1]

Modified: llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll?rev=128919&r1=128918&r2=128919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-09-17-SideEffectsInChain.ll Tue Apr  5 15:20:30 2011
@@ -19,8 +19,8 @@
 }
 
 ; CHECK: movq	___stack_chk_guard at GOTPCREL(%rip), %rax
-; CHECK: movb   38(%rsp), %bl
-; CHECK: movb   8(%rsp), %dl
-; CHECK: movb   %dl, 8(%rsp)
-; CHECK: movb   %bl, 38(%rsp)
+; CHECK: movb   38(%rsp), [[R0:%.+]]
+; CHECK: movb   8(%rsp), [[R1:%.+]]
+; CHECK: movb   [[R1]], 8(%rsp)
+; CHECK: movb   [[R0]], 38(%rsp)
 ; CHECK: callq	___stack_chk_fail

Modified: llvm/trunk/test/CodeGen/X86/abi-isel.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/abi-isel.ll?rev=128919&r1=128918&r2=128919&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/abi-isel.ll (original)
+++ llvm/trunk/test/CodeGen/X86/abi-isel.ll Tue Apr  5 15:20:30 2011
@@ -12,6 +12,17 @@
 ; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC
 ; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC
 
+; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-STATIC
+; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-PIC
+; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-64-STATIC
+; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=LINUX-64-PIC
+; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-32-STATIC
+; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC
+; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-PIC
+; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-64-STATIC
+; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC
+; RUN: llc < %s -asm-verbose=0 -regalloc=basic -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC
+
 @src = external global [131072 x i32]
 @dst = external global [131072 x i32]
 @xsrc = external global [32 x i32]
@@ -38,68 +49,68 @@
 	ret void
 
 ; LINUX-64-STATIC: foo00:
-; LINUX-64-STATIC: movl	src(%rip), %eax
-; LINUX-64-STATIC: movl	%eax, dst
+; LINUX-64-STATIC: movl	src(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl	[[EAX]], dst
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: foo00:
-; LINUX-32-STATIC: 	movl	src, %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, dst
+; LINUX-32-STATIC: 	movl	src, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dst
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: foo00:
-; LINUX-32-PIC: 	movl	src, %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, dst
+; LINUX-32-PIC: 	movl	src, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dst
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: foo00:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r..]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e..]]
+; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), [[RCX:%r..]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _foo00:
-; DARWIN-32-STATIC: 	movl	_src, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _dst
+; DARWIN-32-STATIC: 	movl	_src, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _dst
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _foo00:
-; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, [[EAX:%e..]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EAX]]), [[EAX:%e..]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, [[ECX:%e..]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo00:
 ; DARWIN-32-PIC: 	calll	L0$pb
 ; DARWIN-32-PIC-NEXT: L0$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L0$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L0$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L0$pb([[EAX]]), [[ECX:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	([[ECX]]), [[ECX:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L0$pb([[EAX]]), [[EAX:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _foo00:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r..]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]]), [[EAX:%e..]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r..]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _foo00:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r..]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]]), [[EAX:%e..]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r..]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _foo00:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r..]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e..]]
+; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r..]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -110,68 +121,68 @@
 	ret void
 
 ; LINUX-64-STATIC: fxo00:
-; LINUX-64-STATIC: movl	xsrc(%rip), %eax
-; LINUX-64-STATIC: movl	%eax, xdst
+; LINUX-64-STATIC: movl	xsrc(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl	[[EAX]], xdst
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: fxo00:
-; LINUX-32-STATIC: 	movl	xsrc, %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, xdst
+; LINUX-32-STATIC: 	movl	xsrc, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], xdst
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: fxo00:
-; LINUX-32-PIC: 	movl	xsrc, %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, xdst
+; LINUX-32-PIC: 	movl	xsrc, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], xdst
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: fxo00:
-; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	xdst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _fxo00:
-; DARWIN-32-STATIC: 	movl	_xsrc, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _xdst
+; DARWIN-32-STATIC: 	movl	_xsrc, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _xdst
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _fxo00:
-; DARWIN-32-DYNAMIC: 	movl	L_xsrc$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_xsrc$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _fxo00:
 ; DARWIN-32-PIC: 	calll	L1$pb
 ; DARWIN-32-PIC-NEXT: L1$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L1$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L1$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L1$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L1$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _fxo00:
-; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _fxo00:
-; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _fxo00:
-; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -192,9 +203,9 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: foo01:
-; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _foo01:
@@ -202,36 +213,36 @@
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _foo01:
-; DARWIN-32-DYNAMIC: 	movl	L_dst$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_dst$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo01:
 ; DARWIN-32-PIC: 	calll	L2$pb
 ; DARWIN-32-PIC-NEXT: L2$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L2$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L2$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L2$pb(
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L2$pb(
+; DARWIN-32-PIC-NEXT: 	movl
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _foo01:
-; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _foo01:
-; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _foo01:
-; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -252,9 +263,9 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: fxo01:
-; LINUX-64-PIC: 	movq	xdst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movq	xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _fxo01:
@@ -262,36 +273,36 @@
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _fxo01:
-; DARWIN-32-DYNAMIC: 	movl	L_xdst$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_xdst$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _fxo01:
 ; DARWIN-32-PIC: 	calll	L3$pb
 ; DARWIN-32-PIC-NEXT: L3$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L3$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L3$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[R0:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L3$pb([[R0]]), [[R1:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L3$pb([[R0]]), [[R2:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	[[R1:%e..]], ([[R2]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _fxo01:
-; DARWIN-64-STATIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-STATIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _fxo01:
-; DARWIN-64-DYNAMIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _fxo01:
-; DARWIN-64-PIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-PIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -308,72 +319,72 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: foo02:
-; LINUX-32-STATIC: 	movl	src, %eax
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%eax, (%ecx)
+; LINUX-32-STATIC: 	movl	src, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: foo02:
-; LINUX-32-PIC: 	movl	src, %eax
-; LINUX-32-PIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-PIC-NEXT: 	movl	%eax, (%ecx)
+; LINUX-32-PIC: 	movl	src, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: foo02:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _foo02:
-; DARWIN-32-STATIC: 	movl	_src, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-STATIC: 	movl	_src, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _foo02:
-; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%ecx), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo02:
 ; DARWIN-32-PIC: 	calll	L4$pb
 ; DARWIN-32-PIC-NEXT: L4$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L4$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L4$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[R0:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L4$pb([[R0]]), [[R1:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	([[R1]]), [[R2:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L4$pb([[R0]]), [[R3:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	([[R3]]), [[R4:%e..]]
+; DARWIN-32-PIC-NEXT: 	movl	[[R2]], ([[R4]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _foo02:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _foo02:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _foo02:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -389,73 +400,73 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: fxo02:
-; LINUX-32-STATIC: 	movl	xsrc, %eax
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%eax, (%ecx)
+; LINUX-32-STATIC: 	movl	xsrc, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
 ; LINUX-32-PIC: fxo02:
-; LINUX-32-PIC: 	movl	xsrc, %eax
-; LINUX-32-PIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-PIC-NEXT: 	movl	%eax, (%ecx)
+; LINUX-32-PIC: 	movl	xsrc, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: fxo02:
-; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _fxo02:
-; DARWIN-32-STATIC: 	movl	_xsrc, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-STATIC: 	movl	_xsrc, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _fxo02:
-; DARWIN-32-DYNAMIC: 	movl	L_xsrc$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%ecx), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_xsrc$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _fxo02:
 ; DARWIN-32-PIC: 	calll	L5$pb
 ; DARWIN-32-PIC-NEXT: L5$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L5$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L5$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L5$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L5$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _fxo02:
-; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _fxo02:
-; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _fxo02:
-; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -465,58 +476,58 @@
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 0), align 32
 	ret void
 ; LINUX-64-STATIC: foo03:
-; LINUX-64-STATIC: movl    dsrc(%rip), %eax
-; LINUX-64-STATIC: movl    %eax, ddst
+; LINUX-64-STATIC: movl    dsrc(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ddst
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: foo03:
-; LINUX-32-STATIC: 	movl	dsrc, %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, ddst
+; LINUX-32-STATIC: 	movl	dsrc, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ddst
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: foo03:
-; LINUX-32-PIC: 	movl	dsrc, %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, ddst
+; LINUX-32-PIC: 	movl	dsrc, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ddst
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: foo03:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _foo03:
-; DARWIN-32-STATIC: 	movl	_dsrc, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _ddst
+; DARWIN-32-STATIC: 	movl	_dsrc, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _ddst
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _foo03:
-; DARWIN-32-DYNAMIC: 	movl	_dsrc, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _ddst
+; DARWIN-32-DYNAMIC: 	movl	_dsrc, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _ddst
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo03:
 ; DARWIN-32-PIC: 	calll	L6$pb
 ; DARWIN-32-PIC-NEXT: L6$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	_dsrc-L6$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _ddst-L6$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dsrc-L6$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _ddst-L6$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _foo03:
-; DARWIN-64-STATIC: 	movl	_dsrc(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, _ddst(%rip)
+; DARWIN-64-STATIC: 	movl	_dsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], _ddst(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _foo03:
-; DARWIN-64-DYNAMIC: 	movl	_dsrc(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, _ddst(%rip)
+; DARWIN-64-DYNAMIC: 	movl	_dsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], _ddst(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _foo03:
-; DARWIN-64-PIC: 	movl	_dsrc(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movl	%eax, _ddst(%rip)
+; DARWIN-64-PIC: 	movl	_dsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], _ddst(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -537,9 +548,9 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: foo04:
-; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _foo04:
@@ -553,24 +564,24 @@
 ; DARWIN-32-PIC: _foo04:
 ; DARWIN-32-PIC: 	calll	L7$pb
 ; DARWIN-32-PIC-NEXT: L7$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_ddst-L7$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _dptr-L7$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_ddst-L7$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _dptr-L7$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _foo04:
-; DARWIN-64-STATIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _foo04:
-; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _foo04:
-; DARWIN-64-PIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -587,62 +598,62 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: foo05:
-; LINUX-32-STATIC: 	movl	dsrc, %eax
-; LINUX-32-STATIC-NEXT: 	movl	dptr, %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%eax, (%ecx)
+; LINUX-32-STATIC: 	movl	dsrc, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: foo05:
-; LINUX-32-PIC: 	movl	dsrc, %eax
-; LINUX-32-PIC-NEXT: 	movl	dptr, %ecx
-; LINUX-32-PIC-NEXT: 	movl	%eax, (%ecx)
+; LINUX-32-PIC: 	movl	dsrc, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: foo05:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _foo05:
-; DARWIN-32-STATIC: 	movl	_dsrc, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_dptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-STATIC: 	movl	_dsrc, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _foo05:
-; DARWIN-32-DYNAMIC: 	movl	_dsrc, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	_dsrc, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo05:
 ; DARWIN-32-PIC: 	calll	L8$pb
 ; DARWIN-32-PIC-NEXT: L8$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	_dsrc-L8$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_dptr-L8$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dsrc-L8$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dptr-L8$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _foo05:
-; DARWIN-64-STATIC: 	movl	_dsrc(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-STATIC: 	movl	_dsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _foo05:
-; DARWIN-64-DYNAMIC: 	movl	_dsrc(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movl	_dsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _foo05:
-; DARWIN-64-PIC: 	movl	_dsrc(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-PIC: 	movl	_dsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -652,56 +663,56 @@
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 0), align 4
 	ret void
 ; LINUX-64-STATIC: foo06:
-; LINUX-64-STATIC: movl    lsrc(%rip), %eax
-; LINUX-64-STATIC: movl    %eax, ldst(%rip)
+; LINUX-64-STATIC: movl    lsrc(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ldst(%rip)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: foo06:
-; LINUX-32-STATIC: 	movl	lsrc, %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, ldst
+; LINUX-32-STATIC: 	movl	lsrc, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ldst
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: foo06:
-; LINUX-32-PIC: 	movl	lsrc, %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, ldst
+; LINUX-32-PIC: 	movl	lsrc, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ldst
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: foo06:
-; LINUX-64-PIC: 	movl	lsrc(%rip), %eax
-; LINUX-64-PIC-NEXT: 	movl	%eax, ldst(%rip)
+; LINUX-64-PIC: 	movl	lsrc(%rip), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ldst(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _foo06:
-; DARWIN-32-STATIC: 	movl	_lsrc, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _ldst
+; DARWIN-32-STATIC: 	movl	_lsrc, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _ldst
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _foo06:
-; DARWIN-32-DYNAMIC: 	movl	_lsrc, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _ldst
+; DARWIN-32-DYNAMIC: 	movl	_lsrc, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _ldst
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo06:
 ; DARWIN-32-PIC: 	calll	L9$pb
 ; DARWIN-32-PIC-NEXT: L9$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	_lsrc-L9$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _ldst-L9$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lsrc-L9$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _ldst-L9$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _foo06:
-; DARWIN-64-STATIC: 	movl	_lsrc(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, _ldst(%rip)
+; DARWIN-64-STATIC: 	movl	_lsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], _ldst(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _foo06:
-; DARWIN-64-DYNAMIC: 	movl	_lsrc(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, _ldst(%rip)
+; DARWIN-64-DYNAMIC: 	movl	_lsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], _ldst(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _foo06:
-; DARWIN-64-PIC: 	movl	_lsrc(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movl	%eax, _ldst(%rip)
+; DARWIN-64-PIC: 	movl	_lsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], _ldst(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -722,8 +733,8 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: foo07:
-; LINUX-64-PIC: 	leaq	ldst(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	%rax, lptr(%rip)
+; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _foo07:
@@ -737,24 +748,24 @@
 ; DARWIN-32-PIC: _foo07:
 ; DARWIN-32-PIC: 	calll	L10$pb
 ; DARWIN-32-PIC-NEXT: L10$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_ldst-L10$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _lptr-L10$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_ldst-L10$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _lptr-L10$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _foo07:
-; DARWIN-64-STATIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _foo07:
-; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _foo07:
-; DARWIN-64-PIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -771,60 +782,60 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: foo08:
-; LINUX-32-STATIC: 	movl	lsrc, %eax
-; LINUX-32-STATIC-NEXT: 	movl	lptr, %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%eax, (%ecx)
+; LINUX-32-STATIC: 	movl	lsrc, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: foo08:
-; LINUX-32-PIC: 	movl	lsrc, %eax
-; LINUX-32-PIC-NEXT: 	movl	lptr, %ecx
-; LINUX-32-PIC-NEXT: 	movl	%eax, (%ecx)
+; LINUX-32-PIC: 	movl	lsrc, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: foo08:
-; LINUX-64-PIC: 	movl	lsrc(%rip), %eax
-; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; LINUX-64-PIC: 	movl	lsrc(%rip), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _foo08:
-; DARWIN-32-STATIC: 	movl	_lsrc, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_lptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-STATIC: 	movl	_lsrc, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _foo08:
-; DARWIN-32-DYNAMIC: 	movl	_lsrc, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	_lsrc, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _foo08:
 ; DARWIN-32-PIC: 	calll	L11$pb
 ; DARWIN-32-PIC-NEXT: L11$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	_lsrc-L11$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_lptr-L11$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lsrc-L11$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lptr-L11$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _foo08:
-; DARWIN-64-STATIC: 	movl	_lsrc(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-STATIC: 	movl	_lsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _foo08:
-; DARWIN-64-DYNAMIC: 	movl	_lsrc(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movl	_lsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _foo08:
-; DARWIN-64-PIC: 	movl	_lsrc(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx)
+; DARWIN-64-PIC: 	movl	_lsrc(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -834,68 +845,68 @@
 	store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), align 4
 	ret void
 ; LINUX-64-STATIC: qux00:
-; LINUX-64-STATIC: movl    src+64(%rip), %eax
-; LINUX-64-STATIC: movl    %eax, dst+64(%rip)
+; LINUX-64-STATIC: movl    src+64(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], dst+64(%rip)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: qux00:
-; LINUX-32-STATIC: 	movl	src+64, %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, dst+64
+; LINUX-32-STATIC: 	movl	src+64, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: qux00:
-; LINUX-32-PIC: 	movl	src+64, %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, dst+64
+; LINUX-32-PIC: 	movl	src+64, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qux00:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qux00:
-; DARWIN-32-STATIC: 	movl	_src+64, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _dst+64
+; DARWIN-32-STATIC: 	movl	_src+64, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _dst+64
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _qux00:
-; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	64(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, 64(%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	64([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux00:
 ; DARWIN-32-PIC: 	calll	L12$pb
 ; DARWIN-32-PIC-NEXT: L12$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L12$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	64(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L12$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L12$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	64([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L12$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], 64([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qux00:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qux00:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qux00:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -905,68 +916,68 @@
 	store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), align 4
 	ret void
 ; LINUX-64-STATIC: qxx00:
-; LINUX-64-STATIC: movl    xsrc+64(%rip), %eax
-; LINUX-64-STATIC: movl    %eax, xdst+64(%rip)
+; LINUX-64-STATIC: movl    xsrc+64(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], xdst+64(%rip)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: qxx00:
-; LINUX-32-STATIC: 	movl	xsrc+64, %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, xdst+64
+; LINUX-32-STATIC: 	movl	xsrc+64, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], xdst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: qxx00:
-; LINUX-32-PIC: 	movl	xsrc+64, %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, xdst+64
+; LINUX-32-PIC: 	movl	xsrc+64, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], xdst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qxx00:
-; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	xdst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qxx00:
-; DARWIN-32-STATIC: 	movl	_xsrc+64, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _xdst+64
+; DARWIN-32-STATIC: 	movl	_xsrc+64, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _xdst+64
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _qxx00:
-; DARWIN-32-DYNAMIC: 	movl	L_xsrc$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	64(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, 64(%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_xsrc$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	64([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qxx00:
 ; DARWIN-32-PIC: 	calll	L13$pb
 ; DARWIN-32-PIC-NEXT: L13$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L13$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	64(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L13$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L13$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	64([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L13$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], 64([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qxx00:
-; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qxx00:
-; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qxx00:
-; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -987,10 +998,10 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qux01:
-; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	addq	$64, %rax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	addq	$64, [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qux01:
@@ -998,41 +1009,41 @@
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _qux01:
-; DARWIN-32-DYNAMIC: 	movl	L_dst$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	addl	$64, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_dst$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	addl	$64, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux01:
 ; DARWIN-32-PIC: 	calll	L14$pb
 ; DARWIN-32-PIC-NEXT: L14$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L14$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	addl	$64, %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L14$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L14$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	addl	$64, [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L14$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qux01:
-; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	addq	$64, %rax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	addq	$64, [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qux01:
-; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	addq	$64, %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	addq	$64, [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qux01:
-; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	addq	$64, %rax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	addq	$64, [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1053,10 +1064,10 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qxx01:
-; LINUX-64-PIC: 	movq	xdst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	addq	$64, %rax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movq	xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	addq	$64, [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qxx01:
@@ -1064,41 +1075,41 @@
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _qxx01:
-; DARWIN-32-DYNAMIC: 	movl	L_xdst$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	addl	$64, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_xdst$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	addl	$64, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qxx01:
 ; DARWIN-32-PIC: 	calll	L15$pb
 ; DARWIN-32-PIC-NEXT: L15$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L15$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	addl	$64, %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L15$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L15$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	addl	$64, [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L15$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qxx01:
-; DARWIN-64-STATIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	addq	$64, %rax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-STATIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	addq	$64, [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qxx01:
-; DARWIN-64-DYNAMIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	addq	$64, %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	addq	$64, [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qxx01:
-; DARWIN-64-PIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	addq	$64, %rax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-PIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	addq	$64, [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1109,79 +1120,79 @@
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
 ; LINUX-64-STATIC: qux02:
-; LINUX-64-STATIC: movl    src+64(%rip), %eax
-; LINUX-64-STATIC: movq    ptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 64(%rcx)
+; LINUX-64-STATIC: movl    src+64(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: qux02:
-; LINUX-32-STATIC: 	movl	src+64, %eax
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%eax, 64(%ecx)
+; LINUX-32-STATIC: 	movl	src+64, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
 ; LINUX-32-PIC: qux02:
-; LINUX-32-PIC: 	movl	src+64, %eax
-; LINUX-32-PIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-PIC-NEXT: 	movl	%eax, 64(%ecx)
+; LINUX-32-PIC: 	movl	src+64, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qux02:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qux02:
-; DARWIN-32-STATIC: 	movl	_src+64, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, 64(%ecx)
+; DARWIN-32-STATIC: 	movl	_src+64, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _qux02:
-; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	64(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%ecx), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, 64(%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	64([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux02:
 ; DARWIN-32-PIC: 	calll	L16$pb
 ; DARWIN-32-PIC-NEXT: L16$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L16$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	64(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L16$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L16$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	64([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L16$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], 64([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qux02:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qux02:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qux02:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1192,79 +1203,79 @@
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
 ; LINUX-64-STATIC: qxx02:
-; LINUX-64-STATIC: movl    xsrc+64(%rip), %eax
-; LINUX-64-STATIC: movq    ptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 64(%rcx)
+; LINUX-64-STATIC: movl    xsrc+64(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: qxx02:
-; LINUX-32-STATIC: 	movl	xsrc+64, %eax
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%eax, 64(%ecx)
+; LINUX-32-STATIC: 	movl	xsrc+64, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
 ; LINUX-32-PIC: qxx02:
-; LINUX-32-PIC: 	movl	xsrc+64, %eax
-; LINUX-32-PIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-PIC-NEXT: 	movl	%eax, 64(%ecx)
+; LINUX-32-PIC: 	movl	xsrc+64, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qxx02:
-; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qxx02:
-; DARWIN-32-STATIC: 	movl	_xsrc+64, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, 64(%ecx)
+; DARWIN-32-STATIC: 	movl	_xsrc+64, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _qxx02:
-; DARWIN-32-DYNAMIC: 	movl	L_xsrc$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	64(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%ecx), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, 64(%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_xsrc$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	64([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qxx02:
 ; DARWIN-32-PIC: 	calll	L17$pb
 ; DARWIN-32-PIC-NEXT: L17$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L17$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	64(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L17$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L17$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	64([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L17$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], 64([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qxx02:
-; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qxx02:
-; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qxx02:
-; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1274,58 +1285,58 @@
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), align 32
 	ret void
 ; LINUX-64-STATIC: qux03:
-; LINUX-64-STATIC: movl    dsrc+64(%rip), %eax
-; LINUX-64-STATIC: movl    %eax, ddst+64(%rip)
+; LINUX-64-STATIC: movl    dsrc+64(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ddst+64(%rip)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: qux03:
-; LINUX-32-STATIC: 	movl	dsrc+64, %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, ddst+64
+; LINUX-32-STATIC: 	movl	dsrc+64, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ddst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: qux03:
-; LINUX-32-PIC: 	movl	dsrc+64, %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, ddst+64
+; LINUX-32-PIC: 	movl	dsrc+64, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ddst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qux03:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qux03:
-; DARWIN-32-STATIC: 	movl	_dsrc+64, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _ddst+64
+; DARWIN-32-STATIC: 	movl	_dsrc+64, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _ddst+64
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _qux03:
-; DARWIN-32-DYNAMIC: 	movl	_dsrc+64, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _ddst+64
+; DARWIN-32-DYNAMIC: 	movl	_dsrc+64, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _ddst+64
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux03:
 ; DARWIN-32-PIC: 	calll	L18$pb
 ; DARWIN-32-PIC-NEXT: L18$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L18$pb)+64(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (_ddst-L18$pb)+64(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L18$pb)+64([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], (_ddst-L18$pb)+64([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qux03:
-; DARWIN-64-STATIC: 	movl	_dsrc+64(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, _ddst+64(%rip)
+; DARWIN-64-STATIC: 	movl	_dsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], _ddst+64(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qux03:
-; DARWIN-64-DYNAMIC: 	movl	_dsrc+64(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, _ddst+64(%rip)
+; DARWIN-64-DYNAMIC: 	movl	_dsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], _ddst+64(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qux03:
-; DARWIN-64-PIC: 	movl	_dsrc+64(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movl	%eax, _ddst+64(%rip)
+; DARWIN-64-PIC: 	movl	_dsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], _ddst+64(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1346,10 +1357,10 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qux04:
-; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	addq	$64, %rax
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	addq	$64, [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qux04:
@@ -1363,24 +1374,24 @@
 ; DARWIN-32-PIC: _qux04:
 ; DARWIN-32-PIC: 	calll	L19$pb
 ; DARWIN-32-PIC-NEXT: L19$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L19$pb)+64(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _dptr-L19$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L19$pb)+64([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _dptr-L19$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qux04:
-; DARWIN-64-STATIC: 	leaq	_ddst+64(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ddst+64(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qux04:
-; DARWIN-64-DYNAMIC: 	leaq	_ddst+64(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ddst+64(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qux04:
-; DARWIN-64-PIC: 	leaq	_ddst+64(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ddst+64(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1391,69 +1402,69 @@
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
 ; LINUX-64-STATIC: qux05:
-; LINUX-64-STATIC: movl    dsrc+64(%rip), %eax
-; LINUX-64-STATIC: movq    dptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 64(%rcx)
+; LINUX-64-STATIC: movl    dsrc+64(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: qux05:
-; LINUX-32-STATIC: 	movl	dsrc+64, %eax
-; LINUX-32-STATIC-NEXT: 	movl	dptr, %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%eax, 64(%ecx)
+; LINUX-32-STATIC: 	movl	dsrc+64, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
 ; LINUX-32-PIC: qux05:
-; LINUX-32-PIC: 	movl	dsrc+64, %eax
-; LINUX-32-PIC-NEXT: 	movl	dptr, %ecx
-; LINUX-32-PIC-NEXT: 	movl	%eax, 64(%ecx)
+; LINUX-32-PIC: 	movl	dsrc+64, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qux05:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qux05:
-; DARWIN-32-STATIC: 	movl	_dsrc+64, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_dptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, 64(%ecx)
+; DARWIN-32-STATIC: 	movl	_dsrc+64, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _qux05:
-; DARWIN-32-DYNAMIC: 	movl	_dsrc+64, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, 64(%ecx)
+; DARWIN-32-DYNAMIC: 	movl	_dsrc+64, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux05:
 ; DARWIN-32-PIC: 	calll	L20$pb
 ; DARWIN-32-PIC-NEXT: L20$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L20$pb)+64(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_dptr-L20$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L20$pb)+64([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dptr-L20$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], 64([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qux05:
-; DARWIN-64-STATIC: 	movl	_dsrc+64(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-STATIC: 	movl	_dsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qux05:
-; DARWIN-64-DYNAMIC: 	movl	_dsrc+64(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-DYNAMIC: 	movl	_dsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qux05:
-; DARWIN-64-PIC: 	movl	_dsrc+64(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-PIC: 	movl	_dsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1463,56 +1474,56 @@
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), align 4
 	ret void
 ; LINUX-64-STATIC: qux06:
-; LINUX-64-STATIC: movl    lsrc+64(%rip), %eax
-; LINUX-64-STATIC: movl    %eax, ldst+64
+; LINUX-64-STATIC: movl    lsrc+64(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ldst+64
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: qux06:
-; LINUX-32-STATIC: 	movl	lsrc+64, %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, ldst+64
+; LINUX-32-STATIC: 	movl	lsrc+64, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ldst+64
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: qux06:
-; LINUX-32-PIC: 	movl	lsrc+64, %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, ldst+64
+; LINUX-32-PIC: 	movl	lsrc+64, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ldst+64
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qux06:
-; LINUX-64-PIC: 	movl	lsrc+64(%rip), %eax
-; LINUX-64-PIC-NEXT: 	movl	%eax, ldst+64(%rip)
+; LINUX-64-PIC: 	movl	lsrc+64(%rip), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ldst+64(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qux06:
-; DARWIN-32-STATIC: 	movl	_lsrc+64, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _ldst+64
+; DARWIN-32-STATIC: 	movl	_lsrc+64, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _ldst+64
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _qux06:
-; DARWIN-32-DYNAMIC: 	movl	_lsrc+64, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _ldst+64
+; DARWIN-32-DYNAMIC: 	movl	_lsrc+64, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _ldst+64
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux06:
 ; DARWIN-32-PIC: 	calll	L21$pb
 ; DARWIN-32-PIC-NEXT: L21$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L21$pb)+64(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (_ldst-L21$pb)+64(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L21$pb)+64([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], (_ldst-L21$pb)+64([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qux06:
-; DARWIN-64-STATIC: 	movl	_lsrc+64(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, _ldst+64(%rip)
+; DARWIN-64-STATIC: 	movl	_lsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], _ldst+64(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qux06:
-; DARWIN-64-DYNAMIC: 	movl	_lsrc+64(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, _ldst+64(%rip)
+; DARWIN-64-DYNAMIC: 	movl	_lsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], _ldst+64(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qux06:
-; DARWIN-64-PIC: 	movl	_lsrc+64(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movl	%eax, _ldst+64(%rip)
+; DARWIN-64-PIC: 	movl	_lsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], _ldst+64(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1533,8 +1544,8 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qux07:
-; LINUX-64-PIC: 	leaq	ldst+64(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	%rax, lptr(%rip)
+; LINUX-64-PIC: 	leaq	ldst+64(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qux07:
@@ -1548,24 +1559,24 @@
 ; DARWIN-32-PIC: _qux07:
 ; DARWIN-32-PIC: 	calll	L22$pb
 ; DARWIN-32-PIC-NEXT: L22$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L22$pb)+64(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _lptr-L22$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L22$pb)+64([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _lptr-L22$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qux07:
-; DARWIN-64-STATIC: 	leaq	_ldst+64(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ldst+64(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qux07:
-; DARWIN-64-DYNAMIC: 	leaq	_ldst+64(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ldst+64(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qux07:
-; DARWIN-64-PIC: 	leaq	_ldst+64(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ldst+64(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1576,67 +1587,67 @@
 	%2 = getelementptr i32* %0, i64 16
 	store i32 %1, i32* %2, align 4
 ; LINUX-64-STATIC: qux08:
-; LINUX-64-STATIC: movl    lsrc+64(%rip), %eax
-; LINUX-64-STATIC: movq    lptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 64(%rcx)
+; LINUX-64-STATIC: movl    lsrc+64(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]])
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: qux08:
-; LINUX-32-STATIC: 	movl	lsrc+64, %eax
-; LINUX-32-STATIC-NEXT: 	movl	lptr, %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%eax, 64(%ecx)
+; LINUX-32-STATIC: 	movl	lsrc+64, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 	ret void
 
 ; LINUX-32-PIC: qux08:
-; LINUX-32-PIC: 	movl	lsrc+64, %eax
-; LINUX-32-PIC-NEXT: 	movl	lptr, %ecx
-; LINUX-32-PIC-NEXT: 	movl	%eax, 64(%ecx)
+; LINUX-32-PIC: 	movl	lsrc+64, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: qux08:
-; LINUX-64-PIC: 	movl	lsrc+64(%rip), %eax
-; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; LINUX-64-PIC: 	movl	lsrc+64(%rip), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _qux08:
-; DARWIN-32-STATIC: 	movl	_lsrc+64, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_lptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, 64(%ecx)
+; DARWIN-32-STATIC: 	movl	_lsrc+64, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _qux08:
-; DARWIN-32-DYNAMIC: 	movl	_lsrc+64, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, 64(%ecx)
+; DARWIN-32-DYNAMIC: 	movl	_lsrc+64, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _qux08:
 ; DARWIN-32-PIC: 	calll	L23$pb
 ; DARWIN-32-PIC-NEXT: L23$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L23$pb)+64(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_lptr-L23$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, 64(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L23$pb)+64([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lptr-L23$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], 64([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _qux08:
-; DARWIN-64-STATIC: 	movl	_lsrc+64(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-STATIC: 	movl	_lsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _qux08:
-; DARWIN-64-DYNAMIC: 	movl	_lsrc+64(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-DYNAMIC: 	movl	_lsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _qux08:
-; DARWIN-64-PIC: 	movl	_lsrc+64(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx)
+; DARWIN-64-PIC: 	movl	_lsrc+64(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1648,73 +1659,73 @@
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC: ind00:
-; LINUX-64-STATIC: movl    src(,%rdi,4), %eax
-; LINUX-64-STATIC: movl    %eax, dst(,%rdi,4)
+; LINUX-64-STATIC: movl    src(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], dst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ind00:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	src(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, dst(,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], dst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ind00:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	src(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, dst(,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], dst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ind00:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ind00:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_src(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, _dst(,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_src(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], _dst(,[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ind00:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%ecx,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[ECX]],[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind00:
 ; DARWIN-32-PIC: 	calll	L24$pb
 ; DARWIN-32-PIC-NEXT: L24$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L24$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	movl	(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L24$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L24$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EDX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L24$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], ([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ind00:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ind00:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ind00:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1726,73 +1737,73 @@
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC: ixd00:
-; LINUX-64-STATIC: movl    xsrc(,%rdi,4), %eax
-; LINUX-64-STATIC: movl    %eax, xdst(,%rdi,4)
+; LINUX-64-STATIC: movl    xsrc(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], xdst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ixd00:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	xsrc(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, xdst(,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], xdst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ixd00:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	xsrc(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, xdst(,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], xdst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ixd00:
-; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	xdst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ixd00:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_xsrc(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, _xdst(,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_xsrc(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], _xdst(,[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ixd00:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%ecx,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[ECX]],[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ixd00:
 ; DARWIN-32-PIC: 	calll	L25$pb
 ; DARWIN-32-PIC-NEXT: L25$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L25$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	movl	(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L25$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L25$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EDX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L25$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], ([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ixd00:
-; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ixd00:
-; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ixd00:
-; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1802,73 +1813,73 @@
 	store i32* %0, i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC: ind01:
-; LINUX-64-STATIC: leaq    dst(,%rdi,4), %rax
-; LINUX-64-STATIC: movq    %rax, ptr
+; LINUX-64-STATIC: leaq    dst(,%rdi,4), [[RAX:%r.x]]
+; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ind01:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	dst(,%eax,4), %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, ptr
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	dst(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ind01:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	dst(,%eax,4), %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, ptr
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	dst(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ind01:
 ; LINUX-64-PIC: 	shlq	$2, %rdi
 ; LINUX-64-PIC-NEXT: 	addq	dst at GOTPCREL(%rip), %rdi
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	%rdi, (%rax)
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	%rdi, ([[RAX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ind01:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_dst(,%eax,4), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _ptr
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_dst(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _ptr
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ind01:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	shll	$2, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	addl	L_dst$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	shll	$2, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	addl	L_dst$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind01:
 ; DARWIN-32-PIC: 	calll	L26$pb
 ; DARWIN-32-PIC-NEXT: L26$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	shll	$2, %ecx
-; DARWIN-32-PIC-NEXT: 	addl	L_dst$non_lazy_ptr-L26$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L26$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	shll	$2, [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	addl	L_dst$non_lazy_ptr-L26$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L26$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ind01:
 ; DARWIN-64-STATIC: 	shlq	$2, %rdi
 ; DARWIN-64-STATIC-NEXT: 	addq	_dst at GOTPCREL(%rip), %rdi
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rdi, (%rax)
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	%rdi, ([[RAX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ind01:
 ; DARWIN-64-DYNAMIC: 	shlq	$2, %rdi
 ; DARWIN-64-DYNAMIC-NEXT: 	addq	_dst at GOTPCREL(%rip), %rdi
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rdi, (%rax)
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	%rdi, ([[RAX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ind01:
 ; DARWIN-64-PIC: 	shlq	$2, %rdi
 ; DARWIN-64-PIC-NEXT: 	addq	_dst at GOTPCREL(%rip), %rdi
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rdi, (%rax)
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	%rdi, ([[RAX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1878,73 +1889,73 @@
 	store i32* %0, i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC: ixd01:
-; LINUX-64-STATIC: leaq    xdst(,%rdi,4), %rax
-; LINUX-64-STATIC: movq    %rax, ptr
+; LINUX-64-STATIC: leaq    xdst(,%rdi,4), [[RAX:%r.x]]
+; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ixd01:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	xdst(,%eax,4), %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, ptr
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	xdst(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ixd01:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	xdst(,%eax,4), %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, ptr
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	xdst(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ixd01:
 ; LINUX-64-PIC: 	shlq	$2, %rdi
 ; LINUX-64-PIC-NEXT: 	addq	xdst at GOTPCREL(%rip), %rdi
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	%rdi, (%rax)
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	%rdi, ([[RAX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ixd01:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_xdst(,%eax,4), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _ptr
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_xdst(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _ptr
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ixd01:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	shll	$2, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	addl	L_xdst$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	shll	$2, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	addl	L_xdst$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ixd01:
 ; DARWIN-32-PIC: 	calll	L27$pb
 ; DARWIN-32-PIC-NEXT: L27$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	shll	$2, %ecx
-; DARWIN-32-PIC-NEXT: 	addl	L_xdst$non_lazy_ptr-L27$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L27$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	shll	$2, [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	addl	L_xdst$non_lazy_ptr-L27$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L27$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ixd01:
 ; DARWIN-64-STATIC: 	shlq	$2, %rdi
 ; DARWIN-64-STATIC-NEXT: 	addq	_xdst at GOTPCREL(%rip), %rdi
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rdi, (%rax)
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	%rdi, ([[RAX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ixd01:
 ; DARWIN-64-DYNAMIC: 	shlq	$2, %rdi
 ; DARWIN-64-DYNAMIC-NEXT: 	addq	_xdst at GOTPCREL(%rip), %rdi
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rdi, (%rax)
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	%rdi, ([[RAX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ixd01:
 ; DARWIN-64-PIC: 	shlq	$2, %rdi
 ; DARWIN-64-PIC-NEXT: 	addq	_xdst at GOTPCREL(%rip), %rdi
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rdi, (%rax)
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	%rdi, ([[RAX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -1957,83 +1968,83 @@
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC: ind02:
-; LINUX-64-STATIC: movl    src(,%rdi,4), %eax
-; LINUX-64-STATIC: movq    ptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, (%rcx,%rdi,4)
+; LINUX-64-STATIC: movl    src(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ind02:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	src(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %edx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ind02:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	src(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	ptr, %edx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	src(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ind02:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ind02:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_src(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %edx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_src(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[EDX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ind02:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%ecx,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%edx), %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[ECX]],[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EDX]]), [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind02:
 ; DARWIN-32-PIC: 	calll	L28$pb
 ; DARWIN-32-PIC-NEXT: L28$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L28$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	movl	(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L28$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L28$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EDX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L28$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], ([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ind02:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ind02:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ind02:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2046,83 +2057,83 @@
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC: ixd02:
-; LINUX-64-STATIC: movl    xsrc(,%rdi,4), %eax
-; LINUX-64-STATIC: movq    ptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, (%rcx,%rdi,4)
+; LINUX-64-STATIC: movl    xsrc(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ixd02:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	xsrc(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %edx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ixd02:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	xsrc(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	ptr, %edx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	xsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ixd02:
-; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ixd02:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_xsrc(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %edx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_xsrc(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[EDX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ixd02:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%ecx,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%edx), %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[ECX]],[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EDX]]), [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ixd02:
 ; DARWIN-32-PIC: 	calll	L29$pb
 ; DARWIN-32-PIC-NEXT: L29$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L29$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	movl	(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L29$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L29$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EDX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L29$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], ([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ixd02:
-; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ixd02:
-; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ixd02:
-; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2134,69 +2145,69 @@
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC: ind03:
-; LINUX-64-STATIC: movl    dsrc(,%rdi,4), %eax
-; LINUX-64-STATIC: movl    %eax, ddst(,%rdi,4)
+; LINUX-64-STATIC: movl    dsrc(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ddst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ind03:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	dsrc(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, ddst(,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ddst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ind03:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	dsrc(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, ddst(,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ddst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ind03:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ind03:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_dsrc(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, _ddst(,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dsrc(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], _ddst(,[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ind03:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, _ddst(,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], _ddst(,[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind03:
 ; DARWIN-32-PIC: 	calll	L30$pb
 ; DARWIN-32-PIC-NEXT: L30$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_dsrc-L30$pb(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	%edx, _ddst-L30$pb(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dsrc-L30$pb([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], _ddst-L30$pb([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ind03:
-; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	leaq	_ddst(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	_ddst(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ind03:
-; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ddst(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ddst(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ind03:
-; DARWIN-64-PIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	leaq	_ddst(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	_ddst(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2206,66 +2217,66 @@
 	store i32* %0, i32** @dptr, align 8
 	ret void
 ; LINUX-64-STATIC: ind04:
-; LINUX-64-STATIC: leaq    ddst(,%rdi,4), %rax
-; LINUX-64-STATIC: movq    %rax, dptr
+; LINUX-64-STATIC: leaq    ddst(,%rdi,4), [[RAX:%r.x]]
+; LINUX-64-STATIC: movq    [[RAX]], dptr
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ind04:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	ddst(,%eax,4), %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, dptr
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	ddst(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ind04:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	ddst(,%eax,4), %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, dptr
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	ddst(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ind04:
 ; LINUX-64-PIC: 	shlq	$2, %rdi
 ; LINUX-64-PIC-NEXT: 	addq	ddst at GOTPCREL(%rip), %rdi
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	%rdi, (%rax)
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	%rdi, ([[RAX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ind04:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_ddst(,%eax,4), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _dptr
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_ddst(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _dptr
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ind04:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_ddst(,%eax,4), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _dptr
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_ddst(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _dptr
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind04:
 ; DARWIN-32-PIC: 	calll	L31$pb
 ; DARWIN-32-PIC-NEXT: L31$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	_ddst-L31$pb(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _dptr-L31$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_ddst-L31$pb([[EAX]],[[ECX]],4), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _dptr-L31$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ind04:
-; DARWIN-64-STATIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	(%rax,%rdi,4), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ind04:
-; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	(%rax,%rdi,4), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ind04:
-; DARWIN-64-PIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	(%rax,%rdi,4), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2278,76 +2289,76 @@
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC: ind05:
-; LINUX-64-STATIC: movl    dsrc(,%rdi,4), %eax
-; LINUX-64-STATIC: movq    dptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, (%rcx,%rdi,4)
+; LINUX-64-STATIC: movl    dsrc(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ind05:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	dsrc(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	dptr, %edx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ind05:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	dsrc(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	dptr, %edx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ind05:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ind05:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_dsrc(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	_dptr, %edx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dsrc(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dptr, [[EDX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ind05:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind05:
 ; DARWIN-32-PIC: 	calll	L32$pb
 ; DARWIN-32-PIC-NEXT: L32$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_dsrc-L32$pb(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	_dptr-L32$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dsrc-L32$pb([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dptr-L32$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], ([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ind05:
-; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ind05:
-; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ind05:
-; DARWIN-64-PIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2359,69 +2370,69 @@
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC: ind06:
-; LINUX-64-STATIC: movl    lsrc(,%rdi,4), %eax
-; LINUX-64-STATIC: movl    %eax, ldst(,%rdi,4)
+; LINUX-64-STATIC: movl    lsrc(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ldst(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ind06:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	lsrc(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, ldst(,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ldst(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ind06:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	lsrc(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, ldst(,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ldst(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ind06:
-; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ind06:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_lsrc(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, _ldst(,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lsrc(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], _ldst(,[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ind06:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, _ldst(,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], _ldst(,[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind06:
 ; DARWIN-32-PIC: 	calll	L33$pb
 ; DARWIN-32-PIC-NEXT: L33$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_lsrc-L33$pb(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	%edx, _ldst-L33$pb(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lsrc-L33$pb([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], _ldst-L33$pb([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ind06:
-; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	leaq	_ldst(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	_ldst(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ind06:
-; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ldst(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ldst(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ind06:
-; DARWIN-64-PIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	leaq	_ldst(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	_ldst(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2431,65 +2442,65 @@
 	store i32* %0, i32** @lptr, align 8
 	ret void
 ; LINUX-64-STATIC: ind07:
-; LINUX-64-STATIC: leaq    ldst(,%rdi,4), %rax
-; LINUX-64-STATIC: movq    %rax, lptr
+; LINUX-64-STATIC: leaq    ldst(,%rdi,4), [[RAX:%r.x]]
+; LINUX-64-STATIC: movq    [[RAX]], lptr
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ind07:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	ldst(,%eax,4), %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, lptr
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	ldst(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ind07:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	ldst(,%eax,4), %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, lptr
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	ldst(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ind07:
-; LINUX-64-PIC: 	leaq	ldst(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	(%rax,%rdi,4), %rax
-; LINUX-64-PIC-NEXT: 	movq	%rax, lptr(%rip)
+; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	([[RAX]],%rdi,4), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ind07:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_ldst(,%eax,4), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _lptr
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_ldst(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _lptr
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ind07:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_ldst(,%eax,4), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _lptr
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_ldst(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _lptr
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind07:
 ; DARWIN-32-PIC: 	calll	L34$pb
 ; DARWIN-32-PIC-NEXT: L34$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	_ldst-L34$pb(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _lptr-L34$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_ldst-L34$pb([[EAX]],[[ECX]],4), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _lptr-L34$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ind07:
-; DARWIN-64-STATIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	(%rax,%rdi,4), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ind07:
-; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	(%rax,%rdi,4), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ind07:
-; DARWIN-64-PIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	(%rax,%rdi,4), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2502,75 +2513,75 @@
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC: ind08:
-; LINUX-64-STATIC: movl    lsrc(,%rdi,4), %eax
-; LINUX-64-STATIC: movq    lptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, (%rcx,%rdi,4)
+; LINUX-64-STATIC: movl    lsrc(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: ind08:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	lsrc(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	lptr, %edx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: ind08:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	lsrc(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	lptr, %edx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lsrc(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: ind08:
-; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _ind08:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_lsrc(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	_lptr, %edx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lsrc(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lptr, [[EDX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _ind08:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, (%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], ([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _ind08:
 ; DARWIN-32-PIC: 	calll	L35$pb
 ; DARWIN-32-PIC-NEXT: L35$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_lsrc-L35$pb(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	_lptr-L35$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, (%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lsrc-L35$pb([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lptr-L35$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], ([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _ind08:
-; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _ind08:
-; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _ind08:
-; DARWIN-64-PIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, (%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], ([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2583,73 +2594,73 @@
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC: off00:
-; LINUX-64-STATIC: movl    src+64(,%rdi,4), %eax
-; LINUX-64-STATIC: movl    %eax, dst+64(,%rdi,4)
+; LINUX-64-STATIC: movl    src+64(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], dst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: off00:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	src+64(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, dst+64(,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], dst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: off00:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	src+64(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, dst+64(,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], dst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: off00:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _off00:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_src+64(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, _dst+64(,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_src+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], _dst+64(,[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _off00:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	64(%ecx,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	64([[ECX]],[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off00:
 ; DARWIN-32-PIC: 	calll	L36$pb
 ; DARWIN-32-PIC-NEXT: L36$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L36$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	movl	64(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L36$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L36$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	64([[EDX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L36$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], 64([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _off00:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _off00:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _off00:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2662,73 +2673,73 @@
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC: oxf00:
-; LINUX-64-STATIC: movl    xsrc+64(,%rdi,4), %eax
-; LINUX-64-STATIC: movl    %eax, xdst+64(,%rdi,4)
+; LINUX-64-STATIC: movl    xsrc+64(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], xdst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: oxf00:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	xsrc+64(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, xdst+64(,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], xdst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: oxf00:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	xsrc+64(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, xdst+64(,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], xdst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: oxf00:
-; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	xdst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _oxf00:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_xsrc+64(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, _xdst+64(,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], _xdst+64(,[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _oxf00:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	64(%ecx,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	64([[ECX]],[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _oxf00:
 ; DARWIN-32-PIC: 	calll	L37$pb
 ; DARWIN-32-PIC-NEXT: L37$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L37$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	movl	64(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L37$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L37$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	64([[EDX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L37$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], 64([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _oxf00:
-; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _oxf00:
-; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _oxf00:
-; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_xdst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2739,73 +2750,73 @@
 	store i32* %0, i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC: off01:
-; LINUX-64-STATIC: leaq    dst+64(,%rdi,4), %rax
-; LINUX-64-STATIC: movq    %rax, ptr
+; LINUX-64-STATIC: leaq    dst+64(,%rdi,4), [[RAX:%r.x]]
+; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: off01:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	dst+64(,%eax,4), %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, ptr
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	dst+64(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: off01:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	dst+64(,%eax,4), %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, ptr
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	dst+64(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: off01:
-; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _off01:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_dst+64(,%eax,4), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _ptr
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_dst+64(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _ptr
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _off01:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off01:
 ; DARWIN-32-PIC: 	calll	L38$pb
 ; DARWIN-32-PIC-NEXT: L38$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L38$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	leal	64(%edx,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L38$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L38$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	64([[EDX]],[[ECX]],4), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L38$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _off01:
-; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _off01:
-; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _off01:
-; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2816,73 +2827,73 @@
 	store i32* %0, i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC: oxf01:
-; LINUX-64-STATIC: leaq    xdst+64(,%rdi,4), %rax
-; LINUX-64-STATIC: movq    %rax, ptr
+; LINUX-64-STATIC: leaq    xdst+64(,%rdi,4), [[RAX:%r.x]]
+; LINUX-64-STATIC: movq    [[RAX]], ptr
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: oxf01:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	xdst+64(,%eax,4), %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, ptr
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	xdst+64(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: oxf01:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	xdst+64(,%eax,4), %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, ptr
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	xdst+64(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: oxf01:
-; LINUX-64-PIC: 	movq	xdst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movq	xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _oxf01:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_xdst+64(,%eax,4), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _ptr
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_xdst+64(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _ptr
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _oxf01:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _oxf01:
 ; DARWIN-32-PIC: 	calll	L39$pb
 ; DARWIN-32-PIC-NEXT: L39$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L39$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	leal	64(%edx,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L39$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L39$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	64([[EDX]],[[ECX]],4), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L39$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _oxf01:
-; DARWIN-64-STATIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-STATIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _oxf01:
-; DARWIN-64-DYNAMIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _oxf01:
-; DARWIN-64-PIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-PIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2896,83 +2907,83 @@
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC: off02:
-; LINUX-64-STATIC: movl    src+64(,%rdi,4), %eax
-; LINUX-64-STATIC: movq    ptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 64(%rcx,%rdi,4)
+; LINUX-64-STATIC: movl    src+64(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: off02:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	src+64(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %edx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: off02:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	src+64(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	ptr, %edx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	src+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: off02:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _off02:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_src+64(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %edx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_src+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[EDX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _off02:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	64(%ecx,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%edx), %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	64([[ECX]],[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EDX]]), [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off02:
 ; DARWIN-32-PIC: 	calll	L40$pb
 ; DARWIN-32-PIC-NEXT: L40$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L40$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	movl	64(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L40$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L40$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	64([[EDX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L40$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], 64([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _off02:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _off02:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _off02:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -2986,83 +2997,83 @@
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC: oxf02:
-; LINUX-64-STATIC: movl    xsrc+64(,%rdi,4), %eax
-; LINUX-64-STATIC: movq    ptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 64(%rcx,%rdi,4)
+; LINUX-64-STATIC: movl    xsrc+64(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: oxf02:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	xsrc+64(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %edx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: oxf02:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	xsrc+64(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	ptr, %edx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: oxf02:
-; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _oxf02:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_xsrc+64(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %edx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[EDX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _oxf02:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	64(%ecx,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%edx), %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	64([[ECX]],[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EDX]]), [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _oxf02:
 ; DARWIN-32-PIC: 	calll	L41$pb
 ; DARWIN-32-PIC-NEXT: L41$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L41$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	movl	64(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L41$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L41$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	64([[EDX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L41$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], 64([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _oxf02:
-; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _oxf02:
-; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _oxf02:
-; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3075,69 +3086,69 @@
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC: off03:
-; LINUX-64-STATIC: movl    dsrc+64(,%rdi,4), %eax
-; LINUX-64-STATIC: movl    %eax, ddst+64(,%rdi,4)
+; LINUX-64-STATIC: movl    dsrc+64(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ddst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: off03:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	dsrc+64(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, ddst+64(,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ddst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: off03:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	dsrc+64(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, ddst+64(,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ddst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: off03:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _off03:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_dsrc+64(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, _ddst+64(,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], _ddst+64(,[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _off03:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc+64(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, _ddst+64(,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], _ddst+64(,[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off03:
 ; DARWIN-32-PIC: 	calll	L42$pb
 ; DARWIN-32-PIC-NEXT: L42$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L42$pb)+64(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	%edx, (_ddst-L42$pb)+64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L42$pb)+64([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], (_ddst-L42$pb)+64([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _off03:
-; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	leaq	_ddst(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	_ddst(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _off03:
-; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ddst(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ddst(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _off03:
-; DARWIN-64-PIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	leaq	_ddst(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	_ddst(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3148,66 +3159,66 @@
 	store i32* %0, i32** @dptr, align 8
 	ret void
 ; LINUX-64-STATIC: off04:
-; LINUX-64-STATIC: leaq    ddst+64(,%rdi,4), %rax
-; LINUX-64-STATIC: movq    %rax, dptr
+; LINUX-64-STATIC: leaq    ddst+64(,%rdi,4), [[RAX:%r.x]]
+; LINUX-64-STATIC: movq    [[RAX]], dptr
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: off04:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	ddst+64(,%eax,4), %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, dptr
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	ddst+64(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: off04:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	ddst+64(,%eax,4), %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, dptr
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	ddst+64(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: off04:
-; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _off04:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_ddst+64(,%eax,4), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _dptr
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_ddst+64(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _dptr
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _off04:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_ddst+64(,%eax,4), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _dptr
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_ddst+64(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _dptr
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off04:
 ; DARWIN-32-PIC: 	calll	L43$pb
 ; DARWIN-32-PIC-NEXT: L43$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L43$pb)+64(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _dptr-L43$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L43$pb)+64([[EAX]],[[ECX]],4), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _dptr-L43$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _off04:
-; DARWIN-64-STATIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _off04:
-; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _off04:
-; DARWIN-64-PIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3221,76 +3232,76 @@
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC: off05:
-; LINUX-64-STATIC: movl    dsrc+64(,%rdi,4), %eax
-; LINUX-64-STATIC: movq    dptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 64(%rcx,%rdi,4)
+; LINUX-64-STATIC: movl    dsrc+64(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: off05:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	dsrc+64(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	dptr, %edx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: off05:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	dsrc+64(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	dptr, %edx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: off05:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _off05:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_dsrc+64(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	_dptr, %edx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dptr, [[EDX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _off05:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc+64(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off05:
 ; DARWIN-32-PIC: 	calll	L44$pb
 ; DARWIN-32-PIC-NEXT: L44$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L44$pb)+64(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	_dptr-L44$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L44$pb)+64([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dptr-L44$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], 64([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _off05:
-; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _off05:
-; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _off05:
-; DARWIN-64-PIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3303,69 +3314,69 @@
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC: off06:
-; LINUX-64-STATIC: movl    lsrc+64(,%rdi,4), %eax
-; LINUX-64-STATIC: movl    %eax, ldst+64(,%rdi,4)
+; LINUX-64-STATIC: movl    lsrc+64(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ldst+64(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: off06:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	lsrc+64(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, ldst+64(,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ldst+64(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: off06:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	lsrc+64(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, ldst+64(,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ldst+64(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: off06:
-; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _off06:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_lsrc+64(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, _ldst+64(,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], _ldst+64(,[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _off06:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc+64(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, _ldst+64(,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], _ldst+64(,[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off06:
 ; DARWIN-32-PIC: 	calll	L45$pb
 ; DARWIN-32-PIC-NEXT: L45$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L45$pb)+64(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	%edx, (_ldst-L45$pb)+64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L45$pb)+64([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], (_ldst-L45$pb)+64([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _off06:
-; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	leaq	_ldst(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	_ldst(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _off06:
-; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ldst(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ldst(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _off06:
-; DARWIN-64-PIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	leaq	_ldst(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	_ldst(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3376,65 +3387,65 @@
 	store i32* %0, i32** @lptr, align 8
 	ret void
 ; LINUX-64-STATIC: off07:
-; LINUX-64-STATIC: leaq    ldst+64(,%rdi,4), %rax
-; LINUX-64-STATIC: movq    %rax, lptr
+; LINUX-64-STATIC: leaq    ldst+64(,%rdi,4), [[RAX:%r.x]]
+; LINUX-64-STATIC: movq    [[RAX]], lptr
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: off07:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	ldst+64(,%eax,4), %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, lptr
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	ldst+64(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: off07:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	ldst+64(,%eax,4), %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, lptr
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	ldst+64(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: off07:
-; LINUX-64-PIC: 	leaq	ldst(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; LINUX-64-PIC-NEXT: 	movq	%rax, lptr(%rip)
+; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _off07:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_ldst+64(,%eax,4), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _lptr
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_ldst+64(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _lptr
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _off07:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_ldst+64(,%eax,4), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _lptr
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_ldst+64(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _lptr
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off07:
 ; DARWIN-32-PIC: 	calll	L46$pb
 ; DARWIN-32-PIC-NEXT: L46$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L46$pb)+64(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _lptr-L46$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L46$pb)+64([[EAX]],[[ECX]],4), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _lptr-L46$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _off07:
-; DARWIN-64-STATIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _off07:
-; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _off07:
-; DARWIN-64-PIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3448,75 +3459,75 @@
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC: off08:
-; LINUX-64-STATIC: movl    lsrc+64(,%rdi,4), %eax
-; LINUX-64-STATIC: movq    lptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 64(%rcx,%rdi,4)
+; LINUX-64-STATIC: movl    lsrc+64(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: off08:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	lsrc+64(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	lptr, %edx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: off08:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	lsrc+64(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	lptr, %edx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: off08:
-; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _off08:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_lsrc+64(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	_lptr, %edx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lptr, [[EDX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _off08:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc+64(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, 64(%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], 64([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _off08:
 ; DARWIN-32-PIC: 	calll	L47$pb
 ; DARWIN-32-PIC-NEXT: L47$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L47$pb)+64(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	_lptr-L47$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, 64(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L47$pb)+64([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lptr-L47$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], 64([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _off08:
-; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _off08:
-; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _off08:
-; DARWIN-64-PIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	64(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 64(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	64([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 64([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3526,68 +3537,68 @@
 	store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), align 4
 	ret void
 ; LINUX-64-STATIC: moo00:
-; LINUX-64-STATIC: movl    src+262144(%rip), %eax
-; LINUX-64-STATIC: movl    %eax, dst+262144(%rip)
+; LINUX-64-STATIC: movl    src+262144(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], dst+262144(%rip)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: moo00:
-; LINUX-32-STATIC: 	movl	src+262144, %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, dst+262144
+; LINUX-32-STATIC: 	movl	src+262144, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dst+262144
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: moo00:
-; LINUX-32-PIC: 	movl	src+262144, %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, dst+262144
+; LINUX-32-PIC: 	movl	src+262144, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dst+262144
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: moo00:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	262144(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 262144(%rcx)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _moo00:
-; DARWIN-32-STATIC: 	movl	_src+262144, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _dst+262144
+; DARWIN-32-STATIC: 	movl	_src+262144, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _dst+262144
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _moo00:
-; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	262144(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, 262144(%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	262144([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo00:
 ; DARWIN-32-PIC: 	calll	L48$pb
 ; DARWIN-32-PIC-NEXT: L48$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L48$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	262144(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L48$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, 262144(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L48$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	262144([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L48$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _moo00:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	262144(%rax), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _moo00:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	262144(%rax), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _moo00:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	262144(%rax), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3608,10 +3619,10 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: moo01:
-; LINUX-64-PIC: 	movl	$262144, %eax
-; LINUX-64-PIC-NEXT: 	addq	dst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movl	$262144, [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	addq	dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _moo01:
@@ -3619,41 +3630,41 @@
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _moo01:
-; DARWIN-32-DYNAMIC: 	movl	$262144, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	addl	L_dst$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	$262144, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	addl	L_dst$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo01:
 ; DARWIN-32-PIC: 	calll	L49$pb
 ; DARWIN-32-PIC-NEXT: L49$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	$262144, %ecx
-; DARWIN-32-PIC-NEXT: 	addl	L_dst$non_lazy_ptr-L49$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L49$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	$262144, [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	addl	L_dst$non_lazy_ptr-L49$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L49$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _moo01:
-; DARWIN-64-STATIC: 	movl	$262144, %eax
-; DARWIN-64-STATIC-NEXT: 	addq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-STATIC: 	movl	$262144, [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	addq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _moo01:
-; DARWIN-64-DYNAMIC: 	movl	$262144, %eax
-; DARWIN-64-DYNAMIC-NEXT: 	addq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movl	$262144, [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	addq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _moo01:
-; DARWIN-64-PIC: 	movl	$262144, %eax
-; DARWIN-64-PIC-NEXT: 	addq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-PIC: 	movl	$262144, [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	addq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3665,78 +3676,78 @@
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC: moo02:
-; LINUX-64-STATIC: movl    src+262144(%rip), %eax
-; LINUX-64-STATIC: movq    ptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 262144(%rcx)
+; LINUX-64-STATIC: movl    src+262144(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]])
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: moo02:
-; LINUX-32-STATIC: 	movl	src+262144, %eax
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%eax, 262144(%ecx)
+; LINUX-32-STATIC: 	movl	src+262144, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: moo02:
-; LINUX-32-PIC: 	movl	src+262144, %eax
-; LINUX-32-PIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-PIC-NEXT: 	movl	%eax, 262144(%ecx)
+; LINUX-32-PIC: 	movl	src+262144, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: moo02:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	262144(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 262144(%rcx)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _moo02:
-; DARWIN-32-STATIC: 	movl	_src+262144, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, 262144(%ecx)
+; DARWIN-32-STATIC: 	movl	_src+262144, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _moo02:
-; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	262144(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%ecx), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, 262144(%ecx)
+; DARWIN-32-DYNAMIC: 	movl	L_src$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	262144([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo02:
 ; DARWIN-32-PIC: 	calll	L50$pb
 ; DARWIN-32-PIC-NEXT: L50$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L50$pb(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	262144(%ecx), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L50$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, 262144(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L50$pb([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	262144([[ECX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L50$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _moo02:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	262144(%rax), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _moo02:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	262144(%rax), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _moo02:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	262144(%rax), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3746,58 +3757,58 @@
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), align 32
 	ret void
 ; LINUX-64-STATIC: moo03:
-; LINUX-64-STATIC: movl    dsrc+262144(%rip), %eax
-; LINUX-64-STATIC: movl    %eax, ddst+262144(%rip)
+; LINUX-64-STATIC: movl    dsrc+262144(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ddst+262144(%rip)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: moo03:
-; LINUX-32-STATIC: 	movl	dsrc+262144, %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, ddst+262144
+; LINUX-32-STATIC: 	movl	dsrc+262144, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ddst+262144
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: moo03:
-; LINUX-32-PIC: 	movl	dsrc+262144, %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, ddst+262144
+; LINUX-32-PIC: 	movl	dsrc+262144, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ddst+262144
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: moo03:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	262144(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 262144(%rcx)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _moo03:
-; DARWIN-32-STATIC: 	movl	_dsrc+262144, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _ddst+262144
+; DARWIN-32-STATIC: 	movl	_dsrc+262144, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _ddst+262144
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _moo03:
-; DARWIN-32-DYNAMIC: 	movl	_dsrc+262144, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _ddst+262144
+; DARWIN-32-DYNAMIC: 	movl	_dsrc+262144, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _ddst+262144
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo03:
 ; DARWIN-32-PIC: 	calll	L51$pb
 ; DARWIN-32-PIC-NEXT: L51$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L51$pb)+262144(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (_ddst-L51$pb)+262144(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L51$pb)+262144([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], (_ddst-L51$pb)+262144([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _moo03:
-; DARWIN-64-STATIC: 	movl	_dsrc+262144(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, _ddst+262144(%rip)
+; DARWIN-64-STATIC: 	movl	_dsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], _ddst+262144(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _moo03:
-; DARWIN-64-DYNAMIC: 	movl	_dsrc+262144(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, _ddst+262144(%rip)
+; DARWIN-64-DYNAMIC: 	movl	_dsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], _ddst+262144(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _moo03:
-; DARWIN-64-PIC: 	movl	_dsrc+262144(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movl	%eax, _ddst+262144(%rip)
+; DARWIN-64-PIC: 	movl	_dsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], _ddst+262144(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3818,10 +3829,10 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: moo04:
-; LINUX-64-PIC: 	movl	$262144, %eax
-; LINUX-64-PIC-NEXT: 	addq	ddst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movl	$262144, [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	addq	ddst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _moo04:
@@ -3835,24 +3846,24 @@
 ; DARWIN-32-PIC: _moo04:
 ; DARWIN-32-PIC: 	calll	L52$pb
 ; DARWIN-32-PIC-NEXT: L52$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L52$pb)+262144(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _dptr-L52$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L52$pb)+262144([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _dptr-L52$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _moo04:
-; DARWIN-64-STATIC: 	leaq	_ddst+262144(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ddst+262144(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _moo04:
-; DARWIN-64-DYNAMIC: 	leaq	_ddst+262144(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ddst+262144(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _moo04:
-; DARWIN-64-PIC: 	leaq	_ddst+262144(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ddst+262144(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3864,68 +3875,68 @@
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC: moo05:
-; LINUX-64-STATIC: movl    dsrc+262144(%rip), %eax
-; LINUX-64-STATIC: movq    dptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 262144(%rcx)
+; LINUX-64-STATIC: movl    dsrc+262144(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]])
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: moo05:
-; LINUX-32-STATIC: 	movl	dsrc+262144, %eax
-; LINUX-32-STATIC-NEXT: 	movl	dptr, %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%eax, 262144(%ecx)
+; LINUX-32-STATIC: 	movl	dsrc+262144, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: moo05:
-; LINUX-32-PIC: 	movl	dsrc+262144, %eax
-; LINUX-32-PIC-NEXT: 	movl	dptr, %ecx
-; LINUX-32-PIC-NEXT: 	movl	%eax, 262144(%ecx)
+; LINUX-32-PIC: 	movl	dsrc+262144, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: moo05:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	262144(%rax), %eax
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 262144(%rcx)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]]), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _moo05:
-; DARWIN-32-STATIC: 	movl	_dsrc+262144, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_dptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, 262144(%ecx)
+; DARWIN-32-STATIC: 	movl	_dsrc+262144, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _moo05:
-; DARWIN-32-DYNAMIC: 	movl	_dsrc+262144, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, 262144(%ecx)
+; DARWIN-32-DYNAMIC: 	movl	_dsrc+262144, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo05:
 ; DARWIN-32-PIC: 	calll	L53$pb
 ; DARWIN-32-PIC-NEXT: L53$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L53$pb)+262144(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_dptr-L53$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, 262144(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L53$pb)+262144([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dptr-L53$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _moo05:
-; DARWIN-64-STATIC: 	movl	_dsrc+262144(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-STATIC: 	movl	_dsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _moo05:
-; DARWIN-64-DYNAMIC: 	movl	_dsrc+262144(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-DYNAMIC: 	movl	_dsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _moo05:
-; DARWIN-64-PIC: 	movl	_dsrc+262144(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-PIC: 	movl	_dsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -3935,56 +3946,56 @@
 	store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), align 4
 	ret void
 ; LINUX-64-STATIC: moo06:
-; LINUX-64-STATIC: movl    lsrc+262144(%rip), %eax
-; LINUX-64-STATIC: movl    %eax, ldst+262144(%rip)
+; LINUX-64-STATIC: movl    lsrc+262144(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ldst+262144(%rip)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: moo06:
-; LINUX-32-STATIC: 	movl	lsrc+262144, %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, ldst+262144
+; LINUX-32-STATIC: 	movl	lsrc+262144, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ldst+262144
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: moo06:
-; LINUX-32-PIC: 	movl	lsrc+262144, %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, ldst+262144
+; LINUX-32-PIC: 	movl	lsrc+262144, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ldst+262144
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: moo06:
-; LINUX-64-PIC: 	movl	lsrc+262144(%rip), %eax
-; LINUX-64-PIC-NEXT: 	movl	%eax, ldst+262144(%rip)
+; LINUX-64-PIC: 	movl	lsrc+262144(%rip), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], ldst+262144(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _moo06:
-; DARWIN-32-STATIC: 	movl	_lsrc+262144, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _ldst+262144
+; DARWIN-32-STATIC: 	movl	_lsrc+262144, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _ldst+262144
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _moo06:
-; DARWIN-32-DYNAMIC: 	movl	_lsrc+262144, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _ldst+262144
+; DARWIN-32-DYNAMIC: 	movl	_lsrc+262144, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _ldst+262144
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo06:
 ; DARWIN-32-PIC: 	calll	L54$pb
 ; DARWIN-32-PIC-NEXT: L54$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L54$pb)+262144(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (_ldst-L54$pb)+262144(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L54$pb)+262144([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], (_ldst-L54$pb)+262144([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _moo06:
-; DARWIN-64-STATIC: 	movl	_lsrc+262144(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, _ldst+262144(%rip)
+; DARWIN-64-STATIC: 	movl	_lsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], _ldst+262144(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _moo06:
-; DARWIN-64-DYNAMIC: 	movl	_lsrc+262144(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, _ldst+262144(%rip)
+; DARWIN-64-DYNAMIC: 	movl	_lsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], _ldst+262144(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _moo06:
-; DARWIN-64-PIC: 	movl	_lsrc+262144(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movl	%eax, _ldst+262144(%rip)
+; DARWIN-64-PIC: 	movl	_lsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], _ldst+262144(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4005,8 +4016,8 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: moo07:
-; LINUX-64-PIC: 	leaq	ldst+262144(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	%rax, lptr(%rip)
+; LINUX-64-PIC: 	leaq	ldst+262144(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _moo07:
@@ -4020,24 +4031,24 @@
 ; DARWIN-32-PIC: _moo07:
 ; DARWIN-32-PIC: 	calll	L55$pb
 ; DARWIN-32-PIC-NEXT: L55$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L55$pb)+262144(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _lptr-L55$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L55$pb)+262144([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _lptr-L55$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _moo07:
-; DARWIN-64-STATIC: 	leaq	_ldst+262144(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ldst+262144(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _moo07:
-; DARWIN-64-DYNAMIC: 	leaq	_ldst+262144(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ldst+262144(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _moo07:
-; DARWIN-64-PIC: 	leaq	_ldst+262144(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ldst+262144(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4049,66 +4060,66 @@
 	store i32 %1, i32* %2, align 4
 	ret void
 ; LINUX-64-STATIC: moo08:
-; LINUX-64-STATIC: movl    lsrc+262144(%rip), %eax
-; LINUX-64-STATIC: movq    lptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 262144(%rcx)
+; LINUX-64-STATIC: movl    lsrc+262144(%rip), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]])
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: moo08:
-; LINUX-32-STATIC: 	movl	lsrc+262144, %eax
-; LINUX-32-STATIC-NEXT: 	movl	lptr, %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%eax, 262144(%ecx)
+; LINUX-32-STATIC: 	movl	lsrc+262144, [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: moo08:
-; LINUX-32-PIC: 	movl	lsrc+262144, %eax
-; LINUX-32-PIC-NEXT: 	movl	lptr, %ecx
-; LINUX-32-PIC-NEXT: 	movl	%eax, 262144(%ecx)
+; LINUX-32-PIC: 	movl	lsrc+262144, [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: moo08:
-; LINUX-64-PIC: 	movl	lsrc+262144(%rip), %eax
-; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 262144(%rcx)
+; LINUX-64-PIC: 	movl	lsrc+262144(%rip), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _moo08:
-; DARWIN-32-STATIC: 	movl	_lsrc+262144, %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_lptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, 262144(%ecx)
+; DARWIN-32-STATIC: 	movl	_lsrc+262144, [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _moo08:
-; DARWIN-32-DYNAMIC: 	movl	_lsrc+262144, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, 262144(%ecx)
+; DARWIN-32-DYNAMIC: 	movl	_lsrc+262144, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _moo08:
 ; DARWIN-32-PIC: 	calll	L56$pb
 ; DARWIN-32-PIC-NEXT: L56$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L56$pb)+262144(%eax), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_lptr-L56$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, 262144(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L56$pb)+262144([[EAX]]), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lptr-L56$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _moo08:
-; DARWIN-64-STATIC: 	movl	_lsrc+262144(%rip), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-STATIC: 	movl	_lsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _moo08:
-; DARWIN-64-DYNAMIC: 	movl	_lsrc+262144(%rip), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-DYNAMIC: 	movl	_lsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _moo08:
-; DARWIN-64-PIC: 	movl	_lsrc+262144(%rip), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 262144(%rcx)
+; DARWIN-64-PIC: 	movl	_lsrc+262144(%rip), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4121,73 +4132,73 @@
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC: big00:
-; LINUX-64-STATIC: movl    src+262144(,%rdi,4), %eax
-; LINUX-64-STATIC: movl    %eax, dst+262144(,%rdi,4)
+; LINUX-64-STATIC: movl    src+262144(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], dst+262144(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: big00:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	src+262144(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, dst+262144(,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], dst+262144(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: big00:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	src+262144(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, dst+262144(,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], dst+262144(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: big00:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _big00:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_src+262144(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, _dst+262144(,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_src+262144(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], _dst+262144(,[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _big00:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	262144(%ecx,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	262144([[ECX]],[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big00:
 ; DARWIN-32-PIC: 	calll	L57$pb
 ; DARWIN-32-PIC-NEXT: L57$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L57$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	movl	262144(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L57$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, 262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L57$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	262144([[EDX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L57$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], 262144([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _big00:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _big00:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _big00:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_dst at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4198,73 +4209,73 @@
 	store i32* %0, i32** @ptr, align 8
 	ret void
 ; LINUX-64-STATIC: big01:
-; LINUX-64-STATIC: leaq    dst+262144(,%rdi,4), %rax
-; LINUX-64-STATIC: movq    %rax, ptr(%rip)
+; LINUX-64-STATIC: leaq    dst+262144(,%rdi,4), [[RAX:%r.x]]
+; LINUX-64-STATIC: movq    [[RAX]], ptr(%rip)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: big01:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	dst+262144(,%eax,4), %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, ptr
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	dst+262144(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: big01:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	dst+262144(,%eax,4), %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, ptr
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	dst+262144(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], ptr
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: big01:
-; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _big01:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_dst+262144(,%eax,4), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _ptr
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_dst+262144(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _ptr
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _big01:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, (%ecx)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], ([[ECX]])
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big01:
 ; DARWIN-32-PIC: 	calll	L58$pb
 ; DARWIN-32-PIC-NEXT: L58$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L58$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	leal	262144(%edx,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L58$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, (%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L58$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	262144([[EDX]],[[ECX]],4), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L58$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], ([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _big01:
-; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _big01:
-; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _big01:
-; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4278,83 +4289,83 @@
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC: big02:
-; LINUX-64-STATIC: movl    src+262144(,%rdi,4), %eax
-; LINUX-64-STATIC: movq    ptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-STATIC: movl    src+262144(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    ptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: big02:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	src+262144(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %edx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: big02:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	src+262144(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	ptr, %edx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	src+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[EDX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: big02:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _big02:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_src+262144(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %edx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_src+262144(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[EDX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _big02:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	262144(%ecx,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%edx), %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	262144([[ECX]],[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_ptr$non_lazy_ptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EDX]]), [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big02:
 ; DARWIN-32-PIC: 	calll	L59$pb
 ; DARWIN-32-PIC-NEXT: L59$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L59$pb(%eax), %edx
-; DARWIN-32-PIC-NEXT: 	movl	262144(%edx,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L59$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, 262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L59$pb([[EAX]]), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	262144([[EDX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L59$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], 262144([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _big02:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _big02:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _big02:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4367,69 +4378,69 @@
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC: big03:
-; LINUX-64-STATIC: movl    dsrc+262144(,%rdi,4), %eax
-; LINUX-64-STATIC: movl    %eax, ddst+262144(,%rdi,4)
+; LINUX-64-STATIC: movl    dsrc+262144(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ddst+262144(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: big03:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	dsrc+262144(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, ddst+262144(,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ddst+262144(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: big03:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	dsrc+262144(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, ddst+262144(,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ddst+262144(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: big03:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	ddst at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _big03:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_dsrc+262144(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, _ddst+262144(,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], _ddst+262144(,[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _big03:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc+262144(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, _ddst+262144(,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], _ddst+262144(,[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big03:
 ; DARWIN-32-PIC: 	calll	L60$pb
 ; DARWIN-32-PIC-NEXT: L60$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L60$pb)+262144(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	%edx, (_ddst-L60$pb)+262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L60$pb)+262144([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], (_ddst-L60$pb)+262144([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _big03:
-; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	leaq	_ddst(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	_ddst(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _big03:
-; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ddst(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ddst(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _big03:
-; DARWIN-64-PIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	leaq	_ddst(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	_ddst(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4440,66 +4451,66 @@
 	store i32* %0, i32** @dptr, align 8
 	ret void
 ; LINUX-64-STATIC: big04:
-; LINUX-64-STATIC: leaq    ddst+262144(,%rdi,4), %rax
-; LINUX-64-STATIC: movq    %rax, dptr
+; LINUX-64-STATIC: leaq    ddst+262144(,%rdi,4), [[RAX:%r.x]]
+; LINUX-64-STATIC: movq    [[RAX]], dptr
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: big04:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	ddst+262144(,%eax,4), %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, dptr
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: big04:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	ddst+262144(,%eax,4), %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, dptr
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], dptr
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: big04:
-; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	%rax, (%rcx)
+; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], ([[RCX]])
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _big04:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_ddst+262144(,%eax,4), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _dptr
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_ddst+262144(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _dptr
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _big04:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_ddst+262144(,%eax,4), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _dptr
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_ddst+262144(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _dptr
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big04:
 ; DARWIN-32-PIC: 	calll	L61$pb
 ; DARWIN-32-PIC-NEXT: L61$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L61$pb)+262144(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _dptr-L61$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L61$pb)+262144([[EAX]],[[ECX]],4), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _dptr-L61$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _big04:
-; DARWIN-64-STATIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _big04:
-; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _big04:
-; DARWIN-64-PIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _dptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _dptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4513,76 +4524,76 @@
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC: big05:
-; LINUX-64-STATIC: movl    dsrc+262144(,%rdi,4), %eax
-; LINUX-64-STATIC: movq    dptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-STATIC: movl    dsrc+262144(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    dptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: big05:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	dsrc+262144(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	dptr, %edx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: big05:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	dsrc+262144(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	dptr, %edx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dptr, [[EDX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: big05:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movq	(%rcx), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RCX]]), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _big05:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_dsrc+262144(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	_dptr, %edx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dptr, [[EDX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _big05:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc+262144(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big05:
 ; DARWIN-32-PIC: 	calll	L62$pb
 ; DARWIN-32-PIC-NEXT: L62$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L62$pb)+262144(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	_dptr-L62$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, 262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_dsrc-L62$pb)+262144([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dptr-L62$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], 262144([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _big05:
-; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _big05:
-; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _big05:
-; DARWIN-64-PIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_dptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4595,69 +4606,69 @@
 	store i32 %2, i32* %3, align 4
 	ret void
 ; LINUX-64-STATIC: big06:
-; LINUX-64-STATIC: movl    lsrc+262144(,%rdi,4), %eax
-; LINUX-64-STATIC: movl    %eax, ldst+262144(,%rdi,4)
+; LINUX-64-STATIC: movl    lsrc+262144(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movl    [[EAX]], ldst+262144(,%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: big06:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	lsrc+262144(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, ldst+262144(,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], ldst+262144(,[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: big06:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	lsrc+262144(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, ldst+262144(,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], ldst+262144(,[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: big06:
-; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	leaq	ldst(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _big06:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_lsrc+262144(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, _ldst+262144(,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], _ldst+262144(,[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _big06:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc+262144(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, _ldst+262144(,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], _ldst+262144(,[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big06:
 ; DARWIN-32-PIC: 	calll	L63$pb
 ; DARWIN-32-PIC-NEXT: L63$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L63$pb)+262144(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	%edx, (_ldst-L63$pb)+262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L63$pb)+262144([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], (_ldst-L63$pb)+262144([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _big06:
-; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	leaq	_ldst(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	_ldst(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _big06:
-; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ldst(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	_ldst(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _big06:
-; DARWIN-64-PIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	leaq	_ldst(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	_ldst(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4668,65 +4679,65 @@
 	store i32* %0, i32** @lptr, align 8
 	ret void
 ; LINUX-64-STATIC: big07:
-; LINUX-64-STATIC: leaq    ldst+262144(,%rdi,4), %rax
-; LINUX-64-STATIC: movq    %rax, lptr
+; LINUX-64-STATIC: leaq    ldst+262144(,%rdi,4), [[RAX:%r.x]]
+; LINUX-64-STATIC: movq    [[RAX]], lptr
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: big07:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	ldst+262144(,%eax,4), %eax
-; LINUX-32-STATIC-NEXT: 	movl	%eax, lptr
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: big07:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	ldst+262144(,%eax,4), %eax
-; LINUX-32-PIC-NEXT: 	movl	%eax, lptr
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[EAX]], lptr
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: big07:
-; LINUX-64-PIC: 	leaq	ldst(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; LINUX-64-PIC-NEXT: 	movq	%rax, lptr(%rip)
+; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	[[RAX]], lptr(%rip)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _big07:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_ldst+262144(,%eax,4), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	%eax, _lptr
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_ldst+262144(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[EAX]], _lptr
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _big07:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_ldst+262144(,%eax,4), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%eax, _lptr
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_ldst+262144(,[[EAX]],4), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[EAX]], _lptr
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big07:
 ; DARWIN-32-PIC: 	calll	L64$pb
 ; DARWIN-32-PIC-NEXT: L64$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L64$pb)+262144(%eax,%ecx,4), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	%ecx, _lptr-L64$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L64$pb)+262144([[EAX]],[[ECX]],4), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[ECX]], _lptr-L64$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _big07:
-; DARWIN-64-STATIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-STATIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _big07:
-; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _big07:
-; DARWIN-64-PIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
-; DARWIN-64-PIC-NEXT: 	movq	%rax, _lptr(%rip)
+; DARWIN-64-PIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	[[RAX]], _lptr(%rip)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4740,75 +4751,75 @@
 	store i32 %3, i32* %4, align 4
 	ret void
 ; LINUX-64-STATIC: big08:
-; LINUX-64-STATIC: movl    lsrc+262144(,%rdi,4), %eax
-; LINUX-64-STATIC: movq    lptr(%rip), %rcx
-; LINUX-64-STATIC: movl    %eax, 262144(%rcx,%rdi,4)
+; LINUX-64-STATIC: movl    lsrc+262144(,%rdi,4), [[EAX:%e.x]]
+; LINUX-64-STATIC: movq    lptr(%rip), [[RCX:%r.x]]
+; LINUX-64-STATIC: movl    [[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: big08:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	lsrc+262144(,%eax,4), %ecx
-; LINUX-32-STATIC-NEXT: 	movl	lptr, %edx
-; LINUX-32-STATIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: big08:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	lsrc+262144(,%eax,4), %ecx
-; LINUX-32-PIC-NEXT: 	movl	lptr, %edx
-; LINUX-32-PIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lptr, [[EDX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: big08:
-; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), %rcx
-; LINUX-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; LINUX-64-PIC-NEXT: 	movq	lptr(%rip), [[RCX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _big08:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_lsrc+262144(,%eax,4), %ecx
-; DARWIN-32-STATIC-NEXT: 	movl	_lptr, %edx
-; DARWIN-32-STATIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lptr, [[EDX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _big08:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc+262144(,%eax,4), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, %edx
-; DARWIN-32-DYNAMIC-NEXT: 	movl	%ecx, 262144(%edx,%eax,4)
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, [[EDX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	[[ECX]], 262144([[EDX]],[[EAX]],4)
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _big08:
 ; DARWIN-32-PIC: 	calll	L65$pb
 ; DARWIN-32-PIC-NEXT: L65$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L65$pb)+262144(%eax,%ecx,4), %edx
-; DARWIN-32-PIC-NEXT: 	movl	_lptr-L65$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	%edx, 262144(%eax,%ecx,4)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	(_lsrc-L65$pb)+262144([[EAX]],[[ECX]],4), [[EDX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lptr-L65$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	[[EDX]], 262144([[EAX]],[[ECX]],4)
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _big08:
-; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-STATIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _big08:
-; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-DYNAMIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _big08:
-; DARWIN-64-PIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movl	262144(%rax,%rdi,4), %eax
-; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), %rcx
-; DARWIN-64-PIC-NEXT: 	movl	%eax, 262144(%rcx,%rdi,4)
+; DARWIN-64-PIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	262144([[RAX]],%rdi,4), [[EAX:%e.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_lptr(%rip), [[RCX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movl	[[EAX]], 262144([[RCX]],%rdi,4)
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -4842,8 +4853,8 @@
 ; DARWIN-32-PIC: _bar00:
 ; DARWIN-32-PIC: 	calll	L66$pb
 ; DARWIN-32-PIC-NEXT: L66$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L66$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L66$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bar00:
@@ -4889,8 +4900,8 @@
 ; DARWIN-32-PIC: _bxr00:
 ; DARWIN-32-PIC: 	calll	L67$pb
 ; DARWIN-32-PIC-NEXT: L67$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L67$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L67$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bxr00:
@@ -4936,8 +4947,8 @@
 ; DARWIN-32-PIC: _bar01:
 ; DARWIN-32-PIC: 	calll	L68$pb
 ; DARWIN-32-PIC-NEXT: L68$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L68$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L68$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bar01:
@@ -4983,8 +4994,8 @@
 ; DARWIN-32-PIC: _bxr01:
 ; DARWIN-32-PIC: 	calll	L69$pb
 ; DARWIN-32-PIC-NEXT: L69$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L69$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L69$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bxr01:
@@ -5030,8 +5041,8 @@
 ; DARWIN-32-PIC: _bar02:
 ; DARWIN-32-PIC: 	calll	L70$pb
 ; DARWIN-32-PIC-NEXT: L70$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L70$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L70$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bar02:
@@ -5077,8 +5088,8 @@
 ; DARWIN-32-PIC: _bar03:
 ; DARWIN-32-PIC: 	calll	L71$pb
 ; DARWIN-32-PIC-NEXT: L71$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_dsrc-L71$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_dsrc-L71$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bar03:
@@ -5124,8 +5135,8 @@
 ; DARWIN-32-PIC: _bar04:
 ; DARWIN-32-PIC: 	calll	L72$pb
 ; DARWIN-32-PIC-NEXT: L72$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_ddst-L72$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_ddst-L72$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bar04:
@@ -5171,8 +5182,8 @@
 ; DARWIN-32-PIC: _bar05:
 ; DARWIN-32-PIC: 	calll	L73$pb
 ; DARWIN-32-PIC-NEXT: L73$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_dptr-L73$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_dptr-L73$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bar05:
@@ -5218,8 +5229,8 @@
 ; DARWIN-32-PIC: _bar06:
 ; DARWIN-32-PIC: 	calll	L74$pb
 ; DARWIN-32-PIC-NEXT: L74$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_lsrc-L74$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_lsrc-L74$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bar06:
@@ -5265,8 +5276,8 @@
 ; DARWIN-32-PIC: _bar07:
 ; DARWIN-32-PIC: 	calll	L75$pb
 ; DARWIN-32-PIC-NEXT: L75$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_ldst-L75$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_ldst-L75$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bar07:
@@ -5312,8 +5323,8 @@
 ; DARWIN-32-PIC: _bar08:
 ; DARWIN-32-PIC: 	calll	L76$pb
 ; DARWIN-32-PIC-NEXT: L76$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_lptr-L76$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_lptr-L76$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bar08:
@@ -5359,8 +5370,8 @@
 ; DARWIN-32-PIC: _har00:
 ; DARWIN-32-PIC: 	calll	L77$pb
 ; DARWIN-32-PIC-NEXT: L77$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L77$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L77$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _har00:
@@ -5406,8 +5417,8 @@
 ; DARWIN-32-PIC: _hxr00:
 ; DARWIN-32-PIC: 	calll	L78$pb
 ; DARWIN-32-PIC-NEXT: L78$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L78$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L78$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _hxr00:
@@ -5453,8 +5464,8 @@
 ; DARWIN-32-PIC: _har01:
 ; DARWIN-32-PIC: 	calll	L79$pb
 ; DARWIN-32-PIC-NEXT: L79$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L79$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L79$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _har01:
@@ -5500,8 +5511,8 @@
 ; DARWIN-32-PIC: _hxr01:
 ; DARWIN-32-PIC: 	calll	L80$pb
 ; DARWIN-32-PIC-NEXT: L80$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L80$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L80$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _hxr01:
@@ -5535,8 +5546,8 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: har02:
-; LINUX-64-PIC: 	movq	ptr at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	(%rax), %rax
+; LINUX-64-PIC: 	movq	ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _har02:
@@ -5544,31 +5555,31 @@
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _har02:
-; DARWIN-32-DYNAMIC: 	movl	L_ptr$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%eax), %eax
+; DARWIN-32-DYNAMIC: 	movl	L_ptr$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EAX]]), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _har02:
 ; DARWIN-32-PIC: 	calll	L81$pb
 ; DARWIN-32-PIC-NEXT: L81$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L81$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L81$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _har02:
-; DARWIN-64-STATIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	(%rax), %rax
+; DARWIN-64-STATIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RAX]]), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _har02:
-; DARWIN-64-DYNAMIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rax), %rax
+; DARWIN-64-DYNAMIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RAX]]), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _har02:
-; DARWIN-64-PIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	(%rax), %rax
+; DARWIN-64-PIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -5602,8 +5613,8 @@
 ; DARWIN-32-PIC: _har03:
 ; DARWIN-32-PIC: 	calll	L82$pb
 ; DARWIN-32-PIC-NEXT: L82$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_dsrc-L82$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_dsrc-L82$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _har03:
@@ -5649,8 +5660,8 @@
 ; DARWIN-32-PIC: _har04:
 ; DARWIN-32-PIC: 	calll	L83$pb
 ; DARWIN-32-PIC-NEXT: L83$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_ddst-L83$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_ddst-L83$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _har04:
@@ -5684,8 +5695,8 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: har05:
-; LINUX-64-PIC: 	movq	dptr at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	(%rax), %rax
+; LINUX-64-PIC: 	movq	dptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _har05:
@@ -5699,8 +5710,8 @@
 ; DARWIN-32-PIC: _har05:
 ; DARWIN-32-PIC: 	calll	L84$pb
 ; DARWIN-32-PIC-NEXT: L84$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	_dptr-L84$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dptr-L84$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _har05:
@@ -5746,8 +5757,8 @@
 ; DARWIN-32-PIC: _har06:
 ; DARWIN-32-PIC: 	calll	L85$pb
 ; DARWIN-32-PIC-NEXT: L85$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_lsrc-L85$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_lsrc-L85$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _har06:
@@ -5793,8 +5804,8 @@
 ; DARWIN-32-PIC: _har07:
 ; DARWIN-32-PIC: 	calll	L86$pb
 ; DARWIN-32-PIC-NEXT: L86$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_ldst-L86$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_ldst-L86$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _har07:
@@ -5842,8 +5853,8 @@
 ; DARWIN-32-PIC: _har08:
 ; DARWIN-32-PIC: 	calll	L87$pb
 ; DARWIN-32-PIC-NEXT: L87$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	_lptr-L87$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lptr-L87$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _har08:
@@ -5891,8 +5902,8 @@
 ; DARWIN-32-PIC: _bat00:
 ; DARWIN-32-PIC: 	calll	L88$pb
 ; DARWIN-32-PIC-NEXT: L88$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L88$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L88$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	addl	$64, %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -5944,8 +5955,8 @@
 ; DARWIN-32-PIC: _bxt00:
 ; DARWIN-32-PIC: 	calll	L89$pb
 ; DARWIN-32-PIC-NEXT: L89$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L89$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L89$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	addl	$64, %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -5997,8 +6008,8 @@
 ; DARWIN-32-PIC: _bat01:
 ; DARWIN-32-PIC: 	calll	L90$pb
 ; DARWIN-32-PIC-NEXT: L90$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L90$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L90$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	addl	$64, %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -6050,8 +6061,8 @@
 ; DARWIN-32-PIC: _bxt01:
 ; DARWIN-32-PIC: 	calll	L91$pb
 ; DARWIN-32-PIC-NEXT: L91$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L91$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L91$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	addl	$64, %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -6093,8 +6104,8 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: bat02:
-; LINUX-64-PIC: 	movq	ptr at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	(%rax), %rax
+; LINUX-64-PIC: 	movq	ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -6104,35 +6115,35 @@
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _bat02:
-; DARWIN-32-DYNAMIC: 	movl	L_ptr$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%eax), %eax
+; DARWIN-32-DYNAMIC: 	movl	L_ptr$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
 ; DARWIN-32-DYNAMIC-NEXT: 	addl	$64, %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bat02:
 ; DARWIN-32-PIC: 	calll	L92$pb
 ; DARWIN-32-PIC-NEXT: L92$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L92$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L92$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	addl	$64, %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bat02:
-; DARWIN-64-STATIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	(%rax), %rax
+; DARWIN-64-STATIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RAX]]), %rax
 ; DARWIN-64-STATIC-NEXT: 	addq	$64, %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _bat02:
-; DARWIN-64-DYNAMIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rax), %rax
+; DARWIN-64-DYNAMIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
 ; DARWIN-64-DYNAMIC-NEXT: 	addq	$64, %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _bat02:
-; DARWIN-64-PIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	(%rax), %rax
+; DARWIN-64-PIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; DARWIN-64-PIC-NEXT: 	addq	$64, %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
@@ -6168,8 +6179,8 @@
 ; DARWIN-32-PIC: _bat03:
 ; DARWIN-32-PIC: 	calll	L93$pb
 ; DARWIN-32-PIC-NEXT: L93$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_dsrc-L93$pb)+64(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_dsrc-L93$pb)+64([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bat03:
@@ -6216,8 +6227,8 @@
 ; DARWIN-32-PIC: _bat04:
 ; DARWIN-32-PIC: 	calll	L94$pb
 ; DARWIN-32-PIC-NEXT: L94$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L94$pb)+64(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L94$pb)+64([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bat04:
@@ -6255,8 +6266,8 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: bat05:
-; LINUX-64-PIC: 	movq	dptr at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	(%rax), %rax
+; LINUX-64-PIC: 	movq	dptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), %rax
 ; LINUX-64-PIC-NEXT: 	addq	$64, %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -6273,8 +6284,8 @@
 ; DARWIN-32-PIC: _bat05:
 ; DARWIN-32-PIC: 	calll	L95$pb
 ; DARWIN-32-PIC-NEXT: L95$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	_dptr-L95$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dptr-L95$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	addl	$64, %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -6324,8 +6335,8 @@
 ; DARWIN-32-PIC: _bat06:
 ; DARWIN-32-PIC: 	calll	L96$pb
 ; DARWIN-32-PIC-NEXT: L96$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_lsrc-L96$pb)+64(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_lsrc-L96$pb)+64([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bat06:
@@ -6371,8 +6382,8 @@
 ; DARWIN-32-PIC: _bat07:
 ; DARWIN-32-PIC: 	calll	L97$pb
 ; DARWIN-32-PIC-NEXT: L97$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L97$pb)+64(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L97$pb)+64([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bat07:
@@ -6427,8 +6438,8 @@
 ; DARWIN-32-PIC: _bat08:
 ; DARWIN-32-PIC: 	calll	L98$pb
 ; DARWIN-32-PIC-NEXT: L98$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	_lptr-L98$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lptr-L98$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	addl	$64, %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -6480,9 +6491,9 @@
 ; DARWIN-32-PIC: _bam00:
 ; DARWIN-32-PIC: 	calll	L99$pb
 ; DARWIN-32-PIC-NEXT: L99$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%ecx
+; DARWIN-32-PIC-NEXT: 	popl	[[ECX:%e.x]]
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %eax
-; DARWIN-32-PIC-NEXT: 	addl	L_src$non_lazy_ptr-L99$pb(%ecx), %eax
+; DARWIN-32-PIC-NEXT: 	addl	L_src$non_lazy_ptr-L99$pb([[ECX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bam00:
@@ -6533,9 +6544,9 @@
 ; DARWIN-32-PIC: _bam01:
 ; DARWIN-32-PIC: 	calll	L100$pb
 ; DARWIN-32-PIC-NEXT: L100$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%ecx
+; DARWIN-32-PIC-NEXT: 	popl	[[ECX:%e.x]]
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %eax
-; DARWIN-32-PIC-NEXT: 	addl	L_dst$non_lazy_ptr-L100$pb(%ecx), %eax
+; DARWIN-32-PIC-NEXT: 	addl	L_dst$non_lazy_ptr-L100$pb([[ECX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bam01:
@@ -6586,9 +6597,9 @@
 ; DARWIN-32-PIC: _bxm01:
 ; DARWIN-32-PIC: 	calll	L101$pb
 ; DARWIN-32-PIC-NEXT: L101$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%ecx
+; DARWIN-32-PIC-NEXT: 	popl	[[ECX:%e.x]]
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %eax
-; DARWIN-32-PIC-NEXT: 	addl	L_xdst$non_lazy_ptr-L101$pb(%ecx), %eax
+; DARWIN-32-PIC-NEXT: 	addl	L_xdst$non_lazy_ptr-L101$pb([[ECX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bxm01:
@@ -6629,9 +6640,9 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: bam02:
-; LINUX-64-PIC: 	movq	ptr at GOTPCREL(%rip), %rcx
+; LINUX-64-PIC: 	movq	ptr at GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	$262144, %eax
-; LINUX-64-PIC-NEXT: 	addq	(%rcx), %rax
+; LINUX-64-PIC-NEXT: 	addq	([[RCX]]), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _bam02:
@@ -6640,36 +6651,36 @@
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _bam02:
-; DARWIN-32-DYNAMIC: 	movl	L_ptr$non_lazy_ptr, %ecx
+; DARWIN-32-DYNAMIC: 	movl	L_ptr$non_lazy_ptr, [[ECX:%e.x]]
 ; DARWIN-32-DYNAMIC-NEXT: 	movl	$262144, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	addl	(%ecx), %eax
+; DARWIN-32-DYNAMIC-NEXT: 	addl	([[ECX]]), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _bam02:
 ; DARWIN-32-PIC: 	calll	L102$pb
 ; DARWIN-32-PIC-NEXT: L102$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L102$pb(%eax), %ecx
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L102$pb([[EAX]]), [[ECX:%e.x]]
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %eax
-; DARWIN-32-PIC-NEXT: 	addl	(%ecx), %eax
+; DARWIN-32-PIC-NEXT: 	addl	([[ECX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bam02:
-; DARWIN-64-STATIC: 	movq	_ptr at GOTPCREL(%rip), %rcx
+; DARWIN-64-STATIC: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
 ; DARWIN-64-STATIC-NEXT: 	movl	$262144, %eax
-; DARWIN-64-STATIC-NEXT: 	addq	(%rcx), %rax
+; DARWIN-64-STATIC-NEXT: 	addq	([[RCX]]), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _bam02:
-; DARWIN-64-DYNAMIC: 	movq	_ptr at GOTPCREL(%rip), %rcx
+; DARWIN-64-DYNAMIC: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
 ; DARWIN-64-DYNAMIC-NEXT: 	movl	$262144, %eax
-; DARWIN-64-DYNAMIC-NEXT: 	addq	(%rcx), %rax
+; DARWIN-64-DYNAMIC-NEXT: 	addq	([[RCX]]), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _bam02:
-; DARWIN-64-PIC: 	movq	_ptr at GOTPCREL(%rip), %rcx
+; DARWIN-64-PIC: 	movq	_ptr at GOTPCREL(%rip), [[RCX:%r.x]]
 ; DARWIN-64-PIC-NEXT: 	movl	$262144, %eax
-; DARWIN-64-PIC-NEXT: 	addq	(%rcx), %rax
+; DARWIN-64-PIC-NEXT: 	addq	([[RCX]]), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -6704,8 +6715,8 @@
 ; DARWIN-32-PIC: _bam03:
 ; DARWIN-32-PIC: 	calll	L103$pb
 ; DARWIN-32-PIC-NEXT: L103$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_dsrc-L103$pb)+262144(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_dsrc-L103$pb)+262144([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bam03:
@@ -6752,8 +6763,8 @@
 ; DARWIN-32-PIC: _bam04:
 ; DARWIN-32-PIC: 	calll	L104$pb
 ; DARWIN-32-PIC-NEXT: L104$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L104$pb)+262144(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L104$pb)+262144([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bam04:
@@ -6791,9 +6802,9 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: bam05:
-; LINUX-64-PIC: 	movq	dptr at GOTPCREL(%rip), %rcx
+; LINUX-64-PIC: 	movq	dptr at GOTPCREL(%rip), [[RCX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	movl	$262144, %eax
-; LINUX-64-PIC-NEXT: 	addq	(%rcx), %rax
+; LINUX-64-PIC-NEXT: 	addq	([[RCX]]), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _bam05:
@@ -6809,9 +6820,9 @@
 ; DARWIN-32-PIC: _bam05:
 ; DARWIN-32-PIC: 	calll	L105$pb
 ; DARWIN-32-PIC-NEXT: L105$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%ecx
+; DARWIN-32-PIC-NEXT: 	popl	[[ECX:%e.x]]
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %eax
-; DARWIN-32-PIC-NEXT: 	addl	_dptr-L105$pb(%ecx), %eax
+; DARWIN-32-PIC-NEXT: 	addl	_dptr-L105$pb([[ECX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bam05:
@@ -6860,8 +6871,8 @@
 ; DARWIN-32-PIC: _bam06:
 ; DARWIN-32-PIC: 	calll	L106$pb
 ; DARWIN-32-PIC-NEXT: L106$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_lsrc-L106$pb)+262144(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_lsrc-L106$pb)+262144([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bam06:
@@ -6908,7 +6919,7 @@
 ; DARWIN-32-PIC: 	calll	L107$pb
 ; DARWIN-32-PIC-NEXT: L107$pb:
 ; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L107$pb)+262144(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L107$pb)+262144([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bam07:
@@ -6963,9 +6974,9 @@
 ; DARWIN-32-PIC: _bam08:
 ; DARWIN-32-PIC: 	calll	L108$pb
 ; DARWIN-32-PIC-NEXT: L108$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%ecx
+; DARWIN-32-PIC-NEXT: 	popl	[[ECX:%e.x]]
 ; DARWIN-32-PIC-NEXT: 	movl	$262144, %eax
-; DARWIN-32-PIC-NEXT: 	addl	_lptr-L108$pb(%ecx), %eax
+; DARWIN-32-PIC-NEXT: 	addl	_lptr-L108$pb([[ECX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _bam08:
@@ -6995,53 +7006,53 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cat00:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	src+64(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	src+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cat00:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	src+64(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	src+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cat00:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cat00:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_src+64(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_src+64(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cat00:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat00:
 ; DARWIN-32-PIC: 	calll	L109$pb
 ; DARWIN-32-PIC-NEXT: L109$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L109$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L109$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cat00:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cat00:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cat00:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7056,53 +7067,53 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cxt00:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	xsrc+64(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	xsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cxt00:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	xsrc+64(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	xsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cxt00:
-; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cxt00:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_xsrc+64(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_xsrc+64(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cxt00:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cxt00:
 ; DARWIN-32-PIC: 	calll	L110$pb
 ; DARWIN-32-PIC-NEXT: L110$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L110$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L110$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cxt00:
-; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cxt00:
-; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cxt00:
-; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7117,53 +7128,53 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cat01:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	dst+64(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	dst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cat01:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	dst+64(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	dst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cat01:
-; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cat01:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_dst+64(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_dst+64(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cat01:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat01:
 ; DARWIN-32-PIC: 	calll	L111$pb
 ; DARWIN-32-PIC-NEXT: L111$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L111$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L111$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cat01:
-; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cat01:
-; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cat01:
-; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7178,53 +7189,53 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cxt01:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	xdst+64(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	xdst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cxt01:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	xdst+64(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	xdst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cxt01:
-; LINUX-64-PIC: 	movq	xdst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cxt01:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_xdst+64(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_xdst+64(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cxt01:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cxt01:
 ; DARWIN-32-PIC: 	calll	L112$pb
 ; DARWIN-32-PIC-NEXT: L112$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L112$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L112$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cxt01:
-; DARWIN-64-STATIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cxt01:
-; DARWIN-64-DYNAMIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cxt01:
-; DARWIN-64-PIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7236,67 +7247,67 @@
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC: cat02:
-; LINUX-64-STATIC: movq    ptr(%rip), %rax
-; LINUX-64-STATIC: leaq    64(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: movq    ptr(%rip), [[RAX:%r.x]]
+; LINUX-64-STATIC: leaq    64([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cat02:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-STATIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cat02:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-PIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cat02:
-; LINUX-64-PIC: 	movq	ptr at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	(%rax), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cat02:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cat02:
-; DARWIN-32-DYNAMIC: 	movl	L_ptr$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	64(%eax,%ecx,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	L_ptr$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat02:
 ; DARWIN-32-PIC: 	calll	L113$pb
 ; DARWIN-32-PIC-NEXT: L113$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L113$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L113$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cat02:
-; DARWIN-64-STATIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	(%rax), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cat02:
-; DARWIN-64-DYNAMIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rax), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cat02:
-; DARWIN-64-PIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	(%rax), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7311,51 +7322,51 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cat03:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	dsrc+64(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	dsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cat03:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	dsrc+64(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	dsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cat03:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cat03:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_dsrc+64(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_dsrc+64(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cat03:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_dsrc+64(,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_dsrc+64(,[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat03:
 ; DARWIN-32-PIC: 	calll	L114$pb
 ; DARWIN-32-PIC-NEXT: L114$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_dsrc-L114$pb)+64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_dsrc-L114$pb)+64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cat03:
-; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cat03:
-; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cat03:
-; DARWIN-64-PIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7370,51 +7381,51 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cat04:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	ddst+64(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	ddst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cat04:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	ddst+64(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	ddst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cat04:
-; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cat04:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_ddst+64(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_ddst+64(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cat04:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_ddst+64(,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_ddst+64(,[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat04:
 ; DARWIN-32-PIC: 	calll	L115$pb
 ; DARWIN-32-PIC-NEXT: L115$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L115$pb)+64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L115$pb)+64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cat04:
-; DARWIN-64-STATIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cat04:
-; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cat04:
-; DARWIN-64-PIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7426,62 +7437,62 @@
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC: cat05:
-; LINUX-64-STATIC: movq    dptr(%rip), %rax
-; LINUX-64-STATIC: leaq    64(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: movq    dptr(%rip), [[RAX:%r.x]]
+; LINUX-64-STATIC: leaq    64([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cat05:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	dptr, %ecx
-; LINUX-32-STATIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cat05:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	dptr, %ecx
-; LINUX-32-PIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cat05:
-; LINUX-64-PIC: 	movq	dptr at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	(%rax), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	dptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cat05:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_dptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cat05:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat05:
 ; DARWIN-32-PIC: 	calll	L116$pb
 ; DARWIN-32-PIC-NEXT: L116$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_dptr-L116$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dptr-L116$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cat05:
-; DARWIN-64-STATIC: 	movq	_dptr(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_dptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cat05:
-; DARWIN-64-DYNAMIC: 	movq	_dptr(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_dptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cat05:
-; DARWIN-64-PIC: 	movq	_dptr(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_dptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7496,51 +7507,51 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cat06:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	lsrc+64(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	lsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cat06:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	lsrc+64(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	lsrc+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cat06:
-; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cat06:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_lsrc+64(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_lsrc+64(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cat06:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_lsrc+64(,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_lsrc+64(,[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat06:
 ; DARWIN-32-PIC: 	calll	L117$pb
 ; DARWIN-32-PIC-NEXT: L117$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_lsrc-L117$pb)+64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_lsrc-L117$pb)+64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cat06:
-; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cat06:
-; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cat06:
-; DARWIN-64-PIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7555,51 +7566,51 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cat07:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	ldst+64(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	ldst+64(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cat07:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	ldst+64(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	ldst+64(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cat07:
-; LINUX-64-PIC: 	leaq	ldst(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cat07:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_ldst+64(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_ldst+64(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cat07:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_ldst+64(,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_ldst+64(,[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat07:
 ; DARWIN-32-PIC: 	calll	L118$pb
 ; DARWIN-32-PIC-NEXT: L118$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L118$pb)+64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L118$pb)+64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cat07:
-; DARWIN-64-STATIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cat07:
-; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cat07:
-; DARWIN-64-PIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7611,61 +7622,61 @@
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC: cat08:
-; LINUX-64-STATIC: movq    lptr(%rip), %rax
-; LINUX-64-STATIC: leaq    64(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: movq    lptr(%rip), [[RAX:%r.x]]
+; LINUX-64-STATIC: leaq    64([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cat08:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	lptr, %ecx
-; LINUX-32-STATIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cat08:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	lptr, %ecx
-; LINUX-32-PIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cat08:
-; LINUX-64-PIC: 	movq	lptr(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	lptr(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cat08:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_lptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cat08:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	64(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	64([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cat08:
 ; DARWIN-32-PIC: 	calll	L119$pb
 ; DARWIN-32-PIC-NEXT: L119$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_lptr-L119$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	64(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lptr-L119$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	64([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cat08:
-; DARWIN-64-STATIC: 	movq	_lptr(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_lptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cat08:
-; DARWIN-64-DYNAMIC: 	movq	_lptr(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_lptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cat08:
-; DARWIN-64-PIC: 	movq	_lptr(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	64(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_lptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	64([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7680,53 +7691,53 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cam00:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	src+262144(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	src+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cam00:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	src+262144(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	src+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cam00:
-; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	src at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cam00:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_src+262144(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_src+262144(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cam00:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_src$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam00:
 ; DARWIN-32-PIC: 	calll	L120$pb
 ; DARWIN-32-PIC-NEXT: L120$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L120$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_src$non_lazy_ptr-L120$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cam00:
-; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cam00:
-; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cam00:
-; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_src at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7741,53 +7752,53 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cxm00:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	xsrc+262144(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	xsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cxm00:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	xsrc+262144(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	xsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cxm00:
-; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cxm00:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_xsrc+262144(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_xsrc+262144(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cxm00:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xsrc$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cxm00:
 ; DARWIN-32-PIC: 	calll	L121$pb
 ; DARWIN-32-PIC-NEXT: L121$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L121$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xsrc$non_lazy_ptr-L121$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cxm00:
-; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cxm00:
-; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cxm00:
-; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_xsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7802,53 +7813,53 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cam01:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	dst+262144(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	dst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cam01:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	dst+262144(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	dst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cam01:
-; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cam01:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_dst+262144(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_dst+262144(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cam01:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_dst$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam01:
 ; DARWIN-32-PIC: 	calll	L122$pb
 ; DARWIN-32-PIC-NEXT: L122$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L122$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_dst$non_lazy_ptr-L122$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cam01:
-; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cam01:
-; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cam01:
-; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_dst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7864,52 +7875,52 @@
 
 ; LINUX-32-STATIC: cxm01:
 ; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	xdst+262144(,%eax,4), %eax
+; LINUX-32-STATIC-NEXT: 	leal	xdst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cxm01:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	xdst+262144(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	xdst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cxm01:
-; LINUX-64-PIC: 	movq	xdst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cxm01:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_xdst+262144(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_xdst+262144(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cxm01:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	L_xdst$non_lazy_ptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cxm01:
 ; DARWIN-32-PIC: 	calll	L123$pb
 ; DARWIN-32-PIC-NEXT: L123$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L123$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_xdst$non_lazy_ptr-L123$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cxm01:
-; DARWIN-64-STATIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cxm01:
-; DARWIN-64-DYNAMIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cxm01:
-; DARWIN-64-PIC: 	movq	_xdst at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_xdst at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7921,67 +7932,67 @@
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC: cam02:
-; LINUX-64-STATIC: movq    ptr(%rip), %rax
-; LINUX-64-STATIC: leaq    262144(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: movq    ptr(%rip), [[RAX:%r.x]]
+; LINUX-64-STATIC: leaq    262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cam02:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-STATIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cam02:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	ptr, %ecx
-; LINUX-32-PIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	ptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cam02:
-; LINUX-64-PIC: 	movq	ptr at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	(%rax), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cam02:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_ptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_ptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cam02:
-; DARWIN-32-DYNAMIC: 	movl	L_ptr$non_lazy_ptr, %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	262144(%eax,%ecx,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	L_ptr$non_lazy_ptr, [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam02:
 ; DARWIN-32-PIC: 	calll	L124$pb
 ; DARWIN-32-PIC-NEXT: L124$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L124$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ptr$non_lazy_ptr-L124$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cam02:
-; DARWIN-64-STATIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	movq	(%rax), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cam02:
-; DARWIN-64-DYNAMIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	movq	(%rax), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cam02:
-; DARWIN-64-PIC: 	movq	_ptr at GOTPCREL(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	movq	(%rax), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_ptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -7996,51 +8007,51 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cam03:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	dsrc+262144(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	dsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cam03:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	dsrc+262144(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	dsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cam03:
-; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	dsrc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cam03:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_dsrc+262144(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_dsrc+262144(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cam03:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_dsrc+262144(,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_dsrc+262144(,[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam03:
 ; DARWIN-32-PIC: 	calll	L125$pb
 ; DARWIN-32-PIC-NEXT: L125$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_dsrc-L125$pb)+262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_dsrc-L125$pb)+262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cam03:
-; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cam03:
-; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cam03:
-; DARWIN-64-PIC: 	leaq	_dsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	leaq	_dsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -8055,51 +8066,51 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cam04:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	ddst+262144(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cam04:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	ddst+262144(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	ddst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cam04:
-; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	ddst at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cam04:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_ddst+262144(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_ddst+262144(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cam04:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_ddst+262144(,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_ddst+262144(,[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam04:
 ; DARWIN-32-PIC: 	calll	L126$pb
 ; DARWIN-32-PIC-NEXT: L126$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L126$pb)+262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ddst-L126$pb)+262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cam04:
-; DARWIN-64-STATIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cam04:
-; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cam04:
-; DARWIN-64-PIC: 	leaq	_ddst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	leaq	_ddst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -8111,62 +8122,62 @@
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC: cam05:
-; LINUX-64-STATIC: movq    dptr(%rip), %rax
-; LINUX-64-STATIC: leaq    262144(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: movq    dptr(%rip), [[RAX:%r.x]]
+; LINUX-64-STATIC: leaq    262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cam05:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	dptr, %ecx
-; LINUX-32-STATIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cam05:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	dptr, %ecx
-; LINUX-32-PIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	dptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cam05:
-; LINUX-64-PIC: 	movq	dptr at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	movq	(%rax), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	dptr at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	([[RAX]]), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cam05:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_dptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_dptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cam05:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_dptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam05:
 ; DARWIN-32-PIC: 	calll	L127$pb
 ; DARWIN-32-PIC-NEXT: L127$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_dptr-L127$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_dptr-L127$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cam05:
-; DARWIN-64-STATIC: 	movq	_dptr(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_dptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cam05:
-; DARWIN-64-DYNAMIC: 	movq	_dptr(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_dptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cam05:
-; DARWIN-64-PIC: 	movq	_dptr(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_dptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -8181,51 +8192,51 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cam06:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	lsrc+262144(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	lsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cam06:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	lsrc+262144(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	lsrc+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cam06:
-; LINUX-64-PIC: 	leaq	lsrc(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	leaq	lsrc(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cam06:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_lsrc+262144(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_lsrc+262144(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cam06:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_lsrc+262144(,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_lsrc+262144(,[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam06:
 ; DARWIN-32-PIC: 	calll	L128$pb
 ; DARWIN-32-PIC-NEXT: L128$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_lsrc-L128$pb)+262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_lsrc-L128$pb)+262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cam06:
-; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cam06:
-; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cam06:
-; DARWIN-64-PIC: 	leaq	_lsrc(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	leaq	_lsrc(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -8240,51 +8251,51 @@
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cam07:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	leal	ldst+262144(,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cam07:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	leal	ldst+262144(,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	ldst+262144(,[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cam07:
-; LINUX-64-PIC: 	leaq	ldst(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	leaq	ldst(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cam07:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	leal	_ldst+262144(,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	_ldst+262144(,[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cam07:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	leal	_ldst+262144(,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	_ldst+262144(,[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam07:
 ; DARWIN-32-PIC: 	calll	L129$pb
 ; DARWIN-32-PIC-NEXT: L129$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L129$pb)+262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	(_ldst-L129$pb)+262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cam07:
-; DARWIN-64-STATIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cam07:
-; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cam07:
-; DARWIN-64-PIC: 	leaq	_ldst(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	leaq	_ldst(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -8296,61 +8307,61 @@
 	%3 = bitcast i32* %2 to i8*
 	ret i8* %3
 ; LINUX-64-STATIC: cam08:
-; LINUX-64-STATIC: movq    lptr(%rip), %rax
-; LINUX-64-STATIC: leaq    262144(%rax,%rdi,4), %rax
+; LINUX-64-STATIC: movq    lptr(%rip), [[RAX:%r.x]]
+; LINUX-64-STATIC: leaq    262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-STATIC: ret
 
 ; LINUX-32-STATIC: cam08:
-; LINUX-32-STATIC: 	movl	4(%esp), %eax
-; LINUX-32-STATIC-NEXT: 	movl	lptr, %ecx
-; LINUX-32-STATIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; LINUX-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
+; LINUX-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-STATIC-NEXT: 	ret
 
 ; LINUX-32-PIC: cam08:
-; LINUX-32-PIC: 	movl	4(%esp), %eax
-; LINUX-32-PIC-NEXT: 	movl	lptr, %ecx
-; LINUX-32-PIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; LINUX-32-PIC: 	movl	4(%esp), [[EAX:%e.x]]
+; LINUX-32-PIC-NEXT: 	movl	lptr, [[ECX:%e.x]]
+; LINUX-32-PIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: cam08:
-; LINUX-64-PIC: 	movq	lptr(%rip), %rax
-; LINUX-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; LINUX-64-PIC: 	movq	lptr(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _cam08:
-; DARWIN-32-STATIC: 	movl	4(%esp), %eax
-; DARWIN-32-STATIC-NEXT: 	movl	_lptr, %ecx
-; DARWIN-32-STATIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; DARWIN-32-STATIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	movl	_lptr, [[ECX:%e.x]]
+; DARWIN-32-STATIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-STATIC-NEXT: 	ret
 
 ; DARWIN-32-DYNAMIC: _cam08:
-; DARWIN-32-DYNAMIC: 	movl	4(%esp), %eax
-; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, %ecx
-; DARWIN-32-DYNAMIC-NEXT: 	leal	262144(%ecx,%eax,4), %eax
+; DARWIN-32-DYNAMIC: 	movl	4(%esp), [[EAX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	movl	_lptr, [[ECX:%e.x]]
+; DARWIN-32-DYNAMIC-NEXT: 	leal	262144([[ECX]],[[EAX]],4), %eax
 ; DARWIN-32-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-32-PIC: _cam08:
 ; DARWIN-32-PIC: 	calll	L130$pb
 ; DARWIN-32-PIC-NEXT: L130$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	4(%esp), %ecx
-; DARWIN-32-PIC-NEXT: 	movl	_lptr-L130$pb(%eax), %eax
-; DARWIN-32-PIC-NEXT: 	leal	262144(%eax,%ecx,4), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	4(%esp), [[ECX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	_lptr-L130$pb([[EAX]]), [[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	262144([[EAX]],[[ECX]],4), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _cam08:
-; DARWIN-64-STATIC: 	movq	_lptr(%rip), %rax
-; DARWIN-64-STATIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-STATIC: 	movq	_lptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _cam08:
-; DARWIN-64-DYNAMIC: 	movq	_lptr(%rip), %rax
-; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-DYNAMIC: 	movq	_lptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _cam08:
-; DARWIN-64-PIC: 	movq	_lptr(%rip), %rax
-; DARWIN-64-PIC-NEXT: 	leaq	262144(%rax,%rdi,4), %rax
+; DARWIN-64-PIC: 	movq	_lptr(%rip), [[RAX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	leaq	262144([[RAX]],%rdi,4), %rax
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -8648,8 +8659,8 @@
 ; DARWIN-32-PIC: _address:
 ; DARWIN-32-PIC: 	calll	L133$pb
 ; DARWIN-32-PIC-NEXT: L133$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_callee$non_lazy_ptr-L133$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_callee$non_lazy_ptr-L133$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _address:
@@ -8697,8 +8708,8 @@
 ; DARWIN-32-PIC: _laddress:
 ; DARWIN-32-PIC: 	calll	L134$pb
 ; DARWIN-32-PIC-NEXT: L134$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_lcallee-L134$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_lcallee-L134$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _laddress:
@@ -8744,8 +8755,8 @@
 ; DARWIN-32-PIC: _daddress:
 ; DARWIN-32-PIC: 	calll	L135$pb
 ; DARWIN-32-PIC-NEXT: L135$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	leal	_dcallee-L135$pb(%eax), %eax
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	leal	_dcallee-L135$pb([[EAX]]), %eax
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _daddress:
@@ -9206,11 +9217,11 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: icaller:
-; LINUX-64-PIC: 	pushq	%rbx
-; LINUX-64-PIC-NEXT: 	movq	ifunc at GOTPCREL(%rip), %rbx
-; LINUX-64-PIC-NEXT: 	callq	*(%rbx)
-; LINUX-64-PIC-NEXT: 	callq	*(%rbx)
-; LINUX-64-PIC-NEXT: 	popq	%rbx
+; LINUX-64-PIC: 	pushq	[[RBX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	ifunc at GOTPCREL(%rip), [[RBX:%r.x]]
+; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
+; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
+; LINUX-64-PIC-NEXT: 	popq	[[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _icaller:
@@ -9235,8 +9246,8 @@
 ; DARWIN-32-PIC-NEXT: 	subl	$8, %esp
 ; DARWIN-32-PIC-NEXT: 	calll	L142$pb
 ; DARWIN-32-PIC-NEXT: L142$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_ifunc$non_lazy_ptr-L142$pb(%eax), %esi
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ifunc$non_lazy_ptr-L142$pb([[EAX]]), %esi
 ; DARWIN-32-PIC-NEXT: 	calll	*(%esi)
 ; DARWIN-32-PIC-NEXT: 	calll	*(%esi)
 ; DARWIN-32-PIC-NEXT: 	addl	$8, %esp
@@ -9244,27 +9255,27 @@
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _icaller:
-; DARWIN-64-STATIC: 	pushq	%rbx
-; DARWIN-64-STATIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), %rbx
-; DARWIN-64-STATIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-STATIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-STATIC-NEXT: 	popq	%rbx
+; DARWIN-64-STATIC: 	pushq	[[RBX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), [[RBX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-STATIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-STATIC-NEXT: 	popq	[[RBX:%r.x]]
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _icaller:
-; DARWIN-64-DYNAMIC: 	pushq	%rbx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), %rbx
-; DARWIN-64-DYNAMIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-DYNAMIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-DYNAMIC-NEXT: 	popq	%rbx
+; DARWIN-64-DYNAMIC: 	pushq	[[RBX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), [[RBX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-DYNAMIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-DYNAMIC-NEXT: 	popq	[[RBX:%r.x]]
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _icaller:
-; DARWIN-64-PIC: 	pushq	%rbx
-; DARWIN-64-PIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), %rbx
-; DARWIN-64-PIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-PIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-PIC-NEXT: 	popq	%rbx
+; DARWIN-64-PIC: 	pushq	[[RBX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), [[RBX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-PIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-PIC-NEXT: 	popq	[[RBX:%r.x]]
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -9296,11 +9307,11 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: dicaller:
-; LINUX-64-PIC: 	pushq	%rbx
-; LINUX-64-PIC-NEXT: 	movq	difunc at GOTPCREL(%rip), %rbx
-; LINUX-64-PIC-NEXT: 	callq	*(%rbx)
-; LINUX-64-PIC-NEXT: 	callq	*(%rbx)
-; LINUX-64-PIC-NEXT: 	popq	%rbx
+; LINUX-64-PIC: 	pushq	[[RBX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	difunc at GOTPCREL(%rip), [[RBX:%r.x]]
+; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
+; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
+; LINUX-64-PIC-NEXT: 	popq	[[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _dicaller:
@@ -9461,11 +9472,11 @@
 ; LINUX-32-PIC-NEXT: 	ret
 
 ; LINUX-64-PIC: itailcaller:
-; LINUX-64-PIC: 	pushq	%rbx
-; LINUX-64-PIC-NEXT: 	movq	ifunc at GOTPCREL(%rip), %rbx
-; LINUX-64-PIC-NEXT: 	callq	*(%rbx)
-; LINUX-64-PIC-NEXT: 	callq	*(%rbx)
-; LINUX-64-PIC-NEXT: 	popq	%rbx
+; LINUX-64-PIC: 	pushq	[[RBX:%r.x]]
+; LINUX-64-PIC-NEXT: 	movq	ifunc at GOTPCREL(%rip), [[RBX:%r.x]]
+; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
+; LINUX-64-PIC-NEXT: 	callq	*([[RBX]])
+; LINUX-64-PIC-NEXT: 	popq	[[RBX:%r.x]]
 ; LINUX-64-PIC-NEXT: 	ret
 
 ; DARWIN-32-STATIC: _itailcaller:
@@ -9490,8 +9501,8 @@
 ; DARWIN-32-PIC-NEXT: 	subl	$8, %esp
 ; DARWIN-32-PIC-NEXT: 	calll	L145$pb
 ; DARWIN-32-PIC-NEXT: L145$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	movl	L_ifunc$non_lazy_ptr-L145$pb(%eax), %esi
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	movl	L_ifunc$non_lazy_ptr-L145$pb([[EAX]]), %esi
 ; DARWIN-32-PIC-NEXT: 	calll	*(%esi)
 ; DARWIN-32-PIC-NEXT: 	calll	*(%esi)
 ; DARWIN-32-PIC-NEXT: 	addl	$8, %esp
@@ -9499,27 +9510,27 @@
 ; DARWIN-32-PIC-NEXT: 	ret
 
 ; DARWIN-64-STATIC: _itailcaller:
-; DARWIN-64-STATIC: 	pushq	%rbx
-; DARWIN-64-STATIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), %rbx
-; DARWIN-64-STATIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-STATIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-STATIC-NEXT: 	popq	%rbx
+; DARWIN-64-STATIC: 	pushq	[[RBX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), [[RBX:%r.x]]
+; DARWIN-64-STATIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-STATIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-STATIC-NEXT: 	popq	[[RBX:%r.x]]
 ; DARWIN-64-STATIC-NEXT: 	ret
 
 ; DARWIN-64-DYNAMIC: _itailcaller:
-; DARWIN-64-DYNAMIC: 	pushq	%rbx
-; DARWIN-64-DYNAMIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), %rbx
-; DARWIN-64-DYNAMIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-DYNAMIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-DYNAMIC-NEXT: 	popq	%rbx
+; DARWIN-64-DYNAMIC: 	pushq	[[RBX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), [[RBX:%r.x]]
+; DARWIN-64-DYNAMIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-DYNAMIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-DYNAMIC-NEXT: 	popq	[[RBX:%r.x]]
 ; DARWIN-64-DYNAMIC-NEXT: 	ret
 
 ; DARWIN-64-PIC: _itailcaller:
-; DARWIN-64-PIC: 	pushq	%rbx
-; DARWIN-64-PIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), %rbx
-; DARWIN-64-PIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-PIC-NEXT: 	callq	*(%rbx)
-; DARWIN-64-PIC-NEXT: 	popq	%rbx
+; DARWIN-64-PIC: 	pushq	[[RBX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	movq	_ifunc at GOTPCREL(%rip), [[RBX:%r.x]]
+; DARWIN-64-PIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-PIC-NEXT: 	callq	*([[RBX]])
+; DARWIN-64-PIC-NEXT: 	popq	[[RBX:%r.x]]
 ; DARWIN-64-PIC-NEXT: 	ret
 }
 
@@ -9547,8 +9558,8 @@
 
 ; LINUX-64-PIC: ditailcaller:
 ; LINUX-64-PIC: 	pushq
-; LINUX-64-PIC-NEXT: 	movq	difunc at GOTPCREL(%rip), %rax
-; LINUX-64-PIC-NEXT: 	callq	*(%rax)
+; LINUX-64-PIC-NEXT: 	movq	difunc at GOTPCREL(%rip), [[RAX:%r.x]]
+; LINUX-64-PIC-NEXT: 	callq	*([[RAX]])
 ; LINUX-64-PIC-NEXT: 	popq
 ; LINUX-64-PIC-NEXT: 	ret
 
@@ -9568,8 +9579,8 @@
 ; DARWIN-32-PIC: 	subl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	calll	L146$pb
 ; DARWIN-32-PIC-NEXT: L146$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	calll	*_difunc-L146$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	calll	*_difunc-L146$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 
@@ -9635,8 +9646,8 @@
 ; DARWIN-32-PIC: 	subl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	calll	L147$pb
 ; DARWIN-32-PIC-NEXT: L147$pb:
-; DARWIN-32-PIC-NEXT: 	popl	%eax
-; DARWIN-32-PIC-NEXT: 	calll	*_lifunc-L147$pb(%eax)
+; DARWIN-32-PIC-NEXT: 	popl	[[EAX:%e.x]]
+; DARWIN-32-PIC-NEXT: 	calll	*_lifunc-L147$pb([[EAX]])
 ; DARWIN-32-PIC-NEXT: 	addl	$12, %esp
 ; DARWIN-32-PIC-NEXT: 	ret
 



From rdivacky at freebsd.org  Tue Apr  5 15:25:36 2011
From: rdivacky at freebsd.org (Roman Divacky)
Date: Tue, 05 Apr 2011 20:25:36 -0000
Subject: [llvm-commits] [llvm] r128920 - /llvm/trunk/lib/Support/Host.cpp
Message-ID: <20110405202536.443972A6C12D@llvm.org>

Author: rdivacky
Date: Tue Apr  5 15:25:36 2011
New Revision: 128920

URL: http://llvm.org/viewvc/llvm-project?rev=128920&view=rev
Log:
Add support for detection of Intel SandyBridge.


Modified:
    llvm/trunk/lib/Support/Host.cpp

Modified: llvm/trunk/lib/Support/Host.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=128920&r1=128919&r2=128920&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Host.cpp (original)
+++ llvm/trunk/lib/Support/Host.cpp Tue Apr  5 15:25:36 2011
@@ -214,6 +214,8 @@
                // As found in a Summer 2010 model iMac.
       case 37: // Intel Core i7, laptop version.
         return "corei7";
+      case 42: // SandyBridge
+        return "sandybridge";
 
       case 28: // Intel Atom processor. All processors are manufactured using
                // the 45 nm process



From johnny.chen at apple.com  Tue Apr  5 15:32:23 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 20:32:23 -0000
Subject: [llvm-commits] [llvm] r128922 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
 test/MC/Disassembler/ARM/arm-tests.txt
Message-ID: <20110405203223.41A102A6C12D@llvm.org>

Author: johnny
Date: Tue Apr  5 15:32:23 2011
New Revision: 128922

URL: http://llvm.org/viewvc/llvm-project?rev=128922&view=rev
Log:
The r128085 checkin modified the operand ordering for MRC/MRC2 instructions.
Modify DisassembleCoprocessor() of ARMDisassemblerCore.cpp to react to the change.

rdar://problem/9236873

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128922&r1=128921&r2=128922&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Apr  5 15:32:23 2011
@@ -681,10 +681,17 @@
   // CDP/CDP2 has no GPR operand; the opc1 operand is also wider (Inst{23-20}).
   bool NoGPR = (Opcode == ARM::CDP || Opcode == ARM::CDP2);
   bool LdStCop = LdStCopOpcode(Opcode);
+  bool RtOut = (Opcode == ARM::MRC || Opcode == ARM::MRC2);
 
   OpIdx = 0;
 
+  if (RtOut) {
+    MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
+                                                       decodeRd(insn))));
+    ++OpIdx;
+  }
   MI.addOperand(MCOperand::CreateImm(GetCoprocessor(insn)));
+  ++OpIdx;
 
   if (LdStCop) {
     // Unindex if P:W = 0b00 --> _OPTION variant
@@ -694,6 +701,7 @@
 
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        decodeRn(insn))));
+    OpIdx += 2;
 
     if (PW) {
       MI.addOperand(MCOperand::CreateReg(0));
@@ -704,19 +712,23 @@
       unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2,
                                           ARM_AM::no_shift, IndexMode);
       MI.addOperand(MCOperand::CreateImm(Offset));
-      OpIdx = 5;
+      OpIdx += 2;
     } else {
       MI.addOperand(MCOperand::CreateImm(slice(insn, 7, 0)));
-      OpIdx = 4;
+      ++OpIdx;
     }
   } else {
     MI.addOperand(MCOperand::CreateImm(OneCopOpc ? GetCopOpc(insn)
                                                  : GetCopOpc1(insn, NoGPR)));
+    ++OpIdx;
 
-    MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
-                        : MCOperand::CreateReg(
-                            getRegisterEnum(B, ARM::GPRRegClassID,
-                                            decodeRd(insn))));
+    if (!RtOut) {
+      MI.addOperand(NoGPR ? MCOperand::CreateImm(decodeRd(insn))
+                          : MCOperand::CreateReg(
+                                getRegisterEnum(B, ARM::GPRRegClassID,
+                                                decodeRd(insn))));
+      ++OpIdx;
+    }
 
     MI.addOperand(OneCopOpc ? MCOperand::CreateReg(
                                 getRegisterEnum(B, ARM::GPRRegClassID,
@@ -725,7 +737,7 @@
 
     MI.addOperand(MCOperand::CreateImm(decodeRm(insn)));
 
-    OpIdx = 5;
+    OpIdx += 2;
 
     if (!OneCopOpc) {
       MI.addOperand(MCOperand::CreateImm(GetCopOpc2(insn)));

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=128922&r1=128921&r2=128922&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Tue Apr  5 15:32:23 2011
@@ -236,3 +236,6 @@
 
 # CHECK:	streq	r1, [sp], #-1567
 0x1f 0x16 0xd 0x4
+
+# CHECK:	mrchs	p2, #3, r11, c13, c6, #6
+0xd6 0xb2 0x7d 0x2e



From nicholas at mxc.ca  Tue Apr  5 15:39:27 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 05 Apr 2011 20:39:27 -0000
Subject: [llvm-commits] [llvm] r128924 - in
 /llvm/trunk/lib/Transforms/Instrumentation: MaximumSpanningTree.h
 OptimalEdgeProfiling.cpp
Message-ID: <20110405203927.E36F22A6C12D@llvm.org>

Author: nicholas
Date: Tue Apr  5 15:39:27 2011
New Revision: 128924

URL: http://llvm.org/viewvc/llvm-project?rev=128924&view=rev
Log:
Fix typos. Adjust some whitespace for style. No functionality change.

Modified:
    llvm/trunk/lib/Transforms/Instrumentation/MaximumSpanningTree.h
    llvm/trunk/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp

Modified: llvm/trunk/lib/Transforms/Instrumentation/MaximumSpanningTree.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/MaximumSpanningTree.h?rev=128924&r1=128923&r2=128924&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/MaximumSpanningTree.h (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/MaximumSpanningTree.h Tue Apr  5 15:39:27 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This module privides means for calculating a maximum spanning tree for a
+// This module provides means for calculating a maximum spanning tree for a
 // given set of weighted edges. The type parameter T is the type of a node.
 //
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp?rev=128924&r1=128923&r2=128924&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/OptimalEdgeProfiling.cpp Tue Apr  5 15:39:27 2011
@@ -120,14 +120,14 @@
   NumEdgesInserted = 0;
 
   std::vector<Constant*> Initializer(NumEdges);
-  Constant* Zero = ConstantInt::get(Int32, 0);
-  Constant* Uncounted = ConstantInt::get(Int32, ProfileInfoLoader::Uncounted);
+  Constant *Zero = ConstantInt::get(Int32, 0);
+  Constant *Uncounted = ConstantInt::get(Int32, ProfileInfoLoader::Uncounted);
 
   // Instrument all of the edges not in MST...
   unsigned i = 0;
   for (Module::iterator F = M.begin(), E = M.end(); F != E; ++F) {
     if (F->isDeclaration()) continue;
-    DEBUG(dbgs()<<"Working on "<<F->getNameStr()<<"\n");
+    DEBUG(dbgs() << "Working on " << F->getNameStr() << "\n");
 
     // Calculate a Maximum Spanning Tree with the edge weights determined by
     // ProfileEstimator. ProfileEstimator also assign weights to the virtual
@@ -139,17 +139,17 @@
     ProfileInfo::EdgeWeights ECs =
       getAnalysis<ProfileInfo>(*F).getEdgeWeights(F);
     std::vector<ProfileInfo::EdgeWeight> EdgeVector(ECs.begin(), ECs.end());
-    MaximumSpanningTree<BasicBlock> MST (EdgeVector);
-    std::stable_sort(MST.begin(),MST.end());
+    MaximumSpanningTree<BasicBlock> MST(EdgeVector);
+    std::stable_sort(MST.begin(), MST.end());
 
     // Check if (0,entry) not in the MST. If not, instrument edge
     // (IncrementCounterInBlock()) and set the counter initially to zero, if
     // the edge is in the MST the counter is initialised to -1.
 
     BasicBlock *entry = &(F->getEntryBlock());
-    ProfileInfo::Edge edge = ProfileInfo::getEdge(0,entry);
+    ProfileInfo::Edge edge = ProfileInfo::getEdge(0, entry);
     if (!std::binary_search(MST.begin(), MST.end(), edge)) {
-      printEdgeCounter(edge,entry,i);
+      printEdgeCounter(edge, entry, i);
       IncrementCounterInBlock(entry, i, Counters); ++NumEdgesInserted;
       Initializer[i++] = (Zero);
     } else{
@@ -170,9 +170,9 @@
       // has no successors, the virtual edge (BB,0) is processed.
       TerminatorInst *TI = BB->getTerminator();
       if (TI->getNumSuccessors() == 0) {
-        ProfileInfo::Edge edge = ProfileInfo::getEdge(BB,0);
+        ProfileInfo::Edge edge = ProfileInfo::getEdge(BB, 0);
         if (!std::binary_search(MST.begin(), MST.end(), edge)) {
-          printEdgeCounter(edge,BB,i);
+          printEdgeCounter(edge, BB, i);
           IncrementCounterInBlock(BB, i, Counters); ++NumEdgesInserted;
           Initializer[i++] = (Zero);
         } else{
@@ -195,11 +195,11 @@
           // otherwise insert it in the successor block.
           if (TI->getNumSuccessors() == 1) {
             // Insert counter at the start of the block
-            printEdgeCounter(edge,BB,i);
+            printEdgeCounter(edge, BB, i);
             IncrementCounterInBlock(BB, i, Counters); ++NumEdgesInserted;
           } else {
             // Insert counter at the start of the block
-            printEdgeCounter(edge,Succ,i);
+            printEdgeCounter(edge, Succ, i);
             IncrementCounterInBlock(Succ, i, Counters); ++NumEdgesInserted;
           }
           Initializer[i++] = (Zero);
@@ -212,9 +212,9 @@
 
   // Check if the number of edges counted at first was the number of edges we
   // considered for instrumentation.
-  assert(i==NumEdges && "the number of edges in counting array is wrong");
+  assert(i == NumEdges && "the number of edges in counting array is wrong");
 
-  // Assing the now completely defined initialiser to the array.
+  // Assign the now completely defined initialiser to the array.
   Constant *init = ConstantArray::get(ATy, Initializer);
   Counters->setInitializer(init);
 



From bob.wilson at apple.com  Tue Apr  5 15:44:15 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 05 Apr 2011 20:44:15 -0000
Subject: [llvm-commits] [llvm] r128925 -
	/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
Message-ID: <20110405204415.D3B362A6C12D@llvm.org>

Author: bwilson
Date: Tue Apr  5 15:44:15 2011
New Revision: 128925

URL: http://llvm.org/viewvc/llvm-project?rev=128925&view=rev
Log:
Add an assertion instead of crashing when the scavenger goes past the end
of a basic block.

Modified:
    llvm/trunk/lib/CodeGen/RegisterScavenging.cpp

Modified: llvm/trunk/lib/CodeGen/RegisterScavenging.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterScavenging.cpp?rev=128925&r1=128924&r2=128925&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterScavenging.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterScavenging.cpp Tue Apr  5 15:44:15 2011
@@ -126,9 +126,10 @@
     MBBI = MBB->begin();
     Tracking = true;
   } else {
-    assert(MBBI != MBB->end() && "Already at the end of the basic block!");
+    assert(MBBI != MBB->end() && "Already past the end of the basic block!");
     MBBI = llvm::next(MBBI);
   }
+  assert(MBBI != MBB->end() && "Already at the end of the basic block!");
 
   MachineInstr *MI = MBBI;
 



From aggarwa4 at illinois.edu  Tue Apr  5 15:54:12 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 05 Apr 2011 20:54:12 -0000
Subject: [llvm-commits] [poolalloc] r128926 -
	/poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp
Message-ID: <20110405205412.4E1722A6C12D@llvm.org>

Author: aggarwa4
Date: Tue Apr  5 15:54:12 2011
New Revision: 128926

URL: http://llvm.org/viewvc/llvm-project?rev=128926&view=rev
Log:
Added comments and debug printing.

Modified:
    poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp

Modified: poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp?rev=128926&r1=128925&r2=128926&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp Tue Apr  5 15:54:12 2011
@@ -6,6 +6,12 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+// Convert calls of type 
+// call(bitcast F to (...)*) () 
+// to 
+// call F()
+// if the number and types of arguments passed matches.
+//===----------------------------------------------------------------------===//
 #define DEBUG_TYPE "varargfunc"
 
 #include "llvm/Instructions.h"
@@ -22,6 +28,7 @@
 
 using namespace llvm;
 
+// Pass statistics
 STATISTIC(numSimplified, "Number of Calls Simplified");
 
 namespace {
@@ -29,32 +36,55 @@
   public:
     static char ID;
     VarArgsFunc() : ModulePass(&ID) {}
+
+    //
+    // Method: runOnModule()
+    // Description:
+    //  Entry point for this LLVM pass. Search for functions that are
+    //  unnecessarily casted to varargs type, in a CallInst.
+    //  Replace with direct calls to the function
+    //
+    // Inputs:
+    // M - A reference to the LLVM module to transform.
+    //
+    // Outputs:
+    // M - The transformed LLVM module.
+    //
+    // Return value:
+    //  true  - The module was modified.
+    //  false - The module was not modified.
+    //
     bool runOnModule(Module& M) {
-      bool changed = false;
       std::vector<CallInst*> worklist;
+
       for (Module::iterator I = M.begin(); I != M.end(); ++I) {
-        if (!I->isDeclaration() && !I->mayBeOverridden()) {
-          //Call Sites
-          for(Value::use_iterator ui = I->use_begin(), ue = I->use_end();
-              ui != ue; ++ui) 
-            //Bitcast
-            if (Constant *C = dyn_cast<Constant>(ui)) 
-              if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) 
-                if (CE->getOpcode() == Instruction::BitCast) 
-                  if(CE->getOperand(0) == I) 
-                    if(const FunctionType *FTy  = dyn_cast<FunctionType>
-                       ((cast<PointerType>(CE->getType()))->getElementType())) 
-                      //casting to a varargs funtion
-                      if(FTy->isVarArg()) 
-                        for(Value::use_iterator uii = CE->use_begin(),
-                            uee = CE->use_end(); uii != uee; ++uii) 
-                          if (CallInst* CI = dyn_cast<CallInst>(uii)) 
-                            if(CI->getCalledValue() == CE) 
-                               worklist.push_back(CI);
-        }
+        // Go through all the functions
+        if (I->mayBeOverridden()) 
+          continue;
+        //Uses of Function I
+        for(Value::use_iterator ui = I->use_begin(), ue = I->use_end();
+            ui != ue; ++ui) 
+          //Find all casted uses of the function
+          if (Constant *C = dyn_cast<Constant>(ui)) 
+            if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) 
+              if (CE->getOpcode() == Instruction::BitCast) 
+                if(CE->getOperand(0) == I) 
+                  if(const FunctionType *FTy  = dyn_cast<FunctionType>
+                     ((cast<PointerType>(CE->getType()))->getElementType())) 
+                    //casting to a varargs funtion
+                    if(FTy->isVarArg()) { 
+                      // Check if bitcasted Value is used in a callInst
+                      for(Value::use_iterator uii = CE->use_begin(),
+                          uee = CE->use_end(); uii != uee; ++uii) 
+                        if (CallInst* CI = dyn_cast<CallInst>(uii)) 
+                          if(CI->getCalledValue() == CE) { 
+                            // add to a worklist to process
+                            worklist.push_back(CI);
+                          }
+                    }
       }
+      
       // process the worklist
-
       while(!worklist.empty()) {
         CallInst *CI = worklist.back();
         worklist.pop_back();
@@ -66,9 +96,8 @@
         // Or we can discard the returned value.
         if(F->getReturnType() != CI->getType()) {
           if(!CI->use_empty())
-          continue;
+            continue;
         }
-
         // Check if the parameters passed match the expected types of the 
         // formal arguments
         bool change = true;
@@ -79,28 +108,35 @@
             break;
           }
         }
-        
+
         if(change) {
-            // if we want to ignore the returned value, create a new CallInst
-            SmallVector<Value*, 8> Args;
-            for(unsigned j =1;j<CI->getNumOperands();j++) {
-              Args.push_back(CI->getOperand(j));
-            }
-            CallInst *CINew = CallInst::Create(F, Args.begin(), Args.end(), "", CI);
-            if(F->getReturnType() == CI->getType()){ // else means no uses
-              CI->replaceAllUsesWith(CINew);
-            }
-            CI->eraseFromParent();
-            // else just set the function to call the original function.
-          changed = true;
+          // if we want to ignore the returned value, create a new CallInst
+          SmallVector<Value*, 8> Args;
+          for(unsigned j =1;j<CI->getNumOperands();j++) {
+            Args.push_back(CI->getOperand(j));
+          }
+          CallInst *CINew = CallInst::Create(F, Args.begin(), Args.end(), "", CI);
+          if(F->getReturnType() == CI->getType()){ // else means no uses
+            CI->replaceAllUsesWith(CINew);
+          }
+          DEBUG(errs() << "VA:");
+          DEBUG(errs() << "ERASE:");
+          DEBUG(CI->dump());
+          DEBUG(errs() << "VA:");
+          DEBUG(errs() << "ADDED:");
+          DEBUG(CINew->dump());
+          CI->eraseFromParent();
           numSimplified++;
         }
       }
-      return changed;
+      return (numSimplified > 0 );
     }
   };
 }
 
+// Pass ID variable
 char VarArgsFunc::ID = 0;
+
+// Register the Pass
 static RegisterPass<VarArgsFunc>
-X("varargsfunc", "Specialize for ill-defined non-varargs functions");
+X("varargsfunc", "Optimize non-varargs to varargs function casts");



From stoklund at 2pi.dk  Tue Apr  5 15:56:08 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 20:56:08 -0000
Subject: [llvm-commits] [llvm] r128927 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20110405205608.9686F2A6C12D@llvm.org>

Author: stoklund
Date: Tue Apr  5 15:56:08 2011
New Revision: 128927

URL: http://llvm.org/viewvc/llvm-project?rev=128927&view=rev
Log:
Document llvm/ADT/IntEqClasses.h in ProgrammersManual.html

Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=128927&r1=128926&r2=128927&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Tue Apr  5 15:56:08 2011
@@ -86,6 +86,7 @@
       <li><a href="#dss_valuemap">"llvm/ADT/ValueMap.h"</a></li>
       <li><a href="#dss_intervalmap">"llvm/ADT/IntervalMap.h"</a></li>
       <li><a href="#dss_map">&lt;map&gt;</a></li>
+      <li><a href="#dss_inteqclasses">"llvm/ADT/IntEqClasses.h"</a></li>
       <li><a href="#dss_othermap">Other Map-Like Container Options</a></li>
     </ul></li>
     <li><a href="#ds_string">String-like containers</a>
@@ -1547,6 +1548,26 @@
 
 <!-- _______________________________________________________________________ -->
 <div class="doc_subsubsection">
+  <a name="dss_inteqclasses">"llvm/ADT/IntEqClasses.h"</a>
+</div>
+
+<div class="doc_text">
+
+<p>IntEqClasses provides a compact representation of equivalence classes of
+small integers. Initially, each integer in the range 0..n-1 has its own
+equivalence class. Classes can be joined by passing two class representatives to
+the join(a, b) method. Two integers are in the same class when findLeader()
+returns the same representative.</p>
+
+<p>Once all equivalence classes are formed, the map can be compressed so each
+integer 0..n-1 maps to an equivalence class number in the range 0..m-1, where m
+is the total number of equivalence classes. The map must be uncompressed before
+it can be edited again.</p>
+
+</div>
+
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
   <a name="dss_othermap">Other Map-Like Container Options</a>
 </div>
 



From dpatel at apple.com  Tue Apr  5 16:08:24 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 05 Apr 2011 21:08:24 -0000
Subject: [llvm-commits] [llvm] r128929 - in
 /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfDebug.cpp DwarfDebug.h
Message-ID: <20110405210824.787692A6C12D@llvm.org>

Author: dpatel
Date: Tue Apr  5 16:08:24 2011
New Revision: 128929

URL: http://llvm.org/viewvc/llvm-project?rev=128929&view=rev
Log:
Refactor.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=128929&r1=128928&r2=128929&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Apr  5 16:08:24 2011
@@ -930,6 +930,20 @@
   return true;
 }
 
+/// addTemplateParams - Add template parameters in buffer.
+void DwarfDebug::addTemplateParams(DIE &Buffer, DIArray TParams) {
+  // Add template parameters.
+  for (unsigned i = 0, e = TParams.getNumElements(); i != e; ++i) {
+    DIDescriptor Element = TParams.getElement(i);
+    if (Element.isTemplateTypeParameter())
+      Buffer.addChild(getOrCreateTemplateTypeParameterDIE(
+                        DITemplateTypeParameter(Element)));
+    else if (Element.isTemplateValueParameter())
+      Buffer.addChild(getOrCreateTemplateValueParameterDIE(
+                        DITemplateValueParameter(Element)));
+  }
+
+}
 /// addToContextOwner - Add Die into the list of its context owner's children.
 void DwarfDebug::addToContextOwner(DIE *Die, DIDescriptor Context) {
   if (Context.isType()) {
@@ -1155,20 +1169,9 @@
       addToContextOwner(&Buffer, Context);
     }
 
-    if (Tag == dwarf::DW_TAG_class_type) {
-      DIArray TParams = CTy.getTemplateParams();
-      unsigned N = TParams.getNumElements();
-      // Add template parameters.
-      for (unsigned i = 0; i < N; ++i) {
-        DIDescriptor Element = TParams.getElement(i);
-        if (Element.isTemplateTypeParameter())
-          Buffer.addChild(getOrCreateTemplateTypeParameterDIE(
-                            DITemplateTypeParameter(Element)));
-        else if (Element.isTemplateValueParameter())
-          Buffer.addChild(getOrCreateTemplateValueParameterDIE(
-                            DITemplateValueParameter(Element)));
-      }
-    }
+    if (Tag == dwarf::DW_TAG_class_type) 
+      addTemplateParams(Buffer, CTy.getTemplateParams());
+
     break;
   }
   default:

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=128929&r1=128928&r2=128929&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Tue Apr  5 16:08:24 2011
@@ -39,7 +39,7 @@
 class DIE;
 class DIEBlock;
 class DIEEntry;
-
+class DIArray;
 class DIEnumerator;
 class DIDescriptor;
 class DIVariable;
@@ -320,6 +320,9 @@
   /// addConstantFPValue - Add constant value entry in variable DIE.
   bool addConstantFPValue(DIE *Die, const MachineOperand &MO);
 
+  /// addTemplateParams - Add template parameters in buffer.
+  void addTemplateParams(DIE &Buffer, DIArray TParams);
+
   /// addComplexAddress - Start with the address based on the location provided,
   /// and generate the DWARF information necessary to find the actual variable
   /// (navigating the extra location information encoded in the type) based on



From aggarwa4 at illinois.edu  Tue Apr  5 16:17:58 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 05 Apr 2011 21:17:58 -0000
Subject: [llvm-commits] [poolalloc] r128930 -
	/poolalloc/trunk/lib/AssistDS/SimplifyMRV.cpp
Message-ID: <20110405211758.70B7B2A6C12D@llvm.org>

Author: aggarwa4
Date: Tue Apr  5 16:17:58 2011
New Revision: 128930

URL: http://llvm.org/viewvc/llvm-project?rev=128930&view=rev
Log:
Added comments and debug printing.

Modified:
    poolalloc/trunk/lib/AssistDS/SimplifyMRV.cpp

Modified: poolalloc/trunk/lib/AssistDS/SimplifyMRV.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/SimplifyMRV.cpp?rev=128930&r1=128929&r2=128930&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/SimplifyMRV.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/SimplifyMRV.cpp Tue Apr  5 16:17:58 2011
@@ -6,6 +6,14 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
+//
+// Remove unnecessary insertvalue/extractvalue pairs
+// The name of the pass indicates that such pairs are mostly seen when 
+// mrv(s) occur.
+//
+// Derived from InstCombine
+//
+//===----------------------------------------------------------------------===//
 #define DEBUG_TYPE "simplifymrv"
 
 #include "llvm/Instructions.h"
@@ -24,157 +32,206 @@
 
 using namespace llvm;
 
-STATISTIC(numRemoved, "Number of Instructions Deleted");
+// Pass statistic
+STATISTIC(numErased, "Number of Instructions Deleted");
 
 namespace {
   class SimplifyMRV : public ModulePass {
   public:
     static char ID;
     SimplifyMRV() : ModulePass(&ID) {}
+    //
+    // Method: runOnModule()
+    //
+    // Description:
+    //  Entry point for this LLVM pass. Search for insert/extractvalue instructions
+    //  that can be simplified.
+    //
+    // Inputs:
+    //  M - A reference to the LLVM module to transform.
+    //
+    // Outputs:
+    //  M - The transformed LLVM module.
+    //
+    // Return value:
+    // true  - The module was modified.
+    // false - The module was not modified.
+    //
     bool runOnModule(Module& M) {
-      bool changed = false;
+      // Repeat till no change
+      bool changed;
       do {
         changed = false;
         for (Module::iterator F = M.begin(); F != M.end(); ++F) {
           for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {      
             for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
-              if(ExtractValueInst *EV = dyn_cast<ExtractValueInst>(I++)) {
-                Value *Agg = EV->getAggregateOperand();
-                if (!EV->hasIndices()) {
-                  EV->replaceAllUsesWith(Agg);
+              ExtractValueInst *EV = dyn_cast<ExtractValueInst>(I++);
+              if(!EV)
+                continue;
+              Value *Agg = EV->getAggregateOperand();
+              if (!EV->hasIndices()) {
+                EV->replaceAllUsesWith(Agg);
+                DEBUG(errs() << "MRV:");
+                DEBUG(errs() << "ERASE:");
+                DEBUG(EV->dump());
+                EV->eraseFromParent();
+                numErased++;
+                changed = true;
+                continue;
+              }
+              if (Constant *C = dyn_cast<Constant>(Agg)) {
+                if (isa<UndefValue>(C)) {
+                  EV->replaceAllUsesWith(UndefValue::get(EV->getType()));
+                  DEBUG(errs() << "MRV:");
+                  DEBUG(errs() << "ERASE:");
+                  DEBUG(EV->dump());
                   EV->eraseFromParent();
-                  numRemoved++;
+                  numErased++;
                   changed = true;
                   continue;
                 }
-                if (Constant *C = dyn_cast<Constant>(Agg)) {
-                  if (isa<UndefValue>(C)) {
-                    EV->replaceAllUsesWith(UndefValue::get(EV->getType()));
-                    EV->eraseFromParent();
-                    numRemoved++;
-                    changed = true;
-                    continue;
-                  }
-                  if (isa<ConstantAggregateZero>(C)) {
-                    EV->replaceAllUsesWith(Constant::getNullValue(EV->getType()));
-                    numRemoved++;
-                    EV->eraseFromParent();
-                    changed = true;
-                    continue;
-                  }
-                  if (isa<ConstantArray>(C) || isa<ConstantStruct>(C)) {
-                    // Extract the element indexed by the first index out of the constant
-                    Value *V = C->getOperand(*EV->idx_begin());
-                    if (EV->getNumIndices() > 1) {
-                      // Extract the remaining indices out of the constant indexed by the
-                      // first index
-                      ExtractValueInst *EV_new = ExtractValueInst::Create(V, EV->idx_begin() + 1, EV->idx_end(), "", EV);
-                      EV->replaceAllUsesWith(EV_new);
-                      EV->eraseFromParent();
-                      numRemoved++;
-                      changed = true;
-                      continue;
-                    }  else {
-                      EV->replaceAllUsesWith(V);
-                      EV->eraseFromParent();
-                      numRemoved++;
-                      changed = true;
-                      continue;
-                    }
-                  }
+                if (isa<ConstantAggregateZero>(C)) {
+                  EV->replaceAllUsesWith(Constant::getNullValue(EV->getType()));
+                  DEBUG(errs() << "MRV:");
+                  DEBUG(errs() << "ERASE:");
+                  DEBUG(EV->dump());
+                  EV->eraseFromParent();
+                  numErased++;
+                  changed = true;
                   continue;
                 }
-                if (InsertValueInst *IV = dyn_cast<InsertValueInst>(Agg)) {
-                  bool done = false;
-                  // We're extracting from an insertvalue instruction, compare the indices
-                  const unsigned *exti, *exte, *insi, *inse;
-                  for (exti = EV->idx_begin(), insi = IV->idx_begin(),
-                       exte = EV->idx_end(), inse = IV->idx_end();
-                       exti != exte && insi != inse;
-                       ++exti, ++insi) {
-                    if (*insi != *exti) {
-                      // The insert and extract both reference distinctly different elements.
-                      // This means the extract is not influenced by the insert, and we can
-                      // replace the aggregate operand of the extract with the aggregate
-                      // operand of the insert. i.e., replace
-                      // %I = insertvalue { i32, { i32 } } %A, { i32 } { i32 42 }, 1
-                      // %E = extractvalue { i32, { i32 } } %I, 0
-                      // with
-                      // %E = extractvalue { i32, { i32 } } %A, 0
-                      ExtractValueInst *EV_new = ExtractValueInst::Create(IV->getAggregateOperand(),
-                                                                          EV->idx_begin(), EV->idx_end(),"", EV);
-                      EV->replaceAllUsesWith(EV_new);
-                      EV->eraseFromParent();
-                      numRemoved++;
-                      done = true;
-                      changed = true;
-                      break;
-                    }
-                  }
-                  if(done)
-                    continue;
-                  if (exti == exte && insi == inse) {
-                    // Both iterators are at the end: Index lists are identical. Replace
-                    // %B = insertvalue { i32, { i32 } } %A, i32 42, 1, 0
-                    // %C = extractvalue { i32, { i32 } } %B, 1, 0
-                    // with "i32 42"
-                    EV->replaceAllUsesWith(IV->getInsertedValueOperand());
+                if (isa<ConstantArray>(C) || isa<ConstantStruct>(C)) {
+                  // Extract the element indexed by the first index out of the constant
+                  Value *V = C->getOperand(*EV->idx_begin());
+                  if (EV->getNumIndices() > 1) {
+                    // Extract the remaining indices out of the constant indexed by the
+                    // first index
+                    ExtractValueInst *EV_new = ExtractValueInst::Create(V, 
+                                                                        EV->idx_begin() + 1, 
+                                                                        EV->idx_end(), "", EV);
+                    EV->replaceAllUsesWith(EV_new);
+                    DEBUG(errs() << "MRV:");
+                    DEBUG(errs() << "ERASE:");
+                    DEBUG(EV->dump());
                     EV->eraseFromParent();
-                    numRemoved++;
+                    numErased++;
                     changed = true;
                     continue;
-
-                  }
-                  if (exti == exte) {
-                    // The extract list is a prefix of the insert list. i.e. replace
-                    // %I = insertvalue { i32, { i32 } } %A, i32 42, 1, 0
-                    // %E = extractvalue { i32, { i32 } } %I, 1
-                    // with
-                    // %X = extractvalue { i32, { i32 } } %A, 1
-                    // %E = insertvalue { i32 } %X, i32 42, 0
-                    // by switching the order of the insert and extract (though the
-                    // insertvalue should be left in, since it may have other uses).
-                    Value *NewEV = ExtractValueInst::Create(IV->getAggregateOperand(),
-                                                            EV->idx_begin(), EV->idx_end(), "", EV);
-                    Value *NewIV = InsertValueInst::Create(NewEV, IV->getInsertedValueOperand(),
-                                                           insi, inse, "", EV);
-                    EV->replaceAllUsesWith(NewIV);
+                  }  else {
+                    EV->replaceAllUsesWith(V);
+                    DEBUG(errs() << "MRV:");
+                    DEBUG(errs() << "ERASE:");
+                    DEBUG(EV->dump());
                     EV->eraseFromParent();
-                    numRemoved++;
+                    numErased++;
                     changed = true;
                     continue;
                   }
-                  if (insi == inse) {
-                    // The insert list is a prefix of the extract list
-                    // We can simply remove the common indices from the extract and make it
-                    // operate on the inserted value instead of the insertvalue result.
-                    // i.e., replace
+                }
+                continue;
+              }
+              if (InsertValueInst *IV = dyn_cast<InsertValueInst>(Agg)) {
+                bool done = false;
+                // We're extracting from an insertvalue instruction, compare the indices
+                const unsigned *exti, *exte, *insi, *inse;
+                for (exti = EV->idx_begin(), insi = IV->idx_begin(),
+                     exte = EV->idx_end(), inse = IV->idx_end();
+                     exti != exte && insi != inse;
+                     ++exti, ++insi) {
+                  if (*insi != *exti) {
+                    // The insert and extract both reference distinctly different elements.
+                    // This means the extract is not influenced by the insert, and we can
+                    // replace the aggregate operand of the extract with the aggregate
+                    // operand of the insert. i.e., replace
                     // %I = insertvalue { i32, { i32 } } %A, { i32 } { i32 42 }, 1
-                    // %E = extractvalue { i32, { i32 } } %I, 1, 0
+                    // %E = extractvalue { i32, { i32 } } %I, 0
                     // with
-                    // %E extractvalue { i32 } { i32 42 }, 0
-                    ExtractValueInst *EV_new = ExtractValueInst::Create(IV->getInsertedValueOperand(),
-                                                                        exti, exte,"", EV);
+                    // %E = extractvalue { i32, { i32 } } %A, 0
+                    ExtractValueInst *EV_new = ExtractValueInst::Create(IV->getAggregateOperand(),
+                                                                        EV->idx_begin(), EV->idx_end(),"", EV);
                     EV->replaceAllUsesWith(EV_new);
+                    DEBUG(errs() << "MRV:");
+                    DEBUG(errs() << "ERASE:");
+                    DEBUG(EV->dump());
                     EV->eraseFromParent();
-                    numRemoved++;
+                    numErased++;
+                    done = true;
                     changed = true;
-                    continue;
+                    break;
                   }
+                }
+                if(done)
+                  continue;
+                if (exti == exte && insi == inse) {
+                  // Both iterators are at the end: Index lists are identical. Replace
+                  // %B = insertvalue { i32, { i32 } } %A, i32 42, 1, 0
+                  // %C = extractvalue { i32, { i32 } } %B, 1, 0
+                  // with "i32 42"
+                  EV->replaceAllUsesWith(IV->getInsertedValueOperand());
+                  DEBUG(errs() << "MRV:");
+                  DEBUG(errs() << "ERASE:");
+                  DEBUG(EV->dump());
+                  EV->eraseFromParent();
+                  numErased++;
+                  changed = true;
+                  continue;
 
-
-
+                }
+                if (exti == exte) {
+                  // The extract list is a prefix of the insert list. i.e. replace
+                  // %I = insertvalue { i32, { i32 } } %A, i32 42, 1, 0
+                  // %E = extractvalue { i32, { i32 } } %I, 1
+                  // with
+                  // %X = extractvalue { i32, { i32 } } %A, 1
+                  // %E = insertvalue { i32 } %X, i32 42, 0
+                  // by switching the order of the insert and extract (though the
+                  // insertvalue should be left in, since it may have other uses).
+                  Value *NewEV = ExtractValueInst::Create(IV->getAggregateOperand(),
+                                                          EV->idx_begin(), EV->idx_end(), "", EV);
+                  Value *NewIV = InsertValueInst::Create(NewEV, IV->getInsertedValueOperand(),
+                                                         insi, inse, "", EV);
+                  EV->replaceAllUsesWith(NewIV);
+                  DEBUG(errs() << "MRV:");
+                  DEBUG(errs() << "ERASE:");
+                  DEBUG(EV->dump());
+                  EV->eraseFromParent();
+                  numErased++;
+                  changed = true;
+                  continue;
+                }
+                if (insi == inse) {
+                  // The insert list is a prefix of the extract list
+                  // We can simply remove the common indices from the extract and make it
+                  // operate on the inserted value instead of the insertvalue result.
+                  // i.e., replace
+                  // %I = insertvalue { i32, { i32 } } %A, { i32 } { i32 42 }, 1
+                  // %E = extractvalue { i32, { i32 } } %I, 1, 0
+                  // with
+                  // %E extractvalue { i32 } { i32 42 }, 0
+                  ExtractValueInst *EV_new = ExtractValueInst::Create(IV->getInsertedValueOperand(),
+                                                                      exti, exte,"", EV);
+                  EV->replaceAllUsesWith(EV_new);
+                  DEBUG(errs() << "MRV:");
+                  DEBUG(errs() << "ERASE:");
+                  DEBUG(EV->dump());
+                  EV->eraseFromParent();
+                  numErased++;
+                  changed = true;
+                  continue;
                 }
               }
             }
           }
         }
       } while(changed);
-      return true;
+      return (numErased > 0);
     }
   };
 }
 
+// Pass ID variable
 char SimplifyMRV::ID = 0;
+
+// Register the pass
 static RegisterPass<SimplifyMRV>
-X("simplify-mrv", "Simplify extract/insert value insts created due to mrvs");
+X("simplify-mrv", "Simplify extract/insert value insts");



From aggarwa4 at illinois.edu  Tue Apr  5 16:29:37 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 05 Apr 2011 21:29:37 -0000
Subject: [llvm-commits] [poolalloc] r128931 -
	/poolalloc/trunk/lib/AssistDS/FuncSpec.cpp
Message-ID: <20110405212937.E6E3D2A6C12D@llvm.org>

Author: aggarwa4
Date: Tue Apr  5 16:29:37 2011
New Revision: 128931

URL: http://llvm.org/viewvc/llvm-project?rev=128931&view=rev
Log:
Added comments.

Modified:
    poolalloc/trunk/lib/AssistDS/FuncSpec.cpp

Modified: poolalloc/trunk/lib/AssistDS/FuncSpec.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/FuncSpec.cpp?rev=128931&r1=128930&r2=128931&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/FuncSpec.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/FuncSpec.cpp Tue Apr  5 16:29:37 2011
@@ -27,6 +27,7 @@
 
 using namespace llvm;
 
+// Pass statistics
 STATISTIC(numCloned, "Number of Functions Cloned in FuncSpec");
 STATISTIC(numReplaced, "Number of Calls Replaced");
 
@@ -35,6 +36,23 @@
   public:
     static char ID;
     FuncSpec() : ModulePass(&ID) {}
+    //
+    // Method: runOnModule()
+    //
+    // Description:
+    //  Entry point for this LLVM pass. Search for call sites, that take functions as arguments
+    //  Clone those functions, and pass the clone.
+    //
+    // Inputs:
+    //  M - A reference to the LLVM module to transform
+    //
+    // Outputs:
+    //  M - The transformed LLVM module.
+    //
+    // Return value:
+    //  true  - The module was modified.
+    //  false - The module was not modified.
+    //
     bool runOnModule(Module& M) {
       std::map<CallInst*, std::vector<std::pair<unsigned, Constant*> > > cloneSites;
       std::map<std::pair<Function*, std::vector<std::pair<unsigned, Constant*> > >, Function* > toClone;
@@ -43,26 +61,36 @@
         if (!I->isDeclaration() && !I->mayBeOverridden()) {
           std::vector<unsigned> FPArgs;
           for (Function::arg_iterator ii = I->arg_begin(), ee = I->arg_end();
-               ii != ee; ++ii)
+               ii != ee; ++ii) {
+            // check if this function has a FunctionType(or a pointer to) argument 
             if (const PointerType* Ty = dyn_cast<PointerType>(ii->getType())) {
               if (isa<FunctionType>(Ty->getElementType())) {
+                // Store the index of such an argument
                 FPArgs.push_back(ii->getArgNo());
                 DEBUG(errs() << "Eligible: " << I->getNameStr() << "\n");
               }
             } else if (isa<FunctionType>(ii->getType())) {
+              // Store the index of such an argument
               FPArgs.push_back(ii->getArgNo());
               DEBUG(errs() << "Eligible: " << I->getNameStr() << "\n");
             } 
+          }
+          // Now find all call sites that it is called from
           for(Value::use_iterator ui = I->use_begin(), ue = I->use_end();
               ui != ue; ++ui) {
             if (CallInst* CI = dyn_cast<CallInst>(ui)) {
+              // Check that it is the called value (and not an argument)
               if(CI->getCalledValue()->stripPointerCasts() == I) {
                 std::vector<std::pair<unsigned, Constant*> > Consts;
                 for (unsigned x = 0; x < FPArgs.size(); ++x)
                   if (Constant* C = dyn_cast<Constant>(ui->getOperand(FPArgs.at(x) + 1))) {
+                    // If the argument passed, at any of the locations noted earlier
+                    // is a constant function, store the pair
                     Consts.push_back(std::make_pair(FPArgs.at(x), C));
                   }
                 if (!Consts.empty()) {
+                  // If at least one of the arguments is a constant function,
+                  // we must clone the function.
                   cloneSites[CI] = Consts;
                   toClone[std::make_pair(I, Consts)] = 0;
                 }
@@ -74,14 +102,16 @@
       numCloned += toClone.size();
 
       for (std::map<std::pair<Function*, std::vector<std::pair<unsigned, Constant*> > >, Function* >::iterator I = toClone.begin(), E = toClone.end(); I != E; ++I) {
+        // Clone all the functions we need cloned
         Function* DirectF = CloneFunction(I->first.first);
         DirectF->setName(I->first.first->getNameStr() + "_SPEC");
         DirectF->setLinkage(GlobalValue::InternalLinkage);
         I->first.first->getParent()->getFunctionList().push_back(DirectF);
         I->second = DirectF;
       }
-      
+
       for (std::map<CallInst*, std::vector<std::pair<unsigned, Constant*> > >::iterator ii = cloneSites.begin(), ee = cloneSites.end(); ii != ee; ++ii) {
+        // Transform the call sites, to call the clones
         ii->first->setOperand(0, toClone[std::make_pair(cast<Function>(ii->first->getOperand(0)), ii->second)]);
         ++numReplaced;
       }



From sabre at nondot.org  Tue Apr  5 16:37:08 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 05 Apr 2011 21:37:08 -0000
Subject: [llvm-commits] [llvm] r128933 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20110405213708.3DB9F2A6C12D@llvm.org>

Author: lattner
Date: Tue Apr  5 16:37:08 2011
New Revision: 128933

URL: http://llvm.org/viewvc/llvm-project?rev=128933&view=rev
Log:
only 7 more weeks to go.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128933&r1=128932&r2=128933&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Apr  5 16:37:08 2011
@@ -321,7 +321,8 @@
   for human written assembly.
 
 X86: Reimplemented all of MMX to introduce a new LLVM IR x86_mmx type.  Now
-  random types like &lt;2 x i32&gt; are not iseld to mmx without emms.
+  random types like &lt;2 x i32&gt; are not iseld to mmx without emms.  The
+  -disable-mmx flag is gone now.
 
 Some basic <a href="CodeGenerator.html#mc">internals documentation</a> for MC. 
   
@@ -330,18 +331,23 @@
   
 inline asm multiple alternative constraint support.
   
-LoopIdiom: memset/memcpy formation
+LoopIdiom: memset/memcpy formation.  Build with -ffreestanding or -fno-builtin
+  if your memcpy is being compiled into infinite recursion.
   
+
+TargetLibraryInfo
   
 X86 support for FS/GS relative loads and stores using address space 256/257 are
   reliable now.
   
 ARM: New code placement pass.
   
+unnamed_addr + PR8927
   
 PointerTracking has been removed from mainline, moved to ClamAV.
   
 EarlyCSE pass.
+LoopInstSimplify pass.
 
 - DIBuilder provides simpler interface for front ends like Clang to encode debug info in LLVM IR.
   - This interface hides implementation details (e.g. DIDerivedType, existence of compile unit etc..) that any front end should not know about.
@@ -367,7 +373,16 @@
 Scheduler now models operand latency and pipeline forwarding.
   
 error_code + libsystem + PathV2 changes
-
+  The system_error header from C++0x was added.
+  * Use if (error_code ec = function()) to check for error conditions
+  from functions which return it.
+  * error_code::message returns a human readable description of the error.
+  
+  PathV1 has been deprecated in favor of PathV2 (sorry I didn't finish
+  this before the release).
+  * No Path class, use a r-value convertible to a twine instead.
+  * Assumes all paths are UTF-8.
+  
 new macho-dump tool
 
 Major regalloc rewrite, not on by default for 2.9 and not advised to use it.
@@ -410,15 +425,43 @@
 
 Speedups to various mid-level passes:
   GVN is much faster on functions with deep dominator trees / lots of BBs.
-  DomTree and DominatorFrontier are much faster to compute.
+  DomTree and DominatorFrontier are much faster to compute, and preserved by
+    more passes (so they are computed less often)
   
   
 new 'hotpatch' attribute: LangRef.html#fnattrs
+
+APInt API changes, see PR5207.
+
+DSE is more aggressive with stores of different types: e.g. a large store 
+  following a small one to the same address.
+  
+New naming rules in coding standards: CodingStandards.html#ll_naming
+  
+LiveDebugVariables is a new pass that keeps track of debugging information for
+  user variables that are kept in registers in optimized builds.
+  
+We now optimize various idioms for overflow detection into check of the flag
+  register on various CPUs, e.g.:
+   unsigned long t = a+b;
+   if (t &lt; a) ...
+  into:
+  	addq	%rdi, %rbx
+  	jno	LBB0_2
+
+X86: Much better codegen for several cases using adc/sbb instead of cmovs for
+  conditional increment and other idioms.
+  
+MVT::Flag renamed to MVT::Glue
+  
+Removed the PartialSpecialization pass, it was unmaintained and buggy.
+  
 </pre></li>
 </ul>
   
-Still todo: [101129-110228]
+Still todo: [110117-110228]
 
+  
 </div>
 
 <!--=========================================================================-->



From stoklund at 2pi.dk  Tue Apr  5 16:40:37 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 21:40:37 -0000
Subject: [llvm-commits] [llvm] r128935 - in /llvm/trunk:
 lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/RegAllocGreedy.cpp
 test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
 test/CodeGen/X86/2010-05-26-DotDebugLoc.ll
 test/CodeGen/X86/2010-05-28-Crash.ll
 test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
 test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
 test/CodeGen/X86/dbg-merge-loc-entry.ll
 test/CodeGen/X86/dbg-value-inlined-parameter.ll
 test/CodeGen/X86/dbg-value-location.ll test/CodeGen/X86/dbg-value-range.ll
Message-ID: <20110405214037.AB7642A6C12D@llvm.org>

Author: stoklund
Date: Tue Apr  5 16:40:37 2011
New Revision: 128935

URL: http://llvm.org/viewvc/llvm-project?rev=128935&view=rev
Log:
Run LiveDebugVariables in RegAllocBasic and RegAllocGreedy.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
    llvm/trunk/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
    llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll
    llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll
    llvm/trunk/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
    llvm/trunk/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
    llvm/trunk/test/CodeGen/X86/dbg-merge-loc-entry.ll
    llvm/trunk/test/CodeGen/X86/dbg-value-inlined-parameter.ll
    llvm/trunk/test/CodeGen/X86/dbg-value-location.ll
    llvm/trunk/test/CodeGen/X86/dbg-value-range.ll

Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=128935&r1=128934&r2=128935&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Tue Apr  5 16:40:37 2011
@@ -13,6 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 #define DEBUG_TYPE "regalloc"
+#include "LiveDebugVariables.h"
 #include "LiveIntervalUnion.h"
 #include "LiveRangeEdit.h"
 #include "RegAllocBase.h"
@@ -137,6 +138,7 @@
 } // end anonymous namespace
 
 RABasic::RABasic(): MachineFunctionPass(ID) {
+  initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
   initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
   initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
   initializeStrongPHIEliminationPass(*PassRegistry::getPassRegistry());
@@ -155,6 +157,8 @@
   AU.addPreserved<AliasAnalysis>();
   AU.addRequired<LiveIntervals>();
   AU.addPreserved<SlotIndexes>();
+  AU.addRequired<LiveDebugVariables>();
+  AU.addPreserved<LiveDebugVariables>();
   if (StrongPHIElim)
     AU.addRequiredID(StrongPHIEliminationID);
   AU.addRequiredTransitive<RegisterCoalescer>();
@@ -543,6 +547,9 @@
   // Run rewriter
   VRM->rewrite(LIS->getSlotIndexes());
 
+  // Write out new DBG_VALUE instructions.
+  getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
+
   // The pass output is in VirtRegMap. Release all the transient data.
   releaseMemory();
 

Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=128935&r1=128934&r2=128935&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Apr  5 16:40:37 2011
@@ -15,6 +15,7 @@
 #define DEBUG_TYPE "regalloc"
 #include "AllocationOrder.h"
 #include "InterferenceCache.h"
+#include "LiveDebugVariables.h"
 #include "LiveRangeEdit.h"
 #include "RegAllocBase.h"
 #include "Spiller.h"
@@ -196,6 +197,7 @@
 }
 
 RAGreedy::RAGreedy(): MachineFunctionPass(ID), LRStage(RS_New) {
+  initializeLiveDebugVariablesPass(*PassRegistry::getPassRegistry());
   initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
   initializeLiveIntervalsPass(*PassRegistry::getPassRegistry());
   initializeSlotIndexesPass(*PassRegistry::getPassRegistry());
@@ -218,6 +220,8 @@
   AU.addRequired<LiveIntervals>();
   AU.addRequired<SlotIndexes>();
   AU.addPreserved<SlotIndexes>();
+  AU.addRequired<LiveDebugVariables>();
+  AU.addPreserved<LiveDebugVariables>();
   if (StrongPHIElim)
     AU.addRequiredID(StrongPHIEliminationID);
   AU.addRequiredTransitive<RegisterCoalescer>();
@@ -1183,6 +1187,9 @@
     VRM->rewrite(Indexes);
   }
 
+  // Write out new DBG_VALUE instructions.
+  getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
+
   // The pass output is in VirtRegMap. Release all the transient data.
   releaseMemory();
 

Modified: llvm/trunk/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll?rev=128935&r1=128934&r2=128935&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-05-25-DotDebugLoc.ll Tue Apr  5 16:40:37 2011
@@ -1,4 +1,5 @@
 ; RUN: llc -march=x86-64 -O2 < %s | FileCheck %s
+; RUN: llc -march=x86-64 -O2 -regalloc=basic < %s | FileCheck %s
 ; Test to check .debug_loc support. This test case emits many debug_loc entries.
 
 ; CHECK: Loc expr size

Modified: llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll?rev=128935&r1=128934&r2=128935&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-05-26-DotDebugLoc.ll Tue Apr  5 16:40:37 2011
@@ -1,4 +1,5 @@
 ; RUN: llc -O2 < %s | FileCheck %s
+; RUN: llc -O2 -regalloc=basic < %s | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin"
 

Modified: llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll?rev=128935&r1=128934&r2=128935&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-05-28-Crash.ll Tue Apr  5 16:40:37 2011
@@ -1,4 +1,5 @@
 ; RUN: llc  -mtriple=x86_64-apple-darwin < %s | FileCheck %s
+; RUN: llc  -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s
 ; Test to check separate label for inlined function argument.
 
 define i32 @foo(i32 %y) nounwind optsize ssp {

Modified: llvm/trunk/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll?rev=128935&r1=128934&r2=128935&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2010-06-01-DeadArg-DbgInfo.ll Tue Apr  5 16:40:37 2011
@@ -1,4 +1,5 @@
-; RUN: llc -O2 < %s | FileCheck %s 
+; RUN: llc -O2 < %s | FileCheck %s
+; RUN: llc -O2 -regalloc=basic < %s | FileCheck %s
 ; Test to check that unused argument 'this' is not undefined in debug info.
 
 target triple = "x86_64-apple-darwin10.2"

Modified: llvm/trunk/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll?rev=128935&r1=128934&r2=128935&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-01-24-DbgValue-Before-Use.ll Tue Apr  5 16:40:37 2011
@@ -1,4 +1,5 @@
 ; RUN: llc < %s | FileCheck %s
+; RUN: llc < %s -regalloc=basic | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.0.0"
 

Modified: llvm/trunk/test/CodeGen/X86/dbg-merge-loc-entry.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-merge-loc-entry.ll?rev=128935&r1=128934&r2=128935&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-merge-loc-entry.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dbg-merge-loc-entry.ll Tue Apr  5 16:40:37 2011
@@ -1,4 +1,5 @@
 ; RUN: llc < %s | FileCheck %s
+; RUN: llc < %s -regalloc=basic | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin8"
 

Modified: llvm/trunk/test/CodeGen/X86/dbg-value-inlined-parameter.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-inlined-parameter.ll?rev=128935&r1=128934&r2=128935&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-value-inlined-parameter.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dbg-value-inlined-parameter.ll Tue Apr  5 16:40:37 2011
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s
 
 ;CHECK: DW_TAG_inlined_subroutine
 ;CHECK-NEXT: DW_AT_abstract_origin

Modified: llvm/trunk/test/CodeGen/X86/dbg-value-location.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-location.ll?rev=128935&r1=128934&r2=128935&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-value-location.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dbg-value-location.ll Tue Apr  5 16:40:37 2011
@@ -1,4 +1,5 @@
 ; RUN: llc < %s | FileCheck %s
+; RUN: llc < %s -regalloc=basic | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
 target triple = "x86_64-apple-darwin10.0.0"
 ;Radar 8950491

Modified: llvm/trunk/test/CodeGen/X86/dbg-value-range.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-range.ll?rev=128935&r1=128934&r2=128935&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-value-range.ll (original)
+++ llvm/trunk/test/CodeGen/X86/dbg-value-range.ll Tue Apr  5 16:40:37 2011
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple=x86_64-apple-darwin < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-apple-darwin -regalloc=basic < %s | FileCheck %s
 
 %struct.a = type { i32 }
 



From stoklund at 2pi.dk  Tue Apr  5 16:40:41 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 21:40:41 -0000
Subject: [llvm-commits] [llvm] r128936 - in /llvm/trunk/test/CodeGen:
 ARM/2009-10-27-double-align.ll ARM/arm-returnaddr.ll
 Mips/2008-08-06-Alloca.ll PowerPC/2010-05-03-retaddr1.ll
 SPARC/2011-01-11-FrameAddr.ll
Message-ID: <20110405214041.AD50E2A6C12E@llvm.org>

Author: stoklund
Date: Tue Apr  5 16:40:41 2011
New Revision: 128936

URL: http://llvm.org/viewvc/llvm-project?rev=128936&view=rev
Log:
These tests no longer require linear scan because reserved register coalescing is now universal.

Modified:
    llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll
    llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll
    llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll
    llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
    llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll

Modified: llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll?rev=128936&r1=128935&r2=128936&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/2009-10-27-double-align.ll Tue Apr  5 16:40:41 2011
@@ -1,6 +1,5 @@
-; RUN: llc < %s  -mtriple=arm-linux-gnueabi -regalloc=linearscan | FileCheck %s
-
-; This test depends on linear scan's reserved register coalescing.
+; RUN: llc < %s  -mtriple=arm-linux-gnueabi | FileCheck %s
+; RUN: llc < %s  -mtriple=arm-linux-gnueabi -regalloc=basic | FileCheck %s
 
 @.str = private constant [1 x i8] zeroinitializer, align 1
 

Modified: llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll?rev=128936&r1=128935&r2=128936&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/arm-returnaddr.ll Tue Apr  5 16:40:41 2011
@@ -1,11 +1,10 @@
-; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=linearscan | FileCheck %s
-; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=linearscan | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin | FileCheck %s
+; RUN: llc < %s -mtriple=arm-apple-darwin -regalloc=basic | FileCheck %s
+; RUN: llc < %s -mtriple=thumbv6-apple-darwin -regalloc=basic | FileCheck %s
 ; rdar://8015977
 ; rdar://8020118
 
-; This test needs the reserved register r7 to be coalesced into the ldr.
-; So far, only linear scan can do that.
-
 define i8* @rt0(i32 %x) nounwind readnone {
 entry:
 ; CHECK: rt0:

Modified: llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll?rev=128936&r1=128935&r2=128936&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-08-06-Alloca.ll Tue Apr  5 16:40:41 2011
@@ -1,9 +1,5 @@
-; RUN: llc < %s -march=mips -regalloc=linearscan | grep {subu.*sp} | count 2
-
-; This test depends on a linearscan optimization, joining copies from reserved
-; registers.
-; After coalescing, copies from %SP remain.
-; They are handled by RALinScan::attemptTrivialCoalescing
+; RUN: llc < %s -march=mips | grep {subu.*sp} | count 2
+; RUN: llc < %s -march=mips -regalloc=basic | grep {subu.*sp} | count 2
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"

Modified: llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll?rev=128936&r1=128935&r2=128936&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/2010-05-03-retaddr1.ll Tue Apr  5 16:40:41 2011
@@ -1,4 +1,5 @@
-; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 -regalloc=linearscan | FileCheck %s
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 | FileCheck %s
+; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin -mcpu=g5 -regalloc=basic | FileCheck %s
 
 declare i8* @llvm.frameaddress(i32) nounwind readnone
 

Modified: llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll?rev=128936&r1=128935&r2=128936&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll (original)
+++ llvm/trunk/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll Tue Apr  5 16:40:41 2011
@@ -1,7 +1,7 @@
-;RUN: llc -march=sparc -regalloc=linearscan < %s | FileCheck %s -check-prefix=V8
-;RUN: llc -march=sparc -regalloc=linearscan -mattr=v9 < %s | FileCheck %s -check-prefix=V9
-
-; These tests depend on linear scan's trivial coalescer for reserved registers.
+;RUN: llc -march=sparc < %s | FileCheck %s -check-prefix=V8
+;RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
+;RUN: llc -march=sparc -regalloc=basic < %s | FileCheck %s -check-prefix=V8
+;RUN: llc -march=sparc -regalloc=basic -mattr=v9 < %s | FileCheck %s -check-prefix=V9
 
 define i8* @frameaddr() nounwind readnone {
 entry:



From sabre at nondot.org  Tue Apr  5 16:43:56 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 05 Apr 2011 21:43:56 -0000
Subject: [llvm-commits] [llvm] r128938 - in /llvm/trunk:
 docs/ReleaseNotes.html docs/WritingAnLLVMPass.html
 tools/opt/GraphPrinters.cpp
Message-ID: <20110405214356.A2B812A6C12D@llvm.org>

Author: lattner
Date: Tue Apr  5 16:43:56 2011
New Revision: 128938

URL: http://llvm.org/viewvc/llvm-project?rev=128938&view=rev
Log:
remove graphprinter support for domfrontier.

Modified:
    llvm/trunk/docs/ReleaseNotes.html
    llvm/trunk/docs/WritingAnLLVMPass.html
    llvm/trunk/tools/opt/GraphPrinters.cpp

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128938&r1=128937&r2=128938&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Apr  5 16:43:56 2011
@@ -427,6 +427,7 @@
   GVN is much faster on functions with deep dominator trees / lots of BBs.
   DomTree and DominatorFrontier are much faster to compute, and preserved by
     more passes (so they are computed less often)
+  SRoA is also much faster and doesn't use DominanceFrontier.
   
   
 new 'hotpatch' attribute: LangRef.html#fnattrs
@@ -456,6 +457,9 @@
   
 Removed the PartialSpecialization pass, it was unmaintained and buggy.
   
+SPARC: Many improvements, including using the Y registers for multiplications
+  and addition of a simple delay slot filler.
+  
 </pre></li>
 </ul>
   

Modified: llvm/trunk/docs/WritingAnLLVMPass.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/WritingAnLLVMPass.html?rev=128938&r1=128937&r2=128938&view=diff
==============================================================================
--- llvm/trunk/docs/WritingAnLLVMPass.html (original)
+++ llvm/trunk/docs/WritingAnLLVMPass.html Tue Apr  5 16:43:56 2011
@@ -1207,17 +1207,6 @@
 <div class="doc_text">
 
 <div class="doc_code"><pre>
-  <i>// This is an example implementation from an analysis, which does not modify
-  // the program at all, yet has a prerequisite.</i>
-  <b>void</b> <a href="http://llvm.org/doxygen/classllvm_1_1PostDominanceFrontier.html">PostDominanceFrontier</a>::getAnalysisUsage(AnalysisUsage &amp;AU) <b>const</b> {
-    AU.setPreservesAll();
-    AU.addRequired&lt;<a href="http://llvm.org/doxygen/classllvm_1_1PostDominatorTree.html">PostDominatorTree</a>&gt;();
-  }
-</pre></div>
-
-<p>and:</p>
-
-<div class="doc_code"><pre>
   <i>// This example modifies the program, but does not modify the CFG</i>
   <b>void</b> <a href="http://llvm.org/doxygen/structLICM.html">LICM</a>::getAnalysisUsage(AnalysisUsage &amp;AU) <b>const</b> {
     AU.setPreservesCFG();

Modified: llvm/trunk/tools/opt/GraphPrinters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/opt/GraphPrinters.cpp?rev=128938&r1=128937&r2=128938&view=diff
==============================================================================
--- llvm/trunk/tools/opt/GraphPrinters.cpp (original)
+++ llvm/trunk/tools/opt/GraphPrinters.cpp Tue Apr  5 16:43:56 2011
@@ -18,7 +18,7 @@
 #include "llvm/Pass.h"
 #include "llvm/Value.h"
 #include "llvm/Analysis/CallGraph.h"
-#include "llvm/Analysis/DominanceFrontier.h"
+#include "llvm/Analysis/Dominators.h"
 #include "llvm/Support/ToolOutputFile.h"
 using namespace llvm;
 
@@ -103,13 +103,11 @@
     virtual void getAnalysisUsage(AnalysisUsage &AU) const {
       AU.setPreservesAll();
       AU.addRequired<DominatorTree>();
-      AU.addRequired<DominanceFrontier>();
 
     }
 
     virtual bool runOnFunction(Function &F) {
       getAnalysis<DominatorTree>().dump();
-      getAnalysis<DominanceFrontier>().dump();
       return false;
     }
   };



From resistor at mac.com  Tue Apr  5 16:48:57 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 05 Apr 2011 21:48:57 -0000
Subject: [llvm-commits] [llvm] r128940 - in /llvm/trunk/lib/Target/ARM:
 ARMExpandPseudoInsts.cpp ARMISelLowering.cpp ARMInstrInfo.td
Message-ID: <20110405214858.1EC0F2A6C12D@llvm.org>

Author: resistor
Date: Tue Apr  5 16:48:57 2011
New Revision: 128940

URL: http://llvm.org/viewvc/llvm-project?rev=128940&view=rev
Log:
Fix bugs in the pseuo-ization of ADCS/SBCS pointed out by Jim, as well as doing the expansion earlier (using a custom inserter) to allow for the chance of predicating these instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=128940&r1=128939&r2=128940&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Tue Apr  5 16:48:57 2011
@@ -55,7 +55,6 @@
     void ExpandVLD(MachineBasicBlock::iterator &MBBI);
     void ExpandVST(MachineBasicBlock::iterator &MBBI);
     void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
-    void ExpandSBitOp(MachineBasicBlock::iterator &MBBI);
     void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
                     unsigned Opc, bool IsExt, unsigned NumRegs);
     void ExpandMOV32BitImm(MachineBasicBlock &MBB,
@@ -630,43 +629,6 @@
   MI.eraseFromParent();
 }
 
-void ARMExpandPseudo::ExpandSBitOp(MachineBasicBlock::iterator &MBBI) {
-  MachineInstr &MI = *MBBI;
-  MachineBasicBlock &MBB = *MI.getParent();
-  unsigned OldOpc = MI.getOpcode();
-  unsigned Opc = 0;
-  switch (OldOpc) {
-    case ARM::ADCSSrr:
-      Opc = ARM::ADCrr;
-      break;
-    case ARM::ADCSSri:
-      Opc = ARM::ADCri;
-      break;
-    case ARM::ADCSSrs:
-      Opc = ARM::ADCrs;
-      break;
-    case ARM::SBCSSrr:
-      Opc = ARM::SBCrr;
-      break;
-    case ARM::SBCSSri:
-      Opc = ARM::SBCri;
-      break;
-    case ARM::SBCSSrs:
-      Opc = ARM::SBCrs;
-      break;
-    default:
-      llvm_unreachable("Unknown opcode?");
-  }
-
-  MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
-  MIB.addOperand(MachineOperand::CreateImm(0)); // Predicate
-  MIB.addOperand(MachineOperand::CreateImm(0)); // S bit
-  for (unsigned i = 0; i < MI.getNumOperands(); ++i)
-    MIB.addOperand(MI.getOperand(i));
-  TransferImpOps(MI, MIB, MIB);
-  MI.eraseFromParent();
-}
-
 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator &MBBI) {
   MachineInstr &MI = *MBBI;
@@ -979,15 +941,6 @@
       ExpandMOV32BitImm(MBB, MBBI);
       return true;
 
-    case ARM::ADCSSri:
-    case ARM::ADCSSrr:
-    case ARM::ADCSSrs:
-    case ARM::SBCSSri:
-    case ARM::SBCSSrr:
-    case ARM::SBCSSrs:
-      ExpandSBitOp(MBBI);
-      return true;
-
     case ARM::VMOVQQ: {
       unsigned DstReg = MI.getOperand(0).getReg();
       bool DstIsDead = MI.getOperand(0).isDead();

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=128940&r1=128939&r2=128940&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Apr  5 16:48:57 2011
@@ -2390,7 +2390,7 @@
       assert(VA.getValVT() != MVT::i64 && "i64 should already be lowered");
 
       int index = ArgLocs[i].getValNo();
-      
+
       // Some Ins[] entries become multiple ArgLoc[] entries.
       // Process them only once.
       if (index != lastInsIndex)
@@ -2966,7 +2966,7 @@
     AllOnes = DAG.getNode(ARMISD::VMOVIMM, dl, MVT::v8i8, AllOnes);
     SDValue MaskNot = DAG.getNode(ISD::XOR, dl, OpVT, Mask,
                                   DAG.getNode(ISD::BITCAST, dl, OpVT, AllOnes));
-                                              
+
     SDValue Res = DAG.getNode(ISD::OR, dl, OpVT,
                               DAG.getNode(ISD::AND, dl, OpVT, Tmp1, Mask),
                               DAG.getNode(ISD::AND, dl, OpVT, Tmp0, MaskNot));
@@ -4147,7 +4147,7 @@
                        DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
                                    &VTBLMask[0], 8));
 
-  return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2, 
+  return DAG.getNode(ARMISD::VTBL2, DL, MVT::v8i8, V1, V2,
                      DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v8i8,
                                  &VTBLMask[0], 8));
 }
@@ -4520,7 +4520,7 @@
                                DAG.getNode(ISD::BITCAST, DL, Op1VT, N01), Op1));
 }
 
-static SDValue 
+static SDValue
 LowerSDIV_v4i8(SDValue X, SDValue Y, DebugLoc dl, SelectionDAG &DAG) {
   // Convert to float
   // float4 xf = vcvt_f32_s32(vmovl_s16(a.lo));
@@ -4531,7 +4531,7 @@
   Y = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, Y);
   // Get reciprocal estimate.
   // float4 recip = vrecpeq_f32(yf);
-  Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 
+  Y = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
                    DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), Y);
   // Because char has a smaller range than uchar, we can actually get away
   // without any newton steps.  This requires that we use a weird bias
@@ -4549,7 +4549,7 @@
   return X;
 }
 
-static SDValue 
+static SDValue
 LowerSDIV_v4i16(SDValue N0, SDValue N1, DebugLoc dl, SelectionDAG &DAG) {
   SDValue N2;
   // Convert to float.
@@ -4559,13 +4559,13 @@
   N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v4i32, N1);
   N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0);
   N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1);
-  
+
   // Use reciprocal estimate and one refinement step.
   // float4 recip = vrecpeq_f32(yf);
   // recip *= vrecpsq_f32(yf, recip);
-  N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 
+  N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
                    DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
-  N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 
+  N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
                    DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
                    N1, N2);
   N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
@@ -4595,15 +4595,15 @@
   SDValue N0 = Op.getOperand(0);
   SDValue N1 = Op.getOperand(1);
   SDValue N2, N3;
-  
+
   if (VT == MVT::v8i8) {
     N0 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N0);
     N1 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::v8i16, N1);
-    
+
     N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
                      DAG.getIntPtrConstant(4));
     N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
-                     DAG.getIntPtrConstant(4)); 
+                     DAG.getIntPtrConstant(4));
     N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
                      DAG.getIntPtrConstant(0));
     N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
@@ -4614,7 +4614,7 @@
 
     N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
     N0 = LowerCONCAT_VECTORS(N0, DAG);
-    
+
     N0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::v8i8, N0);
     return N0;
   }
@@ -4630,32 +4630,32 @@
   SDValue N0 = Op.getOperand(0);
   SDValue N1 = Op.getOperand(1);
   SDValue N2, N3;
-  
+
   if (VT == MVT::v8i8) {
     N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0);
     N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1);
-    
+
     N2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
                      DAG.getIntPtrConstant(4));
     N3 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
-                     DAG.getIntPtrConstant(4)); 
+                     DAG.getIntPtrConstant(4));
     N0 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N0,
                      DAG.getIntPtrConstant(0));
     N1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, MVT::v4i16, N1,
                      DAG.getIntPtrConstant(0));
-    
+
     N0 = LowerSDIV_v4i16(N0, N1, dl, DAG); // v4i16
     N2 = LowerSDIV_v4i16(N2, N3, dl, DAG); // v4i16
-    
+
     N0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v8i16, N0, N2);
     N0 = LowerCONCAT_VECTORS(N0, DAG);
-    
-    N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8, 
+
+    N0 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v8i8,
                      DAG.getConstant(Intrinsic::arm_neon_vqmovnsu, MVT::i32),
                      N0);
     return N0;
   }
-  
+
   // v4i16 sdiv ... Convert to float.
   // float4 yf = vcvt_f32_s32(vmovl_u16(y));
   // float4 xf = vcvt_f32_s32(vmovl_u16(x));
@@ -4668,13 +4668,13 @@
   // float4 recip = vrecpeq_f32(yf);
   // recip *= vrecpsq_f32(yf, recip);
   // recip *= vrecpsq_f32(yf, recip);
-  N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 
+  N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
                    DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1);
-  N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 
+  N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
                    DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
                    N1, N2);
   N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
-  N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, 
+  N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32,
                    DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32),
                    N1, N2);
   N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2);
@@ -5024,6 +5024,48 @@
   case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
   case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
 
+  case ARM::ADCSSri:
+  case ARM::ADCSSrr:
+  case ARM::ADCSSrs:
+  case ARM::SBCSSri:
+  case ARM::SBCSSrr:
+  case ARM::SBCSSrs: {
+    unsigned OldOpc = MI->getOpcode();
+    unsigned Opc = 0;
+    switch (OldOpc) {
+      case ARM::ADCSSrr:
+        Opc = ARM::ADCrr;
+        break;
+      case ARM::ADCSSri:
+        Opc = ARM::ADCri;
+        break;
+      case ARM::ADCSSrs:
+        Opc = ARM::ADCrs;
+        break;
+      case ARM::SBCSSrr:
+        Opc = ARM::SBCrr;
+        break;
+      case ARM::SBCSSri:
+        Opc = ARM::SBCri;
+        break;
+      case ARM::SBCSSrs:
+        Opc = ARM::SBCrs;
+        break;
+      default:
+        llvm_unreachable("Unknown opcode?");
+    }
+
+    MachineInstrBuilder MIB =
+      BuildMI(*BB, MI, MI->getDebugLoc(), TII->get(Opc));
+    for (unsigned i = 0; i < MI->getNumOperands(); ++i)
+      MIB.addOperand(MI->getOperand(i));
+    AddDefaultPred(MIB);
+    MIB.addReg(ARM::CPSR, RegState::Define); // S bit
+    MI->eraseFromParent();
+    return BB;
+  }
+
+
   case ARM::tMOVCCr_pseudo: {
     // To "insert" a SELECT_CC instruction, we actually have to insert the
     // diamond control-flow pattern.  The incoming instruction knows the
@@ -5326,7 +5368,7 @@
 
 static SDValue PerformANDCombine(SDNode *N,
                                 TargetLowering::DAGCombinerInfo &DCI) {
-  
+
   // Attempt to use immediate-form VBIC
   BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
   DebugLoc dl = N->getDebugLoc();
@@ -5851,7 +5893,7 @@
     EVT VecTy;
     if (isLoad)
       VecTy = N->getValueType(0);
-    else 
+    else
       VecTy = N->getOperand(AddrOpIdx+1).getValueType();
     unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
     if (isLaneOp)
@@ -5901,7 +5943,7 @@
     DCI.CombineTo(User, SDValue(UpdN.getNode(), NumResultVecs));
 
     break;
-  } 
+  }
   return SDValue();
 }
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128940&r1=128939&r2=128940&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Apr  5 16:48:57 2011
@@ -936,8 +936,7 @@
 }
 // Carry setting variants
 let isCodeGenOnly = 1, Defs = [CPSR] in {
-multiclass AI1_adde_sube_s_irs<bits<4> opcod, string opc, PatFrag opnode,
-                             bit Commutable = 0> {
+multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
   def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
                 Size4Bytes, IIC_iALUi,
                [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
@@ -2197,10 +2196,12 @@
                           BinOpFrag<(sube_dead_carry node:$LHS, node:$RHS)>>;
 
 // ADC and SUBC with 's' bit set.
-defm ADCS : AI1_adde_sube_s_irs<0b0101, "adcs",
-                          BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
-defm SBCS : AI1_adde_sube_s_irs<0b0110, "sbcs",
-                          BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
+let usesCustomInserter = 1 in {
+defm ADCS : AI1_adde_sube_s_irs<
+              BinOpFrag<(adde_live_carry node:$LHS, node:$RHS)>, 1>;
+defm SBCS : AI1_adde_sube_s_irs<
+              BinOpFrag<(sube_live_carry node:$LHS, node:$RHS) >>;
+}
 
 def RSBri : AsI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
                  IIC_iALUi, "rsb", "\t$Rd, $Rn, $imm",



From johnny.chen at apple.com  Tue Apr  5 16:49:44 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 21:49:44 -0000
Subject: [llvm-commits] [llvm] r128941 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
 test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt
Message-ID: <20110405214944.A61F72A6C12D@llvm.org>

Author: johnny
Date: Tue Apr  5 16:49:44 2011
New Revision: 128941

URL: http://llvm.org/viewvc/llvm-project?rev=128941&view=rev
Log:
ARM disassembler was erroneously accepting an invalid LSL instruction.
For register-controlled shifts, we should check that the encoding constraint
Inst{7} = 0 and Inst{4} = 1 is satisfied.

rdar://problem/9237693

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128941&r1=128940&r2=128941&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Apr  5 16:49:44 2011
@@ -1068,6 +1068,10 @@
   MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                      decodeRm(insn))));
   if (Rs) {
+    // If Inst{7} != 0, we should reject this insn as an invalid encoding.
+    if (slice(insn, 7, 7))
+      return false;
+
     // Register-controlled shifts: [Rm, Rs, shift].
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        decodeRs(insn))));

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt?rev=128941&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-MOVs-LSL-arm.txt Tue Apr  5 16:49:44 2011
@@ -0,0 +1,9 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=196 Name=MOVs Format=ARM_FORMAT_DPSOREGFRM(5)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 0: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 0: 0: 0| 0: 1: 0: 0| 0: 0: 1: 0| 1: 0: 0: 1| 0: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+# A8.6.89 LSL (register): Inst{7-4} = 0b0001
+0x93 0x42 0xa0 0xd1



From geek4civic at gmail.com  Tue Apr  5 16:55:14 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Tue, 05 Apr 2011 21:55:14 -0000
Subject: [llvm-commits] [llvm] r128942 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20110405215514.C1F802A6C12D@llvm.org>

Author: chapuni
Date: Tue Apr  5 16:55:14 2011
New Revision: 128942

URL: http://llvm.org/viewvc/llvm-project?rev=128942&view=rev
Log:
docs/ReleaseNotes.html: Please use proper *Heading* elements instead of classified div.

It would be better to browse without stylesheet. (eg. on ViewVC)

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128942&r1=128941&r2=128942&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Apr  5 16:55:14 2011
@@ -9,7 +9,7 @@
 </head>
 <body>
 
-<div class="doc_title">LLVM 2.9 Release Notes</div>
+<h1 class="doc_title">LLVM 2.9 Release Notes</h1>
 
 <img align=right src="http://llvm.org/img/DragonSmall.png"
     width="136" height="136" alt="LLVM Dragon Logo">
@@ -35,9 +35,9 @@
 Release Notes</a>.</h1>
 
 <!-- *********************************************************************** -->
-<div class="doc_section">
+<h1>
   <a name="intro">Introduction</a>
-</div>
+</h1>
 <!-- *********************************************************************** -->
 
 <div class="doc_text">
@@ -75,9 +75,9 @@
  -->
  
 <!-- *********************************************************************** -->
-<div class="doc_section">
+<h1>
   <a name="subproj">Sub-project Status Update</a>
-</div>
+</h1>
 <!-- *********************************************************************** -->
 
 <div class="doc_text">
@@ -93,9 +93,9 @@
 
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="clang">Clang: C/C++/Objective-C Frontend Toolkit</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -126,9 +126,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="dragonegg">DragonEgg: GCC front-ends, LLVM back-end</a>
-</div>
+</h2>
 
 <div class="doc_text">
 <p>
@@ -158,9 +158,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="compiler-rt">compiler-rt: Compiler Runtime Library</a>
-</div>
+</h2>
 
 <div class="doc_text">
 <p>
@@ -186,9 +186,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="lldb">LLDB: Low Level Debugger</a>
-</div>
+</h2>
 
 <div class="doc_text">
 <p>
@@ -212,9 +212,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="libc++">libc++: C++ Standard Library</a>
-</div>
+</h2>
 
 <div class="doc_text">
 <p>
@@ -239,9 +239,9 @@
 
 <!--=========================================================================-->
 <!--
-<div class="doc_subsection">
+<h2>
 <a name="klee">KLEE: A Symbolic Execution Virtual Machine</a>
-</div>
+</h2>
 
 <div class="doc_text">
 <p>
@@ -257,9 +257,9 @@
 
 
 <!-- *********************************************************************** -->
-<div class="doc_section">
+<h1>
   <a name="externalproj">External Open Source Projects Using LLVM 2.9</a>
-</div>
+</h1>
 <!-- *********************************************************************** -->
 
 <div class="doc_text">
@@ -273,9 +273,9 @@
 
 
 <!-- *********************************************************************** -->
-<div class="doc_section">
+<h1>
   <a name="whatsnew">What's New in LLVM 2.9?</a>
-</div>
+</h1>
 <!-- *********************************************************************** -->
 
 <div class="doc_text">
@@ -288,9 +288,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="majorfeatures">Major New Features</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -469,9 +469,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="coreimprovements">LLVM IR and Core Improvements</a>
-</div>
+</h2>
 
 <div class="doc_text">
 <p>LLVM IR has several new features for better support of new targets and that
@@ -483,9 +483,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="optimizer">Optimizer Improvements</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -508,9 +508,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="mc">MC Level Improvements</a>
-</div>
+</h2>
 
 <div class="doc_text">
 <p>
@@ -538,9 +538,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="codegen">Target Independent Code Generator Improvements</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -555,9 +555,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="x86">X86-32 and X86-64 Target Improvements</a>
-</div>
+</h2>
 
 <div class="doc_text">
 <p>New features and major changes in the X86 target include:
@@ -570,9 +570,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="ARM">ARM Target Improvements</a>
-</div>
+</h2>
 
 <div class="doc_text">
 <p>New features of the ARM target include:
@@ -584,9 +584,9 @@
 
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="changes">Major Changes and Removed Features</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -607,9 +607,9 @@
 </div>
 
 <!--=========================================================================-->
-<div class="doc_subsection">
+<h2>
 <a name="devtree_changes">Development Infrastructure Changes</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -623,9 +623,9 @@
 </div>
 
 <!-- *********************************************************************** -->
-<div class="doc_section">
+<h1>
   <a name="knownproblems">Known Problems</a>
-</div>
+</h1>
 <!-- *********************************************************************** -->
 
 <div class="doc_text">
@@ -638,9 +638,9 @@
 </div>
 
 <!-- ======================================================================= -->
-<div class="doc_subsection">
+<h2>
   <a name="experimental">Experimental features included with this release</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -662,9 +662,9 @@
 </div>
 
 <!-- ======================================================================= -->
-<div class="doc_subsection">
+<h2>
   <a name="x86-be">Known problems with the X86 back-end</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -695,9 +695,9 @@
 </div>
 
 <!-- ======================================================================= -->
-<div class="doc_subsection">
+<h2>
   <a name="ppc-be">Known problems with the PowerPC back-end</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -709,9 +709,9 @@
 </div>
 
 <!-- ======================================================================= -->
-<div class="doc_subsection">
+<h2>
   <a name="arm-be">Known problems with the ARM back-end</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -726,9 +726,9 @@
 </div>
 
 <!-- ======================================================================= -->
-<div class="doc_subsection">
+<h2>
   <a name="sparc-be">Known problems with the SPARC back-end</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -740,9 +740,9 @@
 </div>
 
 <!-- ======================================================================= -->
-<div class="doc_subsection">
+<h2>
   <a name="mips-be">Known problems with the MIPS back-end</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -753,9 +753,9 @@
 </div>
 
 <!-- ======================================================================= -->
-<div class="doc_subsection">
+<h2>
   <a name="alpha-be">Known problems with the Alpha back-end</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -768,9 +768,9 @@
 </div>
 
 <!-- ======================================================================= -->
-<div class="doc_subsection">
+<h2>
   <a name="c-be">Known problems with the C back-end</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -791,9 +791,9 @@
 
 
 <!-- ======================================================================= -->
-<div class="doc_subsection">
+<h2>
   <a name="llvm-gcc">Known problems with the llvm-gcc front-end</a>
-</div>
+</h2>
 
 <div class="doc_text">
 
@@ -817,9 +817,9 @@
 </div>
 
 <!-- *********************************************************************** -->
-<div class="doc_section">
+<h1>
   <a name="additionalinfo">Additional Information</a>
-</div>
+</h1>
 <!-- *********************************************************************** -->
 
 <div class="doc_text">



From geek4civic at gmail.com  Tue Apr  5 17:00:25 2011
From: geek4civic at gmail.com (NAKAMURA Takumi)
Date: Wed, 6 Apr 2011 07:00:25 +0900
Subject: [llvm-commits] [PATCH] docs/ReleaseNotes.html: Please use
 proper *Heading* elements instead of classified div.
In-Reply-To: <4B9D9A41-EE99-4B4E-B054-51FAE437AA45@apple.com>
References: <BANLkTik-eNUpXP_ahaNOVa3X349tieZKwg@mail.gmail.com>
	<4B9D9A41-EE99-4B4E-B054-51FAE437AA45@apple.com>
Message-ID: <BANLkTimY1NhwyxHjY1TdY9bKB4PGXpe2=A@mail.gmail.com>

Applied in r128942!

From sabre at nondot.org  Tue Apr  5 16:57:17 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 05 Apr 2011 21:57:17 -0000
Subject: [llvm-commits] [llvm] r128943 - in /llvm/trunk:
 include/llvm/Analysis/PostDominators.h include/llvm/Analysis/RegionInfo.h
 include/llvm/InitializePasses.h include/llvm/LinkAllPasses.h
 lib/Analysis/Analysis.cpp lib/Analysis/PostDominators.cpp
 test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll
 test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll
 test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll
Message-ID: <20110405215717.E217A2A6C12D@llvm.org>

Author: lattner
Date: Tue Apr  5 16:57:17 2011
New Revision: 128943

URL: http://llvm.org/viewvc/llvm-project?rev=128943&view=rev
Log:
remove postdom frontiers, because it is dead.  Forward dom frontiers are
still used by RegionInfo :(

Removed:
    llvm/trunk/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll
    llvm/trunk/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll
    llvm/trunk/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll
Modified:
    llvm/trunk/include/llvm/Analysis/PostDominators.h
    llvm/trunk/include/llvm/Analysis/RegionInfo.h
    llvm/trunk/include/llvm/InitializePasses.h
    llvm/trunk/include/llvm/LinkAllPasses.h
    llvm/trunk/lib/Analysis/Analysis.cpp
    llvm/trunk/lib/Analysis/PostDominators.cpp

Modified: llvm/trunk/include/llvm/Analysis/PostDominators.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/PostDominators.h?rev=128943&r1=128942&r2=128943&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/PostDominators.h (original)
+++ llvm/trunk/include/llvm/Analysis/PostDominators.h Tue Apr  5 16:57:17 2011
@@ -14,7 +14,7 @@
 #ifndef LLVM_ANALYSIS_POST_DOMINATORS_H
 #define LLVM_ANALYSIS_POST_DOMINATORS_H
 
-#include "llvm/Analysis/DominanceFrontier.h"
+#include "llvm/Analysis/Dominators.h"
 
 namespace llvm {
 
@@ -101,37 +101,6 @@
   }
 };
 
-/// PostDominanceFrontier Class - Concrete subclass of DominanceFrontier that is
-/// used to compute the a post-dominance frontier.
-///
-struct PostDominanceFrontier : public DominanceFrontierBase {
-  static char ID;
-  PostDominanceFrontier()
-    : DominanceFrontierBase(ID, true) {
-      initializePostDominanceFrontierPass(*PassRegistry::getPassRegistry());
-    }
-
-  virtual bool runOnFunction(Function &) {
-    Frontiers.clear();
-    PostDominatorTree &DT = getAnalysis<PostDominatorTree>();
-    Roots = DT.getRoots();
-    if (const DomTreeNode *Root = DT.getRootNode())
-      calculate(DT, Root);
-    return false;
-  }
-
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const {
-    AU.setPreservesAll();
-    AU.addRequired<PostDominatorTree>();
-  }
-
-private:
-  const DomSetType &calculate(const PostDominatorTree &DT,
-                              const DomTreeNode *Node);
-};
-
-FunctionPass* createPostDomFrontier();
-
 } // End llvm namespace
 
 #endif

Modified: llvm/trunk/include/llvm/Analysis/RegionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/RegionInfo.h?rev=128943&r1=128942&r2=128943&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/RegionInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/RegionInfo.h Tue Apr  5 16:57:17 2011
@@ -28,9 +28,10 @@
 #define LLVM_ANALYSIS_REGION_INFO_H
 
 #include "llvm/ADT/PointerIntPair.h"
-#include "llvm/Analysis/Dominators.h"
+#include "llvm/Analysis/DominanceFrontier.h"
 #include "llvm/Analysis/PostDominators.h"
 #include "llvm/Support/Allocator.h"
+#include <map>
 
 namespace llvm {
 

Modified: llvm/trunk/include/llvm/InitializePasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=128943&r1=128942&r2=128943&view=diff
==============================================================================
--- llvm/trunk/include/llvm/InitializePasses.h (original)
+++ llvm/trunk/include/llvm/InitializePasses.h Tue Apr  5 16:57:17 2011
@@ -168,7 +168,6 @@
 void initializePostDomOnlyViewerPass(PassRegistry&);
 void initializePostDomPrinterPass(PassRegistry&);
 void initializePostDomViewerPass(PassRegistry&);
-void initializePostDominanceFrontierPass(PassRegistry&);
 void initializePostDominatorTreePass(PassRegistry&);
 void initializePreAllocSplittingPass(PassRegistry&);
 void initializePreVerifierPass(PassRegistry&);

Modified: llvm/trunk/include/llvm/LinkAllPasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=128943&r1=128942&r2=128943&view=diff
==============================================================================
--- llvm/trunk/include/llvm/LinkAllPasses.h (original)
+++ llvm/trunk/include/llvm/LinkAllPasses.h Tue Apr  5 16:57:17 2011
@@ -134,7 +134,6 @@
       (void) llvm::createMemCpyOptPass();
       (void) llvm::createLoopDeletionPass();
       (void) llvm::createPostDomTree();
-      (void) llvm::createPostDomFrontier();
       (void) llvm::createInstructionNamerPass();
       (void) llvm::createFunctionAttrsPass();
       (void) llvm::createMergeFunctionsPass();

Modified: llvm/trunk/lib/Analysis/Analysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Analysis.cpp?rev=128943&r1=128942&r2=128943&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/Analysis.cpp (original)
+++ llvm/trunk/lib/Analysis/Analysis.cpp Tue Apr  5 16:57:17 2011
@@ -49,7 +49,6 @@
   initializeMemoryDependenceAnalysisPass(Registry);
   initializeModuleDebugInfoPrinterPass(Registry);
   initializePostDominatorTreePass(Registry);
-  initializePostDominanceFrontierPass(Registry);
   initializeProfileEstimatorPassPass(Registry);
   initializeNoProfileInfoPass(Registry);
   initializeNoPathProfileInfoPass(Registry);

Modified: llvm/trunk/lib/Analysis/PostDominators.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/PostDominators.cpp?rev=128943&r1=128942&r2=128943&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/PostDominators.cpp (original)
+++ llvm/trunk/lib/Analysis/PostDominators.cpp Tue Apr  5 16:57:17 2011
@@ -28,7 +28,6 @@
 //===----------------------------------------------------------------------===//
 
 char PostDominatorTree::ID = 0;
-char PostDominanceFrontier::ID = 0;
 INITIALIZE_PASS(PostDominatorTree, "postdomtree",
                 "Post-Dominator Tree Construction", true, true)
 
@@ -50,53 +49,3 @@
   return new PostDominatorTree();
 }
 
-//===----------------------------------------------------------------------===//
-//  PostDominanceFrontier Implementation
-//===----------------------------------------------------------------------===//
-
-INITIALIZE_PASS_BEGIN(PostDominanceFrontier, "postdomfrontier",
-                "Post-Dominance Frontier Construction", true, true)
-INITIALIZE_PASS_DEPENDENCY(PostDominatorTree)
-INITIALIZE_PASS_END(PostDominanceFrontier, "postdomfrontier",
-                "Post-Dominance Frontier Construction", true, true)
-
-const DominanceFrontier::DomSetType &
-PostDominanceFrontier::calculate(const PostDominatorTree &DT,
-                                 const DomTreeNode *Node) {
-  // Loop over CFG successors to calculate DFlocal[Node]
-  BasicBlock *BB = Node->getBlock();
-  DomSetType &S = Frontiers[BB];       // The new set to fill in...
-  if (getRoots().empty()) return S;
-
-  if (BB)
-    for (pred_iterator SI = pred_begin(BB), SE = pred_end(BB);
-         SI != SE; ++SI) {
-      BasicBlock *P = *SI;
-      // Does Node immediately dominate this predecessor?
-      DomTreeNode *SINode = DT[P];
-      if (SINode && SINode->getIDom() != Node)
-        S.insert(P);
-    }
-
-  // At this point, S is DFlocal.  Now we union in DFup's of our children...
-  // Loop through and visit the nodes that Node immediately dominates (Node's
-  // children in the IDomTree)
-  //
-  for (DomTreeNode::const_iterator
-         NI = Node->begin(), NE = Node->end(); NI != NE; ++NI) {
-    DomTreeNode *IDominee = *NI;
-    const DomSetType &ChildDF = calculate(DT, IDominee);
-
-    DomSetType::const_iterator CDFI = ChildDF.begin(), CDFE = ChildDF.end();
-    for (; CDFI != CDFE; ++CDFI) {
-      if (!DT.properlyDominates(Node, DT[*CDFI]))
-        S.insert(*CDFI);
-    }
-  }
-
-  return S;
-}
-
-FunctionPass* llvm::createPostDomFrontier() {
-  return new PostDominanceFrontier();
-}

Removed: llvm/trunk/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll?rev=128942&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll (original)
+++ llvm/trunk/test/Analysis/PostDominators/2006-09-26-PostDominanceFrontier.ll (removed)
@@ -1,97 +0,0 @@
-; RUN: opt < %s -analyze -postdomfrontier \
-; RUN:   -disable-verify
-; ModuleID = '2006-09-26-PostDominanceFrontier.bc'
-target datalayout = "e-p:64:64"
-target triple = "alphaev67-unknown-linux-gnu"
-	%struct.FILE = type { i32, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, i8*, %struct._IO_marker*, %struct.FILE*, i32, i32, i64, i16, i8, [1 x i8], i8*, i64, i8*, i8*, i32, [44 x i8] }
-	%struct._IO_marker = type { %struct._IO_marker*, %struct.FILE*, i32 }
- at TOP = external global i64*		; <i64**> [#uses=1]
- at BOT = external global i64*		; <i64**> [#uses=1]
- at str = external global [2 x i8]		; <[2 x i8]*> [#uses=0]
-
-declare void @fopen()
-
-define void @main(i8** %argv) {
-entry:
-	%netSelect.i507 = alloca i64, align 8		; <i64*> [#uses=0]
-	%topStart.i = alloca i64, align 8		; <i64*> [#uses=0]
-	%topEnd.i = alloca i64, align 8		; <i64*> [#uses=0]
-	%botStart.i = alloca i64, align 8		; <i64*> [#uses=0]
-	%botEnd.i = alloca i64, align 8		; <i64*> [#uses=0]
-	%c1.i154 = alloca i32, align 4		; <i32*> [#uses=0]
-	%b1.i155 = alloca i32, align 4		; <i32*> [#uses=0]
-	%t1.i156 = alloca i32, align 4		; <i32*> [#uses=0]
-	%c1.i = alloca i32, align 4		; <i32*> [#uses=0]
-	%b1.i = alloca i32, align 4		; <i32*> [#uses=0]
-	%t1.i = alloca i32, align 4		; <i32*> [#uses=0]
-	%netSelect.i5 = alloca i64, align 8		; <i64*> [#uses=0]
-	%netSelect.i = alloca i64, align 8		; <i64*> [#uses=0]
-	%tmp2.i = getelementptr i8** %argv, i32 1		; <i8**> [#uses=1]
-	%tmp3.i4 = load i8** %tmp2.i		; <i8*> [#uses=0]
-	call void @fopen( )
-	br i1 false, label %DimensionChannel.exit, label %bb.backedge.i
-
-bb.backedge.i:		; preds = %entry
-	ret void
-
-DimensionChannel.exit:		; preds = %entry
-	%tmp13.i137 = malloc i64, i32 0		; <i64*> [#uses=1]
-	%tmp610.i = malloc i64, i32 0		; <i64*> [#uses=1]
-	br label %cond_true.i143
-
-cond_true.i143:		; preds = %cond_true.i143, %DimensionChannel.exit
-	%tmp9.i140 = getelementptr i64* %tmp13.i137, i64 0		; <i64*> [#uses=0]
-	%tmp12.i = getelementptr i64* %tmp610.i, i64 0		; <i64*> [#uses=0]
-	br i1 false, label %bb18.i144, label %cond_true.i143
-
-bb18.i144:		; preds = %cond_true.i143
-	call void @fopen( )
-	%tmp76.i105 = malloc i64, i32 0		; <i64*> [#uses=3]
-	%tmp674.i = malloc i64, i32 0		; <i64*> [#uses=2]
-	%tmp1072.i = malloc i64, i32 0		; <i64*> [#uses=2]
-	%tmp1470.i = malloc i64, i32 0		; <i64*> [#uses=1]
-	br label %cond_true.i114
-
-cond_true.i114:		; preds = %cond_true.i114, %bb18.i144
-	%tmp17.i108 = getelementptr i64* %tmp76.i105, i64 0		; <i64*> [#uses=0]
-	%tmp20.i = getelementptr i64* %tmp674.i, i64 0		; <i64*> [#uses=0]
-	%tmp23.i111 = getelementptr i64* %tmp1470.i, i64 0		; <i64*> [#uses=0]
-	br i1 false, label %cond_true40.i, label %cond_true.i114
-
-cond_true40.i:		; preds = %cond_true40.i, %cond_true.i114
-	%tmp33.i115 = getelementptr i64* %tmp1072.i, i64 0		; <i64*> [#uses=0]
-	br i1 false, label %bb142.i, label %cond_true40.i
-
-cond_next54.i:		; preds = %cond_true76.i
-	%tmp57.i = getelementptr i64* %tmp55.i, i64 0		; <i64*> [#uses=0]
-	br i1 false, label %bb64.i, label %bb69.i
-
-bb64.i:		; preds = %cond_true76.i, %cond_next54.i
-	%tmp67.i117 = getelementptr i64* %tmp76.i105, i64 0		; <i64*> [#uses=0]
-	br i1 false, label %bb114.i, label %cond_true111.i
-
-bb69.i:		; preds = %cond_next54.i
-	br i1 false, label %bb79.i, label %cond_true76.i
-
-cond_true76.i:		; preds = %bb142.i, %bb69.i
-	%tmp48.i = getelementptr i64* %tmp46.i, i64 0		; <i64*> [#uses=0]
-	br i1 false, label %bb64.i, label %cond_next54.i
-
-bb79.i:		; preds = %bb69.i
-	br i1 false, label %bb114.i, label %cond_true111.i
-
-cond_true111.i:		; preds = %bb79.i, %bb64.i
-	%tmp84.i127 = getelementptr i64* %tmp46.i, i64 0		; <i64*> [#uses=0]
-	ret void
-
-bb114.i:		; preds = %bb142.i, %bb79.i, %bb64.i
-	%tmp117.i = getelementptr i64* %tmp76.i105, i64 0		; <i64*> [#uses=0]
-	%tmp132.i131 = getelementptr i64* %tmp674.i, i64 0		; <i64*> [#uses=0]
-	%tmp122.i = getelementptr i64* %tmp1072.i, i64 0		; <i64*> [#uses=0]
-	ret void
-
-bb142.i:		; preds = %cond_true40.i
-	%tmp46.i = load i64** @BOT		; <i64*> [#uses=2]
-	%tmp55.i = load i64** @TOP		; <i64*> [#uses=1]
-	br i1 false, label %bb114.i, label %cond_true76.i
-}

Removed: llvm/trunk/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll?rev=128942&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll (original)
+++ llvm/trunk/test/Analysis/PostDominators/2007-04-17-PostDominanceFrontier.ll (removed)
@@ -1,692 +0,0 @@
-; RUN: opt < %s -postdomfrontier -disable-output
-
-define void @SManager() {
-entry:
-	br label %bb.outer
-
-bb.outer:		; preds = %bb193, %entry
-	br label %bb.outer156
-
-bb.loopexit:		; preds = %bb442
-	br label %bb.outer156
-
-bb.outer156:		; preds = %bb.loopexit, %bb.outer
-	br label %bb
-
-bb:		; preds = %bb.backedge, %bb.outer156
-	br i1 false, label %cond_true, label %bb.cond_next_crit_edge
-
-bb.cond_next_crit_edge:		; preds = %bb
-	br label %cond_next
-
-cond_true:		; preds = %bb
-	br label %cond_next
-
-cond_next:		; preds = %cond_true, %bb.cond_next_crit_edge
-	br i1 false, label %cond_next.bb.backedge_crit_edge, label %cond_next107
-
-cond_next.bb.backedge_crit_edge:		; preds = %cond_next
-	br label %bb.backedge
-
-bb.backedge:		; preds = %cond_true112.bb.backedge_crit_edge, %cond_next.bb.backedge_crit_edge
-	br label %bb
-
-cond_next107:		; preds = %cond_next
-	br i1 false, label %cond_true112, label %cond_next197
-
-cond_true112:		; preds = %cond_next107
-	br i1 false, label %cond_true118, label %cond_true112.bb.backedge_crit_edge
-
-cond_true112.bb.backedge_crit_edge:		; preds = %cond_true112
-	br label %bb.backedge
-
-cond_true118:		; preds = %cond_true112
-	br i1 false, label %bb123.preheader, label %cond_true118.bb148_crit_edge
-
-cond_true118.bb148_crit_edge:		; preds = %cond_true118
-	br label %bb148
-
-bb123.preheader:		; preds = %cond_true118
-	br label %bb123
-
-bb123:		; preds = %bb142.bb123_crit_edge, %bb123.preheader
-	br i1 false, label %bb123.bb142_crit_edge, label %cond_next.i57
-
-bb123.bb142_crit_edge:		; preds = %bb123
-	br label %bb142
-
-cond_next.i57:		; preds = %bb123
-	br i1 false, label %cond_true135, label %cond_next.i57.bb142_crit_edge
-
-cond_next.i57.bb142_crit_edge:		; preds = %cond_next.i57
-	br label %bb142
-
-cond_true135:		; preds = %cond_next.i57
-	br label %bb142
-
-bb142:		; preds = %cond_true135, %cond_next.i57.bb142_crit_edge, %bb123.bb142_crit_edge
-	br i1 false, label %bb148.loopexit, label %bb142.bb123_crit_edge
-
-bb142.bb123_crit_edge:		; preds = %bb142
-	br label %bb123
-
-bb148.loopexit:		; preds = %bb142
-	br label %bb148
-
-bb148:		; preds = %bb148.loopexit, %cond_true118.bb148_crit_edge
-	br i1 false, label %bb151.preheader, label %bb148.bb177_crit_edge
-
-bb148.bb177_crit_edge:		; preds = %bb148
-	br label %bb177
-
-bb151.preheader:		; preds = %bb148
-	br label %bb151
-
-bb151:		; preds = %bb171.bb151_crit_edge, %bb151.preheader
-	br i1 false, label %bb151.bb171_crit_edge, label %cond_next.i49
-
-bb151.bb171_crit_edge:		; preds = %bb151
-	br label %bb171
-
-cond_next.i49:		; preds = %bb151
-	br i1 false, label %cond_true164, label %cond_next.i49.bb171_crit_edge
-
-cond_next.i49.bb171_crit_edge:		; preds = %cond_next.i49
-	br label %bb171
-
-cond_true164:		; preds = %cond_next.i49
-	br label %bb171
-
-bb171:		; preds = %cond_true164, %cond_next.i49.bb171_crit_edge, %bb151.bb171_crit_edge
-	br i1 false, label %bb177.loopexit, label %bb171.bb151_crit_edge
-
-bb171.bb151_crit_edge:		; preds = %bb171
-	br label %bb151
-
-bb177.loopexit:		; preds = %bb171
-	br label %bb177
-
-bb177:		; preds = %bb177.loopexit, %bb148.bb177_crit_edge
-	br i1 false, label %bb180.preheader, label %bb177.bb193_crit_edge
-
-bb177.bb193_crit_edge:		; preds = %bb177
-	br label %bb193
-
-bb180.preheader:		; preds = %bb177
-	br label %bb180
-
-bb180:		; preds = %bb180.bb180_crit_edge, %bb180.preheader
-	br i1 false, label %bb193.loopexit, label %bb180.bb180_crit_edge
-
-bb180.bb180_crit_edge:		; preds = %bb180
-	br label %bb180
-
-bb193.loopexit:		; preds = %bb180
-	br label %bb193
-
-bb193:		; preds = %bb193.loopexit, %bb177.bb193_crit_edge
-	br label %bb.outer
-
-cond_next197:		; preds = %cond_next107
-	br i1 false, label %cond_next210, label %cond_true205
-
-cond_true205:		; preds = %cond_next197
-	br i1 false, label %cond_true205.bb213_crit_edge, label %cond_true205.bb299_crit_edge
-
-cond_true205.bb299_crit_edge:		; preds = %cond_true205
-	br label %bb299
-
-cond_true205.bb213_crit_edge:		; preds = %cond_true205
-	br label %bb213
-
-cond_next210:		; preds = %cond_next197
-	br label %bb293
-
-bb213:		; preds = %bb293.bb213_crit_edge, %cond_true205.bb213_crit_edge
-	br i1 false, label %bb213.cond_next290_crit_edge, label %cond_true248
-
-bb213.cond_next290_crit_edge:		; preds = %bb213
-	br label %cond_next290
-
-cond_true248:		; preds = %bb213
-	br i1 false, label %cond_true248.cond_next290_crit_edge, label %cond_true255
-
-cond_true248.cond_next290_crit_edge:		; preds = %cond_true248
-	br label %cond_next290
-
-cond_true255:		; preds = %cond_true248
-	br i1 false, label %cond_true266, label %cond_true255.cond_next271_crit_edge
-
-cond_true255.cond_next271_crit_edge:		; preds = %cond_true255
-	br label %cond_next271
-
-cond_true266:		; preds = %cond_true255
-	br label %cond_next271
-
-cond_next271:		; preds = %cond_true266, %cond_true255.cond_next271_crit_edge
-	br label %cond_next290
-
-cond_next290:		; preds = %cond_next271, %cond_true248.cond_next290_crit_edge, %bb213.cond_next290_crit_edge
-	br label %bb293
-
-bb293:		; preds = %cond_next290, %cond_next210
-	br i1 false, label %bb293.bb213_crit_edge, label %bb293.bb299_crit_edge
-
-bb293.bb299_crit_edge:		; preds = %bb293
-	br label %bb299
-
-bb293.bb213_crit_edge:		; preds = %bb293
-	br label %bb213
-
-bb299:		; preds = %bb293.bb299_crit_edge, %cond_true205.bb299_crit_edge
-	br i1 false, label %bb302.preheader, label %bb299.bb390_crit_edge
-
-bb299.bb390_crit_edge:		; preds = %bb299
-	br label %bb390
-
-bb302.preheader:		; preds = %bb299
-	br label %bb302
-
-bb302:		; preds = %bb384.bb302_crit_edge, %bb302.preheader
-	br i1 false, label %bb302.bb384_crit_edge, label %cond_true339
-
-bb302.bb384_crit_edge:		; preds = %bb302
-	br label %bb384
-
-cond_true339:		; preds = %bb302
-	br i1 false, label %cond_true339.bb384_crit_edge, label %cond_true346
-
-cond_true339.bb384_crit_edge:		; preds = %cond_true339
-	br label %bb384
-
-cond_true346:		; preds = %cond_true339
-	br i1 false, label %cond_true357, label %cond_true346.cond_next361_crit_edge
-
-cond_true346.cond_next361_crit_edge:		; preds = %cond_true346
-	br label %cond_next361
-
-cond_true357:		; preds = %cond_true346
-	br label %cond_next361
-
-cond_next361:		; preds = %cond_true357, %cond_true346.cond_next361_crit_edge
-	br label %bb384
-
-bb384:		; preds = %cond_next361, %cond_true339.bb384_crit_edge, %bb302.bb384_crit_edge
-	br i1 false, label %bb390.loopexit, label %bb384.bb302_crit_edge
-
-bb384.bb302_crit_edge:		; preds = %bb384
-	br label %bb302
-
-bb390.loopexit:		; preds = %bb384
-	br label %bb390
-
-bb390:		; preds = %bb390.loopexit, %bb299.bb390_crit_edge
-	br i1 false, label %bb391.preheader, label %bb390.bb442.preheader_crit_edge
-
-bb390.bb442.preheader_crit_edge:		; preds = %bb390
-	br label %bb442.preheader
-
-bb391.preheader:		; preds = %bb390
-	br label %bb391
-
-bb391:		; preds = %bb413.bb391_crit_edge, %bb391.preheader
-	br i1 false, label %bb391.bb413_crit_edge, label %cond_next404
-
-bb391.bb413_crit_edge:		; preds = %bb391
-	br label %bb413
-
-cond_next404:		; preds = %bb391
-	br i1 false, label %cond_next404.HWrite.exit_crit_edge, label %cond_next.i13
-
-cond_next404.HWrite.exit_crit_edge:		; preds = %cond_next404
-	br label %HWrite.exit
-
-cond_next.i13:		; preds = %cond_next404
-	br i1 false, label %cond_next.i13.cond_next13.i_crit_edge, label %cond_true12.i
-
-cond_next.i13.cond_next13.i_crit_edge:		; preds = %cond_next.i13
-	br label %cond_next13.i
-
-cond_true12.i:		; preds = %cond_next.i13
-	br label %cond_next13.i
-
-cond_next13.i:		; preds = %cond_true12.i, %cond_next.i13.cond_next13.i_crit_edge
-	br i1 false, label %cond_next13.i.bb.i22_crit_edge, label %cond_next43.i
-
-cond_next13.i.bb.i22_crit_edge:		; preds = %cond_next13.i
-	br label %bb.i22
-
-cond_next43.i:		; preds = %cond_next13.i
-	br i1 false, label %cond_next43.i.bb.i22_crit_edge, label %bb60.i
-
-cond_next43.i.bb.i22_crit_edge:		; preds = %cond_next43.i
-	br label %bb.i22
-
-bb.i22:		; preds = %cond_next43.i.bb.i22_crit_edge, %cond_next13.i.bb.i22_crit_edge
-	br label %bb413
-
-bb60.i:		; preds = %cond_next43.i
-	br i1 false, label %bb60.i.HWrite.exit_crit_edge, label %cond_true81.i
-
-bb60.i.HWrite.exit_crit_edge:		; preds = %bb60.i
-	br label %HWrite.exit
-
-cond_true81.i:		; preds = %bb60.i
-	br label %bb413
-
-HWrite.exit:		; preds = %bb60.i.HWrite.exit_crit_edge, %cond_next404.HWrite.exit_crit_edge
-	br label %bb413
-
-bb413:		; preds = %HWrite.exit, %cond_true81.i, %bb.i22, %bb391.bb413_crit_edge
-	br i1 false, label %bb442.preheader.loopexit, label %bb413.bb391_crit_edge
-
-bb413.bb391_crit_edge:		; preds = %bb413
-	br label %bb391
-
-bb442.preheader.loopexit:		; preds = %bb413
-	br label %bb442.preheader
-
-bb442.preheader:		; preds = %bb442.preheader.loopexit, %bb390.bb442.preheader_crit_edge
-	br label %bb442.outer
-
-bb420:		; preds = %bb442
-	br i1 false, label %bb439.loopexit, label %cond_next433
-
-cond_next433:		; preds = %bb420
-	br i1 false, label %cond_next433.HRead.exit.loopexit_crit_edge, label %cond_next.i
-
-cond_next433.HRead.exit.loopexit_crit_edge:		; preds = %cond_next433
-	br label %HRead.exit.loopexit
-
-cond_next.i:		; preds = %cond_next433
-	br i1 false, label %cond_true9.i, label %cond_false223.i
-
-cond_true9.i:		; preds = %cond_next.i
-	switch i32 0, label %cond_false.i [
-		 i32 1, label %cond_true9.i.cond_true15.i_crit_edge
-		 i32 5, label %cond_true9.i.cond_true15.i_crit_edge9
-	]
-
-cond_true9.i.cond_true15.i_crit_edge9:		; preds = %cond_true9.i
-	br label %cond_true15.i
-
-cond_true9.i.cond_true15.i_crit_edge:		; preds = %cond_true9.i
-	br label %cond_true15.i
-
-cond_true15.i:		; preds = %cond_true9.i.cond_true15.i_crit_edge, %cond_true9.i.cond_true15.i_crit_edge9
-	br i1 false, label %cond_true15.i.cond_true44.i_crit_edge, label %cond_true15.i.cond_false49.i_crit_edge
-
-cond_true15.i.cond_false49.i_crit_edge:		; preds = %cond_true15.i
-	br label %cond_false49.i
-
-cond_true15.i.cond_true44.i_crit_edge:		; preds = %cond_true15.i
-	br label %cond_true44.i
-
-cond_false.i:		; preds = %cond_true9.i
-	br i1 false, label %cond_false.i.cond_next39.i_crit_edge, label %cond_true30.i
-
-cond_false.i.cond_next39.i_crit_edge:		; preds = %cond_false.i
-	br label %cond_next39.i
-
-cond_true30.i:		; preds = %cond_false.i
-	br label %cond_next39.i
-
-cond_next39.i:		; preds = %cond_true30.i, %cond_false.i.cond_next39.i_crit_edge
-	br i1 false, label %cond_next39.i.cond_true44.i_crit_edge, label %cond_next39.i.cond_false49.i_crit_edge
-
-cond_next39.i.cond_false49.i_crit_edge:		; preds = %cond_next39.i
-	br label %cond_false49.i
-
-cond_next39.i.cond_true44.i_crit_edge:		; preds = %cond_next39.i
-	br label %cond_true44.i
-
-cond_true44.i:		; preds = %cond_next39.i.cond_true44.i_crit_edge, %cond_true15.i.cond_true44.i_crit_edge
-	br i1 false, label %cond_true44.i.cond_next70.i_crit_edge, label %cond_true44.i.cond_true61.i_crit_edge
-
-cond_true44.i.cond_true61.i_crit_edge:		; preds = %cond_true44.i
-	br label %cond_true61.i
-
-cond_true44.i.cond_next70.i_crit_edge:		; preds = %cond_true44.i
-	br label %cond_next70.i
-
-cond_false49.i:		; preds = %cond_next39.i.cond_false49.i_crit_edge, %cond_true15.i.cond_false49.i_crit_edge
-	br i1 false, label %cond_false49.i.cond_next70.i_crit_edge, label %cond_false49.i.cond_true61.i_crit_edge
-
-cond_false49.i.cond_true61.i_crit_edge:		; preds = %cond_false49.i
-	br label %cond_true61.i
-
-cond_false49.i.cond_next70.i_crit_edge:		; preds = %cond_false49.i
-	br label %cond_next70.i
-
-cond_true61.i:		; preds = %cond_false49.i.cond_true61.i_crit_edge, %cond_true44.i.cond_true61.i_crit_edge
-	br i1 false, label %cond_true61.i.cond_next70.i_crit_edge, label %cond_true67.i
-
-cond_true61.i.cond_next70.i_crit_edge:		; preds = %cond_true61.i
-	br label %cond_next70.i
-
-cond_true67.i:		; preds = %cond_true61.i
-	br label %cond_next70.i
-
-cond_next70.i:		; preds = %cond_true67.i, %cond_true61.i.cond_next70.i_crit_edge, %cond_false49.i.cond_next70.i_crit_edge, %cond_true44.i.cond_next70.i_crit_edge
-	br i1 false, label %cond_true77.i, label %cond_next81.i
-
-cond_true77.i:		; preds = %cond_next70.i
-	br label %bb442.outer.backedge
-
-cond_next81.i:		; preds = %cond_next70.i
-	br i1 false, label %cond_true87.i, label %cond_false94.i
-
-cond_true87.i:		; preds = %cond_next81.i
-	br i1 false, label %cond_true87.i.cond_true130.i_crit_edge, label %cond_true87.i.cond_next135.i_crit_edge
-
-cond_true87.i.cond_next135.i_crit_edge:		; preds = %cond_true87.i
-	br label %cond_next135.i
-
-cond_true87.i.cond_true130.i_crit_edge:		; preds = %cond_true87.i
-	br label %cond_true130.i
-
-cond_false94.i:		; preds = %cond_next81.i
-	switch i32 0, label %cond_false94.i.cond_next125.i_crit_edge [
-		 i32 1, label %cond_false94.i.cond_true100.i_crit_edge
-		 i32 5, label %cond_false94.i.cond_true100.i_crit_edge10
-	]
-
-cond_false94.i.cond_true100.i_crit_edge10:		; preds = %cond_false94.i
-	br label %cond_true100.i
-
-cond_false94.i.cond_true100.i_crit_edge:		; preds = %cond_false94.i
-	br label %cond_true100.i
-
-cond_false94.i.cond_next125.i_crit_edge:		; preds = %cond_false94.i
-	br label %cond_next125.i
-
-cond_true100.i:		; preds = %cond_false94.i.cond_true100.i_crit_edge, %cond_false94.i.cond_true100.i_crit_edge10
-	br i1 false, label %cond_true107.i, label %cond_true100.i.cond_next109.i_crit_edge
-
-cond_true100.i.cond_next109.i_crit_edge:		; preds = %cond_true100.i
-	br label %cond_next109.i
-
-cond_true107.i:		; preds = %cond_true100.i
-	br label %cond_next109.i
-
-cond_next109.i:		; preds = %cond_true107.i, %cond_true100.i.cond_next109.i_crit_edge
-	br i1 false, label %cond_next109.i.cond_next125.i_crit_edge, label %cond_true116.i
-
-cond_next109.i.cond_next125.i_crit_edge:		; preds = %cond_next109.i
-	br label %cond_next125.i
-
-cond_true116.i:		; preds = %cond_next109.i
-	br label %cond_next125.i
-
-cond_next125.i:		; preds = %cond_true116.i, %cond_next109.i.cond_next125.i_crit_edge, %cond_false94.i.cond_next125.i_crit_edge
-	br i1 false, label %cond_next125.i.cond_true130.i_crit_edge, label %cond_next125.i.cond_next135.i_crit_edge
-
-cond_next125.i.cond_next135.i_crit_edge:		; preds = %cond_next125.i
-	br label %cond_next135.i
-
-cond_next125.i.cond_true130.i_crit_edge:		; preds = %cond_next125.i
-	br label %cond_true130.i
-
-cond_true130.i:		; preds = %cond_next125.i.cond_true130.i_crit_edge, %cond_true87.i.cond_true130.i_crit_edge
-	br label %cond_next135.i
-
-cond_next135.i:		; preds = %cond_true130.i, %cond_next125.i.cond_next135.i_crit_edge, %cond_true87.i.cond_next135.i_crit_edge
-	br i1 false, label %cond_true142.i, label %cond_next135.i.cond_next149.i_crit_edge
-
-cond_next135.i.cond_next149.i_crit_edge:		; preds = %cond_next135.i
-	br label %cond_next149.i
-
-cond_true142.i:		; preds = %cond_next135.i
-	br label %cond_next149.i
-
-cond_next149.i:		; preds = %cond_true142.i, %cond_next135.i.cond_next149.i_crit_edge
-	br i1 false, label %cond_true156.i, label %cond_next149.i.cond_next163.i_crit_edge
-
-cond_next149.i.cond_next163.i_crit_edge:		; preds = %cond_next149.i
-	br label %cond_next163.i
-
-cond_true156.i:		; preds = %cond_next149.i
-	br label %cond_next163.i
-
-cond_next163.i:		; preds = %cond_true156.i, %cond_next149.i.cond_next163.i_crit_edge
-	br i1 false, label %cond_true182.i, label %cond_next163.i.cond_next380.i_crit_edge
-
-cond_next163.i.cond_next380.i_crit_edge:		; preds = %cond_next163.i
-	br label %cond_next380.i
-
-cond_true182.i:		; preds = %cond_next163.i
-	br i1 false, label %cond_true182.i.cond_next380.i_crit_edge, label %cond_true196.i
-
-cond_true182.i.cond_next380.i_crit_edge:		; preds = %cond_true182.i
-	br label %cond_next380.i
-
-cond_true196.i:		; preds = %cond_true182.i
-	br i1 false, label %cond_true210.i, label %cond_true196.i.cond_next380.i_crit_edge
-
-cond_true196.i.cond_next380.i_crit_edge:		; preds = %cond_true196.i
-	br label %cond_next380.i
-
-cond_true210.i:		; preds = %cond_true196.i
-	br i1 false, label %cond_true216.i, label %cond_true210.i.cond_next380.i_crit_edge
-
-cond_true210.i.cond_next380.i_crit_edge:		; preds = %cond_true210.i
-	br label %cond_next380.i
-
-cond_true216.i:		; preds = %cond_true210.i
-	br label %cond_next380.i
-
-cond_false223.i:		; preds = %cond_next.i
-	br i1 false, label %cond_true229.i, label %cond_false355.i
-
-cond_true229.i:		; preds = %cond_false223.i
-	br i1 false, label %cond_true229.i.HRead.exit.loopexit_crit_edge, label %cond_next243.i
-
-cond_true229.i.HRead.exit.loopexit_crit_edge:		; preds = %cond_true229.i
-	br label %HRead.exit.loopexit
-
-cond_next243.i:		; preds = %cond_true229.i
-	br i1 false, label %cond_true248.i, label %cond_false255.i
-
-cond_true248.i:		; preds = %cond_next243.i
-	br label %cond_next260.i
-
-cond_false255.i:		; preds = %cond_next243.i
-	br label %cond_next260.i
-
-cond_next260.i:		; preds = %cond_false255.i, %cond_true248.i
-	br i1 false, label %cond_true267.i, label %cond_next273.i
-
-cond_true267.i:		; preds = %cond_next260.i
-	br label %bb442.backedge
-
-bb442.backedge:		; preds = %bb.i, %cond_true267.i
-	br label %bb442
-
-cond_next273.i:		; preds = %cond_next260.i
-	br i1 false, label %cond_true281.i, label %cond_next273.i.cond_next288.i_crit_edge
-
-cond_next273.i.cond_next288.i_crit_edge:		; preds = %cond_next273.i
-	br label %cond_next288.i
-
-cond_true281.i:		; preds = %cond_next273.i
-	br label %cond_next288.i
-
-cond_next288.i:		; preds = %cond_true281.i, %cond_next273.i.cond_next288.i_crit_edge
-	br i1 false, label %cond_true295.i, label %cond_next288.i.cond_next302.i_crit_edge
-
-cond_next288.i.cond_next302.i_crit_edge:		; preds = %cond_next288.i
-	br label %cond_next302.i
-
-cond_true295.i:		; preds = %cond_next288.i
-	br label %cond_next302.i
-
-cond_next302.i:		; preds = %cond_true295.i, %cond_next288.i.cond_next302.i_crit_edge
-	br i1 false, label %cond_next302.i.cond_next380.i_crit_edge, label %cond_true328.i
-
-cond_next302.i.cond_next380.i_crit_edge:		; preds = %cond_next302.i
-	br label %cond_next380.i
-
-cond_true328.i:		; preds = %cond_next302.i
-	br i1 false, label %cond_true343.i, label %cond_true328.i.cond_next380.i_crit_edge
-
-cond_true328.i.cond_next380.i_crit_edge:		; preds = %cond_true328.i
-	br label %cond_next380.i
-
-cond_true343.i:		; preds = %cond_true328.i
-	br i1 false, label %cond_true349.i, label %cond_true343.i.cond_next380.i_crit_edge
-
-cond_true343.i.cond_next380.i_crit_edge:		; preds = %cond_true343.i
-	br label %cond_next380.i
-
-cond_true349.i:		; preds = %cond_true343.i
-	br label %cond_next380.i
-
-cond_false355.i:		; preds = %cond_false223.i
-	br i1 false, label %cond_false355.i.bb.i_crit_edge, label %cond_next363.i
-
-cond_false355.i.bb.i_crit_edge:		; preds = %cond_false355.i
-	br label %bb.i
-
-cond_next363.i:		; preds = %cond_false355.i
-	br i1 false, label %bb377.i, label %cond_next363.i.bb.i_crit_edge
-
-cond_next363.i.bb.i_crit_edge:		; preds = %cond_next363.i
-	br label %bb.i
-
-bb.i:		; preds = %cond_next363.i.bb.i_crit_edge, %cond_false355.i.bb.i_crit_edge
-	br label %bb442.backedge
-
-bb377.i:		; preds = %cond_next363.i
-	br label %cond_next380.i
-
-cond_next380.i:		; preds = %bb377.i, %cond_true349.i, %cond_true343.i.cond_next380.i_crit_edge, %cond_true328.i.cond_next380.i_crit_edge, %cond_next302.i.cond_next380.i_crit_edge, %cond_true216.i, %cond_true210.i.cond_next380.i_crit_edge, %cond_true196.i.cond_next380.i_crit_edge, %cond_true182.i.cond_next380.i_crit_edge, %cond_next163.i.cond_next380.i_crit_edge
-	br i1 false, label %cond_next380.i.HRead.exit_crit_edge, label %cond_true391.i
-
-cond_next380.i.HRead.exit_crit_edge:		; preds = %cond_next380.i
-	br label %HRead.exit
-
-cond_true391.i:		; preds = %cond_next380.i
-	br label %bb442.outer.backedge
-
-bb442.outer.backedge:		; preds = %bb439, %cond_true391.i, %cond_true77.i
-	br label %bb442.outer
-
-HRead.exit.loopexit:		; preds = %cond_true229.i.HRead.exit.loopexit_crit_edge, %cond_next433.HRead.exit.loopexit_crit_edge
-	br label %HRead.exit
-
-HRead.exit:		; preds = %HRead.exit.loopexit, %cond_next380.i.HRead.exit_crit_edge
-	br label %bb439
-
-bb439.loopexit:		; preds = %bb420
-	br label %bb439
-
-bb439:		; preds = %bb439.loopexit, %HRead.exit
-	br label %bb442.outer.backedge
-
-bb442.outer:		; preds = %bb442.outer.backedge, %bb442.preheader
-	br label %bb442
-
-bb442:		; preds = %bb442.outer, %bb442.backedge
-	br i1 false, label %bb420, label %bb.loopexit
-}
-
-define void @Invalidate() {
-entry:
-	br i1 false, label %cond_false, label %cond_true
-
-cond_true:		; preds = %entry
-	br i1 false, label %cond_true40, label %cond_true.cond_next_crit_edge
-
-cond_true.cond_next_crit_edge:		; preds = %cond_true
-	br label %cond_next
-
-cond_true40:		; preds = %cond_true
-	br label %cond_next
-
-cond_next:		; preds = %cond_true40, %cond_true.cond_next_crit_edge
-	br i1 false, label %cond_true68, label %cond_next.cond_next73_crit_edge
-
-cond_next.cond_next73_crit_edge:		; preds = %cond_next
-	br label %cond_next73
-
-cond_true68:		; preds = %cond_next
-	br label %cond_next73
-
-cond_next73:		; preds = %cond_true68, %cond_next.cond_next73_crit_edge
-	br i1 false, label %cond_true91, label %cond_next73.cond_next96_crit_edge
-
-cond_next73.cond_next96_crit_edge:		; preds = %cond_next73
-	br label %cond_next96
-
-cond_true91:		; preds = %cond_next73
-	br label %cond_next96
-
-cond_next96:		; preds = %cond_true91, %cond_next73.cond_next96_crit_edge
-	br i1 false, label %cond_next96.cond_next112_crit_edge, label %cond_true105
-
-cond_next96.cond_next112_crit_edge:		; preds = %cond_next96
-	br label %cond_next112
-
-cond_true105:		; preds = %cond_next96
-	br label %cond_next112
-
-cond_next112:		; preds = %cond_true105, %cond_next96.cond_next112_crit_edge
-	br i1 false, label %cond_next112.cond_next127_crit_edge, label %cond_true119
-
-cond_next112.cond_next127_crit_edge:		; preds = %cond_next112
-	br label %cond_next127
-
-cond_true119:		; preds = %cond_next112
-	br label %cond_next127
-
-cond_next127:		; preds = %cond_true119, %cond_next112.cond_next127_crit_edge
-	br i1 false, label %cond_next141, label %cond_true134
-
-cond_true134:		; preds = %cond_next127
-	br i1 false, label %cond_true134.bb161_crit_edge, label %cond_true134.bb_crit_edge
-
-cond_true134.bb_crit_edge:		; preds = %cond_true134
-	br label %bb
-
-cond_true134.bb161_crit_edge:		; preds = %cond_true134
-	br label %bb161
-
-cond_next141:		; preds = %cond_next127
-	br label %bb154
-
-bb:		; preds = %bb154.bb_crit_edge, %cond_true134.bb_crit_edge
-	br label %bb154
-
-bb154:		; preds = %bb, %cond_next141
-	br i1 false, label %bb154.bb161_crit_edge, label %bb154.bb_crit_edge
-
-bb154.bb_crit_edge:		; preds = %bb154
-	br label %bb
-
-bb154.bb161_crit_edge:		; preds = %bb154
-	br label %bb161
-
-bb161:		; preds = %bb154.bb161_crit_edge, %cond_true134.bb161_crit_edge
-	br i1 false, label %bb161.cond_next201_crit_edge, label %cond_true198
-
-bb161.cond_next201_crit_edge:		; preds = %bb161
-	br label %cond_next201
-
-cond_true198:		; preds = %bb161
-	br label %cond_next201
-
-cond_next201:		; preds = %cond_true198, %bb161.cond_next201_crit_edge
-	br i1 false, label %cond_next212, label %cond_true206
-
-cond_true206:		; preds = %cond_next201
-	br label %UnifiedReturnBlock
-
-cond_false:		; preds = %entry
-	br label %UnifiedReturnBlock
-
-cond_next212:		; preds = %cond_next201
-	br label %UnifiedReturnBlock
-
-UnifiedReturnBlock:		; preds = %cond_next212, %cond_false, %cond_true206
-	ret void
-}

Removed: llvm/trunk/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll?rev=128942&view=auto
==============================================================================
--- llvm/trunk/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll (original)
+++ llvm/trunk/test/Analysis/PostDominators/2007-04-20-PostDom-Reset.ll (removed)
@@ -1,28 +0,0 @@
-; RUN: opt < %s -postdomfrontier -disable-output
-
-define void @args_out_of_range() {
-entry:
-	br label %bb
-
-bb:		; preds = %bb, %entry
-	br label %bb
-}
-
-define void @args_out_of_range_3() {
-entry:
-	br label %bb
-
-bb:		; preds = %bb, %entry
-	br label %bb
-}
-
-define void @Feq() {
-entry:
-	br i1 false, label %cond_true, label %cond_next
-
-cond_true:		; preds = %entry
-	unreachable
-
-cond_next:		; preds = %entry
-	unreachable
-}



From johnny.chen at apple.com  Tue Apr  5 17:18:08 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 22:18:08 -0000
Subject: [llvm-commits] [llvm] r128945 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
 test/MC/Disassembler/ARM/invalid-RSC-arm.txt
Message-ID: <20110405221808.1C4872A6C12D@llvm.org>

Author: johnny
Date: Tue Apr  5 17:18:07 2011
New Revision: 128945

URL: http://llvm.org/viewvc/llvm-project?rev=128945&view=rev
Log:
ARM disassembler was erroneously accepting an invalid RSC instruction.
Added checks for regs which should not be 15.

rdar://problem/9237734

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128945&r1=128944&r2=128945&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Apr  5 17:18:07 2011
@@ -1072,6 +1072,12 @@
     if (slice(insn, 7, 7))
       return false;
 
+    // A8.6.3 ADC (register-shifted register)
+    // if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
+    if (decodeRd(insn) == 15 || decodeRn(insn) == 15 ||
+        decodeRm(insn) == 15 || decodeRs(insn) == 15)
+      return false;
+    
     // Register-controlled shifts: [Rm, Rs, shift].
     MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                        decodeRs(insn))));

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt?rev=128945&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-RSC-arm.txt Tue Apr  5 17:18:07 2011
@@ -0,0 +1,9 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=261 Name=RSCrs Format=ARM_FORMAT_DPSOREGFRM(5)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 0: 0: 1: 1| 0: 0: 0: 0| 1: 1: 1: 0| 0: 1: 0: 0| 1: 1: 1: 1| 1: 0: 0: 0| 0: 1: 0: 1| 1: 1: 1: 1|
+# -------------------------------------------------------------------------------------------------
+# if d == 15 || n == 15 || m == 15 || s == 15 then UNPREDICTABLE;
+0x5f 0xf8 0xe4 0x30



From resistor at mac.com  Tue Apr  5 17:42:55 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 05 Apr 2011 22:42:55 -0000
Subject: [llvm-commits] [llvm] r128946 - in /llvm/trunk/lib/Target/ARM:
 ARMISelLowering.cpp ARMInstrInfo.td
Message-ID: <20110405224255.2F7372A6C12D@llvm.org>

Author: resistor
Date: Tue Apr  5 17:42:54 2011
New Revision: 128946

URL: http://llvm.org/viewvc/llvm-project?rev=128946&view=rev
Log:
Give RSBS and RSCS the pseudo treatment.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=128946&r1=128945&r2=128946&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Apr  5 17:42:54 2011
@@ -5029,7 +5029,12 @@
   case ARM::ADCSSrs:
   case ARM::SBCSSri:
   case ARM::SBCSSrr:
-  case ARM::SBCSSrs: {
+  case ARM::SBCSSrs:
+  case ARM::RSBSri:
+  case ARM::RSBSrr:
+  case ARM::RSBSrs:
+  case ARM::RSCSri:
+  case ARM::RSCSrs: {
     unsigned OldOpc = MI->getOpcode();
     unsigned Opc = 0;
     switch (OldOpc) {
@@ -5051,6 +5056,21 @@
       case ARM::SBCSSrs:
         Opc = ARM::SBCrs;
         break;
+      case ARM::RSBSri:
+        Opc = ARM::RSBri;
+        break;
+      case ARM::RSBSrr:
+        Opc = ARM::RSBrr;
+        break;
+      case ARM::RSBSrs:
+        Opc = ARM::RSBrs;
+        break;
+      case ARM::RSCSri:
+        Opc = ARM::RSCri;
+        break;
+      case ARM::RSCSrs:
+        Opc = ARM::RSCrs;
+        break;
       default:
         llvm_unreachable("Unknown opcode?");
     }

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128946&r1=128945&r2=128946&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Apr  5 17:42:54 2011
@@ -2243,44 +2243,16 @@
 }
 
 // RSB with 's' bit set.
-let isCodeGenOnly = 1, Defs = [CPSR] in {
-def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
-                 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
-                 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> imm;
-  let Inst{25} = 1;
-  let Inst{20} = 1;
-  let Inst{15-12} = Rd;
-  let Inst{19-16} = Rn;
-  let Inst{11-0} = imm;
-}
-def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
-                 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
-                 [/* For disassembly only; pattern left blank */]> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<4> Rm;
-  let Inst{11-4} = 0b00000000;
-  let Inst{25} = 0;
-  let Inst{20} = 1;
-  let Inst{3-0} = Rm;
-  let Inst{15-12} = Rd;
-  let Inst{19-16} = Rn;
-}
-def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
-                 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
-                 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> shift;
-  let Inst{25} = 0;
-  let Inst{20} = 1;
-  let Inst{11-0} = shift;
-  let Inst{15-12} = Rd;
-  let Inst{19-16} = Rn;
-}
+let isCodeGenOnly = 1, Defs = [CPSR], usesCustomInserter = 1 in {
+def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
+                 Size4Bytes, IIC_iALUi,
+                 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
+def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
+                 Size4Bytes, IIC_iALUr,
+                 [/* For disassembly only; pattern left blank */]>;
+def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+                 Size4Bytes, IIC_iALUsr,
+                 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
 }
 
 let Uses = [CPSR] in {
@@ -2325,33 +2297,15 @@
 }
 
 // FIXME: Allow these to be predicated.
-let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
-def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
-                  DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
+let isCodeGenOnly = 1, usesCustomInserter = 1, Defs = [CPSR], Uses = [CPSR] in {
+def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
+                  Size4Bytes, IIC_iALUi,
                   [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
-                  Requires<[IsARM]> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> imm;
-  let Inst{25} = 1;
-  let Inst{20} = 1;
-  let Inst{15-12} = Rd;
-  let Inst{19-16} = Rn;
-  let Inst{11-0} = imm;
-}
-def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
-                  DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
+                  Requires<[IsARM]>;
+def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+                  Size4Bytes, IIC_iALUsr,
                   [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
-                  Requires<[IsARM]> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> shift;
-  let Inst{25} = 0;
-  let Inst{20} = 1;
-  let Inst{11-0} = shift;
-  let Inst{15-12} = Rd;
-  let Inst{19-16} = Rn;
-}
+                  Requires<[IsARM]>;
 }
 
 // (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.



From lattner at apple.com  Tue Apr  5 17:49:08 2011
From: lattner at apple.com (Tanya Lattner)
Date: Tue, 05 Apr 2011 15:49:08 -0700
Subject: [llvm-commits] [PATCH] ARM DAG Combine on illegal types patch
Message-ID: <6759E2AB-9942-4D0E-B418-3AB269E33DAB@apple.com>

I've attached a patch that includes a fix for 2 crashes in the ARM DAG Combiner when doing an AND or OR combine on an illegal vector type (vectors of size 3). I've also included a test case.

Please review and let me know if its ok to commit. 

Thanks,
Tanya

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From dpatel at apple.com  Tue Apr  5 17:52:06 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 05 Apr 2011 22:52:06 -0000
Subject: [llvm-commits] [llvm] r128947 - in /llvm/trunk:
 docs/SourceLevelDebugging.html include/llvm/Analysis/DIBuilder.h
 include/llvm/Analysis/DebugInfo.h lib/Analysis/DIBuilder.cpp
 lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Message-ID: <20110405225206.9F13B2A6C12D@llvm.org>

Author: dpatel
Date: Tue Apr  5 17:52:06 2011
New Revision: 128947

URL: http://llvm.org/viewvc/llvm-project?rev=128947&view=rev
Log:
Add support to encode function's template parameters.

Modified:
    llvm/trunk/docs/SourceLevelDebugging.html
    llvm/trunk/include/llvm/Analysis/DIBuilder.h
    llvm/trunk/include/llvm/Analysis/DebugInfo.h
    llvm/trunk/lib/Analysis/DIBuilder.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp

Modified: llvm/trunk/docs/SourceLevelDebugging.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=128947&r1=128946&r2=128947&view=diff
==============================================================================
--- llvm/trunk/docs/SourceLevelDebugging.html (original)
+++ llvm/trunk/docs/SourceLevelDebugging.html Tue Apr  5 17:52:06 2011
@@ -441,6 +441,7 @@
   i1        ;; isArtificial
   i1        ;; isOptimized
   Function *;; Pointer to LLVM function
+  metadata  ;; Lists function template parameters
 }
 </pre>
 </div>
@@ -1200,7 +1201,14 @@
   i32 1,             ;; Line number
   metadata !4,       ;; Type
   i1 false,          ;; Is local 
-  i1 true            ;; Is definition
+  i1 true,           ;; Is definition
+  i32 0,             ;; Virtuality attribute, e.g. pure virtual function
+  i32 0,             ;; Index into virtual table for C++ methods
+  i32 0,             ;; Type that holds virtual table.
+  i32 0,             ;; Flags
+  i1 false,          ;; True if this function is optimized
+  Function *,        ;; Pointer to llvm::Function
+  null               ;; Function template parameters
 }
 ;;
 ;; Define the subprogram itself.

Modified: llvm/trunk/include/llvm/Analysis/DIBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DIBuilder.h?rev=128947&r1=128946&r2=128947&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DIBuilder.h (original)
+++ llvm/trunk/include/llvm/Analysis/DIBuilder.h Tue Apr  5 17:52:06 2011
@@ -368,6 +368,7 @@
     ///                      This flags are used to emit dwarf attributes.
     /// @param isOptimized   True if optimization is ON.
     /// @param Fn            llvm::Function pointer.
+    /// @param TParam        Function template parameters.
     DISubprogram createFunction(DIDescriptor Scope, StringRef Name,
                                 StringRef LinkageName,
                                 DIFile File, unsigned LineNo,
@@ -375,7 +376,8 @@
                                 bool isDefinition,
                                 unsigned Flags = 0,
                                 bool isOptimized = false,
-                                Function *Fn = 0);
+                                Function *Fn = 0,
+                                MDNode *TParam = 0);
 
     /// createMethod - Create a new descriptor for the specified C++ method.
     /// See comments in DISubprogram for descriptions of these fields.
@@ -395,6 +397,7 @@
     ///                      This flags are used to emit dwarf attributes.
     /// @param isOptimized   True if optimization is ON.
     /// @param Fn            llvm::Function pointer.
+    /// @param TParam        Function template parameters.
     DISubprogram createMethod(DIDescriptor Scope, StringRef Name,
                               StringRef LinkageName,
                               DIFile File, unsigned LineNo,
@@ -404,7 +407,8 @@
                               MDNode *VTableHolder = 0,
                               unsigned Flags = 0,
                               bool isOptimized = false,
-                              Function *Fn = 0);
+                              Function *Fn = 0,
+                              MDNode *TParam = 0);
 
     /// createNameSpace - This creates new descriptor for a namespace
     /// with the specified parent scope.

Modified: llvm/trunk/include/llvm/Analysis/DebugInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DebugInfo.h?rev=128947&r1=128946&r2=128947&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DebugInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/DebugInfo.h Tue Apr  5 17:52:06 2011
@@ -511,6 +511,7 @@
     bool describes(const Function *F);
 
     Function *getFunction() const { return getFunctionField(16); }
+    DIArray getTemplateParams() const { return getFieldAs<DIArray>(17); }
   };
 
   /// DIGlobalVariable - This is a wrapper for a global variable.

Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=128947&r1=128946&r2=128947&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DIBuilder.cpp (original)
+++ llvm/trunk/lib/Analysis/DIBuilder.cpp Tue Apr  5 17:52:06 2011
@@ -642,7 +642,8 @@
                                        DIType Ty,
                                        bool isLocalToUnit, bool isDefinition,
                                        unsigned Flags, bool isOptimized,
-                                       Function *Fn) {
+                                       Function *Fn,
+                                       MDNode *TParams) {
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_subprogram),
     llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
@@ -660,7 +661,8 @@
     llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
     ConstantInt::get(Type::getInt32Ty(VMContext), Flags),
     ConstantInt::get(Type::getInt1Ty(VMContext), isOptimized),
-    Fn
+    Fn,
+    TParams
   };
   MDNode *Node = MDNode::get(VMContext, &Elts[0], array_lengthof(Elts));
 
@@ -682,7 +684,8 @@
                                      MDNode *VTableHolder,
                                      unsigned Flags,
                                      bool isOptimized,
-                                     Function *Fn) {
+                                     Function *Fn,
+                                     MDNode *TParam) {
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_subprogram),
     llvm::Constant::getNullValue(Type::getInt32Ty(VMContext)),
@@ -700,7 +703,8 @@
     VTableHolder,
     ConstantInt::get(Type::getInt32Ty(VMContext), Flags),
     ConstantInt::get(Type::getInt1Ty(VMContext), isOptimized),
-    Fn
+    Fn,
+    TParam,
   };
   MDNode *Node = MDNode::get(VMContext, &Elts[0], array_lengthof(Elts));
 

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=128947&r1=128946&r2=128947&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue Apr  5 17:52:06 2011
@@ -1455,6 +1455,9 @@
     addUInt(SPDie, dwarf::DW_AT_APPLE_isa, dwarf::DW_FORM_flag, isa);
   }
 
+  // Add function template parameters.
+  addTemplateParams(*SPDie, SP.getTemplateParams());
+
   // DW_TAG_inlined_subroutine may refer to this DIE.
   SPCU->insertDIE(SP, SPDie);
 



From johnny.chen at apple.com  Tue Apr  5 17:57:07 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 22:57:07 -0000
Subject: [llvm-commits] [llvm] r128949 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
 test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
 test/MC/Disassembler/ARM/neon-tests.txt
Message-ID: <20110405225707.7DBCF2A6C12D@llvm.org>

Author: johnny
Date: Tue Apr  5 17:57:07 2011
New Revision: 128949

URL: http://llvm.org/viewvc/llvm-project?rev=128949&view=rev
Log:
A7.3 register encoding
    Qd -> bit[12] == 0
    Qn -> bit[16] == 0
    Qm -> bit[0]  == 0

If one of these bits is 1, the instruction is UNDEFINED.

rdar://problem/9238399
rdar://problem/9238445

Added:
    llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128949&r1=128948&r2=128949&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Apr  5 17:57:07 2011
@@ -94,6 +94,16 @@
   }
 
   // See also decodeNEONRd(), decodeNEONRn(), decodeNEONRm().
+  // A7.3 register encoding
+  //     Qd -> bit[12] == 0
+  //     Qn -> bit[16] == 0
+  //     Qm -> bit[0]  == 0
+  //
+  // If one of these bits is 1, the instruction is UNDEFINED.
+  if (RegClassID == ARM::QPRRegClassID && slice(RawRegister, 0, 0) == 1) {
+    B->SetErr(-1);
+    return 0;
+  }
   unsigned RegNum =
     RegClassID == ARM::QPRRegClassID ? RawRegister >> 1 : RawRegister;
 

Added: llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt?rev=128949&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt (added)
+++ llvm/trunk/test/MC/Disassembler/ARM/invalid-VQADD-arm.txt Tue Apr  5 17:57:07 2011
@@ -0,0 +1,10 @@
+# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
+
+# Opcode=1225 Name=VQADDsv16i8 Format=ARM_FORMAT_N3Reg(37)
+#  31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
+# -------------------------------------------------------------------------------------------------
+# | 1: 1: 1: 1| 0: 0: 1: 0| 0: 1: 0: 0| 0: 0: 0: 0| 1: 1: 1: 0| 0: 0: 0: 0| 1: 1: 0: 1| 1: 0: 1: 1|
+# -------------------------------------------------------------------------------------------------
+#
+# Qm -> bit[0] == 0, otherwise UNDEFINED
+0xdb 0xe0 0x40 0xf2

Modified: llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt?rev=128949&r1=128948&r2=128949&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/neon-tests.txt Tue Apr  5 17:57:07 2011
@@ -67,7 +67,7 @@
 0x5f 0xe5 0xc4 0xf2
 
 # CHECK:	vbic.i32	q2, #0xA900
-0x79 0x53 0x82 0xf3
+0x79 0x43 0x82 0xf3
 
 # CHECK:	vst2.32	{d16, d18}, [r2, :64], r2
 0x92 0x9 0x42 0xf4



From resistor at mac.com  Tue Apr  5 18:03:06 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 05 Apr 2011 23:03:06 -0000
Subject: [llvm-commits] [llvm] r128951 - in /llvm/trunk/lib/Target/ARM:
 ARMISelLowering.cpp ARMInstrInfo.td
Message-ID: <20110405230306.BE8B72A6C12D@llvm.org>

Author: resistor
Date: Tue Apr  5 18:03:06 2011
New Revision: 128951

URL: http://llvm.org/viewvc/llvm-project?rev=128951&view=rev
Log:
Revert r128946 while I figure out why it broke the buildbots.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=128951&r1=128950&r2=128951&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Apr  5 18:03:06 2011
@@ -5029,12 +5029,7 @@
   case ARM::ADCSSrs:
   case ARM::SBCSSri:
   case ARM::SBCSSrr:
-  case ARM::SBCSSrs:
-  case ARM::RSBSri:
-  case ARM::RSBSrr:
-  case ARM::RSBSrs:
-  case ARM::RSCSri:
-  case ARM::RSCSrs: {
+  case ARM::SBCSSrs: {
     unsigned OldOpc = MI->getOpcode();
     unsigned Opc = 0;
     switch (OldOpc) {
@@ -5056,21 +5051,6 @@
       case ARM::SBCSSrs:
         Opc = ARM::SBCrs;
         break;
-      case ARM::RSBSri:
-        Opc = ARM::RSBri;
-        break;
-      case ARM::RSBSrr:
-        Opc = ARM::RSBrr;
-        break;
-      case ARM::RSBSrs:
-        Opc = ARM::RSBrs;
-        break;
-      case ARM::RSCSri:
-        Opc = ARM::RSCri;
-        break;
-      case ARM::RSCSrs:
-        Opc = ARM::RSCrs;
-        break;
       default:
         llvm_unreachable("Unknown opcode?");
     }

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128951&r1=128950&r2=128951&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Apr  5 18:03:06 2011
@@ -2243,16 +2243,44 @@
 }
 
 // RSB with 's' bit set.
-let isCodeGenOnly = 1, Defs = [CPSR], usesCustomInserter = 1 in {
-def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
-                 Size4Bytes, IIC_iALUi,
-                 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
-def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
-                 Size4Bytes, IIC_iALUr,
-                 [/* For disassembly only; pattern left blank */]>;
-def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
-                 Size4Bytes, IIC_iALUsr,
-                 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
+let isCodeGenOnly = 1, Defs = [CPSR] in {
+def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
+                 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
+                 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
+  bits<4> Rd;
+  bits<4> Rn;
+  bits<12> imm;
+  let Inst{25} = 1;
+  let Inst{20} = 1;
+  let Inst{15-12} = Rd;
+  let Inst{19-16} = Rn;
+  let Inst{11-0} = imm;
+}
+def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
+                 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
+                 [/* For disassembly only; pattern left blank */]> {
+  bits<4> Rd;
+  bits<4> Rn;
+  bits<4> Rm;
+  let Inst{11-4} = 0b00000000;
+  let Inst{25} = 0;
+  let Inst{20} = 1;
+  let Inst{3-0} = Rm;
+  let Inst{15-12} = Rd;
+  let Inst{19-16} = Rn;
+}
+def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+                 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
+                 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
+  bits<4> Rd;
+  bits<4> Rn;
+  bits<12> shift;
+  let Inst{25} = 0;
+  let Inst{20} = 1;
+  let Inst{11-0} = shift;
+  let Inst{15-12} = Rd;
+  let Inst{19-16} = Rn;
+}
 }
 
 let Uses = [CPSR] in {
@@ -2297,15 +2325,33 @@
 }
 
 // FIXME: Allow these to be predicated.
-let isCodeGenOnly = 1, usesCustomInserter = 1, Defs = [CPSR], Uses = [CPSR] in {
-def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
-                  Size4Bytes, IIC_iALUi,
+let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
+def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
+                  DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
                   [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
-                  Requires<[IsARM]>;
-def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
-                  Size4Bytes, IIC_iALUsr,
+                  Requires<[IsARM]> {
+  bits<4> Rd;
+  bits<4> Rn;
+  bits<12> imm;
+  let Inst{25} = 1;
+  let Inst{20} = 1;
+  let Inst{15-12} = Rd;
+  let Inst{19-16} = Rn;
+  let Inst{11-0} = imm;
+}
+def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+                  DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
                   [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
-                  Requires<[IsARM]>;
+                  Requires<[IsARM]> {
+  bits<4> Rd;
+  bits<4> Rn;
+  bits<12> shift;
+  let Inst{25} = 0;
+  let Inst{20} = 1;
+  let Inst{11-0} = shift;
+  let Inst{15-12} = Rd;
+  let Inst{19-16} = Rn;
+}
 }
 
 // (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.



From chandlerc at gmail.com  Tue Apr  5 18:03:25 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Tue, 05 Apr 2011 23:03:25 -0000
Subject: [llvm-commits] [llvm] r128952 -
	/llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
Message-ID: <20110405230325.14D692A6C12D@llvm.org>

Author: chandlerc
Date: Tue Apr  5 18:03:24 2011
New Revision: 128952

URL: http://llvm.org/viewvc/llvm-project?rev=128952&view=rev
Log:
Provide an empty virtual destructor to go with the virtual methods in
this class. Clang was warning on this with -Wnon-virtual-dtor.

Modified:
    llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h

Modified: llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h?rev=128952&r1=128951&r2=128952&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h (original)
+++ llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h Tue Apr  5 18:03:24 2011
@@ -33,6 +33,7 @@
   void operator=(const RTDyldMemoryManager&);       // DO NOT IMPLEMENT
 public:
   RTDyldMemoryManager() {}
+  virtual ~RTDyldMemoryManager() {}
 
   // Allocate ActualSize bytes, or more, for the named function. Return
   // a pointer to the allocated memory and update Size to reflect how much



From bob.wilson at apple.com  Tue Apr  5 18:03:25 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 05 Apr 2011 23:03:25 -0000
Subject: [llvm-commits] [llvm] r128953 -
	/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
Message-ID: <20110405230325.A493A2A6C12E@llvm.org>

Author: bwilson
Date: Tue Apr  5 18:03:25 2011
New Revision: 128953

URL: http://llvm.org/viewvc/llvm-project?rev=128953&view=rev
Log:
Clean up some code for clarity.

Modified:
    llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=128953&r1=128952&r2=128953&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Apr  5 18:03:25 2011
@@ -454,6 +454,25 @@
   unsigned PRegNum = PMO.isUndef() ? UINT_MAX
     : getARMRegisterNumbering(PReg);
   unsigned Count = 1;
+  unsigned Limit = ~0U;
+
+  // vldm / vstm limit are 32 for S variants, 16 for D variants.
+
+  switch (Opcode) {
+  default: break;
+  case ARM::VSTRS:
+    Limit = 32;
+    break;
+  case ARM::VSTRD:
+    Limit = 16;
+    break;
+  case ARM::VLDRD:
+    Limit = 16;
+    break;
+  case ARM::VLDRS:
+    Limit = 32;
+    break;
+  }
 
   for (unsigned i = SIndex+1, e = MemOps.size(); i != e; ++i) {
     int NewOffset = MemOps[i].Offset;
@@ -461,13 +480,13 @@
     unsigned Reg = MO.getReg();
     unsigned RegNum = MO.isUndef() ? UINT_MAX
       : getARMRegisterNumbering(Reg);
-    // Register numbers must be in ascending order.  For VFP, the registers
-    // must also be consecutive and there is a limit of 16 double-word
-    // registers per instruction.
+    // Register numbers must be in ascending order. For VFP / NEON load and
+    // store multiples, the registers must also be consecutive and within the
+    // limit on the number of registers per instruction.
     if (Reg != ARM::SP &&
         NewOffset == Offset + (int)Size &&
-        ((isNotVFP && RegNum > PRegNum)
-         || ((Size < 8 || Count < 16) && RegNum == PRegNum+1))) {
+        ((isNotVFP && RegNum > PRegNum) ||
+         ((Count < Limit) && RegNum == PRegNum+1))) {
       Offset += Size;
       PRegNum = RegNum;
       ++Count;



From sabre at nondot.org  Tue Apr  5 18:18:20 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 05 Apr 2011 23:18:20 -0000
Subject: [llvm-commits] [llvm] r128954 -
	/llvm/trunk/docs/ProgrammersManual.html
Message-ID: <20110405231820.A2ADE2A6C12D@llvm.org>

Author: lattner
Date: Tue Apr  5 18:18:20 2011
New Revision: 128954

URL: http://llvm.org/viewvc/llvm-project?rev=128954&view=rev
Log:
mention llvm::ArrayRef, which should be use much more pervasively than
it already is.


Modified:
    llvm/trunk/docs/ProgrammersManual.html

Modified: llvm/trunk/docs/ProgrammersManual.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ProgrammersManual.html?rev=128954&r1=128953&r2=128954&view=diff
==============================================================================
--- llvm/trunk/docs/ProgrammersManual.html (original)
+++ llvm/trunk/docs/ProgrammersManual.html Tue Apr  5 18:18:20 2011
@@ -56,6 +56,7 @@
     <ul>
     <li><a href="#ds_sequential">Sequential Containers (std::vector, std::list, etc)</a>
     <ul>
+      <li><a href="#dss_arrayref">llvm/ADT/ArrayRef.h</a></li>
       <li><a href="#dss_fixedarrays">Fixed Size Arrays</a></li>
       <li><a href="#dss_heaparrays">Heap Allocated Arrays</a></li>
       <li><a href="#dss_smallvector">"llvm/ADT/SmallVector.h"</a></li>
@@ -891,6 +892,21 @@
 
 <!-- _______________________________________________________________________ -->
 <div class="doc_subsubsection">
+  <a name="dss_arrayref">llvm/ADT/ArrayRef.h</a>
+</div>
+
+<div class="doc_text">
+<p>The llvm::ArrayRef class is the preferred class to use in an interface that
+   accepts a sequential list of elements in memory and just reads from them.  By
+   taking an ArrayRef, the API can be passed a fixed size array, an std::vector,
+   an llvm::SmallVector and anything else that is contiguous in memory.
+</p>
+</div>
+
+
+  
+<!-- _______________________________________________________________________ -->
+<div class="doc_subsubsection">
   <a name="dss_fixedarrays">Fixed Size Arrays</a>
 </div>
 



From sabre at nondot.org  Tue Apr  5 18:22:33 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 05 Apr 2011 23:22:33 -0000
Subject: [llvm-commits] [llvm] r128955 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20110405232233.5D18D2A6C12D@llvm.org>

Author: lattner
Date: Tue Apr  5 18:22:33 2011
New Revision: 128955

URL: http://llvm.org/viewvc/llvm-project?rev=128955&view=rev
Log:
finished my pass through all the 2.9 commits, now to make this intelligible



Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128955&r1=128954&r2=128955&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Apr  5 18:22:33 2011
@@ -60,18 +60,14 @@
 <a href="http://llvm.org/releases/">releases page</a>.</p>
 
 </div>
-
-<!--
-Almost dead code.
-  lib/Transforms/IPO/MergeFunctions.cpp => consider for 3.0.
--->
- 
    
-<!-- Features that need text if they're finished for 3.0:
+<!-- Features that need text if they're finished for 3.1:
+  ARM EHABI
   combiner-aa?
   strong phi elim
   loop dependence analysis
   CorrelatedValuePropagation
+  lib/Transforms/IPO/MergeFunctions.cpp => consider for 3.1.
  -->
  
 <!-- *********************************************************************** -->
@@ -331,8 +327,9 @@
   
 inline asm multiple alternative constraint support.
   
-LoopIdiom: memset/memcpy formation.  Build with -ffreestanding or -fno-builtin
-  if your memcpy is being compiled into infinite recursion.
+LoopIdiom: memset/memcpy formation and memset_pattern on darwin.  Build with
+  -ffreestanding or -fno-builtin if your memcpy is being compiled into infinite
+  recursion.
   
 
 TargetLibraryInfo
@@ -351,7 +348,7 @@
 
 - DIBuilder provides simpler interface for front ends like Clang to encode debug info in LLVM IR.
   - This interface hides implementation details (e.g. DIDerivedType, existence of compile unit etc..) that any front end should not know about.
-  For example,
+  For example, DIFactory DebugFactory;
   Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type,
   findRegion(TYPE_CONTEXT(type)),
   StringRef(),
@@ -364,6 +361,7 @@
   MainTy);
   can be replaced by
   DbgTy = DBuilder.createQualifiedType(DW_TAG_volatile_type, MainTy); 
+DIFactory is gone now.
   
 PPC: Switched to MCInstPrinter, and MCCodeEmitter.  Ready to implement support
   for directly writing out mach-o object files, but noone seems interested.
@@ -372,6 +370,9 @@
   
 Scheduler now models operand latency and pipeline forwarding.
   
+Can optimize printf to iprintf when no floating point is used, for embedded
+  targets with smaller iprintf implementation.
+  
 error_code + libsystem + PathV2 changes
   The system_error header from C++0x was added.
   * Use if (error_code ec = function()) to check for error conditions
@@ -407,6 +408,7 @@
   href="CodeGenerator.html#na_instparsing">MnemonicAlias and InstAlias</a>
   
 LoopIndexSplit pass was removed, unmaintained.
+LiveValues, SimplifyHalfPowrLibCalls, and GEPSplitter were removed.
   
 include/llvm/System merged into include/llvm/Support.
  
@@ -460,12 +462,29 @@
 SPARC: Many improvements, including using the Y registers for multiplications
   and addition of a simple delay slot filler.
   
-</pre></li>
-</ul>
   
-Still todo: [110117-110228]
+udiv, ashr, lshr, shl now have exact and nuw/nsw bits: PR8862 / LangRef.html
+  
+lib/Object and llvm-objdump
 
   
+  Target Independent Code Gen:
+  The pre-register-allocation (preRA) instruction scheduler models register pressure
+  much more accurately in some cases. This allows the adoption of more
+  aggressive scheduling heuristics.
+  
+  The X86 backend has adopted a new preRA scheduling
+  mode, "list-ilp", to shorten the height of instruction schedules
+  without inducing register spills.
+  
+  The ARM backend preRA scheduler now models machine resources at cycle
+  granularity. This allows the scheduler to both accurately model
+  instruction latency and avoid overcommitting functional units.
+
+  
+</pre></li>
+</ul>
+  
 </div>
 
 <!--=========================================================================-->



From clattner at apple.com  Tue Apr  5 18:29:02 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 05 Apr 2011 16:29:02 -0700
Subject: [llvm-commits] [llvm] r128952 -
 /llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
In-Reply-To: <20110405230325.14D692A6C12D@llvm.org>
References: <20110405230325.14D692A6C12D@llvm.org>
Message-ID: <2375D85E-4855-4D89-87BC-EB36261311A7@apple.com>


On Apr 5, 2011, at 4:03 PM, Chandler Carruth wrote:

> Author: chandlerc
> Date: Tue Apr  5 18:03:24 2011
> New Revision: 128952
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=128952&view=rev
> Log:
> Provide an empty virtual destructor to go with the virtual methods in
> this class. Clang was warning on this with -Wnon-virtual-dtor.

Hi Chandler,

Please move the method out of line, since it is the only candidate for being a key function.  Thanks!

-Chris

> 
> Modified:
>    llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
> 
> Modified: llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h?rev=128952&r1=128951&r2=128952&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h (original)
> +++ llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h Tue Apr  5 18:03:24 2011
> @@ -33,6 +33,7 @@
>   void operator=(const RTDyldMemoryManager&);       // DO NOT IMPLEMENT
> public:
>   RTDyldMemoryManager() {}
> +  virtual ~RTDyldMemoryManager() {}
> 
>   // Allocate ActualSize bytes, or more, for the named function. Return
>   // a pointer to the allocated memory and update Size to reflect how much
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From johnny.chen at apple.com  Tue Apr  5 18:28:01 2011
From: johnny.chen at apple.com (Johnny Chen)
Date: Tue, 05 Apr 2011 23:28:01 -0000
Subject: [llvm-commits] [llvm] r128958 - in /llvm/trunk:
 lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
 test/MC/Disassembler/ARM/arm-tests.txt
Message-ID: <20110405232801.23CF72A6C12D@llvm.org>

Author: johnny
Date: Tue Apr  5 18:28:00 2011
New Revision: 128958

URL: http://llvm.org/viewvc/llvm-project?rev=128958&view=rev
Log:
Fix a typo in the handling of PKHTB opcode, plus add sanity check for illegal register
encodings for DisassembleArithMiscFrm().

rdar://problem/9238659

Modified:
    llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
    llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt

Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=128958&r1=128957&r2=128958&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Apr  5 18:28:00 2011
@@ -1474,6 +1474,12 @@
 
   bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::GPRRegClassID;
 
+  // Sanity check the registers, which should not be 15.
+  if (decodeRd(insn) == 15 || decodeRm(insn) == 15)
+    return false;
+  if (ThreeReg && decodeRn(insn) == 15)
+    return false;
+
   MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
                                                      decodeRd(insn))));
   ++OpIdx;
@@ -1498,7 +1504,7 @@
     ARM_AM::ShiftOpc Opc = ARM_AM::no_shift;
     if (Opcode == ARM::PKHBT)
       Opc = ARM_AM::lsl;
-    else if (Opcode == ARM::PKHBT)
+    else if (Opcode == ARM::PKHTB)
       Opc = ARM_AM::asr;
     getImmShiftSE(Opc, ShiftAmt);
     MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt)));

Modified: llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt?rev=128958&r1=128957&r2=128958&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt (original)
+++ llvm/trunk/test/MC/Disassembler/ARM/arm-tests.txt Tue Apr  5 18:28:00 2011
@@ -76,9 +76,12 @@
 # CHECK:	pkhbt	r8, r9, r10, lsl #4
 0x1a 0x82 0x89 0xe6
 
-# CHECK-NOT:	pkhbtls	pc, r11, r11, lsl #0
-# CHECK:	pkhbtls	pc, r11, r11
-0x1b 0xf0 0x8b 0x96
+# CHECK-NOT:	pkhbtls	r10, r11, r11, lsl #0
+# CHECK:	pkhbtls	r10, r11, r11
+0x1b 0xa0 0x8b 0x96
+
+# CHECK:	pkhtbmi	lr, r1, r6, asr #21
+0xd6 0xea 0x81 0x46
 
 # CHECK:	pop	{r0, r2, r4, r6, r8, r10}
 0x55 0x05 0xbd 0xe8



From grosbach at apple.com  Tue Apr  5 18:39:08 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 05 Apr 2011 23:39:08 -0000
Subject: [llvm-commits] [llvm] r128959 -
	/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h
Message-ID: <20110405233908.8E6E42A6C12D@llvm.org>

Author: grosbach
Date: Tue Apr  5 18:39:08 2011
New Revision: 128959

URL: http://llvm.org/viewvc/llvm-project?rev=128959&view=rev
Log:
Remove extraneous 'return'.

Modified:
    llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h

Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h?rev=128959&r1=128958&r2=128959&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h (original)
+++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h Tue Apr  5 18:39:08 2011
@@ -47,8 +47,7 @@
     // the address space/sizes we're compiling on are the same as what we're
     // compiling for, so it uses pointer types for its addresses. Explicit
     // casts between them to deal with that.
-    return JMM->endFunctionBody(F, (uint8_t*)FunctionStart,
-                                (uint8_t*)FunctionEnd);
+    JMM->endFunctionBody(F, (uint8_t*)FunctionStart, (uint8_t*)FunctionEnd);
   }
 
 };



From aggarwa4 at illinois.edu  Tue Apr  5 18:40:49 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 05 Apr 2011 23:40:49 -0000
Subject: [llvm-commits] [poolalloc] r128960 - in
 /poolalloc/trunk/lib/AssistDS: FuncSpec.cpp Int2PtrCmp.cpp
Message-ID: <20110405234049.B9EBB2A6C12D@llvm.org>

Author: aggarwa4
Date: Tue Apr  5 18:40:49 2011
New Revision: 128960

URL: http://llvm.org/viewvc/llvm-project?rev=128960&view=rev
Log:
Added comments.

Modified:
    poolalloc/trunk/lib/AssistDS/FuncSpec.cpp
    poolalloc/trunk/lib/AssistDS/Int2PtrCmp.cpp

Modified: poolalloc/trunk/lib/AssistDS/FuncSpec.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/FuncSpec.cpp?rev=128960&r1=128959&r2=128960&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/FuncSpec.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/FuncSpec.cpp Tue Apr  5 18:40:49 2011
@@ -121,6 +121,9 @@
   };
 }
 
+// Pass ID variable
 char FuncSpec::ID = 0;
+
+// Register the pass
 static RegisterPass<FuncSpec>
 X("funcspec", "Specialize for Function Pointers");

Modified: poolalloc/trunk/lib/AssistDS/Int2PtrCmp.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/Int2PtrCmp.cpp?rev=128960&r1=128959&r2=128960&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/Int2PtrCmp.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/Int2PtrCmp.cpp Tue Apr  5 18:40:49 2011
@@ -6,7 +6,12 @@
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "varargfunc"
+// Remove unnecessary inttoptr casts
+// Specially ones used in just compares
+// Most cases derived from InstCombine
+//
+//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "int2ptr-cmp"
 
 #include "llvm/Instructions.h"
 #include "llvm/Module.h"
@@ -32,31 +37,45 @@
   public:
     static char ID;
     Int2PtrCmp() : ModulePass(&ID) {}
+
+    //
+    // Method: runOnModule()
+    //
+    // Description:
+    //  Entry point for this LLVM pass.
+    //  Remove unnecessary inttoptr instructions.
+    //
+    // Inputs:
+    //  M - A reference to the LLVM module to transform
+    //
+    // Outputs:
+    //  M - The transformed LLVM module.
+    //
+    // Return value:
+    //  true  - The module was modified.
+    //  false - The module was not modified.
+    //
     bool runOnModule(Module& M) {
-    TD = &getAnalysis<TargetData>();
-      //std::vector<PtrToIntInst*> worklist;
+      TD = &getAnalysis<TargetData>();
       for (Module::iterator F = M.begin(); F != M.end(); ++F) {
         for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {      
           for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
+            // ptrtoint(inttoptr ty Y) to ty -> Y 
             if(PtrToIntInst *P2I = dyn_cast<PtrToIntInst>(I++)) {
               if(IntToPtrInst *I2P = dyn_cast<IntToPtrInst>(P2I->getOperand(0))) {
                 if(I2P->getSrcTy() == P2I->getDestTy()){
                   P2I->replaceAllUsesWith(I2P->getOperand(0));
                   P2I->eraseFromParent();
-                  if(I2P->use_empty())
+                  if(I2P->use_empty()) {
+                    // If this is the only use of the cast delete it.
                     I2P->eraseFromParent();
+                  }
                 }
-
               }
             }
           }
-        }
-      }
-      
-      //icmp pred inttoptr(X), null  -> icmp pred X 0
-      for (Module::iterator F = M.begin(); F != M.end(); ++F) {
-        for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {      
           for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
+            //icmp pred inttoptr(X), null  -> icmp pred X 0
             if(ICmpInst *CI = dyn_cast<ICmpInst>(I++)) {
               Value *Op0 = CI->getOperand(0);
               Value *Op1 = CI->getOperand(1);
@@ -68,11 +87,13 @@
                         LHSI->getOperand(0)->getType()){
                       ICmpInst *CI_new = new ICmpInst(CI, CI->getPredicate(), LHSI->getOperand(0),
                                                       Constant::getNullValue(LHSI->getOperand(0)->getType()));
-                      
+
                       CI->replaceAllUsesWith(CI_new);
                       CI->eraseFromParent();
-                      if(LHSI->use_empty())
+                      if(LHSI->use_empty()) {
+                        // If this is the only use of the cast delete it.
                         LHSI->eraseFromParent();
+                      }
                     }
                   }
                 }
@@ -98,10 +119,12 @@
                       break;
                     Value *P, *Q, *R;
                     if (match(LHSI, m_Or(m_PtrToInt(m_Value(P)), m_PtrToInt(m_Value(Q))))) {
+                      // Simplify icmp eq (or (ptrtoint P), (ptrtoint Q)), 0
+                      // -> and (icmp eq P, null), (icmp eq Q, null).
                       Value *ICIP = new ICmpInst(ICI, ICI->getPredicate(), P,
-                                                        Constant::getNullValue(P->getType()));
+                                                 Constant::getNullValue(P->getType()));
                       Value *ICIQ = new ICmpInst(ICI, ICI->getPredicate(), Q,
-                                                        Constant::getNullValue(Q->getType()));
+                                                 Constant::getNullValue(Q->getType()));
                       Instruction *Op;
                       if (ICI->getPredicate() == ICmpInst::ICMP_EQ)
                         Op = BinaryOperator::CreateAnd(ICIP, ICIQ,"",ICI);
@@ -109,13 +132,17 @@
                         Op = BinaryOperator::CreateOr(ICIP, ICIQ, "", ICI);
                       ICI->replaceAllUsesWith(Op);
 
-                    } else if(match(LHSI, m_Or(m_Or(m_PtrToInt(m_Value(P)), m_PtrToInt(m_Value(Q))), m_PtrToInt(m_Value(R))))) {
+                    } else if(match(LHSI, m_Or(m_Or(m_PtrToInt(m_Value(P)), 
+                                                    m_PtrToInt(m_Value(Q))), 
+                                               m_PtrToInt(m_Value(R))))) {
+                      // Simplify icmp eq (or (or (ptrtoint P), (ptrtoint Q)), ptrtoint(R)), 0
+                      // -> and (and (icmp eq P, null), (icmp eq Q, null)), (icmp eq R, null).
                       Value *ICIP = new ICmpInst(ICI, ICI->getPredicate(), P,
-                                                        Constant::getNullValue(P->getType()));
+                                                 Constant::getNullValue(P->getType()));
                       Value *ICIQ = new ICmpInst(ICI, ICI->getPredicate(), Q,
-                                                        Constant::getNullValue(Q->getType()));
+                                                 Constant::getNullValue(Q->getType()));
                       Value *ICIR = new ICmpInst(ICI, ICI->getPredicate(), R,
-                                                        Constant::getNullValue(R->getType()));
+                                                 Constant::getNullValue(R->getType()));
                       Instruction *Op;
                       if (ICI->getPredicate() == ICmpInst::ICMP_EQ)
                         Op = BinaryOperator::CreateAnd(ICIP, ICIQ,"",ICI);
@@ -128,13 +155,16 @@
                         Op = BinaryOperator::CreateOr(Op, ICIR, "", ICI);
                       ICI->replaceAllUsesWith(Op);
 
-                    } else if(match(LHSI, m_Or(m_PtrToInt(m_Value(Q)), m_Or(m_PtrToInt(m_Value(P)), m_PtrToInt(m_Value(R)))))) {
+                    } else if(match(LHSI, m_Or(m_PtrToInt(m_Value(Q)), m_Or(
+                            m_PtrToInt(m_Value(P)), m_PtrToInt(m_Value(R)))))) {
+                      // Simplify icmp eq (or  (ptrtoint P), or((ptrtoint Q), ptrtoint(R))), 0
+                      // -> and (icmp eq P, null), (and (icmp eq Q, null), (icmp eq R, null)).
                       Value *ICIP = new ICmpInst(ICI, ICI->getPredicate(), P,
-                                                        Constant::getNullValue(P->getType()));
+                                                 Constant::getNullValue(P->getType()));
                       Value *ICIQ = new ICmpInst(ICI, ICI->getPredicate(), Q,
-                                                        Constant::getNullValue(Q->getType()));
+                                                 Constant::getNullValue(Q->getType()));
                       Value *ICIR = new ICmpInst(ICI, ICI->getPredicate(), R,
-                                                        Constant::getNullValue(R->getType()));
+                                                 Constant::getNullValue(R->getType()));
                       Instruction *Op;
                       if (ICI->getPredicate() == ICmpInst::ICMP_EQ)
                         Op = BinaryOperator::CreateAnd(ICIP, ICIQ,"",ICI);
@@ -162,6 +192,9 @@
   };
 }
 
+// Pass ID variable
 char Int2PtrCmp::ID = 0;
+
+// Register the pass
 static RegisterPass<Int2PtrCmp>
-X("int2ptrcmp", "Simplify inttoptr/ptrtoint if derived from the other");
+X("int2ptrcmp", "Simplify inttoptr/ptrtoint insts");



From stoklund at 2pi.dk  Tue Apr  5 18:43:11 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 23:43:11 -0000
Subject: [llvm-commits] [llvm] r128961 -
	/llvm/trunk/lib/CodeGen/MachineVerifier.cpp
Message-ID: <20110405234311.DFE0C2A6C12D@llvm.org>

Author: stoklund
Date: Tue Apr  5 18:43:11 2011
New Revision: 128961

URL: http://llvm.org/viewvc/llvm-project?rev=128961&view=rev
Log:
Permit blocks to branch directly to a landing pad.

Treat the landing pad as a normal successor when that happens.

Modified:
    llvm/trunk/lib/CodeGen/MachineVerifier.cpp

Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=128961&r1=128960&r2=128961&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Apr  5 18:43:11 2011
@@ -402,6 +402,11 @@
   SmallVector<MachineOperand, 4> Cond;
   if (!TII->AnalyzeBranch(*const_cast<MachineBasicBlock *>(MBB),
                           TBB, FBB, Cond)) {
+    // If the block branches directly to a landing pad successor, pretend that
+    // the landing pad is a normal block.
+    LandingPadSuccs.erase(TBB);
+    LandingPadSuccs.erase(FBB);
+
     // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's
     // check whether its answers match up with reality.
     if (!TBB && !FBB) {



From stoklund at 2pi.dk  Tue Apr  5 18:43:14 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 23:43:14 -0000
Subject: [llvm-commits] [llvm] r128962 - /llvm/trunk/lib/CodeGen/SplitKit.cpp
Message-ID: <20110405234314.2C3022A6C12E@llvm.org>

Author: stoklund
Date: Tue Apr  5 18:43:14 2011
New Revision: 128962

URL: http://llvm.org/viewvc/llvm-project?rev=128962&view=rev
Log:
Don't crash when a value is defined after the last split point.

Modified:
    llvm/trunk/lib/CodeGen/SplitKit.cpp

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=128962&r1=128961&r2=128962&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Apr  5 18:43:14 2011
@@ -673,7 +673,8 @@
          "Range cannot span basic blocks");
 
   // The complement interval will be extended as needed by extendRange().
-  markComplexMapped(0, ParentVNI);
+  if (ParentVNI)
+    markComplexMapped(0, ParentVNI);
   DEBUG(dbgs() << "    overlapIntv [" << Start << ';' << End << "):");
   RegAssign.insert(Start, End, OpenIdx);
   DEBUG(dump());



From stoklund at 2pi.dk  Tue Apr  5 18:43:16 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Tue, 05 Apr 2011 23:43:16 -0000
Subject: [llvm-commits] [llvm] r128963 - /llvm/trunk/lib/CodeGen/SplitKit.cpp
Message-ID: <20110405234316.780F32A6C12F@llvm.org>

Author: stoklund
Date: Tue Apr  5 18:43:16 2011
New Revision: 128963

URL: http://llvm.org/viewvc/llvm-project?rev=128963&view=rev
Log:
Sign error

Modified:
    llvm/trunk/lib/CodeGen/SplitKit.cpp

Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=128963&r1=128962&r2=128963&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SplitKit.cpp (original)
+++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Apr  5 18:43:16 2011
@@ -81,7 +81,7 @@
 
   // If CurLI is live into a landing pad successor, move the last split point
   // back to the call that may throw.
-  if (LPad && LSP.second.isValid() && !LIS.isLiveInToMBB(*CurLI, LPad))
+  if (LPad && LSP.second.isValid() && LIS.isLiveInToMBB(*CurLI, LPad))
     return LSP.second;
   else
     return LSP.first;



From chandlerc at gmail.com  Tue Apr  5 18:54:31 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Tue, 05 Apr 2011 23:54:31 -0000
Subject: [llvm-commits] [llvm] r128964 - in /llvm/trunk:
 include/llvm/ExecutionEngine/RuntimeDyld.h
 lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
Message-ID: <20110405235431.C02FC2A6C12D@llvm.org>

Author: chandlerc
Date: Tue Apr  5 18:54:31 2011
New Revision: 128964

URL: http://llvm.org/viewvc/llvm-project?rev=128964&view=rev
Log:
Make the virtual destructor out-of-line so we have a key function.

Modified:
    llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
    llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp

Modified: llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h?rev=128964&r1=128963&r2=128964&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h (original)
+++ llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h Tue Apr  5 18:54:31 2011
@@ -33,7 +33,7 @@
   void operator=(const RTDyldMemoryManager&);       // DO NOT IMPLEMENT
 public:
   RTDyldMemoryManager() {}
-  virtual ~RTDyldMemoryManager() {}
+  virtual ~RTDyldMemoryManager();
 
   // Allocate ActualSize bytes, or more, for the named function. Return
   // a pointer to the allocated memory and update Size to reflect how much

Modified: llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp?rev=128964&r1=128963&r2=128964&view=diff
==============================================================================
--- llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp (original)
+++ llvm/trunk/lib/ExecutionEngine/RuntimeDyld/RuntimeDyld.cpp Tue Apr  5 18:54:31 2011
@@ -29,6 +29,9 @@
 using namespace llvm;
 using namespace llvm::object;
 
+// Empty out-of-line virtual destructor as the key function.
+RTDyldMemoryManager::~RTDyldMemoryManager() {}
+
 namespace llvm {
 class RuntimeDyldImpl {
   unsigned CPUType;



From resistor at mac.com  Tue Apr  5 18:55:28 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 05 Apr 2011 23:55:28 -0000
Subject: [llvm-commits] [llvm] r128965 - in /llvm/trunk/lib/Target/ARM:
 ARMISelLowering.cpp ARMInstrInfo.td
Message-ID: <20110405235528.83FE42A6C12D@llvm.org>

Author: resistor
Date: Tue Apr  5 18:55:28 2011
New Revision: 128965

URL: http://llvm.org/viewvc/llvm-project?rev=128965&view=rev
Log:
Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=128965&r1=128964&r2=128965&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Apr  5 18:55:28 2011
@@ -5029,7 +5029,12 @@
   case ARM::ADCSSrs:
   case ARM::SBCSSri:
   case ARM::SBCSSrr:
-  case ARM::SBCSSrs: {
+  case ARM::SBCSSrs:
+  case ARM::RSBSri:
+  case ARM::RSBSrr:
+  case ARM::RSBSrs:
+  case ARM::RSCSri:
+  case ARM::RSCSrs: {
     unsigned OldOpc = MI->getOpcode();
     unsigned Opc = 0;
     switch (OldOpc) {
@@ -5051,6 +5056,21 @@
       case ARM::SBCSSrs:
         Opc = ARM::SBCrs;
         break;
+      case ARM::RSBSri:
+        Opc = ARM::RSBri;
+        break;
+      case ARM::RSBSrr:
+        Opc = ARM::RSBrr;
+        break;
+      case ARM::RSBSrs:
+        Opc = ARM::RSBrs;
+        break;
+      case ARM::RSCSri:
+        Opc = ARM::RSCri;
+        break;
+      case ARM::RSCSrs:
+        Opc = ARM::RSCrs;
+        break;
       default:
         llvm_unreachable("Unknown opcode?");
     }

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128965&r1=128964&r2=128965&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Apr  5 18:55:28 2011
@@ -935,7 +935,8 @@
   }
 }
 // Carry setting variants
-let isCodeGenOnly = 1, Defs = [CPSR] in {
+// NOTE: CPSR def omitted because it will be handled by the custom inserter.
+let usesCustomInserter = 1 in {
 multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
   def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
                 Size4Bytes, IIC_iALUi,
@@ -2243,44 +2244,17 @@
 }
 
 // RSB with 's' bit set.
-let isCodeGenOnly = 1, Defs = [CPSR] in {
-def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
-                 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
-                 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> imm;
-  let Inst{25} = 1;
-  let Inst{20} = 1;
-  let Inst{15-12} = Rd;
-  let Inst{19-16} = Rn;
-  let Inst{11-0} = imm;
-}
-def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
-                 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
-                 [/* For disassembly only; pattern left blank */]> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<4> Rm;
-  let Inst{11-4} = 0b00000000;
-  let Inst{25} = 0;
-  let Inst{20} = 1;
-  let Inst{3-0} = Rm;
-  let Inst{15-12} = Rd;
-  let Inst{19-16} = Rn;
-}
-def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
-                 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
-                 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> shift;
-  let Inst{25} = 0;
-  let Inst{20} = 1;
-  let Inst{11-0} = shift;
-  let Inst{15-12} = Rd;
-  let Inst{19-16} = Rn;
-}
+// NOTE: CPSR def omitted because it will be handled by the custom inserter.
+let usesCustomInserter = 1 in {
+def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
+                 Size4Bytes, IIC_iALUi,
+                 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
+def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
+                 Size4Bytes, IIC_iALUr,
+                 [/* For disassembly only; pattern left blank */]>;
+def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+                 Size4Bytes, IIC_iALUsr,
+                 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
 }
 
 let Uses = [CPSR] in {
@@ -2325,33 +2299,16 @@
 }
 
 // FIXME: Allow these to be predicated.
-let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
-def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
-                  DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
+// NOTE: CPSR def omitted because it will be handled by the custom inserter.
+let usesCustomInserter = 1, Uses = [CPSR] in {
+def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
+                  Size4Bytes, IIC_iALUi,
                   [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
-                  Requires<[IsARM]> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> imm;
-  let Inst{25} = 1;
-  let Inst{20} = 1;
-  let Inst{15-12} = Rd;
-  let Inst{19-16} = Rn;
-  let Inst{11-0} = imm;
-}
-def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
-                  DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
+                  Requires<[IsARM]>;
+def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
+                  Size4Bytes, IIC_iALUsr,
                   [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
-                  Requires<[IsARM]> {
-  bits<4> Rd;
-  bits<4> Rn;
-  bits<12> shift;
-  let Inst{25} = 0;
-  let Inst{20} = 1;
-  let Inst{11-0} = shift;
-  let Inst{15-12} = Rd;
-  let Inst{19-16} = Rn;
-}
+                  Requires<[IsARM]>;
 }
 
 // (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.



From chandlerc at gmail.com  Tue Apr  5 19:03:02 2011
From: chandlerc at gmail.com (Chandler Carruth)
Date: Tue, 5 Apr 2011 17:03:02 -0700
Subject: [llvm-commits] [llvm] r128952 -
	/llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
In-Reply-To: <2375D85E-4855-4D89-87BC-EB36261311A7@apple.com>
References: <20110405230325.14D692A6C12D@llvm.org>
	<2375D85E-4855-4D89-87BC-EB36261311A7@apple.com>
Message-ID: <BANLkTinaGLHA+HW5R=+n7QZf2KTi4N9V1w@mail.gmail.com>

On Tue, Apr 5, 2011 at 4:29 PM, Chris Lattner <clattner at apple.com> wrote:

>
> On Apr 5, 2011, at 4:03 PM, Chandler Carruth wrote:
>
> > Author: chandlerc
> > Date: Tue Apr  5 18:03:24 2011
> > New Revision: 128952
> >
> > URL: http://llvm.org/viewvc/llvm-project?rev=128952&view=rev
> > Log:
> > Provide an empty virtual destructor to go with the virtual methods in
> > this class. Clang was warning on this with -Wnon-virtual-dtor.
>
> Hi Chandler,
>
> Please move the method out of line, since it is the only candidate for
> being a key function.  Thanks!
>

Done in r128964. Wonder if there is a feasible way to implement a warning
for *this*...


>
> -Chris
>
> >
> > Modified:
> >    llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
> >
> > Modified: llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h
> > URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h?rev=128952&r1=128951&r2=128952&view=diff
> >
> ==============================================================================
> > --- llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h (original)
> > +++ llvm/trunk/include/llvm/ExecutionEngine/RuntimeDyld.h Tue Apr  5
> 18:03:24 2011
> > @@ -33,6 +33,7 @@
> >   void operator=(const RTDyldMemoryManager&);       // DO NOT IMPLEMENT
> > public:
> >   RTDyldMemoryManager() {}
> > +  virtual ~RTDyldMemoryManager() {}
> >
> >   // Allocate ActualSize bytes, or more, for the named function. Return
> >   // a pointer to the allocated memory and update Size to reflect how
> much
> >
> >
> > _______________________________________________
> > llvm-commits mailing list
> > llvm-commits at cs.uiuc.edu
> > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From aggarwa4 at illinois.edu  Tue Apr  5 19:31:27 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Wed, 06 Apr 2011 00:31:27 -0000
Subject: [llvm-commits] [poolalloc] r128967 - in
 /poolalloc/trunk/lib/AssistDS: MergeArrayIndexGEP.cpp MergeGEP.cpp
Message-ID: <20110406003127.0DA332A6C12D@llvm.org>

Author: aggarwa4
Date: Tue Apr  5 19:31:26 2011
New Revision: 128967

URL: http://llvm.org/viewvc/llvm-project?rev=128967&view=rev
Log:
Merged into one file.

Removed:
    poolalloc/trunk/lib/AssistDS/MergeGEP.cpp
Modified:
    poolalloc/trunk/lib/AssistDS/MergeArrayIndexGEP.cpp

Modified: poolalloc/trunk/lib/AssistDS/MergeArrayIndexGEP.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/MergeArrayIndexGEP.cpp?rev=128967&r1=128966&r2=128967&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/MergeArrayIndexGEP.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/MergeArrayIndexGEP.cpp Tue Apr  5 19:31:26 2011
@@ -35,16 +35,59 @@
       for (Module::iterator F = M.begin(); F != M.end(); ++F){
         for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {      
           for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
-            GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I);
-            I++;
+            GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I++);
             if(GEP == NULL)
               continue;
             simplifyGEP(GEP);
           }
         }
       }
+      bool changed;
+      do {
+        changed = false;
+        for (Module::iterator F = M.begin(); F != M.end(); ++F) {
+          for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {      
+            for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
+              GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(I++);
+              if(GEP == NULL)
+                continue;
+              if(!isa<ArrayType>(GEP->getType()->getElementType()))
+                continue;
+              changed |= mergeUseGEPs(GEP);
+
+            }
+          }
+        }
+      } while(changed);
       return true;
     }
+    static bool mergeUseGEPs(GetElementPtrInst *GEP) {
+      bool changed = false;
+      std::vector<GetElementPtrInst*> worklist;
+      for (Value::use_iterator UI = GEP->use_begin(),
+           UE = GEP->use_end(); UI != UE; ++UI){
+        if(!isa<GetElementPtrInst>(UI))
+          break;
+        GetElementPtrInst *GEPUse = cast<GetElementPtrInst>(UI);
+        worklist.push_back(GEPUse);
+      }
+      while(!worklist.empty()) {
+        GetElementPtrInst *GEPUse = worklist.back();
+        worklist.pop_back();
+        SmallVector<Value*, 8> Indices;
+        Indices.append(GEP->op_begin()+1, GEP->op_end());
+        Indices.append(GEPUse->idx_begin()+1, GEPUse->idx_end());
+        GetElementPtrInst *GEPNew = GetElementPtrInst::Create(GEP->getOperand(0),
+                                                              Indices.begin(),
+                                                              Indices.end(),
+                                                              GEPUse->getName()+ "mod", 
+                                                              GEPUse);
+        GEPUse->replaceAllUsesWith(GEPNew);
+        GEPUse->eraseFromParent();        
+        changed = true;
+      }
+      return changed;
+    }
     static void simplifyGEP(GetElementPtrInst *GEP) {
       Value *PtrOp = GEP->getOperand(0);
       if (GEPOperator *Src = dyn_cast<GEPOperator>(PtrOp)) {
@@ -114,8 +157,6 @@
           GEP->eraseFromParent();
         }
       }
-
-
     }
   };
 }

Removed: poolalloc/trunk/lib/AssistDS/MergeGEP.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/MergeGEP.cpp?rev=128966&view=auto
==============================================================================
--- poolalloc/trunk/lib/AssistDS/MergeGEP.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/MergeGEP.cpp (removed)
@@ -1,117 +0,0 @@
-//===-- MergeGEP.cpp - Merge GEPs for indexing in arrays ------------ ----===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// 
-//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "mergegep"
-
-#include "llvm/Instructions.h"
-#include "llvm/Module.h"
-#include "llvm/Pass.h"
-#include "llvm/Instructions.h"
-#include "llvm/Constants.h"
-#include "llvm/Support/GetElementPtrTypeIterator.h"
-#include "llvm/Transforms/Utils/Cloning.h"
-#include "llvm/ADT/Statistic.h"
-#include "llvm/Support/FormattedStream.h"
-#include "llvm/Support/Debug.h"
-#include <vector>
-
-using namespace llvm;
-
-
-namespace {
-  class MergeGEP : public ModulePass {
-  public:
-    static char ID;
-    MergeGEP() : ModulePass(&ID) {}
-    bool runOnModule(Module& M) {
-      bool changed = false;
-      bool found;
-      do {
-      found = false;
-      for (Module::iterator F = M.begin(); F != M.end(); ++F){
-        for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {      
-          for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE; I++) {
-            if(!(isa<GetElementPtrInst>(I)))
-              continue;
-            GetElementPtrInst *GEP = cast<GetElementPtrInst>(I);
-            if(!isa<ArrayType>(GEP->getType()->getElementType()))
-              continue;
-            std::vector<GetElementPtrInst*> worklist;
-            for (Value::use_iterator UI = GEP->use_begin(),
-                 UE = GEP->use_end(); UI != UE; ++UI){
-              if(!isa<GetElementPtrInst>(UI))
-                break;
-              GetElementPtrInst *GEPUse = cast<GetElementPtrInst>(UI);
-              worklist.push_back(GEPUse);
-            }
-            while(!worklist.empty()){
-              GetElementPtrInst *GEPUse = worklist.back();
-              worklist.pop_back();
-              SmallVector<Value*, 8> Indices;
-              Indices.append(GEP->op_begin()+1, GEP->op_end());
-              Indices.append(GEPUse->idx_begin()+1, GEPUse->idx_end());
-              GetElementPtrInst *GEPNew = GetElementPtrInst::Create(GEP->getOperand(0),
-                                                                    Indices.begin(),
-                                                                    Indices.end(),
-                                                                    GEPUse->getName()+ "moda", 
-                                                                    GEPUse);
-              GEPUse->replaceAllUsesWith(GEPNew);
-              GEPUse->eraseFromParent();        
-              found = true;
-              changed = true;                    
-            }
-          }
-        }
-        std::vector<GetElementPtrInst*> worklist;
-        for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {      
-          for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE; I++) {
-            if(!(isa<GetElementPtrInst>(I)))
-              continue;
-            GetElementPtrInst *GEP1 = cast<GetElementPtrInst>(I);
-            if(!isa<ArrayType>(GEP1->getType()->getElementType()))
-              continue;
-            if (Constant *C = dyn_cast<Constant>(GEP1->getOperand(0))) {
-              if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
-                if (CE->getOpcode() == Instruction::GetElementPtr) {
-                  worklist.push_back(GEP1);
-                }
-              }
-            }
-          }
-        }
-        while(!worklist.empty()) {
-          GetElementPtrInst *GEP1 = worklist.back();
-          worklist.pop_back();
-          Constant *C = cast<Constant>(GEP1->getOperand(0));
-          ConstantExpr *CE = cast<ConstantExpr>(C);
-          SmallVector<Value*, 8> Indices;
-          Indices.append(CE->op_begin()+1, CE->op_end());
-          Indices.append(GEP1->idx_begin()+1, GEP1->idx_end());
-          GetElementPtrInst *GEPNew = GetElementPtrInst::Create(CE->getOperand(0),
-                                                                Indices.begin(),
-                                                                Indices.end(),
-                                                                GEP1->getName()+ "modb", 
-                                                                GEP1);
-          GEP1->replaceAllUsesWith(GEPNew);
-          GEP1->eraseFromParent();
-          changed = true;                    
-          found = true;
-        }
-      }
-      }while(found);
-      return changed;
-    }
-  };
-}
-
-char MergeGEP::ID = 0;
-static RegisterPass<MergeGEP>
-X("mergegep", "Merge GEPs for arrays in structs");



From grosbach at apple.com  Tue Apr  5 19:42:00 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 05 Apr 2011 17:42:00 -0700
Subject: [llvm-commits] [llvm] r128965 - in /llvm/trunk/lib/Target/ARM:
 ARMISelLowering.cpp ARMInstrInfo.td
In-Reply-To: <20110405235528.83FE42A6C12D@llvm.org>
References: <20110405235528.83FE42A6C12D@llvm.org>
Message-ID: <7EBCD82E-7944-4FC5-9724-1E639BA236BE@apple.com>

Yay! All around goodness.

 A couple of trivial cleanup comments below.

On Apr 5, 2011, at 4:55 PM, Owen Anderson wrote:

> Author: resistor
> Date: Tue Apr  5 18:55:28 2011
> New Revision: 128965
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=128965&view=rev
> Log:
> Reapply r128946 (pseudoization of various instructions), and fix the extra imp-def of CPSR it was adding.
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=128965&r1=128964&r2=128965&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Apr  5 18:55:28 2011
> @@ -5029,7 +5029,12 @@
>   case ARM::ADCSSrs:
>   case ARM::SBCSSri:
>   case ARM::SBCSSrr:
> -  case ARM::SBCSSrs: {
> +  case ARM::SBCSSrs:
> +  case ARM::RSBSri:
> +  case ARM::RSBSrr:
> +  case ARM::RSBSrs:
> +  case ARM::RSCSri:
> +  case ARM::RSCSrs: {
>     unsigned OldOpc = MI->getOpcode();
>     unsigned Opc = 0;
>     switch (OldOpc) {
> @@ -5051,6 +5056,21 @@
>       case ARM::SBCSSrs:
>         Opc = ARM::SBCrs;
>         break;
> +      case ARM::RSBSri:
> +        Opc = ARM::RSBri;
> +        break;
> +      case ARM::RSBSrr:
> +        Opc = ARM::RSBrr;
> +        break;
> +      case ARM::RSBSrs:
> +        Opc = ARM::RSBrs;
> +        break;
> +      case ARM::RSCSri:
> +        Opc = ARM::RSCri;
> +        break;
> +      case ARM::RSCSrs:
> +        Opc = ARM::RSCrs;
> +        break;
>       default:
>         llvm_unreachable("Unknown opcode?");
>     }
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=128965&r1=128964&r2=128965&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Apr  5 18:55:28 2011
> @@ -935,7 +935,8 @@
>   }
> }
> // Carry setting variants
> -let isCodeGenOnly = 1, Defs = [CPSR] in {
> +// NOTE: CPSR def omitted because it will be handled by the custom inserter.
> +let usesCustomInserter = 1 in {
> multiclass AI1_adde_sube_s_irs<PatFrag opnode, bit Commutable = 0> {
>   def Sri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
>                 Size4Bytes, IIC_iALUi,
> @@ -2243,44 +2244,17 @@
> }
> 
> // RSB with 's' bit set.
> -let isCodeGenOnly = 1, Defs = [CPSR] in {
> -def RSBSri : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm), DPFrm,
> -                 IIC_iALUi, "rsbs", "\t$Rd, $Rn, $imm",
> -                 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]> {
> -  bits<4> Rd;
> -  bits<4> Rn;
> -  bits<12> imm;
> -  let Inst{25} = 1;
> -  let Inst{20} = 1;
> -  let Inst{15-12} = Rd;
> -  let Inst{19-16} = Rn;
> -  let Inst{11-0} = imm;
> -}
> -def RSBSrr : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
> -                 IIC_iALUr, "rsbs", "\t$Rd, $Rn, $Rm",
> -                 [/* For disassembly only; pattern left blank */]> {
> -  bits<4> Rd;
> -  bits<4> Rn;
> -  bits<4> Rm;
> -  let Inst{11-4} = 0b00000000;
> -  let Inst{25} = 0;
> -  let Inst{20} = 1;
> -  let Inst{3-0} = Rm;
> -  let Inst{15-12} = Rd;
> -  let Inst{19-16} = Rn;
> -}
> -def RSBSrs : AI1<0b0011, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> -                 DPSoRegFrm, IIC_iALUsr, "rsbs", "\t$Rd, $Rn, $shift",
> -                 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]> {
> -  bits<4> Rd;
> -  bits<4> Rn;
> -  bits<12> shift;
> -  let Inst{25} = 0;
> -  let Inst{20} = 1;
> -  let Inst{11-0} = shift;
> -  let Inst{15-12} = Rd;
> -  let Inst{19-16} = Rn;
> -}
> +// NOTE: CPSR def omitted because it will be handled by the custom inserter.
> +let usesCustomInserter = 1 in {
> +def RSBSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
> +                 Size4Bytes, IIC_iALUi,
> +                 [(set GPR:$Rd, (subc so_imm:$imm, GPR:$Rn))]>;
> +def RSBSrr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
> +                 Size4Bytes, IIC_iALUr,
> +                 [/* For disassembly only; pattern left blank */]>;
> +def RSBSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> +                 Size4Bytes, IIC_iALUsr,
> +                 [(set GPR:$Rd, (subc so_reg:$shift, GPR:$Rn))]>;
> }
> 
> let Uses = [CPSR] in {
> @@ -2325,33 +2299,16 @@
> }
> 
> // FIXME: Allow these to be predicated.

Can remove this FIXME now, I think. This should do just that, as well as other goodness. :)

> -let isCodeGenOnly = 1, Defs = [CPSR], Uses = [CPSR] in {
> -def RSCSri : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
> -                  DPFrm, IIC_iALUi, "rscs\t$Rd, $Rn, $imm",
> +// NOTE: CPSR def omitted because it will be handled by the custom inserter.
> +let usesCustomInserter = 1, Uses = [CPSR] in {
> +def RSCSri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm),
> +                  Size4Bytes, IIC_iALUi,
>                   [(set GPR:$Rd, (sube_dead_carry so_imm:$imm, GPR:$Rn))]>,
> -                  Requires<[IsARM]> {
> -  bits<4> Rd;
> -  bits<4> Rn;
> -  bits<12> imm;
> -  let Inst{25} = 1;
> -  let Inst{20} = 1;
> -  let Inst{15-12} = Rd;
> -  let Inst{19-16} = Rn;
> -  let Inst{11-0} = imm;
> -}
> -def RSCSrs : AXI1<0b0111, (outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> -                  DPSoRegFrm, IIC_iALUsr, "rscs\t$Rd, $Rn, $shift",
> +                  Requires<[IsARM]>;
> +def RSCSrs : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_reg:$shift),
> +                  Size4Bytes, IIC_iALUsr,
>                   [(set GPR:$Rd, (sube_dead_carry so_reg:$shift, GPR:$Rn))]>,
> -                  Requires<[IsARM]> {
> -  bits<4> Rd;
> -  bits<4> Rn;
> -  bits<12> shift;
> -  let Inst{25} = 0;
> -  let Inst{20} = 1;
> -  let Inst{11-0} = shift;
> -  let Inst{15-12} = Rd;
> -  let Inst{19-16} = Rn;
> -}
> +                  Requires<[IsARM]>;

No need for an explicit "Requires<[IsARM]>" here, as that's already added by the ARMPseudoInst base class.

> }
> 
> // (sub X, imm) gets canonicalized to (add X, -imm).  Match this form.
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From sabre at nondot.org  Tue Apr  5 19:45:11 2011
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 06 Apr 2011 00:45:11 -0000
Subject: [llvm-commits] [llvm] r128968 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20110406004511.B4D4C2A6C12D@llvm.org>

Author: lattner
Date: Tue Apr  5 19:45:11 2011
New Revision: 128968

URL: http://llvm.org/viewvc/llvm-project?rev=128968&view=rev
Log:
distribute content out to the appropriate sections

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128968&r1=128967&r2=128968&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Apr  5 19:45:11 2011
@@ -102,7 +102,7 @@
 modular, library-based architecture that makes it suitable for creating or
 integrating with other development tools. Clang is considered a
 production-quality compiler for C, Objective-C, C++ and Objective-C++ on x86
-(32- and 64-bit), and for darwin-arm targets.</p>
+(32- and 64-bit), and for darwin/arm targets.</p>
 
 <p>In the LLVM 2.9 time-frame, the Clang team has made many improvements in C,
 C++ and Objective-C support.  C++ support is now generally rock solid, has
@@ -293,137 +293,80 @@
 <p>LLVM 2.9 includes several major new capabilities:</p>
 
 <ul>
-<li><pre>
-  last release for llvm-gcc
-TBAA: On by default in clang.  Disable it with -fno-strict-aliasing.
+  
+<li>
+  TBAA: On by default in clang.  Disable it with -fno-strict-aliasing.
   Could be more aggressive for structs.
+</li>
+
+<li>New Nvidia PTX backend, not generally useful in 2.9 though.</li>
   
-Triple::normalize is new, llvm triples are always stored in normalized form internally.
+<li>
+Much better debug info generated, particularly in optimized code situations.
+</li>
 
-Triple x86_64--mingw64 is obsoleted. Use x86_64--mingw32 instead.
+<li>
+inline asm multiple alternative constraint support.
+</li>  
+  
+<li>
+  New naming rules in coding standards: CodingStandards.html#ll_naming
+</li>
 
-MC Assembler: X86 now generates much better diagnostics for common errors,
-    is much faster at matching instructions, is much more bug-compatible with
-    the GAS assembler, and is now generally useful for a broad range of X86
-    assembly.
+</ul>
   
-New Nvidia PTX backend, not generally useful in 2.9 though.
+</div>
 
-Much better debug info generated, particularly in optimized code situations.
+<!--=========================================================================-->
+<h2>
+<a name="coreimprovements">LLVM IR and Core Improvements</a>
+</h2>
 
-ARM Fast ISel
+<div class="doc_text">
+<p>LLVM IR has several new features for better support of new targets and that
+expose new optimization opportunities:</p>
 
-ELF MC support: on by default in clang.  There are still known missing features
-  for human written assembly.
+<ul>
+<li>udiv, ashr, lshr, shl now have exact and nuw/nsw bits:
+  PR8862 / LangRef.html</li>
+  
+  unnamed_addr + PR8927
 
-X86: Reimplemented all of MMX to introduce a new LLVM IR x86_mmx type.  Now
-  random types like &lt;2 x i32&gt; are not iseld to mmx without emms.  The
-  -disable-mmx flag is gone now.
+  new 'hotpatch' attribute: LangRef.html#fnattrs
 
-Some basic <a href="CodeGenerator.html#mc">internals documentation</a> for MC. 
-  
-MC Assembler support for .file and .loc.
-  
-  
-inline asm multiple alternative constraint support.
-  
-LoopIdiom: memset/memcpy formation and memset_pattern on darwin.  Build with
-  -ffreestanding or -fno-builtin if your memcpy is being compiled into infinite
-  recursion.
-  
+</ul>
 
-TargetLibraryInfo
-  
-X86 support for FS/GS relative loads and stores using address space 256/257 are
-  reliable now.
-  
-ARM: New code placement pass.
-  
-unnamed_addr + PR8927
-  
-PointerTracking has been removed from mainline, moved to ClamAV.
-  
-EarlyCSE pass.
-LoopInstSimplify pass.
+</div>
 
-- DIBuilder provides simpler interface for front ends like Clang to encode debug info in LLVM IR.
-  - This interface hides implementation details (e.g. DIDerivedType, existence of compile unit etc..) that any front end should not know about.
-  For example, DIFactory DebugFactory;
-  Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type,
-  findRegion(TYPE_CONTEXT(type)),
-  StringRef(),
-  getOrCreateFile(main_input_filename),
-  0 /*line no*/,
-  NodeSizeInBits(type),
-  NodeAlignInBits(type),
-  0 /*offset */,
-  0 /* flags */,
-  MainTy);
-  can be replaced by
-  DbgTy = DBuilder.createQualifiedType(DW_TAG_volatile_type, MainTy); 
-DIFactory is gone now.
-  
-PPC: Switched to MCInstPrinter, and MCCodeEmitter.  Ready to implement support
-  for directly writing out mach-o object files, but noone seems interested.
+<!--=========================================================================-->
+<h2>
+<a name="optimizer">Optimizer Improvements</a>
+</h2>
 
-ARM: Improved code generation for Cortex-A8 and Cortex-A9 CPUs.
-  
-Scheduler now models operand latency and pipeline forwarding.
-  
-Can optimize printf to iprintf when no floating point is used, for embedded
-  targets with smaller iprintf implementation.
-  
-error_code + libsystem + PathV2 changes
-  The system_error header from C++0x was added.
-  * Use if (error_code ec = function()) to check for error conditions
-  from functions which return it.
-  * error_code::message returns a human readable description of the error.
-  
-  PathV1 has been deprecated in favor of PathV2 (sorry I didn't finish
-  this before the release).
-  * No Path class, use a r-value convertible to a twine instead.
-  * Assumes all paths are UTF-8.
-  
-new macho-dump tool
+<div class="doc_text">
 
-Major regalloc rewrite, not on by default for 2.9 and not advised to use it.
- * New basic register allocator that can be used as a safe fallback when
-   debugging. Enable with -regalloc=basic.
- * New infrastructure for live range splitting. SplitKit can break a live
-   interval into smaller pieces while preserving SSA form, and SpillPlacement
-   can help find the best split points. This is a work in progress so the API
-   is changing quickly.
- * The inline spiller has learned to clean up after live range splitting. It
-   can hoist spills out of loops, and it can eliminate redundant spills.
-   Rematerialization works with live range splitting.
- * New greedy register allocator using live range splitting. This will be the
-   default register allocator in the next LLVM release, but it is not turned on
-   by default in 2.9.
+<p>In addition to a large array of minor performance tweaks and bug fixes, this
+release includes a few major enhancements and additions to the optimizers:</p>
 
-ARM: __builtin_prefetch turns into prefetch instructions.
-  
-MC assembler support for 3dNow! and 3DNowA instructions.
+<ul>
+  <li>LTO has been improved to use MC for parsing inline asm and now
+  can build large programs like Firefox 4 on both OS X and Linux.</li>
   
-tblgen support for assembler aliases: <a 
-  href="CodeGenerator.html#na_instparsing">MnemonicAlias and InstAlias</a>
   
-LoopIndexSplit pass was removed, unmaintained.
-LiveValues, SimplifyHalfPowrLibCalls, and GEPSplitter were removed.
+ LoopIdiom: memset/memcpy formation and memset_pattern on darwin.  Build with
+  -ffreestanding or -fno-builtin if your memcpy is being compiled into infinite
+  recursion.
   
-include/llvm/System merged into include/llvm/Support.
- 
-Win32 PE-COFF support in the MC assembler has made a lot of progress in the 2.9
-  timeframe, but is still not generally useful.  Please see 
-  "http://llvm.org/bugs/showdependencytree.cgi?id=9100&amp;hide_resolved=1" for open bugs?
-
+  TargetLibraryInfo
+    
+  EarlyCSE pass.
+  LoopInstSimplify pass.
+    
 New <a href="WritingAnLLVMPass.html#RegionPass">RegionPass</a> infrastructure
   for region-based optimizations.
   
-MicroBlaze: major updates for aggressive delay slot filler, MC-based assembly
-   printing, assembly instruction parsing, ELF .o file emission, and MC
-   instruction disassembler.
-  
-Countless ARM microoptimizations.
+  Can optimize printf to iprintf when no floating point is used, for embedded
+  targets with smaller iprintf implementation.
 
 Speedups to various mid-level passes:
   GVN is much faster on functions with deep dominator trees / lots of BBs.
@@ -431,18 +374,9 @@
     more passes (so they are computed less often)
   SRoA is also much faster and doesn't use DominanceFrontier.
   
-  
-new 'hotpatch' attribute: LangRef.html#fnattrs
-
-APInt API changes, see PR5207.
-
 DSE is more aggressive with stores of different types: e.g. a large store 
   following a small one to the same address.
   
-New naming rules in coding standards: CodingStandards.html#ll_naming
-  
-LiveDebugVariables is a new pass that keeps track of debugging information for
-  user variables that are kept in registers in optimized builds.
   
 We now optimize various idioms for overflow detection into check of the flag
   register on various CPUs, e.g.:
@@ -452,69 +386,7 @@
   	addq	%rdi, %rbx
   	jno	LBB0_2
 
-X86: Much better codegen for several cases using adc/sbb instead of cmovs for
-  conditional increment and other idioms.
-  
-MVT::Flag renamed to MVT::Glue
-  
-Removed the PartialSpecialization pass, it was unmaintained and buggy.
-  
-SPARC: Many improvements, including using the Y registers for multiplications
-  and addition of a simple delay slot filler.
-  
-  
-udiv, ashr, lshr, shl now have exact and nuw/nsw bits: PR8862 / LangRef.html
-  
-lib/Object and llvm-objdump
-
   
-  Target Independent Code Gen:
-  The pre-register-allocation (preRA) instruction scheduler models register pressure
-  much more accurately in some cases. This allows the adoption of more
-  aggressive scheduling heuristics.
-  
-  The X86 backend has adopted a new preRA scheduling
-  mode, "list-ilp", to shorten the height of instruction schedules
-  without inducing register spills.
-  
-  The ARM backend preRA scheduler now models machine resources at cycle
-  granularity. This allows the scheduler to both accurately model
-  instruction latency and avoid overcommitting functional units.
-
-  
-</pre></li>
-</ul>
-  
-</div>
-
-<!--=========================================================================-->
-<h2>
-<a name="coreimprovements">LLVM IR and Core Improvements</a>
-</h2>
-
-<div class="doc_text">
-<p>LLVM IR has several new features for better support of new targets and that
-expose new optimization opportunities:</p>
-
-<ul>
-</ul>
-
-</div>
-
-<!--=========================================================================-->
-<h2>
-<a name="optimizer">Optimizer Improvements</a>
-</h2>
-
-<div class="doc_text">
-
-<p>In addition to a large array of minor performance tweaks and bug fixes, this
-release includes a few major enhancements and additions to the optimizers:</p>
-
-<ul>
-  <li>TBAA.</li>
-  <li>LTO has been improved to use MC for parsing inline asm and now
-  can build large programs like Firefox 4 on both OS X and Linux.</li>
 </ul>
 
 <!--
@@ -547,6 +419,39 @@
   <li>MC supports the <tt>.cfi_*</tt> directives for producing DWARF
   frame information, but it is still not used by CodeGen by default.</li>
   <li>COFF support?</li>
+  
+  
+  MC Assembler: X86 now generates much better diagnostics for common errors,
+  is much faster at matching instructions, is much more bug-compatible with
+  the GAS assembler, and is now generally useful for a broad range of X86
+  assembly.
+  
+  
+  ELF MC support: on by default in clang.  There are still known missing features
+  for human written assembly.
+  
+  
+  Some basic <a href="CodeGenerator.html#mc">internals documentation</a> for MC. 
+  
+  MC Assembler support for .file and .loc.
+  
+  tblgen support for assembler aliases: <a 
+    href="CodeGenerator.html#na_instparsing">MnemonicAlias and InstAlias</a>
+  
+  Win32 PE-COFF support in the MC assembler has made a lot of progress in the 2.9
+  timeframe, but is still not generally useful.  Please see 
+  "http://llvm.org/bugs/showdependencytree.cgi?id=9100&amp;hide_resolved=1" for open bugs?
+  
+  
+  lib/Object and llvm-objdump
+  Experimental format independent object file manipulation library.
+  * Supports PE/COFF and ELF.
+  * llvm-nm extended to work with object files. Exactly matches
+  binutils-nm for the files I've tested.
+  * llvm-objdump added with support for disassembly (no relocations displayed).
+  
+
+
 </ul>
 
 <p>For more information, please see the <a
@@ -569,7 +474,34 @@
 
 <ul>
 <!-- SplitKit -->
-FastISel for ARM.
+  
+<li>The pre-register-allocation (preRA) instruction scheduler models register
+  pressure much more accurately in some cases. This allows the adoption of more
+    aggressive scheduling heuristics.
+</li>
+  
+  LiveDebugVariables is a new pass that keeps track of debugging information for
+  user variables that are kept in registers in optimized builds.
+  
+
+Scheduler now models operand latency and pipeline forwarding.
+  
+Major regalloc rewrite, not on by default for 2.9 and not advised to use it.
+ * New basic register allocator that can be used as a safe fallback when
+   debugging. Enable with -regalloc=basic.
+ * New infrastructure for live range splitting. SplitKit can break a live
+   interval into smaller pieces while preserving SSA form, and SpillPlacement
+   can help find the best split points. This is a work in progress so the API
+   is changing quickly.
+ * The inline spiller has learned to clean up after live range splitting. It
+   can hoist spills out of loops, and it can eliminate redundant spills.
+   Rematerialization works with live range splitting.
+ * New greedy register allocator using live range splitting. This will be the
+   default register allocator in the next LLVM release, but it is not turned on
+   by default in 2.9.
+
+
+
 </ul>
 </div>
 
@@ -583,6 +515,30 @@
 </p>
 
 <ul>
+<li>
+X86: Reimplemented all of MMX to introduce a new LLVM IR x86_mmx type.  Now
+  random types like &lt;2 x i32&gt; are not iseld to mmx without emms.  The
+  -disable-mmx flag is gone now.
+</li>
+  
+  <li>
+X86 support for FS/GS relative loads and stores using address space 256/257 are
+  reliable now.
+  </li>
+  
+    <li>
+X86: Much better codegen for several cases using adc/sbb instead of cmovs for
+  conditional increment and other idioms.
+    </li>
+
+  <li>
+  The X86 backend has adopted a new preRA scheduling
+  mode, "list-ilp", to shorten the height of instruction schedules
+  without inducing register spills.
+  </li>
+
+  MC assembler support for 3dNow! and 3DNowA instructions.
+  
   <li>Several bugs have been fixed for Windows x64 code generator.</li>
 </ul>
 
@@ -598,9 +554,39 @@
 </p>
 
 <ul>
+<li>ARM Fast ISel</li>
+<li>ARM: New code placement pass.</li>
+<li>ARM: Improved code generation for Cortex-A8 and Cortex-A9 CPUs.</li>
+<li>ARM: __builtin_prefetch turns into prefetch instructions.</li>
+<li>Countless ARM microoptimizations.</li>
+
+<li>  The ARM backend preRA scheduler now models machine resources at cycle
+  granularity. This allows the scheduler to both accurately model
+  instruction latency and avoid overcommitting functional units.</li>
+
+
 </ul>
 </div>
+  
+<!--=========================================================================-->
+<h2>
+<a name="OtherTS">Other Target Specific Improvements</a>
+</h2>
 
+<div class="doc_text">
+<ul>
+  PPC: Switched to MCInstPrinter, and MCCodeEmitter.  Ready to implement support
+  for directly writing out mach-o object files, but noone seems interested.
+  
+  MicroBlaze: major updates for aggressive delay slot filler, MC-based assembly
+  printing, assembly instruction parsing, ELF .o file emission, and MC
+  instruction disassembler.
+  
+  SPARC: Many improvements, including using the Y registers for multiplications
+  and addition of a simple delay slot filler.
+  
+</ul>
+</div>
 
 <!--=========================================================================-->
 <h2>
@@ -614,30 +600,78 @@
 from the previous release.</p>
 
 <ul>
-</ul>
+  last release for llvm-gcc
+
+- DIBuilder provides simpler interface for front ends like Clang to encode debug info in LLVM IR.
+  - This interface hides implementation details (e.g. DIDerivedType, existence of compile unit etc..) that any front end should not know about.
+  For example, DIFactory DebugFactory;
+  Ty = DebugFactory.CreateDerivedType(DW_TAG_volatile_type,
+  findRegion(TYPE_CONTEXT(type)),
+  StringRef(),
+  getOrCreateFile(main_input_filename),
+  0 /*line no*/,
+  NodeSizeInBits(type),
+  NodeAlignInBits(type),
+  0 /*offset */,
+  0 /* flags */,
+  MainTy);
+  can be replaced by
+  DbgTy = DBuilder.createQualifiedType(DW_TAG_volatile_type, MainTy); 
+DIFactory is gone now.
+  
+    
 
 
 
-<p>In addition, many APIs have changed in this release.  Some of the major LLVM
-API changes are:</p>
-<ul>
+  
+  LoopIndexSplit pass was removed, unmaintained.
+  LiveValues, SimplifyHalfPowrLibCalls, and GEPSplitter were removed.
+  Removed the PartialSpecialization pass, it was unmaintained and buggy.
+  
+  DIFactory removed, use DIBuilder instead.
+  
+  Triple::normalize is new, llvm triples are always stored in normalized form internally.
+  
+  Triple x86_64--mingw64 is obsoleted. Use x86_64--mingw32 instead.
+
+  PointerTracking has been removed from mainline, moved to ClamAV.
+
 </ul>
 
 </div>
 
 <!--=========================================================================-->
 <h2>
-<a name="devtree_changes">Development Infrastructure Changes</a>
+<a name="api_changes">Internal API Changes</a>
 </h2>
 
 <div class="doc_text">
 
-<p>This section lists changes to the LLVM development infrastructure. This
-mostly impacts users who actively work on LLVM or follow development on
-mainline, but may also impact users who leverage the LLVM build infrastructure
-or are interested in LLVM qualification.</p>
+<p>In addition, many APIs have changed in this release.  Some of the major
+  LLVM API changes are:</p>
 
 <ul>
+  
+  include/llvm/System merged into include/llvm/Support.
+  
+  
+  APInt API changes, see PR5207.
+  
+  MVT::Flag renamed to MVT::Glue
+  
+  
+  error_code + libsystem + PathV2 changes
+  The system_error header from C++0x was added.
+  * Use if (error_code ec = function()) to check for error conditions
+  from functions which return it.
+  * error_code::message returns a human readable description of the error.
+  
+  PathV1 has been deprecated in favor of PathV2 (sorry I didn't finish
+  this before the release).
+  * No Path class, use a r-value convertible to a twine instead.
+  * Assumes all paths are UTF-8.
+  
+
 </ul>
 </div>
 



From sabre at nondot.org  Tue Apr  5 19:56:12 2011
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 06 Apr 2011 00:56:12 -0000
Subject: [llvm-commits] [llvm] r128969 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20110406005612.5F77B2A6C12D@llvm.org>

Author: lattner
Date: Tue Apr  5 19:56:12 2011
New Revision: 128969

URL: http://llvm.org/viewvc/llvm-project?rev=128969&view=rev
Log:
some edits.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128969&r1=128968&r2=128969&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Apr  5 19:56:12 2011
@@ -106,7 +106,8 @@
 
 <p>In the LLVM 2.9 time-frame, the Clang team has made many improvements in C,
 C++ and Objective-C support.  C++ support is now generally rock solid, has
-been exercised on a broad variety of code, and has several new C++'0x features
+been exercised on a broad variety of code, and has several new <a 
+href="http://clang.llvm.org/cxx_status.html#cxx0x">C++'0x features</a>
 implemented (such as rvalue references and variadic templates).  LLVM 2.9 has
 also brought in a large range of bug fixes and minor features (e.g. __label__
 support), and is much more compatible with the Linux Kernel.</p>  
@@ -143,8 +144,8 @@
 The 2.9 release has the following notable changes:
 <ul>
 <li>The plugin is much more stable when compiling Fortran.</li>
-<li>Inline asm where an asm output is tied to an input of a different size is
-now supported in many more cases.</li>
+<li>Inline assembly where an asm output is tied to an input of a different size
+is now supported in many more cases.</li>
 <li>Basic support for the __float128 type was added.  It is now possible to
 generate LLVM IR from programs using __float128 but code generation does not
 work yet.</li>
@@ -169,15 +170,13 @@
 this and other low-level routines (some are 3x faster than the equivalent
 libgcc routines).</p>
 
-<p>
-All of the code in the compiler-rt project is available under the standard LLVM
-License, a "BSD-style" license.  
-
-compiler_rt is now dual licensed under MIT and UIUC license
-  
-Several minor changes for better ARM support.
-
-New in LLVM 2.9,  UPDATE</p>
+<p>In the LLVM 2.9 timeframe, compiler_rt has had several minor changes for
+  better ARM support, and a fairly major license change.  All of the code in the
+  compiler-rt project is now <a href="DeveloperPolicy.html#license">dual
+  licensed</a> under MIT and UIUC license, which allows you to use compiler-rt
+  in applications without the binary copyright reproduction clause.  If you
+  prefer the LLVM/UIUC license, you are free to continue using it under that
+  license as well.</p>
 
 </div>
 
@@ -195,15 +194,11 @@
 LLVM disassembler and the LLVM JIT.</p>
 
 <p>
-LLDB is in early development and not included as part of the LLVM 2.9 release,
-
-  
-  
-<!--
-but is mature enough to support basic debugging scenarios on Mac OS X in C,
-Objective-C and C++.  We'd really like help extending and expanding LLDB to 
-support new platforms, new languages, new architectures, and new features.-->
-</p>
+LLDB is has advanced by leaps and bounds in the 2.9 timeframe.  It is
+dramatically more stable and useful, and includes both a new <a 
+href="http://lldb.llvm.org/tutorial.html">tutorial</a> and a <a
+href="http://lldb.llvm.org/lldb-gdb.html">side-by-side comparison with 
+GDB</a>.</p>
 
 </div>
 



From sabre at nondot.org  Tue Apr  5 19:59:18 2011
From: sabre at nondot.org (Chris Lattner)
Date: Wed, 06 Apr 2011 00:59:18 -0000
Subject: [llvm-commits] [llvm] r128970 - /llvm/trunk/docs/ReleaseNotes.html
Message-ID: <20110406005918.C29322A6C12D@llvm.org>

Author: lattner
Date: Tue Apr  5 19:59:18 2011
New Revision: 128970

URL: http://llvm.org/viewvc/llvm-project?rev=128970&view=rev
Log:
some libc++ notes.

Modified:
    llvm/trunk/docs/ReleaseNotes.html

Modified: llvm/trunk/docs/ReleaseNotes.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ReleaseNotes.html?rev=128970&r1=128969&r2=128970&view=diff
==============================================================================
--- llvm/trunk/docs/ReleaseNotes.html (original)
+++ llvm/trunk/docs/ReleaseNotes.html Tue Apr  5 19:59:18 2011
@@ -215,13 +215,13 @@
 delivering great performance.</p>
 
 <p>
-As of the LLVM 2.9 release, UPDATE!
-
-libc++ is now dual licensed under MIT and UIUC license
+In the LLVM 2.9 timeframe, libc++ has had numerous bugs fixed, and is now being
+co-developed with Clang's C++'0x mode.</p>
   
-<!--libc++ is virtually feature complete, but would
-benefit from more testing and better integration with Clang++.  It is also
-looking forward to the C++ committee finalizing the C++'0x standard.-->
+<p>
+Like compiler_rt, libc++ is now <a href="DeveloperPolicy.html#license">dual
+  licensed</a> under the MIT and UIUC license, allowing it to be used more
+  permissively.
 </p>
 
 </div>



From aggarwa4 at illinois.edu  Tue Apr  5 20:01:26 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Wed, 06 Apr 2011 01:01:26 -0000
Subject: [llvm-commits] [poolalloc] r128971 -
	/poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp
Message-ID: <20110406010126.B86C32A6C12D@llvm.org>

Author: aggarwa4
Date: Tue Apr  5 20:01:26 2011
New Revision: 128971

URL: http://llvm.org/viewvc/llvm-project?rev=128971&view=rev
Log:
Added more comments.

Modified:
    poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp

Modified: poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp?rev=128971&r1=128970&r2=128971&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp Tue Apr  5 20:01:26 2011
@@ -1,3 +1,17 @@
+//===--------------- SimplifyGEP.cpp - Simplify GEPs types  ---------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Simplify GEPs with bitcasts (mostly cloned from InstCombine)
+//
+//===----------------------------------------------------------------------===//
+
+
 #define DEBUG_TYPE "simplifygep"
 
 #include "llvm/Instructions.h"
@@ -38,10 +52,26 @@
   public:
     static char ID;
     SimplifyGEP() : ModulePass(&ID) {}
+    //
+    // Method: runOnModule()
+    //
+    // Description:
+    //  Entry point for this LLVM pass.
+    //  Find all GEPs, and simplify them.
+    //
+    // Inputs:
+    //  M - A reference to the LLVM module to transform
+    //
+    // Outputs:
+    //  M - The transformed LLVM module.
+    //
+    // Return value:
+    //  true  - The module was modified.
+    //  false - The module was not modified.
+    //
     bool runOnModule(Module& M) {
-    TD = &getAnalysis<TargetData>();
+      TD = &getAnalysis<TargetData>();
       preprocess(M);
-      //bool changed = false;
       for (Module::iterator F = M.begin(); F != M.end(); ++F){
         for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {      
           for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE; I++) {
@@ -50,16 +80,26 @@
             GetElementPtrInst *GEP = cast<GetElementPtrInst>(I);
             Value *PtrOp = GEP->getOperand(0);
             Value *StrippedPtr = PtrOp->stripPointerCasts();
+            // Check if the GEP base pointer is enclosed in a cast
             if (StrippedPtr != PtrOp) {
               const PointerType *StrippedPtrTy =cast<PointerType>(StrippedPtr->getType());
               bool HasZeroPointerIndex = false;
               if (ConstantInt *C = dyn_cast<ConstantInt>(GEP->getOperand(1)))
                 HasZeroPointerIndex = C->isZero();
+              // Transform: GEP (bitcast [10 x i8]* X to [0 x i8]*), i32 0, ...
+              // into     : GEP [10 x i8]* X, i32 0, ...
+              //
+              // Likewise, transform: GEP (bitcast i8* X to [0 x i8]*), i32 0, ...
+              //           into     : GEP i8* X, ...
+              // 
+              // This occurs when the program declares an array extern like "int X[];"
               if (HasZeroPointerIndex) {
                 const PointerType *CPTy = cast<PointerType>(PtrOp->getType());
                 if (const ArrayType *CATy =
                     dyn_cast<ArrayType>(CPTy->getElementType())) {
+                  // GEP (bitcast i8* X to [0 x i8]*), i32 0, ... ?
                   if (CATy->getElementType() == StrippedPtrTy->getElementType()) {
+                    // -> GEP i8* X, ...
                     SmallVector<Value*, 8> Idx(GEP->idx_begin()+1, GEP->idx_end());
                     GetElementPtrInst *Res =
                       GetElementPtrInst::Create(StrippedPtr, Idx.begin(),
@@ -68,10 +108,16 @@
                     GEP->replaceAllUsesWith(Res);
                     continue;
                   }
-                  
+
                   if (const ArrayType *XATy =
                       dyn_cast<ArrayType>(StrippedPtrTy->getElementType())){
+                    // GEP (bitcast [10 x i8]* X to [0 x i8]*), i32 0, ... ?
                     if (CATy->getElementType() == XATy->getElementType()) {
+                      // -> GEP [10 x i8]* X, i32 0, ...
+                      // At this point, we know that the cast source type is a pointer
+                      // to an array of the same type as the destination pointer
+                      // array.  Because the array type is never stepped over (there
+                      // is a leading zero) we can fold the cast into this GEP.
                       GEP->setOperand(0, StrippedPtr);
                       continue;
                     }
@@ -90,23 +136,23 @@
                   Idx[0] = Constant::getNullValue(Type::getInt32Ty(GEP->getContext()));
                   Idx[1] = GEP->getOperand(1);
                   Value *NewGEP = GetElementPtrInst::Create(StrippedPtr, Idx,
-                                                Idx+2, GEP->getName(), GEP);
+                                                            Idx+2, GEP->getName(), GEP);
                   // V and GEP are both pointer types --> BitCast
                   GEP->replaceAllUsesWith(new BitCastInst(NewGEP, GEP->getType(), GEP->getName(), GEP));
                   continue;
                 }
-                
+
                 // Transform things like:
                 // getelementptr i8* bitcast ([100 x double]* X to i8*), i32 %tmp
                 //   (where tmp = 8*tmp2) into:
                 // getelementptr [100 x double]* %arr, i32 0, i32 %tmp2; bitcast
-                
+
                 if (TD && SrcElTy->isArrayTy() && ResElTy->isIntegerTy(8)) {
                   uint64_t ArrayEltSize =
                     TD->getTypeAllocSize(cast<ArrayType>(SrcElTy)->getElementType());
-                  
+
                   // Check to see if "tmp" is a scale by a multiple of ArrayEltSize.  We
-                 // allow either a mul, shift, or constant here.
+                  // allow either a mul, shift, or constant here.
                   Value *NewIdx = 0;
                   ConstantInt *Scale = 0;
                   if (ArrayEltSize == 1) {
@@ -129,7 +175,7 @@
                       NewIdx = Inst->getOperand(0);
                     }
                   }
-                  
+
                   // If the index will be to exactly the right offset with the scale taken
                   // out, perform the transformation. Note, we don't know whether Scale is
                   // signed or not. We'll use unsigned version of division/modulo
@@ -143,13 +189,13 @@
                                                                  false /*ZExt*/);
                       NewIdx = BinaryOperator::Create(BinaryOperator::Mul, NewIdx, C, "idxscale");
                     }
-                    
+
                     // Insert the new GEP instruction.
                     Value *Idx[2];
                     Idx[0] = Constant::getNullValue(Type::getInt32Ty(GEP->getContext()));
                     Idx[1] = NewIdx;
                     Value *NewGEP = GetElementPtrInst::Create(StrippedPtr, Idx,
-                                                Idx+2, GEP->getName(), GEP);
+                                                              Idx+2, GEP->getName(), GEP);
                     GEP->replaceAllUsesWith(new BitCastInst(NewGEP, GEP->getType(), GEP->getName(), GEP));
                     continue;
                   }
@@ -168,6 +214,9 @@
   };
 }
 
+// Pass ID variable
 char SimplifyGEP::ID = 0;
+
+// Register the pass
 static RegisterPass<SimplifyGEP>
 X("simplifygep", "Simplify GEPs");



From aggarwa4 at illinois.edu  Tue Apr  5 20:10:35 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Wed, 06 Apr 2011 01:10:35 -0000
Subject: [llvm-commits] [poolalloc] r128972 -
	/poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp
Message-ID: <20110406011035.21C8E2A6C12D@llvm.org>

Author: aggarwa4
Date: Tue Apr  5 20:10:34 2011
New Revision: 128972

URL: http://llvm.org/viewvc/llvm-project?rev=128972&view=rev
Log:
Added more comments, and renamed the pass.

Modified:
    poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp

Modified: poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp?rev=128972&r1=128971&r2=128972&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/SimplifyGEP.cpp Tue Apr  5 20:10:34 2011
@@ -12,7 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 
-#define DEBUG_TYPE "simplifygep"
+#define DEBUG_TYPE "simplify-gep"
 
 #include "llvm/Instructio