From eli.friedman at gmail.com Mon May 16 02:43:31 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 16 May 2011 00:43:31 -0700 Subject: [llvm-commits] [llvm] r131399 - in /llvm/trunk: include/llvm/Function.h lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp lib/Transforms/Scalar/TailRecursionElimination.cpp lib/VMCore/Function.cpp test/Transforms/TailCallElim/setjmp.ll In-Reply-To: <20110516030533.786E92A6C12C@llvm.org> References: <20110516030533.786E92A6C12C@llvm.org> Message-ID: On Sun, May 15, 2011 at 8:05 PM, Rafael Espindola wrote: > Author: rafael > Date: Sun May 15 22:05:33 2011 > New Revision: 131399 > > URL: http://llvm.org/viewvc/llvm-project?rev=131399&view=rev > Log: > Don't do tail calls in a function that call setjmp. The stack might be > corrupted when setjmp returns again. > > Added: > ? ?llvm/trunk/test/Transforms/TailCallElim/setjmp.ll > Modified: > ? ?llvm/trunk/include/llvm/Function.h > ? ?llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > ? ?llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp > ? ?llvm/trunk/lib/VMCore/Function.cpp > > Modified: llvm/trunk/include/llvm/Function.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Function.h?rev=131399&r1=131398&r2=131399&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Function.h (original) > +++ llvm/trunk/include/llvm/Function.h Sun May 15 22:05:33 2011 > @@ -414,6 +414,10 @@ > ? /// > ? bool hasAddressTaken(const User** = 0) const; > > + ?/// callsFunctionThatReturnsTwice - Return true if the function has a call to > + ?/// setjmp or other function that gcc recognizes as "returning twice". > + ?bool callsFunctionThatReturnsTwice() const; > + > ?private: > ? // Shadow Value::setValueSubclassData with a private forwarding method so that > ? // subclasses cannot accidentally use it. > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=131399&r1=131398&r2=131399&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Sun May 15 22:05:33 2011 > @@ -208,38 +208,6 @@ > ? MachineFunctionPass::getAnalysisUsage(AU); > ?} > > -/// FunctionCallsSetJmp - Return true if the function has a call to setjmp or > -/// other function that gcc recognizes as "returning twice". This is used to > -/// limit code-gen optimizations on the machine function. > -/// > -/// FIXME: Remove after is fixed. > -static bool FunctionCallsSetJmp(const Function *F) { > - ?const Module *M = F->getParent(); > - ?static const char *ReturnsTwiceFns[] = { > - ? ?"_setjmp", > - ? ?"setjmp", > - ? ?"sigsetjmp", > - ? ?"setjmp_syscall", > - ? ?"savectx", > - ? ?"qsetjmp", > - ? ?"vfork", > - ? ?"getcontext" > - ?}; > - > - ?for (unsigned I = 0; I < array_lengthof(ReturnsTwiceFns); ++I) > - ? ?if (const Function *Callee = M->getFunction(ReturnsTwiceFns[I])) { > - ? ? ?if (!Callee->use_empty()) > - ? ? ? ?for (Value::const_use_iterator > - ? ? ? ? ? ? ? I = Callee->use_begin(), E = Callee->use_end(); > - ? ? ? ? ? ? I != E; ++I) > - ? ? ? ? ?if (const CallInst *CI = dyn_cast(*I)) > - ? ? ? ? ? ?if (CI->getParent()->getParent() == F) > - ? ? ? ? ? ? ?return true; > - ? ?} > - > - ?return false; > -} > - > ?/// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that > ?/// may trap on it. ?In this case we have to split the edge so that the path > ?/// through the predecessor block that doesn't go to the phi block doesn't > @@ -390,7 +358,7 @@ > ? } > > ? // Determine if there is a call to setjmp in the machine function. > - ?MF->setCallsSetJmp(FunctionCallsSetJmp(&Fn)); > + ?MF->setCallsSetJmp(Fn.callsFunctionThatReturnsTwice()); > > ? // Replace forward-declared registers with the registers containing > ? // the desired value. > > Modified: llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp?rev=131399&r1=131398&r2=131399&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp (original) > +++ llvm/trunk/lib/Transforms/Scalar/TailRecursionElimination.cpp Sun May 15 22:05:33 2011 > @@ -59,6 +59,7 @@ > ?#include "llvm/Function.h" > ?#include "llvm/Instructions.h" > ?#include "llvm/IntrinsicInst.h" > +#include "llvm/Module.h" > ?#include "llvm/Pass.h" > ?#include "llvm/Analysis/CaptureTracking.h" > ?#include "llvm/Analysis/InlineCost.h" > @@ -209,10 +210,10 @@ > ? ? } > ? } > > - ?// Finally, if this function contains no non-escaping allocas, mark all calls > - ?// in the function as eligible for tail calls (there is no stack memory for > - ?// them to access). > - ?if (!FunctionContainsEscapingAllocas) > + ?// Finally, if this function contains no non-escaping allocas, or calls > + ?// setjmp, mark all calls in the function as eligible for tail calls > + ?//(there is no stack memory for them to access). > + ?if (!FunctionContainsEscapingAllocas && !F.callsFunctionThatReturnsTwice()) > ? ? for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB) > ? ? ? for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; ++I) > ? ? ? ? if (CallInst *CI = dyn_cast(I)) { > > Modified: llvm/trunk/lib/VMCore/Function.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Function.cpp?rev=131399&r1=131398&r2=131399&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/Function.cpp (original) > +++ llvm/trunk/lib/VMCore/Function.cpp Sun May 15 22:05:33 2011 > @@ -24,6 +24,7 @@ > ?#include "llvm/Support/Threading.h" > ?#include "SymbolTableListTraitsImpl.h" > ?#include "llvm/ADT/DenseMap.h" > +#include "llvm/ADT/STLExtras.h" > ?#include "llvm/ADT/StringExtras.h" > ?using namespace llvm; > > @@ -406,4 +407,36 @@ > ? return false; > ?} > > +/// callsFunctionThatReturnsTwice - Return true if the function has a call to > +/// setjmp or other function that gcc recognizes as "returning twice". > +/// > +/// FIXME: Remove after is fixed. > +/// FIXME: Is the obove FIXME valid? > +bool Function::callsFunctionThatReturnsTwice() const { > + ?const Module *M = this->getParent(); > + ?static const char *ReturnsTwiceFns[] = { > + ? ?"_setjmp", > + ? ?"setjmp", > + ? ?"sigsetjmp", > + ? ?"setjmp_syscall", > + ? ?"savectx", > + ? ?"qsetjmp", > + ? ?"vfork", > + ? ?"getcontext" > + ?}; I think CodeMetrics::analyzeBasicBlock could use this function as well? -Eli From rafael.espindola at gmail.com Mon May 16 10:48:45 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 16 May 2011 15:48:45 -0000 Subject: [llvm-commits] [llvm] r131405 - /llvm/trunk/lib/Analysis/InlineCost.cpp Message-ID: <20110516154845.D5CFB2A6C12C@llvm.org> Author: rafael Date: Mon May 16 10:48:45 2011 New Revision: 131405 URL: http://llvm.org/viewvc/llvm-project?rev=131405&view=rev Log: Extra refactoring noticed by Eli Friedman. Modified: llvm/trunk/lib/Analysis/InlineCost.cpp Modified: llvm/trunk/lib/Analysis/InlineCost.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InlineCost.cpp?rev=131405&r1=131404&r2=131405&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/InlineCost.cpp (original) +++ llvm/trunk/lib/Analysis/InlineCost.cpp Mon May 16 10:48:45 2011 @@ -66,21 +66,13 @@ ImmutableCallSite CS(cast(II)); - // If this function contains a call to setjmp or _setjmp, never inline - // it. This is a hack because we depend on the user marking their local - // variables as volatile if they are live across a setjmp call, and they - // probably won't do this in callers. if (const Function *F = CS.getCalledFunction()) { // If a function is both internal and has a single use, then it is // extremely likely to get inlined in the future (it was probably // exposed by an interleaved devirtualization pass). if (F->hasInternalLinkage() && F->hasOneUse()) ++NumInlineCandidates; - - if (F->isDeclaration() && - (F->getName() == "setjmp" || F->getName() == "_setjmp")) - callsSetJmp = true; - + // If this call is to function itself, then the function is recursive. // Inlining it into other functions is a bad idea, because this is // basically just a form of loop peeling, and our metrics aren't useful @@ -226,6 +218,13 @@ /// analyzeFunction - Fill in the current structure with information gleaned /// from the specified function. void CodeMetrics::analyzeFunction(Function *F) { + // If this function contains a call to setjmp or _setjmp, never inline + // it. This is a hack because we depend on the user marking their local + // variables as volatile if they are live across a setjmp call, and they + // probably won't do this in callers. + if (F->callsFunctionThatReturnsTwice()) + callsSetJmp = true; + // Look at the size of the callee. for (Function::const_iterator BB = F->begin(), E = F->end(); BB != E; ++BB) analyzeBasicBlock(&*BB); From rafael.espindola at gmail.com Mon May 16 11:17:21 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 16 May 2011 16:17:21 -0000 Subject: [llvm-commits] [llvm] r131406 - in /llvm/trunk: include/llvm/MC/MCELFSymbolFlags.h lib/MC/ELFObjectWriter.cpp lib/MC/MCAsmStreamer.cpp lib/MC/MCELF.cpp lib/MC/MCELFStreamer.cpp lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ELF/elf-thumbfunc.s Message-ID: <20110516161721.4AE122A6C12D@llvm.org> Author: rafael Date: Mon May 16 11:17:21 2011 New Revision: 131406 URL: http://llvm.org/viewvc/llvm-project?rev=131406&view=rev Log: sets bit 0 of the function address of thumb function in .symtab ("T is 1 if the target symbol S has type STT_FUNC and the symbol addresses a Thumb instruction ;it is 0 otherwise." from "ELF for the ARM Architecture" 4.7.1.2) Patch by Koan-Sin Tan! Added: llvm/trunk/test/MC/ELF/elf-thumbfunc.s Modified: llvm/trunk/include/llvm/MC/MCELFSymbolFlags.h llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCELF.cpp llvm/trunk/lib/MC/MCELFStreamer.cpp llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCELFSymbolFlags.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCELFSymbolFlags.h?rev=131406&r1=131405&r2=131406&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCELFSymbolFlags.h (original) +++ llvm/trunk/include/llvm/MC/MCELFSymbolFlags.h Mon May 16 11:17:21 2011 @@ -49,7 +49,8 @@ ELF_STV_Hidden = (ELF::STV_HIDDEN << ELF_STV_Shift), ELF_STV_Protected = (ELF::STV_PROTECTED << ELF_STV_Shift), - ELF_Other_Weakref = (1 << ELF_Other_Shift) + ELF_Other_Weakref = (1 << ELF_Other_Shift), + ELF_Other_ThumbFunc = (2 << ELF_Other_Shift) }; } // end namespace llvm Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=131406&r1=131405&r2=131406&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon May 16 11:17:21 2011 @@ -193,8 +193,13 @@ if (!Symbol.isInSection()) return 0; - if (Data.getFragment()) - return Layout.getSymbolOffset(&Data); + + if (Data.getFragment()) { + if (Data.getFlags() & ELF_Other_ThumbFunc) + return Layout.getSymbolOffset(&Data)+1; + else + return Layout.getSymbolOffset(&Data); + } return 0; } Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=131406&r1=131405&r2=131406&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Mon May 16 11:17:21 2011 @@ -323,7 +323,8 @@ // This needs to emit to a temporary string to get properly quoted // MCSymbols when they have spaces in them. OS << "\t.thumb_func"; - if (Func) + // Only Mach-O hasSubsectionsViaSymbols() + if (MAI.hasSubsectionsViaSymbols()) OS << '\t' << *Func; EmitEOL(); } Modified: llvm/trunk/lib/MC/MCELF.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELF.cpp?rev=131406&r1=131405&r2=131406&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELF.cpp (original) +++ llvm/trunk/lib/MC/MCELF.cpp Mon May 16 11:17:21 2011 @@ -57,13 +57,13 @@ assert(Visibility == ELF::STV_DEFAULT || Visibility == ELF::STV_INTERNAL || Visibility == ELF::STV_HIDDEN || Visibility == ELF::STV_PROTECTED); - uint32_t OtherFlags = SD.getFlags() & ~(0xf << ELF_STV_Shift); + uint32_t OtherFlags = SD.getFlags() & ~(0x3 << ELF_STV_Shift); SD.setFlags(OtherFlags | (Visibility << ELF_STV_Shift)); } unsigned MCELF::GetVisibility(MCSymbolData &SD) { unsigned Visibility = - (SD.getFlags() & (0xf << ELF_STV_Shift)) >> ELF_STV_Shift; + (SD.getFlags() & (0x3 << ELF_STV_Shift)) >> ELF_STV_Shift; assert(Visibility == ELF::STV_DEFAULT || Visibility == ELF::STV_INTERNAL || Visibility == ELF::STV_HIDDEN || Visibility == ELF::STV_PROTECTED); return Visibility; Modified: llvm/trunk/lib/MC/MCELFStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCELFStreamer.cpp?rev=131406&r1=131405&r2=131406&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCELFStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCELFStreamer.cpp Mon May 16 11:17:21 2011 @@ -66,6 +66,11 @@ void MCELFStreamer::EmitThumbFunc(MCSymbol *Func) { // FIXME: Anything needed here to flag the function as thumb? + + getAssembler().setIsThumbFunc(Func); + + MCSymbolData &SD = getAssembler().getOrCreateSymbolData(*Func); + SD.setFlags(SD.getFlags() | ELF_Other_ThumbFunc); } void MCELFStreamer::EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) { Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=131406&r1=131405&r2=131406&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Mon May 16 11:17:21 2011 @@ -274,7 +274,7 @@ void ARMAsmPrinter::EmitFunctionEntryLabel() { if (AFI->isThumbFunction()) { OutStreamer.EmitAssemblerFlag(MCAF_Code16); - OutStreamer.EmitThumbFunc(Subtarget->isTargetDarwin()? CurrentFnSym : 0); + OutStreamer.EmitThumbFunc(CurrentFnSym); } OutStreamer.EmitLabel(CurrentFnSym); Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=131406&r1=131405&r2=131406&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon May 16 11:17:21 2011 @@ -15,6 +15,7 @@ #include "llvm/MC/MCParser/MCAsmLexer.h" #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCParser/MCParsedAsmOperand.h" +#include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCExpr.h" @@ -2099,15 +2100,29 @@ /// ParseDirectiveThumbFunc /// ::= .thumbfunc symbol_name bool ARMAsmParser::ParseDirectiveThumbFunc(SMLoc L) { - const AsmToken &Tok = Parser.getTok(); - if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) - return Error(L, "unexpected token in .thumb_func directive"); - StringRef Name = Tok.getString(); - Parser.Lex(); // Consume the identifier token. + const MCAsmInfo &MAI = getParser().getStreamer().getContext().getAsmInfo(); + bool isMachO = MAI.hasSubsectionsViaSymbols(); + StringRef Name; + + // Darwin asm has function name after .thumb_func direction + // ELF doesn't + if (isMachO) { + const AsmToken &Tok = Parser.getTok(); + if (Tok.isNot(AsmToken::Identifier) && Tok.isNot(AsmToken::String)) + return Error(L, "unexpected token in .thumb_func directive"); + Name = Tok.getString(); + Parser.Lex(); // Consume the identifier token. + } + if (getLexer().isNot(AsmToken::EndOfStatement)) return Error(L, "unexpected token in directive"); Parser.Lex(); + // FIXME: assuming function name will be the line following .thumb_func + if (!isMachO) { + Name = Parser.getTok().getString(); + } + // Mark symbol as a thumb symbol. MCSymbol *Func = getParser().getContext().GetOrCreateSymbol(Name); getParser().getStreamer().EmitThumbFunc(Func); Added: llvm/trunk/test/MC/ELF/elf-thumbfunc.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/elf-thumbfunc.s?rev=131406&view=auto ============================================================================== --- llvm/trunk/test/MC/ELF/elf-thumbfunc.s (added) +++ llvm/trunk/test/MC/ELF/elf-thumbfunc.s Mon May 16 11:17:21 2011 @@ -0,0 +1,20 @@ +@@ test st_value bit 0 of thumb function +@ RUN: llvm-mc %s -triple=thumbv7-linux-gnueabi -filetype=obj -o - | \ +@ RUN: elf-dump | FileCheck %s + .syntax unified + .text + .globl foo + .align 2 + .type foo,%function + .code 16 + .thumb_func +foo: + bx lr + +@@ make sure foo is thumb function: bit 0 = 1 (st_value) + at CHECK: Symbol 0x00000004 + at CHECK-NEXT: 'st_name', 0x00000001 + at CHECK-NEXT: 'st_value', 0x00000001 + at CHECK-NEXT: 'st_size', 0x00000000 + at CHECK-NEXT: 'st_bind', 0x00000001 + at CHECK-NEXT: 'st_type', 0x00000002 From jason.w.kim.2009 at gmail.com Mon May 16 11:35:21 2011 From: jason.w.kim.2009 at gmail.com (Jason W Kim) Date: Mon, 16 May 2011 16:35:21 -0000 Subject: [llvm-commits] [llvm] r131411 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20110516163521.E1B8B2A6C12C@llvm.org> Author: jasonwkim Date: Mon May 16 11:35:21 2011 New Revision: 131411 URL: http://llvm.org/viewvc/llvm-project?rev=131411&view=rev Log: Add a FIXME reminder to remove ForceARMElfPIC switch. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=131411&r1=131410&r2=131411&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Mon May 16 11:35:21 2011 @@ -37,6 +37,10 @@ #undef DEBUG_TYPE #define DEBUG_TYPE "reloc-info" +// FIXME: This switch must be removed. Since GNU as does not +// need a command line switch for doing its wierd thing with PIC, +// LLVM should not need it either. +// -- // Emulate the wierd behavior of GNU-as for relocation types namespace llvm { cl::opt From daniel at zuster.org Mon May 16 14:18:23 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Mon, 16 May 2011 12:18:23 -0700 Subject: [llvm-commits] [patch] Don't bake build info into the host In-Reply-To: <4DC829C9.1020302@gmail.com> References: <4DC829C9.1020302@gmail.com> Message-ID: Hi Rafael, I like the spirit of the patch (making getHostTriple() make sense). This is going to imply a change in the behavior of the driver since it uses this to choose the default target, but I think this change makes sense. Do we really need getBuildTriple? I don't think there are good reasons to use it, and find the implementation in the patch confusing to read. I think we should just eliminate it if possible. - Daniel On Mon, May 9, 2011 at 10:52 AM, Rafael Avila de Espindola wrote: > While working with 32 bit build of llvm on a 64 bit host I noticed that the > 32 bit clang was unable to link any program. > > The problem was that the basic 32 bit files (like crtbegin.o) are in > different different paths on i386 and x86_64 hosts. The 32 bit clang was > assuming it was running on a 32 bit host and failing to find them. > > I tracked the problem to getHostTriple. Despite its name, it returns > information about the build too. The attached patch creates an explicit > getBuildTriple. > > With this patch the 32 bit clang can link binaries on a 64 bit host. > > Cheers, > Rafael > From nicholas at mxc.ca Mon May 16 14:29:30 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 16 May 2011 19:29:30 -0000 Subject: [llvm-commits] [llvm] r131416 - /llvm/trunk/docs/LangRef.html Message-ID: <20110516192930.9438F2A6C12C@llvm.org> Author: nicholas Date: Mon May 16 14:29:30 2011 New Revision: 131416 URL: http://llvm.org/viewvc/llvm-project?rev=131416&view=rev Log: Fix errors in this llvm ir example. Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=131416&r1=131415&r2=131416&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Mon May 16 14:29:30 2011 @@ -2446,11 +2446,11 @@ %narrowaddr = bitcast i32* @g to i16* %wideaddr = bitcast i32* @g to i64* - %trap3 = load 16* %narrowaddr ; Returns a trap value. - %trap4 = load i64* %widaddr ; Returns a trap value. + %trap3 = load i16* %narrowaddr ; Returns a trap value. + %trap4 = load i64* %wideaddr ; Returns a trap value. - %cmp = icmp i32 slt %trap, 0 ; Returns a trap value. - %br i1 %cmp, %true, %end ; Branch to either destination. + %cmp = icmp slt i32 %trap, 0 ; Returns a trap value. + br i1 %cmp, label %true, label %end ; Branch to either destination. true: volatile store i32 0, i32* @g ; This is control-dependent on %cmp, so @@ -2467,19 +2467,19 @@ ; if %cmp is true, or the store in %entry ; otherwise, so this is undefined behavior. - %br i1 %cmp, %second_true, %second_end + br i1 %cmp, label %second_true, label %second_end ; The same branch again, but this time the ; true block doesn't have side effects. second_true: ; No side effects! - br label %end + ret void second_end: volatile store i32 0, i32* @g ; This time, the instruction always depends ; on the store in %end. Also, it is ; control-equivalent to %end, so this is - ; well- defined (again, ignoring earlier + ; well-defined (again, ignoring earlier ; undefined behavior in this example). From echristo at apple.com Mon May 16 15:06:14 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 16 May 2011 13:06:14 -0700 Subject: [llvm-commits] [PATCH] ExecutionEngine: fix ErrorStr handling In-Reply-To: References: <094EDE5D-E1D8-40FE-8426-4ADCD32A416C@apple.com> Message-ID: <091BD39D-2EFA-46ED-B670-1449CB83FCBD@apple.com> On May 13, 2011, at 1:41 PM, nobled wrote: > On Wed, May 11, 2011 at 3:45 PM, Eric Christopher wrote: >> >> On May 10, 2011, at 11:35 AM, nobled wrote: >> >>>> Oops, I meant to paste this in the last message: >>>> >>>> When I tried this patch, it causes the test to fail all by itself, >>>> even though the "Engine.get() != NULL" assert doesn't trigger. It >>>> gives this output: >>>> >>>> Error building ExecutionEngine: Unable to find target for this triple >>>> (no targets are registered) >>>> >>>> Does that indicate a bug in the test? >>>> >>> >>> I found the actual bug; the ExecutionEngine code was still setting >>> ErrorStr in the case whenever using the JIT failed, even if the >>> fallback to the interpreter was successful. The attached patch fixes >>> that case, and now the first patch works fine. >>> >>> Okay to commit? >> >> Haven't looked a lot, but why not check to see if the engine is null >> and if so, print out the error string? > You're right, that's definitely better for the first patch. In the > general case, though, is EngineBuilder's current behavior of giving an > error on a successful fallback the right thing to do? I think so for now. We may want it to do any number of other things in the future. If you have ideas on how you think it should work I'm all ears :) -eric From eli.friedman at gmail.com Mon May 16 15:27:46 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 16 May 2011 20:27:46 -0000 Subject: [llvm-commits] [llvm] r131417 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp test/CodeGen/X86/fast-isel-extract.ll Message-ID: <20110516202746.8C5B82A6C12C@llvm.org> Author: efriedma Date: Mon May 16 15:27:46 2011 New Revision: 131417 URL: http://llvm.org/viewvc/llvm-project?rev=131417&view=rev Log: Basic fast-isel of extractvalue. Not too helpful on its own, given the IR clang generates for cases like this, but it should become more useful soon. Added: llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=131417&r1=131416&r2=131417&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Mon May 16 15:27:46 2011 @@ -343,6 +343,8 @@ bool SelectCast(const User *I, unsigned Opcode); + bool SelectExtractValue(const User *I); + /// HandlePHINodesInSuccessorBlocks - Handle PHI nodes in successor blocks. /// Emit code to ensure constants are copied into registers when needed. /// Remember the virtual registers that need to be added to the Machine PHI Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=131417&r1=131416&r2=131417&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon May 16 15:27:46 2011 @@ -44,6 +44,7 @@ #include "llvm/Instructions.h" #include "llvm/IntrinsicInst.h" #include "llvm/Operator.h" +#include "llvm/CodeGen/Analysis.h" #include "llvm/CodeGen/FastISel.h" #include "llvm/CodeGen/FunctionLoweringInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" @@ -839,6 +840,44 @@ } bool +FastISel::SelectExtractValue(const User *U) { + const ExtractValueInst *EVI = dyn_cast(U); + if (!U) + return false; + + // Make sure we only try to handle extracts with a legal result. + EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true); + if (!RealVT.isSimple()) + return false; + MVT VT = RealVT.getSimpleVT(); + if (!TLI.isTypeLegal(VT)) + return false; + + const Value *Op0 = EVI->getOperand(0); + const Type *AggTy = Op0->getType(); + + // Get the base result register. + unsigned ResultReg; + DenseMap::iterator I = FuncInfo.ValueMap.find(Op0); + if (I != FuncInfo.ValueMap.end()) + ResultReg = I->second; + else + ResultReg = FuncInfo.InitializeRegForValue(Op0); + + // Get the actual result register, which is an offset from the base register. + unsigned VTIndex = ComputeLinearIndex(AggTy, EVI->idx_begin(), EVI->idx_end()); + + SmallVector AggValueVTs; + ComputeValueVTs(TLI, AggTy, AggValueVTs); + + for (unsigned i = 0; i < VTIndex; i++) + ResultReg += TLI.getNumRegisters(FuncInfo.Fn->getContext(), AggValueVTs[i]); + + UpdateValueMap(EVI, ResultReg); + return true; +} + +bool FastISel::SelectOperator(const User *I, unsigned Opcode) { switch (Opcode) { case Instruction::Add: @@ -942,6 +981,9 @@ return true; } + case Instruction::ExtractValue: + return SelectExtractValue(I); + case Instruction::PHI: llvm_unreachable("FastISel shouldn't visit PHI nodes!"); Added: llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll?rev=131417&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll (added) +++ llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll Mon May 16 15:27:46 2011 @@ -0,0 +1,26 @@ +; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 | FileCheck %s + +%struct.x = type { i64, i64 } +declare %struct.x @f() + +define void @test1(i64*) nounwind ssp { + %2 = tail call %struct.x @f() nounwind + %3 = extractvalue %struct.x %2, 0 + %4 = add i64 %3, 10 + store i64 %4, i64* %0 + ret void +; CHECK: test1: +; CHECK: callq _f +; CHECK-NEXT: addq $10, %rax +} + +define void @test2(i64*) nounwind ssp { + %2 = tail call %struct.x @f() nounwind + %3 = extractvalue %struct.x %2, 1 + %4 = add i64 %3, 10 + store i64 %4, i64* %0 + ret void +; CHECK: test2: +; CHECK: callq _f +; CHECK-NEXT: addq $10, %rdx +} From eli.friedman at gmail.com Mon May 16 15:34:53 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 16 May 2011 20:34:53 -0000 Subject: [llvm-commits] [llvm] r131419 - /llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Message-ID: <20110516203453.65C562A6C12C@llvm.org> Author: efriedma Date: Mon May 16 15:34:53 2011 New Revision: 131419 URL: http://llvm.org/viewvc/llvm-project?rev=131419&view=rev Log: Fix silly typo. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=131419&r1=131418&r2=131419&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon May 16 15:34:53 2011 @@ -842,7 +842,7 @@ bool FastISel::SelectExtractValue(const User *U) { const ExtractValueInst *EVI = dyn_cast(U); - if (!U) + if (!EVI) return false; // Make sure we only try to handle extracts with a legal result. From eli.friedman at gmail.com Mon May 16 16:06:17 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 16 May 2011 21:06:17 -0000 Subject: [llvm-commits] [llvm] r131420 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-extract.ll Message-ID: <20110516210617.96BAE2A6C12C@llvm.org> Author: efriedma Date: Mon May 16 16:06:17 2011 New Revision: 131420 URL: http://llvm.org/viewvc/llvm-project?rev=131420&view=rev Log: Make fast-isel work correctly s/uadd.with.overflow intrinsics. Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=131420&r1=131419&r2=131420&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Mon May 16 16:06:17 2011 @@ -310,7 +310,7 @@ /// the CFG. void FastEmitBranch(MachineBasicBlock *MBB, DebugLoc DL); - unsigned UpdateValueMap(const Value* I, unsigned Reg); + void UpdateValueMap(const Value* I, unsigned Reg, unsigned NumRegs = 1); unsigned createResultReg(const TargetRegisterClass *RC); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=131420&r1=131419&r2=131420&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon May 16 16:06:17 2011 @@ -235,10 +235,10 @@ /// NOTE: This is only necessary because we might select a block that uses /// a value before we select the block that defines the value. It might be /// possible to fix this by selecting blocks in reverse postorder. -unsigned FastISel::UpdateValueMap(const Value *I, unsigned Reg) { +void FastISel::UpdateValueMap(const Value *I, unsigned Reg, unsigned NumRegs) { if (!isa(I)) { LocalValueMap[I] = Reg; - return Reg; + return; } unsigned &AssignedReg = FuncInfo.ValueMap[I]; @@ -247,12 +247,11 @@ AssignedReg = Reg; else if (Reg != AssignedReg) { // Arrange for uses of AssignedReg to be replaced by uses of Reg. - FuncInfo.RegFixups[AssignedReg] = Reg; + for (unsigned i = 0; i < NumRegs; i++) + FuncInfo.RegFixups[AssignedReg+i] = Reg+i; AssignedReg = Reg; } - - return AssignedReg; } std::pair FastISel::getRegForGEPIndex(const Value *Idx) { @@ -845,12 +844,13 @@ if (!EVI) return false; - // Make sure we only try to handle extracts with a legal result. + // Make sure we only try to handle extracts with a legal result. But also + // allow i1 because it's easy. EVT RealVT = TLI.getValueType(EVI->getType(), /*AllowUnknown=*/true); if (!RealVT.isSimple()) return false; MVT VT = RealVT.getSimpleVT(); - if (!TLI.isTypeLegal(VT)) + if (!TLI.isTypeLegal(VT) && VT != MVT::i1) return false; const Value *Op0 = EVI->getOperand(0); Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=131420&r1=131419&r2=131420&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon May 16 16:06:17 2011 @@ -1008,63 +1008,6 @@ FuncInfo.MBB->addSuccessor(TrueMBB); return true; } - } else if (ExtractValueInst *EI = - dyn_cast(BI->getCondition())) { - // Check to see if the branch instruction is from an "arithmetic with - // overflow" intrinsic. The main way these intrinsics are used is: - // - // %t = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) - // %sum = extractvalue { i32, i1 } %t, 0 - // %obit = extractvalue { i32, i1 } %t, 1 - // br i1 %obit, label %overflow, label %normal - // - // The %sum and %obit are converted in an ADD and a SETO/SETB before - // reaching the branch. Therefore, we search backwards through the MBB - // looking for the SETO/SETB instruction. If an instruction modifies the - // EFLAGS register before we reach the SETO/SETB instruction, then we can't - // convert the branch into a JO/JB instruction. - if (const IntrinsicInst *CI = - dyn_cast(EI->getAggregateOperand())){ - if (CI->getIntrinsicID() == Intrinsic::sadd_with_overflow || - CI->getIntrinsicID() == Intrinsic::uadd_with_overflow) { - const MachineInstr *SetMI = 0; - unsigned Reg = getRegForValue(EI); - - for (MachineBasicBlock::const_reverse_iterator - RI = FuncInfo.MBB->rbegin(), RE = FuncInfo.MBB->rend(); - RI != RE; ++RI) { - const MachineInstr &MI = *RI; - - if (MI.definesRegister(Reg)) { - if (MI.isCopy()) { - Reg = MI.getOperand(1).getReg(); - continue; - } - - SetMI = &MI; - break; - } - - const TargetInstrDesc &TID = MI.getDesc(); - if (TID.hasImplicitDefOfPhysReg(X86::EFLAGS) || - MI.hasUnmodeledSideEffects()) - break; - } - - if (SetMI) { - unsigned OpCode = SetMI->getOpcode(); - - if (OpCode == X86::SETOr || OpCode == X86::SETBr) { - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(OpCode == X86::SETOr ? X86::JO_4 : X86::JB_4)) - .addMBB(TrueMBB); - FastEmitBranch(FalseMBB, DL); - FuncInfo.MBB->addSuccessor(TrueMBB); - return true; - } - } - } - } } else if (TruncInst *TI = dyn_cast(BI->getCondition())) { // Handle things like "%cond = trunc i32 %X to i1 / br i1 %cond", which // typically happen for _Bool and C++ bools. @@ -1391,10 +1334,7 @@ // FIXME: Should fold immediates. // Replace "add with overflow" intrinsics with an "add" instruction followed - // by a seto/setc instruction. Later on, when the "extractvalue" - // instructions are encountered, we use the fact that two registers were - // created sequentially to get the correct registers for the "sum" and the - // "overflow bit". + // by a seto/setc instruction. const Function *Callee = I.getCalledFunction(); const Type *RetTy = cast(Callee->getReturnType())->getTypeAtIndex(unsigned(0)); @@ -1420,27 +1360,18 @@ else return false; - unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); + // The call to CreateRegs builds two sequential registers, to store the + // both the the returned values. + unsigned ResultReg = FuncInfo.CreateRegs(I.getType()); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg) .addReg(Reg1).addReg(Reg2); - unsigned DestReg1 = UpdateValueMap(&I, ResultReg); - - // If the add with overflow is an intra-block value then we just want to - // create temporaries for it like normal. If it is a cross-block value then - // UpdateValueMap will return the cross-block register used. Since we - // *really* want the value to be live in the register pair known by - // UpdateValueMap, we have to use DestReg1+1 as the destination register in - // the cross block case. In the non-cross-block case, we should just make - // another register for the value. - if (DestReg1 != ResultReg) - ResultReg = DestReg1+1; - else - ResultReg = createResultReg(TLI.getRegClassFor(MVT::i8)); unsigned Opc = X86::SETBr; if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow) Opc = X86::SETOr; - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg+1); + + UpdateValueMap(&I, ResultReg, 2); return true; } } Modified: llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll?rev=131420&r1=131419&r2=131420&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll Mon May 16 16:06:17 2011 @@ -1,6 +1,7 @@ ; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 | FileCheck %s %struct.x = type { i64, i64 } +%addovf = type { i32, i1 } declare %struct.x @f() define void @test1(i64*) nounwind ssp { @@ -24,3 +25,24 @@ ; CHECK: callq _f ; CHECK-NEXT: addq $10, %rdx } + +declare %addovf @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone + +define void @test3(i32 %x, i32 %y, i32* %z) { + %r = call %addovf @llvm.sadd.with.overflow.i32(i32 %x, i32 %y) + %sum = extractvalue %addovf %r, 0 + %sum3 = mul i32 %sum, 3 + %bit = extractvalue %addovf %r, 1 + br i1 %bit, label %then, label %end + +then: + store i32 %sum3, i32* %z + br label %end + +end: + ret void +; CHECK: test3 +; CHECK: addl +; CHECK: seto %al +; CHECK: testb $1, %al +} From cdavis at mines.edu Mon May 16 16:13:58 2011 From: cdavis at mines.edu (Charles Davis) Date: Mon, 16 May 2011 21:13:58 -0000 Subject: [llvm-commits] [llvm] r131421 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/MC/MCStreamer.cpp Message-ID: <20110516211358.397FE2A6C12C@llvm.org> Author: cdavis Date: Mon May 16 16:13:58 2011 New Revision: 131421 URL: http://llvm.org/viewvc/llvm-project?rev=131421&view=rev Log: Add a method I forgot in the last commit. Don't worry, this one passed self-host :). Modified: llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/MCStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=131421&r1=131420&r2=131421&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Mon May 16 16:13:58 2011 @@ -463,6 +463,7 @@ virtual void EmitWin64EHAllocStack(int64_t Size); virtual void EmitWin64EHSaveReg(int64_t Register, int64_t Offset); virtual void EmitWin64EHPushFrame(bool Code); + virtual void EmitWin64EHEndProlog(void); /// EmitInstruction - Emit the given @p Instruction into the current /// section. Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=131421&r1=131420&r2=131421&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Mon May 16 16:13:58 2011 @@ -346,6 +346,12 @@ abort(); } +void MCStreamer::EmitWin64EHEndProlog(void) +{ + errs() << "Not implemented yet\n"; + abort(); +} + void MCStreamer::EmitFnStart() { errs() << "Not implemented yet\n"; abort(); From cdavis at mymail.mines.edu Mon May 16 16:21:48 2011 From: cdavis at mymail.mines.edu (Charles Davis) Date: Mon, 16 May 2011 15:21:48 -0600 Subject: [llvm-commits] [PATCH] Implement Win64 EH MCStreamer methods for Assembly Printing Message-ID: <4DD1956C.3090406@mymail.mines.edu> Hi, This patch implements the Win64 EH MCStreamer methods I just added for MCAsmStreamer. Note that GAS doesn't have any directives like this yet, so I've taken license with their names. OK to commit? Chip -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: w64-eh-asm-streamer.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110516/f4d2d293/attachment.pl From dpatel at apple.com Mon May 16 16:24:06 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 16 May 2011 21:24:06 -0000 Subject: [llvm-commits] [llvm] r131422 - in /llvm/trunk/lib: CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Transforms/Utils/Local.cpp Message-ID: <20110516212406.2FB0B2A6C12C@llvm.org> Author: dpatel Date: Mon May 16 16:24:05 2011 New Revision: 131422 URL: http://llvm.org/viewvc/llvm-project?rev=131422&view=rev Log: Preserve debug info for unused zero extended boolean argument. Radar 9422775. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/Transforms/Utils/Local.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=131422&r1=131421&r2=131422&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon May 16 16:24:05 2011 @@ -4026,6 +4026,24 @@ return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); } +// getTruncatedArgReg - Find underlying register used for an truncated +// argument. +static unsigned getTruncatedArgReg(const SDValue &N) { + if (N.getOpcode() != ISD::TRUNCATE) + return 0; + + const SDValue &Ext = N.getOperand(0); + if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ + const SDValue &CFR = Ext.getOperand(0); + if (CFR.getOpcode() == ISD::CopyFromReg) + return cast(CFR.getOperand(1))->getReg(); + else + if (CFR.getOpcode() == ISD::TRUNCATE) + return getTruncatedArgReg(CFR); + } + return 0; +} + /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function /// argument, create the corresponding DBG_VALUE machine instruction for it now. /// At the end of instruction selection, they will be inserted to the entry BB. @@ -4057,9 +4075,12 @@ Reg = 0; } - if (N.getNode() && N.getOpcode() == ISD::CopyFromReg) { - Reg = cast(N.getOperand(1))->getReg(); - if (TargetRegisterInfo::isVirtualRegister(Reg)) { + if (N.getNode()) { + if (N.getOpcode() == ISD::CopyFromReg) + Reg = cast(N.getOperand(1))->getReg(); + else + Reg = getTruncatedArgReg(N); + if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { MachineRegisterInfo &RegInfo = MF.getRegInfo(); unsigned PR = RegInfo.getLiveInPhysReg(Reg); if (PR) @@ -4221,9 +4242,9 @@ SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 0, dl, SDNodeOrder); else { - // Can't do anything with other non-AI cases yet. This might be a - // parameter of a callee function that got inlined, for example. - DEBUG(dbgs() << "Dropping debug info for " << DI); + // Address is an argument, so try to emit its dbg value using + // virtual register info from the FuncInfo.ValueMap. + EmitFuncArgumentDbgValue(Address, Variable, 0, N); return 0; } } else if (AI) Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=131422&r1=131421&r2=131422&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Mon May 16 16:24:05 2011 @@ -785,10 +785,19 @@ if (!DIVar.Verify()) return false; - Instruction *DbgVal = - Builder.insertDbgValueIntrinsic(SI->getOperand(0), 0, - DIVar, SI); - + Instruction *DbgVal = NULL; + // If an argument is zero extended then use argument directly. The ZExt + // may be zapped by an optimization pass in future. + Argument *ExtendedArg = NULL; + if (ZExtInst *ZExt = dyn_cast(SI->getOperand(0))) + ExtendedArg = dyn_cast(ZExt->getOperand(0)); + if (SExtInst *SExt = dyn_cast(SI->getOperand(0))) + ExtendedArg = dyn_cast(SExt->getOperand(0)); + if (ExtendedArg) + DbgVal = Builder.insertDbgValueIntrinsic(ExtendedArg, 0, DIVar, SI); + else + DbgVal = Builder.insertDbgValueIntrinsic(SI->getOperand(0), 0, DIVar, SI); + // Propagate any debug metadata from the store onto the dbg.value. DebugLoc SIDL = SI->getDebugLoc(); if (!SIDL.isUnknown()) From dpatel at apple.com Mon May 16 16:25:49 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 16 May 2011 21:25:49 -0000 Subject: [llvm-commits] [debuginfo-tests] r131423 - /debuginfo-tests/trunk/unused-boolean-arg.ll Message-ID: <20110516212549.975762A6C12C@llvm.org> Author: dpatel Date: Mon May 16 16:25:49 2011 New Revision: 131423 URL: http://llvm.org/viewvc/llvm-project?rev=131423&view=rev Log: Test case for r131422. Added: debuginfo-tests/trunk/unused-boolean-arg.ll Added: debuginfo-tests/trunk/unused-boolean-arg.ll URL: http://llvm.org/viewvc/llvm-project/debuginfo-tests/trunk/unused-boolean-arg.ll?rev=131423&view=auto ============================================================================== --- debuginfo-tests/trunk/unused-boolean-arg.ll (added) +++ debuginfo-tests/trunk/unused-boolean-arg.ll Mon May 16 16:25:49 2011 @@ -0,0 +1,82 @@ +; This test checks debug info of unused, zero extended argument. +; RUN: %clang -arch x86_64 -mllvm -fast-isel=false %s -c -o %t.o +; RUN: %clang -arch x86_64 %t.o -o %t.out +; RUN: %test_debuginfo %s %t.out +; Radar 9422775 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.7" + +%class.aClass = type { float } + +; DEBUGGER: break aClass::setValues +; DEBUGGER: r +; DEBUGGER: p Filter +; CHECK: true + +define void @_ZN6aClass9setValuesEibf(%class.aClass* nocapture %this, i32 %ch, i1 zeroext %Filter, float %a1) nounwind noinline ssp align 2 { +entry: + tail call void @llvm.dbg.value(metadata !{%class.aClass* %this}, i64 0, metadata !19), !dbg !25 + tail call void @llvm.dbg.value(metadata !{i32 %ch}, i64 0, metadata !20), !dbg !26 + tail call void @llvm.dbg.value(metadata !{i1 %Filter}, i64 0, metadata !21), !dbg !27 + tail call void @llvm.dbg.value(metadata !{float %a1}, i64 0, metadata !22), !dbg !28 + %m = getelementptr inbounds %class.aClass* %this, i64 0, i32 0, !dbg !29 + store float %a1, float* %m, align 4, !dbg !29, !tbaa !31 + ret void, !dbg !34 +} + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +define i32 @main() nounwind ssp { +entry: + %a = alloca %class.aClass, align 4 + call void @llvm.dbg.declare(metadata !{%class.aClass* %a}, metadata !23), !dbg !35 + call void @_ZN6aClass9setValuesEibf(%class.aClass* %a, i32 undef, i1 zeroext 1, float 1.000000e+00), !dbg !36 + ret i32 0, !dbg !37 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone + +!llvm.dbg.cu = !{!0} +!llvm.dbg.sp = !{!1, !12, !16} +!llvm.dbg.lv._ZN6aClass9setValuesEibf = !{!19, !20, !21, !22} +!llvm.dbg.lv.main = !{!23} + +!0 = metadata !{i32 589841, i32 0, i32 4, metadata !"two.cpp", metadata !"/private/tmp/inc", metadata !"clang version 3.0 (trunk 131411)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"setValues", metadata !"setValues", metadata !"_ZN6aClass9setValuesEibf", metadata !3, i32 6, metadata !7, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 true, null, null} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 589826, metadata !0, metadata !"aClass", metadata !3, i32 2, i64 32, i64 32, i32 0, i32 0, null, metadata !4, i32 0, null, null} ; [ DW_TAG_class_type ] +!3 = metadata !{i32 589865, metadata !"./one.h", metadata !"/private/tmp/inc", metadata !0} ; [ DW_TAG_file_type ] +!4 = metadata !{metadata !5, metadata !1} +!5 = metadata !{i32 589837, metadata !3, metadata !"m", metadata !3, i32 4, i64 32, i64 32, i64 0, i32 1, metadata !6} ; [ DW_TAG_member ] +!6 = metadata !{i32 589860, metadata !0, metadata !"float", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 4} ; [ DW_TAG_base_type ] +!7 = metadata !{i32 589845, metadata !3, metadata !"", metadata !3, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !8, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!8 = metadata !{null, metadata !9, metadata !10, metadata !11, metadata !6} +!9 = metadata !{i32 589839, metadata !0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !2} ; [ DW_TAG_pointer_type ] +!10 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!11 = metadata !{i32 589860, metadata !0, metadata !"bool", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] +!12 = metadata !{i32 589870, i32 0, metadata !13, metadata !"setValues", metadata !"setValues", metadata !"_ZN6aClass9setValuesEibf", metadata !13, i32 4, metadata !14, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, void (%class.aClass*, i32, i1, float)* @_ZN6aClass9setValuesEibf, null, metadata !1} ; [ DW_TAG_subprogram ] +!13 = metadata !{i32 589865, metadata !"two.cpp", metadata !"/private/tmp/inc", metadata !0} ; [ DW_TAG_file_type ] +!14 = metadata !{i32 589845, metadata !13, metadata !"", metadata !13, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !15, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!15 = metadata !{null} +!16 = metadata !{i32 589870, i32 0, metadata !13, metadata !"main", metadata !"main", metadata !"", metadata !13, i32 9, metadata !17, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 ()* @main, null, null} ; [ DW_TAG_subprogram ] +!17 = metadata !{i32 589845, metadata !13, metadata !"", metadata !13, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !18, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!18 = metadata !{metadata !10} +!19 = metadata !{i32 590081, metadata !12, metadata !"this", metadata !13, i32 16777219, metadata !9, i32 64} ; [ DW_TAG_arg_variable ] +!20 = metadata !{i32 590081, metadata !12, metadata !"ch", metadata !13, i32 33554435, metadata !10, i32 0} ; [ DW_TAG_arg_variable ] +!21 = metadata !{i32 590081, metadata !12, metadata !"Filter", metadata !13, i32 50331651, metadata !11, i32 0} ; [ DW_TAG_arg_variable ] +!22 = metadata !{i32 590081, metadata !12, metadata !"a1", metadata !13, i32 67108867, metadata !6, i32 0} ; [ DW_TAG_arg_variable ] +!23 = metadata !{i32 590080, metadata !24, metadata !"a", metadata !13, i32 10, metadata !2, i32 0} ; [ DW_TAG_auto_variable ] +!24 = metadata !{i32 589835, metadata !16, i32 9, i32 1, metadata !13, i32 1} ; [ DW_TAG_lexical_block ] +!25 = metadata !{i32 3, i32 40, metadata !12, null} +!26 = metadata !{i32 3, i32 54, metadata !12, null} +!27 = metadata !{i32 3, i32 63, metadata !12, null} +!28 = metadata !{i32 3, i32 77, metadata !12, null} +!29 = metadata !{i32 5, i32 2, metadata !30, null} +!30 = metadata !{i32 589835, metadata !12, i32 4, i32 1, metadata !13, i32 0} ; [ DW_TAG_lexical_block ] +!31 = metadata !{metadata !"float", metadata !32} +!32 = metadata !{metadata !"omnipotent char", metadata !33} +!33 = metadata !{metadata !"Simple C/C++ TBAA", null} +!34 = metadata !{i32 6, i32 1, metadata !30, null} +!35 = metadata !{i32 10, i32 11, metadata !24, null} +!36 = metadata !{i32 11, i32 4, metadata !24, null} +!37 = metadata !{i32 12, i32 4, metadata !24, null} From eli.friedman at gmail.com Mon May 16 16:28:22 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 16 May 2011 21:28:22 -0000 Subject: [llvm-commits] [llvm] r131424 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/ret-mmx.ll Message-ID: <20110516212822.61AAE2A6C12C@llvm.org> Author: efriedma Date: Mon May 16 16:28:22 2011 New Revision: 131424 URL: http://llvm.org/viewvc/llvm-project?rev=131424&view=rev Log: Remove dead code. Fix associated test to use FileCheck. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/ret-mmx.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=131424&r1=131423&r2=131424&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon May 16 16:28:22 2011 @@ -1527,20 +1527,6 @@ Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, // This truncation won't change the value. DAG.getIntPtrConstant(1)); - } else if (Is64Bit && CopyVT.isVector() && CopyVT.getSizeInBits() == 64) { - // For x86-64, MMX values are returned in XMM0 / XMM1 except for v1i64. - if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { - Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), - MVT::v2i64, InFlag).getValue(1); - Val = Chain.getValue(0); - Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i64, - Val, DAG.getConstant(0, MVT::i64)); - } else { - Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), - MVT::i64, InFlag).getValue(1); - Val = Chain.getValue(0); - } - Val = DAG.getNode(ISD::BITCAST, dl, CopyVT, Val); } else { Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), CopyVT, InFlag).getValue(1); Modified: llvm/trunk/test/CodeGen/X86/ret-mmx.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ret-mmx.ll?rev=131424&r1=131423&r2=131424&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/ret-mmx.ll (original) +++ llvm/trunk/test/CodeGen/X86/ret-mmx.ll Mon May 16 16:28:22 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 +; RUN: llc < %s -mtriple=x86_64-apple-darwin11 -mattr=+mmx,+sse2 | FileCheck %s ; rdar://6602459 @g_v1di = external global <1 x i64> @@ -8,19 +8,32 @@ %call = call <1 x i64> @return_v1di() ; <<1 x i64>> [#uses=0] store <1 x i64> %call, <1 x i64>* @g_v1di ret void +; CHECK: t1: +; CHECK: callq +; CHECK-NEXT: movq _g_v1di +; CHECK-NEXT: movq %rax, } declare <1 x i64> @return_v1di() define <1 x i64> @t2() nounwind { ret <1 x i64> +; CHECK: t2: +; CHECK: movl $1 +; CHECK-NEXT: ret } define <2 x i32> @t3() nounwind { ret <2 x i32> +; CHECK: t3: +; CHECK: movl $1 +; CHECK: movd {{.*}}, %xmm0 } define double @t4() nounwind { ret double bitcast (<2 x i32> to double) +; CHECK: t4: +; CHECK: movl $1 +; CHECK: movd {{.*}}, %xmm0 } From grosbach at apple.com Mon May 16 16:51:07 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 May 2011 21:51:07 -0000 Subject: [llvm-commits] [llvm] r131426 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <20110516215107.B6EB82A6C12C@llvm.org> Author: grosbach Date: Mon May 16 16:51:07 2011 New Revision: 131426 URL: http://llvm.org/viewvc/llvm-project?rev=131426&view=rev Log: Track how many insns fast-isel successfully selects as well as how many it misses. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=131426&r1=131425&r2=131426&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon May 16 16:51:07 2011 @@ -55,6 +55,7 @@ using namespace llvm; STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); +STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); @@ -927,6 +928,7 @@ // Try to select the instruction with FastISel. if (FastIS->SelectInstruction(Inst)) { + ++NumFastIselSuccess; // If fast isel succeeded, skip over all the folded instructions, and // then see if there is a load right before the selected instructions. // Try to fold the load if so. From dpatel at apple.com Mon May 16 17:05:03 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 16 May 2011 22:05:03 -0000 Subject: [llvm-commits] [llvm] r131427 - /llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Message-ID: <20110516220503.618212A6C12C@llvm.org> Author: dpatel Date: Mon May 16 17:05:03 2011 New Revision: 131427 URL: http://llvm.org/viewvc/llvm-project?rev=131427&view=rev Log: There is no need to force DebugLoc on a PHI at this point. Modified: llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Modified: llvm/trunk/lib/Transforms/Utils/LCSSA.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LCSSA.cpp?rev=131427&r1=131426&r2=131427&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/LCSSA.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/LCSSA.cpp Mon May 16 17:05:03 2011 @@ -36,7 +36,6 @@ #include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/LoopPass.h" #include "llvm/Analysis/ScalarEvolution.h" -#include "llvm/Transforms/Utils/BasicBlockUtils.h" #include "llvm/Transforms/Utils/SSAUpdater.h" #include "llvm/ADT/Statistic.h" #include "llvm/ADT/STLExtras.h" @@ -227,7 +226,6 @@ PredCache.GetNumPreds(ExitBB), Inst->getName()+".lcssa", ExitBB->begin()); - PN->setDebugLoc(GetFirstDebugLocInBasicBlock(ExitBB)); // Add inputs from inside the loop for this PHI. for (BasicBlock **PI = PredCache.GetPreds(ExitBB); *PI; ++PI) { From gohman at apple.com Mon May 16 17:09:53 2011 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 May 2011 22:09:53 -0000 Subject: [llvm-commits] [llvm] r131428 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20110516220953.B52A62A6C12C@llvm.org> Author: djg Date: Mon May 16 17:09:53 2011 New Revision: 131428 URL: http://llvm.org/viewvc/llvm-project?rev=131428&view=rev Log: Fix whitespace and 80-column violations. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=131428&r1=131427&r2=131428&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon May 16 17:09:53 2011 @@ -1094,8 +1094,9 @@ { SDNode *myCALLSEQ_BEGIN = FindCallStartFromCallEnd(Node); - // If the CALLSEQ_START node hasn't been legalized first, legalize it. This - // will cause this node to be legalized as well as handling libcalls right. + // If the CALLSEQ_START node hasn't been legalized first, legalize it. + // This will cause this node to be legalized as well as handling libcalls + // right. if (getLastCALLSEQ().getNode() != Node) { LegalizeOp(SDValue(myCALLSEQ_BEGIN, 0)); DenseMap::iterator I = LegalizedNodes.find(Op); @@ -2060,14 +2061,14 @@ return CallInfo.first; } -/// ExpandLibCall - Generate a libcall taking the given operands as arguments +/// ExpandLibCall - Generate a libcall taking the given operands as arguments /// and returning a result of type RetVT. SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, unsigned NumOps, bool isSigned, DebugLoc dl) { TargetLowering::ArgListTy Args; Args.reserve(NumOps); - + TargetLowering::ArgListEntry Entry; for (unsigned i = 0; i != NumOps; ++i) { Entry.Node = Ops[i]; @@ -2078,14 +2079,14 @@ } SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), TLI.getPointerTy()); - + const Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); std::pair CallInfo = TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, false, 0, TLI.getLibcallCallingConv(LC), false, /*isReturnValueUsed=*/true, Callee, Args, DAG, dl); - + // Legalize the call sequence, starting with the chain. This will advance // the LastCALLSEQ_END to the legalized version of the CALLSEQ_END node that // was added by LowerCallTo (guaranteeing proper serialization of calls). @@ -3433,8 +3434,8 @@ else if (WideVT == MVT::i128) LC = RTLIB::MUL_I128; assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!"); - - // The high part is obtained by SRA'ing all but one of the bits of low + + // The high part is obtained by SRA'ing all but one of the bits of low // part. unsigned LoSize = VT.getSizeInBits(); SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS, @@ -3453,7 +3454,7 @@ TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret, DAG.getIntPtrConstant(1)); } - + if (isSigned) { Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, TLI.getShiftAmountTy(BottomHalf.getValueType())); @@ -3756,4 +3757,3 @@ /// SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); } - From gohman at apple.com Mon May 16 17:14:51 2011 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 May 2011 22:14:51 -0000 Subject: [llvm-commits] [llvm] r131429 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20110516221451.25CB12A6C12C@llvm.org> Author: djg Date: Mon May 16 17:14:50 2011 New Revision: 131429 URL: http://llvm.org/viewvc/llvm-project?rev=131429&view=rev Log: Trim #includes. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=131429&r1=131428&r2=131429&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon May 16 17:14:50 2011 @@ -14,23 +14,16 @@ #include "llvm/Analysis/DebugInfo.h" #include "llvm/CodeGen/Analysis.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineJumpTableInfo.h" -#include "llvm/CodeGen/MachineModuleInfo.h" -#include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/Target/TargetFrameLowering.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetOptions.h" #include "llvm/CallingConv.h" #include "llvm/Constants.h" #include "llvm/DerivedTypes.h" -#include "llvm/Function.h" -#include "llvm/GlobalVariable.h" #include "llvm/LLVMContext.h" -#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" From gohman at apple.com Mon May 16 17:19:55 2011 From: gohman at apple.com (Dan Gohman) Date: Mon, 16 May 2011 22:19:55 -0000 Subject: [llvm-commits] [llvm] r131430 - in /llvm/trunk: include/llvm/CodeGen/SelectionDAG.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <20110516221955.235052A6C12C@llvm.org> Author: djg Date: Mon May 16 17:19:54 2011 New Revision: 131430 URL: http://llvm.org/viewvc/llvm-project?rev=131430&view=rev Log: Delete unused variables. Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/include/llvm/CodeGen/SelectionDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/SelectionDAG.h?rev=131430&r1=131429&r2=131430&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/SelectionDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/SelectionDAG.h Mon May 16 17:19:54 2011 @@ -284,7 +284,7 @@ /// /// Note that this is an involved process that may invalidate pointers into /// the graph. - void Legalize(CodeGenOpt::Level OptLevel); + void Legalize(); /// LegalizeVectors - This transforms the SelectionDAG into a SelectionDAG /// that only uses vector math operations supported by the target. This is Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=131430&r1=131429&r2=131430&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Mon May 16 17:19:54 2011 @@ -50,7 +50,6 @@ const TargetMachine &TM; const TargetLowering &TLI; SelectionDAG &DAG; - CodeGenOpt::Level OptLevel; // Libcall insertion helpers. @@ -86,7 +85,7 @@ } public: - SelectionDAGLegalize(SelectionDAG &DAG, CodeGenOpt::Level ol); + explicit SelectionDAGLegalize(SelectionDAG &DAG); /// getTypeAction - Return how we should legalize values of this type, either /// it is already legal or we need to expand it into multiple registers of @@ -219,10 +218,9 @@ return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); } -SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag, - CodeGenOpt::Level ol) +SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) : TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), - DAG(dag), OptLevel(ol), + DAG(dag), ValueTypeActions(TLI.getValueTypeActions()) { assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE && "Too many value types for ValueTypeActions to hold!"); @@ -3745,8 +3743,8 @@ // SelectionDAG::Legalize - This is the entry point for the file. // -void SelectionDAG::Legalize(CodeGenOpt::Level OptLevel) { +void SelectionDAG::Legalize() { /// run - This is the main entry point to this class. /// - SelectionDAGLegalize(*this, OptLevel).LegalizeDAG(); + SelectionDAGLegalize(*this).LegalizeDAG(); } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=131430&r1=131429&r2=131430&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon May 16 17:19:54 2011 @@ -537,7 +537,7 @@ { NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); - CurDAG->Legalize(OptLevel); + CurDAG->Legalize(); } DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber From grosbach at apple.com Mon May 16 17:24:07 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 16 May 2011 22:24:07 -0000 Subject: [llvm-commits] [llvm] r131431 - /llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Message-ID: <20110516222407.B7DDA2A6C12C@llvm.org> Author: grosbach Date: Mon May 16 17:24:07 2011 New Revision: 131431 URL: http://llvm.org/viewvc/llvm-project?rev=131431&view=rev Log: Kill some dead code. Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=131431&r1=131430&r2=131431&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Mon May 16 17:24:07 2011 @@ -71,12 +71,10 @@ } Base; int Offset; - unsigned Scale; - unsigned PlusReg; // Innocuous defaults for our address. Address() - : BaseType(RegBase), Offset(0), Scale(0), PlusReg(0) { + : BaseType(RegBase), Offset(0) { Base.Reg = 0; } } Address; From gkistanova at gmail.com Mon May 16 17:50:03 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 16 May 2011 15:50:03 -0700 Subject: [llvm-commits] [llvm] r131241 - in /llvm/trunk: lib/CodeGen/BranchFolding.cpp test/CodeGen/X86/hoist-common.ll In-Reply-To: <20110512203002.1A71B2A6C12C@llvm.org> References: <20110512203002.1A71B2A6C12C@llvm.org> Message-ID: Hello, Test llvm/trunk/test/CodeGen/X86/hoist-common.ll fails on two windows machines: http://google1.osuosl.org:8011/builders/llvm-gcc-native-mingw32/builds/1665 http://google1.osuosl.org:8011/builders/llvm-gcc-native-mingw32-win7/builds/1921 Please see attached hoist-common.ll.out. Thanks Galina On Thu, May 12, 2011 at 1:30 PM, Evan Cheng wrote: > Author: evancheng > Date: Thu May 12 15:30:01 2011 > New Revision: 131241 > > URL: http://llvm.org/viewvc/llvm-project?rev=131241&view=rev > Log: > Re-enable branchfolding common code hoisting optimization. Fixed a liveness test bug and also taught it to update liveins. > > Added: > ? ?llvm/trunk/test/CodeGen/X86/hoist-common.ll > Modified: > ? ?llvm/trunk/lib/CodeGen/BranchFolding.cpp > > Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=131241&r1=131240&r2=131241&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) > +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Thu May 12 15:30:01 2011 > @@ -1354,10 +1354,6 @@ > ?/// NOTE: This optimization does not update live-in information so it must be > ?/// run after all passes that require correct liveness information. > ?bool BranchFolder::HoistCommonCode(MachineFunction &MF) { > -#if 1 > - ?// FIXME: Temporarily disabled. > - ?return false; > -#endif > ? bool MadeChange = false; > ? for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ) { > ? ? MachineBasicBlock *MBB = I++; > @@ -1472,10 +1468,10 @@ > ? ? ? ? Uses.erase(Reg); > ? ? ? ? for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) > ? ? ? ? ? Uses.erase(*SR); // Use getSubRegisters to be conservative > - ? ? ? ?Defs.insert(Reg); > - ? ? ? ?for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) > - ? ? ? ? ?Defs.insert(*AS); > ? ? ? } > + ? ? ?Defs.insert(Reg); > + ? ? ?for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) > + ? ? ? ?Defs.insert(*AS); > ? ? } > ? } > > @@ -1511,7 +1507,8 @@ > ? ? return false; > > ? bool HasDups = false; > - ?SmallSet LocalDefs; > + ?SmallVector LocalDefs; > + ?SmallSet LocalDefsSet; > ? MachineBasicBlock::iterator TIB = TBB->begin(); > ? MachineBasicBlock::iterator FIB = FBB->begin(); > ? MachineBasicBlock::iterator TIE = TBB->end(); > @@ -1568,11 +1565,7 @@ > ? ? ? ? ? IsSafe = false; > ? ? ? ? ? break; > ? ? ? ? } > - > - ? ? ? ?LocalDefs.insert(Reg); > - ? ? ? ?for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) > - ? ? ? ? ?LocalDefs.insert(*SR); > - ? ? ?} else if (!LocalDefs.count(Reg)) { > + ? ? ?} else if (!LocalDefsSet.count(Reg)) { > ? ? ? ? if (Defs.count(Reg)) { > ? ? ? ? ? // Use is defined by the instruction at the point of insertion. > ? ? ? ? ? IsSafe = false; > @@ -1587,6 +1580,28 @@ > ? ? if (!TIB->isSafeToMove(TII, 0, DontMoveAcrossStore)) > ? ? ? break; > > + ? ?// Track local defs so we can update liveins. > + ? ?for (unsigned i = 0, e = TIB->getNumOperands(); i != e; ++i) { > + ? ? ?MachineOperand &MO = TIB->getOperand(i); > + ? ? ?if (!MO.isReg()) > + ? ? ? ?continue; > + ? ? ?unsigned Reg = MO.getReg(); > + ? ? ?if (!Reg) > + ? ? ? ?continue; > + ? ? ?if (MO.isDef()) { > + ? ? ? ?if (!MO.isDead()) { > + ? ? ? ? ?LocalDefs.push_back(Reg); > + ? ? ? ? ?LocalDefsSet.insert(Reg); > + ? ? ? ? ?for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) > + ? ? ? ? ? ?LocalDefsSet.insert(*SR); > + ? ? ? ?} > + ? ? ?} else if (MO.isKill() && LocalDefsSet.count(Reg)) { > + ? ? ? ?LocalDefsSet.erase(Reg); > + ? ? ? ?for (const unsigned *SR = TRI->getSubRegisters(Reg); *SR; ++SR) > + ? ? ? ? ?LocalDefsSet.erase(*SR); > + ? ? ?} > + ? ?} > + > ? ? HasDups = true;; > ? ? ++TIB; > ? ? ++FIB; > @@ -1597,6 +1612,16 @@ > > ? MBB->splice(Loc, TBB, TBB->begin(), TIB); > ? FBB->erase(FBB->begin(), FIB); > + > + ?// Update livein's. > + ?for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) { > + ? ?unsigned Def = LocalDefs[i]; > + ? ?if (LocalDefsSet.count(Def)) { > + ? ? ?TBB->addLiveIn(Def); > + ? ? ?FBB->addLiveIn(Def); > + ? ?} > + ?} > + > ? ++NumHoist; > ? return true; > ?} > > Added: llvm/trunk/test/CodeGen/X86/hoist-common.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hoist-common.ll?rev=131241&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/hoist-common.ll (added) > +++ llvm/trunk/test/CodeGen/X86/hoist-common.ll Thu May 12 15:30:01 2011 > @@ -0,0 +1,28 @@ > +; RUN: llc < %s -march=x86-64 ?| FileCheck %s > + > +; Common "xorb al, al" instruction in the two successor blocks should be > +; moved to the entry block above the test + je. > + > +; rdar://9145558 > + > +define zeroext i1 @t(i32 %c) nounwind ssp { > +entry: > +; CHECK: t: > +; CHECK: xorb %al, %al > +; CHECK: test > +; CHECK: je > + ?%tobool = icmp eq i32 %c, 0 > + ?br i1 %tobool, label %return, label %if.then > + > +if.then: > +; CHECK: callq > + ?%call = tail call zeroext i1 (...)* @foo() nounwind > + ?br label %return > + > +return: > +; CHECK: ret > + ?%retval.0 = phi i1 [ %call, %if.then ], [ false, %entry ] > + ?ret i1 %retval.0 > +} > + > +declare zeroext i1 @foo(...) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- .def t; .scl 2; .type 32; .endef .text .globl t .align 16, 0x90 t: # @t # BB#0: # %entry subq $40, %rsp testl %ecx, %ecx jne .LBB0_2 # BB#1: xorb %al, %al addq $40, %rsp ret .LBB0_2: # %if.then callq foo addq $40, %rsp ret From stoklund at 2pi.dk Mon May 16 18:50:05 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 16 May 2011 23:50:05 -0000 Subject: [llvm-commits] [llvm] r131436 - in /llvm/trunk: include/llvm/CodeGen/LiveInterval.h lib/CodeGen/CalcSpillWeights.cpp test/CodeGen/ARM/vldlane.ll test/CodeGen/X86/abi-isel.ll Message-ID: <20110516235005.5F4D82A6C12C@llvm.org> Author: stoklund Date: Mon May 16 18:50:05 2011 New Revision: 131436 URL: http://llvm.org/viewvc/llvm-project?rev=131436&view=rev Log: Teach LiveInterval::isZeroLength about null SlotIndexes. When instructions are deleted, they leave tombstone SlotIndex entries. The isZeroLength method should ignore these null indexes. This causes RABasic to sometimes spill a callee-saved register in the abi-isel.ll test, so don't run that test with -regalloc=basic. Prioritizing register allocation according to spill weight can cause more registers to be used. Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp llvm/trunk/test/CodeGen/ARM/vldlane.ll llvm/trunk/test/CodeGen/X86/abi-isel.ll Modified: llvm/trunk/include/llvm/CodeGen/LiveInterval.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/LiveInterval.h?rev=131436&r1=131435&r2=131436&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/LiveInterval.h (original) +++ llvm/trunk/include/llvm/CodeGen/LiveInterval.h Mon May 16 18:50:05 2011 @@ -492,9 +492,10 @@ /// Returns true if the live interval is zero length, i.e. no live ranges /// span instructions. It doesn't pay to spill such an interval. - bool isZeroLength() const { + bool isZeroLength(SlotIndexes *Indexes) const { for (const_iterator i = begin(), e = end(); i != e; ++i) - if (i->end.getPrevIndex() > i->start) + if (Indexes->getNextNonNullIndex(i->start).getBaseIndex() < + i->end.getBaseIndex()) return false; return true; } Modified: llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp?rev=131436&r1=131435&r2=131436&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp (original) +++ llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp Mon May 16 18:50:05 2011 @@ -165,7 +165,7 @@ return; // Mark li as unspillable if all live ranges are tiny. - if (li.isZeroLength()) { + if (li.isZeroLength(LIS.getSlotIndexes())) { li.markNotSpillable(); return; } Modified: llvm/trunk/test/CodeGen/ARM/vldlane.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vldlane.ll?rev=131436&r1=131435&r2=131436&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vldlane.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vldlane.ll Mon May 16 18:50:05 2011 @@ -222,7 +222,7 @@ define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind { ;CHECK: vld3lanei16: ;Check the (default) alignment value. VLD3 does not support alignment. -;CHECK: vld3.16 {d16[1], d17[1], d18[1]}, [{{r[0-9]+}}] +;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <4 x i16>* %B %tmp2 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 1, i32 8) @@ -265,7 +265,7 @@ define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind { ;CHECK: vld3laneQi16: ;Check the (default) alignment value. VLD3 does not support alignment. -;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [{{r[0-9]+}}] +;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}] %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B %tmp2 = call %struct.__neon_int16x8x3_t @llvm.arm.neon.vld3lane.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1, i32 8) @@ -280,7 +280,7 @@ ;Check for a post-increment updating load with register increment. define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind { ;CHECK: vld3laneQi16_update: -;CHECK: vld3.16 {d16[1], d18[1], d20[1]}, [{{r[0-9]+}}], {{r[0-9]+}} +;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}} %A = load i16** %ptr %tmp0 = bitcast i16* %A to i8* %tmp1 = load <8 x i16>* %B @@ -344,7 +344,7 @@ define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind { ;CHECK: vld4lanei8: ;Check the alignment value. Max for this instruction is 32 bits: -;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}, :32] +;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}, :32] %tmp1 = load <8 x i8>* %B %tmp2 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 8) %tmp3 = extractvalue %struct.__neon_int8x8x4_t %tmp2, 0 Modified: llvm/trunk/test/CodeGen/X86/abi-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/abi-isel.ll?rev=131436&r1=131435&r2=131436&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/abi-isel.ll (original) +++ llvm/trunk/test/CodeGen/X86/abi-isel.ll Mon May 16 18:50:05 2011 @@ -12,17 +12,6 @@ ; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC ; RUN: llc < %s -asm-verbose=0 -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -join-physregs -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-STATIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -join-physregs -mtriple=i686-unknown-linux-gnu -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-32-PIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -join-physregs -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=LINUX-64-STATIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -join-physregs -mtriple=x86_64-unknown-linux-gnu -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=LINUX-64-PIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -join-physregs -mtriple=i686-apple-darwin -march=x86 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-32-STATIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -join-physregs -mtriple=i686-apple-darwin -march=x86 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-DYNAMIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -join-physregs -mtriple=i686-apple-darwin -march=x86 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-32-PIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -join-physregs -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=static -code-model=small | FileCheck %s -check-prefix=DARWIN-64-STATIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -join-physregs -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=dynamic-no-pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-DYNAMIC -; RUN: llc < %s -asm-verbose=0 -regalloc=basic -join-physregs -mtriple=x86_64-apple-darwin -march=x86-64 -relocation-model=pic -code-model=small | FileCheck %s -check-prefix=DARWIN-64-PIC - @src = external global [131072 x i32] @dst = external global [131072 x i32] @xsrc = external global [32 x i32] From resistor at mac.com Mon May 16 19:05:49 2011 From: resistor at mac.com (Owen Anderson) Date: Tue, 17 May 2011 00:05:49 -0000 Subject: [llvm-commits] [llvm] r131437 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <20110517000549.87B072A6C12C@llvm.org> Author: resistor Date: Mon May 16 19:05:49 2011 New Revision: 131437 URL: http://llvm.org/viewvc/llvm-project?rev=131437&view=rev Log: @llvm.lifetime.begin acts as a load, not @llvm.lifetime.end. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=131437&r1=131436&r2=131437&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Mon May 16 19:05:49 2011 @@ -497,7 +497,7 @@ // If we can do a pointer scan, make it happen. bool isLoad = !(MR & AliasAnalysis::Mod); if (IntrinsicInst *II = dyn_cast(QueryInst)) - isLoad |= II->getIntrinsicID() == Intrinsic::lifetime_end; + isLoad |= II->getIntrinsicID() == Intrinsic::lifetime_start; LocalCache = getPointerDependencyFrom(MemLoc, isLoad, ScanPos, QueryParent); From eli.friedman at gmail.com Mon May 16 19:13:47 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 17 May 2011 00:13:47 -0000 Subject: [llvm-commits] [llvm] r131438 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-extract.ll Message-ID: <20110517001347.D56492A6C12C@llvm.org> Author: efriedma Date: Mon May 16 19:13:47 2011 New Revision: 131438 URL: http://llvm.org/viewvc/llvm-project?rev=131438&view=rev Log: Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=131438&r1=131437&r2=131438&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon May 16 19:13:47 2011 @@ -1414,14 +1414,6 @@ if (Subtarget->IsCalleePop(isVarArg, CC)) return false; - // Handle *simple* calls for now. - const Type *RetTy = CS.getType(); - MVT RetVT; - if (RetTy->isVoidTy()) - RetVT = MVT::isVoid; - else if (!isTypeLegal(RetTy, RetVT, true)) - return false; - // Materialize callee address in a register. FIXME: GV address can be // handled with a CALLpcrel32 instead. X86AddressMode CalleeAM; @@ -1436,13 +1428,6 @@ } else return false; - // Allow calls which produce i1 results. - bool AndToI1 = false; - if (RetVT == MVT::i1) { - RetVT = MVT::i8; - AndToI1 = true; - } - // Deal with call operands first. SmallVector ArgVals; SmallVector Args; @@ -1697,63 +1682,73 @@ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp)) .addImm(NumBytes).addImm(NumBytesCallee); - // Now handle call return value (if any). + // Build info for return calling conv lowering code. + // FIXME: This is practically a copy-paste from TargetLowering::LowerCallTo. + SmallVector Ins; + SmallVector RetTys; + ComputeValueVTs(TLI, I->getType(), RetTys); + for (unsigned i = 0, e = RetTys.size(); i != e; ++i) { + EVT VT = RetTys[i]; + EVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT); + unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT); + for (unsigned j = 0; j != NumRegs; ++j) { + ISD::InputArg MyFlags; + MyFlags.VT = RegisterVT.getSimpleVT(); + MyFlags.Used = !CS.getInstruction()->use_empty(); + if (CS.paramHasAttr(0, Attribute::SExt)) + MyFlags.Flags.setSExt(); + if (CS.paramHasAttr(0, Attribute::ZExt)) + MyFlags.Flags.setZExt(); + if (CS.paramHasAttr(0, Attribute::InReg)) + MyFlags.Flags.setInReg(); + Ins.push_back(MyFlags); + } + } + + // Now handle call return values. SmallVector UsedRegs; - if (RetVT != MVT::isVoid) { - SmallVector RVLocs; - CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); - CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); - - // Copy all of the result registers out of their specified physreg. - assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); - EVT CopyVT = RVLocs[0].getValVT(); - TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); + SmallVector RVLocs; + CCState CCRetInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); + unsigned ResultReg = FuncInfo.CreateRegs(I->getType()); + CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86); + for (unsigned i = 0; i != RVLocs.size(); ++i) { + EVT CopyVT = RVLocs[i].getValVT(); + unsigned CopyReg = ResultReg + i; // If this is a call to a function that returns an fp value on the x87 fp // stack, but where we prefer to use the value in xmm registers, copy it // out as F80 and use a truncate to move it from fp stack reg to xmm reg. - if ((RVLocs[0].getLocReg() == X86::ST0 || - RVLocs[0].getLocReg() == X86::ST1) && + if ((RVLocs[i].getLocReg() == X86::ST0 || + RVLocs[i].getLocReg() == X86::ST1) && isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { CopyVT = MVT::f80; - DstRC = X86::RFP80RegisterClass; + CopyReg = createResultReg(X86::RFP80RegisterClass); } - unsigned ResultReg = createResultReg(DstRC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), - ResultReg).addReg(RVLocs[0].getLocReg()); - UsedRegs.push_back(RVLocs[0].getLocReg()); + ResultReg+i).addReg(RVLocs[i].getLocReg()); + UsedRegs.push_back(RVLocs[i].getLocReg()); - if (CopyVT != RVLocs[0].getValVT()) { + if (CopyVT != RVLocs[i].getValVT()) { // Round the F80 the right size, which also moves to the appropriate xmm // register. This is accomplished by storing the F80 value in memory and // then loading it back. Ewww... - EVT ResVT = RVLocs[0].getValVT(); + EVT ResVT = RVLocs[i].getValVT(); unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; unsigned MemSize = ResVT.getSizeInBits()/8; int FI = MFI.CreateStackObject(MemSize, MemSize, false); addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)), FI) - .addReg(ResultReg); - DstRC = ResVT == MVT::f32 - ? X86::FR32RegisterClass : X86::FR64RegisterClass; + .addReg(CopyReg); Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; - ResultReg = createResultReg(DstRC); addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(Opc), ResultReg), FI); - } - - if (AndToI1) { - // Mask out all but lowest bit for some call which produces an i1. - unsigned AndResult = createResultReg(X86::GR8RegisterClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); - ResultReg = AndResult; + TII.get(Opc), ResultReg + i), FI); } - - UpdateValueMap(I, ResultReg); } + if (RVLocs.size()) + UpdateValueMap(I, ResultReg, RVLocs.size()); + // Set all unused physreg defs as dead. static_cast(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); Modified: llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll?rev=131438&r1=131437&r2=131438&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll Mon May 16 19:13:47 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 | FileCheck %s +; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 -fast-isel-abort | FileCheck %s %struct.x = type { i64, i64 } %addovf = type { i32, i1 } From evan.cheng at apple.com Mon May 16 19:15:58 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 17 May 2011 00:15:58 -0000 Subject: [llvm-commits] [llvm] r131439 - /llvm/trunk/test/CodeGen/X86/hoist-common.ll Message-ID: <20110517001558.EB4352A6C12C@llvm.org> Author: evancheng Date: Mon May 16 19:15:58 2011 New Revision: 131439 URL: http://llvm.org/viewvc/llvm-project?rev=131439&view=rev Log: Add target triple so test doesn't fail on Windows machines. Modified: llvm/trunk/test/CodeGen/X86/hoist-common.ll Modified: llvm/trunk/test/CodeGen/X86/hoist-common.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/hoist-common.ll?rev=131439&r1=131438&r2=131439&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/hoist-common.ll (original) +++ llvm/trunk/test/CodeGen/X86/hoist-common.ll Mon May 16 19:15:58 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86-64 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s ; Common "xorb al, al" instruction in the two successor blocks should be ; moved to the entry block above the test + je. From dpatel at apple.com Mon May 16 19:20:50 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 17 May 2011 00:20:50 -0000 Subject: [llvm-commits] [debuginfo-tests] r131442 - /debuginfo-tests/trunk/nested-struct.cpp Message-ID: <20110517002050.7D6352A6C12C@llvm.org> Author: dpatel Date: Mon May 16 19:20:50 2011 New Revision: 131442 URL: http://llvm.org/viewvc/llvm-project?rev=131442&view=rev Log: Test case for r131441. Added: debuginfo-tests/trunk/nested-struct.cpp Added: debuginfo-tests/trunk/nested-struct.cpp URL: http://llvm.org/viewvc/llvm-project/debuginfo-tests/trunk/nested-struct.cpp?rev=131442&view=auto ============================================================================== --- debuginfo-tests/trunk/nested-struct.cpp (added) +++ debuginfo-tests/trunk/nested-struct.cpp Mon May 16 19:20:50 2011 @@ -0,0 +1,21 @@ +// RUN: %clangxx -O0 -g %s -c -o %t.o +// RUN: %test_debuginfo %s %t.o +// Radar 9440721 +// If debug info for my_number() is emitted outside function foo's scope +// then a debugger may not be able to handle it. At least one version of +// gdb crashes in such cases. + +// DEBUGGER: ptype foo +// CHECK: type = int (void) + +int foo() { + struct Local { + static int my_number() { + return 42; + } + }; + + int i = 0; + i = Local::my_number(); + return i + 1; +} From eli.friedman at gmail.com Mon May 16 19:39:14 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 17 May 2011 00:39:14 -0000 Subject: [llvm-commits] [llvm] r131444 - /llvm/trunk/test/CodeGen/X86/fast-isel-call.ll Message-ID: <20110517003914.78CF62A6C12C@llvm.org> Author: efriedma Date: Mon May 16 19:39:14 2011 New Revision: 131444 URL: http://llvm.org/viewvc/llvm-project?rev=131444&view=rev Log: Fix test. Modified: llvm/trunk/test/CodeGen/X86/fast-isel-call.ll Modified: llvm/trunk/test/CodeGen/X86/fast-isel-call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-call.ll?rev=131444&r1=131443&r2=131444&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-call.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-call.ll Mon May 16 19:39:14 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -fast-isel -march=x86 | grep and +; RUN: llc < %s -fast-isel -march=x86 | FileCheck %s define i32 @t() nounwind { tak: @@ -8,6 +8,8 @@ ret i32 1 BB2: ret i32 0 +; CHECK: calll +; CHECK-NEXT: testb $1 } declare i1 @foo() zeroext nounwind From eli.friedman at gmail.com Mon May 16 21:36:59 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 17 May 2011 02:36:59 -0000 Subject: [llvm-commits] [llvm] r131451 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-call.ll test/CodeGen/X86/fast-isel-extract.ll Message-ID: <20110517023659.6533A2A6C12C@llvm.org> Author: efriedma Date: Mon May 16 21:36:59 2011 New Revision: 131451 URL: http://llvm.org/viewvc/llvm-project?rev=131451&view=rev Log: Back out r131444 and r131438; they're breaking nightly tests. I'll look into it more tomorrow. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/test/CodeGen/X86/fast-isel-call.ll llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=131451&r1=131450&r2=131451&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Mon May 16 21:36:59 2011 @@ -1414,6 +1414,14 @@ if (Subtarget->IsCalleePop(isVarArg, CC)) return false; + // Handle *simple* calls for now. + const Type *RetTy = CS.getType(); + MVT RetVT; + if (RetTy->isVoidTy()) + RetVT = MVT::isVoid; + else if (!isTypeLegal(RetTy, RetVT, true)) + return false; + // Materialize callee address in a register. FIXME: GV address can be // handled with a CALLpcrel32 instead. X86AddressMode CalleeAM; @@ -1428,6 +1436,13 @@ } else return false; + // Allow calls which produce i1 results. + bool AndToI1 = false; + if (RetVT == MVT::i1) { + RetVT = MVT::i8; + AndToI1 = true; + } + // Deal with call operands first. SmallVector ArgVals; SmallVector Args; @@ -1682,72 +1697,62 @@ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp)) .addImm(NumBytes).addImm(NumBytesCallee); - // Build info for return calling conv lowering code. - // FIXME: This is practically a copy-paste from TargetLowering::LowerCallTo. - SmallVector Ins; - SmallVector RetTys; - ComputeValueVTs(TLI, I->getType(), RetTys); - for (unsigned i = 0, e = RetTys.size(); i != e; ++i) { - EVT VT = RetTys[i]; - EVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT); - unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT); - for (unsigned j = 0; j != NumRegs; ++j) { - ISD::InputArg MyFlags; - MyFlags.VT = RegisterVT.getSimpleVT(); - MyFlags.Used = !CS.getInstruction()->use_empty(); - if (CS.paramHasAttr(0, Attribute::SExt)) - MyFlags.Flags.setSExt(); - if (CS.paramHasAttr(0, Attribute::ZExt)) - MyFlags.Flags.setZExt(); - if (CS.paramHasAttr(0, Attribute::InReg)) - MyFlags.Flags.setInReg(); - Ins.push_back(MyFlags); - } - } - - // Now handle call return values. + // Now handle call return value (if any). SmallVector UsedRegs; - SmallVector RVLocs; - CCState CCRetInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); - unsigned ResultReg = FuncInfo.CreateRegs(I->getType()); - CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86); - for (unsigned i = 0; i != RVLocs.size(); ++i) { - EVT CopyVT = RVLocs[i].getValVT(); - unsigned CopyReg = ResultReg + i; + if (RetVT != MVT::isVoid) { + SmallVector RVLocs; + CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); + CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); + + // Copy all of the result registers out of their specified physreg. + assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); + EVT CopyVT = RVLocs[0].getValVT(); + TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); // If this is a call to a function that returns an fp value on the x87 fp // stack, but where we prefer to use the value in xmm registers, copy it // out as F80 and use a truncate to move it from fp stack reg to xmm reg. - if ((RVLocs[i].getLocReg() == X86::ST0 || - RVLocs[i].getLocReg() == X86::ST1) && + if ((RVLocs[0].getLocReg() == X86::ST0 || + RVLocs[0].getLocReg() == X86::ST1) && isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { CopyVT = MVT::f80; - CopyReg = createResultReg(X86::RFP80RegisterClass); + DstRC = X86::RFP80RegisterClass; } + unsigned ResultReg = createResultReg(DstRC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), - ResultReg+i).addReg(RVLocs[i].getLocReg()); - UsedRegs.push_back(RVLocs[i].getLocReg()); + ResultReg).addReg(RVLocs[0].getLocReg()); + UsedRegs.push_back(RVLocs[0].getLocReg()); - if (CopyVT != RVLocs[i].getValVT()) { + if (CopyVT != RVLocs[0].getValVT()) { // Round the F80 the right size, which also moves to the appropriate xmm // register. This is accomplished by storing the F80 value in memory and // then loading it back. Ewww... - EVT ResVT = RVLocs[i].getValVT(); + EVT ResVT = RVLocs[0].getValVT(); unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; unsigned MemSize = ResVT.getSizeInBits()/8; int FI = MFI.CreateStackObject(MemSize, MemSize, false); addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)), FI) - .addReg(CopyReg); + .addReg(ResultReg); + DstRC = ResVT == MVT::f32 + ? X86::FR32RegisterClass : X86::FR64RegisterClass; Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; + ResultReg = createResultReg(DstRC); addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(Opc), ResultReg + i), FI); + TII.get(Opc), ResultReg), FI); } - } - if (RVLocs.size()) - UpdateValueMap(I, ResultReg, RVLocs.size()); + if (AndToI1) { + // Mask out all but lowest bit for some call which produces an i1. + unsigned AndResult = createResultReg(X86::GR8RegisterClass); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, + TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); + ResultReg = AndResult; + } + + UpdateValueMap(I, ResultReg); + } // Set all unused physreg defs as dead. static_cast(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); Modified: llvm/trunk/test/CodeGen/X86/fast-isel-call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-call.ll?rev=131451&r1=131450&r2=131451&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-call.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-call.ll Mon May 16 21:36:59 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -fast-isel -march=x86 | FileCheck %s +; RUN: llc < %s -fast-isel -march=x86 | grep and define i32 @t() nounwind { tak: @@ -8,8 +8,6 @@ ret i32 1 BB2: ret i32 0 -; CHECK: calll -; CHECK-NEXT: testb $1 } declare i1 @foo() zeroext nounwind Modified: llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll?rev=131451&r1=131450&r2=131451&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll Mon May 16 21:36:59 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 -fast-isel-abort | FileCheck %s +; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 | FileCheck %s %struct.x = type { i64, i64 } %addovf = type { i32, i1 } From stuart at apple.com Mon May 16 21:38:59 2011 From: stuart at apple.com (Stuart Hastings) Date: Tue, 17 May 2011 02:38:59 -0000 Subject: [llvm-commits] [llvm] r131452 - /llvm/trunk/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll Message-ID: <20110517023859.85E862A6C12C@llvm.org> Author: stuart Date: Mon May 16 21:38:59 2011 New Revision: 131452 URL: http://llvm.org/viewvc/llvm-project?rev=131452&view=rev Log: Drop lli, revise test. Modified: llvm/trunk/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll Modified: llvm/trunk/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll?rev=131452&r1=131451&r2=131452&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/2011-05-13-InBoundsGEP.ll Mon May 16 21:38:59 2011 @@ -1,5 +1,4 @@ -; RUN: opt < %s -instcombine | lli -; REQUIRES: disabled +; RUN: opt < %s -S -instcombine | FileCheck %s ; rdar://problem/9267970 ; ideally this test will run on a 32-bit host ; must not discard GEPs that might overflow at runtime (aren't inbounds) @@ -9,7 +8,9 @@ %tmp1 = add i32 %argc, -2 %tmp2 = add i32 %argc, 1879048192 %p = alloca i8 +; CHECK: getelementptr %p1 = getelementptr i8* %p, i32 %tmp1 +; CHECK: getelementptr %p2 = getelementptr i8* %p, i32 %tmp2 %cmp = icmp ult i8* %p1, %p2 br i1 %cmp, label %bbtrue, label %bbfalse From nadav.rotem at intel.com Tue May 17 02:19:34 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Tue, 17 May 2011 10:19:34 +0300 Subject: [llvm-commits] [PATCH] Fix assert in x86 Extract_vec_EltCombine Message-ID: <6594DDFF12B03D4E89690887C2486994027D7A25F9@hasmsx504.ger.corp.intel.com> This patch fixes a bug in PerformEXTRACT_VECTOR_ELTCombine on 64bit systems. Sorry, no test. I can only reproduce it on LLVM2.8, but the fix is still valid for the trunk. In this code we create an ADD SDNode with two different types. Sometimes the IDX value is not of the same type as the pointer type. May I commit ? Index: lib/Target/X86/X86ISelLowering.cpp =================================================================== --- lib/Target/X86/X86ISelLowering.cpp (revision 131179) +++ lib/Target/X86/X86ISelLowering.cpp (working copy) @@ -11059,7 +11059,7 @@ uint64_t Offset = EltSize * cast(Idx)->getZExtValue(); SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); - SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), + SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), StackPtr, OffsetVal); // Load the scalar. --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110517/3d6ee608/attachment.html From sabre at nondot.org Tue May 17 02:22:33 2011 From: sabre at nondot.org (Chris Lattner) Date: Tue, 17 May 2011 07:22:33 -0000 Subject: [llvm-commits] [llvm] r131455 - /llvm/trunk/lib/Target/X86/README.txt Message-ID: <20110517072234.0B2102A6C12C@llvm.org> Author: lattner Date: Tue May 17 02:22:33 2011 New Revision: 131455 URL: http://llvm.org/viewvc/llvm-project?rev=131455&view=rev Log: add a note Modified: llvm/trunk/lib/Target/X86/README.txt Modified: llvm/trunk/lib/Target/X86/README.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/README.txt?rev=131455&r1=131454&r2=131455&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/README.txt (original) +++ llvm/trunk/lib/Target/X86/README.txt Tue May 17 02:22:33 2011 @@ -2040,3 +2040,29 @@ The move of 0 could be scheduled above the test to make it is xor reg,reg. //===---------------------------------------------------------------------===// + +GCC PR48986. We currently compile this: + +void bar(void); +void yyy(int* p) { + if (__sync_fetch_and_add(p, -1) == 1) + bar(); +} + +into: + movl $-1, %eax + lock + xaddl %eax, (%rdi) + cmpl $1, %eax + je LBB0_2 + +Instead we could generate: + + lock + dec %rdi + je LBB0_2 + +The trick is to match "fetch_and_add(X, -C) == C". + +//===---------------------------------------------------------------------===// + From baldrick at free.fr Tue May 17 02:28:31 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 17 May 2011 09:28:31 +0200 Subject: [llvm-commits] [PATCH] Fix assert in x86 Extract_vec_EltCombine In-Reply-To: <6594DDFF12B03D4E89690887C2486994027D7A25F9@hasmsx504.ger.corp.intel.com> References: <6594DDFF12B03D4E89690887C2486994027D7A25F9@hasmsx504.ger.corp.intel.com> Message-ID: <4DD2239F.1000404@free.fr> Hi Nadav, > This patch fixes a bug in PerformEXTRACT_VECTOR_ELTCombine on 64bit systems. > Sorry, no test. I can only reproduce it on LLVM2.8, but the fix is still valid > for the trunk. > > In this code we create an ADD SDNode with two different types. Sometimes the IDX > value is not of the same type as the pointer type. > > May I commit ? this looks fine to me - please go ahead. Ciao, Duncan. > > Index: lib/Target/X86/X86ISelLowering.cpp > > =================================================================== > > --- lib/Target/X86/X86ISelLowering.cpp (revision 131179) > > +++ lib/Target/X86/X86ISelLowering.cpp (working copy) > > @@ -11059,7 +11059,7 @@ > > uint64_t Offset = EltSize * cast(Idx)->getZExtValue(); > > SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); > > - SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), > > + SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), > > StackPtr, OffsetVal); > > // Load the scalar. > > --------------------------------------------------------------------- > Intel Israel (74) Limited > > This e-mail and any attachments may contain confidential material for > the sole use of the intended recipient(s). Any review or distribution > by others is strictly prohibited. If you are not the intended > recipient, please contact the sender and delete all copies. > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Tue May 17 02:47:55 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 17 May 2011 07:47:55 -0000 Subject: [llvm-commits] [llvm] r131456 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Message-ID: <20110517074755.F12992A6C12D@llvm.org> Author: echristo Date: Tue May 17 02:47:55 2011 New Revision: 131456 URL: http://llvm.org/viewvc/llvm-project?rev=131456&view=rev Log: Make this code a little less magic number laden. Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=131456&r1=131455&r2=131456&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue May 17 02:47:55 2011 @@ -1482,6 +1482,24 @@ } } +enum AtomicOpc { + OR +}; + +enum AtomicSz { + ConstantI8, + I8, + SextConstantI16, + ConstantI16, + I16, + SextConstantI32, + ConstantI32, + I32, + SextConstantI64, + ConstantI64, + I64 +}; + static const unsigned int AtomicOpcTbl[1][11] = { { X86::LOCK_OR8mi, @@ -1521,42 +1539,42 @@ } // Which index into the table. - unsigned index = 0; + enum AtomicOpc Op = OR; unsigned Opc = 0; switch (NVT.getSimpleVT().SimpleTy) { default: return 0; case MVT::i8: if (isCN) - Opc = AtomicOpcTbl[index][0]; + Opc = AtomicOpcTbl[Op][ConstantI8]; else - Opc = AtomicOpcTbl[index][1]; + Opc = AtomicOpcTbl[Op][I8]; break; case MVT::i16: if (isCN) { if (immSext8(Val.getNode())) - Opc = AtomicOpcTbl[index][2]; + Opc = AtomicOpcTbl[Op][SextConstantI16]; else - Opc = AtomicOpcTbl[index][3]; + Opc = AtomicOpcTbl[Op][ConstantI16]; } else - Opc = AtomicOpcTbl[index][4]; + Opc = AtomicOpcTbl[Op][I16]; break; case MVT::i32: if (isCN) { if (immSext8(Val.getNode())) - Opc = AtomicOpcTbl[index][5]; + Opc = AtomicOpcTbl[Op][SextConstantI32]; else - Opc = AtomicOpcTbl[index][6]; + Opc = AtomicOpcTbl[Op][ConstantI32]; } else - Opc = AtomicOpcTbl[index][7]; + Opc = AtomicOpcTbl[Op][I32]; break; case MVT::i64: if (isCN) { if (immSext8(Val.getNode())) - Opc = AtomicOpcTbl[index][8]; + Opc = AtomicOpcTbl[Op][SextConstantI64]; else if (i64immSExt32(Val.getNode())) - Opc = AtomicOpcTbl[index][9]; + Opc = AtomicOpcTbl[Op][ConstantI64]; } else - Opc = AtomicOpcTbl[index][10]; + Opc = AtomicOpcTbl[Op][I64]; break; } From echristo at apple.com Tue May 17 02:53:31 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 17 May 2011 00:53:31 -0700 Subject: [llvm-commits] [llvm] r131200 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp In-Reply-To: <47BD9F01-4096-4758-8F5D-0D5338E6CA8A@apple.com> References: <20110511214458.651262A6C12C@llvm.org> <47BD9F01-4096-4758-8F5D-0D5338E6CA8A@apple.com> Message-ID: On May 11, 2011, at 10:13 PM, Chris Lattner wrote: > Cool, please use an enum to index into the array though, instead of magic numbers like AtomicOpcTbl[index][7] Little better as of r131456. :) -eric -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110517/f489880f/attachment.html From echristo at apple.com Tue May 17 02:50:41 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 17 May 2011 07:50:41 -0000 Subject: [llvm-commits] [llvm] r131457 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Message-ID: <20110517075041.73BB72A6C12D@llvm.org> Author: echristo Date: Tue May 17 02:50:41 2011 New Revision: 131457 URL: http://llvm.org/viewvc/llvm-project?rev=131457&view=rev Log: Couple less magic numbers. Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=131457&r1=131456&r2=131457&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue May 17 02:50:41 2011 @@ -1483,7 +1483,8 @@ } enum AtomicOpc { - OR + OR, + AtomicOpcEnd }; enum AtomicSz { @@ -1497,10 +1498,11 @@ I32, SextConstantI64, ConstantI64, - I64 + I64, + AtomicSzEnd }; -static const unsigned int AtomicOpcTbl[1][11] = { +static const unsigned int AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = { { X86::LOCK_OR8mi, X86::LOCK_OR8mr, From echristo at apple.com Tue May 17 03:10:18 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 17 May 2011 08:10:18 -0000 Subject: [llvm-commits] [llvm] r131458 - in /llvm/trunk/lib/Target/X86: X86ISelDAGToDAG.cpp X86InstrCompiler.td Message-ID: <20110517081018.DDD6E2A6C12D@llvm.org> Author: echristo Date: Tue May 17 03:10:18 2011 New Revision: 131458 URL: http://llvm.org/viewvc/llvm-project?rev=131458&view=rev Log: Support XOR and AND optimization with no return value. Finishes off rdar://8470697 Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp llvm/trunk/lib/Target/X86/X86InstrCompiler.td Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=131458&r1=131457&r2=131458&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue May 17 03:10:18 2011 @@ -189,7 +189,7 @@ SDNode *Select(SDNode *N); SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT); - SDNode *SelectAtomicLoadOr(SDNode *Node, EVT NVT); + SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT); bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM); bool MatchWrapper(SDValue N, X86ISelAddressMode &AM); @@ -1484,6 +1484,8 @@ enum AtomicOpc { OR, + AND, + XOR, AtomicOpcEnd }; @@ -1515,10 +1517,36 @@ X86::LOCK_OR64mi8, X86::LOCK_OR64mi32, X86::LOCK_OR64mr + }, + { + X86::LOCK_AND8mi, + X86::LOCK_AND8mr, + X86::LOCK_AND16mi8, + X86::LOCK_AND16mi, + X86::LOCK_AND16mr, + X86::LOCK_AND32mi8, + X86::LOCK_AND32mi, + X86::LOCK_AND32mr, + X86::LOCK_AND64mi8, + X86::LOCK_AND64mi32, + X86::LOCK_AND64mr + }, + { + X86::LOCK_XOR8mi, + X86::LOCK_XOR8mr, + X86::LOCK_XOR16mi8, + X86::LOCK_XOR16mi, + X86::LOCK_XOR16mr, + X86::LOCK_XOR32mi8, + X86::LOCK_XOR32mi, + X86::LOCK_XOR32mr, + X86::LOCK_XOR64mi8, + X86::LOCK_XOR64mi32, + X86::LOCK_XOR64mr } }; -SDNode *X86DAGToDAGISel::SelectAtomicLoadOr(SDNode *Node, EVT NVT) { +SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) { if (Node->hasAnyUseOfValue(0)) return 0; @@ -1533,6 +1561,22 @@ if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) return 0; + // Which index into the table. + enum AtomicOpc Op; + switch (Node->getOpcode()) { + case ISD::ATOMIC_LOAD_OR: + Op = OR; + break; + case ISD::ATOMIC_LOAD_AND: + Op = AND; + break; + case ISD::ATOMIC_LOAD_XOR: + Op = XOR; + break; + default: + return 0; + } + bool isCN = false; ConstantSDNode *CN = dyn_cast(Val); if (CN) { @@ -1540,8 +1584,6 @@ Val = CurDAG->getTargetConstant(CN->getSExtValue(), NVT); } - // Which index into the table. - enum AtomicOpc Op = OR; unsigned Opc = 0; switch (NVT.getSimpleVT().SimpleTy) { default: return 0; @@ -1693,8 +1735,10 @@ return RetVal; break; } + case ISD::ATOMIC_LOAD_XOR: + case ISD::ATOMIC_LOAD_AND: case ISD::ATOMIC_LOAD_OR: { - SDNode *RetVal = SelectAtomicLoadOr(Node, NVT); + SDNode *RetVal = SelectAtomicLoadArith(Node, NVT); if (RetVal) return RetVal; break; Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=131458&r1=131457&r2=131458&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Tue May 17 03:10:18 2011 @@ -630,6 +630,8 @@ defm LOCK_ADD : LOCK_ArithBinOp<0x00, 0x80, 0x83, MRM0m, "add">; defm LOCK_SUB : LOCK_ArithBinOp<0x28, 0x80, 0x83, MRM5m, "sub">; defm LOCK_OR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM1m, "or">; +defm LOCK_AND : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM4m, "and">; +defm LOCK_XOR : LOCK_ArithBinOp<0x08, 0x80, 0x83, MRM6m, "xor">; // Optimized codegen when the non-memory output is not used. let Defs = [EFLAGS], mayLoad = 1, mayStore = 1, isCodeGenOnly = 1 in { From echristo at apple.com Tue May 17 03:16:14 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 17 May 2011 08:16:14 -0000 Subject: [llvm-commits] [llvm] r131459 - /llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Message-ID: <20110517081614.4CDDA2A6C12D@llvm.org> Author: echristo Date: Tue May 17 03:16:14 2011 New Revision: 131459 URL: http://llvm.org/viewvc/llvm-project?rev=131459&view=rev Log: Update comment. Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=131459&r1=131458&r2=131459&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Tue May 17 03:16:14 2011 @@ -1550,10 +1550,10 @@ if (Node->hasAnyUseOfValue(0)) return 0; - // Optimize common patterns for __sync_or_and_fetch where the result - // is not used. This allows us to use the "lock" version of the or - // instruction. - // FIXME: Same as for 'add' and 'sub'. + // Optimize common patterns for __sync_or_and_fetch and similar arith + // operations where the result is not used. This allows us to use the "lock" + // version of the arithmetic instruction. + // FIXME: Same as for 'add' and 'sub', try to merge those down here. SDValue Chain = Node->getOperand(0); SDValue Ptr = Node->getOperand(1); SDValue Val = Node->getOperand(2); From nadav.rotem at intel.com Tue May 17 03:31:57 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Tue, 17 May 2011 08:31:57 -0000 Subject: [llvm-commits] [llvm] r131461 - /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Message-ID: <20110517083157.A6EF82A6C12C@llvm.org> Author: nadav Date: Tue May 17 03:31:57 2011 New Revision: 131461 URL: http://llvm.org/viewvc/llvm-project?rev=131461&view=rev Log: Fix a bug in PerformEXTRACT_VECTOR_ELTCombine. The code created an ADD SDNode with two different types, in cases where the index and the ptr had different types. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=131461&r1=131460&r2=131461&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue May 17 03:31:57 2011 @@ -11038,14 +11038,14 @@ UE = Uses.end(); UI != UE; ++UI) { SDNode *Extract = *UI; - // Compute the element's address. + // cOMpute the element's address. SDValue Idx = Extract->getOperand(1); unsigned EltSize = InputVector.getValueType().getVectorElementType().getSizeInBits()/8; uint64_t Offset = EltSize * cast(Idx)->getZExtValue(); SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); - SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), + SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), StackPtr, OffsetVal); // Load the scalar. From baldrick at free.fr Tue May 17 06:57:17 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 17 May 2011 11:57:17 -0000 Subject: [llvm-commits] [dragonegg] r131462 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110517115717.BA6672A6C12C@llvm.org> Author: baldrick Date: Tue May 17 06:57:17 2011 New Revision: 131462 URL: http://llvm.org/viewvc/llvm-project?rev=131462&view=rev Log: For some reason inline asm handling was not allowing an implicit conversion for floating point types even though the implementation can handle that. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=131462&r1=131461&r2=131462&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Tue May 17 06:57:17 2011 @@ -7489,8 +7489,7 @@ } } if (OTy && OTy != OpTy) { - if (!(OTy->isIntegerTy() || OTy->isPointerTy()) || - !(OpTy->isIntegerTy() || OpTy->isPointerTy())) { + if (!OTy->isSingleValueType() || !OpTy->isSingleValueType()) { error_at(gimple_location(stmt), "unsupported inline asm: input constraint with a matching " "output constraint of incompatible type!"); From rafael.espindola at gmail.com Tue May 17 10:26:34 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 17 May 2011 15:26:34 -0000 Subject: [llvm-commits] [llvm] r131463 - /llvm/trunk/lib/Support/Unix/Host.inc Message-ID: <20110517152634.7B27F2A6C12C@llvm.org> Author: rafael Date: Tue May 17 10:26:34 2011 New Revision: 131463 URL: http://llvm.org/viewvc/llvm-project?rev=131463&view=rev Log: Don't include information about the build into the information returned by getHostTriple. This fixes a 32 bit clang running on a 64 bit ubuntu. Modified: llvm/trunk/lib/Support/Unix/Host.inc Modified: llvm/trunk/lib/Support/Unix/Host.inc URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Unix/Host.inc?rev=131463&r1=131462&r2=131463&view=diff ============================================================================== --- llvm/trunk/lib/Support/Unix/Host.inc (original) +++ llvm/trunk/lib/Support/Unix/Host.inc Tue May 17 10:26:34 2011 @@ -44,35 +44,6 @@ // Normalize the arch, since the host triple may not actually match the host. std::string Arch = ArchSplit.first; - // It would be nice to do this in terms of llvm::Triple, but that is in - // Support which is layered above us. -#if defined(__x86_64__) - Arch = "x86_64"; -#elif defined(__i386__) - Arch = "i386"; -#elif defined(__ppc64__) - Arch = "powerpc64"; -#elif defined(__ppc__) - Arch = "powerpc"; -#elif defined(__arm__) - - // FIXME: We need to pick the right ARM triple (which involves querying the - // chip). However, for now this is most important for LLVM arch selection, so - // we only need to make sure to distinguish ARM and Thumb. -# if defined(__thumb__) - Arch = "thumb"; -# else - Arch = "arm"; -# endif - -#else - - // FIXME: When enough auto-detection is in place, this should just - // #error. Then at least the arch selection is done, and we only need the OS - // etc selection to kill off the use of LLVM_HOSTTRIPLE. - -#endif - std::string Triple(Arch); Triple += '-'; Triple += ArchSplit.second; From xuzhongxing at gmail.com Mon May 16 07:42:22 2011 From: xuzhongxing at gmail.com (Zhongxing Xu) Date: Mon, 16 May 2011 12:42:22 -0000 Subject: [llvm-commits] [llvm] r131402 - /llvm/trunk/include/llvm/ADT/FoldingSet.h Message-ID: <20110516124222.C8BD42A6C12C@llvm.org> Author: zhongxingxu Date: Mon May 16 07:42:22 2011 New Revision: 131402 URL: http://llvm.org/viewvc/llvm-project?rev=131402&view=rev Log: Remove redundant template partial specilization. Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h Modified: llvm/trunk/include/llvm/ADT/FoldingSet.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/FoldingSet.h?rev=131402&r1=131401&r2=131402&view=diff ============================================================================== --- llvm/trunk/include/llvm/ADT/FoldingSet.h (original) +++ llvm/trunk/include/llvm/ADT/FoldingSet.h Mon May 16 07:42:22 2011 @@ -671,17 +671,10 @@ // Partial specializations of FoldingSetTrait. template struct FoldingSetTrait { - static inline void Profile(const T *X, FoldingSetNodeID &ID) { + static inline void Profile(T *X, FoldingSetNodeID &ID) { ID.AddPointer(X); } }; - -template struct FoldingSetTrait { - static inline void Profile(const T *X, FoldingSetNodeID &ID) { - ID.AddPointer(X); - } -}; - } // End of namespace llvm. #endif From pageexec at freemail.hu Tue May 17 02:45:33 2011 From: pageexec at freemail.hu (pageexec at freemail.hu) Date: Tue, 17 May 2011 09:45:33 +0200 Subject: [llvm-commits] [llvm] r131455 - /llvm/trunk/lib/Target/X86/README.txt In-Reply-To: <20110517072234.0B2102A6C12C@llvm.org> References: <20110517072234.0B2102A6C12C@llvm.org> Message-ID: <4DD2279D.31996.2786C25@pageexec.freemail.hu> On 17 May 2011 at 7:22, Chris Lattner wrote: > +into: > + movl $-1, %eax > + lock > + xaddl %eax, (%rdi) > + cmpl $1, %eax > + je LBB0_2 > + > +Instead we could generate: > + > + lock > + dec %rdi ^^^^ you probably meant dec (%rdi) ? > + je LBB0_2 > + > +The trick is to match "fetch_and_add(X, -C) == C". From stoklund at 2pi.dk Tue May 17 11:38:37 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 17 May 2011 16:38:37 -0000 Subject: [llvm-commits] [llvm] r131466 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Message-ID: <20110517163837.48AF32A6C12C@llvm.org> Author: stoklund Date: Tue May 17 11:38:37 2011 New Revision: 131466 URL: http://llvm.org/viewvc/llvm-project?rev=131466&view=rev Log: Tweak cross-class coalescing to be more aggressive when the target class is small. The greedy register allocator has live range splitting and register class inflation, so it can actually fully undo this join, including restoring the original register classes. We still don't want to do this for long live ranges, mostly because of the high register pressure of there are many constrained live ranges overlapping. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=131466&r1=131465&r2=131466&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue May 17 11:38:37 2011 @@ -987,8 +987,14 @@ LiveInterval &DstInt = li_->getInterval(DstReg); unsigned SrcSize = li_->getApproximateInstructionCount(SrcInt); unsigned DstSize = li_->getApproximateInstructionCount(DstInt); - if (SrcSize <= NewRCCount && DstSize <= NewRCCount) + + // Coalesce aggressively if the intervals are small compared to the number of + // registers in the new class. The number 4 is fairly arbitrary, chosen to be + // less aggressive than the 8 used for the whole function size. + const unsigned ThresSize = 4 * NewRCCount; + if (SrcSize <= ThresSize && DstSize <= ThresSize) return true; + // Estimate *register use density*. If it doubles or more, abort. unsigned SrcUses = std::distance(mri_->use_nodbg_begin(SrcReg), mri_->use_nodbg_end()); @@ -996,12 +1002,12 @@ mri_->use_nodbg_end()); unsigned NewUses = SrcUses + DstUses; unsigned NewSize = SrcSize + DstSize; - if (SrcRC != NewRC && SrcSize > NewRCCount) { + if (SrcRC != NewRC && SrcSize > ThresSize) { unsigned SrcRCCount = allocatableRCRegs_[SrcRC].count(); if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount) return false; } - if (DstRC != NewRC && DstSize > NewRCCount) { + if (DstRC != NewRC && DstSize > ThresSize) { unsigned DstRCCount = allocatableRCRegs_[DstRC].count(); if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount) return false; From stuart at apple.com Tue May 17 11:45:55 2011 From: stuart at apple.com (Stuart Hastings) Date: Tue, 17 May 2011 16:45:55 -0000 Subject: [llvm-commits] [llvm] r131467 - in /llvm/trunk/lib: CodeGen/CallingConvLower.cpp Target/X86/X86ISelLowering.cpp Target/X86/X86ISelLowering.h Message-ID: <20110517164555.D0A112A6C12C@llvm.org> Author: stuart Date: Tue May 17 11:45:55 2011 New Revision: 131467 URL: http://llvm.org/viewvc/llvm-project?rev=131467&view=rev Log: Fix an obscure issue in X86_64 parameter passing: if a tiny byval is passed as the fifth parameter, insure it's passed correctly (in R9). rdar://problem/6920088 Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=131467&r1=131466&r2=131467&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Tue May 17 11:45:55 2011 @@ -48,8 +48,12 @@ if (MinAlign > (int)Align) Align = MinAlign; TM.getTargetLowering()->HandleByVal(const_cast(this), Size); - unsigned Offset = AllocateStack(Size, Align); - addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); + if (Size != 0) { + unsigned Offset = AllocateStack(Size, Align); + addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); + } else { + addLoc(CCValAssign::getReg(ValNo, ValVT, getFirstByValReg(), LocVT, LocInfo)); + } } /// MarkAllocated - Mark a register and all of its aliases as allocated. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=131467&r1=131466&r2=131467&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue May 17 11:45:55 2011 @@ -2091,19 +2091,36 @@ } if (VA.isRegLoc()) { - RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); - if (isVarArg && IsWin64) { - // Win64 ABI requires argument XMM reg to be copied to the corresponding - // shadow reg if callee is a varargs function. - unsigned ShadowReg = 0; - switch (VA.getLocReg()) { - case X86::XMM0: ShadowReg = X86::RCX; break; - case X86::XMM1: ShadowReg = X86::RDX; break; - case X86::XMM2: ShadowReg = X86::R8; break; - case X86::XMM3: ShadowReg = X86::R9; break; + if (isByVal && (!IsSibcall && !isTailCall)) { + // 64-bit only. x86_32 passes everything on the stack. + assert(CCInfo.isFirstByValRegValid() && "isByVal, but no valid register assigned!"); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + unsigned int i, j; + for (i = 0, j = CCInfo.getFirstByValReg(); j <= X86::R9; i++, j++) { + SDValue Const = DAG.getConstant(8*i, MVT::i64); + SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); + SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, + MachinePointerInfo(), + false, false, 0); + MemOpChains.push_back(Load.getValue(1)); + RegsToPass.push_back(std::make_pair(j, Load)); + } + CCInfo.clearFirstByValReg(); + } else { + RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); + if (isVarArg && IsWin64) { + // Win64 ABI requires argument XMM reg to be copied to the corresponding + // shadow reg if callee is a varargs function. + unsigned ShadowReg = 0; + switch (VA.getLocReg()) { + case X86::XMM0: ShadowReg = X86::RCX; break; + case X86::XMM1: ShadowReg = X86::RDX; break; + case X86::XMM2: ShadowReg = X86::R8; break; + case X86::XMM3: ShadowReg = X86::R9; break; + } + if (ShadowReg) + RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); } - if (ShadowReg) - RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); } } else if (!IsSibcall && (!isTailCall || isByVal)) { assert(VA.isMemLoc()); @@ -2438,6 +2455,47 @@ return Offset; } +/// HandleByVal - Every parameter *after* a byval parameter is passed +/// on the stack. Remember the next parameter register to allocate, +/// and then confiscate the rest of the parameter registers to insure +/// this. +void +X86TargetLowering::HandleByVal(CCState *State, unsigned &size) const { + // X86_32 passes all parameters on the stack, byval or whatever. + // X86_64 does not split parameters between registers and memory; if + // the parameter does not fit entirely inside the remaining + // parameter registers, it goes on the stack. + static const unsigned RegList2[] = { + X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 + }; + + if (!Subtarget->is64Bit()) + return; + + if (size > 16) // X86_64 aggregates > 16 bytes are passed in memory. + return; + + unsigned reg = State->getFirstUnallocated(RegList2, 6); + + if (reg == 6) // Out of regs to allocate. + return; + + // We expect the size to be 32 bits, or some non-zero multiple of 64 bits. + unsigned nregs = size / 8; + if (nregs == 0) nregs=1; // 32-bit case. + + unsigned regs_available = 6 - reg; + + if (nregs <= regs_available) { + size = 0; + State->setFirstByValReg(RegList2[reg]); + while (nregs--) { + State->AllocateReg(RegList2[reg]); + reg++; + } + } +} + /// MatchingStackOffset - Return true if the given stack call argument is /// already available in the same position (relatively) of the caller's /// incoming argument stack. @@ -2602,7 +2660,7 @@ } CCInfo.AnalyzeCallOperands(Outs, CC_X86); - if (CCInfo.getNextStackOffset()) { + if (ArgLocs.size()) { MachineFunction &MF = DAG.getMachineFunction(); if (MF.getInfo()->getBytesToPopOnReturn()) return false; @@ -2619,6 +2677,8 @@ ISD::ArgFlagsTy Flags = Outs[i].Flags; if (VA.getLocInfo() == CCValAssign::Indirect) return false; + if (Flags.isByVal()) + return false; if (!VA.isRegLoc()) { if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, MFI, MRI, TII)) Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=131467&r1=131466&r2=131467&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue May 17 11:45:55 2011 @@ -728,6 +728,8 @@ // Call lowering helpers. + void HandleByVal(CCState *, unsigned &) const; + /// IsEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. Targets which want to do tail call /// optimization should implement this function. From stuart at apple.com Tue May 17 11:59:46 2011 From: stuart at apple.com (Stuart Hastings) Date: Tue, 17 May 2011 16:59:46 -0000 Subject: [llvm-commits] [llvm] r131469 - in /llvm/trunk/lib: CodeGen/CallingConvLower.cpp Target/X86/X86ISelLowering.cpp Target/X86/X86ISelLowering.h Message-ID: <20110517165946.543672A6C12C@llvm.org> Author: stuart Date: Tue May 17 11:59:46 2011 New Revision: 131469 URL: http://llvm.org/viewvc/llvm-project?rev=131469&view=rev Log: Revert 131467 due to buildbot complaint. Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/CodeGen/CallingConvLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CallingConvLower.cpp?rev=131469&r1=131468&r2=131469&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CallingConvLower.cpp (original) +++ llvm/trunk/lib/CodeGen/CallingConvLower.cpp Tue May 17 11:59:46 2011 @@ -48,12 +48,8 @@ if (MinAlign > (int)Align) Align = MinAlign; TM.getTargetLowering()->HandleByVal(const_cast(this), Size); - if (Size != 0) { - unsigned Offset = AllocateStack(Size, Align); - addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); - } else { - addLoc(CCValAssign::getReg(ValNo, ValVT, getFirstByValReg(), LocVT, LocInfo)); - } + unsigned Offset = AllocateStack(Size, Align); + addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); } /// MarkAllocated - Mark a register and all of its aliases as allocated. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=131469&r1=131468&r2=131469&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue May 17 11:59:46 2011 @@ -2091,36 +2091,21 @@ } if (VA.isRegLoc()) { - if (isByVal && (!IsSibcall && !isTailCall)) { - // 64-bit only. x86_32 passes everything on the stack. - assert(CCInfo.isFirstByValRegValid() && "isByVal, but no valid register assigned!"); - EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); - unsigned int i, j; - for (i = 0, j = CCInfo.getFirstByValReg(); j <= X86::R9; i++, j++) { - SDValue Const = DAG.getConstant(8*i, MVT::i64); - SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const); - SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, - MachinePointerInfo(), - false, false, 0); - MemOpChains.push_back(Load.getValue(1)); - RegsToPass.push_back(std::make_pair(j, Load)); + RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); + if (isVarArg && IsWin64) { + // Win64 ABI requires argument XMM reg to be copied to the corresponding + // shadow reg if callee is a varargs function. + unsigned ShadowReg = 0; + switch (VA.getLocReg()) { + case X86::XMM0: ShadowReg = X86::RCX; break; + case X86::XMM1: ShadowReg = X86::RDX; break; + case X86::XMM2: ShadowReg = X86::R8; break; + case X86::XMM3: ShadowReg = X86::R9; break; } - CCInfo.clearFirstByValReg(); - } else { + if (ShadowReg) + RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); + } else { // Usual case: not byval. RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); - if (isVarArg && IsWin64) { - // Win64 ABI requires argument XMM reg to be copied to the corresponding - // shadow reg if callee is a varargs function. - unsigned ShadowReg = 0; - switch (VA.getLocReg()) { - case X86::XMM0: ShadowReg = X86::RCX; break; - case X86::XMM1: ShadowReg = X86::RDX; break; - case X86::XMM2: ShadowReg = X86::R8; break; - case X86::XMM3: ShadowReg = X86::R9; break; - } - if (ShadowReg) - RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); - } } } else if (!IsSibcall && (!isTailCall || isByVal)) { assert(VA.isMemLoc()); @@ -2455,47 +2440,6 @@ return Offset; } -/// HandleByVal - Every parameter *after* a byval parameter is passed -/// on the stack. Remember the next parameter register to allocate, -/// and then confiscate the rest of the parameter registers to insure -/// this. -void -X86TargetLowering::HandleByVal(CCState *State, unsigned &size) const { - // X86_32 passes all parameters on the stack, byval or whatever. - // X86_64 does not split parameters between registers and memory; if - // the parameter does not fit entirely inside the remaining - // parameter registers, it goes on the stack. - static const unsigned RegList2[] = { - X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 - }; - - if (!Subtarget->is64Bit()) - return; - - if (size > 16) // X86_64 aggregates > 16 bytes are passed in memory. - return; - - unsigned reg = State->getFirstUnallocated(RegList2, 6); - - if (reg == 6) // Out of regs to allocate. - return; - - // We expect the size to be 32 bits, or some non-zero multiple of 64 bits. - unsigned nregs = size / 8; - if (nregs == 0) nregs=1; // 32-bit case. - - unsigned regs_available = 6 - reg; - - if (nregs <= regs_available) { - size = 0; - State->setFirstByValReg(RegList2[reg]); - while (nregs--) { - State->AllocateReg(RegList2[reg]); - reg++; - } - } -} - /// MatchingStackOffset - Return true if the given stack call argument is /// already available in the same position (relatively) of the caller's /// incoming argument stack. @@ -2660,7 +2604,7 @@ } CCInfo.AnalyzeCallOperands(Outs, CC_X86); - if (ArgLocs.size()) { + if (CCInfo.getNextStackOffset()) { MachineFunction &MF = DAG.getMachineFunction(); if (MF.getInfo()->getBytesToPopOnReturn()) return false; @@ -2677,8 +2621,6 @@ ISD::ArgFlagsTy Flags = Outs[i].Flags; if (VA.getLocInfo() == CCValAssign::Indirect) return false; - if (Flags.isByVal()) - return false; if (!VA.isRegLoc()) { if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, MFI, MRI, TII)) @@ -11121,6 +11063,13 @@ return SDValue(); } +/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index +/// generation and convert it from being a bunch of shuffles and extracts +/// to a simple store and scalar loads to extract the elements. +static SDValue PerformVectorZeroExtendCombine(SDNode *N, SelectionDAG &DAG) { + return SDValue(); +} + /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) { @@ -12181,6 +12130,9 @@ case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); + case X86ISD::PMOVZXBW: + case X86ISD::PMOVZXWD: + case X86ISD::PMOVZXDQ: return PerformVectorZeroExtendCombine(N, DAG); case X86ISD::SHUFPS: // Handle all target specific shuffles case X86ISD::SHUFPD: case X86ISD::PALIGN: Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=131469&r1=131468&r2=131469&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue May 17 11:59:46 2011 @@ -263,6 +263,10 @@ PUNPCKHDQ, PUNPCKHQDQ, + PMOVZXBW, + PMOVZXWD, + PMOVZXDQ, + // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, // according to %al. An operator is needed so that this can be expanded // with control flow. @@ -728,8 +732,6 @@ // Call lowering helpers. - void HandleByVal(CCState *, unsigned &) const; - /// IsEligibleForTailCallOptimization - Check whether the call is eligible /// for tail call optimization. Targets which want to do tail call /// optimization should implement this function. From eli.friedman at gmail.com Tue May 17 13:02:22 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 17 May 2011 18:02:22 -0000 Subject: [llvm-commits] [llvm] r131471 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h Message-ID: <20110517180222.F03C32A6C12C@llvm.org> Author: efriedma Date: Tue May 17 13:02:22 2011 New Revision: 131471 URL: http://llvm.org/viewvc/llvm-project?rev=131471&view=rev Log: Clean up the mess created by r131467+r131469. Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=131471&r1=131470&r2=131471&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue May 17 13:02:22 2011 @@ -2104,8 +2104,6 @@ } if (ShadowReg) RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); - } else { // Usual case: not byval. - RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); } } else if (!IsSibcall && (!isTailCall || isByVal)) { assert(VA.isMemLoc()); @@ -11063,13 +11061,6 @@ return SDValue(); } -/// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index -/// generation and convert it from being a bunch of shuffles and extracts -/// to a simple store and scalar loads to extract the elements. -static SDValue PerformVectorZeroExtendCombine(SDNode *N, SelectionDAG &DAG) { - return SDValue(); -} - /// PerformSELECTCombine - Do target-specific dag combines on SELECT nodes. static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, const X86Subtarget *Subtarget) { @@ -12130,9 +12121,6 @@ case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); - case X86ISD::PMOVZXBW: - case X86ISD::PMOVZXWD: - case X86ISD::PMOVZXDQ: return PerformVectorZeroExtendCombine(N, DAG); case X86ISD::SHUFPS: // Handle all target specific shuffles case X86ISD::SHUFPD: case X86ISD::PALIGN: Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=131471&r1=131470&r2=131471&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue May 17 13:02:22 2011 @@ -263,10 +263,6 @@ PUNPCKHDQ, PUNPCKHQDQ, - PMOVZXBW, - PMOVZXWD, - PMOVZXDQ, - // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack, // according to %al. An operator is needed so that this can be expanded // with control flow. From eli.friedman at gmail.com Tue May 17 13:29:03 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 17 May 2011 18:29:03 -0000 Subject: [llvm-commits] [llvm] r131474 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fast-isel-call.ll test/CodeGen/X86/fast-isel-extract.ll Message-ID: <20110517182903.397A22A6C12C@llvm.org> Author: efriedma Date: Tue May 17 13:29:03 2011 New Revision: 131474 URL: http://llvm.org/viewvc/llvm-project?rev=131474&view=rev Log: Add x86 fast-isel for calls returning first-class aggregates. rdar://9435872. This is r131438 with a couple small fixes. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/test/CodeGen/X86/fast-isel-call.ll llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=131474&r1=131473&r2=131474&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue May 17 13:29:03 2011 @@ -1414,12 +1414,14 @@ if (Subtarget->IsCalleePop(isVarArg, CC)) return false; - // Handle *simple* calls for now. - const Type *RetTy = CS.getType(); - MVT RetVT; - if (RetTy->isVoidTy()) - RetVT = MVT::isVoid; - else if (!isTypeLegal(RetTy, RetVT, true)) + // Check whether the function can return without sret-demotion. + SmallVector Outs; + SmallVector Offsets; + GetReturnInfo(I->getType(), CS.getAttributes().getRetAttributes(), + Outs, TLI, &Offsets); + bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), + FTy->isVarArg(), Outs, FTy->getContext()); + if (!CanLowerReturn) return false; // Materialize callee address in a register. FIXME: GV address can be @@ -1436,13 +1438,6 @@ } else return false; - // Allow calls which produce i1 results. - bool AndToI1 = false; - if (RetVT == MVT::i1) { - RetVT = MVT::i8; - AndToI1 = true; - } - // Deal with call operands first. SmallVector ArgVals; SmallVector Args; @@ -1697,63 +1692,73 @@ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp)) .addImm(NumBytes).addImm(NumBytesCallee); - // Now handle call return value (if any). + // Build info for return calling conv lowering code. + // FIXME: This is practically a copy-paste from TargetLowering::LowerCallTo. + SmallVector Ins; + SmallVector RetTys; + ComputeValueVTs(TLI, I->getType(), RetTys); + for (unsigned i = 0, e = RetTys.size(); i != e; ++i) { + EVT VT = RetTys[i]; + EVT RegisterVT = TLI.getRegisterType(I->getParent()->getContext(), VT); + unsigned NumRegs = TLI.getNumRegisters(I->getParent()->getContext(), VT); + for (unsigned j = 0; j != NumRegs; ++j) { + ISD::InputArg MyFlags; + MyFlags.VT = RegisterVT.getSimpleVT(); + MyFlags.Used = !CS.getInstruction()->use_empty(); + if (CS.paramHasAttr(0, Attribute::SExt)) + MyFlags.Flags.setSExt(); + if (CS.paramHasAttr(0, Attribute::ZExt)) + MyFlags.Flags.setZExt(); + if (CS.paramHasAttr(0, Attribute::InReg)) + MyFlags.Flags.setInReg(); + Ins.push_back(MyFlags); + } + } + + // Now handle call return values. SmallVector UsedRegs; - if (RetVT != MVT::isVoid) { - SmallVector RVLocs; - CCState CCInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); - CCInfo.AnalyzeCallResult(RetVT, RetCC_X86); - - // Copy all of the result registers out of their specified physreg. - assert(RVLocs.size() == 1 && "Can't handle multi-value calls!"); - EVT CopyVT = RVLocs[0].getValVT(); - TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); + SmallVector RVLocs; + CCState CCRetInfo(CC, false, TM, RVLocs, I->getParent()->getContext()); + unsigned ResultReg = FuncInfo.CreateRegs(I->getType()); + CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86); + for (unsigned i = 0; i != RVLocs.size(); ++i) { + EVT CopyVT = RVLocs[i].getValVT(); + unsigned CopyReg = ResultReg + i; // If this is a call to a function that returns an fp value on the x87 fp // stack, but where we prefer to use the value in xmm registers, copy it // out as F80 and use a truncate to move it from fp stack reg to xmm reg. - if ((RVLocs[0].getLocReg() == X86::ST0 || - RVLocs[0].getLocReg() == X86::ST1) && + if ((RVLocs[i].getLocReg() == X86::ST0 || + RVLocs[i].getLocReg() == X86::ST1) && isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { CopyVT = MVT::f80; - DstRC = X86::RFP80RegisterClass; + CopyReg = createResultReg(X86::RFP80RegisterClass); } - unsigned ResultReg = createResultReg(DstRC); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), - ResultReg).addReg(RVLocs[0].getLocReg()); - UsedRegs.push_back(RVLocs[0].getLocReg()); + CopyReg).addReg(RVLocs[i].getLocReg()); + UsedRegs.push_back(RVLocs[i].getLocReg()); - if (CopyVT != RVLocs[0].getValVT()) { + if (CopyVT != RVLocs[i].getValVT()) { // Round the F80 the right size, which also moves to the appropriate xmm // register. This is accomplished by storing the F80 value in memory and // then loading it back. Ewww... - EVT ResVT = RVLocs[0].getValVT(); + EVT ResVT = RVLocs[i].getValVT(); unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; unsigned MemSize = ResVT.getSizeInBits()/8; int FI = MFI.CreateStackObject(MemSize, MemSize, false); addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)), FI) - .addReg(ResultReg); - DstRC = ResVT == MVT::f32 - ? X86::FR32RegisterClass : X86::FR64RegisterClass; + .addReg(CopyReg); Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm; - ResultReg = createResultReg(DstRC); addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(Opc), ResultReg), FI); + TII.get(Opc), ResultReg + i), FI); } - - if (AndToI1) { - // Mask out all but lowest bit for some call which produces an i1. - unsigned AndResult = createResultReg(X86::GR8RegisterClass); - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, - TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1); - ResultReg = AndResult; - } - - UpdateValueMap(I, ResultReg); } + if (RVLocs.size()) + UpdateValueMap(I, ResultReg, RVLocs.size()); + // Set all unused physreg defs as dead. static_cast(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); Modified: llvm/trunk/test/CodeGen/X86/fast-isel-call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-call.ll?rev=131474&r1=131473&r2=131474&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-call.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-call.ll Tue May 17 13:29:03 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -fast-isel -march=x86 | grep and +; RUN: llc < %s -fast-isel -march=x86 | FileCheck %s define i32 @t() nounwind { tak: @@ -8,6 +8,8 @@ ret i32 1 BB2: ret i32 0 +; CHECK: calll +; CHECK-NEXT: testb $1 } declare i1 @foo() zeroext nounwind Modified: llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll?rev=131474&r1=131473&r2=131474&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-extract.ll Tue May 17 13:29:03 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 | FileCheck %s +; RUN: llc < %s -mtriple x86_64-apple-darwin11 -O0 -fast-isel-abort | FileCheck %s %struct.x = type { i64, i64 } %addovf = type { i32, i1 } From grosbach at apple.com Tue May 17 13:29:21 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 17 May 2011 18:29:21 -0000 Subject: [llvm-commits] [llvm] r131475 - in /llvm/trunk/include/llvm/CodeGen: MachineInstrBuilder.h MachineOperand.h Message-ID: <20110517182922.031DE2A6C12C@llvm.org> Author: grosbach Date: Tue May 17 13:29:21 2011 New Revision: 131475 URL: http://llvm.org/viewvc/llvm-project?rev=131475&view=rev Log: Frame indices are signed. Update MachineOperand methods accordingly. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h llvm/trunk/include/llvm/CodeGen/MachineOperand.h Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=131475&r1=131474&r2=131475&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Tue May 17 13:29:21 2011 @@ -88,7 +88,7 @@ return *this; } - const MachineInstrBuilder &addFrameIndex(unsigned Idx) const { + const MachineInstrBuilder &addFrameIndex(int Idx) const { MI->addOperand(MachineOperand::CreateFI(Idx)); return *this; } Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=131475&r1=131474&r2=131475&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Tue May 17 13:29:21 2011 @@ -473,7 +473,7 @@ Op.setTargetFlags(TargetFlags); return Op; } - static MachineOperand CreateFI(unsigned Idx) { + static MachineOperand CreateFI(int Idx) { MachineOperand Op(MachineOperand::MO_FrameIndex); Op.setIndex(Idx); return Op; From wangmp at apple.com Tue May 17 13:33:37 2011 From: wangmp at apple.com (Mon P Wang) Date: Tue, 17 May 2011 18:33:37 -0000 Subject: [llvm-commits] [llvm] r131476 - /llvm/trunk/lib/Target/X86/X86Subtarget.cpp Message-ID: <20110517183337.7F7082A6C12C@llvm.org> Author: wangmp Date: Tue May 17 13:33:37 2011 New Revision: 131476 URL: http://llvm.org/viewvc/llvm-project?rev=131476&view=rev Log: Enable autodetect of popcnt Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=131476&r1=131475&r2=131476&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Tue May 17 13:33:37 2011 @@ -265,6 +265,7 @@ HasCLMUL = IsIntel && ((ECX >> 1) & 0x1); HasFMA3 = IsIntel && ((ECX >> 12) & 0x1); + HasPOPCNT = IsIntel && ((ECX >> 23) & 0x1); HasAES = IsIntel && ((ECX >> 25) & 0x1); if (IsIntel || IsAMD) { From gkistanova at gmail.com Tue May 17 14:06:43 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Tue, 17 May 2011 19:06:43 -0000 Subject: [llvm-commits] [llvm] r131477 - in /llvm/trunk/test/CodeGen: Generic/2011-02-12-shuffle.ll X86/2011-02-12-shuffle.ll Message-ID: <20110517190643.F3AA92A6C12C@llvm.org> Author: gkistanova Date: Tue May 17 14:06:43 2011 New Revision: 131477 URL: http://llvm.org/viewvc/llvm-project?rev=131477&view=rev Log: Move test for appropriate directory. Added: llvm/trunk/test/CodeGen/X86/2011-02-12-shuffle.ll Removed: llvm/trunk/test/CodeGen/Generic/2011-02-12-shuffle.ll Removed: llvm/trunk/test/CodeGen/Generic/2011-02-12-shuffle.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/2011-02-12-shuffle.ll?rev=131476&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/2011-02-12-shuffle.ll (original) +++ llvm/trunk/test/CodeGen/Generic/2011-02-12-shuffle.ll (removed) @@ -1,32 +0,0 @@ -; RUN: llc < %s -; PR9165 - -target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" -target triple = "i686-pc-win32" - -define void @m_387() nounwind { -entry: - br i1 undef, label %if.end, label %UnifiedReturnBlock - -if.end: ; preds = %entry - %tmp1067 = load <16 x i32> addrspace(1)* null, align 64 - %tmp1082 = shufflevector <16 x i32> , - <16 x i32> %tmp1067, - <16 x i32> - - %tmp1100 = shufflevector <16 x i32> %tmp1082, - <16 x i32> %tmp1067, - <16 x i32> - - %tmp1112 = shufflevector <16 x i32> %tmp1100, - <16 x i32> %tmp1067, - <16 x i32> - - store <16 x i32> %tmp1112, <16 x i32> addrspace(1)* undef, align 64 - - ret void - -UnifiedReturnBlock: ; preds = %entry - ret void -} - Added: llvm/trunk/test/CodeGen/X86/2011-02-12-shuffle.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-02-12-shuffle.ll?rev=131477&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-02-12-shuffle.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-02-12-shuffle.ll Tue May 17 14:06:43 2011 @@ -0,0 +1,32 @@ +; RUN: llc < %s +; PR9165 + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-v128:128:128-a0:0:64-f80:32:32-n8:16:32" +target triple = "i686-pc-win32" + +define void @m_387() nounwind { +entry: + br i1 undef, label %if.end, label %UnifiedReturnBlock + +if.end: ; preds = %entry + %tmp1067 = load <16 x i32> addrspace(1)* null, align 64 + %tmp1082 = shufflevector <16 x i32> , + <16 x i32> %tmp1067, + <16 x i32> + + %tmp1100 = shufflevector <16 x i32> %tmp1082, + <16 x i32> %tmp1067, + <16 x i32> + + %tmp1112 = shufflevector <16 x i32> %tmp1100, + <16 x i32> %tmp1067, + <16 x i32> + + store <16 x i32> %tmp1112, <16 x i32> addrspace(1)* undef, align 64 + + ret void + +UnifiedReturnBlock: ; preds = %entry + ret void +} + From dpatel at apple.com Tue May 17 14:43:06 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 17 May 2011 19:43:06 -0000 Subject: [llvm-commits] [llvm] r131480 - /llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Message-ID: <20110517194306.EC5212A6C12C@llvm.org> Author: dpatel Date: Tue May 17 14:43:06 2011 New Revision: 131480 URL: http://llvm.org/viewvc/llvm-project?rev=131480&view=rev Log: Preserve line number information. Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=131480&r1=131479&r2=131480&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Tue May 17 14:43:06 2011 @@ -180,7 +180,8 @@ BasicBlock *NewBB = BasicBlock::Create(TI->getContext(), TIBB->getName() + "." + DestBB->getName() + "_crit_edge"); // Create our unconditional branch. - BranchInst::Create(DestBB, NewBB); + BranchInst *NewBI = BranchInst::Create(DestBB, NewBB); + NewBI->setDebugLoc(TI->getDebugLoc()); // Branch to the new block, breaking the edge. TI->setSuccessor(SuccNum, NewBB); From dpatel at apple.com Tue May 17 14:43:38 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 17 May 2011 19:43:38 -0000 Subject: [llvm-commits] [llvm] r131481 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp Message-ID: <20110517194338.E0F2D2A6C12C@llvm.org> Author: dpatel Date: Tue May 17 14:43:38 2011 New Revision: 131481 URL: http://llvm.org/viewvc/llvm-project?rev=131481&view=rev Log: Set debug loc for new load instruction. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=131481&r1=131480&r2=131481&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue May 17 14:43:38 2011 @@ -1576,6 +1576,9 @@ if (MDNode *Tag = LI->getMetadata(LLVMContext::MD_tbaa)) NewLoad->setMetadata(LLVMContext::MD_tbaa, Tag); + // Transfer DebugLoc. + NewLoad->setDebugLoc(LI->getDebugLoc()); + // Add the newly created load. ValuesPerBlock.push_back(AvailableValueInBlock::get(UnavailablePred, NewLoad)); From dpatel at apple.com Tue May 17 15:00:02 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 17 May 2011 20:00:02 -0000 Subject: [llvm-commits] [llvm] r131482 - /llvm/trunk/lib/Transforms/Scalar/GVN.cpp Message-ID: <20110517200002.AAAB32A6C12C@llvm.org> Author: dpatel Date: Tue May 17 15:00:02 2011 New Revision: 131482 URL: http://llvm.org/viewvc/llvm-project?rev=131482&view=rev Log: Preserve line number information. Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=131482&r1=131481&r2=131482&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Tue May 17 15:00:02 2011 @@ -2102,6 +2102,7 @@ PREInstr->insertBefore(PREPred->getTerminator()); PREInstr->setName(CurInst->getName() + ".pre"); + PREInstr->setDebugLoc(CurInst->getDebugLoc()); predMap[PREPred] = PREInstr; VN.add(PREInstr, ValNo); ++NumGVNPRE; From tonic at nondot.org Tue May 17 15:48:40 2011 From: tonic at nondot.org (Tanya Lattner) Date: Tue, 17 May 2011 20:48:40 -0000 Subject: [llvm-commits] [llvm] r131488 - in /llvm/trunk: lib/Target/ARM/ARMPerfectShuffle.h test/CodeGen/ARM/vrev.ll utils/PerfectShuffle/PerfectShuffle.cpp Message-ID: <20110517204840.731902A6C12C@llvm.org> Author: tbrethou Date: Tue May 17 15:48:40 2011 New Revision: 131488 URL: http://llvm.org/viewvc/llvm-project?rev=131488&view=rev Log: vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. Modified: llvm/trunk/lib/Target/ARM/ARMPerfectShuffle.h llvm/trunk/test/CodeGen/ARM/vrev.ll llvm/trunk/utils/PerfectShuffle/PerfectShuffle.cpp Modified: llvm/trunk/lib/Target/ARM/ARMPerfectShuffle.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMPerfectShuffle.h?rev=131488&r1=131487&r2=131488&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMPerfectShuffle.h (original) +++ llvm/trunk/lib/Target/ARM/ARMPerfectShuffle.h Tue May 17 15:48:40 2011 @@ -14,6573 +14,6574 @@ // 31 entries have cost 0 // 242 entries have cost 1 -// 1447 entries have cost 2 -// 3602 entries have cost 3 -// 1237 entries have cost 4 -// 2 entries have cost 5 +// 1435 entries have cost 2 +// 3712 entries have cost 3 +// 1140 entries have cost 4 +// 1 entries have cost 5 // This table is 6561*4 = 26244 bytes in size. static const unsigned PerfectShuffleTable[6561+1] = { - 135053414U, // <0,0,0,0>: Cost 1 vdup0 LHS - 1543503974U, // <0,0,0,1>: Cost 2 vext2 <0,0,0,0>, LHS - 2618572962U, // <0,0,0,2>: Cost 3 vext2 <0,2,0,0>, <0,2,0,0> - 2568054923U, // <0,0,0,3>: Cost 3 vext1 <3,0,0,0>, <3,0,0,0> - 1476398390U, // <0,0,0,4>: Cost 2 vext1 <0,0,0,0>, RHS - 2550140624U, // <0,0,0,5>: Cost 3 vext1 <0,0,0,0>, <5,1,7,3> - 2550141434U, // <0,0,0,6>: Cost 3 vext1 <0,0,0,0>, <6,2,7,3> - 2591945711U, // <0,0,0,7>: Cost 3 vext1 <7,0,0,0>, <7,0,0,0> - 135053414U, // <0,0,0,u>: Cost 1 vdup0 LHS - 2886516736U, // <0,0,1,0>: Cost 3 vzipl LHS, <0,0,0,0> - 1812775014U, // <0,0,1,1>: Cost 2 vzipl LHS, LHS - 1618133094U, // <0,0,1,2>: Cost 2 vext3 <1,2,3,0>, LHS - 2625209292U, // <0,0,1,3>: Cost 3 vext2 <1,3,0,0>, <1,3,0,0> - 2886558034U, // <0,0,1,4>: Cost 3 vzipl LHS, <0,4,1,5> - 2617246864U, // <0,0,1,5>: Cost 3 vext2 <0,0,0,0>, <1,5,3,7> - 3659723031U, // <0,0,1,6>: Cost 4 vext1 <6,0,0,1>, <6,0,0,1> - 2591953904U, // <0,0,1,7>: Cost 3 vext1 <7,0,0,1>, <7,0,0,1> - 1812775581U, // <0,0,1,u>: Cost 2 vzipl LHS, LHS - 3020734464U, // <0,0,2,0>: Cost 3 vtrnl LHS, <0,0,0,0> - 3020734474U, // <0,0,2,1>: Cost 3 vtrnl LHS, <0,0,1,1> - 1946992742U, // <0,0,2,2>: Cost 2 vtrnl LHS, LHS - 2631181989U, // <0,0,2,3>: Cost 3 vext2 <2,3,0,0>, <2,3,0,0> - 3020734668U, // <0,0,2,4>: Cost 3 vtrnl LHS, <0,2,4,6> - 3826550569U, // <0,0,2,5>: Cost 4 vuzpl <0,2,0,2>, <2,4,5,6> - 2617247674U, // <0,0,2,6>: Cost 3 vext2 <0,0,0,0>, <2,6,3,7> - 2591962097U, // <0,0,2,7>: Cost 3 vext1 <7,0,0,2>, <7,0,0,2> - 1946992796U, // <0,0,2,u>: Cost 2 vtrnl LHS, LHS - 2635163787U, // <0,0,3,0>: Cost 3 vext2 <3,0,0,0>, <3,0,0,0> - 2686419196U, // <0,0,3,1>: Cost 3 vext3 <0,3,1,0>, <0,3,1,0> - 2686492933U, // <0,0,3,2>: Cost 3 vext3 <0,3,2,0>, <0,3,2,0> - 2617248156U, // <0,0,3,3>: Cost 3 vext2 <0,0,0,0>, <3,3,3,3> - 2617248258U, // <0,0,3,4>: Cost 3 vext2 <0,0,0,0>, <3,4,5,6> - 3826551298U, // <0,0,3,5>: Cost 4 vuzpl <0,2,0,2>, <3,4,5,6> - 3690990200U, // <0,0,3,6>: Cost 4 vext2 <0,0,0,0>, <3,6,0,7> - 3713551042U, // <0,0,3,7>: Cost 4 vext2 <3,7,0,0>, <3,7,0,0> - 2635163787U, // <0,0,3,u>: Cost 3 vext2 <3,0,0,0>, <3,0,0,0> - 2617248658U, // <0,0,4,0>: Cost 3 vext2 <0,0,0,0>, <4,0,5,1> - 2888450150U, // <0,0,4,1>: Cost 3 vzipl <0,4,1,5>, LHS - 3021570150U, // <0,0,4,2>: Cost 3 vtrnl <0,2,4,6>, LHS - 3641829519U, // <0,0,4,3>: Cost 4 vext1 <3,0,0,4>, <3,0,0,4> - 3021570252U, // <0,0,4,4>: Cost 3 vtrnl <0,2,4,6>, <0,2,4,6> - 1543507254U, // <0,0,4,5>: Cost 2 vext2 <0,0,0,0>, RHS - 2752810294U, // <0,0,4,6>: Cost 3 vuzpl <0,2,0,2>, RHS - 3786998152U, // <0,0,4,7>: Cost 4 vext3 <4,7,5,0>, <0,4,7,5> - 1543507497U, // <0,0,4,u>: Cost 2 vext2 <0,0,0,0>, RHS - 2684354972U, // <0,0,5,0>: Cost 3 vext3 <0,0,0,0>, <0,5,0,7> - 2617249488U, // <0,0,5,1>: Cost 3 vext2 <0,0,0,0>, <5,1,7,3> - 3765617070U, // <0,0,5,2>: Cost 4 vext3 <1,2,3,0>, <0,5,2,7> - 3635865780U, // <0,0,5,3>: Cost 4 vext1 <2,0,0,5>, <3,0,4,5> - 2617249734U, // <0,0,5,4>: Cost 3 vext2 <0,0,0,0>, <5,4,7,6> - 2617249796U, // <0,0,5,5>: Cost 3 vext2 <0,0,0,0>, <5,5,5,5> - 2718712274U, // <0,0,5,6>: Cost 3 vext3 <5,6,7,0>, <0,5,6,7> - 2617249960U, // <0,0,5,7>: Cost 3 vext2 <0,0,0,0>, <5,7,5,7> - 2720039396U, // <0,0,5,u>: Cost 3 vext3 <5,u,7,0>, <0,5,u,7> - 2684355053U, // <0,0,6,0>: Cost 3 vext3 <0,0,0,0>, <0,6,0,7> - 3963609190U, // <0,0,6,1>: Cost 4 vzipl <0,6,2,7>, LHS - 2617250298U, // <0,0,6,2>: Cost 3 vext2 <0,0,0,0>, <6,2,7,3> - 3796435464U, // <0,0,6,3>: Cost 4 vext3 <6,3,7,0>, <0,6,3,7> - 3659762998U, // <0,0,6,4>: Cost 4 vext1 <6,0,0,6>, RHS - 3659763810U, // <0,0,6,5>: Cost 4 vext1 <6,0,0,6>, <5,6,7,0> - 2617250616U, // <0,0,6,6>: Cost 3 vext2 <0,0,0,0>, <6,6,6,6> - 2657727309U, // <0,0,6,7>: Cost 3 vext2 <6,7,0,0>, <6,7,0,0> - 2658390942U, // <0,0,6,u>: Cost 3 vext2 <6,u,0,0>, <6,u,0,0> - 2659054575U, // <0,0,7,0>: Cost 3 vext2 <7,0,0,0>, <7,0,0,0> - 3635880854U, // <0,0,7,1>: Cost 4 vext1 <2,0,0,7>, <1,2,3,0> - 3635881401U, // <0,0,7,2>: Cost 4 vext1 <2,0,0,7>, <2,0,0,7> - 3734787298U, // <0,0,7,3>: Cost 4 vext2 <7,3,0,0>, <7,3,0,0> - 2617251174U, // <0,0,7,4>: Cost 3 vext2 <0,0,0,0>, <7,4,5,6> - 3659772002U, // <0,0,7,5>: Cost 4 vext1 <6,0,0,7>, <5,6,7,0> - 3659772189U, // <0,0,7,6>: Cost 4 vext1 <6,0,0,7>, <6,0,0,7> - 2617251436U, // <0,0,7,7>: Cost 3 vext2 <0,0,0,0>, <7,7,7,7> - 2659054575U, // <0,0,7,u>: Cost 3 vext2 <7,0,0,0>, <7,0,0,0> - 135053414U, // <0,0,u,0>: Cost 1 vdup0 LHS - 1817419878U, // <0,0,u,1>: Cost 2 vzipl LHS, LHS - 1947435110U, // <0,0,u,2>: Cost 2 vtrnl LHS, LHS - 2568120467U, // <0,0,u,3>: Cost 3 vext1 <3,0,0,u>, <3,0,0,u> - 1476463926U, // <0,0,u,4>: Cost 2 vext1 <0,0,0,u>, RHS - 1543510170U, // <0,0,u,5>: Cost 2 vext2 <0,0,0,0>, RHS - 2752813210U, // <0,0,u,6>: Cost 3 vuzpl <0,2,0,2>, RHS - 2592011255U, // <0,0,u,7>: Cost 3 vext1 <7,0,0,u>, <7,0,0,u> - 135053414U, // <0,0,u,u>: Cost 1 vdup0 LHS - 2618581002U, // <0,1,0,0>: Cost 3 vext2 <0,2,0,1>, <0,0,1,1> - 1557446758U, // <0,1,0,1>: Cost 2 vext2 <2,3,0,1>, LHS - 2618581155U, // <0,1,0,2>: Cost 3 vext2 <0,2,0,1>, <0,2,0,1> - 2690548468U, // <0,1,0,3>: Cost 3 vext3 <1,0,3,0>, <1,0,3,0> - 2626543954U, // <0,1,0,4>: Cost 3 vext2 <1,5,0,1>, <0,4,1,5> - 4094985216U, // <0,1,0,5>: Cost 4 vtrnl <0,2,0,2>, <1,3,5,7> - 2592019278U, // <0,1,0,6>: Cost 3 vext1 <7,0,1,0>, <6,7,0,1> - 2592019448U, // <0,1,0,7>: Cost 3 vext1 <7,0,1,0>, <7,0,1,0> - 1557447325U, // <0,1,0,u>: Cost 2 vext2 <2,3,0,1>, LHS - 1476476938U, // <0,1,1,0>: Cost 2 vext1 <0,0,1,1>, <0,0,1,1> - 2886517556U, // <0,1,1,1>: Cost 3 vzipl LHS, <1,1,1,1> - 2886517654U, // <0,1,1,2>: Cost 3 vzipl LHS, <1,2,3,0> - 2886517720U, // <0,1,1,3>: Cost 3 vzipl LHS, <1,3,1,3> - 1476480310U, // <0,1,1,4>: Cost 2 vext1 <0,0,1,1>, RHS - 2886558864U, // <0,1,1,5>: Cost 3 vzipl LHS, <1,5,3,7> - 2550223354U, // <0,1,1,6>: Cost 3 vext1 <0,0,1,1>, <6,2,7,3> - 2550223856U, // <0,1,1,7>: Cost 3 vext1 <0,0,1,1>, <7,0,0,1> - 1476482862U, // <0,1,1,u>: Cost 2 vext1 <0,0,1,1>, LHS - 1494401126U, // <0,1,2,0>: Cost 2 vext1 <3,0,1,2>, LHS - 3020735284U, // <0,1,2,1>: Cost 3 vtrnl LHS, <1,1,1,1> - 2562172349U, // <0,1,2,2>: Cost 3 vext1 <2,0,1,2>, <2,0,1,2> - 835584U, // <0,1,2,3>: Cost 0 copy LHS - 1494404406U, // <0,1,2,4>: Cost 2 vext1 <3,0,1,2>, RHS - 3020735488U, // <0,1,2,5>: Cost 3 vtrnl LHS, <1,3,5,7> - 2631190458U, // <0,1,2,6>: Cost 3 vext2 <2,3,0,1>, <2,6,3,7> - 1518294010U, // <0,1,2,7>: Cost 2 vext1 <7,0,1,2>, <7,0,1,2> - 835584U, // <0,1,2,u>: Cost 0 copy LHS - 2692318156U, // <0,1,3,0>: Cost 3 vext3 <1,3,0,0>, <1,3,0,0> - 2691875800U, // <0,1,3,1>: Cost 3 vext3 <1,2,3,0>, <1,3,1,3> - 2691875806U, // <0,1,3,2>: Cost 3 vext3 <1,2,3,0>, <1,3,2,0> - 2692539367U, // <0,1,3,3>: Cost 3 vext3 <1,3,3,0>, <1,3,3,0> - 2562182454U, // <0,1,3,4>: Cost 3 vext1 <2,0,1,3>, RHS - 2691875840U, // <0,1,3,5>: Cost 3 vext3 <1,2,3,0>, <1,3,5,7> - 2692760578U, // <0,1,3,6>: Cost 3 vext3 <1,3,6,0>, <1,3,6,0> - 2639817411U, // <0,1,3,7>: Cost 3 vext2 <3,7,0,1>, <3,7,0,1> - 2691875863U, // <0,1,3,u>: Cost 3 vext3 <1,2,3,0>, <1,3,u,3> - 2568159334U, // <0,1,4,0>: Cost 3 vext1 <3,0,1,4>, LHS - 4095312692U, // <0,1,4,1>: Cost 4 vtrnl <0,2,4,6>, <1,1,1,1> - 2568160934U, // <0,1,4,2>: Cost 3 vext1 <3,0,1,4>, <2,3,0,1> - 2568161432U, // <0,1,4,3>: Cost 3 vext1 <3,0,1,4>, <3,0,1,4> - 2568162614U, // <0,1,4,4>: Cost 3 vext1 <3,0,1,4>, RHS - 1557450038U, // <0,1,4,5>: Cost 2 vext2 <2,3,0,1>, RHS - 2754235702U, // <0,1,4,6>: Cost 3 vuzpl <0,4,1,5>, RHS - 2592052220U, // <0,1,4,7>: Cost 3 vext1 <7,0,1,4>, <7,0,1,4> - 1557450281U, // <0,1,4,u>: Cost 2 vext2 <2,3,0,1>, RHS - 3765617775U, // <0,1,5,0>: Cost 4 vext3 <1,2,3,0>, <1,5,0,1> - 2647781007U, // <0,1,5,1>: Cost 3 vext2 <5,1,0,1>, <5,1,0,1> - 3704934138U, // <0,1,5,2>: Cost 4 vext2 <2,3,0,1>, <5,2,3,0> - 2691875984U, // <0,1,5,3>: Cost 3 vext3 <1,2,3,0>, <1,5,3,7> - 2657734598U, // <0,1,5,4>: Cost 3 vext2 <6,7,0,1>, <5,4,7,6> - 2650435539U, // <0,1,5,5>: Cost 3 vext2 <5,5,0,1>, <5,5,0,1> - 2651099172U, // <0,1,5,6>: Cost 3 vext2 <5,6,0,1>, <5,6,0,1> - 2651762805U, // <0,1,5,7>: Cost 3 vext2 <5,7,0,1>, <5,7,0,1> - 2691876029U, // <0,1,5,u>: Cost 3 vext3 <1,2,3,0>, <1,5,u,7> - 2592063590U, // <0,1,6,0>: Cost 3 vext1 <7,0,1,6>, LHS - 3765617871U, // <0,1,6,1>: Cost 4 vext3 <1,2,3,0>, <1,6,1,7> - 2654417337U, // <0,1,6,2>: Cost 3 vext2 <6,2,0,1>, <6,2,0,1> - 3765617889U, // <0,1,6,3>: Cost 4 vext3 <1,2,3,0>, <1,6,3,7> - 2592066870U, // <0,1,6,4>: Cost 3 vext1 <7,0,1,6>, RHS - 3765617907U, // <0,1,6,5>: Cost 4 vext3 <1,2,3,0>, <1,6,5,7> - 2657071869U, // <0,1,6,6>: Cost 3 vext2 <6,6,0,1>, <6,6,0,1> - 1583993678U, // <0,1,6,7>: Cost 2 vext2 <6,7,0,1>, <6,7,0,1> - 1584657311U, // <0,1,6,u>: Cost 2 vext2 <6,u,0,1>, <6,u,0,1> - 2657735672U, // <0,1,7,0>: Cost 3 vext2 <6,7,0,1>, <7,0,1,0> - 2657735808U, // <0,1,7,1>: Cost 3 vext2 <6,7,0,1>, <7,1,7,1> - 2631193772U, // <0,1,7,2>: Cost 3 vext2 <2,3,0,1>, <7,2,3,0> - 2661053667U, // <0,1,7,3>: Cost 3 vext2 <7,3,0,1>, <7,3,0,1> - 2657736038U, // <0,1,7,4>: Cost 3 vext2 <6,7,0,1>, <7,4,5,6> - 3721524621U, // <0,1,7,5>: Cost 4 vext2 <5,1,0,1>, <7,5,1,0> - 2657736158U, // <0,1,7,6>: Cost 3 vext2 <6,7,0,1>, <7,6,1,0> - 2657736300U, // <0,1,7,7>: Cost 3 vext2 <6,7,0,1>, <7,7,7,7> - 2657736322U, // <0,1,7,u>: Cost 3 vext2 <6,7,0,1>, <7,u,1,2> - 1494450278U, // <0,1,u,0>: Cost 2 vext1 <3,0,1,u>, LHS - 1557452590U, // <0,1,u,1>: Cost 2 vext2 <2,3,0,1>, LHS - 2754238254U, // <0,1,u,2>: Cost 3 vuzpl <0,4,1,5>, LHS - 835584U, // <0,1,u,3>: Cost 0 copy LHS - 1494453558U, // <0,1,u,4>: Cost 2 vext1 <3,0,1,u>, RHS - 1557452954U, // <0,1,u,5>: Cost 2 vext2 <2,3,0,1>, RHS - 2754238618U, // <0,1,u,6>: Cost 3 vuzpl <0,4,1,5>, RHS - 1518343168U, // <0,1,u,7>: Cost 2 vext1 <7,0,1,u>, <7,0,1,u> - 835584U, // <0,1,u,u>: Cost 0 copy LHS - 2752299008U, // <0,2,0,0>: Cost 3 vuzpl LHS, <0,0,0,0> - 1544847462U, // <0,2,0,1>: Cost 2 vext2 <0,2,0,2>, LHS - 1678557286U, // <0,2,0,2>: Cost 2 vuzpl LHS, LHS - 2696521165U, // <0,2,0,3>: Cost 3 vext3 <2,0,3,0>, <2,0,3,0> - 2752340172U, // <0,2,0,4>: Cost 3 vuzpl LHS, <0,2,4,6> - 2691876326U, // <0,2,0,5>: Cost 3 vext3 <1,2,3,0>, <2,0,5,7> - 2618589695U, // <0,2,0,6>: Cost 3 vext2 <0,2,0,2>, <0,6,2,7> - 2592093185U, // <0,2,0,7>: Cost 3 vext1 <7,0,2,0>, <7,0,2,0> - 1678557340U, // <0,2,0,u>: Cost 2 vuzpl LHS, LHS - 2618589942U, // <0,2,1,0>: Cost 3 vext2 <0,2,0,2>, <1,0,3,2> - 2752299828U, // <0,2,1,1>: Cost 3 vuzpl LHS, <1,1,1,1> - 2886518376U, // <0,2,1,2>: Cost 3 vzipl LHS, <2,2,2,2> - 2752299766U, // <0,2,1,3>: Cost 3 vuzpl LHS, <1,0,3,2> - 2550295862U, // <0,2,1,4>: Cost 3 vext1 <0,0,2,1>, RHS - 2752340992U, // <0,2,1,5>: Cost 3 vuzpl LHS, <1,3,5,7> - 2886559674U, // <0,2,1,6>: Cost 3 vzipl LHS, <2,6,3,7> - 3934208106U, // <0,2,1,7>: Cost 4 vuzpr <7,0,1,2>, <0,1,2,7> - 2752340771U, // <0,2,1,u>: Cost 3 vuzpl LHS, <1,0,u,2> - 1476558868U, // <0,2,2,0>: Cost 2 vext1 <0,0,2,2>, <0,0,2,2> - 2226628029U, // <0,2,2,1>: Cost 3 vrev <2,0,1,2> - 2752300648U, // <0,2,2,2>: Cost 3 vuzpl LHS, <2,2,2,2> - 3020736114U, // <0,2,2,3>: Cost 3 vtrnl LHS, <2,2,3,3> - 1476562230U, // <0,2,2,4>: Cost 2 vext1 <0,0,2,2>, RHS - 2550304464U, // <0,2,2,5>: Cost 3 vext1 <0,0,2,2>, <5,1,7,3> - 2618591162U, // <0,2,2,6>: Cost 3 vext2 <0,2,0,2>, <2,6,3,7> - 2550305777U, // <0,2,2,7>: Cost 3 vext1 <0,0,2,2>, <7,0,0,2> - 1476564782U, // <0,2,2,u>: Cost 2 vext1 <0,0,2,2>, LHS - 2618591382U, // <0,2,3,0>: Cost 3 vext2 <0,2,0,2>, <3,0,1,2> - 2752301206U, // <0,2,3,1>: Cost 3 vuzpl LHS, <3,0,1,2> - 3826043121U, // <0,2,3,2>: Cost 4 vuzpl LHS, <3,1,2,3> - 2752301468U, // <0,2,3,3>: Cost 3 vuzpl LHS, <3,3,3,3> - 2618591746U, // <0,2,3,4>: Cost 3 vext2 <0,2,0,2>, <3,4,5,6> - 2752301570U, // <0,2,3,5>: Cost 3 vuzpl LHS, <3,4,5,6> - 3830688102U, // <0,2,3,6>: Cost 4 vuzpl LHS, <3,2,6,3> - 2698807012U, // <0,2,3,7>: Cost 3 vext3 <2,3,7,0>, <2,3,7,0> - 2752301269U, // <0,2,3,u>: Cost 3 vuzpl LHS, <3,0,u,2> - 2562261094U, // <0,2,4,0>: Cost 3 vext1 <2,0,2,4>, LHS - 4095313828U, // <0,2,4,1>: Cost 4 vtrnl <0,2,4,6>, <2,6,1,3> - 2226718152U, // <0,2,4,2>: Cost 3 vrev <2,0,2,4> - 2568235169U, // <0,2,4,3>: Cost 3 vext1 <3,0,2,4>, <3,0,2,4> - 2562264374U, // <0,2,4,4>: Cost 3 vext1 <2,0,2,4>, RHS - 1544850742U, // <0,2,4,5>: Cost 2 vext2 <0,2,0,2>, RHS - 1678560566U, // <0,2,4,6>: Cost 2 vuzpl LHS, RHS - 2592125957U, // <0,2,4,7>: Cost 3 vext1 <7,0,2,4>, <7,0,2,4> - 1678560584U, // <0,2,4,u>: Cost 2 vuzpl LHS, RHS - 2691876686U, // <0,2,5,0>: Cost 3 vext3 <1,2,3,0>, <2,5,0,7> - 2618592976U, // <0,2,5,1>: Cost 3 vext2 <0,2,0,2>, <5,1,7,3> - 3765618528U, // <0,2,5,2>: Cost 4 vext3 <1,2,3,0>, <2,5,2,7> - 3765618536U, // <0,2,5,3>: Cost 4 vext3 <1,2,3,0>, <2,5,3,6> - 2618593222U, // <0,2,5,4>: Cost 3 vext2 <0,2,0,2>, <5,4,7,6> - 2752303108U, // <0,2,5,5>: Cost 3 vuzpl LHS, <5,5,5,5> - 2618593378U, // <0,2,5,6>: Cost 3 vext2 <0,2,0,2>, <5,6,7,0> - 2824785206U, // <0,2,5,7>: Cost 3 vuzpr <1,0,3,2>, RHS - 2824785207U, // <0,2,5,u>: Cost 3 vuzpr <1,0,3,2>, RHS - 2752303950U, // <0,2,6,0>: Cost 3 vuzpl LHS, <6,7,0,1> - 3830690081U, // <0,2,6,1>: Cost 4 vuzpl LHS, <6,0,1,2> - 2618593786U, // <0,2,6,2>: Cost 3 vext2 <0,2,0,2>, <6,2,7,3> - 2691876794U, // <0,2,6,3>: Cost 3 vext3 <1,2,3,0>, <2,6,3,7> - 2752303990U, // <0,2,6,4>: Cost 3 vuzpl LHS, <6,7,4,5> - 3830690445U, // <0,2,6,5>: Cost 4 vuzpl LHS, <6,4,5,6> - 2752303928U, // <0,2,6,6>: Cost 3 vuzpl LHS, <6,6,6,6> - 2657743695U, // <0,2,6,7>: Cost 3 vext2 <6,7,0,2>, <6,7,0,2> - 2691876839U, // <0,2,6,u>: Cost 3 vext3 <1,2,3,0>, <2,6,u,7> - 2659070961U, // <0,2,7,0>: Cost 3 vext2 <7,0,0,2>, <7,0,0,2> - 2659734594U, // <0,2,7,1>: Cost 3 vext2 <7,1,0,2>, <7,1,0,2> - 3734140051U, // <0,2,7,2>: Cost 4 vext2 <7,2,0,2>, <7,2,0,2> - 2701166596U, // <0,2,7,3>: Cost 3 vext3 <2,7,3,0>, <2,7,3,0> - 2662389094U, // <0,2,7,4>: Cost 3 vext2 <7,5,0,2>, <7,4,5,6> - 2662389126U, // <0,2,7,5>: Cost 3 vext2 <7,5,0,2>, <7,5,0,2> - 3736794583U, // <0,2,7,6>: Cost 4 vext2 <7,6,0,2>, <7,6,0,2> - 2752304748U, // <0,2,7,7>: Cost 3 vuzpl LHS, <7,7,7,7> - 2659070961U, // <0,2,7,u>: Cost 3 vext2 <7,0,0,2>, <7,0,0,2> - 1476608026U, // <0,2,u,0>: Cost 2 vext1 <0,0,2,u>, <0,0,2,u> - 1544853294U, // <0,2,u,1>: Cost 2 vext2 <0,2,0,2>, LHS - 1678563118U, // <0,2,u,2>: Cost 2 vuzpl LHS, LHS - 3021178482U, // <0,2,u,3>: Cost 3 vtrnl LHS, <2,2,3,3> - 1476611382U, // <0,2,u,4>: Cost 2 vext1 <0,0,2,u>, RHS - 1544853658U, // <0,2,u,5>: Cost 2 vext2 <0,2,0,2>, RHS - 1678563482U, // <0,2,u,6>: Cost 2 vuzpl LHS, RHS - 2824785449U, // <0,2,u,7>: Cost 3 vuzpr <1,0,3,2>, RHS - 1678563172U, // <0,2,u,u>: Cost 2 vuzpl LHS, LHS - 2556329984U, // <0,3,0,0>: Cost 3 vext1 <1,0,3,0>, <0,0,0,0> - 2686421142U, // <0,3,0,1>: Cost 3 vext3 <0,3,1,0>, <3,0,1,2> - 2562303437U, // <0,3,0,2>: Cost 3 vext1 <2,0,3,0>, <2,0,3,0> - 4094986652U, // <0,3,0,3>: Cost 4 vtrnl <0,2,0,2>, <3,3,3,3> - 2556333366U, // <0,3,0,4>: Cost 3 vext1 <1,0,3,0>, RHS - 4094986754U, // <0,3,0,5>: Cost 4 vtrnl <0,2,0,2>, <3,4,5,6> - 3798796488U, // <0,3,0,6>: Cost 4 vext3 <6,7,3,0>, <3,0,6,7> - 3776530634U, // <0,3,0,7>: Cost 4 vext3 <3,0,7,0>, <3,0,7,0> - 2556335918U, // <0,3,0,u>: Cost 3 vext1 <1,0,3,0>, LHS - 2886518934U, // <0,3,1,0>: Cost 3 vzipl LHS, <3,0,1,2> - 2556338933U, // <0,3,1,1>: Cost 3 vext1 <1,0,3,1>, <1,0,3,1> - 2691877105U, // <0,3,1,2>: Cost 3 vext3 <1,2,3,0>, <3,1,2,3> - 2886519196U, // <0,3,1,3>: Cost 3 vzipl LHS, <3,3,3,3> - 2886519298U, // <0,3,1,4>: Cost 3 vzipl LHS, <3,4,5,6> - 4095740418U, // <0,3,1,5>: Cost 4 vtrnl <0,3,1,4>, <3,4,5,6> - 3659944242U, // <0,3,1,6>: Cost 4 vext1 <6,0,3,1>, <6,0,3,1> - 3769600286U, // <0,3,1,7>: Cost 4 vext3 <1,u,3,0>, <3,1,7,3> - 2886519582U, // <0,3,1,u>: Cost 3 vzipl LHS, <3,u,1,2> - 1482604646U, // <0,3,2,0>: Cost 2 vext1 <1,0,3,2>, LHS - 1482605302U, // <0,3,2,1>: Cost 2 vext1 <1,0,3,2>, <1,0,3,2> - 2556348008U, // <0,3,2,2>: Cost 3 vext1 <1,0,3,2>, <2,2,2,2> - 3020736924U, // <0,3,2,3>: Cost 3 vtrnl LHS, <3,3,3,3> - 1482607926U, // <0,3,2,4>: Cost 2 vext1 <1,0,3,2>, RHS - 3020737026U, // <0,3,2,5>: Cost 3 vtrnl LHS, <3,4,5,6> - 2598154746U, // <0,3,2,6>: Cost 3 vext1 , <6,2,7,3> - 2598155258U, // <0,3,2,7>: Cost 3 vext1 , <7,0,1,2> - 1482610478U, // <0,3,2,u>: Cost 2 vext1 <1,0,3,2>, LHS - 3692341398U, // <0,3,3,0>: Cost 4 vext2 <0,2,0,3>, <3,0,1,2> - 2635851999U, // <0,3,3,1>: Cost 3 vext2 <3,1,0,3>, <3,1,0,3> - 3636069840U, // <0,3,3,2>: Cost 4 vext1 <2,0,3,3>, <2,0,3,3> - 2691877276U, // <0,3,3,3>: Cost 3 vext3 <1,2,3,0>, <3,3,3,3> - 3961522690U, // <0,3,3,4>: Cost 4 vzipl <0,3,1,4>, <3,4,5,6> - 3826797058U, // <0,3,3,5>: Cost 4 vuzpl <0,2,3,5>, <3,4,5,6> - 3703622282U, // <0,3,3,6>: Cost 4 vext2 <2,1,0,3>, <3,6,2,7> - 3769600452U, // <0,3,3,7>: Cost 4 vext3 <1,u,3,0>, <3,3,7,7> - 2640497430U, // <0,3,3,u>: Cost 3 vext2 <3,u,0,3>, <3,u,0,3> - 3962194070U, // <0,3,4,0>: Cost 4 vzipl <0,4,1,5>, <3,0,1,2> - 2232617112U, // <0,3,4,1>: Cost 3 vrev <3,0,1,4> - 2232690849U, // <0,3,4,2>: Cost 3 vrev <3,0,2,4> - 4095314332U, // <0,3,4,3>: Cost 4 vtrnl <0,2,4,6>, <3,3,3,3> - 3962194434U, // <0,3,4,4>: Cost 4 vzipl <0,4,1,5>, <3,4,5,6> - 2691877378U, // <0,3,4,5>: Cost 3 vext3 <1,2,3,0>, <3,4,5,6> - 3826765110U, // <0,3,4,6>: Cost 4 vuzpl <0,2,3,1>, RHS - 3665941518U, // <0,3,4,7>: Cost 4 vext1 <7,0,3,4>, <7,0,3,4> - 2691877405U, // <0,3,4,u>: Cost 3 vext3 <1,2,3,0>, <3,4,u,6> - 3630112870U, // <0,3,5,0>: Cost 4 vext1 <1,0,3,5>, LHS - 3630113526U, // <0,3,5,1>: Cost 4 vext1 <1,0,3,5>, <1,0,3,2> - 4035199734U, // <0,3,5,2>: Cost 4 vzipr <1,4,0,5>, <1,0,3,2> - 3769600578U, // <0,3,5,3>: Cost 4 vext3 <1,u,3,0>, <3,5,3,7> - 2232846516U, // <0,3,5,4>: Cost 3 vrev <3,0,4,5> - 3779037780U, // <0,3,5,5>: Cost 4 vext3 <3,4,5,0>, <3,5,5,7> - 2718714461U, // <0,3,5,6>: Cost 3 vext3 <5,6,7,0>, <3,5,6,7> - 2706106975U, // <0,3,5,7>: Cost 3 vext3 <3,5,7,0>, <3,5,7,0> - 2233141464U, // <0,3,5,u>: Cost 3 vrev <3,0,u,5> - 2691877496U, // <0,3,6,0>: Cost 3 vext3 <1,2,3,0>, <3,6,0,7> - 3727511914U, // <0,3,6,1>: Cost 4 vext2 <6,1,0,3>, <6,1,0,3> - 3765619338U, // <0,3,6,2>: Cost 4 vext3 <1,2,3,0>, <3,6,2,7> - 3765619347U, // <0,3,6,3>: Cost 4 vext3 <1,2,3,0>, <3,6,3,7> - 3765987996U, // <0,3,6,4>: Cost 4 vext3 <1,2,u,0>, <3,6,4,7> - 3306670270U, // <0,3,6,5>: Cost 4 vrev <3,0,5,6> - 3792456365U, // <0,3,6,6>: Cost 4 vext3 <5,6,7,0>, <3,6,6,6> - 2706770608U, // <0,3,6,7>: Cost 3 vext3 <3,6,7,0>, <3,6,7,0> - 2706844345U, // <0,3,6,u>: Cost 3 vext3 <3,6,u,0>, <3,6,u,0> - 3769600707U, // <0,3,7,0>: Cost 4 vext3 <1,u,3,0>, <3,7,0,1> - 2659742787U, // <0,3,7,1>: Cost 3 vext2 <7,1,0,3>, <7,1,0,3> - 3636102612U, // <0,3,7,2>: Cost 4 vext1 <2,0,3,7>, <2,0,3,7> - 3769600740U, // <0,3,7,3>: Cost 4 vext3 <1,u,3,0>, <3,7,3,7> - 3769600747U, // <0,3,7,4>: Cost 4 vext3 <1,u,3,0>, <3,7,4,5> - 3769600758U, // <0,3,7,5>: Cost 4 vext3 <1,u,3,0>, <3,7,5,7> - 3659993400U, // <0,3,7,6>: Cost 4 vext1 <6,0,3,7>, <6,0,3,7> - 3781176065U, // <0,3,7,7>: Cost 4 vext3 <3,7,7,0>, <3,7,7,0> - 2664388218U, // <0,3,7,u>: Cost 3 vext2 <7,u,0,3>, <7,u,0,3> - 1482653798U, // <0,3,u,0>: Cost 2 vext1 <1,0,3,u>, LHS - 1482654460U, // <0,3,u,1>: Cost 2 vext1 <1,0,3,u>, <1,0,3,u> - 2556397160U, // <0,3,u,2>: Cost 3 vext1 <1,0,3,u>, <2,2,2,2> - 3021179292U, // <0,3,u,3>: Cost 3 vtrnl LHS, <3,3,3,3> - 1482657078U, // <0,3,u,4>: Cost 2 vext1 <1,0,3,u>, RHS - 3021179394U, // <0,3,u,5>: Cost 3 vtrnl LHS, <3,4,5,6> - 2598203898U, // <0,3,u,6>: Cost 3 vext1 , <6,2,7,3> - 2708097874U, // <0,3,u,7>: Cost 3 vext3 <3,u,7,0>, <3,u,7,0> - 1482659630U, // <0,3,u,u>: Cost 2 vext1 <1,0,3,u>, LHS - 2617278468U, // <0,4,0,0>: Cost 3 vext2 <0,0,0,4>, <0,0,0,4> - 2618605670U, // <0,4,0,1>: Cost 3 vext2 <0,2,0,4>, LHS - 2618605734U, // <0,4,0,2>: Cost 3 vext2 <0,2,0,4>, <0,2,0,4> - 3642091695U, // <0,4,0,3>: Cost 4 vext1 <3,0,4,0>, <3,0,4,0> - 2753134796U, // <0,4,0,4>: Cost 3 vuzpl <0,2,4,6>, <0,2,4,6> - 2718714770U, // <0,4,0,5>: Cost 3 vext3 <5,6,7,0>, <4,0,5,1> - 3021245750U, // <0,4,0,6>: Cost 3 vtrnl <0,2,0,2>, RHS - 3665982483U, // <0,4,0,7>: Cost 4 vext1 <7,0,4,0>, <7,0,4,0> - 3021245768U, // <0,4,0,u>: Cost 3 vtrnl <0,2,0,2>, RHS - 2568355942U, // <0,4,1,0>: Cost 3 vext1 <3,0,4,1>, LHS - 3692348212U, // <0,4,1,1>: Cost 4 vext2 <0,2,0,4>, <1,1,1,1> - 3692348310U, // <0,4,1,2>: Cost 4 vext2 <0,2,0,4>, <1,2,3,0> - 2568358064U, // <0,4,1,3>: Cost 3 vext1 <3,0,4,1>, <3,0,4,1> - 2568359222U, // <0,4,1,4>: Cost 3 vext1 <3,0,4,1>, RHS - 1812778294U, // <0,4,1,5>: Cost 2 vzipl LHS, RHS - 3022671158U, // <0,4,1,6>: Cost 3 vtrnl <0,4,1,5>, RHS - 2592248852U, // <0,4,1,7>: Cost 3 vext1 <7,0,4,1>, <7,0,4,1> - 1812778537U, // <0,4,1,u>: Cost 2 vzipl LHS, RHS - 2568364134U, // <0,4,2,0>: Cost 3 vext1 <3,0,4,2>, LHS - 2238573423U, // <0,4,2,1>: Cost 3 vrev <4,0,1,2> - 3692349032U, // <0,4,2,2>: Cost 4 vext2 <0,2,0,4>, <2,2,2,2> - 2631214761U, // <0,4,2,3>: Cost 3 vext2 <2,3,0,4>, <2,3,0,4> - 2568367414U, // <0,4,2,4>: Cost 3 vext1 <3,0,4,2>, RHS - 2887028022U, // <0,4,2,5>: Cost 3 vzipl <0,2,0,2>, RHS - 1946996022U, // <0,4,2,6>: Cost 2 vtrnl LHS, RHS - 2592257045U, // <0,4,2,7>: Cost 3 vext1 <7,0,4,2>, <7,0,4,2> - 1946996040U, // <0,4,2,u>: Cost 2 vtrnl LHS, RHS - 3692349590U, // <0,4,3,0>: Cost 4 vext2 <0,2,0,4>, <3,0,1,2> - 3826878614U, // <0,4,3,1>: Cost 4 vuzpl <0,2,4,6>, <3,0,1,2> - 3826878625U, // <0,4,3,2>: Cost 4 vuzpl <0,2,4,6>, <3,0,2,4> - 3692349852U, // <0,4,3,3>: Cost 4 vext2 <0,2,0,4>, <3,3,3,3> - 3692349954U, // <0,4,3,4>: Cost 4 vext2 <0,2,0,4>, <3,4,5,6> - 3826878978U, // <0,4,3,5>: Cost 4 vuzpl <0,2,4,6>, <3,4,5,6> - 4095200566U, // <0,4,3,6>: Cost 4 vtrnl <0,2,3,1>, RHS - 3713583814U, // <0,4,3,7>: Cost 4 vext2 <3,7,0,4>, <3,7,0,4> - 3692350238U, // <0,4,3,u>: Cost 4 vext2 <0,2,0,4>, <3,u,1,2> - 2550464552U, // <0,4,4,0>: Cost 3 vext1 <0,0,4,4>, <0,0,4,4> - 3962194914U, // <0,4,4,1>: Cost 4 vzipl <0,4,1,5>, <4,1,5,0> - 3693677631U, // <0,4,4,2>: Cost 4 vext2 <0,4,0,4>, <4,2,6,3> - 3642124467U, // <0,4,4,3>: Cost 4 vext1 <3,0,4,4>, <3,0,4,4> - 2718715088U, // <0,4,4,4>: Cost 3 vext3 <5,6,7,0>, <4,4,4,4> - 2618608950U, // <0,4,4,5>: Cost 3 vext2 <0,2,0,4>, RHS - 2753137974U, // <0,4,4,6>: Cost 3 vuzpl <0,2,4,6>, RHS - 3666015255U, // <0,4,4,7>: Cost 4 vext1 <7,0,4,4>, <7,0,4,4> - 2618609193U, // <0,4,4,u>: Cost 3 vext2 <0,2,0,4>, RHS - 2568388710U, // <0,4,5,0>: Cost 3 vext1 <3,0,4,5>, LHS - 2568389526U, // <0,4,5,1>: Cost 3 vext1 <3,0,4,5>, <1,2,3,0> - 3636159963U, // <0,4,5,2>: Cost 4 vext1 <2,0,4,5>, <2,0,4,5> - 2568390836U, // <0,4,5,3>: Cost 3 vext1 <3,0,4,5>, <3,0,4,5> - 2568391990U, // <0,4,5,4>: Cost 3 vext1 <3,0,4,5>, RHS - 2718715180U, // <0,4,5,5>: Cost 3 vext3 <5,6,7,0>, <4,5,5,6> - 1618136374U, // <0,4,5,6>: Cost 2 vext3 <1,2,3,0>, RHS - 2592281624U, // <0,4,5,7>: Cost 3 vext1 <7,0,4,5>, <7,0,4,5> - 1618136392U, // <0,4,5,u>: Cost 2 vext3 <1,2,3,0>, RHS - 2550480938U, // <0,4,6,0>: Cost 3 vext1 <0,0,4,6>, <0,0,4,6> - 3826880801U, // <0,4,6,1>: Cost 4 vuzpl <0,2,4,6>, <6,0,1,2> - 2562426332U, // <0,4,6,2>: Cost 3 vext1 <2,0,4,6>, <2,0,4,6> - 3786190181U, // <0,4,6,3>: Cost 4 vext3 <4,6,3,0>, <4,6,3,0> - 2718715252U, // <0,4,6,4>: Cost 3 vext3 <5,6,7,0>, <4,6,4,6> - 3826881165U, // <0,4,6,5>: Cost 4 vuzpl <0,2,4,6>, <6,4,5,6> - 2712669568U, // <0,4,6,6>: Cost 3 vext3 <4,6,6,0>, <4,6,6,0> - 2657760081U, // <0,4,6,7>: Cost 3 vext2 <6,7,0,4>, <6,7,0,4> - 2718715284U, // <0,4,6,u>: Cost 3 vext3 <5,6,7,0>, <4,6,u,2> - 3654090854U, // <0,4,7,0>: Cost 4 vext1 <5,0,4,7>, LHS - 3934229326U, // <0,4,7,1>: Cost 4 vuzpr <7,0,1,4>, <6,7,0,1> - 3734156437U, // <0,4,7,2>: Cost 4 vext2 <7,2,0,4>, <7,2,0,4> - 3734820070U, // <0,4,7,3>: Cost 4 vext2 <7,3,0,4>, <7,3,0,4> - 3654094134U, // <0,4,7,4>: Cost 4 vext1 <5,0,4,7>, RHS - 2713259464U, // <0,4,7,5>: Cost 3 vext3 <4,7,5,0>, <4,7,5,0> - 2713333201U, // <0,4,7,6>: Cost 3 vext3 <4,7,6,0>, <4,7,6,0> - 3654095866U, // <0,4,7,7>: Cost 4 vext1 <5,0,4,7>, <7,0,1,2> - 2713259464U, // <0,4,7,u>: Cost 3 vext3 <4,7,5,0>, <4,7,5,0> - 2568413286U, // <0,4,u,0>: Cost 3 vext1 <3,0,4,u>, LHS - 2618611502U, // <0,4,u,1>: Cost 3 vext2 <0,2,0,4>, LHS - 2753140526U, // <0,4,u,2>: Cost 3 vuzpl <0,2,4,6>, LHS - 2568415415U, // <0,4,u,3>: Cost 3 vext1 <3,0,4,u>, <3,0,4,u> - 2568416566U, // <0,4,u,4>: Cost 3 vext1 <3,0,4,u>, RHS - 1817423158U, // <0,4,u,5>: Cost 2 vzipl LHS, RHS - 1947438390U, // <0,4,u,6>: Cost 2 vtrnl LHS, RHS - 2592306203U, // <0,4,u,7>: Cost 3 vext1 <7,0,4,u>, <7,0,4,u> - 1947438408U, // <0,4,u,u>: Cost 2 vtrnl LHS, RHS - 3630219264U, // <0,5,0,0>: Cost 4 vext1 <1,0,5,0>, <0,0,0,0> - 2625912934U, // <0,5,0,1>: Cost 3 vext2 <1,4,0,5>, LHS - 3692355748U, // <0,5,0,2>: Cost 4 vext2 <0,2,0,5>, <0,2,0,2> - 3693019384U, // <0,5,0,3>: Cost 4 vext2 <0,3,0,5>, <0,3,0,5> - 3630222646U, // <0,5,0,4>: Cost 4 vext1 <1,0,5,0>, RHS - 3699655062U, // <0,5,0,5>: Cost 4 vext2 <1,4,0,5>, <0,5,0,1> - 2718715508U, // <0,5,0,6>: Cost 3 vext3 <5,6,7,0>, <5,0,6,1> - 3087011126U, // <0,5,0,7>: Cost 3 vtrnr <0,0,0,0>, RHS - 2625913501U, // <0,5,0,u>: Cost 3 vext2 <1,4,0,5>, LHS - 1500659814U, // <0,5,1,0>: Cost 2 vext1 <4,0,5,1>, LHS - 2886520528U, // <0,5,1,1>: Cost 3 vzipl LHS, <5,1,7,3> - 2574403176U, // <0,5,1,2>: Cost 3 vext1 <4,0,5,1>, <2,2,2,2> - 2574403734U, // <0,5,1,3>: Cost 3 vext1 <4,0,5,1>, <3,0,1,2> - 1500662674U, // <0,5,1,4>: Cost 2 vext1 <4,0,5,1>, <4,0,5,1> - 2886520836U, // <0,5,1,5>: Cost 3 vzipl LHS, <5,5,5,5> - 2886520930U, // <0,5,1,6>: Cost 3 vzipl LHS, <5,6,7,0> - 2718715600U, // <0,5,1,7>: Cost 3 vext3 <5,6,7,0>, <5,1,7,3> - 1500665646U, // <0,5,1,u>: Cost 2 vext1 <4,0,5,1>, LHS - 2556493926U, // <0,5,2,0>: Cost 3 vext1 <1,0,5,2>, LHS - 2244546120U, // <0,5,2,1>: Cost 3 vrev <5,0,1,2> - 3692357256U, // <0,5,2,2>: Cost 4 vext2 <0,2,0,5>, <2,2,5,7> - 2568439994U, // <0,5,2,3>: Cost 3 vext1 <3,0,5,2>, <3,0,5,2> - 2556497206U, // <0,5,2,4>: Cost 3 vext1 <1,0,5,2>, RHS - 3020738564U, // <0,5,2,5>: Cost 3 vtrnl LHS, <5,5,5,5> - 4027877161U, // <0,5,2,6>: Cost 4 vzipr <0,2,0,2>, <2,4,5,6> - 3093220662U, // <0,5,2,7>: Cost 3 vtrnr <1,0,3,2>, RHS - 3093220663U, // <0,5,2,u>: Cost 3 vtrnr <1,0,3,2>, RHS - 3699656854U, // <0,5,3,0>: Cost 4 vext2 <1,4,0,5>, <3,0,1,2> - 3699656927U, // <0,5,3,1>: Cost 4 vext2 <1,4,0,5>, <3,1,0,3> - 3699657006U, // <0,5,3,2>: Cost 4 vext2 <1,4,0,5>, <3,2,0,1> - 3699657116U, // <0,5,3,3>: Cost 4 vext2 <1,4,0,5>, <3,3,3,3> - 2637859284U, // <0,5,3,4>: Cost 3 vext2 <3,4,0,5>, <3,4,0,5> - 3790319453U, // <0,5,3,5>: Cost 4 vext3 <5,3,5,0>, <5,3,5,0> - 3699657354U, // <0,5,3,6>: Cost 4 vext2 <1,4,0,5>, <3,6,2,7> - 2716725103U, // <0,5,3,7>: Cost 3 vext3 <5,3,7,0>, <5,3,7,0> - 2716798840U, // <0,5,3,u>: Cost 3 vext3 <5,3,u,0>, <5,3,u,0> - 2661747602U, // <0,5,4,0>: Cost 3 vext2 <7,4,0,5>, <4,0,5,1> - 3630252810U, // <0,5,4,1>: Cost 4 vext1 <1,0,5,4>, <1,0,5,4> - 3636225507U, // <0,5,4,2>: Cost 4 vext1 <2,0,5,4>, <2,0,5,4> - 3716910172U, // <0,5,4,3>: Cost 4 vext2 <4,3,0,5>, <4,3,0,5> - 3962195892U, // <0,5,4,4>: Cost 4 vzipl <0,4,1,5>, <5,4,5,6> - 2625916214U, // <0,5,4,5>: Cost 3 vext2 <1,4,0,5>, RHS - 3718901071U, // <0,5,4,6>: Cost 4 vext2 <4,6,0,5>, <4,6,0,5> - 2718715846U, // <0,5,4,7>: Cost 3 vext3 <5,6,7,0>, <5,4,7,6> - 2625916457U, // <0,5,4,u>: Cost 3 vext2 <1,4,0,5>, RHS - 3791278034U, // <0,5,5,0>: Cost 4 vext3 <5,5,0,0>, <5,5,0,0> - 3791351771U, // <0,5,5,1>: Cost 4 vext3 <5,5,1,0>, <5,5,1,0> - 3318386260U, // <0,5,5,2>: Cost 4 vrev <5,0,2,5> - 3791499245U, // <0,5,5,3>: Cost 4 vext3 <5,5,3,0>, <5,5,3,0> - 3318533734U, // <0,5,5,4>: Cost 4 vrev <5,0,4,5> - 2718715908U, // <0,5,5,5>: Cost 3 vext3 <5,6,7,0>, <5,5,5,5> - 2657767522U, // <0,5,5,6>: Cost 3 vext2 <6,7,0,5>, <5,6,7,0> - 2718715928U, // <0,5,5,7>: Cost 3 vext3 <5,6,7,0>, <5,5,7,7> - 2718715937U, // <0,5,5,u>: Cost 3 vext3 <5,6,7,0>, <5,5,u,7> - 2592358502U, // <0,5,6,0>: Cost 3 vext1 <7,0,5,6>, LHS - 3792015404U, // <0,5,6,1>: Cost 4 vext3 <5,6,1,0>, <5,6,1,0> - 3731509754U, // <0,5,6,2>: Cost 4 vext2 <6,7,0,5>, <6,2,7,3> - 3785748546U, // <0,5,6,3>: Cost 4 vext3 <4,5,6,0>, <5,6,3,4> - 2592361782U, // <0,5,6,4>: Cost 3 vext1 <7,0,5,6>, RHS - 2592362594U, // <0,5,6,5>: Cost 3 vext1 <7,0,5,6>, <5,6,7,0> - 3785748576U, // <0,5,6,6>: Cost 4 vext3 <4,5,6,0>, <5,6,6,7> - 1644974178U, // <0,5,6,7>: Cost 2 vext3 <5,6,7,0>, <5,6,7,0> - 1645047915U, // <0,5,6,u>: Cost 2 vext3 <5,6,u,0>, <5,6,u,0> - 2562506854U, // <0,5,7,0>: Cost 3 vext1 <2,0,5,7>, LHS - 2562507670U, // <0,5,7,1>: Cost 3 vext1 <2,0,5,7>, <1,2,3,0> - 2562508262U, // <0,5,7,2>: Cost 3 vext1 <2,0,5,7>, <2,0,5,7> - 3636250774U, // <0,5,7,3>: Cost 4 vext1 <2,0,5,7>, <3,0,1,2> - 2562510134U, // <0,5,7,4>: Cost 3 vext1 <2,0,5,7>, RHS - 2718716072U, // <0,5,7,5>: Cost 3 vext3 <5,6,7,0>, <5,7,5,7> - 2718716074U, // <0,5,7,6>: Cost 3 vext3 <5,6,7,0>, <5,7,6,0> - 2719379635U, // <0,5,7,7>: Cost 3 vext3 <5,7,7,0>, <5,7,7,0> - 2562512686U, // <0,5,7,u>: Cost 3 vext1 <2,0,5,7>, LHS - 1500717158U, // <0,5,u,0>: Cost 2 vext1 <4,0,5,u>, LHS - 2625918766U, // <0,5,u,1>: Cost 3 vext2 <1,4,0,5>, LHS - 2719674583U, // <0,5,u,2>: Cost 3 vext3 <5,u,2,0>, <5,u,2,0> - 2568489152U, // <0,5,u,3>: Cost 3 vext1 <3,0,5,u>, <3,0,5,u> - 1500720025U, // <0,5,u,4>: Cost 2 vext1 <4,0,5,u>, <4,0,5,u> - 2625919130U, // <0,5,u,5>: Cost 3 vext2 <1,4,0,5>, RHS - 2586407243U, // <0,5,u,6>: Cost 3 vext1 <6,0,5,u>, <6,0,5,u> - 1646301444U, // <0,5,u,7>: Cost 2 vext3 <5,u,7,0>, <5,u,7,0> - 1646375181U, // <0,5,u,u>: Cost 2 vext3 <5,u,u,0>, <5,u,u,0> - 2586411110U, // <0,6,0,0>: Cost 3 vext1 <6,0,6,0>, LHS - 2619949158U, // <0,6,0,1>: Cost 3 vext2 <0,4,0,6>, LHS - 2619949220U, // <0,6,0,2>: Cost 3 vext2 <0,4,0,6>, <0,2,0,2> - 3785748789U, // <0,6,0,3>: Cost 4 vext3 <4,5,6,0>, <6,0,3,4> - 2619949386U, // <0,6,0,4>: Cost 3 vext2 <0,4,0,6>, <0,4,0,6> - 2586415202U, // <0,6,0,5>: Cost 3 vext1 <6,0,6,0>, <5,6,7,0> - 2586415436U, // <0,6,0,6>: Cost 3 vext1 <6,0,6,0>, <6,0,6,0> - 2952793398U, // <0,6,0,7>: Cost 3 vzipr <0,0,0,0>, RHS - 2619949725U, // <0,6,0,u>: Cost 3 vext2 <0,4,0,6>, LHS - 2562531430U, // <0,6,1,0>: Cost 3 vext1 <2,0,6,1>, LHS - 3693691700U, // <0,6,1,1>: Cost 4 vext2 <0,4,0,6>, <1,1,1,1> - 2886521338U, // <0,6,1,2>: Cost 3 vzipl LHS, <6,2,7,3> - 3693691864U, // <0,6,1,3>: Cost 4 vext2 <0,4,0,6>, <1,3,1,3> - 2562534710U, // <0,6,1,4>: Cost 3 vext1 <2,0,6,1>, RHS - 2580450932U, // <0,6,1,5>: Cost 3 vext1 <5,0,6,1>, <5,0,6,1> - 2886521656U, // <0,6,1,6>: Cost 3 vzipl LHS, <6,6,6,6> - 2966736182U, // <0,6,1,7>: Cost 3 vzipr <2,3,0,1>, RHS - 2966736183U, // <0,6,1,u>: Cost 3 vzipr <2,3,0,1>, RHS - 1500741734U, // <0,6,2,0>: Cost 2 vext1 <4,0,6,2>, LHS - 2250518817U, // <0,6,2,1>: Cost 3 vrev <6,0,1,2> - 2574485096U, // <0,6,2,2>: Cost 3 vext1 <4,0,6,2>, <2,2,2,2> - 2631894694U, // <0,6,2,3>: Cost 3 vext2 <2,4,0,6>, <2,3,0,1> - 1500744604U, // <0,6,2,4>: Cost 2 vext1 <4,0,6,2>, <4,0,6,2> - 2574487248U, // <0,6,2,5>: Cost 3 vext1 <4,0,6,2>, <5,1,7,3> - 3020739384U, // <0,6,2,6>: Cost 3 vtrnl LHS, <6,6,6,6> - 2954136886U, // <0,6,2,7>: Cost 3 vzipr <0,2,0,2>, RHS - 1500747566U, // <0,6,2,u>: Cost 2 vext1 <4,0,6,2>, LHS - 3693693078U, // <0,6,3,0>: Cost 4 vext2 <0,4,0,6>, <3,0,1,2> - 3705637136U, // <0,6,3,1>: Cost 4 vext2 <2,4,0,6>, <3,1,5,7> - 3705637192U, // <0,6,3,2>: Cost 4 vext2 <2,4,0,6>, <3,2,3,0> - 3693693340U, // <0,6,3,3>: Cost 4 vext2 <0,4,0,6>, <3,3,3,3> - 2637867477U, // <0,6,3,4>: Cost 3 vext2 <3,4,0,6>, <3,4,0,6> - 3705637424U, // <0,6,3,5>: Cost 4 vext2 <2,4,0,6>, <3,5,1,7> - 3666154056U, // <0,6,3,6>: Cost 4 vext1 <7,0,6,3>, <6,3,7,0> - 2722697800U, // <0,6,3,7>: Cost 3 vext3 <6,3,7,0>, <6,3,7,0> - 2722771537U, // <0,6,3,u>: Cost 3 vext3 <6,3,u,0>, <6,3,u,0> - 2562556006U, // <0,6,4,0>: Cost 3 vext1 <2,0,6,4>, LHS - 4095316257U, // <0,6,4,1>: Cost 4 vtrnl <0,2,4,6>, <6,0,1,2> - 2562557420U, // <0,6,4,2>: Cost 3 vext1 <2,0,6,4>, <2,0,6,4> - 3636299926U, // <0,6,4,3>: Cost 4 vext1 <2,0,6,4>, <3,0,1,2> - 2562559286U, // <0,6,4,4>: Cost 3 vext1 <2,0,6,4>, RHS - 2619952438U, // <0,6,4,5>: Cost 3 vext2 <0,4,0,6>, RHS - 2723287696U, // <0,6,4,6>: Cost 3 vext3 <6,4,6,0>, <6,4,6,0> - 4027895094U, // <0,6,4,7>: Cost 4 vzipr <0,2,0,4>, RHS - 2619952681U, // <0,6,4,u>: Cost 3 vext2 <0,4,0,6>, RHS - 2718716594U, // <0,6,5,0>: Cost 3 vext3 <5,6,7,0>, <6,5,0,7> - 3648250774U, // <0,6,5,1>: Cost 4 vext1 <4,0,6,5>, <1,2,3,0> - 3792458436U, // <0,6,5,2>: Cost 4 vext3 <5,6,7,0>, <6,5,2,7> - 3705638767U, // <0,6,5,3>: Cost 5 vext2 <2,4,0,6>, <5,3,7,0> - 3648252831U, // <0,6,5,4>: Cost 4 vext1 <4,0,6,5>, <4,0,6,5> - 3797619416U, // <0,6,5,5>: Cost 4 vext3 <6,5,5,0>, <6,5,5,0> - 3792458472U, // <0,6,5,6>: Cost 4 vext3 <5,6,7,0>, <6,5,6,7> - 4035202358U, // <0,6,5,7>: Cost 4 vzipr <1,4,0,5>, RHS - 2718716594U, // <0,6,5,u>: Cost 3 vext3 <5,6,7,0>, <6,5,0,7> - 3786412796U, // <0,6,6,0>: Cost 4 vext3 <4,6,6,0>, <6,6,0,0> - 3792458504U, // <0,6,6,1>: Cost 4 vext3 <5,6,7,0>, <6,6,1,3> - 3728200126U, // <0,6,6,2>: Cost 4 vext2 <6,2,0,6>, <6,2,0,6> - 3798135575U, // <0,6,6,3>: Cost 4 vext3 <6,6,3,0>, <6,6,3,0> - 3786412836U, // <0,6,6,4>: Cost 4 vext3 <4,6,6,0>, <6,6,4,4> - 3792458543U, // <0,6,6,5>: Cost 4 vext3 <5,6,7,0>, <6,6,5,6> - 2718716728U, // <0,6,6,6>: Cost 3 vext3 <5,6,7,0>, <6,6,6,6> - 2718716738U, // <0,6,6,7>: Cost 3 vext3 <5,6,7,0>, <6,6,7,7> - 2718716747U, // <0,6,6,u>: Cost 3 vext3 <5,6,7,0>, <6,6,u,7> - 2718716750U, // <0,6,7,0>: Cost 3 vext3 <5,6,7,0>, <6,7,0,1> - 2724909910U, // <0,6,7,1>: Cost 3 vext3 <6,7,1,0>, <6,7,1,0> - 3636323823U, // <0,6,7,2>: Cost 4 vext1 <2,0,6,7>, <2,0,6,7> - 2725057384U, // <0,6,7,3>: Cost 3 vext3 <6,7,3,0>, <6,7,3,0> - 2718716790U, // <0,6,7,4>: Cost 3 vext3 <5,6,7,0>, <6,7,4,5> - 2718716800U, // <0,6,7,5>: Cost 3 vext3 <5,6,7,0>, <6,7,5,6> - 3792458629U, // <0,6,7,6>: Cost 4 vext3 <5,6,7,0>, <6,7,6,2> - 2725352332U, // <0,6,7,7>: Cost 3 vext3 <6,7,7,0>, <6,7,7,0> - 2718716822U, // <0,6,7,u>: Cost 3 vext3 <5,6,7,0>, <6,7,u,1> - 1500790886U, // <0,6,u,0>: Cost 2 vext1 <4,0,6,u>, LHS - 2619954990U, // <0,6,u,1>: Cost 3 vext2 <0,4,0,6>, LHS - 2562590192U, // <0,6,u,2>: Cost 3 vext1 <2,0,6,u>, <2,0,6,u> - 2725721017U, // <0,6,u,3>: Cost 3 vext3 <6,u,3,0>, <6,u,3,0> - 1500793762U, // <0,6,u,4>: Cost 2 vext1 <4,0,6,u>, <4,0,6,u> - 2619955354U, // <0,6,u,5>: Cost 3 vext2 <0,4,0,6>, RHS - 2725942228U, // <0,6,u,6>: Cost 3 vext3 <6,u,6,0>, <6,u,6,0> - 2954186038U, // <0,6,u,7>: Cost 3 vzipr <0,2,0,u>, RHS - 1500796718U, // <0,6,u,u>: Cost 2 vext1 <4,0,6,u>, LHS - 2256401391U, // <0,7,0,0>: Cost 3 vrev <7,0,0,0> - 2632564838U, // <0,7,0,1>: Cost 3 vext2 <2,5,0,7>, LHS - 2256548865U, // <0,7,0,2>: Cost 3 vrev <7,0,2,0> - 3700998396U, // <0,7,0,3>: Cost 4 vext2 <1,6,0,7>, <0,3,1,0> - 2718716952U, // <0,7,0,4>: Cost 3 vext3 <5,6,7,0>, <7,0,4,5> - 2718716962U, // <0,7,0,5>: Cost 3 vext3 <5,6,7,0>, <7,0,5,6> - 2621284845U, // <0,7,0,6>: Cost 3 vext2 <0,6,0,7>, <0,6,0,7> - 3904685542U, // <0,7,0,7>: Cost 4 vuzpr <2,0,5,7>, <2,0,5,7> - 2632565405U, // <0,7,0,u>: Cost 3 vext2 <2,5,0,7>, LHS - 2256409584U, // <0,7,1,0>: Cost 3 vrev <7,0,0,1> - 3706307380U, // <0,7,1,1>: Cost 4 vext2 <2,5,0,7>, <1,1,1,1> - 2632565654U, // <0,7,1,2>: Cost 3 vext2 <2,5,0,7>, <1,2,3,0> - 3769603168U, // <0,7,1,3>: Cost 4 vext3 <1,u,3,0>, <7,1,3,5> - 2256704532U, // <0,7,1,4>: Cost 3 vrev <7,0,4,1> - 3769603184U, // <0,7,1,5>: Cost 4 vext3 <1,u,3,0>, <7,1,5,3> - 3700999366U, // <0,7,1,6>: Cost 4 vext2 <1,6,0,7>, <1,6,0,7> - 2886522476U, // <0,7,1,7>: Cost 3 vzipl LHS, <7,7,7,7> - 2256999480U, // <0,7,1,u>: Cost 3 vrev <7,0,u,1> - 2586501222U, // <0,7,2,0>: Cost 3 vext1 <6,0,7,2>, LHS - 1182749690U, // <0,7,2,1>: Cost 2 vrev <7,0,1,2> - 3636356595U, // <0,7,2,2>: Cost 4 vext1 <2,0,7,2>, <2,0,7,2> - 2727711916U, // <0,7,2,3>: Cost 3 vext3 <7,2,3,0>, <7,2,3,0> - 2586504502U, // <0,7,2,4>: Cost 3 vext1 <6,0,7,2>, RHS - 2632566606U, // <0,7,2,5>: Cost 3 vext2 <2,5,0,7>, <2,5,0,7> - 2586505559U, // <0,7,2,6>: Cost 3 vext1 <6,0,7,2>, <6,0,7,2> - 3020740204U, // <0,7,2,7>: Cost 3 vtrnl LHS, <7,7,7,7> - 1183265849U, // <0,7,2,u>: Cost 2 vrev <7,0,u,2> - 3701000342U, // <0,7,3,0>: Cost 4 vext2 <1,6,0,7>, <3,0,1,2> - 3706308849U, // <0,7,3,1>: Cost 4 vext2 <2,5,0,7>, <3,1,2,3> - 3330315268U, // <0,7,3,2>: Cost 4 vrev <7,0,2,3> - 3706309020U, // <0,7,3,3>: Cost 4 vext2 <2,5,0,7>, <3,3,3,3> - 3706309122U, // <0,7,3,4>: Cost 4 vext2 <2,5,0,7>, <3,4,5,6> - 3712281127U, // <0,7,3,5>: Cost 4 vext2 <3,5,0,7>, <3,5,0,7> - 2639202936U, // <0,7,3,6>: Cost 3 vext2 <3,6,0,7>, <3,6,0,7> - 3802412321U, // <0,7,3,7>: Cost 4 vext3 <7,3,7,0>, <7,3,7,0> - 2640530202U, // <0,7,3,u>: Cost 3 vext2 <3,u,0,7>, <3,u,0,7> - 3654287462U, // <0,7,4,0>: Cost 4 vext1 <5,0,7,4>, LHS - 2256507900U, // <0,7,4,1>: Cost 3 vrev <7,0,1,4> - 2256581637U, // <0,7,4,2>: Cost 3 vrev <7,0,2,4> - 3660262008U, // <0,7,4,3>: Cost 4 vext1 <6,0,7,4>, <3,6,0,7> - 3786413405U, // <0,7,4,4>: Cost 4 vext3 <4,6,6,0>, <7,4,4,6> - 2632568118U, // <0,7,4,5>: Cost 3 vext2 <2,5,0,7>, RHS - 3718917457U, // <0,7,4,6>: Cost 4 vext2 <4,6,0,7>, <4,6,0,7> - 3787003255U, // <0,7,4,7>: Cost 4 vext3 <4,7,5,0>, <7,4,7,5> - 2632568361U, // <0,7,4,u>: Cost 3 vext2 <2,5,0,7>, RHS - 3706310268U, // <0,7,5,0>: Cost 4 vext2 <2,5,0,7>, <5,0,7,0> - 3792459156U, // <0,7,5,1>: Cost 4 vext3 <5,6,7,0>, <7,5,1,7> - 3330331654U, // <0,7,5,2>: Cost 4 vrev <7,0,2,5> - 3722899255U, // <0,7,5,3>: Cost 4 vext2 <5,3,0,7>, <5,3,0,7> - 2256737304U, // <0,7,5,4>: Cost 3 vrev <7,0,4,5> - 3724226521U, // <0,7,5,5>: Cost 4 vext2 <5,5,0,7>, <5,5,0,7> - 2718717377U, // <0,7,5,6>: Cost 3 vext3 <5,6,7,0>, <7,5,6,7> - 2729997763U, // <0,7,5,7>: Cost 3 vext3 <7,5,7,0>, <7,5,7,0> - 2720044499U, // <0,7,5,u>: Cost 3 vext3 <5,u,7,0>, <7,5,u,7> - 3712946517U, // <0,7,6,0>: Cost 4 vext2 <3,6,0,7>, <6,0,7,0> - 2256524286U, // <0,7,6,1>: Cost 3 vrev <7,0,1,6> - 3792459246U, // <0,7,6,2>: Cost 4 vext3 <5,6,7,0>, <7,6,2,7> - 3796440567U, // <0,7,6,3>: Cost 4 vext3 <6,3,7,0>, <7,6,3,7> - 3654307126U, // <0,7,6,4>: Cost 4 vext1 <5,0,7,6>, RHS - 2656457394U, // <0,7,6,5>: Cost 3 vext2 <6,5,0,7>, <6,5,0,7> - 3792459281U, // <0,7,6,6>: Cost 4 vext3 <5,6,7,0>, <7,6,6,6> - 2730661396U, // <0,7,6,7>: Cost 3 vext3 <7,6,7,0>, <7,6,7,0> - 2658448293U, // <0,7,6,u>: Cost 3 vext2 <6,u,0,7>, <6,u,0,7> - 3787003431U, // <0,7,7,0>: Cost 4 vext3 <4,7,5,0>, <7,7,0,1> - 3654312854U, // <0,7,7,1>: Cost 4 vext1 <5,0,7,7>, <1,2,3,0> - 3654313446U, // <0,7,7,2>: Cost 4 vext1 <5,0,7,7>, <2,0,5,7> - 3804771905U, // <0,7,7,3>: Cost 4 vext3 <7,7,3,0>, <7,7,3,0> - 3654315318U, // <0,7,7,4>: Cost 4 vext1 <5,0,7,7>, RHS - 3654315651U, // <0,7,7,5>: Cost 4 vext1 <5,0,7,7>, <5,0,7,7> - 3660288348U, // <0,7,7,6>: Cost 4 vext1 <6,0,7,7>, <6,0,7,7> - 2718717548U, // <0,7,7,7>: Cost 3 vext3 <5,6,7,0>, <7,7,7,7> - 2664420990U, // <0,7,7,u>: Cost 3 vext2 <7,u,0,7>, <7,u,0,7> - 2256466935U, // <0,7,u,0>: Cost 3 vrev <7,0,0,u> - 1182798848U, // <0,7,u,1>: Cost 2 vrev <7,0,1,u> - 2256614409U, // <0,7,u,2>: Cost 3 vrev <7,0,2,u> - 2731693714U, // <0,7,u,3>: Cost 3 vext3 <7,u,3,0>, <7,u,3,0> - 2256761883U, // <0,7,u,4>: Cost 3 vrev <7,0,4,u> - 2632571034U, // <0,7,u,5>: Cost 3 vext2 <2,5,0,7>, RHS - 2669066421U, // <0,7,u,6>: Cost 3 vext2 , - 2731988662U, // <0,7,u,7>: Cost 3 vext3 <7,u,7,0>, <7,u,7,0> - 1183315007U, // <0,7,u,u>: Cost 2 vrev <7,0,u,u> - 135053414U, // <0,u,0,0>: Cost 1 vdup0 LHS - 1544896614U, // <0,u,0,1>: Cost 2 vext2 <0,2,0,u>, LHS - 1678999654U, // <0,u,0,2>: Cost 2 vuzpl LHS, LHS - 2691880677U, // <0,u,0,3>: Cost 3 vext3 <1,2,3,0>, - 1476988214U, // <0,u,0,4>: Cost 2 vext1 <0,0,u,0>, RHS - 2718791419U, // <0,u,0,5>: Cost 3 vext3 <5,6,u,0>, - 3021248666U, // <0,u,0,6>: Cost 3 vtrnl <0,2,0,2>, RHS - 2592535607U, // <0,u,0,7>: Cost 3 vext1 <7,0,u,0>, <7,0,u,0> - 135053414U, // <0,u,0,u>: Cost 1 vdup0 LHS - 1476993097U, // <0,u,1,0>: Cost 2 vext1 <0,0,u,1>, <0,0,u,1> - 1812780846U, // <0,u,1,1>: Cost 2 vzipl LHS, LHS - 1618138926U, // <0,u,1,2>: Cost 2 vext3 <1,2,3,0>, LHS - 2752742134U, // <0,u,1,3>: Cost 3 vuzpl LHS, <1,0,3,2> - 1476996406U, // <0,u,1,4>: Cost 2 vext1 <0,0,u,1>, RHS - 1812781210U, // <0,u,1,5>: Cost 2 vzipl LHS, RHS - 2887006416U, // <0,u,1,6>: Cost 3 vzipl LHS, - 2966736200U, // <0,u,1,7>: Cost 3 vzipr <2,3,0,1>, RHS - 1812781413U, // <0,u,1,u>: Cost 2 vzipl LHS, LHS - 1482973286U, // <0,u,2,0>: Cost 2 vext1 <1,0,u,2>, LHS - 1482973987U, // <0,u,2,1>: Cost 2 vext1 <1,0,u,2>, <1,0,u,2> - 1946998574U, // <0,u,2,2>: Cost 2 vtrnl LHS, LHS - 835584U, // <0,u,2,3>: Cost 0 copy LHS - 1482976566U, // <0,u,2,4>: Cost 2 vext1 <1,0,u,2>, RHS - 3020781631U, // <0,u,2,5>: Cost 3 vtrnl LHS, - 1946998938U, // <0,u,2,6>: Cost 2 vtrnl LHS, RHS - 1518810169U, // <0,u,2,7>: Cost 2 vext1 <7,0,u,2>, <7,0,u,2> - 835584U, // <0,u,2,u>: Cost 0 copy LHS - 2618640534U, // <0,u,3,0>: Cost 3 vext2 <0,2,0,u>, <3,0,1,2> - 2752743574U, // <0,u,3,1>: Cost 3 vuzpl LHS, <3,0,1,2> - 2636556597U, // <0,u,3,2>: Cost 3 vext2 <3,2,0,u>, <3,2,0,u> - 2752743836U, // <0,u,3,3>: Cost 3 vuzpl LHS, <3,3,3,3> - 2618640898U, // <0,u,3,4>: Cost 3 vext2 <0,2,0,u>, <3,4,5,6> - 2752743938U, // <0,u,3,5>: Cost 3 vuzpl LHS, <3,4,5,6> - 2639202936U, // <0,u,3,6>: Cost 3 vext2 <3,6,0,7>, <3,6,0,7> - 2639874762U, // <0,u,3,7>: Cost 3 vext2 <3,7,0,u>, <3,7,0,u> - 2752743637U, // <0,u,3,u>: Cost 3 vuzpl LHS, <3,0,u,2> - 2562703462U, // <0,u,4,0>: Cost 3 vext1 <2,0,u,4>, LHS - 2888455982U, // <0,u,4,1>: Cost 3 vzipl <0,4,1,5>, LHS - 3021575982U, // <0,u,4,2>: Cost 3 vtrnl <0,2,4,6>, LHS - 2568677591U, // <0,u,4,3>: Cost 3 vext1 <3,0,u,4>, <3,0,u,4> - 2562706742U, // <0,u,4,4>: Cost 3 vext1 <2,0,u,4>, RHS - 1544899894U, // <0,u,4,5>: Cost 2 vext2 <0,2,0,u>, RHS - 1679002934U, // <0,u,4,6>: Cost 2 vuzpl LHS, RHS - 2718718033U, // <0,u,4,7>: Cost 3 vext3 <5,6,7,0>, - 1679002952U, // <0,u,4,u>: Cost 2 vuzpl LHS, RHS - 2568683622U, // <0,u,5,0>: Cost 3 vext1 <3,0,u,5>, LHS - 2568684438U, // <0,u,5,1>: Cost 3 vext1 <3,0,u,5>, <1,2,3,0> - 3765622902U, // <0,u,5,2>: Cost 4 vext3 <1,2,3,0>, - 2691881087U, // <0,u,5,3>: Cost 3 vext3 <1,2,3,0>, - 2568686902U, // <0,u,5,4>: Cost 3 vext1 <3,0,u,5>, RHS - 2650492890U, // <0,u,5,5>: Cost 3 vext2 <5,5,0,u>, <5,5,0,u> - 1618139290U, // <0,u,5,6>: Cost 2 vext3 <1,2,3,0>, RHS - 2824834358U, // <0,u,5,7>: Cost 3 vuzpr <1,0,3,u>, RHS - 1618139308U, // <0,u,5,u>: Cost 2 vext3 <1,2,3,0>, RHS - 2592579686U, // <0,u,6,0>: Cost 3 vext1 <7,0,u,6>, LHS - 2262496983U, // <0,u,6,1>: Cost 3 vrev - 2654474688U, // <0,u,6,2>: Cost 3 vext2 <6,2,0,u>, <6,2,0,u> - 2691881168U, // <0,u,6,3>: Cost 3 vext3 <1,2,3,0>, - 2592582966U, // <0,u,6,4>: Cost 3 vext1 <7,0,u,6>, RHS - 2656465587U, // <0,u,6,5>: Cost 3 vext2 <6,5,0,u>, <6,5,0,u> - 2657129220U, // <0,u,6,6>: Cost 3 vext2 <6,6,0,u>, <6,6,0,u> - 1584051029U, // <0,u,6,7>: Cost 2 vext2 <6,7,0,u>, <6,7,0,u> - 1584714662U, // <0,u,6,u>: Cost 2 vext2 <6,u,0,u>, <6,u,0,u> - 2562728038U, // <0,u,7,0>: Cost 3 vext1 <2,0,u,7>, LHS - 2562728854U, // <0,u,7,1>: Cost 3 vext1 <2,0,u,7>, <1,2,3,0> - 2562729473U, // <0,u,7,2>: Cost 3 vext1 <2,0,u,7>, <2,0,u,7> - 2661111018U, // <0,u,7,3>: Cost 3 vext2 <7,3,0,u>, <7,3,0,u> - 2562731318U, // <0,u,7,4>: Cost 3 vext1 <2,0,u,7>, RHS - 2718718258U, // <0,u,7,5>: Cost 3 vext3 <5,6,7,0>, - 2586620261U, // <0,u,7,6>: Cost 3 vext1 <6,0,u,7>, <6,0,u,7> - 2657793644U, // <0,u,7,7>: Cost 3 vext2 <6,7,0,u>, <7,7,7,7> - 2562733870U, // <0,u,7,u>: Cost 3 vext1 <2,0,u,7>, LHS - 135053414U, // <0,u,u,0>: Cost 1 vdup0 LHS - 1544902446U, // <0,u,u,1>: Cost 2 vext2 <0,2,0,u>, LHS - 1679005486U, // <0,u,u,2>: Cost 2 vuzpl LHS, LHS - 835584U, // <0,u,u,3>: Cost 0 copy LHS - 1483025718U, // <0,u,u,4>: Cost 2 vext1 <1,0,u,u>, RHS - 1544902810U, // <0,u,u,5>: Cost 2 vext2 <0,2,0,u>, RHS - 1679005850U, // <0,u,u,6>: Cost 2 vuzpl LHS, RHS - 1518859327U, // <0,u,u,7>: Cost 2 vext1 <7,0,u,u>, <7,0,u,u> - 835584U, // <0,u,u,u>: Cost 0 copy LHS - 2689744896U, // <1,0,0,0>: Cost 3 vext3 <0,u,1,1>, <0,0,0,0> - 1610694666U, // <1,0,0,1>: Cost 2 vext3 <0,0,1,1>, <0,0,1,1> - 2689744916U, // <1,0,0,2>: Cost 3 vext3 <0,u,1,1>, <0,0,2,2> - 2619310332U, // <1,0,0,3>: Cost 3 vext2 <0,3,1,0>, <0,3,1,0> - 2684657701U, // <1,0,0,4>: Cost 3 vext3 <0,0,4,1>, <0,0,4,1> - 2620637598U, // <1,0,0,5>: Cost 3 vext2 <0,5,1,0>, <0,5,1,0> - 3708977654U, // <1,0,0,6>: Cost 4 vext2 <3,0,1,0>, <0,6,1,7> - 3666351168U, // <1,0,0,7>: Cost 4 vext1 <7,1,0,0>, <7,1,0,0> - 1611210825U, // <1,0,0,u>: Cost 2 vext3 <0,0,u,1>, <0,0,u,1> - 2556780646U, // <1,0,1,0>: Cost 3 vext1 <1,1,0,1>, LHS - 2556781355U, // <1,0,1,1>: Cost 3 vext1 <1,1,0,1>, <1,1,0,1> - 1616003174U, // <1,0,1,2>: Cost 2 vext3 <0,u,1,1>, LHS - 3693052888U, // <1,0,1,3>: Cost 4 vext2 <0,3,1,0>, <1,3,1,3> - 2556783926U, // <1,0,1,4>: Cost 3 vext1 <1,1,0,1>, RHS - 2580672143U, // <1,0,1,5>: Cost 3 vext1 <5,1,0,1>, <5,1,0,1> - 2724839566U, // <1,0,1,6>: Cost 3 vext3 <6,7,0,1>, <0,1,6,7> - 3654415354U, // <1,0,1,7>: Cost 4 vext1 <5,1,0,1>, <7,0,1,2> - 1616003228U, // <1,0,1,u>: Cost 2 vext3 <0,u,1,1>, LHS - 2685690019U, // <1,0,2,0>: Cost 3 vext3 <0,2,0,1>, <0,2,0,1> - 2685763756U, // <1,0,2,1>: Cost 3 vext3 <0,2,1,1>, <0,2,1,1> - 2698297524U, // <1,0,2,2>: Cost 3 vext3 <2,3,0,1>, <0,2,2,0> - 2685911230U, // <1,0,2,3>: Cost 3 vext3 <0,2,3,1>, <0,2,3,1> - 2689745100U, // <1,0,2,4>: Cost 3 vext3 <0,u,1,1>, <0,2,4,6> - 3764814038U, // <1,0,2,5>: Cost 4 vext3 <1,1,1,1>, <0,2,5,7> - 2724839640U, // <1,0,2,6>: Cost 3 vext3 <6,7,0,1>, <0,2,6,0> - 2592625658U, // <1,0,2,7>: Cost 3 vext1 <7,1,0,2>, <7,0,1,2> - 2686279915U, // <1,0,2,u>: Cost 3 vext3 <0,2,u,1>, <0,2,u,1> - 3087843328U, // <1,0,3,0>: Cost 3 vtrnr LHS, <0,0,0,0> - 3087843338U, // <1,0,3,1>: Cost 3 vtrnr LHS, <0,0,1,1> - 67944550U, // <1,0,3,2>: Cost 1 vrev LHS - 2568743135U, // <1,0,3,3>: Cost 3 vext1 <3,1,0,3>, <3,1,0,3> - 2562772278U, // <1,0,3,4>: Cost 3 vext1 <2,1,0,3>, RHS - 4099850454U, // <1,0,3,5>: Cost 4 vtrnl <1,0,3,2>, <0,2,5,7> - 3704998538U, // <1,0,3,6>: Cost 4 vext2 <2,3,1,0>, <3,6,2,7> - 2592633923U, // <1,0,3,7>: Cost 3 vext1 <7,1,0,3>, <7,1,0,3> - 68386972U, // <1,0,3,u>: Cost 1 vrev LHS - 2620640146U, // <1,0,4,0>: Cost 3 vext2 <0,5,1,0>, <4,0,5,1> - 2689745234U, // <1,0,4,1>: Cost 3 vext3 <0,u,1,1>, <0,4,1,5> - 2689745244U, // <1,0,4,2>: Cost 3 vext3 <0,u,1,1>, <0,4,2,6> - 3760980320U, // <1,0,4,3>: Cost 4 vext3 <0,4,3,1>, <0,4,3,1> - 3761054057U, // <1,0,4,4>: Cost 4 vext3 <0,4,4,1>, <0,4,4,1> - 2619313462U, // <1,0,4,5>: Cost 3 vext2 <0,3,1,0>, RHS - 3761201531U, // <1,0,4,6>: Cost 4 vext3 <0,4,6,1>, <0,4,6,1> - 3666383940U, // <1,0,4,7>: Cost 4 vext1 <7,1,0,4>, <7,1,0,4> - 2619313705U, // <1,0,4,u>: Cost 3 vext2 <0,3,1,0>, RHS - 4029300736U, // <1,0,5,0>: Cost 4 vzipr <0,4,1,5>, <0,0,0,0> - 2895249510U, // <1,0,5,1>: Cost 3 vzipl <1,5,3,7>, LHS - 3028287590U, // <1,0,5,2>: Cost 3 vtrnl <1,3,5,7>, LHS - 3642501345U, // <1,0,5,3>: Cost 4 vext1 <3,1,0,5>, <3,1,0,5> - 2215592058U, // <1,0,5,4>: Cost 3 vrev <0,1,4,5> - 3724242907U, // <1,0,5,5>: Cost 4 vext2 <5,5,1,0>, <5,5,1,0> - 3724906540U, // <1,0,5,6>: Cost 4 vext2 <5,6,1,0>, <5,6,1,0> - 3911118134U, // <1,0,5,7>: Cost 4 vuzpr <3,1,3,0>, RHS - 3028287644U, // <1,0,5,u>: Cost 3 vtrnl <1,3,5,7>, LHS - 3762086375U, // <1,0,6,0>: Cost 4 vext3 <0,6,0,1>, <0,6,0,1> - 2698297846U, // <1,0,6,1>: Cost 3 vext3 <2,3,0,1>, <0,6,1,7> - 3760022015U, // <1,0,6,2>: Cost 4 vext3 <0,2,u,1>, <0,6,2,7> - 3642509538U, // <1,0,6,3>: Cost 4 vext1 <3,1,0,6>, <3,1,0,6> - 3762381323U, // <1,0,6,4>: Cost 4 vext3 <0,6,4,1>, <0,6,4,1> - 3730215604U, // <1,0,6,5>: Cost 4 vext2 <6,5,1,0>, <6,5,1,0> - 3730879237U, // <1,0,6,6>: Cost 4 vext2 <6,6,1,0>, <6,6,1,0> - 2657801046U, // <1,0,6,7>: Cost 3 vext2 <6,7,1,0>, <6,7,1,0> - 2658464679U, // <1,0,6,u>: Cost 3 vext2 <6,u,1,0>, <6,u,1,0> - 2659128312U, // <1,0,7,0>: Cost 3 vext2 <7,0,1,0>, <7,0,1,0> - 4047898278U, // <1,0,7,1>: Cost 4 vzipr <3,5,1,7>, <2,3,0,1> - 2215460970U, // <1,0,7,2>: Cost 3 vrev <0,1,2,7> - 3734861035U, // <1,0,7,3>: Cost 4 vext2 <7,3,1,0>, <7,3,1,0> - 3731543398U, // <1,0,7,4>: Cost 4 vext2 <6,7,1,0>, <7,4,5,6> - 3736188301U, // <1,0,7,5>: Cost 4 vext2 <7,5,1,0>, <7,5,1,0> - 2663110110U, // <1,0,7,6>: Cost 3 vext2 <7,6,1,0>, <7,6,1,0> - 3731543660U, // <1,0,7,7>: Cost 4 vext2 <6,7,1,0>, <7,7,7,7> - 2664437376U, // <1,0,7,u>: Cost 3 vext2 <7,u,1,0>, <7,u,1,0> - 3087884288U, // <1,0,u,0>: Cost 3 vtrnr LHS, <0,0,0,0> - 1616003730U, // <1,0,u,1>: Cost 2 vext3 <0,u,1,1>, <0,u,1,1> - 67985515U, // <1,0,u,2>: Cost 1 vrev LHS - 2689893028U, // <1,0,u,3>: Cost 3 vext3 <0,u,3,1>, <0,u,3,1> - 2689745586U, // <1,0,u,4>: Cost 3 vext3 <0,u,1,1>, <0,u,4,6> - 2619316378U, // <1,0,u,5>: Cost 3 vext2 <0,3,1,0>, RHS - 2669082807U, // <1,0,u,6>: Cost 3 vext2 , - 2592674888U, // <1,0,u,7>: Cost 3 vext1 <7,1,0,u>, <7,1,0,u> - 68427937U, // <1,0,u,u>: Cost 1 vrev LHS - 1543585802U, // <1,1,0,0>: Cost 2 vext2 <0,0,1,1>, <0,0,1,1> - 1548894310U, // <1,1,0,1>: Cost 2 vext2 <0,u,1,1>, LHS - 2618654892U, // <1,1,0,2>: Cost 3 vext2 <0,2,1,1>, <0,2,1,1> - 2689745654U, // <1,1,0,3>: Cost 3 vext3 <0,u,1,1>, <1,0,3,2> - 2622636370U, // <1,1,0,4>: Cost 3 vext2 <0,u,1,1>, <0,4,1,5> - 2620645791U, // <1,1,0,5>: Cost 3 vext2 <0,5,1,1>, <0,5,1,1> - 3696378367U, // <1,1,0,6>: Cost 4 vext2 <0,u,1,1>, <0,6,2,7> - 3666424905U, // <1,1,0,7>: Cost 4 vext1 <7,1,1,0>, <7,1,1,0> - 1548894866U, // <1,1,0,u>: Cost 2 vext2 <0,u,1,1>, <0,u,1,1> - 1483112550U, // <1,1,1,0>: Cost 2 vext1 <1,1,1,1>, LHS - 202162278U, // <1,1,1,1>: Cost 1 vdup1 LHS - 2622636950U, // <1,1,1,2>: Cost 3 vext2 <0,u,1,1>, <1,2,3,0> - 2622637016U, // <1,1,1,3>: Cost 3 vext2 <0,u,1,1>, <1,3,1,3> - 1483115830U, // <1,1,1,4>: Cost 2 vext1 <1,1,1,1>, RHS - 2622637200U, // <1,1,1,5>: Cost 3 vext2 <0,u,1,1>, <1,5,3,7> - 2622637263U, // <1,1,1,6>: Cost 3 vext2 <0,u,1,1>, <1,6,1,7> - 2592691274U, // <1,1,1,7>: Cost 3 vext1 <7,1,1,1>, <7,1,1,1> - 202162278U, // <1,1,1,u>: Cost 1 vdup1 LHS - 2550890588U, // <1,1,2,0>: Cost 3 vext1 <0,1,1,2>, <0,1,1,2> - 2617329183U, // <1,1,2,1>: Cost 3 vext2 <0,0,1,1>, <2,1,3,1> - 2622637672U, // <1,1,2,2>: Cost 3 vext2 <0,u,1,1>, <2,2,2,2> - 2622637734U, // <1,1,2,3>: Cost 3 vext2 <0,u,1,1>, <2,3,0,1> - 2550893878U, // <1,1,2,4>: Cost 3 vext1 <0,1,1,2>, RHS - 3696379744U, // <1,1,2,5>: Cost 4 vext2 <0,u,1,1>, <2,5,2,7> - 2622638010U, // <1,1,2,6>: Cost 3 vext2 <0,u,1,1>, <2,6,3,7> - 3804554170U, // <1,1,2,7>: Cost 4 vext3 <7,7,0,1>, <1,2,7,0> - 2622638139U, // <1,1,2,u>: Cost 3 vext2 <0,u,1,1>, <2,u,0,1> - 2622638230U, // <1,1,3,0>: Cost 3 vext2 <0,u,1,1>, <3,0,1,2> - 3087844148U, // <1,1,3,1>: Cost 3 vtrnr LHS, <1,1,1,1> - 4161585244U, // <1,1,3,2>: Cost 4 vtrnr LHS, <0,1,1,2> - 2014101606U, // <1,1,3,3>: Cost 2 vtrnr LHS, LHS - 2622638594U, // <1,1,3,4>: Cost 3 vext2 <0,u,1,1>, <3,4,5,6> - 2689745920U, // <1,1,3,5>: Cost 3 vext3 <0,u,1,1>, <1,3,5,7> - 3763487753U, // <1,1,3,6>: Cost 4 vext3 <0,u,1,1>, <1,3,6,7> - 2592707660U, // <1,1,3,7>: Cost 3 vext1 <7,1,1,3>, <7,1,1,3> - 2014101611U, // <1,1,3,u>: Cost 2 vtrnr LHS, LHS - 2556878950U, // <1,1,4,0>: Cost 3 vext1 <1,1,1,4>, LHS - 2221335351U, // <1,1,4,1>: Cost 3 vrev <1,1,1,4> - 3696380988U, // <1,1,4,2>: Cost 4 vext2 <0,u,1,1>, <4,2,6,0> - 3763487805U, // <1,1,4,3>: Cost 4 vext3 <0,u,1,1>, <1,4,3,5> - 2556882230U, // <1,1,4,4>: Cost 3 vext1 <1,1,1,4>, RHS - 1548897590U, // <1,1,4,5>: Cost 2 vext2 <0,u,1,1>, RHS - 2758184246U, // <1,1,4,6>: Cost 3 vuzpl <1,1,1,1>, RHS - 3666457677U, // <1,1,4,7>: Cost 4 vext1 <7,1,1,4>, <7,1,1,4> - 1548897833U, // <1,1,4,u>: Cost 2 vext2 <0,u,1,1>, RHS - 2693653615U, // <1,1,5,0>: Cost 3 vext3 <1,5,0,1>, <1,5,0,1> - 2617331408U, // <1,1,5,1>: Cost 3 vext2 <0,0,1,1>, <5,1,7,3> - 4029302934U, // <1,1,5,2>: Cost 4 vzipr <0,4,1,5>, <3,0,1,2> - 2689746064U, // <1,1,5,3>: Cost 3 vext3 <0,u,1,1>, <1,5,3,7> - 2221564755U, // <1,1,5,4>: Cost 3 vrev <1,1,4,5> - 2955559250U, // <1,1,5,5>: Cost 3 vzipr <0,4,1,5>, <0,4,1,5> - 2617331810U, // <1,1,5,6>: Cost 3 vext2 <0,0,1,1>, <5,6,7,0> - 2825293110U, // <1,1,5,7>: Cost 3 vuzpr <1,1,1,1>, RHS - 2689746109U, // <1,1,5,u>: Cost 3 vext3 <0,u,1,1>, <1,5,u,7> - 3696382241U, // <1,1,6,0>: Cost 4 vext2 <0,u,1,1>, <6,0,1,2> - 2689746127U, // <1,1,6,1>: Cost 3 vext3 <0,u,1,1>, <1,6,1,7> - 2617332218U, // <1,1,6,2>: Cost 3 vext2 <0,0,1,1>, <6,2,7,3> - 3763487969U, // <1,1,6,3>: Cost 4 vext3 <0,u,1,1>, <1,6,3,7> - 3696382605U, // <1,1,6,4>: Cost 4 vext2 <0,u,1,1>, <6,4,5,6> - 4029309266U, // <1,1,6,5>: Cost 4 vzipr <0,4,1,6>, <0,4,1,5> - 2617332536U, // <1,1,6,6>: Cost 3 vext2 <0,0,1,1>, <6,6,6,6> - 2724840702U, // <1,1,6,7>: Cost 3 vext3 <6,7,0,1>, <1,6,7,0> - 2725504263U, // <1,1,6,u>: Cost 3 vext3 <6,u,0,1>, <1,6,u,0> - 2617332720U, // <1,1,7,0>: Cost 3 vext2 <0,0,1,1>, <7,0,0,1> - 2659800138U, // <1,1,7,1>: Cost 3 vext2 <7,1,1,1>, <7,1,1,1> - 3691074717U, // <1,1,7,2>: Cost 4 vext2 <0,0,1,1>, <7,2,1,3> - 4167811174U, // <1,1,7,3>: Cost 4 vtrnr <1,1,5,7>, LHS - 2617333094U, // <1,1,7,4>: Cost 3 vext2 <0,0,1,1>, <7,4,5,6> - 3295396702U, // <1,1,7,5>: Cost 4 vrev <1,1,5,7> - 3803891014U, // <1,1,7,6>: Cost 4 vext3 <7,6,0,1>, <1,7,6,0> - 2617333356U, // <1,1,7,7>: Cost 3 vext2 <0,0,1,1>, <7,7,7,7> - 2659800138U, // <1,1,7,u>: Cost 3 vext2 <7,1,1,1>, <7,1,1,1> - 1483112550U, // <1,1,u,0>: Cost 2 vext1 <1,1,1,1>, LHS - 202162278U, // <1,1,u,1>: Cost 1 vdup1 LHS - 2622642056U, // <1,1,u,2>: Cost 3 vext2 <0,u,1,1>, - 2014142566U, // <1,1,u,3>: Cost 2 vtrnr LHS, LHS - 1483115830U, // <1,1,u,4>: Cost 2 vext1 <1,1,1,1>, RHS - 1548900506U, // <1,1,u,5>: Cost 2 vext2 <0,u,1,1>, RHS - 2622642384U, // <1,1,u,6>: Cost 3 vext2 <0,u,1,1>, - 2825293353U, // <1,1,u,7>: Cost 3 vuzpr <1,1,1,1>, RHS - 202162278U, // <1,1,u,u>: Cost 1 vdup1 LHS - 2635251712U, // <1,2,0,0>: Cost 3 vext2 <3,0,1,2>, <0,0,0,0> - 1561509990U, // <1,2,0,1>: Cost 2 vext2 <3,0,1,2>, LHS - 2618663085U, // <1,2,0,2>: Cost 3 vext2 <0,2,1,2>, <0,2,1,2> - 2696529358U, // <1,2,0,3>: Cost 3 vext3 <2,0,3,1>, <2,0,3,1> - 2635252050U, // <1,2,0,4>: Cost 3 vext2 <3,0,1,2>, <0,4,1,5> - 3769533926U, // <1,2,0,5>: Cost 4 vext3 <1,u,2,1>, <2,0,5,7> - 2621317617U, // <1,2,0,6>: Cost 3 vext2 <0,6,1,2>, <0,6,1,2> - 2659140170U, // <1,2,0,7>: Cost 3 vext2 <7,0,1,2>, <0,7,2,1> - 1561510557U, // <1,2,0,u>: Cost 2 vext2 <3,0,1,2>, LHS - 2623308516U, // <1,2,1,0>: Cost 3 vext2 <1,0,1,2>, <1,0,1,2> - 2635252532U, // <1,2,1,1>: Cost 3 vext2 <3,0,1,2>, <1,1,1,1> - 2631271318U, // <1,2,1,2>: Cost 3 vext2 <2,3,1,2>, <1,2,3,0> - 2958180454U, // <1,2,1,3>: Cost 3 vzipr <0,u,1,1>, LHS - 2550959414U, // <1,2,1,4>: Cost 3 vext1 <0,1,2,1>, RHS - 2635252880U, // <1,2,1,5>: Cost 3 vext2 <3,0,1,2>, <1,5,3,7> - 2635252952U, // <1,2,1,6>: Cost 3 vext2 <3,0,1,2>, <1,6,2,7> - 3732882731U, // <1,2,1,7>: Cost 4 vext2 <7,0,1,2>, <1,7,3,0> - 2958180459U, // <1,2,1,u>: Cost 3 vzipr <0,u,1,1>, LHS - 2629281213U, // <1,2,2,0>: Cost 3 vext2 <2,0,1,2>, <2,0,1,2> - 2635253280U, // <1,2,2,1>: Cost 3 vext2 <3,0,1,2>, <2,1,3,2> - 2618664552U, // <1,2,2,2>: Cost 3 vext2 <0,2,1,2>, <2,2,2,2> - 2689746546U, // <1,2,2,3>: Cost 3 vext3 <0,u,1,1>, <2,2,3,3> - 3764815485U, // <1,2,2,4>: Cost 4 vext3 <1,1,1,1>, <2,2,4,5> - 3760023176U, // <1,2,2,5>: Cost 4 vext3 <0,2,u,1>, <2,2,5,7> - 2635253690U, // <1,2,2,6>: Cost 3 vext2 <3,0,1,2>, <2,6,3,7> - 2659141610U, // <1,2,2,7>: Cost 3 vext2 <7,0,1,2>, <2,7,0,1> - 2689746591U, // <1,2,2,u>: Cost 3 vext3 <0,u,1,1>, <2,2,u,3> - 403488870U, // <1,2,3,0>: Cost 1 vext1 LHS, LHS - 1477231350U, // <1,2,3,1>: Cost 2 vext1 LHS, <1,0,3,2> - 1477232232U, // <1,2,3,2>: Cost 2 vext1 LHS, <2,2,2,2> - 1477233052U, // <1,2,3,3>: Cost 2 vext1 LHS, <3,3,3,3> - 403492150U, // <1,2,3,4>: Cost 1 vext1 LHS, RHS - 1525010128U, // <1,2,3,5>: Cost 2 vext1 LHS, <5,1,7,3> - 1525010938U, // <1,2,3,6>: Cost 2 vext1 LHS, <6,2,7,3> - 1525011450U, // <1,2,3,7>: Cost 2 vext1 LHS, <7,0,1,2> - 403494702U, // <1,2,3,u>: Cost 1 vext1 LHS, LHS - 2641226607U, // <1,2,4,0>: Cost 3 vext2 <4,0,1,2>, <4,0,1,2> - 3624723446U, // <1,2,4,1>: Cost 4 vext1 <0,1,2,4>, <1,3,4,6> - 3301123609U, // <1,2,4,2>: Cost 4 vrev <2,1,2,4> - 2598759198U, // <1,2,4,3>: Cost 3 vext1 , <3,u,1,2> - 2659142864U, // <1,2,4,4>: Cost 3 vext2 <7,0,1,2>, <4,4,4,4> - 1561513270U, // <1,2,4,5>: Cost 2 vext2 <3,0,1,2>, RHS - 2659143028U, // <1,2,4,6>: Cost 3 vext2 <7,0,1,2>, <4,6,4,6> - 2659143112U, // <1,2,4,7>: Cost 3 vext2 <7,0,1,2>, <4,7,5,0> - 1561513513U, // <1,2,4,u>: Cost 2 vext2 <3,0,1,2>, RHS - 2550988902U, // <1,2,5,0>: Cost 3 vext1 <0,1,2,5>, LHS - 2550989824U, // <1,2,5,1>: Cost 3 vext1 <0,1,2,5>, <1,3,5,7> - 3624732264U, // <1,2,5,2>: Cost 4 vext1 <0,1,2,5>, <2,2,2,2> - 2955559014U, // <1,2,5,3>: Cost 3 vzipr <0,4,1,5>, LHS - 2550992182U, // <1,2,5,4>: Cost 3 vext1 <0,1,2,5>, RHS - 2659143684U, // <1,2,5,5>: Cost 3 vext2 <7,0,1,2>, <5,5,5,5> - 2659143778U, // <1,2,5,6>: Cost 3 vext2 <7,0,1,2>, <5,6,7,0> - 2659143848U, // <1,2,5,7>: Cost 3 vext2 <7,0,1,2>, <5,7,5,7> - 2550994734U, // <1,2,5,u>: Cost 3 vext1 <0,1,2,5>, LHS - 2700289945U, // <1,2,6,0>: Cost 3 vext3 <2,6,0,1>, <2,6,0,1> - 2635256232U, // <1,2,6,1>: Cost 3 vext2 <3,0,1,2>, <6,1,7,2> - 2659144186U, // <1,2,6,2>: Cost 3 vext2 <7,0,1,2>, <6,2,7,3> - 2689746874U, // <1,2,6,3>: Cost 3 vext3 <0,u,1,1>, <2,6,3,7> - 3763488705U, // <1,2,6,4>: Cost 4 vext3 <0,u,1,1>, <2,6,4,5> - 3763488716U, // <1,2,6,5>: Cost 4 vext3 <0,u,1,1>, <2,6,5,7> - 2659144504U, // <1,2,6,6>: Cost 3 vext2 <7,0,1,2>, <6,6,6,6> - 2657817432U, // <1,2,6,7>: Cost 3 vext2 <6,7,1,2>, <6,7,1,2> - 2689746919U, // <1,2,6,u>: Cost 3 vext3 <0,u,1,1>, <2,6,u,7> - 1585402874U, // <1,2,7,0>: Cost 2 vext2 <7,0,1,2>, <7,0,1,2> - 2659144770U, // <1,2,7,1>: Cost 3 vext2 <7,0,1,2>, <7,1,0,2> - 3708998858U, // <1,2,7,2>: Cost 4 vext2 <3,0,1,2>, <7,2,6,3> - 2635257059U, // <1,2,7,3>: Cost 3 vext2 <3,0,1,2>, <7,3,0,1> - 2659145062U, // <1,2,7,4>: Cost 3 vext2 <7,0,1,2>, <7,4,5,6> - 3732886916U, // <1,2,7,5>: Cost 4 vext2 <7,0,1,2>, <7,5,0,0> - 3732886998U, // <1,2,7,6>: Cost 4 vext2 <7,0,1,2>, <7,6,0,1> - 2659145255U, // <1,2,7,7>: Cost 3 vext2 <7,0,1,2>, <7,7,0,1> - 1590711938U, // <1,2,7,u>: Cost 2 vext2 <7,u,1,2>, <7,u,1,2> - 403529835U, // <1,2,u,0>: Cost 1 vext1 LHS, LHS - 1477272310U, // <1,2,u,1>: Cost 2 vext1 LHS, <1,0,3,2> - 1477273192U, // <1,2,u,2>: Cost 2 vext1 LHS, <2,2,2,2> - 1477273750U, // <1,2,u,3>: Cost 2 vext1 LHS, <3,0,1,2> - 403533110U, // <1,2,u,4>: Cost 1 vext1 LHS, RHS - 1561516186U, // <1,2,u,5>: Cost 2 vext2 <3,0,1,2>, RHS - 1525051898U, // <1,2,u,6>: Cost 2 vext1 LHS, <6,2,7,3> - 1525052410U, // <1,2,u,7>: Cost 2 vext1 LHS, <7,0,1,2> - 403535662U, // <1,2,u,u>: Cost 1 vext1 LHS, LHS - 2819407872U, // <1,3,0,0>: Cost 3 vuzpr LHS, <0,0,0,0> - 1551564902U, // <1,3,0,1>: Cost 2 vext2 <1,3,1,3>, LHS - 2819408630U, // <1,3,0,2>: Cost 3 vuzpr LHS, <1,0,3,2> - 2619334911U, // <1,3,0,3>: Cost 3 vext2 <0,3,1,3>, <0,3,1,3> - 2625306962U, // <1,3,0,4>: Cost 3 vext2 <1,3,1,3>, <0,4,1,5> - 3832725879U, // <1,3,0,5>: Cost 4 vuzpl <1,2,3,0>, <0,4,5,6> - 3699048959U, // <1,3,0,6>: Cost 4 vext2 <1,3,1,3>, <0,6,2,7> - 3776538827U, // <1,3,0,7>: Cost 4 vext3 <3,0,7,1>, <3,0,7,1> - 1551565469U, // <1,3,0,u>: Cost 2 vext2 <1,3,1,3>, LHS - 2618671862U, // <1,3,1,0>: Cost 3 vext2 <0,2,1,3>, <1,0,3,2> - 2819408692U, // <1,3,1,1>: Cost 3 vuzpr LHS, <1,1,1,1> - 2624643975U, // <1,3,1,2>: Cost 3 vext2 <1,2,1,3>, <1,2,1,3> - 1745666150U, // <1,3,1,3>: Cost 2 vuzpr LHS, LHS - 2557005110U, // <1,3,1,4>: Cost 3 vext1 <1,1,3,1>, RHS - 2625307792U, // <1,3,1,5>: Cost 3 vext2 <1,3,1,3>, <1,5,3,7> - 3698386127U, // <1,3,1,6>: Cost 4 vext2 <1,2,1,3>, <1,6,1,7> - 2592838748U, // <1,3,1,7>: Cost 3 vext1 <7,1,3,1>, <7,1,3,1> - 1745666155U, // <1,3,1,u>: Cost 2 vuzpr LHS, LHS - 2819408790U, // <1,3,2,0>: Cost 3 vuzpr LHS, <1,2,3,0> - 2625308193U, // <1,3,2,1>: Cost 3 vext2 <1,3,1,3>, <2,1,3,3> - 2819408036U, // <1,3,2,2>: Cost 3 vuzpr LHS, <0,2,0,2> - 2819851890U, // <1,3,2,3>: Cost 3 vuzpr LHS, <2,2,3,3> - 2819408794U, // <1,3,2,4>: Cost 3 vuzpr LHS, <1,2,3,4> - 3893149890U, // <1,3,2,5>: Cost 4 vuzpr LHS, <0,2,3,5> - 2819408076U, // <1,3,2,6>: Cost 3 vuzpr LHS, <0,2,4,6> - 3772041583U, // <1,3,2,7>: Cost 4 vext3 <2,3,0,1>, <3,2,7,3> - 2819408042U, // <1,3,2,u>: Cost 3 vuzpr LHS, <0,2,0,u> - 1483276390U, // <1,3,3,0>: Cost 2 vext1 <1,1,3,3>, LHS - 1483277128U, // <1,3,3,1>: Cost 2 vext1 <1,1,3,3>, <1,1,3,3> - 2557019752U, // <1,3,3,2>: Cost 3 vext1 <1,1,3,3>, <2,2,2,2> - 2819408856U, // <1,3,3,3>: Cost 3 vuzpr LHS, <1,3,1,3> - 1483279670U, // <1,3,3,4>: Cost 2 vext1 <1,1,3,3>, RHS - 2819409614U, // <1,3,3,5>: Cost 3 vuzpr LHS, <2,3,4,5> - 2598826490U, // <1,3,3,6>: Cost 3 vext1 , <6,2,7,3> - 3087844352U, // <1,3,3,7>: Cost 3 vtrnr LHS, <1,3,5,7> - 1483282222U, // <1,3,3,u>: Cost 2 vext1 <1,1,3,3>, LHS - 2568970342U, // <1,3,4,0>: Cost 3 vext1 <3,1,3,4>, LHS - 2568971224U, // <1,3,4,1>: Cost 3 vext1 <3,1,3,4>, <1,3,1,3> - 3832761290U, // <1,3,4,2>: Cost 4 vuzpl <1,2,3,4>, <4,1,2,3> - 2233428219U, // <1,3,4,3>: Cost 3 vrev <3,1,3,4> - 2568973622U, // <1,3,4,4>: Cost 3 vext1 <3,1,3,4>, RHS - 1551568182U, // <1,3,4,5>: Cost 2 vext2 <1,3,1,3>, RHS - 2819410434U, // <1,3,4,6>: Cost 3 vuzpr LHS, <3,4,5,6> - 3666605151U, // <1,3,4,7>: Cost 4 vext1 <7,1,3,4>, <7,1,3,4> - 1551568425U, // <1,3,4,u>: Cost 2 vext2 <1,3,1,3>, RHS - 2563006566U, // <1,3,5,0>: Cost 3 vext1 <2,1,3,5>, LHS - 2568979456U, // <1,3,5,1>: Cost 3 vext1 <3,1,3,5>, <1,3,5,7> - 2563008035U, // <1,3,5,2>: Cost 3 vext1 <2,1,3,5>, <2,1,3,5> - 2233436412U, // <1,3,5,3>: Cost 3 vrev <3,1,3,5> - 2563009846U, // <1,3,5,4>: Cost 3 vext1 <2,1,3,5>, RHS - 2867187716U, // <1,3,5,5>: Cost 3 vuzpr LHS, <5,5,5,5> - 2655834214U, // <1,3,5,6>: Cost 3 vext2 <6,4,1,3>, <5,6,7,4> - 1745669430U, // <1,3,5,7>: Cost 2 vuzpr LHS, RHS - 1745669431U, // <1,3,5,u>: Cost 2 vuzpr LHS, RHS - 2867187810U, // <1,3,6,0>: Cost 3 vuzpr LHS, <5,6,7,0> - 3699052931U, // <1,3,6,1>: Cost 4 vext2 <1,3,1,3>, <6,1,3,1> - 2654507460U, // <1,3,6,2>: Cost 3 vext2 <6,2,1,3>, <6,2,1,3> - 3766291091U, // <1,3,6,3>: Cost 4 vext3 <1,3,3,1>, <3,6,3,7> - 2655834726U, // <1,3,6,4>: Cost 3 vext2 <6,4,1,3>, <6,4,1,3> - 3923384562U, // <1,3,6,5>: Cost 4 vuzpr <5,1,7,3>, - 2657161992U, // <1,3,6,6>: Cost 3 vext2 <6,6,1,3>, <6,6,1,3> - 2819852218U, // <1,3,6,7>: Cost 3 vuzpr LHS, <2,6,3,7> - 2819852219U, // <1,3,6,u>: Cost 3 vuzpr LHS, <2,6,3,u> - 2706926275U, // <1,3,7,0>: Cost 3 vext3 <3,7,0,1>, <3,7,0,1> - 2659816524U, // <1,3,7,1>: Cost 3 vext2 <7,1,1,3>, <7,1,1,3> - 3636766245U, // <1,3,7,2>: Cost 4 vext1 <2,1,3,7>, <2,1,3,7> - 2867187903U, // <1,3,7,3>: Cost 3 vuzpr LHS, <5,7,u,3> - 2625312102U, // <1,3,7,4>: Cost 3 vext2 <1,3,1,3>, <7,4,5,6> - 2867188598U, // <1,3,7,5>: Cost 3 vuzpr LHS, <6,7,4,5> - 3728250344U, // <1,3,7,6>: Cost 4 vext2 <6,2,1,3>, <7,6,2,1> - 2867187880U, // <1,3,7,7>: Cost 3 vuzpr LHS, <5,7,5,7> - 2707516171U, // <1,3,7,u>: Cost 3 vext3 <3,7,u,1>, <3,7,u,1> - 1483317350U, // <1,3,u,0>: Cost 2 vext1 <1,1,3,u>, LHS - 1483318093U, // <1,3,u,1>: Cost 2 vext1 <1,1,3,u>, <1,1,3,u> - 2819410718U, // <1,3,u,2>: Cost 3 vuzpr LHS, <3,u,1,2> - 1745666717U, // <1,3,u,3>: Cost 2 vuzpr LHS, LHS - 1483320630U, // <1,3,u,4>: Cost 2 vext1 <1,1,3,u>, RHS - 1551571098U, // <1,3,u,5>: Cost 2 vext2 <1,3,1,3>, RHS - 2819410758U, // <1,3,u,6>: Cost 3 vuzpr LHS, <3,u,5,6> - 1745669673U, // <1,3,u,7>: Cost 2 vuzpr LHS, RHS - 1745666722U, // <1,3,u,u>: Cost 2 vuzpr LHS, LHS - 2617352205U, // <1,4,0,0>: Cost 3 vext2 <0,0,1,4>, <0,0,1,4> - 2619342950U, // <1,4,0,1>: Cost 3 vext2 <0,3,1,4>, LHS - 3692421295U, // <1,4,0,2>: Cost 4 vext2 <0,2,1,4>, <0,2,1,4> - 2619343104U, // <1,4,0,3>: Cost 3 vext2 <0,3,1,4>, <0,3,1,4> - 2617352530U, // <1,4,0,4>: Cost 3 vext2 <0,0,1,4>, <0,4,1,5> - 1634880402U, // <1,4,0,5>: Cost 2 vext3 <4,0,5,1>, <4,0,5,1> - 2713930652U, // <1,4,0,6>: Cost 3 vext3 <4,u,5,1>, <4,0,6,2> - 3732898396U, // <1,4,0,7>: Cost 4 vext2 <7,0,1,4>, <0,7,4,1> - 1635101613U, // <1,4,0,u>: Cost 2 vext3 <4,0,u,1>, <4,0,u,1> - 3693085430U, // <1,4,1,0>: Cost 4 vext2 <0,3,1,4>, <1,0,3,2> - 2623988535U, // <1,4,1,1>: Cost 3 vext2 <1,1,1,4>, <1,1,1,4> - 3693085590U, // <1,4,1,2>: Cost 4 vext2 <0,3,1,4>, <1,2,3,0> - 3692422134U, // <1,4,1,3>: Cost 4 vext2 <0,2,1,4>, <1,3,4,6> - 3693085726U, // <1,4,1,4>: Cost 4 vext2 <0,3,1,4>, <1,4,0,1> - 2892401974U, // <1,4,1,5>: Cost 3 vzipl <1,1,1,1>, RHS - 3026619702U, // <1,4,1,6>: Cost 3 vtrnl <1,1,1,1>, RHS - 3800206324U, // <1,4,1,7>: Cost 4 vext3 <7,0,4,1>, <4,1,7,0> - 2892402217U, // <1,4,1,u>: Cost 3 vzipl <1,1,1,1>, RHS - 3966978927U, // <1,4,2,0>: Cost 4 vzipl <1,2,3,4>, <4,0,1,2> - 3966979018U, // <1,4,2,1>: Cost 4 vzipl <1,2,3,4>, <4,1,2,3> - 3693086312U, // <1,4,2,2>: Cost 4 vext2 <0,3,1,4>, <2,2,2,2> - 2635269798U, // <1,4,2,3>: Cost 3 vext2 <3,0,1,4>, <2,3,0,1> - 3966979280U, // <1,4,2,4>: Cost 4 vzipl <1,2,3,4>, <4,4,4,4> - 2893204790U, // <1,4,2,5>: Cost 3 vzipl <1,2,3,0>, RHS - 3693086650U, // <1,4,2,6>: Cost 4 vext2 <0,3,1,4>, <2,6,3,7> - 3666662502U, // <1,4,2,7>: Cost 4 vext1 <7,1,4,2>, <7,1,4,2> - 2893205033U, // <1,4,2,u>: Cost 3 vzipl <1,2,3,0>, RHS - 2563063910U, // <1,4,3,0>: Cost 3 vext1 <2,1,4,3>, LHS - 2563064730U, // <1,4,3,1>: Cost 3 vext1 <2,1,4,3>, <1,2,3,4> - 2563065386U, // <1,4,3,2>: Cost 3 vext1 <2,1,4,3>, <2,1,4,3> - 3693087132U, // <1,4,3,3>: Cost 4 vext2 <0,3,1,4>, <3,3,3,3> - 2619345410U, // <1,4,3,4>: Cost 3 vext2 <0,3,1,4>, <3,4,5,6> - 3087843666U, // <1,4,3,5>: Cost 3 vtrnr LHS, <0,4,1,5> - 3087843676U, // <1,4,3,6>: Cost 3 vtrnr LHS, <0,4,2,6> - 3666670695U, // <1,4,3,7>: Cost 4 vext1 <7,1,4,3>, <7,1,4,3> - 3087843669U, // <1,4,3,u>: Cost 3 vtrnr LHS, <0,4,1,u> - 2620672914U, // <1,4,4,0>: Cost 3 vext2 <0,5,1,4>, <4,0,5,1> - 3630842706U, // <1,4,4,1>: Cost 4 vext1 <1,1,4,4>, <1,1,4,4> - 3313069003U, // <1,4,4,2>: Cost 4 vrev <4,1,2,4> - 3642788100U, // <1,4,4,3>: Cost 4 vext1 <3,1,4,4>, <3,1,4,4> - 2713930960U, // <1,4,4,4>: Cost 3 vext3 <4,u,5,1>, <4,4,4,4> - 2619346230U, // <1,4,4,5>: Cost 3 vext2 <0,3,1,4>, RHS - 2713930980U, // <1,4,4,6>: Cost 3 vext3 <4,u,5,1>, <4,4,6,6> - 3736882642U, // <1,4,4,7>: Cost 4 vext2 <7,6,1,4>, <4,7,6,1> - 2619346473U, // <1,4,4,u>: Cost 3 vext2 <0,3,1,4>, RHS - 2557108326U, // <1,4,5,0>: Cost 3 vext1 <1,1,4,5>, LHS - 2557109075U, // <1,4,5,1>: Cost 3 vext1 <1,1,4,5>, <1,1,4,5> - 2598913774U, // <1,4,5,2>: Cost 3 vext1 , <2,3,u,1> - 3630852246U, // <1,4,5,3>: Cost 4 vext1 <1,1,4,5>, <3,0,1,2> - 2557111606U, // <1,4,5,4>: Cost 3 vext1 <1,1,4,5>, RHS - 2895252790U, // <1,4,5,5>: Cost 3 vzipl <1,5,3,7>, RHS - 1616006454U, // <1,4,5,6>: Cost 2 vext3 <0,u,1,1>, RHS - 3899059510U, // <1,4,5,7>: Cost 4 vuzpr <1,1,1,4>, RHS - 1616006472U, // <1,4,5,u>: Cost 2 vext3 <0,u,1,1>, RHS - 2557116518U, // <1,4,6,0>: Cost 3 vext1 <1,1,4,6>, LHS - 2557117236U, // <1,4,6,1>: Cost 3 vext1 <1,1,4,6>, <1,1,1,1> - 3630859880U, // <1,4,6,2>: Cost 4 vext1 <1,1,4,6>, <2,2,2,2> - 2569062550U, // <1,4,6,3>: Cost 3 vext1 <3,1,4,6>, <3,0,1,2> - 2557119798U, // <1,4,6,4>: Cost 3 vext1 <1,1,4,6>, RHS - 3763490174U, // <1,4,6,5>: Cost 4 vext3 <0,u,1,1>, <4,6,5,7> - 3763490183U, // <1,4,6,6>: Cost 4 vext3 <0,u,1,1>, <4,6,6,7> - 2712751498U, // <1,4,6,7>: Cost 3 vext3 <4,6,7,1>, <4,6,7,1> - 2557122350U, // <1,4,6,u>: Cost 3 vext1 <1,1,4,6>, LHS - 2659161084U, // <1,4,7,0>: Cost 3 vext2 <7,0,1,4>, <7,0,1,4> - 3732903040U, // <1,4,7,1>: Cost 4 vext2 <7,0,1,4>, <7,1,7,1> - 3734230174U, // <1,4,7,2>: Cost 4 vext2 <7,2,1,4>, <7,2,1,4> - 3734893807U, // <1,4,7,3>: Cost 4 vext2 <7,3,1,4>, <7,3,1,4> - 3660729654U, // <1,4,7,4>: Cost 4 vext1 <6,1,4,7>, RHS - 3786493384U, // <1,4,7,5>: Cost 4 vext3 <4,6,7,1>, <4,7,5,0> - 2713341394U, // <1,4,7,6>: Cost 3 vext3 <4,7,6,1>, <4,7,6,1> - 3660731386U, // <1,4,7,7>: Cost 4 vext1 <6,1,4,7>, <7,0,1,2> - 2664470148U, // <1,4,7,u>: Cost 3 vext2 <7,u,1,4>, <7,u,1,4> - 2557132902U, // <1,4,u,0>: Cost 3 vext1 <1,1,4,u>, LHS - 2619348782U, // <1,4,u,1>: Cost 3 vext2 <0,3,1,4>, LHS - 2563106351U, // <1,4,u,2>: Cost 3 vext1 <2,1,4,u>, <2,1,4,u> - 2713783816U, // <1,4,u,3>: Cost 3 vext3 <4,u,3,1>, <4,u,3,1> - 2622666815U, // <1,4,u,4>: Cost 3 vext2 <0,u,1,4>, - 1640189466U, // <1,4,u,5>: Cost 2 vext3 <4,u,5,1>, <4,u,5,1> - 1616006697U, // <1,4,u,6>: Cost 2 vext3 <0,u,1,1>, RHS - 2712751498U, // <1,4,u,7>: Cost 3 vext3 <4,6,7,1>, <4,6,7,1> - 1616006715U, // <1,4,u,u>: Cost 2 vext3 <0,u,1,1>, RHS - 2620014592U, // <1,5,0,0>: Cost 3 vext2 <0,4,1,5>, <0,0,0,0> - 1546272870U, // <1,5,0,1>: Cost 2 vext2 <0,4,1,5>, LHS - 2618687664U, // <1,5,0,2>: Cost 3 vext2 <0,2,1,5>, <0,2,1,5> - 3693093120U, // <1,5,0,3>: Cost 4 vext2 <0,3,1,5>, <0,3,1,4> - 1546273106U, // <1,5,0,4>: Cost 2 vext2 <0,4,1,5>, <0,4,1,5> - 2620678563U, // <1,5,0,5>: Cost 3 vext2 <0,5,1,5>, <0,5,1,5> - 2714668660U, // <1,5,0,6>: Cost 3 vext3 <5,0,6,1>, <5,0,6,1> - 3772042877U, // <1,5,0,7>: Cost 4 vext3 <2,3,0,1>, <5,0,7,1> - 1546273437U, // <1,5,0,u>: Cost 2 vext2 <0,4,1,5>, LHS - 2620015350U, // <1,5,1,0>: Cost 3 vext2 <0,4,1,5>, <1,0,3,2> - 2620015412U, // <1,5,1,1>: Cost 3 vext2 <0,4,1,5>, <1,1,1,1> - 2620015510U, // <1,5,1,2>: Cost 3 vext2 <0,4,1,5>, <1,2,3,0> - 2618688512U, // <1,5,1,3>: Cost 3 vext2 <0,2,1,5>, <1,3,5,7> - 2620015677U, // <1,5,1,4>: Cost 3 vext2 <0,4,1,5>, <1,4,3,5> - 2620015727U, // <1,5,1,5>: Cost 3 vext2 <0,4,1,5>, <1,5,0,1> - 2620015859U, // <1,5,1,6>: Cost 3 vext2 <0,4,1,5>, <1,6,5,7> - 3093728566U, // <1,5,1,7>: Cost 3 vtrnr <1,1,1,1>, RHS - 2620015981U, // <1,5,1,u>: Cost 3 vext2 <0,4,1,5>, <1,u,1,3> - 3692430816U, // <1,5,2,0>: Cost 4 vext2 <0,2,1,5>, <2,0,5,1> - 2620016163U, // <1,5,2,1>: Cost 3 vext2 <0,4,1,5>, <2,1,3,5> - 2620016232U, // <1,5,2,2>: Cost 3 vext2 <0,4,1,5>, <2,2,2,2> - 2620016294U, // <1,5,2,3>: Cost 3 vext2 <0,4,1,5>, <2,3,0,1> - 3693758221U, // <1,5,2,4>: Cost 4 vext2 <0,4,1,5>, <2,4,2,5> - 3692431209U, // <1,5,2,5>: Cost 4 vext2 <0,2,1,5>, <2,5,3,7> - 2620016570U, // <1,5,2,6>: Cost 3 vext2 <0,4,1,5>, <2,6,3,7> - 4173598006U, // <1,5,2,7>: Cost 4 vtrnr <2,1,3,2>, RHS - 2620016699U, // <1,5,2,u>: Cost 3 vext2 <0,4,1,5>, <2,u,0,1> - 2620016790U, // <1,5,3,0>: Cost 3 vext2 <0,4,1,5>, <3,0,1,2> - 2569110672U, // <1,5,3,1>: Cost 3 vext1 <3,1,5,3>, <1,5,3,7> - 3693758785U, // <1,5,3,2>: Cost 4 vext2 <0,4,1,5>, <3,2,2,2> - 2620017052U, // <1,5,3,3>: Cost 3 vext2 <0,4,1,5>, <3,3,3,3> - 2620017154U, // <1,5,3,4>: Cost 3 vext2 <0,4,1,5>, <3,4,5,6> - 3135623172U, // <1,5,3,5>: Cost 3 vtrnr LHS, <5,5,5,5> - 4161587048U, // <1,5,3,6>: Cost 4 vtrnr LHS, <2,5,3,6> - 2014104886U, // <1,5,3,7>: Cost 2 vtrnr LHS, RHS - 2014104887U, // <1,5,3,u>: Cost 2 vtrnr LHS, RHS - 2620017554U, // <1,5,4,0>: Cost 3 vext2 <0,4,1,5>, <4,0,5,1> - 2620017634U, // <1,5,4,1>: Cost 3 vext2 <0,4,1,5>, <4,1,5,0> - 3693759551U, // <1,5,4,2>: Cost 4 vext2 <0,4,1,5>, <4,2,6,3> - 3642861837U, // <1,5,4,3>: Cost 4 vext1 <3,1,5,4>, <3,1,5,4> - 2575092710U, // <1,5,4,4>: Cost 3 vext1 <4,1,5,4>, <4,1,5,4> - 1546276150U, // <1,5,4,5>: Cost 2 vext2 <0,4,1,5>, RHS - 2759855414U, // <1,5,4,6>: Cost 3 vuzpl <1,3,5,7>, RHS - 2713931718U, // <1,5,4,7>: Cost 3 vext3 <4,u,5,1>, <5,4,7,6> - 1546276393U, // <1,5,4,u>: Cost 2 vext2 <0,4,1,5>, RHS - 2557182054U, // <1,5,5,0>: Cost 3 vext1 <1,1,5,5>, LHS - 2557182812U, // <1,5,5,1>: Cost 3 vext1 <1,1,5,5>, <1,1,5,5> - 3630925347U, // <1,5,5,2>: Cost 4 vext1 <1,1,5,5>, <2,1,3,5> - 4029301675U, // <1,5,5,3>: Cost 4 vzipr <0,4,1,5>, <1,2,5,3> - 2557185334U, // <1,5,5,4>: Cost 3 vext1 <1,1,5,5>, RHS - 2713931780U, // <1,5,5,5>: Cost 3 vext3 <4,u,5,1>, <5,5,5,5> - 2667794530U, // <1,5,5,6>: Cost 3 vext2 , <5,6,7,0> - 2713931800U, // <1,5,5,7>: Cost 3 vext3 <4,u,5,1>, <5,5,7,7> - 2557187886U, // <1,5,5,u>: Cost 3 vext1 <1,1,5,5>, LHS - 2718208036U, // <1,5,6,0>: Cost 3 vext3 <5,6,0,1>, <5,6,0,1> - 2620019115U, // <1,5,6,1>: Cost 3 vext2 <0,4,1,5>, <6,1,7,5> - 2667794938U, // <1,5,6,2>: Cost 3 vext2 , <6,2,7,3> - 3787673666U, // <1,5,6,3>: Cost 4 vext3 <4,u,5,1>, <5,6,3,4> - 3693761165U, // <1,5,6,4>: Cost 4 vext2 <0,4,1,5>, <6,4,5,6> - 3319279297U, // <1,5,6,5>: Cost 4 vrev <5,1,5,6> - 2667795256U, // <1,5,6,6>: Cost 3 vext2 , <6,6,6,6> - 2713931874U, // <1,5,6,7>: Cost 3 vext3 <4,u,5,1>, <5,6,7,0> - 2713931883U, // <1,5,6,u>: Cost 3 vext3 <4,u,5,1>, <5,6,u,0> - 2557198438U, // <1,5,7,0>: Cost 3 vext1 <1,1,5,7>, LHS - 2557199156U, // <1,5,7,1>: Cost 3 vext1 <1,1,5,7>, <1,1,1,1> - 2569143974U, // <1,5,7,2>: Cost 3 vext1 <3,1,5,7>, <2,3,0,1> - 2569144592U, // <1,5,7,3>: Cost 3 vext1 <3,1,5,7>, <3,1,5,7> - 2557201718U, // <1,5,7,4>: Cost 3 vext1 <1,1,5,7>, RHS - 2713931944U, // <1,5,7,5>: Cost 3 vext3 <4,u,5,1>, <5,7,5,7> - 3787673770U, // <1,5,7,6>: Cost 4 vext3 <4,u,5,1>, <5,7,6,0> - 2719387828U, // <1,5,7,7>: Cost 3 vext3 <5,7,7,1>, <5,7,7,1> - 2557204270U, // <1,5,7,u>: Cost 3 vext1 <1,1,5,7>, LHS - 2620020435U, // <1,5,u,0>: Cost 3 vext2 <0,4,1,5>, - 1546278702U, // <1,5,u,1>: Cost 2 vext2 <0,4,1,5>, LHS - 2620020616U, // <1,5,u,2>: Cost 3 vext2 <0,4,1,5>, - 2620020668U, // <1,5,u,3>: Cost 3 vext2 <0,4,1,5>, - 1594054682U, // <1,5,u,4>: Cost 2 vext2 , - 1546279066U, // <1,5,u,5>: Cost 2 vext2 <0,4,1,5>, RHS - 2620020944U, // <1,5,u,6>: Cost 3 vext2 <0,4,1,5>, - 2014145846U, // <1,5,u,7>: Cost 2 vtrnr LHS, RHS - 2014145847U, // <1,5,u,u>: Cost 2 vtrnr LHS, RHS - 3692437504U, // <1,6,0,0>: Cost 4 vext2 <0,2,1,6>, <0,0,0,0> - 2618695782U, // <1,6,0,1>: Cost 3 vext2 <0,2,1,6>, LHS - 2618695857U, // <1,6,0,2>: Cost 3 vext2 <0,2,1,6>, <0,2,1,6> - 3794161970U, // <1,6,0,3>: Cost 4 vext3 <6,0,3,1>, <6,0,3,1> - 2620023122U, // <1,6,0,4>: Cost 3 vext2 <0,4,1,6>, <0,4,1,5> - 2620686756U, // <1,6,0,5>: Cost 3 vext2 <0,5,1,6>, <0,5,1,6> - 2621350389U, // <1,6,0,6>: Cost 3 vext2 <0,6,1,6>, <0,6,1,6> - 4028599606U, // <1,6,0,7>: Cost 4 vzipr <0,3,1,0>, RHS - 2618696349U, // <1,6,0,u>: Cost 3 vext2 <0,2,1,6>, LHS - 3692438262U, // <1,6,1,0>: Cost 4 vext2 <0,2,1,6>, <1,0,3,2> - 2625995572U, // <1,6,1,1>: Cost 3 vext2 <1,4,1,6>, <1,1,1,1> - 3692438422U, // <1,6,1,2>: Cost 4 vext2 <0,2,1,6>, <1,2,3,0> - 3692438488U, // <1,6,1,3>: Cost 4 vext2 <0,2,1,6>, <1,3,1,3> - 2625995820U, // <1,6,1,4>: Cost 3 vext2 <1,4,1,6>, <1,4,1,6> - 3692438672U, // <1,6,1,5>: Cost 4 vext2 <0,2,1,6>, <1,5,3,7> - 3692438720U, // <1,6,1,6>: Cost 4 vext2 <0,2,1,6>, <1,6,0,1> - 2958183734U, // <1,6,1,7>: Cost 3 vzipr <0,u,1,1>, RHS - 2958183735U, // <1,6,1,u>: Cost 3 vzipr <0,u,1,1>, RHS - 2721526201U, // <1,6,2,0>: Cost 3 vext3 <6,2,0,1>, <6,2,0,1> - 3692439097U, // <1,6,2,1>: Cost 4 vext2 <0,2,1,6>, <2,1,6,0> - 3692439144U, // <1,6,2,2>: Cost 4 vext2 <0,2,1,6>, <2,2,2,2> - 3692439206U, // <1,6,2,3>: Cost 4 vext2 <0,2,1,6>, <2,3,0,1> - 3636948278U, // <1,6,2,4>: Cost 4 vext1 <2,1,6,2>, RHS - 3787674092U, // <1,6,2,5>: Cost 4 vext3 <4,u,5,1>, <6,2,5,7> - 2618697658U, // <1,6,2,6>: Cost 3 vext2 <0,2,1,6>, <2,6,3,7> - 2970799414U, // <1,6,2,7>: Cost 3 vzipr <3,0,1,2>, RHS - 2970799415U, // <1,6,2,u>: Cost 3 vzipr <3,0,1,2>, RHS - 2563211366U, // <1,6,3,0>: Cost 3 vext1 <2,1,6,3>, LHS - 3699738854U, // <1,6,3,1>: Cost 4 vext2 <1,4,1,6>, <3,1,1,1> - 2563212860U, // <1,6,3,2>: Cost 3 vext1 <2,1,6,3>, <2,1,6,3> - 3692439964U, // <1,6,3,3>: Cost 4 vext2 <0,2,1,6>, <3,3,3,3> - 2563214646U, // <1,6,3,4>: Cost 3 vext1 <2,1,6,3>, RHS - 4191820018U, // <1,6,3,5>: Cost 4 vtrnr <5,1,7,3>, - 2587103648U, // <1,6,3,6>: Cost 3 vext1 <6,1,6,3>, <6,1,6,3> - 3087845306U, // <1,6,3,7>: Cost 3 vtrnr LHS, <2,6,3,7> - 3087845307U, // <1,6,3,u>: Cost 3 vtrnr LHS, <2,6,3,u> - 3693767570U, // <1,6,4,0>: Cost 4 vext2 <0,4,1,6>, <4,0,5,1> - 3693767650U, // <1,6,4,1>: Cost 4 vext2 <0,4,1,6>, <4,1,5,0> - 3636962877U, // <1,6,4,2>: Cost 4 vext1 <2,1,6,4>, <2,1,6,4> - 3325088134U, // <1,6,4,3>: Cost 4 vrev <6,1,3,4> - 3693767898U, // <1,6,4,4>: Cost 4 vext2 <0,4,1,6>, <4,4,5,5> - 2618699062U, // <1,6,4,5>: Cost 3 vext2 <0,2,1,6>, RHS - 3833670966U, // <1,6,4,6>: Cost 4 vuzpl <1,3,6,7>, RHS - 4028632374U, // <1,6,4,7>: Cost 4 vzipr <0,3,1,4>, RHS - 2618699305U, // <1,6,4,u>: Cost 3 vext2 <0,2,1,6>, RHS - 3693768264U, // <1,6,5,0>: Cost 4 vext2 <0,4,1,6>, <5,0,1,2> - 3630998373U, // <1,6,5,1>: Cost 4 vext1 <1,1,6,5>, <1,1,6,5> - 3636971070U, // <1,6,5,2>: Cost 4 vext1 <2,1,6,5>, <2,1,6,5> - 3642943767U, // <1,6,5,3>: Cost 4 vext1 <3,1,6,5>, <3,1,6,5> - 3693768628U, // <1,6,5,4>: Cost 4 vext2 <0,4,1,6>, <5,4,5,6> - 3732918276U, // <1,6,5,5>: Cost 4 vext2 <7,0,1,6>, <5,5,5,5> - 2620690530U, // <1,6,5,6>: Cost 3 vext2 <0,5,1,6>, <5,6,7,0> - 2955562294U, // <1,6,5,7>: Cost 3 vzipr <0,4,1,5>, RHS - 2955562295U, // <1,6,5,u>: Cost 3 vzipr <0,4,1,5>, RHS - 2724180733U, // <1,6,6,0>: Cost 3 vext3 <6,6,0,1>, <6,6,0,1> - 3631006566U, // <1,6,6,1>: Cost 4 vext1 <1,1,6,6>, <1,1,6,6> - 3631007674U, // <1,6,6,2>: Cost 4 vext1 <1,1,6,6>, <2,6,3,7> - 3692442184U, // <1,6,6,3>: Cost 4 vext2 <0,2,1,6>, <6,3,7,0> - 3631009078U, // <1,6,6,4>: Cost 4 vext1 <1,1,6,6>, RHS - 3787674416U, // <1,6,6,5>: Cost 4 vext3 <4,u,5,1>, <6,6,5,7> - 2713932600U, // <1,6,6,6>: Cost 3 vext3 <4,u,5,1>, <6,6,6,6> - 2713932610U, // <1,6,6,7>: Cost 3 vext3 <4,u,5,1>, <6,6,7,7> - 2713932619U, // <1,6,6,u>: Cost 3 vext3 <4,u,5,1>, <6,6,u,7> - 1651102542U, // <1,6,7,0>: Cost 2 vext3 <6,7,0,1>, <6,7,0,1> - 2724918103U, // <1,6,7,1>: Cost 3 vext3 <6,7,1,1>, <6,7,1,1> - 2698302306U, // <1,6,7,2>: Cost 3 vext3 <2,3,0,1>, <6,7,2,3> - 3642960153U, // <1,6,7,3>: Cost 4 vext1 <3,1,6,7>, <3,1,6,7> - 2713932662U, // <1,6,7,4>: Cost 3 vext3 <4,u,5,1>, <6,7,4,5> - 2725213051U, // <1,6,7,5>: Cost 3 vext3 <6,7,5,1>, <6,7,5,1> - 2724844426U, // <1,6,7,6>: Cost 3 vext3 <6,7,0,1>, <6,7,6,7> - 4035956022U, // <1,6,7,7>: Cost 4 vzipr <1,5,1,7>, RHS - 1651692438U, // <1,6,7,u>: Cost 2 vext3 <6,7,u,1>, <6,7,u,1> - 1651766175U, // <1,6,u,0>: Cost 2 vext3 <6,u,0,1>, <6,u,0,1> - 2618701614U, // <1,6,u,1>: Cost 3 vext2 <0,2,1,6>, LHS - 3135663508U, // <1,6,u,2>: Cost 3 vtrnr LHS, <4,6,u,2> - 3692443580U, // <1,6,u,3>: Cost 4 vext2 <0,2,1,6>, - 2713932743U, // <1,6,u,4>: Cost 3 vext3 <4,u,5,1>, <6,u,4,5> - 2618701978U, // <1,6,u,5>: Cost 3 vext2 <0,2,1,6>, RHS - 2622683344U, // <1,6,u,6>: Cost 3 vext2 <0,u,1,6>, - 3087886266U, // <1,6,u,7>: Cost 3 vtrnr LHS, <2,6,3,7> - 1652356071U, // <1,6,u,u>: Cost 2 vext3 <6,u,u,1>, <6,u,u,1> - 2726171632U, // <1,7,0,0>: Cost 3 vext3 <7,0,0,1>, <7,0,0,1> - 2626666598U, // <1,7,0,1>: Cost 3 vext2 <1,5,1,7>, LHS - 3695100067U, // <1,7,0,2>: Cost 4 vext2 <0,6,1,7>, <0,2,0,1> - 3707044102U, // <1,7,0,3>: Cost 4 vext2 <2,6,1,7>, <0,3,2,1> - 2726466580U, // <1,7,0,4>: Cost 3 vext3 <7,0,4,1>, <7,0,4,1> - 3654921933U, // <1,7,0,5>: Cost 4 vext1 <5,1,7,0>, <5,1,7,0> - 2621358582U, // <1,7,0,6>: Cost 3 vext2 <0,6,1,7>, <0,6,1,7> - 2622022215U, // <1,7,0,7>: Cost 3 vext2 <0,7,1,7>, <0,7,1,7> - 2626667165U, // <1,7,0,u>: Cost 3 vext2 <1,5,1,7>, LHS - 2593128550U, // <1,7,1,0>: Cost 3 vext1 <7,1,7,1>, LHS - 2626667316U, // <1,7,1,1>: Cost 3 vext2 <1,5,1,7>, <1,1,1,1> - 3700409238U, // <1,7,1,2>: Cost 4 vext2 <1,5,1,7>, <1,2,3,0> - 2257294428U, // <1,7,1,3>: Cost 3 vrev <7,1,3,1> - 2593131830U, // <1,7,1,4>: Cost 3 vext1 <7,1,7,1>, RHS - 2626667646U, // <1,7,1,5>: Cost 3 vext2 <1,5,1,7>, <1,5,1,7> - 2627331279U, // <1,7,1,6>: Cost 3 vext2 <1,6,1,7>, <1,6,1,7> - 2593133696U, // <1,7,1,7>: Cost 3 vext1 <7,1,7,1>, <7,1,7,1> - 2628658545U, // <1,7,1,u>: Cost 3 vext2 <1,u,1,7>, <1,u,1,7> - 2587164774U, // <1,7,2,0>: Cost 3 vext1 <6,1,7,2>, LHS - 3701073445U, // <1,7,2,1>: Cost 4 vext2 <1,6,1,7>, <2,1,3,7> - 3700409960U, // <1,7,2,2>: Cost 4 vext2 <1,5,1,7>, <2,2,2,2> - 2638612134U, // <1,7,2,3>: Cost 3 vext2 <3,5,1,7>, <2,3,0,1> - 2587168054U, // <1,7,2,4>: Cost 3 vext1 <6,1,7,2>, RHS - 3706382167U, // <1,7,2,5>: Cost 4 vext2 <2,5,1,7>, <2,5,1,7> - 2587169192U, // <1,7,2,6>: Cost 3 vext1 <6,1,7,2>, <6,1,7,2> - 3660911610U, // <1,7,2,7>: Cost 4 vext1 <6,1,7,2>, <7,0,1,2> - 2587170606U, // <1,7,2,u>: Cost 3 vext1 <6,1,7,2>, LHS - 1507459174U, // <1,7,3,0>: Cost 2 vext1 <5,1,7,3>, LHS - 2569257984U, // <1,7,3,1>: Cost 3 vext1 <3,1,7,3>, <1,3,5,7> - 2581202536U, // <1,7,3,2>: Cost 3 vext1 <5,1,7,3>, <2,2,2,2> - 2569259294U, // <1,7,3,3>: Cost 3 vext1 <3,1,7,3>, <3,1,7,3> - 1507462454U, // <1,7,3,4>: Cost 2 vext1 <5,1,7,3>, RHS - 1507462864U, // <1,7,3,5>: Cost 2 vext1 <5,1,7,3>, <5,1,7,3> - 2581205498U, // <1,7,3,6>: Cost 3 vext1 <5,1,7,3>, <6,2,7,3> - 2581206010U, // <1,7,3,7>: Cost 3 vext1 <5,1,7,3>, <7,0,1,2> - 1507465006U, // <1,7,3,u>: Cost 2 vext1 <5,1,7,3>, LHS - 2728826164U, // <1,7,4,0>: Cost 3 vext3 <7,4,0,1>, <7,4,0,1> - 3654951732U, // <1,7,4,1>: Cost 4 vext1 <5,1,7,4>, <1,1,1,1> - 3330987094U, // <1,7,4,2>: Cost 4 vrev <7,1,2,4> - 3331060831U, // <1,7,4,3>: Cost 4 vrev <7,1,3,4> - 3787674971U, // <1,7,4,4>: Cost 4 vext3 <4,u,5,1>, <7,4,4,4> - 2626669878U, // <1,7,4,5>: Cost 3 vext2 <1,5,1,7>, RHS - 3785979241U, // <1,7,4,6>: Cost 4 vext3 <4,6,0,1>, <7,4,6,0> - 3787085176U, // <1,7,4,7>: Cost 4 vext3 <4,7,6,1>, <7,4,7,6> - 2626670121U, // <1,7,4,u>: Cost 3 vext2 <1,5,1,7>, RHS - 2569273446U, // <1,7,5,0>: Cost 3 vext1 <3,1,7,5>, LHS - 2569274368U, // <1,7,5,1>: Cost 3 vext1 <3,1,7,5>, <1,3,5,7> - 3643016808U, // <1,7,5,2>: Cost 4 vext1 <3,1,7,5>, <2,2,2,2> - 2569275680U, // <1,7,5,3>: Cost 3 vext1 <3,1,7,5>, <3,1,7,5> - 2569276726U, // <1,7,5,4>: Cost 3 vext1 <3,1,7,5>, RHS - 4102034790U, // <1,7,5,5>: Cost 4 vtrnl <1,3,5,7>, <7,4,5,6> - 2651222067U, // <1,7,5,6>: Cost 3 vext2 <5,6,1,7>, <5,6,1,7> - 3899378998U, // <1,7,5,7>: Cost 4 vuzpr <1,1,5,7>, RHS - 2569279278U, // <1,7,5,u>: Cost 3 vext1 <3,1,7,5>, LHS - 2730153430U, // <1,7,6,0>: Cost 3 vext3 <7,6,0,1>, <7,6,0,1> - 2724845022U, // <1,7,6,1>: Cost 3 vext3 <6,7,0,1>, <7,6,1,0> - 3643025338U, // <1,7,6,2>: Cost 4 vext1 <3,1,7,6>, <2,6,3,7> - 3643025697U, // <1,7,6,3>: Cost 4 vext1 <3,1,7,6>, <3,1,7,6> - 3643026742U, // <1,7,6,4>: Cost 4 vext1 <3,1,7,6>, RHS - 3654971091U, // <1,7,6,5>: Cost 4 vext1 <5,1,7,6>, <5,1,7,6> - 3787675153U, // <1,7,6,6>: Cost 4 vext3 <4,u,5,1>, <7,6,6,6> - 2724845076U, // <1,7,6,7>: Cost 3 vext3 <6,7,0,1>, <7,6,7,0> - 2725508637U, // <1,7,6,u>: Cost 3 vext3 <6,u,0,1>, <7,6,u,0> - 2730817063U, // <1,7,7,0>: Cost 3 vext3 <7,7,0,1>, <7,7,0,1> - 3631088436U, // <1,7,7,1>: Cost 4 vext1 <1,1,7,7>, <1,1,1,1> - 3660949158U, // <1,7,7,2>: Cost 4 vext1 <6,1,7,7>, <2,3,0,1> - 3801904705U, // <1,7,7,3>: Cost 4 vext3 <7,3,0,1>, <7,7,3,0> - 3631090998U, // <1,7,7,4>: Cost 4 vext1 <1,1,7,7>, RHS - 2662503828U, // <1,7,7,5>: Cost 3 vext2 <7,5,1,7>, <7,5,1,7> - 3660951981U, // <1,7,7,6>: Cost 4 vext1 <6,1,7,7>, <6,1,7,7> - 2713933420U, // <1,7,7,7>: Cost 3 vext3 <4,u,5,1>, <7,7,7,7> - 2731406959U, // <1,7,7,u>: Cost 3 vext3 <7,7,u,1>, <7,7,u,1> - 1507500134U, // <1,7,u,0>: Cost 2 vext1 <5,1,7,u>, LHS - 2626672430U, // <1,7,u,1>: Cost 3 vext2 <1,5,1,7>, LHS - 2581243496U, // <1,7,u,2>: Cost 3 vext1 <5,1,7,u>, <2,2,2,2> - 2569300259U, // <1,7,u,3>: Cost 3 vext1 <3,1,7,u>, <3,1,7,u> - 1507503414U, // <1,7,u,4>: Cost 2 vext1 <5,1,7,u>, RHS - 1507503829U, // <1,7,u,5>: Cost 2 vext1 <5,1,7,u>, <5,1,7,u> - 2581246458U, // <1,7,u,6>: Cost 3 vext1 <5,1,7,u>, <6,2,7,3> - 2581246970U, // <1,7,u,7>: Cost 3 vext1 <5,1,7,u>, <7,0,1,2> - 1507505966U, // <1,7,u,u>: Cost 2 vext1 <5,1,7,u>, LHS - 1543643153U, // <1,u,0,0>: Cost 2 vext2 <0,0,1,u>, <0,0,1,u> - 1546297446U, // <1,u,0,1>: Cost 2 vext2 <0,4,1,u>, LHS - 2819448852U, // <1,u,0,2>: Cost 3 vuzpr LHS, <0,0,2,2> - 2619375876U, // <1,u,0,3>: Cost 3 vext2 <0,3,1,u>, <0,3,1,u> - 1546297685U, // <1,u,0,4>: Cost 2 vext2 <0,4,1,u>, <0,4,1,u> - 1658771190U, // <1,u,0,5>: Cost 2 vext3 , - 2736789248U, // <1,u,0,6>: Cost 3 vext3 , - 2659189376U, // <1,u,0,7>: Cost 3 vext2 <7,0,1,u>, <0,7,u,1> - 1546298013U, // <1,u,0,u>: Cost 2 vext2 <0,4,1,u>, LHS - 1483112550U, // <1,u,1,0>: Cost 2 vext1 <1,1,1,1>, LHS - 202162278U, // <1,u,1,1>: Cost 1 vdup1 LHS - 1616009006U, // <1,u,1,2>: Cost 2 vext3 <0,u,1,1>, LHS - 1745707110U, // <1,u,1,3>: Cost 2 vuzpr LHS, LHS - 1483115830U, // <1,u,1,4>: Cost 2 vext1 <1,1,1,1>, RHS - 2620040336U, // <1,u,1,5>: Cost 3 vext2 <0,4,1,u>, <1,5,3,7> - 3026622618U, // <1,u,1,6>: Cost 3 vtrnl <1,1,1,1>, RHS - 2958183752U, // <1,u,1,7>: Cost 3 vzipr <0,u,1,1>, RHS - 202162278U, // <1,u,1,u>: Cost 1 vdup1 LHS - 2819449750U, // <1,u,2,0>: Cost 3 vuzpr LHS, <1,2,3,0> - 2893207342U, // <1,u,2,1>: Cost 3 vzipl <1,2,3,0>, LHS - 2819448996U, // <1,u,2,2>: Cost 3 vuzpr LHS, <0,2,0,2> - 2819450482U, // <1,u,2,3>: Cost 3 vuzpr LHS, <2,2,3,3> - 2819449754U, // <1,u,2,4>: Cost 3 vuzpr LHS, <1,2,3,4> - 2893207706U, // <1,u,2,5>: Cost 3 vzipl <1,2,3,0>, RHS - 2819449036U, // <1,u,2,6>: Cost 3 vuzpr LHS, <0,2,4,6> - 2970799432U, // <1,u,2,7>: Cost 3 vzipr <3,0,1,2>, RHS - 2819449002U, // <1,u,2,u>: Cost 3 vuzpr LHS, <0,2,0,u> - 403931292U, // <1,u,3,0>: Cost 1 vext1 LHS, LHS - 1477673718U, // <1,u,3,1>: Cost 2 vext1 LHS, <1,0,3,2> - 115726126U, // <1,u,3,2>: Cost 1 vrev LHS - 2014102173U, // <1,u,3,3>: Cost 2 vtrnr LHS, LHS - 403934518U, // <1,u,3,4>: Cost 1 vext1 LHS, RHS - 1507536601U, // <1,u,3,5>: Cost 2 vext1 <5,1,u,3>, <5,1,u,3> - 1525453306U, // <1,u,3,6>: Cost 2 vext1 LHS, <6,2,7,3> - 2014105129U, // <1,u,3,7>: Cost 2 vtrnr LHS, RHS - 403937070U, // <1,u,3,u>: Cost 1 vext1 LHS, LHS - 2620042157U, // <1,u,4,0>: Cost 3 vext2 <0,4,1,u>, <4,0,u,1> - 2620042237U, // <1,u,4,1>: Cost 3 vext2 <0,4,1,u>, <4,1,u,0> - 2263217967U, // <1,u,4,2>: Cost 3 vrev - 2569341224U, // <1,u,4,3>: Cost 3 vext1 <3,1,u,4>, <3,1,u,4> - 2569342262U, // <1,u,4,4>: Cost 3 vext1 <3,1,u,4>, RHS - 1546300726U, // <1,u,4,5>: Cost 2 vext2 <0,4,1,u>, RHS - 2819449180U, // <1,u,4,6>: Cost 3 vuzpr LHS, <0,4,2,6> - 2724845649U, // <1,u,4,7>: Cost 3 vext3 <6,7,0,1>, - 1546300969U, // <1,u,4,u>: Cost 2 vext2 <0,4,1,u>, RHS - 2551431270U, // <1,u,5,0>: Cost 3 vext1 <0,1,u,5>, LHS - 2551432192U, // <1,u,5,1>: Cost 3 vext1 <0,1,u,5>, <1,3,5,7> - 3028293422U, // <1,u,5,2>: Cost 3 vtrnl <1,3,5,7>, LHS - 2955559068U, // <1,u,5,3>: Cost 3 vzipr <0,4,1,5>, LHS - 2551434550U, // <1,u,5,4>: Cost 3 vext1 <0,1,u,5>, RHS - 2895255706U, // <1,u,5,5>: Cost 3 vzipl <1,5,3,7>, RHS - 1616009370U, // <1,u,5,6>: Cost 2 vext3 <0,u,1,1>, RHS - 1745710390U, // <1,u,5,7>: Cost 2 vuzpr LHS, RHS - 1745710391U, // <1,u,5,u>: Cost 2 vuzpr LHS, RHS - 2653221159U, // <1,u,6,0>: Cost 3 vext2 <6,0,1,u>, <6,0,1,u> - 2725509303U, // <1,u,6,1>: Cost 3 vext3 <6,u,0,1>, - 2659193338U, // <1,u,6,2>: Cost 3 vext2 <7,0,1,u>, <6,2,7,3> - 2689751248U, // <1,u,6,3>: Cost 3 vext3 <0,u,1,1>, - 2867228774U, // <1,u,6,4>: Cost 3 vuzpr LHS, <5,6,7,4> - 3764820194U, // <1,u,6,5>: Cost 4 vext3 <1,1,1,1>, - 2657202957U, // <1,u,6,6>: Cost 3 vext2 <6,6,1,u>, <6,6,1,u> - 2819450810U, // <1,u,6,7>: Cost 3 vuzpr LHS, <2,6,3,7> - 2819450811U, // <1,u,6,u>: Cost 3 vuzpr LHS, <2,6,3,u> - 1585452032U, // <1,u,7,0>: Cost 2 vext2 <7,0,1,u>, <7,0,1,u> - 2557420340U, // <1,u,7,1>: Cost 3 vext1 <1,1,u,7>, <1,1,1,1> - 2569365158U, // <1,u,7,2>: Cost 3 vext1 <3,1,u,7>, <2,3,0,1> - 2569365803U, // <1,u,7,3>: Cost 3 vext1 <3,1,u,7>, <3,1,u,7> - 2557422902U, // <1,u,7,4>: Cost 3 vext1 <1,1,u,7>, RHS - 2662512021U, // <1,u,7,5>: Cost 3 vext2 <7,5,1,u>, <7,5,1,u> - 2724845884U, // <1,u,7,6>: Cost 3 vext3 <6,7,0,1>, - 2659194476U, // <1,u,7,7>: Cost 3 vext2 <7,0,1,u>, <7,7,7,7> - 1590761096U, // <1,u,7,u>: Cost 2 vext2 <7,u,1,u>, <7,u,1,u> - 403972257U, // <1,u,u,0>: Cost 1 vext1 LHS, LHS - 202162278U, // <1,u,u,1>: Cost 1 vdup1 LHS - 115767091U, // <1,u,u,2>: Cost 1 vrev LHS - 1745707677U, // <1,u,u,3>: Cost 2 vuzpr LHS, LHS - 403975478U, // <1,u,u,4>: Cost 1 vext1 LHS, RHS - 1546303642U, // <1,u,u,5>: Cost 2 vext2 <0,4,1,u>, RHS - 1616009613U, // <1,u,u,6>: Cost 2 vext3 <0,u,1,1>, RHS - 1745710633U, // <1,u,u,7>: Cost 2 vuzpr LHS, RHS - 403978030U, // <1,u,u,u>: Cost 1 vext1 LHS, LHS - 2551463936U, // <2,0,0,0>: Cost 3 vext1 <0,2,0,0>, <0,0,0,0> - 2685698058U, // <2,0,0,1>: Cost 3 vext3 <0,2,0,2>, <0,0,1,1> - 1610776596U, // <2,0,0,2>: Cost 2 vext3 <0,0,2,2>, <0,0,2,2> - 2619384069U, // <2,0,0,3>: Cost 3 vext2 <0,3,2,0>, <0,3,2,0> - 2551467318U, // <2,0,0,4>: Cost 3 vext1 <0,2,0,0>, RHS - 3899836596U, // <2,0,0,5>: Cost 4 vuzpr <1,2,3,0>, <3,0,4,5> - 2621374968U, // <2,0,0,6>: Cost 3 vext2 <0,6,2,0>, <0,6,2,0> - 4168271334U, // <2,0,0,7>: Cost 4 vtrnr <1,2,3,0>, <2,0,5,7> - 1611219018U, // <2,0,0,u>: Cost 2 vext3 <0,0,u,2>, <0,0,u,2> - 2551472138U, // <2,0,1,0>: Cost 3 vext1 <0,2,0,1>, <0,0,1,1> - 2690564186U, // <2,0,1,1>: Cost 3 vext3 <1,0,3,2>, <0,1,1,0> - 1611956326U, // <2,0,1,2>: Cost 2 vext3 <0,2,0,2>, LHS - 2826092646U, // <2,0,1,3>: Cost 3 vuzpr <1,2,3,0>, LHS - 2551475510U, // <2,0,1,4>: Cost 3 vext1 <0,2,0,1>, RHS - 3692463248U, // <2,0,1,5>: Cost 4 vext2 <0,2,2,0>, <1,5,3,7> - 2587308473U, // <2,0,1,6>: Cost 3 vext1 <6,2,0,1>, <6,2,0,1> - 3661050874U, // <2,0,1,7>: Cost 4 vext1 <6,2,0,1>, <7,0,1,2> - 1611956380U, // <2,0,1,u>: Cost 2 vext3 <0,2,0,2>, LHS - 1477738598U, // <2,0,2,0>: Cost 2 vext1 <0,2,0,2>, LHS - 2551481078U, // <2,0,2,1>: Cost 3 vext1 <0,2,0,2>, <1,0,3,2> - 2551481796U, // <2,0,2,2>: Cost 3 vext1 <0,2,0,2>, <2,0,2,0> - 2551482518U, // <2,0,2,3>: Cost 3 vext1 <0,2,0,2>, <3,0,1,2> - 1477741878U, // <2,0,2,4>: Cost 2 vext1 <0,2,0,2>, RHS - 2551484112U, // <2,0,2,5>: Cost 3 vext1 <0,2,0,2>, <5,1,7,3> - 2551484759U, // <2,0,2,6>: Cost 3 vext1 <0,2,0,2>, <6,0,7,2> - 2551485434U, // <2,0,2,7>: Cost 3 vext1 <0,2,0,2>, <7,0,1,2> - 1477744430U, // <2,0,2,u>: Cost 2 vext1 <0,2,0,2>, LHS - 2953625600U, // <2,0,3,0>: Cost 3 vzipr LHS, <0,0,0,0> - 2953627302U, // <2,0,3,1>: Cost 3 vzipr LHS, <2,3,0,1> - 2953625764U, // <2,0,3,2>: Cost 3 vzipr LHS, <0,2,0,2> - 4027369695U, // <2,0,3,3>: Cost 4 vzipr LHS, <3,1,0,3> - 3625233718U, // <2,0,3,4>: Cost 4 vext1 <0,2,0,3>, RHS - 3899836110U, // <2,0,3,5>: Cost 4 vuzpr <1,2,3,0>, <2,3,4,5> - 4032012618U, // <2,0,3,6>: Cost 4 vzipr LHS, <0,4,0,6> - 3899835392U, // <2,0,3,7>: Cost 4 vuzpr <1,2,3,0>, <1,3,5,7> - 2953625770U, // <2,0,3,u>: Cost 3 vzipr LHS, <0,2,0,u> - 2551496806U, // <2,0,4,0>: Cost 3 vext1 <0,2,0,4>, LHS - 2685698386U, // <2,0,4,1>: Cost 3 vext3 <0,2,0,2>, <0,4,1,5> - 2685698396U, // <2,0,4,2>: Cost 3 vext3 <0,2,0,2>, <0,4,2,6> - 3625240726U, // <2,0,4,3>: Cost 4 vext1 <0,2,0,4>, <3,0,1,2> - 2551500086U, // <2,0,4,4>: Cost 3 vext1 <0,2,0,4>, RHS - 2618723638U, // <2,0,4,5>: Cost 3 vext2 <0,2,2,0>, RHS - 2765409590U, // <2,0,4,6>: Cost 3 vuzpl <2,3,0,1>, RHS - 3799990664U, // <2,0,4,7>: Cost 4 vext3 <7,0,1,2>, <0,4,7,5> - 2685698450U, // <2,0,4,u>: Cost 3 vext3 <0,2,0,2>, <0,4,u,6> - 3625246822U, // <2,0,5,0>: Cost 4 vext1 <0,2,0,5>, LHS - 3289776304U, // <2,0,5,1>: Cost 4 vrev <0,2,1,5> - 2690564526U, // <2,0,5,2>: Cost 3 vext3 <1,0,3,2>, <0,5,2,7> - 3289923778U, // <2,0,5,3>: Cost 4 vrev <0,2,3,5> - 2216255691U, // <2,0,5,4>: Cost 3 vrev <0,2,4,5> - 3726307332U, // <2,0,5,5>: Cost 4 vext2 <5,u,2,0>, <5,5,5,5> - 3726307426U, // <2,0,5,6>: Cost 4 vext2 <5,u,2,0>, <5,6,7,0> - 2826095926U, // <2,0,5,7>: Cost 3 vuzpr <1,2,3,0>, RHS - 2216550639U, // <2,0,5,u>: Cost 3 vrev <0,2,u,5> - 4162420736U, // <2,0,6,0>: Cost 4 vtrnr <0,2,4,6>, <0,0,0,0> - 2901885030U, // <2,0,6,1>: Cost 3 vzipl <2,6,3,7>, LHS - 2685698559U, // <2,0,6,2>: Cost 3 vext3 <0,2,0,2>, <0,6,2,7> - 3643173171U, // <2,0,6,3>: Cost 4 vext1 <3,2,0,6>, <3,2,0,6> - 2216263884U, // <2,0,6,4>: Cost 3 vrev <0,2,4,6> - 3730289341U, // <2,0,6,5>: Cost 4 vext2 <6,5,2,0>, <6,5,2,0> - 3726308152U, // <2,0,6,6>: Cost 4 vext2 <5,u,2,0>, <6,6,6,6> - 3899836346U, // <2,0,6,7>: Cost 4 vuzpr <1,2,3,0>, <2,6,3,7> - 2216558832U, // <2,0,6,u>: Cost 3 vrev <0,2,u,6> - 2659202049U, // <2,0,7,0>: Cost 3 vext2 <7,0,2,0>, <7,0,2,0> - 3726308437U, // <2,0,7,1>: Cost 4 vext2 <5,u,2,0>, <7,1,2,3> - 2726249034U, // <2,0,7,2>: Cost 3 vext3 <7,0,1,2>, <0,7,2,1> - 3734934772U, // <2,0,7,3>: Cost 4 vext2 <7,3,2,0>, <7,3,2,0> - 3726308710U, // <2,0,7,4>: Cost 4 vext2 <5,u,2,0>, <7,4,5,6> - 3726308814U, // <2,0,7,5>: Cost 4 vext2 <5,u,2,0>, <7,5,u,2> - 3736925671U, // <2,0,7,6>: Cost 4 vext2 <7,6,2,0>, <7,6,2,0> - 3726308972U, // <2,0,7,7>: Cost 4 vext2 <5,u,2,0>, <7,7,7,7> - 2659202049U, // <2,0,7,u>: Cost 3 vext2 <7,0,2,0>, <7,0,2,0> - 1477787750U, // <2,0,u,0>: Cost 2 vext1 <0,2,0,u>, LHS - 2953668262U, // <2,0,u,1>: Cost 3 vzipr LHS, <2,3,0,1> - 1611956893U, // <2,0,u,2>: Cost 2 vext3 <0,2,0,2>, LHS - 2551531670U, // <2,0,u,3>: Cost 3 vext1 <0,2,0,u>, <3,0,1,2> - 1477791030U, // <2,0,u,4>: Cost 2 vext1 <0,2,0,u>, RHS - 2618726554U, // <2,0,u,5>: Cost 3 vext2 <0,2,2,0>, RHS - 2765412506U, // <2,0,u,6>: Cost 3 vuzpl <2,3,0,1>, RHS - 2826096169U, // <2,0,u,7>: Cost 3 vuzpr <1,2,3,0>, RHS - 1611956947U, // <2,0,u,u>: Cost 2 vext3 <0,2,0,2>, LHS - 2569453670U, // <2,1,0,0>: Cost 3 vext1 <3,2,1,0>, LHS - 2619392102U, // <2,1,0,1>: Cost 3 vext2 <0,3,2,1>, LHS - 3759440619U, // <2,1,0,2>: Cost 4 vext3 <0,2,0,2>, <1,0,2,0> - 1616823030U, // <2,1,0,3>: Cost 2 vext3 <1,0,3,2>, <1,0,3,2> - 2569456950U, // <2,1,0,4>: Cost 3 vext1 <3,2,1,0>, RHS - 2690712328U, // <2,1,0,5>: Cost 3 vext3 <1,0,5,2>, <1,0,5,2> - 3661115841U, // <2,1,0,6>: Cost 4 vext1 <6,2,1,0>, <6,2,1,0> - 2622046794U, // <2,1,0,7>: Cost 3 vext2 <0,7,2,1>, <0,7,2,1> - 1617191715U, // <2,1,0,u>: Cost 2 vext3 <1,0,u,2>, <1,0,u,2> - 2551545958U, // <2,1,1,0>: Cost 3 vext1 <0,2,1,1>, LHS - 2685698868U, // <2,1,1,1>: Cost 3 vext3 <0,2,0,2>, <1,1,1,1> - 2628682646U, // <2,1,1,2>: Cost 3 vext2 <1,u,2,1>, <1,2,3,0> - 2685698888U, // <2,1,1,3>: Cost 3 vext3 <0,2,0,2>, <1,1,3,3> - 2551549238U, // <2,1,1,4>: Cost 3 vext1 <0,2,1,1>, RHS - 3693134992U, // <2,1,1,5>: Cost 4 vext2 <0,3,2,1>, <1,5,3,7> - 3661124034U, // <2,1,1,6>: Cost 4 vext1 <6,2,1,1>, <6,2,1,1> - 3625292794U, // <2,1,1,7>: Cost 4 vext1 <0,2,1,1>, <7,0,1,2> - 2685698933U, // <2,1,1,u>: Cost 3 vext3 <0,2,0,2>, <1,1,u,3> - 2551554150U, // <2,1,2,0>: Cost 3 vext1 <0,2,1,2>, LHS - 3893649571U, // <2,1,2,1>: Cost 4 vuzpr <0,2,0,1>, <0,2,0,1> - 2551555688U, // <2,1,2,2>: Cost 3 vext1 <0,2,1,2>, <2,2,2,2> - 2685698966U, // <2,1,2,3>: Cost 3 vext3 <0,2,0,2>, <1,2,3,0> - 2551557430U, // <2,1,2,4>: Cost 3 vext1 <0,2,1,2>, RHS - 3763422123U, // <2,1,2,5>: Cost 4 vext3 <0,u,0,2>, <1,2,5,3> - 3693135802U, // <2,1,2,6>: Cost 4 vext2 <0,3,2,1>, <2,6,3,7> - 2726249402U, // <2,1,2,7>: Cost 3 vext3 <7,0,1,2>, <1,2,7,0> - 2685699011U, // <2,1,2,u>: Cost 3 vext3 <0,2,0,2>, <1,2,u,0> - 2551562342U, // <2,1,3,0>: Cost 3 vext1 <0,2,1,3>, LHS - 2953625610U, // <2,1,3,1>: Cost 3 vzipr LHS, <0,0,1,1> - 2953627798U, // <2,1,3,2>: Cost 3 vzipr LHS, <3,0,1,2> - 2953626584U, // <2,1,3,3>: Cost 3 vzipr LHS, <1,3,1,3> - 2551565622U, // <2,1,3,4>: Cost 3 vext1 <0,2,1,3>, RHS - 2953625938U, // <2,1,3,5>: Cost 3 vzipr LHS, <0,4,1,5> - 2587398596U, // <2,1,3,6>: Cost 3 vext1 <6,2,1,3>, <6,2,1,3> - 4032013519U, // <2,1,3,7>: Cost 4 vzipr LHS, <1,6,1,7> - 2953625617U, // <2,1,3,u>: Cost 3 vzipr LHS, <0,0,1,u> - 2690565154U, // <2,1,4,0>: Cost 3 vext3 <1,0,3,2>, <1,4,0,5> - 3625313270U, // <2,1,4,1>: Cost 4 vext1 <0,2,1,4>, <1,3,4,6> - 3771532340U, // <2,1,4,2>: Cost 4 vext3 <2,2,2,2>, <1,4,2,5> - 1148404634U, // <2,1,4,3>: Cost 2 vrev <1,2,3,4> - 3625315638U, // <2,1,4,4>: Cost 4 vext1 <0,2,1,4>, RHS - 2619395382U, // <2,1,4,5>: Cost 3 vext2 <0,3,2,1>, RHS - 3837242678U, // <2,1,4,6>: Cost 4 vuzpl <2,0,1,2>, RHS - 3799991394U, // <2,1,4,7>: Cost 4 vext3 <7,0,1,2>, <1,4,7,6> - 1148773319U, // <2,1,4,u>: Cost 2 vrev <1,2,u,4> - 2551578726U, // <2,1,5,0>: Cost 3 vext1 <0,2,1,5>, LHS - 2551579648U, // <2,1,5,1>: Cost 3 vext1 <0,2,1,5>, <1,3,5,7> - 3625321952U, // <2,1,5,2>: Cost 4 vext1 <0,2,1,5>, <2,0,5,1> - 2685699216U, // <2,1,5,3>: Cost 3 vext3 <0,2,0,2>, <1,5,3,7> - 2551582006U, // <2,1,5,4>: Cost 3 vext1 <0,2,1,5>, RHS - 3740913668U, // <2,1,5,5>: Cost 4 vext2 , <5,5,5,5> - 3661156806U, // <2,1,5,6>: Cost 4 vext1 <6,2,1,5>, <6,2,1,5> - 3893652790U, // <2,1,5,7>: Cost 4 vuzpr <0,2,0,1>, RHS - 2685699261U, // <2,1,5,u>: Cost 3 vext3 <0,2,0,2>, <1,5,u,7> - 2551586918U, // <2,1,6,0>: Cost 3 vext1 <0,2,1,6>, LHS - 3625329398U, // <2,1,6,1>: Cost 4 vext1 <0,2,1,6>, <1,0,3,2> - 2551588794U, // <2,1,6,2>: Cost 3 vext1 <0,2,1,6>, <2,6,3,7> - 3088679014U, // <2,1,6,3>: Cost 3 vtrnr <0,2,4,6>, LHS - 2551590198U, // <2,1,6,4>: Cost 3 vext1 <0,2,1,6>, RHS - 4029382994U, // <2,1,6,5>: Cost 4 vzipr <0,4,2,6>, <0,4,1,5> - 3625333560U, // <2,1,6,6>: Cost 4 vext1 <0,2,1,6>, <6,6,6,6> - 3731624800U, // <2,1,6,7>: Cost 4 vext2 <6,7,2,1>, <6,7,2,1> - 2551592750U, // <2,1,6,u>: Cost 3 vext1 <0,2,1,6>, LHS - 2622051322U, // <2,1,7,0>: Cost 3 vext2 <0,7,2,1>, <7,0,1,2> - 3733615699U, // <2,1,7,1>: Cost 4 vext2 <7,1,2,1>, <7,1,2,1> - 3795125538U, // <2,1,7,2>: Cost 4 vext3 <6,1,7,2>, <1,7,2,0> - 2222171037U, // <2,1,7,3>: Cost 3 vrev <1,2,3,7> - 3740915046U, // <2,1,7,4>: Cost 4 vext2 , <7,4,5,6> - 3296060335U, // <2,1,7,5>: Cost 4 vrev <1,2,5,7> - 3736933864U, // <2,1,7,6>: Cost 4 vext2 <7,6,2,1>, <7,6,2,1> - 3805300055U, // <2,1,7,7>: Cost 4 vext3 <7,u,1,2>, <1,7,7,u> - 2669827714U, // <2,1,7,u>: Cost 3 vext2 , <7,u,1,2> - 2551603302U, // <2,1,u,0>: Cost 3 vext1 <0,2,1,u>, LHS - 2953666570U, // <2,1,u,1>: Cost 3 vzipr LHS, <0,0,1,1> - 2953668758U, // <2,1,u,2>: Cost 3 vzipr LHS, <3,0,1,2> - 1148437406U, // <2,1,u,3>: Cost 2 vrev <1,2,3,u> - 2551606582U, // <2,1,u,4>: Cost 3 vext1 <0,2,1,u>, RHS - 2953666898U, // <2,1,u,5>: Cost 3 vzipr LHS, <0,4,1,5> - 2587398596U, // <2,1,u,6>: Cost 3 vext1 <6,2,1,3>, <6,2,1,3> - 2669828370U, // <2,1,u,7>: Cost 3 vext2 , - 1148806091U, // <2,1,u,u>: Cost 2 vrev <1,2,u,u> - 1543667732U, // <2,2,0,0>: Cost 2 vext2 <0,0,2,2>, <0,0,2,2> - 1548976230U, // <2,2,0,1>: Cost 2 vext2 <0,u,2,2>, LHS - 2685699524U, // <2,2,0,2>: Cost 3 vext3 <0,2,0,2>, <2,0,2,0> - 2685699535U, // <2,2,0,3>: Cost 3 vext3 <0,2,0,2>, <2,0,3,2> - 2551614774U, // <2,2,0,4>: Cost 3 vext1 <0,2,2,0>, RHS - 3704422830U, // <2,2,0,5>: Cost 4 vext2 <2,2,2,2>, <0,5,2,7> - 3893657642U, // <2,2,0,6>: Cost 4 vuzpr <0,2,0,2>, <0,0,4,6> - 3770574323U, // <2,2,0,7>: Cost 4 vext3 <2,0,7,2>, <2,0,7,2> - 1548976796U, // <2,2,0,u>: Cost 2 vext2 <0,u,2,2>, <0,u,2,2> - 2622718710U, // <2,2,1,0>: Cost 3 vext2 <0,u,2,2>, <1,0,3,2> - 2622718772U, // <2,2,1,1>: Cost 3 vext2 <0,u,2,2>, <1,1,1,1> - 2622718870U, // <2,2,1,2>: Cost 3 vext2 <0,u,2,2>, <1,2,3,0> - 2819915878U, // <2,2,1,3>: Cost 3 vuzpr <0,2,0,2>, LHS - 3625364790U, // <2,2,1,4>: Cost 4 vext1 <0,2,2,1>, RHS - 2622719120U, // <2,2,1,5>: Cost 3 vext2 <0,u,2,2>, <1,5,3,7> - 3760031292U, // <2,2,1,6>: Cost 4 vext3 <0,2,u,2>, <2,1,6,3> - 3667170468U, // <2,2,1,7>: Cost 4 vext1 <7,2,2,1>, <7,2,2,1> - 2819915883U, // <2,2,1,u>: Cost 3 vuzpr <0,2,0,2>, LHS - 1489829990U, // <2,2,2,0>: Cost 2 vext1 <2,2,2,2>, LHS - 2563572470U, // <2,2,2,1>: Cost 3 vext1 <2,2,2,2>, <1,0,3,2> - 269271142U, // <2,2,2,2>: Cost 1 vdup2 LHS - 2685699698U, // <2,2,2,3>: Cost 3 vext3 <0,2,0,2>, <2,2,3,3> - 1489833270U, // <2,2,2,4>: Cost 2 vext1 <2,2,2,2>, RHS - 2685699720U, // <2,2,2,5>: Cost 3 vext3 <0,2,0,2>, <2,2,5,7> - 2622719930U, // <2,2,2,6>: Cost 3 vext2 <0,u,2,2>, <2,6,3,7> - 2593436837U, // <2,2,2,7>: Cost 3 vext1 <7,2,2,2>, <7,2,2,2> - 269271142U, // <2,2,2,u>: Cost 1 vdup2 LHS - 2685699750U, // <2,2,3,0>: Cost 3 vext3 <0,2,0,2>, <2,3,0,1> - 2690565806U, // <2,2,3,1>: Cost 3 vext3 <1,0,3,2>, <2,3,1,0> - 2953627240U, // <2,2,3,2>: Cost 3 vzipr LHS, <2,2,2,2> - 1879883878U, // <2,2,3,3>: Cost 2 vzipr LHS, LHS - 2685699790U, // <2,2,3,4>: Cost 3 vext3 <0,2,0,2>, <2,3,4,5> - 3893659342U, // <2,2,3,5>: Cost 4 vuzpr <0,2,0,2>, <2,3,4,5> - 2958270812U, // <2,2,3,6>: Cost 3 vzipr LHS, <0,4,2,6> - 2593445030U, // <2,2,3,7>: Cost 3 vext1 <7,2,2,3>, <7,2,2,3> - 1879883883U, // <2,2,3,u>: Cost 2 vzipr LHS, LHS - 2551644262U, // <2,2,4,0>: Cost 3 vext1 <0,2,2,4>, LHS - 3625386742U, // <2,2,4,1>: Cost 4 vext1 <0,2,2,4>, <1,0,3,2> - 2551645902U, // <2,2,4,2>: Cost 3 vext1 <0,2,2,4>, <2,3,4,5> - 3759441686U, // <2,2,4,3>: Cost 4 vext3 <0,2,0,2>, <2,4,3,5> - 2551647542U, // <2,2,4,4>: Cost 3 vext1 <0,2,2,4>, RHS - 1548979510U, // <2,2,4,5>: Cost 2 vext2 <0,u,2,2>, RHS - 2764901686U, // <2,2,4,6>: Cost 3 vuzpl <2,2,2,2>, RHS - 3667195047U, // <2,2,4,7>: Cost 4 vext1 <7,2,2,4>, <7,2,2,4> - 1548979753U, // <2,2,4,u>: Cost 2 vext2 <0,u,2,2>, RHS - 3696463432U, // <2,2,5,0>: Cost 4 vext2 <0,u,2,2>, <5,0,1,2> - 2617413328U, // <2,2,5,1>: Cost 3 vext2 <0,0,2,2>, <5,1,7,3> - 2685699936U, // <2,2,5,2>: Cost 3 vext3 <0,2,0,2>, <2,5,2,7> - 4027383910U, // <2,2,5,3>: Cost 4 vzipr <0,1,2,5>, LHS - 2228201085U, // <2,2,5,4>: Cost 3 vrev <2,2,4,5> - 2617413636U, // <2,2,5,5>: Cost 3 vext2 <0,0,2,2>, <5,5,5,5> - 2617413730U, // <2,2,5,6>: Cost 3 vext2 <0,0,2,2>, <5,6,7,0> - 2819919158U, // <2,2,5,7>: Cost 3 vuzpr <0,2,0,2>, RHS - 2819919159U, // <2,2,5,u>: Cost 3 vuzpr <0,2,0,2>, RHS - 3625402554U, // <2,2,6,0>: Cost 4 vext1 <0,2,2,6>, <0,2,2,6> - 3760031652U, // <2,2,6,1>: Cost 4 vext3 <0,2,u,2>, <2,6,1,3> - 2617414138U, // <2,2,6,2>: Cost 3 vext2 <0,0,2,2>, <6,2,7,3> - 2685700026U, // <2,2,6,3>: Cost 3 vext3 <0,2,0,2>, <2,6,3,7> - 3625405750U, // <2,2,6,4>: Cost 4 vext1 <0,2,2,6>, RHS - 3760031692U, // <2,2,6,5>: Cost 4 vext3 <0,2,u,2>, <2,6,5,7> - 3088679116U, // <2,2,6,6>: Cost 3 vtrnr <0,2,4,6>, <0,2,4,6> - 2657891169U, // <2,2,6,7>: Cost 3 vext2 <6,7,2,2>, <6,7,2,2> - 2685700071U, // <2,2,6,u>: Cost 3 vext3 <0,2,0,2>, <2,6,u,7> - 2726250474U, // <2,2,7,0>: Cost 3 vext3 <7,0,1,2>, <2,7,0,1> - 3704427616U, // <2,2,7,1>: Cost 4 vext2 <2,2,2,2>, <7,1,3,5> - 2660545701U, // <2,2,7,2>: Cost 3 vext2 <7,2,2,2>, <7,2,2,2> - 4030718054U, // <2,2,7,3>: Cost 4 vzipr <0,6,2,7>, LHS - 2617415014U, // <2,2,7,4>: Cost 3 vext2 <0,0,2,2>, <7,4,5,6> - 3302033032U, // <2,2,7,5>: Cost 4 vrev <2,2,5,7> - 3661246929U, // <2,2,7,6>: Cost 4 vext1 <6,2,2,7>, <6,2,2,7> - 2617415276U, // <2,2,7,7>: Cost 3 vext2 <0,0,2,2>, <7,7,7,7> - 2731558962U, // <2,2,7,u>: Cost 3 vext3 <7,u,1,2>, <2,7,u,1> - 1489829990U, // <2,2,u,0>: Cost 2 vext1 <2,2,2,2>, LHS - 1548982062U, // <2,2,u,1>: Cost 2 vext2 <0,u,2,2>, LHS - 269271142U, // <2,2,u,2>: Cost 1 vdup2 LHS - 1879924838U, // <2,2,u,3>: Cost 2 vzipr LHS, LHS - 1489833270U, // <2,2,u,4>: Cost 2 vext1 <2,2,2,2>, RHS - 1548982426U, // <2,2,u,5>: Cost 2 vext2 <0,u,2,2>, RHS - 2953666908U, // <2,2,u,6>: Cost 3 vzipr LHS, <0,4,2,6> - 2819919401U, // <2,2,u,7>: Cost 3 vuzpr <0,2,0,2>, RHS - 269271142U, // <2,2,u,u>: Cost 1 vdup2 LHS - 1544339456U, // <2,3,0,0>: Cost 2 vext2 LHS, <0,0,0,0> - 470597734U, // <2,3,0,1>: Cost 1 vext2 LHS, LHS - 1548984484U, // <2,3,0,2>: Cost 2 vext2 LHS, <0,2,0,2> - 2619408648U, // <2,3,0,3>: Cost 3 vext2 <0,3,2,3>, <0,3,2,3> - 1548984658U, // <2,3,0,4>: Cost 2 vext2 LHS, <0,4,1,5> - 2665857454U, // <2,3,0,5>: Cost 3 vext2 LHS, <0,5,2,7> - 2622726655U, // <2,3,0,6>: Cost 3 vext2 LHS, <0,6,2,7> - 2593494188U, // <2,3,0,7>: Cost 3 vext1 <7,2,3,0>, <7,2,3,0> - 470598301U, // <2,3,0,u>: Cost 1 vext2 LHS, LHS - 1544340214U, // <2,3,1,0>: Cost 2 vext2 LHS, <1,0,3,2> - 1544340276U, // <2,3,1,1>: Cost 2 vext2 LHS, <1,1,1,1> - 1544340374U, // <2,3,1,2>: Cost 2 vext2 LHS, <1,2,3,0> - 1548985304U, // <2,3,1,3>: Cost 2 vext2 LHS, <1,3,1,3> - 2551696694U, // <2,3,1,4>: Cost 3 vext1 <0,2,3,1>, RHS - 1548985488U, // <2,3,1,5>: Cost 2 vext2 LHS, <1,5,3,7> - 2622727375U, // <2,3,1,6>: Cost 3 vext2 LHS, <1,6,1,7> - 2665858347U, // <2,3,1,7>: Cost 3 vext2 LHS, <1,7,3,0> - 1548985709U, // <2,3,1,u>: Cost 2 vext2 LHS, <1,u,1,3> - 2622727613U, // <2,3,2,0>: Cost 3 vext2 LHS, <2,0,1,2> - 2622727711U, // <2,3,2,1>: Cost 3 vext2 LHS, <2,1,3,1> - 1544341096U, // <2,3,2,2>: Cost 2 vext2 LHS, <2,2,2,2> - 1544341158U, // <2,3,2,3>: Cost 2 vext2 LHS, <2,3,0,1> - 2622727958U, // <2,3,2,4>: Cost 3 vext2 LHS, <2,4,3,5> - 2622728032U, // <2,3,2,5>: Cost 3 vext2 LHS, <2,5,2,7> - 1548986298U, // <2,3,2,6>: Cost 2 vext2 LHS, <2,6,3,7> - 2665859050U, // <2,3,2,7>: Cost 3 vext2 LHS, <2,7,0,1> - 1548986427U, // <2,3,2,u>: Cost 2 vext2 LHS, <2,u,0,1> - 1548986518U, // <2,3,3,0>: Cost 2 vext2 LHS, <3,0,1,2> - 2622728415U, // <2,3,3,1>: Cost 3 vext2 LHS, <3,1,0,3> - 1489913458U, // <2,3,3,2>: Cost 2 vext1 <2,2,3,3>, <2,2,3,3> - 1544341916U, // <2,3,3,3>: Cost 2 vext2 LHS, <3,3,3,3> - 1548986882U, // <2,3,3,4>: Cost 2 vext2 LHS, <3,4,5,6> - 2665859632U, // <2,3,3,5>: Cost 3 vext2 LHS, <3,5,1,7> - 2234304870U, // <2,3,3,6>: Cost 3 vrev <3,2,6,3> - 2958271632U, // <2,3,3,7>: Cost 3 vzipr LHS, <1,5,3,7> - 1548987166U, // <2,3,3,u>: Cost 2 vext2 LHS, <3,u,1,2> - 1483948134U, // <2,3,4,0>: Cost 2 vext1 <1,2,3,4>, LHS - 1483948954U, // <2,3,4,1>: Cost 2 vext1 <1,2,3,4>, <1,2,3,4> - 2622729276U, // <2,3,4,2>: Cost 3 vext2 LHS, <4,2,6,0> - 2557692054U, // <2,3,4,3>: Cost 3 vext1 <1,2,3,4>, <3,0,1,2> - 1483951414U, // <2,3,4,4>: Cost 2 vext1 <1,2,3,4>, RHS - 470601014U, // <2,3,4,5>: Cost 1 vext2 LHS, RHS - 1592118644U, // <2,3,4,6>: Cost 2 vext2 LHS, <4,6,4,6> - 2593526960U, // <2,3,4,7>: Cost 3 vext1 <7,2,3,4>, <7,2,3,4> - 470601257U, // <2,3,4,u>: Cost 1 vext2 LHS, RHS - 2551726182U, // <2,3,5,0>: Cost 3 vext1 <0,2,3,5>, LHS - 1592118992U, // <2,3,5,1>: Cost 2 vext2 LHS, <5,1,7,3> - 2665860862U, // <2,3,5,2>: Cost 3 vext2 LHS, <5,2,3,4> - 2551728642U, // <2,3,5,3>: Cost 3 vext1 <0,2,3,5>, <3,4,5,6> - 1592119238U, // <2,3,5,4>: Cost 2 vext2 LHS, <5,4,7,6> - 1592119300U, // <2,3,5,5>: Cost 2 vext2 LHS, <5,5,5,5> - 1592119394U, // <2,3,5,6>: Cost 2 vext2 LHS, <5,6,7,0> - 1592119464U, // <2,3,5,7>: Cost 2 vext2 LHS, <5,7,5,7> - 1592119545U, // <2,3,5,u>: Cost 2 vext2 LHS, <5,u,5,7> - 2622730529U, // <2,3,6,0>: Cost 3 vext2 LHS, <6,0,1,2> - 2557707164U, // <2,3,6,1>: Cost 3 vext1 <1,2,3,6>, <1,2,3,6> - 1592119802U, // <2,3,6,2>: Cost 2 vext2 LHS, <6,2,7,3> - 2665861682U, // <2,3,6,3>: Cost 3 vext2 LHS, <6,3,4,5> - 2622730893U, // <2,3,6,4>: Cost 3 vext2 LHS, <6,4,5,6> - 2665861810U, // <2,3,6,5>: Cost 3 vext2 LHS, <6,5,0,7> - 1592120120U, // <2,3,6,6>: Cost 2 vext2 LHS, <6,6,6,6> - 1592120142U, // <2,3,6,7>: Cost 2 vext2 LHS, <6,7,0,1> - 1592120223U, // <2,3,6,u>: Cost 2 vext2 LHS, <6,u,0,1> - 1592120314U, // <2,3,7,0>: Cost 2 vext2 LHS, <7,0,1,2> - 2659890261U, // <2,3,7,1>: Cost 3 vext2 <7,1,2,3>, <7,1,2,3> - 2660553894U, // <2,3,7,2>: Cost 3 vext2 <7,2,2,3>, <7,2,2,3> - 2665862371U, // <2,3,7,3>: Cost 3 vext2 LHS, <7,3,0,1> - 1592120678U, // <2,3,7,4>: Cost 2 vext2 LHS, <7,4,5,6> - 2665862534U, // <2,3,7,5>: Cost 3 vext2 LHS, <7,5,0,2> - 2665862614U, // <2,3,7,6>: Cost 3 vext2 LHS, <7,6,0,1> - 1592120940U, // <2,3,7,7>: Cost 2 vext2 LHS, <7,7,7,7> - 1592120962U, // <2,3,7,u>: Cost 2 vext2 LHS, <7,u,1,2> - 1548990163U, // <2,3,u,0>: Cost 2 vext2 LHS, - 470603566U, // <2,3,u,1>: Cost 1 vext2 LHS, LHS - 1548990341U, // <2,3,u,2>: Cost 2 vext2 LHS, - 1548990396U, // <2,3,u,3>: Cost 2 vext2 LHS, - 1548990527U, // <2,3,u,4>: Cost 2 vext2 LHS, - 470603930U, // <2,3,u,5>: Cost 1 vext2 LHS, RHS - 1548990672U, // <2,3,u,6>: Cost 2 vext2 LHS, - 1592121600U, // <2,3,u,7>: Cost 2 vext2 LHS, - 470604133U, // <2,3,u,u>: Cost 1 vext2 LHS, LHS - 2617425942U, // <2,4,0,0>: Cost 3 vext2 <0,0,2,4>, <0,0,2,4> - 2618753126U, // <2,4,0,1>: Cost 3 vext2 <0,2,2,4>, LHS - 2618753208U, // <2,4,0,2>: Cost 3 vext2 <0,2,2,4>, <0,2,2,4> - 2619416841U, // <2,4,0,3>: Cost 3 vext2 <0,3,2,4>, <0,3,2,4> - 2587593628U, // <2,4,0,4>: Cost 3 vext1 <6,2,4,0>, <4,0,6,2> - 2712832914U, // <2,4,0,5>: Cost 3 vext3 <4,6,u,2>, <4,0,5,1> - 1634962332U, // <2,4,0,6>: Cost 2 vext3 <4,0,6,2>, <4,0,6,2> - 3799993252U, // <2,4,0,7>: Cost 4 vext3 <7,0,1,2>, <4,0,7,1> - 1634962332U, // <2,4,0,u>: Cost 2 vext3 <4,0,6,2>, <4,0,6,2> - 2619417334U, // <2,4,1,0>: Cost 3 vext2 <0,3,2,4>, <1,0,3,2> - 3692495668U, // <2,4,1,1>: Cost 4 vext2 <0,2,2,4>, <1,1,1,1> - 2625389466U, // <2,4,1,2>: Cost 3 vext2 <1,3,2,4>, <1,2,3,4> - 2826125414U, // <2,4,1,3>: Cost 3 vuzpr <1,2,3,4>, LHS - 3699794995U, // <2,4,1,4>: Cost 4 vext2 <1,4,2,4>, <1,4,2,4> - 3692496016U, // <2,4,1,5>: Cost 4 vext2 <0,2,2,4>, <1,5,3,7> - 3763424238U, // <2,4,1,6>: Cost 4 vext3 <0,u,0,2>, <4,1,6,3> - 3667317942U, // <2,4,1,7>: Cost 4 vext1 <7,2,4,1>, <7,2,4,1> - 2826125419U, // <2,4,1,u>: Cost 3 vuzpr <1,2,3,4>, LHS - 2629371336U, // <2,4,2,0>: Cost 3 vext2 <2,0,2,4>, <2,0,2,4> - 3699131946U, // <2,4,2,1>: Cost 4 vext2 <1,3,2,4>, <2,1,4,3> - 2630698602U, // <2,4,2,2>: Cost 3 vext2 <2,2,2,4>, <2,2,2,4> - 2618754766U, // <2,4,2,3>: Cost 3 vext2 <0,2,2,4>, <2,3,4,5> - 2826126234U, // <2,4,2,4>: Cost 3 vuzpr <1,2,3,4>, <1,2,3,4> - 2899119414U, // <2,4,2,5>: Cost 3 vzipl <2,2,2,2>, RHS - 3033337142U, // <2,4,2,6>: Cost 3 vtrnl <2,2,2,2>, RHS - 3800214597U, // <2,4,2,7>: Cost 4 vext3 <7,0,4,2>, <4,2,7,0> - 2899119657U, // <2,4,2,u>: Cost 3 vzipl <2,2,2,2>, RHS - 2635344033U, // <2,4,3,0>: Cost 3 vext2 <3,0,2,4>, <3,0,2,4> - 4032012325U, // <2,4,3,1>: Cost 4 vzipr LHS, <0,0,4,1> - 3692497228U, // <2,4,3,2>: Cost 4 vext2 <0,2,2,4>, <3,2,3,4> - 3692497308U, // <2,4,3,3>: Cost 4 vext2 <0,2,2,4>, <3,3,3,3> - 3001404624U, // <2,4,3,4>: Cost 3 vzipr LHS, <4,4,4,4> - 2953627342U, // <2,4,3,5>: Cost 3 vzipr LHS, <2,3,4,5> - 2953625804U, // <2,4,3,6>: Cost 3 vzipr LHS, <0,2,4,6> - 3899868160U, // <2,4,3,7>: Cost 4 vuzpr <1,2,3,4>, <1,3,5,7> - 2953625806U, // <2,4,3,u>: Cost 3 vzipr LHS, <0,2,4,u> - 2710916266U, // <2,4,4,0>: Cost 3 vext3 <4,4,0,2>, <4,4,0,2> - 3899869648U, // <2,4,4,1>: Cost 4 vuzpr <1,2,3,4>, <3,4,0,1> - 3899869658U, // <2,4,4,2>: Cost 4 vuzpr <1,2,3,4>, <3,4,1,2> - 3899868930U, // <2,4,4,3>: Cost 4 vuzpr <1,2,3,4>, <2,4,1,3> - 2712833232U, // <2,4,4,4>: Cost 3 vext3 <4,6,u,2>, <4,4,4,4> - 2618756406U, // <2,4,4,5>: Cost 3 vext2 <0,2,2,4>, RHS - 2765737270U, // <2,4,4,6>: Cost 3 vuzpl <2,3,4,5>, RHS - 4168304426U, // <2,4,4,7>: Cost 4 vtrnr <1,2,3,4>, <2,4,5,7> - 2618756649U, // <2,4,4,u>: Cost 3 vext2 <0,2,2,4>, RHS - 2551800011U, // <2,4,5,0>: Cost 3 vext1 <0,2,4,5>, <0,2,4,5> - 2569716470U, // <2,4,5,1>: Cost 3 vext1 <3,2,4,5>, <1,0,3,2> - 2563745405U, // <2,4,5,2>: Cost 3 vext1 <2,2,4,5>, <2,2,4,5> - 2569718102U, // <2,4,5,3>: Cost 3 vext1 <3,2,4,5>, <3,2,4,5> - 2551803190U, // <2,4,5,4>: Cost 3 vext1 <0,2,4,5>, RHS - 3625545732U, // <2,4,5,5>: Cost 4 vext1 <0,2,4,5>, <5,5,5,5> - 1611959606U, // <2,4,5,6>: Cost 2 vext3 <0,2,0,2>, RHS - 2826128694U, // <2,4,5,7>: Cost 3 vuzpr <1,2,3,4>, RHS - 1611959624U, // <2,4,5,u>: Cost 2 vext3 <0,2,0,2>, RHS - 1478066278U, // <2,4,6,0>: Cost 2 vext1 <0,2,4,6>, LHS - 2551808758U, // <2,4,6,1>: Cost 3 vext1 <0,2,4,6>, <1,0,3,2> - 2551809516U, // <2,4,6,2>: Cost 3 vext1 <0,2,4,6>, <2,0,6,4> - 2551810198U, // <2,4,6,3>: Cost 3 vext1 <0,2,4,6>, <3,0,1,2> - 1478069558U, // <2,4,6,4>: Cost 2 vext1 <0,2,4,6>, RHS - 2901888310U, // <2,4,6,5>: Cost 3 vzipl <2,6,3,7>, RHS - 2551812920U, // <2,4,6,6>: Cost 3 vext1 <0,2,4,6>, <6,6,6,6> - 2726251914U, // <2,4,6,7>: Cost 3 vext3 <7,0,1,2>, <4,6,7,1> - 1478072110U, // <2,4,6,u>: Cost 2 vext1 <0,2,4,6>, LHS - 2659234821U, // <2,4,7,0>: Cost 3 vext2 <7,0,2,4>, <7,0,2,4> - 3786722726U, // <2,4,7,1>: Cost 4 vext3 <4,7,1,2>, <4,7,1,2> - 3734303911U, // <2,4,7,2>: Cost 4 vext2 <7,2,2,4>, <7,2,2,4> - 3734967544U, // <2,4,7,3>: Cost 4 vext2 <7,3,2,4>, <7,3,2,4> - 3727005030U, // <2,4,7,4>: Cost 4 vext2 <6,0,2,4>, <7,4,5,6> - 2726251976U, // <2,4,7,5>: Cost 3 vext3 <7,0,1,2>, <4,7,5,0> - 2726251986U, // <2,4,7,6>: Cost 3 vext3 <7,0,1,2>, <4,7,6,1> - 3727005292U, // <2,4,7,7>: Cost 4 vext2 <6,0,2,4>, <7,7,7,7> - 2659234821U, // <2,4,7,u>: Cost 3 vext2 <7,0,2,4>, <7,0,2,4> - 1478082662U, // <2,4,u,0>: Cost 2 vext1 <0,2,4,u>, LHS - 2618758958U, // <2,4,u,1>: Cost 3 vext2 <0,2,2,4>, LHS - 2551826024U, // <2,4,u,2>: Cost 3 vext1 <0,2,4,u>, <2,2,2,2> - 2551826582U, // <2,4,u,3>: Cost 3 vext1 <0,2,4,u>, <3,0,1,2> - 1478085942U, // <2,4,u,4>: Cost 2 vext1 <0,2,4,u>, RHS - 2953668302U, // <2,4,u,5>: Cost 3 vzipr LHS, <2,3,4,5> - 1611959849U, // <2,4,u,6>: Cost 2 vext3 <0,2,0,2>, RHS - 2826128937U, // <2,4,u,7>: Cost 3 vuzpr <1,2,3,4>, RHS - 1611959867U, // <2,4,u,u>: Cost 2 vext3 <0,2,0,2>, RHS - 3691839488U, // <2,5,0,0>: Cost 4 vext2 <0,1,2,5>, <0,0,0,0> - 2618097766U, // <2,5,0,1>: Cost 3 vext2 <0,1,2,5>, LHS - 2620088484U, // <2,5,0,2>: Cost 3 vext2 <0,4,2,5>, <0,2,0,2> - 2619425034U, // <2,5,0,3>: Cost 3 vext2 <0,3,2,5>, <0,3,2,5> - 2620088667U, // <2,5,0,4>: Cost 3 vext2 <0,4,2,5>, <0,4,2,5> - 2620752300U, // <2,5,0,5>: Cost 3 vext2 <0,5,2,5>, <0,5,2,5> - 3693830655U, // <2,5,0,6>: Cost 4 vext2 <0,4,2,5>, <0,6,2,7> - 3094531382U, // <2,5,0,7>: Cost 3 vtrnr <1,2,3,0>, RHS - 2618098333U, // <2,5,0,u>: Cost 3 vext2 <0,1,2,5>, LHS - 3691840246U, // <2,5,1,0>: Cost 4 vext2 <0,1,2,5>, <1,0,3,2> - 3691840308U, // <2,5,1,1>: Cost 4 vext2 <0,1,2,5>, <1,1,1,1> - 2626061206U, // <2,5,1,2>: Cost 3 vext2 <1,4,2,5>, <1,2,3,0> - 2618098688U, // <2,5,1,3>: Cost 3 vext2 <0,1,2,5>, <1,3,5,7> - 2626061364U, // <2,5,1,4>: Cost 3 vext2 <1,4,2,5>, <1,4,2,5> - 3691840656U, // <2,5,1,5>: Cost 4 vext2 <0,1,2,5>, <1,5,3,7> - 3789082310U, // <2,5,1,6>: Cost 4 vext3 <5,1,6,2>, <5,1,6,2> - 2712833744U, // <2,5,1,7>: Cost 3 vext3 <4,6,u,2>, <5,1,7,3> - 2628715896U, // <2,5,1,u>: Cost 3 vext2 <1,u,2,5>, <1,u,2,5> - 3693831613U, // <2,5,2,0>: Cost 4 vext2 <0,4,2,5>, <2,0,1,2> - 4026698642U, // <2,5,2,1>: Cost 4 vzipr <0,0,2,2>, <4,0,5,1> - 2632033896U, // <2,5,2,2>: Cost 3 vext2 <2,4,2,5>, <2,2,2,2> - 3691841190U, // <2,5,2,3>: Cost 4 vext2 <0,1,2,5>, <2,3,0,1> - 2632034061U, // <2,5,2,4>: Cost 3 vext2 <2,4,2,5>, <2,4,2,5> - 3691841352U, // <2,5,2,5>: Cost 4 vext2 <0,1,2,5>, <2,5,0,1> - 3691841466U, // <2,5,2,6>: Cost 4 vext2 <0,1,2,5>, <2,6,3,7> - 3088354614U, // <2,5,2,7>: Cost 3 vtrnr <0,2,0,2>, RHS - 3088354615U, // <2,5,2,u>: Cost 3 vtrnr <0,2,0,2>, RHS - 2557829222U, // <2,5,3,0>: Cost 3 vext1 <1,2,5,3>, LHS - 2557830059U, // <2,5,3,1>: Cost 3 vext1 <1,2,5,3>, <1,2,5,3> - 2575746766U, // <2,5,3,2>: Cost 3 vext1 <4,2,5,3>, <2,3,4,5> - 3691841948U, // <2,5,3,3>: Cost 4 vext2 <0,1,2,5>, <3,3,3,3> - 2619427330U, // <2,5,3,4>: Cost 3 vext2 <0,3,2,5>, <3,4,5,6> - 2581720847U, // <2,5,3,5>: Cost 3 vext1 <5,2,5,3>, <5,2,5,3> - 2953628162U, // <2,5,3,6>: Cost 3 vzipr LHS, <3,4,5,6> - 2953626624U, // <2,5,3,7>: Cost 3 vzipr LHS, <1,3,5,7> - 2953626625U, // <2,5,3,u>: Cost 3 vzipr LHS, <1,3,5,u> - 2569781350U, // <2,5,4,0>: Cost 3 vext1 <3,2,5,4>, LHS - 3631580076U, // <2,5,4,1>: Cost 4 vext1 <1,2,5,4>, <1,2,5,4> - 2569782990U, // <2,5,4,2>: Cost 3 vext1 <3,2,5,4>, <2,3,4,5> - 2569783646U, // <2,5,4,3>: Cost 3 vext1 <3,2,5,4>, <3,2,5,4> - 2569784630U, // <2,5,4,4>: Cost 3 vext1 <3,2,5,4>, RHS - 2618101046U, // <2,5,4,5>: Cost 3 vext2 <0,1,2,5>, RHS - 3893905922U, // <2,5,4,6>: Cost 4 vuzpr <0,2,3,5>, <3,4,5,6> - 3094564150U, // <2,5,4,7>: Cost 3 vtrnr <1,2,3,4>, RHS - 2618101289U, // <2,5,4,u>: Cost 3 vext2 <0,1,2,5>, RHS - 2551873638U, // <2,5,5,0>: Cost 3 vext1 <0,2,5,5>, LHS - 3637560320U, // <2,5,5,1>: Cost 4 vext1 <2,2,5,5>, <1,3,5,7> - 3637560966U, // <2,5,5,2>: Cost 4 vext1 <2,2,5,5>, <2,2,5,5> - 3723030343U, // <2,5,5,3>: Cost 4 vext2 <5,3,2,5>, <5,3,2,5> - 2551876918U, // <2,5,5,4>: Cost 3 vext1 <0,2,5,5>, RHS - 2712834052U, // <2,5,5,5>: Cost 3 vext3 <4,6,u,2>, <5,5,5,5> - 4028713474U, // <2,5,5,6>: Cost 4 vzipr <0,3,2,5>, <3,4,5,6> - 2712834072U, // <2,5,5,7>: Cost 3 vext3 <4,6,u,2>, <5,5,7,7> - 2712834081U, // <2,5,5,u>: Cost 3 vext3 <4,6,u,2>, <5,5,u,7> - 2575769702U, // <2,5,6,0>: Cost 3 vext1 <4,2,5,6>, LHS - 3631596462U, // <2,5,6,1>: Cost 4 vext1 <1,2,5,6>, <1,2,5,6> - 2655924730U, // <2,5,6,2>: Cost 3 vext2 <6,4,2,5>, <6,2,7,3> - 3643541856U, // <2,5,6,3>: Cost 4 vext1 <3,2,5,6>, <3,2,5,6> - 2655924849U, // <2,5,6,4>: Cost 3 vext2 <6,4,2,5>, <6,4,2,5> - 3787755607U, // <2,5,6,5>: Cost 4 vext3 <4,u,6,2>, <5,6,5,7> - 4029385218U, // <2,5,6,6>: Cost 4 vzipr <0,4,2,6>, <3,4,5,6> - 3088682294U, // <2,5,6,7>: Cost 3 vtrnr <0,2,4,6>, RHS - 3088682295U, // <2,5,6,u>: Cost 3 vtrnr <0,2,4,6>, RHS - 2563833958U, // <2,5,7,0>: Cost 3 vext1 <2,2,5,7>, LHS - 2551890678U, // <2,5,7,1>: Cost 3 vext1 <0,2,5,7>, <1,0,3,2> - 2563835528U, // <2,5,7,2>: Cost 3 vext1 <2,2,5,7>, <2,2,5,7> - 3637577878U, // <2,5,7,3>: Cost 4 vext1 <2,2,5,7>, <3,0,1,2> - 2563837238U, // <2,5,7,4>: Cost 3 vext1 <2,2,5,7>, RHS - 2712834216U, // <2,5,7,5>: Cost 3 vext3 <4,6,u,2>, <5,7,5,7> - 2712834220U, // <2,5,7,6>: Cost 3 vext3 <4,6,u,2>, <5,7,6,2> - 4174449974U, // <2,5,7,7>: Cost 4 vtrnr <2,2,5,7>, RHS - 2563839790U, // <2,5,7,u>: Cost 3 vext1 <2,2,5,7>, LHS - 2563842150U, // <2,5,u,0>: Cost 3 vext1 <2,2,5,u>, LHS - 2618103598U, // <2,5,u,1>: Cost 3 vext2 <0,1,2,5>, LHS - 2563843721U, // <2,5,u,2>: Cost 3 vext1 <2,2,5,u>, <2,2,5,u> - 2569816418U, // <2,5,u,3>: Cost 3 vext1 <3,2,5,u>, <3,2,5,u> - 2622748735U, // <2,5,u,4>: Cost 3 vext2 <0,u,2,5>, - 2618103962U, // <2,5,u,5>: Cost 3 vext2 <0,1,2,5>, RHS - 2953669122U, // <2,5,u,6>: Cost 3 vzipr LHS, <3,4,5,6> - 2953667584U, // <2,5,u,7>: Cost 3 vzipr LHS, <1,3,5,7> - 2618104165U, // <2,5,u,u>: Cost 3 vext2 <0,1,2,5>, LHS - 2620096512U, // <2,6,0,0>: Cost 3 vext2 <0,4,2,6>, <0,0,0,0> - 1546354790U, // <2,6,0,1>: Cost 2 vext2 <0,4,2,6>, LHS - 2620096676U, // <2,6,0,2>: Cost 3 vext2 <0,4,2,6>, <0,2,0,2> - 3693838588U, // <2,6,0,3>: Cost 4 vext2 <0,4,2,6>, <0,3,1,0> - 1546355036U, // <2,6,0,4>: Cost 2 vext2 <0,4,2,6>, <0,4,2,6> - 3694502317U, // <2,6,0,5>: Cost 4 vext2 <0,5,2,6>, <0,5,2,6> - 2551911246U, // <2,6,0,6>: Cost 3 vext1 <0,2,6,0>, <6,7,0,1> - 2720723287U, // <2,6,0,7>: Cost 3 vext3 <6,0,7,2>, <6,0,7,2> - 1546355357U, // <2,6,0,u>: Cost 2 vext2 <0,4,2,6>, LHS - 2620097270U, // <2,6,1,0>: Cost 3 vext2 <0,4,2,6>, <1,0,3,2> - 2620097332U, // <2,6,1,1>: Cost 3 vext2 <0,4,2,6>, <1,1,1,1> - 2620097430U, // <2,6,1,2>: Cost 3 vext2 <0,4,2,6>, <1,2,3,0> - 2820243558U, // <2,6,1,3>: Cost 3 vuzpr <0,2,4,6>, LHS - 2620097598U, // <2,6,1,4>: Cost 3 vext2 <0,4,2,6>, <1,4,3,6> - 2620097680U, // <2,6,1,5>: Cost 3 vext2 <0,4,2,6>, <1,5,3,7> - 3693839585U, // <2,6,1,6>: Cost 4 vext2 <0,4,2,6>, <1,6,3,7> - 2721386920U, // <2,6,1,7>: Cost 3 vext3 <6,1,7,2>, <6,1,7,2> - 2820243563U, // <2,6,1,u>: Cost 3 vuzpr <0,2,4,6>, LHS - 2714014137U, // <2,6,2,0>: Cost 3 vext3 <4,u,6,2>, <6,2,0,1> - 2712834500U, // <2,6,2,1>: Cost 3 vext3 <4,6,u,2>, <6,2,1,3> - 2620098152U, // <2,6,2,2>: Cost 3 vext2 <0,4,2,6>, <2,2,2,2> - 2620098214U, // <2,6,2,3>: Cost 3 vext2 <0,4,2,6>, <2,3,0,1> - 2632042254U, // <2,6,2,4>: Cost 3 vext2 <2,4,2,6>, <2,4,2,6> - 2712834540U, // <2,6,2,5>: Cost 3 vext3 <4,6,u,2>, <6,2,5,7> - 2820243660U, // <2,6,2,6>: Cost 3 vuzpr <0,2,4,6>, <0,2,4,6> - 2958265654U, // <2,6,2,7>: Cost 3 vzipr <0,u,2,2>, RHS - 2620098619U, // <2,6,2,u>: Cost 3 vext2 <0,4,2,6>, <2,u,0,1> - 2620098710U, // <2,6,3,0>: Cost 3 vext2 <0,4,2,6>, <3,0,1,2> - 3893986982U, // <2,6,3,1>: Cost 4 vuzpr <0,2,4,6>, <2,3,0,1> - 2569848762U, // <2,6,3,2>: Cost 3 vext1 <3,2,6,3>, <2,6,3,7> - 2620098972U, // <2,6,3,3>: Cost 3 vext2 <0,4,2,6>, <3,3,3,3> - 2620099074U, // <2,6,3,4>: Cost 3 vext2 <0,4,2,6>, <3,4,5,6> - 3893987022U, // <2,6,3,5>: Cost 4 vuzpr <0,2,4,6>, <2,3,4,5> - 3001404644U, // <2,6,3,6>: Cost 3 vzipr LHS, <4,4,6,6> - 1879887158U, // <2,6,3,7>: Cost 2 vzipr LHS, RHS - 1879887159U, // <2,6,3,u>: Cost 2 vzipr LHS, RHS - 2620099484U, // <2,6,4,0>: Cost 3 vext2 <0,4,2,6>, <4,0,6,2> - 2620099566U, // <2,6,4,1>: Cost 3 vext2 <0,4,2,6>, <4,1,6,3> - 2620099644U, // <2,6,4,2>: Cost 3 vext2 <0,4,2,6>, <4,2,6,0> - 3643599207U, // <2,6,4,3>: Cost 4 vext1 <3,2,6,4>, <3,2,6,4> - 2575830080U, // <2,6,4,4>: Cost 3 vext1 <4,2,6,4>, <4,2,6,4> - 1546358070U, // <2,6,4,5>: Cost 2 vext2 <0,4,2,6>, RHS - 2667875700U, // <2,6,4,6>: Cost 3 vext2 , <4,6,4,6> - 4028042550U, // <2,6,4,7>: Cost 4 vzipr <0,2,2,4>, RHS - 1546358313U, // <2,6,4,u>: Cost 2 vext2 <0,4,2,6>, RHS - 3693841992U, // <2,6,5,0>: Cost 4 vext2 <0,4,2,6>, <5,0,1,2> - 2667876048U, // <2,6,5,1>: Cost 3 vext2 , <5,1,7,3> - 2712834756U, // <2,6,5,2>: Cost 3 vext3 <4,6,u,2>, <6,5,2,7> - 3643607400U, // <2,6,5,3>: Cost 4 vext1 <3,2,6,5>, <3,2,6,5> - 2252091873U, // <2,6,5,4>: Cost 3 vrev <6,2,4,5> - 2667876356U, // <2,6,5,5>: Cost 3 vext2 , <5,5,5,5> - 2667876450U, // <2,6,5,6>: Cost 3 vext2 , <5,6,7,0> - 2820246838U, // <2,6,5,7>: Cost 3 vuzpr <0,2,4,6>, RHS - 2820246839U, // <2,6,5,u>: Cost 3 vuzpr <0,2,4,6>, RHS - 2563899494U, // <2,6,6,0>: Cost 3 vext1 <2,2,6,6>, LHS - 3893988683U, // <2,6,6,1>: Cost 4 vuzpr <0,2,4,6>, <4,6,0,1> - 2563901072U, // <2,6,6,2>: Cost 3 vext1 <2,2,6,6>, <2,2,6,6> - 3893987236U, // <2,6,6,3>: Cost 4 vuzpr <0,2,4,6>, <2,6,1,3> - 2563902774U, // <2,6,6,4>: Cost 3 vext1 <2,2,6,6>, RHS - 3893988723U, // <2,6,6,5>: Cost 4 vuzpr <0,2,4,6>, <4,6,4,5> - 2712834872U, // <2,6,6,6>: Cost 3 vext3 <4,6,u,2>, <6,6,6,6> - 2955644214U, // <2,6,6,7>: Cost 3 vzipr <0,4,2,6>, RHS - 2955644215U, // <2,6,6,u>: Cost 3 vzipr <0,4,2,6>, RHS - 2712834894U, // <2,6,7,0>: Cost 3 vext3 <4,6,u,2>, <6,7,0,1> - 2724926296U, // <2,6,7,1>: Cost 3 vext3 <6,7,1,2>, <6,7,1,2> - 2725000033U, // <2,6,7,2>: Cost 3 vext3 <6,7,2,2>, <6,7,2,2> - 2702365544U, // <2,6,7,3>: Cost 3 vext3 <3,0,1,2>, <6,7,3,0> - 2712834934U, // <2,6,7,4>: Cost 3 vext3 <4,6,u,2>, <6,7,4,5> - 3776107393U, // <2,6,7,5>: Cost 4 vext3 <3,0,1,2>, <6,7,5,7> - 2725294981U, // <2,6,7,6>: Cost 3 vext3 <6,7,6,2>, <6,7,6,2> - 2726253452U, // <2,6,7,7>: Cost 3 vext3 <7,0,1,2>, <6,7,7,0> - 2712834966U, // <2,6,7,u>: Cost 3 vext3 <4,6,u,2>, <6,7,u,1> - 2620102355U, // <2,6,u,0>: Cost 3 vext2 <0,4,2,6>, - 1546360622U, // <2,6,u,1>: Cost 2 vext2 <0,4,2,6>, LHS - 2620102536U, // <2,6,u,2>: Cost 3 vext2 <0,4,2,6>, - 2820244125U, // <2,6,u,3>: Cost 3 vuzpr <0,2,4,6>, LHS - 1594136612U, // <2,6,u,4>: Cost 2 vext2 , - 1546360986U, // <2,6,u,5>: Cost 2 vext2 <0,4,2,6>, RHS - 2620102864U, // <2,6,u,6>: Cost 3 vext2 <0,4,2,6>, - 1879928118U, // <2,6,u,7>: Cost 2 vzipr LHS, RHS - 1879928119U, // <2,6,u,u>: Cost 2 vzipr LHS, RHS - 2726179825U, // <2,7,0,0>: Cost 3 vext3 <7,0,0,2>, <7,0,0,2> - 1652511738U, // <2,7,0,1>: Cost 2 vext3 <7,0,1,2>, <7,0,1,2> - 2621431972U, // <2,7,0,2>: Cost 3 vext2 <0,6,2,7>, <0,2,0,2> - 2257949868U, // <2,7,0,3>: Cost 3 vrev <7,2,3,0> - 2726474773U, // <2,7,0,4>: Cost 3 vext3 <7,0,4,2>, <7,0,4,2> - 2620768686U, // <2,7,0,5>: Cost 3 vext2 <0,5,2,7>, <0,5,2,7> - 2621432319U, // <2,7,0,6>: Cost 3 vext2 <0,6,2,7>, <0,6,2,7> - 2599760953U, // <2,7,0,7>: Cost 3 vext1 , <7,0,u,2> - 1653027897U, // <2,7,0,u>: Cost 2 vext3 <7,0,u,2>, <7,0,u,2> - 2639348470U, // <2,7,1,0>: Cost 3 vext2 <3,6,2,7>, <1,0,3,2> - 3695174452U, // <2,7,1,1>: Cost 4 vext2 <0,6,2,7>, <1,1,1,1> - 3695174550U, // <2,7,1,2>: Cost 4 vext2 <0,6,2,7>, <1,2,3,0> - 3694511104U, // <2,7,1,3>: Cost 4 vext2 <0,5,2,7>, <1,3,5,7> - 3713090594U, // <2,7,1,4>: Cost 4 vext2 <3,6,2,7>, <1,4,0,5> - 3693184144U, // <2,7,1,5>: Cost 4 vext2 <0,3,2,7>, <1,5,3,7> - 2627405016U, // <2,7,1,6>: Cost 3 vext2 <1,6,2,7>, <1,6,2,7> - 3799995519U, // <2,7,1,7>: Cost 4 vext3 <7,0,1,2>, <7,1,7,0> - 2639348470U, // <2,7,1,u>: Cost 3 vext2 <3,6,2,7>, <1,0,3,2> - 3695175101U, // <2,7,2,0>: Cost 4 vext2 <0,6,2,7>, <2,0,1,2> - 3643655168U, // <2,7,2,1>: Cost 4 vext1 <3,2,7,2>, <1,3,5,7> - 2257892517U, // <2,7,2,2>: Cost 3 vrev <7,2,2,2> - 3695175334U, // <2,7,2,3>: Cost 4 vext2 <0,6,2,7>, <2,3,0,1> - 3695175465U, // <2,7,2,4>: Cost 4 vext2 <0,6,2,7>, <2,4,5,6> - 2632714080U, // <2,7,2,5>: Cost 3 vext2 <2,5,2,7>, <2,5,2,7> - 2633377713U, // <2,7,2,6>: Cost 3 vext2 <2,6,2,7>, <2,6,2,7> - 3695175658U, // <2,7,2,7>: Cost 4 vext2 <0,6,2,7>, <2,7,0,1> - 2634704979U, // <2,7,2,u>: Cost 3 vext2 <2,u,2,7>, <2,u,2,7> - 1514094694U, // <2,7,3,0>: Cost 2 vext1 <6,2,7,3>, LHS - 2569921680U, // <2,7,3,1>: Cost 3 vext1 <3,2,7,3>, <1,5,3,7> - 2587838056U, // <2,7,3,2>: Cost 3 vext1 <6,2,7,3>, <2,2,2,2> - 2569922927U, // <2,7,3,3>: Cost 3 vext1 <3,2,7,3>, <3,2,7,3> - 1514097974U, // <2,7,3,4>: Cost 2 vext1 <6,2,7,3>, RHS - 2581868321U, // <2,7,3,5>: Cost 3 vext1 <5,2,7,3>, <5,2,7,3> - 1514099194U, // <2,7,3,6>: Cost 2 vext1 <6,2,7,3>, <6,2,7,3> - 2587841530U, // <2,7,3,7>: Cost 3 vext1 <6,2,7,3>, <7,0,1,2> - 1514100526U, // <2,7,3,u>: Cost 2 vext1 <6,2,7,3>, LHS - 2708706617U, // <2,7,4,0>: Cost 3 vext3 <4,0,6,2>, <7,4,0,6> - 3649643418U, // <2,7,4,1>: Cost 4 vext1 <4,2,7,4>, <1,2,3,4> - 3649644330U, // <2,7,4,2>: Cost 4 vext1 <4,2,7,4>, <2,4,5,7> - 2257982640U, // <2,7,4,3>: Cost 3 vrev <7,2,3,4> - 3649645641U, // <2,7,4,4>: Cost 4 vext1 <4,2,7,4>, <4,2,7,4> - 2621435190U, // <2,7,4,5>: Cost 3 vext2 <0,6,2,7>, RHS - 2712835441U, // <2,7,4,6>: Cost 3 vext3 <4,6,u,2>, <7,4,6,u> - 3799995762U, // <2,7,4,7>: Cost 4 vext3 <7,0,1,2>, <7,4,7,0> - 2621435433U, // <2,7,4,u>: Cost 3 vext2 <0,6,2,7>, RHS - 2729497990U, // <2,7,5,0>: Cost 3 vext3 <7,5,0,2>, <7,5,0,2> - 3643679744U, // <2,7,5,1>: Cost 4 vext1 <3,2,7,5>, <1,3,5,7> - 3637708424U, // <2,7,5,2>: Cost 4 vext1 <2,2,7,5>, <2,2,5,7> - 3643681137U, // <2,7,5,3>: Cost 4 vext1 <3,2,7,5>, <3,2,7,5> - 2599800118U, // <2,7,5,4>: Cost 3 vext1 , RHS - 3786577334U, // <2,7,5,5>: Cost 4 vext3 <4,6,u,2>, <7,5,5,5> - 3786577345U, // <2,7,5,6>: Cost 4 vext3 <4,6,u,2>, <7,5,6,7> - 2599802214U, // <2,7,5,7>: Cost 3 vext1 , <7,4,5,6> - 2599802670U, // <2,7,5,u>: Cost 3 vext1 , LHS - 2581889126U, // <2,7,6,0>: Cost 3 vext1 <5,2,7,6>, LHS - 3643687936U, // <2,7,6,1>: Cost 4 vext1 <3,2,7,6>, <1,3,5,7> - 2663240186U, // <2,7,6,2>: Cost 3 vext2 <7,6,2,7>, <6,2,7,3> - 3643689330U, // <2,7,6,3>: Cost 4 vext1 <3,2,7,6>, <3,2,7,6> - 2581892406U, // <2,7,6,4>: Cost 3 vext1 <5,2,7,6>, RHS - 2581892900U, // <2,7,6,5>: Cost 3 vext1 <5,2,7,6>, <5,2,7,6> - 2587865597U, // <2,7,6,6>: Cost 3 vext1 <6,2,7,6>, <6,2,7,6> - 3786577428U, // <2,7,6,7>: Cost 4 vext3 <4,6,u,2>, <7,6,7,0> - 2581894958U, // <2,7,6,u>: Cost 3 vext1 <5,2,7,6>, LHS - 2726254119U, // <2,7,7,0>: Cost 3 vext3 <7,0,1,2>, <7,7,0,1> - 3804640817U, // <2,7,7,1>: Cost 4 vext3 <7,7,1,2>, <7,7,1,2> - 3637724826U, // <2,7,7,2>: Cost 4 vext1 <2,2,7,7>, <2,2,7,7> - 3734992123U, // <2,7,7,3>: Cost 4 vext2 <7,3,2,7>, <7,3,2,7> - 2552040758U, // <2,7,7,4>: Cost 3 vext1 <0,2,7,7>, RHS - 3799995992U, // <2,7,7,5>: Cost 4 vext3 <7,0,1,2>, <7,7,5,5> - 2663241198U, // <2,7,7,6>: Cost 3 vext2 <7,6,2,7>, <7,6,2,7> - 2712835692U, // <2,7,7,7>: Cost 3 vext3 <4,6,u,2>, <7,7,7,7> - 2731562607U, // <2,7,7,u>: Cost 3 vext3 <7,u,1,2>, <7,7,u,1> - 1514135654U, // <2,7,u,0>: Cost 2 vext1 <6,2,7,u>, LHS - 1657820802U, // <2,7,u,1>: Cost 2 vext3 <7,u,1,2>, <7,u,1,2> - 2587879016U, // <2,7,u,2>: Cost 3 vext1 <6,2,7,u>, <2,2,2,2> - 2569963892U, // <2,7,u,3>: Cost 3 vext1 <3,2,7,u>, <3,2,7,u> - 1514138934U, // <2,7,u,4>: Cost 2 vext1 <6,2,7,u>, RHS - 2621438106U, // <2,7,u,5>: Cost 3 vext2 <0,6,2,7>, RHS - 1514140159U, // <2,7,u,6>: Cost 2 vext1 <6,2,7,u>, <6,2,7,u> - 2587882490U, // <2,7,u,7>: Cost 3 vext1 <6,2,7,u>, <7,0,1,2> - 1514141486U, // <2,7,u,u>: Cost 2 vext1 <6,2,7,u>, LHS - 1544380416U, // <2,u,0,0>: Cost 2 vext2 LHS, <0,0,0,0> - 470638699U, // <2,u,0,1>: Cost 1 vext2 LHS, LHS - 1544380580U, // <2,u,0,2>: Cost 2 vext2 LHS, <0,2,0,2> - 1658631909U, // <2,u,0,3>: Cost 2 vext3 , - 1544380754U, // <2,u,0,4>: Cost 2 vext2 LHS, <0,4,1,5> - 2665898414U, // <2,u,0,5>: Cost 3 vext2 LHS, <0,5,2,7> - 1658853120U, // <2,u,0,6>: Cost 2 vext3 , - 3094531625U, // <2,u,0,7>: Cost 3 vtrnr <1,2,3,0>, RHS - 470639261U, // <2,u,0,u>: Cost 1 vext2 LHS, LHS - 1544381174U, // <2,u,1,0>: Cost 2 vext2 LHS, <1,0,3,2> - 1544381236U, // <2,u,1,1>: Cost 2 vext2 LHS, <1,1,1,1> - 1544381334U, // <2,u,1,2>: Cost 2 vext2 LHS, <1,2,3,0> - 1544381400U, // <2,u,1,3>: Cost 2 vext2 LHS, <1,3,1,3> - 2618123325U, // <2,u,1,4>: Cost 3 vext2 LHS, <1,4,3,5> - 1544381584U, // <2,u,1,5>: Cost 2 vext2 LHS, <1,5,3,7> - 2618123489U, // <2,u,1,6>: Cost 3 vext2 LHS, <1,6,3,7> - 2726254427U, // <2,u,1,7>: Cost 3 vext3 <7,0,1,2>, - 1544381823U, // <2,u,1,u>: Cost 2 vext2 LHS, <1,u,3,3> - 1478328422U, // <2,u,2,0>: Cost 2 vext1 <0,2,u,2>, LHS - 2618123807U, // <2,u,2,1>: Cost 3 vext2 LHS, <2,1,3,1> - 269271142U, // <2,u,2,2>: Cost 1 vdup2 LHS - 1544382118U, // <2,u,2,3>: Cost 2 vext2 LHS, <2,3,0,1> - 1478331702U, // <2,u,2,4>: Cost 2 vext1 <0,2,u,2>, RHS - 2618124136U, // <2,u,2,5>: Cost 3 vext2 LHS, <2,5,3,6> - 1544382394U, // <2,u,2,6>: Cost 2 vext2 LHS, <2,6,3,7> - 3088354857U, // <2,u,2,7>: Cost 3 vtrnr <0,2,0,2>, RHS - 269271142U, // <2,u,2,u>: Cost 1 vdup2 LHS - 1544382614U, // <2,u,3,0>: Cost 2 vext2 LHS, <3,0,1,2> - 2953627374U, // <2,u,3,1>: Cost 3 vzipr LHS, <2,3,u,1> - 1490282143U, // <2,u,3,2>: Cost 2 vext1 <2,2,u,3>, <2,2,u,3> - 1879883932U, // <2,u,3,3>: Cost 2 vzipr LHS, LHS - 1544382978U, // <2,u,3,4>: Cost 2 vext2 LHS, <3,4,5,6> - 2953627378U, // <2,u,3,5>: Cost 3 vzipr LHS, <2,3,u,5> - 1514172931U, // <2,u,3,6>: Cost 2 vext1 <6,2,u,3>, <6,2,u,3> - 1879887176U, // <2,u,3,7>: Cost 2 vzipr LHS, RHS - 1879883937U, // <2,u,3,u>: Cost 2 vzipr LHS, LHS - 1484316774U, // <2,u,4,0>: Cost 2 vext1 <1,2,u,4>, LHS - 1484317639U, // <2,u,4,1>: Cost 2 vext1 <1,2,u,4>, <1,2,u,4> - 2552088270U, // <2,u,4,2>: Cost 3 vext1 <0,2,u,4>, <2,3,4,5> - 1190213513U, // <2,u,4,3>: Cost 2 vrev - 1484320054U, // <2,u,4,4>: Cost 2 vext1 <1,2,u,4>, RHS - 470641974U, // <2,u,4,5>: Cost 1 vext2 LHS, RHS - 1592159604U, // <2,u,4,6>: Cost 2 vext2 LHS, <4,6,4,6> - 3094564393U, // <2,u,4,7>: Cost 3 vtrnr <1,2,3,4>, RHS - 470642217U, // <2,u,4,u>: Cost 1 vext2 LHS, RHS - 2552094959U, // <2,u,5,0>: Cost 3 vext1 <0,2,u,5>, <0,2,u,5> - 1592159952U, // <2,u,5,1>: Cost 2 vext2 LHS, <5,1,7,3> - 2564040353U, // <2,u,5,2>: Cost 3 vext1 <2,2,u,5>, <2,2,u,5> - 2690275455U, // <2,u,5,3>: Cost 3 vext3 <0,u,u,2>, - 1592160198U, // <2,u,5,4>: Cost 2 vext2 LHS, <5,4,7,6> - 1592160260U, // <2,u,5,5>: Cost 2 vext2 LHS, <5,5,5,5> - 1611962522U, // <2,u,5,6>: Cost 2 vext3 <0,2,0,2>, RHS - 1592160424U, // <2,u,5,7>: Cost 2 vext2 LHS, <5,7,5,7> - 1611962540U, // <2,u,5,u>: Cost 2 vext3 <0,2,0,2>, RHS - 1478361190U, // <2,u,6,0>: Cost 2 vext1 <0,2,u,6>, LHS - 2552103670U, // <2,u,6,1>: Cost 3 vext1 <0,2,u,6>, <1,0,3,2> - 1592160762U, // <2,u,6,2>: Cost 2 vext2 LHS, <6,2,7,3> - 2685704400U, // <2,u,6,3>: Cost 3 vext3 <0,2,0,2>, - 1478364470U, // <2,u,6,4>: Cost 2 vext1 <0,2,u,6>, RHS - 2901891226U, // <2,u,6,5>: Cost 3 vzipl <2,6,3,7>, RHS - 1592161080U, // <2,u,6,6>: Cost 2 vext2 LHS, <6,6,6,6> - 1592161102U, // <2,u,6,7>: Cost 2 vext2 LHS, <6,7,0,1> - 1478367022U, // <2,u,6,u>: Cost 2 vext1 <0,2,u,6>, LHS - 1592161274U, // <2,u,7,0>: Cost 2 vext2 LHS, <7,0,1,2> - 2659931226U, // <2,u,7,1>: Cost 3 vext2 <7,1,2,u>, <7,1,2,u> - 2564056739U, // <2,u,7,2>: Cost 3 vext1 <2,2,u,7>, <2,2,u,7> - 2665903331U, // <2,u,7,3>: Cost 3 vext2 LHS, <7,3,0,1> - 1592161638U, // <2,u,7,4>: Cost 2 vext2 LHS, <7,4,5,6> - 2665903494U, // <2,u,7,5>: Cost 3 vext2 LHS, <7,5,0,2> - 2587947527U, // <2,u,7,6>: Cost 3 vext1 <6,2,u,7>, <6,2,u,7> - 1592161900U, // <2,u,7,7>: Cost 2 vext2 LHS, <7,7,7,7> - 1592161922U, // <2,u,7,u>: Cost 2 vext2 LHS, <7,u,1,2> - 1478377574U, // <2,u,u,0>: Cost 2 vext1 <0,2,u,u>, LHS - 470644526U, // <2,u,u,1>: Cost 1 vext2 LHS, LHS - 269271142U, // <2,u,u,2>: Cost 1 vdup2 LHS - 1879924892U, // <2,u,u,3>: Cost 2 vzipr LHS, LHS - 1478380854U, // <2,u,u,4>: Cost 2 vext1 <0,2,u,u>, RHS - 470644890U, // <2,u,u,5>: Cost 1 vext2 LHS, RHS - 1611962765U, // <2,u,u,6>: Cost 2 vext3 <0,2,0,2>, RHS - 1879928136U, // <2,u,u,7>: Cost 2 vzipr LHS, RHS - 470645093U, // <2,u,u,u>: Cost 1 vext2 LHS, LHS - 1611448320U, // <3,0,0,0>: Cost 2 vext3 LHS, <0,0,0,0> - 1611890698U, // <3,0,0,1>: Cost 2 vext3 LHS, <0,0,1,1> - 1611890708U, // <3,0,0,2>: Cost 2 vext3 LHS, <0,0,2,2> - 3763576860U, // <3,0,0,3>: Cost 4 vext3 LHS, <0,0,3,1> - 2689835045U, // <3,0,0,4>: Cost 3 vext3 LHS, <0,0,4,1> - 3698508206U, // <3,0,0,5>: Cost 4 vext2 <1,2,3,0>, <0,5,2,7> - 3763576887U, // <3,0,0,6>: Cost 4 vext3 LHS, <0,0,6,1> - 3667678434U, // <3,0,0,7>: Cost 4 vext1 <7,3,0,0>, <7,3,0,0> - 1616093258U, // <3,0,0,u>: Cost 2 vext3 LHS, <0,0,u,2> - 1490337894U, // <3,0,1,0>: Cost 2 vext1 <2,3,0,1>, LHS - 2685632602U, // <3,0,1,1>: Cost 3 vext3 LHS, <0,1,1,0> - 537706598U, // <3,0,1,2>: Cost 1 vext3 LHS, LHS - 2624766936U, // <3,0,1,3>: Cost 3 vext2 <1,2,3,0>, <1,3,1,3> - 1490341174U, // <3,0,1,4>: Cost 2 vext1 <2,3,0,1>, RHS - 2624767120U, // <3,0,1,5>: Cost 3 vext2 <1,2,3,0>, <1,5,3,7> - 2732966030U, // <3,0,1,6>: Cost 3 vext3 LHS, <0,1,6,7> - 2593944803U, // <3,0,1,7>: Cost 3 vext1 <7,3,0,1>, <7,3,0,1> - 537706652U, // <3,0,1,u>: Cost 1 vext3 LHS, LHS - 1611890852U, // <3,0,2,0>: Cost 2 vext3 LHS, <0,2,0,2> - 2685632684U, // <3,0,2,1>: Cost 3 vext3 LHS, <0,2,1,1> - 2685632692U, // <3,0,2,2>: Cost 3 vext3 LHS, <0,2,2,0> - 2685632702U, // <3,0,2,3>: Cost 3 vext3 LHS, <0,2,3,1> - 1611890892U, // <3,0,2,4>: Cost 2 vext3 LHS, <0,2,4,6> - 2732966102U, // <3,0,2,5>: Cost 3 vext3 LHS, <0,2,5,7> - 2624767930U, // <3,0,2,6>: Cost 3 vext2 <1,2,3,0>, <2,6,3,7> - 2685632744U, // <3,0,2,7>: Cost 3 vext3 LHS, <0,2,7,7> - 1611890924U, // <3,0,2,u>: Cost 2 vext3 LHS, <0,2,u,2> - 2624768150U, // <3,0,3,0>: Cost 3 vext2 <1,2,3,0>, <3,0,1,2> - 2685632764U, // <3,0,3,1>: Cost 3 vext3 LHS, <0,3,1,0> - 2685632774U, // <3,0,3,2>: Cost 3 vext3 LHS, <0,3,2,1> - 2624768412U, // <3,0,3,3>: Cost 3 vext2 <1,2,3,0>, <3,3,3,3> - 2624768514U, // <3,0,3,4>: Cost 3 vext2 <1,2,3,0>, <3,4,5,6> - 3702491714U, // <3,0,3,5>: Cost 4 vext2 <1,u,3,0>, <3,5,3,7> - 2624768632U, // <3,0,3,6>: Cost 3 vext2 <1,2,3,0>, <3,6,0,7> - 3702491843U, // <3,0,3,7>: Cost 4 vext2 <1,u,3,0>, <3,7,0,1> - 2686959934U, // <3,0,3,u>: Cost 3 vext3 <0,3,u,3>, <0,3,u,3> - 2689835336U, // <3,0,4,0>: Cost 3 vext3 LHS, <0,4,0,4> - 1611891026U, // <3,0,4,1>: Cost 2 vext3 LHS, <0,4,1,5> - 1611891036U, // <3,0,4,2>: Cost 2 vext3 LHS, <0,4,2,6> - 3763577184U, // <3,0,4,3>: Cost 4 vext3 LHS, <0,4,3,1> - 2689835374U, // <3,0,4,4>: Cost 3 vext3 LHS, <0,4,4,6> - 1551027510U, // <3,0,4,5>: Cost 2 vext2 <1,2,3,0>, RHS - 2666573172U, // <3,0,4,6>: Cost 3 vext2 , <4,6,4,6> - 3667711206U, // <3,0,4,7>: Cost 4 vext1 <7,3,0,4>, <7,3,0,4> - 1616093586U, // <3,0,4,u>: Cost 2 vext3 LHS, <0,4,u,6> - 2685190556U, // <3,0,5,0>: Cost 3 vext3 LHS, <0,5,0,7> - 2666573520U, // <3,0,5,1>: Cost 3 vext2 , <5,1,7,3> - 3040886886U, // <3,0,5,2>: Cost 3 vtrnl <3,4,5,6>, LHS - 3625912834U, // <3,0,5,3>: Cost 4 vext1 <0,3,0,5>, <3,4,5,6> - 2666573766U, // <3,0,5,4>: Cost 3 vext2 , <5,4,7,6> - 2666573828U, // <3,0,5,5>: Cost 3 vext2 , <5,5,5,5> - 2732966354U, // <3,0,5,6>: Cost 3 vext3 LHS, <0,5,6,7> - 2666573992U, // <3,0,5,7>: Cost 3 vext2 , <5,7,5,7> - 3040886940U, // <3,0,5,u>: Cost 3 vtrnl <3,4,5,6>, LHS - 2685190637U, // <3,0,6,0>: Cost 3 vext3 LHS, <0,6,0,7> - 2732966390U, // <3,0,6,1>: Cost 3 vext3 LHS, <0,6,1,7> - 2689835519U, // <3,0,6,2>: Cost 3 vext3 LHS, <0,6,2,7> - 3667724438U, // <3,0,6,3>: Cost 4 vext1 <7,3,0,6>, <3,0,1,2> - 3763577355U, // <3,0,6,4>: Cost 4 vext3 LHS, <0,6,4,1> - 3806708243U, // <3,0,6,5>: Cost 4 vext3 LHS, <0,6,5,0> - 2666574648U, // <3,0,6,6>: Cost 3 vext2 , <6,6,6,6> - 2657948520U, // <3,0,6,7>: Cost 3 vext2 <6,7,3,0>, <6,7,3,0> - 2689835573U, // <3,0,6,u>: Cost 3 vext3 LHS, <0,6,u,7> - 2666574842U, // <3,0,7,0>: Cost 3 vext2 , <7,0,1,2> - 2685633095U, // <3,0,7,1>: Cost 3 vext3 LHS, <0,7,1,7> - 2660603052U, // <3,0,7,2>: Cost 3 vext2 <7,2,3,0>, <7,2,3,0> - 3643844997U, // <3,0,7,3>: Cost 4 vext1 <3,3,0,7>, <3,3,0,7> - 2666575206U, // <3,0,7,4>: Cost 3 vext2 , <7,4,5,6> - 3655790391U, // <3,0,7,5>: Cost 4 vext1 <5,3,0,7>, <5,3,0,7> - 3731690968U, // <3,0,7,6>: Cost 4 vext2 <6,7,3,0>, <7,6,0,3> - 2666575468U, // <3,0,7,7>: Cost 3 vext2 , <7,7,7,7> - 2664584850U, // <3,0,7,u>: Cost 3 vext2 <7,u,3,0>, <7,u,3,0> - 1616093834U, // <3,0,u,0>: Cost 2 vext3 LHS, <0,u,0,2> - 1611891346U, // <3,0,u,1>: Cost 2 vext3 LHS, <0,u,1,1> - 537707165U, // <3,0,u,2>: Cost 1 vext3 LHS, LHS - 2689835684U, // <3,0,u,3>: Cost 3 vext3 LHS, <0,u,3,1> - 1616093874U, // <3,0,u,4>: Cost 2 vext3 LHS, <0,u,4,6> - 1551030426U, // <3,0,u,5>: Cost 2 vext2 <1,2,3,0>, RHS - 2624772304U, // <3,0,u,6>: Cost 3 vext2 <1,2,3,0>, - 2594002154U, // <3,0,u,7>: Cost 3 vext1 <7,3,0,u>, <7,3,0,u> - 537707219U, // <3,0,u,u>: Cost 1 vext3 LHS, LHS - 2552201318U, // <3,1,0,0>: Cost 3 vext1 <0,3,1,0>, LHS - 2618802278U, // <3,1,0,1>: Cost 3 vext2 <0,2,3,1>, LHS - 2618802366U, // <3,1,0,2>: Cost 3 vext2 <0,2,3,1>, <0,2,3,1> - 1611449078U, // <3,1,0,3>: Cost 2 vext3 LHS, <1,0,3,2> - 2552204598U, // <3,1,0,4>: Cost 3 vext1 <0,3,1,0>, RHS - 2732966663U, // <3,1,0,5>: Cost 3 vext3 LHS, <1,0,5,1> - 3906258396U, // <3,1,0,6>: Cost 4 vuzpr <2,3,0,1>, <2,0,4,6> - 3667752171U, // <3,1,0,7>: Cost 4 vext1 <7,3,1,0>, <7,3,1,0> - 1611891491U, // <3,1,0,u>: Cost 2 vext3 LHS, <1,0,u,2> - 2689835819U, // <3,1,1,0>: Cost 3 vext3 LHS, <1,1,0,1> - 1611449140U, // <3,1,1,1>: Cost 2 vext3 LHS, <1,1,1,1> - 2624775063U, // <3,1,1,2>: Cost 3 vext2 <1,2,3,1>, <1,2,3,1> - 1611891528U, // <3,1,1,3>: Cost 2 vext3 LHS, <1,1,3,3> - 2689835859U, // <3,1,1,4>: Cost 3 vext3 LHS, <1,1,4,5> - 2689835868U, // <3,1,1,5>: Cost 3 vext3 LHS, <1,1,5,5> - 3763577701U, // <3,1,1,6>: Cost 4 vext3 LHS, <1,1,6,5> - 3765273452U, // <3,1,1,7>: Cost 4 vext3 <1,1,7,3>, <1,1,7,3> - 1611891573U, // <3,1,1,u>: Cost 2 vext3 LHS, <1,1,u,3> - 2629420494U, // <3,1,2,0>: Cost 3 vext2 <2,0,3,1>, <2,0,3,1> - 2689835911U, // <3,1,2,1>: Cost 3 vext3 LHS, <1,2,1,3> - 2564163248U, // <3,1,2,2>: Cost 3 vext1 <2,3,1,2>, <2,3,1,2> - 1611449238U, // <3,1,2,3>: Cost 2 vext3 LHS, <1,2,3,0> - 2564164918U, // <3,1,2,4>: Cost 3 vext1 <2,3,1,2>, RHS - 2689835947U, // <3,1,2,5>: Cost 3 vext3 LHS, <1,2,5,3> - 3692545978U, // <3,1,2,6>: Cost 4 vext2 <0,2,3,1>, <2,6,3,7> - 2732966842U, // <3,1,2,7>: Cost 3 vext3 LHS, <1,2,7,0> - 1611891651U, // <3,1,2,u>: Cost 2 vext3 LHS, <1,2,u,0> - 1484456038U, // <3,1,3,0>: Cost 2 vext1 <1,3,1,3>, LHS - 1611891672U, // <3,1,3,1>: Cost 2 vext3 LHS, <1,3,1,3> - 2685633502U, // <3,1,3,2>: Cost 3 vext3 LHS, <1,3,2,0> - 2685633512U, // <3,1,3,3>: Cost 3 vext3 LHS, <1,3,3,1> - 1484459318U, // <3,1,3,4>: Cost 2 vext1 <1,3,1,3>, RHS - 1611891712U, // <3,1,3,5>: Cost 2 vext3 LHS, <1,3,5,7> - 2689836041U, // <3,1,3,6>: Cost 3 vext3 LHS, <1,3,6,7> - 2733409294U, // <3,1,3,7>: Cost 3 vext3 LHS, <1,3,7,3> - 1611891735U, // <3,1,3,u>: Cost 2 vext3 LHS, <1,3,u,3> - 2552234086U, // <3,1,4,0>: Cost 3 vext1 <0,3,1,4>, LHS - 2732966955U, // <3,1,4,1>: Cost 3 vext3 LHS, <1,4,1,5> - 2732966964U, // <3,1,4,2>: Cost 3 vext3 LHS, <1,4,2,5> - 2685633597U, // <3,1,4,3>: Cost 3 vext3 LHS, <1,4,3,5> - 2552237366U, // <3,1,4,4>: Cost 3 vext1 <0,3,1,4>, RHS - 2618805558U, // <3,1,4,5>: Cost 3 vext2 <0,2,3,1>, RHS - 2769472822U, // <3,1,4,6>: Cost 3 vuzpl <3,0,1,2>, RHS - 3667784943U, // <3,1,4,7>: Cost 4 vext1 <7,3,1,4>, <7,3,1,4> - 2685633642U, // <3,1,4,u>: Cost 3 vext3 LHS, <1,4,u,5> - 2689836143U, // <3,1,5,0>: Cost 3 vext3 LHS, <1,5,0,1> - 2564187280U, // <3,1,5,1>: Cost 3 vext1 <2,3,1,5>, <1,5,3,7> - 2564187827U, // <3,1,5,2>: Cost 3 vext1 <2,3,1,5>, <2,3,1,5> - 1611891856U, // <3,1,5,3>: Cost 2 vext3 LHS, <1,5,3,7> - 2689836183U, // <3,1,5,4>: Cost 3 vext3 LHS, <1,5,4,5> - 3759375522U, // <3,1,5,5>: Cost 4 vext3 LHS, <1,5,5,7> - 3720417378U, // <3,1,5,6>: Cost 4 vext2 <4,u,3,1>, <5,6,7,0> - 2832518454U, // <3,1,5,7>: Cost 3 vuzpr <2,3,0,1>, RHS - 1611891901U, // <3,1,5,u>: Cost 2 vext3 LHS, <1,5,u,7> - 3763578048U, // <3,1,6,0>: Cost 4 vext3 LHS, <1,6,0,1> - 2689836239U, // <3,1,6,1>: Cost 3 vext3 LHS, <1,6,1,7> - 2732967128U, // <3,1,6,2>: Cost 3 vext3 LHS, <1,6,2,7> - 2685633761U, // <3,1,6,3>: Cost 3 vext3 LHS, <1,6,3,7> - 3763578088U, // <3,1,6,4>: Cost 4 vext3 LHS, <1,6,4,5> - 2689836275U, // <3,1,6,5>: Cost 3 vext3 LHS, <1,6,5,7> - 3763578108U, // <3,1,6,6>: Cost 4 vext3 LHS, <1,6,6,7> - 2732967166U, // <3,1,6,7>: Cost 3 vext3 LHS, <1,6,7,0> - 2685633806U, // <3,1,6,u>: Cost 3 vext3 LHS, <1,6,u,7> - 3631972454U, // <3,1,7,0>: Cost 4 vext1 <1,3,1,7>, LHS - 2659947612U, // <3,1,7,1>: Cost 3 vext2 <7,1,3,1>, <7,1,3,1> - 4036102294U, // <3,1,7,2>: Cost 4 vzipr <1,5,3,7>, <3,0,1,2> - 3095396454U, // <3,1,7,3>: Cost 3 vtrnr <1,3,5,7>, LHS - 3631975734U, // <3,1,7,4>: Cost 4 vext1 <1,3,1,7>, RHS - 2222982144U, // <3,1,7,5>: Cost 3 vrev <1,3,5,7> - 3296797705U, // <3,1,7,6>: Cost 4 vrev <1,3,6,7> - 3720418924U, // <3,1,7,7>: Cost 4 vext2 <4,u,3,1>, <7,7,7,7> - 3095396459U, // <3,1,7,u>: Cost 3 vtrnr <1,3,5,7>, LHS - 1484496998U, // <3,1,u,0>: Cost 2 vext1 <1,3,1,u>, LHS - 1611892077U, // <3,1,u,1>: Cost 2 vext3 LHS, <1,u,1,3> - 2685633907U, // <3,1,u,2>: Cost 3 vext3 LHS, <1,u,2,0> - 1611892092U, // <3,1,u,3>: Cost 2 vext3 LHS, <1,u,3,0> - 1484500278U, // <3,1,u,4>: Cost 2 vext1 <1,3,1,u>, RHS - 1611892117U, // <3,1,u,5>: Cost 2 vext3 LHS, <1,u,5,7> - 2685633950U, // <3,1,u,6>: Cost 3 vext3 LHS, <1,u,6,7> - 2832518697U, // <3,1,u,7>: Cost 3 vuzpr <2,3,0,1>, RHS - 1611892140U, // <3,1,u,u>: Cost 2 vext3 LHS, <1,u,u,3> - 2623455232U, // <3,2,0,0>: Cost 3 vext2 <1,0,3,2>, <0,0,0,0> - 1549713510U, // <3,2,0,1>: Cost 2 vext2 <1,0,3,2>, LHS - 2689836484U, // <3,2,0,2>: Cost 3 vext3 LHS, <2,0,2,0> - 2685633997U, // <3,2,0,3>: Cost 3 vext3 LHS, <2,0,3,0> - 2623455570U, // <3,2,0,4>: Cost 3 vext2 <1,0,3,2>, <0,4,1,5> - 2732967398U, // <3,2,0,5>: Cost 3 vext3 LHS, <2,0,5,7> - 2689836524U, // <3,2,0,6>: Cost 3 vext3 LHS, <2,0,6,4> - 2229044964U, // <3,2,0,7>: Cost 3 vrev <2,3,7,0> - 1549714077U, // <3,2,0,u>: Cost 2 vext2 <1,0,3,2>, LHS - 1549714166U, // <3,2,1,0>: Cost 2 vext2 <1,0,3,2>, <1,0,3,2> - 2623456052U, // <3,2,1,1>: Cost 3 vext2 <1,0,3,2>, <1,1,1,1> - 2623456150U, // <3,2,1,2>: Cost 3 vext2 <1,0,3,2>, <1,2,3,0> - 2685634079U, // <3,2,1,3>: Cost 3 vext3 LHS, <2,1,3,1> - 2552286518U, // <3,2,1,4>: Cost 3 vext1 <0,3,2,1>, RHS - 2623456400U, // <3,2,1,5>: Cost 3 vext2 <1,0,3,2>, <1,5,3,7> - 2689836604U, // <3,2,1,6>: Cost 3 vext3 LHS, <2,1,6,3> - 3667834101U, // <3,2,1,7>: Cost 4 vext1 <7,3,2,1>, <7,3,2,1> - 1155385070U, // <3,2,1,u>: Cost 2 vrev <2,3,u,1> - 2689836629U, // <3,2,2,0>: Cost 3 vext3 LHS, <2,2,0,1> - 2689836640U, // <3,2,2,1>: Cost 3 vext3 LHS, <2,2,1,3> - 1611449960U, // <3,2,2,2>: Cost 2 vext3 LHS, <2,2,2,2> - 1611892338U, // <3,2,2,3>: Cost 2 vext3 LHS, <2,2,3,3> - 2689836669U, // <3,2,2,4>: Cost 3 vext3 LHS, <2,2,4,5> - 2689836680U, // <3,2,2,5>: Cost 3 vext3 LHS, <2,2,5,7> - 2689836688U, // <3,2,2,6>: Cost 3 vext3 LHS, <2,2,6,6> - 3763578518U, // <3,2,2,7>: Cost 4 vext3 LHS, <2,2,7,3> - 1611892383U, // <3,2,2,u>: Cost 2 vext3 LHS, <2,2,u,3> - 1611450022U, // <3,2,3,0>: Cost 2 vext3 LHS, <2,3,0,1> - 2685191854U, // <3,2,3,1>: Cost 3 vext3 LHS, <2,3,1,0> - 2685191865U, // <3,2,3,2>: Cost 3 vext3 LHS, <2,3,2,2> - 2685191875U, // <3,2,3,3>: Cost 3 vext3 LHS, <2,3,3,3> - 1611450062U, // <3,2,3,4>: Cost 2 vext3 LHS, <2,3,4,5> - 2732967635U, // <3,2,3,5>: Cost 3 vext3 LHS, <2,3,5,1> - 2732967645U, // <3,2,3,6>: Cost 3 vext3 LHS, <2,3,6,2> - 2732967652U, // <3,2,3,7>: Cost 3 vext3 LHS, <2,3,7,0> - 1611450094U, // <3,2,3,u>: Cost 2 vext3 LHS, <2,3,u,1> - 2558279782U, // <3,2,4,0>: Cost 3 vext1 <1,3,2,4>, LHS - 2558280602U, // <3,2,4,1>: Cost 3 vext1 <1,3,2,4>, <1,2,3,4> - 2732967692U, // <3,2,4,2>: Cost 3 vext3 LHS, <2,4,2,4> - 2685634326U, // <3,2,4,3>: Cost 3 vext3 LHS, <2,4,3,5> - 2558283062U, // <3,2,4,4>: Cost 3 vext1 <1,3,2,4>, RHS - 1549716790U, // <3,2,4,5>: Cost 2 vext2 <1,0,3,2>, RHS - 2689836844U, // <3,2,4,6>: Cost 3 vext3 LHS, <2,4,6,0> - 2229077736U, // <3,2,4,7>: Cost 3 vrev <2,3,7,4> - 1549717033U, // <3,2,4,u>: Cost 2 vext2 <1,0,3,2>, RHS - 2552316006U, // <3,2,5,0>: Cost 3 vext1 <0,3,2,5>, LHS - 2228643507U, // <3,2,5,1>: Cost 3 vrev <2,3,1,5> - 2689836896U, // <3,2,5,2>: Cost 3 vext3 LHS, <2,5,2,7> - 2685634408U, // <3,2,5,3>: Cost 3 vext3 LHS, <2,5,3,6> - 1155122894U, // <3,2,5,4>: Cost 2 vrev <2,3,4,5> - 2665263108U, // <3,2,5,5>: Cost 3 vext2 , <5,5,5,5> - 2689836932U, // <3,2,5,6>: Cost 3 vext3 LHS, <2,5,6,7> - 2665263272U, // <3,2,5,7>: Cost 3 vext2 , <5,7,5,7> - 1155417842U, // <3,2,5,u>: Cost 2 vrev <2,3,u,5> - 2689836953U, // <3,2,6,0>: Cost 3 vext3 LHS, <2,6,0,1> - 2689836964U, // <3,2,6,1>: Cost 3 vext3 LHS, <2,6,1,3> - 2689836976U, // <3,2,6,2>: Cost 3 vext3 LHS, <2,6,2,6> - 1611892666U, // <3,2,6,3>: Cost 2 vext3 LHS, <2,6,3,7> - 2689836993U, // <3,2,6,4>: Cost 3 vext3 LHS, <2,6,4,5> - 2689837004U, // <3,2,6,5>: Cost 3 vext3 LHS, <2,6,5,7> - 2689837013U, // <3,2,6,6>: Cost 3 vext3 LHS, <2,6,6,7> - 2665263950U, // <3,2,6,7>: Cost 3 vext2 , <6,7,0,1> - 1611892711U, // <3,2,6,u>: Cost 2 vext3 LHS, <2,6,u,7> - 2665264122U, // <3,2,7,0>: Cost 3 vext2 , <7,0,1,2> - 2623460419U, // <3,2,7,1>: Cost 3 vext2 <1,0,3,2>, <7,1,0,3> - 4169138340U, // <3,2,7,2>: Cost 4 vtrnr <1,3,5,7>, <0,2,0,2> - 2962358374U, // <3,2,7,3>: Cost 3 vzipr <1,5,3,7>, LHS - 2665264486U, // <3,2,7,4>: Cost 3 vext2 , <7,4,5,6> - 2228954841U, // <3,2,7,5>: Cost 3 vrev <2,3,5,7> - 2229028578U, // <3,2,7,6>: Cost 3 vrev <2,3,6,7> - 2665264748U, // <3,2,7,7>: Cost 3 vext2 , <7,7,7,7> - 2962358379U, // <3,2,7,u>: Cost 3 vzipr <1,5,3,7>, LHS - 1611892795U, // <3,2,u,0>: Cost 2 vext3 LHS, <2,u,0,1> - 1549719342U, // <3,2,u,1>: Cost 2 vext2 <1,0,3,2>, LHS - 1611449960U, // <3,2,u,2>: Cost 2 vext3 LHS, <2,2,2,2> - 1611892824U, // <3,2,u,3>: Cost 2 vext3 LHS, <2,u,3,3> - 1611892835U, // <3,2,u,4>: Cost 2 vext3 LHS, <2,u,4,5> - 1549719706U, // <3,2,u,5>: Cost 2 vext2 <1,0,3,2>, RHS - 2689837168U, // <3,2,u,6>: Cost 3 vext3 LHS, <2,u,6,0> - 2665265408U, // <3,2,u,7>: Cost 3 vext2 , - 1611892867U, // <3,2,u,u>: Cost 2 vext3 LHS, <2,u,u,1> - 2685192331U, // <3,3,0,0>: Cost 3 vext3 LHS, <3,0,0,0> - 1611450518U, // <3,3,0,1>: Cost 2 vext3 LHS, <3,0,1,2> - 2685634717U, // <3,3,0,2>: Cost 3 vext3 LHS, <3,0,2,0> - 2564294806U, // <3,3,0,3>: Cost 3 vext1 <2,3,3,0>, <3,0,1,2> - 2685634736U, // <3,3,0,4>: Cost 3 vext3 LHS, <3,0,4,1> - 2732968122U, // <3,3,0,5>: Cost 3 vext3 LHS, <3,0,5,2> - 3763579075U, // <3,3,0,6>: Cost 4 vext3 LHS, <3,0,6,2> - 4034053264U, // <3,3,0,7>: Cost 4 vzipr <1,2,3,0>, <1,5,3,7> - 1611450581U, // <3,3,0,u>: Cost 2 vext3 LHS, <3,0,u,2> - 2685192415U, // <3,3,1,0>: Cost 3 vext3 LHS, <3,1,0,3> - 1550385992U, // <3,3,1,1>: Cost 2 vext2 <1,1,3,3>, <1,1,3,3> - 2685192433U, // <3,3,1,2>: Cost 3 vext3 LHS, <3,1,2,3> - 2685634808U, // <3,3,1,3>: Cost 3 vext3 LHS, <3,1,3,1> - 2558332214U, // <3,3,1,4>: Cost 3 vext1 <1,3,3,1>, RHS - 2685634828U, // <3,3,1,5>: Cost 3 vext3 LHS, <3,1,5,3> - 3759376661U, // <3,3,1,6>: Cost 4 vext3 LHS, <3,1,6,3> - 2703477022U, // <3,3,1,7>: Cost 3 vext3 <3,1,7,3>, <3,1,7,3> - 1555031423U, // <3,3,1,u>: Cost 2 vext2 <1,u,3,3>, <1,u,3,3> - 2564309094U, // <3,3,2,0>: Cost 3 vext1 <2,3,3,2>, LHS - 2630100513U, // <3,3,2,1>: Cost 3 vext2 <2,1,3,3>, <2,1,3,3> - 1557022322U, // <3,3,2,2>: Cost 2 vext2 <2,2,3,3>, <2,2,3,3> - 2685192520U, // <3,3,2,3>: Cost 3 vext3 LHS, <3,2,3,0> - 2564312374U, // <3,3,2,4>: Cost 3 vext1 <2,3,3,2>, RHS - 2732968286U, // <3,3,2,5>: Cost 3 vext3 LHS, <3,2,5,4> - 2685634918U, // <3,3,2,6>: Cost 3 vext3 LHS, <3,2,6,3> - 2704140655U, // <3,3,2,7>: Cost 3 vext3 <3,2,7,3>, <3,2,7,3> - 1561004120U, // <3,3,2,u>: Cost 2 vext2 <2,u,3,3>, <2,u,3,3> - 1496547430U, // <3,3,3,0>: Cost 2 vext1 <3,3,3,3>, LHS - 2624129256U, // <3,3,3,1>: Cost 3 vext2 <1,1,3,3>, <3,1,1,3> - 2630764866U, // <3,3,3,2>: Cost 3 vext2 <2,2,3,3>, <3,2,2,3> - 336380006U, // <3,3,3,3>: Cost 1 vdup3 LHS - 1496550710U, // <3,3,3,4>: Cost 2 vext1 <3,3,3,3>, RHS - 2732968368U, // <3,3,3,5>: Cost 3 vext3 LHS, <3,3,5,5> - 2624129683U, // <3,3,3,6>: Cost 3 vext2 <1,1,3,3>, <3,6,3,7> - 2594182400U, // <3,3,3,7>: Cost 3 vext1 <7,3,3,3>, <7,3,3,3> - 336380006U, // <3,3,3,u>: Cost 1 vdup3 LHS - 2558353510U, // <3,3,4,0>: Cost 3 vext1 <1,3,3,4>, LHS - 2558354411U, // <3,3,4,1>: Cost 3 vext1 <1,3,3,4>, <1,3,3,4> - 2564327108U, // <3,3,4,2>: Cost 3 vext1 <2,3,3,4>, <2,3,3,4> - 2564327938U, // <3,3,4,3>: Cost 3 vext1 <2,3,3,4>, <3,4,5,6> - 2960343962U, // <3,3,4,4>: Cost 3 vzipr <1,2,3,4>, <1,2,3,4> - 1611893250U, // <3,3,4,5>: Cost 2 vext3 LHS, <3,4,5,6> - 2771619126U, // <3,3,4,6>: Cost 3 vuzpl <3,3,3,3>, RHS - 4034086032U, // <3,3,4,7>: Cost 4 vzipr <1,2,3,4>, <1,5,3,7> - 1611893277U, // <3,3,4,u>: Cost 2 vext3 LHS, <3,4,u,6> - 2558361702U, // <3,3,5,0>: Cost 3 vext1 <1,3,3,5>, LHS - 2558362604U, // <3,3,5,1>: Cost 3 vext1 <1,3,3,5>, <1,3,3,5> - 2558363342U, // <3,3,5,2>: Cost 3 vext1 <1,3,3,5>, <2,3,4,5> - 2732968512U, // <3,3,5,3>: Cost 3 vext3 LHS, <3,5,3,5> - 2558364982U, // <3,3,5,4>: Cost 3 vext1 <1,3,3,5>, RHS - 3101279950U, // <3,3,5,5>: Cost 3 vtrnr <2,3,4,5>, <2,3,4,5> - 2665934946U, // <3,3,5,6>: Cost 3 vext2 , <5,6,7,0> - 2826636598U, // <3,3,5,7>: Cost 3 vuzpr <1,3,1,3>, RHS - 2826636599U, // <3,3,5,u>: Cost 3 vuzpr <1,3,1,3>, RHS - 2732968568U, // <3,3,6,0>: Cost 3 vext3 LHS, <3,6,0,7> - 3763579521U, // <3,3,6,1>: Cost 4 vext3 LHS, <3,6,1,7> - 2732968586U, // <3,3,6,2>: Cost 3 vext3 LHS, <3,6,2,7> - 2732968595U, // <3,3,6,3>: Cost 3 vext3 LHS, <3,6,3,7> - 2732968604U, // <3,3,6,4>: Cost 3 vext3 LHS, <3,6,4,7> - 3763579557U, // <3,3,6,5>: Cost 4 vext3 LHS, <3,6,5,7> - 2732968621U, // <3,3,6,6>: Cost 3 vext3 LHS, <3,6,6,6> - 2657973099U, // <3,3,6,7>: Cost 3 vext2 <6,7,3,3>, <6,7,3,3> - 2658636732U, // <3,3,6,u>: Cost 3 vext2 <6,u,3,3>, <6,u,3,3> - 2558378086U, // <3,3,7,0>: Cost 3 vext1 <1,3,3,7>, LHS - 2558378990U, // <3,3,7,1>: Cost 3 vext1 <1,3,3,7>, <1,3,3,7> - 2564351687U, // <3,3,7,2>: Cost 3 vext1 <2,3,3,7>, <2,3,3,7> - 2661291264U, // <3,3,7,3>: Cost 3 vext2 <7,3,3,3>, <7,3,3,3> - 2558381366U, // <3,3,7,4>: Cost 3 vext1 <1,3,3,7>, RHS - 2732968694U, // <3,3,7,5>: Cost 3 vext3 LHS, <3,7,5,7> - 3781126907U, // <3,3,7,6>: Cost 4 vext3 <3,7,6,3>, <3,7,6,3> - 3095397376U, // <3,3,7,7>: Cost 3 vtrnr <1,3,5,7>, <1,3,5,7> - 2558383918U, // <3,3,7,u>: Cost 3 vext1 <1,3,3,7>, LHS - 1496547430U, // <3,3,u,0>: Cost 2 vext1 <3,3,3,3>, LHS - 1611893534U, // <3,3,u,1>: Cost 2 vext3 LHS, <3,u,1,2> - 1592858504U, // <3,3,u,2>: Cost 2 vext2 , - 336380006U, // <3,3,u,3>: Cost 1 vdup3 LHS - 1496550710U, // <3,3,u,4>: Cost 2 vext1 <3,3,3,3>, RHS - 1611893574U, // <3,3,u,5>: Cost 2 vext3 LHS, <3,u,5,6> - 2690280268U, // <3,3,u,6>: Cost 3 vext3 LHS, <3,u,6,3> - 2826636841U, // <3,3,u,7>: Cost 3 vuzpr <1,3,1,3>, RHS - 336380006U, // <3,3,u,u>: Cost 1 vdup3 LHS - 2624798720U, // <3,4,0,0>: Cost 3 vext2 <1,2,3,4>, <0,0,0,0> - 1551056998U, // <3,4,0,1>: Cost 2 vext2 <1,2,3,4>, LHS - 2624798884U, // <3,4,0,2>: Cost 3 vext2 <1,2,3,4>, <0,2,0,2> - 3693232384U, // <3,4,0,3>: Cost 4 vext2 <0,3,3,4>, <0,3,1,4> - 2624799058U, // <3,4,0,4>: Cost 3 vext2 <1,2,3,4>, <0,4,1,5> - 1659227026U, // <3,4,0,5>: Cost 2 vext3 LHS, <4,0,5,1> - 1659227036U, // <3,4,0,6>: Cost 2 vext3 LHS, <4,0,6,2> - 3667973382U, // <3,4,0,7>: Cost 4 vext1 <7,3,4,0>, <7,3,4,0> - 1551057565U, // <3,4,0,u>: Cost 2 vext2 <1,2,3,4>, LHS - 2624799478U, // <3,4,1,0>: Cost 3 vext2 <1,2,3,4>, <1,0,3,2> - 2624799540U, // <3,4,1,1>: Cost 3 vext2 <1,2,3,4>, <1,1,1,1> - 1551057818U, // <3,4,1,2>: Cost 2 vext2 <1,2,3,4>, <1,2,3,4> - 2624799704U, // <3,4,1,3>: Cost 3 vext2 <1,2,3,4>, <1,3,1,3> - 2564377910U, // <3,4,1,4>: Cost 3 vext1 <2,3,4,1>, RHS - 2689838050U, // <3,4,1,5>: Cost 3 vext3 LHS, <4,1,5,0> - 2689838062U, // <3,4,1,6>: Cost 3 vext3 LHS, <4,1,6,3> - 2628117807U, // <3,4,1,7>: Cost 3 vext2 <1,7,3,4>, <1,7,3,4> - 1555039616U, // <3,4,1,u>: Cost 2 vext2 <1,u,3,4>, <1,u,3,4> - 3626180710U, // <3,4,2,0>: Cost 4 vext1 <0,3,4,2>, LHS - 2624800298U, // <3,4,2,1>: Cost 3 vext2 <1,2,3,4>, <2,1,4,3> - 2624800360U, // <3,4,2,2>: Cost 3 vext2 <1,2,3,4>, <2,2,2,2> - 2624800422U, // <3,4,2,3>: Cost 3 vext2 <1,2,3,4>, <2,3,0,1> - 2624800514U, // <3,4,2,4>: Cost 3 vext2 <1,2,3,4>, <2,4,1,3> - 2709965878U, // <3,4,2,5>: Cost 3 vext3 <4,2,5,3>, <4,2,5,3> - 2689838140U, // <3,4,2,6>: Cost 3 vext3 LHS, <4,2,6,0> - 2634090504U, // <3,4,2,7>: Cost 3 vext2 <2,7,3,4>, <2,7,3,4> - 2689838158U, // <3,4,2,u>: Cost 3 vext3 LHS, <4,2,u,0> - 2624800918U, // <3,4,3,0>: Cost 3 vext2 <1,2,3,4>, <3,0,1,2> - 2636081403U, // <3,4,3,1>: Cost 3 vext2 <3,1,3,4>, <3,1,3,4> - 2636745036U, // <3,4,3,2>: Cost 3 vext2 <3,2,3,4>, <3,2,3,4> - 2624801180U, // <3,4,3,3>: Cost 3 vext2 <1,2,3,4>, <3,3,3,3> - 2624801232U, // <3,4,3,4>: Cost 3 vext2 <1,2,3,4>, <3,4,0,1> - 2905836854U, // <3,4,3,5>: Cost 3 vzipl <3,3,3,3>, RHS - 3040054582U, // <3,4,3,6>: Cost 3 vtrnl <3,3,3,3>, RHS - 3702524611U, // <3,4,3,7>: Cost 4 vext2 <1,u,3,4>, <3,7,0,1> - 2624801566U, // <3,4,3,u>: Cost 3 vext2 <1,2,3,4>, <3,u,1,2> - 2564399206U, // <3,4,4,0>: Cost 3 vext1 <2,3,4,4>, LHS - 2564400026U, // <3,4,4,1>: Cost 3 vext1 <2,3,4,4>, <1,2,3,4> - 2564400845U, // <3,4,4,2>: Cost 3 vext1 <2,3,4,4>, <2,3,4,4> - 2570373542U, // <3,4,4,3>: Cost 3 vext1 <3,3,4,4>, <3,3,4,4> - 1659227344U, // <3,4,4,4>: Cost 2 vext3 LHS, <4,4,4,4> - 1551060278U, // <3,4,4,5>: Cost 2 vext2 <1,2,3,4>, RHS - 1659227364U, // <3,4,4,6>: Cost 2 vext3 LHS, <4,4,6,6> - 3668006154U, // <3,4,4,7>: Cost 4 vext1 <7,3,4,4>, <7,3,4,4> - 1551060521U, // <3,4,4,u>: Cost 2 vext2 <1,2,3,4>, RHS - 1490665574U, // <3,4,5,0>: Cost 2 vext1 <2,3,4,5>, LHS - 2689838341U, // <3,4,5,1>: Cost 3 vext3 LHS, <4,5,1,3> - 1490667214U, // <3,4,5,2>: Cost 2 vext1 <2,3,4,5>, <2,3,4,5> - 2564409494U, // <3,4,5,3>: Cost 3 vext1 <2,3,4,5>, <3,0,1,2> - 1490668854U, // <3,4,5,4>: Cost 2 vext1 <2,3,4,5>, RHS - 2689838381U, // <3,4,5,5>: Cost 3 vext3 LHS, <4,5,5,7> - 537709878U, // <3,4,5,6>: Cost 1 vext3 LHS, RHS - 2594272523U, // <3,4,5,7>: Cost 3 vext1 <7,3,4,5>, <7,3,4,5> - 537709896U, // <3,4,5,u>: Cost 1 vext3 LHS, RHS - 2689838411U, // <3,4,6,0>: Cost 3 vext3 LHS, <4,6,0,1> - 2558444534U, // <3,4,6,1>: Cost 3 vext1 <1,3,4,6>, <1,3,4,6> - 2666607098U, // <3,4,6,2>: Cost 3 vext2 , <6,2,7,3> - 2558446082U, // <3,4,6,3>: Cost 3 vext1 <1,3,4,6>, <3,4,5,6> - 1659227508U, // <3,4,6,4>: Cost 2 vext3 LHS, <4,6,4,6> - 2689838462U, // <3,4,6,5>: Cost 3 vext3 LHS, <4,6,5,7> - 2689838471U, // <3,4,6,6>: Cost 3 vext3 LHS, <4,6,6,7> - 2657981292U, // <3,4,6,7>: Cost 3 vext2 <6,7,3,4>, <6,7,3,4> - 1659227540U, // <3,4,6,u>: Cost 2 vext3 LHS, <4,6,u,2> - 2666607610U, // <3,4,7,0>: Cost 3 vext2 , <7,0,1,2> - 3702527072U, // <3,4,7,1>: Cost 4 vext2 <1,u,3,4>, <7,1,3,5> - 2660635824U, // <3,4,7,2>: Cost 3 vext2 <7,2,3,4>, <7,2,3,4> - 3644139945U, // <3,4,7,3>: Cost 4 vext1 <3,3,4,7>, <3,3,4,7> - 2666607974U, // <3,4,7,4>: Cost 3 vext2 , <7,4,5,6> - 2732969416U, // <3,4,7,5>: Cost 3 vext3 LHS, <4,7,5,0> - 2732969425U, // <3,4,7,6>: Cost 3 vext3 LHS, <4,7,6,0> - 2666608236U, // <3,4,7,7>: Cost 3 vext2 , <7,7,7,7> - 2664617622U, // <3,4,7,u>: Cost 3 vext2 <7,u,3,4>, <7,u,3,4> - 1490690150U, // <3,4,u,0>: Cost 2 vext1 <2,3,4,u>, LHS - 1551062830U, // <3,4,u,1>: Cost 2 vext2 <1,2,3,4>, LHS - 1490691793U, // <3,4,u,2>: Cost 2 vext1 <2,3,4,u>, <2,3,4,u> - 2624804796U, // <3,4,u,3>: Cost 3 vext2 <1,2,3,4>, - 1490693430U, // <3,4,u,4>: Cost 2 vext1 <2,3,4,u>, RHS - 1551063194U, // <3,4,u,5>: Cost 2 vext2 <1,2,3,4>, RHS - 537710121U, // <3,4,u,6>: Cost 1 vext3 LHS, RHS - 2594297102U, // <3,4,u,7>: Cost 3 vext1 <7,3,4,u>, <7,3,4,u> - 537710139U, // <3,4,u,u>: Cost 1 vext3 LHS, RHS - 3692576768U, // <3,5,0,0>: Cost 4 vext2 <0,2,3,5>, <0,0,0,0> - 2618835046U, // <3,5,0,1>: Cost 3 vext2 <0,2,3,5>, LHS - 2618835138U, // <3,5,0,2>: Cost 3 vext2 <0,2,3,5>, <0,2,3,5> - 3692577024U, // <3,5,0,3>: Cost 4 vext2 <0,2,3,5>, <0,3,1,4> - 2689838690U, // <3,5,0,4>: Cost 3 vext3 LHS, <5,0,4,1> - 2732969579U, // <3,5,0,5>: Cost 3 vext3 LHS, <5,0,5,1> - 2732969588U, // <3,5,0,6>: Cost 3 vext3 LHS, <5,0,6,1> - 2246963055U, // <3,5,0,7>: Cost 3 vrev <5,3,7,0> - 2618835613U, // <3,5,0,u>: Cost 3 vext2 <0,2,3,5>, LHS - 2594308198U, // <3,5,1,0>: Cost 3 vext1 <7,3,5,1>, LHS - 3692577588U, // <3,5,1,1>: Cost 4 vext2 <0,2,3,5>, <1,1,1,1> - 2624807835U, // <3,5,1,2>: Cost 3 vext2 <1,2,3,5>, <1,2,3,5> - 2625471468U, // <3,5,1,3>: Cost 3 vext2 <1,3,3,5>, <1,3,3,5> - 2626135101U, // <3,5,1,4>: Cost 3 vext2 <1,4,3,5>, <1,4,3,5> - 2594311888U, // <3,5,1,5>: Cost 3 vext1 <7,3,5,1>, <5,1,7,3> - 3699877107U, // <3,5,1,6>: Cost 4 vext2 <1,4,3,5>, <1,6,5,7> - 1641680592U, // <3,5,1,7>: Cost 2 vext3 <5,1,7,3>, <5,1,7,3> - 1641754329U, // <3,5,1,u>: Cost 2 vext3 <5,1,u,3>, <5,1,u,3> - 3692578274U, // <3,5,2,0>: Cost 4 vext2 <0,2,3,5>, <2,0,5,3> - 2630116899U, // <3,5,2,1>: Cost 3 vext2 <2,1,3,5>, <2,1,3,5> - 3692578408U, // <3,5,2,2>: Cost 4 vext2 <0,2,3,5>, <2,2,2,2> - 2625472206U, // <3,5,2,3>: Cost 3 vext2 <1,3,3,5>, <2,3,4,5> - 2632107798U, // <3,5,2,4>: Cost 3 vext2 <2,4,3,5>, <2,4,3,5> - 2715938575U, // <3,5,2,5>: Cost 3 vext3 <5,2,5,3>, <5,2,5,3> - 3692578746U, // <3,5,2,6>: Cost 4 vext2 <0,2,3,5>, <2,6,3,7> - 2716086049U, // <3,5,2,7>: Cost 3 vext3 <5,2,7,3>, <5,2,7,3> - 2634762330U, // <3,5,2,u>: Cost 3 vext2 <2,u,3,5>, <2,u,3,5> - 3692578966U, // <3,5,3,0>: Cost 4 vext2 <0,2,3,5>, <3,0,1,2> - 2636089596U, // <3,5,3,1>: Cost 3 vext2 <3,1,3,5>, <3,1,3,5> - 3699214668U, // <3,5,3,2>: Cost 4 vext2 <1,3,3,5>, <3,2,3,4> - 2638080412U, // <3,5,3,3>: Cost 3 vext2 <3,4,3,5>, <3,3,3,3> - 2618837506U, // <3,5,3,4>: Cost 3 vext2 <0,2,3,5>, <3,4,5,6> - 2832844494U, // <3,5,3,5>: Cost 3 vuzpr <2,3,4,5>, <2,3,4,5> - 4033415682U, // <3,5,3,6>: Cost 4 vzipr <1,1,3,3>, <3,4,5,6> - 3095072054U, // <3,5,3,7>: Cost 3 vtrnr <1,3,1,3>, RHS - 3095072055U, // <3,5,3,u>: Cost 3 vtrnr <1,3,1,3>, RHS - 2600304742U, // <3,5,4,0>: Cost 3 vext1 , LHS - 3763580815U, // <3,5,4,1>: Cost 4 vext3 LHS, <5,4,1,5> - 2564474582U, // <3,5,4,2>: Cost 3 vext1 <2,3,5,4>, <2,3,5,4> - 3699879044U, // <3,5,4,3>: Cost 4 vext2 <1,4,3,5>, <4,3,5,0> - 2600308022U, // <3,5,4,4>: Cost 3 vext1 , RHS - 2618838326U, // <3,5,4,5>: Cost 3 vext2 <0,2,3,5>, RHS - 2772454710U, // <3,5,4,6>: Cost 3 vuzpl <3,4,5,6>, RHS - 1659228102U, // <3,5,4,7>: Cost 2 vext3 LHS, <5,4,7,6> - 1659228111U, // <3,5,4,u>: Cost 2 vext3 LHS, <5,4,u,6> - 2570453094U, // <3,5,5,0>: Cost 3 vext1 <3,3,5,5>, LHS - 2624810704U, // <3,5,5,1>: Cost 3 vext2 <1,2,3,5>, <5,1,7,3> - 2570454734U, // <3,5,5,2>: Cost 3 vext1 <3,3,5,5>, <2,3,4,5> - 2570455472U, // <3,5,5,3>: Cost 3 vext1 <3,3,5,5>, <3,3,5,5> - 2570456374U, // <3,5,5,4>: Cost 3 vext1 <3,3,5,5>, RHS - 1659228164U, // <3,5,5,5>: Cost 2 vext3 LHS, <5,5,5,5> - 2732969998U, // <3,5,5,6>: Cost 3 vext3 LHS, <5,5,6,6> - 1659228184U, // <3,5,5,7>: Cost 2 vext3 LHS, <5,5,7,7> - 1659228193U, // <3,5,5,u>: Cost 2 vext3 LHS, <5,5,u,7> - 2732970020U, // <3,5,6,0>: Cost 3 vext3 LHS, <5,6,0,1> - 2732970035U, // <3,5,6,1>: Cost 3 vext3 LHS, <5,6,1,7> - 2564490968U, // <3,5,6,2>: Cost 3 vext1 <2,3,5,6>, <2,3,5,6> - 2732970050U, // <3,5,6,3>: Cost 3 vext3 LHS, <5,6,3,4> - 2732970060U, // <3,5,6,4>: Cost 3 vext3 LHS, <5,6,4,5> - 2732970071U, // <3,5,6,5>: Cost 3 vext3 LHS, <5,6,5,7> - 2732970080U, // <3,5,6,6>: Cost 3 vext3 LHS, <5,6,6,7> - 1659228258U, // <3,5,6,7>: Cost 2 vext3 LHS, <5,6,7,0> - 1659228267U, // <3,5,6,u>: Cost 2 vext3 LHS, <5,6,u,0> - 1484783718U, // <3,5,7,0>: Cost 2 vext1 <1,3,5,7>, LHS - 1484784640U, // <3,5,7,1>: Cost 2 vext1 <1,3,5,7>, <1,3,5,7> - 2558527080U, // <3,5,7,2>: Cost 3 vext1 <1,3,5,7>, <2,2,2,2> - 2558527638U, // <3,5,7,3>: Cost 3 vext1 <1,3,5,7>, <3,0,1,2> - 1484786998U, // <3,5,7,4>: Cost 2 vext1 <1,3,5,7>, RHS - 1659228328U, // <3,5,7,5>: Cost 2 vext3 LHS, <5,7,5,7> - 2732970154U, // <3,5,7,6>: Cost 3 vext3 LHS, <5,7,6,0> - 2558531180U, // <3,5,7,7>: Cost 3 vext1 <1,3,5,7>, <7,7,7,7> - 1484789550U, // <3,5,7,u>: Cost 2 vext1 <1,3,5,7>, LHS - 1484791910U, // <3,5,u,0>: Cost 2 vext1 <1,3,5,u>, LHS - 1484792833U, // <3,5,u,1>: Cost 2 vext1 <1,3,5,u>, <1,3,5,u> - 2558535272U, // <3,5,u,2>: Cost 3 vext1 <1,3,5,u>, <2,2,2,2> - 2558535830U, // <3,5,u,3>: Cost 3 vext1 <1,3,5,u>, <3,0,1,2> - 1484795190U, // <3,5,u,4>: Cost 2 vext1 <1,3,5,u>, RHS - 1659228409U, // <3,5,u,5>: Cost 2 vext3 LHS, <5,u,5,7> - 2772457626U, // <3,5,u,6>: Cost 3 vuzpl <3,4,5,6>, RHS - 1646326023U, // <3,5,u,7>: Cost 2 vext3 <5,u,7,3>, <5,u,7,3> - 1484797742U, // <3,5,u,u>: Cost 2 vext1 <1,3,5,u>, LHS - 2558541926U, // <3,6,0,0>: Cost 3 vext1 <1,3,6,0>, LHS - 2689839393U, // <3,6,0,1>: Cost 3 vext3 LHS, <6,0,1,2> - 2689839404U, // <3,6,0,2>: Cost 3 vext3 LHS, <6,0,2,4> - 3706519808U, // <3,6,0,3>: Cost 4 vext2 <2,5,3,6>, <0,3,1,4> - 2689839420U, // <3,6,0,4>: Cost 3 vext3 LHS, <6,0,4,2> - 2732970314U, // <3,6,0,5>: Cost 3 vext3 LHS, <6,0,5,7> - 2732970316U, // <3,6,0,6>: Cost 3 vext3 LHS, <6,0,6,0> - 2960313654U, // <3,6,0,7>: Cost 3 vzipr <1,2,3,0>, RHS - 2689839456U, // <3,6,0,u>: Cost 3 vext3 LHS, <6,0,u,2> - 3763581290U, // <3,6,1,0>: Cost 4 vext3 LHS, <6,1,0,3> - 3763581297U, // <3,6,1,1>: Cost 4 vext3 LHS, <6,1,1,1> - 2624816028U, // <3,6,1,2>: Cost 3 vext2 <1,2,3,6>, <1,2,3,6> - 3763581315U, // <3,6,1,3>: Cost 4 vext3 LHS, <6,1,3,1> - 2626143294U, // <3,6,1,4>: Cost 3 vext2 <1,4,3,6>, <1,4,3,6> - 3763581335U, // <3,6,1,5>: Cost 4 vext3 LHS, <6,1,5,3> - 2721321376U, // <3,6,1,6>: Cost 3 vext3 <6,1,6,3>, <6,1,6,3> - 2721395113U, // <3,6,1,7>: Cost 3 vext3 <6,1,7,3>, <6,1,7,3> - 2628797826U, // <3,6,1,u>: Cost 3 vext2 <1,u,3,6>, <1,u,3,6> - 2594390118U, // <3,6,2,0>: Cost 3 vext1 <7,3,6,2>, LHS - 2721616324U, // <3,6,2,1>: Cost 3 vext3 <6,2,1,3>, <6,2,1,3> - 2630788725U, // <3,6,2,2>: Cost 3 vext2 <2,2,3,6>, <2,2,3,6> - 3763581395U, // <3,6,2,3>: Cost 4 vext3 LHS, <6,2,3,0> - 2632115991U, // <3,6,2,4>: Cost 3 vext2 <2,4,3,6>, <2,4,3,6> - 2632779624U, // <3,6,2,5>: Cost 3 vext2 <2,5,3,6>, <2,5,3,6> - 2594394618U, // <3,6,2,6>: Cost 3 vext1 <7,3,6,2>, <6,2,7,3> - 1648316922U, // <3,6,2,7>: Cost 2 vext3 <6,2,7,3>, <6,2,7,3> - 1648390659U, // <3,6,2,u>: Cost 2 vext3 <6,2,u,3>, <6,2,u,3> - 3693914262U, // <3,6,3,0>: Cost 4 vext2 <0,4,3,6>, <3,0,1,2> - 3638281176U, // <3,6,3,1>: Cost 4 vext1 <2,3,6,3>, <1,3,1,3> - 3696568678U, // <3,6,3,2>: Cost 4 vext2 <0,u,3,6>, <3,2,6,3> - 2638088604U, // <3,6,3,3>: Cost 3 vext2 <3,4,3,6>, <3,3,3,3> - 2632780290U, // <3,6,3,4>: Cost 3 vext2 <2,5,3,6>, <3,4,5,6> - 3712494145U, // <3,6,3,5>: Cost 4 vext2 <3,5,3,6>, <3,5,3,6> - 3698559612U, // <3,6,3,6>: Cost 4 vext2 <1,2,3,6>, <3,6,1,2> - 2959674678U, // <3,6,3,7>: Cost 3 vzipr <1,1,3,3>, RHS - 2959674679U, // <3,6,3,u>: Cost 3 vzipr <1,1,3,3>, RHS - 3763581536U, // <3,6,4,0>: Cost 4 vext3 LHS, <6,4,0,6> - 2722943590U, // <3,6,4,1>: Cost 3 vext3 <6,4,1,3>, <6,4,1,3> - 2732970609U, // <3,6,4,2>: Cost 3 vext3 LHS, <6,4,2,5> - 3698560147U, // <3,6,4,3>: Cost 4 vext2 <1,2,3,6>, <4,3,6,6> - 2732970628U, // <3,6,4,4>: Cost 3 vext3 LHS, <6,4,4,6> - 2689839757U, // <3,6,4,5>: Cost 3 vext3 LHS, <6,4,5,6> - 2732970640U, // <3,6,4,6>: Cost 3 vext3 LHS, <6,4,6,0> - 2960346422U, // <3,6,4,7>: Cost 3 vzipr <1,2,3,4>, RHS - 2689839784U, // <3,6,4,u>: Cost 3 vext3 LHS, <6,4,u,6> - 2576498790U, // <3,6,5,0>: Cost 3 vext1 <4,3,6,5>, LHS - 3650241270U, // <3,6,5,1>: Cost 4 vext1 <4,3,6,5>, <1,0,3,2> - 2732970692U, // <3,6,5,2>: Cost 3 vext3 LHS, <6,5,2,7> - 2576501250U, // <3,6,5,3>: Cost 3 vext1 <4,3,6,5>, <3,4,5,6> - 2576501906U, // <3,6,5,4>: Cost 3 vext1 <4,3,6,5>, <4,3,6,5> - 3650244622U, // <3,6,5,5>: Cost 4 vext1 <4,3,6,5>, <5,5,6,6> - 4114633528U, // <3,6,5,6>: Cost 4 vtrnl <3,4,5,6>, <6,6,6,6> - 2732970735U, // <3,6,5,7>: Cost 3 vext3 LHS, <6,5,7,5> - 2576504622U, // <3,6,5,u>: Cost 3 vext1 <4,3,6,5>, LHS - 2732970749U, // <3,6,6,0>: Cost 3 vext3 LHS, <6,6,0,1> - 2724270856U, // <3,6,6,1>: Cost 3 vext3 <6,6,1,3>, <6,6,1,3> - 2624819706U, // <3,6,6,2>: Cost 3 vext2 <1,2,3,6>, <6,2,7,3> - 3656223234U, // <3,6,6,3>: Cost 4 vext1 <5,3,6,6>, <3,4,5,6> - 2732970788U, // <3,6,6,4>: Cost 3 vext3 LHS, <6,6,4,4> - 2732970800U, // <3,6,6,5>: Cost 3 vext3 LHS, <6,6,5,7> - 1659228984U, // <3,6,6,6>: Cost 2 vext3 LHS, <6,6,6,6> - 1659228994U, // <3,6,6,7>: Cost 2 vext3 LHS, <6,6,7,7> - 1659229003U, // <3,6,6,u>: Cost 2 vext3 LHS, <6,6,u,7> - 1659229006U, // <3,6,7,0>: Cost 2 vext3 LHS, <6,7,0,1> - 2558600201U, // <3,6,7,1>: Cost 3 vext1 <1,3,6,7>, <1,3,6,7> - 2558601146U, // <3,6,7,2>: Cost 3 vext1 <1,3,6,7>, <2,6,3,7> - 2725081963U, // <3,6,7,3>: Cost 3 vext3 <6,7,3,3>, <6,7,3,3> - 1659229046U, // <3,6,7,4>: Cost 2 vext3 LHS, <6,7,4,5> - 2715423611U, // <3,6,7,5>: Cost 3 vext3 <5,1,7,3>, <6,7,5,1> - 2722059141U, // <3,6,7,6>: Cost 3 vext3 <6,2,7,3>, <6,7,6,2> - 2962361654U, // <3,6,7,7>: Cost 3 vzipr <1,5,3,7>, RHS - 1659229078U, // <3,6,7,u>: Cost 2 vext3 LHS, <6,7,u,1> - 1659229087U, // <3,6,u,0>: Cost 2 vext3 LHS, <6,u,0,1> - 2689840041U, // <3,6,u,1>: Cost 3 vext3 LHS, <6,u,1,2> - 2558609339U, // <3,6,u,2>: Cost 3 vext1 <1,3,6,u>, <2,6,3,u> - 2576525853U, // <3,6,u,3>: Cost 3 vext1 <4,3,6,u>, <3,4,u,6> - 1659229127U, // <3,6,u,4>: Cost 2 vext3 LHS, <6,u,4,5> - 2689840081U, // <3,6,u,5>: Cost 3 vext3 LHS, <6,u,5,6> - 1659228984U, // <3,6,u,6>: Cost 2 vext3 LHS, <6,6,6,6> - 1652298720U, // <3,6,u,7>: Cost 2 vext3 <6,u,7,3>, <6,u,7,3> - 1659229159U, // <3,6,u,u>: Cost 2 vext3 LHS, <6,u,u,1> - 2626813952U, // <3,7,0,0>: Cost 3 vext2 <1,5,3,7>, <0,0,0,0> - 1553072230U, // <3,7,0,1>: Cost 2 vext2 <1,5,3,7>, LHS - 2626814116U, // <3,7,0,2>: Cost 3 vext2 <1,5,3,7>, <0,2,0,2> - 3700556028U, // <3,7,0,3>: Cost 4 vext2 <1,5,3,7>, <0,3,1,0> - 2626814290U, // <3,7,0,4>: Cost 3 vext2 <1,5,3,7>, <0,4,1,5> - 2582507375U, // <3,7,0,5>: Cost 3 vext1 <5,3,7,0>, <5,3,7,0> - 2588480072U, // <3,7,0,6>: Cost 3 vext1 <6,3,7,0>, <6,3,7,0> - 2732971055U, // <3,7,0,7>: Cost 3 vext3 LHS, <7,0,7,1> - 1553072797U, // <3,7,0,u>: Cost 2 vext2 <1,5,3,7>, LHS - 2626814710U, // <3,7,1,0>: Cost 3 vext2 <1,5,3,7>, <1,0,3,2> - 2626814772U, // <3,7,1,1>: Cost 3 vext2 <1,5,3,7>, <1,1,1,1> - 2626814870U, // <3,7,1,2>: Cost 3 vext2 <1,5,3,7>, <1,2,3,0> - 2625487854U, // <3,7,1,3>: Cost 3 vext2 <1,3,3,7>, <1,3,3,7> - 2582514998U, // <3,7,1,4>: Cost 3 vext1 <5,3,7,1>, RHS - 1553073296U, // <3,7,1,5>: Cost 2 vext2 <1,5,3,7>, <1,5,3,7> - 2627478753U, // <3,7,1,6>: Cost 3 vext2 <1,6,3,7>, <1,6,3,7> - 2727367810U, // <3,7,1,7>: Cost 3 vext3 <7,1,7,3>, <7,1,7,3> - 1555064195U, // <3,7,1,u>: Cost 2 vext2 <1,u,3,7>, <1,u,3,7> - 2588491878U, // <3,7,2,0>: Cost 3 vext1 <6,3,7,2>, LHS - 3700557318U, // <3,7,2,1>: Cost 4 vext2 <1,5,3,7>, <2,1,0,3> - 2626815592U, // <3,7,2,2>: Cost 3 vext2 <1,5,3,7>, <2,2,2,2> - 2626815654U, // <3,7,2,3>: Cost 3 vext2 <1,5,3,7>, <2,3,0,1> - 2588495158U, // <3,7,2,4>: Cost 3 vext1 <6,3,7,2>, RHS - 2632787817U, // <3,7,2,5>: Cost 3 vext2 <2,5,3,7>, <2,5,3,7> - 1559709626U, // <3,7,2,6>: Cost 2 vext2 <2,6,3,7>, <2,6,3,7> - 2728031443U, // <3,7,2,7>: Cost 3 vext3 <7,2,7,3>, <7,2,7,3> - 1561036892U, // <3,7,2,u>: Cost 2 vext2 <2,u,3,7>, <2,u,3,7> - 2626816150U, // <3,7,3,0>: Cost 3 vext2 <1,5,3,7>, <3,0,1,2> - 2626816268U, // <3,7,3,1>: Cost 3 vext2 <1,5,3,7>, <3,1,5,3> - 2633451878U, // <3,7,3,2>: Cost 3 vext2 <2,6,3,7>, <3,2,6,3> - 2626816412U, // <3,7,3,3>: Cost 3 vext2 <1,5,3,7>, <3,3,3,3> - 2626816514U, // <3,7,3,4>: Cost 3 vext2 <1,5,3,7>, <3,4,5,6> - 2638760514U, // <3,7,3,5>: Cost 3 vext2 <3,5,3,7>, <3,5,3,7> - 2639424147U, // <3,7,3,6>: Cost 3 vext2 <3,6,3,7>, <3,6,3,7> - 2826961920U, // <3,7,3,7>: Cost 3 vuzpr <1,3,5,7>, <1,3,5,7> - 2626816798U, // <3,7,3,u>: Cost 3 vext2 <1,5,3,7>, <3,u,1,2> - 2582536294U, // <3,7,4,0>: Cost 3 vext1 <5,3,7,4>, LHS - 2582537360U, // <3,7,4,1>: Cost 3 vext1 <5,3,7,4>, <1,5,3,7> - 2588510138U, // <3,7,4,2>: Cost 3 vext1 <6,3,7,4>, <2,6,3,7> - 3700558996U, // <3,7,4,3>: Cost 4 vext2 <1,5,3,7>, <4,3,6,7> - 2582539574U, // <3,7,4,4>: Cost 3 vext1 <5,3,7,4>, RHS - 1553075510U, // <3,7,4,5>: Cost 2 vext2 <1,5,3,7>, RHS - 2588512844U, // <3,7,4,6>: Cost 3 vext1 <6,3,7,4>, <6,3,7,4> - 2564625766U, // <3,7,4,7>: Cost 3 vext1 <2,3,7,4>, <7,4,5,6> - 1553075753U, // <3,7,4,u>: Cost 2 vext2 <1,5,3,7>, RHS - 2732971398U, // <3,7,5,0>: Cost 3 vext3 LHS, <7,5,0,2> - 2626817744U, // <3,7,5,1>: Cost 3 vext2 <1,5,3,7>, <5,1,7,3> - 3700559649U, // <3,7,5,2>: Cost 4 vext2 <1,5,3,7>, <5,2,7,3> - 2626817903U, // <3,7,5,3>: Cost 3 vext2 <1,5,3,7>, <5,3,7,0> - 2258728203U, // <3,7,5,4>: Cost 3 vrev <7,3,4,5> - 2732971446U, // <3,7,5,5>: Cost 3 vext3 LHS, <7,5,5,5> - 2732971457U, // <3,7,5,6>: Cost 3 vext3 LHS, <7,5,6,7> - 2826964278U, // <3,7,5,7>: Cost 3 vuzpr <1,3,5,7>, RHS - 2826964279U, // <3,7,5,u>: Cost 3 vuzpr <1,3,5,7>, RHS - 2732971478U, // <3,7,6,0>: Cost 3 vext3 LHS, <7,6,0,1> - 2732971486U, // <3,7,6,1>: Cost 3 vext3 LHS, <7,6,1,0> - 2633454074U, // <3,7,6,2>: Cost 3 vext2 <2,6,3,7>, <6,2,7,3> - 2633454152U, // <3,7,6,3>: Cost 3 vext2 <2,6,3,7>, <6,3,7,0> - 2732971518U, // <3,7,6,4>: Cost 3 vext3 LHS, <7,6,4,5> - 2732971526U, // <3,7,6,5>: Cost 3 vext3 LHS, <7,6,5,4> - 2732971537U, // <3,7,6,6>: Cost 3 vext3 LHS, <7,6,6,6> - 2732971540U, // <3,7,6,7>: Cost 3 vext3 LHS, <7,6,7,0> - 2726041124U, // <3,7,6,u>: Cost 3 vext3 <6,u,7,3>, <7,6,u,7> - 2570616934U, // <3,7,7,0>: Cost 3 vext1 <3,3,7,7>, LHS - 2570617856U, // <3,7,7,1>: Cost 3 vext1 <3,3,7,7>, <1,3,5,7> - 2564646635U, // <3,7,7,2>: Cost 3 vext1 <2,3,7,7>, <2,3,7,7> - 2570619332U, // <3,7,7,3>: Cost 3 vext1 <3,3,7,7>, <3,3,7,7> - 2570620214U, // <3,7,7,4>: Cost 3 vext1 <3,3,7,7>, RHS - 2582564726U, // <3,7,7,5>: Cost 3 vext1 <5,3,7,7>, <5,3,7,7> - 2588537423U, // <3,7,7,6>: Cost 3 vext1 <6,3,7,7>, <6,3,7,7> - 1659229804U, // <3,7,7,7>: Cost 2 vext3 LHS, <7,7,7,7> - 1659229804U, // <3,7,7,u>: Cost 2 vext3 LHS, <7,7,7,7> - 2626819795U, // <3,7,u,0>: Cost 3 vext2 <1,5,3,7>, - 1553078062U, // <3,7,u,1>: Cost 2 vext2 <1,5,3,7>, LHS - 2626819973U, // <3,7,u,2>: Cost 3 vext2 <1,5,3,7>, - 2826961565U, // <3,7,u,3>: Cost 3 vuzpr <1,3,5,7>, LHS - 2626820159U, // <3,7,u,4>: Cost 3 vext2 <1,5,3,7>, - 1553078426U, // <3,7,u,5>: Cost 2 vext2 <1,5,3,7>, RHS - 1595545808U, // <3,7,u,6>: Cost 2 vext2 , - 1659229804U, // <3,7,u,7>: Cost 2 vext3 LHS, <7,7,7,7> - 1553078629U, // <3,7,u,u>: Cost 2 vext2 <1,5,3,7>, LHS - 1611448320U, // <3,u,0,0>: Cost 2 vext3 LHS, <0,0,0,0> - 1611896531U, // <3,u,0,1>: Cost 2 vext3 LHS, - 1659672284U, // <3,u,0,2>: Cost 2 vext3 LHS, - 1616099045U, // <3,u,0,3>: Cost 2 vext3 LHS, - 2685638381U, // <3,u,0,4>: Cost 3 vext3 LHS, - 1663874806U, // <3,u,0,5>: Cost 2 vext3 LHS, - 1663874816U, // <3,u,0,6>: Cost 2 vext3 LHS, - 2960313672U, // <3,u,0,7>: Cost 3 vzipr <1,2,3,0>, RHS - 1611896594U, // <3,u,0,u>: Cost 2 vext3 LHS, - 1549763324U, // <3,u,1,0>: Cost 2 vext2 <1,0,3,u>, <1,0,3,u> - 1550426957U, // <3,u,1,1>: Cost 2 vext2 <1,1,3,u>, <1,1,3,u> - 537712430U, // <3,u,1,2>: Cost 1 vext3 LHS, LHS - 1616541495U, // <3,u,1,3>: Cost 2 vext3 LHS, - 1490930998U, // <3,u,1,4>: Cost 2 vext1 <2,3,u,1>, RHS - 1553081489U, // <3,u,1,5>: Cost 2 vext2 <1,5,3,u>, <1,5,3,u> - 2627486946U, // <3,u,1,6>: Cost 3 vext2 <1,6,3,u>, <1,6,3,u> - 1659230043U, // <3,u,1,7>: Cost 2 vext3 LHS, - 537712484U, // <3,u,1,u>: Cost 1 vext3 LHS, LHS - 1611890852U, // <3,u,2,0>: Cost 2 vext3 LHS, <0,2,0,2> - 2624833102U, // <3,u,2,1>: Cost 3 vext2 <1,2,3,u>, <2,1,u,3> - 1557063287U, // <3,u,2,2>: Cost 2 vext2 <2,2,3,u>, <2,2,3,u> - 1616099205U, // <3,u,2,3>: Cost 2 vext3 LHS, - 1611890892U, // <3,u,2,4>: Cost 2 vext3 LHS, <0,2,4,6> - 2689841054U, // <3,u,2,5>: Cost 3 vext3 LHS, - 1559717819U, // <3,u,2,6>: Cost 2 vext2 <2,6,3,u>, <2,6,3,u> - 1659230124U, // <3,u,2,7>: Cost 2 vext3 LHS, - 1616541618U, // <3,u,2,u>: Cost 2 vext3 LHS, - 1611896764U, // <3,u,3,0>: Cost 2 vext3 LHS, - 1484973079U, // <3,u,3,1>: Cost 2 vext1 <1,3,u,3>, <1,3,u,3> - 2685638607U, // <3,u,3,2>: Cost 3 vext3 LHS, - 336380006U, // <3,u,3,3>: Cost 1 vdup3 LHS - 1611896804U, // <3,u,3,4>: Cost 2 vext3 LHS, - 1616541679U, // <3,u,3,5>: Cost 2 vext3 LHS, - 2690283512U, // <3,u,3,6>: Cost 3 vext3 LHS, - 2959674696U, // <3,u,3,7>: Cost 3 vzipr <1,1,3,3>, RHS - 336380006U, // <3,u,3,u>: Cost 1 vdup3 LHS - 2558722150U, // <3,u,4,0>: Cost 3 vext1 <1,3,u,4>, LHS - 1659672602U, // <3,u,4,1>: Cost 2 vext3 LHS, - 1659672612U, // <3,u,4,2>: Cost 2 vext3 LHS, - 2689841196U, // <3,u,4,3>: Cost 3 vext3 LHS, - 1659227344U, // <3,u,4,4>: Cost 2 vext3 LHS, <4,4,4,4> - 1611896895U, // <3,u,4,5>: Cost 2 vext3 LHS, - 1663875144U, // <3,u,4,6>: Cost 2 vext3 LHS, - 1659230289U, // <3,u,4,7>: Cost 2 vext3 LHS, - 1611896922U, // <3,u,4,u>: Cost 2 vext3 LHS, - 1490960486U, // <3,u,5,0>: Cost 2 vext1 <2,3,u,5>, LHS - 2689841261U, // <3,u,5,1>: Cost 3 vext3 LHS, - 1490962162U, // <3,u,5,2>: Cost 2 vext1 <2,3,u,5>, <2,3,u,5> - 1616541823U, // <3,u,5,3>: Cost 2 vext3 LHS, - 1490963766U, // <3,u,5,4>: Cost 2 vext1 <2,3,u,5>, RHS - 1659228164U, // <3,u,5,5>: Cost 2 vext3 LHS, <5,5,5,5> - 537712794U, // <3,u,5,6>: Cost 1 vext3 LHS, RHS - 1659230371U, // <3,u,5,7>: Cost 2 vext3 LHS, - 537712812U, // <3,u,5,u>: Cost 1 vext3 LHS, RHS - 2689841327U, // <3,u,6,0>: Cost 3 vext3 LHS, - 2558739482U, // <3,u,6,1>: Cost 3 vext1 <1,3,u,6>, <1,3,u,6> - 2689841351U, // <3,u,6,2>: Cost 3 vext3 LHS, - 1616099536U, // <3,u,6,3>: Cost 2 vext3 LHS, - 1659227508U, // <3,u,6,4>: Cost 2 vext3 LHS, <4,6,4,6> - 2690283746U, // <3,u,6,5>: Cost 3 vext3 LHS, - 1659228984U, // <3,u,6,6>: Cost 2 vext3 LHS, <6,6,6,6> - 1659230445U, // <3,u,6,7>: Cost 2 vext3 LHS, - 1616099581U, // <3,u,6,u>: Cost 2 vext3 LHS, - 1485004902U, // <3,u,7,0>: Cost 2 vext1 <1,3,u,7>, LHS - 1485005851U, // <3,u,7,1>: Cost 2 vext1 <1,3,u,7>, <1,3,u,7> - 2558748264U, // <3,u,7,2>: Cost 3 vext1 <1,3,u,7>, <2,2,2,2> - 3095397021U, // <3,u,7,3>: Cost 3 vtrnr <1,3,5,7>, LHS - 1485008182U, // <3,u,7,4>: Cost 2 vext1 <1,3,u,7>, RHS - 1659228328U, // <3,u,7,5>: Cost 2 vext3 LHS, <5,7,5,7> - 2722060599U, // <3,u,7,6>: Cost 3 vext3 <6,2,7,3>, - 1659229804U, // <3,u,7,7>: Cost 2 vext3 LHS, <7,7,7,7> - 1485010734U, // <3,u,7,u>: Cost 2 vext1 <1,3,u,7>, LHS - 1616099665U, // <3,u,u,0>: Cost 2 vext3 LHS, - 1611897179U, // <3,u,u,1>: Cost 2 vext3 LHS, - 537712997U, // <3,u,u,2>: Cost 1 vext3 LHS, LHS - 336380006U, // <3,u,u,3>: Cost 1 vdup3 LHS - 1616099705U, // <3,u,u,4>: Cost 2 vext3 LHS, - 1611897219U, // <3,u,u,5>: Cost 2 vext3 LHS, - 537713037U, // <3,u,u,6>: Cost 1 vext3 LHS, RHS - 1659230607U, // <3,u,u,7>: Cost 2 vext3 LHS, - 537713051U, // <3,u,u,u>: Cost 1 vext3 LHS, LHS - 2691907584U, // <4,0,0,0>: Cost 3 vext3 <1,2,3,4>, <0,0,0,0> - 2691907594U, // <4,0,0,1>: Cost 3 vext3 <1,2,3,4>, <0,0,1,1> - 2691907604U, // <4,0,0,2>: Cost 3 vext3 <1,2,3,4>, <0,0,2,2> - 3709862144U, // <4,0,0,3>: Cost 4 vext2 <3,1,4,0>, <0,3,1,4> - 2684682280U, // <4,0,0,4>: Cost 3 vext3 <0,0,4,4>, <0,0,4,4> - 3694600633U, // <4,0,0,5>: Cost 4 vext2 <0,5,4,0>, <0,5,4,0> - 3291431290U, // <4,0,0,6>: Cost 4 vrev <0,4,6,0> - 3668342067U, // <4,0,0,7>: Cost 4 vext1 <7,4,0,0>, <7,4,0,0> - 2691907657U, // <4,0,0,u>: Cost 3 vext3 <1,2,3,4>, <0,0,u,1> - 2570715238U, // <4,0,1,0>: Cost 3 vext1 <3,4,0,1>, LHS - 2570716058U, // <4,0,1,1>: Cost 3 vext1 <3,4,0,1>, <1,2,3,4> - 1618165862U, // <4,0,1,2>: Cost 2 vext3 <1,2,3,4>, LHS - 2570717648U, // <4,0,1,3>: Cost 3 vext1 <3,4,0,1>, <3,4,0,1> - 2570718518U, // <4,0,1,4>: Cost 3 vext1 <3,4,0,1>, RHS - 2594607206U, // <4,0,1,5>: Cost 3 vext1 <7,4,0,1>, <5,6,7,4> - 3662377563U, // <4,0,1,6>: Cost 4 vext1 <6,4,0,1>, <6,4,0,1> - 2594608436U, // <4,0,1,7>: Cost 3 vext1 <7,4,0,1>, <7,4,0,1> - 1618165916U, // <4,0,1,u>: Cost 2 vext3 <1,2,3,4>, LHS - 2685714598U, // <4,0,2,0>: Cost 3 vext3 <0,2,0,4>, <0,2,0,4> - 3759530159U, // <4,0,2,1>: Cost 4 vext3 <0,2,1,4>, <0,2,1,4> - 2685862072U, // <4,0,2,2>: Cost 3 vext3 <0,2,2,4>, <0,2,2,4> - 2631476937U, // <4,0,2,3>: Cost 3 vext2 <2,3,4,0>, <2,3,4,0> - 2685714636U, // <4,0,2,4>: Cost 3 vext3 <0,2,0,4>, <0,2,4,6> - 3765649622U, // <4,0,2,5>: Cost 4 vext3 <1,2,3,4>, <0,2,5,7> - 2686157020U, // <4,0,2,6>: Cost 3 vext3 <0,2,6,4>, <0,2,6,4> - 3668358453U, // <4,0,2,7>: Cost 4 vext1 <7,4,0,2>, <7,4,0,2> - 2686304494U, // <4,0,2,u>: Cost 3 vext3 <0,2,u,4>, <0,2,u,4> - 3632529510U, // <4,0,3,0>: Cost 4 vext1 <1,4,0,3>, LHS - 2686451968U, // <4,0,3,1>: Cost 3 vext3 <0,3,1,4>, <0,3,1,4> - 2686525705U, // <4,0,3,2>: Cost 3 vext3 <0,3,2,4>, <0,3,2,4> - 3760341266U, // <4,0,3,3>: Cost 4 vext3 <0,3,3,4>, <0,3,3,4> - 3632532790U, // <4,0,3,4>: Cost 4 vext1 <1,4,0,3>, RHS - 3913254606U, // <4,0,3,5>: Cost 4 vuzpr <3,4,5,0>, <2,3,4,5> - 3705219740U, // <4,0,3,6>: Cost 4 vext2 <2,3,4,0>, <3,6,4,7> - 3713845990U, // <4,0,3,7>: Cost 4 vext2 <3,7,4,0>, <3,7,4,0> - 2686451968U, // <4,0,3,u>: Cost 3 vext3 <0,3,1,4>, <0,3,1,4> - 2552823910U, // <4,0,4,0>: Cost 3 vext1 <0,4,0,4>, LHS - 2691907922U, // <4,0,4,1>: Cost 3 vext3 <1,2,3,4>, <0,4,1,5> - 2691907932U, // <4,0,4,2>: Cost 3 vext3 <1,2,3,4>, <0,4,2,6> - 3626567830U, // <4,0,4,3>: Cost 4 vext1 <0,4,0,4>, <3,0,1,2> - 2552827190U, // <4,0,4,4>: Cost 3 vext1 <0,4,0,4>, RHS - 2631478582U, // <4,0,4,5>: Cost 3 vext2 <2,3,4,0>, RHS - 3626570017U, // <4,0,4,6>: Cost 4 vext1 <0,4,0,4>, <6,0,1,2> - 3668374839U, // <4,0,4,7>: Cost 4 vext1 <7,4,0,4>, <7,4,0,4> - 2552829742U, // <4,0,4,u>: Cost 3 vext1 <0,4,0,4>, LHS - 2558804070U, // <4,0,5,0>: Cost 3 vext1 <1,4,0,5>, LHS - 1839644774U, // <4,0,5,1>: Cost 2 vzipl RHS, LHS - 2913386660U, // <4,0,5,2>: Cost 3 vzipl RHS, <0,2,0,2> - 2570750420U, // <4,0,5,3>: Cost 3 vext1 <3,4,0,5>, <3,4,0,5> - 2558807350U, // <4,0,5,4>: Cost 3 vext1 <1,4,0,5>, RHS - 3987128750U, // <4,0,5,5>: Cost 4 vzipl RHS, <0,5,2,7> - 3987128822U, // <4,0,5,6>: Cost 4 vzipl RHS, <0,6,1,7> - 2594641208U, // <4,0,5,7>: Cost 3 vext1 <7,4,0,5>, <7,4,0,5> - 1839645341U, // <4,0,5,u>: Cost 2 vzipl RHS, LHS - 2552840294U, // <4,0,6,0>: Cost 3 vext1 <0,4,0,6>, LHS - 3047604234U, // <4,0,6,1>: Cost 3 vtrnl RHS, <0,0,1,1> - 1973862502U, // <4,0,6,2>: Cost 2 vtrnl RHS, LHS - 2570758613U, // <4,0,6,3>: Cost 3 vext1 <3,4,0,6>, <3,4,0,6> - 2552843574U, // <4,0,6,4>: Cost 3 vext1 <0,4,0,6>, RHS - 2217664887U, // <4,0,6,5>: Cost 3 vrev <0,4,5,6> - 3662418528U, // <4,0,6,6>: Cost 4 vext1 <6,4,0,6>, <6,4,0,6> - 2658022257U, // <4,0,6,7>: Cost 3 vext2 <6,7,4,0>, <6,7,4,0> - 1973862556U, // <4,0,6,u>: Cost 2 vtrnl RHS, LHS - 3731764218U, // <4,0,7,0>: Cost 4 vext2 <6,7,4,0>, <7,0,1,2> - 3988324454U, // <4,0,7,1>: Cost 4 vzipl <4,7,5,0>, LHS - 4122034278U, // <4,0,7,2>: Cost 4 vtrnl <4,6,7,1>, LHS - 3735082246U, // <4,0,7,3>: Cost 4 vext2 <7,3,4,0>, <7,3,4,0> - 3731764536U, // <4,0,7,4>: Cost 4 vext2 <6,7,4,0>, <7,4,0,5> - 3937145718U, // <4,0,7,5>: Cost 4 vuzpr <7,4,5,0>, <6,7,4,5> - 3737073145U, // <4,0,7,6>: Cost 4 vext2 <7,6,4,0>, <7,6,4,0> - 3731764844U, // <4,0,7,7>: Cost 4 vext2 <6,7,4,0>, <7,7,7,7> - 4122034332U, // <4,0,7,u>: Cost 4 vtrnl <4,6,7,1>, LHS - 2552856678U, // <4,0,u,0>: Cost 3 vext1 <0,4,0,u>, LHS - 1841635430U, // <4,0,u,1>: Cost 2 vzipl RHS, LHS - 1618166429U, // <4,0,u,2>: Cost 2 vext3 <1,2,3,4>, LHS - 2570774999U, // <4,0,u,3>: Cost 3 vext1 <3,4,0,u>, <3,4,0,u> - 2552859958U, // <4,0,u,4>: Cost 3 vext1 <0,4,0,u>, RHS - 2631481498U, // <4,0,u,5>: Cost 3 vext2 <2,3,4,0>, RHS - 2686157020U, // <4,0,u,6>: Cost 3 vext3 <0,2,6,4>, <0,2,6,4> - 2594665787U, // <4,0,u,7>: Cost 3 vext1 <7,4,0,u>, <7,4,0,u> - 1618166483U, // <4,0,u,u>: Cost 2 vext3 <1,2,3,4>, LHS - 2617548837U, // <4,1,0,0>: Cost 3 vext2 <0,0,4,1>, <0,0,4,1> - 2622857318U, // <4,1,0,1>: Cost 3 vext2 <0,u,4,1>, LHS - 3693281484U, // <4,1,0,2>: Cost 4 vext2 <0,3,4,1>, <0,2,4,6> - 2691908342U, // <4,1,0,3>: Cost 3 vext3 <1,2,3,4>, <1,0,3,2> - 2622857554U, // <4,1,0,4>: Cost 3 vext2 <0,u,4,1>, <0,4,1,5> - 3764470538U, // <4,1,0,5>: Cost 4 vext3 <1,0,5,4>, <1,0,5,4> - 3695272459U, // <4,1,0,6>: Cost 4 vext2 <0,6,4,1>, <0,6,4,1> - 3733094980U, // <4,1,0,7>: Cost 4 vext2 <7,0,4,1>, <0,7,1,4> - 2622857885U, // <4,1,0,u>: Cost 3 vext2 <0,u,4,1>, LHS - 3696599798U, // <4,1,1,0>: Cost 4 vext2 <0,u,4,1>, <1,0,3,2> - 2691097399U, // <4,1,1,1>: Cost 3 vext3 <1,1,1,4>, <1,1,1,4> - 2631484314U, // <4,1,1,2>: Cost 3 vext2 <2,3,4,1>, <1,2,3,4> - 2691908424U, // <4,1,1,3>: Cost 3 vext3 <1,2,3,4>, <1,1,3,3> - 3696600125U, // <4,1,1,4>: Cost 4 vext2 <0,u,4,1>, <1,4,3,5> - 3696600175U, // <4,1,1,5>: Cost 4 vext2 <0,u,4,1>, <1,5,0,1> - 3696600307U, // <4,1,1,6>: Cost 4 vext2 <0,u,4,1>, <1,6,5,7> - 3668423997U, // <4,1,1,7>: Cost 4 vext1 <7,4,1,1>, <7,4,1,1> - 2691908469U, // <4,1,1,u>: Cost 3 vext3 <1,2,3,4>, <1,1,u,3> - 2570797158U, // <4,1,2,0>: Cost 3 vext1 <3,4,1,2>, LHS - 2570797978U, // <4,1,2,1>: Cost 3 vext1 <3,4,1,2>, <1,2,3,4> - 3696600680U, // <4,1,2,2>: Cost 4 vext2 <0,u,4,1>, <2,2,2,2> - 1618166682U, // <4,1,2,3>: Cost 2 vext3 <1,2,3,4>, <1,2,3,4> - 2570800438U, // <4,1,2,4>: Cost 3 vext1 <3,4,1,2>, RHS - 3765650347U, // <4,1,2,5>: Cost 4 vext3 <1,2,3,4>, <1,2,5,3> - 3696601018U, // <4,1,2,6>: Cost 4 vext2 <0,u,4,1>, <2,6,3,7> - 3668432190U, // <4,1,2,7>: Cost 4 vext1 <7,4,1,2>, <7,4,1,2> - 1618535367U, // <4,1,2,u>: Cost 2 vext3 <1,2,u,4>, <1,2,u,4> - 2564833382U, // <4,1,3,0>: Cost 3 vext1 <2,4,1,3>, LHS - 2691908568U, // <4,1,3,1>: Cost 3 vext3 <1,2,3,4>, <1,3,1,3> - 2691908578U, // <4,1,3,2>: Cost 3 vext3 <1,2,3,4>, <1,3,2,4> - 2692572139U, // <4,1,3,3>: Cost 3 vext3 <1,3,3,4>, <1,3,3,4> - 2564836662U, // <4,1,3,4>: Cost 3 vext1 <2,4,1,3>, RHS - 2691908608U, // <4,1,3,5>: Cost 3 vext3 <1,2,3,4>, <1,3,5,7> - 2588725862U, // <4,1,3,6>: Cost 3 vext1 <6,4,1,3>, <6,4,1,3> - 3662468090U, // <4,1,3,7>: Cost 4 vext1 <6,4,1,3>, <7,0,1,2> - 2691908631U, // <4,1,3,u>: Cost 3 vext3 <1,2,3,4>, <1,3,u,3> - 3760194590U, // <4,1,4,0>: Cost 4 vext3 <0,3,1,4>, <1,4,0,1> - 3693947874U, // <4,1,4,1>: Cost 4 vext2 <0,4,4,1>, <4,1,5,0> - 3765650484U, // <4,1,4,2>: Cost 4 vext3 <1,2,3,4>, <1,4,2,5> - 3113877606U, // <4,1,4,3>: Cost 3 vtrnr <4,4,4,4>, LHS - 3760194630U, // <4,1,4,4>: Cost 4 vext3 <0,3,1,4>, <1,4,4,5> - 2622860598U, // <4,1,4,5>: Cost 3 vext2 <0,u,4,1>, RHS - 3297436759U, // <4,1,4,6>: Cost 4 vrev <1,4,6,4> - 3800007772U, // <4,1,4,7>: Cost 4 vext3 <7,0,1,4>, <1,4,7,0> - 2622860841U, // <4,1,4,u>: Cost 3 vext2 <0,u,4,1>, RHS - 1479164006U, // <4,1,5,0>: Cost 2 vext1 <0,4,1,5>, LHS - 2552906486U, // <4,1,5,1>: Cost 3 vext1 <0,4,1,5>, <1,0,3,2> - 2552907299U, // <4,1,5,2>: Cost 3 vext1 <0,4,1,5>, <2,1,3,5> - 2552907926U, // <4,1,5,3>: Cost 3 vext1 <0,4,1,5>, <3,0,1,2> - 1479167286U, // <4,1,5,4>: Cost 2 vext1 <0,4,1,5>, RHS - 2913387664U, // <4,1,5,5>: Cost 3 vzipl RHS, <1,5,3,7> - 2600686074U, // <4,1,5,6>: Cost 3 vext1 , <6,2,7,3> - 2600686586U, // <4,1,5,7>: Cost 3 vext1 , <7,0,1,2> - 1479169838U, // <4,1,5,u>: Cost 2 vext1 <0,4,1,5>, LHS - 2552914022U, // <4,1,6,0>: Cost 3 vext1 <0,4,1,6>, LHS - 2558886708U, // <4,1,6,1>: Cost 3 vext1 <1,4,1,6>, <1,1,1,1> - 4028205206U, // <4,1,6,2>: Cost 4 vzipr <0,2,4,6>, <3,0,1,2> - 3089858662U, // <4,1,6,3>: Cost 3 vtrnr <0,4,2,6>, LHS - 2552917302U, // <4,1,6,4>: Cost 3 vext1 <0,4,1,6>, RHS - 2223637584U, // <4,1,6,5>: Cost 3 vrev <1,4,5,6> - 4121347081U, // <4,1,6,6>: Cost 4 vtrnl RHS, <1,3,6,7> - 3721155406U, // <4,1,6,7>: Cost 4 vext2 <5,0,4,1>, <6,7,0,1> - 2552919854U, // <4,1,6,u>: Cost 3 vext1 <0,4,1,6>, LHS - 2659357716U, // <4,1,7,0>: Cost 3 vext2 <7,0,4,1>, <7,0,4,1> - 3733763173U, // <4,1,7,1>: Cost 4 vext2 <7,1,4,1>, <7,1,4,1> - 3734426806U, // <4,1,7,2>: Cost 4 vext2 <7,2,4,1>, <7,2,4,1> - 2695226671U, // <4,1,7,3>: Cost 3 vext3 <1,7,3,4>, <1,7,3,4> - 3721155942U, // <4,1,7,4>: Cost 4 vext2 <5,0,4,1>, <7,4,5,6> - 3721155976U, // <4,1,7,5>: Cost 4 vext2 <5,0,4,1>, <7,5,0,4> - 3662500458U, // <4,1,7,6>: Cost 4 vext1 <6,4,1,7>, <6,4,1,7> - 3721156204U, // <4,1,7,7>: Cost 4 vext2 <5,0,4,1>, <7,7,7,7> - 2659357716U, // <4,1,7,u>: Cost 3 vext2 <7,0,4,1>, <7,0,4,1> - 1479188582U, // <4,1,u,0>: Cost 2 vext1 <0,4,1,u>, LHS - 2552931062U, // <4,1,u,1>: Cost 3 vext1 <0,4,1,u>, <1,0,3,2> - 2552931944U, // <4,1,u,2>: Cost 3 vext1 <0,4,1,u>, <2,2,2,2> - 1622148480U, // <4,1,u,3>: Cost 2 vext3 <1,u,3,4>, <1,u,3,4> - 1479191862U, // <4,1,u,4>: Cost 2 vext1 <0,4,1,u>, RHS - 2622863514U, // <4,1,u,5>: Cost 3 vext2 <0,u,4,1>, RHS - 2588725862U, // <4,1,u,6>: Cost 3 vext1 <6,4,1,3>, <6,4,1,3> - 2600686586U, // <4,1,u,7>: Cost 3 vext1 , <7,0,1,2> - 1479194414U, // <4,1,u,u>: Cost 2 vext1 <0,4,1,u>, LHS - 2617557030U, // <4,2,0,0>: Cost 3 vext2 <0,0,4,2>, <0,0,4,2> - 2622865510U, // <4,2,0,1>: Cost 3 vext2 <0,u,4,2>, LHS - 2622865612U, // <4,2,0,2>: Cost 3 vext2 <0,u,4,2>, <0,2,4,6> - 3693289753U, // <4,2,0,3>: Cost 4 vext2 <0,3,4,2>, <0,3,4,2> - 2635473244U, // <4,2,0,4>: Cost 3 vext2 <3,0,4,2>, <0,4,2,6> - 3765650918U, // <4,2,0,5>: Cost 4 vext3 <1,2,3,4>, <2,0,5,7> - 2696775148U, // <4,2,0,6>: Cost 3 vext3 <2,0,6,4>, <2,0,6,4> - 3695944285U, // <4,2,0,7>: Cost 4 vext2 <0,7,4,2>, <0,7,4,2> - 2622866077U, // <4,2,0,u>: Cost 3 vext2 <0,u,4,2>, LHS - 3696607990U, // <4,2,1,0>: Cost 4 vext2 <0,u,4,2>, <1,0,3,2> - 3696608052U, // <4,2,1,1>: Cost 4 vext2 <0,u,4,2>, <1,1,1,1> - 3696608150U, // <4,2,1,2>: Cost 4 vext2 <0,u,4,2>, <1,2,3,0> - 3895574630U, // <4,2,1,3>: Cost 4 vuzpr <0,4,u,2>, LHS - 2691909162U, // <4,2,1,4>: Cost 3 vext3 <1,2,3,4>, <2,1,4,3> - 3696608400U, // <4,2,1,5>: Cost 4 vext2 <0,u,4,2>, <1,5,3,7> - 3760784956U, // <4,2,1,6>: Cost 4 vext3 <0,4,0,4>, <2,1,6,3> - 3773908549U, // <4,2,1,7>: Cost 5 vext3 <2,5,7,4>, <2,1,7,3> - 2691909162U, // <4,2,1,u>: Cost 3 vext3 <1,2,3,4>, <2,1,4,3> - 3696608748U, // <4,2,2,0>: Cost 4 vext2 <0,u,4,2>, <2,0,6,4> - 3696608828U, // <4,2,2,1>: Cost 4 vext2 <0,u,4,2>, <2,1,6,3> - 2691909224U, // <4,2,2,2>: Cost 3 vext3 <1,2,3,4>, <2,2,2,2> - 2691909234U, // <4,2,2,3>: Cost 3 vext3 <1,2,3,4>, <2,2,3,3> - 3759605368U, // <4,2,2,4>: Cost 4 vext3 <0,2,2,4>, <2,2,4,0> - 3696609156U, // <4,2,2,5>: Cost 4 vext2 <0,u,4,2>, <2,5,6,7> - 3760785040U, // <4,2,2,6>: Cost 4 vext3 <0,4,0,4>, <2,2,6,6> - 3668505927U, // <4,2,2,7>: Cost 4 vext1 <7,4,2,2>, <7,4,2,2> - 2691909279U, // <4,2,2,u>: Cost 3 vext3 <1,2,3,4>, <2,2,u,3> - 2691909286U, // <4,2,3,0>: Cost 3 vext3 <1,2,3,4>, <2,3,0,1> - 3764840111U, // <4,2,3,1>: Cost 4 vext3 <1,1,1,4>, <2,3,1,1> - 3765651129U, // <4,2,3,2>: Cost 4 vext3 <1,2,3,4>, <2,3,2,2> - 2698544836U, // <4,2,3,3>: Cost 3 vext3 <2,3,3,4>, <2,3,3,4> - 2685863630U, // <4,2,3,4>: Cost 3 vext3 <0,2,2,4>, <2,3,4,5> - 2698692310U, // <4,2,3,5>: Cost 3 vext3 <2,3,5,4>, <2,3,5,4> - 3772507871U, // <4,2,3,6>: Cost 4 vext3 <2,3,6,4>, <2,3,6,4> - 2698839784U, // <4,2,3,7>: Cost 3 vext3 <2,3,7,4>, <2,3,7,4> - 2691909358U, // <4,2,3,u>: Cost 3 vext3 <1,2,3,4>, <2,3,u,1> - 2564915302U, // <4,2,4,0>: Cost 3 vext1 <2,4,2,4>, LHS - 2564916122U, // <4,2,4,1>: Cost 3 vext1 <2,4,2,4>, <1,2,3,4> - 2564917004U, // <4,2,4,2>: Cost 3 vext1 <2,4,2,4>, <2,4,2,4> - 2699208469U, // <4,2,4,3>: Cost 3 vext3 <2,4,3,4>, <2,4,3,4> - 2564918582U, // <4,2,4,4>: Cost 3 vext1 <2,4,2,4>, RHS - 2622868790U, // <4,2,4,5>: Cost 3 vext2 <0,u,4,2>, RHS - 2229667632U, // <4,2,4,6>: Cost 3 vrev <2,4,6,4> - 3800082229U, // <4,2,4,7>: Cost 4 vext3 <7,0,2,4>, <2,4,7,0> - 2622869033U, // <4,2,4,u>: Cost 3 vext2 <0,u,4,2>, RHS - 2552979558U, // <4,2,5,0>: Cost 3 vext1 <0,4,2,5>, LHS - 2558952342U, // <4,2,5,1>: Cost 3 vext1 <1,4,2,5>, <1,2,3,0> - 2564925032U, // <4,2,5,2>: Cost 3 vext1 <2,4,2,5>, <2,2,2,2> - 2967060582U, // <4,2,5,3>: Cost 3 vzipr <2,3,4,5>, LHS - 2552982838U, // <4,2,5,4>: Cost 3 vext1 <0,4,2,5>, RHS - 3987130190U, // <4,2,5,5>: Cost 4 vzipl RHS, <2,5,0,7> - 2913388474U, // <4,2,5,6>: Cost 3 vzipl RHS, <2,6,3,7> - 3895577910U, // <4,2,5,7>: Cost 4 vuzpr <0,4,u,2>, RHS - 2552985390U, // <4,2,5,u>: Cost 3 vext1 <0,4,2,5>, LHS - 1479245926U, // <4,2,6,0>: Cost 2 vext1 <0,4,2,6>, LHS - 2552988406U, // <4,2,6,1>: Cost 3 vext1 <0,4,2,6>, <1,0,3,2> - 2552989288U, // <4,2,6,2>: Cost 3 vext1 <0,4,2,6>, <2,2,2,2> - 2954461286U, // <4,2,6,3>: Cost 3 vzipr <0,2,4,6>, LHS - 1479249206U, // <4,2,6,4>: Cost 2 vext1 <0,4,2,6>, RHS - 2229610281U, // <4,2,6,5>: Cost 3 vrev <2,4,5,6> - 2600767994U, // <4,2,6,6>: Cost 3 vext1 , <6,2,7,3> - 2600768506U, // <4,2,6,7>: Cost 3 vext1 , <7,0,1,2> - 1479251758U, // <4,2,6,u>: Cost 2 vext1 <0,4,2,6>, LHS - 2659365909U, // <4,2,7,0>: Cost 3 vext2 <7,0,4,2>, <7,0,4,2> - 3733771366U, // <4,2,7,1>: Cost 4 vext2 <7,1,4,2>, <7,1,4,2> - 3734434999U, // <4,2,7,2>: Cost 4 vext2 <7,2,4,2>, <7,2,4,2> - 2701199368U, // <4,2,7,3>: Cost 3 vext3 <2,7,3,4>, <2,7,3,4> - 4175774618U, // <4,2,7,4>: Cost 4 vtrnr <2,4,5,7>, <1,2,3,4> - 3303360298U, // <4,2,7,5>: Cost 4 vrev <2,4,5,7> - 3727136217U, // <4,2,7,6>: Cost 4 vext2 <6,0,4,2>, <7,6,0,4> - 3727136364U, // <4,2,7,7>: Cost 4 vext2 <6,0,4,2>, <7,7,7,7> - 2659365909U, // <4,2,7,u>: Cost 3 vext2 <7,0,4,2>, <7,0,4,2> - 1479262310U, // <4,2,u,0>: Cost 2 vext1 <0,4,2,u>, LHS - 2553004790U, // <4,2,u,1>: Cost 3 vext1 <0,4,2,u>, <1,0,3,2> - 2553005672U, // <4,2,u,2>: Cost 3 vext1 <0,4,2,u>, <2,2,2,2> - 2954477670U, // <4,2,u,3>: Cost 3 vzipr <0,2,4,u>, LHS - 1479265590U, // <4,2,u,4>: Cost 2 vext1 <0,4,2,u>, RHS - 2622871706U, // <4,2,u,5>: Cost 3 vext2 <0,u,4,2>, RHS - 2229700404U, // <4,2,u,6>: Cost 3 vrev <2,4,6,u> - 2600784890U, // <4,2,u,7>: Cost 3 vext1 , <7,0,1,2> - 1479268142U, // <4,2,u,u>: Cost 2 vext1 <0,4,2,u>, LHS - 3765651595U, // <4,3,0,0>: Cost 4 vext3 <1,2,3,4>, <3,0,0,0> - 2691909782U, // <4,3,0,1>: Cost 3 vext3 <1,2,3,4>, <3,0,1,2> - 2702452897U, // <4,3,0,2>: Cost 3 vext3 <3,0,2,4>, <3,0,2,4> - 3693297946U, // <4,3,0,3>: Cost 4 vext2 <0,3,4,3>, <0,3,4,3> - 3760711856U, // <4,3,0,4>: Cost 4 vext3 <0,3,u,4>, <3,0,4,1> - 2235533820U, // <4,3,0,5>: Cost 3 vrev <3,4,5,0> - 3309349381U, // <4,3,0,6>: Cost 4 vrev <3,4,6,0> - 3668563278U, // <4,3,0,7>: Cost 4 vext1 <7,4,3,0>, <7,4,3,0> - 2691909845U, // <4,3,0,u>: Cost 3 vext3 <1,2,3,4>, <3,0,u,2> - 2235173328U, // <4,3,1,0>: Cost 3 vrev <3,4,0,1> - 3764840678U, // <4,3,1,1>: Cost 4 vext3 <1,1,1,4>, <3,1,1,1> - 2630173594U, // <4,3,1,2>: Cost 3 vext2 <2,1,4,3>, <1,2,3,4> - 2703190267U, // <4,3,1,3>: Cost 3 vext3 <3,1,3,4>, <3,1,3,4> - 3760195840U, // <4,3,1,4>: Cost 4 vext3 <0,3,1,4>, <3,1,4,0> - 3765651724U, // <4,3,1,5>: Cost 4 vext3 <1,2,3,4>, <3,1,5,3> - 3309357574U, // <4,3,1,6>: Cost 4 vrev <3,4,6,1> - 3769633054U, // <4,3,1,7>: Cost 4 vext3 <1,u,3,4>, <3,1,7,3> - 2703558952U, // <4,3,1,u>: Cost 3 vext3 <3,1,u,4>, <3,1,u,4> - 3626770534U, // <4,3,2,0>: Cost 4 vext1 <0,4,3,2>, LHS - 2630174250U, // <4,3,2,1>: Cost 3 vext2 <2,1,4,3>, <2,1,4,3> - 3765651777U, // <4,3,2,2>: Cost 4 vext3 <1,2,3,4>, <3,2,2,2> - 2703853900U, // <4,3,2,3>: Cost 3 vext3 <3,2,3,4>, <3,2,3,4> - 3626773814U, // <4,3,2,4>: Cost 4 vext1 <0,4,3,2>, RHS - 2704001374U, // <4,3,2,5>: Cost 3 vext3 <3,2,5,4>, <3,2,5,4> - 3765651814U, // <4,3,2,6>: Cost 4 vext3 <1,2,3,4>, <3,2,6,3> - 3769633135U, // <4,3,2,7>: Cost 4 vext3 <1,u,3,4>, <3,2,7,3> - 2634819681U, // <4,3,2,u>: Cost 3 vext2 <2,u,4,3>, <2,u,4,3> - 3765651839U, // <4,3,3,0>: Cost 4 vext3 <1,2,3,4>, <3,3,0,1> - 3765651848U, // <4,3,3,1>: Cost 4 vext3 <1,2,3,4>, <3,3,1,1> - 3710552404U, // <4,3,3,2>: Cost 4 vext2 <3,2,4,3>, <3,2,4,3> - 2691910044U, // <4,3,3,3>: Cost 3 vext3 <1,2,3,4>, <3,3,3,3> - 2704591270U, // <4,3,3,4>: Cost 3 vext3 <3,3,4,4>, <3,3,4,4> - 3769633202U, // <4,3,3,5>: Cost 4 vext3 <1,u,3,4>, <3,3,5,7> - 3703917212U, // <4,3,3,6>: Cost 4 vext2 <2,1,4,3>, <3,6,4,7> - 3769633220U, // <4,3,3,7>: Cost 4 vext3 <1,u,3,4>, <3,3,7,7> - 2691910044U, // <4,3,3,u>: Cost 3 vext3 <1,2,3,4>, <3,3,3,3> - 2691910096U, // <4,3,4,0>: Cost 3 vext3 <1,2,3,4>, <3,4,0,1> - 2691910106U, // <4,3,4,1>: Cost 3 vext3 <1,2,3,4>, <3,4,1,2> - 2564990741U, // <4,3,4,2>: Cost 3 vext1 <2,4,3,4>, <2,4,3,4> - 3765651946U, // <4,3,4,3>: Cost 4 vext3 <1,2,3,4>, <3,4,3,0> - 2691910136U, // <4,3,4,4>: Cost 3 vext3 <1,2,3,4>, <3,4,4,5> - 2686454274U, // <4,3,4,5>: Cost 3 vext3 <0,3,1,4>, <3,4,5,6> - 2235640329U, // <4,3,4,6>: Cost 3 vrev <3,4,6,4> - 3801483792U, // <4,3,4,7>: Cost 4 vext3 <7,2,3,4>, <3,4,7,2> - 2691910168U, // <4,3,4,u>: Cost 3 vext3 <1,2,3,4>, <3,4,u,1> - 2559025254U, // <4,3,5,0>: Cost 3 vext1 <1,4,3,5>, LHS - 2559026237U, // <4,3,5,1>: Cost 3 vext1 <1,4,3,5>, <1,4,3,5> - 2564998862U, // <4,3,5,2>: Cost 3 vext1 <2,4,3,5>, <2,3,4,5> - 2570971548U, // <4,3,5,3>: Cost 3 vext1 <3,4,3,5>, <3,3,3,3> - 2559028534U, // <4,3,5,4>: Cost 3 vext1 <1,4,3,5>, RHS - 4163519477U, // <4,3,5,5>: Cost 4 vtrnr <0,4,1,5>, <1,3,4,5> - 3309390346U, // <4,3,5,6>: Cost 4 vrev <3,4,6,5> - 2706139747U, // <4,3,5,7>: Cost 3 vext3 <3,5,7,4>, <3,5,7,4> - 2559031086U, // <4,3,5,u>: Cost 3 vext1 <1,4,3,5>, LHS - 2559033446U, // <4,3,6,0>: Cost 3 vext1 <1,4,3,6>, LHS - 2559034430U, // <4,3,6,1>: Cost 3 vext1 <1,4,3,6>, <1,4,3,6> - 2565007127U, // <4,3,6,2>: Cost 3 vext1 <2,4,3,6>, <2,4,3,6> - 2570979740U, // <4,3,6,3>: Cost 3 vext1 <3,4,3,6>, <3,3,3,3> - 2559036726U, // <4,3,6,4>: Cost 3 vext1 <1,4,3,6>, RHS - 1161841154U, // <4,3,6,5>: Cost 2 vrev <3,4,5,6> - 4028203932U, // <4,3,6,6>: Cost 4 vzipr <0,2,4,6>, <1,2,3,6> - 2706803380U, // <4,3,6,7>: Cost 3 vext3 <3,6,7,4>, <3,6,7,4> - 1162062365U, // <4,3,6,u>: Cost 2 vrev <3,4,u,6> - 3769633475U, // <4,3,7,0>: Cost 4 vext3 <1,u,3,4>, <3,7,0,1> - 3769633488U, // <4,3,7,1>: Cost 4 vext3 <1,u,3,4>, <3,7,1,5> - 3638757144U, // <4,3,7,2>: Cost 4 vext1 <2,4,3,7>, <2,4,3,7> - 3769633508U, // <4,3,7,3>: Cost 4 vext3 <1,u,3,4>, <3,7,3,7> - 3769633515U, // <4,3,7,4>: Cost 4 vext3 <1,u,3,4>, <3,7,4,5> - 3769633526U, // <4,3,7,5>: Cost 4 vext3 <1,u,3,4>, <3,7,5,7> - 3662647932U, // <4,3,7,6>: Cost 4 vext1 <6,4,3,7>, <6,4,3,7> - 3781208837U, // <4,3,7,7>: Cost 4 vext3 <3,7,7,4>, <3,7,7,4> - 3769633547U, // <4,3,7,u>: Cost 4 vext3 <1,u,3,4>, <3,7,u,1> - 2559049830U, // <4,3,u,0>: Cost 3 vext1 <1,4,3,u>, LHS - 2691910430U, // <4,3,u,1>: Cost 3 vext3 <1,2,3,4>, <3,u,1,2> - 2565023513U, // <4,3,u,2>: Cost 3 vext1 <2,4,3,u>, <2,4,3,u> - 2707835698U, // <4,3,u,3>: Cost 3 vext3 <3,u,3,4>, <3,u,3,4> - 2559053110U, // <4,3,u,4>: Cost 3 vext1 <1,4,3,u>, RHS - 1161857540U, // <4,3,u,5>: Cost 2 vrev <3,4,5,u> - 2235673101U, // <4,3,u,6>: Cost 3 vrev <3,4,6,u> - 2708130646U, // <4,3,u,7>: Cost 3 vext3 <3,u,7,4>, <3,u,7,4> - 1162078751U, // <4,3,u,u>: Cost 2 vrev <3,4,u,u> - 2617573416U, // <4,4,0,0>: Cost 3 vext2 <0,0,4,4>, <0,0,4,4> - 1570373734U, // <4,4,0,1>: Cost 2 vext2 <4,4,4,4>, LHS - 2779676774U, // <4,4,0,2>: Cost 3 vuzpl <4,6,4,6>, LHS - 3760196480U, // <4,4,0,3>: Cost 4 vext3 <0,3,1,4>, <4,0,3,1> - 2576977100U, // <4,4,0,4>: Cost 3 vext1 <4,4,4,0>, <4,4,4,0> - 2718747538U, // <4,4,0,5>: Cost 3 vext3 <5,6,7,4>, <4,0,5,1> - 2718747548U, // <4,4,0,6>: Cost 3 vext3 <5,6,7,4>, <4,0,6,2> - 3668637015U, // <4,4,0,7>: Cost 4 vext1 <7,4,4,0>, <7,4,4,0> - 1570374301U, // <4,4,0,u>: Cost 2 vext2 <4,4,4,4>, LHS - 2644116214U, // <4,4,1,0>: Cost 3 vext2 <4,4,4,4>, <1,0,3,2> - 2644116276U, // <4,4,1,1>: Cost 3 vext2 <4,4,4,4>, <1,1,1,1> - 2691910602U, // <4,4,1,2>: Cost 3 vext3 <1,2,3,4>, <4,1,2,3> - 2644116440U, // <4,4,1,3>: Cost 3 vext2 <4,4,4,4>, <1,3,1,3> - 2711227356U, // <4,4,1,4>: Cost 3 vext3 <4,4,4,4>, <4,1,4,3> - 2709310438U, // <4,4,1,5>: Cost 3 vext3 <4,1,5,4>, <4,1,5,4> - 3765652462U, // <4,4,1,6>: Cost 4 vext3 <1,2,3,4>, <4,1,6,3> - 3768970231U, // <4,4,1,7>: Cost 4 vext3 <1,7,3,4>, <4,1,7,3> - 2695891968U, // <4,4,1,u>: Cost 3 vext3 <1,u,3,4>, <4,1,u,3> - 3703260634U, // <4,4,2,0>: Cost 4 vext2 <2,0,4,4>, <2,0,4,4> - 3765652499U, // <4,4,2,1>: Cost 4 vext3 <1,2,3,4>, <4,2,1,4> - 2644117096U, // <4,4,2,2>: Cost 3 vext2 <4,4,4,4>, <2,2,2,2> - 2631509709U, // <4,4,2,3>: Cost 3 vext2 <2,3,4,4>, <2,3,4,4> - 2644117269U, // <4,4,2,4>: Cost 3 vext2 <4,4,4,4>, <2,4,3,4> - 3705251698U, // <4,4,2,5>: Cost 4 vext2 <2,3,4,4>, <2,5,4,7> - 2710047808U, // <4,4,2,6>: Cost 3 vext3 <4,2,6,4>, <4,2,6,4> - 3783863369U, // <4,4,2,7>: Cost 4 vext3 <4,2,7,4>, <4,2,7,4> - 2634827874U, // <4,4,2,u>: Cost 3 vext2 <2,u,4,4>, <2,u,4,4> - 2644117654U, // <4,4,3,0>: Cost 3 vext2 <4,4,4,4>, <3,0,1,2> - 3638797210U, // <4,4,3,1>: Cost 4 vext1 <2,4,4,3>, <1,2,3,4> - 3638798082U, // <4,4,3,2>: Cost 4 vext1 <2,4,4,3>, <2,4,1,3> - 2637482406U, // <4,4,3,3>: Cost 3 vext2 <3,3,4,4>, <3,3,4,4> - 2638146039U, // <4,4,3,4>: Cost 3 vext2 <3,4,4,4>, <3,4,4,4> - 3913287374U, // <4,4,3,5>: Cost 4 vuzpr <3,4,5,4>, <2,3,4,5> - 3765652625U, // <4,4,3,6>: Cost 4 vext3 <1,2,3,4>, <4,3,6,4> - 3713878762U, // <4,4,3,7>: Cost 4 vext2 <3,7,4,4>, <3,7,4,4> - 2637482406U, // <4,4,3,u>: Cost 3 vext2 <3,3,4,4>, <3,3,4,4> - 1503264870U, // <4,4,4,0>: Cost 2 vext1 <4,4,4,4>, LHS - 2577007514U, // <4,4,4,1>: Cost 3 vext1 <4,4,4,4>, <1,2,3,4> - 2577008232U, // <4,4,4,2>: Cost 3 vext1 <4,4,4,4>, <2,2,2,2> - 2571037175U, // <4,4,4,3>: Cost 3 vext1 <3,4,4,4>, <3,4,4,4> - 161926454U, // <4,4,4,4>: Cost 1 vdup0 RHS - 1570377014U, // <4,4,4,5>: Cost 2 vext2 <4,4,4,4>, RHS - 2779680054U, // <4,4,4,6>: Cost 3 vuzpl <4,6,4,6>, RHS - 2594927963U, // <4,4,4,7>: Cost 3 vext1 <7,4,4,4>, <7,4,4,4> - 161926454U, // <4,4,4,u>: Cost 1 vdup0 RHS - 2571042918U, // <4,4,5,0>: Cost 3 vext1 <3,4,4,5>, LHS - 2571043738U, // <4,4,5,1>: Cost 3 vext1 <3,4,4,5>, <1,2,3,4> - 3638814495U, // <4,4,5,2>: Cost 4 vext1 <2,4,4,5>, <2,4,4,5> - 2571045368U, // <4,4,5,3>: Cost 3 vext1 <3,4,4,5>, <3,4,4,5> - 2571046198U, // <4,4,5,4>: Cost 3 vext1 <3,4,4,5>, RHS - 1839648054U, // <4,4,5,5>: Cost 2 vzipl RHS, RHS - 1618169142U, // <4,4,5,6>: Cost 2 vext3 <1,2,3,4>, RHS - 2594936156U, // <4,4,5,7>: Cost 3 vext1 <7,4,4,5>, <7,4,4,5> - 1618169160U, // <4,4,5,u>: Cost 2 vext3 <1,2,3,4>, RHS - 2553135206U, // <4,4,6,0>: Cost 3 vext1 <0,4,4,6>, LHS - 3626877686U, // <4,4,6,1>: Cost 4 vext1 <0,4,4,6>, <1,0,3,2> - 2565080782U, // <4,4,6,2>: Cost 3 vext1 <2,4,4,6>, <2,3,4,5> - 2571053561U, // <4,4,6,3>: Cost 3 vext1 <3,4,4,6>, <3,4,4,6> - 2553138486U, // <4,4,6,4>: Cost 3 vext1 <0,4,4,6>, RHS - 2241555675U, // <4,4,6,5>: Cost 3 vrev <4,4,5,6> - 1973865782U, // <4,4,6,6>: Cost 2 vtrnl RHS, RHS - 2658055029U, // <4,4,6,7>: Cost 3 vext2 <6,7,4,4>, <6,7,4,4> - 1973865800U, // <4,4,6,u>: Cost 2 vtrnl RHS, RHS - 2644120570U, // <4,4,7,0>: Cost 3 vext2 <4,4,4,4>, <7,0,1,2> - 3638829978U, // <4,4,7,1>: Cost 4 vext1 <2,4,4,7>, <1,2,3,4> - 3638830881U, // <4,4,7,2>: Cost 4 vext1 <2,4,4,7>, <2,4,4,7> - 3735115018U, // <4,4,7,3>: Cost 4 vext2 <7,3,4,4>, <7,3,4,4> - 2662036827U, // <4,4,7,4>: Cost 3 vext2 <7,4,4,4>, <7,4,4,4> - 2713292236U, // <4,4,7,5>: Cost 3 vext3 <4,7,5,4>, <4,7,5,4> - 2713365973U, // <4,4,7,6>: Cost 3 vext3 <4,7,6,4>, <4,7,6,4> - 2644121196U, // <4,4,7,7>: Cost 3 vext2 <4,4,4,4>, <7,7,7,7> - 2662036827U, // <4,4,7,u>: Cost 3 vext2 <7,4,4,4>, <7,4,4,4> - 1503297638U, // <4,4,u,0>: Cost 2 vext1 <4,4,4,u>, LHS - 1570379566U, // <4,4,u,1>: Cost 2 vext2 <4,4,4,4>, LHS - 2779682606U, // <4,4,u,2>: Cost 3 vuzpl <4,6,4,6>, LHS - 2571069947U, // <4,4,u,3>: Cost 3 vext1 <3,4,4,u>, <3,4,4,u> - 161926454U, // <4,4,u,4>: Cost 1 vdup0 RHS - 1841638710U, // <4,4,u,5>: Cost 2 vzipl RHS, RHS - 1618169385U, // <4,4,u,6>: Cost 2 vext3 <1,2,3,4>, RHS - 2594960735U, // <4,4,u,7>: Cost 3 vext1 <7,4,4,u>, <7,4,4,u> - 161926454U, // <4,4,u,u>: Cost 1 vdup0 RHS - 2631516160U, // <4,5,0,0>: Cost 3 vext2 <2,3,4,5>, <0,0,0,0> - 1557774438U, // <4,5,0,1>: Cost 2 vext2 <2,3,4,5>, LHS - 2618908875U, // <4,5,0,2>: Cost 3 vext2 <0,2,4,5>, <0,2,4,5> - 2571078140U, // <4,5,0,3>: Cost 3 vext1 <3,4,5,0>, <3,4,5,0> - 2626871634U, // <4,5,0,4>: Cost 3 vext2 <1,5,4,5>, <0,4,1,5> - 3705258414U, // <4,5,0,5>: Cost 4 vext2 <2,3,4,5>, <0,5,2,7> - 2594968438U, // <4,5,0,6>: Cost 3 vext1 <7,4,5,0>, <6,7,4,5> - 2594968928U, // <4,5,0,7>: Cost 3 vext1 <7,4,5,0>, <7,4,5,0> - 1557775005U, // <4,5,0,u>: Cost 2 vext2 <2,3,4,5>, LHS - 2631516918U, // <4,5,1,0>: Cost 3 vext2 <2,3,4,5>, <1,0,3,2> - 2624217939U, // <4,5,1,1>: Cost 3 vext2 <1,1,4,5>, <1,1,4,5> - 2631517078U, // <4,5,1,2>: Cost 3 vext2 <2,3,4,5>, <1,2,3,0> - 2821341286U, // <4,5,1,3>: Cost 3 vuzpr <0,4,1,5>, LHS - 3895086054U, // <4,5,1,4>: Cost 4 vuzpr <0,4,1,5>, <4,1,5,4> - 2626872471U, // <4,5,1,5>: Cost 3 vext2 <1,5,4,5>, <1,5,4,5> - 3895083131U, // <4,5,1,6>: Cost 4 vuzpr <0,4,1,5>, <0,1,4,6> - 2718748368U, // <4,5,1,7>: Cost 3 vext3 <5,6,7,4>, <5,1,7,3> - 2821341291U, // <4,5,1,u>: Cost 3 vuzpr <0,4,1,5>, LHS - 2571092070U, // <4,5,2,0>: Cost 3 vext1 <3,4,5,2>, LHS - 3699287585U, // <4,5,2,1>: Cost 4 vext2 <1,3,4,5>, <2,1,3,3> - 2630854269U, // <4,5,2,2>: Cost 3 vext2 <2,2,4,5>, <2,2,4,5> - 1557776078U, // <4,5,2,3>: Cost 2 vext2 <2,3,4,5>, <2,3,4,5> - 2631517974U, // <4,5,2,4>: Cost 3 vext2 <2,3,4,5>, <2,4,3,5> - 3692652384U, // <4,5,2,5>: Cost 4 vext2 <0,2,4,5>, <2,5,2,7> - 2631518138U, // <4,5,2,6>: Cost 3 vext2 <2,3,4,5>, <2,6,3,7> - 4164013366U, // <4,5,2,7>: Cost 4 vtrnr <0,4,u,2>, RHS - 1561094243U, // <4,5,2,u>: Cost 2 vext2 <2,u,4,5>, <2,u,4,5> - 2631518358U, // <4,5,3,0>: Cost 3 vext2 <2,3,4,5>, <3,0,1,2> - 3895084710U, // <4,5,3,1>: Cost 4 vuzpr <0,4,1,5>, <2,3,0,1> - 2631518540U, // <4,5,3,2>: Cost 3 vext2 <2,3,4,5>, <3,2,3,4> - 2631518620U, // <4,5,3,3>: Cost 3 vext2 <2,3,4,5>, <3,3,3,3> - 2631518716U, // <4,5,3,4>: Cost 3 vext2 <2,3,4,5>, <3,4,5,0> - 2631518784U, // <4,5,3,5>: Cost 3 vext2 <2,3,4,5>, <3,5,3,5> - 2658060980U, // <4,5,3,6>: Cost 3 vext2 <6,7,4,5>, <3,6,7,4> - 2640145131U, // <4,5,3,7>: Cost 3 vext2 <3,7,4,5>, <3,7,4,5> - 2631519006U, // <4,5,3,u>: Cost 3 vext2 <2,3,4,5>, <3,u,1,2> - 2571108454U, // <4,5,4,0>: Cost 3 vext1 <3,4,5,4>, LHS - 3632907342U, // <4,5,4,1>: Cost 4 vext1 <1,4,5,4>, <1,4,5,4> - 2571110094U, // <4,5,4,2>: Cost 3 vext1 <3,4,5,4>, <2,3,4,5> - 2571110912U, // <4,5,4,3>: Cost 3 vext1 <3,4,5,4>, <3,4,5,4> - 2571111734U, // <4,5,4,4>: Cost 3 vext1 <3,4,5,4>, RHS - 1557777718U, // <4,5,4,5>: Cost 2 vext2 <2,3,4,5>, RHS - 2645454195U, // <4,5,4,6>: Cost 3 vext2 <4,6,4,5>, <4,6,4,5> - 2718748614U, // <4,5,4,7>: Cost 3 vext3 <5,6,7,4>, <5,4,7,6> - 1557777961U, // <4,5,4,u>: Cost 2 vext2 <2,3,4,5>, RHS - 1503346790U, // <4,5,5,0>: Cost 2 vext1 <4,4,5,5>, LHS - 2913398480U, // <4,5,5,1>: Cost 3 vzipl RHS, <5,1,7,3> - 2631519998U, // <4,5,5,2>: Cost 3 vext2 <2,3,4,5>, <5,2,3,4> - 2577090710U, // <4,5,5,3>: Cost 3 vext1 <4,4,5,5>, <3,0,1,2> - 1503349978U, // <4,5,5,4>: Cost 2 vext1 <4,4,5,5>, <4,4,5,5> - 2631520260U, // <4,5,5,5>: Cost 3 vext2 <2,3,4,5>, <5,5,5,5> - 2913390690U, // <4,5,5,6>: Cost 3 vzipl RHS, <5,6,7,0> - 2821344566U, // <4,5,5,7>: Cost 3 vuzpr <0,4,1,5>, RHS - 1503352622U, // <4,5,5,u>: Cost 2 vext1 <4,4,5,5>, LHS - 1497383014U, // <4,5,6,0>: Cost 2 vext1 <3,4,5,6>, LHS - 2559181904U, // <4,5,6,1>: Cost 3 vext1 <1,4,5,6>, <1,4,5,6> - 2565154601U, // <4,5,6,2>: Cost 3 vext1 <2,4,5,6>, <2,4,5,6> - 1497385474U, // <4,5,6,3>: Cost 2 vext1 <3,4,5,6>, <3,4,5,6> - 1497386294U, // <4,5,6,4>: Cost 2 vext1 <3,4,5,6>, RHS - 3047608324U, // <4,5,6,5>: Cost 3 vtrnl RHS, <5,5,5,5> - 2571129656U, // <4,5,6,6>: Cost 3 vext1 <3,4,5,6>, <6,6,6,6> - 27705344U, // <4,5,6,7>: Cost 0 copy RHS - 27705344U, // <4,5,6,u>: Cost 0 copy RHS - 2565161062U, // <4,5,7,0>: Cost 3 vext1 <2,4,5,7>, LHS - 2565161882U, // <4,5,7,1>: Cost 3 vext1 <2,4,5,7>, <1,2,3,4> - 2565162794U, // <4,5,7,2>: Cost 3 vext1 <2,4,5,7>, <2,4,5,7> - 2661381387U, // <4,5,7,3>: Cost 3 vext2 <7,3,4,5>, <7,3,4,5> - 2565164342U, // <4,5,7,4>: Cost 3 vext1 <2,4,5,7>, RHS - 2718748840U, // <4,5,7,5>: Cost 3 vext3 <5,6,7,4>, <5,7,5,7> - 2718748846U, // <4,5,7,6>: Cost 3 vext3 <5,6,7,4>, <5,7,6,4> - 2719412407U, // <4,5,7,7>: Cost 3 vext3 <5,7,7,4>, <5,7,7,4> - 2565166894U, // <4,5,7,u>: Cost 3 vext1 <2,4,5,7>, LHS - 1497399398U, // <4,5,u,0>: Cost 2 vext1 <3,4,5,u>, LHS - 1557780270U, // <4,5,u,1>: Cost 2 vext2 <2,3,4,5>, LHS - 2631522181U, // <4,5,u,2>: Cost 3 vext2 <2,3,4,5>, - 1497401860U, // <4,5,u,3>: Cost 2 vext1 <3,4,5,u>, <3,4,5,u> - 1497402678U, // <4,5,u,4>: Cost 2 vext1 <3,4,5,u>, RHS - 1557780634U, // <4,5,u,5>: Cost 2 vext2 <2,3,4,5>, RHS - 2631522512U, // <4,5,u,6>: Cost 3 vext2 <2,3,4,5>, - 27705344U, // <4,5,u,7>: Cost 0 copy RHS - 27705344U, // <4,5,u,u>: Cost 0 copy RHS - 2618916864U, // <4,6,0,0>: Cost 3 vext2 <0,2,4,6>, <0,0,0,0> - 1545175142U, // <4,6,0,1>: Cost 2 vext2 <0,2,4,6>, LHS - 1545175244U, // <4,6,0,2>: Cost 2 vext2 <0,2,4,6>, <0,2,4,6> - 3692658940U, // <4,6,0,3>: Cost 4 vext2 <0,2,4,6>, <0,3,1,0> - 2618917202U, // <4,6,0,4>: Cost 3 vext2 <0,2,4,6>, <0,4,1,5> - 3852910806U, // <4,6,0,5>: Cost 4 vuzpl RHS, <0,2,5,7> - 2253525648U, // <4,6,0,6>: Cost 3 vrev <6,4,6,0> - 4040764726U, // <4,6,0,7>: Cost 4 vzipr <2,3,4,0>, RHS - 1545175709U, // <4,6,0,u>: Cost 2 vext2 <0,2,4,6>, LHS - 2618917622U, // <4,6,1,0>: Cost 3 vext2 <0,2,4,6>, <1,0,3,2> - 2618917684U, // <4,6,1,1>: Cost 3 vext2 <0,2,4,6>, <1,1,1,1> - 2618917782U, // <4,6,1,2>: Cost 3 vext2 <0,2,4,6>, <1,2,3,0> - 2618917848U, // <4,6,1,3>: Cost 3 vext2 <0,2,4,6>, <1,3,1,3> - 3692659773U, // <4,6,1,4>: Cost 4 vext2 <0,2,4,6>, <1,4,3,5> - 2618918032U, // <4,6,1,5>: Cost 3 vext2 <0,2,4,6>, <1,5,3,7> - 3692659937U, // <4,6,1,6>: Cost 4 vext2 <0,2,4,6>, <1,6,3,7> - 4032146742U, // <4,6,1,7>: Cost 4 vzipr <0,u,4,1>, RHS - 2618918253U, // <4,6,1,u>: Cost 3 vext2 <0,2,4,6>, <1,u,1,3> - 2618918380U, // <4,6,2,0>: Cost 3 vext2 <0,2,4,6>, <2,0,6,4> - 2618918460U, // <4,6,2,1>: Cost 3 vext2 <0,2,4,6>, <2,1,6,3> - 2618918504U, // <4,6,2,2>: Cost 3 vext2 <0,2,4,6>, <2,2,2,2> - 2618918566U, // <4,6,2,3>: Cost 3 vext2 <0,2,4,6>, <2,3,0,1> - 2618918679U, // <4,6,2,4>: Cost 3 vext2 <0,2,4,6>, <2,4,3,6> - 2618918788U, // <4,6,2,5>: Cost 3 vext2 <0,2,4,6>, <2,5,6,7> - 2618918842U, // <4,6,2,6>: Cost 3 vext2 <0,2,4,6>, <2,6,3,7> - 2718749178U, // <4,6,2,7>: Cost 3 vext3 <5,6,7,4>, <6,2,7,3> - 2618918971U, // <4,6,2,u>: Cost 3 vext2 <0,2,4,6>, <2,u,0,1> - 2618919062U, // <4,6,3,0>: Cost 3 vext2 <0,2,4,6>, <3,0,1,2> - 2636171526U, // <4,6,3,1>: Cost 3 vext2 <3,1,4,6>, <3,1,4,6> - 3692661057U, // <4,6,3,2>: Cost 4 vext2 <0,2,4,6>, <3,2,2,2> - 2618919324U, // <4,6,3,3>: Cost 3 vext2 <0,2,4,6>, <3,3,3,3> - 2618919426U, // <4,6,3,4>: Cost 3 vext2 <0,2,4,6>, <3,4,5,6> - 2638826058U, // <4,6,3,5>: Cost 3 vext2 <3,5,4,6>, <3,5,4,6> - 3913303030U, // <4,6,3,6>: Cost 4 vuzpr <3,4,5,6>, <1,3,4,6> - 2722730572U, // <4,6,3,7>: Cost 3 vext3 <6,3,7,4>, <6,3,7,4> - 2618919710U, // <4,6,3,u>: Cost 3 vext2 <0,2,4,6>, <3,u,1,2> - 2565210214U, // <4,6,4,0>: Cost 3 vext1 <2,4,6,4>, LHS - 2718749286U, // <4,6,4,1>: Cost 3 vext3 <5,6,7,4>, <6,4,1,3> - 2565211952U, // <4,6,4,2>: Cost 3 vext1 <2,4,6,4>, <2,4,6,4> - 2571184649U, // <4,6,4,3>: Cost 3 vext1 <3,4,6,4>, <3,4,6,4> - 2565213494U, // <4,6,4,4>: Cost 3 vext1 <2,4,6,4>, RHS - 1545178422U, // <4,6,4,5>: Cost 2 vext2 <0,2,4,6>, RHS - 1705430326U, // <4,6,4,6>: Cost 2 vuzpl RHS, RHS - 2595075437U, // <4,6,4,7>: Cost 3 vext1 <7,4,6,4>, <7,4,6,4> - 1545178665U, // <4,6,4,u>: Cost 2 vext2 <0,2,4,6>, RHS - 2565218406U, // <4,6,5,0>: Cost 3 vext1 <2,4,6,5>, LHS - 2645462736U, // <4,6,5,1>: Cost 3 vext2 <4,6,4,6>, <5,1,7,3> - 2913399290U, // <4,6,5,2>: Cost 3 vzipl RHS, <6,2,7,3> - 3913305394U, // <4,6,5,3>: Cost 4 vuzpr <3,4,5,6>, <4,5,6,3> - 2645462982U, // <4,6,5,4>: Cost 3 vext2 <4,6,4,6>, <5,4,7,6> - 2779172868U, // <4,6,5,5>: Cost 3 vuzpl RHS, <5,5,5,5> - 2913391416U, // <4,6,5,6>: Cost 3 vzipl RHS, <6,6,6,6> - 2821426486U, // <4,6,5,7>: Cost 3 vuzpr <0,4,2,6>, RHS - 2821426487U, // <4,6,5,u>: Cost 3 vuzpr <0,4,2,6>, RHS - 1503428710U, // <4,6,6,0>: Cost 2 vext1 <4,4,6,6>, LHS - 2577171190U, // <4,6,6,1>: Cost 3 vext1 <4,4,6,6>, <1,0,3,2> - 2645463546U, // <4,6,6,2>: Cost 3 vext2 <4,6,4,6>, <6,2,7,3> - 2577172630U, // <4,6,6,3>: Cost 3 vext1 <4,4,6,6>, <3,0,1,2> - 1503431908U, // <4,6,6,4>: Cost 2 vext1 <4,4,6,6>, <4,4,6,6> - 2253501069U, // <4,6,6,5>: Cost 3 vrev <6,4,5,6> - 2618921784U, // <4,6,6,6>: Cost 3 vext2 <0,2,4,6>, <6,6,6,6> - 2954464566U, // <4,6,6,7>: Cost 3 vzipr <0,2,4,6>, RHS - 1503434542U, // <4,6,6,u>: Cost 2 vext1 <4,4,6,6>, LHS - 2645464058U, // <4,6,7,0>: Cost 3 vext2 <4,6,4,6>, <7,0,1,2> - 2779173882U, // <4,6,7,1>: Cost 3 vuzpl RHS, <7,0,1,2> - 3638978355U, // <4,6,7,2>: Cost 4 vext1 <2,4,6,7>, <2,4,6,7> - 2725090156U, // <4,6,7,3>: Cost 3 vext3 <6,7,3,4>, <6,7,3,4> - 2645464422U, // <4,6,7,4>: Cost 3 vext2 <4,6,4,6>, <7,4,5,6> - 2779174246U, // <4,6,7,5>: Cost 3 vuzpl RHS, <7,4,5,6> - 3852915914U, // <4,6,7,6>: Cost 4 vuzpl RHS, <7,2,6,3> - 2779174508U, // <4,6,7,7>: Cost 3 vuzpl RHS, <7,7,7,7> - 2779173945U, // <4,6,7,u>: Cost 3 vuzpl RHS, <7,0,u,2> - 1503445094U, // <4,6,u,0>: Cost 2 vext1 <4,4,6,u>, LHS - 1545180974U, // <4,6,u,1>: Cost 2 vext2 <0,2,4,6>, LHS - 1705432878U, // <4,6,u,2>: Cost 2 vuzpl RHS, LHS - 2618922940U, // <4,6,u,3>: Cost 3 vext2 <0,2,4,6>, - 1503448294U, // <4,6,u,4>: Cost 2 vext1 <4,4,6,u>, <4,4,6,u> - 1545181338U, // <4,6,u,5>: Cost 2 vext2 <0,2,4,6>, RHS - 1705433242U, // <4,6,u,6>: Cost 2 vuzpl RHS, RHS - 2954480950U, // <4,6,u,7>: Cost 3 vzipr <0,2,4,u>, RHS - 1545181541U, // <4,6,u,u>: Cost 2 vext2 <0,2,4,6>, LHS - 3706601472U, // <4,7,0,0>: Cost 4 vext2 <2,5,4,7>, <0,0,0,0> - 2632859750U, // <4,7,0,1>: Cost 3 vext2 <2,5,4,7>, LHS - 2726343685U, // <4,7,0,2>: Cost 3 vext3 <7,0,2,4>, <7,0,2,4> - 3701293312U, // <4,7,0,3>: Cost 4 vext2 <1,6,4,7>, <0,3,1,4> - 3706601810U, // <4,7,0,4>: Cost 4 vext2 <2,5,4,7>, <0,4,1,5> - 2259424608U, // <4,7,0,5>: Cost 3 vrev <7,4,5,0> - 3695321617U, // <4,7,0,6>: Cost 4 vext2 <0,6,4,7>, <0,6,4,7> - 3800454194U, // <4,7,0,7>: Cost 4 vext3 <7,0,7,4>, <7,0,7,4> - 2632860317U, // <4,7,0,u>: Cost 3 vext2 <2,5,4,7>, LHS - 2259064116U, // <4,7,1,0>: Cost 3 vrev <7,4,0,1> - 3700630324U, // <4,7,1,1>: Cost 4 vext2 <1,5,4,7>, <1,1,1,1> - 2632860570U, // <4,7,1,2>: Cost 3 vext2 <2,5,4,7>, <1,2,3,4> - 3769635936U, // <4,7,1,3>: Cost 4 vext3 <1,u,3,4>, <7,1,3,5> - 3656920374U, // <4,7,1,4>: Cost 4 vext1 <5,4,7,1>, RHS - 3700630681U, // <4,7,1,5>: Cost 4 vext2 <1,5,4,7>, <1,5,4,7> - 3701294314U, // <4,7,1,6>: Cost 4 vext2 <1,6,4,7>, <1,6,4,7> - 3793818754U, // <4,7,1,7>: Cost 4 vext3 <5,u,7,4>, <7,1,7,3> - 2259654012U, // <4,7,1,u>: Cost 3 vrev <7,4,u,1> - 3656925286U, // <4,7,2,0>: Cost 4 vext1 <5,4,7,2>, LHS - 3706603050U, // <4,7,2,1>: Cost 4 vext2 <2,5,4,7>, <2,1,4,3> - 3706603112U, // <4,7,2,2>: Cost 4 vext2 <2,5,4,7>, <2,2,2,2> - 2727744688U, // <4,7,2,3>: Cost 3 vext3 <7,2,3,4>, <7,2,3,4> - 3705939745U, // <4,7,2,4>: Cost 4 vext2 <2,4,4,7>, <2,4,4,7> - 2632861554U, // <4,7,2,5>: Cost 3 vext2 <2,5,4,7>, <2,5,4,7> - 3706603450U, // <4,7,2,6>: Cost 4 vext2 <2,5,4,7>, <2,6,3,7> - 3792491731U, // <4,7,2,7>: Cost 4 vext3 <5,6,7,4>, <7,2,7,3> - 2634852453U, // <4,7,2,u>: Cost 3 vext2 <2,u,4,7>, <2,u,4,7> - 3706603670U, // <4,7,3,0>: Cost 4 vext2 <2,5,4,7>, <3,0,1,2> - 3662906266U, // <4,7,3,1>: Cost 4 vext1 <6,4,7,3>, <1,2,3,4> - 3725183326U, // <4,7,3,2>: Cost 4 vext2 <5,6,4,7>, <3,2,5,4> - 3706603932U, // <4,7,3,3>: Cost 4 vext2 <2,5,4,7>, <3,3,3,3> - 3701295618U, // <4,7,3,4>: Cost 4 vext2 <1,6,4,7>, <3,4,5,6> - 2638834251U, // <4,7,3,5>: Cost 3 vext2 <3,5,4,7>, <3,5,4,7> - 2639497884U, // <4,7,3,6>: Cost 3 vext2 <3,6,4,7>, <3,6,4,7> - 3802445093U, // <4,7,3,7>: Cost 4 vext3 <7,3,7,4>, <7,3,7,4> - 2640825150U, // <4,7,3,u>: Cost 3 vext2 <3,u,4,7>, <3,u,4,7> - 2718750004U, // <4,7,4,0>: Cost 3 vext3 <5,6,7,4>, <7,4,0,1> - 3706604490U, // <4,7,4,1>: Cost 4 vext2 <2,5,4,7>, <4,1,2,3> - 3656943474U, // <4,7,4,2>: Cost 4 vext1 <5,4,7,4>, <2,5,4,7> - 3779884371U, // <4,7,4,3>: Cost 4 vext3 <3,5,7,4>, <7,4,3,5> - 2259383643U, // <4,7,4,4>: Cost 3 vrev <7,4,4,4> - 2632863030U, // <4,7,4,5>: Cost 3 vext2 <2,5,4,7>, RHS - 2259531117U, // <4,7,4,6>: Cost 3 vrev <7,4,6,4> - 3907340074U, // <4,7,4,7>: Cost 4 vuzpr <2,4,5,7>, <2,4,5,7> - 2632863273U, // <4,7,4,u>: Cost 3 vext2 <2,5,4,7>, RHS - 2913391610U, // <4,7,5,0>: Cost 3 vzipl RHS, <7,0,1,2> - 3645006848U, // <4,7,5,1>: Cost 4 vext1 <3,4,7,5>, <1,3,5,7> - 2589181646U, // <4,7,5,2>: Cost 3 vext1 <6,4,7,5>, <2,3,4,5> - 3645008403U, // <4,7,5,3>: Cost 4 vext1 <3,4,7,5>, <3,4,7,5> - 2913391974U, // <4,7,5,4>: Cost 3 vzipl RHS, <7,4,5,6> - 2583211973U, // <4,7,5,5>: Cost 3 vext1 <5,4,7,5>, <5,4,7,5> - 2589184670U, // <4,7,5,6>: Cost 3 vext1 <6,4,7,5>, <6,4,7,5> - 2913392236U, // <4,7,5,7>: Cost 3 vzipl RHS, <7,7,7,7> - 2913392258U, // <4,7,5,u>: Cost 3 vzipl RHS, <7,u,1,2> - 1509474406U, // <4,7,6,0>: Cost 2 vext1 <5,4,7,6>, LHS - 3047609338U, // <4,7,6,1>: Cost 3 vtrnl RHS, <7,0,1,2> - 2583217768U, // <4,7,6,2>: Cost 3 vext1 <5,4,7,6>, <2,2,2,2> - 2583218326U, // <4,7,6,3>: Cost 3 vext1 <5,4,7,6>, <3,0,1,2> - 1509477686U, // <4,7,6,4>: Cost 2 vext1 <5,4,7,6>, RHS - 1509478342U, // <4,7,6,5>: Cost 2 vext1 <5,4,7,6>, <5,4,7,6> - 2583220730U, // <4,7,6,6>: Cost 3 vext1 <5,4,7,6>, <6,2,7,3> - 3047609964U, // <4,7,6,7>: Cost 3 vtrnl RHS, <7,7,7,7> - 1509480238U, // <4,7,6,u>: Cost 2 vext1 <5,4,7,6>, LHS - 3650994278U, // <4,7,7,0>: Cost 4 vext1 <4,4,7,7>, LHS - 3650995098U, // <4,7,7,1>: Cost 4 vext1 <4,4,7,7>, <1,2,3,4> - 3650996010U, // <4,7,7,2>: Cost 4 vext1 <4,4,7,7>, <2,4,5,7> - 3804804677U, // <4,7,7,3>: Cost 4 vext3 <7,7,3,4>, <7,7,3,4> - 3650997486U, // <4,7,7,4>: Cost 4 vext1 <4,4,7,7>, <4,4,7,7> - 2662725039U, // <4,7,7,5>: Cost 3 vext2 <7,5,4,7>, <7,5,4,7> - 3662942880U, // <4,7,7,6>: Cost 4 vext1 <6,4,7,7>, <6,4,7,7> - 2718750316U, // <4,7,7,7>: Cost 3 vext3 <5,6,7,4>, <7,7,7,7> - 2664715938U, // <4,7,7,u>: Cost 3 vext2 <7,u,4,7>, <7,u,4,7> - 1509490790U, // <4,7,u,0>: Cost 2 vext1 <5,4,7,u>, LHS - 2632865582U, // <4,7,u,1>: Cost 3 vext2 <2,5,4,7>, LHS - 2583234152U, // <4,7,u,2>: Cost 3 vext1 <5,4,7,u>, <2,2,2,2> - 2583234710U, // <4,7,u,3>: Cost 3 vext1 <5,4,7,u>, <3,0,1,2> - 1509494070U, // <4,7,u,4>: Cost 2 vext1 <5,4,7,u>, RHS - 1509494728U, // <4,7,u,5>: Cost 2 vext1 <5,4,7,u>, <5,4,7,u> - 2583237114U, // <4,7,u,6>: Cost 3 vext1 <5,4,7,u>, <6,2,7,3> - 3047757420U, // <4,7,u,7>: Cost 3 vtrnl RHS, <7,7,7,7> - 1509496622U, // <4,7,u,u>: Cost 2 vext1 <5,4,7,u>, LHS - 2618933248U, // <4,u,0,0>: Cost 3 vext2 <0,2,4,u>, <0,0,0,0> - 1545191526U, // <4,u,0,1>: Cost 2 vext2 <0,2,4,u>, LHS - 1545191630U, // <4,u,0,2>: Cost 2 vext2 <0,2,4,u>, <0,2,4,u> - 2691913445U, // <4,u,0,3>: Cost 3 vext3 <1,2,3,4>, - 2618933586U, // <4,u,0,4>: Cost 3 vext2 <0,2,4,u>, <0,4,1,5> - 2265397305U, // <4,u,0,5>: Cost 3 vrev - 2595189625U, // <4,u,0,6>: Cost 3 vext1 <7,4,u,0>, <6,7,4,u> - 2595190139U, // <4,u,0,7>: Cost 3 vext1 <7,4,u,0>, <7,4,u,0> - 1545192093U, // <4,u,0,u>: Cost 2 vext2 <0,2,4,u>, LHS - 2618934006U, // <4,u,1,0>: Cost 3 vext2 <0,2,4,u>, <1,0,3,2> - 2618934068U, // <4,u,1,1>: Cost 3 vext2 <0,2,4,u>, <1,1,1,1> - 1618171694U, // <4,u,1,2>: Cost 2 vext3 <1,2,3,4>, LHS - 2618934232U, // <4,u,1,3>: Cost 3 vext2 <0,2,4,u>, <1,3,1,3> - 2695894848U, // <4,u,1,4>: Cost 3 vext3 <1,u,3,4>, - 2618934416U, // <4,u,1,5>: Cost 3 vext2 <0,2,4,u>, <1,5,3,7> - 3692676321U, // <4,u,1,6>: Cost 4 vext2 <0,2,4,u>, <1,6,3,7> - 2718750555U, // <4,u,1,7>: Cost 3 vext3 <5,6,7,4>, - 1618171748U, // <4,u,1,u>: Cost 2 vext3 <1,2,3,4>, LHS - 2553397350U, // <4,u,2,0>: Cost 3 vext1 <0,4,u,2>, LHS - 2630215215U, // <4,u,2,1>: Cost 3 vext2 <2,1,4,u>, <2,1,4,u> - 2618934888U, // <4,u,2,2>: Cost 3 vext2 <0,2,4,u>, <2,2,2,2> - 1557800657U, // <4,u,2,3>: Cost 2 vext2 <2,3,4,u>, <2,3,4,u> - 2618935065U, // <4,u,2,4>: Cost 3 vext2 <0,2,4,u>, <2,4,3,u> - 2733864859U, // <4,u,2,5>: Cost 3 vext3 , - 2618935226U, // <4,u,2,6>: Cost 3 vext2 <0,2,4,u>, <2,6,3,7> - 2718750636U, // <4,u,2,7>: Cost 3 vext3 <5,6,7,4>, - 1561118822U, // <4,u,2,u>: Cost 2 vext2 <2,u,4,u>, <2,u,4,u> - 2618935446U, // <4,u,3,0>: Cost 3 vext2 <0,2,4,u>, <3,0,1,2> - 2779318422U, // <4,u,3,1>: Cost 3 vuzpl RHS, <3,0,1,2> - 2636851545U, // <4,u,3,2>: Cost 3 vext2 <3,2,4,u>, <3,2,4,u> - 2618935708U, // <4,u,3,3>: Cost 3 vext2 <0,2,4,u>, <3,3,3,3> - 2618935810U, // <4,u,3,4>: Cost 3 vext2 <0,2,4,u>, <3,4,5,6> - 2691913711U, // <4,u,3,5>: Cost 3 vext3 <1,2,3,4>, - 2588725862U, // <4,u,3,6>: Cost 3 vext1 <6,4,1,3>, <6,4,1,3> - 2640169710U, // <4,u,3,7>: Cost 3 vext2 <3,7,4,u>, <3,7,4,u> - 2618936094U, // <4,u,3,u>: Cost 3 vext2 <0,2,4,u>, <3,u,1,2> - 1503559782U, // <4,u,4,0>: Cost 2 vext1 <4,4,u,4>, LHS - 2692282391U, // <4,u,4,1>: Cost 3 vext3 <1,2,u,4>, - 2565359426U, // <4,u,4,2>: Cost 3 vext1 <2,4,u,4>, <2,4,u,4> - 2571332123U, // <4,u,4,3>: Cost 3 vext1 <3,4,u,4>, <3,4,u,4> - 161926454U, // <4,u,4,4>: Cost 1 vdup0 RHS - 1545194806U, // <4,u,4,5>: Cost 2 vext2 <0,2,4,u>, RHS - 1705577782U, // <4,u,4,6>: Cost 2 vuzpl RHS, RHS - 2718750801U, // <4,u,4,7>: Cost 3 vext3 <5,6,7,4>, - 161926454U, // <4,u,4,u>: Cost 1 vdup0 RHS - 1479164006U, // <4,u,5,0>: Cost 2 vext1 <0,4,1,5>, LHS - 1839650606U, // <4,u,5,1>: Cost 2 vzipl RHS, LHS - 2565367502U, // <4,u,5,2>: Cost 3 vext1 <2,4,u,5>, <2,3,4,5> - 3089777309U, // <4,u,5,3>: Cost 3 vtrnr <0,4,1,5>, LHS - 1479167286U, // <4,u,5,4>: Cost 2 vext1 <0,4,1,5>, RHS - 1839650970U, // <4,u,5,5>: Cost 2 vzipl RHS, RHS - 1618172058U, // <4,u,5,6>: Cost 2 vext3 <1,2,3,4>, RHS - 3089780265U, // <4,u,5,7>: Cost 3 vtrnr <0,4,1,5>, RHS - 1618172076U, // <4,u,5,u>: Cost 2 vext3 <1,2,3,4>, RHS - 1479688294U, // <4,u,6,0>: Cost 2 vext1 <0,4,u,6>, LHS - 2553430774U, // <4,u,6,1>: Cost 3 vext1 <0,4,u,6>, <1,0,3,2> - 1973868334U, // <4,u,6,2>: Cost 2 vtrnl RHS, LHS - 1497606685U, // <4,u,6,3>: Cost 2 vext1 <3,4,u,6>, <3,4,u,6> - 1479691574U, // <4,u,6,4>: Cost 2 vext1 <0,4,u,6>, RHS - 1509552079U, // <4,u,6,5>: Cost 2 vext1 <5,4,u,6>, <5,4,u,6> - 1973868698U, // <4,u,6,6>: Cost 2 vtrnl RHS, RHS - 27705344U, // <4,u,6,7>: Cost 0 copy RHS - 27705344U, // <4,u,6,u>: Cost 0 copy RHS - 2565382246U, // <4,u,7,0>: Cost 3 vext1 <2,4,u,7>, LHS - 2565383066U, // <4,u,7,1>: Cost 3 vext1 <2,4,u,7>, <1,2,3,4> - 2565384005U, // <4,u,7,2>: Cost 3 vext1 <2,4,u,7>, <2,4,u,7> - 2661405966U, // <4,u,7,3>: Cost 3 vext2 <7,3,4,u>, <7,3,4,u> - 2565385526U, // <4,u,7,4>: Cost 3 vext1 <2,4,u,7>, RHS - 2779321702U, // <4,u,7,5>: Cost 3 vuzpl RHS, <7,4,5,6> - 2589274793U, // <4,u,7,6>: Cost 3 vext1 <6,4,u,7>, <6,4,u,7> - 2779321964U, // <4,u,7,7>: Cost 3 vuzpl RHS, <7,7,7,7> - 2565388078U, // <4,u,7,u>: Cost 3 vext1 <2,4,u,7>, LHS - 1479704678U, // <4,u,u,0>: Cost 2 vext1 <0,4,u,u>, LHS - 1545197358U, // <4,u,u,1>: Cost 2 vext2 <0,2,4,u>, LHS - 1618172261U, // <4,u,u,2>: Cost 2 vext3 <1,2,3,4>, LHS - 1497623071U, // <4,u,u,3>: Cost 2 vext1 <3,4,u,u>, <3,4,u,u> - 161926454U, // <4,u,u,4>: Cost 1 vdup0 RHS - 1545197722U, // <4,u,u,5>: Cost 2 vext2 <0,2,4,u>, RHS - 1618172301U, // <4,u,u,6>: Cost 2 vext3 <1,2,3,4>, RHS - 27705344U, // <4,u,u,7>: Cost 0 copy RHS - 27705344U, // <4,u,u,u>: Cost 0 copy RHS - 2687123456U, // <5,0,0,0>: Cost 3 vext3 <0,4,1,5>, <0,0,0,0> - 2687123466U, // <5,0,0,1>: Cost 3 vext3 <0,4,1,5>, <0,0,1,1> - 2687123476U, // <5,0,0,2>: Cost 3 vext3 <0,4,1,5>, <0,0,2,2> - 3710599434U, // <5,0,0,3>: Cost 4 vext2 <3,2,5,0>, <0,3,2,5> - 2642166098U, // <5,0,0,4>: Cost 3 vext2 <4,1,5,0>, <0,4,1,5> - 3657060306U, // <5,0,0,5>: Cost 4 vext1 <5,5,0,0>, <5,5,0,0> - 3292094923U, // <5,0,0,6>: Cost 4 vrev <0,5,6,0> - 3669005700U, // <5,0,0,7>: Cost 4 vext1 <7,5,0,0>, <7,5,0,0> - 2687123530U, // <5,0,0,u>: Cost 3 vext3 <0,4,1,5>, <0,0,u,2> - 2559434854U, // <5,0,1,0>: Cost 3 vext1 <1,5,0,1>, LHS - 2559435887U, // <5,0,1,1>: Cost 3 vext1 <1,5,0,1>, <1,5,0,1> - 1613381734U, // <5,0,1,2>: Cost 2 vext3 <0,4,1,5>, LHS - 3698656256U, // <5,0,1,3>: Cost 4 vext2 <1,2,5,0>, <1,3,5,7> - 2559438134U, // <5,0,1,4>: Cost 3 vext1 <1,5,0,1>, RHS - 2583326675U, // <5,0,1,5>: Cost 3 vext1 <5,5,0,1>, <5,5,0,1> - 3715908851U, // <5,0,1,6>: Cost 4 vext2 <4,1,5,0>, <1,6,5,7> - 3657069562U, // <5,0,1,7>: Cost 4 vext1 <5,5,0,1>, <7,0,1,2> - 1613381788U, // <5,0,1,u>: Cost 2 vext3 <0,4,1,5>, LHS - 2686017700U, // <5,0,2,0>: Cost 3 vext3 <0,2,4,5>, <0,2,0,2> - 2685796528U, // <5,0,2,1>: Cost 3 vext3 <0,2,1,5>, <0,2,1,5> - 2698625208U, // <5,0,2,2>: Cost 3 vext3 <2,3,4,5>, <0,2,2,4> - 2685944002U, // <5,0,2,3>: Cost 3 vext3 <0,2,3,5>, <0,2,3,5> - 2686017739U, // <5,0,2,4>: Cost 3 vext3 <0,2,4,5>, <0,2,4,5> - 2686091476U, // <5,0,2,5>: Cost 3 vext3 <0,2,5,5>, <0,2,5,5> - 2725167324U, // <5,0,2,6>: Cost 3 vext3 <6,7,4,5>, <0,2,6,4> - 2595280230U, // <5,0,2,7>: Cost 3 vext1 <7,5,0,2>, <7,4,5,6> - 2686312687U, // <5,0,2,u>: Cost 3 vext3 <0,2,u,5>, <0,2,u,5> - 3760128248U, // <5,0,3,0>: Cost 4 vext3 <0,3,0,5>, <0,3,0,5> - 3759685888U, // <5,0,3,1>: Cost 4 vext3 <0,2,3,5>, <0,3,1,4> - 2686533898U, // <5,0,3,2>: Cost 3 vext3 <0,3,2,5>, <0,3,2,5> - 3760349459U, // <5,0,3,3>: Cost 4 vext3 <0,3,3,5>, <0,3,3,5> - 2638187004U, // <5,0,3,4>: Cost 3 vext2 <3,4,5,0>, <3,4,5,0> - 3776348452U, // <5,0,3,5>: Cost 4 vext3 <3,0,4,5>, <0,3,5,4> - 3713256094U, // <5,0,3,6>: Cost 4 vext2 <3,6,5,0>, <3,6,5,0> - 3914064896U, // <5,0,3,7>: Cost 4 vuzpr <3,5,7,0>, <1,3,5,7> - 2686976320U, // <5,0,3,u>: Cost 3 vext3 <0,3,u,5>, <0,3,u,5> - 2559459430U, // <5,0,4,0>: Cost 3 vext1 <1,5,0,4>, LHS - 1613381970U, // <5,0,4,1>: Cost 2 vext3 <0,4,1,5>, <0,4,1,5> - 2687123804U, // <5,0,4,2>: Cost 3 vext3 <0,4,1,5>, <0,4,2,6> - 3761013092U, // <5,0,4,3>: Cost 4 vext3 <0,4,3,5>, <0,4,3,5> - 2559462710U, // <5,0,4,4>: Cost 3 vext1 <1,5,0,4>, RHS - 2638187830U, // <5,0,4,5>: Cost 3 vext2 <3,4,5,0>, RHS - 3761234303U, // <5,0,4,6>: Cost 4 vext3 <0,4,6,5>, <0,4,6,5> - 2646150600U, // <5,0,4,7>: Cost 3 vext2 <4,7,5,0>, <4,7,5,0> - 1613381970U, // <5,0,4,u>: Cost 2 vext3 <0,4,1,5>, <0,4,1,5> - 3766763926U, // <5,0,5,0>: Cost 4 vext3 <1,4,0,5>, <0,5,0,1> - 2919268454U, // <5,0,5,1>: Cost 3 vzipl <5,5,5,5>, LHS - 3053486182U, // <5,0,5,2>: Cost 3 vtrnl <5,5,5,5>, LHS - 3723210589U, // <5,0,5,3>: Cost 4 vext2 <5,3,5,0>, <5,3,5,0> - 3766763966U, // <5,0,5,4>: Cost 4 vext3 <1,4,0,5>, <0,5,4,5> - 2650796031U, // <5,0,5,5>: Cost 3 vext2 <5,5,5,0>, <5,5,5,0> - 3719893090U, // <5,0,5,6>: Cost 4 vext2 <4,7,5,0>, <5,6,7,0> - 3914067254U, // <5,0,5,7>: Cost 4 vuzpr <3,5,7,0>, RHS - 2919269021U, // <5,0,5,u>: Cost 3 vzipl <5,5,5,5>, LHS - 4047519744U, // <5,0,6,0>: Cost 4 vzipr <3,4,5,6>, <0,0,0,0> - 2920038502U, // <5,0,6,1>: Cost 3 vzipl <5,6,7,0>, LHS - 3759759871U, // <5,0,6,2>: Cost 4 vext3 <0,2,4,5>, <0,6,2,7> - 3645164070U, // <5,0,6,3>: Cost 4 vext1 <3,5,0,6>, <3,5,0,6> - 3762414095U, // <5,0,6,4>: Cost 4 vext3 <0,6,4,5>, <0,6,4,5> - 3993780690U, // <5,0,6,5>: Cost 4 vzipl <5,6,7,0>, <0,5,6,7> - 3719893816U, // <5,0,6,6>: Cost 4 vext2 <4,7,5,0>, <6,6,6,6> - 2662077302U, // <5,0,6,7>: Cost 3 vext2 <7,4,5,0>, <6,7,4,5> - 2920039069U, // <5,0,6,u>: Cost 3 vzipl <5,6,7,0>, LHS - 2565455974U, // <5,0,7,0>: Cost 3 vext1 <2,5,0,7>, LHS - 2565456790U, // <5,0,7,1>: Cost 3 vext1 <2,5,0,7>, <1,2,3,0> - 2565457742U, // <5,0,7,2>: Cost 3 vext1 <2,5,0,7>, <2,5,0,7> - 3639199894U, // <5,0,7,3>: Cost 4 vext1 <2,5,0,7>, <3,0,1,2> - 2565459254U, // <5,0,7,4>: Cost 3 vext1 <2,5,0,7>, RHS - 2589347938U, // <5,0,7,5>: Cost 3 vext1 <6,5,0,7>, <5,6,7,0> - 2589348530U, // <5,0,7,6>: Cost 3 vext1 <6,5,0,7>, <6,5,0,7> - 4188456422U, // <5,0,7,7>: Cost 4 vtrnr RHS, <2,0,5,7> - 2565461806U, // <5,0,7,u>: Cost 3 vext1 <2,5,0,7>, LHS - 2687124106U, // <5,0,u,0>: Cost 3 vext3 <0,4,1,5>, <0,u,0,2> - 1616036502U, // <5,0,u,1>: Cost 2 vext3 <0,u,1,5>, <0,u,1,5> - 1613382301U, // <5,0,u,2>: Cost 2 vext3 <0,4,1,5>, LHS - 2689925800U, // <5,0,u,3>: Cost 3 vext3 <0,u,3,5>, <0,u,3,5> - 2687124146U, // <5,0,u,4>: Cost 3 vext3 <0,4,1,5>, <0,u,4,6> - 2638190746U, // <5,0,u,5>: Cost 3 vext2 <3,4,5,0>, RHS - 2589356723U, // <5,0,u,6>: Cost 3 vext1 <6,5,0,u>, <6,5,0,u> - 2595280230U, // <5,0,u,7>: Cost 3 vext1 <7,5,0,2>, <7,4,5,6> - 1613382355U, // <5,0,u,u>: Cost 2 vext3 <0,4,1,5>, LHS - 2646818816U, // <5,1,0,0>: Cost 3 vext2 <4,u,5,1>, <0,0,0,0> - 1573077094U, // <5,1,0,1>: Cost 2 vext2 <4,u,5,1>, LHS - 2646818980U, // <5,1,0,2>: Cost 3 vext2 <4,u,5,1>, <0,2,0,2> - 2687124214U, // <5,1,0,3>: Cost 3 vext3 <0,4,1,5>, <1,0,3,2> - 2641510738U, // <5,1,0,4>: Cost 3 vext2 <4,0,5,1>, <0,4,1,5> - 2641510814U, // <5,1,0,5>: Cost 3 vext2 <4,0,5,1>, <0,5,1,0> - 3720561142U, // <5,1,0,6>: Cost 4 vext2 <4,u,5,1>, <0,6,1,7> - 3298141357U, // <5,1,0,7>: Cost 4 vrev <1,5,7,0> - 1573077661U, // <5,1,0,u>: Cost 2 vext2 <4,u,5,1>, LHS - 2223891567U, // <5,1,1,0>: Cost 3 vrev <1,5,0,1> - 2687124276U, // <5,1,1,1>: Cost 3 vext3 <0,4,1,5>, <1,1,1,1> - 2646819734U, // <5,1,1,2>: Cost 3 vext2 <4,u,5,1>, <1,2,3,0> - 2687124296U, // <5,1,1,3>: Cost 3 vext3 <0,4,1,5>, <1,1,3,3> - 2691326803U, // <5,1,1,4>: Cost 3 vext3 <1,1,4,5>, <1,1,4,5> - 2691400540U, // <5,1,1,5>: Cost 3 vext3 <1,1,5,5>, <1,1,5,5> - 3765216101U, // <5,1,1,6>: Cost 4 vext3 <1,1,6,5>, <1,1,6,5> - 3765289838U, // <5,1,1,7>: Cost 4 vext3 <1,1,7,5>, <1,1,7,5> - 2687124341U, // <5,1,1,u>: Cost 3 vext3 <0,4,1,5>, <1,1,u,3> - 3297641584U, // <5,1,2,0>: Cost 4 vrev <1,5,0,2> - 3763520391U, // <5,1,2,1>: Cost 4 vext3 <0,u,1,5>, <1,2,1,3> - 2646820456U, // <5,1,2,2>: Cost 3 vext2 <4,u,5,1>, <2,2,2,2> - 2687124374U, // <5,1,2,3>: Cost 3 vext3 <0,4,1,5>, <1,2,3,0> - 2691990436U, // <5,1,2,4>: Cost 3 vext3 <1,2,4,5>, <1,2,4,5> - 2687124395U, // <5,1,2,5>: Cost 3 vext3 <0,4,1,5>, <1,2,5,3> - 2646820794U, // <5,1,2,6>: Cost 3 vext2 <4,u,5,1>, <2,6,3,7> - 3808199610U, // <5,1,2,7>: Cost 4 vext3 , <1,2,7,0> - 2687124419U, // <5,1,2,u>: Cost 3 vext3 <0,4,1,5>, <1,2,u,0> - 2577440870U, // <5,1,3,0>: Cost 3 vext1 <4,5,1,3>, LHS - 2687124440U, // <5,1,3,1>: Cost 3 vext3 <0,4,1,5>, <1,3,1,3> - 3759686627U, // <5,1,3,2>: Cost 4 vext3 <0,2,3,5>, <1,3,2,5> - 2692580332U, // <5,1,3,3>: Cost 3 vext3 <1,3,3,5>, <1,3,3,5> - 2687124469U, // <5,1,3,4>: Cost 3 vext3 <0,4,1,5>, <1,3,4,5> - 2685207552U, // <5,1,3,5>: Cost 3 vext3 <0,1,2,5>, <1,3,5,7> - 3760866313U, // <5,1,3,6>: Cost 4 vext3 <0,4,1,5>, <1,3,6,7> - 2692875280U, // <5,1,3,7>: Cost 3 vext3 <1,3,7,5>, <1,3,7,5> - 2687124503U, // <5,1,3,u>: Cost 3 vext3 <0,4,1,5>, <1,3,u,3> - 1567771538U, // <5,1,4,0>: Cost 2 vext2 <4,0,5,1>, <4,0,5,1> - 2693096491U, // <5,1,4,1>: Cost 3 vext3 <1,4,1,5>, <1,4,1,5> - 2693170228U, // <5,1,4,2>: Cost 3 vext3 <1,4,2,5>, <1,4,2,5> - 2687124541U, // <5,1,4,3>: Cost 3 vext3 <0,4,1,5>, <1,4,3,5> - 2646822096U, // <5,1,4,4>: Cost 3 vext2 <4,u,5,1>, <4,4,4,4> - 1573080374U, // <5,1,4,5>: Cost 2 vext2 <4,u,5,1>, RHS - 2646822260U, // <5,1,4,6>: Cost 3 vext2 <4,u,5,1>, <4,6,4,6> - 3298174129U, // <5,1,4,7>: Cost 4 vrev <1,5,7,4> - 1573080602U, // <5,1,4,u>: Cost 2 vext2 <4,u,5,1>, <4,u,5,1> - 2687124591U, // <5,1,5,0>: Cost 3 vext3 <0,4,1,5>, <1,5,0,1> - 2646822543U, // <5,1,5,1>: Cost 3 vext2 <4,u,5,1>, <5,1,0,1> - 3760866433U, // <5,1,5,2>: Cost 4 vext3 <0,4,1,5>, <1,5,2,1> - 2687124624U, // <5,1,5,3>: Cost 3 vext3 <0,4,1,5>, <1,5,3,7> - 2687124631U, // <5,1,5,4>: Cost 3 vext3 <0,4,1,5>, <1,5,4,5> - 2646822916U, // <5,1,5,5>: Cost 3 vext2 <4,u,5,1>, <5,5,5,5> - 2646823010U, // <5,1,5,6>: Cost 3 vext2 <4,u,5,1>, <5,6,7,0> - 2646823080U, // <5,1,5,7>: Cost 3 vext2 <4,u,5,1>, <5,7,5,7> - 2687124663U, // <5,1,5,u>: Cost 3 vext3 <0,4,1,5>, <1,5,u,1> - 2553577574U, // <5,1,6,0>: Cost 3 vext1 <0,5,1,6>, LHS - 3763520719U, // <5,1,6,1>: Cost 4 vext3 <0,u,1,5>, <1,6,1,7> - 2646823418U, // <5,1,6,2>: Cost 3 vext2 <4,u,5,1>, <6,2,7,3> - 3760866529U, // <5,1,6,3>: Cost 4 vext3 <0,4,1,5>, <1,6,3,7> - 2553580854U, // <5,1,6,4>: Cost 3 vext1 <0,5,1,6>, RHS - 2687124723U, // <5,1,6,5>: Cost 3 vext3 <0,4,1,5>, <1,6,5,7> - 2646823736U, // <5,1,6,6>: Cost 3 vext2 <4,u,5,1>, <6,6,6,6> - 2646823758U, // <5,1,6,7>: Cost 3 vext2 <4,u,5,1>, <6,7,0,1> - 2646823839U, // <5,1,6,u>: Cost 3 vext2 <4,u,5,1>, <6,u,0,1> - 2559557734U, // <5,1,7,0>: Cost 3 vext1 <1,5,1,7>, LHS - 2559558452U, // <5,1,7,1>: Cost 3 vext1 <1,5,1,7>, <1,1,1,1> - 2571503270U, // <5,1,7,2>: Cost 3 vext1 <3,5,1,7>, <2,3,0,1> - 2040971366U, // <5,1,7,3>: Cost 2 vtrnr RHS, LHS - 2559561014U, // <5,1,7,4>: Cost 3 vext1 <1,5,1,7>, RHS - 2595393232U, // <5,1,7,5>: Cost 3 vext1 <7,5,1,7>, <5,1,7,3> - 4188455035U, // <5,1,7,6>: Cost 4 vtrnr RHS, <0,1,4,6> - 2646824556U, // <5,1,7,7>: Cost 3 vext2 <4,u,5,1>, <7,7,7,7> - 2040971371U, // <5,1,7,u>: Cost 2 vtrnr RHS, LHS - 1591662326U, // <5,1,u,0>: Cost 2 vext2 , - 1573082926U, // <5,1,u,1>: Cost 2 vext2 <4,u,5,1>, LHS - 2695824760U, // <5,1,u,2>: Cost 3 vext3 <1,u,2,5>, <1,u,2,5> - 2040979558U, // <5,1,u,3>: Cost 2 vtrnr RHS, LHS - 2687124874U, // <5,1,u,4>: Cost 3 vext3 <0,4,1,5>, <1,u,4,5> - 1573083290U, // <5,1,u,5>: Cost 2 vext2 <4,u,5,1>, RHS - 2646825168U, // <5,1,u,6>: Cost 3 vext2 <4,u,5,1>, - 2646825216U, // <5,1,u,7>: Cost 3 vext2 <4,u,5,1>, - 2040979563U, // <5,1,u,u>: Cost 2 vtrnr RHS, LHS - 3702652928U, // <5,2,0,0>: Cost 4 vext2 <1,u,5,2>, <0,0,0,0> - 2628911206U, // <5,2,0,1>: Cost 3 vext2 <1,u,5,2>, LHS - 2641518756U, // <5,2,0,2>: Cost 3 vext2 <4,0,5,2>, <0,2,0,2> - 3759760847U, // <5,2,0,3>: Cost 4 vext3 <0,2,4,5>, <2,0,3,2> - 3760866775U, // <5,2,0,4>: Cost 4 vext3 <0,4,1,5>, <2,0,4,1> - 3759539680U, // <5,2,0,5>: Cost 4 vext3 <0,2,1,5>, <2,0,5,1> - 3760866796U, // <5,2,0,6>: Cost 4 vext3 <0,4,1,5>, <2,0,6,4> - 3304114054U, // <5,2,0,7>: Cost 4 vrev <2,5,7,0> - 2628911773U, // <5,2,0,u>: Cost 3 vext2 <1,u,5,2>, LHS - 2623603464U, // <5,2,1,0>: Cost 3 vext2 <1,0,5,2>, <1,0,5,2> - 3698008921U, // <5,2,1,1>: Cost 4 vext2 <1,1,5,2>, <1,1,5,2> - 3633325603U, // <5,2,1,2>: Cost 4 vext1 <1,5,2,1>, <2,1,3,5> - 2687125027U, // <5,2,1,3>: Cost 3 vext3 <0,4,1,5>, <2,1,3,5> - 3633327414U, // <5,2,1,4>: Cost 4 vext1 <1,5,2,1>, RHS - 3759539760U, // <5,2,1,5>: Cost 4 vext3 <0,2,1,5>, <2,1,5,0> - 3760866876U, // <5,2,1,6>: Cost 4 vext3 <0,4,1,5>, <2,1,6,3> - 3304122247U, // <5,2,1,7>: Cost 4 vrev <2,5,7,1> - 2687125072U, // <5,2,1,u>: Cost 3 vext3 <0,4,1,5>, <2,1,u,5> - 3633332326U, // <5,2,2,0>: Cost 4 vext1 <1,5,2,2>, LHS - 3759760992U, // <5,2,2,1>: Cost 4 vext3 <0,2,4,5>, <2,2,1,3> - 2687125096U, // <5,2,2,2>: Cost 3 vext3 <0,4,1,5>, <2,2,2,2> - 2687125106U, // <5,2,2,3>: Cost 3 vext3 <0,4,1,5>, <2,2,3,3> - 2697963133U, // <5,2,2,4>: Cost 3 vext3 <2,2,4,5>, <2,2,4,5> - 3759466120U, // <5,2,2,5>: Cost 4 vext3 <0,2,0,5>, <2,2,5,7> - 3760866960U, // <5,2,2,6>: Cost 4 vext3 <0,4,1,5>, <2,2,6,6> - 3771926168U, // <5,2,2,7>: Cost 4 vext3 <2,2,7,5>, <2,2,7,5> - 2687125151U, // <5,2,2,u>: Cost 3 vext3 <0,4,1,5>, <2,2,u,3> - 2687125158U, // <5,2,3,0>: Cost 3 vext3 <0,4,1,5>, <2,3,0,1> - 2698405555U, // <5,2,3,1>: Cost 3 vext3 <2,3,1,5>, <2,3,1,5> - 2577516238U, // <5,2,3,2>: Cost 3 vext1 <4,5,2,3>, <2,3,4,5> - 3759687365U, // <5,2,3,3>: Cost 4 vext3 <0,2,3,5>, <2,3,3,5> - 1624884942U, // <5,2,3,4>: Cost 2 vext3 <2,3,4,5>, <2,3,4,5> - 2698700503U, // <5,2,3,5>: Cost 3 vext3 <2,3,5,5>, <2,3,5,5> - 3772368608U, // <5,2,3,6>: Cost 4 vext3 <2,3,4,5>, <2,3,6,5> - 3702655716U, // <5,2,3,7>: Cost 4 vext2 <1,u,5,2>, <3,7,3,7> - 1625179890U, // <5,2,3,u>: Cost 2 vext3 <2,3,u,5>, <2,3,u,5> - 2641521555U, // <5,2,4,0>: Cost 3 vext2 <4,0,5,2>, <4,0,5,2> - 3772368642U, // <5,2,4,1>: Cost 4 vext3 <2,3,4,5>, <2,4,1,3> - 2699142925U, // <5,2,4,2>: Cost 3 vext3 <2,4,2,5>, <2,4,2,5> - 2698626838U, // <5,2,4,3>: Cost 3 vext3 <2,3,4,5>, <2,4,3,5> - 2698626848U, // <5,2,4,4>: Cost 3 vext3 <2,3,4,5>, <2,4,4,6> - 2628914486U, // <5,2,4,5>: Cost 3 vext2 <1,u,5,2>, RHS - 2645503353U, // <5,2,4,6>: Cost 3 vext2 <4,6,5,2>, <4,6,5,2> - 3304146826U, // <5,2,4,7>: Cost 4 vrev <2,5,7,4> - 2628914729U, // <5,2,4,u>: Cost 3 vext2 <1,u,5,2>, RHS - 2553643110U, // <5,2,5,0>: Cost 3 vext1 <0,5,2,5>, LHS - 3758950227U, // <5,2,5,1>: Cost 4 vext3 <0,1,2,5>, <2,5,1,3> - 3759761248U, // <5,2,5,2>: Cost 4 vext3 <0,2,4,5>, <2,5,2,7> - 2982396006U, // <5,2,5,3>: Cost 3 vzipr <4,u,5,5>, LHS - 2553646390U, // <5,2,5,4>: Cost 3 vext1 <0,5,2,5>, RHS - 2553647108U, // <5,2,5,5>: Cost 3 vext1 <0,5,2,5>, <5,5,5,5> - 3760867204U, // <5,2,5,6>: Cost 4 vext3 <0,4,1,5>, <2,5,6,7> - 3702657141U, // <5,2,5,7>: Cost 4 vext2 <1,u,5,2>, <5,7,0,1> - 2982396011U, // <5,2,5,u>: Cost 3 vzipr <4,u,5,5>, LHS - 3627393126U, // <5,2,6,0>: Cost 4 vext1 <0,5,2,6>, LHS - 3760867236U, // <5,2,6,1>: Cost 4 vext3 <0,4,1,5>, <2,6,1,3> - 2645504506U, // <5,2,6,2>: Cost 3 vext2 <4,6,5,2>, <6,2,7,3> - 2687125434U, // <5,2,6,3>: Cost 3 vext3 <0,4,1,5>, <2,6,3,7> - 2700617665U, // <5,2,6,4>: Cost 3 vext3 <2,6,4,5>, <2,6,4,5> - 3760867276U, // <5,2,6,5>: Cost 4 vext3 <0,4,1,5>, <2,6,5,7> - 3763521493U, // <5,2,6,6>: Cost 4 vext3 <0,u,1,5>, <2,6,6,7> - 3719246670U, // <5,2,6,7>: Cost 4 vext2 <4,6,5,2>, <6,7,0,1> - 2687125479U, // <5,2,6,u>: Cost 3 vext3 <0,4,1,5>, <2,6,u,7> - 2565603430U, // <5,2,7,0>: Cost 3 vext1 <2,5,2,7>, LHS - 2553660150U, // <5,2,7,1>: Cost 3 vext1 <0,5,2,7>, <1,0,3,2> - 2565605216U, // <5,2,7,2>: Cost 3 vext1 <2,5,2,7>, <2,5,2,7> - 2961178726U, // <5,2,7,3>: Cost 3 vzipr <1,3,5,7>, LHS - 2565606710U, // <5,2,7,4>: Cost 3 vext1 <2,5,2,7>, RHS - 4034920552U, // <5,2,7,5>: Cost 4 vzipr <1,3,5,7>, <0,1,2,5> - 3114713292U, // <5,2,7,6>: Cost 3 vtrnr RHS, <0,2,4,6> - 3702658668U, // <5,2,7,7>: Cost 4 vext2 <1,u,5,2>, <7,7,7,7> - 2961178731U, // <5,2,7,u>: Cost 3 vzipr <1,3,5,7>, LHS - 2687125563U, // <5,2,u,0>: Cost 3 vext3 <0,4,1,5>, <2,u,0,1> - 2628917038U, // <5,2,u,1>: Cost 3 vext2 <1,u,5,2>, LHS - 2565613409U, // <5,2,u,2>: Cost 3 vext1 <2,5,2,u>, <2,5,2,u> - 2687125592U, // <5,2,u,3>: Cost 3 vext3 <0,4,1,5>, <2,u,3,3> - 1628203107U, // <5,2,u,4>: Cost 2 vext3 <2,u,4,5>, <2,u,4,5> - 2628917402U, // <5,2,u,5>: Cost 3 vext2 <1,u,5,2>, RHS - 2702092405U, // <5,2,u,6>: Cost 3 vext3 <2,u,6,5>, <2,u,6,5> - 3304179598U, // <5,2,u,7>: Cost 4 vrev <2,5,7,u> - 1628498055U, // <5,2,u,u>: Cost 2 vext3 <2,u,u,5>, <2,u,u,5> - 3760867467U, // <5,3,0,0>: Cost 4 vext3 <0,4,1,5>, <3,0,0,0> - 2687125654U, // <5,3,0,1>: Cost 3 vext3 <0,4,1,5>, <3,0,1,2> - 3759761565U, // <5,3,0,2>: Cost 4 vext3 <0,2,4,5>, <3,0,2,0> - 3633391766U, // <5,3,0,3>: Cost 4 vext1 <1,5,3,0>, <3,0,1,2> - 2687125680U, // <5,3,0,4>: Cost 3 vext3 <0,4,1,5>, <3,0,4,1> - 3760277690U, // <5,3,0,5>: Cost 4 vext3 <0,3,2,5>, <3,0,5,2> - 3310013014U, // <5,3,0,6>: Cost 4 vrev <3,5,6,0> - 2236344927U, // <5,3,0,7>: Cost 3 vrev <3,5,7,0> - 2687125717U, // <5,3,0,u>: Cost 3 vext3 <0,4,1,5>, <3,0,u,2> - 3760867551U, // <5,3,1,0>: Cost 4 vext3 <0,4,1,5>, <3,1,0,3> - 3760867558U, // <5,3,1,1>: Cost 4 vext3 <0,4,1,5>, <3,1,1,1> - 2624938923U, // <5,3,1,2>: Cost 3 vext2 <1,2,5,3>, <1,2,5,3> - 2703198460U, // <5,3,1,3>: Cost 3 vext3 <3,1,3,5>, <3,1,3,5> - 3760867587U, // <5,3,1,4>: Cost 4 vext3 <0,4,1,5>, <3,1,4,3> - 2636219536U, // <5,3,1,5>: Cost 3 vext2 <3,1,5,3>, <1,5,3,7> - 3698681075U, // <5,3,1,6>: Cost 4 vext2 <1,2,5,3>, <1,6,5,7> - 2703493408U, // <5,3,1,7>: Cost 3 vext3 <3,1,7,5>, <3,1,7,5> - 2628920721U, // <5,3,1,u>: Cost 3 vext2 <1,u,5,3>, <1,u,5,3> - 3766765870U, // <5,3,2,0>: Cost 4 vext3 <1,4,0,5>, <3,2,0,1> - 3698681379U, // <5,3,2,1>: Cost 4 vext2 <1,2,5,3>, <2,1,3,5> - 3760867649U, // <5,3,2,2>: Cost 4 vext3 <0,4,1,5>, <3,2,2,2> - 2698627404U, // <5,3,2,3>: Cost 3 vext3 <2,3,4,5>, <3,2,3,4> - 2703935830U, // <5,3,2,4>: Cost 3 vext3 <3,2,4,5>, <3,2,4,5> - 2698627422U, // <5,3,2,5>: Cost 3 vext3 <2,3,4,5>, <3,2,5,4> - 3760867686U, // <5,3,2,6>: Cost 4 vext3 <0,4,1,5>, <3,2,6,3> - 3769788783U, // <5,3,2,7>: Cost 4 vext3 <1,u,5,5>, <3,2,7,3> - 2701945209U, // <5,3,2,u>: Cost 3 vext3 <2,u,4,5>, <3,2,u,4> - 3760867711U, // <5,3,3,0>: Cost 4 vext3 <0,4,1,5>, <3,3,0,1> - 2636220684U, // <5,3,3,1>: Cost 3 vext2 <3,1,5,3>, <3,1,5,3> - 3772369298U, // <5,3,3,2>: Cost 4 vext3 <2,3,4,5>, <3,3,2,2> - 2687125916U, // <5,3,3,3>: Cost 3 vext3 <0,4,1,5>, <3,3,3,3> - 2704599463U, // <5,3,3,4>: Cost 3 vext3 <3,3,4,5>, <3,3,4,5> - 2704673200U, // <5,3,3,5>: Cost 3 vext3 <3,3,5,5>, <3,3,5,5> - 3709962935U, // <5,3,3,6>: Cost 4 vext2 <3,1,5,3>, <3,6,7,7> - 3772369346U, // <5,3,3,7>: Cost 4 vext3 <2,3,4,5>, <3,3,7,5> - 2704894411U, // <5,3,3,u>: Cost 3 vext3 <3,3,u,5>, <3,3,u,5> - 2704968148U, // <5,3,4,0>: Cost 3 vext3 <3,4,0,5>, <3,4,0,5> - 3698682850U, // <5,3,4,1>: Cost 4 vext2 <1,2,5,3>, <4,1,5,0> - 2642857014U, // <5,3,4,2>: Cost 3 vext2 <4,2,5,3>, <4,2,5,3> - 2705189359U, // <5,3,4,3>: Cost 3 vext3 <3,4,3,5>, <3,4,3,5> - 2705263096U, // <5,3,4,4>: Cost 3 vext3 <3,4,4,5>, <3,4,4,5> - 2685946370U, // <5,3,4,5>: Cost 3 vext3 <0,2,3,5>, <3,4,5,6> - 3779152394U, // <5,3,4,6>: Cost 4 vext3 <3,4,6,5>, <3,4,6,5> - 2236377699U, // <5,3,4,7>: Cost 3 vrev <3,5,7,4> - 2687126045U, // <5,3,4,u>: Cost 3 vext3 <0,4,1,5>, <3,4,u,6> - 2571632742U, // <5,3,5,0>: Cost 3 vext1 <3,5,3,5>, LHS - 2559689870U, // <5,3,5,1>: Cost 3 vext1 <1,5,3,5>, <1,5,3,5> - 2571634382U, // <5,3,5,2>: Cost 3 vext1 <3,5,3,5>, <2,3,4,5> - 2571635264U, // <5,3,5,3>: Cost 3 vext1 <3,5,3,5>, <3,5,3,5> - 2571636022U, // <5,3,5,4>: Cost 3 vext1 <3,5,3,5>, RHS - 2559692804U, // <5,3,5,5>: Cost 3 vext1 <1,5,3,5>, <5,5,5,5> - 3720581218U, // <5,3,5,6>: Cost 4 vext2 <4,u,5,3>, <5,6,7,0> - 2236385892U, // <5,3,5,7>: Cost 3 vrev <3,5,7,5> - 2571638574U, // <5,3,5,u>: Cost 3 vext1 <3,5,3,5>, LHS - 2565668966U, // <5,3,6,0>: Cost 3 vext1 <2,5,3,6>, LHS - 3633439887U, // <5,3,6,1>: Cost 4 vext1 <1,5,3,6>, <1,5,3,6> - 2565670760U, // <5,3,6,2>: Cost 3 vext1 <2,5,3,6>, <2,5,3,6> - 2565671426U, // <5,3,6,3>: Cost 3 vext1 <2,5,3,6>, <3,4,5,6> - 2565672246U, // <5,3,6,4>: Cost 3 vext1 <2,5,3,6>, RHS - 3639414630U, // <5,3,6,5>: Cost 4 vext1 <2,5,3,6>, <5,3,6,0> - 4047521640U, // <5,3,6,6>: Cost 4 vzipr <3,4,5,6>, <2,5,3,6> - 2725169844U, // <5,3,6,7>: Cost 3 vext3 <6,7,4,5>, <3,6,7,4> - 2565674798U, // <5,3,6,u>: Cost 3 vext1 <2,5,3,6>, LHS - 1485963366U, // <5,3,7,0>: Cost 2 vext1 <1,5,3,7>, LHS - 1485964432U, // <5,3,7,1>: Cost 2 vext1 <1,5,3,7>, <1,5,3,7> - 2559706728U, // <5,3,7,2>: Cost 3 vext1 <1,5,3,7>, <2,2,2,2> - 2559707286U, // <5,3,7,3>: Cost 3 vext1 <1,5,3,7>, <3,0,1,2> - 1485966646U, // <5,3,7,4>: Cost 2 vext1 <1,5,3,7>, RHS - 2559708880U, // <5,3,7,5>: Cost 3 vext1 <1,5,3,7>, <5,1,7,3> - 2601513466U, // <5,3,7,6>: Cost 3 vext1 , <6,2,7,3> - 3114714112U, // <5,3,7,7>: Cost 3 vtrnr RHS, <1,3,5,7> - 1485969198U, // <5,3,7,u>: Cost 2 vext1 <1,5,3,7>, LHS - 1485971558U, // <5,3,u,0>: Cost 2 vext1 <1,5,3,u>, LHS - 1485972625U, // <5,3,u,1>: Cost 2 vext1 <1,5,3,u>, <1,5,3,u> - 2559714920U, // <5,3,u,2>: Cost 3 vext1 <1,5,3,u>, <2,2,2,2> - 2559715478U, // <5,3,u,3>: Cost 3 vext1 <1,5,3,u>, <3,0,1,2> - 1485974838U, // <5,3,u,4>: Cost 2 vext1 <1,5,3,u>, RHS - 2687126342U, // <5,3,u,5>: Cost 3 vext3 <0,4,1,5>, <3,u,5,6> - 2601521658U, // <5,3,u,6>: Cost 3 vext1 , <6,2,7,3> - 2236410471U, // <5,3,u,7>: Cost 3 vrev <3,5,7,u> - 1485977390U, // <5,3,u,u>: Cost 2 vext1 <1,5,3,u>, LHS - 3627491430U, // <5,4,0,0>: Cost 4 vext1 <0,5,4,0>, LHS - 2636890214U, // <5,4,0,1>: Cost 3 vext2 <3,2,5,4>, LHS - 3703333028U, // <5,4,0,2>: Cost 4 vext2 <2,0,5,4>, <0,2,0,2> - 3782249348U, // <5,4,0,3>: Cost 4 vext3 <4,0,3,5>, <4,0,3,5> - 2642198866U, // <5,4,0,4>: Cost 3 vext2 <4,1,5,4>, <0,4,1,5> - 2687126418U, // <5,4,0,5>: Cost 3 vext3 <0,4,1,5>, <4,0,5,1> - 2242243887U, // <5,4,0,6>: Cost 3 vrev <4,5,6,0> - 3316059448U, // <5,4,0,7>: Cost 4 vrev <4,5,7,0> - 2636890781U, // <5,4,0,u>: Cost 3 vext2 <3,2,5,4>, LHS - 2241809658U, // <5,4,1,0>: Cost 3 vrev <4,5,0,1> - 3698025307U, // <5,4,1,1>: Cost 4 vext2 <1,1,5,4>, <1,1,5,4> - 3698688940U, // <5,4,1,2>: Cost 4 vext2 <1,2,5,4>, <1,2,5,4> - 3698689024U, // <5,4,1,3>: Cost 4 vext2 <1,2,5,4>, <1,3,5,7> - 3700016206U, // <5,4,1,4>: Cost 4 vext2 <1,4,5,4>, <1,4,5,4> - 2687126498U, // <5,4,1,5>: Cost 3 vext3 <0,4,1,5>, <4,1,5,0> - 3760868336U, // <5,4,1,6>: Cost 4 vext3 <0,4,1,5>, <4,1,6,5> - 3316067641U, // <5,4,1,7>: Cost 4 vrev <4,5,7,1> - 2242399554U, // <5,4,1,u>: Cost 3 vrev <4,5,u,1> - 3703334371U, // <5,4,2,0>: Cost 4 vext2 <2,0,5,4>, <2,0,5,4> - 3703998004U, // <5,4,2,1>: Cost 4 vext2 <2,1,5,4>, <2,1,5,4> - 3704661637U, // <5,4,2,2>: Cost 4 vext2 <2,2,5,4>, <2,2,5,4> - 2636891854U, // <5,4,2,3>: Cost 3 vext2 <3,2,5,4>, <2,3,4,5> - 3705988903U, // <5,4,2,4>: Cost 4 vext2 <2,4,5,4>, <2,4,5,4> - 2698628150U, // <5,4,2,5>: Cost 3 vext3 <2,3,4,5>, <4,2,5,3> - 3760868415U, // <5,4,2,6>: Cost 4 vext3 <0,4,1,5>, <4,2,6,3> - 3783871562U, // <5,4,2,7>: Cost 4 vext3 <4,2,7,5>, <4,2,7,5> - 2666752099U, // <5,4,2,u>: Cost 3 vext2 , <2,u,4,5> - 3639459942U, // <5,4,3,0>: Cost 4 vext1 <2,5,4,3>, LHS - 3709970701U, // <5,4,3,1>: Cost 4 vext2 <3,1,5,4>, <3,1,5,4> - 2636892510U, // <5,4,3,2>: Cost 3 vext2 <3,2,5,4>, <3,2,5,4> - 3710634396U, // <5,4,3,3>: Cost 4 vext2 <3,2,5,4>, <3,3,3,3> - 2638219776U, // <5,4,3,4>: Cost 3 vext2 <3,4,5,4>, <3,4,5,4> - 3766987908U, // <5,4,3,5>: Cost 4 vext3 <1,4,3,5>, <4,3,5,0> - 2710719634U, // <5,4,3,6>: Cost 3 vext3 <4,3,6,5>, <4,3,6,5> - 3914097664U, // <5,4,3,7>: Cost 4 vuzpr <3,5,7,4>, <1,3,5,7> - 2640874308U, // <5,4,3,u>: Cost 3 vext2 <3,u,5,4>, <3,u,5,4> - 2583642214U, // <5,4,4,0>: Cost 3 vext1 <5,5,4,4>, LHS - 2642201574U, // <5,4,4,1>: Cost 3 vext2 <4,1,5,4>, <4,1,5,4> - 3710635062U, // <5,4,4,2>: Cost 4 vext2 <3,2,5,4>, <4,2,5,3> - 3717270664U, // <5,4,4,3>: Cost 4 vext2 <4,3,5,4>, <4,3,5,4> - 2713963728U, // <5,4,4,4>: Cost 3 vext3 <4,u,5,5>, <4,4,4,4> - 1637567706U, // <5,4,4,5>: Cost 2 vext3 <4,4,5,5>, <4,4,5,5> - 2242276659U, // <5,4,4,6>: Cost 3 vrev <4,5,6,4> - 2646183372U, // <5,4,4,7>: Cost 3 vext2 <4,7,5,4>, <4,7,5,4> - 1637788917U, // <5,4,4,u>: Cost 2 vext3 <4,4,u,5>, <4,4,u,5> - 2559762534U, // <5,4,5,0>: Cost 3 vext1 <1,5,4,5>, LHS - 2559763607U, // <5,4,5,1>: Cost 3 vext1 <1,5,4,5>, <1,5,4,5> - 2698628366U, // <5,4,5,2>: Cost 3 vext3 <2,3,4,5>, <4,5,2,3> - 3633506454U, // <5,4,5,3>: Cost 4 vext1 <1,5,4,5>, <3,0,1,2> - 2559765814U, // <5,4,5,4>: Cost 3 vext1 <1,5,4,5>, RHS - 2583654395U, // <5,4,5,5>: Cost 3 vext1 <5,5,4,5>, <5,5,4,5> - 1613385014U, // <5,4,5,6>: Cost 2 vext3 <0,4,1,5>, RHS - 3901639990U, // <5,4,5,7>: Cost 4 vuzpr <1,5,0,4>, RHS - 1613385032U, // <5,4,5,u>: Cost 2 vext3 <0,4,1,5>, RHS - 2559770726U, // <5,4,6,0>: Cost 3 vext1 <1,5,4,6>, LHS - 2559771648U, // <5,4,6,1>: Cost 3 vext1 <1,5,4,6>, <1,3,5,7> - 3633514088U, // <5,4,6,2>: Cost 4 vext1 <1,5,4,6>, <2,2,2,2> - 2571717122U, // <5,4,6,3>: Cost 3 vext1 <3,5,4,6>, <3,4,5,6> - 2559774006U, // <5,4,6,4>: Cost 3 vext1 <1,5,4,6>, RHS - 2712636796U, // <5,4,6,5>: Cost 3 vext3 <4,6,5,5>, <4,6,5,5> - 3760868743U, // <5,4,6,6>: Cost 4 vext3 <0,4,1,5>, <4,6,6,7> - 2712784270U, // <5,4,6,7>: Cost 3 vext3 <4,6,7,5>, <4,6,7,5> - 2559776558U, // <5,4,6,u>: Cost 3 vext1 <1,5,4,6>, LHS - 2565750886U, // <5,4,7,0>: Cost 3 vext1 <2,5,4,7>, LHS - 2565751706U, // <5,4,7,1>: Cost 3 vext1 <2,5,4,7>, <1,2,3,4> - 2565752690U, // <5,4,7,2>: Cost 3 vext1 <2,5,4,7>, <2,5,4,7> - 2571725387U, // <5,4,7,3>: Cost 3 vext1 <3,5,4,7>, <3,5,4,7> - 2565754166U, // <5,4,7,4>: Cost 3 vext1 <2,5,4,7>, RHS - 3114713426U, // <5,4,7,5>: Cost 3 vtrnr RHS, <0,4,1,5> - 94817590U, // <5,4,7,6>: Cost 1 vrev RHS - 2595616175U, // <5,4,7,7>: Cost 3 vext1 <7,5,4,7>, <7,5,4,7> - 94965064U, // <5,4,7,u>: Cost 1 vrev RHS - 2559787110U, // <5,4,u,0>: Cost 3 vext1 <1,5,4,u>, LHS - 2559788186U, // <5,4,u,1>: Cost 3 vext1 <1,5,4,u>, <1,5,4,u> - 2242014483U, // <5,4,u,2>: Cost 3 vrev <4,5,2,u> - 2667419628U, // <5,4,u,3>: Cost 3 vext2 , - 2559790390U, // <5,4,u,4>: Cost 3 vext1 <1,5,4,u>, RHS - 1640222238U, // <5,4,u,5>: Cost 2 vext3 <4,u,5,5>, <4,u,5,5> - 94825783U, // <5,4,u,6>: Cost 1 vrev RHS - 2714111536U, // <5,4,u,7>: Cost 3 vext3 <4,u,7,5>, <4,u,7,5> - 94973257U, // <5,4,u,u>: Cost 1 vrev RHS - 2646851584U, // <5,5,0,0>: Cost 3 vext2 <4,u,5,5>, <0,0,0,0> - 1573109862U, // <5,5,0,1>: Cost 2 vext2 <4,u,5,5>, LHS - 2646851748U, // <5,5,0,2>: Cost 3 vext2 <4,u,5,5>, <0,2,0,2> - 3760279130U, // <5,5,0,3>: Cost 4 vext3 <0,3,2,5>, <5,0,3,2> - 2687127138U, // <5,5,0,4>: Cost 3 vext3 <0,4,1,5>, <5,0,4,1> - 2248142847U, // <5,5,0,5>: Cost 3 vrev <5,5,5,0> - 3720593910U, // <5,5,0,6>: Cost 4 vext2 <4,u,5,5>, <0,6,1,7> - 4182502710U, // <5,5,0,7>: Cost 4 vtrnr <3,5,7,0>, RHS - 1573110429U, // <5,5,0,u>: Cost 2 vext2 <4,u,5,5>, LHS - 2646852342U, // <5,5,1,0>: Cost 3 vext2 <4,u,5,5>, <1,0,3,2> - 2624291676U, // <5,5,1,1>: Cost 3 vext2 <1,1,5,5>, <1,1,5,5> - 2646852502U, // <5,5,1,2>: Cost 3 vext2 <4,u,5,5>, <1,2,3,0> - 2646852568U, // <5,5,1,3>: Cost 3 vext2 <4,u,5,5>, <1,3,1,3> - 2715217591U, // <5,5,1,4>: Cost 3 vext3 <5,1,4,5>, <5,1,4,5> - 2628936848U, // <5,5,1,5>: Cost 3 vext2 <1,u,5,5>, <1,5,3,7> - 3698033907U, // <5,5,1,6>: Cost 4 vext2 <1,1,5,5>, <1,6,5,7> - 2713964240U, // <5,5,1,7>: Cost 3 vext3 <4,u,5,5>, <5,1,7,3> - 2628937107U, // <5,5,1,u>: Cost 3 vext2 <1,u,5,5>, <1,u,5,5> - 3645497446U, // <5,5,2,0>: Cost 4 vext1 <3,5,5,2>, LHS - 3760869099U, // <5,5,2,1>: Cost 4 vext3 <0,4,1,5>, <5,2,1,3> - 2646853224U, // <5,5,2,2>: Cost 3 vext2 <4,u,5,5>, <2,2,2,2> - 2698628862U, // <5,5,2,3>: Cost 3 vext3 <2,3,4,5>, <5,2,3,4> - 3772370694U, // <5,5,2,4>: Cost 4 vext3 <2,3,4,5>, <5,2,4,3> - 2713964303U, // <5,5,2,5>: Cost 3 vext3 <4,u,5,5>, <5,2,5,3> - 2646853562U, // <5,5,2,6>: Cost 3 vext2 <4,u,5,5>, <2,6,3,7> - 4038198272U, // <5,5,2,7>: Cost 4 vzipr <1,u,5,2>, <1,3,5,7> - 2701946667U, // <5,5,2,u>: Cost 3 vext3 <2,u,4,5>, <5,2,u,4> - 2646853782U, // <5,5,3,0>: Cost 3 vext2 <4,u,5,5>, <3,0,1,2> - 3698034922U, // <5,5,3,1>: Cost 4 vext2 <1,1,5,5>, <3,1,1,5> - 3702679919U, // <5,5,3,2>: Cost 4 vext2 <1,u,5,5>, <3,2,7,3> - 2637564336U, // <5,5,3,3>: Cost 3 vext2 <3,3,5,5>, <3,3,5,5> - 2646854146U, // <5,5,3,4>: Cost 3 vext2 <4,u,5,5>, <3,4,5,6> - 2638891602U, // <5,5,3,5>: Cost 3 vext2 <3,5,5,5>, <3,5,5,5> - 3702680247U, // <5,5,3,6>: Cost 4 vext2 <1,u,5,5>, <3,6,7,7> - 3702680259U, // <5,5,3,7>: Cost 4 vext2 <1,u,5,5>, <3,7,0,1> - 2646854430U, // <5,5,3,u>: Cost 3 vext2 <4,u,5,5>, <3,u,1,2> - 2646854546U, // <5,5,4,0>: Cost 3 vext2 <4,u,5,5>, <4,0,5,1> - 2642209767U, // <5,5,4,1>: Cost 3 vext2 <4,1,5,5>, <4,1,5,5> - 3711306806U, // <5,5,4,2>: Cost 4 vext2 <3,3,5,5>, <4,2,5,3> - 3645516369U, // <5,5,4,3>: Cost 4 vext1 <3,5,5,4>, <3,5,5,4> - 1570458842U, // <5,5,4,4>: Cost 2 vext2 <4,4,5,5>, <4,4,5,5> - 1573113142U, // <5,5,4,5>: Cost 2 vext2 <4,u,5,5>, RHS - 2645527932U, // <5,5,4,6>: Cost 3 vext2 <4,6,5,5>, <4,6,5,5> - 2713964486U, // <5,5,4,7>: Cost 3 vext3 <4,u,5,5>, <5,4,7,6> - 1573113374U, // <5,5,4,u>: Cost 2 vext2 <4,u,5,5>, <4,u,5,5> - 1509982310U, // <5,5,5,0>: Cost 2 vext1 <5,5,5,5>, LHS - 2646855376U, // <5,5,5,1>: Cost 3 vext2 <4,u,5,5>, <5,1,7,3> - 2583725672U, // <5,5,5,2>: Cost 3 vext1 <5,5,5,5>, <2,2,2,2> - 2583726230U, // <5,5,5,3>: Cost 3 vext1 <5,5,5,5>, <3,0,1,2> - 1509985590U, // <5,5,5,4>: Cost 2 vext1 <5,5,5,5>, RHS - 229035318U, // <5,5,5,5>: Cost 1 vdup1 RHS - 2646855778U, // <5,5,5,6>: Cost 3 vext2 <4,u,5,5>, <5,6,7,0> - 2646855848U, // <5,5,5,7>: Cost 3 vext2 <4,u,5,5>, <5,7,5,7> - 229035318U, // <5,5,5,u>: Cost 1 vdup1 RHS - 2577760358U, // <5,5,6,0>: Cost 3 vext1 <4,5,5,6>, LHS - 3633587361U, // <5,5,6,1>: Cost 4 vext1 <1,5,5,6>, <1,5,5,6> - 2646856186U, // <5,5,6,2>: Cost 3 vext2 <4,u,5,5>, <6,2,7,3> - 3633588738U, // <5,5,6,3>: Cost 4 vext1 <1,5,5,6>, <3,4,5,6> - 2718535756U, // <5,5,6,4>: Cost 3 vext3 <5,6,4,5>, <5,6,4,5> - 2644202223U, // <5,5,6,5>: Cost 3 vext2 <4,4,5,5>, <6,5,7,5> - 2973780482U, // <5,5,6,6>: Cost 3 vzipr <3,4,5,6>, <3,4,5,6> - 2646856526U, // <5,5,6,7>: Cost 3 vext2 <4,u,5,5>, <6,7,0,1> - 2646856607U, // <5,5,6,u>: Cost 3 vext2 <4,u,5,5>, <6,u,0,1> - 2571796582U, // <5,5,7,0>: Cost 3 vext1 <3,5,5,7>, LHS - 3633595392U, // <5,5,7,1>: Cost 4 vext1 <1,5,5,7>, <1,3,5,7> - 2571798222U, // <5,5,7,2>: Cost 3 vext1 <3,5,5,7>, <2,3,4,5> - 2571799124U, // <5,5,7,3>: Cost 3 vext1 <3,5,5,7>, <3,5,5,7> - 2571799862U, // <5,5,7,4>: Cost 3 vext1 <3,5,5,7>, RHS - 3114717188U, // <5,5,7,5>: Cost 3 vtrnr RHS, <5,5,5,5> - 4034923010U, // <5,5,7,6>: Cost 4 vzipr <1,3,5,7>, <3,4,5,6> - 2040974646U, // <5,5,7,7>: Cost 2 vtrnr RHS, RHS - 2040974647U, // <5,5,7,u>: Cost 2 vtrnr RHS, RHS - 1509982310U, // <5,5,u,0>: Cost 2 vext1 <5,5,5,5>, LHS - 1573115694U, // <5,5,u,1>: Cost 2 vext2 <4,u,5,5>, LHS - 2571806414U, // <5,5,u,2>: Cost 3 vext1 <3,5,5,u>, <2,3,4,5> - 2571807317U, // <5,5,u,3>: Cost 3 vext1 <3,5,5,u>, <3,5,5,u> - 1509985590U, // <5,5,u,4>: Cost 2 vext1 <5,5,5,5>, RHS - 229035318U, // <5,5,u,5>: Cost 1 vdup1 RHS - 2646857936U, // <5,5,u,6>: Cost 3 vext2 <4,u,5,5>, - 2040982838U, // <5,5,u,7>: Cost 2 vtrnr RHS, RHS - 229035318U, // <5,5,u,u>: Cost 1 vdup1 RHS - 2638233600U, // <5,6,0,0>: Cost 3 vext2 <3,4,5,6>, <0,0,0,0> - 1564491878U, // <5,6,0,1>: Cost 2 vext2 <3,4,5,6>, LHS - 2632261796U, // <5,6,0,2>: Cost 3 vext2 <2,4,5,6>, <0,2,0,2> - 2638233856U, // <5,6,0,3>: Cost 3 vext2 <3,4,5,6>, <0,3,1,4> - 2638233938U, // <5,6,0,4>: Cost 3 vext2 <3,4,5,6>, <0,4,1,5> - 3706003885U, // <5,6,0,5>: Cost 4 vext2 <2,4,5,6>, <0,5,2,6> - 3706003967U, // <5,6,0,6>: Cost 4 vext2 <2,4,5,6>, <0,6,2,7> - 4047473974U, // <5,6,0,7>: Cost 4 vzipr <3,4,5,0>, RHS - 1564492445U, // <5,6,0,u>: Cost 2 vext2 <3,4,5,6>, LHS - 2638234358U, // <5,6,1,0>: Cost 3 vext2 <3,4,5,6>, <1,0,3,2> - 2638234420U, // <5,6,1,1>: Cost 3 vext2 <3,4,5,6>, <1,1,1,1> - 2638234518U, // <5,6,1,2>: Cost 3 vext2 <3,4,5,6>, <1,2,3,0> - 2638234584U, // <5,6,1,3>: Cost 3 vext2 <3,4,5,6>, <1,3,1,3> - 2626290768U, // <5,6,1,4>: Cost 3 vext2 <1,4,5,6>, <1,4,5,6> - 2638234768U, // <5,6,1,5>: Cost 3 vext2 <3,4,5,6>, <1,5,3,7> - 3700032719U, // <5,6,1,6>: Cost 4 vext2 <1,4,5,6>, <1,6,1,7> - 2982366518U, // <5,6,1,7>: Cost 3 vzipr <4,u,5,1>, RHS - 2628945300U, // <5,6,1,u>: Cost 3 vext2 <1,u,5,6>, <1,u,5,6> - 3706004925U, // <5,6,2,0>: Cost 4 vext2 <2,4,5,6>, <2,0,1,2> - 3711976966U, // <5,6,2,1>: Cost 4 vext2 <3,4,5,6>, <2,1,0,3> - 2638235240U, // <5,6,2,2>: Cost 3 vext2 <3,4,5,6>, <2,2,2,2> - 2638235302U, // <5,6,2,3>: Cost 3 vext2 <3,4,5,6>, <2,3,0,1> - 2632263465U, // <5,6,2,4>: Cost 3 vext2 <2,4,5,6>, <2,4,5,6> - 2638235496U, // <5,6,2,5>: Cost 3 vext2 <3,4,5,6>, <2,5,3,6> - 2638235578U, // <5,6,2,6>: Cost 3 vext2 <3,4,5,6>, <2,6,3,7> - 2713965050U, // <5,6,2,7>: Cost 3 vext3 <4,u,5,5>, <6,2,7,3> - 2634917997U, // <5,6,2,u>: Cost 3 vext2 <2,u,5,6>, <2,u,5,6> - 2638235798U, // <5,6,3,0>: Cost 3 vext2 <3,4,5,6>, <3,0,1,2> - 3711977695U, // <5,6,3,1>: Cost 4 vext2 <3,4,5,6>, <3,1,0,3> - 3710650720U, // <5,6,3,2>: Cost 4 vext2 <3,2,5,6>, <3,2,5,6> - 2638236060U, // <5,6,3,3>: Cost 3 vext2 <3,4,5,6>, <3,3,3,3> - 1564494338U, // <5,6,3,4>: Cost 2 vext2 <3,4,5,6>, <3,4,5,6> - 2638236234U, // <5,6,3,5>: Cost 3 vext2 <3,4,5,6>, <3,5,4,6> - 3711978104U, // <5,6,3,6>: Cost 4 vext2 <3,4,5,6>, <3,6,0,7> - 4034227510U, // <5,6,3,7>: Cost 4 vzipr <1,2,5,3>, RHS - 1567148870U, // <5,6,3,u>: Cost 2 vext2 <3,u,5,6>, <3,u,5,6> - 2577817702U, // <5,6,4,0>: Cost 3 vext1 <4,5,6,4>, LHS - 3700034544U, // <5,6,4,1>: Cost 4 vext2 <1,4,5,6>, <4,1,6,5> - 2723033713U, // <5,6,4,2>: Cost 3 vext3 <6,4,2,5>, <6,4,2,5> - 2638236818U, // <5,6,4,3>: Cost 3 vext2 <3,4,5,6>, <4,3,6,5> - 2644208859U, // <5,6,4,4>: Cost 3 vext2 <4,4,5,6>, <4,4,5,6> - 1564495158U, // <5,6,4,5>: Cost 2 vext2 <3,4,5,6>, RHS - 2645536125U, // <5,6,4,6>: Cost 3 vext2 <4,6,5,6>, <4,6,5,6> - 2723402398U, // <5,6,4,7>: Cost 3 vext3 <6,4,7,5>, <6,4,7,5> - 1564495401U, // <5,6,4,u>: Cost 2 vext2 <3,4,5,6>, RHS - 2577825894U, // <5,6,5,0>: Cost 3 vext1 <4,5,6,5>, LHS - 2662125264U, // <5,6,5,1>: Cost 3 vext2 <7,4,5,6>, <5,1,7,3> - 3775836867U, // <5,6,5,2>: Cost 4 vext3 <2,u,6,5>, <6,5,2,6> - 3711979343U, // <5,6,5,3>: Cost 4 vext2 <3,4,5,6>, <5,3,3,4> - 2650181556U, // <5,6,5,4>: Cost 3 vext2 <5,4,5,6>, <5,4,5,6> - 2662125572U, // <5,6,5,5>: Cost 3 vext2 <7,4,5,6>, <5,5,5,5> - 2638237732U, // <5,6,5,6>: Cost 3 vext2 <3,4,5,6>, <5,6,0,1> - 2982399286U, // <5,6,5,7>: Cost 3 vzipr <4,u,5,5>, RHS - 2982399287U, // <5,6,5,u>: Cost 3 vzipr <4,u,5,5>, RHS - 2583806054U, // <5,6,6,0>: Cost 3 vext1 <5,5,6,6>, LHS - 3711979910U, // <5,6,6,1>: Cost 4 vext2 <3,4,5,6>, <6,1,3,4> - 2662126074U, // <5,6,6,2>: Cost 3 vext2 <7,4,5,6>, <6,2,7,3> - 2583808514U, // <5,6,6,3>: Cost 3 vext1 <5,5,6,6>, <3,4,5,6> - 2583809334U, // <5,6,6,4>: Cost 3 vext1 <5,5,6,6>, RHS - 2583810062U, // <5,6,6,5>: Cost 3 vext1 <5,5,6,6>, <5,5,6,6> - 2638238520U, // <5,6,6,6>: Cost 3 vext2 <3,4,5,6>, <6,6,6,6> - 2973781302U, // <5,6,6,7>: Cost 3 vzipr <3,4,5,6>, RHS - 2973781303U, // <5,6,6,u>: Cost 3 vzipr <3,4,5,6>, RHS - 430358630U, // <5,6,7,0>: Cost 1 vext1 RHS, LHS - 1504101110U, // <5,6,7,1>: Cost 2 vext1 RHS, <1,0,3,2> - 1504101992U, // <5,6,7,2>: Cost 2 vext1 RHS, <2,2,2,2> - 1504102550U, // <5,6,7,3>: Cost 2 vext1 RHS, <3,0,1,2> - 430361910U, // <5,6,7,4>: Cost 1 vext1 RHS, RHS - 1504104390U, // <5,6,7,5>: Cost 2 vext1 RHS, <5,4,7,6> - 1504105272U, // <5,6,7,6>: Cost 2 vext1 RHS, <6,6,6,6> - 1504106092U, // <5,6,7,7>: Cost 2 vext1 RHS, <7,7,7,7> - 430364462U, // <5,6,7,u>: Cost 1 vext1 RHS, LHS - 430366822U, // <5,6,u,0>: Cost 1 vext1 RHS, LHS - 1564497710U, // <5,6,u,1>: Cost 2 vext2 <3,4,5,6>, LHS - 1504110184U, // <5,6,u,2>: Cost 2 vext1 RHS, <2,2,2,2> - 1504110742U, // <5,6,u,3>: Cost 2 vext1 RHS, <3,0,1,2> - 430370103U, // <5,6,u,4>: Cost 1 vext1 RHS, RHS - 1564498074U, // <5,6,u,5>: Cost 2 vext2 <3,4,5,6>, RHS - 1504113146U, // <5,6,u,6>: Cost 2 vext1 RHS, <6,2,7,3> - 1504113658U, // <5,6,u,7>: Cost 2 vext1 RHS, <7,0,1,2> - 430372654U, // <5,6,u,u>: Cost 1 vext1 RHS, LHS - 2625634304U, // <5,7,0,0>: Cost 3 vext2 <1,3,5,7>, <0,0,0,0> - 1551892582U, // <5,7,0,1>: Cost 2 vext2 <1,3,5,7>, LHS - 2625634468U, // <5,7,0,2>: Cost 3 vext2 <1,3,5,7>, <0,2,0,2> - 2571889247U, // <5,7,0,3>: Cost 3 vext1 <3,5,7,0>, <3,5,7,0> - 2625634642U, // <5,7,0,4>: Cost 3 vext2 <1,3,5,7>, <0,4,1,5> - 2595778728U, // <5,7,0,5>: Cost 3 vext1 <7,5,7,0>, <5,7,5,7> - 3699376639U, // <5,7,0,6>: Cost 4 vext2 <1,3,5,7>, <0,6,2,7> - 2260235715U, // <5,7,0,7>: Cost 3 vrev <7,5,7,0> - 1551893149U, // <5,7,0,u>: Cost 2 vext2 <1,3,5,7>, LHS - 2625635062U, // <5,7,1,0>: Cost 3 vext2 <1,3,5,7>, <1,0,3,2> - 2624308020U, // <5,7,1,1>: Cost 3 vext2 <1,1,5,7>, <1,1,1,1> - 2625635222U, // <5,7,1,2>: Cost 3 vext2 <1,3,5,7>, <1,2,3,0> - 1551893504U, // <5,7,1,3>: Cost 2 vext2 <1,3,5,7>, <1,3,5,7> - 2571898166U, // <5,7,1,4>: Cost 3 vext1 <3,5,7,1>, RHS - 2625635472U, // <5,7,1,5>: Cost 3 vext2 <1,3,5,7>, <1,5,3,7> - 2627626227U, // <5,7,1,6>: Cost 3 vext2 <1,6,5,7>, <1,6,5,7> - 3702031684U, // <5,7,1,7>: Cost 4 vext2 <1,7,5,7>, <1,7,5,7> - 1555211669U, // <5,7,1,u>: Cost 2 vext2 <1,u,5,7>, <1,u,5,7> - 2629617126U, // <5,7,2,0>: Cost 3 vext2 <2,0,5,7>, <2,0,5,7> - 3699377670U, // <5,7,2,1>: Cost 4 vext2 <1,3,5,7>, <2,1,0,3> - 2625635944U, // <5,7,2,2>: Cost 3 vext2 <1,3,5,7>, <2,2,2,2> - 2625636006U, // <5,7,2,3>: Cost 3 vext2 <1,3,5,7>, <2,3,0,1> - 2632271658U, // <5,7,2,4>: Cost 3 vext2 <2,4,5,7>, <2,4,5,7> - 2625636201U, // <5,7,2,5>: Cost 3 vext2 <1,3,5,7>, <2,5,3,7> - 2625636282U, // <5,7,2,6>: Cost 3 vext2 <1,3,5,7>, <2,6,3,7> - 3708004381U, // <5,7,2,7>: Cost 4 vext2 <2,7,5,7>, <2,7,5,7> - 2625636411U, // <5,7,2,u>: Cost 3 vext2 <1,3,5,7>, <2,u,0,1> - 2625636502U, // <5,7,3,0>: Cost 3 vext2 <1,3,5,7>, <3,0,1,2> - 2625636604U, // <5,7,3,1>: Cost 3 vext2 <1,3,5,7>, <3,1,3,5> - 3699378478U, // <5,7,3,2>: Cost 4 vext2 <1,3,5,7>, <3,2,0,1> - 2625636764U, // <5,7,3,3>: Cost 3 vext2 <1,3,5,7>, <3,3,3,3> - 2625636866U, // <5,7,3,4>: Cost 3 vext2 <1,3,5,7>, <3,4,5,6> - 2625636959U, // <5,7,3,5>: Cost 3 vext2 <1,3,5,7>, <3,5,7,0> - 3699378808U, // <5,7,3,6>: Cost 4 vext2 <1,3,5,7>, <3,6,0,7> - 2640235254U, // <5,7,3,7>: Cost 3 vext2 <3,7,5,7>, <3,7,5,7> - 2625637150U, // <5,7,3,u>: Cost 3 vext2 <1,3,5,7>, <3,u,1,2> - 2571919462U, // <5,7,4,0>: Cost 3 vext1 <3,5,7,4>, LHS - 2571920384U, // <5,7,4,1>: Cost 3 vext1 <3,5,7,4>, <1,3,5,7> - 3699379260U, // <5,7,4,2>: Cost 4 vext2 <1,3,5,7>, <4,2,6,0> - 2571922019U, // <5,7,4,3>: Cost 3 vext1 <3,5,7,4>, <3,5,7,4> - 2571922742U, // <5,7,4,4>: Cost 3 vext1 <3,5,7,4>, RHS - 1551895862U, // <5,7,4,5>: Cost 2 vext2 <1,3,5,7>, RHS - 2846277980U, // <5,7,4,6>: Cost 3 vuzpr RHS, <0,4,2,6> - 2646207951U, // <5,7,4,7>: Cost 3 vext2 <4,7,5,7>, <4,7,5,7> - 1551896105U, // <5,7,4,u>: Cost 2 vext2 <1,3,5,7>, RHS - 2583871590U, // <5,7,5,0>: Cost 3 vext1 <5,5,7,5>, LHS - 2652180176U, // <5,7,5,1>: Cost 3 vext2 <5,7,5,7>, <5,1,7,3> - 2625638177U, // <5,7,5,2>: Cost 3 vext2 <1,3,5,7>, <5,2,7,3> - 2625638262U, // <5,7,5,3>: Cost 3 vext2 <1,3,5,7>, <5,3,7,7> - 2583874870U, // <5,7,5,4>: Cost 3 vext1 <5,5,7,5>, RHS - 2846281732U, // <5,7,5,5>: Cost 3 vuzpr RHS, <5,5,5,5> - 2651517015U, // <5,7,5,6>: Cost 3 vext2 <5,6,5,7>, <5,6,5,7> - 1772539190U, // <5,7,5,7>: Cost 2 vuzpr RHS, RHS - 1772539191U, // <5,7,5,u>: Cost 2 vuzpr RHS, RHS - 2846281826U, // <5,7,6,0>: Cost 3 vuzpr RHS, <5,6,7,0> - 3699380615U, // <5,7,6,1>: Cost 4 vext2 <1,3,5,7>, <6,1,3,5> - 2846281108U, // <5,7,6,2>: Cost 3 vuzpr RHS, <4,6,u,2> - 2589854210U, // <5,7,6,3>: Cost 3 vext1 <6,5,7,6>, <3,4,5,6> - 2846281830U, // <5,7,6,4>: Cost 3 vuzpr RHS, <5,6,7,4> - 2725467658U, // <5,7,6,5>: Cost 3 vext3 <6,7,u,5>, <7,6,5,u> - 2846281076U, // <5,7,6,6>: Cost 3 vuzpr RHS, <4,6,4,6> - 2846279610U, // <5,7,6,7>: Cost 3 vuzpr RHS, <2,6,3,7> - 2846279611U, // <5,7,6,u>: Cost 3 vuzpr RHS, <2,6,3,u> - 1510146150U, // <5,7,7,0>: Cost 2 vext1 <5,5,7,7>, LHS - 2846282574U, // <5,7,7,1>: Cost 3 vuzpr RHS, <6,7,0,1> - 2583889512U, // <5,7,7,2>: Cost 3 vext1 <5,5,7,7>, <2,2,2,2> - 2846281919U, // <5,7,7,3>: Cost 3 vuzpr RHS, <5,7,u,3> - 1510149430U, // <5,7,7,4>: Cost 2 vext1 <5,5,7,7>, RHS - 1510150168U, // <5,7,7,5>: Cost 2 vext1 <5,5,7,7>, <5,5,7,7> - 2583892474U, // <5,7,7,6>: Cost 3 vext1 <5,5,7,7>, <6,2,7,3> - 2625640044U, // <5,7,7,7>: Cost 3 vext2 <1,3,5,7>, <7,7,7,7> - 1510151982U, // <5,7,7,u>: Cost 2 vext1 <5,5,7,7>, LHS - 1510154342U, // <5,7,u,0>: Cost 2 vext1 <5,5,7,u>, LHS - 1551898414U, // <5,7,u,1>: Cost 2 vext2 <1,3,5,7>, LHS - 2625640325U, // <5,7,u,2>: Cost 3 vext2 <1,3,5,7>, - 1772536477U, // <5,7,u,3>: Cost 2 vuzpr RHS, LHS - 1510157622U, // <5,7,u,4>: Cost 2 vext1 <5,5,7,u>, RHS - 1551898778U, // <5,7,u,5>: Cost 2 vext2 <1,3,5,7>, RHS - 2625640656U, // <5,7,u,6>: Cost 3 vext2 <1,3,5,7>, - 1772539433U, // <5,7,u,7>: Cost 2 vuzpr RHS, RHS - 1551898981U, // <5,7,u,u>: Cost 2 vext2 <1,3,5,7>, LHS - 2625642496U, // <5,u,0,0>: Cost 3 vext2 <1,3,5,u>, <0,0,0,0> - 1551900774U, // <5,u,0,1>: Cost 2 vext2 <1,3,5,u>, LHS - 2625642660U, // <5,u,0,2>: Cost 3 vext2 <1,3,5,u>, <0,2,0,2> - 2698630885U, // <5,u,0,3>: Cost 3 vext3 <2,3,4,5>, - 2687129325U, // <5,u,0,4>: Cost 3 vext3 <0,4,1,5>, - 2689783542U, // <5,u,0,5>: Cost 3 vext3 <0,u,1,5>, - 2266134675U, // <5,u,0,6>: Cost 3 vrev - 2595853772U, // <5,u,0,7>: Cost 3 vext1 <7,5,u,0>, <7,5,u,0> - 1551901341U, // <5,u,0,u>: Cost 2 vext2 <1,3,5,u>, LHS - 2625643254U, // <5,u,1,0>: Cost 3 vext2 <1,3,5,u>, <1,0,3,2> - 2625643316U, // <5,u,1,1>: Cost 3 vext2 <1,3,5,u>, <1,1,1,1> - 1613387566U, // <5,u,1,2>: Cost 2 vext3 <0,4,1,5>, LHS - 1551901697U, // <5,u,1,3>: Cost 2 vext2 <1,3,5,u>, <1,3,5,u> - 2626307154U, // <5,u,1,4>: Cost 3 vext2 <1,4,5,u>, <1,4,5,u> - 2689783622U, // <5,u,1,5>: Cost 3 vext3 <0,u,1,5>, - 2627634420U, // <5,u,1,6>: Cost 3 vext2 <1,6,5,u>, <1,6,5,u> - 2982366536U, // <5,u,1,7>: Cost 3 vzipr <4,u,5,1>, RHS - 1613387620U, // <5,u,1,u>: Cost 2 vext3 <0,4,1,5>, LHS - 2846286742U, // <5,u,2,0>: Cost 3 vuzpr RHS, <1,2,3,0> - 2685796528U, // <5,u,2,1>: Cost 3 vext3 <0,2,1,5>, <0,2,1,5> - 2625644136U, // <5,u,2,2>: Cost 3 vext2 <1,3,5,u>, <2,2,2,2> - 2687129480U, // <5,u,2,3>: Cost 3 vext3 <0,4,1,5>, - 2632279851U, // <5,u,2,4>: Cost 3 vext2 <2,4,5,u>, <2,4,5,u> - 2625644394U, // <5,u,2,5>: Cost 3 vext2 <1,3,5,u>, <2,5,3,u> - 2625644474U, // <5,u,2,6>: Cost 3 vext2 <1,3,5,u>, <2,6,3,7> - 2713966508U, // <5,u,2,7>: Cost 3 vext3 <4,u,5,5>, - 2625644603U, // <5,u,2,u>: Cost 3 vext2 <1,3,5,u>, <2,u,0,1> - 2687129532U, // <5,u,3,0>: Cost 3 vext3 <0,4,1,5>, - 2636261649U, // <5,u,3,1>: Cost 3 vext2 <3,1,5,u>, <3,1,5,u> - 2636925282U, // <5,u,3,2>: Cost 3 vext2 <3,2,5,u>, <3,2,5,u> - 2625644956U, // <5,u,3,3>: Cost 3 vext2 <1,3,5,u>, <3,3,3,3> - 1564510724U, // <5,u,3,4>: Cost 2 vext2 <3,4,5,u>, <3,4,5,u> - 2625645160U, // <5,u,3,5>: Cost 3 vext2 <1,3,5,u>, <3,5,u,0> - 2734610422U, // <5,u,3,6>: Cost 3 vext3 , - 2640243447U, // <5,u,3,7>: Cost 3 vext2 <3,7,5,u>, <3,7,5,u> - 1567165256U, // <5,u,3,u>: Cost 2 vext2 <3,u,5,u>, <3,u,5,u> - 1567828889U, // <5,u,4,0>: Cost 2 vext2 <4,0,5,u>, <4,0,5,u> - 1661163546U, // <5,u,4,1>: Cost 2 vext3 , - 2734463012U, // <5,u,4,2>: Cost 3 vext3 , - 2698631212U, // <5,u,4,3>: Cost 3 vext3 <2,3,4,5>, - 1570458842U, // <5,u,4,4>: Cost 2 vext2 <4,4,5,5>, <4,4,5,5> - 1551904054U, // <5,u,4,5>: Cost 2 vext2 <1,3,5,u>, RHS - 2846286172U, // <5,u,4,6>: Cost 3 vuzpr RHS, <0,4,2,6> - 2646216144U, // <5,u,4,7>: Cost 3 vext2 <4,7,5,u>, <4,7,5,u> - 1551904297U, // <5,u,4,u>: Cost 2 vext2 <1,3,5,u>, RHS - 1509982310U, // <5,u,5,0>: Cost 2 vext1 <5,5,5,5>, LHS - 2560058555U, // <5,u,5,1>: Cost 3 vext1 <1,5,u,5>, <1,5,u,5> - 2698926194U, // <5,u,5,2>: Cost 3 vext3 <2,3,u,5>, - 2698631295U, // <5,u,5,3>: Cost 3 vext3 <2,3,4,5>, - 1509985590U, // <5,u,5,4>: Cost 2 vext1 <5,5,5,5>, RHS - 229035318U, // <5,u,5,5>: Cost 1 vdup1 RHS - 1613387930U, // <5,u,5,6>: Cost 2 vext3 <0,4,1,5>, RHS - 1772547382U, // <5,u,5,7>: Cost 2 vuzpr RHS, RHS - 229035318U, // <5,u,5,u>: Cost 1 vdup1 RHS - 2566037606U, // <5,u,6,0>: Cost 3 vext1 <2,5,u,6>, LHS - 2920044334U, // <5,u,6,1>: Cost 3 vzipl <5,6,7,0>, LHS - 2566039445U, // <5,u,6,2>: Cost 3 vext1 <2,5,u,6>, <2,5,u,6> - 2687129808U, // <5,u,6,3>: Cost 3 vext3 <0,4,1,5>, - 2566040886U, // <5,u,6,4>: Cost 3 vext1 <2,5,u,6>, RHS - 2920044698U, // <5,u,6,5>: Cost 3 vzipl <5,6,7,0>, RHS - 2846289268U, // <5,u,6,6>: Cost 3 vuzpr RHS, <4,6,4,6> - 2973781320U, // <5,u,6,7>: Cost 3 vzipr <3,4,5,6>, RHS - 2687129853U, // <5,u,6,u>: Cost 3 vext3 <0,4,1,5>, - 430506086U, // <5,u,7,0>: Cost 1 vext1 RHS, LHS - 1486333117U, // <5,u,7,1>: Cost 2 vext1 <1,5,u,7>, <1,5,u,7> - 1504249448U, // <5,u,7,2>: Cost 2 vext1 RHS, <2,2,2,2> - 2040971933U, // <5,u,7,3>: Cost 2 vtrnr RHS, LHS - 430509384U, // <5,u,7,4>: Cost 1 vext1 RHS, RHS - 1504251600U, // <5,u,7,5>: Cost 2 vext1 RHS, <5,1,7,3> - 118708378U, // <5,u,7,6>: Cost 1 vrev RHS - 2040974889U, // <5,u,7,7>: Cost 2 vtrnr RHS, RHS - 430511918U, // <5,u,7,u>: Cost 1 vext1 RHS, LHS - 430514278U, // <5,u,u,0>: Cost 1 vext1 RHS, LHS - 1551906606U, // <5,u,u,1>: Cost 2 vext2 <1,3,5,u>, LHS - 1613388133U, // <5,u,u,2>: Cost 2 vext3 <0,4,1,5>, LHS - 1772544669U, // <5,u,u,3>: Cost 2 vuzpr RHS, LHS - 430517577U, // <5,u,u,4>: Cost 1 vext1 RHS, RHS - 229035318U, // <5,u,u,5>: Cost 1 vdup1 RHS - 118716571U, // <5,u,u,6>: Cost 1 vrev RHS - 1772547625U, // <5,u,u,7>: Cost 2 vuzpr RHS, RHS - 430520110U, // <5,u,u,u>: Cost 1 vext1 RHS, LHS - 2686025728U, // <6,0,0,0>: Cost 3 vext3 <0,2,4,6>, <0,0,0,0> - 2686025738U, // <6,0,0,1>: Cost 3 vext3 <0,2,4,6>, <0,0,1,1> - 2686025748U, // <6,0,0,2>: Cost 3 vext3 <0,2,4,6>, <0,0,2,2> - 3779084320U, // <6,0,0,3>: Cost 4 vext3 <3,4,5,6>, <0,0,3,5> - 2642903388U, // <6,0,0,4>: Cost 3 vext2 <4,2,6,0>, <0,4,2,6> - 3657723939U, // <6,0,0,5>: Cost 4 vext1 <5,6,0,0>, <5,6,0,0> - 3926676514U, // <6,0,0,6>: Cost 4 vuzpr <5,6,7,0>, <7,0,5,6> - 3926675786U, // <6,0,0,7>: Cost 4 vuzpr <5,6,7,0>, <6,0,5,7> - 2686025802U, // <6,0,0,u>: Cost 3 vext3 <0,2,4,6>, <0,0,u,2> - 2566070374U, // <6,0,1,0>: Cost 3 vext1 <2,6,0,1>, LHS - 3759767642U, // <6,0,1,1>: Cost 4 vext3 <0,2,4,6>, <0,1,1,0> - 1612284006U, // <6,0,1,2>: Cost 2 vext3 <0,2,4,6>, LHS - 2583988738U, // <6,0,1,3>: Cost 3 vext1 <5,6,0,1>, <3,4,5,6> - 2566073654U, // <6,0,1,4>: Cost 3 vext1 <2,6,0,1>, RHS - 2583990308U, // <6,0,1,5>: Cost 3 vext1 <5,6,0,1>, <5,6,0,1> - 2589963005U, // <6,0,1,6>: Cost 3 vext1 <6,6,0,1>, <6,6,0,1> - 2595935702U, // <6,0,1,7>: Cost 3 vext1 <7,6,0,1>, <7,6,0,1> - 1612284060U, // <6,0,1,u>: Cost 2 vext3 <0,2,4,6>, LHS - 2686025892U, // <6,0,2,0>: Cost 3 vext3 <0,2,4,6>, <0,2,0,2> - 2685804721U, // <6,0,2,1>: Cost 3 vext3 <0,2,1,6>, <0,2,1,6> - 3759620282U, // <6,0,2,2>: Cost 4 vext3 <0,2,2,6>, <0,2,2,6> - 2705342658U, // <6,0,2,3>: Cost 3 vext3 <3,4,5,6>, <0,2,3,5> - 1612284108U, // <6,0,2,4>: Cost 2 vext3 <0,2,4,6>, <0,2,4,6> - 3706029956U, // <6,0,2,5>: Cost 4 vext2 <2,4,6,0>, <2,5,6,7> - 2686173406U, // <6,0,2,6>: Cost 3 vext3 <0,2,6,6>, <0,2,6,6> - 3651769338U, // <6,0,2,7>: Cost 4 vext1 <4,6,0,2>, <7,0,1,2> - 1612579056U, // <6,0,2,u>: Cost 2 vext3 <0,2,u,6>, <0,2,u,6> - 3706030230U, // <6,0,3,0>: Cost 4 vext2 <2,4,6,0>, <3,0,1,2> - 2705342720U, // <6,0,3,1>: Cost 3 vext3 <3,4,5,6>, <0,3,1,4> - 2705342730U, // <6,0,3,2>: Cost 3 vext3 <3,4,5,6>, <0,3,2,5> - 3706030492U, // <6,0,3,3>: Cost 4 vext2 <2,4,6,0>, <3,3,3,3> - 2644896258U, // <6,0,3,4>: Cost 3 vext2 <4,5,6,0>, <3,4,5,6> - 3718638154U, // <6,0,3,5>: Cost 4 vext2 <4,5,6,0>, <3,5,4,6> - 3729918619U, // <6,0,3,6>: Cost 4 vext2 <6,4,6,0>, <3,6,4,6> - 3926672384U, // <6,0,3,7>: Cost 4 vuzpr <5,6,7,0>, <1,3,5,7> - 2705342784U, // <6,0,3,u>: Cost 3 vext3 <3,4,5,6>, <0,3,u,5> - 2687058250U, // <6,0,4,0>: Cost 3 vext3 <0,4,0,6>, <0,4,0,6> - 2686026066U, // <6,0,4,1>: Cost 3 vext3 <0,2,4,6>, <0,4,1,5> - 1613463900U, // <6,0,4,2>: Cost 2 vext3 <0,4,2,6>, <0,4,2,6> - 3761021285U, // <6,0,4,3>: Cost 4 vext3 <0,4,3,6>, <0,4,3,6> - 2687353198U, // <6,0,4,4>: Cost 3 vext3 <0,4,4,6>, <0,4,4,6> - 2632289590U, // <6,0,4,5>: Cost 3 vext2 <2,4,6,0>, RHS - 2645560704U, // <6,0,4,6>: Cost 3 vext2 <4,6,6,0>, <4,6,6,0> - 2646224337U, // <6,0,4,7>: Cost 3 vext2 <4,7,6,0>, <4,7,6,0> - 1613906322U, // <6,0,4,u>: Cost 2 vext3 <0,4,u,6>, <0,4,u,6> - 3651788902U, // <6,0,5,0>: Cost 4 vext1 <4,6,0,5>, LHS - 2687795620U, // <6,0,5,1>: Cost 3 vext3 <0,5,1,6>, <0,5,1,6> - 3761611181U, // <6,0,5,2>: Cost 4 vext3 <0,5,2,6>, <0,5,2,6> - 3723284326U, // <6,0,5,3>: Cost 4 vext2 <5,3,6,0>, <5,3,6,0> - 2646224838U, // <6,0,5,4>: Cost 3 vext2 <4,7,6,0>, <5,4,7,6> - 3718639630U, // <6,0,5,5>: Cost 4 vext2 <4,5,6,0>, <5,5,6,6> - 2652196962U, // <6,0,5,6>: Cost 3 vext2 <5,7,6,0>, <5,6,7,0> - 2852932918U, // <6,0,5,7>: Cost 3 vuzpr <5,6,7,0>, RHS - 2852932919U, // <6,0,5,u>: Cost 3 vuzpr <5,6,7,0>, RHS - 2852933730U, // <6,0,6,0>: Cost 3 vuzpr <5,6,7,0>, <5,6,7,0> - 2925985894U, // <6,0,6,1>: Cost 3 vzipl <6,6,6,6>, LHS - 3060203622U, // <6,0,6,2>: Cost 3 vtrnl <6,6,6,6>, LHS - 3718640178U, // <6,0,6,3>: Cost 4 vext2 <4,5,6,0>, <6,3,4,5> - 2656178832U, // <6,0,6,4>: Cost 3 vext2 <6,4,6,0>, <6,4,6,0> - 3725939378U, // <6,0,6,5>: Cost 4 vext2 <5,7,6,0>, <6,5,0,7> - 2657506098U, // <6,0,6,6>: Cost 3 vext2 <6,6,6,0>, <6,6,6,0> - 2619020110U, // <6,0,6,7>: Cost 3 vext2 <0,2,6,0>, <6,7,0,1> - 2925986461U, // <6,0,6,u>: Cost 3 vzipl <6,6,6,6>, LHS - 2572091494U, // <6,0,7,0>: Cost 3 vext1 <3,6,0,7>, LHS - 2572092310U, // <6,0,7,1>: Cost 3 vext1 <3,6,0,7>, <1,2,3,0> - 2980495524U, // <6,0,7,2>: Cost 3 vzipr RHS, <0,2,0,2> - 2572094072U, // <6,0,7,3>: Cost 3 vext1 <3,6,0,7>, <3,6,0,7> - 2572094774U, // <6,0,7,4>: Cost 3 vext1 <3,6,0,7>, RHS - 4054238242U, // <6,0,7,5>: Cost 4 vzipr RHS, <1,4,0,5> - 3645837653U, // <6,0,7,6>: Cost 4 vext1 <3,6,0,7>, <6,0,7,0> - 4054239054U, // <6,0,7,7>: Cost 4 vzipr RHS, <2,5,0,7> - 2572097326U, // <6,0,7,u>: Cost 3 vext1 <3,6,0,7>, LHS - 2686026378U, // <6,0,u,0>: Cost 3 vext3 <0,2,4,6>, <0,u,0,2> - 2686026386U, // <6,0,u,1>: Cost 3 vext3 <0,2,4,6>, <0,u,1,1> - 1612284573U, // <6,0,u,2>: Cost 2 vext3 <0,2,4,6>, LHS - 2705343144U, // <6,0,u,3>: Cost 3 vext3 <3,4,5,6>, <0,u,3,5> - 1616265906U, // <6,0,u,4>: Cost 2 vext3 <0,u,4,6>, <0,u,4,6> - 2632292506U, // <6,0,u,5>: Cost 3 vext2 <2,4,6,0>, RHS - 2590020356U, // <6,0,u,6>: Cost 3 vext1 <6,6,0,u>, <6,6,0,u> - 2852933161U, // <6,0,u,7>: Cost 3 vuzpr <5,6,7,0>, RHS - 1612284627U, // <6,0,u,u>: Cost 2 vext3 <0,2,4,6>, LHS - 2595995750U, // <6,1,0,0>: Cost 3 vext1 <7,6,1,0>, LHS - 2646229094U, // <6,1,0,1>: Cost 3 vext2 <4,7,6,1>, LHS - 3694092492U, // <6,1,0,2>: Cost 4 vext2 <0,4,6,1>, <0,2,4,6> - 2686026486U, // <6,1,0,3>: Cost 3 vext3 <0,2,4,6>, <1,0,3,2> - 2595999030U, // <6,1,0,4>: Cost 3 vext1 <7,6,1,0>, RHS - 3767730952U, // <6,1,0,5>: Cost 4 vext3 <1,5,4,6>, <1,0,5,2> - 2596000590U, // <6,1,0,6>: Cost 3 vext1 <7,6,1,0>, <6,7,0,1> - 2596001246U, // <6,1,0,7>: Cost 3 vext1 <7,6,1,0>, <7,6,1,0> - 2686026531U, // <6,1,0,u>: Cost 3 vext3 <0,2,4,6>, <1,0,u,2> - 3763602219U, // <6,1,1,0>: Cost 4 vext3 <0,u,2,6>, <1,1,0,1> - 2686026548U, // <6,1,1,1>: Cost 3 vext3 <0,2,4,6>, <1,1,1,1> - 3764929346U, // <6,1,1,2>: Cost 4 vext3 <1,1,2,6>, <1,1,2,6> - 2686026568U, // <6,1,1,3>: Cost 3 vext3 <0,2,4,6>, <1,1,3,3> - 2691334996U, // <6,1,1,4>: Cost 3 vext3 <1,1,4,6>, <1,1,4,6> - 3760874332U, // <6,1,1,5>: Cost 4 vext3 <0,4,1,6>, <1,1,5,5> - 3765224294U, // <6,1,1,6>: Cost 4 vext3 <1,1,6,6>, <1,1,6,6> - 3669751263U, // <6,1,1,7>: Cost 4 vext1 <7,6,1,1>, <7,6,1,1> - 2686026613U, // <6,1,1,u>: Cost 3 vext3 <0,2,4,6>, <1,1,u,3> - 2554208358U, // <6,1,2,0>: Cost 3 vext1 <0,6,1,2>, LHS - 3763602311U, // <6,1,2,1>: Cost 4 vext3 <0,u,2,6>, <1,2,1,3> - 3639895971U, // <6,1,2,2>: Cost 4 vext1 <2,6,1,2>, <2,6,1,2> - 2686026646U, // <6,1,2,3>: Cost 3 vext3 <0,2,4,6>, <1,2,3,0> - 2554211638U, // <6,1,2,4>: Cost 3 vext1 <0,6,1,2>, RHS - 3760874411U, // <6,1,2,5>: Cost 4 vext3 <0,4,1,6>, <1,2,5,3> - 2554212858U, // <6,1,2,6>: Cost 3 vext1 <0,6,1,2>, <6,2,7,3> - 3802973114U, // <6,1,2,7>: Cost 4 vext3 <7,4,5,6>, <1,2,7,0> - 2686026691U, // <6,1,2,u>: Cost 3 vext3 <0,2,4,6>, <1,2,u,0> - 2566160486U, // <6,1,3,0>: Cost 3 vext1 <2,6,1,3>, LHS - 2686026712U, // <6,1,3,1>: Cost 3 vext3 <0,2,4,6>, <1,3,1,3> - 2686026724U, // <6,1,3,2>: Cost 3 vext3 <0,2,4,6>, <1,3,2,6> - 3759768552U, // <6,1,3,3>: Cost 4 vext3 <0,2,4,6>, <1,3,3,1> - 2692662262U, // <6,1,3,4>: Cost 3 vext3 <1,3,4,6>, <1,3,4,6> - 2686026752U, // <6,1,3,5>: Cost 3 vext3 <0,2,4,6>, <1,3,5,7> - 2590053128U, // <6,1,3,6>: Cost 3 vext1 <6,6,1,3>, <6,6,1,3> - 3663795194U, // <6,1,3,7>: Cost 4 vext1 <6,6,1,3>, <7,0,1,2> - 2686026775U, // <6,1,3,u>: Cost 3 vext3 <0,2,4,6>, <1,3,u,3> - 2641587099U, // <6,1,4,0>: Cost 3 vext2 <4,0,6,1>, <4,0,6,1> - 2693104684U, // <6,1,4,1>: Cost 3 vext3 <1,4,1,6>, <1,4,1,6> - 3639912357U, // <6,1,4,2>: Cost 4 vext1 <2,6,1,4>, <2,6,1,4> - 2687206462U, // <6,1,4,3>: Cost 3 vext3 <0,4,2,6>, <1,4,3,6> - 3633941814U, // <6,1,4,4>: Cost 4 vext1 <1,6,1,4>, RHS - 2693399632U, // <6,1,4,5>: Cost 3 vext3 <1,4,5,6>, <1,4,5,6> - 3765077075U, // <6,1,4,6>: Cost 4 vext3 <1,1,4,6>, <1,4,6,0> - 2646232530U, // <6,1,4,7>: Cost 3 vext2 <4,7,6,1>, <4,7,6,1> - 2687206507U, // <6,1,4,u>: Cost 3 vext3 <0,4,2,6>, <1,4,u,6> - 2647559796U, // <6,1,5,0>: Cost 3 vext2 <5,0,6,1>, <5,0,6,1> - 3765077118U, // <6,1,5,1>: Cost 4 vext3 <1,1,4,6>, <1,5,1,7> - 3767583878U, // <6,1,5,2>: Cost 4 vext3 <1,5,2,6>, <1,5,2,6> - 2686026896U, // <6,1,5,3>: Cost 3 vext3 <0,2,4,6>, <1,5,3,7> - 2693989528U, // <6,1,5,4>: Cost 3 vext3 <1,5,4,6>, <1,5,4,6> - 3767805089U, // <6,1,5,5>: Cost 4 vext3 <1,5,5,6>, <1,5,5,6> - 2652868706U, // <6,1,5,6>: Cost 3 vext2 <5,u,6,1>, <5,6,7,0> - 3908250934U, // <6,1,5,7>: Cost 4 vuzpr <2,6,0,1>, RHS - 2686026941U, // <6,1,5,u>: Cost 3 vext3 <0,2,4,6>, <1,5,u,7> - 2554241126U, // <6,1,6,0>: Cost 3 vext1 <0,6,1,6>, LHS - 3763602639U, // <6,1,6,1>: Cost 4 vext3 <0,u,2,6>, <1,6,1,7> - 3759547607U, // <6,1,6,2>: Cost 4 vext3 <0,2,1,6>, <1,6,2,6> - 3115221094U, // <6,1,6,3>: Cost 3 vtrnr <4,6,4,6>, LHS - 2554244406U, // <6,1,6,4>: Cost 3 vext1 <0,6,1,6>, RHS - 3760874739U, // <6,1,6,5>: Cost 4 vext3 <0,4,1,6>, <1,6,5,7> - 2554245944U, // <6,1,6,6>: Cost 3 vext1 <0,6,1,6>, <6,6,6,6> - 3719975758U, // <6,1,6,7>: Cost 4 vext2 <4,7,6,1>, <6,7,0,1> - 3115221099U, // <6,1,6,u>: Cost 3 vtrnr <4,6,4,6>, LHS - 2560221286U, // <6,1,7,0>: Cost 3 vext1 <1,6,1,7>, LHS - 2560222415U, // <6,1,7,1>: Cost 3 vext1 <1,6,1,7>, <1,6,1,7> - 2980497558U, // <6,1,7,2>: Cost 3 vzipr RHS, <3,0,1,2> - 3103211622U, // <6,1,7,3>: Cost 3 vtrnr <2,6,3,7>, LHS - 2560224566U, // <6,1,7,4>: Cost 3 vext1 <1,6,1,7>, RHS - 2980495698U, // <6,1,7,5>: Cost 3 vzipr RHS, <0,4,1,5> - 3633967526U, // <6,1,7,6>: Cost 4 vext1 <1,6,1,7>, <6,1,7,0> - 4054237686U, // <6,1,7,7>: Cost 4 vzipr RHS, <0,6,1,7> - 2560227118U, // <6,1,7,u>: Cost 3 vext1 <1,6,1,7>, LHS - 2560229478U, // <6,1,u,0>: Cost 3 vext1 <1,6,1,u>, LHS - 2686027117U, // <6,1,u,1>: Cost 3 vext3 <0,2,4,6>, <1,u,1,3> - 2686027129U, // <6,1,u,2>: Cost 3 vext3 <0,2,4,6>, <1,u,2,6> - 2686027132U, // <6,1,u,3>: Cost 3 vext3 <0,2,4,6>, <1,u,3,0> - 2687206795U, // <6,1,u,4>: Cost 3 vext3 <0,4,2,6>, <1,u,4,6> - 2686027157U, // <6,1,u,5>: Cost 3 vext3 <0,2,4,6>, <1,u,5,7> - 2590094093U, // <6,1,u,6>: Cost 3 vext1 <6,6,1,u>, <6,6,1,u> - 2596066790U, // <6,1,u,7>: Cost 3 vext1 <7,6,1,u>, <7,6,1,u> - 2686027177U, // <6,1,u,u>: Cost 3 vext3 <0,2,4,6>, <1,u,u,0> - 2646900736U, // <6,2,0,0>: Cost 3 vext2 <4,u,6,2>, <0,0,0,0> - 1573159014U, // <6,2,0,1>: Cost 2 vext2 <4,u,6,2>, LHS - 2646900900U, // <6,2,0,2>: Cost 3 vext2 <4,u,6,2>, <0,2,0,2> - 3759769037U, // <6,2,0,3>: Cost 4 vext3 <0,2,4,6>, <2,0,3,0> - 2641592668U, // <6,2,0,4>: Cost 3 vext2 <4,0,6,2>, <0,4,2,6> - 3779085794U, // <6,2,0,5>: Cost 4 vext3 <3,4,5,6>, <2,0,5,3> - 2686027244U, // <6,2,0,6>: Cost 3 vext3 <0,2,4,6>, <2,0,6,4> - 3669816807U, // <6,2,0,7>: Cost 4 vext1 <7,6,2,0>, <7,6,2,0> - 1573159581U, // <6,2,0,u>: Cost 2 vext2 <4,u,6,2>, LHS - 2230527897U, // <6,2,1,0>: Cost 3 vrev <2,6,0,1> - 2646901556U, // <6,2,1,1>: Cost 3 vext2 <4,u,6,2>, <1,1,1,1> - 2646901654U, // <6,2,1,2>: Cost 3 vext2 <4,u,6,2>, <1,2,3,0> - 2847047782U, // <6,2,1,3>: Cost 3 vuzpr <4,6,u,2>, LHS - 3771049517U, // <6,2,1,4>: Cost 4 vext3 <2,1,4,6>, <2,1,4,6> - 2646901904U, // <6,2,1,5>: Cost 3 vext2 <4,u,6,2>, <1,5,3,7> - 2686027324U, // <6,2,1,6>: Cost 3 vext3 <0,2,4,6>, <2,1,6,3> - 3669825000U, // <6,2,1,7>: Cost 4 vext1 <7,6,2,1>, <7,6,2,1> - 2231117793U, // <6,2,1,u>: Cost 3 vrev <2,6,u,1> - 3763603029U, // <6,2,2,0>: Cost 4 vext3 <0,u,2,6>, <2,2,0,1> - 3759769184U, // <6,2,2,1>: Cost 4 vext3 <0,2,4,6>, <2,2,1,3> - 2686027368U, // <6,2,2,2>: Cost 3 vext3 <0,2,4,6>, <2,2,2,2> - 2686027378U, // <6,2,2,3>: Cost 3 vext3 <0,2,4,6>, <2,2,3,3> - 2697971326U, // <6,2,2,4>: Cost 3 vext3 <2,2,4,6>, <2,2,4,6> - 3759769224U, // <6,2,2,5>: Cost 4 vext3 <0,2,4,6>, <2,2,5,7> - 2698118800U, // <6,2,2,6>: Cost 3 vext3 <2,2,6,6>, <2,2,6,6> - 3920794092U, // <6,2,2,7>: Cost 4 vuzpr <4,6,u,2>, <6,2,5,7> - 2686027423U, // <6,2,2,u>: Cost 3 vext3 <0,2,4,6>, <2,2,u,3> - 2686027430U, // <6,2,3,0>: Cost 3 vext3 <0,2,4,6>, <2,3,0,1> - 3759769262U, // <6,2,3,1>: Cost 4 vext3 <0,2,4,6>, <2,3,1,0> - 2698487485U, // <6,2,3,2>: Cost 3 vext3 <2,3,2,6>, <2,3,2,6> - 2705344196U, // <6,2,3,3>: Cost 3 vext3 <3,4,5,6>, <2,3,3,4> - 2686027470U, // <6,2,3,4>: Cost 3 vext3 <0,2,4,6>, <2,3,4,5> - 2698708696U, // <6,2,3,5>: Cost 3 vext3 <2,3,5,6>, <2,3,5,6> - 2724660961U, // <6,2,3,6>: Cost 3 vext3 <6,6,6,6>, <2,3,6,6> - 2729232104U, // <6,2,3,7>: Cost 3 vext3 <7,4,5,6>, <2,3,7,4> - 2686027502U, // <6,2,3,u>: Cost 3 vext3 <0,2,4,6>, <2,3,u,1> - 1567853468U, // <6,2,4,0>: Cost 2 vext2 <4,0,6,2>, <4,0,6,2> - 3759769351U, // <6,2,4,1>: Cost 4 vext3 <0,2,4,6>, <2,4,1,u> - 2699151118U, // <6,2,4,2>: Cost 3 vext3 <2,4,2,6>, <2,4,2,6> - 2686027543U, // <6,2,4,3>: Cost 3 vext3 <0,2,4,6>, <2,4,3,6> - 2699298592U, // <6,2,4,4>: Cost 3 vext3 <2,4,4,6>, <2,4,4,6> - 1573162294U, // <6,2,4,5>: Cost 2 vext2 <4,u,6,2>, RHS - 2686027564U, // <6,2,4,6>: Cost 3 vext3 <0,2,4,6>, <2,4,6,0> - 3719982547U, // <6,2,4,7>: Cost 4 vext2 <4,7,6,2>, <4,7,6,2> - 1573162532U, // <6,2,4,u>: Cost 2 vext2 <4,u,6,2>, <4,u,6,2> - 3779086154U, // <6,2,5,0>: Cost 4 vext3 <3,4,5,6>, <2,5,0,3> - 2646904528U, // <6,2,5,1>: Cost 3 vext2 <4,u,6,2>, <5,1,7,3> - 3759769440U, // <6,2,5,2>: Cost 4 vext3 <0,2,4,6>, <2,5,2,7> - 2699888488U, // <6,2,5,3>: Cost 3 vext3 <2,5,3,6>, <2,5,3,6> - 2230855617U, // <6,2,5,4>: Cost 3 vrev <2,6,4,5> - 2646904836U, // <6,2,5,5>: Cost 3 vext2 <4,u,6,2>, <5,5,5,5> - 2646904930U, // <6,2,5,6>: Cost 3 vext2 <4,u,6,2>, <5,6,7,0> - 2847051062U, // <6,2,5,7>: Cost 3 vuzpr <4,6,u,2>, RHS - 2700257173U, // <6,2,5,u>: Cost 3 vext3 <2,5,u,6>, <2,5,u,6> - 2687207321U, // <6,2,6,0>: Cost 3 vext3 <0,4,2,6>, <2,6,0,1> - 2686027684U, // <6,2,6,1>: Cost 3 vext3 <0,2,4,6>, <2,6,1,3> - 2566260656U, // <6,2,6,2>: Cost 3 vext1 <2,6,2,6>, <2,6,2,6> - 2685806522U, // <6,2,6,3>: Cost 3 vext3 <0,2,1,6>, <2,6,3,7> - 2687207361U, // <6,2,6,4>: Cost 3 vext3 <0,4,2,6>, <2,6,4,5> - 2686027724U, // <6,2,6,5>: Cost 3 vext3 <0,2,4,6>, <2,6,5,7> - 2646905656U, // <6,2,6,6>: Cost 3 vext2 <4,u,6,2>, <6,6,6,6> - 2646905678U, // <6,2,6,7>: Cost 3 vext2 <4,u,6,2>, <6,7,0,1> - 2686027751U, // <6,2,6,u>: Cost 3 vext3 <0,2,4,6>, <2,6,u,7> - 2554323046U, // <6,2,7,0>: Cost 3 vext1 <0,6,2,7>, LHS - 2572239606U, // <6,2,7,1>: Cost 3 vext1 <3,6,2,7>, <1,0,3,2> - 2566268849U, // <6,2,7,2>: Cost 3 vext1 <2,6,2,7>, <2,6,2,7> - 1906753638U, // <6,2,7,3>: Cost 2 vzipr RHS, LHS - 2554326326U, // <6,2,7,4>: Cost 3 vext1 <0,6,2,7>, RHS - 3304687564U, // <6,2,7,5>: Cost 4 vrev <2,6,5,7> - 2980495708U, // <6,2,7,6>: Cost 3 vzipr RHS, <0,4,2,6> - 2646906476U, // <6,2,7,7>: Cost 3 vext2 <4,u,6,2>, <7,7,7,7> - 1906753643U, // <6,2,7,u>: Cost 2 vzipr RHS, LHS - 1591744256U, // <6,2,u,0>: Cost 2 vext2 , - 1573164846U, // <6,2,u,1>: Cost 2 vext2 <4,u,6,2>, LHS - 2701805650U, // <6,2,u,2>: Cost 3 vext3 <2,u,2,6>, <2,u,2,6> - 1906761830U, // <6,2,u,3>: Cost 2 vzipr RHS, LHS - 2686027875U, // <6,2,u,4>: Cost 3 vext3 <0,2,4,6>, <2,u,4,5> - 1573165210U, // <6,2,u,5>: Cost 2 vext2 <4,u,6,2>, RHS - 2686322800U, // <6,2,u,6>: Cost 3 vext3 <0,2,u,6>, <2,u,6,0> - 2847051305U, // <6,2,u,7>: Cost 3 vuzpr <4,6,u,2>, RHS - 1906761835U, // <6,2,u,u>: Cost 2 vzipr RHS, LHS - 3759769739U, // <6,3,0,0>: Cost 4 vext3 <0,2,4,6>, <3,0,0,0> - 2686027926U, // <6,3,0,1>: Cost 3 vext3 <0,2,4,6>, <3,0,1,2> - 2686027937U, // <6,3,0,2>: Cost 3 vext3 <0,2,4,6>, <3,0,2,4> - 3640027286U, // <6,3,0,3>: Cost 4 vext1 <2,6,3,0>, <3,0,1,2> - 2687207601U, // <6,3,0,4>: Cost 3 vext3 <0,4,2,6>, <3,0,4,2> - 2705344698U, // <6,3,0,5>: Cost 3 vext3 <3,4,5,6>, <3,0,5,2> - 3663917847U, // <6,3,0,6>: Cost 4 vext1 <6,6,3,0>, <6,6,3,0> - 2237008560U, // <6,3,0,7>: Cost 3 vrev <3,6,7,0> - 2686027989U, // <6,3,0,u>: Cost 3 vext3 <0,2,4,6>, <3,0,u,2> - 3759769823U, // <6,3,1,0>: Cost 4 vext3 <0,2,4,6>, <3,1,0,3> - 3759769830U, // <6,3,1,1>: Cost 4 vext3 <0,2,4,6>, <3,1,1,1> - 3759769841U, // <6,3,1,2>: Cost 4 vext3 <0,2,4,6>, <3,1,2,3> - 3759769848U, // <6,3,1,3>: Cost 4 vext3 <0,2,4,6>, <3,1,3,1> - 2703280390U, // <6,3,1,4>: Cost 3 vext3 <3,1,4,6>, <3,1,4,6> - 3759769868U, // <6,3,1,5>: Cost 4 vext3 <0,2,4,6>, <3,1,5,3> - 3704063194U, // <6,3,1,6>: Cost 4 vext2 <2,1,6,3>, <1,6,3,0> - 3767732510U, // <6,3,1,7>: Cost 4 vext3 <1,5,4,6>, <3,1,7,3> - 2703280390U, // <6,3,1,u>: Cost 3 vext3 <3,1,4,6>, <3,1,4,6> - 3704063468U, // <6,3,2,0>: Cost 4 vext2 <2,1,6,3>, <2,0,6,4> - 2630321724U, // <6,3,2,1>: Cost 3 vext2 <2,1,6,3>, <2,1,6,3> - 3759769921U, // <6,3,2,2>: Cost 4 vext3 <0,2,4,6>, <3,2,2,2> - 3759769928U, // <6,3,2,3>: Cost 4 vext3 <0,2,4,6>, <3,2,3,0> - 3704063767U, // <6,3,2,4>: Cost 4 vext2 <2,1,6,3>, <2,4,3,6> - 3704063876U, // <6,3,2,5>: Cost 4 vext2 <2,1,6,3>, <2,5,6,7> - 2636957626U, // <6,3,2,6>: Cost 3 vext2 <3,2,6,3>, <2,6,3,7> - 3777907058U, // <6,3,2,7>: Cost 4 vext3 <3,2,7,6>, <3,2,7,6> - 2630321724U, // <6,3,2,u>: Cost 3 vext2 <2,1,6,3>, <2,1,6,3> - 3759769983U, // <6,3,3,0>: Cost 4 vext3 <0,2,4,6>, <3,3,0,1> - 3710036245U, // <6,3,3,1>: Cost 4 vext2 <3,1,6,3>, <3,1,6,3> - 2636958054U, // <6,3,3,2>: Cost 3 vext2 <3,2,6,3>, <3,2,6,3> - 2686028188U, // <6,3,3,3>: Cost 3 vext3 <0,2,4,6>, <3,3,3,3> - 2704607656U, // <6,3,3,4>: Cost 3 vext3 <3,3,4,6>, <3,3,4,6> - 3773041072U, // <6,3,3,5>: Cost 4 vext3 <2,4,4,6>, <3,3,5,5> - 3711363731U, // <6,3,3,6>: Cost 4 vext2 <3,3,6,3>, <3,6,3,7> - 3767732676U, // <6,3,3,7>: Cost 4 vext3 <1,5,4,6>, <3,3,7,7> - 2707999179U, // <6,3,3,u>: Cost 3 vext3 <3,u,5,6>, <3,3,u,5> - 2584232038U, // <6,3,4,0>: Cost 3 vext1 <5,6,3,4>, LHS - 2642267118U, // <6,3,4,1>: Cost 3 vext2 <4,1,6,3>, <4,1,6,3> - 2642930751U, // <6,3,4,2>: Cost 3 vext2 <4,2,6,3>, <4,2,6,3> - 2705197552U, // <6,3,4,3>: Cost 3 vext3 <3,4,3,6>, <3,4,3,6> - 2584235318U, // <6,3,4,4>: Cost 3 vext1 <5,6,3,4>, RHS - 1631603202U, // <6,3,4,5>: Cost 2 vext3 <3,4,5,6>, <3,4,5,6> - 2654211444U, // <6,3,4,6>: Cost 3 vext2 <6,1,6,3>, <4,6,4,6> - 2237041332U, // <6,3,4,7>: Cost 3 vrev <3,6,7,4> - 1631824413U, // <6,3,4,u>: Cost 2 vext3 <3,4,u,6>, <3,4,u,6> - 3640066150U, // <6,3,5,0>: Cost 4 vext1 <2,6,3,5>, LHS - 3772746288U, // <6,3,5,1>: Cost 4 vext3 <2,4,0,6>, <3,5,1,7> - 3640067790U, // <6,3,5,2>: Cost 4 vext1 <2,6,3,5>, <2,3,4,5> - 3773041216U, // <6,3,5,3>: Cost 4 vext3 <2,4,4,6>, <3,5,3,5> - 2705934922U, // <6,3,5,4>: Cost 3 vext3 <3,5,4,6>, <3,5,4,6> - 3773041236U, // <6,3,5,5>: Cost 4 vext3 <2,4,4,6>, <3,5,5,7> - 3779086940U, // <6,3,5,6>: Cost 4 vext3 <3,4,5,6>, <3,5,6,6> - 3767732831U, // <6,3,5,7>: Cost 4 vext3 <1,5,4,6>, <3,5,7,0> - 2706229870U, // <6,3,5,u>: Cost 3 vext3 <3,5,u,6>, <3,5,u,6> - 2602164326U, // <6,3,6,0>: Cost 3 vext1 , LHS - 2654212512U, // <6,3,6,1>: Cost 3 vext2 <6,1,6,3>, <6,1,6,3> - 2566334393U, // <6,3,6,2>: Cost 3 vext1 <2,6,3,6>, <2,6,3,6> - 3704066588U, // <6,3,6,3>: Cost 4 vext2 <2,1,6,3>, <6,3,2,1> - 2602167524U, // <6,3,6,4>: Cost 3 vext1 , <4,4,6,6> - 3710702321U, // <6,3,6,5>: Cost 4 vext2 <3,2,6,3>, <6,5,7,7> - 2724661933U, // <6,3,6,6>: Cost 3 vext3 <6,6,6,6>, <3,6,6,6> - 3710702465U, // <6,3,6,7>: Cost 4 vext2 <3,2,6,3>, <6,7,5,7> - 2602170158U, // <6,3,6,u>: Cost 3 vext1 , LHS - 1492598886U, // <6,3,7,0>: Cost 2 vext1 <2,6,3,7>, LHS - 2560369889U, // <6,3,7,1>: Cost 3 vext1 <1,6,3,7>, <1,6,3,7> - 1492600762U, // <6,3,7,2>: Cost 2 vext1 <2,6,3,7>, <2,6,3,7> - 2566342806U, // <6,3,7,3>: Cost 3 vext1 <2,6,3,7>, <3,0,1,2> - 1492602166U, // <6,3,7,4>: Cost 2 vext1 <2,6,3,7>, RHS - 2602176208U, // <6,3,7,5>: Cost 3 vext1 , <5,1,7,3> - 2566345210U, // <6,3,7,6>: Cost 3 vext1 <2,6,3,7>, <6,2,7,3> - 2980496528U, // <6,3,7,7>: Cost 3 vzipr RHS, <1,5,3,7> - 1492604718U, // <6,3,7,u>: Cost 2 vext1 <2,6,3,7>, LHS - 1492607078U, // <6,3,u,0>: Cost 2 vext1 <2,6,3,u>, LHS - 2686028574U, // <6,3,u,1>: Cost 3 vext3 <0,2,4,6>, <3,u,1,2> - 1492608955U, // <6,3,u,2>: Cost 2 vext1 <2,6,3,u>, <2,6,3,u> - 2566350998U, // <6,3,u,3>: Cost 3 vext1 <2,6,3,u>, <3,0,1,2> - 1492610358U, // <6,3,u,4>: Cost 2 vext1 <2,6,3,u>, RHS - 1634257734U, // <6,3,u,5>: Cost 2 vext3 <3,u,5,6>, <3,u,5,6> - 2566353489U, // <6,3,u,6>: Cost 3 vext1 <2,6,3,u>, <6,3,u,0> - 2980504720U, // <6,3,u,7>: Cost 3 vzipr RHS, <1,5,3,7> - 1492612910U, // <6,3,u,u>: Cost 2 vext1 <2,6,3,u>, LHS - 3703406592U, // <6,4,0,0>: Cost 4 vext2 <2,0,6,4>, <0,0,0,0> - 2629664870U, // <6,4,0,1>: Cost 3 vext2 <2,0,6,4>, LHS - 2629664972U, // <6,4,0,2>: Cost 3 vext2 <2,0,6,4>, <0,2,4,6> - 3779087232U, // <6,4,0,3>: Cost 4 vext3 <3,4,5,6>, <4,0,3,1> - 2642936156U, // <6,4,0,4>: Cost 3 vext2 <4,2,6,4>, <0,4,2,6> - 2712570770U, // <6,4,0,5>: Cost 3 vext3 <4,6,4,6>, <4,0,5,1> - 2687208348U, // <6,4,0,6>: Cost 3 vext3 <0,4,2,6>, <4,0,6,2> - 3316723081U, // <6,4,0,7>: Cost 4 vrev <4,6,7,0> - 2629665437U, // <6,4,0,u>: Cost 3 vext2 <2,0,6,4>, LHS - 2242473291U, // <6,4,1,0>: Cost 3 vrev <4,6,0,1> - 3700089652U, // <6,4,1,1>: Cost 4 vext2 <1,4,6,4>, <1,1,1,1> - 3703407510U, // <6,4,1,2>: Cost 4 vext2 <2,0,6,4>, <1,2,3,0> - 2852962406U, // <6,4,1,3>: Cost 3 vuzpr <5,6,7,4>, LHS - 3628166454U, // <6,4,1,4>: Cost 4 vext1 <0,6,4,1>, RHS - 3760876514U, // <6,4,1,5>: Cost 4 vext3 <0,4,1,6>, <4,1,5,0> - 2687208430U, // <6,4,1,6>: Cost 3 vext3 <0,4,2,6>, <4,1,6,3> - 3316731274U, // <6,4,1,7>: Cost 4 vrev <4,6,7,1> - 2243063187U, // <6,4,1,u>: Cost 3 vrev <4,6,u,1> - 2629666284U, // <6,4,2,0>: Cost 3 vext2 <2,0,6,4>, <2,0,6,4> - 3703408188U, // <6,4,2,1>: Cost 4 vext2 <2,0,6,4>, <2,1,6,3> - 3703408232U, // <6,4,2,2>: Cost 4 vext2 <2,0,6,4>, <2,2,2,2> - 3703408294U, // <6,4,2,3>: Cost 4 vext2 <2,0,6,4>, <2,3,0,1> - 2632320816U, // <6,4,2,4>: Cost 3 vext2 <2,4,6,4>, <2,4,6,4> - 2923384118U, // <6,4,2,5>: Cost 3 vzipl <6,2,7,3>, RHS - 2687208508U, // <6,4,2,6>: Cost 3 vext3 <0,4,2,6>, <4,2,6,0> - 3760950341U, // <6,4,2,7>: Cost 4 vext3 <0,4,2,6>, <4,2,7,0> - 2634975348U, // <6,4,2,u>: Cost 3 vext2 <2,u,6,4>, <2,u,6,4> - 3703408790U, // <6,4,3,0>: Cost 4 vext2 <2,0,6,4>, <3,0,1,2> - 3316305238U, // <6,4,3,1>: Cost 4 vrev <4,6,1,3> - 3703408947U, // <6,4,3,2>: Cost 4 vext2 <2,0,6,4>, <3,2,0,6> - 3703409052U, // <6,4,3,3>: Cost 4 vext2 <2,0,6,4>, <3,3,3,3> - 2644929026U, // <6,4,3,4>: Cost 3 vext2 <4,5,6,4>, <3,4,5,6> - 3718670922U, // <6,4,3,5>: Cost 4 vext2 <4,5,6,4>, <3,5,4,6> - 2705345682U, // <6,4,3,6>: Cost 3 vext3 <3,4,5,6>, <4,3,6,5> - 3926705152U, // <6,4,3,7>: Cost 4 vuzpr <5,6,7,4>, <1,3,5,7> - 2668817222U, // <6,4,3,u>: Cost 3 vext2 , <3,u,5,6> - 2590277734U, // <6,4,4,0>: Cost 3 vext1 <6,6,4,4>, LHS - 3716017135U, // <6,4,4,1>: Cost 4 vext2 <4,1,6,4>, <4,1,6,4> - 2642938944U, // <6,4,4,2>: Cost 3 vext2 <4,2,6,4>, <4,2,6,4> - 3717344401U, // <6,4,4,3>: Cost 4 vext2 <4,3,6,4>, <4,3,6,4> - 2712571088U, // <6,4,4,4>: Cost 3 vext3 <4,6,4,6>, <4,4,4,4> - 2629668150U, // <6,4,4,5>: Cost 3 vext2 <2,0,6,4>, RHS - 1637649636U, // <6,4,4,6>: Cost 2 vext3 <4,4,6,6>, <4,4,6,6> - 2646257109U, // <6,4,4,7>: Cost 3 vext2 <4,7,6,4>, <4,7,6,4> - 1637649636U, // <6,4,4,u>: Cost 2 vext3 <4,4,6,6>, <4,4,6,6> - 2566398054U, // <6,4,5,0>: Cost 3 vext1 <2,6,4,5>, LHS - 3760876805U, // <6,4,5,1>: Cost 4 vext3 <0,4,1,6>, <4,5,1,3> - 2566399937U, // <6,4,5,2>: Cost 3 vext1 <2,6,4,5>, <2,6,4,5> - 2584316418U, // <6,4,5,3>: Cost 3 vext1 <5,6,4,5>, <3,4,5,6> - 2566401334U, // <6,4,5,4>: Cost 3 vext1 <2,6,4,5>, RHS - 2584318028U, // <6,4,5,5>: Cost 3 vext1 <5,6,4,5>, <5,6,4,5> - 1612287286U, // <6,4,5,6>: Cost 2 vext3 <0,2,4,6>, RHS - 2852965686U, // <6,4,5,7>: Cost 3 vuzpr <5,6,7,4>, RHS - 1612287304U, // <6,4,5,u>: Cost 2 vext3 <0,2,4,6>, RHS - 1504608358U, // <6,4,6,0>: Cost 2 vext1 <4,6,4,6>, LHS - 2578350838U, // <6,4,6,1>: Cost 3 vext1 <4,6,4,6>, <1,0,3,2> - 2578351720U, // <6,4,6,2>: Cost 3 vext1 <4,6,4,6>, <2,2,2,2> - 2578352278U, // <6,4,6,3>: Cost 3 vext1 <4,6,4,6>, <3,0,1,2> - 1504611638U, // <6,4,6,4>: Cost 2 vext1 <4,6,4,6>, RHS - 2578353872U, // <6,4,6,5>: Cost 3 vext1 <4,6,4,6>, <5,1,7,3> - 2578354682U, // <6,4,6,6>: Cost 3 vext1 <4,6,4,6>, <6,2,7,3> - 2578355194U, // <6,4,6,7>: Cost 3 vext1 <4,6,4,6>, <7,0,1,2> - 1504614190U, // <6,4,6,u>: Cost 2 vext1 <4,6,4,6>, LHS - 2572386406U, // <6,4,7,0>: Cost 3 vext1 <3,6,4,7>, LHS - 2572387226U, // <6,4,7,1>: Cost 3 vext1 <3,6,4,7>, <1,2,3,4> - 3640157902U, // <6,4,7,2>: Cost 4 vext1 <2,6,4,7>, <2,3,4,5> - 2572389020U, // <6,4,7,3>: Cost 3 vext1 <3,6,4,7>, <3,6,4,7> - 2572389686U, // <6,4,7,4>: Cost 3 vext1 <3,6,4,7>, RHS - 2980497102U, // <6,4,7,5>: Cost 3 vzipr RHS, <2,3,4,5> - 2980495564U, // <6,4,7,6>: Cost 3 vzipr RHS, <0,2,4,6> - 4054239090U, // <6,4,7,7>: Cost 4 vzipr RHS, <2,5,4,7> - 2572392238U, // <6,4,7,u>: Cost 3 vext1 <3,6,4,7>, LHS - 1504608358U, // <6,4,u,0>: Cost 2 vext1 <4,6,4,6>, LHS - 2629670702U, // <6,4,u,1>: Cost 3 vext2 <2,0,6,4>, LHS - 2566424516U, // <6,4,u,2>: Cost 3 vext1 <2,6,4,u>, <2,6,4,u> - 2584340994U, // <6,4,u,3>: Cost 3 vext1 <5,6,4,u>, <3,4,5,6> - 1640156694U, // <6,4,u,4>: Cost 2 vext3 <4,u,4,6>, <4,u,4,6> - 2629671066U, // <6,4,u,5>: Cost 3 vext2 <2,0,6,4>, RHS - 1612287529U, // <6,4,u,6>: Cost 2 vext3 <0,2,4,6>, RHS - 2852965929U, // <6,4,u,7>: Cost 3 vuzpr <5,6,7,4>, RHS - 1612287547U, // <6,4,u,u>: Cost 2 vext3 <0,2,4,6>, RHS - 3708723200U, // <6,5,0,0>: Cost 4 vext2 <2,u,6,5>, <0,0,0,0> - 2634981478U, // <6,5,0,1>: Cost 3 vext2 <2,u,6,5>, LHS - 3694125260U, // <6,5,0,2>: Cost 4 vext2 <0,4,6,5>, <0,2,4,6> - 3779087962U, // <6,5,0,3>: Cost 4 vext3 <3,4,5,6>, <5,0,3,2> - 3760877154U, // <6,5,0,4>: Cost 4 vext3 <0,4,1,6>, <5,0,4,1> - 4195110916U, // <6,5,0,5>: Cost 4 vtrnr <5,6,7,0>, <5,5,5,5> - 3696779775U, // <6,5,0,6>: Cost 4 vext2 <0,u,6,5>, <0,6,2,7> - 1175212130U, // <6,5,0,7>: Cost 2 vrev <5,6,7,0> - 1175285867U, // <6,5,0,u>: Cost 2 vrev <5,6,u,0> - 2248445988U, // <6,5,1,0>: Cost 3 vrev <5,6,0,1> - 3698107237U, // <6,5,1,1>: Cost 4 vext2 <1,1,6,5>, <1,1,6,5> - 3708724118U, // <6,5,1,2>: Cost 4 vext2 <2,u,6,5>, <1,2,3,0> - 3908575334U, // <6,5,1,3>: Cost 4 vuzpr <2,6,4,5>, LHS - 3716023376U, // <6,5,1,4>: Cost 4 vext2 <4,1,6,5>, <1,4,5,6> - 3708724368U, // <6,5,1,5>: Cost 4 vext2 <2,u,6,5>, <1,5,3,7> - 3767733960U, // <6,5,1,6>: Cost 4 vext3 <1,5,4,6>, <5,1,6,4> - 2712571600U, // <6,5,1,7>: Cost 3 vext3 <4,6,4,6>, <5,1,7,3> - 2712571609U, // <6,5,1,u>: Cost 3 vext3 <4,6,4,6>, <5,1,u,3> - 2578391142U, // <6,5,2,0>: Cost 3 vext1 <4,6,5,2>, LHS - 3704079934U, // <6,5,2,1>: Cost 4 vext2 <2,1,6,5>, <2,1,6,5> - 3708724840U, // <6,5,2,2>: Cost 4 vext2 <2,u,6,5>, <2,2,2,2> - 3705407182U, // <6,5,2,3>: Cost 4 vext2 <2,3,6,5>, <2,3,4,5> - 2578394422U, // <6,5,2,4>: Cost 3 vext1 <4,6,5,2>, RHS - 3717351272U, // <6,5,2,5>: Cost 4 vext2 <4,3,6,5>, <2,5,3,6> - 2634983354U, // <6,5,2,6>: Cost 3 vext2 <2,u,6,5>, <2,6,3,7> - 3115486518U, // <6,5,2,7>: Cost 3 vtrnr <4,6,u,2>, RHS - 2634983541U, // <6,5,2,u>: Cost 3 vext2 <2,u,6,5>, <2,u,6,5> - 3708725398U, // <6,5,3,0>: Cost 4 vext2 <2,u,6,5>, <3,0,1,2> - 3710052631U, // <6,5,3,1>: Cost 4 vext2 <3,1,6,5>, <3,1,6,5> - 3708725606U, // <6,5,3,2>: Cost 4 vext2 <2,u,6,5>, <3,2,6,3> - 3708725660U, // <6,5,3,3>: Cost 4 vext2 <2,u,6,5>, <3,3,3,3> - 2643610114U, // <6,5,3,4>: Cost 3 vext2 <4,3,6,5>, <3,4,5,6> - 3717352010U, // <6,5,3,5>: Cost 4 vext2 <4,3,6,5>, <3,5,4,6> - 3773632358U, // <6,5,3,6>: Cost 4 vext3 <2,5,3,6>, <5,3,6,0> - 2248978533U, // <6,5,3,7>: Cost 3 vrev <5,6,7,3> - 2249052270U, // <6,5,3,u>: Cost 3 vrev <5,6,u,3> - 2596323430U, // <6,5,4,0>: Cost 3 vext1 <7,6,5,4>, LHS - 3716025328U, // <6,5,4,1>: Cost 4 vext2 <4,1,6,5>, <4,1,6,5> - 3716688961U, // <6,5,4,2>: Cost 4 vext2 <4,2,6,5>, <4,2,6,5> - 2643610770U, // <6,5,4,3>: Cost 3 vext2 <4,3,6,5>, <4,3,6,5> - 2596326710U, // <6,5,4,4>: Cost 3 vext1 <7,6,5,4>, RHS - 2634984758U, // <6,5,4,5>: Cost 3 vext2 <2,u,6,5>, RHS - 3767734199U, // <6,5,4,6>: Cost 4 vext3 <1,5,4,6>, <5,4,6,0> - 1643696070U, // <6,5,4,7>: Cost 2 vext3 <5,4,7,6>, <5,4,7,6> - 1643769807U, // <6,5,4,u>: Cost 2 vext3 <5,4,u,6>, <5,4,u,6> - 2578415718U, // <6,5,5,0>: Cost 3 vext1 <4,6,5,5>, LHS - 3652158198U, // <6,5,5,1>: Cost 4 vext1 <4,6,5,5>, <1,0,3,2> - 3652159080U, // <6,5,5,2>: Cost 4 vext1 <4,6,5,5>, <2,2,2,2> - 3652159638U, // <6,5,5,3>: Cost 4 vext1 <4,6,5,5>, <3,0,1,2> - 2578418998U, // <6,5,5,4>: Cost 3 vext1 <4,6,5,5>, RHS - 2712571908U, // <6,5,5,5>: Cost 3 vext3 <4,6,4,6>, <5,5,5,5> - 2718027790U, // <6,5,5,6>: Cost 3 vext3 <5,5,6,6>, <5,5,6,6> - 2712571928U, // <6,5,5,7>: Cost 3 vext3 <4,6,4,6>, <5,5,7,7> - 2712571937U, // <6,5,5,u>: Cost 3 vext3 <4,6,4,6>, <5,5,u,7> - 2705346596U, // <6,5,6,0>: Cost 3 vext3 <3,4,5,6>, <5,6,0,1> - 3767144496U, // <6,5,6,1>: Cost 4 vext3 <1,4,5,6>, <5,6,1,4> - 3773116473U, // <6,5,6,2>: Cost 4 vext3 <2,4,5,6>, <5,6,2,4> - 2705346626U, // <6,5,6,3>: Cost 3 vext3 <3,4,5,6>, <5,6,3,4> - 2705346636U, // <6,5,6,4>: Cost 3 vext3 <3,4,5,6>, <5,6,4,5> - 3908577217U, // <6,5,6,5>: Cost 4 vuzpr <2,6,4,5>, <2,6,4,5> - 2578428728U, // <6,5,6,6>: Cost 3 vext1 <4,6,5,6>, <6,6,6,6> - 2712572002U, // <6,5,6,7>: Cost 3 vext3 <4,6,4,6>, <5,6,7,0> - 2705346668U, // <6,5,6,u>: Cost 3 vext3 <3,4,5,6>, <5,6,u,1> - 2560516198U, // <6,5,7,0>: Cost 3 vext1 <1,6,5,7>, LHS - 2560517363U, // <6,5,7,1>: Cost 3 vext1 <1,6,5,7>, <1,6,5,7> - 2566490060U, // <6,5,7,2>: Cost 3 vext1 <2,6,5,7>, <2,6,5,7> - 3634260118U, // <6,5,7,3>: Cost 4 vext1 <1,6,5,7>, <3,0,1,2> - 2560519478U, // <6,5,7,4>: Cost 3 vext1 <1,6,5,7>, RHS - 2980498650U, // <6,5,7,5>: Cost 3 vzipr RHS, <4,4,5,5> - 2980497922U, // <6,5,7,6>: Cost 3 vzipr RHS, <3,4,5,6> - 3103214902U, // <6,5,7,7>: Cost 3 vtrnr <2,6,3,7>, RHS - 2560522030U, // <6,5,7,u>: Cost 3 vext1 <1,6,5,7>, LHS - 2560524390U, // <6,5,u,0>: Cost 3 vext1 <1,6,5,u>, LHS - 2560525556U, // <6,5,u,1>: Cost 3 vext1 <1,6,5,u>, <1,6,5,u> - 2566498253U, // <6,5,u,2>: Cost 3 vext1 <2,6,5,u>, <2,6,5,u> - 2646931439U, // <6,5,u,3>: Cost 3 vext2 <4,u,6,5>, - 2560527670U, // <6,5,u,4>: Cost 3 vext1 <1,6,5,u>, RHS - 2634987674U, // <6,5,u,5>: Cost 3 vext2 <2,u,6,5>, RHS - 2980506114U, // <6,5,u,6>: Cost 3 vzipr RHS, <3,4,5,6> - 1175277674U, // <6,5,u,7>: Cost 2 vrev <5,6,7,u> - 1175351411U, // <6,5,u,u>: Cost 2 vrev <5,6,u,u> - 2578448486U, // <6,6,0,0>: Cost 3 vext1 <4,6,6,0>, LHS - 1573191782U, // <6,6,0,1>: Cost 2 vext2 <4,u,6,6>, LHS - 2686030124U, // <6,6,0,2>: Cost 3 vext3 <0,2,4,6>, <6,0,2,4> - 3779088690U, // <6,6,0,3>: Cost 4 vext3 <3,4,5,6>, <6,0,3,1> - 2687209788U, // <6,6,0,4>: Cost 3 vext3 <0,4,2,6>, <6,0,4,2> - 3652194000U, // <6,6,0,5>: Cost 4 vext1 <4,6,6,0>, <5,1,7,3> - 2254852914U, // <6,6,0,6>: Cost 3 vrev <6,6,6,0> - 4041575734U, // <6,6,0,7>: Cost 4 vzipr <2,4,6,0>, RHS - 1573192349U, // <6,6,0,u>: Cost 2 vext2 <4,u,6,6>, LHS - 2646934262U, // <6,6,1,0>: Cost 3 vext2 <4,u,6,6>, <1,0,3,2> - 2646934324U, // <6,6,1,1>: Cost 3 vext2 <4,u,6,6>, <1,1,1,1> - 2646934422U, // <6,6,1,2>: Cost 3 vext2 <4,u,6,6>, <1,2,3,0> - 2846785638U, // <6,6,1,3>: Cost 3 vuzpr <4,6,4,6>, LHS - 3760951694U, // <6,6,1,4>: Cost 4 vext3 <0,4,2,6>, <6,1,4,3> - 2646934672U, // <6,6,1,5>: Cost 3 vext2 <4,u,6,6>, <1,5,3,7> - 2712572320U, // <6,6,1,6>: Cost 3 vext3 <4,6,4,6>, <6,1,6,3> - 3775549865U, // <6,6,1,7>: Cost 4 vext3 <2,u,2,6>, <6,1,7,3> - 2846785643U, // <6,6,1,u>: Cost 3 vuzpr <4,6,4,6>, LHS - 3759772094U, // <6,6,2,0>: Cost 4 vext3 <0,2,4,6>, <6,2,0,6> - 3704751676U, // <6,6,2,1>: Cost 4 vext2 <2,2,6,6>, <2,1,6,3> - 2631009936U, // <6,6,2,2>: Cost 3 vext2 <2,2,6,6>, <2,2,6,6> - 2646935206U, // <6,6,2,3>: Cost 3 vext2 <4,u,6,6>, <2,3,0,1> - 3759772127U, // <6,6,2,4>: Cost 4 vext3 <0,2,4,6>, <6,2,4,3> - 3704752004U, // <6,6,2,5>: Cost 4 vext2 <2,2,6,6>, <2,5,6,7> - 2646935482U, // <6,6,2,6>: Cost 3 vext2 <4,u,6,6>, <2,6,3,7> - 2712572410U, // <6,6,2,7>: Cost 3 vext3 <4,6,4,6>, <6,2,7,3> - 2712572419U, // <6,6,2,u>: Cost 3 vext3 <4,6,4,6>, <6,2,u,3> - 2646935702U, // <6,6,3,0>: Cost 3 vext2 <4,u,6,6>, <3,0,1,2> - 3777024534U, // <6,6,3,1>: Cost 4 vext3 <3,1,4,6>, <6,3,1,4> - 3704752453U, // <6,6,3,2>: Cost 4 vext2 <2,2,6,6>, <3,2,2,6> - 2646935964U, // <6,6,3,3>: Cost 3 vext2 <4,u,6,6>, <3,3,3,3> - 2705347122U, // <6,6,3,4>: Cost 3 vext3 <3,4,5,6>, <6,3,4,5> - 3779678778U, // <6,6,3,5>: Cost 4 vext3 <3,5,4,6>, <6,3,5,4> - 2657553069U, // <6,6,3,6>: Cost 3 vext2 <6,6,6,6>, <3,6,6,6> - 4039609654U, // <6,6,3,7>: Cost 4 vzipr <2,1,6,3>, RHS - 2708001366U, // <6,6,3,u>: Cost 3 vext3 <3,u,5,6>, <6,3,u,5> - 2578481254U, // <6,6,4,0>: Cost 3 vext1 <4,6,6,4>, LHS - 3652223734U, // <6,6,4,1>: Cost 4 vext1 <4,6,6,4>, <1,0,3,2> - 3760951922U, // <6,6,4,2>: Cost 4 vext3 <0,4,2,6>, <6,4,2,6> - 3779089019U, // <6,6,4,3>: Cost 4 vext3 <3,4,5,6>, <6,4,3,6> - 1570540772U, // <6,6,4,4>: Cost 2 vext2 <4,4,6,6>, <4,4,6,6> - 1573195062U, // <6,6,4,5>: Cost 2 vext2 <4,u,6,6>, RHS - 2712572560U, // <6,6,4,6>: Cost 3 vext3 <4,6,4,6>, <6,4,6,0> - 2723410591U, // <6,6,4,7>: Cost 3 vext3 <6,4,7,6>, <6,4,7,6> - 1573195304U, // <6,6,4,u>: Cost 2 vext2 <4,u,6,6>, <4,u,6,6> - 3640287334U, // <6,6,5,0>: Cost 4 vext1 <2,6,6,5>, LHS - 2646937296U, // <6,6,5,1>: Cost 3 vext2 <4,u,6,6>, <5,1,7,3> - 3640289235U, // <6,6,5,2>: Cost 4 vext1 <2,6,6,5>, <2,6,6,5> - 3720679279U, // <6,6,5,3>: Cost 4 vext2 <4,u,6,6>, <5,3,7,0> - 2646937542U, // <6,6,5,4>: Cost 3 vext2 <4,u,6,6>, <5,4,7,6> - 2646937604U, // <6,6,5,5>: Cost 3 vext2 <4,u,6,6>, <5,5,5,5> - 2646937698U, // <6,6,5,6>: Cost 3 vext2 <4,u,6,6>, <5,6,7,0> - 2846788918U, // <6,6,5,7>: Cost 3 vuzpr <4,6,4,6>, RHS - 2846788919U, // <6,6,5,u>: Cost 3 vuzpr <4,6,4,6>, RHS - 1516699750U, // <6,6,6,0>: Cost 2 vext1 <6,6,6,6>, LHS - 2590442230U, // <6,6,6,1>: Cost 3 vext1 <6,6,6,6>, <1,0,3,2> - 2646938106U, // <6,6,6,2>: Cost 3 vext2 <4,u,6,6>, <6,2,7,3> - 2590443670U, // <6,6,6,3>: Cost 3 vext1 <6,6,6,6>, <3,0,1,2> - 1516703030U, // <6,6,6,4>: Cost 2 vext1 <6,6,6,6>, RHS - 2590445264U, // <6,6,6,5>: Cost 3 vext1 <6,6,6,6>, <5,1,7,3> - 296144182U, // <6,6,6,6>: Cost 1 vdup2 RHS - 2712572738U, // <6,6,6,7>: Cost 3 vext3 <4,6,4,6>, <6,6,7,7> - 296144182U, // <6,6,6,u>: Cost 1 vdup2 RHS - 2566561894U, // <6,6,7,0>: Cost 3 vext1 <2,6,6,7>, LHS - 3634332924U, // <6,6,7,1>: Cost 4 vext1 <1,6,6,7>, <1,6,6,7> - 2566563797U, // <6,6,7,2>: Cost 3 vext1 <2,6,6,7>, <2,6,6,7> - 2584480258U, // <6,6,7,3>: Cost 3 vext1 <5,6,6,7>, <3,4,5,6> - 2566565174U, // <6,6,7,4>: Cost 3 vext1 <2,6,6,7>, RHS - 2717438846U, // <6,6,7,5>: Cost 3 vext3 <5,4,7,6>, <6,7,5,4> - 2980500280U, // <6,6,7,6>: Cost 3 vzipr RHS, <6,6,6,6> - 1906756918U, // <6,6,7,7>: Cost 2 vzipr RHS, RHS - 1906756919U, // <6,6,7,u>: Cost 2 vzipr RHS, RHS - 1516699750U, // <6,6,u,0>: Cost 2 vext1 <6,6,6,6>, LHS - 1573197614U, // <6,6,u,1>: Cost 2 vext2 <4,u,6,6>, LHS - 2566571990U, // <6,6,u,2>: Cost 3 vext1 <2,6,6,u>, <2,6,6,u> - 2846786205U, // <6,6,u,3>: Cost 3 vuzpr <4,6,4,6>, LHS - 1516703030U, // <6,6,u,4>: Cost 2 vext1 <6,6,6,6>, RHS - 1573197978U, // <6,6,u,5>: Cost 2 vext2 <4,u,6,6>, RHS - 296144182U, // <6,6,u,6>: Cost 1 vdup2 RHS - 1906765110U, // <6,6,u,7>: Cost 2 vzipr RHS, RHS - 296144182U, // <6,6,u,u>: Cost 1 vdup2 RHS - 1571209216U, // <6,7,0,0>: Cost 2 vext2 RHS, <0,0,0,0> - 497467494U, // <6,7,0,1>: Cost 1 vext2 RHS, LHS - 1571209380U, // <6,7,0,2>: Cost 2 vext2 RHS, <0,2,0,2> - 2644951292U, // <6,7,0,3>: Cost 3 vext2 RHS, <0,3,1,0> - 1571209554U, // <6,7,0,4>: Cost 2 vext2 RHS, <0,4,1,5> - 1510756450U, // <6,7,0,5>: Cost 2 vext1 <5,6,7,0>, <5,6,7,0> - 2644951542U, // <6,7,0,6>: Cost 3 vext2 RHS, <0,6,1,7> - 2584499194U, // <6,7,0,7>: Cost 3 vext1 <5,6,7,0>, <7,0,1,2> - 497468061U, // <6,7,0,u>: Cost 1 vext2 RHS, LHS - 1571209974U, // <6,7,1,0>: Cost 2 vext2 RHS, <1,0,3,2> - 1571210036U, // <6,7,1,1>: Cost 2 vext2 RHS, <1,1,1,1> - 1571210134U, // <6,7,1,2>: Cost 2 vext2 RHS, <1,2,3,0> - 1571210200U, // <6,7,1,3>: Cost 2 vext2 RHS, <1,3,1,3> - 2644952098U, // <6,7,1,4>: Cost 3 vext2 RHS, <1,4,0,5> - 1571210384U, // <6,7,1,5>: Cost 2 vext2 RHS, <1,5,3,7> - 2644952271U, // <6,7,1,6>: Cost 3 vext2 RHS, <1,6,1,7> - 2578535418U, // <6,7,1,7>: Cost 3 vext1 <4,6,7,1>, <7,0,1,2> - 1571210605U, // <6,7,1,u>: Cost 2 vext2 RHS, <1,u,1,3> - 2644952509U, // <6,7,2,0>: Cost 3 vext2 RHS, <2,0,1,2> - 2644952582U, // <6,7,2,1>: Cost 3 vext2 RHS, <2,1,0,3> - 1571210856U, // <6,7,2,2>: Cost 2 vext2 RHS, <2,2,2,2> - 1571210918U, // <6,7,2,3>: Cost 2 vext2 RHS, <2,3,0,1> - 2644952828U, // <6,7,2,4>: Cost 3 vext2 RHS, <2,4,0,6> - 2633009028U, // <6,7,2,5>: Cost 3 vext2 <2,5,6,7>, <2,5,6,7> - 1571211194U, // <6,7,2,6>: Cost 2 vext2 RHS, <2,6,3,7> - 2668840938U, // <6,7,2,7>: Cost 3 vext2 RHS, <2,7,0,1> - 1571211323U, // <6,7,2,u>: Cost 2 vext2 RHS, <2,u,0,1> - 1571211414U, // <6,7,3,0>: Cost 2 vext2 RHS, <3,0,1,2> - 2644953311U, // <6,7,3,1>: Cost 3 vext2 RHS, <3,1,0,3> - 2644953390U, // <6,7,3,2>: Cost 3 vext2 RHS, <3,2,0,1> - 1571211676U, // <6,7,3,3>: Cost 2 vext2 RHS, <3,3,3,3> - 1571211778U, // <6,7,3,4>: Cost 2 vext2 RHS, <3,4,5,6> - 2644953648U, // <6,7,3,5>: Cost 3 vext2 RHS, <3,5,1,7> - 2644953720U, // <6,7,3,6>: Cost 3 vext2 RHS, <3,6,0,7> - 2644953795U, // <6,7,3,7>: Cost 3 vext2 RHS, <3,7,0,1> - 1571212062U, // <6,7,3,u>: Cost 2 vext2 RHS, <3,u,1,2> - 1573202834U, // <6,7,4,0>: Cost 2 vext2 RHS, <4,0,5,1> - 2644954058U, // <6,7,4,1>: Cost 3 vext2 RHS, <4,1,2,3> - 2644954166U, // <6,7,4,2>: Cost 3 vext2 RHS, <4,2,5,3> - 2644954258U, // <6,7,4,3>: Cost 3 vext2 RHS, <4,3,6,5> - 1571212496U, // <6,7,4,4>: Cost 2 vext2 RHS, <4,4,4,4> - 497470774U, // <6,7,4,5>: Cost 1 vext2 RHS, RHS - 1573203316U, // <6,7,4,6>: Cost 2 vext2 RHS, <4,6,4,6> - 2646281688U, // <6,7,4,7>: Cost 3 vext2 <4,7,6,7>, <4,7,6,7> - 497471017U, // <6,7,4,u>: Cost 1 vext2 RHS, RHS - 2644954696U, // <6,7,5,0>: Cost 3 vext2 RHS, <5,0,1,2> - 1573203664U, // <6,7,5,1>: Cost 2 vext2 RHS, <5,1,7,3> - 2644954878U, // <6,7,5,2>: Cost 3 vext2 RHS, <5,2,3,4> - 2644954991U, // <6,7,5,3>: Cost 3 vext2 RHS, <5,3,7,0> - 1571213254U, // <6,7,5,4>: Cost 2 vext2 RHS, <5,4,7,6> - 1571213316U, // <6,7,5,5>: Cost 2 vext2 RHS, <5,5,5,5> - 1571213410U, // <6,7,5,6>: Cost 2 vext2 RHS, <5,6,7,0> - 1573204136U, // <6,7,5,7>: Cost 2 vext2 RHS, <5,7,5,7> - 1573204217U, // <6,7,5,u>: Cost 2 vext2 RHS, <5,u,5,7> - 2644955425U, // <6,7,6,0>: Cost 3 vext2 RHS, <6,0,1,2> - 2644955561U, // <6,7,6,1>: Cost 3 vext2 RHS, <6,1,7,3> - 1573204474U, // <6,7,6,2>: Cost 2 vext2 RHS, <6,2,7,3> - 2644955698U, // <6,7,6,3>: Cost 3 vext2 RHS, <6,3,4,5> - 2644955789U, // <6,7,6,4>: Cost 3 vext2 RHS, <6,4,5,6> - 2644955889U, // <6,7,6,5>: Cost 3 vext2 RHS, <6,5,7,7> - 1571214136U, // <6,7,6,6>: Cost 2 vext2 RHS, <6,6,6,6> - 1571214158U, // <6,7,6,7>: Cost 2 vext2 RHS, <6,7,0,1> - 1573204895U, // <6,7,6,u>: Cost 2 vext2 RHS, <6,u,0,1> - 1573204986U, // <6,7,7,0>: Cost 2 vext2 RHS, <7,0,1,2> - 2572608656U, // <6,7,7,1>: Cost 3 vext1 <3,6,7,7>, <1,5,3,7> - 2644956362U, // <6,7,7,2>: Cost 3 vext2 RHS, <7,2,6,3> - 2572610231U, // <6,7,7,3>: Cost 3 vext1 <3,6,7,7>, <3,6,7,7> - 1573205350U, // <6,7,7,4>: Cost 2 vext2 RHS, <7,4,5,6> - 2646947220U, // <6,7,7,5>: Cost 3 vext2 RHS, <7,5,1,7> - 1516786498U, // <6,7,7,6>: Cost 2 vext1 <6,6,7,7>, <6,6,7,7> - 1571214956U, // <6,7,7,7>: Cost 2 vext2 RHS, <7,7,7,7> - 1573205634U, // <6,7,7,u>: Cost 2 vext2 RHS, <7,u,1,2> - 1571215059U, // <6,7,u,0>: Cost 2 vext2 RHS, - 497473326U, // <6,7,u,1>: Cost 1 vext2 RHS, LHS - 1571215237U, // <6,7,u,2>: Cost 2 vext2 RHS, - 1571215292U, // <6,7,u,3>: Cost 2 vext2 RHS, - 1571215423U, // <6,7,u,4>: Cost 2 vext2 RHS, - 497473690U, // <6,7,u,5>: Cost 1 vext2 RHS, RHS - 1571215568U, // <6,7,u,6>: Cost 2 vext2 RHS, - 1573206272U, // <6,7,u,7>: Cost 2 vext2 RHS, - 497473893U, // <6,7,u,u>: Cost 1 vext2 RHS, LHS - 1571217408U, // <6,u,0,0>: Cost 2 vext2 RHS, <0,0,0,0> - 497475686U, // <6,u,0,1>: Cost 1 vext2 RHS, LHS - 1571217572U, // <6,u,0,2>: Cost 2 vext2 RHS, <0,2,0,2> - 2689865445U, // <6,u,0,3>: Cost 3 vext3 <0,u,2,6>, - 1571217746U, // <6,u,0,4>: Cost 2 vext2 RHS, <0,4,1,5> - 1510830187U, // <6,u,0,5>: Cost 2 vext1 <5,6,u,0>, <5,6,u,0> - 2644959734U, // <6,u,0,6>: Cost 3 vext2 RHS, <0,6,1,7> - 1193130221U, // <6,u,0,7>: Cost 2 vrev - 497476253U, // <6,u,0,u>: Cost 1 vext2 RHS, LHS - 1571218166U, // <6,u,1,0>: Cost 2 vext2 RHS, <1,0,3,2> - 1571218228U, // <6,u,1,1>: Cost 2 vext2 RHS, <1,1,1,1> - 1612289838U, // <6,u,1,2>: Cost 2 vext3 <0,2,4,6>, LHS - 1571218392U, // <6,u,1,3>: Cost 2 vext2 RHS, <1,3,1,3> - 2566663478U, // <6,u,1,4>: Cost 3 vext1 <2,6,u,1>, RHS - 1571218576U, // <6,u,1,5>: Cost 2 vext2 RHS, <1,5,3,7> - 2644960463U, // <6,u,1,6>: Cost 3 vext2 RHS, <1,6,1,7> - 2717439835U, // <6,u,1,7>: Cost 3 vext3 <5,4,7,6>, - 1612289892U, // <6,u,1,u>: Cost 2 vext3 <0,2,4,6>, LHS - 1504870502U, // <6,u,2,0>: Cost 2 vext1 <4,6,u,2>, LHS - 2644960774U, // <6,u,2,1>: Cost 3 vext2 RHS, <2,1,0,3> - 1571219048U, // <6,u,2,2>: Cost 2 vext2 RHS, <2,2,2,2> - 1571219110U, // <6,u,2,3>: Cost 2 vext2 RHS, <2,3,0,1> - 1504873782U, // <6,u,2,4>: Cost 2 vext1 <4,6,u,2>, RHS - 2633017221U, // <6,u,2,5>: Cost 3 vext2 <2,5,6,u>, <2,5,6,u> - 1571219386U, // <6,u,2,6>: Cost 2 vext2 RHS, <2,6,3,7> - 2712573868U, // <6,u,2,7>: Cost 3 vext3 <4,6,4,6>, - 1571219515U, // <6,u,2,u>: Cost 2 vext2 RHS, <2,u,0,1> - 1571219606U, // <6,u,3,0>: Cost 2 vext2 RHS, <3,0,1,2> - 2644961503U, // <6,u,3,1>: Cost 3 vext2 RHS, <3,1,0,3> - 2566678499U, // <6,u,3,2>: Cost 3 vext1 <2,6,u,3>, <2,6,u,3> - 1571219868U, // <6,u,3,3>: Cost 2 vext2 RHS, <3,3,3,3> - 1571219970U, // <6,u,3,4>: Cost 2 vext2 RHS, <3,4,5,6> - 2689865711U, // <6,u,3,5>: Cost 3 vext3 <0,u,2,6>, - 2708002806U, // <6,u,3,6>: Cost 3 vext3 <3,u,5,6>, - 2644961987U, // <6,u,3,7>: Cost 3 vext2 RHS, <3,7,0,1> - 1571220254U, // <6,u,3,u>: Cost 2 vext2 RHS, <3,u,1,2> - 1571220370U, // <6,u,4,0>: Cost 2 vext2 RHS, <4,0,5,1> - 2644962250U, // <6,u,4,1>: Cost 3 vext2 RHS, <4,1,2,3> - 1661245476U, // <6,u,4,2>: Cost 2 vext3 , - 2686031917U, // <6,u,4,3>: Cost 3 vext3 <0,2,4,6>, - 1571220688U, // <6,u,4,4>: Cost 2 vext2 RHS, <4,4,4,4> - 497478967U, // <6,u,4,5>: Cost 1 vext2 RHS, RHS - 1571220852U, // <6,u,4,6>: Cost 2 vext2 RHS, <4,6,4,6> - 1661614161U, // <6,u,4,7>: Cost 2 vext3 , - 497479209U, // <6,u,4,u>: Cost 1 vext2 RHS, RHS - 2566692966U, // <6,u,5,0>: Cost 3 vext1 <2,6,u,5>, LHS - 1571221200U, // <6,u,5,1>: Cost 2 vext2 RHS, <5,1,7,3> - 2566694885U, // <6,u,5,2>: Cost 3 vext1 <2,6,u,5>, <2,6,u,5> - 2689865855U, // <6,u,5,3>: Cost 3 vext3 <0,u,2,6>, - 1571221446U, // <6,u,5,4>: Cost 2 vext2 RHS, <5,4,7,6> - 1571221508U, // <6,u,5,5>: Cost 2 vext2 RHS, <5,5,5,5> - 1612290202U, // <6,u,5,6>: Cost 2 vext3 <0,2,4,6>, RHS - 1571221672U, // <6,u,5,7>: Cost 2 vext2 RHS, <5,7,5,7> - 1612290220U, // <6,u,5,u>: Cost 2 vext3 <0,2,4,6>, RHS - 1504903270U, // <6,u,6,0>: Cost 2 vext1 <4,6,u,6>, LHS - 2644963752U, // <6,u,6,1>: Cost 3 vext2 RHS, <6,1,7,2> - 1571222010U, // <6,u,6,2>: Cost 2 vext2 RHS, <6,2,7,3> - 2686032080U, // <6,u,6,3>: Cost 3 vext3 <0,2,4,6>, - 1504906550U, // <6,u,6,4>: Cost 2 vext1 <4,6,u,6>, RHS - 2644964079U, // <6,u,6,5>: Cost 3 vext2 RHS, <6,5,7,5> - 296144182U, // <6,u,6,6>: Cost 1 vdup2 RHS - 1571222350U, // <6,u,6,7>: Cost 2 vext2 RHS, <6,7,0,1> - 296144182U, // <6,u,6,u>: Cost 1 vdup2 RHS - 1492967526U, // <6,u,7,0>: Cost 2 vext1 <2,6,u,7>, LHS - 2560738574U, // <6,u,7,1>: Cost 3 vext1 <1,6,u,7>, <1,6,u,7> - 1492969447U, // <6,u,7,2>: Cost 2 vext1 <2,6,u,7>, <2,6,u,7> - 1906753692U, // <6,u,7,3>: Cost 2 vzipr RHS, LHS - 1492970806U, // <6,u,7,4>: Cost 2 vext1 <2,6,u,7>, RHS - 2980495761U, // <6,u,7,5>: Cost 3 vzipr RHS, <0,4,u,5> - 1516860235U, // <6,u,7,6>: Cost 2 vext1 <6,6,u,7>, <6,6,u,7> - 1906756936U, // <6,u,7,7>: Cost 2 vzipr RHS, RHS - 1492973358U, // <6,u,7,u>: Cost 2 vext1 <2,6,u,7>, LHS - 1492975718U, // <6,u,u,0>: Cost 2 vext1 <2,6,u,u>, LHS - 497481518U, // <6,u,u,1>: Cost 1 vext2 RHS, LHS - 1612290405U, // <6,u,u,2>: Cost 2 vext3 <0,2,4,6>, LHS - 1571223484U, // <6,u,u,3>: Cost 2 vext2 RHS, - 1492978998U, // <6,u,u,4>: Cost 2 vext1 <2,6,u,u>, RHS - 497481882U, // <6,u,u,5>: Cost 1 vext2 RHS, RHS - 296144182U, // <6,u,u,6>: Cost 1 vdup2 RHS - 1906765128U, // <6,u,u,7>: Cost 2 vzipr RHS, RHS - 497482085U, // <6,u,u,u>: Cost 1 vext2 RHS, LHS - 1638318080U, // <7,0,0,0>: Cost 2 vext3 RHS, <0,0,0,0> - 1638318090U, // <7,0,0,1>: Cost 2 vext3 RHS, <0,0,1,1> - 1638318100U, // <7,0,0,2>: Cost 2 vext3 RHS, <0,0,2,2> - 3646442178U, // <7,0,0,3>: Cost 4 vext1 <3,7,0,0>, <3,7,0,0> - 2712059941U, // <7,0,0,4>: Cost 3 vext3 RHS, <0,0,4,1> - 2651603364U, // <7,0,0,5>: Cost 3 vext2 <5,6,7,0>, <0,5,1,6> - 2590618445U, // <7,0,0,6>: Cost 3 vext1 <6,7,0,0>, <6,7,0,0> - 3785801798U, // <7,0,0,7>: Cost 4 vext3 RHS, <0,0,7,7> - 1638318153U, // <7,0,0,u>: Cost 2 vext3 RHS, <0,0,u,1> - 1516879974U, // <7,0,1,0>: Cost 2 vext1 <6,7,0,1>, LHS - 2693922911U, // <7,0,1,1>: Cost 3 vext3 <1,5,3,7>, <0,1,1,5> - 564576358U, // <7,0,1,2>: Cost 1 vext3 RHS, LHS - 2638996480U, // <7,0,1,3>: Cost 3 vext2 <3,5,7,0>, <1,3,5,7> - 1516883254U, // <7,0,1,4>: Cost 2 vext1 <6,7,0,1>, RHS - 2649613456U, // <7,0,1,5>: Cost 3 vext2 <5,3,7,0>, <1,5,3,7> - 1516884814U, // <7,0,1,6>: Cost 2 vext1 <6,7,0,1>, <6,7,0,1> - 2590626808U, // <7,0,1,7>: Cost 3 vext1 <6,7,0,1>, <7,0,1,0> - 564576412U, // <7,0,1,u>: Cost 1 vext3 RHS, LHS - 1638318244U, // <7,0,2,0>: Cost 2 vext3 RHS, <0,2,0,2> - 2692743344U, // <7,0,2,1>: Cost 3 vext3 <1,3,5,7>, <0,2,1,5> - 2712060084U, // <7,0,2,2>: Cost 3 vext3 RHS, <0,2,2,0> - 2712060094U, // <7,0,2,3>: Cost 3 vext3 RHS, <0,2,3,1> - 1638318284U, // <7,0,2,4>: Cost 2 vext3 RHS, <0,2,4,6> - 2712060118U, // <7,0,2,5>: Cost 3 vext3 RHS, <0,2,5,7> - 2651604922U, // <7,0,2,6>: Cost 3 vext2 <5,6,7,0>, <2,6,3,7> - 2686255336U, // <7,0,2,7>: Cost 3 vext3 <0,2,7,7>, <0,2,7,7> - 1638318316U, // <7,0,2,u>: Cost 2 vext3 RHS, <0,2,u,2> - 2651605142U, // <7,0,3,0>: Cost 3 vext2 <5,6,7,0>, <3,0,1,2> - 2712060156U, // <7,0,3,1>: Cost 3 vext3 RHS, <0,3,1,0> - 2712060165U, // <7,0,3,2>: Cost 3 vext3 RHS, <0,3,2,0> - 2651605404U, // <7,0,3,3>: Cost 3 vext2 <5,6,7,0>, <3,3,3,3> - 2651605506U, // <7,0,3,4>: Cost 3 vext2 <5,6,7,0>, <3,4,5,6> - 2638998111U, // <7,0,3,5>: Cost 3 vext2 <3,5,7,0>, <3,5,7,0> - 2639661744U, // <7,0,3,6>: Cost 3 vext2 <3,6,7,0>, <3,6,7,0> - 3712740068U, // <7,0,3,7>: Cost 4 vext2 <3,5,7,0>, <3,7,3,7> - 2640989010U, // <7,0,3,u>: Cost 3 vext2 <3,u,7,0>, <3,u,7,0> - 2712060232U, // <7,0,4,0>: Cost 3 vext3 RHS, <0,4,0,4> - 1638318418U, // <7,0,4,1>: Cost 2 vext3 RHS, <0,4,1,5> - 1638318428U, // <7,0,4,2>: Cost 2 vext3 RHS, <0,4,2,6> - 3646474950U, // <7,0,4,3>: Cost 4 vext1 <3,7,0,4>, <3,7,0,4> - 2712060270U, // <7,0,4,4>: Cost 3 vext3 RHS, <0,4,4,6> - 1577864502U, // <7,0,4,5>: Cost 2 vext2 <5,6,7,0>, RHS - 2651606388U, // <7,0,4,6>: Cost 3 vext2 <5,6,7,0>, <4,6,4,6> - 3787792776U, // <7,0,4,7>: Cost 4 vext3 RHS, <0,4,7,5> - 1638318481U, // <7,0,4,u>: Cost 2 vext3 RHS, <0,4,u,5> - 2590654566U, // <7,0,5,0>: Cost 3 vext1 <6,7,0,5>, LHS - 2651606736U, // <7,0,5,1>: Cost 3 vext2 <5,6,7,0>, <5,1,7,3> - 2712060334U, // <7,0,5,2>: Cost 3 vext3 RHS, <0,5,2,7> - 2649616239U, // <7,0,5,3>: Cost 3 vext2 <5,3,7,0>, <5,3,7,0> - 2651606982U, // <7,0,5,4>: Cost 3 vext2 <5,6,7,0>, <5,4,7,6> - 2651607044U, // <7,0,5,5>: Cost 3 vext2 <5,6,7,0>, <5,5,5,5> - 1577865314U, // <7,0,5,6>: Cost 2 vext2 <5,6,7,0>, <5,6,7,0> - 2651607208U, // <7,0,5,7>: Cost 3 vext2 <5,6,7,0>, <5,7,5,7> - 1579192580U, // <7,0,5,u>: Cost 2 vext2 <5,u,7,0>, <5,u,7,0> - 2688393709U, // <7,0,6,0>: Cost 3 vext3 <0,6,0,7>, <0,6,0,7> - 2712060406U, // <7,0,6,1>: Cost 3 vext3 RHS, <0,6,1,7> - 2688541183U, // <7,0,6,2>: Cost 3 vext3 <0,6,2,7>, <0,6,2,7> - 2655588936U, // <7,0,6,3>: Cost 3 vext2 <6,3,7,0>, <6,3,7,0> - 3762430481U, // <7,0,6,4>: Cost 4 vext3 <0,6,4,7>, <0,6,4,7> - 2651607730U, // <7,0,6,5>: Cost 3 vext2 <5,6,7,0>, <6,5,0,7> - 2651607864U, // <7,0,6,6>: Cost 3 vext2 <5,6,7,0>, <6,6,6,6> - 2651607886U, // <7,0,6,7>: Cost 3 vext2 <5,6,7,0>, <6,7,0,1> - 2688983605U, // <7,0,6,u>: Cost 3 vext3 <0,6,u,7>, <0,6,u,7> - 2651608058U, // <7,0,7,0>: Cost 3 vext2 <5,6,7,0>, <7,0,1,2> - 2932703334U, // <7,0,7,1>: Cost 3 vzipl <7,7,7,7>, LHS - 3066921062U, // <7,0,7,2>: Cost 3 vtrnl <7,7,7,7>, LHS - 3712742678U, // <7,0,7,3>: Cost 4 vext2 <3,5,7,0>, <7,3,5,7> - 2651608422U, // <7,0,7,4>: Cost 3 vext2 <5,6,7,0>, <7,4,5,6> - 2651608513U, // <7,0,7,5>: Cost 3 vext2 <5,6,7,0>, <7,5,6,7> - 2663552532U, // <7,0,7,6>: Cost 3 vext2 <7,6,7,0>, <7,6,7,0> - 2651608684U, // <7,0,7,7>: Cost 3 vext2 <5,6,7,0>, <7,7,7,7> - 2651608706U, // <7,0,7,u>: Cost 3 vext2 <5,6,7,0>, <7,u,1,2> - 1638318730U, // <7,0,u,0>: Cost 2 vext3 RHS, <0,u,0,2> - 1638318738U, // <7,0,u,1>: Cost 2 vext3 RHS, <0,u,1,1> - 564576925U, // <7,0,u,2>: Cost 1 vext3 RHS, LHS - 2572765898U, // <7,0,u,3>: Cost 3 vext1 <3,7,0,u>, <3,7,0,u> - 1638318770U, // <7,0,u,4>: Cost 2 vext3 RHS, <0,u,4,6> - 1577867418U, // <7,0,u,5>: Cost 2 vext2 <5,6,7,0>, RHS - 1516942165U, // <7,0,u,6>: Cost 2 vext1 <6,7,0,u>, <6,7,0,u> - 2651609344U, // <7,0,u,7>: Cost 3 vext2 <5,6,7,0>, - 564576979U, // <7,0,u,u>: Cost 1 vext3 RHS, LHS - 2590687334U, // <7,1,0,0>: Cost 3 vext1 <6,7,1,0>, LHS - 2639003750U, // <7,1,0,1>: Cost 3 vext2 <3,5,7,1>, LHS - 2793357414U, // <7,1,0,2>: Cost 3 vuzpl <7,0,1,2>, LHS - 1638318838U, // <7,1,0,3>: Cost 2 vext3 RHS, <1,0,3,2> - 2590690614U, // <7,1,0,4>: Cost 3 vext1 <6,7,1,0>, RHS - 2712060679U, // <7,1,0,5>: Cost 3 vext3 RHS, <1,0,5,1> - 2590692182U, // <7,1,0,6>: Cost 3 vext1 <6,7,1,0>, <6,7,1,0> - 3785802521U, // <7,1,0,7>: Cost 4 vext3 RHS, <1,0,7,1> - 1638318883U, // <7,1,0,u>: Cost 2 vext3 RHS, <1,0,u,2> - 2712060715U, // <7,1,1,0>: Cost 3 vext3 RHS, <1,1,0,1> - 1638318900U, // <7,1,1,1>: Cost 2 vext3 RHS, <1,1,1,1> - 3774300994U, // <7,1,1,2>: Cost 4 vext3 <2,6,3,7>, <1,1,2,6> - 1638318920U, // <7,1,1,3>: Cost 2 vext3 RHS, <1,1,3,3> - 2712060755U, // <7,1,1,4>: Cost 3 vext3 RHS, <1,1,4,5> - 2691416926U, // <7,1,1,5>: Cost 3 vext3 <1,1,5,7>, <1,1,5,7> - 2590700375U, // <7,1,1,6>: Cost 3 vext1 <6,7,1,1>, <6,7,1,1> - 3765158766U, // <7,1,1,7>: Cost 4 vext3 <1,1,5,7>, <1,1,7,5> - 1638318965U, // <7,1,1,u>: Cost 2 vext3 RHS, <1,1,u,3> - 2712060796U, // <7,1,2,0>: Cost 3 vext3 RHS, <1,2,0,1> - 2712060807U, // <7,1,2,1>: Cost 3 vext3 RHS, <1,2,1,3> - 3712747112U, // <7,1,2,2>: Cost 4 vext2 <3,5,7,1>, <2,2,2,2> - 1638318998U, // <7,1,2,3>: Cost 2 vext3 RHS, <1,2,3,0> - 2712060836U, // <7,1,2,4>: Cost 3 vext3 RHS, <1,2,4,5> - 2712060843U, // <7,1,2,5>: Cost 3 vext3 RHS, <1,2,5,3> - 2590708568U, // <7,1,2,6>: Cost 3 vext1 <6,7,1,2>, <6,7,1,2> - 2735948730U, // <7,1,2,7>: Cost 3 vext3 RHS, <1,2,7,0> - 1638319043U, // <7,1,2,u>: Cost 2 vext3 RHS, <1,2,u,0> - 2712060876U, // <7,1,3,0>: Cost 3 vext3 RHS, <1,3,0,0> - 1638319064U, // <7,1,3,1>: Cost 2 vext3 RHS, <1,3,1,3> - 2712060894U, // <7,1,3,2>: Cost 3 vext3 RHS, <1,3,2,0> - 2692596718U, // <7,1,3,3>: Cost 3 vext3 <1,3,3,7>, <1,3,3,7> - 2712060917U, // <7,1,3,4>: Cost 3 vext3 RHS, <1,3,4,5> - 1619002368U, // <7,1,3,5>: Cost 2 vext3 <1,3,5,7>, <1,3,5,7> - 2692817929U, // <7,1,3,6>: Cost 3 vext3 <1,3,6,7>, <1,3,6,7> - 2735948814U, // <7,1,3,7>: Cost 3 vext3 RHS, <1,3,7,3> - 1619223579U, // <7,1,3,u>: Cost 2 vext3 <1,3,u,7>, <1,3,u,7> - 2712060962U, // <7,1,4,0>: Cost 3 vext3 RHS, <1,4,0,5> - 2712060971U, // <7,1,4,1>: Cost 3 vext3 RHS, <1,4,1,5> - 2712060980U, // <7,1,4,2>: Cost 3 vext3 RHS, <1,4,2,5> - 2712060989U, // <7,1,4,3>: Cost 3 vext3 RHS, <1,4,3,5> - 3785802822U, // <7,1,4,4>: Cost 4 vext3 RHS, <1,4,4,5> - 2639007030U, // <7,1,4,5>: Cost 3 vext2 <3,5,7,1>, RHS - 2645642634U, // <7,1,4,6>: Cost 3 vext2 <4,6,7,1>, <4,6,7,1> - 3719384520U, // <7,1,4,7>: Cost 4 vext2 <4,6,7,1>, <4,7,5,0> - 2639007273U, // <7,1,4,u>: Cost 3 vext2 <3,5,7,1>, RHS - 2572812390U, // <7,1,5,0>: Cost 3 vext1 <3,7,1,5>, LHS - 2693776510U, // <7,1,5,1>: Cost 3 vext3 <1,5,1,7>, <1,5,1,7> - 3774301318U, // <7,1,5,2>: Cost 4 vext3 <2,6,3,7>, <1,5,2,6> - 1620182160U, // <7,1,5,3>: Cost 2 vext3 <1,5,3,7>, <1,5,3,7> - 2572815670U, // <7,1,5,4>: Cost 3 vext1 <3,7,1,5>, RHS - 3766486178U, // <7,1,5,5>: Cost 4 vext3 <1,3,5,7>, <1,5,5,7> - 2651615331U, // <7,1,5,6>: Cost 3 vext2 <5,6,7,1>, <5,6,7,1> - 2652278964U, // <7,1,5,7>: Cost 3 vext2 <5,7,7,1>, <5,7,7,1> - 1620550845U, // <7,1,5,u>: Cost 2 vext3 <1,5,u,7>, <1,5,u,7> - 3768108230U, // <7,1,6,0>: Cost 4 vext3 <1,6,0,7>, <1,6,0,7> - 2694440143U, // <7,1,6,1>: Cost 3 vext3 <1,6,1,7>, <1,6,1,7> - 2712061144U, // <7,1,6,2>: Cost 3 vext3 RHS, <1,6,2,7> - 2694587617U, // <7,1,6,3>: Cost 3 vext3 <1,6,3,7>, <1,6,3,7> - 3768403178U, // <7,1,6,4>: Cost 4 vext3 <1,6,4,7>, <1,6,4,7> - 2694735091U, // <7,1,6,5>: Cost 3 vext3 <1,6,5,7>, <1,6,5,7> - 3768550652U, // <7,1,6,6>: Cost 4 vext3 <1,6,6,7>, <1,6,6,7> - 2652279630U, // <7,1,6,7>: Cost 3 vext2 <5,7,7,1>, <6,7,0,1> - 2694956302U, // <7,1,6,u>: Cost 3 vext3 <1,6,u,7>, <1,6,u,7> - 2645644282U, // <7,1,7,0>: Cost 3 vext2 <4,6,7,1>, <7,0,1,2> - 2859062094U, // <7,1,7,1>: Cost 3 vuzpr <6,7,0,1>, <6,7,0,1> - 3779462437U, // <7,1,7,2>: Cost 4 vext3 <3,5,1,7>, <1,7,2,3> - 3121938534U, // <7,1,7,3>: Cost 3 vtrnr <5,7,5,7>, LHS - 2554916150U, // <7,1,7,4>: Cost 3 vext1 <0,7,1,7>, RHS - 3769140548U, // <7,1,7,5>: Cost 4 vext3 <1,7,5,7>, <1,7,5,7> - 3726022164U, // <7,1,7,6>: Cost 4 vext2 <5,7,7,1>, <7,6,7,0> - 2554918508U, // <7,1,7,7>: Cost 3 vext1 <0,7,1,7>, <7,7,7,7> - 3121938539U, // <7,1,7,u>: Cost 3 vtrnr <5,7,5,7>, LHS - 2572836966U, // <7,1,u,0>: Cost 3 vext1 <3,7,1,u>, LHS - 1638319469U, // <7,1,u,1>: Cost 2 vext3 RHS, <1,u,1,3> - 2712061299U, // <7,1,u,2>: Cost 3 vext3 RHS, <1,u,2,0> - 1622173059U, // <7,1,u,3>: Cost 2 vext3 <1,u,3,7>, <1,u,3,7> - 2572840246U, // <7,1,u,4>: Cost 3 vext1 <3,7,1,u>, RHS - 1622320533U, // <7,1,u,5>: Cost 2 vext3 <1,u,5,7>, <1,u,5,7> - 2696136094U, // <7,1,u,6>: Cost 3 vext3 <1,u,6,7>, <1,u,6,7> - 2859060777U, // <7,1,u,7>: Cost 3 vuzpr <6,7,0,1>, RHS - 1622541744U, // <7,1,u,u>: Cost 2 vext3 <1,u,u,7>, <1,u,u,7> - 2712061364U, // <7,2,0,0>: Cost 3 vext3 RHS, <2,0,0,2> - 2712061373U, // <7,2,0,1>: Cost 3 vext3 RHS, <2,0,1,2> - 2712061380U, // <7,2,0,2>: Cost 3 vext3 RHS, <2,0,2,0> - 2712061389U, // <7,2,0,3>: Cost 3 vext3 RHS, <2,0,3,0> - 2712061404U, // <7,2,0,4>: Cost 3 vext3 RHS, <2,0,4,6> - 2696725990U, // <7,2,0,5>: Cost 3 vext3 <2,0,5,7>, <2,0,5,7> - 2712061417U, // <7,2,0,6>: Cost 3 vext3 RHS, <2,0,6,1> - 3785803251U, // <7,2,0,7>: Cost 4 vext3 RHS, <2,0,7,2> - 2696947201U, // <7,2,0,u>: Cost 3 vext3 <2,0,u,7>, <2,0,u,7> - 2712061446U, // <7,2,1,0>: Cost 3 vext3 RHS, <2,1,0,3> - 3785803276U, // <7,2,1,1>: Cost 4 vext3 RHS, <2,1,1,0> - 3785803285U, // <7,2,1,2>: Cost 4 vext3 RHS, <2,1,2,0> - 2712061471U, // <7,2,1,3>: Cost 3 vext3 RHS, <2,1,3,1> - 2712061482U, // <7,2,1,4>: Cost 3 vext3 RHS, <2,1,4,3> - 3766486576U, // <7,2,1,5>: Cost 4 vext3 <1,3,5,7>, <2,1,5,0> - 2712061500U, // <7,2,1,6>: Cost 3 vext3 RHS, <2,1,6,3> - 2602718850U, // <7,2,1,7>: Cost 3 vext1 , <7,u,1,2> - 2712061516U, // <7,2,1,u>: Cost 3 vext3 RHS, <2,1,u,1> - 2712061525U, // <7,2,2,0>: Cost 3 vext3 RHS, <2,2,0,1> - 2712061536U, // <7,2,2,1>: Cost 3 vext3 RHS, <2,2,1,3> - 1638319720U, // <7,2,2,2>: Cost 2 vext3 RHS, <2,2,2,2> - 1638319730U, // <7,2,2,3>: Cost 2 vext3 RHS, <2,2,3,3> - 2712061565U, // <7,2,2,4>: Cost 3 vext3 RHS, <2,2,4,5> - 2698053256U, // <7,2,2,5>: Cost 3 vext3 <2,2,5,7>, <2,2,5,7> - 2712061584U, // <7,2,2,6>: Cost 3 vext3 RHS, <2,2,6,6> - 3771795096U, // <7,2,2,7>: Cost 4 vext3 <2,2,5,7>, <2,2,7,5> - 1638319775U, // <7,2,2,u>: Cost 2 vext3 RHS, <2,2,u,3> - 1638319782U, // <7,2,3,0>: Cost 2 vext3 RHS, <2,3,0,1> - 2693924531U, // <7,2,3,1>: Cost 3 vext3 <1,5,3,7>, <2,3,1,5> - 2700560061U, // <7,2,3,2>: Cost 3 vext3 <2,6,3,7>, <2,3,2,6> - 2693924551U, // <7,2,3,3>: Cost 3 vext3 <1,5,3,7>, <2,3,3,7> - 1638319822U, // <7,2,3,4>: Cost 2 vext3 RHS, <2,3,4,5> - 2698716889U, // <7,2,3,5>: Cost 3 vext3 <2,3,5,7>, <2,3,5,7> - 2712061665U, // <7,2,3,6>: Cost 3 vext3 RHS, <2,3,6,6> - 2735949540U, // <7,2,3,7>: Cost 3 vext3 RHS, <2,3,7,0> - 1638319854U, // <7,2,3,u>: Cost 2 vext3 RHS, <2,3,u,1> - 2712061692U, // <7,2,4,0>: Cost 3 vext3 RHS, <2,4,0,6> - 2712061698U, // <7,2,4,1>: Cost 3 vext3 RHS, <2,4,1,3> - 2712061708U, // <7,2,4,2>: Cost 3 vext3 RHS, <2,4,2,4> - 2712061718U, // <7,2,4,3>: Cost 3 vext3 RHS, <2,4,3,5> - 2712061728U, // <7,2,4,4>: Cost 3 vext3 RHS, <2,4,4,6> - 2699380522U, // <7,2,4,5>: Cost 3 vext3 <2,4,5,7>, <2,4,5,7> - 2712061740U, // <7,2,4,6>: Cost 3 vext3 RHS, <2,4,6,0> - 3809691445U, // <7,2,4,7>: Cost 4 vext3 RHS, <2,4,7,0> - 2699601733U, // <7,2,4,u>: Cost 3 vext3 <2,4,u,7>, <2,4,u,7> - 2699675470U, // <7,2,5,0>: Cost 3 vext3 <2,5,0,7>, <2,5,0,7> - 3766486867U, // <7,2,5,1>: Cost 4 vext3 <1,3,5,7>, <2,5,1,3> - 2699822944U, // <7,2,5,2>: Cost 3 vext3 <2,5,2,7>, <2,5,2,7> - 2692745065U, // <7,2,5,3>: Cost 3 vext3 <1,3,5,7>, <2,5,3,7> - 2699970418U, // <7,2,5,4>: Cost 3 vext3 <2,5,4,7>, <2,5,4,7> - 3766486907U, // <7,2,5,5>: Cost 4 vext3 <1,3,5,7>, <2,5,5,7> - 2700117892U, // <7,2,5,6>: Cost 3 vext3 <2,5,6,7>, <2,5,6,7> - 3771795334U, // <7,2,5,7>: Cost 4 vext3 <2,2,5,7>, <2,5,7,0> - 2692745110U, // <7,2,5,u>: Cost 3 vext3 <1,3,5,7>, <2,5,u,7> - 2572894310U, // <7,2,6,0>: Cost 3 vext1 <3,7,2,6>, LHS - 2712061860U, // <7,2,6,1>: Cost 3 vext3 RHS, <2,6,1,3> - 2700486577U, // <7,2,6,2>: Cost 3 vext3 <2,6,2,7>, <2,6,2,7> - 1626818490U, // <7,2,6,3>: Cost 2 vext3 <2,6,3,7>, <2,6,3,7> - 2572897590U, // <7,2,6,4>: Cost 3 vext1 <3,7,2,6>, RHS - 2700707788U, // <7,2,6,5>: Cost 3 vext3 <2,6,5,7>, <2,6,5,7> - 2700781525U, // <7,2,6,6>: Cost 3 vext3 <2,6,6,7>, <2,6,6,7> - 3774597086U, // <7,2,6,7>: Cost 4 vext3 <2,6,7,7>, <2,6,7,7> - 1627187175U, // <7,2,6,u>: Cost 2 vext3 <2,6,u,7>, <2,6,u,7> - 2735949802U, // <7,2,7,0>: Cost 3 vext3 RHS, <2,7,0,1> - 3780200434U, // <7,2,7,1>: Cost 4 vext3 <3,6,2,7>, <2,7,1,0> - 3773564928U, // <7,2,7,2>: Cost 4 vext3 <2,5,2,7>, <2,7,2,5> - 2986541158U, // <7,2,7,3>: Cost 3 vzipr <5,5,7,7>, LHS - 2554989878U, // <7,2,7,4>: Cost 3 vext1 <0,7,2,7>, RHS - 3775113245U, // <7,2,7,5>: Cost 4 vext3 <2,7,5,7>, <2,7,5,7> - 4060283228U, // <7,2,7,6>: Cost 4 vzipr <5,5,7,7>, <0,4,2,6> - 2554992236U, // <7,2,7,7>: Cost 3 vext1 <0,7,2,7>, <7,7,7,7> - 2986541163U, // <7,2,7,u>: Cost 3 vzipr <5,5,7,7>, LHS - 1638320187U, // <7,2,u,0>: Cost 2 vext3 RHS, <2,u,0,1> - 2693924936U, // <7,2,u,1>: Cost 3 vext3 <1,5,3,7>, <2,u,1,5> - 1638319720U, // <7,2,u,2>: Cost 2 vext3 RHS, <2,2,2,2> - 1628145756U, // <7,2,u,3>: Cost 2 vext3 <2,u,3,7>, <2,u,3,7> - 1638320227U, // <7,2,u,4>: Cost 2 vext3 RHS, <2,u,4,5> - 2702035054U, // <7,2,u,5>: Cost 3 vext3 <2,u,5,7>, <2,u,5,7> - 2702108791U, // <7,2,u,6>: Cost 3 vext3 <2,u,6,7>, <2,u,6,7> - 2735949945U, // <7,2,u,7>: Cost 3 vext3 RHS, <2,u,7,0> - 1628514441U, // <7,2,u,u>: Cost 2 vext3 <2,u,u,7>, <2,u,u,7> - 2712062091U, // <7,3,0,0>: Cost 3 vext3 RHS, <3,0,0,0> - 1638320278U, // <7,3,0,1>: Cost 2 vext3 RHS, <3,0,1,2> - 2712062109U, // <7,3,0,2>: Cost 3 vext3 RHS, <3,0,2,0> - 2590836886U, // <7,3,0,3>: Cost 3 vext1 <6,7,3,0>, <3,0,1,2> - 2712062128U, // <7,3,0,4>: Cost 3 vext3 RHS, <3,0,4,1> - 2712062138U, // <7,3,0,5>: Cost 3 vext3 RHS, <3,0,5,2> - 2590839656U, // <7,3,0,6>: Cost 3 vext1 <6,7,3,0>, <6,7,3,0> - 3311414017U, // <7,3,0,7>: Cost 4 vrev <3,7,7,0> - 1638320341U, // <7,3,0,u>: Cost 2 vext3 RHS, <3,0,u,2> - 2237164227U, // <7,3,1,0>: Cost 3 vrev <3,7,0,1> - 2712062182U, // <7,3,1,1>: Cost 3 vext3 RHS, <3,1,1,1> - 2712062193U, // <7,3,1,2>: Cost 3 vext3 RHS, <3,1,2,3> - 2692745468U, // <7,3,1,3>: Cost 3 vext3 <1,3,5,7>, <3,1,3,5> - 2712062214U, // <7,3,1,4>: Cost 3 vext3 RHS, <3,1,4,6> - 2693925132U, // <7,3,1,5>: Cost 3 vext3 <1,5,3,7>, <3,1,5,3> - 3768183059U, // <7,3,1,6>: Cost 4 vext3 <1,6,1,7>, <3,1,6,1> - 2692745504U, // <7,3,1,7>: Cost 3 vext3 <1,3,5,7>, <3,1,7,5> - 2696063273U, // <7,3,1,u>: Cost 3 vext3 <1,u,5,7>, <3,1,u,5> - 2712062254U, // <7,3,2,0>: Cost 3 vext3 RHS, <3,2,0,1> - 2712062262U, // <7,3,2,1>: Cost 3 vext3 RHS, <3,2,1,0> - 2712062273U, // <7,3,2,2>: Cost 3 vext3 RHS, <3,2,2,2> - 2712062280U, // <7,3,2,3>: Cost 3 vext3 RHS, <3,2,3,0> - 2712062294U, // <7,3,2,4>: Cost 3 vext3 RHS, <3,2,4,5> - 2712062302U, // <7,3,2,5>: Cost 3 vext3 RHS, <3,2,5,4> - 2700560742U, // <7,3,2,6>: Cost 3 vext3 <2,6,3,7>, <3,2,6,3> - 2712062319U, // <7,3,2,7>: Cost 3 vext3 RHS, <3,2,7,3> - 2712062325U, // <7,3,2,u>: Cost 3 vext3 RHS, <3,2,u,0> - 2712062335U, // <7,3,3,0>: Cost 3 vext3 RHS, <3,3,0,1> - 2636368158U, // <7,3,3,1>: Cost 3 vext2 <3,1,7,3>, <3,1,7,3> - 2637031791U, // <7,3,3,2>: Cost 3 vext2 <3,2,7,3>, <3,2,7,3> - 1638320540U, // <7,3,3,3>: Cost 2 vext3 RHS, <3,3,3,3> - 2712062374U, // <7,3,3,4>: Cost 3 vext3 RHS, <3,3,4,4> - 2704689586U, // <7,3,3,5>: Cost 3 vext3 <3,3,5,7>, <3,3,5,7> - 2590864235U, // <7,3,3,6>: Cost 3 vext1 <6,7,3,3>, <6,7,3,3> - 2704837060U, // <7,3,3,7>: Cost 3 vext3 <3,3,7,7>, <3,3,7,7> - 1638320540U, // <7,3,3,u>: Cost 2 vext3 RHS, <3,3,3,3> - 2712062416U, // <7,3,4,0>: Cost 3 vext3 RHS, <3,4,0,1> - 2712062426U, // <7,3,4,1>: Cost 3 vext3 RHS, <3,4,1,2> - 2566981640U, // <7,3,4,2>: Cost 3 vext1 <2,7,3,4>, <2,7,3,4> - 2712062447U, // <7,3,4,3>: Cost 3 vext3 RHS, <3,4,3,5> - 2712062456U, // <7,3,4,4>: Cost 3 vext3 RHS, <3,4,4,5> - 1638320642U, // <7,3,4,5>: Cost 2 vext3 RHS, <3,4,5,6> - 2648313204U, // <7,3,4,6>: Cost 3 vext2 <5,1,7,3>, <4,6,4,6> - 3311446789U, // <7,3,4,7>: Cost 4 vrev <3,7,7,4> - 1638320669U, // <7,3,4,u>: Cost 2 vext3 RHS, <3,4,u,6> - 2602819686U, // <7,3,5,0>: Cost 3 vext1 , LHS - 1574571728U, // <7,3,5,1>: Cost 2 vext2 <5,1,7,3>, <5,1,7,3> - 2648977185U, // <7,3,5,2>: Cost 3 vext2 <5,2,7,3>, <5,2,7,3> - 2705869378U, // <7,3,5,3>: Cost 3 vext3 <3,5,3,7>, <3,5,3,7> - 2237491947U, // <7,3,5,4>: Cost 3 vrev <3,7,4,5> - 2706016852U, // <7,3,5,5>: Cost 3 vext3 <3,5,5,7>, <3,5,5,7> - 2648313954U, // <7,3,5,6>: Cost 3 vext2 <5,1,7,3>, <5,6,7,0> - 2692745823U, // <7,3,5,7>: Cost 3 vext3 <1,3,5,7>, <3,5,7,0> - 1579217159U, // <7,3,5,u>: Cost 2 vext2 <5,u,7,3>, <5,u,7,3> - 2706311800U, // <7,3,6,0>: Cost 3 vext3 <3,6,0,7>, <3,6,0,7> - 2654286249U, // <7,3,6,1>: Cost 3 vext2 <6,1,7,3>, <6,1,7,3> - 1581208058U, // <7,3,6,2>: Cost 2 vext2 <6,2,7,3>, <6,2,7,3> - 2706533011U, // <7,3,6,3>: Cost 3 vext3 <3,6,3,7>, <3,6,3,7> - 2706606748U, // <7,3,6,4>: Cost 3 vext3 <3,6,4,7>, <3,6,4,7> - 3780422309U, // <7,3,6,5>: Cost 4 vext3 <3,6,5,7>, <3,6,5,7> - 2712062637U, // <7,3,6,6>: Cost 3 vext3 RHS, <3,6,6,6> - 2706827959U, // <7,3,6,7>: Cost 3 vext3 <3,6,7,7>, <3,6,7,7> - 1585189856U, // <7,3,6,u>: Cost 2 vext2 <6,u,7,3>, <6,u,7,3> - 2693925571U, // <7,3,7,0>: Cost 3 vext3 <1,5,3,7>, <3,7,0,1> - 2693925584U, // <7,3,7,1>: Cost 3 vext3 <1,5,3,7>, <3,7,1,5> - 2700561114U, // <7,3,7,2>: Cost 3 vext3 <2,6,3,7>, <3,7,2,6> - 2572978916U, // <7,3,7,3>: Cost 3 vext1 <3,7,3,7>, <3,7,3,7> - 2693925611U, // <7,3,7,4>: Cost 3 vext3 <1,5,3,7>, <3,7,4,5> - 2707344118U, // <7,3,7,5>: Cost 3 vext3 <3,7,5,7>, <3,7,5,7> - 2654950894U, // <7,3,7,6>: Cost 3 vext2 <6,2,7,3>, <7,6,2,7> - 2648315500U, // <7,3,7,7>: Cost 3 vext2 <5,1,7,3>, <7,7,7,7> - 2693925643U, // <7,3,7,u>: Cost 3 vext3 <1,5,3,7>, <3,7,u,1> - 2237221578U, // <7,3,u,0>: Cost 3 vrev <3,7,0,u> - 1638320926U, // <7,3,u,1>: Cost 2 vext3 RHS, <3,u,1,2> - 1593153452U, // <7,3,u,2>: Cost 2 vext2 , - 1638320540U, // <7,3,u,3>: Cost 2 vext3 RHS, <3,3,3,3> - 2237516526U, // <7,3,u,4>: Cost 3 vrev <3,7,4,u> - 1638320966U, // <7,3,u,5>: Cost 2 vext3 RHS, <3,u,5,6> - 2712062796U, // <7,3,u,6>: Cost 3 vext3 RHS, <3,u,6,3> - 2692967250U, // <7,3,u,7>: Cost 3 vext3 <1,3,u,7>, <3,u,7,0> - 1638320989U, // <7,3,u,u>: Cost 2 vext3 RHS, <3,u,u,2> - 2651635712U, // <7,4,0,0>: Cost 3 vext2 <5,6,7,4>, <0,0,0,0> - 1577893990U, // <7,4,0,1>: Cost 2 vext2 <5,6,7,4>, LHS - 2651635876U, // <7,4,0,2>: Cost 3 vext2 <5,6,7,4>, <0,2,0,2> - 3785804672U, // <7,4,0,3>: Cost 4 vext3 RHS, <4,0,3,1> - 2651636050U, // <7,4,0,4>: Cost 3 vext2 <5,6,7,4>, <0,4,1,5> - 1638468498U, // <7,4,0,5>: Cost 2 vext3 RHS, <4,0,5,1> - 1638468508U, // <7,4,0,6>: Cost 2 vext3 RHS, <4,0,6,2> - 3787795364U, // <7,4,0,7>: Cost 4 vext3 RHS, <4,0,7,1> - 1640459181U, // <7,4,0,u>: Cost 2 vext3 RHS, <4,0,u,1> - 2651636470U, // <7,4,1,0>: Cost 3 vext2 <5,6,7,4>, <1,0,3,2> - 2651636532U, // <7,4,1,1>: Cost 3 vext2 <5,6,7,4>, <1,1,1,1> - 2712062922U, // <7,4,1,2>: Cost 3 vext3 RHS, <4,1,2,3> - 2639029248U, // <7,4,1,3>: Cost 3 vext2 <3,5,7,4>, <1,3,5,7> - 2712062940U, // <7,4,1,4>: Cost 3 vext3 RHS, <4,1,4,3> - 2712062946U, // <7,4,1,5>: Cost 3 vext3 RHS, <4,1,5,0> - 2712062958U, // <7,4,1,6>: Cost 3 vext3 RHS, <4,1,6,3> - 3785804791U, // <7,4,1,7>: Cost 4 vext3 RHS, <4,1,7,3> - 2712062973U, // <7,4,1,u>: Cost 3 vext3 RHS, <4,1,u,0> - 3785804807U, // <7,4,2,0>: Cost 4 vext3 RHS, <4,2,0,1> - 3785804818U, // <7,4,2,1>: Cost 4 vext3 RHS, <4,2,1,3> - 2651637352U, // <7,4,2,2>: Cost 3 vext2 <5,6,7,4>, <2,2,2,2> - 2651637414U, // <7,4,2,3>: Cost 3 vext2 <5,6,7,4>, <2,3,0,1> - 3716753194U, // <7,4,2,4>: Cost 4 vext2 <4,2,7,4>, <2,4,5,7> - 2712063030U, // <7,4,2,5>: Cost 3 vext3 RHS, <4,2,5,3> - 2712063036U, // <7,4,2,6>: Cost 3 vext3 RHS, <4,2,6,0> - 3773123658U, // <7,4,2,7>: Cost 4 vext3 <2,4,5,7>, <4,2,7,5> - 2712063054U, // <7,4,2,u>: Cost 3 vext3 RHS, <4,2,u,0> - 2651637910U, // <7,4,3,0>: Cost 3 vext2 <5,6,7,4>, <3,0,1,2> - 3712772348U, // <7,4,3,1>: Cost 4 vext2 <3,5,7,4>, <3,1,3,5> - 3785804906U, // <7,4,3,2>: Cost 4 vext3 RHS, <4,3,2,1> - 2651638172U, // <7,4,3,3>: Cost 3 vext2 <5,6,7,4>, <3,3,3,3> - 2651638274U, // <7,4,3,4>: Cost 3 vext2 <5,6,7,4>, <3,4,5,6> - 2639030883U, // <7,4,3,5>: Cost 3 vext2 <3,5,7,4>, <3,5,7,4> - 2712063122U, // <7,4,3,6>: Cost 3 vext3 RHS, <4,3,6,5> - 3712772836U, // <7,4,3,7>: Cost 4 vext2 <3,5,7,4>, <3,7,3,7> - 2641021782U, // <7,4,3,u>: Cost 3 vext2 <3,u,7,4>, <3,u,7,4> - 2714053802U, // <7,4,4,0>: Cost 3 vext3 RHS, <4,4,0,2> - 3785804978U, // <7,4,4,1>: Cost 4 vext3 RHS, <4,4,1,1> - 3716754505U, // <7,4,4,2>: Cost 4 vext2 <4,2,7,4>, <4,2,7,4> - 3785804998U, // <7,4,4,3>: Cost 4 vext3 RHS, <4,4,3,3> - 1638321360U, // <7,4,4,4>: Cost 2 vext3 RHS, <4,4,4,4> - 1638468826U, // <7,4,4,5>: Cost 2 vext3 RHS, <4,4,5,5> - 1638468836U, // <7,4,4,6>: Cost 2 vext3 RHS, <4,4,6,6> - 3785215214U, // <7,4,4,7>: Cost 4 vext3 <4,4,7,7>, <4,4,7,7> - 1640459509U, // <7,4,4,u>: Cost 2 vext3 RHS, <4,4,u,5> - 1517207654U, // <7,4,5,0>: Cost 2 vext1 <6,7,4,5>, LHS - 2573034640U, // <7,4,5,1>: Cost 3 vext1 <3,7,4,5>, <1,5,3,7> - 2712063246U, // <7,4,5,2>: Cost 3 vext3 RHS, <4,5,2,3> - 2573036267U, // <7,4,5,3>: Cost 3 vext1 <3,7,4,5>, <3,7,4,5> - 1517210934U, // <7,4,5,4>: Cost 2 vext1 <6,7,4,5>, RHS - 2711989549U, // <7,4,5,5>: Cost 3 vext3 <4,5,5,7>, <4,5,5,7> - 564579638U, // <7,4,5,6>: Cost 1 vext3 RHS, RHS - 2651639976U, // <7,4,5,7>: Cost 3 vext2 <5,6,7,4>, <5,7,5,7> - 564579656U, // <7,4,5,u>: Cost 1 vext3 RHS, RHS - 2712063307U, // <7,4,6,0>: Cost 3 vext3 RHS, <4,6,0,1> - 3767668056U, // <7,4,6,1>: Cost 4 vext3 <1,5,3,7>, <4,6,1,5> - 2651640314U, // <7,4,6,2>: Cost 3 vext2 <5,6,7,4>, <6,2,7,3> - 2655621708U, // <7,4,6,3>: Cost 3 vext2 <6,3,7,4>, <6,3,7,4> - 1638468980U, // <7,4,6,4>: Cost 2 vext3 RHS, <4,6,4,6> - 2712063358U, // <7,4,6,5>: Cost 3 vext3 RHS, <4,6,5,7> - 2712063367U, // <7,4,6,6>: Cost 3 vext3 RHS, <4,6,6,7> - 2712210826U, // <7,4,6,7>: Cost 3 vext3 RHS, <4,6,7,1> - 1638469012U, // <7,4,6,u>: Cost 2 vext3 RHS, <4,6,u,2> - 2651640826U, // <7,4,7,0>: Cost 3 vext2 <5,6,7,4>, <7,0,1,2> - 3773713830U, // <7,4,7,1>: Cost 4 vext3 <2,5,4,7>, <4,7,1,2> - 3773713842U, // <7,4,7,2>: Cost 4 vext3 <2,5,4,7>, <4,7,2,5> - 3780349372U, // <7,4,7,3>: Cost 4 vext3 <3,6,4,7>, <4,7,3,6> - 2651641140U, // <7,4,7,4>: Cost 3 vext2 <5,6,7,4>, <7,4,0,1> - 2712210888U, // <7,4,7,5>: Cost 3 vext3 RHS, <4,7,5,0> - 2712210898U, // <7,4,7,6>: Cost 3 vext3 RHS, <4,7,6,1> - 2651641452U, // <7,4,7,7>: Cost 3 vext2 <5,6,7,4>, <7,7,7,7> - 2713538026U, // <7,4,7,u>: Cost 3 vext3 <4,7,u,7>, <4,7,u,7> - 1517232230U, // <7,4,u,0>: Cost 2 vext1 <6,7,4,u>, LHS - 1577899822U, // <7,4,u,1>: Cost 2 vext2 <5,6,7,4>, LHS - 2712063489U, // <7,4,u,2>: Cost 3 vext3 RHS, <4,u,2,3> - 2573060846U, // <7,4,u,3>: Cost 3 vext1 <3,7,4,u>, <3,7,4,u> - 1640312342U, // <7,4,u,4>: Cost 2 vext3 RHS, <4,u,4,6> - 1638469146U, // <7,4,u,5>: Cost 2 vext3 RHS, <4,u,5,1> - 564579881U, // <7,4,u,6>: Cost 1 vext3 RHS, RHS - 2714054192U, // <7,4,u,7>: Cost 3 vext3 RHS, <4,u,7,5> - 564579899U, // <7,4,u,u>: Cost 1 vext3 RHS, RHS - 2579038310U, // <7,5,0,0>: Cost 3 vext1 <4,7,5,0>, LHS - 2636382310U, // <7,5,0,1>: Cost 3 vext2 <3,1,7,5>, LHS - 2796339302U, // <7,5,0,2>: Cost 3 vuzpl <7,4,5,6>, LHS - 3646810719U, // <7,5,0,3>: Cost 4 vext1 <3,7,5,0>, <3,5,7,0> - 2712063586U, // <7,5,0,4>: Cost 3 vext3 RHS, <5,0,4,1> - 2735951467U, // <7,5,0,5>: Cost 3 vext3 RHS, <5,0,5,1> - 2735951476U, // <7,5,0,6>: Cost 3 vext3 RHS, <5,0,6,1> - 2579043322U, // <7,5,0,7>: Cost 3 vext1 <4,7,5,0>, <7,0,1,2> - 2636382877U, // <7,5,0,u>: Cost 3 vext2 <3,1,7,5>, LHS - 2712211087U, // <7,5,1,0>: Cost 3 vext3 RHS, <5,1,0,1> - 3698180916U, // <7,5,1,1>: Cost 4 vext2 <1,1,7,5>, <1,1,1,1> - 3710124950U, // <7,5,1,2>: Cost 4 vext2 <3,1,7,5>, <1,2,3,0> - 2636383232U, // <7,5,1,3>: Cost 3 vext2 <3,1,7,5>, <1,3,5,7> - 2712211127U, // <7,5,1,4>: Cost 3 vext3 RHS, <5,1,4,5> - 2590994128U, // <7,5,1,5>: Cost 3 vext1 <6,7,5,1>, <5,1,7,3> - 2590995323U, // <7,5,1,6>: Cost 3 vext1 <6,7,5,1>, <6,7,5,1> - 1638469328U, // <7,5,1,7>: Cost 2 vext3 RHS, <5,1,7,3> - 1638469337U, // <7,5,1,u>: Cost 2 vext3 RHS, <5,1,u,3> - 3785805536U, // <7,5,2,0>: Cost 4 vext3 RHS, <5,2,0,1> - 3785805544U, // <7,5,2,1>: Cost 4 vext3 RHS, <5,2,1,0> - 3704817288U, // <7,5,2,2>: Cost 4 vext2 <2,2,7,5>, <2,2,5,7> - 2712063742U, // <7,5,2,3>: Cost 3 vext3 RHS, <5,2,3,4> - 3716761386U, // <7,5,2,4>: Cost 4 vext2 <4,2,7,5>, <2,4,5,7> - 2714054415U, // <7,5,2,5>: Cost 3 vext3 RHS, <5,2,5,3> - 3774304024U, // <7,5,2,6>: Cost 4 vext3 <2,6,3,7>, <5,2,6,3> - 2712063777U, // <7,5,2,7>: Cost 3 vext3 RHS, <5,2,7,3> - 2712063787U, // <7,5,2,u>: Cost 3 vext3 RHS, <5,2,u,4> - 3634888806U, // <7,5,3,0>: Cost 4 vext1 <1,7,5,3>, LHS - 2636384544U, // <7,5,3,1>: Cost 3 vext2 <3,1,7,5>, <3,1,7,5> - 3710790001U, // <7,5,3,2>: Cost 4 vext2 <3,2,7,5>, <3,2,7,5> - 3710126492U, // <7,5,3,3>: Cost 4 vext2 <3,1,7,5>, <3,3,3,3> - 3634892086U, // <7,5,3,4>: Cost 4 vext1 <1,7,5,3>, RHS - 2639039076U, // <7,5,3,5>: Cost 3 vext2 <3,5,7,5>, <3,5,7,5> - 3713444533U, // <7,5,3,6>: Cost 4 vext2 <3,6,7,5>, <3,6,7,5> - 2693926767U, // <7,5,3,7>: Cost 3 vext3 <1,5,3,7>, <5,3,7,0> - 2712063864U, // <7,5,3,u>: Cost 3 vext3 RHS, <5,3,u,0> - 2579071078U, // <7,5,4,0>: Cost 3 vext1 <4,7,5,4>, LHS - 3646841856U, // <7,5,4,1>: Cost 4 vext1 <3,7,5,4>, <1,3,5,7> - 3716762698U, // <7,5,4,2>: Cost 4 vext2 <4,2,7,5>, <4,2,7,5> - 3646843491U, // <7,5,4,3>: Cost 4 vext1 <3,7,5,4>, <3,5,7,4> - 2579074358U, // <7,5,4,4>: Cost 3 vext1 <4,7,5,4>, RHS - 2636385590U, // <7,5,4,5>: Cost 3 vext2 <3,1,7,5>, RHS - 2645675406U, // <7,5,4,6>: Cost 3 vext2 <4,6,7,5>, <4,6,7,5> - 1638322118U, // <7,5,4,7>: Cost 2 vext3 RHS, <5,4,7,6> - 1638469583U, // <7,5,4,u>: Cost 2 vext3 RHS, <5,4,u,6> - 2714054611U, // <7,5,5,0>: Cost 3 vext3 RHS, <5,5,0,1> - 2652974800U, // <7,5,5,1>: Cost 3 vext2 <5,u,7,5>, <5,1,7,3> - 3710127905U, // <7,5,5,2>: Cost 4 vext2 <3,1,7,5>, <5,2,7,3> - 3785805808U, // <7,5,5,3>: Cost 4 vext3 RHS, <5,5,3,3> - 2712211450U, // <7,5,5,4>: Cost 3 vext3 RHS, <5,5,4,4> - 1638322180U, // <7,5,5,5>: Cost 2 vext3 RHS, <5,5,5,5> - 2712064014U, // <7,5,5,6>: Cost 3 vext3 RHS, <5,5,6,6> - 1638469656U, // <7,5,5,7>: Cost 2 vext3 RHS, <5,5,7,7> - 1638469665U, // <7,5,5,u>: Cost 2 vext3 RHS, <5,5,u,7> - 2712064036U, // <7,5,6,0>: Cost 3 vext3 RHS, <5,6,0,1> - 2714054707U, // <7,5,6,1>: Cost 3 vext3 RHS, <5,6,1,7> - 3785805879U, // <7,5,6,2>: Cost 4 vext3 RHS, <5,6,2,2> - 2712064066U, // <7,5,6,3>: Cost 3 vext3 RHS, <5,6,3,4> - 2712064076U, // <7,5,6,4>: Cost 3 vext3 RHS, <5,6,4,5> - 2714054743U, // <7,5,6,5>: Cost 3 vext3 RHS, <5,6,5,7> - 2712064096U, // <7,5,6,6>: Cost 3 vext3 RHS, <5,6,6,7> - 1638322274U, // <7,5,6,7>: Cost 2 vext3 RHS, <5,6,7,0> - 1638469739U, // <7,5,6,u>: Cost 2 vext3 RHS, <5,6,u,0> - 1511325798U, // <7,5,7,0>: Cost 2 vext1 <5,7,5,7>, LHS - 2692747392U, // <7,5,7,1>: Cost 3 vext3 <1,3,5,7>, <5,7,1,3> - 2585069160U, // <7,5,7,2>: Cost 3 vext1 <5,7,5,7>, <2,2,2,2> - 2573126390U, // <7,5,7,3>: Cost 3 vext1 <3,7,5,7>, <3,7,5,7> - 1511329078U, // <7,5,7,4>: Cost 2 vext1 <5,7,5,7>, RHS - 1638469800U, // <7,5,7,5>: Cost 2 vext3 RHS, <5,7,5,7> - 2712211626U, // <7,5,7,6>: Cost 3 vext3 RHS, <5,7,6,0> - 2712211636U, // <7,5,7,7>: Cost 3 vext3 RHS, <5,7,7,1> - 1638469823U, // <7,5,7,u>: Cost 2 vext3 RHS, <5,7,u,3> - 1511333990U, // <7,5,u,0>: Cost 2 vext1 <5,7,5,u>, LHS - 2636388142U, // <7,5,u,1>: Cost 3 vext2 <3,1,7,5>, LHS - 2712211671U, // <7,5,u,2>: Cost 3 vext3 RHS, <5,u,2,0> - 2573134583U, // <7,5,u,3>: Cost 3 vext1 <3,7,5,u>, <3,7,5,u> - 1511337270U, // <7,5,u,4>: Cost 2 vext1 <5,7,5,u>, RHS - 1638469881U, // <7,5,u,5>: Cost 2 vext3 RHS, <5,u,5,7> - 2712064258U, // <7,5,u,6>: Cost 3 vext3 RHS, <5,u,6,7> - 1638469892U, // <7,5,u,7>: Cost 2 vext3 RHS, <5,u,7,0> - 1638469904U, // <7,5,u,u>: Cost 2 vext3 RHS, <5,u,u,3> - 2650324992U, // <7,6,0,0>: Cost 3 vext2 <5,4,7,6>, <0,0,0,0> - 1576583270U, // <7,6,0,1>: Cost 2 vext2 <5,4,7,6>, LHS - 2712064300U, // <7,6,0,2>: Cost 3 vext3 RHS, <6,0,2,4> - 2255295336U, // <7,6,0,3>: Cost 3 vrev <6,7,3,0> - 2712064316U, // <7,6,0,4>: Cost 3 vext3 RHS, <6,0,4,2> - 2585088098U, // <7,6,0,5>: Cost 3 vext1 <5,7,6,0>, <5,6,7,0> - 2735952204U, // <7,6,0,6>: Cost 3 vext3 RHS, <6,0,6,0> - 2712211799U, // <7,6,0,7>: Cost 3 vext3 RHS, <6,0,7,2> - 1576583837U, // <7,6,0,u>: Cost 2 vext2 <5,4,7,6>, LHS - 1181340494U, // <7,6,1,0>: Cost 2 vrev <6,7,0,1> - 2650325812U, // <7,6,1,1>: Cost 3 vext2 <5,4,7,6>, <1,1,1,1> - 2650325910U, // <7,6,1,2>: Cost 3 vext2 <5,4,7,6>, <1,2,3,0> - 2650325976U, // <7,6,1,3>: Cost 3 vext2 <5,4,7,6>, <1,3,1,3> - 2579123510U, // <7,6,1,4>: Cost 3 vext1 <4,7,6,1>, RHS - 2650326160U, // <7,6,1,5>: Cost 3 vext2 <5,4,7,6>, <1,5,3,7> - 2714055072U, // <7,6,1,6>: Cost 3 vext3 RHS, <6,1,6,3> - 2712064425U, // <7,6,1,7>: Cost 3 vext3 RHS, <6,1,7,3> - 1181930390U, // <7,6,1,u>: Cost 2 vrev <6,7,u,1> - 2712211897U, // <7,6,2,0>: Cost 3 vext3 RHS, <6,2,0,1> - 2714055108U, // <7,6,2,1>: Cost 3 vext3 RHS, <6,2,1,3> - 2650326632U, // <7,6,2,2>: Cost 3 vext2 <5,4,7,6>, <2,2,2,2> - 2650326694U, // <7,6,2,3>: Cost 3 vext2 <5,4,7,6>, <2,3,0,1> - 2714055137U, // <7,6,2,4>: Cost 3 vext3 RHS, <6,2,4,5> - 2714055148U, // <7,6,2,5>: Cost 3 vext3 RHS, <6,2,5,7> - 2650326970U, // <7,6,2,6>: Cost 3 vext2 <5,4,7,6>, <2,6,3,7> - 1638470138U, // <7,6,2,7>: Cost 2 vext3 RHS, <6,2,7,3> - 1638470147U, // <7,6,2,u>: Cost 2 vext3 RHS, <6,2,u,3> - 2650327190U, // <7,6,3,0>: Cost 3 vext2 <5,4,7,6>, <3,0,1,2> - 2255172441U, // <7,6,3,1>: Cost 3 vrev <6,7,1,3> - 2255246178U, // <7,6,3,2>: Cost 3 vrev <6,7,2,3> - 2650327452U, // <7,6,3,3>: Cost 3 vext2 <5,4,7,6>, <3,3,3,3> - 2712064562U, // <7,6,3,4>: Cost 3 vext3 RHS, <6,3,4,5> - 2650327627U, // <7,6,3,5>: Cost 3 vext2 <5,4,7,6>, <3,5,4,7> - 3713452726U, // <7,6,3,6>: Cost 4 vext2 <3,6,7,6>, <3,6,7,6> - 2700563016U, // <7,6,3,7>: Cost 3 vext3 <2,6,3,7>, <6,3,7,0> - 2712064593U, // <7,6,3,u>: Cost 3 vext3 RHS, <6,3,u,0> - 2650327954U, // <7,6,4,0>: Cost 3 vext2 <5,4,7,6>, <4,0,5,1> - 2735952486U, // <7,6,4,1>: Cost 3 vext3 RHS, <6,4,1,3> - 2735952497U, // <7,6,4,2>: Cost 3 vext3 RHS, <6,4,2,5> - 2255328108U, // <7,6,4,3>: Cost 3 vrev <6,7,3,4> - 2712212100U, // <7,6,4,4>: Cost 3 vext3 RHS, <6,4,4,6> - 1576586550U, // <7,6,4,5>: Cost 2 vext2 <5,4,7,6>, RHS - 2714055312U, // <7,6,4,6>: Cost 3 vext3 RHS, <6,4,6,0> - 2712212126U, // <7,6,4,7>: Cost 3 vext3 RHS, <6,4,7,5> - 1576586793U, // <7,6,4,u>: Cost 2 vext2 <5,4,7,6>, RHS - 2579152998U, // <7,6,5,0>: Cost 3 vext1 <4,7,6,5>, LHS - 2650328784U, // <7,6,5,1>: Cost 3 vext2 <5,4,7,6>, <5,1,7,3> - 2714055364U, // <7,6,5,2>: Cost 3 vext3 RHS, <6,5,2,7> - 3785806538U, // <7,6,5,3>: Cost 4 vext3 RHS, <6,5,3,4> - 1576587206U, // <7,6,5,4>: Cost 2 vext2 <5,4,7,6>, <5,4,7,6> - 2650329092U, // <7,6,5,5>: Cost 3 vext2 <5,4,7,6>, <5,5,5,5> - 2650329186U, // <7,6,5,6>: Cost 3 vext2 <5,4,7,6>, <5,6,7,0> - 2712064753U, // <7,6,5,7>: Cost 3 vext3 RHS, <6,5,7,7> - 1181963162U, // <7,6,5,u>: Cost 2 vrev <6,7,u,5> - 2714055421U, // <7,6,6,0>: Cost 3 vext3 RHS, <6,6,0,1> - 2714055432U, // <7,6,6,1>: Cost 3 vext3 RHS, <6,6,1,3> - 2650329594U, // <7,6,6,2>: Cost 3 vext2 <5,4,7,6>, <6,2,7,3> - 3785806619U, // <7,6,6,3>: Cost 4 vext3 RHS, <6,6,3,4> - 2712212260U, // <7,6,6,4>: Cost 3 vext3 RHS, <6,6,4,4> - 2714055472U, // <7,6,6,5>: Cost 3 vext3 RHS, <6,6,5,7> - 1638323000U, // <7,6,6,6>: Cost 2 vext3 RHS, <6,6,6,6> - 1638470466U, // <7,6,6,7>: Cost 2 vext3 RHS, <6,6,7,7> - 1638470475U, // <7,6,6,u>: Cost 2 vext3 RHS, <6,6,u,7> - 1638323022U, // <7,6,7,0>: Cost 2 vext3 RHS, <6,7,0,1> - 2712064854U, // <7,6,7,1>: Cost 3 vext3 RHS, <6,7,1,0> - 2712064865U, // <7,6,7,2>: Cost 3 vext3 RHS, <6,7,2,2> - 2712064872U, // <7,6,7,3>: Cost 3 vext3 RHS, <6,7,3,0> - 1638323062U, // <7,6,7,4>: Cost 2 vext3 RHS, <6,7,4,5> - 2712064894U, // <7,6,7,5>: Cost 3 vext3 RHS, <6,7,5,4> - 2712064905U, // <7,6,7,6>: Cost 3 vext3 RHS, <6,7,6,6> - 2712064915U, // <7,6,7,7>: Cost 3 vext3 RHS, <6,7,7,7> - 1638323094U, // <7,6,7,u>: Cost 2 vext3 RHS, <6,7,u,1> - 1638470559U, // <7,6,u,0>: Cost 2 vext3 RHS, <6,u,0,1> - 1576589102U, // <7,6,u,1>: Cost 2 vext2 <5,4,7,6>, LHS - 2712212402U, // <7,6,u,2>: Cost 3 vext3 RHS, <6,u,2,2> - 2712212409U, // <7,6,u,3>: Cost 3 vext3 RHS, <6,u,3,0> - 1638470599U, // <7,6,u,4>: Cost 2 vext3 RHS, <6,u,4,5> - 1576589466U, // <7,6,u,5>: Cost 2 vext2 <5,4,7,6>, RHS - 1638323000U, // <7,6,u,6>: Cost 2 vext3 RHS, <6,6,6,6> - 1638470624U, // <7,6,u,7>: Cost 2 vext3 RHS, <6,u,7,3> - 1638470631U, // <7,6,u,u>: Cost 2 vext3 RHS, <6,u,u,1> - 2712065007U, // <7,7,0,0>: Cost 3 vext3 RHS, <7,0,0,0> - 1638323194U, // <7,7,0,1>: Cost 2 vext3 RHS, <7,0,1,2> - 2712065025U, // <7,7,0,2>: Cost 3 vext3 RHS, <7,0,2,0> - 3646958337U, // <7,7,0,3>: Cost 4 vext1 <3,7,7,0>, <3,7,7,0> - 2712065044U, // <7,7,0,4>: Cost 3 vext3 RHS, <7,0,4,1> - 2585161907U, // <7,7,0,5>: Cost 3 vext1 <5,7,7,0>, <5,7,7,0> - 2591134604U, // <7,7,0,6>: Cost 3 vext1 <6,7,7,0>, <6,7,7,0> - 2591134714U, // <7,7,0,7>: Cost 3 vext1 <6,7,7,0>, <7,0,1,2> - 1638323257U, // <7,7,0,u>: Cost 2 vext3 RHS, <7,0,u,2> - 2712065091U, // <7,7,1,0>: Cost 3 vext3 RHS, <7,1,0,3> - 2712065098U, // <7,7,1,1>: Cost 3 vext3 RHS, <7,1,1,1> - 2712065109U, // <7,7,1,2>: Cost 3 vext3 RHS, <7,1,2,3> - 2692748384U, // <7,7,1,3>: Cost 3 vext3 <1,3,5,7>, <7,1,3,5> - 2585169206U, // <7,7,1,4>: Cost 3 vext1 <5,7,7,1>, RHS - 2693928048U, // <7,7,1,5>: Cost 3 vext3 <1,5,3,7>, <7,1,5,3> - 2585170766U, // <7,7,1,6>: Cost 3 vext1 <5,7,7,1>, <6,7,0,1> - 2735953024U, // <7,7,1,7>: Cost 3 vext3 RHS, <7,1,7,1> - 2695918731U, // <7,7,1,u>: Cost 3 vext3 <1,u,3,7>, <7,1,u,3> - 3770471574U, // <7,7,2,0>: Cost 4 vext3 <2,0,5,7>, <7,2,0,5> - 3785807002U, // <7,7,2,1>: Cost 4 vext3 RHS, <7,2,1,0> - 2712065189U, // <7,7,2,2>: Cost 3 vext3 RHS, <7,2,2,2> - 2712065196U, // <7,7,2,3>: Cost 3 vext3 RHS, <7,2,3,0> - 3773125818U, // <7,7,2,4>: Cost 4 vext3 <2,4,5,7>, <7,2,4,5> - 3766490305U, // <7,7,2,5>: Cost 4 vext3 <1,3,5,7>, <7,2,5,3> - 2700563658U, // <7,7,2,6>: Cost 3 vext3 <2,6,3,7>, <7,2,6,3> - 2735953107U, // <7,7,2,7>: Cost 3 vext3 RHS, <7,2,7,3> - 2701890780U, // <7,7,2,u>: Cost 3 vext3 <2,u,3,7>, <7,2,u,3> - 2712065251U, // <7,7,3,0>: Cost 3 vext3 RHS, <7,3,0,1> - 3766490350U, // <7,7,3,1>: Cost 4 vext3 <1,3,5,7>, <7,3,1,3> - 3774305530U, // <7,7,3,2>: Cost 4 vext3 <2,6,3,7>, <7,3,2,6> - 2637728196U, // <7,7,3,3>: Cost 3 vext2 <3,3,7,7>, <3,3,7,7> - 2712065291U, // <7,7,3,4>: Cost 3 vext3 RHS, <7,3,4,5> - 2585186486U, // <7,7,3,5>: Cost 3 vext1 <5,7,7,3>, <5,7,7,3> - 2639719095U, // <7,7,3,6>: Cost 3 vext2 <3,6,7,7>, <3,6,7,7> - 2640382728U, // <7,7,3,7>: Cost 3 vext2 <3,7,7,7>, <3,7,7,7> - 2641046361U, // <7,7,3,u>: Cost 3 vext2 <3,u,7,7>, <3,u,7,7> - 2712212792U, // <7,7,4,0>: Cost 3 vext3 RHS, <7,4,0,5> - 3646989312U, // <7,7,4,1>: Cost 4 vext1 <3,7,7,4>, <1,3,5,7> - 3785807176U, // <7,7,4,2>: Cost 4 vext3 RHS, <7,4,2,3> - 3646991109U, // <7,7,4,3>: Cost 4 vext1 <3,7,7,4>, <3,7,7,4> - 2712065371U, // <7,7,4,4>: Cost 3 vext3 RHS, <7,4,4,4> - 1638323558U, // <7,7,4,5>: Cost 2 vext3 RHS, <7,4,5,6> - 2712212845U, // <7,7,4,6>: Cost 3 vext3 RHS, <7,4,6,4> - 2591167846U, // <7,7,4,7>: Cost 3 vext1 <6,7,7,4>, <7,4,5,6> - 1638323585U, // <7,7,4,u>: Cost 2 vext3 RHS, <7,4,u,6> - 2585198694U, // <7,7,5,0>: Cost 3 vext1 <5,7,7,5>, LHS - 2712212884U, // <7,7,5,1>: Cost 3 vext3 RHS, <7,5,1,7> - 3711471393U, // <7,7,5,2>: Cost 4 vext2 <3,3,7,7>, <5,2,7,3> - 2649673590U, // <7,7,5,3>: Cost 3 vext2 <5,3,7,7>, <5,3,7,7> - 2712065455U, // <7,7,5,4>: Cost 3 vext3 RHS, <7,5,4,7> - 1577259032U, // <7,7,5,5>: Cost 2 vext2 <5,5,7,7>, <5,5,7,7> - 2712065473U, // <7,7,5,6>: Cost 3 vext3 RHS, <7,5,6,7> - 2712212936U, // <7,7,5,7>: Cost 3 vext3 RHS, <7,5,7,5> - 1579249931U, // <7,7,5,u>: Cost 2 vext2 <5,u,7,7>, <5,u,7,7> - 2591178854U, // <7,7,6,0>: Cost 3 vext1 <6,7,7,6>, LHS - 2735953374U, // <7,7,6,1>: Cost 3 vext3 RHS, <7,6,1,0> - 2712212974U, // <7,7,6,2>: Cost 3 vext3 RHS, <7,6,2,7> - 2655646287U, // <7,7,6,3>: Cost 3 vext2 <6,3,7,7>, <6,3,7,7> - 2591182134U, // <7,7,6,4>: Cost 3 vext1 <6,7,7,6>, RHS - 2656973553U, // <7,7,6,5>: Cost 3 vext2 <6,5,7,7>, <6,5,7,7> - 1583895362U, // <7,7,6,6>: Cost 2 vext2 <6,6,7,7>, <6,6,7,7> - 2712065556U, // <7,7,6,7>: Cost 3 vext3 RHS, <7,6,7,0> - 1585222628U, // <7,7,6,u>: Cost 2 vext2 <6,u,7,7>, <6,u,7,7> - 1523417190U, // <7,7,7,0>: Cost 2 vext1 <7,7,7,7>, LHS - 2597159670U, // <7,7,7,1>: Cost 3 vext1 <7,7,7,7>, <1,0,3,2> - 2597160552U, // <7,7,7,2>: Cost 3 vext1 <7,7,7,7>, <2,2,2,2> - 2597161110U, // <7,7,7,3>: Cost 3 vext1 <7,7,7,7>, <3,0,1,2> - 1523420470U, // <7,7,7,4>: Cost 2 vext1 <7,7,7,7>, RHS - 2651002296U, // <7,7,7,5>: Cost 3 vext2 <5,5,7,7>, <7,5,5,7> - 2657637906U, // <7,7,7,6>: Cost 3 vext2 <6,6,7,7>, <7,6,6,7> - 363253046U, // <7,7,7,7>: Cost 1 vdup3 RHS - 363253046U, // <7,7,7,u>: Cost 1 vdup3 RHS - 1523417190U, // <7,7,u,0>: Cost 2 vext1 <7,7,7,7>, LHS - 1638471298U, // <7,7,u,1>: Cost 2 vext3 RHS, <7,u,1,2> - 2712213132U, // <7,7,u,2>: Cost 3 vext3 RHS, <7,u,2,3> - 2712213138U, // <7,7,u,3>: Cost 3 vext3 RHS, <7,u,3,0> - 1523420470U, // <7,7,u,4>: Cost 2 vext1 <7,7,7,7>, RHS - 1638471338U, // <7,7,u,5>: Cost 2 vext3 RHS, <7,u,5,6> - 1595840756U, // <7,7,u,6>: Cost 2 vext2 , - 363253046U, // <7,7,u,7>: Cost 1 vdup3 RHS - 363253046U, // <7,7,u,u>: Cost 1 vdup3 RHS - 1638318080U, // <7,u,0,0>: Cost 2 vext3 RHS, <0,0,0,0> - 1638323923U, // <7,u,0,1>: Cost 2 vext3 RHS, - 1662211804U, // <7,u,0,2>: Cost 2 vext3 RHS, - 1638323941U, // <7,u,0,3>: Cost 2 vext3 RHS, - 2712065773U, // <7,u,0,4>: Cost 3 vext3 RHS, - 1662359286U, // <7,u,0,5>: Cost 2 vext3 RHS, - 1662359296U, // <7,u,0,6>: Cost 2 vext3 RHS, - 2987150664U, // <7,u,0,7>: Cost 3 vzipr <5,6,7,0>, RHS - 1638323986U, // <7,u,0,u>: Cost 2 vext3 RHS, - 1517469798U, // <7,u,1,0>: Cost 2 vext1 <6,7,u,1>, LHS - 1638318900U, // <7,u,1,1>: Cost 2 vext3 RHS, <1,1,1,1> - 564582190U, // <7,u,1,2>: Cost 1 vext3 RHS, LHS - 1638324023U, // <7,u,1,3>: Cost 2 vext3 RHS, - 1517473078U, // <7,u,1,4>: Cost 2 vext1 <6,7,u,1>, RHS - 2693928777U, // <7,u,1,5>: Cost 3 vext3 <1,5,3,7>, - 1517474710U, // <7,u,1,6>: Cost 2 vext1 <6,7,u,1>, <6,7,u,1> - 1640462171U, // <7,u,1,7>: Cost 2 vext3 RHS, - 564582244U, // <7,u,1,u>: Cost 1 vext3 RHS, LHS - 1638318244U, // <7,u,2,0>: Cost 2 vext3 RHS, <0,2,0,2> - 2712065907U, // <7,u,2,1>: Cost 3 vext3 RHS, - 1638319720U, // <7,u,2,2>: Cost 2 vext3 RHS, <2,2,2,2> - 1638324101U, // <7,u,2,3>: Cost 2 vext3 RHS, - 1638318284U, // <7,u,2,4>: Cost 2 vext3 RHS, <0,2,4,6> - 2712065947U, // <7,u,2,5>: Cost 3 vext3 RHS, - 2700564387U, // <7,u,2,6>: Cost 3 vext3 <2,6,3,7>, - 1640314796U, // <7,u,2,7>: Cost 2 vext3 RHS, - 1638324146U, // <7,u,2,u>: Cost 2 vext3 RHS, - 1638324156U, // <7,u,3,0>: Cost 2 vext3 RHS, - 1638319064U, // <7,u,3,1>: Cost 2 vext3 RHS, <1,3,1,3> - 2700564435U, // <7,u,3,2>: Cost 3 vext3 <2,6,3,7>, - 1638320540U, // <7,u,3,3>: Cost 2 vext3 RHS, <3,3,3,3> - 1638324196U, // <7,u,3,4>: Cost 2 vext3 RHS, - 1638324207U, // <7,u,3,5>: Cost 2 vext3 RHS, - 2700564472U, // <7,u,3,6>: Cost 3 vext3 <2,6,3,7>, - 2695919610U, // <7,u,3,7>: Cost 3 vext3 <1,u,3,7>, - 1638324228U, // <7,u,3,u>: Cost 2 vext3 RHS, - 2712066061U, // <7,u,4,0>: Cost 3 vext3 RHS, - 1662212122U, // <7,u,4,1>: Cost 2 vext3 RHS, - 1662212132U, // <7,u,4,2>: Cost 2 vext3 RHS, - 2712066092U, // <7,u,4,3>: Cost 3 vext3 RHS, - 1638321360U, // <7,u,4,4>: Cost 2 vext3 RHS, <4,4,4,4> - 1638324287U, // <7,u,4,5>: Cost 2 vext3 RHS, - 1662359624U, // <7,u,4,6>: Cost 2 vext3 RHS, - 1640314961U, // <7,u,4,7>: Cost 2 vext3 RHS, - 1638324314U, // <7,u,4,u>: Cost 2 vext3 RHS, - 1517502566U, // <7,u,5,0>: Cost 2 vext1 <6,7,u,5>, LHS - 1574612693U, // <7,u,5,1>: Cost 2 vext2 <5,1,7,u>, <5,1,7,u> - 2712066162U, // <7,u,5,2>: Cost 3 vext3 RHS, - 1638324351U, // <7,u,5,3>: Cost 2 vext3 RHS, - 1576603592U, // <7,u,5,4>: Cost 2 vext2 <5,4,7,u>, <5,4,7,u> - 1577267225U, // <7,u,5,5>: Cost 2 vext2 <5,5,7,u>, <5,5,7,u> - 564582554U, // <7,u,5,6>: Cost 1 vext3 RHS, RHS - 1640462499U, // <7,u,5,7>: Cost 2 vext3 RHS, - 564582572U, // <7,u,5,u>: Cost 1 vext3 RHS, RHS - 2712066223U, // <7,u,6,0>: Cost 3 vext3 RHS, - 2712066238U, // <7,u,6,1>: Cost 3 vext3 RHS, - 1581249023U, // <7,u,6,2>: Cost 2 vext2 <6,2,7,u>, <6,2,7,u> - 1638324432U, // <7,u,6,3>: Cost 2 vext3 RHS, - 1638468980U, // <7,u,6,4>: Cost 2 vext3 RHS, <4,6,4,6> - 2712066274U, // <7,u,6,5>: Cost 3 vext3 RHS, - 1583903555U, // <7,u,6,6>: Cost 2 vext2 <6,6,7,u>, <6,6,7,u> - 1640315117U, // <7,u,6,7>: Cost 2 vext3 RHS, - 1638324477U, // <7,u,6,u>: Cost 2 vext3 RHS, - 1638471936U, // <7,u,7,0>: Cost 2 vext3 RHS, - 2692970763U, // <7,u,7,1>: Cost 3 vext3 <1,3,u,7>, - 2700933399U, // <7,u,7,2>: Cost 3 vext3 <2,6,u,7>, - 2573347601U, // <7,u,7,3>: Cost 3 vext1 <3,7,u,7>, <3,7,u,7> - 1638471976U, // <7,u,7,4>: Cost 2 vext3 RHS, - 1511551171U, // <7,u,7,5>: Cost 2 vext1 <5,7,u,7>, <5,7,u,7> - 2712213815U, // <7,u,7,6>: Cost 3 vext3 RHS, - 363253046U, // <7,u,7,7>: Cost 1 vdup3 RHS - 363253046U, // <7,u,7,u>: Cost 1 vdup3 RHS - 1638324561U, // <7,u,u,0>: Cost 2 vext3 RHS, - 1638324571U, // <7,u,u,1>: Cost 2 vext3 RHS, - 564582757U, // <7,u,u,2>: Cost 1 vext3 RHS, LHS - 1638324587U, // <7,u,u,3>: Cost 2 vext3 RHS, - 1638324601U, // <7,u,u,4>: Cost 2 vext3 RHS, - 1638324611U, // <7,u,u,5>: Cost 2 vext3 RHS, - 564582797U, // <7,u,u,6>: Cost 1 vext3 RHS, RHS - 363253046U, // <7,u,u,7>: Cost 1 vdup3 RHS - 564582811U, // <7,u,u,u>: Cost 1 vext3 RHS, LHS - 135053414U, // : Cost 1 vdup0 LHS - 1611489290U, // : Cost 2 vext3 LHS, <0,0,1,1> - 1611489300U, // : Cost 2 vext3 LHS, <0,0,2,2> - 2568054923U, // : Cost 3 vext1 <3,0,0,0>, <3,0,0,0> - 1481706806U, // : Cost 2 vext1 <0,u,0,0>, RHS - 2555449040U, // : Cost 3 vext1 <0,u,0,0>, <5,1,7,3> - 2591282078U, // : Cost 3 vext1 <6,u,0,0>, <6,u,0,0> - 2591945711U, // : Cost 3 vext1 <7,0,0,0>, <7,0,0,0> - 135053414U, // : Cost 1 vdup0 LHS - 1493655654U, // : Cost 2 vext1 <2,u,0,1>, LHS - 1860550758U, // : Cost 2 vzipl LHS, LHS - 537747563U, // : Cost 1 vext3 LHS, LHS - 2625135576U, // : Cost 3 vext2 <1,2,u,0>, <1,3,1,3> - 1493658934U, // : Cost 2 vext1 <2,u,0,1>, RHS - 2625135760U, // : Cost 3 vext2 <1,2,u,0>, <1,5,3,7> - 1517548447U, // : Cost 2 vext1 <6,u,0,1>, <6,u,0,1> - 2591290362U, // : Cost 3 vext1 <6,u,0,1>, <7,0,1,2> - 537747612U, // : Cost 1 vext3 LHS, LHS - 1611489444U, // : Cost 2 vext3 LHS, <0,2,0,2> - 2685231276U, // : Cost 3 vext3 LHS, <0,2,1,1> - 1994768486U, // : Cost 2 vtrnl LHS, LHS - 2685231294U, // : Cost 3 vext3 LHS, <0,2,3,1> - 1611489484U, // : Cost 2 vext3 LHS, <0,2,4,6> - 2712068310U, // : Cost 3 vext3 RHS, <0,2,5,7> - 2625136570U, // : Cost 3 vext2 <1,2,u,0>, <2,6,3,7> - 2591962097U, // : Cost 3 vext1 <7,0,0,2>, <7,0,0,2> - 1611489516U, // : Cost 2 vext3 LHS, <0,2,u,2> - 2954067968U, // : Cost 3 vzipr LHS, <0,0,0,0> - 2685231356U, // : Cost 3 vext3 LHS, <0,3,1,0> - 72589981U, // : Cost 1 vrev LHS - 2625137052U, // : Cost 3 vext2 <1,2,u,0>, <3,3,3,3> - 2625137154U, // : Cost 3 vext2 <1,2,u,0>, <3,4,5,6> - 2639071848U, // : Cost 3 vext2 <3,5,u,0>, <3,5,u,0> - 2639735481U, // : Cost 3 vext2 <3,6,u,0>, <3,6,u,0> - 2597279354U, // : Cost 3 vext1 <7,u,0,3>, <7,u,0,3> - 73032403U, // : Cost 1 vrev LHS - 2687074636U, // : Cost 3 vext3 <0,4,0,u>, <0,4,0,u> - 1611489618U, // : Cost 2 vext3 LHS, <0,4,1,5> - 1611489628U, // : Cost 2 vext3 LHS, <0,4,2,6> - 3629222038U, // : Cost 4 vext1 <0,u,0,4>, <3,0,1,2> - 2555481398U, // : Cost 3 vext1 <0,u,0,4>, RHS - 1551396150U, // : Cost 2 vext2 <1,2,u,0>, RHS - 2651680116U, // : Cost 3 vext2 <5,6,u,0>, <4,6,4,6> - 2646150600U, // : Cost 3 vext2 <4,7,5,0>, <4,7,5,0> - 1611932050U, // : Cost 2 vext3 LHS, <0,4,u,6> - 2561458278U, // : Cost 3 vext1 <1,u,0,5>, LHS - 1863532646U, // : Cost 2 vzipl RHS, LHS - 2712068526U, // : Cost 3 vext3 RHS, <0,5,2,7> - 2649689976U, // : Cost 3 vext2 <5,3,u,0>, <5,3,u,0> - 2220237489U, // : Cost 3 vrev <0,u,4,5> - 2651680772U, // : Cost 3 vext2 <5,6,u,0>, <5,5,5,5> - 1577939051U, // : Cost 2 vext2 <5,6,u,0>, <5,6,u,0> - 2830077238U, // : Cost 3 vuzpr <1,u,3,0>, RHS - 1579266317U, // : Cost 2 vext2 <5,u,u,0>, <5,u,u,0> - 2555494502U, // : Cost 3 vext1 <0,u,0,6>, LHS - 2712068598U, // : Cost 3 vext3 RHS, <0,6,1,7> - 1997750374U, // : Cost 2 vtrnl RHS, LHS - 2655662673U, // : Cost 3 vext2 <6,3,u,0>, <6,3,u,0> - 2555497782U, // : Cost 3 vext1 <0,u,0,6>, RHS - 2651681459U, // : Cost 3 vext2 <5,6,u,0>, <6,5,0,u> - 2651681592U, // : Cost 3 vext2 <5,6,u,0>, <6,6,6,6> - 2651681614U, // : Cost 3 vext2 <5,6,u,0>, <6,7,0,1> - 1997750428U, // : Cost 2 vtrnl RHS, LHS - 2567446630U, // : Cost 3 vext1 <2,u,0,7>, LHS - 2567447446U, // : Cost 3 vext1 <2,u,0,7>, <1,2,3,0> - 2567448641U, // : Cost 3 vext1 <2,u,0,7>, <2,u,0,7> - 2573421338U, // : Cost 3 vext1 <3,u,0,7>, <3,u,0,7> - 2567449910U, // : Cost 3 vext1 <2,u,0,7>, RHS - 2651682242U, // : Cost 3 vext2 <5,6,u,0>, <7,5,6,u> - 2591339429U, // : Cost 3 vext1 <6,u,0,7>, <6,u,0,7> - 2651682412U, // : Cost 3 vext2 <5,6,u,0>, <7,7,7,7> - 2567452462U, // : Cost 3 vext1 <2,u,0,7>, LHS - 135053414U, // : Cost 1 vdup0 LHS - 1611489938U, // : Cost 2 vext3 LHS, <0,u,1,1> - 537748125U, // : Cost 1 vext3 LHS, LHS - 2685674148U, // : Cost 3 vext3 LHS, <0,u,3,1> - 1611932338U, // : Cost 2 vext3 LHS, <0,u,4,6> - 1551399066U, // : Cost 2 vext2 <1,2,u,0>, RHS - 1517605798U, // : Cost 2 vext1 <6,u,0,u>, <6,u,0,u> - 2830077481U, // : Cost 3 vuzpr <1,u,3,0>, RHS - 537748179U, // : Cost 1 vext3 LHS, LHS - 1544101961U, // : Cost 2 vext2 <0,0,u,1>, <0,0,u,1> - 1558036582U, // : Cost 2 vext2 <2,3,u,1>, LHS - 2619171051U, // : Cost 3 vext2 <0,2,u,1>, <0,2,u,1> - 1611490038U, // : Cost 2 vext3 LHS, <1,0,3,2> - 2555522358U, // : Cost 3 vext1 <0,u,1,0>, RHS - 2712068871U, // : Cost 3 vext3 RHS, <1,0,5,1> - 2591355815U, // : Cost 3 vext1 <6,u,1,0>, <6,u,1,0> - 2597328512U, // : Cost 3 vext1 <7,u,1,0>, <7,u,1,0> - 1611490083U, // : Cost 2 vext3 LHS, <1,0,u,2> - 1481785446U, // : Cost 2 vext1 <0,u,1,1>, LHS - 202162278U, // : Cost 1 vdup1 LHS - 2555528808U, // : Cost 3 vext1 <0,u,1,1>, <2,2,2,2> - 1611490120U, // : Cost 2 vext3 LHS, <1,1,3,3> - 1481788726U, // : Cost 2 vext1 <0,u,1,1>, RHS - 2689876828U, // : Cost 3 vext3 LHS, <1,1,5,5> - 2591364008U, // : Cost 3 vext1 <6,u,1,1>, <6,u,1,1> - 2592691274U, // : Cost 3 vext1 <7,1,1,1>, <7,1,1,1> - 202162278U, // : Cost 1 vdup1 LHS - 1499709542U, // : Cost 2 vext1 <3,u,1,2>, LHS - 2689876871U, // : Cost 3 vext3 LHS, <1,2,1,3> - 2631116445U, // : Cost 3 vext2 <2,2,u,1>, <2,2,u,1> - 835584U, // : Cost 0 copy LHS - 1499712822U, // : Cost 2 vext1 <3,u,1,2>, RHS - 2689876907U, // : Cost 3 vext3 LHS, <1,2,5,3> - 2631780282U, // : Cost 3 vext2 <2,3,u,1>, <2,6,3,7> - 1523603074U, // : Cost 2 vext1 <7,u,1,2>, <7,u,1,2> - 835584U, // : Cost 0 copy LHS - 1487773798U, // : Cost 2 vext1 <1,u,1,3>, LHS - 1611490264U, // : Cost 2 vext3 LHS, <1,3,1,3> - 2685232094U, // : Cost 3 vext3 LHS, <1,3,2,0> - 2018746470U, // : Cost 2 vtrnr LHS, LHS - 1487777078U, // : Cost 2 vext1 <1,u,1,3>, RHS - 1611490304U, // : Cost 2 vext3 LHS, <1,3,5,7> - 2685674505U, // : Cost 3 vext3 LHS, <1,3,6,7> - 2640407307U, // : Cost 3 vext2 <3,7,u,1>, <3,7,u,1> - 1611490327U, // : Cost 2 vext3 LHS, <1,3,u,3> - 1567992749U, // : Cost 2 vext2 <4,0,u,1>, <4,0,u,1> - 2693121070U, // : Cost 3 vext3 <1,4,1,u>, <1,4,1,u> - 2693194807U, // : Cost 3 vext3 <1,4,2,u>, <1,4,2,u> - 1152386432U, // : Cost 2 vrev <1,u,3,4> - 2555555126U, // : Cost 3 vext1 <0,u,1,4>, RHS - 1558039862U, // : Cost 2 vext2 <2,3,u,1>, RHS - 2645716371U, // : Cost 3 vext2 <4,6,u,1>, <4,6,u,1> - 2597361284U, // : Cost 3 vext1 <7,u,1,4>, <7,u,1,4> - 1152755117U, // : Cost 2 vrev <1,u,u,4> - 1481818214U, // : Cost 2 vext1 <0,u,1,5>, LHS - 2555560694U, // : Cost 3 vext1 <0,u,1,5>, <1,0,3,2> - 2555561576U, // : Cost 3 vext1 <0,u,1,5>, <2,2,2,2> - 1611490448U, // : Cost 2 vext3 LHS, <1,5,3,7> - 1481821494U, // : Cost 2 vext1 <0,u,1,5>, RHS - 2651025435U, // : Cost 3 vext2 <5,5,u,1>, <5,5,u,1> - 2651689068U, // : Cost 3 vext2 <5,6,u,1>, <5,6,u,1> - 2823966006U, // : Cost 3 vuzpr <0,u,1,1>, RHS - 1611932861U, // : Cost 2 vext3 LHS, <1,5,u,7> - 2555568230U, // : Cost 3 vext1 <0,u,1,6>, LHS - 2689877199U, // : Cost 3 vext3 LHS, <1,6,1,7> - 2712069336U, // : Cost 3 vext3 RHS, <1,6,2,7> - 2685232353U, // : Cost 3 vext3 LHS, <1,6,3,7> - 2555571510U, // : Cost 3 vext1 <0,u,1,6>, RHS - 2689877235U, // : Cost 3 vext3 LHS, <1,6,5,7> - 2657661765U, // : Cost 3 vext2 <6,6,u,1>, <6,6,u,1> - 1584583574U, // : Cost 2 vext2 <6,7,u,1>, <6,7,u,1> - 1585247207U, // : Cost 2 vext2 <6,u,u,1>, <6,u,u,1> - 2561548390U, // : Cost 3 vext1 <1,u,1,7>, LHS - 2561549681U, // : Cost 3 vext1 <1,u,1,7>, <1,u,1,7> - 2573493926U, // : Cost 3 vext1 <3,u,1,7>, <2,3,0,1> - 2042962022U, // : Cost 2 vtrnr RHS, LHS - 2561551670U, // : Cost 3 vext1 <1,u,1,7>, RHS - 2226300309U, // : Cost 3 vrev <1,u,5,7> - 2658325990U, // : Cost 3 vext2 <6,7,u,1>, <7,6,1,u> - 2658326124U, // : Cost 3 vext2 <6,7,u,1>, <7,7,7,7> - 2042962027U, // : Cost 2 vtrnr RHS, LHS - 1481842790U, // : Cost 2 vext1 <0,u,1,u>, LHS - 202162278U, // : Cost 1 vdup1 LHS - 2685674867U, // : Cost 3 vext3 LHS, <1,u,2,0> - 835584U, // : Cost 0 copy LHS - 1481846070U, // : Cost 2 vext1 <0,u,1,u>, RHS - 1611933077U, // : Cost 2 vext3 LHS, <1,u,5,7> - 2685674910U, // : Cost 3 vext3 LHS, <1,u,6,7> - 1523652232U, // : Cost 2 vext1 <7,u,1,u>, <7,u,1,u> - 835584U, // : Cost 0 copy LHS - 1544110154U, // : Cost 2 vext2 <0,0,u,2>, <0,0,u,2> - 1545437286U, // : Cost 2 vext2 <0,2,u,2>, LHS - 1545437420U, // : Cost 2 vext2 <0,2,u,2>, <0,2,u,2> - 2685232589U, // : Cost 3 vext3 LHS, <2,0,3,0> - 2619179346U, // : Cost 3 vext2 <0,2,u,2>, <0,4,1,5> - 2712069606U, // : Cost 3 vext3 RHS, <2,0,5,7> - 2689877484U, // : Cost 3 vext3 LHS, <2,0,6,4> - 2659656273U, // : Cost 3 vext2 <7,0,u,2>, <0,7,2,u> - 1545437853U, // : Cost 2 vext2 <0,2,u,2>, LHS - 1550082851U, // : Cost 2 vext2 <1,0,u,2>, <1,0,u,2> - 2619179828U, // : Cost 3 vext2 <0,2,u,2>, <1,1,1,1> - 2619179926U, // : Cost 3 vext2 <0,2,u,2>, <1,2,3,0> - 2685232671U, // : Cost 3 vext3 LHS, <2,1,3,1> - 2555604278U, // : Cost 3 vext1 <0,u,2,1>, RHS - 2619180176U, // : Cost 3 vext2 <0,2,u,2>, <1,5,3,7> - 2689877564U, // : Cost 3 vext3 LHS, <2,1,6,3> - 2602718850U, // : Cost 3 vext1 , <7,u,1,2> - 1158703235U, // : Cost 2 vrev <2,u,u,1> - 1481867366U, // : Cost 2 vext1 <0,u,2,2>, LHS - 2555609846U, // : Cost 3 vext1 <0,u,2,2>, <1,0,3,2> - 269271142U, // : Cost 1 vdup2 LHS - 1611490930U, // : Cost 2 vext3 LHS, <2,2,3,3> - 1481870646U, // : Cost 2 vext1 <0,u,2,2>, RHS - 2689877640U, // : Cost 3 vext3 LHS, <2,2,5,7> - 2619180986U, // : Cost 3 vext2 <0,2,u,2>, <2,6,3,7> - 2593436837U, // : Cost 3 vext1 <7,2,2,2>, <7,2,2,2> - 269271142U, // : Cost 1 vdup2 LHS - 408134301U, // : Cost 1 vext1 LHS, LHS - 1481876214U, // : Cost 2 vext1 LHS, <1,0,3,2> - 1481877096U, // : Cost 2 vext1 LHS, <2,2,2,2> - 1880326246U, // : Cost 2 vzipr LHS, LHS - 408137014U, // : Cost 1 vext1 LHS, RHS - 1529654992U, // : Cost 2 vext1 LHS, <5,1,7,3> - 1529655802U, // : Cost 2 vext1 LHS, <6,2,7,3> - 1529656314U, // : Cost 2 vext1 LHS, <7,0,1,2> - 408139566U, // : Cost 1 vext1 LHS, LHS - 1567853468U, // : Cost 2 vext2 <4,0,6,2>, <4,0,6,2> - 2561598362U, // : Cost 3 vext1 <1,u,2,4>, <1,2,3,4> - 2555627214U, // : Cost 3 vext1 <0,u,2,4>, <2,3,4,5> - 2685232918U, // : Cost 3 vext3 LHS, <2,4,3,5> - 2555628854U, // : Cost 3 vext1 <0,u,2,4>, RHS - 1545440566U, // : Cost 2 vext2 <0,2,u,2>, RHS - 1571982740U, // : Cost 2 vext2 <4,6,u,2>, <4,6,u,2> - 2592125957U, // : Cost 3 vext1 <7,0,2,4>, <7,0,2,4> - 1545440809U, // : Cost 2 vext2 <0,2,u,2>, RHS - 2555633766U, // : Cost 3 vext1 <0,u,2,5>, LHS - 2561606550U, // : Cost 3 vext1 <1,u,2,5>, <1,2,3,0> - 2689877856U, // : Cost 3 vext3 LHS, <2,5,2,7> - 2685233000U, // : Cost 3 vext3 LHS, <2,5,3,6> - 1158441059U, // : Cost 2 vrev <2,u,4,5> - 2645725188U, // : Cost 3 vext2 <4,6,u,2>, <5,5,5,5> - 2689877892U, // : Cost 3 vext3 LHS, <2,5,6,7> - 2823900470U, // : Cost 3 vuzpr <0,u,0,2>, RHS - 1158736007U, // : Cost 2 vrev <2,u,u,5> - 1481900134U, // : Cost 2 vext1 <0,u,2,6>, LHS - 2555642614U, // : Cost 3 vext1 <0,u,2,6>, <1,0,3,2> - 2555643496U, // : Cost 3 vext1 <0,u,2,6>, <2,2,2,2> - 1611491258U, // : Cost 2 vext3 LHS, <2,6,3,7> - 1481903414U, // : Cost 2 vext1 <0,u,2,6>, RHS - 2689877964U, // : Cost 3 vext3 LHS, <2,6,5,7> - 2689877973U, // : Cost 3 vext3 LHS, <2,6,6,7> - 2645726030U, // : Cost 3 vext2 <4,6,u,2>, <6,7,0,1> - 1611933671U, // : Cost 2 vext3 LHS, <2,6,u,7> - 1585919033U, // : Cost 2 vext2 <7,0,u,2>, <7,0,u,2> - 2573566710U, // : Cost 3 vext1 <3,u,2,7>, <1,0,3,2> - 2567596115U, // : Cost 3 vext1 <2,u,2,7>, <2,u,2,7> - 1906901094U, // : Cost 2 vzipr RHS, LHS - 2555653430U, // : Cost 3 vext1 <0,u,2,7>, RHS - 2800080230U, // : Cost 3 vuzpl LHS, <7,4,5,6> - 2980643164U, // : Cost 3 vzipr RHS, <0,4,2,6> - 2645726828U, // : Cost 3 vext2 <4,6,u,2>, <7,7,7,7> - 1906901099U, // : Cost 2 vzipr RHS, LHS - 408175266U, // : Cost 1 vext1 LHS, LHS - 1545443118U, // : Cost 2 vext2 <0,2,u,2>, LHS - 269271142U, // : Cost 1 vdup2 LHS - 1611491416U, // : Cost 2 vext3 LHS, <2,u,3,3> - 408177974U, // : Cost 1 vext1 LHS, RHS - 1545443482U, // : Cost 2 vext2 <0,2,u,2>, RHS - 1726339226U, // : Cost 2 vuzpl LHS, RHS - 1529697274U, // : Cost 2 vext1 LHS, <7,0,1,2> - 408180526U, // : Cost 1 vext1 LHS, LHS - 1544781824U, // : Cost 2 vext2 LHS, <0,0,0,0> - 471040156U, // : Cost 1 vext2 LHS, LHS - 1544781988U, // : Cost 2 vext2 LHS, <0,2,0,2> - 2618523900U, // : Cost 3 vext2 LHS, <0,3,1,0> - 1544782162U, // : Cost 2 vext2 LHS, <0,4,1,5> - 2238188352U, // : Cost 3 vrev <3,u,5,0> - 2623169023U, // : Cost 3 vext2 LHS, <0,6,2,7> - 2238335826U, // : Cost 3 vrev <3,u,7,0> - 471040669U, // : Cost 1 vext2 LHS, LHS - 1544782582U, // : Cost 2 vext2 LHS, <1,0,3,2> - 1544782644U, // : Cost 2 vext2 LHS, <1,1,1,1> - 1544782742U, // : Cost 2 vext2 LHS, <1,2,3,0> - 1544782808U, // : Cost 2 vext2 LHS, <1,3,1,3> - 2618524733U, // : Cost 3 vext2 LHS, <1,4,3,5> - 1544782992U, // : Cost 2 vext2 LHS, <1,5,3,7> - 2618524897U, // : Cost 3 vext2 LHS, <1,6,3,7> - 2703517987U, // : Cost 3 vext3 <3,1,7,u>, <3,1,7,u> - 1544783213U, // : Cost 2 vext2 LHS, <1,u,1,3> - 1529716838U, // : Cost 2 vext1 , LHS - 1164167966U, // : Cost 2 vrev <3,u,1,2> - 1544783464U, // : Cost 2 vext2 LHS, <2,2,2,2> - 1544783526U, // : Cost 2 vext2 LHS, <2,3,0,1> - 1529720118U, // : Cost 2 vext1 , RHS - 2618525544U, // : Cost 3 vext2 LHS, <2,5,3,6> - 1544783802U, // : Cost 2 vext2 LHS, <2,6,3,7> - 2704181620U, // : Cost 3 vext3 <3,2,7,u>, <3,2,7,u> - 1544783931U, // : Cost 2 vext2 LHS, <2,u,0,1> - 1544784022U, // : Cost 2 vext2 LHS, <3,0,1,2> - 1487922559U, // : Cost 2 vext1 <1,u,3,3>, <1,u,3,3> - 1493895256U, // : Cost 2 vext1 <2,u,3,3>, <2,u,3,3> - 336380006U, // : Cost 1 vdup3 LHS - 1544784386U, // : Cost 2 vext2 LHS, <3,4,5,6> - 2824054478U, // : Cost 3 vuzpr LHS, <2,3,4,5> - 2238286668U, // : Cost 3 vrev <3,u,6,3> - 2954069136U, // : Cost 3 vzipr LHS, <1,5,3,7> - 336380006U, // : Cost 1 vdup3 LHS - 1487929446U, // : Cost 2 vext1 <1,u,3,4>, LHS - 1487930752U, // : Cost 2 vext1 <1,u,3,4>, <1,u,3,4> - 2623171644U, // : Cost 3 vext2 LHS, <4,2,6,0> - 2561673366U, // : Cost 3 vext1 <1,u,3,4>, <3,0,1,2> - 1487932726U, // : Cost 2 vext1 <1,u,3,4>, RHS - 471043382U, // : Cost 1 vext2 LHS, RHS - 1592561012U, // : Cost 2 vext2 LHS, <4,6,4,6> - 2238368598U, // : Cost 3 vrev <3,u,7,4> - 471043625U, // : Cost 1 vext2 LHS, RHS - 2555707494U, // : Cost 3 vext1 <0,u,3,5>, LHS - 1574645465U, // : Cost 2 vext2 <5,1,u,3>, <5,1,u,3> - 2567653106U, // : Cost 3 vext1 <2,u,3,5>, <2,3,u,5> - 2555709954U, // : Cost 3 vext1 <0,u,3,5>, <3,4,5,6> - 1592561606U, // : Cost 2 vext2 LHS, <5,4,7,6> - 1592561668U, // : Cost 2 vext2 LHS, <5,5,5,5> - 1592561762U, // : Cost 2 vext2 LHS, <5,6,7,0> - 1750314294U, // : Cost 2 vuzpr LHS, RHS - 1750314295U, // : Cost 2 vuzpr LHS, RHS - 2623172897U, // : Cost 3 vext2 LHS, <6,0,1,2> - 2561688962U, // : Cost 3 vext1 <1,u,3,6>, <1,u,3,6> - 1581281795U, // : Cost 2 vext2 <6,2,u,3>, <6,2,u,3> - 2706541204U, // : Cost 3 vext3 <3,6,3,u>, <3,6,3,u> - 2623173261U, // : Cost 3 vext2 LHS, <6,4,5,6> - 1164495686U, // : Cost 2 vrev <3,u,5,6> - 1592562488U, // : Cost 2 vext2 LHS, <6,6,6,6> - 1592562510U, // : Cost 2 vext2 LHS, <6,7,0,1> - 1164716897U, // : Cost 2 vrev <3,u,u,6> - 1487954022U, // : Cost 2 vext1 <1,u,3,7>, LHS - 1487955331U, // : Cost 2 vext1 <1,u,3,7>, <1,u,3,7> - 1493928028U, // : Cost 2 vext1 <2,u,3,7>, <2,u,3,7> - 2561697942U, // : Cost 3 vext1 <1,u,3,7>, <3,0,1,2> - 1487957302U, // : Cost 2 vext1 <1,u,3,7>, RHS - 2707352311U, // : Cost 3 vext3 <3,7,5,u>, <3,7,5,u> - 2655024623U, // : Cost 3 vext2 <6,2,u,3>, <7,6,2,u> - 1592563308U, // : Cost 2 vext2 LHS, <7,7,7,7> - 1487959854U, // : Cost 2 vext1 <1,u,3,7>, LHS - 1544787667U, // : Cost 2 vext2 LHS, - 471045934U, // : Cost 1 vext2 LHS, LHS - 1549432709U, // : Cost 2 vext2 LHS, - 336380006U, // : Cost 1 vdup3 LHS - 1544788031U, // : Cost 2 vext2 LHS, - 471046298U, // : Cost 1 vext2 LHS, RHS - 1549433040U, // : Cost 2 vext2 LHS, - 1750314537U, // : Cost 2 vuzpr LHS, RHS - 471046501U, // : Cost 1 vext2 LHS, LHS - 2625167360U, // : Cost 3 vext2 <1,2,u,4>, <0,0,0,0> - 1551425638U, // : Cost 2 vext2 <1,2,u,4>, LHS - 2619195630U, // : Cost 3 vext2 <0,2,u,4>, <0,2,u,4> - 2619343104U, // : Cost 3 vext2 <0,3,1,4>, <0,3,1,4> - 2625167698U, // : Cost 3 vext2 <1,2,u,4>, <0,4,1,5> - 1638329234U, // : Cost 2 vext3 RHS, <4,0,5,1> - 1638329244U, // : Cost 2 vext3 RHS, <4,0,6,2> - 3787803556U, // : Cost 4 vext3 RHS, <4,0,7,1> - 1551426205U, // : Cost 2 vext2 <1,2,u,4>, LHS - 2555748454U, // : Cost 3 vext1 <0,u,4,1>, LHS - 2625168180U, // : Cost 3 vext2 <1,2,u,4>, <1,1,1,1> - 1551426503U, // : Cost 2 vext2 <1,2,u,4>, <1,2,u,4> - 2625168344U, // : Cost 3 vext2 <1,2,u,4>, <1,3,1,3> - 2555751734U, // : Cost 3 vext1 <0,u,4,1>, RHS - 1860554038U, // : Cost 2 vzipl LHS, RHS - 2689879022U, // : Cost 3 vext3 LHS, <4,1,6,3> - 2592248852U, // : Cost 3 vext1 <7,0,4,1>, <7,0,4,1> - 1555408301U, // : Cost 2 vext2 <1,u,u,4>, <1,u,u,4> - 2555756646U, // : Cost 3 vext1 <0,u,4,2>, LHS - 2625168943U, // : Cost 3 vext2 <1,2,u,4>, <2,1,4,u> - 2625169000U, // : Cost 3 vext2 <1,2,u,4>, <2,2,2,2> - 2619197134U, // : Cost 3 vext2 <0,2,u,4>, <2,3,4,5> - 2555759926U, // : Cost 3 vext1 <0,u,4,2>, RHS - 2712071222U, // : Cost 3 vext3 RHS, <4,2,5,3> - 1994771766U, // : Cost 2 vtrnl LHS, RHS - 2592257045U, // : Cost 3 vext1 <7,0,4,2>, <7,0,4,2> - 1994771784U, // : Cost 2 vtrnl LHS, RHS - 2625169558U, // : Cost 3 vext2 <1,2,u,4>, <3,0,1,2> - 2567709594U, // : Cost 3 vext1 <2,u,4,3>, <1,2,3,4> - 2567710817U, // : Cost 3 vext1 <2,u,4,3>, <2,u,4,3> - 2625169820U, // : Cost 3 vext2 <1,2,u,4>, <3,3,3,3> - 2625169922U, // : Cost 3 vext2 <1,2,u,4>, <3,4,5,6> - 2954069710U, // : Cost 3 vzipr LHS, <2,3,4,5> - 2954068172U, // : Cost 3 vzipr LHS, <0,2,4,6> - 3903849472U, // : Cost 4 vuzpr <1,u,3,4>, <1,3,5,7> - 2954068174U, // : Cost 3 vzipr LHS, <0,2,4,u> - 1505919078U, // : Cost 2 vext1 <4,u,4,4>, LHS - 2567717831U, // : Cost 3 vext1 <2,u,4,4>, <1,2,u,4> - 2567719010U, // : Cost 3 vext1 <2,u,4,4>, <2,u,4,4> - 2570373542U, // : Cost 3 vext1 <3,3,4,4>, <3,3,4,4> - 161926454U, // : Cost 1 vdup0 RHS - 1551428918U, // : Cost 2 vext2 <1,2,u,4>, RHS - 1638329572U, // : Cost 2 vext3 RHS, <4,4,6,6> - 2594927963U, // : Cost 3 vext1 <7,4,4,4>, <7,4,4,4> - 161926454U, // : Cost 1 vdup0 RHS - 1493983334U, // : Cost 2 vext1 <2,u,4,5>, LHS - 2689879301U, // : Cost 3 vext3 LHS, <4,5,1,3> - 1493985379U, // : Cost 2 vext1 <2,u,4,5>, <2,u,4,5> - 2567727254U, // : Cost 3 vext1 <2,u,4,5>, <3,0,1,2> - 1493986614U, // : Cost 2 vext1 <2,u,4,5>, RHS - 1863535926U, // : Cost 2 vzipl RHS, RHS - 537750838U, // : Cost 1 vext3 LHS, RHS - 2830110006U, // : Cost 3 vuzpr <1,u,3,4>, RHS - 537750856U, // : Cost 1 vext3 LHS, RHS - 1482047590U, // : Cost 2 vext1 <0,u,4,6>, LHS - 2555790070U, // : Cost 3 vext1 <0,u,4,6>, <1,0,3,2> - 2555790952U, // : Cost 3 vext1 <0,u,4,6>, <2,2,2,2> - 2555791510U, // : Cost 3 vext1 <0,u,4,6>, <3,0,1,2> - 1482050870U, // : Cost 2 vext1 <0,u,4,6>, RHS - 2689879422U, // : Cost 3 vext3 LHS, <4,6,5,7> - 1997753654U, // : Cost 2 vtrnl RHS, RHS - 2712071562U, // : Cost 3 vext3 RHS, <4,6,7,1> - 1482053422U, // : Cost 2 vext1 <0,u,4,6>, LHS - 2567741542U, // : Cost 3 vext1 <2,u,4,7>, LHS - 2567742362U, // : Cost 3 vext1 <2,u,4,7>, <1,2,3,4> - 2567743589U, // : Cost 3 vext1 <2,u,4,7>, <2,u,4,7> - 2573716286U, // : Cost 3 vext1 <3,u,4,7>, <3,u,4,7> - 2567744822U, // : Cost 3 vext1 <2,u,4,7>, RHS - 2712071624U, // : Cost 3 vext3 RHS, <4,7,5,0> - 96808489U, // : Cost 1 vrev RHS - 2651715180U, // : Cost 3 vext2 <5,6,u,4>, <7,7,7,7> - 96955963U, // : Cost 1 vrev RHS - 1482063974U, // : Cost 2 vext1 <0,u,4,u>, LHS - 1551431470U, // : Cost 2 vext2 <1,2,u,4>, LHS - 1494009958U, // : Cost 2 vext1 <2,u,4,u>, <2,u,4,u> - 2555807894U, // : Cost 3 vext1 <0,u,4,u>, <3,0,1,2> - 161926454U, // : Cost 1 vdup0 RHS - 1551431834U, // : Cost 2 vext2 <1,2,u,4>, RHS - 537751081U, // : Cost 1 vext3 LHS, RHS - 2830110249U, // : Cost 3 vuzpr <1,u,3,4>, RHS - 537751099U, // : Cost 1 vext3 LHS, RHS - 2631811072U, // : Cost 3 vext2 <2,3,u,5>, <0,0,0,0> - 1558069350U, // : Cost 2 vext2 <2,3,u,5>, LHS - 2619203823U, // : Cost 3 vext2 <0,2,u,5>, <0,2,u,5> - 2619867456U, // : Cost 3 vext2 <0,3,u,5>, <0,3,u,5> - 1546273106U, // : Cost 2 vext2 <0,4,1,5>, <0,4,1,5> - 2733010539U, // : Cost 3 vext3 LHS, <5,0,5,1> - 2597622682U, // : Cost 3 vext1 <7,u,5,0>, <6,7,u,5> - 1176539396U, // : Cost 2 vrev <5,u,7,0> - 1558069917U, // : Cost 2 vext2 <2,3,u,5>, LHS - 1505968230U, // : Cost 2 vext1 <4,u,5,1>, LHS - 2624512887U, // : Cost 3 vext2 <1,1,u,5>, <1,1,u,5> - 2631811990U, // : Cost 3 vext2 <2,3,u,5>, <1,2,3,0> - 2618541056U, // : Cost 3 vext2 <0,1,u,5>, <1,3,5,7> - 1505971510U, // : Cost 2 vext1 <4,u,5,1>, RHS - 2627167419U, // : Cost 3 vext2 <1,5,u,5>, <1,5,u,5> - 2579714554U, // : Cost 3 vext1 <4,u,5,1>, <6,2,7,3> - 1638330064U, // : Cost 2 vext3 RHS, <5,1,7,3> - 1638477529U, // : Cost 2 vext3 RHS, <5,1,u,3> - 2561802342U, // : Cost 3 vext1 <1,u,5,2>, LHS - 2561803264U, // : Cost 3 vext1 <1,u,5,2>, <1,3,5,7> - 2631149217U, // : Cost 3 vext2 <2,2,u,5>, <2,2,u,5> - 1558071026U, // : Cost 2 vext2 <2,3,u,5>, <2,3,u,5> - 2561805622U, // : Cost 3 vext1 <1,u,5,2>, RHS - 2714062607U, // : Cost 3 vext3 RHS, <5,2,5,3> - 2631813050U, // : Cost 3 vext2 <2,3,u,5>, <2,6,3,7> - 3092335926U, // : Cost 3 vtrnr <0,u,0,2>, RHS - 1561389191U, // : Cost 2 vext2 <2,u,u,5>, <2,u,u,5> - 2561810534U, // : Cost 3 vext1 <1,u,5,3>, LHS - 2561811857U, // : Cost 3 vext1 <1,u,5,3>, <1,u,5,3> - 2631813474U, // : Cost 3 vext2 <2,3,u,5>, <3,2,5,u> - 2631813532U, // : Cost 3 vext2 <2,3,u,5>, <3,3,3,3> - 2619869698U, // : Cost 3 vext2 <0,3,u,5>, <3,4,5,6> - 3001847002U, // : Cost 3 vzipr LHS, <4,4,5,5> - 2954070530U, // : Cost 3 vzipr LHS, <3,4,5,6> - 2018749750U, // : Cost 2 vtrnr LHS, RHS - 2018749751U, // : Cost 2 vtrnr LHS, RHS - 2573762662U, // : Cost 3 vext1 <3,u,5,4>, LHS - 2620017634U, // : Cost 3 vext2 <0,4,1,5>, <4,1,5,0> - 2573764338U, // : Cost 3 vext1 <3,u,5,4>, <2,3,u,5> - 2573765444U, // : Cost 3 vext1 <3,u,5,4>, <3,u,5,4> - 1570680053U, // : Cost 2 vext2 <4,4,u,5>, <4,4,u,5> - 1558072630U, // : Cost 2 vext2 <2,3,u,5>, RHS - 2645749143U, // : Cost 3 vext2 <4,6,u,5>, <4,6,u,5> - 1638330310U, // : Cost 2 vext3 RHS, <5,4,7,6> - 1558072873U, // : Cost 2 vext2 <2,3,u,5>, RHS - 1506000998U, // : Cost 2 vext1 <4,u,5,5>, LHS - 2561827984U, // : Cost 3 vext1 <1,u,5,5>, <1,5,3,7> - 2579744360U, // : Cost 3 vext1 <4,u,5,5>, <2,2,2,2> - 2579744918U, // : Cost 3 vext1 <4,u,5,5>, <3,0,1,2> - 1506004278U, // : Cost 2 vext1 <4,u,5,5>, RHS - 229035318U, // : Cost 1 vdup1 RHS - 2712072206U, // : Cost 3 vext3 RHS, <5,5,6,6> - 1638330392U, // : Cost 2 vext3 RHS, <5,5,7,7> - 229035318U, // : Cost 1 vdup1 RHS - 1500037222U, // : Cost 2 vext1 <3,u,5,6>, LHS - 2561836436U, // : Cost 3 vext1 <1,u,5,6>, <1,u,5,6> - 2567809133U, // : Cost 3 vext1 <2,u,5,6>, <2,u,5,6> - 1500040006U, // : Cost 2 vext1 <3,u,5,6>, <3,u,5,6> - 1500040502U, // : Cost 2 vext1 <3,u,5,6>, RHS - 2714062935U, // : Cost 3 vext3 RHS, <5,6,5,7> - 2712072288U, // : Cost 3 vext3 RHS, <5,6,6,7> - 27705344U, // : Cost 0 copy RHS - 27705344U, // : Cost 0 copy RHS - 1488101478U, // : Cost 2 vext1 <1,u,5,7>, LHS - 1488102805U, // : Cost 2 vext1 <1,u,5,7>, <1,u,5,7> - 2561844840U, // : Cost 3 vext1 <1,u,5,7>, <2,2,2,2> - 2561845398U, // : Cost 3 vext1 <1,u,5,7>, <3,0,1,2> - 1488104758U, // : Cost 2 vext1 <1,u,5,7>, RHS - 1638330536U, // : Cost 2 vext3 RHS, <5,7,5,7> - 2712072362U, // : Cost 3 vext3 RHS, <5,7,6,0> - 2042965302U, // : Cost 2 vtrnr RHS, RHS - 1488107310U, // : Cost 2 vext1 <1,u,5,7>, LHS - 1488109670U, // : Cost 2 vext1 <1,u,5,u>, LHS - 1488110998U, // : Cost 2 vext1 <1,u,5,u>, <1,u,5,u> - 2561853032U, // : Cost 3 vext1 <1,u,5,u>, <2,2,2,2> - 1500056392U, // : Cost 2 vext1 <3,u,5,u>, <3,u,5,u> - 1488112950U, // : Cost 2 vext1 <1,u,5,u>, RHS - 229035318U, // : Cost 1 vdup1 RHS - 2954111490U, // : Cost 3 vzipr LHS, <3,4,5,6> - 27705344U, // : Cost 0 copy RHS - 27705344U, // : Cost 0 copy RHS - 2619211776U, // : Cost 3 vext2 <0,2,u,6>, <0,0,0,0> - 1545470054U, // : Cost 2 vext2 <0,2,u,6>, LHS - 1545470192U, // : Cost 2 vext2 <0,2,u,6>, <0,2,u,6> - 2255958969U, // : Cost 3 vrev <6,u,3,0> - 1546797458U, // : Cost 2 vext2 <0,4,u,6>, <0,4,u,6> - 2720624971U, // : Cost 3 vext3 <6,0,5,u>, <6,0,5,u> - 2256180180U, // : Cost 3 vrev <6,u,6,0> - 2960682294U, // : Cost 3 vzipr <1,2,u,0>, RHS - 1545470621U, // : Cost 2 vext2 <0,2,u,6>, LHS - 1182004127U, // : Cost 2 vrev <6,u,0,1> - 2619212596U, // : Cost 3 vext2 <0,2,u,6>, <1,1,1,1> - 2619212694U, // : Cost 3 vext2 <0,2,u,6>, <1,2,3,0> - 2619212760U, // : Cost 3 vext2 <0,2,u,6>, <1,3,1,3> - 2626511979U, // : Cost 3 vext2 <1,4,u,6>, <1,4,u,6> - 2619212944U, // : Cost 3 vext2 <0,2,u,6>, <1,5,3,7> - 2714063264U, // : Cost 3 vext3 RHS, <6,1,6,3> - 2967326006U, // : Cost 3 vzipr <2,3,u,1>, RHS - 1182594023U, // : Cost 2 vrev <6,u,u,1> - 1506050150U, // : Cost 2 vext1 <4,u,6,2>, LHS - 2579792630U, // : Cost 3 vext1 <4,u,6,2>, <1,0,3,2> - 2619213416U, // : Cost 3 vext2 <0,2,u,6>, <2,2,2,2> - 2619213478U, // : Cost 3 vext2 <0,2,u,6>, <2,3,0,1> - 1506053430U, // : Cost 2 vext1 <4,u,6,2>, RHS - 2633148309U, // : Cost 3 vext2 <2,5,u,6>, <2,5,u,6> - 2619213754U, // : Cost 3 vext2 <0,2,u,6>, <2,6,3,7> - 1638330874U, // : Cost 2 vext3 RHS, <6,2,7,3> - 1638478339U, // : Cost 2 vext3 RHS, <6,2,u,3> - 2619213974U, // : Cost 3 vext2 <0,2,u,6>, <3,0,1,2> - 2255836074U, // : Cost 3 vrev <6,u,1,3> - 2255909811U, // : Cost 3 vrev <6,u,2,3> - 2619214236U, // : Cost 3 vext2 <0,2,u,6>, <3,3,3,3> - 1564715549U, // : Cost 2 vext2 <3,4,u,6>, <3,4,u,6> - 2639121006U, // : Cost 3 vext2 <3,5,u,6>, <3,5,u,6> - 3001847012U, // : Cost 3 vzipr LHS, <4,4,6,6> - 1880329526U, // : Cost 2 vzipr LHS, RHS - 1880329527U, // : Cost 2 vzipr LHS, RHS - 2567864422U, // : Cost 3 vext1 <2,u,6,4>, LHS - 2733011558U, // : Cost 3 vext3 LHS, <6,4,1,3> - 2567866484U, // : Cost 3 vext1 <2,u,6,4>, <2,u,6,4> - 2638458005U, // : Cost 3 vext2 <3,4,u,6>, <4,3,6,u> - 1570540772U, // : Cost 2 vext2 <4,4,6,6>, <4,4,6,6> - 1545473334U, // : Cost 2 vext2 <0,2,u,6>, RHS - 1572015512U, // : Cost 2 vext2 <4,6,u,6>, <4,6,u,6> - 2960715062U, // : Cost 3 vzipr <1,2,u,4>, RHS - 1545473577U, // : Cost 2 vext2 <0,2,u,6>, RHS - 2567872614U, // : Cost 3 vext1 <2,u,6,5>, LHS - 2645757648U, // : Cost 3 vext2 <4,6,u,6>, <5,1,7,3> - 2567874490U, // : Cost 3 vext1 <2,u,6,5>, <2,6,3,7> - 2576501250U, // : Cost 3 vext1 <4,3,6,5>, <3,4,5,6> - 1576660943U, // : Cost 2 vext2 <5,4,u,6>, <5,4,u,6> - 2645757956U, // : Cost 3 vext2 <4,6,u,6>, <5,5,5,5> - 2645758050U, // : Cost 3 vext2 <4,6,u,6>, <5,6,7,0> - 2824080694U, // : Cost 3 vuzpr <0,u,2,6>, RHS - 1182626795U, // : Cost 2 vrev <6,u,u,5> - 1506082918U, // : Cost 2 vext1 <4,u,6,6>, LHS - 2579825398U, // : Cost 3 vext1 <4,u,6,6>, <1,0,3,2> - 2645758458U, // : Cost 3 vext2 <4,6,u,6>, <6,2,7,3> - 2579826838U, // : Cost 3 vext1 <4,u,6,6>, <3,0,1,2> - 1506086198U, // : Cost 2 vext1 <4,u,6,6>, RHS - 2579828432U, // : Cost 3 vext1 <4,u,6,6>, <5,1,7,3> - 296144182U, // : Cost 1 vdup2 RHS - 1638331202U, // : Cost 2 vext3 RHS, <6,6,7,7> - 296144182U, // : Cost 1 vdup2 RHS - 432349286U, // : Cost 1 vext1 RHS, LHS - 1506091766U, // : Cost 2 vext1 RHS, <1,0,3,2> - 1506092648U, // : Cost 2 vext1 RHS, <2,2,2,2> - 1506093206U, // : Cost 2 vext1 RHS, <3,0,1,2> - 432352809U, // : Cost 1 vext1 RHS, RHS - 1506094800U, // : Cost 2 vext1 RHS, <5,1,7,3> - 1506095610U, // : Cost 2 vext1 RHS, <6,2,7,3> - 1906904374U, // : Cost 2 vzipr RHS, RHS - 432355118U, // : Cost 1 vext1 RHS, LHS - 432357478U, // : Cost 1 vext1 RHS, LHS - 1545475886U, // : Cost 2 vext2 <0,2,u,6>, LHS - 1506100840U, // : Cost 2 vext1 RHS, <2,2,2,2> - 1506101398U, // : Cost 2 vext1 RHS, <3,0,1,2> - 432361002U, // : Cost 1 vext1 RHS, RHS - 1545476250U, // : Cost 2 vext2 <0,2,u,6>, RHS - 296144182U, // : Cost 1 vdup2 RHS - 1880370486U, // : Cost 2 vzipr LHS, RHS - 432363310U, // : Cost 1 vext1 RHS, LHS - 1571356672U, // : Cost 2 vext2 RHS, <0,0,0,0> - 497614950U, // : Cost 1 vext2 RHS, LHS - 1571356836U, // : Cost 2 vext2 RHS, <0,2,0,2> - 2573880146U, // : Cost 3 vext1 <3,u,7,0>, <3,u,7,0> - 1571357010U, // : Cost 2 vext2 RHS, <0,4,1,5> - 1512083716U, // : Cost 2 vext1 <5,u,7,0>, <5,u,7,0> - 2621874741U, // : Cost 3 vext2 <0,6,u,7>, <0,6,u,7> - 2585826298U, // : Cost 3 vext1 <5,u,7,0>, <7,0,1,2> - 497615517U, // : Cost 1 vext2 RHS, LHS - 1571357430U, // : Cost 2 vext2 RHS, <1,0,3,2> - 1571357492U, // : Cost 2 vext2 RHS, <1,1,1,1> - 1571357590U, // : Cost 2 vext2 RHS, <1,2,3,0> - 1552114715U, // : Cost 2 vext2 <1,3,u,7>, <1,3,u,7> - 2573888822U, // : Cost 3 vext1 <3,u,7,1>, RHS - 1553441981U, // : Cost 2 vext2 <1,5,u,7>, <1,5,u,7> - 2627847438U, // : Cost 3 vext2 <1,6,u,7>, <1,6,u,7> - 2727408775U, // : Cost 3 vext3 <7,1,7,u>, <7,1,7,u> - 1555432880U, // : Cost 2 vext2 <1,u,u,7>, <1,u,u,7> - 2629838337U, // : Cost 3 vext2 <2,0,u,7>, <2,0,u,7> - 1188058754U, // : Cost 2 vrev <7,u,1,2> - 1571358312U, // : Cost 2 vext2 RHS, <2,2,2,2> - 1571358374U, // : Cost 2 vext2 RHS, <2,3,0,1> - 2632492869U, // : Cost 3 vext2 <2,4,u,7>, <2,4,u,7> - 2633156502U, // : Cost 3 vext2 <2,5,u,7>, <2,5,u,7> - 1560078311U, // : Cost 2 vext2 <2,6,u,7>, <2,6,u,7> - 2728072408U, // : Cost 3 vext3 <7,2,7,u>, <7,2,7,u> - 1561405577U, // : Cost 2 vext2 <2,u,u,7>, <2,u,u,7> - 1571358870U, // : Cost 2 vext2 RHS, <3,0,1,2> - 2627184913U, // : Cost 3 vext2 <1,5,u,7>, <3,1,5,u> - 2633820523U, // : Cost 3 vext2 <2,6,u,7>, <3,2,6,u> - 1571359132U, // : Cost 2 vext2 RHS, <3,3,3,3> - 1571359234U, // : Cost 2 vext2 RHS, <3,4,5,6> - 1512108295U, // : Cost 2 vext1 <5,u,7,3>, <5,u,7,3> - 1518080992U, // : Cost 2 vext1 <6,u,7,3>, <6,u,7,3> - 2640456465U, // : Cost 3 vext2 <3,7,u,7>, <3,7,u,7> - 1571359518U, // : Cost 2 vext2 RHS, <3,u,1,2> - 1571359634U, // : Cost 2 vext2 RHS, <4,0,5,1> - 2573911067U, // : Cost 3 vext1 <3,u,7,4>, <1,3,u,7> - 2645101622U, // : Cost 3 vext2 RHS, <4,2,5,3> - 2573912918U, // : Cost 3 vext1 <3,u,7,4>, <3,u,7,4> - 1571359952U, // : Cost 2 vext2 RHS, <4,4,4,4> - 497618248U, // : Cost 1 vext2 RHS, RHS - 1571360116U, // : Cost 2 vext2 RHS, <4,6,4,6> - 2645102024U, // : Cost 3 vext2 RHS, <4,7,5,0> - 497618473U, // : Cost 1 vext2 RHS, RHS - 2645102152U, // : Cost 3 vext2 RHS, <5,0,1,2> - 1571360464U, // : Cost 2 vext2 RHS, <5,1,7,3> - 2645102334U, // : Cost 3 vext2 RHS, <5,2,3,4> - 2645102447U, // : Cost 3 vext2 RHS, <5,3,7,0> - 1571360710U, // : Cost 2 vext2 RHS, <5,4,7,6> - 1571360772U, // : Cost 2 vext2 RHS, <5,5,5,5> - 1571360866U, // : Cost 2 vext2 RHS, <5,6,7,0> - 1571360936U, // : Cost 2 vext2 RHS, <5,7,5,7> - 1571361017U, // : Cost 2 vext2 RHS, <5,u,5,7> - 1530044518U, // : Cost 2 vext1 , LHS - 2645103016U, // : Cost 3 vext2 RHS, <6,1,7,2> - 1571361274U, // : Cost 2 vext2 RHS, <6,2,7,3> - 2645103154U, // : Cost 3 vext2 RHS, <6,3,4,5> - 1530047798U, // : Cost 2 vext1 , RHS - 1188386474U, // : Cost 2 vrev <7,u,5,6> - 1571361592U, // : Cost 2 vext2 RHS, <6,6,6,6> - 1571361614U, // : Cost 2 vext2 RHS, <6,7,0,1> - 1571361695U, // : Cost 2 vext2 RHS, <6,u,0,1> - 1571361786U, // : Cost 2 vext2 RHS, <7,0,1,2> - 2573935616U, // : Cost 3 vext1 <3,u,7,7>, <1,3,5,7> - 2645103781U, // : Cost 3 vext2 RHS, <7,2,2,2> - 2573937497U, // : Cost 3 vext1 <3,u,7,7>, <3,u,7,7> - 1571362150U, // : Cost 2 vext2 RHS, <7,4,5,6> - 1512141067U, // : Cost 2 vext1 <5,u,7,7>, <5,u,7,7> - 1518113764U, // : Cost 2 vext1 <6,u,7,7>, <6,u,7,7> - 363253046U, // : Cost 1 vdup3 RHS - 363253046U, // : Cost 1 vdup3 RHS - 1571362515U, // : Cost 2 vext2 RHS, - 497620782U, // : Cost 1 vext2 RHS, LHS - 1571362693U, // : Cost 2 vext2 RHS, - 1571362748U, // : Cost 2 vext2 RHS, - 1571362879U, // : Cost 2 vext2 RHS, - 497621146U, // : Cost 1 vext2 RHS, RHS - 1571363024U, // : Cost 2 vext2 RHS, - 363253046U, // : Cost 1 vdup3 RHS - 497621349U, // : Cost 1 vext2 RHS, LHS - 135053414U, // : Cost 1 vdup0 LHS - 471081121U, // : Cost 1 vext2 LHS, LHS - 1544822948U, // : Cost 2 vext2 LHS, <0,2,0,2> - 1616140005U, // : Cost 2 vext3 LHS, - 1544823122U, // : Cost 2 vext2 LHS, <0,4,1,5> - 1512157453U, // : Cost 2 vext1 <5,u,u,0>, <5,u,u,0> - 1662220032U, // : Cost 2 vext3 RHS, - 1194457487U, // : Cost 2 vrev - 471081629U, // : Cost 1 vext2 LHS, LHS - 1544823542U, // : Cost 2 vext2 LHS, <1,0,3,2> - 202162278U, // : Cost 1 vdup1 LHS - 537753390U, // : Cost 1 vext3 LHS, LHS - 1544823768U, // : Cost 2 vext2 LHS, <1,3,1,3> - 1494248758U, // : Cost 2 vext1 <2,u,u,1>, RHS - 1544823952U, // : Cost 2 vext2 LHS, <1,5,3,7> - 1518138343U, // : Cost 2 vext1 <6,u,u,1>, <6,u,u,1> - 1640322907U, // : Cost 2 vext3 RHS, - 537753444U, // : Cost 1 vext3 LHS, LHS - 1482309734U, // : Cost 2 vext1 <0,u,u,2>, LHS - 1194031451U, // : Cost 2 vrev - 269271142U, // : Cost 1 vdup2 LHS - 835584U, // : Cost 0 copy LHS - 1482313014U, // : Cost 2 vext1 <0,u,u,2>, RHS - 2618566504U, // : Cost 3 vext2 LHS, <2,5,3,6> - 1544824762U, // : Cost 2 vext2 LHS, <2,6,3,7> - 1638479788U, // : Cost 2 vext3 RHS, - 835584U, // : Cost 0 copy LHS - 408576723U, // : Cost 1 vext1 LHS, LHS - 1482318582U, // : Cost 2 vext1 LHS, <1,0,3,2> - 120371557U, // : Cost 1 vrev LHS - 336380006U, // : Cost 1 vdup3 LHS - 408579382U, // : Cost 1 vext1 LHS, RHS - 1616140271U, // : Cost 2 vext3 LHS, - 1530098170U, // : Cost 2 vext1 LHS, <6,2,7,3> - 1880329544U, // : Cost 2 vzipr LHS, RHS - 408581934U, // : Cost 1 vext1 LHS, LHS - 1488298086U, // : Cost 2 vext1 <1,u,u,4>, LHS - 1488299437U, // : Cost 2 vext1 <1,u,u,4>, <1,u,u,4> - 1659271204U, // : Cost 2 vext3 LHS, - 1194195311U, // : Cost 2 vrev - 161926454U, // : Cost 1 vdup0 RHS - 471084342U, // : Cost 1 vext2 LHS, RHS - 1571368308U, // : Cost 2 vext2 RHS, <4,6,4,6> - 1640323153U, // : Cost 2 vext3 RHS, - 471084585U, // : Cost 1 vext2 LHS, RHS - 1494278246U, // : Cost 2 vext1 <2,u,u,5>, LHS - 1571368656U, // : Cost 2 vext2 RHS, <5,1,7,3> - 1494280327U, // : Cost 2 vext1 <2,u,u,5>, <2,u,u,5> - 1616140415U, // : Cost 2 vext3 LHS, - 1494281526U, // : Cost 2 vext1 <2,u,u,5>, RHS - 229035318U, // : Cost 1 vdup1 RHS - 537753754U, // : Cost 1 vext3 LHS, RHS - 1750355254U, // : Cost 2 vuzpr LHS, RHS - 537753772U, // : Cost 1 vext3 LHS, RHS - 1482342502U, // : Cost 2 vext1 <0,u,u,6>, LHS - 2556084982U, // : Cost 3 vext1 <0,u,u,6>, <1,0,3,2> - 1571369466U, // : Cost 2 vext2 RHS, <6,2,7,3> - 1611938000U, // : Cost 2 vext3 LHS, - 1482345782U, // : Cost 2 vext1 <0,u,u,6>, RHS - 1194359171U, // : Cost 2 vrev - 296144182U, // : Cost 1 vdup2 RHS - 27705344U, // : Cost 0 copy RHS - 27705344U, // : Cost 0 copy RHS - 432496742U, // : Cost 1 vext1 RHS, LHS - 1488324016U, // : Cost 2 vext1 <1,u,u,7>, <1,u,u,7> - 1494296713U, // : Cost 2 vext1 <2,u,u,7>, <2,u,u,7> - 1906901148U, // : Cost 2 vzipr RHS, LHS - 432500283U, // : Cost 1 vext1 RHS, RHS - 1506242256U, // : Cost 2 vext1 RHS, <5,1,7,3> - 120699277U, // : Cost 1 vrev RHS - 363253046U, // : Cost 1 vdup3 RHS - 432502574U, // : Cost 1 vext1 RHS, LHS - 408617688U, // : Cost 1 vext1 LHS, LHS - 471086894U, // : Cost 1 vext2 LHS, LHS - 537753957U, // : Cost 1 vext3 LHS, LHS - 835584U, // : Cost 0 copy LHS - 408620342U, // : Cost 1 vext1 LHS, RHS - 471087258U, // : Cost 1 vext2 LHS, RHS - 537753997U, // : Cost 1 vext3 LHS, RHS - 27705344U, // : Cost 0 copy RHS - 835584U, // : Cost 0 copy LHS + 135053414U, // <0,0,0,0>: Cost 1 vdup0 LHS + 1543503974U, // <0,0,0,1>: Cost 2 vext2 <0,0,0,0>, LHS + 2618572962U, // <0,0,0,2>: Cost 3 vext2 <0,2,0,0>, <0,2,0,0> + 2232510603U, // <0,0,0,3>: Cost 3 vrev <3,0,0,0> + 1476398390U, // <0,0,0,4>: Cost 2 vext1 <0,0,0,0>, RHS + 2550140624U, // <0,0,0,5>: Cost 3 vext1 <0,0,0,0>, <5,1,7,3> + 2550141434U, // <0,0,0,6>: Cost 3 vext1 <0,0,0,0>, <6,2,7,3> + 2256401391U, // <0,0,0,7>: Cost 3 vrev <7,0,0,0> + 135053414U, // <0,0,0,u>: Cost 1 vdup0 LHS + 2886516736U, // <0,0,1,0>: Cost 3 vzipl LHS, <0,0,0,0> + 1812775014U, // <0,0,1,1>: Cost 2 vzipl LHS, LHS + 1618133094U, // <0,0,1,2>: Cost 2 vext3 <1,2,3,0>, LHS + 2625209292U, // <0,0,1,3>: Cost 3 vext2 <1,3,0,0>, <1,3,0,0> + 2886558034U, // <0,0,1,4>: Cost 3 vzipl LHS, <0,4,1,5> + 2617246864U, // <0,0,1,5>: Cost 3 vext2 <0,0,0,0>, <1,5,3,7> + 3659723031U, // <0,0,1,6>: Cost 4 vext1 <6,0,0,1>, <6,0,0,1> + 2591953904U, // <0,0,1,7>: Cost 3 vext1 <7,0,0,1>, <7,0,0,1> + 1812775581U, // <0,0,1,u>: Cost 2 vzipl LHS, LHS + 3020734464U, // <0,0,2,0>: Cost 3 vtrnl LHS, <0,0,0,0> + 3020734474U, // <0,0,2,1>: Cost 3 vtrnl LHS, <0,0,1,1> + 1946992742U, // <0,0,2,2>: Cost 2 vtrnl LHS, LHS + 2631181989U, // <0,0,2,3>: Cost 3 vext2 <2,3,0,0>, <2,3,0,0> + 3020734668U, // <0,0,2,4>: Cost 3 vtrnl LHS, <0,2,4,6> + 3826550569U, // <0,0,2,5>: Cost 4 vuzpl <0,2,0,2>, <2,4,5,6> + 2617247674U, // <0,0,2,6>: Cost 3 vext2 <0,0,0,0>, <2,6,3,7> + 2591962097U, // <0,0,2,7>: Cost 3 vext1 <7,0,0,2>, <7,0,0,2> + 1946992796U, // <0,0,2,u>: Cost 2 vtrnl LHS, LHS + 2635163787U, // <0,0,3,0>: Cost 3 vext2 <3,0,0,0>, <3,0,0,0> + 2686419196U, // <0,0,3,1>: Cost 3 vext3 <0,3,1,0>, <0,3,1,0> + 2691875078U, // <0,0,3,2>: Cost 3 vext3 <1,2,3,0>, <0,3,2,1> + 2617248156U, // <0,0,3,3>: Cost 3 vext2 <0,0,0,0>, <3,3,3,3> + 2617248258U, // <0,0,3,4>: Cost 3 vext2 <0,0,0,0>, <3,4,5,6> + 3826551298U, // <0,0,3,5>: Cost 4 vuzpl <0,2,0,2>, <3,4,5,6> + 3690990200U, // <0,0,3,6>: Cost 4 vext2 <0,0,0,0>, <3,6,0,7> + 3713551042U, // <0,0,3,7>: Cost 4 vext2 <3,7,0,0>, <3,7,0,0> + 2695856444U, // <0,0,3,u>: Cost 3 vext3 <1,u,3,0>, <0,3,u,1> + 2617248658U, // <0,0,4,0>: Cost 3 vext2 <0,0,0,0>, <4,0,5,1> + 2888450150U, // <0,0,4,1>: Cost 3 vzipl <0,4,1,5>, LHS + 3021570150U, // <0,0,4,2>: Cost 3 vtrnl <0,2,4,6>, LHS + 3772326241U, // <0,0,4,3>: Cost 4 vext3 <2,3,4,0>, <0,4,3,2> + 3021570252U, // <0,0,4,4>: Cost 3 vtrnl <0,2,4,6>, <0,2,4,6> + 1543507254U, // <0,0,4,5>: Cost 2 vext2 <0,0,0,0>, RHS + 2752810294U, // <0,0,4,6>: Cost 3 vuzpl <0,2,0,2>, RHS + 3786998152U, // <0,0,4,7>: Cost 4 vext3 <4,7,5,0>, <0,4,7,5> + 1543507497U, // <0,0,4,u>: Cost 2 vext2 <0,0,0,0>, RHS + 2684354972U, // <0,0,5,0>: Cost 3 vext3 <0,0,0,0>, <0,5,0,7> + 2617249488U, // <0,0,5,1>: Cost 3 vext2 <0,0,0,0>, <5,1,7,3> + 3635865015U, // <0,0,5,2>: Cost 4 vext1 <2,0,0,5>, <2,0,0,5> + 3635865780U, // <0,0,5,3>: Cost 4 vext1 <2,0,0,5>, <3,0,4,5> + 3761709497U, // <0,0,5,4>: Cost 4 vext3 <0,5,4,0>, <0,5,4,0> + 2617249796U, // <0,0,5,5>: Cost 3 vext2 <0,0,0,0>, <5,5,5,5> + 2718712274U, // <0,0,5,6>: Cost 3 vext3 <5,6,7,0>, <0,5,6,7> + 2617249960U, // <0,0,5,7>: Cost 3 vext2 <0,0,0,0>, <5,7,5,7> + 2720039396U, // <0,0,5,u>: Cost 3 vext3 <5,u,7,0>, <0,5,u,7> + 2684355053U, // <0,0,6,0>: Cost 3 vext3 <0,0,0,0>, <0,6,0,7> + 3963609190U, // <0,0,6,1>: Cost 4 vzipl <0,6,2,7>, LHS + 2617250298U, // <0,0,6,2>: Cost 3 vext2 <0,0,0,0>, <6,2,7,3> + 3796435464U, // <0,0,6,3>: Cost 4 vext3 <6,3,7,0>, <0,6,3,7> + 3773137420U, // <0,0,6,4>: Cost 4 vext3 <2,4,6,0>, <0,6,4,2> + 3785744919U, // <0,0,6,5>: Cost 4 vext3 <4,5,6,0>, <0,6,5,4> + 2617250616U, // <0,0,6,6>: Cost 3 vext2 <0,0,0,0>, <6,6,6,6> + 2657727309U, // <0,0,6,7>: Cost 3 vext2 <6,7,0,0>, <6,7,0,0> + 2658390942U, // <0,0,6,u>: Cost 3 vext2 <6,u,0,0>, <6,u,0,0> + 2659054575U, // <0,0,7,0>: Cost 3 vext2 <7,0,0,0>, <7,0,0,0> + 2689073728U, // <0,0,7,1>: Cost 3 vext3 <0,7,1,0>, <0,7,1,0> + 3635881401U, // <0,0,7,2>: Cost 4 vext1 <2,0,0,7>, <2,0,0,7> + 3310897858U, // <0,0,7,3>: Cost 4 vrev <3,7,0,0> + 2617251174U, // <0,0,7,4>: Cost 3 vext2 <0,0,0,0>, <7,4,5,6> + 3779846759U, // <0,0,7,5>: Cost 4 vext3 <3,5,7,0>, <0,7,5,3> + 2718712434U, // <0,0,7,6>: Cost 3 vext3 <5,6,7,0>, <0,7,6,5> + 2617251436U, // <0,0,7,7>: Cost 3 vext2 <0,0,0,0>, <7,7,7,7> + 2720039556U, // <0,0,7,u>: Cost 3 vext3 <5,u,7,0>, <0,7,u,5> + 135053414U, // <0,0,u,0>: Cost 1 vdup0 LHS + 1817419878U, // <0,0,u,1>: Cost 2 vzipl LHS, LHS + 1947435110U, // <0,0,u,2>: Cost 2 vtrnl LHS, LHS + 2568120467U, // <0,0,u,3>: Cost 3 vext1 <3,0,0,u>, <3,0,0,u> + 1476463926U, // <0,0,u,4>: Cost 2 vext1 <0,0,0,u>, RHS + 1543510170U, // <0,0,u,5>: Cost 2 vext2 <0,0,0,0>, RHS + 2752813210U, // <0,0,u,6>: Cost 3 vuzpl <0,2,0,2>, RHS + 2592011255U, // <0,0,u,7>: Cost 3 vext1 <7,0,0,u>, <7,0,0,u> + 135053414U, // <0,0,u,u>: Cost 1 vdup0 LHS + 2618581002U, // <0,1,0,0>: Cost 3 vext2 <0,2,0,1>, <0,0,1,1> + 1557446758U, // <0,1,0,1>: Cost 2 vext2 <2,3,0,1>, LHS + 2618581155U, // <0,1,0,2>: Cost 3 vext2 <0,2,0,1>, <0,2,0,1> + 2690548468U, // <0,1,0,3>: Cost 3 vext3 <1,0,3,0>, <1,0,3,0> + 2626543954U, // <0,1,0,4>: Cost 3 vext2 <1,5,0,1>, <0,4,1,5> + 4094985216U, // <0,1,0,5>: Cost 4 vtrnl <0,2,0,2>, <1,3,5,7> + 2592019278U, // <0,1,0,6>: Cost 3 vext1 <7,0,1,0>, <6,7,0,1> + 2256475128U, // <0,1,0,7>: Cost 3 vrev <7,0,1,0> + 1557447325U, // <0,1,0,u>: Cost 2 vext2 <2,3,0,1>, LHS + 1476476938U, // <0,1,1,0>: Cost 2 vext1 <0,0,1,1>, <0,0,1,1> + 2886517556U, // <0,1,1,1>: Cost 3 vzipl LHS, <1,1,1,1> + 2886517654U, // <0,1,1,2>: Cost 3 vzipl LHS, <1,2,3,0> + 2886517720U, // <0,1,1,3>: Cost 3 vzipl LHS, <1,3,1,3> + 1476480310U, // <0,1,1,4>: Cost 2 vext1 <0,0,1,1>, RHS + 2886558864U, // <0,1,1,5>: Cost 3 vzipl LHS, <1,5,3,7> + 2550223354U, // <0,1,1,6>: Cost 3 vext1 <0,0,1,1>, <6,2,7,3> + 2550223856U, // <0,1,1,7>: Cost 3 vext1 <0,0,1,1>, <7,0,0,1> + 1476482862U, // <0,1,1,u>: Cost 2 vext1 <0,0,1,1>, LHS + 1494401126U, // <0,1,2,0>: Cost 2 vext1 <3,0,1,2>, LHS + 3020735284U, // <0,1,2,1>: Cost 3 vtrnl LHS, <1,1,1,1> + 2562172349U, // <0,1,2,2>: Cost 3 vext1 <2,0,1,2>, <2,0,1,2> + 835584U, // <0,1,2,3>: Cost 0 copy LHS + 1494404406U, // <0,1,2,4>: Cost 2 vext1 <3,0,1,2>, RHS + 3020735488U, // <0,1,2,5>: Cost 3 vtrnl LHS, <1,3,5,7> + 2631190458U, // <0,1,2,6>: Cost 3 vext2 <2,3,0,1>, <2,6,3,7> + 1518294010U, // <0,1,2,7>: Cost 2 vext1 <7,0,1,2>, <7,0,1,2> + 835584U, // <0,1,2,u>: Cost 0 copy LHS + 2692318156U, // <0,1,3,0>: Cost 3 vext3 <1,3,0,0>, <1,3,0,0> + 2691875800U, // <0,1,3,1>: Cost 3 vext3 <1,2,3,0>, <1,3,1,3> + 2691875806U, // <0,1,3,2>: Cost 3 vext3 <1,2,3,0>, <1,3,2,0> + 2692539367U, // <0,1,3,3>: Cost 3 vext3 <1,3,3,0>, <1,3,3,0> + 2562182454U, // <0,1,3,4>: Cost 3 vext1 <2,0,1,3>, RHS + 2691875840U, // <0,1,3,5>: Cost 3 vext3 <1,2,3,0>, <1,3,5,7> + 2692760578U, // <0,1,3,6>: Cost 3 vext3 <1,3,6,0>, <1,3,6,0> + 2639817411U, // <0,1,3,7>: Cost 3 vext2 <3,7,0,1>, <3,7,0,1> + 2691875863U, // <0,1,3,u>: Cost 3 vext3 <1,2,3,0>, <1,3,u,3> + 2568159334U, // <0,1,4,0>: Cost 3 vext1 <3,0,1,4>, LHS + 4095312692U, // <0,1,4,1>: Cost 4 vtrnl <0,2,4,6>, <1,1,1,1> + 2568160934U, // <0,1,4,2>: Cost 3 vext1 <3,0,1,4>, <2,3,0,1> + 2568161432U, // <0,1,4,3>: Cost 3 vext1 <3,0,1,4>, <3,0,1,4> + 2568162614U, // <0,1,4,4>: Cost 3 vext1 <3,0,1,4>, RHS + 1557450038U, // <0,1,4,5>: Cost 2 vext2 <2,3,0,1>, RHS + 2754235702U, // <0,1,4,6>: Cost 3 vuzpl <0,4,1,5>, RHS + 2592052220U, // <0,1,4,7>: Cost 3 vext1 <7,0,1,4>, <7,0,1,4> + 1557450281U, // <0,1,4,u>: Cost 2 vext2 <2,3,0,1>, RHS + 2217984414U, // <0,1,5,0>: Cost 3 vrev <0,5,1,0> + 2647781007U, // <0,1,5,1>: Cost 3 vext2 <5,1,0,1>, <5,1,0,1> + 3704934138U, // <0,1,5,2>: Cost 4 vext2 <2,3,0,1>, <5,2,3,0> + 2691875984U, // <0,1,5,3>: Cost 3 vext3 <1,2,3,0>, <1,5,3,7> + 2649771906U, // <0,1,5,4>: Cost 3 vext2 <5,4,0,1>, <5,4,0,1> + 2650435539U, // <0,1,5,5>: Cost 3 vext2 <5,5,0,1>, <5,5,0,1> + 2651099172U, // <0,1,5,6>: Cost 3 vext2 <5,6,0,1>, <5,6,0,1> + 2651762805U, // <0,1,5,7>: Cost 3 vext2 <5,7,0,1>, <5,7,0,1> + 2691876029U, // <0,1,5,u>: Cost 3 vext3 <1,2,3,0>, <1,5,u,7> + 2592063590U, // <0,1,6,0>: Cost 3 vext1 <7,0,1,6>, LHS + 3765322959U, // <0,1,6,1>: Cost 4 vext3 <1,1,u,0>, <1,6,1,7> + 2654417337U, // <0,1,6,2>: Cost 3 vext2 <6,2,0,1>, <6,2,0,1> + 3765617889U, // <0,1,6,3>: Cost 4 vext3 <1,2,3,0>, <1,6,3,7> + 2592066870U, // <0,1,6,4>: Cost 3 vext1 <7,0,1,6>, RHS + 3765617907U, // <0,1,6,5>: Cost 4 vext3 <1,2,3,0>, <1,6,5,7> + 2657071869U, // <0,1,6,6>: Cost 3 vext2 <6,6,0,1>, <6,6,0,1> + 1583993678U, // <0,1,6,7>: Cost 2 vext2 <6,7,0,1>, <6,7,0,1> + 1584657311U, // <0,1,6,u>: Cost 2 vext2 <6,u,0,1>, <6,u,0,1> + 2657735672U, // <0,1,7,0>: Cost 3 vext2 <6,7,0,1>, <7,0,1,0> + 2657735808U, // <0,1,7,1>: Cost 3 vext2 <6,7,0,1>, <7,1,7,1> + 2631193772U, // <0,1,7,2>: Cost 3 vext2 <2,3,0,1>, <7,2,3,0> + 2661053667U, // <0,1,7,3>: Cost 3 vext2 <7,3,0,1>, <7,3,0,1> + 2657736038U, // <0,1,7,4>: Cost 3 vext2 <6,7,0,1>, <7,4,5,6> + 3704935840U, // <0,1,7,5>: Cost 4 vext2 <2,3,0,1>, <7,5,3,1> + 2657736198U, // <0,1,7,6>: Cost 3 vext2 <6,7,0,1>, <7,6,5,4> + 2657736300U, // <0,1,7,7>: Cost 3 vext2 <6,7,0,1>, <7,7,7,7> + 2657736322U, // <0,1,7,u>: Cost 3 vext2 <6,7,0,1>, <7,u,1,2> + 1494450278U, // <0,1,u,0>: Cost 2 vext1 <3,0,1,u>, LHS + 1557452590U, // <0,1,u,1>: Cost 2 vext2 <2,3,0,1>, LHS + 2754238254U, // <0,1,u,2>: Cost 3 vuzpl <0,4,1,5>, LHS + 835584U, // <0,1,u,3>: Cost 0 copy LHS + 1494453558U, // <0,1,u,4>: Cost 2 vext1 <3,0,1,u>, RHS + 1557452954U, // <0,1,u,5>: Cost 2 vext2 <2,3,0,1>, RHS + 2754238618U, // <0,1,u,6>: Cost 3 vuzpl <0,4,1,5>, RHS + 1518343168U, // <0,1,u,7>: Cost 2 vext1 <7,0,1,u>, <7,0,1,u> + 835584U, // <0,1,u,u>: Cost 0 copy LHS + 2752299008U, // <0,2,0,0>: Cost 3 vuzpl LHS, <0,0,0,0> + 1544847462U, // <0,2,0,1>: Cost 2 vext2 <0,2,0,2>, LHS + 1678557286U, // <0,2,0,2>: Cost 2 vuzpl LHS, LHS + 2696521165U, // <0,2,0,3>: Cost 3 vext3 <2,0,3,0>, <2,0,3,0> + 2752340172U, // <0,2,0,4>: Cost 3 vuzpl LHS, <0,2,4,6> + 2691876326U, // <0,2,0,5>: Cost 3 vext3 <1,2,3,0>, <2,0,5,7> + 2618589695U, // <0,2,0,6>: Cost 3 vext2 <0,2,0,2>, <0,6,2,7> + 2256548865U, // <0,2,0,7>: Cost 3 vrev <7,0,2,0> + 1678557340U, // <0,2,0,u>: Cost 2 vuzpl LHS, LHS + 2703672835U, // <0,2,1,0>: Cost 3 vext3 <3,2,1,0>, <2,1,0,0> + 2752299828U, // <0,2,1,1>: Cost 3 vuzpl LHS, <1,1,1,1> + 2886518376U, // <0,2,1,2>: Cost 3 vzipl LHS, <2,2,2,2> + 2752299926U, // <0,2,1,3>: Cost 3 vuzpl LHS, <1,2,3,0> + 2550295862U, // <0,2,1,4>: Cost 3 vext1 <0,0,2,1>, RHS + 2752340992U, // <0,2,1,5>: Cost 3 vuzpl LHS, <1,3,5,7> + 2886559674U, // <0,2,1,6>: Cost 3 vzipl LHS, <2,6,3,7> + 3934208106U, // <0,2,1,7>: Cost 4 vuzpr <7,0,1,2>, <0,1,2,7> + 2752340931U, // <0,2,1,u>: Cost 3 vuzpl LHS, <1,2,u,0> + 1476558868U, // <0,2,2,0>: Cost 2 vext1 <0,0,2,2>, <0,0,2,2> + 2550301492U, // <0,2,2,1>: Cost 3 vext1 <0,0,2,2>, <1,1,1,1> + 2752300648U, // <0,2,2,2>: Cost 3 vuzpl LHS, <2,2,2,2> + 3020736114U, // <0,2,2,3>: Cost 3 vtrnl LHS, <2,2,3,3> + 1476562230U, // <0,2,2,4>: Cost 2 vext1 <0,0,2,2>, RHS + 2550304464U, // <0,2,2,5>: Cost 3 vext1 <0,0,2,2>, <5,1,7,3> + 2618591162U, // <0,2,2,6>: Cost 3 vext2 <0,2,0,2>, <2,6,3,7> + 2550305777U, // <0,2,2,7>: Cost 3 vext1 <0,0,2,2>, <7,0,0,2> + 1476564782U, // <0,2,2,u>: Cost 2 vext1 <0,0,2,2>, LHS + 2618591382U, // <0,2,3,0>: Cost 3 vext2 <0,2,0,2>, <3,0,1,2> + 2752301206U, // <0,2,3,1>: Cost 3 vuzpl LHS, <3,0,1,2> + 2618591542U, // <0,2,3,2>: Cost 3 vext2 <0,2,0,2>, <3,2,1,0> + 2752301468U, // <0,2,3,3>: Cost 3 vuzpl LHS, <3,3,3,3> + 2618591746U, // <0,2,3,4>: Cost 3 vext2 <0,2,0,2>, <3,4,5,6> + 2752301570U, // <0,2,3,5>: Cost 3 vuzpl LHS, <3,4,5,6> + 3830688102U, // <0,2,3,6>: Cost 4 vuzpl LHS, <3,2,6,3> + 2698807012U, // <0,2,3,7>: Cost 3 vext3 <2,3,7,0>, <2,3,7,0> + 2752301269U, // <0,2,3,u>: Cost 3 vuzpl LHS, <3,0,u,2> + 2562261094U, // <0,2,4,0>: Cost 3 vext1 <2,0,2,4>, LHS + 4095313828U, // <0,2,4,1>: Cost 4 vtrnl <0,2,4,6>, <2,6,1,3> + 2562262472U, // <0,2,4,2>: Cost 3 vext1 <2,0,2,4>, <2,0,2,4> + 2568235169U, // <0,2,4,3>: Cost 3 vext1 <3,0,2,4>, <3,0,2,4> + 2562264374U, // <0,2,4,4>: Cost 3 vext1 <2,0,2,4>, RHS + 1544850742U, // <0,2,4,5>: Cost 2 vext2 <0,2,0,2>, RHS + 1678560566U, // <0,2,4,6>: Cost 2 vuzpl LHS, RHS + 2592125957U, // <0,2,4,7>: Cost 3 vext1 <7,0,2,4>, <7,0,2,4> + 1678560584U, // <0,2,4,u>: Cost 2 vuzpl LHS, RHS + 2691876686U, // <0,2,5,0>: Cost 3 vext3 <1,2,3,0>, <2,5,0,7> + 2618592976U, // <0,2,5,1>: Cost 3 vext2 <0,2,0,2>, <5,1,7,3> + 3765618528U, // <0,2,5,2>: Cost 4 vext3 <1,2,3,0>, <2,5,2,7> + 3765618536U, // <0,2,5,3>: Cost 4 vext3 <1,2,3,0>, <2,5,3,6> + 3696316340U, // <0,2,5,4>: Cost 4 vext2 <0,u,0,2>, <5,4,5,6> + 2752303108U, // <0,2,5,5>: Cost 3 vuzpl LHS, <5,5,5,5> + 2618593378U, // <0,2,5,6>: Cost 3 vext2 <0,2,0,2>, <5,6,7,0> + 2836581686U, // <0,2,5,7>: Cost 3 vuzpr <3,0,1,2>, RHS + 2836581687U, // <0,2,5,u>: Cost 3 vuzpr <3,0,1,2>, RHS + 2752303950U, // <0,2,6,0>: Cost 3 vuzpl LHS, <6,7,0,1> + 3830690081U, // <0,2,6,1>: Cost 4 vuzpl LHS, <6,0,1,2> + 2618593786U, // <0,2,6,2>: Cost 3 vext2 <0,2,0,2>, <6,2,7,3> + 2691876794U, // <0,2,6,3>: Cost 3 vext3 <1,2,3,0>, <2,6,3,7> + 2752303990U, // <0,2,6,4>: Cost 3 vuzpl LHS, <6,7,4,5> + 3830690445U, // <0,2,6,5>: Cost 4 vuzpl LHS, <6,4,5,6> + 2752303928U, // <0,2,6,6>: Cost 3 vuzpl LHS, <6,6,6,6> + 2657743695U, // <0,2,6,7>: Cost 3 vext2 <6,7,0,2>, <6,7,0,2> + 2691876839U, // <0,2,6,u>: Cost 3 vext3 <1,2,3,0>, <2,6,u,7> + 2659070961U, // <0,2,7,0>: Cost 3 vext2 <7,0,0,2>, <7,0,0,2> + 2659734594U, // <0,2,7,1>: Cost 3 vext2 <7,1,0,2>, <7,1,0,2> + 3734140051U, // <0,2,7,2>: Cost 4 vext2 <7,2,0,2>, <7,2,0,2> + 2701166596U, // <0,2,7,3>: Cost 3 vext3 <2,7,3,0>, <2,7,3,0> + 2662389094U, // <0,2,7,4>: Cost 3 vext2 <7,5,0,2>, <7,4,5,6> + 2662389126U, // <0,2,7,5>: Cost 3 vext2 <7,5,0,2>, <7,5,0,2> + 2618594822U, // <0,2,7,6>: Cost 3 vext2 <0,2,0,2>, <7,6,5,4> + 2752304748U, // <0,2,7,7>: Cost 3 vuzpl LHS, <7,7,7,7> + 2659070961U, // <0,2,7,u>: Cost 3 vext2 <7,0,0,2>, <7,0,0,2> + 1476608026U, // <0,2,u,0>: Cost 2 vext1 <0,0,2,u>, <0,0,2,u> + 1544853294U, // <0,2,u,1>: Cost 2 vext2 <0,2,0,2>, LHS + 1678563118U, // <0,2,u,2>: Cost 2 vuzpl LHS, LHS + 3021178482U, // <0,2,u,3>: Cost 3 vtrnl LHS, <2,2,3,3> + 1476611382U, // <0,2,u,4>: Cost 2 vext1 <0,0,2,u>, RHS + 1544853658U, // <0,2,u,5>: Cost 2 vext2 <0,2,0,2>, RHS + 1678563482U, // <0,2,u,6>: Cost 2 vuzpl LHS, RHS + 2836581929U, // <0,2,u,7>: Cost 3 vuzpr <3,0,1,2>, RHS + 1678563172U, // <0,2,u,u>: Cost 2 vuzpl LHS, LHS + 2556329984U, // <0,3,0,0>: Cost 3 vext1 <1,0,3,0>, <0,0,0,0> + 2686421142U, // <0,3,0,1>: Cost 3 vext3 <0,3,1,0>, <3,0,1,2> + 2562303437U, // <0,3,0,2>: Cost 3 vext1 <2,0,3,0>, <2,0,3,0> + 4094986652U, // <0,3,0,3>: Cost 4 vtrnl <0,2,0,2>, <3,3,3,3> + 2556333366U, // <0,3,0,4>: Cost 3 vext1 <1,0,3,0>, RHS + 4094986754U, // <0,3,0,5>: Cost 4 vtrnl <0,2,0,2>, <3,4,5,6> + 3798796488U, // <0,3,0,6>: Cost 4 vext3 <6,7,3,0>, <3,0,6,7> + 3776530634U, // <0,3,0,7>: Cost 4 vext3 <3,0,7,0>, <3,0,7,0> + 2556335918U, // <0,3,0,u>: Cost 3 vext1 <1,0,3,0>, LHS + 2886518934U, // <0,3,1,0>: Cost 3 vzipl LHS, <3,0,1,2> + 2556338933U, // <0,3,1,1>: Cost 3 vext1 <1,0,3,1>, <1,0,3,1> + 2886519094U, // <0,3,1,2>: Cost 3 vzipl LHS, <3,2,1,0> + 2886519196U, // <0,3,1,3>: Cost 3 vzipl LHS, <3,3,3,3> + 2886519298U, // <0,3,1,4>: Cost 3 vzipl LHS, <3,4,5,6> + 4095740418U, // <0,3,1,5>: Cost 4 vtrnl <0,3,1,4>, <3,4,5,6> + 3659944242U, // <0,3,1,6>: Cost 4 vext1 <6,0,3,1>, <6,0,3,1> + 3769600286U, // <0,3,1,7>: Cost 4 vext3 <1,u,3,0>, <3,1,7,3> + 2886519582U, // <0,3,1,u>: Cost 3 vzipl LHS, <3,u,1,2> + 2556346388U, // <0,3,2,0>: Cost 3 vext1 <1,0,3,2>, <0,0,2,2> + 1148371862U, // <0,3,2,1>: Cost 2 vrev <1,2,3,0> + 2562319823U, // <0,3,2,2>: Cost 3 vext1 <2,0,3,2>, <2,0,3,2> + 3020736924U, // <0,3,2,3>: Cost 3 vtrnl LHS, <3,3,3,3> + 2556349750U, // <0,3,2,4>: Cost 3 vext1 <1,0,3,2>, RHS + 3020737026U, // <0,3,2,5>: Cost 3 vtrnl LHS, <3,4,5,6> + 4099123558U, // <0,3,2,6>: Cost 4 vtrnl LHS, <3,2,6,3> + 2257949868U, // <0,3,2,7>: Cost 3 vrev <7,2,3,0> + 1630447989U, // <0,3,2,u>: Cost 2 vext3 <3,2,u,0>, <3,2,u,0> + 2665711772U, // <0,3,3,0>: Cost 3 vext2 , <3,0,1,u> + 2222777319U, // <0,3,3,1>: Cost 3 vrev <1,3,3,0> + 2228750016U, // <0,3,3,2>: Cost 3 vrev <2,3,3,0> + 2691877276U, // <0,3,3,3>: Cost 3 vext3 <1,2,3,0>, <3,3,3,3> + 3961522690U, // <0,3,3,4>: Cost 4 vzipl <0,3,1,4>, <3,4,5,6> + 3826797058U, // <0,3,3,5>: Cost 4 vuzpl <0,2,3,5>, <3,4,5,6> + 3765619124U, // <0,3,3,6>: Cost 4 vext3 <1,2,3,0>, <3,3,6,0> + 3769600452U, // <0,3,3,7>: Cost 4 vext3 <1,u,3,0>, <3,3,7,7> + 2707655111U, // <0,3,3,u>: Cost 3 vext3 <3,u,1,0>, <3,3,u,1> + 3962194070U, // <0,3,4,0>: Cost 4 vzipl <0,4,1,5>, <3,0,1,2> + 4095314070U, // <0,3,4,1>: Cost 4 vtrnl <0,2,4,6>, <3,0,1,2> + 2703673830U, // <0,3,4,2>: Cost 3 vext3 <3,2,1,0>, <3,4,2,5> + 4095314332U, // <0,3,4,3>: Cost 4 vtrnl <0,2,4,6>, <3,3,3,3> + 3962194434U, // <0,3,4,4>: Cost 4 vzipl <0,4,1,5>, <3,4,5,6> + 2691877378U, // <0,3,4,5>: Cost 3 vext3 <1,2,3,0>, <3,4,5,6> + 3826765110U, // <0,3,4,6>: Cost 4 vuzpl <0,2,3,1>, RHS + 3665941518U, // <0,3,4,7>: Cost 4 vext1 <7,0,3,4>, <7,0,3,4> + 2691877405U, // <0,3,4,u>: Cost 3 vext3 <1,2,3,0>, <3,4,u,6> + 3636084838U, // <0,3,5,0>: Cost 4 vext1 <2,0,3,5>, LHS + 3765619248U, // <0,3,5,1>: Cost 4 vext3 <1,2,3,0>, <3,5,1,7> + 3636086226U, // <0,3,5,2>: Cost 4 vext1 <2,0,3,5>, <2,0,3,5> + 3769600578U, // <0,3,5,3>: Cost 4 vext3 <1,u,3,0>, <3,5,3,7> + 3636088118U, // <0,3,5,4>: Cost 4 vext1 <2,0,3,5>, RHS + 3777415764U, // <0,3,5,5>: Cost 4 vext3 <3,2,1,0>, <3,5,5,7> + 2653769826U, // <0,3,5,6>: Cost 3 vext2 <6,1,0,3>, <5,6,7,0> + 2706106975U, // <0,3,5,7>: Cost 3 vext3 <3,5,7,0>, <3,5,7,0> + 2706180712U, // <0,3,5,u>: Cost 3 vext3 <3,5,u,0>, <3,5,u,0> + 2691877496U, // <0,3,6,0>: Cost 3 vext3 <1,2,3,0>, <3,6,0,7> + 2653770090U, // <0,3,6,1>: Cost 3 vext2 <6,1,0,3>, <6,1,0,3> + 3636094419U, // <0,3,6,2>: Cost 4 vext1 <2,0,3,6>, <2,0,3,6> + 3765619347U, // <0,3,6,3>: Cost 4 vext3 <1,2,3,0>, <3,6,3,7> + 3765987996U, // <0,3,6,4>: Cost 4 vext3 <1,2,u,0>, <3,6,4,7> + 3322400830U, // <0,3,6,5>: Cost 4 vrev <5,6,3,0> + 3792456365U, // <0,3,6,6>: Cost 4 vext3 <5,6,7,0>, <3,6,6,6> + 2706770608U, // <0,3,6,7>: Cost 3 vext3 <3,6,7,0>, <3,6,7,0> + 2653770090U, // <0,3,6,u>: Cost 3 vext2 <6,1,0,3>, <6,1,0,3> + 3769600707U, // <0,3,7,0>: Cost 4 vext3 <1,u,3,0>, <3,7,0,1> + 2225431851U, // <0,3,7,1>: Cost 3 vrev <1,7,3,0> + 2231404548U, // <0,3,7,2>: Cost 3 vrev <2,7,3,0> + 3769600740U, // <0,3,7,3>: Cost 4 vext3 <1,u,3,0>, <3,7,3,7> + 3769600747U, // <0,3,7,4>: Cost 4 vext3 <1,u,3,0>, <3,7,4,5> + 3769600758U, // <0,3,7,5>: Cost 4 vext3 <1,u,3,0>, <3,7,5,7> + 2255295336U, // <0,3,7,6>: Cost 3 vrev <6,7,3,0> + 3781176065U, // <0,3,7,7>: Cost 4 vext3 <3,7,7,0>, <3,7,7,0> + 2267240730U, // <0,3,7,u>: Cost 3 vrev + 2891163798U, // <0,3,u,0>: Cost 3 vzipl LHS, <3,0,1,2> + 1152353660U, // <0,3,u,1>: Cost 2 vrev <1,u,3,0> + 2891163958U, // <0,3,u,2>: Cost 3 vzipl LHS, <3,2,1,0> + 3021179292U, // <0,3,u,3>: Cost 3 vtrnl LHS, <3,3,3,3> + 2891164162U, // <0,3,u,4>: Cost 3 vzipl LHS, <3,4,5,6> + 3021179394U, // <0,3,u,5>: Cost 3 vtrnl LHS, <3,4,5,6> + 2255958969U, // <0,3,u,6>: Cost 3 vrev <6,u,3,0> + 2708097874U, // <0,3,u,7>: Cost 3 vext3 <3,u,7,0>, <3,u,7,0> + 1634429787U, // <0,3,u,u>: Cost 2 vext3 <3,u,u,0>, <3,u,u,0> + 2617278468U, // <0,4,0,0>: Cost 3 vext2 <0,0,0,4>, <0,0,0,4> + 2618605670U, // <0,4,0,1>: Cost 3 vext2 <0,2,0,4>, LHS + 2618605734U, // <0,4,0,2>: Cost 3 vext2 <0,2,0,4>, <0,2,0,4> + 3306547375U, // <0,4,0,3>: Cost 4 vrev <3,0,4,0> + 2753134796U, // <0,4,0,4>: Cost 3 vuzpl <0,2,4,6>, <0,2,4,6> + 2718714770U, // <0,4,0,5>: Cost 3 vext3 <5,6,7,0>, <4,0,5,1> + 3021245750U, // <0,4,0,6>: Cost 3 vtrnl <0,2,0,2>, RHS + 3330438163U, // <0,4,0,7>: Cost 4 vrev <7,0,4,0> + 3021245768U, // <0,4,0,u>: Cost 3 vtrnl <0,2,0,2>, RHS + 2568355942U, // <0,4,1,0>: Cost 3 vext1 <3,0,4,1>, LHS + 3692348212U, // <0,4,1,1>: Cost 4 vext2 <0,2,0,4>, <1,1,1,1> + 3692348310U, // <0,4,1,2>: Cost 4 vext2 <0,2,0,4>, <1,2,3,0> + 2568358064U, // <0,4,1,3>: Cost 3 vext1 <3,0,4,1>, <3,0,4,1> + 2568359222U, // <0,4,1,4>: Cost 3 vext1 <3,0,4,1>, RHS + 1812778294U, // <0,4,1,5>: Cost 2 vzipl LHS, RHS + 3022671158U, // <0,4,1,6>: Cost 3 vtrnl <0,4,1,5>, RHS + 2592248852U, // <0,4,1,7>: Cost 3 vext1 <7,0,4,1>, <7,0,4,1> + 1812778537U, // <0,4,1,u>: Cost 2 vzipl LHS, RHS + 2568364134U, // <0,4,2,0>: Cost 3 vext1 <3,0,4,2>, LHS + 2629887495U, // <0,4,2,1>: Cost 3 vext2 <2,1,0,4>, <2,1,0,4> + 3692349032U, // <0,4,2,2>: Cost 4 vext2 <0,2,0,4>, <2,2,2,2> + 2631214761U, // <0,4,2,3>: Cost 3 vext2 <2,3,0,4>, <2,3,0,4> + 2568367414U, // <0,4,2,4>: Cost 3 vext1 <3,0,4,2>, RHS + 2887028022U, // <0,4,2,5>: Cost 3 vzipl <0,2,0,2>, RHS + 1946996022U, // <0,4,2,6>: Cost 2 vtrnl LHS, RHS + 2592257045U, // <0,4,2,7>: Cost 3 vext1 <7,0,4,2>, <7,0,4,2> + 1946996040U, // <0,4,2,u>: Cost 2 vtrnl LHS, RHS + 3692349590U, // <0,4,3,0>: Cost 4 vext2 <0,2,0,4>, <3,0,1,2> + 3826878614U, // <0,4,3,1>: Cost 4 vuzpl <0,2,4,6>, <3,0,1,2> + 2228823753U, // <0,4,3,2>: Cost 3 vrev <2,3,4,0> + 3692349852U, // <0,4,3,3>: Cost 4 vext2 <0,2,0,4>, <3,3,3,3> + 3692349954U, // <0,4,3,4>: Cost 4 vext2 <0,2,0,4>, <3,4,5,6> + 3826878978U, // <0,4,3,5>: Cost 4 vuzpl <0,2,4,6>, <3,4,5,6> + 4095200566U, // <0,4,3,6>: Cost 4 vtrnl <0,2,3,1>, RHS + 3713583814U, // <0,4,3,7>: Cost 4 vext2 <3,7,0,4>, <3,7,0,4> + 2665720604U, // <0,4,3,u>: Cost 3 vext2 , <3,u,1,0> + 2550464552U, // <0,4,4,0>: Cost 3 vext1 <0,0,4,4>, <0,0,4,4> + 3962194914U, // <0,4,4,1>: Cost 4 vzipl <0,4,1,5>, <4,1,5,0> + 3693677631U, // <0,4,4,2>: Cost 4 vext2 <0,4,0,4>, <4,2,6,3> + 3642124467U, // <0,4,4,3>: Cost 4 vext1 <3,0,4,4>, <3,0,4,4> + 2718715088U, // <0,4,4,4>: Cost 3 vext3 <5,6,7,0>, <4,4,4,4> + 2618608950U, // <0,4,4,5>: Cost 3 vext2 <0,2,0,4>, RHS + 2753137974U, // <0,4,4,6>: Cost 3 vuzpl <0,2,4,6>, RHS + 3666015255U, // <0,4,4,7>: Cost 4 vext1 <7,0,4,4>, <7,0,4,4> + 2618609193U, // <0,4,4,u>: Cost 3 vext2 <0,2,0,4>, RHS + 2568388710U, // <0,4,5,0>: Cost 3 vext1 <3,0,4,5>, LHS + 2568389526U, // <0,4,5,1>: Cost 3 vext1 <3,0,4,5>, <1,2,3,0> + 3636159963U, // <0,4,5,2>: Cost 4 vext1 <2,0,4,5>, <2,0,4,5> + 2568390836U, // <0,4,5,3>: Cost 3 vext1 <3,0,4,5>, <3,0,4,5> + 2568391990U, // <0,4,5,4>: Cost 3 vext1 <3,0,4,5>, RHS + 2718715180U, // <0,4,5,5>: Cost 3 vext3 <5,6,7,0>, <4,5,5,6> + 1618136374U, // <0,4,5,6>: Cost 2 vext3 <1,2,3,0>, RHS + 2592281624U, // <0,4,5,7>: Cost 3 vext1 <7,0,4,5>, <7,0,4,5> + 1618136392U, // <0,4,5,u>: Cost 2 vext3 <1,2,3,0>, RHS + 2550480938U, // <0,4,6,0>: Cost 3 vext1 <0,0,4,6>, <0,0,4,6> + 3826880801U, // <0,4,6,1>: Cost 4 vuzpl <0,2,4,6>, <6,0,1,2> + 2712374620U, // <0,4,6,2>: Cost 3 vext3 <4,6,2,0>, <4,6,2,0> + 3777416551U, // <0,4,6,3>: Cost 4 vext3 <3,2,1,0>, <4,6,3,2> + 2718715252U, // <0,4,6,4>: Cost 3 vext3 <5,6,7,0>, <4,6,4,6> + 3826881165U, // <0,4,6,5>: Cost 4 vuzpl <0,2,4,6>, <6,4,5,6> + 2712669568U, // <0,4,6,6>: Cost 3 vext3 <4,6,6,0>, <4,6,6,0> + 2657760081U, // <0,4,6,7>: Cost 3 vext2 <6,7,0,4>, <6,7,0,4> + 2718715284U, // <0,4,6,u>: Cost 3 vext3 <5,6,7,0>, <4,6,u,2> + 3654090854U, // <0,4,7,0>: Cost 4 vext1 <5,0,4,7>, LHS + 3934229326U, // <0,4,7,1>: Cost 4 vuzpr <7,0,1,4>, <6,7,0,1> + 3734156437U, // <0,4,7,2>: Cost 4 vext2 <7,2,0,4>, <7,2,0,4> + 3734820070U, // <0,4,7,3>: Cost 4 vext2 <7,3,0,4>, <7,3,0,4> + 3654094134U, // <0,4,7,4>: Cost 4 vext1 <5,0,4,7>, RHS + 2713259464U, // <0,4,7,5>: Cost 3 vext3 <4,7,5,0>, <4,7,5,0> + 2255369073U, // <0,4,7,6>: Cost 3 vrev <6,7,4,0> + 3654095866U, // <0,4,7,7>: Cost 4 vext1 <5,0,4,7>, <7,0,1,2> + 2267314467U, // <0,4,7,u>: Cost 3 vrev + 2568413286U, // <0,4,u,0>: Cost 3 vext1 <3,0,4,u>, LHS + 2618611502U, // <0,4,u,1>: Cost 3 vext2 <0,2,0,4>, LHS + 2753140526U, // <0,4,u,2>: Cost 3 vuzpl <0,2,4,6>, LHS + 2568415415U, // <0,4,u,3>: Cost 3 vext1 <3,0,4,u>, <3,0,4,u> + 2568416566U, // <0,4,u,4>: Cost 3 vext1 <3,0,4,u>, RHS + 1817423158U, // <0,4,u,5>: Cost 2 vzipl LHS, RHS + 1947438390U, // <0,4,u,6>: Cost 2 vtrnl LHS, RHS + 2592306203U, // <0,4,u,7>: Cost 3 vext1 <7,0,4,u>, <7,0,4,u> + 1947438408U, // <0,4,u,u>: Cost 2 vtrnl LHS, RHS + 3630219264U, // <0,5,0,0>: Cost 4 vext1 <1,0,5,0>, <0,0,0,0> + 2637856870U, // <0,5,0,1>: Cost 3 vext2 <3,4,0,5>, LHS + 3692355748U, // <0,5,0,2>: Cost 4 vext2 <0,2,0,5>, <0,2,0,2> + 3693019384U, // <0,5,0,3>: Cost 4 vext2 <0,3,0,5>, <0,3,0,5> + 3630222646U, // <0,5,0,4>: Cost 4 vext1 <1,0,5,0>, RHS + 3910568116U, // <0,5,0,5>: Cost 4 vuzpr <3,0,4,5>, <3,0,4,5> + 2718715508U, // <0,5,0,6>: Cost 3 vext3 <5,6,7,0>, <5,0,6,1> + 3087011126U, // <0,5,0,7>: Cost 3 vtrnr <0,0,0,0>, RHS + 2637857437U, // <0,5,0,u>: Cost 3 vext2 <3,4,0,5>, LHS + 1500659814U, // <0,5,1,0>: Cost 2 vext1 <4,0,5,1>, LHS + 2886520528U, // <0,5,1,1>: Cost 3 vzipl LHS, <5,1,7,3> + 2574403176U, // <0,5,1,2>: Cost 3 vext1 <4,0,5,1>, <2,2,2,2> + 2574403734U, // <0,5,1,3>: Cost 3 vext1 <4,0,5,1>, <3,0,1,2> + 1500662674U, // <0,5,1,4>: Cost 2 vext1 <4,0,5,1>, <4,0,5,1> + 2886520836U, // <0,5,1,5>: Cost 3 vzipl LHS, <5,5,5,5> + 2886520930U, // <0,5,1,6>: Cost 3 vzipl LHS, <5,6,7,0> + 2718715600U, // <0,5,1,7>: Cost 3 vext3 <5,6,7,0>, <5,1,7,3> + 1500665646U, // <0,5,1,u>: Cost 2 vext1 <4,0,5,1>, LHS + 2556493926U, // <0,5,2,0>: Cost 3 vext1 <1,0,5,2>, LHS + 2556494600U, // <0,5,2,1>: Cost 3 vext1 <1,0,5,2>, <1,0,5,2> + 3692357256U, // <0,5,2,2>: Cost 4 vext2 <0,2,0,5>, <2,2,5,7> + 2568439994U, // <0,5,2,3>: Cost 3 vext1 <3,0,5,2>, <3,0,5,2> + 2556497206U, // <0,5,2,4>: Cost 3 vext1 <1,0,5,2>, RHS + 3020738564U, // <0,5,2,5>: Cost 3 vtrnl LHS, <5,5,5,5> + 4027877161U, // <0,5,2,6>: Cost 4 vzipr <0,2,0,2>, <2,4,5,6> + 3105017142U, // <0,5,2,7>: Cost 3 vtrnr <3,0,1,2>, RHS + 3105017143U, // <0,5,2,u>: Cost 3 vtrnr <3,0,1,2>, RHS + 2637858966U, // <0,5,3,0>: Cost 3 vext2 <3,4,0,5>, <3,0,1,2> + 3711600902U, // <0,5,3,1>: Cost 4 vext2 <3,4,0,5>, <3,1,4,6> + 3302639314U, // <0,5,3,2>: Cost 4 vrev <2,3,5,0> + 3308612011U, // <0,5,3,3>: Cost 4 vrev <3,3,5,0> + 2637859284U, // <0,5,3,4>: Cost 3 vext2 <3,4,0,5>, <3,4,0,5> + 3320557405U, // <0,5,3,5>: Cost 4 vrev <5,3,5,0> + 3790393190U, // <0,5,3,6>: Cost 4 vext3 <5,3,6,0>, <5,3,6,0> + 2716725103U, // <0,5,3,7>: Cost 3 vext3 <5,3,7,0>, <5,3,7,0> + 2640513816U, // <0,5,3,u>: Cost 3 vext2 <3,u,0,5>, <3,u,0,5> + 2661747602U, // <0,5,4,0>: Cost 3 vext2 <7,4,0,5>, <4,0,5,1> + 3962195634U, // <0,5,4,1>: Cost 4 vzipl <0,4,1,5>, <5,1,4,0> + 3303302947U, // <0,5,4,2>: Cost 4 vrev <2,4,5,0> + 2235533820U, // <0,5,4,3>: Cost 3 vrev <3,4,5,0> + 3962195892U, // <0,5,4,4>: Cost 4 vzipl <0,4,1,5>, <5,4,5,6> + 2637860150U, // <0,5,4,5>: Cost 3 vext2 <3,4,0,5>, RHS + 3791056823U, // <0,5,4,6>: Cost 4 vext3 <5,4,6,0>, <5,4,6,0> + 2259424608U, // <0,5,4,7>: Cost 3 vrev <7,4,5,0> + 2637860393U, // <0,5,4,u>: Cost 3 vext2 <3,4,0,5>, RHS + 3791278034U, // <0,5,5,0>: Cost 4 vext3 <5,5,0,0>, <5,5,0,0> + 3297993883U, // <0,5,5,1>: Cost 4 vrev <1,5,5,0> + 3303966580U, // <0,5,5,2>: Cost 4 vrev <2,5,5,0> + 3309939277U, // <0,5,5,3>: Cost 4 vrev <3,5,5,0> + 2242170150U, // <0,5,5,4>: Cost 3 vrev <4,5,5,0> + 2718715908U, // <0,5,5,5>: Cost 3 vext3 <5,6,7,0>, <5,5,5,5> + 2657767522U, // <0,5,5,6>: Cost 3 vext2 <6,7,0,5>, <5,6,7,0> + 2718715928U, // <0,5,5,7>: Cost 3 vext3 <5,6,7,0>, <5,5,7,7> + 2718715937U, // <0,5,5,u>: Cost 3 vext3 <5,6,7,0>, <5,5,u,7> + 2592358502U, // <0,5,6,0>: Cost 3 vext1 <7,0,5,6>, LHS + 3792457779U, // <0,5,6,1>: Cost 4 vext3 <5,6,7,0>, <5,6,1,7> + 3731509754U, // <0,5,6,2>: Cost 4 vext2 <6,7,0,5>, <6,2,7,3> + 3781398594U, // <0,5,6,3>: Cost 4 vext3 <3,u,1,0>, <5,6,3,4> + 2592361782U, // <0,5,6,4>: Cost 3 vext1 <7,0,5,6>, RHS + 2592362594U, // <0,5,6,5>: Cost 3 vext1 <7,0,5,6>, <5,6,7,0> + 3781398624U, // <0,5,6,6>: Cost 4 vext3 <3,u,1,0>, <5,6,6,7> + 1644974178U, // <0,5,6,7>: Cost 2 vext3 <5,6,7,0>, <5,6,7,0> + 1645047915U, // <0,5,6,u>: Cost 2 vext3 <5,6,u,0>, <5,6,u,0> + 2562506854U, // <0,5,7,0>: Cost 3 vext1 <2,0,5,7>, LHS + 2562507670U, // <0,5,7,1>: Cost 3 vext1 <2,0,5,7>, <1,2,3,0> + 2562508262U, // <0,5,7,2>: Cost 3 vext1 <2,0,5,7>, <2,0,5,7> + 3636250774U, // <0,5,7,3>: Cost 4 vext1 <2,0,5,7>, <3,0,1,2> + 2562510134U, // <0,5,7,4>: Cost 3 vext1 <2,0,5,7>, RHS + 2718716072U, // <0,5,7,5>: Cost 3 vext3 <5,6,7,0>, <5,7,5,7> + 2718716074U, // <0,5,7,6>: Cost 3 vext3 <5,6,7,0>, <5,7,6,0> + 2719379635U, // <0,5,7,7>: Cost 3 vext3 <5,7,7,0>, <5,7,7,0> + 2562512686U, // <0,5,7,u>: Cost 3 vext1 <2,0,5,7>, LHS + 1500717158U, // <0,5,u,0>: Cost 2 vext1 <4,0,5,u>, LHS + 2562515862U, // <0,5,u,1>: Cost 3 vext1 <2,0,5,u>, <1,2,3,0> + 2562516455U, // <0,5,u,2>: Cost 3 vext1 <2,0,5,u>, <2,0,5,u> + 2238188352U, // <0,5,u,3>: Cost 3 vrev <3,u,5,0> + 1500720025U, // <0,5,u,4>: Cost 2 vext1 <4,0,5,u>, <4,0,5,u> + 2637863066U, // <0,5,u,5>: Cost 3 vext2 <3,4,0,5>, RHS + 2586407243U, // <0,5,u,6>: Cost 3 vext1 <6,0,5,u>, <6,0,5,u> + 1646301444U, // <0,5,u,7>: Cost 2 vext3 <5,u,7,0>, <5,u,7,0> + 1646375181U, // <0,5,u,u>: Cost 2 vext3 <5,u,u,0>, <5,u,u,0> + 2586411110U, // <0,6,0,0>: Cost 3 vext1 <6,0,6,0>, LHS + 2619949158U, // <0,6,0,1>: Cost 3 vext2 <0,4,0,6>, LHS + 2619949220U, // <0,6,0,2>: Cost 3 vext2 <0,4,0,6>, <0,2,0,2> + 3785748789U, // <0,6,0,3>: Cost 4 vext3 <4,5,6,0>, <6,0,3,4> + 2619949386U, // <0,6,0,4>: Cost 3 vext2 <0,4,0,6>, <0,4,0,6> + 2586415202U, // <0,6,0,5>: Cost 3 vext1 <6,0,6,0>, <5,6,7,0> + 2586415436U, // <0,6,0,6>: Cost 3 vext1 <6,0,6,0>, <6,0,6,0> + 2952793398U, // <0,6,0,7>: Cost 3 vzipr <0,0,0,0>, RHS + 2619949725U, // <0,6,0,u>: Cost 3 vext2 <0,4,0,6>, LHS + 2562531430U, // <0,6,1,0>: Cost 3 vext1 <2,0,6,1>, LHS + 3693691700U, // <0,6,1,1>: Cost 4 vext2 <0,4,0,6>, <1,1,1,1> + 2886521338U, // <0,6,1,2>: Cost 3 vzipl LHS, <6,2,7,3> + 3693691864U, // <0,6,1,3>: Cost 4 vext2 <0,4,0,6>, <1,3,1,3> + 2562534710U, // <0,6,1,4>: Cost 3 vext1 <2,0,6,1>, RHS + 2580450932U, // <0,6,1,5>: Cost 3 vext1 <5,0,6,1>, <5,0,6,1> + 2886521656U, // <0,6,1,6>: Cost 3 vzipl LHS, <6,6,6,6> + 2966736182U, // <0,6,1,7>: Cost 3 vzipr <2,3,0,1>, RHS + 2966736183U, // <0,6,1,u>: Cost 3 vzipr <2,3,0,1>, RHS + 1500741734U, // <0,6,2,0>: Cost 2 vext1 <4,0,6,2>, LHS + 2574484276U, // <0,6,2,1>: Cost 3 vext1 <4,0,6,2>, <1,1,1,1> + 2574485096U, // <0,6,2,2>: Cost 3 vext1 <4,0,6,2>, <2,2,2,2> + 2631894694U, // <0,6,2,3>: Cost 3 vext2 <2,4,0,6>, <2,3,0,1> + 1500744604U, // <0,6,2,4>: Cost 2 vext1 <4,0,6,2>, <4,0,6,2> + 2574487248U, // <0,6,2,5>: Cost 3 vext1 <4,0,6,2>, <5,1,7,3> + 3020739384U, // <0,6,2,6>: Cost 3 vtrnl LHS, <6,6,6,6> + 2954136886U, // <0,6,2,7>: Cost 3 vzipr <0,2,0,2>, RHS + 1500747566U, // <0,6,2,u>: Cost 2 vext1 <4,0,6,2>, LHS + 3693693078U, // <0,6,3,0>: Cost 4 vext2 <0,4,0,6>, <3,0,1,2> + 3705637136U, // <0,6,3,1>: Cost 4 vext2 <2,4,0,6>, <3,1,5,7> + 3693693238U, // <0,6,3,2>: Cost 4 vext2 <0,4,0,6>, <3,2,1,0> + 3693693340U, // <0,6,3,3>: Cost 4 vext2 <0,4,0,6>, <3,3,3,3> + 2637867477U, // <0,6,3,4>: Cost 3 vext2 <3,4,0,6>, <3,4,0,6> + 3705637424U, // <0,6,3,5>: Cost 4 vext2 <2,4,0,6>, <3,5,1,7> + 3666154056U, // <0,6,3,6>: Cost 4 vext1 <7,0,6,3>, <6,3,7,0> + 2722697800U, // <0,6,3,7>: Cost 3 vext3 <6,3,7,0>, <6,3,7,0> + 2722771537U, // <0,6,3,u>: Cost 3 vext3 <6,3,u,0>, <6,3,u,0> + 2661755804U, // <0,6,4,0>: Cost 3 vext2 <7,4,0,6>, <4,0,6,2> + 4095316257U, // <0,6,4,1>: Cost 4 vtrnl <0,2,4,6>, <6,0,1,2> + 2229634860U, // <0,6,4,2>: Cost 3 vrev <2,4,6,0> + 3309349381U, // <0,6,4,3>: Cost 4 vrev <3,4,6,0> + 3636301110U, // <0,6,4,4>: Cost 4 vext1 <2,0,6,4>, RHS + 2619952438U, // <0,6,4,5>: Cost 3 vext2 <0,4,0,6>, RHS + 2253525648U, // <0,6,4,6>: Cost 3 vrev <6,4,6,0> + 4027895094U, // <0,6,4,7>: Cost 4 vzipr <0,2,0,4>, RHS + 2619952681U, // <0,6,4,u>: Cost 3 vext2 <0,4,0,6>, RHS + 2718716594U, // <0,6,5,0>: Cost 3 vext3 <5,6,7,0>, <6,5,0,7> + 3735498448U, // <0,6,5,1>: Cost 4 vext2 <7,4,0,6>, <5,1,7,3> + 3792458436U, // <0,6,5,2>: Cost 4 vext3 <5,6,7,0>, <6,5,2,7> + 3672140290U, // <0,6,5,3>: Cost 4 vext1 , <3,4,5,6> + 2242243887U, // <0,6,5,4>: Cost 3 vrev <4,5,6,0> + 3797619416U, // <0,6,5,5>: Cost 4 vext3 <6,5,5,0>, <6,5,5,0> + 3792458472U, // <0,6,5,6>: Cost 4 vext3 <5,6,7,0>, <6,5,6,7> + 3777417969U, // <0,6,5,7>: Cost 4 vext3 <3,2,1,0>, <6,5,7,7> + 2266134675U, // <0,6,5,u>: Cost 3 vrev + 3786412796U, // <0,6,6,0>: Cost 4 vext3 <4,6,6,0>, <6,6,0,0> + 3792458504U, // <0,6,6,1>: Cost 4 vext3 <5,6,7,0>, <6,6,1,3> + 3304703950U, // <0,6,6,2>: Cost 4 vrev <2,6,6,0> + 3798135575U, // <0,6,6,3>: Cost 4 vext3 <6,6,3,0>, <6,6,3,0> + 2242907520U, // <0,6,6,4>: Cost 3 vrev <4,6,6,0> + 3322622041U, // <0,6,6,5>: Cost 4 vrev <5,6,6,0> + 2718716728U, // <0,6,6,6>: Cost 3 vext3 <5,6,7,0>, <6,6,6,6> + 2718716738U, // <0,6,6,7>: Cost 3 vext3 <5,6,7,0>, <6,6,7,7> + 2718716747U, // <0,6,6,u>: Cost 3 vext3 <5,6,7,0>, <6,6,u,7> + 2718716750U, // <0,6,7,0>: Cost 3 vext3 <5,6,7,0>, <6,7,0,1> + 2691879768U, // <0,6,7,1>: Cost 3 vext3 <1,2,3,0>, <6,7,1,2> + 3636323823U, // <0,6,7,2>: Cost 4 vext1 <2,0,6,7>, <2,0,6,7> + 2725057384U, // <0,6,7,3>: Cost 3 vext3 <6,7,3,0>, <6,7,3,0> + 2718716790U, // <0,6,7,4>: Cost 3 vext3 <5,6,7,0>, <6,7,4,5> + 2718716800U, // <0,6,7,5>: Cost 3 vext3 <5,6,7,0>, <6,7,5,6> + 3777418122U, // <0,6,7,6>: Cost 4 vext3 <3,2,1,0>, <6,7,6,7> + 2725352332U, // <0,6,7,7>: Cost 3 vext3 <6,7,7,0>, <6,7,7,0> + 2718716822U, // <0,6,7,u>: Cost 3 vext3 <5,6,7,0>, <6,7,u,1> + 1500790886U, // <0,6,u,0>: Cost 2 vext1 <4,0,6,u>, LHS + 2619954990U, // <0,6,u,1>: Cost 3 vext2 <0,4,0,6>, LHS + 2232289392U, // <0,6,u,2>: Cost 3 vrev <2,u,6,0> + 2725721017U, // <0,6,u,3>: Cost 3 vext3 <6,u,3,0>, <6,u,3,0> + 1500793762U, // <0,6,u,4>: Cost 2 vext1 <4,0,6,u>, <4,0,6,u> + 2619955354U, // <0,6,u,5>: Cost 3 vext2 <0,4,0,6>, RHS + 2256180180U, // <0,6,u,6>: Cost 3 vrev <6,u,6,0> + 2954186038U, // <0,6,u,7>: Cost 3 vzipr <0,2,0,u>, RHS + 1500796718U, // <0,6,u,u>: Cost 2 vext1 <4,0,6,u>, LHS + 2726163439U, // <0,7,0,0>: Cost 3 vext3 <7,0,0,0>, <7,0,0,0> + 2632564838U, // <0,7,0,1>: Cost 3 vext2 <2,5,0,7>, LHS + 2726310913U, // <0,7,0,2>: Cost 3 vext3 <7,0,2,0>, <7,0,2,0> + 3700998396U, // <0,7,0,3>: Cost 4 vext2 <1,6,0,7>, <0,3,1,0> + 2718716952U, // <0,7,0,4>: Cost 3 vext3 <5,6,7,0>, <7,0,4,5> + 2718716962U, // <0,7,0,5>: Cost 3 vext3 <5,6,7,0>, <7,0,5,6> + 2621284845U, // <0,7,0,6>: Cost 3 vext2 <0,6,0,7>, <0,6,0,7> + 3904685542U, // <0,7,0,7>: Cost 4 vuzpr <2,0,5,7>, <2,0,5,7> + 2632565405U, // <0,7,0,u>: Cost 3 vext2 <2,5,0,7>, LHS + 2886521850U, // <0,7,1,0>: Cost 3 vzipl LHS, <7,0,1,2> + 3700335474U, // <0,7,1,1>: Cost 4 vext2 <1,5,0,7>, <1,1,u,0> + 2632565654U, // <0,7,1,2>: Cost 3 vext2 <2,5,0,7>, <1,2,3,0> + 3769603168U, // <0,7,1,3>: Cost 4 vext3 <1,u,3,0>, <7,1,3,5> + 2886522214U, // <0,7,1,4>: Cost 3 vzipl LHS, <7,4,5,6> + 3700335733U, // <0,7,1,5>: Cost 4 vext2 <1,5,0,7>, <1,5,0,7> + 2886522374U, // <0,7,1,6>: Cost 3 vzipl LHS, <7,6,5,4> + 2886522476U, // <0,7,1,7>: Cost 3 vzipl LHS, <7,7,7,7> + 2668397948U, // <0,7,1,u>: Cost 3 vext2 , <1,u,3,0> + 2586501222U, // <0,7,2,0>: Cost 3 vext1 <6,0,7,2>, LHS + 3020739578U, // <0,7,2,1>: Cost 3 vtrnl LHS, <7,0,1,2> + 3636356595U, // <0,7,2,2>: Cost 4 vext1 <2,0,7,2>, <2,0,7,2> + 2727711916U, // <0,7,2,3>: Cost 3 vext3 <7,2,3,0>, <7,2,3,0> + 2586504502U, // <0,7,2,4>: Cost 3 vext1 <6,0,7,2>, RHS + 2632566606U, // <0,7,2,5>: Cost 3 vext2 <2,5,0,7>, <2,5,0,7> + 2586505559U, // <0,7,2,6>: Cost 3 vext1 <6,0,7,2>, <6,0,7,2> + 3020740204U, // <0,7,2,7>: Cost 3 vtrnl LHS, <7,7,7,7> + 2634557505U, // <0,7,2,u>: Cost 3 vext2 <2,u,0,7>, <2,u,0,7> + 3701000342U, // <0,7,3,0>: Cost 4 vext2 <1,6,0,7>, <3,0,1,2> + 3706308849U, // <0,7,3,1>: Cost 4 vext2 <2,5,0,7>, <3,1,2,3> + 2627258678U, // <0,7,3,2>: Cost 3 vext2 <1,6,0,7>, <3,2,1,0> + 3706309020U, // <0,7,3,3>: Cost 4 vext2 <2,5,0,7>, <3,3,3,3> + 3706309122U, // <0,7,3,4>: Cost 4 vext2 <2,5,0,7>, <3,4,5,6> + 2246963055U, // <0,7,3,5>: Cost 3 vrev <5,3,7,0> + 2639202936U, // <0,7,3,6>: Cost 3 vext2 <3,6,0,7>, <3,6,0,7> + 3332650273U, // <0,7,3,7>: Cost 4 vrev <7,3,7,0> + 2640530202U, // <0,7,3,u>: Cost 3 vext2 <3,u,0,7>, <3,u,0,7> + 3654287462U, // <0,7,4,0>: Cost 4 vext1 <5,0,7,4>, LHS + 3654288278U, // <0,7,4,1>: Cost 4 vext1 <5,0,7,4>, <1,2,3,0> + 3654289230U, // <0,7,4,2>: Cost 4 vext1 <5,0,7,4>, <2,5,0,7> + 3660262008U, // <0,7,4,3>: Cost 4 vext1 <6,0,7,4>, <3,6,0,7> + 3786413405U, // <0,7,4,4>: Cost 4 vext3 <4,6,6,0>, <7,4,4,6> + 2632568118U, // <0,7,4,5>: Cost 3 vext2 <2,5,0,7>, RHS + 3718917457U, // <0,7,4,6>: Cost 4 vext2 <4,6,0,7>, <4,6,0,7> + 3787003255U, // <0,7,4,7>: Cost 4 vext3 <4,7,5,0>, <7,4,7,5> + 2632568361U, // <0,7,4,u>: Cost 3 vext2 <2,5,0,7>, RHS + 3706310268U, // <0,7,5,0>: Cost 4 vext2 <2,5,0,7>, <5,0,7,0> + 3298141357U, // <0,7,5,1>: Cost 4 vrev <1,5,7,0> + 3304114054U, // <0,7,5,2>: Cost 4 vrev <2,5,7,0> + 2236344927U, // <0,7,5,3>: Cost 3 vrev <3,5,7,0> + 3316059448U, // <0,7,5,4>: Cost 4 vrev <4,5,7,0> + 3724226521U, // <0,7,5,5>: Cost 4 vext2 <5,5,0,7>, <5,5,0,7> + 2718717377U, // <0,7,5,6>: Cost 3 vext3 <5,6,7,0>, <7,5,6,7> + 2260235715U, // <0,7,5,7>: Cost 3 vrev <7,5,7,0> + 2720044499U, // <0,7,5,u>: Cost 3 vext3 <5,u,7,0>, <7,5,u,7> + 2598477926U, // <0,7,6,0>: Cost 3 vext1 , LHS + 2556674846U, // <0,7,6,1>: Cost 3 vext1 <1,0,7,6>, <1,0,7,6> + 3792459246U, // <0,7,6,2>: Cost 4 vext3 <5,6,7,0>, <7,6,2,7> + 2237008560U, // <0,7,6,3>: Cost 3 vrev <3,6,7,0> + 2598481206U, // <0,7,6,4>: Cost 3 vext1 , RHS + 1175212130U, // <0,7,6,5>: Cost 2 vrev <5,6,7,0> + 2598482773U, // <0,7,6,6>: Cost 3 vext1 , <6,7,0,u> + 2260899348U, // <0,7,6,7>: Cost 3 vrev <7,6,7,0> + 1193130221U, // <0,7,6,u>: Cost 2 vrev + 2665747456U, // <0,7,7,0>: Cost 3 vext2 , <7,0,1,u> + 3654312854U, // <0,7,7,1>: Cost 4 vext1 <5,0,7,7>, <1,2,3,0> + 3654313446U, // <0,7,7,2>: Cost 4 vext1 <5,0,7,7>, <2,0,5,7> + 3311414017U, // <0,7,7,3>: Cost 4 vrev <3,7,7,0> + 3654315318U, // <0,7,7,4>: Cost 4 vext1 <5,0,7,7>, RHS + 2249617587U, // <0,7,7,5>: Cost 3 vrev <5,7,7,0> + 2255590284U, // <0,7,7,6>: Cost 3 vrev <6,7,7,0> + 2718717548U, // <0,7,7,7>: Cost 3 vext3 <5,6,7,0>, <7,7,7,7> + 2664420990U, // <0,7,7,u>: Cost 3 vext2 <7,u,0,7>, <7,u,0,7> + 2726163439U, // <0,7,u,0>: Cost 3 vext3 <7,0,0,0>, <7,0,0,0> + 2632570670U, // <0,7,u,1>: Cost 3 vext2 <2,5,0,7>, LHS + 2733536906U, // <0,7,u,2>: Cost 3 vext3 , <7,u,2,1> + 2238335826U, // <0,7,u,3>: Cost 3 vrev <3,u,7,0> + 2718716952U, // <0,7,u,4>: Cost 3 vext3 <5,6,7,0>, <7,0,4,5> + 1176539396U, // <0,7,u,5>: Cost 2 vrev <5,u,7,0> + 2256253917U, // <0,7,u,6>: Cost 3 vrev <6,u,7,0> + 2262226614U, // <0,7,u,7>: Cost 3 vrev <7,u,7,0> + 1194457487U, // <0,7,u,u>: Cost 2 vrev + 135053414U, // <0,u,0,0>: Cost 1 vdup0 LHS + 1544896614U, // <0,u,0,1>: Cost 2 vext2 <0,2,0,u>, LHS + 1678999654U, // <0,u,0,2>: Cost 2 vuzpl LHS, LHS + 2233100499U, // <0,u,0,3>: Cost 3 vrev <3,0,u,0> + 1476988214U, // <0,u,0,4>: Cost 2 vext1 <0,0,u,0>, RHS + 2718791419U, // <0,u,0,5>: Cost 3 vext3 <5,6,u,0>, + 3021248666U, // <0,u,0,6>: Cost 3 vtrnl <0,2,0,2>, RHS + 2256991287U, // <0,u,0,7>: Cost 3 vrev <7,0,u,0> + 135053414U, // <0,u,0,u>: Cost 1 vdup0 LHS + 1476993097U, // <0,u,1,0>: Cost 2 vext1 <0,0,u,1>, <0,0,u,1> + 1812780846U, // <0,u,1,1>: Cost 2 vzipl LHS, LHS + 1618138926U, // <0,u,1,2>: Cost 2 vext3 <1,2,3,0>, LHS + 2752742216U, // <0,u,1,3>: Cost 3 vuzpl LHS, <1,1,3,3> + 1476996406U, // <0,u,1,4>: Cost 2 vext1 <0,0,u,1>, RHS + 1812781210U, // <0,u,1,5>: Cost 2 vzipl LHS, RHS + 2887006416U, // <0,u,1,6>: Cost 3 vzipl LHS, + 2966736200U, // <0,u,1,7>: Cost 3 vzipr <2,3,0,1>, RHS + 1812781413U, // <0,u,1,u>: Cost 2 vzipl LHS, LHS + 1494917222U, // <0,u,2,0>: Cost 2 vext1 <3,0,u,2>, LHS + 1148740547U, // <0,u,2,1>: Cost 2 vrev <1,2,u,0> + 1946998574U, // <0,u,2,2>: Cost 2 vtrnl LHS, LHS + 835584U, // <0,u,2,3>: Cost 0 copy LHS + 1494920502U, // <0,u,2,4>: Cost 2 vext1 <3,0,u,2>, RHS + 3020781631U, // <0,u,2,5>: Cost 3 vtrnl LHS, + 1946998938U, // <0,u,2,6>: Cost 2 vtrnl LHS, RHS + 1518810169U, // <0,u,2,7>: Cost 2 vext1 <7,0,u,2>, <7,0,u,2> + 835584U, // <0,u,2,u>: Cost 0 copy LHS + 2618640534U, // <0,u,3,0>: Cost 3 vext2 <0,2,0,u>, <3,0,1,2> + 2752743574U, // <0,u,3,1>: Cost 3 vuzpl LHS, <3,0,1,2> + 2618640694U, // <0,u,3,2>: Cost 3 vext2 <0,2,0,u>, <3,2,1,0> + 2752743836U, // <0,u,3,3>: Cost 3 vuzpl LHS, <3,3,3,3> + 2618640898U, // <0,u,3,4>: Cost 3 vext2 <0,2,0,u>, <3,4,5,6> + 2752743938U, // <0,u,3,5>: Cost 3 vuzpl LHS, <3,4,5,6> + 2253009489U, // <0,u,3,6>: Cost 3 vrev <6,3,u,0> + 2639874762U, // <0,u,3,7>: Cost 3 vext2 <3,7,0,u>, <3,7,0,u> + 2752743637U, // <0,u,3,u>: Cost 3 vuzpl LHS, <3,0,u,2> + 2562703462U, // <0,u,4,0>: Cost 3 vext1 <2,0,u,4>, LHS + 2888455982U, // <0,u,4,1>: Cost 3 vzipl <0,4,1,5>, LHS + 3021575982U, // <0,u,4,2>: Cost 3 vtrnl <0,2,4,6>, LHS + 2568677591U, // <0,u,4,3>: Cost 3 vext1 <3,0,u,4>, <3,0,u,4> + 2562706742U, // <0,u,4,4>: Cost 3 vext1 <2,0,u,4>, RHS + 1544899894U, // <0,u,4,5>: Cost 2 vext2 <0,2,0,u>, RHS + 1679002934U, // <0,u,4,6>: Cost 2 vuzpl LHS, RHS + 2592568379U, // <0,u,4,7>: Cost 3 vext1 <7,0,u,4>, <7,0,u,4> + 1679002952U, // <0,u,4,u>: Cost 2 vuzpl LHS, RHS + 2568683622U, // <0,u,5,0>: Cost 3 vext1 <3,0,u,5>, LHS + 2568684438U, // <0,u,5,1>: Cost 3 vext1 <3,0,u,5>, <1,2,3,0> + 3765622902U, // <0,u,5,2>: Cost 4 vext3 <1,2,3,0>, + 2691881087U, // <0,u,5,3>: Cost 3 vext3 <1,2,3,0>, + 2568686902U, // <0,u,5,4>: Cost 3 vext1 <3,0,u,5>, RHS + 2650492890U, // <0,u,5,5>: Cost 3 vext2 <5,5,0,u>, <5,5,0,u> + 1618139290U, // <0,u,5,6>: Cost 2 vext3 <1,2,3,0>, RHS + 2836630838U, // <0,u,5,7>: Cost 3 vuzpr <3,0,1,u>, RHS + 1618139308U, // <0,u,5,u>: Cost 2 vext3 <1,2,3,0>, RHS + 2592579686U, // <0,u,6,0>: Cost 3 vext1 <7,0,u,6>, LHS + 2653770090U, // <0,u,6,1>: Cost 3 vext2 <6,1,0,3>, <6,1,0,3> + 2654474688U, // <0,u,6,2>: Cost 3 vext2 <6,2,0,u>, <6,2,0,u> + 2691881168U, // <0,u,6,3>: Cost 3 vext3 <1,2,3,0>, + 2592582966U, // <0,u,6,4>: Cost 3 vext1 <7,0,u,6>, RHS + 1175285867U, // <0,u,6,5>: Cost 2 vrev <5,6,u,0> + 2657129220U, // <0,u,6,6>: Cost 3 vext2 <6,6,0,u>, <6,6,0,u> + 1584051029U, // <0,u,6,7>: Cost 2 vext2 <6,7,0,u>, <6,7,0,u> + 1584714662U, // <0,u,6,u>: Cost 2 vext2 <6,u,0,u>, <6,u,0,u> + 2562728038U, // <0,u,7,0>: Cost 3 vext1 <2,0,u,7>, LHS + 2562728854U, // <0,u,7,1>: Cost 3 vext1 <2,0,u,7>, <1,2,3,0> + 2562729473U, // <0,u,7,2>: Cost 3 vext1 <2,0,u,7>, <2,0,u,7> + 2661111018U, // <0,u,7,3>: Cost 3 vext2 <7,3,0,u>, <7,3,0,u> + 2562731318U, // <0,u,7,4>: Cost 3 vext1 <2,0,u,7>, RHS + 2718718258U, // <0,u,7,5>: Cost 3 vext3 <5,6,7,0>, + 2586620261U, // <0,u,7,6>: Cost 3 vext1 <6,0,u,7>, <6,0,u,7> + 2657793644U, // <0,u,7,7>: Cost 3 vext2 <6,7,0,u>, <7,7,7,7> + 2562733870U, // <0,u,7,u>: Cost 3 vext1 <2,0,u,7>, LHS + 135053414U, // <0,u,u,0>: Cost 1 vdup0 LHS + 1544902446U, // <0,u,u,1>: Cost 2 vext2 <0,2,0,u>, LHS + 1679005486U, // <0,u,u,2>: Cost 2 vuzpl LHS, LHS + 835584U, // <0,u,u,3>: Cost 0 copy LHS + 1494969654U, // <0,u,u,4>: Cost 2 vext1 <3,0,u,u>, RHS + 1544902810U, // <0,u,u,5>: Cost 2 vext2 <0,2,0,u>, RHS + 1679005850U, // <0,u,u,6>: Cost 2 vuzpl LHS, RHS + 1518859327U, // <0,u,u,7>: Cost 2 vext1 <7,0,u,u>, <7,0,u,u> + 835584U, // <0,u,u,u>: Cost 0 copy LHS + 2689744896U, // <1,0,0,0>: Cost 3 vext3 <0,u,1,1>, <0,0,0,0> + 1562820710U, // <1,0,0,1>: Cost 2 vext2 <3,2,1,0>, LHS + 2689744916U, // <1,0,0,2>: Cost 3 vext3 <0,u,1,1>, <0,0,2,2> + 2619310332U, // <1,0,0,3>: Cost 3 vext2 <0,3,1,0>, <0,3,1,0> + 2636562770U, // <1,0,0,4>: Cost 3 vext2 <3,2,1,0>, <0,4,1,5> + 2620637598U, // <1,0,0,5>: Cost 3 vext2 <0,5,1,0>, <0,5,1,0> + 3708977654U, // <1,0,0,6>: Cost 4 vext2 <3,0,1,0>, <0,6,1,7> + 2256409584U, // <1,0,0,7>: Cost 3 vrev <7,0,0,1> + 1562821277U, // <1,0,0,u>: Cost 2 vext2 <3,2,1,0>, LHS + 2556780646U, // <1,0,1,0>: Cost 3 vext1 <1,1,0,1>, LHS + 2221237035U, // <1,0,1,1>: Cost 3 vrev <1,1,0,1> + 1616003174U, // <1,0,1,2>: Cost 2 vext3 <0,u,1,1>, LHS + 2636563416U, // <1,0,1,3>: Cost 3 vext2 <3,2,1,0>, <1,3,1,3> + 2556783926U, // <1,0,1,4>: Cost 3 vext1 <1,1,0,1>, RHS + 2636563600U, // <1,0,1,5>: Cost 3 vext2 <3,2,1,0>, <1,5,3,7> + 2724839566U, // <1,0,1,6>: Cost 3 vext3 <6,7,0,1>, <0,1,6,7> + 3654415354U, // <1,0,1,7>: Cost 4 vext1 <5,1,0,1>, <7,0,1,2> + 1616003228U, // <1,0,1,u>: Cost 2 vext3 <0,u,1,1>, LHS + 2685690019U, // <1,0,2,0>: Cost 3 vext3 <0,2,0,1>, <0,2,0,1> + 2685763756U, // <1,0,2,1>: Cost 3 vext3 <0,2,1,1>, <0,2,1,1> + 2227873365U, // <1,0,2,2>: Cost 3 vrev <2,2,0,1> + 2685911230U, // <1,0,2,3>: Cost 3 vext3 <0,2,3,1>, <0,2,3,1> + 2689745100U, // <1,0,2,4>: Cost 3 vext3 <0,u,1,1>, <0,2,4,6> + 4044540372U, // <1,0,2,5>: Cost 4 vzipr <3,0,1,2>, <3,4,0,5> + 2636564410U, // <1,0,2,6>: Cost 3 vext2 <3,2,1,0>, <2,6,3,7> + 2592625658U, // <1,0,2,7>: Cost 3 vext1 <7,1,0,2>, <7,0,1,2> + 2686279915U, // <1,0,2,u>: Cost 3 vext3 <0,2,u,1>, <0,2,u,1> + 3087843328U, // <1,0,3,0>: Cost 3 vtrnr LHS, <0,0,0,0> + 3087843338U, // <1,0,3,1>: Cost 3 vtrnr LHS, <0,0,1,1> + 1154795174U, // <1,0,3,2>: Cost 2 vrev <2,3,0,1> + 2636564881U, // <1,0,3,3>: Cost 3 vext2 <3,2,1,0>, <3,3,2,1> + 2636564994U, // <1,0,3,4>: Cost 3 vext2 <3,2,1,0>, <3,4,5,6> + 2586660962U, // <1,0,3,5>: Cost 3 vext1 <6,1,0,3>, <5,6,7,0> + 2586661226U, // <1,0,3,6>: Cost 3 vext1 <6,1,0,3>, <6,1,0,3> + 2258400483U, // <1,0,3,7>: Cost 3 vrev <7,3,0,1> + 1566804764U, // <1,0,3,u>: Cost 2 vext2 <3,u,1,0>, <3,u,1,0> + 2598608998U, // <1,0,4,0>: Cost 3 vext1 , LHS + 2689745234U, // <1,0,4,1>: Cost 3 vext3 <0,u,1,1>, <0,4,1,5> + 2689745244U, // <1,0,4,2>: Cost 3 vext3 <0,u,1,1>, <0,4,2,6> + 2235173328U, // <1,0,4,3>: Cost 3 vrev <3,4,0,1> + 2598612278U, // <1,0,4,4>: Cost 3 vext1 , RHS + 1562823990U, // <1,0,4,5>: Cost 2 vext2 <3,2,1,0>, RHS + 2666425716U, // <1,0,4,6>: Cost 3 vext2 , <4,6,4,6> + 2259064116U, // <1,0,4,7>: Cost 3 vrev <7,4,0,1> + 1562824233U, // <1,0,4,u>: Cost 2 vext2 <3,2,1,0>, RHS + 4029300736U, // <1,0,5,0>: Cost 4 vzipr <0,4,1,5>, <0,0,0,0> + 2223891567U, // <1,0,5,1>: Cost 3 vrev <1,5,0,1> + 3028287590U, // <1,0,5,2>: Cost 3 vtrnl <1,3,5,7>, LHS + 3710308163U, // <1,0,5,3>: Cost 4 vext2 <3,2,1,0>, <5,3,2,1> + 2241809658U, // <1,0,5,4>: Cost 3 vrev <4,5,0,1> + 2247782355U, // <1,0,5,5>: Cost 3 vrev <5,5,0,1> + 2666426466U, // <1,0,5,6>: Cost 3 vext2 , <5,6,7,0> + 2666426536U, // <1,0,5,7>: Cost 3 vext2 , <5,7,5,7> + 3028287644U, // <1,0,5,u>: Cost 3 vtrnl <1,3,5,7>, LHS + 3292324327U, // <1,0,6,0>: Cost 4 vrev <0,6,0,1> + 2698297846U, // <1,0,6,1>: Cost 3 vext3 <2,3,0,1>, <0,6,1,7> + 2230527897U, // <1,0,6,2>: Cost 3 vrev <2,6,0,1> + 3642509538U, // <1,0,6,3>: Cost 4 vext1 <3,1,0,6>, <3,1,0,6> + 2242473291U, // <1,0,6,4>: Cost 3 vrev <4,6,0,1> + 2248445988U, // <1,0,6,5>: Cost 3 vrev <5,6,0,1> + 2254418685U, // <1,0,6,6>: Cost 3 vrev <6,6,0,1> + 2659128142U, // <1,0,6,7>: Cost 3 vext2 <7,0,1,0>, <6,7,0,1> + 2666427295U, // <1,0,6,u>: Cost 3 vext2 , <6,u,0,1> + 2659128312U, // <1,0,7,0>: Cost 3 vext2 <7,0,1,0>, <7,0,1,0> + 3298960657U, // <1,0,7,1>: Cost 4 vrev <1,7,0,1> + 2689155658U, // <1,0,7,2>: Cost 3 vext3 <0,7,2,1>, <0,7,2,1> + 2237164227U, // <1,0,7,3>: Cost 3 vrev <3,7,0,1> + 2598636854U, // <1,0,7,4>: Cost 3 vext1 , RHS + 2249109621U, // <1,0,7,5>: Cost 3 vrev <5,7,0,1> + 1181340494U, // <1,0,7,6>: Cost 2 vrev <6,7,0,1> + 2261055015U, // <1,0,7,7>: Cost 3 vrev <7,7,0,1> + 1193285888U, // <1,0,7,u>: Cost 2 vrev + 3087884288U, // <1,0,u,0>: Cost 3 vtrnr LHS, <0,0,0,0> + 1616003730U, // <1,0,u,1>: Cost 2 vext3 <0,u,1,1>, <0,u,1,1> + 1616003741U, // <1,0,u,2>: Cost 2 vext3 <0,u,1,1>, LHS + 2689893028U, // <1,0,u,3>: Cost 3 vext3 <0,u,3,1>, <0,u,3,1> + 2689745586U, // <1,0,u,4>: Cost 3 vext3 <0,u,1,1>, <0,u,4,6> + 1562826906U, // <1,0,u,5>: Cost 2 vext2 <3,2,1,0>, RHS + 1182004127U, // <1,0,u,6>: Cost 2 vrev <6,u,0,1> + 2261718648U, // <1,0,u,7>: Cost 3 vrev <7,u,0,1> + 1616003795U, // <1,0,u,u>: Cost 2 vext3 <0,u,1,1>, LHS + 1543585802U, // <1,1,0,0>: Cost 2 vext2 <0,0,1,1>, <0,0,1,1> + 1548894310U, // <1,1,0,1>: Cost 2 vext2 <0,u,1,1>, LHS + 2618654892U, // <1,1,0,2>: Cost 3 vext2 <0,2,1,1>, <0,2,1,1> + 2690556661U, // <1,1,0,3>: Cost 3 vext3 <1,0,3,1>, <1,0,3,1> + 2622636370U, // <1,1,0,4>: Cost 3 vext2 <0,u,1,1>, <0,4,1,5> + 2620645791U, // <1,1,0,5>: Cost 3 vext2 <0,5,1,1>, <0,5,1,1> + 3696378367U, // <1,1,0,6>: Cost 4 vext2 <0,u,1,1>, <0,6,2,7> + 2724840222U, // <1,1,0,7>: Cost 3 vext3 <6,7,0,1>, <1,0,7,6> + 1548894866U, // <1,1,0,u>: Cost 2 vext2 <0,u,1,1>, <0,u,1,1> + 1483112550U, // <1,1,1,0>: Cost 2 vext1 <1,1,1,1>, LHS + 202162278U, // <1,1,1,1>: Cost 1 vdup1 LHS + 2622636950U, // <1,1,1,2>: Cost 3 vext2 <0,u,1,1>, <1,2,3,0> + 2622637016U, // <1,1,1,3>: Cost 3 vext2 <0,u,1,1>, <1,3,1,3> + 1483115830U, // <1,1,1,4>: Cost 2 vext1 <1,1,1,1>, RHS + 2622637200U, // <1,1,1,5>: Cost 3 vext2 <0,u,1,1>, <1,5,3,7> + 2622637263U, // <1,1,1,6>: Cost 3 vext2 <0,u,1,1>, <1,6,1,7> + 2257146954U, // <1,1,1,7>: Cost 3 vrev <7,1,1,1> + 202162278U, // <1,1,1,u>: Cost 1 vdup1 LHS + 2550890588U, // <1,1,2,0>: Cost 3 vext1 <0,1,1,2>, <0,1,1,2> + 2617329183U, // <1,1,2,1>: Cost 3 vext2 <0,0,1,1>, <2,1,3,1> + 2622637672U, // <1,1,2,2>: Cost 3 vext2 <0,u,1,1>, <2,2,2,2> + 2622637734U, // <1,1,2,3>: Cost 3 vext2 <0,u,1,1>, <2,3,0,1> + 2550893878U, // <1,1,2,4>: Cost 3 vext1 <0,1,1,2>, RHS + 3696379744U, // <1,1,2,5>: Cost 4 vext2 <0,u,1,1>, <2,5,2,7> + 2622638010U, // <1,1,2,6>: Cost 3 vext2 <0,u,1,1>, <2,6,3,7> + 3804554170U, // <1,1,2,7>: Cost 4 vext3 <7,7,0,1>, <1,2,7,0> + 2622638139U, // <1,1,2,u>: Cost 3 vext2 <0,u,1,1>, <2,u,0,1> + 2622638230U, // <1,1,3,0>: Cost 3 vext2 <0,u,1,1>, <3,0,1,2> + 3087844148U, // <1,1,3,1>: Cost 3 vtrnr LHS, <1,1,1,1> + 2622638390U, // <1,1,3,2>: Cost 3 vext2 <0,u,1,1>, <3,2,1,0> + 2014101606U, // <1,1,3,3>: Cost 2 vtrnr LHS, LHS + 2622638594U, // <1,1,3,4>: Cost 3 vext2 <0,u,1,1>, <3,4,5,6> + 2689745920U, // <1,1,3,5>: Cost 3 vext3 <0,u,1,1>, <1,3,5,7> + 3763487753U, // <1,1,3,6>: Cost 4 vext3 <0,u,1,1>, <1,3,6,7> + 2592707660U, // <1,1,3,7>: Cost 3 vext1 <7,1,1,3>, <7,1,1,3> + 2014101611U, // <1,1,3,u>: Cost 2 vtrnr LHS, LHS + 2556878950U, // <1,1,4,0>: Cost 3 vext1 <1,1,1,4>, LHS + 2556879671U, // <1,1,4,1>: Cost 3 vext1 <1,1,1,4>, <1,1,1,4> + 3696380988U, // <1,1,4,2>: Cost 4 vext2 <0,u,1,1>, <4,2,6,0> + 3763487805U, // <1,1,4,3>: Cost 4 vext3 <0,u,1,1>, <1,4,3,5> + 2556882230U, // <1,1,4,4>: Cost 3 vext1 <1,1,1,4>, RHS + 1548897590U, // <1,1,4,5>: Cost 2 vext2 <0,u,1,1>, RHS + 2758184246U, // <1,1,4,6>: Cost 3 vuzpl <1,1,1,1>, RHS + 3666457677U, // <1,1,4,7>: Cost 4 vext1 <7,1,1,4>, <7,1,1,4> + 1548897833U, // <1,1,4,u>: Cost 2 vext2 <0,u,1,1>, RHS + 2693653615U, // <1,1,5,0>: Cost 3 vext3 <1,5,0,1>, <1,5,0,1> + 2617331408U, // <1,1,5,1>: Cost 3 vext2 <0,0,1,1>, <5,1,7,3> + 4029302934U, // <1,1,5,2>: Cost 4 vzipr <0,4,1,5>, <3,0,1,2> + 2689746064U, // <1,1,5,3>: Cost 3 vext3 <0,u,1,1>, <1,5,3,7> + 2550918454U, // <1,1,5,4>: Cost 3 vext1 <0,1,1,5>, RHS + 2955559250U, // <1,1,5,5>: Cost 3 vzipr <0,4,1,5>, <0,4,1,5> + 2617331810U, // <1,1,5,6>: Cost 3 vext2 <0,0,1,1>, <5,6,7,0> + 2825293110U, // <1,1,5,7>: Cost 3 vuzpr <1,1,1,1>, RHS + 2689746109U, // <1,1,5,u>: Cost 3 vext3 <0,u,1,1>, <1,5,u,7> + 3696382241U, // <1,1,6,0>: Cost 4 vext2 <0,u,1,1>, <6,0,1,2> + 2689746127U, // <1,1,6,1>: Cost 3 vext3 <0,u,1,1>, <1,6,1,7> + 2617332218U, // <1,1,6,2>: Cost 3 vext2 <0,0,1,1>, <6,2,7,3> + 3763487969U, // <1,1,6,3>: Cost 4 vext3 <0,u,1,1>, <1,6,3,7> + 3696382572U, // <1,1,6,4>: Cost 4 vext2 <0,u,1,1>, <6,4,2,0> + 4029309266U, // <1,1,6,5>: Cost 4 vzipr <0,4,1,6>, <0,4,1,5> + 2617332536U, // <1,1,6,6>: Cost 3 vext2 <0,0,1,1>, <6,6,6,6> + 2724840702U, // <1,1,6,7>: Cost 3 vext3 <6,7,0,1>, <1,6,7,0> + 2725504263U, // <1,1,6,u>: Cost 3 vext3 <6,u,0,1>, <1,6,u,0> + 2617332720U, // <1,1,7,0>: Cost 3 vext2 <0,0,1,1>, <7,0,0,1> + 2659800138U, // <1,1,7,1>: Cost 3 vext2 <7,1,1,1>, <7,1,1,1> + 3691074725U, // <1,1,7,2>: Cost 4 vext2 <0,0,1,1>, <7,2,2,2> + 4167811174U, // <1,1,7,3>: Cost 4 vtrnr <1,1,5,7>, LHS + 2617333094U, // <1,1,7,4>: Cost 3 vext2 <0,0,1,1>, <7,4,5,6> + 3769091390U, // <1,1,7,5>: Cost 4 vext3 <1,7,5,1>, <1,7,5,1> + 2255156055U, // <1,1,7,6>: Cost 3 vrev <6,7,1,1> + 2617333356U, // <1,1,7,7>: Cost 3 vext2 <0,0,1,1>, <7,7,7,7> + 2267101449U, // <1,1,7,u>: Cost 3 vrev + 1483112550U, // <1,1,u,0>: Cost 2 vext1 <1,1,1,1>, LHS + 202162278U, // <1,1,u,1>: Cost 1 vdup1 LHS + 2622642035U, // <1,1,u,2>: Cost 3 vext2 <0,u,1,1>, + 2014142566U, // <1,1,u,3>: Cost 2 vtrnr LHS, LHS + 1483115830U, // <1,1,u,4>: Cost 2 vext1 <1,1,1,1>, RHS + 1548900506U, // <1,1,u,5>: Cost 2 vext2 <0,u,1,1>, RHS + 2622642384U, // <1,1,u,6>: Cost 3 vext2 <0,u,1,1>, + 2825293353U, // <1,1,u,7>: Cost 3 vuzpr <1,1,1,1>, RHS + 202162278U, // <1,1,u,u>: Cost 1 vdup1 LHS + 2635251712U, // <1,2,0,0>: Cost 3 vext2 <3,0,1,2>, <0,0,0,0> + 1561509990U, // <1,2,0,1>: Cost 2 vext2 <3,0,1,2>, LHS + 2618663085U, // <1,2,0,2>: Cost 3 vext2 <0,2,1,2>, <0,2,1,2> + 2619326718U, // <1,2,0,3>: Cost 3 vext2 <0,3,1,2>, <0,3,1,2> + 2635252050U, // <1,2,0,4>: Cost 3 vext2 <3,0,1,2>, <0,4,1,5> + 2635252142U, // <1,2,0,5>: Cost 3 vext2 <3,0,1,2>, <0,5,2,7> + 2621317617U, // <1,2,0,6>: Cost 3 vext2 <0,6,1,2>, <0,6,1,2> + 2659140160U, // <1,2,0,7>: Cost 3 vext2 <7,0,1,2>, <0,7,1,0> + 1561510557U, // <1,2,0,u>: Cost 2 vext2 <3,0,1,2>, LHS + 2623308516U, // <1,2,1,0>: Cost 3 vext2 <1,0,1,2>, <1,0,1,2> + 2635252532U, // <1,2,1,1>: Cost 3 vext2 <3,0,1,2>, <1,1,1,1> + 2631271318U, // <1,2,1,2>: Cost 3 vext2 <2,3,1,2>, <1,2,3,0> + 2958180454U, // <1,2,1,3>: Cost 3 vzipr <0,u,1,1>, LHS + 2550959414U, // <1,2,1,4>: Cost 3 vext1 <0,1,2,1>, RHS + 2635252880U, // <1,2,1,5>: Cost 3 vext2 <3,0,1,2>, <1,5,3,7> + 2635252952U, // <1,2,1,6>: Cost 3 vext2 <3,0,1,2>, <1,6,2,7> + 3732882731U, // <1,2,1,7>: Cost 4 vext2 <7,0,1,2>, <1,7,3,0> + 2958180459U, // <1,2,1,u>: Cost 3 vzipr <0,u,1,1>, LHS + 2629281213U, // <1,2,2,0>: Cost 3 vext2 <2,0,1,2>, <2,0,1,2> + 2635253254U, // <1,2,2,1>: Cost 3 vext2 <3,0,1,2>, <2,1,0,3> + 2618664552U, // <1,2,2,2>: Cost 3 vext2 <0,2,1,2>, <2,2,2,2> + 2689746546U, // <1,2,2,3>: Cost 3 vext3 <0,u,1,1>, <2,2,3,3> + 3764815485U, // <1,2,2,4>: Cost 4 vext3 <1,1,1,1>, <2,2,4,5> + 3760023176U, // <1,2,2,5>: Cost 4 vext3 <0,2,u,1>, <2,2,5,7> + 2635253690U, // <1,2,2,6>: Cost 3 vext2 <3,0,1,2>, <2,6,3,7> + 2659141610U, // <1,2,2,7>: Cost 3 vext2 <7,0,1,2>, <2,7,0,1> + 2689746591U, // <1,2,2,u>: Cost 3 vext3 <0,u,1,1>, <2,2,u,3> + 403488870U, // <1,2,3,0>: Cost 1 vext1 LHS, LHS + 1477231412U, // <1,2,3,1>: Cost 2 vext1 LHS, <1,1,1,1> + 1477232232U, // <1,2,3,2>: Cost 2 vext1 LHS, <2,2,2,2> + 1477232950U, // <1,2,3,3>: Cost 2 vext1 LHS, <3,2,1,0> + 403492150U, // <1,2,3,4>: Cost 1 vext1 LHS, RHS + 1525010128U, // <1,2,3,5>: Cost 2 vext1 LHS, <5,1,7,3> + 1525010938U, // <1,2,3,6>: Cost 2 vext1 LHS, <6,2,7,3> + 1525011450U, // <1,2,3,7>: Cost 2 vext1 LHS, <7,0,1,2> + 403494702U, // <1,2,3,u>: Cost 1 vext1 LHS, LHS + 2641226607U, // <1,2,4,0>: Cost 3 vext2 <4,0,1,2>, <4,0,1,2> + 3624723446U, // <1,2,4,1>: Cost 4 vext1 <0,1,2,4>, <1,3,4,6> + 3636667929U, // <1,2,4,2>: Cost 4 vext1 <2,1,2,4>, <2,1,2,4> + 2598759198U, // <1,2,4,3>: Cost 3 vext1 , <3,u,1,2> + 2659142864U, // <1,2,4,4>: Cost 3 vext2 <7,0,1,2>, <4,4,4,4> + 1561513270U, // <1,2,4,5>: Cost 2 vext2 <3,0,1,2>, RHS + 2659143028U, // <1,2,4,6>: Cost 3 vext2 <7,0,1,2>, <4,6,4,6> + 2659143112U, // <1,2,4,7>: Cost 3 vext2 <7,0,1,2>, <4,7,5,0> + 1561513513U, // <1,2,4,u>: Cost 2 vext2 <3,0,1,2>, RHS + 2550988902U, // <1,2,5,0>: Cost 3 vext1 <0,1,2,5>, LHS + 2550989824U, // <1,2,5,1>: Cost 3 vext1 <0,1,2,5>, <1,3,5,7> + 3624732264U, // <1,2,5,2>: Cost 4 vext1 <0,1,2,5>, <2,2,2,2> + 2955559014U, // <1,2,5,3>: Cost 3 vzipr <0,4,1,5>, LHS + 2550992182U, // <1,2,5,4>: Cost 3 vext1 <0,1,2,5>, RHS + 2659143684U, // <1,2,5,5>: Cost 3 vext2 <7,0,1,2>, <5,5,5,5> + 2659143778U, // <1,2,5,6>: Cost 3 vext2 <7,0,1,2>, <5,6,7,0> + 2659143848U, // <1,2,5,7>: Cost 3 vext2 <7,0,1,2>, <5,7,5,7> + 2550994734U, // <1,2,5,u>: Cost 3 vext1 <0,1,2,5>, LHS + 2700289945U, // <1,2,6,0>: Cost 3 vext3 <2,6,0,1>, <2,6,0,1> + 2635256232U, // <1,2,6,1>: Cost 3 vext2 <3,0,1,2>, <6,1,7,2> + 2659144186U, // <1,2,6,2>: Cost 3 vext2 <7,0,1,2>, <6,2,7,3> + 2689746874U, // <1,2,6,3>: Cost 3 vext3 <0,u,1,1>, <2,6,3,7> + 3763488705U, // <1,2,6,4>: Cost 4 vext3 <0,u,1,1>, <2,6,4,5> + 3763488716U, // <1,2,6,5>: Cost 4 vext3 <0,u,1,1>, <2,6,5,7> + 2659144504U, // <1,2,6,6>: Cost 3 vext2 <7,0,1,2>, <6,6,6,6> + 2657817432U, // <1,2,6,7>: Cost 3 vext2 <6,7,1,2>, <6,7,1,2> + 2689746919U, // <1,2,6,u>: Cost 3 vext3 <0,u,1,1>, <2,6,u,7> + 1585402874U, // <1,2,7,0>: Cost 2 vext2 <7,0,1,2>, <7,0,1,2> + 2659144770U, // <1,2,7,1>: Cost 3 vext2 <7,0,1,2>, <7,1,0,2> + 3708998858U, // <1,2,7,2>: Cost 4 vext2 <3,0,1,2>, <7,2,6,3> + 2635257059U, // <1,2,7,3>: Cost 3 vext2 <3,0,1,2>, <7,3,0,1> + 2659145062U, // <1,2,7,4>: Cost 3 vext2 <7,0,1,2>, <7,4,5,6> + 3708999072U, // <1,2,7,5>: Cost 4 vext2 <3,0,1,2>, <7,5,3,1> + 2659145222U, // <1,2,7,6>: Cost 3 vext2 <7,0,1,2>, <7,6,5,4> + 2659145255U, // <1,2,7,7>: Cost 3 vext2 <7,0,1,2>, <7,7,0,1> + 1590711938U, // <1,2,7,u>: Cost 2 vext2 <7,u,1,2>, <7,u,1,2> + 403529835U, // <1,2,u,0>: Cost 1 vext1 LHS, LHS + 1477272372U, // <1,2,u,1>: Cost 2 vext1 LHS, <1,1,1,1> + 1477273192U, // <1,2,u,2>: Cost 2 vext1 LHS, <2,2,2,2> + 1477273750U, // <1,2,u,3>: Cost 2 vext1 LHS, <3,0,1,2> + 403533110U, // <1,2,u,4>: Cost 1 vext1 LHS, RHS + 1561516186U, // <1,2,u,5>: Cost 2 vext2 <3,0,1,2>, RHS + 1525051898U, // <1,2,u,6>: Cost 2 vext1 LHS, <6,2,7,3> + 1525052410U, // <1,2,u,7>: Cost 2 vext1 LHS, <7,0,1,2> + 403535662U, // <1,2,u,u>: Cost 1 vext1 LHS, LHS + 2819407872U, // <1,3,0,0>: Cost 3 vuzpr LHS, <0,0,0,0> + 1551564902U, // <1,3,0,1>: Cost 2 vext2 <1,3,1,3>, LHS + 2819410070U, // <1,3,0,2>: Cost 3 vuzpr LHS, <3,0,1,2> + 2619334911U, // <1,3,0,3>: Cost 3 vext2 <0,3,1,3>, <0,3,1,3> + 2625306962U, // <1,3,0,4>: Cost 3 vext2 <1,3,1,3>, <0,4,1,5> + 3832725879U, // <1,3,0,5>: Cost 4 vuzpl <1,2,3,0>, <0,4,5,6> + 3699048959U, // <1,3,0,6>: Cost 4 vext2 <1,3,1,3>, <0,6,2,7> + 3776538827U, // <1,3,0,7>: Cost 4 vext3 <3,0,7,1>, <3,0,7,1> + 1551565469U, // <1,3,0,u>: Cost 2 vext2 <1,3,1,3>, LHS + 2557001830U, // <1,3,1,0>: Cost 3 vext1 <1,1,3,1>, LHS + 2819408692U, // <1,3,1,1>: Cost 3 vuzpr LHS, <1,1,1,1> + 2618672022U, // <1,3,1,2>: Cost 3 vext2 <0,2,1,3>, <1,2,3,0> + 1745666150U, // <1,3,1,3>: Cost 2 vuzpr LHS, LHS + 2557005110U, // <1,3,1,4>: Cost 3 vext1 <1,1,3,1>, RHS + 2625307792U, // <1,3,1,5>: Cost 3 vext2 <1,3,1,3>, <1,5,3,7> + 3698386127U, // <1,3,1,6>: Cost 4 vext2 <1,2,1,3>, <1,6,1,7> + 2257294428U, // <1,3,1,7>: Cost 3 vrev <7,1,3,1> + 1745666155U, // <1,3,1,u>: Cost 2 vuzpr LHS, LHS + 2819408790U, // <1,3,2,0>: Cost 3 vuzpr LHS, <1,2,3,0> + 2689747254U, // <1,3,2,1>: Cost 3 vext3 <0,u,1,1>, <3,2,1,0> + 2819408036U, // <1,3,2,2>: Cost 3 vuzpr LHS, <0,2,0,2> + 2819851890U, // <1,3,2,3>: Cost 3 vuzpr LHS, <2,2,3,3> + 2819408794U, // <1,3,2,4>: Cost 3 vuzpr LHS, <1,2,3,4> + 3893149890U, // <1,3,2,5>: Cost 4 vuzpr LHS, <0,2,3,5> + 2819408076U, // <1,3,2,6>: Cost 3 vuzpr LHS, <0,2,4,6> + 3772041583U, // <1,3,2,7>: Cost 4 vext3 <2,3,0,1>, <3,2,7,3> + 2819408042U, // <1,3,2,u>: Cost 3 vuzpr LHS, <0,2,0,u> + 1483276390U, // <1,3,3,0>: Cost 2 vext1 <1,1,3,3>, LHS + 1483277128U, // <1,3,3,1>: Cost 2 vext1 <1,1,3,3>, <1,1,3,3> + 2557019752U, // <1,3,3,2>: Cost 3 vext1 <1,1,3,3>, <2,2,2,2> + 2819408856U, // <1,3,3,3>: Cost 3 vuzpr LHS, <1,3,1,3> + 1483279670U, // <1,3,3,4>: Cost 2 vext1 <1,1,3,3>, RHS + 2819409614U, // <1,3,3,5>: Cost 3 vuzpr LHS, <2,3,4,5> + 2598826490U, // <1,3,3,6>: Cost 3 vext1 , <6,2,7,3> + 3087844352U, // <1,3,3,7>: Cost 3 vtrnr LHS, <1,3,5,7> + 1483282222U, // <1,3,3,u>: Cost 2 vext1 <1,1,3,3>, LHS + 2568970342U, // <1,3,4,0>: Cost 3 vext1 <3,1,3,4>, LHS + 2568971224U, // <1,3,4,1>: Cost 3 vext1 <3,1,3,4>, <1,3,1,3> + 3832761290U, // <1,3,4,2>: Cost 4 vuzpl <1,2,3,4>, <4,1,2,3> + 2568972539U, // <1,3,4,3>: Cost 3 vext1 <3,1,3,4>, <3,1,3,4> + 2568973622U, // <1,3,4,4>: Cost 3 vext1 <3,1,3,4>, RHS + 1551568182U, // <1,3,4,5>: Cost 2 vext2 <1,3,1,3>, RHS + 2819410434U, // <1,3,4,6>: Cost 3 vuzpr LHS, <3,4,5,6> + 3729575382U, // <1,3,4,7>: Cost 4 vext2 <6,4,1,3>, <4,7,6,5> + 1551568425U, // <1,3,4,u>: Cost 2 vext2 <1,3,1,3>, RHS + 2563006566U, // <1,3,5,0>: Cost 3 vext1 <2,1,3,5>, LHS + 2568979456U, // <1,3,5,1>: Cost 3 vext1 <3,1,3,5>, <1,3,5,7> + 2563008035U, // <1,3,5,2>: Cost 3 vext1 <2,1,3,5>, <2,1,3,5> + 2568980732U, // <1,3,5,3>: Cost 3 vext1 <3,1,3,5>, <3,1,3,5> + 2563009846U, // <1,3,5,4>: Cost 3 vext1 <2,1,3,5>, RHS + 2867187716U, // <1,3,5,5>: Cost 3 vuzpr LHS, <5,5,5,5> + 2655834214U, // <1,3,5,6>: Cost 3 vext2 <6,4,1,3>, <5,6,7,4> + 1745669430U, // <1,3,5,7>: Cost 2 vuzpr LHS, RHS + 1745669431U, // <1,3,5,u>: Cost 2 vuzpr LHS, RHS + 2867187810U, // <1,3,6,0>: Cost 3 vuzpr LHS, <5,6,7,0> + 3699052931U, // <1,3,6,1>: Cost 4 vext2 <1,3,1,3>, <6,1,3,1> + 2654507460U, // <1,3,6,2>: Cost 3 vext2 <6,2,1,3>, <6,2,1,3> + 3766291091U, // <1,3,6,3>: Cost 4 vext3 <1,3,3,1>, <3,6,3,7> + 2655834726U, // <1,3,6,4>: Cost 3 vext2 <6,4,1,3>, <6,4,1,3> + 3923384562U, // <1,3,6,5>: Cost 4 vuzpr <5,1,7,3>, + 2657161992U, // <1,3,6,6>: Cost 3 vext2 <6,6,1,3>, <6,6,1,3> + 2819852218U, // <1,3,6,7>: Cost 3 vuzpr LHS, <2,6,3,7> + 2819852219U, // <1,3,6,u>: Cost 3 vuzpr LHS, <2,6,3,u> + 2706926275U, // <1,3,7,0>: Cost 3 vext3 <3,7,0,1>, <3,7,0,1> + 2659816524U, // <1,3,7,1>: Cost 3 vext2 <7,1,1,3>, <7,1,1,3> + 3636766245U, // <1,3,7,2>: Cost 4 vext1 <2,1,3,7>, <2,1,3,7> + 2867187903U, // <1,3,7,3>: Cost 3 vuzpr LHS, <5,7,u,3> + 2625312102U, // <1,3,7,4>: Cost 3 vext2 <1,3,1,3>, <7,4,5,6> + 2662471056U, // <1,3,7,5>: Cost 3 vext2 <7,5,1,3>, <7,5,1,3> + 2625312262U, // <1,3,7,6>: Cost 3 vext2 <1,3,1,3>, <7,6,5,4> + 2867187880U, // <1,3,7,7>: Cost 3 vuzpr LHS, <5,7,5,7> + 2707516171U, // <1,3,7,u>: Cost 3 vext3 <3,7,u,1>, <3,7,u,1> + 1483317350U, // <1,3,u,0>: Cost 2 vext1 <1,1,3,u>, LHS + 1483318093U, // <1,3,u,1>: Cost 2 vext1 <1,1,3,u>, <1,1,3,u> + 2819410718U, // <1,3,u,2>: Cost 3 vuzpr LHS, <3,u,1,2> + 1745666717U, // <1,3,u,3>: Cost 2 vuzpr LHS, LHS + 1483320630U, // <1,3,u,4>: Cost 2 vext1 <1,1,3,u>, RHS + 1551571098U, // <1,3,u,5>: Cost 2 vext2 <1,3,1,3>, RHS + 2819410758U, // <1,3,u,6>: Cost 3 vuzpr LHS, <3,u,5,6> + 1745669673U, // <1,3,u,7>: Cost 2 vuzpr LHS, RHS + 1745666722U, // <1,3,u,u>: Cost 2 vuzpr LHS, LHS + 2580955238U, // <1,4,0,0>: Cost 3 vext1 <5,1,4,0>, LHS + 2619342950U, // <1,4,0,1>: Cost 3 vext2 <0,3,1,4>, LHS + 3692421295U, // <1,4,0,2>: Cost 4 vext2 <0,2,1,4>, <0,2,1,4> + 2619343104U, // <1,4,0,3>: Cost 3 vext2 <0,3,1,4>, <0,3,1,4> + 2580958518U, // <1,4,0,4>: Cost 3 vext1 <5,1,4,0>, RHS + 1634880402U, // <1,4,0,5>: Cost 2 vext3 <4,0,5,1>, <4,0,5,1> + 2713930652U, // <1,4,0,6>: Cost 3 vext3 <4,u,5,1>, <4,0,6,2> + 2256704532U, // <1,4,0,7>: Cost 3 vrev <7,0,4,1> + 1635101613U, // <1,4,0,u>: Cost 2 vext3 <4,0,u,1>, <4,0,u,1> + 3763710902U, // <1,4,1,0>: Cost 4 vext3 <0,u,4,1>, <4,1,0,1> + 2623988535U, // <1,4,1,1>: Cost 3 vext2 <1,1,1,4>, <1,1,1,4> + 3693085590U, // <1,4,1,2>: Cost 4 vext2 <0,3,1,4>, <1,2,3,0> + 3692422134U, // <1,4,1,3>: Cost 4 vext2 <0,2,1,4>, <1,3,4,6> + 3693085726U, // <1,4,1,4>: Cost 4 vext2 <0,3,1,4>, <1,4,0,1> + 2892401974U, // <1,4,1,5>: Cost 3 vzipl <1,1,1,1>, RHS + 3026619702U, // <1,4,1,6>: Cost 3 vtrnl <1,1,1,1>, RHS + 3800206324U, // <1,4,1,7>: Cost 4 vext3 <7,0,4,1>, <4,1,7,0> + 2892402217U, // <1,4,1,u>: Cost 3 vzipl <1,1,1,1>, RHS + 3966978927U, // <1,4,2,0>: Cost 4 vzipl <1,2,3,4>, <4,0,1,2> + 3966979018U, // <1,4,2,1>: Cost 4 vzipl <1,2,3,4>, <4,1,2,3> + 3693086312U, // <1,4,2,2>: Cost 4 vext2 <0,3,1,4>, <2,2,2,2> + 2635269798U, // <1,4,2,3>: Cost 3 vext2 <3,0,1,4>, <2,3,0,1> + 3966979280U, // <1,4,2,4>: Cost 4 vzipl <1,2,3,4>, <4,4,4,4> + 2893204790U, // <1,4,2,5>: Cost 3 vzipl <1,2,3,0>, RHS + 3693086650U, // <1,4,2,6>: Cost 4 vext2 <0,3,1,4>, <2,6,3,7> + 3666662502U, // <1,4,2,7>: Cost 4 vext1 <7,1,4,2>, <7,1,4,2> + 2893205033U, // <1,4,2,u>: Cost 3 vzipl <1,2,3,0>, RHS + 2563063910U, // <1,4,3,0>: Cost 3 vext1 <2,1,4,3>, LHS + 2563064730U, // <1,4,3,1>: Cost 3 vext1 <2,1,4,3>, <1,2,3,4> + 2563065386U, // <1,4,3,2>: Cost 3 vext1 <2,1,4,3>, <2,1,4,3> + 3693087132U, // <1,4,3,3>: Cost 4 vext2 <0,3,1,4>, <3,3,3,3> + 2619345410U, // <1,4,3,4>: Cost 3 vext2 <0,3,1,4>, <3,4,5,6> + 3087843666U, // <1,4,3,5>: Cost 3 vtrnr LHS, <0,4,1,5> + 3087843676U, // <1,4,3,6>: Cost 3 vtrnr LHS, <0,4,2,6> + 3666670695U, // <1,4,3,7>: Cost 4 vext1 <7,1,4,3>, <7,1,4,3> + 3087843669U, // <1,4,3,u>: Cost 3 vtrnr LHS, <0,4,1,u> + 2620672914U, // <1,4,4,0>: Cost 3 vext2 <0,5,1,4>, <4,0,5,1> + 3693087696U, // <1,4,4,1>: Cost 4 vext2 <0,3,1,4>, <4,1,3,0> + 3624871590U, // <1,4,4,2>: Cost 4 vext1 <0,1,4,4>, <2,3,0,1> + 3642788100U, // <1,4,4,3>: Cost 4 vext1 <3,1,4,4>, <3,1,4,4> + 2713930960U, // <1,4,4,4>: Cost 3 vext3 <4,u,5,1>, <4,4,4,4> + 2619346230U, // <1,4,4,5>: Cost 3 vext2 <0,3,1,4>, RHS + 2713930980U, // <1,4,4,6>: Cost 3 vext3 <4,u,5,1>, <4,4,6,6> + 3736882642U, // <1,4,4,7>: Cost 4 vext2 <7,6,1,4>, <4,7,6,1> + 2619346473U, // <1,4,4,u>: Cost 3 vext2 <0,3,1,4>, RHS + 2557108326U, // <1,4,5,0>: Cost 3 vext1 <1,1,4,5>, LHS + 2557109075U, // <1,4,5,1>: Cost 3 vext1 <1,1,4,5>, <1,1,4,5> + 2598913774U, // <1,4,5,2>: Cost 3 vext1 , <2,3,u,1> + 3630852246U, // <1,4,5,3>: Cost 4 vext1 <1,1,4,5>, <3,0,1,2> + 2557111606U, // <1,4,5,4>: Cost 3 vext1 <1,1,4,5>, RHS + 2895252790U, // <1,4,5,5>: Cost 3 vzipl <1,5,3,7>, RHS + 1616006454U, // <1,4,5,6>: Cost 2 vext3 <0,u,1,1>, RHS + 3899059510U, // <1,4,5,7>: Cost 4 vuzpr <1,1,1,4>, RHS + 1616006472U, // <1,4,5,u>: Cost 2 vext3 <0,u,1,1>, RHS + 2557116518U, // <1,4,6,0>: Cost 3 vext1 <1,1,4,6>, LHS + 2557117236U, // <1,4,6,1>: Cost 3 vext1 <1,1,4,6>, <1,1,1,1> + 2698300764U, // <1,4,6,2>: Cost 3 vext3 <2,3,0,1>, <4,6,2,0> + 2569062550U, // <1,4,6,3>: Cost 3 vext1 <3,1,4,6>, <3,0,1,2> + 2557119798U, // <1,4,6,4>: Cost 3 vext1 <1,1,4,6>, RHS + 3763490174U, // <1,4,6,5>: Cost 4 vext3 <0,u,1,1>, <4,6,5,7> + 3763490183U, // <1,4,6,6>: Cost 4 vext3 <0,u,1,1>, <4,6,6,7> + 2712751498U, // <1,4,6,7>: Cost 3 vext3 <4,6,7,1>, <4,6,7,1> + 2557122350U, // <1,4,6,u>: Cost 3 vext1 <1,1,4,6>, LHS + 2659161084U, // <1,4,7,0>: Cost 3 vext2 <7,0,1,4>, <7,0,1,4> + 3732903040U, // <1,4,7,1>: Cost 4 vext2 <7,0,1,4>, <7,1,7,1> + 3734230174U, // <1,4,7,2>: Cost 4 vext2 <7,2,1,4>, <7,2,1,4> + 3734893807U, // <1,4,7,3>: Cost 4 vext2 <7,3,1,4>, <7,3,1,4> + 2622002534U, // <1,4,7,4>: Cost 3 vext2 <0,7,1,4>, <7,4,5,6> + 3786493384U, // <1,4,7,5>: Cost 4 vext3 <4,6,7,1>, <4,7,5,0> + 2713341394U, // <1,4,7,6>: Cost 3 vext3 <4,7,6,1>, <4,7,6,1> + 3660731386U, // <1,4,7,7>: Cost 4 vext1 <6,1,4,7>, <7,0,1,2> + 2664470148U, // <1,4,7,u>: Cost 3 vext2 <7,u,1,4>, <7,u,1,4> + 2557132902U, // <1,4,u,0>: Cost 3 vext1 <1,1,4,u>, LHS + 2619348782U, // <1,4,u,1>: Cost 3 vext2 <0,3,1,4>, LHS + 2232150111U, // <1,4,u,2>: Cost 3 vrev <2,u,4,1> + 2619343104U, // <1,4,u,3>: Cost 3 vext2 <0,3,1,4>, <0,3,1,4> + 2622666815U, // <1,4,u,4>: Cost 3 vext2 <0,u,1,4>, + 1640189466U, // <1,4,u,5>: Cost 2 vext3 <4,u,5,1>, <4,u,5,1> + 1616006697U, // <1,4,u,6>: Cost 2 vext3 <0,u,1,1>, RHS + 2256704532U, // <1,4,u,7>: Cost 3 vrev <7,0,4,1> + 1616006715U, // <1,4,u,u>: Cost 2 vext3 <0,u,1,1>, RHS + 2620014592U, // <1,5,0,0>: Cost 3 vext2 <0,4,1,5>, <0,0,0,0> + 1546272870U, // <1,5,0,1>: Cost 2 vext2 <0,4,1,5>, LHS + 2618687664U, // <1,5,0,2>: Cost 3 vext2 <0,2,1,5>, <0,2,1,5> + 3693093120U, // <1,5,0,3>: Cost 4 vext2 <0,3,1,5>, <0,3,1,4> + 1546273106U, // <1,5,0,4>: Cost 2 vext2 <0,4,1,5>, <0,4,1,5> + 2620678563U, // <1,5,0,5>: Cost 3 vext2 <0,5,1,5>, <0,5,1,5> + 2714668660U, // <1,5,0,6>: Cost 3 vext3 <5,0,6,1>, <5,0,6,1> + 4167978294U, // <1,5,0,7>: Cost 4 vtrnr <1,1,u,0>, RHS + 1546273437U, // <1,5,0,u>: Cost 2 vext2 <0,4,1,5>, LHS + 2713931407U, // <1,5,1,0>: Cost 3 vext3 <4,u,5,1>, <5,1,0,1> + 2620015412U, // <1,5,1,1>: Cost 3 vext2 <0,4,1,5>, <1,1,1,1> + 2620015510U, // <1,5,1,2>: Cost 3 vext2 <0,4,1,5>, <1,2,3,0> + 2618688512U, // <1,5,1,3>: Cost 3 vext2 <0,2,1,5>, <1,3,5,7> + 2620015677U, // <1,5,1,4>: Cost 3 vext2 <0,4,1,5>, <1,4,3,5> + 2620015727U, // <1,5,1,5>: Cost 3 vext2 <0,4,1,5>, <1,5,0,1> + 2620015859U, // <1,5,1,6>: Cost 3 vext2 <0,4,1,5>, <1,6,5,7> + 3093728566U, // <1,5,1,7>: Cost 3 vtrnr <1,1,1,1>, RHS + 2620015981U, // <1,5,1,u>: Cost 3 vext2 <0,4,1,5>, <1,u,1,3> + 3693757885U, // <1,5,2,0>: Cost 4 vext2 <0,4,1,5>, <2,0,1,2> + 2620016163U, // <1,5,2,1>: Cost 3 vext2 <0,4,1,5>, <2,1,3,5> + 2620016232U, // <1,5,2,2>: Cost 3 vext2 <0,4,1,5>, <2,2,2,2> + 2620016294U, // <1,5,2,3>: Cost 3 vext2 <0,4,1,5>, <2,3,0,1> + 3693758221U, // <1,5,2,4>: Cost 4 vext2 <0,4,1,5>, <2,4,2,5> + 3692431209U, // <1,5,2,5>: Cost 4 vext2 <0,2,1,5>, <2,5,3,7> + 2620016570U, // <1,5,2,6>: Cost 3 vext2 <0,4,1,5>, <2,6,3,7> + 4173598006U, // <1,5,2,7>: Cost 4 vtrnr <2,1,3,2>, RHS + 2620016699U, // <1,5,2,u>: Cost 3 vext2 <0,4,1,5>, <2,u,0,1> + 2620016790U, // <1,5,3,0>: Cost 3 vext2 <0,4,1,5>, <3,0,1,2> + 2569110672U, // <1,5,3,1>: Cost 3 vext1 <3,1,5,3>, <1,5,3,7> + 2620016950U, // <1,5,3,2>: Cost 3 vext2 <0,4,1,5>, <3,2,1,0> + 2620017052U, // <1,5,3,3>: Cost 3 vext2 <0,4,1,5>, <3,3,3,3> + 2620017154U, // <1,5,3,4>: Cost 3 vext2 <0,4,1,5>, <3,4,5,6> + 3135623172U, // <1,5,3,5>: Cost 3 vtrnr LHS, <5,5,5,5> + 4161587048U, // <1,5,3,6>: Cost 4 vtrnr LHS, <2,5,3,6> + 2014104886U, // <1,5,3,7>: Cost 2 vtrnr LHS, RHS + 2014104887U, // <1,5,3,u>: Cost 2 vtrnr LHS, RHS + 2575089766U, // <1,5,4,0>: Cost 3 vext1 <4,1,5,4>, LHS + 2620017634U, // <1,5,4,1>: Cost 3 vext2 <0,4,1,5>, <4,1,5,0> + 3693759551U, // <1,5,4,2>: Cost 4 vext2 <0,4,1,5>, <4,2,6,3> + 3772632990U, // <1,5,4,3>: Cost 4 vext3 <2,3,u,1>, <5,4,3,2> + 2575092710U, // <1,5,4,4>: Cost 3 vext1 <4,1,5,4>, <4,1,5,4> + 1546276150U, // <1,5,4,5>: Cost 2 vext2 <0,4,1,5>, RHS + 2759855414U, // <1,5,4,6>: Cost 3 vuzpl <1,3,5,7>, RHS + 4167494966U, // <1,5,4,7>: Cost 4 vtrnr <1,1,1,4>, RHS + 1546276393U, // <1,5,4,u>: Cost 2 vext2 <0,4,1,5>, RHS + 2557182054U, // <1,5,5,0>: Cost 3 vext1 <1,1,5,5>, LHS + 2620018354U, // <1,5,5,1>: Cost 3 vext2 <0,4,1,5>, <5,1,4,0> + 3630925347U, // <1,5,5,2>: Cost 4 vext1 <1,1,5,5>, <2,1,3,5> + 4029301675U, // <1,5,5,3>: Cost 4 vzipr <0,4,1,5>, <1,2,5,3> + 2557185334U, // <1,5,5,4>: Cost 3 vext1 <1,1,5,5>, RHS + 2713931780U, // <1,5,5,5>: Cost 3 vext3 <4,u,5,1>, <5,5,5,5> + 2667794530U, // <1,5,5,6>: Cost 3 vext2 , <5,6,7,0> + 2713931800U, // <1,5,5,7>: Cost 3 vext3 <4,u,5,1>, <5,5,7,7> + 2557187886U, // <1,5,5,u>: Cost 3 vext1 <1,1,5,5>, LHS + 2718208036U, // <1,5,6,0>: Cost 3 vext3 <5,6,0,1>, <5,6,0,1> + 2620019115U, // <1,5,6,1>: Cost 3 vext2 <0,4,1,5>, <6,1,7,5> + 2667794938U, // <1,5,6,2>: Cost 3 vext2 , <6,2,7,3> + 3787673666U, // <1,5,6,3>: Cost 4 vext3 <4,u,5,1>, <5,6,3,4> + 3693761132U, // <1,5,6,4>: Cost 4 vext2 <0,4,1,5>, <6,4,2,0> + 3654823617U, // <1,5,6,5>: Cost 4 vext1 <5,1,5,6>, <5,1,5,6> + 2667795256U, // <1,5,6,6>: Cost 3 vext2 , <6,6,6,6> + 2713931874U, // <1,5,6,7>: Cost 3 vext3 <4,u,5,1>, <5,6,7,0> + 2713931883U, // <1,5,6,u>: Cost 3 vext3 <4,u,5,1>, <5,6,u,0> + 2557198438U, // <1,5,7,0>: Cost 3 vext1 <1,1,5,7>, LHS + 2557199156U, // <1,5,7,1>: Cost 3 vext1 <1,1,5,7>, <1,1,1,1> + 2569143974U, // <1,5,7,2>: Cost 3 vext1 <3,1,5,7>, <2,3,0,1> + 2569144592U, // <1,5,7,3>: Cost 3 vext1 <3,1,5,7>, <3,1,5,7> + 2557201718U, // <1,5,7,4>: Cost 3 vext1 <1,1,5,7>, RHS + 2713931944U, // <1,5,7,5>: Cost 3 vext3 <4,u,5,1>, <5,7,5,7> + 2255451003U, // <1,5,7,6>: Cost 3 vrev <6,7,5,1> + 2719387828U, // <1,5,7,7>: Cost 3 vext3 <5,7,7,1>, <5,7,7,1> + 2557204270U, // <1,5,7,u>: Cost 3 vext1 <1,1,5,7>, LHS + 2620020435U, // <1,5,u,0>: Cost 3 vext2 <0,4,1,5>, + 1546278702U, // <1,5,u,1>: Cost 2 vext2 <0,4,1,5>, LHS + 2620020595U, // <1,5,u,2>: Cost 3 vext2 <0,4,1,5>, + 2620020668U, // <1,5,u,3>: Cost 3 vext2 <0,4,1,5>, + 1594054682U, // <1,5,u,4>: Cost 2 vext2 , + 1546279066U, // <1,5,u,5>: Cost 2 vext2 <0,4,1,5>, RHS + 2620020944U, // <1,5,u,6>: Cost 3 vext2 <0,4,1,5>, + 2014145846U, // <1,5,u,7>: Cost 2 vtrnr LHS, RHS + 2014145847U, // <1,5,u,u>: Cost 2 vtrnr LHS, RHS + 3692437504U, // <1,6,0,0>: Cost 4 vext2 <0,2,1,6>, <0,0,0,0> + 2618695782U, // <1,6,0,1>: Cost 3 vext2 <0,2,1,6>, LHS + 2618695857U, // <1,6,0,2>: Cost 3 vext2 <0,2,1,6>, <0,2,1,6> + 3794161970U, // <1,6,0,3>: Cost 4 vext3 <6,0,3,1>, <6,0,3,1> + 2620023122U, // <1,6,0,4>: Cost 3 vext2 <0,4,1,6>, <0,4,1,5> + 2620686756U, // <1,6,0,5>: Cost 3 vext2 <0,5,1,6>, <0,5,1,6> + 2621350389U, // <1,6,0,6>: Cost 3 vext2 <0,6,1,6>, <0,6,1,6> + 2972110134U, // <1,6,0,7>: Cost 3 vzipr <3,2,1,0>, RHS + 2618696349U, // <1,6,0,u>: Cost 3 vext2 <0,2,1,6>, LHS + 3642908774U, // <1,6,1,0>: Cost 4 vext1 <3,1,6,1>, LHS + 2625995572U, // <1,6,1,1>: Cost 3 vext2 <1,4,1,6>, <1,1,1,1> + 3692438422U, // <1,6,1,2>: Cost 4 vext2 <0,2,1,6>, <1,2,3,0> + 3692438488U, // <1,6,1,3>: Cost 4 vext2 <0,2,1,6>, <1,3,1,3> + 2625995820U, // <1,6,1,4>: Cost 3 vext2 <1,4,1,6>, <1,4,1,6> + 3692438672U, // <1,6,1,5>: Cost 4 vext2 <0,2,1,6>, <1,5,3,7> + 3692438720U, // <1,6,1,6>: Cost 4 vext2 <0,2,1,6>, <1,6,0,1> + 2958183734U, // <1,6,1,7>: Cost 3 vzipr <0,u,1,1>, RHS + 2958183735U, // <1,6,1,u>: Cost 3 vzipr <0,u,1,1>, RHS + 2721526201U, // <1,6,2,0>: Cost 3 vext3 <6,2,0,1>, <6,2,0,1> + 3692439097U, // <1,6,2,1>: Cost 4 vext2 <0,2,1,6>, <2,1,6,0> + 3692439144U, // <1,6,2,2>: Cost 4 vext2 <0,2,1,6>, <2,2,2,2> + 3692439206U, // <1,6,2,3>: Cost 4 vext2 <0,2,1,6>, <2,3,0,1> + 3763491292U, // <1,6,2,4>: Cost 4 vext3 <0,u,1,1>, <6,2,4,0> + 3787674092U, // <1,6,2,5>: Cost 4 vext3 <4,u,5,1>, <6,2,5,7> + 2618697658U, // <1,6,2,6>: Cost 3 vext2 <0,2,1,6>, <2,6,3,7> + 2970799414U, // <1,6,2,7>: Cost 3 vzipr <3,0,1,2>, RHS + 2970799415U, // <1,6,2,u>: Cost 3 vzipr <3,0,1,2>, RHS + 2563211366U, // <1,6,3,0>: Cost 3 vext1 <2,1,6,3>, LHS + 3699738854U, // <1,6,3,1>: Cost 4 vext2 <1,4,1,6>, <3,1,1,1> + 2563212860U, // <1,6,3,2>: Cost 3 vext1 <2,1,6,3>, <2,1,6,3> + 3692439964U, // <1,6,3,3>: Cost 4 vext2 <0,2,1,6>, <3,3,3,3> + 2563214646U, // <1,6,3,4>: Cost 3 vext1 <2,1,6,3>, RHS + 4191820018U, // <1,6,3,5>: Cost 4 vtrnr <5,1,7,3>, + 2587103648U, // <1,6,3,6>: Cost 3 vext1 <6,1,6,3>, <6,1,6,3> + 3087845306U, // <1,6,3,7>: Cost 3 vtrnr LHS, <2,6,3,7> + 3087845307U, // <1,6,3,u>: Cost 3 vtrnr LHS, <2,6,3,u> + 3636961382U, // <1,6,4,0>: Cost 4 vext1 <2,1,6,4>, LHS + 3693767650U, // <1,6,4,1>: Cost 4 vext2 <0,4,1,6>, <4,1,5,0> + 3763491436U, // <1,6,4,2>: Cost 4 vext3 <0,u,1,1>, <6,4,2,0> + 3309357574U, // <1,6,4,3>: Cost 4 vrev <3,4,6,1> + 3693767898U, // <1,6,4,4>: Cost 4 vext2 <0,4,1,6>, <4,4,5,5> + 2618699062U, // <1,6,4,5>: Cost 3 vext2 <0,2,1,6>, RHS + 3833670966U, // <1,6,4,6>: Cost 4 vuzpl <1,3,6,7>, RHS + 4028632374U, // <1,6,4,7>: Cost 4 vzipr <0,3,1,4>, RHS + 2618699305U, // <1,6,4,u>: Cost 3 vext2 <0,2,1,6>, RHS + 2575171686U, // <1,6,5,0>: Cost 3 vext1 <4,1,6,5>, LHS + 2575172608U, // <1,6,5,1>: Cost 3 vext1 <4,1,6,5>, <1,3,5,7> + 3636971070U, // <1,6,5,2>: Cost 4 vext1 <2,1,6,5>, <2,1,6,5> + 3642943767U, // <1,6,5,3>: Cost 4 vext1 <3,1,6,5>, <3,1,6,5> + 2575174640U, // <1,6,5,4>: Cost 3 vext1 <4,1,6,5>, <4,1,6,5> + 3732918276U, // <1,6,5,5>: Cost 4 vext2 <7,0,1,6>, <5,5,5,5> + 2620690530U, // <1,6,5,6>: Cost 3 vext2 <0,5,1,6>, <5,6,7,0> + 2955562294U, // <1,6,5,7>: Cost 3 vzipr <0,4,1,5>, RHS + 2955562295U, // <1,6,5,u>: Cost 3 vzipr <0,4,1,5>, RHS + 2724180733U, // <1,6,6,0>: Cost 3 vext3 <6,6,0,1>, <6,6,0,1> + 3692441977U, // <1,6,6,1>: Cost 4 vext2 <0,2,1,6>, <6,1,2,0> + 3631007674U, // <1,6,6,2>: Cost 4 vext1 <1,1,6,6>, <2,6,3,7> + 3692442184U, // <1,6,6,3>: Cost 4 vext2 <0,2,1,6>, <6,3,7,0> + 3631009078U, // <1,6,6,4>: Cost 4 vext1 <1,1,6,6>, RHS + 3787674416U, // <1,6,6,5>: Cost 4 vext3 <4,u,5,1>, <6,6,5,7> + 2713932600U, // <1,6,6,6>: Cost 3 vext3 <4,u,5,1>, <6,6,6,6> + 2713932610U, // <1,6,6,7>: Cost 3 vext3 <4,u,5,1>, <6,6,7,7> + 2713932619U, // <1,6,6,u>: Cost 3 vext3 <4,u,5,1>, <6,6,u,7> + 1651102542U, // <1,6,7,0>: Cost 2 vext3 <6,7,0,1>, <6,7,0,1> + 2724918103U, // <1,6,7,1>: Cost 3 vext3 <6,7,1,1>, <6,7,1,1> + 2698302306U, // <1,6,7,2>: Cost 3 vext3 <2,3,0,1>, <6,7,2,3> + 3642960153U, // <1,6,7,3>: Cost 4 vext1 <3,1,6,7>, <3,1,6,7> + 2713932662U, // <1,6,7,4>: Cost 3 vext3 <4,u,5,1>, <6,7,4,5> + 2725213051U, // <1,6,7,5>: Cost 3 vext3 <6,7,5,1>, <6,7,5,1> + 2724844426U, // <1,6,7,6>: Cost 3 vext3 <6,7,0,1>, <6,7,6,7> + 4035956022U, // <1,6,7,7>: Cost 4 vzipr <1,5,1,7>, RHS + 1651692438U, // <1,6,7,u>: Cost 2 vext3 <6,7,u,1>, <6,7,u,1> + 1651766175U, // <1,6,u,0>: Cost 2 vext3 <6,u,0,1>, <6,u,0,1> + 2618701614U, // <1,6,u,1>: Cost 3 vext2 <0,2,1,6>, LHS + 3135663508U, // <1,6,u,2>: Cost 3 vtrnr LHS, <4,6,u,2> + 3692443580U, // <1,6,u,3>: Cost 4 vext2 <0,2,1,6>, + 2713932743U, // <1,6,u,4>: Cost 3 vext3 <4,u,5,1>, <6,u,4,5> + 2618701978U, // <1,6,u,5>: Cost 3 vext2 <0,2,1,6>, RHS + 2622683344U, // <1,6,u,6>: Cost 3 vext2 <0,u,1,6>, + 3087886266U, // <1,6,u,7>: Cost 3 vtrnr LHS, <2,6,3,7> + 1652356071U, // <1,6,u,u>: Cost 2 vext3 <6,u,u,1>, <6,u,u,1> + 2726171632U, // <1,7,0,0>: Cost 3 vext3 <7,0,0,1>, <7,0,0,1> + 2626666598U, // <1,7,0,1>: Cost 3 vext2 <1,5,1,7>, LHS + 3695100067U, // <1,7,0,2>: Cost 4 vext2 <0,6,1,7>, <0,2,0,1> + 3707044102U, // <1,7,0,3>: Cost 4 vext2 <2,6,1,7>, <0,3,2,1> + 2726466580U, // <1,7,0,4>: Cost 3 vext3 <7,0,4,1>, <7,0,4,1> + 3318722173U, // <1,7,0,5>: Cost 4 vrev <5,0,7,1> + 2621358582U, // <1,7,0,6>: Cost 3 vext2 <0,6,1,7>, <0,6,1,7> + 2622022215U, // <1,7,0,7>: Cost 3 vext2 <0,7,1,7>, <0,7,1,7> + 2626667165U, // <1,7,0,u>: Cost 3 vext2 <1,5,1,7>, LHS + 2593128550U, // <1,7,1,0>: Cost 3 vext1 <7,1,7,1>, LHS + 2626667316U, // <1,7,1,1>: Cost 3 vext2 <1,5,1,7>, <1,1,1,1> + 3700409238U, // <1,7,1,2>: Cost 4 vext2 <1,5,1,7>, <1,2,3,0> + 2727056476U, // <1,7,1,3>: Cost 3 vext3 <7,1,3,1>, <7,1,3,1> + 2593131830U, // <1,7,1,4>: Cost 3 vext1 <7,1,7,1>, RHS + 2626667646U, // <1,7,1,5>: Cost 3 vext2 <1,5,1,7>, <1,5,1,7> + 2627331279U, // <1,7,1,6>: Cost 3 vext2 <1,6,1,7>, <1,6,1,7> + 2593133696U, // <1,7,1,7>: Cost 3 vext1 <7,1,7,1>, <7,1,7,1> + 2628658545U, // <1,7,1,u>: Cost 3 vext2 <1,u,1,7>, <1,u,1,7> + 2587164774U, // <1,7,2,0>: Cost 3 vext1 <6,1,7,2>, LHS + 3701073445U, // <1,7,2,1>: Cost 4 vext2 <1,6,1,7>, <2,1,3,7> + 3700409960U, // <1,7,2,2>: Cost 4 vext2 <1,5,1,7>, <2,2,2,2> + 2638612134U, // <1,7,2,3>: Cost 3 vext2 <3,5,1,7>, <2,3,0,1> + 2587168054U, // <1,7,2,4>: Cost 3 vext1 <6,1,7,2>, RHS + 3706382167U, // <1,7,2,5>: Cost 4 vext2 <2,5,1,7>, <2,5,1,7> + 2587169192U, // <1,7,2,6>: Cost 3 vext1 <6,1,7,2>, <6,1,7,2> + 3660911610U, // <1,7,2,7>: Cost 4 vext1 <6,1,7,2>, <7,0,1,2> + 2587170606U, // <1,7,2,u>: Cost 3 vext1 <6,1,7,2>, LHS + 1507459174U, // <1,7,3,0>: Cost 2 vext1 <5,1,7,3>, LHS + 2569257984U, // <1,7,3,1>: Cost 3 vext1 <3,1,7,3>, <1,3,5,7> + 2581202536U, // <1,7,3,2>: Cost 3 vext1 <5,1,7,3>, <2,2,2,2> + 2569259294U, // <1,7,3,3>: Cost 3 vext1 <3,1,7,3>, <3,1,7,3> + 1507462454U, // <1,7,3,4>: Cost 2 vext1 <5,1,7,3>, RHS + 1507462864U, // <1,7,3,5>: Cost 2 vext1 <5,1,7,3>, <5,1,7,3> + 2581205498U, // <1,7,3,6>: Cost 3 vext1 <5,1,7,3>, <6,2,7,3> + 2581206010U, // <1,7,3,7>: Cost 3 vext1 <5,1,7,3>, <7,0,1,2> + 1507465006U, // <1,7,3,u>: Cost 2 vext1 <5,1,7,3>, LHS + 2728826164U, // <1,7,4,0>: Cost 3 vext3 <7,4,0,1>, <7,4,0,1> + 3654951732U, // <1,7,4,1>: Cost 4 vext1 <5,1,7,4>, <1,1,1,1> + 3772044616U, // <1,7,4,2>: Cost 4 vext3 <2,3,0,1>, <7,4,2,3> + 3784136016U, // <1,7,4,3>: Cost 4 vext3 <4,3,2,1>, <7,4,3,2> + 3787674971U, // <1,7,4,4>: Cost 4 vext3 <4,u,5,1>, <7,4,4,4> + 2626669878U, // <1,7,4,5>: Cost 3 vext2 <1,5,1,7>, RHS + 3785979241U, // <1,7,4,6>: Cost 4 vext3 <4,6,0,1>, <7,4,6,0> + 3787085176U, // <1,7,4,7>: Cost 4 vext3 <4,7,6,1>, <7,4,7,6> + 2626670121U, // <1,7,4,u>: Cost 3 vext2 <1,5,1,7>, RHS + 2587189350U, // <1,7,5,0>: Cost 3 vext1 <6,1,7,5>, LHS + 2662502096U, // <1,7,5,1>: Cost 3 vext2 <7,5,1,7>, <5,1,7,3> + 3660932643U, // <1,7,5,2>: Cost 4 vext1 <6,1,7,5>, <2,1,3,5> + 2236353120U, // <1,7,5,3>: Cost 3 vrev <3,5,7,1> + 2587192630U, // <1,7,5,4>: Cost 3 vext1 <6,1,7,5>, RHS + 4102034790U, // <1,7,5,5>: Cost 4 vtrnl <1,3,5,7>, <7,4,5,6> + 2651222067U, // <1,7,5,6>: Cost 3 vext2 <5,6,1,7>, <5,6,1,7> + 3899378998U, // <1,7,5,7>: Cost 4 vuzpr <1,1,5,7>, RHS + 2652549333U, // <1,7,5,u>: Cost 3 vext2 <5,u,1,7>, <5,u,1,7> + 3643023462U, // <1,7,6,0>: Cost 4 vext1 <3,1,7,6>, LHS + 3701076390U, // <1,7,6,1>: Cost 4 vext2 <1,6,1,7>, <6,1,7,0> + 3643025338U, // <1,7,6,2>: Cost 4 vext1 <3,1,7,6>, <2,6,3,7> + 3643025697U, // <1,7,6,3>: Cost 4 vext1 <3,1,7,6>, <3,1,7,6> + 3643026742U, // <1,7,6,4>: Cost 4 vext1 <3,1,7,6>, RHS + 2713933318U, // <1,7,6,5>: Cost 3 vext3 <4,u,5,1>, <7,6,5,4> + 3787675153U, // <1,7,6,6>: Cost 4 vext3 <4,u,5,1>, <7,6,6,6> + 2724845076U, // <1,7,6,7>: Cost 3 vext3 <6,7,0,1>, <7,6,7,0> + 2724845089U, // <1,7,6,u>: Cost 3 vext3 <6,7,0,1>, <7,6,u,4> + 2730817063U, // <1,7,7,0>: Cost 3 vext3 <7,7,0,1>, <7,7,0,1> + 3631088436U, // <1,7,7,1>: Cost 4 vext1 <1,1,7,7>, <1,1,1,1> + 3660949158U, // <1,7,7,2>: Cost 4 vext1 <6,1,7,7>, <2,3,0,1> + 3311422210U, // <1,7,7,3>: Cost 4 vrev <3,7,7,1> + 3631090998U, // <1,7,7,4>: Cost 4 vext1 <1,1,7,7>, RHS + 2662503828U, // <1,7,7,5>: Cost 3 vext2 <7,5,1,7>, <7,5,1,7> + 3787675233U, // <1,7,7,6>: Cost 4 vext3 <4,u,5,1>, <7,7,6,5> + 2713933420U, // <1,7,7,7>: Cost 3 vext3 <4,u,5,1>, <7,7,7,7> + 2731406959U, // <1,7,7,u>: Cost 3 vext3 <7,7,u,1>, <7,7,u,1> + 1507500134U, // <1,7,u,0>: Cost 2 vext1 <5,1,7,u>, LHS + 2626672430U, // <1,7,u,1>: Cost 3 vext2 <1,5,1,7>, LHS + 2581243496U, // <1,7,u,2>: Cost 3 vext1 <5,1,7,u>, <2,2,2,2> + 2569300259U, // <1,7,u,3>: Cost 3 vext1 <3,1,7,u>, <3,1,7,u> + 1507503414U, // <1,7,u,4>: Cost 2 vext1 <5,1,7,u>, RHS + 1507503829U, // <1,7,u,5>: Cost 2 vext1 <5,1,7,u>, <5,1,7,u> + 2581246458U, // <1,7,u,6>: Cost 3 vext1 <5,1,7,u>, <6,2,7,3> + 2581246970U, // <1,7,u,7>: Cost 3 vext1 <5,1,7,u>, <7,0,1,2> + 1507505966U, // <1,7,u,u>: Cost 2 vext1 <5,1,7,u>, LHS + 1543643153U, // <1,u,0,0>: Cost 2 vext2 <0,0,1,u>, <0,0,1,u> + 1546297446U, // <1,u,0,1>: Cost 2 vext2 <0,4,1,u>, LHS + 2819448852U, // <1,u,0,2>: Cost 3 vuzpr LHS, <0,0,2,2> + 2619375876U, // <1,u,0,3>: Cost 3 vext2 <0,3,1,u>, <0,3,1,u> + 1546297685U, // <1,u,0,4>: Cost 2 vext2 <0,4,1,u>, <0,4,1,u> + 1658771190U, // <1,u,0,5>: Cost 2 vext3 , + 2736789248U, // <1,u,0,6>: Cost 3 vext3 , + 2972110152U, // <1,u,0,7>: Cost 3 vzipr <3,2,1,0>, RHS + 1546298013U, // <1,u,0,u>: Cost 2 vext2 <0,4,1,u>, LHS + 1483112550U, // <1,u,1,0>: Cost 2 vext1 <1,1,1,1>, LHS + 202162278U, // <1,u,1,1>: Cost 1 vdup1 LHS + 1616009006U, // <1,u,1,2>: Cost 2 vext3 <0,u,1,1>, LHS + 1745707110U, // <1,u,1,3>: Cost 2 vuzpr LHS, LHS + 1483115830U, // <1,u,1,4>: Cost 2 vext1 <1,1,1,1>, RHS + 2620040336U, // <1,u,1,5>: Cost 3 vext2 <0,4,1,u>, <1,5,3,7> + 3026622618U, // <1,u,1,6>: Cost 3 vtrnl <1,1,1,1>, RHS + 2958183752U, // <1,u,1,7>: Cost 3 vzipr <0,u,1,1>, RHS + 202162278U, // <1,u,1,u>: Cost 1 vdup1 LHS + 2819449750U, // <1,u,2,0>: Cost 3 vuzpr LHS, <1,2,3,0> + 2689750899U, // <1,u,2,1>: Cost 3 vext3 <0,u,1,1>, + 2819448996U, // <1,u,2,2>: Cost 3 vuzpr LHS, <0,2,0,2> + 2819450482U, // <1,u,2,3>: Cost 3 vuzpr LHS, <2,2,3,3> + 2819449754U, // <1,u,2,4>: Cost 3 vuzpr LHS, <1,2,3,4> + 2893207706U, // <1,u,2,5>: Cost 3 vzipl <1,2,3,0>, RHS + 2819449036U, // <1,u,2,6>: Cost 3 vuzpr LHS, <0,2,4,6> + 2970799432U, // <1,u,2,7>: Cost 3 vzipr <3,0,1,2>, RHS + 2819449002U, // <1,u,2,u>: Cost 3 vuzpr LHS, <0,2,0,u> + 403931292U, // <1,u,3,0>: Cost 1 vext1 LHS, LHS + 1477673780U, // <1,u,3,1>: Cost 2 vext1 LHS, <1,1,1,1> + 1477674600U, // <1,u,3,2>: Cost 2 vext1 LHS, <2,2,2,2> + 2014102173U, // <1,u,3,3>: Cost 2 vtrnr LHS, LHS + 403934518U, // <1,u,3,4>: Cost 1 vext1 LHS, RHS + 1507536601U, // <1,u,3,5>: Cost 2 vext1 <5,1,u,3>, <5,1,u,3> + 1525453306U, // <1,u,3,6>: Cost 2 vext1 LHS, <6,2,7,3> + 2014105129U, // <1,u,3,7>: Cost 2 vtrnr LHS, RHS + 403937070U, // <1,u,3,u>: Cost 1 vext1 LHS, LHS + 2569338982U, // <1,u,4,0>: Cost 3 vext1 <3,1,u,4>, LHS + 2620042237U, // <1,u,4,1>: Cost 3 vext2 <0,4,1,u>, <4,1,u,0> + 2734135332U, // <1,u,4,2>: Cost 3 vext3 , + 2569341224U, // <1,u,4,3>: Cost 3 vext1 <3,1,u,4>, <3,1,u,4> + 2569342262U, // <1,u,4,4>: Cost 3 vext1 <3,1,u,4>, RHS + 1546300726U, // <1,u,4,5>: Cost 2 vext2 <0,4,1,u>, RHS + 2819449180U, // <1,u,4,6>: Cost 3 vuzpr LHS, <0,4,2,6> + 2259654012U, // <1,u,4,7>: Cost 3 vrev <7,4,u,1> + 1546300969U, // <1,u,4,u>: Cost 2 vext2 <0,4,1,u>, RHS + 2551431270U, // <1,u,5,0>: Cost 3 vext1 <0,1,u,5>, LHS + 2551432192U, // <1,u,5,1>: Cost 3 vext1 <0,1,u,5>, <1,3,5,7> + 3028293422U, // <1,u,5,2>: Cost 3 vtrnl <1,3,5,7>, LHS + 2955559068U, // <1,u,5,3>: Cost 3 vzipr <0,4,1,5>, LHS + 2551434550U, // <1,u,5,4>: Cost 3 vext1 <0,1,u,5>, RHS + 2895255706U, // <1,u,5,5>: Cost 3 vzipl <1,5,3,7>, RHS + 1616009370U, // <1,u,5,6>: Cost 2 vext3 <0,u,1,1>, RHS + 1745710390U, // <1,u,5,7>: Cost 2 vuzpr LHS, RHS + 1745710391U, // <1,u,5,u>: Cost 2 vuzpr LHS, RHS + 2653221159U, // <1,u,6,0>: Cost 3 vext2 <6,0,1,u>, <6,0,1,u> + 2557117236U, // <1,u,6,1>: Cost 3 vext1 <1,1,4,6>, <1,1,1,1> + 2231117793U, // <1,u,6,2>: Cost 3 vrev <2,6,u,1> + 2689751248U, // <1,u,6,3>: Cost 3 vext3 <0,u,1,1>, + 2243063187U, // <1,u,6,4>: Cost 3 vrev <4,6,u,1> + 2713934047U, // <1,u,6,5>: Cost 3 vext3 <4,u,5,1>, + 2657202957U, // <1,u,6,6>: Cost 3 vext2 <6,6,1,u>, <6,6,1,u> + 2819450810U, // <1,u,6,7>: Cost 3 vuzpr LHS, <2,6,3,7> + 2819450811U, // <1,u,6,u>: Cost 3 vuzpr LHS, <2,6,3,u> + 1585452032U, // <1,u,7,0>: Cost 2 vext2 <7,0,1,u>, <7,0,1,u> + 2557420340U, // <1,u,7,1>: Cost 3 vext1 <1,1,u,7>, <1,1,1,1> + 2569365158U, // <1,u,7,2>: Cost 3 vext1 <3,1,u,7>, <2,3,0,1> + 2569365803U, // <1,u,7,3>: Cost 3 vext1 <3,1,u,7>, <3,1,u,7> + 2557422902U, // <1,u,7,4>: Cost 3 vext1 <1,1,u,7>, RHS + 2249699517U, // <1,u,7,5>: Cost 3 vrev <5,7,u,1> + 1181930390U, // <1,u,7,6>: Cost 2 vrev <6,7,u,1> + 2659194476U, // <1,u,7,7>: Cost 3 vext2 <7,0,1,u>, <7,7,7,7> + 1590761096U, // <1,u,7,u>: Cost 2 vext2 <7,u,1,u>, <7,u,1,u> + 403972257U, // <1,u,u,0>: Cost 1 vext1 LHS, LHS + 202162278U, // <1,u,u,1>: Cost 1 vdup1 LHS + 1477715560U, // <1,u,u,2>: Cost 2 vext1 LHS, <2,2,2,2> + 1745707677U, // <1,u,u,3>: Cost 2 vuzpr LHS, LHS + 403975478U, // <1,u,u,4>: Cost 1 vext1 LHS, RHS + 1546303642U, // <1,u,u,5>: Cost 2 vext2 <0,4,1,u>, RHS + 1616009613U, // <1,u,u,6>: Cost 2 vext3 <0,u,1,1>, RHS + 1745710633U, // <1,u,u,7>: Cost 2 vuzpr LHS, RHS + 403978030U, // <1,u,u,u>: Cost 1 vext1 LHS, LHS + 2551463936U, // <2,0,0,0>: Cost 3 vext1 <0,2,0,0>, <0,0,0,0> + 2685698058U, // <2,0,0,1>: Cost 3 vext3 <0,2,0,2>, <0,0,1,1> + 1610776596U, // <2,0,0,2>: Cost 2 vext3 <0,0,2,2>, <0,0,2,2> + 2232526989U, // <2,0,0,3>: Cost 3 vrev <3,0,0,2> + 2551467318U, // <2,0,0,4>: Cost 3 vext1 <0,2,0,0>, RHS + 3899836596U, // <2,0,0,5>: Cost 4 vuzpr <1,2,3,0>, <3,0,4,5> + 2621374968U, // <2,0,0,6>: Cost 3 vext2 <0,6,2,0>, <0,6,2,0> + 2256417777U, // <2,0,0,7>: Cost 3 vrev <7,0,0,2> + 1611219018U, // <2,0,0,u>: Cost 2 vext3 <0,0,u,2>, <0,0,u,2> + 2551472138U, // <2,0,1,0>: Cost 3 vext1 <0,2,0,1>, <0,0,1,1> + 2685108316U, // <2,0,1,1>: Cost 3 vext3 <0,1,1,2>, <0,1,1,2> + 1611956326U, // <2,0,1,2>: Cost 2 vext3 <0,2,0,2>, LHS + 2826092646U, // <2,0,1,3>: Cost 3 vuzpr <1,2,3,0>, LHS + 2551475510U, // <2,0,1,4>: Cost 3 vext1 <0,2,0,1>, RHS + 3692463248U, // <2,0,1,5>: Cost 4 vext2 <0,2,2,0>, <1,5,3,7> + 2587308473U, // <2,0,1,6>: Cost 3 vext1 <6,2,0,1>, <6,2,0,1> + 3661050874U, // <2,0,1,7>: Cost 4 vext1 <6,2,0,1>, <7,0,1,2> + 1611956380U, // <2,0,1,u>: Cost 2 vext3 <0,2,0,2>, LHS + 1477738598U, // <2,0,2,0>: Cost 2 vext1 <0,2,0,2>, LHS + 2551481140U, // <2,0,2,1>: Cost 3 vext1 <0,2,0,2>, <1,1,1,1> + 2551481796U, // <2,0,2,2>: Cost 3 vext1 <0,2,0,2>, <2,0,2,0> + 2551482518U, // <2,0,2,3>: Cost 3 vext1 <0,2,0,2>, <3,0,1,2> + 1477741878U, // <2,0,2,4>: Cost 2 vext1 <0,2,0,2>, RHS + 2551484112U, // <2,0,2,5>: Cost 3 vext1 <0,2,0,2>, <5,1,7,3> + 2551484759U, // <2,0,2,6>: Cost 3 vext1 <0,2,0,2>, <6,0,7,2> + 2551485434U, // <2,0,2,7>: Cost 3 vext1 <0,2,0,2>, <7,0,1,2> + 1477744430U, // <2,0,2,u>: Cost 2 vext1 <0,2,0,2>, LHS + 2953625600U, // <2,0,3,0>: Cost 3 vzipr LHS, <0,0,0,0> + 2953627302U, // <2,0,3,1>: Cost 3 vzipr LHS, <2,3,0,1> + 2953625764U, // <2,0,3,2>: Cost 3 vzipr LHS, <0,2,0,2> + 3625232534U, // <2,0,3,3>: Cost 4 vext1 <0,2,0,3>, <3,0,1,2> + 3625233718U, // <2,0,3,4>: Cost 4 vext1 <0,2,0,3>, RHS + 3899836110U, // <2,0,3,5>: Cost 4 vuzpr <1,2,3,0>, <2,3,4,5> + 4032012618U, // <2,0,3,6>: Cost 4 vzipr LHS, <0,4,0,6> + 3899835392U, // <2,0,3,7>: Cost 4 vuzpr <1,2,3,0>, <1,3,5,7> + 2953625770U, // <2,0,3,u>: Cost 3 vzipr LHS, <0,2,0,u> + 2551496806U, // <2,0,4,0>: Cost 3 vext1 <0,2,0,4>, LHS + 2685698386U, // <2,0,4,1>: Cost 3 vext3 <0,2,0,2>, <0,4,1,5> + 2685698396U, // <2,0,4,2>: Cost 3 vext3 <0,2,0,2>, <0,4,2,6> + 3625240726U, // <2,0,4,3>: Cost 4 vext1 <0,2,0,4>, <3,0,1,2> + 2551500086U, // <2,0,4,4>: Cost 3 vext1 <0,2,0,4>, RHS + 2618723638U, // <2,0,4,5>: Cost 3 vext2 <0,2,2,0>, RHS + 2765409590U, // <2,0,4,6>: Cost 3 vuzpl <2,3,0,1>, RHS + 3799990664U, // <2,0,4,7>: Cost 4 vext3 <7,0,1,2>, <0,4,7,5> + 2685698450U, // <2,0,4,u>: Cost 3 vext3 <0,2,0,2>, <0,4,u,6> + 3625246822U, // <2,0,5,0>: Cost 4 vext1 <0,2,0,5>, LHS + 3297641584U, // <2,0,5,1>: Cost 4 vrev <1,5,0,2> + 2702361006U, // <2,0,5,2>: Cost 3 vext3 <3,0,1,2>, <0,5,2,7> + 3643164978U, // <2,0,5,3>: Cost 4 vext1 <3,2,0,5>, <3,2,0,5> + 3625250102U, // <2,0,5,4>: Cost 4 vext1 <0,2,0,5>, RHS + 3719008260U, // <2,0,5,5>: Cost 4 vext2 <4,6,2,0>, <5,5,5,5> + 3719008354U, // <2,0,5,6>: Cost 4 vext2 <4,6,2,0>, <5,6,7,0> + 2826095926U, // <2,0,5,7>: Cost 3 vuzpr <1,2,3,0>, RHS + 2826095927U, // <2,0,5,u>: Cost 3 vuzpr <1,2,3,0>, RHS + 4162420736U, // <2,0,6,0>: Cost 4 vtrnr <0,2,4,6>, <0,0,0,0> + 2901885030U, // <2,0,6,1>: Cost 3 vzipl <2,6,3,7>, LHS + 2685698559U, // <2,0,6,2>: Cost 3 vext3 <0,2,0,2>, <0,6,2,7> + 3310250611U, // <2,0,6,3>: Cost 4 vrev <3,6,0,2> + 2242481484U, // <2,0,6,4>: Cost 3 vrev <4,6,0,2> + 3322196005U, // <2,0,6,5>: Cost 4 vrev <5,6,0,2> + 3719009080U, // <2,0,6,6>: Cost 4 vext2 <4,6,2,0>, <6,6,6,6> + 2621379406U, // <2,0,6,7>: Cost 3 vext2 <0,6,2,0>, <6,7,0,1> + 2901885597U, // <2,0,6,u>: Cost 3 vzipl <2,6,3,7>, LHS + 2659202049U, // <2,0,7,0>: Cost 3 vext2 <7,0,2,0>, <7,0,2,0> + 2726249024U, // <2,0,7,1>: Cost 3 vext3 <7,0,1,2>, <0,7,1,0> + 2726249034U, // <2,0,7,2>: Cost 3 vext3 <7,0,1,2>, <0,7,2,1> + 3310914244U, // <2,0,7,3>: Cost 4 vrev <3,7,0,2> + 3719009638U, // <2,0,7,4>: Cost 4 vext2 <4,6,2,0>, <7,4,5,6> + 3322859638U, // <2,0,7,5>: Cost 4 vrev <5,7,0,2> + 2255090511U, // <2,0,7,6>: Cost 3 vrev <6,7,0,2> + 3719009900U, // <2,0,7,7>: Cost 4 vext2 <4,6,2,0>, <7,7,7,7> + 2267035905U, // <2,0,7,u>: Cost 3 vrev + 1477787750U, // <2,0,u,0>: Cost 2 vext1 <0,2,0,u>, LHS + 2953668262U, // <2,0,u,1>: Cost 3 vzipr LHS, <2,3,0,1> + 1611956893U, // <2,0,u,2>: Cost 2 vext3 <0,2,0,2>, LHS + 2551531670U, // <2,0,u,3>: Cost 3 vext1 <0,2,0,u>, <3,0,1,2> + 1477791030U, // <2,0,u,4>: Cost 2 vext1 <0,2,0,u>, RHS + 2618726554U, // <2,0,u,5>: Cost 3 vext2 <0,2,2,0>, RHS + 2765412506U, // <2,0,u,6>: Cost 3 vuzpl <2,3,0,1>, RHS + 2826096169U, // <2,0,u,7>: Cost 3 vuzpr <1,2,3,0>, RHS + 1611956947U, // <2,0,u,u>: Cost 2 vext3 <0,2,0,2>, LHS + 1495711846U, // <2,1,0,0>: Cost 2 vext1 <3,2,1,0>, LHS + 2619392102U, // <2,1,0,1>: Cost 3 vext2 <0,3,2,1>, LHS + 2226628029U, // <2,1,0,2>: Cost 3 vrev <2,0,1,2> + 1158858902U, // <2,1,0,3>: Cost 2 vrev <3,0,1,2> + 1495715126U, // <2,1,0,4>: Cost 2 vext1 <3,2,1,0>, RHS + 2244546120U, // <2,1,0,5>: Cost 3 vrev <5,0,1,2> + 2250518817U, // <2,1,0,6>: Cost 3 vrev <6,0,1,2> + 1182749690U, // <2,1,0,7>: Cost 2 vrev <7,0,1,2> + 1495717678U, // <2,1,0,u>: Cost 2 vext1 <3,2,1,0>, LHS + 2551545958U, // <2,1,1,0>: Cost 3 vext1 <0,2,1,1>, LHS + 2685698868U, // <2,1,1,1>: Cost 3 vext3 <0,2,0,2>, <1,1,1,1> + 2643280794U, // <2,1,1,2>: Cost 3 vext2 <4,3,2,1>, <1,2,3,4> + 2685698888U, // <2,1,1,3>: Cost 3 vext3 <0,2,0,2>, <1,1,3,3> + 2551549238U, // <2,1,1,4>: Cost 3 vext1 <0,2,1,1>, RHS + 3693134992U, // <2,1,1,5>: Cost 4 vext2 <0,3,2,1>, <1,5,3,7> + 3711050950U, // <2,1,1,6>: Cost 4 vext2 <3,3,2,1>, <1,6,0,7> + 3625292794U, // <2,1,1,7>: Cost 4 vext1 <0,2,1,1>, <7,0,1,2> + 2685698933U, // <2,1,1,u>: Cost 3 vext3 <0,2,0,2>, <1,1,u,3> + 2551554150U, // <2,1,2,0>: Cost 3 vext1 <0,2,1,2>, LHS + 3893649571U, // <2,1,2,1>: Cost 4 vuzpr <0,2,0,1>, <0,2,0,1> + 2551555688U, // <2,1,2,2>: Cost 3 vext1 <0,2,1,2>, <2,2,2,2> + 2685698966U, // <2,1,2,3>: Cost 3 vext3 <0,2,0,2>, <1,2,3,0> + 2551557430U, // <2,1,2,4>: Cost 3 vext1 <0,2,1,2>, RHS + 3763422123U, // <2,1,2,5>: Cost 4 vext3 <0,u,0,2>, <1,2,5,3> + 3693135802U, // <2,1,2,6>: Cost 4 vext2 <0,3,2,1>, <2,6,3,7> + 2726249402U, // <2,1,2,7>: Cost 3 vext3 <7,0,1,2>, <1,2,7,0> + 2685699011U, // <2,1,2,u>: Cost 3 vext3 <0,2,0,2>, <1,2,u,0> + 2953627958U, // <2,1,3,0>: Cost 3 vzipr LHS, <3,2,1,0> + 2953625610U, // <2,1,3,1>: Cost 3 vzipr LHS, <0,0,1,1> + 2953627798U, // <2,1,3,2>: Cost 3 vzipr LHS, <3,0,1,2> + 2953626584U, // <2,1,3,3>: Cost 3 vzipr LHS, <1,3,1,3> + 2551565622U, // <2,1,3,4>: Cost 3 vext1 <0,2,1,3>, RHS + 2953625938U, // <2,1,3,5>: Cost 3 vzipr LHS, <0,4,1,5> + 2587398596U, // <2,1,3,6>: Cost 3 vext1 <6,2,1,3>, <6,2,1,3> + 4032013519U, // <2,1,3,7>: Cost 4 vzipr LHS, <1,6,1,7> + 2953625617U, // <2,1,3,u>: Cost 3 vzipr LHS, <0,0,1,u> + 3625312358U, // <2,1,4,0>: Cost 4 vext1 <0,2,1,4>, LHS + 3625313270U, // <2,1,4,1>: Cost 4 vext1 <0,2,1,4>, <1,3,4,6> + 3771532340U, // <2,1,4,2>: Cost 4 vext3 <2,2,2,2>, <1,4,2,5> + 3094560870U, // <2,1,4,3>: Cost 3 vtrnr <1,2,3,4>, LHS + 3625315638U, // <2,1,4,4>: Cost 4 vext1 <0,2,1,4>, RHS + 2619395382U, // <2,1,4,5>: Cost 3 vext2 <0,3,2,1>, RHS + 3837242678U, // <2,1,4,6>: Cost 4 vuzpl <2,0,1,2>, RHS + 3799991394U, // <2,1,4,7>: Cost 4 vext3 <7,0,1,2>, <1,4,7,6> + 2619395625U, // <2,1,4,u>: Cost 3 vext2 <0,3,2,1>, RHS + 2551578726U, // <2,1,5,0>: Cost 3 vext1 <0,2,1,5>, LHS + 2551579648U, // <2,1,5,1>: Cost 3 vext1 <0,2,1,5>, <1,3,5,7> + 3625322032U, // <2,1,5,2>: Cost 4 vext1 <0,2,1,5>, <2,1,5,0> + 2685699216U, // <2,1,5,3>: Cost 3 vext3 <0,2,0,2>, <1,5,3,7> + 2551582006U, // <2,1,5,4>: Cost 3 vext1 <0,2,1,5>, RHS + 3625324192U, // <2,1,5,5>: Cost 4 vext1 <0,2,1,5>, <5,1,2,0> + 3720343650U, // <2,1,5,6>: Cost 4 vext2 <4,u,2,1>, <5,6,7,0> + 3893652790U, // <2,1,5,7>: Cost 4 vuzpr <0,2,0,1>, RHS + 2685699261U, // <2,1,5,u>: Cost 3 vext3 <0,2,0,2>, <1,5,u,7> + 2551586918U, // <2,1,6,0>: Cost 3 vext1 <0,2,1,6>, LHS + 3625329460U, // <2,1,6,1>: Cost 4 vext1 <0,2,1,6>, <1,1,1,1> + 2551588794U, // <2,1,6,2>: Cost 3 vext1 <0,2,1,6>, <2,6,3,7> + 3088679014U, // <2,1,6,3>: Cost 3 vtrnr <0,2,4,6>, LHS + 2551590198U, // <2,1,6,4>: Cost 3 vext1 <0,2,1,6>, RHS + 4029382994U, // <2,1,6,5>: Cost 4 vzipr <0,4,2,6>, <0,4,1,5> + 3625333113U, // <2,1,6,6>: Cost 4 vext1 <0,2,1,6>, <6,1,2,0> + 3720344398U, // <2,1,6,7>: Cost 4 vext2 <4,u,2,1>, <6,7,0,1> + 2551592750U, // <2,1,6,u>: Cost 3 vext1 <0,2,1,6>, LHS + 2622051322U, // <2,1,7,0>: Cost 3 vext2 <0,7,2,1>, <7,0,1,2> + 3733615699U, // <2,1,7,1>: Cost 4 vext2 <7,1,2,1>, <7,1,2,1> + 3795125538U, // <2,1,7,2>: Cost 4 vext3 <6,1,7,2>, <1,7,2,0> + 2661201141U, // <2,1,7,3>: Cost 3 vext2 <7,3,2,1>, <7,3,2,1> + 3316960678U, // <2,1,7,4>: Cost 4 vrev <4,7,1,2> + 3322933375U, // <2,1,7,5>: Cost 4 vrev <5,7,1,2> + 2255164248U, // <2,1,7,6>: Cost 3 vrev <6,7,1,2> + 3720345196U, // <2,1,7,7>: Cost 4 vext2 <4,u,2,1>, <7,7,7,7> + 2664519306U, // <2,1,7,u>: Cost 3 vext2 <7,u,2,1>, <7,u,2,1> + 1525637222U, // <2,1,u,0>: Cost 2 vext1 , LHS + 2953666570U, // <2,1,u,1>: Cost 3 vzipr LHS, <0,0,1,1> + 2953668758U, // <2,1,u,2>: Cost 3 vzipr LHS, <3,0,1,2> + 1164167966U, // <2,1,u,3>: Cost 2 vrev <3,u,1,2> + 1525640502U, // <2,1,u,4>: Cost 2 vext1 , RHS + 2953666898U, // <2,1,u,5>: Cost 3 vzipr LHS, <0,4,1,5> + 2587439561U, // <2,1,u,6>: Cost 3 vext1 <6,2,1,u>, <6,2,1,u> + 1188058754U, // <2,1,u,7>: Cost 2 vrev <7,u,1,2> + 1525643131U, // <2,1,u,u>: Cost 2 vext1 , + 1543667732U, // <2,2,0,0>: Cost 2 vext2 <0,0,2,2>, <0,0,2,2> + 1548976230U, // <2,2,0,1>: Cost 2 vext2 <0,u,2,2>, LHS + 2685699524U, // <2,2,0,2>: Cost 3 vext3 <0,2,0,2>, <2,0,2,0> + 2685699535U, // <2,2,0,3>: Cost 3 vext3 <0,2,0,2>, <2,0,3,2> + 2551614774U, // <2,2,0,4>: Cost 3 vext1 <0,2,2,0>, RHS + 3771532774U, // <2,2,0,5>: Cost 4 vext3 <2,2,2,2>, <2,0,5,7> + 3893657642U, // <2,2,0,6>: Cost 4 vuzpr <0,2,0,2>, <0,0,4,6> + 3770574323U, // <2,2,0,7>: Cost 4 vext3 <2,0,7,2>, <2,0,7,2> + 1548976796U, // <2,2,0,u>: Cost 2 vext2 <0,u,2,2>, <0,u,2,2> + 2702362118U, // <2,2,1,0>: Cost 3 vext3 <3,0,1,2>, <2,1,0,3> + 2622718772U, // <2,2,1,1>: Cost 3 vext2 <0,u,2,2>, <1,1,1,1> + 2622718870U, // <2,2,1,2>: Cost 3 vext2 <0,u,2,2>, <1,2,3,0> + 2819915878U, // <2,2,1,3>: Cost 3 vuzpr <0,2,0,2>, LHS + 3625364790U, // <2,2,1,4>: Cost 4 vext1 <0,2,2,1>, RHS + 2622719120U, // <2,2,1,5>: Cost 3 vext2 <0,u,2,2>, <1,5,3,7> + 3760031292U, // <2,2,1,6>: Cost 4 vext3 <0,2,u,2>, <2,1,6,3> + 3798664776U, // <2,2,1,7>: Cost 4 vext3 <6,7,1,2>, <2,1,7,6> + 2819915883U, // <2,2,1,u>: Cost 3 vuzpr <0,2,0,2>, LHS + 1489829990U, // <2,2,2,0>: Cost 2 vext1 <2,2,2,2>, LHS + 2563572532U, // <2,2,2,1>: Cost 3 vext1 <2,2,2,2>, <1,1,1,1> + 269271142U, // <2,2,2,2>: Cost 1 vdup2 LHS + 2685699698U, // <2,2,2,3>: Cost 3 vext3 <0,2,0,2>, <2,2,3,3> + 1489833270U, // <2,2,2,4>: Cost 2 vext1 <2,2,2,2>, RHS + 2685699720U, // <2,2,2,5>: Cost 3 vext3 <0,2,0,2>, <2,2,5,7> + 2622719930U, // <2,2,2,6>: Cost 3 vext2 <0,u,2,2>, <2,6,3,7> + 2257892517U, // <2,2,2,7>: Cost 3 vrev <7,2,2,2> + 269271142U, // <2,2,2,u>: Cost 1 vdup2 LHS + 2685699750U, // <2,2,3,0>: Cost 3 vext3 <0,2,0,2>, <2,3,0,1> + 2698380976U, // <2,2,3,1>: Cost 3 vext3 <2,3,1,2>, <2,3,1,2> + 2953627240U, // <2,2,3,2>: Cost 3 vzipr LHS, <2,2,2,2> + 1879883878U, // <2,2,3,3>: Cost 2 vzipr LHS, LHS + 2685699790U, // <2,2,3,4>: Cost 3 vext3 <0,2,0,2>, <2,3,4,5> + 3893659342U, // <2,2,3,5>: Cost 4 vuzpr <0,2,0,2>, <2,3,4,5> + 2958270812U, // <2,2,3,6>: Cost 3 vzipr LHS, <0,4,2,6> + 2593445030U, // <2,2,3,7>: Cost 3 vext1 <7,2,2,3>, <7,2,2,3> + 1879883883U, // <2,2,3,u>: Cost 2 vzipr LHS, LHS + 2551644262U, // <2,2,4,0>: Cost 3 vext1 <0,2,2,4>, LHS + 3625386804U, // <2,2,4,1>: Cost 4 vext1 <0,2,2,4>, <1,1,1,1> + 2551645902U, // <2,2,4,2>: Cost 3 vext1 <0,2,2,4>, <2,3,4,5> + 3759441686U, // <2,2,4,3>: Cost 4 vext3 <0,2,0,2>, <2,4,3,5> + 2551647542U, // <2,2,4,4>: Cost 3 vext1 <0,2,2,4>, RHS + 1548979510U, // <2,2,4,5>: Cost 2 vext2 <0,u,2,2>, RHS + 2764901686U, // <2,2,4,6>: Cost 3 vuzpl <2,2,2,2>, RHS + 3667195047U, // <2,2,4,7>: Cost 4 vext1 <7,2,2,4>, <7,2,2,4> + 1548979753U, // <2,2,4,u>: Cost 2 vext2 <0,u,2,2>, RHS + 3696463432U, // <2,2,5,0>: Cost 4 vext2 <0,u,2,2>, <5,0,1,2> + 2617413328U, // <2,2,5,1>: Cost 3 vext2 <0,0,2,2>, <5,1,7,3> + 2685699936U, // <2,2,5,2>: Cost 3 vext3 <0,2,0,2>, <2,5,2,7> + 4027383910U, // <2,2,5,3>: Cost 4 vzipr <0,1,2,5>, LHS + 3696463796U, // <2,2,5,4>: Cost 4 vext2 <0,u,2,2>, <5,4,5,6> + 2617413636U, // <2,2,5,5>: Cost 3 vext2 <0,0,2,2>, <5,5,5,5> + 2617413730U, // <2,2,5,6>: Cost 3 vext2 <0,0,2,2>, <5,6,7,0> + 2819919158U, // <2,2,5,7>: Cost 3 vuzpr <0,2,0,2>, RHS + 2819919159U, // <2,2,5,u>: Cost 3 vuzpr <0,2,0,2>, RHS + 3625402554U, // <2,2,6,0>: Cost 4 vext1 <0,2,2,6>, <0,2,2,6> + 3760031652U, // <2,2,6,1>: Cost 4 vext3 <0,2,u,2>, <2,6,1,3> + 2617414138U, // <2,2,6,2>: Cost 3 vext2 <0,0,2,2>, <6,2,7,3> + 2685700026U, // <2,2,6,3>: Cost 3 vext3 <0,2,0,2>, <2,6,3,7> + 3625405750U, // <2,2,6,4>: Cost 4 vext1 <0,2,2,6>, RHS + 3760031692U, // <2,2,6,5>: Cost 4 vext3 <0,2,u,2>, <2,6,5,7> + 3088679116U, // <2,2,6,6>: Cost 3 vtrnr <0,2,4,6>, <0,2,4,6> + 2657891169U, // <2,2,6,7>: Cost 3 vext2 <6,7,2,2>, <6,7,2,2> + 2685700071U, // <2,2,6,u>: Cost 3 vext3 <0,2,0,2>, <2,6,u,7> + 2726250474U, // <2,2,7,0>: Cost 3 vext3 <7,0,1,2>, <2,7,0,1> + 3704427616U, // <2,2,7,1>: Cost 4 vext2 <2,2,2,2>, <7,1,3,5> + 2660545701U, // <2,2,7,2>: Cost 3 vext2 <7,2,2,2>, <7,2,2,2> + 4030718054U, // <2,2,7,3>: Cost 4 vzipr <0,6,2,7>, LHS + 2617415014U, // <2,2,7,4>: Cost 3 vext2 <0,0,2,2>, <7,4,5,6> + 3704427936U, // <2,2,7,5>: Cost 4 vext2 <2,2,2,2>, <7,5,3,1> + 2255237985U, // <2,2,7,6>: Cost 3 vrev <6,7,2,2> + 2617415276U, // <2,2,7,7>: Cost 3 vext2 <0,0,2,2>, <7,7,7,7> + 2731558962U, // <2,2,7,u>: Cost 3 vext3 <7,u,1,2>, <2,7,u,1> + 1489829990U, // <2,2,u,0>: Cost 2 vext1 <2,2,2,2>, LHS + 1548982062U, // <2,2,u,1>: Cost 2 vext2 <0,u,2,2>, LHS + 269271142U, // <2,2,u,2>: Cost 1 vdup2 LHS + 1879924838U, // <2,2,u,3>: Cost 2 vzipr LHS, LHS + 1489833270U, // <2,2,u,4>: Cost 2 vext1 <2,2,2,2>, RHS + 1548982426U, // <2,2,u,5>: Cost 2 vext2 <0,u,2,2>, RHS + 2953666908U, // <2,2,u,6>: Cost 3 vzipr LHS, <0,4,2,6> + 2819919401U, // <2,2,u,7>: Cost 3 vuzpr <0,2,0,2>, RHS + 269271142U, // <2,2,u,u>: Cost 1 vdup2 LHS + 1544339456U, // <2,3,0,0>: Cost 2 vext2 LHS, <0,0,0,0> + 470597734U, // <2,3,0,1>: Cost 1 vext2 LHS, LHS + 1548984484U, // <2,3,0,2>: Cost 2 vext2 LHS, <0,2,0,2> + 2619408648U, // <2,3,0,3>: Cost 3 vext2 <0,3,2,3>, <0,3,2,3> + 1548984658U, // <2,3,0,4>: Cost 2 vext2 LHS, <0,4,1,5> + 2665857454U, // <2,3,0,5>: Cost 3 vext2 LHS, <0,5,2,7> + 2622726655U, // <2,3,0,6>: Cost 3 vext2 LHS, <0,6,2,7> + 2593494188U, // <2,3,0,7>: Cost 3 vext1 <7,2,3,0>, <7,2,3,0> + 470598301U, // <2,3,0,u>: Cost 1 vext2 LHS, LHS + 2551693414U, // <2,3,1,0>: Cost 3 vext1 <0,2,3,1>, LHS + 1544340276U, // <2,3,1,1>: Cost 2 vext2 LHS, <1,1,1,1> + 1544340374U, // <2,3,1,2>: Cost 2 vext2 LHS, <1,2,3,0> + 1548985304U, // <2,3,1,3>: Cost 2 vext2 LHS, <1,3,1,3> + 2551696694U, // <2,3,1,4>: Cost 3 vext1 <0,2,3,1>, RHS + 1548985488U, // <2,3,1,5>: Cost 2 vext2 LHS, <1,5,3,7> + 2622727375U, // <2,3,1,6>: Cost 3 vext2 LHS, <1,6,1,7> + 2665858347U, // <2,3,1,7>: Cost 3 vext2 LHS, <1,7,3,0> + 1548985709U, // <2,3,1,u>: Cost 2 vext2 LHS, <1,u,1,3> + 2622727613U, // <2,3,2,0>: Cost 3 vext2 LHS, <2,0,1,2> + 2685700406U, // <2,3,2,1>: Cost 3 vext3 <0,2,0,2>, <3,2,1,0> + 1544341096U, // <2,3,2,2>: Cost 2 vext2 LHS, <2,2,2,2> + 1544341158U, // <2,3,2,3>: Cost 2 vext2 LHS, <2,3,0,1> + 2622727958U, // <2,3,2,4>: Cost 3 vext2 LHS, <2,4,3,5> + 2622728032U, // <2,3,2,5>: Cost 3 vext2 LHS, <2,5,2,7> + 1548986298U, // <2,3,2,6>: Cost 2 vext2 LHS, <2,6,3,7> + 2665859050U, // <2,3,2,7>: Cost 3 vext2 LHS, <2,7,0,1> + 1548986427U, // <2,3,2,u>: Cost 2 vext2 LHS, <2,u,0,1> + 1548986518U, // <2,3,3,0>: Cost 2 vext2 LHS, <3,0,1,2> + 2622728422U, // <2,3,3,1>: Cost 3 vext2 LHS, <3,1,1,1> + 1544341814U, // <2,3,3,2>: Cost 2 vext2 LHS, <3,2,1,0> + 1544341916U, // <2,3,3,3>: Cost 2 vext2 LHS, <3,3,3,3> + 1548986882U, // <2,3,3,4>: Cost 2 vext2 LHS, <3,4,5,6> + 2665859632U, // <2,3,3,5>: Cost 3 vext2 LHS, <3,5,1,7> + 2665859704U, // <2,3,3,6>: Cost 3 vext2 LHS, <3,6,0,7> + 2958271632U, // <2,3,3,7>: Cost 3 vzipr LHS, <1,5,3,7> + 1548987164U, // <2,3,3,u>: Cost 2 vext2 LHS, <3,u,1,0> + 1483948134U, // <2,3,4,0>: Cost 2 vext1 <1,2,3,4>, LHS + 1483948954U, // <2,3,4,1>: Cost 2 vext1 <1,2,3,4>, <1,2,3,4> + 2622729276U, // <2,3,4,2>: Cost 3 vext2 LHS, <4,2,6,0> + 2557692054U, // <2,3,4,3>: Cost 3 vext1 <1,2,3,4>, <3,0,1,2> + 1483951414U, // <2,3,4,4>: Cost 2 vext1 <1,2,3,4>, RHS + 470601014U, // <2,3,4,5>: Cost 1 vext2 LHS, RHS + 1592118644U, // <2,3,4,6>: Cost 2 vext2 LHS, <4,6,4,6> + 2593526960U, // <2,3,4,7>: Cost 3 vext1 <7,2,3,4>, <7,2,3,4> + 470601257U, // <2,3,4,u>: Cost 1 vext2 LHS, RHS + 2551726182U, // <2,3,5,0>: Cost 3 vext1 <0,2,3,5>, LHS + 1592118992U, // <2,3,5,1>: Cost 2 vext2 LHS, <5,1,7,3> + 2665860862U, // <2,3,5,2>: Cost 3 vext2 LHS, <5,2,3,4> + 2551728642U, // <2,3,5,3>: Cost 3 vext1 <0,2,3,5>, <3,4,5,6> + 2551729462U, // <2,3,5,4>: Cost 3 vext1 <0,2,3,5>, RHS + 1592119300U, // <2,3,5,5>: Cost 2 vext2 LHS, <5,5,5,5> + 1592119394U, // <2,3,5,6>: Cost 2 vext2 LHS, <5,6,7,0> + 1592119464U, // <2,3,5,7>: Cost 2 vext2 LHS, <5,7,5,7> + 1592119545U, // <2,3,5,u>: Cost 2 vext2 LHS, <5,u,5,7> + 2622730529U, // <2,3,6,0>: Cost 3 vext2 LHS, <6,0,1,2> + 2557707164U, // <2,3,6,1>: Cost 3 vext1 <1,2,3,6>, <1,2,3,6> + 1592119802U, // <2,3,6,2>: Cost 2 vext2 LHS, <6,2,7,3> + 2665861682U, // <2,3,6,3>: Cost 3 vext2 LHS, <6,3,4,5> + 2622730860U, // <2,3,6,4>: Cost 3 vext2 LHS, <6,4,2,0> + 2665861810U, // <2,3,6,5>: Cost 3 vext2 LHS, <6,5,0,7> + 1592120120U, // <2,3,6,6>: Cost 2 vext2 LHS, <6,6,6,6> + 1592120142U, // <2,3,6,7>: Cost 2 vext2 LHS, <6,7,0,1> + 1592120223U, // <2,3,6,u>: Cost 2 vext2 LHS, <6,u,0,1> + 1592120314U, // <2,3,7,0>: Cost 2 vext2 LHS, <7,0,1,2> + 2659890261U, // <2,3,7,1>: Cost 3 vext2 <7,1,2,3>, <7,1,2,3> + 2660553894U, // <2,3,7,2>: Cost 3 vext2 <7,2,2,3>, <7,2,2,3> + 2665862371U, // <2,3,7,3>: Cost 3 vext2 LHS, <7,3,0,1> + 1592120678U, // <2,3,7,4>: Cost 2 vext2 LHS, <7,4,5,6> + 2665862534U, // <2,3,7,5>: Cost 3 vext2 LHS, <7,5,0,2> + 1592120838U, // <2,3,7,6>: Cost 2 vext2 LHS, <7,6,5,4> + 1592120940U, // <2,3,7,7>: Cost 2 vext2 LHS, <7,7,7,7> + 1592120962U, // <2,3,7,u>: Cost 2 vext2 LHS, <7,u,1,2> + 1548990163U, // <2,3,u,0>: Cost 2 vext2 LHS, + 470603566U, // <2,3,u,1>: Cost 1 vext2 LHS, LHS + 1548990323U, // <2,3,u,2>: Cost 2 vext2 LHS, + 1548990396U, // <2,3,u,3>: Cost 2 vext2 LHS, + 1548990527U, // <2,3,u,4>: Cost 2 vext2 LHS, + 470603930U, // <2,3,u,5>: Cost 1 vext2 LHS, RHS + 1548990672U, // <2,3,u,6>: Cost 2 vext2 LHS, + 1592121600U, // <2,3,u,7>: Cost 2 vext2 LHS, + 470604133U, // <2,3,u,u>: Cost 1 vext2 LHS, LHS + 2587590758U, // <2,4,0,0>: Cost 3 vext1 <6,2,4,0>, LHS + 2618753126U, // <2,4,0,1>: Cost 3 vext2 <0,2,2,4>, LHS + 2618753208U, // <2,4,0,2>: Cost 3 vext2 <0,2,2,4>, <0,2,2,4> + 2232821937U, // <2,4,0,3>: Cost 3 vrev <3,0,4,2> + 2587594038U, // <2,4,0,4>: Cost 3 vext1 <6,2,4,0>, RHS + 2712832914U, // <2,4,0,5>: Cost 3 vext3 <4,6,u,2>, <4,0,5,1> + 1634962332U, // <2,4,0,6>: Cost 2 vext3 <4,0,6,2>, <4,0,6,2> + 2256712725U, // <2,4,0,7>: Cost 3 vrev <7,0,4,2> + 1634962332U, // <2,4,0,u>: Cost 2 vext3 <4,0,6,2>, <4,0,6,2> + 3697140463U, // <2,4,1,0>: Cost 4 vext2 <1,0,2,4>, <1,0,2,4> + 3692495668U, // <2,4,1,1>: Cost 4 vext2 <0,2,2,4>, <1,1,1,1> + 2625389466U, // <2,4,1,2>: Cost 3 vext2 <1,3,2,4>, <1,2,3,4> + 2826125414U, // <2,4,1,3>: Cost 3 vuzpr <1,2,3,4>, LHS + 3699794995U, // <2,4,1,4>: Cost 4 vext2 <1,4,2,4>, <1,4,2,4> + 3692496016U, // <2,4,1,5>: Cost 4 vext2 <0,2,2,4>, <1,5,3,7> + 3763424238U, // <2,4,1,6>: Cost 4 vext3 <0,u,0,2>, <4,1,6,3> + 3331118182U, // <2,4,1,7>: Cost 4 vrev <7,1,4,2> + 2826125419U, // <2,4,1,u>: Cost 3 vuzpr <1,2,3,4>, LHS + 2629371336U, // <2,4,2,0>: Cost 3 vext2 <2,0,2,4>, <2,0,2,4> + 3699131946U, // <2,4,2,1>: Cost 4 vext2 <1,3,2,4>, <2,1,4,3> + 2630698602U, // <2,4,2,2>: Cost 3 vext2 <2,2,2,4>, <2,2,2,4> + 2618754766U, // <2,4,2,3>: Cost 3 vext2 <0,2,2,4>, <2,3,4,5> + 2826126234U, // <2,4,2,4>: Cost 3 vuzpr <1,2,3,4>, <1,2,3,4> + 2899119414U, // <2,4,2,5>: Cost 3 vzipl <2,2,2,2>, RHS + 3033337142U, // <2,4,2,6>: Cost 3 vtrnl <2,2,2,2>, RHS + 3800214597U, // <2,4,2,7>: Cost 4 vext3 <7,0,4,2>, <4,2,7,0> + 2899119657U, // <2,4,2,u>: Cost 3 vzipl <2,2,2,2>, RHS + 2635344033U, // <2,4,3,0>: Cost 3 vext2 <3,0,2,4>, <3,0,2,4> + 4032012325U, // <2,4,3,1>: Cost 4 vzipr LHS, <0,0,4,1> + 3692497206U, // <2,4,3,2>: Cost 4 vext2 <0,2,2,4>, <3,2,1,0> + 3692497308U, // <2,4,3,3>: Cost 4 vext2 <0,2,2,4>, <3,3,3,3> + 3001404624U, // <2,4,3,4>: Cost 3 vzipr LHS, <4,4,4,4> + 2953627342U, // <2,4,3,5>: Cost 3 vzipr LHS, <2,3,4,5> + 2953625804U, // <2,4,3,6>: Cost 3 vzipr LHS, <0,2,4,6> + 3899868160U, // <2,4,3,7>: Cost 4 vuzpr <1,2,3,4>, <1,3,5,7> + 2953625806U, // <2,4,3,u>: Cost 3 vzipr LHS, <0,2,4,u> + 2710916266U, // <2,4,4,0>: Cost 3 vext3 <4,4,0,2>, <4,4,0,2> + 3899869648U, // <2,4,4,1>: Cost 4 vuzpr <1,2,3,4>, <3,4,0,1> + 3692497944U, // <2,4,4,2>: Cost 4 vext2 <0,2,2,4>, <4,2,2,0> + 3899868930U, // <2,4,4,3>: Cost 4 vuzpr <1,2,3,4>, <2,4,1,3> + 2712833232U, // <2,4,4,4>: Cost 3 vext3 <4,6,u,2>, <4,4,4,4> + 2618756406U, // <2,4,4,5>: Cost 3 vext2 <0,2,2,4>, RHS + 2765737270U, // <2,4,4,6>: Cost 3 vuzpl <2,3,4,5>, RHS + 4168304426U, // <2,4,4,7>: Cost 4 vtrnr <1,2,3,4>, <2,4,5,7> + 2618756649U, // <2,4,4,u>: Cost 3 vext2 <0,2,2,4>, RHS + 2551800011U, // <2,4,5,0>: Cost 3 vext1 <0,2,4,5>, <0,2,4,5> + 2557772708U, // <2,4,5,1>: Cost 3 vext1 <1,2,4,5>, <1,2,4,5> + 2563745405U, // <2,4,5,2>: Cost 3 vext1 <2,2,4,5>, <2,2,4,5> + 2557773974U, // <2,4,5,3>: Cost 3 vext1 <1,2,4,5>, <3,0,1,2> + 2551803190U, // <2,4,5,4>: Cost 3 vext1 <0,2,4,5>, RHS + 3625545619U, // <2,4,5,5>: Cost 4 vext1 <0,2,4,5>, <5,4,2,0> + 1611959606U, // <2,4,5,6>: Cost 2 vext3 <0,2,0,2>, RHS + 2826128694U, // <2,4,5,7>: Cost 3 vuzpr <1,2,3,4>, RHS + 1611959624U, // <2,4,5,u>: Cost 2 vext3 <0,2,0,2>, RHS + 1478066278U, // <2,4,6,0>: Cost 2 vext1 <0,2,4,6>, LHS + 2551808820U, // <2,4,6,1>: Cost 3 vext1 <0,2,4,6>, <1,1,1,1> + 2551809640U, // <2,4,6,2>: Cost 3 vext1 <0,2,4,6>, <2,2,2,2> + 2551810198U, // <2,4,6,3>: Cost 3 vext1 <0,2,4,6>, <3,0,1,2> + 1478069558U, // <2,4,6,4>: Cost 2 vext1 <0,2,4,6>, RHS + 2901888310U, // <2,4,6,5>: Cost 3 vzipl <2,6,3,7>, RHS + 2551812716U, // <2,4,6,6>: Cost 3 vext1 <0,2,4,6>, <6,4,2,0> + 2726251914U, // <2,4,6,7>: Cost 3 vext3 <7,0,1,2>, <4,6,7,1> + 1478072110U, // <2,4,6,u>: Cost 2 vext1 <0,2,4,6>, LHS + 2659234821U, // <2,4,7,0>: Cost 3 vext2 <7,0,2,4>, <7,0,2,4> + 3786722726U, // <2,4,7,1>: Cost 4 vext3 <4,7,1,2>, <4,7,1,2> + 3734303911U, // <2,4,7,2>: Cost 4 vext2 <7,2,2,4>, <7,2,2,4> + 3734967544U, // <2,4,7,3>: Cost 4 vext2 <7,3,2,4>, <7,3,2,4> + 3727005030U, // <2,4,7,4>: Cost 4 vext2 <6,0,2,4>, <7,4,5,6> + 2726251976U, // <2,4,7,5>: Cost 3 vext3 <7,0,1,2>, <4,7,5,0> + 2726251986U, // <2,4,7,6>: Cost 3 vext3 <7,0,1,2>, <4,7,6,1> + 3727005292U, // <2,4,7,7>: Cost 4 vext2 <6,0,2,4>, <7,7,7,7> + 2726252003U, // <2,4,7,u>: Cost 3 vext3 <7,0,1,2>, <4,7,u,0> + 1478082662U, // <2,4,u,0>: Cost 2 vext1 <0,2,4,u>, LHS + 2618758958U, // <2,4,u,1>: Cost 3 vext2 <0,2,2,4>, LHS + 2551826024U, // <2,4,u,2>: Cost 3 vext1 <0,2,4,u>, <2,2,2,2> + 2551826582U, // <2,4,u,3>: Cost 3 vext1 <0,2,4,u>, <3,0,1,2> + 1478085942U, // <2,4,u,4>: Cost 2 vext1 <0,2,4,u>, RHS + 2953668302U, // <2,4,u,5>: Cost 3 vzipr LHS, <2,3,4,5> + 1611959849U, // <2,4,u,6>: Cost 2 vext3 <0,2,0,2>, RHS + 2826128937U, // <2,4,u,7>: Cost 3 vuzpr <1,2,3,4>, RHS + 1611959867U, // <2,4,u,u>: Cost 2 vext3 <0,2,0,2>, RHS + 3691839488U, // <2,5,0,0>: Cost 4 vext2 <0,1,2,5>, <0,0,0,0> + 2618097766U, // <2,5,0,1>: Cost 3 vext2 <0,1,2,5>, LHS + 2620088484U, // <2,5,0,2>: Cost 3 vext2 <0,4,2,5>, <0,2,0,2> + 2619425034U, // <2,5,0,3>: Cost 3 vext2 <0,3,2,5>, <0,3,2,5> + 2620088667U, // <2,5,0,4>: Cost 3 vext2 <0,4,2,5>, <0,4,2,5> + 2620752300U, // <2,5,0,5>: Cost 3 vext2 <0,5,2,5>, <0,5,2,5> + 3693830655U, // <2,5,0,6>: Cost 4 vext2 <0,4,2,5>, <0,6,2,7> + 3094531382U, // <2,5,0,7>: Cost 3 vtrnr <1,2,3,0>, RHS + 2618098333U, // <2,5,0,u>: Cost 3 vext2 <0,1,2,5>, LHS + 3631554662U, // <2,5,1,0>: Cost 4 vext1 <1,2,5,1>, LHS + 3691840308U, // <2,5,1,1>: Cost 4 vext2 <0,1,2,5>, <1,1,1,1> + 2626061206U, // <2,5,1,2>: Cost 3 vext2 <1,4,2,5>, <1,2,3,0> + 2618098688U, // <2,5,1,3>: Cost 3 vext2 <0,1,2,5>, <1,3,5,7> + 2626061364U, // <2,5,1,4>: Cost 3 vext2 <1,4,2,5>, <1,4,2,5> + 3691840656U, // <2,5,1,5>: Cost 4 vext2 <0,1,2,5>, <1,5,3,7> + 3711747270U, // <2,5,1,6>: Cost 4 vext2 <3,4,2,5>, <1,6,0,7> + 2712833744U, // <2,5,1,7>: Cost 3 vext3 <4,6,u,2>, <5,1,7,3> + 2628715896U, // <2,5,1,u>: Cost 3 vext2 <1,u,2,5>, <1,u,2,5> + 3693831613U, // <2,5,2,0>: Cost 4 vext2 <0,4,2,5>, <2,0,1,2> + 3711747587U, // <2,5,2,1>: Cost 4 vext2 <3,4,2,5>, <2,1,0,0> + 2632033896U, // <2,5,2,2>: Cost 3 vext2 <2,4,2,5>, <2,2,2,2> + 3691841190U, // <2,5,2,3>: Cost 4 vext2 <0,1,2,5>, <2,3,0,1> + 2632034061U, // <2,5,2,4>: Cost 3 vext2 <2,4,2,5>, <2,4,2,5> + 3691841352U, // <2,5,2,5>: Cost 4 vext2 <0,1,2,5>, <2,5,0,1> + 3691841466U, // <2,5,2,6>: Cost 4 vext2 <0,1,2,5>, <2,6,3,7> + 3088354614U, // <2,5,2,7>: Cost 3 vtrnr <0,2,0,2>, RHS + 3088354615U, // <2,5,2,u>: Cost 3 vtrnr <0,2,0,2>, RHS + 2557829222U, // <2,5,3,0>: Cost 3 vext1 <1,2,5,3>, LHS + 2557830059U, // <2,5,3,1>: Cost 3 vext1 <1,2,5,3>, <1,2,5,3> + 2638006582U, // <2,5,3,2>: Cost 3 vext2 <3,4,2,5>, <3,2,1,0> + 3691841948U, // <2,5,3,3>: Cost 4 vext2 <0,1,2,5>, <3,3,3,3> + 2619427330U, // <2,5,3,4>: Cost 3 vext2 <0,3,2,5>, <3,4,5,6> + 2581720847U, // <2,5,3,5>: Cost 3 vext1 <5,2,5,3>, <5,2,5,3> + 2953628162U, // <2,5,3,6>: Cost 3 vzipr LHS, <3,4,5,6> + 2953626624U, // <2,5,3,7>: Cost 3 vzipr LHS, <1,3,5,7> + 2953626625U, // <2,5,3,u>: Cost 3 vzipr LHS, <1,3,5,u> + 3631579238U, // <2,5,4,0>: Cost 4 vext1 <1,2,5,4>, LHS + 3631580076U, // <2,5,4,1>: Cost 4 vext1 <1,2,5,4>, <1,2,5,4> + 3693833267U, // <2,5,4,2>: Cost 4 vext2 <0,4,2,5>, <4,2,5,0> + 2235550206U, // <2,5,4,3>: Cost 3 vrev <3,4,5,2> + 3631582518U, // <2,5,4,4>: Cost 4 vext1 <1,2,5,4>, RHS + 2618101046U, // <2,5,4,5>: Cost 3 vext2 <0,1,2,5>, RHS + 3893905922U, // <2,5,4,6>: Cost 4 vuzpr <0,2,3,5>, <3,4,5,6> + 3094564150U, // <2,5,4,7>: Cost 3 vtrnr <1,2,3,4>, RHS + 2618101289U, // <2,5,4,u>: Cost 3 vext2 <0,1,2,5>, RHS + 2551873638U, // <2,5,5,0>: Cost 3 vext1 <0,2,5,5>, LHS + 3637560320U, // <2,5,5,1>: Cost 4 vext1 <2,2,5,5>, <1,3,5,7> + 3691843304U, // <2,5,5,2>: Cost 4 vext2 <0,1,2,5>, <5,2,1,0> + 3309955663U, // <2,5,5,3>: Cost 4 vrev <3,5,5,2> + 2551876918U, // <2,5,5,4>: Cost 3 vext1 <0,2,5,5>, RHS + 2712834052U, // <2,5,5,5>: Cost 3 vext3 <4,6,u,2>, <5,5,5,5> + 4028713474U, // <2,5,5,6>: Cost 4 vzipr <0,3,2,5>, <3,4,5,6> + 2712834072U, // <2,5,5,7>: Cost 3 vext3 <4,6,u,2>, <5,5,7,7> + 2712834081U, // <2,5,5,u>: Cost 3 vext3 <4,6,u,2>, <5,5,u,7> + 2575769702U, // <2,5,6,0>: Cost 3 vext1 <4,2,5,6>, LHS + 3631596462U, // <2,5,6,1>: Cost 4 vext1 <1,2,5,6>, <1,2,5,6> + 2655924730U, // <2,5,6,2>: Cost 3 vext2 <6,4,2,5>, <6,2,7,3> + 3643541856U, // <2,5,6,3>: Cost 4 vext1 <3,2,5,6>, <3,2,5,6> + 2655924849U, // <2,5,6,4>: Cost 3 vext2 <6,4,2,5>, <6,4,2,5> + 3787755607U, // <2,5,6,5>: Cost 4 vext3 <4,u,6,2>, <5,6,5,7> + 4029385218U, // <2,5,6,6>: Cost 4 vzipr <0,4,2,6>, <3,4,5,6> + 3088682294U, // <2,5,6,7>: Cost 3 vtrnr <0,2,4,6>, RHS + 3088682295U, // <2,5,6,u>: Cost 3 vtrnr <0,2,4,6>, RHS + 2563833958U, // <2,5,7,0>: Cost 3 vext1 <2,2,5,7>, LHS + 3769766016U, // <2,5,7,1>: Cost 4 vext3 <1,u,5,2>, <5,7,1,3> + 2563835528U, // <2,5,7,2>: Cost 3 vext1 <2,2,5,7>, <2,2,5,7> + 2551892118U, // <2,5,7,3>: Cost 3 vext1 <0,2,5,7>, <3,0,1,2> + 2563837238U, // <2,5,7,4>: Cost 3 vext1 <2,2,5,7>, RHS + 2712834216U, // <2,5,7,5>: Cost 3 vext3 <4,6,u,2>, <5,7,5,7> + 2712834220U, // <2,5,7,6>: Cost 3 vext3 <4,6,u,2>, <5,7,6,2> + 3637581208U, // <2,5,7,7>: Cost 4 vext1 <2,2,5,7>, <7,5,2,2> + 2563839790U, // <2,5,7,u>: Cost 3 vext1 <2,2,5,7>, LHS + 2563842150U, // <2,5,u,0>: Cost 3 vext1 <2,2,5,u>, LHS + 2618103598U, // <2,5,u,1>: Cost 3 vext2 <0,1,2,5>, LHS + 2563843721U, // <2,5,u,2>: Cost 3 vext1 <2,2,5,u>, <2,2,5,u> + 2238204738U, // <2,5,u,3>: Cost 3 vrev <3,u,5,2> + 2622748735U, // <2,5,u,4>: Cost 3 vext2 <0,u,2,5>, + 2618103962U, // <2,5,u,5>: Cost 3 vext2 <0,1,2,5>, RHS + 2953669122U, // <2,5,u,6>: Cost 3 vzipr LHS, <3,4,5,6> + 2953667584U, // <2,5,u,7>: Cost 3 vzipr LHS, <1,3,5,7> + 2618104165U, // <2,5,u,u>: Cost 3 vext2 <0,1,2,5>, LHS + 2620096512U, // <2,6,0,0>: Cost 3 vext2 <0,4,2,6>, <0,0,0,0> + 1546354790U, // <2,6,0,1>: Cost 2 vext2 <0,4,2,6>, LHS + 2620096676U, // <2,6,0,2>: Cost 3 vext2 <0,4,2,6>, <0,2,0,2> + 3693838588U, // <2,6,0,3>: Cost 4 vext2 <0,4,2,6>, <0,3,1,0> + 1546355036U, // <2,6,0,4>: Cost 2 vext2 <0,4,2,6>, <0,4,2,6> + 3694502317U, // <2,6,0,5>: Cost 4 vext2 <0,5,2,6>, <0,5,2,6> + 2551911246U, // <2,6,0,6>: Cost 3 vext1 <0,2,6,0>, <6,7,0,1> + 2720723287U, // <2,6,0,7>: Cost 3 vext3 <6,0,7,2>, <6,0,7,2> + 1546355357U, // <2,6,0,u>: Cost 2 vext2 <0,4,2,6>, LHS + 3693839092U, // <2,6,1,0>: Cost 4 vext2 <0,4,2,6>, <1,0,3,0> + 2620097332U, // <2,6,1,1>: Cost 3 vext2 <0,4,2,6>, <1,1,1,1> + 2620097430U, // <2,6,1,2>: Cost 3 vext2 <0,4,2,6>, <1,2,3,0> + 2820243558U, // <2,6,1,3>: Cost 3 vuzpr <0,2,4,6>, LHS + 2620097598U, // <2,6,1,4>: Cost 3 vext2 <0,4,2,6>, <1,4,3,6> + 2620097680U, // <2,6,1,5>: Cost 3 vext2 <0,4,2,6>, <1,5,3,7> + 3693839585U, // <2,6,1,6>: Cost 4 vext2 <0,4,2,6>, <1,6,3,7> + 2721386920U, // <2,6,1,7>: Cost 3 vext3 <6,1,7,2>, <6,1,7,2> + 2820243563U, // <2,6,1,u>: Cost 3 vuzpr <0,2,4,6>, LHS + 2714014137U, // <2,6,2,0>: Cost 3 vext3 <4,u,6,2>, <6,2,0,1> + 2712834500U, // <2,6,2,1>: Cost 3 vext3 <4,6,u,2>, <6,2,1,3> + 2620098152U, // <2,6,2,2>: Cost 3 vext2 <0,4,2,6>, <2,2,2,2> + 2620098214U, // <2,6,2,3>: Cost 3 vext2 <0,4,2,6>, <2,3,0,1> + 2632042254U, // <2,6,2,4>: Cost 3 vext2 <2,4,2,6>, <2,4,2,6> + 2712834540U, // <2,6,2,5>: Cost 3 vext3 <4,6,u,2>, <6,2,5,7> + 2820243660U, // <2,6,2,6>: Cost 3 vuzpr <0,2,4,6>, <0,2,4,6> + 2958265654U, // <2,6,2,7>: Cost 3 vzipr <0,u,2,2>, RHS + 2620098619U, // <2,6,2,u>: Cost 3 vext2 <0,4,2,6>, <2,u,0,1> + 2620098710U, // <2,6,3,0>: Cost 3 vext2 <0,4,2,6>, <3,0,1,2> + 3893986982U, // <2,6,3,1>: Cost 4 vuzpr <0,2,4,6>, <2,3,0,1> + 2620098870U, // <2,6,3,2>: Cost 3 vext2 <0,4,2,6>, <3,2,1,0> + 2620098972U, // <2,6,3,3>: Cost 3 vext2 <0,4,2,6>, <3,3,3,3> + 2620099074U, // <2,6,3,4>: Cost 3 vext2 <0,4,2,6>, <3,4,5,6> + 3893987022U, // <2,6,3,5>: Cost 4 vuzpr <0,2,4,6>, <2,3,4,5> + 3001404644U, // <2,6,3,6>: Cost 3 vzipr LHS, <4,4,6,6> + 1879887158U, // <2,6,3,7>: Cost 2 vzipr LHS, RHS + 1879887159U, // <2,6,3,u>: Cost 2 vzipr LHS, RHS + 2575827046U, // <2,6,4,0>: Cost 3 vext1 <4,2,6,4>, LHS + 2620099566U, // <2,6,4,1>: Cost 3 vext2 <0,4,2,6>, <4,1,6,3> + 2620099644U, // <2,6,4,2>: Cost 3 vext2 <0,4,2,6>, <4,2,6,0> + 3643599207U, // <2,6,4,3>: Cost 4 vext1 <3,2,6,4>, <3,2,6,4> + 2575830080U, // <2,6,4,4>: Cost 3 vext1 <4,2,6,4>, <4,2,6,4> + 1546358070U, // <2,6,4,5>: Cost 2 vext2 <0,4,2,6>, RHS + 2667875700U, // <2,6,4,6>: Cost 3 vext2 , <4,6,4,6> + 4028042550U, // <2,6,4,7>: Cost 4 vzipr <0,2,2,4>, RHS + 1546358313U, // <2,6,4,u>: Cost 2 vext2 <0,4,2,6>, RHS + 3693841992U, // <2,6,5,0>: Cost 4 vext2 <0,4,2,6>, <5,0,1,2> + 2667876048U, // <2,6,5,1>: Cost 3 vext2 , <5,1,7,3> + 2712834756U, // <2,6,5,2>: Cost 3 vext3 <4,6,u,2>, <6,5,2,7> + 3643607400U, // <2,6,5,3>: Cost 4 vext1 <3,2,6,5>, <3,2,6,5> + 3693842356U, // <2,6,5,4>: Cost 4 vext2 <0,4,2,6>, <5,4,5,6> + 2667876356U, // <2,6,5,5>: Cost 3 vext2 , <5,5,5,5> + 2667876450U, // <2,6,5,6>: Cost 3 vext2 , <5,6,7,0> + 2820246838U, // <2,6,5,7>: Cost 3 vuzpr <0,2,4,6>, RHS + 2820246839U, // <2,6,5,u>: Cost 3 vuzpr <0,2,4,6>, RHS + 2563899494U, // <2,6,6,0>: Cost 3 vext1 <2,2,6,6>, LHS + 3893988683U, // <2,6,6,1>: Cost 4 vuzpr <0,2,4,6>, <4,6,0,1> + 2620101084U, // <2,6,6,2>: Cost 3 vext2 <0,4,2,6>, <6,2,4,0> + 3893987236U, // <2,6,6,3>: Cost 4 vuzpr <0,2,4,6>, <2,6,1,3> + 2563902774U, // <2,6,6,4>: Cost 3 vext1 <2,2,6,6>, RHS + 3893988723U, // <2,6,6,5>: Cost 4 vuzpr <0,2,4,6>, <4,6,4,5> + 2712834872U, // <2,6,6,6>: Cost 3 vext3 <4,6,u,2>, <6,6,6,6> + 2955644214U, // <2,6,6,7>: Cost 3 vzipr <0,4,2,6>, RHS + 2955644215U, // <2,6,6,u>: Cost 3 vzipr <0,4,2,6>, RHS + 2712834894U, // <2,6,7,0>: Cost 3 vext3 <4,6,u,2>, <6,7,0,1> + 2724926296U, // <2,6,7,1>: Cost 3 vext3 <6,7,1,2>, <6,7,1,2> + 2725000033U, // <2,6,7,2>: Cost 3 vext3 <6,7,2,2>, <6,7,2,2> + 2725073770U, // <2,6,7,3>: Cost 3 vext3 <6,7,3,2>, <6,7,3,2> + 2712834934U, // <2,6,7,4>: Cost 3 vext3 <4,6,u,2>, <6,7,4,5> + 3776107393U, // <2,6,7,5>: Cost 4 vext3 <3,0,1,2>, <6,7,5,7> + 2255532933U, // <2,6,7,6>: Cost 3 vrev <6,7,6,2> + 2726253452U, // <2,6,7,7>: Cost 3 vext3 <7,0,1,2>, <6,7,7,0> + 2712834966U, // <2,6,7,u>: Cost 3 vext3 <4,6,u,2>, <6,7,u,1> + 2620102355U, // <2,6,u,0>: Cost 3 vext2 <0,4,2,6>, + 1546360622U, // <2,6,u,1>: Cost 2 vext2 <0,4,2,6>, LHS + 2620102515U, // <2,6,u,2>: Cost 3 vext2 <0,4,2,6>, + 2820244125U, // <2,6,u,3>: Cost 3 vuzpr <0,2,4,6>, LHS + 1594136612U, // <2,6,u,4>: Cost 2 vext2 , + 1546360986U, // <2,6,u,5>: Cost 2 vext2 <0,4,2,6>, RHS + 2620102864U, // <2,6,u,6>: Cost 3 vext2 <0,4,2,6>, + 1879928118U, // <2,6,u,7>: Cost 2 vzipr LHS, RHS + 1879928119U, // <2,6,u,u>: Cost 2 vzipr LHS, RHS + 2726179825U, // <2,7,0,0>: Cost 3 vext3 <7,0,0,2>, <7,0,0,2> + 1652511738U, // <2,7,0,1>: Cost 2 vext3 <7,0,1,2>, <7,0,1,2> + 2621431972U, // <2,7,0,2>: Cost 3 vext2 <0,6,2,7>, <0,2,0,2> + 3693183244U, // <2,7,0,3>: Cost 4 vext2 <0,3,2,7>, <0,3,2,7> + 2726474773U, // <2,7,0,4>: Cost 3 vext3 <7,0,4,2>, <7,0,4,2> + 2620768686U, // <2,7,0,5>: Cost 3 vext2 <0,5,2,7>, <0,5,2,7> + 2621432319U, // <2,7,0,6>: Cost 3 vext2 <0,6,2,7>, <0,6,2,7> + 2599760953U, // <2,7,0,7>: Cost 3 vext1 , <7,0,u,2> + 1653027897U, // <2,7,0,u>: Cost 2 vext3 <7,0,u,2>, <7,0,u,2> + 2726843458U, // <2,7,1,0>: Cost 3 vext3 <7,1,0,2>, <7,1,0,2> + 3695174452U, // <2,7,1,1>: Cost 4 vext2 <0,6,2,7>, <1,1,1,1> + 3695174550U, // <2,7,1,2>: Cost 4 vext2 <0,6,2,7>, <1,2,3,0> + 3694511104U, // <2,7,1,3>: Cost 4 vext2 <0,5,2,7>, <1,3,5,7> + 2599767350U, // <2,7,1,4>: Cost 3 vext1 , RHS + 3693184144U, // <2,7,1,5>: Cost 4 vext2 <0,3,2,7>, <1,5,3,7> + 2627405016U, // <2,7,1,6>: Cost 3 vext2 <1,6,2,7>, <1,6,2,7> + 2599769082U, // <2,7,1,7>: Cost 3 vext1 , <7,0,1,2> + 2599769902U, // <2,7,1,u>: Cost 3 vext1 , LHS + 3695175101U, // <2,7,2,0>: Cost 4 vext2 <0,6,2,7>, <2,0,1,2> + 3643655168U, // <2,7,2,1>: Cost 4 vext1 <3,2,7,2>, <1,3,5,7> + 2727654565U, // <2,7,2,2>: Cost 3 vext3 <7,2,2,2>, <7,2,2,2> + 3695175334U, // <2,7,2,3>: Cost 4 vext2 <0,6,2,7>, <2,3,0,1> + 3695175465U, // <2,7,2,4>: Cost 4 vext2 <0,6,2,7>, <2,4,5,6> + 2632714080U, // <2,7,2,5>: Cost 3 vext2 <2,5,2,7>, <2,5,2,7> + 2633377713U, // <2,7,2,6>: Cost 3 vext2 <2,6,2,7>, <2,6,2,7> + 3695175658U, // <2,7,2,7>: Cost 4 vext2 <0,6,2,7>, <2,7,0,1> + 2634704979U, // <2,7,2,u>: Cost 3 vext2 <2,u,2,7>, <2,u,2,7> + 1514094694U, // <2,7,3,0>: Cost 2 vext1 <6,2,7,3>, LHS + 2569921680U, // <2,7,3,1>: Cost 3 vext1 <3,2,7,3>, <1,5,3,7> + 2587838056U, // <2,7,3,2>: Cost 3 vext1 <6,2,7,3>, <2,2,2,2> + 2569922927U, // <2,7,3,3>: Cost 3 vext1 <3,2,7,3>, <3,2,7,3> + 1514097974U, // <2,7,3,4>: Cost 2 vext1 <6,2,7,3>, RHS + 2581868321U, // <2,7,3,5>: Cost 3 vext1 <5,2,7,3>, <5,2,7,3> + 1514099194U, // <2,7,3,6>: Cost 2 vext1 <6,2,7,3>, <6,2,7,3> + 2587841530U, // <2,7,3,7>: Cost 3 vext1 <6,2,7,3>, <7,0,1,2> + 1514100526U, // <2,7,3,u>: Cost 2 vext1 <6,2,7,3>, LHS + 2708706617U, // <2,7,4,0>: Cost 3 vext3 <4,0,6,2>, <7,4,0,6> + 3649643418U, // <2,7,4,1>: Cost 4 vext1 <4,2,7,4>, <1,2,3,4> + 3649644330U, // <2,7,4,2>: Cost 4 vext1 <4,2,7,4>, <2,4,5,7> + 3802797392U, // <2,7,4,3>: Cost 4 vext3 <7,4,3,2>, <7,4,3,2> + 3649645641U, // <2,7,4,4>: Cost 4 vext1 <4,2,7,4>, <4,2,7,4> + 2621435190U, // <2,7,4,5>: Cost 3 vext2 <0,6,2,7>, RHS + 2712835441U, // <2,7,4,6>: Cost 3 vext3 <4,6,u,2>, <7,4,6,u> + 3799995762U, // <2,7,4,7>: Cost 4 vext3 <7,0,1,2>, <7,4,7,0> + 2621435433U, // <2,7,4,u>: Cost 3 vext2 <0,6,2,7>, RHS + 2729497990U, // <2,7,5,0>: Cost 3 vext3 <7,5,0,2>, <7,5,0,2> + 3643679744U, // <2,7,5,1>: Cost 4 vext1 <3,2,7,5>, <1,3,5,7> + 3706457886U, // <2,7,5,2>: Cost 4 vext2 <2,5,2,7>, <5,2,7,0> + 3769767328U, // <2,7,5,3>: Cost 4 vext3 <1,u,5,2>, <7,5,3,1> + 2599800118U, // <2,7,5,4>: Cost 3 vext1 , RHS + 3786577334U, // <2,7,5,5>: Cost 4 vext3 <4,6,u,2>, <7,5,5,5> + 3786577345U, // <2,7,5,6>: Cost 4 vext3 <4,6,u,2>, <7,5,6,7> + 2599802214U, // <2,7,5,7>: Cost 3 vext1 , <7,4,5,6> + 2599802670U, // <2,7,5,u>: Cost 3 vext1 , LHS + 2581889126U, // <2,7,6,0>: Cost 3 vext1 <5,2,7,6>, LHS + 3643687936U, // <2,7,6,1>: Cost 4 vext1 <3,2,7,6>, <1,3,5,7> + 2663240186U, // <2,7,6,2>: Cost 3 vext2 <7,6,2,7>, <6,2,7,3> + 3975632154U, // <2,7,6,3>: Cost 4 vzipl <2,6,3,7>, <7,3,6,2> + 2581892406U, // <2,7,6,4>: Cost 3 vext1 <5,2,7,6>, RHS + 2712835590U, // <2,7,6,5>: Cost 3 vext3 <4,6,u,2>, <7,6,5,4> + 2587865597U, // <2,7,6,6>: Cost 3 vext1 <6,2,7,6>, <6,2,7,6> + 3786577428U, // <2,7,6,7>: Cost 4 vext3 <4,6,u,2>, <7,6,7,0> + 2581894958U, // <2,7,6,u>: Cost 3 vext1 <5,2,7,6>, LHS + 2726254119U, // <2,7,7,0>: Cost 3 vext3 <7,0,1,2>, <7,7,0,1> + 3804640817U, // <2,7,7,1>: Cost 4 vext3 <7,7,1,2>, <7,7,1,2> + 3695178951U, // <2,7,7,2>: Cost 4 vext2 <0,6,2,7>, <7,2,6,0> + 3734992123U, // <2,7,7,3>: Cost 4 vext2 <7,3,2,7>, <7,3,2,7> + 2552040758U, // <2,7,7,4>: Cost 3 vext1 <0,2,7,7>, RHS + 3323375797U, // <2,7,7,5>: Cost 4 vrev <5,7,7,2> + 2663241198U, // <2,7,7,6>: Cost 3 vext2 <7,6,2,7>, <7,6,2,7> + 2712835692U, // <2,7,7,7>: Cost 3 vext3 <4,6,u,2>, <7,7,7,7> + 2731562607U, // <2,7,7,u>: Cost 3 vext3 <7,u,1,2>, <7,7,u,1> + 1514135654U, // <2,7,u,0>: Cost 2 vext1 <6,2,7,u>, LHS + 1657820802U, // <2,7,u,1>: Cost 2 vext3 <7,u,1,2>, <7,u,1,2> + 2587879016U, // <2,7,u,2>: Cost 3 vext1 <6,2,7,u>, <2,2,2,2> + 2569963892U, // <2,7,u,3>: Cost 3 vext1 <3,2,7,u>, <3,2,7,u> + 1514138934U, // <2,7,u,4>: Cost 2 vext1 <6,2,7,u>, RHS + 2621438106U, // <2,7,u,5>: Cost 3 vext2 <0,6,2,7>, RHS + 1514140159U, // <2,7,u,6>: Cost 2 vext1 <6,2,7,u>, <6,2,7,u> + 2587882490U, // <2,7,u,7>: Cost 3 vext1 <6,2,7,u>, <7,0,1,2> + 1514141486U, // <2,7,u,u>: Cost 2 vext1 <6,2,7,u>, LHS + 1544380416U, // <2,u,0,0>: Cost 2 vext2 LHS, <0,0,0,0> + 470638699U, // <2,u,0,1>: Cost 1 vext2 LHS, LHS + 1544380580U, // <2,u,0,2>: Cost 2 vext2 LHS, <0,2,0,2> + 1159375061U, // <2,u,0,3>: Cost 2 vrev <3,0,u,2> + 1544380754U, // <2,u,0,4>: Cost 2 vext2 LHS, <0,4,1,5> + 2245062279U, // <2,u,0,5>: Cost 3 vrev <5,0,u,2> + 1658853120U, // <2,u,0,6>: Cost 2 vext3 , + 1183265849U, // <2,u,0,7>: Cost 2 vrev <7,0,u,2> + 470639261U, // <2,u,0,u>: Cost 1 vext2 LHS, LHS + 2618122996U, // <2,u,1,0>: Cost 3 vext2 LHS, <1,0,3,0> + 1544381236U, // <2,u,1,1>: Cost 2 vext2 LHS, <1,1,1,1> + 1544381334U, // <2,u,1,2>: Cost 2 vext2 LHS, <1,2,3,0> + 1544381400U, // <2,u,1,3>: Cost 2 vext2 LHS, <1,3,1,3> + 2618123325U, // <2,u,1,4>: Cost 3 vext2 LHS, <1,4,3,5> + 1544381584U, // <2,u,1,5>: Cost 2 vext2 LHS, <1,5,3,7> + 2618123489U, // <2,u,1,6>: Cost 3 vext2 LHS, <1,6,3,7> + 2726254427U, // <2,u,1,7>: Cost 3 vext3 <7,0,1,2>, + 1544381823U, // <2,u,1,u>: Cost 2 vext2 LHS, <1,u,3,3> + 1478328422U, // <2,u,2,0>: Cost 2 vext1 <0,2,u,2>, LHS + 2618123806U, // <2,u,2,1>: Cost 3 vext2 LHS, <2,1,3,0> + 269271142U, // <2,u,2,2>: Cost 1 vdup2 LHS + 1544382118U, // <2,u,2,3>: Cost 2 vext2 LHS, <2,3,0,1> + 1478331702U, // <2,u,2,4>: Cost 2 vext1 <0,2,u,2>, RHS + 2618124136U, // <2,u,2,5>: Cost 3 vext2 LHS, <2,5,3,6> + 1544382394U, // <2,u,2,6>: Cost 2 vext2 LHS, <2,6,3,7> + 3088354857U, // <2,u,2,7>: Cost 3 vtrnr <0,2,0,2>, RHS + 269271142U, // <2,u,2,u>: Cost 1 vdup2 LHS + 1544382614U, // <2,u,3,0>: Cost 2 vext2 LHS, <3,0,1,2> + 2953627374U, // <2,u,3,1>: Cost 3 vzipr LHS, <2,3,u,1> + 1544382774U, // <2,u,3,2>: Cost 2 vext2 LHS, <3,2,1,0> + 1879883932U, // <2,u,3,3>: Cost 2 vzipr LHS, LHS + 1544382978U, // <2,u,3,4>: Cost 2 vext2 LHS, <3,4,5,6> + 2953627378U, // <2,u,3,5>: Cost 3 vzipr LHS, <2,3,u,5> + 1514172931U, // <2,u,3,6>: Cost 2 vext1 <6,2,u,3>, <6,2,u,3> + 1879887176U, // <2,u,3,7>: Cost 2 vzipr LHS, RHS + 1879883937U, // <2,u,3,u>: Cost 2 vzipr LHS, LHS + 1484316774U, // <2,u,4,0>: Cost 2 vext1 <1,2,u,4>, LHS + 1484317639U, // <2,u,4,1>: Cost 2 vext1 <1,2,u,4>, <1,2,u,4> + 2552088270U, // <2,u,4,2>: Cost 3 vext1 <0,2,u,4>, <2,3,4,5> + 3094561437U, // <2,u,4,3>: Cost 3 vtrnr <1,2,3,4>, LHS + 1484320054U, // <2,u,4,4>: Cost 2 vext1 <1,2,u,4>, RHS + 470641974U, // <2,u,4,5>: Cost 1 vext2 LHS, RHS + 1592159604U, // <2,u,4,6>: Cost 2 vext2 LHS, <4,6,4,6> + 3094564393U, // <2,u,4,7>: Cost 3 vtrnr <1,2,3,4>, RHS + 470642217U, // <2,u,4,u>: Cost 1 vext2 LHS, RHS + 2552094959U, // <2,u,5,0>: Cost 3 vext1 <0,2,u,5>, <0,2,u,5> + 1592159952U, // <2,u,5,1>: Cost 2 vext2 LHS, <5,1,7,3> + 2564040353U, // <2,u,5,2>: Cost 3 vext1 <2,2,u,5>, <2,2,u,5> + 2690275455U, // <2,u,5,3>: Cost 3 vext3 <0,u,u,2>, + 2552098102U, // <2,u,5,4>: Cost 3 vext1 <0,2,u,5>, RHS + 1592160260U, // <2,u,5,5>: Cost 2 vext2 LHS, <5,5,5,5> + 1611962522U, // <2,u,5,6>: Cost 2 vext3 <0,2,0,2>, RHS + 1592160424U, // <2,u,5,7>: Cost 2 vext2 LHS, <5,7,5,7> + 1611962540U, // <2,u,5,u>: Cost 2 vext3 <0,2,0,2>, RHS + 1478361190U, // <2,u,6,0>: Cost 2 vext1 <0,2,u,6>, LHS + 2552103732U, // <2,u,6,1>: Cost 3 vext1 <0,2,u,6>, <1,1,1,1> + 1592160762U, // <2,u,6,2>: Cost 2 vext2 LHS, <6,2,7,3> + 2685704400U, // <2,u,6,3>: Cost 3 vext3 <0,2,0,2>, + 1478364470U, // <2,u,6,4>: Cost 2 vext1 <0,2,u,6>, RHS + 2901891226U, // <2,u,6,5>: Cost 3 vzipl <2,6,3,7>, RHS + 1592161080U, // <2,u,6,6>: Cost 2 vext2 LHS, <6,6,6,6> + 1592161102U, // <2,u,6,7>: Cost 2 vext2 LHS, <6,7,0,1> + 1478367022U, // <2,u,6,u>: Cost 2 vext1 <0,2,u,6>, LHS + 1592161274U, // <2,u,7,0>: Cost 2 vext2 LHS, <7,0,1,2> + 2659931226U, // <2,u,7,1>: Cost 3 vext2 <7,1,2,u>, <7,1,2,u> + 2564056739U, // <2,u,7,2>: Cost 3 vext1 <2,2,u,7>, <2,2,u,7> + 2661258492U, // <2,u,7,3>: Cost 3 vext2 <7,3,2,u>, <7,3,2,u> + 1592161638U, // <2,u,7,4>: Cost 2 vext2 LHS, <7,4,5,6> + 2665903494U, // <2,u,7,5>: Cost 3 vext2 LHS, <7,5,0,2> + 1592161798U, // <2,u,7,6>: Cost 2 vext2 LHS, <7,6,5,4> + 1592161900U, // <2,u,7,7>: Cost 2 vext2 LHS, <7,7,7,7> + 1592161922U, // <2,u,7,u>: Cost 2 vext2 LHS, <7,u,1,2> + 1478377574U, // <2,u,u,0>: Cost 2 vext1 <0,2,u,u>, LHS + 470644526U, // <2,u,u,1>: Cost 1 vext2 LHS, LHS + 269271142U, // <2,u,u,2>: Cost 1 vdup2 LHS + 1879924892U, // <2,u,u,3>: Cost 2 vzipr LHS, LHS + 1478380854U, // <2,u,u,4>: Cost 2 vext1 <0,2,u,u>, RHS + 470644890U, // <2,u,u,5>: Cost 1 vext2 LHS, RHS + 1611962765U, // <2,u,u,6>: Cost 2 vext3 <0,2,0,2>, RHS + 1879928136U, // <2,u,u,7>: Cost 2 vzipr LHS, RHS + 470645093U, // <2,u,u,u>: Cost 1 vext2 LHS, LHS + 1611448320U, // <3,0,0,0>: Cost 2 vext3 LHS, <0,0,0,0> + 1611890698U, // <3,0,0,1>: Cost 2 vext3 LHS, <0,0,1,1> + 1611890708U, // <3,0,0,2>: Cost 2 vext3 LHS, <0,0,2,2> + 2624766214U, // <3,0,0,3>: Cost 3 vext2 <1,2,3,0>, <0,3,2,1> + 2689835045U, // <3,0,0,4>: Cost 3 vext3 LHS, <0,0,4,1> + 3731685806U, // <3,0,0,5>: Cost 4 vext2 <6,7,3,0>, <0,5,2,7> + 3763576887U, // <3,0,0,6>: Cost 4 vext3 LHS, <0,0,6,1> + 3667678434U, // <3,0,0,7>: Cost 4 vext1 <7,3,0,0>, <7,3,0,0> + 1616093258U, // <3,0,0,u>: Cost 2 vext3 LHS, <0,0,u,2> + 1490337894U, // <3,0,1,0>: Cost 2 vext1 <2,3,0,1>, LHS + 2685632603U, // <3,0,1,1>: Cost 3 vext3 LHS, <0,1,1,1> + 537706598U, // <3,0,1,2>: Cost 1 vext3 LHS, LHS + 2624766936U, // <3,0,1,3>: Cost 3 vext2 <1,2,3,0>, <1,3,1,3> + 1490341174U, // <3,0,1,4>: Cost 2 vext1 <2,3,0,1>, RHS + 2624767120U, // <3,0,1,5>: Cost 3 vext2 <1,2,3,0>, <1,5,3,7> + 2732966030U, // <3,0,1,6>: Cost 3 vext3 LHS, <0,1,6,7> + 2593944803U, // <3,0,1,7>: Cost 3 vext1 <7,3,0,1>, <7,3,0,1> + 537706652U, // <3,0,1,u>: Cost 1 vext3 LHS, LHS + 1611890852U, // <3,0,2,0>: Cost 2 vext3 LHS, <0,2,0,2> + 2685632684U, // <3,0,2,1>: Cost 3 vext3 LHS, <0,2,1,1> + 2685632692U, // <3,0,2,2>: Cost 3 vext3 LHS, <0,2,2,0> + 2685632702U, // <3,0,2,3>: Cost 3 vext3 LHS, <0,2,3,1> + 1611890892U, // <3,0,2,4>: Cost 2 vext3 LHS, <0,2,4,6> + 2732966102U, // <3,0,2,5>: Cost 3 vext3 LHS, <0,2,5,7> + 2624767930U, // <3,0,2,6>: Cost 3 vext2 <1,2,3,0>, <2,6,3,7> + 2685632744U, // <3,0,2,7>: Cost 3 vext3 LHS, <0,2,7,7> + 1611890924U, // <3,0,2,u>: Cost 2 vext3 LHS, <0,2,u,2> + 2624768150U, // <3,0,3,0>: Cost 3 vext2 <1,2,3,0>, <3,0,1,2> + 2685632764U, // <3,0,3,1>: Cost 3 vext3 LHS, <0,3,1,0> + 2685632774U, // <3,0,3,2>: Cost 3 vext3 LHS, <0,3,2,1> + 2624768412U, // <3,0,3,3>: Cost 3 vext2 <1,2,3,0>, <3,3,3,3> + 2624768514U, // <3,0,3,4>: Cost 3 vext2 <1,2,3,0>, <3,4,5,6> + 3698510384U, // <3,0,3,5>: Cost 4 vext2 <1,2,3,0>, <3,5,1,7> + 2624768632U, // <3,0,3,6>: Cost 3 vext2 <1,2,3,0>, <3,6,0,7> + 3702491843U, // <3,0,3,7>: Cost 4 vext2 <1,u,3,0>, <3,7,0,1> + 2686959934U, // <3,0,3,u>: Cost 3 vext3 <0,3,u,3>, <0,3,u,3> + 2689835336U, // <3,0,4,0>: Cost 3 vext3 LHS, <0,4,0,4> + 1611891026U, // <3,0,4,1>: Cost 2 vext3 LHS, <0,4,1,5> + 1611891036U, // <3,0,4,2>: Cost 2 vext3 LHS, <0,4,2,6> + 3763577184U, // <3,0,4,3>: Cost 4 vext3 LHS, <0,4,3,1> + 2689835374U, // <3,0,4,4>: Cost 3 vext3 LHS, <0,4,4,6> + 1551027510U, // <3,0,4,5>: Cost 2 vext2 <1,2,3,0>, RHS + 2666573172U, // <3,0,4,6>: Cost 3 vext2 , <4,6,4,6> + 3667711206U, // <3,0,4,7>: Cost 4 vext1 <7,3,0,4>, <7,3,0,4> + 1616093586U, // <3,0,4,u>: Cost 2 vext3 LHS, <0,4,u,6> + 2685190556U, // <3,0,5,0>: Cost 3 vext3 LHS, <0,5,0,7> + 2666573520U, // <3,0,5,1>: Cost 3 vext2 , <5,1,7,3> + 3040886886U, // <3,0,5,2>: Cost 3 vtrnl <3,4,5,6>, LHS + 3625912834U, // <3,0,5,3>: Cost 4 vext1 <0,3,0,5>, <3,4,5,6> + 3625913654U, // <3,0,5,4>: Cost 4 vext1 <0,3,0,5>, RHS + 2666573828U, // <3,0,5,5>: Cost 3 vext2 , <5,5,5,5> + 2732966354U, // <3,0,5,6>: Cost 3 vext3 LHS, <0,5,6,7> + 2666573992U, // <3,0,5,7>: Cost 3 vext2 , <5,7,5,7> + 3040886940U, // <3,0,5,u>: Cost 3 vtrnl <3,4,5,6>, LHS + 2685190637U, // <3,0,6,0>: Cost 3 vext3 LHS, <0,6,0,7> + 2732966390U, // <3,0,6,1>: Cost 3 vext3 LHS, <0,6,1,7> + 2689835519U, // <3,0,6,2>: Cost 3 vext3 LHS, <0,6,2,7> + 3667724438U, // <3,0,6,3>: Cost 4 vext1 <7,3,0,6>, <3,0,1,2> + 3763577355U, // <3,0,6,4>: Cost 4 vext3 LHS, <0,6,4,1> + 3322204198U, // <3,0,6,5>: Cost 4 vrev <5,6,0,3> + 2666574648U, // <3,0,6,6>: Cost 3 vext2 , <6,6,6,6> + 2657948520U, // <3,0,6,7>: Cost 3 vext2 <6,7,3,0>, <6,7,3,0> + 2689835573U, // <3,0,6,u>: Cost 3 vext3 LHS, <0,6,u,7> + 2666574842U, // <3,0,7,0>: Cost 3 vext2 , <7,0,1,2> + 2685633088U, // <3,0,7,1>: Cost 3 vext3 LHS, <0,7,1,0> + 2660603052U, // <3,0,7,2>: Cost 3 vext2 <7,2,3,0>, <7,2,3,0> + 3702494480U, // <3,0,7,3>: Cost 4 vext2 <1,u,3,0>, <7,3,5,1> + 2666575206U, // <3,0,7,4>: Cost 3 vext2 , <7,4,5,6> + 3702494624U, // <3,0,7,5>: Cost 4 vext2 <1,u,3,0>, <7,5,3,1> + 2732966514U, // <3,0,7,6>: Cost 3 vext3 LHS, <0,7,6,5> + 2666575468U, // <3,0,7,7>: Cost 3 vext2 , <7,7,7,7> + 2664584850U, // <3,0,7,u>: Cost 3 vext2 <7,u,3,0>, <7,u,3,0> + 1616093834U, // <3,0,u,0>: Cost 2 vext3 LHS, <0,u,0,2> + 1611891346U, // <3,0,u,1>: Cost 2 vext3 LHS, <0,u,1,1> + 537707165U, // <3,0,u,2>: Cost 1 vext3 LHS, LHS + 2689835684U, // <3,0,u,3>: Cost 3 vext3 LHS, <0,u,3,1> + 1616093874U, // <3,0,u,4>: Cost 2 vext3 LHS, <0,u,4,6> + 1551030426U, // <3,0,u,5>: Cost 2 vext2 <1,2,3,0>, RHS + 2624772304U, // <3,0,u,6>: Cost 3 vext2 <1,2,3,0>, + 2594002154U, // <3,0,u,7>: Cost 3 vext1 <7,3,0,u>, <7,3,0,u> + 537707219U, // <3,0,u,u>: Cost 1 vext3 LHS, LHS + 2552201318U, // <3,1,0,0>: Cost 3 vext1 <0,3,1,0>, LHS + 2618802278U, // <3,1,0,1>: Cost 3 vext2 <0,2,3,1>, LHS + 2618802366U, // <3,1,0,2>: Cost 3 vext2 <0,2,3,1>, <0,2,3,1> + 2685633268U, // <3,1,0,3>: Cost 3 vext3 LHS, <1,0,3,0> + 2552204598U, // <3,1,0,4>: Cost 3 vext1 <0,3,1,0>, RHS + 2732966664U, // <3,1,0,5>: Cost 3 vext3 LHS, <1,0,5,2> + 3906258396U, // <3,1,0,6>: Cost 4 vuzpr <2,3,0,1>, <2,0,4,6> + 2732966686U, // <3,1,0,7>: Cost 3 vext3 LHS, <1,0,7,6> + 2685633313U, // <3,1,0,u>: Cost 3 vext3 LHS, <1,0,u,0> + 2689835819U, // <3,1,1,0>: Cost 3 vext3 LHS, <1,1,0,1> + 1611449140U, // <3,1,1,1>: Cost 2 vext3 LHS, <1,1,1,1> + 2624775063U, // <3,1,1,2>: Cost 3 vext2 <1,2,3,1>, <1,2,3,1> + 1611891528U, // <3,1,1,3>: Cost 2 vext3 LHS, <1,1,3,3> + 2689835859U, // <3,1,1,4>: Cost 3 vext3 LHS, <1,1,4,5> + 2689835868U, // <3,1,1,5>: Cost 3 vext3 LHS, <1,1,5,5> + 3763577701U, // <3,1,1,6>: Cost 4 vext3 LHS, <1,1,6,5> + 2257163340U, // <3,1,1,7>: Cost 3 vrev <7,1,1,3> + 1611891573U, // <3,1,1,u>: Cost 2 vext3 LHS, <1,1,u,3> + 2552217702U, // <3,1,2,0>: Cost 3 vext1 <0,3,1,2>, LHS + 2689835911U, // <3,1,2,1>: Cost 3 vext3 LHS, <1,2,1,3> + 2564163248U, // <3,1,2,2>: Cost 3 vext1 <2,3,1,2>, <2,3,1,2> + 1611449238U, // <3,1,2,3>: Cost 2 vext3 LHS, <1,2,3,0> + 2552220982U, // <3,1,2,4>: Cost 3 vext1 <0,3,1,2>, RHS + 2689835947U, // <3,1,2,5>: Cost 3 vext3 LHS, <1,2,5,3> + 3692545978U, // <3,1,2,6>: Cost 4 vext2 <0,2,3,1>, <2,6,3,7> + 2732966842U, // <3,1,2,7>: Cost 3 vext3 LHS, <1,2,7,0> + 1611891651U, // <3,1,2,u>: Cost 2 vext3 LHS, <1,2,u,0> + 1484456038U, // <3,1,3,0>: Cost 2 vext1 <1,3,1,3>, LHS + 1611891672U, // <3,1,3,1>: Cost 2 vext3 LHS, <1,3,1,3> + 2685633502U, // <3,1,3,2>: Cost 3 vext3 LHS, <1,3,2,0> + 2685633512U, // <3,1,3,3>: Cost 3 vext3 LHS, <1,3,3,1> + 1484459318U, // <3,1,3,4>: Cost 2 vext1 <1,3,1,3>, RHS + 1611891712U, // <3,1,3,5>: Cost 2 vext3 LHS, <1,3,5,7> + 2689836041U, // <3,1,3,6>: Cost 3 vext3 LHS, <1,3,6,7> + 2733409294U, // <3,1,3,7>: Cost 3 vext3 LHS, <1,3,7,3> + 1611891735U, // <3,1,3,u>: Cost 2 vext3 LHS, <1,3,u,3> + 2552234086U, // <3,1,4,0>: Cost 3 vext1 <0,3,1,4>, LHS + 2732966955U, // <3,1,4,1>: Cost 3 vext3 LHS, <1,4,1,5> + 2732966964U, // <3,1,4,2>: Cost 3 vext3 LHS, <1,4,2,5> + 2685633597U, // <3,1,4,3>: Cost 3 vext3 LHS, <1,4,3,5> + 2552237366U, // <3,1,4,4>: Cost 3 vext1 <0,3,1,4>, RHS + 2618805558U, // <3,1,4,5>: Cost 3 vext2 <0,2,3,1>, RHS + 2769472822U, // <3,1,4,6>: Cost 3 vuzpl <3,0,1,2>, RHS + 3667784943U, // <3,1,4,7>: Cost 4 vext1 <7,3,1,4>, <7,3,1,4> + 2685633642U, // <3,1,4,u>: Cost 3 vext3 LHS, <1,4,u,5> + 2689836143U, // <3,1,5,0>: Cost 3 vext3 LHS, <1,5,0,1> + 2564187280U, // <3,1,5,1>: Cost 3 vext1 <2,3,1,5>, <1,5,3,7> + 2564187827U, // <3,1,5,2>: Cost 3 vext1 <2,3,1,5>, <2,3,1,5> + 1611891856U, // <3,1,5,3>: Cost 2 vext3 LHS, <1,5,3,7> + 2689836183U, // <3,1,5,4>: Cost 3 vext3 LHS, <1,5,4,5> + 3759375522U, // <3,1,5,5>: Cost 4 vext3 LHS, <1,5,5,7> + 3733688418U, // <3,1,5,6>: Cost 4 vext2 <7,1,3,1>, <5,6,7,0> + 2832518454U, // <3,1,5,7>: Cost 3 vuzpr <2,3,0,1>, RHS + 1611891901U, // <3,1,5,u>: Cost 2 vext3 LHS, <1,5,u,7> + 2732967110U, // <3,1,6,0>: Cost 3 vext3 LHS, <1,6,0,7> + 2689836239U, // <3,1,6,1>: Cost 3 vext3 LHS, <1,6,1,7> + 2732967128U, // <3,1,6,2>: Cost 3 vext3 LHS, <1,6,2,7> + 2685633761U, // <3,1,6,3>: Cost 3 vext3 LHS, <1,6,3,7> + 3763578088U, // <3,1,6,4>: Cost 4 vext3 LHS, <1,6,4,5> + 2689836275U, // <3,1,6,5>: Cost 3 vext3 LHS, <1,6,5,7> + 3763578108U, // <3,1,6,6>: Cost 4 vext3 LHS, <1,6,6,7> + 2732967166U, // <3,1,6,7>: Cost 3 vext3 LHS, <1,6,7,0> + 2685633806U, // <3,1,6,u>: Cost 3 vext3 LHS, <1,6,u,7> + 3631972454U, // <3,1,7,0>: Cost 4 vext1 <1,3,1,7>, LHS + 2659947612U, // <3,1,7,1>: Cost 3 vext2 <7,1,3,1>, <7,1,3,1> + 4036102294U, // <3,1,7,2>: Cost 4 vzipr <1,5,3,7>, <3,0,1,2> + 3095396454U, // <3,1,7,3>: Cost 3 vtrnr <1,3,5,7>, LHS + 3631975734U, // <3,1,7,4>: Cost 4 vext1 <1,3,1,7>, RHS + 2249199744U, // <3,1,7,5>: Cost 3 vrev <5,7,1,3> + 2255172441U, // <3,1,7,6>: Cost 3 vrev <6,7,1,3> + 3733689964U, // <3,1,7,7>: Cost 4 vext2 <7,1,3,1>, <7,7,7,7> + 3095396459U, // <3,1,7,u>: Cost 3 vtrnr <1,3,5,7>, LHS + 1484496998U, // <3,1,u,0>: Cost 2 vext1 <1,3,1,u>, LHS + 1611892077U, // <3,1,u,1>: Cost 2 vext3 LHS, <1,u,1,3> + 2685633907U, // <3,1,u,2>: Cost 3 vext3 LHS, <1,u,2,0> + 1611892092U, // <3,1,u,3>: Cost 2 vext3 LHS, <1,u,3,0> + 1484500278U, // <3,1,u,4>: Cost 2 vext1 <1,3,1,u>, RHS + 1611892117U, // <3,1,u,5>: Cost 2 vext3 LHS, <1,u,5,7> + 2685633950U, // <3,1,u,6>: Cost 3 vext3 LHS, <1,u,6,7> + 2832518697U, // <3,1,u,7>: Cost 3 vuzpr <2,3,0,1>, RHS + 1611892140U, // <3,1,u,u>: Cost 2 vext3 LHS, <1,u,u,3> + 2623455252U, // <3,2,0,0>: Cost 3 vext2 <1,0,3,2>, <0,0,2,2> + 2689836477U, // <3,2,0,1>: Cost 3 vext3 LHS, <2,0,1,2> + 2689836484U, // <3,2,0,2>: Cost 3 vext3 LHS, <2,0,2,0> + 2685633997U, // <3,2,0,3>: Cost 3 vext3 LHS, <2,0,3,0> + 2558250294U, // <3,2,0,4>: Cost 3 vext1 <1,3,2,0>, RHS + 2732967398U, // <3,2,0,5>: Cost 3 vext3 LHS, <2,0,5,7> + 2732967401U, // <3,2,0,6>: Cost 3 vext3 LHS, <2,0,6,1> + 3763578355U, // <3,2,0,7>: Cost 4 vext3 LHS, <2,0,7,2> + 2685634042U, // <3,2,0,u>: Cost 3 vext3 LHS, <2,0,u,0> + 67944550U, // <3,2,1,0>: Cost 1 vrev LHS + 2576171930U, // <3,2,1,1>: Cost 3 vext1 <4,3,2,1>, <1,2,3,4> + 2624783256U, // <3,2,1,2>: Cost 3 vext2 <1,2,3,2>, <1,2,3,2> + 2685634078U, // <3,2,1,3>: Cost 3 vext3 LHS, <2,1,3,0> + 2552286518U, // <3,2,1,4>: Cost 3 vext1 <0,3,2,1>, RHS + 3763578416U, // <3,2,1,5>: Cost 4 vext3 LHS, <2,1,5,0> + 2689836604U, // <3,2,1,6>: Cost 3 vext3 LHS, <2,1,6,3> + 2257237077U, // <3,2,1,7>: Cost 3 vrev <7,1,2,3> + 115726126U, // <3,2,1,u>: Cost 1 vrev LHS + 2689836629U, // <3,2,2,0>: Cost 3 vext3 LHS, <2,2,0,1> + 2689836640U, // <3,2,2,1>: Cost 3 vext3 LHS, <2,2,1,3> + 1611449960U, // <3,2,2,2>: Cost 2 vext3 LHS, <2,2,2,2> + 1611892338U, // <3,2,2,3>: Cost 2 vext3 LHS, <2,2,3,3> + 2689836669U, // <3,2,2,4>: Cost 3 vext3 LHS, <2,2,4,5> + 2689836680U, // <3,2,2,5>: Cost 3 vext3 LHS, <2,2,5,7> + 2689836688U, // <3,2,2,6>: Cost 3 vext3 LHS, <2,2,6,6> + 2257900710U, // <3,2,2,7>: Cost 3 vrev <7,2,2,3> + 1611892383U, // <3,2,2,u>: Cost 2 vext3 LHS, <2,2,u,3> + 1611450022U, // <3,2,3,0>: Cost 2 vext3 LHS, <2,3,0,1> + 2685191855U, // <3,2,3,1>: Cost 3 vext3 LHS, <2,3,1,1> + 2685191865U, // <3,2,3,2>: Cost 3 vext3 LHS, <2,3,2,2> + 2685191874U, // <3,2,3,3>: Cost 3 vext3 LHS, <2,3,3,2> + 1611450062U, // <3,2,3,4>: Cost 2 vext3 LHS, <2,3,4,5> + 2732967635U, // <3,2,3,5>: Cost 3 vext3 LHS, <2,3,5,1> + 2732967645U, // <3,2,3,6>: Cost 3 vext3 LHS, <2,3,6,2> + 2732967652U, // <3,2,3,7>: Cost 3 vext3 LHS, <2,3,7,0> + 1611450094U, // <3,2,3,u>: Cost 2 vext3 LHS, <2,3,u,1> + 2558279782U, // <3,2,4,0>: Cost 3 vext1 <1,3,2,4>, LHS + 2558280602U, // <3,2,4,1>: Cost 3 vext1 <1,3,2,4>, <1,2,3,4> + 2732967692U, // <3,2,4,2>: Cost 3 vext3 LHS, <2,4,2,4> + 2685634326U, // <3,2,4,3>: Cost 3 vext3 LHS, <2,4,3,5> + 2558283062U, // <3,2,4,4>: Cost 3 vext1 <1,3,2,4>, RHS + 2689836841U, // <3,2,4,5>: Cost 3 vext3 LHS, <2,4,5,6> + 2689836844U, // <3,2,4,6>: Cost 3 vext3 LHS, <2,4,6,0> + 3667858680U, // <3,2,4,7>: Cost 4 vext1 <7,3,2,4>, <7,3,2,4> + 2685634371U, // <3,2,4,u>: Cost 3 vext3 LHS, <2,4,u,5> + 2552316006U, // <3,2,5,0>: Cost 3 vext1 <0,3,2,5>, LHS + 3759376211U, // <3,2,5,1>: Cost 4 vext3 LHS, <2,5,1,3> + 2689836896U, // <3,2,5,2>: Cost 3 vext3 LHS, <2,5,2,7> + 2685634408U, // <3,2,5,3>: Cost 3 vext3 LHS, <2,5,3,6> + 2552319286U, // <3,2,5,4>: Cost 3 vext1 <0,3,2,5>, RHS + 3759376251U, // <3,2,5,5>: Cost 4 vext3 LHS, <2,5,5,7> + 2689836932U, // <3,2,5,6>: Cost 3 vext3 LHS, <2,5,6,7> + 3894398262U, // <3,2,5,7>: Cost 4 vuzpr <0,3,1,2>, RHS + 2685634453U, // <3,2,5,u>: Cost 3 vext3 LHS, <2,5,u,6> + 2689836953U, // <3,2,6,0>: Cost 3 vext3 LHS, <2,6,0,1> + 2689836964U, // <3,2,6,1>: Cost 3 vext3 LHS, <2,6,1,3> + 2689836976U, // <3,2,6,2>: Cost 3 vext3 LHS, <2,6,2,6> + 1611892666U, // <3,2,6,3>: Cost 2 vext3 LHS, <2,6,3,7> + 2689836993U, // <3,2,6,4>: Cost 3 vext3 LHS, <2,6,4,5> + 2689837004U, // <3,2,6,5>: Cost 3 vext3 LHS, <2,6,5,7> + 2689837013U, // <3,2,6,6>: Cost 3 vext3 LHS, <2,6,6,7> + 2657964906U, // <3,2,6,7>: Cost 3 vext2 <6,7,3,2>, <6,7,3,2> + 1611892711U, // <3,2,6,u>: Cost 2 vext3 LHS, <2,6,u,7> + 2732967914U, // <3,2,7,0>: Cost 3 vext3 LHS, <2,7,0,1> + 3626075280U, // <3,2,7,1>: Cost 4 vext1 <0,3,2,7>, <1,5,3,7> + 4169138340U, // <3,2,7,2>: Cost 4 vtrnr <1,3,5,7>, <0,2,0,2> + 2962358374U, // <3,2,7,3>: Cost 3 vzipr <1,5,3,7>, LHS + 3626077494U, // <3,2,7,4>: Cost 4 vext1 <0,3,2,7>, RHS + 4169138352U, // <3,2,7,5>: Cost 4 vtrnr <1,3,5,7>, <0,2,1,5> + 2255246178U, // <3,2,7,6>: Cost 3 vrev <6,7,2,3> + 3723744876U, // <3,2,7,7>: Cost 4 vext2 <5,4,3,2>, <7,7,7,7> + 2962358379U, // <3,2,7,u>: Cost 3 vzipr <1,5,3,7>, LHS + 72589981U, // <3,2,u,0>: Cost 1 vrev LHS + 2685634628U, // <3,2,u,1>: Cost 3 vext3 LHS, <2,u,1,1> + 1611449960U, // <3,2,u,2>: Cost 2 vext3 LHS, <2,2,2,2> + 1611892824U, // <3,2,u,3>: Cost 2 vext3 LHS, <2,u,3,3> + 1611892835U, // <3,2,u,4>: Cost 2 vext3 LHS, <2,u,4,5> + 2689837165U, // <3,2,u,5>: Cost 3 vext3 LHS, <2,u,5,6> + 2689837168U, // <3,2,u,6>: Cost 3 vext3 LHS, <2,u,6,0> + 2594149628U, // <3,2,u,7>: Cost 3 vext1 <7,3,2,u>, <7,3,2,u> + 120371557U, // <3,2,u,u>: Cost 1 vrev LHS + 2685192331U, // <3,3,0,0>: Cost 3 vext3 LHS, <3,0,0,0> + 1611450518U, // <3,3,0,1>: Cost 2 vext3 LHS, <3,0,1,2> + 2685634717U, // <3,3,0,2>: Cost 3 vext3 LHS, <3,0,2,0> + 2564294806U, // <3,3,0,3>: Cost 3 vext1 <2,3,3,0>, <3,0,1,2> + 2685634736U, // <3,3,0,4>: Cost 3 vext3 LHS, <3,0,4,1> + 2732968122U, // <3,3,0,5>: Cost 3 vext3 LHS, <3,0,5,2> + 3763579075U, // <3,3,0,6>: Cost 4 vext3 LHS, <3,0,6,2> + 4034053264U, // <3,3,0,7>: Cost 4 vzipr <1,2,3,0>, <1,5,3,7> + 1611450581U, // <3,3,0,u>: Cost 2 vext3 LHS, <3,0,u,2> + 2558328934U, // <3,3,1,0>: Cost 3 vext1 <1,3,3,1>, LHS + 1550385992U, // <3,3,1,1>: Cost 2 vext2 <1,1,3,3>, <1,1,3,3> + 2685192433U, // <3,3,1,2>: Cost 3 vext3 LHS, <3,1,2,3> + 2685634808U, // <3,3,1,3>: Cost 3 vext3 LHS, <3,1,3,1> + 2558332214U, // <3,3,1,4>: Cost 3 vext1 <1,3,3,1>, RHS + 2685634828U, // <3,3,1,5>: Cost 3 vext3 LHS, <3,1,5,3> + 3759376661U, // <3,3,1,6>: Cost 4 vext3 LHS, <3,1,6,3> + 2703477022U, // <3,3,1,7>: Cost 3 vext3 <3,1,7,3>, <3,1,7,3> + 1555031423U, // <3,3,1,u>: Cost 2 vext2 <1,u,3,3>, <1,u,3,3> + 2564309094U, // <3,3,2,0>: Cost 3 vext1 <2,3,3,2>, LHS + 1611450678U, // <3,3,2,1>: Cost 2 vext3 LHS, <3,2,1,0> + 1557022322U, // <3,3,2,2>: Cost 2 vext2 <2,2,3,3>, <2,2,3,3> + 2685192520U, // <3,3,2,3>: Cost 3 vext3 LHS, <3,2,3,0> + 2564312374U, // <3,3,2,4>: Cost 3 vext1 <2,3,3,2>, RHS + 3759376733U, // <3,3,2,5>: Cost 4 vext3 LHS, <3,2,5,3> + 2685634918U, // <3,3,2,6>: Cost 3 vext3 LHS, <3,2,6,3> + 2704140655U, // <3,3,2,7>: Cost 3 vext3 <3,2,7,3>, <3,2,7,3> + 1616095605U, // <3,3,2,u>: Cost 2 vext3 LHS, <3,2,u,0> + 1496547430U, // <3,3,3,0>: Cost 2 vext1 <3,3,3,3>, LHS + 2624129256U, // <3,3,3,1>: Cost 3 vext2 <1,1,3,3>, <3,1,1,3> + 2685192593U, // <3,3,3,2>: Cost 3 vext3 LHS, <3,3,2,1> + 336380006U, // <3,3,3,3>: Cost 1 vdup3 LHS + 1496550710U, // <3,3,3,4>: Cost 2 vext1 <3,3,3,3>, RHS + 2732968368U, // <3,3,3,5>: Cost 3 vext3 LHS, <3,3,5,5> + 2624129683U, // <3,3,3,6>: Cost 3 vext2 <1,1,3,3>, <3,6,3,7> + 2258638080U, // <3,3,3,7>: Cost 3 vrev <7,3,3,3> + 336380006U, // <3,3,3,u>: Cost 1 vdup3 LHS + 2558353510U, // <3,3,4,0>: Cost 3 vext1 <1,3,3,4>, LHS + 2558354411U, // <3,3,4,1>: Cost 3 vext1 <1,3,3,4>, <1,3,3,4> + 2564327108U, // <3,3,4,2>: Cost 3 vext1 <2,3,3,4>, <2,3,3,4> + 2564327938U, // <3,3,4,3>: Cost 3 vext1 <2,3,3,4>, <3,4,5,6> + 2960343962U, // <3,3,4,4>: Cost 3 vzipr <1,2,3,4>, <1,2,3,4> + 1611893250U, // <3,3,4,5>: Cost 2 vext3 LHS, <3,4,5,6> + 2771619126U, // <3,3,4,6>: Cost 3 vuzpl <3,3,3,3>, RHS + 4034086032U, // <3,3,4,7>: Cost 4 vzipr <1,2,3,4>, <1,5,3,7> + 1611893277U, // <3,3,4,u>: Cost 2 vext3 LHS, <3,4,u,6> + 2558361702U, // <3,3,5,0>: Cost 3 vext1 <1,3,3,5>, LHS + 2558362604U, // <3,3,5,1>: Cost 3 vext1 <1,3,3,5>, <1,3,3,5> + 2558363342U, // <3,3,5,2>: Cost 3 vext1 <1,3,3,5>, <2,3,4,5> + 2732968512U, // <3,3,5,3>: Cost 3 vext3 LHS, <3,5,3,5> + 2558364982U, // <3,3,5,4>: Cost 3 vext1 <1,3,3,5>, RHS + 3101279950U, // <3,3,5,5>: Cost 3 vtrnr <2,3,4,5>, <2,3,4,5> + 2665934946U, // <3,3,5,6>: Cost 3 vext2 , <5,6,7,0> + 2826636598U, // <3,3,5,7>: Cost 3 vuzpr <1,3,1,3>, RHS + 2826636599U, // <3,3,5,u>: Cost 3 vuzpr <1,3,1,3>, RHS + 2732968568U, // <3,3,6,0>: Cost 3 vext3 LHS, <3,6,0,7> + 3763579521U, // <3,3,6,1>: Cost 4 vext3 LHS, <3,6,1,7> + 2732968586U, // <3,3,6,2>: Cost 3 vext3 LHS, <3,6,2,7> + 2732968595U, // <3,3,6,3>: Cost 3 vext3 LHS, <3,6,3,7> + 2732968604U, // <3,3,6,4>: Cost 3 vext3 LHS, <3,6,4,7> + 3763579557U, // <3,3,6,5>: Cost 4 vext3 LHS, <3,6,5,7> + 2732968621U, // <3,3,6,6>: Cost 3 vext3 LHS, <3,6,6,6> + 2657973099U, // <3,3,6,7>: Cost 3 vext2 <6,7,3,3>, <6,7,3,3> + 2658636732U, // <3,3,6,u>: Cost 3 vext2 <6,u,3,3>, <6,u,3,3> + 2558378086U, // <3,3,7,0>: Cost 3 vext1 <1,3,3,7>, LHS + 2558378990U, // <3,3,7,1>: Cost 3 vext1 <1,3,3,7>, <1,3,3,7> + 2564351687U, // <3,3,7,2>: Cost 3 vext1 <2,3,3,7>, <2,3,3,7> + 2661291264U, // <3,3,7,3>: Cost 3 vext2 <7,3,3,3>, <7,3,3,3> + 2558381366U, // <3,3,7,4>: Cost 3 vext1 <1,3,3,7>, RHS + 2732968694U, // <3,3,7,5>: Cost 3 vext3 LHS, <3,7,5,7> + 2255319915U, // <3,3,7,6>: Cost 3 vrev <6,7,3,3> + 3095397376U, // <3,3,7,7>: Cost 3 vtrnr <1,3,5,7>, <1,3,5,7> + 2558383918U, // <3,3,7,u>: Cost 3 vext1 <1,3,3,7>, LHS + 1496547430U, // <3,3,u,0>: Cost 2 vext1 <3,3,3,3>, LHS + 1611893532U, // <3,3,u,1>: Cost 2 vext3 LHS, <3,u,1,0> + 1592858504U, // <3,3,u,2>: Cost 2 vext2 , + 336380006U, // <3,3,u,3>: Cost 1 vdup3 LHS + 1496550710U, // <3,3,u,4>: Cost 2 vext1 <3,3,3,3>, RHS + 1611893574U, // <3,3,u,5>: Cost 2 vext3 LHS, <3,u,5,6> + 2690280268U, // <3,3,u,6>: Cost 3 vext3 LHS, <3,u,6,3> + 2826636841U, // <3,3,u,7>: Cost 3 vuzpr <1,3,1,3>, RHS + 336380006U, // <3,3,u,u>: Cost 1 vdup3 LHS + 2624798720U, // <3,4,0,0>: Cost 3 vext2 <1,2,3,4>, <0,0,0,0> + 1551056998U, // <3,4,0,1>: Cost 2 vext2 <1,2,3,4>, LHS + 2624798884U, // <3,4,0,2>: Cost 3 vext2 <1,2,3,4>, <0,2,0,2> + 3693232384U, // <3,4,0,3>: Cost 4 vext2 <0,3,3,4>, <0,3,1,4> + 2624799058U, // <3,4,0,4>: Cost 3 vext2 <1,2,3,4>, <0,4,1,5> + 1659227026U, // <3,4,0,5>: Cost 2 vext3 LHS, <4,0,5,1> + 1659227036U, // <3,4,0,6>: Cost 2 vext3 LHS, <4,0,6,2> + 3667973382U, // <3,4,0,7>: Cost 4 vext1 <7,3,4,0>, <7,3,4,0> + 1551057565U, // <3,4,0,u>: Cost 2 vext2 <1,2,3,4>, LHS + 2564374630U, // <3,4,1,0>: Cost 3 vext1 <2,3,4,1>, LHS + 2624799540U, // <3,4,1,1>: Cost 3 vext2 <1,2,3,4>, <1,1,1,1> + 1551057818U, // <3,4,1,2>: Cost 2 vext2 <1,2,3,4>, <1,2,3,4> + 2624799704U, // <3,4,1,3>: Cost 3 vext2 <1,2,3,4>, <1,3,1,3> + 2564377910U, // <3,4,1,4>: Cost 3 vext1 <2,3,4,1>, RHS + 2689838050U, // <3,4,1,5>: Cost 3 vext3 LHS, <4,1,5,0> + 2689838062U, // <3,4,1,6>: Cost 3 vext3 LHS, <4,1,6,3> + 2628117807U, // <3,4,1,7>: Cost 3 vext2 <1,7,3,4>, <1,7,3,4> + 1555039616U, // <3,4,1,u>: Cost 2 vext2 <1,u,3,4>, <1,u,3,4> + 3626180710U, // <3,4,2,0>: Cost 4 vext1 <0,3,4,2>, LHS + 2624800298U, // <3,4,2,1>: Cost 3 vext2 <1,2,3,4>, <2,1,4,3> + 2624800360U, // <3,4,2,2>: Cost 3 vext2 <1,2,3,4>, <2,2,2,2> + 2624800422U, // <3,4,2,3>: Cost 3 vext2 <1,2,3,4>, <2,3,0,1> + 2624800514U, // <3,4,2,4>: Cost 3 vext2 <1,2,3,4>, <2,4,1,3> + 2905001270U, // <3,4,2,5>: Cost 3 vzipl <3,2,1,0>, RHS + 2689838140U, // <3,4,2,6>: Cost 3 vext3 LHS, <4,2,6,0> + 2634090504U, // <3,4,2,7>: Cost 3 vext2 <2,7,3,4>, <2,7,3,4> + 2689838158U, // <3,4,2,u>: Cost 3 vext3 LHS, <4,2,u,0> + 2624800918U, // <3,4,3,0>: Cost 3 vext2 <1,2,3,4>, <3,0,1,2> + 2636081403U, // <3,4,3,1>: Cost 3 vext2 <3,1,3,4>, <3,1,3,4> + 2624801078U, // <3,4,3,2>: Cost 3 vext2 <1,2,3,4>, <3,2,1,0> + 2624801180U, // <3,4,3,3>: Cost 3 vext2 <1,2,3,4>, <3,3,3,3> + 2624801232U, // <3,4,3,4>: Cost 3 vext2 <1,2,3,4>, <3,4,0,1> + 2905836854U, // <3,4,3,5>: Cost 3 vzipl <3,3,3,3>, RHS + 3040054582U, // <3,4,3,6>: Cost 3 vtrnl <3,3,3,3>, RHS + 3702524611U, // <3,4,3,7>: Cost 4 vext2 <1,u,3,4>, <3,7,0,1> + 2624801564U, // <3,4,3,u>: Cost 3 vext2 <1,2,3,4>, <3,u,1,0> + 2564399206U, // <3,4,4,0>: Cost 3 vext1 <2,3,4,4>, LHS + 2564400026U, // <3,4,4,1>: Cost 3 vext1 <2,3,4,4>, <1,2,3,4> + 2564400845U, // <3,4,4,2>: Cost 3 vext1 <2,3,4,4>, <2,3,4,4> + 2624801898U, // <3,4,4,3>: Cost 3 vext2 <1,2,3,4>, <4,3,2,1> + 1659227344U, // <3,4,4,4>: Cost 2 vext3 LHS, <4,4,4,4> + 1551060278U, // <3,4,4,5>: Cost 2 vext2 <1,2,3,4>, RHS + 1659227364U, // <3,4,4,6>: Cost 2 vext3 LHS, <4,4,6,6> + 3668006154U, // <3,4,4,7>: Cost 4 vext1 <7,3,4,4>, <7,3,4,4> + 1551060521U, // <3,4,4,u>: Cost 2 vext2 <1,2,3,4>, RHS + 1490665574U, // <3,4,5,0>: Cost 2 vext1 <2,3,4,5>, LHS + 2689838341U, // <3,4,5,1>: Cost 3 vext3 LHS, <4,5,1,3> + 1490667214U, // <3,4,5,2>: Cost 2 vext1 <2,3,4,5>, <2,3,4,5> + 2564409494U, // <3,4,5,3>: Cost 3 vext1 <2,3,4,5>, <3,0,1,2> + 1490668854U, // <3,4,5,4>: Cost 2 vext1 <2,3,4,5>, RHS + 2689838381U, // <3,4,5,5>: Cost 3 vext3 LHS, <4,5,5,7> + 537709878U, // <3,4,5,6>: Cost 1 vext3 LHS, RHS + 2594272523U, // <3,4,5,7>: Cost 3 vext1 <7,3,4,5>, <7,3,4,5> + 537709896U, // <3,4,5,u>: Cost 1 vext3 LHS, RHS + 2689838411U, // <3,4,6,0>: Cost 3 vext3 LHS, <4,6,0,1> + 2558444534U, // <3,4,6,1>: Cost 3 vext1 <1,3,4,6>, <1,3,4,6> + 2732969308U, // <3,4,6,2>: Cost 3 vext3 LHS, <4,6,2,0> + 2558446082U, // <3,4,6,3>: Cost 3 vext1 <1,3,4,6>, <3,4,5,6> + 1659227508U, // <3,4,6,4>: Cost 2 vext3 LHS, <4,6,4,6> + 2689838462U, // <3,4,6,5>: Cost 3 vext3 LHS, <4,6,5,7> + 2689838471U, // <3,4,6,6>: Cost 3 vext3 LHS, <4,6,6,7> + 2657981292U, // <3,4,6,7>: Cost 3 vext2 <6,7,3,4>, <6,7,3,4> + 1659227540U, // <3,4,6,u>: Cost 2 vext3 LHS, <4,6,u,2> + 2666607610U, // <3,4,7,0>: Cost 3 vext2 , <7,0,1,2> + 3702527072U, // <3,4,7,1>: Cost 4 vext2 <1,u,3,4>, <7,1,3,5> + 2660635824U, // <3,4,7,2>: Cost 3 vext2 <7,2,3,4>, <7,2,3,4> + 3702527248U, // <3,4,7,3>: Cost 4 vext2 <1,u,3,4>, <7,3,5,1> + 2666607974U, // <3,4,7,4>: Cost 3 vext2 , <7,4,5,6> + 2732969416U, // <3,4,7,5>: Cost 3 vext3 LHS, <4,7,5,0> + 2732969426U, // <3,4,7,6>: Cost 3 vext3 LHS, <4,7,6,1> + 2666608236U, // <3,4,7,7>: Cost 3 vext2 , <7,7,7,7> + 2664617622U, // <3,4,7,u>: Cost 3 vext2 <7,u,3,4>, <7,u,3,4> + 1490690150U, // <3,4,u,0>: Cost 2 vext1 <2,3,4,u>, LHS + 1551062830U, // <3,4,u,1>: Cost 2 vext2 <1,2,3,4>, LHS + 1490691793U, // <3,4,u,2>: Cost 2 vext1 <2,3,4,u>, <2,3,4,u> + 2624804796U, // <3,4,u,3>: Cost 3 vext2 <1,2,3,4>, + 1490693430U, // <3,4,u,4>: Cost 2 vext1 <2,3,4,u>, RHS + 1551063194U, // <3,4,u,5>: Cost 2 vext2 <1,2,3,4>, RHS + 537710121U, // <3,4,u,6>: Cost 1 vext3 LHS, RHS + 2594297102U, // <3,4,u,7>: Cost 3 vext1 <7,3,4,u>, <7,3,4,u> + 537710139U, // <3,4,u,u>: Cost 1 vext3 LHS, RHS + 3692576768U, // <3,5,0,0>: Cost 4 vext2 <0,2,3,5>, <0,0,0,0> + 2618835046U, // <3,5,0,1>: Cost 3 vext2 <0,2,3,5>, LHS + 2618835138U, // <3,5,0,2>: Cost 3 vext2 <0,2,3,5>, <0,2,3,5> + 3692577024U, // <3,5,0,3>: Cost 4 vext2 <0,2,3,5>, <0,3,1,4> + 2689838690U, // <3,5,0,4>: Cost 3 vext3 LHS, <5,0,4,1> + 2732969579U, // <3,5,0,5>: Cost 3 vext3 LHS, <5,0,5,1> + 2732969588U, // <3,5,0,6>: Cost 3 vext3 LHS, <5,0,6,1> + 4162817334U, // <3,5,0,7>: Cost 4 vtrnr <0,3,1,0>, RHS + 2618835613U, // <3,5,0,u>: Cost 3 vext2 <0,2,3,5>, LHS + 2594308198U, // <3,5,1,0>: Cost 3 vext1 <7,3,5,1>, LHS + 3692577588U, // <3,5,1,1>: Cost 4 vext2 <0,2,3,5>, <1,1,1,1> + 2624807835U, // <3,5,1,2>: Cost 3 vext2 <1,2,3,5>, <1,2,3,5> + 2625471468U, // <3,5,1,3>: Cost 3 vext2 <1,3,3,5>, <1,3,3,5> + 2689838770U, // <3,5,1,4>: Cost 3 vext3 LHS, <5,1,4,0> + 2594311888U, // <3,5,1,5>: Cost 3 vext1 <7,3,5,1>, <5,1,7,3> + 3699877107U, // <3,5,1,6>: Cost 4 vext2 <1,4,3,5>, <1,6,5,7> + 1641680592U, // <3,5,1,7>: Cost 2 vext3 <5,1,7,3>, <5,1,7,3> + 1641754329U, // <3,5,1,u>: Cost 2 vext3 <5,1,u,3>, <5,1,u,3> + 3703195090U, // <3,5,2,0>: Cost 4 vext2 <2,0,3,5>, <2,0,3,5> + 2630116899U, // <3,5,2,1>: Cost 3 vext2 <2,1,3,5>, <2,1,3,5> + 3692578408U, // <3,5,2,2>: Cost 4 vext2 <0,2,3,5>, <2,2,2,2> + 2625472206U, // <3,5,2,3>: Cost 3 vext2 <1,3,3,5>, <2,3,4,5> + 2632107798U, // <3,5,2,4>: Cost 3 vext2 <2,4,3,5>, <2,4,3,5> + 2715938575U, // <3,5,2,5>: Cost 3 vext3 <5,2,5,3>, <5,2,5,3> + 3692578746U, // <3,5,2,6>: Cost 4 vext2 <0,2,3,5>, <2,6,3,7> + 2716086049U, // <3,5,2,7>: Cost 3 vext3 <5,2,7,3>, <5,2,7,3> + 2634762330U, // <3,5,2,u>: Cost 3 vext2 <2,u,3,5>, <2,u,3,5> + 3692578966U, // <3,5,3,0>: Cost 4 vext2 <0,2,3,5>, <3,0,1,2> + 2636089596U, // <3,5,3,1>: Cost 3 vext2 <3,1,3,5>, <3,1,3,5> + 3692579126U, // <3,5,3,2>: Cost 4 vext2 <0,2,3,5>, <3,2,1,0> + 2638080412U, // <3,5,3,3>: Cost 3 vext2 <3,4,3,5>, <3,3,3,3> + 2618837506U, // <3,5,3,4>: Cost 3 vext2 <0,2,3,5>, <3,4,5,6> + 2832844494U, // <3,5,3,5>: Cost 3 vuzpr <2,3,4,5>, <2,3,4,5> + 4033415682U, // <3,5,3,6>: Cost 4 vzipr <1,1,3,3>, <3,4,5,6> + 3095072054U, // <3,5,3,7>: Cost 3 vtrnr <1,3,1,3>, RHS + 3095072055U, // <3,5,3,u>: Cost 3 vtrnr <1,3,1,3>, RHS + 2732969858U, // <3,5,4,0>: Cost 3 vext3 LHS, <5,4,0,1> + 2732969874U, // <3,5,4,1>: Cost 3 vext3 LHS, <5,4,1,u> + 3763580819U, // <3,5,4,2>: Cost 4 vext3 LHS, <5,4,2,0> + 2732969886U, // <3,5,4,3>: Cost 3 vext3 LHS, <5,4,3,2> + 2732969898U, // <3,5,4,4>: Cost 3 vext3 LHS, <5,4,4,5> + 2618838326U, // <3,5,4,5>: Cost 3 vext2 <0,2,3,5>, RHS + 2772454710U, // <3,5,4,6>: Cost 3 vuzpl <3,4,5,6>, RHS + 2732969925U, // <3,5,4,7>: Cost 3 vext3 LHS, <5,4,7,5> + 2618838569U, // <3,5,4,u>: Cost 3 vext2 <0,2,3,5>, RHS + 2570453094U, // <3,5,5,0>: Cost 3 vext1 <3,3,5,5>, LHS + 2624810704U, // <3,5,5,1>: Cost 3 vext2 <1,2,3,5>, <5,1,7,3> + 2570454734U, // <3,5,5,2>: Cost 3 vext1 <3,3,5,5>, <2,3,4,5> + 2570455472U, // <3,5,5,3>: Cost 3 vext1 <3,3,5,5>, <3,3,5,5> + 2570456374U, // <3,5,5,4>: Cost 3 vext1 <3,3,5,5>, RHS + 1659228164U, // <3,5,5,5>: Cost 2 vext3 LHS, <5,5,5,5> + 2732969998U, // <3,5,5,6>: Cost 3 vext3 LHS, <5,5,6,6> + 1659228184U, // <3,5,5,7>: Cost 2 vext3 LHS, <5,5,7,7> + 1659228193U, // <3,5,5,u>: Cost 2 vext3 LHS, <5,5,u,7> + 2732970020U, // <3,5,6,0>: Cost 3 vext3 LHS, <5,6,0,1> + 2732970035U, // <3,5,6,1>: Cost 3 vext3 LHS, <5,6,1,7> + 2564490968U, // <3,5,6,2>: Cost 3 vext1 <2,3,5,6>, <2,3,5,6> + 2732970050U, // <3,5,6,3>: Cost 3 vext3 LHS, <5,6,3,4> + 2732970060U, // <3,5,6,4>: Cost 3 vext3 LHS, <5,6,4,5> + 2732970071U, // <3,5,6,5>: Cost 3 vext3 LHS, <5,6,5,7> + 2732970080U, // <3,5,6,6>: Cost 3 vext3 LHS, <5,6,6,7> + 1659228258U, // <3,5,6,7>: Cost 2 vext3 LHS, <5,6,7,0> + 1659228267U, // <3,5,6,u>: Cost 2 vext3 LHS, <5,6,u,0> + 1484783718U, // <3,5,7,0>: Cost 2 vext1 <1,3,5,7>, LHS + 1484784640U, // <3,5,7,1>: Cost 2 vext1 <1,3,5,7>, <1,3,5,7> + 2558527080U, // <3,5,7,2>: Cost 3 vext1 <1,3,5,7>, <2,2,2,2> + 2558527638U, // <3,5,7,3>: Cost 3 vext1 <1,3,5,7>, <3,0,1,2> + 1484786998U, // <3,5,7,4>: Cost 2 vext1 <1,3,5,7>, RHS + 1659228328U, // <3,5,7,5>: Cost 2 vext3 LHS, <5,7,5,7> + 2732970154U, // <3,5,7,6>: Cost 3 vext3 LHS, <5,7,6,0> + 2558530976U, // <3,5,7,7>: Cost 3 vext1 <1,3,5,7>, <7,5,3,1> + 1484789550U, // <3,5,7,u>: Cost 2 vext1 <1,3,5,7>, LHS + 1484791910U, // <3,5,u,0>: Cost 2 vext1 <1,3,5,u>, LHS + 1484792833U, // <3,5,u,1>: Cost 2 vext1 <1,3,5,u>, <1,3,5,u> + 2558535272U, // <3,5,u,2>: Cost 3 vext1 <1,3,5,u>, <2,2,2,2> + 2558535830U, // <3,5,u,3>: Cost 3 vext1 <1,3,5,u>, <3,0,1,2> + 1484795190U, // <3,5,u,4>: Cost 2 vext1 <1,3,5,u>, RHS + 1659228409U, // <3,5,u,5>: Cost 2 vext3 LHS, <5,u,5,7> + 2772457626U, // <3,5,u,6>: Cost 3 vuzpl <3,4,5,6>, RHS + 1646326023U, // <3,5,u,7>: Cost 2 vext3 <5,u,7,3>, <5,u,7,3> + 1484797742U, // <3,5,u,u>: Cost 2 vext1 <1,3,5,u>, LHS + 2558541926U, // <3,6,0,0>: Cost 3 vext1 <1,3,6,0>, LHS + 2689839393U, // <3,6,0,1>: Cost 3 vext3 LHS, <6,0,1,2> + 2689839404U, // <3,6,0,2>: Cost 3 vext3 LHS, <6,0,2,4> + 3706519808U, // <3,6,0,3>: Cost 4 vext2 <2,5,3,6>, <0,3,1,4> + 2689839420U, // <3,6,0,4>: Cost 3 vext3 LHS, <6,0,4,2> + 2732970314U, // <3,6,0,5>: Cost 3 vext3 LHS, <6,0,5,7> + 2732970316U, // <3,6,0,6>: Cost 3 vext3 LHS, <6,0,6,0> + 2960313654U, // <3,6,0,7>: Cost 3 vzipr <1,2,3,0>, RHS + 2689839456U, // <3,6,0,u>: Cost 3 vext3 LHS, <6,0,u,2> + 2720878954U, // <3,6,1,0>: Cost 3 vext3 <6,1,0,3>, <6,1,0,3> + 3763581297U, // <3,6,1,1>: Cost 4 vext3 LHS, <6,1,1,1> + 2624816028U, // <3,6,1,2>: Cost 3 vext2 <1,2,3,6>, <1,2,3,6> + 3763581315U, // <3,6,1,3>: Cost 4 vext3 LHS, <6,1,3,1> + 2626143294U, // <3,6,1,4>: Cost 3 vext2 <1,4,3,6>, <1,4,3,6> + 3763581335U, // <3,6,1,5>: Cost 4 vext3 LHS, <6,1,5,3> + 2721321376U, // <3,6,1,6>: Cost 3 vext3 <6,1,6,3>, <6,1,6,3> + 2721395113U, // <3,6,1,7>: Cost 3 vext3 <6,1,7,3>, <6,1,7,3> + 2628797826U, // <3,6,1,u>: Cost 3 vext2 <1,u,3,6>, <1,u,3,6> + 2594390118U, // <3,6,2,0>: Cost 3 vext1 <7,3,6,2>, LHS + 2721616324U, // <3,6,2,1>: Cost 3 vext3 <6,2,1,3>, <6,2,1,3> + 2630788725U, // <3,6,2,2>: Cost 3 vext2 <2,2,3,6>, <2,2,3,6> + 2234304870U, // <3,6,2,3>: Cost 3 vrev <3,2,6,3> + 2689839580U, // <3,6,2,4>: Cost 3 vext3 LHS, <6,2,4,0> + 2632779624U, // <3,6,2,5>: Cost 3 vext2 <2,5,3,6>, <2,5,3,6> + 2594394618U, // <3,6,2,6>: Cost 3 vext1 <7,3,6,2>, <6,2,7,3> + 1648316922U, // <3,6,2,7>: Cost 2 vext3 <6,2,7,3>, <6,2,7,3> + 1648390659U, // <3,6,2,u>: Cost 2 vext3 <6,2,u,3>, <6,2,u,3> + 3693914262U, // <3,6,3,0>: Cost 4 vext2 <0,4,3,6>, <3,0,1,2> + 3638281176U, // <3,6,3,1>: Cost 4 vext1 <2,3,6,3>, <1,3,1,3> + 3763581468U, // <3,6,3,2>: Cost 4 vext3 LHS, <6,3,2,1> + 2638088604U, // <3,6,3,3>: Cost 3 vext2 <3,4,3,6>, <3,3,3,3> + 2632780290U, // <3,6,3,4>: Cost 3 vext2 <2,5,3,6>, <3,4,5,6> + 3712494145U, // <3,6,3,5>: Cost 4 vext2 <3,5,3,6>, <3,5,3,6> + 3698559612U, // <3,6,3,6>: Cost 4 vext2 <1,2,3,6>, <3,6,1,2> + 2959674678U, // <3,6,3,7>: Cost 3 vzipr <1,1,3,3>, RHS + 2959674679U, // <3,6,3,u>: Cost 3 vzipr <1,1,3,3>, RHS + 3638288486U, // <3,6,4,0>: Cost 4 vext1 <2,3,6,4>, LHS + 2722943590U, // <3,6,4,1>: Cost 3 vext3 <6,4,1,3>, <6,4,1,3> + 2689839724U, // <3,6,4,2>: Cost 3 vext3 LHS, <6,4,2,0> + 3698560147U, // <3,6,4,3>: Cost 4 vext2 <1,2,3,6>, <4,3,6,6> + 2732970628U, // <3,6,4,4>: Cost 3 vext3 LHS, <6,4,4,6> + 2689839757U, // <3,6,4,5>: Cost 3 vext3 LHS, <6,4,5,6> + 2732970640U, // <3,6,4,6>: Cost 3 vext3 LHS, <6,4,6,0> + 2960346422U, // <3,6,4,7>: Cost 3 vzipr <1,2,3,4>, RHS + 2689839784U, // <3,6,4,u>: Cost 3 vext3 LHS, <6,4,u,6> + 2732970674U, // <3,6,5,0>: Cost 3 vext3 LHS, <6,5,0,7> + 3789165243U, // <3,6,5,1>: Cost 4 vext3 <5,1,7,3>, <6,5,1,7> + 2732970692U, // <3,6,5,2>: Cost 3 vext3 LHS, <6,5,2,7> + 2576501250U, // <3,6,5,3>: Cost 3 vext1 <4,3,6,5>, <3,4,5,6> + 2242268466U, // <3,6,5,4>: Cost 3 vrev <4,5,6,3> + 3806712536U, // <3,6,5,5>: Cost 4 vext3 LHS, <6,5,5,0> + 4114633528U, // <3,6,5,6>: Cost 4 vtrnl <3,4,5,6>, <6,6,6,6> + 2732970735U, // <3,6,5,7>: Cost 3 vext3 LHS, <6,5,7,5> + 2724123382U, // <3,6,5,u>: Cost 3 vext3 <6,5,u,3>, <6,5,u,3> + 2732970749U, // <3,6,6,0>: Cost 3 vext3 LHS, <6,6,0,1> + 2724270856U, // <3,6,6,1>: Cost 3 vext3 <6,6,1,3>, <6,6,1,3> + 2624819706U, // <3,6,6,2>: Cost 3 vext2 <1,2,3,6>, <6,2,7,3> + 3699888686U, // <3,6,6,3>: Cost 4 vext2 <1,4,3,6>, <6,3,4,1> + 2732970788U, // <3,6,6,4>: Cost 3 vext3 LHS, <6,6,4,4> + 2732970800U, // <3,6,6,5>: Cost 3 vext3 LHS, <6,6,5,7> + 1659228984U, // <3,6,6,6>: Cost 2 vext3 LHS, <6,6,6,6> + 1659228994U, // <3,6,6,7>: Cost 2 vext3 LHS, <6,6,7,7> + 1659229003U, // <3,6,6,u>: Cost 2 vext3 LHS, <6,6,u,7> + 1659229006U, // <3,6,7,0>: Cost 2 vext3 LHS, <6,7,0,1> + 2558600201U, // <3,6,7,1>: Cost 3 vext1 <1,3,6,7>, <1,3,6,7> + 2558601146U, // <3,6,7,2>: Cost 3 vext1 <1,3,6,7>, <2,6,3,7> + 2725081963U, // <3,6,7,3>: Cost 3 vext3 <6,7,3,3>, <6,7,3,3> + 1659229046U, // <3,6,7,4>: Cost 2 vext3 LHS, <6,7,4,5> + 2715423611U, // <3,6,7,5>: Cost 3 vext3 <5,1,7,3>, <6,7,5,1> + 2722059141U, // <3,6,7,6>: Cost 3 vext3 <6,2,7,3>, <6,7,6,2> + 2962361654U, // <3,6,7,7>: Cost 3 vzipr <1,5,3,7>, RHS + 1659229078U, // <3,6,7,u>: Cost 2 vext3 LHS, <6,7,u,1> + 1659229087U, // <3,6,u,0>: Cost 2 vext3 LHS, <6,u,0,1> + 2689840041U, // <3,6,u,1>: Cost 3 vext3 LHS, <6,u,1,2> + 2689840048U, // <3,6,u,2>: Cost 3 vext3 LHS, <6,u,2,0> + 2238286668U, // <3,6,u,3>: Cost 3 vrev <3,u,6,3> + 1659229127U, // <3,6,u,4>: Cost 2 vext3 LHS, <6,u,4,5> + 2689840081U, // <3,6,u,5>: Cost 3 vext3 LHS, <6,u,5,6> + 1659228984U, // <3,6,u,6>: Cost 2 vext3 LHS, <6,6,6,6> + 1652298720U, // <3,6,u,7>: Cost 2 vext3 <6,u,7,3>, <6,u,7,3> + 1659229159U, // <3,6,u,u>: Cost 2 vext3 LHS, <6,u,u,1> + 2626813952U, // <3,7,0,0>: Cost 3 vext2 <1,5,3,7>, <0,0,0,0> + 1553072230U, // <3,7,0,1>: Cost 2 vext2 <1,5,3,7>, LHS + 2626814116U, // <3,7,0,2>: Cost 3 vext2 <1,5,3,7>, <0,2,0,2> + 3700556028U, // <3,7,0,3>: Cost 4 vext2 <1,5,3,7>, <0,3,1,0> + 2626814290U, // <3,7,0,4>: Cost 3 vext2 <1,5,3,7>, <0,4,1,5> + 2582507375U, // <3,7,0,5>: Cost 3 vext1 <5,3,7,0>, <5,3,7,0> + 2588480072U, // <3,7,0,6>: Cost 3 vext1 <6,3,7,0>, <6,3,7,0> + 2732971055U, // <3,7,0,7>: Cost 3 vext3 LHS, <7,0,7,1> + 1553072797U, // <3,7,0,u>: Cost 2 vext2 <1,5,3,7>, LHS + 2582511718U, // <3,7,1,0>: Cost 3 vext1 <5,3,7,1>, LHS + 2626814772U, // <3,7,1,1>: Cost 3 vext2 <1,5,3,7>, <1,1,1,1> + 2626814870U, // <3,7,1,2>: Cost 3 vext2 <1,5,3,7>, <1,2,3,0> + 2625487854U, // <3,7,1,3>: Cost 3 vext2 <1,3,3,7>, <1,3,3,7> + 2582514998U, // <3,7,1,4>: Cost 3 vext1 <5,3,7,1>, RHS + 1553073296U, // <3,7,1,5>: Cost 2 vext2 <1,5,3,7>, <1,5,3,7> + 2627478753U, // <3,7,1,6>: Cost 3 vext2 <1,6,3,7>, <1,6,3,7> + 2727367810U, // <3,7,1,7>: Cost 3 vext3 <7,1,7,3>, <7,1,7,3> + 1555064195U, // <3,7,1,u>: Cost 2 vext2 <1,u,3,7>, <1,u,3,7> + 2588491878U, // <3,7,2,0>: Cost 3 vext1 <6,3,7,2>, LHS + 3700557342U, // <3,7,2,1>: Cost 4 vext2 <1,5,3,7>, <2,1,3,0> + 2626815592U, // <3,7,2,2>: Cost 3 vext2 <1,5,3,7>, <2,2,2,2> + 2626815654U, // <3,7,2,3>: Cost 3 vext2 <1,5,3,7>, <2,3,0,1> + 2588495158U, // <3,7,2,4>: Cost 3 vext1 <6,3,7,2>, RHS + 2632787817U, // <3,7,2,5>: Cost 3 vext2 <2,5,3,7>, <2,5,3,7> + 1559709626U, // <3,7,2,6>: Cost 2 vext2 <2,6,3,7>, <2,6,3,7> + 2728031443U, // <3,7,2,7>: Cost 3 vext3 <7,2,7,3>, <7,2,7,3> + 1561036892U, // <3,7,2,u>: Cost 2 vext2 <2,u,3,7>, <2,u,3,7> + 2626816150U, // <3,7,3,0>: Cost 3 vext2 <1,5,3,7>, <3,0,1,2> + 2626816268U, // <3,7,3,1>: Cost 3 vext2 <1,5,3,7>, <3,1,5,3> + 2626816310U, // <3,7,3,2>: Cost 3 vext2 <1,5,3,7>, <3,2,1,0> + 2626816412U, // <3,7,3,3>: Cost 3 vext2 <1,5,3,7>, <3,3,3,3> + 2626816514U, // <3,7,3,4>: Cost 3 vext2 <1,5,3,7>, <3,4,5,6> + 2638760514U, // <3,7,3,5>: Cost 3 vext2 <3,5,3,7>, <3,5,3,7> + 2639424147U, // <3,7,3,6>: Cost 3 vext2 <3,6,3,7>, <3,6,3,7> + 2826961920U, // <3,7,3,7>: Cost 3 vuzpr <1,3,5,7>, <1,3,5,7> + 2626816796U, // <3,7,3,u>: Cost 3 vext2 <1,5,3,7>, <3,u,1,0> + 2582536294U, // <3,7,4,0>: Cost 3 vext1 <5,3,7,4>, LHS + 2582537360U, // <3,7,4,1>: Cost 3 vext1 <5,3,7,4>, <1,5,3,7> + 2588510138U, // <3,7,4,2>: Cost 3 vext1 <6,3,7,4>, <2,6,3,7> + 3700558954U, // <3,7,4,3>: Cost 4 vext2 <1,5,3,7>, <4,3,2,1> + 2582539574U, // <3,7,4,4>: Cost 3 vext1 <5,3,7,4>, RHS + 1553075510U, // <3,7,4,5>: Cost 2 vext2 <1,5,3,7>, RHS + 2588512844U, // <3,7,4,6>: Cost 3 vext1 <6,3,7,4>, <6,3,7,4> + 2564625766U, // <3,7,4,7>: Cost 3 vext1 <2,3,7,4>, <7,4,5,6> + 1553075753U, // <3,7,4,u>: Cost 2 vext2 <1,5,3,7>, RHS + 2732971398U, // <3,7,5,0>: Cost 3 vext3 LHS, <7,5,0,2> + 2715424148U, // <3,7,5,1>: Cost 3 vext3 <5,1,7,3>, <7,5,1,7> + 3700559649U, // <3,7,5,2>: Cost 4 vext2 <1,5,3,7>, <5,2,7,3> + 2626817903U, // <3,7,5,3>: Cost 3 vext2 <1,5,3,7>, <5,3,7,0> + 3900705379U, // <3,7,5,4>: Cost 4 vuzpr <1,3,5,7>, <3,5,7,4> + 2732971446U, // <3,7,5,5>: Cost 3 vext3 LHS, <7,5,5,5> + 2732971457U, // <3,7,5,6>: Cost 3 vext3 LHS, <7,5,6,7> + 2826964278U, // <3,7,5,7>: Cost 3 vuzpr <1,3,5,7>, RHS + 2826964279U, // <3,7,5,u>: Cost 3 vuzpr <1,3,5,7>, RHS + 2600468582U, // <3,7,6,0>: Cost 3 vext1 , LHS + 2633453993U, // <3,7,6,1>: Cost 3 vext2 <2,6,3,7>, <6,1,7,3> + 2722059758U, // <3,7,6,2>: Cost 3 vext3 <6,2,7,3>, <7,6,2,7> + 2633454152U, // <3,7,6,3>: Cost 3 vext2 <2,6,3,7>, <6,3,7,0> + 2600471862U, // <3,7,6,4>: Cost 3 vext1 , RHS + 1659229702U, // <3,7,6,5>: Cost 2 vext3 LHS, <7,6,5,4> + 2732971537U, // <3,7,6,6>: Cost 3 vext3 LHS, <7,6,6,6> + 2732971540U, // <3,7,6,7>: Cost 3 vext3 LHS, <7,6,7,0> + 1659229729U, // <3,7,6,u>: Cost 2 vext3 LHS, <7,6,u,4> + 2570616934U, // <3,7,7,0>: Cost 3 vext1 <3,3,7,7>, LHS + 2570617856U, // <3,7,7,1>: Cost 3 vext1 <3,3,7,7>, <1,3,5,7> + 2564646635U, // <3,7,7,2>: Cost 3 vext1 <2,3,7,7>, <2,3,7,7> + 2626819344U, // <3,7,7,3>: Cost 3 vext2 <1,5,3,7>, <7,3,5,1> + 2570620214U, // <3,7,7,4>: Cost 3 vext1 <3,3,7,7>, RHS + 2732971608U, // <3,7,7,5>: Cost 3 vext3 LHS, <7,7,5,5> + 2732971617U, // <3,7,7,6>: Cost 3 vext3 LHS, <7,7,6,5> + 1659229804U, // <3,7,7,7>: Cost 2 vext3 LHS, <7,7,7,7> + 1659229804U, // <3,7,7,u>: Cost 2 vext3 LHS, <7,7,7,7> + 2626819795U, // <3,7,u,0>: Cost 3 vext2 <1,5,3,7>, + 1553078062U, // <3,7,u,1>: Cost 2 vext2 <1,5,3,7>, LHS + 2626819955U, // <3,7,u,2>: Cost 3 vext2 <1,5,3,7>, + 2826961565U, // <3,7,u,3>: Cost 3 vuzpr <1,3,5,7>, LHS + 2626820159U, // <3,7,u,4>: Cost 3 vext2 <1,5,3,7>, + 1553078426U, // <3,7,u,5>: Cost 2 vext2 <1,5,3,7>, RHS + 1595545808U, // <3,7,u,6>: Cost 2 vext2 , + 1659229804U, // <3,7,u,7>: Cost 2 vext3 LHS, <7,7,7,7> + 1553078629U, // <3,7,u,u>: Cost 2 vext2 <1,5,3,7>, LHS + 1611448320U, // <3,u,0,0>: Cost 2 vext3 LHS, <0,0,0,0> + 1611896531U, // <3,u,0,1>: Cost 2 vext3 LHS, + 1659672284U, // <3,u,0,2>: Cost 2 vext3 LHS, + 2689840867U, // <3,u,0,3>: Cost 3 vext3 LHS, + 2685638381U, // <3,u,0,4>: Cost 3 vext3 LHS, + 1663874806U, // <3,u,0,5>: Cost 2 vext3 LHS, + 1663874816U, // <3,u,0,6>: Cost 2 vext3 LHS, + 2960313672U, // <3,u,0,7>: Cost 3 vzipr <1,2,3,0>, RHS + 1611896594U, // <3,u,0,u>: Cost 2 vext3 LHS, + 68386972U, // <3,u,1,0>: Cost 1 vrev LHS + 1550426957U, // <3,u,1,1>: Cost 2 vext2 <1,1,3,u>, <1,1,3,u> + 537712430U, // <3,u,1,2>: Cost 1 vext3 LHS, LHS + 1616541495U, // <3,u,1,3>: Cost 2 vext3 LHS, + 1490930998U, // <3,u,1,4>: Cost 2 vext1 <2,3,u,1>, RHS + 1553081489U, // <3,u,1,5>: Cost 2 vext2 <1,5,3,u>, <1,5,3,u> + 2627486946U, // <3,u,1,6>: Cost 3 vext2 <1,6,3,u>, <1,6,3,u> + 1659230043U, // <3,u,1,7>: Cost 2 vext3 LHS, + 537712484U, // <3,u,1,u>: Cost 1 vext3 LHS, LHS + 1611890852U, // <3,u,2,0>: Cost 2 vext3 LHS, <0,2,0,2> + 1611896691U, // <3,u,2,1>: Cost 2 vext3 LHS, + 1557063287U, // <3,u,2,2>: Cost 2 vext2 <2,2,3,u>, <2,2,3,u> + 1616099205U, // <3,u,2,3>: Cost 2 vext3 LHS, + 1611890892U, // <3,u,2,4>: Cost 2 vext3 LHS, <0,2,4,6> + 2689841054U, // <3,u,2,5>: Cost 3 vext3 LHS, + 1559717819U, // <3,u,2,6>: Cost 2 vext2 <2,6,3,u>, <2,6,3,u> + 1659230124U, // <3,u,2,7>: Cost 2 vext3 LHS, + 1616541618U, // <3,u,2,u>: Cost 2 vext3 LHS, + 1611896764U, // <3,u,3,0>: Cost 2 vext3 LHS, + 1484973079U, // <3,u,3,1>: Cost 2 vext1 <1,3,u,3>, <1,3,u,3> + 2685638606U, // <3,u,3,2>: Cost 3 vext3 LHS, + 336380006U, // <3,u,3,3>: Cost 1 vdup3 LHS + 1611896804U, // <3,u,3,4>: Cost 2 vext3 LHS, + 1616541679U, // <3,u,3,5>: Cost 2 vext3 LHS, + 2690283512U, // <3,u,3,6>: Cost 3 vext3 LHS, + 2959674696U, // <3,u,3,7>: Cost 3 vzipr <1,1,3,3>, RHS + 336380006U, // <3,u,3,u>: Cost 1 vdup3 LHS + 2558722150U, // <3,u,4,0>: Cost 3 vext1 <1,3,u,4>, LHS + 1659672602U, // <3,u,4,1>: Cost 2 vext3 LHS, + 1659672612U, // <3,u,4,2>: Cost 2 vext3 LHS, + 2689841196U, // <3,u,4,3>: Cost 3 vext3 LHS, + 1659227344U, // <3,u,4,4>: Cost 2 vext3 LHS, <4,4,4,4> + 1611896895U, // <3,u,4,5>: Cost 2 vext3 LHS, + 1663875144U, // <3,u,4,6>: Cost 2 vext3 LHS, + 2960346440U, // <3,u,4,7>: Cost 3 vzipr <1,2,3,4>, RHS + 1611896922U, // <3,u,4,u>: Cost 2 vext3 LHS, + 1490960486U, // <3,u,5,0>: Cost 2 vext1 <2,3,u,5>, LHS + 2689841261U, // <3,u,5,1>: Cost 3 vext3 LHS, + 1490962162U, // <3,u,5,2>: Cost 2 vext1 <2,3,u,5>, <2,3,u,5> + 1616541823U, // <3,u,5,3>: Cost 2 vext3 LHS, + 1490963766U, // <3,u,5,4>: Cost 2 vext1 <2,3,u,5>, RHS + 1659228164U, // <3,u,5,5>: Cost 2 vext3 LHS, <5,5,5,5> + 537712794U, // <3,u,5,6>: Cost 1 vext3 LHS, RHS + 1659230371U, // <3,u,5,7>: Cost 2 vext3 LHS, + 537712812U, // <3,u,5,u>: Cost 1 vext3 LHS, RHS + 2689841327U, // <3,u,6,0>: Cost 3 vext3 LHS, + 2558739482U, // <3,u,6,1>: Cost 3 vext1 <1,3,u,6>, <1,3,u,6> + 2689841351U, // <3,u,6,2>: Cost 3 vext3 LHS, + 1616099536U, // <3,u,6,3>: Cost 2 vext3 LHS, + 1659227508U, // <3,u,6,4>: Cost 2 vext3 LHS, <4,6,4,6> + 1659230431U, // <3,u,6,5>: Cost 2 vext3 LHS, + 1659228984U, // <3,u,6,6>: Cost 2 vext3 LHS, <6,6,6,6> + 1659230445U, // <3,u,6,7>: Cost 2 vext3 LHS, + 1616099581U, // <3,u,6,u>: Cost 2 vext3 LHS, + 1485004902U, // <3,u,7,0>: Cost 2 vext1 <1,3,u,7>, LHS + 1485005851U, // <3,u,7,1>: Cost 2 vext1 <1,3,u,7>, <1,3,u,7> + 2558748264U, // <3,u,7,2>: Cost 3 vext1 <1,3,u,7>, <2,2,2,2> + 3095397021U, // <3,u,7,3>: Cost 3 vtrnr <1,3,5,7>, LHS + 1485008182U, // <3,u,7,4>: Cost 2 vext1 <1,3,u,7>, RHS + 1659228328U, // <3,u,7,5>: Cost 2 vext3 LHS, <5,7,5,7> + 2722060599U, // <3,u,7,6>: Cost 3 vext3 <6,2,7,3>, + 1659229804U, // <3,u,7,7>: Cost 2 vext3 LHS, <7,7,7,7> + 1485010734U, // <3,u,7,u>: Cost 2 vext1 <1,3,u,7>, LHS + 73032403U, // <3,u,u,0>: Cost 1 vrev LHS + 1611897179U, // <3,u,u,1>: Cost 2 vext3 LHS, + 537712997U, // <3,u,u,2>: Cost 1 vext3 LHS, LHS + 336380006U, // <3,u,u,3>: Cost 1 vdup3 LHS + 1616099705U, // <3,u,u,4>: Cost 2 vext3 LHS, + 1611897219U, // <3,u,u,5>: Cost 2 vext3 LHS, + 537713037U, // <3,u,u,6>: Cost 1 vext3 LHS, RHS + 1659230607U, // <3,u,u,7>: Cost 2 vext3 LHS, + 537713051U, // <3,u,u,u>: Cost 1 vext3 LHS, LHS + 2691907584U, // <4,0,0,0>: Cost 3 vext3 <1,2,3,4>, <0,0,0,0> + 2691907594U, // <4,0,0,1>: Cost 3 vext3 <1,2,3,4>, <0,0,1,1> + 2691907604U, // <4,0,0,2>: Cost 3 vext3 <1,2,3,4>, <0,0,2,2> + 3306285199U, // <4,0,0,3>: Cost 4 vrev <3,0,0,4> + 2648064338U, // <4,0,0,4>: Cost 3 vext2 <5,1,4,0>, <0,4,1,5> + 3694600633U, // <4,0,0,5>: Cost 4 vext2 <0,5,4,0>, <0,5,4,0> + 3324203290U, // <4,0,0,6>: Cost 4 vrev <6,0,0,4> + 3330175987U, // <4,0,0,7>: Cost 4 vrev <7,0,0,4> + 2691907657U, // <4,0,0,u>: Cost 3 vext3 <1,2,3,4>, <0,0,u,1> + 2570715238U, // <4,0,1,0>: Cost 3 vext1 <3,4,0,1>, LHS + 2570716058U, // <4,0,1,1>: Cost 3 vext1 <3,4,0,1>, <1,2,3,4> + 1618165862U, // <4,0,1,2>: Cost 2 vext3 <1,2,3,4>, LHS + 2570717648U, // <4,0,1,3>: Cost 3 vext1 <3,4,0,1>, <3,4,0,1> + 2570718518U, // <4,0,1,4>: Cost 3 vext1 <3,4,0,1>, RHS + 2594607206U, // <4,0,1,5>: Cost 3 vext1 <7,4,0,1>, <5,6,7,4> + 3721807091U, // <4,0,1,6>: Cost 4 vext2 <5,1,4,0>, <1,6,5,7> + 2594608436U, // <4,0,1,7>: Cost 3 vext1 <7,4,0,1>, <7,4,0,1> + 1618165916U, // <4,0,1,u>: Cost 2 vext3 <1,2,3,4>, LHS + 2685714598U, // <4,0,2,0>: Cost 3 vext3 <0,2,0,4>, <0,2,0,4> + 3759530159U, // <4,0,2,1>: Cost 4 vext3 <0,2,1,4>, <0,2,1,4> + 2685862072U, // <4,0,2,2>: Cost 3 vext3 <0,2,2,4>, <0,2,2,4> + 2631476937U, // <4,0,2,3>: Cost 3 vext2 <2,3,4,0>, <2,3,4,0> + 2685714636U, // <4,0,2,4>: Cost 3 vext3 <0,2,0,4>, <0,2,4,6> + 3705218930U, // <4,0,2,5>: Cost 4 vext2 <2,3,4,0>, <2,5,4,7> + 2686157020U, // <4,0,2,6>: Cost 3 vext3 <0,2,6,4>, <0,2,6,4> + 3331503253U, // <4,0,2,7>: Cost 4 vrev <7,2,0,4> + 2686304494U, // <4,0,2,u>: Cost 3 vext3 <0,2,u,4>, <0,2,u,4> + 3632529510U, // <4,0,3,0>: Cost 4 vext1 <1,4,0,3>, LHS + 2686451968U, // <4,0,3,1>: Cost 3 vext3 <0,3,1,4>, <0,3,1,4> + 2228561577U, // <4,0,3,2>: Cost 3 vrev <2,3,0,4> + 3760341266U, // <4,0,3,3>: Cost 4 vext3 <0,3,3,4>, <0,3,3,4> + 3632532790U, // <4,0,3,4>: Cost 4 vext1 <1,4,0,3>, RHS + 3913254606U, // <4,0,3,5>: Cost 4 vuzpr <3,4,5,0>, <2,3,4,5> + 3705219740U, // <4,0,3,6>: Cost 4 vext2 <2,3,4,0>, <3,6,4,7> + 3332166886U, // <4,0,3,7>: Cost 4 vrev <7,3,0,4> + 2264397759U, // <4,0,3,u>: Cost 3 vrev + 2552823910U, // <4,0,4,0>: Cost 3 vext1 <0,4,0,4>, LHS + 2691907922U, // <4,0,4,1>: Cost 3 vext3 <1,2,3,4>, <0,4,1,5> + 2691907932U, // <4,0,4,2>: Cost 3 vext3 <1,2,3,4>, <0,4,2,6> + 3626567830U, // <4,0,4,3>: Cost 4 vext1 <0,4,0,4>, <3,0,1,2> + 2552827190U, // <4,0,4,4>: Cost 3 vext1 <0,4,0,4>, RHS + 2631478582U, // <4,0,4,5>: Cost 3 vext2 <2,3,4,0>, RHS + 3626570017U, // <4,0,4,6>: Cost 4 vext1 <0,4,0,4>, <6,0,1,2> + 3332830519U, // <4,0,4,7>: Cost 4 vrev <7,4,0,4> + 2552829742U, // <4,0,4,u>: Cost 3 vext1 <0,4,0,4>, LHS + 2570748006U, // <4,0,5,0>: Cost 3 vext1 <3,4,0,5>, LHS + 1839644774U, // <4,0,5,1>: Cost 2 vzipl RHS, LHS + 2913386660U, // <4,0,5,2>: Cost 3 vzipl RHS, <0,2,0,2> + 2570750102U, // <4,0,5,3>: Cost 3 vext1 <3,4,0,5>, <3,0,1,2> + 2570751286U, // <4,0,5,4>: Cost 3 vext1 <3,4,0,5>, RHS + 3987128750U, // <4,0,5,5>: Cost 4 vzipl RHS, <0,5,2,7> + 3987128822U, // <4,0,5,6>: Cost 4 vzipl RHS, <0,6,1,7> + 2594641208U, // <4,0,5,7>: Cost 3 vext1 <7,4,0,5>, <7,4,0,5> + 1839645341U, // <4,0,5,u>: Cost 2 vzipl RHS, LHS + 2552840294U, // <4,0,6,0>: Cost 3 vext1 <0,4,0,6>, LHS + 3047604234U, // <4,0,6,1>: Cost 3 vtrnl RHS, <0,0,1,1> + 1973862502U, // <4,0,6,2>: Cost 2 vtrnl RHS, LHS + 2570758613U, // <4,0,6,3>: Cost 3 vext1 <3,4,0,6>, <3,4,0,6> + 2552843574U, // <4,0,6,4>: Cost 3 vext1 <0,4,0,6>, RHS + 2656694991U, // <4,0,6,5>: Cost 3 vext2 <6,5,4,0>, <6,5,4,0> + 3721810744U, // <4,0,6,6>: Cost 4 vext2 <5,1,4,0>, <6,6,6,6> + 2658022257U, // <4,0,6,7>: Cost 3 vext2 <6,7,4,0>, <6,7,4,0> + 1973862556U, // <4,0,6,u>: Cost 2 vtrnl RHS, LHS + 3721810938U, // <4,0,7,0>: Cost 4 vext2 <5,1,4,0>, <7,0,1,2> + 2689106500U, // <4,0,7,1>: Cost 3 vext3 <0,7,1,4>, <0,7,1,4> + 4122034278U, // <4,0,7,2>: Cost 4 vtrnl <4,6,7,1>, LHS + 3310930630U, // <4,0,7,3>: Cost 4 vrev <3,7,0,4> + 3721811302U, // <4,0,7,4>: Cost 4 vext2 <5,1,4,0>, <7,4,5,6> + 3721811345U, // <4,0,7,5>: Cost 4 vext2 <5,1,4,0>, <7,5,1,4> + 2255106897U, // <4,0,7,6>: Cost 3 vrev <6,7,0,4> + 3721811564U, // <4,0,7,7>: Cost 4 vext2 <5,1,4,0>, <7,7,7,7> + 2668639912U, // <4,0,7,u>: Cost 3 vext2 , <7,u,5,4> + 2552856678U, // <4,0,u,0>: Cost 3 vext1 <0,4,0,u>, LHS + 1841635430U, // <4,0,u,1>: Cost 2 vzipl RHS, LHS + 1618166429U, // <4,0,u,2>: Cost 2 vext3 <1,2,3,4>, LHS + 2570774999U, // <4,0,u,3>: Cost 3 vext1 <3,4,0,u>, <3,4,0,u> + 2552859958U, // <4,0,u,4>: Cost 3 vext1 <0,4,0,u>, RHS + 2631481498U, // <4,0,u,5>: Cost 3 vext2 <2,3,4,0>, RHS + 2255770530U, // <4,0,u,6>: Cost 3 vrev <6,u,0,4> + 2594665787U, // <4,0,u,7>: Cost 3 vext1 <7,4,0,u>, <7,4,0,u> + 1618166483U, // <4,0,u,u>: Cost 2 vext3 <1,2,3,4>, LHS + 2617548837U, // <4,1,0,0>: Cost 3 vext2 <0,0,4,1>, <0,0,4,1> + 2622857318U, // <4,1,0,1>: Cost 3 vext2 <0,u,4,1>, LHS + 3693281484U, // <4,1,0,2>: Cost 4 vext2 <0,3,4,1>, <0,2,4,6> + 2232617112U, // <4,1,0,3>: Cost 3 vrev <3,0,1,4> + 2622857554U, // <4,1,0,4>: Cost 3 vext2 <0,u,4,1>, <0,4,1,5> + 3694608826U, // <4,1,0,5>: Cost 4 vext2 <0,5,4,1>, <0,5,4,1> + 3695272459U, // <4,1,0,6>: Cost 4 vext2 <0,6,4,1>, <0,6,4,1> + 2256507900U, // <4,1,0,7>: Cost 3 vrev <7,0,1,4> + 2622857885U, // <4,1,0,u>: Cost 3 vext2 <0,u,4,1>, LHS + 2215362654U, // <4,1,1,0>: Cost 3 vrev <0,1,1,4> + 2221335351U, // <4,1,1,1>: Cost 3 vrev <1,1,1,4> + 2631484314U, // <4,1,1,2>: Cost 3 vext2 <2,3,4,1>, <1,2,3,4> + 2691908424U, // <4,1,1,3>: Cost 3 vext3 <1,2,3,4>, <1,1,3,3> + 3696600125U, // <4,1,1,4>: Cost 4 vext2 <0,u,4,1>, <1,4,3,5> + 3696600175U, // <4,1,1,5>: Cost 4 vext2 <0,u,4,1>, <1,5,0,1> + 3696600307U, // <4,1,1,6>: Cost 4 vext2 <0,u,4,1>, <1,6,5,7> + 3330913357U, // <4,1,1,7>: Cost 4 vrev <7,1,1,4> + 2691908469U, // <4,1,1,u>: Cost 3 vext3 <1,2,3,4>, <1,1,u,3> + 2570797158U, // <4,1,2,0>: Cost 3 vext1 <3,4,1,2>, LHS + 2570797978U, // <4,1,2,1>: Cost 3 vext1 <3,4,1,2>, <1,2,3,4> + 3696600680U, // <4,1,2,2>: Cost 4 vext2 <0,u,4,1>, <2,2,2,2> + 1618166682U, // <4,1,2,3>: Cost 2 vext3 <1,2,3,4>, <1,2,3,4> + 2570800438U, // <4,1,2,4>: Cost 3 vext1 <3,4,1,2>, RHS + 3765650347U, // <4,1,2,5>: Cost 4 vext3 <1,2,3,4>, <1,2,5,3> + 3696601018U, // <4,1,2,6>: Cost 4 vext2 <0,u,4,1>, <2,6,3,7> + 3331576990U, // <4,1,2,7>: Cost 4 vrev <7,2,1,4> + 1618535367U, // <4,1,2,u>: Cost 2 vext3 <1,2,u,4>, <1,2,u,4> + 2564833382U, // <4,1,3,0>: Cost 3 vext1 <2,4,1,3>, LHS + 2691908568U, // <4,1,3,1>: Cost 3 vext3 <1,2,3,4>, <1,3,1,3> + 2691908578U, // <4,1,3,2>: Cost 3 vext3 <1,2,3,4>, <1,3,2,4> + 2692572139U, // <4,1,3,3>: Cost 3 vext3 <1,3,3,4>, <1,3,3,4> + 2564836662U, // <4,1,3,4>: Cost 3 vext1 <2,4,1,3>, RHS + 2691908608U, // <4,1,3,5>: Cost 3 vext3 <1,2,3,4>, <1,3,5,7> + 2588725862U, // <4,1,3,6>: Cost 3 vext1 <6,4,1,3>, <6,4,1,3> + 3662468090U, // <4,1,3,7>: Cost 4 vext1 <6,4,1,3>, <7,0,1,2> + 2691908631U, // <4,1,3,u>: Cost 3 vext3 <1,2,3,4>, <1,3,u,3> + 3760194590U, // <4,1,4,0>: Cost 4 vext3 <0,3,1,4>, <1,4,0,1> + 3693947874U, // <4,1,4,1>: Cost 4 vext2 <0,4,4,1>, <4,1,5,0> + 3765650484U, // <4,1,4,2>: Cost 4 vext3 <1,2,3,4>, <1,4,2,5> + 3113877606U, // <4,1,4,3>: Cost 3 vtrnr <4,4,4,4>, LHS + 3760194630U, // <4,1,4,4>: Cost 4 vext3 <0,3,1,4>, <1,4,4,5> + 2622860598U, // <4,1,4,5>: Cost 3 vext2 <0,u,4,1>, RHS + 3767198807U, // <4,1,4,6>: Cost 4 vext3 <1,4,6,4>, <1,4,6,4> + 3800007772U, // <4,1,4,7>: Cost 4 vext3 <7,0,1,4>, <1,4,7,0> + 2622860841U, // <4,1,4,u>: Cost 3 vext2 <0,u,4,1>, RHS + 1479164006U, // <4,1,5,0>: Cost 2 vext1 <0,4,1,5>, LHS + 2552906548U, // <4,1,5,1>: Cost 3 vext1 <0,4,1,5>, <1,1,1,1> + 2552907299U, // <4,1,5,2>: Cost 3 vext1 <0,4,1,5>, <2,1,3,5> + 2552907926U, // <4,1,5,3>: Cost 3 vext1 <0,4,1,5>, <3,0,1,2> + 1479167286U, // <4,1,5,4>: Cost 2 vext1 <0,4,1,5>, RHS + 2552909490U, // <4,1,5,5>: Cost 3 vext1 <0,4,1,5>, <5,1,4,0> + 2600686074U, // <4,1,5,6>: Cost 3 vext1 , <6,2,7,3> + 2600686586U, // <4,1,5,7>: Cost 3 vext1 , <7,0,1,2> + 1479169838U, // <4,1,5,u>: Cost 2 vext1 <0,4,1,5>, LHS + 2552914022U, // <4,1,6,0>: Cost 3 vext1 <0,4,1,6>, LHS + 2558886708U, // <4,1,6,1>: Cost 3 vext1 <1,4,1,6>, <1,1,1,1> + 4028205206U, // <4,1,6,2>: Cost 4 vzipr <0,2,4,6>, <3,0,1,2> + 3089858662U, // <4,1,6,3>: Cost 3 vtrnr <0,4,2,6>, LHS + 2552917302U, // <4,1,6,4>: Cost 3 vext1 <0,4,1,6>, RHS + 3047605248U, // <4,1,6,5>: Cost 3 vtrnl RHS, <1,3,5,7> + 3626660235U, // <4,1,6,6>: Cost 4 vext1 <0,4,1,6>, <6,1,4,0> + 3721155406U, // <4,1,6,7>: Cost 4 vext2 <5,0,4,1>, <6,7,0,1> + 2552919854U, // <4,1,6,u>: Cost 3 vext1 <0,4,1,6>, LHS + 2659357716U, // <4,1,7,0>: Cost 3 vext2 <7,0,4,1>, <7,0,4,1> + 3733763173U, // <4,1,7,1>: Cost 4 vext2 <7,1,4,1>, <7,1,4,1> + 3734426806U, // <4,1,7,2>: Cost 4 vext2 <7,2,4,1>, <7,2,4,1> + 2695226671U, // <4,1,7,3>: Cost 3 vext3 <1,7,3,4>, <1,7,3,4> + 3721155942U, // <4,1,7,4>: Cost 4 vext2 <5,0,4,1>, <7,4,5,6> + 3721155976U, // <4,1,7,5>: Cost 4 vext2 <5,0,4,1>, <7,5,0,4> + 3721156102U, // <4,1,7,6>: Cost 4 vext2 <5,0,4,1>, <7,6,5,4> + 3721156204U, // <4,1,7,7>: Cost 4 vext2 <5,0,4,1>, <7,7,7,7> + 2659357716U, // <4,1,7,u>: Cost 3 vext2 <7,0,4,1>, <7,0,4,1> + 1479188582U, // <4,1,u,0>: Cost 2 vext1 <0,4,1,u>, LHS + 2552931124U, // <4,1,u,1>: Cost 3 vext1 <0,4,1,u>, <1,1,1,1> + 2552931944U, // <4,1,u,2>: Cost 3 vext1 <0,4,1,u>, <2,2,2,2> + 1622148480U, // <4,1,u,3>: Cost 2 vext3 <1,u,3,4>, <1,u,3,4> + 1479191862U, // <4,1,u,4>: Cost 2 vext1 <0,4,1,u>, RHS + 2622863514U, // <4,1,u,5>: Cost 3 vext2 <0,u,4,1>, RHS + 2588766827U, // <4,1,u,6>: Cost 3 vext1 <6,4,1,u>, <6,4,1,u> + 2261816964U, // <4,1,u,7>: Cost 3 vrev <7,u,1,4> + 1479194414U, // <4,1,u,u>: Cost 2 vext1 <0,4,1,u>, LHS + 2588770406U, // <4,2,0,0>: Cost 3 vext1 <6,4,2,0>, LHS + 2622865510U, // <4,2,0,1>: Cost 3 vext2 <0,u,4,2>, LHS + 2622865612U, // <4,2,0,2>: Cost 3 vext2 <0,u,4,2>, <0,2,4,6> + 2232690849U, // <4,2,0,3>: Cost 3 vrev <3,0,2,4> + 2635473244U, // <4,2,0,4>: Cost 3 vext2 <3,0,4,2>, <0,4,2,6> + 3765650918U, // <4,2,0,5>: Cost 4 vext3 <1,2,3,4>, <2,0,5,7> + 2250608940U, // <4,2,0,6>: Cost 3 vrev <6,0,2,4> + 2256581637U, // <4,2,0,7>: Cost 3 vrev <7,0,2,4> + 2622866077U, // <4,2,0,u>: Cost 3 vext2 <0,u,4,2>, LHS + 2215436391U, // <4,2,1,0>: Cost 3 vrev <0,1,2,4> + 3696608052U, // <4,2,1,1>: Cost 4 vext2 <0,u,4,2>, <1,1,1,1> + 3696608150U, // <4,2,1,2>: Cost 4 vext2 <0,u,4,2>, <1,2,3,0> + 3895574630U, // <4,2,1,3>: Cost 4 vuzpr <0,4,u,2>, LHS + 2691909162U, // <4,2,1,4>: Cost 3 vext3 <1,2,3,4>, <2,1,4,3> + 3696608400U, // <4,2,1,5>: Cost 4 vext2 <0,u,4,2>, <1,5,3,7> + 3760784956U, // <4,2,1,6>: Cost 4 vext3 <0,4,0,4>, <2,1,6,3> + 3330987094U, // <4,2,1,7>: Cost 4 vrev <7,1,2,4> + 2263217967U, // <4,2,1,u>: Cost 3 vrev + 2216100024U, // <4,2,2,0>: Cost 3 vrev <0,2,2,4> + 3696608828U, // <4,2,2,1>: Cost 4 vext2 <0,u,4,2>, <2,1,6,3> + 2691909224U, // <4,2,2,2>: Cost 3 vext3 <1,2,3,4>, <2,2,2,2> + 2691909234U, // <4,2,2,3>: Cost 3 vext3 <1,2,3,4>, <2,2,3,3> + 3759605368U, // <4,2,2,4>: Cost 4 vext3 <0,2,2,4>, <2,2,4,0> + 3696609156U, // <4,2,2,5>: Cost 4 vext2 <0,u,4,2>, <2,5,6,7> + 3760785040U, // <4,2,2,6>: Cost 4 vext3 <0,4,0,4>, <2,2,6,6> + 3331650727U, // <4,2,2,7>: Cost 4 vrev <7,2,2,4> + 2691909279U, // <4,2,2,u>: Cost 3 vext3 <1,2,3,4>, <2,2,u,3> + 2691909286U, // <4,2,3,0>: Cost 3 vext3 <1,2,3,4>, <2,3,0,1> + 3764840111U, // <4,2,3,1>: Cost 4 vext3 <1,1,1,4>, <2,3,1,1> + 3696609590U, // <4,2,3,2>: Cost 4 vext2 <0,u,4,2>, <3,2,1,0> + 2698544836U, // <4,2,3,3>: Cost 3 vext3 <2,3,3,4>, <2,3,3,4> + 2685863630U, // <4,2,3,4>: Cost 3 vext3 <0,2,2,4>, <2,3,4,5> + 3772434134U, // <4,2,3,5>: Cost 4 vext3 <2,3,5,4>, <2,3,5,4> + 3772507871U, // <4,2,3,6>: Cost 4 vext3 <2,3,6,4>, <2,3,6,4> + 2698839784U, // <4,2,3,7>: Cost 3 vext3 <2,3,7,4>, <2,3,7,4> + 2691909358U, // <4,2,3,u>: Cost 3 vext3 <1,2,3,4>, <2,3,u,1> + 2564915302U, // <4,2,4,0>: Cost 3 vext1 <2,4,2,4>, LHS + 2564916122U, // <4,2,4,1>: Cost 3 vext1 <2,4,2,4>, <1,2,3,4> + 2564917004U, // <4,2,4,2>: Cost 3 vext1 <2,4,2,4>, <2,4,2,4> + 2699208469U, // <4,2,4,3>: Cost 3 vext3 <2,4,3,4>, <2,4,3,4> + 2564918582U, // <4,2,4,4>: Cost 3 vext1 <2,4,2,4>, RHS + 2622868790U, // <4,2,4,5>: Cost 3 vext2 <0,u,4,2>, RHS + 2699429680U, // <4,2,4,6>: Cost 3 vext3 <2,4,6,4>, <2,4,6,4> + 3800082229U, // <4,2,4,7>: Cost 4 vext3 <7,0,2,4>, <2,4,7,0> + 2622869033U, // <4,2,4,u>: Cost 3 vext2 <0,u,4,2>, RHS + 2552979558U, // <4,2,5,0>: Cost 3 vext1 <0,4,2,5>, LHS + 2558952342U, // <4,2,5,1>: Cost 3 vext1 <1,4,2,5>, <1,2,3,0> + 2564925032U, // <4,2,5,2>: Cost 3 vext1 <2,4,2,5>, <2,2,2,2> + 2967060582U, // <4,2,5,3>: Cost 3 vzipr <2,3,4,5>, LHS + 2552982838U, // <4,2,5,4>: Cost 3 vext1 <0,4,2,5>, RHS + 3626725123U, // <4,2,5,5>: Cost 4 vext1 <0,4,2,5>, <5,2,4,0> + 2913388474U, // <4,2,5,6>: Cost 3 vzipl RHS, <2,6,3,7> + 3895577910U, // <4,2,5,7>: Cost 4 vuzpr <0,4,u,2>, RHS + 2552985390U, // <4,2,5,u>: Cost 3 vext1 <0,4,2,5>, LHS + 1479245926U, // <4,2,6,0>: Cost 2 vext1 <0,4,2,6>, LHS + 2552988468U, // <4,2,6,1>: Cost 3 vext1 <0,4,2,6>, <1,1,1,1> + 2552989288U, // <4,2,6,2>: Cost 3 vext1 <0,4,2,6>, <2,2,2,2> + 2954461286U, // <4,2,6,3>: Cost 3 vzipr <0,2,4,6>, LHS + 1479249206U, // <4,2,6,4>: Cost 2 vext1 <0,4,2,6>, RHS + 2600767184U, // <4,2,6,5>: Cost 3 vext1 , <5,1,7,3> + 2552992220U, // <4,2,6,6>: Cost 3 vext1 <0,4,2,6>, <6,2,4,0> + 2600768506U, // <4,2,6,7>: Cost 3 vext1 , <7,0,1,2> + 1479251758U, // <4,2,6,u>: Cost 2 vext1 <0,4,2,6>, LHS + 2659365909U, // <4,2,7,0>: Cost 3 vext2 <7,0,4,2>, <7,0,4,2> + 3733771366U, // <4,2,7,1>: Cost 4 vext2 <7,1,4,2>, <7,1,4,2> + 3734434999U, // <4,2,7,2>: Cost 4 vext2 <7,2,4,2>, <7,2,4,2> + 2701199368U, // <4,2,7,3>: Cost 3 vext3 <2,7,3,4>, <2,7,3,4> + 4175774618U, // <4,2,7,4>: Cost 4 vtrnr <2,4,5,7>, <1,2,3,4> + 3323023498U, // <4,2,7,5>: Cost 4 vrev <5,7,2,4> + 3727136217U, // <4,2,7,6>: Cost 4 vext2 <6,0,4,2>, <7,6,0,4> + 3727136364U, // <4,2,7,7>: Cost 4 vext2 <6,0,4,2>, <7,7,7,7> + 2659365909U, // <4,2,7,u>: Cost 3 vext2 <7,0,4,2>, <7,0,4,2> + 1479262310U, // <4,2,u,0>: Cost 2 vext1 <0,4,2,u>, LHS + 2553004852U, // <4,2,u,1>: Cost 3 vext1 <0,4,2,u>, <1,1,1,1> + 2553005672U, // <4,2,u,2>: Cost 3 vext1 <0,4,2,u>, <2,2,2,2> + 2954477670U, // <4,2,u,3>: Cost 3 vzipr <0,2,4,u>, LHS + 1479265590U, // <4,2,u,4>: Cost 2 vext1 <0,4,2,u>, RHS + 2622871706U, // <4,2,u,5>: Cost 3 vext2 <0,u,4,2>, RHS + 2702084212U, // <4,2,u,6>: Cost 3 vext3 <2,u,6,4>, <2,u,6,4> + 2600784890U, // <4,2,u,7>: Cost 3 vext1 , <7,0,1,2> + 1479268142U, // <4,2,u,u>: Cost 2 vext1 <0,4,2,u>, LHS + 3765651595U, // <4,3,0,0>: Cost 4 vext3 <1,2,3,4>, <3,0,0,0> + 2691909782U, // <4,3,0,1>: Cost 3 vext3 <1,2,3,4>, <3,0,1,2> + 2702452897U, // <4,3,0,2>: Cost 3 vext3 <3,0,2,4>, <3,0,2,4> + 3693297946U, // <4,3,0,3>: Cost 4 vext2 <0,3,4,3>, <0,3,4,3> + 3760711856U, // <4,3,0,4>: Cost 4 vext3 <0,3,u,4>, <3,0,4,1> + 4181690062U, // <4,3,0,5>: Cost 4 vtrnr <3,4,5,0>, <2,3,4,5> + 3324424501U, // <4,3,0,6>: Cost 4 vrev <6,0,3,4> + 3330397198U, // <4,3,0,7>: Cost 4 vrev <7,0,3,4> + 2691909845U, // <4,3,0,u>: Cost 3 vext3 <1,2,3,4>, <3,0,u,2> + 3626762342U, // <4,3,1,0>: Cost 4 vext1 <0,4,3,1>, LHS + 3764840678U, // <4,3,1,1>: Cost 4 vext3 <1,1,1,4>, <3,1,1,1> + 2630173594U, // <4,3,1,2>: Cost 3 vext2 <2,1,4,3>, <1,2,3,4> + 2233428219U, // <4,3,1,3>: Cost 3 vrev <3,1,3,4> + 3760195840U, // <4,3,1,4>: Cost 4 vext3 <0,3,1,4>, <3,1,4,0> + 3765651724U, // <4,3,1,5>: Cost 4 vext3 <1,2,3,4>, <3,1,5,3> + 3325088134U, // <4,3,1,6>: Cost 4 vrev <6,1,3,4> + 3769633054U, // <4,3,1,7>: Cost 4 vext3 <1,u,3,4>, <3,1,7,3> + 2703558952U, // <4,3,1,u>: Cost 3 vext3 <3,1,u,4>, <3,1,u,4> + 2582888550U, // <4,3,2,0>: Cost 3 vext1 <5,4,3,2>, LHS + 1148404634U, // <4,3,2,1>: Cost 2 vrev <1,2,3,4> + 2582890190U, // <4,3,2,2>: Cost 3 vext1 <5,4,3,2>, <2,3,4,5> + 2234091852U, // <4,3,2,3>: Cost 3 vrev <3,2,3,4> + 2582891830U, // <4,3,2,4>: Cost 3 vext1 <5,4,3,2>, RHS + 2246037246U, // <4,3,2,5>: Cost 3 vrev <5,2,3,4> + 3765651814U, // <4,3,2,6>: Cost 4 vext3 <1,2,3,4>, <3,2,6,3> + 2257982640U, // <4,3,2,7>: Cost 3 vrev <7,2,3,4> + 1190213513U, // <4,3,2,u>: Cost 2 vrev + 3765651839U, // <4,3,3,0>: Cost 4 vext3 <1,2,3,4>, <3,3,0,1> + 2222810091U, // <4,3,3,1>: Cost 3 vrev <1,3,3,4> + 2228782788U, // <4,3,3,2>: Cost 3 vrev <2,3,3,4> + 2691910044U, // <4,3,3,3>: Cost 3 vext3 <1,2,3,4>, <3,3,3,3> + 2704591270U, // <4,3,3,4>: Cost 3 vext3 <3,3,4,4>, <3,3,4,4> + 3769633202U, // <4,3,3,5>: Cost 4 vext3 <1,u,3,4>, <3,3,5,7> + 3703917212U, // <4,3,3,6>: Cost 4 vext2 <2,1,4,3>, <3,6,4,7> + 3769633220U, // <4,3,3,7>: Cost 4 vext3 <1,u,3,4>, <3,3,7,7> + 2264618970U, // <4,3,3,u>: Cost 3 vrev + 2691910096U, // <4,3,4,0>: Cost 3 vext3 <1,2,3,4>, <3,4,0,1> + 2691910106U, // <4,3,4,1>: Cost 3 vext3 <1,2,3,4>, <3,4,1,2> + 2564990741U, // <4,3,4,2>: Cost 3 vext1 <2,4,3,4>, <2,4,3,4> + 3765651946U, // <4,3,4,3>: Cost 4 vext3 <1,2,3,4>, <3,4,3,0> + 2691910136U, // <4,3,4,4>: Cost 3 vext3 <1,2,3,4>, <3,4,4,5> + 2686454274U, // <4,3,4,5>: Cost 3 vext3 <0,3,1,4>, <3,4,5,6> + 2705402377U, // <4,3,4,6>: Cost 3 vext3 <3,4,6,4>, <3,4,6,4> + 3801483792U, // <4,3,4,7>: Cost 4 vext3 <7,2,3,4>, <3,4,7,2> + 2691910168U, // <4,3,4,u>: Cost 3 vext3 <1,2,3,4>, <3,4,u,1> + 2559025254U, // <4,3,5,0>: Cost 3 vext1 <1,4,3,5>, LHS + 2559026237U, // <4,3,5,1>: Cost 3 vext1 <1,4,3,5>, <1,4,3,5> + 2564998862U, // <4,3,5,2>: Cost 3 vext1 <2,4,3,5>, <2,3,4,5> + 2570971548U, // <4,3,5,3>: Cost 3 vext1 <3,4,3,5>, <3,3,3,3> + 2559028534U, // <4,3,5,4>: Cost 3 vext1 <1,4,3,5>, RHS + 4163519477U, // <4,3,5,5>: Cost 4 vtrnr <0,4,1,5>, <1,3,4,5> + 3987131000U, // <4,3,5,6>: Cost 4 vzipl RHS, <3,6,0,7> + 2706139747U, // <4,3,5,7>: Cost 3 vext3 <3,5,7,4>, <3,5,7,4> + 2559031086U, // <4,3,5,u>: Cost 3 vext1 <1,4,3,5>, LHS + 2559033446U, // <4,3,6,0>: Cost 3 vext1 <1,4,3,6>, LHS + 2559034430U, // <4,3,6,1>: Cost 3 vext1 <1,4,3,6>, <1,4,3,6> + 2565007127U, // <4,3,6,2>: Cost 3 vext1 <2,4,3,6>, <2,4,3,6> + 2570979740U, // <4,3,6,3>: Cost 3 vext1 <3,4,3,6>, <3,3,3,3> + 2559036726U, // <4,3,6,4>: Cost 3 vext1 <1,4,3,6>, RHS + 3047606786U, // <4,3,6,5>: Cost 3 vtrnl RHS, <3,4,5,6> + 4028203932U, // <4,3,6,6>: Cost 4 vzipr <0,2,4,6>, <1,2,3,6> + 2706803380U, // <4,3,6,7>: Cost 3 vext3 <3,6,7,4>, <3,6,7,4> + 2559039278U, // <4,3,6,u>: Cost 3 vext1 <1,4,3,6>, LHS + 3769633475U, // <4,3,7,0>: Cost 4 vext3 <1,u,3,4>, <3,7,0,1> + 2225464623U, // <4,3,7,1>: Cost 3 vrev <1,7,3,4> + 2231437320U, // <4,3,7,2>: Cost 3 vrev <2,7,3,4> + 3769633508U, // <4,3,7,3>: Cost 4 vext3 <1,u,3,4>, <3,7,3,7> + 3769633515U, // <4,3,7,4>: Cost 4 vext3 <1,u,3,4>, <3,7,4,5> + 3769633526U, // <4,3,7,5>: Cost 4 vext3 <1,u,3,4>, <3,7,5,7> + 2255328108U, // <4,3,7,6>: Cost 3 vrev <6,7,3,4> + 3781208837U, // <4,3,7,7>: Cost 4 vext3 <3,7,7,4>, <3,7,7,4> + 2267273502U, // <4,3,7,u>: Cost 3 vrev + 2559049830U, // <4,3,u,0>: Cost 3 vext1 <1,4,3,u>, LHS + 1152386432U, // <4,3,u,1>: Cost 2 vrev <1,u,3,4> + 2565023513U, // <4,3,u,2>: Cost 3 vext1 <2,4,3,u>, <2,4,3,u> + 2238073650U, // <4,3,u,3>: Cost 3 vrev <3,u,3,4> + 2559053110U, // <4,3,u,4>: Cost 3 vext1 <1,4,3,u>, RHS + 2691910470U, // <4,3,u,5>: Cost 3 vext3 <1,2,3,4>, <3,u,5,6> + 2255991741U, // <4,3,u,6>: Cost 3 vrev <6,u,3,4> + 2708130646U, // <4,3,u,7>: Cost 3 vext3 <3,u,7,4>, <3,u,7,4> + 1194195311U, // <4,3,u,u>: Cost 2 vrev + 2617573416U, // <4,4,0,0>: Cost 3 vext2 <0,0,4,4>, <0,0,4,4> + 1570373734U, // <4,4,0,1>: Cost 2 vext2 <4,4,4,4>, LHS + 2779676774U, // <4,4,0,2>: Cost 3 vuzpl <4,6,4,6>, LHS + 3760196480U, // <4,4,0,3>: Cost 4 vext3 <0,3,1,4>, <4,0,3,1> + 2576977100U, // <4,4,0,4>: Cost 3 vext1 <4,4,4,0>, <4,4,4,0> + 2718747538U, // <4,4,0,5>: Cost 3 vext3 <5,6,7,4>, <4,0,5,1> + 2718747548U, // <4,4,0,6>: Cost 3 vext3 <5,6,7,4>, <4,0,6,2> + 3798608809U, // <4,4,0,7>: Cost 4 vext3 <6,7,0,4>, <4,0,7,6> + 1570374301U, // <4,4,0,u>: Cost 2 vext2 <4,4,4,4>, LHS + 3626836070U, // <4,4,1,0>: Cost 4 vext1 <0,4,4,1>, LHS + 2644116276U, // <4,4,1,1>: Cost 3 vext2 <4,4,4,4>, <1,1,1,1> + 2691910602U, // <4,4,1,2>: Cost 3 vext3 <1,2,3,4>, <4,1,2,3> + 2644116440U, // <4,4,1,3>: Cost 3 vext2 <4,4,4,4>, <1,3,1,3> + 2711227356U, // <4,4,1,4>: Cost 3 vext3 <4,4,4,4>, <4,1,4,3> + 2709310438U, // <4,4,1,5>: Cost 3 vext3 <4,1,5,4>, <4,1,5,4> + 3765652462U, // <4,4,1,6>: Cost 4 vext3 <1,2,3,4>, <4,1,6,3> + 3768970231U, // <4,4,1,7>: Cost 4 vext3 <1,7,3,4>, <4,1,7,3> + 2695891968U, // <4,4,1,u>: Cost 3 vext3 <1,u,3,4>, <4,1,u,3> + 3703260634U, // <4,4,2,0>: Cost 4 vext2 <2,0,4,4>, <2,0,4,4> + 3705251370U, // <4,4,2,1>: Cost 4 vext2 <2,3,4,4>, <2,1,4,3> + 2644117096U, // <4,4,2,2>: Cost 3 vext2 <4,4,4,4>, <2,2,2,2> + 2631509709U, // <4,4,2,3>: Cost 3 vext2 <2,3,4,4>, <2,3,4,4> + 2644117269U, // <4,4,2,4>: Cost 3 vext2 <4,4,4,4>, <2,4,3,4> + 3705251698U, // <4,4,2,5>: Cost 4 vext2 <2,3,4,4>, <2,5,4,7> + 2710047808U, // <4,4,2,6>: Cost 3 vext3 <4,2,6,4>, <4,2,6,4> + 3783863369U, // <4,4,2,7>: Cost 4 vext3 <4,2,7,4>, <4,2,7,4> + 2634827874U, // <4,4,2,u>: Cost 3 vext2 <2,u,4,4>, <2,u,4,4> + 2644117654U, // <4,4,3,0>: Cost 3 vext2 <4,4,4,4>, <3,0,1,2> + 3638797210U, // <4,4,3,1>: Cost 4 vext1 <2,4,4,3>, <1,2,3,4> + 2691910762U, // <4,4,3,2>: Cost 3 vext3 <1,2,3,4>, <4,3,2,1> + 2637482406U, // <4,4,3,3>: Cost 3 vext2 <3,3,4,4>, <3,3,4,4> + 2638146039U, // <4,4,3,4>: Cost 3 vext2 <3,4,4,4>, <3,4,4,4> + 3913287374U, // <4,4,3,5>: Cost 4 vuzpr <3,4,5,4>, <2,3,4,5> + 3765652625U, // <4,4,3,6>: Cost 4 vext3 <1,2,3,4>, <4,3,6,4> + 3798830236U, // <4,4,3,7>: Cost 4 vext3 <6,7,3,4>, <4,3,7,6> + 2695892128U, // <4,4,3,u>: Cost 3 vext3 <1,u,3,4>, <4,3,u,1> + 1503264870U, // <4,4,4,0>: Cost 2 vext1 <4,4,4,4>, LHS + 2577007514U, // <4,4,4,1>: Cost 3 vext1 <4,4,4,4>, <1,2,3,4> + 2577008232U, // <4,4,4,2>: Cost 3 vext1 <4,4,4,4>, <2,2,2,2> + 2235492855U, // <4,4,4,3>: Cost 3 vrev <3,4,4,4> + 161926454U, // <4,4,4,4>: Cost 1 vdup0 RHS + 1570377014U, // <4,4,4,5>: Cost 2 vext2 <4,4,4,4>, RHS + 2779680054U, // <4,4,4,6>: Cost 3 vuzpl <4,6,4,6>, RHS + 2259383643U, // <4,4,4,7>: Cost 3 vrev <7,4,4,4> + 161926454U, // <4,4,4,u>: Cost 1 vdup0 RHS + 2571042918U, // <4,4,5,0>: Cost 3 vext1 <3,4,4,5>, LHS + 2571043738U, // <4,4,5,1>: Cost 3 vext1 <3,4,4,5>, <1,2,3,4> + 3638814495U, // <4,4,5,2>: Cost 4 vext1 <2,4,4,5>, <2,4,4,5> + 2571045368U, // <4,4,5,3>: Cost 3 vext1 <3,4,4,5>, <3,4,4,5> + 2571046198U, // <4,4,5,4>: Cost 3 vext1 <3,4,4,5>, RHS + 1839648054U, // <4,4,5,5>: Cost 2 vzipl RHS, RHS + 1618169142U, // <4,4,5,6>: Cost 2 vext3 <1,2,3,4>, RHS + 2594936156U, // <4,4,5,7>: Cost 3 vext1 <7,4,4,5>, <7,4,4,5> + 1618169160U, // <4,4,5,u>: Cost 2 vext3 <1,2,3,4>, RHS + 2553135206U, // <4,4,6,0>: Cost 3 vext1 <0,4,4,6>, LHS + 3626877748U, // <4,4,6,1>: Cost 4 vext1 <0,4,4,6>, <1,1,1,1> + 2565080782U, // <4,4,6,2>: Cost 3 vext1 <2,4,4,6>, <2,3,4,5> + 2571053561U, // <4,4,6,3>: Cost 3 vext1 <3,4,4,6>, <3,4,4,6> + 2553138486U, // <4,4,6,4>: Cost 3 vext1 <0,4,4,6>, RHS + 3047607186U, // <4,4,6,5>: Cost 3 vtrnl RHS, <4,0,5,1> + 1973865782U, // <4,4,6,6>: Cost 2 vtrnl RHS, RHS + 2658055029U, // <4,4,6,7>: Cost 3 vext2 <6,7,4,4>, <6,7,4,4> + 1973865800U, // <4,4,6,u>: Cost 2 vtrnl RHS, RHS + 2644120570U, // <4,4,7,0>: Cost 3 vext2 <4,4,4,4>, <7,0,1,2> + 3638829978U, // <4,4,7,1>: Cost 4 vext1 <2,4,4,7>, <1,2,3,4> + 3638830881U, // <4,4,7,2>: Cost 4 vext1 <2,4,4,7>, <2,4,4,7> + 3790499259U, // <4,4,7,3>: Cost 4 vext3 <5,3,7,4>, <4,7,3,5> + 2662036827U, // <4,4,7,4>: Cost 3 vext2 <7,4,4,4>, <7,4,4,4> + 2713292236U, // <4,4,7,5>: Cost 3 vext3 <4,7,5,4>, <4,7,5,4> + 2718748118U, // <4,4,7,6>: Cost 3 vext3 <5,6,7,4>, <4,7,6,5> + 2644121196U, // <4,4,7,7>: Cost 3 vext2 <4,4,4,4>, <7,7,7,7> + 2720075240U, // <4,4,7,u>: Cost 3 vext3 <5,u,7,4>, <4,7,u,5> + 1503297638U, // <4,4,u,0>: Cost 2 vext1 <4,4,4,u>, LHS + 1570379566U, // <4,4,u,1>: Cost 2 vext2 <4,4,4,4>, LHS + 2692279807U, // <4,4,u,2>: Cost 3 vext3 <1,2,u,4>, <4,u,2,1> + 2571069947U, // <4,4,u,3>: Cost 3 vext1 <3,4,4,u>, <3,4,4,u> + 161926454U, // <4,4,u,4>: Cost 1 vdup0 RHS + 1841638710U, // <4,4,u,5>: Cost 2 vzipl RHS, RHS + 1618169385U, // <4,4,u,6>: Cost 2 vext3 <1,2,3,4>, RHS + 2594960735U, // <4,4,u,7>: Cost 3 vext1 <7,4,4,u>, <7,4,4,u> + 161926454U, // <4,4,u,u>: Cost 1 vdup0 RHS + 2631516160U, // <4,5,0,0>: Cost 3 vext2 <2,3,4,5>, <0,0,0,0> + 1557774438U, // <4,5,0,1>: Cost 2 vext2 <2,3,4,5>, LHS + 2618908875U, // <4,5,0,2>: Cost 3 vext2 <0,2,4,5>, <0,2,4,5> + 2571078140U, // <4,5,0,3>: Cost 3 vext1 <3,4,5,0>, <3,4,5,0> + 2626871634U, // <4,5,0,4>: Cost 3 vext2 <1,5,4,5>, <0,4,1,5> + 3644821246U, // <4,5,0,5>: Cost 4 vext1 <3,4,5,0>, <5,2,3,4> + 2594968438U, // <4,5,0,6>: Cost 3 vext1 <7,4,5,0>, <6,7,4,5> + 2594968928U, // <4,5,0,7>: Cost 3 vext1 <7,4,5,0>, <7,4,5,0> + 1557775005U, // <4,5,0,u>: Cost 2 vext2 <2,3,4,5>, LHS + 2623554306U, // <4,5,1,0>: Cost 3 vext2 <1,0,4,5>, <1,0,4,5> + 2624217939U, // <4,5,1,1>: Cost 3 vext2 <1,1,4,5>, <1,1,4,5> + 2631517078U, // <4,5,1,2>: Cost 3 vext2 <2,3,4,5>, <1,2,3,0> + 2821341286U, // <4,5,1,3>: Cost 3 vuzpr <0,4,1,5>, LHS + 2239548390U, // <4,5,1,4>: Cost 3 vrev <4,1,5,4> + 2626872471U, // <4,5,1,5>: Cost 3 vext2 <1,5,4,5>, <1,5,4,5> + 3895083131U, // <4,5,1,6>: Cost 4 vuzpr <0,4,1,5>, <0,1,4,6> + 2718748368U, // <4,5,1,7>: Cost 3 vext3 <5,6,7,4>, <5,1,7,3> + 2821341291U, // <4,5,1,u>: Cost 3 vuzpr <0,4,1,5>, LHS + 2571092070U, // <4,5,2,0>: Cost 3 vext1 <3,4,5,2>, LHS + 3296035756U, // <4,5,2,1>: Cost 4 vrev <1,2,5,4> + 2630854269U, // <4,5,2,2>: Cost 3 vext2 <2,2,4,5>, <2,2,4,5> + 1557776078U, // <4,5,2,3>: Cost 2 vext2 <2,3,4,5>, <2,3,4,5> + 2631517974U, // <4,5,2,4>: Cost 3 vext2 <2,3,4,5>, <2,4,3,5> + 3692652384U, // <4,5,2,5>: Cost 4 vext2 <0,2,4,5>, <2,5,2,7> + 2631518138U, // <4,5,2,6>: Cost 3 vext2 <2,3,4,5>, <2,6,3,7> + 4164013366U, // <4,5,2,7>: Cost 4 vtrnr <0,4,u,2>, RHS + 1561094243U, // <4,5,2,u>: Cost 2 vext2 <2,u,4,5>, <2,u,4,5> + 2631518358U, // <4,5,3,0>: Cost 3 vext2 <2,3,4,5>, <3,0,1,2> + 3895084710U, // <4,5,3,1>: Cost 4 vuzpr <0,4,1,5>, <2,3,0,1> + 2631518518U, // <4,5,3,2>: Cost 3 vext2 <2,3,4,5>, <3,2,1,0> + 2631518620U, // <4,5,3,3>: Cost 3 vext2 <2,3,4,5>, <3,3,3,3> + 2631518716U, // <4,5,3,4>: Cost 3 vext2 <2,3,4,5>, <3,4,5,0> + 2631518784U, // <4,5,3,5>: Cost 3 vext2 <2,3,4,5>, <3,5,3,5> + 2658060980U, // <4,5,3,6>: Cost 3 vext2 <6,7,4,5>, <3,6,7,4> + 2640145131U, // <4,5,3,7>: Cost 3 vext2 <3,7,4,5>, <3,7,4,5> + 2631519004U, // <4,5,3,u>: Cost 3 vext2 <2,3,4,5>, <3,u,1,0> + 2571108454U, // <4,5,4,0>: Cost 3 vext1 <3,4,5,4>, LHS + 3297363022U, // <4,5,4,1>: Cost 4 vrev <1,4,5,4> + 2571110094U, // <4,5,4,2>: Cost 3 vext1 <3,4,5,4>, <2,3,4,5> + 2235566592U, // <4,5,4,3>: Cost 3 vrev <3,4,5,4> + 2571111734U, // <4,5,4,4>: Cost 3 vext1 <3,4,5,4>, RHS + 1557777718U, // <4,5,4,5>: Cost 2 vext2 <2,3,4,5>, RHS + 2645454195U, // <4,5,4,6>: Cost 3 vext2 <4,6,4,5>, <4,6,4,5> + 2259457380U, // <4,5,4,7>: Cost 3 vrev <7,4,5,4> + 1557777961U, // <4,5,4,u>: Cost 2 vext2 <2,3,4,5>, RHS + 1503346790U, // <4,5,5,0>: Cost 2 vext1 <4,4,5,5>, LHS + 2913398480U, // <4,5,5,1>: Cost 3 vzipl RHS, <5,1,7,3> + 2631519998U, // <4,5,5,2>: Cost 3 vext2 <2,3,4,5>, <5,2,3,4> + 2577090710U, // <4,5,5,3>: Cost 3 vext1 <4,4,5,5>, <3,0,1,2> + 1503349978U, // <4,5,5,4>: Cost 2 vext1 <4,4,5,5>, <4,4,5,5> + 2631520260U, // <4,5,5,5>: Cost 3 vext2 <2,3,4,5>, <5,5,5,5> + 2913390690U, // <4,5,5,6>: Cost 3 vzipl RHS, <5,6,7,0> + 2821344566U, // <4,5,5,7>: Cost 3 vuzpr <0,4,1,5>, RHS + 1503352622U, // <4,5,5,u>: Cost 2 vext1 <4,4,5,5>, LHS + 1497383014U, // <4,5,6,0>: Cost 2 vext1 <3,4,5,6>, LHS + 2559181904U, // <4,5,6,1>: Cost 3 vext1 <1,4,5,6>, <1,4,5,6> + 2565154601U, // <4,5,6,2>: Cost 3 vext1 <2,4,5,6>, <2,4,5,6> + 1497385474U, // <4,5,6,3>: Cost 2 vext1 <3,4,5,6>, <3,4,5,6> + 1497386294U, // <4,5,6,4>: Cost 2 vext1 <3,4,5,6>, RHS + 3047608324U, // <4,5,6,5>: Cost 3 vtrnl RHS, <5,5,5,5> + 2571129554U, // <4,5,6,6>: Cost 3 vext1 <3,4,5,6>, <6,5,4,3> + 27705344U, // <4,5,6,7>: Cost 0 copy RHS + 27705344U, // <4,5,6,u>: Cost 0 copy RHS + 2565161062U, // <4,5,7,0>: Cost 3 vext1 <2,4,5,7>, LHS + 2565161882U, // <4,5,7,1>: Cost 3 vext1 <2,4,5,7>, <1,2,3,4> + 2565162794U, // <4,5,7,2>: Cost 3 vext1 <2,4,5,7>, <2,4,5,7> + 2661381387U, // <4,5,7,3>: Cost 3 vext2 <7,3,4,5>, <7,3,4,5> + 2565164342U, // <4,5,7,4>: Cost 3 vext1 <2,4,5,7>, RHS + 2718748840U, // <4,5,7,5>: Cost 3 vext3 <5,6,7,4>, <5,7,5,7> + 2718748846U, // <4,5,7,6>: Cost 3 vext3 <5,6,7,4>, <5,7,6,4> + 2719412407U, // <4,5,7,7>: Cost 3 vext3 <5,7,7,4>, <5,7,7,4> + 2565166894U, // <4,5,7,u>: Cost 3 vext1 <2,4,5,7>, LHS + 1497399398U, // <4,5,u,0>: Cost 2 vext1 <3,4,5,u>, LHS + 1557780270U, // <4,5,u,1>: Cost 2 vext2 <2,3,4,5>, LHS + 2631522163U, // <4,5,u,2>: Cost 3 vext2 <2,3,4,5>, + 1497401860U, // <4,5,u,3>: Cost 2 vext1 <3,4,5,u>, <3,4,5,u> + 1497402678U, // <4,5,u,4>: Cost 2 vext1 <3,4,5,u>, RHS + 1557780634U, // <4,5,u,5>: Cost 2 vext2 <2,3,4,5>, RHS + 2631522512U, // <4,5,u,6>: Cost 3 vext2 <2,3,4,5>, + 27705344U, // <4,5,u,7>: Cost 0 copy RHS + 27705344U, // <4,5,u,u>: Cost 0 copy RHS + 2618916864U, // <4,6,0,0>: Cost 3 vext2 <0,2,4,6>, <0,0,0,0> + 1545175142U, // <4,6,0,1>: Cost 2 vext2 <0,2,4,6>, LHS + 1545175244U, // <4,6,0,2>: Cost 2 vext2 <0,2,4,6>, <0,2,4,6> + 3692658940U, // <4,6,0,3>: Cost 4 vext2 <0,2,4,6>, <0,3,1,0> + 2618917202U, // <4,6,0,4>: Cost 3 vext2 <0,2,4,6>, <0,4,1,5> + 3709911470U, // <4,6,0,5>: Cost 4 vext2 <3,1,4,6>, <0,5,2,7> + 2589069968U, // <4,6,0,6>: Cost 3 vext1 <6,4,6,0>, <6,4,6,0> + 4040764726U, // <4,6,0,7>: Cost 4 vzipr <2,3,4,0>, RHS + 1545175709U, // <4,6,0,u>: Cost 2 vext2 <0,2,4,6>, LHS + 3692659444U, // <4,6,1,0>: Cost 4 vext2 <0,2,4,6>, <1,0,3,0> + 2618917684U, // <4,6,1,1>: Cost 3 vext2 <0,2,4,6>, <1,1,1,1> + 2618917782U, // <4,6,1,2>: Cost 3 vext2 <0,2,4,6>, <1,2,3,0> + 2618917848U, // <4,6,1,3>: Cost 3 vext2 <0,2,4,6>, <1,3,1,3> + 3692659773U, // <4,6,1,4>: Cost 4 vext2 <0,2,4,6>, <1,4,3,5> + 2618918032U, // <4,6,1,5>: Cost 3 vext2 <0,2,4,6>, <1,5,3,7> + 3692659937U, // <4,6,1,6>: Cost 4 vext2 <0,2,4,6>, <1,6,3,7> + 4032146742U, // <4,6,1,7>: Cost 4 vzipr <0,u,4,1>, RHS + 2618918253U, // <4,6,1,u>: Cost 3 vext2 <0,2,4,6>, <1,u,1,3> + 2779170470U, // <4,6,2,0>: Cost 3 vuzpl RHS, <2,3,0,1> + 2618918460U, // <4,6,2,1>: Cost 3 vext2 <0,2,4,6>, <2,1,6,3> + 2618918504U, // <4,6,2,2>: Cost 3 vext2 <0,2,4,6>, <2,2,2,2> + 2618918566U, // <4,6,2,3>: Cost 3 vext2 <0,2,4,6>, <2,3,0,1> + 2618918679U, // <4,6,2,4>: Cost 3 vext2 <0,2,4,6>, <2,4,3,6> + 2618918788U, // <4,6,2,5>: Cost 3 vext2 <0,2,4,6>, <2,5,6,7> + 2618918842U, // <4,6,2,6>: Cost 3 vext2 <0,2,4,6>, <2,6,3,7> + 2718749178U, // <4,6,2,7>: Cost 3 vext3 <5,6,7,4>, <6,2,7,3> + 2618918971U, // <4,6,2,u>: Cost 3 vext2 <0,2,4,6>, <2,u,0,1> + 2618919062U, // <4,6,3,0>: Cost 3 vext2 <0,2,4,6>, <3,0,1,2> + 2636171526U, // <4,6,3,1>: Cost 3 vext2 <3,1,4,6>, <3,1,4,6> + 2618919222U, // <4,6,3,2>: Cost 3 vext2 <0,2,4,6>, <3,2,1,0> + 2618919324U, // <4,6,3,3>: Cost 3 vext2 <0,2,4,6>, <3,3,3,3> + 2618919426U, // <4,6,3,4>: Cost 3 vext2 <0,2,4,6>, <3,4,5,6> + 2638826058U, // <4,6,3,5>: Cost 3 vext2 <3,5,4,6>, <3,5,4,6> + 3913303030U, // <4,6,3,6>: Cost 4 vuzpr <3,4,5,6>, <1,3,4,6> + 2722730572U, // <4,6,3,7>: Cost 3 vext3 <6,3,7,4>, <6,3,7,4> + 2618919708U, // <4,6,3,u>: Cost 3 vext2 <0,2,4,6>, <3,u,1,0> + 2565210214U, // <4,6,4,0>: Cost 3 vext1 <2,4,6,4>, LHS + 2718749286U, // <4,6,4,1>: Cost 3 vext3 <5,6,7,4>, <6,4,1,3> + 2229667632U, // <4,6,4,2>: Cost 3 vrev <2,4,6,4> + 2235640329U, // <4,6,4,3>: Cost 3 vrev <3,4,6,4> + 2565213494U, // <4,6,4,4>: Cost 3 vext1 <2,4,6,4>, RHS + 1545178422U, // <4,6,4,5>: Cost 2 vext2 <0,2,4,6>, RHS + 1705430326U, // <4,6,4,6>: Cost 2 vuzpl RHS, RHS + 2259531117U, // <4,6,4,7>: Cost 3 vrev <7,4,6,4> + 1545178665U, // <4,6,4,u>: Cost 2 vext2 <0,2,4,6>, RHS + 2565218406U, // <4,6,5,0>: Cost 3 vext1 <2,4,6,5>, LHS + 2645462736U, // <4,6,5,1>: Cost 3 vext2 <4,6,4,6>, <5,1,7,3> + 2913399290U, // <4,6,5,2>: Cost 3 vzipl RHS, <6,2,7,3> + 3913305394U, // <4,6,5,3>: Cost 4 vuzpr <3,4,5,6>, <4,5,6,3> + 2242276659U, // <4,6,5,4>: Cost 3 vrev <4,5,6,4> + 2779172868U, // <4,6,5,5>: Cost 3 vuzpl RHS, <5,5,5,5> + 2913391416U, // <4,6,5,6>: Cost 3 vzipl RHS, <6,6,6,6> + 2821426486U, // <4,6,5,7>: Cost 3 vuzpr <0,4,2,6>, RHS + 2821426487U, // <4,6,5,u>: Cost 3 vuzpr <0,4,2,6>, RHS + 1503428710U, // <4,6,6,0>: Cost 2 vext1 <4,4,6,6>, LHS + 2577171252U, // <4,6,6,1>: Cost 3 vext1 <4,4,6,6>, <1,1,1,1> + 2645463546U, // <4,6,6,2>: Cost 3 vext2 <4,6,4,6>, <6,2,7,3> + 2577172630U, // <4,6,6,3>: Cost 3 vext1 <4,4,6,6>, <3,0,1,2> + 1503431908U, // <4,6,6,4>: Cost 2 vext1 <4,4,6,6>, <4,4,6,6> + 2577174224U, // <4,6,6,5>: Cost 3 vext1 <4,4,6,6>, <5,1,7,3> + 2618921784U, // <4,6,6,6>: Cost 3 vext2 <0,2,4,6>, <6,6,6,6> + 2954464566U, // <4,6,6,7>: Cost 3 vzipr <0,2,4,6>, RHS + 1503434542U, // <4,6,6,u>: Cost 2 vext1 <4,4,6,6>, LHS + 2645464058U, // <4,6,7,0>: Cost 3 vext2 <4,6,4,6>, <7,0,1,2> + 2779173882U, // <4,6,7,1>: Cost 3 vuzpl RHS, <7,0,1,2> + 3638978355U, // <4,6,7,2>: Cost 4 vext1 <2,4,6,7>, <2,4,6,7> + 2725090156U, // <4,6,7,3>: Cost 3 vext3 <6,7,3,4>, <6,7,3,4> + 2645464422U, // <4,6,7,4>: Cost 3 vext2 <4,6,4,6>, <7,4,5,6> + 2779174246U, // <4,6,7,5>: Cost 3 vuzpl RHS, <7,4,5,6> + 2645464582U, // <4,6,7,6>: Cost 3 vext2 <4,6,4,6>, <7,6,5,4> + 2779174508U, // <4,6,7,7>: Cost 3 vuzpl RHS, <7,7,7,7> + 2779173945U, // <4,6,7,u>: Cost 3 vuzpl RHS, <7,0,u,2> + 1503445094U, // <4,6,u,0>: Cost 2 vext1 <4,4,6,u>, LHS + 1545180974U, // <4,6,u,1>: Cost 2 vext2 <0,2,4,6>, LHS + 1705432878U, // <4,6,u,2>: Cost 2 vuzpl RHS, LHS + 2618922940U, // <4,6,u,3>: Cost 3 vext2 <0,2,4,6>, + 1503448294U, // <4,6,u,4>: Cost 2 vext1 <4,4,6,u>, <4,4,6,u> + 1545181338U, // <4,6,u,5>: Cost 2 vext2 <0,2,4,6>, RHS + 1705433242U, // <4,6,u,6>: Cost 2 vuzpl RHS, RHS + 2954480950U, // <4,6,u,7>: Cost 3 vzipr <0,2,4,u>, RHS + 1545181541U, // <4,6,u,u>: Cost 2 vext2 <0,2,4,6>, LHS + 3706601472U, // <4,7,0,0>: Cost 4 vext2 <2,5,4,7>, <0,0,0,0> + 2632859750U, // <4,7,0,1>: Cost 3 vext2 <2,5,4,7>, LHS + 2726343685U, // <4,7,0,2>: Cost 3 vext3 <7,0,2,4>, <7,0,2,4> + 3701293312U, // <4,7,0,3>: Cost 4 vext2 <1,6,4,7>, <0,3,1,4> + 3706601810U, // <4,7,0,4>: Cost 4 vext2 <2,5,4,7>, <0,4,1,5> + 3318746752U, // <4,7,0,5>: Cost 4 vrev <5,0,7,4> + 3695321617U, // <4,7,0,6>: Cost 4 vext2 <0,6,4,7>, <0,6,4,7> + 3330692146U, // <4,7,0,7>: Cost 4 vrev <7,0,7,4> + 2632860317U, // <4,7,0,u>: Cost 3 vext2 <2,5,4,7>, LHS + 3656917094U, // <4,7,1,0>: Cost 4 vext1 <5,4,7,1>, LHS + 3700630324U, // <4,7,1,1>: Cost 4 vext2 <1,5,4,7>, <1,1,1,1> + 2632860570U, // <4,7,1,2>: Cost 3 vext2 <2,5,4,7>, <1,2,3,4> + 3769635936U, // <4,7,1,3>: Cost 4 vext3 <1,u,3,4>, <7,1,3,5> + 3656920374U, // <4,7,1,4>: Cost 4 vext1 <5,4,7,1>, RHS + 3700630681U, // <4,7,1,5>: Cost 4 vext2 <1,5,4,7>, <1,5,4,7> + 3701294314U, // <4,7,1,6>: Cost 4 vext2 <1,6,4,7>, <1,6,4,7> + 3793818754U, // <4,7,1,7>: Cost 4 vext3 <5,u,7,4>, <7,1,7,3> + 2632860570U, // <4,7,1,u>: Cost 3 vext2 <2,5,4,7>, <1,2,3,4> + 3656925286U, // <4,7,2,0>: Cost 4 vext1 <5,4,7,2>, LHS + 3706603050U, // <4,7,2,1>: Cost 4 vext2 <2,5,4,7>, <2,1,4,3> + 3706603112U, // <4,7,2,2>: Cost 4 vext2 <2,5,4,7>, <2,2,2,2> + 2727744688U, // <4,7,2,3>: Cost 3 vext3 <7,2,3,4>, <7,2,3,4> + 3705939745U, // <4,7,2,4>: Cost 4 vext2 <2,4,4,7>, <2,4,4,7> + 2632861554U, // <4,7,2,5>: Cost 3 vext2 <2,5,4,7>, <2,5,4,7> + 3706603450U, // <4,7,2,6>: Cost 4 vext2 <2,5,4,7>, <2,6,3,7> + 3792491731U, // <4,7,2,7>: Cost 4 vext3 <5,6,7,4>, <7,2,7,3> + 2634852453U, // <4,7,2,u>: Cost 3 vext2 <2,u,4,7>, <2,u,4,7> + 3706603670U, // <4,7,3,0>: Cost 4 vext2 <2,5,4,7>, <3,0,1,2> + 3656934544U, // <4,7,3,1>: Cost 4 vext1 <5,4,7,3>, <1,5,3,7> + 2229077736U, // <4,7,3,2>: Cost 3 vrev <2,3,7,4> + 3706603932U, // <4,7,3,3>: Cost 4 vext2 <2,5,4,7>, <3,3,3,3> + 3701295618U, // <4,7,3,4>: Cost 4 vext2 <1,6,4,7>, <3,4,5,6> + 2246995827U, // <4,7,3,5>: Cost 3 vrev <5,3,7,4> + 2639497884U, // <4,7,3,6>: Cost 3 vext2 <3,6,4,7>, <3,6,4,7> + 3332683045U, // <4,7,3,7>: Cost 4 vrev <7,3,7,4> + 2640825150U, // <4,7,3,u>: Cost 3 vext2 <3,u,4,7>, <3,u,4,7> + 2718750004U, // <4,7,4,0>: Cost 3 vext3 <5,6,7,4>, <7,4,0,1> + 3706604490U, // <4,7,4,1>: Cost 4 vext2 <2,5,4,7>, <4,1,2,3> + 3656943474U, // <4,7,4,2>: Cost 4 vext1 <5,4,7,4>, <2,5,4,7> + 3706604650U, // <4,7,4,3>: Cost 4 vext2 <2,5,4,7>, <4,3,2,1> + 2729145691U, // <4,7,4,4>: Cost 3 vext3 <7,4,4,4>, <7,4,4,4> + 2632863030U, // <4,7,4,5>: Cost 3 vext2 <2,5,4,7>, RHS + 2729293165U, // <4,7,4,6>: Cost 3 vext3 <7,4,6,4>, <7,4,6,4> + 3907340074U, // <4,7,4,7>: Cost 4 vuzpr <2,4,5,7>, <2,4,5,7> + 2632863273U, // <4,7,4,u>: Cost 3 vext2 <2,5,4,7>, RHS + 2913391610U, // <4,7,5,0>: Cost 3 vzipl RHS, <7,0,1,2> + 3298174129U, // <4,7,5,1>: Cost 4 vrev <1,5,7,4> + 2589181646U, // <4,7,5,2>: Cost 3 vext1 <6,4,7,5>, <2,3,4,5> + 2236377699U, // <4,7,5,3>: Cost 3 vrev <3,5,7,4> + 2913391974U, // <4,7,5,4>: Cost 3 vzipl RHS, <7,4,5,6> + 2583211973U, // <4,7,5,5>: Cost 3 vext1 <5,4,7,5>, <5,4,7,5> + 2913392134U, // <4,7,5,6>: Cost 3 vzipl RHS, <7,6,5,4> + 2913392236U, // <4,7,5,7>: Cost 3 vzipl RHS, <7,7,7,7> + 2913392258U, // <4,7,5,u>: Cost 3 vzipl RHS, <7,u,1,2> + 2583216230U, // <4,7,6,0>: Cost 3 vext1 <5,4,7,6>, LHS + 3047609338U, // <4,7,6,1>: Cost 3 vtrnl RHS, <7,0,1,2> + 4121351169U, // <4,7,6,2>: Cost 4 vtrnl RHS, <7,0,2,0> + 2237041332U, // <4,7,6,3>: Cost 3 vrev <3,6,7,4> + 2583219510U, // <4,7,6,4>: Cost 3 vext1 <5,4,7,6>, RHS + 1175244902U, // <4,7,6,5>: Cost 2 vrev <5,6,7,4> + 2589192863U, // <4,7,6,6>: Cost 3 vext1 <6,4,7,6>, <6,4,7,6> + 3047609964U, // <4,7,6,7>: Cost 3 vtrnl RHS, <7,7,7,7> + 1657026081U, // <4,7,6,u>: Cost 2 vext3 <7,6,u,4>, <7,6,u,4> + 3650994278U, // <4,7,7,0>: Cost 4 vext1 <4,4,7,7>, LHS + 3650995098U, // <4,7,7,1>: Cost 4 vext1 <4,4,7,7>, <1,2,3,4> + 3650996010U, // <4,7,7,2>: Cost 4 vext1 <4,4,7,7>, <2,4,5,7> + 3311446789U, // <4,7,7,3>: Cost 4 vrev <3,7,7,4> + 2668696936U, // <4,7,7,4>: Cost 3 vext2 , <7,4,5,u> + 2249650359U, // <4,7,7,5>: Cost 3 vrev <5,7,7,4> + 2255623056U, // <4,7,7,6>: Cost 3 vrev <6,7,7,4> + 2718750316U, // <4,7,7,7>: Cost 3 vext3 <5,6,7,4>, <7,7,7,7> + 2664715938U, // <4,7,7,u>: Cost 3 vext2 <7,u,4,7>, <7,u,4,7> + 2915382266U, // <4,7,u,0>: Cost 3 vzipl RHS, <7,0,1,2> + 2632865582U, // <4,7,u,1>: Cost 3 vext2 <2,5,4,7>, LHS + 2726343685U, // <4,7,u,2>: Cost 3 vext3 <7,0,2,4>, <7,0,2,4> + 2238368598U, // <4,7,u,3>: Cost 3 vrev <3,u,7,4> + 2915382630U, // <4,7,u,4>: Cost 3 vzipl RHS, <7,4,5,6> + 1176572168U, // <4,7,u,5>: Cost 2 vrev <5,u,7,4> + 2915382790U, // <4,7,u,6>: Cost 3 vzipl RHS, <7,6,5,4> + 3047757420U, // <4,7,u,7>: Cost 3 vtrnl RHS, <7,7,7,7> + 1658353347U, // <4,7,u,u>: Cost 2 vext3 <7,u,u,4>, <7,u,u,4> + 2618933248U, // <4,u,0,0>: Cost 3 vext2 <0,2,4,u>, <0,0,0,0> + 1545191526U, // <4,u,0,1>: Cost 2 vext2 <0,2,4,u>, LHS + 1545191630U, // <4,u,0,2>: Cost 2 vext2 <0,2,4,u>, <0,2,4,u> + 2233133271U, // <4,u,0,3>: Cost 3 vrev <3,0,u,4> + 2618933586U, // <4,u,0,4>: Cost 3 vext2 <0,2,4,u>, <0,4,1,5> + 2736518902U, // <4,u,0,5>: Cost 3 vext3 , + 2251051362U, // <4,u,0,6>: Cost 3 vrev <6,0,u,4> + 2257024059U, // <4,u,0,7>: Cost 3 vrev <7,0,u,4> + 1545192093U, // <4,u,0,u>: Cost 2 vext2 <0,2,4,u>, LHS + 2571305062U, // <4,u,1,0>: Cost 3 vext1 <3,4,u,1>, LHS + 2618934068U, // <4,u,1,1>: Cost 3 vext2 <0,2,4,u>, <1,1,1,1> + 1618171694U, // <4,u,1,2>: Cost 2 vext3 <1,2,3,4>, LHS + 2618934232U, // <4,u,1,3>: Cost 3 vext2 <0,2,4,u>, <1,3,1,3> + 2571308342U, // <4,u,1,4>: Cost 3 vext1 <3,4,u,1>, RHS + 2618934416U, // <4,u,1,5>: Cost 3 vext2 <0,2,4,u>, <1,5,3,7> + 3692676321U, // <4,u,1,6>: Cost 4 vext2 <0,2,4,u>, <1,6,3,7> + 2718750555U, // <4,u,1,7>: Cost 3 vext3 <5,6,7,4>, + 1618171748U, // <4,u,1,u>: Cost 2 vext3 <1,2,3,4>, LHS + 2553397350U, // <4,u,2,0>: Cost 3 vext1 <0,4,u,2>, LHS + 1148773319U, // <4,u,2,1>: Cost 2 vrev <1,2,u,4> + 2618934888U, // <4,u,2,2>: Cost 3 vext2 <0,2,4,u>, <2,2,2,2> + 1557800657U, // <4,u,2,3>: Cost 2 vext2 <2,3,4,u>, <2,3,4,u> + 2618935065U, // <4,u,2,4>: Cost 3 vext2 <0,2,4,u>, <2,4,3,u> + 2246405931U, // <4,u,2,5>: Cost 3 vrev <5,2,u,4> + 2618935226U, // <4,u,2,6>: Cost 3 vext2 <0,2,4,u>, <2,6,3,7> + 2718750636U, // <4,u,2,7>: Cost 3 vext3 <5,6,7,4>, + 1561118822U, // <4,u,2,u>: Cost 2 vext2 <2,u,4,u>, <2,u,4,u> + 2618935446U, // <4,u,3,0>: Cost 3 vext2 <0,2,4,u>, <3,0,1,2> + 2223178776U, // <4,u,3,1>: Cost 3 vrev <1,3,u,4> + 2618935606U, // <4,u,3,2>: Cost 3 vext2 <0,2,4,u>, <3,2,1,0> + 2618935708U, // <4,u,3,3>: Cost 3 vext2 <0,2,4,u>, <3,3,3,3> + 2618935810U, // <4,u,3,4>: Cost 3 vext2 <0,2,4,u>, <3,4,5,6> + 2691913711U, // <4,u,3,5>: Cost 3 vext3 <1,2,3,4>, + 2253042261U, // <4,u,3,6>: Cost 3 vrev <6,3,u,4> + 2640169710U, // <4,u,3,7>: Cost 3 vext2 <3,7,4,u>, <3,7,4,u> + 2618936092U, // <4,u,3,u>: Cost 3 vext2 <0,2,4,u>, <3,u,1,0> + 1503559782U, // <4,u,4,0>: Cost 2 vext1 <4,4,u,4>, LHS + 2692282391U, // <4,u,4,1>: Cost 3 vext3 <1,2,u,4>, + 2229815106U, // <4,u,4,2>: Cost 3 vrev <2,4,u,4> + 2235787803U, // <4,u,4,3>: Cost 3 vrev <3,4,u,4> + 161926454U, // <4,u,4,4>: Cost 1 vdup0 RHS + 1545194806U, // <4,u,4,5>: Cost 2 vext2 <0,2,4,u>, RHS + 1705577782U, // <4,u,4,6>: Cost 2 vuzpl RHS, RHS + 2259678591U, // <4,u,4,7>: Cost 3 vrev <7,4,u,4> + 161926454U, // <4,u,4,u>: Cost 1 vdup0 RHS + 1479164006U, // <4,u,5,0>: Cost 2 vext1 <0,4,1,5>, LHS + 1839650606U, // <4,u,5,1>: Cost 2 vzipl RHS, LHS + 2565367502U, // <4,u,5,2>: Cost 3 vext1 <2,4,u,5>, <2,3,4,5> + 3089777309U, // <4,u,5,3>: Cost 3 vtrnr <0,4,1,5>, LHS + 1479167286U, // <4,u,5,4>: Cost 2 vext1 <0,4,1,5>, RHS + 1839650970U, // <4,u,5,5>: Cost 2 vzipl RHS, RHS + 1618172058U, // <4,u,5,6>: Cost 2 vext3 <1,2,3,4>, RHS + 3089780265U, // <4,u,5,7>: Cost 3 vtrnr <0,4,1,5>, RHS + 1618172076U, // <4,u,5,u>: Cost 2 vext3 <1,2,3,4>, RHS + 1479688294U, // <4,u,6,0>: Cost 2 vext1 <0,4,u,6>, LHS + 2553430836U, // <4,u,6,1>: Cost 3 vext1 <0,4,u,6>, <1,1,1,1> + 1973868334U, // <4,u,6,2>: Cost 2 vtrnl RHS, LHS + 1497606685U, // <4,u,6,3>: Cost 2 vext1 <3,4,u,6>, <3,4,u,6> + 1479691574U, // <4,u,6,4>: Cost 2 vext1 <0,4,u,6>, RHS + 1175318639U, // <4,u,6,5>: Cost 2 vrev <5,6,u,4> + 1973868698U, // <4,u,6,6>: Cost 2 vtrnl RHS, RHS + 27705344U, // <4,u,6,7>: Cost 0 copy RHS + 27705344U, // <4,u,6,u>: Cost 0 copy RHS + 2565382246U, // <4,u,7,0>: Cost 3 vext1 <2,4,u,7>, LHS + 2565383066U, // <4,u,7,1>: Cost 3 vext1 <2,4,u,7>, <1,2,3,4> + 2565384005U, // <4,u,7,2>: Cost 3 vext1 <2,4,u,7>, <2,4,u,7> + 2661405966U, // <4,u,7,3>: Cost 3 vext2 <7,3,4,u>, <7,3,4,u> + 2565385526U, // <4,u,7,4>: Cost 3 vext1 <2,4,u,7>, RHS + 2779321702U, // <4,u,7,5>: Cost 3 vuzpl RHS, <7,4,5,6> + 2589274793U, // <4,u,7,6>: Cost 3 vext1 <6,4,u,7>, <6,4,u,7> + 2779321964U, // <4,u,7,7>: Cost 3 vuzpl RHS, <7,7,7,7> + 2565388078U, // <4,u,7,u>: Cost 3 vext1 <2,4,u,7>, LHS + 1479704678U, // <4,u,u,0>: Cost 2 vext1 <0,4,u,u>, LHS + 1545197358U, // <4,u,u,1>: Cost 2 vext2 <0,2,4,u>, LHS + 1618172261U, // <4,u,u,2>: Cost 2 vext3 <1,2,3,4>, LHS + 1497623071U, // <4,u,u,3>: Cost 2 vext1 <3,4,u,u>, <3,4,u,u> + 161926454U, // <4,u,u,4>: Cost 1 vdup0 RHS + 1545197722U, // <4,u,u,5>: Cost 2 vext2 <0,2,4,u>, RHS + 1618172301U, // <4,u,u,6>: Cost 2 vext3 <1,2,3,4>, RHS + 27705344U, // <4,u,u,7>: Cost 0 copy RHS + 27705344U, // <4,u,u,u>: Cost 0 copy RHS + 2687123456U, // <5,0,0,0>: Cost 3 vext3 <0,4,1,5>, <0,0,0,0> + 2687123466U, // <5,0,0,1>: Cost 3 vext3 <0,4,1,5>, <0,0,1,1> + 2687123476U, // <5,0,0,2>: Cost 3 vext3 <0,4,1,5>, <0,0,2,2> + 3710599434U, // <5,0,0,3>: Cost 4 vext2 <3,2,5,0>, <0,3,2,5> + 2642166098U, // <5,0,0,4>: Cost 3 vext2 <4,1,5,0>, <0,4,1,5> + 3711926716U, // <5,0,0,5>: Cost 4 vext2 <3,4,5,0>, <0,5,4,3> + 3695338003U, // <5,0,0,6>: Cost 4 vext2 <0,6,5,0>, <0,6,5,0> + 3669005700U, // <5,0,0,7>: Cost 4 vext1 <7,5,0,0>, <7,5,0,0> + 2687123530U, // <5,0,0,u>: Cost 3 vext3 <0,4,1,5>, <0,0,u,2> + 2559434854U, // <5,0,1,0>: Cost 3 vext1 <1,5,0,1>, LHS + 2559435887U, // <5,0,1,1>: Cost 3 vext1 <1,5,0,1>, <1,5,0,1> + 1613381734U, // <5,0,1,2>: Cost 2 vext3 <0,4,1,5>, LHS + 3698656256U, // <5,0,1,3>: Cost 4 vext2 <1,2,5,0>, <1,3,5,7> + 2559438134U, // <5,0,1,4>: Cost 3 vext1 <1,5,0,1>, RHS + 2583326675U, // <5,0,1,5>: Cost 3 vext1 <5,5,0,1>, <5,5,0,1> + 3715908851U, // <5,0,1,6>: Cost 4 vext2 <4,1,5,0>, <1,6,5,7> + 3657069562U, // <5,0,1,7>: Cost 4 vext1 <5,5,0,1>, <7,0,1,2> + 1613381788U, // <5,0,1,u>: Cost 2 vext3 <0,4,1,5>, LHS + 2686017700U, // <5,0,2,0>: Cost 3 vext3 <0,2,4,5>, <0,2,0,2> + 2685796528U, // <5,0,2,1>: Cost 3 vext3 <0,2,1,5>, <0,2,1,5> + 2698625208U, // <5,0,2,2>: Cost 3 vext3 <2,3,4,5>, <0,2,2,4> + 2685944002U, // <5,0,2,3>: Cost 3 vext3 <0,2,3,5>, <0,2,3,5> + 2686017739U, // <5,0,2,4>: Cost 3 vext3 <0,2,4,5>, <0,2,4,5> + 2686091476U, // <5,0,2,5>: Cost 3 vext3 <0,2,5,5>, <0,2,5,5> + 2725167324U, // <5,0,2,6>: Cost 3 vext3 <6,7,4,5>, <0,2,6,4> + 2595280230U, // <5,0,2,7>: Cost 3 vext1 <7,5,0,2>, <7,4,5,6> + 2686312687U, // <5,0,2,u>: Cost 3 vext3 <0,2,u,5>, <0,2,u,5> + 3760128248U, // <5,0,3,0>: Cost 4 vext3 <0,3,0,5>, <0,3,0,5> + 3759685888U, // <5,0,3,1>: Cost 4 vext3 <0,2,3,5>, <0,3,1,4> + 2686533898U, // <5,0,3,2>: Cost 3 vext3 <0,3,2,5>, <0,3,2,5> + 3760349459U, // <5,0,3,3>: Cost 4 vext3 <0,3,3,5>, <0,3,3,5> + 2638187004U, // <5,0,3,4>: Cost 3 vext2 <3,4,5,0>, <3,4,5,0> + 3711928896U, // <5,0,3,5>: Cost 4 vext2 <3,4,5,0>, <3,5,3,5> + 3713256094U, // <5,0,3,6>: Cost 4 vext2 <3,6,5,0>, <3,6,5,0> + 3914064896U, // <5,0,3,7>: Cost 4 vuzpr <3,5,7,0>, <1,3,5,7> + 2686976320U, // <5,0,3,u>: Cost 3 vext3 <0,3,u,5>, <0,3,u,5> + 2559459430U, // <5,0,4,0>: Cost 3 vext1 <1,5,0,4>, LHS + 1613381970U, // <5,0,4,1>: Cost 2 vext3 <0,4,1,5>, <0,4,1,5> + 2687123804U, // <5,0,4,2>: Cost 3 vext3 <0,4,1,5>, <0,4,2,6> + 2235206100U, // <5,0,4,3>: Cost 3 vrev <3,4,0,5> + 2559462710U, // <5,0,4,4>: Cost 3 vext1 <1,5,0,4>, RHS + 2638187830U, // <5,0,4,5>: Cost 3 vext2 <3,4,5,0>, RHS + 3761234303U, // <5,0,4,6>: Cost 4 vext3 <0,4,6,5>, <0,4,6,5> + 2646150600U, // <5,0,4,7>: Cost 3 vext2 <4,7,5,0>, <4,7,5,0> + 1613381970U, // <5,0,4,u>: Cost 2 vext3 <0,4,1,5>, <0,4,1,5> + 3778707862U, // <5,0,5,0>: Cost 4 vext3 <3,4,0,5>, <0,5,0,1> + 2919268454U, // <5,0,5,1>: Cost 3 vzipl <5,5,5,5>, LHS + 3053486182U, // <5,0,5,2>: Cost 3 vtrnl <5,5,5,5>, LHS + 3778707888U, // <5,0,5,3>: Cost 4 vext3 <3,4,0,5>, <0,5,3,0> + 3778707902U, // <5,0,5,4>: Cost 4 vext3 <3,4,0,5>, <0,5,4,5> + 2650796031U, // <5,0,5,5>: Cost 3 vext2 <5,5,5,0>, <5,5,5,0> + 3719893090U, // <5,0,5,6>: Cost 4 vext2 <4,7,5,0>, <5,6,7,0> + 3914067254U, // <5,0,5,7>: Cost 4 vuzpr <3,5,7,0>, RHS + 2919269021U, // <5,0,5,u>: Cost 3 vzipl <5,5,5,5>, LHS + 4047519744U, // <5,0,6,0>: Cost 4 vzipr <3,4,5,6>, <0,0,0,0> + 2920038502U, // <5,0,6,1>: Cost 3 vzipl <5,6,7,0>, LHS + 3759759871U, // <5,0,6,2>: Cost 4 vext3 <0,2,4,5>, <0,6,2,7> + 3645164070U, // <5,0,6,3>: Cost 4 vext1 <3,5,0,6>, <3,5,0,6> + 3762414095U, // <5,0,6,4>: Cost 4 vext3 <0,6,4,5>, <0,6,4,5> + 3993780690U, // <5,0,6,5>: Cost 4 vzipl <5,6,7,0>, <0,5,6,7> + 3719893816U, // <5,0,6,6>: Cost 4 vext2 <4,7,5,0>, <6,6,6,6> + 2662077302U, // <5,0,6,7>: Cost 3 vext2 <7,4,5,0>, <6,7,4,5> + 2920039069U, // <5,0,6,u>: Cost 3 vzipl <5,6,7,0>, LHS + 2565455974U, // <5,0,7,0>: Cost 3 vext1 <2,5,0,7>, LHS + 2565456790U, // <5,0,7,1>: Cost 3 vext1 <2,5,0,7>, <1,2,3,0> + 2565457742U, // <5,0,7,2>: Cost 3 vext1 <2,5,0,7>, <2,5,0,7> + 3639199894U, // <5,0,7,3>: Cost 4 vext1 <2,5,0,7>, <3,0,1,2> + 2565459254U, // <5,0,7,4>: Cost 3 vext1 <2,5,0,7>, RHS + 2589347938U, // <5,0,7,5>: Cost 3 vext1 <6,5,0,7>, <5,6,7,0> + 2589348530U, // <5,0,7,6>: Cost 3 vext1 <6,5,0,7>, <6,5,0,7> + 4188456422U, // <5,0,7,7>: Cost 4 vtrnr RHS, <2,0,5,7> + 2565461806U, // <5,0,7,u>: Cost 3 vext1 <2,5,0,7>, LHS + 2687124106U, // <5,0,u,0>: Cost 3 vext3 <0,4,1,5>, <0,u,0,2> + 1616036502U, // <5,0,u,1>: Cost 2 vext3 <0,u,1,5>, <0,u,1,5> + 1613382301U, // <5,0,u,2>: Cost 2 vext3 <0,4,1,5>, LHS + 2689925800U, // <5,0,u,3>: Cost 3 vext3 <0,u,3,5>, <0,u,3,5> + 2687124146U, // <5,0,u,4>: Cost 3 vext3 <0,4,1,5>, <0,u,4,6> + 2638190746U, // <5,0,u,5>: Cost 3 vext2 <3,4,5,0>, RHS + 2255778723U, // <5,0,u,6>: Cost 3 vrev <6,u,0,5> + 2595280230U, // <5,0,u,7>: Cost 3 vext1 <7,5,0,2>, <7,4,5,6> + 1613382355U, // <5,0,u,u>: Cost 2 vext3 <0,4,1,5>, LHS + 2646818816U, // <5,1,0,0>: Cost 3 vext2 <4,u,5,1>, <0,0,0,0> + 1573077094U, // <5,1,0,1>: Cost 2 vext2 <4,u,5,1>, LHS + 2646818980U, // <5,1,0,2>: Cost 3 vext2 <4,u,5,1>, <0,2,0,2> + 3760866036U, // <5,1,0,3>: Cost 4 vext3 <0,4,1,5>, <1,0,3,0> + 2646819154U, // <5,1,0,4>: Cost 3 vext2 <4,u,5,1>, <0,4,1,5> + 2641510814U, // <5,1,0,5>: Cost 3 vext2 <4,0,5,1>, <0,5,1,0> + 3720561142U, // <5,1,0,6>: Cost 4 vext2 <4,u,5,1>, <0,6,1,7> + 3798909726U, // <5,1,0,7>: Cost 4 vext3 <6,7,4,5>, <1,0,7,6> + 1573077661U, // <5,1,0,u>: Cost 2 vext2 <4,u,5,1>, LHS + 2553536614U, // <5,1,1,0>: Cost 3 vext1 <0,5,1,1>, LHS + 2687124276U, // <5,1,1,1>: Cost 3 vext3 <0,4,1,5>, <1,1,1,1> + 2646819734U, // <5,1,1,2>: Cost 3 vext2 <4,u,5,1>, <1,2,3,0> + 2687124296U, // <5,1,1,3>: Cost 3 vext3 <0,4,1,5>, <1,1,3,3> + 2691326803U, // <5,1,1,4>: Cost 3 vext3 <1,1,4,5>, <1,1,4,5> + 2691400540U, // <5,1,1,5>: Cost 3 vext3 <1,1,5,5>, <1,1,5,5> + 3765216101U, // <5,1,1,6>: Cost 4 vext3 <1,1,6,5>, <1,1,6,5> + 3701982526U, // <5,1,1,7>: Cost 4 vext2 <1,7,5,1>, <1,7,5,1> + 2687124341U, // <5,1,1,u>: Cost 3 vext3 <0,4,1,5>, <1,1,u,3> + 3289776304U, // <5,1,2,0>: Cost 4 vrev <0,2,1,5> + 3763520391U, // <5,1,2,1>: Cost 4 vext3 <0,u,1,5>, <1,2,1,3> + 2646820456U, // <5,1,2,2>: Cost 3 vext2 <4,u,5,1>, <2,2,2,2> + 2687124374U, // <5,1,2,3>: Cost 3 vext3 <0,4,1,5>, <1,2,3,0> + 2691990436U, // <5,1,2,4>: Cost 3 vext3 <1,2,4,5>, <1,2,4,5> + 2687124395U, // <5,1,2,5>: Cost 3 vext3 <0,4,1,5>, <1,2,5,3> + 2646820794U, // <5,1,2,6>: Cost 3 vext2 <4,u,5,1>, <2,6,3,7> + 3808199610U, // <5,1,2,7>: Cost 4 vext3 , <1,2,7,0> + 2687124419U, // <5,1,2,u>: Cost 3 vext3 <0,4,1,5>, <1,2,u,0> + 2577440870U, // <5,1,3,0>: Cost 3 vext1 <4,5,1,3>, LHS + 2687124440U, // <5,1,3,1>: Cost 3 vext3 <0,4,1,5>, <1,3,1,3> + 2228643507U, // <5,1,3,2>: Cost 3 vrev <2,3,1,5> + 2692580332U, // <5,1,3,3>: Cost 3 vext3 <1,3,3,5>, <1,3,3,5> + 2687124469U, // <5,1,3,4>: Cost 3 vext3 <0,4,1,5>, <1,3,4,5> + 2685207552U, // <5,1,3,5>: Cost 3 vext3 <0,1,2,5>, <1,3,5,7> + 2595361654U, // <5,1,3,6>: Cost 3 vext1 <7,5,1,3>, <6,7,4,5> + 2595362192U, // <5,1,3,7>: Cost 3 vext1 <7,5,1,3>, <7,5,1,3> + 2687124503U, // <5,1,3,u>: Cost 3 vext3 <0,4,1,5>, <1,3,u,3> + 1567771538U, // <5,1,4,0>: Cost 2 vext2 <4,0,5,1>, <4,0,5,1> + 2693096491U, // <5,1,4,1>: Cost 3 vext3 <1,4,1,5>, <1,4,1,5> + 2693170228U, // <5,1,4,2>: Cost 3 vext3 <1,4,2,5>, <1,4,2,5> + 2687124541U, // <5,1,4,3>: Cost 3 vext3 <0,4,1,5>, <1,4,3,5> + 2646822096U, // <5,1,4,4>: Cost 3 vext2 <4,u,5,1>, <4,4,4,4> + 1573080374U, // <5,1,4,5>: Cost 2 vext2 <4,u,5,1>, RHS + 2646822260U, // <5,1,4,6>: Cost 3 vext2 <4,u,5,1>, <4,6,4,6> + 3720564168U, // <5,1,4,7>: Cost 4 vext2 <4,u,5,1>, <4,7,5,0> + 1573080602U, // <5,1,4,u>: Cost 2 vext2 <4,u,5,1>, <4,u,5,1> + 2687124591U, // <5,1,5,0>: Cost 3 vext3 <0,4,1,5>, <1,5,0,1> + 2646822543U, // <5,1,5,1>: Cost 3 vext2 <4,u,5,1>, <5,1,0,1> + 3760866433U, // <5,1,5,2>: Cost 4 vext3 <0,4,1,5>, <1,5,2,1> + 2687124624U, // <5,1,5,3>: Cost 3 vext3 <0,4,1,5>, <1,5,3,7> + 2687124631U, // <5,1,5,4>: Cost 3 vext3 <0,4,1,5>, <1,5,4,5> + 2646822916U, // <5,1,5,5>: Cost 3 vext2 <4,u,5,1>, <5,5,5,5> + 2646823010U, // <5,1,5,6>: Cost 3 vext2 <4,u,5,1>, <5,6,7,0> + 2646823080U, // <5,1,5,7>: Cost 3 vext2 <4,u,5,1>, <5,7,5,7> + 2687124663U, // <5,1,5,u>: Cost 3 vext3 <0,4,1,5>, <1,5,u,1> + 2553577574U, // <5,1,6,0>: Cost 3 vext1 <0,5,1,6>, LHS + 3763520719U, // <5,1,6,1>: Cost 4 vext3 <0,u,1,5>, <1,6,1,7> + 2646823418U, // <5,1,6,2>: Cost 3 vext2 <4,u,5,1>, <6,2,7,3> + 3760866529U, // <5,1,6,3>: Cost 4 vext3 <0,4,1,5>, <1,6,3,7> + 2553580854U, // <5,1,6,4>: Cost 3 vext1 <0,5,1,6>, RHS + 2687124723U, // <5,1,6,5>: Cost 3 vext3 <0,4,1,5>, <1,6,5,7> + 2646823736U, // <5,1,6,6>: Cost 3 vext2 <4,u,5,1>, <6,6,6,6> + 2646823758U, // <5,1,6,7>: Cost 3 vext2 <4,u,5,1>, <6,7,0,1> + 2646823839U, // <5,1,6,u>: Cost 3 vext2 <4,u,5,1>, <6,u,0,1> + 2559557734U, // <5,1,7,0>: Cost 3 vext1 <1,5,1,7>, LHS + 2559558452U, // <5,1,7,1>: Cost 3 vext1 <1,5,1,7>, <1,1,1,1> + 2571503270U, // <5,1,7,2>: Cost 3 vext1 <3,5,1,7>, <2,3,0,1> + 2040971366U, // <5,1,7,3>: Cost 2 vtrnr RHS, LHS + 2559561014U, // <5,1,7,4>: Cost 3 vext1 <1,5,1,7>, RHS + 2595393232U, // <5,1,7,5>: Cost 3 vext1 <7,5,1,7>, <5,1,7,3> + 2646824454U, // <5,1,7,6>: Cost 3 vext2 <4,u,5,1>, <7,6,5,4> + 2646824556U, // <5,1,7,7>: Cost 3 vext2 <4,u,5,1>, <7,7,7,7> + 2040971371U, // <5,1,7,u>: Cost 2 vtrnr RHS, LHS + 1591662326U, // <5,1,u,0>: Cost 2 vext2 , + 1573082926U, // <5,1,u,1>: Cost 2 vext2 <4,u,5,1>, LHS + 2695824760U, // <5,1,u,2>: Cost 3 vext3 <1,u,2,5>, <1,u,2,5> + 2040979558U, // <5,1,u,3>: Cost 2 vtrnr RHS, LHS + 2687124874U, // <5,1,u,4>: Cost 3 vext3 <0,4,1,5>, <1,u,4,5> + 1573083290U, // <5,1,u,5>: Cost 2 vext2 <4,u,5,1>, RHS + 2646825168U, // <5,1,u,6>: Cost 3 vext2 <4,u,5,1>, + 2646825216U, // <5,1,u,7>: Cost 3 vext2 <4,u,5,1>, + 2040979563U, // <5,1,u,u>: Cost 2 vtrnr RHS, LHS + 3702652928U, // <5,2,0,0>: Cost 4 vext2 <1,u,5,2>, <0,0,0,0> + 2628911206U, // <5,2,0,1>: Cost 3 vext2 <1,u,5,2>, LHS + 2641518756U, // <5,2,0,2>: Cost 3 vext2 <4,0,5,2>, <0,2,0,2> + 3759760847U, // <5,2,0,3>: Cost 4 vext3 <0,2,4,5>, <2,0,3,2> + 3760866775U, // <5,2,0,4>: Cost 4 vext3 <0,4,1,5>, <2,0,4,1> + 3766912486U, // <5,2,0,5>: Cost 4 vext3 <1,4,2,5>, <2,0,5,7> + 3775686121U, // <5,2,0,6>: Cost 4 vext3 <2,u,4,5>, <2,0,6,1> + 3330331654U, // <5,2,0,7>: Cost 4 vrev <7,0,2,5> + 2628911773U, // <5,2,0,u>: Cost 3 vext2 <1,u,5,2>, LHS + 2623603464U, // <5,2,1,0>: Cost 3 vext2 <1,0,5,2>, <1,0,5,2> + 3698008921U, // <5,2,1,1>: Cost 4 vext2 <1,1,5,2>, <1,1,5,2> + 3633325603U, // <5,2,1,2>: Cost 4 vext1 <1,5,2,1>, <2,1,3,5> + 2687125027U, // <5,2,1,3>: Cost 3 vext3 <0,4,1,5>, <2,1,3,5> + 3633327414U, // <5,2,1,4>: Cost 4 vext1 <1,5,2,1>, RHS + 3759539760U, // <5,2,1,5>: Cost 4 vext3 <0,2,1,5>, <2,1,5,0> + 3760866876U, // <5,2,1,6>: Cost 4 vext3 <0,4,1,5>, <2,1,6,3> + 3330995287U, // <5,2,1,7>: Cost 4 vrev <7,1,2,5> + 2687125072U, // <5,2,1,u>: Cost 3 vext3 <0,4,1,5>, <2,1,u,5> + 3633332326U, // <5,2,2,0>: Cost 4 vext1 <1,5,2,2>, LHS + 3759760992U, // <5,2,2,1>: Cost 4 vext3 <0,2,4,5>, <2,2,1,3> + 2687125096U, // <5,2,2,2>: Cost 3 vext3 <0,4,1,5>, <2,2,2,2> + 2687125106U, // <5,2,2,3>: Cost 3 vext3 <0,4,1,5>, <2,2,3,3> + 2697963133U, // <5,2,2,4>: Cost 3 vext3 <2,2,4,5>, <2,2,4,5> + 3759466120U, // <5,2,2,5>: Cost 4 vext3 <0,2,0,5>, <2,2,5,7> + 3760866960U, // <5,2,2,6>: Cost 4 vext3 <0,4,1,5>, <2,2,6,6> + 3331658920U, // <5,2,2,7>: Cost 4 vrev <7,2,2,5> + 2687125151U, // <5,2,2,u>: Cost 3 vext3 <0,4,1,5>, <2,2,u,3> + 2687125158U, // <5,2,3,0>: Cost 3 vext3 <0,4,1,5>, <2,3,0,1> + 2698405555U, // <5,2,3,1>: Cost 3 vext3 <2,3,1,5>, <2,3,1,5> + 2577516238U, // <5,2,3,2>: Cost 3 vext1 <4,5,2,3>, <2,3,4,5> + 3759687365U, // <5,2,3,3>: Cost 4 vext3 <0,2,3,5>, <2,3,3,5> + 1624884942U, // <5,2,3,4>: Cost 2 vext3 <2,3,4,5>, <2,3,4,5> + 2698700503U, // <5,2,3,5>: Cost 3 vext3 <2,3,5,5>, <2,3,5,5> + 3772368608U, // <5,2,3,6>: Cost 4 vext3 <2,3,4,5>, <2,3,6,5> + 3702655716U, // <5,2,3,7>: Cost 4 vext2 <1,u,5,2>, <3,7,3,7> + 1625179890U, // <5,2,3,u>: Cost 2 vext3 <2,3,u,5>, <2,3,u,5> + 2641521555U, // <5,2,4,0>: Cost 3 vext2 <4,0,5,2>, <4,0,5,2> + 3297150004U, // <5,2,4,1>: Cost 4 vrev <1,4,2,5> + 2699142925U, // <5,2,4,2>: Cost 3 vext3 <2,4,2,5>, <2,4,2,5> + 2698626838U, // <5,2,4,3>: Cost 3 vext3 <2,3,4,5>, <2,4,3,5> + 2698626848U, // <5,2,4,4>: Cost 3 vext3 <2,3,4,5>, <2,4,4,6> + 2628914486U, // <5,2,4,5>: Cost 3 vext2 <1,u,5,2>, RHS + 2645503353U, // <5,2,4,6>: Cost 3 vext2 <4,6,5,2>, <4,6,5,2> + 3332986186U, // <5,2,4,7>: Cost 4 vrev <7,4,2,5> + 2628914729U, // <5,2,4,u>: Cost 3 vext2 <1,u,5,2>, RHS + 2553643110U, // <5,2,5,0>: Cost 3 vext1 <0,5,2,5>, LHS + 3758950227U, // <5,2,5,1>: Cost 4 vext3 <0,1,2,5>, <2,5,1,3> + 3759761248U, // <5,2,5,2>: Cost 4 vext3 <0,2,4,5>, <2,5,2,7> + 2982396006U, // <5,2,5,3>: Cost 3 vzipr <4,u,5,5>, LHS + 2553646390U, // <5,2,5,4>: Cost 3 vext1 <0,5,2,5>, RHS + 2553647108U, // <5,2,5,5>: Cost 3 vext1 <0,5,2,5>, <5,5,5,5> + 3760867204U, // <5,2,5,6>: Cost 4 vext3 <0,4,1,5>, <2,5,6,7> + 3702657141U, // <5,2,5,7>: Cost 4 vext2 <1,u,5,2>, <5,7,0,1> + 2982396011U, // <5,2,5,u>: Cost 3 vzipr <4,u,5,5>, LHS + 3627393126U, // <5,2,6,0>: Cost 4 vext1 <0,5,2,6>, LHS + 3760867236U, // <5,2,6,1>: Cost 4 vext3 <0,4,1,5>, <2,6,1,3> + 2645504506U, // <5,2,6,2>: Cost 3 vext2 <4,6,5,2>, <6,2,7,3> + 2687125434U, // <5,2,6,3>: Cost 3 vext3 <0,4,1,5>, <2,6,3,7> + 2700617665U, // <5,2,6,4>: Cost 3 vext3 <2,6,4,5>, <2,6,4,5> + 3760867276U, // <5,2,6,5>: Cost 4 vext3 <0,4,1,5>, <2,6,5,7> + 3763521493U, // <5,2,6,6>: Cost 4 vext3 <0,u,1,5>, <2,6,6,7> + 3719246670U, // <5,2,6,7>: Cost 4 vext2 <4,6,5,2>, <6,7,0,1> + 2687125479U, // <5,2,6,u>: Cost 3 vext3 <0,4,1,5>, <2,6,u,7> + 2565603430U, // <5,2,7,0>: Cost 3 vext1 <2,5,2,7>, LHS + 3627402240U, // <5,2,7,1>: Cost 4 vext1 <0,5,2,7>, <1,3,5,7> + 2565605216U, // <5,2,7,2>: Cost 3 vext1 <2,5,2,7>, <2,5,2,7> + 2961178726U, // <5,2,7,3>: Cost 3 vzipr <1,3,5,7>, LHS + 2565606710U, // <5,2,7,4>: Cost 3 vext1 <2,5,2,7>, RHS + 4034920552U, // <5,2,7,5>: Cost 4 vzipr <1,3,5,7>, <0,1,2,5> + 3114713292U, // <5,2,7,6>: Cost 3 vtrnr RHS, <0,2,4,6> + 3702658668U, // <5,2,7,7>: Cost 4 vext2 <1,u,5,2>, <7,7,7,7> + 2961178731U, // <5,2,7,u>: Cost 3 vzipr <1,3,5,7>, LHS + 2687125563U, // <5,2,u,0>: Cost 3 vext3 <0,4,1,5>, <2,u,0,1> + 2628917038U, // <5,2,u,1>: Cost 3 vext2 <1,u,5,2>, LHS + 2565613409U, // <5,2,u,2>: Cost 3 vext1 <2,5,2,u>, <2,5,2,u> + 2687125592U, // <5,2,u,3>: Cost 3 vext3 <0,4,1,5>, <2,u,3,3> + 1628203107U, // <5,2,u,4>: Cost 2 vext3 <2,u,4,5>, <2,u,4,5> + 2628917402U, // <5,2,u,5>: Cost 3 vext2 <1,u,5,2>, RHS + 2702092405U, // <5,2,u,6>: Cost 3 vext3 <2,u,6,5>, <2,u,6,5> + 4188463318U, // <5,2,u,7>: Cost 4 vtrnr RHS, <0,2,5,7> + 1628498055U, // <5,2,u,u>: Cost 2 vext3 <2,u,u,5>, <2,u,u,5> + 3760867467U, // <5,3,0,0>: Cost 4 vext3 <0,4,1,5>, <3,0,0,0> + 2687125654U, // <5,3,0,1>: Cost 3 vext3 <0,4,1,5>, <3,0,1,2> + 3759761565U, // <5,3,0,2>: Cost 4 vext3 <0,2,4,5>, <3,0,2,0> + 3633391766U, // <5,3,0,3>: Cost 4 vext1 <1,5,3,0>, <3,0,1,2> + 2687125680U, // <5,3,0,4>: Cost 3 vext3 <0,4,1,5>, <3,0,4,1> + 3787704506U, // <5,3,0,5>: Cost 4 vext3 <4,u,5,5>, <3,0,5,2> + 3763742921U, // <5,3,0,6>: Cost 5 vext3 <0,u,4,5>, <3,0,6,u> + 4182500352U, // <5,3,0,7>: Cost 4 vtrnr <3,5,7,0>, <1,3,5,7> + 2687125717U, // <5,3,0,u>: Cost 3 vext3 <0,4,1,5>, <3,0,u,2> + 2595487846U, // <5,3,1,0>: Cost 3 vext1 <7,5,3,1>, LHS + 2595488768U, // <5,3,1,1>: Cost 3 vext1 <7,5,3,1>, <1,3,5,7> + 2624938923U, // <5,3,1,2>: Cost 3 vext2 <1,2,5,3>, <1,2,5,3> + 2233436412U, // <5,3,1,3>: Cost 3 vrev <3,1,3,5> + 2595491126U, // <5,3,1,4>: Cost 3 vext1 <7,5,3,1>, RHS + 2636219536U, // <5,3,1,5>: Cost 3 vext2 <3,1,5,3>, <1,5,3,7> + 3698681075U, // <5,3,1,6>: Cost 4 vext2 <1,2,5,3>, <1,6,5,7> + 2257327200U, // <5,3,1,7>: Cost 3 vrev <7,1,3,5> + 2628920721U, // <5,3,1,u>: Cost 3 vext2 <1,u,5,3>, <1,u,5,3> + 3289923778U, // <5,3,2,0>: Cost 4 vrev <0,2,3,5> + 2687125814U, // <5,3,2,1>: Cost 3 vext3 <0,4,1,5>, <3,2,1,0> + 3760867649U, // <5,3,2,2>: Cost 4 vext3 <0,4,1,5>, <3,2,2,2> + 2698627404U, // <5,3,2,3>: Cost 3 vext3 <2,3,4,5>, <3,2,3,4> + 3633409334U, // <5,3,2,4>: Cost 4 vext1 <1,5,3,2>, RHS + 3760277850U, // <5,3,2,5>: Cost 4 vext3 <0,3,2,5>, <3,2,5,0> + 3760867686U, // <5,3,2,6>: Cost 4 vext3 <0,4,1,5>, <3,2,6,3> + 3769788783U, // <5,3,2,7>: Cost 4 vext3 <1,u,5,5>, <3,2,7,3> + 2698627445U, // <5,3,2,u>: Cost 3 vext3 <2,3,4,5>, <3,2,u,0> + 3760867711U, // <5,3,3,0>: Cost 4 vext3 <0,4,1,5>, <3,3,0,1> + 2636220684U, // <5,3,3,1>: Cost 3 vext2 <3,1,5,3>, <3,1,5,3> + 3760867729U, // <5,3,3,2>: Cost 4 vext3 <0,4,1,5>, <3,3,2,1> + 2687125916U, // <5,3,3,3>: Cost 3 vext3 <0,4,1,5>, <3,3,3,3> + 2704599463U, // <5,3,3,4>: Cost 3 vext3 <3,3,4,5>, <3,3,4,5> + 2704673200U, // <5,3,3,5>: Cost 3 vext3 <3,3,5,5>, <3,3,5,5> + 3709962935U, // <5,3,3,6>: Cost 4 vext2 <3,1,5,3>, <3,6,7,7> + 3772369346U, // <5,3,3,7>: Cost 4 vext3 <2,3,4,5>, <3,3,7,5> + 2704894411U, // <5,3,3,u>: Cost 3 vext3 <3,3,u,5>, <3,3,u,5> + 2704968148U, // <5,3,4,0>: Cost 3 vext3 <3,4,0,5>, <3,4,0,5> + 3698682850U, // <5,3,4,1>: Cost 4 vext2 <1,2,5,3>, <4,1,5,0> + 2705115622U, // <5,3,4,2>: Cost 3 vext3 <3,4,2,5>, <3,4,2,5> + 2705189359U, // <5,3,4,3>: Cost 3 vext3 <3,4,3,5>, <3,4,3,5> + 2705263096U, // <5,3,4,4>: Cost 3 vext3 <3,4,4,5>, <3,4,4,5> + 2685946370U, // <5,3,4,5>: Cost 3 vext3 <0,2,3,5>, <3,4,5,6> + 3779152394U, // <5,3,4,6>: Cost 4 vext3 <3,4,6,5>, <3,4,6,5> + 3779226131U, // <5,3,4,7>: Cost 4 vext3 <3,4,7,5>, <3,4,7,5> + 2687126045U, // <5,3,4,u>: Cost 3 vext3 <0,4,1,5>, <3,4,u,6> + 2571632742U, // <5,3,5,0>: Cost 3 vext1 <3,5,3,5>, LHS + 2559689870U, // <5,3,5,1>: Cost 3 vext1 <1,5,3,5>, <1,5,3,5> + 2571634382U, // <5,3,5,2>: Cost 3 vext1 <3,5,3,5>, <2,3,4,5> + 2571635264U, // <5,3,5,3>: Cost 3 vext1 <3,5,3,5>, <3,5,3,5> + 2571636022U, // <5,3,5,4>: Cost 3 vext1 <3,5,3,5>, RHS + 2559692804U, // <5,3,5,5>: Cost 3 vext1 <1,5,3,5>, <5,5,5,5> + 3720581218U, // <5,3,5,6>: Cost 4 vext2 <4,u,5,3>, <5,6,7,0> + 2706147940U, // <5,3,5,7>: Cost 3 vext3 <3,5,7,5>, <3,5,7,5> + 2571638574U, // <5,3,5,u>: Cost 3 vext1 <3,5,3,5>, LHS + 2565668966U, // <5,3,6,0>: Cost 3 vext1 <2,5,3,6>, LHS + 3633439887U, // <5,3,6,1>: Cost 4 vext1 <1,5,3,6>, <1,5,3,6> + 2565670760U, // <5,3,6,2>: Cost 3 vext1 <2,5,3,6>, <2,5,3,6> + 2565671426U, // <5,3,6,3>: Cost 3 vext1 <2,5,3,6>, <3,4,5,6> + 2565672246U, // <5,3,6,4>: Cost 3 vext1 <2,5,3,6>, RHS + 3639414630U, // <5,3,6,5>: Cost 4 vext1 <2,5,3,6>, <5,3,6,0> + 3639415352U, // <5,3,6,6>: Cost 4 vext1 <2,5,3,6>, <6,3,5,2> + 2725169844U, // <5,3,6,7>: Cost 3 vext3 <6,7,4,5>, <3,6,7,4> + 2565674798U, // <5,3,6,u>: Cost 3 vext1 <2,5,3,6>, LHS + 1485963366U, // <5,3,7,0>: Cost 2 vext1 <1,5,3,7>, LHS + 1485964432U, // <5,3,7,1>: Cost 2 vext1 <1,5,3,7>, <1,5,3,7> + 2559706728U, // <5,3,7,2>: Cost 3 vext1 <1,5,3,7>, <2,2,2,2> + 2559707286U, // <5,3,7,3>: Cost 3 vext1 <1,5,3,7>, <3,0,1,2> + 1485966646U, // <5,3,7,4>: Cost 2 vext1 <1,5,3,7>, RHS + 2559709039U, // <5,3,7,5>: Cost 3 vext1 <1,5,3,7>, <5,3,7,0> + 2601513466U, // <5,3,7,6>: Cost 3 vext1 , <6,2,7,3> + 2559710480U, // <5,3,7,7>: Cost 3 vext1 <1,5,3,7>, <7,3,5,1> + 1485969198U, // <5,3,7,u>: Cost 2 vext1 <1,5,3,7>, LHS + 1485971558U, // <5,3,u,0>: Cost 2 vext1 <1,5,3,u>, LHS + 1485972625U, // <5,3,u,1>: Cost 2 vext1 <1,5,3,u>, <1,5,3,u> + 2559714920U, // <5,3,u,2>: Cost 3 vext1 <1,5,3,u>, <2,2,2,2> + 2559715478U, // <5,3,u,3>: Cost 3 vext1 <1,5,3,u>, <3,0,1,2> + 1485974838U, // <5,3,u,4>: Cost 2 vext1 <1,5,3,u>, RHS + 2687126342U, // <5,3,u,5>: Cost 3 vext3 <0,4,1,5>, <3,u,5,6> + 2601521658U, // <5,3,u,6>: Cost 3 vext1 , <6,2,7,3> + 3114722304U, // <5,3,u,7>: Cost 3 vtrnr RHS, <1,3,5,7> + 1485977390U, // <5,3,u,u>: Cost 2 vext1 <1,5,3,u>, LHS + 2663432192U, // <5,4,0,0>: Cost 3 vext2 <7,6,5,4>, <0,0,0,0> + 1589690470U, // <5,4,0,1>: Cost 2 vext2 <7,6,5,4>, LHS + 2663432356U, // <5,4,0,2>: Cost 3 vext2 <7,6,5,4>, <0,2,0,2> + 2232846516U, // <5,4,0,3>: Cost 3 vrev <3,0,4,5> + 2642198866U, // <5,4,0,4>: Cost 3 vext2 <4,1,5,4>, <0,4,1,5> + 2713963410U, // <5,4,0,5>: Cost 3 vext3 <4,u,5,5>, <4,0,5,1> + 2713963420U, // <5,4,0,6>: Cost 3 vext3 <4,u,5,5>, <4,0,6,2> + 2256737304U, // <5,4,0,7>: Cost 3 vrev <7,0,4,5> + 1589691037U, // <5,4,0,u>: Cost 2 vext2 <7,6,5,4>, LHS + 2215592058U, // <5,4,1,0>: Cost 3 vrev <0,1,4,5> + 2221564755U, // <5,4,1,1>: Cost 3 vrev <1,1,4,5> + 2663433110U, // <5,4,1,2>: Cost 3 vext2 <7,6,5,4>, <1,2,3,0> + 2663433176U, // <5,4,1,3>: Cost 3 vext2 <7,6,5,4>, <1,3,1,3> + 3627502902U, // <5,4,1,4>: Cost 4 vext1 <0,5,4,1>, RHS + 2687126498U, // <5,4,1,5>: Cost 3 vext3 <0,4,1,5>, <4,1,5,0> + 2709392368U, // <5,4,1,6>: Cost 3 vext3 <4,1,6,5>, <4,1,6,5> + 3331142761U, // <5,4,1,7>: Cost 4 vrev <7,1,4,5> + 2916748841U, // <5,4,1,u>: Cost 3 vzipl <5,1,7,3>, RHS + 2216255691U, // <5,4,2,0>: Cost 3 vrev <0,2,4,5> + 2222228388U, // <5,4,2,1>: Cost 3 vrev <1,2,4,5> + 2228201085U, // <5,4,2,2>: Cost 3 vrev <2,2,4,5> + 2638218958U, // <5,4,2,3>: Cost 3 vext2 <3,4,5,4>, <2,3,4,5> + 3705988903U, // <5,4,2,4>: Cost 4 vext2 <2,4,5,4>, <2,4,5,4> + 2698628150U, // <5,4,2,5>: Cost 3 vext3 <2,3,4,5>, <4,2,5,3> + 2252091873U, // <5,4,2,6>: Cost 3 vrev <6,2,4,5> + 3331806394U, // <5,4,2,7>: Cost 4 vrev <7,2,4,5> + 2663434299U, // <5,4,2,u>: Cost 3 vext2 <7,6,5,4>, <2,u,0,1> + 2589605990U, // <5,4,3,0>: Cost 3 vext1 <6,5,4,3>, LHS + 2222892021U, // <5,4,3,1>: Cost 3 vrev <1,3,4,5> + 1155122894U, // <5,4,3,2>: Cost 2 vrev <2,3,4,5> + 2234837415U, // <5,4,3,3>: Cost 3 vrev <3,3,4,5> + 2638219776U, // <5,4,3,4>: Cost 3 vext2 <3,4,5,4>, <3,4,5,4> + 3766987908U, // <5,4,3,5>: Cost 4 vext3 <1,4,3,5>, <4,3,5,0> + 2252755506U, // <5,4,3,6>: Cost 3 vrev <6,3,4,5> + 2258728203U, // <5,4,3,7>: Cost 3 vrev <7,3,4,5> + 1190959076U, // <5,4,3,u>: Cost 2 vrev + 2583642214U, // <5,4,4,0>: Cost 3 vext1 <5,5,4,4>, LHS + 2642201574U, // <5,4,4,1>: Cost 3 vext2 <4,1,5,4>, <4,1,5,4> + 3303270175U, // <5,4,4,2>: Cost 4 vrev <2,4,4,5> + 2235501048U, // <5,4,4,3>: Cost 3 vrev <3,4,4,5> + 2713963728U, // <5,4,4,4>: Cost 3 vext3 <4,u,5,5>, <4,4,4,4> + 1589693750U, // <5,4,4,5>: Cost 2 vext2 <7,6,5,4>, RHS + 2713963748U, // <5,4,4,6>: Cost 3 vext3 <4,u,5,5>, <4,4,6,6> + 2646183372U, // <5,4,4,7>: Cost 3 vext2 <4,7,5,4>, <4,7,5,4> + 1589693993U, // <5,4,4,u>: Cost 2 vext2 <7,6,5,4>, RHS + 2559762534U, // <5,4,5,0>: Cost 3 vext1 <1,5,4,5>, LHS + 2224219287U, // <5,4,5,1>: Cost 3 vrev <1,5,4,5> + 2698628366U, // <5,4,5,2>: Cost 3 vext3 <2,3,4,5>, <4,5,2,3> + 3633506454U, // <5,4,5,3>: Cost 4 vext1 <1,5,4,5>, <3,0,1,2> + 2559765814U, // <5,4,5,4>: Cost 3 vext1 <1,5,4,5>, RHS + 2248110075U, // <5,4,5,5>: Cost 3 vrev <5,5,4,5> + 1613385014U, // <5,4,5,6>: Cost 2 vext3 <0,4,1,5>, RHS + 2663436456U, // <5,4,5,7>: Cost 3 vext2 <7,6,5,4>, <5,7,5,7> + 1613385032U, // <5,4,5,u>: Cost 2 vext3 <0,4,1,5>, RHS + 2559770726U, // <5,4,6,0>: Cost 3 vext1 <1,5,4,6>, LHS + 2559771648U, // <5,4,6,1>: Cost 3 vext1 <1,5,4,6>, <1,3,5,7> + 2230855617U, // <5,4,6,2>: Cost 3 vrev <2,6,4,5> + 2571717122U, // <5,4,6,3>: Cost 3 vext1 <3,5,4,6>, <3,4,5,6> + 2559774006U, // <5,4,6,4>: Cost 3 vext1 <1,5,4,6>, RHS + 2712636796U, // <5,4,6,5>: Cost 3 vext3 <4,6,5,5>, <4,6,5,5> + 2254746405U, // <5,4,6,6>: Cost 3 vrev <6,6,4,5> + 2712784270U, // <5,4,6,7>: Cost 3 vext3 <4,6,7,5>, <4,6,7,5> + 2559776558U, // <5,4,6,u>: Cost 3 vext1 <1,5,4,6>, LHS + 2565750886U, // <5,4,7,0>: Cost 3 vext1 <2,5,4,7>, LHS + 2565751706U, // <5,4,7,1>: Cost 3 vext1 <2,5,4,7>, <1,2,3,4> + 2565752690U, // <5,4,7,2>: Cost 3 vext1 <2,5,4,7>, <2,5,4,7> + 2237491947U, // <5,4,7,3>: Cost 3 vrev <3,7,4,5> + 2565754166U, // <5,4,7,4>: Cost 3 vext1 <2,5,4,7>, RHS + 3114713426U, // <5,4,7,5>: Cost 3 vtrnr RHS, <0,4,1,5> + 1181668214U, // <5,4,7,6>: Cost 2 vrev <6,7,4,5> + 2663437921U, // <5,4,7,7>: Cost 3 vext2 <7,6,5,4>, <7,7,6,5> + 1591023272U, // <5,4,7,u>: Cost 2 vext2 <7,u,5,4>, <7,u,5,4> + 2220237489U, // <5,4,u,0>: Cost 3 vrev <0,u,4,5> + 1589696302U, // <5,4,u,1>: Cost 2 vext2 <7,6,5,4>, LHS + 1158441059U, // <5,4,u,2>: Cost 2 vrev <2,u,4,5> + 2238155580U, // <5,4,u,3>: Cost 3 vrev <3,u,4,5> + 2559790390U, // <5,4,u,4>: Cost 3 vext1 <1,5,4,u>, RHS + 1640222238U, // <5,4,u,5>: Cost 2 vext3 <4,u,5,5>, <4,u,5,5> + 1613385257U, // <5,4,u,6>: Cost 2 vext3 <0,4,1,5>, RHS + 2714111536U, // <5,4,u,7>: Cost 3 vext3 <4,u,7,5>, <4,u,7,5> + 1613385275U, // <5,4,u,u>: Cost 2 vext3 <0,4,1,5>, RHS + 2646851584U, // <5,5,0,0>: Cost 3 vext2 <4,u,5,5>, <0,0,0,0> + 1573109862U, // <5,5,0,1>: Cost 2 vext2 <4,u,5,5>, LHS + 2646851748U, // <5,5,0,2>: Cost 3 vext2 <4,u,5,5>, <0,2,0,2> + 3760279130U, // <5,5,0,3>: Cost 4 vext3 <0,3,2,5>, <5,0,3,2> + 2687127138U, // <5,5,0,4>: Cost 3 vext3 <0,4,1,5>, <5,0,4,1> + 2583687167U, // <5,5,0,5>: Cost 3 vext1 <5,5,5,0>, <5,5,5,0> + 3720593910U, // <5,5,0,6>: Cost 4 vext2 <4,u,5,5>, <0,6,1,7> + 4182502710U, // <5,5,0,7>: Cost 4 vtrnr <3,5,7,0>, RHS + 1573110429U, // <5,5,0,u>: Cost 2 vext2 <4,u,5,5>, LHS + 2577719398U, // <5,5,1,0>: Cost 3 vext1 <4,5,5,1>, LHS + 2624291676U, // <5,5,1,1>: Cost 3 vext2 <1,1,5,5>, <1,1,5,5> + 2646852502U, // <5,5,1,2>: Cost 3 vext2 <4,u,5,5>, <1,2,3,0> + 2646852568U, // <5,5,1,3>: Cost 3 vext2 <4,u,5,5>, <1,3,1,3> + 2687127218U, // <5,5,1,4>: Cost 3 vext3 <0,4,1,5>, <5,1,4,0> + 2628936848U, // <5,5,1,5>: Cost 3 vext2 <1,u,5,5>, <1,5,3,7> + 3698033907U, // <5,5,1,6>: Cost 4 vext2 <1,1,5,5>, <1,6,5,7> + 2713964240U, // <5,5,1,7>: Cost 3 vext3 <4,u,5,5>, <5,1,7,3> + 2689781462U, // <5,5,1,u>: Cost 3 vext3 <0,u,1,5>, <5,1,u,0> + 3645497446U, // <5,5,2,0>: Cost 4 vext1 <3,5,5,2>, LHS + 3758952168U, // <5,5,2,1>: Cost 4 vext3 <0,1,2,5>, <5,2,1,0> + 2646853224U, // <5,5,2,2>: Cost 3 vext2 <4,u,5,5>, <2,2,2,2> + 2698628862U, // <5,5,2,3>: Cost 3 vext3 <2,3,4,5>, <5,2,3,4> + 3760942851U, // <5,5,2,4>: Cost 4 vext3 <0,4,2,5>, <5,2,4,0> + 2713964303U, // <5,5,2,5>: Cost 3 vext3 <4,u,5,5>, <5,2,5,3> + 2646853562U, // <5,5,2,6>: Cost 3 vext2 <4,u,5,5>, <2,6,3,7> + 4038198272U, // <5,5,2,7>: Cost 4 vzipr <1,u,5,2>, <1,3,5,7> + 2701946667U, // <5,5,2,u>: Cost 3 vext3 <2,u,4,5>, <5,2,u,4> + 2646853782U, // <5,5,3,0>: Cost 3 vext2 <4,u,5,5>, <3,0,1,2> + 3698034922U, // <5,5,3,1>: Cost 4 vext2 <1,1,5,5>, <3,1,1,5> + 2646853942U, // <5,5,3,2>: Cost 3 vext2 <4,u,5,5>, <3,2,1,0> + 2637564336U, // <5,5,3,3>: Cost 3 vext2 <3,3,5,5>, <3,3,5,5> + 2646854146U, // <5,5,3,4>: Cost 3 vext2 <4,u,5,5>, <3,4,5,6> + 2638891602U, // <5,5,3,5>: Cost 3 vext2 <3,5,5,5>, <3,5,5,5> + 3702680247U, // <5,5,3,6>: Cost 4 vext2 <1,u,5,5>, <3,6,7,7> + 3702680259U, // <5,5,3,7>: Cost 4 vext2 <1,u,5,5>, <3,7,0,1> + 2646854428U, // <5,5,3,u>: Cost 3 vext2 <4,u,5,5>, <3,u,1,0> + 2646854546U, // <5,5,4,0>: Cost 3 vext2 <4,u,5,5>, <4,0,5,1> + 3760869263U, // <5,5,4,1>: Cost 4 vext3 <0,4,1,5>, <5,4,1,5> + 3759763347U, // <5,5,4,2>: Cost 4 vext3 <0,2,4,5>, <5,4,2,0> + 2698629022U, // <5,5,4,3>: Cost 3 vext3 <2,3,4,5>, <5,4,3,2> + 1570458842U, // <5,5,4,4>: Cost 2 vext2 <4,4,5,5>, <4,4,5,5> + 1573113142U, // <5,5,4,5>: Cost 2 vext2 <4,u,5,5>, RHS + 2645527932U, // <5,5,4,6>: Cost 3 vext2 <4,6,5,5>, <4,6,5,5> + 2717429701U, // <5,5,4,7>: Cost 3 vext3 <5,4,7,5>, <5,4,7,5> + 1573113374U, // <5,5,4,u>: Cost 2 vext2 <4,u,5,5>, <4,u,5,5> + 1509982310U, // <5,5,5,0>: Cost 2 vext1 <5,5,5,5>, LHS + 2646855376U, // <5,5,5,1>: Cost 3 vext2 <4,u,5,5>, <5,1,7,3> + 2583725672U, // <5,5,5,2>: Cost 3 vext1 <5,5,5,5>, <2,2,2,2> + 2583726230U, // <5,5,5,3>: Cost 3 vext1 <5,5,5,5>, <3,0,1,2> + 1509985590U, // <5,5,5,4>: Cost 2 vext1 <5,5,5,5>, RHS + 229035318U, // <5,5,5,5>: Cost 1 vdup1 RHS + 2646855778U, // <5,5,5,6>: Cost 3 vext2 <4,u,5,5>, <5,6,7,0> + 2646855848U, // <5,5,5,7>: Cost 3 vext2 <4,u,5,5>, <5,7,5,7> + 229035318U, // <5,5,5,u>: Cost 1 vdup1 RHS + 2577760358U, // <5,5,6,0>: Cost 3 vext1 <4,5,5,6>, LHS + 3633587361U, // <5,5,6,1>: Cost 4 vext1 <1,5,5,6>, <1,5,5,6> + 2646856186U, // <5,5,6,2>: Cost 3 vext2 <4,u,5,5>, <6,2,7,3> + 3633588738U, // <5,5,6,3>: Cost 4 vext1 <1,5,5,6>, <3,4,5,6> + 2718535756U, // <5,5,6,4>: Cost 3 vext3 <5,6,4,5>, <5,6,4,5> + 2644202223U, // <5,5,6,5>: Cost 3 vext2 <4,4,5,5>, <6,5,7,5> + 2973780482U, // <5,5,6,6>: Cost 3 vzipr <3,4,5,6>, <3,4,5,6> + 2646856526U, // <5,5,6,7>: Cost 3 vext2 <4,u,5,5>, <6,7,0,1> + 2646856607U, // <5,5,6,u>: Cost 3 vext2 <4,u,5,5>, <6,u,0,1> + 2571796582U, // <5,5,7,0>: Cost 3 vext1 <3,5,5,7>, LHS + 3633595392U, // <5,5,7,1>: Cost 4 vext1 <1,5,5,7>, <1,3,5,7> + 2571798222U, // <5,5,7,2>: Cost 3 vext1 <3,5,5,7>, <2,3,4,5> + 2571799124U, // <5,5,7,3>: Cost 3 vext1 <3,5,5,7>, <3,5,5,7> + 2571799862U, // <5,5,7,4>: Cost 3 vext1 <3,5,5,7>, RHS + 3114717188U, // <5,5,7,5>: Cost 3 vtrnr RHS, <5,5,5,5> + 2646857222U, // <5,5,7,6>: Cost 3 vext2 <4,u,5,5>, <7,6,5,4> + 2040974646U, // <5,5,7,7>: Cost 2 vtrnr RHS, RHS + 2040974647U, // <5,5,7,u>: Cost 2 vtrnr RHS, RHS + 1509982310U, // <5,5,u,0>: Cost 2 vext1 <5,5,5,5>, LHS + 1573115694U, // <5,5,u,1>: Cost 2 vext2 <4,u,5,5>, LHS + 2571806414U, // <5,5,u,2>: Cost 3 vext1 <3,5,5,u>, <2,3,4,5> + 2698924258U, // <5,5,u,3>: Cost 3 vext3 <2,3,u,5>, <5,u,3,2> + 1509985590U, // <5,5,u,4>: Cost 2 vext1 <5,5,5,5>, RHS + 229035318U, // <5,5,u,5>: Cost 1 vdup1 RHS + 2646857936U, // <5,5,u,6>: Cost 3 vext2 <4,u,5,5>, + 2040982838U, // <5,5,u,7>: Cost 2 vtrnr RHS, RHS + 229035318U, // <5,5,u,u>: Cost 1 vdup1 RHS + 2638233600U, // <5,6,0,0>: Cost 3 vext2 <3,4,5,6>, <0,0,0,0> + 1564491878U, // <5,6,0,1>: Cost 2 vext2 <3,4,5,6>, LHS + 2632261796U, // <5,6,0,2>: Cost 3 vext2 <2,4,5,6>, <0,2,0,2> + 2638233856U, // <5,6,0,3>: Cost 3 vext2 <3,4,5,6>, <0,3,1,4> + 2638233938U, // <5,6,0,4>: Cost 3 vext2 <3,4,5,6>, <0,4,1,5> + 3706003885U, // <5,6,0,5>: Cost 4 vext2 <2,4,5,6>, <0,5,2,6> + 3706003967U, // <5,6,0,6>: Cost 4 vext2 <2,4,5,6>, <0,6,2,7> + 2662122052U, // <5,6,0,7>: Cost 3 vext2 <7,4,5,6>, <0,7,1,4> + 1564492445U, // <5,6,0,u>: Cost 2 vext2 <3,4,5,6>, LHS + 3700032228U, // <5,6,1,0>: Cost 4 vext2 <1,4,5,6>, <1,0,1,2> + 2638234420U, // <5,6,1,1>: Cost 3 vext2 <3,4,5,6>, <1,1,1,1> + 2638234518U, // <5,6,1,2>: Cost 3 vext2 <3,4,5,6>, <1,2,3,0> + 2638234584U, // <5,6,1,3>: Cost 3 vext2 <3,4,5,6>, <1,3,1,3> + 2626290768U, // <5,6,1,4>: Cost 3 vext2 <1,4,5,6>, <1,4,5,6> + 2638234768U, // <5,6,1,5>: Cost 3 vext2 <3,4,5,6>, <1,5,3,7> + 3700032719U, // <5,6,1,6>: Cost 4 vext2 <1,4,5,6>, <1,6,1,7> + 2982366518U, // <5,6,1,7>: Cost 3 vzipr <4,u,5,1>, RHS + 2628945300U, // <5,6,1,u>: Cost 3 vext2 <1,u,5,6>, <1,u,5,6> + 3706004925U, // <5,6,2,0>: Cost 4 vext2 <2,4,5,6>, <2,0,1,2> + 3711976963U, // <5,6,2,1>: Cost 4 vext2 <3,4,5,6>, <2,1,0,0> + 2638235240U, // <5,6,2,2>: Cost 3 vext2 <3,4,5,6>, <2,2,2,2> + 2638235302U, // <5,6,2,3>: Cost 3 vext2 <3,4,5,6>, <2,3,0,1> + 2632263465U, // <5,6,2,4>: Cost 3 vext2 <2,4,5,6>, <2,4,5,6> + 2638235496U, // <5,6,2,5>: Cost 3 vext2 <3,4,5,6>, <2,5,3,6> + 2638235578U, // <5,6,2,6>: Cost 3 vext2 <3,4,5,6>, <2,6,3,7> + 2713965050U, // <5,6,2,7>: Cost 3 vext3 <4,u,5,5>, <6,2,7,3> + 2634917997U, // <5,6,2,u>: Cost 3 vext2 <2,u,5,6>, <2,u,5,6> + 2638235798U, // <5,6,3,0>: Cost 3 vext2 <3,4,5,6>, <3,0,1,2> + 3711977702U, // <5,6,3,1>: Cost 4 vext2 <3,4,5,6>, <3,1,1,1> + 2638235958U, // <5,6,3,2>: Cost 3 vext2 <3,4,5,6>, <3,2,1,0> + 2638236060U, // <5,6,3,3>: Cost 3 vext2 <3,4,5,6>, <3,3,3,3> + 1564494338U, // <5,6,3,4>: Cost 2 vext2 <3,4,5,6>, <3,4,5,6> + 2638236234U, // <5,6,3,5>: Cost 3 vext2 <3,4,5,6>, <3,5,4,6> + 3711978104U, // <5,6,3,6>: Cost 4 vext2 <3,4,5,6>, <3,6,0,7> + 4034227510U, // <5,6,3,7>: Cost 4 vzipr <1,2,5,3>, RHS + 1567148870U, // <5,6,3,u>: Cost 2 vext2 <3,u,5,6>, <3,u,5,6> + 2577817702U, // <5,6,4,0>: Cost 3 vext1 <4,5,6,4>, LHS + 3711978442U, // <5,6,4,1>: Cost 4 vext2 <3,4,5,6>, <4,1,2,3> + 2723033713U, // <5,6,4,2>: Cost 3 vext3 <6,4,2,5>, <6,4,2,5> + 2577820162U, // <5,6,4,3>: Cost 3 vext1 <4,5,6,4>, <3,4,5,6> + 2644208859U, // <5,6,4,4>: Cost 3 vext2 <4,4,5,6>, <4,4,5,6> + 1564495158U, // <5,6,4,5>: Cost 2 vext2 <3,4,5,6>, RHS + 2645536125U, // <5,6,4,6>: Cost 3 vext2 <4,6,5,6>, <4,6,5,6> + 2646199758U, // <5,6,4,7>: Cost 3 vext2 <4,7,5,6>, <4,7,5,6> + 1564495401U, // <5,6,4,u>: Cost 2 vext2 <3,4,5,6>, RHS + 2577825894U, // <5,6,5,0>: Cost 3 vext1 <4,5,6,5>, LHS + 2662125264U, // <5,6,5,1>: Cost 3 vext2 <7,4,5,6>, <5,1,7,3> + 3775836867U, // <5,6,5,2>: Cost 4 vext3 <2,u,6,5>, <6,5,2,6> + 3711979330U, // <5,6,5,3>: Cost 4 vext2 <3,4,5,6>, <5,3,2,0> + 2650181556U, // <5,6,5,4>: Cost 3 vext2 <5,4,5,6>, <5,4,5,6> + 2662125572U, // <5,6,5,5>: Cost 3 vext2 <7,4,5,6>, <5,5,5,5> + 2638237732U, // <5,6,5,6>: Cost 3 vext2 <3,4,5,6>, <5,6,0,1> + 2982399286U, // <5,6,5,7>: Cost 3 vzipr <4,u,5,5>, RHS + 2982399287U, // <5,6,5,u>: Cost 3 vzipr <4,u,5,5>, RHS + 2583806054U, // <5,6,6,0>: Cost 3 vext1 <5,5,6,6>, LHS + 3711979910U, // <5,6,6,1>: Cost 4 vext2 <3,4,5,6>, <6,1,3,4> + 2662126074U, // <5,6,6,2>: Cost 3 vext2 <7,4,5,6>, <6,2,7,3> + 2583808514U, // <5,6,6,3>: Cost 3 vext1 <5,5,6,6>, <3,4,5,6> + 2583809334U, // <5,6,6,4>: Cost 3 vext1 <5,5,6,6>, RHS + 2638238418U, // <5,6,6,5>: Cost 3 vext2 <3,4,5,6>, <6,5,4,3> + 2638238520U, // <5,6,6,6>: Cost 3 vext2 <3,4,5,6>, <6,6,6,6> + 2973781302U, // <5,6,6,7>: Cost 3 vzipr <3,4,5,6>, RHS + 2973781303U, // <5,6,6,u>: Cost 3 vzipr <3,4,5,6>, RHS + 430358630U, // <5,6,7,0>: Cost 1 vext1 RHS, LHS + 1504101172U, // <5,6,7,1>: Cost 2 vext1 RHS, <1,1,1,1> + 1504101992U, // <5,6,7,2>: Cost 2 vext1 RHS, <2,2,2,2> + 1504102550U, // <5,6,7,3>: Cost 2 vext1 RHS, <3,0,1,2> + 430361910U, // <5,6,7,4>: Cost 1 vext1 RHS, RHS + 1504104452U, // <5,6,7,5>: Cost 2 vext1 RHS, <5,5,5,5> + 1504105272U, // <5,6,7,6>: Cost 2 vext1 RHS, <6,6,6,6> + 1504105990U, // <5,6,7,7>: Cost 2 vext1 RHS, <7,6,5,4> + 430364462U, // <5,6,7,u>: Cost 1 vext1 RHS, LHS + 430366822U, // <5,6,u,0>: Cost 1 vext1 RHS, LHS + 1564497710U, // <5,6,u,1>: Cost 2 vext2 <3,4,5,6>, LHS + 1504110184U, // <5,6,u,2>: Cost 2 vext1 RHS, <2,2,2,2> + 1504110742U, // <5,6,u,3>: Cost 2 vext1 RHS, <3,0,1,2> + 430370103U, // <5,6,u,4>: Cost 1 vext1 RHS, RHS + 1564498074U, // <5,6,u,5>: Cost 2 vext2 <3,4,5,6>, RHS + 1504113146U, // <5,6,u,6>: Cost 2 vext1 RHS, <6,2,7,3> + 1504113658U, // <5,6,u,7>: Cost 2 vext1 RHS, <7,0,1,2> + 430372654U, // <5,6,u,u>: Cost 1 vext1 RHS, LHS + 2625634304U, // <5,7,0,0>: Cost 3 vext2 <1,3,5,7>, <0,0,0,0> + 1551892582U, // <5,7,0,1>: Cost 2 vext2 <1,3,5,7>, LHS + 2625634468U, // <5,7,0,2>: Cost 3 vext2 <1,3,5,7>, <0,2,0,2> + 2571889247U, // <5,7,0,3>: Cost 3 vext1 <3,5,7,0>, <3,5,7,0> + 2625634642U, // <5,7,0,4>: Cost 3 vext2 <1,3,5,7>, <0,4,1,5> + 2595778728U, // <5,7,0,5>: Cost 3 vext1 <7,5,7,0>, <5,7,5,7> + 3699376639U, // <5,7,0,6>: Cost 4 vext2 <1,3,5,7>, <0,6,2,7> + 2595780035U, // <5,7,0,7>: Cost 3 vext1 <7,5,7,0>, <7,5,7,0> + 1551893149U, // <5,7,0,u>: Cost 2 vext2 <1,3,5,7>, LHS + 2571894886U, // <5,7,1,0>: Cost 3 vext1 <3,5,7,1>, LHS + 2624308020U, // <5,7,1,1>: Cost 3 vext2 <1,1,5,7>, <1,1,1,1> + 2625635222U, // <5,7,1,2>: Cost 3 vext2 <1,3,5,7>, <1,2,3,0> + 1551893504U, // <5,7,1,3>: Cost 2 vext2 <1,3,5,7>, <1,3,5,7> + 2571898166U, // <5,7,1,4>: Cost 3 vext1 <3,5,7,1>, RHS + 2625635472U, // <5,7,1,5>: Cost 3 vext2 <1,3,5,7>, <1,5,3,7> + 2627626227U, // <5,7,1,6>: Cost 3 vext2 <1,6,5,7>, <1,6,5,7> + 3702031684U, // <5,7,1,7>: Cost 4 vext2 <1,7,5,7>, <1,7,5,7> + 1555211669U, // <5,7,1,u>: Cost 2 vext2 <1,u,5,7>, <1,u,5,7> + 2629617126U, // <5,7,2,0>: Cost 3 vext2 <2,0,5,7>, <2,0,5,7> + 3699377694U, // <5,7,2,1>: Cost 4 vext2 <1,3,5,7>, <2,1,3,0> + 2625635944U, // <5,7,2,2>: Cost 3 vext2 <1,3,5,7>, <2,2,2,2> + 2625636006U, // <5,7,2,3>: Cost 3 vext2 <1,3,5,7>, <2,3,0,1> + 2632271658U, // <5,7,2,4>: Cost 3 vext2 <2,4,5,7>, <2,4,5,7> + 2625636201U, // <5,7,2,5>: Cost 3 vext2 <1,3,5,7>, <2,5,3,7> + 2625636282U, // <5,7,2,6>: Cost 3 vext2 <1,3,5,7>, <2,6,3,7> + 3708004381U, // <5,7,2,7>: Cost 4 vext2 <2,7,5,7>, <2,7,5,7> + 2625636411U, // <5,7,2,u>: Cost 3 vext2 <1,3,5,7>, <2,u,0,1> + 2625636502U, // <5,7,3,0>: Cost 3 vext2 <1,3,5,7>, <3,0,1,2> + 2625636604U, // <5,7,3,1>: Cost 3 vext2 <1,3,5,7>, <3,1,3,5> + 2625636662U, // <5,7,3,2>: Cost 3 vext2 <1,3,5,7>, <3,2,1,0> + 2625636764U, // <5,7,3,3>: Cost 3 vext2 <1,3,5,7>, <3,3,3,3> + 2625636866U, // <5,7,3,4>: Cost 3 vext2 <1,3,5,7>, <3,4,5,6> + 2625636959U, // <5,7,3,5>: Cost 3 vext2 <1,3,5,7>, <3,5,7,0> + 3699378808U, // <5,7,3,6>: Cost 4 vext2 <1,3,5,7>, <3,6,0,7> + 2640235254U, // <5,7,3,7>: Cost 3 vext2 <3,7,5,7>, <3,7,5,7> + 2625637148U, // <5,7,3,u>: Cost 3 vext2 <1,3,5,7>, <3,u,1,0> + 2571919462U, // <5,7,4,0>: Cost 3 vext1 <3,5,7,4>, LHS + 2571920384U, // <5,7,4,1>: Cost 3 vext1 <3,5,7,4>, <1,3,5,7> + 3699379260U, // <5,7,4,2>: Cost 4 vext2 <1,3,5,7>, <4,2,6,0> + 2571922019U, // <5,7,4,3>: Cost 3 vext1 <3,5,7,4>, <3,5,7,4> + 2571922742U, // <5,7,4,4>: Cost 3 vext1 <3,5,7,4>, RHS + 1551895862U, // <5,7,4,5>: Cost 2 vext2 <1,3,5,7>, RHS + 2846277980U, // <5,7,4,6>: Cost 3 vuzpr RHS, <0,4,2,6> + 2646207951U, // <5,7,4,7>: Cost 3 vext2 <4,7,5,7>, <4,7,5,7> + 1551896105U, // <5,7,4,u>: Cost 2 vext2 <1,3,5,7>, RHS + 2583871590U, // <5,7,5,0>: Cost 3 vext1 <5,5,7,5>, LHS + 2652180176U, // <5,7,5,1>: Cost 3 vext2 <5,7,5,7>, <5,1,7,3> + 2625638177U, // <5,7,5,2>: Cost 3 vext2 <1,3,5,7>, <5,2,7,3> + 2625638271U, // <5,7,5,3>: Cost 3 vext2 <1,3,5,7>, <5,3,u,7> + 2583874870U, // <5,7,5,4>: Cost 3 vext1 <5,5,7,5>, RHS + 2846281732U, // <5,7,5,5>: Cost 3 vuzpr RHS, <5,5,5,5> + 2651517015U, // <5,7,5,6>: Cost 3 vext2 <5,6,5,7>, <5,6,5,7> + 1772539190U, // <5,7,5,7>: Cost 2 vuzpr RHS, RHS + 1772539191U, // <5,7,5,u>: Cost 2 vuzpr RHS, RHS + 2846281826U, // <5,7,6,0>: Cost 3 vuzpr RHS, <5,6,7,0> + 3699380615U, // <5,7,6,1>: Cost 4 vext2 <1,3,5,7>, <6,1,3,5> + 2846281108U, // <5,7,6,2>: Cost 3 vuzpr RHS, <4,6,u,2> + 2589854210U, // <5,7,6,3>: Cost 3 vext1 <6,5,7,6>, <3,4,5,6> + 2846281830U, // <5,7,6,4>: Cost 3 vuzpr RHS, <5,6,7,4> + 2713966086U, // <5,7,6,5>: Cost 3 vext3 <4,u,5,5>, <7,6,5,4> + 2846281076U, // <5,7,6,6>: Cost 3 vuzpr RHS, <4,6,4,6> + 2846279610U, // <5,7,6,7>: Cost 3 vuzpr RHS, <2,6,3,7> + 2846279611U, // <5,7,6,u>: Cost 3 vuzpr RHS, <2,6,3,u> + 1510146150U, // <5,7,7,0>: Cost 2 vext1 <5,5,7,7>, LHS + 2846282574U, // <5,7,7,1>: Cost 3 vuzpr RHS, <6,7,0,1> + 2583889512U, // <5,7,7,2>: Cost 3 vext1 <5,5,7,7>, <2,2,2,2> + 2846281919U, // <5,7,7,3>: Cost 3 vuzpr RHS, <5,7,u,3> + 1510149430U, // <5,7,7,4>: Cost 2 vext1 <5,5,7,7>, RHS + 1510150168U, // <5,7,7,5>: Cost 2 vext1 <5,5,7,7>, <5,5,7,7> + 2583892474U, // <5,7,7,6>: Cost 3 vext1 <5,5,7,7>, <6,2,7,3> + 2625640044U, // <5,7,7,7>: Cost 3 vext2 <1,3,5,7>, <7,7,7,7> + 1510151982U, // <5,7,7,u>: Cost 2 vext1 <5,5,7,7>, LHS + 1510154342U, // <5,7,u,0>: Cost 2 vext1 <5,5,7,u>, LHS + 1551898414U, // <5,7,u,1>: Cost 2 vext2 <1,3,5,7>, LHS + 2625640307U, // <5,7,u,2>: Cost 3 vext2 <1,3,5,7>, + 1772536477U, // <5,7,u,3>: Cost 2 vuzpr RHS, LHS + 1510157622U, // <5,7,u,4>: Cost 2 vext1 <5,5,7,u>, RHS + 1551898778U, // <5,7,u,5>: Cost 2 vext2 <1,3,5,7>, RHS + 2625640656U, // <5,7,u,6>: Cost 3 vext2 <1,3,5,7>, + 1772539433U, // <5,7,u,7>: Cost 2 vuzpr RHS, RHS + 1551898981U, // <5,7,u,u>: Cost 2 vext2 <1,3,5,7>, LHS + 2625642496U, // <5,u,0,0>: Cost 3 vext2 <1,3,5,u>, <0,0,0,0> + 1551900774U, // <5,u,0,1>: Cost 2 vext2 <1,3,5,u>, LHS + 2625642660U, // <5,u,0,2>: Cost 3 vext2 <1,3,5,u>, <0,2,0,2> + 2233141464U, // <5,u,0,3>: Cost 3 vrev <3,0,u,5> + 2687129325U, // <5,u,0,4>: Cost 3 vext3 <0,4,1,5>, + 2595852457U, // <5,u,0,5>: Cost 3 vext1 <7,5,u,0>, <5,7,5,u> + 2737116928U, // <5,u,0,6>: Cost 3 vext3 , + 2257032252U, // <5,u,0,7>: Cost 3 vrev <7,0,u,5> + 1551901341U, // <5,u,0,u>: Cost 2 vext2 <1,3,5,u>, LHS + 2560024678U, // <5,u,1,0>: Cost 3 vext1 <1,5,u,1>, LHS + 2221859703U, // <5,u,1,1>: Cost 3 vrev <1,1,u,5> + 1613387566U, // <5,u,1,2>: Cost 2 vext3 <0,4,1,5>, LHS + 1551901697U, // <5,u,1,3>: Cost 2 vext2 <1,3,5,u>, <1,3,5,u> + 2626307154U, // <5,u,1,4>: Cost 3 vext2 <1,4,5,u>, <1,4,5,u> + 2689783622U, // <5,u,1,5>: Cost 3 vext3 <0,u,1,5>, + 2627634420U, // <5,u,1,6>: Cost 3 vext2 <1,6,5,u>, <1,6,5,u> + 2982366536U, // <5,u,1,7>: Cost 3 vzipr <4,u,5,1>, RHS + 1613387620U, // <5,u,1,u>: Cost 2 vext3 <0,4,1,5>, LHS + 2216550639U, // <5,u,2,0>: Cost 3 vrev <0,2,u,5> + 2687129459U, // <5,u,2,1>: Cost 3 vext3 <0,4,1,5>, + 2625644136U, // <5,u,2,2>: Cost 3 vext2 <1,3,5,u>, <2,2,2,2> + 2687129480U, // <5,u,2,3>: Cost 3 vext3 <0,4,1,5>, + 2632279851U, // <5,u,2,4>: Cost 3 vext2 <2,4,5,u>, <2,4,5,u> + 2625644394U, // <5,u,2,5>: Cost 3 vext2 <1,3,5,u>, <2,5,3,u> + 2625644474U, // <5,u,2,6>: Cost 3 vext2 <1,3,5,u>, <2,6,3,7> + 2713966508U, // <5,u,2,7>: Cost 3 vext3 <4,u,5,5>, + 2625644603U, // <5,u,2,u>: Cost 3 vext2 <1,3,5,u>, <2,u,0,1> + 2687129532U, // <5,u,3,0>: Cost 3 vext3 <0,4,1,5>, + 2223186969U, // <5,u,3,1>: Cost 3 vrev <1,3,u,5> + 1155417842U, // <5,u,3,2>: Cost 2 vrev <2,3,u,5> + 2625644956U, // <5,u,3,3>: Cost 3 vext2 <1,3,5,u>, <3,3,3,3> + 1564510724U, // <5,u,3,4>: Cost 2 vext2 <3,4,5,u>, <3,4,5,u> + 2625645160U, // <5,u,3,5>: Cost 3 vext2 <1,3,5,u>, <3,5,u,0> + 2253050454U, // <5,u,3,6>: Cost 3 vrev <6,3,u,5> + 2640243447U, // <5,u,3,7>: Cost 3 vext2 <3,7,5,u>, <3,7,5,u> + 1567165256U, // <5,u,3,u>: Cost 2 vext2 <3,u,5,u>, <3,u,5,u> + 1567828889U, // <5,u,4,0>: Cost 2 vext2 <4,0,5,u>, <4,0,5,u> + 1661163546U, // <5,u,4,1>: Cost 2 vext3 , + 2734463012U, // <5,u,4,2>: Cost 3 vext3 , + 2698631212U, // <5,u,4,3>: Cost 3 vext3 <2,3,4,5>, + 1570458842U, // <5,u,4,4>: Cost 2 vext2 <4,4,5,5>, <4,4,5,5> + 1551904054U, // <5,u,4,5>: Cost 2 vext2 <1,3,5,u>, RHS + 2846286172U, // <5,u,4,6>: Cost 3 vuzpr RHS, <0,4,2,6> + 2646216144U, // <5,u,4,7>: Cost 3 vext2 <4,7,5,u>, <4,7,5,u> + 1551904297U, // <5,u,4,u>: Cost 2 vext2 <1,3,5,u>, RHS + 1509982310U, // <5,u,5,0>: Cost 2 vext1 <5,5,5,5>, LHS + 2224514235U, // <5,u,5,1>: Cost 3 vrev <1,5,u,5> + 2698926194U, // <5,u,5,2>: Cost 3 vext3 <2,3,u,5>, + 2698631295U, // <5,u,5,3>: Cost 3 vext3 <2,3,4,5>, + 1509985590U, // <5,u,5,4>: Cost 2 vext1 <5,5,5,5>, RHS + 229035318U, // <5,u,5,5>: Cost 1 vdup1 RHS + 1613387930U, // <5,u,5,6>: Cost 2 vext3 <0,4,1,5>, RHS + 1772547382U, // <5,u,5,7>: Cost 2 vuzpr RHS, RHS + 229035318U, // <5,u,5,u>: Cost 1 vdup1 RHS + 2566037606U, // <5,u,6,0>: Cost 3 vext1 <2,5,u,6>, LHS + 2920044334U, // <5,u,6,1>: Cost 3 vzipl <5,6,7,0>, LHS + 2566039445U, // <5,u,6,2>: Cost 3 vext1 <2,5,u,6>, <2,5,u,6> + 2687129808U, // <5,u,6,3>: Cost 3 vext3 <0,4,1,5>, + 2566040886U, // <5,u,6,4>: Cost 3 vext1 <2,5,u,6>, RHS + 2713966815U, // <5,u,6,5>: Cost 3 vext3 <4,u,5,5>, + 2846289268U, // <5,u,6,6>: Cost 3 vuzpr RHS, <4,6,4,6> + 2973781320U, // <5,u,6,7>: Cost 3 vzipr <3,4,5,6>, RHS + 2687129853U, // <5,u,6,u>: Cost 3 vext3 <0,4,1,5>, + 430506086U, // <5,u,7,0>: Cost 1 vext1 RHS, LHS + 1486333117U, // <5,u,7,1>: Cost 2 vext1 <1,5,u,7>, <1,5,u,7> + 1504249448U, // <5,u,7,2>: Cost 2 vext1 RHS, <2,2,2,2> + 2040971933U, // <5,u,7,3>: Cost 2 vtrnr RHS, LHS + 430509384U, // <5,u,7,4>: Cost 1 vext1 RHS, RHS + 1504251600U, // <5,u,7,5>: Cost 2 vext1 RHS, <5,1,7,3> + 1504252410U, // <5,u,7,6>: Cost 2 vext1 RHS, <6,2,7,3> + 2040974889U, // <5,u,7,7>: Cost 2 vtrnr RHS, RHS + 430511918U, // <5,u,7,u>: Cost 1 vext1 RHS, LHS + 430514278U, // <5,u,u,0>: Cost 1 vext1 RHS, LHS + 1551906606U, // <5,u,u,1>: Cost 2 vext2 <1,3,5,u>, LHS + 1613388133U, // <5,u,u,2>: Cost 2 vext3 <0,4,1,5>, LHS + 1772544669U, // <5,u,u,3>: Cost 2 vuzpr RHS, LHS + 430517577U, // <5,u,u,4>: Cost 1 vext1 RHS, RHS + 229035318U, // <5,u,u,5>: Cost 1 vdup1 RHS + 1613388173U, // <5,u,u,6>: Cost 2 vext3 <0,4,1,5>, RHS + 1772547625U, // <5,u,u,7>: Cost 2 vuzpr RHS, RHS + 430520110U, // <5,u,u,u>: Cost 1 vext1 RHS, LHS + 2686025728U, // <6,0,0,0>: Cost 3 vext3 <0,2,4,6>, <0,0,0,0> + 2686025738U, // <6,0,0,1>: Cost 3 vext3 <0,2,4,6>, <0,0,1,1> + 2686025748U, // <6,0,0,2>: Cost 3 vext3 <0,2,4,6>, <0,0,2,2> + 3779084320U, // <6,0,0,3>: Cost 4 vext3 <3,4,5,6>, <0,0,3,5> + 2642903388U, // <6,0,0,4>: Cost 3 vext2 <4,2,6,0>, <0,4,2,6> + 3657723939U, // <6,0,0,5>: Cost 4 vext1 <5,6,0,0>, <5,6,0,0> + 3706028556U, // <6,0,0,6>: Cost 4 vext2 <2,4,6,0>, <0,6,4,2> + 3926675786U, // <6,0,0,7>: Cost 4 vuzpr <5,6,7,0>, <6,0,5,7> + 2686025802U, // <6,0,0,u>: Cost 3 vext3 <0,2,4,6>, <0,0,u,2> + 2566070374U, // <6,0,1,0>: Cost 3 vext1 <2,6,0,1>, LHS + 3759767643U, // <6,0,1,1>: Cost 4 vext3 <0,2,4,6>, <0,1,1,1> + 1612284006U, // <6,0,1,2>: Cost 2 vext3 <0,2,4,6>, LHS + 2583988738U, // <6,0,1,3>: Cost 3 vext1 <5,6,0,1>, <3,4,5,6> + 2566073654U, // <6,0,1,4>: Cost 3 vext1 <2,6,0,1>, RHS + 2583990308U, // <6,0,1,5>: Cost 3 vext1 <5,6,0,1>, <5,6,0,1> + 2589963005U, // <6,0,1,6>: Cost 3 vext1 <6,6,0,1>, <6,6,0,1> + 3651761146U, // <6,0,1,7>: Cost 4 vext1 <4,6,0,1>, <7,0,1,2> + 1612284060U, // <6,0,1,u>: Cost 2 vext3 <0,2,4,6>, LHS + 2686025892U, // <6,0,2,0>: Cost 3 vext3 <0,2,4,6>, <0,2,0,2> + 2685804721U, // <6,0,2,1>: Cost 3 vext3 <0,2,1,6>, <0,2,1,6> + 3759620282U, // <6,0,2,2>: Cost 4 vext3 <0,2,2,6>, <0,2,2,6> + 2705342658U, // <6,0,2,3>: Cost 3 vext3 <3,4,5,6>, <0,2,3,5> + 1612284108U, // <6,0,2,4>: Cost 2 vext3 <0,2,4,6>, <0,2,4,6> + 3706029956U, // <6,0,2,5>: Cost 4 vext2 <2,4,6,0>, <2,5,6,7> + 2686173406U, // <6,0,2,6>: Cost 3 vext3 <0,2,6,6>, <0,2,6,6> + 3651769338U, // <6,0,2,7>: Cost 4 vext1 <4,6,0,2>, <7,0,1,2> + 1612579056U, // <6,0,2,u>: Cost 2 vext3 <0,2,u,6>, <0,2,u,6> + 3706030230U, // <6,0,3,0>: Cost 4 vext2 <2,4,6,0>, <3,0,1,2> + 2705342720U, // <6,0,3,1>: Cost 3 vext3 <3,4,5,6>, <0,3,1,4> + 2705342730U, // <6,0,3,2>: Cost 3 vext3 <3,4,5,6>, <0,3,2,5> + 3706030492U, // <6,0,3,3>: Cost 4 vext2 <2,4,6,0>, <3,3,3,3> + 2644896258U, // <6,0,3,4>: Cost 3 vext2 <4,5,6,0>, <3,4,5,6> + 3718638154U, // <6,0,3,5>: Cost 4 vext2 <4,5,6,0>, <3,5,4,6> + 3729918619U, // <6,0,3,6>: Cost 4 vext2 <6,4,6,0>, <3,6,4,6> + 3926672384U, // <6,0,3,7>: Cost 4 vuzpr <5,6,7,0>, <1,3,5,7> + 2705342783U, // <6,0,3,u>: Cost 3 vext3 <3,4,5,6>, <0,3,u,4> + 2687058250U, // <6,0,4,0>: Cost 3 vext3 <0,4,0,6>, <0,4,0,6> + 2686026066U, // <6,0,4,1>: Cost 3 vext3 <0,2,4,6>, <0,4,1,5> + 1613463900U, // <6,0,4,2>: Cost 2 vext3 <0,4,2,6>, <0,4,2,6> + 2235214293U, // <6,0,4,3>: Cost 3 vrev <3,4,0,6> + 2687353198U, // <6,0,4,4>: Cost 3 vext3 <0,4,4,6>, <0,4,4,6> + 2632289590U, // <6,0,4,5>: Cost 3 vext2 <2,4,6,0>, RHS + 2645560704U, // <6,0,4,6>: Cost 3 vext2 <4,6,6,0>, <4,6,6,0> + 2259105081U, // <6,0,4,7>: Cost 3 vrev <7,4,0,6> + 1613906322U, // <6,0,4,u>: Cost 2 vext3 <0,4,u,6>, <0,4,u,6> + 3721293427U, // <6,0,5,0>: Cost 4 vext2 <5,0,6,0>, <5,0,6,0> + 2687795620U, // <6,0,5,1>: Cost 3 vext3 <0,5,1,6>, <0,5,1,6> + 3761611181U, // <6,0,5,2>: Cost 4 vext3 <0,5,2,6>, <0,5,2,6> + 3723284326U, // <6,0,5,3>: Cost 4 vext2 <5,3,6,0>, <5,3,6,0> + 3791028669U, // <6,0,5,4>: Cost 4 vext3 <5,4,5,6>, <0,5,4,4> + 3718639630U, // <6,0,5,5>: Cost 4 vext2 <4,5,6,0>, <5,5,6,6> + 2652196962U, // <6,0,5,6>: Cost 3 vext2 <5,7,6,0>, <5,6,7,0> + 2852932918U, // <6,0,5,7>: Cost 3 vuzpr <5,6,7,0>, RHS + 2852932919U, // <6,0,5,u>: Cost 3 vuzpr <5,6,7,0>, RHS + 2852933730U, // <6,0,6,0>: Cost 3 vuzpr <5,6,7,0>, <5,6,7,0> + 2925985894U, // <6,0,6,1>: Cost 3 vzipl <6,6,6,6>, LHS + 3060203622U, // <6,0,6,2>: Cost 3 vtrnl <6,6,6,6>, LHS + 3718640178U, // <6,0,6,3>: Cost 4 vext2 <4,5,6,0>, <6,3,4,5> + 2656178832U, // <6,0,6,4>: Cost 3 vext2 <6,4,6,0>, <6,4,6,0> + 3718640338U, // <6,0,6,5>: Cost 4 vext2 <4,5,6,0>, <6,5,4,3> + 2657506098U, // <6,0,6,6>: Cost 3 vext2 <6,6,6,0>, <6,6,6,0> + 2619020110U, // <6,0,6,7>: Cost 3 vext2 <0,2,6,0>, <6,7,0,1> + 2925986461U, // <6,0,6,u>: Cost 3 vzipl <6,6,6,6>, LHS + 2572091494U, // <6,0,7,0>: Cost 3 vext1 <3,6,0,7>, LHS + 2572092310U, // <6,0,7,1>: Cost 3 vext1 <3,6,0,7>, <1,2,3,0> + 2980495524U, // <6,0,7,2>: Cost 3 vzipr RHS, <0,2,0,2> + 2572094072U, // <6,0,7,3>: Cost 3 vext1 <3,6,0,7>, <3,6,0,7> + 2572094774U, // <6,0,7,4>: Cost 3 vext1 <3,6,0,7>, RHS + 4054239700U, // <6,0,7,5>: Cost 4 vzipr RHS, <3,4,0,5> + 3645837653U, // <6,0,7,6>: Cost 4 vext1 <3,6,0,7>, <6,0,7,0> + 3645838376U, // <6,0,7,7>: Cost 4 vext1 <3,6,0,7>, <7,0,6,3> + 2572097326U, // <6,0,7,u>: Cost 3 vext1 <3,6,0,7>, LHS + 2686026378U, // <6,0,u,0>: Cost 3 vext3 <0,2,4,6>, <0,u,0,2> + 2686026386U, // <6,0,u,1>: Cost 3 vext3 <0,2,4,6>, <0,u,1,1> + 1612284573U, // <6,0,u,2>: Cost 2 vext3 <0,2,4,6>, LHS + 2705343144U, // <6,0,u,3>: Cost 3 vext3 <3,4,5,6>, <0,u,3,5> + 1616265906U, // <6,0,u,4>: Cost 2 vext3 <0,u,4,6>, <0,u,4,6> + 2632292506U, // <6,0,u,5>: Cost 3 vext2 <2,4,6,0>, RHS + 2590020356U, // <6,0,u,6>: Cost 3 vext1 <6,6,0,u>, <6,6,0,u> + 2852933161U, // <6,0,u,7>: Cost 3 vuzpr <5,6,7,0>, RHS + 1612284627U, // <6,0,u,u>: Cost 2 vext3 <0,2,4,6>, LHS + 2641584138U, // <6,1,0,0>: Cost 3 vext2 <4,0,6,1>, <0,0,1,1> + 2646229094U, // <6,1,0,1>: Cost 3 vext2 <4,7,6,1>, LHS + 3694092492U, // <6,1,0,2>: Cost 4 vext2 <0,4,6,1>, <0,2,4,6> + 3121365094U, // <6,1,0,3>: Cost 3 vtrnr <5,6,7,0>, LHS + 3694092667U, // <6,1,0,4>: Cost 4 vext2 <0,4,6,1>, <0,4,6,1> + 3767730952U, // <6,1,0,5>: Cost 4 vext3 <1,5,4,6>, <1,0,5,2> + 3696747007U, // <6,1,0,6>: Cost 4 vext2 <0,u,6,1>, <0,6,2,7> + 2256524286U, // <6,1,0,7>: Cost 3 vrev <7,0,1,6> + 2646229661U, // <6,1,0,u>: Cost 3 vext2 <4,7,6,1>, LHS + 3763602219U, // <6,1,1,0>: Cost 4 vext3 <0,u,2,6>, <1,1,0,1> + 2686026548U, // <6,1,1,1>: Cost 3 vext3 <0,2,4,6>, <1,1,1,1> + 3764929346U, // <6,1,1,2>: Cost 4 vext3 <1,1,2,6>, <1,1,2,6> + 2686026568U, // <6,1,1,3>: Cost 3 vext3 <0,2,4,6>, <1,1,3,3> + 2691334996U, // <6,1,1,4>: Cost 3 vext3 <1,1,4,6>, <1,1,4,6> + 3760874332U, // <6,1,1,5>: Cost 4 vext3 <0,4,1,6>, <1,1,5,5> + 3765224294U, // <6,1,1,6>: Cost 4 vext3 <1,1,6,6>, <1,1,6,6> + 3330929743U, // <6,1,1,7>: Cost 4 vrev <7,1,1,6> + 2686026613U, // <6,1,1,u>: Cost 3 vext3 <0,2,4,6>, <1,1,u,3> + 2554208358U, // <6,1,2,0>: Cost 3 vext1 <0,6,1,2>, LHS + 3763602311U, // <6,1,2,1>: Cost 4 vext3 <0,u,2,6>, <1,2,1,3> + 3639895971U, // <6,1,2,2>: Cost 4 vext1 <2,6,1,2>, <2,6,1,2> + 2686026646U, // <6,1,2,3>: Cost 3 vext3 <0,2,4,6>, <1,2,3,0> + 2554211638U, // <6,1,2,4>: Cost 3 vext1 <0,6,1,2>, RHS + 3760874411U, // <6,1,2,5>: Cost 4 vext3 <0,4,1,6>, <1,2,5,3> + 2554212858U, // <6,1,2,6>: Cost 3 vext1 <0,6,1,2>, <6,2,7,3> + 3331593376U, // <6,1,2,7>: Cost 4 vrev <7,2,1,6> + 2686026691U, // <6,1,2,u>: Cost 3 vext3 <0,2,4,6>, <1,2,u,0> + 2566160486U, // <6,1,3,0>: Cost 3 vext1 <2,6,1,3>, LHS + 2686026712U, // <6,1,3,1>: Cost 3 vext3 <0,2,4,6>, <1,3,1,3> + 2686026724U, // <6,1,3,2>: Cost 3 vext3 <0,2,4,6>, <1,3,2,6> + 3759768552U, // <6,1,3,3>: Cost 4 vext3 <0,2,4,6>, <1,3,3,1> + 2692662262U, // <6,1,3,4>: Cost 3 vext3 <1,3,4,6>, <1,3,4,6> + 2686026752U, // <6,1,3,5>: Cost 3 vext3 <0,2,4,6>, <1,3,5,7> + 2590053128U, // <6,1,3,6>: Cost 3 vext1 <6,6,1,3>, <6,6,1,3> + 3663795194U, // <6,1,3,7>: Cost 4 vext1 <6,6,1,3>, <7,0,1,2> + 2686026775U, // <6,1,3,u>: Cost 3 vext3 <0,2,4,6>, <1,3,u,3> + 2641587099U, // <6,1,4,0>: Cost 3 vext2 <4,0,6,1>, <4,0,6,1> + 2693104684U, // <6,1,4,1>: Cost 3 vext3 <1,4,1,6>, <1,4,1,6> + 3639912357U, // <6,1,4,2>: Cost 4 vext1 <2,6,1,4>, <2,6,1,4> + 2687206462U, // <6,1,4,3>: Cost 3 vext3 <0,4,2,6>, <1,4,3,6> + 3633941814U, // <6,1,4,4>: Cost 4 vext1 <1,6,1,4>, RHS + 2693399632U, // <6,1,4,5>: Cost 3 vext3 <1,4,5,6>, <1,4,5,6> + 3765077075U, // <6,1,4,6>: Cost 4 vext3 <1,1,4,6>, <1,4,6,0> + 2646232530U, // <6,1,4,7>: Cost 3 vext2 <4,7,6,1>, <4,7,6,1> + 2687206507U, // <6,1,4,u>: Cost 3 vext3 <0,4,2,6>, <1,4,u,6> + 2647559796U, // <6,1,5,0>: Cost 3 vext2 <5,0,6,1>, <5,0,6,1> + 3765077118U, // <6,1,5,1>: Cost 4 vext3 <1,1,4,6>, <1,5,1,7> + 3767583878U, // <6,1,5,2>: Cost 4 vext3 <1,5,2,6>, <1,5,2,6> + 2686026896U, // <6,1,5,3>: Cost 3 vext3 <0,2,4,6>, <1,5,3,7> + 2693989528U, // <6,1,5,4>: Cost 3 vext3 <1,5,4,6>, <1,5,4,6> + 3767805089U, // <6,1,5,5>: Cost 4 vext3 <1,5,5,6>, <1,5,5,6> + 2652868706U, // <6,1,5,6>: Cost 3 vext2 <5,u,6,1>, <5,6,7,0> + 3908250934U, // <6,1,5,7>: Cost 4 vuzpr <2,6,0,1>, RHS + 2686026941U, // <6,1,5,u>: Cost 3 vext3 <0,2,4,6>, <1,5,u,7> + 2554241126U, // <6,1,6,0>: Cost 3 vext1 <0,6,1,6>, LHS + 3763602639U, // <6,1,6,1>: Cost 4 vext3 <0,u,2,6>, <1,6,1,7> + 3759547607U, // <6,1,6,2>: Cost 4 vext3 <0,2,1,6>, <1,6,2,6> + 3115221094U, // <6,1,6,3>: Cost 3 vtrnr <4,6,4,6>, LHS + 2554244406U, // <6,1,6,4>: Cost 3 vext1 <0,6,1,6>, RHS + 3760874739U, // <6,1,6,5>: Cost 4 vext3 <0,4,1,6>, <1,6,5,7> + 2554245944U, // <6,1,6,6>: Cost 3 vext1 <0,6,1,6>, <6,6,6,6> + 3719975758U, // <6,1,6,7>: Cost 4 vext2 <4,7,6,1>, <6,7,0,1> + 3115221099U, // <6,1,6,u>: Cost 3 vtrnr <4,6,4,6>, LHS + 2560221286U, // <6,1,7,0>: Cost 3 vext1 <1,6,1,7>, LHS + 2560222415U, // <6,1,7,1>: Cost 3 vext1 <1,6,1,7>, <1,6,1,7> + 2980497558U, // <6,1,7,2>: Cost 3 vzipr RHS, <3,0,1,2> + 3103211622U, // <6,1,7,3>: Cost 3 vtrnr <2,6,3,7>, LHS + 2560224566U, // <6,1,7,4>: Cost 3 vext1 <1,6,1,7>, RHS + 2980495698U, // <6,1,7,5>: Cost 3 vzipr RHS, <0,4,1,5> + 3633967526U, // <6,1,7,6>: Cost 4 vext1 <1,6,1,7>, <6,1,7,0> + 4054237686U, // <6,1,7,7>: Cost 4 vzipr RHS, <0,6,1,7> + 2560227118U, // <6,1,7,u>: Cost 3 vext1 <1,6,1,7>, LHS + 2560229478U, // <6,1,u,0>: Cost 3 vext1 <1,6,1,u>, LHS + 2686027117U, // <6,1,u,1>: Cost 3 vext3 <0,2,4,6>, <1,u,1,3> + 2686027129U, // <6,1,u,2>: Cost 3 vext3 <0,2,4,6>, <1,u,2,6> + 2686027132U, // <6,1,u,3>: Cost 3 vext3 <0,2,4,6>, <1,u,3,0> + 2687206795U, // <6,1,u,4>: Cost 3 vext3 <0,4,2,6>, <1,u,4,6> + 2686027157U, // <6,1,u,5>: Cost 3 vext3 <0,2,4,6>, <1,u,5,7> + 2590094093U, // <6,1,u,6>: Cost 3 vext1 <6,6,1,u>, <6,6,1,u> + 2261833350U, // <6,1,u,7>: Cost 3 vrev <7,u,1,6> + 2686027177U, // <6,1,u,u>: Cost 3 vext3 <0,2,4,6>, <1,u,u,0> + 2578153574U, // <6,2,0,0>: Cost 3 vext1 <4,6,2,0>, LHS + 1573159014U, // <6,2,0,1>: Cost 2 vext2 <4,u,6,2>, LHS + 2578155174U, // <6,2,0,2>: Cost 3 vext1 <4,6,2,0>, <2,3,0,1> + 3759769037U, // <6,2,0,3>: Cost 4 vext3 <0,2,4,6>, <2,0,3,0> + 2578156854U, // <6,2,0,4>: Cost 3 vext1 <4,6,2,0>, RHS + 3779085798U, // <6,2,0,5>: Cost 4 vext3 <3,4,5,6>, <2,0,5,7> + 2554270542U, // <6,2,0,6>: Cost 3 vext1 <0,6,2,0>, <6,7,0,1> + 3651900410U, // <6,2,0,7>: Cost 4 vext1 <4,6,2,0>, <7,0,1,2> + 1573159581U, // <6,2,0,u>: Cost 2 vext2 <4,u,6,2>, LHS + 3777021446U, // <6,2,1,0>: Cost 4 vext3 <3,1,4,6>, <2,1,0,3> + 2646901556U, // <6,2,1,1>: Cost 3 vext2 <4,u,6,2>, <1,1,1,1> + 2646901654U, // <6,2,1,2>: Cost 3 vext2 <4,u,6,2>, <1,2,3,0> + 2847047782U, // <6,2,1,3>: Cost 3 vuzpr <4,6,u,2>, LHS + 3771049517U, // <6,2,1,4>: Cost 4 vext3 <2,1,4,6>, <2,1,4,6> + 2646901904U, // <6,2,1,5>: Cost 3 vext2 <4,u,6,2>, <1,5,3,7> + 2686027324U, // <6,2,1,6>: Cost 3 vext3 <0,2,4,6>, <2,1,6,3> + 3331003480U, // <6,2,1,7>: Cost 4 vrev <7,1,2,6> + 2847047787U, // <6,2,1,u>: Cost 3 vuzpr <4,6,u,2>, LHS + 3289858234U, // <6,2,2,0>: Cost 4 vrev <0,2,2,6> + 3759769184U, // <6,2,2,1>: Cost 4 vext3 <0,2,4,6>, <2,2,1,3> + 2686027368U, // <6,2,2,2>: Cost 3 vext3 <0,2,4,6>, <2,2,2,2> + 2686027378U, // <6,2,2,3>: Cost 3 vext3 <0,2,4,6>, <2,2,3,3> + 2697971326U, // <6,2,2,4>: Cost 3 vext3 <2,2,4,6>, <2,2,4,6> + 3759769224U, // <6,2,2,5>: Cost 4 vext3 <0,2,4,6>, <2,2,5,7> + 2698118800U, // <6,2,2,6>: Cost 3 vext3 <2,2,6,6>, <2,2,6,6> + 3920794092U, // <6,2,2,7>: Cost 4 vuzpr <4,6,u,2>, <6,2,5,7> + 2686027423U, // <6,2,2,u>: Cost 3 vext3 <0,2,4,6>, <2,2,u,3> + 2686027430U, // <6,2,3,0>: Cost 3 vext3 <0,2,4,6>, <2,3,0,1> + 3759769263U, // <6,2,3,1>: Cost 4 vext3 <0,2,4,6>, <2,3,1,1> + 2228725437U, // <6,2,3,2>: Cost 3 vrev <2,3,2,6> + 2705344196U, // <6,2,3,3>: Cost 3 vext3 <3,4,5,6>, <2,3,3,4> + 2686027470U, // <6,2,3,4>: Cost 3 vext3 <0,2,4,6>, <2,3,4,5> + 2698708696U, // <6,2,3,5>: Cost 3 vext3 <2,3,5,6>, <2,3,5,6> + 2724660961U, // <6,2,3,6>: Cost 3 vext3 <6,6,6,6>, <2,3,6,6> + 2698856170U, // <6,2,3,7>: Cost 3 vext3 <2,3,7,6>, <2,3,7,6> + 2686027502U, // <6,2,3,u>: Cost 3 vext3 <0,2,4,6>, <2,3,u,1> + 1567853468U, // <6,2,4,0>: Cost 2 vext2 <4,0,6,2>, <4,0,6,2> + 3759769351U, // <6,2,4,1>: Cost 4 vext3 <0,2,4,6>, <2,4,1,u> + 2699151118U, // <6,2,4,2>: Cost 3 vext3 <2,4,2,6>, <2,4,2,6> + 2686027543U, // <6,2,4,3>: Cost 3 vext3 <0,2,4,6>, <2,4,3,6> + 2699298592U, // <6,2,4,4>: Cost 3 vext3 <2,4,4,6>, <2,4,4,6> + 1573162294U, // <6,2,4,5>: Cost 2 vext2 <4,u,6,2>, RHS + 2686027564U, // <6,2,4,6>: Cost 3 vext3 <0,2,4,6>, <2,4,6,0> + 3719982547U, // <6,2,4,7>: Cost 4 vext2 <4,7,6,2>, <4,7,6,2> + 1573162532U, // <6,2,4,u>: Cost 2 vext2 <4,u,6,2>, <4,u,6,2> + 3779086154U, // <6,2,5,0>: Cost 4 vext3 <3,4,5,6>, <2,5,0,3> + 2646904528U, // <6,2,5,1>: Cost 3 vext2 <4,u,6,2>, <5,1,7,3> + 3759769440U, // <6,2,5,2>: Cost 4 vext3 <0,2,4,6>, <2,5,2,7> + 2699888488U, // <6,2,5,3>: Cost 3 vext3 <2,5,3,6>, <2,5,3,6> + 3759769458U, // <6,2,5,4>: Cost 4 vext3 <0,2,4,6>, <2,5,4,7> + 2646904836U, // <6,2,5,5>: Cost 3 vext2 <4,u,6,2>, <5,5,5,5> + 2646904930U, // <6,2,5,6>: Cost 3 vext2 <4,u,6,2>, <5,6,7,0> + 2847051062U, // <6,2,5,7>: Cost 3 vuzpr <4,6,u,2>, RHS + 2700257173U, // <6,2,5,u>: Cost 3 vext3 <2,5,u,6>, <2,5,u,6> + 2687207321U, // <6,2,6,0>: Cost 3 vext3 <0,4,2,6>, <2,6,0,1> + 2686027684U, // <6,2,6,1>: Cost 3 vext3 <0,2,4,6>, <2,6,1,3> + 2566260656U, // <6,2,6,2>: Cost 3 vext1 <2,6,2,6>, <2,6,2,6> + 2685806522U, // <6,2,6,3>: Cost 3 vext3 <0,2,1,6>, <2,6,3,7> + 2687207361U, // <6,2,6,4>: Cost 3 vext3 <0,4,2,6>, <2,6,4,5> + 2686027724U, // <6,2,6,5>: Cost 3 vext3 <0,2,4,6>, <2,6,5,7> + 2646905656U, // <6,2,6,6>: Cost 3 vext2 <4,u,6,2>, <6,6,6,6> + 2646905678U, // <6,2,6,7>: Cost 3 vext2 <4,u,6,2>, <6,7,0,1> + 2686027751U, // <6,2,6,u>: Cost 3 vext3 <0,2,4,6>, <2,6,u,7> + 2554323046U, // <6,2,7,0>: Cost 3 vext1 <0,6,2,7>, LHS + 2560296152U, // <6,2,7,1>: Cost 3 vext1 <1,6,2,7>, <1,6,2,7> + 2566268849U, // <6,2,7,2>: Cost 3 vext1 <2,6,2,7>, <2,6,2,7> + 1906753638U, // <6,2,7,3>: Cost 2 vzipr RHS, LHS + 2554326326U, // <6,2,7,4>: Cost 3 vext1 <0,6,2,7>, RHS + 4054237288U, // <6,2,7,5>: Cost 4 vzipr RHS, <0,1,2,5> + 2980495708U, // <6,2,7,6>: Cost 3 vzipr RHS, <0,4,2,6> + 2646906476U, // <6,2,7,7>: Cost 3 vext2 <4,u,6,2>, <7,7,7,7> + 1906753643U, // <6,2,7,u>: Cost 2 vzipr RHS, LHS + 1591744256U, // <6,2,u,0>: Cost 2 vext2 , + 1573164846U, // <6,2,u,1>: Cost 2 vext2 <4,u,6,2>, LHS + 2232043602U, // <6,2,u,2>: Cost 3 vrev <2,u,2,6> + 1906761830U, // <6,2,u,3>: Cost 2 vzipr RHS, LHS + 2686027875U, // <6,2,u,4>: Cost 3 vext3 <0,2,4,6>, <2,u,4,5> + 1573165210U, // <6,2,u,5>: Cost 2 vext2 <4,u,6,2>, RHS + 2686322800U, // <6,2,u,6>: Cost 3 vext3 <0,2,u,6>, <2,u,6,0> + 2847051305U, // <6,2,u,7>: Cost 3 vuzpr <4,6,u,2>, RHS + 1906761835U, // <6,2,u,u>: Cost 2 vzipr RHS, LHS + 3759769739U, // <6,3,0,0>: Cost 4 vext3 <0,2,4,6>, <3,0,0,0> + 2686027926U, // <6,3,0,1>: Cost 3 vext3 <0,2,4,6>, <3,0,1,2> + 2686027937U, // <6,3,0,2>: Cost 3 vext3 <0,2,4,6>, <3,0,2,4> + 3640027286U, // <6,3,0,3>: Cost 4 vext1 <2,6,3,0>, <3,0,1,2> + 2687207601U, // <6,3,0,4>: Cost 3 vext3 <0,4,2,6>, <3,0,4,2> + 2705344698U, // <6,3,0,5>: Cost 3 vext3 <3,4,5,6>, <3,0,5,2> + 3663917847U, // <6,3,0,6>: Cost 4 vext1 <6,6,3,0>, <6,6,3,0> + 4195107840U, // <6,3,0,7>: Cost 4 vtrnr <5,6,7,0>, <1,3,5,7> + 2686027989U, // <6,3,0,u>: Cost 3 vext3 <0,2,4,6>, <3,0,u,2> + 2602123366U, // <6,3,1,0>: Cost 3 vext1 , LHS + 3759769830U, // <6,3,1,1>: Cost 4 vext3 <0,2,4,6>, <3,1,1,1> + 3759769841U, // <6,3,1,2>: Cost 4 vext3 <0,2,4,6>, <3,1,2,3> + 2602125462U, // <6,3,1,3>: Cost 3 vext1 , <3,0,1,2> + 2703280390U, // <6,3,1,4>: Cost 3 vext3 <3,1,4,6>, <3,1,4,6> + 3759769868U, // <6,3,1,5>: Cost 4 vext3 <0,2,4,6>, <3,1,5,3> + 3704063194U, // <6,3,1,6>: Cost 4 vext2 <2,1,6,3>, <1,6,3,0> + 3767732510U, // <6,3,1,7>: Cost 4 vext3 <1,5,4,6>, <3,1,7,3> + 2602129198U, // <6,3,1,u>: Cost 3 vext1 , LHS + 3640041574U, // <6,3,2,0>: Cost 4 vext1 <2,6,3,2>, LHS + 2686028086U, // <6,3,2,1>: Cost 3 vext3 <0,2,4,6>, <3,2,1,0> + 3759769921U, // <6,3,2,2>: Cost 4 vext3 <0,2,4,6>, <3,2,2,2> + 3759769928U, // <6,3,2,3>: Cost 4 vext3 <0,2,4,6>, <3,2,3,0> + 3704063767U, // <6,3,2,4>: Cost 4 vext2 <2,1,6,3>, <2,4,3,6> + 3704063876U, // <6,3,2,5>: Cost 4 vext2 <2,1,6,3>, <2,5,6,7> + 2636957626U, // <6,3,2,6>: Cost 3 vext2 <3,2,6,3>, <2,6,3,7> + 3708045346U, // <6,3,2,7>: Cost 4 vext2 <2,7,6,3>, <2,7,6,3> + 2689862005U, // <6,3,2,u>: Cost 3 vext3 <0,u,2,6>, <3,2,u,0> + 3759769983U, // <6,3,3,0>: Cost 4 vext3 <0,2,4,6>, <3,3,0,1> + 3710036245U, // <6,3,3,1>: Cost 4 vext2 <3,1,6,3>, <3,1,6,3> + 2636958054U, // <6,3,3,2>: Cost 3 vext2 <3,2,6,3>, <3,2,6,3> + 2686028188U, // <6,3,3,3>: Cost 3 vext3 <0,2,4,6>, <3,3,3,3> + 2704607656U, // <6,3,3,4>: Cost 3 vext3 <3,3,4,6>, <3,3,4,6> + 3773041072U, // <6,3,3,5>: Cost 4 vext3 <2,4,4,6>, <3,3,5,5> + 3710700166U, // <6,3,3,6>: Cost 4 vext2 <3,2,6,3>, <3,6,2,3> + 3767732676U, // <6,3,3,7>: Cost 4 vext3 <1,5,4,6>, <3,3,7,7> + 2707999179U, // <6,3,3,u>: Cost 3 vext3 <3,u,5,6>, <3,3,u,5> + 2584232038U, // <6,3,4,0>: Cost 3 vext1 <5,6,3,4>, LHS + 2642267118U, // <6,3,4,1>: Cost 3 vext2 <4,1,6,3>, <4,1,6,3> + 2642930751U, // <6,3,4,2>: Cost 3 vext2 <4,2,6,3>, <4,2,6,3> + 2705197552U, // <6,3,4,3>: Cost 3 vext3 <3,4,3,6>, <3,4,3,6> + 2584235318U, // <6,3,4,4>: Cost 3 vext1 <5,6,3,4>, RHS + 1631603202U, // <6,3,4,5>: Cost 2 vext3 <3,4,5,6>, <3,4,5,6> + 2654211444U, // <6,3,4,6>: Cost 3 vext2 <6,1,6,3>, <4,6,4,6> + 3779234324U, // <6,3,4,7>: Cost 4 vext3 <3,4,7,6>, <3,4,7,6> + 1631824413U, // <6,3,4,u>: Cost 2 vext3 <3,4,u,6>, <3,4,u,6> + 3640066150U, // <6,3,5,0>: Cost 4 vext1 <2,6,3,5>, LHS + 3772746288U, // <6,3,5,1>: Cost 4 vext3 <2,4,0,6>, <3,5,1,7> + 3303868264U, // <6,3,5,2>: Cost 4 vrev <2,5,3,6> + 3773041216U, // <6,3,5,3>: Cost 4 vext3 <2,4,4,6>, <3,5,3,5> + 2705934922U, // <6,3,5,4>: Cost 3 vext3 <3,5,4,6>, <3,5,4,6> + 3773041236U, // <6,3,5,5>: Cost 4 vext3 <2,4,4,6>, <3,5,5,7> + 3779086940U, // <6,3,5,6>: Cost 4 vext3 <3,4,5,6>, <3,5,6,6> + 3767732831U, // <6,3,5,7>: Cost 4 vext3 <1,5,4,6>, <3,5,7,0> + 2706229870U, // <6,3,5,u>: Cost 3 vext3 <3,5,u,6>, <3,5,u,6> + 2602164326U, // <6,3,6,0>: Cost 3 vext1 , LHS + 2654212512U, // <6,3,6,1>: Cost 3 vext2 <6,1,6,3>, <6,1,6,3> + 2566334393U, // <6,3,6,2>: Cost 3 vext1 <2,6,3,6>, <2,6,3,6> + 3773631120U, // <6,3,6,3>: Cost 4 vext3 <2,5,3,6>, <3,6,3,4> + 2602167524U, // <6,3,6,4>: Cost 3 vext1 , <4,4,6,6> + 3710702321U, // <6,3,6,5>: Cost 4 vext2 <3,2,6,3>, <6,5,7,7> + 2724661933U, // <6,3,6,6>: Cost 3 vext3 <6,6,6,6>, <3,6,6,6> + 3710702465U, // <6,3,6,7>: Cost 4 vext2 <3,2,6,3>, <6,7,5,7> + 2602170158U, // <6,3,6,u>: Cost 3 vext1 , LHS + 1492598886U, // <6,3,7,0>: Cost 2 vext1 <2,6,3,7>, LHS + 2560369889U, // <6,3,7,1>: Cost 3 vext1 <1,6,3,7>, <1,6,3,7> + 1492600762U, // <6,3,7,2>: Cost 2 vext1 <2,6,3,7>, <2,6,3,7> + 2566342806U, // <6,3,7,3>: Cost 3 vext1 <2,6,3,7>, <3,0,1,2> + 1492602166U, // <6,3,7,4>: Cost 2 vext1 <2,6,3,7>, RHS + 2602176208U, // <6,3,7,5>: Cost 3 vext1 , <5,1,7,3> + 2566345288U, // <6,3,7,6>: Cost 3 vext1 <2,6,3,7>, <6,3,7,0> + 2566346010U, // <6,3,7,7>: Cost 3 vext1 <2,6,3,7>, <7,3,6,2> + 1492604718U, // <6,3,7,u>: Cost 2 vext1 <2,6,3,7>, LHS + 1492607078U, // <6,3,u,0>: Cost 2 vext1 <2,6,3,u>, LHS + 2686028572U, // <6,3,u,1>: Cost 3 vext3 <0,2,4,6>, <3,u,1,0> + 1492608955U, // <6,3,u,2>: Cost 2 vext1 <2,6,3,u>, <2,6,3,u> + 2566350998U, // <6,3,u,3>: Cost 3 vext1 <2,6,3,u>, <3,0,1,2> + 1492610358U, // <6,3,u,4>: Cost 2 vext1 <2,6,3,u>, RHS + 1634257734U, // <6,3,u,5>: Cost 2 vext3 <3,u,5,6>, <3,u,5,6> + 2566353489U, // <6,3,u,6>: Cost 3 vext1 <2,6,3,u>, <6,3,u,0> + 2980504720U, // <6,3,u,7>: Cost 3 vzipr RHS, <1,5,3,7> + 1492612910U, // <6,3,u,u>: Cost 2 vext1 <2,6,3,u>, LHS + 3703406614U, // <6,4,0,0>: Cost 4 vext2 <2,0,6,4>, <0,0,2,4> + 2632319078U, // <6,4,0,1>: Cost 3 vext2 <2,4,6,4>, LHS + 2632319180U, // <6,4,0,2>: Cost 3 vext2 <2,4,6,4>, <0,2,4,6> + 3779087232U, // <6,4,0,3>: Cost 4 vext3 <3,4,5,6>, <4,0,3,1> + 2642936156U, // <6,4,0,4>: Cost 3 vext2 <4,2,6,4>, <0,4,2,6> + 2712570770U, // <6,4,0,5>: Cost 3 vext3 <4,6,4,6>, <4,0,5,1> + 2712570780U, // <6,4,0,6>: Cost 3 vext3 <4,6,4,6>, <4,0,6,2> + 3330487321U, // <6,4,0,7>: Cost 4 vrev <7,0,4,6> + 2632319645U, // <6,4,0,u>: Cost 3 vext2 <2,4,6,4>, LHS + 3628163174U, // <6,4,1,0>: Cost 4 vext1 <0,6,4,1>, LHS + 3295314772U, // <6,4,1,1>: Cost 4 vrev <1,1,4,6> + 3706061718U, // <6,4,1,2>: Cost 4 vext2 <2,4,6,4>, <1,2,3,0> + 2852962406U, // <6,4,1,3>: Cost 3 vuzpr <5,6,7,4>, LHS + 3628166454U, // <6,4,1,4>: Cost 4 vext1 <0,6,4,1>, RHS + 3760876514U, // <6,4,1,5>: Cost 4 vext3 <0,4,1,6>, <4,1,5,0> + 2687208430U, // <6,4,1,6>: Cost 3 vext3 <0,4,2,6>, <4,1,6,3> + 3331150954U, // <6,4,1,7>: Cost 4 vrev <7,1,4,6> + 2852962411U, // <6,4,1,u>: Cost 3 vuzpr <5,6,7,4>, LHS + 2216263884U, // <6,4,2,0>: Cost 3 vrev <0,2,4,6> + 3704071741U, // <6,4,2,1>: Cost 4 vext2 <2,1,6,4>, <2,1,6,4> + 3301951102U, // <6,4,2,2>: Cost 4 vrev <2,2,4,6> + 3705399007U, // <6,4,2,3>: Cost 4 vext2 <2,3,6,4>, <2,3,6,4> + 2632320816U, // <6,4,2,4>: Cost 3 vext2 <2,4,6,4>, <2,4,6,4> + 2923384118U, // <6,4,2,5>: Cost 3 vzipl <6,2,7,3>, RHS + 2687208508U, // <6,4,2,6>: Cost 3 vext3 <0,4,2,6>, <4,2,6,0> + 3331814587U, // <6,4,2,7>: Cost 4 vrev <7,2,4,6> + 2634975348U, // <6,4,2,u>: Cost 3 vext2 <2,u,6,4>, <2,u,6,4> + 3706062998U, // <6,4,3,0>: Cost 4 vext2 <2,4,6,4>, <3,0,1,2> + 3296642038U, // <6,4,3,1>: Cost 4 vrev <1,3,4,6> + 2228872911U, // <6,4,3,2>: Cost 3 vrev <2,3,4,6> + 3706063260U, // <6,4,3,3>: Cost 4 vext2 <2,4,6,4>, <3,3,3,3> + 2644929026U, // <6,4,3,4>: Cost 3 vext2 <4,5,6,4>, <3,4,5,6> + 3718670922U, // <6,4,3,5>: Cost 4 vext2 <4,5,6,4>, <3,5,4,6> + 2705345682U, // <6,4,3,6>: Cost 3 vext3 <3,4,5,6>, <4,3,6,5> + 3926705152U, // <6,4,3,7>: Cost 4 vuzpr <5,6,7,4>, <1,3,5,7> + 2264709093U, // <6,4,3,u>: Cost 3 vrev + 2590277734U, // <6,4,4,0>: Cost 3 vext1 <6,6,4,4>, LHS + 3716017135U, // <6,4,4,1>: Cost 4 vext2 <4,1,6,4>, <4,1,6,4> + 2642938944U, // <6,4,4,2>: Cost 3 vext2 <4,2,6,4>, <4,2,6,4> + 2235509241U, // <6,4,4,3>: Cost 3 vrev <3,4,4,6> + 2712571088U, // <6,4,4,4>: Cost 3 vext3 <4,6,4,6>, <4,4,4,4> + 2632322358U, // <6,4,4,5>: Cost 3 vext2 <2,4,6,4>, RHS + 1637649636U, // <6,4,4,6>: Cost 2 vext3 <4,4,6,6>, <4,4,6,6> + 2259400029U, // <6,4,4,7>: Cost 3 vrev <7,4,4,6> + 1637649636U, // <6,4,4,u>: Cost 2 vext3 <4,4,6,6>, <4,4,6,6> + 2566398054U, // <6,4,5,0>: Cost 3 vext1 <2,6,4,5>, LHS + 3760876805U, // <6,4,5,1>: Cost 4 vext3 <0,4,1,6>, <4,5,1,3> + 2566399937U, // <6,4,5,2>: Cost 3 vext1 <2,6,4,5>, <2,6,4,5> + 2584316418U, // <6,4,5,3>: Cost 3 vext1 <5,6,4,5>, <3,4,5,6> + 2566401334U, // <6,4,5,4>: Cost 3 vext1 <2,6,4,5>, RHS + 2584318028U, // <6,4,5,5>: Cost 3 vext1 <5,6,4,5>, <5,6,4,5> + 1612287286U, // <6,4,5,6>: Cost 2 vext3 <0,2,4,6>, RHS + 2852965686U, // <6,4,5,7>: Cost 3 vuzpr <5,6,7,4>, RHS + 1612287304U, // <6,4,5,u>: Cost 2 vext3 <0,2,4,6>, RHS + 1504608358U, // <6,4,6,0>: Cost 2 vext1 <4,6,4,6>, LHS + 2578350900U, // <6,4,6,1>: Cost 3 vext1 <4,6,4,6>, <1,1,1,1> + 2578351720U, // <6,4,6,2>: Cost 3 vext1 <4,6,4,6>, <2,2,2,2> + 2578352278U, // <6,4,6,3>: Cost 3 vext1 <4,6,4,6>, <3,0,1,2> + 1504611638U, // <6,4,6,4>: Cost 2 vext1 <4,6,4,6>, RHS + 2578353872U, // <6,4,6,5>: Cost 3 vext1 <4,6,4,6>, <5,1,7,3> + 2578354682U, // <6,4,6,6>: Cost 3 vext1 <4,6,4,6>, <6,2,7,3> + 2578355194U, // <6,4,6,7>: Cost 3 vext1 <4,6,4,6>, <7,0,1,2> + 1504614190U, // <6,4,6,u>: Cost 2 vext1 <4,6,4,6>, LHS + 2572386406U, // <6,4,7,0>: Cost 3 vext1 <3,6,4,7>, LHS + 2572387226U, // <6,4,7,1>: Cost 3 vext1 <3,6,4,7>, <1,2,3,4> + 3640157902U, // <6,4,7,2>: Cost 4 vext1 <2,6,4,7>, <2,3,4,5> + 2572389020U, // <6,4,7,3>: Cost 3 vext1 <3,6,4,7>, <3,6,4,7> + 2572389686U, // <6,4,7,4>: Cost 3 vext1 <3,6,4,7>, RHS + 2980497102U, // <6,4,7,5>: Cost 3 vzipr RHS, <2,3,4,5> + 2980495564U, // <6,4,7,6>: Cost 3 vzipr RHS, <0,2,4,6> + 4054239090U, // <6,4,7,7>: Cost 4 vzipr RHS, <2,5,4,7> + 2572392238U, // <6,4,7,u>: Cost 3 vext1 <3,6,4,7>, LHS + 1504608358U, // <6,4,u,0>: Cost 2 vext1 <4,6,4,6>, LHS + 2632324910U, // <6,4,u,1>: Cost 3 vext2 <2,4,6,4>, LHS + 2566424516U, // <6,4,u,2>: Cost 3 vext1 <2,6,4,u>, <2,6,4,u> + 2584340994U, // <6,4,u,3>: Cost 3 vext1 <5,6,4,u>, <3,4,5,6> + 1640156694U, // <6,4,u,4>: Cost 2 vext3 <4,u,4,6>, <4,u,4,6> + 2632325274U, // <6,4,u,5>: Cost 3 vext2 <2,4,6,4>, RHS + 1612287529U, // <6,4,u,6>: Cost 2 vext3 <0,2,4,6>, RHS + 2852965929U, // <6,4,u,7>: Cost 3 vuzpr <5,6,7,4>, RHS + 1612287547U, // <6,4,u,u>: Cost 2 vext3 <0,2,4,6>, RHS + 3708723200U, // <6,5,0,0>: Cost 4 vext2 <2,u,6,5>, <0,0,0,0> + 2634981478U, // <6,5,0,1>: Cost 3 vext2 <2,u,6,5>, LHS + 3694125260U, // <6,5,0,2>: Cost 4 vext2 <0,4,6,5>, <0,2,4,6> + 3779087962U, // <6,5,0,3>: Cost 4 vext3 <3,4,5,6>, <5,0,3,2> + 3760877154U, // <6,5,0,4>: Cost 4 vext3 <0,4,1,6>, <5,0,4,1> + 4195110916U, // <6,5,0,5>: Cost 4 vtrnr <5,6,7,0>, <5,5,5,5> + 3696779775U, // <6,5,0,6>: Cost 4 vext2 <0,u,6,5>, <0,6,2,7> + 3121368374U, // <6,5,0,7>: Cost 3 vtrnr <5,6,7,0>, RHS + 2634982045U, // <6,5,0,u>: Cost 3 vext2 <2,u,6,5>, LHS + 3652124774U, // <6,5,1,0>: Cost 4 vext1 <4,6,5,1>, LHS + 3698107237U, // <6,5,1,1>: Cost 4 vext2 <1,1,6,5>, <1,1,6,5> + 3708724118U, // <6,5,1,2>: Cost 4 vext2 <2,u,6,5>, <1,2,3,0> + 2642281472U, // <6,5,1,3>: Cost 3 vext2 <4,1,6,5>, <1,3,5,7> + 3760877234U, // <6,5,1,4>: Cost 4 vext3 <0,4,1,6>, <5,1,4,0> + 3708724368U, // <6,5,1,5>: Cost 4 vext2 <2,u,6,5>, <1,5,3,7> + 3708724449U, // <6,5,1,6>: Cost 4 vext2 <2,u,6,5>, <1,6,3,7> + 2712571600U, // <6,5,1,7>: Cost 3 vext3 <4,6,4,6>, <5,1,7,3> + 2712571609U, // <6,5,1,u>: Cost 3 vext3 <4,6,4,6>, <5,1,u,3> + 2578391142U, // <6,5,2,0>: Cost 3 vext1 <4,6,5,2>, LHS + 3704079934U, // <6,5,2,1>: Cost 4 vext2 <2,1,6,5>, <2,1,6,5> + 3708724840U, // <6,5,2,2>: Cost 4 vext2 <2,u,6,5>, <2,2,2,2> + 3705407182U, // <6,5,2,3>: Cost 4 vext2 <2,3,6,5>, <2,3,4,5> + 2578394422U, // <6,5,2,4>: Cost 3 vext1 <4,6,5,2>, RHS + 3652136656U, // <6,5,2,5>: Cost 4 vext1 <4,6,5,2>, <5,1,7,3> + 2634983354U, // <6,5,2,6>: Cost 3 vext2 <2,u,6,5>, <2,6,3,7> + 3115486518U, // <6,5,2,7>: Cost 3 vtrnr <4,6,u,2>, RHS + 2634983541U, // <6,5,2,u>: Cost 3 vext2 <2,u,6,5>, <2,u,6,5> + 3708725398U, // <6,5,3,0>: Cost 4 vext2 <2,u,6,5>, <3,0,1,2> + 3710052631U, // <6,5,3,1>: Cost 4 vext2 <3,1,6,5>, <3,1,6,5> + 2228946648U, // <6,5,3,2>: Cost 3 vrev <2,3,5,6> + 3708725660U, // <6,5,3,3>: Cost 4 vext2 <2,u,6,5>, <3,3,3,3> + 2643610114U, // <6,5,3,4>: Cost 3 vext2 <4,3,6,5>, <3,4,5,6> + 3696118365U, // <6,5,3,5>: Cost 4 vext2 <0,7,6,5>, <3,5,6,7> + 3773632358U, // <6,5,3,6>: Cost 4 vext3 <2,5,3,6>, <5,3,6,0> + 2640292605U, // <6,5,3,7>: Cost 3 vext2 <3,7,6,5>, <3,7,6,5> + 2264782830U, // <6,5,3,u>: Cost 3 vrev + 1522581606U, // <6,5,4,0>: Cost 2 vext1 <7,6,5,4>, LHS + 2223637584U, // <6,5,4,1>: Cost 3 vrev <1,4,5,6> + 2229610281U, // <6,5,4,2>: Cost 3 vrev <2,4,5,6> + 1161841154U, // <6,5,4,3>: Cost 2 vrev <3,4,5,6> + 1522584886U, // <6,5,4,4>: Cost 2 vext1 <7,6,5,4>, RHS + 2634984758U, // <6,5,4,5>: Cost 3 vext2 <2,u,6,5>, RHS + 2253501069U, // <6,5,4,6>: Cost 3 vrev <6,4,5,6> + 1185731942U, // <6,5,4,7>: Cost 2 vrev <7,4,5,6> + 1522587438U, // <6,5,4,u>: Cost 2 vext1 <7,6,5,4>, LHS + 2578415718U, // <6,5,5,0>: Cost 3 vext1 <4,6,5,5>, LHS + 3652158260U, // <6,5,5,1>: Cost 4 vext1 <4,6,5,5>, <1,1,1,1> + 3652159080U, // <6,5,5,2>: Cost 4 vext1 <4,6,5,5>, <2,2,2,2> + 3652159638U, // <6,5,5,3>: Cost 4 vext1 <4,6,5,5>, <3,0,1,2> + 2578418998U, // <6,5,5,4>: Cost 3 vext1 <4,6,5,5>, RHS + 2712571908U, // <6,5,5,5>: Cost 3 vext3 <4,6,4,6>, <5,5,5,5> + 2718027790U, // <6,5,5,6>: Cost 3 vext3 <5,5,6,6>, <5,5,6,6> + 2712571928U, // <6,5,5,7>: Cost 3 vext3 <4,6,4,6>, <5,5,7,7> + 2712571937U, // <6,5,5,u>: Cost 3 vext3 <4,6,4,6>, <5,5,u,7> + 2705346596U, // <6,5,6,0>: Cost 3 vext3 <3,4,5,6>, <5,6,0,1> + 3767144496U, // <6,5,6,1>: Cost 4 vext3 <1,4,5,6>, <5,6,1,4> + 3773116473U, // <6,5,6,2>: Cost 4 vext3 <2,4,5,6>, <5,6,2,4> + 2705346626U, // <6,5,6,3>: Cost 3 vext3 <3,4,5,6>, <5,6,3,4> + 2705346636U, // <6,5,6,4>: Cost 3 vext3 <3,4,5,6>, <5,6,4,5> + 3908577217U, // <6,5,6,5>: Cost 4 vuzpr <2,6,4,5>, <2,6,4,5> + 2578428728U, // <6,5,6,6>: Cost 3 vext1 <4,6,5,6>, <6,6,6,6> + 2712572002U, // <6,5,6,7>: Cost 3 vext3 <4,6,4,6>, <5,6,7,0> + 2705346668U, // <6,5,6,u>: Cost 3 vext3 <3,4,5,6>, <5,6,u,1> + 2560516198U, // <6,5,7,0>: Cost 3 vext1 <1,6,5,7>, LHS + 2560517363U, // <6,5,7,1>: Cost 3 vext1 <1,6,5,7>, <1,6,5,7> + 2566490060U, // <6,5,7,2>: Cost 3 vext1 <2,6,5,7>, <2,6,5,7> + 3634260118U, // <6,5,7,3>: Cost 4 vext1 <1,6,5,7>, <3,0,1,2> + 2560519478U, // <6,5,7,4>: Cost 3 vext1 <1,6,5,7>, RHS + 2980498650U, // <6,5,7,5>: Cost 3 vzipr RHS, <4,4,5,5> + 2980497922U, // <6,5,7,6>: Cost 3 vzipr RHS, <3,4,5,6> + 3103214902U, // <6,5,7,7>: Cost 3 vtrnr <2,6,3,7>, RHS + 2560522030U, // <6,5,7,u>: Cost 3 vext1 <1,6,5,7>, LHS + 1528586342U, // <6,5,u,0>: Cost 2 vext1 , LHS + 2560525556U, // <6,5,u,1>: Cost 3 vext1 <1,6,5,u>, <1,6,5,u> + 2566498253U, // <6,5,u,2>: Cost 3 vext1 <2,6,5,u>, <2,6,5,u> + 1164495686U, // <6,5,u,3>: Cost 2 vrev <3,u,5,6> + 1528589622U, // <6,5,u,4>: Cost 2 vext1 , RHS + 2634987674U, // <6,5,u,5>: Cost 3 vext2 <2,u,6,5>, RHS + 2980506114U, // <6,5,u,6>: Cost 3 vzipr RHS, <3,4,5,6> + 1188386474U, // <6,5,u,7>: Cost 2 vrev <7,u,5,6> + 1528592611U, // <6,5,u,u>: Cost 2 vext1 , + 2578448486U, // <6,6,0,0>: Cost 3 vext1 <4,6,6,0>, LHS + 1573191782U, // <6,6,0,1>: Cost 2 vext2 <4,u,6,6>, LHS + 2686030124U, // <6,6,0,2>: Cost 3 vext3 <0,2,4,6>, <6,0,2,4> + 3779088690U, // <6,6,0,3>: Cost 4 vext3 <3,4,5,6>, <6,0,3,1> + 2687209788U, // <6,6,0,4>: Cost 3 vext3 <0,4,2,6>, <6,0,4,2> + 3652194000U, // <6,6,0,5>: Cost 4 vext1 <4,6,6,0>, <5,1,7,3> + 2590397234U, // <6,6,0,6>: Cost 3 vext1 <6,6,6,0>, <6,6,6,0> + 4041575734U, // <6,6,0,7>: Cost 4 vzipr <2,4,6,0>, RHS + 1573192349U, // <6,6,0,u>: Cost 2 vext2 <4,u,6,6>, LHS + 3640254566U, // <6,6,1,0>: Cost 4 vext1 <2,6,6,1>, LHS + 2646934324U, // <6,6,1,1>: Cost 3 vext2 <4,u,6,6>, <1,1,1,1> + 2646934422U, // <6,6,1,2>: Cost 3 vext2 <4,u,6,6>, <1,2,3,0> + 2846785638U, // <6,6,1,3>: Cost 3 vuzpr <4,6,4,6>, LHS + 3760877963U, // <6,6,1,4>: Cost 4 vext3 <0,4,1,6>, <6,1,4,0> + 2646934672U, // <6,6,1,5>: Cost 3 vext2 <4,u,6,6>, <1,5,3,7> + 2712572320U, // <6,6,1,6>: Cost 3 vext3 <4,6,4,6>, <6,1,6,3> + 3775549865U, // <6,6,1,7>: Cost 4 vext3 <2,u,2,6>, <6,1,7,3> + 2846785643U, // <6,6,1,u>: Cost 3 vuzpr <4,6,4,6>, LHS + 3640262758U, // <6,6,2,0>: Cost 4 vext1 <2,6,6,2>, LHS + 3704751676U, // <6,6,2,1>: Cost 4 vext2 <2,2,6,6>, <2,1,6,3> + 2631009936U, // <6,6,2,2>: Cost 3 vext2 <2,2,6,6>, <2,2,6,6> + 2646935206U, // <6,6,2,3>: Cost 3 vext2 <4,u,6,6>, <2,3,0,1> + 2687209948U, // <6,6,2,4>: Cost 3 vext3 <0,4,2,6>, <6,2,4,0> + 3704752004U, // <6,6,2,5>: Cost 4 vext2 <2,2,6,6>, <2,5,6,7> + 2646935482U, // <6,6,2,6>: Cost 3 vext2 <4,u,6,6>, <2,6,3,7> + 2712572410U, // <6,6,2,7>: Cost 3 vext3 <4,6,4,6>, <6,2,7,3> + 2712572419U, // <6,6,2,u>: Cost 3 vext3 <4,6,4,6>, <6,2,u,3> + 2646935702U, // <6,6,3,0>: Cost 3 vext2 <4,u,6,6>, <3,0,1,2> + 3777024534U, // <6,6,3,1>: Cost 4 vext3 <3,1,4,6>, <6,3,1,4> + 2646935862U, // <6,6,3,2>: Cost 3 vext2 <4,u,6,6>, <3,2,1,0> + 2646935964U, // <6,6,3,3>: Cost 3 vext2 <4,u,6,6>, <3,3,3,3> + 2705347122U, // <6,6,3,4>: Cost 3 vext3 <3,4,5,6>, <6,3,4,5> + 3773633080U, // <6,6,3,5>: Cost 4 vext3 <2,5,3,6>, <6,3,5,2> + 2657553069U, // <6,6,3,6>: Cost 3 vext2 <6,6,6,6>, <3,6,6,6> + 4039609654U, // <6,6,3,7>: Cost 4 vzipr <2,1,6,3>, RHS + 2708001366U, // <6,6,3,u>: Cost 3 vext3 <3,u,5,6>, <6,3,u,5> + 2646936466U, // <6,6,4,0>: Cost 3 vext2 <4,u,6,6>, <4,0,5,1> + 3765080676U, // <6,6,4,1>: Cost 4 vext3 <1,1,4,6>, <6,4,1,1> + 2686030444U, // <6,6,4,2>: Cost 3 vext3 <0,2,4,6>, <6,4,2,0> + 3766407798U, // <6,6,4,3>: Cost 4 vext3 <1,3,4,6>, <6,4,3,1> + 1570540772U, // <6,6,4,4>: Cost 2 vext2 <4,4,6,6>, <4,4,6,6> + 1573195062U, // <6,6,4,5>: Cost 2 vext2 <4,u,6,6>, RHS + 2712572560U, // <6,6,4,6>: Cost 3 vext3 <4,6,4,6>, <6,4,6,0> + 2723410591U, // <6,6,4,7>: Cost 3 vext3 <6,4,7,6>, <6,4,7,6> + 1573195304U, // <6,6,4,u>: Cost 2 vext2 <4,u,6,6>, <4,u,6,6> + 3640287334U, // <6,6,5,0>: Cost 4 vext1 <2,6,6,5>, LHS + 2646937296U, // <6,6,5,1>: Cost 3 vext2 <4,u,6,6>, <5,1,7,3> + 3640289235U, // <6,6,5,2>: Cost 4 vext1 <2,6,6,5>, <2,6,6,5> + 3720679279U, // <6,6,5,3>: Cost 4 vext2 <4,u,6,6>, <5,3,7,0> + 2705347282U, // <6,6,5,4>: Cost 3 vext3 <3,4,5,6>, <6,5,4,3> + 2646937604U, // <6,6,5,5>: Cost 3 vext2 <4,u,6,6>, <5,5,5,5> + 2646937698U, // <6,6,5,6>: Cost 3 vext2 <4,u,6,6>, <5,6,7,0> + 2846788918U, // <6,6,5,7>: Cost 3 vuzpr <4,6,4,6>, RHS + 2708001526U, // <6,6,5,u>: Cost 3 vext3 <3,u,5,6>, <6,5,u,3> + 1516699750U, // <6,6,6,0>: Cost 2 vext1 <6,6,6,6>, LHS + 2590442292U, // <6,6,6,1>: Cost 3 vext1 <6,6,6,6>, <1,1,1,1> + 2646938106U, // <6,6,6,2>: Cost 3 vext2 <4,u,6,6>, <6,2,7,3> + 2590443670U, // <6,6,6,3>: Cost 3 vext1 <6,6,6,6>, <3,0,1,2> + 1516703030U, // <6,6,6,4>: Cost 2 vext1 <6,6,6,6>, RHS + 2590445264U, // <6,6,6,5>: Cost 3 vext1 <6,6,6,6>, <5,1,7,3> + 296144182U, // <6,6,6,6>: Cost 1 vdup2 RHS + 2712572738U, // <6,6,6,7>: Cost 3 vext3 <4,6,4,6>, <6,6,7,7> + 296144182U, // <6,6,6,u>: Cost 1 vdup2 RHS + 2566561894U, // <6,6,7,0>: Cost 3 vext1 <2,6,6,7>, LHS + 3634332924U, // <6,6,7,1>: Cost 4 vext1 <1,6,6,7>, <1,6,6,7> + 2566563797U, // <6,6,7,2>: Cost 3 vext1 <2,6,6,7>, <2,6,6,7> + 2584480258U, // <6,6,7,3>: Cost 3 vext1 <5,6,6,7>, <3,4,5,6> + 2566565174U, // <6,6,7,4>: Cost 3 vext1 <2,6,6,7>, RHS + 2584481888U, // <6,6,7,5>: Cost 3 vext1 <5,6,6,7>, <5,6,6,7> + 2980500280U, // <6,6,7,6>: Cost 3 vzipr RHS, <6,6,6,6> + 1906756918U, // <6,6,7,7>: Cost 2 vzipr RHS, RHS + 1906756919U, // <6,6,7,u>: Cost 2 vzipr RHS, RHS + 1516699750U, // <6,6,u,0>: Cost 2 vext1 <6,6,6,6>, LHS + 1573197614U, // <6,6,u,1>: Cost 2 vext2 <4,u,6,6>, LHS + 2686325680U, // <6,6,u,2>: Cost 3 vext3 <0,2,u,6>, <6,u,2,0> + 2846786205U, // <6,6,u,3>: Cost 3 vuzpr <4,6,4,6>, LHS + 1516703030U, // <6,6,u,4>: Cost 2 vext1 <6,6,6,6>, RHS + 1573197978U, // <6,6,u,5>: Cost 2 vext2 <4,u,6,6>, RHS + 296144182U, // <6,6,u,6>: Cost 1 vdup2 RHS + 1906765110U, // <6,6,u,7>: Cost 2 vzipr RHS, RHS + 296144182U, // <6,6,u,u>: Cost 1 vdup2 RHS + 1571209216U, // <6,7,0,0>: Cost 2 vext2 RHS, <0,0,0,0> + 497467494U, // <6,7,0,1>: Cost 1 vext2 RHS, LHS + 1571209380U, // <6,7,0,2>: Cost 2 vext2 RHS, <0,2,0,2> + 2644951292U, // <6,7,0,3>: Cost 3 vext2 RHS, <0,3,1,0> + 1571209554U, // <6,7,0,4>: Cost 2 vext2 RHS, <0,4,1,5> + 1510756450U, // <6,7,0,5>: Cost 2 vext1 <5,6,7,0>, <5,6,7,0> + 2644951542U, // <6,7,0,6>: Cost 3 vext2 RHS, <0,6,1,7> + 2584499194U, // <6,7,0,7>: Cost 3 vext1 <5,6,7,0>, <7,0,1,2> + 497468061U, // <6,7,0,u>: Cost 1 vext2 RHS, LHS + 2644951770U, // <6,7,1,0>: Cost 3 vext2 RHS, <1,0,0,1> + 1571210036U, // <6,7,1,1>: Cost 2 vext2 RHS, <1,1,1,1> + 1571210134U, // <6,7,1,2>: Cost 2 vext2 RHS, <1,2,3,0> + 1571210200U, // <6,7,1,3>: Cost 2 vext2 RHS, <1,3,1,3> + 2644952107U, // <6,7,1,4>: Cost 3 vext2 RHS, <1,4,1,5> + 1571210384U, // <6,7,1,5>: Cost 2 vext2 RHS, <1,5,3,7> + 2644952262U, // <6,7,1,6>: Cost 3 vext2 RHS, <1,6,0,7> + 2578535418U, // <6,7,1,7>: Cost 3 vext1 <4,6,7,1>, <7,0,1,2> + 1571210605U, // <6,7,1,u>: Cost 2 vext2 RHS, <1,u,1,3> + 2644952509U, // <6,7,2,0>: Cost 3 vext2 RHS, <2,0,1,2> + 2644952579U, // <6,7,2,1>: Cost 3 vext2 RHS, <2,1,0,0> + 1571210856U, // <6,7,2,2>: Cost 2 vext2 RHS, <2,2,2,2> + 1571210918U, // <6,7,2,3>: Cost 2 vext2 RHS, <2,3,0,1> + 2644952828U, // <6,7,2,4>: Cost 3 vext2 RHS, <2,4,0,6> + 2633009028U, // <6,7,2,5>: Cost 3 vext2 <2,5,6,7>, <2,5,6,7> + 1571211194U, // <6,7,2,6>: Cost 2 vext2 RHS, <2,6,3,7> + 2668840938U, // <6,7,2,7>: Cost 3 vext2 RHS, <2,7,0,1> + 1571211323U, // <6,7,2,u>: Cost 2 vext2 RHS, <2,u,0,1> + 1571211414U, // <6,7,3,0>: Cost 2 vext2 RHS, <3,0,1,2> + 2644953318U, // <6,7,3,1>: Cost 3 vext2 RHS, <3,1,1,1> + 1571211574U, // <6,7,3,2>: Cost 2 vext2 RHS, <3,2,1,0> + 1571211676U, // <6,7,3,3>: Cost 2 vext2 RHS, <3,3,3,3> + 1571211778U, // <6,7,3,4>: Cost 2 vext2 RHS, <3,4,5,6> + 2644953648U, // <6,7,3,5>: Cost 3 vext2 RHS, <3,5,1,7> + 2644953720U, // <6,7,3,6>: Cost 3 vext2 RHS, <3,6,0,7> + 2644953795U, // <6,7,3,7>: Cost 3 vext2 RHS, <3,7,0,1> + 1571212060U, // <6,7,3,u>: Cost 2 vext2 RHS, <3,u,1,0> + 1573202834U, // <6,7,4,0>: Cost 2 vext2 RHS, <4,0,5,1> + 2644954058U, // <6,7,4,1>: Cost 3 vext2 RHS, <4,1,2,3> + 2644954166U, // <6,7,4,2>: Cost 3 vext2 RHS, <4,2,5,3> + 2644954218U, // <6,7,4,3>: Cost 3 vext2 RHS, <4,3,2,1> + 1571212496U, // <6,7,4,4>: Cost 2 vext2 RHS, <4,4,4,4> + 497470774U, // <6,7,4,5>: Cost 1 vext2 RHS, RHS + 1573203316U, // <6,7,4,6>: Cost 2 vext2 RHS, <4,6,4,6> + 2646281688U, // <6,7,4,7>: Cost 3 vext2 <4,7,6,7>, <4,7,6,7> + 497471017U, // <6,7,4,u>: Cost 1 vext2 RHS, RHS + 2644954696U, // <6,7,5,0>: Cost 3 vext2 RHS, <5,0,1,2> + 1573203664U, // <6,7,5,1>: Cost 2 vext2 RHS, <5,1,7,3> + 2644954878U, // <6,7,5,2>: Cost 3 vext2 RHS, <5,2,3,4> + 2644954991U, // <6,7,5,3>: Cost 3 vext2 RHS, <5,3,7,0> + 2644955038U, // <6,7,5,4>: Cost 3 vext2 RHS, <5,4,3,2> + 1571213316U, // <6,7,5,5>: Cost 2 vext2 RHS, <5,5,5,5> + 1571213410U, // <6,7,5,6>: Cost 2 vext2 RHS, <5,6,7,0> + 1573204136U, // <6,7,5,7>: Cost 2 vext2 RHS, <5,7,5,7> + 1573204217U, // <6,7,5,u>: Cost 2 vext2 RHS, <5,u,5,7> + 2644955425U, // <6,7,6,0>: Cost 3 vext2 RHS, <6,0,1,2> + 2644955561U, // <6,7,6,1>: Cost 3 vext2 RHS, <6,1,7,3> + 1573204474U, // <6,7,6,2>: Cost 2 vext2 RHS, <6,2,7,3> + 2644955698U, // <6,7,6,3>: Cost 3 vext2 RHS, <6,3,4,5> + 2644955756U, // <6,7,6,4>: Cost 3 vext2 RHS, <6,4,2,0> + 2644955858U, // <6,7,6,5>: Cost 3 vext2 RHS, <6,5,4,3> + 1571214136U, // <6,7,6,6>: Cost 2 vext2 RHS, <6,6,6,6> + 1571214158U, // <6,7,6,7>: Cost 2 vext2 RHS, <6,7,0,1> + 1573204895U, // <6,7,6,u>: Cost 2 vext2 RHS, <6,u,0,1> + 1573204986U, // <6,7,7,0>: Cost 2 vext2 RHS, <7,0,1,2> + 2572608656U, // <6,7,7,1>: Cost 3 vext1 <3,6,7,7>, <1,5,3,7> + 2644956362U, // <6,7,7,2>: Cost 3 vext2 RHS, <7,2,6,3> + 2572610231U, // <6,7,7,3>: Cost 3 vext1 <3,6,7,7>, <3,6,7,7> + 1573205350U, // <6,7,7,4>: Cost 2 vext2 RHS, <7,4,5,6> + 2644956576U, // <6,7,7,5>: Cost 3 vext2 RHS, <7,5,3,1> + 1571214854U, // <6,7,7,6>: Cost 2 vext2 RHS, <7,6,5,4> + 1571214956U, // <6,7,7,7>: Cost 2 vext2 RHS, <7,7,7,7> + 1573205634U, // <6,7,7,u>: Cost 2 vext2 RHS, <7,u,1,2> + 1571215059U, // <6,7,u,0>: Cost 2 vext2 RHS, + 497473326U, // <6,7,u,1>: Cost 1 vext2 RHS, LHS + 1571215219U, // <6,7,u,2>: Cost 2 vext2 RHS, + 1571215292U, // <6,7,u,3>: Cost 2 vext2 RHS, + 1571215423U, // <6,7,u,4>: Cost 2 vext2 RHS, + 497473690U, // <6,7,u,5>: Cost 1 vext2 RHS, RHS + 1571215568U, // <6,7,u,6>: Cost 2 vext2 RHS, + 1573206272U, // <6,7,u,7>: Cost 2 vext2 RHS, + 497473893U, // <6,7,u,u>: Cost 1 vext2 RHS, LHS + 1571217408U, // <6,u,0,0>: Cost 2 vext2 RHS, <0,0,0,0> + 497475686U, // <6,u,0,1>: Cost 1 vext2 RHS, LHS + 1571217572U, // <6,u,0,2>: Cost 2 vext2 RHS, <0,2,0,2> + 2644959484U, // <6,u,0,3>: Cost 3 vext2 RHS, <0,3,1,0> + 1571217746U, // <6,u,0,4>: Cost 2 vext2 RHS, <0,4,1,5> + 1510830187U, // <6,u,0,5>: Cost 2 vext1 <5,6,u,0>, <5,6,u,0> + 2644959734U, // <6,u,0,6>: Cost 3 vext2 RHS, <0,6,1,7> + 3121368617U, // <6,u,0,7>: Cost 3 vtrnr <5,6,7,0>, RHS + 497476253U, // <6,u,0,u>: Cost 1 vext2 RHS, LHS + 2566660198U, // <6,u,1,0>: Cost 3 vext1 <2,6,u,1>, LHS + 1571218228U, // <6,u,1,1>: Cost 2 vext2 RHS, <1,1,1,1> + 1612289838U, // <6,u,1,2>: Cost 2 vext3 <0,2,4,6>, LHS + 1571218392U, // <6,u,1,3>: Cost 2 vext2 RHS, <1,3,1,3> + 2566663478U, // <6,u,1,4>: Cost 3 vext1 <2,6,u,1>, RHS + 1571218576U, // <6,u,1,5>: Cost 2 vext2 RHS, <1,5,3,7> + 2644960454U, // <6,u,1,6>: Cost 3 vext2 RHS, <1,6,0,7> + 2724665179U, // <6,u,1,7>: Cost 3 vext3 <6,6,6,6>, + 1612289892U, // <6,u,1,u>: Cost 2 vext3 <0,2,4,6>, LHS + 1504870502U, // <6,u,2,0>: Cost 2 vext1 <4,6,u,2>, LHS + 2686031731U, // <6,u,2,1>: Cost 3 vext3 <0,2,4,6>, + 1571219048U, // <6,u,2,2>: Cost 2 vext2 RHS, <2,2,2,2> + 1571219110U, // <6,u,2,3>: Cost 2 vext2 RHS, <2,3,0,1> + 1504873782U, // <6,u,2,4>: Cost 2 vext1 <4,6,u,2>, RHS + 2633017221U, // <6,u,2,5>: Cost 3 vext2 <2,5,6,u>, <2,5,6,u> + 1571219386U, // <6,u,2,6>: Cost 2 vext2 RHS, <2,6,3,7> + 2712573868U, // <6,u,2,7>: Cost 3 vext3 <4,6,4,6>, + 1571219515U, // <6,u,2,u>: Cost 2 vext2 RHS, <2,u,0,1> + 1571219606U, // <6,u,3,0>: Cost 2 vext2 RHS, <3,0,1,2> + 2644961510U, // <6,u,3,1>: Cost 3 vext2 RHS, <3,1,1,1> + 1571219766U, // <6,u,3,2>: Cost 2 vext2 RHS, <3,2,1,0> + 1571219868U, // <6,u,3,3>: Cost 2 vext2 RHS, <3,3,3,3> + 1571219970U, // <6,u,3,4>: Cost 2 vext2 RHS, <3,4,5,6> + 2689865711U, // <6,u,3,5>: Cost 3 vext3 <0,u,2,6>, + 2644961912U, // <6,u,3,6>: Cost 3 vext2 RHS, <3,6,0,7> + 2644961987U, // <6,u,3,7>: Cost 3 vext2 RHS, <3,7,0,1> + 1571220252U, // <6,u,3,u>: Cost 2 vext2 RHS, <3,u,1,0> + 1571220370U, // <6,u,4,0>: Cost 2 vext2 RHS, <4,0,5,1> + 2223858795U, // <6,u,4,1>: Cost 3 vrev <1,4,u,6> + 1661245476U, // <6,u,4,2>: Cost 2 vext3 , + 1162062365U, // <6,u,4,3>: Cost 2 vrev <3,4,u,6> + 1571220688U, // <6,u,4,4>: Cost 2 vext2 RHS, <4,4,4,4> + 497478967U, // <6,u,4,5>: Cost 1 vext2 RHS, RHS + 1571220852U, // <6,u,4,6>: Cost 2 vext2 RHS, <4,6,4,6> + 1185953153U, // <6,u,4,7>: Cost 2 vrev <7,4,u,6> + 497479209U, // <6,u,4,u>: Cost 1 vext2 RHS, RHS + 2566692966U, // <6,u,5,0>: Cost 3 vext1 <2,6,u,5>, LHS + 1571221200U, // <6,u,5,1>: Cost 2 vext2 RHS, <5,1,7,3> + 2566694885U, // <6,u,5,2>: Cost 3 vext1 <2,6,u,5>, <2,6,u,5> + 2689865855U, // <6,u,5,3>: Cost 3 vext3 <0,u,2,6>, + 2566696246U, // <6,u,5,4>: Cost 3 vext1 <2,6,u,5>, RHS + 1571221508U, // <6,u,5,5>: Cost 2 vext2 RHS, <5,5,5,5> + 1612290202U, // <6,u,5,6>: Cost 2 vext3 <0,2,4,6>, RHS + 1571221672U, // <6,u,5,7>: Cost 2 vext2 RHS, <5,7,5,7> + 1612290220U, // <6,u,5,u>: Cost 2 vext3 <0,2,4,6>, RHS + 1504903270U, // <6,u,6,0>: Cost 2 vext1 <4,6,u,6>, LHS + 2644963752U, // <6,u,6,1>: Cost 3 vext2 RHS, <6,1,7,2> + 1571222010U, // <6,u,6,2>: Cost 2 vext2 RHS, <6,2,7,3> + 2686032080U, // <6,u,6,3>: Cost 3 vext3 <0,2,4,6>, + 1504906550U, // <6,u,6,4>: Cost 2 vext1 <4,6,u,6>, RHS + 2644964050U, // <6,u,6,5>: Cost 3 vext2 RHS, <6,5,4,3> + 296144182U, // <6,u,6,6>: Cost 1 vdup2 RHS + 1571222350U, // <6,u,6,7>: Cost 2 vext2 RHS, <6,7,0,1> + 296144182U, // <6,u,6,u>: Cost 1 vdup2 RHS + 1492967526U, // <6,u,7,0>: Cost 2 vext1 <2,6,u,7>, LHS + 2560738574U, // <6,u,7,1>: Cost 3 vext1 <1,6,u,7>, <1,6,u,7> + 1492969447U, // <6,u,7,2>: Cost 2 vext1 <2,6,u,7>, <2,6,u,7> + 1906753692U, // <6,u,7,3>: Cost 2 vzipr RHS, LHS + 1492970806U, // <6,u,7,4>: Cost 2 vext1 <2,6,u,7>, RHS + 2980495761U, // <6,u,7,5>: Cost 3 vzipr RHS, <0,4,u,5> + 1571223046U, // <6,u,7,6>: Cost 2 vext2 RHS, <7,6,5,4> + 1906756936U, // <6,u,7,7>: Cost 2 vzipr RHS, RHS + 1492973358U, // <6,u,7,u>: Cost 2 vext1 <2,6,u,7>, LHS + 1492975718U, // <6,u,u,0>: Cost 2 vext1 <2,6,u,u>, LHS + 497481518U, // <6,u,u,1>: Cost 1 vext2 RHS, LHS + 1612290405U, // <6,u,u,2>: Cost 2 vext3 <0,2,4,6>, LHS + 1164716897U, // <6,u,u,3>: Cost 2 vrev <3,u,u,6> + 1492978998U, // <6,u,u,4>: Cost 2 vext1 <2,6,u,u>, RHS + 497481882U, // <6,u,u,5>: Cost 1 vext2 RHS, RHS + 296144182U, // <6,u,u,6>: Cost 1 vdup2 RHS + 1906765128U, // <6,u,u,7>: Cost 2 vzipr RHS, RHS + 497482085U, // <6,u,u,u>: Cost 1 vext2 RHS, LHS + 1638318080U, // <7,0,0,0>: Cost 2 vext3 RHS, <0,0,0,0> + 1638318090U, // <7,0,0,1>: Cost 2 vext3 RHS, <0,0,1,1> + 1638318100U, // <7,0,0,2>: Cost 2 vext3 RHS, <0,0,2,2> + 3646442178U, // <7,0,0,3>: Cost 4 vext1 <3,7,0,0>, <3,7,0,0> + 2712059941U, // <7,0,0,4>: Cost 3 vext3 RHS, <0,0,4,1> + 2651603364U, // <7,0,0,5>: Cost 3 vext2 <5,6,7,0>, <0,5,1,6> + 2590618445U, // <7,0,0,6>: Cost 3 vext1 <6,7,0,0>, <6,7,0,0> + 2651603570U, // <7,0,0,7>: Cost 3 vext2 <5,6,7,0>, <0,7,6,5> + 1638318153U, // <7,0,0,u>: Cost 2 vext3 RHS, <0,0,u,1> + 1516879974U, // <7,0,1,0>: Cost 2 vext1 <6,7,0,1>, LHS + 2693922911U, // <7,0,1,1>: Cost 3 vext3 <1,5,3,7>, <0,1,1,5> + 564576358U, // <7,0,1,2>: Cost 1 vext3 RHS, LHS + 2638996480U, // <7,0,1,3>: Cost 3 vext2 <3,5,7,0>, <1,3,5,7> + 1516883254U, // <7,0,1,4>: Cost 2 vext1 <6,7,0,1>, RHS + 2649613456U, // <7,0,1,5>: Cost 3 vext2 <5,3,7,0>, <1,5,3,7> + 1516884814U, // <7,0,1,6>: Cost 2 vext1 <6,7,0,1>, <6,7,0,1> + 2590626808U, // <7,0,1,7>: Cost 3 vext1 <6,7,0,1>, <7,0,1,0> + 564576412U, // <7,0,1,u>: Cost 1 vext3 RHS, LHS + 1638318244U, // <7,0,2,0>: Cost 2 vext3 RHS, <0,2,0,2> + 2692743344U, // <7,0,2,1>: Cost 3 vext3 <1,3,5,7>, <0,2,1,5> + 2712060084U, // <7,0,2,2>: Cost 3 vext3 RHS, <0,2,2,0> + 2712060094U, // <7,0,2,3>: Cost 3 vext3 RHS, <0,2,3,1> + 1638318284U, // <7,0,2,4>: Cost 2 vext3 RHS, <0,2,4,6> + 2712060118U, // <7,0,2,5>: Cost 3 vext3 RHS, <0,2,5,7> + 2651604922U, // <7,0,2,6>: Cost 3 vext2 <5,6,7,0>, <2,6,3,7> + 2686255336U, // <7,0,2,7>: Cost 3 vext3 <0,2,7,7>, <0,2,7,7> + 1638318316U, // <7,0,2,u>: Cost 2 vext3 RHS, <0,2,u,2> + 2651605142U, // <7,0,3,0>: Cost 3 vext2 <5,6,7,0>, <3,0,1,2> + 2712060156U, // <7,0,3,1>: Cost 3 vext3 RHS, <0,3,1,0> + 2712060166U, // <7,0,3,2>: Cost 3 vext3 RHS, <0,3,2,1> + 2651605404U, // <7,0,3,3>: Cost 3 vext2 <5,6,7,0>, <3,3,3,3> + 2651605506U, // <7,0,3,4>: Cost 3 vext2 <5,6,7,0>, <3,4,5,6> + 2638998111U, // <7,0,3,5>: Cost 3 vext2 <3,5,7,0>, <3,5,7,0> + 2639661744U, // <7,0,3,6>: Cost 3 vext2 <3,6,7,0>, <3,6,7,0> + 3712740068U, // <7,0,3,7>: Cost 4 vext2 <3,5,7,0>, <3,7,3,7> + 2640989010U, // <7,0,3,u>: Cost 3 vext2 <3,u,7,0>, <3,u,7,0> + 2712060232U, // <7,0,4,0>: Cost 3 vext3 RHS, <0,4,0,4> + 1638318418U, // <7,0,4,1>: Cost 2 vext3 RHS, <0,4,1,5> + 1638318428U, // <7,0,4,2>: Cost 2 vext3 RHS, <0,4,2,6> + 3646474950U, // <7,0,4,3>: Cost 4 vext1 <3,7,0,4>, <3,7,0,4> + 2712060270U, // <7,0,4,4>: Cost 3 vext3 RHS, <0,4,4,6> + 1577864502U, // <7,0,4,5>: Cost 2 vext2 <5,6,7,0>, RHS + 2651606388U, // <7,0,4,6>: Cost 3 vext2 <5,6,7,0>, <4,6,4,6> + 3787792776U, // <7,0,4,7>: Cost 4 vext3 RHS, <0,4,7,5> + 1638318481U, // <7,0,4,u>: Cost 2 vext3 RHS, <0,4,u,5> + 2590654566U, // <7,0,5,0>: Cost 3 vext1 <6,7,0,5>, LHS + 2651606736U, // <7,0,5,1>: Cost 3 vext2 <5,6,7,0>, <5,1,7,3> + 2712060334U, // <7,0,5,2>: Cost 3 vext3 RHS, <0,5,2,7> + 2649616239U, // <7,0,5,3>: Cost 3 vext2 <5,3,7,0>, <5,3,7,0> + 2590657846U, // <7,0,5,4>: Cost 3 vext1 <6,7,0,5>, RHS + 2651607044U, // <7,0,5,5>: Cost 3 vext2 <5,6,7,0>, <5,5,5,5> + 1577865314U, // <7,0,5,6>: Cost 2 vext2 <5,6,7,0>, <5,6,7,0> + 2651607208U, // <7,0,5,7>: Cost 3 vext2 <5,6,7,0>, <5,7,5,7> + 1579192580U, // <7,0,5,u>: Cost 2 vext2 <5,u,7,0>, <5,u,7,0> + 2688393709U, // <7,0,6,0>: Cost 3 vext3 <0,6,0,7>, <0,6,0,7> + 2712060406U, // <7,0,6,1>: Cost 3 vext3 RHS, <0,6,1,7> + 2688541183U, // <7,0,6,2>: Cost 3 vext3 <0,6,2,7>, <0,6,2,7> + 2655588936U, // <7,0,6,3>: Cost 3 vext2 <6,3,7,0>, <6,3,7,0> + 3762430481U, // <7,0,6,4>: Cost 4 vext3 <0,6,4,7>, <0,6,4,7> + 2651607730U, // <7,0,6,5>: Cost 3 vext2 <5,6,7,0>, <6,5,0,7> + 2651607864U, // <7,0,6,6>: Cost 3 vext2 <5,6,7,0>, <6,6,6,6> + 2651607886U, // <7,0,6,7>: Cost 3 vext2 <5,6,7,0>, <6,7,0,1> + 2688983605U, // <7,0,6,u>: Cost 3 vext3 <0,6,u,7>, <0,6,u,7> + 2651608058U, // <7,0,7,0>: Cost 3 vext2 <5,6,7,0>, <7,0,1,2> + 2932703334U, // <7,0,7,1>: Cost 3 vzipl <7,7,7,7>, LHS + 3066921062U, // <7,0,7,2>: Cost 3 vtrnl <7,7,7,7>, LHS + 3712742678U, // <7,0,7,3>: Cost 4 vext2 <3,5,7,0>, <7,3,5,7> + 2651608422U, // <7,0,7,4>: Cost 3 vext2 <5,6,7,0>, <7,4,5,6> + 2651608513U, // <7,0,7,5>: Cost 3 vext2 <5,6,7,0>, <7,5,6,7> + 2651608582U, // <7,0,7,6>: Cost 3 vext2 <5,6,7,0>, <7,6,5,4> + 2651608684U, // <7,0,7,7>: Cost 3 vext2 <5,6,7,0>, <7,7,7,7> + 2651608706U, // <7,0,7,u>: Cost 3 vext2 <5,6,7,0>, <7,u,1,2> + 1638318730U, // <7,0,u,0>: Cost 2 vext3 RHS, <0,u,0,2> + 1638318738U, // <7,0,u,1>: Cost 2 vext3 RHS, <0,u,1,1> + 564576925U, // <7,0,u,2>: Cost 1 vext3 RHS, LHS + 2572765898U, // <7,0,u,3>: Cost 3 vext1 <3,7,0,u>, <3,7,0,u> + 1638318770U, // <7,0,u,4>: Cost 2 vext3 RHS, <0,u,4,6> + 1577867418U, // <7,0,u,5>: Cost 2 vext2 <5,6,7,0>, RHS + 1516942165U, // <7,0,u,6>: Cost 2 vext1 <6,7,0,u>, <6,7,0,u> + 2651609344U, // <7,0,u,7>: Cost 3 vext2 <5,6,7,0>, + 564576979U, // <7,0,u,u>: Cost 1 vext3 RHS, LHS + 2712060634U, // <7,1,0,0>: Cost 3 vext3 RHS, <1,0,0,1> + 2639003750U, // <7,1,0,1>: Cost 3 vext2 <3,5,7,1>, LHS + 2793357414U, // <7,1,0,2>: Cost 3 vuzpl <7,0,1,2>, LHS + 2712060660U, // <7,1,0,3>: Cost 3 vext3 RHS, <1,0,3,0> + 2712060674U, // <7,1,0,4>: Cost 3 vext3 RHS, <1,0,4,5> + 2712060680U, // <7,1,0,5>: Cost 3 vext3 RHS, <1,0,5,2> + 3785802513U, // <7,1,0,6>: Cost 4 vext3 RHS, <1,0,6,2> + 2735948574U, // <7,1,0,7>: Cost 3 vext3 RHS, <1,0,7,6> + 2639004317U, // <7,1,0,u>: Cost 3 vext2 <3,5,7,1>, LHS + 2712060715U, // <7,1,1,0>: Cost 3 vext3 RHS, <1,1,0,1> + 1638318900U, // <7,1,1,1>: Cost 2 vext3 RHS, <1,1,1,1> + 3774300994U, // <7,1,1,2>: Cost 4 vext3 <2,6,3,7>, <1,1,2,6> + 1638318920U, // <7,1,1,3>: Cost 2 vext3 RHS, <1,1,3,3> + 2712060755U, // <7,1,1,4>: Cost 3 vext3 RHS, <1,1,4,5> + 2691416926U, // <7,1,1,5>: Cost 3 vext3 <1,1,5,7>, <1,1,5,7> + 2590700375U, // <7,1,1,6>: Cost 3 vext1 <6,7,1,1>, <6,7,1,1> + 3765306224U, // <7,1,1,7>: Cost 4 vext3 <1,1,7,7>, <1,1,7,7> + 1638318965U, // <7,1,1,u>: Cost 2 vext3 RHS, <1,1,u,3> + 2712060796U, // <7,1,2,0>: Cost 3 vext3 RHS, <1,2,0,1> + 2712060807U, // <7,1,2,1>: Cost 3 vext3 RHS, <1,2,1,3> + 3712747112U, // <7,1,2,2>: Cost 4 vext2 <3,5,7,1>, <2,2,2,2> + 1638318998U, // <7,1,2,3>: Cost 2 vext3 RHS, <1,2,3,0> + 2712060836U, // <7,1,2,4>: Cost 3 vext3 RHS, <1,2,4,5> + 2712060843U, // <7,1,2,5>: Cost 3 vext3 RHS, <1,2,5,3> + 2590708568U, // <7,1,2,6>: Cost 3 vext1 <6,7,1,2>, <6,7,1,2> + 2735948730U, // <7,1,2,7>: Cost 3 vext3 RHS, <1,2,7,0> + 1638319043U, // <7,1,2,u>: Cost 2 vext3 RHS, <1,2,u,0> + 2712060876U, // <7,1,3,0>: Cost 3 vext3 RHS, <1,3,0,0> + 1638319064U, // <7,1,3,1>: Cost 2 vext3 RHS, <1,3,1,3> + 2712060894U, // <7,1,3,2>: Cost 3 vext3 RHS, <1,3,2,0> + 2692596718U, // <7,1,3,3>: Cost 3 vext3 <1,3,3,7>, <1,3,3,7> + 2712060917U, // <7,1,3,4>: Cost 3 vext3 RHS, <1,3,4,5> + 1619002368U, // <7,1,3,5>: Cost 2 vext3 <1,3,5,7>, <1,3,5,7> + 2692817929U, // <7,1,3,6>: Cost 3 vext3 <1,3,6,7>, <1,3,6,7> + 2735948814U, // <7,1,3,7>: Cost 3 vext3 RHS, <1,3,7,3> + 1619223579U, // <7,1,3,u>: Cost 2 vext3 <1,3,u,7>, <1,3,u,7> + 2554888294U, // <7,1,4,0>: Cost 3 vext1 <0,7,1,4>, LHS + 2712060971U, // <7,1,4,1>: Cost 3 vext3 RHS, <1,4,1,5> + 2712060980U, // <7,1,4,2>: Cost 3 vext3 RHS, <1,4,2,5> + 2712060989U, // <7,1,4,3>: Cost 3 vext3 RHS, <1,4,3,5> + 2554891574U, // <7,1,4,4>: Cost 3 vext1 <0,7,1,4>, RHS + 2639007030U, // <7,1,4,5>: Cost 3 vext2 <3,5,7,1>, RHS + 2645642634U, // <7,1,4,6>: Cost 3 vext2 <4,6,7,1>, <4,6,7,1> + 2554893670U, // <7,1,4,7>: Cost 3 vext1 <0,7,1,4>, <7,4,5,6> + 2639007273U, // <7,1,4,u>: Cost 3 vext2 <3,5,7,1>, RHS + 2572812390U, // <7,1,5,0>: Cost 3 vext1 <3,7,1,5>, LHS + 2693776510U, // <7,1,5,1>: Cost 3 vext3 <1,5,1,7>, <1,5,1,7> + 3774301318U, // <7,1,5,2>: Cost 4 vext3 <2,6,3,7>, <1,5,2,6> + 1620182160U, // <7,1,5,3>: Cost 2 vext3 <1,5,3,7>, <1,5,3,7> + 2572815670U, // <7,1,5,4>: Cost 3 vext1 <3,7,1,5>, RHS + 3766486178U, // <7,1,5,5>: Cost 4 vext3 <1,3,5,7>, <1,5,5,7> + 2651615331U, // <7,1,5,6>: Cost 3 vext2 <5,6,7,1>, <5,6,7,1> + 2652278964U, // <7,1,5,7>: Cost 3 vext2 <5,7,7,1>, <5,7,7,1> + 1620550845U, // <7,1,5,u>: Cost 2 vext3 <1,5,u,7>, <1,5,u,7> + 2712061126U, // <7,1,6,0>: Cost 3 vext3 RHS, <1,6,0,7> + 2694440143U, // <7,1,6,1>: Cost 3 vext3 <1,6,1,7>, <1,6,1,7> + 2712061144U, // <7,1,6,2>: Cost 3 vext3 RHS, <1,6,2,7> + 2694587617U, // <7,1,6,3>: Cost 3 vext3 <1,6,3,7>, <1,6,3,7> + 2554907958U, // <7,1,6,4>: Cost 3 vext1 <0,7,1,6>, RHS + 2694735091U, // <7,1,6,5>: Cost 3 vext3 <1,6,5,7>, <1,6,5,7> + 3768550652U, // <7,1,6,6>: Cost 4 vext3 <1,6,6,7>, <1,6,6,7> + 2652279630U, // <7,1,6,7>: Cost 3 vext2 <5,7,7,1>, <6,7,0,1> + 2694956302U, // <7,1,6,u>: Cost 3 vext3 <1,6,u,7>, <1,6,u,7> + 2645644282U, // <7,1,7,0>: Cost 3 vext2 <4,6,7,1>, <7,0,1,2> + 2859062094U, // <7,1,7,1>: Cost 3 vuzpr <6,7,0,1>, <6,7,0,1> + 3779462437U, // <7,1,7,2>: Cost 4 vext3 <3,5,1,7>, <1,7,2,3> + 3121938534U, // <7,1,7,3>: Cost 3 vtrnr <5,7,5,7>, LHS + 2554916150U, // <7,1,7,4>: Cost 3 vext1 <0,7,1,7>, RHS + 3769140548U, // <7,1,7,5>: Cost 4 vext3 <1,7,5,7>, <1,7,5,7> + 3719386630U, // <7,1,7,6>: Cost 4 vext2 <4,6,7,1>, <7,6,5,4> + 2554918508U, // <7,1,7,7>: Cost 3 vext1 <0,7,1,7>, <7,7,7,7> + 3121938539U, // <7,1,7,u>: Cost 3 vtrnr <5,7,5,7>, LHS + 2572836966U, // <7,1,u,0>: Cost 3 vext1 <3,7,1,u>, LHS + 1638319469U, // <7,1,u,1>: Cost 2 vext3 RHS, <1,u,1,3> + 2712061299U, // <7,1,u,2>: Cost 3 vext3 RHS, <1,u,2,0> + 1622173059U, // <7,1,u,3>: Cost 2 vext3 <1,u,3,7>, <1,u,3,7> + 2572840246U, // <7,1,u,4>: Cost 3 vext1 <3,7,1,u>, RHS + 1622320533U, // <7,1,u,5>: Cost 2 vext3 <1,u,5,7>, <1,u,5,7> + 2696136094U, // <7,1,u,6>: Cost 3 vext3 <1,u,6,7>, <1,u,6,7> + 2859060777U, // <7,1,u,7>: Cost 3 vuzpr <6,7,0,1>, RHS + 1622541744U, // <7,1,u,u>: Cost 2 vext3 <1,u,u,7>, <1,u,u,7> + 2712061364U, // <7,2,0,0>: Cost 3 vext3 RHS, <2,0,0,2> + 2712061373U, // <7,2,0,1>: Cost 3 vext3 RHS, <2,0,1,2> + 2712061380U, // <7,2,0,2>: Cost 3 vext3 RHS, <2,0,2,0> + 2712061389U, // <7,2,0,3>: Cost 3 vext3 RHS, <2,0,3,0> + 2712061404U, // <7,2,0,4>: Cost 3 vext3 RHS, <2,0,4,6> + 2696725990U, // <7,2,0,5>: Cost 3 vext3 <2,0,5,7>, <2,0,5,7> + 2712061417U, // <7,2,0,6>: Cost 3 vext3 RHS, <2,0,6,1> + 3785803251U, // <7,2,0,7>: Cost 4 vext3 RHS, <2,0,7,2> + 2696947201U, // <7,2,0,u>: Cost 3 vext3 <2,0,u,7>, <2,0,u,7> + 2712061443U, // <7,2,1,0>: Cost 3 vext3 RHS, <2,1,0,0> + 3785803276U, // <7,2,1,1>: Cost 4 vext3 RHS, <2,1,1,0> + 3785803285U, // <7,2,1,2>: Cost 4 vext3 RHS, <2,1,2,0> + 2712061470U, // <7,2,1,3>: Cost 3 vext3 RHS, <2,1,3,0> + 2712061482U, // <7,2,1,4>: Cost 3 vext3 RHS, <2,1,4,3> + 3766486576U, // <7,2,1,5>: Cost 4 vext3 <1,3,5,7>, <2,1,5,0> + 2712061500U, // <7,2,1,6>: Cost 3 vext3 RHS, <2,1,6,3> + 2554942458U, // <7,2,1,7>: Cost 3 vext1 <0,7,2,1>, <7,0,1,2> + 2712061515U, // <7,2,1,u>: Cost 3 vext3 RHS, <2,1,u,0> + 2712061525U, // <7,2,2,0>: Cost 3 vext3 RHS, <2,2,0,1> + 2712061536U, // <7,2,2,1>: Cost 3 vext3 RHS, <2,2,1,3> + 1638319720U, // <7,2,2,2>: Cost 2 vext3 RHS, <2,2,2,2> + 1638319730U, // <7,2,2,3>: Cost 2 vext3 RHS, <2,2,3,3> + 2712061565U, // <7,2,2,4>: Cost 3 vext3 RHS, <2,2,4,5> + 2698053256U, // <7,2,2,5>: Cost 3 vext3 <2,2,5,7>, <2,2,5,7> + 2712061584U, // <7,2,2,6>: Cost 3 vext3 RHS, <2,2,6,6> + 3771942554U, // <7,2,2,7>: Cost 4 vext3 <2,2,7,7>, <2,2,7,7> + 1638319775U, // <7,2,2,u>: Cost 2 vext3 RHS, <2,2,u,3> + 1638319782U, // <7,2,3,0>: Cost 2 vext3 RHS, <2,3,0,1> + 2693924531U, // <7,2,3,1>: Cost 3 vext3 <1,5,3,7>, <2,3,1,5> + 2700560061U, // <7,2,3,2>: Cost 3 vext3 <2,6,3,7>, <2,3,2,6> + 2693924551U, // <7,2,3,3>: Cost 3 vext3 <1,5,3,7>, <2,3,3,7> + 1638319822U, // <7,2,3,4>: Cost 2 vext3 RHS, <2,3,4,5> + 2698716889U, // <7,2,3,5>: Cost 3 vext3 <2,3,5,7>, <2,3,5,7> + 2712061665U, // <7,2,3,6>: Cost 3 vext3 RHS, <2,3,6,6> + 2735949540U, // <7,2,3,7>: Cost 3 vext3 RHS, <2,3,7,0> + 1638319854U, // <7,2,3,u>: Cost 2 vext3 RHS, <2,3,u,1> + 2712061692U, // <7,2,4,0>: Cost 3 vext3 RHS, <2,4,0,6> + 2712061698U, // <7,2,4,1>: Cost 3 vext3 RHS, <2,4,1,3> + 2712061708U, // <7,2,4,2>: Cost 3 vext3 RHS, <2,4,2,4> + 2712061718U, // <7,2,4,3>: Cost 3 vext3 RHS, <2,4,3,5> + 2712061728U, // <7,2,4,4>: Cost 3 vext3 RHS, <2,4,4,6> + 2699380522U, // <7,2,4,5>: Cost 3 vext3 <2,4,5,7>, <2,4,5,7> + 2712061740U, // <7,2,4,6>: Cost 3 vext3 RHS, <2,4,6,0> + 3809691445U, // <7,2,4,7>: Cost 4 vext3 RHS, <2,4,7,0> + 2699601733U, // <7,2,4,u>: Cost 3 vext3 <2,4,u,7>, <2,4,u,7> + 2699675470U, // <7,2,5,0>: Cost 3 vext3 <2,5,0,7>, <2,5,0,7> + 3766486867U, // <7,2,5,1>: Cost 4 vext3 <1,3,5,7>, <2,5,1,3> + 2699822944U, // <7,2,5,2>: Cost 3 vext3 <2,5,2,7>, <2,5,2,7> + 2692745065U, // <7,2,5,3>: Cost 3 vext3 <1,3,5,7>, <2,5,3,7> + 2699970418U, // <7,2,5,4>: Cost 3 vext3 <2,5,4,7>, <2,5,4,7> + 3766486907U, // <7,2,5,5>: Cost 4 vext3 <1,3,5,7>, <2,5,5,7> + 2700117892U, // <7,2,5,6>: Cost 3 vext3 <2,5,6,7>, <2,5,6,7> + 3771795334U, // <7,2,5,7>: Cost 4 vext3 <2,2,5,7>, <2,5,7,0> + 2692745110U, // <7,2,5,u>: Cost 3 vext3 <1,3,5,7>, <2,5,u,7> + 2572894310U, // <7,2,6,0>: Cost 3 vext1 <3,7,2,6>, LHS + 2712061860U, // <7,2,6,1>: Cost 3 vext3 RHS, <2,6,1,3> + 2700486577U, // <7,2,6,2>: Cost 3 vext3 <2,6,2,7>, <2,6,2,7> + 1626818490U, // <7,2,6,3>: Cost 2 vext3 <2,6,3,7>, <2,6,3,7> + 2572897590U, // <7,2,6,4>: Cost 3 vext1 <3,7,2,6>, RHS + 2700707788U, // <7,2,6,5>: Cost 3 vext3 <2,6,5,7>, <2,6,5,7> + 2700781525U, // <7,2,6,6>: Cost 3 vext3 <2,6,6,7>, <2,6,6,7> + 2260588014U, // <7,2,6,7>: Cost 3 vrev <7,6,2,7> + 1627187175U, // <7,2,6,u>: Cost 2 vext3 <2,6,u,7>, <2,6,u,7> + 2735949802U, // <7,2,7,0>: Cost 3 vext3 RHS, <2,7,0,1> + 3785803768U, // <7,2,7,1>: Cost 4 vext3 RHS, <2,7,1,6> + 3773564928U, // <7,2,7,2>: Cost 4 vext3 <2,5,2,7>, <2,7,2,5> + 2986541158U, // <7,2,7,3>: Cost 3 vzipr <5,5,7,7>, LHS + 2554989878U, // <7,2,7,4>: Cost 3 vext1 <0,7,2,7>, RHS + 3775113245U, // <7,2,7,5>: Cost 4 vext3 <2,7,5,7>, <2,7,5,7> + 3785803810U, // <7,2,7,6>: Cost 4 vext3 RHS, <2,7,6,3> + 2554992236U, // <7,2,7,7>: Cost 3 vext1 <0,7,2,7>, <7,7,7,7> + 2986541163U, // <7,2,7,u>: Cost 3 vzipr <5,5,7,7>, LHS + 1638320187U, // <7,2,u,0>: Cost 2 vext3 RHS, <2,u,0,1> + 2693924936U, // <7,2,u,1>: Cost 3 vext3 <1,5,3,7>, <2,u,1,5> + 1638319720U, // <7,2,u,2>: Cost 2 vext3 RHS, <2,2,2,2> + 1628145756U, // <7,2,u,3>: Cost 2 vext3 <2,u,3,7>, <2,u,3,7> + 1638320227U, // <7,2,u,4>: Cost 2 vext3 RHS, <2,u,4,5> + 2702035054U, // <7,2,u,5>: Cost 3 vext3 <2,u,5,7>, <2,u,5,7> + 2702108791U, // <7,2,u,6>: Cost 3 vext3 <2,u,6,7>, <2,u,6,7> + 2261915280U, // <7,2,u,7>: Cost 3 vrev <7,u,2,7> + 1628514441U, // <7,2,u,u>: Cost 2 vext3 <2,u,u,7>, <2,u,u,7> + 2712062091U, // <7,3,0,0>: Cost 3 vext3 RHS, <3,0,0,0> + 1638320278U, // <7,3,0,1>: Cost 2 vext3 RHS, <3,0,1,2> + 2712062109U, // <7,3,0,2>: Cost 3 vext3 RHS, <3,0,2,0> + 2590836886U, // <7,3,0,3>: Cost 3 vext1 <6,7,3,0>, <3,0,1,2> + 2712062128U, // <7,3,0,4>: Cost 3 vext3 RHS, <3,0,4,1> + 2712062138U, // <7,3,0,5>: Cost 3 vext3 RHS, <3,0,5,2> + 2590839656U, // <7,3,0,6>: Cost 3 vext1 <6,7,3,0>, <6,7,3,0> + 3785803978U, // <7,3,0,7>: Cost 4 vext3 RHS, <3,0,7,0> + 1638320341U, // <7,3,0,u>: Cost 2 vext3 RHS, <3,0,u,2> + 3710108424U, // <7,3,1,0>: Cost 4 vext2 <3,1,7,3>, <1,0,5,2> + 2712062182U, // <7,3,1,1>: Cost 3 vext3 RHS, <3,1,1,1> + 2712062193U, // <7,3,1,2>: Cost 3 vext3 RHS, <3,1,2,3> + 2692745468U, // <7,3,1,3>: Cost 3 vext3 <1,3,5,7>, <3,1,3,5> + 2712062214U, // <7,3,1,4>: Cost 3 vext3 RHS, <3,1,4,6> + 2693925132U, // <7,3,1,5>: Cost 3 vext3 <1,5,3,7>, <3,1,5,3> + 3768183059U, // <7,3,1,6>: Cost 4 vext3 <1,6,1,7>, <3,1,6,1> + 2712062238U, // <7,3,1,7>: Cost 3 vext3 RHS, <3,1,7,3> + 2696063273U, // <7,3,1,u>: Cost 3 vext3 <1,u,5,7>, <3,1,u,5> + 2590851174U, // <7,3,2,0>: Cost 3 vext1 <6,7,3,2>, LHS + 1638320438U, // <7,3,2,1>: Cost 2 vext3 RHS, <3,2,1,0> + 2712062273U, // <7,3,2,2>: Cost 3 vext3 RHS, <3,2,2,2> + 2712062280U, // <7,3,2,3>: Cost 3 vext3 RHS, <3,2,3,0> + 2590854454U, // <7,3,2,4>: Cost 3 vext1 <6,7,3,2>, RHS + 3773565276U, // <7,3,2,5>: Cost 4 vext3 <2,5,2,7>, <3,2,5,2> + 2700560742U, // <7,3,2,6>: Cost 3 vext3 <2,6,3,7>, <3,2,6,3> + 2712062319U, // <7,3,2,7>: Cost 3 vext3 RHS, <3,2,7,3> + 1638320501U, // <7,3,2,u>: Cost 2 vext3 RHS, <3,2,u,0> + 2712062335U, // <7,3,3,0>: Cost 3 vext3 RHS, <3,3,0,1> + 2636368158U, // <7,3,3,1>: Cost 3 vext2 <3,1,7,3>, <3,1,7,3> + 2637031791U, // <7,3,3,2>: Cost 3 vext2 <3,2,7,3>, <3,2,7,3> + 1638320540U, // <7,3,3,3>: Cost 2 vext3 RHS, <3,3,3,3> + 2712062374U, // <7,3,3,4>: Cost 3 vext3 RHS, <3,3,4,4> + 2704689586U, // <7,3,3,5>: Cost 3 vext3 <3,3,5,7>, <3,3,5,7> + 2590864235U, // <7,3,3,6>: Cost 3 vext1 <6,7,3,3>, <6,7,3,3> + 2704837060U, // <7,3,3,7>: Cost 3 vext3 <3,3,7,7>, <3,3,7,7> + 1638320540U, // <7,3,3,u>: Cost 2 vext3 RHS, <3,3,3,3> + 2712062416U, // <7,3,4,0>: Cost 3 vext3 RHS, <3,4,0,1> + 2712062426U, // <7,3,4,1>: Cost 3 vext3 RHS, <3,4,1,2> + 2712062438U, // <7,3,4,2>: Cost 3 vext3 RHS, <3,4,2,5> + 2712062447U, // <7,3,4,3>: Cost 3 vext3 RHS, <3,4,3,5> + 2712062456U, // <7,3,4,4>: Cost 3 vext3 RHS, <3,4,4,5> + 1638320642U, // <7,3,4,5>: Cost 2 vext3 RHS, <3,4,5,6> + 2648313204U, // <7,3,4,6>: Cost 3 vext2 <5,1,7,3>, <4,6,4,6> + 3785804302U, // <7,3,4,7>: Cost 4 vext3 RHS, <3,4,7,0> + 1638320669U, // <7,3,4,u>: Cost 2 vext3 RHS, <3,4,u,6> + 2602819686U, // <7,3,5,0>: Cost 3 vext1 , LHS + 1574571728U, // <7,3,5,1>: Cost 2 vext2 <5,1,7,3>, <5,1,7,3> + 2648977185U, // <7,3,5,2>: Cost 3 vext2 <5,2,7,3>, <5,2,7,3> + 2705869378U, // <7,3,5,3>: Cost 3 vext3 <3,5,3,7>, <3,5,3,7> + 2712062538U, // <7,3,5,4>: Cost 3 vext3 RHS, <3,5,4,6> + 2706016852U, // <7,3,5,5>: Cost 3 vext3 <3,5,5,7>, <3,5,5,7> + 2648313954U, // <7,3,5,6>: Cost 3 vext2 <5,1,7,3>, <5,6,7,0> + 2692745823U, // <7,3,5,7>: Cost 3 vext3 <1,3,5,7>, <3,5,7,0> + 1579217159U, // <7,3,5,u>: Cost 2 vext2 <5,u,7,3>, <5,u,7,3> + 2706311800U, // <7,3,6,0>: Cost 3 vext3 <3,6,0,7>, <3,6,0,7> + 2654286249U, // <7,3,6,1>: Cost 3 vext2 <6,1,7,3>, <6,1,7,3> + 1581208058U, // <7,3,6,2>: Cost 2 vext2 <6,2,7,3>, <6,2,7,3> + 2706533011U, // <7,3,6,3>: Cost 3 vext3 <3,6,3,7>, <3,6,3,7> + 2706606748U, // <7,3,6,4>: Cost 3 vext3 <3,6,4,7>, <3,6,4,7> + 3780422309U, // <7,3,6,5>: Cost 4 vext3 <3,6,5,7>, <3,6,5,7> + 2712062637U, // <7,3,6,6>: Cost 3 vext3 RHS, <3,6,6,6> + 2706827959U, // <7,3,6,7>: Cost 3 vext3 <3,6,7,7>, <3,6,7,7> + 1585189856U, // <7,3,6,u>: Cost 2 vext2 <6,u,7,3>, <6,u,7,3> + 2693925571U, // <7,3,7,0>: Cost 3 vext3 <1,5,3,7>, <3,7,0,1> + 2693925584U, // <7,3,7,1>: Cost 3 vext3 <1,5,3,7>, <3,7,1,5> + 2700561114U, // <7,3,7,2>: Cost 3 vext3 <2,6,3,7>, <3,7,2,6> + 2572978916U, // <7,3,7,3>: Cost 3 vext1 <3,7,3,7>, <3,7,3,7> + 2693925611U, // <7,3,7,4>: Cost 3 vext3 <1,5,3,7>, <3,7,4,5> + 2707344118U, // <7,3,7,5>: Cost 3 vext3 <3,7,5,7>, <3,7,5,7> + 2648315398U, // <7,3,7,6>: Cost 3 vext2 <5,1,7,3>, <7,6,5,4> + 2648315500U, // <7,3,7,7>: Cost 3 vext2 <5,1,7,3>, <7,7,7,7> + 2693925643U, // <7,3,7,u>: Cost 3 vext3 <1,5,3,7>, <3,7,u,1> + 2707639066U, // <7,3,u,0>: Cost 3 vext3 <3,u,0,7>, <3,u,0,7> + 1638320924U, // <7,3,u,1>: Cost 2 vext3 RHS, <3,u,1,0> + 1593153452U, // <7,3,u,2>: Cost 2 vext2 , + 1638320540U, // <7,3,u,3>: Cost 2 vext3 RHS, <3,3,3,3> + 2707934014U, // <7,3,u,4>: Cost 3 vext3 <3,u,4,7>, <3,u,4,7> + 1638320966U, // <7,3,u,5>: Cost 2 vext3 RHS, <3,u,5,6> + 2712062796U, // <7,3,u,6>: Cost 3 vext3 RHS, <3,u,6,3> + 2692967250U, // <7,3,u,7>: Cost 3 vext3 <1,3,u,7>, <3,u,7,0> + 1638320987U, // <7,3,u,u>: Cost 2 vext3 RHS, <3,u,u,0> + 2651635712U, // <7,4,0,0>: Cost 3 vext2 <5,6,7,4>, <0,0,0,0> + 1577893990U, // <7,4,0,1>: Cost 2 vext2 <5,6,7,4>, LHS + 2651635876U, // <7,4,0,2>: Cost 3 vext2 <5,6,7,4>, <0,2,0,2> + 3785804672U, // <7,4,0,3>: Cost 4 vext3 RHS, <4,0,3,1> + 2651636050U, // <7,4,0,4>: Cost 3 vext2 <5,6,7,4>, <0,4,1,5> + 1638468498U, // <7,4,0,5>: Cost 2 vext3 RHS, <4,0,5,1> + 1638468508U, // <7,4,0,6>: Cost 2 vext3 RHS, <4,0,6,2> + 3787795364U, // <7,4,0,7>: Cost 4 vext3 RHS, <4,0,7,1> + 1640459181U, // <7,4,0,u>: Cost 2 vext3 RHS, <4,0,u,1> + 3712770824U, // <7,4,1,0>: Cost 4 vext2 <3,5,7,4>, <1,0,5,2> + 2651636532U, // <7,4,1,1>: Cost 3 vext2 <5,6,7,4>, <1,1,1,1> + 2712062922U, // <7,4,1,2>: Cost 3 vext3 RHS, <4,1,2,3> + 2639029248U, // <7,4,1,3>: Cost 3 vext2 <3,5,7,4>, <1,3,5,7> + 2712062940U, // <7,4,1,4>: Cost 3 vext3 RHS, <4,1,4,3> + 2712062946U, // <7,4,1,5>: Cost 3 vext3 RHS, <4,1,5,0> + 2712062958U, // <7,4,1,6>: Cost 3 vext3 RHS, <4,1,6,3> + 3785804791U, // <7,4,1,7>: Cost 4 vext3 RHS, <4,1,7,3> + 2712062973U, // <7,4,1,u>: Cost 3 vext3 RHS, <4,1,u,0> + 3785804807U, // <7,4,2,0>: Cost 4 vext3 RHS, <4,2,0,1> + 3785804818U, // <7,4,2,1>: Cost 4 vext3 RHS, <4,2,1,3> + 2651637352U, // <7,4,2,2>: Cost 3 vext2 <5,6,7,4>, <2,2,2,2> + 2651637414U, // <7,4,2,3>: Cost 3 vext2 <5,6,7,4>, <2,3,0,1> + 3716753194U, // <7,4,2,4>: Cost 4 vext2 <4,2,7,4>, <2,4,5,7> + 2712063030U, // <7,4,2,5>: Cost 3 vext3 RHS, <4,2,5,3> + 2712063036U, // <7,4,2,6>: Cost 3 vext3 RHS, <4,2,6,0> + 3785804872U, // <7,4,2,7>: Cost 4 vext3 RHS, <4,2,7,3> + 2712063054U, // <7,4,2,u>: Cost 3 vext3 RHS, <4,2,u,0> + 2651637910U, // <7,4,3,0>: Cost 3 vext2 <5,6,7,4>, <3,0,1,2> + 3712772348U, // <7,4,3,1>: Cost 4 vext2 <3,5,7,4>, <3,1,3,5> + 2712063082U, // <7,4,3,2>: Cost 3 vext3 RHS, <4,3,2,1> + 2651638172U, // <7,4,3,3>: Cost 3 vext2 <5,6,7,4>, <3,3,3,3> + 2651638274U, // <7,4,3,4>: Cost 3 vext2 <5,6,7,4>, <3,4,5,6> + 2639030883U, // <7,4,3,5>: Cost 3 vext2 <3,5,7,4>, <3,5,7,4> + 2712210578U, // <7,4,3,6>: Cost 3 vext3 RHS, <4,3,6,5> + 3712772836U, // <7,4,3,7>: Cost 4 vext2 <3,5,7,4>, <3,7,3,7> + 2641021782U, // <7,4,3,u>: Cost 3 vext2 <3,u,7,4>, <3,u,7,4> + 2714053802U, // <7,4,4,0>: Cost 3 vext3 RHS, <4,4,0,2> + 3785804978U, // <7,4,4,1>: Cost 4 vext3 RHS, <4,4,1,1> + 3716754505U, // <7,4,4,2>: Cost 4 vext2 <4,2,7,4>, <4,2,7,4> + 3785804997U, // <7,4,4,3>: Cost 4 vext3 RHS, <4,4,3,2> + 1638321360U, // <7,4,4,4>: Cost 2 vext3 RHS, <4,4,4,4> + 1638468826U, // <7,4,4,5>: Cost 2 vext3 RHS, <4,4,5,5> + 1638468836U, // <7,4,4,6>: Cost 2 vext3 RHS, <4,4,6,6> + 2651639254U, // <7,4,4,7>: Cost 3 vext2 <5,6,7,4>, <4,7,6,5> + 1640459509U, // <7,4,4,u>: Cost 2 vext3 RHS, <4,4,u,5> + 1517207654U, // <7,4,5,0>: Cost 2 vext1 <6,7,4,5>, LHS + 2573034640U, // <7,4,5,1>: Cost 3 vext1 <3,7,4,5>, <1,5,3,7> + 2712063246U, // <7,4,5,2>: Cost 3 vext3 RHS, <4,5,2,3> + 2573036267U, // <7,4,5,3>: Cost 3 vext1 <3,7,4,5>, <3,7,4,5> + 1517210934U, // <7,4,5,4>: Cost 2 vext1 <6,7,4,5>, RHS + 2711989549U, // <7,4,5,5>: Cost 3 vext3 <4,5,5,7>, <4,5,5,7> + 564579638U, // <7,4,5,6>: Cost 1 vext3 RHS, RHS + 2651639976U, // <7,4,5,7>: Cost 3 vext2 <5,6,7,4>, <5,7,5,7> + 564579656U, // <7,4,5,u>: Cost 1 vext3 RHS, RHS + 2712063307U, // <7,4,6,0>: Cost 3 vext3 RHS, <4,6,0,1> + 3767668056U, // <7,4,6,1>: Cost 4 vext3 <1,5,3,7>, <4,6,1,5> + 2712210780U, // <7,4,6,2>: Cost 3 vext3 RHS, <4,6,2,0> + 2655621708U, // <7,4,6,3>: Cost 3 vext2 <6,3,7,4>, <6,3,7,4> + 1638468980U, // <7,4,6,4>: Cost 2 vext3 RHS, <4,6,4,6> + 2712063358U, // <7,4,6,5>: Cost 3 vext3 RHS, <4,6,5,7> + 2712063367U, // <7,4,6,6>: Cost 3 vext3 RHS, <4,6,6,7> + 2712210826U, // <7,4,6,7>: Cost 3 vext3 RHS, <4,6,7,1> + 1638469012U, // <7,4,6,u>: Cost 2 vext3 RHS, <4,6,u,2> + 2651640826U, // <7,4,7,0>: Cost 3 vext2 <5,6,7,4>, <7,0,1,2> + 3773713830U, // <7,4,7,1>: Cost 4 vext3 <2,5,4,7>, <4,7,1,2> + 3773713842U, // <7,4,7,2>: Cost 4 vext3 <2,5,4,7>, <4,7,2,5> + 3780349372U, // <7,4,7,3>: Cost 4 vext3 <3,6,4,7>, <4,7,3,6> + 2651641140U, // <7,4,7,4>: Cost 3 vext2 <5,6,7,4>, <7,4,0,1> + 2712210888U, // <7,4,7,5>: Cost 3 vext3 RHS, <4,7,5,0> + 2712210898U, // <7,4,7,6>: Cost 3 vext3 RHS, <4,7,6,1> + 2651641452U, // <7,4,7,7>: Cost 3 vext2 <5,6,7,4>, <7,7,7,7> + 2713538026U, // <7,4,7,u>: Cost 3 vext3 <4,7,u,7>, <4,7,u,7> + 1517232230U, // <7,4,u,0>: Cost 2 vext1 <6,7,4,u>, LHS + 1577899822U, // <7,4,u,1>: Cost 2 vext2 <5,6,7,4>, LHS + 2712063487U, // <7,4,u,2>: Cost 3 vext3 RHS, <4,u,2,1> + 2573060846U, // <7,4,u,3>: Cost 3 vext1 <3,7,4,u>, <3,7,4,u> + 1640312342U, // <7,4,u,4>: Cost 2 vext3 RHS, <4,u,4,6> + 1638469146U, // <7,4,u,5>: Cost 2 vext3 RHS, <4,u,5,1> + 564579881U, // <7,4,u,6>: Cost 1 vext3 RHS, RHS + 2714054192U, // <7,4,u,7>: Cost 3 vext3 RHS, <4,u,7,5> + 564579899U, // <7,4,u,u>: Cost 1 vext3 RHS, RHS + 2579038310U, // <7,5,0,0>: Cost 3 vext1 <4,7,5,0>, LHS + 2712063560U, // <7,5,0,1>: Cost 3 vext3 RHS, <5,0,1,2> + 2796339302U, // <7,5,0,2>: Cost 3 vuzpl <7,4,5,6>, LHS + 3646810719U, // <7,5,0,3>: Cost 4 vext1 <3,7,5,0>, <3,5,7,0> + 2712063586U, // <7,5,0,4>: Cost 3 vext3 RHS, <5,0,4,1> + 2735951467U, // <7,5,0,5>: Cost 3 vext3 RHS, <5,0,5,1> + 2735951476U, // <7,5,0,6>: Cost 3 vext3 RHS, <5,0,6,1> + 2579043322U, // <7,5,0,7>: Cost 3 vext1 <4,7,5,0>, <7,0,1,2> + 2712063622U, // <7,5,0,u>: Cost 3 vext3 RHS, <5,0,u,1> + 2714054287U, // <7,5,1,0>: Cost 3 vext3 RHS, <5,1,0,1> + 3295396702U, // <7,5,1,1>: Cost 4 vrev <1,1,5,7> + 3766488736U, // <7,5,1,2>: Cost 4 vext3 <1,3,5,7>, <5,1,2,0> + 2859384934U, // <7,5,1,3>: Cost 3 vuzpr <6,7,4,5>, LHS + 2712063666U, // <7,5,1,4>: Cost 3 vext3 RHS, <5,1,4,0> + 2590994128U, // <7,5,1,5>: Cost 3 vext1 <6,7,5,1>, <5,1,7,3> + 2590995323U, // <7,5,1,6>: Cost 3 vext1 <6,7,5,1>, <6,7,5,1> + 1638469328U, // <7,5,1,7>: Cost 2 vext3 RHS, <5,1,7,3> + 1638469337U, // <7,5,1,u>: Cost 2 vext3 RHS, <5,1,u,3> + 3785805536U, // <7,5,2,0>: Cost 4 vext3 RHS, <5,2,0,1> + 3766488808U, // <7,5,2,1>: Cost 4 vext3 <1,3,5,7>, <5,2,1,0> + 3302033032U, // <7,5,2,2>: Cost 4 vrev <2,2,5,7> + 2712063742U, // <7,5,2,3>: Cost 3 vext3 RHS, <5,2,3,4> + 3785805571U, // <7,5,2,4>: Cost 4 vext3 RHS, <5,2,4,0> + 2714054415U, // <7,5,2,5>: Cost 3 vext3 RHS, <5,2,5,3> + 3774304024U, // <7,5,2,6>: Cost 4 vext3 <2,6,3,7>, <5,2,6,3> + 2712063777U, // <7,5,2,7>: Cost 3 vext3 RHS, <5,2,7,3> + 2712063787U, // <7,5,2,u>: Cost 3 vext3 RHS, <5,2,u,4> + 3634888806U, // <7,5,3,0>: Cost 4 vext1 <1,7,5,3>, LHS + 2222982144U, // <7,5,3,1>: Cost 3 vrev <1,3,5,7> + 2228954841U, // <7,5,3,2>: Cost 3 vrev <2,3,5,7> + 3308669362U, // <7,5,3,3>: Cost 4 vrev <3,3,5,7> + 3634892086U, // <7,5,3,4>: Cost 4 vext1 <1,7,5,3>, RHS + 2639039076U, // <7,5,3,5>: Cost 3 vext2 <3,5,7,5>, <3,5,7,5> + 3713444533U, // <7,5,3,6>: Cost 4 vext2 <3,6,7,5>, <3,6,7,5> + 2693926767U, // <7,5,3,7>: Cost 3 vext3 <1,5,3,7>, <5,3,7,0> + 2712063864U, // <7,5,3,u>: Cost 3 vext3 RHS, <5,3,u,0> + 2579071078U, // <7,5,4,0>: Cost 3 vext1 <4,7,5,4>, LHS + 2735951762U, // <7,5,4,1>: Cost 3 vext3 RHS, <5,4,1,u> + 3303360298U, // <7,5,4,2>: Cost 4 vrev <2,4,5,7> + 2712063902U, // <7,5,4,3>: Cost 3 vext3 RHS, <5,4,3,2> + 2579074358U, // <7,5,4,4>: Cost 3 vext1 <4,7,5,4>, RHS + 2712063924U, // <7,5,4,5>: Cost 3 vext3 RHS, <5,4,5,6> + 2645675406U, // <7,5,4,6>: Cost 3 vext2 <4,6,7,5>, <4,6,7,5> + 2712211397U, // <7,5,4,7>: Cost 3 vext3 RHS, <5,4,7,5> + 2712063947U, // <7,5,4,u>: Cost 3 vext3 RHS, <5,4,u,2> + 2714054611U, // <7,5,5,0>: Cost 3 vext3 RHS, <5,5,0,1> + 2652974800U, // <7,5,5,1>: Cost 3 vext2 <5,u,7,5>, <5,1,7,3> + 3785805799U, // <7,5,5,2>: Cost 4 vext3 RHS, <5,5,2,3> + 2236254804U, // <7,5,5,3>: Cost 3 vrev <3,5,5,7> + 2712211450U, // <7,5,5,4>: Cost 3 vext3 RHS, <5,5,4,4> + 1638322180U, // <7,5,5,5>: Cost 2 vext3 RHS, <5,5,5,5> + 2712064014U, // <7,5,5,6>: Cost 3 vext3 RHS, <5,5,6,6> + 1638469656U, // <7,5,5,7>: Cost 2 vext3 RHS, <5,5,7,7> + 1638469665U, // <7,5,5,u>: Cost 2 vext3 RHS, <5,5,u,7> + 2712064036U, // <7,5,6,0>: Cost 3 vext3 RHS, <5,6,0,1> + 2714054707U, // <7,5,6,1>: Cost 3 vext3 RHS, <5,6,1,7> + 3304687564U, // <7,5,6,2>: Cost 4 vrev <2,6,5,7> + 2712064066U, // <7,5,6,3>: Cost 3 vext3 RHS, <5,6,3,4> + 2712064076U, // <7,5,6,4>: Cost 3 vext3 RHS, <5,6,4,5> + 2714054743U, // <7,5,6,5>: Cost 3 vext3 RHS, <5,6,5,7> + 2712064096U, // <7,5,6,6>: Cost 3 vext3 RHS, <5,6,6,7> + 1638322274U, // <7,5,6,7>: Cost 2 vext3 RHS, <5,6,7,0> + 1638469739U, // <7,5,6,u>: Cost 2 vext3 RHS, <5,6,u,0> + 1511325798U, // <7,5,7,0>: Cost 2 vext1 <5,7,5,7>, LHS + 2692747392U, // <7,5,7,1>: Cost 3 vext3 <1,3,5,7>, <5,7,1,3> + 2585069160U, // <7,5,7,2>: Cost 3 vext1 <5,7,5,7>, <2,2,2,2> + 2573126390U, // <7,5,7,3>: Cost 3 vext1 <3,7,5,7>, <3,7,5,7> + 1511329078U, // <7,5,7,4>: Cost 2 vext1 <5,7,5,7>, RHS + 1638469800U, // <7,5,7,5>: Cost 2 vext3 RHS, <5,7,5,7> + 2712211626U, // <7,5,7,6>: Cost 3 vext3 RHS, <5,7,6,0> + 2712211636U, // <7,5,7,7>: Cost 3 vext3 RHS, <5,7,7,1> + 1638469823U, // <7,5,7,u>: Cost 2 vext3 RHS, <5,7,u,3> + 1511333990U, // <7,5,u,0>: Cost 2 vext1 <5,7,5,u>, LHS + 2226300309U, // <7,5,u,1>: Cost 3 vrev <1,u,5,7> + 2585077352U, // <7,5,u,2>: Cost 3 vext1 <5,7,5,u>, <2,2,2,2> + 2573134583U, // <7,5,u,3>: Cost 3 vext1 <3,7,5,u>, <3,7,5,u> + 1511337270U, // <7,5,u,4>: Cost 2 vext1 <5,7,5,u>, RHS + 1638469881U, // <7,5,u,5>: Cost 2 vext3 RHS, <5,u,5,7> + 2712064258U, // <7,5,u,6>: Cost 3 vext3 RHS, <5,u,6,7> + 1638469892U, // <7,5,u,7>: Cost 2 vext3 RHS, <5,u,7,0> + 1638469904U, // <7,5,u,u>: Cost 2 vext3 RHS, <5,u,u,3> + 2585084006U, // <7,6,0,0>: Cost 3 vext1 <5,7,6,0>, LHS + 2712064289U, // <7,6,0,1>: Cost 3 vext3 RHS, <6,0,1,2> + 2712064300U, // <7,6,0,2>: Cost 3 vext3 RHS, <6,0,2,4> + 3785806130U, // <7,6,0,3>: Cost 4 vext3 RHS, <6,0,3,1> + 2712064316U, // <7,6,0,4>: Cost 3 vext3 RHS, <6,0,4,2> + 2585088098U, // <7,6,0,5>: Cost 3 vext1 <5,7,6,0>, <5,6,7,0> + 2735952204U, // <7,6,0,6>: Cost 3 vext3 RHS, <6,0,6,0> + 2712211799U, // <7,6,0,7>: Cost 3 vext3 RHS, <6,0,7,2> + 2712064352U, // <7,6,0,u>: Cost 3 vext3 RHS, <6,0,u,2> + 2579120230U, // <7,6,1,0>: Cost 3 vext1 <4,7,6,1>, LHS + 3785806193U, // <7,6,1,1>: Cost 4 vext3 RHS, <6,1,1,1> + 3774304633U, // <7,6,1,2>: Cost 4 vext3 <2,6,3,7>, <6,1,2,0> + 3766489479U, // <7,6,1,3>: Cost 4 vext3 <1,3,5,7>, <6,1,3,5> + 2579123510U, // <7,6,1,4>: Cost 3 vext1 <4,7,6,1>, RHS + 3767669143U, // <7,6,1,5>: Cost 4 vext3 <1,5,3,7>, <6,1,5,3> + 2714055072U, // <7,6,1,6>: Cost 3 vext3 RHS, <6,1,6,3> + 2712064425U, // <7,6,1,7>: Cost 3 vext3 RHS, <6,1,7,3> + 2579126062U, // <7,6,1,u>: Cost 3 vext1 <4,7,6,1>, LHS + 2714055097U, // <7,6,2,0>: Cost 3 vext3 RHS, <6,2,0,1> + 2714055108U, // <7,6,2,1>: Cost 3 vext3 RHS, <6,2,1,3> + 3785806284U, // <7,6,2,2>: Cost 4 vext3 RHS, <6,2,2,2> + 2631747306U, // <7,6,2,3>: Cost 3 vext2 <2,3,7,6>, <2,3,7,6> + 2712064476U, // <7,6,2,4>: Cost 3 vext3 RHS, <6,2,4,0> + 2714055148U, // <7,6,2,5>: Cost 3 vext3 RHS, <6,2,5,7> + 2591077253U, // <7,6,2,6>: Cost 3 vext1 <6,7,6,2>, <6,7,6,2> + 1638470138U, // <7,6,2,7>: Cost 2 vext3 RHS, <6,2,7,3> + 1638470147U, // <7,6,2,u>: Cost 2 vext3 RHS, <6,2,u,3> + 3640934502U, // <7,6,3,0>: Cost 4 vext1 <2,7,6,3>, LHS + 3296797705U, // <7,6,3,1>: Cost 4 vrev <1,3,6,7> + 2229028578U, // <7,6,3,2>: Cost 3 vrev <2,3,6,7> + 3646909179U, // <7,6,3,3>: Cost 4 vext1 <3,7,6,3>, <3,7,6,3> + 2712064562U, // <7,6,3,4>: Cost 3 vext3 RHS, <6,3,4,5> + 3785806392U, // <7,6,3,5>: Cost 4 vext3 RHS, <6,3,5,2> + 3713452726U, // <7,6,3,6>: Cost 4 vext2 <3,6,7,6>, <3,6,7,6> + 2700563016U, // <7,6,3,7>: Cost 3 vext3 <2,6,3,7>, <6,3,7,0> + 2712064593U, // <7,6,3,u>: Cost 3 vext3 RHS, <6,3,u,0> + 2585116774U, // <7,6,4,0>: Cost 3 vext1 <5,7,6,4>, LHS + 2735952486U, // <7,6,4,1>: Cost 3 vext3 RHS, <6,4,1,3> + 2712064620U, // <7,6,4,2>: Cost 3 vext3 RHS, <6,4,2,0> + 3785806454U, // <7,6,4,3>: Cost 4 vext3 RHS, <6,4,3,1> + 2712212100U, // <7,6,4,4>: Cost 3 vext3 RHS, <6,4,4,6> + 2712064653U, // <7,6,4,5>: Cost 3 vext3 RHS, <6,4,5,6> + 2714055312U, // <7,6,4,6>: Cost 3 vext3 RHS, <6,4,6,0> + 2712212126U, // <7,6,4,7>: Cost 3 vext3 RHS, <6,4,7,5> + 2712064674U, // <7,6,4,u>: Cost 3 vext3 RHS, <6,4,u,0> + 2579152998U, // <7,6,5,0>: Cost 3 vext1 <4,7,6,5>, LHS + 3785806519U, // <7,6,5,1>: Cost 4 vext3 RHS, <6,5,1,3> + 2714055364U, // <7,6,5,2>: Cost 3 vext3 RHS, <6,5,2,7> + 2236328541U, // <7,6,5,3>: Cost 3 vrev <3,5,6,7> + 94817590U, // <7,6,5,4>: Cost 1 vrev RHS + 2555269218U, // <7,6,5,5>: Cost 3 vext1 <0,7,6,5>, <5,6,7,0> + 2651656296U, // <7,6,5,6>: Cost 3 vext2 <5,6,7,6>, <5,6,7,6> + 2712064753U, // <7,6,5,7>: Cost 3 vext3 RHS, <6,5,7,7> + 118708378U, // <7,6,5,u>: Cost 1 vrev RHS + 2714055421U, // <7,6,6,0>: Cost 3 vext3 RHS, <6,6,0,1> + 2714055432U, // <7,6,6,1>: Cost 3 vext3 RHS, <6,6,1,3> + 2652983802U, // <7,6,6,2>: Cost 3 vext2 <5,u,7,6>, <6,2,7,3> + 2236992174U, // <7,6,6,3>: Cost 3 vrev <3,6,6,7> + 2712212260U, // <7,6,6,4>: Cost 3 vext3 RHS, <6,6,4,4> + 2714055472U, // <7,6,6,5>: Cost 3 vext3 RHS, <6,6,5,7> + 1638323000U, // <7,6,6,6>: Cost 2 vext3 RHS, <6,6,6,6> + 1638470466U, // <7,6,6,7>: Cost 2 vext3 RHS, <6,6,7,7> + 1638470475U, // <7,6,6,u>: Cost 2 vext3 RHS, <6,6,u,7> + 1638323022U, // <7,6,7,0>: Cost 2 vext3 RHS, <6,7,0,1> + 2712064855U, // <7,6,7,1>: Cost 3 vext3 RHS, <6,7,1,1> + 2712064865U, // <7,6,7,2>: Cost 3 vext3 RHS, <6,7,2,2> + 2712064872U, // <7,6,7,3>: Cost 3 vext3 RHS, <6,7,3,0> + 1638323062U, // <7,6,7,4>: Cost 2 vext3 RHS, <6,7,4,5> + 2712064895U, // <7,6,7,5>: Cost 3 vext3 RHS, <6,7,5,5> + 2712064905U, // <7,6,7,6>: Cost 3 vext3 RHS, <6,7,6,6> + 2712064914U, // <7,6,7,7>: Cost 3 vext3 RHS, <6,7,7,6> + 1638323094U, // <7,6,7,u>: Cost 2 vext3 RHS, <6,7,u,1> + 1638470559U, // <7,6,u,0>: Cost 2 vext3 RHS, <6,u,0,1> + 2712064937U, // <7,6,u,1>: Cost 3 vext3 RHS, <6,u,1,2> + 2712064944U, // <7,6,u,2>: Cost 3 vext3 RHS, <6,u,2,0> + 2712212409U, // <7,6,u,3>: Cost 3 vext3 RHS, <6,u,3,0> + 96808489U, // <7,6,u,4>: Cost 1 vrev RHS + 2712064977U, // <7,6,u,5>: Cost 3 vext3 RHS, <6,u,5,6> + 1638323000U, // <7,6,u,6>: Cost 2 vext3 RHS, <6,6,6,6> + 1638470624U, // <7,6,u,7>: Cost 2 vext3 RHS, <6,u,7,3> + 120699277U, // <7,6,u,u>: Cost 1 vrev RHS + 2712065007U, // <7,7,0,0>: Cost 3 vext3 RHS, <7,0,0,0> + 1638323194U, // <7,7,0,1>: Cost 2 vext3 RHS, <7,0,1,2> + 2712065025U, // <7,7,0,2>: Cost 3 vext3 RHS, <7,0,2,0> + 3646958337U, // <7,7,0,3>: Cost 4 vext1 <3,7,7,0>, <3,7,7,0> + 2712065044U, // <7,7,0,4>: Cost 3 vext3 RHS, <7,0,4,1> + 2585161907U, // <7,7,0,5>: Cost 3 vext1 <5,7,7,0>, <5,7,7,0> + 2591134604U, // <7,7,0,6>: Cost 3 vext1 <6,7,7,0>, <6,7,7,0> + 2591134714U, // <7,7,0,7>: Cost 3 vext1 <6,7,7,0>, <7,0,1,2> + 1638323257U, // <7,7,0,u>: Cost 2 vext3 RHS, <7,0,u,2> + 2585165926U, // <7,7,1,0>: Cost 3 vext1 <5,7,7,1>, LHS + 2712065098U, // <7,7,1,1>: Cost 3 vext3 RHS, <7,1,1,1> + 2712065109U, // <7,7,1,2>: Cost 3 vext3 RHS, <7,1,2,3> + 2692748384U, // <7,7,1,3>: Cost 3 vext3 <1,3,5,7>, <7,1,3,5> + 2585169206U, // <7,7,1,4>: Cost 3 vext1 <5,7,7,1>, RHS + 2693928048U, // <7,7,1,5>: Cost 3 vext3 <1,5,3,7>, <7,1,5,3> + 2585170766U, // <7,7,1,6>: Cost 3 vext1 <5,7,7,1>, <6,7,0,1> + 2735953024U, // <7,7,1,7>: Cost 3 vext3 RHS, <7,1,7,1> + 2695918731U, // <7,7,1,u>: Cost 3 vext3 <1,u,3,7>, <7,1,u,3> + 3770471574U, // <7,7,2,0>: Cost 4 vext3 <2,0,5,7>, <7,2,0,5> + 3785807002U, // <7,7,2,1>: Cost 4 vext3 RHS, <7,2,1,0> + 2712065189U, // <7,7,2,2>: Cost 3 vext3 RHS, <7,2,2,2> + 2712065196U, // <7,7,2,3>: Cost 3 vext3 RHS, <7,2,3,0> + 3773125818U, // <7,7,2,4>: Cost 4 vext3 <2,4,5,7>, <7,2,4,5> + 3766490305U, // <7,7,2,5>: Cost 4 vext3 <1,3,5,7>, <7,2,5,3> + 2700563658U, // <7,7,2,6>: Cost 3 vext3 <2,6,3,7>, <7,2,6,3> + 2735953107U, // <7,7,2,7>: Cost 3 vext3 RHS, <7,2,7,3> + 2701890780U, // <7,7,2,u>: Cost 3 vext3 <2,u,3,7>, <7,2,u,3> + 2712065251U, // <7,7,3,0>: Cost 3 vext3 RHS, <7,3,0,1> + 3766490350U, // <7,7,3,1>: Cost 4 vext3 <1,3,5,7>, <7,3,1,3> + 2712065269U, // <7,7,3,2>: Cost 3 vext3 RHS, <7,3,2,1> + 2637728196U, // <7,7,3,3>: Cost 3 vext2 <3,3,7,7>, <3,3,7,7> + 2712065291U, // <7,7,3,4>: Cost 3 vext3 RHS, <7,3,4,5> + 2693928208U, // <7,7,3,5>: Cost 3 vext3 <1,5,3,7>, <7,3,5,1> + 2700563738U, // <7,7,3,6>: Cost 3 vext3 <2,6,3,7>, <7,3,6,2> + 2640382728U, // <7,7,3,7>: Cost 3 vext2 <3,7,7,7>, <3,7,7,7> + 2701890860U, // <7,7,3,u>: Cost 3 vext3 <2,u,3,7>, <7,3,u,2> + 2712212792U, // <7,7,4,0>: Cost 3 vext3 RHS, <7,4,0,5> + 3646989312U, // <7,7,4,1>: Cost 4 vext1 <3,7,7,4>, <1,3,5,7> + 3785807176U, // <7,7,4,2>: Cost 4 vext3 RHS, <7,4,2,3> + 3646991109U, // <7,7,4,3>: Cost 4 vext1 <3,7,7,4>, <3,7,7,4> + 2712065371U, // <7,7,4,4>: Cost 3 vext3 RHS, <7,4,4,4> + 1638323558U, // <7,7,4,5>: Cost 2 vext3 RHS, <7,4,5,6> + 2712212845U, // <7,7,4,6>: Cost 3 vext3 RHS, <7,4,6,4> + 2591167846U, // <7,7,4,7>: Cost 3 vext1 <6,7,7,4>, <7,4,5,6> + 1638323585U, // <7,7,4,u>: Cost 2 vext3 RHS, <7,4,u,6> + 2585198694U, // <7,7,5,0>: Cost 3 vext1 <5,7,7,5>, LHS + 2712212884U, // <7,7,5,1>: Cost 3 vext3 RHS, <7,5,1,7> + 3771798936U, // <7,7,5,2>: Cost 4 vext3 <2,2,5,7>, <7,5,2,2> + 2692748704U, // <7,7,5,3>: Cost 3 vext3 <1,3,5,7>, <7,5,3,1> + 2585201974U, // <7,7,5,4>: Cost 3 vext1 <5,7,7,5>, RHS + 1577259032U, // <7,7,5,5>: Cost 2 vext2 <5,5,7,7>, <5,5,7,7> + 2712065473U, // <7,7,5,6>: Cost 3 vext3 RHS, <7,5,6,7> + 2712212936U, // <7,7,5,7>: Cost 3 vext3 RHS, <7,5,7,5> + 1579249931U, // <7,7,5,u>: Cost 2 vext2 <5,u,7,7>, <5,u,7,7> + 2591178854U, // <7,7,6,0>: Cost 3 vext1 <6,7,7,6>, LHS + 3785807333U, // <7,7,6,1>: Cost 4 vext3 RHS, <7,6,1,7> + 2712212974U, // <7,7,6,2>: Cost 3 vext3 RHS, <7,6,2,7> + 3766564337U, // <7,7,6,3>: Cost 4 vext3 <1,3,6,7>, <7,6,3,1> + 2591182134U, // <7,7,6,4>: Cost 3 vext1 <6,7,7,6>, RHS + 1638323718U, // <7,7,6,5>: Cost 2 vext3 RHS, <7,6,5,4> + 1583895362U, // <7,7,6,6>: Cost 2 vext2 <6,6,7,7>, <6,6,7,7> + 2712065556U, // <7,7,6,7>: Cost 3 vext3 RHS, <7,6,7,0> + 1640314401U, // <7,7,6,u>: Cost 2 vext3 RHS, <7,6,u,4> + 1523417190U, // <7,7,7,0>: Cost 2 vext1 <7,7,7,7>, LHS + 2597159732U, // <7,7,7,1>: Cost 3 vext1 <7,7,7,7>, <1,1,1,1> + 2597160552U, // <7,7,7,2>: Cost 3 vext1 <7,7,7,7>, <2,2,2,2> + 2597161110U, // <7,7,7,3>: Cost 3 vext1 <7,7,7,7>, <3,0,1,2> + 1523420470U, // <7,7,7,4>: Cost 2 vext1 <7,7,7,7>, RHS + 2651002296U, // <7,7,7,5>: Cost 3 vext2 <5,5,7,7>, <7,5,5,7> + 2712065633U, // <7,7,7,6>: Cost 3 vext3 RHS, <7,7,6,5> + 363253046U, // <7,7,7,7>: Cost 1 vdup3 RHS + 363253046U, // <7,7,7,u>: Cost 1 vdup3 RHS + 1523417190U, // <7,7,u,0>: Cost 2 vext1 <7,7,7,7>, LHS + 1638471298U, // <7,7,u,1>: Cost 2 vext3 RHS, <7,u,1,2> + 2712213130U, // <7,7,u,2>: Cost 3 vext3 RHS, <7,u,2,1> + 2692970131U, // <7,7,u,3>: Cost 3 vext3 <1,3,u,7>, <7,u,3,1> + 1523420470U, // <7,7,u,4>: Cost 2 vext1 <7,7,7,7>, RHS + 1638471336U, // <7,7,u,5>: Cost 2 vext3 RHS, <7,u,5,4> + 1595840756U, // <7,7,u,6>: Cost 2 vext2 , + 363253046U, // <7,7,u,7>: Cost 1 vdup3 RHS + 363253046U, // <7,7,u,u>: Cost 1 vdup3 RHS + 1638318080U, // <7,u,0,0>: Cost 2 vext3 RHS, <0,0,0,0> + 1638323923U, // <7,u,0,1>: Cost 2 vext3 RHS, + 1662211804U, // <7,u,0,2>: Cost 2 vext3 RHS, + 2712065763U, // <7,u,0,3>: Cost 3 vext3 RHS, + 2712065773U, // <7,u,0,4>: Cost 3 vext3 RHS, + 1662359286U, // <7,u,0,5>: Cost 2 vext3 RHS, + 1662359296U, // <7,u,0,6>: Cost 2 vext3 RHS, + 2987150664U, // <7,u,0,7>: Cost 3 vzipr <5,6,7,0>, RHS + 1638323986U, // <7,u,0,u>: Cost 2 vext3 RHS, + 1517469798U, // <7,u,1,0>: Cost 2 vext1 <6,7,u,1>, LHS + 1638318900U, // <7,u,1,1>: Cost 2 vext3 RHS, <1,1,1,1> + 564582190U, // <7,u,1,2>: Cost 1 vext3 RHS, LHS + 1638324023U, // <7,u,1,3>: Cost 2 vext3 RHS, + 1517473078U, // <7,u,1,4>: Cost 2 vext1 <6,7,u,1>, RHS + 2693928777U, // <7,u,1,5>: Cost 3 vext3 <1,5,3,7>, + 1517474710U, // <7,u,1,6>: Cost 2 vext1 <6,7,u,1>, <6,7,u,1> + 1640462171U, // <7,u,1,7>: Cost 2 vext3 RHS, + 564582244U, // <7,u,1,u>: Cost 1 vext3 RHS, LHS + 1638318244U, // <7,u,2,0>: Cost 2 vext3 RHS, <0,2,0,2> + 1638324083U, // <7,u,2,1>: Cost 2 vext3 RHS, + 1638319720U, // <7,u,2,2>: Cost 2 vext3 RHS, <2,2,2,2> + 1638324101U, // <7,u,2,3>: Cost 2 vext3 RHS, + 1638318284U, // <7,u,2,4>: Cost 2 vext3 RHS, <0,2,4,6> + 2712065950U, // <7,u,2,5>: Cost 3 vext3 RHS, + 2700564387U, // <7,u,2,6>: Cost 3 vext3 <2,6,3,7>, + 1640314796U, // <7,u,2,7>: Cost 2 vext3 RHS, + 1638324146U, // <7,u,2,u>: Cost 2 vext3 RHS, + 1638324156U, // <7,u,3,0>: Cost 2 vext3 RHS, + 1638319064U, // <7,u,3,1>: Cost 2 vext3 RHS, <1,3,1,3> + 2700564435U, // <7,u,3,2>: Cost 3 vext3 <2,6,3,7>, + 1638320540U, // <7,u,3,3>: Cost 2 vext3 RHS, <3,3,3,3> + 1638324196U, // <7,u,3,4>: Cost 2 vext3 RHS, + 1638324207U, // <7,u,3,5>: Cost 2 vext3 RHS, + 2700564472U, // <7,u,3,6>: Cost 3 vext3 <2,6,3,7>, + 2695919610U, // <7,u,3,7>: Cost 3 vext3 <1,u,3,7>, + 1638324228U, // <7,u,3,u>: Cost 2 vext3 RHS, + 2712066061U, // <7,u,4,0>: Cost 3 vext3 RHS, + 1662212122U, // <7,u,4,1>: Cost 2 vext3 RHS, + 1662212132U, // <7,u,4,2>: Cost 2 vext3 RHS, + 2712066089U, // <7,u,4,3>: Cost 3 vext3 RHS, + 1638321360U, // <7,u,4,4>: Cost 2 vext3 RHS, <4,4,4,4> + 1638324287U, // <7,u,4,5>: Cost 2 vext3 RHS, + 1662359624U, // <7,u,4,6>: Cost 2 vext3 RHS, + 2987183432U, // <7,u,4,7>: Cost 3 vzipr <5,6,7,4>, RHS + 1638324314U, // <7,u,4,u>: Cost 2 vext3 RHS, + 1517502566U, // <7,u,5,0>: Cost 2 vext1 <6,7,u,5>, LHS + 1574612693U, // <7,u,5,1>: Cost 2 vext2 <5,1,7,u>, <5,1,7,u> + 2712066162U, // <7,u,5,2>: Cost 3 vext3 RHS, + 1638324351U, // <7,u,5,3>: Cost 2 vext3 RHS, + 94965064U, // <7,u,5,4>: Cost 1 vrev RHS + 1577267225U, // <7,u,5,5>: Cost 2 vext2 <5,5,7,u>, <5,5,7,u> + 564582554U, // <7,u,5,6>: Cost 1 vext3 RHS, RHS + 1640462499U, // <7,u,5,7>: Cost 2 vext3 RHS, + 564582572U, // <7,u,5,u>: Cost 1 vext3 RHS, RHS + 2712066223U, // <7,u,6,0>: Cost 3 vext3 RHS, + 2712066238U, // <7,u,6,1>: Cost 3 vext3 RHS, + 1581249023U, // <7,u,6,2>: Cost 2 vext2 <6,2,7,u>, <6,2,7,u> + 1638324432U, // <7,u,6,3>: Cost 2 vext3 RHS, + 1638468980U, // <7,u,6,4>: Cost 2 vext3 RHS, <4,6,4,6> + 1638471903U, // <7,u,6,5>: Cost 2 vext3 RHS, + 1583903555U, // <7,u,6,6>: Cost 2 vext2 <6,6,7,u>, <6,6,7,u> + 1640315117U, // <7,u,6,7>: Cost 2 vext3 RHS, + 1638324477U, // <7,u,6,u>: Cost 2 vext3 RHS, + 1638471936U, // <7,u,7,0>: Cost 2 vext3 RHS, + 2692970763U, // <7,u,7,1>: Cost 3 vext3 <1,3,u,7>, + 2700933399U, // <7,u,7,2>: Cost 3 vext3 <2,6,u,7>, + 2573347601U, // <7,u,7,3>: Cost 3 vext1 <3,7,u,7>, <3,7,u,7> + 1638471976U, // <7,u,7,4>: Cost 2 vext3 RHS, + 1511551171U, // <7,u,7,5>: Cost 2 vext1 <5,7,u,7>, <5,7,u,7> + 2712213815U, // <7,u,7,6>: Cost 3 vext3 RHS, + 363253046U, // <7,u,7,7>: Cost 1 vdup3 RHS + 363253046U, // <7,u,7,u>: Cost 1 vdup3 RHS + 1638324561U, // <7,u,u,0>: Cost 2 vext3 RHS, + 1638324569U, // <7,u,u,1>: Cost 2 vext3 RHS, + 564582757U, // <7,u,u,2>: Cost 1 vext3 RHS, LHS + 1638324587U, // <7,u,u,3>: Cost 2 vext3 RHS, + 96955963U, // <7,u,u,4>: Cost 1 vrev RHS + 1638324611U, // <7,u,u,5>: Cost 2 vext3 RHS, + 564582797U, // <7,u,u,6>: Cost 1 vext3 RHS, RHS + 363253046U, // <7,u,u,7>: Cost 1 vdup3 RHS + 564582811U, // <7,u,u,u>: Cost 1 vext3 RHS, LHS + 135053414U, // : Cost 1 vdup0 LHS + 1611489290U, // : Cost 2 vext3 LHS, <0,0,1,1> + 1611489300U, // : Cost 2 vext3 LHS, <0,0,2,2> + 2232576147U, // : Cost 3 vrev <3,0,0,u> + 1481706806U, // : Cost 2 vext1 <0,u,0,0>, RHS + 2555449040U, // : Cost 3 vext1 <0,u,0,0>, <5,1,7,3> + 2591282078U, // : Cost 3 vext1 <6,u,0,0>, <6,u,0,0> + 2256466935U, // : Cost 3 vrev <7,0,0,u> + 135053414U, // : Cost 1 vdup0 LHS + 1493655654U, // : Cost 2 vext1 <2,u,0,1>, LHS + 1860550758U, // : Cost 2 vzipl LHS, LHS + 537747563U, // : Cost 1 vext3 LHS, LHS + 2625135576U, // : Cost 3 vext2 <1,2,u,0>, <1,3,1,3> + 1493658934U, // : Cost 2 vext1 <2,u,0,1>, RHS + 2625135760U, // : Cost 3 vext2 <1,2,u,0>, <1,5,3,7> + 1517548447U, // : Cost 2 vext1 <6,u,0,1>, <6,u,0,1> + 2591290362U, // : Cost 3 vext1 <6,u,0,1>, <7,0,1,2> + 537747612U, // : Cost 1 vext3 LHS, LHS + 1611489444U, // : Cost 2 vext3 LHS, <0,2,0,2> + 2685231276U, // : Cost 3 vext3 LHS, <0,2,1,1> + 1994768486U, // : Cost 2 vtrnl LHS, LHS + 2685231294U, // : Cost 3 vext3 LHS, <0,2,3,1> + 1611489484U, // : Cost 2 vext3 LHS, <0,2,4,6> + 2712068310U, // : Cost 3 vext3 RHS, <0,2,5,7> + 2625136570U, // : Cost 3 vext2 <1,2,u,0>, <2,6,3,7> + 2591962097U, // : Cost 3 vext1 <7,0,0,2>, <7,0,0,2> + 1611489516U, // : Cost 2 vext3 LHS, <0,2,u,2> + 2954067968U, // : Cost 3 vzipr LHS, <0,0,0,0> + 2685231356U, // : Cost 3 vext3 LHS, <0,3,1,0> + 1154852525U, // : Cost 2 vrev <2,3,0,u> + 2625137052U, // : Cost 3 vext2 <1,2,u,0>, <3,3,3,3> + 2625137154U, // : Cost 3 vext2 <1,2,u,0>, <3,4,5,6> + 2639071848U, // : Cost 3 vext2 <3,5,u,0>, <3,5,u,0> + 2586661226U, // : Cost 3 vext1 <6,1,0,3>, <6,1,0,3> + 2258457834U, // : Cost 3 vrev <7,3,0,u> + 1567320923U, // : Cost 2 vext2 <3,u,u,0>, <3,u,u,0> + 2687074636U, // : Cost 3 vext3 <0,4,0,u>, <0,4,0,u> + 1611489618U, // : Cost 2 vext3 LHS, <0,4,1,5> + 1611489628U, // : Cost 2 vext3 LHS, <0,4,2,6> + 2235230679U, // : Cost 3 vrev <3,4,0,u> + 2555481398U, // : Cost 3 vext1 <0,u,0,4>, RHS + 1551396150U, // : Cost 2 vext2 <1,2,u,0>, RHS + 2651680116U, // : Cost 3 vext2 <5,6,u,0>, <4,6,4,6> + 2259121467U, // : Cost 3 vrev <7,4,0,u> + 1611932050U, // : Cost 2 vext3 LHS, <0,4,u,6> + 2573402214U, // : Cost 3 vext1 <3,u,0,5>, LHS + 1863532646U, // : Cost 2 vzipl RHS, LHS + 2712068526U, // : Cost 3 vext3 RHS, <0,5,2,7> + 2573404310U, // : Cost 3 vext1 <3,u,0,5>, <3,0,1,2> + 2573405494U, // : Cost 3 vext1 <3,u,0,5>, RHS + 2247839706U, // : Cost 3 vrev <5,5,0,u> + 1577939051U, // : Cost 2 vext2 <5,6,u,0>, <5,6,u,0> + 2830077238U, // : Cost 3 vuzpr <1,u,3,0>, RHS + 1579266317U, // : Cost 2 vext2 <5,u,u,0>, <5,u,u,0> + 2555494502U, // : Cost 3 vext1 <0,u,0,6>, LHS + 2712068598U, // : Cost 3 vext3 RHS, <0,6,1,7> + 1997750374U, // : Cost 2 vtrnl RHS, LHS + 2655662673U, // : Cost 3 vext2 <6,3,u,0>, <6,3,u,0> + 2555497782U, // : Cost 3 vext1 <0,u,0,6>, RHS + 2248503339U, // : Cost 3 vrev <5,6,0,u> + 2651681592U, // : Cost 3 vext2 <5,6,u,0>, <6,6,6,6> + 2651681614U, // : Cost 3 vext2 <5,6,u,0>, <6,7,0,1> + 1997750428U, // : Cost 2 vtrnl RHS, LHS + 2567446630U, // : Cost 3 vext1 <2,u,0,7>, LHS + 2567447446U, // : Cost 3 vext1 <2,u,0,7>, <1,2,3,0> + 2567448641U, // : Cost 3 vext1 <2,u,0,7>, <2,u,0,7> + 2237221578U, // : Cost 3 vrev <3,7,0,u> + 2567449910U, // : Cost 3 vext1 <2,u,0,7>, RHS + 2651682242U, // : Cost 3 vext2 <5,6,u,0>, <7,5,6,u> + 1181397845U, // : Cost 2 vrev <6,7,0,u> + 2651682412U, // : Cost 3 vext2 <5,6,u,0>, <7,7,7,7> + 1193343239U, // : Cost 2 vrev + 135053414U, // : Cost 1 vdup0 LHS + 1611489938U, // : Cost 2 vext3 LHS, <0,u,1,1> + 537748125U, // : Cost 1 vext3 LHS, LHS + 2685674148U, // : Cost 3 vext3 LHS, <0,u,3,1> + 1611932338U, // : Cost 2 vext3 LHS, <0,u,4,6> + 1551399066U, // : Cost 2 vext2 <1,2,u,0>, RHS + 1182061478U, // : Cost 2 vrev <6,u,0,u> + 2830077481U, // : Cost 3 vuzpr <1,u,3,0>, RHS + 537748179U, // : Cost 1 vext3 LHS, LHS + 1499693158U, // : Cost 2 vext1 <3,u,1,0>, LHS + 1558036582U, // : Cost 2 vext2 <2,3,u,1>, LHS + 2619171051U, // : Cost 3 vext2 <0,2,u,1>, <0,2,u,1> + 1158908060U, // : Cost 2 vrev <3,0,1,u> + 1499696438U, // : Cost 2 vext1 <3,u,1,0>, RHS + 2712068872U, // : Cost 3 vext3 RHS, <1,0,5,2> + 2250567975U, // : Cost 3 vrev <6,0,1,u> + 1182798848U, // : Cost 2 vrev <7,0,1,u> + 1558037149U, // : Cost 2 vext2 <2,3,u,1>, LHS + 1481785446U, // : Cost 2 vext1 <0,u,1,1>, LHS + 202162278U, // : Cost 1 vdup1 LHS + 2555528808U, // : Cost 3 vext1 <0,u,1,1>, <2,2,2,2> + 1611490120U, // : Cost 2 vext3 LHS, <1,1,3,3> + 1481788726U, // : Cost 2 vext1 <0,u,1,1>, RHS + 2689876828U, // : Cost 3 vext3 LHS, <1,1,5,5> + 2591364008U, // : Cost 3 vext1 <6,u,1,1>, <6,u,1,1> + 2257204305U, // : Cost 3 vrev <7,1,1,u> + 202162278U, // : Cost 1 vdup1 LHS + 1499709542U, // : Cost 2 vext1 <3,u,1,2>, LHS + 2689876871U, // : Cost 3 vext3 LHS, <1,2,1,3> + 2631116445U, // : Cost 3 vext2 <2,2,u,1>, <2,2,u,1> + 835584U, // : Cost 0 copy LHS + 1499712822U, // : Cost 2 vext1 <3,u,1,2>, RHS + 2689876907U, // : Cost 3 vext3 LHS, <1,2,5,3> + 2631780282U, // : Cost 3 vext2 <2,3,u,1>, <2,6,3,7> + 1523603074U, // : Cost 2 vext1 <7,u,1,2>, <7,u,1,2> + 835584U, // : Cost 0 copy LHS + 1487773798U, // : Cost 2 vext1 <1,u,1,3>, LHS + 1611490264U, // : Cost 2 vext3 LHS, <1,3,1,3> + 2685232094U, // : Cost 3 vext3 LHS, <1,3,2,0> + 2018746470U, // : Cost 2 vtrnr LHS, LHS + 1487777078U, // : Cost 2 vext1 <1,u,1,3>, RHS + 1611490304U, // : Cost 2 vext3 LHS, <1,3,5,7> + 2685674505U, // : Cost 3 vext3 LHS, <1,3,6,7> + 2640407307U, // : Cost 3 vext2 <3,7,u,1>, <3,7,u,1> + 1611490327U, // : Cost 2 vext3 LHS, <1,3,u,3> + 1567992749U, // : Cost 2 vext2 <4,0,u,1>, <4,0,u,1> + 2693121070U, // : Cost 3 vext3 <1,4,1,u>, <1,4,1,u> + 2693194807U, // : Cost 3 vext3 <1,4,2,u>, <1,4,2,u> + 2685232189U, // : Cost 3 vext3 LHS, <1,4,3,5> + 2555555126U, // : Cost 3 vext1 <0,u,1,4>, RHS + 1558039862U, // : Cost 2 vext2 <2,3,u,1>, RHS + 2645716371U, // : Cost 3 vext2 <4,6,u,1>, <4,6,u,1> + 2597361284U, // : Cost 3 vext1 <7,u,1,4>, <7,u,1,4> + 1558040105U, // : Cost 2 vext2 <2,3,u,1>, RHS + 1481818214U, // : Cost 2 vext1 <0,u,1,5>, LHS + 2555560756U, // : Cost 3 vext1 <0,u,1,5>, <1,1,1,1> + 2555561576U, // : Cost 3 vext1 <0,u,1,5>, <2,2,2,2> + 1611490448U, // : Cost 2 vext3 LHS, <1,5,3,7> + 1481821494U, // : Cost 2 vext1 <0,u,1,5>, RHS + 2555563734U, // : Cost 3 vext1 <0,u,1,5>, <5,1,u,0> + 2651689068U, // : Cost 3 vext2 <5,6,u,1>, <5,6,u,1> + 2823966006U, // : Cost 3 vuzpr <0,u,1,1>, RHS + 1611932861U, // : Cost 2 vext3 LHS, <1,5,u,7> + 2555568230U, // : Cost 3 vext1 <0,u,1,6>, LHS + 2689877199U, // : Cost 3 vext3 LHS, <1,6,1,7> + 2712069336U, // : Cost 3 vext3 RHS, <1,6,2,7> + 2685232353U, // : Cost 3 vext3 LHS, <1,6,3,7> + 2555571510U, // : Cost 3 vext1 <0,u,1,6>, RHS + 2689877235U, // : Cost 3 vext3 LHS, <1,6,5,7> + 2657661765U, // : Cost 3 vext2 <6,6,u,1>, <6,6,u,1> + 1584583574U, // : Cost 2 vext2 <6,7,u,1>, <6,7,u,1> + 1585247207U, // : Cost 2 vext2 <6,u,u,1>, <6,u,u,1> + 2561548390U, // : Cost 3 vext1 <1,u,1,7>, LHS + 2561549681U, // : Cost 3 vext1 <1,u,1,7>, <1,u,1,7> + 2573493926U, // : Cost 3 vext1 <3,u,1,7>, <2,3,0,1> + 2042962022U, // : Cost 2 vtrnr RHS, LHS + 2561551670U, // : Cost 3 vext1 <1,u,1,7>, RHS + 2980643154U, // : Cost 3 vzipr RHS, <0,4,1,5> + 2255213406U, // : Cost 3 vrev <6,7,1,u> + 2658326124U, // : Cost 3 vext2 <6,7,u,1>, <7,7,7,7> + 2042962027U, // : Cost 2 vtrnr RHS, LHS + 1481842790U, // : Cost 2 vext1 <0,u,1,u>, LHS + 202162278U, // : Cost 1 vdup1 LHS + 2685674867U, // : Cost 3 vext3 LHS, <1,u,2,0> + 835584U, // : Cost 0 copy LHS + 1481846070U, // : Cost 2 vext1 <0,u,1,u>, RHS + 1611933077U, // : Cost 2 vext3 LHS, <1,u,5,7> + 2685674910U, // : Cost 3 vext3 LHS, <1,u,6,7> + 1188107912U, // : Cost 2 vrev <7,u,1,u> + 835584U, // : Cost 0 copy LHS + 1544110154U, // : Cost 2 vext2 <0,0,u,2>, <0,0,u,2> + 1545437286U, // : Cost 2 vext2 <0,2,u,2>, LHS + 1545437420U, // : Cost 2 vext2 <0,2,u,2>, <0,2,u,2> + 2685232589U, // : Cost 3 vext3 LHS, <2,0,3,0> + 2619179346U, // : Cost 3 vext2 <0,2,u,2>, <0,4,1,5> + 2696734183U, // : Cost 3 vext3 <2,0,5,u>, <2,0,5,u> + 2712069609U, // : Cost 3 vext3 RHS, <2,0,6,1> + 2256614409U, // : Cost 3 vrev <7,0,2,u> + 1545437853U, // : Cost 2 vext2 <0,2,u,2>, LHS + 67985515U, // : Cost 1 vrev LHS + 2619179828U, // : Cost 3 vext2 <0,2,u,2>, <1,1,1,1> + 2619179926U, // : Cost 3 vext2 <0,2,u,2>, <1,2,3,0> + 2685232670U, // : Cost 3 vext3 LHS, <2,1,3,0> + 2555604278U, // : Cost 3 vext1 <0,u,2,1>, RHS + 2619180176U, // : Cost 3 vext2 <0,2,u,2>, <1,5,3,7> + 2689877564U, // : Cost 3 vext3 LHS, <2,1,6,3> + 2257278042U, // : Cost 3 vrev <7,1,2,u> + 115767091U, // : Cost 1 vrev LHS + 1481867366U, // : Cost 2 vext1 <0,u,2,2>, LHS + 2555609908U, // : Cost 3 vext1 <0,u,2,2>, <1,1,1,1> + 269271142U, // : Cost 1 vdup2 LHS + 1611490930U, // : Cost 2 vext3 LHS, <2,2,3,3> + 1481870646U, // : Cost 2 vext1 <0,u,2,2>, RHS + 2689877640U, // : Cost 3 vext3 LHS, <2,2,5,7> + 2619180986U, // : Cost 3 vext2 <0,2,u,2>, <2,6,3,7> + 2257941675U, // : Cost 3 vrev <7,2,2,u> + 269271142U, // : Cost 1 vdup2 LHS + 408134301U, // : Cost 1 vext1 LHS, LHS + 1481876276U, // : Cost 2 vext1 LHS, <1,1,1,1> + 1481877096U, // : Cost 2 vext1 LHS, <2,2,2,2> + 1880326246U, // : Cost 2 vzipr LHS, LHS + 408137014U, // : Cost 1 vext1 LHS, RHS + 1529654992U, // : Cost 2 vext1 LHS, <5,1,7,3> + 1529655802U, // : Cost 2 vext1 LHS, <6,2,7,3> + 1529656314U, // : Cost 2 vext1 LHS, <7,0,1,2> + 408139566U, // : Cost 1 vext1 LHS, LHS + 1567853468U, // : Cost 2 vext2 <4,0,6,2>, <4,0,6,2> + 2561598362U, // : Cost 3 vext1 <1,u,2,4>, <1,2,3,4> + 2555627214U, // : Cost 3 vext1 <0,u,2,4>, <2,3,4,5> + 2685232918U, // : Cost 3 vext3 LHS, <2,4,3,5> + 2555628854U, // : Cost 3 vext1 <0,u,2,4>, RHS + 1545440566U, // : Cost 2 vext2 <0,2,u,2>, RHS + 1571982740U, // : Cost 2 vext2 <4,6,u,2>, <4,6,u,2> + 2659659225U, // : Cost 3 vext2 <7,0,u,2>, <4,7,6,u> + 1545440809U, // : Cost 2 vext2 <0,2,u,2>, RHS + 2555633766U, // : Cost 3 vext1 <0,u,2,5>, LHS + 2561606550U, // : Cost 3 vext1 <1,u,2,5>, <1,2,3,0> + 2689877856U, // : Cost 3 vext3 LHS, <2,5,2,7> + 2685233000U, // : Cost 3 vext3 LHS, <2,5,3,6> + 2555637046U, // : Cost 3 vext1 <0,u,2,5>, RHS + 2645725188U, // : Cost 3 vext2 <4,6,u,2>, <5,5,5,5> + 2689877892U, // : Cost 3 vext3 LHS, <2,5,6,7> + 2823900470U, // : Cost 3 vuzpr <0,u,0,2>, RHS + 2685675413U, // : Cost 3 vext3 LHS, <2,5,u,6> + 1481900134U, // : Cost 2 vext1 <0,u,2,6>, LHS + 2555642676U, // : Cost 3 vext1 <0,u,2,6>, <1,1,1,1> + 2555643496U, // : Cost 3 vext1 <0,u,2,6>, <2,2,2,2> + 1611491258U, // : Cost 2 vext3 LHS, <2,6,3,7> + 1481903414U, // : Cost 2 vext1 <0,u,2,6>, RHS + 2689877964U, // : Cost 3 vext3 LHS, <2,6,5,7> + 2689877973U, // : Cost 3 vext3 LHS, <2,6,6,7> + 2645726030U, // : Cost 3 vext2 <4,6,u,2>, <6,7,0,1> + 1611933671U, // : Cost 2 vext3 LHS, <2,6,u,7> + 1585919033U, // : Cost 2 vext2 <7,0,u,2>, <7,0,u,2> + 2800079866U, // : Cost 3 vuzpl LHS, <7,0,1,2> + 2567596115U, // : Cost 3 vext1 <2,u,2,7>, <2,u,2,7> + 1906901094U, // : Cost 2 vzipr RHS, LHS + 2555653430U, // : Cost 3 vext1 <0,u,2,7>, RHS + 2800080230U, // : Cost 3 vuzpl LHS, <7,4,5,6> + 2980643164U, // : Cost 3 vzipr RHS, <0,4,2,6> + 2645726828U, // : Cost 3 vext2 <4,6,u,2>, <7,7,7,7> + 1906901099U, // : Cost 2 vzipr RHS, LHS + 72630946U, // : Cost 1 vrev LHS + 1545443118U, // : Cost 2 vext2 <0,2,u,2>, LHS + 269271142U, // : Cost 1 vdup2 LHS + 1611491416U, // : Cost 2 vext3 LHS, <2,u,3,3> + 408177974U, // : Cost 1 vext1 LHS, RHS + 1545443482U, // : Cost 2 vext2 <0,2,u,2>, RHS + 1726339226U, // : Cost 2 vuzpl LHS, RHS + 1529697274U, // : Cost 2 vext1 LHS, <7,0,1,2> + 408180526U, // : Cost 1 vext1 LHS, LHS + 1544781824U, // : Cost 2 vext2 LHS, <0,0,0,0> + 471040156U, // : Cost 1 vext2 LHS, LHS + 1544781988U, // : Cost 2 vext2 LHS, <0,2,0,2> + 2618523900U, // : Cost 3 vext2 LHS, <0,3,1,0> + 1544782162U, // : Cost 2 vext2 LHS, <0,4,1,5> + 2712070330U, // : Cost 3 vext3 RHS, <3,0,5,2> + 2623169023U, // : Cost 3 vext2 LHS, <0,6,2,7> + 2597475986U, // : Cost 3 vext1 <7,u,3,0>, <7,u,3,0> + 471040669U, // : Cost 1 vext2 LHS, LHS + 2618524404U, // : Cost 3 vext2 LHS, <1,0,3,0> + 1544782644U, // : Cost 2 vext2 LHS, <1,1,1,1> + 1544782742U, // : Cost 2 vext2 LHS, <1,2,3,0> + 1544782808U, // : Cost 2 vext2 LHS, <1,3,1,3> + 2618524733U, // : Cost 3 vext2 LHS, <1,4,3,5> + 1544782992U, // : Cost 2 vext2 LHS, <1,5,3,7> + 2618524897U, // : Cost 3 vext2 LHS, <1,6,3,7> + 2703517987U, // : Cost 3 vext3 <3,1,7,u>, <3,1,7,u> + 1544783213U, // : Cost 2 vext2 LHS, <1,u,1,3> + 2618525133U, // : Cost 3 vext2 LHS, <2,0,3,0> + 1611491638U, // : Cost 2 vext3 LHS, <3,2,1,0> + 1544783464U, // : Cost 2 vext2 LHS, <2,2,2,2> + 1544783526U, // : Cost 2 vext2 LHS, <2,3,0,1> + 2618525462U, // : Cost 3 vext2 LHS, <2,4,3,5> + 2618525544U, // : Cost 3 vext2 LHS, <2,5,3,6> + 1544783802U, // : Cost 2 vext2 LHS, <2,6,3,7> + 2704181620U, // : Cost 3 vext3 <3,2,7,u>, <3,2,7,u> + 1544783931U, // : Cost 2 vext2 LHS, <2,u,0,1> + 1544784022U, // : Cost 2 vext2 LHS, <3,0,1,2> + 1487922559U, // : Cost 2 vext1 <1,u,3,3>, <1,u,3,3> + 1544784182U, // : Cost 2 vext2 LHS, <3,2,1,0> + 336380006U, // : Cost 1 vdup3 LHS + 1544784386U, // : Cost 2 vext2 LHS, <3,4,5,6> + 2824054478U, // : Cost 3 vuzpr LHS, <2,3,4,5> + 2591527868U, // : Cost 3 vext1 <6,u,3,3>, <6,u,3,3> + 2954069136U, // : Cost 3 vzipr LHS, <1,5,3,7> + 336380006U, // : Cost 1 vdup3 LHS + 1487929446U, // : Cost 2 vext1 <1,u,3,4>, LHS + 1487930752U, // : Cost 2 vext1 <1,u,3,4>, <1,u,3,4> + 2623171644U, // : Cost 3 vext2 LHS, <4,2,6,0> + 2561673366U, // : Cost 3 vext1 <1,u,3,4>, <3,0,1,2> + 1487932726U, // : Cost 2 vext1 <1,u,3,4>, RHS + 471043382U, // : Cost 1 vext2 LHS, RHS + 1592561012U, // : Cost 2 vext2 LHS, <4,6,4,6> + 2597508758U, // : Cost 3 vext1 <7,u,3,4>, <7,u,3,4> + 471043625U, // : Cost 1 vext2 LHS, RHS + 2555707494U, // : Cost 3 vext1 <0,u,3,5>, LHS + 1574645465U, // : Cost 2 vext2 <5,1,u,3>, <5,1,u,3> + 2567653106U, // : Cost 3 vext1 <2,u,3,5>, <2,3,u,5> + 2555709954U, // : Cost 3 vext1 <0,u,3,5>, <3,4,5,6> + 2555710774U, // : Cost 3 vext1 <0,u,3,5>, RHS + 1592561668U, // : Cost 2 vext2 LHS, <5,5,5,5> + 1592561762U, // : Cost 2 vext2 LHS, <5,6,7,0> + 1750314294U, // : Cost 2 vuzpr LHS, RHS + 1750314295U, // : Cost 2 vuzpr LHS, RHS + 2623172897U, // : Cost 3 vext2 LHS, <6,0,1,2> + 2561688962U, // : Cost 3 vext1 <1,u,3,6>, <1,u,3,6> + 1581281795U, // : Cost 2 vext2 <6,2,u,3>, <6,2,u,3> + 2706541204U, // : Cost 3 vext3 <3,6,3,u>, <3,6,3,u> + 2623173228U, // : Cost 3 vext2 LHS, <6,4,2,0> + 2248724550U, // : Cost 3 vrev <5,6,3,u> + 1592562488U, // : Cost 2 vext2 LHS, <6,6,6,6> + 1592562510U, // : Cost 2 vext2 LHS, <6,7,0,1> + 1592562591U, // : Cost 2 vext2 LHS, <6,u,0,1> + 1487954022U, // : Cost 2 vext1 <1,u,3,7>, LHS + 1487955331U, // : Cost 2 vext1 <1,u,3,7>, <1,u,3,7> + 1493928028U, // : Cost 2 vext1 <2,u,3,7>, <2,u,3,7> + 2561697942U, // : Cost 3 vext1 <1,u,3,7>, <3,0,1,2> + 1487957302U, // : Cost 2 vext1 <1,u,3,7>, RHS + 2707352311U, // : Cost 3 vext3 <3,7,5,u>, <3,7,5,u> + 1592563206U, // : Cost 2 vext2 LHS, <7,6,5,4> + 1592563308U, // : Cost 2 vext2 LHS, <7,7,7,7> + 1487959854U, // : Cost 2 vext1 <1,u,3,7>, LHS + 1544787667U, // : Cost 2 vext2 LHS, + 471045934U, // : Cost 1 vext2 LHS, LHS + 1544787827U, // : Cost 2 vext2 LHS, + 336380006U, // : Cost 1 vdup3 LHS + 1544788031U, // : Cost 2 vext2 LHS, + 471046298U, // : Cost 1 vext2 LHS, RHS + 1549433040U, // : Cost 2 vext2 LHS, + 1750314537U, // : Cost 2 vuzpr LHS, RHS + 471046501U, // : Cost 1 vext2 LHS, LHS + 2625167360U, // : Cost 3 vext2 <1,2,u,4>, <0,0,0,0> + 1551425638U, // : Cost 2 vext2 <1,2,u,4>, LHS + 2619195630U, // : Cost 3 vext2 <0,2,u,4>, <0,2,u,4> + 2232871095U, // : Cost 3 vrev <3,0,4,u> + 2625167698U, // : Cost 3 vext2 <1,2,u,4>, <0,4,1,5> + 1638329234U, // : Cost 2 vext3 RHS, <4,0,5,1> + 1638329244U, // : Cost 2 vext3 RHS, <4,0,6,2> + 2256761883U, // : Cost 3 vrev <7,0,4,u> + 1551426205U, // : Cost 2 vext2 <1,2,u,4>, LHS + 2555748454U, // : Cost 3 vext1 <0,u,4,1>, LHS + 2221589334U, // : Cost 3 vrev <1,1,4,u> + 1551426503U, // : Cost 2 vext2 <1,2,u,4>, <1,2,u,4> + 2625168344U, // : Cost 3 vext2 <1,2,u,4>, <1,3,1,3> + 2555751734U, // : Cost 3 vext1 <0,u,4,1>, RHS + 1860554038U, // : Cost 2 vzipl LHS, RHS + 2689879022U, // : Cost 3 vext3 LHS, <4,1,6,3> + 2592248852U, // : Cost 3 vext1 <7,0,4,1>, <7,0,4,1> + 1555408301U, // : Cost 2 vext2 <1,u,u,4>, <1,u,u,4> + 2216280270U, // : Cost 3 vrev <0,2,4,u> + 2222252967U, // : Cost 3 vrev <1,2,4,u> + 2625169000U, // : Cost 3 vext2 <1,2,u,4>, <2,2,2,2> + 2619197134U, // : Cost 3 vext2 <0,2,u,4>, <2,3,4,5> + 2555759926U, // : Cost 3 vext1 <0,u,4,2>, RHS + 2712071222U, // : Cost 3 vext3 RHS, <4,2,5,3> + 1994771766U, // : Cost 2 vtrnl LHS, RHS + 2592257045U, // : Cost 3 vext1 <7,0,4,2>, <7,0,4,2> + 1994771784U, // : Cost 2 vtrnl LHS, RHS + 2625169558U, // : Cost 3 vext2 <1,2,u,4>, <3,0,1,2> + 2222916600U, // : Cost 3 vrev <1,3,4,u> + 1155147473U, // : Cost 2 vrev <2,3,4,u> + 2625169820U, // : Cost 3 vext2 <1,2,u,4>, <3,3,3,3> + 2625169922U, // : Cost 3 vext2 <1,2,u,4>, <3,4,5,6> + 2954069710U, // : Cost 3 vzipr LHS, <2,3,4,5> + 2954068172U, // : Cost 3 vzipr LHS, <0,2,4,6> + 2258752782U, // : Cost 3 vrev <7,3,4,u> + 1190983655U, // : Cost 2 vrev + 1505919078U, // : Cost 2 vext1 <4,u,4,4>, LHS + 2567717831U, // : Cost 3 vext1 <2,u,4,4>, <1,2,u,4> + 2567719010U, // : Cost 3 vext1 <2,u,4,4>, <2,u,4,4> + 2235525627U, // : Cost 3 vrev <3,4,4,u> + 161926454U, // : Cost 1 vdup0 RHS + 1551428918U, // : Cost 2 vext2 <1,2,u,4>, RHS + 1638329572U, // : Cost 2 vext3 RHS, <4,4,6,6> + 2259416415U, // : Cost 3 vrev <7,4,4,u> + 161926454U, // : Cost 1 vdup0 RHS + 1493983334U, // : Cost 2 vext1 <2,u,4,5>, LHS + 2689879301U, // : Cost 3 vext3 LHS, <4,5,1,3> + 1493985379U, // : Cost 2 vext1 <2,u,4,5>, <2,u,4,5> + 2567727254U, // : Cost 3 vext1 <2,u,4,5>, <3,0,1,2> + 1493986614U, // : Cost 2 vext1 <2,u,4,5>, RHS + 1863535926U, // : Cost 2 vzipl RHS, RHS + 537750838U, // : Cost 1 vext3 LHS, RHS + 2830110006U, // : Cost 3 vuzpr <1,u,3,4>, RHS + 537750856U, // : Cost 1 vext3 LHS, RHS + 1482047590U, // : Cost 2 vext1 <0,u,4,6>, LHS + 2555790132U, // : Cost 3 vext1 <0,u,4,6>, <1,1,1,1> + 2555790952U, // : Cost 3 vext1 <0,u,4,6>, <2,2,2,2> + 2555791510U, // : Cost 3 vext1 <0,u,4,6>, <3,0,1,2> + 1482050870U, // : Cost 2 vext1 <0,u,4,6>, RHS + 2689879422U, // : Cost 3 vext3 LHS, <4,6,5,7> + 1997753654U, // : Cost 2 vtrnl RHS, RHS + 2712071562U, // : Cost 3 vext3 RHS, <4,6,7,1> + 1482053422U, // : Cost 2 vext1 <0,u,4,6>, LHS + 2567741542U, // : Cost 3 vext1 <2,u,4,7>, LHS + 2567742362U, // : Cost 3 vext1 <2,u,4,7>, <1,2,3,4> + 2567743589U, // : Cost 3 vext1 <2,u,4,7>, <2,u,4,7> + 2237516526U, // : Cost 3 vrev <3,7,4,u> + 2567744822U, // : Cost 3 vext1 <2,u,4,7>, RHS + 2712071624U, // : Cost 3 vext3 RHS, <4,7,5,0> + 1181692793U, // : Cost 2 vrev <6,7,4,u> + 2651715180U, // : Cost 3 vext2 <5,6,u,4>, <7,7,7,7> + 1591244483U, // : Cost 2 vext2 <7,u,u,4>, <7,u,u,4> + 1482063974U, // : Cost 2 vext1 <0,u,4,u>, LHS + 1551431470U, // : Cost 2 vext2 <1,2,u,4>, LHS + 1158465638U, // : Cost 2 vrev <2,u,4,u> + 2555807894U, // : Cost 3 vext1 <0,u,4,u>, <3,0,1,2> + 161926454U, // : Cost 1 vdup0 RHS + 1551431834U, // : Cost 2 vext2 <1,2,u,4>, RHS + 537751081U, // : Cost 1 vext3 LHS, RHS + 2830110249U, // : Cost 3 vuzpr <1,u,3,4>, RHS + 537751099U, // : Cost 1 vext3 LHS, RHS + 2631811072U, // : Cost 3 vext2 <2,3,u,5>, <0,0,0,0> + 1558069350U, // : Cost 2 vext2 <2,3,u,5>, LHS + 2619203823U, // : Cost 3 vext2 <0,2,u,5>, <0,2,u,5> + 2619867456U, // : Cost 3 vext2 <0,3,u,5>, <0,3,u,5> + 1546273106U, // : Cost 2 vext2 <0,4,1,5>, <0,4,1,5> + 2733010539U, // : Cost 3 vext3 LHS, <5,0,5,1> + 2597622682U, // : Cost 3 vext1 <7,u,5,0>, <6,7,u,5> + 3098512694U, // : Cost 3 vtrnr <1,u,3,0>, RHS + 1558069917U, // : Cost 2 vext2 <2,3,u,5>, LHS + 1505968230U, // : Cost 2 vext1 <4,u,5,1>, LHS + 2624512887U, // : Cost 3 vext2 <1,1,u,5>, <1,1,u,5> + 2631811990U, // : Cost 3 vext2 <2,3,u,5>, <1,2,3,0> + 2618541056U, // : Cost 3 vext2 <0,1,u,5>, <1,3,5,7> + 1505971510U, // : Cost 2 vext1 <4,u,5,1>, RHS + 2627167419U, // : Cost 3 vext2 <1,5,u,5>, <1,5,u,5> + 2579714554U, // : Cost 3 vext1 <4,u,5,1>, <6,2,7,3> + 1638330064U, // : Cost 2 vext3 RHS, <5,1,7,3> + 1638477529U, // : Cost 2 vext3 RHS, <5,1,u,3> + 2561802342U, // : Cost 3 vext1 <1,u,5,2>, LHS + 2561803264U, // : Cost 3 vext1 <1,u,5,2>, <1,3,5,7> + 2631149217U, // : Cost 3 vext2 <2,2,u,5>, <2,2,u,5> + 1558071026U, // : Cost 2 vext2 <2,3,u,5>, <2,3,u,5> + 2561805622U, // : Cost 3 vext1 <1,u,5,2>, RHS + 2714062607U, // : Cost 3 vext3 RHS, <5,2,5,3> + 2631813050U, // : Cost 3 vext2 <2,3,u,5>, <2,6,3,7> + 3092335926U, // : Cost 3 vtrnr <0,u,0,2>, RHS + 1561389191U, // : Cost 2 vext2 <2,u,u,5>, <2,u,u,5> + 2561810534U, // : Cost 3 vext1 <1,u,5,3>, LHS + 2222990337U, // : Cost 3 vrev <1,3,5,u> + 2631813430U, // : Cost 3 vext2 <2,3,u,5>, <3,2,1,0> + 2631813532U, // : Cost 3 vext2 <2,3,u,5>, <3,3,3,3> + 2619869698U, // : Cost 3 vext2 <0,3,u,5>, <3,4,5,6> + 3001847002U, // : Cost 3 vzipr LHS, <4,4,5,5> + 2954070530U, // : Cost 3 vzipr LHS, <3,4,5,6> + 2018749750U, // : Cost 2 vtrnr LHS, RHS + 2018749751U, // : Cost 2 vtrnr LHS, RHS + 1523908710U, // : Cost 2 vext1 <7,u,5,4>, LHS + 2223653970U, // : Cost 3 vrev <1,4,5,u> + 2229626667U, // : Cost 3 vrev <2,4,5,u> + 1161857540U, // : Cost 2 vrev <3,4,5,u> + 1523911990U, // : Cost 2 vext1 <7,u,5,4>, RHS + 1558072630U, // : Cost 2 vext2 <2,3,u,5>, RHS + 2645749143U, // : Cost 3 vext2 <4,6,u,5>, <4,6,u,5> + 1185748328U, // : Cost 2 vrev <7,4,5,u> + 1558072873U, // : Cost 2 vext2 <2,3,u,5>, RHS + 1506000998U, // : Cost 2 vext1 <4,u,5,5>, LHS + 2561827984U, // : Cost 3 vext1 <1,u,5,5>, <1,5,3,7> + 2579744360U, // : Cost 3 vext1 <4,u,5,5>, <2,2,2,2> + 2579744918U, // : Cost 3 vext1 <4,u,5,5>, <3,0,1,2> + 1506004278U, // : Cost 2 vext1 <4,u,5,5>, RHS + 229035318U, // : Cost 1 vdup1 RHS + 2712072206U, // : Cost 3 vext3 RHS, <5,5,6,6> + 1638330392U, // : Cost 2 vext3 RHS, <5,5,7,7> + 229035318U, // : Cost 1 vdup1 RHS + 1500037222U, // : Cost 2 vext1 <3,u,5,6>, LHS + 2561836436U, // : Cost 3 vext1 <1,u,5,6>, <1,u,5,6> + 2567809133U, // : Cost 3 vext1 <2,u,5,6>, <2,u,5,6> + 1500040006U, // : Cost 2 vext1 <3,u,5,6>, <3,u,5,6> + 1500040502U, // : Cost 2 vext1 <3,u,5,6>, RHS + 2714062935U, // : Cost 3 vext3 RHS, <5,6,5,7> + 2573783798U, // : Cost 3 vext1 <3,u,5,6>, <6,5,u,3> + 27705344U, // : Cost 0 copy RHS + 27705344U, // : Cost 0 copy RHS + 1488101478U, // : Cost 2 vext1 <1,u,5,7>, LHS + 1488102805U, // : Cost 2 vext1 <1,u,5,7>, <1,u,5,7> + 2561844840U, // : Cost 3 vext1 <1,u,5,7>, <2,2,2,2> + 2561845398U, // : Cost 3 vext1 <1,u,5,7>, <3,0,1,2> + 1488104758U, // : Cost 2 vext1 <1,u,5,7>, RHS + 1638330536U, // : Cost 2 vext3 RHS, <5,7,5,7> + 2712072362U, // : Cost 3 vext3 RHS, <5,7,6,0> + 2042965302U, // : Cost 2 vtrnr RHS, RHS + 1488107310U, // : Cost 2 vext1 <1,u,5,7>, LHS + 1488109670U, // : Cost 2 vext1 <1,u,5,u>, LHS + 1488110998U, // : Cost 2 vext1 <1,u,5,u>, <1,u,5,u> + 2561853032U, // : Cost 3 vext1 <1,u,5,u>, <2,2,2,2> + 1164512072U, // : Cost 2 vrev <3,u,5,u> + 1488112950U, // : Cost 2 vext1 <1,u,5,u>, RHS + 229035318U, // : Cost 1 vdup1 RHS + 2954111490U, // : Cost 3 vzipr LHS, <3,4,5,6> + 27705344U, // : Cost 0 copy RHS + 27705344U, // : Cost 0 copy RHS + 2619211776U, // : Cost 3 vext2 <0,2,u,6>, <0,0,0,0> + 1545470054U, // : Cost 2 vext2 <0,2,u,6>, LHS + 1545470192U, // : Cost 2 vext2 <0,2,u,6>, <0,2,u,6> + 2638233856U, // : Cost 3 vext2 <3,4,5,6>, <0,3,1,4> + 1546797458U, // : Cost 2 vext2 <0,4,u,6>, <0,4,u,6> + 2720624971U, // : Cost 3 vext3 <6,0,5,u>, <6,0,5,u> + 2591724500U, // : Cost 3 vext1 <6,u,6,0>, <6,u,6,0> + 2960682294U, // : Cost 3 vzipr <1,2,u,0>, RHS + 1545470621U, // : Cost 2 vext2 <0,2,u,6>, LHS + 2585755750U, // : Cost 3 vext1 <5,u,6,1>, LHS + 2619212596U, // : Cost 3 vext2 <0,2,u,6>, <1,1,1,1> + 2619212694U, // : Cost 3 vext2 <0,2,u,6>, <1,2,3,0> + 2619212760U, // : Cost 3 vext2 <0,2,u,6>, <1,3,1,3> + 2626511979U, // : Cost 3 vext2 <1,4,u,6>, <1,4,u,6> + 2619212944U, // : Cost 3 vext2 <0,2,u,6>, <1,5,3,7> + 2714063264U, // : Cost 3 vext3 RHS, <6,1,6,3> + 2967326006U, // : Cost 3 vzipr <2,3,u,1>, RHS + 2619213165U, // : Cost 3 vext2 <0,2,u,6>, <1,u,1,3> + 1506050150U, // : Cost 2 vext1 <4,u,6,2>, LHS + 2579792692U, // : Cost 3 vext1 <4,u,6,2>, <1,1,1,1> + 2619213416U, // : Cost 3 vext2 <0,2,u,6>, <2,2,2,2> + 2619213478U, // : Cost 3 vext2 <0,2,u,6>, <2,3,0,1> + 1506053430U, // : Cost 2 vext1 <4,u,6,2>, RHS + 2633148309U, // : Cost 3 vext2 <2,5,u,6>, <2,5,u,6> + 2619213754U, // : Cost 3 vext2 <0,2,u,6>, <2,6,3,7> + 1638330874U, // : Cost 2 vext3 RHS, <6,2,7,3> + 1638478339U, // : Cost 2 vext3 RHS, <6,2,u,3> + 2619213974U, // : Cost 3 vext2 <0,2,u,6>, <3,0,1,2> + 2803058838U, // : Cost 3 vuzpl RHS, <3,0,1,2> + 2619214134U, // : Cost 3 vext2 <0,2,u,6>, <3,2,1,0> + 2619214236U, // : Cost 3 vext2 <0,2,u,6>, <3,3,3,3> + 1564715549U, // : Cost 2 vext2 <3,4,u,6>, <3,4,u,6> + 2639121006U, // : Cost 3 vext2 <3,5,u,6>, <3,5,u,6> + 3001847012U, // : Cost 3 vzipr LHS, <4,4,6,6> + 1880329526U, // : Cost 2 vzipr LHS, RHS + 1880329527U, // : Cost 2 vzipr LHS, RHS + 2567864422U, // : Cost 3 vext1 <2,u,6,4>, LHS + 2722984555U, // : Cost 3 vext3 <6,4,1,u>, <6,4,1,u> + 2689880684U, // : Cost 3 vext3 LHS, <6,4,2,0> + 2577820162U, // : Cost 3 vext1 <4,5,6,4>, <3,4,5,6> + 1570540772U, // : Cost 2 vext2 <4,4,6,6>, <4,4,6,6> + 1545473334U, // : Cost 2 vext2 <0,2,u,6>, RHS + 1572015512U, // : Cost 2 vext2 <4,6,u,6>, <4,6,u,6> + 2960715062U, // : Cost 3 vzipr <1,2,u,4>, RHS + 1545473577U, // : Cost 2 vext2 <0,2,u,6>, RHS + 2567872614U, // : Cost 3 vext1 <2,u,6,5>, LHS + 2645757648U, // : Cost 3 vext2 <4,6,u,6>, <5,1,7,3> + 2567874490U, // : Cost 3 vext1 <2,u,6,5>, <2,6,3,7> + 2236336734U, // : Cost 3 vrev <3,5,6,u> + 94825783U, // : Cost 1 vrev RHS + 2645757956U, // : Cost 3 vext2 <4,6,u,6>, <5,5,5,5> + 2645758050U, // : Cost 3 vext2 <4,6,u,6>, <5,6,7,0> + 2824080694U, // : Cost 3 vuzpr <0,u,2,6>, RHS + 118716571U, // : Cost 1 vrev RHS + 1506082918U, // : Cost 2 vext1 <4,u,6,6>, LHS + 2579825460U, // : Cost 3 vext1 <4,u,6,6>, <1,1,1,1> + 2645758458U, // : Cost 3 vext2 <4,6,u,6>, <6,2,7,3> + 2579826838U, // : Cost 3 vext1 <4,u,6,6>, <3,0,1,2> + 1506086198U, // : Cost 2 vext1 <4,u,6,6>, RHS + 2579828432U, // : Cost 3 vext1 <4,u,6,6>, <5,1,7,3> + 296144182U, // : Cost 1 vdup2 RHS + 1638331202U, // : Cost 2 vext3 RHS, <6,6,7,7> + 296144182U, // : Cost 1 vdup2 RHS + 432349286U, // : Cost 1 vext1 RHS, LHS + 1506091828U, // : Cost 2 vext1 RHS, <1,1,1,1> + 1506092648U, // : Cost 2 vext1 RHS, <2,2,2,2> + 1506093206U, // : Cost 2 vext1 RHS, <3,0,1,2> + 432352809U, // : Cost 1 vext1 RHS, RHS + 1506094800U, // : Cost 2 vext1 RHS, <5,1,7,3> + 1506095610U, // : Cost 2 vext1 RHS, <6,2,7,3> + 1906904374U, // : Cost 2 vzipr RHS, RHS + 432355118U, // : Cost 1 vext1 RHS, LHS + 432357478U, // : Cost 1 vext1 RHS, LHS + 1545475886U, // : Cost 2 vext2 <0,2,u,6>, LHS + 1506100840U, // : Cost 2 vext1 RHS, <2,2,2,2> + 1506101398U, // : Cost 2 vext1 RHS, <3,0,1,2> + 96816682U, // : Cost 1 vrev RHS + 1545476250U, // : Cost 2 vext2 <0,2,u,6>, RHS + 296144182U, // : Cost 1 vdup2 RHS + 1880370486U, // : Cost 2 vzipr LHS, RHS + 432363310U, // : Cost 1 vext1 RHS, LHS + 1571356672U, // : Cost 2 vext2 RHS, <0,0,0,0> + 497614950U, // : Cost 1 vext2 RHS, LHS + 1571356836U, // : Cost 2 vext2 RHS, <0,2,0,2> + 2573880146U, // : Cost 3 vext1 <3,u,7,0>, <3,u,7,0> + 1571357010U, // : Cost 2 vext2 RHS, <0,4,1,5> + 1512083716U, // : Cost 2 vext1 <5,u,7,0>, <5,u,7,0> + 2621874741U, // : Cost 3 vext2 <0,6,u,7>, <0,6,u,7> + 2585826298U, // : Cost 3 vext1 <5,u,7,0>, <7,0,1,2> + 497615517U, // : Cost 1 vext2 RHS, LHS + 2573885542U, // : Cost 3 vext1 <3,u,7,1>, LHS + 1571357492U, // : Cost 2 vext2 RHS, <1,1,1,1> + 1571357590U, // : Cost 2 vext2 RHS, <1,2,3,0> + 1552114715U, // : Cost 2 vext2 <1,3,u,7>, <1,3,u,7> + 2573888822U, // : Cost 3 vext1 <3,u,7,1>, RHS + 1553441981U, // : Cost 2 vext2 <1,5,u,7>, <1,5,u,7> + 2627847438U, // : Cost 3 vext2 <1,6,u,7>, <1,6,u,7> + 2727408775U, // : Cost 3 vext3 <7,1,7,u>, <7,1,7,u> + 1555432880U, // : Cost 2 vext2 <1,u,u,7>, <1,u,u,7> + 2629838337U, // : Cost 3 vext2 <2,0,u,7>, <2,0,u,7> + 2645100035U, // : Cost 3 vext2 RHS, <2,1,0,0> + 1571358312U, // : Cost 2 vext2 RHS, <2,2,2,2> + 1571358374U, // : Cost 2 vext2 RHS, <2,3,0,1> + 2632492869U, // : Cost 3 vext2 <2,4,u,7>, <2,4,u,7> + 2633156502U, // : Cost 3 vext2 <2,5,u,7>, <2,5,u,7> + 1560078311U, // : Cost 2 vext2 <2,6,u,7>, <2,6,u,7> + 2728072408U, // : Cost 3 vext3 <7,2,7,u>, <7,2,7,u> + 1561405577U, // : Cost 2 vext2 <2,u,u,7>, <2,u,u,7> + 1571358870U, // : Cost 2 vext2 RHS, <3,0,1,2> + 2627184913U, // : Cost 3 vext2 <1,5,u,7>, <3,1,5,u> + 1571359030U, // : Cost 2 vext2 RHS, <3,2,1,0> + 1571359132U, // : Cost 2 vext2 RHS, <3,3,3,3> + 1571359234U, // : Cost 2 vext2 RHS, <3,4,5,6> + 1512108295U, // : Cost 2 vext1 <5,u,7,3>, <5,u,7,3> + 1518080992U, // : Cost 2 vext1 <6,u,7,3>, <6,u,7,3> + 2640456465U, // : Cost 3 vext2 <3,7,u,7>, <3,7,u,7> + 1571359516U, // : Cost 2 vext2 RHS, <3,u,1,0> + 1571359634U, // : Cost 2 vext2 RHS, <4,0,5,1> + 2573911067U, // : Cost 3 vext1 <3,u,7,4>, <1,3,u,7> + 2645101622U, // : Cost 3 vext2 RHS, <4,2,5,3> + 2573912918U, // : Cost 3 vext1 <3,u,7,4>, <3,u,7,4> + 1571359952U, // : Cost 2 vext2 RHS, <4,4,4,4> + 497618248U, // : Cost 1 vext2 RHS, RHS + 1571360116U, // : Cost 2 vext2 RHS, <4,6,4,6> + 2645102024U, // : Cost 3 vext2 RHS, <4,7,5,0> + 497618473U, // : Cost 1 vext2 RHS, RHS + 2645102152U, // : Cost 3 vext2 RHS, <5,0,1,2> + 1571360464U, // : Cost 2 vext2 RHS, <5,1,7,3> + 2645102334U, // : Cost 3 vext2 RHS, <5,2,3,4> + 2236410471U, // : Cost 3 vrev <3,5,7,u> + 2645102494U, // : Cost 3 vext2 RHS, <5,4,3,2> + 1571360772U, // : Cost 2 vext2 RHS, <5,5,5,5> + 1571360866U, // : Cost 2 vext2 RHS, <5,6,7,0> + 1571360936U, // : Cost 2 vext2 RHS, <5,7,5,7> + 1571361017U, // : Cost 2 vext2 RHS, <5,u,5,7> + 2645102881U, // : Cost 3 vext2 RHS, <6,0,1,2> + 2645103016U, // : Cost 3 vext2 RHS, <6,1,7,2> + 1571361274U, // : Cost 2 vext2 RHS, <6,2,7,3> + 2645103154U, // : Cost 3 vext2 RHS, <6,3,4,5> + 2645103212U, // : Cost 3 vext2 RHS, <6,4,2,0> + 1638331910U, // : Cost 2 vext3 RHS, <7,6,5,4> + 1571361592U, // : Cost 2 vext2 RHS, <6,6,6,6> + 1571361614U, // : Cost 2 vext2 RHS, <6,7,0,1> + 1571361695U, // : Cost 2 vext2 RHS, <6,u,0,1> + 1571361786U, // : Cost 2 vext2 RHS, <7,0,1,2> + 2573935616U, // : Cost 3 vext1 <3,u,7,7>, <1,3,5,7> + 2645103781U, // : Cost 3 vext2 RHS, <7,2,2,2> + 2573937497U, // : Cost 3 vext1 <3,u,7,7>, <3,u,7,7> + 1571362150U, // : Cost 2 vext2 RHS, <7,4,5,6> + 1512141067U, // : Cost 2 vext1 <5,u,7,7>, <5,u,7,7> + 1571362310U, // : Cost 2 vext2 RHS, <7,6,5,4> + 363253046U, // : Cost 1 vdup3 RHS + 363253046U, // : Cost 1 vdup3 RHS + 1571362515U, // : Cost 2 vext2 RHS, + 497620782U, // : Cost 1 vext2 RHS, LHS + 1571362675U, // : Cost 2 vext2 RHS, + 1571362748U, // : Cost 2 vext2 RHS, + 1571362879U, // : Cost 2 vext2 RHS, + 497621146U, // : Cost 1 vext2 RHS, RHS + 1571363024U, // : Cost 2 vext2 RHS, + 363253046U, // : Cost 1 vdup3 RHS + 497621349U, // : Cost 1 vext2 RHS, LHS + 135053414U, // : Cost 1 vdup0 LHS + 471081121U, // : Cost 1 vext2 LHS, LHS + 1544822948U, // : Cost 2 vext2 LHS, <0,2,0,2> + 1159424219U, // : Cost 2 vrev <3,0,u,u> + 1544823122U, // : Cost 2 vext2 LHS, <0,4,1,5> + 1512157453U, // : Cost 2 vext1 <5,u,u,0>, <5,u,u,0> + 1662220032U, // : Cost 2 vext3 RHS, + 1183315007U, // : Cost 2 vrev <7,0,u,u> + 471081629U, // : Cost 1 vext2 LHS, LHS + 68427937U, // : Cost 1 vrev LHS + 202162278U, // : Cost 1 vdup1 LHS + 537753390U, // : Cost 1 vext3 LHS, LHS + 1544823768U, // : Cost 2 vext2 LHS, <1,3,1,3> + 1494248758U, // : Cost 2 vext1 <2,u,u,1>, RHS + 1544823952U, // : Cost 2 vext2 LHS, <1,5,3,7> + 1518138343U, // : Cost 2 vext1 <6,u,u,1>, <6,u,u,1> + 1640322907U, // : Cost 2 vext3 RHS, + 537753444U, // : Cost 1 vext3 LHS, LHS + 1482309734U, // : Cost 2 vext1 <0,u,u,2>, LHS + 1611495283U, // : Cost 2 vext3 LHS, + 269271142U, // : Cost 1 vdup2 LHS + 835584U, // : Cost 0 copy LHS + 1482313014U, // : Cost 2 vext1 <0,u,u,2>, RHS + 2618566504U, // : Cost 3 vext2 LHS, <2,5,3,6> + 1544824762U, // : Cost 2 vext2 LHS, <2,6,3,7> + 1638479788U, // : Cost 2 vext3 RHS, + 835584U, // : Cost 0 copy LHS + 408576723U, // : Cost 1 vext1 LHS, LHS + 1482318644U, // : Cost 2 vext1 LHS, <1,1,1,1> + 1544825142U, // : Cost 2 vext2 LHS, <3,2,1,0> + 336380006U, // : Cost 1 vdup3 LHS + 408579382U, // : Cost 1 vext1 LHS, RHS + 1616140271U, // : Cost 2 vext3 LHS, + 1530098170U, // : Cost 2 vext1 LHS, <6,2,7,3> + 1880329544U, // : Cost 2 vzipr LHS, RHS + 408581934U, // : Cost 1 vext1 LHS, LHS + 1488298086U, // : Cost 2 vext1 <1,u,u,4>, LHS + 1488299437U, // : Cost 2 vext1 <1,u,u,4>, <1,u,u,4> + 1659271204U, // : Cost 2 vext3 LHS, + 1162078751U, // : Cost 2 vrev <3,4,u,u> + 161926454U, // : Cost 1 vdup0 RHS + 471084342U, // : Cost 1 vext2 LHS, RHS + 1571368308U, // : Cost 2 vext2 RHS, <4,6,4,6> + 1185969539U, // : Cost 2 vrev <7,4,u,u> + 471084585U, // : Cost 1 vext2 LHS, RHS + 1494278246U, // : Cost 2 vext1 <2,u,u,5>, LHS + 1571368656U, // : Cost 2 vext2 RHS, <5,1,7,3> + 1494280327U, // : Cost 2 vext1 <2,u,u,5>, <2,u,u,5> + 1616140415U, // : Cost 2 vext3 LHS, + 94973257U, // : Cost 1 vrev RHS + 229035318U, // : Cost 1 vdup1 RHS + 537753754U, // : Cost 1 vext3 LHS, RHS + 1750355254U, // : Cost 2 vuzpr LHS, RHS + 537753772U, // : Cost 1 vext3 LHS, RHS + 1482342502U, // : Cost 2 vext1 <0,u,u,6>, LHS + 2556085044U, // : Cost 3 vext1 <0,u,u,6>, <1,1,1,1> + 1571369466U, // : Cost 2 vext2 RHS, <6,2,7,3> + 1611938000U, // : Cost 2 vext3 LHS, + 1482345782U, // : Cost 2 vext1 <0,u,u,6>, RHS + 1638332639U, // : Cost 2 vext3 RHS, + 296144182U, // : Cost 1 vdup2 RHS + 27705344U, // : Cost 0 copy RHS + 27705344U, // : Cost 0 copy RHS + 432496742U, // : Cost 1 vext1 RHS, LHS + 1488324016U, // : Cost 2 vext1 <1,u,u,7>, <1,u,u,7> + 1494296713U, // : Cost 2 vext1 <2,u,u,7>, <2,u,u,7> + 1906901148U, // : Cost 2 vzipr RHS, LHS + 432500283U, // : Cost 1 vext1 RHS, RHS + 1506242256U, // : Cost 2 vext1 RHS, <5,1,7,3> + 1571370502U, // : Cost 2 vext2 RHS, <7,6,5,4> + 363253046U, // : Cost 1 vdup3 RHS + 432502574U, // : Cost 1 vext1 RHS, LHS + 73073368U, // : Cost 1 vrev LHS + 471086894U, // : Cost 1 vext2 LHS, LHS + 537753957U, // : Cost 1 vext3 LHS, LHS + 835584U, // : Cost 0 copy LHS + 408620342U, // : Cost 1 vext1 LHS, RHS + 471087258U, // : Cost 1 vext2 LHS, RHS + 537753997U, // : Cost 1 vext3 LHS, RHS + 27705344U, // : Cost 0 copy RHS + 835584U, // : Cost 0 copy LHS 0 }; + Modified: llvm/trunk/test/CodeGen/ARM/vrev.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=131488&r1=131487&r2=131488&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrev.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vrev.ll Tue May 17 15:48:40 2011 @@ -147,3 +147,20 @@ store <4 x float> %tmp8, <4 x float>* %v, align 16 ret void } + +; Test the shuffle of a 4xi16 which exposed a problem with the perfect shuffle table +; entry for vrev. +define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { +; CHECK: test_vrev64: +; CHECK: vrev64.16 +; CHECK: vext.16 +entry: + %0 = bitcast <4 x i16>* %source to <8 x i16>* + %tmp2 = load <8 x i16>* %0, align 4 + %tmp3 = extractelement <8 x i16> %tmp2, i32 6 + %tmp5 = insertelement <2 x i16> undef, i16 %tmp3, i32 0 + %tmp9 = extractelement <8 x i16> %tmp2, i32 5 + %tmp11 = insertelement <2 x i16> %tmp5, i16 %tmp9, i32 1 + store <2 x i16> %tmp11, <2 x i16>* %dst, align 4 + ret void +} Modified: llvm/trunk/utils/PerfectShuffle/PerfectShuffle.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/PerfectShuffle/PerfectShuffle.cpp?rev=131488&r1=131487&r2=131488&view=diff ============================================================================== --- llvm/trunk/utils/PerfectShuffle/PerfectShuffle.cpp (original) +++ llvm/trunk/utils/PerfectShuffle/PerfectShuffle.cpp Tue May 17 15:48:40 2011 @@ -520,7 +520,7 @@ }; struct vrev : public Operator { - vrev() : Operator(0x1032, "vrev", OP_VREV) {} + vrev() : Operator(0x3210, "vrev", OP_VREV) {} } the_vrev; template From stuart at apple.com Tue May 17 17:13:31 2011 From: stuart at apple.com (Stuart Hastings) Date: Tue, 17 May 2011 22:13:31 -0000 Subject: [llvm-commits] [llvm] r131493 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp test/CodeGen/X86/2011-05-17-pmovzxwd.ll Message-ID: <20110517221331.910192A6C12C@llvm.org> Author: stuart Date: Tue May 17 17:13:31 2011 New Revision: 131493 URL: http://llvm.org/viewvc/llvm-project?rev=131493&view=rev Log: X86 pmovsx/pmovzx ignore the upper half of their inputs. rdar://problem/6945110 Added: llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=131493&r1=131492&r2=131493&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Tue May 17 17:13:31 2011 @@ -588,6 +588,28 @@ break; } + + case Intrinsic::x86_sse41_pmovsxbw: + case Intrinsic::x86_sse41_pmovsxwd: + case Intrinsic::x86_sse41_pmovsxdq: + case Intrinsic::x86_sse41_pmovzxbw: + case Intrinsic::x86_sse41_pmovzxwd: + case Intrinsic::x86_sse41_pmovzxdq: { + unsigned VWidth = + cast(II->getArgOperand(0)->getType())->getNumElements(); + unsigned LowHalfElts = VWidth / 2; + APInt InputDemandedElts(VWidth, 0); + InputDemandedElts = InputDemandedElts.getBitsSet(VWidth, 0, LowHalfElts); + APInt UndefElts(VWidth, 0); + if (Value *TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), + InputDemandedElts, + UndefElts)) { + II->setArgOperand(0, TmpV); + return II; + } + break; + } + case Intrinsic::ppc_altivec_vperm: // Turn vperm(V1,V2,mask) -> shuffle(V1,V2,mask) if mask is a constant. if (ConstantVector *Mask = dyn_cast(II->getArgOperand(2))) { Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=131493&r1=131492&r2=131493&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Tue May 17 17:13:31 2011 @@ -867,7 +867,7 @@ if (Depth == 10) return 0; - // If multiple users are using the root value, procede with + // If multiple users are using the root value, proceed with // simplification conservatively assuming that all elements // are needed. if (!V->hasOneUse()) { Added: llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll?rev=131493&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll Tue May 17 17:13:31 2011 @@ -0,0 +1,15 @@ +; RUN: opt -instcombine -S < %s | FileCheck %s +; + +define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind { +entry: + %tmp = load <4 x i16>* %src + %tmp1 = load <8 x i16>* %foo +; CHECK: shufflevector + %tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> +; CHECK-NOT: shufflevector + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> + %0 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3) + ret <4 x i32> %0 +} +declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone From gohman at apple.com Tue May 17 17:20:36 2011 From: gohman at apple.com (Dan Gohman) Date: Tue, 17 May 2011 22:20:36 -0000 Subject: [llvm-commits] [llvm] r131495 - /llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Message-ID: <20110517222037.064402A6C12C@llvm.org> Author: djg Date: Tue May 17 17:20:36 2011 New Revision: 131495 URL: http://llvm.org/viewvc/llvm-project?rev=131495&view=rev Log: Misc. code cleanups. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=131495&r1=131494&r2=131495&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue May 17 17:20:36 2011 @@ -529,7 +529,8 @@ cast(N0.getOperand(1)), cast(N1)); return DAG.getNode(Opc, DL, VT, N0.getOperand(0), OpNode); - } else if (N0.hasOneUse()) { + } + if (N0.hasOneUse()) { // reassoc. (op (op x, c1), y) -> (op (op x, y), c1) iff x+c1 has one use SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, N0.getOperand(0), N1); @@ -546,7 +547,8 @@ cast(N1.getOperand(1)), cast(N0)); return DAG.getNode(Opc, DL, VT, N1.getOperand(0), OpNode); - } else if (N1.hasOneUse()) { + } + if (N1.hasOneUse()) { // reassoc. (op y, (op x, c1)) -> (op (op x, y), c1) iff x+c1 has one use SDValue OpNode = DAG.getNode(Opc, N0.getDebugLoc(), VT, N1.getOperand(0), N0); @@ -1566,7 +1568,8 @@ SelectionDAG &DAG, bool LegalOperations) { if (!VT.isVector()) { return DAG.getConstant(0, VT); - } else if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { + } + if (!LegalOperations || TLI.isOperationLegal(ISD::BUILD_VECTOR, VT)) { // Produce a vector of zeros. SDValue El = DAG.getConstant(0, VT.getVectorElementType()); std::vector Ops(VT.getVectorNumElements(), El); @@ -4014,7 +4017,7 @@ EVT EltVT = VT.getVectorElementType(); SmallVector OneOps(VT.getVectorNumElements(), DAG.getConstant(1, EltVT)); - if (VT.getSizeInBits() == N0VT.getSizeInBits()) { + if (VT.getSizeInBits() == N0VT.getSizeInBits()) // We know that the # elements of the results is the same as the // # elements of the compare (and the # elements of the compare result // for that matter). Check to see that they are the same size. If so, @@ -4026,25 +4029,24 @@ cast(N0.getOperand(2))->get()), DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, &OneOps[0], OneOps.size())); - } else { - // If the desired elements are smaller or larger than the source - // elements we can use a matching integer vector type and then - // truncate/sign extend - EVT MatchingElementType = - EVT::getIntegerVT(*DAG.getContext(), - N0VT.getScalarType().getSizeInBits()); - EVT MatchingVectorType = - EVT::getVectorVT(*DAG.getContext(), MatchingElementType, - N0VT.getVectorNumElements()); - SDValue VsetCC = - DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), - N0.getOperand(1), - cast(N0.getOperand(2))->get()); - return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, - DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), - DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, - &OneOps[0], OneOps.size())); - } + + // If the desired elements are smaller or larger than the source + // elements we can use a matching integer vector type and then + // truncate/sign extend + EVT MatchingElementType = + EVT::getIntegerVT(*DAG.getContext(), + N0VT.getScalarType().getSizeInBits()); + EVT MatchingVectorType = + EVT::getVectorVT(*DAG.getContext(), MatchingElementType, + N0VT.getVectorNumElements()); + SDValue VsetCC = + DAG.getVSetCC(N->getDebugLoc(), MatchingVectorType, N0.getOperand(0), + N0.getOperand(1), + cast(N0.getOperand(2))->get()); + return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, + DAG.getSExtOrTrunc(VsetCC, N->getDebugLoc(), VT), + DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT, + &OneOps[0], OneOps.size())); } // zext(setcc x,y,cc) -> select_cc x, y, 1, 0, cc @@ -7505,18 +7507,17 @@ SrcValueAlign = LD->getOriginalAlignment(); TBAAInfo = LD->getTBAAInfo(); return true; - } else if (StoreSDNode *ST = dyn_cast(N)) { + } + if (StoreSDNode *ST = dyn_cast(N)) { Ptr = ST->getBasePtr(); Size = ST->getMemoryVT().getSizeInBits() >> 3; SrcValue = ST->getSrcValue(); SrcValueOffset = ST->getSrcValueOffset(); SrcValueAlign = ST->getOriginalAlignment(); TBAAInfo = ST->getTBAAInfo(); - } else { - llvm_unreachable("FindAliasInfo expected a memory operand"); + return false; } - - return false; + llvm_unreachable("FindAliasInfo expected a memory operand"); } /// GatherAllAliases - Walk up chain skipping non-aliasing memory nodes, @@ -7629,13 +7630,13 @@ // Accumulate all the aliases to this node. GatherAllAliases(N, OldChain, Aliases); - if (Aliases.size() == 0) { - // If no operands then chain to entry token. + // If no operands then chain to entry token. + if (Aliases.size() == 0) return DAG.getEntryNode(); - } else if (Aliases.size() == 1) { - // If a single operand then chain to it. We don't need to revisit it. + + // If a single operand then chain to it. We don't need to revisit it. + if (Aliases.size() == 1) return Aliases[0]; - } // Construct a custom tailored token factor. return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other, From gohman at apple.com Tue May 17 17:22:53 2011 From: gohman at apple.com (Dan Gohman) Date: Tue, 17 May 2011 22:22:53 -0000 Subject: [llvm-commits] [llvm] r131497 - /llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Message-ID: <20110517222253.314DD2A6C12C@llvm.org> Author: djg Date: Tue May 17 17:22:52 2011 New Revision: 131497 URL: http://llvm.org/viewvc/llvm-project?rev=131497&view=rev Log: Misc. code cleanups. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=131497&r1=131496&r2=131497&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue May 17 17:22:52 2011 @@ -432,68 +432,67 @@ SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); return DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), ST->isVolatile(), ST->isNonTemporal(), Alignment); - } else { - // Do a (aligned) store to a stack slot, then copy from the stack slot - // to the final destination using (unaligned) integer loads and stores. - EVT StoredVT = ST->getMemoryVT(); - EVT RegVT = - TLI.getRegisterType(*DAG.getContext(), - EVT::getIntegerVT(*DAG.getContext(), - StoredVT.getSizeInBits())); - unsigned StoredBytes = StoredVT.getSizeInBits() / 8; - unsigned RegBytes = RegVT.getSizeInBits() / 8; - unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; - - // Make sure the stack slot is also aligned for the register type. - SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); - - // Perform the original store, only redirected to the stack slot. - SDValue Store = DAG.getTruncStore(Chain, dl, - Val, StackPtr, MachinePointerInfo(), - StoredVT, false, false, 0); - SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); - SmallVector Stores; - unsigned Offset = 0; - - // Do all but one copies using the full register width. - for (unsigned i = 1; i < NumRegs; i++) { - // Load one integer register's worth from the stack slot. - SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, - MachinePointerInfo(), - false, false, 0); - // Store it to the final location. Remember the store. - Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, - ST->getPointerInfo().getWithOffset(Offset), - ST->isVolatile(), ST->isNonTemporal(), - MinAlign(ST->getAlignment(), Offset))); - // Increment the pointers. - Offset += RegBytes; - StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, - Increment); - Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); - } + } + // Do a (aligned) store to a stack slot, then copy from the stack slot + // to the final destination using (unaligned) integer loads and stores. + EVT StoredVT = ST->getMemoryVT(); + EVT RegVT = + TLI.getRegisterType(*DAG.getContext(), + EVT::getIntegerVT(*DAG.getContext(), + StoredVT.getSizeInBits())); + unsigned StoredBytes = StoredVT.getSizeInBits() / 8; + unsigned RegBytes = RegVT.getSizeInBits() / 8; + unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; + + // Make sure the stack slot is also aligned for the register type. + SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); - // The last store may be partial. Do a truncating store. On big-endian - // machines this requires an extending load from the stack slot to ensure - // that the bits are in the right place. - EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), - 8 * (StoredBytes - Offset)); - - // Load from the stack slot. - SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, - MachinePointerInfo(), - MemVT, false, false, 0); - - Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, - ST->getPointerInfo() - .getWithOffset(Offset), - MemVT, ST->isVolatile(), - ST->isNonTemporal(), - MinAlign(ST->getAlignment(), Offset))); - // The order of the stores doesn't matter - say it with a TokenFactor. - return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], - Stores.size()); + // Perform the original store, only redirected to the stack slot. + SDValue Store = DAG.getTruncStore(Chain, dl, + Val, StackPtr, MachinePointerInfo(), + StoredVT, false, false, 0); + SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); + SmallVector Stores; + unsigned Offset = 0; + + // Do all but one copies using the full register width. + for (unsigned i = 1; i < NumRegs; i++) { + // Load one integer register's worth from the stack slot. + SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, + MachinePointerInfo(), + false, false, 0); + // Store it to the final location. Remember the store. + Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, + ST->getPointerInfo().getWithOffset(Offset), + ST->isVolatile(), ST->isNonTemporal(), + MinAlign(ST->getAlignment(), Offset))); + // Increment the pointers. + Offset += RegBytes; + StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, + Increment); + Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); } + + // The last store may be partial. Do a truncating store. On big-endian + // machines this requires an extending load from the stack slot to ensure + // that the bits are in the right place. + EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), + 8 * (StoredBytes - Offset)); + + // Load from the stack slot. + SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, + MachinePointerInfo(), + MemVT, false, false, 0); + + Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, + ST->getPointerInfo() + .getWithOffset(Offset), + MemVT, ST->isVolatile(), + ST->isNonTemporal(), + MinAlign(ST->getAlignment(), Offset))); + // The order of the stores doesn't matter - say it with a TokenFactor. + return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], + Stores.size()); } assert(ST->getMemoryVT().isInteger() && !ST->getMemoryVT().isVector() && From aggarwa4 at illinois.edu Tue May 17 17:58:03 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 17 May 2011 22:58:03 -0000 Subject: [llvm-commits] [poolalloc] r131500 - /poolalloc/trunk/lib/DSA/AllocatorIdentification.cpp Message-ID: <20110517225803.42E852A6C12C@llvm.org> Author: aggarwa4 Date: Tue May 17 17:58:03 2011 New Revision: 131500 URL: http://llvm.org/viewvc/llvm-project?rev=131500&view=rev Log: Loop Info is not required transitively. Modified: poolalloc/trunk/lib/DSA/AllocatorIdentification.cpp Modified: poolalloc/trunk/lib/DSA/AllocatorIdentification.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/AllocatorIdentification.cpp?rev=131500&r1=131499&r2=131500&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/AllocatorIdentification.cpp (original) +++ poolalloc/trunk/lib/DSA/AllocatorIdentification.cpp Tue May 17 17:58:03 2011 @@ -187,7 +187,7 @@ return false; } void AllocIdentify::getAnalysisUsage(AnalysisUsage &AU) const { - AU.addRequiredTransitive(); + AU.addRequired(); AU.setPreservesAll(); } From eli.friedman at gmail.com Tue May 17 18:02:10 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 17 May 2011 23:02:10 -0000 Subject: [llvm-commits] [llvm] r131502 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Message-ID: <20110517230210.9555E2A6C12C@llvm.org> Author: efriedma Date: Tue May 17 18:02:10 2011 New Revision: 131502 URL: http://llvm.org/viewvc/llvm-project?rev=131502&view=rev Log: Make fast-isel miss counting in -stats and -fast-isel-verbose take terminators into account; since there are many fewer isel misses with recent changes, misses caused by terminators are more significant. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=131502&r1=131501&r2=131502&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue May 17 18:02:10 2011 @@ -972,9 +972,14 @@ continue; } - // Otherwise, give up on FastISel for the rest of the block. - // For now, be a little lenient about non-branch terminators. - if (!isa(Inst) || isa(Inst)) { + if (isa(Inst) && !isa(Inst)) { + // Don't abort, and use a different message for terminator misses. + ++NumFastIselFailures; + if (EnableFastISelVerbose || EnableFastISelAbort) { + dbgs() << "FastISel missed terminator: "; + Inst->dump(); + } + } else { ++NumFastIselFailures; if (EnableFastISelVerbose || EnableFastISelAbort) { dbgs() << "FastISel miss: "; From isanbard at gmail.com Tue May 17 18:05:13 2011 From: isanbard at gmail.com (Bill Wendling) Date: Tue, 17 May 2011 23:05:13 -0000 Subject: [llvm-commits] [llvm] r131503 - in /llvm/trunk: include/llvm/LinkAllPasses.h include/llvm/Transforms/Instrumentation.h lib/Transforms/Instrumentation/GCOVProfiling.cpp Message-ID: <20110517230513.300E42A6C12C@llvm.org> Author: void Date: Tue May 17 18:05:13 2011 New Revision: 131503 URL: http://llvm.org/viewvc/llvm-project?rev=131503&view=rev Log: Conditionalize the format of the GCOV files by target type. Darwin uses the 4.2 format. Modified: llvm/trunk/include/llvm/LinkAllPasses.h llvm/trunk/include/llvm/Transforms/Instrumentation.h llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Modified: llvm/trunk/include/llvm/LinkAllPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/LinkAllPasses.h?rev=131503&r1=131502&r2=131503&view=diff ============================================================================== --- llvm/trunk/include/llvm/LinkAllPasses.h (original) +++ llvm/trunk/include/llvm/LinkAllPasses.h Tue May 17 18:05:13 2011 @@ -70,7 +70,7 @@ (void) llvm::createEdgeProfilerPass(); (void) llvm::createOptimalEdgeProfilerPass(); (void) llvm::createPathProfilerPass(); - (void) llvm::createGCOVProfilerPass(true, true); + (void) llvm::createGCOVProfilerPass(true, true, false); (void) llvm::createFunctionInliningPass(); (void) llvm::createAlwaysInlinerPass(); (void) llvm::createGlobalDCEPass(); Modified: llvm/trunk/include/llvm/Transforms/Instrumentation.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Transforms/Instrumentation.h?rev=131503&r1=131502&r2=131503&view=diff ============================================================================== --- llvm/trunk/include/llvm/Transforms/Instrumentation.h (original) +++ llvm/trunk/include/llvm/Transforms/Instrumentation.h Tue May 17 18:05:13 2011 @@ -28,7 +28,8 @@ ModulePass *createPathProfilerPass(); // Insert GCOV profiling instrumentation -ModulePass *createGCOVProfilerPass(bool EmitNotes = true, bool EmitData = true); +ModulePass *createGCOVProfilerPass(bool EmitNotes = true, bool EmitData = true, + bool Use402Format = false); } // End llvm namespace Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=131503&r1=131502&r2=131503&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original) +++ llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Tue May 17 18:05:13 2011 @@ -43,11 +43,12 @@ public: static char ID; GCOVProfiler() - : ModulePass(ID), EmitNotes(true), EmitData(true) { + : ModulePass(ID), EmitNotes(true), EmitData(true), Use402Format(false) { initializeGCOVProfilerPass(*PassRegistry::getPassRegistry()); } - GCOVProfiler(bool EmitNotes, bool EmitData) - : ModulePass(ID), EmitNotes(EmitNotes), EmitData(EmitData) { + GCOVProfiler(bool EmitNotes, bool EmitData, bool use402Format = false) + : ModulePass(ID), EmitNotes(EmitNotes), EmitData(EmitData), + Use402Format(use402Format) { assert((EmitNotes || EmitData) && "GCOVProfiler asked to do nothing?"); initializeGCOVProfilerPass(*PassRegistry::getPassRegistry()); } @@ -93,6 +94,7 @@ bool EmitNotes; bool EmitData; + bool Use402Format; Module *M; LLVMContext *Ctx; @@ -103,8 +105,9 @@ INITIALIZE_PASS(GCOVProfiler, "insert-gcov-profiling", "Insert instrumentation for GCOV profiling", false, false) -ModulePass *llvm::createGCOVProfilerPass(bool EmitNotes, bool EmitData) { - return new GCOVProfiler(EmitNotes, EmitData); +ModulePass *llvm::createGCOVProfilerPass(bool EmitNotes, bool EmitData, + bool Use402Format) { + return new GCOVProfiler(EmitNotes, EmitData, Use402Format); } static DISubprogram findSubprogram(DIScope Scope) { @@ -250,7 +253,7 @@ // object users can construct, the blocks and lines will be rooted here. class GCOVFunction : public GCOVRecord { public: - GCOVFunction(DISubprogram SP, raw_ostream *os) { + GCOVFunction(DISubprogram SP, raw_ostream *os, bool Use402Format) { this->os = os; Function *F = SP.getFunction(); @@ -261,13 +264,16 @@ ReturnBlock = new GCOVBlock(i++, os); writeBytes(FunctionTag, 4); - uint32_t BlockLen = 1 + 1 + 1 + 1 + lengthOfGCOVString(SP.getName()) + + uint32_t BlockLen = 1 + 1 + 1 + lengthOfGCOVString(SP.getName()) + 1 + lengthOfGCOVString(SP.getFilename()) + 1; + if (!Use402Format) + ++BlockLen; // For second checksum. write(BlockLen); uint32_t Ident = reinterpret_cast((MDNode*)SP); write(Ident); write(0); // checksum #1 - write(0); // checksum #2 + if (!Use402Format) + write(0); // checksum #2 writeGCOVString(SP.getName()); writeGCOVString(SP.getFilename()); write(SP.getLineNumber()); @@ -368,7 +374,10 @@ std::string ErrorInfo; out = new raw_fd_ostream(mangleName(CU, "gcno").c_str(), ErrorInfo, raw_fd_ostream::F_Binary); - out->write("oncg*404MVLL", 12); + if (!Use402Format) + out->write("oncg*404MVLL", 12); + else + out->write("oncg*402MVLL", 12); } for (DebugInfoFinder::iterator SPI = DIF.subprogram_begin(), @@ -378,7 +387,7 @@ Function *F = SP.getFunction(); if (!F) continue; - GCOVFunction Func(SP, os); + GCOVFunction Func(SP, os, Use402Format); for (Function::iterator BB = F->begin(), E = F->end(); BB != E; ++BB) { GCOVBlock &Block = Func.getBlock(BB); From zwarich at apple.com Tue May 17 18:11:12 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Tue, 17 May 2011 23:11:12 -0000 Subject: [llvm-commits] [llvm] r131506 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20110517231112.4A35D2A6C12C@llvm.org> Author: zwarich Date: Tue May 17 18:11:12 2011 New Revision: 131506 URL: http://llvm.org/viewvc/llvm-project?rev=131506&view=rev Log: Correct a minor problem with the Thumb2 LDREX and STREX instruction encodings. They were marked as taking a tGPR when in reality they take an rGPR. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=131506&r1=131505&r2=131506&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue May 17 18:11:12 2011 @@ -158,7 +158,7 @@ // def t2addrmode_reg : Operand { let PrintMethod = "printAddrMode7Operand"; - let MIOperandInfo = (ops tGPR); + let MIOperandInfo = (ops rGPR); let ParserMatchClass = MemMode7AsmOperand; } From zwarich at apple.com Tue May 17 18:26:20 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Tue, 17 May 2011 23:26:20 -0000 Subject: [llvm-commits] [llvm] r131507 - /llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Message-ID: <20110517232620.8F2A02A6C12C@llvm.org> Author: zwarich Date: Tue May 17 18:26:20 2011 New Revision: 131507 URL: http://llvm.org/viewvc/llvm-project?rev=131507&view=rev Log: Actually, the address operand of the Thumb2 LDREX / STREX instructions *can* take r13, so we can just make it a GPR. This fixes PR8825. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=131507&r1=131506&r2=131507&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue May 17 18:26:20 2011 @@ -158,7 +158,7 @@ // def t2addrmode_reg : Operand { let PrintMethod = "printAddrMode7Operand"; - let MIOperandInfo = (ops rGPR); + let MIOperandInfo = (ops GPR); let ParserMatchClass = MemMode7AsmOperand; } From dpatel at apple.com Tue May 17 18:29:06 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 17 May 2011 23:29:06 -0000 Subject: [llvm-commits] [llvm] r131508 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110517232906.2717E2A6C12C@llvm.org> Author: dpatel Date: Tue May 17 18:29:05 2011 New Revision: 131508 URL: http://llvm.org/viewvc/llvm-project?rev=131508&view=rev Log: Preseve line numbers while simplifying CFG. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131508&r1=131507&r2=131508&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Tue May 17 18:29:05 2011 @@ -773,11 +773,13 @@ assert(TD && "Cannot switch on pointer without TargetData"); CV = new PtrToIntInst(CV, TD->getIntPtrType(CV->getContext()), "magicptr", PTI); + cast(CV)->setDebugLoc(PTI->getDebugLoc()); } // Now that the successors are updated, create the new Switch instruction. SwitchInst *NewSI = SwitchInst::Create(CV, PredDefault, PredCases.size(), PTI); + NewSI->setDebugLoc(PTI->getDebugLoc()); for (unsigned i = 0, e = PredCases.size(); i != e; ++i) NewSI->addCase(PredCases[i].first, PredCases[i].second); @@ -917,9 +919,11 @@ // These values do not agree. Insert a select instruction before NT // that determines the right value. SelectInst *&SI = InsertedSelects[std::make_pair(BB1V, BB2V)]; - if (SI == 0) + if (SI == 0) { SI = SelectInst::Create(BI->getCondition(), BB1V, BB2V, BB1V->getName()+"."+BB2V->getName(), NT); + SI->setDebugLoc(BI->getDebugLoc()); + } // Make the PHI node use the select for all incoming values for BB1/BB2 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) if (PN->getIncomingBlock(i) == BB1 || PN->getIncomingBlock(i) == BB2) @@ -1084,6 +1088,7 @@ else SI = SelectInst::Create(BrCond, HInst, FalseV, HInst->getName() + "." + FalseV->getName(), BI); + SI->setDebugLoc(BI->getDebugLoc()); // Make the PHI node use the select for all incoming values for "then" and // "if" blocks. @@ -1338,7 +1343,8 @@ Value *TrueVal = PN->getIncomingValue(PN->getIncomingBlock(0) == IfFalse); Value *FalseVal = PN->getIncomingValue(PN->getIncomingBlock(0) == IfTrue); - Value *NV = SelectInst::Create(IfCond, TrueVal, FalseVal, "", InsertPt); + SelectInst *NV = SelectInst::Create(IfCond, TrueVal, FalseVal, "", InsertPt); + NV->setDebugLoc(InsertPt->getDebugLoc()); PN->replaceAllUsesWith(NV); NV->takeName(PN); PN->eraseFromParent(); @@ -1348,7 +1354,8 @@ // has been flattened. Change DomBlock to jump directly to our new block to // avoid other simplifycfg's kicking in on the diamond. TerminatorInst *OldTI = DomBlock->getTerminator(); - BranchInst::Create(BB, OldTI); + BranchInst *NewBI = BranchInst::Create(BB, OldTI); + NewBI->setDebugLoc(OldTI->getDebugLoc()); OldTI->eraseFromParent(); return true; } @@ -1601,8 +1608,9 @@ New->takeName(Cond); Cond->setName(New->getName()+".old"); - Value *NewCond = BinaryOperator::Create(Opc, PBI->getCondition(), - New, "or.cond", PBI); + Instruction *NewCond = BinaryOperator::Create(Opc, PBI->getCondition(), + New, "or.cond", PBI); + NewCond->setDebugLoc(PBI->getDebugLoc()); PBI->setCondition(NewCond); if (PBI->getSuccessor(0) == BB) { AddPredecessorToBlock(TrueDest, PredBlock, BB); @@ -2078,11 +2086,13 @@ CompVal = new PtrToIntInst(CompVal, TD->getIntPtrType(CompVal->getContext()), "magicptr", BI); + cast(CompVal)->setDebugLoc(BI->getDebugLoc()); } // Create the new switch instruction now. SwitchInst *New = SwitchInst::Create(CompVal, DefaultBB, Values.size(), BI); - + New->setDebugLoc(BI->getDebugLoc()); + // Add all of the 'cases' to the switch instruction. for (unsigned i = 0, e = Values.size(); i != e; ++i) New->addCase(Values[i], EdgeBB); From eli.friedman at gmail.com Tue May 17 19:00:10 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 00:00:10 -0000 Subject: [llvm-commits] [llvm] r131510 - /llvm/trunk/test/CodeGen/X86/fast-isel.ll Message-ID: <20110518000010.99EAA2A6C12C@llvm.org> Author: efriedma Date: Tue May 17 19:00:10 2011 New Revision: 131510 URL: http://llvm.org/viewvc/llvm-project?rev=131510&view=rev Log: Make some of the fast-isel tests actually test fast-isel (and fix test failures). Modified: llvm/trunk/test/CodeGen/X86/fast-isel.ll Modified: llvm/trunk/test/CodeGen/X86/fast-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel.ll?rev=131510&r1=131509&r2=131510&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel.ll Tue May 17 19:00:10 2011 @@ -27,7 +27,7 @@ ret i32* %t8 } -define double @bar(double* %p, double* %q) nounwind { +define void @bar(double* %p, double* %q) nounwind { entry: %r = load double* %p %s = load double* %q @@ -41,7 +41,8 @@ br label %exit exit: - ret double %t3 + store double %t3, double* %q + ret void } define i32 @cast() nounwind { @@ -68,24 +69,28 @@ ret i8* %t } -define i8 @trunc_i32_i8(i32 %x) signext nounwind { +define void @trunc_i32_i8(i32 %x, i8* %p) nounwind { %tmp1 = trunc i32 %x to i8 - ret i8 %tmp1 + store i8 %tmp1, i8* %p + ret void } -define i8 @trunc_i16_i8(i16 signext %x) signext nounwind { +define void @trunc_i16_i8(i16 signext %x, i8* %p) nounwind { %tmp1 = trunc i16 %x to i8 - ret i8 %tmp1 + store i8 %tmp1, i8* %p + ret void } -define i8 @shl_i8(i8 %a, i8 %c) nounwind { - %tmp = shl i8 %a, %c - ret i8 %tmp +define void @shl_i8(i8 %a, i8 %c, i8* %p) nounwind { + %tmp = shl i8 %a, %c + store i8 %tmp, i8* %p + ret void } -define i8 @mul_i8(i8 %a) nounwind { - %tmp = mul i8 %a, 17 - ret i8 %tmp +define void @mul_i8(i8 %a, i8* %p) nounwind { + %tmp = mul i8 %a, 17 + store i8 %tmp, i8* %p + ret void } define void @load_store_i1(i1* %p, i1* %q) nounwind { From aggarwa4 at illinois.edu Tue May 17 19:22:28 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 18 May 2011 00:22:28 -0000 Subject: [llvm-commits] [poolalloc] r131511 - /poolalloc/trunk/test/dsa/regression/2011-03-17-CBUAssert.ll Message-ID: <20110518002228.CC9892A6C12C@llvm.org> Author: aggarwa4 Date: Tue May 17 19:22:28 2011 New Revision: 131511 URL: http://llvm.org/viewvc/llvm-project?rev=131511&view=rev Log: Added a testcase for bug 9502. Added: poolalloc/trunk/test/dsa/regression/2011-03-17-CBUAssert.ll Added: poolalloc/trunk/test/dsa/regression/2011-03-17-CBUAssert.ll URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/dsa/regression/2011-03-17-CBUAssert.ll?rev=131511&view=auto ============================================================================== --- poolalloc/trunk/test/dsa/regression/2011-03-17-CBUAssert.ll (added) +++ poolalloc/trunk/test/dsa/regression/2011-03-17-CBUAssert.ll Tue May 17 19:22:28 2011 @@ -0,0 +1,22 @@ +;RUN: dsaopt %s -dsa-cbu -disable-output +; ModuleID = 'bugpoint-reduced-simplified.bc' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%struct.anon = type { %struct.node*, %struct.node* } +%struct.bitvect_t = type { i32*, i32, i32 } +%struct.node = type { i32, %union.anon, %struct.bitvect_t*, %struct.bitvect_t*, i32 } +%struct.regmatcher = type { [128 x i32], i32, i32**, i32* } +%union.anon = type { %struct.anon } + +define %struct.regmatcher* @compile(i8* %expr) nounwind { + entry: + %0 = call %struct.node* (...)* bitcast (%struct.node* ()* @end_node to %struct.node* (...)*)() nounwind ; <%struct.node*> [#uses=0] + unreachable +} + +define %struct.node* @end_node() nounwind { + entry: + ret %struct.node* undef +} + From eli.friedman at gmail.com Tue May 17 19:32:01 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 00:32:01 -0000 Subject: [llvm-commits] [llvm] r131512 - in /llvm/trunk/lib/Transforms/InstCombine: InstCombineCalls.cpp InstCombineCasts.cpp InstructionCombining.cpp Message-ID: <20110518003201.7112D2A6C12C@llvm.org> Author: efriedma Date: Tue May 17 19:32:01 2011 New Revision: 131512 URL: http://llvm.org/viewvc/llvm-project?rev=131512&view=rev Log: Use ReplaceInstUsesWith instead of replaceAllUsesWith where appropriate in instcombine. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=131512&r1=131511&r2=131512&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Tue May 17 19:32:01 2011 @@ -835,7 +835,7 @@ // If OldCall dues not return void then replaceAllUsesWith undef. // This allows ValueHandlers and custom metadata to adjust itself. if (!OldCall->getType()->isVoidTy()) - OldCall->replaceAllUsesWith(UndefValue::get(OldCall->getType())); + ReplaceInstUsesWith(*OldCall, UndefValue::get(OldCall->getType())); if (isa(OldCall)) return EraseInstFromFunction(*OldCall); @@ -857,8 +857,8 @@ // If CS does not return void then replaceAllUsesWith undef. // This allows ValueHandlers and custom metadata to adjust itself. if (!CS.getInstruction()->getType()->isVoidTy()) - CS.getInstruction()-> - replaceAllUsesWith(UndefValue::get(CS.getInstruction()->getType())); + ReplaceInstUsesWith(*CS.getInstruction(), + UndefValue::get(CS.getInstruction()->getType())); if (InvokeInst *II = dyn_cast(CS.getInstruction())) { // Don't break the CFG, insert a dummy cond branch. @@ -1145,8 +1145,8 @@ } if (!Caller->use_empty()) - Caller->replaceAllUsesWith(NV); - + ReplaceInstUsesWith(*Caller, NV); + EraseInstFromFunction(*Caller); return true; } @@ -1291,7 +1291,7 @@ cast(NewCaller)->setAttributes(NewPAL); } if (!Caller->getType()->isVoidTy()) - Caller->replaceAllUsesWith(NewCaller); + ReplaceInstUsesWith(*Caller, NewCaller); Caller->eraseFromParent(); Worklist.Remove(Caller); return 0; Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=131512&r1=131511&r2=131512&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp Tue May 17 19:32:01 2011 @@ -133,7 +133,7 @@ // New is the allocation instruction, pointer typed. AI is the original // allocation instruction, also pointer typed. Thus, cast to use is BitCast. Value *NewCast = AllocaBuilder.CreateBitCast(New, AI.getType(), "tmpcast"); - AI.replaceAllUsesWith(NewCast); + ReplaceInstUsesWith(AI, NewCast); } return ReplaceInstUsesWith(CI, New); } @@ -1228,7 +1228,7 @@ // Remove the old Call. With -fmath-errno, it won't get marked readnone. - Call->replaceAllUsesWith(UndefValue::get(Call->getType())); + ReplaceInstUsesWith(*Call, UndefValue::get(Call->getType())); EraseInstFromFunction(*Call); return ret; } Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=131512&r1=131511&r2=131512&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Tue May 17 19:32:01 2011 @@ -1261,7 +1261,7 @@ case Intrinsic::sadd_with_overflow: if (*EV.idx_begin() == 0) { // Normal result. Value *LHS = II->getArgOperand(0), *RHS = II->getArgOperand(1); - II->replaceAllUsesWith(UndefValue::get(II->getType())); + ReplaceInstUsesWith(*II, UndefValue::get(II->getType())); EraseInstFromFunction(*II); return BinaryOperator::CreateAdd(LHS, RHS); } @@ -1278,7 +1278,7 @@ case Intrinsic::ssub_with_overflow: if (*EV.idx_begin() == 0) { // Normal result. Value *LHS = II->getArgOperand(0), *RHS = II->getArgOperand(1); - II->replaceAllUsesWith(UndefValue::get(II->getType())); + ReplaceInstUsesWith(*II, UndefValue::get(II->getType())); EraseInstFromFunction(*II); return BinaryOperator::CreateSub(LHS, RHS); } @@ -1287,7 +1287,7 @@ case Intrinsic::smul_with_overflow: if (*EV.idx_begin() == 0) { // Normal result. Value *LHS = II->getArgOperand(0), *RHS = II->getArgOperand(1); - II->replaceAllUsesWith(UndefValue::get(II->getType())); + ReplaceInstUsesWith(*II, UndefValue::get(II->getType())); EraseInstFromFunction(*II); return BinaryOperator::CreateMul(LHS, RHS); } From aggarwa4 at illinois.edu Tue May 17 19:34:56 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 18 May 2011 00:34:56 -0000 Subject: [llvm-commits] [poolalloc] r131513 - /poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Message-ID: <20110518003456.BF6622A6C12C@llvm.org> Author: aggarwa4 Date: Tue May 17 19:34:56 2011 New Revision: 131513 URL: http://llvm.org/viewvc/llvm-project?rev=131513&view=rev Log: Change isIndirect. A call of a bitcasted function is not an indirect call. This is the same logic as used by Local, when visiting a CallSite. Fixes PR9502. Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Modified: poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp?rev=131513&r1=131512&r2=131513&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp (original) +++ poolalloc/trunk/lib/DSA/CompleteBottomUp.cpp Tue May 17 19:34:56 2011 @@ -120,8 +120,9 @@ // Graph, but at least one of the functions in the SCC // should have an entry in the GlobalsGraph - bool isIndirect = ((*ii).getCalledFunction() == NULL); - + Value *CalledValue = (*ii).getCalledValue()->stripPointerCasts(); + + bool isIndirect = (!isa(CalledValue)); if (isIndirect) { DSCallGraph::callee_iterator csii = callgraph.callee_begin(*ii), csee = callgraph.callee_end(*ii); From eli.friedman at gmail.com Tue May 17 20:28:27 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 01:28:27 -0000 Subject: [llvm-commits] [llvm] r131516 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/InstCombine/InstructionCombining.cpp test/Transforms/InstCombine/call.ll Message-ID: <20110518012827.9FAAB2A6C12C@llvm.org> Author: efriedma Date: Tue May 17 20:28:27 2011 New Revision: 131516 URL: http://llvm.org/viewvc/llvm-project?rev=131516&view=rev Log: Start trying to make InstCombine preserve more debug info. The idea here is to set the debug location on the IRBuilder, which will be then right location in most cases. This should magically give many transformations debug locations, and fixing places which are missing a debug location will usually just means changing the code creating it to use the IRBuilder. As an example, the change to InstCombineCalls catches a common case where a call to a bitcast of a function is rewritten. Chris, does this approach look reasonable? Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp llvm/trunk/test/Transforms/InstCombine/call.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=131516&r1=131515&r2=131516&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Tue May 17 20:28:27 2011 @@ -1106,15 +1106,15 @@ Instruction *NC; if (InvokeInst *II = dyn_cast(Caller)) { - NC = InvokeInst::Create(Callee, II->getNormalDest(), II->getUnwindDest(), - Args.begin(), Args.end(), - Caller->getName(), Caller); + NC = Builder->CreateInvoke(Callee, II->getNormalDest(), + II->getUnwindDest(), Args.begin(), Args.end()); + NC->takeName(II); cast(NC)->setCallingConv(II->getCallingConv()); cast(NC)->setAttributes(NewCallerPAL); } else { - NC = CallInst::Create(Callee, Args.begin(), Args.end(), - Caller->getName(), Caller); CallInst *CI = cast(Caller); + NC = Builder->CreateCall(Callee, Args.begin(), Args.end()); + NC->takeName(CI); if (CI->isTailCall()) cast(NC)->setTailCall(); cast(NC)->setCallingConv(CI->getCallingConv()); Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=131516&r1=131515&r2=131516&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Tue May 17 20:28:27 2011 @@ -1575,6 +1575,7 @@ // Now that we have an instruction, try combining it to simplify it. Builder->SetInsertPoint(I->getParent(), I); + Builder->SetCurrentDebugLocation(I->getDebugLoc()); #ifndef NDEBUG std::string OrigI; Modified: llvm/trunk/test/Transforms/InstCombine/call.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/call.ll?rev=131516&r1=131515&r2=131516&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/call.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/call.ll Tue May 17 20:28:27 2011 @@ -53,8 +53,8 @@ define i32 @test4() { %X = call i32 bitcast (i8 ()* @test4a to i32 ()*)( ) ; [#uses=1] ret i32 %X -; CHECK: %X1 = call i8 @test4a() -; CHECK: %tmp = zext i8 %X1 to i32 +; CHECK: %X = call i8 @test4a() +; CHECK: %tmp = zext i8 %X to i32 ; CHECK: ret i32 %tmp } @@ -77,8 +77,8 @@ define i32 @test6() { %X = call i32 bitcast (i32 (i32)* @test6a to i32 ()*)( ) ret i32 %X -; CHECK: %X1 = call i32 @test6a(i32 0) -; CHECK: ret i32 %X1 +; CHECK: %X = call i32 @test6a(i32 0) +; CHECK: ret i32 %X } From zwarich at apple.com Tue May 17 21:20:07 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 18 May 2011 02:20:07 -0000 Subject: [llvm-commits] [llvm] r131518 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20110518022007.9FBF72A6C12C@llvm.org> Author: zwarich Date: Tue May 17 21:20:07 2011 New Revision: 131518 URL: http://llvm.org/viewvc/llvm-project?rev=131518&view=rev Log: Fix more of PR8825 by correctly using rGPR registers when lowering atomic compare-and-swap intrinsics. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=131518&r1=131517&r2=131518&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue May 17 21:20:07 2011 @@ -4860,12 +4860,21 @@ unsigned ptr = MI->getOperand(1).getReg(); unsigned oldval = MI->getOperand(2).getReg(); unsigned newval = MI->getOperand(3).getReg(); - unsigned scratch = BB->getParent()->getRegInfo() - .createVirtualRegister(ARM::GPRRegisterClass); const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); DebugLoc dl = MI->getDebugLoc(); bool isThumb2 = Subtarget->isThumb2(); + MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); + unsigned scratch = + MRI.createVirtualRegister(isThumb2 ? ARM::tGPRRegisterClass + : ARM::GPRRegisterClass); + + if (isThumb2) { + MRI.constrainRegClass(dest, ARM::tGPRRegisterClass); + MRI.constrainRegClass(oldval, ARM::tGPRRegisterClass); + MRI.constrainRegClass(newval, ARM::tGPRRegisterClass); + } + unsigned ldrOpc, strOpc; switch (Size) { default: llvm_unreachable("unsupported size for AtomicCmpSwap!"); From zwarich at apple.com Tue May 17 21:29:50 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 18 May 2011 02:29:50 -0000 Subject: [llvm-commits] [llvm] r131519 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20110518022950.983492A6C12C@llvm.org> Author: zwarich Date: Tue May 17 21:29:50 2011 New Revision: 131519 URL: http://llvm.org/viewvc/llvm-project?rev=131519&view=rev Log: Fix typo. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=131519&r1=131518&r2=131519&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue May 17 21:29:50 2011 @@ -4866,13 +4866,13 @@ MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); unsigned scratch = - MRI.createVirtualRegister(isThumb2 ? ARM::tGPRRegisterClass + MRI.createVirtualRegister(isThumb2 ? ARM::rGPRRegisterClass : ARM::GPRRegisterClass); if (isThumb2) { - MRI.constrainRegClass(dest, ARM::tGPRRegisterClass); - MRI.constrainRegClass(oldval, ARM::tGPRRegisterClass); - MRI.constrainRegClass(newval, ARM::tGPRRegisterClass); + MRI.constrainRegClass(dest, ARM::rGPRRegisterClass); + MRI.constrainRegClass(oldval, ARM::rGPRRegisterClass); + MRI.constrainRegClass(newval, ARM::rGPRRegisterClass); } unsigned ldrOpc, strOpc; From stoklund at 2pi.dk Tue May 17 23:18:19 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 18 May 2011 04:18:19 -0000 Subject: [llvm-commits] [llvm] r131521 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Message-ID: <20110518041819.36FF72A6C12C@llvm.org> Author: stoklund Date: Tue May 17 23:18:19 2011 New Revision: 131521 URL: http://llvm.org/viewvc/llvm-project?rev=131521&view=rev Log: Properly shrink live ranges after deleting dead copies. Clean up after all joined copies. LiveInterval::shrinkToUses recomputes the live range from scratch instead of removing snippets. This should avoid the problem with dangling live ranges. Leave physreg identity copies alone. They can be created when joining a virtreg with a physreg. They don't affect register allocation, and they will be removed by the rewriter. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=131521&r1=131520&r2=131521&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue May 17 23:18:19 2011 @@ -1038,6 +1038,7 @@ // If they are already joined we continue. if (CP.getSrcReg() == CP.getDstReg()) { + markAsJoined(CopyMI); DEBUG(dbgs() << "\tCopy already coalesced.\n"); return false; // Not coalescable. } @@ -1696,13 +1697,11 @@ // or else the scavenger may complain. LowerSubregs will // delete them later. DoDelete = false; - + if (MI->allDefsAreDead()) { - if (li_->hasInterval(SrcReg)) { - LiveInterval &li = li_->getInterval(SrcReg); - if (!ShortenDeadCopySrcLiveRange(li, MI)) - ShortenDeadCopyLiveRange(li, MI); - } + if (TargetRegisterInfo::isVirtualRegister(SrcReg) && + li_->hasInterval(SrcReg)) + li_->shrinkToUses(&li_->getInterval(SrcReg)); DoDelete = true; } if (!DoDelete) { @@ -1754,24 +1753,6 @@ DeadDefs.clear(); } - // If the move will be an identity move delete it - if (MI->isIdentityCopy()) { - unsigned SrcReg = MI->getOperand(1).getReg(); - if (li_->hasInterval(SrcReg)) { - LiveInterval &RegInt = li_->getInterval(SrcReg); - // If def of this move instruction is dead, remove its live range - // from the destination register's live interval. - if (MI->allDefsAreDead()) { - if (!ShortenDeadCopySrcLiveRange(RegInt, MI)) - ShortenDeadCopyLiveRange(RegInt, MI); - } - } - li_->RemoveMachineInstrFromMaps(MI); - mii = mbbi->erase(mii); - ++numPeep; - continue; - } - ++mii; // Check for now unnecessary kill flags. From clattner at apple.com Tue May 17 23:33:45 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 17 May 2011 21:33:45 -0700 Subject: [llvm-commits] [llvm] r131493 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp test/CodeGen/X86/2011-05-17-pmovzxwd.ll In-Reply-To: <20110517221331.910192A6C12C@llvm.org> References: <20110517221331.910192A6C12C@llvm.org> Message-ID: <6CB7DD3F-FE71-479F-A78F-93138957D8EC@apple.com> On May 17, 2011, at 3:13 PM, Stuart Hastings wrote: > Author: stuart > Date: Tue May 17 17:13:31 2011 > New Revision: 131493 > > URL: http://llvm.org/viewvc/llvm-project?rev=131493&view=rev > Log: > X86 pmovsx/pmovzx ignore the upper half of their inputs. > rdar://problem/6945110 Hi Stuart, > + case Intrinsic::x86_sse41_pmovzxdq: { > + unsigned VWidth = > + cast(II->getArgOperand(0)->getType())->getNumElements(); > + unsigned LowHalfElts = VWidth / 2; > + APInt InputDemandedElts(VWidth, 0); > + InputDemandedElts = InputDemandedElts.getBitsSet(VWidth, 0, LowHalfElts); getBitsSet is a static method. Please do this instead: APInt InputDemandedElts(APInt::getBitsSet(VWidth, 0, LowHalfElts)); > +++ llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll Tue May 17 17:13:31 2011 > @@ -0,0 +1,15 @@ > +; RUN: opt -instcombine -S < %s | FileCheck %s > +; > + > +define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind { > +entry: > + %tmp = load <4 x i16>* %src > + %tmp1 = load <8 x i16>* %foo > +; CHECK: shufflevector > + %tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> > +; CHECK-NOT: shufflevector > + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> > + %0 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3) > + ret <4 x i32> %0 > +} > +declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone Please make the CHECK lines more specific so that it is more clear what you're doing here, add a comment explaining what is going on (to the test) and merge the test into an extant .ll file. Thanks, -Chris From clattner at apple.com Tue May 17 23:35:37 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 17 May 2011 21:35:37 -0700 Subject: [llvm-commits] [llvm] r131516 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/InstCombine/InstructionCombining.cpp test/Transforms/InstCombine/call.ll In-Reply-To: <20110518012827.9FAAB2A6C12C@llvm.org> References: <20110518012827.9FAAB2A6C12C@llvm.org> Message-ID: <92FB380D-70A0-44A2-9998-0755F7EBC775@apple.com> On May 17, 2011, at 6:28 PM, Eli Friedman wrote: > Author: efriedma > Date: Tue May 17 20:28:27 2011 > New Revision: 131516 > > URL: http://llvm.org/viewvc/llvm-project?rev=131516&view=rev > Log: > Start trying to make InstCombine preserve more debug info. The idea here is to set the debug location on the IRBuilder, which will be then right location in most cases. This should magically give many transformations debug locations, and fixing places which are missing a debug location will usually just means changing the code creating it to use the IRBuilder. > > As an example, the change to InstCombineCalls catches a common case where a call to a bitcast of a function is rewritten. > > Chris, does this approach look reasonable? Yep, this is a great approach for InstCombine, thanks Eli. Incidentally, Devang, we really shouldn't have to sprinkle setDebugLoc() through to a zillion different other transformations. Maybe they should start migrating to IRBuilder. -Chris From cdavis at mines.edu Tue May 17 23:47:22 2011 From: cdavis at mines.edu (Charles Davis) Date: Wed, 18 May 2011 04:47:22 -0000 Subject: [llvm-commits] [llvm] r131522 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/MC/MCStreamer.cpp Message-ID: <20110518044722.541712A6C12C@llvm.org> Author: cdavis Date: Tue May 17 23:47:22 2011 New Revision: 131522 URL: http://llvm.org/viewvc/llvm-project?rev=131522&view=rev Log: While thinking about how to know where the functions' boundaries are for the purposes of the Win64 EH tables, I realized we had no way to tell where the function ends. (MASM bounds functions with PROC and ENDP keywords.) Add a directive to delimit the end of the function, and rename the 'frame' directive to more accurately reflect its duality with the new directive. Modified: llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/MCStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=131522&r1=131521&r2=131522&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Tue May 17 23:47:22 2011 @@ -457,13 +457,14 @@ virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset); virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment); - virtual void EmitWin64EHFrame(MCSymbol *Symbol, MCSymbol *EHandler = 0); + virtual void EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler = 0); + virtual void EmitWin64EHEndProc(); virtual void EmitWin64EHPushReg(int64_t Register); virtual void EmitWin64EHSetFrame(int64_t Register, int64_t Offset); virtual void EmitWin64EHAllocStack(int64_t Size); virtual void EmitWin64EHSaveReg(int64_t Register, int64_t Offset); virtual void EmitWin64EHPushFrame(bool Code); - virtual void EmitWin64EHEndProlog(void); + virtual void EmitWin64EHEndProlog(); /// EmitInstruction - Emit the given @p Instruction into the current /// section. Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=131522&r1=131521&r2=131522&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Tue May 17 23:47:22 2011 @@ -310,7 +310,13 @@ CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitWin64EHFrame(MCSymbol *Symbol, MCSymbol *EHandler) +void MCStreamer::EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler) +{ + errs() << "Not implemented yet\n"; + abort(); +} + +void MCStreamer::EmitWin64EHEndProc() { errs() << "Not implemented yet\n"; abort(); @@ -346,7 +352,7 @@ abort(); } -void MCStreamer::EmitWin64EHEndProlog(void) +void MCStreamer::EmitWin64EHEndProlog() { errs() << "Not implemented yet\n"; abort(); From stoklund at 2pi.dk Tue May 17 23:51:12 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 18 May 2011 04:51:12 -0000 Subject: [llvm-commits] [llvm] r131523 - /llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Message-ID: <20110518045112.4E3F22A6C12C@llvm.org> Author: stoklund Date: Tue May 17 23:51:12 2011 New Revision: 131523 URL: http://llvm.org/viewvc/llvm-project?rev=131523&view=rev Log: Also use shrinkToUses after AdjustCopiesBackFrom(). The 'last use' may not be in the same basic block, and we still want a correct live range. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=131523&r1=131522&r2=131523&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue May 17 23:51:12 2011 @@ -272,7 +272,7 @@ // merge, find the last use and trim the live range. That will also add the // isKill marker. if (ALR->end == CopyIdx) - TrimLiveIntervalToLastUse(CopyUseIdx, CopyMI->getParent(), IntA, ALR); + li_->shrinkToUses(&IntA); ++numExtends; return true; From stoklund at 2pi.dk Tue May 17 23:51:15 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 18 May 2011 04:51:15 -0000 Subject: [llvm-commits] [llvm] r131524 - in /llvm/trunk/lib/CodeGen: SimpleRegisterCoalescing.cpp SimpleRegisterCoalescing.h Message-ID: <20110518045115.C4C1C2A6C12D@llvm.org> Author: stoklund Date: Tue May 17 23:51:15 2011 New Revision: 131524 URL: http://llvm.org/viewvc/llvm-project?rev=131524&view=rev Log: Eliminate dead dead code elimination code. Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=131524&r1=131523&r2=131524&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Tue May 17 23:51:15 2011 @@ -47,7 +47,6 @@ STATISTIC(NumReMats , "Number of instructions re-materialized"); STATISTIC(numPeep , "Number of identity moves eliminated after coalescing"); STATISTIC(numAborts , "Number of times interval joining aborted"); -STATISTIC(numDeadValNo, "Number of valno def marked dead"); char SimpleRegisterCoalescing::ID = 0; static cl::opt @@ -503,98 +502,6 @@ return true; } -/// isSameOrFallThroughBB - Return true if MBB == SuccMBB or MBB simply -/// fallthoughs to SuccMBB. -static bool isSameOrFallThroughBB(MachineBasicBlock *MBB, - MachineBasicBlock *SuccMBB, - const TargetInstrInfo *tii_) { - if (MBB == SuccMBB) - return true; - MachineBasicBlock *TBB = 0, *FBB = 0; - SmallVector Cond; - return !tii_->AnalyzeBranch(*MBB, TBB, FBB, Cond) && !TBB && !FBB && - MBB->isSuccessor(SuccMBB); -} - -/// removeRange - Wrapper for LiveInterval::removeRange. This removes a range -/// from a physical register live interval as well as from the live intervals -/// of its sub-registers. -static void removeRange(LiveInterval &li, - SlotIndex Start, SlotIndex End, - LiveIntervals *li_, const TargetRegisterInfo *tri_) { - li.removeRange(Start, End, true); - if (TargetRegisterInfo::isPhysicalRegister(li.reg)) { - for (const unsigned* SR = tri_->getSubRegisters(li.reg); *SR; ++SR) { - if (!li_->hasInterval(*SR)) - continue; - LiveInterval &sli = li_->getInterval(*SR); - SlotIndex RemoveStart = Start; - SlotIndex RemoveEnd = Start; - - while (RemoveEnd != End) { - LiveInterval::iterator LR = sli.FindLiveRangeContaining(RemoveStart); - if (LR == sli.end()) - break; - RemoveEnd = (LR->end < End) ? LR->end : End; - sli.removeRange(RemoveStart, RemoveEnd, true); - RemoveStart = RemoveEnd; - } - } - } -} - -/// TrimLiveIntervalToLastUse - If there is a last use in the same basic block -/// as the copy instruction, trim the live interval to the last use and return -/// true. -bool -SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx, - MachineBasicBlock *CopyMBB, - LiveInterval &li, - const LiveRange *LR) { - SlotIndex MBBStart = li_->getMBBStartIdx(CopyMBB); - SlotIndex LastUseIdx; - MachineOperand *LastUse = - lastRegisterUse(LR->start, CopyIdx.getPrevSlot(), li.reg, LastUseIdx); - if (LastUse) { - MachineInstr *LastUseMI = LastUse->getParent(); - if (!isSameOrFallThroughBB(LastUseMI->getParent(), CopyMBB, tii_)) { - // r1024 = op - // ... - // BB1: - // = r1024 - // - // BB2: - // r1025 = r1024 - if (MBBStart < LR->end) - removeRange(li, MBBStart, LR->end, li_, tri_); - return true; - } - - // There are uses before the copy, just shorten the live range to the end - // of last use. - LastUse->setIsKill(); - removeRange(li, LastUseIdx.getDefIndex(), LR->end, li_, tri_); - if (LastUseMI->isCopy()) { - MachineOperand &DefMO = LastUseMI->getOperand(0); - if (DefMO.getReg() == li.reg && !DefMO.getSubReg()) - DefMO.setIsDead(); - } - return true; - } - - // Is it livein? - if (LR->start <= MBBStart && LR->end > MBBStart) { - if (LR->start == li_->getZeroIndex()) { - assert(TargetRegisterInfo::isPhysicalRegister(li.reg)); - // Live-in to the function but dead. Remove it from entry live-in set. - mf_->begin()->removeLiveIn(li.reg); - } - // FIXME: Shorten intervals in BBs that reaches this BB. - } - - return false; -} - /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial /// computation, replace the copy by rematerialize the definition. bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt, @@ -781,26 +688,6 @@ return false; } -/// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy. -/// Return true if live interval is removed. -bool SimpleRegisterCoalescing::ShortenDeadCopyLiveRange(LiveInterval &li, - MachineInstr *CopyMI) { - SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI); - LiveInterval::iterator MLR = - li.FindLiveRangeContaining(CopyIdx.getDefIndex()); - if (MLR == li.end()) - return false; // Already removed by ShortenDeadCopySrcLiveRange. - SlotIndex RemoveStart = MLR->start; - SlotIndex RemoveEnd = MLR->end; - SlotIndex DefIdx = CopyIdx.getDefIndex(); - // Remove the liverange that's defined by this. - if (RemoveStart == DefIdx && RemoveEnd == DefIdx.getStoreIndex()) { - removeRange(li, RemoveStart, RemoveEnd, li_, tri_); - return removeIntervalIfEmpty(li, li_, tri_); - } - return false; -} - /// RemoveDeadDef - If a def of a live interval is now determined dead, remove /// the val# it defines. If the live interval becomes empty, remove it as well. bool SimpleRegisterCoalescing::RemoveDeadDef(LiveInterval &li, @@ -834,84 +721,6 @@ } } -/// PropagateDeadness - Propagate the dead marker to the instruction which -/// defines the val#. -static void PropagateDeadness(LiveInterval &li, MachineInstr *CopyMI, - SlotIndex &LRStart, LiveIntervals *li_, - const TargetRegisterInfo* tri_) { - MachineInstr *DefMI = - li_->getInstructionFromIndex(LRStart.getDefIndex()); - if (DefMI && DefMI != CopyMI) { - int DeadIdx = DefMI->findRegisterDefOperandIdx(li.reg); - if (DeadIdx != -1) - DefMI->getOperand(DeadIdx).setIsDead(); - else - DefMI->addOperand(MachineOperand::CreateReg(li.reg, - /*def*/true, /*implicit*/true, /*kill*/false, /*dead*/true)); - LRStart = LRStart.getNextSlot(); - } -} - -/// ShortenDeadCopySrcLiveRange - Shorten a live range as it's artificially -/// extended by a dead copy. Mark the last use (if any) of the val# as kill as -/// ends the live range there. If there isn't another use, then this live range -/// is dead. Return true if live interval is removed. -bool -SimpleRegisterCoalescing::ShortenDeadCopySrcLiveRange(LiveInterval &li, - MachineInstr *CopyMI) { - SlotIndex CopyIdx = li_->getInstructionIndex(CopyMI); - if (CopyIdx == SlotIndex()) { - // FIXME: special case: function live in. It can be a general case if the - // first instruction index starts at > 0 value. - assert(TargetRegisterInfo::isPhysicalRegister(li.reg)); - // Live-in to the function but dead. Remove it from entry live-in set. - if (mf_->begin()->isLiveIn(li.reg)) - mf_->begin()->removeLiveIn(li.reg); - if (const LiveRange *LR = li.getLiveRangeContaining(CopyIdx)) - removeRange(li, LR->start, LR->end, li_, tri_); - return removeIntervalIfEmpty(li, li_, tri_); - } - - LiveInterval::iterator LR = - li.FindLiveRangeContaining(CopyIdx.getPrevIndex().getStoreIndex()); - if (LR == li.end()) - // Livein but defined by a phi. - return false; - - SlotIndex RemoveStart = LR->start; - SlotIndex RemoveEnd = CopyIdx.getStoreIndex(); - if (LR->end > RemoveEnd) - // More uses past this copy? Nothing to do. - return false; - - // If there is a last use in the same bb, we can't remove the live range. - // Shorten the live interval and return. - MachineBasicBlock *CopyMBB = CopyMI->getParent(); - if (TrimLiveIntervalToLastUse(CopyIdx, CopyMBB, li, LR)) - return false; - - // There are other kills of the val#. Nothing to do. - if (!li.isOnlyLROfValNo(LR)) - return false; - - MachineBasicBlock *StartMBB = li_->getMBBFromIndex(RemoveStart); - if (!isSameOrFallThroughBB(StartMBB, CopyMBB, tii_)) - // If the live range starts in another mbb and the copy mbb is not a fall - // through mbb, then we can only cut the range from the beginning of the - // copy mbb. - RemoveStart = li_->getMBBStartIdx(CopyMBB).getNextIndex().getBaseIndex(); - - if (LR->valno->def == RemoveStart) { - // If the def MI defines the val# and this copy is the only kill of the - // val#, then propagate the dead marker. - PropagateDeadness(li, CopyMI, RemoveStart, li_, tri_); - ++numDeadValNo; - } - - removeRange(li, RemoveStart, RemoveEnd, li_, tri_); - return removeIntervalIfEmpty(li, li_, tri_); -} - /// shouldJoinPhys - Return true if a copy involving a physreg should be joined. /// We need to be careful about coalescing a source physical register with a /// virtual register. Once the coalescing is done, it cannot be broken and these @@ -1558,81 +1367,6 @@ } } -/// Return true if the two specified registers belong to different register -/// classes. The registers may be either phys or virt regs. -bool -SimpleRegisterCoalescing::differingRegisterClasses(unsigned RegA, - unsigned RegB) const { - // Get the register classes for the first reg. - if (TargetRegisterInfo::isPhysicalRegister(RegA)) { - assert(TargetRegisterInfo::isVirtualRegister(RegB) && - "Shouldn't consider two physregs!"); - return !mri_->getRegClass(RegB)->contains(RegA); - } - - // Compare against the regclass for the second reg. - const TargetRegisterClass *RegClassA = mri_->getRegClass(RegA); - if (TargetRegisterInfo::isVirtualRegister(RegB)) { - const TargetRegisterClass *RegClassB = mri_->getRegClass(RegB); - return RegClassA != RegClassB; - } - return !RegClassA->contains(RegB); -} - -/// lastRegisterUse - Returns the last (non-debug) use of the specific register -/// between cycles Start and End or NULL if there are no uses. -MachineOperand * -SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start, - SlotIndex End, - unsigned Reg, - SlotIndex &UseIdx) const{ - UseIdx = SlotIndex(); - if (TargetRegisterInfo::isVirtualRegister(Reg)) { - MachineOperand *LastUse = NULL; - for (MachineRegisterInfo::use_nodbg_iterator I = mri_->use_nodbg_begin(Reg), - E = mri_->use_nodbg_end(); I != E; ++I) { - MachineOperand &Use = I.getOperand(); - MachineInstr *UseMI = Use.getParent(); - if (UseMI->isIdentityCopy()) - continue; - SlotIndex Idx = li_->getInstructionIndex(UseMI); - if (Idx >= Start && Idx < End && (!UseIdx.isValid() || Idx >= UseIdx)) { - LastUse = &Use; - UseIdx = Idx.getUseIndex(); - } - } - return LastUse; - } - - SlotIndex s = Start; - SlotIndex e = End.getPrevSlot().getBaseIndex(); - while (e >= s) { - // Skip deleted instructions - MachineInstr *MI = li_->getInstructionFromIndex(e); - while (e != SlotIndex() && e.getPrevIndex() >= s && !MI) { - e = e.getPrevIndex(); - MI = li_->getInstructionFromIndex(e); - } - if (e < s || MI == NULL) - return NULL; - - // Ignore identity copies. - if (!MI->isIdentityCopy()) - for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) { - MachineOperand &Use = MI->getOperand(i); - if (Use.isReg() && Use.isUse() && Use.getReg() && - tri_->regsOverlap(Use.getReg(), Reg)) { - UseIdx = e.getUseIndex(); - return &Use; - } - } - - e = e.getPrevIndex(); - } - - return NULL; -} - void SimpleRegisterCoalescing::releaseMemory() { JoinedCopies.clear(); ReMatCopies.clear(); Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=131524&r1=131523&r2=131524&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Tue May 17 23:51:15 2011 @@ -103,10 +103,6 @@ /// use this information below to update aliases. bool JoinIntervals(CoalescerPair &CP); - /// Return true if the two specified registers belong to different register - /// classes. The registers may be either phys or virt regs. - bool differingRegisterClasses(unsigned RegA, unsigned RegB) const; - /// AdjustCopiesBackFrom - We found a non-trivially-coalescable copy. If /// the source value number is defined by a copy from the destination reg /// see if we can merge these two destination reg valno# into a single @@ -124,13 +120,6 @@ /// can transform the copy into a noop by commuting the definition. bool RemoveCopyByCommutingDef(const CoalescerPair &CP,MachineInstr *CopyMI); - /// TrimLiveIntervalToLastUse - If there is a last use in the same basic - /// block as the copy instruction, trim the ive interval to the last use - /// and return true. - bool TrimLiveIntervalToLastUse(SlotIndex CopyIdx, - MachineBasicBlock *CopyMBB, - LiveInterval &li, const LiveRange *LR); - /// ReMaterializeTrivialDef - If the source of a copy is defined by a trivial /// computation, replace the copy by rematerialize the definition. /// If PreserveSrcInt is true, make sure SrcInt is valid after the call. @@ -156,16 +145,6 @@ /// subregister. void UpdateRegDefsUses(const CoalescerPair &CP); - /// ShortenDeadCopyLiveRange - Shorten a live range defined by a dead copy. - /// Return true if live interval is removed. - bool ShortenDeadCopyLiveRange(LiveInterval &li, MachineInstr *CopyMI); - - /// ShortenDeadCopyLiveRange - Shorten a live range as it's artificially - /// extended by a dead copy. Mark the last use (if any) of the val# as kill - /// as ends the live range there. If there isn't another use, then this - /// live range is dead. Return true if live interval is removed. - bool ShortenDeadCopySrcLiveRange(LiveInterval &li, MachineInstr *CopyMI); - /// RemoveDeadDef - If a def of a live interval is now determined dead, /// remove the val# it defines. If the live interval becomes empty, remove /// it as well. @@ -175,11 +154,6 @@ /// VNInfo copy flag for DstReg and all aliases. void RemoveCopyFlag(unsigned DstReg, const MachineInstr *CopyMI); - /// lastRegisterUse - Returns the last use of the specific register between - /// cycles Start and End or NULL if there are no uses. - MachineOperand *lastRegisterUse(SlotIndex Start, SlotIndex End, - unsigned Reg, SlotIndex &LastUseIdx) const; - /// markAsJoined - Remember that CopyMI has already been joined. void markAsJoined(MachineInstr *CopyMI); }; From cdavis at mines.edu Tue May 17 23:58:05 2011 From: cdavis at mines.edu (Charles Davis) Date: Wed, 18 May 2011 04:58:05 -0000 Subject: [llvm-commits] [llvm] r131525 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp Message-ID: <20110518045805.E92FE2A6C12C@llvm.org> Author: cdavis Date: Tue May 17 23:58:05 2011 New Revision: 131525 URL: http://llvm.org/viewvc/llvm-project?rev=131525&view=rev Log: Implement the Win64 EH directive methods for the assembly language streamer. GAS has no such directives (not even mingw-w64 GAS has them), so I took creative license with their names in assembly. I prefixed them all with "w64_" to avoid namespace collisions, for example. If I discover that GAS has taken a different approach, I'll change ours to match. Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=131525&r1=131524&r2=131525&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Tue May 17 23:58:05 2011 @@ -208,6 +208,15 @@ virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset); virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment); + virtual void EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler = 0); + virtual void EmitWin64EHEndProc(); + virtual void EmitWin64EHPushReg(int64_t Register); + virtual void EmitWin64EHSetFrame(int64_t Register, int64_t Offset); + virtual void EmitWin64EHAllocStack(int64_t Size); + virtual void EmitWin64EHSaveReg(int64_t Register, int64_t Offset); + virtual void EmitWin64EHPushFrame(bool Code); + virtual void EmitWin64EHEndProlog(); + virtual void EmitFnStart(); virtual void EmitFnEnd(); virtual void EmitCantUnwind(); @@ -915,6 +924,74 @@ EmitEOL(); } +void MCAsmStreamer::EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler) +{ + //MCStreamer::EmitWin64EHStartProc(Symbol, EHandler); + + OS << ".w64_startproc " << *Symbol; + if (EHandler) + OS << ", " << *EHandler; + EmitEOL(); +} + +void MCAsmStreamer::EmitWin64EHEndProc() +{ + //MCStreamer::EmitWin64EHEndProc(); + + OS << "\t.w64_endproc"; + EmitEOL(); +} + +void MCAsmStreamer::EmitWin64EHPushReg(int64_t Register) +{ + //MCStreamer::EmitWin64EHPushReg(Register); + + OS << "\t.w64_pushreg " << Register; + EmitEOL(); +} + +void MCAsmStreamer::EmitWin64EHSetFrame(int64_t Register, int64_t Offset) +{ + //MCStreamer::EmitWin64EHSetFrame(Register, Offset); + + OS << "\t.w64_setframe " << Register << ", " << Offset; + EmitEOL(); +} + +void MCAsmStreamer::EmitWin64EHAllocStack(int64_t Size) +{ + //MCStremaer::EmitWin64EHAllocStack(Size); + + OS << "\t.w64_allocstack " << Size; + EmitEOL(); +} + +void MCAsmStreamer::EmitWin64EHSaveReg(int64_t Register, int64_t Offset) +{ + //MCStreamer::EmitWin64EHSaveReg(Register, Offset) + + OS << "\t.w64_savereg " << Register << ", " << Offset; + EmitEOL(); +} + +void MCAsmStreamer::EmitWin64EHPushFrame(bool Code) +{ + //MCStreamer::EmitWin64EHPushFrame(Code); + + OS << "\t.w64_pushframe"; + if (Code) + OS << " " << "code"; + EmitEOL(); +} + +void MCAsmStreamer::EmitWin64EHEndProlog(void) +{ + //MCStreamer::EmitWin64EHEndProlog(); + + OS << "\t.w64_endprolog"; + EmitEOL(); +} + void MCAsmStreamer::AddEncodingComment(const MCInst &Inst) { raw_ostream &OS = GetCommentOS(); SmallString<256> Code; From cdavis at mymail.mines.edu Wed May 18 00:08:15 2011 From: cdavis at mymail.mines.edu (Charles Davis) Date: Tue, 17 May 2011 23:08:15 -0600 Subject: [llvm-commits] [PATCH] Implement Win64 EH MCStreamer methods for Assembly Printing In-Reply-To: <4DD1956C.3090406@mymail.mines.edu> References: <4DD1956C.3090406@mymail.mines.edu> Message-ID: <4DD3543F.40308@mymail.mines.edu> On 5/16/11 3:21 PM, Charles Davis wrote: > Hi, > > This patch implements the Win64 EH MCStreamer methods I just added for > MCAsmStreamer. > > Note that GAS doesn't have any directives like this yet, so I've taken > license with their names. > > OK to commit? Since nobody seems interested in reviewing my patches, I've simply decided to commit anyway, subject to post-commit review. Hope that's OK. Chip From echristo at apple.com Wed May 18 00:32:40 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 17 May 2011 22:32:40 -0700 Subject: [llvm-commits] [PATCH] Implement Win64 EH MCStreamer methods for Assembly Printing In-Reply-To: <4DD3543F.40308@mymail.mines.edu> References: <4DD1956C.3090406@mymail.mines.edu> <4DD3543F.40308@mymail.mines.edu> Message-ID: On May 17, 2011, at 10:08 PM, Charles Davis wrote: > On 5/16/11 3:21 PM, Charles Davis wrote: >> Hi, >> >> This patch implements the Win64 EH MCStreamer methods I just added for >> MCAsmStreamer. >> >> Note that GAS doesn't have any directives like this yet, so I've taken >> license with their names. >> >> OK to commit? > Since nobody seems interested in reviewing my patches, I've simply > decided to commit anyway, subject to post-commit review. Hope that's OK. I took a glance as I saw them go by, looked ok to me :) -eric From baldrick at free.fr Wed May 18 00:39:08 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 18 May 2011 07:39:08 +0200 Subject: [llvm-commits] [llvm] r131525 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp In-Reply-To: <20110518045805.E92FE2A6C12C@llvm.org> References: <20110518045805.E92FE2A6C12C@llvm.org> Message-ID: <4DD35B7C.6000506@free.fr> Hi Charles, > Implement the Win64 EH directive methods for the assembly language streamer. > > GAS has no such directives (not even mingw-w64 GAS has them), so I took > creative license with their names in assembly. what about the native windows assembler (assuming there is such a thing...)? Ciao, Duncan. From tonic at nondot.org Wed May 18 01:42:21 2011 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 18 May 2011 06:42:21 -0000 Subject: [llvm-commits] [llvm] r131529 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMPerfectShuffle.h test/CodeGen/ARM/vrev.ll utils/PerfectShuffle/PerfectShuffle.cpp Message-ID: <20110518064221.701C72A6C12C@llvm.org> Author: tbrethou Date: Wed May 18 01:42:21 2011 New Revision: 131529 URL: http://llvm.org/viewvc/llvm-project?rev=131529&view=rev Log: In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. Updated test case and reverted change to the PerfectShuffle Table. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMPerfectShuffle.h llvm/trunk/test/CodeGen/ARM/vrev.ll llvm/trunk/utils/PerfectShuffle/PerfectShuffle.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=131529&r1=131528&r2=131529&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed May 18 01:42:21 2011 @@ -4182,7 +4182,15 @@ switch (OpNum) { default: llvm_unreachable("Unknown shuffle opcode!"); case OP_VREV: - return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); + // VREV divides the vector in half and swaps within the half. + if (VT.getVectorElementType() == MVT::i32) + return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); + // vrev <4 x i16> -> VREV32 + if (VT.getVectorElementType() == MVT::i16) + return DAG.getNode(ARMISD::VREV32, dl, VT, OpLHS); + // vrev <4 x i8> -> VREV16 + assert(VT.getVectorElementType() == MVT::i8); + return DAG.getNode(ARMISD::VREV16, dl, VT, OpLHS); case OP_VDUP0: case OP_VDUP1: case OP_VDUP2: Modified: llvm/trunk/lib/Target/ARM/ARMPerfectShuffle.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMPerfectShuffle.h?rev=131529&r1=131528&r2=131529&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMPerfectShuffle.h (original) +++ llvm/trunk/lib/Target/ARM/ARMPerfectShuffle.h Wed May 18 01:42:21 2011 @@ -14,21 +14,21 @@ // 31 entries have cost 0 // 242 entries have cost 1 -// 1435 entries have cost 2 -// 3712 entries have cost 3 -// 1140 entries have cost 4 -// 1 entries have cost 5 +// 1447 entries have cost 2 +// 3602 entries have cost 3 +// 1237 entries have cost 4 +// 2 entries have cost 5 // This table is 6561*4 = 26244 bytes in size. static const unsigned PerfectShuffleTable[6561+1] = { 135053414U, // <0,0,0,0>: Cost 1 vdup0 LHS 1543503974U, // <0,0,0,1>: Cost 2 vext2 <0,0,0,0>, LHS 2618572962U, // <0,0,0,2>: Cost 3 vext2 <0,2,0,0>, <0,2,0,0> - 2232510603U, // <0,0,0,3>: Cost 3 vrev <3,0,0,0> + 2568054923U, // <0,0,0,3>: Cost 3 vext1 <3,0,0,0>, <3,0,0,0> 1476398390U, // <0,0,0,4>: Cost 2 vext1 <0,0,0,0>, RHS 2550140624U, // <0,0,0,5>: Cost 3 vext1 <0,0,0,0>, <5,1,7,3> 2550141434U, // <0,0,0,6>: Cost 3 vext1 <0,0,0,0>, <6,2,7,3> - 2256401391U, // <0,0,0,7>: Cost 3 vrev <7,0,0,0> + 2591945711U, // <0,0,0,7>: Cost 3 vext1 <7,0,0,0>, <7,0,0,0> 135053414U, // <0,0,0,u>: Cost 1 vdup0 LHS 2886516736U, // <0,0,1,0>: Cost 3 vzipl LHS, <0,0,0,0> 1812775014U, // <0,0,1,1>: Cost 2 vzipl LHS, LHS @@ -50,17 +50,17 @@ 1946992796U, // <0,0,2,u>: Cost 2 vtrnl LHS, LHS 2635163787U, // <0,0,3,0>: Cost 3 vext2 <3,0,0,0>, <3,0,0,0> 2686419196U, // <0,0,3,1>: Cost 3 vext3 <0,3,1,0>, <0,3,1,0> - 2691875078U, // <0,0,3,2>: Cost 3 vext3 <1,2,3,0>, <0,3,2,1> + 2686492933U, // <0,0,3,2>: Cost 3 vext3 <0,3,2,0>, <0,3,2,0> 2617248156U, // <0,0,3,3>: Cost 3 vext2 <0,0,0,0>, <3,3,3,3> 2617248258U, // <0,0,3,4>: Cost 3 vext2 <0,0,0,0>, <3,4,5,6> 3826551298U, // <0,0,3,5>: Cost 4 vuzpl <0,2,0,2>, <3,4,5,6> 3690990200U, // <0,0,3,6>: Cost 4 vext2 <0,0,0,0>, <3,6,0,7> 3713551042U, // <0,0,3,7>: Cost 4 vext2 <3,7,0,0>, <3,7,0,0> - 2695856444U, // <0,0,3,u>: Cost 3 vext3 <1,u,3,0>, <0,3,u,1> + 2635163787U, // <0,0,3,u>: Cost 3 vext2 <3,0,0,0>, <3,0,0,0> 2617248658U, // <0,0,4,0>: Cost 3 vext2 <0,0,0,0>, <4,0,5,1> 2888450150U, // <0,0,4,1>: Cost 3 vzipl <0,4,1,5>, LHS 3021570150U, // <0,0,4,2>: Cost 3 vtrnl <0,2,4,6>, LHS - 3772326241U, // <0,0,4,3>: Cost 4 vext3 <2,3,4,0>, <0,4,3,2> + 3641829519U, // <0,0,4,3>: Cost 4 vext1 <3,0,0,4>, <3,0,0,4> 3021570252U, // <0,0,4,4>: Cost 3 vtrnl <0,2,4,6>, <0,2,4,6> 1543507254U, // <0,0,4,5>: Cost 2 vext2 <0,0,0,0>, RHS 2752810294U, // <0,0,4,6>: Cost 3 vuzpl <0,2,0,2>, RHS @@ -68,9 +68,9 @@ 1543507497U, // <0,0,4,u>: Cost 2 vext2 <0,0,0,0>, RHS 2684354972U, // <0,0,5,0>: Cost 3 vext3 <0,0,0,0>, <0,5,0,7> 2617249488U, // <0,0,5,1>: Cost 3 vext2 <0,0,0,0>, <5,1,7,3> - 3635865015U, // <0,0,5,2>: Cost 4 vext1 <2,0,0,5>, <2,0,0,5> + 3765617070U, // <0,0,5,2>: Cost 4 vext3 <1,2,3,0>, <0,5,2,7> 3635865780U, // <0,0,5,3>: Cost 4 vext1 <2,0,0,5>, <3,0,4,5> - 3761709497U, // <0,0,5,4>: Cost 4 vext3 <0,5,4,0>, <0,5,4,0> + 2617249734U, // <0,0,5,4>: Cost 3 vext2 <0,0,0,0>, <5,4,7,6> 2617249796U, // <0,0,5,5>: Cost 3 vext2 <0,0,0,0>, <5,5,5,5> 2718712274U, // <0,0,5,6>: Cost 3 vext3 <5,6,7,0>, <0,5,6,7> 2617249960U, // <0,0,5,7>: Cost 3 vext2 <0,0,0,0>, <5,7,5,7> @@ -79,20 +79,20 @@ 3963609190U, // <0,0,6,1>: Cost 4 vzipl <0,6,2,7>, LHS 2617250298U, // <0,0,6,2>: Cost 3 vext2 <0,0,0,0>, <6,2,7,3> 3796435464U, // <0,0,6,3>: Cost 4 vext3 <6,3,7,0>, <0,6,3,7> - 3773137420U, // <0,0,6,4>: Cost 4 vext3 <2,4,6,0>, <0,6,4,2> - 3785744919U, // <0,0,6,5>: Cost 4 vext3 <4,5,6,0>, <0,6,5,4> + 3659762998U, // <0,0,6,4>: Cost 4 vext1 <6,0,0,6>, RHS + 3659763810U, // <0,0,6,5>: Cost 4 vext1 <6,0,0,6>, <5,6,7,0> 2617250616U, // <0,0,6,6>: Cost 3 vext2 <0,0,0,0>, <6,6,6,6> 2657727309U, // <0,0,6,7>: Cost 3 vext2 <6,7,0,0>, <6,7,0,0> 2658390942U, // <0,0,6,u>: Cost 3 vext2 <6,u,0,0>, <6,u,0,0> 2659054575U, // <0,0,7,0>: Cost 3 vext2 <7,0,0,0>, <7,0,0,0> - 2689073728U, // <0,0,7,1>: Cost 3 vext3 <0,7,1,0>, <0,7,1,0> + 3635880854U, // <0,0,7,1>: Cost 4 vext1 <2,0,0,7>, <1,2,3,0> 3635881401U, // <0,0,7,2>: Cost 4 vext1 <2,0,0,7>, <2,0,0,7> - 3310897858U, // <0,0,7,3>: Cost 4 vrev <3,7,0,0> + 3734787298U, // <0,0,7,3>: Cost 4 vext2 <7,3,0,0>, <7,3,0,0> 2617251174U, // <0,0,7,4>: Cost 3 vext2 <0,0,0,0>, <7,4,5,6> - 3779846759U, // <0,0,7,5>: Cost 4 vext3 <3,5,7,0>, <0,7,5,3> - 2718712434U, // <0,0,7,6>: Cost 3 vext3 <5,6,7,0>, <0,7,6,5> + 3659772002U, // <0,0,7,5>: Cost 4 vext1 <6,0,0,7>, <5,6,7,0> + 3659772189U, // <0,0,7,6>: Cost 4 vext1 <6,0,0,7>, <6,0,0,7> 2617251436U, // <0,0,7,7>: Cost 3 vext2 <0,0,0,0>, <7,7,7,7> - 2720039556U, // <0,0,7,u>: Cost 3 vext3 <5,u,7,0>, <0,7,u,5> + 2659054575U, // <0,0,7,u>: Cost 3 vext2 <7,0,0,0>, <7,0,0,0> 135053414U, // <0,0,u,0>: Cost 1 vdup0 LHS 1817419878U, // <0,0,u,1>: Cost 2 vzipl LHS, LHS 1947435110U, // <0,0,u,2>: Cost 2 vtrnl LHS, LHS @@ -109,7 +109,7 @@ 2626543954U, // <0,1,0,4>: Cost 3 vext2 <1,5,0,1>, <0,4,1,5> 4094985216U, // <0,1,0,5>: Cost 4 vtrnl <0,2,0,2>, <1,3,5,7> 2592019278U, // <0,1,0,6>: Cost 3 vext1 <7,0,1,0>, <6,7,0,1> - 2256475128U, // <0,1,0,7>: Cost 3 vrev <7,0,1,0> + 2592019448U, // <0,1,0,7>: Cost 3 vext1 <7,0,1,0>, <7,0,1,0> 1557447325U, // <0,1,0,u>: Cost 2 vext2 <2,3,0,1>, LHS 1476476938U, // <0,1,1,0>: Cost 2 vext1 <0,0,1,1>, <0,0,1,1> 2886517556U, // <0,1,1,1>: Cost 3 vzipl LHS, <1,1,1,1> @@ -147,17 +147,17 @@ 2754235702U, // <0,1,4,6>: Cost 3 vuzpl <0,4,1,5>, RHS 2592052220U, // <0,1,4,7>: Cost 3 vext1 <7,0,1,4>, <7,0,1,4> 1557450281U, // <0,1,4,u>: Cost 2 vext2 <2,3,0,1>, RHS - 2217984414U, // <0,1,5,0>: Cost 3 vrev <0,5,1,0> + 3765617775U, // <0,1,5,0>: Cost 4 vext3 <1,2,3,0>, <1,5,0,1> 2647781007U, // <0,1,5,1>: Cost 3 vext2 <5,1,0,1>, <5,1,0,1> 3704934138U, // <0,1,5,2>: Cost 4 vext2 <2,3,0,1>, <5,2,3,0> 2691875984U, // <0,1,5,3>: Cost 3 vext3 <1,2,3,0>, <1,5,3,7> - 2649771906U, // <0,1,5,4>: Cost 3 vext2 <5,4,0,1>, <5,4,0,1> + 2657734598U, // <0,1,5,4>: Cost 3 vext2 <6,7,0,1>, <5,4,7,6> 2650435539U, // <0,1,5,5>: Cost 3 vext2 <5,5,0,1>, <5,5,0,1> 2651099172U, // <0,1,5,6>: Cost 3 vext2 <5,6,0,1>, <5,6,0,1> 2651762805U, // <0,1,5,7>: Cost 3 vext2 <5,7,0,1>, <5,7,0,1> 2691876029U, // <0,1,5,u>: Cost 3 vext3 <1,2,3,0>, <1,5,u,7> 2592063590U, // <0,1,6,0>: Cost 3 vext1 <7,0,1,6>, LHS - 3765322959U, // <0,1,6,1>: Cost 4 vext3 <1,1,u,0>, <1,6,1,7> + 3765617871U, // <0,1,6,1>: Cost 4 vext3 <1,2,3,0>, <1,6,1,7> 2654417337U, // <0,1,6,2>: Cost 3 vext2 <6,2,0,1>, <6,2,0,1> 3765617889U, // <0,1,6,3>: Cost 4 vext3 <1,2,3,0>, <1,6,3,7> 2592066870U, // <0,1,6,4>: Cost 3 vext1 <7,0,1,6>, RHS @@ -170,8 +170,8 @@ 2631193772U, // <0,1,7,2>: Cost 3 vext2 <2,3,0,1>, <7,2,3,0> 2661053667U, // <0,1,7,3>: Cost 3 vext2 <7,3,0,1>, <7,3,0,1> 2657736038U, // <0,1,7,4>: Cost 3 vext2 <6,7,0,1>, <7,4,5,6> - 3704935840U, // <0,1,7,5>: Cost 4 vext2 <2,3,0,1>, <7,5,3,1> - 2657736198U, // <0,1,7,6>: Cost 3 vext2 <6,7,0,1>, <7,6,5,4> + 3721524621U, // <0,1,7,5>: Cost 4 vext2 <5,1,0,1>, <7,5,1,0> + 2657736158U, // <0,1,7,6>: Cost 3 vext2 <6,7,0,1>, <7,6,1,0> 2657736300U, // <0,1,7,7>: Cost 3 vext2 <6,7,0,1>, <7,7,7,7> 2657736322U, // <0,1,7,u>: Cost 3 vext2 <6,7,0,1>, <7,u,1,2> 1494450278U, // <0,1,u,0>: Cost 2 vext1 <3,0,1,u>, LHS @@ -190,19 +190,19 @@ 2752340172U, // <0,2,0,4>: Cost 3 vuzpl LHS, <0,2,4,6> 2691876326U, // <0,2,0,5>: Cost 3 vext3 <1,2,3,0>, <2,0,5,7> 2618589695U, // <0,2,0,6>: Cost 3 vext2 <0,2,0,2>, <0,6,2,7> - 2256548865U, // <0,2,0,7>: Cost 3 vrev <7,0,2,0> + 2592093185U, // <0,2,0,7>: Cost 3 vext1 <7,0,2,0>, <7,0,2,0> 1678557340U, // <0,2,0,u>: Cost 2 vuzpl LHS, LHS - 2703672835U, // <0,2,1,0>: Cost 3 vext3 <3,2,1,0>, <2,1,0,0> + 2618589942U, // <0,2,1,0>: Cost 3 vext2 <0,2,0,2>, <1,0,3,2> 2752299828U, // <0,2,1,1>: Cost 3 vuzpl LHS, <1,1,1,1> 2886518376U, // <0,2,1,2>: Cost 3 vzipl LHS, <2,2,2,2> - 2752299926U, // <0,2,1,3>: Cost 3 vuzpl LHS, <1,2,3,0> + 2752299766U, // <0,2,1,3>: Cost 3 vuzpl LHS, <1,0,3,2> 2550295862U, // <0,2,1,4>: Cost 3 vext1 <0,0,2,1>, RHS 2752340992U, // <0,2,1,5>: Cost 3 vuzpl LHS, <1,3,5,7> 2886559674U, // <0,2,1,6>: Cost 3 vzipl LHS, <2,6,3,7> 3934208106U, // <0,2,1,7>: Cost 4 vuzpr <7,0,1,2>, <0,1,2,7> - 2752340931U, // <0,2,1,u>: Cost 3 vuzpl LHS, <1,2,u,0> + 2752340771U, // <0,2,1,u>: Cost 3 vuzpl LHS, <1,0,u,2> 1476558868U, // <0,2,2,0>: Cost 2 vext1 <0,0,2,2>, <0,0,2,2> - 2550301492U, // <0,2,2,1>: Cost 3 vext1 <0,0,2,2>, <1,1,1,1> + 2226628029U, // <0,2,2,1>: Cost 3 vrev <2,0,1,2> 2752300648U, // <0,2,2,2>: Cost 3 vuzpl LHS, <2,2,2,2> 3020736114U, // <0,2,2,3>: Cost 3 vtrnl LHS, <2,2,3,3> 1476562230U, // <0,2,2,4>: Cost 2 vext1 <0,0,2,2>, RHS @@ -212,7 +212,7 @@ 1476564782U, // <0,2,2,u>: Cost 2 vext1 <0,0,2,2>, LHS 2618591382U, // <0,2,3,0>: Cost 3 vext2 <0,2,0,2>, <3,0,1,2> 2752301206U, // <0,2,3,1>: Cost 3 vuzpl LHS, <3,0,1,2> - 2618591542U, // <0,2,3,2>: Cost 3 vext2 <0,2,0,2>, <3,2,1,0> + 3826043121U, // <0,2,3,2>: Cost 4 vuzpl LHS, <3,1,2,3> 2752301468U, // <0,2,3,3>: Cost 3 vuzpl LHS, <3,3,3,3> 2618591746U, // <0,2,3,4>: Cost 3 vext2 <0,2,0,2>, <3,4,5,6> 2752301570U, // <0,2,3,5>: Cost 3 vuzpl LHS, <3,4,5,6> @@ -221,7 +221,7 @@ 2752301269U, // <0,2,3,u>: Cost 3 vuzpl LHS, <3,0,u,2> 2562261094U, // <0,2,4,0>: Cost 3 vext1 <2,0,2,4>, LHS 4095313828U, // <0,2,4,1>: Cost 4 vtrnl <0,2,4,6>, <2,6,1,3> - 2562262472U, // <0,2,4,2>: Cost 3 vext1 <2,0,2,4>, <2,0,2,4> + 2226718152U, // <0,2,4,2>: Cost 3 vrev <2,0,2,4> 2568235169U, // <0,2,4,3>: Cost 3 vext1 <3,0,2,4>, <3,0,2,4> 2562264374U, // <0,2,4,4>: Cost 3 vext1 <2,0,2,4>, RHS 1544850742U, // <0,2,4,5>: Cost 2 vext2 <0,2,0,2>, RHS @@ -232,11 +232,11 @@ 2618592976U, // <0,2,5,1>: Cost 3 vext2 <0,2,0,2>, <5,1,7,3> 3765618528U, // <0,2,5,2>: Cost 4 vext3 <1,2,3,0>, <2,5,2,7> 3765618536U, // <0,2,5,3>: Cost 4 vext3 <1,2,3,0>, <2,5,3,6> - 3696316340U, // <0,2,5,4>: Cost 4 vext2 <0,u,0,2>, <5,4,5,6> + 2618593222U, // <0,2,5,4>: Cost 3 vext2 <0,2,0,2>, <5,4,7,6> 2752303108U, // <0,2,5,5>: Cost 3 vuzpl LHS, <5,5,5,5> 2618593378U, // <0,2,5,6>: Cost 3 vext2 <0,2,0,2>, <5,6,7,0> - 2836581686U, // <0,2,5,7>: Cost 3 vuzpr <3,0,1,2>, RHS - 2836581687U, // <0,2,5,u>: Cost 3 vuzpr <3,0,1,2>, RHS + 2824785206U, // <0,2,5,7>: Cost 3 vuzpr <1,0,3,2>, RHS + 2824785207U, // <0,2,5,u>: Cost 3 vuzpr <1,0,3,2>, RHS 2752303950U, // <0,2,6,0>: Cost 3 vuzpl LHS, <6,7,0,1> 3830690081U, // <0,2,6,1>: Cost 4 vuzpl LHS, <6,0,1,2> 2618593786U, // <0,2,6,2>: Cost 3 vext2 <0,2,0,2>, <6,2,7,3> @@ -252,7 +252,7 @@ 2701166596U, // <0,2,7,3>: Cost 3 vext3 <2,7,3,0>, <2,7,3,0> 2662389094U, // <0,2,7,4>: Cost 3 vext2 <7,5,0,2>, <7,4,5,6> 2662389126U, // <0,2,7,5>: Cost 3 vext2 <7,5,0,2>, <7,5,0,2> - 2618594822U, // <0,2,7,6>: Cost 3 vext2 <0,2,0,2>, <7,6,5,4> + 3736794583U, // <0,2,7,6>: Cost 4 vext2 <7,6,0,2>, <7,6,0,2> 2752304748U, // <0,2,7,7>: Cost 3 vuzpl LHS, <7,7,7,7> 2659070961U, // <0,2,7,u>: Cost 3 vext2 <7,0,0,2>, <7,0,0,2> 1476608026U, // <0,2,u,0>: Cost 2 vext1 <0,0,2,u>, <0,0,2,u> @@ -262,7 +262,7 @@ 1476611382U, // <0,2,u,4>: Cost 2 vext1 <0,0,2,u>, RHS 1544853658U, // <0,2,u,5>: Cost 2 vext2 <0,2,0,2>, RHS 1678563482U, // <0,2,u,6>: Cost 2 vuzpl LHS, RHS - 2836581929U, // <0,2,u,7>: Cost 3 vuzpr <3,0,1,2>, RHS + 2824785449U, // <0,2,u,7>: Cost 3 vuzpr <1,0,3,2>, RHS 1678563172U, // <0,2,u,u>: Cost 2 vuzpl LHS, LHS 2556329984U, // <0,3,0,0>: Cost 3 vext1 <1,0,3,0>, <0,0,0,0> 2686421142U, // <0,3,0,1>: Cost 3 vext3 <0,3,1,0>, <3,0,1,2> @@ -275,84 +275,84 @@ 2556335918U, // <0,3,0,u>: Cost 3 vext1 <1,0,3,0>, LHS 2886518934U, // <0,3,1,0>: Cost 3 vzipl LHS, <3,0,1,2> 2556338933U, // <0,3,1,1>: Cost 3 vext1 <1,0,3,1>, <1,0,3,1> - 2886519094U, // <0,3,1,2>: Cost 3 vzipl LHS, <3,2,1,0> + 2691877105U, // <0,3,1,2>: Cost 3 vext3 <1,2,3,0>, <3,1,2,3> 2886519196U, // <0,3,1,3>: Cost 3 vzipl LHS, <3,3,3,3> 2886519298U, // <0,3,1,4>: Cost 3 vzipl LHS, <3,4,5,6> 4095740418U, // <0,3,1,5>: Cost 4 vtrnl <0,3,1,4>, <3,4,5,6> 3659944242U, // <0,3,1,6>: Cost 4 vext1 <6,0,3,1>, <6,0,3,1> 3769600286U, // <0,3,1,7>: Cost 4 vext3 <1,u,3,0>, <3,1,7,3> 2886519582U, // <0,3,1,u>: Cost 3 vzipl LHS, <3,u,1,2> - 2556346388U, // <0,3,2,0>: Cost 3 vext1 <1,0,3,2>, <0,0,2,2> - 1148371862U, // <0,3,2,1>: Cost 2 vrev <1,2,3,0> - 2562319823U, // <0,3,2,2>: Cost 3 vext1 <2,0,3,2>, <2,0,3,2> + 1482604646U, // <0,3,2,0>: Cost 2 vext1 <1,0,3,2>, LHS + 1482605302U, // <0,3,2,1>: Cost 2 vext1 <1,0,3,2>, <1,0,3,2> + 2556348008U, // <0,3,2,2>: Cost 3 vext1 <1,0,3,2>, <2,2,2,2> 3020736924U, // <0,3,2,3>: Cost 3 vtrnl LHS, <3,3,3,3> - 2556349750U, // <0,3,2,4>: Cost 3 vext1 <1,0,3,2>, RHS + 1482607926U, // <0,3,2,4>: Cost 2 vext1 <1,0,3,2>, RHS 3020737026U, // <0,3,2,5>: Cost 3 vtrnl LHS, <3,4,5,6> - 4099123558U, // <0,3,2,6>: Cost 4 vtrnl LHS, <3,2,6,3> - 2257949868U, // <0,3,2,7>: Cost 3 vrev <7,2,3,0> - 1630447989U, // <0,3,2,u>: Cost 2 vext3 <3,2,u,0>, <3,2,u,0> - 2665711772U, // <0,3,3,0>: Cost 3 vext2 , <3,0,1,u> - 2222777319U, // <0,3,3,1>: Cost 3 vrev <1,3,3,0> - 2228750016U, // <0,3,3,2>: Cost 3 vrev <2,3,3,0> + 2598154746U, // <0,3,2,6>: Cost 3 vext1 , <6,2,7,3> + 2598155258U, // <0,3,2,7>: Cost 3 vext1 , <7,0,1,2> + 1482610478U, // <0,3,2,u>: Cost 2 vext1 <1,0,3,2>, LHS + 3692341398U, // <0,3,3,0>: Cost 4 vext2 <0,2,0,3>, <3,0,1,2> + 2635851999U, // <0,3,3,1>: Cost 3 vext2 <3,1,0,3>, <3,1,0,3> + 3636069840U, // <0,3,3,2>: Cost 4 vext1 <2,0,3,3>, <2,0,3,3> 2691877276U, // <0,3,3,3>: Cost 3 vext3 <1,2,3,0>, <3,3,3,3> 3961522690U, // <0,3,3,4>: Cost 4 vzipl <0,3,1,4>, <3,4,5,6> 3826797058U, // <0,3,3,5>: Cost 4 vuzpl <0,2,3,5>, <3,4,5,6> - 3765619124U, // <0,3,3,6>: Cost 4 vext3 <1,2,3,0>, <3,3,6,0> + 3703622282U, // <0,3,3,6>: Cost 4 vext2 <2,1,0,3>, <3,6,2,7> 3769600452U, // <0,3,3,7>: Cost 4 vext3 <1,u,3,0>, <3,3,7,7> - 2707655111U, // <0,3,3,u>: Cost 3 vext3 <3,u,1,0>, <3,3,u,1> + 2640497430U, // <0,3,3,u>: Cost 3 vext2 <3,u,0,3>, <3,u,0,3> 3962194070U, // <0,3,4,0>: Cost 4 vzipl <0,4,1,5>, <3,0,1,2> - 4095314070U, // <0,3,4,1>: Cost 4 vtrnl <0,2,4,6>, <3,0,1,2> - 2703673830U, // <0,3,4,2>: Cost 3 vext3 <3,2,1,0>, <3,4,2,5> + 2232617112U, // <0,3,4,1>: Cost 3 vrev <3,0,1,4> + 2232690849U, // <0,3,4,2>: Cost 3 vrev <3,0,2,4> 4095314332U, // <0,3,4,3>: Cost 4 vtrnl <0,2,4,6>, <3,3,3,3> 3962194434U, // <0,3,4,4>: Cost 4 vzipl <0,4,1,5>, <3,4,5,6> 2691877378U, // <0,3,4,5>: Cost 3 vext3 <1,2,3,0>, <3,4,5,6> 3826765110U, // <0,3,4,6>: Cost 4 vuzpl <0,2,3,1>, RHS 3665941518U, // <0,3,4,7>: Cost 4 vext1 <7,0,3,4>, <7,0,3,4> 2691877405U, // <0,3,4,u>: Cost 3 vext3 <1,2,3,0>, <3,4,u,6> - 3636084838U, // <0,3,5,0>: Cost 4 vext1 <2,0,3,5>, LHS - 3765619248U, // <0,3,5,1>: Cost 4 vext3 <1,2,3,0>, <3,5,1,7> - 3636086226U, // <0,3,5,2>: Cost 4 vext1 <2,0,3,5>, <2,0,3,5> + 3630112870U, // <0,3,5,0>: Cost 4 vext1 <1,0,3,5>, LHS + 3630113526U, // <0,3,5,1>: Cost 4 vext1 <1,0,3,5>, <1,0,3,2> + 4035199734U, // <0,3,5,2>: Cost 4 vzipr <1,4,0,5>, <1,0,3,2> 3769600578U, // <0,3,5,3>: Cost 4 vext3 <1,u,3,0>, <3,5,3,7> - 3636088118U, // <0,3,5,4>: Cost 4 vext1 <2,0,3,5>, RHS - 3777415764U, // <0,3,5,5>: Cost 4 vext3 <3,2,1,0>, <3,5,5,7> - 2653769826U, // <0,3,5,6>: Cost 3 vext2 <6,1,0,3>, <5,6,7,0> + 2232846516U, // <0,3,5,4>: Cost 3 vrev <3,0,4,5> + 3779037780U, // <0,3,5,5>: Cost 4 vext3 <3,4,5,0>, <3,5,5,7> + 2718714461U, // <0,3,5,6>: Cost 3 vext3 <5,6,7,0>, <3,5,6,7> 2706106975U, // <0,3,5,7>: Cost 3 vext3 <3,5,7,0>, <3,5,7,0> - 2706180712U, // <0,3,5,u>: Cost 3 vext3 <3,5,u,0>, <3,5,u,0> + 2233141464U, // <0,3,5,u>: Cost 3 vrev <3,0,u,5> 2691877496U, // <0,3,6,0>: Cost 3 vext3 <1,2,3,0>, <3,6,0,7> - 2653770090U, // <0,3,6,1>: Cost 3 vext2 <6,1,0,3>, <6,1,0,3> - 3636094419U, // <0,3,6,2>: Cost 4 vext1 <2,0,3,6>, <2,0,3,6> + 3727511914U, // <0,3,6,1>: Cost 4 vext2 <6,1,0,3>, <6,1,0,3> + 3765619338U, // <0,3,6,2>: Cost 4 vext3 <1,2,3,0>, <3,6,2,7> 3765619347U, // <0,3,6,3>: Cost 4 vext3 <1,2,3,0>, <3,6,3,7> 3765987996U, // <0,3,6,4>: Cost 4 vext3 <1,2,u,0>, <3,6,4,7> - 3322400830U, // <0,3,6,5>: Cost 4 vrev <5,6,3,0> + 3306670270U, // <0,3,6,5>: Cost 4 vrev <3,0,5,6> 3792456365U, // <0,3,6,6>: Cost 4 vext3 <5,6,7,0>, <3,6,6,6> 2706770608U, // <0,3,6,7>: Cost 3 vext3 <3,6,7,0>, <3,6,7,0> - 2653770090U, // <0,3,6,u>: Cost 3 vext2 <6,1,0,3>, <6,1,0,3> + 2706844345U, // <0,3,6,u>: Cost 3 vext3 <3,6,u,0>, <3,6,u,0> 3769600707U, // <0,3,7,0>: Cost 4 vext3 <1,u,3,0>, <3,7,0,1> - 2225431851U, // <0,3,7,1>: Cost 3 vrev <1,7,3,0> - 2231404548U, // <0,3,7,2>: Cost 3 vrev <2,7,3,0> + 2659742787U, // <0,3,7,1>: Cost 3 vext2 <7,1,0,3>, <7,1,0,3> + 3636102612U, // <0,3,7,2>: Cost 4 vext1 <2,0,3,7>, <2,0,3,7> 3769600740U, // <0,3,7,3>: Cost 4 vext3 <1,u,3,0>, <3,7,3,7> 3769600747U, // <0,3,7,4>: Cost 4 vext3 <1,u,3,0>, <3,7,4,5> 3769600758U, // <0,3,7,5>: Cost 4 vext3 <1,u,3,0>, <3,7,5,7> - 2255295336U, // <0,3,7,6>: Cost 3 vrev <6,7,3,0> + 3659993400U, // <0,3,7,6>: Cost 4 vext1 <6,0,3,7>, <6,0,3,7> 3781176065U, // <0,3,7,7>: Cost 4 vext3 <3,7,7,0>, <3,7,7,0> - 2267240730U, // <0,3,7,u>: Cost 3 vrev - 2891163798U, // <0,3,u,0>: Cost 3 vzipl LHS, <3,0,1,2> - 1152353660U, // <0,3,u,1>: Cost 2 vrev <1,u,3,0> - 2891163958U, // <0,3,u,2>: Cost 3 vzipl LHS, <3,2,1,0> + 2664388218U, // <0,3,7,u>: Cost 3 vext2 <7,u,0,3>, <7,u,0,3> + 1482653798U, // <0,3,u,0>: Cost 2 vext1 <1,0,3,u>, LHS + 1482654460U, // <0,3,u,1>: Cost 2 vext1 <1,0,3,u>, <1,0,3,u> + 2556397160U, // <0,3,u,2>: Cost 3 vext1 <1,0,3,u>, <2,2,2,2> 3021179292U, // <0,3,u,3>: Cost 3 vtrnl LHS, <3,3,3,3> - 2891164162U, // <0,3,u,4>: Cost 3 vzipl LHS, <3,4,5,6> + 1482657078U, // <0,3,u,4>: Cost 2 vext1 <1,0,3,u>, RHS 3021179394U, // <0,3,u,5>: Cost 3 vtrnl LHS, <3,4,5,6> - 2255958969U, // <0,3,u,6>: Cost 3 vrev <6,u,3,0> + 2598203898U, // <0,3,u,6>: Cost 3 vext1 , <6,2,7,3> 2708097874U, // <0,3,u,7>: Cost 3 vext3 <3,u,7,0>, <3,u,7,0> - 1634429787U, // <0,3,u,u>: Cost 2 vext3 <3,u,u,0>, <3,u,u,0> + 1482659630U, // <0,3,u,u>: Cost 2 vext1 <1,0,3,u>, LHS 2617278468U, // <0,4,0,0>: Cost 3 vext2 <0,0,0,4>, <0,0,0,4> 2618605670U, // <0,4,0,1>: Cost 3 vext2 <0,2,0,4>, LHS 2618605734U, // <0,4,0,2>: Cost 3 vext2 <0,2,0,4>, <0,2,0,4> - 3306547375U, // <0,4,0,3>: Cost 4 vrev <3,0,4,0> + 3642091695U, // <0,4,0,3>: Cost 4 vext1 <3,0,4,0>, <3,0,4,0> 2753134796U, // <0,4,0,4>: Cost 3 vuzpl <0,2,4,6>, <0,2,4,6> 2718714770U, // <0,4,0,5>: Cost 3 vext3 <5,6,7,0>, <4,0,5,1> 3021245750U, // <0,4,0,6>: Cost 3 vtrnl <0,2,0,2>, RHS - 3330438163U, // <0,4,0,7>: Cost 4 vrev <7,0,4,0> + 3665982483U, // <0,4,0,7>: Cost 4 vext1 <7,0,4,0>, <7,0,4,0> 3021245768U, // <0,4,0,u>: Cost 3 vtrnl <0,2,0,2>, RHS 2568355942U, // <0,4,1,0>: Cost 3 vext1 <3,0,4,1>, LHS 3692348212U, // <0,4,1,1>: Cost 4 vext2 <0,2,0,4>, <1,1,1,1> @@ -364,7 +364,7 @@ 2592248852U, // <0,4,1,7>: Cost 3 vext1 <7,0,4,1>, <7,0,4,1> 1812778537U, // <0,4,1,u>: Cost 2 vzipl LHS, RHS 2568364134U, // <0,4,2,0>: Cost 3 vext1 <3,0,4,2>, LHS - 2629887495U, // <0,4,2,1>: Cost 3 vext2 <2,1,0,4>, <2,1,0,4> + 2238573423U, // <0,4,2,1>: Cost 3 vrev <4,0,1,2> 3692349032U, // <0,4,2,2>: Cost 4 vext2 <0,2,0,4>, <2,2,2,2> 2631214761U, // <0,4,2,3>: Cost 3 vext2 <2,3,0,4>, <2,3,0,4> 2568367414U, // <0,4,2,4>: Cost 3 vext1 <3,0,4,2>, RHS @@ -374,13 +374,13 @@ 1946996040U, // <0,4,2,u>: Cost 2 vtrnl LHS, RHS 3692349590U, // <0,4,3,0>: Cost 4 vext2 <0,2,0,4>, <3,0,1,2> 3826878614U, // <0,4,3,1>: Cost 4 vuzpl <0,2,4,6>, <3,0,1,2> - 2228823753U, // <0,4,3,2>: Cost 3 vrev <2,3,4,0> + 3826878625U, // <0,4,3,2>: Cost 4 vuzpl <0,2,4,6>, <3,0,2,4> 3692349852U, // <0,4,3,3>: Cost 4 vext2 <0,2,0,4>, <3,3,3,3> 3692349954U, // <0,4,3,4>: Cost 4 vext2 <0,2,0,4>, <3,4,5,6> 3826878978U, // <0,4,3,5>: Cost 4 vuzpl <0,2,4,6>, <3,4,5,6> 4095200566U, // <0,4,3,6>: Cost 4 vtrnl <0,2,3,1>, RHS 3713583814U, // <0,4,3,7>: Cost 4 vext2 <3,7,0,4>, <3,7,0,4> - 2665720604U, // <0,4,3,u>: Cost 3 vext2 , <3,u,1,0> + 3692350238U, // <0,4,3,u>: Cost 4 vext2 <0,2,0,4>, <3,u,1,2> 2550464552U, // <0,4,4,0>: Cost 3 vext1 <0,0,4,4>, <0,0,4,4> 3962194914U, // <0,4,4,1>: Cost 4 vzipl <0,4,1,5>, <4,1,5,0> 3693677631U, // <0,4,4,2>: Cost 4 vext2 <0,4,0,4>, <4,2,6,3> @@ -401,8 +401,8 @@ 1618136392U, // <0,4,5,u>: Cost 2 vext3 <1,2,3,0>, RHS 2550480938U, // <0,4,6,0>: Cost 3 vext1 <0,0,4,6>, <0,0,4,6> 3826880801U, // <0,4,6,1>: Cost 4 vuzpl <0,2,4,6>, <6,0,1,2> - 2712374620U, // <0,4,6,2>: Cost 3 vext3 <4,6,2,0>, <4,6,2,0> - 3777416551U, // <0,4,6,3>: Cost 4 vext3 <3,2,1,0>, <4,6,3,2> + 2562426332U, // <0,4,6,2>: Cost 3 vext1 <2,0,4,6>, <2,0,4,6> + 3786190181U, // <0,4,6,3>: Cost 4 vext3 <4,6,3,0>, <4,6,3,0> 2718715252U, // <0,4,6,4>: Cost 3 vext3 <5,6,7,0>, <4,6,4,6> 3826881165U, // <0,4,6,5>: Cost 4 vuzpl <0,2,4,6>, <6,4,5,6> 2712669568U, // <0,4,6,6>: Cost 3 vext3 <4,6,6,0>, <4,6,6,0> @@ -414,9 +414,9 @@ 3734820070U, // <0,4,7,3>: Cost 4 vext2 <7,3,0,4>, <7,3,0,4> 3654094134U, // <0,4,7,4>: Cost 4 vext1 <5,0,4,7>, RHS 2713259464U, // <0,4,7,5>: Cost 3 vext3 <4,7,5,0>, <4,7,5,0> - 2255369073U, // <0,4,7,6>: Cost 3 vrev <6,7,4,0> + 2713333201U, // <0,4,7,6>: Cost 3 vext3 <4,7,6,0>, <4,7,6,0> 3654095866U, // <0,4,7,7>: Cost 4 vext1 <5,0,4,7>, <7,0,1,2> - 2267314467U, // <0,4,7,u>: Cost 3 vrev + 2713259464U, // <0,4,7,u>: Cost 3 vext3 <4,7,5,0>, <4,7,5,0> 2568413286U, // <0,4,u,0>: Cost 3 vext1 <3,0,4,u>, LHS 2618611502U, // <0,4,u,1>: Cost 3 vext2 <0,2,0,4>, LHS 2753140526U, // <0,4,u,2>: Cost 3 vuzpl <0,2,4,6>, LHS @@ -427,14 +427,14 @@ 2592306203U, // <0,4,u,7>: Cost 3 vext1 <7,0,4,u>, <7,0,4,u> 1947438408U, // <0,4,u,u>: Cost 2 vtrnl LHS, RHS 3630219264U, // <0,5,0,0>: Cost 4 vext1 <1,0,5,0>, <0,0,0,0> - 2637856870U, // <0,5,0,1>: Cost 3 vext2 <3,4,0,5>, LHS + 2625912934U, // <0,5,0,1>: Cost 3 vext2 <1,4,0,5>, LHS 3692355748U, // <0,5,0,2>: Cost 4 vext2 <0,2,0,5>, <0,2,0,2> 3693019384U, // <0,5,0,3>: Cost 4 vext2 <0,3,0,5>, <0,3,0,5> 3630222646U, // <0,5,0,4>: Cost 4 vext1 <1,0,5,0>, RHS - 3910568116U, // <0,5,0,5>: Cost 4 vuzpr <3,0,4,5>, <3,0,4,5> + 3699655062U, // <0,5,0,5>: Cost 4 vext2 <1,4,0,5>, <0,5,0,1> 2718715508U, // <0,5,0,6>: Cost 3 vext3 <5,6,7,0>, <5,0,6,1> 3087011126U, // <0,5,0,7>: Cost 3 vtrnr <0,0,0,0>, RHS - 2637857437U, // <0,5,0,u>: Cost 3 vext2 <3,4,0,5>, LHS + 2625913501U, // <0,5,0,u>: Cost 3 vext2 <1,4,0,5>, LHS 1500659814U, // <0,5,1,0>: Cost 2 vext1 <4,0,5,1>, LHS 2886520528U, // <0,5,1,1>: Cost 3 vzipl LHS, <5,1,7,3> 2574403176U, // <0,5,1,2>: Cost 3 vext1 <4,0,5,1>, <2,2,2,2> @@ -445,48 +445,48 @@ 2718715600U, // <0,5,1,7>: Cost 3 vext3 <5,6,7,0>, <5,1,7,3> 1500665646U, // <0,5,1,u>: Cost 2 vext1 <4,0,5,1>, LHS 2556493926U, // <0,5,2,0>: Cost 3 vext1 <1,0,5,2>, LHS - 2556494600U, // <0,5,2,1>: Cost 3 vext1 <1,0,5,2>, <1,0,5,2> + 2244546120U, // <0,5,2,1>: Cost 3 vrev <5,0,1,2> 3692357256U, // <0,5,2,2>: Cost 4 vext2 <0,2,0,5>, <2,2,5,7> 2568439994U, // <0,5,2,3>: Cost 3 vext1 <3,0,5,2>, <3,0,5,2> 2556497206U, // <0,5,2,4>: Cost 3 vext1 <1,0,5,2>, RHS 3020738564U, // <0,5,2,5>: Cost 3 vtrnl LHS, <5,5,5,5> 4027877161U, // <0,5,2,6>: Cost 4 vzipr <0,2,0,2>, <2,4,5,6> - 3105017142U, // <0,5,2,7>: Cost 3 vtrnr <3,0,1,2>, RHS - 3105017143U, // <0,5,2,u>: Cost 3 vtrnr <3,0,1,2>, RHS - 2637858966U, // <0,5,3,0>: Cost 3 vext2 <3,4,0,5>, <3,0,1,2> - 3711600902U, // <0,5,3,1>: Cost 4 vext2 <3,4,0,5>, <3,1,4,6> - 3302639314U, // <0,5,3,2>: Cost 4 vrev <2,3,5,0> - 3308612011U, // <0,5,3,3>: Cost 4 vrev <3,3,5,0> + 3093220662U, // <0,5,2,7>: Cost 3 vtrnr <1,0,3,2>, RHS + 3093220663U, // <0,5,2,u>: Cost 3 vtrnr <1,0,3,2>, RHS + 3699656854U, // <0,5,3,0>: Cost 4 vext2 <1,4,0,5>, <3,0,1,2> + 3699656927U, // <0,5,3,1>: Cost 4 vext2 <1,4,0,5>, <3,1,0,3> + 3699657006U, // <0,5,3,2>: Cost 4 vext2 <1,4,0,5>, <3,2,0,1> + 3699657116U, // <0,5,3,3>: Cost 4 vext2 <1,4,0,5>, <3,3,3,3> 2637859284U, // <0,5,3,4>: Cost 3 vext2 <3,4,0,5>, <3,4,0,5> - 3320557405U, // <0,5,3,5>: Cost 4 vrev <5,3,5,0> - 3790393190U, // <0,5,3,6>: Cost 4 vext3 <5,3,6,0>, <5,3,6,0> + 3790319453U, // <0,5,3,5>: Cost 4 vext3 <5,3,5,0>, <5,3,5,0> + 3699657354U, // <0,5,3,6>: Cost 4 vext2 <1,4,0,5>, <3,6,2,7> 2716725103U, // <0,5,3,7>: Cost 3 vext3 <5,3,7,0>, <5,3,7,0> - 2640513816U, // <0,5,3,u>: Cost 3 vext2 <3,u,0,5>, <3,u,0,5> + 2716798840U, // <0,5,3,u>: Cost 3 vext3 <5,3,u,0>, <5,3,u,0> 2661747602U, // <0,5,4,0>: Cost 3 vext2 <7,4,0,5>, <4,0,5,1> - 3962195634U, // <0,5,4,1>: Cost 4 vzipl <0,4,1,5>, <5,1,4,0> - 3303302947U, // <0,5,4,2>: Cost 4 vrev <2,4,5,0> - 2235533820U, // <0,5,4,3>: Cost 3 vrev <3,4,5,0> + 3630252810U, // <0,5,4,1>: Cost 4 vext1 <1,0,5,4>, <1,0,5,4> + 3636225507U, // <0,5,4,2>: Cost 4 vext1 <2,0,5,4>, <2,0,5,4> + 3716910172U, // <0,5,4,3>: Cost 4 vext2 <4,3,0,5>, <4,3,0,5> 3962195892U, // <0,5,4,4>: Cost 4 vzipl <0,4,1,5>, <5,4,5,6> - 2637860150U, // <0,5,4,5>: Cost 3 vext2 <3,4,0,5>, RHS - 3791056823U, // <0,5,4,6>: Cost 4 vext3 <5,4,6,0>, <5,4,6,0> - 2259424608U, // <0,5,4,7>: Cost 3 vrev <7,4,5,0> - 2637860393U, // <0,5,4,u>: Cost 3 vext2 <3,4,0,5>, RHS + 2625916214U, // <0,5,4,5>: Cost 3 vext2 <1,4,0,5>, RHS + 3718901071U, // <0,5,4,6>: Cost 4 vext2 <4,6,0,5>, <4,6,0,5> + 2718715846U, // <0,5,4,7>: Cost 3 vext3 <5,6,7,0>, <5,4,7,6> + 2625916457U, // <0,5,4,u>: Cost 3 vext2 <1,4,0,5>, RHS 3791278034U, // <0,5,5,0>: Cost 4 vext3 <5,5,0,0>, <5,5,0,0> - 3297993883U, // <0,5,5,1>: Cost 4 vrev <1,5,5,0> - 3303966580U, // <0,5,5,2>: Cost 4 vrev <2,5,5,0> - 3309939277U, // <0,5,5,3>: Cost 4 vrev <3,5,5,0> - 2242170150U, // <0,5,5,4>: Cost 3 vrev <4,5,5,0> + 3791351771U, // <0,5,5,1>: Cost 4 vext3 <5,5,1,0>, <5,5,1,0> + 3318386260U, // <0,5,5,2>: Cost 4 vrev <5,0,2,5> + 3791499245U, // <0,5,5,3>: Cost 4 vext3 <5,5,3,0>, <5,5,3,0> + 3318533734U, // <0,5,5,4>: Cost 4 vrev <5,0,4,5> 2718715908U, // <0,5,5,5>: Cost 3 vext3 <5,6,7,0>, <5,5,5,5> 2657767522U, // <0,5,5,6>: Cost 3 vext2 <6,7,0,5>, <5,6,7,0> 2718715928U, // <0,5,5,7>: Cost 3 vext3 <5,6,7,0>, <5,5,7,7> 2718715937U, // <0,5,5,u>: Cost 3 vext3 <5,6,7,0>, <5,5,u,7> 2592358502U, // <0,5,6,0>: Cost 3 vext1 <7,0,5,6>, LHS - 3792457779U, // <0,5,6,1>: Cost 4 vext3 <5,6,7,0>, <5,6,1,7> + 3792015404U, // <0,5,6,1>: Cost 4 vext3 <5,6,1,0>, <5,6,1,0> 3731509754U, // <0,5,6,2>: Cost 4 vext2 <6,7,0,5>, <6,2,7,3> - 3781398594U, // <0,5,6,3>: Cost 4 vext3 <3,u,1,0>, <5,6,3,4> + 3785748546U, // <0,5,6,3>: Cost 4 vext3 <4,5,6,0>, <5,6,3,4> 2592361782U, // <0,5,6,4>: Cost 3 vext1 <7,0,5,6>, RHS 2592362594U, // <0,5,6,5>: Cost 3 vext1 <7,0,5,6>, <5,6,7,0> - 3781398624U, // <0,5,6,6>: Cost 4 vext3 <3,u,1,0>, <5,6,6,7> + 3785748576U, // <0,5,6,6>: Cost 4 vext3 <4,5,6,0>, <5,6,6,7> 1644974178U, // <0,5,6,7>: Cost 2 vext3 <5,6,7,0>, <5,6,7,0> 1645047915U, // <0,5,6,u>: Cost 2 vext3 <5,6,u,0>, <5,6,u,0> 2562506854U, // <0,5,7,0>: Cost 3 vext1 <2,0,5,7>, LHS @@ -499,11 +499,11 @@ 2719379635U, // <0,5,7,7>: Cost 3 vext3 <5,7,7,0>, <5,7,7,0> 2562512686U, // <0,5,7,u>: Cost 3 vext1 <2,0,5,7>, LHS 1500717158U, // <0,5,u,0>: Cost 2 vext1 <4,0,5,u>, LHS - 2562515862U, // <0,5,u,1>: Cost 3 vext1 <2,0,5,u>, <1,2,3,0> - 2562516455U, // <0,5,u,2>: Cost 3 vext1 <2,0,5,u>, <2,0,5,u> - 2238188352U, // <0,5,u,3>: Cost 3 vrev <3,u,5,0> + 2625918766U, // <0,5,u,1>: Cost 3 vext2 <1,4,0,5>, LHS + 2719674583U, // <0,5,u,2>: Cost 3 vext3 <5,u,2,0>, <5,u,2,0> + 2568489152U, // <0,5,u,3>: Cost 3 vext1 <3,0,5,u>, <3,0,5,u> 1500720025U, // <0,5,u,4>: Cost 2 vext1 <4,0,5,u>, <4,0,5,u> - 2637863066U, // <0,5,u,5>: Cost 3 vext2 <3,4,0,5>, RHS + 2625919130U, // <0,5,u,5>: Cost 3 vext2 <1,4,0,5>, RHS 2586407243U, // <0,5,u,6>: Cost 3 vext1 <6,0,5,u>, <6,0,5,u> 1646301444U, // <0,5,u,7>: Cost 2 vext3 <5,u,7,0>, <5,u,7,0> 1646375181U, // <0,5,u,u>: Cost 2 vext3 <5,u,u,0>, <5,u,u,0> @@ -526,7 +526,7 @@ 2966736182U, // <0,6,1,7>: Cost 3 vzipr <2,3,0,1>, RHS 2966736183U, // <0,6,1,u>: Cost 3 vzipr <2,3,0,1>, RHS 1500741734U, // <0,6,2,0>: Cost 2 vext1 <4,0,6,2>, LHS - 2574484276U, // <0,6,2,1>: Cost 3 vext1 <4,0,6,2>, <1,1,1,1> + 2250518817U, // <0,6,2,1>: Cost 3 vrev <6,0,1,2> 2574485096U, // <0,6,2,2>: Cost 3 vext1 <4,0,6,2>, <2,2,2,2> 2631894694U, // <0,6,2,3>: Cost 3 vext2 <2,4,0,6>, <2,3,0,1> 1500744604U, // <0,6,2,4>: Cost 2 vext1 <4,0,6,2>, <4,0,6,2> @@ -536,97 +536,97 @@ 1500747566U, // <0,6,2,u>: Cost 2 vext1 <4,0,6,2>, LHS 3693693078U, // <0,6,3,0>: Cost 4 vext2 <0,4,0,6>, <3,0,1,2> 3705637136U, // <0,6,3,1>: Cost 4 vext2 <2,4,0,6>, <3,1,5,7> - 3693693238U, // <0,6,3,2>: Cost 4 vext2 <0,4,0,6>, <3,2,1,0> + 3705637192U, // <0,6,3,2>: Cost 4 vext2 <2,4,0,6>, <3,2,3,0> 3693693340U, // <0,6,3,3>: Cost 4 vext2 <0,4,0,6>, <3,3,3,3> 2637867477U, // <0,6,3,4>: Cost 3 vext2 <3,4,0,6>, <3,4,0,6> 3705637424U, // <0,6,3,5>: Cost 4 vext2 <2,4,0,6>, <3,5,1,7> 3666154056U, // <0,6,3,6>: Cost 4 vext1 <7,0,6,3>, <6,3,7,0> 2722697800U, // <0,6,3,7>: Cost 3 vext3 <6,3,7,0>, <6,3,7,0> 2722771537U, // <0,6,3,u>: Cost 3 vext3 <6,3,u,0>, <6,3,u,0> - 2661755804U, // <0,6,4,0>: Cost 3 vext2 <7,4,0,6>, <4,0,6,2> + 2562556006U, // <0,6,4,0>: Cost 3 vext1 <2,0,6,4>, LHS 4095316257U, // <0,6,4,1>: Cost 4 vtrnl <0,2,4,6>, <6,0,1,2> - 2229634860U, // <0,6,4,2>: Cost 3 vrev <2,4,6,0> - 3309349381U, // <0,6,4,3>: Cost 4 vrev <3,4,6,0> - 3636301110U, // <0,6,4,4>: Cost 4 vext1 <2,0,6,4>, RHS + 2562557420U, // <0,6,4,2>: Cost 3 vext1 <2,0,6,4>, <2,0,6,4> + 3636299926U, // <0,6,4,3>: Cost 4 vext1 <2,0,6,4>, <3,0,1,2> + 2562559286U, // <0,6,4,4>: Cost 3 vext1 <2,0,6,4>, RHS 2619952438U, // <0,6,4,5>: Cost 3 vext2 <0,4,0,6>, RHS - 2253525648U, // <0,6,4,6>: Cost 3 vrev <6,4,6,0> + 2723287696U, // <0,6,4,6>: Cost 3 vext3 <6,4,6,0>, <6,4,6,0> 4027895094U, // <0,6,4,7>: Cost 4 vzipr <0,2,0,4>, RHS 2619952681U, // <0,6,4,u>: Cost 3 vext2 <0,4,0,6>, RHS 2718716594U, // <0,6,5,0>: Cost 3 vext3 <5,6,7,0>, <6,5,0,7> - 3735498448U, // <0,6,5,1>: Cost 4 vext2 <7,4,0,6>, <5,1,7,3> + 3648250774U, // <0,6,5,1>: Cost 4 vext1 <4,0,6,5>, <1,2,3,0> 3792458436U, // <0,6,5,2>: Cost 4 vext3 <5,6,7,0>, <6,5,2,7> - 3672140290U, // <0,6,5,3>: Cost 4 vext1 , <3,4,5,6> - 2242243887U, // <0,6,5,4>: Cost 3 vrev <4,5,6,0> + 3705638767U, // <0,6,5,3>: Cost 5 vext2 <2,4,0,6>, <5,3,7,0> + 3648252831U, // <0,6,5,4>: Cost 4 vext1 <4,0,6,5>, <4,0,6,5> 3797619416U, // <0,6,5,5>: Cost 4 vext3 <6,5,5,0>, <6,5,5,0> 3792458472U, // <0,6,5,6>: Cost 4 vext3 <5,6,7,0>, <6,5,6,7> - 3777417969U, // <0,6,5,7>: Cost 4 vext3 <3,2,1,0>, <6,5,7,7> - 2266134675U, // <0,6,5,u>: Cost 3 vrev + 4035202358U, // <0,6,5,7>: Cost 4 vzipr <1,4,0,5>, RHS + 2718716594U, // <0,6,5,u>: Cost 3 vext3 <5,6,7,0>, <6,5,0,7> 3786412796U, // <0,6,6,0>: Cost 4 vext3 <4,6,6,0>, <6,6,0,0> 3792458504U, // <0,6,6,1>: Cost 4 vext3 <5,6,7,0>, <6,6,1,3> - 3304703950U, // <0,6,6,2>: Cost 4 vrev <2,6,6,0> + 3728200126U, // <0,6,6,2>: Cost 4 vext2 <6,2,0,6>, <6,2,0,6> 3798135575U, // <0,6,6,3>: Cost 4 vext3 <6,6,3,0>, <6,6,3,0> - 2242907520U, // <0,6,6,4>: Cost 3 vrev <4,6,6,0> - 3322622041U, // <0,6,6,5>: Cost 4 vrev <5,6,6,0> + 3786412836U, // <0,6,6,4>: Cost 4 vext3 <4,6,6,0>, <6,6,4,4> + 3792458543U, // <0,6,6,5>: Cost 4 vext3 <5,6,7,0>, <6,6,5,6> 2718716728U, // <0,6,6,6>: Cost 3 vext3 <5,6,7,0>, <6,6,6,6> 2718716738U, // <0,6,6,7>: Cost 3 vext3 <5,6,7,0>, <6,6,7,7> 2718716747U, // <0,6,6,u>: Cost 3 vext3 <5,6,7,0>, <6,6,u,7> 2718716750U, // <0,6,7,0>: Cost 3 vext3 <5,6,7,0>, <6,7,0,1> - 2691879768U, // <0,6,7,1>: Cost 3 vext3 <1,2,3,0>, <6,7,1,2> + 2724909910U, // <0,6,7,1>: Cost 3 vext3 <6,7,1,0>, <6,7,1,0> 3636323823U, // <0,6,7,2>: Cost 4 vext1 <2,0,6,7>, <2,0,6,7> 2725057384U, // <0,6,7,3>: Cost 3 vext3 <6,7,3,0>, <6,7,3,0> 2718716790U, // <0,6,7,4>: Cost 3 vext3 <5,6,7,0>, <6,7,4,5> 2718716800U, // <0,6,7,5>: Cost 3 vext3 <5,6,7,0>, <6,7,5,6> - 3777418122U, // <0,6,7,6>: Cost 4 vext3 <3,2,1,0>, <6,7,6,7> + 3792458629U, // <0,6,7,6>: Cost 4 vext3 <5,6,7,0>, <6,7,6,2> 2725352332U, // <0,6,7,7>: Cost 3 vext3 <6,7,7,0>, <6,7,7,0> 2718716822U, // <0,6,7,u>: Cost 3 vext3 <5,6,7,0>, <6,7,u,1> 1500790886U, // <0,6,u,0>: Cost 2 vext1 <4,0,6,u>, LHS 2619954990U, // <0,6,u,1>: Cost 3 vext2 <0,4,0,6>, LHS - 2232289392U, // <0,6,u,2>: Cost 3 vrev <2,u,6,0> + 2562590192U, // <0,6,u,2>: Cost 3 vext1 <2,0,6,u>, <2,0,6,u> 2725721017U, // <0,6,u,3>: Cost 3 vext3 <6,u,3,0>, <6,u,3,0> 1500793762U, // <0,6,u,4>: Cost 2 vext1 <4,0,6,u>, <4,0,6,u> 2619955354U, // <0,6,u,5>: Cost 3 vext2 <0,4,0,6>, RHS - 2256180180U, // <0,6,u,6>: Cost 3 vrev <6,u,6,0> + 2725942228U, // <0,6,u,6>: Cost 3 vext3 <6,u,6,0>, <6,u,6,0> 2954186038U, // <0,6,u,7>: Cost 3 vzipr <0,2,0,u>, RHS 1500796718U, // <0,6,u,u>: Cost 2 vext1 <4,0,6,u>, LHS - 2726163439U, // <0,7,0,0>: Cost 3 vext3 <7,0,0,0>, <7,0,0,0> + 2256401391U, // <0,7,0,0>: Cost 3 vrev <7,0,0,0> 2632564838U, // <0,7,0,1>: Cost 3 vext2 <2,5,0,7>, LHS - 2726310913U, // <0,7,0,2>: Cost 3 vext3 <7,0,2,0>, <7,0,2,0> + 2256548865U, // <0,7,0,2>: Cost 3 vrev <7,0,2,0> 3700998396U, // <0,7,0,3>: Cost 4 vext2 <1,6,0,7>, <0,3,1,0> 2718716952U, // <0,7,0,4>: Cost 3 vext3 <5,6,7,0>, <7,0,4,5> 2718716962U, // <0,7,0,5>: Cost 3 vext3 <5,6,7,0>, <7,0,5,6> 2621284845U, // <0,7,0,6>: Cost 3 vext2 <0,6,0,7>, <0,6,0,7> 3904685542U, // <0,7,0,7>: Cost 4 vuzpr <2,0,5,7>, <2,0,5,7> 2632565405U, // <0,7,0,u>: Cost 3 vext2 <2,5,0,7>, LHS - 2886521850U, // <0,7,1,0>: Cost 3 vzipl LHS, <7,0,1,2> - 3700335474U, // <0,7,1,1>: Cost 4 vext2 <1,5,0,7>, <1,1,u,0> + 2256409584U, // <0,7,1,0>: Cost 3 vrev <7,0,0,1> + 3706307380U, // <0,7,1,1>: Cost 4 vext2 <2,5,0,7>, <1,1,1,1> 2632565654U, // <0,7,1,2>: Cost 3 vext2 <2,5,0,7>, <1,2,3,0> 3769603168U, // <0,7,1,3>: Cost 4 vext3 <1,u,3,0>, <7,1,3,5> - 2886522214U, // <0,7,1,4>: Cost 3 vzipl LHS, <7,4,5,6> - 3700335733U, // <0,7,1,5>: Cost 4 vext2 <1,5,0,7>, <1,5,0,7> - 2886522374U, // <0,7,1,6>: Cost 3 vzipl LHS, <7,6,5,4> + 2256704532U, // <0,7,1,4>: Cost 3 vrev <7,0,4,1> + 3769603184U, // <0,7,1,5>: Cost 4 vext3 <1,u,3,0>, <7,1,5,3> + 3700999366U, // <0,7,1,6>: Cost 4 vext2 <1,6,0,7>, <1,6,0,7> 2886522476U, // <0,7,1,7>: Cost 3 vzipl LHS, <7,7,7,7> - 2668397948U, // <0,7,1,u>: Cost 3 vext2 , <1,u,3,0> + 2256999480U, // <0,7,1,u>: Cost 3 vrev <7,0,u,1> 2586501222U, // <0,7,2,0>: Cost 3 vext1 <6,0,7,2>, LHS - 3020739578U, // <0,7,2,1>: Cost 3 vtrnl LHS, <7,0,1,2> + 1182749690U, // <0,7,2,1>: Cost 2 vrev <7,0,1,2> 3636356595U, // <0,7,2,2>: Cost 4 vext1 <2,0,7,2>, <2,0,7,2> 2727711916U, // <0,7,2,3>: Cost 3 vext3 <7,2,3,0>, <7,2,3,0> 2586504502U, // <0,7,2,4>: Cost 3 vext1 <6,0,7,2>, RHS 2632566606U, // <0,7,2,5>: Cost 3 vext2 <2,5,0,7>, <2,5,0,7> 2586505559U, // <0,7,2,6>: Cost 3 vext1 <6,0,7,2>, <6,0,7,2> 3020740204U, // <0,7,2,7>: Cost 3 vtrnl LHS, <7,7,7,7> - 2634557505U, // <0,7,2,u>: Cost 3 vext2 <2,u,0,7>, <2,u,0,7> + 1183265849U, // <0,7,2,u>: Cost 2 vrev <7,0,u,2> 3701000342U, // <0,7,3,0>: Cost 4 vext2 <1,6,0,7>, <3,0,1,2> 3706308849U, // <0,7,3,1>: Cost 4 vext2 <2,5,0,7>, <3,1,2,3> - 2627258678U, // <0,7,3,2>: Cost 3 vext2 <1,6,0,7>, <3,2,1,0> + 3330315268U, // <0,7,3,2>: Cost 4 vrev <7,0,2,3> 3706309020U, // <0,7,3,3>: Cost 4 vext2 <2,5,0,7>, <3,3,3,3> 3706309122U, // <0,7,3,4>: Cost 4 vext2 <2,5,0,7>, <3,4,5,6> - 2246963055U, // <0,7,3,5>: Cost 3 vrev <5,3,7,0> + 3712281127U, // <0,7,3,5>: Cost 4 vext2 <3,5,0,7>, <3,5,0,7> 2639202936U, // <0,7,3,6>: Cost 3 vext2 <3,6,0,7>, <3,6,0,7> - 3332650273U, // <0,7,3,7>: Cost 4 vrev <7,3,7,0> + 3802412321U, // <0,7,3,7>: Cost 4 vext3 <7,3,7,0>, <7,3,7,0> 2640530202U, // <0,7,3,u>: Cost 3 vext2 <3,u,0,7>, <3,u,0,7> 3654287462U, // <0,7,4,0>: Cost 4 vext1 <5,0,7,4>, LHS - 3654288278U, // <0,7,4,1>: Cost 4 vext1 <5,0,7,4>, <1,2,3,0> - 3654289230U, // <0,7,4,2>: Cost 4 vext1 <5,0,7,4>, <2,5,0,7> + 2256507900U, // <0,7,4,1>: Cost 3 vrev <7,0,1,4> + 2256581637U, // <0,7,4,2>: Cost 3 vrev <7,0,2,4> 3660262008U, // <0,7,4,3>: Cost 4 vext1 <6,0,7,4>, <3,6,0,7> 3786413405U, // <0,7,4,4>: Cost 4 vext3 <4,6,6,0>, <7,4,4,6> 2632568118U, // <0,7,4,5>: Cost 3 vext2 <2,5,0,7>, RHS @@ -634,75 +634,75 @@ 3787003255U, // <0,7,4,7>: Cost 4 vext3 <4,7,5,0>, <7,4,7,5> 2632568361U, // <0,7,4,u>: Cost 3 vext2 <2,5,0,7>, RHS 3706310268U, // <0,7,5,0>: Cost 4 vext2 <2,5,0,7>, <5,0,7,0> - 3298141357U, // <0,7,5,1>: Cost 4 vrev <1,5,7,0> - 3304114054U, // <0,7,5,2>: Cost 4 vrev <2,5,7,0> - 2236344927U, // <0,7,5,3>: Cost 3 vrev <3,5,7,0> - 3316059448U, // <0,7,5,4>: Cost 4 vrev <4,5,7,0> + 3792459156U, // <0,7,5,1>: Cost 4 vext3 <5,6,7,0>, <7,5,1,7> + 3330331654U, // <0,7,5,2>: Cost 4 vrev <7,0,2,5> + 3722899255U, // <0,7,5,3>: Cost 4 vext2 <5,3,0,7>, <5,3,0,7> + 2256737304U, // <0,7,5,4>: Cost 3 vrev <7,0,4,5> 3724226521U, // <0,7,5,5>: Cost 4 vext2 <5,5,0,7>, <5,5,0,7> 2718717377U, // <0,7,5,6>: Cost 3 vext3 <5,6,7,0>, <7,5,6,7> - 2260235715U, // <0,7,5,7>: Cost 3 vrev <7,5,7,0> + 2729997763U, // <0,7,5,7>: Cost 3 vext3 <7,5,7,0>, <7,5,7,0> 2720044499U, // <0,7,5,u>: Cost 3 vext3 <5,u,7,0>, <7,5,u,7> - 2598477926U, // <0,7,6,0>: Cost 3 vext1 , LHS - 2556674846U, // <0,7,6,1>: Cost 3 vext1 <1,0,7,6>, <1,0,7,6> + 3712946517U, // <0,7,6,0>: Cost 4 vext2 <3,6,0,7>, <6,0,7,0> + 2256524286U, // <0,7,6,1>: Cost 3 vrev <7,0,1,6> 3792459246U, // <0,7,6,2>: Cost 4 vext3 <5,6,7,0>, <7,6,2,7> - 2237008560U, // <0,7,6,3>: Cost 3 vrev <3,6,7,0> - 2598481206U, // <0,7,6,4>: Cost 3 vext1 , RHS - 1175212130U, // <0,7,6,5>: Cost 2 vrev <5,6,7,0> - 2598482773U, // <0,7,6,6>: Cost 3 vext1 , <6,7,0,u> - 2260899348U, // <0,7,6,7>: Cost 3 vrev <7,6,7,0> - 1193130221U, // <0,7,6,u>: Cost 2 vrev - 2665747456U, // <0,7,7,0>: Cost 3 vext2 , <7,0,1,u> + 3796440567U, // <0,7,6,3>: Cost 4 vext3 <6,3,7,0>, <7,6,3,7> + 3654307126U, // <0,7,6,4>: Cost 4 vext1 <5,0,7,6>, RHS + 2656457394U, // <0,7,6,5>: Cost 3 vext2 <6,5,0,7>, <6,5,0,7> + 3792459281U, // <0,7,6,6>: Cost 4 vext3 <5,6,7,0>, <7,6,6,6> + 2730661396U, // <0,7,6,7>: Cost 3 vext3 <7,6,7,0>, <7,6,7,0> + 2658448293U, // <0,7,6,u>: Cost 3 vext2 <6,u,0,7>, <6,u,0,7> + 3787003431U, // <0,7,7,0>: Cost 4 vext3 <4,7,5,0>, <7,7,0,1> 3654312854U, // <0,7,7,1>: Cost 4 vext1 <5,0,7,7>, <1,2,3,0> 3654313446U, // <0,7,7,2>: Cost 4 vext1 <5,0,7,7>, <2,0,5,7> - 3311414017U, // <0,7,7,3>: Cost 4 vrev <3,7,7,0> + 3804771905U, // <0,7,7,3>: Cost 4 vext3 <7,7,3,0>, <7,7,3,0> 3654315318U, // <0,7,7,4>: Cost 4 vext1 <5,0,7,7>, RHS - 2249617587U, // <0,7,7,5>: Cost 3 vrev <5,7,7,0> - 2255590284U, // <0,7,7,6>: Cost 3 vrev <6,7,7,0> + 3654315651U, // <0,7,7,5>: Cost 4 vext1 <5,0,7,7>, <5,0,7,7> + 3660288348U, // <0,7,7,6>: Cost 4 vext1 <6,0,7,7>, <6,0,7,7> 2718717548U, // <0,7,7,7>: Cost 3 vext3 <5,6,7,0>, <7,7,7,7> 2664420990U, // <0,7,7,u>: Cost 3 vext2 <7,u,0,7>, <7,u,0,7> - 2726163439U, // <0,7,u,0>: Cost 3 vext3 <7,0,0,0>, <7,0,0,0> - 2632570670U, // <0,7,u,1>: Cost 3 vext2 <2,5,0,7>, LHS - 2733536906U, // <0,7,u,2>: Cost 3 vext3 , <7,u,2,1> - 2238335826U, // <0,7,u,3>: Cost 3 vrev <3,u,7,0> - 2718716952U, // <0,7,u,4>: Cost 3 vext3 <5,6,7,0>, <7,0,4,5> - 1176539396U, // <0,7,u,5>: Cost 2 vrev <5,u,7,0> - 2256253917U, // <0,7,u,6>: Cost 3 vrev <6,u,7,0> - 2262226614U, // <0,7,u,7>: Cost 3 vrev <7,u,7,0> - 1194457487U, // <0,7,u,u>: Cost 2 vrev + 2256466935U, // <0,7,u,0>: Cost 3 vrev <7,0,0,u> + 1182798848U, // <0,7,u,1>: Cost 2 vrev <7,0,1,u> + 2256614409U, // <0,7,u,2>: Cost 3 vrev <7,0,2,u> + 2731693714U, // <0,7,u,3>: Cost 3 vext3 <7,u,3,0>, <7,u,3,0> + 2256761883U, // <0,7,u,4>: Cost 3 vrev <7,0,4,u> + 2632571034U, // <0,7,u,5>: Cost 3 vext2 <2,5,0,7>, RHS + 2669066421U, // <0,7,u,6>: Cost 3 vext2 , + 2731988662U, // <0,7,u,7>: Cost 3 vext3 <7,u,7,0>, <7,u,7,0> + 1183315007U, // <0,7,u,u>: Cost 2 vrev <7,0,u,u> 135053414U, // <0,u,0,0>: Cost 1 vdup0 LHS 1544896614U, // <0,u,0,1>: Cost 2 vext2 <0,2,0,u>, LHS 1678999654U, // <0,u,0,2>: Cost 2 vuzpl LHS, LHS - 2233100499U, // <0,u,0,3>: Cost 3 vrev <3,0,u,0> + 2691880677U, // <0,u,0,3>: Cost 3 vext3 <1,2,3,0>, 1476988214U, // <0,u,0,4>: Cost 2 vext1 <0,0,u,0>, RHS 2718791419U, // <0,u,0,5>: Cost 3 vext3 <5,6,u,0>, 3021248666U, // <0,u,0,6>: Cost 3 vtrnl <0,2,0,2>, RHS - 2256991287U, // <0,u,0,7>: Cost 3 vrev <7,0,u,0> + 2592535607U, // <0,u,0,7>: Cost 3 vext1 <7,0,u,0>, <7,0,u,0> 135053414U, // <0,u,0,u>: Cost 1 vdup0 LHS 1476993097U, // <0,u,1,0>: Cost 2 vext1 <0,0,u,1>, <0,0,u,1> 1812780846U, // <0,u,1,1>: Cost 2 vzipl LHS, LHS 1618138926U, // <0,u,1,2>: Cost 2 vext3 <1,2,3,0>, LHS - 2752742216U, // <0,u,1,3>: Cost 3 vuzpl LHS, <1,1,3,3> + 2752742134U, // <0,u,1,3>: Cost 3 vuzpl LHS, <1,0,3,2> 1476996406U, // <0,u,1,4>: Cost 2 vext1 <0,0,u,1>, RHS 1812781210U, // <0,u,1,5>: Cost 2 vzipl LHS, RHS 2887006416U, // <0,u,1,6>: Cost 3 vzipl LHS, 2966736200U, // <0,u,1,7>: Cost 3 vzipr <2,3,0,1>, RHS 1812781413U, // <0,u,1,u>: Cost 2 vzipl LHS, LHS - 1494917222U, // <0,u,2,0>: Cost 2 vext1 <3,0,u,2>, LHS - 1148740547U, // <0,u,2,1>: Cost 2 vrev <1,2,u,0> + 1482973286U, // <0,u,2,0>: Cost 2 vext1 <1,0,u,2>, LHS + 1482973987U, // <0,u,2,1>: Cost 2 vext1 <1,0,u,2>, <1,0,u,2> 1946998574U, // <0,u,2,2>: Cost 2 vtrnl LHS, LHS 835584U, // <0,u,2,3>: Cost 0 copy LHS - 1494920502U, // <0,u,2,4>: Cost 2 vext1 <3,0,u,2>, RHS + 1482976566U, // <0,u,2,4>: Cost 2 vext1 <1,0,u,2>, RHS 3020781631U, // <0,u,2,5>: Cost 3 vtrnl LHS, 1946998938U, // <0,u,2,6>: Cost 2 vtrnl LHS, RHS 1518810169U, // <0,u,2,7>: Cost 2 vext1 <7,0,u,2>, <7,0,u,2> 835584U, // <0,u,2,u>: Cost 0 copy LHS 2618640534U, // <0,u,3,0>: Cost 3 vext2 <0,2,0,u>, <3,0,1,2> 2752743574U, // <0,u,3,1>: Cost 3 vuzpl LHS, <3,0,1,2> - 2618640694U, // <0,u,3,2>: Cost 3 vext2 <0,2,0,u>, <3,2,1,0> + 2636556597U, // <0,u,3,2>: Cost 3 vext2 <3,2,0,u>, <3,2,0,u> 2752743836U, // <0,u,3,3>: Cost 3 vuzpl LHS, <3,3,3,3> 2618640898U, // <0,u,3,4>: Cost 3 vext2 <0,2,0,u>, <3,4,5,6> 2752743938U, // <0,u,3,5>: Cost 3 vuzpl LHS, <3,4,5,6> - 2253009489U, // <0,u,3,6>: Cost 3 vrev <6,3,u,0> + 2639202936U, // <0,u,3,6>: Cost 3 vext2 <3,6,0,7>, <3,6,0,7> 2639874762U, // <0,u,3,7>: Cost 3 vext2 <3,7,0,u>, <3,7,0,u> 2752743637U, // <0,u,3,u>: Cost 3 vuzpl LHS, <3,0,u,2> 2562703462U, // <0,u,4,0>: Cost 3 vext1 <2,0,u,4>, LHS @@ -712,7 +712,7 @@ 2562706742U, // <0,u,4,4>: Cost 3 vext1 <2,0,u,4>, RHS 1544899894U, // <0,u,4,5>: Cost 2 vext2 <0,2,0,u>, RHS 1679002934U, // <0,u,4,6>: Cost 2 vuzpl LHS, RHS - 2592568379U, // <0,u,4,7>: Cost 3 vext1 <7,0,u,4>, <7,0,u,4> + 2718718033U, // <0,u,4,7>: Cost 3 vext3 <5,6,7,0>, 1679002952U, // <0,u,4,u>: Cost 2 vuzpl LHS, RHS 2568683622U, // <0,u,5,0>: Cost 3 vext1 <3,0,u,5>, LHS 2568684438U, // <0,u,5,1>: Cost 3 vext1 <3,0,u,5>, <1,2,3,0> @@ -721,14 +721,14 @@ 2568686902U, // <0,u,5,4>: Cost 3 vext1 <3,0,u,5>, RHS 2650492890U, // <0,u,5,5>: Cost 3 vext2 <5,5,0,u>, <5,5,0,u> 1618139290U, // <0,u,5,6>: Cost 2 vext3 <1,2,3,0>, RHS - 2836630838U, // <0,u,5,7>: Cost 3 vuzpr <3,0,1,u>, RHS + 2824834358U, // <0,u,5,7>: Cost 3 vuzpr <1,0,3,u>, RHS 1618139308U, // <0,u,5,u>: Cost 2 vext3 <1,2,3,0>, RHS 2592579686U, // <0,u,6,0>: Cost 3 vext1 <7,0,u,6>, LHS - 2653770090U, // <0,u,6,1>: Cost 3 vext2 <6,1,0,3>, <6,1,0,3> + 2262496983U, // <0,u,6,1>: Cost 3 vrev 2654474688U, // <0,u,6,2>: Cost 3 vext2 <6,2,0,u>, <6,2,0,u> 2691881168U, // <0,u,6,3>: Cost 3 vext3 <1,2,3,0>, 2592582966U, // <0,u,6,4>: Cost 3 vext1 <7,0,u,6>, RHS - 1175285867U, // <0,u,6,5>: Cost 2 vrev <5,6,u,0> + 2656465587U, // <0,u,6,5>: Cost 3 vext2 <6,5,0,u>, <6,5,0,u> 2657129220U, // <0,u,6,6>: Cost 3 vext2 <6,6,0,u>, <6,6,0,u> 1584051029U, // <0,u,6,7>: Cost 2 vext2 <6,7,0,u>, <6,7,0,u> 1584714662U, // <0,u,6,u>: Cost 2 vext2 <6,u,0,u>, <6,u,0,u> @@ -745,100 +745,100 @@ 1544902446U, // <0,u,u,1>: Cost 2 vext2 <0,2,0,u>, LHS 1679005486U, // <0,u,u,2>: Cost 2 vuzpl LHS, LHS 835584U, // <0,u,u,3>: Cost 0 copy LHS - 1494969654U, // <0,u,u,4>: Cost 2 vext1 <3,0,u,u>, RHS + 1483025718U, // <0,u,u,4>: Cost 2 vext1 <1,0,u,u>, RHS 1544902810U, // <0,u,u,5>: Cost 2 vext2 <0,2,0,u>, RHS 1679005850U, // <0,u,u,6>: Cost 2 vuzpl LHS, RHS 1518859327U, // <0,u,u,7>: Cost 2 vext1 <7,0,u,u>, <7,0,u,u> 835584U, // <0,u,u,u>: Cost 0 copy LHS 2689744896U, // <1,0,0,0>: Cost 3 vext3 <0,u,1,1>, <0,0,0,0> - 1562820710U, // <1,0,0,1>: Cost 2 vext2 <3,2,1,0>, LHS + 1610694666U, // <1,0,0,1>: Cost 2 vext3 <0,0,1,1>, <0,0,1,1> 2689744916U, // <1,0,0,2>: Cost 3 vext3 <0,u,1,1>, <0,0,2,2> 2619310332U, // <1,0,0,3>: Cost 3 vext2 <0,3,1,0>, <0,3,1,0> - 2636562770U, // <1,0,0,4>: Cost 3 vext2 <3,2,1,0>, <0,4,1,5> + 2684657701U, // <1,0,0,4>: Cost 3 vext3 <0,0,4,1>, <0,0,4,1> 2620637598U, // <1,0,0,5>: Cost 3 vext2 <0,5,1,0>, <0,5,1,0> 3708977654U, // <1,0,0,6>: Cost 4 vext2 <3,0,1,0>, <0,6,1,7> - 2256409584U, // <1,0,0,7>: Cost 3 vrev <7,0,0,1> - 1562821277U, // <1,0,0,u>: Cost 2 vext2 <3,2,1,0>, LHS + 3666351168U, // <1,0,0,7>: Cost 4 vext1 <7,1,0,0>, <7,1,0,0> + 1611210825U, // <1,0,0,u>: Cost 2 vext3 <0,0,u,1>, <0,0,u,1> 2556780646U, // <1,0,1,0>: Cost 3 vext1 <1,1,0,1>, LHS - 2221237035U, // <1,0,1,1>: Cost 3 vrev <1,1,0,1> + 2556781355U, // <1,0,1,1>: Cost 3 vext1 <1,1,0,1>, <1,1,0,1> 1616003174U, // <1,0,1,2>: Cost 2 vext3 <0,u,1,1>, LHS - 2636563416U, // <1,0,1,3>: Cost 3 vext2 <3,2,1,0>, <1,3,1,3> + 3693052888U, // <1,0,1,3>: Cost 4 vext2 <0,3,1,0>, <1,3,1,3> 2556783926U, // <1,0,1,4>: Cost 3 vext1 <1,1,0,1>, RHS - 2636563600U, // <1,0,1,5>: Cost 3 vext2 <3,2,1,0>, <1,5,3,7> + 2580672143U, // <1,0,1,5>: Cost 3 vext1 <5,1,0,1>, <5,1,0,1> 2724839566U, // <1,0,1,6>: Cost 3 vext3 <6,7,0,1>, <0,1,6,7> 3654415354U, // <1,0,1,7>: Cost 4 vext1 <5,1,0,1>, <7,0,1,2> 1616003228U, // <1,0,1,u>: Cost 2 vext3 <0,u,1,1>, LHS 2685690019U, // <1,0,2,0>: Cost 3 vext3 <0,2,0,1>, <0,2,0,1> 2685763756U, // <1,0,2,1>: Cost 3 vext3 <0,2,1,1>, <0,2,1,1> - 2227873365U, // <1,0,2,2>: Cost 3 vrev <2,2,0,1> + 2698297524U, // <1,0,2,2>: Cost 3 vext3 <2,3,0,1>, <0,2,2,0> 2685911230U, // <1,0,2,3>: Cost 3 vext3 <0,2,3,1>, <0,2,3,1> 2689745100U, // <1,0,2,4>: Cost 3 vext3 <0,u,1,1>, <0,2,4,6> - 4044540372U, // <1,0,2,5>: Cost 4 vzipr <3,0,1,2>, <3,4,0,5> - 2636564410U, // <1,0,2,6>: Cost 3 vext2 <3,2,1,0>, <2,6,3,7> + 3764814038U, // <1,0,2,5>: Cost 4 vext3 <1,1,1,1>, <0,2,5,7> + 2724839640U, // <1,0,2,6>: Cost 3 vext3 <6,7,0,1>, <0,2,6,0> 2592625658U, // <1,0,2,7>: Cost 3 vext1 <7,1,0,2>, <7,0,1,2> 2686279915U, // <1,0,2,u>: Cost 3 vext3 <0,2,u,1>, <0,2,u,1> 3087843328U, // <1,0,3,0>: Cost 3 vtrnr LHS, <0,0,0,0> 3087843338U, // <1,0,3,1>: Cost 3 vtrnr LHS, <0,0,1,1> - 1154795174U, // <1,0,3,2>: Cost 2 vrev <2,3,0,1> - 2636564881U, // <1,0,3,3>: Cost 3 vext2 <3,2,1,0>, <3,3,2,1> - 2636564994U, // <1,0,3,4>: Cost 3 vext2 <3,2,1,0>, <3,4,5,6> - 2586660962U, // <1,0,3,5>: Cost 3 vext1 <6,1,0,3>, <5,6,7,0> - 2586661226U, // <1,0,3,6>: Cost 3 vext1 <6,1,0,3>, <6,1,0,3> - 2258400483U, // <1,0,3,7>: Cost 3 vrev <7,3,0,1> - 1566804764U, // <1,0,3,u>: Cost 2 vext2 <3,u,1,0>, <3,u,1,0> - 2598608998U, // <1,0,4,0>: Cost 3 vext1 , LHS + 67944550U, // <1,0,3,2>: Cost 1 vrev LHS + 2568743135U, // <1,0,3,3>: Cost 3 vext1 <3,1,0,3>, <3,1,0,3> + 2562772278U, // <1,0,3,4>: Cost 3 vext1 <2,1,0,3>, RHS + 4099850454U, // <1,0,3,5>: Cost 4 vtrnl <1,0,3,2>, <0,2,5,7> + 3704998538U, // <1,0,3,6>: Cost 4 vext2 <2,3,1,0>, <3,6,2,7> + 2592633923U, // <1,0,3,7>: Cost 3 vext1 <7,1,0,3>, <7,1,0,3> + 68386972U, // <1,0,3,u>: Cost 1 vrev LHS + 2620640146U, // <1,0,4,0>: Cost 3 vext2 <0,5,1,0>, <4,0,5,1> 2689745234U, // <1,0,4,1>: Cost 3 vext3 <0,u,1,1>, <0,4,1,5> 2689745244U, // <1,0,4,2>: Cost 3 vext3 <0,u,1,1>, <0,4,2,6> - 2235173328U, // <1,0,4,3>: Cost 3 vrev <3,4,0,1> - 2598612278U, // <1,0,4,4>: Cost 3 vext1 , RHS - 1562823990U, // <1,0,4,5>: Cost 2 vext2 <3,2,1,0>, RHS - 2666425716U, // <1,0,4,6>: Cost 3 vext2 , <4,6,4,6> - 2259064116U, // <1,0,4,7>: Cost 3 vrev <7,4,0,1> - 1562824233U, // <1,0,4,u>: Cost 2 vext2 <3,2,1,0>, RHS + 3760980320U, // <1,0,4,3>: Cost 4 vext3 <0,4,3,1>, <0,4,3,1> + 3761054057U, // <1,0,4,4>: Cost 4 vext3 <0,4,4,1>, <0,4,4,1> + 2619313462U, // <1,0,4,5>: Cost 3 vext2 <0,3,1,0>, RHS + 3761201531U, // <1,0,4,6>: Cost 4 vext3 <0,4,6,1>, <0,4,6,1> + 3666383940U, // <1,0,4,7>: Cost 4 vext1 <7,1,0,4>, <7,1,0,4> + 2619313705U, // <1,0,4,u>: Cost 3 vext2 <0,3,1,0>, RHS 4029300736U, // <1,0,5,0>: Cost 4 vzipr <0,4,1,5>, <0,0,0,0> - 2223891567U, // <1,0,5,1>: Cost 3 vrev <1,5,0,1> + 2895249510U, // <1,0,5,1>: Cost 3 vzipl <1,5,3,7>, LHS 3028287590U, // <1,0,5,2>: Cost 3 vtrnl <1,3,5,7>, LHS - 3710308163U, // <1,0,5,3>: Cost 4 vext2 <3,2,1,0>, <5,3,2,1> - 2241809658U, // <1,0,5,4>: Cost 3 vrev <4,5,0,1> - 2247782355U, // <1,0,5,5>: Cost 3 vrev <5,5,0,1> - 2666426466U, // <1,0,5,6>: Cost 3 vext2 , <5,6,7,0> - 2666426536U, // <1,0,5,7>: Cost 3 vext2 , <5,7,5,7> + 3642501345U, // <1,0,5,3>: Cost 4 vext1 <3,1,0,5>, <3,1,0,5> + 2215592058U, // <1,0,5,4>: Cost 3 vrev <0,1,4,5> + 3724242907U, // <1,0,5,5>: Cost 4 vext2 <5,5,1,0>, <5,5,1,0> + 3724906540U, // <1,0,5,6>: Cost 4 vext2 <5,6,1,0>, <5,6,1,0> + 3911118134U, // <1,0,5,7>: Cost 4 vuzpr <3,1,3,0>, RHS 3028287644U, // <1,0,5,u>: Cost 3 vtrnl <1,3,5,7>, LHS - 3292324327U, // <1,0,6,0>: Cost 4 vrev <0,6,0,1> + 3762086375U, // <1,0,6,0>: Cost 4 vext3 <0,6,0,1>, <0,6,0,1> 2698297846U, // <1,0,6,1>: Cost 3 vext3 <2,3,0,1>, <0,6,1,7> - 2230527897U, // <1,0,6,2>: Cost 3 vrev <2,6,0,1> + 3760022015U, // <1,0,6,2>: Cost 4 vext3 <0,2,u,1>, <0,6,2,7> 3642509538U, // <1,0,6,3>: Cost 4 vext1 <3,1,0,6>, <3,1,0,6> - 2242473291U, // <1,0,6,4>: Cost 3 vrev <4,6,0,1> - 2248445988U, // <1,0,6,5>: Cost 3 vrev <5,6,0,1> - 2254418685U, // <1,0,6,6>: Cost 3 vrev <6,6,0,1> - 2659128142U, // <1,0,6,7>: Cost 3 vext2 <7,0,1,0>, <6,7,0,1> - 2666427295U, // <1,0,6,u>: Cost 3 vext2 , <6,u,0,1> + 3762381323U, // <1,0,6,4>: Cost 4 vext3 <0,6,4,1>, <0,6,4,1> + 3730215604U, // <1,0,6,5>: Cost 4 vext2 <6,5,1,0>, <6,5,1,0> + 3730879237U, // <1,0,6,6>: Cost 4 vext2 <6,6,1,0>, <6,6,1,0> + 2657801046U, // <1,0,6,7>: Cost 3 vext2 <6,7,1,0>, <6,7,1,0> + 2658464679U, // <1,0,6,u>: Cost 3 vext2 <6,u,1,0>, <6,u,1,0> 2659128312U, // <1,0,7,0>: Cost 3 vext2 <7,0,1,0>, <7,0,1,0> - 3298960657U, // <1,0,7,1>: Cost 4 vrev <1,7,0,1> - 2689155658U, // <1,0,7,2>: Cost 3 vext3 <0,7,2,1>, <0,7,2,1> - 2237164227U, // <1,0,7,3>: Cost 3 vrev <3,7,0,1> - 2598636854U, // <1,0,7,4>: Cost 3 vext1 , RHS - 2249109621U, // <1,0,7,5>: Cost 3 vrev <5,7,0,1> - 1181340494U, // <1,0,7,6>: Cost 2 vrev <6,7,0,1> - 2261055015U, // <1,0,7,7>: Cost 3 vrev <7,7,0,1> - 1193285888U, // <1,0,7,u>: Cost 2 vrev + 4047898278U, // <1,0,7,1>: Cost 4 vzipr <3,5,1,7>, <2,3,0,1> + 2215460970U, // <1,0,7,2>: Cost 3 vrev <0,1,2,7> + 3734861035U, // <1,0,7,3>: Cost 4 vext2 <7,3,1,0>, <7,3,1,0> + 3731543398U, // <1,0,7,4>: Cost 4 vext2 <6,7,1,0>, <7,4,5,6> + 3736188301U, // <1,0,7,5>: Cost 4 vext2 <7,5,1,0>, <7,5,1,0> + 2663110110U, // <1,0,7,6>: Cost 3 vext2 <7,6,1,0>, <7,6,1,0> + 3731543660U, // <1,0,7,7>: Cost 4 vext2 <6,7,1,0>, <7,7,7,7> + 2664437376U, // <1,0,7,u>: Cost 3 vext2 <7,u,1,0>, <7,u,1,0> 3087884288U, // <1,0,u,0>: Cost 3 vtrnr LHS, <0,0,0,0> 1616003730U, // <1,0,u,1>: Cost 2 vext3 <0,u,1,1>, <0,u,1,1> - 1616003741U, // <1,0,u,2>: Cost 2 vext3 <0,u,1,1>, LHS + 67985515U, // <1,0,u,2>: Cost 1 vrev LHS 2689893028U, // <1,0,u,3>: Cost 3 vext3 <0,u,3,1>, <0,u,3,1> 2689745586U, // <1,0,u,4>: Cost 3 vext3 <0,u,1,1>, <0,u,4,6> - 1562826906U, // <1,0,u,5>: Cost 2 vext2 <3,2,1,0>, RHS - 1182004127U, // <1,0,u,6>: Cost 2 vrev <6,u,0,1> - 2261718648U, // <1,0,u,7>: Cost 3 vrev <7,u,0,1> - 1616003795U, // <1,0,u,u>: Cost 2 vext3 <0,u,1,1>, LHS + 2619316378U, // <1,0,u,5>: Cost 3 vext2 <0,3,1,0>, RHS + 2669082807U, // <1,0,u,6>: Cost 3 vext2 , + 2592674888U, // <1,0,u,7>: Cost 3 vext1 <7,1,0,u>, <7,1,0,u> + 68427937U, // <1,0,u,u>: Cost 1 vrev LHS 1543585802U, // <1,1,0,0>: Cost 2 vext2 <0,0,1,1>, <0,0,1,1> 1548894310U, // <1,1,0,1>: Cost 2 vext2 <0,u,1,1>, LHS 2618654892U, // <1,1,0,2>: Cost 3 vext2 <0,2,1,1>, <0,2,1,1> - 2690556661U, // <1,1,0,3>: Cost 3 vext3 <1,0,3,1>, <1,0,3,1> + 2689745654U, // <1,1,0,3>: Cost 3 vext3 <0,u,1,1>, <1,0,3,2> 2622636370U, // <1,1,0,4>: Cost 3 vext2 <0,u,1,1>, <0,4,1,5> 2620645791U, // <1,1,0,5>: Cost 3 vext2 <0,5,1,1>, <0,5,1,1> 3696378367U, // <1,1,0,6>: Cost 4 vext2 <0,u,1,1>, <0,6,2,7> - 2724840222U, // <1,1,0,7>: Cost 3 vext3 <6,7,0,1>, <1,0,7,6> + 3666424905U, // <1,1,0,7>: Cost 4 vext1 <7,1,1,0>, <7,1,1,0> 1548894866U, // <1,1,0,u>: Cost 2 vext2 <0,u,1,1>, <0,u,1,1> 1483112550U, // <1,1,1,0>: Cost 2 vext1 <1,1,1,1>, LHS 202162278U, // <1,1,1,1>: Cost 1 vdup1 LHS @@ -847,7 +847,7 @@ 1483115830U, // <1,1,1,4>: Cost 2 vext1 <1,1,1,1>, RHS 2622637200U, // <1,1,1,5>: Cost 3 vext2 <0,u,1,1>, <1,5,3,7> 2622637263U, // <1,1,1,6>: Cost 3 vext2 <0,u,1,1>, <1,6,1,7> - 2257146954U, // <1,1,1,7>: Cost 3 vrev <7,1,1,1> + 2592691274U, // <1,1,1,7>: Cost 3 vext1 <7,1,1,1>, <7,1,1,1> 202162278U, // <1,1,1,u>: Cost 1 vdup1 LHS 2550890588U, // <1,1,2,0>: Cost 3 vext1 <0,1,1,2>, <0,1,1,2> 2617329183U, // <1,1,2,1>: Cost 3 vext2 <0,0,1,1>, <2,1,3,1> @@ -860,7 +860,7 @@ 2622638139U, // <1,1,2,u>: Cost 3 vext2 <0,u,1,1>, <2,u,0,1> 2622638230U, // <1,1,3,0>: Cost 3 vext2 <0,u,1,1>, <3,0,1,2> 3087844148U, // <1,1,3,1>: Cost 3 vtrnr LHS, <1,1,1,1> - 2622638390U, // <1,1,3,2>: Cost 3 vext2 <0,u,1,1>, <3,2,1,0> + 4161585244U, // <1,1,3,2>: Cost 4 vtrnr LHS, <0,1,1,2> 2014101606U, // <1,1,3,3>: Cost 2 vtrnr LHS, LHS 2622638594U, // <1,1,3,4>: Cost 3 vext2 <0,u,1,1>, <3,4,5,6> 2689745920U, // <1,1,3,5>: Cost 3 vext3 <0,u,1,1>, <1,3,5,7> @@ -868,7 +868,7 @@ 2592707660U, // <1,1,3,7>: Cost 3 vext1 <7,1,1,3>, <7,1,1,3> 2014101611U, // <1,1,3,u>: Cost 2 vtrnr LHS, LHS 2556878950U, // <1,1,4,0>: Cost 3 vext1 <1,1,1,4>, LHS - 2556879671U, // <1,1,4,1>: Cost 3 vext1 <1,1,1,4>, <1,1,1,4> + 2221335351U, // <1,1,4,1>: Cost 3 vrev <1,1,1,4> 3696380988U, // <1,1,4,2>: Cost 4 vext2 <0,u,1,1>, <4,2,6,0> 3763487805U, // <1,1,4,3>: Cost 4 vext3 <0,u,1,1>, <1,4,3,5> 2556882230U, // <1,1,4,4>: Cost 3 vext1 <1,1,1,4>, RHS @@ -880,7 +880,7 @@ 2617331408U, // <1,1,5,1>: Cost 3 vext2 <0,0,1,1>, <5,1,7,3> 4029302934U, // <1,1,5,2>: Cost 4 vzipr <0,4,1,5>, <3,0,1,2> 2689746064U, // <1,1,5,3>: Cost 3 vext3 <0,u,1,1>, <1,5,3,7> - 2550918454U, // <1,1,5,4>: Cost 3 vext1 <0,1,1,5>, RHS + 2221564755U, // <1,1,5,4>: Cost 3 vrev <1,1,4,5> 2955559250U, // <1,1,5,5>: Cost 3 vzipr <0,4,1,5>, <0,4,1,5> 2617331810U, // <1,1,5,6>: Cost 3 vext2 <0,0,1,1>, <5,6,7,0> 2825293110U, // <1,1,5,7>: Cost 3 vuzpr <1,1,1,1>, RHS @@ -889,23 +889,23 @@ 2689746127U, // <1,1,6,1>: Cost 3 vext3 <0,u,1,1>, <1,6,1,7> 2617332218U, // <1,1,6,2>: Cost 3 vext2 <0,0,1,1>, <6,2,7,3> 3763487969U, // <1,1,6,3>: Cost 4 vext3 <0,u,1,1>, <1,6,3,7> - 3696382572U, // <1,1,6,4>: Cost 4 vext2 <0,u,1,1>, <6,4,2,0> + 3696382605U, // <1,1,6,4>: Cost 4 vext2 <0,u,1,1>, <6,4,5,6> 4029309266U, // <1,1,6,5>: Cost 4 vzipr <0,4,1,6>, <0,4,1,5> 2617332536U, // <1,1,6,6>: Cost 3 vext2 <0,0,1,1>, <6,6,6,6> 2724840702U, // <1,1,6,7>: Cost 3 vext3 <6,7,0,1>, <1,6,7,0> 2725504263U, // <1,1,6,u>: Cost 3 vext3 <6,u,0,1>, <1,6,u,0> 2617332720U, // <1,1,7,0>: Cost 3 vext2 <0,0,1,1>, <7,0,0,1> 2659800138U, // <1,1,7,1>: Cost 3 vext2 <7,1,1,1>, <7,1,1,1> - 3691074725U, // <1,1,7,2>: Cost 4 vext2 <0,0,1,1>, <7,2,2,2> + 3691074717U, // <1,1,7,2>: Cost 4 vext2 <0,0,1,1>, <7,2,1,3> 4167811174U, // <1,1,7,3>: Cost 4 vtrnr <1,1,5,7>, LHS 2617333094U, // <1,1,7,4>: Cost 3 vext2 <0,0,1,1>, <7,4,5,6> - 3769091390U, // <1,1,7,5>: Cost 4 vext3 <1,7,5,1>, <1,7,5,1> - 2255156055U, // <1,1,7,6>: Cost 3 vrev <6,7,1,1> + 3295396702U, // <1,1,7,5>: Cost 4 vrev <1,1,5,7> + 3803891014U, // <1,1,7,6>: Cost 4 vext3 <7,6,0,1>, <1,7,6,0> 2617333356U, // <1,1,7,7>: Cost 3 vext2 <0,0,1,1>, <7,7,7,7> - 2267101449U, // <1,1,7,u>: Cost 3 vrev + 2659800138U, // <1,1,7,u>: Cost 3 vext2 <7,1,1,1>, <7,1,1,1> 1483112550U, // <1,1,u,0>: Cost 2 vext1 <1,1,1,1>, LHS 202162278U, // <1,1,u,1>: Cost 1 vdup1 LHS - 2622642035U, // <1,1,u,2>: Cost 3 vext2 <0,u,1,1>, + 2622642056U, // <1,1,u,2>: Cost 3 vext2 <0,u,1,1>, 2014142566U, // <1,1,u,3>: Cost 2 vtrnr LHS, LHS 1483115830U, // <1,1,u,4>: Cost 2 vext1 <1,1,1,1>, RHS 1548900506U, // <1,1,u,5>: Cost 2 vext2 <0,u,1,1>, RHS @@ -915,11 +915,11 @@ 2635251712U, // <1,2,0,0>: Cost 3 vext2 <3,0,1,2>, <0,0,0,0> 1561509990U, // <1,2,0,1>: Cost 2 vext2 <3,0,1,2>, LHS 2618663085U, // <1,2,0,2>: Cost 3 vext2 <0,2,1,2>, <0,2,1,2> - 2619326718U, // <1,2,0,3>: Cost 3 vext2 <0,3,1,2>, <0,3,1,2> + 2696529358U, // <1,2,0,3>: Cost 3 vext3 <2,0,3,1>, <2,0,3,1> 2635252050U, // <1,2,0,4>: Cost 3 vext2 <3,0,1,2>, <0,4,1,5> - 2635252142U, // <1,2,0,5>: Cost 3 vext2 <3,0,1,2>, <0,5,2,7> + 3769533926U, // <1,2,0,5>: Cost 4 vext3 <1,u,2,1>, <2,0,5,7> 2621317617U, // <1,2,0,6>: Cost 3 vext2 <0,6,1,2>, <0,6,1,2> - 2659140160U, // <1,2,0,7>: Cost 3 vext2 <7,0,1,2>, <0,7,1,0> + 2659140170U, // <1,2,0,7>: Cost 3 vext2 <7,0,1,2>, <0,7,2,1> 1561510557U, // <1,2,0,u>: Cost 2 vext2 <3,0,1,2>, LHS 2623308516U, // <1,2,1,0>: Cost 3 vext2 <1,0,1,2>, <1,0,1,2> 2635252532U, // <1,2,1,1>: Cost 3 vext2 <3,0,1,2>, <1,1,1,1> @@ -931,7 +931,7 @@ 3732882731U, // <1,2,1,7>: Cost 4 vext2 <7,0,1,2>, <1,7,3,0> 2958180459U, // <1,2,1,u>: Cost 3 vzipr <0,u,1,1>, LHS 2629281213U, // <1,2,2,0>: Cost 3 vext2 <2,0,1,2>, <2,0,1,2> - 2635253254U, // <1,2,2,1>: Cost 3 vext2 <3,0,1,2>, <2,1,0,3> + 2635253280U, // <1,2,2,1>: Cost 3 vext2 <3,0,1,2>, <2,1,3,2> 2618664552U, // <1,2,2,2>: Cost 3 vext2 <0,2,1,2>, <2,2,2,2> 2689746546U, // <1,2,2,3>: Cost 3 vext3 <0,u,1,1>, <2,2,3,3> 3764815485U, // <1,2,2,4>: Cost 4 vext3 <1,1,1,1>, <2,2,4,5> @@ -940,9 +940,9 @@ 2659141610U, // <1,2,2,7>: Cost 3 vext2 <7,0,1,2>, <2,7,0,1> 2689746591U, // <1,2,2,u>: Cost 3 vext3 <0,u,1,1>, <2,2,u,3> 403488870U, // <1,2,3,0>: Cost 1 vext1 LHS, LHS - 1477231412U, // <1,2,3,1>: Cost 2 vext1 LHS, <1,1,1,1> + 1477231350U, // <1,2,3,1>: Cost 2 vext1 LHS, <1,0,3,2> 1477232232U, // <1,2,3,2>: Cost 2 vext1 LHS, <2,2,2,2> - 1477232950U, // <1,2,3,3>: Cost 2 vext1 LHS, <3,2,1,0> + 1477233052U, // <1,2,3,3>: Cost 2 vext1 LHS, <3,3,3,3> 403492150U, // <1,2,3,4>: Cost 1 vext1 LHS, RHS 1525010128U, // <1,2,3,5>: Cost 2 vext1 LHS, <5,1,7,3> 1525010938U, // <1,2,3,6>: Cost 2 vext1 LHS, <6,2,7,3> @@ -950,7 +950,7 @@ 403494702U, // <1,2,3,u>: Cost 1 vext1 LHS, LHS 2641226607U, // <1,2,4,0>: Cost 3 vext2 <4,0,1,2>, <4,0,1,2> 3624723446U, // <1,2,4,1>: Cost 4 vext1 <0,1,2,4>, <1,3,4,6> - 3636667929U, // <1,2,4,2>: Cost 4 vext1 <2,1,2,4>, <2,1,2,4> + 3301123609U, // <1,2,4,2>: Cost 4 vrev <2,1,2,4> 2598759198U, // <1,2,4,3>: Cost 3 vext1 , <3,u,1,2> 2659142864U, // <1,2,4,4>: Cost 3 vext2 <7,0,1,2>, <4,4,4,4> 1561513270U, // <1,2,4,5>: Cost 2 vext2 <3,0,1,2>, RHS @@ -980,12 +980,12 @@ 3708998858U, // <1,2,7,2>: Cost 4 vext2 <3,0,1,2>, <7,2,6,3> 2635257059U, // <1,2,7,3>: Cost 3 vext2 <3,0,1,2>, <7,3,0,1> 2659145062U, // <1,2,7,4>: Cost 3 vext2 <7,0,1,2>, <7,4,5,6> - 3708999072U, // <1,2,7,5>: Cost 4 vext2 <3,0,1,2>, <7,5,3,1> - 2659145222U, // <1,2,7,6>: Cost 3 vext2 <7,0,1,2>, <7,6,5,4> + 3732886916U, // <1,2,7,5>: Cost 4 vext2 <7,0,1,2>, <7,5,0,0> + 3732886998U, // <1,2,7,6>: Cost 4 vext2 <7,0,1,2>, <7,6,0,1> 2659145255U, // <1,2,7,7>: Cost 3 vext2 <7,0,1,2>, <7,7,0,1> 1590711938U, // <1,2,7,u>: Cost 2 vext2 <7,u,1,2>, <7,u,1,2> 403529835U, // <1,2,u,0>: Cost 1 vext1 LHS, LHS - 1477272372U, // <1,2,u,1>: Cost 2 vext1 LHS, <1,1,1,1> + 1477272310U, // <1,2,u,1>: Cost 2 vext1 LHS, <1,0,3,2> 1477273192U, // <1,2,u,2>: Cost 2 vext1 LHS, <2,2,2,2> 1477273750U, // <1,2,u,3>: Cost 2 vext1 LHS, <3,0,1,2> 403533110U, // <1,2,u,4>: Cost 1 vext1 LHS, RHS @@ -995,24 +995,24 @@ 403535662U, // <1,2,u,u>: Cost 1 vext1 LHS, LHS 2819407872U, // <1,3,0,0>: Cost 3 vuzpr LHS, <0,0,0,0> 1551564902U, // <1,3,0,1>: Cost 2 vext2 <1,3,1,3>, LHS - 2819410070U, // <1,3,0,2>: Cost 3 vuzpr LHS, <3,0,1,2> + 2819408630U, // <1,3,0,2>: Cost 3 vuzpr LHS, <1,0,3,2> 2619334911U, // <1,3,0,3>: Cost 3 vext2 <0,3,1,3>, <0,3,1,3> 2625306962U, // <1,3,0,4>: Cost 3 vext2 <1,3,1,3>, <0,4,1,5> 3832725879U, // <1,3,0,5>: Cost 4 vuzpl <1,2,3,0>, <0,4,5,6> 3699048959U, // <1,3,0,6>: Cost 4 vext2 <1,3,1,3>, <0,6,2,7> 3776538827U, // <1,3,0,7>: Cost 4 vext3 <3,0,7,1>, <3,0,7,1> 1551565469U, // <1,3,0,u>: Cost 2 vext2 <1,3,1,3>, LHS - 2557001830U, // <1,3,1,0>: Cost 3 vext1 <1,1,3,1>, LHS + 2618671862U, // <1,3,1,0>: Cost 3 vext2 <0,2,1,3>, <1,0,3,2> 2819408692U, // <1,3,1,1>: Cost 3 vuzpr LHS, <1,1,1,1> - 2618672022U, // <1,3,1,2>: Cost 3 vext2 <0,2,1,3>, <1,2,3,0> + 2624643975U, // <1,3,1,2>: Cost 3 vext2 <1,2,1,3>, <1,2,1,3> 1745666150U, // <1,3,1,3>: Cost 2 vuzpr LHS, LHS 2557005110U, // <1,3,1,4>: Cost 3 vext1 <1,1,3,1>, RHS 2625307792U, // <1,3,1,5>: Cost 3 vext2 <1,3,1,3>, <1,5,3,7> 3698386127U, // <1,3,1,6>: Cost 4 vext2 <1,2,1,3>, <1,6,1,7> - 2257294428U, // <1,3,1,7>: Cost 3 vrev <7,1,3,1> + 2592838748U, // <1,3,1,7>: Cost 3 vext1 <7,1,3,1>, <7,1,3,1> 1745666155U, // <1,3,1,u>: Cost 2 vuzpr LHS, LHS 2819408790U, // <1,3,2,0>: Cost 3 vuzpr LHS, <1,2,3,0> - 2689747254U, // <1,3,2,1>: Cost 3 vext3 <0,u,1,1>, <3,2,1,0> + 2625308193U, // <1,3,2,1>: Cost 3 vext2 <1,3,1,3>, <2,1,3,3> 2819408036U, // <1,3,2,2>: Cost 3 vuzpr LHS, <0,2,0,2> 2819851890U, // <1,3,2,3>: Cost 3 vuzpr LHS, <2,2,3,3> 2819408794U, // <1,3,2,4>: Cost 3 vuzpr LHS, <1,2,3,4> @@ -1032,16 +1032,16 @@ 2568970342U, // <1,3,4,0>: Cost 3 vext1 <3,1,3,4>, LHS 2568971224U, // <1,3,4,1>: Cost 3 vext1 <3,1,3,4>, <1,3,1,3> 3832761290U, // <1,3,4,2>: Cost 4 vuzpl <1,2,3,4>, <4,1,2,3> - 2568972539U, // <1,3,4,3>: Cost 3 vext1 <3,1,3,4>, <3,1,3,4> + 2233428219U, // <1,3,4,3>: Cost 3 vrev <3,1,3,4> 2568973622U, // <1,3,4,4>: Cost 3 vext1 <3,1,3,4>, RHS 1551568182U, // <1,3,4,5>: Cost 2 vext2 <1,3,1,3>, RHS 2819410434U, // <1,3,4,6>: Cost 3 vuzpr LHS, <3,4,5,6> - 3729575382U, // <1,3,4,7>: Cost 4 vext2 <6,4,1,3>, <4,7,6,5> + 3666605151U, // <1,3,4,7>: Cost 4 vext1 <7,1,3,4>, <7,1,3,4> 1551568425U, // <1,3,4,u>: Cost 2 vext2 <1,3,1,3>, RHS 2563006566U, // <1,3,5,0>: Cost 3 vext1 <2,1,3,5>, LHS 2568979456U, // <1,3,5,1>: Cost 3 vext1 <3,1,3,5>, <1,3,5,7> 2563008035U, // <1,3,5,2>: Cost 3 vext1 <2,1,3,5>, <2,1,3,5> - 2568980732U, // <1,3,5,3>: Cost 3 vext1 <3,1,3,5>, <3,1,3,5> + 2233436412U, // <1,3,5,3>: Cost 3 vrev <3,1,3,5> 2563009846U, // <1,3,5,4>: Cost 3 vext1 <2,1,3,5>, RHS 2867187716U, // <1,3,5,5>: Cost 3 vuzpr LHS, <5,5,5,5> 2655834214U, // <1,3,5,6>: Cost 3 vext2 <6,4,1,3>, <5,6,7,4> @@ -1061,8 +1061,8 @@ 3636766245U, // <1,3,7,2>: Cost 4 vext1 <2,1,3,7>, <2,1,3,7> 2867187903U, // <1,3,7,3>: Cost 3 vuzpr LHS, <5,7,u,3> 2625312102U, // <1,3,7,4>: Cost 3 vext2 <1,3,1,3>, <7,4,5,6> - 2662471056U, // <1,3,7,5>: Cost 3 vext2 <7,5,1,3>, <7,5,1,3> - 2625312262U, // <1,3,7,6>: Cost 3 vext2 <1,3,1,3>, <7,6,5,4> + 2867188598U, // <1,3,7,5>: Cost 3 vuzpr LHS, <6,7,4,5> + 3728250344U, // <1,3,7,6>: Cost 4 vext2 <6,2,1,3>, <7,6,2,1> 2867187880U, // <1,3,7,7>: Cost 3 vuzpr LHS, <5,7,5,7> 2707516171U, // <1,3,7,u>: Cost 3 vext3 <3,7,u,1>, <3,7,u,1> 1483317350U, // <1,3,u,0>: Cost 2 vext1 <1,1,3,u>, LHS @@ -1074,16 +1074,16 @@ 2819410758U, // <1,3,u,6>: Cost 3 vuzpr LHS, <3,u,5,6> 1745669673U, // <1,3,u,7>: Cost 2 vuzpr LHS, RHS 1745666722U, // <1,3,u,u>: Cost 2 vuzpr LHS, LHS - 2580955238U, // <1,4,0,0>: Cost 3 vext1 <5,1,4,0>, LHS + 2617352205U, // <1,4,0,0>: Cost 3 vext2 <0,0,1,4>, <0,0,1,4> 2619342950U, // <1,4,0,1>: Cost 3 vext2 <0,3,1,4>, LHS 3692421295U, // <1,4,0,2>: Cost 4 vext2 <0,2,1,4>, <0,2,1,4> 2619343104U, // <1,4,0,3>: Cost 3 vext2 <0,3,1,4>, <0,3,1,4> - 2580958518U, // <1,4,0,4>: Cost 3 vext1 <5,1,4,0>, RHS + 2617352530U, // <1,4,0,4>: Cost 3 vext2 <0,0,1,4>, <0,4,1,5> 1634880402U, // <1,4,0,5>: Cost 2 vext3 <4,0,5,1>, <4,0,5,1> 2713930652U, // <1,4,0,6>: Cost 3 vext3 <4,u,5,1>, <4,0,6,2> - 2256704532U, // <1,4,0,7>: Cost 3 vrev <7,0,4,1> + 3732898396U, // <1,4,0,7>: Cost 4 vext2 <7,0,1,4>, <0,7,4,1> 1635101613U, // <1,4,0,u>: Cost 2 vext3 <4,0,u,1>, <4,0,u,1> - 3763710902U, // <1,4,1,0>: Cost 4 vext3 <0,u,4,1>, <4,1,0,1> + 3693085430U, // <1,4,1,0>: Cost 4 vext2 <0,3,1,4>, <1,0,3,2> 2623988535U, // <1,4,1,1>: Cost 3 vext2 <1,1,1,4>, <1,1,1,4> 3693085590U, // <1,4,1,2>: Cost 4 vext2 <0,3,1,4>, <1,2,3,0> 3692422134U, // <1,4,1,3>: Cost 4 vext2 <0,2,1,4>, <1,3,4,6> @@ -1111,8 +1111,8 @@ 3666670695U, // <1,4,3,7>: Cost 4 vext1 <7,1,4,3>, <7,1,4,3> 3087843669U, // <1,4,3,u>: Cost 3 vtrnr LHS, <0,4,1,u> 2620672914U, // <1,4,4,0>: Cost 3 vext2 <0,5,1,4>, <4,0,5,1> - 3693087696U, // <1,4,4,1>: Cost 4 vext2 <0,3,1,4>, <4,1,3,0> - 3624871590U, // <1,4,4,2>: Cost 4 vext1 <0,1,4,4>, <2,3,0,1> + 3630842706U, // <1,4,4,1>: Cost 4 vext1 <1,1,4,4>, <1,1,4,4> + 3313069003U, // <1,4,4,2>: Cost 4 vrev <4,1,2,4> 3642788100U, // <1,4,4,3>: Cost 4 vext1 <3,1,4,4>, <3,1,4,4> 2713930960U, // <1,4,4,4>: Cost 3 vext3 <4,u,5,1>, <4,4,4,4> 2619346230U, // <1,4,4,5>: Cost 3 vext2 <0,3,1,4>, RHS @@ -1130,7 +1130,7 @@ 1616006472U, // <1,4,5,u>: Cost 2 vext3 <0,u,1,1>, RHS 2557116518U, // <1,4,6,0>: Cost 3 vext1 <1,1,4,6>, LHS 2557117236U, // <1,4,6,1>: Cost 3 vext1 <1,1,4,6>, <1,1,1,1> - 2698300764U, // <1,4,6,2>: Cost 3 vext3 <2,3,0,1>, <4,6,2,0> + 3630859880U, // <1,4,6,2>: Cost 4 vext1 <1,1,4,6>, <2,2,2,2> 2569062550U, // <1,4,6,3>: Cost 3 vext1 <3,1,4,6>, <3,0,1,2> 2557119798U, // <1,4,6,4>: Cost 3 vext1 <1,1,4,6>, RHS 3763490174U, // <1,4,6,5>: Cost 4 vext3 <0,u,1,1>, <4,6,5,7> @@ -1141,19 +1141,19 @@ 3732903040U, // <1,4,7,1>: Cost 4 vext2 <7,0,1,4>, <7,1,7,1> 3734230174U, // <1,4,7,2>: Cost 4 vext2 <7,2,1,4>, <7,2,1,4> 3734893807U, // <1,4,7,3>: Cost 4 vext2 <7,3,1,4>, <7,3,1,4> - 2622002534U, // <1,4,7,4>: Cost 3 vext2 <0,7,1,4>, <7,4,5,6> + 3660729654U, // <1,4,7,4>: Cost 4 vext1 <6,1,4,7>, RHS 3786493384U, // <1,4,7,5>: Cost 4 vext3 <4,6,7,1>, <4,7,5,0> 2713341394U, // <1,4,7,6>: Cost 3 vext3 <4,7,6,1>, <4,7,6,1> 3660731386U, // <1,4,7,7>: Cost 4 vext1 <6,1,4,7>, <7,0,1,2> 2664470148U, // <1,4,7,u>: Cost 3 vext2 <7,u,1,4>, <7,u,1,4> 2557132902U, // <1,4,u,0>: Cost 3 vext1 <1,1,4,u>, LHS 2619348782U, // <1,4,u,1>: Cost 3 vext2 <0,3,1,4>, LHS - 2232150111U, // <1,4,u,2>: Cost 3 vrev <2,u,4,1> - 2619343104U, // <1,4,u,3>: Cost 3 vext2 <0,3,1,4>, <0,3,1,4> + 2563106351U, // <1,4,u,2>: Cost 3 vext1 <2,1,4,u>, <2,1,4,u> + 2713783816U, // <1,4,u,3>: Cost 3 vext3 <4,u,3,1>, <4,u,3,1> 2622666815U, // <1,4,u,4>: Cost 3 vext2 <0,u,1,4>, 1640189466U, // <1,4,u,5>: Cost 2 vext3 <4,u,5,1>, <4,u,5,1> 1616006697U, // <1,4,u,6>: Cost 2 vext3 <0,u,1,1>, RHS - 2256704532U, // <1,4,u,7>: Cost 3 vrev <7,0,4,1> + 2712751498U, // <1,4,u,7>: Cost 3 vext3 <4,6,7,1>, <4,6,7,1> 1616006715U, // <1,4,u,u>: Cost 2 vext3 <0,u,1,1>, RHS 2620014592U, // <1,5,0,0>: Cost 3 vext2 <0,4,1,5>, <0,0,0,0> 1546272870U, // <1,5,0,1>: Cost 2 vext2 <0,4,1,5>, LHS @@ -1162,9 +1162,9 @@ 1546273106U, // <1,5,0,4>: Cost 2 vext2 <0,4,1,5>, <0,4,1,5> 2620678563U, // <1,5,0,5>: Cost 3 vext2 <0,5,1,5>, <0,5,1,5> 2714668660U, // <1,5,0,6>: Cost 3 vext3 <5,0,6,1>, <5,0,6,1> - 4167978294U, // <1,5,0,7>: Cost 4 vtrnr <1,1,u,0>, RHS + 3772042877U, // <1,5,0,7>: Cost 4 vext3 <2,3,0,1>, <5,0,7,1> 1546273437U, // <1,5,0,u>: Cost 2 vext2 <0,4,1,5>, LHS - 2713931407U, // <1,5,1,0>: Cost 3 vext3 <4,u,5,1>, <5,1,0,1> + 2620015350U, // <1,5,1,0>: Cost 3 vext2 <0,4,1,5>, <1,0,3,2> 2620015412U, // <1,5,1,1>: Cost 3 vext2 <0,4,1,5>, <1,1,1,1> 2620015510U, // <1,5,1,2>: Cost 3 vext2 <0,4,1,5>, <1,2,3,0> 2618688512U, // <1,5,1,3>: Cost 3 vext2 <0,2,1,5>, <1,3,5,7> @@ -1173,7 +1173,7 @@ 2620015859U, // <1,5,1,6>: Cost 3 vext2 <0,4,1,5>, <1,6,5,7> 3093728566U, // <1,5,1,7>: Cost 3 vtrnr <1,1,1,1>, RHS 2620015981U, // <1,5,1,u>: Cost 3 vext2 <0,4,1,5>, <1,u,1,3> - 3693757885U, // <1,5,2,0>: Cost 4 vext2 <0,4,1,5>, <2,0,1,2> + 3692430816U, // <1,5,2,0>: Cost 4 vext2 <0,2,1,5>, <2,0,5,1> 2620016163U, // <1,5,2,1>: Cost 3 vext2 <0,4,1,5>, <2,1,3,5> 2620016232U, // <1,5,2,2>: Cost 3 vext2 <0,4,1,5>, <2,2,2,2> 2620016294U, // <1,5,2,3>: Cost 3 vext2 <0,4,1,5>, <2,3,0,1> @@ -1184,24 +1184,24 @@ 2620016699U, // <1,5,2,u>: Cost 3 vext2 <0,4,1,5>, <2,u,0,1> 2620016790U, // <1,5,3,0>: Cost 3 vext2 <0,4,1,5>, <3,0,1,2> 2569110672U, // <1,5,3,1>: Cost 3 vext1 <3,1,5,3>, <1,5,3,7> - 2620016950U, // <1,5,3,2>: Cost 3 vext2 <0,4,1,5>, <3,2,1,0> + 3693758785U, // <1,5,3,2>: Cost 4 vext2 <0,4,1,5>, <3,2,2,2> 2620017052U, // <1,5,3,3>: Cost 3 vext2 <0,4,1,5>, <3,3,3,3> 2620017154U, // <1,5,3,4>: Cost 3 vext2 <0,4,1,5>, <3,4,5,6> 3135623172U, // <1,5,3,5>: Cost 3 vtrnr LHS, <5,5,5,5> 4161587048U, // <1,5,3,6>: Cost 4 vtrnr LHS, <2,5,3,6> 2014104886U, // <1,5,3,7>: Cost 2 vtrnr LHS, RHS 2014104887U, // <1,5,3,u>: Cost 2 vtrnr LHS, RHS - 2575089766U, // <1,5,4,0>: Cost 3 vext1 <4,1,5,4>, LHS + 2620017554U, // <1,5,4,0>: Cost 3 vext2 <0,4,1,5>, <4,0,5,1> 2620017634U, // <1,5,4,1>: Cost 3 vext2 <0,4,1,5>, <4,1,5,0> 3693759551U, // <1,5,4,2>: Cost 4 vext2 <0,4,1,5>, <4,2,6,3> - 3772632990U, // <1,5,4,3>: Cost 4 vext3 <2,3,u,1>, <5,4,3,2> + 3642861837U, // <1,5,4,3>: Cost 4 vext1 <3,1,5,4>, <3,1,5,4> 2575092710U, // <1,5,4,4>: Cost 3 vext1 <4,1,5,4>, <4,1,5,4> 1546276150U, // <1,5,4,5>: Cost 2 vext2 <0,4,1,5>, RHS 2759855414U, // <1,5,4,6>: Cost 3 vuzpl <1,3,5,7>, RHS - 4167494966U, // <1,5,4,7>: Cost 4 vtrnr <1,1,1,4>, RHS + 2713931718U, // <1,5,4,7>: Cost 3 vext3 <4,u,5,1>, <5,4,7,6> 1546276393U, // <1,5,4,u>: Cost 2 vext2 <0,4,1,5>, RHS 2557182054U, // <1,5,5,0>: Cost 3 vext1 <1,1,5,5>, LHS - 2620018354U, // <1,5,5,1>: Cost 3 vext2 <0,4,1,5>, <5,1,4,0> + 2557182812U, // <1,5,5,1>: Cost 3 vext1 <1,1,5,5>, <1,1,5,5> 3630925347U, // <1,5,5,2>: Cost 4 vext1 <1,1,5,5>, <2,1,3,5> 4029301675U, // <1,5,5,3>: Cost 4 vzipr <0,4,1,5>, <1,2,5,3> 2557185334U, // <1,5,5,4>: Cost 3 vext1 <1,1,5,5>, RHS @@ -1213,8 +1213,8 @@ 2620019115U, // <1,5,6,1>: Cost 3 vext2 <0,4,1,5>, <6,1,7,5> 2667794938U, // <1,5,6,2>: Cost 3 vext2 , <6,2,7,3> 3787673666U, // <1,5,6,3>: Cost 4 vext3 <4,u,5,1>, <5,6,3,4> - 3693761132U, // <1,5,6,4>: Cost 4 vext2 <0,4,1,5>, <6,4,2,0> - 3654823617U, // <1,5,6,5>: Cost 4 vext1 <5,1,5,6>, <5,1,5,6> + 3693761165U, // <1,5,6,4>: Cost 4 vext2 <0,4,1,5>, <6,4,5,6> + 3319279297U, // <1,5,6,5>: Cost 4 vrev <5,1,5,6> 2667795256U, // <1,5,6,6>: Cost 3 vext2 , <6,6,6,6> 2713931874U, // <1,5,6,7>: Cost 3 vext3 <4,u,5,1>, <5,6,7,0> 2713931883U, // <1,5,6,u>: Cost 3 vext3 <4,u,5,1>, <5,6,u,0> @@ -1224,12 +1224,12 @@ 2569144592U, // <1,5,7,3>: Cost 3 vext1 <3,1,5,7>, <3,1,5,7> 2557201718U, // <1,5,7,4>: Cost 3 vext1 <1,1,5,7>, RHS 2713931944U, // <1,5,7,5>: Cost 3 vext3 <4,u,5,1>, <5,7,5,7> - 2255451003U, // <1,5,7,6>: Cost 3 vrev <6,7,5,1> + 3787673770U, // <1,5,7,6>: Cost 4 vext3 <4,u,5,1>, <5,7,6,0> 2719387828U, // <1,5,7,7>: Cost 3 vext3 <5,7,7,1>, <5,7,7,1> 2557204270U, // <1,5,7,u>: Cost 3 vext1 <1,1,5,7>, LHS 2620020435U, // <1,5,u,0>: Cost 3 vext2 <0,4,1,5>, 1546278702U, // <1,5,u,1>: Cost 2 vext2 <0,4,1,5>, LHS - 2620020595U, // <1,5,u,2>: Cost 3 vext2 <0,4,1,5>, + 2620020616U, // <1,5,u,2>: Cost 3 vext2 <0,4,1,5>, 2620020668U, // <1,5,u,3>: Cost 3 vext2 <0,4,1,5>, 1594054682U, // <1,5,u,4>: Cost 2 vext2 , 1546279066U, // <1,5,u,5>: Cost 2 vext2 <0,4,1,5>, RHS @@ -1243,9 +1243,9 @@ 2620023122U, // <1,6,0,4>: Cost 3 vext2 <0,4,1,6>, <0,4,1,5> 2620686756U, // <1,6,0,5>: Cost 3 vext2 <0,5,1,6>, <0,5,1,6> 2621350389U, // <1,6,0,6>: Cost 3 vext2 <0,6,1,6>, <0,6,1,6> - 2972110134U, // <1,6,0,7>: Cost 3 vzipr <3,2,1,0>, RHS + 4028599606U, // <1,6,0,7>: Cost 4 vzipr <0,3,1,0>, RHS 2618696349U, // <1,6,0,u>: Cost 3 vext2 <0,2,1,6>, LHS - 3642908774U, // <1,6,1,0>: Cost 4 vext1 <3,1,6,1>, LHS + 3692438262U, // <1,6,1,0>: Cost 4 vext2 <0,2,1,6>, <1,0,3,2> 2625995572U, // <1,6,1,1>: Cost 3 vext2 <1,4,1,6>, <1,1,1,1> 3692438422U, // <1,6,1,2>: Cost 4 vext2 <0,2,1,6>, <1,2,3,0> 3692438488U, // <1,6,1,3>: Cost 4 vext2 <0,2,1,6>, <1,3,1,3> @@ -1258,7 +1258,7 @@ 3692439097U, // <1,6,2,1>: Cost 4 vext2 <0,2,1,6>, <2,1,6,0> 3692439144U, // <1,6,2,2>: Cost 4 vext2 <0,2,1,6>, <2,2,2,2> 3692439206U, // <1,6,2,3>: Cost 4 vext2 <0,2,1,6>, <2,3,0,1> - 3763491292U, // <1,6,2,4>: Cost 4 vext3 <0,u,1,1>, <6,2,4,0> + 3636948278U, // <1,6,2,4>: Cost 4 vext1 <2,1,6,2>, RHS 3787674092U, // <1,6,2,5>: Cost 4 vext3 <4,u,5,1>, <6,2,5,7> 2618697658U, // <1,6,2,6>: Cost 3 vext2 <0,2,1,6>, <2,6,3,7> 2970799414U, // <1,6,2,7>: Cost 3 vzipr <3,0,1,2>, RHS @@ -1272,26 +1272,26 @@ 2587103648U, // <1,6,3,6>: Cost 3 vext1 <6,1,6,3>, <6,1,6,3> 3087845306U, // <1,6,3,7>: Cost 3 vtrnr LHS, <2,6,3,7> 3087845307U, // <1,6,3,u>: Cost 3 vtrnr LHS, <2,6,3,u> - 3636961382U, // <1,6,4,0>: Cost 4 vext1 <2,1,6,4>, LHS + 3693767570U, // <1,6,4,0>: Cost 4 vext2 <0,4,1,6>, <4,0,5,1> 3693767650U, // <1,6,4,1>: Cost 4 vext2 <0,4,1,6>, <4,1,5,0> - 3763491436U, // <1,6,4,2>: Cost 4 vext3 <0,u,1,1>, <6,4,2,0> - 3309357574U, // <1,6,4,3>: Cost 4 vrev <3,4,6,1> + 3636962877U, // <1,6,4,2>: Cost 4 vext1 <2,1,6,4>, <2,1,6,4> + 3325088134U, // <1,6,4,3>: Cost 4 vrev <6,1,3,4> 3693767898U, // <1,6,4,4>: Cost 4 vext2 <0,4,1,6>, <4,4,5,5> 2618699062U, // <1,6,4,5>: Cost 3 vext2 <0,2,1,6>, RHS 3833670966U, // <1,6,4,6>: Cost 4 vuzpl <1,3,6,7>, RHS 4028632374U, // <1,6,4,7>: Cost 4 vzipr <0,3,1,4>, RHS 2618699305U, // <1,6,4,u>: Cost 3 vext2 <0,2,1,6>, RHS - 2575171686U, // <1,6,5,0>: Cost 3 vext1 <4,1,6,5>, LHS - 2575172608U, // <1,6,5,1>: Cost 3 vext1 <4,1,6,5>, <1,3,5,7> + 3693768264U, // <1,6,5,0>: Cost 4 vext2 <0,4,1,6>, <5,0,1,2> + 3630998373U, // <1,6,5,1>: Cost 4 vext1 <1,1,6,5>, <1,1,6,5> 3636971070U, // <1,6,5,2>: Cost 4 vext1 <2,1,6,5>, <2,1,6,5> 3642943767U, // <1,6,5,3>: Cost 4 vext1 <3,1,6,5>, <3,1,6,5> - 2575174640U, // <1,6,5,4>: Cost 3 vext1 <4,1,6,5>, <4,1,6,5> + 3693768628U, // <1,6,5,4>: Cost 4 vext2 <0,4,1,6>, <5,4,5,6> 3732918276U, // <1,6,5,5>: Cost 4 vext2 <7,0,1,6>, <5,5,5,5> 2620690530U, // <1,6,5,6>: Cost 3 vext2 <0,5,1,6>, <5,6,7,0> 2955562294U, // <1,6,5,7>: Cost 3 vzipr <0,4,1,5>, RHS 2955562295U, // <1,6,5,u>: Cost 3 vzipr <0,4,1,5>, RHS 2724180733U, // <1,6,6,0>: Cost 3 vext3 <6,6,0,1>, <6,6,0,1> - 3692441977U, // <1,6,6,1>: Cost 4 vext2 <0,2,1,6>, <6,1,2,0> + 3631006566U, // <1,6,6,1>: Cost 4 vext1 <1,1,6,6>, <1,1,6,6> 3631007674U, // <1,6,6,2>: Cost 4 vext1 <1,1,6,6>, <2,6,3,7> 3692442184U, // <1,6,6,3>: Cost 4 vext2 <0,2,1,6>, <6,3,7,0> 3631009078U, // <1,6,6,4>: Cost 4 vext1 <1,1,6,6>, RHS @@ -1322,14 +1322,14 @@ 3695100067U, // <1,7,0,2>: Cost 4 vext2 <0,6,1,7>, <0,2,0,1> 3707044102U, // <1,7,0,3>: Cost 4 vext2 <2,6,1,7>, <0,3,2,1> 2726466580U, // <1,7,0,4>: Cost 3 vext3 <7,0,4,1>, <7,0,4,1> - 3318722173U, // <1,7,0,5>: Cost 4 vrev <5,0,7,1> + 3654921933U, // <1,7,0,5>: Cost 4 vext1 <5,1,7,0>, <5,1,7,0> 2621358582U, // <1,7,0,6>: Cost 3 vext2 <0,6,1,7>, <0,6,1,7> 2622022215U, // <1,7,0,7>: Cost 3 vext2 <0,7,1,7>, <0,7,1,7> 2626667165U, // <1,7,0,u>: Cost 3 vext2 <1,5,1,7>, LHS 2593128550U, // <1,7,1,0>: Cost 3 vext1 <7,1,7,1>, LHS 2626667316U, // <1,7,1,1>: Cost 3 vext2 <1,5,1,7>, <1,1,1,1> 3700409238U, // <1,7,1,2>: Cost 4 vext2 <1,5,1,7>, <1,2,3,0> - 2727056476U, // <1,7,1,3>: Cost 3 vext3 <7,1,3,1>, <7,1,3,1> + 2257294428U, // <1,7,1,3>: Cost 3 vrev <7,1,3,1> 2593131830U, // <1,7,1,4>: Cost 3 vext1 <7,1,7,1>, RHS 2626667646U, // <1,7,1,5>: Cost 3 vext2 <1,5,1,7>, <1,5,1,7> 2627331279U, // <1,7,1,6>: Cost 3 vext2 <1,6,1,7>, <1,6,1,7> @@ -1355,38 +1355,38 @@ 1507465006U, // <1,7,3,u>: Cost 2 vext1 <5,1,7,3>, LHS 2728826164U, // <1,7,4,0>: Cost 3 vext3 <7,4,0,1>, <7,4,0,1> 3654951732U, // <1,7,4,1>: Cost 4 vext1 <5,1,7,4>, <1,1,1,1> - 3772044616U, // <1,7,4,2>: Cost 4 vext3 <2,3,0,1>, <7,4,2,3> - 3784136016U, // <1,7,4,3>: Cost 4 vext3 <4,3,2,1>, <7,4,3,2> + 3330987094U, // <1,7,4,2>: Cost 4 vrev <7,1,2,4> + 3331060831U, // <1,7,4,3>: Cost 4 vrev <7,1,3,4> 3787674971U, // <1,7,4,4>: Cost 4 vext3 <4,u,5,1>, <7,4,4,4> 2626669878U, // <1,7,4,5>: Cost 3 vext2 <1,5,1,7>, RHS 3785979241U, // <1,7,4,6>: Cost 4 vext3 <4,6,0,1>, <7,4,6,0> 3787085176U, // <1,7,4,7>: Cost 4 vext3 <4,7,6,1>, <7,4,7,6> 2626670121U, // <1,7,4,u>: Cost 3 vext2 <1,5,1,7>, RHS - 2587189350U, // <1,7,5,0>: Cost 3 vext1 <6,1,7,5>, LHS - 2662502096U, // <1,7,5,1>: Cost 3 vext2 <7,5,1,7>, <5,1,7,3> - 3660932643U, // <1,7,5,2>: Cost 4 vext1 <6,1,7,5>, <2,1,3,5> - 2236353120U, // <1,7,5,3>: Cost 3 vrev <3,5,7,1> - 2587192630U, // <1,7,5,4>: Cost 3 vext1 <6,1,7,5>, RHS + 2569273446U, // <1,7,5,0>: Cost 3 vext1 <3,1,7,5>, LHS + 2569274368U, // <1,7,5,1>: Cost 3 vext1 <3,1,7,5>, <1,3,5,7> + 3643016808U, // <1,7,5,2>: Cost 4 vext1 <3,1,7,5>, <2,2,2,2> + 2569275680U, // <1,7,5,3>: Cost 3 vext1 <3,1,7,5>, <3,1,7,5> + 2569276726U, // <1,7,5,4>: Cost 3 vext1 <3,1,7,5>, RHS 4102034790U, // <1,7,5,5>: Cost 4 vtrnl <1,3,5,7>, <7,4,5,6> 2651222067U, // <1,7,5,6>: Cost 3 vext2 <5,6,1,7>, <5,6,1,7> 3899378998U, // <1,7,5,7>: Cost 4 vuzpr <1,1,5,7>, RHS - 2652549333U, // <1,7,5,u>: Cost 3 vext2 <5,u,1,7>, <5,u,1,7> - 3643023462U, // <1,7,6,0>: Cost 4 vext1 <3,1,7,6>, LHS - 3701076390U, // <1,7,6,1>: Cost 4 vext2 <1,6,1,7>, <6,1,7,0> + 2569279278U, // <1,7,5,u>: Cost 3 vext1 <3,1,7,5>, LHS + 2730153430U, // <1,7,6,0>: Cost 3 vext3 <7,6,0,1>, <7,6,0,1> + 2724845022U, // <1,7,6,1>: Cost 3 vext3 <6,7,0,1>, <7,6,1,0> 3643025338U, // <1,7,6,2>: Cost 4 vext1 <3,1,7,6>, <2,6,3,7> 3643025697U, // <1,7,6,3>: Cost 4 vext1 <3,1,7,6>, <3,1,7,6> 3643026742U, // <1,7,6,4>: Cost 4 vext1 <3,1,7,6>, RHS - 2713933318U, // <1,7,6,5>: Cost 3 vext3 <4,u,5,1>, <7,6,5,4> + 3654971091U, // <1,7,6,5>: Cost 4 vext1 <5,1,7,6>, <5,1,7,6> 3787675153U, // <1,7,6,6>: Cost 4 vext3 <4,u,5,1>, <7,6,6,6> 2724845076U, // <1,7,6,7>: Cost 3 vext3 <6,7,0,1>, <7,6,7,0> - 2724845089U, // <1,7,6,u>: Cost 3 vext3 <6,7,0,1>, <7,6,u,4> + 2725508637U, // <1,7,6,u>: Cost 3 vext3 <6,u,0,1>, <7,6,u,0> 2730817063U, // <1,7,7,0>: Cost 3 vext3 <7,7,0,1>, <7,7,0,1> 3631088436U, // <1,7,7,1>: Cost 4 vext1 <1,1,7,7>, <1,1,1,1> 3660949158U, // <1,7,7,2>: Cost 4 vext1 <6,1,7,7>, <2,3,0,1> - 3311422210U, // <1,7,7,3>: Cost 4 vrev <3,7,7,1> + 3801904705U, // <1,7,7,3>: Cost 4 vext3 <7,3,0,1>, <7,7,3,0> 3631090998U, // <1,7,7,4>: Cost 4 vext1 <1,1,7,7>, RHS 2662503828U, // <1,7,7,5>: Cost 3 vext2 <7,5,1,7>, <7,5,1,7> - 3787675233U, // <1,7,7,6>: Cost 4 vext3 <4,u,5,1>, <7,7,6,5> + 3660951981U, // <1,7,7,6>: Cost 4 vext1 <6,1,7,7>, <6,1,7,7> 2713933420U, // <1,7,7,7>: Cost 3 vext3 <4,u,5,1>, <7,7,7,7> 2731406959U, // <1,7,7,u>: Cost 3 vext3 <7,7,u,1>, <7,7,u,1> 1507500134U, // <1,7,u,0>: Cost 2 vext1 <5,1,7,u>, LHS @@ -1405,7 +1405,7 @@ 1546297685U, // <1,u,0,4>: Cost 2 vext2 <0,4,1,u>, <0,4,1,u> 1658771190U, // <1,u,0,5>: Cost 2 vext3 , 2736789248U, // <1,u,0,6>: Cost 3 vext3 , - 2972110152U, // <1,u,0,7>: Cost 3 vzipr <3,2,1,0>, RHS + 2659189376U, // <1,u,0,7>: Cost 3 vext2 <7,0,1,u>, <0,7,u,1> 1546298013U, // <1,u,0,u>: Cost 2 vext2 <0,4,1,u>, LHS 1483112550U, // <1,u,1,0>: Cost 2 vext1 <1,1,1,1>, LHS 202162278U, // <1,u,1,1>: Cost 1 vdup1 LHS @@ -1417,7 +1417,7 @@ 2958183752U, // <1,u,1,7>: Cost 3 vzipr <0,u,1,1>, RHS 202162278U, // <1,u,1,u>: Cost 1 vdup1 LHS 2819449750U, // <1,u,2,0>: Cost 3 vuzpr LHS, <1,2,3,0> - 2689750899U, // <1,u,2,1>: Cost 3 vext3 <0,u,1,1>, + 2893207342U, // <1,u,2,1>: Cost 3 vzipl <1,2,3,0>, LHS 2819448996U, // <1,u,2,2>: Cost 3 vuzpr LHS, <0,2,0,2> 2819450482U, // <1,u,2,3>: Cost 3 vuzpr LHS, <2,2,3,3> 2819449754U, // <1,u,2,4>: Cost 3 vuzpr LHS, <1,2,3,4> @@ -1426,22 +1426,22 @@ 2970799432U, // <1,u,2,7>: Cost 3 vzipr <3,0,1,2>, RHS 2819449002U, // <1,u,2,u>: Cost 3 vuzpr LHS, <0,2,0,u> 403931292U, // <1,u,3,0>: Cost 1 vext1 LHS, LHS - 1477673780U, // <1,u,3,1>: Cost 2 vext1 LHS, <1,1,1,1> - 1477674600U, // <1,u,3,2>: Cost 2 vext1 LHS, <2,2,2,2> + 1477673718U, // <1,u,3,1>: Cost 2 vext1 LHS, <1,0,3,2> + 115726126U, // <1,u,3,2>: Cost 1 vrev LHS 2014102173U, // <1,u,3,3>: Cost 2 vtrnr LHS, LHS 403934518U, // <1,u,3,4>: Cost 1 vext1 LHS, RHS 1507536601U, // <1,u,3,5>: Cost 2 vext1 <5,1,u,3>, <5,1,u,3> 1525453306U, // <1,u,3,6>: Cost 2 vext1 LHS, <6,2,7,3> 2014105129U, // <1,u,3,7>: Cost 2 vtrnr LHS, RHS 403937070U, // <1,u,3,u>: Cost 1 vext1 LHS, LHS - 2569338982U, // <1,u,4,0>: Cost 3 vext1 <3,1,u,4>, LHS + 2620042157U, // <1,u,4,0>: Cost 3 vext2 <0,4,1,u>, <4,0,u,1> 2620042237U, // <1,u,4,1>: Cost 3 vext2 <0,4,1,u>, <4,1,u,0> - 2734135332U, // <1,u,4,2>: Cost 3 vext3 , + 2263217967U, // <1,u,4,2>: Cost 3 vrev 2569341224U, // <1,u,4,3>: Cost 3 vext1 <3,1,u,4>, <3,1,u,4> 2569342262U, // <1,u,4,4>: Cost 3 vext1 <3,1,u,4>, RHS 1546300726U, // <1,u,4,5>: Cost 2 vext2 <0,4,1,u>, RHS 2819449180U, // <1,u,4,6>: Cost 3 vuzpr LHS, <0,4,2,6> - 2259654012U, // <1,u,4,7>: Cost 3 vrev <7,4,u,1> + 2724845649U, // <1,u,4,7>: Cost 3 vext3 <6,7,0,1>, 1546300969U, // <1,u,4,u>: Cost 2 vext2 <0,4,1,u>, RHS 2551431270U, // <1,u,5,0>: Cost 3 vext1 <0,1,u,5>, LHS 2551432192U, // <1,u,5,1>: Cost 3 vext1 <0,1,u,5>, <1,3,5,7> @@ -1453,11 +1453,11 @@ 1745710390U, // <1,u,5,7>: Cost 2 vuzpr LHS, RHS 1745710391U, // <1,u,5,u>: Cost 2 vuzpr LHS, RHS 2653221159U, // <1,u,6,0>: Cost 3 vext2 <6,0,1,u>, <6,0,1,u> - 2557117236U, // <1,u,6,1>: Cost 3 vext1 <1,1,4,6>, <1,1,1,1> - 2231117793U, // <1,u,6,2>: Cost 3 vrev <2,6,u,1> + 2725509303U, // <1,u,6,1>: Cost 3 vext3 <6,u,0,1>, + 2659193338U, // <1,u,6,2>: Cost 3 vext2 <7,0,1,u>, <6,2,7,3> 2689751248U, // <1,u,6,3>: Cost 3 vext3 <0,u,1,1>, - 2243063187U, // <1,u,6,4>: Cost 3 vrev <4,6,u,1> - 2713934047U, // <1,u,6,5>: Cost 3 vext3 <4,u,5,1>, + 2867228774U, // <1,u,6,4>: Cost 3 vuzpr LHS, <5,6,7,4> + 3764820194U, // <1,u,6,5>: Cost 4 vext3 <1,1,1,1>, 2657202957U, // <1,u,6,6>: Cost 3 vext2 <6,6,1,u>, <6,6,1,u> 2819450810U, // <1,u,6,7>: Cost 3 vuzpr LHS, <2,6,3,7> 2819450811U, // <1,u,6,u>: Cost 3 vuzpr LHS, <2,6,3,u> @@ -1466,13 +1466,13 @@ 2569365158U, // <1,u,7,2>: Cost 3 vext1 <3,1,u,7>, <2,3,0,1> 2569365803U, // <1,u,7,3>: Cost 3 vext1 <3,1,u,7>, <3,1,u,7> 2557422902U, // <1,u,7,4>: Cost 3 vext1 <1,1,u,7>, RHS - 2249699517U, // <1,u,7,5>: Cost 3 vrev <5,7,u,1> - 1181930390U, // <1,u,7,6>: Cost 2 vrev <6,7,u,1> + 2662512021U, // <1,u,7,5>: Cost 3 vext2 <7,5,1,u>, <7,5,1,u> + 2724845884U, // <1,u,7,6>: Cost 3 vext3 <6,7,0,1>, 2659194476U, // <1,u,7,7>: Cost 3 vext2 <7,0,1,u>, <7,7,7,7> 1590761096U, // <1,u,7,u>: Cost 2 vext2 <7,u,1,u>, <7,u,1,u> 403972257U, // <1,u,u,0>: Cost 1 vext1 LHS, LHS 202162278U, // <1,u,u,1>: Cost 1 vdup1 LHS - 1477715560U, // <1,u,u,2>: Cost 2 vext1 LHS, <2,2,2,2> + 115767091U, // <1,u,u,2>: Cost 1 vrev LHS 1745707677U, // <1,u,u,3>: Cost 2 vuzpr LHS, LHS 403975478U, // <1,u,u,4>: Cost 1 vext1 LHS, RHS 1546303642U, // <1,u,u,5>: Cost 2 vext2 <0,4,1,u>, RHS @@ -1482,14 +1482,14 @@ 2551463936U, // <2,0,0,0>: Cost 3 vext1 <0,2,0,0>, <0,0,0,0> 2685698058U, // <2,0,0,1>: Cost 3 vext3 <0,2,0,2>, <0,0,1,1> 1610776596U, // <2,0,0,2>: Cost 2 vext3 <0,0,2,2>, <0,0,2,2> - 2232526989U, // <2,0,0,3>: Cost 3 vrev <3,0,0,2> + 2619384069U, // <2,0,0,3>: Cost 3 vext2 <0,3,2,0>, <0,3,2,0> 2551467318U, // <2,0,0,4>: Cost 3 vext1 <0,2,0,0>, RHS 3899836596U, // <2,0,0,5>: Cost 4 vuzpr <1,2,3,0>, <3,0,4,5> 2621374968U, // <2,0,0,6>: Cost 3 vext2 <0,6,2,0>, <0,6,2,0> - 2256417777U, // <2,0,0,7>: Cost 3 vrev <7,0,0,2> + 4168271334U, // <2,0,0,7>: Cost 4 vtrnr <1,2,3,0>, <2,0,5,7> 1611219018U, // <2,0,0,u>: Cost 2 vext3 <0,0,u,2>, <0,0,u,2> 2551472138U, // <2,0,1,0>: Cost 3 vext1 <0,2,0,1>, <0,0,1,1> - 2685108316U, // <2,0,1,1>: Cost 3 vext3 <0,1,1,2>, <0,1,1,2> + 2690564186U, // <2,0,1,1>: Cost 3 vext3 <1,0,3,2>, <0,1,1,0> 1611956326U, // <2,0,1,2>: Cost 2 vext3 <0,2,0,2>, LHS 2826092646U, // <2,0,1,3>: Cost 3 vuzpr <1,2,3,0>, LHS 2551475510U, // <2,0,1,4>: Cost 3 vext1 <0,2,0,1>, RHS @@ -1498,7 +1498,7 @@ 3661050874U, // <2,0,1,7>: Cost 4 vext1 <6,2,0,1>, <7,0,1,2> 1611956380U, // <2,0,1,u>: Cost 2 vext3 <0,2,0,2>, LHS 1477738598U, // <2,0,2,0>: Cost 2 vext1 <0,2,0,2>, LHS - 2551481140U, // <2,0,2,1>: Cost 3 vext1 <0,2,0,2>, <1,1,1,1> + 2551481078U, // <2,0,2,1>: Cost 3 vext1 <0,2,0,2>, <1,0,3,2> 2551481796U, // <2,0,2,2>: Cost 3 vext1 <0,2,0,2>, <2,0,2,0> 2551482518U, // <2,0,2,3>: Cost 3 vext1 <0,2,0,2>, <3,0,1,2> 1477741878U, // <2,0,2,4>: Cost 2 vext1 <0,2,0,2>, RHS @@ -1509,7 +1509,7 @@ 2953625600U, // <2,0,3,0>: Cost 3 vzipr LHS, <0,0,0,0> 2953627302U, // <2,0,3,1>: Cost 3 vzipr LHS, <2,3,0,1> 2953625764U, // <2,0,3,2>: Cost 3 vzipr LHS, <0,2,0,2> - 3625232534U, // <2,0,3,3>: Cost 4 vext1 <0,2,0,3>, <3,0,1,2> + 4027369695U, // <2,0,3,3>: Cost 4 vzipr LHS, <3,1,0,3> 3625233718U, // <2,0,3,4>: Cost 4 vext1 <0,2,0,3>, RHS 3899836110U, // <2,0,3,5>: Cost 4 vuzpr <1,2,3,0>, <2,3,4,5> 4032012618U, // <2,0,3,6>: Cost 4 vzipr LHS, <0,4,0,6> @@ -1525,32 +1525,32 @@ 3799990664U, // <2,0,4,7>: Cost 4 vext3 <7,0,1,2>, <0,4,7,5> 2685698450U, // <2,0,4,u>: Cost 3 vext3 <0,2,0,2>, <0,4,u,6> 3625246822U, // <2,0,5,0>: Cost 4 vext1 <0,2,0,5>, LHS - 3297641584U, // <2,0,5,1>: Cost 4 vrev <1,5,0,2> - 2702361006U, // <2,0,5,2>: Cost 3 vext3 <3,0,1,2>, <0,5,2,7> - 3643164978U, // <2,0,5,3>: Cost 4 vext1 <3,2,0,5>, <3,2,0,5> - 3625250102U, // <2,0,5,4>: Cost 4 vext1 <0,2,0,5>, RHS - 3719008260U, // <2,0,5,5>: Cost 4 vext2 <4,6,2,0>, <5,5,5,5> - 3719008354U, // <2,0,5,6>: Cost 4 vext2 <4,6,2,0>, <5,6,7,0> + 3289776304U, // <2,0,5,1>: Cost 4 vrev <0,2,1,5> + 2690564526U, // <2,0,5,2>: Cost 3 vext3 <1,0,3,2>, <0,5,2,7> + 3289923778U, // <2,0,5,3>: Cost 4 vrev <0,2,3,5> + 2216255691U, // <2,0,5,4>: Cost 3 vrev <0,2,4,5> + 3726307332U, // <2,0,5,5>: Cost 4 vext2 <5,u,2,0>, <5,5,5,5> + 3726307426U, // <2,0,5,6>: Cost 4 vext2 <5,u,2,0>, <5,6,7,0> 2826095926U, // <2,0,5,7>: Cost 3 vuzpr <1,2,3,0>, RHS - 2826095927U, // <2,0,5,u>: Cost 3 vuzpr <1,2,3,0>, RHS + 2216550639U, // <2,0,5,u>: Cost 3 vrev <0,2,u,5> 4162420736U, // <2,0,6,0>: Cost 4 vtrnr <0,2,4,6>, <0,0,0,0> 2901885030U, // <2,0,6,1>: Cost 3 vzipl <2,6,3,7>, LHS 2685698559U, // <2,0,6,2>: Cost 3 vext3 <0,2,0,2>, <0,6,2,7> - 3310250611U, // <2,0,6,3>: Cost 4 vrev <3,6,0,2> - 2242481484U, // <2,0,6,4>: Cost 3 vrev <4,6,0,2> - 3322196005U, // <2,0,6,5>: Cost 4 vrev <5,6,0,2> - 3719009080U, // <2,0,6,6>: Cost 4 vext2 <4,6,2,0>, <6,6,6,6> - 2621379406U, // <2,0,6,7>: Cost 3 vext2 <0,6,2,0>, <6,7,0,1> - 2901885597U, // <2,0,6,u>: Cost 3 vzipl <2,6,3,7>, LHS + 3643173171U, // <2,0,6,3>: Cost 4 vext1 <3,2,0,6>, <3,2,0,6> + 2216263884U, // <2,0,6,4>: Cost 3 vrev <0,2,4,6> + 3730289341U, // <2,0,6,5>: Cost 4 vext2 <6,5,2,0>, <6,5,2,0> + 3726308152U, // <2,0,6,6>: Cost 4 vext2 <5,u,2,0>, <6,6,6,6> + 3899836346U, // <2,0,6,7>: Cost 4 vuzpr <1,2,3,0>, <2,6,3,7> + 2216558832U, // <2,0,6,u>: Cost 3 vrev <0,2,u,6> 2659202049U, // <2,0,7,0>: Cost 3 vext2 <7,0,2,0>, <7,0,2,0> - 2726249024U, // <2,0,7,1>: Cost 3 vext3 <7,0,1,2>, <0,7,1,0> + 3726308437U, // <2,0,7,1>: Cost 4 vext2 <5,u,2,0>, <7,1,2,3> 2726249034U, // <2,0,7,2>: Cost 3 vext3 <7,0,1,2>, <0,7,2,1> - 3310914244U, // <2,0,7,3>: Cost 4 vrev <3,7,0,2> - 3719009638U, // <2,0,7,4>: Cost 4 vext2 <4,6,2,0>, <7,4,5,6> - 3322859638U, // <2,0,7,5>: Cost 4 vrev <5,7,0,2> - 2255090511U, // <2,0,7,6>: Cost 3 vrev <6,7,0,2> - 3719009900U, // <2,0,7,7>: Cost 4 vext2 <4,6,2,0>, <7,7,7,7> - 2267035905U, // <2,0,7,u>: Cost 3 vrev + 3734934772U, // <2,0,7,3>: Cost 4 vext2 <7,3,2,0>, <7,3,2,0> + 3726308710U, // <2,0,7,4>: Cost 4 vext2 <5,u,2,0>, <7,4,5,6> + 3726308814U, // <2,0,7,5>: Cost 4 vext2 <5,u,2,0>, <7,5,u,2> + 3736925671U, // <2,0,7,6>: Cost 4 vext2 <7,6,2,0>, <7,6,2,0> + 3726308972U, // <2,0,7,7>: Cost 4 vext2 <5,u,2,0>, <7,7,7,7> + 2659202049U, // <2,0,7,u>: Cost 3 vext2 <7,0,2,0>, <7,0,2,0> 1477787750U, // <2,0,u,0>: Cost 2 vext1 <0,2,0,u>, LHS 2953668262U, // <2,0,u,1>: Cost 3 vzipr LHS, <2,3,0,1> 1611956893U, // <2,0,u,2>: Cost 2 vext3 <0,2,0,2>, LHS @@ -1560,22 +1560,22 @@ 2765412506U, // <2,0,u,6>: Cost 3 vuzpl <2,3,0,1>, RHS 2826096169U, // <2,0,u,7>: Cost 3 vuzpr <1,2,3,0>, RHS 1611956947U, // <2,0,u,u>: Cost 2 vext3 <0,2,0,2>, LHS - 1495711846U, // <2,1,0,0>: Cost 2 vext1 <3,2,1,0>, LHS + 2569453670U, // <2,1,0,0>: Cost 3 vext1 <3,2,1,0>, LHS 2619392102U, // <2,1,0,1>: Cost 3 vext2 <0,3,2,1>, LHS - 2226628029U, // <2,1,0,2>: Cost 3 vrev <2,0,1,2> - 1158858902U, // <2,1,0,3>: Cost 2 vrev <3,0,1,2> - 1495715126U, // <2,1,0,4>: Cost 2 vext1 <3,2,1,0>, RHS - 2244546120U, // <2,1,0,5>: Cost 3 vrev <5,0,1,2> - 2250518817U, // <2,1,0,6>: Cost 3 vrev <6,0,1,2> - 1182749690U, // <2,1,0,7>: Cost 2 vrev <7,0,1,2> - 1495717678U, // <2,1,0,u>: Cost 2 vext1 <3,2,1,0>, LHS + 3759440619U, // <2,1,0,2>: Cost 4 vext3 <0,2,0,2>, <1,0,2,0> + 1616823030U, // <2,1,0,3>: Cost 2 vext3 <1,0,3,2>, <1,0,3,2> + 2569456950U, // <2,1,0,4>: Cost 3 vext1 <3,2,1,0>, RHS + 2690712328U, // <2,1,0,5>: Cost 3 vext3 <1,0,5,2>, <1,0,5,2> + 3661115841U, // <2,1,0,6>: Cost 4 vext1 <6,2,1,0>, <6,2,1,0> + 2622046794U, // <2,1,0,7>: Cost 3 vext2 <0,7,2,1>, <0,7,2,1> + 1617191715U, // <2,1,0,u>: Cost 2 vext3 <1,0,u,2>, <1,0,u,2> 2551545958U, // <2,1,1,0>: Cost 3 vext1 <0,2,1,1>, LHS 2685698868U, // <2,1,1,1>: Cost 3 vext3 <0,2,0,2>, <1,1,1,1> - 2643280794U, // <2,1,1,2>: Cost 3 vext2 <4,3,2,1>, <1,2,3,4> + 2628682646U, // <2,1,1,2>: Cost 3 vext2 <1,u,2,1>, <1,2,3,0> 2685698888U, // <2,1,1,3>: Cost 3 vext3 <0,2,0,2>, <1,1,3,3> 2551549238U, // <2,1,1,4>: Cost 3 vext1 <0,2,1,1>, RHS 3693134992U, // <2,1,1,5>: Cost 4 vext2 <0,3,2,1>, <1,5,3,7> - 3711050950U, // <2,1,1,6>: Cost 4 vext2 <3,3,2,1>, <1,6,0,7> + 3661124034U, // <2,1,1,6>: Cost 4 vext1 <6,2,1,1>, <6,2,1,1> 3625292794U, // <2,1,1,7>: Cost 4 vext1 <0,2,1,1>, <7,0,1,2> 2685698933U, // <2,1,1,u>: Cost 3 vext3 <0,2,0,2>, <1,1,u,3> 2551554150U, // <2,1,2,0>: Cost 3 vext1 <0,2,1,2>, LHS @@ -1587,7 +1587,7 @@ 3693135802U, // <2,1,2,6>: Cost 4 vext2 <0,3,2,1>, <2,6,3,7> 2726249402U, // <2,1,2,7>: Cost 3 vext3 <7,0,1,2>, <1,2,7,0> 2685699011U, // <2,1,2,u>: Cost 3 vext3 <0,2,0,2>, <1,2,u,0> - 2953627958U, // <2,1,3,0>: Cost 3 vzipr LHS, <3,2,1,0> + 2551562342U, // <2,1,3,0>: Cost 3 vext1 <0,2,1,3>, LHS 2953625610U, // <2,1,3,1>: Cost 3 vzipr LHS, <0,0,1,1> 2953627798U, // <2,1,3,2>: Cost 3 vzipr LHS, <3,0,1,2> 2953626584U, // <2,1,3,3>: Cost 3 vzipr LHS, <1,3,1,3> @@ -1596,80 +1596,80 @@ 2587398596U, // <2,1,3,6>: Cost 3 vext1 <6,2,1,3>, <6,2,1,3> 4032013519U, // <2,1,3,7>: Cost 4 vzipr LHS, <1,6,1,7> 2953625617U, // <2,1,3,u>: Cost 3 vzipr LHS, <0,0,1,u> - 3625312358U, // <2,1,4,0>: Cost 4 vext1 <0,2,1,4>, LHS + 2690565154U, // <2,1,4,0>: Cost 3 vext3 <1,0,3,2>, <1,4,0,5> 3625313270U, // <2,1,4,1>: Cost 4 vext1 <0,2,1,4>, <1,3,4,6> 3771532340U, // <2,1,4,2>: Cost 4 vext3 <2,2,2,2>, <1,4,2,5> - 3094560870U, // <2,1,4,3>: Cost 3 vtrnr <1,2,3,4>, LHS + 1148404634U, // <2,1,4,3>: Cost 2 vrev <1,2,3,4> 3625315638U, // <2,1,4,4>: Cost 4 vext1 <0,2,1,4>, RHS 2619395382U, // <2,1,4,5>: Cost 3 vext2 <0,3,2,1>, RHS 3837242678U, // <2,1,4,6>: Cost 4 vuzpl <2,0,1,2>, RHS 3799991394U, // <2,1,4,7>: Cost 4 vext3 <7,0,1,2>, <1,4,7,6> - 2619395625U, // <2,1,4,u>: Cost 3 vext2 <0,3,2,1>, RHS + 1148773319U, // <2,1,4,u>: Cost 2 vrev <1,2,u,4> 2551578726U, // <2,1,5,0>: Cost 3 vext1 <0,2,1,5>, LHS 2551579648U, // <2,1,5,1>: Cost 3 vext1 <0,2,1,5>, <1,3,5,7> - 3625322032U, // <2,1,5,2>: Cost 4 vext1 <0,2,1,5>, <2,1,5,0> + 3625321952U, // <2,1,5,2>: Cost 4 vext1 <0,2,1,5>, <2,0,5,1> 2685699216U, // <2,1,5,3>: Cost 3 vext3 <0,2,0,2>, <1,5,3,7> 2551582006U, // <2,1,5,4>: Cost 3 vext1 <0,2,1,5>, RHS - 3625324192U, // <2,1,5,5>: Cost 4 vext1 <0,2,1,5>, <5,1,2,0> - 3720343650U, // <2,1,5,6>: Cost 4 vext2 <4,u,2,1>, <5,6,7,0> + 3740913668U, // <2,1,5,5>: Cost 4 vext2 , <5,5,5,5> + 3661156806U, // <2,1,5,6>: Cost 4 vext1 <6,2,1,5>, <6,2,1,5> 3893652790U, // <2,1,5,7>: Cost 4 vuzpr <0,2,0,1>, RHS 2685699261U, // <2,1,5,u>: Cost 3 vext3 <0,2,0,2>, <1,5,u,7> 2551586918U, // <2,1,6,0>: Cost 3 vext1 <0,2,1,6>, LHS - 3625329460U, // <2,1,6,1>: Cost 4 vext1 <0,2,1,6>, <1,1,1,1> + 3625329398U, // <2,1,6,1>: Cost 4 vext1 <0,2,1,6>, <1,0,3,2> 2551588794U, // <2,1,6,2>: Cost 3 vext1 <0,2,1,6>, <2,6,3,7> 3088679014U, // <2,1,6,3>: Cost 3 vtrnr <0,2,4,6>, LHS 2551590198U, // <2,1,6,4>: Cost 3 vext1 <0,2,1,6>, RHS 4029382994U, // <2,1,6,5>: Cost 4 vzipr <0,4,2,6>, <0,4,1,5> - 3625333113U, // <2,1,6,6>: Cost 4 vext1 <0,2,1,6>, <6,1,2,0> - 3720344398U, // <2,1,6,7>: Cost 4 vext2 <4,u,2,1>, <6,7,0,1> + 3625333560U, // <2,1,6,6>: Cost 4 vext1 <0,2,1,6>, <6,6,6,6> + 3731624800U, // <2,1,6,7>: Cost 4 vext2 <6,7,2,1>, <6,7,2,1> 2551592750U, // <2,1,6,u>: Cost 3 vext1 <0,2,1,6>, LHS 2622051322U, // <2,1,7,0>: Cost 3 vext2 <0,7,2,1>, <7,0,1,2> 3733615699U, // <2,1,7,1>: Cost 4 vext2 <7,1,2,1>, <7,1,2,1> 3795125538U, // <2,1,7,2>: Cost 4 vext3 <6,1,7,2>, <1,7,2,0> - 2661201141U, // <2,1,7,3>: Cost 3 vext2 <7,3,2,1>, <7,3,2,1> - 3316960678U, // <2,1,7,4>: Cost 4 vrev <4,7,1,2> - 3322933375U, // <2,1,7,5>: Cost 4 vrev <5,7,1,2> - 2255164248U, // <2,1,7,6>: Cost 3 vrev <6,7,1,2> - 3720345196U, // <2,1,7,7>: Cost 4 vext2 <4,u,2,1>, <7,7,7,7> - 2664519306U, // <2,1,7,u>: Cost 3 vext2 <7,u,2,1>, <7,u,2,1> - 1525637222U, // <2,1,u,0>: Cost 2 vext1 , LHS + 2222171037U, // <2,1,7,3>: Cost 3 vrev <1,2,3,7> + 3740915046U, // <2,1,7,4>: Cost 4 vext2 , <7,4,5,6> + 3296060335U, // <2,1,7,5>: Cost 4 vrev <1,2,5,7> + 3736933864U, // <2,1,7,6>: Cost 4 vext2 <7,6,2,1>, <7,6,2,1> + 3805300055U, // <2,1,7,7>: Cost 4 vext3 <7,u,1,2>, <1,7,7,u> + 2669827714U, // <2,1,7,u>: Cost 3 vext2 , <7,u,1,2> + 2551603302U, // <2,1,u,0>: Cost 3 vext1 <0,2,1,u>, LHS 2953666570U, // <2,1,u,1>: Cost 3 vzipr LHS, <0,0,1,1> 2953668758U, // <2,1,u,2>: Cost 3 vzipr LHS, <3,0,1,2> - 1164167966U, // <2,1,u,3>: Cost 2 vrev <3,u,1,2> - 1525640502U, // <2,1,u,4>: Cost 2 vext1 , RHS + 1148437406U, // <2,1,u,3>: Cost 2 vrev <1,2,3,u> + 2551606582U, // <2,1,u,4>: Cost 3 vext1 <0,2,1,u>, RHS 2953666898U, // <2,1,u,5>: Cost 3 vzipr LHS, <0,4,1,5> - 2587439561U, // <2,1,u,6>: Cost 3 vext1 <6,2,1,u>, <6,2,1,u> - 1188058754U, // <2,1,u,7>: Cost 2 vrev <7,u,1,2> - 1525643131U, // <2,1,u,u>: Cost 2 vext1 , + 2587398596U, // <2,1,u,6>: Cost 3 vext1 <6,2,1,3>, <6,2,1,3> + 2669828370U, // <2,1,u,7>: Cost 3 vext2 , + 1148806091U, // <2,1,u,u>: Cost 2 vrev <1,2,u,u> 1543667732U, // <2,2,0,0>: Cost 2 vext2 <0,0,2,2>, <0,0,2,2> 1548976230U, // <2,2,0,1>: Cost 2 vext2 <0,u,2,2>, LHS 2685699524U, // <2,2,0,2>: Cost 3 vext3 <0,2,0,2>, <2,0,2,0> 2685699535U, // <2,2,0,3>: Cost 3 vext3 <0,2,0,2>, <2,0,3,2> 2551614774U, // <2,2,0,4>: Cost 3 vext1 <0,2,2,0>, RHS - 3771532774U, // <2,2,0,5>: Cost 4 vext3 <2,2,2,2>, <2,0,5,7> + 3704422830U, // <2,2,0,5>: Cost 4 vext2 <2,2,2,2>, <0,5,2,7> 3893657642U, // <2,2,0,6>: Cost 4 vuzpr <0,2,0,2>, <0,0,4,6> 3770574323U, // <2,2,0,7>: Cost 4 vext3 <2,0,7,2>, <2,0,7,2> 1548976796U, // <2,2,0,u>: Cost 2 vext2 <0,u,2,2>, <0,u,2,2> - 2702362118U, // <2,2,1,0>: Cost 3 vext3 <3,0,1,2>, <2,1,0,3> + 2622718710U, // <2,2,1,0>: Cost 3 vext2 <0,u,2,2>, <1,0,3,2> 2622718772U, // <2,2,1,1>: Cost 3 vext2 <0,u,2,2>, <1,1,1,1> 2622718870U, // <2,2,1,2>: Cost 3 vext2 <0,u,2,2>, <1,2,3,0> 2819915878U, // <2,2,1,3>: Cost 3 vuzpr <0,2,0,2>, LHS 3625364790U, // <2,2,1,4>: Cost 4 vext1 <0,2,2,1>, RHS 2622719120U, // <2,2,1,5>: Cost 3 vext2 <0,u,2,2>, <1,5,3,7> 3760031292U, // <2,2,1,6>: Cost 4 vext3 <0,2,u,2>, <2,1,6,3> - 3798664776U, // <2,2,1,7>: Cost 4 vext3 <6,7,1,2>, <2,1,7,6> + 3667170468U, // <2,2,1,7>: Cost 4 vext1 <7,2,2,1>, <7,2,2,1> 2819915883U, // <2,2,1,u>: Cost 3 vuzpr <0,2,0,2>, LHS 1489829990U, // <2,2,2,0>: Cost 2 vext1 <2,2,2,2>, LHS - 2563572532U, // <2,2,2,1>: Cost 3 vext1 <2,2,2,2>, <1,1,1,1> + 2563572470U, // <2,2,2,1>: Cost 3 vext1 <2,2,2,2>, <1,0,3,2> 269271142U, // <2,2,2,2>: Cost 1 vdup2 LHS 2685699698U, // <2,2,2,3>: Cost 3 vext3 <0,2,0,2>, <2,2,3,3> 1489833270U, // <2,2,2,4>: Cost 2 vext1 <2,2,2,2>, RHS 2685699720U, // <2,2,2,5>: Cost 3 vext3 <0,2,0,2>, <2,2,5,7> 2622719930U, // <2,2,2,6>: Cost 3 vext2 <0,u,2,2>, <2,6,3,7> - 2257892517U, // <2,2,2,7>: Cost 3 vrev <7,2,2,2> + 2593436837U, // <2,2,2,7>: Cost 3 vext1 <7,2,2,2>, <7,2,2,2> 269271142U, // <2,2,2,u>: Cost 1 vdup2 LHS 2685699750U, // <2,2,3,0>: Cost 3 vext3 <0,2,0,2>, <2,3,0,1> - 2698380976U, // <2,2,3,1>: Cost 3 vext3 <2,3,1,2>, <2,3,1,2> + 2690565806U, // <2,2,3,1>: Cost 3 vext3 <1,0,3,2>, <2,3,1,0> 2953627240U, // <2,2,3,2>: Cost 3 vzipr LHS, <2,2,2,2> 1879883878U, // <2,2,3,3>: Cost 2 vzipr LHS, LHS 2685699790U, // <2,2,3,4>: Cost 3 vext3 <0,2,0,2>, <2,3,4,5> @@ -1678,7 +1678,7 @@ 2593445030U, // <2,2,3,7>: Cost 3 vext1 <7,2,2,3>, <7,2,2,3> 1879883883U, // <2,2,3,u>: Cost 2 vzipr LHS, LHS 2551644262U, // <2,2,4,0>: Cost 3 vext1 <0,2,2,4>, LHS - 3625386804U, // <2,2,4,1>: Cost 4 vext1 <0,2,2,4>, <1,1,1,1> + 3625386742U, // <2,2,4,1>: Cost 4 vext1 <0,2,2,4>, <1,0,3,2> 2551645902U, // <2,2,4,2>: Cost 3 vext1 <0,2,2,4>, <2,3,4,5> 3759441686U, // <2,2,4,3>: Cost 4 vext3 <0,2,0,2>, <2,4,3,5> 2551647542U, // <2,2,4,4>: Cost 3 vext1 <0,2,2,4>, RHS @@ -1690,7 +1690,7 @@ 2617413328U, // <2,2,5,1>: Cost 3 vext2 <0,0,2,2>, <5,1,7,3> 2685699936U, // <2,2,5,2>: Cost 3 vext3 <0,2,0,2>, <2,5,2,7> 4027383910U, // <2,2,5,3>: Cost 4 vzipr <0,1,2,5>, LHS - 3696463796U, // <2,2,5,4>: Cost 4 vext2 <0,u,2,2>, <5,4,5,6> + 2228201085U, // <2,2,5,4>: Cost 3 vrev <2,2,4,5> 2617413636U, // <2,2,5,5>: Cost 3 vext2 <0,0,2,2>, <5,5,5,5> 2617413730U, // <2,2,5,6>: Cost 3 vext2 <0,0,2,2>, <5,6,7,0> 2819919158U, // <2,2,5,7>: Cost 3 vuzpr <0,2,0,2>, RHS @@ -1709,8 +1709,8 @@ 2660545701U, // <2,2,7,2>: Cost 3 vext2 <7,2,2,2>, <7,2,2,2> 4030718054U, // <2,2,7,3>: Cost 4 vzipr <0,6,2,7>, LHS 2617415014U, // <2,2,7,4>: Cost 3 vext2 <0,0,2,2>, <7,4,5,6> - 3704427936U, // <2,2,7,5>: Cost 4 vext2 <2,2,2,2>, <7,5,3,1> - 2255237985U, // <2,2,7,6>: Cost 3 vrev <6,7,2,2> + 3302033032U, // <2,2,7,5>: Cost 4 vrev <2,2,5,7> + 3661246929U, // <2,2,7,6>: Cost 4 vext1 <6,2,2,7>, <6,2,2,7> 2617415276U, // <2,2,7,7>: Cost 3 vext2 <0,0,2,2>, <7,7,7,7> 2731558962U, // <2,2,7,u>: Cost 3 vext3 <7,u,1,2>, <2,7,u,1> 1489829990U, // <2,2,u,0>: Cost 2 vext1 <2,2,2,2>, LHS @@ -1731,7 +1731,7 @@ 2622726655U, // <2,3,0,6>: Cost 3 vext2 LHS, <0,6,2,7> 2593494188U, // <2,3,0,7>: Cost 3 vext1 <7,2,3,0>, <7,2,3,0> 470598301U, // <2,3,0,u>: Cost 1 vext2 LHS, LHS - 2551693414U, // <2,3,1,0>: Cost 3 vext1 <0,2,3,1>, LHS + 1544340214U, // <2,3,1,0>: Cost 2 vext2 LHS, <1,0,3,2> 1544340276U, // <2,3,1,1>: Cost 2 vext2 LHS, <1,1,1,1> 1544340374U, // <2,3,1,2>: Cost 2 vext2 LHS, <1,2,3,0> 1548985304U, // <2,3,1,3>: Cost 2 vext2 LHS, <1,3,1,3> @@ -1741,7 +1741,7 @@ 2665858347U, // <2,3,1,7>: Cost 3 vext2 LHS, <1,7,3,0> 1548985709U, // <2,3,1,u>: Cost 2 vext2 LHS, <1,u,1,3> 2622727613U, // <2,3,2,0>: Cost 3 vext2 LHS, <2,0,1,2> - 2685700406U, // <2,3,2,1>: Cost 3 vext3 <0,2,0,2>, <3,2,1,0> + 2622727711U, // <2,3,2,1>: Cost 3 vext2 LHS, <2,1,3,1> 1544341096U, // <2,3,2,2>: Cost 2 vext2 LHS, <2,2,2,2> 1544341158U, // <2,3,2,3>: Cost 2 vext2 LHS, <2,3,0,1> 2622727958U, // <2,3,2,4>: Cost 3 vext2 LHS, <2,4,3,5> @@ -1750,14 +1750,14 @@ 2665859050U, // <2,3,2,7>: Cost 3 vext2 LHS, <2,7,0,1> 1548986427U, // <2,3,2,u>: Cost 2 vext2 LHS, <2,u,0,1> 1548986518U, // <2,3,3,0>: Cost 2 vext2 LHS, <3,0,1,2> - 2622728422U, // <2,3,3,1>: Cost 3 vext2 LHS, <3,1,1,1> - 1544341814U, // <2,3,3,2>: Cost 2 vext2 LHS, <3,2,1,0> + 2622728415U, // <2,3,3,1>: Cost 3 vext2 LHS, <3,1,0,3> + 1489913458U, // <2,3,3,2>: Cost 2 vext1 <2,2,3,3>, <2,2,3,3> 1544341916U, // <2,3,3,3>: Cost 2 vext2 LHS, <3,3,3,3> 1548986882U, // <2,3,3,4>: Cost 2 vext2 LHS, <3,4,5,6> 2665859632U, // <2,3,3,5>: Cost 3 vext2 LHS, <3,5,1,7> - 2665859704U, // <2,3,3,6>: Cost 3 vext2 LHS, <3,6,0,7> + 2234304870U, // <2,3,3,6>: Cost 3 vrev <3,2,6,3> 2958271632U, // <2,3,3,7>: Cost 3 vzipr LHS, <1,5,3,7> - 1548987164U, // <2,3,3,u>: Cost 2 vext2 LHS, <3,u,1,0> + 1548987166U, // <2,3,3,u>: Cost 2 vext2 LHS, <3,u,1,2> 1483948134U, // <2,3,4,0>: Cost 2 vext1 <1,2,3,4>, LHS 1483948954U, // <2,3,4,1>: Cost 2 vext1 <1,2,3,4>, <1,2,3,4> 2622729276U, // <2,3,4,2>: Cost 3 vext2 LHS, <4,2,6,0> @@ -1771,7 +1771,7 @@ 1592118992U, // <2,3,5,1>: Cost 2 vext2 LHS, <5,1,7,3> 2665860862U, // <2,3,5,2>: Cost 3 vext2 LHS, <5,2,3,4> 2551728642U, // <2,3,5,3>: Cost 3 vext1 <0,2,3,5>, <3,4,5,6> - 2551729462U, // <2,3,5,4>: Cost 3 vext1 <0,2,3,5>, RHS + 1592119238U, // <2,3,5,4>: Cost 2 vext2 LHS, <5,4,7,6> 1592119300U, // <2,3,5,5>: Cost 2 vext2 LHS, <5,5,5,5> 1592119394U, // <2,3,5,6>: Cost 2 vext2 LHS, <5,6,7,0> 1592119464U, // <2,3,5,7>: Cost 2 vext2 LHS, <5,7,5,7> @@ -1780,7 +1780,7 @@ 2557707164U, // <2,3,6,1>: Cost 3 vext1 <1,2,3,6>, <1,2,3,6> 1592119802U, // <2,3,6,2>: Cost 2 vext2 LHS, <6,2,7,3> 2665861682U, // <2,3,6,3>: Cost 3 vext2 LHS, <6,3,4,5> - 2622730860U, // <2,3,6,4>: Cost 3 vext2 LHS, <6,4,2,0> + 2622730893U, // <2,3,6,4>: Cost 3 vext2 LHS, <6,4,5,6> 2665861810U, // <2,3,6,5>: Cost 3 vext2 LHS, <6,5,0,7> 1592120120U, // <2,3,6,6>: Cost 2 vext2 LHS, <6,6,6,6> 1592120142U, // <2,3,6,7>: Cost 2 vext2 LHS, <6,7,0,1> @@ -1791,35 +1791,35 @@ 2665862371U, // <2,3,7,3>: Cost 3 vext2 LHS, <7,3,0,1> 1592120678U, // <2,3,7,4>: Cost 2 vext2 LHS, <7,4,5,6> 2665862534U, // <2,3,7,5>: Cost 3 vext2 LHS, <7,5,0,2> - 1592120838U, // <2,3,7,6>: Cost 2 vext2 LHS, <7,6,5,4> + 2665862614U, // <2,3,7,6>: Cost 3 vext2 LHS, <7,6,0,1> 1592120940U, // <2,3,7,7>: Cost 2 vext2 LHS, <7,7,7,7> 1592120962U, // <2,3,7,u>: Cost 2 vext2 LHS, <7,u,1,2> 1548990163U, // <2,3,u,0>: Cost 2 vext2 LHS, 470603566U, // <2,3,u,1>: Cost 1 vext2 LHS, LHS - 1548990323U, // <2,3,u,2>: Cost 2 vext2 LHS, + 1548990341U, // <2,3,u,2>: Cost 2 vext2 LHS, 1548990396U, // <2,3,u,3>: Cost 2 vext2 LHS, 1548990527U, // <2,3,u,4>: Cost 2 vext2 LHS, 470603930U, // <2,3,u,5>: Cost 1 vext2 LHS, RHS 1548990672U, // <2,3,u,6>: Cost 2 vext2 LHS, 1592121600U, // <2,3,u,7>: Cost 2 vext2 LHS, 470604133U, // <2,3,u,u>: Cost 1 vext2 LHS, LHS - 2587590758U, // <2,4,0,0>: Cost 3 vext1 <6,2,4,0>, LHS + 2617425942U, // <2,4,0,0>: Cost 3 vext2 <0,0,2,4>, <0,0,2,4> 2618753126U, // <2,4,0,1>: Cost 3 vext2 <0,2,2,4>, LHS 2618753208U, // <2,4,0,2>: Cost 3 vext2 <0,2,2,4>, <0,2,2,4> - 2232821937U, // <2,4,0,3>: Cost 3 vrev <3,0,4,2> - 2587594038U, // <2,4,0,4>: Cost 3 vext1 <6,2,4,0>, RHS + 2619416841U, // <2,4,0,3>: Cost 3 vext2 <0,3,2,4>, <0,3,2,4> + 2587593628U, // <2,4,0,4>: Cost 3 vext1 <6,2,4,0>, <4,0,6,2> 2712832914U, // <2,4,0,5>: Cost 3 vext3 <4,6,u,2>, <4,0,5,1> 1634962332U, // <2,4,0,6>: Cost 2 vext3 <4,0,6,2>, <4,0,6,2> - 2256712725U, // <2,4,0,7>: Cost 3 vrev <7,0,4,2> + 3799993252U, // <2,4,0,7>: Cost 4 vext3 <7,0,1,2>, <4,0,7,1> 1634962332U, // <2,4,0,u>: Cost 2 vext3 <4,0,6,2>, <4,0,6,2> - 3697140463U, // <2,4,1,0>: Cost 4 vext2 <1,0,2,4>, <1,0,2,4> + 2619417334U, // <2,4,1,0>: Cost 3 vext2 <0,3,2,4>, <1,0,3,2> 3692495668U, // <2,4,1,1>: Cost 4 vext2 <0,2,2,4>, <1,1,1,1> 2625389466U, // <2,4,1,2>: Cost 3 vext2 <1,3,2,4>, <1,2,3,4> 2826125414U, // <2,4,1,3>: Cost 3 vuzpr <1,2,3,4>, LHS 3699794995U, // <2,4,1,4>: Cost 4 vext2 <1,4,2,4>, <1,4,2,4> 3692496016U, // <2,4,1,5>: Cost 4 vext2 <0,2,2,4>, <1,5,3,7> 3763424238U, // <2,4,1,6>: Cost 4 vext3 <0,u,0,2>, <4,1,6,3> - 3331118182U, // <2,4,1,7>: Cost 4 vrev <7,1,4,2> + 3667317942U, // <2,4,1,7>: Cost 4 vext1 <7,2,4,1>, <7,2,4,1> 2826125419U, // <2,4,1,u>: Cost 3 vuzpr <1,2,3,4>, LHS 2629371336U, // <2,4,2,0>: Cost 3 vext2 <2,0,2,4>, <2,0,2,4> 3699131946U, // <2,4,2,1>: Cost 4 vext2 <1,3,2,4>, <2,1,4,3> @@ -1832,7 +1832,7 @@ 2899119657U, // <2,4,2,u>: Cost 3 vzipl <2,2,2,2>, RHS 2635344033U, // <2,4,3,0>: Cost 3 vext2 <3,0,2,4>, <3,0,2,4> 4032012325U, // <2,4,3,1>: Cost 4 vzipr LHS, <0,0,4,1> - 3692497206U, // <2,4,3,2>: Cost 4 vext2 <0,2,2,4>, <3,2,1,0> + 3692497228U, // <2,4,3,2>: Cost 4 vext2 <0,2,2,4>, <3,2,3,4> 3692497308U, // <2,4,3,3>: Cost 4 vext2 <0,2,2,4>, <3,3,3,3> 3001404624U, // <2,4,3,4>: Cost 3 vzipr LHS, <4,4,4,4> 2953627342U, // <2,4,3,5>: Cost 3 vzipr LHS, <2,3,4,5> @@ -1841,7 +1841,7 @@ 2953625806U, // <2,4,3,u>: Cost 3 vzipr LHS, <0,2,4,u> 2710916266U, // <2,4,4,0>: Cost 3 vext3 <4,4,0,2>, <4,4,0,2> 3899869648U, // <2,4,4,1>: Cost 4 vuzpr <1,2,3,4>, <3,4,0,1> - 3692497944U, // <2,4,4,2>: Cost 4 vext2 <0,2,2,4>, <4,2,2,0> + 3899869658U, // <2,4,4,2>: Cost 4 vuzpr <1,2,3,4>, <3,4,1,2> 3899868930U, // <2,4,4,3>: Cost 4 vuzpr <1,2,3,4>, <2,4,1,3> 2712833232U, // <2,4,4,4>: Cost 3 vext3 <4,6,u,2>, <4,4,4,4> 2618756406U, // <2,4,4,5>: Cost 3 vext2 <0,2,2,4>, RHS @@ -1849,21 +1849,21 @@ 4168304426U, // <2,4,4,7>: Cost 4 vtrnr <1,2,3,4>, <2,4,5,7> 2618756649U, // <2,4,4,u>: Cost 3 vext2 <0,2,2,4>, RHS 2551800011U, // <2,4,5,0>: Cost 3 vext1 <0,2,4,5>, <0,2,4,5> - 2557772708U, // <2,4,5,1>: Cost 3 vext1 <1,2,4,5>, <1,2,4,5> + 2569716470U, // <2,4,5,1>: Cost 3 vext1 <3,2,4,5>, <1,0,3,2> 2563745405U, // <2,4,5,2>: Cost 3 vext1 <2,2,4,5>, <2,2,4,5> - 2557773974U, // <2,4,5,3>: Cost 3 vext1 <1,2,4,5>, <3,0,1,2> + 2569718102U, // <2,4,5,3>: Cost 3 vext1 <3,2,4,5>, <3,2,4,5> 2551803190U, // <2,4,5,4>: Cost 3 vext1 <0,2,4,5>, RHS - 3625545619U, // <2,4,5,5>: Cost 4 vext1 <0,2,4,5>, <5,4,2,0> + 3625545732U, // <2,4,5,5>: Cost 4 vext1 <0,2,4,5>, <5,5,5,5> 1611959606U, // <2,4,5,6>: Cost 2 vext3 <0,2,0,2>, RHS 2826128694U, // <2,4,5,7>: Cost 3 vuzpr <1,2,3,4>, RHS 1611959624U, // <2,4,5,u>: Cost 2 vext3 <0,2,0,2>, RHS 1478066278U, // <2,4,6,0>: Cost 2 vext1 <0,2,4,6>, LHS - 2551808820U, // <2,4,6,1>: Cost 3 vext1 <0,2,4,6>, <1,1,1,1> - 2551809640U, // <2,4,6,2>: Cost 3 vext1 <0,2,4,6>, <2,2,2,2> + 2551808758U, // <2,4,6,1>: Cost 3 vext1 <0,2,4,6>, <1,0,3,2> + 2551809516U, // <2,4,6,2>: Cost 3 vext1 <0,2,4,6>, <2,0,6,4> 2551810198U, // <2,4,6,3>: Cost 3 vext1 <0,2,4,6>, <3,0,1,2> 1478069558U, // <2,4,6,4>: Cost 2 vext1 <0,2,4,6>, RHS 2901888310U, // <2,4,6,5>: Cost 3 vzipl <2,6,3,7>, RHS - 2551812716U, // <2,4,6,6>: Cost 3 vext1 <0,2,4,6>, <6,4,2,0> + 2551812920U, // <2,4,6,6>: Cost 3 vext1 <0,2,4,6>, <6,6,6,6> 2726251914U, // <2,4,6,7>: Cost 3 vext3 <7,0,1,2>, <4,6,7,1> 1478072110U, // <2,4,6,u>: Cost 2 vext1 <0,2,4,6>, LHS 2659234821U, // <2,4,7,0>: Cost 3 vext2 <7,0,2,4>, <7,0,2,4> @@ -1874,7 +1874,7 @@ 2726251976U, // <2,4,7,5>: Cost 3 vext3 <7,0,1,2>, <4,7,5,0> 2726251986U, // <2,4,7,6>: Cost 3 vext3 <7,0,1,2>, <4,7,6,1> 3727005292U, // <2,4,7,7>: Cost 4 vext2 <6,0,2,4>, <7,7,7,7> - 2726252003U, // <2,4,7,u>: Cost 3 vext3 <7,0,1,2>, <4,7,u,0> + 2659234821U, // <2,4,7,u>: Cost 3 vext2 <7,0,2,4>, <7,0,2,4> 1478082662U, // <2,4,u,0>: Cost 2 vext1 <0,2,4,u>, LHS 2618758958U, // <2,4,u,1>: Cost 3 vext2 <0,2,2,4>, LHS 2551826024U, // <2,4,u,2>: Cost 3 vext1 <0,2,4,u>, <2,2,2,2> @@ -1893,17 +1893,17 @@ 3693830655U, // <2,5,0,6>: Cost 4 vext2 <0,4,2,5>, <0,6,2,7> 3094531382U, // <2,5,0,7>: Cost 3 vtrnr <1,2,3,0>, RHS 2618098333U, // <2,5,0,u>: Cost 3 vext2 <0,1,2,5>, LHS - 3631554662U, // <2,5,1,0>: Cost 4 vext1 <1,2,5,1>, LHS + 3691840246U, // <2,5,1,0>: Cost 4 vext2 <0,1,2,5>, <1,0,3,2> 3691840308U, // <2,5,1,1>: Cost 4 vext2 <0,1,2,5>, <1,1,1,1> 2626061206U, // <2,5,1,2>: Cost 3 vext2 <1,4,2,5>, <1,2,3,0> 2618098688U, // <2,5,1,3>: Cost 3 vext2 <0,1,2,5>, <1,3,5,7> 2626061364U, // <2,5,1,4>: Cost 3 vext2 <1,4,2,5>, <1,4,2,5> 3691840656U, // <2,5,1,5>: Cost 4 vext2 <0,1,2,5>, <1,5,3,7> - 3711747270U, // <2,5,1,6>: Cost 4 vext2 <3,4,2,5>, <1,6,0,7> + 3789082310U, // <2,5,1,6>: Cost 4 vext3 <5,1,6,2>, <5,1,6,2> 2712833744U, // <2,5,1,7>: Cost 3 vext3 <4,6,u,2>, <5,1,7,3> 2628715896U, // <2,5,1,u>: Cost 3 vext2 <1,u,2,5>, <1,u,2,5> 3693831613U, // <2,5,2,0>: Cost 4 vext2 <0,4,2,5>, <2,0,1,2> - 3711747587U, // <2,5,2,1>: Cost 4 vext2 <3,4,2,5>, <2,1,0,0> + 4026698642U, // <2,5,2,1>: Cost 4 vzipr <0,0,2,2>, <4,0,5,1> 2632033896U, // <2,5,2,2>: Cost 3 vext2 <2,4,2,5>, <2,2,2,2> 3691841190U, // <2,5,2,3>: Cost 4 vext2 <0,1,2,5>, <2,3,0,1> 2632034061U, // <2,5,2,4>: Cost 3 vext2 <2,4,2,5>, <2,4,2,5> @@ -1913,26 +1913,26 @@ 3088354615U, // <2,5,2,u>: Cost 3 vtrnr <0,2,0,2>, RHS 2557829222U, // <2,5,3,0>: Cost 3 vext1 <1,2,5,3>, LHS 2557830059U, // <2,5,3,1>: Cost 3 vext1 <1,2,5,3>, <1,2,5,3> - 2638006582U, // <2,5,3,2>: Cost 3 vext2 <3,4,2,5>, <3,2,1,0> + 2575746766U, // <2,5,3,2>: Cost 3 vext1 <4,2,5,3>, <2,3,4,5> 3691841948U, // <2,5,3,3>: Cost 4 vext2 <0,1,2,5>, <3,3,3,3> 2619427330U, // <2,5,3,4>: Cost 3 vext2 <0,3,2,5>, <3,4,5,6> 2581720847U, // <2,5,3,5>: Cost 3 vext1 <5,2,5,3>, <5,2,5,3> 2953628162U, // <2,5,3,6>: Cost 3 vzipr LHS, <3,4,5,6> 2953626624U, // <2,5,3,7>: Cost 3 vzipr LHS, <1,3,5,7> 2953626625U, // <2,5,3,u>: Cost 3 vzipr LHS, <1,3,5,u> - 3631579238U, // <2,5,4,0>: Cost 4 vext1 <1,2,5,4>, LHS + 2569781350U, // <2,5,4,0>: Cost 3 vext1 <3,2,5,4>, LHS 3631580076U, // <2,5,4,1>: Cost 4 vext1 <1,2,5,4>, <1,2,5,4> - 3693833267U, // <2,5,4,2>: Cost 4 vext2 <0,4,2,5>, <4,2,5,0> - 2235550206U, // <2,5,4,3>: Cost 3 vrev <3,4,5,2> - 3631582518U, // <2,5,4,4>: Cost 4 vext1 <1,2,5,4>, RHS + 2569782990U, // <2,5,4,2>: Cost 3 vext1 <3,2,5,4>, <2,3,4,5> + 2569783646U, // <2,5,4,3>: Cost 3 vext1 <3,2,5,4>, <3,2,5,4> + 2569784630U, // <2,5,4,4>: Cost 3 vext1 <3,2,5,4>, RHS 2618101046U, // <2,5,4,5>: Cost 3 vext2 <0,1,2,5>, RHS 3893905922U, // <2,5,4,6>: Cost 4 vuzpr <0,2,3,5>, <3,4,5,6> 3094564150U, // <2,5,4,7>: Cost 3 vtrnr <1,2,3,4>, RHS 2618101289U, // <2,5,4,u>: Cost 3 vext2 <0,1,2,5>, RHS 2551873638U, // <2,5,5,0>: Cost 3 vext1 <0,2,5,5>, LHS 3637560320U, // <2,5,5,1>: Cost 4 vext1 <2,2,5,5>, <1,3,5,7> - 3691843304U, // <2,5,5,2>: Cost 4 vext2 <0,1,2,5>, <5,2,1,0> - 3309955663U, // <2,5,5,3>: Cost 4 vrev <3,5,5,2> + 3637560966U, // <2,5,5,2>: Cost 4 vext1 <2,2,5,5>, <2,2,5,5> + 3723030343U, // <2,5,5,3>: Cost 4 vext2 <5,3,2,5>, <5,3,2,5> 2551876918U, // <2,5,5,4>: Cost 3 vext1 <0,2,5,5>, RHS 2712834052U, // <2,5,5,5>: Cost 3 vext3 <4,6,u,2>, <5,5,5,5> 4028713474U, // <2,5,5,6>: Cost 4 vzipr <0,3,2,5>, <3,4,5,6> @@ -1948,18 +1948,18 @@ 3088682294U, // <2,5,6,7>: Cost 3 vtrnr <0,2,4,6>, RHS 3088682295U, // <2,5,6,u>: Cost 3 vtrnr <0,2,4,6>, RHS 2563833958U, // <2,5,7,0>: Cost 3 vext1 <2,2,5,7>, LHS - 3769766016U, // <2,5,7,1>: Cost 4 vext3 <1,u,5,2>, <5,7,1,3> + 2551890678U, // <2,5,7,1>: Cost 3 vext1 <0,2,5,7>, <1,0,3,2> 2563835528U, // <2,5,7,2>: Cost 3 vext1 <2,2,5,7>, <2,2,5,7> - 2551892118U, // <2,5,7,3>: Cost 3 vext1 <0,2,5,7>, <3,0,1,2> + 3637577878U, // <2,5,7,3>: Cost 4 vext1 <2,2,5,7>, <3,0,1,2> 2563837238U, // <2,5,7,4>: Cost 3 vext1 <2,2,5,7>, RHS 2712834216U, // <2,5,7,5>: Cost 3 vext3 <4,6,u,2>, <5,7,5,7> 2712834220U, // <2,5,7,6>: Cost 3 vext3 <4,6,u,2>, <5,7,6,2> - 3637581208U, // <2,5,7,7>: Cost 4 vext1 <2,2,5,7>, <7,5,2,2> + 4174449974U, // <2,5,7,7>: Cost 4 vtrnr <2,2,5,7>, RHS 2563839790U, // <2,5,7,u>: Cost 3 vext1 <2,2,5,7>, LHS 2563842150U, // <2,5,u,0>: Cost 3 vext1 <2,2,5,u>, LHS 2618103598U, // <2,5,u,1>: Cost 3 vext2 <0,1,2,5>, LHS 2563843721U, // <2,5,u,2>: Cost 3 vext1 <2,2,5,u>, <2,2,5,u> - 2238204738U, // <2,5,u,3>: Cost 3 vrev <3,u,5,2> + 2569816418U, // <2,5,u,3>: Cost 3 vext1 <3,2,5,u>, <3,2,5,u> 2622748735U, // <2,5,u,4>: Cost 3 vext2 <0,u,2,5>, 2618103962U, // <2,5,u,5>: Cost 3 vext2 <0,1,2,5>, RHS 2953669122U, // <2,5,u,6>: Cost 3 vzipr LHS, <3,4,5,6> @@ -1974,7 +1974,7 @@ 2551911246U, // <2,6,0,6>: Cost 3 vext1 <0,2,6,0>, <6,7,0,1> 2720723287U, // <2,6,0,7>: Cost 3 vext3 <6,0,7,2>, <6,0,7,2> 1546355357U, // <2,6,0,u>: Cost 2 vext2 <0,4,2,6>, LHS - 3693839092U, // <2,6,1,0>: Cost 4 vext2 <0,4,2,6>, <1,0,3,0> + 2620097270U, // <2,6,1,0>: Cost 3 vext2 <0,4,2,6>, <1,0,3,2> 2620097332U, // <2,6,1,1>: Cost 3 vext2 <0,4,2,6>, <1,1,1,1> 2620097430U, // <2,6,1,2>: Cost 3 vext2 <0,4,2,6>, <1,2,3,0> 2820243558U, // <2,6,1,3>: Cost 3 vuzpr <0,2,4,6>, LHS @@ -1994,14 +1994,14 @@ 2620098619U, // <2,6,2,u>: Cost 3 vext2 <0,4,2,6>, <2,u,0,1> 2620098710U, // <2,6,3,0>: Cost 3 vext2 <0,4,2,6>, <3,0,1,2> 3893986982U, // <2,6,3,1>: Cost 4 vuzpr <0,2,4,6>, <2,3,0,1> - 2620098870U, // <2,6,3,2>: Cost 3 vext2 <0,4,2,6>, <3,2,1,0> + 2569848762U, // <2,6,3,2>: Cost 3 vext1 <3,2,6,3>, <2,6,3,7> 2620098972U, // <2,6,3,3>: Cost 3 vext2 <0,4,2,6>, <3,3,3,3> 2620099074U, // <2,6,3,4>: Cost 3 vext2 <0,4,2,6>, <3,4,5,6> 3893987022U, // <2,6,3,5>: Cost 4 vuzpr <0,2,4,6>, <2,3,4,5> 3001404644U, // <2,6,3,6>: Cost 3 vzipr LHS, <4,4,6,6> 1879887158U, // <2,6,3,7>: Cost 2 vzipr LHS, RHS 1879887159U, // <2,6,3,u>: Cost 2 vzipr LHS, RHS - 2575827046U, // <2,6,4,0>: Cost 3 vext1 <4,2,6,4>, LHS + 2620099484U, // <2,6,4,0>: Cost 3 vext2 <0,4,2,6>, <4,0,6,2> 2620099566U, // <2,6,4,1>: Cost 3 vext2 <0,4,2,6>, <4,1,6,3> 2620099644U, // <2,6,4,2>: Cost 3 vext2 <0,4,2,6>, <4,2,6,0> 3643599207U, // <2,6,4,3>: Cost 4 vext1 <3,2,6,4>, <3,2,6,4> @@ -2014,14 +2014,14 @@ 2667876048U, // <2,6,5,1>: Cost 3 vext2 , <5,1,7,3> 2712834756U, // <2,6,5,2>: Cost 3 vext3 <4,6,u,2>, <6,5,2,7> 3643607400U, // <2,6,5,3>: Cost 4 vext1 <3,2,6,5>, <3,2,6,5> - 3693842356U, // <2,6,5,4>: Cost 4 vext2 <0,4,2,6>, <5,4,5,6> + 2252091873U, // <2,6,5,4>: Cost 3 vrev <6,2,4,5> 2667876356U, // <2,6,5,5>: Cost 3 vext2 , <5,5,5,5> 2667876450U, // <2,6,5,6>: Cost 3 vext2 , <5,6,7,0> 2820246838U, // <2,6,5,7>: Cost 3 vuzpr <0,2,4,6>, RHS 2820246839U, // <2,6,5,u>: Cost 3 vuzpr <0,2,4,6>, RHS 2563899494U, // <2,6,6,0>: Cost 3 vext1 <2,2,6,6>, LHS 3893988683U, // <2,6,6,1>: Cost 4 vuzpr <0,2,4,6>, <4,6,0,1> - 2620101084U, // <2,6,6,2>: Cost 3 vext2 <0,4,2,6>, <6,2,4,0> + 2563901072U, // <2,6,6,2>: Cost 3 vext1 <2,2,6,6>, <2,2,6,6> 3893987236U, // <2,6,6,3>: Cost 4 vuzpr <0,2,4,6>, <2,6,1,3> 2563902774U, // <2,6,6,4>: Cost 3 vext1 <2,2,6,6>, RHS 3893988723U, // <2,6,6,5>: Cost 4 vuzpr <0,2,4,6>, <4,6,4,5> @@ -2031,15 +2031,15 @@ 2712834894U, // <2,6,7,0>: Cost 3 vext3 <4,6,u,2>, <6,7,0,1> 2724926296U, // <2,6,7,1>: Cost 3 vext3 <6,7,1,2>, <6,7,1,2> 2725000033U, // <2,6,7,2>: Cost 3 vext3 <6,7,2,2>, <6,7,2,2> - 2725073770U, // <2,6,7,3>: Cost 3 vext3 <6,7,3,2>, <6,7,3,2> + 2702365544U, // <2,6,7,3>: Cost 3 vext3 <3,0,1,2>, <6,7,3,0> 2712834934U, // <2,6,7,4>: Cost 3 vext3 <4,6,u,2>, <6,7,4,5> 3776107393U, // <2,6,7,5>: Cost 4 vext3 <3,0,1,2>, <6,7,5,7> - 2255532933U, // <2,6,7,6>: Cost 3 vrev <6,7,6,2> + 2725294981U, // <2,6,7,6>: Cost 3 vext3 <6,7,6,2>, <6,7,6,2> 2726253452U, // <2,6,7,7>: Cost 3 vext3 <7,0,1,2>, <6,7,7,0> 2712834966U, // <2,6,7,u>: Cost 3 vext3 <4,6,u,2>, <6,7,u,1> 2620102355U, // <2,6,u,0>: Cost 3 vext2 <0,4,2,6>, 1546360622U, // <2,6,u,1>: Cost 2 vext2 <0,4,2,6>, LHS - 2620102515U, // <2,6,u,2>: Cost 3 vext2 <0,4,2,6>, + 2620102536U, // <2,6,u,2>: Cost 3 vext2 <0,4,2,6>, 2820244125U, // <2,6,u,3>: Cost 3 vuzpr <0,2,4,6>, LHS 1594136612U, // <2,6,u,4>: Cost 2 vext2 , 1546360986U, // <2,6,u,5>: Cost 2 vext2 <0,4,2,6>, RHS @@ -2049,24 +2049,24 @@ 2726179825U, // <2,7,0,0>: Cost 3 vext3 <7,0,0,2>, <7,0,0,2> 1652511738U, // <2,7,0,1>: Cost 2 vext3 <7,0,1,2>, <7,0,1,2> 2621431972U, // <2,7,0,2>: Cost 3 vext2 <0,6,2,7>, <0,2,0,2> - 3693183244U, // <2,7,0,3>: Cost 4 vext2 <0,3,2,7>, <0,3,2,7> + 2257949868U, // <2,7,0,3>: Cost 3 vrev <7,2,3,0> 2726474773U, // <2,7,0,4>: Cost 3 vext3 <7,0,4,2>, <7,0,4,2> 2620768686U, // <2,7,0,5>: Cost 3 vext2 <0,5,2,7>, <0,5,2,7> 2621432319U, // <2,7,0,6>: Cost 3 vext2 <0,6,2,7>, <0,6,2,7> 2599760953U, // <2,7,0,7>: Cost 3 vext1 , <7,0,u,2> 1653027897U, // <2,7,0,u>: Cost 2 vext3 <7,0,u,2>, <7,0,u,2> - 2726843458U, // <2,7,1,0>: Cost 3 vext3 <7,1,0,2>, <7,1,0,2> + 2639348470U, // <2,7,1,0>: Cost 3 vext2 <3,6,2,7>, <1,0,3,2> 3695174452U, // <2,7,1,1>: Cost 4 vext2 <0,6,2,7>, <1,1,1,1> 3695174550U, // <2,7,1,2>: Cost 4 vext2 <0,6,2,7>, <1,2,3,0> 3694511104U, // <2,7,1,3>: Cost 4 vext2 <0,5,2,7>, <1,3,5,7> - 2599767350U, // <2,7,1,4>: Cost 3 vext1 , RHS + 3713090594U, // <2,7,1,4>: Cost 4 vext2 <3,6,2,7>, <1,4,0,5> 3693184144U, // <2,7,1,5>: Cost 4 vext2 <0,3,2,7>, <1,5,3,7> 2627405016U, // <2,7,1,6>: Cost 3 vext2 <1,6,2,7>, <1,6,2,7> - 2599769082U, // <2,7,1,7>: Cost 3 vext1 , <7,0,1,2> - 2599769902U, // <2,7,1,u>: Cost 3 vext1 , LHS + 3799995519U, // <2,7,1,7>: Cost 4 vext3 <7,0,1,2>, <7,1,7,0> + 2639348470U, // <2,7,1,u>: Cost 3 vext2 <3,6,2,7>, <1,0,3,2> 3695175101U, // <2,7,2,0>: Cost 4 vext2 <0,6,2,7>, <2,0,1,2> 3643655168U, // <2,7,2,1>: Cost 4 vext1 <3,2,7,2>, <1,3,5,7> - 2727654565U, // <2,7,2,2>: Cost 3 vext3 <7,2,2,2>, <7,2,2,2> + 2257892517U, // <2,7,2,2>: Cost 3 vrev <7,2,2,2> 3695175334U, // <2,7,2,3>: Cost 4 vext2 <0,6,2,7>, <2,3,0,1> 3695175465U, // <2,7,2,4>: Cost 4 vext2 <0,6,2,7>, <2,4,5,6> 2632714080U, // <2,7,2,5>: Cost 3 vext2 <2,5,2,7>, <2,5,2,7> @@ -2085,7 +2085,7 @@ 2708706617U, // <2,7,4,0>: Cost 3 vext3 <4,0,6,2>, <7,4,0,6> 3649643418U, // <2,7,4,1>: Cost 4 vext1 <4,2,7,4>, <1,2,3,4> 3649644330U, // <2,7,4,2>: Cost 4 vext1 <4,2,7,4>, <2,4,5,7> - 3802797392U, // <2,7,4,3>: Cost 4 vext3 <7,4,3,2>, <7,4,3,2> + 2257982640U, // <2,7,4,3>: Cost 3 vrev <7,2,3,4> 3649645641U, // <2,7,4,4>: Cost 4 vext1 <4,2,7,4>, <4,2,7,4> 2621435190U, // <2,7,4,5>: Cost 3 vext2 <0,6,2,7>, RHS 2712835441U, // <2,7,4,6>: Cost 3 vext3 <4,6,u,2>, <7,4,6,u> @@ -2093,8 +2093,8 @@ 2621435433U, // <2,7,4,u>: Cost 3 vext2 <0,6,2,7>, RHS 2729497990U, // <2,7,5,0>: Cost 3 vext3 <7,5,0,2>, <7,5,0,2> 3643679744U, // <2,7,5,1>: Cost 4 vext1 <3,2,7,5>, <1,3,5,7> - 3706457886U, // <2,7,5,2>: Cost 4 vext2 <2,5,2,7>, <5,2,7,0> - 3769767328U, // <2,7,5,3>: Cost 4 vext3 <1,u,5,2>, <7,5,3,1> + 3637708424U, // <2,7,5,2>: Cost 4 vext1 <2,2,7,5>, <2,2,5,7> + 3643681137U, // <2,7,5,3>: Cost 4 vext1 <3,2,7,5>, <3,2,7,5> 2599800118U, // <2,7,5,4>: Cost 3 vext1 , RHS 3786577334U, // <2,7,5,5>: Cost 4 vext3 <4,6,u,2>, <7,5,5,5> 3786577345U, // <2,7,5,6>: Cost 4 vext3 <4,6,u,2>, <7,5,6,7> @@ -2103,18 +2103,18 @@ 2581889126U, // <2,7,6,0>: Cost 3 vext1 <5,2,7,6>, LHS 3643687936U, // <2,7,6,1>: Cost 4 vext1 <3,2,7,6>, <1,3,5,7> 2663240186U, // <2,7,6,2>: Cost 3 vext2 <7,6,2,7>, <6,2,7,3> - 3975632154U, // <2,7,6,3>: Cost 4 vzipl <2,6,3,7>, <7,3,6,2> + 3643689330U, // <2,7,6,3>: Cost 4 vext1 <3,2,7,6>, <3,2,7,6> 2581892406U, // <2,7,6,4>: Cost 3 vext1 <5,2,7,6>, RHS - 2712835590U, // <2,7,6,5>: Cost 3 vext3 <4,6,u,2>, <7,6,5,4> + 2581892900U, // <2,7,6,5>: Cost 3 vext1 <5,2,7,6>, <5,2,7,6> 2587865597U, // <2,7,6,6>: Cost 3 vext1 <6,2,7,6>, <6,2,7,6> 3786577428U, // <2,7,6,7>: Cost 4 vext3 <4,6,u,2>, <7,6,7,0> 2581894958U, // <2,7,6,u>: Cost 3 vext1 <5,2,7,6>, LHS 2726254119U, // <2,7,7,0>: Cost 3 vext3 <7,0,1,2>, <7,7,0,1> 3804640817U, // <2,7,7,1>: Cost 4 vext3 <7,7,1,2>, <7,7,1,2> - 3695178951U, // <2,7,7,2>: Cost 4 vext2 <0,6,2,7>, <7,2,6,0> + 3637724826U, // <2,7,7,2>: Cost 4 vext1 <2,2,7,7>, <2,2,7,7> 3734992123U, // <2,7,7,3>: Cost 4 vext2 <7,3,2,7>, <7,3,2,7> 2552040758U, // <2,7,7,4>: Cost 3 vext1 <0,2,7,7>, RHS - 3323375797U, // <2,7,7,5>: Cost 4 vrev <5,7,7,2> + 3799995992U, // <2,7,7,5>: Cost 4 vext3 <7,0,1,2>, <7,7,5,5> 2663241198U, // <2,7,7,6>: Cost 3 vext2 <7,6,2,7>, <7,6,2,7> 2712835692U, // <2,7,7,7>: Cost 3 vext3 <4,6,u,2>, <7,7,7,7> 2731562607U, // <2,7,7,u>: Cost 3 vext3 <7,u,1,2>, <7,7,u,1> @@ -2130,13 +2130,13 @@ 1544380416U, // <2,u,0,0>: Cost 2 vext2 LHS, <0,0,0,0> 470638699U, // <2,u,0,1>: Cost 1 vext2 LHS, LHS 1544380580U, // <2,u,0,2>: Cost 2 vext2 LHS, <0,2,0,2> - 1159375061U, // <2,u,0,3>: Cost 2 vrev <3,0,u,2> + 1658631909U, // <2,u,0,3>: Cost 2 vext3 , 1544380754U, // <2,u,0,4>: Cost 2 vext2 LHS, <0,4,1,5> - 2245062279U, // <2,u,0,5>: Cost 3 vrev <5,0,u,2> + 2665898414U, // <2,u,0,5>: Cost 3 vext2 LHS, <0,5,2,7> 1658853120U, // <2,u,0,6>: Cost 2 vext3 , - 1183265849U, // <2,u,0,7>: Cost 2 vrev <7,0,u,2> + 3094531625U, // <2,u,0,7>: Cost 3 vtrnr <1,2,3,0>, RHS 470639261U, // <2,u,0,u>: Cost 1 vext2 LHS, LHS - 2618122996U, // <2,u,1,0>: Cost 3 vext2 LHS, <1,0,3,0> + 1544381174U, // <2,u,1,0>: Cost 2 vext2 LHS, <1,0,3,2> 1544381236U, // <2,u,1,1>: Cost 2 vext2 LHS, <1,1,1,1> 1544381334U, // <2,u,1,2>: Cost 2 vext2 LHS, <1,2,3,0> 1544381400U, // <2,u,1,3>: Cost 2 vext2 LHS, <1,3,1,3> @@ -2146,7 +2146,7 @@ 2726254427U, // <2,u,1,7>: Cost 3 vext3 <7,0,1,2>, 1544381823U, // <2,u,1,u>: Cost 2 vext2 LHS, <1,u,3,3> 1478328422U, // <2,u,2,0>: Cost 2 vext1 <0,2,u,2>, LHS - 2618123806U, // <2,u,2,1>: Cost 3 vext2 LHS, <2,1,3,0> + 2618123807U, // <2,u,2,1>: Cost 3 vext2 LHS, <2,1,3,1> 269271142U, // <2,u,2,2>: Cost 1 vdup2 LHS 1544382118U, // <2,u,2,3>: Cost 2 vext2 LHS, <2,3,0,1> 1478331702U, // <2,u,2,4>: Cost 2 vext1 <0,2,u,2>, RHS @@ -2156,7 +2156,7 @@ 269271142U, // <2,u,2,u>: Cost 1 vdup2 LHS 1544382614U, // <2,u,3,0>: Cost 2 vext2 LHS, <3,0,1,2> 2953627374U, // <2,u,3,1>: Cost 3 vzipr LHS, <2,3,u,1> - 1544382774U, // <2,u,3,2>: Cost 2 vext2 LHS, <3,2,1,0> + 1490282143U, // <2,u,3,2>: Cost 2 vext1 <2,2,u,3>, <2,2,u,3> 1879883932U, // <2,u,3,3>: Cost 2 vzipr LHS, LHS 1544382978U, // <2,u,3,4>: Cost 2 vext2 LHS, <3,4,5,6> 2953627378U, // <2,u,3,5>: Cost 3 vzipr LHS, <2,3,u,5> @@ -2166,7 +2166,7 @@ 1484316774U, // <2,u,4,0>: Cost 2 vext1 <1,2,u,4>, LHS 1484317639U, // <2,u,4,1>: Cost 2 vext1 <1,2,u,4>, <1,2,u,4> 2552088270U, // <2,u,4,2>: Cost 3 vext1 <0,2,u,4>, <2,3,4,5> - 3094561437U, // <2,u,4,3>: Cost 3 vtrnr <1,2,3,4>, LHS + 1190213513U, // <2,u,4,3>: Cost 2 vrev 1484320054U, // <2,u,4,4>: Cost 2 vext1 <1,2,u,4>, RHS 470641974U, // <2,u,4,5>: Cost 1 vext2 LHS, RHS 1592159604U, // <2,u,4,6>: Cost 2 vext2 LHS, <4,6,4,6> @@ -2176,13 +2176,13 @@ 1592159952U, // <2,u,5,1>: Cost 2 vext2 LHS, <5,1,7,3> 2564040353U, // <2,u,5,2>: Cost 3 vext1 <2,2,u,5>, <2,2,u,5> 2690275455U, // <2,u,5,3>: Cost 3 vext3 <0,u,u,2>, - 2552098102U, // <2,u,5,4>: Cost 3 vext1 <0,2,u,5>, RHS + 1592160198U, // <2,u,5,4>: Cost 2 vext2 LHS, <5,4,7,6> 1592160260U, // <2,u,5,5>: Cost 2 vext2 LHS, <5,5,5,5> 1611962522U, // <2,u,5,6>: Cost 2 vext3 <0,2,0,2>, RHS 1592160424U, // <2,u,5,7>: Cost 2 vext2 LHS, <5,7,5,7> 1611962540U, // <2,u,5,u>: Cost 2 vext3 <0,2,0,2>, RHS 1478361190U, // <2,u,6,0>: Cost 2 vext1 <0,2,u,6>, LHS - 2552103732U, // <2,u,6,1>: Cost 3 vext1 <0,2,u,6>, <1,1,1,1> + 2552103670U, // <2,u,6,1>: Cost 3 vext1 <0,2,u,6>, <1,0,3,2> 1592160762U, // <2,u,6,2>: Cost 2 vext2 LHS, <6,2,7,3> 2685704400U, // <2,u,6,3>: Cost 3 vext3 <0,2,0,2>, 1478364470U, // <2,u,6,4>: Cost 2 vext1 <0,2,u,6>, RHS @@ -2193,10 +2193,10 @@ 1592161274U, // <2,u,7,0>: Cost 2 vext2 LHS, <7,0,1,2> 2659931226U, // <2,u,7,1>: Cost 3 vext2 <7,1,2,u>, <7,1,2,u> 2564056739U, // <2,u,7,2>: Cost 3 vext1 <2,2,u,7>, <2,2,u,7> - 2661258492U, // <2,u,7,3>: Cost 3 vext2 <7,3,2,u>, <7,3,2,u> + 2665903331U, // <2,u,7,3>: Cost 3 vext2 LHS, <7,3,0,1> 1592161638U, // <2,u,7,4>: Cost 2 vext2 LHS, <7,4,5,6> 2665903494U, // <2,u,7,5>: Cost 3 vext2 LHS, <7,5,0,2> - 1592161798U, // <2,u,7,6>: Cost 2 vext2 LHS, <7,6,5,4> + 2587947527U, // <2,u,7,6>: Cost 3 vext1 <6,2,u,7>, <6,2,u,7> 1592161900U, // <2,u,7,7>: Cost 2 vext2 LHS, <7,7,7,7> 1592161922U, // <2,u,7,u>: Cost 2 vext2 LHS, <7,u,1,2> 1478377574U, // <2,u,u,0>: Cost 2 vext1 <0,2,u,u>, LHS @@ -2211,14 +2211,14 @@ 1611448320U, // <3,0,0,0>: Cost 2 vext3 LHS, <0,0,0,0> 1611890698U, // <3,0,0,1>: Cost 2 vext3 LHS, <0,0,1,1> 1611890708U, // <3,0,0,2>: Cost 2 vext3 LHS, <0,0,2,2> - 2624766214U, // <3,0,0,3>: Cost 3 vext2 <1,2,3,0>, <0,3,2,1> + 3763576860U, // <3,0,0,3>: Cost 4 vext3 LHS, <0,0,3,1> 2689835045U, // <3,0,0,4>: Cost 3 vext3 LHS, <0,0,4,1> - 3731685806U, // <3,0,0,5>: Cost 4 vext2 <6,7,3,0>, <0,5,2,7> + 3698508206U, // <3,0,0,5>: Cost 4 vext2 <1,2,3,0>, <0,5,2,7> 3763576887U, // <3,0,0,6>: Cost 4 vext3 LHS, <0,0,6,1> 3667678434U, // <3,0,0,7>: Cost 4 vext1 <7,3,0,0>, <7,3,0,0> 1616093258U, // <3,0,0,u>: Cost 2 vext3 LHS, <0,0,u,2> 1490337894U, // <3,0,1,0>: Cost 2 vext1 <2,3,0,1>, LHS - 2685632603U, // <3,0,1,1>: Cost 3 vext3 LHS, <0,1,1,1> + 2685632602U, // <3,0,1,1>: Cost 3 vext3 LHS, <0,1,1,0> 537706598U, // <3,0,1,2>: Cost 1 vext3 LHS, LHS 2624766936U, // <3,0,1,3>: Cost 3 vext2 <1,2,3,0>, <1,3,1,3> 1490341174U, // <3,0,1,4>: Cost 2 vext1 <2,3,0,1>, RHS @@ -2240,7 +2240,7 @@ 2685632774U, // <3,0,3,2>: Cost 3 vext3 LHS, <0,3,2,1> 2624768412U, // <3,0,3,3>: Cost 3 vext2 <1,2,3,0>, <3,3,3,3> 2624768514U, // <3,0,3,4>: Cost 3 vext2 <1,2,3,0>, <3,4,5,6> - 3698510384U, // <3,0,3,5>: Cost 4 vext2 <1,2,3,0>, <3,5,1,7> + 3702491714U, // <3,0,3,5>: Cost 4 vext2 <1,u,3,0>, <3,5,3,7> 2624768632U, // <3,0,3,6>: Cost 3 vext2 <1,2,3,0>, <3,6,0,7> 3702491843U, // <3,0,3,7>: Cost 4 vext2 <1,u,3,0>, <3,7,0,1> 2686959934U, // <3,0,3,u>: Cost 3 vext3 <0,3,u,3>, <0,3,u,3> @@ -2257,7 +2257,7 @@ 2666573520U, // <3,0,5,1>: Cost 3 vext2 , <5,1,7,3> 3040886886U, // <3,0,5,2>: Cost 3 vtrnl <3,4,5,6>, LHS 3625912834U, // <3,0,5,3>: Cost 4 vext1 <0,3,0,5>, <3,4,5,6> - 3625913654U, // <3,0,5,4>: Cost 4 vext1 <0,3,0,5>, RHS + 2666573766U, // <3,0,5,4>: Cost 3 vext2 , <5,4,7,6> 2666573828U, // <3,0,5,5>: Cost 3 vext2 , <5,5,5,5> 2732966354U, // <3,0,5,6>: Cost 3 vext3 LHS, <0,5,6,7> 2666573992U, // <3,0,5,7>: Cost 3 vext2 , <5,7,5,7> @@ -2267,17 +2267,17 @@ 2689835519U, // <3,0,6,2>: Cost 3 vext3 LHS, <0,6,2,7> 3667724438U, // <3,0,6,3>: Cost 4 vext1 <7,3,0,6>, <3,0,1,2> 3763577355U, // <3,0,6,4>: Cost 4 vext3 LHS, <0,6,4,1> - 3322204198U, // <3,0,6,5>: Cost 4 vrev <5,6,0,3> + 3806708243U, // <3,0,6,5>: Cost 4 vext3 LHS, <0,6,5,0> 2666574648U, // <3,0,6,6>: Cost 3 vext2 , <6,6,6,6> 2657948520U, // <3,0,6,7>: Cost 3 vext2 <6,7,3,0>, <6,7,3,0> 2689835573U, // <3,0,6,u>: Cost 3 vext3 LHS, <0,6,u,7> 2666574842U, // <3,0,7,0>: Cost 3 vext2 , <7,0,1,2> - 2685633088U, // <3,0,7,1>: Cost 3 vext3 LHS, <0,7,1,0> + 2685633095U, // <3,0,7,1>: Cost 3 vext3 LHS, <0,7,1,7> 2660603052U, // <3,0,7,2>: Cost 3 vext2 <7,2,3,0>, <7,2,3,0> - 3702494480U, // <3,0,7,3>: Cost 4 vext2 <1,u,3,0>, <7,3,5,1> + 3643844997U, // <3,0,7,3>: Cost 4 vext1 <3,3,0,7>, <3,3,0,7> 2666575206U, // <3,0,7,4>: Cost 3 vext2 , <7,4,5,6> - 3702494624U, // <3,0,7,5>: Cost 4 vext2 <1,u,3,0>, <7,5,3,1> - 2732966514U, // <3,0,7,6>: Cost 3 vext3 LHS, <0,7,6,5> + 3655790391U, // <3,0,7,5>: Cost 4 vext1 <5,3,0,7>, <5,3,0,7> + 3731690968U, // <3,0,7,6>: Cost 4 vext2 <6,7,3,0>, <7,6,0,3> 2666575468U, // <3,0,7,7>: Cost 3 vext2 , <7,7,7,7> 2664584850U, // <3,0,7,u>: Cost 3 vext2 <7,u,3,0>, <7,u,3,0> 1616093834U, // <3,0,u,0>: Cost 2 vext3 LHS, <0,u,0,2> @@ -2292,12 +2292,12 @@ 2552201318U, // <3,1,0,0>: Cost 3 vext1 <0,3,1,0>, LHS 2618802278U, // <3,1,0,1>: Cost 3 vext2 <0,2,3,1>, LHS 2618802366U, // <3,1,0,2>: Cost 3 vext2 <0,2,3,1>, <0,2,3,1> - 2685633268U, // <3,1,0,3>: Cost 3 vext3 LHS, <1,0,3,0> + 1611449078U, // <3,1,0,3>: Cost 2 vext3 LHS, <1,0,3,2> 2552204598U, // <3,1,0,4>: Cost 3 vext1 <0,3,1,0>, RHS - 2732966664U, // <3,1,0,5>: Cost 3 vext3 LHS, <1,0,5,2> + 2732966663U, // <3,1,0,5>: Cost 3 vext3 LHS, <1,0,5,1> 3906258396U, // <3,1,0,6>: Cost 4 vuzpr <2,3,0,1>, <2,0,4,6> - 2732966686U, // <3,1,0,7>: Cost 3 vext3 LHS, <1,0,7,6> - 2685633313U, // <3,1,0,u>: Cost 3 vext3 LHS, <1,0,u,0> + 3667752171U, // <3,1,0,7>: Cost 4 vext1 <7,3,1,0>, <7,3,1,0> + 1611891491U, // <3,1,0,u>: Cost 2 vext3 LHS, <1,0,u,2> 2689835819U, // <3,1,1,0>: Cost 3 vext3 LHS, <1,1,0,1> 1611449140U, // <3,1,1,1>: Cost 2 vext3 LHS, <1,1,1,1> 2624775063U, // <3,1,1,2>: Cost 3 vext2 <1,2,3,1>, <1,2,3,1> @@ -2305,13 +2305,13 @@ 2689835859U, // <3,1,1,4>: Cost 3 vext3 LHS, <1,1,4,5> 2689835868U, // <3,1,1,5>: Cost 3 vext3 LHS, <1,1,5,5> 3763577701U, // <3,1,1,6>: Cost 4 vext3 LHS, <1,1,6,5> - 2257163340U, // <3,1,1,7>: Cost 3 vrev <7,1,1,3> + 3765273452U, // <3,1,1,7>: Cost 4 vext3 <1,1,7,3>, <1,1,7,3> 1611891573U, // <3,1,1,u>: Cost 2 vext3 LHS, <1,1,u,3> - 2552217702U, // <3,1,2,0>: Cost 3 vext1 <0,3,1,2>, LHS + 2629420494U, // <3,1,2,0>: Cost 3 vext2 <2,0,3,1>, <2,0,3,1> 2689835911U, // <3,1,2,1>: Cost 3 vext3 LHS, <1,2,1,3> 2564163248U, // <3,1,2,2>: Cost 3 vext1 <2,3,1,2>, <2,3,1,2> 1611449238U, // <3,1,2,3>: Cost 2 vext3 LHS, <1,2,3,0> - 2552220982U, // <3,1,2,4>: Cost 3 vext1 <0,3,1,2>, RHS + 2564164918U, // <3,1,2,4>: Cost 3 vext1 <2,3,1,2>, RHS 2689835947U, // <3,1,2,5>: Cost 3 vext3 LHS, <1,2,5,3> 3692545978U, // <3,1,2,6>: Cost 4 vext2 <0,2,3,1>, <2,6,3,7> 2732966842U, // <3,1,2,7>: Cost 3 vext3 LHS, <1,2,7,0> @@ -2340,10 +2340,10 @@ 1611891856U, // <3,1,5,3>: Cost 2 vext3 LHS, <1,5,3,7> 2689836183U, // <3,1,5,4>: Cost 3 vext3 LHS, <1,5,4,5> 3759375522U, // <3,1,5,5>: Cost 4 vext3 LHS, <1,5,5,7> - 3733688418U, // <3,1,5,6>: Cost 4 vext2 <7,1,3,1>, <5,6,7,0> + 3720417378U, // <3,1,5,6>: Cost 4 vext2 <4,u,3,1>, <5,6,7,0> 2832518454U, // <3,1,5,7>: Cost 3 vuzpr <2,3,0,1>, RHS 1611891901U, // <3,1,5,u>: Cost 2 vext3 LHS, <1,5,u,7> - 2732967110U, // <3,1,6,0>: Cost 3 vext3 LHS, <1,6,0,7> + 3763578048U, // <3,1,6,0>: Cost 4 vext3 LHS, <1,6,0,1> 2689836239U, // <3,1,6,1>: Cost 3 vext3 LHS, <1,6,1,7> 2732967128U, // <3,1,6,2>: Cost 3 vext3 LHS, <1,6,2,7> 2685633761U, // <3,1,6,3>: Cost 3 vext3 LHS, <1,6,3,7> @@ -2357,9 +2357,9 @@ 4036102294U, // <3,1,7,2>: Cost 4 vzipr <1,5,3,7>, <3,0,1,2> 3095396454U, // <3,1,7,3>: Cost 3 vtrnr <1,3,5,7>, LHS 3631975734U, // <3,1,7,4>: Cost 4 vext1 <1,3,1,7>, RHS - 2249199744U, // <3,1,7,5>: Cost 3 vrev <5,7,1,3> - 2255172441U, // <3,1,7,6>: Cost 3 vrev <6,7,1,3> - 3733689964U, // <3,1,7,7>: Cost 4 vext2 <7,1,3,1>, <7,7,7,7> + 2222982144U, // <3,1,7,5>: Cost 3 vrev <1,3,5,7> + 3296797705U, // <3,1,7,6>: Cost 4 vrev <1,3,6,7> + 3720418924U, // <3,1,7,7>: Cost 4 vext2 <4,u,3,1>, <7,7,7,7> 3095396459U, // <3,1,7,u>: Cost 3 vtrnr <1,3,5,7>, LHS 1484496998U, // <3,1,u,0>: Cost 2 vext1 <1,3,1,u>, LHS 1611892077U, // <3,1,u,1>: Cost 2 vext3 LHS, <1,u,1,3> @@ -2370,24 +2370,24 @@ 2685633950U, // <3,1,u,6>: Cost 3 vext3 LHS, <1,u,6,7> 2832518697U, // <3,1,u,7>: Cost 3 vuzpr <2,3,0,1>, RHS 1611892140U, // <3,1,u,u>: Cost 2 vext3 LHS, <1,u,u,3> - 2623455252U, // <3,2,0,0>: Cost 3 vext2 <1,0,3,2>, <0,0,2,2> - 2689836477U, // <3,2,0,1>: Cost 3 vext3 LHS, <2,0,1,2> + 2623455232U, // <3,2,0,0>: Cost 3 vext2 <1,0,3,2>, <0,0,0,0> + 1549713510U, // <3,2,0,1>: Cost 2 vext2 <1,0,3,2>, LHS 2689836484U, // <3,2,0,2>: Cost 3 vext3 LHS, <2,0,2,0> 2685633997U, // <3,2,0,3>: Cost 3 vext3 LHS, <2,0,3,0> - 2558250294U, // <3,2,0,4>: Cost 3 vext1 <1,3,2,0>, RHS + 2623455570U, // <3,2,0,4>: Cost 3 vext2 <1,0,3,2>, <0,4,1,5> 2732967398U, // <3,2,0,5>: Cost 3 vext3 LHS, <2,0,5,7> - 2732967401U, // <3,2,0,6>: Cost 3 vext3 LHS, <2,0,6,1> - 3763578355U, // <3,2,0,7>: Cost 4 vext3 LHS, <2,0,7,2> - 2685634042U, // <3,2,0,u>: Cost 3 vext3 LHS, <2,0,u,0> - 67944550U, // <3,2,1,0>: Cost 1 vrev LHS - 2576171930U, // <3,2,1,1>: Cost 3 vext1 <4,3,2,1>, <1,2,3,4> - 2624783256U, // <3,2,1,2>: Cost 3 vext2 <1,2,3,2>, <1,2,3,2> - 2685634078U, // <3,2,1,3>: Cost 3 vext3 LHS, <2,1,3,0> + 2689836524U, // <3,2,0,6>: Cost 3 vext3 LHS, <2,0,6,4> + 2229044964U, // <3,2,0,7>: Cost 3 vrev <2,3,7,0> + 1549714077U, // <3,2,0,u>: Cost 2 vext2 <1,0,3,2>, LHS + 1549714166U, // <3,2,1,0>: Cost 2 vext2 <1,0,3,2>, <1,0,3,2> + 2623456052U, // <3,2,1,1>: Cost 3 vext2 <1,0,3,2>, <1,1,1,1> + 2623456150U, // <3,2,1,2>: Cost 3 vext2 <1,0,3,2>, <1,2,3,0> + 2685634079U, // <3,2,1,3>: Cost 3 vext3 LHS, <2,1,3,1> 2552286518U, // <3,2,1,4>: Cost 3 vext1 <0,3,2,1>, RHS - 3763578416U, // <3,2,1,5>: Cost 4 vext3 LHS, <2,1,5,0> + 2623456400U, // <3,2,1,5>: Cost 3 vext2 <1,0,3,2>, <1,5,3,7> 2689836604U, // <3,2,1,6>: Cost 3 vext3 LHS, <2,1,6,3> - 2257237077U, // <3,2,1,7>: Cost 3 vrev <7,1,2,3> - 115726126U, // <3,2,1,u>: Cost 1 vrev LHS + 3667834101U, // <3,2,1,7>: Cost 4 vext1 <7,3,2,1>, <7,3,2,1> + 1155385070U, // <3,2,1,u>: Cost 2 vrev <2,3,u,1> 2689836629U, // <3,2,2,0>: Cost 3 vext3 LHS, <2,2,0,1> 2689836640U, // <3,2,2,1>: Cost 3 vext3 LHS, <2,2,1,3> 1611449960U, // <3,2,2,2>: Cost 2 vext3 LHS, <2,2,2,2> @@ -2395,12 +2395,12 @@ 2689836669U, // <3,2,2,4>: Cost 3 vext3 LHS, <2,2,4,5> 2689836680U, // <3,2,2,5>: Cost 3 vext3 LHS, <2,2,5,7> 2689836688U, // <3,2,2,6>: Cost 3 vext3 LHS, <2,2,6,6> - 2257900710U, // <3,2,2,7>: Cost 3 vrev <7,2,2,3> + 3763578518U, // <3,2,2,7>: Cost 4 vext3 LHS, <2,2,7,3> 1611892383U, // <3,2,2,u>: Cost 2 vext3 LHS, <2,2,u,3> 1611450022U, // <3,2,3,0>: Cost 2 vext3 LHS, <2,3,0,1> - 2685191855U, // <3,2,3,1>: Cost 3 vext3 LHS, <2,3,1,1> + 2685191854U, // <3,2,3,1>: Cost 3 vext3 LHS, <2,3,1,0> 2685191865U, // <3,2,3,2>: Cost 3 vext3 LHS, <2,3,2,2> - 2685191874U, // <3,2,3,3>: Cost 3 vext3 LHS, <2,3,3,2> + 2685191875U, // <3,2,3,3>: Cost 3 vext3 LHS, <2,3,3,3> 1611450062U, // <3,2,3,4>: Cost 2 vext3 LHS, <2,3,4,5> 2732967635U, // <3,2,3,5>: Cost 3 vext3 LHS, <2,3,5,1> 2732967645U, // <3,2,3,6>: Cost 3 vext3 LHS, <2,3,6,2> @@ -2411,19 +2411,19 @@ 2732967692U, // <3,2,4,2>: Cost 3 vext3 LHS, <2,4,2,4> 2685634326U, // <3,2,4,3>: Cost 3 vext3 LHS, <2,4,3,5> 2558283062U, // <3,2,4,4>: Cost 3 vext1 <1,3,2,4>, RHS - 2689836841U, // <3,2,4,5>: Cost 3 vext3 LHS, <2,4,5,6> + 1549716790U, // <3,2,4,5>: Cost 2 vext2 <1,0,3,2>, RHS 2689836844U, // <3,2,4,6>: Cost 3 vext3 LHS, <2,4,6,0> - 3667858680U, // <3,2,4,7>: Cost 4 vext1 <7,3,2,4>, <7,3,2,4> - 2685634371U, // <3,2,4,u>: Cost 3 vext3 LHS, <2,4,u,5> + 2229077736U, // <3,2,4,7>: Cost 3 vrev <2,3,7,4> + 1549717033U, // <3,2,4,u>: Cost 2 vext2 <1,0,3,2>, RHS 2552316006U, // <3,2,5,0>: Cost 3 vext1 <0,3,2,5>, LHS - 3759376211U, // <3,2,5,1>: Cost 4 vext3 LHS, <2,5,1,3> + 2228643507U, // <3,2,5,1>: Cost 3 vrev <2,3,1,5> 2689836896U, // <3,2,5,2>: Cost 3 vext3 LHS, <2,5,2,7> 2685634408U, // <3,2,5,3>: Cost 3 vext3 LHS, <2,5,3,6> - 2552319286U, // <3,2,5,4>: Cost 3 vext1 <0,3,2,5>, RHS - 3759376251U, // <3,2,5,5>: Cost 4 vext3 LHS, <2,5,5,7> + 1155122894U, // <3,2,5,4>: Cost 2 vrev <2,3,4,5> + 2665263108U, // <3,2,5,5>: Cost 3 vext2 , <5,5,5,5> 2689836932U, // <3,2,5,6>: Cost 3 vext3 LHS, <2,5,6,7> - 3894398262U, // <3,2,5,7>: Cost 4 vuzpr <0,3,1,2>, RHS - 2685634453U, // <3,2,5,u>: Cost 3 vext3 LHS, <2,5,u,6> + 2665263272U, // <3,2,5,7>: Cost 3 vext2 , <5,7,5,7> + 1155417842U, // <3,2,5,u>: Cost 2 vrev <2,3,u,5> 2689836953U, // <3,2,6,0>: Cost 3 vext3 LHS, <2,6,0,1> 2689836964U, // <3,2,6,1>: Cost 3 vext3 LHS, <2,6,1,3> 2689836976U, // <3,2,6,2>: Cost 3 vext3 LHS, <2,6,2,6> @@ -2431,26 +2431,26 @@ 2689836993U, // <3,2,6,4>: Cost 3 vext3 LHS, <2,6,4,5> 2689837004U, // <3,2,6,5>: Cost 3 vext3 LHS, <2,6,5,7> 2689837013U, // <3,2,6,6>: Cost 3 vext3 LHS, <2,6,6,7> - 2657964906U, // <3,2,6,7>: Cost 3 vext2 <6,7,3,2>, <6,7,3,2> + 2665263950U, // <3,2,6,7>: Cost 3 vext2 , <6,7,0,1> 1611892711U, // <3,2,6,u>: Cost 2 vext3 LHS, <2,6,u,7> - 2732967914U, // <3,2,7,0>: Cost 3 vext3 LHS, <2,7,0,1> - 3626075280U, // <3,2,7,1>: Cost 4 vext1 <0,3,2,7>, <1,5,3,7> + 2665264122U, // <3,2,7,0>: Cost 3 vext2 , <7,0,1,2> + 2623460419U, // <3,2,7,1>: Cost 3 vext2 <1,0,3,2>, <7,1,0,3> 4169138340U, // <3,2,7,2>: Cost 4 vtrnr <1,3,5,7>, <0,2,0,2> 2962358374U, // <3,2,7,3>: Cost 3 vzipr <1,5,3,7>, LHS - 3626077494U, // <3,2,7,4>: Cost 4 vext1 <0,3,2,7>, RHS - 4169138352U, // <3,2,7,5>: Cost 4 vtrnr <1,3,5,7>, <0,2,1,5> - 2255246178U, // <3,2,7,6>: Cost 3 vrev <6,7,2,3> - 3723744876U, // <3,2,7,7>: Cost 4 vext2 <5,4,3,2>, <7,7,7,7> + 2665264486U, // <3,2,7,4>: Cost 3 vext2 , <7,4,5,6> + 2228954841U, // <3,2,7,5>: Cost 3 vrev <2,3,5,7> + 2229028578U, // <3,2,7,6>: Cost 3 vrev <2,3,6,7> + 2665264748U, // <3,2,7,7>: Cost 3 vext2 , <7,7,7,7> 2962358379U, // <3,2,7,u>: Cost 3 vzipr <1,5,3,7>, LHS - 72589981U, // <3,2,u,0>: Cost 1 vrev LHS - 2685634628U, // <3,2,u,1>: Cost 3 vext3 LHS, <2,u,1,1> + 1611892795U, // <3,2,u,0>: Cost 2 vext3 LHS, <2,u,0,1> + 1549719342U, // <3,2,u,1>: Cost 2 vext2 <1,0,3,2>, LHS 1611449960U, // <3,2,u,2>: Cost 2 vext3 LHS, <2,2,2,2> 1611892824U, // <3,2,u,3>: Cost 2 vext3 LHS, <2,u,3,3> 1611892835U, // <3,2,u,4>: Cost 2 vext3 LHS, <2,u,4,5> - 2689837165U, // <3,2,u,5>: Cost 3 vext3 LHS, <2,u,5,6> + 1549719706U, // <3,2,u,5>: Cost 2 vext2 <1,0,3,2>, RHS 2689837168U, // <3,2,u,6>: Cost 3 vext3 LHS, <2,u,6,0> - 2594149628U, // <3,2,u,7>: Cost 3 vext1 <7,3,2,u>, <7,3,2,u> - 120371557U, // <3,2,u,u>: Cost 1 vrev LHS + 2665265408U, // <3,2,u,7>: Cost 3 vext2 , + 1611892867U, // <3,2,u,u>: Cost 2 vext3 LHS, <2,u,u,1> 2685192331U, // <3,3,0,0>: Cost 3 vext3 LHS, <3,0,0,0> 1611450518U, // <3,3,0,1>: Cost 2 vext3 LHS, <3,0,1,2> 2685634717U, // <3,3,0,2>: Cost 3 vext3 LHS, <3,0,2,0> @@ -2460,7 +2460,7 @@ 3763579075U, // <3,3,0,6>: Cost 4 vext3 LHS, <3,0,6,2> 4034053264U, // <3,3,0,7>: Cost 4 vzipr <1,2,3,0>, <1,5,3,7> 1611450581U, // <3,3,0,u>: Cost 2 vext3 LHS, <3,0,u,2> - 2558328934U, // <3,3,1,0>: Cost 3 vext1 <1,3,3,1>, LHS + 2685192415U, // <3,3,1,0>: Cost 3 vext3 LHS, <3,1,0,3> 1550385992U, // <3,3,1,1>: Cost 2 vext2 <1,1,3,3>, <1,1,3,3> 2685192433U, // <3,3,1,2>: Cost 3 vext3 LHS, <3,1,2,3> 2685634808U, // <3,3,1,3>: Cost 3 vext3 LHS, <3,1,3,1> @@ -2470,22 +2470,22 @@ 2703477022U, // <3,3,1,7>: Cost 3 vext3 <3,1,7,3>, <3,1,7,3> 1555031423U, // <3,3,1,u>: Cost 2 vext2 <1,u,3,3>, <1,u,3,3> 2564309094U, // <3,3,2,0>: Cost 3 vext1 <2,3,3,2>, LHS - 1611450678U, // <3,3,2,1>: Cost 2 vext3 LHS, <3,2,1,0> + 2630100513U, // <3,3,2,1>: Cost 3 vext2 <2,1,3,3>, <2,1,3,3> 1557022322U, // <3,3,2,2>: Cost 2 vext2 <2,2,3,3>, <2,2,3,3> 2685192520U, // <3,3,2,3>: Cost 3 vext3 LHS, <3,2,3,0> 2564312374U, // <3,3,2,4>: Cost 3 vext1 <2,3,3,2>, RHS - 3759376733U, // <3,3,2,5>: Cost 4 vext3 LHS, <3,2,5,3> + 2732968286U, // <3,3,2,5>: Cost 3 vext3 LHS, <3,2,5,4> 2685634918U, // <3,3,2,6>: Cost 3 vext3 LHS, <3,2,6,3> 2704140655U, // <3,3,2,7>: Cost 3 vext3 <3,2,7,3>, <3,2,7,3> - 1616095605U, // <3,3,2,u>: Cost 2 vext3 LHS, <3,2,u,0> + 1561004120U, // <3,3,2,u>: Cost 2 vext2 <2,u,3,3>, <2,u,3,3> 1496547430U, // <3,3,3,0>: Cost 2 vext1 <3,3,3,3>, LHS 2624129256U, // <3,3,3,1>: Cost 3 vext2 <1,1,3,3>, <3,1,1,3> - 2685192593U, // <3,3,3,2>: Cost 3 vext3 LHS, <3,3,2,1> + 2630764866U, // <3,3,3,2>: Cost 3 vext2 <2,2,3,3>, <3,2,2,3> 336380006U, // <3,3,3,3>: Cost 1 vdup3 LHS 1496550710U, // <3,3,3,4>: Cost 2 vext1 <3,3,3,3>, RHS 2732968368U, // <3,3,3,5>: Cost 3 vext3 LHS, <3,3,5,5> 2624129683U, // <3,3,3,6>: Cost 3 vext2 <1,1,3,3>, <3,6,3,7> - 2258638080U, // <3,3,3,7>: Cost 3 vrev <7,3,3,3> + 2594182400U, // <3,3,3,7>: Cost 3 vext1 <7,3,3,3>, <7,3,3,3> 336380006U, // <3,3,3,u>: Cost 1 vdup3 LHS 2558353510U, // <3,3,4,0>: Cost 3 vext1 <1,3,3,4>, LHS 2558354411U, // <3,3,4,1>: Cost 3 vext1 <1,3,3,4>, <1,3,3,4> @@ -2520,11 +2520,11 @@ 2661291264U, // <3,3,7,3>: Cost 3 vext2 <7,3,3,3>, <7,3,3,3> 2558381366U, // <3,3,7,4>: Cost 3 vext1 <1,3,3,7>, RHS 2732968694U, // <3,3,7,5>: Cost 3 vext3 LHS, <3,7,5,7> - 2255319915U, // <3,3,7,6>: Cost 3 vrev <6,7,3,3> + 3781126907U, // <3,3,7,6>: Cost 4 vext3 <3,7,6,3>, <3,7,6,3> 3095397376U, // <3,3,7,7>: Cost 3 vtrnr <1,3,5,7>, <1,3,5,7> 2558383918U, // <3,3,7,u>: Cost 3 vext1 <1,3,3,7>, LHS 1496547430U, // <3,3,u,0>: Cost 2 vext1 <3,3,3,3>, LHS - 1611893532U, // <3,3,u,1>: Cost 2 vext3 LHS, <3,u,1,0> + 1611893534U, // <3,3,u,1>: Cost 2 vext3 LHS, <3,u,1,2> 1592858504U, // <3,3,u,2>: Cost 2 vext2 , 336380006U, // <3,3,u,3>: Cost 1 vdup3 LHS 1496550710U, // <3,3,u,4>: Cost 2 vext1 <3,3,3,3>, RHS @@ -2541,7 +2541,7 @@ 1659227036U, // <3,4,0,6>: Cost 2 vext3 LHS, <4,0,6,2> 3667973382U, // <3,4,0,7>: Cost 4 vext1 <7,3,4,0>, <7,3,4,0> 1551057565U, // <3,4,0,u>: Cost 2 vext2 <1,2,3,4>, LHS - 2564374630U, // <3,4,1,0>: Cost 3 vext1 <2,3,4,1>, LHS + 2624799478U, // <3,4,1,0>: Cost 3 vext2 <1,2,3,4>, <1,0,3,2> 2624799540U, // <3,4,1,1>: Cost 3 vext2 <1,2,3,4>, <1,1,1,1> 1551057818U, // <3,4,1,2>: Cost 2 vext2 <1,2,3,4>, <1,2,3,4> 2624799704U, // <3,4,1,3>: Cost 3 vext2 <1,2,3,4>, <1,3,1,3> @@ -2555,23 +2555,23 @@ 2624800360U, // <3,4,2,2>: Cost 3 vext2 <1,2,3,4>, <2,2,2,2> 2624800422U, // <3,4,2,3>: Cost 3 vext2 <1,2,3,4>, <2,3,0,1> 2624800514U, // <3,4,2,4>: Cost 3 vext2 <1,2,3,4>, <2,4,1,3> - 2905001270U, // <3,4,2,5>: Cost 3 vzipl <3,2,1,0>, RHS + 2709965878U, // <3,4,2,5>: Cost 3 vext3 <4,2,5,3>, <4,2,5,3> 2689838140U, // <3,4,2,6>: Cost 3 vext3 LHS, <4,2,6,0> 2634090504U, // <3,4,2,7>: Cost 3 vext2 <2,7,3,4>, <2,7,3,4> 2689838158U, // <3,4,2,u>: Cost 3 vext3 LHS, <4,2,u,0> 2624800918U, // <3,4,3,0>: Cost 3 vext2 <1,2,3,4>, <3,0,1,2> 2636081403U, // <3,4,3,1>: Cost 3 vext2 <3,1,3,4>, <3,1,3,4> - 2624801078U, // <3,4,3,2>: Cost 3 vext2 <1,2,3,4>, <3,2,1,0> + 2636745036U, // <3,4,3,2>: Cost 3 vext2 <3,2,3,4>, <3,2,3,4> 2624801180U, // <3,4,3,3>: Cost 3 vext2 <1,2,3,4>, <3,3,3,3> 2624801232U, // <3,4,3,4>: Cost 3 vext2 <1,2,3,4>, <3,4,0,1> 2905836854U, // <3,4,3,5>: Cost 3 vzipl <3,3,3,3>, RHS 3040054582U, // <3,4,3,6>: Cost 3 vtrnl <3,3,3,3>, RHS 3702524611U, // <3,4,3,7>: Cost 4 vext2 <1,u,3,4>, <3,7,0,1> - 2624801564U, // <3,4,3,u>: Cost 3 vext2 <1,2,3,4>, <3,u,1,0> + 2624801566U, // <3,4,3,u>: Cost 3 vext2 <1,2,3,4>, <3,u,1,2> 2564399206U, // <3,4,4,0>: Cost 3 vext1 <2,3,4,4>, LHS 2564400026U, // <3,4,4,1>: Cost 3 vext1 <2,3,4,4>, <1,2,3,4> 2564400845U, // <3,4,4,2>: Cost 3 vext1 <2,3,4,4>, <2,3,4,4> - 2624801898U, // <3,4,4,3>: Cost 3 vext2 <1,2,3,4>, <4,3,2,1> + 2570373542U, // <3,4,4,3>: Cost 3 vext1 <3,3,4,4>, <3,3,4,4> 1659227344U, // <3,4,4,4>: Cost 2 vext3 LHS, <4,4,4,4> 1551060278U, // <3,4,4,5>: Cost 2 vext2 <1,2,3,4>, RHS 1659227364U, // <3,4,4,6>: Cost 2 vext3 LHS, <4,4,6,6> @@ -2588,7 +2588,7 @@ 537709896U, // <3,4,5,u>: Cost 1 vext3 LHS, RHS 2689838411U, // <3,4,6,0>: Cost 3 vext3 LHS, <4,6,0,1> 2558444534U, // <3,4,6,1>: Cost 3 vext1 <1,3,4,6>, <1,3,4,6> - 2732969308U, // <3,4,6,2>: Cost 3 vext3 LHS, <4,6,2,0> + 2666607098U, // <3,4,6,2>: Cost 3 vext2 , <6,2,7,3> 2558446082U, // <3,4,6,3>: Cost 3 vext1 <1,3,4,6>, <3,4,5,6> 1659227508U, // <3,4,6,4>: Cost 2 vext3 LHS, <4,6,4,6> 2689838462U, // <3,4,6,5>: Cost 3 vext3 LHS, <4,6,5,7> @@ -2598,10 +2598,10 @@ 2666607610U, // <3,4,7,0>: Cost 3 vext2 , <7,0,1,2> 3702527072U, // <3,4,7,1>: Cost 4 vext2 <1,u,3,4>, <7,1,3,5> 2660635824U, // <3,4,7,2>: Cost 3 vext2 <7,2,3,4>, <7,2,3,4> - 3702527248U, // <3,4,7,3>: Cost 4 vext2 <1,u,3,4>, <7,3,5,1> + 3644139945U, // <3,4,7,3>: Cost 4 vext1 <3,3,4,7>, <3,3,4,7> 2666607974U, // <3,4,7,4>: Cost 3 vext2 , <7,4,5,6> 2732969416U, // <3,4,7,5>: Cost 3 vext3 LHS, <4,7,5,0> - 2732969426U, // <3,4,7,6>: Cost 3 vext3 LHS, <4,7,6,1> + 2732969425U, // <3,4,7,6>: Cost 3 vext3 LHS, <4,7,6,0> 2666608236U, // <3,4,7,7>: Cost 3 vext2 , <7,7,7,7> 2664617622U, // <3,4,7,u>: Cost 3 vext2 <7,u,3,4>, <7,u,3,4> 1490690150U, // <3,4,u,0>: Cost 2 vext1 <2,3,4,u>, LHS @@ -2620,18 +2620,18 @@ 2689838690U, // <3,5,0,4>: Cost 3 vext3 LHS, <5,0,4,1> 2732969579U, // <3,5,0,5>: Cost 3 vext3 LHS, <5,0,5,1> 2732969588U, // <3,5,0,6>: Cost 3 vext3 LHS, <5,0,6,1> - 4162817334U, // <3,5,0,7>: Cost 4 vtrnr <0,3,1,0>, RHS + 2246963055U, // <3,5,0,7>: Cost 3 vrev <5,3,7,0> 2618835613U, // <3,5,0,u>: Cost 3 vext2 <0,2,3,5>, LHS 2594308198U, // <3,5,1,0>: Cost 3 vext1 <7,3,5,1>, LHS 3692577588U, // <3,5,1,1>: Cost 4 vext2 <0,2,3,5>, <1,1,1,1> 2624807835U, // <3,5,1,2>: Cost 3 vext2 <1,2,3,5>, <1,2,3,5> 2625471468U, // <3,5,1,3>: Cost 3 vext2 <1,3,3,5>, <1,3,3,5> - 2689838770U, // <3,5,1,4>: Cost 3 vext3 LHS, <5,1,4,0> + 2626135101U, // <3,5,1,4>: Cost 3 vext2 <1,4,3,5>, <1,4,3,5> 2594311888U, // <3,5,1,5>: Cost 3 vext1 <7,3,5,1>, <5,1,7,3> 3699877107U, // <3,5,1,6>: Cost 4 vext2 <1,4,3,5>, <1,6,5,7> 1641680592U, // <3,5,1,7>: Cost 2 vext3 <5,1,7,3>, <5,1,7,3> 1641754329U, // <3,5,1,u>: Cost 2 vext3 <5,1,u,3>, <5,1,u,3> - 3703195090U, // <3,5,2,0>: Cost 4 vext2 <2,0,3,5>, <2,0,3,5> + 3692578274U, // <3,5,2,0>: Cost 4 vext2 <0,2,3,5>, <2,0,5,3> 2630116899U, // <3,5,2,1>: Cost 3 vext2 <2,1,3,5>, <2,1,3,5> 3692578408U, // <3,5,2,2>: Cost 4 vext2 <0,2,3,5>, <2,2,2,2> 2625472206U, // <3,5,2,3>: Cost 3 vext2 <1,3,3,5>, <2,3,4,5> @@ -2642,22 +2642,22 @@ 2634762330U, // <3,5,2,u>: Cost 3 vext2 <2,u,3,5>, <2,u,3,5> 3692578966U, // <3,5,3,0>: Cost 4 vext2 <0,2,3,5>, <3,0,1,2> 2636089596U, // <3,5,3,1>: Cost 3 vext2 <3,1,3,5>, <3,1,3,5> - 3692579126U, // <3,5,3,2>: Cost 4 vext2 <0,2,3,5>, <3,2,1,0> + 3699214668U, // <3,5,3,2>: Cost 4 vext2 <1,3,3,5>, <3,2,3,4> 2638080412U, // <3,5,3,3>: Cost 3 vext2 <3,4,3,5>, <3,3,3,3> 2618837506U, // <3,5,3,4>: Cost 3 vext2 <0,2,3,5>, <3,4,5,6> 2832844494U, // <3,5,3,5>: Cost 3 vuzpr <2,3,4,5>, <2,3,4,5> 4033415682U, // <3,5,3,6>: Cost 4 vzipr <1,1,3,3>, <3,4,5,6> 3095072054U, // <3,5,3,7>: Cost 3 vtrnr <1,3,1,3>, RHS 3095072055U, // <3,5,3,u>: Cost 3 vtrnr <1,3,1,3>, RHS - 2732969858U, // <3,5,4,0>: Cost 3 vext3 LHS, <5,4,0,1> - 2732969874U, // <3,5,4,1>: Cost 3 vext3 LHS, <5,4,1,u> - 3763580819U, // <3,5,4,2>: Cost 4 vext3 LHS, <5,4,2,0> - 2732969886U, // <3,5,4,3>: Cost 3 vext3 LHS, <5,4,3,2> - 2732969898U, // <3,5,4,4>: Cost 3 vext3 LHS, <5,4,4,5> + 2600304742U, // <3,5,4,0>: Cost 3 vext1 , LHS + 3763580815U, // <3,5,4,1>: Cost 4 vext3 LHS, <5,4,1,5> + 2564474582U, // <3,5,4,2>: Cost 3 vext1 <2,3,5,4>, <2,3,5,4> + 3699879044U, // <3,5,4,3>: Cost 4 vext2 <1,4,3,5>, <4,3,5,0> + 2600308022U, // <3,5,4,4>: Cost 3 vext1 , RHS 2618838326U, // <3,5,4,5>: Cost 3 vext2 <0,2,3,5>, RHS 2772454710U, // <3,5,4,6>: Cost 3 vuzpl <3,4,5,6>, RHS - 2732969925U, // <3,5,4,7>: Cost 3 vext3 LHS, <5,4,7,5> - 2618838569U, // <3,5,4,u>: Cost 3 vext2 <0,2,3,5>, RHS + 1659228102U, // <3,5,4,7>: Cost 2 vext3 LHS, <5,4,7,6> + 1659228111U, // <3,5,4,u>: Cost 2 vext3 LHS, <5,4,u,6> 2570453094U, // <3,5,5,0>: Cost 3 vext1 <3,3,5,5>, LHS 2624810704U, // <3,5,5,1>: Cost 3 vext2 <1,2,3,5>, <5,1,7,3> 2570454734U, // <3,5,5,2>: Cost 3 vext1 <3,3,5,5>, <2,3,4,5> @@ -2683,7 +2683,7 @@ 1484786998U, // <3,5,7,4>: Cost 2 vext1 <1,3,5,7>, RHS 1659228328U, // <3,5,7,5>: Cost 2 vext3 LHS, <5,7,5,7> 2732970154U, // <3,5,7,6>: Cost 3 vext3 LHS, <5,7,6,0> - 2558530976U, // <3,5,7,7>: Cost 3 vext1 <1,3,5,7>, <7,5,3,1> + 2558531180U, // <3,5,7,7>: Cost 3 vext1 <1,3,5,7>, <7,7,7,7> 1484789550U, // <3,5,7,u>: Cost 2 vext1 <1,3,5,7>, LHS 1484791910U, // <3,5,u,0>: Cost 2 vext1 <1,3,5,u>, LHS 1484792833U, // <3,5,u,1>: Cost 2 vext1 <1,3,5,u>, <1,3,5,u> @@ -2703,7 +2703,7 @@ 2732970316U, // <3,6,0,6>: Cost 3 vext3 LHS, <6,0,6,0> 2960313654U, // <3,6,0,7>: Cost 3 vzipr <1,2,3,0>, RHS 2689839456U, // <3,6,0,u>: Cost 3 vext3 LHS, <6,0,u,2> - 2720878954U, // <3,6,1,0>: Cost 3 vext3 <6,1,0,3>, <6,1,0,3> + 3763581290U, // <3,6,1,0>: Cost 4 vext3 LHS, <6,1,0,3> 3763581297U, // <3,6,1,1>: Cost 4 vext3 LHS, <6,1,1,1> 2624816028U, // <3,6,1,2>: Cost 3 vext2 <1,2,3,6>, <1,2,3,6> 3763581315U, // <3,6,1,3>: Cost 4 vext3 LHS, <6,1,3,1> @@ -2715,43 +2715,43 @@ 2594390118U, // <3,6,2,0>: Cost 3 vext1 <7,3,6,2>, LHS 2721616324U, // <3,6,2,1>: Cost 3 vext3 <6,2,1,3>, <6,2,1,3> 2630788725U, // <3,6,2,2>: Cost 3 vext2 <2,2,3,6>, <2,2,3,6> - 2234304870U, // <3,6,2,3>: Cost 3 vrev <3,2,6,3> - 2689839580U, // <3,6,2,4>: Cost 3 vext3 LHS, <6,2,4,0> + 3763581395U, // <3,6,2,3>: Cost 4 vext3 LHS, <6,2,3,0> + 2632115991U, // <3,6,2,4>: Cost 3 vext2 <2,4,3,6>, <2,4,3,6> 2632779624U, // <3,6,2,5>: Cost 3 vext2 <2,5,3,6>, <2,5,3,6> 2594394618U, // <3,6,2,6>: Cost 3 vext1 <7,3,6,2>, <6,2,7,3> 1648316922U, // <3,6,2,7>: Cost 2 vext3 <6,2,7,3>, <6,2,7,3> 1648390659U, // <3,6,2,u>: Cost 2 vext3 <6,2,u,3>, <6,2,u,3> 3693914262U, // <3,6,3,0>: Cost 4 vext2 <0,4,3,6>, <3,0,1,2> 3638281176U, // <3,6,3,1>: Cost 4 vext1 <2,3,6,3>, <1,3,1,3> - 3763581468U, // <3,6,3,2>: Cost 4 vext3 LHS, <6,3,2,1> + 3696568678U, // <3,6,3,2>: Cost 4 vext2 <0,u,3,6>, <3,2,6,3> 2638088604U, // <3,6,3,3>: Cost 3 vext2 <3,4,3,6>, <3,3,3,3> 2632780290U, // <3,6,3,4>: Cost 3 vext2 <2,5,3,6>, <3,4,5,6> 3712494145U, // <3,6,3,5>: Cost 4 vext2 <3,5,3,6>, <3,5,3,6> 3698559612U, // <3,6,3,6>: Cost 4 vext2 <1,2,3,6>, <3,6,1,2> 2959674678U, // <3,6,3,7>: Cost 3 vzipr <1,1,3,3>, RHS 2959674679U, // <3,6,3,u>: Cost 3 vzipr <1,1,3,3>, RHS - 3638288486U, // <3,6,4,0>: Cost 4 vext1 <2,3,6,4>, LHS + 3763581536U, // <3,6,4,0>: Cost 4 vext3 LHS, <6,4,0,6> 2722943590U, // <3,6,4,1>: Cost 3 vext3 <6,4,1,3>, <6,4,1,3> - 2689839724U, // <3,6,4,2>: Cost 3 vext3 LHS, <6,4,2,0> + 2732970609U, // <3,6,4,2>: Cost 3 vext3 LHS, <6,4,2,5> 3698560147U, // <3,6,4,3>: Cost 4 vext2 <1,2,3,6>, <4,3,6,6> 2732970628U, // <3,6,4,4>: Cost 3 vext3 LHS, <6,4,4,6> 2689839757U, // <3,6,4,5>: Cost 3 vext3 LHS, <6,4,5,6> 2732970640U, // <3,6,4,6>: Cost 3 vext3 LHS, <6,4,6,0> 2960346422U, // <3,6,4,7>: Cost 3 vzipr <1,2,3,4>, RHS 2689839784U, // <3,6,4,u>: Cost 3 vext3 LHS, <6,4,u,6> - 2732970674U, // <3,6,5,0>: Cost 3 vext3 LHS, <6,5,0,7> - 3789165243U, // <3,6,5,1>: Cost 4 vext3 <5,1,7,3>, <6,5,1,7> + 2576498790U, // <3,6,5,0>: Cost 3 vext1 <4,3,6,5>, LHS + 3650241270U, // <3,6,5,1>: Cost 4 vext1 <4,3,6,5>, <1,0,3,2> 2732970692U, // <3,6,5,2>: Cost 3 vext3 LHS, <6,5,2,7> 2576501250U, // <3,6,5,3>: Cost 3 vext1 <4,3,6,5>, <3,4,5,6> - 2242268466U, // <3,6,5,4>: Cost 3 vrev <4,5,6,3> - 3806712536U, // <3,6,5,5>: Cost 4 vext3 LHS, <6,5,5,0> + 2576501906U, // <3,6,5,4>: Cost 3 vext1 <4,3,6,5>, <4,3,6,5> + 3650244622U, // <3,6,5,5>: Cost 4 vext1 <4,3,6,5>, <5,5,6,6> 4114633528U, // <3,6,5,6>: Cost 4 vtrnl <3,4,5,6>, <6,6,6,6> 2732970735U, // <3,6,5,7>: Cost 3 vext3 LHS, <6,5,7,5> - 2724123382U, // <3,6,5,u>: Cost 3 vext3 <6,5,u,3>, <6,5,u,3> + 2576504622U, // <3,6,5,u>: Cost 3 vext1 <4,3,6,5>, LHS 2732970749U, // <3,6,6,0>: Cost 3 vext3 LHS, <6,6,0,1> 2724270856U, // <3,6,6,1>: Cost 3 vext3 <6,6,1,3>, <6,6,1,3> 2624819706U, // <3,6,6,2>: Cost 3 vext2 <1,2,3,6>, <6,2,7,3> - 3699888686U, // <3,6,6,3>: Cost 4 vext2 <1,4,3,6>, <6,3,4,1> + 3656223234U, // <3,6,6,3>: Cost 4 vext1 <5,3,6,6>, <3,4,5,6> 2732970788U, // <3,6,6,4>: Cost 3 vext3 LHS, <6,6,4,4> 2732970800U, // <3,6,6,5>: Cost 3 vext3 LHS, <6,6,5,7> 1659228984U, // <3,6,6,6>: Cost 2 vext3 LHS, <6,6,6,6> @@ -2768,8 +2768,8 @@ 1659229078U, // <3,6,7,u>: Cost 2 vext3 LHS, <6,7,u,1> 1659229087U, // <3,6,u,0>: Cost 2 vext3 LHS, <6,u,0,1> 2689840041U, // <3,6,u,1>: Cost 3 vext3 LHS, <6,u,1,2> - 2689840048U, // <3,6,u,2>: Cost 3 vext3 LHS, <6,u,2,0> - 2238286668U, // <3,6,u,3>: Cost 3 vrev <3,u,6,3> + 2558609339U, // <3,6,u,2>: Cost 3 vext1 <1,3,6,u>, <2,6,3,u> + 2576525853U, // <3,6,u,3>: Cost 3 vext1 <4,3,6,u>, <3,4,u,6> 1659229127U, // <3,6,u,4>: Cost 2 vext3 LHS, <6,u,4,5> 2689840081U, // <3,6,u,5>: Cost 3 vext3 LHS, <6,u,5,6> 1659228984U, // <3,6,u,6>: Cost 2 vext3 LHS, <6,6,6,6> @@ -2784,7 +2784,7 @@ 2588480072U, // <3,7,0,6>: Cost 3 vext1 <6,3,7,0>, <6,3,7,0> 2732971055U, // <3,7,0,7>: Cost 3 vext3 LHS, <7,0,7,1> 1553072797U, // <3,7,0,u>: Cost 2 vext2 <1,5,3,7>, LHS - 2582511718U, // <3,7,1,0>: Cost 3 vext1 <5,3,7,1>, LHS + 2626814710U, // <3,7,1,0>: Cost 3 vext2 <1,5,3,7>, <1,0,3,2> 2626814772U, // <3,7,1,1>: Cost 3 vext2 <1,5,3,7>, <1,1,1,1> 2626814870U, // <3,7,1,2>: Cost 3 vext2 <1,5,3,7>, <1,2,3,0> 2625487854U, // <3,7,1,3>: Cost 3 vext2 <1,3,3,7>, <1,3,3,7> @@ -2794,7 +2794,7 @@ 2727367810U, // <3,7,1,7>: Cost 3 vext3 <7,1,7,3>, <7,1,7,3> 1555064195U, // <3,7,1,u>: Cost 2 vext2 <1,u,3,7>, <1,u,3,7> 2588491878U, // <3,7,2,0>: Cost 3 vext1 <6,3,7,2>, LHS - 3700557342U, // <3,7,2,1>: Cost 4 vext2 <1,5,3,7>, <2,1,3,0> + 3700557318U, // <3,7,2,1>: Cost 4 vext2 <1,5,3,7>, <2,1,0,3> 2626815592U, // <3,7,2,2>: Cost 3 vext2 <1,5,3,7>, <2,2,2,2> 2626815654U, // <3,7,2,3>: Cost 3 vext2 <1,5,3,7>, <2,3,0,1> 2588495158U, // <3,7,2,4>: Cost 3 vext1 <6,3,7,2>, RHS @@ -2804,52 +2804,52 @@ 1561036892U, // <3,7,2,u>: Cost 2 vext2 <2,u,3,7>, <2,u,3,7> 2626816150U, // <3,7,3,0>: Cost 3 vext2 <1,5,3,7>, <3,0,1,2> 2626816268U, // <3,7,3,1>: Cost 3 vext2 <1,5,3,7>, <3,1,5,3> - 2626816310U, // <3,7,3,2>: Cost 3 vext2 <1,5,3,7>, <3,2,1,0> + 2633451878U, // <3,7,3,2>: Cost 3 vext2 <2,6,3,7>, <3,2,6,3> 2626816412U, // <3,7,3,3>: Cost 3 vext2 <1,5,3,7>, <3,3,3,3> 2626816514U, // <3,7,3,4>: Cost 3 vext2 <1,5,3,7>, <3,4,5,6> 2638760514U, // <3,7,3,5>: Cost 3 vext2 <3,5,3,7>, <3,5,3,7> 2639424147U, // <3,7,3,6>: Cost 3 vext2 <3,6,3,7>, <3,6,3,7> 2826961920U, // <3,7,3,7>: Cost 3 vuzpr <1,3,5,7>, <1,3,5,7> - 2626816796U, // <3,7,3,u>: Cost 3 vext2 <1,5,3,7>, <3,u,1,0> + 2626816798U, // <3,7,3,u>: Cost 3 vext2 <1,5,3,7>, <3,u,1,2> 2582536294U, // <3,7,4,0>: Cost 3 vext1 <5,3,7,4>, LHS 2582537360U, // <3,7,4,1>: Cost 3 vext1 <5,3,7,4>, <1,5,3,7> 2588510138U, // <3,7,4,2>: Cost 3 vext1 <6,3,7,4>, <2,6,3,7> - 3700558954U, // <3,7,4,3>: Cost 4 vext2 <1,5,3,7>, <4,3,2,1> + 3700558996U, // <3,7,4,3>: Cost 4 vext2 <1,5,3,7>, <4,3,6,7> 2582539574U, // <3,7,4,4>: Cost 3 vext1 <5,3,7,4>, RHS 1553075510U, // <3,7,4,5>: Cost 2 vext2 <1,5,3,7>, RHS 2588512844U, // <3,7,4,6>: Cost 3 vext1 <6,3,7,4>, <6,3,7,4> 2564625766U, // <3,7,4,7>: Cost 3 vext1 <2,3,7,4>, <7,4,5,6> 1553075753U, // <3,7,4,u>: Cost 2 vext2 <1,5,3,7>, RHS 2732971398U, // <3,7,5,0>: Cost 3 vext3 LHS, <7,5,0,2> - 2715424148U, // <3,7,5,1>: Cost 3 vext3 <5,1,7,3>, <7,5,1,7> + 2626817744U, // <3,7,5,1>: Cost 3 vext2 <1,5,3,7>, <5,1,7,3> 3700559649U, // <3,7,5,2>: Cost 4 vext2 <1,5,3,7>, <5,2,7,3> 2626817903U, // <3,7,5,3>: Cost 3 vext2 <1,5,3,7>, <5,3,7,0> - 3900705379U, // <3,7,5,4>: Cost 4 vuzpr <1,3,5,7>, <3,5,7,4> + 2258728203U, // <3,7,5,4>: Cost 3 vrev <7,3,4,5> 2732971446U, // <3,7,5,5>: Cost 3 vext3 LHS, <7,5,5,5> 2732971457U, // <3,7,5,6>: Cost 3 vext3 LHS, <7,5,6,7> 2826964278U, // <3,7,5,7>: Cost 3 vuzpr <1,3,5,7>, RHS 2826964279U, // <3,7,5,u>: Cost 3 vuzpr <1,3,5,7>, RHS - 2600468582U, // <3,7,6,0>: Cost 3 vext1 , LHS - 2633453993U, // <3,7,6,1>: Cost 3 vext2 <2,6,3,7>, <6,1,7,3> - 2722059758U, // <3,7,6,2>: Cost 3 vext3 <6,2,7,3>, <7,6,2,7> + 2732971478U, // <3,7,6,0>: Cost 3 vext3 LHS, <7,6,0,1> + 2732971486U, // <3,7,6,1>: Cost 3 vext3 LHS, <7,6,1,0> + 2633454074U, // <3,7,6,2>: Cost 3 vext2 <2,6,3,7>, <6,2,7,3> 2633454152U, // <3,7,6,3>: Cost 3 vext2 <2,6,3,7>, <6,3,7,0> - 2600471862U, // <3,7,6,4>: Cost 3 vext1 , RHS - 1659229702U, // <3,7,6,5>: Cost 2 vext3 LHS, <7,6,5,4> + 2732971518U, // <3,7,6,4>: Cost 3 vext3 LHS, <7,6,4,5> + 2732971526U, // <3,7,6,5>: Cost 3 vext3 LHS, <7,6,5,4> 2732971537U, // <3,7,6,6>: Cost 3 vext3 LHS, <7,6,6,6> 2732971540U, // <3,7,6,7>: Cost 3 vext3 LHS, <7,6,7,0> - 1659229729U, // <3,7,6,u>: Cost 2 vext3 LHS, <7,6,u,4> + 2726041124U, // <3,7,6,u>: Cost 3 vext3 <6,u,7,3>, <7,6,u,7> 2570616934U, // <3,7,7,0>: Cost 3 vext1 <3,3,7,7>, LHS 2570617856U, // <3,7,7,1>: Cost 3 vext1 <3,3,7,7>, <1,3,5,7> 2564646635U, // <3,7,7,2>: Cost 3 vext1 <2,3,7,7>, <2,3,7,7> - 2626819344U, // <3,7,7,3>: Cost 3 vext2 <1,5,3,7>, <7,3,5,1> + 2570619332U, // <3,7,7,3>: Cost 3 vext1 <3,3,7,7>, <3,3,7,7> 2570620214U, // <3,7,7,4>: Cost 3 vext1 <3,3,7,7>, RHS - 2732971608U, // <3,7,7,5>: Cost 3 vext3 LHS, <7,7,5,5> - 2732971617U, // <3,7,7,6>: Cost 3 vext3 LHS, <7,7,6,5> + 2582564726U, // <3,7,7,5>: Cost 3 vext1 <5,3,7,7>, <5,3,7,7> + 2588537423U, // <3,7,7,6>: Cost 3 vext1 <6,3,7,7>, <6,3,7,7> 1659229804U, // <3,7,7,7>: Cost 2 vext3 LHS, <7,7,7,7> 1659229804U, // <3,7,7,u>: Cost 2 vext3 LHS, <7,7,7,7> 2626819795U, // <3,7,u,0>: Cost 3 vext2 <1,5,3,7>, 1553078062U, // <3,7,u,1>: Cost 2 vext2 <1,5,3,7>, LHS - 2626819955U, // <3,7,u,2>: Cost 3 vext2 <1,5,3,7>, + 2626819973U, // <3,7,u,2>: Cost 3 vext2 <1,5,3,7>, 2826961565U, // <3,7,u,3>: Cost 3 vuzpr <1,3,5,7>, LHS 2626820159U, // <3,7,u,4>: Cost 3 vext2 <1,5,3,7>, 1553078426U, // <3,7,u,5>: Cost 2 vext2 <1,5,3,7>, RHS @@ -2859,13 +2859,13 @@ 1611448320U, // <3,u,0,0>: Cost 2 vext3 LHS, <0,0,0,0> 1611896531U, // <3,u,0,1>: Cost 2 vext3 LHS, 1659672284U, // <3,u,0,2>: Cost 2 vext3 LHS, - 2689840867U, // <3,u,0,3>: Cost 3 vext3 LHS, + 1616099045U, // <3,u,0,3>: Cost 2 vext3 LHS, 2685638381U, // <3,u,0,4>: Cost 3 vext3 LHS, 1663874806U, // <3,u,0,5>: Cost 2 vext3 LHS, 1663874816U, // <3,u,0,6>: Cost 2 vext3 LHS, 2960313672U, // <3,u,0,7>: Cost 3 vzipr <1,2,3,0>, RHS 1611896594U, // <3,u,0,u>: Cost 2 vext3 LHS, - 68386972U, // <3,u,1,0>: Cost 1 vrev LHS + 1549763324U, // <3,u,1,0>: Cost 2 vext2 <1,0,3,u>, <1,0,3,u> 1550426957U, // <3,u,1,1>: Cost 2 vext2 <1,1,3,u>, <1,1,3,u> 537712430U, // <3,u,1,2>: Cost 1 vext3 LHS, LHS 1616541495U, // <3,u,1,3>: Cost 2 vext3 LHS, @@ -2875,7 +2875,7 @@ 1659230043U, // <3,u,1,7>: Cost 2 vext3 LHS, 537712484U, // <3,u,1,u>: Cost 1 vext3 LHS, LHS 1611890852U, // <3,u,2,0>: Cost 2 vext3 LHS, <0,2,0,2> - 1611896691U, // <3,u,2,1>: Cost 2 vext3 LHS, + 2624833102U, // <3,u,2,1>: Cost 3 vext2 <1,2,3,u>, <2,1,u,3> 1557063287U, // <3,u,2,2>: Cost 2 vext2 <2,2,3,u>, <2,2,3,u> 1616099205U, // <3,u,2,3>: Cost 2 vext3 LHS, 1611890892U, // <3,u,2,4>: Cost 2 vext3 LHS, <0,2,4,6> @@ -2885,7 +2885,7 @@ 1616541618U, // <3,u,2,u>: Cost 2 vext3 LHS, 1611896764U, // <3,u,3,0>: Cost 2 vext3 LHS, 1484973079U, // <3,u,3,1>: Cost 2 vext1 <1,3,u,3>, <1,3,u,3> - 2685638606U, // <3,u,3,2>: Cost 3 vext3 LHS, + 2685638607U, // <3,u,3,2>: Cost 3 vext3 LHS, 336380006U, // <3,u,3,3>: Cost 1 vdup3 LHS 1611896804U, // <3,u,3,4>: Cost 2 vext3 LHS, 1616541679U, // <3,u,3,5>: Cost 2 vext3 LHS, @@ -2899,7 +2899,7 @@ 1659227344U, // <3,u,4,4>: Cost 2 vext3 LHS, <4,4,4,4> 1611896895U, // <3,u,4,5>: Cost 2 vext3 LHS, 1663875144U, // <3,u,4,6>: Cost 2 vext3 LHS, - 2960346440U, // <3,u,4,7>: Cost 3 vzipr <1,2,3,4>, RHS + 1659230289U, // <3,u,4,7>: Cost 2 vext3 LHS, 1611896922U, // <3,u,4,u>: Cost 2 vext3 LHS, 1490960486U, // <3,u,5,0>: Cost 2 vext1 <2,3,u,5>, LHS 2689841261U, // <3,u,5,1>: Cost 3 vext3 LHS, @@ -2915,7 +2915,7 @@ 2689841351U, // <3,u,6,2>: Cost 3 vext3 LHS, 1616099536U, // <3,u,6,3>: Cost 2 vext3 LHS, 1659227508U, // <3,u,6,4>: Cost 2 vext3 LHS, <4,6,4,6> - 1659230431U, // <3,u,6,5>: Cost 2 vext3 LHS, + 2690283746U, // <3,u,6,5>: Cost 3 vext3 LHS, 1659228984U, // <3,u,6,6>: Cost 2 vext3 LHS, <6,6,6,6> 1659230445U, // <3,u,6,7>: Cost 2 vext3 LHS, 1616099581U, // <3,u,6,u>: Cost 2 vext3 LHS, @@ -2928,7 +2928,7 @@ 2722060599U, // <3,u,7,6>: Cost 3 vext3 <6,2,7,3>, 1659229804U, // <3,u,7,7>: Cost 2 vext3 LHS, <7,7,7,7> 1485010734U, // <3,u,7,u>: Cost 2 vext1 <1,3,u,7>, LHS - 73032403U, // <3,u,u,0>: Cost 1 vrev LHS + 1616099665U, // <3,u,u,0>: Cost 2 vext3 LHS, 1611897179U, // <3,u,u,1>: Cost 2 vext3 LHS, 537712997U, // <3,u,u,2>: Cost 1 vext3 LHS, LHS 336380006U, // <3,u,u,3>: Cost 1 vdup3 LHS @@ -2940,11 +2940,11 @@ 2691907584U, // <4,0,0,0>: Cost 3 vext3 <1,2,3,4>, <0,0,0,0> 2691907594U, // <4,0,0,1>: Cost 3 vext3 <1,2,3,4>, <0,0,1,1> 2691907604U, // <4,0,0,2>: Cost 3 vext3 <1,2,3,4>, <0,0,2,2> - 3306285199U, // <4,0,0,3>: Cost 4 vrev <3,0,0,4> - 2648064338U, // <4,0,0,4>: Cost 3 vext2 <5,1,4,0>, <0,4,1,5> + 3709862144U, // <4,0,0,3>: Cost 4 vext2 <3,1,4,0>, <0,3,1,4> + 2684682280U, // <4,0,0,4>: Cost 3 vext3 <0,0,4,4>, <0,0,4,4> 3694600633U, // <4,0,0,5>: Cost 4 vext2 <0,5,4,0>, <0,5,4,0> - 3324203290U, // <4,0,0,6>: Cost 4 vrev <6,0,0,4> - 3330175987U, // <4,0,0,7>: Cost 4 vrev <7,0,0,4> + 3291431290U, // <4,0,0,6>: Cost 4 vrev <0,4,6,0> + 3668342067U, // <4,0,0,7>: Cost 4 vext1 <7,4,0,0>, <7,4,0,0> 2691907657U, // <4,0,0,u>: Cost 3 vext3 <1,2,3,4>, <0,0,u,1> 2570715238U, // <4,0,1,0>: Cost 3 vext1 <3,4,0,1>, LHS 2570716058U, // <4,0,1,1>: Cost 3 vext1 <3,4,0,1>, <1,2,3,4> @@ -2952,7 +2952,7 @@ 2570717648U, // <4,0,1,3>: Cost 3 vext1 <3,4,0,1>, <3,4,0,1> 2570718518U, // <4,0,1,4>: Cost 3 vext1 <3,4,0,1>, RHS 2594607206U, // <4,0,1,5>: Cost 3 vext1 <7,4,0,1>, <5,6,7,4> - 3721807091U, // <4,0,1,6>: Cost 4 vext2 <5,1,4,0>, <1,6,5,7> + 3662377563U, // <4,0,1,6>: Cost 4 vext1 <6,4,0,1>, <6,4,0,1> 2594608436U, // <4,0,1,7>: Cost 3 vext1 <7,4,0,1>, <7,4,0,1> 1618165916U, // <4,0,1,u>: Cost 2 vext3 <1,2,3,4>, LHS 2685714598U, // <4,0,2,0>: Cost 3 vext3 <0,2,0,4>, <0,2,0,4> @@ -2960,19 +2960,19 @@ 2685862072U, // <4,0,2,2>: Cost 3 vext3 <0,2,2,4>, <0,2,2,4> 2631476937U, // <4,0,2,3>: Cost 3 vext2 <2,3,4,0>, <2,3,4,0> 2685714636U, // <4,0,2,4>: Cost 3 vext3 <0,2,0,4>, <0,2,4,6> - 3705218930U, // <4,0,2,5>: Cost 4 vext2 <2,3,4,0>, <2,5,4,7> + 3765649622U, // <4,0,2,5>: Cost 4 vext3 <1,2,3,4>, <0,2,5,7> 2686157020U, // <4,0,2,6>: Cost 3 vext3 <0,2,6,4>, <0,2,6,4> - 3331503253U, // <4,0,2,7>: Cost 4 vrev <7,2,0,4> + 3668358453U, // <4,0,2,7>: Cost 4 vext1 <7,4,0,2>, <7,4,0,2> 2686304494U, // <4,0,2,u>: Cost 3 vext3 <0,2,u,4>, <0,2,u,4> 3632529510U, // <4,0,3,0>: Cost 4 vext1 <1,4,0,3>, LHS 2686451968U, // <4,0,3,1>: Cost 3 vext3 <0,3,1,4>, <0,3,1,4> - 2228561577U, // <4,0,3,2>: Cost 3 vrev <2,3,0,4> + 2686525705U, // <4,0,3,2>: Cost 3 vext3 <0,3,2,4>, <0,3,2,4> 3760341266U, // <4,0,3,3>: Cost 4 vext3 <0,3,3,4>, <0,3,3,4> 3632532790U, // <4,0,3,4>: Cost 4 vext1 <1,4,0,3>, RHS 3913254606U, // <4,0,3,5>: Cost 4 vuzpr <3,4,5,0>, <2,3,4,5> 3705219740U, // <4,0,3,6>: Cost 4 vext2 <2,3,4,0>, <3,6,4,7> - 3332166886U, // <4,0,3,7>: Cost 4 vrev <7,3,0,4> - 2264397759U, // <4,0,3,u>: Cost 3 vrev + 3713845990U, // <4,0,3,7>: Cost 4 vext2 <3,7,4,0>, <3,7,4,0> + 2686451968U, // <4,0,3,u>: Cost 3 vext3 <0,3,1,4>, <0,3,1,4> 2552823910U, // <4,0,4,0>: Cost 3 vext1 <0,4,0,4>, LHS 2691907922U, // <4,0,4,1>: Cost 3 vext3 <1,2,3,4>, <0,4,1,5> 2691907932U, // <4,0,4,2>: Cost 3 vext3 <1,2,3,4>, <0,4,2,6> @@ -2980,13 +2980,13 @@ 2552827190U, // <4,0,4,4>: Cost 3 vext1 <0,4,0,4>, RHS 2631478582U, // <4,0,4,5>: Cost 3 vext2 <2,3,4,0>, RHS 3626570017U, // <4,0,4,6>: Cost 4 vext1 <0,4,0,4>, <6,0,1,2> - 3332830519U, // <4,0,4,7>: Cost 4 vrev <7,4,0,4> + 3668374839U, // <4,0,4,7>: Cost 4 vext1 <7,4,0,4>, <7,4,0,4> 2552829742U, // <4,0,4,u>: Cost 3 vext1 <0,4,0,4>, LHS - 2570748006U, // <4,0,5,0>: Cost 3 vext1 <3,4,0,5>, LHS + 2558804070U, // <4,0,5,0>: Cost 3 vext1 <1,4,0,5>, LHS 1839644774U, // <4,0,5,1>: Cost 2 vzipl RHS, LHS 2913386660U, // <4,0,5,2>: Cost 3 vzipl RHS, <0,2,0,2> - 2570750102U, // <4,0,5,3>: Cost 3 vext1 <3,4,0,5>, <3,0,1,2> - 2570751286U, // <4,0,5,4>: Cost 3 vext1 <3,4,0,5>, RHS + 2570750420U, // <4,0,5,3>: Cost 3 vext1 <3,4,0,5>, <3,4,0,5> + 2558807350U, // <4,0,5,4>: Cost 3 vext1 <1,4,0,5>, RHS 3987128750U, // <4,0,5,5>: Cost 4 vzipl RHS, <0,5,2,7> 3987128822U, // <4,0,5,6>: Cost 4 vzipl RHS, <0,6,1,7> 2594641208U, // <4,0,5,7>: Cost 3 vext1 <7,4,0,5>, <7,4,0,5> @@ -2996,45 +2996,45 @@ 1973862502U, // <4,0,6,2>: Cost 2 vtrnl RHS, LHS 2570758613U, // <4,0,6,3>: Cost 3 vext1 <3,4,0,6>, <3,4,0,6> 2552843574U, // <4,0,6,4>: Cost 3 vext1 <0,4,0,6>, RHS - 2656694991U, // <4,0,6,5>: Cost 3 vext2 <6,5,4,0>, <6,5,4,0> - 3721810744U, // <4,0,6,6>: Cost 4 vext2 <5,1,4,0>, <6,6,6,6> + 2217664887U, // <4,0,6,5>: Cost 3 vrev <0,4,5,6> + 3662418528U, // <4,0,6,6>: Cost 4 vext1 <6,4,0,6>, <6,4,0,6> 2658022257U, // <4,0,6,7>: Cost 3 vext2 <6,7,4,0>, <6,7,4,0> 1973862556U, // <4,0,6,u>: Cost 2 vtrnl RHS, LHS - 3721810938U, // <4,0,7,0>: Cost 4 vext2 <5,1,4,0>, <7,0,1,2> - 2689106500U, // <4,0,7,1>: Cost 3 vext3 <0,7,1,4>, <0,7,1,4> + 3731764218U, // <4,0,7,0>: Cost 4 vext2 <6,7,4,0>, <7,0,1,2> + 3988324454U, // <4,0,7,1>: Cost 4 vzipl <4,7,5,0>, LHS 4122034278U, // <4,0,7,2>: Cost 4 vtrnl <4,6,7,1>, LHS - 3310930630U, // <4,0,7,3>: Cost 4 vrev <3,7,0,4> - 3721811302U, // <4,0,7,4>: Cost 4 vext2 <5,1,4,0>, <7,4,5,6> - 3721811345U, // <4,0,7,5>: Cost 4 vext2 <5,1,4,0>, <7,5,1,4> - 2255106897U, // <4,0,7,6>: Cost 3 vrev <6,7,0,4> - 3721811564U, // <4,0,7,7>: Cost 4 vext2 <5,1,4,0>, <7,7,7,7> - 2668639912U, // <4,0,7,u>: Cost 3 vext2 , <7,u,5,4> + 3735082246U, // <4,0,7,3>: Cost 4 vext2 <7,3,4,0>, <7,3,4,0> + 3731764536U, // <4,0,7,4>: Cost 4 vext2 <6,7,4,0>, <7,4,0,5> + 3937145718U, // <4,0,7,5>: Cost 4 vuzpr <7,4,5,0>, <6,7,4,5> + 3737073145U, // <4,0,7,6>: Cost 4 vext2 <7,6,4,0>, <7,6,4,0> + 3731764844U, // <4,0,7,7>: Cost 4 vext2 <6,7,4,0>, <7,7,7,7> + 4122034332U, // <4,0,7,u>: Cost 4 vtrnl <4,6,7,1>, LHS 2552856678U, // <4,0,u,0>: Cost 3 vext1 <0,4,0,u>, LHS 1841635430U, // <4,0,u,1>: Cost 2 vzipl RHS, LHS 1618166429U, // <4,0,u,2>: Cost 2 vext3 <1,2,3,4>, LHS 2570774999U, // <4,0,u,3>: Cost 3 vext1 <3,4,0,u>, <3,4,0,u> 2552859958U, // <4,0,u,4>: Cost 3 vext1 <0,4,0,u>, RHS 2631481498U, // <4,0,u,5>: Cost 3 vext2 <2,3,4,0>, RHS - 2255770530U, // <4,0,u,6>: Cost 3 vrev <6,u,0,4> + 2686157020U, // <4,0,u,6>: Cost 3 vext3 <0,2,6,4>, <0,2,6,4> 2594665787U, // <4,0,u,7>: Cost 3 vext1 <7,4,0,u>, <7,4,0,u> 1618166483U, // <4,0,u,u>: Cost 2 vext3 <1,2,3,4>, LHS 2617548837U, // <4,1,0,0>: Cost 3 vext2 <0,0,4,1>, <0,0,4,1> 2622857318U, // <4,1,0,1>: Cost 3 vext2 <0,u,4,1>, LHS 3693281484U, // <4,1,0,2>: Cost 4 vext2 <0,3,4,1>, <0,2,4,6> - 2232617112U, // <4,1,0,3>: Cost 3 vrev <3,0,1,4> + 2691908342U, // <4,1,0,3>: Cost 3 vext3 <1,2,3,4>, <1,0,3,2> 2622857554U, // <4,1,0,4>: Cost 3 vext2 <0,u,4,1>, <0,4,1,5> - 3694608826U, // <4,1,0,5>: Cost 4 vext2 <0,5,4,1>, <0,5,4,1> + 3764470538U, // <4,1,0,5>: Cost 4 vext3 <1,0,5,4>, <1,0,5,4> 3695272459U, // <4,1,0,6>: Cost 4 vext2 <0,6,4,1>, <0,6,4,1> - 2256507900U, // <4,1,0,7>: Cost 3 vrev <7,0,1,4> + 3733094980U, // <4,1,0,7>: Cost 4 vext2 <7,0,4,1>, <0,7,1,4> 2622857885U, // <4,1,0,u>: Cost 3 vext2 <0,u,4,1>, LHS - 2215362654U, // <4,1,1,0>: Cost 3 vrev <0,1,1,4> - 2221335351U, // <4,1,1,1>: Cost 3 vrev <1,1,1,4> + 3696599798U, // <4,1,1,0>: Cost 4 vext2 <0,u,4,1>, <1,0,3,2> + 2691097399U, // <4,1,1,1>: Cost 3 vext3 <1,1,1,4>, <1,1,1,4> 2631484314U, // <4,1,1,2>: Cost 3 vext2 <2,3,4,1>, <1,2,3,4> 2691908424U, // <4,1,1,3>: Cost 3 vext3 <1,2,3,4>, <1,1,3,3> 3696600125U, // <4,1,1,4>: Cost 4 vext2 <0,u,4,1>, <1,4,3,5> 3696600175U, // <4,1,1,5>: Cost 4 vext2 <0,u,4,1>, <1,5,0,1> 3696600307U, // <4,1,1,6>: Cost 4 vext2 <0,u,4,1>, <1,6,5,7> - 3330913357U, // <4,1,1,7>: Cost 4 vrev <7,1,1,4> + 3668423997U, // <4,1,1,7>: Cost 4 vext1 <7,4,1,1>, <7,4,1,1> 2691908469U, // <4,1,1,u>: Cost 3 vext3 <1,2,3,4>, <1,1,u,3> 2570797158U, // <4,1,2,0>: Cost 3 vext1 <3,4,1,2>, LHS 2570797978U, // <4,1,2,1>: Cost 3 vext1 <3,4,1,2>, <1,2,3,4> @@ -3043,7 +3043,7 @@ 2570800438U, // <4,1,2,4>: Cost 3 vext1 <3,4,1,2>, RHS 3765650347U, // <4,1,2,5>: Cost 4 vext3 <1,2,3,4>, <1,2,5,3> 3696601018U, // <4,1,2,6>: Cost 4 vext2 <0,u,4,1>, <2,6,3,7> - 3331576990U, // <4,1,2,7>: Cost 4 vrev <7,2,1,4> + 3668432190U, // <4,1,2,7>: Cost 4 vext1 <7,4,1,2>, <7,4,1,2> 1618535367U, // <4,1,2,u>: Cost 2 vext3 <1,2,u,4>, <1,2,u,4> 2564833382U, // <4,1,3,0>: Cost 3 vext1 <2,4,1,3>, LHS 2691908568U, // <4,1,3,1>: Cost 3 vext3 <1,2,3,4>, <1,3,1,3> @@ -3060,15 +3060,15 @@ 3113877606U, // <4,1,4,3>: Cost 3 vtrnr <4,4,4,4>, LHS 3760194630U, // <4,1,4,4>: Cost 4 vext3 <0,3,1,4>, <1,4,4,5> 2622860598U, // <4,1,4,5>: Cost 3 vext2 <0,u,4,1>, RHS - 3767198807U, // <4,1,4,6>: Cost 4 vext3 <1,4,6,4>, <1,4,6,4> + 3297436759U, // <4,1,4,6>: Cost 4 vrev <1,4,6,4> 3800007772U, // <4,1,4,7>: Cost 4 vext3 <7,0,1,4>, <1,4,7,0> 2622860841U, // <4,1,4,u>: Cost 3 vext2 <0,u,4,1>, RHS 1479164006U, // <4,1,5,0>: Cost 2 vext1 <0,4,1,5>, LHS - 2552906548U, // <4,1,5,1>: Cost 3 vext1 <0,4,1,5>, <1,1,1,1> + 2552906486U, // <4,1,5,1>: Cost 3 vext1 <0,4,1,5>, <1,0,3,2> 2552907299U, // <4,1,5,2>: Cost 3 vext1 <0,4,1,5>, <2,1,3,5> 2552907926U, // <4,1,5,3>: Cost 3 vext1 <0,4,1,5>, <3,0,1,2> 1479167286U, // <4,1,5,4>: Cost 2 vext1 <0,4,1,5>, RHS - 2552909490U, // <4,1,5,5>: Cost 3 vext1 <0,4,1,5>, <5,1,4,0> + 2913387664U, // <4,1,5,5>: Cost 3 vzipl RHS, <1,5,3,7> 2600686074U, // <4,1,5,6>: Cost 3 vext1 , <6,2,7,3> 2600686586U, // <4,1,5,7>: Cost 3 vext1 , <7,0,1,2> 1479169838U, // <4,1,5,u>: Cost 2 vext1 <0,4,1,5>, LHS @@ -3077,8 +3077,8 @@ 4028205206U, // <4,1,6,2>: Cost 4 vzipr <0,2,4,6>, <3,0,1,2> 3089858662U, // <4,1,6,3>: Cost 3 vtrnr <0,4,2,6>, LHS 2552917302U, // <4,1,6,4>: Cost 3 vext1 <0,4,1,6>, RHS - 3047605248U, // <4,1,6,5>: Cost 3 vtrnl RHS, <1,3,5,7> - 3626660235U, // <4,1,6,6>: Cost 4 vext1 <0,4,1,6>, <6,1,4,0> + 2223637584U, // <4,1,6,5>: Cost 3 vrev <1,4,5,6> + 4121347081U, // <4,1,6,6>: Cost 4 vtrnl RHS, <1,3,6,7> 3721155406U, // <4,1,6,7>: Cost 4 vext2 <5,0,4,1>, <6,7,0,1> 2552919854U, // <4,1,6,u>: Cost 3 vext1 <0,4,1,6>, LHS 2659357716U, // <4,1,7,0>: Cost 3 vext2 <7,0,4,1>, <7,0,4,1> @@ -3087,51 +3087,51 @@ 2695226671U, // <4,1,7,3>: Cost 3 vext3 <1,7,3,4>, <1,7,3,4> 3721155942U, // <4,1,7,4>: Cost 4 vext2 <5,0,4,1>, <7,4,5,6> 3721155976U, // <4,1,7,5>: Cost 4 vext2 <5,0,4,1>, <7,5,0,4> - 3721156102U, // <4,1,7,6>: Cost 4 vext2 <5,0,4,1>, <7,6,5,4> + 3662500458U, // <4,1,7,6>: Cost 4 vext1 <6,4,1,7>, <6,4,1,7> 3721156204U, // <4,1,7,7>: Cost 4 vext2 <5,0,4,1>, <7,7,7,7> 2659357716U, // <4,1,7,u>: Cost 3 vext2 <7,0,4,1>, <7,0,4,1> 1479188582U, // <4,1,u,0>: Cost 2 vext1 <0,4,1,u>, LHS - 2552931124U, // <4,1,u,1>: Cost 3 vext1 <0,4,1,u>, <1,1,1,1> + 2552931062U, // <4,1,u,1>: Cost 3 vext1 <0,4,1,u>, <1,0,3,2> 2552931944U, // <4,1,u,2>: Cost 3 vext1 <0,4,1,u>, <2,2,2,2> 1622148480U, // <4,1,u,3>: Cost 2 vext3 <1,u,3,4>, <1,u,3,4> 1479191862U, // <4,1,u,4>: Cost 2 vext1 <0,4,1,u>, RHS 2622863514U, // <4,1,u,5>: Cost 3 vext2 <0,u,4,1>, RHS - 2588766827U, // <4,1,u,6>: Cost 3 vext1 <6,4,1,u>, <6,4,1,u> - 2261816964U, // <4,1,u,7>: Cost 3 vrev <7,u,1,4> + 2588725862U, // <4,1,u,6>: Cost 3 vext1 <6,4,1,3>, <6,4,1,3> + 2600686586U, // <4,1,u,7>: Cost 3 vext1 , <7,0,1,2> 1479194414U, // <4,1,u,u>: Cost 2 vext1 <0,4,1,u>, LHS - 2588770406U, // <4,2,0,0>: Cost 3 vext1 <6,4,2,0>, LHS + 2617557030U, // <4,2,0,0>: Cost 3 vext2 <0,0,4,2>, <0,0,4,2> 2622865510U, // <4,2,0,1>: Cost 3 vext2 <0,u,4,2>, LHS 2622865612U, // <4,2,0,2>: Cost 3 vext2 <0,u,4,2>, <0,2,4,6> - 2232690849U, // <4,2,0,3>: Cost 3 vrev <3,0,2,4> + 3693289753U, // <4,2,0,3>: Cost 4 vext2 <0,3,4,2>, <0,3,4,2> 2635473244U, // <4,2,0,4>: Cost 3 vext2 <3,0,4,2>, <0,4,2,6> 3765650918U, // <4,2,0,5>: Cost 4 vext3 <1,2,3,4>, <2,0,5,7> - 2250608940U, // <4,2,0,6>: Cost 3 vrev <6,0,2,4> - 2256581637U, // <4,2,0,7>: Cost 3 vrev <7,0,2,4> + 2696775148U, // <4,2,0,6>: Cost 3 vext3 <2,0,6,4>, <2,0,6,4> + 3695944285U, // <4,2,0,7>: Cost 4 vext2 <0,7,4,2>, <0,7,4,2> 2622866077U, // <4,2,0,u>: Cost 3 vext2 <0,u,4,2>, LHS - 2215436391U, // <4,2,1,0>: Cost 3 vrev <0,1,2,4> + 3696607990U, // <4,2,1,0>: Cost 4 vext2 <0,u,4,2>, <1,0,3,2> 3696608052U, // <4,2,1,1>: Cost 4 vext2 <0,u,4,2>, <1,1,1,1> 3696608150U, // <4,2,1,2>: Cost 4 vext2 <0,u,4,2>, <1,2,3,0> 3895574630U, // <4,2,1,3>: Cost 4 vuzpr <0,4,u,2>, LHS 2691909162U, // <4,2,1,4>: Cost 3 vext3 <1,2,3,4>, <2,1,4,3> 3696608400U, // <4,2,1,5>: Cost 4 vext2 <0,u,4,2>, <1,5,3,7> 3760784956U, // <4,2,1,6>: Cost 4 vext3 <0,4,0,4>, <2,1,6,3> - 3330987094U, // <4,2,1,7>: Cost 4 vrev <7,1,2,4> - 2263217967U, // <4,2,1,u>: Cost 3 vrev - 2216100024U, // <4,2,2,0>: Cost 3 vrev <0,2,2,4> + 3773908549U, // <4,2,1,7>: Cost 5 vext3 <2,5,7,4>, <2,1,7,3> + 2691909162U, // <4,2,1,u>: Cost 3 vext3 <1,2,3,4>, <2,1,4,3> + 3696608748U, // <4,2,2,0>: Cost 4 vext2 <0,u,4,2>, <2,0,6,4> 3696608828U, // <4,2,2,1>: Cost 4 vext2 <0,u,4,2>, <2,1,6,3> 2691909224U, // <4,2,2,2>: Cost 3 vext3 <1,2,3,4>, <2,2,2,2> 2691909234U, // <4,2,2,3>: Cost 3 vext3 <1,2,3,4>, <2,2,3,3> 3759605368U, // <4,2,2,4>: Cost 4 vext3 <0,2,2,4>, <2,2,4,0> 3696609156U, // <4,2,2,5>: Cost 4 vext2 <0,u,4,2>, <2,5,6,7> 3760785040U, // <4,2,2,6>: Cost 4 vext3 <0,4,0,4>, <2,2,6,6> - 3331650727U, // <4,2,2,7>: Cost 4 vrev <7,2,2,4> + 3668505927U, // <4,2,2,7>: Cost 4 vext1 <7,4,2,2>, <7,4,2,2> 2691909279U, // <4,2,2,u>: Cost 3 vext3 <1,2,3,4>, <2,2,u,3> 2691909286U, // <4,2,3,0>: Cost 3 vext3 <1,2,3,4>, <2,3,0,1> 3764840111U, // <4,2,3,1>: Cost 4 vext3 <1,1,1,4>, <2,3,1,1> - 3696609590U, // <4,2,3,2>: Cost 4 vext2 <0,u,4,2>, <3,2,1,0> + 3765651129U, // <4,2,3,2>: Cost 4 vext3 <1,2,3,4>, <2,3,2,2> 2698544836U, // <4,2,3,3>: Cost 3 vext3 <2,3,3,4>, <2,3,3,4> 2685863630U, // <4,2,3,4>: Cost 3 vext3 <0,2,2,4>, <2,3,4,5> - 3772434134U, // <4,2,3,5>: Cost 4 vext3 <2,3,5,4>, <2,3,5,4> + 2698692310U, // <4,2,3,5>: Cost 3 vext3 <2,3,5,4>, <2,3,5,4> 3772507871U, // <4,2,3,6>: Cost 4 vext3 <2,3,6,4>, <2,3,6,4> 2698839784U, // <4,2,3,7>: Cost 3 vext3 <2,3,7,4>, <2,3,7,4> 2691909358U, // <4,2,3,u>: Cost 3 vext3 <1,2,3,4>, <2,3,u,1> @@ -3141,7 +3141,7 @@ 2699208469U, // <4,2,4,3>: Cost 3 vext3 <2,4,3,4>, <2,4,3,4> 2564918582U, // <4,2,4,4>: Cost 3 vext1 <2,4,2,4>, RHS 2622868790U, // <4,2,4,5>: Cost 3 vext2 <0,u,4,2>, RHS - 2699429680U, // <4,2,4,6>: Cost 3 vext3 <2,4,6,4>, <2,4,6,4> + 2229667632U, // <4,2,4,6>: Cost 3 vrev <2,4,6,4> 3800082229U, // <4,2,4,7>: Cost 4 vext3 <7,0,2,4>, <2,4,7,0> 2622869033U, // <4,2,4,u>: Cost 3 vext2 <0,u,4,2>, RHS 2552979558U, // <4,2,5,0>: Cost 3 vext1 <0,4,2,5>, LHS @@ -3149,17 +3149,17 @@ 2564925032U, // <4,2,5,2>: Cost 3 vext1 <2,4,2,5>, <2,2,2,2> 2967060582U, // <4,2,5,3>: Cost 3 vzipr <2,3,4,5>, LHS 2552982838U, // <4,2,5,4>: Cost 3 vext1 <0,4,2,5>, RHS - 3626725123U, // <4,2,5,5>: Cost 4 vext1 <0,4,2,5>, <5,2,4,0> + 3987130190U, // <4,2,5,5>: Cost 4 vzipl RHS, <2,5,0,7> 2913388474U, // <4,2,5,6>: Cost 3 vzipl RHS, <2,6,3,7> 3895577910U, // <4,2,5,7>: Cost 4 vuzpr <0,4,u,2>, RHS 2552985390U, // <4,2,5,u>: Cost 3 vext1 <0,4,2,5>, LHS 1479245926U, // <4,2,6,0>: Cost 2 vext1 <0,4,2,6>, LHS - 2552988468U, // <4,2,6,1>: Cost 3 vext1 <0,4,2,6>, <1,1,1,1> + 2552988406U, // <4,2,6,1>: Cost 3 vext1 <0,4,2,6>, <1,0,3,2> 2552989288U, // <4,2,6,2>: Cost 3 vext1 <0,4,2,6>, <2,2,2,2> 2954461286U, // <4,2,6,3>: Cost 3 vzipr <0,2,4,6>, LHS 1479249206U, // <4,2,6,4>: Cost 2 vext1 <0,4,2,6>, RHS - 2600767184U, // <4,2,6,5>: Cost 3 vext1 , <5,1,7,3> - 2552992220U, // <4,2,6,6>: Cost 3 vext1 <0,4,2,6>, <6,2,4,0> + 2229610281U, // <4,2,6,5>: Cost 3 vrev <2,4,5,6> + 2600767994U, // <4,2,6,6>: Cost 3 vext1 , <6,2,7,3> 2600768506U, // <4,2,6,7>: Cost 3 vext1 , <7,0,1,2> 1479251758U, // <4,2,6,u>: Cost 2 vext1 <0,4,2,6>, LHS 2659365909U, // <4,2,7,0>: Cost 3 vext2 <7,0,4,2>, <7,0,4,2> @@ -3167,17 +3167,17 @@ 3734434999U, // <4,2,7,2>: Cost 4 vext2 <7,2,4,2>, <7,2,4,2> 2701199368U, // <4,2,7,3>: Cost 3 vext3 <2,7,3,4>, <2,7,3,4> 4175774618U, // <4,2,7,4>: Cost 4 vtrnr <2,4,5,7>, <1,2,3,4> - 3323023498U, // <4,2,7,5>: Cost 4 vrev <5,7,2,4> + 3303360298U, // <4,2,7,5>: Cost 4 vrev <2,4,5,7> 3727136217U, // <4,2,7,6>: Cost 4 vext2 <6,0,4,2>, <7,6,0,4> 3727136364U, // <4,2,7,7>: Cost 4 vext2 <6,0,4,2>, <7,7,7,7> 2659365909U, // <4,2,7,u>: Cost 3 vext2 <7,0,4,2>, <7,0,4,2> 1479262310U, // <4,2,u,0>: Cost 2 vext1 <0,4,2,u>, LHS - 2553004852U, // <4,2,u,1>: Cost 3 vext1 <0,4,2,u>, <1,1,1,1> + 2553004790U, // <4,2,u,1>: Cost 3 vext1 <0,4,2,u>, <1,0,3,2> 2553005672U, // <4,2,u,2>: Cost 3 vext1 <0,4,2,u>, <2,2,2,2> 2954477670U, // <4,2,u,3>: Cost 3 vzipr <0,2,4,u>, LHS 1479265590U, // <4,2,u,4>: Cost 2 vext1 <0,4,2,u>, RHS 2622871706U, // <4,2,u,5>: Cost 3 vext2 <0,u,4,2>, RHS - 2702084212U, // <4,2,u,6>: Cost 3 vext3 <2,u,6,4>, <2,u,6,4> + 2229700404U, // <4,2,u,6>: Cost 3 vrev <2,4,6,u> 2600784890U, // <4,2,u,7>: Cost 3 vext1 , <7,0,1,2> 1479268142U, // <4,2,u,u>: Cost 2 vext1 <0,4,2,u>, LHS 3765651595U, // <4,3,0,0>: Cost 4 vext3 <1,2,3,4>, <3,0,0,0> @@ -3185,44 +3185,44 @@ 2702452897U, // <4,3,0,2>: Cost 3 vext3 <3,0,2,4>, <3,0,2,4> 3693297946U, // <4,3,0,3>: Cost 4 vext2 <0,3,4,3>, <0,3,4,3> 3760711856U, // <4,3,0,4>: Cost 4 vext3 <0,3,u,4>, <3,0,4,1> - 4181690062U, // <4,3,0,5>: Cost 4 vtrnr <3,4,5,0>, <2,3,4,5> - 3324424501U, // <4,3,0,6>: Cost 4 vrev <6,0,3,4> - 3330397198U, // <4,3,0,7>: Cost 4 vrev <7,0,3,4> + 2235533820U, // <4,3,0,5>: Cost 3 vrev <3,4,5,0> + 3309349381U, // <4,3,0,6>: Cost 4 vrev <3,4,6,0> + 3668563278U, // <4,3,0,7>: Cost 4 vext1 <7,4,3,0>, <7,4,3,0> 2691909845U, // <4,3,0,u>: Cost 3 vext3 <1,2,3,4>, <3,0,u,2> - 3626762342U, // <4,3,1,0>: Cost 4 vext1 <0,4,3,1>, LHS + 2235173328U, // <4,3,1,0>: Cost 3 vrev <3,4,0,1> 3764840678U, // <4,3,1,1>: Cost 4 vext3 <1,1,1,4>, <3,1,1,1> 2630173594U, // <4,3,1,2>: Cost 3 vext2 <2,1,4,3>, <1,2,3,4> - 2233428219U, // <4,3,1,3>: Cost 3 vrev <3,1,3,4> + 2703190267U, // <4,3,1,3>: Cost 3 vext3 <3,1,3,4>, <3,1,3,4> 3760195840U, // <4,3,1,4>: Cost 4 vext3 <0,3,1,4>, <3,1,4,0> 3765651724U, // <4,3,1,5>: Cost 4 vext3 <1,2,3,4>, <3,1,5,3> - 3325088134U, // <4,3,1,6>: Cost 4 vrev <6,1,3,4> + 3309357574U, // <4,3,1,6>: Cost 4 vrev <3,4,6,1> 3769633054U, // <4,3,1,7>: Cost 4 vext3 <1,u,3,4>, <3,1,7,3> 2703558952U, // <4,3,1,u>: Cost 3 vext3 <3,1,u,4>, <3,1,u,4> - 2582888550U, // <4,3,2,0>: Cost 3 vext1 <5,4,3,2>, LHS - 1148404634U, // <4,3,2,1>: Cost 2 vrev <1,2,3,4> - 2582890190U, // <4,3,2,2>: Cost 3 vext1 <5,4,3,2>, <2,3,4,5> - 2234091852U, // <4,3,2,3>: Cost 3 vrev <3,2,3,4> - 2582891830U, // <4,3,2,4>: Cost 3 vext1 <5,4,3,2>, RHS - 2246037246U, // <4,3,2,5>: Cost 3 vrev <5,2,3,4> + 3626770534U, // <4,3,2,0>: Cost 4 vext1 <0,4,3,2>, LHS + 2630174250U, // <4,3,2,1>: Cost 3 vext2 <2,1,4,3>, <2,1,4,3> + 3765651777U, // <4,3,2,2>: Cost 4 vext3 <1,2,3,4>, <3,2,2,2> + 2703853900U, // <4,3,2,3>: Cost 3 vext3 <3,2,3,4>, <3,2,3,4> + 3626773814U, // <4,3,2,4>: Cost 4 vext1 <0,4,3,2>, RHS + 2704001374U, // <4,3,2,5>: Cost 3 vext3 <3,2,5,4>, <3,2,5,4> 3765651814U, // <4,3,2,6>: Cost 4 vext3 <1,2,3,4>, <3,2,6,3> - 2257982640U, // <4,3,2,7>: Cost 3 vrev <7,2,3,4> - 1190213513U, // <4,3,2,u>: Cost 2 vrev + 3769633135U, // <4,3,2,7>: Cost 4 vext3 <1,u,3,4>, <3,2,7,3> + 2634819681U, // <4,3,2,u>: Cost 3 vext2 <2,u,4,3>, <2,u,4,3> 3765651839U, // <4,3,3,0>: Cost 4 vext3 <1,2,3,4>, <3,3,0,1> - 2222810091U, // <4,3,3,1>: Cost 3 vrev <1,3,3,4> - 2228782788U, // <4,3,3,2>: Cost 3 vrev <2,3,3,4> + 3765651848U, // <4,3,3,1>: Cost 4 vext3 <1,2,3,4>, <3,3,1,1> + 3710552404U, // <4,3,3,2>: Cost 4 vext2 <3,2,4,3>, <3,2,4,3> 2691910044U, // <4,3,3,3>: Cost 3 vext3 <1,2,3,4>, <3,3,3,3> 2704591270U, // <4,3,3,4>: Cost 3 vext3 <3,3,4,4>, <3,3,4,4> 3769633202U, // <4,3,3,5>: Cost 4 vext3 <1,u,3,4>, <3,3,5,7> 3703917212U, // <4,3,3,6>: Cost 4 vext2 <2,1,4,3>, <3,6,4,7> 3769633220U, // <4,3,3,7>: Cost 4 vext3 <1,u,3,4>, <3,3,7,7> - 2264618970U, // <4,3,3,u>: Cost 3 vrev + 2691910044U, // <4,3,3,u>: Cost 3 vext3 <1,2,3,4>, <3,3,3,3> 2691910096U, // <4,3,4,0>: Cost 3 vext3 <1,2,3,4>, <3,4,0,1> 2691910106U, // <4,3,4,1>: Cost 3 vext3 <1,2,3,4>, <3,4,1,2> 2564990741U, // <4,3,4,2>: Cost 3 vext1 <2,4,3,4>, <2,4,3,4> 3765651946U, // <4,3,4,3>: Cost 4 vext3 <1,2,3,4>, <3,4,3,0> 2691910136U, // <4,3,4,4>: Cost 3 vext3 <1,2,3,4>, <3,4,4,5> 2686454274U, // <4,3,4,5>: Cost 3 vext3 <0,3,1,4>, <3,4,5,6> - 2705402377U, // <4,3,4,6>: Cost 3 vext3 <3,4,6,4>, <3,4,6,4> + 2235640329U, // <4,3,4,6>: Cost 3 vrev <3,4,6,4> 3801483792U, // <4,3,4,7>: Cost 4 vext3 <7,2,3,4>, <3,4,7,2> 2691910168U, // <4,3,4,u>: Cost 3 vext3 <1,2,3,4>, <3,4,u,1> 2559025254U, // <4,3,5,0>: Cost 3 vext1 <1,4,3,5>, LHS @@ -3231,7 +3231,7 @@ 2570971548U, // <4,3,5,3>: Cost 3 vext1 <3,4,3,5>, <3,3,3,3> 2559028534U, // <4,3,5,4>: Cost 3 vext1 <1,4,3,5>, RHS 4163519477U, // <4,3,5,5>: Cost 4 vtrnr <0,4,1,5>, <1,3,4,5> - 3987131000U, // <4,3,5,6>: Cost 4 vzipl RHS, <3,6,0,7> + 3309390346U, // <4,3,5,6>: Cost 4 vrev <3,4,6,5> 2706139747U, // <4,3,5,7>: Cost 3 vext3 <3,5,7,4>, <3,5,7,4> 2559031086U, // <4,3,5,u>: Cost 3 vext1 <1,4,3,5>, LHS 2559033446U, // <4,3,6,0>: Cost 3 vext1 <1,4,3,6>, LHS @@ -3239,28 +3239,28 @@ 2565007127U, // <4,3,6,2>: Cost 3 vext1 <2,4,3,6>, <2,4,3,6> 2570979740U, // <4,3,6,3>: Cost 3 vext1 <3,4,3,6>, <3,3,3,3> 2559036726U, // <4,3,6,4>: Cost 3 vext1 <1,4,3,6>, RHS - 3047606786U, // <4,3,6,5>: Cost 3 vtrnl RHS, <3,4,5,6> + 1161841154U, // <4,3,6,5>: Cost 2 vrev <3,4,5,6> 4028203932U, // <4,3,6,6>: Cost 4 vzipr <0,2,4,6>, <1,2,3,6> 2706803380U, // <4,3,6,7>: Cost 3 vext3 <3,6,7,4>, <3,6,7,4> - 2559039278U, // <4,3,6,u>: Cost 3 vext1 <1,4,3,6>, LHS + 1162062365U, // <4,3,6,u>: Cost 2 vrev <3,4,u,6> 3769633475U, // <4,3,7,0>: Cost 4 vext3 <1,u,3,4>, <3,7,0,1> - 2225464623U, // <4,3,7,1>: Cost 3 vrev <1,7,3,4> - 2231437320U, // <4,3,7,2>: Cost 3 vrev <2,7,3,4> + 3769633488U, // <4,3,7,1>: Cost 4 vext3 <1,u,3,4>, <3,7,1,5> + 3638757144U, // <4,3,7,2>: Cost 4 vext1 <2,4,3,7>, <2,4,3,7> 3769633508U, // <4,3,7,3>: Cost 4 vext3 <1,u,3,4>, <3,7,3,7> 3769633515U, // <4,3,7,4>: Cost 4 vext3 <1,u,3,4>, <3,7,4,5> 3769633526U, // <4,3,7,5>: Cost 4 vext3 <1,u,3,4>, <3,7,5,7> - 2255328108U, // <4,3,7,6>: Cost 3 vrev <6,7,3,4> + 3662647932U, // <4,3,7,6>: Cost 4 vext1 <6,4,3,7>, <6,4,3,7> 3781208837U, // <4,3,7,7>: Cost 4 vext3 <3,7,7,4>, <3,7,7,4> - 2267273502U, // <4,3,7,u>: Cost 3 vrev + 3769633547U, // <4,3,7,u>: Cost 4 vext3 <1,u,3,4>, <3,7,u,1> 2559049830U, // <4,3,u,0>: Cost 3 vext1 <1,4,3,u>, LHS - 1152386432U, // <4,3,u,1>: Cost 2 vrev <1,u,3,4> + 2691910430U, // <4,3,u,1>: Cost 3 vext3 <1,2,3,4>, <3,u,1,2> 2565023513U, // <4,3,u,2>: Cost 3 vext1 <2,4,3,u>, <2,4,3,u> - 2238073650U, // <4,3,u,3>: Cost 3 vrev <3,u,3,4> + 2707835698U, // <4,3,u,3>: Cost 3 vext3 <3,u,3,4>, <3,u,3,4> 2559053110U, // <4,3,u,4>: Cost 3 vext1 <1,4,3,u>, RHS - 2691910470U, // <4,3,u,5>: Cost 3 vext3 <1,2,3,4>, <3,u,5,6> - 2255991741U, // <4,3,u,6>: Cost 3 vrev <6,u,3,4> + 1161857540U, // <4,3,u,5>: Cost 2 vrev <3,4,5,u> + 2235673101U, // <4,3,u,6>: Cost 3 vrev <3,4,6,u> 2708130646U, // <4,3,u,7>: Cost 3 vext3 <3,u,7,4>, <3,u,7,4> - 1194195311U, // <4,3,u,u>: Cost 2 vrev + 1162078751U, // <4,3,u,u>: Cost 2 vrev <3,4,u,u> 2617573416U, // <4,4,0,0>: Cost 3 vext2 <0,0,4,4>, <0,0,4,4> 1570373734U, // <4,4,0,1>: Cost 2 vext2 <4,4,4,4>, LHS 2779676774U, // <4,4,0,2>: Cost 3 vuzpl <4,6,4,6>, LHS @@ -3268,9 +3268,9 @@ 2576977100U, // <4,4,0,4>: Cost 3 vext1 <4,4,4,0>, <4,4,4,0> 2718747538U, // <4,4,0,5>: Cost 3 vext3 <5,6,7,4>, <4,0,5,1> 2718747548U, // <4,4,0,6>: Cost 3 vext3 <5,6,7,4>, <4,0,6,2> - 3798608809U, // <4,4,0,7>: Cost 4 vext3 <6,7,0,4>, <4,0,7,6> + 3668637015U, // <4,4,0,7>: Cost 4 vext1 <7,4,4,0>, <7,4,4,0> 1570374301U, // <4,4,0,u>: Cost 2 vext2 <4,4,4,4>, LHS - 3626836070U, // <4,4,1,0>: Cost 4 vext1 <0,4,4,1>, LHS + 2644116214U, // <4,4,1,0>: Cost 3 vext2 <4,4,4,4>, <1,0,3,2> 2644116276U, // <4,4,1,1>: Cost 3 vext2 <4,4,4,4>, <1,1,1,1> 2691910602U, // <4,4,1,2>: Cost 3 vext3 <1,2,3,4>, <4,1,2,3> 2644116440U, // <4,4,1,3>: Cost 3 vext2 <4,4,4,4>, <1,3,1,3> @@ -3280,7 +3280,7 @@ 3768970231U, // <4,4,1,7>: Cost 4 vext3 <1,7,3,4>, <4,1,7,3> 2695891968U, // <4,4,1,u>: Cost 3 vext3 <1,u,3,4>, <4,1,u,3> 3703260634U, // <4,4,2,0>: Cost 4 vext2 <2,0,4,4>, <2,0,4,4> - 3705251370U, // <4,4,2,1>: Cost 4 vext2 <2,3,4,4>, <2,1,4,3> + 3765652499U, // <4,4,2,1>: Cost 4 vext3 <1,2,3,4>, <4,2,1,4> 2644117096U, // <4,4,2,2>: Cost 3 vext2 <4,4,4,4>, <2,2,2,2> 2631509709U, // <4,4,2,3>: Cost 3 vext2 <2,3,4,4>, <2,3,4,4> 2644117269U, // <4,4,2,4>: Cost 3 vext2 <4,4,4,4>, <2,4,3,4> @@ -3290,21 +3290,21 @@ 2634827874U, // <4,4,2,u>: Cost 3 vext2 <2,u,4,4>, <2,u,4,4> 2644117654U, // <4,4,3,0>: Cost 3 vext2 <4,4,4,4>, <3,0,1,2> 3638797210U, // <4,4,3,1>: Cost 4 vext1 <2,4,4,3>, <1,2,3,4> - 2691910762U, // <4,4,3,2>: Cost 3 vext3 <1,2,3,4>, <4,3,2,1> + 3638798082U, // <4,4,3,2>: Cost 4 vext1 <2,4,4,3>, <2,4,1,3> 2637482406U, // <4,4,3,3>: Cost 3 vext2 <3,3,4,4>, <3,3,4,4> 2638146039U, // <4,4,3,4>: Cost 3 vext2 <3,4,4,4>, <3,4,4,4> 3913287374U, // <4,4,3,5>: Cost 4 vuzpr <3,4,5,4>, <2,3,4,5> 3765652625U, // <4,4,3,6>: Cost 4 vext3 <1,2,3,4>, <4,3,6,4> - 3798830236U, // <4,4,3,7>: Cost 4 vext3 <6,7,3,4>, <4,3,7,6> - 2695892128U, // <4,4,3,u>: Cost 3 vext3 <1,u,3,4>, <4,3,u,1> + 3713878762U, // <4,4,3,7>: Cost 4 vext2 <3,7,4,4>, <3,7,4,4> + 2637482406U, // <4,4,3,u>: Cost 3 vext2 <3,3,4,4>, <3,3,4,4> 1503264870U, // <4,4,4,0>: Cost 2 vext1 <4,4,4,4>, LHS 2577007514U, // <4,4,4,1>: Cost 3 vext1 <4,4,4,4>, <1,2,3,4> 2577008232U, // <4,4,4,2>: Cost 3 vext1 <4,4,4,4>, <2,2,2,2> - 2235492855U, // <4,4,4,3>: Cost 3 vrev <3,4,4,4> + 2571037175U, // <4,4,4,3>: Cost 3 vext1 <3,4,4,4>, <3,4,4,4> 161926454U, // <4,4,4,4>: Cost 1 vdup0 RHS 1570377014U, // <4,4,4,5>: Cost 2 vext2 <4,4,4,4>, RHS 2779680054U, // <4,4,4,6>: Cost 3 vuzpl <4,6,4,6>, RHS - 2259383643U, // <4,4,4,7>: Cost 3 vrev <7,4,4,4> + 2594927963U, // <4,4,4,7>: Cost 3 vext1 <7,4,4,4>, <7,4,4,4> 161926454U, // <4,4,4,u>: Cost 1 vdup0 RHS 2571042918U, // <4,4,5,0>: Cost 3 vext1 <3,4,4,5>, LHS 2571043738U, // <4,4,5,1>: Cost 3 vext1 <3,4,4,5>, <1,2,3,4> @@ -3316,26 +3316,26 @@ 2594936156U, // <4,4,5,7>: Cost 3 vext1 <7,4,4,5>, <7,4,4,5> 1618169160U, // <4,4,5,u>: Cost 2 vext3 <1,2,3,4>, RHS 2553135206U, // <4,4,6,0>: Cost 3 vext1 <0,4,4,6>, LHS - 3626877748U, // <4,4,6,1>: Cost 4 vext1 <0,4,4,6>, <1,1,1,1> + 3626877686U, // <4,4,6,1>: Cost 4 vext1 <0,4,4,6>, <1,0,3,2> 2565080782U, // <4,4,6,2>: Cost 3 vext1 <2,4,4,6>, <2,3,4,5> 2571053561U, // <4,4,6,3>: Cost 3 vext1 <3,4,4,6>, <3,4,4,6> 2553138486U, // <4,4,6,4>: Cost 3 vext1 <0,4,4,6>, RHS - 3047607186U, // <4,4,6,5>: Cost 3 vtrnl RHS, <4,0,5,1> + 2241555675U, // <4,4,6,5>: Cost 3 vrev <4,4,5,6> 1973865782U, // <4,4,6,6>: Cost 2 vtrnl RHS, RHS 2658055029U, // <4,4,6,7>: Cost 3 vext2 <6,7,4,4>, <6,7,4,4> 1973865800U, // <4,4,6,u>: Cost 2 vtrnl RHS, RHS 2644120570U, // <4,4,7,0>: Cost 3 vext2 <4,4,4,4>, <7,0,1,2> 3638829978U, // <4,4,7,1>: Cost 4 vext1 <2,4,4,7>, <1,2,3,4> 3638830881U, // <4,4,7,2>: Cost 4 vext1 <2,4,4,7>, <2,4,4,7> - 3790499259U, // <4,4,7,3>: Cost 4 vext3 <5,3,7,4>, <4,7,3,5> + 3735115018U, // <4,4,7,3>: Cost 4 vext2 <7,3,4,4>, <7,3,4,4> 2662036827U, // <4,4,7,4>: Cost 3 vext2 <7,4,4,4>, <7,4,4,4> 2713292236U, // <4,4,7,5>: Cost 3 vext3 <4,7,5,4>, <4,7,5,4> - 2718748118U, // <4,4,7,6>: Cost 3 vext3 <5,6,7,4>, <4,7,6,5> + 2713365973U, // <4,4,7,6>: Cost 3 vext3 <4,7,6,4>, <4,7,6,4> 2644121196U, // <4,4,7,7>: Cost 3 vext2 <4,4,4,4>, <7,7,7,7> - 2720075240U, // <4,4,7,u>: Cost 3 vext3 <5,u,7,4>, <4,7,u,5> + 2662036827U, // <4,4,7,u>: Cost 3 vext2 <7,4,4,4>, <7,4,4,4> 1503297638U, // <4,4,u,0>: Cost 2 vext1 <4,4,4,u>, LHS 1570379566U, // <4,4,u,1>: Cost 2 vext2 <4,4,4,4>, LHS - 2692279807U, // <4,4,u,2>: Cost 3 vext3 <1,2,u,4>, <4,u,2,1> + 2779682606U, // <4,4,u,2>: Cost 3 vuzpl <4,6,4,6>, LHS 2571069947U, // <4,4,u,3>: Cost 3 vext1 <3,4,4,u>, <3,4,4,u> 161926454U, // <4,4,u,4>: Cost 1 vdup0 RHS 1841638710U, // <4,4,u,5>: Cost 2 vzipl RHS, RHS @@ -3347,21 +3347,21 @@ 2618908875U, // <4,5,0,2>: Cost 3 vext2 <0,2,4,5>, <0,2,4,5> 2571078140U, // <4,5,0,3>: Cost 3 vext1 <3,4,5,0>, <3,4,5,0> 2626871634U, // <4,5,0,4>: Cost 3 vext2 <1,5,4,5>, <0,4,1,5> - 3644821246U, // <4,5,0,5>: Cost 4 vext1 <3,4,5,0>, <5,2,3,4> + 3705258414U, // <4,5,0,5>: Cost 4 vext2 <2,3,4,5>, <0,5,2,7> 2594968438U, // <4,5,0,6>: Cost 3 vext1 <7,4,5,0>, <6,7,4,5> 2594968928U, // <4,5,0,7>: Cost 3 vext1 <7,4,5,0>, <7,4,5,0> 1557775005U, // <4,5,0,u>: Cost 2 vext2 <2,3,4,5>, LHS - 2623554306U, // <4,5,1,0>: Cost 3 vext2 <1,0,4,5>, <1,0,4,5> + 2631516918U, // <4,5,1,0>: Cost 3 vext2 <2,3,4,5>, <1,0,3,2> 2624217939U, // <4,5,1,1>: Cost 3 vext2 <1,1,4,5>, <1,1,4,5> 2631517078U, // <4,5,1,2>: Cost 3 vext2 <2,3,4,5>, <1,2,3,0> 2821341286U, // <4,5,1,3>: Cost 3 vuzpr <0,4,1,5>, LHS - 2239548390U, // <4,5,1,4>: Cost 3 vrev <4,1,5,4> + 3895086054U, // <4,5,1,4>: Cost 4 vuzpr <0,4,1,5>, <4,1,5,4> 2626872471U, // <4,5,1,5>: Cost 3 vext2 <1,5,4,5>, <1,5,4,5> 3895083131U, // <4,5,1,6>: Cost 4 vuzpr <0,4,1,5>, <0,1,4,6> 2718748368U, // <4,5,1,7>: Cost 3 vext3 <5,6,7,4>, <5,1,7,3> 2821341291U, // <4,5,1,u>: Cost 3 vuzpr <0,4,1,5>, LHS 2571092070U, // <4,5,2,0>: Cost 3 vext1 <3,4,5,2>, LHS - 3296035756U, // <4,5,2,1>: Cost 4 vrev <1,2,5,4> + 3699287585U, // <4,5,2,1>: Cost 4 vext2 <1,3,4,5>, <2,1,3,3> 2630854269U, // <4,5,2,2>: Cost 3 vext2 <2,2,4,5>, <2,2,4,5> 1557776078U, // <4,5,2,3>: Cost 2 vext2 <2,3,4,5>, <2,3,4,5> 2631517974U, // <4,5,2,4>: Cost 3 vext2 <2,3,4,5>, <2,4,3,5> @@ -3371,21 +3371,21 @@ 1561094243U, // <4,5,2,u>: Cost 2 vext2 <2,u,4,5>, <2,u,4,5> 2631518358U, // <4,5,3,0>: Cost 3 vext2 <2,3,4,5>, <3,0,1,2> 3895084710U, // <4,5,3,1>: Cost 4 vuzpr <0,4,1,5>, <2,3,0,1> - 2631518518U, // <4,5,3,2>: Cost 3 vext2 <2,3,4,5>, <3,2,1,0> + 2631518540U, // <4,5,3,2>: Cost 3 vext2 <2,3,4,5>, <3,2,3,4> 2631518620U, // <4,5,3,3>: Cost 3 vext2 <2,3,4,5>, <3,3,3,3> 2631518716U, // <4,5,3,4>: Cost 3 vext2 <2,3,4,5>, <3,4,5,0> 2631518784U, // <4,5,3,5>: Cost 3 vext2 <2,3,4,5>, <3,5,3,5> 2658060980U, // <4,5,3,6>: Cost 3 vext2 <6,7,4,5>, <3,6,7,4> 2640145131U, // <4,5,3,7>: Cost 3 vext2 <3,7,4,5>, <3,7,4,5> - 2631519004U, // <4,5,3,u>: Cost 3 vext2 <2,3,4,5>, <3,u,1,0> + 2631519006U, // <4,5,3,u>: Cost 3 vext2 <2,3,4,5>, <3,u,1,2> 2571108454U, // <4,5,4,0>: Cost 3 vext1 <3,4,5,4>, LHS - 3297363022U, // <4,5,4,1>: Cost 4 vrev <1,4,5,4> + 3632907342U, // <4,5,4,1>: Cost 4 vext1 <1,4,5,4>, <1,4,5,4> 2571110094U, // <4,5,4,2>: Cost 3 vext1 <3,4,5,4>, <2,3,4,5> - 2235566592U, // <4,5,4,3>: Cost 3 vrev <3,4,5,4> + 2571110912U, // <4,5,4,3>: Cost 3 vext1 <3,4,5,4>, <3,4,5,4> 2571111734U, // <4,5,4,4>: Cost 3 vext1 <3,4,5,4>, RHS 1557777718U, // <4,5,4,5>: Cost 2 vext2 <2,3,4,5>, RHS 2645454195U, // <4,5,4,6>: Cost 3 vext2 <4,6,4,5>, <4,6,4,5> - 2259457380U, // <4,5,4,7>: Cost 3 vrev <7,4,5,4> + 2718748614U, // <4,5,4,7>: Cost 3 vext3 <5,6,7,4>, <5,4,7,6> 1557777961U, // <4,5,4,u>: Cost 2 vext2 <2,3,4,5>, RHS 1503346790U, // <4,5,5,0>: Cost 2 vext1 <4,4,5,5>, LHS 2913398480U, // <4,5,5,1>: Cost 3 vzipl RHS, <5,1,7,3> @@ -3402,7 +3402,7 @@ 1497385474U, // <4,5,6,3>: Cost 2 vext1 <3,4,5,6>, <3,4,5,6> 1497386294U, // <4,5,6,4>: Cost 2 vext1 <3,4,5,6>, RHS 3047608324U, // <4,5,6,5>: Cost 3 vtrnl RHS, <5,5,5,5> - 2571129554U, // <4,5,6,6>: Cost 3 vext1 <3,4,5,6>, <6,5,4,3> + 2571129656U, // <4,5,6,6>: Cost 3 vext1 <3,4,5,6>, <6,6,6,6> 27705344U, // <4,5,6,7>: Cost 0 copy RHS 27705344U, // <4,5,6,u>: Cost 0 copy RHS 2565161062U, // <4,5,7,0>: Cost 3 vext1 <2,4,5,7>, LHS @@ -3416,7 +3416,7 @@ 2565166894U, // <4,5,7,u>: Cost 3 vext1 <2,4,5,7>, LHS 1497399398U, // <4,5,u,0>: Cost 2 vext1 <3,4,5,u>, LHS 1557780270U, // <4,5,u,1>: Cost 2 vext2 <2,3,4,5>, LHS - 2631522163U, // <4,5,u,2>: Cost 3 vext2 <2,3,4,5>, + 2631522181U, // <4,5,u,2>: Cost 3 vext2 <2,3,4,5>, 1497401860U, // <4,5,u,3>: Cost 2 vext1 <3,4,5,u>, <3,4,5,u> 1497402678U, // <4,5,u,4>: Cost 2 vext1 <3,4,5,u>, RHS 1557780634U, // <4,5,u,5>: Cost 2 vext2 <2,3,4,5>, RHS @@ -3428,11 +3428,11 @@ 1545175244U, // <4,6,0,2>: Cost 2 vext2 <0,2,4,6>, <0,2,4,6> 3692658940U, // <4,6,0,3>: Cost 4 vext2 <0,2,4,6>, <0,3,1,0> 2618917202U, // <4,6,0,4>: Cost 3 vext2 <0,2,4,6>, <0,4,1,5> - 3709911470U, // <4,6,0,5>: Cost 4 vext2 <3,1,4,6>, <0,5,2,7> - 2589069968U, // <4,6,0,6>: Cost 3 vext1 <6,4,6,0>, <6,4,6,0> + 3852910806U, // <4,6,0,5>: Cost 4 vuzpl RHS, <0,2,5,7> + 2253525648U, // <4,6,0,6>: Cost 3 vrev <6,4,6,0> 4040764726U, // <4,6,0,7>: Cost 4 vzipr <2,3,4,0>, RHS 1545175709U, // <4,6,0,u>: Cost 2 vext2 <0,2,4,6>, LHS - 3692659444U, // <4,6,1,0>: Cost 4 vext2 <0,2,4,6>, <1,0,3,0> + 2618917622U, // <4,6,1,0>: Cost 3 vext2 <0,2,4,6>, <1,0,3,2> 2618917684U, // <4,6,1,1>: Cost 3 vext2 <0,2,4,6>, <1,1,1,1> 2618917782U, // <4,6,1,2>: Cost 3 vext2 <0,2,4,6>, <1,2,3,0> 2618917848U, // <4,6,1,3>: Cost 3 vext2 <0,2,4,6>, <1,3,1,3> @@ -3441,7 +3441,7 @@ 3692659937U, // <4,6,1,6>: Cost 4 vext2 <0,2,4,6>, <1,6,3,7> 4032146742U, // <4,6,1,7>: Cost 4 vzipr <0,u,4,1>, RHS 2618918253U, // <4,6,1,u>: Cost 3 vext2 <0,2,4,6>, <1,u,1,3> - 2779170470U, // <4,6,2,0>: Cost 3 vuzpl RHS, <2,3,0,1> + 2618918380U, // <4,6,2,0>: Cost 3 vext2 <0,2,4,6>, <2,0,6,4> 2618918460U, // <4,6,2,1>: Cost 3 vext2 <0,2,4,6>, <2,1,6,3> 2618918504U, // <4,6,2,2>: Cost 3 vext2 <0,2,4,6>, <2,2,2,2> 2618918566U, // <4,6,2,3>: Cost 3 vext2 <0,2,4,6>, <2,3,0,1> @@ -3452,37 +3452,37 @@ 2618918971U, // <4,6,2,u>: Cost 3 vext2 <0,2,4,6>, <2,u,0,1> 2618919062U, // <4,6,3,0>: Cost 3 vext2 <0,2,4,6>, <3,0,1,2> 2636171526U, // <4,6,3,1>: Cost 3 vext2 <3,1,4,6>, <3,1,4,6> - 2618919222U, // <4,6,3,2>: Cost 3 vext2 <0,2,4,6>, <3,2,1,0> + 3692661057U, // <4,6,3,2>: Cost 4 vext2 <0,2,4,6>, <3,2,2,2> 2618919324U, // <4,6,3,3>: Cost 3 vext2 <0,2,4,6>, <3,3,3,3> 2618919426U, // <4,6,3,4>: Cost 3 vext2 <0,2,4,6>, <3,4,5,6> 2638826058U, // <4,6,3,5>: Cost 3 vext2 <3,5,4,6>, <3,5,4,6> 3913303030U, // <4,6,3,6>: Cost 4 vuzpr <3,4,5,6>, <1,3,4,6> 2722730572U, // <4,6,3,7>: Cost 3 vext3 <6,3,7,4>, <6,3,7,4> - 2618919708U, // <4,6,3,u>: Cost 3 vext2 <0,2,4,6>, <3,u,1,0> + 2618919710U, // <4,6,3,u>: Cost 3 vext2 <0,2,4,6>, <3,u,1,2> 2565210214U, // <4,6,4,0>: Cost 3 vext1 <2,4,6,4>, LHS 2718749286U, // <4,6,4,1>: Cost 3 vext3 <5,6,7,4>, <6,4,1,3> - 2229667632U, // <4,6,4,2>: Cost 3 vrev <2,4,6,4> - 2235640329U, // <4,6,4,3>: Cost 3 vrev <3,4,6,4> + 2565211952U, // <4,6,4,2>: Cost 3 vext1 <2,4,6,4>, <2,4,6,4> + 2571184649U, // <4,6,4,3>: Cost 3 vext1 <3,4,6,4>, <3,4,6,4> 2565213494U, // <4,6,4,4>: Cost 3 vext1 <2,4,6,4>, RHS 1545178422U, // <4,6,4,5>: Cost 2 vext2 <0,2,4,6>, RHS 1705430326U, // <4,6,4,6>: Cost 2 vuzpl RHS, RHS - 2259531117U, // <4,6,4,7>: Cost 3 vrev <7,4,6,4> + 2595075437U, // <4,6,4,7>: Cost 3 vext1 <7,4,6,4>, <7,4,6,4> 1545178665U, // <4,6,4,u>: Cost 2 vext2 <0,2,4,6>, RHS 2565218406U, // <4,6,5,0>: Cost 3 vext1 <2,4,6,5>, LHS 2645462736U, // <4,6,5,1>: Cost 3 vext2 <4,6,4,6>, <5,1,7,3> 2913399290U, // <4,6,5,2>: Cost 3 vzipl RHS, <6,2,7,3> 3913305394U, // <4,6,5,3>: Cost 4 vuzpr <3,4,5,6>, <4,5,6,3> - 2242276659U, // <4,6,5,4>: Cost 3 vrev <4,5,6,4> + 2645462982U, // <4,6,5,4>: Cost 3 vext2 <4,6,4,6>, <5,4,7,6> 2779172868U, // <4,6,5,5>: Cost 3 vuzpl RHS, <5,5,5,5> 2913391416U, // <4,6,5,6>: Cost 3 vzipl RHS, <6,6,6,6> 2821426486U, // <4,6,5,7>: Cost 3 vuzpr <0,4,2,6>, RHS 2821426487U, // <4,6,5,u>: Cost 3 vuzpr <0,4,2,6>, RHS 1503428710U, // <4,6,6,0>: Cost 2 vext1 <4,4,6,6>, LHS - 2577171252U, // <4,6,6,1>: Cost 3 vext1 <4,4,6,6>, <1,1,1,1> + 2577171190U, // <4,6,6,1>: Cost 3 vext1 <4,4,6,6>, <1,0,3,2> 2645463546U, // <4,6,6,2>: Cost 3 vext2 <4,6,4,6>, <6,2,7,3> 2577172630U, // <4,6,6,3>: Cost 3 vext1 <4,4,6,6>, <3,0,1,2> 1503431908U, // <4,6,6,4>: Cost 2 vext1 <4,4,6,6>, <4,4,6,6> - 2577174224U, // <4,6,6,5>: Cost 3 vext1 <4,4,6,6>, <5,1,7,3> + 2253501069U, // <4,6,6,5>: Cost 3 vrev <6,4,5,6> 2618921784U, // <4,6,6,6>: Cost 3 vext2 <0,2,4,6>, <6,6,6,6> 2954464566U, // <4,6,6,7>: Cost 3 vzipr <0,2,4,6>, RHS 1503434542U, // <4,6,6,u>: Cost 2 vext1 <4,4,6,6>, LHS @@ -3492,7 +3492,7 @@ 2725090156U, // <4,6,7,3>: Cost 3 vext3 <6,7,3,4>, <6,7,3,4> 2645464422U, // <4,6,7,4>: Cost 3 vext2 <4,6,4,6>, <7,4,5,6> 2779174246U, // <4,6,7,5>: Cost 3 vuzpl RHS, <7,4,5,6> - 2645464582U, // <4,6,7,6>: Cost 3 vext2 <4,6,4,6>, <7,6,5,4> + 3852915914U, // <4,6,7,6>: Cost 4 vuzpl RHS, <7,2,6,3> 2779174508U, // <4,6,7,7>: Cost 3 vuzpl RHS, <7,7,7,7> 2779173945U, // <4,6,7,u>: Cost 3 vuzpl RHS, <7,0,u,2> 1503445094U, // <4,6,u,0>: Cost 2 vext1 <4,4,6,u>, LHS @@ -3509,11 +3509,11 @@ 2726343685U, // <4,7,0,2>: Cost 3 vext3 <7,0,2,4>, <7,0,2,4> 3701293312U, // <4,7,0,3>: Cost 4 vext2 <1,6,4,7>, <0,3,1,4> 3706601810U, // <4,7,0,4>: Cost 4 vext2 <2,5,4,7>, <0,4,1,5> - 3318746752U, // <4,7,0,5>: Cost 4 vrev <5,0,7,4> + 2259424608U, // <4,7,0,5>: Cost 3 vrev <7,4,5,0> 3695321617U, // <4,7,0,6>: Cost 4 vext2 <0,6,4,7>, <0,6,4,7> - 3330692146U, // <4,7,0,7>: Cost 4 vrev <7,0,7,4> + 3800454194U, // <4,7,0,7>: Cost 4 vext3 <7,0,7,4>, <7,0,7,4> 2632860317U, // <4,7,0,u>: Cost 3 vext2 <2,5,4,7>, LHS - 3656917094U, // <4,7,1,0>: Cost 4 vext1 <5,4,7,1>, LHS + 2259064116U, // <4,7,1,0>: Cost 3 vrev <7,4,0,1> 3700630324U, // <4,7,1,1>: Cost 4 vext2 <1,5,4,7>, <1,1,1,1> 2632860570U, // <4,7,1,2>: Cost 3 vext2 <2,5,4,7>, <1,2,3,4> 3769635936U, // <4,7,1,3>: Cost 4 vext3 <1,u,3,4>, <7,1,3,5> @@ -3521,7 +3521,7 @@ 3700630681U, // <4,7,1,5>: Cost 4 vext2 <1,5,4,7>, <1,5,4,7> 3701294314U, // <4,7,1,6>: Cost 4 vext2 <1,6,4,7>, <1,6,4,7> 3793818754U, // <4,7,1,7>: Cost 4 vext3 <5,u,7,4>, <7,1,7,3> - 2632860570U, // <4,7,1,u>: Cost 3 vext2 <2,5,4,7>, <1,2,3,4> + 2259654012U, // <4,7,1,u>: Cost 3 vrev <7,4,u,1> 3656925286U, // <4,7,2,0>: Cost 4 vext1 <5,4,7,2>, LHS 3706603050U, // <4,7,2,1>: Cost 4 vext2 <2,5,4,7>, <2,1,4,3> 3706603112U, // <4,7,2,2>: Cost 4 vext2 <2,5,4,7>, <2,2,2,2> @@ -3532,103 +3532,103 @@ 3792491731U, // <4,7,2,7>: Cost 4 vext3 <5,6,7,4>, <7,2,7,3> 2634852453U, // <4,7,2,u>: Cost 3 vext2 <2,u,4,7>, <2,u,4,7> 3706603670U, // <4,7,3,0>: Cost 4 vext2 <2,5,4,7>, <3,0,1,2> - 3656934544U, // <4,7,3,1>: Cost 4 vext1 <5,4,7,3>, <1,5,3,7> - 2229077736U, // <4,7,3,2>: Cost 3 vrev <2,3,7,4> + 3662906266U, // <4,7,3,1>: Cost 4 vext1 <6,4,7,3>, <1,2,3,4> + 3725183326U, // <4,7,3,2>: Cost 4 vext2 <5,6,4,7>, <3,2,5,4> 3706603932U, // <4,7,3,3>: Cost 4 vext2 <2,5,4,7>, <3,3,3,3> 3701295618U, // <4,7,3,4>: Cost 4 vext2 <1,6,4,7>, <3,4,5,6> - 2246995827U, // <4,7,3,5>: Cost 3 vrev <5,3,7,4> + 2638834251U, // <4,7,3,5>: Cost 3 vext2 <3,5,4,7>, <3,5,4,7> 2639497884U, // <4,7,3,6>: Cost 3 vext2 <3,6,4,7>, <3,6,4,7> - 3332683045U, // <4,7,3,7>: Cost 4 vrev <7,3,7,4> + 3802445093U, // <4,7,3,7>: Cost 4 vext3 <7,3,7,4>, <7,3,7,4> 2640825150U, // <4,7,3,u>: Cost 3 vext2 <3,u,4,7>, <3,u,4,7> 2718750004U, // <4,7,4,0>: Cost 3 vext3 <5,6,7,4>, <7,4,0,1> 3706604490U, // <4,7,4,1>: Cost 4 vext2 <2,5,4,7>, <4,1,2,3> 3656943474U, // <4,7,4,2>: Cost 4 vext1 <5,4,7,4>, <2,5,4,7> - 3706604650U, // <4,7,4,3>: Cost 4 vext2 <2,5,4,7>, <4,3,2,1> - 2729145691U, // <4,7,4,4>: Cost 3 vext3 <7,4,4,4>, <7,4,4,4> + 3779884371U, // <4,7,4,3>: Cost 4 vext3 <3,5,7,4>, <7,4,3,5> + 2259383643U, // <4,7,4,4>: Cost 3 vrev <7,4,4,4> 2632863030U, // <4,7,4,5>: Cost 3 vext2 <2,5,4,7>, RHS - 2729293165U, // <4,7,4,6>: Cost 3 vext3 <7,4,6,4>, <7,4,6,4> + 2259531117U, // <4,7,4,6>: Cost 3 vrev <7,4,6,4> 3907340074U, // <4,7,4,7>: Cost 4 vuzpr <2,4,5,7>, <2,4,5,7> 2632863273U, // <4,7,4,u>: Cost 3 vext2 <2,5,4,7>, RHS 2913391610U, // <4,7,5,0>: Cost 3 vzipl RHS, <7,0,1,2> - 3298174129U, // <4,7,5,1>: Cost 4 vrev <1,5,7,4> + 3645006848U, // <4,7,5,1>: Cost 4 vext1 <3,4,7,5>, <1,3,5,7> 2589181646U, // <4,7,5,2>: Cost 3 vext1 <6,4,7,5>, <2,3,4,5> - 2236377699U, // <4,7,5,3>: Cost 3 vrev <3,5,7,4> + 3645008403U, // <4,7,5,3>: Cost 4 vext1 <3,4,7,5>, <3,4,7,5> 2913391974U, // <4,7,5,4>: Cost 3 vzipl RHS, <7,4,5,6> 2583211973U, // <4,7,5,5>: Cost 3 vext1 <5,4,7,5>, <5,4,7,5> - 2913392134U, // <4,7,5,6>: Cost 3 vzipl RHS, <7,6,5,4> + 2589184670U, // <4,7,5,6>: Cost 3 vext1 <6,4,7,5>, <6,4,7,5> 2913392236U, // <4,7,5,7>: Cost 3 vzipl RHS, <7,7,7,7> 2913392258U, // <4,7,5,u>: Cost 3 vzipl RHS, <7,u,1,2> - 2583216230U, // <4,7,6,0>: Cost 3 vext1 <5,4,7,6>, LHS + 1509474406U, // <4,7,6,0>: Cost 2 vext1 <5,4,7,6>, LHS 3047609338U, // <4,7,6,1>: Cost 3 vtrnl RHS, <7,0,1,2> - 4121351169U, // <4,7,6,2>: Cost 4 vtrnl RHS, <7,0,2,0> - 2237041332U, // <4,7,6,3>: Cost 3 vrev <3,6,7,4> - 2583219510U, // <4,7,6,4>: Cost 3 vext1 <5,4,7,6>, RHS - 1175244902U, // <4,7,6,5>: Cost 2 vrev <5,6,7,4> - 2589192863U, // <4,7,6,6>: Cost 3 vext1 <6,4,7,6>, <6,4,7,6> + 2583217768U, // <4,7,6,2>: Cost 3 vext1 <5,4,7,6>, <2,2,2,2> + 2583218326U, // <4,7,6,3>: Cost 3 vext1 <5,4,7,6>, <3,0,1,2> + 1509477686U, // <4,7,6,4>: Cost 2 vext1 <5,4,7,6>, RHS + 1509478342U, // <4,7,6,5>: Cost 2 vext1 <5,4,7,6>, <5,4,7,6> + 2583220730U, // <4,7,6,6>: Cost 3 vext1 <5,4,7,6>, <6,2,7,3> 3047609964U, // <4,7,6,7>: Cost 3 vtrnl RHS, <7,7,7,7> - 1657026081U, // <4,7,6,u>: Cost 2 vext3 <7,6,u,4>, <7,6,u,4> + 1509480238U, // <4,7,6,u>: Cost 2 vext1 <5,4,7,6>, LHS 3650994278U, // <4,7,7,0>: Cost 4 vext1 <4,4,7,7>, LHS 3650995098U, // <4,7,7,1>: Cost 4 vext1 <4,4,7,7>, <1,2,3,4> 3650996010U, // <4,7,7,2>: Cost 4 vext1 <4,4,7,7>, <2,4,5,7> - 3311446789U, // <4,7,7,3>: Cost 4 vrev <3,7,7,4> - 2668696936U, // <4,7,7,4>: Cost 3 vext2 , <7,4,5,u> - 2249650359U, // <4,7,7,5>: Cost 3 vrev <5,7,7,4> - 2255623056U, // <4,7,7,6>: Cost 3 vrev <6,7,7,4> + 3804804677U, // <4,7,7,3>: Cost 4 vext3 <7,7,3,4>, <7,7,3,4> + 3650997486U, // <4,7,7,4>: Cost 4 vext1 <4,4,7,7>, <4,4,7,7> + 2662725039U, // <4,7,7,5>: Cost 3 vext2 <7,5,4,7>, <7,5,4,7> + 3662942880U, // <4,7,7,6>: Cost 4 vext1 <6,4,7,7>, <6,4,7,7> 2718750316U, // <4,7,7,7>: Cost 3 vext3 <5,6,7,4>, <7,7,7,7> 2664715938U, // <4,7,7,u>: Cost 3 vext2 <7,u,4,7>, <7,u,4,7> - 2915382266U, // <4,7,u,0>: Cost 3 vzipl RHS, <7,0,1,2> + 1509490790U, // <4,7,u,0>: Cost 2 vext1 <5,4,7,u>, LHS 2632865582U, // <4,7,u,1>: Cost 3 vext2 <2,5,4,7>, LHS - 2726343685U, // <4,7,u,2>: Cost 3 vext3 <7,0,2,4>, <7,0,2,4> - 2238368598U, // <4,7,u,3>: Cost 3 vrev <3,u,7,4> - 2915382630U, // <4,7,u,4>: Cost 3 vzipl RHS, <7,4,5,6> - 1176572168U, // <4,7,u,5>: Cost 2 vrev <5,u,7,4> - 2915382790U, // <4,7,u,6>: Cost 3 vzipl RHS, <7,6,5,4> + 2583234152U, // <4,7,u,2>: Cost 3 vext1 <5,4,7,u>, <2,2,2,2> + 2583234710U, // <4,7,u,3>: Cost 3 vext1 <5,4,7,u>, <3,0,1,2> + 1509494070U, // <4,7,u,4>: Cost 2 vext1 <5,4,7,u>, RHS + 1509494728U, // <4,7,u,5>: Cost 2 vext1 <5,4,7,u>, <5,4,7,u> + 2583237114U, // <4,7,u,6>: Cost 3 vext1 <5,4,7,u>, <6,2,7,3> 3047757420U, // <4,7,u,7>: Cost 3 vtrnl RHS, <7,7,7,7> - 1658353347U, // <4,7,u,u>: Cost 2 vext3 <7,u,u,4>, <7,u,u,4> + 1509496622U, // <4,7,u,u>: Cost 2 vext1 <5,4,7,u>, LHS 2618933248U, // <4,u,0,0>: Cost 3 vext2 <0,2,4,u>, <0,0,0,0> 1545191526U, // <4,u,0,1>: Cost 2 vext2 <0,2,4,u>, LHS 1545191630U, // <4,u,0,2>: Cost 2 vext2 <0,2,4,u>, <0,2,4,u> - 2233133271U, // <4,u,0,3>: Cost 3 vrev <3,0,u,4> + 2691913445U, // <4,u,0,3>: Cost 3 vext3 <1,2,3,4>, 2618933586U, // <4,u,0,4>: Cost 3 vext2 <0,2,4,u>, <0,4,1,5> - 2736518902U, // <4,u,0,5>: Cost 3 vext3 , - 2251051362U, // <4,u,0,6>: Cost 3 vrev <6,0,u,4> - 2257024059U, // <4,u,0,7>: Cost 3 vrev <7,0,u,4> + 2265397305U, // <4,u,0,5>: Cost 3 vrev + 2595189625U, // <4,u,0,6>: Cost 3 vext1 <7,4,u,0>, <6,7,4,u> + 2595190139U, // <4,u,0,7>: Cost 3 vext1 <7,4,u,0>, <7,4,u,0> 1545192093U, // <4,u,0,u>: Cost 2 vext2 <0,2,4,u>, LHS - 2571305062U, // <4,u,1,0>: Cost 3 vext1 <3,4,u,1>, LHS + 2618934006U, // <4,u,1,0>: Cost 3 vext2 <0,2,4,u>, <1,0,3,2> 2618934068U, // <4,u,1,1>: Cost 3 vext2 <0,2,4,u>, <1,1,1,1> 1618171694U, // <4,u,1,2>: Cost 2 vext3 <1,2,3,4>, LHS 2618934232U, // <4,u,1,3>: Cost 3 vext2 <0,2,4,u>, <1,3,1,3> - 2571308342U, // <4,u,1,4>: Cost 3 vext1 <3,4,u,1>, RHS + 2695894848U, // <4,u,1,4>: Cost 3 vext3 <1,u,3,4>, 2618934416U, // <4,u,1,5>: Cost 3 vext2 <0,2,4,u>, <1,5,3,7> 3692676321U, // <4,u,1,6>: Cost 4 vext2 <0,2,4,u>, <1,6,3,7> 2718750555U, // <4,u,1,7>: Cost 3 vext3 <5,6,7,4>, 1618171748U, // <4,u,1,u>: Cost 2 vext3 <1,2,3,4>, LHS 2553397350U, // <4,u,2,0>: Cost 3 vext1 <0,4,u,2>, LHS - 1148773319U, // <4,u,2,1>: Cost 2 vrev <1,2,u,4> + 2630215215U, // <4,u,2,1>: Cost 3 vext2 <2,1,4,u>, <2,1,4,u> 2618934888U, // <4,u,2,2>: Cost 3 vext2 <0,2,4,u>, <2,2,2,2> 1557800657U, // <4,u,2,3>: Cost 2 vext2 <2,3,4,u>, <2,3,4,u> 2618935065U, // <4,u,2,4>: Cost 3 vext2 <0,2,4,u>, <2,4,3,u> - 2246405931U, // <4,u,2,5>: Cost 3 vrev <5,2,u,4> + 2733864859U, // <4,u,2,5>: Cost 3 vext3 , 2618935226U, // <4,u,2,6>: Cost 3 vext2 <0,2,4,u>, <2,6,3,7> 2718750636U, // <4,u,2,7>: Cost 3 vext3 <5,6,7,4>, 1561118822U, // <4,u,2,u>: Cost 2 vext2 <2,u,4,u>, <2,u,4,u> 2618935446U, // <4,u,3,0>: Cost 3 vext2 <0,2,4,u>, <3,0,1,2> - 2223178776U, // <4,u,3,1>: Cost 3 vrev <1,3,u,4> - 2618935606U, // <4,u,3,2>: Cost 3 vext2 <0,2,4,u>, <3,2,1,0> + 2779318422U, // <4,u,3,1>: Cost 3 vuzpl RHS, <3,0,1,2> + 2636851545U, // <4,u,3,2>: Cost 3 vext2 <3,2,4,u>, <3,2,4,u> 2618935708U, // <4,u,3,3>: Cost 3 vext2 <0,2,4,u>, <3,3,3,3> 2618935810U, // <4,u,3,4>: Cost 3 vext2 <0,2,4,u>, <3,4,5,6> 2691913711U, // <4,u,3,5>: Cost 3 vext3 <1,2,3,4>, - 2253042261U, // <4,u,3,6>: Cost 3 vrev <6,3,u,4> + 2588725862U, // <4,u,3,6>: Cost 3 vext1 <6,4,1,3>, <6,4,1,3> 2640169710U, // <4,u,3,7>: Cost 3 vext2 <3,7,4,u>, <3,7,4,u> - 2618936092U, // <4,u,3,u>: Cost 3 vext2 <0,2,4,u>, <3,u,1,0> + 2618936094U, // <4,u,3,u>: Cost 3 vext2 <0,2,4,u>, <3,u,1,2> 1503559782U, // <4,u,4,0>: Cost 2 vext1 <4,4,u,4>, LHS 2692282391U, // <4,u,4,1>: Cost 3 vext3 <1,2,u,4>, - 2229815106U, // <4,u,4,2>: Cost 3 vrev <2,4,u,4> - 2235787803U, // <4,u,4,3>: Cost 3 vrev <3,4,u,4> + 2565359426U, // <4,u,4,2>: Cost 3 vext1 <2,4,u,4>, <2,4,u,4> + 2571332123U, // <4,u,4,3>: Cost 3 vext1 <3,4,u,4>, <3,4,u,4> 161926454U, // <4,u,4,4>: Cost 1 vdup0 RHS 1545194806U, // <4,u,4,5>: Cost 2 vext2 <0,2,4,u>, RHS 1705577782U, // <4,u,4,6>: Cost 2 vuzpl RHS, RHS - 2259678591U, // <4,u,4,7>: Cost 3 vrev <7,4,u,4> + 2718750801U, // <4,u,4,7>: Cost 3 vext3 <5,6,7,4>, 161926454U, // <4,u,4,u>: Cost 1 vdup0 RHS 1479164006U, // <4,u,5,0>: Cost 2 vext1 <0,4,1,5>, LHS 1839650606U, // <4,u,5,1>: Cost 2 vzipl RHS, LHS @@ -3640,11 +3640,11 @@ 3089780265U, // <4,u,5,7>: Cost 3 vtrnr <0,4,1,5>, RHS 1618172076U, // <4,u,5,u>: Cost 2 vext3 <1,2,3,4>, RHS 1479688294U, // <4,u,6,0>: Cost 2 vext1 <0,4,u,6>, LHS - 2553430836U, // <4,u,6,1>: Cost 3 vext1 <0,4,u,6>, <1,1,1,1> + 2553430774U, // <4,u,6,1>: Cost 3 vext1 <0,4,u,6>, <1,0,3,2> 1973868334U, // <4,u,6,2>: Cost 2 vtrnl RHS, LHS 1497606685U, // <4,u,6,3>: Cost 2 vext1 <3,4,u,6>, <3,4,u,6> 1479691574U, // <4,u,6,4>: Cost 2 vext1 <0,4,u,6>, RHS - 1175318639U, // <4,u,6,5>: Cost 2 vrev <5,6,u,4> + 1509552079U, // <4,u,6,5>: Cost 2 vext1 <5,4,u,6>, <5,4,u,6> 1973868698U, // <4,u,6,6>: Cost 2 vtrnl RHS, RHS 27705344U, // <4,u,6,7>: Cost 0 copy RHS 27705344U, // <4,u,6,u>: Cost 0 copy RHS @@ -3671,8 +3671,8 @@ 2687123476U, // <5,0,0,2>: Cost 3 vext3 <0,4,1,5>, <0,0,2,2> 3710599434U, // <5,0,0,3>: Cost 4 vext2 <3,2,5,0>, <0,3,2,5> 2642166098U, // <5,0,0,4>: Cost 3 vext2 <4,1,5,0>, <0,4,1,5> - 3711926716U, // <5,0,0,5>: Cost 4 vext2 <3,4,5,0>, <0,5,4,3> - 3695338003U, // <5,0,0,6>: Cost 4 vext2 <0,6,5,0>, <0,6,5,0> + 3657060306U, // <5,0,0,5>: Cost 4 vext1 <5,5,0,0>, <5,5,0,0> + 3292094923U, // <5,0,0,6>: Cost 4 vrev <0,5,6,0> 3669005700U, // <5,0,0,7>: Cost 4 vext1 <7,5,0,0>, <7,5,0,0> 2687123530U, // <5,0,0,u>: Cost 3 vext3 <0,4,1,5>, <0,0,u,2> 2559434854U, // <5,0,1,0>: Cost 3 vext1 <1,5,0,1>, LHS @@ -3698,24 +3698,24 @@ 2686533898U, // <5,0,3,2>: Cost 3 vext3 <0,3,2,5>, <0,3,2,5> 3760349459U, // <5,0,3,3>: Cost 4 vext3 <0,3,3,5>, <0,3,3,5> 2638187004U, // <5,0,3,4>: Cost 3 vext2 <3,4,5,0>, <3,4,5,0> - 3711928896U, // <5,0,3,5>: Cost 4 vext2 <3,4,5,0>, <3,5,3,5> + 3776348452U, // <5,0,3,5>: Cost 4 vext3 <3,0,4,5>, <0,3,5,4> 3713256094U, // <5,0,3,6>: Cost 4 vext2 <3,6,5,0>, <3,6,5,0> 3914064896U, // <5,0,3,7>: Cost 4 vuzpr <3,5,7,0>, <1,3,5,7> 2686976320U, // <5,0,3,u>: Cost 3 vext3 <0,3,u,5>, <0,3,u,5> 2559459430U, // <5,0,4,0>: Cost 3 vext1 <1,5,0,4>, LHS 1613381970U, // <5,0,4,1>: Cost 2 vext3 <0,4,1,5>, <0,4,1,5> 2687123804U, // <5,0,4,2>: Cost 3 vext3 <0,4,1,5>, <0,4,2,6> - 2235206100U, // <5,0,4,3>: Cost 3 vrev <3,4,0,5> + 3761013092U, // <5,0,4,3>: Cost 4 vext3 <0,4,3,5>, <0,4,3,5> 2559462710U, // <5,0,4,4>: Cost 3 vext1 <1,5,0,4>, RHS 2638187830U, // <5,0,4,5>: Cost 3 vext2 <3,4,5,0>, RHS 3761234303U, // <5,0,4,6>: Cost 4 vext3 <0,4,6,5>, <0,4,6,5> 2646150600U, // <5,0,4,7>: Cost 3 vext2 <4,7,5,0>, <4,7,5,0> 1613381970U, // <5,0,4,u>: Cost 2 vext3 <0,4,1,5>, <0,4,1,5> - 3778707862U, // <5,0,5,0>: Cost 4 vext3 <3,4,0,5>, <0,5,0,1> + 3766763926U, // <5,0,5,0>: Cost 4 vext3 <1,4,0,5>, <0,5,0,1> 2919268454U, // <5,0,5,1>: Cost 3 vzipl <5,5,5,5>, LHS 3053486182U, // <5,0,5,2>: Cost 3 vtrnl <5,5,5,5>, LHS - 3778707888U, // <5,0,5,3>: Cost 4 vext3 <3,4,0,5>, <0,5,3,0> - 3778707902U, // <5,0,5,4>: Cost 4 vext3 <3,4,0,5>, <0,5,4,5> + 3723210589U, // <5,0,5,3>: Cost 4 vext2 <5,3,5,0>, <5,3,5,0> + 3766763966U, // <5,0,5,4>: Cost 4 vext3 <1,4,0,5>, <0,5,4,5> 2650796031U, // <5,0,5,5>: Cost 3 vext2 <5,5,5,0>, <5,5,5,0> 3719893090U, // <5,0,5,6>: Cost 4 vext2 <4,7,5,0>, <5,6,7,0> 3914067254U, // <5,0,5,7>: Cost 4 vuzpr <3,5,7,0>, RHS @@ -3744,28 +3744,28 @@ 2689925800U, // <5,0,u,3>: Cost 3 vext3 <0,u,3,5>, <0,u,3,5> 2687124146U, // <5,0,u,4>: Cost 3 vext3 <0,4,1,5>, <0,u,4,6> 2638190746U, // <5,0,u,5>: Cost 3 vext2 <3,4,5,0>, RHS - 2255778723U, // <5,0,u,6>: Cost 3 vrev <6,u,0,5> + 2589356723U, // <5,0,u,6>: Cost 3 vext1 <6,5,0,u>, <6,5,0,u> 2595280230U, // <5,0,u,7>: Cost 3 vext1 <7,5,0,2>, <7,4,5,6> 1613382355U, // <5,0,u,u>: Cost 2 vext3 <0,4,1,5>, LHS 2646818816U, // <5,1,0,0>: Cost 3 vext2 <4,u,5,1>, <0,0,0,0> 1573077094U, // <5,1,0,1>: Cost 2 vext2 <4,u,5,1>, LHS 2646818980U, // <5,1,0,2>: Cost 3 vext2 <4,u,5,1>, <0,2,0,2> - 3760866036U, // <5,1,0,3>: Cost 4 vext3 <0,4,1,5>, <1,0,3,0> - 2646819154U, // <5,1,0,4>: Cost 3 vext2 <4,u,5,1>, <0,4,1,5> + 2687124214U, // <5,1,0,3>: Cost 3 vext3 <0,4,1,5>, <1,0,3,2> + 2641510738U, // <5,1,0,4>: Cost 3 vext2 <4,0,5,1>, <0,4,1,5> 2641510814U, // <5,1,0,5>: Cost 3 vext2 <4,0,5,1>, <0,5,1,0> 3720561142U, // <5,1,0,6>: Cost 4 vext2 <4,u,5,1>, <0,6,1,7> - 3798909726U, // <5,1,0,7>: Cost 4 vext3 <6,7,4,5>, <1,0,7,6> + 3298141357U, // <5,1,0,7>: Cost 4 vrev <1,5,7,0> 1573077661U, // <5,1,0,u>: Cost 2 vext2 <4,u,5,1>, LHS - 2553536614U, // <5,1,1,0>: Cost 3 vext1 <0,5,1,1>, LHS + 2223891567U, // <5,1,1,0>: Cost 3 vrev <1,5,0,1> 2687124276U, // <5,1,1,1>: Cost 3 vext3 <0,4,1,5>, <1,1,1,1> 2646819734U, // <5,1,1,2>: Cost 3 vext2 <4,u,5,1>, <1,2,3,0> 2687124296U, // <5,1,1,3>: Cost 3 vext3 <0,4,1,5>, <1,1,3,3> 2691326803U, // <5,1,1,4>: Cost 3 vext3 <1,1,4,5>, <1,1,4,5> 2691400540U, // <5,1,1,5>: Cost 3 vext3 <1,1,5,5>, <1,1,5,5> 3765216101U, // <5,1,1,6>: Cost 4 vext3 <1,1,6,5>, <1,1,6,5> - 3701982526U, // <5,1,1,7>: Cost 4 vext2 <1,7,5,1>, <1,7,5,1> + 3765289838U, // <5,1,1,7>: Cost 4 vext3 <1,1,7,5>, <1,1,7,5> 2687124341U, // <5,1,1,u>: Cost 3 vext3 <0,4,1,5>, <1,1,u,3> - 3289776304U, // <5,1,2,0>: Cost 4 vrev <0,2,1,5> + 3297641584U, // <5,1,2,0>: Cost 4 vrev <1,5,0,2> 3763520391U, // <5,1,2,1>: Cost 4 vext3 <0,u,1,5>, <1,2,1,3> 2646820456U, // <5,1,2,2>: Cost 3 vext2 <4,u,5,1>, <2,2,2,2> 2687124374U, // <5,1,2,3>: Cost 3 vext3 <0,4,1,5>, <1,2,3,0> @@ -3776,12 +3776,12 @@ 2687124419U, // <5,1,2,u>: Cost 3 vext3 <0,4,1,5>, <1,2,u,0> 2577440870U, // <5,1,3,0>: Cost 3 vext1 <4,5,1,3>, LHS 2687124440U, // <5,1,3,1>: Cost 3 vext3 <0,4,1,5>, <1,3,1,3> - 2228643507U, // <5,1,3,2>: Cost 3 vrev <2,3,1,5> + 3759686627U, // <5,1,3,2>: Cost 4 vext3 <0,2,3,5>, <1,3,2,5> 2692580332U, // <5,1,3,3>: Cost 3 vext3 <1,3,3,5>, <1,3,3,5> 2687124469U, // <5,1,3,4>: Cost 3 vext3 <0,4,1,5>, <1,3,4,5> 2685207552U, // <5,1,3,5>: Cost 3 vext3 <0,1,2,5>, <1,3,5,7> - 2595361654U, // <5,1,3,6>: Cost 3 vext1 <7,5,1,3>, <6,7,4,5> - 2595362192U, // <5,1,3,7>: Cost 3 vext1 <7,5,1,3>, <7,5,1,3> + 3760866313U, // <5,1,3,6>: Cost 4 vext3 <0,4,1,5>, <1,3,6,7> + 2692875280U, // <5,1,3,7>: Cost 3 vext3 <1,3,7,5>, <1,3,7,5> 2687124503U, // <5,1,3,u>: Cost 3 vext3 <0,4,1,5>, <1,3,u,3> 1567771538U, // <5,1,4,0>: Cost 2 vext2 <4,0,5,1>, <4,0,5,1> 2693096491U, // <5,1,4,1>: Cost 3 vext3 <1,4,1,5>, <1,4,1,5> @@ -3790,7 +3790,7 @@ 2646822096U, // <5,1,4,4>: Cost 3 vext2 <4,u,5,1>, <4,4,4,4> 1573080374U, // <5,1,4,5>: Cost 2 vext2 <4,u,5,1>, RHS 2646822260U, // <5,1,4,6>: Cost 3 vext2 <4,u,5,1>, <4,6,4,6> - 3720564168U, // <5,1,4,7>: Cost 4 vext2 <4,u,5,1>, <4,7,5,0> + 3298174129U, // <5,1,4,7>: Cost 4 vrev <1,5,7,4> 1573080602U, // <5,1,4,u>: Cost 2 vext2 <4,u,5,1>, <4,u,5,1> 2687124591U, // <5,1,5,0>: Cost 3 vext3 <0,4,1,5>, <1,5,0,1> 2646822543U, // <5,1,5,1>: Cost 3 vext2 <4,u,5,1>, <5,1,0,1> @@ -3816,7 +3816,7 @@ 2040971366U, // <5,1,7,3>: Cost 2 vtrnr RHS, LHS 2559561014U, // <5,1,7,4>: Cost 3 vext1 <1,5,1,7>, RHS 2595393232U, // <5,1,7,5>: Cost 3 vext1 <7,5,1,7>, <5,1,7,3> - 2646824454U, // <5,1,7,6>: Cost 3 vext2 <4,u,5,1>, <7,6,5,4> + 4188455035U, // <5,1,7,6>: Cost 4 vtrnr RHS, <0,1,4,6> 2646824556U, // <5,1,7,7>: Cost 3 vext2 <4,u,5,1>, <7,7,7,7> 2040971371U, // <5,1,7,u>: Cost 2 vtrnr RHS, LHS 1591662326U, // <5,1,u,0>: Cost 2 vext2 , @@ -3833,9 +3833,9 @@ 2641518756U, // <5,2,0,2>: Cost 3 vext2 <4,0,5,2>, <0,2,0,2> 3759760847U, // <5,2,0,3>: Cost 4 vext3 <0,2,4,5>, <2,0,3,2> 3760866775U, // <5,2,0,4>: Cost 4 vext3 <0,4,1,5>, <2,0,4,1> - 3766912486U, // <5,2,0,5>: Cost 4 vext3 <1,4,2,5>, <2,0,5,7> - 3775686121U, // <5,2,0,6>: Cost 4 vext3 <2,u,4,5>, <2,0,6,1> - 3330331654U, // <5,2,0,7>: Cost 4 vrev <7,0,2,5> + 3759539680U, // <5,2,0,5>: Cost 4 vext3 <0,2,1,5>, <2,0,5,1> + 3760866796U, // <5,2,0,6>: Cost 4 vext3 <0,4,1,5>, <2,0,6,4> + 3304114054U, // <5,2,0,7>: Cost 4 vrev <2,5,7,0> 2628911773U, // <5,2,0,u>: Cost 3 vext2 <1,u,5,2>, LHS 2623603464U, // <5,2,1,0>: Cost 3 vext2 <1,0,5,2>, <1,0,5,2> 3698008921U, // <5,2,1,1>: Cost 4 vext2 <1,1,5,2>, <1,1,5,2> @@ -3844,7 +3844,7 @@ 3633327414U, // <5,2,1,4>: Cost 4 vext1 <1,5,2,1>, RHS 3759539760U, // <5,2,1,5>: Cost 4 vext3 <0,2,1,5>, <2,1,5,0> 3760866876U, // <5,2,1,6>: Cost 4 vext3 <0,4,1,5>, <2,1,6,3> - 3330995287U, // <5,2,1,7>: Cost 4 vrev <7,1,2,5> + 3304122247U, // <5,2,1,7>: Cost 4 vrev <2,5,7,1> 2687125072U, // <5,2,1,u>: Cost 3 vext3 <0,4,1,5>, <2,1,u,5> 3633332326U, // <5,2,2,0>: Cost 4 vext1 <1,5,2,2>, LHS 3759760992U, // <5,2,2,1>: Cost 4 vext3 <0,2,4,5>, <2,2,1,3> @@ -3853,7 +3853,7 @@ 2697963133U, // <5,2,2,4>: Cost 3 vext3 <2,2,4,5>, <2,2,4,5> 3759466120U, // <5,2,2,5>: Cost 4 vext3 <0,2,0,5>, <2,2,5,7> 3760866960U, // <5,2,2,6>: Cost 4 vext3 <0,4,1,5>, <2,2,6,6> - 3331658920U, // <5,2,2,7>: Cost 4 vrev <7,2,2,5> + 3771926168U, // <5,2,2,7>: Cost 4 vext3 <2,2,7,5>, <2,2,7,5> 2687125151U, // <5,2,2,u>: Cost 3 vext3 <0,4,1,5>, <2,2,u,3> 2687125158U, // <5,2,3,0>: Cost 3 vext3 <0,4,1,5>, <2,3,0,1> 2698405555U, // <5,2,3,1>: Cost 3 vext3 <2,3,1,5>, <2,3,1,5> @@ -3865,13 +3865,13 @@ 3702655716U, // <5,2,3,7>: Cost 4 vext2 <1,u,5,2>, <3,7,3,7> 1625179890U, // <5,2,3,u>: Cost 2 vext3 <2,3,u,5>, <2,3,u,5> 2641521555U, // <5,2,4,0>: Cost 3 vext2 <4,0,5,2>, <4,0,5,2> - 3297150004U, // <5,2,4,1>: Cost 4 vrev <1,4,2,5> + 3772368642U, // <5,2,4,1>: Cost 4 vext3 <2,3,4,5>, <2,4,1,3> 2699142925U, // <5,2,4,2>: Cost 3 vext3 <2,4,2,5>, <2,4,2,5> 2698626838U, // <5,2,4,3>: Cost 3 vext3 <2,3,4,5>, <2,4,3,5> 2698626848U, // <5,2,4,4>: Cost 3 vext3 <2,3,4,5>, <2,4,4,6> 2628914486U, // <5,2,4,5>: Cost 3 vext2 <1,u,5,2>, RHS 2645503353U, // <5,2,4,6>: Cost 3 vext2 <4,6,5,2>, <4,6,5,2> - 3332986186U, // <5,2,4,7>: Cost 4 vrev <7,4,2,5> + 3304146826U, // <5,2,4,7>: Cost 4 vrev <2,5,7,4> 2628914729U, // <5,2,4,u>: Cost 3 vext2 <1,u,5,2>, RHS 2553643110U, // <5,2,5,0>: Cost 3 vext1 <0,5,2,5>, LHS 3758950227U, // <5,2,5,1>: Cost 4 vext3 <0,1,2,5>, <2,5,1,3> @@ -3892,7 +3892,7 @@ 3719246670U, // <5,2,6,7>: Cost 4 vext2 <4,6,5,2>, <6,7,0,1> 2687125479U, // <5,2,6,u>: Cost 3 vext3 <0,4,1,5>, <2,6,u,7> 2565603430U, // <5,2,7,0>: Cost 3 vext1 <2,5,2,7>, LHS - 3627402240U, // <5,2,7,1>: Cost 4 vext1 <0,5,2,7>, <1,3,5,7> + 2553660150U, // <5,2,7,1>: Cost 3 vext1 <0,5,2,7>, <1,0,3,2> 2565605216U, // <5,2,7,2>: Cost 3 vext1 <2,5,2,7>, <2,5,2,7> 2961178726U, // <5,2,7,3>: Cost 3 vzipr <1,3,5,7>, LHS 2565606710U, // <5,2,7,4>: Cost 3 vext1 <2,5,2,7>, RHS @@ -3907,38 +3907,38 @@ 1628203107U, // <5,2,u,4>: Cost 2 vext3 <2,u,4,5>, <2,u,4,5> 2628917402U, // <5,2,u,5>: Cost 3 vext2 <1,u,5,2>, RHS 2702092405U, // <5,2,u,6>: Cost 3 vext3 <2,u,6,5>, <2,u,6,5> - 4188463318U, // <5,2,u,7>: Cost 4 vtrnr RHS, <0,2,5,7> + 3304179598U, // <5,2,u,7>: Cost 4 vrev <2,5,7,u> 1628498055U, // <5,2,u,u>: Cost 2 vext3 <2,u,u,5>, <2,u,u,5> 3760867467U, // <5,3,0,0>: Cost 4 vext3 <0,4,1,5>, <3,0,0,0> 2687125654U, // <5,3,0,1>: Cost 3 vext3 <0,4,1,5>, <3,0,1,2> 3759761565U, // <5,3,0,2>: Cost 4 vext3 <0,2,4,5>, <3,0,2,0> 3633391766U, // <5,3,0,3>: Cost 4 vext1 <1,5,3,0>, <3,0,1,2> 2687125680U, // <5,3,0,4>: Cost 3 vext3 <0,4,1,5>, <3,0,4,1> - 3787704506U, // <5,3,0,5>: Cost 4 vext3 <4,u,5,5>, <3,0,5,2> - 3763742921U, // <5,3,0,6>: Cost 5 vext3 <0,u,4,5>, <3,0,6,u> - 4182500352U, // <5,3,0,7>: Cost 4 vtrnr <3,5,7,0>, <1,3,5,7> + 3760277690U, // <5,3,0,5>: Cost 4 vext3 <0,3,2,5>, <3,0,5,2> + 3310013014U, // <5,3,0,6>: Cost 4 vrev <3,5,6,0> + 2236344927U, // <5,3,0,7>: Cost 3 vrev <3,5,7,0> 2687125717U, // <5,3,0,u>: Cost 3 vext3 <0,4,1,5>, <3,0,u,2> - 2595487846U, // <5,3,1,0>: Cost 3 vext1 <7,5,3,1>, LHS - 2595488768U, // <5,3,1,1>: Cost 3 vext1 <7,5,3,1>, <1,3,5,7> + 3760867551U, // <5,3,1,0>: Cost 4 vext3 <0,4,1,5>, <3,1,0,3> + 3760867558U, // <5,3,1,1>: Cost 4 vext3 <0,4,1,5>, <3,1,1,1> 2624938923U, // <5,3,1,2>: Cost 3 vext2 <1,2,5,3>, <1,2,5,3> - 2233436412U, // <5,3,1,3>: Cost 3 vrev <3,1,3,5> - 2595491126U, // <5,3,1,4>: Cost 3 vext1 <7,5,3,1>, RHS + 2703198460U, // <5,3,1,3>: Cost 3 vext3 <3,1,3,5>, <3,1,3,5> + 3760867587U, // <5,3,1,4>: Cost 4 vext3 <0,4,1,5>, <3,1,4,3> 2636219536U, // <5,3,1,5>: Cost 3 vext2 <3,1,5,3>, <1,5,3,7> 3698681075U, // <5,3,1,6>: Cost 4 vext2 <1,2,5,3>, <1,6,5,7> - 2257327200U, // <5,3,1,7>: Cost 3 vrev <7,1,3,5> + 2703493408U, // <5,3,1,7>: Cost 3 vext3 <3,1,7,5>, <3,1,7,5> 2628920721U, // <5,3,1,u>: Cost 3 vext2 <1,u,5,3>, <1,u,5,3> - 3289923778U, // <5,3,2,0>: Cost 4 vrev <0,2,3,5> - 2687125814U, // <5,3,2,1>: Cost 3 vext3 <0,4,1,5>, <3,2,1,0> + 3766765870U, // <5,3,2,0>: Cost 4 vext3 <1,4,0,5>, <3,2,0,1> + 3698681379U, // <5,3,2,1>: Cost 4 vext2 <1,2,5,3>, <2,1,3,5> 3760867649U, // <5,3,2,2>: Cost 4 vext3 <0,4,1,5>, <3,2,2,2> 2698627404U, // <5,3,2,3>: Cost 3 vext3 <2,3,4,5>, <3,2,3,4> - 3633409334U, // <5,3,2,4>: Cost 4 vext1 <1,5,3,2>, RHS - 3760277850U, // <5,3,2,5>: Cost 4 vext3 <0,3,2,5>, <3,2,5,0> + 2703935830U, // <5,3,2,4>: Cost 3 vext3 <3,2,4,5>, <3,2,4,5> + 2698627422U, // <5,3,2,5>: Cost 3 vext3 <2,3,4,5>, <3,2,5,4> 3760867686U, // <5,3,2,6>: Cost 4 vext3 <0,4,1,5>, <3,2,6,3> 3769788783U, // <5,3,2,7>: Cost 4 vext3 <1,u,5,5>, <3,2,7,3> - 2698627445U, // <5,3,2,u>: Cost 3 vext3 <2,3,4,5>, <3,2,u,0> + 2701945209U, // <5,3,2,u>: Cost 3 vext3 <2,u,4,5>, <3,2,u,4> 3760867711U, // <5,3,3,0>: Cost 4 vext3 <0,4,1,5>, <3,3,0,1> 2636220684U, // <5,3,3,1>: Cost 3 vext2 <3,1,5,3>, <3,1,5,3> - 3760867729U, // <5,3,3,2>: Cost 4 vext3 <0,4,1,5>, <3,3,2,1> + 3772369298U, // <5,3,3,2>: Cost 4 vext3 <2,3,4,5>, <3,3,2,2> 2687125916U, // <5,3,3,3>: Cost 3 vext3 <0,4,1,5>, <3,3,3,3> 2704599463U, // <5,3,3,4>: Cost 3 vext3 <3,3,4,5>, <3,3,4,5> 2704673200U, // <5,3,3,5>: Cost 3 vext3 <3,3,5,5>, <3,3,5,5> @@ -3947,12 +3947,12 @@ 2704894411U, // <5,3,3,u>: Cost 3 vext3 <3,3,u,5>, <3,3,u,5> 2704968148U, // <5,3,4,0>: Cost 3 vext3 <3,4,0,5>, <3,4,0,5> 3698682850U, // <5,3,4,1>: Cost 4 vext2 <1,2,5,3>, <4,1,5,0> - 2705115622U, // <5,3,4,2>: Cost 3 vext3 <3,4,2,5>, <3,4,2,5> + 2642857014U, // <5,3,4,2>: Cost 3 vext2 <4,2,5,3>, <4,2,5,3> 2705189359U, // <5,3,4,3>: Cost 3 vext3 <3,4,3,5>, <3,4,3,5> 2705263096U, // <5,3,4,4>: Cost 3 vext3 <3,4,4,5>, <3,4,4,5> 2685946370U, // <5,3,4,5>: Cost 3 vext3 <0,2,3,5>, <3,4,5,6> 3779152394U, // <5,3,4,6>: Cost 4 vext3 <3,4,6,5>, <3,4,6,5> - 3779226131U, // <5,3,4,7>: Cost 4 vext3 <3,4,7,5>, <3,4,7,5> + 2236377699U, // <5,3,4,7>: Cost 3 vrev <3,5,7,4> 2687126045U, // <5,3,4,u>: Cost 3 vext3 <0,4,1,5>, <3,4,u,6> 2571632742U, // <5,3,5,0>: Cost 3 vext1 <3,5,3,5>, LHS 2559689870U, // <5,3,5,1>: Cost 3 vext1 <1,5,3,5>, <1,5,3,5> @@ -3961,7 +3961,7 @@ 2571636022U, // <5,3,5,4>: Cost 3 vext1 <3,5,3,5>, RHS 2559692804U, // <5,3,5,5>: Cost 3 vext1 <1,5,3,5>, <5,5,5,5> 3720581218U, // <5,3,5,6>: Cost 4 vext2 <4,u,5,3>, <5,6,7,0> - 2706147940U, // <5,3,5,7>: Cost 3 vext3 <3,5,7,5>, <3,5,7,5> + 2236385892U, // <5,3,5,7>: Cost 3 vrev <3,5,7,5> 2571638574U, // <5,3,5,u>: Cost 3 vext1 <3,5,3,5>, LHS 2565668966U, // <5,3,6,0>: Cost 3 vext1 <2,5,3,6>, LHS 3633439887U, // <5,3,6,1>: Cost 4 vext1 <1,5,3,6>, <1,5,3,6> @@ -3969,7 +3969,7 @@ 2565671426U, // <5,3,6,3>: Cost 3 vext1 <2,5,3,6>, <3,4,5,6> 2565672246U, // <5,3,6,4>: Cost 3 vext1 <2,5,3,6>, RHS 3639414630U, // <5,3,6,5>: Cost 4 vext1 <2,5,3,6>, <5,3,6,0> - 3639415352U, // <5,3,6,6>: Cost 4 vext1 <2,5,3,6>, <6,3,5,2> + 4047521640U, // <5,3,6,6>: Cost 4 vzipr <3,4,5,6>, <2,5,3,6> 2725169844U, // <5,3,6,7>: Cost 3 vext3 <6,7,4,5>, <3,6,7,4> 2565674798U, // <5,3,6,u>: Cost 3 vext1 <2,5,3,6>, LHS 1485963366U, // <5,3,7,0>: Cost 2 vext1 <1,5,3,7>, LHS @@ -3977,9 +3977,9 @@ 2559706728U, // <5,3,7,2>: Cost 3 vext1 <1,5,3,7>, <2,2,2,2> 2559707286U, // <5,3,7,3>: Cost 3 vext1 <1,5,3,7>, <3,0,1,2> 1485966646U, // <5,3,7,4>: Cost 2 vext1 <1,5,3,7>, RHS - 2559709039U, // <5,3,7,5>: Cost 3 vext1 <1,5,3,7>, <5,3,7,0> + 2559708880U, // <5,3,7,5>: Cost 3 vext1 <1,5,3,7>, <5,1,7,3> 2601513466U, // <5,3,7,6>: Cost 3 vext1 , <6,2,7,3> - 2559710480U, // <5,3,7,7>: Cost 3 vext1 <1,5,3,7>, <7,3,5,1> + 3114714112U, // <5,3,7,7>: Cost 3 vtrnr RHS, <1,3,5,7> 1485969198U, // <5,3,7,u>: Cost 2 vext1 <1,5,3,7>, LHS 1485971558U, // <5,3,u,0>: Cost 2 vext1 <1,5,3,u>, LHS 1485972625U, // <5,3,u,1>: Cost 2 vext1 <1,5,3,u>, <1,5,3,u> @@ -3988,133 +3988,133 @@ 1485974838U, // <5,3,u,4>: Cost 2 vext1 <1,5,3,u>, RHS 2687126342U, // <5,3,u,5>: Cost 3 vext3 <0,4,1,5>, <3,u,5,6> 2601521658U, // <5,3,u,6>: Cost 3 vext1 , <6,2,7,3> - 3114722304U, // <5,3,u,7>: Cost 3 vtrnr RHS, <1,3,5,7> + 2236410471U, // <5,3,u,7>: Cost 3 vrev <3,5,7,u> 1485977390U, // <5,3,u,u>: Cost 2 vext1 <1,5,3,u>, LHS - 2663432192U, // <5,4,0,0>: Cost 3 vext2 <7,6,5,4>, <0,0,0,0> - 1589690470U, // <5,4,0,1>: Cost 2 vext2 <7,6,5,4>, LHS - 2663432356U, // <5,4,0,2>: Cost 3 vext2 <7,6,5,4>, <0,2,0,2> - 2232846516U, // <5,4,0,3>: Cost 3 vrev <3,0,4,5> + 3627491430U, // <5,4,0,0>: Cost 4 vext1 <0,5,4,0>, LHS + 2636890214U, // <5,4,0,1>: Cost 3 vext2 <3,2,5,4>, LHS + 3703333028U, // <5,4,0,2>: Cost 4 vext2 <2,0,5,4>, <0,2,0,2> + 3782249348U, // <5,4,0,3>: Cost 4 vext3 <4,0,3,5>, <4,0,3,5> 2642198866U, // <5,4,0,4>: Cost 3 vext2 <4,1,5,4>, <0,4,1,5> - 2713963410U, // <5,4,0,5>: Cost 3 vext3 <4,u,5,5>, <4,0,5,1> - 2713963420U, // <5,4,0,6>: Cost 3 vext3 <4,u,5,5>, <4,0,6,2> - 2256737304U, // <5,4,0,7>: Cost 3 vrev <7,0,4,5> - 1589691037U, // <5,4,0,u>: Cost 2 vext2 <7,6,5,4>, LHS - 2215592058U, // <5,4,1,0>: Cost 3 vrev <0,1,4,5> - 2221564755U, // <5,4,1,1>: Cost 3 vrev <1,1,4,5> - 2663433110U, // <5,4,1,2>: Cost 3 vext2 <7,6,5,4>, <1,2,3,0> - 2663433176U, // <5,4,1,3>: Cost 3 vext2 <7,6,5,4>, <1,3,1,3> - 3627502902U, // <5,4,1,4>: Cost 4 vext1 <0,5,4,1>, RHS + 2687126418U, // <5,4,0,5>: Cost 3 vext3 <0,4,1,5>, <4,0,5,1> + 2242243887U, // <5,4,0,6>: Cost 3 vrev <4,5,6,0> + 3316059448U, // <5,4,0,7>: Cost 4 vrev <4,5,7,0> + 2636890781U, // <5,4,0,u>: Cost 3 vext2 <3,2,5,4>, LHS + 2241809658U, // <5,4,1,0>: Cost 3 vrev <4,5,0,1> + 3698025307U, // <5,4,1,1>: Cost 4 vext2 <1,1,5,4>, <1,1,5,4> + 3698688940U, // <5,4,1,2>: Cost 4 vext2 <1,2,5,4>, <1,2,5,4> + 3698689024U, // <5,4,1,3>: Cost 4 vext2 <1,2,5,4>, <1,3,5,7> + 3700016206U, // <5,4,1,4>: Cost 4 vext2 <1,4,5,4>, <1,4,5,4> 2687126498U, // <5,4,1,5>: Cost 3 vext3 <0,4,1,5>, <4,1,5,0> - 2709392368U, // <5,4,1,6>: Cost 3 vext3 <4,1,6,5>, <4,1,6,5> - 3331142761U, // <5,4,1,7>: Cost 4 vrev <7,1,4,5> - 2916748841U, // <5,4,1,u>: Cost 3 vzipl <5,1,7,3>, RHS - 2216255691U, // <5,4,2,0>: Cost 3 vrev <0,2,4,5> - 2222228388U, // <5,4,2,1>: Cost 3 vrev <1,2,4,5> - 2228201085U, // <5,4,2,2>: Cost 3 vrev <2,2,4,5> - 2638218958U, // <5,4,2,3>: Cost 3 vext2 <3,4,5,4>, <2,3,4,5> + 3760868336U, // <5,4,1,6>: Cost 4 vext3 <0,4,1,5>, <4,1,6,5> + 3316067641U, // <5,4,1,7>: Cost 4 vrev <4,5,7,1> + 2242399554U, // <5,4,1,u>: Cost 3 vrev <4,5,u,1> + 3703334371U, // <5,4,2,0>: Cost 4 vext2 <2,0,5,4>, <2,0,5,4> + 3703998004U, // <5,4,2,1>: Cost 4 vext2 <2,1,5,4>, <2,1,5,4> + 3704661637U, // <5,4,2,2>: Cost 4 vext2 <2,2,5,4>, <2,2,5,4> + 2636891854U, // <5,4,2,3>: Cost 3 vext2 <3,2,5,4>, <2,3,4,5> 3705988903U, // <5,4,2,4>: Cost 4 vext2 <2,4,5,4>, <2,4,5,4> 2698628150U, // <5,4,2,5>: Cost 3 vext3 <2,3,4,5>, <4,2,5,3> - 2252091873U, // <5,4,2,6>: Cost 3 vrev <6,2,4,5> - 3331806394U, // <5,4,2,7>: Cost 4 vrev <7,2,4,5> - 2663434299U, // <5,4,2,u>: Cost 3 vext2 <7,6,5,4>, <2,u,0,1> - 2589605990U, // <5,4,3,0>: Cost 3 vext1 <6,5,4,3>, LHS - 2222892021U, // <5,4,3,1>: Cost 3 vrev <1,3,4,5> - 1155122894U, // <5,4,3,2>: Cost 2 vrev <2,3,4,5> - 2234837415U, // <5,4,3,3>: Cost 3 vrev <3,3,4,5> + 3760868415U, // <5,4,2,6>: Cost 4 vext3 <0,4,1,5>, <4,2,6,3> + 3783871562U, // <5,4,2,7>: Cost 4 vext3 <4,2,7,5>, <4,2,7,5> + 2666752099U, // <5,4,2,u>: Cost 3 vext2 , <2,u,4,5> + 3639459942U, // <5,4,3,0>: Cost 4 vext1 <2,5,4,3>, LHS + 3709970701U, // <5,4,3,1>: Cost 4 vext2 <3,1,5,4>, <3,1,5,4> + 2636892510U, // <5,4,3,2>: Cost 3 vext2 <3,2,5,4>, <3,2,5,4> + 3710634396U, // <5,4,3,3>: Cost 4 vext2 <3,2,5,4>, <3,3,3,3> 2638219776U, // <5,4,3,4>: Cost 3 vext2 <3,4,5,4>, <3,4,5,4> 3766987908U, // <5,4,3,5>: Cost 4 vext3 <1,4,3,5>, <4,3,5,0> - 2252755506U, // <5,4,3,6>: Cost 3 vrev <6,3,4,5> - 2258728203U, // <5,4,3,7>: Cost 3 vrev <7,3,4,5> - 1190959076U, // <5,4,3,u>: Cost 2 vrev + 2710719634U, // <5,4,3,6>: Cost 3 vext3 <4,3,6,5>, <4,3,6,5> + 3914097664U, // <5,4,3,7>: Cost 4 vuzpr <3,5,7,4>, <1,3,5,7> + 2640874308U, // <5,4,3,u>: Cost 3 vext2 <3,u,5,4>, <3,u,5,4> 2583642214U, // <5,4,4,0>: Cost 3 vext1 <5,5,4,4>, LHS 2642201574U, // <5,4,4,1>: Cost 3 vext2 <4,1,5,4>, <4,1,5,4> - 3303270175U, // <5,4,4,2>: Cost 4 vrev <2,4,4,5> - 2235501048U, // <5,4,4,3>: Cost 3 vrev <3,4,4,5> + 3710635062U, // <5,4,4,2>: Cost 4 vext2 <3,2,5,4>, <4,2,5,3> + 3717270664U, // <5,4,4,3>: Cost 4 vext2 <4,3,5,4>, <4,3,5,4> 2713963728U, // <5,4,4,4>: Cost 3 vext3 <4,u,5,5>, <4,4,4,4> - 1589693750U, // <5,4,4,5>: Cost 2 vext2 <7,6,5,4>, RHS - 2713963748U, // <5,4,4,6>: Cost 3 vext3 <4,u,5,5>, <4,4,6,6> + 1637567706U, // <5,4,4,5>: Cost 2 vext3 <4,4,5,5>, <4,4,5,5> + 2242276659U, // <5,4,4,6>: Cost 3 vrev <4,5,6,4> 2646183372U, // <5,4,4,7>: Cost 3 vext2 <4,7,5,4>, <4,7,5,4> - 1589693993U, // <5,4,4,u>: Cost 2 vext2 <7,6,5,4>, RHS + 1637788917U, // <5,4,4,u>: Cost 2 vext3 <4,4,u,5>, <4,4,u,5> 2559762534U, // <5,4,5,0>: Cost 3 vext1 <1,5,4,5>, LHS - 2224219287U, // <5,4,5,1>: Cost 3 vrev <1,5,4,5> + 2559763607U, // <5,4,5,1>: Cost 3 vext1 <1,5,4,5>, <1,5,4,5> 2698628366U, // <5,4,5,2>: Cost 3 vext3 <2,3,4,5>, <4,5,2,3> 3633506454U, // <5,4,5,3>: Cost 4 vext1 <1,5,4,5>, <3,0,1,2> 2559765814U, // <5,4,5,4>: Cost 3 vext1 <1,5,4,5>, RHS - 2248110075U, // <5,4,5,5>: Cost 3 vrev <5,5,4,5> + 2583654395U, // <5,4,5,5>: Cost 3 vext1 <5,5,4,5>, <5,5,4,5> 1613385014U, // <5,4,5,6>: Cost 2 vext3 <0,4,1,5>, RHS - 2663436456U, // <5,4,5,7>: Cost 3 vext2 <7,6,5,4>, <5,7,5,7> + 3901639990U, // <5,4,5,7>: Cost 4 vuzpr <1,5,0,4>, RHS 1613385032U, // <5,4,5,u>: Cost 2 vext3 <0,4,1,5>, RHS 2559770726U, // <5,4,6,0>: Cost 3 vext1 <1,5,4,6>, LHS 2559771648U, // <5,4,6,1>: Cost 3 vext1 <1,5,4,6>, <1,3,5,7> - 2230855617U, // <5,4,6,2>: Cost 3 vrev <2,6,4,5> + 3633514088U, // <5,4,6,2>: Cost 4 vext1 <1,5,4,6>, <2,2,2,2> 2571717122U, // <5,4,6,3>: Cost 3 vext1 <3,5,4,6>, <3,4,5,6> 2559774006U, // <5,4,6,4>: Cost 3 vext1 <1,5,4,6>, RHS 2712636796U, // <5,4,6,5>: Cost 3 vext3 <4,6,5,5>, <4,6,5,5> - 2254746405U, // <5,4,6,6>: Cost 3 vrev <6,6,4,5> + 3760868743U, // <5,4,6,6>: Cost 4 vext3 <0,4,1,5>, <4,6,6,7> 2712784270U, // <5,4,6,7>: Cost 3 vext3 <4,6,7,5>, <4,6,7,5> 2559776558U, // <5,4,6,u>: Cost 3 vext1 <1,5,4,6>, LHS 2565750886U, // <5,4,7,0>: Cost 3 vext1 <2,5,4,7>, LHS 2565751706U, // <5,4,7,1>: Cost 3 vext1 <2,5,4,7>, <1,2,3,4> 2565752690U, // <5,4,7,2>: Cost 3 vext1 <2,5,4,7>, <2,5,4,7> - 2237491947U, // <5,4,7,3>: Cost 3 vrev <3,7,4,5> + 2571725387U, // <5,4,7,3>: Cost 3 vext1 <3,5,4,7>, <3,5,4,7> 2565754166U, // <5,4,7,4>: Cost 3 vext1 <2,5,4,7>, RHS 3114713426U, // <5,4,7,5>: Cost 3 vtrnr RHS, <0,4,1,5> - 1181668214U, // <5,4,7,6>: Cost 2 vrev <6,7,4,5> - 2663437921U, // <5,4,7,7>: Cost 3 vext2 <7,6,5,4>, <7,7,6,5> - 1591023272U, // <5,4,7,u>: Cost 2 vext2 <7,u,5,4>, <7,u,5,4> - 2220237489U, // <5,4,u,0>: Cost 3 vrev <0,u,4,5> - 1589696302U, // <5,4,u,1>: Cost 2 vext2 <7,6,5,4>, LHS - 1158441059U, // <5,4,u,2>: Cost 2 vrev <2,u,4,5> - 2238155580U, // <5,4,u,3>: Cost 3 vrev <3,u,4,5> + 94817590U, // <5,4,7,6>: Cost 1 vrev RHS + 2595616175U, // <5,4,7,7>: Cost 3 vext1 <7,5,4,7>, <7,5,4,7> + 94965064U, // <5,4,7,u>: Cost 1 vrev RHS + 2559787110U, // <5,4,u,0>: Cost 3 vext1 <1,5,4,u>, LHS + 2559788186U, // <5,4,u,1>: Cost 3 vext1 <1,5,4,u>, <1,5,4,u> + 2242014483U, // <5,4,u,2>: Cost 3 vrev <4,5,2,u> + 2667419628U, // <5,4,u,3>: Cost 3 vext2 , 2559790390U, // <5,4,u,4>: Cost 3 vext1 <1,5,4,u>, RHS 1640222238U, // <5,4,u,5>: Cost 2 vext3 <4,u,5,5>, <4,u,5,5> - 1613385257U, // <5,4,u,6>: Cost 2 vext3 <0,4,1,5>, RHS + 94825783U, // <5,4,u,6>: Cost 1 vrev RHS 2714111536U, // <5,4,u,7>: Cost 3 vext3 <4,u,7,5>, <4,u,7,5> - 1613385275U, // <5,4,u,u>: Cost 2 vext3 <0,4,1,5>, RHS + 94973257U, // <5,4,u,u>: Cost 1 vrev RHS 2646851584U, // <5,5,0,0>: Cost 3 vext2 <4,u,5,5>, <0,0,0,0> 1573109862U, // <5,5,0,1>: Cost 2 vext2 <4,u,5,5>, LHS 2646851748U, // <5,5,0,2>: Cost 3 vext2 <4,u,5,5>, <0,2,0,2> 3760279130U, // <5,5,0,3>: Cost 4 vext3 <0,3,2,5>, <5,0,3,2> 2687127138U, // <5,5,0,4>: Cost 3 vext3 <0,4,1,5>, <5,0,4,1> - 2583687167U, // <5,5,0,5>: Cost 3 vext1 <5,5,5,0>, <5,5,5,0> + 2248142847U, // <5,5,0,5>: Cost 3 vrev <5,5,5,0> 3720593910U, // <5,5,0,6>: Cost 4 vext2 <4,u,5,5>, <0,6,1,7> 4182502710U, // <5,5,0,7>: Cost 4 vtrnr <3,5,7,0>, RHS 1573110429U, // <5,5,0,u>: Cost 2 vext2 <4,u,5,5>, LHS - 2577719398U, // <5,5,1,0>: Cost 3 vext1 <4,5,5,1>, LHS + 2646852342U, // <5,5,1,0>: Cost 3 vext2 <4,u,5,5>, <1,0,3,2> 2624291676U, // <5,5,1,1>: Cost 3 vext2 <1,1,5,5>, <1,1,5,5> 2646852502U, // <5,5,1,2>: Cost 3 vext2 <4,u,5,5>, <1,2,3,0> 2646852568U, // <5,5,1,3>: Cost 3 vext2 <4,u,5,5>, <1,3,1,3> - 2687127218U, // <5,5,1,4>: Cost 3 vext3 <0,4,1,5>, <5,1,4,0> + 2715217591U, // <5,5,1,4>: Cost 3 vext3 <5,1,4,5>, <5,1,4,5> 2628936848U, // <5,5,1,5>: Cost 3 vext2 <1,u,5,5>, <1,5,3,7> 3698033907U, // <5,5,1,6>: Cost 4 vext2 <1,1,5,5>, <1,6,5,7> 2713964240U, // <5,5,1,7>: Cost 3 vext3 <4,u,5,5>, <5,1,7,3> - 2689781462U, // <5,5,1,u>: Cost 3 vext3 <0,u,1,5>, <5,1,u,0> + 2628937107U, // <5,5,1,u>: Cost 3 vext2 <1,u,5,5>, <1,u,5,5> 3645497446U, // <5,5,2,0>: Cost 4 vext1 <3,5,5,2>, LHS - 3758952168U, // <5,5,2,1>: Cost 4 vext3 <0,1,2,5>, <5,2,1,0> + 3760869099U, // <5,5,2,1>: Cost 4 vext3 <0,4,1,5>, <5,2,1,3> 2646853224U, // <5,5,2,2>: Cost 3 vext2 <4,u,5,5>, <2,2,2,2> 2698628862U, // <5,5,2,3>: Cost 3 vext3 <2,3,4,5>, <5,2,3,4> - 3760942851U, // <5,5,2,4>: Cost 4 vext3 <0,4,2,5>, <5,2,4,0> + 3772370694U, // <5,5,2,4>: Cost 4 vext3 <2,3,4,5>, <5,2,4,3> 2713964303U, // <5,5,2,5>: Cost 3 vext3 <4,u,5,5>, <5,2,5,3> 2646853562U, // <5,5,2,6>: Cost 3 vext2 <4,u,5,5>, <2,6,3,7> 4038198272U, // <5,5,2,7>: Cost 4 vzipr <1,u,5,2>, <1,3,5,7> 2701946667U, // <5,5,2,u>: Cost 3 vext3 <2,u,4,5>, <5,2,u,4> 2646853782U, // <5,5,3,0>: Cost 3 vext2 <4,u,5,5>, <3,0,1,2> 3698034922U, // <5,5,3,1>: Cost 4 vext2 <1,1,5,5>, <3,1,1,5> - 2646853942U, // <5,5,3,2>: Cost 3 vext2 <4,u,5,5>, <3,2,1,0> + 3702679919U, // <5,5,3,2>: Cost 4 vext2 <1,u,5,5>, <3,2,7,3> 2637564336U, // <5,5,3,3>: Cost 3 vext2 <3,3,5,5>, <3,3,5,5> 2646854146U, // <5,5,3,4>: Cost 3 vext2 <4,u,5,5>, <3,4,5,6> 2638891602U, // <5,5,3,5>: Cost 3 vext2 <3,5,5,5>, <3,5,5,5> 3702680247U, // <5,5,3,6>: Cost 4 vext2 <1,u,5,5>, <3,6,7,7> 3702680259U, // <5,5,3,7>: Cost 4 vext2 <1,u,5,5>, <3,7,0,1> - 2646854428U, // <5,5,3,u>: Cost 3 vext2 <4,u,5,5>, <3,u,1,0> + 2646854430U, // <5,5,3,u>: Cost 3 vext2 <4,u,5,5>, <3,u,1,2> 2646854546U, // <5,5,4,0>: Cost 3 vext2 <4,u,5,5>, <4,0,5,1> - 3760869263U, // <5,5,4,1>: Cost 4 vext3 <0,4,1,5>, <5,4,1,5> - 3759763347U, // <5,5,4,2>: Cost 4 vext3 <0,2,4,5>, <5,4,2,0> - 2698629022U, // <5,5,4,3>: Cost 3 vext3 <2,3,4,5>, <5,4,3,2> + 2642209767U, // <5,5,4,1>: Cost 3 vext2 <4,1,5,5>, <4,1,5,5> + 3711306806U, // <5,5,4,2>: Cost 4 vext2 <3,3,5,5>, <4,2,5,3> + 3645516369U, // <5,5,4,3>: Cost 4 vext1 <3,5,5,4>, <3,5,5,4> 1570458842U, // <5,5,4,4>: Cost 2 vext2 <4,4,5,5>, <4,4,5,5> 1573113142U, // <5,5,4,5>: Cost 2 vext2 <4,u,5,5>, RHS 2645527932U, // <5,5,4,6>: Cost 3 vext2 <4,6,5,5>, <4,6,5,5> - 2717429701U, // <5,5,4,7>: Cost 3 vext3 <5,4,7,5>, <5,4,7,5> + 2713964486U, // <5,5,4,7>: Cost 3 vext3 <4,u,5,5>, <5,4,7,6> 1573113374U, // <5,5,4,u>: Cost 2 vext2 <4,u,5,5>, <4,u,5,5> 1509982310U, // <5,5,5,0>: Cost 2 vext1 <5,5,5,5>, LHS 2646855376U, // <5,5,5,1>: Cost 3 vext2 <4,u,5,5>, <5,1,7,3> @@ -4140,13 +4140,13 @@ 2571799124U, // <5,5,7,3>: Cost 3 vext1 <3,5,5,7>, <3,5,5,7> 2571799862U, // <5,5,7,4>: Cost 3 vext1 <3,5,5,7>, RHS 3114717188U, // <5,5,7,5>: Cost 3 vtrnr RHS, <5,5,5,5> - 2646857222U, // <5,5,7,6>: Cost 3 vext2 <4,u,5,5>, <7,6,5,4> + 4034923010U, // <5,5,7,6>: Cost 4 vzipr <1,3,5,7>, <3,4,5,6> 2040974646U, // <5,5,7,7>: Cost 2 vtrnr RHS, RHS 2040974647U, // <5,5,7,u>: Cost 2 vtrnr RHS, RHS 1509982310U, // <5,5,u,0>: Cost 2 vext1 <5,5,5,5>, LHS 1573115694U, // <5,5,u,1>: Cost 2 vext2 <4,u,5,5>, LHS 2571806414U, // <5,5,u,2>: Cost 3 vext1 <3,5,5,u>, <2,3,4,5> - 2698924258U, // <5,5,u,3>: Cost 3 vext3 <2,3,u,5>, <5,u,3,2> + 2571807317U, // <5,5,u,3>: Cost 3 vext1 <3,5,5,u>, <3,5,5,u> 1509985590U, // <5,5,u,4>: Cost 2 vext1 <5,5,5,5>, RHS 229035318U, // <5,5,u,5>: Cost 1 vdup1 RHS 2646857936U, // <5,5,u,6>: Cost 3 vext2 <4,u,5,5>, @@ -4159,9 +4159,9 @@ 2638233938U, // <5,6,0,4>: Cost 3 vext2 <3,4,5,6>, <0,4,1,5> 3706003885U, // <5,6,0,5>: Cost 4 vext2 <2,4,5,6>, <0,5,2,6> 3706003967U, // <5,6,0,6>: Cost 4 vext2 <2,4,5,6>, <0,6,2,7> - 2662122052U, // <5,6,0,7>: Cost 3 vext2 <7,4,5,6>, <0,7,1,4> + 4047473974U, // <5,6,0,7>: Cost 4 vzipr <3,4,5,0>, RHS 1564492445U, // <5,6,0,u>: Cost 2 vext2 <3,4,5,6>, LHS - 3700032228U, // <5,6,1,0>: Cost 4 vext2 <1,4,5,6>, <1,0,1,2> + 2638234358U, // <5,6,1,0>: Cost 3 vext2 <3,4,5,6>, <1,0,3,2> 2638234420U, // <5,6,1,1>: Cost 3 vext2 <3,4,5,6>, <1,1,1,1> 2638234518U, // <5,6,1,2>: Cost 3 vext2 <3,4,5,6>, <1,2,3,0> 2638234584U, // <5,6,1,3>: Cost 3 vext2 <3,4,5,6>, <1,3,1,3> @@ -4171,7 +4171,7 @@ 2982366518U, // <5,6,1,7>: Cost 3 vzipr <4,u,5,1>, RHS 2628945300U, // <5,6,1,u>: Cost 3 vext2 <1,u,5,6>, <1,u,5,6> 3706004925U, // <5,6,2,0>: Cost 4 vext2 <2,4,5,6>, <2,0,1,2> - 3711976963U, // <5,6,2,1>: Cost 4 vext2 <3,4,5,6>, <2,1,0,0> + 3711976966U, // <5,6,2,1>: Cost 4 vext2 <3,4,5,6>, <2,1,0,3> 2638235240U, // <5,6,2,2>: Cost 3 vext2 <3,4,5,6>, <2,2,2,2> 2638235302U, // <5,6,2,3>: Cost 3 vext2 <3,4,5,6>, <2,3,0,1> 2632263465U, // <5,6,2,4>: Cost 3 vext2 <2,4,5,6>, <2,4,5,6> @@ -4180,8 +4180,8 @@ 2713965050U, // <5,6,2,7>: Cost 3 vext3 <4,u,5,5>, <6,2,7,3> 2634917997U, // <5,6,2,u>: Cost 3 vext2 <2,u,5,6>, <2,u,5,6> 2638235798U, // <5,6,3,0>: Cost 3 vext2 <3,4,5,6>, <3,0,1,2> - 3711977702U, // <5,6,3,1>: Cost 4 vext2 <3,4,5,6>, <3,1,1,1> - 2638235958U, // <5,6,3,2>: Cost 3 vext2 <3,4,5,6>, <3,2,1,0> + 3711977695U, // <5,6,3,1>: Cost 4 vext2 <3,4,5,6>, <3,1,0,3> + 3710650720U, // <5,6,3,2>: Cost 4 vext2 <3,2,5,6>, <3,2,5,6> 2638236060U, // <5,6,3,3>: Cost 3 vext2 <3,4,5,6>, <3,3,3,3> 1564494338U, // <5,6,3,4>: Cost 2 vext2 <3,4,5,6>, <3,4,5,6> 2638236234U, // <5,6,3,5>: Cost 3 vext2 <3,4,5,6>, <3,5,4,6> @@ -4189,18 +4189,18 @@ 4034227510U, // <5,6,3,7>: Cost 4 vzipr <1,2,5,3>, RHS 1567148870U, // <5,6,3,u>: Cost 2 vext2 <3,u,5,6>, <3,u,5,6> 2577817702U, // <5,6,4,0>: Cost 3 vext1 <4,5,6,4>, LHS - 3711978442U, // <5,6,4,1>: Cost 4 vext2 <3,4,5,6>, <4,1,2,3> + 3700034544U, // <5,6,4,1>: Cost 4 vext2 <1,4,5,6>, <4,1,6,5> 2723033713U, // <5,6,4,2>: Cost 3 vext3 <6,4,2,5>, <6,4,2,5> - 2577820162U, // <5,6,4,3>: Cost 3 vext1 <4,5,6,4>, <3,4,5,6> + 2638236818U, // <5,6,4,3>: Cost 3 vext2 <3,4,5,6>, <4,3,6,5> 2644208859U, // <5,6,4,4>: Cost 3 vext2 <4,4,5,6>, <4,4,5,6> 1564495158U, // <5,6,4,5>: Cost 2 vext2 <3,4,5,6>, RHS 2645536125U, // <5,6,4,6>: Cost 3 vext2 <4,6,5,6>, <4,6,5,6> - 2646199758U, // <5,6,4,7>: Cost 3 vext2 <4,7,5,6>, <4,7,5,6> + 2723402398U, // <5,6,4,7>: Cost 3 vext3 <6,4,7,5>, <6,4,7,5> 1564495401U, // <5,6,4,u>: Cost 2 vext2 <3,4,5,6>, RHS 2577825894U, // <5,6,5,0>: Cost 3 vext1 <4,5,6,5>, LHS 2662125264U, // <5,6,5,1>: Cost 3 vext2 <7,4,5,6>, <5,1,7,3> 3775836867U, // <5,6,5,2>: Cost 4 vext3 <2,u,6,5>, <6,5,2,6> - 3711979330U, // <5,6,5,3>: Cost 4 vext2 <3,4,5,6>, <5,3,2,0> + 3711979343U, // <5,6,5,3>: Cost 4 vext2 <3,4,5,6>, <5,3,3,4> 2650181556U, // <5,6,5,4>: Cost 3 vext2 <5,4,5,6>, <5,4,5,6> 2662125572U, // <5,6,5,5>: Cost 3 vext2 <7,4,5,6>, <5,5,5,5> 2638237732U, // <5,6,5,6>: Cost 3 vext2 <3,4,5,6>, <5,6,0,1> @@ -4211,18 +4211,18 @@ 2662126074U, // <5,6,6,2>: Cost 3 vext2 <7,4,5,6>, <6,2,7,3> 2583808514U, // <5,6,6,3>: Cost 3 vext1 <5,5,6,6>, <3,4,5,6> 2583809334U, // <5,6,6,4>: Cost 3 vext1 <5,5,6,6>, RHS - 2638238418U, // <5,6,6,5>: Cost 3 vext2 <3,4,5,6>, <6,5,4,3> + 2583810062U, // <5,6,6,5>: Cost 3 vext1 <5,5,6,6>, <5,5,6,6> 2638238520U, // <5,6,6,6>: Cost 3 vext2 <3,4,5,6>, <6,6,6,6> 2973781302U, // <5,6,6,7>: Cost 3 vzipr <3,4,5,6>, RHS 2973781303U, // <5,6,6,u>: Cost 3 vzipr <3,4,5,6>, RHS 430358630U, // <5,6,7,0>: Cost 1 vext1 RHS, LHS - 1504101172U, // <5,6,7,1>: Cost 2 vext1 RHS, <1,1,1,1> + 1504101110U, // <5,6,7,1>: Cost 2 vext1 RHS, <1,0,3,2> 1504101992U, // <5,6,7,2>: Cost 2 vext1 RHS, <2,2,2,2> 1504102550U, // <5,6,7,3>: Cost 2 vext1 RHS, <3,0,1,2> 430361910U, // <5,6,7,4>: Cost 1 vext1 RHS, RHS - 1504104452U, // <5,6,7,5>: Cost 2 vext1 RHS, <5,5,5,5> + 1504104390U, // <5,6,7,5>: Cost 2 vext1 RHS, <5,4,7,6> 1504105272U, // <5,6,7,6>: Cost 2 vext1 RHS, <6,6,6,6> - 1504105990U, // <5,6,7,7>: Cost 2 vext1 RHS, <7,6,5,4> + 1504106092U, // <5,6,7,7>: Cost 2 vext1 RHS, <7,7,7,7> 430364462U, // <5,6,7,u>: Cost 1 vext1 RHS, LHS 430366822U, // <5,6,u,0>: Cost 1 vext1 RHS, LHS 1564497710U, // <5,6,u,1>: Cost 2 vext2 <3,4,5,6>, LHS @@ -4240,9 +4240,9 @@ 2625634642U, // <5,7,0,4>: Cost 3 vext2 <1,3,5,7>, <0,4,1,5> 2595778728U, // <5,7,0,5>: Cost 3 vext1 <7,5,7,0>, <5,7,5,7> 3699376639U, // <5,7,0,6>: Cost 4 vext2 <1,3,5,7>, <0,6,2,7> - 2595780035U, // <5,7,0,7>: Cost 3 vext1 <7,5,7,0>, <7,5,7,0> + 2260235715U, // <5,7,0,7>: Cost 3 vrev <7,5,7,0> 1551893149U, // <5,7,0,u>: Cost 2 vext2 <1,3,5,7>, LHS - 2571894886U, // <5,7,1,0>: Cost 3 vext1 <3,5,7,1>, LHS + 2625635062U, // <5,7,1,0>: Cost 3 vext2 <1,3,5,7>, <1,0,3,2> 2624308020U, // <5,7,1,1>: Cost 3 vext2 <1,1,5,7>, <1,1,1,1> 2625635222U, // <5,7,1,2>: Cost 3 vext2 <1,3,5,7>, <1,2,3,0> 1551893504U, // <5,7,1,3>: Cost 2 vext2 <1,3,5,7>, <1,3,5,7> @@ -4252,7 +4252,7 @@ 3702031684U, // <5,7,1,7>: Cost 4 vext2 <1,7,5,7>, <1,7,5,7> 1555211669U, // <5,7,1,u>: Cost 2 vext2 <1,u,5,7>, <1,u,5,7> 2629617126U, // <5,7,2,0>: Cost 3 vext2 <2,0,5,7>, <2,0,5,7> - 3699377694U, // <5,7,2,1>: Cost 4 vext2 <1,3,5,7>, <2,1,3,0> + 3699377670U, // <5,7,2,1>: Cost 4 vext2 <1,3,5,7>, <2,1,0,3> 2625635944U, // <5,7,2,2>: Cost 3 vext2 <1,3,5,7>, <2,2,2,2> 2625636006U, // <5,7,2,3>: Cost 3 vext2 <1,3,5,7>, <2,3,0,1> 2632271658U, // <5,7,2,4>: Cost 3 vext2 <2,4,5,7>, <2,4,5,7> @@ -4262,13 +4262,13 @@ 2625636411U, // <5,7,2,u>: Cost 3 vext2 <1,3,5,7>, <2,u,0,1> 2625636502U, // <5,7,3,0>: Cost 3 vext2 <1,3,5,7>, <3,0,1,2> 2625636604U, // <5,7,3,1>: Cost 3 vext2 <1,3,5,7>, <3,1,3,5> - 2625636662U, // <5,7,3,2>: Cost 3 vext2 <1,3,5,7>, <3,2,1,0> + 3699378478U, // <5,7,3,2>: Cost 4 vext2 <1,3,5,7>, <3,2,0,1> 2625636764U, // <5,7,3,3>: Cost 3 vext2 <1,3,5,7>, <3,3,3,3> 2625636866U, // <5,7,3,4>: Cost 3 vext2 <1,3,5,7>, <3,4,5,6> 2625636959U, // <5,7,3,5>: Cost 3 vext2 <1,3,5,7>, <3,5,7,0> 3699378808U, // <5,7,3,6>: Cost 4 vext2 <1,3,5,7>, <3,6,0,7> 2640235254U, // <5,7,3,7>: Cost 3 vext2 <3,7,5,7>, <3,7,5,7> - 2625637148U, // <5,7,3,u>: Cost 3 vext2 <1,3,5,7>, <3,u,1,0> + 2625637150U, // <5,7,3,u>: Cost 3 vext2 <1,3,5,7>, <3,u,1,2> 2571919462U, // <5,7,4,0>: Cost 3 vext1 <3,5,7,4>, LHS 2571920384U, // <5,7,4,1>: Cost 3 vext1 <3,5,7,4>, <1,3,5,7> 3699379260U, // <5,7,4,2>: Cost 4 vext2 <1,3,5,7>, <4,2,6,0> @@ -4281,7 +4281,7 @@ 2583871590U, // <5,7,5,0>: Cost 3 vext1 <5,5,7,5>, LHS 2652180176U, // <5,7,5,1>: Cost 3 vext2 <5,7,5,7>, <5,1,7,3> 2625638177U, // <5,7,5,2>: Cost 3 vext2 <1,3,5,7>, <5,2,7,3> - 2625638271U, // <5,7,5,3>: Cost 3 vext2 <1,3,5,7>, <5,3,u,7> + 2625638262U, // <5,7,5,3>: Cost 3 vext2 <1,3,5,7>, <5,3,7,7> 2583874870U, // <5,7,5,4>: Cost 3 vext1 <5,5,7,5>, RHS 2846281732U, // <5,7,5,5>: Cost 3 vuzpr RHS, <5,5,5,5> 2651517015U, // <5,7,5,6>: Cost 3 vext2 <5,6,5,7>, <5,6,5,7> @@ -4292,7 +4292,7 @@ 2846281108U, // <5,7,6,2>: Cost 3 vuzpr RHS, <4,6,u,2> 2589854210U, // <5,7,6,3>: Cost 3 vext1 <6,5,7,6>, <3,4,5,6> 2846281830U, // <5,7,6,4>: Cost 3 vuzpr RHS, <5,6,7,4> - 2713966086U, // <5,7,6,5>: Cost 3 vext3 <4,u,5,5>, <7,6,5,4> + 2725467658U, // <5,7,6,5>: Cost 3 vext3 <6,7,u,5>, <7,6,5,u> 2846281076U, // <5,7,6,6>: Cost 3 vuzpr RHS, <4,6,4,6> 2846279610U, // <5,7,6,7>: Cost 3 vuzpr RHS, <2,6,3,7> 2846279611U, // <5,7,6,u>: Cost 3 vuzpr RHS, <2,6,3,u> @@ -4307,7 +4307,7 @@ 1510151982U, // <5,7,7,u>: Cost 2 vext1 <5,5,7,7>, LHS 1510154342U, // <5,7,u,0>: Cost 2 vext1 <5,5,7,u>, LHS 1551898414U, // <5,7,u,1>: Cost 2 vext2 <1,3,5,7>, LHS - 2625640307U, // <5,7,u,2>: Cost 3 vext2 <1,3,5,7>, + 2625640325U, // <5,7,u,2>: Cost 3 vext2 <1,3,5,7>, 1772536477U, // <5,7,u,3>: Cost 2 vuzpr RHS, LHS 1510157622U, // <5,7,u,4>: Cost 2 vext1 <5,5,7,u>, RHS 1551898778U, // <5,7,u,5>: Cost 2 vext2 <1,3,5,7>, RHS @@ -4317,14 +4317,14 @@ 2625642496U, // <5,u,0,0>: Cost 3 vext2 <1,3,5,u>, <0,0,0,0> 1551900774U, // <5,u,0,1>: Cost 2 vext2 <1,3,5,u>, LHS 2625642660U, // <5,u,0,2>: Cost 3 vext2 <1,3,5,u>, <0,2,0,2> - 2233141464U, // <5,u,0,3>: Cost 3 vrev <3,0,u,5> + 2698630885U, // <5,u,0,3>: Cost 3 vext3 <2,3,4,5>, 2687129325U, // <5,u,0,4>: Cost 3 vext3 <0,4,1,5>, - 2595852457U, // <5,u,0,5>: Cost 3 vext1 <7,5,u,0>, <5,7,5,u> - 2737116928U, // <5,u,0,6>: Cost 3 vext3 , - 2257032252U, // <5,u,0,7>: Cost 3 vrev <7,0,u,5> + 2689783542U, // <5,u,0,5>: Cost 3 vext3 <0,u,1,5>, + 2266134675U, // <5,u,0,6>: Cost 3 vrev + 2595853772U, // <5,u,0,7>: Cost 3 vext1 <7,5,u,0>, <7,5,u,0> 1551901341U, // <5,u,0,u>: Cost 2 vext2 <1,3,5,u>, LHS - 2560024678U, // <5,u,1,0>: Cost 3 vext1 <1,5,u,1>, LHS - 2221859703U, // <5,u,1,1>: Cost 3 vrev <1,1,u,5> + 2625643254U, // <5,u,1,0>: Cost 3 vext2 <1,3,5,u>, <1,0,3,2> + 2625643316U, // <5,u,1,1>: Cost 3 vext2 <1,3,5,u>, <1,1,1,1> 1613387566U, // <5,u,1,2>: Cost 2 vext3 <0,4,1,5>, LHS 1551901697U, // <5,u,1,3>: Cost 2 vext2 <1,3,5,u>, <1,3,5,u> 2626307154U, // <5,u,1,4>: Cost 3 vext2 <1,4,5,u>, <1,4,5,u> @@ -4332,8 +4332,8 @@ 2627634420U, // <5,u,1,6>: Cost 3 vext2 <1,6,5,u>, <1,6,5,u> 2982366536U, // <5,u,1,7>: Cost 3 vzipr <4,u,5,1>, RHS 1613387620U, // <5,u,1,u>: Cost 2 vext3 <0,4,1,5>, LHS - 2216550639U, // <5,u,2,0>: Cost 3 vrev <0,2,u,5> - 2687129459U, // <5,u,2,1>: Cost 3 vext3 <0,4,1,5>, + 2846286742U, // <5,u,2,0>: Cost 3 vuzpr RHS, <1,2,3,0> + 2685796528U, // <5,u,2,1>: Cost 3 vext3 <0,2,1,5>, <0,2,1,5> 2625644136U, // <5,u,2,2>: Cost 3 vext2 <1,3,5,u>, <2,2,2,2> 2687129480U, // <5,u,2,3>: Cost 3 vext3 <0,4,1,5>, 2632279851U, // <5,u,2,4>: Cost 3 vext2 <2,4,5,u>, <2,4,5,u> @@ -4342,12 +4342,12 @@ 2713966508U, // <5,u,2,7>: Cost 3 vext3 <4,u,5,5>, 2625644603U, // <5,u,2,u>: Cost 3 vext2 <1,3,5,u>, <2,u,0,1> 2687129532U, // <5,u,3,0>: Cost 3 vext3 <0,4,1,5>, - 2223186969U, // <5,u,3,1>: Cost 3 vrev <1,3,u,5> - 1155417842U, // <5,u,3,2>: Cost 2 vrev <2,3,u,5> + 2636261649U, // <5,u,3,1>: Cost 3 vext2 <3,1,5,u>, <3,1,5,u> + 2636925282U, // <5,u,3,2>: Cost 3 vext2 <3,2,5,u>, <3,2,5,u> 2625644956U, // <5,u,3,3>: Cost 3 vext2 <1,3,5,u>, <3,3,3,3> 1564510724U, // <5,u,3,4>: Cost 2 vext2 <3,4,5,u>, <3,4,5,u> 2625645160U, // <5,u,3,5>: Cost 3 vext2 <1,3,5,u>, <3,5,u,0> - 2253050454U, // <5,u,3,6>: Cost 3 vrev <6,3,u,5> + 2734610422U, // <5,u,3,6>: Cost 3 vext3 , 2640243447U, // <5,u,3,7>: Cost 3 vext2 <3,7,5,u>, <3,7,5,u> 1567165256U, // <5,u,3,u>: Cost 2 vext2 <3,u,5,u>, <3,u,5,u> 1567828889U, // <5,u,4,0>: Cost 2 vext2 <4,0,5,u>, <4,0,5,u> @@ -4360,7 +4360,7 @@ 2646216144U, // <5,u,4,7>: Cost 3 vext2 <4,7,5,u>, <4,7,5,u> 1551904297U, // <5,u,4,u>: Cost 2 vext2 <1,3,5,u>, RHS 1509982310U, // <5,u,5,0>: Cost 2 vext1 <5,5,5,5>, LHS - 2224514235U, // <5,u,5,1>: Cost 3 vrev <1,5,u,5> + 2560058555U, // <5,u,5,1>: Cost 3 vext1 <1,5,u,5>, <1,5,u,5> 2698926194U, // <5,u,5,2>: Cost 3 vext3 <2,3,u,5>, 2698631295U, // <5,u,5,3>: Cost 3 vext3 <2,3,4,5>, 1509985590U, // <5,u,5,4>: Cost 2 vext1 <5,5,5,5>, RHS @@ -4373,7 +4373,7 @@ 2566039445U, // <5,u,6,2>: Cost 3 vext1 <2,5,u,6>, <2,5,u,6> 2687129808U, // <5,u,6,3>: Cost 3 vext3 <0,4,1,5>, 2566040886U, // <5,u,6,4>: Cost 3 vext1 <2,5,u,6>, RHS - 2713966815U, // <5,u,6,5>: Cost 3 vext3 <4,u,5,5>, + 2920044698U, // <5,u,6,5>: Cost 3 vzipl <5,6,7,0>, RHS 2846289268U, // <5,u,6,6>: Cost 3 vuzpr RHS, <4,6,4,6> 2973781320U, // <5,u,6,7>: Cost 3 vzipr <3,4,5,6>, RHS 2687129853U, // <5,u,6,u>: Cost 3 vext3 <0,4,1,5>, @@ -4383,7 +4383,7 @@ 2040971933U, // <5,u,7,3>: Cost 2 vtrnr RHS, LHS 430509384U, // <5,u,7,4>: Cost 1 vext1 RHS, RHS 1504251600U, // <5,u,7,5>: Cost 2 vext1 RHS, <5,1,7,3> - 1504252410U, // <5,u,7,6>: Cost 2 vext1 RHS, <6,2,7,3> + 118708378U, // <5,u,7,6>: Cost 1 vrev RHS 2040974889U, // <5,u,7,7>: Cost 2 vtrnr RHS, RHS 430511918U, // <5,u,7,u>: Cost 1 vext1 RHS, LHS 430514278U, // <5,u,u,0>: Cost 1 vext1 RHS, LHS @@ -4392,7 +4392,7 @@ 1772544669U, // <5,u,u,3>: Cost 2 vuzpr RHS, LHS 430517577U, // <5,u,u,4>: Cost 1 vext1 RHS, RHS 229035318U, // <5,u,u,5>: Cost 1 vdup1 RHS - 1613388173U, // <5,u,u,6>: Cost 2 vext3 <0,4,1,5>, RHS + 118716571U, // <5,u,u,6>: Cost 1 vrev RHS 1772547625U, // <5,u,u,7>: Cost 2 vuzpr RHS, RHS 430520110U, // <5,u,u,u>: Cost 1 vext1 RHS, LHS 2686025728U, // <6,0,0,0>: Cost 3 vext3 <0,2,4,6>, <0,0,0,0> @@ -4401,17 +4401,17 @@ 3779084320U, // <6,0,0,3>: Cost 4 vext3 <3,4,5,6>, <0,0,3,5> 2642903388U, // <6,0,0,4>: Cost 3 vext2 <4,2,6,0>, <0,4,2,6> 3657723939U, // <6,0,0,5>: Cost 4 vext1 <5,6,0,0>, <5,6,0,0> - 3706028556U, // <6,0,0,6>: Cost 4 vext2 <2,4,6,0>, <0,6,4,2> + 3926676514U, // <6,0,0,6>: Cost 4 vuzpr <5,6,7,0>, <7,0,5,6> 3926675786U, // <6,0,0,7>: Cost 4 vuzpr <5,6,7,0>, <6,0,5,7> 2686025802U, // <6,0,0,u>: Cost 3 vext3 <0,2,4,6>, <0,0,u,2> 2566070374U, // <6,0,1,0>: Cost 3 vext1 <2,6,0,1>, LHS - 3759767643U, // <6,0,1,1>: Cost 4 vext3 <0,2,4,6>, <0,1,1,1> + 3759767642U, // <6,0,1,1>: Cost 4 vext3 <0,2,4,6>, <0,1,1,0> 1612284006U, // <6,0,1,2>: Cost 2 vext3 <0,2,4,6>, LHS 2583988738U, // <6,0,1,3>: Cost 3 vext1 <5,6,0,1>, <3,4,5,6> 2566073654U, // <6,0,1,4>: Cost 3 vext1 <2,6,0,1>, RHS 2583990308U, // <6,0,1,5>: Cost 3 vext1 <5,6,0,1>, <5,6,0,1> 2589963005U, // <6,0,1,6>: Cost 3 vext1 <6,6,0,1>, <6,6,0,1> - 3651761146U, // <6,0,1,7>: Cost 4 vext1 <4,6,0,1>, <7,0,1,2> + 2595935702U, // <6,0,1,7>: Cost 3 vext1 <7,6,0,1>, <7,6,0,1> 1612284060U, // <6,0,1,u>: Cost 2 vext3 <0,2,4,6>, LHS 2686025892U, // <6,0,2,0>: Cost 3 vext3 <0,2,4,6>, <0,2,0,2> 2685804721U, // <6,0,2,1>: Cost 3 vext3 <0,2,1,6>, <0,2,1,6> @@ -4430,21 +4430,21 @@ 3718638154U, // <6,0,3,5>: Cost 4 vext2 <4,5,6,0>, <3,5,4,6> 3729918619U, // <6,0,3,6>: Cost 4 vext2 <6,4,6,0>, <3,6,4,6> 3926672384U, // <6,0,3,7>: Cost 4 vuzpr <5,6,7,0>, <1,3,5,7> - 2705342783U, // <6,0,3,u>: Cost 3 vext3 <3,4,5,6>, <0,3,u,4> + 2705342784U, // <6,0,3,u>: Cost 3 vext3 <3,4,5,6>, <0,3,u,5> 2687058250U, // <6,0,4,0>: Cost 3 vext3 <0,4,0,6>, <0,4,0,6> 2686026066U, // <6,0,4,1>: Cost 3 vext3 <0,2,4,6>, <0,4,1,5> 1613463900U, // <6,0,4,2>: Cost 2 vext3 <0,4,2,6>, <0,4,2,6> - 2235214293U, // <6,0,4,3>: Cost 3 vrev <3,4,0,6> + 3761021285U, // <6,0,4,3>: Cost 4 vext3 <0,4,3,6>, <0,4,3,6> 2687353198U, // <6,0,4,4>: Cost 3 vext3 <0,4,4,6>, <0,4,4,6> 2632289590U, // <6,0,4,5>: Cost 3 vext2 <2,4,6,0>, RHS 2645560704U, // <6,0,4,6>: Cost 3 vext2 <4,6,6,0>, <4,6,6,0> - 2259105081U, // <6,0,4,7>: Cost 3 vrev <7,4,0,6> + 2646224337U, // <6,0,4,7>: Cost 3 vext2 <4,7,6,0>, <4,7,6,0> 1613906322U, // <6,0,4,u>: Cost 2 vext3 <0,4,u,6>, <0,4,u,6> - 3721293427U, // <6,0,5,0>: Cost 4 vext2 <5,0,6,0>, <5,0,6,0> + 3651788902U, // <6,0,5,0>: Cost 4 vext1 <4,6,0,5>, LHS 2687795620U, // <6,0,5,1>: Cost 3 vext3 <0,5,1,6>, <0,5,1,6> 3761611181U, // <6,0,5,2>: Cost 4 vext3 <0,5,2,6>, <0,5,2,6> 3723284326U, // <6,0,5,3>: Cost 4 vext2 <5,3,6,0>, <5,3,6,0> - 3791028669U, // <6,0,5,4>: Cost 4 vext3 <5,4,5,6>, <0,5,4,4> + 2646224838U, // <6,0,5,4>: Cost 3 vext2 <4,7,6,0>, <5,4,7,6> 3718639630U, // <6,0,5,5>: Cost 4 vext2 <4,5,6,0>, <5,5,6,6> 2652196962U, // <6,0,5,6>: Cost 3 vext2 <5,7,6,0>, <5,6,7,0> 2852932918U, // <6,0,5,7>: Cost 3 vuzpr <5,6,7,0>, RHS @@ -4454,7 +4454,7 @@ 3060203622U, // <6,0,6,2>: Cost 3 vtrnl <6,6,6,6>, LHS 3718640178U, // <6,0,6,3>: Cost 4 vext2 <4,5,6,0>, <6,3,4,5> 2656178832U, // <6,0,6,4>: Cost 3 vext2 <6,4,6,0>, <6,4,6,0> - 3718640338U, // <6,0,6,5>: Cost 4 vext2 <4,5,6,0>, <6,5,4,3> + 3725939378U, // <6,0,6,5>: Cost 4 vext2 <5,7,6,0>, <6,5,0,7> 2657506098U, // <6,0,6,6>: Cost 3 vext2 <6,6,6,0>, <6,6,6,0> 2619020110U, // <6,0,6,7>: Cost 3 vext2 <0,2,6,0>, <6,7,0,1> 2925986461U, // <6,0,6,u>: Cost 3 vzipl <6,6,6,6>, LHS @@ -4463,9 +4463,9 @@ 2980495524U, // <6,0,7,2>: Cost 3 vzipr RHS, <0,2,0,2> 2572094072U, // <6,0,7,3>: Cost 3 vext1 <3,6,0,7>, <3,6,0,7> 2572094774U, // <6,0,7,4>: Cost 3 vext1 <3,6,0,7>, RHS - 4054239700U, // <6,0,7,5>: Cost 4 vzipr RHS, <3,4,0,5> + 4054238242U, // <6,0,7,5>: Cost 4 vzipr RHS, <1,4,0,5> 3645837653U, // <6,0,7,6>: Cost 4 vext1 <3,6,0,7>, <6,0,7,0> - 3645838376U, // <6,0,7,7>: Cost 4 vext1 <3,6,0,7>, <7,0,6,3> + 4054239054U, // <6,0,7,7>: Cost 4 vzipr RHS, <2,5,0,7> 2572097326U, // <6,0,7,u>: Cost 3 vext1 <3,6,0,7>, LHS 2686026378U, // <6,0,u,0>: Cost 3 vext3 <0,2,4,6>, <0,u,0,2> 2686026386U, // <6,0,u,1>: Cost 3 vext3 <0,2,4,6>, <0,u,1,1> @@ -4476,15 +4476,15 @@ 2590020356U, // <6,0,u,6>: Cost 3 vext1 <6,6,0,u>, <6,6,0,u> 2852933161U, // <6,0,u,7>: Cost 3 vuzpr <5,6,7,0>, RHS 1612284627U, // <6,0,u,u>: Cost 2 vext3 <0,2,4,6>, LHS - 2641584138U, // <6,1,0,0>: Cost 3 vext2 <4,0,6,1>, <0,0,1,1> + 2595995750U, // <6,1,0,0>: Cost 3 vext1 <7,6,1,0>, LHS 2646229094U, // <6,1,0,1>: Cost 3 vext2 <4,7,6,1>, LHS 3694092492U, // <6,1,0,2>: Cost 4 vext2 <0,4,6,1>, <0,2,4,6> - 3121365094U, // <6,1,0,3>: Cost 3 vtrnr <5,6,7,0>, LHS - 3694092667U, // <6,1,0,4>: Cost 4 vext2 <0,4,6,1>, <0,4,6,1> + 2686026486U, // <6,1,0,3>: Cost 3 vext3 <0,2,4,6>, <1,0,3,2> + 2595999030U, // <6,1,0,4>: Cost 3 vext1 <7,6,1,0>, RHS 3767730952U, // <6,1,0,5>: Cost 4 vext3 <1,5,4,6>, <1,0,5,2> - 3696747007U, // <6,1,0,6>: Cost 4 vext2 <0,u,6,1>, <0,6,2,7> - 2256524286U, // <6,1,0,7>: Cost 3 vrev <7,0,1,6> - 2646229661U, // <6,1,0,u>: Cost 3 vext2 <4,7,6,1>, LHS + 2596000590U, // <6,1,0,6>: Cost 3 vext1 <7,6,1,0>, <6,7,0,1> + 2596001246U, // <6,1,0,7>: Cost 3 vext1 <7,6,1,0>, <7,6,1,0> + 2686026531U, // <6,1,0,u>: Cost 3 vext3 <0,2,4,6>, <1,0,u,2> 3763602219U, // <6,1,1,0>: Cost 4 vext3 <0,u,2,6>, <1,1,0,1> 2686026548U, // <6,1,1,1>: Cost 3 vext3 <0,2,4,6>, <1,1,1,1> 3764929346U, // <6,1,1,2>: Cost 4 vext3 <1,1,2,6>, <1,1,2,6> @@ -4492,7 +4492,7 @@ 2691334996U, // <6,1,1,4>: Cost 3 vext3 <1,1,4,6>, <1,1,4,6> 3760874332U, // <6,1,1,5>: Cost 4 vext3 <0,4,1,6>, <1,1,5,5> 3765224294U, // <6,1,1,6>: Cost 4 vext3 <1,1,6,6>, <1,1,6,6> - 3330929743U, // <6,1,1,7>: Cost 4 vrev <7,1,1,6> + 3669751263U, // <6,1,1,7>: Cost 4 vext1 <7,6,1,1>, <7,6,1,1> 2686026613U, // <6,1,1,u>: Cost 3 vext3 <0,2,4,6>, <1,1,u,3> 2554208358U, // <6,1,2,0>: Cost 3 vext1 <0,6,1,2>, LHS 3763602311U, // <6,1,2,1>: Cost 4 vext3 <0,u,2,6>, <1,2,1,3> @@ -4501,7 +4501,7 @@ 2554211638U, // <6,1,2,4>: Cost 3 vext1 <0,6,1,2>, RHS 3760874411U, // <6,1,2,5>: Cost 4 vext3 <0,4,1,6>, <1,2,5,3> 2554212858U, // <6,1,2,6>: Cost 3 vext1 <0,6,1,2>, <6,2,7,3> - 3331593376U, // <6,1,2,7>: Cost 4 vrev <7,2,1,6> + 3802973114U, // <6,1,2,7>: Cost 4 vext3 <7,4,5,6>, <1,2,7,0> 2686026691U, // <6,1,2,u>: Cost 3 vext3 <0,2,4,6>, <1,2,u,0> 2566160486U, // <6,1,3,0>: Cost 3 vext1 <2,6,1,3>, LHS 2686026712U, // <6,1,3,1>: Cost 3 vext3 <0,2,4,6>, <1,3,1,3> @@ -4555,27 +4555,27 @@ 2687206795U, // <6,1,u,4>: Cost 3 vext3 <0,4,2,6>, <1,u,4,6> 2686027157U, // <6,1,u,5>: Cost 3 vext3 <0,2,4,6>, <1,u,5,7> 2590094093U, // <6,1,u,6>: Cost 3 vext1 <6,6,1,u>, <6,6,1,u> - 2261833350U, // <6,1,u,7>: Cost 3 vrev <7,u,1,6> + 2596066790U, // <6,1,u,7>: Cost 3 vext1 <7,6,1,u>, <7,6,1,u> 2686027177U, // <6,1,u,u>: Cost 3 vext3 <0,2,4,6>, <1,u,u,0> - 2578153574U, // <6,2,0,0>: Cost 3 vext1 <4,6,2,0>, LHS + 2646900736U, // <6,2,0,0>: Cost 3 vext2 <4,u,6,2>, <0,0,0,0> 1573159014U, // <6,2,0,1>: Cost 2 vext2 <4,u,6,2>, LHS - 2578155174U, // <6,2,0,2>: Cost 3 vext1 <4,6,2,0>, <2,3,0,1> + 2646900900U, // <6,2,0,2>: Cost 3 vext2 <4,u,6,2>, <0,2,0,2> 3759769037U, // <6,2,0,3>: Cost 4 vext3 <0,2,4,6>, <2,0,3,0> - 2578156854U, // <6,2,0,4>: Cost 3 vext1 <4,6,2,0>, RHS - 3779085798U, // <6,2,0,5>: Cost 4 vext3 <3,4,5,6>, <2,0,5,7> - 2554270542U, // <6,2,0,6>: Cost 3 vext1 <0,6,2,0>, <6,7,0,1> - 3651900410U, // <6,2,0,7>: Cost 4 vext1 <4,6,2,0>, <7,0,1,2> + 2641592668U, // <6,2,0,4>: Cost 3 vext2 <4,0,6,2>, <0,4,2,6> + 3779085794U, // <6,2,0,5>: Cost 4 vext3 <3,4,5,6>, <2,0,5,3> + 2686027244U, // <6,2,0,6>: Cost 3 vext3 <0,2,4,6>, <2,0,6,4> + 3669816807U, // <6,2,0,7>: Cost 4 vext1 <7,6,2,0>, <7,6,2,0> 1573159581U, // <6,2,0,u>: Cost 2 vext2 <4,u,6,2>, LHS - 3777021446U, // <6,2,1,0>: Cost 4 vext3 <3,1,4,6>, <2,1,0,3> + 2230527897U, // <6,2,1,0>: Cost 3 vrev <2,6,0,1> 2646901556U, // <6,2,1,1>: Cost 3 vext2 <4,u,6,2>, <1,1,1,1> 2646901654U, // <6,2,1,2>: Cost 3 vext2 <4,u,6,2>, <1,2,3,0> 2847047782U, // <6,2,1,3>: Cost 3 vuzpr <4,6,u,2>, LHS 3771049517U, // <6,2,1,4>: Cost 4 vext3 <2,1,4,6>, <2,1,4,6> 2646901904U, // <6,2,1,5>: Cost 3 vext2 <4,u,6,2>, <1,5,3,7> 2686027324U, // <6,2,1,6>: Cost 3 vext3 <0,2,4,6>, <2,1,6,3> - 3331003480U, // <6,2,1,7>: Cost 4 vrev <7,1,2,6> - 2847047787U, // <6,2,1,u>: Cost 3 vuzpr <4,6,u,2>, LHS - 3289858234U, // <6,2,2,0>: Cost 4 vrev <0,2,2,6> + 3669825000U, // <6,2,1,7>: Cost 4 vext1 <7,6,2,1>, <7,6,2,1> + 2231117793U, // <6,2,1,u>: Cost 3 vrev <2,6,u,1> + 3763603029U, // <6,2,2,0>: Cost 4 vext3 <0,u,2,6>, <2,2,0,1> 3759769184U, // <6,2,2,1>: Cost 4 vext3 <0,2,4,6>, <2,2,1,3> 2686027368U, // <6,2,2,2>: Cost 3 vext3 <0,2,4,6>, <2,2,2,2> 2686027378U, // <6,2,2,3>: Cost 3 vext3 <0,2,4,6>, <2,2,3,3> @@ -4585,13 +4585,13 @@ 3920794092U, // <6,2,2,7>: Cost 4 vuzpr <4,6,u,2>, <6,2,5,7> 2686027423U, // <6,2,2,u>: Cost 3 vext3 <0,2,4,6>, <2,2,u,3> 2686027430U, // <6,2,3,0>: Cost 3 vext3 <0,2,4,6>, <2,3,0,1> - 3759769263U, // <6,2,3,1>: Cost 4 vext3 <0,2,4,6>, <2,3,1,1> - 2228725437U, // <6,2,3,2>: Cost 3 vrev <2,3,2,6> + 3759769262U, // <6,2,3,1>: Cost 4 vext3 <0,2,4,6>, <2,3,1,0> + 2698487485U, // <6,2,3,2>: Cost 3 vext3 <2,3,2,6>, <2,3,2,6> 2705344196U, // <6,2,3,3>: Cost 3 vext3 <3,4,5,6>, <2,3,3,4> 2686027470U, // <6,2,3,4>: Cost 3 vext3 <0,2,4,6>, <2,3,4,5> 2698708696U, // <6,2,3,5>: Cost 3 vext3 <2,3,5,6>, <2,3,5,6> 2724660961U, // <6,2,3,6>: Cost 3 vext3 <6,6,6,6>, <2,3,6,6> - 2698856170U, // <6,2,3,7>: Cost 3 vext3 <2,3,7,6>, <2,3,7,6> + 2729232104U, // <6,2,3,7>: Cost 3 vext3 <7,4,5,6>, <2,3,7,4> 2686027502U, // <6,2,3,u>: Cost 3 vext3 <0,2,4,6>, <2,3,u,1> 1567853468U, // <6,2,4,0>: Cost 2 vext2 <4,0,6,2>, <4,0,6,2> 3759769351U, // <6,2,4,1>: Cost 4 vext3 <0,2,4,6>, <2,4,1,u> @@ -4606,7 +4606,7 @@ 2646904528U, // <6,2,5,1>: Cost 3 vext2 <4,u,6,2>, <5,1,7,3> 3759769440U, // <6,2,5,2>: Cost 4 vext3 <0,2,4,6>, <2,5,2,7> 2699888488U, // <6,2,5,3>: Cost 3 vext3 <2,5,3,6>, <2,5,3,6> - 3759769458U, // <6,2,5,4>: Cost 4 vext3 <0,2,4,6>, <2,5,4,7> + 2230855617U, // <6,2,5,4>: Cost 3 vrev <2,6,4,5> 2646904836U, // <6,2,5,5>: Cost 3 vext2 <4,u,6,2>, <5,5,5,5> 2646904930U, // <6,2,5,6>: Cost 3 vext2 <4,u,6,2>, <5,6,7,0> 2847051062U, // <6,2,5,7>: Cost 3 vuzpr <4,6,u,2>, RHS @@ -4621,17 +4621,17 @@ 2646905678U, // <6,2,6,7>: Cost 3 vext2 <4,u,6,2>, <6,7,0,1> 2686027751U, // <6,2,6,u>: Cost 3 vext3 <0,2,4,6>, <2,6,u,7> 2554323046U, // <6,2,7,0>: Cost 3 vext1 <0,6,2,7>, LHS - 2560296152U, // <6,2,7,1>: Cost 3 vext1 <1,6,2,7>, <1,6,2,7> + 2572239606U, // <6,2,7,1>: Cost 3 vext1 <3,6,2,7>, <1,0,3,2> 2566268849U, // <6,2,7,2>: Cost 3 vext1 <2,6,2,7>, <2,6,2,7> 1906753638U, // <6,2,7,3>: Cost 2 vzipr RHS, LHS 2554326326U, // <6,2,7,4>: Cost 3 vext1 <0,6,2,7>, RHS - 4054237288U, // <6,2,7,5>: Cost 4 vzipr RHS, <0,1,2,5> + 3304687564U, // <6,2,7,5>: Cost 4 vrev <2,6,5,7> 2980495708U, // <6,2,7,6>: Cost 3 vzipr RHS, <0,4,2,6> 2646906476U, // <6,2,7,7>: Cost 3 vext2 <4,u,6,2>, <7,7,7,7> 1906753643U, // <6,2,7,u>: Cost 2 vzipr RHS, LHS 1591744256U, // <6,2,u,0>: Cost 2 vext2 , 1573164846U, // <6,2,u,1>: Cost 2 vext2 <4,u,6,2>, LHS - 2232043602U, // <6,2,u,2>: Cost 3 vrev <2,u,2,6> + 2701805650U, // <6,2,u,2>: Cost 3 vext3 <2,u,2,6>, <2,u,2,6> 1906761830U, // <6,2,u,3>: Cost 2 vzipr RHS, LHS 2686027875U, // <6,2,u,4>: Cost 3 vext3 <0,2,4,6>, <2,u,4,5> 1573165210U, // <6,2,u,5>: Cost 2 vext2 <4,u,6,2>, RHS @@ -4645,33 +4645,33 @@ 2687207601U, // <6,3,0,4>: Cost 3 vext3 <0,4,2,6>, <3,0,4,2> 2705344698U, // <6,3,0,5>: Cost 3 vext3 <3,4,5,6>, <3,0,5,2> 3663917847U, // <6,3,0,6>: Cost 4 vext1 <6,6,3,0>, <6,6,3,0> - 4195107840U, // <6,3,0,7>: Cost 4 vtrnr <5,6,7,0>, <1,3,5,7> + 2237008560U, // <6,3,0,7>: Cost 3 vrev <3,6,7,0> 2686027989U, // <6,3,0,u>: Cost 3 vext3 <0,2,4,6>, <3,0,u,2> - 2602123366U, // <6,3,1,0>: Cost 3 vext1 , LHS + 3759769823U, // <6,3,1,0>: Cost 4 vext3 <0,2,4,6>, <3,1,0,3> 3759769830U, // <6,3,1,1>: Cost 4 vext3 <0,2,4,6>, <3,1,1,1> 3759769841U, // <6,3,1,2>: Cost 4 vext3 <0,2,4,6>, <3,1,2,3> - 2602125462U, // <6,3,1,3>: Cost 3 vext1 , <3,0,1,2> + 3759769848U, // <6,3,1,3>: Cost 4 vext3 <0,2,4,6>, <3,1,3,1> 2703280390U, // <6,3,1,4>: Cost 3 vext3 <3,1,4,6>, <3,1,4,6> 3759769868U, // <6,3,1,5>: Cost 4 vext3 <0,2,4,6>, <3,1,5,3> 3704063194U, // <6,3,1,6>: Cost 4 vext2 <2,1,6,3>, <1,6,3,0> 3767732510U, // <6,3,1,7>: Cost 4 vext3 <1,5,4,6>, <3,1,7,3> - 2602129198U, // <6,3,1,u>: Cost 3 vext1 , LHS - 3640041574U, // <6,3,2,0>: Cost 4 vext1 <2,6,3,2>, LHS - 2686028086U, // <6,3,2,1>: Cost 3 vext3 <0,2,4,6>, <3,2,1,0> + 2703280390U, // <6,3,1,u>: Cost 3 vext3 <3,1,4,6>, <3,1,4,6> + 3704063468U, // <6,3,2,0>: Cost 4 vext2 <2,1,6,3>, <2,0,6,4> + 2630321724U, // <6,3,2,1>: Cost 3 vext2 <2,1,6,3>, <2,1,6,3> 3759769921U, // <6,3,2,2>: Cost 4 vext3 <0,2,4,6>, <3,2,2,2> 3759769928U, // <6,3,2,3>: Cost 4 vext3 <0,2,4,6>, <3,2,3,0> 3704063767U, // <6,3,2,4>: Cost 4 vext2 <2,1,6,3>, <2,4,3,6> 3704063876U, // <6,3,2,5>: Cost 4 vext2 <2,1,6,3>, <2,5,6,7> 2636957626U, // <6,3,2,6>: Cost 3 vext2 <3,2,6,3>, <2,6,3,7> - 3708045346U, // <6,3,2,7>: Cost 4 vext2 <2,7,6,3>, <2,7,6,3> - 2689862005U, // <6,3,2,u>: Cost 3 vext3 <0,u,2,6>, <3,2,u,0> + 3777907058U, // <6,3,2,7>: Cost 4 vext3 <3,2,7,6>, <3,2,7,6> + 2630321724U, // <6,3,2,u>: Cost 3 vext2 <2,1,6,3>, <2,1,6,3> 3759769983U, // <6,3,3,0>: Cost 4 vext3 <0,2,4,6>, <3,3,0,1> 3710036245U, // <6,3,3,1>: Cost 4 vext2 <3,1,6,3>, <3,1,6,3> 2636958054U, // <6,3,3,2>: Cost 3 vext2 <3,2,6,3>, <3,2,6,3> 2686028188U, // <6,3,3,3>: Cost 3 vext3 <0,2,4,6>, <3,3,3,3> 2704607656U, // <6,3,3,4>: Cost 3 vext3 <3,3,4,6>, <3,3,4,6> 3773041072U, // <6,3,3,5>: Cost 4 vext3 <2,4,4,6>, <3,3,5,5> - 3710700166U, // <6,3,3,6>: Cost 4 vext2 <3,2,6,3>, <3,6,2,3> + 3711363731U, // <6,3,3,6>: Cost 4 vext2 <3,3,6,3>, <3,6,3,7> 3767732676U, // <6,3,3,7>: Cost 4 vext3 <1,5,4,6>, <3,3,7,7> 2707999179U, // <6,3,3,u>: Cost 3 vext3 <3,u,5,6>, <3,3,u,5> 2584232038U, // <6,3,4,0>: Cost 3 vext1 <5,6,3,4>, LHS @@ -4681,11 +4681,11 @@ 2584235318U, // <6,3,4,4>: Cost 3 vext1 <5,6,3,4>, RHS 1631603202U, // <6,3,4,5>: Cost 2 vext3 <3,4,5,6>, <3,4,5,6> 2654211444U, // <6,3,4,6>: Cost 3 vext2 <6,1,6,3>, <4,6,4,6> - 3779234324U, // <6,3,4,7>: Cost 4 vext3 <3,4,7,6>, <3,4,7,6> + 2237041332U, // <6,3,4,7>: Cost 3 vrev <3,6,7,4> 1631824413U, // <6,3,4,u>: Cost 2 vext3 <3,4,u,6>, <3,4,u,6> 3640066150U, // <6,3,5,0>: Cost 4 vext1 <2,6,3,5>, LHS 3772746288U, // <6,3,5,1>: Cost 4 vext3 <2,4,0,6>, <3,5,1,7> - 3303868264U, // <6,3,5,2>: Cost 4 vrev <2,5,3,6> + 3640067790U, // <6,3,5,2>: Cost 4 vext1 <2,6,3,5>, <2,3,4,5> 3773041216U, // <6,3,5,3>: Cost 4 vext3 <2,4,4,6>, <3,5,3,5> 2705934922U, // <6,3,5,4>: Cost 3 vext3 <3,5,4,6>, <3,5,4,6> 3773041236U, // <6,3,5,5>: Cost 4 vext3 <2,4,4,6>, <3,5,5,7> @@ -4695,7 +4695,7 @@ 2602164326U, // <6,3,6,0>: Cost 3 vext1 , LHS 2654212512U, // <6,3,6,1>: Cost 3 vext2 <6,1,6,3>, <6,1,6,3> 2566334393U, // <6,3,6,2>: Cost 3 vext1 <2,6,3,6>, <2,6,3,6> - 3773631120U, // <6,3,6,3>: Cost 4 vext3 <2,5,3,6>, <3,6,3,4> + 3704066588U, // <6,3,6,3>: Cost 4 vext2 <2,1,6,3>, <6,3,2,1> 2602167524U, // <6,3,6,4>: Cost 3 vext1 , <4,4,6,6> 3710702321U, // <6,3,6,5>: Cost 4 vext2 <3,2,6,3>, <6,5,7,7> 2724661933U, // <6,3,6,6>: Cost 3 vext3 <6,6,6,6>, <3,6,6,6> @@ -4707,11 +4707,11 @@ 2566342806U, // <6,3,7,3>: Cost 3 vext1 <2,6,3,7>, <3,0,1,2> 1492602166U, // <6,3,7,4>: Cost 2 vext1 <2,6,3,7>, RHS 2602176208U, // <6,3,7,5>: Cost 3 vext1 , <5,1,7,3> - 2566345288U, // <6,3,7,6>: Cost 3 vext1 <2,6,3,7>, <6,3,7,0> - 2566346010U, // <6,3,7,7>: Cost 3 vext1 <2,6,3,7>, <7,3,6,2> + 2566345210U, // <6,3,7,6>: Cost 3 vext1 <2,6,3,7>, <6,2,7,3> + 2980496528U, // <6,3,7,7>: Cost 3 vzipr RHS, <1,5,3,7> 1492604718U, // <6,3,7,u>: Cost 2 vext1 <2,6,3,7>, LHS 1492607078U, // <6,3,u,0>: Cost 2 vext1 <2,6,3,u>, LHS - 2686028572U, // <6,3,u,1>: Cost 3 vext3 <0,2,4,6>, <3,u,1,0> + 2686028574U, // <6,3,u,1>: Cost 3 vext3 <0,2,4,6>, <3,u,1,2> 1492608955U, // <6,3,u,2>: Cost 2 vext1 <2,6,3,u>, <2,6,3,u> 2566350998U, // <6,3,u,3>: Cost 3 vext1 <2,6,3,u>, <3,0,1,2> 1492610358U, // <6,3,u,4>: Cost 2 vext1 <2,6,3,u>, RHS @@ -4719,50 +4719,50 @@ 2566353489U, // <6,3,u,6>: Cost 3 vext1 <2,6,3,u>, <6,3,u,0> 2980504720U, // <6,3,u,7>: Cost 3 vzipr RHS, <1,5,3,7> 1492612910U, // <6,3,u,u>: Cost 2 vext1 <2,6,3,u>, LHS - 3703406614U, // <6,4,0,0>: Cost 4 vext2 <2,0,6,4>, <0,0,2,4> - 2632319078U, // <6,4,0,1>: Cost 3 vext2 <2,4,6,4>, LHS - 2632319180U, // <6,4,0,2>: Cost 3 vext2 <2,4,6,4>, <0,2,4,6> + 3703406592U, // <6,4,0,0>: Cost 4 vext2 <2,0,6,4>, <0,0,0,0> + 2629664870U, // <6,4,0,1>: Cost 3 vext2 <2,0,6,4>, LHS + 2629664972U, // <6,4,0,2>: Cost 3 vext2 <2,0,6,4>, <0,2,4,6> 3779087232U, // <6,4,0,3>: Cost 4 vext3 <3,4,5,6>, <4,0,3,1> 2642936156U, // <6,4,0,4>: Cost 3 vext2 <4,2,6,4>, <0,4,2,6> 2712570770U, // <6,4,0,5>: Cost 3 vext3 <4,6,4,6>, <4,0,5,1> - 2712570780U, // <6,4,0,6>: Cost 3 vext3 <4,6,4,6>, <4,0,6,2> - 3330487321U, // <6,4,0,7>: Cost 4 vrev <7,0,4,6> - 2632319645U, // <6,4,0,u>: Cost 3 vext2 <2,4,6,4>, LHS - 3628163174U, // <6,4,1,0>: Cost 4 vext1 <0,6,4,1>, LHS - 3295314772U, // <6,4,1,1>: Cost 4 vrev <1,1,4,6> - 3706061718U, // <6,4,1,2>: Cost 4 vext2 <2,4,6,4>, <1,2,3,0> + 2687208348U, // <6,4,0,6>: Cost 3 vext3 <0,4,2,6>, <4,0,6,2> + 3316723081U, // <6,4,0,7>: Cost 4 vrev <4,6,7,0> + 2629665437U, // <6,4,0,u>: Cost 3 vext2 <2,0,6,4>, LHS + 2242473291U, // <6,4,1,0>: Cost 3 vrev <4,6,0,1> + 3700089652U, // <6,4,1,1>: Cost 4 vext2 <1,4,6,4>, <1,1,1,1> + 3703407510U, // <6,4,1,2>: Cost 4 vext2 <2,0,6,4>, <1,2,3,0> 2852962406U, // <6,4,1,3>: Cost 3 vuzpr <5,6,7,4>, LHS 3628166454U, // <6,4,1,4>: Cost 4 vext1 <0,6,4,1>, RHS 3760876514U, // <6,4,1,5>: Cost 4 vext3 <0,4,1,6>, <4,1,5,0> 2687208430U, // <6,4,1,6>: Cost 3 vext3 <0,4,2,6>, <4,1,6,3> - 3331150954U, // <6,4,1,7>: Cost 4 vrev <7,1,4,6> - 2852962411U, // <6,4,1,u>: Cost 3 vuzpr <5,6,7,4>, LHS - 2216263884U, // <6,4,2,0>: Cost 3 vrev <0,2,4,6> - 3704071741U, // <6,4,2,1>: Cost 4 vext2 <2,1,6,4>, <2,1,6,4> - 3301951102U, // <6,4,2,2>: Cost 4 vrev <2,2,4,6> - 3705399007U, // <6,4,2,3>: Cost 4 vext2 <2,3,6,4>, <2,3,6,4> + 3316731274U, // <6,4,1,7>: Cost 4 vrev <4,6,7,1> + 2243063187U, // <6,4,1,u>: Cost 3 vrev <4,6,u,1> + 2629666284U, // <6,4,2,0>: Cost 3 vext2 <2,0,6,4>, <2,0,6,4> + 3703408188U, // <6,4,2,1>: Cost 4 vext2 <2,0,6,4>, <2,1,6,3> + 3703408232U, // <6,4,2,2>: Cost 4 vext2 <2,0,6,4>, <2,2,2,2> + 3703408294U, // <6,4,2,3>: Cost 4 vext2 <2,0,6,4>, <2,3,0,1> 2632320816U, // <6,4,2,4>: Cost 3 vext2 <2,4,6,4>, <2,4,6,4> 2923384118U, // <6,4,2,5>: Cost 3 vzipl <6,2,7,3>, RHS 2687208508U, // <6,4,2,6>: Cost 3 vext3 <0,4,2,6>, <4,2,6,0> - 3331814587U, // <6,4,2,7>: Cost 4 vrev <7,2,4,6> + 3760950341U, // <6,4,2,7>: Cost 4 vext3 <0,4,2,6>, <4,2,7,0> 2634975348U, // <6,4,2,u>: Cost 3 vext2 <2,u,6,4>, <2,u,6,4> - 3706062998U, // <6,4,3,0>: Cost 4 vext2 <2,4,6,4>, <3,0,1,2> - 3296642038U, // <6,4,3,1>: Cost 4 vrev <1,3,4,6> - 2228872911U, // <6,4,3,2>: Cost 3 vrev <2,3,4,6> - 3706063260U, // <6,4,3,3>: Cost 4 vext2 <2,4,6,4>, <3,3,3,3> + 3703408790U, // <6,4,3,0>: Cost 4 vext2 <2,0,6,4>, <3,0,1,2> + 3316305238U, // <6,4,3,1>: Cost 4 vrev <4,6,1,3> + 3703408947U, // <6,4,3,2>: Cost 4 vext2 <2,0,6,4>, <3,2,0,6> + 3703409052U, // <6,4,3,3>: Cost 4 vext2 <2,0,6,4>, <3,3,3,3> 2644929026U, // <6,4,3,4>: Cost 3 vext2 <4,5,6,4>, <3,4,5,6> 3718670922U, // <6,4,3,5>: Cost 4 vext2 <4,5,6,4>, <3,5,4,6> 2705345682U, // <6,4,3,6>: Cost 3 vext3 <3,4,5,6>, <4,3,6,5> 3926705152U, // <6,4,3,7>: Cost 4 vuzpr <5,6,7,4>, <1,3,5,7> - 2264709093U, // <6,4,3,u>: Cost 3 vrev + 2668817222U, // <6,4,3,u>: Cost 3 vext2 , <3,u,5,6> 2590277734U, // <6,4,4,0>: Cost 3 vext1 <6,6,4,4>, LHS 3716017135U, // <6,4,4,1>: Cost 4 vext2 <4,1,6,4>, <4,1,6,4> 2642938944U, // <6,4,4,2>: Cost 3 vext2 <4,2,6,4>, <4,2,6,4> - 2235509241U, // <6,4,4,3>: Cost 3 vrev <3,4,4,6> + 3717344401U, // <6,4,4,3>: Cost 4 vext2 <4,3,6,4>, <4,3,6,4> 2712571088U, // <6,4,4,4>: Cost 3 vext3 <4,6,4,6>, <4,4,4,4> - 2632322358U, // <6,4,4,5>: Cost 3 vext2 <2,4,6,4>, RHS + 2629668150U, // <6,4,4,5>: Cost 3 vext2 <2,0,6,4>, RHS 1637649636U, // <6,4,4,6>: Cost 2 vext3 <4,4,6,6>, <4,4,6,6> - 2259400029U, // <6,4,4,7>: Cost 3 vrev <7,4,4,6> + 2646257109U, // <6,4,4,7>: Cost 3 vext2 <4,7,6,4>, <4,7,6,4> 1637649636U, // <6,4,4,u>: Cost 2 vext3 <4,4,6,6>, <4,4,6,6> 2566398054U, // <6,4,5,0>: Cost 3 vext1 <2,6,4,5>, LHS 3760876805U, // <6,4,5,1>: Cost 4 vext3 <0,4,1,6>, <4,5,1,3> @@ -4774,7 +4774,7 @@ 2852965686U, // <6,4,5,7>: Cost 3 vuzpr <5,6,7,4>, RHS 1612287304U, // <6,4,5,u>: Cost 2 vext3 <0,2,4,6>, RHS 1504608358U, // <6,4,6,0>: Cost 2 vext1 <4,6,4,6>, LHS - 2578350900U, // <6,4,6,1>: Cost 3 vext1 <4,6,4,6>, <1,1,1,1> + 2578350838U, // <6,4,6,1>: Cost 3 vext1 <4,6,4,6>, <1,0,3,2> 2578351720U, // <6,4,6,2>: Cost 3 vext1 <4,6,4,6>, <2,2,2,2> 2578352278U, // <6,4,6,3>: Cost 3 vext1 <4,6,4,6>, <3,0,1,2> 1504611638U, // <6,4,6,4>: Cost 2 vext1 <4,6,4,6>, RHS @@ -4792,11 +4792,11 @@ 4054239090U, // <6,4,7,7>: Cost 4 vzipr RHS, <2,5,4,7> 2572392238U, // <6,4,7,u>: Cost 3 vext1 <3,6,4,7>, LHS 1504608358U, // <6,4,u,0>: Cost 2 vext1 <4,6,4,6>, LHS - 2632324910U, // <6,4,u,1>: Cost 3 vext2 <2,4,6,4>, LHS + 2629670702U, // <6,4,u,1>: Cost 3 vext2 <2,0,6,4>, LHS 2566424516U, // <6,4,u,2>: Cost 3 vext1 <2,6,4,u>, <2,6,4,u> 2584340994U, // <6,4,u,3>: Cost 3 vext1 <5,6,4,u>, <3,4,5,6> 1640156694U, // <6,4,u,4>: Cost 2 vext3 <4,u,4,6>, <4,u,4,6> - 2632325274U, // <6,4,u,5>: Cost 3 vext2 <2,4,6,4>, RHS + 2629671066U, // <6,4,u,5>: Cost 3 vext2 <2,0,6,4>, RHS 1612287529U, // <6,4,u,6>: Cost 2 vext3 <0,2,4,6>, RHS 2852965929U, // <6,4,u,7>: Cost 3 vuzpr <5,6,7,4>, RHS 1612287547U, // <6,4,u,u>: Cost 2 vext3 <0,2,4,6>, RHS @@ -4807,15 +4807,15 @@ 3760877154U, // <6,5,0,4>: Cost 4 vext3 <0,4,1,6>, <5,0,4,1> 4195110916U, // <6,5,0,5>: Cost 4 vtrnr <5,6,7,0>, <5,5,5,5> 3696779775U, // <6,5,0,6>: Cost 4 vext2 <0,u,6,5>, <0,6,2,7> - 3121368374U, // <6,5,0,7>: Cost 3 vtrnr <5,6,7,0>, RHS - 2634982045U, // <6,5,0,u>: Cost 3 vext2 <2,u,6,5>, LHS - 3652124774U, // <6,5,1,0>: Cost 4 vext1 <4,6,5,1>, LHS + 1175212130U, // <6,5,0,7>: Cost 2 vrev <5,6,7,0> + 1175285867U, // <6,5,0,u>: Cost 2 vrev <5,6,u,0> + 2248445988U, // <6,5,1,0>: Cost 3 vrev <5,6,0,1> 3698107237U, // <6,5,1,1>: Cost 4 vext2 <1,1,6,5>, <1,1,6,5> 3708724118U, // <6,5,1,2>: Cost 4 vext2 <2,u,6,5>, <1,2,3,0> - 2642281472U, // <6,5,1,3>: Cost 3 vext2 <4,1,6,5>, <1,3,5,7> - 3760877234U, // <6,5,1,4>: Cost 4 vext3 <0,4,1,6>, <5,1,4,0> + 3908575334U, // <6,5,1,3>: Cost 4 vuzpr <2,6,4,5>, LHS + 3716023376U, // <6,5,1,4>: Cost 4 vext2 <4,1,6,5>, <1,4,5,6> 3708724368U, // <6,5,1,5>: Cost 4 vext2 <2,u,6,5>, <1,5,3,7> - 3708724449U, // <6,5,1,6>: Cost 4 vext2 <2,u,6,5>, <1,6,3,7> + 3767733960U, // <6,5,1,6>: Cost 4 vext3 <1,5,4,6>, <5,1,6,4> 2712571600U, // <6,5,1,7>: Cost 3 vext3 <4,6,4,6>, <5,1,7,3> 2712571609U, // <6,5,1,u>: Cost 3 vext3 <4,6,4,6>, <5,1,u,3> 2578391142U, // <6,5,2,0>: Cost 3 vext1 <4,6,5,2>, LHS @@ -4823,30 +4823,30 @@ 3708724840U, // <6,5,2,2>: Cost 4 vext2 <2,u,6,5>, <2,2,2,2> 3705407182U, // <6,5,2,3>: Cost 4 vext2 <2,3,6,5>, <2,3,4,5> 2578394422U, // <6,5,2,4>: Cost 3 vext1 <4,6,5,2>, RHS - 3652136656U, // <6,5,2,5>: Cost 4 vext1 <4,6,5,2>, <5,1,7,3> + 3717351272U, // <6,5,2,5>: Cost 4 vext2 <4,3,6,5>, <2,5,3,6> 2634983354U, // <6,5,2,6>: Cost 3 vext2 <2,u,6,5>, <2,6,3,7> 3115486518U, // <6,5,2,7>: Cost 3 vtrnr <4,6,u,2>, RHS 2634983541U, // <6,5,2,u>: Cost 3 vext2 <2,u,6,5>, <2,u,6,5> 3708725398U, // <6,5,3,0>: Cost 4 vext2 <2,u,6,5>, <3,0,1,2> 3710052631U, // <6,5,3,1>: Cost 4 vext2 <3,1,6,5>, <3,1,6,5> - 2228946648U, // <6,5,3,2>: Cost 3 vrev <2,3,5,6> + 3708725606U, // <6,5,3,2>: Cost 4 vext2 <2,u,6,5>, <3,2,6,3> 3708725660U, // <6,5,3,3>: Cost 4 vext2 <2,u,6,5>, <3,3,3,3> 2643610114U, // <6,5,3,4>: Cost 3 vext2 <4,3,6,5>, <3,4,5,6> - 3696118365U, // <6,5,3,5>: Cost 4 vext2 <0,7,6,5>, <3,5,6,7> + 3717352010U, // <6,5,3,5>: Cost 4 vext2 <4,3,6,5>, <3,5,4,6> 3773632358U, // <6,5,3,6>: Cost 4 vext3 <2,5,3,6>, <5,3,6,0> - 2640292605U, // <6,5,3,7>: Cost 3 vext2 <3,7,6,5>, <3,7,6,5> - 2264782830U, // <6,5,3,u>: Cost 3 vrev - 1522581606U, // <6,5,4,0>: Cost 2 vext1 <7,6,5,4>, LHS - 2223637584U, // <6,5,4,1>: Cost 3 vrev <1,4,5,6> - 2229610281U, // <6,5,4,2>: Cost 3 vrev <2,4,5,6> - 1161841154U, // <6,5,4,3>: Cost 2 vrev <3,4,5,6> - 1522584886U, // <6,5,4,4>: Cost 2 vext1 <7,6,5,4>, RHS + 2248978533U, // <6,5,3,7>: Cost 3 vrev <5,6,7,3> + 2249052270U, // <6,5,3,u>: Cost 3 vrev <5,6,u,3> + 2596323430U, // <6,5,4,0>: Cost 3 vext1 <7,6,5,4>, LHS + 3716025328U, // <6,5,4,1>: Cost 4 vext2 <4,1,6,5>, <4,1,6,5> + 3716688961U, // <6,5,4,2>: Cost 4 vext2 <4,2,6,5>, <4,2,6,5> + 2643610770U, // <6,5,4,3>: Cost 3 vext2 <4,3,6,5>, <4,3,6,5> + 2596326710U, // <6,5,4,4>: Cost 3 vext1 <7,6,5,4>, RHS 2634984758U, // <6,5,4,5>: Cost 3 vext2 <2,u,6,5>, RHS - 2253501069U, // <6,5,4,6>: Cost 3 vrev <6,4,5,6> - 1185731942U, // <6,5,4,7>: Cost 2 vrev <7,4,5,6> - 1522587438U, // <6,5,4,u>: Cost 2 vext1 <7,6,5,4>, LHS + 3767734199U, // <6,5,4,6>: Cost 4 vext3 <1,5,4,6>, <5,4,6,0> + 1643696070U, // <6,5,4,7>: Cost 2 vext3 <5,4,7,6>, <5,4,7,6> + 1643769807U, // <6,5,4,u>: Cost 2 vext3 <5,4,u,6>, <5,4,u,6> 2578415718U, // <6,5,5,0>: Cost 3 vext1 <4,6,5,5>, LHS - 3652158260U, // <6,5,5,1>: Cost 4 vext1 <4,6,5,5>, <1,1,1,1> + 3652158198U, // <6,5,5,1>: Cost 4 vext1 <4,6,5,5>, <1,0,3,2> 3652159080U, // <6,5,5,2>: Cost 4 vext1 <4,6,5,5>, <2,2,2,2> 3652159638U, // <6,5,5,3>: Cost 4 vext1 <4,6,5,5>, <3,0,1,2> 2578418998U, // <6,5,5,4>: Cost 3 vext1 <4,6,5,5>, RHS @@ -4872,55 +4872,55 @@ 2980497922U, // <6,5,7,6>: Cost 3 vzipr RHS, <3,4,5,6> 3103214902U, // <6,5,7,7>: Cost 3 vtrnr <2,6,3,7>, RHS 2560522030U, // <6,5,7,u>: Cost 3 vext1 <1,6,5,7>, LHS - 1528586342U, // <6,5,u,0>: Cost 2 vext1 , LHS + 2560524390U, // <6,5,u,0>: Cost 3 vext1 <1,6,5,u>, LHS 2560525556U, // <6,5,u,1>: Cost 3 vext1 <1,6,5,u>, <1,6,5,u> 2566498253U, // <6,5,u,2>: Cost 3 vext1 <2,6,5,u>, <2,6,5,u> - 1164495686U, // <6,5,u,3>: Cost 2 vrev <3,u,5,6> - 1528589622U, // <6,5,u,4>: Cost 2 vext1 , RHS + 2646931439U, // <6,5,u,3>: Cost 3 vext2 <4,u,6,5>, + 2560527670U, // <6,5,u,4>: Cost 3 vext1 <1,6,5,u>, RHS 2634987674U, // <6,5,u,5>: Cost 3 vext2 <2,u,6,5>, RHS 2980506114U, // <6,5,u,6>: Cost 3 vzipr RHS, <3,4,5,6> - 1188386474U, // <6,5,u,7>: Cost 2 vrev <7,u,5,6> - 1528592611U, // <6,5,u,u>: Cost 2 vext1 , + 1175277674U, // <6,5,u,7>: Cost 2 vrev <5,6,7,u> + 1175351411U, // <6,5,u,u>: Cost 2 vrev <5,6,u,u> 2578448486U, // <6,6,0,0>: Cost 3 vext1 <4,6,6,0>, LHS 1573191782U, // <6,6,0,1>: Cost 2 vext2 <4,u,6,6>, LHS 2686030124U, // <6,6,0,2>: Cost 3 vext3 <0,2,4,6>, <6,0,2,4> 3779088690U, // <6,6,0,3>: Cost 4 vext3 <3,4,5,6>, <6,0,3,1> 2687209788U, // <6,6,0,4>: Cost 3 vext3 <0,4,2,6>, <6,0,4,2> 3652194000U, // <6,6,0,5>: Cost 4 vext1 <4,6,6,0>, <5,1,7,3> - 2590397234U, // <6,6,0,6>: Cost 3 vext1 <6,6,6,0>, <6,6,6,0> + 2254852914U, // <6,6,0,6>: Cost 3 vrev <6,6,6,0> 4041575734U, // <6,6,0,7>: Cost 4 vzipr <2,4,6,0>, RHS 1573192349U, // <6,6,0,u>: Cost 2 vext2 <4,u,6,6>, LHS - 3640254566U, // <6,6,1,0>: Cost 4 vext1 <2,6,6,1>, LHS + 2646934262U, // <6,6,1,0>: Cost 3 vext2 <4,u,6,6>, <1,0,3,2> 2646934324U, // <6,6,1,1>: Cost 3 vext2 <4,u,6,6>, <1,1,1,1> 2646934422U, // <6,6,1,2>: Cost 3 vext2 <4,u,6,6>, <1,2,3,0> 2846785638U, // <6,6,1,3>: Cost 3 vuzpr <4,6,4,6>, LHS - 3760877963U, // <6,6,1,4>: Cost 4 vext3 <0,4,1,6>, <6,1,4,0> + 3760951694U, // <6,6,1,4>: Cost 4 vext3 <0,4,2,6>, <6,1,4,3> 2646934672U, // <6,6,1,5>: Cost 3 vext2 <4,u,6,6>, <1,5,3,7> 2712572320U, // <6,6,1,6>: Cost 3 vext3 <4,6,4,6>, <6,1,6,3> 3775549865U, // <6,6,1,7>: Cost 4 vext3 <2,u,2,6>, <6,1,7,3> 2846785643U, // <6,6,1,u>: Cost 3 vuzpr <4,6,4,6>, LHS - 3640262758U, // <6,6,2,0>: Cost 4 vext1 <2,6,6,2>, LHS + 3759772094U, // <6,6,2,0>: Cost 4 vext3 <0,2,4,6>, <6,2,0,6> 3704751676U, // <6,6,2,1>: Cost 4 vext2 <2,2,6,6>, <2,1,6,3> 2631009936U, // <6,6,2,2>: Cost 3 vext2 <2,2,6,6>, <2,2,6,6> 2646935206U, // <6,6,2,3>: Cost 3 vext2 <4,u,6,6>, <2,3,0,1> - 2687209948U, // <6,6,2,4>: Cost 3 vext3 <0,4,2,6>, <6,2,4,0> + 3759772127U, // <6,6,2,4>: Cost 4 vext3 <0,2,4,6>, <6,2,4,3> 3704752004U, // <6,6,2,5>: Cost 4 vext2 <2,2,6,6>, <2,5,6,7> 2646935482U, // <6,6,2,6>: Cost 3 vext2 <4,u,6,6>, <2,6,3,7> 2712572410U, // <6,6,2,7>: Cost 3 vext3 <4,6,4,6>, <6,2,7,3> 2712572419U, // <6,6,2,u>: Cost 3 vext3 <4,6,4,6>, <6,2,u,3> 2646935702U, // <6,6,3,0>: Cost 3 vext2 <4,u,6,6>, <3,0,1,2> 3777024534U, // <6,6,3,1>: Cost 4 vext3 <3,1,4,6>, <6,3,1,4> - 2646935862U, // <6,6,3,2>: Cost 3 vext2 <4,u,6,6>, <3,2,1,0> + 3704752453U, // <6,6,3,2>: Cost 4 vext2 <2,2,6,6>, <3,2,2,6> 2646935964U, // <6,6,3,3>: Cost 3 vext2 <4,u,6,6>, <3,3,3,3> 2705347122U, // <6,6,3,4>: Cost 3 vext3 <3,4,5,6>, <6,3,4,5> - 3773633080U, // <6,6,3,5>: Cost 4 vext3 <2,5,3,6>, <6,3,5,2> + 3779678778U, // <6,6,3,5>: Cost 4 vext3 <3,5,4,6>, <6,3,5,4> 2657553069U, // <6,6,3,6>: Cost 3 vext2 <6,6,6,6>, <3,6,6,6> 4039609654U, // <6,6,3,7>: Cost 4 vzipr <2,1,6,3>, RHS 2708001366U, // <6,6,3,u>: Cost 3 vext3 <3,u,5,6>, <6,3,u,5> - 2646936466U, // <6,6,4,0>: Cost 3 vext2 <4,u,6,6>, <4,0,5,1> - 3765080676U, // <6,6,4,1>: Cost 4 vext3 <1,1,4,6>, <6,4,1,1> - 2686030444U, // <6,6,4,2>: Cost 3 vext3 <0,2,4,6>, <6,4,2,0> - 3766407798U, // <6,6,4,3>: Cost 4 vext3 <1,3,4,6>, <6,4,3,1> + 2578481254U, // <6,6,4,0>: Cost 3 vext1 <4,6,6,4>, LHS + 3652223734U, // <6,6,4,1>: Cost 4 vext1 <4,6,6,4>, <1,0,3,2> + 3760951922U, // <6,6,4,2>: Cost 4 vext3 <0,4,2,6>, <6,4,2,6> + 3779089019U, // <6,6,4,3>: Cost 4 vext3 <3,4,5,6>, <6,4,3,6> 1570540772U, // <6,6,4,4>: Cost 2 vext2 <4,4,6,6>, <4,4,6,6> 1573195062U, // <6,6,4,5>: Cost 2 vext2 <4,u,6,6>, RHS 2712572560U, // <6,6,4,6>: Cost 3 vext3 <4,6,4,6>, <6,4,6,0> @@ -4930,13 +4930,13 @@ 2646937296U, // <6,6,5,1>: Cost 3 vext2 <4,u,6,6>, <5,1,7,3> 3640289235U, // <6,6,5,2>: Cost 4 vext1 <2,6,6,5>, <2,6,6,5> 3720679279U, // <6,6,5,3>: Cost 4 vext2 <4,u,6,6>, <5,3,7,0> - 2705347282U, // <6,6,5,4>: Cost 3 vext3 <3,4,5,6>, <6,5,4,3> + 2646937542U, // <6,6,5,4>: Cost 3 vext2 <4,u,6,6>, <5,4,7,6> 2646937604U, // <6,6,5,5>: Cost 3 vext2 <4,u,6,6>, <5,5,5,5> 2646937698U, // <6,6,5,6>: Cost 3 vext2 <4,u,6,6>, <5,6,7,0> 2846788918U, // <6,6,5,7>: Cost 3 vuzpr <4,6,4,6>, RHS - 2708001526U, // <6,6,5,u>: Cost 3 vext3 <3,u,5,6>, <6,5,u,3> + 2846788919U, // <6,6,5,u>: Cost 3 vuzpr <4,6,4,6>, RHS 1516699750U, // <6,6,6,0>: Cost 2 vext1 <6,6,6,6>, LHS - 2590442292U, // <6,6,6,1>: Cost 3 vext1 <6,6,6,6>, <1,1,1,1> + 2590442230U, // <6,6,6,1>: Cost 3 vext1 <6,6,6,6>, <1,0,3,2> 2646938106U, // <6,6,6,2>: Cost 3 vext2 <4,u,6,6>, <6,2,7,3> 2590443670U, // <6,6,6,3>: Cost 3 vext1 <6,6,6,6>, <3,0,1,2> 1516703030U, // <6,6,6,4>: Cost 2 vext1 <6,6,6,6>, RHS @@ -4949,13 +4949,13 @@ 2566563797U, // <6,6,7,2>: Cost 3 vext1 <2,6,6,7>, <2,6,6,7> 2584480258U, // <6,6,7,3>: Cost 3 vext1 <5,6,6,7>, <3,4,5,6> 2566565174U, // <6,6,7,4>: Cost 3 vext1 <2,6,6,7>, RHS - 2584481888U, // <6,6,7,5>: Cost 3 vext1 <5,6,6,7>, <5,6,6,7> + 2717438846U, // <6,6,7,5>: Cost 3 vext3 <5,4,7,6>, <6,7,5,4> 2980500280U, // <6,6,7,6>: Cost 3 vzipr RHS, <6,6,6,6> 1906756918U, // <6,6,7,7>: Cost 2 vzipr RHS, RHS 1906756919U, // <6,6,7,u>: Cost 2 vzipr RHS, RHS 1516699750U, // <6,6,u,0>: Cost 2 vext1 <6,6,6,6>, LHS 1573197614U, // <6,6,u,1>: Cost 2 vext2 <4,u,6,6>, LHS - 2686325680U, // <6,6,u,2>: Cost 3 vext3 <0,2,u,6>, <6,u,2,0> + 2566571990U, // <6,6,u,2>: Cost 3 vext1 <2,6,6,u>, <2,6,6,u> 2846786205U, // <6,6,u,3>: Cost 3 vuzpr <4,6,4,6>, LHS 1516703030U, // <6,6,u,4>: Cost 2 vext1 <6,6,6,6>, RHS 1573197978U, // <6,6,u,5>: Cost 2 vext2 <4,u,6,6>, RHS @@ -4971,17 +4971,17 @@ 2644951542U, // <6,7,0,6>: Cost 3 vext2 RHS, <0,6,1,7> 2584499194U, // <6,7,0,7>: Cost 3 vext1 <5,6,7,0>, <7,0,1,2> 497468061U, // <6,7,0,u>: Cost 1 vext2 RHS, LHS - 2644951770U, // <6,7,1,0>: Cost 3 vext2 RHS, <1,0,0,1> + 1571209974U, // <6,7,1,0>: Cost 2 vext2 RHS, <1,0,3,2> 1571210036U, // <6,7,1,1>: Cost 2 vext2 RHS, <1,1,1,1> 1571210134U, // <6,7,1,2>: Cost 2 vext2 RHS, <1,2,3,0> 1571210200U, // <6,7,1,3>: Cost 2 vext2 RHS, <1,3,1,3> - 2644952107U, // <6,7,1,4>: Cost 3 vext2 RHS, <1,4,1,5> + 2644952098U, // <6,7,1,4>: Cost 3 vext2 RHS, <1,4,0,5> 1571210384U, // <6,7,1,5>: Cost 2 vext2 RHS, <1,5,3,7> - 2644952262U, // <6,7,1,6>: Cost 3 vext2 RHS, <1,6,0,7> + 2644952271U, // <6,7,1,6>: Cost 3 vext2 RHS, <1,6,1,7> 2578535418U, // <6,7,1,7>: Cost 3 vext1 <4,6,7,1>, <7,0,1,2> 1571210605U, // <6,7,1,u>: Cost 2 vext2 RHS, <1,u,1,3> 2644952509U, // <6,7,2,0>: Cost 3 vext2 RHS, <2,0,1,2> - 2644952579U, // <6,7,2,1>: Cost 3 vext2 RHS, <2,1,0,0> + 2644952582U, // <6,7,2,1>: Cost 3 vext2 RHS, <2,1,0,3> 1571210856U, // <6,7,2,2>: Cost 2 vext2 RHS, <2,2,2,2> 1571210918U, // <6,7,2,3>: Cost 2 vext2 RHS, <2,3,0,1> 2644952828U, // <6,7,2,4>: Cost 3 vext2 RHS, <2,4,0,6> @@ -4990,18 +4990,18 @@ 2668840938U, // <6,7,2,7>: Cost 3 vext2 RHS, <2,7,0,1> 1571211323U, // <6,7,2,u>: Cost 2 vext2 RHS, <2,u,0,1> 1571211414U, // <6,7,3,0>: Cost 2 vext2 RHS, <3,0,1,2> - 2644953318U, // <6,7,3,1>: Cost 3 vext2 RHS, <3,1,1,1> - 1571211574U, // <6,7,3,2>: Cost 2 vext2 RHS, <3,2,1,0> + 2644953311U, // <6,7,3,1>: Cost 3 vext2 RHS, <3,1,0,3> + 2644953390U, // <6,7,3,2>: Cost 3 vext2 RHS, <3,2,0,1> 1571211676U, // <6,7,3,3>: Cost 2 vext2 RHS, <3,3,3,3> 1571211778U, // <6,7,3,4>: Cost 2 vext2 RHS, <3,4,5,6> 2644953648U, // <6,7,3,5>: Cost 3 vext2 RHS, <3,5,1,7> 2644953720U, // <6,7,3,6>: Cost 3 vext2 RHS, <3,6,0,7> 2644953795U, // <6,7,3,7>: Cost 3 vext2 RHS, <3,7,0,1> - 1571212060U, // <6,7,3,u>: Cost 2 vext2 RHS, <3,u,1,0> + 1571212062U, // <6,7,3,u>: Cost 2 vext2 RHS, <3,u,1,2> 1573202834U, // <6,7,4,0>: Cost 2 vext2 RHS, <4,0,5,1> 2644954058U, // <6,7,4,1>: Cost 3 vext2 RHS, <4,1,2,3> 2644954166U, // <6,7,4,2>: Cost 3 vext2 RHS, <4,2,5,3> - 2644954218U, // <6,7,4,3>: Cost 3 vext2 RHS, <4,3,2,1> + 2644954258U, // <6,7,4,3>: Cost 3 vext2 RHS, <4,3,6,5> 1571212496U, // <6,7,4,4>: Cost 2 vext2 RHS, <4,4,4,4> 497470774U, // <6,7,4,5>: Cost 1 vext2 RHS, RHS 1573203316U, // <6,7,4,6>: Cost 2 vext2 RHS, <4,6,4,6> @@ -5011,7 +5011,7 @@ 1573203664U, // <6,7,5,1>: Cost 2 vext2 RHS, <5,1,7,3> 2644954878U, // <6,7,5,2>: Cost 3 vext2 RHS, <5,2,3,4> 2644954991U, // <6,7,5,3>: Cost 3 vext2 RHS, <5,3,7,0> - 2644955038U, // <6,7,5,4>: Cost 3 vext2 RHS, <5,4,3,2> + 1571213254U, // <6,7,5,4>: Cost 2 vext2 RHS, <5,4,7,6> 1571213316U, // <6,7,5,5>: Cost 2 vext2 RHS, <5,5,5,5> 1571213410U, // <6,7,5,6>: Cost 2 vext2 RHS, <5,6,7,0> 1573204136U, // <6,7,5,7>: Cost 2 vext2 RHS, <5,7,5,7> @@ -5020,8 +5020,8 @@ 2644955561U, // <6,7,6,1>: Cost 3 vext2 RHS, <6,1,7,3> 1573204474U, // <6,7,6,2>: Cost 2 vext2 RHS, <6,2,7,3> 2644955698U, // <6,7,6,3>: Cost 3 vext2 RHS, <6,3,4,5> - 2644955756U, // <6,7,6,4>: Cost 3 vext2 RHS, <6,4,2,0> - 2644955858U, // <6,7,6,5>: Cost 3 vext2 RHS, <6,5,4,3> + 2644955789U, // <6,7,6,4>: Cost 3 vext2 RHS, <6,4,5,6> + 2644955889U, // <6,7,6,5>: Cost 3 vext2 RHS, <6,5,7,7> 1571214136U, // <6,7,6,6>: Cost 2 vext2 RHS, <6,6,6,6> 1571214158U, // <6,7,6,7>: Cost 2 vext2 RHS, <6,7,0,1> 1573204895U, // <6,7,6,u>: Cost 2 vext2 RHS, <6,u,0,1> @@ -5030,13 +5030,13 @@ 2644956362U, // <6,7,7,2>: Cost 3 vext2 RHS, <7,2,6,3> 2572610231U, // <6,7,7,3>: Cost 3 vext1 <3,6,7,7>, <3,6,7,7> 1573205350U, // <6,7,7,4>: Cost 2 vext2 RHS, <7,4,5,6> - 2644956576U, // <6,7,7,5>: Cost 3 vext2 RHS, <7,5,3,1> - 1571214854U, // <6,7,7,6>: Cost 2 vext2 RHS, <7,6,5,4> + 2646947220U, // <6,7,7,5>: Cost 3 vext2 RHS, <7,5,1,7> + 1516786498U, // <6,7,7,6>: Cost 2 vext1 <6,6,7,7>, <6,6,7,7> 1571214956U, // <6,7,7,7>: Cost 2 vext2 RHS, <7,7,7,7> 1573205634U, // <6,7,7,u>: Cost 2 vext2 RHS, <7,u,1,2> 1571215059U, // <6,7,u,0>: Cost 2 vext2 RHS, 497473326U, // <6,7,u,1>: Cost 1 vext2 RHS, LHS - 1571215219U, // <6,7,u,2>: Cost 2 vext2 RHS, + 1571215237U, // <6,7,u,2>: Cost 2 vext2 RHS, 1571215292U, // <6,7,u,3>: Cost 2 vext2 RHS, 1571215423U, // <6,7,u,4>: Cost 2 vext2 RHS, 497473690U, // <6,7,u,5>: Cost 1 vext2 RHS, RHS @@ -5046,23 +5046,23 @@ 1571217408U, // <6,u,0,0>: Cost 2 vext2 RHS, <0,0,0,0> 497475686U, // <6,u,0,1>: Cost 1 vext2 RHS, LHS 1571217572U, // <6,u,0,2>: Cost 2 vext2 RHS, <0,2,0,2> - 2644959484U, // <6,u,0,3>: Cost 3 vext2 RHS, <0,3,1,0> + 2689865445U, // <6,u,0,3>: Cost 3 vext3 <0,u,2,6>, 1571217746U, // <6,u,0,4>: Cost 2 vext2 RHS, <0,4,1,5> 1510830187U, // <6,u,0,5>: Cost 2 vext1 <5,6,u,0>, <5,6,u,0> 2644959734U, // <6,u,0,6>: Cost 3 vext2 RHS, <0,6,1,7> - 3121368617U, // <6,u,0,7>: Cost 3 vtrnr <5,6,7,0>, RHS + 1193130221U, // <6,u,0,7>: Cost 2 vrev 497476253U, // <6,u,0,u>: Cost 1 vext2 RHS, LHS - 2566660198U, // <6,u,1,0>: Cost 3 vext1 <2,6,u,1>, LHS + 1571218166U, // <6,u,1,0>: Cost 2 vext2 RHS, <1,0,3,2> 1571218228U, // <6,u,1,1>: Cost 2 vext2 RHS, <1,1,1,1> 1612289838U, // <6,u,1,2>: Cost 2 vext3 <0,2,4,6>, LHS 1571218392U, // <6,u,1,3>: Cost 2 vext2 RHS, <1,3,1,3> 2566663478U, // <6,u,1,4>: Cost 3 vext1 <2,6,u,1>, RHS 1571218576U, // <6,u,1,5>: Cost 2 vext2 RHS, <1,5,3,7> - 2644960454U, // <6,u,1,6>: Cost 3 vext2 RHS, <1,6,0,7> - 2724665179U, // <6,u,1,7>: Cost 3 vext3 <6,6,6,6>, + 2644960463U, // <6,u,1,6>: Cost 3 vext2 RHS, <1,6,1,7> + 2717439835U, // <6,u,1,7>: Cost 3 vext3 <5,4,7,6>, 1612289892U, // <6,u,1,u>: Cost 2 vext3 <0,2,4,6>, LHS 1504870502U, // <6,u,2,0>: Cost 2 vext1 <4,6,u,2>, LHS - 2686031731U, // <6,u,2,1>: Cost 3 vext3 <0,2,4,6>, + 2644960774U, // <6,u,2,1>: Cost 3 vext2 RHS, <2,1,0,3> 1571219048U, // <6,u,2,2>: Cost 2 vext2 RHS, <2,2,2,2> 1571219110U, // <6,u,2,3>: Cost 2 vext2 RHS, <2,3,0,1> 1504873782U, // <6,u,2,4>: Cost 2 vext1 <4,6,u,2>, RHS @@ -5071,28 +5071,28 @@ 2712573868U, // <6,u,2,7>: Cost 3 vext3 <4,6,4,6>, 1571219515U, // <6,u,2,u>: Cost 2 vext2 RHS, <2,u,0,1> 1571219606U, // <6,u,3,0>: Cost 2 vext2 RHS, <3,0,1,2> - 2644961510U, // <6,u,3,1>: Cost 3 vext2 RHS, <3,1,1,1> - 1571219766U, // <6,u,3,2>: Cost 2 vext2 RHS, <3,2,1,0> + 2644961503U, // <6,u,3,1>: Cost 3 vext2 RHS, <3,1,0,3> + 2566678499U, // <6,u,3,2>: Cost 3 vext1 <2,6,u,3>, <2,6,u,3> 1571219868U, // <6,u,3,3>: Cost 2 vext2 RHS, <3,3,3,3> 1571219970U, // <6,u,3,4>: Cost 2 vext2 RHS, <3,4,5,6> 2689865711U, // <6,u,3,5>: Cost 3 vext3 <0,u,2,6>, - 2644961912U, // <6,u,3,6>: Cost 3 vext2 RHS, <3,6,0,7> + 2708002806U, // <6,u,3,6>: Cost 3 vext3 <3,u,5,6>, 2644961987U, // <6,u,3,7>: Cost 3 vext2 RHS, <3,7,0,1> - 1571220252U, // <6,u,3,u>: Cost 2 vext2 RHS, <3,u,1,0> + 1571220254U, // <6,u,3,u>: Cost 2 vext2 RHS, <3,u,1,2> 1571220370U, // <6,u,4,0>: Cost 2 vext2 RHS, <4,0,5,1> - 2223858795U, // <6,u,4,1>: Cost 3 vrev <1,4,u,6> + 2644962250U, // <6,u,4,1>: Cost 3 vext2 RHS, <4,1,2,3> 1661245476U, // <6,u,4,2>: Cost 2 vext3 , - 1162062365U, // <6,u,4,3>: Cost 2 vrev <3,4,u,6> + 2686031917U, // <6,u,4,3>: Cost 3 vext3 <0,2,4,6>, 1571220688U, // <6,u,4,4>: Cost 2 vext2 RHS, <4,4,4,4> 497478967U, // <6,u,4,5>: Cost 1 vext2 RHS, RHS 1571220852U, // <6,u,4,6>: Cost 2 vext2 RHS, <4,6,4,6> - 1185953153U, // <6,u,4,7>: Cost 2 vrev <7,4,u,6> + 1661614161U, // <6,u,4,7>: Cost 2 vext3 , 497479209U, // <6,u,4,u>: Cost 1 vext2 RHS, RHS 2566692966U, // <6,u,5,0>: Cost 3 vext1 <2,6,u,5>, LHS 1571221200U, // <6,u,5,1>: Cost 2 vext2 RHS, <5,1,7,3> 2566694885U, // <6,u,5,2>: Cost 3 vext1 <2,6,u,5>, <2,6,u,5> 2689865855U, // <6,u,5,3>: Cost 3 vext3 <0,u,2,6>, - 2566696246U, // <6,u,5,4>: Cost 3 vext1 <2,6,u,5>, RHS + 1571221446U, // <6,u,5,4>: Cost 2 vext2 RHS, <5,4,7,6> 1571221508U, // <6,u,5,5>: Cost 2 vext2 RHS, <5,5,5,5> 1612290202U, // <6,u,5,6>: Cost 2 vext3 <0,2,4,6>, RHS 1571221672U, // <6,u,5,7>: Cost 2 vext2 RHS, <5,7,5,7> @@ -5102,7 +5102,7 @@ 1571222010U, // <6,u,6,2>: Cost 2 vext2 RHS, <6,2,7,3> 2686032080U, // <6,u,6,3>: Cost 3 vext3 <0,2,4,6>, 1504906550U, // <6,u,6,4>: Cost 2 vext1 <4,6,u,6>, RHS - 2644964050U, // <6,u,6,5>: Cost 3 vext2 RHS, <6,5,4,3> + 2644964079U, // <6,u,6,5>: Cost 3 vext2 RHS, <6,5,7,5> 296144182U, // <6,u,6,6>: Cost 1 vdup2 RHS 1571222350U, // <6,u,6,7>: Cost 2 vext2 RHS, <6,7,0,1> 296144182U, // <6,u,6,u>: Cost 1 vdup2 RHS @@ -5112,13 +5112,13 @@ 1906753692U, // <6,u,7,3>: Cost 2 vzipr RHS, LHS 1492970806U, // <6,u,7,4>: Cost 2 vext1 <2,6,u,7>, RHS 2980495761U, // <6,u,7,5>: Cost 3 vzipr RHS, <0,4,u,5> - 1571223046U, // <6,u,7,6>: Cost 2 vext2 RHS, <7,6,5,4> + 1516860235U, // <6,u,7,6>: Cost 2 vext1 <6,6,u,7>, <6,6,u,7> 1906756936U, // <6,u,7,7>: Cost 2 vzipr RHS, RHS 1492973358U, // <6,u,7,u>: Cost 2 vext1 <2,6,u,7>, LHS 1492975718U, // <6,u,u,0>: Cost 2 vext1 <2,6,u,u>, LHS 497481518U, // <6,u,u,1>: Cost 1 vext2 RHS, LHS 1612290405U, // <6,u,u,2>: Cost 2 vext3 <0,2,4,6>, LHS - 1164716897U, // <6,u,u,3>: Cost 2 vrev <3,u,u,6> + 1571223484U, // <6,u,u,3>: Cost 2 vext2 RHS, 1492978998U, // <6,u,u,4>: Cost 2 vext1 <2,6,u,u>, RHS 497481882U, // <6,u,u,5>: Cost 1 vext2 RHS, RHS 296144182U, // <6,u,u,6>: Cost 1 vdup2 RHS @@ -5131,7 +5131,7 @@ 2712059941U, // <7,0,0,4>: Cost 3 vext3 RHS, <0,0,4,1> 2651603364U, // <7,0,0,5>: Cost 3 vext2 <5,6,7,0>, <0,5,1,6> 2590618445U, // <7,0,0,6>: Cost 3 vext1 <6,7,0,0>, <6,7,0,0> - 2651603570U, // <7,0,0,7>: Cost 3 vext2 <5,6,7,0>, <0,7,6,5> + 3785801798U, // <7,0,0,7>: Cost 4 vext3 RHS, <0,0,7,7> 1638318153U, // <7,0,0,u>: Cost 2 vext3 RHS, <0,0,u,1> 1516879974U, // <7,0,1,0>: Cost 2 vext1 <6,7,0,1>, LHS 2693922911U, // <7,0,1,1>: Cost 3 vext3 <1,5,3,7>, <0,1,1,5> @@ -5153,7 +5153,7 @@ 1638318316U, // <7,0,2,u>: Cost 2 vext3 RHS, <0,2,u,2> 2651605142U, // <7,0,3,0>: Cost 3 vext2 <5,6,7,0>, <3,0,1,2> 2712060156U, // <7,0,3,1>: Cost 3 vext3 RHS, <0,3,1,0> - 2712060166U, // <7,0,3,2>: Cost 3 vext3 RHS, <0,3,2,1> + 2712060165U, // <7,0,3,2>: Cost 3 vext3 RHS, <0,3,2,0> 2651605404U, // <7,0,3,3>: Cost 3 vext2 <5,6,7,0>, <3,3,3,3> 2651605506U, // <7,0,3,4>: Cost 3 vext2 <5,6,7,0>, <3,4,5,6> 2638998111U, // <7,0,3,5>: Cost 3 vext2 <3,5,7,0>, <3,5,7,0> @@ -5173,7 +5173,7 @@ 2651606736U, // <7,0,5,1>: Cost 3 vext2 <5,6,7,0>, <5,1,7,3> 2712060334U, // <7,0,5,2>: Cost 3 vext3 RHS, <0,5,2,7> 2649616239U, // <7,0,5,3>: Cost 3 vext2 <5,3,7,0>, <5,3,7,0> - 2590657846U, // <7,0,5,4>: Cost 3 vext1 <6,7,0,5>, RHS + 2651606982U, // <7,0,5,4>: Cost 3 vext2 <5,6,7,0>, <5,4,7,6> 2651607044U, // <7,0,5,5>: Cost 3 vext2 <5,6,7,0>, <5,5,5,5> 1577865314U, // <7,0,5,6>: Cost 2 vext2 <5,6,7,0>, <5,6,7,0> 2651607208U, // <7,0,5,7>: Cost 3 vext2 <5,6,7,0>, <5,7,5,7> @@ -5193,7 +5193,7 @@ 3712742678U, // <7,0,7,3>: Cost 4 vext2 <3,5,7,0>, <7,3,5,7> 2651608422U, // <7,0,7,4>: Cost 3 vext2 <5,6,7,0>, <7,4,5,6> 2651608513U, // <7,0,7,5>: Cost 3 vext2 <5,6,7,0>, <7,5,6,7> - 2651608582U, // <7,0,7,6>: Cost 3 vext2 <5,6,7,0>, <7,6,5,4> + 2663552532U, // <7,0,7,6>: Cost 3 vext2 <7,6,7,0>, <7,6,7,0> 2651608684U, // <7,0,7,7>: Cost 3 vext2 <5,6,7,0>, <7,7,7,7> 2651608706U, // <7,0,7,u>: Cost 3 vext2 <5,6,7,0>, <7,u,1,2> 1638318730U, // <7,0,u,0>: Cost 2 vext3 RHS, <0,u,0,2> @@ -5205,15 +5205,15 @@ 1516942165U, // <7,0,u,6>: Cost 2 vext1 <6,7,0,u>, <6,7,0,u> 2651609344U, // <7,0,u,7>: Cost 3 vext2 <5,6,7,0>, 564576979U, // <7,0,u,u>: Cost 1 vext3 RHS, LHS - 2712060634U, // <7,1,0,0>: Cost 3 vext3 RHS, <1,0,0,1> + 2590687334U, // <7,1,0,0>: Cost 3 vext1 <6,7,1,0>, LHS 2639003750U, // <7,1,0,1>: Cost 3 vext2 <3,5,7,1>, LHS 2793357414U, // <7,1,0,2>: Cost 3 vuzpl <7,0,1,2>, LHS - 2712060660U, // <7,1,0,3>: Cost 3 vext3 RHS, <1,0,3,0> - 2712060674U, // <7,1,0,4>: Cost 3 vext3 RHS, <1,0,4,5> - 2712060680U, // <7,1,0,5>: Cost 3 vext3 RHS, <1,0,5,2> - 3785802513U, // <7,1,0,6>: Cost 4 vext3 RHS, <1,0,6,2> - 2735948574U, // <7,1,0,7>: Cost 3 vext3 RHS, <1,0,7,6> - 2639004317U, // <7,1,0,u>: Cost 3 vext2 <3,5,7,1>, LHS + 1638318838U, // <7,1,0,3>: Cost 2 vext3 RHS, <1,0,3,2> + 2590690614U, // <7,1,0,4>: Cost 3 vext1 <6,7,1,0>, RHS + 2712060679U, // <7,1,0,5>: Cost 3 vext3 RHS, <1,0,5,1> + 2590692182U, // <7,1,0,6>: Cost 3 vext1 <6,7,1,0>, <6,7,1,0> + 3785802521U, // <7,1,0,7>: Cost 4 vext3 RHS, <1,0,7,1> + 1638318883U, // <7,1,0,u>: Cost 2 vext3 RHS, <1,0,u,2> 2712060715U, // <7,1,1,0>: Cost 3 vext3 RHS, <1,1,0,1> 1638318900U, // <7,1,1,1>: Cost 2 vext3 RHS, <1,1,1,1> 3774300994U, // <7,1,1,2>: Cost 4 vext3 <2,6,3,7>, <1,1,2,6> @@ -5221,7 +5221,7 @@ 2712060755U, // <7,1,1,4>: Cost 3 vext3 RHS, <1,1,4,5> 2691416926U, // <7,1,1,5>: Cost 3 vext3 <1,1,5,7>, <1,1,5,7> 2590700375U, // <7,1,1,6>: Cost 3 vext1 <6,7,1,1>, <6,7,1,1> - 3765306224U, // <7,1,1,7>: Cost 4 vext3 <1,1,7,7>, <1,1,7,7> + 3765158766U, // <7,1,1,7>: Cost 4 vext3 <1,1,5,7>, <1,1,7,5> 1638318965U, // <7,1,1,u>: Cost 2 vext3 RHS, <1,1,u,3> 2712060796U, // <7,1,2,0>: Cost 3 vext3 RHS, <1,2,0,1> 2712060807U, // <7,1,2,1>: Cost 3 vext3 RHS, <1,2,1,3> @@ -5241,14 +5241,14 @@ 2692817929U, // <7,1,3,6>: Cost 3 vext3 <1,3,6,7>, <1,3,6,7> 2735948814U, // <7,1,3,7>: Cost 3 vext3 RHS, <1,3,7,3> 1619223579U, // <7,1,3,u>: Cost 2 vext3 <1,3,u,7>, <1,3,u,7> - 2554888294U, // <7,1,4,0>: Cost 3 vext1 <0,7,1,4>, LHS + 2712060962U, // <7,1,4,0>: Cost 3 vext3 RHS, <1,4,0,5> 2712060971U, // <7,1,4,1>: Cost 3 vext3 RHS, <1,4,1,5> 2712060980U, // <7,1,4,2>: Cost 3 vext3 RHS, <1,4,2,5> 2712060989U, // <7,1,4,3>: Cost 3 vext3 RHS, <1,4,3,5> - 2554891574U, // <7,1,4,4>: Cost 3 vext1 <0,7,1,4>, RHS + 3785802822U, // <7,1,4,4>: Cost 4 vext3 RHS, <1,4,4,5> 2639007030U, // <7,1,4,5>: Cost 3 vext2 <3,5,7,1>, RHS 2645642634U, // <7,1,4,6>: Cost 3 vext2 <4,6,7,1>, <4,6,7,1> - 2554893670U, // <7,1,4,7>: Cost 3 vext1 <0,7,1,4>, <7,4,5,6> + 3719384520U, // <7,1,4,7>: Cost 4 vext2 <4,6,7,1>, <4,7,5,0> 2639007273U, // <7,1,4,u>: Cost 3 vext2 <3,5,7,1>, RHS 2572812390U, // <7,1,5,0>: Cost 3 vext1 <3,7,1,5>, LHS 2693776510U, // <7,1,5,1>: Cost 3 vext3 <1,5,1,7>, <1,5,1,7> @@ -5259,11 +5259,11 @@ 2651615331U, // <7,1,5,6>: Cost 3 vext2 <5,6,7,1>, <5,6,7,1> 2652278964U, // <7,1,5,7>: Cost 3 vext2 <5,7,7,1>, <5,7,7,1> 1620550845U, // <7,1,5,u>: Cost 2 vext3 <1,5,u,7>, <1,5,u,7> - 2712061126U, // <7,1,6,0>: Cost 3 vext3 RHS, <1,6,0,7> + 3768108230U, // <7,1,6,0>: Cost 4 vext3 <1,6,0,7>, <1,6,0,7> 2694440143U, // <7,1,6,1>: Cost 3 vext3 <1,6,1,7>, <1,6,1,7> 2712061144U, // <7,1,6,2>: Cost 3 vext3 RHS, <1,6,2,7> 2694587617U, // <7,1,6,3>: Cost 3 vext3 <1,6,3,7>, <1,6,3,7> - 2554907958U, // <7,1,6,4>: Cost 3 vext1 <0,7,1,6>, RHS + 3768403178U, // <7,1,6,4>: Cost 4 vext3 <1,6,4,7>, <1,6,4,7> 2694735091U, // <7,1,6,5>: Cost 3 vext3 <1,6,5,7>, <1,6,5,7> 3768550652U, // <7,1,6,6>: Cost 4 vext3 <1,6,6,7>, <1,6,6,7> 2652279630U, // <7,1,6,7>: Cost 3 vext2 <5,7,7,1>, <6,7,0,1> @@ -5274,7 +5274,7 @@ 3121938534U, // <7,1,7,3>: Cost 3 vtrnr <5,7,5,7>, LHS 2554916150U, // <7,1,7,4>: Cost 3 vext1 <0,7,1,7>, RHS 3769140548U, // <7,1,7,5>: Cost 4 vext3 <1,7,5,7>, <1,7,5,7> - 3719386630U, // <7,1,7,6>: Cost 4 vext2 <4,6,7,1>, <7,6,5,4> + 3726022164U, // <7,1,7,6>: Cost 4 vext2 <5,7,7,1>, <7,6,7,0> 2554918508U, // <7,1,7,7>: Cost 3 vext1 <0,7,1,7>, <7,7,7,7> 3121938539U, // <7,1,7,u>: Cost 3 vtrnr <5,7,5,7>, LHS 2572836966U, // <7,1,u,0>: Cost 3 vext1 <3,7,1,u>, LHS @@ -5295,15 +5295,15 @@ 2712061417U, // <7,2,0,6>: Cost 3 vext3 RHS, <2,0,6,1> 3785803251U, // <7,2,0,7>: Cost 4 vext3 RHS, <2,0,7,2> 2696947201U, // <7,2,0,u>: Cost 3 vext3 <2,0,u,7>, <2,0,u,7> - 2712061443U, // <7,2,1,0>: Cost 3 vext3 RHS, <2,1,0,0> + 2712061446U, // <7,2,1,0>: Cost 3 vext3 RHS, <2,1,0,3> 3785803276U, // <7,2,1,1>: Cost 4 vext3 RHS, <2,1,1,0> 3785803285U, // <7,2,1,2>: Cost 4 vext3 RHS, <2,1,2,0> - 2712061470U, // <7,2,1,3>: Cost 3 vext3 RHS, <2,1,3,0> + 2712061471U, // <7,2,1,3>: Cost 3 vext3 RHS, <2,1,3,1> 2712061482U, // <7,2,1,4>: Cost 3 vext3 RHS, <2,1,4,3> 3766486576U, // <7,2,1,5>: Cost 4 vext3 <1,3,5,7>, <2,1,5,0> 2712061500U, // <7,2,1,6>: Cost 3 vext3 RHS, <2,1,6,3> - 2554942458U, // <7,2,1,7>: Cost 3 vext1 <0,7,2,1>, <7,0,1,2> - 2712061515U, // <7,2,1,u>: Cost 3 vext3 RHS, <2,1,u,0> + 2602718850U, // <7,2,1,7>: Cost 3 vext1 , <7,u,1,2> + 2712061516U, // <7,2,1,u>: Cost 3 vext3 RHS, <2,1,u,1> 2712061525U, // <7,2,2,0>: Cost 3 vext3 RHS, <2,2,0,1> 2712061536U, // <7,2,2,1>: Cost 3 vext3 RHS, <2,2,1,3> 1638319720U, // <7,2,2,2>: Cost 2 vext3 RHS, <2,2,2,2> @@ -5311,7 +5311,7 @@ 2712061565U, // <7,2,2,4>: Cost 3 vext3 RHS, <2,2,4,5> 2698053256U, // <7,2,2,5>: Cost 3 vext3 <2,2,5,7>, <2,2,5,7> 2712061584U, // <7,2,2,6>: Cost 3 vext3 RHS, <2,2,6,6> - 3771942554U, // <7,2,2,7>: Cost 4 vext3 <2,2,7,7>, <2,2,7,7> + 3771795096U, // <7,2,2,7>: Cost 4 vext3 <2,2,5,7>, <2,2,7,5> 1638319775U, // <7,2,2,u>: Cost 2 vext3 RHS, <2,2,u,3> 1638319782U, // <7,2,3,0>: Cost 2 vext3 RHS, <2,3,0,1> 2693924531U, // <7,2,3,1>: Cost 3 vext3 <1,5,3,7>, <2,3,1,5> @@ -5347,15 +5347,15 @@ 2572897590U, // <7,2,6,4>: Cost 3 vext1 <3,7,2,6>, RHS 2700707788U, // <7,2,6,5>: Cost 3 vext3 <2,6,5,7>, <2,6,5,7> 2700781525U, // <7,2,6,6>: Cost 3 vext3 <2,6,6,7>, <2,6,6,7> - 2260588014U, // <7,2,6,7>: Cost 3 vrev <7,6,2,7> + 3774597086U, // <7,2,6,7>: Cost 4 vext3 <2,6,7,7>, <2,6,7,7> 1627187175U, // <7,2,6,u>: Cost 2 vext3 <2,6,u,7>, <2,6,u,7> 2735949802U, // <7,2,7,0>: Cost 3 vext3 RHS, <2,7,0,1> - 3785803768U, // <7,2,7,1>: Cost 4 vext3 RHS, <2,7,1,6> + 3780200434U, // <7,2,7,1>: Cost 4 vext3 <3,6,2,7>, <2,7,1,0> 3773564928U, // <7,2,7,2>: Cost 4 vext3 <2,5,2,7>, <2,7,2,5> 2986541158U, // <7,2,7,3>: Cost 3 vzipr <5,5,7,7>, LHS 2554989878U, // <7,2,7,4>: Cost 3 vext1 <0,7,2,7>, RHS 3775113245U, // <7,2,7,5>: Cost 4 vext3 <2,7,5,7>, <2,7,5,7> - 3785803810U, // <7,2,7,6>: Cost 4 vext3 RHS, <2,7,6,3> + 4060283228U, // <7,2,7,6>: Cost 4 vzipr <5,5,7,7>, <0,4,2,6> 2554992236U, // <7,2,7,7>: Cost 3 vext1 <0,7,2,7>, <7,7,7,7> 2986541163U, // <7,2,7,u>: Cost 3 vzipr <5,5,7,7>, LHS 1638320187U, // <7,2,u,0>: Cost 2 vext3 RHS, <2,u,0,1> @@ -5365,7 +5365,7 @@ 1638320227U, // <7,2,u,4>: Cost 2 vext3 RHS, <2,u,4,5> 2702035054U, // <7,2,u,5>: Cost 3 vext3 <2,u,5,7>, <2,u,5,7> 2702108791U, // <7,2,u,6>: Cost 3 vext3 <2,u,6,7>, <2,u,6,7> - 2261915280U, // <7,2,u,7>: Cost 3 vrev <7,u,2,7> + 2735949945U, // <7,2,u,7>: Cost 3 vext3 RHS, <2,u,7,0> 1628514441U, // <7,2,u,u>: Cost 2 vext3 <2,u,u,7>, <2,u,u,7> 2712062091U, // <7,3,0,0>: Cost 3 vext3 RHS, <3,0,0,0> 1638320278U, // <7,3,0,1>: Cost 2 vext3 RHS, <3,0,1,2> @@ -5374,26 +5374,26 @@ 2712062128U, // <7,3,0,4>: Cost 3 vext3 RHS, <3,0,4,1> 2712062138U, // <7,3,0,5>: Cost 3 vext3 RHS, <3,0,5,2> 2590839656U, // <7,3,0,6>: Cost 3 vext1 <6,7,3,0>, <6,7,3,0> - 3785803978U, // <7,3,0,7>: Cost 4 vext3 RHS, <3,0,7,0> + 3311414017U, // <7,3,0,7>: Cost 4 vrev <3,7,7,0> 1638320341U, // <7,3,0,u>: Cost 2 vext3 RHS, <3,0,u,2> - 3710108424U, // <7,3,1,0>: Cost 4 vext2 <3,1,7,3>, <1,0,5,2> + 2237164227U, // <7,3,1,0>: Cost 3 vrev <3,7,0,1> 2712062182U, // <7,3,1,1>: Cost 3 vext3 RHS, <3,1,1,1> 2712062193U, // <7,3,1,2>: Cost 3 vext3 RHS, <3,1,2,3> 2692745468U, // <7,3,1,3>: Cost 3 vext3 <1,3,5,7>, <3,1,3,5> 2712062214U, // <7,3,1,4>: Cost 3 vext3 RHS, <3,1,4,6> 2693925132U, // <7,3,1,5>: Cost 3 vext3 <1,5,3,7>, <3,1,5,3> 3768183059U, // <7,3,1,6>: Cost 4 vext3 <1,6,1,7>, <3,1,6,1> - 2712062238U, // <7,3,1,7>: Cost 3 vext3 RHS, <3,1,7,3> + 2692745504U, // <7,3,1,7>: Cost 3 vext3 <1,3,5,7>, <3,1,7,5> 2696063273U, // <7,3,1,u>: Cost 3 vext3 <1,u,5,7>, <3,1,u,5> - 2590851174U, // <7,3,2,0>: Cost 3 vext1 <6,7,3,2>, LHS - 1638320438U, // <7,3,2,1>: Cost 2 vext3 RHS, <3,2,1,0> + 2712062254U, // <7,3,2,0>: Cost 3 vext3 RHS, <3,2,0,1> + 2712062262U, // <7,3,2,1>: Cost 3 vext3 RHS, <3,2,1,0> 2712062273U, // <7,3,2,2>: Cost 3 vext3 RHS, <3,2,2,2> 2712062280U, // <7,3,2,3>: Cost 3 vext3 RHS, <3,2,3,0> - 2590854454U, // <7,3,2,4>: Cost 3 vext1 <6,7,3,2>, RHS - 3773565276U, // <7,3,2,5>: Cost 4 vext3 <2,5,2,7>, <3,2,5,2> + 2712062294U, // <7,3,2,4>: Cost 3 vext3 RHS, <3,2,4,5> + 2712062302U, // <7,3,2,5>: Cost 3 vext3 RHS, <3,2,5,4> 2700560742U, // <7,3,2,6>: Cost 3 vext3 <2,6,3,7>, <3,2,6,3> 2712062319U, // <7,3,2,7>: Cost 3 vext3 RHS, <3,2,7,3> - 1638320501U, // <7,3,2,u>: Cost 2 vext3 RHS, <3,2,u,0> + 2712062325U, // <7,3,2,u>: Cost 3 vext3 RHS, <3,2,u,0> 2712062335U, // <7,3,3,0>: Cost 3 vext3 RHS, <3,3,0,1> 2636368158U, // <7,3,3,1>: Cost 3 vext2 <3,1,7,3>, <3,1,7,3> 2637031791U, // <7,3,3,2>: Cost 3 vext2 <3,2,7,3>, <3,2,7,3> @@ -5405,18 +5405,18 @@ 1638320540U, // <7,3,3,u>: Cost 2 vext3 RHS, <3,3,3,3> 2712062416U, // <7,3,4,0>: Cost 3 vext3 RHS, <3,4,0,1> 2712062426U, // <7,3,4,1>: Cost 3 vext3 RHS, <3,4,1,2> - 2712062438U, // <7,3,4,2>: Cost 3 vext3 RHS, <3,4,2,5> + 2566981640U, // <7,3,4,2>: Cost 3 vext1 <2,7,3,4>, <2,7,3,4> 2712062447U, // <7,3,4,3>: Cost 3 vext3 RHS, <3,4,3,5> 2712062456U, // <7,3,4,4>: Cost 3 vext3 RHS, <3,4,4,5> 1638320642U, // <7,3,4,5>: Cost 2 vext3 RHS, <3,4,5,6> 2648313204U, // <7,3,4,6>: Cost 3 vext2 <5,1,7,3>, <4,6,4,6> - 3785804302U, // <7,3,4,7>: Cost 4 vext3 RHS, <3,4,7,0> + 3311446789U, // <7,3,4,7>: Cost 4 vrev <3,7,7,4> 1638320669U, // <7,3,4,u>: Cost 2 vext3 RHS, <3,4,u,6> 2602819686U, // <7,3,5,0>: Cost 3 vext1 , LHS 1574571728U, // <7,3,5,1>: Cost 2 vext2 <5,1,7,3>, <5,1,7,3> 2648977185U, // <7,3,5,2>: Cost 3 vext2 <5,2,7,3>, <5,2,7,3> 2705869378U, // <7,3,5,3>: Cost 3 vext3 <3,5,3,7>, <3,5,3,7> - 2712062538U, // <7,3,5,4>: Cost 3 vext3 RHS, <3,5,4,6> + 2237491947U, // <7,3,5,4>: Cost 3 vrev <3,7,4,5> 2706016852U, // <7,3,5,5>: Cost 3 vext3 <3,5,5,7>, <3,5,5,7> 2648313954U, // <7,3,5,6>: Cost 3 vext2 <5,1,7,3>, <5,6,7,0> 2692745823U, // <7,3,5,7>: Cost 3 vext3 <1,3,5,7>, <3,5,7,0> @@ -5436,18 +5436,18 @@ 2572978916U, // <7,3,7,3>: Cost 3 vext1 <3,7,3,7>, <3,7,3,7> 2693925611U, // <7,3,7,4>: Cost 3 vext3 <1,5,3,7>, <3,7,4,5> 2707344118U, // <7,3,7,5>: Cost 3 vext3 <3,7,5,7>, <3,7,5,7> - 2648315398U, // <7,3,7,6>: Cost 3 vext2 <5,1,7,3>, <7,6,5,4> + 2654950894U, // <7,3,7,6>: Cost 3 vext2 <6,2,7,3>, <7,6,2,7> 2648315500U, // <7,3,7,7>: Cost 3 vext2 <5,1,7,3>, <7,7,7,7> 2693925643U, // <7,3,7,u>: Cost 3 vext3 <1,5,3,7>, <3,7,u,1> - 2707639066U, // <7,3,u,0>: Cost 3 vext3 <3,u,0,7>, <3,u,0,7> - 1638320924U, // <7,3,u,1>: Cost 2 vext3 RHS, <3,u,1,0> + 2237221578U, // <7,3,u,0>: Cost 3 vrev <3,7,0,u> + 1638320926U, // <7,3,u,1>: Cost 2 vext3 RHS, <3,u,1,2> 1593153452U, // <7,3,u,2>: Cost 2 vext2 , 1638320540U, // <7,3,u,3>: Cost 2 vext3 RHS, <3,3,3,3> - 2707934014U, // <7,3,u,4>: Cost 3 vext3 <3,u,4,7>, <3,u,4,7> + 2237516526U, // <7,3,u,4>: Cost 3 vrev <3,7,4,u> 1638320966U, // <7,3,u,5>: Cost 2 vext3 RHS, <3,u,5,6> 2712062796U, // <7,3,u,6>: Cost 3 vext3 RHS, <3,u,6,3> 2692967250U, // <7,3,u,7>: Cost 3 vext3 <1,3,u,7>, <3,u,7,0> - 1638320987U, // <7,3,u,u>: Cost 2 vext3 RHS, <3,u,u,0> + 1638320989U, // <7,3,u,u>: Cost 2 vext3 RHS, <3,u,u,2> 2651635712U, // <7,4,0,0>: Cost 3 vext2 <5,6,7,4>, <0,0,0,0> 1577893990U, // <7,4,0,1>: Cost 2 vext2 <5,6,7,4>, LHS 2651635876U, // <7,4,0,2>: Cost 3 vext2 <5,6,7,4>, <0,2,0,2> @@ -5457,7 +5457,7 @@ 1638468508U, // <7,4,0,6>: Cost 2 vext3 RHS, <4,0,6,2> 3787795364U, // <7,4,0,7>: Cost 4 vext3 RHS, <4,0,7,1> 1640459181U, // <7,4,0,u>: Cost 2 vext3 RHS, <4,0,u,1> - 3712770824U, // <7,4,1,0>: Cost 4 vext2 <3,5,7,4>, <1,0,5,2> + 2651636470U, // <7,4,1,0>: Cost 3 vext2 <5,6,7,4>, <1,0,3,2> 2651636532U, // <7,4,1,1>: Cost 3 vext2 <5,6,7,4>, <1,1,1,1> 2712062922U, // <7,4,1,2>: Cost 3 vext3 RHS, <4,1,2,3> 2639029248U, // <7,4,1,3>: Cost 3 vext2 <3,5,7,4>, <1,3,5,7> @@ -5473,25 +5473,25 @@ 3716753194U, // <7,4,2,4>: Cost 4 vext2 <4,2,7,4>, <2,4,5,7> 2712063030U, // <7,4,2,5>: Cost 3 vext3 RHS, <4,2,5,3> 2712063036U, // <7,4,2,6>: Cost 3 vext3 RHS, <4,2,6,0> - 3785804872U, // <7,4,2,7>: Cost 4 vext3 RHS, <4,2,7,3> + 3773123658U, // <7,4,2,7>: Cost 4 vext3 <2,4,5,7>, <4,2,7,5> 2712063054U, // <7,4,2,u>: Cost 3 vext3 RHS, <4,2,u,0> 2651637910U, // <7,4,3,0>: Cost 3 vext2 <5,6,7,4>, <3,0,1,2> 3712772348U, // <7,4,3,1>: Cost 4 vext2 <3,5,7,4>, <3,1,3,5> - 2712063082U, // <7,4,3,2>: Cost 3 vext3 RHS, <4,3,2,1> + 3785804906U, // <7,4,3,2>: Cost 4 vext3 RHS, <4,3,2,1> 2651638172U, // <7,4,3,3>: Cost 3 vext2 <5,6,7,4>, <3,3,3,3> 2651638274U, // <7,4,3,4>: Cost 3 vext2 <5,6,7,4>, <3,4,5,6> 2639030883U, // <7,4,3,5>: Cost 3 vext2 <3,5,7,4>, <3,5,7,4> - 2712210578U, // <7,4,3,6>: Cost 3 vext3 RHS, <4,3,6,5> + 2712063122U, // <7,4,3,6>: Cost 3 vext3 RHS, <4,3,6,5> 3712772836U, // <7,4,3,7>: Cost 4 vext2 <3,5,7,4>, <3,7,3,7> 2641021782U, // <7,4,3,u>: Cost 3 vext2 <3,u,7,4>, <3,u,7,4> 2714053802U, // <7,4,4,0>: Cost 3 vext3 RHS, <4,4,0,2> 3785804978U, // <7,4,4,1>: Cost 4 vext3 RHS, <4,4,1,1> 3716754505U, // <7,4,4,2>: Cost 4 vext2 <4,2,7,4>, <4,2,7,4> - 3785804997U, // <7,4,4,3>: Cost 4 vext3 RHS, <4,4,3,2> + 3785804998U, // <7,4,4,3>: Cost 4 vext3 RHS, <4,4,3,3> 1638321360U, // <7,4,4,4>: Cost 2 vext3 RHS, <4,4,4,4> 1638468826U, // <7,4,4,5>: Cost 2 vext3 RHS, <4,4,5,5> 1638468836U, // <7,4,4,6>: Cost 2 vext3 RHS, <4,4,6,6> - 2651639254U, // <7,4,4,7>: Cost 3 vext2 <5,6,7,4>, <4,7,6,5> + 3785215214U, // <7,4,4,7>: Cost 4 vext3 <4,4,7,7>, <4,4,7,7> 1640459509U, // <7,4,4,u>: Cost 2 vext3 RHS, <4,4,u,5> 1517207654U, // <7,4,5,0>: Cost 2 vext1 <6,7,4,5>, LHS 2573034640U, // <7,4,5,1>: Cost 3 vext1 <3,7,4,5>, <1,5,3,7> @@ -5504,7 +5504,7 @@ 564579656U, // <7,4,5,u>: Cost 1 vext3 RHS, RHS 2712063307U, // <7,4,6,0>: Cost 3 vext3 RHS, <4,6,0,1> 3767668056U, // <7,4,6,1>: Cost 4 vext3 <1,5,3,7>, <4,6,1,5> - 2712210780U, // <7,4,6,2>: Cost 3 vext3 RHS, <4,6,2,0> + 2651640314U, // <7,4,6,2>: Cost 3 vext2 <5,6,7,4>, <6,2,7,3> 2655621708U, // <7,4,6,3>: Cost 3 vext2 <6,3,7,4>, <6,3,7,4> 1638468980U, // <7,4,6,4>: Cost 2 vext3 RHS, <4,6,4,6> 2712063358U, // <7,4,6,5>: Cost 3 vext3 RHS, <4,6,5,7> @@ -5522,7 +5522,7 @@ 2713538026U, // <7,4,7,u>: Cost 3 vext3 <4,7,u,7>, <4,7,u,7> 1517232230U, // <7,4,u,0>: Cost 2 vext1 <6,7,4,u>, LHS 1577899822U, // <7,4,u,1>: Cost 2 vext2 <5,6,7,4>, LHS - 2712063487U, // <7,4,u,2>: Cost 3 vext3 RHS, <4,u,2,1> + 2712063489U, // <7,4,u,2>: Cost 3 vext3 RHS, <4,u,2,3> 2573060846U, // <7,4,u,3>: Cost 3 vext1 <3,7,4,u>, <3,7,4,u> 1640312342U, // <7,4,u,4>: Cost 2 vext3 RHS, <4,u,4,6> 1638469146U, // <7,4,u,5>: Cost 2 vext3 RHS, <4,u,5,1> @@ -5530,54 +5530,54 @@ 2714054192U, // <7,4,u,7>: Cost 3 vext3 RHS, <4,u,7,5> 564579899U, // <7,4,u,u>: Cost 1 vext3 RHS, RHS 2579038310U, // <7,5,0,0>: Cost 3 vext1 <4,7,5,0>, LHS - 2712063560U, // <7,5,0,1>: Cost 3 vext3 RHS, <5,0,1,2> + 2636382310U, // <7,5,0,1>: Cost 3 vext2 <3,1,7,5>, LHS 2796339302U, // <7,5,0,2>: Cost 3 vuzpl <7,4,5,6>, LHS 3646810719U, // <7,5,0,3>: Cost 4 vext1 <3,7,5,0>, <3,5,7,0> 2712063586U, // <7,5,0,4>: Cost 3 vext3 RHS, <5,0,4,1> 2735951467U, // <7,5,0,5>: Cost 3 vext3 RHS, <5,0,5,1> 2735951476U, // <7,5,0,6>: Cost 3 vext3 RHS, <5,0,6,1> 2579043322U, // <7,5,0,7>: Cost 3 vext1 <4,7,5,0>, <7,0,1,2> - 2712063622U, // <7,5,0,u>: Cost 3 vext3 RHS, <5,0,u,1> - 2714054287U, // <7,5,1,0>: Cost 3 vext3 RHS, <5,1,0,1> - 3295396702U, // <7,5,1,1>: Cost 4 vrev <1,1,5,7> - 3766488736U, // <7,5,1,2>: Cost 4 vext3 <1,3,5,7>, <5,1,2,0> - 2859384934U, // <7,5,1,3>: Cost 3 vuzpr <6,7,4,5>, LHS - 2712063666U, // <7,5,1,4>: Cost 3 vext3 RHS, <5,1,4,0> + 2636382877U, // <7,5,0,u>: Cost 3 vext2 <3,1,7,5>, LHS + 2712211087U, // <7,5,1,0>: Cost 3 vext3 RHS, <5,1,0,1> + 3698180916U, // <7,5,1,1>: Cost 4 vext2 <1,1,7,5>, <1,1,1,1> + 3710124950U, // <7,5,1,2>: Cost 4 vext2 <3,1,7,5>, <1,2,3,0> + 2636383232U, // <7,5,1,3>: Cost 3 vext2 <3,1,7,5>, <1,3,5,7> + 2712211127U, // <7,5,1,4>: Cost 3 vext3 RHS, <5,1,4,5> 2590994128U, // <7,5,1,5>: Cost 3 vext1 <6,7,5,1>, <5,1,7,3> 2590995323U, // <7,5,1,6>: Cost 3 vext1 <6,7,5,1>, <6,7,5,1> 1638469328U, // <7,5,1,7>: Cost 2 vext3 RHS, <5,1,7,3> 1638469337U, // <7,5,1,u>: Cost 2 vext3 RHS, <5,1,u,3> 3785805536U, // <7,5,2,0>: Cost 4 vext3 RHS, <5,2,0,1> - 3766488808U, // <7,5,2,1>: Cost 4 vext3 <1,3,5,7>, <5,2,1,0> - 3302033032U, // <7,5,2,2>: Cost 4 vrev <2,2,5,7> + 3785805544U, // <7,5,2,1>: Cost 4 vext3 RHS, <5,2,1,0> + 3704817288U, // <7,5,2,2>: Cost 4 vext2 <2,2,7,5>, <2,2,5,7> 2712063742U, // <7,5,2,3>: Cost 3 vext3 RHS, <5,2,3,4> - 3785805571U, // <7,5,2,4>: Cost 4 vext3 RHS, <5,2,4,0> + 3716761386U, // <7,5,2,4>: Cost 4 vext2 <4,2,7,5>, <2,4,5,7> 2714054415U, // <7,5,2,5>: Cost 3 vext3 RHS, <5,2,5,3> 3774304024U, // <7,5,2,6>: Cost 4 vext3 <2,6,3,7>, <5,2,6,3> 2712063777U, // <7,5,2,7>: Cost 3 vext3 RHS, <5,2,7,3> 2712063787U, // <7,5,2,u>: Cost 3 vext3 RHS, <5,2,u,4> 3634888806U, // <7,5,3,0>: Cost 4 vext1 <1,7,5,3>, LHS - 2222982144U, // <7,5,3,1>: Cost 3 vrev <1,3,5,7> - 2228954841U, // <7,5,3,2>: Cost 3 vrev <2,3,5,7> - 3308669362U, // <7,5,3,3>: Cost 4 vrev <3,3,5,7> + 2636384544U, // <7,5,3,1>: Cost 3 vext2 <3,1,7,5>, <3,1,7,5> + 3710790001U, // <7,5,3,2>: Cost 4 vext2 <3,2,7,5>, <3,2,7,5> + 3710126492U, // <7,5,3,3>: Cost 4 vext2 <3,1,7,5>, <3,3,3,3> 3634892086U, // <7,5,3,4>: Cost 4 vext1 <1,7,5,3>, RHS 2639039076U, // <7,5,3,5>: Cost 3 vext2 <3,5,7,5>, <3,5,7,5> 3713444533U, // <7,5,3,6>: Cost 4 vext2 <3,6,7,5>, <3,6,7,5> 2693926767U, // <7,5,3,7>: Cost 3 vext3 <1,5,3,7>, <5,3,7,0> 2712063864U, // <7,5,3,u>: Cost 3 vext3 RHS, <5,3,u,0> 2579071078U, // <7,5,4,0>: Cost 3 vext1 <4,7,5,4>, LHS - 2735951762U, // <7,5,4,1>: Cost 3 vext3 RHS, <5,4,1,u> - 3303360298U, // <7,5,4,2>: Cost 4 vrev <2,4,5,7> - 2712063902U, // <7,5,4,3>: Cost 3 vext3 RHS, <5,4,3,2> + 3646841856U, // <7,5,4,1>: Cost 4 vext1 <3,7,5,4>, <1,3,5,7> + 3716762698U, // <7,5,4,2>: Cost 4 vext2 <4,2,7,5>, <4,2,7,5> + 3646843491U, // <7,5,4,3>: Cost 4 vext1 <3,7,5,4>, <3,5,7,4> 2579074358U, // <7,5,4,4>: Cost 3 vext1 <4,7,5,4>, RHS - 2712063924U, // <7,5,4,5>: Cost 3 vext3 RHS, <5,4,5,6> + 2636385590U, // <7,5,4,5>: Cost 3 vext2 <3,1,7,5>, RHS 2645675406U, // <7,5,4,6>: Cost 3 vext2 <4,6,7,5>, <4,6,7,5> - 2712211397U, // <7,5,4,7>: Cost 3 vext3 RHS, <5,4,7,5> - 2712063947U, // <7,5,4,u>: Cost 3 vext3 RHS, <5,4,u,2> + 1638322118U, // <7,5,4,7>: Cost 2 vext3 RHS, <5,4,7,6> + 1638469583U, // <7,5,4,u>: Cost 2 vext3 RHS, <5,4,u,6> 2714054611U, // <7,5,5,0>: Cost 3 vext3 RHS, <5,5,0,1> 2652974800U, // <7,5,5,1>: Cost 3 vext2 <5,u,7,5>, <5,1,7,3> - 3785805799U, // <7,5,5,2>: Cost 4 vext3 RHS, <5,5,2,3> - 2236254804U, // <7,5,5,3>: Cost 3 vrev <3,5,5,7> + 3710127905U, // <7,5,5,2>: Cost 4 vext2 <3,1,7,5>, <5,2,7,3> + 3785805808U, // <7,5,5,3>: Cost 4 vext3 RHS, <5,5,3,3> 2712211450U, // <7,5,5,4>: Cost 3 vext3 RHS, <5,5,4,4> 1638322180U, // <7,5,5,5>: Cost 2 vext3 RHS, <5,5,5,5> 2712064014U, // <7,5,5,6>: Cost 3 vext3 RHS, <5,5,6,6> @@ -5585,7 +5585,7 @@ 1638469665U, // <7,5,5,u>: Cost 2 vext3 RHS, <5,5,u,7> 2712064036U, // <7,5,6,0>: Cost 3 vext3 RHS, <5,6,0,1> 2714054707U, // <7,5,6,1>: Cost 3 vext3 RHS, <5,6,1,7> - 3304687564U, // <7,5,6,2>: Cost 4 vrev <2,6,5,7> + 3785805879U, // <7,5,6,2>: Cost 4 vext3 RHS, <5,6,2,2> 2712064066U, // <7,5,6,3>: Cost 3 vext3 RHS, <5,6,3,4> 2712064076U, // <7,5,6,4>: Cost 3 vext3 RHS, <5,6,4,5> 2714054743U, // <7,5,6,5>: Cost 3 vext3 RHS, <5,6,5,7> @@ -5602,95 +5602,95 @@ 2712211636U, // <7,5,7,7>: Cost 3 vext3 RHS, <5,7,7,1> 1638469823U, // <7,5,7,u>: Cost 2 vext3 RHS, <5,7,u,3> 1511333990U, // <7,5,u,0>: Cost 2 vext1 <5,7,5,u>, LHS - 2226300309U, // <7,5,u,1>: Cost 3 vrev <1,u,5,7> - 2585077352U, // <7,5,u,2>: Cost 3 vext1 <5,7,5,u>, <2,2,2,2> + 2636388142U, // <7,5,u,1>: Cost 3 vext2 <3,1,7,5>, LHS + 2712211671U, // <7,5,u,2>: Cost 3 vext3 RHS, <5,u,2,0> 2573134583U, // <7,5,u,3>: Cost 3 vext1 <3,7,5,u>, <3,7,5,u> 1511337270U, // <7,5,u,4>: Cost 2 vext1 <5,7,5,u>, RHS 1638469881U, // <7,5,u,5>: Cost 2 vext3 RHS, <5,u,5,7> 2712064258U, // <7,5,u,6>: Cost 3 vext3 RHS, <5,u,6,7> 1638469892U, // <7,5,u,7>: Cost 2 vext3 RHS, <5,u,7,0> 1638469904U, // <7,5,u,u>: Cost 2 vext3 RHS, <5,u,u,3> - 2585084006U, // <7,6,0,0>: Cost 3 vext1 <5,7,6,0>, LHS - 2712064289U, // <7,6,0,1>: Cost 3 vext3 RHS, <6,0,1,2> + 2650324992U, // <7,6,0,0>: Cost 3 vext2 <5,4,7,6>, <0,0,0,0> + 1576583270U, // <7,6,0,1>: Cost 2 vext2 <5,4,7,6>, LHS 2712064300U, // <7,6,0,2>: Cost 3 vext3 RHS, <6,0,2,4> - 3785806130U, // <7,6,0,3>: Cost 4 vext3 RHS, <6,0,3,1> + 2255295336U, // <7,6,0,3>: Cost 3 vrev <6,7,3,0> 2712064316U, // <7,6,0,4>: Cost 3 vext3 RHS, <6,0,4,2> 2585088098U, // <7,6,0,5>: Cost 3 vext1 <5,7,6,0>, <5,6,7,0> 2735952204U, // <7,6,0,6>: Cost 3 vext3 RHS, <6,0,6,0> 2712211799U, // <7,6,0,7>: Cost 3 vext3 RHS, <6,0,7,2> - 2712064352U, // <7,6,0,u>: Cost 3 vext3 RHS, <6,0,u,2> - 2579120230U, // <7,6,1,0>: Cost 3 vext1 <4,7,6,1>, LHS - 3785806193U, // <7,6,1,1>: Cost 4 vext3 RHS, <6,1,1,1> - 3774304633U, // <7,6,1,2>: Cost 4 vext3 <2,6,3,7>, <6,1,2,0> - 3766489479U, // <7,6,1,3>: Cost 4 vext3 <1,3,5,7>, <6,1,3,5> + 1576583837U, // <7,6,0,u>: Cost 2 vext2 <5,4,7,6>, LHS + 1181340494U, // <7,6,1,0>: Cost 2 vrev <6,7,0,1> + 2650325812U, // <7,6,1,1>: Cost 3 vext2 <5,4,7,6>, <1,1,1,1> + 2650325910U, // <7,6,1,2>: Cost 3 vext2 <5,4,7,6>, <1,2,3,0> + 2650325976U, // <7,6,1,3>: Cost 3 vext2 <5,4,7,6>, <1,3,1,3> 2579123510U, // <7,6,1,4>: Cost 3 vext1 <4,7,6,1>, RHS - 3767669143U, // <7,6,1,5>: Cost 4 vext3 <1,5,3,7>, <6,1,5,3> + 2650326160U, // <7,6,1,5>: Cost 3 vext2 <5,4,7,6>, <1,5,3,7> 2714055072U, // <7,6,1,6>: Cost 3 vext3 RHS, <6,1,6,3> 2712064425U, // <7,6,1,7>: Cost 3 vext3 RHS, <6,1,7,3> - 2579126062U, // <7,6,1,u>: Cost 3 vext1 <4,7,6,1>, LHS - 2714055097U, // <7,6,2,0>: Cost 3 vext3 RHS, <6,2,0,1> + 1181930390U, // <7,6,1,u>: Cost 2 vrev <6,7,u,1> + 2712211897U, // <7,6,2,0>: Cost 3 vext3 RHS, <6,2,0,1> 2714055108U, // <7,6,2,1>: Cost 3 vext3 RHS, <6,2,1,3> - 3785806284U, // <7,6,2,2>: Cost 4 vext3 RHS, <6,2,2,2> - 2631747306U, // <7,6,2,3>: Cost 3 vext2 <2,3,7,6>, <2,3,7,6> - 2712064476U, // <7,6,2,4>: Cost 3 vext3 RHS, <6,2,4,0> + 2650326632U, // <7,6,2,2>: Cost 3 vext2 <5,4,7,6>, <2,2,2,2> + 2650326694U, // <7,6,2,3>: Cost 3 vext2 <5,4,7,6>, <2,3,0,1> + 2714055137U, // <7,6,2,4>: Cost 3 vext3 RHS, <6,2,4,5> 2714055148U, // <7,6,2,5>: Cost 3 vext3 RHS, <6,2,5,7> - 2591077253U, // <7,6,2,6>: Cost 3 vext1 <6,7,6,2>, <6,7,6,2> + 2650326970U, // <7,6,2,6>: Cost 3 vext2 <5,4,7,6>, <2,6,3,7> 1638470138U, // <7,6,2,7>: Cost 2 vext3 RHS, <6,2,7,3> 1638470147U, // <7,6,2,u>: Cost 2 vext3 RHS, <6,2,u,3> - 3640934502U, // <7,6,3,0>: Cost 4 vext1 <2,7,6,3>, LHS - 3296797705U, // <7,6,3,1>: Cost 4 vrev <1,3,6,7> - 2229028578U, // <7,6,3,2>: Cost 3 vrev <2,3,6,7> - 3646909179U, // <7,6,3,3>: Cost 4 vext1 <3,7,6,3>, <3,7,6,3> + 2650327190U, // <7,6,3,0>: Cost 3 vext2 <5,4,7,6>, <3,0,1,2> + 2255172441U, // <7,6,3,1>: Cost 3 vrev <6,7,1,3> + 2255246178U, // <7,6,3,2>: Cost 3 vrev <6,7,2,3> + 2650327452U, // <7,6,3,3>: Cost 3 vext2 <5,4,7,6>, <3,3,3,3> 2712064562U, // <7,6,3,4>: Cost 3 vext3 RHS, <6,3,4,5> - 3785806392U, // <7,6,3,5>: Cost 4 vext3 RHS, <6,3,5,2> + 2650327627U, // <7,6,3,5>: Cost 3 vext2 <5,4,7,6>, <3,5,4,7> 3713452726U, // <7,6,3,6>: Cost 4 vext2 <3,6,7,6>, <3,6,7,6> 2700563016U, // <7,6,3,7>: Cost 3 vext3 <2,6,3,7>, <6,3,7,0> 2712064593U, // <7,6,3,u>: Cost 3 vext3 RHS, <6,3,u,0> - 2585116774U, // <7,6,4,0>: Cost 3 vext1 <5,7,6,4>, LHS + 2650327954U, // <7,6,4,0>: Cost 3 vext2 <5,4,7,6>, <4,0,5,1> 2735952486U, // <7,6,4,1>: Cost 3 vext3 RHS, <6,4,1,3> - 2712064620U, // <7,6,4,2>: Cost 3 vext3 RHS, <6,4,2,0> - 3785806454U, // <7,6,4,3>: Cost 4 vext3 RHS, <6,4,3,1> + 2735952497U, // <7,6,4,2>: Cost 3 vext3 RHS, <6,4,2,5> + 2255328108U, // <7,6,4,3>: Cost 3 vrev <6,7,3,4> 2712212100U, // <7,6,4,4>: Cost 3 vext3 RHS, <6,4,4,6> - 2712064653U, // <7,6,4,5>: Cost 3 vext3 RHS, <6,4,5,6> + 1576586550U, // <7,6,4,5>: Cost 2 vext2 <5,4,7,6>, RHS 2714055312U, // <7,6,4,6>: Cost 3 vext3 RHS, <6,4,6,0> 2712212126U, // <7,6,4,7>: Cost 3 vext3 RHS, <6,4,7,5> - 2712064674U, // <7,6,4,u>: Cost 3 vext3 RHS, <6,4,u,0> + 1576586793U, // <7,6,4,u>: Cost 2 vext2 <5,4,7,6>, RHS 2579152998U, // <7,6,5,0>: Cost 3 vext1 <4,7,6,5>, LHS - 3785806519U, // <7,6,5,1>: Cost 4 vext3 RHS, <6,5,1,3> + 2650328784U, // <7,6,5,1>: Cost 3 vext2 <5,4,7,6>, <5,1,7,3> 2714055364U, // <7,6,5,2>: Cost 3 vext3 RHS, <6,5,2,7> - 2236328541U, // <7,6,5,3>: Cost 3 vrev <3,5,6,7> - 94817590U, // <7,6,5,4>: Cost 1 vrev RHS - 2555269218U, // <7,6,5,5>: Cost 3 vext1 <0,7,6,5>, <5,6,7,0> - 2651656296U, // <7,6,5,6>: Cost 3 vext2 <5,6,7,6>, <5,6,7,6> + 3785806538U, // <7,6,5,3>: Cost 4 vext3 RHS, <6,5,3,4> + 1576587206U, // <7,6,5,4>: Cost 2 vext2 <5,4,7,6>, <5,4,7,6> + 2650329092U, // <7,6,5,5>: Cost 3 vext2 <5,4,7,6>, <5,5,5,5> + 2650329186U, // <7,6,5,6>: Cost 3 vext2 <5,4,7,6>, <5,6,7,0> 2712064753U, // <7,6,5,7>: Cost 3 vext3 RHS, <6,5,7,7> - 118708378U, // <7,6,5,u>: Cost 1 vrev RHS + 1181963162U, // <7,6,5,u>: Cost 2 vrev <6,7,u,5> 2714055421U, // <7,6,6,0>: Cost 3 vext3 RHS, <6,6,0,1> 2714055432U, // <7,6,6,1>: Cost 3 vext3 RHS, <6,6,1,3> - 2652983802U, // <7,6,6,2>: Cost 3 vext2 <5,u,7,6>, <6,2,7,3> - 2236992174U, // <7,6,6,3>: Cost 3 vrev <3,6,6,7> + 2650329594U, // <7,6,6,2>: Cost 3 vext2 <5,4,7,6>, <6,2,7,3> + 3785806619U, // <7,6,6,3>: Cost 4 vext3 RHS, <6,6,3,4> 2712212260U, // <7,6,6,4>: Cost 3 vext3 RHS, <6,6,4,4> 2714055472U, // <7,6,6,5>: Cost 3 vext3 RHS, <6,6,5,7> 1638323000U, // <7,6,6,6>: Cost 2 vext3 RHS, <6,6,6,6> 1638470466U, // <7,6,6,7>: Cost 2 vext3 RHS, <6,6,7,7> 1638470475U, // <7,6,6,u>: Cost 2 vext3 RHS, <6,6,u,7> 1638323022U, // <7,6,7,0>: Cost 2 vext3 RHS, <6,7,0,1> - 2712064855U, // <7,6,7,1>: Cost 3 vext3 RHS, <6,7,1,1> + 2712064854U, // <7,6,7,1>: Cost 3 vext3 RHS, <6,7,1,0> 2712064865U, // <7,6,7,2>: Cost 3 vext3 RHS, <6,7,2,2> 2712064872U, // <7,6,7,3>: Cost 3 vext3 RHS, <6,7,3,0> 1638323062U, // <7,6,7,4>: Cost 2 vext3 RHS, <6,7,4,5> - 2712064895U, // <7,6,7,5>: Cost 3 vext3 RHS, <6,7,5,5> + 2712064894U, // <7,6,7,5>: Cost 3 vext3 RHS, <6,7,5,4> 2712064905U, // <7,6,7,6>: Cost 3 vext3 RHS, <6,7,6,6> - 2712064914U, // <7,6,7,7>: Cost 3 vext3 RHS, <6,7,7,6> + 2712064915U, // <7,6,7,7>: Cost 3 vext3 RHS, <6,7,7,7> 1638323094U, // <7,6,7,u>: Cost 2 vext3 RHS, <6,7,u,1> 1638470559U, // <7,6,u,0>: Cost 2 vext3 RHS, <6,u,0,1> - 2712064937U, // <7,6,u,1>: Cost 3 vext3 RHS, <6,u,1,2> - 2712064944U, // <7,6,u,2>: Cost 3 vext3 RHS, <6,u,2,0> + 1576589102U, // <7,6,u,1>: Cost 2 vext2 <5,4,7,6>, LHS + 2712212402U, // <7,6,u,2>: Cost 3 vext3 RHS, <6,u,2,2> 2712212409U, // <7,6,u,3>: Cost 3 vext3 RHS, <6,u,3,0> - 96808489U, // <7,6,u,4>: Cost 1 vrev RHS - 2712064977U, // <7,6,u,5>: Cost 3 vext3 RHS, <6,u,5,6> + 1638470599U, // <7,6,u,4>: Cost 2 vext3 RHS, <6,u,4,5> + 1576589466U, // <7,6,u,5>: Cost 2 vext2 <5,4,7,6>, RHS 1638323000U, // <7,6,u,6>: Cost 2 vext3 RHS, <6,6,6,6> 1638470624U, // <7,6,u,7>: Cost 2 vext3 RHS, <6,u,7,3> - 120699277U, // <7,6,u,u>: Cost 1 vrev RHS + 1638470631U, // <7,6,u,u>: Cost 2 vext3 RHS, <6,u,u,1> 2712065007U, // <7,7,0,0>: Cost 3 vext3 RHS, <7,0,0,0> 1638323194U, // <7,7,0,1>: Cost 2 vext3 RHS, <7,0,1,2> 2712065025U, // <7,7,0,2>: Cost 3 vext3 RHS, <7,0,2,0> @@ -5700,7 +5700,7 @@ 2591134604U, // <7,7,0,6>: Cost 3 vext1 <6,7,7,0>, <6,7,7,0> 2591134714U, // <7,7,0,7>: Cost 3 vext1 <6,7,7,0>, <7,0,1,2> 1638323257U, // <7,7,0,u>: Cost 2 vext3 RHS, <7,0,u,2> - 2585165926U, // <7,7,1,0>: Cost 3 vext1 <5,7,7,1>, LHS + 2712065091U, // <7,7,1,0>: Cost 3 vext3 RHS, <7,1,0,3> 2712065098U, // <7,7,1,1>: Cost 3 vext3 RHS, <7,1,1,1> 2712065109U, // <7,7,1,2>: Cost 3 vext3 RHS, <7,1,2,3> 2692748384U, // <7,7,1,3>: Cost 3 vext3 <1,3,5,7>, <7,1,3,5> @@ -5720,13 +5720,13 @@ 2701890780U, // <7,7,2,u>: Cost 3 vext3 <2,u,3,7>, <7,2,u,3> 2712065251U, // <7,7,3,0>: Cost 3 vext3 RHS, <7,3,0,1> 3766490350U, // <7,7,3,1>: Cost 4 vext3 <1,3,5,7>, <7,3,1,3> - 2712065269U, // <7,7,3,2>: Cost 3 vext3 RHS, <7,3,2,1> + 3774305530U, // <7,7,3,2>: Cost 4 vext3 <2,6,3,7>, <7,3,2,6> 2637728196U, // <7,7,3,3>: Cost 3 vext2 <3,3,7,7>, <3,3,7,7> 2712065291U, // <7,7,3,4>: Cost 3 vext3 RHS, <7,3,4,5> - 2693928208U, // <7,7,3,5>: Cost 3 vext3 <1,5,3,7>, <7,3,5,1> - 2700563738U, // <7,7,3,6>: Cost 3 vext3 <2,6,3,7>, <7,3,6,2> + 2585186486U, // <7,7,3,5>: Cost 3 vext1 <5,7,7,3>, <5,7,7,3> + 2639719095U, // <7,7,3,6>: Cost 3 vext2 <3,6,7,7>, <3,6,7,7> 2640382728U, // <7,7,3,7>: Cost 3 vext2 <3,7,7,7>, <3,7,7,7> - 2701890860U, // <7,7,3,u>: Cost 3 vext3 <2,u,3,7>, <7,3,u,2> + 2641046361U, // <7,7,3,u>: Cost 3 vext2 <3,u,7,7>, <3,u,7,7> 2712212792U, // <7,7,4,0>: Cost 3 vext3 RHS, <7,4,0,5> 3646989312U, // <7,7,4,1>: Cost 4 vext1 <3,7,7,4>, <1,3,5,7> 3785807176U, // <7,7,4,2>: Cost 4 vext3 RHS, <7,4,2,3> @@ -5738,44 +5738,44 @@ 1638323585U, // <7,7,4,u>: Cost 2 vext3 RHS, <7,4,u,6> 2585198694U, // <7,7,5,0>: Cost 3 vext1 <5,7,7,5>, LHS 2712212884U, // <7,7,5,1>: Cost 3 vext3 RHS, <7,5,1,7> - 3771798936U, // <7,7,5,2>: Cost 4 vext3 <2,2,5,7>, <7,5,2,2> - 2692748704U, // <7,7,5,3>: Cost 3 vext3 <1,3,5,7>, <7,5,3,1> - 2585201974U, // <7,7,5,4>: Cost 3 vext1 <5,7,7,5>, RHS + 3711471393U, // <7,7,5,2>: Cost 4 vext2 <3,3,7,7>, <5,2,7,3> + 2649673590U, // <7,7,5,3>: Cost 3 vext2 <5,3,7,7>, <5,3,7,7> + 2712065455U, // <7,7,5,4>: Cost 3 vext3 RHS, <7,5,4,7> 1577259032U, // <7,7,5,5>: Cost 2 vext2 <5,5,7,7>, <5,5,7,7> 2712065473U, // <7,7,5,6>: Cost 3 vext3 RHS, <7,5,6,7> 2712212936U, // <7,7,5,7>: Cost 3 vext3 RHS, <7,5,7,5> 1579249931U, // <7,7,5,u>: Cost 2 vext2 <5,u,7,7>, <5,u,7,7> 2591178854U, // <7,7,6,0>: Cost 3 vext1 <6,7,7,6>, LHS - 3785807333U, // <7,7,6,1>: Cost 4 vext3 RHS, <7,6,1,7> + 2735953374U, // <7,7,6,1>: Cost 3 vext3 RHS, <7,6,1,0> 2712212974U, // <7,7,6,2>: Cost 3 vext3 RHS, <7,6,2,7> - 3766564337U, // <7,7,6,3>: Cost 4 vext3 <1,3,6,7>, <7,6,3,1> + 2655646287U, // <7,7,6,3>: Cost 3 vext2 <6,3,7,7>, <6,3,7,7> 2591182134U, // <7,7,6,4>: Cost 3 vext1 <6,7,7,6>, RHS - 1638323718U, // <7,7,6,5>: Cost 2 vext3 RHS, <7,6,5,4> + 2656973553U, // <7,7,6,5>: Cost 3 vext2 <6,5,7,7>, <6,5,7,7> 1583895362U, // <7,7,6,6>: Cost 2 vext2 <6,6,7,7>, <6,6,7,7> 2712065556U, // <7,7,6,7>: Cost 3 vext3 RHS, <7,6,7,0> - 1640314401U, // <7,7,6,u>: Cost 2 vext3 RHS, <7,6,u,4> + 1585222628U, // <7,7,6,u>: Cost 2 vext2 <6,u,7,7>, <6,u,7,7> 1523417190U, // <7,7,7,0>: Cost 2 vext1 <7,7,7,7>, LHS - 2597159732U, // <7,7,7,1>: Cost 3 vext1 <7,7,7,7>, <1,1,1,1> + 2597159670U, // <7,7,7,1>: Cost 3 vext1 <7,7,7,7>, <1,0,3,2> 2597160552U, // <7,7,7,2>: Cost 3 vext1 <7,7,7,7>, <2,2,2,2> 2597161110U, // <7,7,7,3>: Cost 3 vext1 <7,7,7,7>, <3,0,1,2> 1523420470U, // <7,7,7,4>: Cost 2 vext1 <7,7,7,7>, RHS 2651002296U, // <7,7,7,5>: Cost 3 vext2 <5,5,7,7>, <7,5,5,7> - 2712065633U, // <7,7,7,6>: Cost 3 vext3 RHS, <7,7,6,5> + 2657637906U, // <7,7,7,6>: Cost 3 vext2 <6,6,7,7>, <7,6,6,7> 363253046U, // <7,7,7,7>: Cost 1 vdup3 RHS 363253046U, // <7,7,7,u>: Cost 1 vdup3 RHS 1523417190U, // <7,7,u,0>: Cost 2 vext1 <7,7,7,7>, LHS 1638471298U, // <7,7,u,1>: Cost 2 vext3 RHS, <7,u,1,2> - 2712213130U, // <7,7,u,2>: Cost 3 vext3 RHS, <7,u,2,1> - 2692970131U, // <7,7,u,3>: Cost 3 vext3 <1,3,u,7>, <7,u,3,1> + 2712213132U, // <7,7,u,2>: Cost 3 vext3 RHS, <7,u,2,3> + 2712213138U, // <7,7,u,3>: Cost 3 vext3 RHS, <7,u,3,0> 1523420470U, // <7,7,u,4>: Cost 2 vext1 <7,7,7,7>, RHS - 1638471336U, // <7,7,u,5>: Cost 2 vext3 RHS, <7,u,5,4> + 1638471338U, // <7,7,u,5>: Cost 2 vext3 RHS, <7,u,5,6> 1595840756U, // <7,7,u,6>: Cost 2 vext2 , 363253046U, // <7,7,u,7>: Cost 1 vdup3 RHS 363253046U, // <7,7,u,u>: Cost 1 vdup3 RHS 1638318080U, // <7,u,0,0>: Cost 2 vext3 RHS, <0,0,0,0> 1638323923U, // <7,u,0,1>: Cost 2 vext3 RHS, 1662211804U, // <7,u,0,2>: Cost 2 vext3 RHS, - 2712065763U, // <7,u,0,3>: Cost 3 vext3 RHS, + 1638323941U, // <7,u,0,3>: Cost 2 vext3 RHS, 2712065773U, // <7,u,0,4>: Cost 3 vext3 RHS, 1662359286U, // <7,u,0,5>: Cost 2 vext3 RHS, 1662359296U, // <7,u,0,6>: Cost 2 vext3 RHS, @@ -5791,11 +5791,11 @@ 1640462171U, // <7,u,1,7>: Cost 2 vext3 RHS, 564582244U, // <7,u,1,u>: Cost 1 vext3 RHS, LHS 1638318244U, // <7,u,2,0>: Cost 2 vext3 RHS, <0,2,0,2> - 1638324083U, // <7,u,2,1>: Cost 2 vext3 RHS, + 2712065907U, // <7,u,2,1>: Cost 3 vext3 RHS, 1638319720U, // <7,u,2,2>: Cost 2 vext3 RHS, <2,2,2,2> 1638324101U, // <7,u,2,3>: Cost 2 vext3 RHS, 1638318284U, // <7,u,2,4>: Cost 2 vext3 RHS, <0,2,4,6> - 2712065950U, // <7,u,2,5>: Cost 3 vext3 RHS, + 2712065947U, // <7,u,2,5>: Cost 3 vext3 RHS, 2700564387U, // <7,u,2,6>: Cost 3 vext3 <2,6,3,7>, 1640314796U, // <7,u,2,7>: Cost 2 vext3 RHS, 1638324146U, // <7,u,2,u>: Cost 2 vext3 RHS, @@ -5811,17 +5811,17 @@ 2712066061U, // <7,u,4,0>: Cost 3 vext3 RHS, 1662212122U, // <7,u,4,1>: Cost 2 vext3 RHS, 1662212132U, // <7,u,4,2>: Cost 2 vext3 RHS, - 2712066089U, // <7,u,4,3>: Cost 3 vext3 RHS, + 2712066092U, // <7,u,4,3>: Cost 3 vext3 RHS, 1638321360U, // <7,u,4,4>: Cost 2 vext3 RHS, <4,4,4,4> 1638324287U, // <7,u,4,5>: Cost 2 vext3 RHS, 1662359624U, // <7,u,4,6>: Cost 2 vext3 RHS, - 2987183432U, // <7,u,4,7>: Cost 3 vzipr <5,6,7,4>, RHS + 1640314961U, // <7,u,4,7>: Cost 2 vext3 RHS, 1638324314U, // <7,u,4,u>: Cost 2 vext3 RHS, 1517502566U, // <7,u,5,0>: Cost 2 vext1 <6,7,u,5>, LHS 1574612693U, // <7,u,5,1>: Cost 2 vext2 <5,1,7,u>, <5,1,7,u> 2712066162U, // <7,u,5,2>: Cost 3 vext3 RHS, 1638324351U, // <7,u,5,3>: Cost 2 vext3 RHS, - 94965064U, // <7,u,5,4>: Cost 1 vrev RHS + 1576603592U, // <7,u,5,4>: Cost 2 vext2 <5,4,7,u>, <5,4,7,u> 1577267225U, // <7,u,5,5>: Cost 2 vext2 <5,5,7,u>, <5,5,7,u> 564582554U, // <7,u,5,6>: Cost 1 vext3 RHS, RHS 1640462499U, // <7,u,5,7>: Cost 2 vext3 RHS, @@ -5831,7 +5831,7 @@ 1581249023U, // <7,u,6,2>: Cost 2 vext2 <6,2,7,u>, <6,2,7,u> 1638324432U, // <7,u,6,3>: Cost 2 vext3 RHS, 1638468980U, // <7,u,6,4>: Cost 2 vext3 RHS, <4,6,4,6> - 1638471903U, // <7,u,6,5>: Cost 2 vext3 RHS, + 2712066274U, // <7,u,6,5>: Cost 3 vext3 RHS, 1583903555U, // <7,u,6,6>: Cost 2 vext2 <6,6,7,u>, <6,6,7,u> 1640315117U, // <7,u,6,7>: Cost 2 vext3 RHS, 1638324477U, // <7,u,6,u>: Cost 2 vext3 RHS, @@ -5845,10 +5845,10 @@ 363253046U, // <7,u,7,7>: Cost 1 vdup3 RHS 363253046U, // <7,u,7,u>: Cost 1 vdup3 RHS 1638324561U, // <7,u,u,0>: Cost 2 vext3 RHS, - 1638324569U, // <7,u,u,1>: Cost 2 vext3 RHS, + 1638324571U, // <7,u,u,1>: Cost 2 vext3 RHS, 564582757U, // <7,u,u,2>: Cost 1 vext3 RHS, LHS 1638324587U, // <7,u,u,3>: Cost 2 vext3 RHS, - 96955963U, // <7,u,u,4>: Cost 1 vrev RHS + 1638324601U, // <7,u,u,4>: Cost 2 vext3 RHS, 1638324611U, // <7,u,u,5>: Cost 2 vext3 RHS, 564582797U, // <7,u,u,6>: Cost 1 vext3 RHS, RHS 363253046U, // <7,u,u,7>: Cost 1 vdup3 RHS @@ -5856,11 +5856,11 @@ 135053414U, // : Cost 1 vdup0 LHS 1611489290U, // : Cost 2 vext3 LHS, <0,0,1,1> 1611489300U, // : Cost 2 vext3 LHS, <0,0,2,2> - 2232576147U, // : Cost 3 vrev <3,0,0,u> + 2568054923U, // : Cost 3 vext1 <3,0,0,0>, <3,0,0,0> 1481706806U, // : Cost 2 vext1 <0,u,0,0>, RHS 2555449040U, // : Cost 3 vext1 <0,u,0,0>, <5,1,7,3> 2591282078U, // : Cost 3 vext1 <6,u,0,0>, <6,u,0,0> - 2256466935U, // : Cost 3 vrev <7,0,0,u> + 2591945711U, // : Cost 3 vext1 <7,0,0,0>, <7,0,0,0> 135053414U, // : Cost 1 vdup0 LHS 1493655654U, // : Cost 2 vext1 <2,u,0,1>, LHS 1860550758U, // : Cost 2 vzipl LHS, LHS @@ -5882,28 +5882,28 @@ 1611489516U, // : Cost 2 vext3 LHS, <0,2,u,2> 2954067968U, // : Cost 3 vzipr LHS, <0,0,0,0> 2685231356U, // : Cost 3 vext3 LHS, <0,3,1,0> - 1154852525U, // : Cost 2 vrev <2,3,0,u> + 72589981U, // : Cost 1 vrev LHS 2625137052U, // : Cost 3 vext2 <1,2,u,0>, <3,3,3,3> 2625137154U, // : Cost 3 vext2 <1,2,u,0>, <3,4,5,6> 2639071848U, // : Cost 3 vext2 <3,5,u,0>, <3,5,u,0> - 2586661226U, // : Cost 3 vext1 <6,1,0,3>, <6,1,0,3> - 2258457834U, // : Cost 3 vrev <7,3,0,u> - 1567320923U, // : Cost 2 vext2 <3,u,u,0>, <3,u,u,0> + 2639735481U, // : Cost 3 vext2 <3,6,u,0>, <3,6,u,0> + 2597279354U, // : Cost 3 vext1 <7,u,0,3>, <7,u,0,3> + 73032403U, // : Cost 1 vrev LHS 2687074636U, // : Cost 3 vext3 <0,4,0,u>, <0,4,0,u> 1611489618U, // : Cost 2 vext3 LHS, <0,4,1,5> 1611489628U, // : Cost 2 vext3 LHS, <0,4,2,6> - 2235230679U, // : Cost 3 vrev <3,4,0,u> + 3629222038U, // : Cost 4 vext1 <0,u,0,4>, <3,0,1,2> 2555481398U, // : Cost 3 vext1 <0,u,0,4>, RHS 1551396150U, // : Cost 2 vext2 <1,2,u,0>, RHS 2651680116U, // : Cost 3 vext2 <5,6,u,0>, <4,6,4,6> - 2259121467U, // : Cost 3 vrev <7,4,0,u> + 2646150600U, // : Cost 3 vext2 <4,7,5,0>, <4,7,5,0> 1611932050U, // : Cost 2 vext3 LHS, <0,4,u,6> - 2573402214U, // : Cost 3 vext1 <3,u,0,5>, LHS + 2561458278U, // : Cost 3 vext1 <1,u,0,5>, LHS 1863532646U, // : Cost 2 vzipl RHS, LHS 2712068526U, // : Cost 3 vext3 RHS, <0,5,2,7> - 2573404310U, // : Cost 3 vext1 <3,u,0,5>, <3,0,1,2> - 2573405494U, // : Cost 3 vext1 <3,u,0,5>, RHS - 2247839706U, // : Cost 3 vrev <5,5,0,u> + 2649689976U, // : Cost 3 vext2 <5,3,u,0>, <5,3,u,0> + 2220237489U, // : Cost 3 vrev <0,u,4,5> + 2651680772U, // : Cost 3 vext2 <5,6,u,0>, <5,5,5,5> 1577939051U, // : Cost 2 vext2 <5,6,u,0>, <5,6,u,0> 2830077238U, // : Cost 3 vuzpr <1,u,3,0>, RHS 1579266317U, // : Cost 2 vext2 <5,u,u,0>, <5,u,u,0> @@ -5912,37 +5912,37 @@ 1997750374U, // : Cost 2 vtrnl RHS, LHS 2655662673U, // : Cost 3 vext2 <6,3,u,0>, <6,3,u,0> 2555497782U, // : Cost 3 vext1 <0,u,0,6>, RHS - 2248503339U, // : Cost 3 vrev <5,6,0,u> + 2651681459U, // : Cost 3 vext2 <5,6,u,0>, <6,5,0,u> 2651681592U, // : Cost 3 vext2 <5,6,u,0>, <6,6,6,6> 2651681614U, // : Cost 3 vext2 <5,6,u,0>, <6,7,0,1> 1997750428U, // : Cost 2 vtrnl RHS, LHS 2567446630U, // : Cost 3 vext1 <2,u,0,7>, LHS 2567447446U, // : Cost 3 vext1 <2,u,0,7>, <1,2,3,0> 2567448641U, // : Cost 3 vext1 <2,u,0,7>, <2,u,0,7> - 2237221578U, // : Cost 3 vrev <3,7,0,u> + 2573421338U, // : Cost 3 vext1 <3,u,0,7>, <3,u,0,7> 2567449910U, // : Cost 3 vext1 <2,u,0,7>, RHS 2651682242U, // : Cost 3 vext2 <5,6,u,0>, <7,5,6,u> - 1181397845U, // : Cost 2 vrev <6,7,0,u> + 2591339429U, // : Cost 3 vext1 <6,u,0,7>, <6,u,0,7> 2651682412U, // : Cost 3 vext2 <5,6,u,0>, <7,7,7,7> - 1193343239U, // : Cost 2 vrev + 2567452462U, // : Cost 3 vext1 <2,u,0,7>, LHS 135053414U, // : Cost 1 vdup0 LHS 1611489938U, // : Cost 2 vext3 LHS, <0,u,1,1> 537748125U, // : Cost 1 vext3 LHS, LHS 2685674148U, // : Cost 3 vext3 LHS, <0,u,3,1> 1611932338U, // : Cost 2 vext3 LHS, <0,u,4,6> 1551399066U, // : Cost 2 vext2 <1,2,u,0>, RHS - 1182061478U, // : Cost 2 vrev <6,u,0,u> + 1517605798U, // : Cost 2 vext1 <6,u,0,u>, <6,u,0,u> 2830077481U, // : Cost 3 vuzpr <1,u,3,0>, RHS 537748179U, // : Cost 1 vext3 LHS, LHS - 1499693158U, // : Cost 2 vext1 <3,u,1,0>, LHS + 1544101961U, // : Cost 2 vext2 <0,0,u,1>, <0,0,u,1> 1558036582U, // : Cost 2 vext2 <2,3,u,1>, LHS 2619171051U, // : Cost 3 vext2 <0,2,u,1>, <0,2,u,1> - 1158908060U, // : Cost 2 vrev <3,0,1,u> - 1499696438U, // : Cost 2 vext1 <3,u,1,0>, RHS - 2712068872U, // : Cost 3 vext3 RHS, <1,0,5,2> - 2250567975U, // : Cost 3 vrev <6,0,1,u> - 1182798848U, // : Cost 2 vrev <7,0,1,u> - 1558037149U, // : Cost 2 vext2 <2,3,u,1>, LHS + 1611490038U, // : Cost 2 vext3 LHS, <1,0,3,2> + 2555522358U, // : Cost 3 vext1 <0,u,1,0>, RHS + 2712068871U, // : Cost 3 vext3 RHS, <1,0,5,1> + 2591355815U, // : Cost 3 vext1 <6,u,1,0>, <6,u,1,0> + 2597328512U, // : Cost 3 vext1 <7,u,1,0>, <7,u,1,0> + 1611490083U, // : Cost 2 vext3 LHS, <1,0,u,2> 1481785446U, // : Cost 2 vext1 <0,u,1,1>, LHS 202162278U, // : Cost 1 vdup1 LHS 2555528808U, // : Cost 3 vext1 <0,u,1,1>, <2,2,2,2> @@ -5950,7 +5950,7 @@ 1481788726U, // : Cost 2 vext1 <0,u,1,1>, RHS 2689876828U, // : Cost 3 vext3 LHS, <1,1,5,5> 2591364008U, // : Cost 3 vext1 <6,u,1,1>, <6,u,1,1> - 2257204305U, // : Cost 3 vrev <7,1,1,u> + 2592691274U, // : Cost 3 vext1 <7,1,1,1>, <7,1,1,1> 202162278U, // : Cost 1 vdup1 LHS 1499709542U, // : Cost 2 vext1 <3,u,1,2>, LHS 2689876871U, // : Cost 3 vext3 LHS, <1,2,1,3> @@ -5973,18 +5973,18 @@ 1567992749U, // : Cost 2 vext2 <4,0,u,1>, <4,0,u,1> 2693121070U, // : Cost 3 vext3 <1,4,1,u>, <1,4,1,u> 2693194807U, // : Cost 3 vext3 <1,4,2,u>, <1,4,2,u> - 2685232189U, // : Cost 3 vext3 LHS, <1,4,3,5> + 1152386432U, // : Cost 2 vrev <1,u,3,4> 2555555126U, // : Cost 3 vext1 <0,u,1,4>, RHS 1558039862U, // : Cost 2 vext2 <2,3,u,1>, RHS 2645716371U, // : Cost 3 vext2 <4,6,u,1>, <4,6,u,1> 2597361284U, // : Cost 3 vext1 <7,u,1,4>, <7,u,1,4> - 1558040105U, // : Cost 2 vext2 <2,3,u,1>, RHS + 1152755117U, // : Cost 2 vrev <1,u,u,4> 1481818214U, // : Cost 2 vext1 <0,u,1,5>, LHS - 2555560756U, // : Cost 3 vext1 <0,u,1,5>, <1,1,1,1> + 2555560694U, // : Cost 3 vext1 <0,u,1,5>, <1,0,3,2> 2555561576U, // : Cost 3 vext1 <0,u,1,5>, <2,2,2,2> 1611490448U, // : Cost 2 vext3 LHS, <1,5,3,7> 1481821494U, // : Cost 2 vext1 <0,u,1,5>, RHS - 2555563734U, // : Cost 3 vext1 <0,u,1,5>, <5,1,u,0> + 2651025435U, // : Cost 3 vext2 <5,5,u,1>, <5,5,u,1> 2651689068U, // : Cost 3 vext2 <5,6,u,1>, <5,6,u,1> 2823966006U, // : Cost 3 vuzpr <0,u,1,1>, RHS 1611932861U, // : Cost 2 vext3 LHS, <1,5,u,7> @@ -6002,8 +6002,8 @@ 2573493926U, // : Cost 3 vext1 <3,u,1,7>, <2,3,0,1> 2042962022U, // : Cost 2 vtrnr RHS, LHS 2561551670U, // : Cost 3 vext1 <1,u,1,7>, RHS - 2980643154U, // : Cost 3 vzipr RHS, <0,4,1,5> - 2255213406U, // : Cost 3 vrev <6,7,1,u> + 2226300309U, // : Cost 3 vrev <1,u,5,7> + 2658325990U, // : Cost 3 vext2 <6,7,u,1>, <7,6,1,u> 2658326124U, // : Cost 3 vext2 <6,7,u,1>, <7,7,7,7> 2042962027U, // : Cost 2 vtrnr RHS, LHS 1481842790U, // : Cost 2 vext1 <0,u,1,u>, LHS @@ -6013,37 +6013,37 @@ 1481846070U, // : Cost 2 vext1 <0,u,1,u>, RHS 1611933077U, // : Cost 2 vext3 LHS, <1,u,5,7> 2685674910U, // : Cost 3 vext3 LHS, <1,u,6,7> - 1188107912U, // : Cost 2 vrev <7,u,1,u> + 1523652232U, // : Cost 2 vext1 <7,u,1,u>, <7,u,1,u> 835584U, // : Cost 0 copy LHS 1544110154U, // : Cost 2 vext2 <0,0,u,2>, <0,0,u,2> 1545437286U, // : Cost 2 vext2 <0,2,u,2>, LHS 1545437420U, // : Cost 2 vext2 <0,2,u,2>, <0,2,u,2> 2685232589U, // : Cost 3 vext3 LHS, <2,0,3,0> 2619179346U, // : Cost 3 vext2 <0,2,u,2>, <0,4,1,5> - 2696734183U, // : Cost 3 vext3 <2,0,5,u>, <2,0,5,u> - 2712069609U, // : Cost 3 vext3 RHS, <2,0,6,1> - 2256614409U, // : Cost 3 vrev <7,0,2,u> + 2712069606U, // : Cost 3 vext3 RHS, <2,0,5,7> + 2689877484U, // : Cost 3 vext3 LHS, <2,0,6,4> + 2659656273U, // : Cost 3 vext2 <7,0,u,2>, <0,7,2,u> 1545437853U, // : Cost 2 vext2 <0,2,u,2>, LHS - 67985515U, // : Cost 1 vrev LHS + 1550082851U, // : Cost 2 vext2 <1,0,u,2>, <1,0,u,2> 2619179828U, // : Cost 3 vext2 <0,2,u,2>, <1,1,1,1> 2619179926U, // : Cost 3 vext2 <0,2,u,2>, <1,2,3,0> - 2685232670U, // : Cost 3 vext3 LHS, <2,1,3,0> + 2685232671U, // : Cost 3 vext3 LHS, <2,1,3,1> 2555604278U, // : Cost 3 vext1 <0,u,2,1>, RHS 2619180176U, // : Cost 3 vext2 <0,2,u,2>, <1,5,3,7> 2689877564U, // : Cost 3 vext3 LHS, <2,1,6,3> - 2257278042U, // : Cost 3 vrev <7,1,2,u> - 115767091U, // : Cost 1 vrev LHS + 2602718850U, // : Cost 3 vext1 , <7,u,1,2> + 1158703235U, // : Cost 2 vrev <2,u,u,1> 1481867366U, // : Cost 2 vext1 <0,u,2,2>, LHS - 2555609908U, // : Cost 3 vext1 <0,u,2,2>, <1,1,1,1> + 2555609846U, // : Cost 3 vext1 <0,u,2,2>, <1,0,3,2> 269271142U, // : Cost 1 vdup2 LHS 1611490930U, // : Cost 2 vext3 LHS, <2,2,3,3> 1481870646U, // : Cost 2 vext1 <0,u,2,2>, RHS 2689877640U, // : Cost 3 vext3 LHS, <2,2,5,7> 2619180986U, // : Cost 3 vext2 <0,2,u,2>, <2,6,3,7> - 2257941675U, // : Cost 3 vrev <7,2,2,u> + 2593436837U, // : Cost 3 vext1 <7,2,2,2>, <7,2,2,2> 269271142U, // : Cost 1 vdup2 LHS 408134301U, // : Cost 1 vext1 LHS, LHS - 1481876276U, // : Cost 2 vext1 LHS, <1,1,1,1> + 1481876214U, // : Cost 2 vext1 LHS, <1,0,3,2> 1481877096U, // : Cost 2 vext1 LHS, <2,2,2,2> 1880326246U, // : Cost 2 vzipr LHS, LHS 408137014U, // : Cost 1 vext1 LHS, RHS @@ -6058,19 +6058,19 @@ 2555628854U, // : Cost 3 vext1 <0,u,2,4>, RHS 1545440566U, // : Cost 2 vext2 <0,2,u,2>, RHS 1571982740U, // : Cost 2 vext2 <4,6,u,2>, <4,6,u,2> - 2659659225U, // : Cost 3 vext2 <7,0,u,2>, <4,7,6,u> + 2592125957U, // : Cost 3 vext1 <7,0,2,4>, <7,0,2,4> 1545440809U, // : Cost 2 vext2 <0,2,u,2>, RHS 2555633766U, // : Cost 3 vext1 <0,u,2,5>, LHS 2561606550U, // : Cost 3 vext1 <1,u,2,5>, <1,2,3,0> 2689877856U, // : Cost 3 vext3 LHS, <2,5,2,7> 2685233000U, // : Cost 3 vext3 LHS, <2,5,3,6> - 2555637046U, // : Cost 3 vext1 <0,u,2,5>, RHS + 1158441059U, // : Cost 2 vrev <2,u,4,5> 2645725188U, // : Cost 3 vext2 <4,6,u,2>, <5,5,5,5> 2689877892U, // : Cost 3 vext3 LHS, <2,5,6,7> 2823900470U, // : Cost 3 vuzpr <0,u,0,2>, RHS - 2685675413U, // : Cost 3 vext3 LHS, <2,5,u,6> + 1158736007U, // : Cost 2 vrev <2,u,u,5> 1481900134U, // : Cost 2 vext1 <0,u,2,6>, LHS - 2555642676U, // : Cost 3 vext1 <0,u,2,6>, <1,1,1,1> + 2555642614U, // : Cost 3 vext1 <0,u,2,6>, <1,0,3,2> 2555643496U, // : Cost 3 vext1 <0,u,2,6>, <2,2,2,2> 1611491258U, // : Cost 2 vext3 LHS, <2,6,3,7> 1481903414U, // : Cost 2 vext1 <0,u,2,6>, RHS @@ -6079,7 +6079,7 @@ 2645726030U, // : Cost 3 vext2 <4,6,u,2>, <6,7,0,1> 1611933671U, // : Cost 2 vext3 LHS, <2,6,u,7> 1585919033U, // : Cost 2 vext2 <7,0,u,2>, <7,0,u,2> - 2800079866U, // : Cost 3 vuzpl LHS, <7,0,1,2> + 2573566710U, // : Cost 3 vext1 <3,u,2,7>, <1,0,3,2> 2567596115U, // : Cost 3 vext1 <2,u,2,7>, <2,u,2,7> 1906901094U, // : Cost 2 vzipr RHS, LHS 2555653430U, // : Cost 3 vext1 <0,u,2,7>, RHS @@ -6087,7 +6087,7 @@ 2980643164U, // : Cost 3 vzipr RHS, <0,4,2,6> 2645726828U, // : Cost 3 vext2 <4,6,u,2>, <7,7,7,7> 1906901099U, // : Cost 2 vzipr RHS, LHS - 72630946U, // : Cost 1 vrev LHS + 408175266U, // : Cost 1 vext1 LHS, LHS 1545443118U, // : Cost 2 vext2 <0,2,u,2>, LHS 269271142U, // : Cost 1 vdup2 LHS 1611491416U, // : Cost 2 vext3 LHS, <2,u,3,3> @@ -6101,11 +6101,11 @@ 1544781988U, // : Cost 2 vext2 LHS, <0,2,0,2> 2618523900U, // : Cost 3 vext2 LHS, <0,3,1,0> 1544782162U, // : Cost 2 vext2 LHS, <0,4,1,5> - 2712070330U, // : Cost 3 vext3 RHS, <3,0,5,2> + 2238188352U, // : Cost 3 vrev <3,u,5,0> 2623169023U, // : Cost 3 vext2 LHS, <0,6,2,7> - 2597475986U, // : Cost 3 vext1 <7,u,3,0>, <7,u,3,0> + 2238335826U, // : Cost 3 vrev <3,u,7,0> 471040669U, // : Cost 1 vext2 LHS, LHS - 2618524404U, // : Cost 3 vext2 LHS, <1,0,3,0> + 1544782582U, // : Cost 2 vext2 LHS, <1,0,3,2> 1544782644U, // : Cost 2 vext2 LHS, <1,1,1,1> 1544782742U, // : Cost 2 vext2 LHS, <1,2,3,0> 1544782808U, // : Cost 2 vext2 LHS, <1,3,1,3> @@ -6114,22 +6114,22 @@ 2618524897U, // : Cost 3 vext2 LHS, <1,6,3,7> 2703517987U, // : Cost 3 vext3 <3,1,7,u>, <3,1,7,u> 1544783213U, // : Cost 2 vext2 LHS, <1,u,1,3> - 2618525133U, // : Cost 3 vext2 LHS, <2,0,3,0> - 1611491638U, // : Cost 2 vext3 LHS, <3,2,1,0> + 1529716838U, // : Cost 2 vext1 , LHS + 1164167966U, // : Cost 2 vrev <3,u,1,2> 1544783464U, // : Cost 2 vext2 LHS, <2,2,2,2> 1544783526U, // : Cost 2 vext2 LHS, <2,3,0,1> - 2618525462U, // : Cost 3 vext2 LHS, <2,4,3,5> + 1529720118U, // : Cost 2 vext1 , RHS 2618525544U, // : Cost 3 vext2 LHS, <2,5,3,6> 1544783802U, // : Cost 2 vext2 LHS, <2,6,3,7> 2704181620U, // : Cost 3 vext3 <3,2,7,u>, <3,2,7,u> 1544783931U, // : Cost 2 vext2 LHS, <2,u,0,1> 1544784022U, // : Cost 2 vext2 LHS, <3,0,1,2> 1487922559U, // : Cost 2 vext1 <1,u,3,3>, <1,u,3,3> - 1544784182U, // : Cost 2 vext2 LHS, <3,2,1,0> + 1493895256U, // : Cost 2 vext1 <2,u,3,3>, <2,u,3,3> 336380006U, // : Cost 1 vdup3 LHS 1544784386U, // : Cost 2 vext2 LHS, <3,4,5,6> 2824054478U, // : Cost 3 vuzpr LHS, <2,3,4,5> - 2591527868U, // : Cost 3 vext1 <6,u,3,3>, <6,u,3,3> + 2238286668U, // : Cost 3 vrev <3,u,6,3> 2954069136U, // : Cost 3 vzipr LHS, <1,5,3,7> 336380006U, // : Cost 1 vdup3 LHS 1487929446U, // : Cost 2 vext1 <1,u,3,4>, LHS @@ -6139,13 +6139,13 @@ 1487932726U, // : Cost 2 vext1 <1,u,3,4>, RHS 471043382U, // : Cost 1 vext2 LHS, RHS 1592561012U, // : Cost 2 vext2 LHS, <4,6,4,6> - 2597508758U, // : Cost 3 vext1 <7,u,3,4>, <7,u,3,4> + 2238368598U, // : Cost 3 vrev <3,u,7,4> 471043625U, // : Cost 1 vext2 LHS, RHS 2555707494U, // : Cost 3 vext1 <0,u,3,5>, LHS 1574645465U, // : Cost 2 vext2 <5,1,u,3>, <5,1,u,3> 2567653106U, // : Cost 3 vext1 <2,u,3,5>, <2,3,u,5> 2555709954U, // : Cost 3 vext1 <0,u,3,5>, <3,4,5,6> - 2555710774U, // : Cost 3 vext1 <0,u,3,5>, RHS + 1592561606U, // : Cost 2 vext2 LHS, <5,4,7,6> 1592561668U, // : Cost 2 vext2 LHS, <5,5,5,5> 1592561762U, // : Cost 2 vext2 LHS, <5,6,7,0> 1750314294U, // : Cost 2 vuzpr LHS, RHS @@ -6154,23 +6154,23 @@ 2561688962U, // : Cost 3 vext1 <1,u,3,6>, <1,u,3,6> 1581281795U, // : Cost 2 vext2 <6,2,u,3>, <6,2,u,3> 2706541204U, // : Cost 3 vext3 <3,6,3,u>, <3,6,3,u> - 2623173228U, // : Cost 3 vext2 LHS, <6,4,2,0> - 2248724550U, // : Cost 3 vrev <5,6,3,u> + 2623173261U, // : Cost 3 vext2 LHS, <6,4,5,6> + 1164495686U, // : Cost 2 vrev <3,u,5,6> 1592562488U, // : Cost 2 vext2 LHS, <6,6,6,6> 1592562510U, // : Cost 2 vext2 LHS, <6,7,0,1> - 1592562591U, // : Cost 2 vext2 LHS, <6,u,0,1> + 1164716897U, // : Cost 2 vrev <3,u,u,6> 1487954022U, // : Cost 2 vext1 <1,u,3,7>, LHS 1487955331U, // : Cost 2 vext1 <1,u,3,7>, <1,u,3,7> 1493928028U, // : Cost 2 vext1 <2,u,3,7>, <2,u,3,7> 2561697942U, // : Cost 3 vext1 <1,u,3,7>, <3,0,1,2> 1487957302U, // : Cost 2 vext1 <1,u,3,7>, RHS 2707352311U, // : Cost 3 vext3 <3,7,5,u>, <3,7,5,u> - 1592563206U, // : Cost 2 vext2 LHS, <7,6,5,4> + 2655024623U, // : Cost 3 vext2 <6,2,u,3>, <7,6,2,u> 1592563308U, // : Cost 2 vext2 LHS, <7,7,7,7> 1487959854U, // : Cost 2 vext1 <1,u,3,7>, LHS 1544787667U, // : Cost 2 vext2 LHS, 471045934U, // : Cost 1 vext2 LHS, LHS - 1544787827U, // : Cost 2 vext2 LHS, + 1549432709U, // : Cost 2 vext2 LHS, 336380006U, // : Cost 1 vdup3 LHS 1544788031U, // : Cost 2 vext2 LHS, 471046298U, // : Cost 1 vext2 LHS, RHS @@ -6180,14 +6180,14 @@ 2625167360U, // : Cost 3 vext2 <1,2,u,4>, <0,0,0,0> 1551425638U, // : Cost 2 vext2 <1,2,u,4>, LHS 2619195630U, // : Cost 3 vext2 <0,2,u,4>, <0,2,u,4> - 2232871095U, // : Cost 3 vrev <3,0,4,u> + 2619343104U, // : Cost 3 vext2 <0,3,1,4>, <0,3,1,4> 2625167698U, // : Cost 3 vext2 <1,2,u,4>, <0,4,1,5> 1638329234U, // : Cost 2 vext3 RHS, <4,0,5,1> 1638329244U, // : Cost 2 vext3 RHS, <4,0,6,2> - 2256761883U, // : Cost 3 vrev <7,0,4,u> + 3787803556U, // : Cost 4 vext3 RHS, <4,0,7,1> 1551426205U, // : Cost 2 vext2 <1,2,u,4>, LHS 2555748454U, // : Cost 3 vext1 <0,u,4,1>, LHS - 2221589334U, // : Cost 3 vrev <1,1,4,u> + 2625168180U, // : Cost 3 vext2 <1,2,u,4>, <1,1,1,1> 1551426503U, // : Cost 2 vext2 <1,2,u,4>, <1,2,u,4> 2625168344U, // : Cost 3 vext2 <1,2,u,4>, <1,3,1,3> 2555751734U, // : Cost 3 vext1 <0,u,4,1>, RHS @@ -6195,8 +6195,8 @@ 2689879022U, // : Cost 3 vext3 LHS, <4,1,6,3> 2592248852U, // : Cost 3 vext1 <7,0,4,1>, <7,0,4,1> 1555408301U, // : Cost 2 vext2 <1,u,u,4>, <1,u,u,4> - 2216280270U, // : Cost 3 vrev <0,2,4,u> - 2222252967U, // : Cost 3 vrev <1,2,4,u> + 2555756646U, // : Cost 3 vext1 <0,u,4,2>, LHS + 2625168943U, // : Cost 3 vext2 <1,2,u,4>, <2,1,4,u> 2625169000U, // : Cost 3 vext2 <1,2,u,4>, <2,2,2,2> 2619197134U, // : Cost 3 vext2 <0,2,u,4>, <2,3,4,5> 2555759926U, // : Cost 3 vext1 <0,u,4,2>, RHS @@ -6205,22 +6205,22 @@ 2592257045U, // : Cost 3 vext1 <7,0,4,2>, <7,0,4,2> 1994771784U, // : Cost 2 vtrnl LHS, RHS 2625169558U, // : Cost 3 vext2 <1,2,u,4>, <3,0,1,2> - 2222916600U, // : Cost 3 vrev <1,3,4,u> - 1155147473U, // : Cost 2 vrev <2,3,4,u> + 2567709594U, // : Cost 3 vext1 <2,u,4,3>, <1,2,3,4> + 2567710817U, // : Cost 3 vext1 <2,u,4,3>, <2,u,4,3> 2625169820U, // : Cost 3 vext2 <1,2,u,4>, <3,3,3,3> 2625169922U, // : Cost 3 vext2 <1,2,u,4>, <3,4,5,6> 2954069710U, // : Cost 3 vzipr LHS, <2,3,4,5> 2954068172U, // : Cost 3 vzipr LHS, <0,2,4,6> - 2258752782U, // : Cost 3 vrev <7,3,4,u> - 1190983655U, // : Cost 2 vrev + 3903849472U, // : Cost 4 vuzpr <1,u,3,4>, <1,3,5,7> + 2954068174U, // : Cost 3 vzipr LHS, <0,2,4,u> 1505919078U, // : Cost 2 vext1 <4,u,4,4>, LHS 2567717831U, // : Cost 3 vext1 <2,u,4,4>, <1,2,u,4> 2567719010U, // : Cost 3 vext1 <2,u,4,4>, <2,u,4,4> - 2235525627U, // : Cost 3 vrev <3,4,4,u> + 2570373542U, // : Cost 3 vext1 <3,3,4,4>, <3,3,4,4> 161926454U, // : Cost 1 vdup0 RHS 1551428918U, // : Cost 2 vext2 <1,2,u,4>, RHS 1638329572U, // : Cost 2 vext3 RHS, <4,4,6,6> - 2259416415U, // : Cost 3 vrev <7,4,4,u> + 2594927963U, // : Cost 3 vext1 <7,4,4,4>, <7,4,4,4> 161926454U, // : Cost 1 vdup0 RHS 1493983334U, // : Cost 2 vext1 <2,u,4,5>, LHS 2689879301U, // : Cost 3 vext3 LHS, <4,5,1,3> @@ -6232,7 +6232,7 @@ 2830110006U, // : Cost 3 vuzpr <1,u,3,4>, RHS 537750856U, // : Cost 1 vext3 LHS, RHS 1482047590U, // : Cost 2 vext1 <0,u,4,6>, LHS - 2555790132U, // : Cost 3 vext1 <0,u,4,6>, <1,1,1,1> + 2555790070U, // : Cost 3 vext1 <0,u,4,6>, <1,0,3,2> 2555790952U, // : Cost 3 vext1 <0,u,4,6>, <2,2,2,2> 2555791510U, // : Cost 3 vext1 <0,u,4,6>, <3,0,1,2> 1482050870U, // : Cost 2 vext1 <0,u,4,6>, RHS @@ -6243,15 +6243,15 @@ 2567741542U, // : Cost 3 vext1 <2,u,4,7>, LHS 2567742362U, // : Cost 3 vext1 <2,u,4,7>, <1,2,3,4> 2567743589U, // : Cost 3 vext1 <2,u,4,7>, <2,u,4,7> - 2237516526U, // : Cost 3 vrev <3,7,4,u> + 2573716286U, // : Cost 3 vext1 <3,u,4,7>, <3,u,4,7> 2567744822U, // : Cost 3 vext1 <2,u,4,7>, RHS 2712071624U, // : Cost 3 vext3 RHS, <4,7,5,0> - 1181692793U, // : Cost 2 vrev <6,7,4,u> + 96808489U, // : Cost 1 vrev RHS 2651715180U, // : Cost 3 vext2 <5,6,u,4>, <7,7,7,7> - 1591244483U, // : Cost 2 vext2 <7,u,u,4>, <7,u,u,4> + 96955963U, // : Cost 1 vrev RHS 1482063974U, // : Cost 2 vext1 <0,u,4,u>, LHS 1551431470U, // : Cost 2 vext2 <1,2,u,4>, LHS - 1158465638U, // : Cost 2 vrev <2,u,4,u> + 1494009958U, // : Cost 2 vext1 <2,u,4,u>, <2,u,4,u> 2555807894U, // : Cost 3 vext1 <0,u,4,u>, <3,0,1,2> 161926454U, // : Cost 1 vdup0 RHS 1551431834U, // : Cost 2 vext2 <1,2,u,4>, RHS @@ -6265,7 +6265,7 @@ 1546273106U, // : Cost 2 vext2 <0,4,1,5>, <0,4,1,5> 2733010539U, // : Cost 3 vext3 LHS, <5,0,5,1> 2597622682U, // : Cost 3 vext1 <7,u,5,0>, <6,7,u,5> - 3098512694U, // : Cost 3 vtrnr <1,u,3,0>, RHS + 1176539396U, // : Cost 2 vrev <5,u,7,0> 1558069917U, // : Cost 2 vext2 <2,3,u,5>, LHS 1505968230U, // : Cost 2 vext1 <4,u,5,1>, LHS 2624512887U, // : Cost 3 vext2 <1,1,u,5>, <1,1,u,5> @@ -6286,22 +6286,22 @@ 3092335926U, // : Cost 3 vtrnr <0,u,0,2>, RHS 1561389191U, // : Cost 2 vext2 <2,u,u,5>, <2,u,u,5> 2561810534U, // : Cost 3 vext1 <1,u,5,3>, LHS - 2222990337U, // : Cost 3 vrev <1,3,5,u> - 2631813430U, // : Cost 3 vext2 <2,3,u,5>, <3,2,1,0> + 2561811857U, // : Cost 3 vext1 <1,u,5,3>, <1,u,5,3> + 2631813474U, // : Cost 3 vext2 <2,3,u,5>, <3,2,5,u> 2631813532U, // : Cost 3 vext2 <2,3,u,5>, <3,3,3,3> 2619869698U, // : Cost 3 vext2 <0,3,u,5>, <3,4,5,6> 3001847002U, // : Cost 3 vzipr LHS, <4,4,5,5> 2954070530U, // : Cost 3 vzipr LHS, <3,4,5,6> 2018749750U, // : Cost 2 vtrnr LHS, RHS 2018749751U, // : Cost 2 vtrnr LHS, RHS - 1523908710U, // : Cost 2 vext1 <7,u,5,4>, LHS - 2223653970U, // : Cost 3 vrev <1,4,5,u> - 2229626667U, // : Cost 3 vrev <2,4,5,u> - 1161857540U, // : Cost 2 vrev <3,4,5,u> - 1523911990U, // : Cost 2 vext1 <7,u,5,4>, RHS + 2573762662U, // : Cost 3 vext1 <3,u,5,4>, LHS + 2620017634U, // : Cost 3 vext2 <0,4,1,5>, <4,1,5,0> + 2573764338U, // : Cost 3 vext1 <3,u,5,4>, <2,3,u,5> + 2573765444U, // : Cost 3 vext1 <3,u,5,4>, <3,u,5,4> + 1570680053U, // : Cost 2 vext2 <4,4,u,5>, <4,4,u,5> 1558072630U, // : Cost 2 vext2 <2,3,u,5>, RHS 2645749143U, // : Cost 3 vext2 <4,6,u,5>, <4,6,u,5> - 1185748328U, // : Cost 2 vrev <7,4,5,u> + 1638330310U, // : Cost 2 vext3 RHS, <5,4,7,6> 1558072873U, // : Cost 2 vext2 <2,3,u,5>, RHS 1506000998U, // : Cost 2 vext1 <4,u,5,5>, LHS 2561827984U, // : Cost 3 vext1 <1,u,5,5>, <1,5,3,7> @@ -6318,7 +6318,7 @@ 1500040006U, // : Cost 2 vext1 <3,u,5,6>, <3,u,5,6> 1500040502U, // : Cost 2 vext1 <3,u,5,6>, RHS 2714062935U, // : Cost 3 vext3 RHS, <5,6,5,7> - 2573783798U, // : Cost 3 vext1 <3,u,5,6>, <6,5,u,3> + 2712072288U, // : Cost 3 vext3 RHS, <5,6,6,7> 27705344U, // : Cost 0 copy RHS 27705344U, // : Cost 0 copy RHS 1488101478U, // : Cost 2 vext1 <1,u,5,7>, LHS @@ -6333,7 +6333,7 @@ 1488109670U, // : Cost 2 vext1 <1,u,5,u>, LHS 1488110998U, // : Cost 2 vext1 <1,u,5,u>, <1,u,5,u> 2561853032U, // : Cost 3 vext1 <1,u,5,u>, <2,2,2,2> - 1164512072U, // : Cost 2 vrev <3,u,5,u> + 1500056392U, // : Cost 2 vext1 <3,u,5,u>, <3,u,5,u> 1488112950U, // : Cost 2 vext1 <1,u,5,u>, RHS 229035318U, // : Cost 1 vdup1 RHS 2954111490U, // : Cost 3 vzipr LHS, <3,4,5,6> @@ -6342,13 +6342,13 @@ 2619211776U, // : Cost 3 vext2 <0,2,u,6>, <0,0,0,0> 1545470054U, // : Cost 2 vext2 <0,2,u,6>, LHS 1545470192U, // : Cost 2 vext2 <0,2,u,6>, <0,2,u,6> - 2638233856U, // : Cost 3 vext2 <3,4,5,6>, <0,3,1,4> + 2255958969U, // : Cost 3 vrev <6,u,3,0> 1546797458U, // : Cost 2 vext2 <0,4,u,6>, <0,4,u,6> 2720624971U, // : Cost 3 vext3 <6,0,5,u>, <6,0,5,u> - 2591724500U, // : Cost 3 vext1 <6,u,6,0>, <6,u,6,0> + 2256180180U, // : Cost 3 vrev <6,u,6,0> 2960682294U, // : Cost 3 vzipr <1,2,u,0>, RHS 1545470621U, // : Cost 2 vext2 <0,2,u,6>, LHS - 2585755750U, // : Cost 3 vext1 <5,u,6,1>, LHS + 1182004127U, // : Cost 2 vrev <6,u,0,1> 2619212596U, // : Cost 3 vext2 <0,2,u,6>, <1,1,1,1> 2619212694U, // : Cost 3 vext2 <0,2,u,6>, <1,2,3,0> 2619212760U, // : Cost 3 vext2 <0,2,u,6>, <1,3,1,3> @@ -6356,9 +6356,9 @@ 2619212944U, // : Cost 3 vext2 <0,2,u,6>, <1,5,3,7> 2714063264U, // : Cost 3 vext3 RHS, <6,1,6,3> 2967326006U, // : Cost 3 vzipr <2,3,u,1>, RHS - 2619213165U, // : Cost 3 vext2 <0,2,u,6>, <1,u,1,3> + 1182594023U, // : Cost 2 vrev <6,u,u,1> 1506050150U, // : Cost 2 vext1 <4,u,6,2>, LHS - 2579792692U, // : Cost 3 vext1 <4,u,6,2>, <1,1,1,1> + 2579792630U, // : Cost 3 vext1 <4,u,6,2>, <1,0,3,2> 2619213416U, // : Cost 3 vext2 <0,2,u,6>, <2,2,2,2> 2619213478U, // : Cost 3 vext2 <0,2,u,6>, <2,3,0,1> 1506053430U, // : Cost 2 vext1 <4,u,6,2>, RHS @@ -6367,8 +6367,8 @@ 1638330874U, // : Cost 2 vext3 RHS, <6,2,7,3> 1638478339U, // : Cost 2 vext3 RHS, <6,2,u,3> 2619213974U, // : Cost 3 vext2 <0,2,u,6>, <3,0,1,2> - 2803058838U, // : Cost 3 vuzpl RHS, <3,0,1,2> - 2619214134U, // : Cost 3 vext2 <0,2,u,6>, <3,2,1,0> + 2255836074U, // : Cost 3 vrev <6,u,1,3> + 2255909811U, // : Cost 3 vrev <6,u,2,3> 2619214236U, // : Cost 3 vext2 <0,2,u,6>, <3,3,3,3> 1564715549U, // : Cost 2 vext2 <3,4,u,6>, <3,4,u,6> 2639121006U, // : Cost 3 vext2 <3,5,u,6>, <3,5,u,6> @@ -6376,9 +6376,9 @@ 1880329526U, // : Cost 2 vzipr LHS, RHS 1880329527U, // : Cost 2 vzipr LHS, RHS 2567864422U, // : Cost 3 vext1 <2,u,6,4>, LHS - 2722984555U, // : Cost 3 vext3 <6,4,1,u>, <6,4,1,u> - 2689880684U, // : Cost 3 vext3 LHS, <6,4,2,0> - 2577820162U, // : Cost 3 vext1 <4,5,6,4>, <3,4,5,6> + 2733011558U, // : Cost 3 vext3 LHS, <6,4,1,3> + 2567866484U, // : Cost 3 vext1 <2,u,6,4>, <2,u,6,4> + 2638458005U, // : Cost 3 vext2 <3,4,u,6>, <4,3,6,u> 1570540772U, // : Cost 2 vext2 <4,4,6,6>, <4,4,6,6> 1545473334U, // : Cost 2 vext2 <0,2,u,6>, RHS 1572015512U, // : Cost 2 vext2 <4,6,u,6>, <4,6,u,6> @@ -6387,14 +6387,14 @@ 2567872614U, // : Cost 3 vext1 <2,u,6,5>, LHS 2645757648U, // : Cost 3 vext2 <4,6,u,6>, <5,1,7,3> 2567874490U, // : Cost 3 vext1 <2,u,6,5>, <2,6,3,7> - 2236336734U, // : Cost 3 vrev <3,5,6,u> - 94825783U, // : Cost 1 vrev RHS + 2576501250U, // : Cost 3 vext1 <4,3,6,5>, <3,4,5,6> + 1576660943U, // : Cost 2 vext2 <5,4,u,6>, <5,4,u,6> 2645757956U, // : Cost 3 vext2 <4,6,u,6>, <5,5,5,5> 2645758050U, // : Cost 3 vext2 <4,6,u,6>, <5,6,7,0> 2824080694U, // : Cost 3 vuzpr <0,u,2,6>, RHS - 118716571U, // : Cost 1 vrev RHS + 1182626795U, // : Cost 2 vrev <6,u,u,5> 1506082918U, // : Cost 2 vext1 <4,u,6,6>, LHS - 2579825460U, // : Cost 3 vext1 <4,u,6,6>, <1,1,1,1> + 2579825398U, // : Cost 3 vext1 <4,u,6,6>, <1,0,3,2> 2645758458U, // : Cost 3 vext2 <4,6,u,6>, <6,2,7,3> 2579826838U, // : Cost 3 vext1 <4,u,6,6>, <3,0,1,2> 1506086198U, // : Cost 2 vext1 <4,u,6,6>, RHS @@ -6403,7 +6403,7 @@ 1638331202U, // : Cost 2 vext3 RHS, <6,6,7,7> 296144182U, // : Cost 1 vdup2 RHS 432349286U, // : Cost 1 vext1 RHS, LHS - 1506091828U, // : Cost 2 vext1 RHS, <1,1,1,1> + 1506091766U, // : Cost 2 vext1 RHS, <1,0,3,2> 1506092648U, // : Cost 2 vext1 RHS, <2,2,2,2> 1506093206U, // : Cost 2 vext1 RHS, <3,0,1,2> 432352809U, // : Cost 1 vext1 RHS, RHS @@ -6415,7 +6415,7 @@ 1545475886U, // : Cost 2 vext2 <0,2,u,6>, LHS 1506100840U, // : Cost 2 vext1 RHS, <2,2,2,2> 1506101398U, // : Cost 2 vext1 RHS, <3,0,1,2> - 96816682U, // : Cost 1 vrev RHS + 432361002U, // : Cost 1 vext1 RHS, RHS 1545476250U, // : Cost 2 vext2 <0,2,u,6>, RHS 296144182U, // : Cost 1 vdup2 RHS 1880370486U, // : Cost 2 vzipr LHS, RHS @@ -6429,7 +6429,7 @@ 2621874741U, // : Cost 3 vext2 <0,6,u,7>, <0,6,u,7> 2585826298U, // : Cost 3 vext1 <5,u,7,0>, <7,0,1,2> 497615517U, // : Cost 1 vext2 RHS, LHS - 2573885542U, // : Cost 3 vext1 <3,u,7,1>, LHS + 1571357430U, // : Cost 2 vext2 RHS, <1,0,3,2> 1571357492U, // : Cost 2 vext2 RHS, <1,1,1,1> 1571357590U, // : Cost 2 vext2 RHS, <1,2,3,0> 1552114715U, // : Cost 2 vext2 <1,3,u,7>, <1,3,u,7> @@ -6439,7 +6439,7 @@ 2727408775U, // : Cost 3 vext3 <7,1,7,u>, <7,1,7,u> 1555432880U, // : Cost 2 vext2 <1,u,u,7>, <1,u,u,7> 2629838337U, // : Cost 3 vext2 <2,0,u,7>, <2,0,u,7> - 2645100035U, // : Cost 3 vext2 RHS, <2,1,0,0> + 1188058754U, // : Cost 2 vrev <7,u,1,2> 1571358312U, // : Cost 2 vext2 RHS, <2,2,2,2> 1571358374U, // : Cost 2 vext2 RHS, <2,3,0,1> 2632492869U, // : Cost 3 vext2 <2,4,u,7>, <2,4,u,7> @@ -6449,13 +6449,13 @@ 1561405577U, // : Cost 2 vext2 <2,u,u,7>, <2,u,u,7> 1571358870U, // : Cost 2 vext2 RHS, <3,0,1,2> 2627184913U, // : Cost 3 vext2 <1,5,u,7>, <3,1,5,u> - 1571359030U, // : Cost 2 vext2 RHS, <3,2,1,0> + 2633820523U, // : Cost 3 vext2 <2,6,u,7>, <3,2,6,u> 1571359132U, // : Cost 2 vext2 RHS, <3,3,3,3> 1571359234U, // : Cost 2 vext2 RHS, <3,4,5,6> 1512108295U, // : Cost 2 vext1 <5,u,7,3>, <5,u,7,3> 1518080992U, // : Cost 2 vext1 <6,u,7,3>, <6,u,7,3> 2640456465U, // : Cost 3 vext2 <3,7,u,7>, <3,7,u,7> - 1571359516U, // : Cost 2 vext2 RHS, <3,u,1,0> + 1571359518U, // : Cost 2 vext2 RHS, <3,u,1,2> 1571359634U, // : Cost 2 vext2 RHS, <4,0,5,1> 2573911067U, // : Cost 3 vext1 <3,u,7,4>, <1,3,u,7> 2645101622U, // : Cost 3 vext2 RHS, <4,2,5,3> @@ -6468,18 +6468,18 @@ 2645102152U, // : Cost 3 vext2 RHS, <5,0,1,2> 1571360464U, // : Cost 2 vext2 RHS, <5,1,7,3> 2645102334U, // : Cost 3 vext2 RHS, <5,2,3,4> - 2236410471U, // : Cost 3 vrev <3,5,7,u> - 2645102494U, // : Cost 3 vext2 RHS, <5,4,3,2> + 2645102447U, // : Cost 3 vext2 RHS, <5,3,7,0> + 1571360710U, // : Cost 2 vext2 RHS, <5,4,7,6> 1571360772U, // : Cost 2 vext2 RHS, <5,5,5,5> 1571360866U, // : Cost 2 vext2 RHS, <5,6,7,0> 1571360936U, // : Cost 2 vext2 RHS, <5,7,5,7> 1571361017U, // : Cost 2 vext2 RHS, <5,u,5,7> - 2645102881U, // : Cost 3 vext2 RHS, <6,0,1,2> + 1530044518U, // : Cost 2 vext1 , LHS 2645103016U, // : Cost 3 vext2 RHS, <6,1,7,2> 1571361274U, // : Cost 2 vext2 RHS, <6,2,7,3> 2645103154U, // : Cost 3 vext2 RHS, <6,3,4,5> - 2645103212U, // : Cost 3 vext2 RHS, <6,4,2,0> - 1638331910U, // : Cost 2 vext3 RHS, <7,6,5,4> + 1530047798U, // : Cost 2 vext1 , RHS + 1188386474U, // : Cost 2 vrev <7,u,5,6> 1571361592U, // : Cost 2 vext2 RHS, <6,6,6,6> 1571361614U, // : Cost 2 vext2 RHS, <6,7,0,1> 1571361695U, // : Cost 2 vext2 RHS, <6,u,0,1> @@ -6489,12 +6489,12 @@ 2573937497U, // : Cost 3 vext1 <3,u,7,7>, <3,u,7,7> 1571362150U, // : Cost 2 vext2 RHS, <7,4,5,6> 1512141067U, // : Cost 2 vext1 <5,u,7,7>, <5,u,7,7> - 1571362310U, // : Cost 2 vext2 RHS, <7,6,5,4> + 1518113764U, // : Cost 2 vext1 <6,u,7,7>, <6,u,7,7> 363253046U, // : Cost 1 vdup3 RHS 363253046U, // : Cost 1 vdup3 RHS 1571362515U, // : Cost 2 vext2 RHS, 497620782U, // : Cost 1 vext2 RHS, LHS - 1571362675U, // : Cost 2 vext2 RHS, + 1571362693U, // : Cost 2 vext2 RHS, 1571362748U, // : Cost 2 vext2 RHS, 1571362879U, // : Cost 2 vext2 RHS, 497621146U, // : Cost 1 vext2 RHS, RHS @@ -6504,13 +6504,13 @@ 135053414U, // : Cost 1 vdup0 LHS 471081121U, // : Cost 1 vext2 LHS, LHS 1544822948U, // : Cost 2 vext2 LHS, <0,2,0,2> - 1159424219U, // : Cost 2 vrev <3,0,u,u> + 1616140005U, // : Cost 2 vext3 LHS, 1544823122U, // : Cost 2 vext2 LHS, <0,4,1,5> 1512157453U, // : Cost 2 vext1 <5,u,u,0>, <5,u,u,0> 1662220032U, // : Cost 2 vext3 RHS, - 1183315007U, // : Cost 2 vrev <7,0,u,u> + 1194457487U, // : Cost 2 vrev 471081629U, // : Cost 1 vext2 LHS, LHS - 68427937U, // : Cost 1 vrev LHS + 1544823542U, // : Cost 2 vext2 LHS, <1,0,3,2> 202162278U, // : Cost 1 vdup1 LHS 537753390U, // : Cost 1 vext3 LHS, LHS 1544823768U, // : Cost 2 vext2 LHS, <1,3,1,3> @@ -6520,7 +6520,7 @@ 1640322907U, // : Cost 2 vext3 RHS, 537753444U, // : Cost 1 vext3 LHS, LHS 1482309734U, // : Cost 2 vext1 <0,u,u,2>, LHS - 1611495283U, // : Cost 2 vext3 LHS, + 1194031451U, // : Cost 2 vrev 269271142U, // : Cost 1 vdup2 LHS 835584U, // : Cost 0 copy LHS 1482313014U, // : Cost 2 vext1 <0,u,u,2>, RHS @@ -6529,8 +6529,8 @@ 1638479788U, // : Cost 2 vext3 RHS, 835584U, // : Cost 0 copy LHS 408576723U, // : Cost 1 vext1 LHS, LHS - 1482318644U, // : Cost 2 vext1 LHS, <1,1,1,1> - 1544825142U, // : Cost 2 vext2 LHS, <3,2,1,0> + 1482318582U, // : Cost 2 vext1 LHS, <1,0,3,2> + 120371557U, // : Cost 1 vrev LHS 336380006U, // : Cost 1 vdup3 LHS 408579382U, // : Cost 1 vext1 LHS, RHS 1616140271U, // : Cost 2 vext3 LHS, @@ -6540,27 +6540,27 @@ 1488298086U, // : Cost 2 vext1 <1,u,u,4>, LHS 1488299437U, // : Cost 2 vext1 <1,u,u,4>, <1,u,u,4> 1659271204U, // : Cost 2 vext3 LHS, - 1162078751U, // : Cost 2 vrev <3,4,u,u> + 1194195311U, // : Cost 2 vrev 161926454U, // : Cost 1 vdup0 RHS 471084342U, // : Cost 1 vext2 LHS, RHS 1571368308U, // : Cost 2 vext2 RHS, <4,6,4,6> - 1185969539U, // : Cost 2 vrev <7,4,u,u> + 1640323153U, // : Cost 2 vext3 RHS, 471084585U, // : Cost 1 vext2 LHS, RHS 1494278246U, // : Cost 2 vext1 <2,u,u,5>, LHS 1571368656U, // : Cost 2 vext2 RHS, <5,1,7,3> 1494280327U, // : Cost 2 vext1 <2,u,u,5>, <2,u,u,5> 1616140415U, // : Cost 2 vext3 LHS, - 94973257U, // : Cost 1 vrev RHS + 1494281526U, // : Cost 2 vext1 <2,u,u,5>, RHS 229035318U, // : Cost 1 vdup1 RHS 537753754U, // : Cost 1 vext3 LHS, RHS 1750355254U, // : Cost 2 vuzpr LHS, RHS 537753772U, // : Cost 1 vext3 LHS, RHS 1482342502U, // : Cost 2 vext1 <0,u,u,6>, LHS - 2556085044U, // : Cost 3 vext1 <0,u,u,6>, <1,1,1,1> + 2556084982U, // : Cost 3 vext1 <0,u,u,6>, <1,0,3,2> 1571369466U, // : Cost 2 vext2 RHS, <6,2,7,3> 1611938000U, // : Cost 2 vext3 LHS, 1482345782U, // : Cost 2 vext1 <0,u,u,6>, RHS - 1638332639U, // : Cost 2 vext3 RHS, + 1194359171U, // : Cost 2 vrev 296144182U, // : Cost 1 vdup2 RHS 27705344U, // : Cost 0 copy RHS 27705344U, // : Cost 0 copy RHS @@ -6570,10 +6570,10 @@ 1906901148U, // : Cost 2 vzipr RHS, LHS 432500283U, // : Cost 1 vext1 RHS, RHS 1506242256U, // : Cost 2 vext1 RHS, <5,1,7,3> - 1571370502U, // : Cost 2 vext2 RHS, <7,6,5,4> + 120699277U, // : Cost 1 vrev RHS 363253046U, // : Cost 1 vdup3 RHS 432502574U, // : Cost 1 vext1 RHS, LHS - 73073368U, // : Cost 1 vrev LHS + 408617688U, // : Cost 1 vext1 LHS, LHS 471086894U, // : Cost 1 vext2 LHS, LHS 537753957U, // : Cost 1 vext3 LHS, LHS 835584U, // : Cost 0 copy LHS @@ -6584,4 +6584,3 @@ 835584U, // : Cost 0 copy LHS 0 }; - Modified: llvm/trunk/test/CodeGen/ARM/vrev.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=131529&r1=131528&r2=131529&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrev.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vrev.ll Wed May 18 01:42:21 2011 @@ -148,12 +148,11 @@ ret void } -; Test the shuffle of a 4xi16 which exposed a problem with the perfect shuffle table -; entry for vrev. +; vrev <4 x i16> should use VREV32 and not VREV64 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp { ; CHECK: test_vrev64: -; CHECK: vrev64.16 ; CHECK: vext.16 +; CHECK: vrev32.16 entry: %0 = bitcast <4 x i16>* %source to <8 x i16>* %tmp2 = load <8 x i16>* %0, align 4 Modified: llvm/trunk/utils/PerfectShuffle/PerfectShuffle.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/PerfectShuffle/PerfectShuffle.cpp?rev=131529&r1=131528&r2=131529&view=diff ============================================================================== --- llvm/trunk/utils/PerfectShuffle/PerfectShuffle.cpp (original) +++ llvm/trunk/utils/PerfectShuffle/PerfectShuffle.cpp Wed May 18 01:42:21 2011 @@ -520,7 +520,7 @@ }; struct vrev : public Operator { - vrev() : Operator(0x3210, "vrev", OP_VREV) {} + vrev() : Operator(0x1032, "vrev", OP_VREV) {} } the_vrev; template From anton at korobeynikov.info Wed May 18 01:49:28 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Wed, 18 May 2011 10:49:28 +0400 Subject: [llvm-commits] [PATCH] Implement Win64 EH MCStreamer methods for Assembly Printing In-Reply-To: <4DD1956C.3090406@mymail.mines.edu> References: <4DD1956C.3090406@mymail.mines.edu> Message-ID: Hi Chip, > Note that GAS doesn't have any directives like this yet, so I've taken > license with their names. One minor thing: maybe it might ask / send e-mail to binutils folks telling them you're going to use these names :) -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From baldrick at free.fr Wed May 18 02:13:41 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 18 May 2011 07:13:41 -0000 Subject: [llvm-commits] [llvm] r131530 - in /llvm/trunk: lib/VMCore/Instructions.cpp unittests/VMCore/InstructionsTest.cpp Message-ID: <20110518071341.E91362A6C12C@llvm.org> Author: baldrick Date: Wed May 18 02:13:41 2011 New Revision: 131530 URL: http://llvm.org/viewvc/llvm-project?rev=131530&view=rev Log: Teach getCastOpcode about element-by-element vector casts. For example, "trunc" can be used to turn a <4 x i64> into a <4 x i32> but getCastOpcode would assert if you passed these types to it. Note that this strictly extends the previous functionality: if getCastOpcode previously accepted two vector types (i.e. didn't assert) then it still will and returns the same opcode (BitCast). That's because before it would only accept vectors with the same bitwidth, and the new code only touches vectors with the same length. However if two vectors have both the same bitwidth and the same length then their element types have the same bitwidth, so the new logic will return BitCast as before. Modified: llvm/trunk/lib/VMCore/Instructions.cpp llvm/trunk/unittests/VMCore/InstructionsTest.cpp Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=131530&r1=131529&r2=131530&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Wed May 18 02:13:41 2011 @@ -2254,6 +2254,14 @@ if (SrcTy == DestTy) return true; + if (const VectorType *SrcVecTy = dyn_cast(SrcTy)) + if (const VectorType *DestVecTy = dyn_cast(DestTy)) + if (SrcVecTy->getNumElements() == DestVecTy->getNumElements()) { + // An element by element cast. Valid if casting the elements is valid. + SrcTy = SrcVecTy->getElementType(); + DestTy = DestVecTy->getElementType(); + } + // Get the bit sizes, we'll need these unsigned SrcBits = SrcTy->getScalarSizeInBits(); // 0 for ptr unsigned DestBits = DestTy->getScalarSizeInBits(); // 0 for ptr @@ -2322,14 +2330,27 @@ Instruction::CastOps CastInst::getCastOpcode( const Value *Src, bool SrcIsSigned, const Type *DestTy, bool DestIsSigned) { - // Get the bit sizes, we'll need these const Type *SrcTy = Src->getType(); - unsigned SrcBits = SrcTy->getScalarSizeInBits(); // 0 for ptr - unsigned DestBits = DestTy->getScalarSizeInBits(); // 0 for ptr assert(SrcTy->isFirstClassType() && DestTy->isFirstClassType() && "Only first class types are castable!"); + if (SrcTy == DestTy) + return BitCast; + + if (const VectorType *SrcVecTy = dyn_cast(SrcTy)) + if (const VectorType *DestVecTy = dyn_cast(DestTy)) + if (SrcVecTy->getNumElements() == DestVecTy->getNumElements()) { + // An element by element cast. Find the appropriate opcode based on the + // element types. + SrcTy = SrcVecTy->getElementType(); + DestTy = DestVecTy->getElementType(); + } + + // Get the bit sizes, we'll need these + unsigned SrcBits = SrcTy->getScalarSizeInBits(); // 0 for ptr + unsigned DestBits = DestTy->getScalarSizeInBits(); // 0 for ptr + // Run through the possibilities ... if (DestTy->isIntegerTy()) { // Casting to integral if (SrcTy->isIntegerTy()) { // Casting from integral @@ -2384,7 +2405,7 @@ if (const VectorType *SrcPTy = dyn_cast(SrcTy)) { assert(DestPTy->getBitWidth() == SrcPTy->getBitWidth() && "Casting vector to vector of different widths"); - SrcPTy = NULL; + (void)SrcPTy; return BitCast; // vector -> vector } else if (DestPTy->getBitWidth() == SrcBits) { return BitCast; // float/int -> vector Modified: llvm/trunk/unittests/VMCore/InstructionsTest.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/VMCore/InstructionsTest.cpp?rev=131530&r1=131529&r2=131530&view=diff ============================================================================== --- llvm/trunk/unittests/VMCore/InstructionsTest.cpp (original) +++ llvm/trunk/unittests/VMCore/InstructionsTest.cpp Wed May 18 02:13:41 2011 @@ -114,11 +114,19 @@ const Type* Int8Ty = Type::getInt8Ty(C); const Type* Int64Ty = Type::getInt64Ty(C); const Type* V8x8Ty = VectorType::get(Int8Ty, 8); + const Type* V8x64Ty = VectorType::get(Int64Ty, 8); const Type* X86MMXTy = Type::getX86_MMXTy(C); + const Constant* c8 = Constant::getNullValue(V8x8Ty); + const Constant* c64 = Constant::getNullValue(V8x64Ty); + EXPECT_TRUE(CastInst::isCastable(V8x8Ty, X86MMXTy)); EXPECT_TRUE(CastInst::isCastable(X86MMXTy, V8x8Ty)); EXPECT_FALSE(CastInst::isCastable(Int64Ty, X86MMXTy)); + EXPECT_TRUE(CastInst::isCastable(V8x64Ty, V8x8Ty)); + EXPECT_TRUE(CastInst::isCastable(V8x8Ty, V8x64Ty)); + EXPECT_EQ(CastInst::getCastOpcode(c64, true, V8x8Ty, true), CastInst::Trunc); + EXPECT_EQ(CastInst::getCastOpcode(c8, true, V8x64Ty, true), CastInst::SExt); } } // end anonymous namespace From fvbommel at gmail.com Wed May 18 02:44:19 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Wed, 18 May 2011 09:44:19 +0200 Subject: [llvm-commits] [llvm] r131516 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/InstCombine/InstructionCombining.cpp test/Transforms/InstCombine/call.ll In-Reply-To: <20110518012827.9FAAB2A6C12C@llvm.org> References: <20110518012827.9FAAB2A6C12C@llvm.org> Message-ID: On Wed, May 18, 2011 at 3:28 AM, Eli Friedman wrote: > Start trying to make InstCombine preserve more debug info. ?The idea here is > to set the debug location on the IRBuilder, which will be then right > location in most cases. ?This should magically give many transformations > debug locations, and fixing places which are missing a debug location will > usually just means changing the code creating it to use the IRBuilder. > ? ? // Now that we have an instruction, try combining it to simplify it. > ? ? Builder->SetInsertPoint(I->getParent(), I); > + ? ?Builder->SetCurrentDebugLocation(I->getDebugLoc()); This would look even nicer if the IRBuilder::SetInsertPoint() overloads that take an Instruction* did this automatically :). That would also make the migration of other passes to IRBuilder look cleaner. IRBuilder users that want a different DebugLoc can always set it manually... From baldrick at free.fr Wed May 18 03:06:18 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 18 May 2011 08:06:18 -0000 Subject: [llvm-commits] [dragonegg] r131531 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110518080618.3E5A12A6C12D@llvm.org> Author: baldrick Date: Wed May 18 03:06:18 2011 New Revision: 131531 URL: http://llvm.org/viewvc/llvm-project?rev=131531&view=rev Log: Simplify using CastToAnyType now that getCastOpcode understands vector types better. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=131531&r1=131530&r2=131531&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Wed May 18 03:06:18 2011 @@ -7109,14 +7109,11 @@ // Truncate the input elements to the output element type, eg: <2 x double> // -> <2 x float>. unsigned Length = TYPE_VECTOR_SUBPARTS(TREE_TYPE(op0)); - const Type *TruncTy = VectorType::get(getRegType(TREE_TYPE(type)), Length); - if (FLOAT_TYPE_P(TREE_TYPE(type))) { - LHS = Builder.CreateFPTrunc(LHS, TruncTy); - RHS = Builder.CreateFPTrunc(RHS, TruncTy); - } else { - LHS = Builder.CreateTrunc(LHS, TruncTy); - RHS = Builder.CreateTrunc(RHS, TruncTy); - } + const Type *DestTy = VectorType::get(getRegType(TREE_TYPE(type)), Length); + LHS = CastToAnyType(LHS, !TYPE_UNSIGNED(TREE_TYPE(op0)), DestTy, + !TYPE_UNSIGNED(TREE_TYPE(type))); + RHS = CastToAnyType(RHS, !TYPE_UNSIGNED(TREE_TYPE(op0)), DestTy, + !TYPE_UNSIGNED(TREE_TYPE(type))); // Concatenate the truncated inputs into one vector of twice the length, // eg: <2 x float>, <2 x float> -> <4 x float>. @@ -7136,12 +7133,9 @@ // Extend the input elements to the output element type, eg: <2 x float> // -> <2 x double>. - const Type *ExtTy = getRegType(type); - if (FLOAT_TYPE_P(TREE_TYPE(TREE_TYPE(op0)))) - return Builder.CreateFPExt(Op, ExtTy); - if (TYPE_UNSIGNED(TREE_TYPE(TREE_TYPE(op0)))) - return Builder.CreateZExt(Op, ExtTy); - return Builder.CreateSExt(Op, ExtTy); + const Type *DestTy = getRegType(type); + return CastToAnyType(Op, !TYPE_UNSIGNED(TREE_TYPE(op0)), DestTy, + !TYPE_UNSIGNED(TREE_TYPE(type))); } Value *TreeToLLVM::EmitReg_VEC_UNPACK_LO_EXPR(tree type, tree op0) { @@ -7153,12 +7147,9 @@ // Extend the input elements to the output element type, eg: <2 x float> // -> <2 x double>. - const Type *ExtTy = getRegType(type); - if (FLOAT_TYPE_P(TREE_TYPE(TREE_TYPE(op0)))) - return Builder.CreateFPExt(Op, ExtTy); - if (TYPE_UNSIGNED(TREE_TYPE(TREE_TYPE(op0)))) - return Builder.CreateZExt(Op, ExtTy); - return Builder.CreateSExt(Op, ExtTy); + const Type *DestTy = getRegType(type); + return CastToAnyType(Op, !TYPE_UNSIGNED(TREE_TYPE(op0)), DestTy, + !TYPE_UNSIGNED(TREE_TYPE(type))); } From nadav.rotem at intel.com Wed May 18 04:04:47 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Wed, 18 May 2011 12:04:47 +0300 Subject: [llvm-commits] [PATCH] TypeLegalizer refactoring (a part of vector-select support) Message-ID: <6594DDFF12B03D4E89690887C2486994027D7F8F7A@hasmsx504.ger.corp.intel.com> Hi, I started working on supporting vector-select in the codegen. I sent a big patch [1] two weeks ago, which adds this support. You can give it a try and see if you like the generates code. However, the patch I sent is pretty big and touches many parts in the codegen (and no one on the list reviewed it). I decided to break it to smaller pieces and start pushing it gradually. In this email I attached a patch for refactoring getActionType and getTypeToTransformTo and placing all of the 'extended type decision' in one place. I would appreciate a review. Thanks, Nadav [1] - http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110502/120445.html --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110518/f1384692/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: legalizer_level1.diff Type: application/octet-stream Size: 11318 bytes Desc: legalizer_level1.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110518/f1384692/attachment.obj From baldrick at free.fr Wed May 18 04:21:57 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 18 May 2011 09:21:57 -0000 Subject: [llvm-commits] [llvm] r131532 - in /llvm/trunk: lib/VMCore/Instructions.cpp test/Assembler/invalid_cast.ll test/Assembler/invalid_cast2.ll Message-ID: <20110518092157.7DD6C2A6C12C@llvm.org> Author: baldrick Date: Wed May 18 04:21:57 2011 New Revision: 131532 URL: http://llvm.org/viewvc/llvm-project?rev=131532&view=rev Log: Tighten up checking of the validity of casts. (1) The IR parser would happily accept things like "sext <2 x i32> to <999 x i64>". It would also accept "sext <2 x i32> to i64", though the verifier would catch that later. Fixed by having castIsValid check that vector lengths match except when doing a bitcast. (2) When creating a cast instruction, check that the cast is valid (this was already done when creating constexpr casts). While there, replace getScalarSizeInBits (used to allow more vector casts) with getPrimitiveSizeInBits in getCastOpcode and isCastable since vector to vector casts are now handled explicitly by passing to the element types; i.e. this bit should result in no functional change. Added: llvm/trunk/test/Assembler/invalid_cast.ll llvm/trunk/test/Assembler/invalid_cast2.ll Modified: llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=131532&r1=131531&r2=131532&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Wed May 18 04:21:57 2011 @@ -2076,6 +2076,7 @@ CastInst *CastInst::Create(Instruction::CastOps op, Value *S, const Type *Ty, const Twine &Name, Instruction *InsertBefore) { + assert(castIsValid(op, S, Ty) && "Invalid cast!"); // Construct and return the appropriate CastInst subclass switch (op) { case Trunc: return new TruncInst (S, Ty, Name, InsertBefore); @@ -2098,6 +2099,7 @@ CastInst *CastInst::Create(Instruction::CastOps op, Value *S, const Type *Ty, const Twine &Name, BasicBlock *InsertAtEnd) { + assert(castIsValid(op, S, Ty) && "Invalid cast!"); // Construct and return the appropriate CastInst subclass switch (op) { case Trunc: return new TruncInst (S, Ty, Name, InsertAtEnd); @@ -2263,8 +2265,8 @@ } // Get the bit sizes, we'll need these - unsigned SrcBits = SrcTy->getScalarSizeInBits(); // 0 for ptr - unsigned DestBits = DestTy->getScalarSizeInBits(); // 0 for ptr + unsigned SrcBits = SrcTy->getPrimitiveSizeInBits(); // 0 for ptr + unsigned DestBits = DestTy->getPrimitiveSizeInBits(); // 0 for ptr // Run through the possibilities ... if (DestTy->isIntegerTy()) { // Casting to integral @@ -2348,8 +2350,8 @@ } // Get the bit sizes, we'll need these - unsigned SrcBits = SrcTy->getScalarSizeInBits(); // 0 for ptr - unsigned DestBits = DestTy->getScalarSizeInBits(); // 0 for ptr + unsigned SrcBits = SrcTy->getPrimitiveSizeInBits(); // 0 for ptr + unsigned DestBits = DestTy->getPrimitiveSizeInBits(); // 0 for ptr // Run through the possibilities ... if (DestTy->isIntegerTy()) { // Casting to integral @@ -2463,46 +2465,40 @@ unsigned SrcBitSize = SrcTy->getScalarSizeInBits(); unsigned DstBitSize = DstTy->getScalarSizeInBits(); + // If these are vector types, get the lengths of the vectors (using zero for + // scalar types means that checking that vector lengths match also checks that + // scalars are not being converted to vectors or vectors to scalars). + unsigned SrcLength = SrcTy->isVectorTy() ? + cast(SrcTy)->getNumElements() : 0; + unsigned DstLength = DstTy->isVectorTy() ? + cast(DstTy)->getNumElements() : 0; + // Switch on the opcode provided switch (op) { default: return false; // This is an input error case Instruction::Trunc: - return SrcTy->isIntOrIntVectorTy() && - DstTy->isIntOrIntVectorTy()&& SrcBitSize > DstBitSize; + return SrcTy->isIntOrIntVectorTy() && DstTy->isIntOrIntVectorTy() && + SrcLength == DstLength && SrcBitSize > DstBitSize; case Instruction::ZExt: - return SrcTy->isIntOrIntVectorTy() && - DstTy->isIntOrIntVectorTy()&& SrcBitSize < DstBitSize; + return SrcTy->isIntOrIntVectorTy() && DstTy->isIntOrIntVectorTy() && + SrcLength == DstLength && SrcBitSize < DstBitSize; case Instruction::SExt: - return SrcTy->isIntOrIntVectorTy() && - DstTy->isIntOrIntVectorTy()&& SrcBitSize < DstBitSize; + return SrcTy->isIntOrIntVectorTy() && DstTy->isIntOrIntVectorTy() && + SrcLength == DstLength && SrcBitSize < DstBitSize; case Instruction::FPTrunc: - return SrcTy->isFPOrFPVectorTy() && - DstTy->isFPOrFPVectorTy() && - SrcBitSize > DstBitSize; + return SrcTy->isFPOrFPVectorTy() && DstTy->isFPOrFPVectorTy() && + SrcLength == DstLength && SrcBitSize > DstBitSize; case Instruction::FPExt: - return SrcTy->isFPOrFPVectorTy() && - DstTy->isFPOrFPVectorTy() && - SrcBitSize < DstBitSize; + return SrcTy->isFPOrFPVectorTy() && DstTy->isFPOrFPVectorTy() && + SrcLength == DstLength && SrcBitSize < DstBitSize; case Instruction::UIToFP: case Instruction::SIToFP: - if (const VectorType *SVTy = dyn_cast(SrcTy)) { - if (const VectorType *DVTy = dyn_cast(DstTy)) { - return SVTy->getElementType()->isIntOrIntVectorTy() && - DVTy->getElementType()->isFPOrFPVectorTy() && - SVTy->getNumElements() == DVTy->getNumElements(); - } - } - return SrcTy->isIntOrIntVectorTy() && DstTy->isFPOrFPVectorTy(); + return SrcTy->isIntOrIntVectorTy() && DstTy->isFPOrFPVectorTy() && + SrcLength == DstLength; case Instruction::FPToUI: case Instruction::FPToSI: - if (const VectorType *SVTy = dyn_cast(SrcTy)) { - if (const VectorType *DVTy = dyn_cast(DstTy)) { - return SVTy->getElementType()->isFPOrFPVectorTy() && - DVTy->getElementType()->isIntOrIntVectorTy() && - SVTy->getNumElements() == DVTy->getNumElements(); - } - } - return SrcTy->isFPOrFPVectorTy() && DstTy->isIntOrIntVectorTy(); + return SrcTy->isFPOrFPVectorTy() && DstTy->isIntOrIntVectorTy() && + SrcLength == DstLength; case Instruction::PtrToInt: return SrcTy->isPointerTy() && DstTy->isIntegerTy(); case Instruction::IntToPtr: Added: llvm/trunk/test/Assembler/invalid_cast.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/invalid_cast.ll?rev=131532&view=auto ============================================================================== --- llvm/trunk/test/Assembler/invalid_cast.ll (added) +++ llvm/trunk/test/Assembler/invalid_cast.ll Wed May 18 04:21:57 2011 @@ -0,0 +1,6 @@ +; RUN: not llvm-as < %s |& grep {invalid cast opcode} + +define <3 x i8> @foo(<4 x i64> %x) { + %y = trunc <4 x i64> %x to <3 x i8> + ret <3 x i8> %y +} Added: llvm/trunk/test/Assembler/invalid_cast2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/invalid_cast2.ll?rev=131532&view=auto ============================================================================== --- llvm/trunk/test/Assembler/invalid_cast2.ll (added) +++ llvm/trunk/test/Assembler/invalid_cast2.ll Wed May 18 04:21:57 2011 @@ -0,0 +1,6 @@ +; RUN: not llvm-as < %s |& grep {invalid cast opcode} + +define i8 @foo(<4 x i64> %x) { + %y = trunc <4 x i64> %x to i8 + ret i8 %y +} From baldrick at free.fr Wed May 18 05:59:25 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 18 May 2011 10:59:25 -0000 Subject: [llvm-commits] [llvm] r131533 - /llvm/trunk/lib/VMCore/Instructions.cpp Message-ID: <20110518105925.DACB42A6C12C@llvm.org> Author: baldrick Date: Wed May 18 05:59:25 2011 New Revision: 131533 URL: http://llvm.org/viewvc/llvm-project?rev=131533&view=rev Log: Now that SrcBits and DestBits always represent the primitive size, rather than either the primitive size or the element primitive size (in the case of vectors), simplify the vector logic. No functionality change. There is some distracting churn in the patch because I lined up comments better while there - sorry about that. Modified: llvm/trunk/lib/VMCore/Instructions.cpp Modified: llvm/trunk/lib/VMCore/Instructions.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=131533&r1=131532&r2=131533&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Instructions.cpp (original) +++ llvm/trunk/lib/VMCore/Instructions.cpp Wed May 18 05:59:25 2011 @@ -2269,55 +2269,43 @@ unsigned DestBits = DestTy->getPrimitiveSizeInBits(); // 0 for ptr // Run through the possibilities ... - if (DestTy->isIntegerTy()) { // Casting to integral - if (SrcTy->isIntegerTy()) { // Casting from integral + if (DestTy->isIntegerTy()) { // Casting to integral + if (SrcTy->isIntegerTy()) { // Casting from integral return true; - } else if (SrcTy->isFloatingPointTy()) { // Casting from floating pt + } else if (SrcTy->isFloatingPointTy()) { // Casting from floating pt return true; - } else if (const VectorType *PTy = dyn_cast(SrcTy)) { - // Casting from vector - return DestBits == PTy->getBitWidth(); + } else if (SrcTy->isVectorTy()) { // Casting from vector + return DestBits == SrcBits; } else { // Casting from something else return SrcTy->isPointerTy(); } - } else if (DestTy->isFloatingPointTy()) { // Casting to floating pt - if (SrcTy->isIntegerTy()) { // Casting from integral + } else if (DestTy->isFloatingPointTy()) { // Casting to floating pt + if (SrcTy->isIntegerTy()) { // Casting from integral return true; - } else if (SrcTy->isFloatingPointTy()) { // Casting from floating pt + } else if (SrcTy->isFloatingPointTy()) { // Casting from floating pt return true; - } else if (const VectorType *PTy = dyn_cast(SrcTy)) { - // Casting from vector - return DestBits == PTy->getBitWidth(); + } else if (SrcTy->isVectorTy()) { // Casting from vector + return DestBits == SrcBits; } else { // Casting from something else return false; } - } else if (const VectorType *DestPTy = dyn_cast(DestTy)) { - // Casting to vector - if (const VectorType *SrcPTy = dyn_cast(SrcTy)) { - // Casting from vector - return DestPTy->getBitWidth() == SrcPTy->getBitWidth(); - } else if (DestPTy->getBitWidth() == SrcBits) { - return true; // float/int -> vector - } else if (SrcTy->isX86_MMXTy()) { - return DestPTy->getBitWidth() == 64; // MMX to 64-bit vector - } else { - return false; - } + } else if (DestTy->isVectorTy()) { // Casting to vector + return DestBits == SrcBits; } else if (DestTy->isPointerTy()) { // Casting to pointer - if (SrcTy->isPointerTy()) { // Casting from pointer + if (SrcTy->isPointerTy()) { // Casting from pointer return true; - } else if (SrcTy->isIntegerTy()) { // Casting from integral + } else if (SrcTy->isIntegerTy()) { // Casting from integral return true; - } else { // Casting from something else + } else { // Casting from something else return false; } } else if (DestTy->isX86_MMXTy()) { - if (const VectorType *SrcPTy = dyn_cast(SrcTy)) { - return SrcPTy->getBitWidth() == 64; // 64-bit vector to MMX + if (SrcTy->isVectorTy()) { + return DestBits == SrcBits; // 64-bit vector to MMX } else { return false; } - } else { // Casting to something else + } else { // Casting to something else return false; } } @@ -2371,10 +2359,9 @@ return FPToSI; // FP -> sint else return FPToUI; // FP -> uint - } else if (const VectorType *PTy = dyn_cast(SrcTy)) { - assert(DestBits == PTy->getBitWidth() && - "Casting vector to integer of different width"); - PTy = NULL; + } else if (SrcTy->isVectorTy()) { + assert(DestBits == SrcBits && + "Casting vector to integer of different width"); return BitCast; // Same size, no-op cast } else { assert(SrcTy->isPointerTy() && @@ -2395,29 +2382,17 @@ } else { return BitCast; // same size, no-op cast } - } else if (const VectorType *PTy = dyn_cast(SrcTy)) { - assert(DestBits == PTy->getBitWidth() && + } else if (SrcTy->isVectorTy()) { + assert(DestBits == SrcBits && "Casting vector to floating point of different width"); - PTy = NULL; return BitCast; // same size, no-op cast } else { llvm_unreachable("Casting pointer or non-first class to float"); } - } else if (const VectorType *DestPTy = dyn_cast(DestTy)) { - if (const VectorType *SrcPTy = dyn_cast(SrcTy)) { - assert(DestPTy->getBitWidth() == SrcPTy->getBitWidth() && - "Casting vector to vector of different widths"); - (void)SrcPTy; - return BitCast; // vector -> vector - } else if (DestPTy->getBitWidth() == SrcBits) { - return BitCast; // float/int -> vector - } else if (SrcTy->isX86_MMXTy()) { - assert(DestPTy->getBitWidth()==64 && - "Casting X86_MMX to vector of wrong width"); - return BitCast; // MMX to 64-bit vector - } else { - assert(!"Illegal cast to vector (wrong type or size)"); - } + } else if (DestTy->isVectorTy()) { + assert(DestBits == SrcBits && + "Illegal cast to vector (wrong type or size)"); + return BitCast; } else if (DestTy->isPointerTy()) { if (SrcTy->isPointerTy()) { return BitCast; // ptr -> ptr @@ -2427,9 +2402,8 @@ assert(!"Casting pointer to other than pointer or int"); } } else if (DestTy->isX86_MMXTy()) { - if (isa(SrcTy)) { - assert(cast(SrcTy)->getBitWidth() == 64 && - "Casting vector of wrong width to X86_MMX"); + if (SrcTy->isVectorTy()) { + assert(DestBits == SrcBits && "Casting vector of wrong width to X86_MMX"); return BitCast; // 64-bit vector to MMX } else { assert(!"Illegal cast to X86_MMX"); From baldrick at free.fr Wed May 18 07:02:06 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 18 May 2011 14:02:06 +0200 Subject: [llvm-commits] [PATCH] TypeLegalizer refactoring (a part of vector-select support) In-Reply-To: <6594DDFF12B03D4E89690887C2486994027D7F8F7A@hasmsx504.ger.corp.intel.com> References: <6594DDFF12B03D4E89690887C2486994027D7F8F7A@hasmsx504.ger.corp.intel.com> Message-ID: <4DD3B53E.5090901@free.fr> Hi Nadav, > @@ -1814,6 +1732,74 @@ > > ValueTypeActionImpl ValueTypeActions; > > + typedef std::pair LegalizeKind; > + > + LegalizeKind > + getTypeConversion(LLVMContext &Context, EVT VT) const { did you try defining this out-of-line? It is rather big to be in a header file. Last time I tried to do this I failed due to circular library dependencies being created, but perhaps things are better now. > + // If this is a simple type, use the ComputeRegisterProp mechanism. > + if (VT.isSimple()) { > + assert((unsigned)VT.getSimpleVT().SimpleTy < > + array_lengthof(TransformToType)); > + EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; > + LegalizeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT()); > + /*assert(ValueTypeActions.getTypeAction(NVT) != Promote && > + "Promote may not follow Expand or Promote");*/ did you mean to comment out this assertion? > + return LegalizeKind(LA, NVT); > + } > + > + // Handle Extended Scalar Types. > + if (!VT.isVector()) { > + > + assert(VT.isInteger() && "Float types must be simple"); > + unsigned BitSize = VT.getSizeInBits(); > + // First promote to a power-of-two size, then expand if necessary. > + if (BitSize < 8 || !isPowerOf2_32(BitSize)) { > + return LegalizeKind(Promote, VT.getRoundIntegerType(Context)); > + } No need for curly brackets. > + return LegalizeKind(Expand, > + EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); > + } > + > + // Handle vector types. > + unsigned NumElts = VT.getVectorNumElements(); > + EVT EltVT = VT.getVectorElementType(); > + > + // Vectors with only one element are always scalarized. > + if (NumElts == 1) { > + return LegalizeKind(Expand, EltVT); > + } No need for curly brackets. Otherwise it looks good. Thanks for working on this! Ciao, Duncan. From nadav.rotem at intel.com Wed May 18 07:18:20 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Wed, 18 May 2011 15:18:20 +0300 Subject: [llvm-commits] [PATCH] TypeLegalizer refactoring (a part of vector-select support) In-Reply-To: <4DD3B53E.5090901@free.fr> References: <6594DDFF12B03D4E89690887C2486994027D7F8F7A@hasmsx504.ger.corp.intel.com> <4DD3B53E.5090901@free.fr> Message-ID: <6594DDFF12B03D4E89690887C2486994027D7F914B@hasmsx504.ger.corp.intel.com> Hi Duncan, I also hit the circular dependency issue when moving this method to the cpp file. I will fix the other issues you mentioned and commit. Thanks, Nadav -----Original Message----- From: llvm-commits-bounces at cs.uiuc.edu [mailto:llvm-commits-bounces at cs.uiuc.edu] On Behalf Of Duncan Sands Sent: Wednesday, May 18, 2011 15:02 To: llvm-commits at cs.uiuc.edu Subject: Re: [llvm-commits] [PATCH] TypeLegalizer refactoring (a part of vector-select support) Hi Nadav, > @@ -1814,6 +1732,74 @@ > > ValueTypeActionImpl ValueTypeActions; > > + typedef std::pair LegalizeKind; > + > + LegalizeKind > + getTypeConversion(LLVMContext &Context, EVT VT) const { did you try defining this out-of-line? It is rather big to be in a header file. Last time I tried to do this I failed due to circular library dependencies being created, but perhaps things are better now. > + // If this is a simple type, use the ComputeRegisterProp mechanism. > + if (VT.isSimple()) { > + assert((unsigned)VT.getSimpleVT().SimpleTy < > + array_lengthof(TransformToType)); > + EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; > + LegalizeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT()); > + /*assert(ValueTypeActions.getTypeAction(NVT) != Promote && > + "Promote may not follow Expand or Promote");*/ did you mean to comment out this assertion? > + return LegalizeKind(LA, NVT); > + } > + > + // Handle Extended Scalar Types. > + if (!VT.isVector()) { > + > + assert(VT.isInteger() && "Float types must be simple"); > + unsigned BitSize = VT.getSizeInBits(); > + // First promote to a power-of-two size, then expand if necessary. > + if (BitSize < 8 || !isPowerOf2_32(BitSize)) { > + return LegalizeKind(Promote, VT.getRoundIntegerType(Context)); > + } No need for curly brackets. > + return LegalizeKind(Expand, > + EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); > + } > + > + // Handle vector types. > + unsigned NumElts = VT.getVectorNumElements(); > + EVT EltVT = VT.getVectorElementType(); > + > + // Vectors with only one element are always scalarized. > + if (NumElts == 1) { > + return LegalizeKind(Expand, EltVT); > + } No need for curly brackets. Otherwise it looks good. Thanks for working on this! Ciao, Duncan. _______________________________________________ llvm-commits mailing list llvm-commits at cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. From nadav.rotem at intel.com Wed May 18 07:26:38 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Wed, 18 May 2011 12:26:38 -0000 Subject: [llvm-commits] [llvm] r131534 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Transforms/Scalar/CodeGenPrepare.cpp Message-ID: <20110518122638.E97FA2A6C12C@llvm.org> Author: nadav Date: Wed May 18 07:26:38 2011 New Revision: 131534 URL: http://llvm.org/viewvc/llvm-project?rev=131534&view=rev Log: Refactor getActionType and getTypeToTransformTo ; place all of the 'decision' code in one place. Modified: llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=131534&r1=131533&r2=131534&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed May 18 07:26:38 2011 @@ -204,62 +204,11 @@ /// that indicates how instruction selection should deal with the type. uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; - LegalizeAction getExtendedTypeAction(EVT VT) const { - // Handle non-vector integers. - if (!VT.isVector()) { - assert(VT.isInteger() && "Unsupported extended type!"); - unsigned BitSize = VT.getSizeInBits(); - // First promote to a power-of-two size, then expand if necessary. - if (BitSize < 8 || !isPowerOf2_32(BitSize)) - return Promote; - return Expand; - } - - // Vectors with only one element are always scalarized. - if (VT.getVectorNumElements() == 1) - return Expand; - - // Vectors with a number of elements that is not a power of two are always - // widened, for example <3 x float> -> <4 x float>. - if (!VT.isPow2VectorType()) - return Promote; - - // Vectors with a crazy element type are always expanded, for example - // <4 x i2> is expanded into two vectors of type <2 x i2>. - if (!VT.getVectorElementType().isSimple()) - return Expand; - - // If this type is smaller than a legal vector type then widen it, - // otherwise expand it. E.g. <2 x float> -> <4 x float>. - MVT EltType = VT.getVectorElementType().getSimpleVT(); - unsigned NumElts = VT.getVectorNumElements(); - while (1) { - // Round up to the next power of 2. - NumElts = (unsigned)NextPowerOf2(NumElts); - - // If there is no simple vector type with this many elements then there - // cannot be a larger legal vector type. Note that this assumes that - // there are no skipped intermediate vector types in the simple types. - MVT LargerVector = MVT::getVectorVT(EltType, NumElts); - if (LargerVector == MVT()) - return Expand; - - // If this type is legal then widen the vector. - if (getTypeAction(LargerVector) == Legal) - return Promote; - } - } public: ValueTypeActionImpl() { std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); } - LegalizeAction getTypeAction(EVT VT) const { - if (!VT.isExtended()) - return getTypeAction(VT.getSimpleVT()); - return getExtendedTypeAction(VT); - } - LegalizeAction getTypeAction(MVT VT) const { return (LegalizeAction)ValueTypeActions[VT.SimpleTy]; } @@ -278,8 +227,8 @@ /// it is already legal (return 'Legal') or we need to promote it to a larger /// type (return 'Promote'), or we need to expand it into multiple registers /// of smaller integer type (return 'Expand'). 'Custom' is not an option. - LegalizeAction getTypeAction(EVT VT) const { - return ValueTypeActions.getTypeAction(VT); + LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { + return getTypeConversion(Context, VT).first; } LegalizeAction getTypeAction(MVT VT) const { return ValueTypeActions.getTypeAction(VT); @@ -292,38 +241,7 @@ /// to get to the smaller register. For illegal floating point types, this /// returns the integer type to transform to. EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { - if (VT.isSimple()) { - assert((unsigned)VT.getSimpleVT().SimpleTy < - array_lengthof(TransformToType)); - EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; - assert(getTypeAction(NVT) != Promote && - "Promote may not follow Expand or Promote"); - return NVT; - } - - if (VT.isVector()) { - EVT NVT = VT.getPow2VectorType(Context); - if (NVT == VT) { - // Vector length is a power of 2 - split to half the size. - unsigned NumElts = VT.getVectorNumElements(); - EVT EltVT = VT.getVectorElementType(); - return (NumElts == 1) ? - EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); - } - // Promote to a power of two size, avoiding multi-step promotion. - return getTypeAction(NVT) == Promote ? - getTypeToTransformTo(Context, NVT) : NVT; - } else if (VT.isInteger()) { - EVT NVT = VT.getRoundIntegerType(Context); - if (NVT == VT) // Size is a power of two - expand to half the size. - return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); - - // Promote to a power of two size, avoiding multi-step promotion. - return getTypeAction(NVT) == Promote ? - getTypeToTransformTo(Context, NVT) : NVT; - } - assert(0 && "Unsupported extended type!"); - return MVT(MVT::Other); // Not reached + return getTypeConversion(Context, VT).second; } /// getTypeToExpandTo - For types supported by the target, this is an @@ -333,7 +251,7 @@ EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { assert(!VT.isVector()); while (true) { - switch (getTypeAction(VT)) { + switch (getTypeAction(Context, VT)) { case Legal: return VT; case Expand: @@ -1814,6 +1732,73 @@ ValueTypeActionImpl ValueTypeActions; + typedef std::pair LegalizeKind; + + LegalizeKind + getTypeConversion(LLVMContext &Context, EVT VT) const { + // If this is a simple type, use the ComputeRegisterProp mechanism. + if (VT.isSimple()) { + assert((unsigned)VT.getSimpleVT().SimpleTy < + array_lengthof(TransformToType)); + EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; + LegalizeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT()); + if (NVT.isSimple() && LA != Legal) + assert(ValueTypeActions.getTypeAction(NVT.getSimpleVT()) != Promote && + "Promote may not follow Expand or Promote"); + return LegalizeKind(LA, NVT); + } + + // Handle Extended Scalar Types. + if (!VT.isVector()) { + assert(VT.isInteger() && "Float types must be simple"); + unsigned BitSize = VT.getSizeInBits(); + // First promote to a power-of-two size, then expand if necessary. + if (BitSize < 8 || !isPowerOf2_32(BitSize)) + return LegalizeKind(Promote, VT.getRoundIntegerType(Context)); + + return LegalizeKind(Expand, + EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); + } + + // Handle vector types. + unsigned NumElts = VT.getVectorNumElements(); + EVT EltVT = VT.getVectorElementType(); + + // Vectors with only one element are always scalarized. + if (NumElts == 1) + return LegalizeKind(Expand, EltVT); + + // Try to widen the vector until a legal type is found. + // If there is no wider legal type, split the vector. + while (1) { + // Round up to the next power of 2. + NumElts = (unsigned)NextPowerOf2(NumElts); + + // If there is no simple vector type with this many elements then there + // cannot be a larger legal vector type. Note that this assumes that + // there are no skipped intermediate vector types in the simple types. + MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); + if (LargerVector == MVT()) break; + + // If this type is legal then widen the vector. + if (ValueTypeActions.getTypeAction(LargerVector) == Legal) + return LegalizeKind(Promote, LargerVector); + } + + // Widen odd vectors to next power of two. + if (!VT.isPow2VectorType()) { + EVT NVT = VT.getPow2VectorType(Context); + return LegalizeKind(Promote, NVT); + } + + // Vectors with illegal element types are expanded. + EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); + return LegalizeKind(Expand, NVT); + + assert(false && "Unable to handle this kind of vector type"); + return LegalizeKind(Legal, VT); + } + std::vector > AvailableRegClasses; /// TargetDAGCombineArray - Targets can specify ISD nodes that they would Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=131534&r1=131533&r2=131534&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed May 18 07:26:38 2011 @@ -91,7 +91,7 @@ /// it is already legal or we need to expand it into multiple registers of /// smaller integer type, or we need to promote it to a larger type. LegalizeAction getTypeAction(EVT VT) const { - return (LegalizeAction)ValueTypeActions.getTypeAction(VT); + return (LegalizeAction)TLI.getTypeAction(*DAG.getContext(), VT); } /// isTypeLegal - Return true if this type is legal on this target. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=131534&r1=131533&r2=131534&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed May 18 07:26:38 2011 @@ -75,7 +75,7 @@ /// getTypeAction - Return how we should legalize values of this type. LegalizeAction getTypeAction(EVT VT) const { - switch (ValueTypeActions.getTypeAction(VT)) { + switch (TLI.getTypeAction(*DAG.getContext(), VT)) { default: assert(false && "Unknown legalize action!"); case TargetLowering::Legal: @@ -108,7 +108,7 @@ /// isTypeLegal - Return true if this type is legal on this target. bool isTypeLegal(EVT VT) const { - return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal; + return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::Legal; } /// IgnoreNodeResults - Pretend all of this node's results are legal. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=131534&r1=131533&r2=131534&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed May 18 07:26:38 2011 @@ -892,7 +892,7 @@ // If there is a wider vector type with the same element type as this one, // we should widen to that legal vector type. This handles things like // <2 x float> -> <4 x float>. - if (NumElts != 1 && getTypeAction(VT) == Promote) { + if (NumElts != 1 && getTypeAction(Context, VT) == Promote) { RegisterVT = getTypeToTransformTo(Context, VT); if (isTypeLegal(RegisterVT)) { IntermediateVT = RegisterVT; Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=131534&r1=131533&r2=131534&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Wed May 18 07:26:38 2011 @@ -371,9 +371,9 @@ // If these values will be promoted, find out what they will be promoted // to. This helps us consider truncates on PPC as noop copies when they // are. - if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) + if (TLI.getTypeAction(CI->getContext(), SrcVT) == TargetLowering::Promote) SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT); - if (TLI.getTypeAction(DstVT) == TargetLowering::Promote) + if (TLI.getTypeAction(CI->getContext(), DstVT) == TargetLowering::Promote) DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); // If, after promotion, these are the same types, this is a noop copy. From baldrick at free.fr Wed May 18 07:40:13 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 18 May 2011 14:40:13 +0200 Subject: [llvm-commits] [llvm] r131534 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Transforms/Scalar/CodeGenPrepare.cpp In-Reply-To: <20110518122638.E97FA2A6C12C@llvm.org> References: <20110518122638.E97FA2A6C12C@llvm.org> Message-ID: <4DD3BE2D.70006@free.fr> Hi Nadav, > @@ -1814,6 +1732,73 @@ > > ValueTypeActionImpl ValueTypeActions; > > + typedef std::pair LegalizeKind; > + > + LegalizeKind > + getTypeConversion(LLVMContext&Context, EVT VT) const { > + // If this is a simple type, use the ComputeRegisterProp mechanism. > + if (VT.isSimple()) { > + assert((unsigned)VT.getSimpleVT().SimpleTy< > + array_lengthof(TransformToType)); > + EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; > + LegalizeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT()); > + if (NVT.isSimple()&& LA != Legal) > + assert(ValueTypeActions.getTypeAction(NVT.getSimpleVT()) != Promote&& > + "Promote may not follow Expand or Promote"); did you really mean to have the assertion be guarded by that "if" statement? Better to incorporate the condition into the assert. Ciao, Duncan. From cdavis at mymail.mines.edu Wed May 18 08:05:45 2011 From: cdavis at mymail.mines.edu (Charles Davis) Date: Wed, 18 May 2011 07:05:45 -0600 Subject: [llvm-commits] [llvm] r131525 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp In-Reply-To: <4DD35B7C.6000506@free.fr> References: <20110518045805.E92FE2A6C12C@llvm.org> <4DD35B7C.6000506@free.fr> Message-ID: <4DD3C429.3060707@mymail.mines.edu> On 5/17/11 11:39 PM, Duncan Sands wrote: > Hi Charles, > >> Implement the Win64 EH directive methods for the assembly language streamer. >> >> GAS has no such directives (not even mingw-w64 GAS has them), so I took >> creative license with their names in assembly. > > what about the native windows assembler (assuming there is such a thing...)? I based my directives on the native Windows assembler--MASM. Last I checked, LLVM doesn't support emitting assembly for MASM. (Would somebody correct me on that if I'm wrong?) Chip From anton at korobeynikov.info Wed May 18 09:54:04 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Wed, 18 May 2011 18:54:04 +0400 Subject: [llvm-commits] [llvm] r131525 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp In-Reply-To: <4DD3C429.3060707@mymail.mines.edu> References: <20110518045805.E92FE2A6C12C@llvm.org> <4DD35B7C.6000506@free.fr> <4DD3C429.3060707@mymail.mines.edu> Message-ID: Chip, >> what about the native windows assembler (assuming there is such a thing...)? > I based my directives on the native Windows assembler--MASM. Last I > checked, LLVM doesn't support emitting assembly for MASM. (Would > somebody correct me on that if I'm wrong?) Exactly. MASM is too weak to support stuff necessary for C++ binaries. -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From baldrick at free.fr Wed May 18 09:53:51 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 18 May 2011 14:53:51 -0000 Subject: [llvm-commits] [test-suite] r131535 - in /test-suite/trunk/SingleSource/UnitTests/SetjmpLongjmp/C: MultipleSetjmp.c WhileLoop.c Message-ID: <20110518145351.2D28B2A6C12C@llvm.org> Author: baldrick Date: Wed May 18 09:53:50 2011 New Revision: 131535 URL: http://llvm.org/viewvc/llvm-project?rev=131535&view=rev Log: Make these tests return a deterministic exit code. Modified: test-suite/trunk/SingleSource/UnitTests/SetjmpLongjmp/C/MultipleSetjmp.c test-suite/trunk/SingleSource/UnitTests/SetjmpLongjmp/C/WhileLoop.c Modified: test-suite/trunk/SingleSource/UnitTests/SetjmpLongjmp/C/MultipleSetjmp.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/SetjmpLongjmp/C/MultipleSetjmp.c?rev=131535&r1=131534&r2=131535&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/SetjmpLongjmp/C/MultipleSetjmp.c (original) +++ test-suite/trunk/SingleSource/UnitTests/SetjmpLongjmp/C/MultipleSetjmp.c Wed May 18 09:53:50 2011 @@ -23,4 +23,6 @@ } else { bar(buf, 37); } + + return 0; } Modified: test-suite/trunk/SingleSource/UnitTests/SetjmpLongjmp/C/WhileLoop.c URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/SetjmpLongjmp/C/WhileLoop.c?rev=131535&r1=131534&r2=131535&view=diff ============================================================================== --- test-suite/trunk/SingleSource/UnitTests/SetjmpLongjmp/C/WhileLoop.c (original) +++ test-suite/trunk/SingleSource/UnitTests/SetjmpLongjmp/C/WhileLoop.c Wed May 18 09:53:50 2011 @@ -21,4 +21,6 @@ foo(buf, i); } } + + return 0; } From baldrick at free.fr Wed May 18 09:57:56 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 18 May 2011 14:57:56 -0000 Subject: [llvm-commits] [llvm] r131536 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Transforms/Scalar/CodeGenPrepare.cpp Message-ID: <20110518145756.78CF02A6C12C@llvm.org> Author: baldrick Date: Wed May 18 09:57:56 2011 New Revision: 131536 URL: http://llvm.org/viewvc/llvm-project?rev=131536&view=rev Log: Revert commit 131534 since it seems to have broken several buildbots. Original log entry: Refactor getActionType and getTypeToTransformTo ; place all of the 'decision' code in one place. Modified: llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=131536&r1=131535&r2=131536&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed May 18 09:57:56 2011 @@ -204,11 +204,62 @@ /// that indicates how instruction selection should deal with the type. uint8_t ValueTypeActions[MVT::LAST_VALUETYPE]; + LegalizeAction getExtendedTypeAction(EVT VT) const { + // Handle non-vector integers. + if (!VT.isVector()) { + assert(VT.isInteger() && "Unsupported extended type!"); + unsigned BitSize = VT.getSizeInBits(); + // First promote to a power-of-two size, then expand if necessary. + if (BitSize < 8 || !isPowerOf2_32(BitSize)) + return Promote; + return Expand; + } + + // Vectors with only one element are always scalarized. + if (VT.getVectorNumElements() == 1) + return Expand; + + // Vectors with a number of elements that is not a power of two are always + // widened, for example <3 x float> -> <4 x float>. + if (!VT.isPow2VectorType()) + return Promote; + + // Vectors with a crazy element type are always expanded, for example + // <4 x i2> is expanded into two vectors of type <2 x i2>. + if (!VT.getVectorElementType().isSimple()) + return Expand; + + // If this type is smaller than a legal vector type then widen it, + // otherwise expand it. E.g. <2 x float> -> <4 x float>. + MVT EltType = VT.getVectorElementType().getSimpleVT(); + unsigned NumElts = VT.getVectorNumElements(); + while (1) { + // Round up to the next power of 2. + NumElts = (unsigned)NextPowerOf2(NumElts); + + // If there is no simple vector type with this many elements then there + // cannot be a larger legal vector type. Note that this assumes that + // there are no skipped intermediate vector types in the simple types. + MVT LargerVector = MVT::getVectorVT(EltType, NumElts); + if (LargerVector == MVT()) + return Expand; + + // If this type is legal then widen the vector. + if (getTypeAction(LargerVector) == Legal) + return Promote; + } + } public: ValueTypeActionImpl() { std::fill(ValueTypeActions, array_endof(ValueTypeActions), 0); } + LegalizeAction getTypeAction(EVT VT) const { + if (!VT.isExtended()) + return getTypeAction(VT.getSimpleVT()); + return getExtendedTypeAction(VT); + } + LegalizeAction getTypeAction(MVT VT) const { return (LegalizeAction)ValueTypeActions[VT.SimpleTy]; } @@ -227,8 +278,8 @@ /// it is already legal (return 'Legal') or we need to promote it to a larger /// type (return 'Promote'), or we need to expand it into multiple registers /// of smaller integer type (return 'Expand'). 'Custom' is not an option. - LegalizeAction getTypeAction(LLVMContext &Context, EVT VT) const { - return getTypeConversion(Context, VT).first; + LegalizeAction getTypeAction(EVT VT) const { + return ValueTypeActions.getTypeAction(VT); } LegalizeAction getTypeAction(MVT VT) const { return ValueTypeActions.getTypeAction(VT); @@ -241,7 +292,38 @@ /// to get to the smaller register. For illegal floating point types, this /// returns the integer type to transform to. EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const { - return getTypeConversion(Context, VT).second; + if (VT.isSimple()) { + assert((unsigned)VT.getSimpleVT().SimpleTy < + array_lengthof(TransformToType)); + EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; + assert(getTypeAction(NVT) != Promote && + "Promote may not follow Expand or Promote"); + return NVT; + } + + if (VT.isVector()) { + EVT NVT = VT.getPow2VectorType(Context); + if (NVT == VT) { + // Vector length is a power of 2 - split to half the size. + unsigned NumElts = VT.getVectorNumElements(); + EVT EltVT = VT.getVectorElementType(); + return (NumElts == 1) ? + EltVT : EVT::getVectorVT(Context, EltVT, NumElts / 2); + } + // Promote to a power of two size, avoiding multi-step promotion. + return getTypeAction(NVT) == Promote ? + getTypeToTransformTo(Context, NVT) : NVT; + } else if (VT.isInteger()) { + EVT NVT = VT.getRoundIntegerType(Context); + if (NVT == VT) // Size is a power of two - expand to half the size. + return EVT::getIntegerVT(Context, VT.getSizeInBits() / 2); + + // Promote to a power of two size, avoiding multi-step promotion. + return getTypeAction(NVT) == Promote ? + getTypeToTransformTo(Context, NVT) : NVT; + } + assert(0 && "Unsupported extended type!"); + return MVT(MVT::Other); // Not reached } /// getTypeToExpandTo - For types supported by the target, this is an @@ -251,7 +333,7 @@ EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const { assert(!VT.isVector()); while (true) { - switch (getTypeAction(Context, VT)) { + switch (getTypeAction(VT)) { case Legal: return VT; case Expand: @@ -1732,73 +1814,6 @@ ValueTypeActionImpl ValueTypeActions; - typedef std::pair LegalizeKind; - - LegalizeKind - getTypeConversion(LLVMContext &Context, EVT VT) const { - // If this is a simple type, use the ComputeRegisterProp mechanism. - if (VT.isSimple()) { - assert((unsigned)VT.getSimpleVT().SimpleTy < - array_lengthof(TransformToType)); - EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; - LegalizeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT()); - if (NVT.isSimple() && LA != Legal) - assert(ValueTypeActions.getTypeAction(NVT.getSimpleVT()) != Promote && - "Promote may not follow Expand or Promote"); - return LegalizeKind(LA, NVT); - } - - // Handle Extended Scalar Types. - if (!VT.isVector()) { - assert(VT.isInteger() && "Float types must be simple"); - unsigned BitSize = VT.getSizeInBits(); - // First promote to a power-of-two size, then expand if necessary. - if (BitSize < 8 || !isPowerOf2_32(BitSize)) - return LegalizeKind(Promote, VT.getRoundIntegerType(Context)); - - return LegalizeKind(Expand, - EVT::getIntegerVT(Context, VT.getSizeInBits()/2)); - } - - // Handle vector types. - unsigned NumElts = VT.getVectorNumElements(); - EVT EltVT = VT.getVectorElementType(); - - // Vectors with only one element are always scalarized. - if (NumElts == 1) - return LegalizeKind(Expand, EltVT); - - // Try to widen the vector until a legal type is found. - // If there is no wider legal type, split the vector. - while (1) { - // Round up to the next power of 2. - NumElts = (unsigned)NextPowerOf2(NumElts); - - // If there is no simple vector type with this many elements then there - // cannot be a larger legal vector type. Note that this assumes that - // there are no skipped intermediate vector types in the simple types. - MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); - if (LargerVector == MVT()) break; - - // If this type is legal then widen the vector. - if (ValueTypeActions.getTypeAction(LargerVector) == Legal) - return LegalizeKind(Promote, LargerVector); - } - - // Widen odd vectors to next power of two. - if (!VT.isPow2VectorType()) { - EVT NVT = VT.getPow2VectorType(Context); - return LegalizeKind(Promote, NVT); - } - - // Vectors with illegal element types are expanded. - EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2); - return LegalizeKind(Expand, NVT); - - assert(false && "Unable to handle this kind of vector type"); - return LegalizeKind(Legal, VT); - } - std::vector > AvailableRegClasses; /// TargetDAGCombineArray - Targets can specify ISD nodes that they would Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=131536&r1=131535&r2=131536&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed May 18 09:57:56 2011 @@ -91,7 +91,7 @@ /// it is already legal or we need to expand it into multiple registers of /// smaller integer type, or we need to promote it to a larger type. LegalizeAction getTypeAction(EVT VT) const { - return (LegalizeAction)TLI.getTypeAction(*DAG.getContext(), VT); + return (LegalizeAction)ValueTypeActions.getTypeAction(VT); } /// isTypeLegal - Return true if this type is legal on this target. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=131536&r1=131535&r2=131536&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed May 18 09:57:56 2011 @@ -75,7 +75,7 @@ /// getTypeAction - Return how we should legalize values of this type. LegalizeAction getTypeAction(EVT VT) const { - switch (TLI.getTypeAction(*DAG.getContext(), VT)) { + switch (ValueTypeActions.getTypeAction(VT)) { default: assert(false && "Unknown legalize action!"); case TargetLowering::Legal: @@ -108,7 +108,7 @@ /// isTypeLegal - Return true if this type is legal on this target. bool isTypeLegal(EVT VT) const { - return TLI.getTypeAction(*DAG.getContext(), VT) == TargetLowering::Legal; + return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal; } /// IgnoreNodeResults - Pretend all of this node's results are legal. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=131536&r1=131535&r2=131536&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed May 18 09:57:56 2011 @@ -892,7 +892,7 @@ // If there is a wider vector type with the same element type as this one, // we should widen to that legal vector type. This handles things like // <2 x float> -> <4 x float>. - if (NumElts != 1 && getTypeAction(Context, VT) == Promote) { + if (NumElts != 1 && getTypeAction(VT) == Promote) { RegisterVT = getTypeToTransformTo(Context, VT); if (isTypeLegal(RegisterVT)) { IntermediateVT = RegisterVT; Modified: llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp?rev=131536&r1=131535&r2=131536&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/CodeGenPrepare.cpp Wed May 18 09:57:56 2011 @@ -371,9 +371,9 @@ // If these values will be promoted, find out what they will be promoted // to. This helps us consider truncates on PPC as noop copies when they // are. - if (TLI.getTypeAction(CI->getContext(), SrcVT) == TargetLowering::Promote) + if (TLI.getTypeAction(SrcVT) == TargetLowering::Promote) SrcVT = TLI.getTypeToTransformTo(CI->getContext(), SrcVT); - if (TLI.getTypeAction(CI->getContext(), DstVT) == TargetLowering::Promote) + if (TLI.getTypeAction(DstVT) == TargetLowering::Promote) DstVT = TLI.getTypeToTransformTo(CI->getContext(), DstVT); // If, after promotion, these are the same types, this is a noop copy. From baldrick at free.fr Wed May 18 10:03:59 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 18 May 2011 17:03:59 +0200 Subject: [llvm-commits] [llvm] r131534 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/LegalizeDAG.cpp lib/CodeGen/SelectionDAG/LegalizeTypes.h lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Transforms/Scalar/CodeGenPrepare.cpp In-Reply-To: <4DD3BE2D.70006@free.fr> References: <20110518122638.E97FA2A6C12C@llvm.org> <4DD3BE2D.70006@free.fr> Message-ID: <4DD3DFDF.9080506@free.fr> Hi Nadav, I reverted your commit because it broke several buildbots. Ciao, Duncan. From justin.holewinski at gmail.com Wed May 18 10:42:23 2011 From: justin.holewinski at gmail.com (Justin Holewinski) Date: Wed, 18 May 2011 15:42:23 -0000 Subject: [llvm-commits] [llvm] r131537 - in /llvm/trunk: lib/Target/PTX/PTX.td lib/Target/PTX/PTXInstrInfo.td lib/Target/PTX/PTXSubtarget.cpp lib/Target/PTX/PTXSubtarget.h test/CodeGen/PTX/mad-disabling.ll Message-ID: <20110518154223.C1BD92A6C12C@llvm.org> Author: jholewinski Date: Wed May 18 10:42:23 2011 New Revision: 131537 URL: http://llvm.org/viewvc/llvm-project?rev=131537&view=rev Log: PTX: add flag to disable mad/fma selection Patch by Dan Bailey Added: llvm/trunk/test/CodeGen/PTX/mad-disabling.ll Modified: llvm/trunk/lib/Target/PTX/PTX.td llvm/trunk/lib/Target/PTX/PTXInstrInfo.td llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp llvm/trunk/lib/Target/PTX/PTXSubtarget.h Modified: llvm/trunk/lib/Target/PTX/PTX.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.td?rev=131537&r1=131536&r2=131537&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTX.td (original) +++ llvm/trunk/lib/Target/PTX/PTX.td Wed May 18 10:42:23 2011 @@ -24,6 +24,9 @@ def FeatureDouble : SubtargetFeature<"double", "SupportsDouble", "true", "Do not demote .f64 to .f32">; +def FeatureNoFMA : SubtargetFeature<"no-fma","SupportsFMA", "false", + "Disable Fused-Multiply Add">; + //===- PTX Version --------------------------------------------------------===// def FeaturePTX20 : SubtargetFeature<"ptx20", "PTXVersion", "PTX_VERSION_2_0", Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=131537&r1=131536&r2=131537&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Wed May 18 10:42:23 2011 @@ -39,6 +39,10 @@ def SupportsPTX23 : Predicate<"getSubtarget().supportsPTX23()">; def DoesNotSupportPTX23 : Predicate<"!getSubtarget().supportsPTX23()">; +// Fused-Multiply Add +def SupportsFMA : Predicate<"getSubtarget().supportsFMA()">; +def DoesNotSupportFMA : Predicate<"!getSubtarget().supportsFMA()">; + //===----------------------------------------------------------------------===// // Instruction Pattern Stuff //===----------------------------------------------------------------------===// @@ -629,8 +633,8 @@ // In the short term, mad is supported on all PTX versions and we use a // default rounding mode no matter what shader model or PTX version. // TODO: Allow the rounding mode to be selectable through llc. -defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>, Requires<[SupportsSM13]>; -defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>, Requires<[DoesNotSupportSM13]>; +defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>, Requires<[SupportsSM13, SupportsFMA]>; +defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>, Requires<[DoesNotSupportSM13, SupportsFMA]>; ///===- Floating-Point Intrinsic Instructions -----------------------------===// @@ -667,6 +671,8 @@ ///===- Comparison and Selection Instructions -----------------------------===// +// .setp + // Compare u16 defm SETPEQu16 : PTX_SETP_I; Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=131537&r1=131536&r2=131537&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Wed May 18 10:42:23 2011 @@ -21,7 +21,8 @@ : PTXShaderModel(PTX_SM_1_0), PTXVersion(PTX_VERSION_2_0), SupportsDouble(false), - Is64Bit(is64Bit) { + SupportsFMA(true), + Is64Bit(is64Bit) { std::string TARGET = "generic"; ParseSubtargetFeatures(FS, TARGET); } Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.h?rev=131537&r1=131536&r2=131537&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSubtarget.h (original) +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.h Wed May 18 10:42:23 2011 @@ -49,7 +49,10 @@ // The native .f64 type is supported on the hardware. bool SupportsDouble; - + + // Support the fused-multiply add (FMA) and multiply-add (MAD) instructions + bool SupportsFMA; + // Use .u64 instead of .u32 for addresses. bool Is64Bit; @@ -64,6 +67,8 @@ bool is64Bit() const { return Is64Bit; } + bool supportsFMA() const { return SupportsFMA; } + bool supportsSM13() const { return PTXShaderModel >= PTX_SM_1_3; } bool supportsSM20() const { return PTXShaderModel >= PTX_SM_2_0; } Added: llvm/trunk/test/CodeGen/PTX/mad-disabling.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mad-disabling.ll?rev=131537&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PTX/mad-disabling.ll (added) +++ llvm/trunk/test/CodeGen/PTX/mad-disabling.ll Wed May 18 10:42:23 2011 @@ -0,0 +1,16 @@ +; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20 | grep "mad" +; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20,+no-fma | grep -v "mad" + +define ptx_device float @test_mul_add_f(float %x, float %y, float %z) { +entry: + %a = fmul float %x, %y + %b = fadd float %a, %z + ret float %b +} + +define ptx_device double @test_mul_add_d(double %x, double %y, double %z) { +entry: + %a = fmul double %x, %y + %b = fadd double %a, %z + ret double %b +} From stuart at apple.com Wed May 18 10:54:26 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 18 May 2011 15:54:26 -0000 Subject: [llvm-commits] [llvm] r131538 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Message-ID: <20110518155426.628E92A6C12C@llvm.org> Author: stuart Date: Wed May 18 10:54:26 2011 New Revision: 131538 URL: http://llvm.org/viewvc/llvm-project?rev=131538&view=rev Log: Fix inelegant initialization. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=131538&r1=131537&r2=131538&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Wed May 18 10:54:26 2011 @@ -598,8 +598,7 @@ unsigned VWidth = cast(II->getArgOperand(0)->getType())->getNumElements(); unsigned LowHalfElts = VWidth / 2; - APInt InputDemandedElts(VWidth, 0); - InputDemandedElts = InputDemandedElts.getBitsSet(VWidth, 0, LowHalfElts); + APInt InputDemandedElts(APInt::getBitsSet(VWidth, 0, LowHalfElts)); APInt UndefElts(VWidth, 0); if (Value *TmpV = SimplifyDemandedVectorElts(II->getArgOperand(0), InputDemandedElts, From dpatel at apple.com Wed May 18 11:38:30 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 09:38:30 -0700 Subject: [llvm-commits] [llvm] r131516 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/InstCombine/InstructionCombining.cpp test/Transforms/InstCombine/call.ll In-Reply-To: <92FB380D-70A0-44A2-9998-0755F7EBC775@apple.com> References: <20110518012827.9FAAB2A6C12C@llvm.org> <92FB380D-70A0-44A2-9998-0755F7EBC775@apple.com> Message-ID: On May 17, 2011, at 9:35 PM, Chris Lattner wrote: > Incidentally, Devang, we really shouldn't have to sprinkle setDebugLoc() through to a zillion different other transformations. Maybe they should start migrating to IRBuilder. I agree. Usually, there is a balance, and I know I crossed tipping point for SimplifyCFG yesterday. - Devang From stuart at apple.com Wed May 18 12:02:04 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 18 May 2011 17:02:04 -0000 Subject: [llvm-commits] [llvm] r131539 - in /llvm/trunk/test/CodeGen/X86: 2011-05-17-pmovzxwd.ll vec_shuffle-36.ll Message-ID: <20110518170204.3E9F52A6C12C@llvm.org> Author: stuart Date: Wed May 18 12:02:04 2011 New Revision: 131539 URL: http://llvm.org/viewvc/llvm-project?rev=131539&view=rev Log: Merge pmovzx test case into existing file. Removed: llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll Removed: llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll?rev=131538&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll (original) +++ llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll (removed) @@ -1,15 +0,0 @@ -; RUN: opt -instcombine -S < %s | FileCheck %s -; - -define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind { -entry: - %tmp = load <4 x i16>* %src - %tmp1 = load <8 x i16>* %foo -; CHECK: shufflevector - %tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> -; CHECK-NOT: shufflevector - %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> - %0 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3) - ret <4 x i32> %0 -} -declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll?rev=131539&r1=131538&r2=131539&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll Wed May 18 12:02:04 2011 @@ -1,4 +1,5 @@ ; RUN: llc < %s -march=x86-64 -mattr=sse41 | FileCheck %s +; RUN: opt -std-compile-opts < %s | llc -march=x86-64 -mattr=sse41 | FileCheck --check-prefix=CHECK_OPT_LLC %s define <8 x i16> @shuf6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { ; CHECK: pshufb @@ -14,3 +15,21 @@ %tmp10 = shufflevector <8 x i16> %t0, <8 x i16> undef, <8 x i32> < i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 undef, i32 undef > ret <8 x i16> %tmp10 } + + +; +define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind { +entry: +; CHECK_OPT_LLC: call{{.*nothing}} + call void @nothing() + %tmp = load <4 x i16>* %src + %tmp1 = load <8 x i16>* %foo +; pmovzxwd ignores the upper 64-bits of its input; everything between the call and pmovzxwd should be removed. + %tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> +; CHECK_OPT_LLC-NEXT: pmovzxwd + %0 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3) + ret <4 x i32> %0 +} +declare void @nothing() nounwind +declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone From stuart at apple.com Wed May 18 12:07:34 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 18 May 2011 10:07:34 -0700 Subject: [llvm-commits] [llvm] r131493 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp test/CodeGen/X86/2011-05-17-pmovzxwd.ll In-Reply-To: <6CB7DD3F-FE71-479F-A78F-93138957D8EC@apple.com> References: <20110517221331.910192A6C12C@llvm.org> <6CB7DD3F-FE71-479F-A78F-93138957D8EC@apple.com> Message-ID: On May 17, 2011, at 9:33 PM, Chris Lattner wrote: > > On May 17, 2011, at 3:13 PM, Stuart Hastings wrote: > >> Author: stuart >> Date: Tue May 17 17:13:31 2011 >> New Revision: 131493 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=131493&view=rev >> Log: >> X86 pmovsx/pmovzx ignore the upper half of their inputs. >> rdar://problem/6945110 > > Hi Stuart, > >> + case Intrinsic::x86_sse41_pmovzxdq: { >> + unsigned VWidth = >> + cast(II->getArgOperand(0)->getType())->getNumElements(); >> + unsigned LowHalfElts = VWidth / 2; >> + APInt InputDemandedElts(VWidth, 0); >> + InputDemandedElts = InputDemandedElts.getBitsSet(VWidth, 0, LowHalfElts); > > getBitsSet is a static method. Please do this instead: > > APInt InputDemandedElts(APInt::getBitsSet(VWidth, 0, LowHalfElts)); Done in 131538. >> +++ llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll Tue May 17 17:13:31 2011 >> @@ -0,0 +1,15 @@ >> +; RUN: opt -instcombine -S < %s | FileCheck %s >> +; >> + >> +define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind { >> +entry: >> + %tmp = load <4 x i16>* %src >> + %tmp1 = load <8 x i16>* %foo >> +; CHECK: shufflevector >> + %tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> >> +; CHECK-NOT: shufflevector >> + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> >> + %0 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3) >> + ret <4 x i32> %0 >> +} >> +declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone > > Please make the CHECK lines more specific so that it is more clear what you're doing here, add a comment explaining what is going on (to the test) > and merge the test into an extant .ll file. Merged into vec_shuffle-36.ll in 131539. > Thanks, Thanks for the review, stuart From grosbach at apple.com Wed May 18 12:12:37 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 18 May 2011 10:12:37 -0700 Subject: [llvm-commits] [llvm] r131502 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp In-Reply-To: <20110517230210.9555E2A6C12C@llvm.org> References: <20110517230210.9555E2A6C12C@llvm.org> Message-ID: <9CC65569-767F-4797-AEC3-2492E3800A0D@apple.com> Hey Eli, There's some buildbot fallout that looks like it may be related to this. ( http://google1.osuosl.org:8011/builders/llvm-gcc-native-mingw32-win7/builds/1933) At first impression, the tests may just need updated to deal with the improved handling. Can you have a look? -Jim On May 17, 2011, at 4:02 PM, Eli Friedman wrote: > Author: efriedma > Date: Tue May 17 18:02:10 2011 > New Revision: 131502 > > URL: http://llvm.org/viewvc/llvm-project?rev=131502&view=rev > Log: > Make fast-isel miss counting in -stats and -fast-isel-verbose take terminators into account; since there are many fewer isel misses with recent changes, misses caused by terminators are more significant. > > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=131502&r1=131501&r2=131502&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue May 17 18:02:10 2011 > @@ -972,9 +972,14 @@ > continue; > } > > - // Otherwise, give up on FastISel for the rest of the block. > - // For now, be a little lenient about non-branch terminators. > - if (!isa(Inst) || isa(Inst)) { > + if (isa(Inst) && !isa(Inst)) { > + // Don't abort, and use a different message for terminator misses. > + ++NumFastIselFailures; > + if (EnableFastISelVerbose || EnableFastISelAbort) { > + dbgs() << "FastISel missed terminator: "; > + Inst->dump(); > + } > + } else { > ++NumFastIselFailures; > if (EnableFastISelVerbose || EnableFastISelAbort) { > dbgs() << "FastISel miss: "; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From eli.friedman at gmail.com Wed May 18 12:16:37 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 17:16:37 -0000 Subject: [llvm-commits] [llvm] r131540 - in /llvm/trunk/test/CodeGen/X86: fast-isel-fneg.ll fast-isel.ll Message-ID: <20110518171637.4817F2A6C12C@llvm.org> Author: efriedma Date: Wed May 18 12:16:37 2011 New Revision: 131540 URL: http://llvm.org/viewvc/llvm-project?rev=131540&view=rev Log: Force a triple on a couple of tests; we don't support fast-isel of ret on Win64. Modified: llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll llvm/trunk/test/CodeGen/X86/fast-isel.ll Modified: llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll?rev=131540&r1=131539&r2=131540&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel-fneg.ll Wed May 18 12:16:37 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86-64 | FileCheck %s +; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 | FileCheck %s ; RUN: llc < %s -fast-isel -march=x86 -mattr=+sse2 | grep xor | count 2 ; CHECK: doo: Modified: llvm/trunk/test/CodeGen/X86/fast-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fast-isel.ll?rev=131540&r1=131539&r2=131540&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fast-isel.ll (original) +++ llvm/trunk/test/CodeGen/X86/fast-isel.ll Wed May 18 12:16:37 2011 @@ -1,5 +1,5 @@ ; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86 -mattr=sse2 -; RUN: llc < %s -fast-isel -fast-isel-abort -march=x86-64 +; RUN: llc < %s -fast-isel -fast-isel-abort -mtriple=x86_64-apple-darwin10 ; This tests very minimal fast-isel functionality. From eli.friedman at gmail.com Wed May 18 12:22:21 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 10:22:21 -0700 Subject: [llvm-commits] [llvm] r131502 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp In-Reply-To: <9CC65569-767F-4797-AEC3-2492E3800A0D@apple.com> References: <20110517230210.9555E2A6C12C@llvm.org> <9CC65569-767F-4797-AEC3-2492E3800A0D@apple.com> Message-ID: On Wed, May 18, 2011 at 10:12 AM, Jim Grosbach wrote: > Hey Eli, > > There's some buildbot fallout that looks like it may be related to this. ( http://google1.osuosl.org:8011/builders/llvm-gcc-native-mingw32-win7/builds/1933) > > At first impression, the tests may just need updated to deal with the improved handling. Can you have a look? Thanks; r131540 -Eli From dpatel at apple.com Wed May 18 12:26:46 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 17:26:46 -0000 Subject: [llvm-commits] [llvm] r131541 - in /llvm/trunk/lib: Transforms/Utils/Local.cpp VMCore/DebugInfoProbe.cpp Message-ID: <20110518172646.A62E42A6C12C@llvm.org> Author: dpatel Date: Wed May 18 12:26:46 2011 New Revision: 131541 URL: http://llvm.org/viewvc/llvm-project?rev=131541&view=rev Log: Use IRBuiler while constant folding terminator. Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp llvm/trunk/lib/VMCore/DebugInfoProbe.cpp Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=131541&r1=131540&r2=131541&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Wed May 18 12:26:46 2011 @@ -34,6 +34,7 @@ #include "llvm/Support/CFG.h" #include "llvm/Support/Debug.h" #include "llvm/Support/GetElementPtrTypeIterator.h" +#include "llvm/SUpport/IRBuilder.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/ValueHandle.h" #include "llvm/Support/raw_ostream.h" @@ -49,6 +50,7 @@ // bool llvm::ConstantFoldTerminator(BasicBlock *BB) { TerminatorInst *T = BB->getTerminator(); + IRBuilder<> Builder(T); // Branch - See if we are conditional jumping on constant if (BranchInst *BI = dyn_cast(T)) { @@ -71,7 +73,7 @@ OldDest->removePredecessor(BB); // Replace the conditional branch with an unconditional one. - BranchInst::Create(Destination, BI); + Builder.CreateBr(Destination); BI->eraseFromParent(); return true; } @@ -86,7 +88,7 @@ Dest1->removePredecessor(BI->getParent()); // Replace the conditional branch with an unconditional one. - BranchInst::Create(Dest1, BI); + Builder.CreateBr(Dest1); BI->eraseFromParent(); return true; } @@ -136,7 +138,7 @@ // now. if (TheOnlyDest) { // Insert the new branch. - BranchInst::Create(TheOnlyDest, SI); + Builder.CreateBr(TheOnlyDest); BasicBlock *BB = SI->getParent(); // Remove entries from PHI nodes which we no longer branch to... @@ -157,10 +159,11 @@ if (SI->getNumSuccessors() == 2) { // Otherwise, we can fold this switch into a conditional branch // instruction if it has only one non-default destination. - Value *Cond = new ICmpInst(SI, ICmpInst::ICMP_EQ, SI->getCondition(), - SI->getSuccessorValue(1), "cond"); + Value *Cond = Builder.CreateICmpEQ(SI->getCondition(), + SI->getSuccessorValue(1), "cond"); + // Insert the new branch. - BranchInst::Create(SI->getSuccessor(1), SI->getSuccessor(0), Cond, SI); + Builder.CreateCondBr(Cond, SI->getSuccessor(1), SI->getSuccessor(0)); // Delete the old switch. SI->eraseFromParent(); @@ -175,7 +178,7 @@ dyn_cast(IBI->getAddress()->stripPointerCasts())) { BasicBlock *TheOnlyDest = BA->getBasicBlock(); // Insert the new branch. - BranchInst::Create(TheOnlyDest, IBI); + Builder.CreateBr(TheOnlyDest); for (unsigned i = 0, e = IBI->getNumDestinations(); i != e; ++i) { if (IBI->getDestination(i) == TheOnlyDest) Modified: llvm/trunk/lib/VMCore/DebugInfoProbe.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/DebugInfoProbe.cpp?rev=131541&r1=131540&r2=131541&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/DebugInfoProbe.cpp (original) +++ llvm/trunk/lib/VMCore/DebugInfoProbe.cpp Wed May 18 12:26:46 2011 @@ -70,7 +70,7 @@ for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ++BI) { - if (BI->getDebugLoc().isUnknown()) + if (!isa(BI) && BI->getDebugLoc().isUnknown()) MissingDebugLoc.insert(BI); if (!isa(BI)) continue; Value *Addr = NULL; @@ -116,7 +116,7 @@ for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); BI != BE; ++BI) { - if (BI->getDebugLoc().isUnknown() && + if (!isa(BI) && BI->getDebugLoc().isUnknown() && MissingDebugLoc.count(BI) == 0) { ++NumDbgLineLost; DEBUG(dbgs() << "DebugInfoProbe (" << PassName << "): --- "); From eli.friedman at gmail.com Wed May 18 12:31:55 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 17:31:55 -0000 Subject: [llvm-commits] [llvm] r131542 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Message-ID: <20110518173156.019912A6C12C@llvm.org> Author: efriedma Date: Wed May 18 12:31:55 2011 New Revision: 131542 URL: http://llvm.org/viewvc/llvm-project?rev=131542&view=rev Log: Switch inst insertion in instcombine transform to IRBuilder. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=131542&r1=131541&r2=131542&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Wed May 18 12:31:55 2011 @@ -604,9 +604,7 @@ return BinaryOperator::CreateOr(CondVal, FalseVal); } // Change: A = select B, false, C --> A = and !B, C - Value *NotCond = - InsertNewInstBefore(BinaryOperator::CreateNot(CondVal, - "not."+CondVal->getName()), SI); + Value *NotCond = Builder->CreateNot(CondVal, "not."+CondVal->getName()); return BinaryOperator::CreateAnd(NotCond, FalseVal); } else if (ConstantInt *C = dyn_cast(FalseVal)) { if (C->getZExtValue() == false) { @@ -614,9 +612,7 @@ return BinaryOperator::CreateAnd(CondVal, TrueVal); } // Change: A = select B, C, true --> A = or !B, C - Value *NotCond = - InsertNewInstBefore(BinaryOperator::CreateNot(CondVal, - "not."+CondVal->getName()), SI); + Value *NotCond = Builder->CreateNot(CondVal, "not."+CondVal->getName()); return BinaryOperator::CreateOr(NotCond, TrueVal); } From matthewbg at google.com Wed May 18 12:37:10 2011 From: matthewbg at google.com (Matt Beaumont-Gay) Date: Wed, 18 May 2011 17:37:10 -0000 Subject: [llvm-commits] [llvm] r131543 - /llvm/trunk/lib/Transforms/Utils/Local.cpp Message-ID: <20110518173710.59F202A6C12C@llvm.org> Author: matthewbg Date: Wed May 18 12:37:10 2011 New Revision: 131543 URL: http://llvm.org/viewvc/llvm-project?rev=131543&view=rev Log: fix typo Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=131543&r1=131542&r2=131543&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Wed May 18 12:37:10 2011 @@ -34,7 +34,7 @@ #include "llvm/Support/CFG.h" #include "llvm/Support/Debug.h" #include "llvm/Support/GetElementPtrTypeIterator.h" -#include "llvm/SUpport/IRBuilder.h" +#include "llvm/Support/IRBuilder.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/ValueHandle.h" #include "llvm/Support/raw_ostream.h" From dpatel at apple.com Wed May 18 12:48:31 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 10:48:31 -0700 Subject: [llvm-commits] [llvm] r131543 - /llvm/trunk/lib/Transforms/Utils/Local.cpp In-Reply-To: <20110518173710.59F202A6C12C@llvm.org> References: <20110518173710.59F202A6C12C@llvm.org> Message-ID: <15C556C2-E361-4405-B251-92D8743D3BAF@apple.com> On May 18, 2011, at 10:37 AM, Matt Beaumont-Gay wrote: > Author: matthewbg > Date: Wed May 18 12:37:10 2011 > New Revision: 131543 > > URL: http://llvm.org/viewvc/llvm-project?rev=131543&view=rev > Log: > fix typo Thanks! - Devang > > Modified: > llvm/trunk/lib/Transforms/Utils/Local.cpp > > Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=131543&r1=131542&r2=131543&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Wed May 18 12:37:10 2011 > @@ -34,7 +34,7 @@ > #include "llvm/Support/CFG.h" > #include "llvm/Support/Debug.h" > #include "llvm/Support/GetElementPtrTypeIterator.h" > -#include "llvm/SUpport/IRBuilder.h" > +#include "llvm/Support/IRBuilder.h" > #include "llvm/Support/MathExtras.h" > #include "llvm/Support/ValueHandle.h" > #include "llvm/Support/raw_ostream.h" > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From eli.friedman at gmail.com Wed May 18 12:58:37 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 17:58:37 -0000 Subject: [llvm-commits] [llvm] r131544 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Message-ID: <20110518175837.D37BB2A6C12C@llvm.org> Author: efriedma Date: Wed May 18 12:58:37 2011 New Revision: 131544 URL: http://llvm.org/viewvc/llvm-project?rev=131544&view=rev Log: Switch more inst insertion in instcombine to IRBuilder. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=131544&r1=131543&r2=131544&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Wed May 18 12:58:37 2011 @@ -751,27 +751,20 @@ // So at this point we know we have (Y -> OtherAddOp): // select C, (add X, Y), (sub X, Z) Value *NegVal; // Compute -Z - if (Constant *C = dyn_cast(SubOp->getOperand(1))) { - NegVal = ConstantExpr::getNeg(C); - } else if (SI.getType()->isFloatingPointTy()) { - NegVal = InsertNewInstBefore( - BinaryOperator::CreateFNeg(SubOp->getOperand(1), - "tmp"), SI); + if (SI.getType()->isFloatingPointTy()) { + NegVal = Builder->CreateFNeg(SubOp->getOperand(1)); } else { - NegVal = InsertNewInstBefore( - BinaryOperator::CreateNeg(SubOp->getOperand(1), - "tmp"), SI); + NegVal = Builder->CreateNeg(SubOp->getOperand(1)); } Value *NewTrueOp = OtherAddOp; Value *NewFalseOp = NegVal; if (AddOp != TI) std::swap(NewTrueOp, NewFalseOp); - Instruction *NewSel = - SelectInst::Create(CondVal, NewTrueOp, - NewFalseOp, SI.getName() + ".p"); + Value *NewSel = + Builder->CreateSelect(CondVal, NewTrueOp, + NewFalseOp, SI.getName() + ".p"); - NewSel = InsertNewInstBefore(NewSel, SI); if (SI.getType()->isFloatingPointTy()) return BinaryOperator::CreateFAdd(SubOp->getOperand(0), NewSel); else From dpatel at apple.com Wed May 18 13:01:27 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 18:01:27 -0000 Subject: [llvm-commits] [llvm] r131545 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110518180127.380D42A6C12C@llvm.org> Author: dpatel Date: Wed May 18 13:01:27 2011 New Revision: 131545 URL: http://llvm.org/viewvc/llvm-project?rev=131545&view=rev Log: Set up IRBuilder for use during simplification. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131545&r1=131544&r2=131545&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 13:01:27 2011 @@ -32,6 +32,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/ConstantRange.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/IRBuilder.h" #include "llvm/Support/raw_ostream.h" #include #include @@ -2638,6 +2639,8 @@ if (MergeBlockIntoPredecessor(BB)) return true; + IRBuilder<> Builder(BB); + // If there is a trivial two-entry PHI node in this basic block, and we can // eliminate it, do so now. if (PHINode *PN = dyn_cast(BB->begin())) From eli.friedman at gmail.com Wed May 18 13:10:28 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 18:10:28 -0000 Subject: [llvm-commits] [llvm] r131547 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Message-ID: <20110518181028.B70532A6C12C@llvm.org> Author: efriedma Date: Wed May 18 13:10:28 2011 New Revision: 131547 URL: http://llvm.org/viewvc/llvm-project?rev=131547&view=rev Log: Switch more inst insertion in instcombine to IRBuilder. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=131547&r1=131546&r2=131547&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Wed May 18 13:10:28 2011 @@ -133,9 +133,8 @@ } // Fold this by inserting a select from the input values. - SelectInst *NewSI = SelectInst::Create(SI.getCondition(), TI->getOperand(0), - FI->getOperand(0), SI.getName()+".v"); - InsertNewInstBefore(NewSI, SI); + Value *NewSI = Builder->CreateSelect(SI.getCondition(), TI->getOperand(0), + FI->getOperand(0), SI.getName()+".v"); return CastInst::Create(Instruction::CastOps(TI->getOpcode()), NewSI, TI->getType()); } @@ -174,9 +173,8 @@ } // If we reach here, they do have operations in common. - SelectInst *NewSI = SelectInst::Create(SI.getCondition(), OtherOpT, - OtherOpF, SI.getName()+".v"); - InsertNewInstBefore(NewSI, SI); + Value *NewSI = Builder->CreateSelect(SI.getCondition(), OtherOpT, + OtherOpF, SI.getName()+".v"); if (BinaryOperator *BO = dyn_cast(TI)) { if (MatchIsOpZero) @@ -224,8 +222,7 @@ // Avoid creating select between 2 constants unless it's selecting // between 0, 1 and -1. if (!isa(OOp) || isSelect01(C, cast(OOp))) { - Instruction *NewSel = SelectInst::Create(SI.getCondition(), OOp, C); - InsertNewInstBefore(NewSel, SI); + Value *NewSel = Builder->CreateSelect(SI.getCondition(), OOp, C); NewSel->takeName(TVI); BinaryOperator *TVI_BO = cast(TVI); BinaryOperator *BO = BinaryOperator::Create(TVI_BO->getOpcode(), @@ -260,8 +257,7 @@ // Avoid creating select between 2 constants unless it's selecting // between 0, 1 and -1. if (!isa(OOp) || isSelect01(C, cast(OOp))) { - Instruction *NewSel = SelectInst::Create(SI.getCondition(), C, OOp); - InsertNewInstBefore(NewSel, SI); + Value *NewSel = Builder->CreateSelect(SI.getCondition(), C, OOp); NewSel->takeName(FVI); BinaryOperator *FVI_BO = cast(FVI); BinaryOperator *BO = BinaryOperator::Create(FVI_BO->getOpcode(), From dpatel at apple.com Wed May 18 13:16:44 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 18:16:44 -0000 Subject: [llvm-commits] [llvm] r131548 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110518181644.6C6CA2A6C12C@llvm.org> Author: dpatel Date: Wed May 18 13:16:44 2011 New Revision: 131548 URL: http://llvm.org/viewvc/llvm-project?rev=131548&view=rev Log: Use IRBuilder while folding two entry PHINode. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131548&r1=131547&r2=131548&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 13:16:44 2011 @@ -1228,7 +1228,8 @@ /// FoldTwoEntryPHINode - Given a BB that starts with the specified two-entry /// PHI node, see if we can eliminate it. -static bool FoldTwoEntryPHINode(PHINode *PN, const TargetData *TD) { +static bool FoldTwoEntryPHINode(PHINode *PN, const TargetData *TD, + IRBuilder<> &Builder) { // Ok, this is a two entry PHI node. Check to see if this is a simple "if // statement", which has a very simple dominance structure. Basically, we // are trying to find the condition that is being branched on, which @@ -1327,6 +1328,7 @@ // If we can still promote the PHI nodes after this gauntlet of tests, // do all of the PHI's now. Instruction *InsertPt = DomBlock->getTerminator(); + Builder.SetInsertPoint(InsertPt); // Move all 'aggressive' instructions, which are defined in the // conditional parts of the if's up to the dominating block. @@ -1344,8 +1346,8 @@ Value *TrueVal = PN->getIncomingValue(PN->getIncomingBlock(0) == IfFalse); Value *FalseVal = PN->getIncomingValue(PN->getIncomingBlock(0) == IfTrue); - SelectInst *NV = SelectInst::Create(IfCond, TrueVal, FalseVal, "", InsertPt); - NV->setDebugLoc(InsertPt->getDebugLoc()); + SelectInst *NV = + cast(Builder.CreateSelect(IfCond, TrueVal, FalseVal, "")); PN->replaceAllUsesWith(NV); NV->takeName(PN); PN->eraseFromParent(); @@ -1355,8 +1357,8 @@ // has been flattened. Change DomBlock to jump directly to our new block to // avoid other simplifycfg's kicking in on the diamond. TerminatorInst *OldTI = DomBlock->getTerminator(); - BranchInst *NewBI = BranchInst::Create(BB, OldTI); - NewBI->setDebugLoc(OldTI->getDebugLoc()); + Builder.SetInsertPoint(OldTI); + Builder.CreateBr(BB); OldTI->eraseFromParent(); return true; } @@ -2645,7 +2647,7 @@ // eliminate it, do so now. if (PHINode *PN = dyn_cast(BB->begin())) if (PN->getNumIncomingValues() == 2) - Changed |= FoldTwoEntryPHINode(PN, TD); + Changed |= FoldTwoEntryPHINode(PN, TD, Builder); if (BranchInst *BI = dyn_cast(BB->getTerminator())) { if (BI->isUnconditional()) { From dpatel at apple.com Wed May 18 13:28:48 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 18:28:48 -0000 Subject: [llvm-commits] [llvm] r131551 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110518182849.043FD2A6C12C@llvm.org> Author: dpatel Date: Wed May 18 13:28:48 2011 New Revision: 131551 URL: http://llvm.org/viewvc/llvm-project?rev=131551&view=rev Log: Use IRBuilder while simplifying unconditional branch. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131551&r1=131550&r2=131551&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 13:28:48 2011 @@ -65,7 +65,7 @@ bool SimplifyUnreachable(UnreachableInst *UI); bool SimplifySwitch(SwitchInst *SI); bool SimplifyIndirectBr(IndirectBrInst *IBI); - bool SimplifyUncondBranch(BranchInst *BI); + bool SimplifyUncondBranch(BranchInst *BI, IRBuilder <> &Builder); bool SimplifyCondBranch(BranchInst *BI); public: @@ -1923,8 +1923,10 @@ /// We prefer to split the edge to 'end' so that there is a true/false entry to /// the PHI, merging the third icmp into the switch. static bool TryToSimplifyUncondBranchWithICmpInIt(ICmpInst *ICI, - const TargetData *TD) { + const TargetData *TD, + IRBuilder<> &Builder) { BasicBlock *BB = ICI->getParent(); + // If the block has any PHIs in it or the icmp has multiple uses, it is too // complex. if (isa(BB->begin()) || !ICI->hasOneUse()) return false; @@ -2002,7 +2004,9 @@ SI->addCase(Cst, NewBB); // NewBB branches to the phi block, add the uncond branch and the phi entry. - BranchInst::Create(SuccBlock, NewBB); + Builder.SetInsertPoint(NewBB); + Builder.SetCurrentDebugLocation(SI->getDebugLoc()); + Builder.CreateBr(SuccBlock); PHIUse->addIncoming(NewCst, NewBB); return true; } @@ -2503,7 +2507,7 @@ return Changed; } -bool SimplifyCFGOpt::SimplifyUncondBranch(BranchInst *BI) { +bool SimplifyCFGOpt::SimplifyUncondBranch(BranchInst *BI, IRBuilder<> &Builder){ BasicBlock *BB = BI->getParent(); // If the Terminator is the only non-phi instruction, simplify the block. @@ -2518,7 +2522,8 @@ if (ICI->isEquality() && isa(ICI->getOperand(1))) { for (++I; isa(I); ++I) ; - if (I->isTerminator() && TryToSimplifyUncondBranchWithICmpInIt(ICI, TD)) + if (I->isTerminator() + && TryToSimplifyUncondBranchWithICmpInIt(ICI, TD, Builder)) return true; } @@ -2651,7 +2656,7 @@ if (BranchInst *BI = dyn_cast(BB->getTerminator())) { if (BI->isUnconditional()) { - if (SimplifyUncondBranch(BI)) return true; + if (SimplifyUncondBranch(BI, Builder)) return true; } else { if (SimplifyCondBranch(BI)) return true; } From mcrosier at apple.com Wed May 18 13:07:16 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 18 May 2011 18:07:16 -0000 Subject: [llvm-commits] [llvm] r131546 - /llvm/trunk/docs/TestingGuide.html Message-ID: <20110518180716.9B18D2A6C12C@llvm.org> Author: mcrosier Date: Wed May 18 13:07:16 2011 New Revision: 131546 URL: http://llvm.org/viewvc/llvm-project?rev=131546&view=rev Log: Correct typos in TestingGuide.html Modified: llvm/trunk/docs/TestingGuide.html Modified: llvm/trunk/docs/TestingGuide.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/TestingGuide.html?rev=131546&r1=131545&r2=131546&view=diff ============================================================================== --- llvm/trunk/docs/TestingGuide.html (original) +++ llvm/trunk/docs/TestingGuide.html Wed May 18 13:07:16 2011 @@ -365,8 +365,8 @@ obtained by using Tcl's glob command. Any directory that contains only directories does not need the dg.exp file.

-

The llvm-runtests function lookas at each file that is passed to - it and gathers any lines together that match "RUN:". This are the "RUN" lines +

The llvm-runtests function looks at each file that is passed to + it and gathers any lines together that match "RUN:". These are the "RUN" lines that specify how the test is to be run. So, each test script must contain RUN lines if it is to do anything. If there are no RUN lines, the llvm-runtests function will issue an error and the test will From dpatel at apple.com Wed May 18 13:43:31 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 18:43:31 -0000 Subject: [llvm-commits] [llvm] r131552 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110518184331.B91672A6C12C@llvm.org> Author: dpatel Date: Wed May 18 13:43:31 2011 New Revision: 131552 URL: http://llvm.org/viewvc/llvm-project?rev=131552&view=rev Log: Use IRBuilder while simplifying terminator. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131552&r1=131551&r2=131552&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 13:43:31 2011 @@ -1835,16 +1835,19 @@ Succ->removePredecessor(OldTerm->getParent()); } + IRBuilder<> Builder(OldTerm); + Builder.SetCurrentDebugLocation(OldTerm->getDebugLoc()); + // Insert an appropriate new terminator. if ((KeepEdge1 == 0) && (KeepEdge2 == 0)) { if (TrueBB == FalseBB) // We were only looking for one successor, and it was present. // Create an unconditional branch to it. - BranchInst::Create(TrueBB, OldTerm); + Builder.CreateBr(TrueBB); else // We found both of the successors we were looking for. // Create a conditional branch sharing the condition of the select. - BranchInst::Create(TrueBB, FalseBB, Cond, OldTerm); + Builder.CreateCondBr(Cond, TrueBB, FalseBB); } else if (KeepEdge1 && (KeepEdge2 || TrueBB == FalseBB)) { // Neither of the selected blocks were successors, so this // terminator must be unreachable. @@ -1855,10 +1858,10 @@ // the edge to the one that wasn't must be unreachable. if (KeepEdge1 == 0) // Only TrueBB was found. - BranchInst::Create(TrueBB, OldTerm); + Builder.CreateBr(TrueBB); else // Only FalseBB was found. - BranchInst::Create(FalseBB, OldTerm); + Builder.CreateBr(FalseBB); } EraseTerminatorInstAndDCECond(OldTerm); From evan.cheng at apple.com Wed May 18 13:47:27 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 18 May 2011 18:47:27 -0000 Subject: [llvm-commits] [llvm] r131553 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20110518184727.B7F132A6C12C@llvm.org> Author: evancheng Date: Wed May 18 13:47:27 2011 New Revision: 131553 URL: http://llvm.org/viewvc/llvm-project?rev=131553&view=rev Log: Fix an ARMTargetLowering::LowerSELECT bug: legalized result must have same type as input. Sorry test cases only trigger when dag combine is disabled. rdar://9449178 Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=131553&r1=131552&r2=131553&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed May 18 13:47:27 2011 @@ -2697,7 +2697,9 @@ SDValue ARMcc = Cond.getOperand(2); SDValue CCR = Cond.getOperand(3); SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); - return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); + return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), + DAG.getNode(ARMISD::CMOV, dl, VT, True, False, + ARMcc, CCR, Cmp)); } } } From evan.cheng at apple.com Wed May 18 13:59:17 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 18 May 2011 18:59:17 -0000 Subject: [llvm-commits] [llvm] r131555 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20110518185917.C44182A6C12C@llvm.org> Author: evancheng Date: Wed May 18 13:59:17 2011 New Revision: 131555 URL: http://llvm.org/viewvc/llvm-project?rev=131555&view=rev Log: Revise r131553. Just use the type of the input node and forgo the bitcast. rdar://9449159. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=131555&r1=131554&r2=131555&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed May 18 13:59:17 2011 @@ -2693,13 +2693,12 @@ } if (True.getNode() && False.getNode()) { - EVT VT = Cond.getValueType(); + EVT VT = Op.getValueType(); SDValue ARMcc = Cond.getOperand(2); SDValue CCR = Cond.getOperand(3); SDValue Cmp = duplicateCmp(Cond.getOperand(4), DAG); - return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), - DAG.getNode(ARMISD::CMOV, dl, VT, True, False, - ARMcc, CCR, Cmp)); + assert(True.getValueType() == VT); + return DAG.getNode(ARMISD::CMOV, dl, VT, True, False, ARMcc, CCR, Cmp); } } } From csdavec at swan.ac.uk Wed May 18 14:00:41 2011 From: csdavec at swan.ac.uk (David Chisnall) Date: Wed, 18 May 2011 19:00:41 -0000 Subject: [llvm-commits] [llvm] r131556 - in /llvm/trunk: include/llvm/DefaultPasses.h include/llvm/Support/StandardPasses.h lib/Support/StandardPasses.cpp Message-ID: <20110518190041.A1B5E2A6C12C@llvm.org> Author: theraven Date: Wed May 18 14:00:41 2011 New Revision: 131556 URL: http://llvm.org/viewvc/llvm-project?rev=131556&view=rev Log: Second pass at allowing plugins to modify default passes. This time without bonus inter-library dependencies. Added: llvm/trunk/include/llvm/DefaultPasses.h llvm/trunk/lib/Support/StandardPasses.cpp Modified: llvm/trunk/include/llvm/Support/StandardPasses.h Added: llvm/trunk/include/llvm/DefaultPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DefaultPasses.h?rev=131556&view=auto ============================================================================== --- llvm/trunk/include/llvm/DefaultPasses.h (added) +++ llvm/trunk/include/llvm/DefaultPasses.h Wed May 18 14:00:41 2011 @@ -0,0 +1,162 @@ +//===- llvm/DefaultPasses.h - Default Pass Support code --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// This file defines the infrastructure for registering the standard pass list. +// This defines sets of standard optimizations that plugins can modify and +// front ends can use. +//===----------------------------------------------------------------------===// + +#ifndef LLVM_DEFAULT_PASS_SUPPORT_H +#define LLVM_DEFAULT_PASS_SUPPORT_H + +namespace llvm { + +class PassManagerBase; + +/// Unique identifiers for the default standard passes. The addresses of +/// these symbols are used to uniquely identify passes from the default list. +namespace DefaultStandardPasses { +extern unsigned char AggressiveDCEID; +extern unsigned char ArgumentPromotionID; +extern unsigned char BasicAliasAnalysisID; +extern unsigned char CFGSimplificationID; +extern unsigned char ConstantMergeID; +extern unsigned char CorrelatedValuePropagationID; +extern unsigned char DeadArgEliminationID; +extern unsigned char DeadStoreEliminationID; +extern unsigned char DeadTypeEliminationID; +extern unsigned char EarlyCSEID; +extern unsigned char FunctionAttrsID; +extern unsigned char FunctionInliningID; +extern unsigned char GVNID; +extern unsigned char GlobalDCEID; +extern unsigned char GlobalOptimizerID; +extern unsigned char GlobalsModRefID; +extern unsigned char IPSCCPID; +extern unsigned char IndVarSimplifyID; +extern unsigned char InlinerPlaceholderID; +extern unsigned char InstructionCombiningID; +extern unsigned char JumpThreadingID; +extern unsigned char LICMID; +extern unsigned char LoopDeletionID; +extern unsigned char LoopIdiomID; +extern unsigned char LoopRotateID; +extern unsigned char LoopUnrollID; +extern unsigned char LoopUnswitchID; +extern unsigned char MemCpyOptID; +extern unsigned char PruneEHID; +extern unsigned char ReassociateID; +extern unsigned char SCCPID; +extern unsigned char ScalarReplAggregatesID; +extern unsigned char SimplifyLibCallsID; +extern unsigned char StripDeadPrototypesID; +extern unsigned char TailCallEliminationID; +extern unsigned char TypeBasedAliasAnalysisID; +} + +/// StandardPass - The class responsible for maintaining the lists of standard +class StandardPass { + friend class RegisterStandardPassLists; + public: + /// Predefined standard sets of passes + enum StandardSet { + AliasAnalysis, + Function, + Module, + LTO + }; + /// Flags to specify whether a pass should be enabled. Passes registered + /// with the standard sets may specify a minimum optimization level and one + /// or more flags that must be set when constructing the set for the pass to + /// be used. + enum OptimizationFlags { + /// Optimize for size was requested. + OptimizeSize = 1<<0, + /// Allow passes which may make global module changes. + UnitAtATime = 1<<1, + /// UnrollLoops - Allow loop unrolling. + UnrollLoops = 1<<2, + /// Allow library calls to be simplified. + SimplifyLibCalls = 1<<3, + /// Whether the module may have code using exceptions. + HaveExceptions = 1<<4, + // Run an inliner pass as part of this set. + RunInliner = 1<<5 + }; + enum OptimizationFlagComponents { + /// The low bits are used to store the optimization level. When requesting + /// passes, this should store the requested optimisation level. When + /// setting passes, this should set the minimum optimization level at which + /// the pass will run. + OptimizationLevelMask=0xf, + /// The maximum optimisation level at which the pass is run. + MaxOptimizationLevelMask=0xf0, + // Flags that must be set + RequiredFlagMask=0xff00, + // Flags that may not be set. + DisallowedFlagMask=0xff0000, + MaxOptimizationLevelShift=4, + RequiredFlagShift=8, + DisallowedFlagShift=16 + }; + /// Returns the optimisation level from a set of flags. + static unsigned OptimizationLevel(unsigned flags) { + return flags & OptimizationLevelMask ; }; + /// Returns the maximum optimization level for this set of flags + static unsigned MaxOptimizationLevel(unsigned flags) { + return (flags & MaxOptimizationLevelMask) >> 4; }; + /// Constructs a set of flags from the specified minimum and maximum + /// optimisation level + static unsigned OptimzationFlags(unsigned minLevel=0, unsigned maxLevel=0xf, + unsigned requiredFlags=0, unsigned disallowedFlags=0) { + return ((minLevel & OptimizationLevelMask) | + ((maxLevel<> RequiredFlagShift; }; + /// Returns the flags that must not be set for this to match + static unsigned DisallowedFlags(unsigned flags) { + return (flags & DisallowedFlagMask) >> DisallowedFlagShift; }; + /// Register a standard pass in the specified set. If flags is non-zero, + /// then the pass will only be returned when the specified flags are set. + template + class RegisterStandardPass { + public: + RegisterStandardPass(StandardSet set, unsigned char *runBefore=0, + unsigned flags=0, unsigned char *ID=0) { + // Use the pass's ID if one is not specified + RegisterDefaultPass(PassInfo::NormalCtor_t(callDefaultCtor), + ID ? ID : (unsigned char*)&passName::ID, runBefore, set, flags); + }; + }; + /// Adds the passes from the specified set to the provided pass manager + static void AddPassesFromSet(PassManagerBase *PM, + StandardSet set, + unsigned flags=0, + bool VerifyEach=false, + Pass *inliner=0); + private: + /// Registers the default passes. This is set by RegisterStandardPassLists + /// and is called lazily. + static void (*RegisterDefaultPasses)(void); + /// Creates the verifier pass that is inserted when a VerifyEach is passed to + /// AddPassesFromSet() + static Pass* (*CreateVerifierPass)(void); + /// Registers the pass + static void RegisterDefaultPass(PassInfo::NormalCtor_t constructor, + unsigned char *newPass, + unsigned char *oldPass, + StandardSet set, + unsigned flags=0); +}; + +} // namespace llvm + +#endif Modified: llvm/trunk/include/llvm/Support/StandardPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=131556&r1=131555&r2=131556&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) +++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed May 18 14:00:41 2011 @@ -20,6 +20,7 @@ #define LLVM_SUPPORT_STANDARDPASSES_H #include "llvm/PassManager.h" +#include "llvm/DefaultPasses.h" #include "llvm/Analysis/Passes.h" #include "llvm/Analysis/Verifier.h" #include "llvm/Transforms/Scalar.h" @@ -27,12 +28,273 @@ namespace llvm { + /// RegisterStandardPassLists solves a circular dependency problem. The + /// default list of passes has to live somewhere. It can't live in the core + /// modules, because these don't link to the libraries that actually define + /// the passes. It's in this header, so that a copy is created in every + /// library that requests the default set, while still allowing plugins to + /// register new passes without requiring them to link anything more than + /// VMCore. + class RegisterStandardPassLists { + public: + RegisterStandardPassLists() { + StandardPass::RegisterDefaultPasses = RegisterStandardPassList; + StandardPass::CreateVerifierPass = CreateVerifierPass; + } + private: + static llvm::Pass *CreateVerifierPass() { return createVerifierPass(); } + /// Passes must be registered with functions that take no arguments, so we have + /// to wrap their existing constructors. + static Pass *createDefaultScalarReplAggregatesPass(void) { + return createScalarReplAggregatesPass(-1, false); + } + static Pass *createDefaultLoopUnswitchPass(void) { + return createLoopUnswitchPass(false); + } + static Pass *createDefaultLoopUnrollPass(void) { + return createLoopUnrollPass(); + } + static Pass *createSizeOptimizingLoopUnswitchPass(void) { + return createLoopUnswitchPass(true); + } + static void RegisterStandardPassList(void) { + // Standard alias analysis passes + + // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that + // BasicAliasAnalysis wins if they disagree. This is intended to help + // support "obvious" type-punning idioms. +#define DEFAULT_ALIAS_ANALYSIS_PASS(pass, flags)\ + StandardPass::RegisterDefaultPass(\ + PassInfo::NormalCtor_t(create ## pass ## Pass),\ + &DefaultStandardPasses::pass ## ID, 0, StandardPass::AliasAnalysis, flags) + DEFAULT_ALIAS_ANALYSIS_PASS(TypeBasedAliasAnalysis, 0); + DEFAULT_ALIAS_ANALYSIS_PASS(BasicAliasAnalysis, 0); +#undef DEFAULT_ALIAS_ANALYSIS_PASS + +#define DEFAULT_FUNCTION_PASS(pass, flags)\ + StandardPass::RegisterDefaultPass(\ + PassInfo::NormalCtor_t(create ## pass ## Pass),\ + &DefaultStandardPasses::pass ## ID, 0, StandardPass::Function, flags) + DEFAULT_FUNCTION_PASS(CFGSimplification, + StandardPass::OptimzationFlags(1)); + DEFAULT_FUNCTION_PASS(ScalarReplAggregates, + StandardPass::OptimzationFlags(1)); + DEFAULT_FUNCTION_PASS(EarlyCSE, StandardPass::OptimzationFlags(1)); +#undef DEFAULT_FUNCTION_PASS + +#define DEFAULT_MODULE_PASS(pass, flags)\ + StandardPass::RegisterDefaultPass(\ + PassInfo::NormalCtor_t(create ## pass ## Pass),\ + &DefaultStandardPasses::pass ## ID, 0, StandardPass::Module, flags) + // Optimize out global vars + DEFAULT_MODULE_PASS(GlobalOptimizer, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + // IP SCCP + DEFAULT_MODULE_PASS(IPSCCP, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + // Dead argument elimination + DEFAULT_MODULE_PASS(DeadArgElimination, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + // Clean up after IPCP & DAE + DEFAULT_MODULE_PASS(InstructionCombining, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + // Clean up after IPCP & DAE + DEFAULT_MODULE_PASS(CFGSimplification, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + + // Remove dead EH info + DEFAULT_MODULE_PASS(PruneEH, StandardPass::OptimzationFlags(0, 0, + StandardPass::UnitAtATime | StandardPass::HaveExceptions)); + // Placeholder that will be replaced by an inliner if one is specified + StandardPass::RegisterDefaultPass(0, + &DefaultStandardPasses::InlinerPlaceholderID, 0, + StandardPass::Module); + // Set readonly/readnone attrs + DEFAULT_MODULE_PASS(FunctionAttrs, StandardPass::OptimzationFlags(0, 0, + StandardPass::UnitAtATime)); + // Scalarize uninlined fn args + DEFAULT_MODULE_PASS(ArgumentPromotion, StandardPass::OptimzationFlags(2)); + // Start of function pass. + // Break up aggregate allocas, using SSAUpdater. + StandardPass::RegisterDefaultPass( + PassInfo::NormalCtor_t(createDefaultScalarReplAggregatesPass), + &DefaultStandardPasses::ScalarReplAggregatesID, 0, + StandardPass::Module); + // Catch trivial redundancies + DEFAULT_MODULE_PASS(EarlyCSE, 0); + // Library Call Optimizations + DEFAULT_MODULE_PASS(SimplifyLibCalls, + StandardPass::OptimzationFlags(0, 0, StandardPass::SimplifyLibCalls)); + // Thread jumps + DEFAULT_MODULE_PASS(JumpThreading, 0); + // Propagate conditionals + DEFAULT_MODULE_PASS(CorrelatedValuePropagation, 0); + // Merge & remove BBs + DEFAULT_MODULE_PASS(CFGSimplification, 0); + // Combine silly seq's + DEFAULT_MODULE_PASS(InstructionCombining, 0); + // Eliminate tail calls + DEFAULT_MODULE_PASS(TailCallElimination, 0); + // Merge & remove BBs + DEFAULT_MODULE_PASS(CFGSimplification, 0); + // Reassociate expressions + DEFAULT_MODULE_PASS(Reassociate, 0); + // Rotate Loop + DEFAULT_MODULE_PASS(LoopRotate, 0); + // Hoist loop invariants + DEFAULT_MODULE_PASS(LICM, 0); + // Optimize for size if the optimzation level is 0-2 + StandardPass::RegisterDefaultPass( + PassInfo::NormalCtor_t(createSizeOptimizingLoopUnswitchPass), + &DefaultStandardPasses::LoopUnswitchID, 0, + StandardPass::Module, + StandardPass::OptimzationFlags(0, 2)); + // Optimize for size if the optimzation level is >2, and OptimizeSize is + // set + StandardPass::RegisterDefaultPass( + PassInfo::NormalCtor_t(createSizeOptimizingLoopUnswitchPass), + &DefaultStandardPasses::LoopUnswitchID, 0, + StandardPass::Module, + StandardPass::OptimzationFlags(3, 0, StandardPass::OptimizeSize)); + // Don't optimize for size if optimisation level is >2 and OptimizeSize + // is not set + StandardPass::RegisterDefaultPass( + PassInfo::NormalCtor_t(createDefaultLoopUnswitchPass), + &DefaultStandardPasses::LoopUnswitchID, 0, + StandardPass::Module, + StandardPass::OptimzationFlags(3, 0, 0, StandardPass::OptimizeSize)); + DEFAULT_MODULE_PASS(InstructionCombining, 0); + // Canonicalize indvars + DEFAULT_MODULE_PASS(IndVarSimplify, 0); + // Recognize idioms like memset. + DEFAULT_MODULE_PASS(LoopIdiom, 0); + // Delete dead loops + DEFAULT_MODULE_PASS(LoopDeletion, 0); + // Unroll small loops + StandardPass::RegisterDefaultPass( + PassInfo::NormalCtor_t(createDefaultLoopUnrollPass), + &DefaultStandardPasses::LoopUnrollID, 0, + StandardPass::Module, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnrollLoops)); + // Remove redundancies + DEFAULT_MODULE_PASS(GVN, StandardPass::OptimzationFlags(2)); + // Remove memcpy / form memset + DEFAULT_MODULE_PASS(MemCpyOpt, 0); + // Constant prop with SCCP + DEFAULT_MODULE_PASS(SCCP, 0); + + // Run instcombine after redundancy elimination to exploit opportunities + // opened up by them. + DEFAULT_MODULE_PASS(InstructionCombining, 0); + // Thread jumps + DEFAULT_MODULE_PASS(JumpThreading, 0); + DEFAULT_MODULE_PASS(CorrelatedValuePropagation, 0); + // Delete dead stores + DEFAULT_MODULE_PASS(DeadStoreElimination, 0); + // Delete dead instructions + DEFAULT_MODULE_PASS(AggressiveDCE, 0); + // Merge & remove BBs + DEFAULT_MODULE_PASS(CFGSimplification, 0); + // Clean up after everything. + DEFAULT_MODULE_PASS(InstructionCombining, 0); + + // Get rid of dead prototypes + DEFAULT_MODULE_PASS(StripDeadPrototypes, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + // Eliminate dead types + DEFAULT_MODULE_PASS(DeadTypeElimination, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + + // GlobalOpt already deletes dead functions and globals, at -O3 try a + // late pass of GlobalDCE. It is capable of deleting dead cycles. + // Remove dead fns and globals. + DEFAULT_MODULE_PASS(GlobalDCE, + StandardPass::OptimzationFlags(3, 0, StandardPass::UnitAtATime)); + // Merge dup global constants + DEFAULT_MODULE_PASS(ConstantMerge, + StandardPass::OptimzationFlags(2, 0, StandardPass::UnitAtATime)); +#undef DEFAULT_MODULE_PASS + +#define DEFAULT_LTO_PASS(pass, flags)\ + StandardPass::RegisterDefaultPass(\ + PassInfo::NormalCtor_t(create ## pass ## Pass), &DefaultStandardPasses::pass ## ID, 0, StandardPass::LTO, flags) + + // LTO passes + + // Propagate constants at call sites into the functions they call. This + // opens opportunities for globalopt (and inlining) by substituting function + // pointers passed as arguments to direct uses of functions. + DEFAULT_LTO_PASS(IPSCCP, 0); + + // Now that we internalized some globals, see if we can hack on them! + DEFAULT_LTO_PASS(GlobalOptimizer, 0); + + // Linking modules together can lead to duplicated global constants, only + // keep one copy of each constant... + DEFAULT_LTO_PASS(ConstantMerge, 0); + + // Remove unused arguments from functions... + DEFAULT_LTO_PASS(DeadArgElimination, 0); + + // Reduce the code after globalopt and ipsccp. Both can open up significant + // simplification opportunities, and both can propagate functions through + // function pointers. When this happens, we often have to resolve varargs + // calls, etc, so let instcombine do this. + DEFAULT_LTO_PASS(InstructionCombining, 0); + + // Inline small functions + DEFAULT_LTO_PASS(FunctionInlining, + StandardPass::OptimzationFlags(0, 0xf, StandardPass::RunInliner)); + // Remove dead EH info. + DEFAULT_LTO_PASS(PruneEH, 0); + // Optimize globals again if we ran the inliner. + DEFAULT_LTO_PASS(GlobalOptimizer, + StandardPass::OptimzationFlags(0, 0xf, StandardPass::RunInliner)); + DEFAULT_LTO_PASS(GlobalDCE, 0); + + // If we didn't decide to inline a function, check to see if we can + // transform it to pass arguments by value instead of by reference. + DEFAULT_LTO_PASS(ArgumentPromotion, 0); + + // The IPO passes may leave cruft around. Clean up after them. + DEFAULT_LTO_PASS(InstructionCombining, 0); + DEFAULT_LTO_PASS(JumpThreading, 0); + // Break up allocas + DEFAULT_LTO_PASS(ScalarReplAggregates, 0); + + // Run a few AA driven optimizations here and now, to cleanup the code. + // Add nocapture. + DEFAULT_LTO_PASS(FunctionAttrs, 0); + // IP alias analysis. + DEFAULT_LTO_PASS(GlobalsModRef, 0); + + // Hoist loop invariants. + DEFAULT_LTO_PASS(LICM, 0); + // Remove redundancies. + DEFAULT_LTO_PASS(GVN, 0); + // Remove dead memcpys. + DEFAULT_LTO_PASS(MemCpyOpt, 0); + // Nuke dead stores. + DEFAULT_LTO_PASS(DeadStoreElimination, 0); + + // Cleanup and simplify the code after the scalar optimizations. + DEFAULT_LTO_PASS(InstructionCombining, 0); + + DEFAULT_LTO_PASS(JumpThreading, 0); + + // Delete basic blocks, which optimization passes may have killed. + DEFAULT_LTO_PASS(CFGSimplification, 0); + + // Now that we have optimized the program, discard unreachable functions. + DEFAULT_LTO_PASS(GlobalDCE, 0); +#undef DEFAULT_LTO_PASS + } + }; + static RegisterStandardPassLists AutoRegister; + + static inline void createStandardAliasAnalysisPasses(PassManagerBase *PM) { - // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that - // BasicAliasAnalysis wins if they disagree. This is intended to help - // support "obvious" type-punning idioms. - PM->add(createTypeBasedAliasAnalysisPass()); - PM->add(createBasicAliasAnalysisPass()); + StandardPass::AddPassesFromSet(PM, StandardPass::AliasAnalysis); } /// createStandardFunctionPasses - Add the standard list of function passes to @@ -42,12 +304,8 @@ /// -O1, etc. static inline void createStandardFunctionPasses(PassManagerBase *PM, unsigned OptimizationLevel) { - if (OptimizationLevel > 0) { - createStandardAliasAnalysisPasses(PM); - PM->add(createCFGSimplificationPass()); - PM->add(createScalarReplAggregatesPass()); - PM->add(createEarlyCSEPass()); - } + StandardPass::AddPassesFromSet(PM, StandardPass::AliasAnalysis); + StandardPass::AddPassesFromSet(PM, StandardPass::Function, OptimizationLevel); } /// createStandardModulePasses - Add the standard list of module passes to the @@ -78,84 +336,17 @@ PM->add(InliningPass); return; } - - if (UnitAtATime) { - PM->add(createGlobalOptimizerPass()); // Optimize out global vars - - PM->add(createIPSCCPPass()); // IP SCCP - PM->add(createDeadArgEliminationPass()); // Dead argument elimination - - PM->add(createInstructionCombiningPass());// Clean up after IPCP & DAE - PM->add(createCFGSimplificationPass()); // Clean up after IPCP & DAE - } - - // Start of CallGraph SCC passes. - if (UnitAtATime && HaveExceptions) - PM->add(createPruneEHPass()); // Remove dead EH info - if (InliningPass) - PM->add(InliningPass); - if (UnitAtATime) - PM->add(createFunctionAttrsPass()); // Set readonly/readnone attrs - if (OptimizationLevel > 2) - PM->add(createArgumentPromotionPass()); // Scalarize uninlined fn args - - // Start of function pass. - // Break up aggregate allocas, using SSAUpdater. - PM->add(createScalarReplAggregatesPass(-1, false)); - PM->add(createEarlyCSEPass()); // Catch trivial redundancies - if (SimplifyLibCalls) - PM->add(createSimplifyLibCallsPass()); // Library Call Optimizations - PM->add(createJumpThreadingPass()); // Thread jumps. - PM->add(createCorrelatedValuePropagationPass()); // Propagate conditionals - PM->add(createCFGSimplificationPass()); // Merge & remove BBs - PM->add(createInstructionCombiningPass()); // Combine silly seq's - - PM->add(createTailCallEliminationPass()); // Eliminate tail calls - PM->add(createCFGSimplificationPass()); // Merge & remove BBs - PM->add(createReassociatePass()); // Reassociate expressions - PM->add(createLoopRotatePass()); // Rotate Loop - PM->add(createLICMPass()); // Hoist loop invariants - PM->add(createLoopUnswitchPass(OptimizeSize || OptimizationLevel < 3)); - PM->add(createInstructionCombiningPass()); - PM->add(createIndVarSimplifyPass()); // Canonicalize indvars - PM->add(createLoopIdiomPass()); // Recognize idioms like memset. - PM->add(createLoopDeletionPass()); // Delete dead loops - if (UnrollLoops) - PM->add(createLoopUnrollPass()); // Unroll small loops - if (OptimizationLevel > 1) - PM->add(createGVNPass()); // Remove redundancies - PM->add(createMemCpyOptPass()); // Remove memcpy / form memset - PM->add(createSCCPPass()); // Constant prop with SCCP - - // Run instcombine after redundancy elimination to exploit opportunities - // opened up by them. - PM->add(createInstructionCombiningPass()); - PM->add(createJumpThreadingPass()); // Thread jumps - PM->add(createCorrelatedValuePropagationPass()); - PM->add(createDeadStoreEliminationPass()); // Delete dead stores - PM->add(createAggressiveDCEPass()); // Delete dead instructions - PM->add(createCFGSimplificationPass()); // Merge & remove BBs - PM->add(createInstructionCombiningPass()); // Clean up after everything. - - if (UnitAtATime) { - PM->add(createStripDeadPrototypesPass()); // Get rid of dead prototypes - PM->add(createDeadTypeEliminationPass()); // Eliminate dead types - // GlobalOpt already deletes dead functions and globals, at -O3 try a - // late pass of GlobalDCE. It is capable of deleting dead cycles. - if (OptimizationLevel > 2) - PM->add(createGlobalDCEPass()); // Remove dead fns and globals. + StandardPass::AddPassesFromSet(PM, StandardPass::Module, + StandardPass::OptimzationFlags(OptimizationLevel, 0, + (OptimizeSize ? StandardPass::OptimizeSize : 0) | + (UnitAtATime ? StandardPass::UnitAtATime : 0) | + (UnrollLoops ? StandardPass::UnrollLoops : 0) | + (SimplifyLibCalls ? StandardPass::SimplifyLibCalls : 0) | + (HaveExceptions ? StandardPass::HaveExceptions : 0)), + false, + InliningPass); - if (OptimizationLevel > 1) - PM->add(createConstantMergePass()); // Merge dup global constants - } - } - - static inline void addOnePass(PassManagerBase *PM, Pass *P, bool AndVerify) { - PM->add(P); - - if (AndVerify) - PM->add(createVerifierPass()); } /// createStandardLTOPasses - Add the standard list of module passes suitable @@ -174,70 +365,15 @@ // Now that composite has been compiled, scan through the module, looking // for a main function. If main is defined, mark all other functions // internal. - if (Internalize) - addOnePass(PM, createInternalizePass(true), VerifyEach); - - // Propagate constants at call sites into the functions they call. This - // opens opportunities for globalopt (and inlining) by substituting function - // pointers passed as arguments to direct uses of functions. - addOnePass(PM, createIPSCCPPass(), VerifyEach); - - // Now that we internalized some globals, see if we can hack on them! - addOnePass(PM, createGlobalOptimizerPass(), VerifyEach); - - // Linking modules together can lead to duplicated global constants, only - // keep one copy of each constant... - addOnePass(PM, createConstantMergePass(), VerifyEach); - - // Remove unused arguments from functions... - addOnePass(PM, createDeadArgEliminationPass(), VerifyEach); - - // Reduce the code after globalopt and ipsccp. Both can open up significant - // simplification opportunities, and both can propagate functions through - // function pointers. When this happens, we often have to resolve varargs - // calls, etc, so let instcombine do this. - addOnePass(PM, createInstructionCombiningPass(), VerifyEach); - - // Inline small functions - if (RunInliner) - addOnePass(PM, createFunctionInliningPass(), VerifyEach); - - addOnePass(PM, createPruneEHPass(), VerifyEach); // Remove dead EH info. - // Optimize globals again if we ran the inliner. - if (RunInliner) - addOnePass(PM, createGlobalOptimizerPass(), VerifyEach); - addOnePass(PM, createGlobalDCEPass(), VerifyEach); // Remove dead functions. - - // If we didn't decide to inline a function, check to see if we can - // transform it to pass arguments by value instead of by reference. - addOnePass(PM, createArgumentPromotionPass(), VerifyEach); - - // The IPO passes may leave cruft around. Clean up after them. - addOnePass(PM, createInstructionCombiningPass(), VerifyEach); - addOnePass(PM, createJumpThreadingPass(), VerifyEach); - // Break up allocas - addOnePass(PM, createScalarReplAggregatesPass(), VerifyEach); - - // Run a few AA driven optimizations here and now, to cleanup the code. - addOnePass(PM, createFunctionAttrsPass(), VerifyEach); // Add nocapture. - addOnePass(PM, createGlobalsModRefPass(), VerifyEach); // IP alias analysis. - - addOnePass(PM, createLICMPass(), VerifyEach); // Hoist loop invariants. - addOnePass(PM, createGVNPass(), VerifyEach); // Remove redundancies. - addOnePass(PM, createMemCpyOptPass(), VerifyEach); // Remove dead memcpys. - // Nuke dead stores. - addOnePass(PM, createDeadStoreEliminationPass(), VerifyEach); - - // Cleanup and simplify the code after the scalar optimizations. - addOnePass(PM, createInstructionCombiningPass(), VerifyEach); - - addOnePass(PM, createJumpThreadingPass(), VerifyEach); - - // Delete basic blocks, which optimization passes may have killed. - addOnePass(PM, createCFGSimplificationPass(), VerifyEach); + if (Internalize) { + PM->add(createInternalizePass(true)); + if (VerifyEach) + PM->add(createVerifierPass()); + } - // Now that we have optimized the program, discard unreachable functions. - addOnePass(PM, createGlobalDCEPass(), VerifyEach); + StandardPass::AddPassesFromSet(PM, StandardPass::LTO, + StandardPass::OptimzationFlags(0, 0, RunInliner ? + StandardPass::RunInliner : 0), VerifyEach); } } Added: llvm/trunk/lib/Support/StandardPasses.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/StandardPasses.cpp?rev=131556&view=auto ============================================================================== --- llvm/trunk/lib/Support/StandardPasses.cpp (added) +++ llvm/trunk/lib/Support/StandardPasses.cpp Wed May 18 14:00:41 2011 @@ -0,0 +1,247 @@ +//===-- lib/Support/StandardPasses.cpp - Standard pass lists -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines utility functions for creating a "standard" set of +// optimization passes, so that compilers and tools which use optimization +// passes use the same set of standard passes. +// +// This allows the creation of multiple standard sets, and their later +// modification by plugins and front ends. +// +//===----------------------------------------------------------------------===// + +#include "llvm/PassManager.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/ManagedStatic.h" +#include "llvm/DefaultPasses.h" +#include "llvm/Support/Mutex.h" + +using namespace llvm::DefaultStandardPasses; +using namespace llvm; + +namespace { + +/// Entry in the standard passes list. +struct StandardPassEntry { + /// Function called to create the pass + PassInfo::NormalCtor_t createPass; + /// Unique identifier for this pass + unsigned char *passID; + /// Flags specifying when this pass should be run + unsigned flags; + + StandardPassEntry(PassInfo::NormalCtor_t constructor, unsigned char *ID, + unsigned f) : createPass(constructor), passID(ID), flags(f) {}; +}; + +/// Standard alias analysis passes +static llvm::SmallVector AAPasses; +/// Standard function passes +static llvm::SmallVector FunctionPasses; +/// Standard module passes +static llvm::SmallVector ModulePasses; +/// Standard link-time optimization passes +static llvm::SmallVector LTOPasses; + +/// Entry in the unresolved standard pass list. IF a pass is inserted in front +/// of a pass that is not yet registered in the standard pass list then it is +/// stored in a separate list and resolved later. +struct UnresolvedStandardPass : public StandardPassEntry { + /// The set into which this is stored + StandardPass::StandardSet set; + /// The unique ID of the pass that should follow this one in the sequence + unsigned char *next; + UnresolvedStandardPass(PassInfo::NormalCtor_t constructor, + unsigned char *newPass, + unsigned char *oldPass, + StandardPass::StandardSet s, + unsigned f) : + StandardPassEntry(constructor, newPass, f), set(s), next(oldPass) {} +}; + +/// The passes that can not be inserted into the correct lists yet because of +/// their place in the sequence. +static llvm::SmallVector UnresolvedPasses; + +/// Returns a reference to the pass list for the corresponding set of +/// optimisations. +llvm::SmallVectorImpl& +PassList(StandardPass::StandardSet set) { + switch (set) { + case StandardPass::AliasAnalysis: return AAPasses; + case StandardPass::Function: return FunctionPasses; + case StandardPass::Module: return ModulePasses; + case StandardPass::LTO: return LTOPasses; + } + // We could use a map of standard pass lists to allow definition of new + // default sets + llvm_unreachable("Invalid standard optimization set requested"); +} + +static ManagedStatic > Lock; + +/// Registers the default set of standard passes. This is called lazily when +/// an attempt is made to read or modify the standard pass list +void RegisterDefaultStandardPasses(void(*doRegister)(void)) { + // Only initialize the standard passes once + static volatile bool initialized = false; + if (initialized) return; + + llvm::sys::SmartScopedLock Guard(*Lock); + if (initialized) return; + if (doRegister) { + assert("No passes registered before setting default passes" && + AAPasses.size() == 0 && + FunctionPasses.size() == 0 && + LTOPasses.size() == 0 && + ModulePasses.size() == 0); + + // We must set initialized to true before calling this function, because + // the doRegister() function will probably call RegisterDefaultPasses(), + // which will call this function, and we'd end up with infinite recursion + // and breakage if we didn't. + initialized = true; + doRegister(); + } +} + +} // Anonymous namespace + +void (*StandardPass::RegisterDefaultPasses)(void); +Pass* (*StandardPass::CreateVerifierPass)(void); + +void StandardPass::RegisterDefaultPass(PassInfo::NormalCtor_t constructor, + unsigned char *newPass, + unsigned char *oldPass, + StandardPass::StandardSet set, + unsigned flags) { + // Make sure that the standard sets are already regstered + RegisterDefaultStandardPasses(RegisterDefaultPasses); + // Get the correct list to modify + llvm::SmallVectorImpl& passList = PassList(set); + + // If there is no old pass specified, then we are adding a new final pass, so + // just push it onto the end. + if (!oldPass) { + StandardPassEntry pass(constructor, newPass, flags); + passList.push_back(pass); + return; + } + + // Find the correct place to insert the pass. This is a linear search, but + // this shouldn't be too slow since the SmallVector will store the values in + // a contiguous block of memory. Each entry is just three words of memory, so + // in most cases we are only going to be looking in one or two cache lines. + // The extra memory accesses from a more complex search structure would + // offset any performance gain (unless someone decides to add an insanely + // large set of standard passes to a set) + for (SmallVectorImpl::iterator i=passList.begin(), + e=passList.end() ; i!=e ; ++i) { + if (i->passID == oldPass) { + StandardPassEntry pass(constructor, newPass, flags); + passList.insert(i, pass); + // If we've added a new pass, then there may have gained the ability to + // insert one of the previously unresolved ones. If so, insert the new + // one. + for (SmallVectorImpl::iterator + u=UnresolvedPasses.begin(), eu=UnresolvedPasses.end() ; u!=eu ; ++u){ + if (u->next == newPass && u->set == set) { + UnresolvedStandardPass p = *u; + UnresolvedPasses.erase(u); + RegisterDefaultPass(p.createPass, p.passID, p.next, p.set, p.flags); + } + } + return; + } + } + // If we get to here, then we didn't find the correct place to insert the new + // pass + UnresolvedStandardPass pass(constructor, newPass, oldPass, set, flags); + UnresolvedPasses.push_back(pass); +} + +void StandardPass::AddPassesFromSet(PassManagerBase *PM, + StandardSet set, + unsigned flags, + bool VerifyEach, + Pass *inliner) { + RegisterDefaultStandardPasses(RegisterDefaultPasses); + unsigned level = OptimizationLevel(flags); + flags = RequiredFlags(flags); + llvm::SmallVectorImpl& passList = PassList(set); + + // Add all of the passes from this set + for (SmallVectorImpl::iterator i=passList.begin(), + e=passList.end() ; i!=e ; ++i) { + // Skip passes that don't have conditions that match the ones specified + // here. For a pass to match: + // - Its minimum optimisation level must be less than or equal to the + // specified level. + // - Its maximum optimisation level must be greater than or equal to the + // specified level + // - All of its required flags must be set + // - None of its disallowed flags may be set + if ((level >= OptimizationLevel(i->flags)) && + ((level <= MaxOptimizationLevel(i->flags)) + || MaxOptimizationLevel(i->flags) == 0) && + ((RequiredFlags(i->flags) & flags) == RequiredFlags(i->flags)) && + ((DisallowedFlags(i->flags) & flags) == 0)) { + // This is quite an ugly way of allowing us to specify an inliner pass to + // insert. Ideally, we'd replace this with a general mechanism allowing + // callers to replace arbitrary passes in the list. + Pass *p = 0; + if (&InlinerPlaceholderID == i->passID) { + p = inliner; + } else if (i->createPass) + p = i->createPass(); + if (p) { + PM->add(p); + if (VerifyEach) + PM->add(CreateVerifierPass()); + } + } + } +} + +unsigned char DefaultStandardPasses::AggressiveDCEID; +unsigned char DefaultStandardPasses::ArgumentPromotionID; +unsigned char DefaultStandardPasses::BasicAliasAnalysisID; +unsigned char DefaultStandardPasses::CFGSimplificationID; +unsigned char DefaultStandardPasses::ConstantMergeID; +unsigned char DefaultStandardPasses::CorrelatedValuePropagationID; +unsigned char DefaultStandardPasses::DeadArgEliminationID; +unsigned char DefaultStandardPasses::DeadStoreEliminationID; +unsigned char DefaultStandardPasses::DeadTypeEliminationID; +unsigned char DefaultStandardPasses::EarlyCSEID; +unsigned char DefaultStandardPasses::FunctionAttrsID; +unsigned char DefaultStandardPasses::FunctionInliningID; +unsigned char DefaultStandardPasses::GVNID; +unsigned char DefaultStandardPasses::GlobalDCEID; +unsigned char DefaultStandardPasses::GlobalOptimizerID; +unsigned char DefaultStandardPasses::GlobalsModRefID; +unsigned char DefaultStandardPasses::IPSCCPID; +unsigned char DefaultStandardPasses::IndVarSimplifyID; +unsigned char DefaultStandardPasses::InlinerPlaceholderID; +unsigned char DefaultStandardPasses::InstructionCombiningID; +unsigned char DefaultStandardPasses::JumpThreadingID; +unsigned char DefaultStandardPasses::LICMID; +unsigned char DefaultStandardPasses::LoopDeletionID; +unsigned char DefaultStandardPasses::LoopIdiomID; +unsigned char DefaultStandardPasses::LoopRotateID; +unsigned char DefaultStandardPasses::LoopUnrollID; +unsigned char DefaultStandardPasses::LoopUnswitchID; +unsigned char DefaultStandardPasses::MemCpyOptID; +unsigned char DefaultStandardPasses::PruneEHID; +unsigned char DefaultStandardPasses::ReassociateID; +unsigned char DefaultStandardPasses::SCCPID; +unsigned char DefaultStandardPasses::ScalarReplAggregatesID; +unsigned char DefaultStandardPasses::SimplifyLibCallsID; +unsigned char DefaultStandardPasses::StripDeadPrototypesID; +unsigned char DefaultStandardPasses::TailCallEliminationID; +unsigned char DefaultStandardPasses::TypeBasedAliasAnalysisID; From stuart at apple.com Wed May 18 14:19:17 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 18 May 2011 19:19:17 -0000 Subject: [llvm-commits] [llvm] r131557 - /llvm/trunk/test/CodeGen/X86/sibcall.ll Message-ID: <20110518191917.E5CBE2A6C12C@llvm.org> Author: stuart Date: Wed May 18 14:19:17 2011 New Revision: 131557 URL: http://llvm.org/viewvc/llvm-project?rev=131557&view=rev Log: An imminent fix to the x86_64 byval logic will expose a flaw in the x86_64 sibcall logic. I've filed PR9943 for the sibcall problem, and this patch alters the testcase to work around the flaw. When PR9943 is fixed, this patch should be reverted. Modified: llvm/trunk/test/CodeGen/X86/sibcall.ll Modified: llvm/trunk/test/CodeGen/X86/sibcall.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sibcall.ll?rev=131557&r1=131556&r2=131557&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/sibcall.ll (original) +++ llvm/trunk/test/CodeGen/X86/sibcall.ll Wed May 18 14:19:17 2011 @@ -198,7 +198,7 @@ ; rdar://r7717598 %struct.ns = type { i32, i32 } -%struct.cp = type { float, float } +%struct.cp = type { float, float, float, float, float } define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp { ; 32: t13: From eli.friedman at gmail.com Wed May 18 14:57:15 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 19:57:15 -0000 Subject: [llvm-commits] [llvm] r131559 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp test/Transforms/InstCombine/intrinsics.ll Message-ID: <20110518195715.2145D2A6C12C@llvm.org> Author: efriedma Date: Wed May 18 14:57:14 2011 New Revision: 131559 URL: http://llvm.org/viewvc/llvm-project?rev=131559&view=rev Log: More instcombine cleanup aimed towards improving debug line info. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/test/Transforms/InstCombine/intrinsics.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=131559&r1=131558&r2=131559&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Wed May 18 14:57:14 2011 @@ -111,10 +111,10 @@ Value *Src = Builder->CreateBitCast(MI->getArgOperand(1), NewSrcPtrTy); Value *Dest = Builder->CreateBitCast(MI->getArgOperand(0), NewDstPtrTy); - Instruction *L = new LoadInst(Src, "tmp", MI->isVolatile(), SrcAlign); - InsertNewInstBefore(L, *MI); - InsertNewInstBefore(new StoreInst(L, Dest, MI->isVolatile(), DstAlign), - *MI); + LoadInst *L = Builder->CreateLoad(Src, MI->isVolatile()); + L->setAlignment(SrcAlign); + StoreInst *S = Builder->CreateStore(L, Dest, MI->isVolatile()); + S->setAlignment(DstAlign); // Set the size of the copy to 0, it will be deleted on the next iteration. MI->setArgOperand(2, Constant::getNullValue(MemOpLength->getType())); @@ -154,8 +154,9 @@ // Extract the fill value and store. uint64_t Fill = FillC->getZExtValue()*0x0101010101010101ULL; - InsertNewInstBefore(new StoreInst(ConstantInt::get(ITy, Fill), - Dest, false, Alignment), *MI); + StoreInst *S = Builder->CreateStore(ConstantInt::get(ITy, Fill), Dest, + MI->isVolatile()); + S->setAlignment(Alignment); // Set the size of the copy to 0, it will be deleted on the next iteration. MI->setLength(Constant::getNullValue(LenC->getType())); @@ -405,20 +406,21 @@ if (LHSKnownNegative && RHSKnownNegative) { // The sign bit is set in both cases: this MUST overflow. // Create a simple add instruction, and insert it into the struct. - Instruction *Add = BinaryOperator::CreateAdd(LHS, RHS, "", &CI); - Worklist.Add(Add); + Value *Add = Builder->CreateAdd(LHS, RHS); + Add->takeName(&CI); Constant *V[] = { - UndefValue::get(LHS->getType()),ConstantInt::getTrue(II->getContext()) + UndefValue::get(LHS->getType()), + ConstantInt::getTrue(II->getContext()) }; Constant *Struct = ConstantStruct::get(II->getContext(), V, 2, false); return InsertValueInst::Create(Struct, Add, 0); } - + if (LHSKnownPositive && RHSKnownPositive) { // The sign bit is clear in both cases: this CANNOT overflow. // Create a simple add instruction, and insert it into the struct. - Instruction *Add = BinaryOperator::CreateNUWAdd(LHS, RHS, "", &CI); - Worklist.Add(Add); + Value *Add = Builder->CreateNUWAdd(LHS, RHS); + Add->takeName(&CI); Constant *V[] = { UndefValue::get(LHS->getType()), ConstantInt::getFalse(II->getContext()) @@ -1276,24 +1278,19 @@ if (InvokeInst *II = dyn_cast(Caller)) { NewCaller = InvokeInst::Create(NewCallee, II->getNormalDest(), II->getUnwindDest(), - NewArgs.begin(), NewArgs.end(), - Caller->getName(), Caller); + NewArgs.begin(), NewArgs.end()); cast(NewCaller)->setCallingConv(II->getCallingConv()); cast(NewCaller)->setAttributes(NewPAL); } else { - NewCaller = CallInst::Create(NewCallee, NewArgs.begin(), NewArgs.end(), - Caller->getName(), Caller); + NewCaller = CallInst::Create(NewCallee, NewArgs.begin(), NewArgs.end()); if (cast(Caller)->isTailCall()) cast(NewCaller)->setTailCall(); cast(NewCaller)-> setCallingConv(cast(Caller)->getCallingConv()); cast(NewCaller)->setAttributes(NewPAL); } - if (!Caller->getType()->isVoidTy()) - ReplaceInstUsesWith(*Caller, NewCaller); - Caller->eraseFromParent(); - Worklist.Remove(Caller); - return 0; + + return NewCaller; } } Modified: llvm/trunk/test/Transforms/InstCombine/intrinsics.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/intrinsics.ll?rev=131559&r1=131558&r2=131559&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/intrinsics.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/intrinsics.ll Wed May 18 14:57:14 2011 @@ -30,9 +30,9 @@ ; CHECK: @uaddtest2 ; CHECK-NEXT: %and.A = and i8 %A, 127 ; CHECK-NEXT: %and.B = and i8 %B, 127 -; CHECK-NEXT: %1 = add nuw i8 %and.A, %and.B +; CHECK-NEXT: %x = add nuw i8 %and.A, %and.B ; CHECK-NEXT: store i1 false, i1* %overflowPtr -; CHECK-NEXT: ret i8 %1 +; CHECK-NEXT: ret i8 %x } define i8 @uaddtest3(i8 %A, i8 %B, i1* %overflowPtr) { @@ -46,9 +46,9 @@ ; CHECK: @uaddtest3 ; CHECK-NEXT: %or.A = or i8 %A, -128 ; CHECK-NEXT: %or.B = or i8 %B, -128 -; CHECK-NEXT: %1 = add i8 %or.A, %or.B +; CHECK-NEXT: %x = add i8 %or.A, %or.B ; CHECK-NEXT: store i1 true, i1* %overflowPtr -; CHECK-NEXT: ret i8 %1 +; CHECK-NEXT: ret i8 %x } define i8 @uaddtest4(i8 %A, i1* %overflowPtr) { From mcrosier at apple.com Wed May 18 14:59:50 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 18 May 2011 19:59:50 -0000 Subject: [llvm-commits] [llvm] r131560 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/bool-zext.ll test/CodeGen/X86/vararg_tailcall.ll Message-ID: <20110518195950.8F2B62A6C12C@llvm.org> Author: mcrosier Date: Wed May 18 14:59:50 2011 New Revision: 131560 URL: http://llvm.org/viewvc/llvm-project?rev=131560&view=rev Log: Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible. Added: llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/test/CodeGen/X86/bool-zext.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=131560&r1=131559&r2=131560&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed May 18 14:59:50 2011 @@ -2525,16 +2525,29 @@ if (RegInfo->needsStackRealignment(MF)) return false; - // Do not sibcall optimize vararg calls unless the call site is not passing - // any arguments. - if (isVarArg && !Outs.empty()) - return false; - // Also avoid sibcall optimization if either caller or callee uses struct // return semantics. if (isCalleeStructRet || isCallerStructRet) return false; + // Do not sibcall optimize vararg calls unless all arguments are passed via + // registers + if (isVarArg && !Outs.empty()) { + SmallVector ArgLocs; + CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), + ArgLocs, *DAG.getContext()); + + // Allocate shadow area for Win64 + if (Subtarget->isTargetWin64()) { + CCInfo.AllocateStack(32, 8); + } + + CCInfo.AnalyzeCallOperands(Outs, CC_X86); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) + if (!ArgLocs[i].isRegLoc()) + return false; + } + // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. // Therefore if it's not used by the call it is not safe to optimize this into // a sibcall. Modified: llvm/trunk/test/CodeGen/X86/bool-zext.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bool-zext.ll?rev=131560&r1=131559&r2=131560&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/bool-zext.ll (original) +++ llvm/trunk/test/CodeGen/X86/bool-zext.ll Wed May 18 14:59:50 2011 @@ -2,7 +2,7 @@ ; CHECK: @bar1 ; CHECK: movzbl -; CHECK: callq +; CHECK: jmp define void @bar1(i1 zeroext %v1) nounwind ssp { entry: %conv = zext i1 %v1 to i32 @@ -12,7 +12,7 @@ ; CHECK: @bar2 ; CHECK-NOT: movzbl -; CHECK: callq +; CHECK: jmp define void @bar2(i8 zeroext %v1) nounwind ssp { entry: %conv = zext i8 %v1 to i32 Added: llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll?rev=131560&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll (added) +++ llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll Wed May 18 14:59:50 2011 @@ -0,0 +1,85 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + + at .str = private unnamed_addr constant [5 x i8] c"%ld\0A\00" + at sel = external global i8* + at sel3 = external global i8* + at sel4 = external global i8* + at sel5 = external global i8* + at sel6 = external global i8* + at sel7 = external global i8* + +; CHECK: @foo +; CHECK: jmp +define void @foo(i64 %arg) nounwind optsize ssp noredzone { +entry: + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone + ret void +} + +declare i32 @printf(i8*, ...) optsize noredzone + +; CHECK: @bar +; CHECK: jmp +define void @bar(i64 %arg) nounwind optsize ssp noredzone { +entry: + tail call void @bar2(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone + ret void +} + +declare void @bar2(i8*, i64) optsize noredzone + +; CHECK: @foo2 +; CHECK: jmp +define i8* @foo2(i8* %arg) nounwind optsize ssp noredzone { +entry: + %tmp1 = load i8** @sel, align 8, !tbaa !0 + %call = tail call i8* (i8*, i8*, ...)* @x2(i8* %arg, i8* %tmp1) nounwind optsize noredzone + ret i8* %call +} + +declare i8* @x2(i8*, i8*, ...) optsize noredzone + +; CHECK: @foo6 +; CHECK: jmp +define i8* @foo6(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { +entry: + %tmp2 = load i8** @sel3, align 8, !tbaa !0 + %tmp3 = load i8** @sel4, align 8, !tbaa !0 + %tmp4 = load i8** @sel5, align 8, !tbaa !0 + %tmp5 = load i8** @sel6, align 8, !tbaa !0 + %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5) nounwind optsize noredzone + ret i8* %call +} + +declare i8* @x3(i8*, i8*, i8*, ...) optsize noredzone + +; CHECK: @foo7 +; CHECK: callq +define i8* @foo7(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { +entry: + %tmp2 = load i8** @sel3, align 8, !tbaa !0 + %tmp3 = load i8** @sel4, align 8, !tbaa !0 + %tmp4 = load i8** @sel5, align 8, !tbaa !0 + %tmp5 = load i8** @sel6, align 8, !tbaa !0 + %tmp6 = load i8** @sel7, align 8, !tbaa !0 + %call = tail call i8* (i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...)* @x7(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i8* %tmp6) nounwind optsize noredzone + ret i8* %call +} + +declare i8* @x7(i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...) optsize noredzone + +; CHECK: @foo8 +; CHECK: callq +define i8* @foo8(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { +entry: + %tmp2 = load i8** @sel3, align 8, !tbaa !0 + %tmp3 = load i8** @sel4, align 8, !tbaa !0 + %tmp4 = load i8** @sel5, align 8, !tbaa !0 + %tmp5 = load i8** @sel6, align 8, !tbaa !0 + %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i32 48879, i32 48879) nounwind optsize noredzone + ret i8* %call +} + +!0 = metadata !{metadata !"any pointer", metadata !1} +!1 = metadata !{metadata !"omnipotent char", metadata !2} +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} From dpatel at apple.com Wed May 18 15:01:18 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 20:01:18 -0000 Subject: [llvm-commits] [llvm] r131561 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110518200118.95EDE2A6C12C@llvm.org> Author: dpatel Date: Wed May 18 15:01:18 2011 New Revision: 131561 URL: http://llvm.org/viewvc/llvm-project?rev=131561&view=rev Log: Use IRBuilder while simplifying unwind. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131561&r1=131560&r2=131561&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 15:01:18 2011 @@ -61,7 +61,7 @@ bool FoldValueComparisonIntoPredecessors(TerminatorInst *TI); bool SimplifyReturn(ReturnInst *RI); - bool SimplifyUnwind(UnwindInst *UI); + bool SimplifyUnwind(UnwindInst *UI, IRBuilder<> &Builder); bool SimplifyUnreachable(UnreachableInst *UI); bool SimplifySwitch(SwitchInst *SI); bool SimplifyIndirectBr(IndirectBrInst *IBI); @@ -2175,7 +2175,7 @@ return false; } -bool SimplifyCFGOpt::SimplifyUnwind(UnwindInst *UI) { +bool SimplifyCFGOpt::SimplifyUnwind(UnwindInst *UI, IRBuilder<> &Builder) { // Check to see if the first instruction in this block is just an unwind. // If so, replace any invoke instructions which use this as an exception // destination with call instructions. @@ -2190,14 +2190,16 @@ if (II && II->getUnwindDest() == BB) { // Insert a new branch instruction before the invoke, because this // is now a fall through. - BranchInst *BI = BranchInst::Create(II->getNormalDest(), II); + Builder.SetInsertPoint(II); + BranchInst *BI = Builder.CreateBr(II->getNormalDest()); Pred->getInstList().remove(II); // Take out of symbol table // Insert the call now. SmallVector Args(II->op_begin(), II->op_end()-3); - CallInst *CI = CallInst::Create(II->getCalledValue(), - Args.begin(), Args.end(), - II->getName(), BI); + Builder.SetInsertPoint(BI); + CallInst *CI = Builder.CreateCall(II->getCalledValue(), + Args.begin(), Args.end(), + II->getName()); CI->setCallingConv(II->getCallingConv()); CI->setAttributes(II->getAttributes()); // If the invoke produced a value, the Call now does instead. @@ -2671,7 +2673,7 @@ dyn_cast(BB->getTerminator())) { if (SimplifyUnreachable(UI)) return true; } else if (UnwindInst *UI = dyn_cast(BB->getTerminator())) { - if (SimplifyUnwind(UI)) return true; + if (SimplifyUnwind(UI, Builder)) return true; } else if (IndirectBrInst *IBI = dyn_cast(BB->getTerminator())) { if (SimplifyIndirectBr(IBI)) return true; From aggarwa4 at illinois.edu Wed May 18 15:23:04 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 18 May 2011 20:23:04 -0000 Subject: [llvm-commits] [poolalloc] r131562 - in /poolalloc/trunk: include/assistDS/VarArgsFunc.h lib/AssistDS/ArgCast.cpp lib/AssistDS/VarArgsFunc.cpp Message-ID: <20110518202304.1C77A2A6C12C@llvm.org> Author: aggarwa4 Date: Wed May 18 15:23:03 2011 New Revision: 131562 URL: http://llvm.org/viewvc/llvm-project?rev=131562&view=rev Log: ArgCast supersedes VarArgsFunc. Also code cleanup. Removed: poolalloc/trunk/include/assistDS/VarArgsFunc.h poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp Modified: poolalloc/trunk/lib/AssistDS/ArgCast.cpp Removed: poolalloc/trunk/include/assistDS/VarArgsFunc.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/VarArgsFunc.h?rev=131561&view=auto ============================================================================== --- poolalloc/trunk/include/assistDS/VarArgsFunc.h (original) +++ poolalloc/trunk/include/assistDS/VarArgsFunc.h (removed) @@ -1,31 +0,0 @@ -//===--- VarArgsFunc.cpp - Simplify calls to bitcasted const funcs --------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// Convert calls of type -// call(bitcast F to (...)*) () -// to -// call F() -// if the number and types of arguments passed matches. -//===----------------------------------------------------------------------===// - -#include "llvm/Instructions.h" -#include "llvm/Module.h" -#include "llvm/Pass.h" - -namespace llvm { - // - // Class: VarArgsFunc - // - class VarArgsFunc : public ModulePass { - public: - static char ID; - VarArgsFunc() : ModulePass(&ID) {} - virtual bool runOnModule(Module& M); - }; -} - Modified: poolalloc/trunk/lib/AssistDS/ArgCast.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/ArgCast.cpp?rev=131562&r1=131561&r2=131562&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/ArgCast.cpp (original) +++ poolalloc/trunk/lib/AssistDS/ArgCast.cpp Wed May 18 15:23:03 2011 @@ -52,42 +52,56 @@ bool ArgCast::runOnModule(Module& M) { std::vector worklist; - for (Module::iterator I = M.begin(); I != M.end(); ++I) - if (!I->isDeclaration() && !I->mayBeOverridden()) - // Find all uses of this function - for(Value::use_iterator ui = I->use_begin(), ue = I->use_end(); ui != ue; ++ui) - // check if is ever casted to a different function type - if (Constant *C = dyn_cast(ui)) - if (ConstantExpr *CE = dyn_cast(C)) - if (CE->getOpcode() == Instruction::BitCast) - if(CE->getOperand(0) == I) - if(const FunctionType *FTy = dyn_cast - ((cast(CE->getType()))->getElementType())) { - //casting to a varargs funtion - if(FTy->isVarArg()) - for(Value::use_iterator uii = CE->use_begin(), - uee = CE->use_end(); uii != uee; ++uii) { - // Find all uses of the casted value, and check if it is - // used in a Call Instruction - if (CallInst* CI = dyn_cast(uii)) { - // Check that it is the called value, and not an argument - if(CI->getCalledValue() != CE) - continue; - // Check that the number of arguments passed, and expected - // by the function are the same. - if(CI->getNumOperands() != I->arg_size() + 1) - continue; - // Check that the return type of the function matches that - // expected by the call inst(ensures that the reason for the - // cast is not the return type). - if(CI->getType() != I->getReturnType()) - continue; - - // If so, add to worklist - worklist.push_back(CI); - } - } - } + for (Module::iterator I = M.begin(); I != M.end(); ++I) { + if (I->isDeclaration() || I->mayBeOverridden()) + continue; + // Find all uses of this function + for(Value::use_iterator ui = I->use_begin(), ue = I->use_end(); ui != ue; ) { + // check if is ever casted to a different function type + ConstantExpr *CE = dyn_cast(ui++); + if(!CE) + continue; + if (CE->getOpcode() != Instruction::BitCast) + continue; + if(CE->getOperand(0) != I) + continue; + const PointerType *PTy = dyn_cast(CE->getType()); + if (!PTy) + continue; + const Type *ETy = PTy->getElementType(); + const FunctionType *FTy = dyn_cast(ETy); + if(!FTy) + continue; + // casting to a varargs funtion + // or function with same number of arguments + // possibly varying types of arguments + if(FTy->getNumParams() != I->arg_size() && !FTy->isVarArg()) + continue; + for(Value::use_iterator uii = CE->use_begin(), + uee = CE->use_end(); uii != uee; ++uii) { + // Find all uses of the casted value, and check if it is + // used in a Call Instruction + if (CallInst* CI = dyn_cast(uii)) { + // Check that it is the called value, and not an argument + if(CI->getCalledValue() != CE) + continue; + // Check that the number of arguments passed, and expected + // by the function are the same. + if(CI->getNumOperands() != I->arg_size() + 1) + continue; + // Check that the return type of the function matches that + // expected by the call inst(ensures that the reason for the + // cast is not the return type). + if(CI->getType() != I->getReturnType()) { + if(CI->getNumUses() != 0) + continue; + } + // If so, add to worklist + worklist.push_back(CI); + } + } + } + } // Proces the worklist of potential call sites to transform while(!worklist.empty()) { @@ -154,7 +168,17 @@ CallInst *CINew = CallInst::Create(F, Args.begin(), Args.end(), "", CI); CINew->setCallingConv(CI->getCallingConv()); CINew->setAttributes(CI->getAttributes()); - CI->replaceAllUsesWith(CINew); + if(!CI->use_empty()) + CI->replaceAllUsesWith(CINew); + + // Debug printing + DEBUG(errs() << "ARGCAST:"); + DEBUG(errs() << "ERASE:"); + DEBUG(CI->dump()); + DEBUG(errs() << "ARGCAST:"); + DEBUG(errs() << "ADDED:"); + DEBUG(CINew->dump()); + CI->eraseFromParent(); numChanged++; } Removed: poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp?rev=131561&view=auto ============================================================================== --- poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp (original) +++ poolalloc/trunk/lib/AssistDS/VarArgsFunc.cpp (removed) @@ -1,132 +0,0 @@ -//===-- VarArgsFunc.cpp - Simplify calls to bitcasted const funcs --------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// Convert calls of type -// call(bitcast F to (...)*) () -// to -// call F() -// if the number and types of arguments passed matches. -//===----------------------------------------------------------------------===// -#define DEBUG_TYPE "varargfunc" - -#include "assistDS/VarArgsFunc.h" -#include "llvm/Transforms/Utils/Cloning.h" -#include "llvm/ADT/Statistic.h" -#include "llvm/Support/FormattedStream.h" -#include "llvm/Support/Debug.h" - -#include -#include -#include - -using namespace llvm; - -// Pass statistics -STATISTIC(numSimplified, "Number of Calls Simplified"); - -// -// Method: runOnModule() -// Description: -// Entry point for this LLVM pass. Search for functions that are -// unnecessarily casted to varargs type, in a CallInst. -// Replace with direct calls to the function -// -// Inputs: -// M - A reference to the LLVM module to transform. -// -// Outputs: -// M - The transformed LLVM module. -// -// Return value: -// true - The module was modified. -// false - The module was not modified. -// -bool VarArgsFunc::runOnModule(Module& M) { - std::vector worklist; - - for (Module::iterator I = M.begin(); I != M.end(); ++I) { - // Go through all the functions - if (I->mayBeOverridden()) - continue; - //Uses of Function I - for(Value::use_iterator ui = I->use_begin(), ue = I->use_end(); - ui != ue; ++ui) - //Find all casted uses of the function - if (Constant *C = dyn_cast(ui)) - if (ConstantExpr *CE = dyn_cast(C)) - if (CE->getOpcode() == Instruction::BitCast) - if(CE->getOperand(0) == I) - if(const FunctionType *FTy = dyn_cast - ((cast(CE->getType()))->getElementType())) - //casting to a varargs funtion - if(FTy->isVarArg()) { - // Check if bitcasted Value is used in a callInst - for(Value::use_iterator uii = CE->use_begin(), - uee = CE->use_end(); uii != uee; ++uii) - if (CallInst* CI = dyn_cast(uii)) - if(CI->getCalledValue() == CE) { - // add to a worklist to process - worklist.push_back(CI); - } - } - } - - // process the worklist - while(!worklist.empty()) { - CallInst *CI = worklist.back(); - worklist.pop_back(); - Function *F = cast(CI->getCalledValue()->stripPointerCasts()); - // Only continue, if we are passing the exact number of arguments - if(F->arg_size() != (CI->getNumOperands()-1)) - continue; - // Only continue if we are getting the same return type value - // Or we can discard the returned value. - if(F->getReturnType() != CI->getType()) { - if(!CI->use_empty()) - continue; - } - // Check if the parameters passed match the expected types of the - // formal arguments - bool change = true; - unsigned arg_count = 1; - for (Function::arg_iterator ii = F->arg_begin(), ee = F->arg_end();ii != ee; ++ii,arg_count++) { - if(ii->getType() != CI->getOperand(arg_count)->getType()) { - change = false; - break; - } - } - - if(change) { - // if we want to ignore the returned value, create a new CallInst - SmallVector Args; - for(unsigned j =1;jgetNumOperands();j++) { - Args.push_back(CI->getOperand(j)); - } - CallInst *CINew = CallInst::Create(F, Args.begin(), Args.end(), "", CI); - if(F->getReturnType() == CI->getType()){ // else means no uses - CI->replaceAllUsesWith(CINew); - } - DEBUG(errs() << "VA:"); - DEBUG(errs() << "ERASE:"); - DEBUG(CI->dump()); - DEBUG(errs() << "VA:"); - DEBUG(errs() << "ADDED:"); - DEBUG(CINew->dump()); - CI->eraseFromParent(); - numSimplified++; - } - } - return (numSimplified > 0 ); -} - -// Pass ID variable -char VarArgsFunc::ID = 0; - -// Register the Pass -static RegisterPass -X("varargsfunc", "Optimize non-varargs to varargs function casts"); From aggarwa4 at illinois.edu Wed May 18 15:24:50 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 18 May 2011 20:24:50 -0000 Subject: [llvm-commits] [poolalloc] r131563 - /poolalloc/trunk/test/TEST.types.Makefile Message-ID: <20110518202450.8AC342A6C12C@llvm.org> Author: aggarwa4 Date: Wed May 18 15:24:50 2011 New Revision: 131563 URL: http://llvm.org/viewvc/llvm-project?rev=131563&view=rev Log: Remove references to varargsfunc. Modified: poolalloc/trunk/test/TEST.types.Makefile Modified: poolalloc/trunk/test/TEST.types.Makefile URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.types.Makefile?rev=131563&r1=131562&r2=131563&view=diff ============================================================================== --- poolalloc/trunk/test/TEST.types.Makefile (original) +++ poolalloc/trunk/test/TEST.types.Makefile Wed May 18 15:24:50 2011 @@ -52,7 +52,7 @@ $(PROGRAMS_TO_TEST:%=Output/%.opt.bc): \ Output/%.opt.bc: Output/%.llvm1.bc $(LOPT) $(ASSIST_SO) - -$(RUNOPT) -load $(ASSIST_SO) -disable-opt -info-output-file=$(CURDIR)/$@.info -instnamer -internalize -mem2reg -dce -basiccg -inline -dce -varargsfunc -indclone -funcspec -ipsccp -deadargelim -simplify-gep -die -die -mergearrgep -die -globaldce -simplifycfg -deadargelim -arg-simplify -die -varargsfunc -die -simplifycfg -globaldce -indclone -funcspec -deadargelim -globaldce -die -simplifycfg -gep-expr-arg -deadargelim -die -mergefunc -die -die -mergearrgep -die -globaldce -int2ptrcmp -die -dce -inline -mem2reg -dce -arg-cast -dce -sretpromotion -struct-ret -deadargelim -simplify-ev -simplify-iv -dce -ld-args -gep-expr-arg -deadargelim -mergefunc -dce -stats -time-passes $< -f -o $@ + -$(RUNOPT) -load $(ASSIST_SO) -disable-opt -info-output-file=$(CURDIR)/$@.info -instnamer -internalize -mem2reg -dce -basiccg -inline -dce -arg-cast -indclone -funcspec -ipsccp -deadargelim -simplify-gep -die -die -mergearrgep -die -globaldce -simplifycfg -deadargelim -arg-simplify -die -arg-cast -die -simplifycfg -globaldce -indclone -funcspec -deadargelim -globaldce -die -simplifycfg -gep-expr-arg -deadargelim -die -mergefunc -die -die -mergearrgep -die -globaldce -int2ptrcmp -die -dce -inline -mem2reg -dce -arg-cast -dce -sretpromotion -struct-ret -deadargelim -simplify-ev -simplify-iv -dce -ld-args -gep-expr-arg -deadargelim -mergefunc -dce -stats -time-passes $< -f -o $@ $(PROGRAMS_TO_TEST:%=Output/%.count.bc): \ Output/%.count.bc: Output/%.opt.bc $(LOPT) $(ASSIST_SO) From aggarwa4 at illinois.edu Wed May 18 15:32:28 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 18 May 2011 20:32:28 -0000 Subject: [llvm-commits] [poolalloc] r131564 - in /poolalloc/trunk/lib/AssistDS: SimplifyExtractValue.cpp SimplifyInsertValue.cpp Message-ID: <20110518203228.3097F2A6C12C@llvm.org> Author: aggarwa4 Date: Wed May 18 15:32:28 2011 New Revision: 131564 URL: http://llvm.org/viewvc/llvm-project?rev=131564&view=rev Log: Added some minor comments. Modified: poolalloc/trunk/lib/AssistDS/SimplifyExtractValue.cpp poolalloc/trunk/lib/AssistDS/SimplifyInsertValue.cpp Modified: poolalloc/trunk/lib/AssistDS/SimplifyExtractValue.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/SimplifyExtractValue.cpp?rev=131564&r1=131563&r2=131564&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/SimplifyExtractValue.cpp (original) +++ poolalloc/trunk/lib/AssistDS/SimplifyExtractValue.cpp Wed May 18 15:32:28 2011 @@ -122,6 +122,9 @@ continue; } if (LoadInst * LI = dyn_cast(Agg)) { + // if the Agg value came from a load instruction + // replace the extract value intruction with + // a gep and a load. SmallVector Indices; const Type *Int32Ty = Type::getInt32Ty(M.getContext()); Indices.push_back(Constant::getNullValue(Int32Ty)); @@ -138,7 +141,6 @@ changed = true; numErased++; continue; - } if (InsertValueInst *IV = dyn_cast(Agg)) { bool done = false; @@ -185,7 +187,6 @@ numErased++; changed = true; continue; - } if (exti == exte) { // The extract list is a prefix of the insert list. i.e. replace Modified: poolalloc/trunk/lib/AssistDS/SimplifyInsertValue.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/SimplifyInsertValue.cpp?rev=131564&r1=131563&r2=131564&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/SimplifyInsertValue.cpp (original) +++ poolalloc/trunk/lib/AssistDS/SimplifyInsertValue.cpp Wed May 18 15:32:28 2011 @@ -59,17 +59,20 @@ InsertValueInst *IV = dyn_cast(I++); if(!IV) continue; - //Value *Agg = IV->getAggregateOperand(); + // Find all insert value instructions. if(IV->getNumUses() != 1) continue; + // Check that its only use is a StoreInst StoreInst *SI = dyn_cast(IV->use_begin()); if(!SI) continue; + // Check that it is the stored value if(SI->getOperand(0) != IV) continue; changed = true; numErased++; do { + // replace by a series of gep/stores SmallVector Indices; const Type *Int32Ty = Type::getInt32Ty(M.getContext()); Indices.push_back(Constant::getNullValue(Int32Ty)); @@ -84,7 +87,6 @@ } while(IV); worklist.push_back(SI); - } } } From johnny.chen at apple.com Wed May 18 15:32:41 2011 From: johnny.chen at apple.com (Johnny Chen) Date: Wed, 18 May 2011 20:32:41 -0000 Subject: [llvm-commits] [llvm] r131565 - in /llvm/trunk: lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h test/MC/Disassembler/ARM/thumb-tests.txt Message-ID: <20110518203241.A66C52A6C12C@llvm.org> Author: johnny Date: Wed May 18 15:32:41 2011 New Revision: 131565 URL: http://llvm.org/viewvc/llvm-project?rev=131565&view=rev Log: Disassembly of tBcc was wrongly adding 4 to the SignExtend'ed imm8:'0' immediate operand. Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=131565&r1=131564&r2=131565&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Wed May 18 15:32:41 2011 @@ -957,7 +957,7 @@ unsigned Imm8 = getT1Imm8(insn); MI.addOperand(MCOperand::CreateImm( - Opcode == ARM::tBcc ? SignExtend32<9>(Imm8 << 1) + 4 + Opcode == ARM::tBcc ? SignExtend32<9>(Imm8 << 1) : (int)Imm8)); // Predicate operands by ARMBasicMCBuilder::TryPredicateAndSBitModifier(). Modified: llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt?rev=131565&r1=131564&r2=131565&view=diff ============================================================================== --- llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt (original) +++ llvm/trunk/test/MC/Disassembler/ARM/thumb-tests.txt Wed May 18 15:32:41 2011 @@ -262,3 +262,6 @@ # CHECK: nop.w 0xaf 0xf3 0x00 0x80 + +# CHECK: bne #24 +0x0c 0xd1 From dpatel at apple.com Wed May 18 15:35:38 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 20:35:38 -0000 Subject: [llvm-commits] [llvm] r131566 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110518203538.ACC392A6C12C@llvm.org> Author: dpatel Date: Wed May 18 15:35:38 2011 New Revision: 131566 URL: http://llvm.org/viewvc/llvm-project?rev=131566&view=rev Log: Use IRBuilder while simplifying switch instruction. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131566&r1=131565&r2=131566&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 15:35:38 2011 @@ -57,16 +57,17 @@ BasicBlock *GetValueEqualityComparisonCases(TerminatorInst *TI, std::vector > &Cases); bool SimplifyEqualityComparisonWithOnlyPredecessor(TerminatorInst *TI, - BasicBlock *Pred); + BasicBlock *Pred, + IRBuilder<> &Builder); bool FoldValueComparisonIntoPredecessors(TerminatorInst *TI); bool SimplifyReturn(ReturnInst *RI); bool SimplifyUnwind(UnwindInst *UI, IRBuilder<> &Builder); bool SimplifyUnreachable(UnreachableInst *UI); - bool SimplifySwitch(SwitchInst *SI); + bool SimplifySwitch(SwitchInst *SI, IRBuilder<> &Builder); bool SimplifyIndirectBr(IndirectBrInst *IBI); bool SimplifyUncondBranch(BranchInst *BI, IRBuilder <> &Builder); - bool SimplifyCondBranch(BranchInst *BI); + bool SimplifyCondBranch(BranchInst *BI, IRBuilder <>&Builder); public: explicit SimplifyCFGOpt(const TargetData *td) : TD(td) {} @@ -543,7 +544,8 @@ /// form of jump threading. bool SimplifyCFGOpt:: SimplifyEqualityComparisonWithOnlyPredecessor(TerminatorInst *TI, - BasicBlock *Pred) { + BasicBlock *Pred, + IRBuilder<> &Builder) { Value *PredVal = isValueEqualityComparison(Pred->getTerminator()); if (!PredVal) return false; // Not a value comparison in predecessor. @@ -576,7 +578,7 @@ // uncond br. assert(ThisCases.size() == 1 && "Branch can only have one case!"); // Insert the new branch. - Instruction *NI = BranchInst::Create(ThisDef, TI); + Instruction *NI = Builder.CreateBr(ThisDef); (void) NI; // Remove PHI node entries for the dead edge. @@ -641,7 +643,7 @@ CheckEdge = 0; // Insert the new branch. - Instruction *NI = BranchInst::Create(TheRealDest, TI); + Instruction *NI = Builder.CreateBr(TheRealDest); (void) NI; DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator() @@ -2366,7 +2368,7 @@ /// TurnSwitchRangeIntoICmp - Turns a switch with that contains only a /// integer range comparison into a sub, an icmp and a branch. -static bool TurnSwitchRangeIntoICmp(SwitchInst *SI) { +static bool TurnSwitchRangeIntoICmp(SwitchInst *SI, IRBuilder<> &Builder) { assert(SI->getNumCases() > 2 && "Degenerate switch?"); // Make sure all cases point to the same destination and gather the values. @@ -2393,7 +2395,7 @@ if (!Offset->isNullValue()) Sub = BinaryOperator::CreateAdd(Sub, Offset, Sub->getName()+".off", SI); Value *Cmp = new ICmpInst(SI, ICmpInst::ICMP_ULT, Sub, NumCases, "switch"); - BranchInst::Create(SI->getSuccessor(1), SI->getDefaultDest(), Cmp, SI); + Builder.CreateCondBr(Cmp, SI->getSuccessor(1), SI->getDefaultDest()); // Prune obsolete incoming values off the successor's PHI nodes. for (BasicBlock::iterator BBI = SI->getSuccessor(1)->begin(); @@ -2436,7 +2438,7 @@ return !DeadCases.empty(); } -bool SimplifyCFGOpt::SimplifySwitch(SwitchInst *SI) { +bool SimplifyCFGOpt::SimplifySwitch(SwitchInst *SI, IRBuilder<> &Builder) { // If this switch is too complex to want to look at, ignore it. if (!isValueEqualityComparison(SI)) return false; @@ -2446,7 +2448,7 @@ // If we only have one predecessor, and if it is a branch on this value, // see if that predecessor totally determines the outcome of this switch. if (BasicBlock *OnlyPred = BB->getSinglePredecessor()) - if (SimplifyEqualityComparisonWithOnlyPredecessor(SI, OnlyPred)) + if (SimplifyEqualityComparisonWithOnlyPredecessor(SI, OnlyPred, Builder)) return SimplifyCFG(BB) | true; Value *Cond = SI->getCondition(); @@ -2465,7 +2467,7 @@ return SimplifyCFG(BB) | true; // Try to transform the switch into an icmp and a branch. - if (TurnSwitchRangeIntoICmp(SI)) + if (TurnSwitchRangeIntoICmp(SI, Builder)) return SimplifyCFG(BB) | true; // Remove unreachable cases. @@ -2536,7 +2538,7 @@ } -bool SimplifyCFGOpt::SimplifyCondBranch(BranchInst *BI) { +bool SimplifyCFGOpt::SimplifyCondBranch(BranchInst *BI, IRBuilder<> &Builder) { BasicBlock *BB = BI->getParent(); // Conditional branch @@ -2545,7 +2547,7 @@ // see if that predecessor totally determines the outcome of this // switch. if (BasicBlock *OnlyPred = BB->getSinglePredecessor()) - if (SimplifyEqualityComparisonWithOnlyPredecessor(BI, OnlyPred)) + if (SimplifyEqualityComparisonWithOnlyPredecessor(BI, OnlyPred, Builder)) return SimplifyCFG(BB) | true; // This block must be empty, except for the setcond inst, if it exists. @@ -2659,16 +2661,17 @@ if (PN->getNumIncomingValues() == 2) Changed |= FoldTwoEntryPHINode(PN, TD, Builder); + Builder.SetInsertPoint(BB->getTerminator()); if (BranchInst *BI = dyn_cast(BB->getTerminator())) { if (BI->isUnconditional()) { if (SimplifyUncondBranch(BI, Builder)) return true; } else { - if (SimplifyCondBranch(BI)) return true; + if (SimplifyCondBranch(BI, Builder)) return true; } } else if (ReturnInst *RI = dyn_cast(BB->getTerminator())) { if (SimplifyReturn(RI)) return true; } else if (SwitchInst *SI = dyn_cast(BB->getTerminator())) { - if (SimplifySwitch(SI)) return true; + if (SimplifySwitch(SI, Builder)) return true; } else if (UnreachableInst *UI = dyn_cast(BB->getTerminator())) { if (SimplifyUnreachable(UI)) return true; From eli.friedman at gmail.com Wed May 18 15:39:27 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 20:39:27 -0000 Subject: [llvm-commits] [llvm] r131567 - in /llvm/trunk: include/llvm/DefaultPasses.h include/llvm/Support/StandardPasses.h lib/Support/StandardPasses.cpp Message-ID: <20110518203927.36DA42A6C12C@llvm.org> Author: efriedma Date: Wed May 18 15:39:27 2011 New Revision: 131567 URL: http://llvm.org/viewvc/llvm-project?rev=131567&view=rev Log: Revert r131556; it's breaking buildbots/clang tests. Modified: llvm/trunk/include/llvm/DefaultPasses.h llvm/trunk/include/llvm/Support/StandardPasses.h llvm/trunk/lib/Support/StandardPasses.cpp Modified: llvm/trunk/include/llvm/DefaultPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DefaultPasses.h?rev=131567&r1=131566&r2=131567&view=diff ============================================================================== --- llvm/trunk/include/llvm/DefaultPasses.h (original) +++ llvm/trunk/include/llvm/DefaultPasses.h Wed May 18 15:39:27 2011 @@ -1,162 +0,0 @@ -//===- llvm/DefaultPasses.h - Default Pass Support code --------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// This file defines the infrastructure for registering the standard pass list. -// This defines sets of standard optimizations that plugins can modify and -// front ends can use. -//===----------------------------------------------------------------------===// - -#ifndef LLVM_DEFAULT_PASS_SUPPORT_H -#define LLVM_DEFAULT_PASS_SUPPORT_H - -namespace llvm { - -class PassManagerBase; - -/// Unique identifiers for the default standard passes. The addresses of -/// these symbols are used to uniquely identify passes from the default list. -namespace DefaultStandardPasses { -extern unsigned char AggressiveDCEID; -extern unsigned char ArgumentPromotionID; -extern unsigned char BasicAliasAnalysisID; -extern unsigned char CFGSimplificationID; -extern unsigned char ConstantMergeID; -extern unsigned char CorrelatedValuePropagationID; -extern unsigned char DeadArgEliminationID; -extern unsigned char DeadStoreEliminationID; -extern unsigned char DeadTypeEliminationID; -extern unsigned char EarlyCSEID; -extern unsigned char FunctionAttrsID; -extern unsigned char FunctionInliningID; -extern unsigned char GVNID; -extern unsigned char GlobalDCEID; -extern unsigned char GlobalOptimizerID; -extern unsigned char GlobalsModRefID; -extern unsigned char IPSCCPID; -extern unsigned char IndVarSimplifyID; -extern unsigned char InlinerPlaceholderID; -extern unsigned char InstructionCombiningID; -extern unsigned char JumpThreadingID; -extern unsigned char LICMID; -extern unsigned char LoopDeletionID; -extern unsigned char LoopIdiomID; -extern unsigned char LoopRotateID; -extern unsigned char LoopUnrollID; -extern unsigned char LoopUnswitchID; -extern unsigned char MemCpyOptID; -extern unsigned char PruneEHID; -extern unsigned char ReassociateID; -extern unsigned char SCCPID; -extern unsigned char ScalarReplAggregatesID; -extern unsigned char SimplifyLibCallsID; -extern unsigned char StripDeadPrototypesID; -extern unsigned char TailCallEliminationID; -extern unsigned char TypeBasedAliasAnalysisID; -} - -/// StandardPass - The class responsible for maintaining the lists of standard -class StandardPass { - friend class RegisterStandardPassLists; - public: - /// Predefined standard sets of passes - enum StandardSet { - AliasAnalysis, - Function, - Module, - LTO - }; - /// Flags to specify whether a pass should be enabled. Passes registered - /// with the standard sets may specify a minimum optimization level and one - /// or more flags that must be set when constructing the set for the pass to - /// be used. - enum OptimizationFlags { - /// Optimize for size was requested. - OptimizeSize = 1<<0, - /// Allow passes which may make global module changes. - UnitAtATime = 1<<1, - /// UnrollLoops - Allow loop unrolling. - UnrollLoops = 1<<2, - /// Allow library calls to be simplified. - SimplifyLibCalls = 1<<3, - /// Whether the module may have code using exceptions. - HaveExceptions = 1<<4, - // Run an inliner pass as part of this set. - RunInliner = 1<<5 - }; - enum OptimizationFlagComponents { - /// The low bits are used to store the optimization level. When requesting - /// passes, this should store the requested optimisation level. When - /// setting passes, this should set the minimum optimization level at which - /// the pass will run. - OptimizationLevelMask=0xf, - /// The maximum optimisation level at which the pass is run. - MaxOptimizationLevelMask=0xf0, - // Flags that must be set - RequiredFlagMask=0xff00, - // Flags that may not be set. - DisallowedFlagMask=0xff0000, - MaxOptimizationLevelShift=4, - RequiredFlagShift=8, - DisallowedFlagShift=16 - }; - /// Returns the optimisation level from a set of flags. - static unsigned OptimizationLevel(unsigned flags) { - return flags & OptimizationLevelMask ; }; - /// Returns the maximum optimization level for this set of flags - static unsigned MaxOptimizationLevel(unsigned flags) { - return (flags & MaxOptimizationLevelMask) >> 4; }; - /// Constructs a set of flags from the specified minimum and maximum - /// optimisation level - static unsigned OptimzationFlags(unsigned minLevel=0, unsigned maxLevel=0xf, - unsigned requiredFlags=0, unsigned disallowedFlags=0) { - return ((minLevel & OptimizationLevelMask) | - ((maxLevel<> RequiredFlagShift; }; - /// Returns the flags that must not be set for this to match - static unsigned DisallowedFlags(unsigned flags) { - return (flags & DisallowedFlagMask) >> DisallowedFlagShift; }; - /// Register a standard pass in the specified set. If flags is non-zero, - /// then the pass will only be returned when the specified flags are set. - template - class RegisterStandardPass { - public: - RegisterStandardPass(StandardSet set, unsigned char *runBefore=0, - unsigned flags=0, unsigned char *ID=0) { - // Use the pass's ID if one is not specified - RegisterDefaultPass(PassInfo::NormalCtor_t(callDefaultCtor), - ID ? ID : (unsigned char*)&passName::ID, runBefore, set, flags); - }; - }; - /// Adds the passes from the specified set to the provided pass manager - static void AddPassesFromSet(PassManagerBase *PM, - StandardSet set, - unsigned flags=0, - bool VerifyEach=false, - Pass *inliner=0); - private: - /// Registers the default passes. This is set by RegisterStandardPassLists - /// and is called lazily. - static void (*RegisterDefaultPasses)(void); - /// Creates the verifier pass that is inserted when a VerifyEach is passed to - /// AddPassesFromSet() - static Pass* (*CreateVerifierPass)(void); - /// Registers the pass - static void RegisterDefaultPass(PassInfo::NormalCtor_t constructor, - unsigned char *newPass, - unsigned char *oldPass, - StandardSet set, - unsigned flags=0); -}; - -} // namespace llvm - -#endif Modified: llvm/trunk/include/llvm/Support/StandardPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=131567&r1=131566&r2=131567&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) +++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed May 18 15:39:27 2011 @@ -20,7 +20,6 @@ #define LLVM_SUPPORT_STANDARDPASSES_H #include "llvm/PassManager.h" -#include "llvm/DefaultPasses.h" #include "llvm/Analysis/Passes.h" #include "llvm/Analysis/Verifier.h" #include "llvm/Transforms/Scalar.h" @@ -28,273 +27,12 @@ namespace llvm { - /// RegisterStandardPassLists solves a circular dependency problem. The - /// default list of passes has to live somewhere. It can't live in the core - /// modules, because these don't link to the libraries that actually define - /// the passes. It's in this header, so that a copy is created in every - /// library that requests the default set, while still allowing plugins to - /// register new passes without requiring them to link anything more than - /// VMCore. - class RegisterStandardPassLists { - public: - RegisterStandardPassLists() { - StandardPass::RegisterDefaultPasses = RegisterStandardPassList; - StandardPass::CreateVerifierPass = CreateVerifierPass; - } - private: - static llvm::Pass *CreateVerifierPass() { return createVerifierPass(); } - /// Passes must be registered with functions that take no arguments, so we have - /// to wrap their existing constructors. - static Pass *createDefaultScalarReplAggregatesPass(void) { - return createScalarReplAggregatesPass(-1, false); - } - static Pass *createDefaultLoopUnswitchPass(void) { - return createLoopUnswitchPass(false); - } - static Pass *createDefaultLoopUnrollPass(void) { - return createLoopUnrollPass(); - } - static Pass *createSizeOptimizingLoopUnswitchPass(void) { - return createLoopUnswitchPass(true); - } - static void RegisterStandardPassList(void) { - // Standard alias analysis passes - - // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that - // BasicAliasAnalysis wins if they disagree. This is intended to help - // support "obvious" type-punning idioms. -#define DEFAULT_ALIAS_ANALYSIS_PASS(pass, flags)\ - StandardPass::RegisterDefaultPass(\ - PassInfo::NormalCtor_t(create ## pass ## Pass),\ - &DefaultStandardPasses::pass ## ID, 0, StandardPass::AliasAnalysis, flags) - DEFAULT_ALIAS_ANALYSIS_PASS(TypeBasedAliasAnalysis, 0); - DEFAULT_ALIAS_ANALYSIS_PASS(BasicAliasAnalysis, 0); -#undef DEFAULT_ALIAS_ANALYSIS_PASS - -#define DEFAULT_FUNCTION_PASS(pass, flags)\ - StandardPass::RegisterDefaultPass(\ - PassInfo::NormalCtor_t(create ## pass ## Pass),\ - &DefaultStandardPasses::pass ## ID, 0, StandardPass::Function, flags) - DEFAULT_FUNCTION_PASS(CFGSimplification, - StandardPass::OptimzationFlags(1)); - DEFAULT_FUNCTION_PASS(ScalarReplAggregates, - StandardPass::OptimzationFlags(1)); - DEFAULT_FUNCTION_PASS(EarlyCSE, StandardPass::OptimzationFlags(1)); -#undef DEFAULT_FUNCTION_PASS - -#define DEFAULT_MODULE_PASS(pass, flags)\ - StandardPass::RegisterDefaultPass(\ - PassInfo::NormalCtor_t(create ## pass ## Pass),\ - &DefaultStandardPasses::pass ## ID, 0, StandardPass::Module, flags) - // Optimize out global vars - DEFAULT_MODULE_PASS(GlobalOptimizer, - StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); - // IP SCCP - DEFAULT_MODULE_PASS(IPSCCP, - StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); - // Dead argument elimination - DEFAULT_MODULE_PASS(DeadArgElimination, - StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); - // Clean up after IPCP & DAE - DEFAULT_MODULE_PASS(InstructionCombining, - StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); - // Clean up after IPCP & DAE - DEFAULT_MODULE_PASS(CFGSimplification, - StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); - - // Remove dead EH info - DEFAULT_MODULE_PASS(PruneEH, StandardPass::OptimzationFlags(0, 0, - StandardPass::UnitAtATime | StandardPass::HaveExceptions)); - // Placeholder that will be replaced by an inliner if one is specified - StandardPass::RegisterDefaultPass(0, - &DefaultStandardPasses::InlinerPlaceholderID, 0, - StandardPass::Module); - // Set readonly/readnone attrs - DEFAULT_MODULE_PASS(FunctionAttrs, StandardPass::OptimzationFlags(0, 0, - StandardPass::UnitAtATime)); - // Scalarize uninlined fn args - DEFAULT_MODULE_PASS(ArgumentPromotion, StandardPass::OptimzationFlags(2)); - // Start of function pass. - // Break up aggregate allocas, using SSAUpdater. - StandardPass::RegisterDefaultPass( - PassInfo::NormalCtor_t(createDefaultScalarReplAggregatesPass), - &DefaultStandardPasses::ScalarReplAggregatesID, 0, - StandardPass::Module); - // Catch trivial redundancies - DEFAULT_MODULE_PASS(EarlyCSE, 0); - // Library Call Optimizations - DEFAULT_MODULE_PASS(SimplifyLibCalls, - StandardPass::OptimzationFlags(0, 0, StandardPass::SimplifyLibCalls)); - // Thread jumps - DEFAULT_MODULE_PASS(JumpThreading, 0); - // Propagate conditionals - DEFAULT_MODULE_PASS(CorrelatedValuePropagation, 0); - // Merge & remove BBs - DEFAULT_MODULE_PASS(CFGSimplification, 0); - // Combine silly seq's - DEFAULT_MODULE_PASS(InstructionCombining, 0); - // Eliminate tail calls - DEFAULT_MODULE_PASS(TailCallElimination, 0); - // Merge & remove BBs - DEFAULT_MODULE_PASS(CFGSimplification, 0); - // Reassociate expressions - DEFAULT_MODULE_PASS(Reassociate, 0); - // Rotate Loop - DEFAULT_MODULE_PASS(LoopRotate, 0); - // Hoist loop invariants - DEFAULT_MODULE_PASS(LICM, 0); - // Optimize for size if the optimzation level is 0-2 - StandardPass::RegisterDefaultPass( - PassInfo::NormalCtor_t(createSizeOptimizingLoopUnswitchPass), - &DefaultStandardPasses::LoopUnswitchID, 0, - StandardPass::Module, - StandardPass::OptimzationFlags(0, 2)); - // Optimize for size if the optimzation level is >2, and OptimizeSize is - // set - StandardPass::RegisterDefaultPass( - PassInfo::NormalCtor_t(createSizeOptimizingLoopUnswitchPass), - &DefaultStandardPasses::LoopUnswitchID, 0, - StandardPass::Module, - StandardPass::OptimzationFlags(3, 0, StandardPass::OptimizeSize)); - // Don't optimize for size if optimisation level is >2 and OptimizeSize - // is not set - StandardPass::RegisterDefaultPass( - PassInfo::NormalCtor_t(createDefaultLoopUnswitchPass), - &DefaultStandardPasses::LoopUnswitchID, 0, - StandardPass::Module, - StandardPass::OptimzationFlags(3, 0, 0, StandardPass::OptimizeSize)); - DEFAULT_MODULE_PASS(InstructionCombining, 0); - // Canonicalize indvars - DEFAULT_MODULE_PASS(IndVarSimplify, 0); - // Recognize idioms like memset. - DEFAULT_MODULE_PASS(LoopIdiom, 0); - // Delete dead loops - DEFAULT_MODULE_PASS(LoopDeletion, 0); - // Unroll small loops - StandardPass::RegisterDefaultPass( - PassInfo::NormalCtor_t(createDefaultLoopUnrollPass), - &DefaultStandardPasses::LoopUnrollID, 0, - StandardPass::Module, - StandardPass::OptimzationFlags(0, 0, StandardPass::UnrollLoops)); - // Remove redundancies - DEFAULT_MODULE_PASS(GVN, StandardPass::OptimzationFlags(2)); - // Remove memcpy / form memset - DEFAULT_MODULE_PASS(MemCpyOpt, 0); - // Constant prop with SCCP - DEFAULT_MODULE_PASS(SCCP, 0); - - // Run instcombine after redundancy elimination to exploit opportunities - // opened up by them. - DEFAULT_MODULE_PASS(InstructionCombining, 0); - // Thread jumps - DEFAULT_MODULE_PASS(JumpThreading, 0); - DEFAULT_MODULE_PASS(CorrelatedValuePropagation, 0); - // Delete dead stores - DEFAULT_MODULE_PASS(DeadStoreElimination, 0); - // Delete dead instructions - DEFAULT_MODULE_PASS(AggressiveDCE, 0); - // Merge & remove BBs - DEFAULT_MODULE_PASS(CFGSimplification, 0); - // Clean up after everything. - DEFAULT_MODULE_PASS(InstructionCombining, 0); - - // Get rid of dead prototypes - DEFAULT_MODULE_PASS(StripDeadPrototypes, - StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); - // Eliminate dead types - DEFAULT_MODULE_PASS(DeadTypeElimination, - StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); - - // GlobalOpt already deletes dead functions and globals, at -O3 try a - // late pass of GlobalDCE. It is capable of deleting dead cycles. - // Remove dead fns and globals. - DEFAULT_MODULE_PASS(GlobalDCE, - StandardPass::OptimzationFlags(3, 0, StandardPass::UnitAtATime)); - // Merge dup global constants - DEFAULT_MODULE_PASS(ConstantMerge, - StandardPass::OptimzationFlags(2, 0, StandardPass::UnitAtATime)); -#undef DEFAULT_MODULE_PASS - -#define DEFAULT_LTO_PASS(pass, flags)\ - StandardPass::RegisterDefaultPass(\ - PassInfo::NormalCtor_t(create ## pass ## Pass), &DefaultStandardPasses::pass ## ID, 0, StandardPass::LTO, flags) - - // LTO passes - - // Propagate constants at call sites into the functions they call. This - // opens opportunities for globalopt (and inlining) by substituting function - // pointers passed as arguments to direct uses of functions. - DEFAULT_LTO_PASS(IPSCCP, 0); - - // Now that we internalized some globals, see if we can hack on them! - DEFAULT_LTO_PASS(GlobalOptimizer, 0); - - // Linking modules together can lead to duplicated global constants, only - // keep one copy of each constant... - DEFAULT_LTO_PASS(ConstantMerge, 0); - - // Remove unused arguments from functions... - DEFAULT_LTO_PASS(DeadArgElimination, 0); - - // Reduce the code after globalopt and ipsccp. Both can open up significant - // simplification opportunities, and both can propagate functions through - // function pointers. When this happens, we often have to resolve varargs - // calls, etc, so let instcombine do this. - DEFAULT_LTO_PASS(InstructionCombining, 0); - - // Inline small functions - DEFAULT_LTO_PASS(FunctionInlining, - StandardPass::OptimzationFlags(0, 0xf, StandardPass::RunInliner)); - // Remove dead EH info. - DEFAULT_LTO_PASS(PruneEH, 0); - // Optimize globals again if we ran the inliner. - DEFAULT_LTO_PASS(GlobalOptimizer, - StandardPass::OptimzationFlags(0, 0xf, StandardPass::RunInliner)); - DEFAULT_LTO_PASS(GlobalDCE, 0); - - // If we didn't decide to inline a function, check to see if we can - // transform it to pass arguments by value instead of by reference. - DEFAULT_LTO_PASS(ArgumentPromotion, 0); - - // The IPO passes may leave cruft around. Clean up after them. - DEFAULT_LTO_PASS(InstructionCombining, 0); - DEFAULT_LTO_PASS(JumpThreading, 0); - // Break up allocas - DEFAULT_LTO_PASS(ScalarReplAggregates, 0); - - // Run a few AA driven optimizations here and now, to cleanup the code. - // Add nocapture. - DEFAULT_LTO_PASS(FunctionAttrs, 0); - // IP alias analysis. - DEFAULT_LTO_PASS(GlobalsModRef, 0); - - // Hoist loop invariants. - DEFAULT_LTO_PASS(LICM, 0); - // Remove redundancies. - DEFAULT_LTO_PASS(GVN, 0); - // Remove dead memcpys. - DEFAULT_LTO_PASS(MemCpyOpt, 0); - // Nuke dead stores. - DEFAULT_LTO_PASS(DeadStoreElimination, 0); - - // Cleanup and simplify the code after the scalar optimizations. - DEFAULT_LTO_PASS(InstructionCombining, 0); - - DEFAULT_LTO_PASS(JumpThreading, 0); - - // Delete basic blocks, which optimization passes may have killed. - DEFAULT_LTO_PASS(CFGSimplification, 0); - - // Now that we have optimized the program, discard unreachable functions. - DEFAULT_LTO_PASS(GlobalDCE, 0); -#undef DEFAULT_LTO_PASS - } - }; - static RegisterStandardPassLists AutoRegister; - - static inline void createStandardAliasAnalysisPasses(PassManagerBase *PM) { - StandardPass::AddPassesFromSet(PM, StandardPass::AliasAnalysis); + // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that + // BasicAliasAnalysis wins if they disagree. This is intended to help + // support "obvious" type-punning idioms. + PM->add(createTypeBasedAliasAnalysisPass()); + PM->add(createBasicAliasAnalysisPass()); } /// createStandardFunctionPasses - Add the standard list of function passes to @@ -304,8 +42,12 @@ /// -O1, etc. static inline void createStandardFunctionPasses(PassManagerBase *PM, unsigned OptimizationLevel) { - StandardPass::AddPassesFromSet(PM, StandardPass::AliasAnalysis); - StandardPass::AddPassesFromSet(PM, StandardPass::Function, OptimizationLevel); + if (OptimizationLevel > 0) { + createStandardAliasAnalysisPasses(PM); + PM->add(createCFGSimplificationPass()); + PM->add(createScalarReplAggregatesPass()); + PM->add(createEarlyCSEPass()); + } } /// createStandardModulePasses - Add the standard list of module passes to the @@ -336,17 +78,84 @@ PM->add(InliningPass); return; } + + if (UnitAtATime) { + PM->add(createGlobalOptimizerPass()); // Optimize out global vars + + PM->add(createIPSCCPPass()); // IP SCCP + PM->add(createDeadArgEliminationPass()); // Dead argument elimination + + PM->add(createInstructionCombiningPass());// Clean up after IPCP & DAE + PM->add(createCFGSimplificationPass()); // Clean up after IPCP & DAE + } + + // Start of CallGraph SCC passes. + if (UnitAtATime && HaveExceptions) + PM->add(createPruneEHPass()); // Remove dead EH info + if (InliningPass) + PM->add(InliningPass); + if (UnitAtATime) + PM->add(createFunctionAttrsPass()); // Set readonly/readnone attrs + if (OptimizationLevel > 2) + PM->add(createArgumentPromotionPass()); // Scalarize uninlined fn args + + // Start of function pass. + // Break up aggregate allocas, using SSAUpdater. + PM->add(createScalarReplAggregatesPass(-1, false)); + PM->add(createEarlyCSEPass()); // Catch trivial redundancies + if (SimplifyLibCalls) + PM->add(createSimplifyLibCallsPass()); // Library Call Optimizations + PM->add(createJumpThreadingPass()); // Thread jumps. + PM->add(createCorrelatedValuePropagationPass()); // Propagate conditionals + PM->add(createCFGSimplificationPass()); // Merge & remove BBs + PM->add(createInstructionCombiningPass()); // Combine silly seq's + + PM->add(createTailCallEliminationPass()); // Eliminate tail calls + PM->add(createCFGSimplificationPass()); // Merge & remove BBs + PM->add(createReassociatePass()); // Reassociate expressions + PM->add(createLoopRotatePass()); // Rotate Loop + PM->add(createLICMPass()); // Hoist loop invariants + PM->add(createLoopUnswitchPass(OptimizeSize || OptimizationLevel < 3)); + PM->add(createInstructionCombiningPass()); + PM->add(createIndVarSimplifyPass()); // Canonicalize indvars + PM->add(createLoopIdiomPass()); // Recognize idioms like memset. + PM->add(createLoopDeletionPass()); // Delete dead loops + if (UnrollLoops) + PM->add(createLoopUnrollPass()); // Unroll small loops + if (OptimizationLevel > 1) + PM->add(createGVNPass()); // Remove redundancies + PM->add(createMemCpyOptPass()); // Remove memcpy / form memset + PM->add(createSCCPPass()); // Constant prop with SCCP + + // Run instcombine after redundancy elimination to exploit opportunities + // opened up by them. + PM->add(createInstructionCombiningPass()); + PM->add(createJumpThreadingPass()); // Thread jumps + PM->add(createCorrelatedValuePropagationPass()); + PM->add(createDeadStoreEliminationPass()); // Delete dead stores + PM->add(createAggressiveDCEPass()); // Delete dead instructions + PM->add(createCFGSimplificationPass()); // Merge & remove BBs + PM->add(createInstructionCombiningPass()); // Clean up after everything. + + if (UnitAtATime) { + PM->add(createStripDeadPrototypesPass()); // Get rid of dead prototypes + PM->add(createDeadTypeEliminationPass()); // Eliminate dead types - StandardPass::AddPassesFromSet(PM, StandardPass::Module, - StandardPass::OptimzationFlags(OptimizationLevel, 0, - (OptimizeSize ? StandardPass::OptimizeSize : 0) | - (UnitAtATime ? StandardPass::UnitAtATime : 0) | - (UnrollLoops ? StandardPass::UnrollLoops : 0) | - (SimplifyLibCalls ? StandardPass::SimplifyLibCalls : 0) | - (HaveExceptions ? StandardPass::HaveExceptions : 0)), - false, - InliningPass); + // GlobalOpt already deletes dead functions and globals, at -O3 try a + // late pass of GlobalDCE. It is capable of deleting dead cycles. + if (OptimizationLevel > 2) + PM->add(createGlobalDCEPass()); // Remove dead fns and globals. + if (OptimizationLevel > 1) + PM->add(createConstantMergePass()); // Merge dup global constants + } + } + + static inline void addOnePass(PassManagerBase *PM, Pass *P, bool AndVerify) { + PM->add(P); + + if (AndVerify) + PM->add(createVerifierPass()); } /// createStandardLTOPasses - Add the standard list of module passes suitable @@ -365,15 +174,70 @@ // Now that composite has been compiled, scan through the module, looking // for a main function. If main is defined, mark all other functions // internal. - if (Internalize) { - PM->add(createInternalizePass(true)); - if (VerifyEach) - PM->add(createVerifierPass()); - } + if (Internalize) + addOnePass(PM, createInternalizePass(true), VerifyEach); + + // Propagate constants at call sites into the functions they call. This + // opens opportunities for globalopt (and inlining) by substituting function + // pointers passed as arguments to direct uses of functions. + addOnePass(PM, createIPSCCPPass(), VerifyEach); + + // Now that we internalized some globals, see if we can hack on them! + addOnePass(PM, createGlobalOptimizerPass(), VerifyEach); + + // Linking modules together can lead to duplicated global constants, only + // keep one copy of each constant... + addOnePass(PM, createConstantMergePass(), VerifyEach); + + // Remove unused arguments from functions... + addOnePass(PM, createDeadArgEliminationPass(), VerifyEach); + + // Reduce the code after globalopt and ipsccp. Both can open up significant + // simplification opportunities, and both can propagate functions through + // function pointers. When this happens, we often have to resolve varargs + // calls, etc, so let instcombine do this. + addOnePass(PM, createInstructionCombiningPass(), VerifyEach); + + // Inline small functions + if (RunInliner) + addOnePass(PM, createFunctionInliningPass(), VerifyEach); + + addOnePass(PM, createPruneEHPass(), VerifyEach); // Remove dead EH info. + // Optimize globals again if we ran the inliner. + if (RunInliner) + addOnePass(PM, createGlobalOptimizerPass(), VerifyEach); + addOnePass(PM, createGlobalDCEPass(), VerifyEach); // Remove dead functions. + + // If we didn't decide to inline a function, check to see if we can + // transform it to pass arguments by value instead of by reference. + addOnePass(PM, createArgumentPromotionPass(), VerifyEach); + + // The IPO passes may leave cruft around. Clean up after them. + addOnePass(PM, createInstructionCombiningPass(), VerifyEach); + addOnePass(PM, createJumpThreadingPass(), VerifyEach); + // Break up allocas + addOnePass(PM, createScalarReplAggregatesPass(), VerifyEach); + + // Run a few AA driven optimizations here and now, to cleanup the code. + addOnePass(PM, createFunctionAttrsPass(), VerifyEach); // Add nocapture. + addOnePass(PM, createGlobalsModRefPass(), VerifyEach); // IP alias analysis. + + addOnePass(PM, createLICMPass(), VerifyEach); // Hoist loop invariants. + addOnePass(PM, createGVNPass(), VerifyEach); // Remove redundancies. + addOnePass(PM, createMemCpyOptPass(), VerifyEach); // Remove dead memcpys. + // Nuke dead stores. + addOnePass(PM, createDeadStoreEliminationPass(), VerifyEach); + + // Cleanup and simplify the code after the scalar optimizations. + addOnePass(PM, createInstructionCombiningPass(), VerifyEach); + + addOnePass(PM, createJumpThreadingPass(), VerifyEach); + + // Delete basic blocks, which optimization passes may have killed. + addOnePass(PM, createCFGSimplificationPass(), VerifyEach); - StandardPass::AddPassesFromSet(PM, StandardPass::LTO, - StandardPass::OptimzationFlags(0, 0, RunInliner ? - StandardPass::RunInliner : 0), VerifyEach); + // Now that we have optimized the program, discard unreachable functions. + addOnePass(PM, createGlobalDCEPass(), VerifyEach); } } Modified: llvm/trunk/lib/Support/StandardPasses.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/StandardPasses.cpp?rev=131567&r1=131566&r2=131567&view=diff ============================================================================== --- llvm/trunk/lib/Support/StandardPasses.cpp (original) +++ llvm/trunk/lib/Support/StandardPasses.cpp Wed May 18 15:39:27 2011 @@ -1,247 +0,0 @@ -//===-- lib/Support/StandardPasses.cpp - Standard pass lists -----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines utility functions for creating a "standard" set of -// optimization passes, so that compilers and tools which use optimization -// passes use the same set of standard passes. -// -// This allows the creation of multiple standard sets, and their later -// modification by plugins and front ends. -// -//===----------------------------------------------------------------------===// - -#include "llvm/PassManager.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/ManagedStatic.h" -#include "llvm/DefaultPasses.h" -#include "llvm/Support/Mutex.h" - -using namespace llvm::DefaultStandardPasses; -using namespace llvm; - -namespace { - -/// Entry in the standard passes list. -struct StandardPassEntry { - /// Function called to create the pass - PassInfo::NormalCtor_t createPass; - /// Unique identifier for this pass - unsigned char *passID; - /// Flags specifying when this pass should be run - unsigned flags; - - StandardPassEntry(PassInfo::NormalCtor_t constructor, unsigned char *ID, - unsigned f) : createPass(constructor), passID(ID), flags(f) {}; -}; - -/// Standard alias analysis passes -static llvm::SmallVector AAPasses; -/// Standard function passes -static llvm::SmallVector FunctionPasses; -/// Standard module passes -static llvm::SmallVector ModulePasses; -/// Standard link-time optimization passes -static llvm::SmallVector LTOPasses; - -/// Entry in the unresolved standard pass list. IF a pass is inserted in front -/// of a pass that is not yet registered in the standard pass list then it is -/// stored in a separate list and resolved later. -struct UnresolvedStandardPass : public StandardPassEntry { - /// The set into which this is stored - StandardPass::StandardSet set; - /// The unique ID of the pass that should follow this one in the sequence - unsigned char *next; - UnresolvedStandardPass(PassInfo::NormalCtor_t constructor, - unsigned char *newPass, - unsigned char *oldPass, - StandardPass::StandardSet s, - unsigned f) : - StandardPassEntry(constructor, newPass, f), set(s), next(oldPass) {} -}; - -/// The passes that can not be inserted into the correct lists yet because of -/// their place in the sequence. -static llvm::SmallVector UnresolvedPasses; - -/// Returns a reference to the pass list for the corresponding set of -/// optimisations. -llvm::SmallVectorImpl& -PassList(StandardPass::StandardSet set) { - switch (set) { - case StandardPass::AliasAnalysis: return AAPasses; - case StandardPass::Function: return FunctionPasses; - case StandardPass::Module: return ModulePasses; - case StandardPass::LTO: return LTOPasses; - } - // We could use a map of standard pass lists to allow definition of new - // default sets - llvm_unreachable("Invalid standard optimization set requested"); -} - -static ManagedStatic > Lock; - -/// Registers the default set of standard passes. This is called lazily when -/// an attempt is made to read or modify the standard pass list -void RegisterDefaultStandardPasses(void(*doRegister)(void)) { - // Only initialize the standard passes once - static volatile bool initialized = false; - if (initialized) return; - - llvm::sys::SmartScopedLock Guard(*Lock); - if (initialized) return; - if (doRegister) { - assert("No passes registered before setting default passes" && - AAPasses.size() == 0 && - FunctionPasses.size() == 0 && - LTOPasses.size() == 0 && - ModulePasses.size() == 0); - - // We must set initialized to true before calling this function, because - // the doRegister() function will probably call RegisterDefaultPasses(), - // which will call this function, and we'd end up with infinite recursion - // and breakage if we didn't. - initialized = true; - doRegister(); - } -} - -} // Anonymous namespace - -void (*StandardPass::RegisterDefaultPasses)(void); -Pass* (*StandardPass::CreateVerifierPass)(void); - -void StandardPass::RegisterDefaultPass(PassInfo::NormalCtor_t constructor, - unsigned char *newPass, - unsigned char *oldPass, - StandardPass::StandardSet set, - unsigned flags) { - // Make sure that the standard sets are already regstered - RegisterDefaultStandardPasses(RegisterDefaultPasses); - // Get the correct list to modify - llvm::SmallVectorImpl& passList = PassList(set); - - // If there is no old pass specified, then we are adding a new final pass, so - // just push it onto the end. - if (!oldPass) { - StandardPassEntry pass(constructor, newPass, flags); - passList.push_back(pass); - return; - } - - // Find the correct place to insert the pass. This is a linear search, but - // this shouldn't be too slow since the SmallVector will store the values in - // a contiguous block of memory. Each entry is just three words of memory, so - // in most cases we are only going to be looking in one or two cache lines. - // The extra memory accesses from a more complex search structure would - // offset any performance gain (unless someone decides to add an insanely - // large set of standard passes to a set) - for (SmallVectorImpl::iterator i=passList.begin(), - e=passList.end() ; i!=e ; ++i) { - if (i->passID == oldPass) { - StandardPassEntry pass(constructor, newPass, flags); - passList.insert(i, pass); - // If we've added a new pass, then there may have gained the ability to - // insert one of the previously unresolved ones. If so, insert the new - // one. - for (SmallVectorImpl::iterator - u=UnresolvedPasses.begin(), eu=UnresolvedPasses.end() ; u!=eu ; ++u){ - if (u->next == newPass && u->set == set) { - UnresolvedStandardPass p = *u; - UnresolvedPasses.erase(u); - RegisterDefaultPass(p.createPass, p.passID, p.next, p.set, p.flags); - } - } - return; - } - } - // If we get to here, then we didn't find the correct place to insert the new - // pass - UnresolvedStandardPass pass(constructor, newPass, oldPass, set, flags); - UnresolvedPasses.push_back(pass); -} - -void StandardPass::AddPassesFromSet(PassManagerBase *PM, - StandardSet set, - unsigned flags, - bool VerifyEach, - Pass *inliner) { - RegisterDefaultStandardPasses(RegisterDefaultPasses); - unsigned level = OptimizationLevel(flags); - flags = RequiredFlags(flags); - llvm::SmallVectorImpl& passList = PassList(set); - - // Add all of the passes from this set - for (SmallVectorImpl::iterator i=passList.begin(), - e=passList.end() ; i!=e ; ++i) { - // Skip passes that don't have conditions that match the ones specified - // here. For a pass to match: - // - Its minimum optimisation level must be less than or equal to the - // specified level. - // - Its maximum optimisation level must be greater than or equal to the - // specified level - // - All of its required flags must be set - // - None of its disallowed flags may be set - if ((level >= OptimizationLevel(i->flags)) && - ((level <= MaxOptimizationLevel(i->flags)) - || MaxOptimizationLevel(i->flags) == 0) && - ((RequiredFlags(i->flags) & flags) == RequiredFlags(i->flags)) && - ((DisallowedFlags(i->flags) & flags) == 0)) { - // This is quite an ugly way of allowing us to specify an inliner pass to - // insert. Ideally, we'd replace this with a general mechanism allowing - // callers to replace arbitrary passes in the list. - Pass *p = 0; - if (&InlinerPlaceholderID == i->passID) { - p = inliner; - } else if (i->createPass) - p = i->createPass(); - if (p) { - PM->add(p); - if (VerifyEach) - PM->add(CreateVerifierPass()); - } - } - } -} - -unsigned char DefaultStandardPasses::AggressiveDCEID; -unsigned char DefaultStandardPasses::ArgumentPromotionID; -unsigned char DefaultStandardPasses::BasicAliasAnalysisID; -unsigned char DefaultStandardPasses::CFGSimplificationID; -unsigned char DefaultStandardPasses::ConstantMergeID; -unsigned char DefaultStandardPasses::CorrelatedValuePropagationID; -unsigned char DefaultStandardPasses::DeadArgEliminationID; -unsigned char DefaultStandardPasses::DeadStoreEliminationID; -unsigned char DefaultStandardPasses::DeadTypeEliminationID; -unsigned char DefaultStandardPasses::EarlyCSEID; -unsigned char DefaultStandardPasses::FunctionAttrsID; -unsigned char DefaultStandardPasses::FunctionInliningID; -unsigned char DefaultStandardPasses::GVNID; -unsigned char DefaultStandardPasses::GlobalDCEID; -unsigned char DefaultStandardPasses::GlobalOptimizerID; -unsigned char DefaultStandardPasses::GlobalsModRefID; -unsigned char DefaultStandardPasses::IPSCCPID; -unsigned char DefaultStandardPasses::IndVarSimplifyID; -unsigned char DefaultStandardPasses::InlinerPlaceholderID; -unsigned char DefaultStandardPasses::InstructionCombiningID; -unsigned char DefaultStandardPasses::JumpThreadingID; -unsigned char DefaultStandardPasses::LICMID; -unsigned char DefaultStandardPasses::LoopDeletionID; -unsigned char DefaultStandardPasses::LoopIdiomID; -unsigned char DefaultStandardPasses::LoopRotateID; -unsigned char DefaultStandardPasses::LoopUnrollID; -unsigned char DefaultStandardPasses::LoopUnswitchID; -unsigned char DefaultStandardPasses::MemCpyOptID; -unsigned char DefaultStandardPasses::PruneEHID; -unsigned char DefaultStandardPasses::ReassociateID; -unsigned char DefaultStandardPasses::SCCPID; -unsigned char DefaultStandardPasses::ScalarReplAggregatesID; -unsigned char DefaultStandardPasses::SimplifyLibCallsID; -unsigned char DefaultStandardPasses::StripDeadPrototypesID; -unsigned char DefaultStandardPasses::TailCallEliminationID; -unsigned char DefaultStandardPasses::TypeBasedAliasAnalysisID; From eli.friedman at gmail.com Wed May 18 15:46:00 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 13:46:00 -0700 Subject: [llvm-commits] [llvm] r131556 - in /llvm/trunk: include/llvm/DefaultPasses.h include/llvm/Support/StandardPasses.h lib/Support/StandardPasses.cpp In-Reply-To: <20110518190041.A1B5E2A6C12C@llvm.org> References: <20110518190041.A1B5E2A6C12C@llvm.org> Message-ID: Reverted in r131567; this is breaking clang tests. See, for example, the failure on http://google1.osuosl.org:8011/builders/clang-x86_64-darwin10-cross-mingw32/builds/452 . -Eli On Wed, May 18, 2011 at 12:00 PM, David Chisnall wrote: > Author: theraven > Date: Wed May 18 14:00:41 2011 > New Revision: 131556 > > URL: http://llvm.org/viewvc/llvm-project?rev=131556&view=rev > Log: > Second pass at allowing plugins to modify default passes. ?This time without bonus inter-library dependencies. > > > Added: > ? ?llvm/trunk/include/llvm/DefaultPasses.h > ? ?llvm/trunk/lib/Support/StandardPasses.cpp > Modified: > ? ?llvm/trunk/include/llvm/Support/StandardPasses.h > > Added: llvm/trunk/include/llvm/DefaultPasses.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DefaultPasses.h?rev=131556&view=auto > ============================================================================== > --- llvm/trunk/include/llvm/DefaultPasses.h (added) > +++ llvm/trunk/include/llvm/DefaultPasses.h Wed May 18 14:00:41 2011 > @@ -0,0 +1,162 @@ > +//===- llvm/DefaultPasses.h - Default Pass Support code --------*- C++ -*-===// > +// > +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// This file defines the infrastructure for registering the standard pass list. > +// This defines sets of standard optimizations that plugins can modify and > +// front ends can use. > +//===----------------------------------------------------------------------===// > + > +#ifndef LLVM_DEFAULT_PASS_SUPPORT_H > +#define LLVM_DEFAULT_PASS_SUPPORT_H > + > +namespace llvm { > + > +class PassManagerBase; > + > +/// Unique identifiers for the default standard passes. ?The addresses of > +/// these symbols are used to uniquely identify passes from the default list. > +namespace DefaultStandardPasses { > +extern unsigned char AggressiveDCEID; > +extern unsigned char ArgumentPromotionID; > +extern unsigned char BasicAliasAnalysisID; > +extern unsigned char CFGSimplificationID; > +extern unsigned char ConstantMergeID; > +extern unsigned char CorrelatedValuePropagationID; > +extern unsigned char DeadArgEliminationID; > +extern unsigned char DeadStoreEliminationID; > +extern unsigned char DeadTypeEliminationID; > +extern unsigned char EarlyCSEID; > +extern unsigned char FunctionAttrsID; > +extern unsigned char FunctionInliningID; > +extern unsigned char GVNID; > +extern unsigned char GlobalDCEID; > +extern unsigned char GlobalOptimizerID; > +extern unsigned char GlobalsModRefID; > +extern unsigned char IPSCCPID; > +extern unsigned char IndVarSimplifyID; > +extern unsigned char InlinerPlaceholderID; > +extern unsigned char InstructionCombiningID; > +extern unsigned char JumpThreadingID; > +extern unsigned char LICMID; > +extern unsigned char LoopDeletionID; > +extern unsigned char LoopIdiomID; > +extern unsigned char LoopRotateID; > +extern unsigned char LoopUnrollID; > +extern unsigned char LoopUnswitchID; > +extern unsigned char MemCpyOptID; > +extern unsigned char PruneEHID; > +extern unsigned char ReassociateID; > +extern unsigned char SCCPID; > +extern unsigned char ScalarReplAggregatesID; > +extern unsigned char SimplifyLibCallsID; > +extern unsigned char StripDeadPrototypesID; > +extern unsigned char TailCallEliminationID; > +extern unsigned char TypeBasedAliasAnalysisID; > +} > + > +/// StandardPass - The class responsible for maintaining the lists of standard > +class StandardPass { > + ?friend class RegisterStandardPassLists; > + ?public: > + ?/// Predefined standard sets of passes > + ?enum StandardSet { > + ? ?AliasAnalysis, > + ? ?Function, > + ? ?Module, > + ? ?LTO > + ?}; > + ?/// Flags to specify whether a pass should be enabled. ?Passes registered > + ?/// with the standard sets may specify a minimum optimization level and one > + ?/// or more flags that must be set when constructing the set for the pass to > + ?/// be used. > + ?enum OptimizationFlags { > + ? ?/// Optimize for size was requested. > + ? ?OptimizeSize = 1<<0, > + ? ?/// Allow passes which may make global module changes. > + ? ?UnitAtATime = 1<<1, > + ? ?/// UnrollLoops - Allow loop unrolling. > + ? ?UnrollLoops = 1<<2, > + ? ?/// Allow library calls to be simplified. > + ? ?SimplifyLibCalls = 1<<3, > + ? ?/// Whether the module may have code using exceptions. > + ? ?HaveExceptions = 1<<4, > + ? ?// Run an inliner pass as part of this set. > + ? ?RunInliner = 1<<5 > + ?}; > + ?enum OptimizationFlagComponents { > + ? ?/// The low bits are used to store the optimization level. ?When requesting > + ? ?/// passes, this should store the requested optimisation level. ?When > + ? ?/// setting passes, this should set the minimum optimization level at which > + ? ?/// the pass will run. > + ? ?OptimizationLevelMask=0xf, > + ? ?/// The maximum optimisation level at which the pass is run. > + ? ?MaxOptimizationLevelMask=0xf0, > + ? ?// Flags that must be set > + ? ?RequiredFlagMask=0xff00, > + ? ?// Flags that may not be set. > + ? ?DisallowedFlagMask=0xff0000, > + ? ?MaxOptimizationLevelShift=4, > + ? ?RequiredFlagShift=8, > + ? ?DisallowedFlagShift=16 > + ?}; > + ?/// Returns the optimisation level from a set of flags. > + ?static unsigned OptimizationLevel(unsigned flags) { > + ? ? ?return flags & OptimizationLevelMask ; }; > + ?/// Returns the maximum optimization level for this set of flags > + ?static unsigned MaxOptimizationLevel(unsigned flags) { > + ? ? ?return (flags & MaxOptimizationLevelMask) >> 4; }; > + ?/// Constructs a set of flags from the specified minimum and maximum > + ?/// optimisation level > + ?static unsigned OptimzationFlags(unsigned minLevel=0, unsigned maxLevel=0xf, > + ? ? ?unsigned requiredFlags=0, unsigned disallowedFlags=0) { > + ? ?return ((minLevel & OptimizationLevelMask) | > + ? ? ? ? ? ?((maxLevel< + ? ? ? ? ? ?| ((requiredFlags< + ? ? ? ? ? ?| ((disallowedFlags< + ?/// Returns the flags that must be set for this to match > + ?static unsigned RequiredFlags(unsigned flags) { > + ? ? ?return (flags & RequiredFlagMask) >> RequiredFlagShift; }; > + ?/// Returns the flags that must not be set for this to match > + ?static unsigned DisallowedFlags(unsigned flags) { > + ? ? ?return (flags & DisallowedFlagMask) >> DisallowedFlagShift; }; > + ?/// Register a standard pass in the specified set. ?If flags is non-zero, > + ?/// then the pass will only be returned when the specified flags are set. > + ?template > + ?class RegisterStandardPass { > + ? ?public: > + ? ?RegisterStandardPass(StandardSet set, unsigned char *runBefore=0, > + ? ? ? ?unsigned flags=0, unsigned char *ID=0) { > + ? ? ?// Use the pass's ID if one is not specified > + ? ? ?RegisterDefaultPass(PassInfo::NormalCtor_t(callDefaultCtor), > + ? ? ? ? ? ? ? ID ? ID : (unsigned char*)&passName::ID, runBefore, set, flags); > + ? ?}; > + ?}; > + ?/// Adds the passes from the specified set to the provided pass manager > + ?static void AddPassesFromSet(PassManagerBase *PM, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StandardSet set, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned flags=0, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool VerifyEach=false, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? Pass *inliner=0); > + ?private: > + ?/// Registers the default passes. ?This is set by RegisterStandardPassLists > + ?/// and is called lazily. > + ?static void (*RegisterDefaultPasses)(void); > + ?/// Creates the verifier pass that is inserted when a VerifyEach is passed to > + ?/// AddPassesFromSet() > + ?static Pass* (*CreateVerifierPass)(void); > + ?/// Registers the pass > + ?static void RegisterDefaultPass(PassInfo::NormalCtor_t constructor, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned char *newPass, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned char *oldPass, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StandardSet set, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned flags=0); > +}; > + > +} // namespace llvm > + > +#endif > > Modified: llvm/trunk/include/llvm/Support/StandardPasses.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=131556&r1=131555&r2=131556&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) > +++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed May 18 14:00:41 2011 > @@ -20,6 +20,7 @@ > ?#define LLVM_SUPPORT_STANDARDPASSES_H > > ?#include "llvm/PassManager.h" > +#include "llvm/DefaultPasses.h" > ?#include "llvm/Analysis/Passes.h" > ?#include "llvm/Analysis/Verifier.h" > ?#include "llvm/Transforms/Scalar.h" > @@ -27,12 +28,273 @@ > > ?namespace llvm { > > + ?/// RegisterStandardPassLists solves a circular dependency problem. ?The > + ?/// default list of passes has to live somewhere. ?It can't live in the core > + ?/// modules, because these don't link to the libraries that actually define > + ?/// the passes. ?It's in this header, so that a copy is created in every > + ?/// library that requests the default set, while still allowing plugins to > + ?/// register new passes without requiring them to link anything more than > + ?/// VMCore. > + ?class RegisterStandardPassLists { > + ? ?public: > + ? ?RegisterStandardPassLists() { > + ? ? ?StandardPass::RegisterDefaultPasses = RegisterStandardPassList; > + ? ? ?StandardPass::CreateVerifierPass = CreateVerifierPass; > + ? ?} > + ? ?private: > + ? ?static llvm::Pass *CreateVerifierPass() { return createVerifierPass(); } > + ? ?/// Passes must be registered with functions that take no arguments, so we have > + ? ?/// to wrap their existing constructors. > + ? ?static Pass *createDefaultScalarReplAggregatesPass(void) { > + ? ? ?return createScalarReplAggregatesPass(-1, false); > + ? ?} > + ? ?static Pass *createDefaultLoopUnswitchPass(void) { > + ? ? ?return createLoopUnswitchPass(false); > + ? ?} > + ? ?static Pass *createDefaultLoopUnrollPass(void) { > + ? ? ?return createLoopUnrollPass(); > + ? ?} > + ? ?static Pass *createSizeOptimizingLoopUnswitchPass(void) { > + ? ? ?return createLoopUnswitchPass(true); > + ? ?} > + ? ?static void RegisterStandardPassList(void) { > + ? ? ?// Standard alias analysis passes > + > + ? ? ?// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that > + ? ? ?// BasicAliasAnalysis wins if they disagree. This is intended to help > + ? ? ?// support "obvious" type-punning idioms. > +#define DEFAULT_ALIAS_ANALYSIS_PASS(pass, flags)\ > + ?StandardPass::RegisterDefaultPass(\ > + ? ?PassInfo::NormalCtor_t(create ## pass ## Pass),\ > + ? ?&DefaultStandardPasses::pass ## ID, 0, StandardPass::AliasAnalysis, flags) > + ? ? ?DEFAULT_ALIAS_ANALYSIS_PASS(TypeBasedAliasAnalysis, 0); > + ? ? ?DEFAULT_ALIAS_ANALYSIS_PASS(BasicAliasAnalysis, 0); > +#undef DEFAULT_ALIAS_ANALYSIS_PASS > + > +#define DEFAULT_FUNCTION_PASS(pass, flags)\ > + ?StandardPass::RegisterDefaultPass(\ > + ? ? ?PassInfo::NormalCtor_t(create ## pass ## Pass),\ > + ? ? ?&DefaultStandardPasses::pass ## ID, 0, StandardPass::Function, flags) > + ? ? ?DEFAULT_FUNCTION_PASS(CFGSimplification, > + ? ? ? ? ?StandardPass::OptimzationFlags(1)); > + ? ? ?DEFAULT_FUNCTION_PASS(ScalarReplAggregates, > + ? ? ? ? ?StandardPass::OptimzationFlags(1)); > + ? ? ?DEFAULT_FUNCTION_PASS(EarlyCSE, StandardPass::OptimzationFlags(1)); > +#undef DEFAULT_FUNCTION_PASS > + > +#define DEFAULT_MODULE_PASS(pass, flags)\ > + ?StandardPass::RegisterDefaultPass(\ > + ? ? ?PassInfo::NormalCtor_t(create ## pass ## Pass),\ > + ? ? ?&DefaultStandardPasses::pass ## ID, 0, StandardPass::Module, flags) > + ? ? ?// Optimize out global vars > + ? ? ?DEFAULT_MODULE_PASS(GlobalOptimizer, > + ? ? ? ? ?StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); > + ? ? ?// IP SCCP > + ? ? ?DEFAULT_MODULE_PASS(IPSCCP, > + ? ? ? ? ?StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); > + ? ? ?// Dead argument elimination > + ? ? ?DEFAULT_MODULE_PASS(DeadArgElimination, > + ? ? ? ? ?StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); > + ? ? ?// Clean up after IPCP & DAE > + ? ? ?DEFAULT_MODULE_PASS(InstructionCombining, > + ? ? ? ? ?StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); > + ? ? ?// Clean up after IPCP & DAE > + ? ? ?DEFAULT_MODULE_PASS(CFGSimplification, > + ? ? ? ? ?StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); > + > + ? ? ?// Remove dead EH info > + ? ? ?DEFAULT_MODULE_PASS(PruneEH, StandardPass::OptimzationFlags(0, 0, > + ? ? ? ? ? ?StandardPass::UnitAtATime | StandardPass::HaveExceptions)); > + ? ? ?// Placeholder that will be replaced by an inliner if one is specified > + ? ? ?StandardPass::RegisterDefaultPass(0, > + ? ? ? ?&DefaultStandardPasses::InlinerPlaceholderID, 0, > + ? ? ? ?StandardPass::Module); > + ? ? ?// Set readonly/readnone attrs > + ? ? ?DEFAULT_MODULE_PASS(FunctionAttrs, StandardPass::OptimzationFlags(0, 0, > + ? ? ? ? ? ?StandardPass::UnitAtATime)); > + ? ? ?// Scalarize uninlined fn args > + ? ? ?DEFAULT_MODULE_PASS(ArgumentPromotion, StandardPass::OptimzationFlags(2)); > + ? ? ?// Start of function pass. > + ? ? ?// Break up aggregate allocas, using SSAUpdater. > + ? ? ?StandardPass::RegisterDefaultPass( > + ? ? ? ? ?PassInfo::NormalCtor_t(createDefaultScalarReplAggregatesPass), > + ? ? ? ? ?&DefaultStandardPasses::ScalarReplAggregatesID, 0, > + ? ? ? ? ?StandardPass::Module); > + ? ? ?// Catch trivial redundancies > + ? ? ?DEFAULT_MODULE_PASS(EarlyCSE, 0); > + ? ? ?// Library Call Optimizations > + ? ? ?DEFAULT_MODULE_PASS(SimplifyLibCalls, > + ? ? ? ? ?StandardPass::OptimzationFlags(0, 0, StandardPass::SimplifyLibCalls)); > + ? ? ?// Thread jumps > + ? ? ?DEFAULT_MODULE_PASS(JumpThreading, 0); > + ? ? ?// Propagate conditionals > + ? ? ?DEFAULT_MODULE_PASS(CorrelatedValuePropagation, 0); > + ? ? ?// Merge & remove BBs > + ? ? ?DEFAULT_MODULE_PASS(CFGSimplification, 0); > + ? ? ?// Combine silly seq's > + ? ? ?DEFAULT_MODULE_PASS(InstructionCombining, 0); > + ? ? ?// Eliminate tail calls > + ? ? ?DEFAULT_MODULE_PASS(TailCallElimination, 0); > + ? ? ?// Merge & remove BBs > + ? ? ?DEFAULT_MODULE_PASS(CFGSimplification, 0); > + ? ? ?// Reassociate expressions > + ? ? ?DEFAULT_MODULE_PASS(Reassociate, 0); > + ? ? ?// Rotate Loop > + ? ? ?DEFAULT_MODULE_PASS(LoopRotate, 0); > + ? ? ?// Hoist loop invariants > + ? ? ?DEFAULT_MODULE_PASS(LICM, 0); > + ? ? ?// Optimize for size if the optimzation level is 0-2 > + ? ? ?StandardPass::RegisterDefaultPass( > + ? ? ? ? ?PassInfo::NormalCtor_t(createSizeOptimizingLoopUnswitchPass), > + ? ? ? ? ?&DefaultStandardPasses::LoopUnswitchID, 0, > + ? ? ? ? ?StandardPass::Module, > + ? ? ? ? ?StandardPass::OptimzationFlags(0, 2)); > + ? ? ?// Optimize for size if the optimzation level is >2, and OptimizeSize is > + ? ? ?// set > + ? ? ?StandardPass::RegisterDefaultPass( > + ? ? ? ? ?PassInfo::NormalCtor_t(createSizeOptimizingLoopUnswitchPass), > + ? ? ? ? ?&DefaultStandardPasses::LoopUnswitchID, 0, > + ? ? ? ? ?StandardPass::Module, > + ? ? ? ? ?StandardPass::OptimzationFlags(3, 0, StandardPass::OptimizeSize)); > + ? ? ?// Don't optimize for size if optimisation level is >2 and OptimizeSize > + ? ? ?// is not set > + ? ? ?StandardPass::RegisterDefaultPass( > + ? ? ? ? ?PassInfo::NormalCtor_t(createDefaultLoopUnswitchPass), > + ? ? ? ? ?&DefaultStandardPasses::LoopUnswitchID, 0, > + ? ? ? ? ?StandardPass::Module, > + ? ? ? ? ?StandardPass::OptimzationFlags(3, 0, 0, StandardPass::OptimizeSize)); > + ? ? ?DEFAULT_MODULE_PASS(InstructionCombining, 0); > + ? ? ?// Canonicalize indvars > + ? ? ?DEFAULT_MODULE_PASS(IndVarSimplify, 0); > + ? ? ?// Recognize idioms like memset. > + ? ? ?DEFAULT_MODULE_PASS(LoopIdiom, 0); > + ? ? ?// Delete dead loops > + ? ? ?DEFAULT_MODULE_PASS(LoopDeletion, 0); > + ? ? ?// Unroll small loops > + ? ? ?StandardPass::RegisterDefaultPass( > + ? ? ? ? ?PassInfo::NormalCtor_t(createDefaultLoopUnrollPass), > + ? ? ? ? ?&DefaultStandardPasses::LoopUnrollID, 0, > + ? ? ? ? ?StandardPass::Module, > + ? ? ? ? ? ? ?StandardPass::OptimzationFlags(0, 0, StandardPass::UnrollLoops)); > + ? ? ?// Remove redundancies > + ? ? ?DEFAULT_MODULE_PASS(GVN, StandardPass::OptimzationFlags(2)); > + ? ? ?// Remove memcpy / form memset > + ? ? ?DEFAULT_MODULE_PASS(MemCpyOpt, 0); > + ? ? ?// Constant prop with SCCP > + ? ? ?DEFAULT_MODULE_PASS(SCCP, 0); > + > + ? ? ?// Run instcombine after redundancy elimination to exploit opportunities > + ? ? ?// opened up by them. > + ? ? ?DEFAULT_MODULE_PASS(InstructionCombining, 0); > + ? ? ?// Thread jumps > + ? ? ?DEFAULT_MODULE_PASS(JumpThreading, 0); > + ? ? ?DEFAULT_MODULE_PASS(CorrelatedValuePropagation, 0); > + ? ? ?// Delete dead stores > + ? ? ?DEFAULT_MODULE_PASS(DeadStoreElimination, 0); > + ? ? ?// Delete dead instructions > + ? ? ?DEFAULT_MODULE_PASS(AggressiveDCE, 0); > + ? ? ?// Merge & remove BBs > + ? ? ?DEFAULT_MODULE_PASS(CFGSimplification, 0); > + ? ? ?// Clean up after everything. > + ? ? ?DEFAULT_MODULE_PASS(InstructionCombining, 0); > + > + ? ? ?// Get rid of dead prototypes > + ? ? ?DEFAULT_MODULE_PASS(StripDeadPrototypes, > + ? ? ? ? ? ? ?StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); > + ? ? ?// Eliminate dead types > + ? ? ?DEFAULT_MODULE_PASS(DeadTypeElimination, > + ? ? ? ? ? ? ?StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); > + > + ? ? ?// GlobalOpt already deletes dead functions and globals, at -O3 try a > + ? ? ?// late pass of GlobalDCE. ?It is capable of deleting dead cycles. > + ? ? ?// Remove dead fns and globals. > + ? ? ?DEFAULT_MODULE_PASS(GlobalDCE, > + ? ? ? ? ? ? ?StandardPass::OptimzationFlags(3, 0, StandardPass::UnitAtATime)); > + ? ? ?// Merge dup global constants > + ? ? ?DEFAULT_MODULE_PASS(ConstantMerge, > + ? ? ? ? ? ? ?StandardPass::OptimzationFlags(2, 0, StandardPass::UnitAtATime)); > +#undef DEFAULT_MODULE_PASS > + > +#define DEFAULT_LTO_PASS(pass, flags)\ > + ?StandardPass::RegisterDefaultPass(\ > + ? ? ?PassInfo::NormalCtor_t(create ## pass ## Pass), &DefaultStandardPasses::pass ## ID, 0, StandardPass::LTO, flags) > + > + ? ? ?// LTO passes > + > + ? ? ?// Propagate constants at call sites into the functions they call. ?This > + ? ? ?// opens opportunities for globalopt (and inlining) by substituting function > + ? ? ?// pointers passed as arguments to direct uses of functions. > + ? ? ?DEFAULT_LTO_PASS(IPSCCP, 0); > + > + ? ? ?// Now that we internalized some globals, see if we can hack on them! > + ? ? ?DEFAULT_LTO_PASS(GlobalOptimizer, 0); > + > + ? ? ?// Linking modules together can lead to duplicated global constants, only > + ? ? ?// keep one copy of each constant... > + ? ? ?DEFAULT_LTO_PASS(ConstantMerge, 0); > + > + ? ? ?// Remove unused arguments from functions... > + ? ? ?DEFAULT_LTO_PASS(DeadArgElimination, 0); > + > + ? ? ?// Reduce the code after globalopt and ipsccp. ?Both can open up significant > + ? ? ?// simplification opportunities, and both can propagate functions through > + ? ? ?// function pointers. ?When this happens, we often have to resolve varargs > + ? ? ?// calls, etc, so let instcombine do this. > + ? ? ?DEFAULT_LTO_PASS(InstructionCombining, 0); > + > + ? ? ?// Inline small functions > + ? ? ?DEFAULT_LTO_PASS(FunctionInlining, > + ? ? ? ? ?StandardPass::OptimzationFlags(0, 0xf, StandardPass::RunInliner)); > + ? ? ?// Remove dead EH info. > + ? ? ?DEFAULT_LTO_PASS(PruneEH, 0); > + ? ? ?// Optimize globals again if we ran the inliner. > + ? ? ?DEFAULT_LTO_PASS(GlobalOptimizer, > + ? ? ? ? ?StandardPass::OptimzationFlags(0, 0xf, StandardPass::RunInliner)); > + ? ? ?DEFAULT_LTO_PASS(GlobalDCE, 0); > + > + ? ? ?// If we didn't decide to inline a function, check to see if we can > + ? ? ?// transform it to pass arguments by value instead of by reference. > + ? ? ?DEFAULT_LTO_PASS(ArgumentPromotion, 0); > + > + ? ? ?// The IPO passes may leave cruft around. ?Clean up after them. > + ? ? ?DEFAULT_LTO_PASS(InstructionCombining, 0); > + ? ? ?DEFAULT_LTO_PASS(JumpThreading, 0); > + ? ? ?// Break up allocas > + ? ? ?DEFAULT_LTO_PASS(ScalarReplAggregates, 0); > + > + ? ? ?// Run a few AA driven optimizations here and now, to cleanup the code. > + ? ? ?// Add nocapture. > + ? ? ?DEFAULT_LTO_PASS(FunctionAttrs, 0); > + ? ? ?// IP alias analysis. > + ? ? ?DEFAULT_LTO_PASS(GlobalsModRef, 0); > + > + ? ? ?// Hoist loop invariants. > + ? ? ?DEFAULT_LTO_PASS(LICM, 0); > + ? ? ?// Remove redundancies. > + ? ? ?DEFAULT_LTO_PASS(GVN, 0); > + ? ? ?// Remove dead memcpys. > + ? ? ?DEFAULT_LTO_PASS(MemCpyOpt, 0); > + ? ? ?// Nuke dead stores. > + ? ? ?DEFAULT_LTO_PASS(DeadStoreElimination, 0); > + > + ? ? ?// Cleanup and simplify the code after the scalar optimizations. > + ? ? ?DEFAULT_LTO_PASS(InstructionCombining, 0); > + > + ? ? ?DEFAULT_LTO_PASS(JumpThreading, 0); > + > + ? ? ?// Delete basic blocks, which optimization passes may have killed. > + ? ? ?DEFAULT_LTO_PASS(CFGSimplification, 0); > + > + ? ? ?// Now that we have optimized the program, discard unreachable functions. > + ? ? ?DEFAULT_LTO_PASS(GlobalDCE, 0); > +#undef DEFAULT_LTO_PASS > + ? ?} > + ?}; > + ?static RegisterStandardPassLists AutoRegister; > + > + > ? static inline void createStandardAliasAnalysisPasses(PassManagerBase *PM) { > - ? ?// Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that > - ? ?// BasicAliasAnalysis wins if they disagree. This is intended to help > - ? ?// support "obvious" type-punning idioms. > - ? ?PM->add(createTypeBasedAliasAnalysisPass()); > - ? ?PM->add(createBasicAliasAnalysisPass()); > + ? ?StandardPass::AddPassesFromSet(PM, StandardPass::AliasAnalysis); > ? } > > ? /// createStandardFunctionPasses - Add the standard list of function passes to > @@ -42,12 +304,8 @@ > ? /// -O1, etc. > ? static inline void createStandardFunctionPasses(PassManagerBase *PM, > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned OptimizationLevel) { > - ? ?if (OptimizationLevel > 0) { > - ? ? ?createStandardAliasAnalysisPasses(PM); > - ? ? ?PM->add(createCFGSimplificationPass()); > - ? ? ?PM->add(createScalarReplAggregatesPass()); > - ? ? ?PM->add(createEarlyCSEPass()); > - ? ?} > + ? ?StandardPass::AddPassesFromSet(PM, StandardPass::AliasAnalysis); > + ? ?StandardPass::AddPassesFromSet(PM, StandardPass::Function, OptimizationLevel); > ? } > > ? /// createStandardModulePasses - Add the standard list of module passes to the > @@ -78,84 +336,17 @@ > ? ? ? ? PM->add(InliningPass); > ? ? ? return; > ? ? } > - > - ? ?if (UnitAtATime) { > - ? ? ?PM->add(createGlobalOptimizerPass()); ? ? // Optimize out global vars > - > - ? ? ?PM->add(createIPSCCPPass()); ? ? ? ? ? ? ?// IP SCCP > - ? ? ?PM->add(createDeadArgEliminationPass()); ?// Dead argument elimination > - > - ? ? ?PM->add(createInstructionCombiningPass());// Clean up after IPCP & DAE > - ? ? ?PM->add(createCFGSimplificationPass()); ? // Clean up after IPCP & DAE > - ? ?} > - > - ? ?// Start of CallGraph SCC passes. > - ? ?if (UnitAtATime && HaveExceptions) > - ? ? ?PM->add(createPruneEHPass()); ? ? ? ? ? ? // Remove dead EH info > - ? ?if (InliningPass) > - ? ? ?PM->add(InliningPass); > - ? ?if (UnitAtATime) > - ? ? ?PM->add(createFunctionAttrsPass()); ? ? ? // Set readonly/readnone attrs > - ? ?if (OptimizationLevel > 2) > - ? ? ?PM->add(createArgumentPromotionPass()); ? // Scalarize uninlined fn args > - > - ? ?// Start of function pass. > - ? ?// Break up aggregate allocas, using SSAUpdater. > - ? ?PM->add(createScalarReplAggregatesPass(-1, false)); > - ? ?PM->add(createEarlyCSEPass()); ? ? ? ? ? ? ?// Catch trivial redundancies > - ? ?if (SimplifyLibCalls) > - ? ? ?PM->add(createSimplifyLibCallsPass()); ? ?// Library Call Optimizations > - ? ?PM->add(createJumpThreadingPass()); ? ? ? ? // Thread jumps. > - ? ?PM->add(createCorrelatedValuePropagationPass()); // Propagate conditionals > - ? ?PM->add(createCFGSimplificationPass()); ? ? // Merge & remove BBs > - ? ?PM->add(createInstructionCombiningPass()); ?// Combine silly seq's > - > - ? ?PM->add(createTailCallEliminationPass()); ? // Eliminate tail calls > - ? ?PM->add(createCFGSimplificationPass()); ? ? // Merge & remove BBs > - ? ?PM->add(createReassociatePass()); ? ? ? ? ? // Reassociate expressions > - ? ?PM->add(createLoopRotatePass()); ? ? ? ? ? ?// Rotate Loop > - ? ?PM->add(createLICMPass()); ? ? ? ? ? ? ? ? ?// Hoist loop invariants > - ? ?PM->add(createLoopUnswitchPass(OptimizeSize || OptimizationLevel < 3)); > - ? ?PM->add(createInstructionCombiningPass()); > - ? ?PM->add(createIndVarSimplifyPass()); ? ? ? ?// Canonicalize indvars > - ? ?PM->add(createLoopIdiomPass()); ? ? ? ? ? ? // Recognize idioms like memset. > - ? ?PM->add(createLoopDeletionPass()); ? ? ? ? ?// Delete dead loops > - ? ?if (UnrollLoops) > - ? ? ?PM->add(createLoopUnrollPass()); ? ? ? ? ?// Unroll small loops > - ? ?if (OptimizationLevel > 1) > - ? ? ?PM->add(createGVNPass()); ? ? ? ? ? ? ? ? // Remove redundancies > - ? ?PM->add(createMemCpyOptPass()); ? ? ? ? ? ? // Remove memcpy / form memset > - ? ?PM->add(createSCCPPass()); ? ? ? ? ? ? ? ? ?// Constant prop with SCCP > - > - ? ?// Run instcombine after redundancy elimination to exploit opportunities > - ? ?// opened up by them. > - ? ?PM->add(createInstructionCombiningPass()); > - ? ?PM->add(createJumpThreadingPass()); ? ? ? ? // Thread jumps > - ? ?PM->add(createCorrelatedValuePropagationPass()); > - ? ?PM->add(createDeadStoreEliminationPass()); ?// Delete dead stores > - ? ?PM->add(createAggressiveDCEPass()); ? ? ? ? // Delete dead instructions > - ? ?PM->add(createCFGSimplificationPass()); ? ? // Merge & remove BBs > - ? ?PM->add(createInstructionCombiningPass()); ?// Clean up after everything. > - > - ? ?if (UnitAtATime) { > - ? ? ?PM->add(createStripDeadPrototypesPass()); // Get rid of dead prototypes > - ? ? ?PM->add(createDeadTypeEliminationPass()); // Eliminate dead types > > - ? ? ?// GlobalOpt already deletes dead functions and globals, at -O3 try a > - ? ? ?// late pass of GlobalDCE. ?It is capable of deleting dead cycles. > - ? ? ?if (OptimizationLevel > 2) > - ? ? ? ?PM->add(createGlobalDCEPass()); ? ? ? ? // Remove dead fns and globals. > + ? ?StandardPass::AddPassesFromSet(PM, StandardPass::Module, > + ? ? ?StandardPass::OptimzationFlags(OptimizationLevel, 0, > + ? ? ? ?(OptimizeSize ? StandardPass::OptimizeSize : 0) | > + ? ? ? ?(UnitAtATime ? StandardPass::UnitAtATime : 0) | > + ? ? ? ?(UnrollLoops ? StandardPass::UnrollLoops : 0) | > + ? ? ? ?(SimplifyLibCalls ? StandardPass::SimplifyLibCalls : 0) | > + ? ? ? ?(HaveExceptions ? StandardPass::HaveExceptions : 0)), > + ? ? ?false, > + ? ? ?InliningPass); > > - ? ? ?if (OptimizationLevel > 1) > - ? ? ? ?PM->add(createConstantMergePass()); ? ? ? // Merge dup global constants > - ? ?} > - ?} > - > - ?static inline void addOnePass(PassManagerBase *PM, Pass *P, bool AndVerify) { > - ? ?PM->add(P); > - > - ? ?if (AndVerify) > - ? ? ?PM->add(createVerifierPass()); > ? } > > ? /// createStandardLTOPasses - Add the standard list of module passes suitable > @@ -174,70 +365,15 @@ > ? ? // Now that composite has been compiled, scan through the module, looking > ? ? // for a main function. ?If main is defined, mark all other functions > ? ? // internal. > - ? ?if (Internalize) > - ? ? ?addOnePass(PM, createInternalizePass(true), VerifyEach); > - > - ? ?// Propagate constants at call sites into the functions they call. ?This > - ? ?// opens opportunities for globalopt (and inlining) by substituting function > - ? ?// pointers passed as arguments to direct uses of functions. > - ? ?addOnePass(PM, createIPSCCPPass(), VerifyEach); > - > - ? ?// Now that we internalized some globals, see if we can hack on them! > - ? ?addOnePass(PM, createGlobalOptimizerPass(), VerifyEach); > - > - ? ?// Linking modules together can lead to duplicated global constants, only > - ? ?// keep one copy of each constant... > - ? ?addOnePass(PM, createConstantMergePass(), VerifyEach); > - > - ? ?// Remove unused arguments from functions... > - ? ?addOnePass(PM, createDeadArgEliminationPass(), VerifyEach); > - > - ? ?// Reduce the code after globalopt and ipsccp. ?Both can open up significant > - ? ?// simplification opportunities, and both can propagate functions through > - ? ?// function pointers. ?When this happens, we often have to resolve varargs > - ? ?// calls, etc, so let instcombine do this. > - ? ?addOnePass(PM, createInstructionCombiningPass(), VerifyEach); > - > - ? ?// Inline small functions > - ? ?if (RunInliner) > - ? ? ?addOnePass(PM, createFunctionInliningPass(), VerifyEach); > - > - ? ?addOnePass(PM, createPruneEHPass(), VerifyEach); ? // Remove dead EH info. > - ? ?// Optimize globals again if we ran the inliner. > - ? ?if (RunInliner) > - ? ? ?addOnePass(PM, createGlobalOptimizerPass(), VerifyEach); > - ? ?addOnePass(PM, createGlobalDCEPass(), VerifyEach); // Remove dead functions. > - > - ? ?// If we didn't decide to inline a function, check to see if we can > - ? ?// transform it to pass arguments by value instead of by reference. > - ? ?addOnePass(PM, createArgumentPromotionPass(), VerifyEach); > - > - ? ?// The IPO passes may leave cruft around. ?Clean up after them. > - ? ?addOnePass(PM, createInstructionCombiningPass(), VerifyEach); > - ? ?addOnePass(PM, createJumpThreadingPass(), VerifyEach); > - ? ?// Break up allocas > - ? ?addOnePass(PM, createScalarReplAggregatesPass(), VerifyEach); > - > - ? ?// Run a few AA driven optimizations here and now, to cleanup the code. > - ? ?addOnePass(PM, createFunctionAttrsPass(), VerifyEach); // Add nocapture. > - ? ?addOnePass(PM, createGlobalsModRefPass(), VerifyEach); // IP alias analysis. > - > - ? ?addOnePass(PM, createLICMPass(), VerifyEach); ? ? ?// Hoist loop invariants. > - ? ?addOnePass(PM, createGVNPass(), VerifyEach); ? ? ? // Remove redundancies. > - ? ?addOnePass(PM, createMemCpyOptPass(), VerifyEach); // Remove dead memcpys. > - ? ?// Nuke dead stores. > - ? ?addOnePass(PM, createDeadStoreEliminationPass(), VerifyEach); > - > - ? ?// Cleanup and simplify the code after the scalar optimizations. > - ? ?addOnePass(PM, createInstructionCombiningPass(), VerifyEach); > - > - ? ?addOnePass(PM, createJumpThreadingPass(), VerifyEach); > - > - ? ?// Delete basic blocks, which optimization passes may have killed. > - ? ?addOnePass(PM, createCFGSimplificationPass(), VerifyEach); > + ? ?if (Internalize) { > + ? ? ?PM->add(createInternalizePass(true)); > + ? ? ?if (VerifyEach) > + ? ? ? ?PM->add(createVerifierPass()); > + ? ?} > > - ? ?// Now that we have optimized the program, discard unreachable functions. > - ? ?addOnePass(PM, createGlobalDCEPass(), VerifyEach); > + ? ?StandardPass::AddPassesFromSet(PM, StandardPass::LTO, > + ? ? ?StandardPass::OptimzationFlags(0, 0, RunInliner ? > + ? ? ? ?StandardPass::RunInliner : 0), VerifyEach); > ? } > ?} > > > Added: llvm/trunk/lib/Support/StandardPasses.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/StandardPasses.cpp?rev=131556&view=auto > ============================================================================== > --- llvm/trunk/lib/Support/StandardPasses.cpp (added) > +++ llvm/trunk/lib/Support/StandardPasses.cpp Wed May 18 14:00:41 2011 > @@ -0,0 +1,247 @@ > +//===-- lib/Support/StandardPasses.cpp - Standard pass lists -----*- C++ -*-===// > +// > +// ? ? ? ? ? ? ? ? ? ? The LLVM Compiler Infrastructure > +// > +// This file is distributed under the University of Illinois Open Source > +// License. See LICENSE.TXT for details. > +// > +//===----------------------------------------------------------------------===// > +// > +// This file defines utility functions for creating a "standard" set of > +// optimization passes, so that compilers and tools which use optimization > +// passes use the same set of standard passes. > +// > +// This allows the creation of multiple standard sets, and their later > +// modification by plugins and front ends. > +// > +//===----------------------------------------------------------------------===// > + > +#include "llvm/PassManager.h" > +#include "llvm/Support/ErrorHandling.h" > +#include "llvm/Support/ManagedStatic.h" > +#include "llvm/DefaultPasses.h" > +#include "llvm/Support/Mutex.h" > + > +using namespace llvm::DefaultStandardPasses; > +using namespace llvm; > + > +namespace { > + > +/// Entry in the standard passes list. > +struct StandardPassEntry { > + ?/// Function called to create the pass > + ?PassInfo::NormalCtor_t createPass; > + ?/// Unique identifier for this pass > + ?unsigned char *passID; > + ?/// Flags specifying when this pass should be run > + ?unsigned flags; > + > + ?StandardPassEntry(PassInfo::NormalCtor_t constructor, unsigned char *ID, > + ? ? ?unsigned f) : createPass(constructor), passID(ID), flags(f) {}; > +}; > + > +/// Standard alias analysis passes > +static llvm::SmallVector AAPasses; > +/// Standard function passes > +static llvm::SmallVector FunctionPasses; > +/// Standard module passes > +static llvm::SmallVector ModulePasses; > +/// Standard link-time optimization passes > +static llvm::SmallVector LTOPasses; > + > +/// Entry in the unresolved standard pass list. ?IF a pass is inserted in front > +/// of a pass that is not yet registered in the standard pass list then it is > +/// stored in a separate list and resolved later. > +struct UnresolvedStandardPass : public StandardPassEntry { > + ?/// The set into which this is stored > + ?StandardPass::StandardSet set; > + ?/// The unique ID of the pass that should follow this one in the sequence > + ?unsigned char *next; > + ?UnresolvedStandardPass(PassInfo::NormalCtor_t constructor, > + ? ? ? ? ? ? ? ? ? ? ? ? unsigned char *newPass, > + ? ? ? ? ? ? ? ? ? ? ? ? unsigned char *oldPass, > + ? ? ? ? ? ? ? ? ? ? ? ? StandardPass::StandardSet s, > + ? ? ? ? ? ? ? ? ? ? ? ? unsigned f) : > + ? ?StandardPassEntry(constructor, newPass, f), set(s), next(oldPass) {} > +}; > + > +/// The passes that can not be inserted into the correct lists yet because of > +/// their place in the sequence. > +static llvm::SmallVector UnresolvedPasses; > + > +/// Returns a reference to the pass list for the corresponding set of > +/// optimisations. > +llvm::SmallVectorImpl& > +PassList(StandardPass::StandardSet set) { > + ?switch (set) { > + ? ?case StandardPass::AliasAnalysis: return AAPasses; > + ? ?case StandardPass::Function: return FunctionPasses; > + ? ?case StandardPass::Module: return ModulePasses; > + ? ?case StandardPass::LTO: return LTOPasses; > + ?} > + ?// We could use a map of standard pass lists to allow definition of new > + ?// default sets > + ?llvm_unreachable("Invalid standard optimization set requested"); > +} > + > +static ManagedStatic > Lock; > + > +/// Registers the default set of standard passes. ?This is called lazily when > +/// an attempt is made to read or modify the standard pass list > +void RegisterDefaultStandardPasses(void(*doRegister)(void)) { > + ?// Only initialize the standard passes once > + ?static volatile bool initialized = false; > + ?if (initialized) return; > + > + ?llvm::sys::SmartScopedLock Guard(*Lock); > + ?if (initialized) return; > + ?if (doRegister) { > + ? ?assert("No passes registered before setting default passes" && > + ? ? ? ? ? ?AAPasses.size() == 0 && > + ? ? ? ? ? ?FunctionPasses.size() == 0 && > + ? ? ? ? ? ?LTOPasses.size() == 0 && > + ? ? ? ? ? ?ModulePasses.size() == 0); > + > + ? ?// We must set initialized to true before calling this function, because > + ? ?// the doRegister() function will probably call RegisterDefaultPasses(), > + ? ?// which will call this function, and we'd end up with infinite recursion > + ? ?// and breakage if we didn't. > + ? ?initialized = true; > + ? ?doRegister(); > + ?} > +} > + > +} // Anonymous namespace > + > +void (*StandardPass::RegisterDefaultPasses)(void); > +Pass* (*StandardPass::CreateVerifierPass)(void); > + > +void StandardPass::RegisterDefaultPass(PassInfo::NormalCtor_t constructor, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned char *newPass, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned char *oldPass, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? StandardPass::StandardSet set, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned flags) { > + ?// Make sure that the standard sets are already regstered > + ?RegisterDefaultStandardPasses(RegisterDefaultPasses); > + ?// Get the correct list to modify > + ?llvm::SmallVectorImpl& passList = PassList(set); > + > + ?// If there is no old pass specified, then we are adding a new final pass, so > + ?// just push it onto the end. > + ?if (!oldPass) { > + ? ?StandardPassEntry pass(constructor, newPass, flags); > + ? ?passList.push_back(pass); > + ? ?return; > + ?} > + > + ?// Find the correct place to insert the pass. ?This is a linear search, but > + ?// this shouldn't be too slow since the SmallVector will store the values in > + ?// a contiguous block of memory. ?Each entry is just three words of memory, so > + ?// in most cases we are only going to be looking in one or two cache lines. > + ?// The extra memory accesses from a more complex search structure would > + ?// offset any performance gain (unless someone decides to add an insanely > + ?// large set of standard passes to a set) > + ?for (SmallVectorImpl::iterator i=passList.begin(), > + ? ? ? e=passList.end() ; i!=e ; ++i) { > + ? ?if (i->passID == oldPass) { > + ? ? ?StandardPassEntry pass(constructor, newPass, flags); > + ? ? ?passList.insert(i, pass); > + ? ? ?// If we've added a new pass, then there may have gained the ability to > + ? ? ?// insert one of the previously unresolved ones. ?If so, insert the new > + ? ? ?// one. > + ? ? ?for (SmallVectorImpl::iterator > + ? ? ? ? ?u=UnresolvedPasses.begin(), eu=UnresolvedPasses.end() ; u!=eu ; ++u){ > + ? ? ? ?if (u->next == newPass && u->set == set) { > + ? ? ? ? ?UnresolvedStandardPass p = *u; > + ? ? ? ? ?UnresolvedPasses.erase(u); > + ? ? ? ? ?RegisterDefaultPass(p.createPass, p.passID, p.next, p.set, p.flags); > + ? ? ? ?} > + ? ? ?} > + ? ? ?return; > + ? ?} > + ?} > + ?// If we get to here, then we didn't find the correct place to insert the new > + ?// pass > + ?UnresolvedStandardPass pass(constructor, newPass, oldPass, set, flags); > + ?UnresolvedPasses.push_back(pass); > +} > + > +void StandardPass::AddPassesFromSet(PassManagerBase *PM, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?StandardSet set, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?unsigned flags, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool VerifyEach, > + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?Pass *inliner) { > + ?RegisterDefaultStandardPasses(RegisterDefaultPasses); > + ?unsigned level = OptimizationLevel(flags); > + ?flags = RequiredFlags(flags); > + ?llvm::SmallVectorImpl& passList = PassList(set); > + > + ?// Add all of the passes from this set > + ?for (SmallVectorImpl::iterator i=passList.begin(), > + ? ? ? e=passList.end() ; i!=e ; ++i) { > + ? ?// Skip passes that don't have conditions that match the ones specified > + ? ?// here. ?For a pass to match: > + ? ?// - Its minimum optimisation level must be less than or equal to the > + ? ?// ? specified level. > + ? ?// - Its maximum optimisation level must be greater than or equal to the > + ? ?// ? specified level > + ? ?// - All of its required flags must be set > + ? ?// - None of its disallowed flags may be set > + ? ?if ((level >= OptimizationLevel(i->flags)) && > + ? ? ? ?((level <= MaxOptimizationLevel(i->flags)) > + ? ? ? ? ?|| MaxOptimizationLevel(i->flags) == 0) ?&& > + ? ? ? ?((RequiredFlags(i->flags) & flags) == RequiredFlags(i->flags)) && > + ? ? ? ?((DisallowedFlags(i->flags) & flags) == 0)) { > + ? ? ?// This is quite an ugly way of allowing us to specify an inliner pass to > + ? ? ?// insert. ?Ideally, we'd replace this with a general mechanism allowing > + ? ? ?// callers to replace arbitrary passes in the list. > + ? ? ?Pass *p = 0; > + ? ? ?if (&InlinerPlaceholderID == i->passID) { > + ? ? ? ? ?p = inliner; > + ? ? ?} else if (i->createPass) > + ? ? ? ?p = i->createPass(); > + ? ? ?if (p) { > + ? ? ? ?PM->add(p); > + ? ? ? ?if (VerifyEach) > + ? ? ? ? ?PM->add(CreateVerifierPass()); > + ? ? ?} > + ? ?} > + ?} > +} > + > +unsigned char DefaultStandardPasses::AggressiveDCEID; > +unsigned char DefaultStandardPasses::ArgumentPromotionID; > +unsigned char DefaultStandardPasses::BasicAliasAnalysisID; > +unsigned char DefaultStandardPasses::CFGSimplificationID; > +unsigned char DefaultStandardPasses::ConstantMergeID; > +unsigned char DefaultStandardPasses::CorrelatedValuePropagationID; > +unsigned char DefaultStandardPasses::DeadArgEliminationID; > +unsigned char DefaultStandardPasses::DeadStoreEliminationID; > +unsigned char DefaultStandardPasses::DeadTypeEliminationID; > +unsigned char DefaultStandardPasses::EarlyCSEID; > +unsigned char DefaultStandardPasses::FunctionAttrsID; > +unsigned char DefaultStandardPasses::FunctionInliningID; > +unsigned char DefaultStandardPasses::GVNID; > +unsigned char DefaultStandardPasses::GlobalDCEID; > +unsigned char DefaultStandardPasses::GlobalOptimizerID; > +unsigned char DefaultStandardPasses::GlobalsModRefID; > +unsigned char DefaultStandardPasses::IPSCCPID; > +unsigned char DefaultStandardPasses::IndVarSimplifyID; > +unsigned char DefaultStandardPasses::InlinerPlaceholderID; > +unsigned char DefaultStandardPasses::InstructionCombiningID; > +unsigned char DefaultStandardPasses::JumpThreadingID; > +unsigned char DefaultStandardPasses::LICMID; > +unsigned char DefaultStandardPasses::LoopDeletionID; > +unsigned char DefaultStandardPasses::LoopIdiomID; > +unsigned char DefaultStandardPasses::LoopRotateID; > +unsigned char DefaultStandardPasses::LoopUnrollID; > +unsigned char DefaultStandardPasses::LoopUnswitchID; > +unsigned char DefaultStandardPasses::MemCpyOptID; > +unsigned char DefaultStandardPasses::PruneEHID; > +unsigned char DefaultStandardPasses::ReassociateID; > +unsigned char DefaultStandardPasses::SCCPID; > +unsigned char DefaultStandardPasses::ScalarReplAggregatesID; > +unsigned char DefaultStandardPasses::SimplifyLibCallsID; > +unsigned char DefaultStandardPasses::StripDeadPrototypesID; > +unsigned char DefaultStandardPasses::TailCallEliminationID; > +unsigned char DefaultStandardPasses::TypeBasedAliasAnalysisID; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From aggarwa4 at illinois.edu Wed May 18 15:45:16 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 18 May 2011 20:45:16 -0000 Subject: [llvm-commits] [poolalloc] r131568 - /poolalloc/trunk/lib/AssistDS/GEPExprArgs.cpp Message-ID: <20110518204516.D0EC32A6C12C@llvm.org> Author: aggarwa4 Date: Wed May 18 15:45:16 2011 New Revision: 131568 URL: http://llvm.org/viewvc/llvm-project?rev=131568&view=rev Log: Correctly map attributes when replace a CallInst. Modified: poolalloc/trunk/lib/AssistDS/GEPExprArgs.cpp Modified: poolalloc/trunk/lib/AssistDS/GEPExprArgs.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/GEPExprArgs.cpp?rev=131568&r1=131567&r2=131568&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/GEPExprArgs.cpp (original) +++ poolalloc/trunk/lib/AssistDS/GEPExprArgs.cpp Wed May 18 15:45:16 2011 @@ -108,7 +108,7 @@ &M); Function::arg_iterator NI = NewF->arg_begin(); - NI->setName("Sarg"); + NI->setName("GEParg"); ++NI; DenseMap ValueMap; @@ -116,6 +116,7 @@ for (Function::arg_iterator II = F->arg_begin(); NI != NewF->arg_end(); ++II, ++NI) { ValueMap[II] = NI; NI->setName(II->getName()); + NI->addAttr(F->getAttributes().getParamAttributes(II->getArgNo() + 1)); } // Perform the cloning. SmallVector Returns; @@ -126,16 +127,24 @@ fargs.push_back(ai); } - NewF->setAlignment(F->getAlignment()); + NewF->setAttributes(NewF->getAttributes().addAttr( + 0, F->getAttributes().getRetAttributes())); + NewF->setAttributes(NewF->getAttributes().addAttr( + ~0, F->getAttributes().getFnAttributes())); + //NewF->setAlignment(F->getAlignment()); //Get the point to insert the GEP instr. - NI = NewF->arg_begin(); SmallVector Ops(CI->op_begin()+1, CI->op_end()); Instruction *InsertPoint; - for (BasicBlock::iterator insrt = NewF->front().begin(); isa(InsertPoint = insrt); ++insrt) {;} + for (BasicBlock::iterator insrt = NewF->front().begin(); + isa(InsertPoint = insrt); ++insrt) {;} + NI = NewF->arg_begin(); SmallVector Indices; Indices.append(GEP->op_begin()+1, GEP->op_end()); - GetElementPtrInst *GEP_new = GetElementPtrInst::Create(cast(NI), Indices.begin(), Indices.end(), "", InsertPoint); + GetElementPtrInst *GEP_new = GetElementPtrInst::Create(cast(NI), + Indices.begin(), + Indices.end(), + "", InsertPoint); fargs.at(argNum)->replaceAllUsesWith(GEP_new); unsigned j = argNum + 1; for(; j < CI->getNumOperands();j++) { @@ -143,13 +152,33 @@ fargs.at(j)->replaceAllUsesWith(GEP_new); } + SmallVector AttributesVec; + + // Get the initial attributes of the call + AttrListPtr CallPAL = CI->getAttributes(); + Attributes RAttrs = CallPAL.getRetAttributes(); + Attributes FnAttrs = CallPAL.getFnAttributes(); + SmallVector Args; Args.push_back(GEP->getPointerOperand()); for(unsigned j =1;jgetNumOperands();j++) { Args.push_back(CI->getOperand(j)); + // position in the AttributesVec + if (Attributes Attrs = CallPAL.getParamAttributes(j)) + AttributesVec.push_back(AttributeWithIndex::get(Args.size(), Attrs)); } + // Create the new attributes vec. + if (FnAttrs != Attribute::None) + AttributesVec.push_back(AttributeWithIndex::get(~0, FnAttrs)); + if (RAttrs) + AttributesVec.push_back(AttributeWithIndex::get(0, RAttrs)); + + AttrListPtr NewCallPAL = AttrListPtr::get(AttributesVec.begin(), + AttributesVec.end()); + CallInst *CallI = CallInst::Create(NewF,Args.begin(), Args.end(),"", CI); CallI->setCallingConv(CI->getCallingConv()); + CallI->setAttributes(NewCallPAL); CI->replaceAllUsesWith(CallI); CI->eraseFromParent(); changed = true; From csdavec at swan.ac.uk Wed May 18 15:53:10 2011 From: csdavec at swan.ac.uk (David Chisnall) Date: Wed, 18 May 2011 21:53:10 +0100 Subject: [llvm-commits] [llvm] r131556 - in /llvm/trunk: include/llvm/DefaultPasses.h include/llvm/Support/StandardPasses.h lib/Support/StandardPasses.cpp In-Reply-To: References: <20110518190041.A1B5E2A6C12C@llvm.org> Message-ID: <83CF1029-7421-48C3-A491-50A183986D63@swan.ac.uk> On 18 May 2011, at 21:46, Eli Friedman wrote: > Reverted in r131567; this is breaking clang tests. See, for example, > the failure on http://google1.osuosl.org:8011/builders/clang-x86_64-darwin10-cross-mingw32/builds/452 Do you have any explanation of this? I can't reproduce the test failure - all LLVM and Clang tests pass for me. David From aggarwa4 at illinois.edu Wed May 18 15:50:04 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 18 May 2011 20:50:04 -0000 Subject: [llvm-commits] [poolalloc] r131569 - /poolalloc/trunk/lib/AssistDS/LoadArgs.cpp Message-ID: <20110518205004.338102A6C12C@llvm.org> Author: aggarwa4 Date: Wed May 18 15:50:04 2011 New Revision: 131569 URL: http://llvm.org/viewvc/llvm-project?rev=131569&view=rev Log: Correctly copy attributes when replacing call inst. Modified: poolalloc/trunk/lib/AssistDS/LoadArgs.cpp Modified: poolalloc/trunk/lib/AssistDS/LoadArgs.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/LoadArgs.cpp?rev=131569&r1=131568&r2=131569&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/LoadArgs.cpp (original) +++ poolalloc/trunk/lib/AssistDS/LoadArgs.cpp Wed May 18 15:50:04 2011 @@ -129,7 +129,7 @@ &M); Function::arg_iterator NI = NewF->arg_begin(); - NI->setName("Sarg"); + NI->setName("LDarg"); ++NI; DenseMap ValueMap; @@ -137,6 +137,7 @@ for (Function::arg_iterator II = F->arg_begin(); NI != NewF->arg_end(); ++II, ++NI) { ValueMap[II] = NI; NI->setName(II->getName()); + NI->addAttr(F->getAttributes().getParamAttributes(II->getArgNo() + 1)); } // Perform the cloning. SmallVector Returns; @@ -147,23 +148,44 @@ fargs.push_back(ai); } - NewF->setAlignment(F->getAlignment()); + NewF->setAttributes(NewF->getAttributes().addAttr( + 0, F->getAttributes().getRetAttributes())); + NewF->setAttributes(NewF->getAttributes().addAttr( + ~0, F->getAttributes().getFnAttributes())); //Get the point to insert the GEP instr. - NI = NewF->arg_begin(); SmallVector Ops(CI->op_begin()+1, CI->op_end()); Instruction *InsertPoint; for (BasicBlock::iterator insrt = NewF->front().begin(); isa(InsertPoint = insrt); ++insrt) {;} + NI = NewF->arg_begin(); LoadInst *LI_new = new LoadInst(cast(NI), "", InsertPoint); fargs.at(argNum)->replaceAllUsesWith(LI_new); + SmallVector AttributesVec; + + // Get the initial attributes of the call + AttrListPtr CallPAL = CI->getAttributes(); + Attributes RAttrs = CallPAL.getRetAttributes(); + Attributes FnAttrs = CallPAL.getFnAttributes(); SmallVector Args; Args.push_back(LI->getOperand(0)); for(unsigned j =1;jgetNumOperands();j++) { Args.push_back(CI->getOperand(j)); + // position in the AttributesVec + if (Attributes Attrs = CallPAL.getParamAttributes(j)) + AttributesVec.push_back(AttributeWithIndex::get(Args.size(), Attrs)); } + // Create the new attributes vec. + if (FnAttrs != Attribute::None) + AttributesVec.push_back(AttributeWithIndex::get(~0, FnAttrs)); + if (RAttrs) + AttributesVec.push_back(AttributeWithIndex::get(0, RAttrs)); + + AttrListPtr NewCallPAL = AttrListPtr::get(AttributesVec.begin(), + AttributesVec.end()); CallInst *CallI = CallInst::Create(NewF,Args.begin(), Args.end(),"", CI); CallI->setCallingConv(CI->getCallingConv()); + CallI->setAttributes(NewCallPAL); CI->replaceAllUsesWith(CallI); CI->eraseFromParent(); changed = true; From aggarwa4 at illinois.edu Wed May 18 15:52:42 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 18 May 2011 20:52:42 -0000 Subject: [llvm-commits] [poolalloc] r131570 - in /poolalloc/trunk/lib/AssistDS: GEPExprArgs.cpp LoadArgs.cpp Message-ID: <20110518205242.634782A6C12C@llvm.org> Author: aggarwa4 Date: Wed May 18 15:52:42 2011 New Revision: 131570 URL: http://llvm.org/viewvc/llvm-project?rev=131570&view=rev Log: Minor comments. Modified: poolalloc/trunk/lib/AssistDS/GEPExprArgs.cpp poolalloc/trunk/lib/AssistDS/LoadArgs.cpp Modified: poolalloc/trunk/lib/AssistDS/GEPExprArgs.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/GEPExprArgs.cpp?rev=131570&r1=131569&r2=131570&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/GEPExprArgs.cpp (original) +++ poolalloc/trunk/lib/AssistDS/GEPExprArgs.cpp Wed May 18 15:52:42 2011 @@ -131,7 +131,6 @@ 0, F->getAttributes().getRetAttributes())); NewF->setAttributes(NewF->getAttributes().addAttr( ~0, F->getAttributes().getFnAttributes())); - //NewF->setAlignment(F->getAlignment()); //Get the point to insert the GEP instr. SmallVector Ops(CI->op_begin()+1, CI->op_end()); Instruction *InsertPoint; Modified: poolalloc/trunk/lib/AssistDS/LoadArgs.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/LoadArgs.cpp?rev=131570&r1=131569&r2=131570&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/LoadArgs.cpp (original) +++ poolalloc/trunk/lib/AssistDS/LoadArgs.cpp Wed May 18 15:52:42 2011 @@ -60,7 +60,7 @@ if(CI->hasByValArgument()) continue; - // if the GEP calls a function, that is externally defined, + // if the CallInst calls a function, that is externally defined, // or might be changed, ignore this call site. Function *F = CI->getCalledFunction(); @@ -75,6 +75,7 @@ Function::arg_iterator ai = F->arg_begin(), ae = F->arg_end(); unsigned argNum = 1; for(; argNum < CI->getNumOperands();argNum++, ++ai) { + // do not care about dead arguments if(ai->use_empty()) continue; if(F->paramHasAttr(argNum, Attribute::SExt) || From dpatel at apple.com Wed May 18 15:53:17 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 20:53:17 -0000 Subject: [llvm-commits] [llvm] r131571 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110518205317.B27FF2A6C12C@llvm.org> Author: dpatel Date: Wed May 18 15:53:17 2011 New Revision: 131571 URL: http://llvm.org/viewvc/llvm-project?rev=131571&view=rev Log: Spread use of IRBuilder even more. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131571&r1=131570&r2=131571&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 15:53:17 2011 @@ -59,7 +59,8 @@ bool SimplifyEqualityComparisonWithOnlyPredecessor(TerminatorInst *TI, BasicBlock *Pred, IRBuilder<> &Builder); - bool FoldValueComparisonIntoPredecessors(TerminatorInst *TI); + bool FoldValueComparisonIntoPredecessors(TerminatorInst *TI, + IRBuilder<> &Builder); bool SimplifyReturn(ReturnInst *RI); bool SimplifyUnwind(UnwindInst *UI, IRBuilder<> &Builder); @@ -678,7 +679,8 @@ /// equality comparison instruction (either a switch or a branch on "X == c"). /// See if any of the predecessors of the terminator block are value comparisons /// on the same value. If so, and if safe to do so, fold them together. -bool SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(TerminatorInst *TI) { +bool SimplifyCFGOpt::FoldValueComparisonIntoPredecessors(TerminatorInst *TI, + IRBuilder<> &Builder) { BasicBlock *BB = TI->getParent(); Value *CV = isValueEqualityComparison(TI); // CondVal assert(CV && "Not a comparison?"); @@ -771,17 +773,17 @@ for (unsigned i = 0, e = NewSuccessors.size(); i != e; ++i) AddPredecessorToBlock(NewSuccessors[i], Pred, BB); + Builder.SetInsertPoint(PTI); // Convert pointer to int before we switch. if (CV->getType()->isPointerTy()) { assert(TD && "Cannot switch on pointer without TargetData"); - CV = new PtrToIntInst(CV, TD->getIntPtrType(CV->getContext()), - "magicptr", PTI); - cast(CV)->setDebugLoc(PTI->getDebugLoc()); + CV = Builder.CreatePtrToInt(CV, TD->getIntPtrType(CV->getContext()), + "magicptr"); } // Now that the successors are updated, create the new Switch instruction. - SwitchInst *NewSI = SwitchInst::Create(CV, PredDefault, - PredCases.size(), PTI); + SwitchInst *NewSI = Builder.CreateSwitch(CV, PredDefault, + PredCases.size()); NewSI->setDebugLoc(PTI->getDebugLoc()); for (unsigned i = 0, e = PredCases.size(); i != e; ++i) NewSI->addCase(PredCases[i].first, PredCases[i].second); @@ -2463,7 +2465,7 @@ while (isa(BBI)) ++BBI; if (SI == &*BBI) - if (FoldValueComparisonIntoPredecessors(SI)) + if (FoldValueComparisonIntoPredecessors(SI, Builder)) return SimplifyCFG(BB) | true; // Try to transform the switch into an icmp and a branch. @@ -2557,14 +2559,14 @@ while (isa(I)) ++I; if (&*I == BI) { - if (FoldValueComparisonIntoPredecessors(BI)) + if (FoldValueComparisonIntoPredecessors(BI, Builder)) return SimplifyCFG(BB) | true; } else if (&*I == cast(BI->getCondition())){ ++I; // Ignore dbg intrinsics. while (isa(I)) ++I; - if (&*I == BI && FoldValueComparisonIntoPredecessors(BI)) + if (&*I == BI && FoldValueComparisonIntoPredecessors(BI, Builder)) return SimplifyCFG(BB) | true; } } From cdavis at mines.edu Wed May 18 15:54:10 2011 From: cdavis at mines.edu (Charles Davis) Date: Wed, 18 May 2011 20:54:10 -0000 Subject: [llvm-commits] [llvm] r131572 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/MC/MCAsmStreamer.cpp lib/MC/MCStreamer.cpp Message-ID: <20110518205410.35D332A6C12C@llvm.org> Author: cdavis Date: Wed May 18 15:54:10 2011 New Revision: 131572 URL: http://llvm.org/viewvc/llvm-project?rev=131572&view=rev Log: Add some more Win64 EH directives: - StartChained and EndChained delimit a chained unwind area, which can contain additional operations to be undone if an exception occurs inside of it. - UnwindOnly declares that this function doesn't handle any exceptions. If it has a handler, it's an unwind handler instead of an exception handler. - Lsda declares the location and size of the LSDA, which in the Win64 EH scheme is kept inside the UNWIND_INFO struct. Windows itself ignores the LSDA; it's used by the Language-Specific Handler (the "Personality Function" from DWARF). Modified: llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=131572&r1=131571&r2=131572&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed May 18 15:54:10 2011 @@ -459,6 +459,10 @@ virtual void EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler = 0); virtual void EmitWin64EHEndProc(); + virtual void EmitWin64EHStartChained(); + virtual void EmitWin64EHEndChained(); + virtual void EmitWin64EHUnwindOnly(); + virtual void EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size); virtual void EmitWin64EHPushReg(int64_t Register); virtual void EmitWin64EHSetFrame(int64_t Register, int64_t Offset); virtual void EmitWin64EHAllocStack(int64_t Size); Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=131572&r1=131571&r2=131572&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed May 18 15:54:10 2011 @@ -210,6 +210,10 @@ virtual void EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler = 0); virtual void EmitWin64EHEndProc(); + virtual void EmitWin64EHStartChained(); + virtual void EmitWin64EHEndChained(); + virtual void EmitWin64EHUnwindOnly(); + virtual void EmitWin64EHLsda(cosnt MCSymbol *Sym, int64_t Size); virtual void EmitWin64EHPushReg(int64_t Register); virtual void EmitWin64EHSetFrame(int64_t Register, int64_t Offset); virtual void EmitWin64EHAllocStack(int64_t Size); @@ -942,6 +946,38 @@ EmitEOL(); } +void MCAsmStreamer::EmitWin64EHStartChained() +{ + //MCStreamer::EmitWin64EHStartChained(); + + OS << "\t.w64_startchained"; + EmitEOL(); +} + +void MCAsmStreamer::EmitWin64EHEndChained() +{ + //MCStreamer::EmitWin64EHEndChained(); + + OS << "\t.w64_endchained"; + EmitEOL(); +} + +void MCAsmStreamer::EmitWin64EHUnwindOnly() +{ + //MCStreamer::EmitWin64EHUnwindOnly(); + + OS << "\t.w64_unwind_only"; + EmitEOL(); +} + +void MCAsmStreamer::EmitWin64EHLsda(cosnt MCSymbol *Sym, int64_t Size) +{ + //MCStreamer::EmitWin64EHLsda(Sym, Size); + + OS << "\t.w64_lsda " << *Sym << ", " << Size; + EmitEOL(); +} + void MCAsmStreamer::EmitWin64EHPushReg(int64_t Register) { //MCStreamer::EmitWin64EHPushReg(Register); Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=131572&r1=131571&r2=131572&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Wed May 18 15:54:10 2011 @@ -322,6 +322,30 @@ abort(); } +void MCStreamer::EmitWin64EHStartChained() +{ + errs() << "Not implemented yet\n"; + abort(); +} + +void MCStreamer::EmitWin64EHEndChained() +{ + errs() << "Not implemented yet\n"; + abort(); +} + +void MCStreamer::EmitWin64EHUnwindOnly() +{ + errs() << "Not implemented yet\n"; + abort(); +} + +void MCStreamer::EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size) +{ + errs() << "Not implemented yet\n"; + abort(); +} + void MCStreamer::EmitWin64EHPushReg(int64_t Register) { errs() << "Not implemented yet\n"; From dpatel at apple.com Wed May 18 15:58:47 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 20:58:47 -0000 Subject: [llvm-commits] [llvm] r131575 - /llvm/trunk/include/llvm/Support/IRBuilder.h Message-ID: <20110518205847.CBF8A2A6C12C@llvm.org> Author: dpatel Date: Wed May 18 15:58:47 2011 New Revision: 131575 URL: http://llvm.org/viewvc/llvm-project?rev=131575&view=rev Log: Set debug location while setting insertion point. Modified: llvm/trunk/include/llvm/Support/IRBuilder.h Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=131575&r1=131574&r2=131575&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Wed May 18 15:58:47 2011 @@ -80,6 +80,7 @@ void SetInsertPoint(Instruction *I) { BB = I->getParent(); InsertPt = I; + SetCurrentDebugLocation(I->getDebugLoc()); } /// SetInsertPoint - This specifies that created instructions should be From dpatel at apple.com Wed May 18 16:04:38 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 14:04:38 -0700 Subject: [llvm-commits] [llvm] r131516 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/InstCombine/InstructionCombining.cpp test/Transforms/InstCombine/call.ll In-Reply-To: References: <20110518012827.9FAAB2A6C12C@llvm.org> Message-ID: <0E01649B-8940-4C3E-9FDB-F9946A4BB14B@apple.com> On May 18, 2011, at 12:44 AM, Frits van Bommel wrote: > On Wed, May 18, 2011 at 3:28 AM, Eli Friedman wrote: >> Start trying to make InstCombine preserve more debug info. The idea here is >> to set the debug location on the IRBuilder, which will be then right >> location in most cases. This should magically give many transformations >> debug locations, and fixing places which are missing a debug location will >> usually just means changing the code creating it to use the IRBuilder. > >> // Now that we have an instruction, try combining it to simplify it. >> Builder->SetInsertPoint(I->getParent(), I); >> + Builder->SetCurrentDebugLocation(I->getDebugLoc()); > > This would look even nicer if the IRBuilder::SetInsertPoint() > overloads that take an Instruction* did this automatically :). Good idea! r131575. - Devang > That would also make the migration of other passes to IRBuilder look cleaner. > > IRBuilder users that want a different DebugLoc can always set it manually... From gohman at apple.com Wed May 18 16:02:19 2011 From: gohman at apple.com (Dan Gohman) Date: Wed, 18 May 2011 21:02:19 -0000 Subject: [llvm-commits] [llvm] r131576 - in /llvm/trunk: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll Message-ID: <20110518210219.1AD8A2A6C12C@llvm.org> Author: djg Date: Wed May 18 16:02:18 2011 New Revision: 131576 URL: http://llvm.org/viewvc/llvm-project?rev=131576&view=rev Log: When forming an ICmpZero LSRUse, normalize the non-IV operand of the comparison, so that the resulting expression is fully normalized. This fixes PR9939. Added: llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=131576&r1=131575&r2=131576&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Wed May 18 16:02:18 2011 @@ -2073,6 +2073,10 @@ // x == y --> x - y == 0 const SCEV *N = SE.getSCEV(NV); if (SE.isLoopInvariant(N, L)) { + // S is normalized, so normalize N before folding it into S + // to keep the result normalized. + N = TransformForPostIncUse(Normalize, N, CI, 0, + LF.PostIncLoops, SE, DT); Kind = LSRUse::ICmpZero; S = SE.getMinusSCEV(N, S); } Added: llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll?rev=131576&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll (added) +++ llvm/trunk/test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll Wed May 18 16:02:18 2011 @@ -0,0 +1,91 @@ +; RUN: opt -loop-reduce -S < %s | FileCheck %s +; PR9939 + +; LSR should property handle the post-inc offset when folding the +; non-IV operand of an icmp into the IV. + +; CHECK: %tmp2 = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast +; CHECK: %tmp3 = lshr i64 %tmp2, 1 +; CHECK: %tmp4 = mul i64 %tmp3, 2 +; CHECK: br label %for.body +; CHECK: for.body: +; CHECK: %lsr.iv5 = phi i64 [ %lsr.iv.next, %for.body ], [ %tmp4, %for.body.lr.ph ] +; CHECK: %lsr.iv.next = add i64 %lsr.iv5, -2 +; CHECK: %lsr.iv.next6 = inttoptr i64 %lsr.iv.next to i16* +; CHECK: %cmp27 = icmp eq i16* %lsr.iv.next6, null + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-unknown-linux-gnu" + +%struct.Vector2 = type { i16*, [64 x i16], i32 } + + at .str = private unnamed_addr constant [37 x i8] c"0123456789abcdefghijklmnopqrstuvwxyz\00" + +define void @_Z15IntegerToStringjjR7Vector2(i32 %i, i32 %radix, %struct.Vector2* nocapture %result) nounwind noinline { +entry: + %buffer = alloca [33 x i16], align 16 + %add.ptr = getelementptr inbounds [33 x i16]* %buffer, i64 0, i64 33 + br label %do.body + +do.body: ; preds = %do.body, %entry + %0 = phi i64 [ %indvar.next44, %do.body ], [ 0, %entry ] + %i.addr.0 = phi i32 [ %div, %do.body ], [ %i, %entry ] + %tmp51 = sub i64 32, %0 + %incdec.ptr = getelementptr [33 x i16]* %buffer, i64 0, i64 %tmp51 + %rem = urem i32 %i.addr.0, 10 + %div = udiv i32 %i.addr.0, 10 + %idxprom = zext i32 %rem to i64 + %arrayidx = getelementptr inbounds [37 x i8]* @.str, i64 0, i64 %idxprom + %tmp5 = load i8* %arrayidx, align 1 + %conv = sext i8 %tmp5 to i16 + store i16 %conv, i16* %incdec.ptr, align 2 + %1 = icmp ugt i32 %i.addr.0, 9 + %indvar.next44 = add i64 %0, 1 + br i1 %1, label %do.body, label %do.end + +do.end: ; preds = %do.body + %xap.0 = inttoptr i64 %0 to i1* + %cap.0 = ptrtoint i1* %xap.0 to i64 + %sub.ptr.lhs.cast = ptrtoint i16* %add.ptr to i64 + %sub.ptr.rhs.cast = ptrtoint i16* %incdec.ptr to i64 + %sub.ptr.sub = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast + %sub.ptr.div39 = lshr exact i64 %sub.ptr.sub, 1 + %conv11 = trunc i64 %sub.ptr.div39 to i32 + %mLength = getelementptr inbounds %struct.Vector2* %result, i64 0, i32 2 + %idx.ext21 = bitcast i64 %sub.ptr.div39 to i64 + %incdec.ptr.sum = add i64 %idx.ext21, -1 + %cp.0.sum = sub i64 %incdec.ptr.sum, %0 + %add.ptr22 = getelementptr [33 x i16]* %buffer, i64 1, i64 %cp.0.sum + %cmp2740 = icmp eq i64 %idx.ext21, 0 + br i1 %cmp2740, label %for.end, label %for.body.lr.ph + +for.body.lr.ph: ; preds = %do.end + %tmp16 = load i32* %mLength, align 4 + %mBegin = getelementptr inbounds %struct.Vector2* %result, i64 0, i32 0 + %tmp14 = load i16** %mBegin, align 8 + %tmp48 = zext i32 %tmp16 to i64 + br label %for.body + +for.body: ; preds = %for.body, %for.body.lr.ph + %indvar = phi i64 [ 0, %for.body.lr.ph ], [ %indvar.next, %for.body ] + %tmp46 = add i64 %tmp51, %indvar + %p.042 = getelementptr [33 x i16]* %buffer, i64 0, i64 %tmp46 + %tmp47 = sub i64 %indvar, %0 + %incdec.ptr32 = getelementptr [33 x i16]* %buffer, i64 1, i64 %tmp47 + %tmp49 = add i64 %tmp48, %indvar + %dst.041 = getelementptr i16* %tmp14, i64 %tmp49 + %tmp29 = load i16* %p.042, align 2 + store i16 %tmp29, i16* %dst.041, align 2 + %cmp27 = icmp eq i16* %incdec.ptr32, %add.ptr22 + %indvar.next = add i64 %indvar, 1 + br i1 %cmp27, label %for.end.loopexit, label %for.body + +for.end.loopexit: ; preds = %for.body + br label %for.end + +for.end: ; preds = %for.end.loopexit, %do.end + %tmp38 = load i32* %mLength, align 4 + %add = add i32 %tmp38, %conv11 + store i32 %add, i32* %mLength, align 4 + ret void +} From aggarwa4 at illinois.edu Wed May 18 16:03:46 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 18 May 2011 21:03:46 -0000 Subject: [llvm-commits] [poolalloc] r131577 - /poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp Message-ID: <20110518210346.8B6732A6C12C@llvm.org> Author: aggarwa4 Date: Wed May 18 16:03:46 2011 New Revision: 131577 URL: http://llvm.org/viewvc/llvm-project?rev=131577&view=rev Log: Add correct Attributes when replacing call sites/cloning functions. Modified: poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp Modified: poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp?rev=131577&r1=131576&r2=131577&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp (original) +++ poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp Wed May 18 16:03:46 2011 @@ -47,19 +47,19 @@ // bool StructRet::runOnModule(Module& M) { - std::vector worklistR; + std::vector worklist; for (Module::iterator I = M.begin(); I != M.end(); ++I) if (!I->isDeclaration() && !I->mayBeOverridden()) { if(I->hasAddressTaken()) continue; if(I->getReturnType()->isStructTy()) { - worklistR.push_back(I); + worklist.push_back(I); } } - while(!worklistR.empty()) { - Function *F = worklistR.back(); - worklistR.pop_back(); + while(!worklist.empty()) { + Function *F = worklist.back(); + worklist.pop_back(); const Type *NewArgType = F->getReturnType()->getPointerTo(); // Construct the new Type @@ -79,9 +79,9 @@ NI->setName("ret"); ++NI; for (Function::arg_iterator II = F->arg_begin(); II != F->arg_end(); ++II, ++NI) { - //II->replaceAllUsesWith(NI); ValueMap[II] = NI; NI->setName(II->getName()); + NI->addAttr(F->getAttributes().getParamAttributes(II->getArgNo() + 1)); } // Perform the cloning. SmallVector Returns; @@ -91,15 +91,17 @@ ae= NF->arg_end(); ai != ae; ++ai) { fargs.push_back(ai); } - NF->setAlignment(F->getAlignment()); + NF->setAttributes(NF->getAttributes().addAttr( + 0, F->getAttributes().getRetAttributes())); + NF->setAttributes(NF->getAttributes().addAttr( + ~0, F->getAttributes().getFnAttributes())); + for (Function::iterator B = NF->begin(), FE = NF->end(); B != FE; ++B) { for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { ReturnInst * RI = dyn_cast(I++); if(!RI) continue; new StoreInst(RI->getOperand(0), fargs.at(0), RI); - //ReturnInst::Create(M.getContext(), fargs, RI); - //RI->eraseFromParent(); } } @@ -115,11 +117,32 @@ AllocaInst *AllocaNew = new AllocaInst(F->getReturnType(), 0, "", CI); SmallVector Args; + SmallVector AttributesVec; + + // Get the initial attributes of the call + AttrListPtr CallPAL = CI->getAttributes(); + Attributes RAttrs = CallPAL.getRetAttributes(); + Attributes FnAttrs = CallPAL.getFnAttributes(); + Args.push_back(AllocaNew); for(unsigned j =1;jgetNumOperands();j++) { Args.push_back(CI->getOperand(j)); + // position in the AttributesVec + if (Attributes Attrs = CallPAL.getParamAttributes(j)) + AttributesVec.push_back(AttributeWithIndex::get(Args.size(), Attrs)); } - CallInst::Create(NF, Args.begin(), Args.end(), "", CI); + // Create the new attributes vec. + if (FnAttrs != Attribute::None) + AttributesVec.push_back(AttributeWithIndex::get(~0, FnAttrs)); + if (RAttrs) + AttributesVec.push_back(AttributeWithIndex::get(0, RAttrs)); + + AttrListPtr NewCallPAL = AttrListPtr::get(AttributesVec.begin(), + AttributesVec.end()); + + CallInst *CallI = CallInst::Create(NF, Args.begin(), Args.end(), "", CI); + CallI->setCallingConv(CI->getCallingConv()); + CallI->setAttributes(NewCallPAL); LoadInst *LI = new LoadInst(AllocaNew, "", CI); CI->replaceAllUsesWith(LI); CI->eraseFromParent(); From nlewycky at google.com Wed May 18 16:11:52 2011 From: nlewycky at google.com (Nick Lewycky) Date: Wed, 18 May 2011 14:11:52 -0700 Subject: [llvm-commits] [llvm] r131205 - in /llvm/trunk/lib/MC: ELFObjectWriter.cpp ELFObjectWriter.h In-Reply-To: <20110511225306.571622A6C12C@llvm.org> References: <20110511225306.571622A6C12C@llvm.org> Message-ID: Jason, do you have a testcase for this? I'd like to figure out how GNU as knows what to do so that we can remove the flag, but I can't be sure I'm looking at the right thing without a testcase. On 11 May 2011 15:53, Jason W Kim wrote: > Author: jasonwkim > Date: Wed May 11 17:53:06 2011 > New Revision: 131205 > > URL: http://llvm.org/viewvc/llvm-project?rev=131205&view=rev > Log: > Address the last bit of relocation flag related divergence betweeen > LLVM and binutils. > > With this patch, there are no functional differences between the .o > produced directly from LLVM versus the .s to .o via GNU as, for relocation > tags > at least, for both PIC and non-PIC modes. > > Because some non-PIC reloc tags are used (legally) on PIC, so IsPCRel flag > is > necessary but not sufficient to determine whether the overall codegen mode > is > PIC or not. Why is this necessary? There is an incompatibility of how > relocs > are emitted in the .rodata section. Binutils PIC likes to emit certain > relocs > as section relative offsets. Non-PIC does not do this. > > So I added a hidden switch on the ELFObjectwriter "-arm-elf-force-pic" > which > forces the objectwriter to pretend that all relocs are for PIC mode. > > > Todo: Activate ForceARMElfPIC to true if -relocation-model=pic is selected > on llc. > > Todo: There are probably more issues for PIC mode on ARM/MC/ELF... > > Todo: Existing tests in MC/ARM/elf-reloc*.ll need to be converted over to > .s > tests as well as expanded to cover the gamut. > > > Modified: > llvm/trunk/lib/MC/ELFObjectWriter.cpp > llvm/trunk/lib/MC/ELFObjectWriter.h > > Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=131205&r1=131204&r2=131205&view=diff > > ============================================================================== > --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) > +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed May 11 17:53:06 2011 > @@ -25,6 +25,8 @@ > #include "llvm/Support/ELF.h" > #include "llvm/Target/TargetAsmBackend.h" > #include "llvm/ADT/StringSwitch.h" > +#include "llvm/Support/CommandLine.h" > +#include "llvm/ADT/Statistic.h" > > #include "../Target/X86/X86FixupKinds.h" > #include "../Target/ARM/ARMFixupKinds.h" > @@ -32,6 +34,16 @@ > #include > using namespace llvm; > > +#undef DEBUG_TYPE > +#define DEBUG_TYPE "reloc-info" > + > +// Emulate the wierd behavior of GNU-as for relocation types > +namespace llvm { > +cl::opt > +ForceARMElfPIC("arm-elf-force-pic", cl::Hidden, cl::init(false), > + cl::desc("Force ELF emitter to emit PIC style > relocations")); > +} > + > bool ELFObjectWriter::isFixupKindPCRel(const MCAssembler &Asm, unsigned > Kind) { > const MCFixupKindInfo &FKI = > Asm.getBackend().getFixupKindInfo((MCFixupKind) Kind); > @@ -319,7 +331,9 @@ > > const MCSymbol *ELFObjectWriter::SymbolToReloc(const MCAssembler &Asm, > const MCValue &Target, > - const MCFragment &F) const > { > + const MCFragment &F, > + const MCFixup &Fixup, > + bool IsPCRel) const { > const MCSymbol &Symbol = Target.getSymA()->getSymbol(); > const MCSymbol &ASymbol = Symbol.AliasedSymbol(); > const MCSymbol *Renamed = Renames.lookup(&Symbol); > @@ -342,7 +356,7 @@ > const SectionKind secKind = Section.getKind(); > > if (secKind.isBSS()) > - return ExplicitRelSym(Asm, Target, F, true); > + return ExplicitRelSym(Asm, Target, F, Fixup, IsPCRel); > > if (secKind.isThreadLocal()) { > if (Renamed) > @@ -365,13 +379,14 @@ > > if (Section.getFlags() & ELF::SHF_MERGE) { > if (Target.getConstant() == 0) > - return NULL; > + return ExplicitRelSym(Asm, Target, F, Fixup, IsPCRel); > if (Renamed) > return Renamed; > return &Symbol; > } > > - return ExplicitRelSym(Asm, Target, F, false); > + return ExplicitRelSym(Asm, Target, F, Fixup, IsPCRel); > + > } > > > @@ -390,7 +405,7 @@ > if (!Target.isAbsolute()) { > const MCSymbol &Symbol = Target.getSymA()->getSymbol(); > const MCSymbol &ASymbol = Symbol.AliasedSymbol(); > - RelocSymbol = SymbolToReloc(Asm, Target, *Fragment); > + RelocSymbol = SymbolToReloc(Asm, Target, *Fragment, Fixup, IsPCRel); > > if (const MCSymbolRefExpr *RefB = Target.getSymB()) { > const MCSymbol &SymbolB = RefB->getSymbol(); > @@ -1261,32 +1276,93 @@ > > // In ARM, _MergedGlobals and other most symbols get emitted directly. > // I.e. not as an offset to a section symbol. > -// This code is a first-cut approximation of what ARM/gcc does. > +// This code is an approximation of what ARM/gcc does. > + > +STATISTIC(PCRelCount, "Total number of PIC Relocations"); > +STATISTIC(NonPCRelCount, "Total number of non-PIC relocations"); > > const MCSymbol *ARMELFObjectWriter::ExplicitRelSym(const MCAssembler &Asm, > const MCValue &Target, > const MCFragment &F, > - bool IsBSS) const { > + const MCFixup &Fixup, > + bool IsPCRel) const { > const MCSymbol &Symbol = Target.getSymA()->getSymbol(); > bool EmitThisSym = false; > > - if (IsBSS) { > - EmitThisSym = StringSwitch(Symbol.getName()) > - .Case("_MergedGlobals", true) > - .Default(false); > + const MCSectionELF &Section = > + static_cast(Symbol.getSection()); > + const SectionKind secKind = Section.getKind(); > + const MCSymbolRefExpr::VariantKind Kind = Target.getSymA()->getKind(); > + MCSymbolRefExpr::VariantKind Kind2; > + Kind2 = Target.getSymB() ? Target.getSymB()->getKind() : > + MCSymbolRefExpr::VK_None; > + bool InNormalSection = true; > + unsigned RelocType = 0; > + RelocType = GetRelocTypeInner(Target, Fixup, IsPCRel); > + > + DEBUG(dbgs() << "considering symbol " > + << Section.getSectionName() << "/" > + << Symbol.getName() << "/" > + << " Rel:" << (unsigned)RelocType > + << " Kind: " << (int)Kind << "/" << (int)Kind2 > + << " Tmp:" > + << Symbol.isAbsolute() << "/" << Symbol.isDefined() << "/" > + << Symbol.isVariable() << "/" << Symbol.isTemporary() > + << " Counts:" << PCRelCount << "/" << NonPCRelCount << "\n"); > + > + if (IsPCRel || ForceARMElfPIC) { ++PCRelCount; > + switch (RelocType) { > + default: > + // Most relocation types are emitted as explicit symbols > + InNormalSection = > + StringSwitch(Section.getSectionName()) > + .Case(".data.rel.ro.local", false) > + .Case(".data.rel", false) > + .Case(".bss", false) > + .Default(true); > + EmitThisSym = true; > + break; > + case ELF::R_ARM_ABS32: > + // But things get strange with R_ARM_ABS32 > + // In this case, most things that go in .rodata show up > + // as section relative relocations > + InNormalSection = > + StringSwitch(Section.getSectionName()) > + .Case(".data.rel.ro.local", false) > + .Case(".data.rel", false) > + .Case(".rodata", false) > + .Case(".bss", false) > + .Default(true); > + EmitThisSym = false; > + break; > + } > } else { > - EmitThisSym = StringSwitch(Symbol.getName()) > - .Case("_MergedGlobals", true) > - .StartsWith(".L.str", true) > - .Default(false); > + NonPCRelCount++; > + InNormalSection = > + StringSwitch(Section.getSectionName()) > + .Case(".data.rel.ro.local", false) > + .Case(".rodata", false) > + .Case(".data.rel", false) > + .Case(".bss", false) > + .Default(true); > + > + switch (RelocType) { > + default: EmitThisSym = true; break; > + case ELF::R_ARM_ABS32: EmitThisSym = false; break; > + } > } > + > if (EmitThisSym) > return &Symbol; > - if (! Symbol.isTemporary()) > + if (! Symbol.isTemporary() && InNormalSection) { > return &Symbol; > + } > return NULL; > } > > +// Need to examine the Fixup when determining whether to > +// emit the relocation as an explicit symbol or as a section relative > +// offset > unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target, > const MCFixup &Fixup, > bool IsPCRel, > @@ -1295,6 +1371,20 @@ > MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? > MCSymbolRefExpr::VK_None : Target.getSymA()->getKind(); > > + unsigned Type = GetRelocTypeInner(Target, Fixup, IsPCRel); > + > + if (RelocNeedsGOT(Modifier)) > + NeedsGOT = true; > + > + return Type; > +} > + > +unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, > + const MCFixup &Fixup, > + bool IsPCRel) const { > + MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? > + MCSymbolRefExpr::VK_None : Target.getSymA()->getKind(); > + > unsigned Type = 0; > if (IsPCRel) { > switch ((unsigned)Fixup.getKind()) { > @@ -1303,7 +1393,7 @@ > switch (Modifier) { > default: llvm_unreachable("Unsupported Modifier"); > case MCSymbolRefExpr::VK_None: > - Type = ELF::R_ARM_BASE_PREL; > + Type = ELF::R_ARM_REL32; > break; > case MCSymbolRefExpr::VK_ARM_TLSGD: > assert(0 && "unimplemented"); > @@ -1399,9 +1489,6 @@ > } > } > > - if (RelocNeedsGOT(Modifier)) > - NeedsGOT = true; > - > return Type; > } > > > Modified: llvm/trunk/lib/MC/ELFObjectWriter.h > URL: > http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=131205&r1=131204&r2=131205&view=diff > > ============================================================================== > --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) > +++ llvm/trunk/lib/MC/ELFObjectWriter.h Wed May 11 17:53:06 2011 > @@ -140,15 +140,18 @@ > unsigned ShstrtabIndex; > > > - const MCSymbol *SymbolToReloc(const MCAssembler &Asm, > - const MCValue &Target, > - const MCFragment &F) const; > + virtual const MCSymbol *SymbolToReloc(const MCAssembler &Asm, > + const MCValue &Target, > + const MCFragment &F, > + const MCFixup &Fixup, > + bool IsPCRel) const; > > // For arch-specific emission of explicit reloc symbol > virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, > const MCValue &Target, > const MCFragment &F, > - bool IsBSS) const { > + const MCFixup &Fixup, > + bool IsPCRel) const { > return NULL; > } > > @@ -380,11 +383,16 @@ > virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, > const MCValue &Target, > const MCFragment &F, > - bool IsBSS) const; > + const MCFixup &Fixup, > + bool IsPCRel) const; > > virtual unsigned GetRelocType(const MCValue &Target, const MCFixup > &Fixup, > bool IsPCRel, bool IsRelocWithSymbol, > int64_t Addend); > + private: > + unsigned GetRelocTypeInner(const MCValue &Target, > + const MCFixup &Fixup, bool IsPCRel) const; > + > }; > > //===- MBlazeELFObjectWriter > -------------------------------------------===// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110518/e9b6c5d8/attachment-0001.html From evan.cheng at apple.com Wed May 18 16:15:16 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 18 May 2011 14:15:16 -0700 Subject: [llvm-commits] [llvm] r131560 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/bool-zext.ll test/CodeGen/X86/vararg_tailcall.ll In-Reply-To: <20110518195950.8F2B62A6C12C@llvm.org> References: <20110518195950.8F2B62A6C12C@llvm.org> Message-ID: <29DAF6ED-923F-4FB9-9F1C-917ADA563810@apple.com> Hi Chad, Comments below. On May 18, 2011, at 12:59 PM, Chad Rosier wrote: > Author: mcrosier > Date: Wed May 18 14:59:50 2011 > New Revision: 131560 > > URL: http://llvm.org/viewvc/llvm-project?rev=131560&view=rev > Log: > Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible. > > Added: > llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll > Modified: > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > llvm/trunk/test/CodeGen/X86/bool-zext.ll > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=131560&r1=131559&r2=131560&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed May 18 14:59:50 2011 > @@ -2525,16 +2525,29 @@ > if (RegInfo->needsStackRealignment(MF)) > return false; > > - // Do not sibcall optimize vararg calls unless the call site is not passing > - // any arguments. > - if (isVarArg && !Outs.empty()) > - return false; > - > // Also avoid sibcall optimization if either caller or callee uses struct > // return semantics. > if (isCalleeStructRet || isCallerStructRet) > return false; > > + // Do not sibcall optimize vararg calls unless all arguments are passed via > + // registers > + if (isVarArg && !Outs.empty()) { > + SmallVector ArgLocs; > + CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), > + ArgLocs, *DAG.getContext()); > + > + // Allocate shadow area for Win64 > + if (Subtarget->isTargetWin64()) { > + CCInfo.AllocateStack(32, 8); > + } Stylistic nitpick. Please remove the '{ }' since the if part is a simple statement. Also, is this even safe to do sibcall here when stack space is being allocated? You know this already. Please test this very carefully. Tailcall optimization can break stuff in very subtle ways. Evan > + > + CCInfo.AnalyzeCallOperands(Outs, CC_X86); > + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) > + if (!ArgLocs[i].isRegLoc()) > + return false; > + } > + > // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. > // Therefore if it's not used by the call it is not safe to optimize this into > // a sibcall. > > Modified: llvm/trunk/test/CodeGen/X86/bool-zext.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bool-zext.ll?rev=131560&r1=131559&r2=131560&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/bool-zext.ll (original) > +++ llvm/trunk/test/CodeGen/X86/bool-zext.ll Wed May 18 14:59:50 2011 > @@ -2,7 +2,7 @@ > > ; CHECK: @bar1 > ; CHECK: movzbl > -; CHECK: callq > +; CHECK: jmp > define void @bar1(i1 zeroext %v1) nounwind ssp { > entry: > %conv = zext i1 %v1 to i32 > @@ -12,7 +12,7 @@ > > ; CHECK: @bar2 > ; CHECK-NOT: movzbl > -; CHECK: callq > +; CHECK: jmp > define void @bar2(i8 zeroext %v1) nounwind ssp { > entry: > %conv = zext i8 %v1 to i32 > > Added: llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll?rev=131560&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll (added) > +++ llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll Wed May 18 14:59:50 2011 > @@ -0,0 +1,85 @@ > +; RUN: llc < %s -march=x86-64 | FileCheck %s > + > + at .str = private unnamed_addr constant [5 x i8] c"%ld\0A\00" > + at sel = external global i8* > + at sel3 = external global i8* > + at sel4 = external global i8* > + at sel5 = external global i8* > + at sel6 = external global i8* > + at sel7 = external global i8* > + > +; CHECK: @foo > +; CHECK: jmp > +define void @foo(i64 %arg) nounwind optsize ssp noredzone { > +entry: > + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone > + ret void > +} > + > +declare i32 @printf(i8*, ...) optsize noredzone > + > +; CHECK: @bar > +; CHECK: jmp > +define void @bar(i64 %arg) nounwind optsize ssp noredzone { > +entry: > + tail call void @bar2(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone > + ret void > +} > + > +declare void @bar2(i8*, i64) optsize noredzone > + > +; CHECK: @foo2 > +; CHECK: jmp > +define i8* @foo2(i8* %arg) nounwind optsize ssp noredzone { > +entry: > + %tmp1 = load i8** @sel, align 8, !tbaa !0 > + %call = tail call i8* (i8*, i8*, ...)* @x2(i8* %arg, i8* %tmp1) nounwind optsize noredzone > + ret i8* %call > +} > + > +declare i8* @x2(i8*, i8*, ...) optsize noredzone > + > +; CHECK: @foo6 > +; CHECK: jmp > +define i8* @foo6(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { > +entry: > + %tmp2 = load i8** @sel3, align 8, !tbaa !0 > + %tmp3 = load i8** @sel4, align 8, !tbaa !0 > + %tmp4 = load i8** @sel5, align 8, !tbaa !0 > + %tmp5 = load i8** @sel6, align 8, !tbaa !0 > + %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5) nounwind optsize noredzone > + ret i8* %call > +} > + > +declare i8* @x3(i8*, i8*, i8*, ...) optsize noredzone > + > +; CHECK: @foo7 > +; CHECK: callq > +define i8* @foo7(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { > +entry: > + %tmp2 = load i8** @sel3, align 8, !tbaa !0 > + %tmp3 = load i8** @sel4, align 8, !tbaa !0 > + %tmp4 = load i8** @sel5, align 8, !tbaa !0 > + %tmp5 = load i8** @sel6, align 8, !tbaa !0 > + %tmp6 = load i8** @sel7, align 8, !tbaa !0 > + %call = tail call i8* (i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...)* @x7(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i8* %tmp6) nounwind optsize noredzone > + ret i8* %call > +} > + > +declare i8* @x7(i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...) optsize noredzone > + > +; CHECK: @foo8 > +; CHECK: callq > +define i8* @foo8(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { > +entry: > + %tmp2 = load i8** @sel3, align 8, !tbaa !0 > + %tmp3 = load i8** @sel4, align 8, !tbaa !0 > + %tmp4 = load i8** @sel5, align 8, !tbaa !0 > + %tmp5 = load i8** @sel6, align 8, !tbaa !0 > + %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i32 48879, i32 48879) nounwind optsize noredzone > + ret i8* %call > +} > + > +!0 = metadata !{metadata !"any pointer", metadata !1} > +!1 = metadata !{metadata !"omnipotent char", metadata !2} > +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Wed May 18 16:25:31 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 18 May 2011 14:25:31 -0700 Subject: [llvm-commits] [llvm] r131525 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp In-Reply-To: <20110518045805.E92FE2A6C12C@llvm.org> References: <20110518045805.E92FE2A6C12C@llvm.org> Message-ID: <246D5D75-85CA-42F7-8CD8-2F8887CE7E06@apple.com> On May 17, 2011, at 9:58 PM, Charles Davis wrote: > Author: cdavis > Date: Tue May 17 23:58:05 2011 > New Revision: 131525 > > URL: http://llvm.org/viewvc/llvm-project?rev=131525&view=rev > Log: > Implement the Win64 EH directive methods for the assembly language streamer. > > GAS has no such directives (not even mingw-w64 GAS has them), so I took > creative license with their names in assembly. I prefixed them all with > "w64_" to avoid namespace collisions, for example. If I discover that GAS > has taken a different approach, I'll change ours to match. Hi Chip, Please remove the commented out lines of code. -Chris > > Modified: > llvm/trunk/lib/MC/MCAsmStreamer.cpp > > Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=131525&r1=131524&r2=131525&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) > +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Tue May 17 23:58:05 2011 > @@ -208,6 +208,15 @@ > virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset); > virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment); > > + virtual void EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler = 0); > + virtual void EmitWin64EHEndProc(); > + virtual void EmitWin64EHPushReg(int64_t Register); > + virtual void EmitWin64EHSetFrame(int64_t Register, int64_t Offset); > + virtual void EmitWin64EHAllocStack(int64_t Size); > + virtual void EmitWin64EHSaveReg(int64_t Register, int64_t Offset); > + virtual void EmitWin64EHPushFrame(bool Code); > + virtual void EmitWin64EHEndProlog(); > + > virtual void EmitFnStart(); > virtual void EmitFnEnd(); > virtual void EmitCantUnwind(); > @@ -915,6 +924,74 @@ > EmitEOL(); > } > > +void MCAsmStreamer::EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler) > +{ > + //MCStreamer::EmitWin64EHStartProc(Symbol, EHandler); > + > + OS << ".w64_startproc " << *Symbol; > + if (EHandler) > + OS << ", " << *EHandler; > + EmitEOL(); > +} > + > +void MCAsmStreamer::EmitWin64EHEndProc() > +{ > + //MCStreamer::EmitWin64EHEndProc(); > + > + OS << "\t.w64_endproc"; > + EmitEOL(); > +} > + > +void MCAsmStreamer::EmitWin64EHPushReg(int64_t Register) > +{ > + //MCStreamer::EmitWin64EHPushReg(Register); > + > + OS << "\t.w64_pushreg " << Register; > + EmitEOL(); > +} > + > +void MCAsmStreamer::EmitWin64EHSetFrame(int64_t Register, int64_t Offset) > +{ > + //MCStreamer::EmitWin64EHSetFrame(Register, Offset); > + > + OS << "\t.w64_setframe " << Register << ", " << Offset; > + EmitEOL(); > +} > + > +void MCAsmStreamer::EmitWin64EHAllocStack(int64_t Size) > +{ > + //MCStremaer::EmitWin64EHAllocStack(Size); > + > + OS << "\t.w64_allocstack " << Size; > + EmitEOL(); > +} > + > +void MCAsmStreamer::EmitWin64EHSaveReg(int64_t Register, int64_t Offset) > +{ > + //MCStreamer::EmitWin64EHSaveReg(Register, Offset) > + > + OS << "\t.w64_savereg " << Register << ", " << Offset; > + EmitEOL(); > +} > + > +void MCAsmStreamer::EmitWin64EHPushFrame(bool Code) > +{ > + //MCStreamer::EmitWin64EHPushFrame(Code); > + > + OS << "\t.w64_pushframe"; > + if (Code) > + OS << " " << "code"; > + EmitEOL(); > +} > + > +void MCAsmStreamer::EmitWin64EHEndProlog(void) > +{ > + //MCStreamer::EmitWin64EHEndProlog(); > + > + OS << "\t.w64_endprolog"; > + EmitEOL(); > +} > + > void MCAsmStreamer::AddEncodingComment(const MCInst &Inst) { > raw_ostream &OS = GetCommentOS(); > SmallString<256> Code; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From clattner at apple.com Wed May 18 16:27:13 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 18 May 2011 14:27:13 -0700 Subject: [llvm-commits] [llvm] r131493 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp test/CodeGen/X86/2011-05-17-pmovzxwd.ll In-Reply-To: References: <20110517221331.910192A6C12C@llvm.org> <6CB7DD3F-FE71-479F-A78F-93138957D8EC@apple.com> Message-ID: <0E177D02-703D-468C-AC2E-690E3395FF6B@apple.com> Thanks Stuart! -Chris On May 18, 2011, at 10:07 AM, Stuart Hastings wrote: > > On May 17, 2011, at 9:33 PM, Chris Lattner wrote: > >> >> On May 17, 2011, at 3:13 PM, Stuart Hastings wrote: >> >>> Author: stuart >>> Date: Tue May 17 17:13:31 2011 >>> New Revision: 131493 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=131493&view=rev >>> Log: >>> X86 pmovsx/pmovzx ignore the upper half of their inputs. >>> rdar://problem/6945110 >> >> Hi Stuart, >> >>> + case Intrinsic::x86_sse41_pmovzxdq: { >>> + unsigned VWidth = >>> + cast(II->getArgOperand(0)->getType())->getNumElements(); >>> + unsigned LowHalfElts = VWidth / 2; >>> + APInt InputDemandedElts(VWidth, 0); >>> + InputDemandedElts = InputDemandedElts.getBitsSet(VWidth, 0, LowHalfElts); >> >> getBitsSet is a static method. Please do this instead: >> >> APInt InputDemandedElts(APInt::getBitsSet(VWidth, 0, LowHalfElts)); > > Done in 131538. > >>> +++ llvm/trunk/test/CodeGen/X86/2011-05-17-pmovzxwd.ll Tue May 17 17:13:31 2011 >>> @@ -0,0 +1,15 @@ >>> +; RUN: opt -instcombine -S < %s | FileCheck %s >>> +; >>> + >>> +define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind { >>> +entry: >>> + %tmp = load <4 x i16>* %src >>> + %tmp1 = load <8 x i16>* %foo >>> +; CHECK: shufflevector >>> + %tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> >>> +; CHECK-NOT: shufflevector >>> + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> >>> + %0 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3) >>> + ret <4 x i32> %0 >>> +} >>> +declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone >> >> Please make the CHECK lines more specific so that it is more clear what you're doing here, add a comment explaining what is going on (to the test) >> and merge the test into an extant .ll file. > > Merged into vec_shuffle-36.ll in 131539. > >> Thanks, > > Thanks for the review, > > stuart From clattner at apple.com Wed May 18 16:28:03 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 18 May 2011 14:28:03 -0700 Subject: [llvm-commits] [llvm] r131539 - in /llvm/trunk/test/CodeGen/X86: 2011-05-17-pmovzxwd.ll vec_shuffle-36.ll In-Reply-To: <20110518170204.3E9F52A6C12C@llvm.org> References: <20110518170204.3E9F52A6C12C@llvm.org> Message-ID: On May 18, 2011, at 10:02 AM, Stuart Hastings wrote: > URL: http://llvm.org/viewvc/llvm-project?rev=131539&view=rev > Log: > Merge pmovzx test case into existing file. One more thing: > +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll Wed May 18 12:02:04 2011 > @@ -1,4 +1,5 @@ > ; RUN: llc < %s -march=x86-64 -mattr=sse41 | FileCheck %s > +; RUN: opt -std-compile-opts < %s | llc -march=x86-64 -mattr=sse41 | FileCheck --check-prefix=CHECK_OPT_LLC %s Why are you running -std-compile-opts here? This is an instcombine patch, so the test should go in Transforms/Instcombine, and should *only* run instcombine. -Chris > > define <8 x i16> @shuf6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { > ; CHECK: pshufb > @@ -14,3 +15,21 @@ > %tmp10 = shufflevector <8 x i16> %t0, <8 x i16> undef, <8 x i32> < i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 undef, i32 undef > > ret <8 x i16> %tmp10 > } > + > + > +; > +define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind { > +entry: > +; CHECK_OPT_LLC: call{{.*nothing}} > + call void @nothing() > + %tmp = load <4 x i16>* %src > + %tmp1 = load <8 x i16>* %foo > +; pmovzxwd ignores the upper 64-bits of its input; everything between the call and pmovzxwd should be removed. > + %tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> > + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> > +; CHECK_OPT_LLC-NEXT: pmovzxwd > + %0 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3) > + ret <4 x i32> %0 > +} > +declare void @nothing() nounwind > +declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From zwarich at apple.com Wed May 18 16:25:14 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 18 May 2011 21:25:14 -0000 Subject: [llvm-commits] [llvm] r131578 - /llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Message-ID: <20110518212515.062ED2A6C12C@llvm.org> Author: zwarich Date: Wed May 18 16:25:14 2011 New Revision: 131578 URL: http://llvm.org/viewvc/llvm-project?rev=131578&view=rev Log: Fix more of PR8825. Now all of CodeGen/ARM passes with VerifyCoalescing turned on. Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=131578&r1=131577&r2=131578&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed May 18 16:25:14 2011 @@ -1672,10 +1672,14 @@ Ops.pop_back(); Ops.pop_back(); + const TargetInstrDesc &TID = TII->get(NewOpc); + const TargetRegisterClass *TRC = TID.OpInfo[0].getRegClass(TRI); + MRI->constrainRegClass(EvenReg, TRC); + MRI->constrainRegClass(OddReg, TRC); + // Form the pair instruction. if (isLd) { - MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, - dl, TII->get(NewOpc)) + MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TID) .addReg(EvenReg, RegState::Define) .addReg(OddReg, RegState::Define) .addReg(BaseReg); @@ -1687,8 +1691,7 @@ MIB.addImm(Offset).addImm(Pred).addReg(PredReg); ++NumLDRDFormed; } else { - MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, - dl, TII->get(NewOpc)) + MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TID) .addReg(EvenReg) .addReg(OddReg) .addReg(BaseReg); From zwarich at apple.com Wed May 18 16:29:07 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 18 May 2011 21:29:07 -0000 Subject: [llvm-commits] [llvm] r131579 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp Message-ID: <20110518212907.7287F2A6C12C@llvm.org> Author: zwarich Date: Wed May 18 16:29:07 2011 New Revision: 131579 URL: http://llvm.org/viewvc/llvm-project?rev=131579&view=rev Log: Fix an obvious typo in r131572. Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=131579&r1=131578&r2=131579&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed May 18 16:29:07 2011 @@ -213,7 +213,7 @@ virtual void EmitWin64EHStartChained(); virtual void EmitWin64EHEndChained(); virtual void EmitWin64EHUnwindOnly(); - virtual void EmitWin64EHLsda(cosnt MCSymbol *Sym, int64_t Size); + virtual void EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size); virtual void EmitWin64EHPushReg(int64_t Register); virtual void EmitWin64EHSetFrame(int64_t Register, int64_t Offset); virtual void EmitWin64EHAllocStack(int64_t Size); @@ -970,7 +970,7 @@ EmitEOL(); } -void MCAsmStreamer::EmitWin64EHLsda(cosnt MCSymbol *Sym, int64_t Size) +void MCAsmStreamer::EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size) { //MCStreamer::EmitWin64EHLsda(Sym, Size); From zwarich at apple.com Wed May 18 16:34:42 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 18 May 2011 14:34:42 -0700 Subject: [llvm-commits] [llvm] r131572 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/MC/MCAsmStreamer.cpp lib/MC/MCStreamer.cpp In-Reply-To: <20110518205410.35D332A6C12C@llvm.org> References: <20110518205410.35D332A6C12C@llvm.org> Message-ID: This code doesn't compile due to an obvious problems (cosnt instead of const). In the future, please check that your patches compile before committing them. Cameron From dpatel at apple.com Wed May 18 16:33:11 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 21:33:11 -0000 Subject: [llvm-commits] [llvm] r131580 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110518213312.088DF2A6C12C@llvm.org> Author: dpatel Date: Wed May 18 16:33:11 2011 New Revision: 131580 URL: http://llvm.org/viewvc/llvm-project?rev=131580&view=rev Log: Use IRBuilder while simplifying return instruction. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131580&r1=131579&r2=131580&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 16:33:11 2011 @@ -62,7 +62,7 @@ bool FoldValueComparisonIntoPredecessors(TerminatorInst *TI, IRBuilder<> &Builder); - bool SimplifyReturn(ReturnInst *RI); + bool SimplifyReturn(ReturnInst *RI, IRBuilder<> &Builder); bool SimplifyUnwind(UnwindInst *UI, IRBuilder<> &Builder); bool SimplifyUnreachable(UnreachableInst *UI); bool SimplifySwitch(SwitchInst *SI, IRBuilder<> &Builder); @@ -1370,7 +1370,8 @@ /// SimplifyCondBranchToTwoReturns - If we found a conditional branch that goes /// to two returning blocks, try to merge them together into one return, /// introducing a select if the return values disagree. -static bool SimplifyCondBranchToTwoReturns(BranchInst *BI) { +static bool SimplifyCondBranchToTwoReturns(BranchInst *BI, + IRBuilder<> &Builder) { assert(BI->isConditional() && "Must be a conditional branch"); BasicBlock *TrueSucc = BI->getSuccessor(0); BasicBlock *FalseSucc = BI->getSuccessor(1); @@ -1385,13 +1386,14 @@ if (!FalseSucc->getFirstNonPHIOrDbg()->isTerminator()) return false; + Builder.SetInsertPoint(BI); // Okay, we found a branch that is going to two return nodes. If // there is no return value for this function, just change the // branch into a return. if (FalseRet->getNumOperands() == 0) { TrueSucc->removePredecessor(BI->getParent()); FalseSucc->removePredecessor(BI->getParent()); - ReturnInst::Create(BI->getContext(), 0, BI); + Builder.CreateRetVoid(); EraseTerminatorInstAndDCECond(BI); return true; } @@ -1434,14 +1436,14 @@ } else if (isa(TrueValue)) { TrueValue = FalseValue; } else { - TrueValue = SelectInst::Create(BrCond, TrueValue, - FalseValue, "retval", BI); + TrueValue = Builder.CreateSelect(BrCond, TrueValue, + FalseValue, "retval"); } } - Value *RI = !TrueValue ? - ReturnInst::Create(BI->getContext(), BI) : - ReturnInst::Create(BI->getContext(), TrueValue, BI); + Value *RI = !TrueValue ? + Builder.CreateRetVoid() : Builder.CreateRet(TrueValue); + (void) RI; DEBUG(dbgs() << "\nCHANGING BRANCH TO TWO RETURNS INTO SELECT:" @@ -2129,7 +2131,7 @@ return true; } -bool SimplifyCFGOpt::SimplifyReturn(ReturnInst *RI) { +bool SimplifyCFGOpt::SimplifyReturn(ReturnInst *RI, IRBuilder<> &Builder) { BasicBlock *BB = RI->getParent(); if (!BB->getFirstNonPHIOrDbg()->isTerminator()) return false; @@ -2173,7 +2175,7 @@ // Check to see if the non-BB successor is also a return block. if (isa(BI->getSuccessor(0)->getTerminator()) && isa(BI->getSuccessor(1)->getTerminator()) && - SimplifyCondBranchToTwoReturns(BI)) + SimplifyCondBranchToTwoReturns(BI, Builder)) return true; } return false; @@ -2671,7 +2673,7 @@ if (SimplifyCondBranch(BI, Builder)) return true; } } else if (ReturnInst *RI = dyn_cast(BB->getTerminator())) { - if (SimplifyReturn(RI)) return true; + if (SimplifyReturn(RI, Builder)) return true; } else if (SwitchInst *SI = dyn_cast(BB->getTerminator())) { if (SimplifySwitch(SI, Builder)) return true; } else if (UnreachableInst *UI = From gohman at apple.com Wed May 18 16:42:29 2011 From: gohman at apple.com (Dan Gohman) Date: Wed, 18 May 2011 14:42:29 -0700 Subject: [llvm-commits] [llvm] r131186 - in /llvm/trunk: include/llvm/Support/Program.h lib/Support/Program.cpp lib/Support/Unix/Program.inc tools/bugpoint/ExecutionDriver.cpp tools/bugpoint/Miscompilation.cpp tools/bugpoint/ToolRunner.cpp In-Reply-To: <20110511163124.D83B82A6C12C@llvm.org> References: <20110511163124.D83B82A6C12C@llvm.org> Message-ID: > --- llvm/trunk/include/llvm/Support/Program.h (original) > +++ llvm/trunk/include/llvm/Support/Program.h Wed May 11 11:31:24 2011 > @@ -96,9 +96,11 @@ > ///< expires, the child is killed and this call returns. If zero, > ///< this function will wait until the child finishes or forever if > ///< it doesn't. > - std::string* ErrMsg ///< If non-zero, provides a pointer to a string > + std::string* ErrMsg, ///< If non-zero, provides a pointer to a string > ///< instance in which error messages will be returned. If the string > ///< is non-empty upon return an error occurred while waiting. > + const char *SignalPrefix ///< If non-zero, provides a prefix to be > + ///< prepended to ErrMsg if the process is terminated abnormally. > ); This function is documented to return a negative value if the process is terminated abnormally. Shouldn't the task of producing a pretty error message belong to client code, rather than being built into these low-level support functions? Dan From eli.friedman at gmail.com Wed May 18 16:40:04 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 21:40:04 -0000 Subject: [llvm-commits] [llvm] r131581 - in /llvm/trunk: include/llvm/DefaultPasses.h include/llvm/Support/StandardPasses.h lib/Support/StandardPasses.cpp Message-ID: <20110518214004.8D7CF2A6C12C@llvm.org> Author: efriedma Date: Wed May 18 16:40:04 2011 New Revision: 131581 URL: http://llvm.org/viewvc/llvm-project?rev=131581&view=rev Log: Third pass at allowing plugins to modify default passes. This time with a tweak so that we don't depend on an uninitialized argument. Modified: llvm/trunk/include/llvm/DefaultPasses.h llvm/trunk/include/llvm/Support/StandardPasses.h llvm/trunk/lib/Support/StandardPasses.cpp Modified: llvm/trunk/include/llvm/DefaultPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/DefaultPasses.h?rev=131581&r1=131580&r2=131581&view=diff ============================================================================== --- llvm/trunk/include/llvm/DefaultPasses.h (original) +++ llvm/trunk/include/llvm/DefaultPasses.h Wed May 18 16:40:04 2011 @@ -0,0 +1,162 @@ +//===- llvm/DefaultPasses.h - Default Pass Support code --------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// This file defines the infrastructure for registering the standard pass list. +// This defines sets of standard optimizations that plugins can modify and +// front ends can use. +//===----------------------------------------------------------------------===// + +#ifndef LLVM_DEFAULT_PASS_SUPPORT_H +#define LLVM_DEFAULT_PASS_SUPPORT_H + +namespace llvm { + +class PassManagerBase; + +/// Unique identifiers for the default standard passes. The addresses of +/// these symbols are used to uniquely identify passes from the default list. +namespace DefaultStandardPasses { +extern unsigned char AggressiveDCEID; +extern unsigned char ArgumentPromotionID; +extern unsigned char BasicAliasAnalysisID; +extern unsigned char CFGSimplificationID; +extern unsigned char ConstantMergeID; +extern unsigned char CorrelatedValuePropagationID; +extern unsigned char DeadArgEliminationID; +extern unsigned char DeadStoreEliminationID; +extern unsigned char DeadTypeEliminationID; +extern unsigned char EarlyCSEID; +extern unsigned char FunctionAttrsID; +extern unsigned char FunctionInliningID; +extern unsigned char GVNID; +extern unsigned char GlobalDCEID; +extern unsigned char GlobalOptimizerID; +extern unsigned char GlobalsModRefID; +extern unsigned char IPSCCPID; +extern unsigned char IndVarSimplifyID; +extern unsigned char InlinerPlaceholderID; +extern unsigned char InstructionCombiningID; +extern unsigned char JumpThreadingID; +extern unsigned char LICMID; +extern unsigned char LoopDeletionID; +extern unsigned char LoopIdiomID; +extern unsigned char LoopRotateID; +extern unsigned char LoopUnrollID; +extern unsigned char LoopUnswitchID; +extern unsigned char MemCpyOptID; +extern unsigned char PruneEHID; +extern unsigned char ReassociateID; +extern unsigned char SCCPID; +extern unsigned char ScalarReplAggregatesID; +extern unsigned char SimplifyLibCallsID; +extern unsigned char StripDeadPrototypesID; +extern unsigned char TailCallEliminationID; +extern unsigned char TypeBasedAliasAnalysisID; +} + +/// StandardPass - The class responsible for maintaining the lists of standard +class StandardPass { + friend class RegisterStandardPassLists; + public: + /// Predefined standard sets of passes + enum StandardSet { + AliasAnalysis, + Function, + Module, + LTO + }; + /// Flags to specify whether a pass should be enabled. Passes registered + /// with the standard sets may specify a minimum optimization level and one + /// or more flags that must be set when constructing the set for the pass to + /// be used. + enum OptimizationFlags { + /// Optimize for size was requested. + OptimizeSize = 1<<0, + /// Allow passes which may make global module changes. + UnitAtATime = 1<<1, + /// UnrollLoops - Allow loop unrolling. + UnrollLoops = 1<<2, + /// Allow library calls to be simplified. + SimplifyLibCalls = 1<<3, + /// Whether the module may have code using exceptions. + HaveExceptions = 1<<4, + // Run an inliner pass as part of this set. + RunInliner = 1<<5 + }; + enum OptimizationFlagComponents { + /// The low bits are used to store the optimization level. When requesting + /// passes, this should store the requested optimisation level. When + /// setting passes, this should set the minimum optimization level at which + /// the pass will run. + OptimizationLevelMask=0xf, + /// The maximum optimisation level at which the pass is run. + MaxOptimizationLevelMask=0xf0, + // Flags that must be set + RequiredFlagMask=0xff00, + // Flags that may not be set. + DisallowedFlagMask=0xff0000, + MaxOptimizationLevelShift=4, + RequiredFlagShift=8, + DisallowedFlagShift=16 + }; + /// Returns the optimisation level from a set of flags. + static unsigned OptimizationLevel(unsigned flags) { + return flags & OptimizationLevelMask ; }; + /// Returns the maximum optimization level for this set of flags + static unsigned MaxOptimizationLevel(unsigned flags) { + return (flags & MaxOptimizationLevelMask) >> 4; }; + /// Constructs a set of flags from the specified minimum and maximum + /// optimisation level + static unsigned OptimzationFlags(unsigned minLevel=0, unsigned maxLevel=0xf, + unsigned requiredFlags=0, unsigned disallowedFlags=0) { + return ((minLevel & OptimizationLevelMask) | + ((maxLevel<> RequiredFlagShift; }; + /// Returns the flags that must not be set for this to match + static unsigned DisallowedFlags(unsigned flags) { + return (flags & DisallowedFlagMask) >> DisallowedFlagShift; }; + /// Register a standard pass in the specified set. If flags is non-zero, + /// then the pass will only be returned when the specified flags are set. + template + class RegisterStandardPass { + public: + RegisterStandardPass(StandardSet set, unsigned char *runBefore=0, + unsigned flags=0, unsigned char *ID=0) { + // Use the pass's ID if one is not specified + RegisterDefaultPass(PassInfo::NormalCtor_t(callDefaultCtor), + ID ? ID : (unsigned char*)&passName::ID, runBefore, set, flags); + }; + }; + /// Adds the passes from the specified set to the provided pass manager + static void AddPassesFromSet(PassManagerBase *PM, + StandardSet set, + unsigned flags=0, + bool VerifyEach=false, + Pass *inliner=0); + private: + /// Registers the default passes. This is set by RegisterStandardPassLists + /// and is called lazily. + static void (*RegisterDefaultPasses)(void); + /// Creates the verifier pass that is inserted when a VerifyEach is passed to + /// AddPassesFromSet() + static Pass* (*CreateVerifierPass)(void); + /// Registers the pass + static void RegisterDefaultPass(PassInfo::NormalCtor_t constructor, + unsigned char *newPass, + unsigned char *oldPass, + StandardSet set, + unsigned flags=0); +}; + +} // namespace llvm + +#endif Modified: llvm/trunk/include/llvm/Support/StandardPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=131581&r1=131580&r2=131581&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) +++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed May 18 16:40:04 2011 @@ -20,6 +20,7 @@ #define LLVM_SUPPORT_STANDARDPASSES_H #include "llvm/PassManager.h" +#include "llvm/DefaultPasses.h" #include "llvm/Analysis/Passes.h" #include "llvm/Analysis/Verifier.h" #include "llvm/Transforms/Scalar.h" @@ -27,12 +28,279 @@ namespace llvm { + /// RegisterStandardPassLists solves a circular dependency problem. The + /// default list of passes has to live somewhere. It can't live in the core + /// modules, because these don't link to the libraries that actually define + /// the passes. It's in this header, so that a copy is created in every + /// library that requests the default set, while still allowing plugins to + /// register new passes without requiring them to link anything more than + /// VMCore. + class RegisterStandardPassLists { + public: + RegisterStandardPassLists() { + StandardPass::RegisterDefaultPasses = RegisterStandardPassList; + StandardPass::CreateVerifierPass = CreateVerifierPass; + } + private: + static llvm::Pass *CreateVerifierPass() { return createVerifierPass(); } + /// Passes must be registered with functions that take no arguments, so we have + /// to wrap their existing constructors. + static Pass *createDefaultScalarReplAggregatesPass(void) { + return createScalarReplAggregatesPass(-1, false); + } + static Pass *createDefaultLoopUnswitchPass(void) { + return createLoopUnswitchPass(false); + } + static Pass *createDefaultLoopUnrollPass(void) { + return createLoopUnrollPass(); + } + static Pass *createSizeOptimizingLoopUnswitchPass(void) { + return createLoopUnswitchPass(true); + } + static Pass *createDefaultGVNPass(void) { + return createGVNPass(); + } + static void RegisterStandardPassList(void) { + // Standard alias analysis passes + + // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that + // BasicAliasAnalysis wins if they disagree. This is intended to help + // support "obvious" type-punning idioms. +#define DEFAULT_ALIAS_ANALYSIS_PASS(pass, flags)\ + StandardPass::RegisterDefaultPass(\ + PassInfo::NormalCtor_t(create ## pass ## Pass),\ + &DefaultStandardPasses::pass ## ID, 0, StandardPass::AliasAnalysis, flags) + DEFAULT_ALIAS_ANALYSIS_PASS(TypeBasedAliasAnalysis, 0); + DEFAULT_ALIAS_ANALYSIS_PASS(BasicAliasAnalysis, 0); +#undef DEFAULT_ALIAS_ANALYSIS_PASS + +#define DEFAULT_FUNCTION_PASS(pass, flags)\ + StandardPass::RegisterDefaultPass(\ + PassInfo::NormalCtor_t(create ## pass ## Pass),\ + &DefaultStandardPasses::pass ## ID, 0, StandardPass::Function, flags) + DEFAULT_FUNCTION_PASS(CFGSimplification, + StandardPass::OptimzationFlags(1)); + DEFAULT_FUNCTION_PASS(ScalarReplAggregates, + StandardPass::OptimzationFlags(1)); + DEFAULT_FUNCTION_PASS(EarlyCSE, StandardPass::OptimzationFlags(1)); +#undef DEFAULT_FUNCTION_PASS + +#define DEFAULT_MODULE_PASS(pass, flags)\ + StandardPass::RegisterDefaultPass(\ + PassInfo::NormalCtor_t(create ## pass ## Pass),\ + &DefaultStandardPasses::pass ## ID, 0, StandardPass::Module, flags) + // Optimize out global vars + DEFAULT_MODULE_PASS(GlobalOptimizer, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + // IP SCCP + DEFAULT_MODULE_PASS(IPSCCP, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + // Dead argument elimination + DEFAULT_MODULE_PASS(DeadArgElimination, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + // Clean up after IPCP & DAE + DEFAULT_MODULE_PASS(InstructionCombining, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + // Clean up after IPCP & DAE + DEFAULT_MODULE_PASS(CFGSimplification, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + + // Remove dead EH info + DEFAULT_MODULE_PASS(PruneEH, StandardPass::OptimzationFlags(0, 0, + StandardPass::UnitAtATime | StandardPass::HaveExceptions)); + // Placeholder that will be replaced by an inliner if one is specified + StandardPass::RegisterDefaultPass(0, + &DefaultStandardPasses::InlinerPlaceholderID, 0, + StandardPass::Module); + // Set readonly/readnone attrs + DEFAULT_MODULE_PASS(FunctionAttrs, StandardPass::OptimzationFlags(0, 0, + StandardPass::UnitAtATime)); + // Scalarize uninlined fn args + DEFAULT_MODULE_PASS(ArgumentPromotion, StandardPass::OptimzationFlags(3)); + // Start of function pass. + // Break up aggregate allocas, using SSAUpdater. + StandardPass::RegisterDefaultPass( + PassInfo::NormalCtor_t(createDefaultScalarReplAggregatesPass), + &DefaultStandardPasses::ScalarReplAggregatesID, 0, + StandardPass::Module); + // Catch trivial redundancies + DEFAULT_MODULE_PASS(EarlyCSE, 0); + // Library Call Optimizations + DEFAULT_MODULE_PASS(SimplifyLibCalls, + StandardPass::OptimzationFlags(0, 0, StandardPass::SimplifyLibCalls)); + // Thread jumps + DEFAULT_MODULE_PASS(JumpThreading, 0); + // Propagate conditionals + DEFAULT_MODULE_PASS(CorrelatedValuePropagation, 0); + // Merge & remove BBs + DEFAULT_MODULE_PASS(CFGSimplification, 0); + // Combine silly seq's + DEFAULT_MODULE_PASS(InstructionCombining, 0); + // Eliminate tail calls + DEFAULT_MODULE_PASS(TailCallElimination, 0); + // Merge & remove BBs + DEFAULT_MODULE_PASS(CFGSimplification, 0); + // Reassociate expressions + DEFAULT_MODULE_PASS(Reassociate, 0); + // Rotate Loop + DEFAULT_MODULE_PASS(LoopRotate, 0); + // Hoist loop invariants + DEFAULT_MODULE_PASS(LICM, 0); + // Optimize for size if the optimzation level is 0-2 + StandardPass::RegisterDefaultPass( + PassInfo::NormalCtor_t(createSizeOptimizingLoopUnswitchPass), + &DefaultStandardPasses::LoopUnswitchID, 0, + StandardPass::Module, + StandardPass::OptimzationFlags(0, 2)); + // Optimize for size if the optimzation level is >2, and OptimizeSize is + // set + StandardPass::RegisterDefaultPass( + PassInfo::NormalCtor_t(createSizeOptimizingLoopUnswitchPass), + &DefaultStandardPasses::LoopUnswitchID, 0, + StandardPass::Module, + StandardPass::OptimzationFlags(3, 0, StandardPass::OptimizeSize)); + // Don't optimize for size if optimisation level is >2 and OptimizeSize + // is not set + StandardPass::RegisterDefaultPass( + PassInfo::NormalCtor_t(createDefaultLoopUnswitchPass), + &DefaultStandardPasses::LoopUnswitchID, 0, + StandardPass::Module, + StandardPass::OptimzationFlags(3, 0, 0, StandardPass::OptimizeSize)); + DEFAULT_MODULE_PASS(InstructionCombining, 0); + // Canonicalize indvars + DEFAULT_MODULE_PASS(IndVarSimplify, 0); + // Recognize idioms like memset. + DEFAULT_MODULE_PASS(LoopIdiom, 0); + // Delete dead loops + DEFAULT_MODULE_PASS(LoopDeletion, 0); + // Unroll small loops + StandardPass::RegisterDefaultPass( + PassInfo::NormalCtor_t(createDefaultLoopUnrollPass), + &DefaultStandardPasses::LoopUnrollID, 0, + StandardPass::Module, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnrollLoops)); + // Remove redundancies + StandardPass::RegisterDefaultPass( + PassInfo::NormalCtor_t(createDefaultGVNPass), + &DefaultStandardPasses::GVNID, 0, + StandardPass::Module, StandardPass::OptimzationFlags(2)); + // Remove memcpy / form memset + DEFAULT_MODULE_PASS(MemCpyOpt, 0); + // Constant prop with SCCP + DEFAULT_MODULE_PASS(SCCP, 0); + + // Run instcombine after redundancy elimination to exploit opportunities + // opened up by them. + DEFAULT_MODULE_PASS(InstructionCombining, 0); + // Thread jumps + DEFAULT_MODULE_PASS(JumpThreading, 0); + DEFAULT_MODULE_PASS(CorrelatedValuePropagation, 0); + // Delete dead stores + DEFAULT_MODULE_PASS(DeadStoreElimination, 0); + // Delete dead instructions + DEFAULT_MODULE_PASS(AggressiveDCE, 0); + // Merge & remove BBs + DEFAULT_MODULE_PASS(CFGSimplification, 0); + // Clean up after everything. + DEFAULT_MODULE_PASS(InstructionCombining, 0); + + // Get rid of dead prototypes + DEFAULT_MODULE_PASS(StripDeadPrototypes, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + // Eliminate dead types + DEFAULT_MODULE_PASS(DeadTypeElimination, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnitAtATime)); + + // GlobalOpt already deletes dead functions and globals, at -O3 try a + // late pass of GlobalDCE. It is capable of deleting dead cycles. + // Remove dead fns and globals. + DEFAULT_MODULE_PASS(GlobalDCE, + StandardPass::OptimzationFlags(3, 0, StandardPass::UnitAtATime)); + // Merge dup global constants + DEFAULT_MODULE_PASS(ConstantMerge, + StandardPass::OptimzationFlags(2, 0, StandardPass::UnitAtATime)); +#undef DEFAULT_MODULE_PASS + +#define DEFAULT_LTO_PASS(pass, flags)\ + StandardPass::RegisterDefaultPass(\ + PassInfo::NormalCtor_t(create ## pass ## Pass), &DefaultStandardPasses::pass ## ID, 0, StandardPass::LTO, flags) + + // LTO passes + + // Propagate constants at call sites into the functions they call. This + // opens opportunities for globalopt (and inlining) by substituting function + // pointers passed as arguments to direct uses of functions. + DEFAULT_LTO_PASS(IPSCCP, 0); + + // Now that we internalized some globals, see if we can hack on them! + DEFAULT_LTO_PASS(GlobalOptimizer, 0); + + // Linking modules together can lead to duplicated global constants, only + // keep one copy of each constant... + DEFAULT_LTO_PASS(ConstantMerge, 0); + + // Remove unused arguments from functions... + DEFAULT_LTO_PASS(DeadArgElimination, 0); + + // Reduce the code after globalopt and ipsccp. Both can open up significant + // simplification opportunities, and both can propagate functions through + // function pointers. When this happens, we often have to resolve varargs + // calls, etc, so let instcombine do this. + DEFAULT_LTO_PASS(InstructionCombining, 0); + + // Inline small functions + DEFAULT_LTO_PASS(FunctionInlining, + StandardPass::OptimzationFlags(0, 0xf, StandardPass::RunInliner)); + // Remove dead EH info. + DEFAULT_LTO_PASS(PruneEH, 0); + // Optimize globals again if we ran the inliner. + DEFAULT_LTO_PASS(GlobalOptimizer, + StandardPass::OptimzationFlags(0, 0xf, StandardPass::RunInliner)); + DEFAULT_LTO_PASS(GlobalDCE, 0); + + // If we didn't decide to inline a function, check to see if we can + // transform it to pass arguments by value instead of by reference. + DEFAULT_LTO_PASS(ArgumentPromotion, 0); + + // The IPO passes may leave cruft around. Clean up after them. + DEFAULT_LTO_PASS(InstructionCombining, 0); + DEFAULT_LTO_PASS(JumpThreading, 0); + // Break up allocas + DEFAULT_LTO_PASS(ScalarReplAggregates, 0); + + // Run a few AA driven optimizations here and now, to cleanup the code. + // Add nocapture. + DEFAULT_LTO_PASS(FunctionAttrs, 0); + // IP alias analysis. + DEFAULT_LTO_PASS(GlobalsModRef, 0); + + // Hoist loop invariants. + DEFAULT_LTO_PASS(LICM, 0); + // Remove redundancies. + DEFAULT_LTO_PASS(GVN, 0); + // Remove dead memcpys. + DEFAULT_LTO_PASS(MemCpyOpt, 0); + // Nuke dead stores. + DEFAULT_LTO_PASS(DeadStoreElimination, 0); + + // Cleanup and simplify the code after the scalar optimizations. + DEFAULT_LTO_PASS(InstructionCombining, 0); + + DEFAULT_LTO_PASS(JumpThreading, 0); + + // Delete basic blocks, which optimization passes may have killed. + DEFAULT_LTO_PASS(CFGSimplification, 0); + + // Now that we have optimized the program, discard unreachable functions. + DEFAULT_LTO_PASS(GlobalDCE, 0); +#undef DEFAULT_LTO_PASS + } + }; + static RegisterStandardPassLists AutoRegister; + + static inline void createStandardAliasAnalysisPasses(PassManagerBase *PM) { - // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that - // BasicAliasAnalysis wins if they disagree. This is intended to help - // support "obvious" type-punning idioms. - PM->add(createTypeBasedAliasAnalysisPass()); - PM->add(createBasicAliasAnalysisPass()); + StandardPass::AddPassesFromSet(PM, StandardPass::AliasAnalysis); } /// createStandardFunctionPasses - Add the standard list of function passes to @@ -42,12 +310,8 @@ /// -O1, etc. static inline void createStandardFunctionPasses(PassManagerBase *PM, unsigned OptimizationLevel) { - if (OptimizationLevel > 0) { - createStandardAliasAnalysisPasses(PM); - PM->add(createCFGSimplificationPass()); - PM->add(createScalarReplAggregatesPass()); - PM->add(createEarlyCSEPass()); - } + StandardPass::AddPassesFromSet(PM, StandardPass::AliasAnalysis); + StandardPass::AddPassesFromSet(PM, StandardPass::Function, OptimizationLevel); } /// createStandardModulePasses - Add the standard list of module passes to the @@ -78,84 +342,17 @@ PM->add(InliningPass); return; } - - if (UnitAtATime) { - PM->add(createGlobalOptimizerPass()); // Optimize out global vars - - PM->add(createIPSCCPPass()); // IP SCCP - PM->add(createDeadArgEliminationPass()); // Dead argument elimination - - PM->add(createInstructionCombiningPass());// Clean up after IPCP & DAE - PM->add(createCFGSimplificationPass()); // Clean up after IPCP & DAE - } - - // Start of CallGraph SCC passes. - if (UnitAtATime && HaveExceptions) - PM->add(createPruneEHPass()); // Remove dead EH info - if (InliningPass) - PM->add(InliningPass); - if (UnitAtATime) - PM->add(createFunctionAttrsPass()); // Set readonly/readnone attrs - if (OptimizationLevel > 2) - PM->add(createArgumentPromotionPass()); // Scalarize uninlined fn args - - // Start of function pass. - // Break up aggregate allocas, using SSAUpdater. - PM->add(createScalarReplAggregatesPass(-1, false)); - PM->add(createEarlyCSEPass()); // Catch trivial redundancies - if (SimplifyLibCalls) - PM->add(createSimplifyLibCallsPass()); // Library Call Optimizations - PM->add(createJumpThreadingPass()); // Thread jumps. - PM->add(createCorrelatedValuePropagationPass()); // Propagate conditionals - PM->add(createCFGSimplificationPass()); // Merge & remove BBs - PM->add(createInstructionCombiningPass()); // Combine silly seq's - - PM->add(createTailCallEliminationPass()); // Eliminate tail calls - PM->add(createCFGSimplificationPass()); // Merge & remove BBs - PM->add(createReassociatePass()); // Reassociate expressions - PM->add(createLoopRotatePass()); // Rotate Loop - PM->add(createLICMPass()); // Hoist loop invariants - PM->add(createLoopUnswitchPass(OptimizeSize || OptimizationLevel < 3)); - PM->add(createInstructionCombiningPass()); - PM->add(createIndVarSimplifyPass()); // Canonicalize indvars - PM->add(createLoopIdiomPass()); // Recognize idioms like memset. - PM->add(createLoopDeletionPass()); // Delete dead loops - if (UnrollLoops) - PM->add(createLoopUnrollPass()); // Unroll small loops - if (OptimizationLevel > 1) - PM->add(createGVNPass()); // Remove redundancies - PM->add(createMemCpyOptPass()); // Remove memcpy / form memset - PM->add(createSCCPPass()); // Constant prop with SCCP - - // Run instcombine after redundancy elimination to exploit opportunities - // opened up by them. - PM->add(createInstructionCombiningPass()); - PM->add(createJumpThreadingPass()); // Thread jumps - PM->add(createCorrelatedValuePropagationPass()); - PM->add(createDeadStoreEliminationPass()); // Delete dead stores - PM->add(createAggressiveDCEPass()); // Delete dead instructions - PM->add(createCFGSimplificationPass()); // Merge & remove BBs - PM->add(createInstructionCombiningPass()); // Clean up after everything. - - if (UnitAtATime) { - PM->add(createStripDeadPrototypesPass()); // Get rid of dead prototypes - PM->add(createDeadTypeEliminationPass()); // Eliminate dead types - // GlobalOpt already deletes dead functions and globals, at -O3 try a - // late pass of GlobalDCE. It is capable of deleting dead cycles. - if (OptimizationLevel > 2) - PM->add(createGlobalDCEPass()); // Remove dead fns and globals. + StandardPass::AddPassesFromSet(PM, StandardPass::Module, + StandardPass::OptimzationFlags(OptimizationLevel, 0, + (OptimizeSize ? StandardPass::OptimizeSize : 0) | + (UnitAtATime ? StandardPass::UnitAtATime : 0) | + (UnrollLoops ? StandardPass::UnrollLoops : 0) | + (SimplifyLibCalls ? StandardPass::SimplifyLibCalls : 0) | + (HaveExceptions ? StandardPass::HaveExceptions : 0)), + false, + InliningPass); - if (OptimizationLevel > 1) - PM->add(createConstantMergePass()); // Merge dup global constants - } - } - - static inline void addOnePass(PassManagerBase *PM, Pass *P, bool AndVerify) { - PM->add(P); - - if (AndVerify) - PM->add(createVerifierPass()); } /// createStandardLTOPasses - Add the standard list of module passes suitable @@ -174,70 +371,15 @@ // Now that composite has been compiled, scan through the module, looking // for a main function. If main is defined, mark all other functions // internal. - if (Internalize) - addOnePass(PM, createInternalizePass(true), VerifyEach); - - // Propagate constants at call sites into the functions they call. This - // opens opportunities for globalopt (and inlining) by substituting function - // pointers passed as arguments to direct uses of functions. - addOnePass(PM, createIPSCCPPass(), VerifyEach); - - // Now that we internalized some globals, see if we can hack on them! - addOnePass(PM, createGlobalOptimizerPass(), VerifyEach); - - // Linking modules together can lead to duplicated global constants, only - // keep one copy of each constant... - addOnePass(PM, createConstantMergePass(), VerifyEach); - - // Remove unused arguments from functions... - addOnePass(PM, createDeadArgEliminationPass(), VerifyEach); - - // Reduce the code after globalopt and ipsccp. Both can open up significant - // simplification opportunities, and both can propagate functions through - // function pointers. When this happens, we often have to resolve varargs - // calls, etc, so let instcombine do this. - addOnePass(PM, createInstructionCombiningPass(), VerifyEach); - - // Inline small functions - if (RunInliner) - addOnePass(PM, createFunctionInliningPass(), VerifyEach); - - addOnePass(PM, createPruneEHPass(), VerifyEach); // Remove dead EH info. - // Optimize globals again if we ran the inliner. - if (RunInliner) - addOnePass(PM, createGlobalOptimizerPass(), VerifyEach); - addOnePass(PM, createGlobalDCEPass(), VerifyEach); // Remove dead functions. - - // If we didn't decide to inline a function, check to see if we can - // transform it to pass arguments by value instead of by reference. - addOnePass(PM, createArgumentPromotionPass(), VerifyEach); - - // The IPO passes may leave cruft around. Clean up after them. - addOnePass(PM, createInstructionCombiningPass(), VerifyEach); - addOnePass(PM, createJumpThreadingPass(), VerifyEach); - // Break up allocas - addOnePass(PM, createScalarReplAggregatesPass(), VerifyEach); - - // Run a few AA driven optimizations here and now, to cleanup the code. - addOnePass(PM, createFunctionAttrsPass(), VerifyEach); // Add nocapture. - addOnePass(PM, createGlobalsModRefPass(), VerifyEach); // IP alias analysis. - - addOnePass(PM, createLICMPass(), VerifyEach); // Hoist loop invariants. - addOnePass(PM, createGVNPass(), VerifyEach); // Remove redundancies. - addOnePass(PM, createMemCpyOptPass(), VerifyEach); // Remove dead memcpys. - // Nuke dead stores. - addOnePass(PM, createDeadStoreEliminationPass(), VerifyEach); - - // Cleanup and simplify the code after the scalar optimizations. - addOnePass(PM, createInstructionCombiningPass(), VerifyEach); - - addOnePass(PM, createJumpThreadingPass(), VerifyEach); - - // Delete basic blocks, which optimization passes may have killed. - addOnePass(PM, createCFGSimplificationPass(), VerifyEach); + if (Internalize) { + PM->add(createInternalizePass(true)); + if (VerifyEach) + PM->add(createVerifierPass()); + } - // Now that we have optimized the program, discard unreachable functions. - addOnePass(PM, createGlobalDCEPass(), VerifyEach); + StandardPass::AddPassesFromSet(PM, StandardPass::LTO, + StandardPass::OptimzationFlags(0, 0, RunInliner ? + StandardPass::RunInliner : 0), VerifyEach); } } Modified: llvm/trunk/lib/Support/StandardPasses.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/StandardPasses.cpp?rev=131581&r1=131580&r2=131581&view=diff ============================================================================== --- llvm/trunk/lib/Support/StandardPasses.cpp (original) +++ llvm/trunk/lib/Support/StandardPasses.cpp Wed May 18 16:40:04 2011 @@ -0,0 +1,247 @@ +//===-- lib/Support/StandardPasses.cpp - Standard pass lists -----*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines utility functions for creating a "standard" set of +// optimization passes, so that compilers and tools which use optimization +// passes use the same set of standard passes. +// +// This allows the creation of multiple standard sets, and their later +// modification by plugins and front ends. +// +//===----------------------------------------------------------------------===// + +#include "llvm/PassManager.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/ManagedStatic.h" +#include "llvm/DefaultPasses.h" +#include "llvm/Support/Mutex.h" + +using namespace llvm::DefaultStandardPasses; +using namespace llvm; + +namespace { + +/// Entry in the standard passes list. +struct StandardPassEntry { + /// Function called to create the pass + PassInfo::NormalCtor_t createPass; + /// Unique identifier for this pass + unsigned char *passID; + /// Flags specifying when this pass should be run + unsigned flags; + + StandardPassEntry(PassInfo::NormalCtor_t constructor, unsigned char *ID, + unsigned f) : createPass(constructor), passID(ID), flags(f) {}; +}; + +/// Standard alias analysis passes +static llvm::SmallVector AAPasses; +/// Standard function passes +static llvm::SmallVector FunctionPasses; +/// Standard module passes +static llvm::SmallVector ModulePasses; +/// Standard link-time optimization passes +static llvm::SmallVector LTOPasses; + +/// Entry in the unresolved standard pass list. IF a pass is inserted in front +/// of a pass that is not yet registered in the standard pass list then it is +/// stored in a separate list and resolved later. +struct UnresolvedStandardPass : public StandardPassEntry { + /// The set into which this is stored + StandardPass::StandardSet set; + /// The unique ID of the pass that should follow this one in the sequence + unsigned char *next; + UnresolvedStandardPass(PassInfo::NormalCtor_t constructor, + unsigned char *newPass, + unsigned char *oldPass, + StandardPass::StandardSet s, + unsigned f) : + StandardPassEntry(constructor, newPass, f), set(s), next(oldPass) {} +}; + +/// The passes that can not be inserted into the correct lists yet because of +/// their place in the sequence. +static llvm::SmallVector UnresolvedPasses; + +/// Returns a reference to the pass list for the corresponding set of +/// optimisations. +llvm::SmallVectorImpl& +PassList(StandardPass::StandardSet set) { + switch (set) { + case StandardPass::AliasAnalysis: return AAPasses; + case StandardPass::Function: return FunctionPasses; + case StandardPass::Module: return ModulePasses; + case StandardPass::LTO: return LTOPasses; + } + // We could use a map of standard pass lists to allow definition of new + // default sets + llvm_unreachable("Invalid standard optimization set requested"); +} + +static ManagedStatic > Lock; + +/// Registers the default set of standard passes. This is called lazily when +/// an attempt is made to read or modify the standard pass list +void RegisterDefaultStandardPasses(void(*doRegister)(void)) { + // Only initialize the standard passes once + static volatile bool initialized = false; + if (initialized) return; + + llvm::sys::SmartScopedLock Guard(*Lock); + if (initialized) return; + if (doRegister) { + assert("No passes registered before setting default passes" && + AAPasses.size() == 0 && + FunctionPasses.size() == 0 && + LTOPasses.size() == 0 && + ModulePasses.size() == 0); + + // We must set initialized to true before calling this function, because + // the doRegister() function will probably call RegisterDefaultPasses(), + // which will call this function, and we'd end up with infinite recursion + // and breakage if we didn't. + initialized = true; + doRegister(); + } +} + +} // Anonymous namespace + +void (*StandardPass::RegisterDefaultPasses)(void); +Pass* (*StandardPass::CreateVerifierPass)(void); + +void StandardPass::RegisterDefaultPass(PassInfo::NormalCtor_t constructor, + unsigned char *newPass, + unsigned char *oldPass, + StandardPass::StandardSet set, + unsigned flags) { + // Make sure that the standard sets are already regstered + RegisterDefaultStandardPasses(RegisterDefaultPasses); + // Get the correct list to modify + llvm::SmallVectorImpl& passList = PassList(set); + + // If there is no old pass specified, then we are adding a new final pass, so + // just push it onto the end. + if (!oldPass) { + StandardPassEntry pass(constructor, newPass, flags); + passList.push_back(pass); + return; + } + + // Find the correct place to insert the pass. This is a linear search, but + // this shouldn't be too slow since the SmallVector will store the values in + // a contiguous block of memory. Each entry is just three words of memory, so + // in most cases we are only going to be looking in one or two cache lines. + // The extra memory accesses from a more complex search structure would + // offset any performance gain (unless someone decides to add an insanely + // large set of standard passes to a set) + for (SmallVectorImpl::iterator i=passList.begin(), + e=passList.end() ; i!=e ; ++i) { + if (i->passID == oldPass) { + StandardPassEntry pass(constructor, newPass, flags); + passList.insert(i, pass); + // If we've added a new pass, then there may have gained the ability to + // insert one of the previously unresolved ones. If so, insert the new + // one. + for (SmallVectorImpl::iterator + u=UnresolvedPasses.begin(), eu=UnresolvedPasses.end() ; u!=eu ; ++u){ + if (u->next == newPass && u->set == set) { + UnresolvedStandardPass p = *u; + UnresolvedPasses.erase(u); + RegisterDefaultPass(p.createPass, p.passID, p.next, p.set, p.flags); + } + } + return; + } + } + // If we get to here, then we didn't find the correct place to insert the new + // pass + UnresolvedStandardPass pass(constructor, newPass, oldPass, set, flags); + UnresolvedPasses.push_back(pass); +} + +void StandardPass::AddPassesFromSet(PassManagerBase *PM, + StandardSet set, + unsigned flags, + bool VerifyEach, + Pass *inliner) { + RegisterDefaultStandardPasses(RegisterDefaultPasses); + unsigned level = OptimizationLevel(flags); + flags = RequiredFlags(flags); + llvm::SmallVectorImpl& passList = PassList(set); + + // Add all of the passes from this set + for (SmallVectorImpl::iterator i=passList.begin(), + e=passList.end() ; i!=e ; ++i) { + // Skip passes that don't have conditions that match the ones specified + // here. For a pass to match: + // - Its minimum optimisation level must be less than or equal to the + // specified level. + // - Its maximum optimisation level must be greater than or equal to the + // specified level + // - All of its required flags must be set + // - None of its disallowed flags may be set + if ((level >= OptimizationLevel(i->flags)) && + ((level <= MaxOptimizationLevel(i->flags)) + || MaxOptimizationLevel(i->flags) == 0) && + ((RequiredFlags(i->flags) & flags) == RequiredFlags(i->flags)) && + ((DisallowedFlags(i->flags) & flags) == 0)) { + // This is quite an ugly way of allowing us to specify an inliner pass to + // insert. Ideally, we'd replace this with a general mechanism allowing + // callers to replace arbitrary passes in the list. + Pass *p = 0; + if (&InlinerPlaceholderID == i->passID) { + p = inliner; + } else if (i->createPass) + p = i->createPass(); + if (p) { + PM->add(p); + if (VerifyEach) + PM->add(CreateVerifierPass()); + } + } + } +} + +unsigned char DefaultStandardPasses::AggressiveDCEID; +unsigned char DefaultStandardPasses::ArgumentPromotionID; +unsigned char DefaultStandardPasses::BasicAliasAnalysisID; +unsigned char DefaultStandardPasses::CFGSimplificationID; +unsigned char DefaultStandardPasses::ConstantMergeID; +unsigned char DefaultStandardPasses::CorrelatedValuePropagationID; +unsigned char DefaultStandardPasses::DeadArgEliminationID; +unsigned char DefaultStandardPasses::DeadStoreEliminationID; +unsigned char DefaultStandardPasses::DeadTypeEliminationID; +unsigned char DefaultStandardPasses::EarlyCSEID; +unsigned char DefaultStandardPasses::FunctionAttrsID; +unsigned char DefaultStandardPasses::FunctionInliningID; +unsigned char DefaultStandardPasses::GVNID; +unsigned char DefaultStandardPasses::GlobalDCEID; +unsigned char DefaultStandardPasses::GlobalOptimizerID; +unsigned char DefaultStandardPasses::GlobalsModRefID; +unsigned char DefaultStandardPasses::IPSCCPID; +unsigned char DefaultStandardPasses::IndVarSimplifyID; +unsigned char DefaultStandardPasses::InlinerPlaceholderID; +unsigned char DefaultStandardPasses::InstructionCombiningID; +unsigned char DefaultStandardPasses::JumpThreadingID; +unsigned char DefaultStandardPasses::LICMID; +unsigned char DefaultStandardPasses::LoopDeletionID; +unsigned char DefaultStandardPasses::LoopIdiomID; +unsigned char DefaultStandardPasses::LoopRotateID; +unsigned char DefaultStandardPasses::LoopUnrollID; +unsigned char DefaultStandardPasses::LoopUnswitchID; +unsigned char DefaultStandardPasses::MemCpyOptID; +unsigned char DefaultStandardPasses::PruneEHID; +unsigned char DefaultStandardPasses::ReassociateID; +unsigned char DefaultStandardPasses::SCCPID; +unsigned char DefaultStandardPasses::ScalarReplAggregatesID; +unsigned char DefaultStandardPasses::SimplifyLibCallsID; +unsigned char DefaultStandardPasses::StripDeadPrototypesID; +unsigned char DefaultStandardPasses::TailCallEliminationID; +unsigned char DefaultStandardPasses::TypeBasedAliasAnalysisID; From tonic at nondot.org Wed May 18 16:44:54 2011 From: tonic at nondot.org (Tanya Lattner) Date: Wed, 18 May 2011 21:44:54 -0000 Subject: [llvm-commits] [llvm] r131582 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vrev.ll Message-ID: <20110518214454.78F122A6C12C@llvm.org> Author: tbrethou Date: Wed May 18 16:44:54 2011 New Revision: 131582 URL: http://llvm.org/viewvc/llvm-project?rev=131582&view=rev Log: Handle perfect shuffle case that generates a vrev for vectors of floats. Add test case. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/test/CodeGen/ARM/vrev.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=131582&r1=131581&r2=131582&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed May 18 16:44:54 2011 @@ -4184,7 +4184,8 @@ default: llvm_unreachable("Unknown shuffle opcode!"); case OP_VREV: // VREV divides the vector in half and swaps within the half. - if (VT.getVectorElementType() == MVT::i32) + if (VT.getVectorElementType() == MVT::i32 || + VT.getVectorElementType() == MVT::f32) return DAG.getNode(ARMISD::VREV64, dl, VT, OpLHS); // vrev <4 x i16> -> VREV32 if (VT.getVectorElementType() == MVT::i16) Modified: llvm/trunk/test/CodeGen/ARM/vrev.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vrev.ll?rev=131582&r1=131581&r2=131582&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/vrev.ll (original) +++ llvm/trunk/test/CodeGen/ARM/vrev.ll Wed May 18 16:44:54 2011 @@ -163,3 +163,18 @@ store <2 x i16> %tmp11, <2 x i16>* %dst, align 4 ret void } + +; Test vrev of float4 +define void @float_vrev64(float* nocapture %source, <4 x float>* nocapture %dest) nounwind noinline ssp { +; CHECK: float_vrev64 +; CHECK: vext.32 +; CHECK: vrev64.32 +entry: + %0 = bitcast float* %source to <4 x float>* + %tmp2 = load <4 x float>* %0, align 4 + %tmp5 = shufflevector <4 x float> , <4 x float> %tmp2, <4 x i32> + %arrayidx8 = getelementptr inbounds <4 x float>* %dest, i32 11 + store <4 x float> %tmp5, <4 x float>* %arrayidx8, align 4 + ret void +} + From grosbach at apple.com Wed May 18 16:52:01 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 18 May 2011 14:52:01 -0700 Subject: [llvm-commits] [llvm] r131579 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp In-Reply-To: <20110518212907.7287F2A6C12C@llvm.org> References: <20110518212907.7287F2A6C12C@llvm.org> Message-ID: The buildbots say "thanks!" :) On May 18, 2011, at 2:29 PM, Cameron Zwarich wrote: > Author: zwarich > Date: Wed May 18 16:29:07 2011 > New Revision: 131579 > > URL: http://llvm.org/viewvc/llvm-project?rev=131579&view=rev > Log: > Fix an obvious typo in r131572. > > Modified: > llvm/trunk/lib/MC/MCAsmStreamer.cpp > > Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=131579&r1=131578&r2=131579&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) > +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed May 18 16:29:07 2011 > @@ -213,7 +213,7 @@ > virtual void EmitWin64EHStartChained(); > virtual void EmitWin64EHEndChained(); > virtual void EmitWin64EHUnwindOnly(); > - virtual void EmitWin64EHLsda(cosnt MCSymbol *Sym, int64_t Size); > + virtual void EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size); > virtual void EmitWin64EHPushReg(int64_t Register); > virtual void EmitWin64EHSetFrame(int64_t Register, int64_t Offset); > virtual void EmitWin64EHAllocStack(int64_t Size); > @@ -970,7 +970,7 @@ > EmitEOL(); > } > > -void MCAsmStreamer::EmitWin64EHLsda(cosnt MCSymbol *Sym, int64_t Size) > +void MCAsmStreamer::EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size) > { > //MCStreamer::EmitWin64EHLsda(Sym, Size); > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From cdavis at mymail.mines.edu Wed May 18 16:59:42 2011 From: cdavis at mymail.mines.edu (Charles Davis) Date: Wed, 18 May 2011 15:59:42 -0600 Subject: [llvm-commits] [llvm] r131572 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/MC/MCAsmStreamer.cpp lib/MC/MCStreamer.cpp In-Reply-To: References: <20110518205410.35D332A6C12C@llvm.org> Message-ID: <4DD4414E.9090602@mymail.mines.edu> On 5/18/11 3:34 PM, Cameron Zwarich wrote: > This code doesn't compile due to an obvious problems (cosnt instead of const). In the future, please check that your patches compile before committing them. > > Cameron Heh heh, sorry... Guess I'm a little too eager. Chip From zwarich at apple.com Wed May 18 16:54:32 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 18 May 2011 21:54:32 -0000 Subject: [llvm-commits] [llvm] r131587 - /llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Message-ID: <20110518215432.EDA562A6C12C@llvm.org> Author: zwarich Date: Wed May 18 16:54:32 2011 New Revision: 131587 URL: http://llvm.org/viewvc/llvm-project?rev=131587&view=rev Log: Reserve r29 on Alpha. This fixes all verifier failures in CodeGen/Alpha. Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=131587&r1=131586&r2=131587&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Wed May 18 16:54:32 2011 @@ -69,6 +69,7 @@ BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); Reserved.set(Alpha::R15); + Reserved.set(Alpha::R29); Reserved.set(Alpha::R30); Reserved.set(Alpha::R31); return Reserved; From cdavis at mines.edu Wed May 18 17:13:51 2011 From: cdavis at mines.edu (Charles Davis) Date: Wed, 18 May 2011 22:13:51 -0000 Subject: [llvm-commits] [llvm] r131590 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp Message-ID: <20110518221351.BE6BC2A6C12C@llvm.org> Author: cdavis Date: Wed May 18 17:13:51 2011 New Revision: 131590 URL: http://llvm.org/viewvc/llvm-project?rev=131590&view=rev Log: Remove comments as Chris requested. Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=131590&r1=131589&r2=131590&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed May 18 17:13:51 2011 @@ -928,102 +928,66 @@ EmitEOL(); } -void MCAsmStreamer::EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler) -{ - //MCStreamer::EmitWin64EHStartProc(Symbol, EHandler); - +void MCAsmStreamer::EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler) { OS << ".w64_startproc " << *Symbol; if (EHandler) OS << ", " << *EHandler; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHEndProc() -{ - //MCStreamer::EmitWin64EHEndProc(); - +void MCAsmStreamer::EmitWin64EHEndProc() { OS << "\t.w64_endproc"; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHStartChained() -{ - //MCStreamer::EmitWin64EHStartChained(); - +void MCAsmStreamer::EmitWin64EHStartChained() { OS << "\t.w64_startchained"; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHEndChained() -{ - //MCStreamer::EmitWin64EHEndChained(); - +void MCAsmStreamer::EmitWin64EHEndChained() { OS << "\t.w64_endchained"; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHUnwindOnly() -{ - //MCStreamer::EmitWin64EHUnwindOnly(); - +void MCAsmStreamer::EmitWin64EHUnwindOnly() { OS << "\t.w64_unwind_only"; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size) -{ - //MCStreamer::EmitWin64EHLsda(Sym, Size); - +void MCAsmStreamer::EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size) { OS << "\t.w64_lsda " << *Sym << ", " << Size; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHPushReg(int64_t Register) -{ - //MCStreamer::EmitWin64EHPushReg(Register); - +void MCAsmStreamer::EmitWin64EHPushReg(int64_t Register) { OS << "\t.w64_pushreg " << Register; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHSetFrame(int64_t Register, int64_t Offset) -{ - //MCStreamer::EmitWin64EHSetFrame(Register, Offset); - +void MCAsmStreamer::EmitWin64EHSetFrame(int64_t Register, int64_t Offset) { OS << "\t.w64_setframe " << Register << ", " << Offset; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHAllocStack(int64_t Size) -{ - //MCStremaer::EmitWin64EHAllocStack(Size); - +void MCAsmStreamer::EmitWin64EHAllocStack(int64_t Size) { OS << "\t.w64_allocstack " << Size; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHSaveReg(int64_t Register, int64_t Offset) -{ - //MCStreamer::EmitWin64EHSaveReg(Register, Offset) - +void MCAsmStreamer::EmitWin64EHSaveReg(int64_t Register, int64_t Offset) { OS << "\t.w64_savereg " << Register << ", " << Offset; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHPushFrame(bool Code) -{ - //MCStreamer::EmitWin64EHPushFrame(Code); - +void MCAsmStreamer::EmitWin64EHPushFrame(bool Code) { OS << "\t.w64_pushframe"; if (Code) OS << " " << "code"; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHEndProlog(void) -{ - //MCStreamer::EmitWin64EHEndProlog(); - +void MCAsmStreamer::EmitWin64EHEndProlog(void) { OS << "\t.w64_endprolog"; EmitEOL(); } From cdavis at mymail.mines.edu Wed May 18 17:19:37 2011 From: cdavis at mymail.mines.edu (Charles Davis) Date: Wed, 18 May 2011 16:19:37 -0600 Subject: [llvm-commits] [llvm] r131525 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp In-Reply-To: <246D5D75-85CA-42F7-8CD8-2F8887CE7E06@apple.com> References: <20110518045805.E92FE2A6C12C@llvm.org> <246D5D75-85CA-42F7-8CD8-2F8887CE7E06@apple.com> Message-ID: <4DD445F9.9060008@mymail.mines.edu> On 5/18/11 3:25 PM, Chris Lattner wrote: > Hi Chip, > > Please remove the commented out lines of code. Done in r131590. Chip From zwarich at apple.com Wed May 18 17:24:48 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 18 May 2011 22:24:48 -0000 Subject: [llvm-commits] [llvm] r131591 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <20110518222448.CF1692A6C12C@llvm.org> Author: zwarich Date: Wed May 18 17:24:48 2011 New Revision: 131591 URL: http://llvm.org/viewvc/llvm-project?rev=131591&view=rev Log: Reserve the segment registers on x86 to fix verifier failures in any code that uses them. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=131591&r1=131590&r2=131591&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed May 18 17:24:48 2011 @@ -468,6 +468,15 @@ Reserved.set(X86::ST5); Reserved.set(X86::ST6); Reserved.set(X86::ST7); + + // Mark the segment registers as reserved. + Reserved.set(X86::CS); + Reserved.set(X86::SS); + Reserved.set(X86::DS); + Reserved.set(X86::ES); + Reserved.set(X86::FS); + Reserved.set(X86::GS); + return Reserved; } From fvbommel at gmail.com Wed May 18 17:35:26 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Thu, 19 May 2011 00:35:26 +0200 Subject: [llvm-commits] [llvm] r131516 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/InstCombine/InstructionCombining.cpp test/Transforms/InstCombine/call.ll In-Reply-To: <0E01649B-8940-4C3E-9FDB-F9946A4BB14B@apple.com> References: <20110518012827.9FAAB2A6C12C@llvm.org> <0E01649B-8940-4C3E-9FDB-F9946A4BB14B@apple.com> Message-ID: On Wed, May 18, 2011 at 11:04 PM, Devang Patel wrote: > On May 18, 2011, at 12:44 AM, Frits van Bommel wrote: >> On Wed, May 18, 2011 at 3:28 AM, Eli Friedman wrote: >>> ? ? // Now that we have an instruction, try combining it to simplify it. >>> ? ? Builder->SetInsertPoint(I->getParent(), I); >>> + ? ?Builder->SetCurrentDebugLocation(I->getDebugLoc()); >> >> This would look even nicer if the IRBuilder::SetInsertPoint() >> overloads that take an Instruction* did this automatically :). > > Good idea! r131575. The idea was to then also remove that explicit Builder->SetCurrentDebugLocation() call :). (Same goes for occurrences of this pattern in other passes, if any) From csdavec at swan.ac.uk Wed May 18 17:46:02 2011 From: csdavec at swan.ac.uk (David Chisnall) Date: Wed, 18 May 2011 22:46:02 -0000 Subject: [llvm-commits] [llvm] r131592 - /llvm/trunk/include/llvm/Support/StandardPasses.h Message-ID: <20110518224602.506AF2A6C12C@llvm.org> Author: theraven Date: Wed May 18 17:46:02 2011 New Revision: 131592 URL: http://llvm.org/viewvc/llvm-project?rev=131592&view=rev Log: Some better type safety enforcement in the standard pass list, along with some small tidies and some fixes for bugs that the stricter checking found. Modified: llvm/trunk/include/llvm/Support/StandardPasses.h Modified: llvm/trunk/include/llvm/Support/StandardPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=131592&r1=131591&r2=131592&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) +++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed May 18 17:46:02 2011 @@ -27,6 +27,7 @@ #include "llvm/Transforms/IPO.h" namespace llvm { + //template static Pass *CreatePassFn(void) { return X(); } /// RegisterStandardPassLists solves a circular dependency problem. The /// default list of passes has to live somewhere. It can't live in the core @@ -42,23 +43,36 @@ StandardPass::CreateVerifierPass = CreateVerifierPass; } private: + /// Define a template function that does the casting for us, so that we can + /// perform safe function pointer casts, but catch unsafe ones. + template static llvm::Pass* + CreatePassFn(void) { return X(); } + template static llvm::Pass* + CreatePassFn(void) { return X(); } + template static llvm::Pass* + CreatePassFn(void) { return X(); } + template static llvm::Pass* + CreatePassFn(void) { return X(); } static llvm::Pass *CreateVerifierPass() { return createVerifierPass(); } /// Passes must be registered with functions that take no arguments, so we have /// to wrap their existing constructors. - static Pass *createDefaultScalarReplAggregatesPass(void) { - return createScalarReplAggregatesPass(-1, false); + static Pass *createScalarReplAggregatesPass(void) { + return llvm::createScalarReplAggregatesPass(-1, false); } static Pass *createDefaultLoopUnswitchPass(void) { return createLoopUnswitchPass(false); } - static Pass *createDefaultLoopUnrollPass(void) { - return createLoopUnrollPass(); - } static Pass *createSizeOptimizingLoopUnswitchPass(void) { return createLoopUnswitchPass(true); } - static Pass *createDefaultGVNPass(void) { - return createGVNPass(); + static Pass *createArgumentPromotionPass(void) { + return llvm::createArgumentPromotionPass(); + } + static Pass *createLoopUnrollPass(void) { + return llvm::createLoopUnrollPass(); + } + static Pass *createGVNPass(void) { + return llvm::createGVNPass(); } static void RegisterStandardPassList(void) { // Standard alias analysis passes @@ -68,15 +82,15 @@ // support "obvious" type-punning idioms. #define DEFAULT_ALIAS_ANALYSIS_PASS(pass, flags)\ StandardPass::RegisterDefaultPass(\ - PassInfo::NormalCtor_t(create ## pass ## Pass),\ - &DefaultStandardPasses::pass ## ID, 0, StandardPass::AliasAnalysis, flags) + CreatePassFn,\ + &DefaultStandardPasses::pass ## ID, (unsigned char*)0, StandardPass::AliasAnalysis, flags) DEFAULT_ALIAS_ANALYSIS_PASS(TypeBasedAliasAnalysis, 0); DEFAULT_ALIAS_ANALYSIS_PASS(BasicAliasAnalysis, 0); #undef DEFAULT_ALIAS_ANALYSIS_PASS #define DEFAULT_FUNCTION_PASS(pass, flags)\ StandardPass::RegisterDefaultPass(\ - PassInfo::NormalCtor_t(create ## pass ## Pass),\ + CreatePassFn,\ &DefaultStandardPasses::pass ## ID, 0, StandardPass::Function, flags) DEFAULT_FUNCTION_PASS(CFGSimplification, StandardPass::OptimzationFlags(1)); @@ -87,7 +101,7 @@ #define DEFAULT_MODULE_PASS(pass, flags)\ StandardPass::RegisterDefaultPass(\ - PassInfo::NormalCtor_t(create ## pass ## Pass),\ + CreatePassFn,\ &DefaultStandardPasses::pass ## ID, 0, StandardPass::Module, flags) // Optimize out global vars DEFAULT_MODULE_PASS(GlobalOptimizer, @@ -119,10 +133,7 @@ DEFAULT_MODULE_PASS(ArgumentPromotion, StandardPass::OptimzationFlags(3)); // Start of function pass. // Break up aggregate allocas, using SSAUpdater. - StandardPass::RegisterDefaultPass( - PassInfo::NormalCtor_t(createDefaultScalarReplAggregatesPass), - &DefaultStandardPasses::ScalarReplAggregatesID, 0, - StandardPass::Module); + DEFAULT_MODULE_PASS(ScalarReplAggregates, 0); // Catch trivial redundancies DEFAULT_MODULE_PASS(EarlyCSE, 0); // Library Call Optimizations @@ -174,16 +185,10 @@ // Delete dead loops DEFAULT_MODULE_PASS(LoopDeletion, 0); // Unroll small loops - StandardPass::RegisterDefaultPass( - PassInfo::NormalCtor_t(createDefaultLoopUnrollPass), - &DefaultStandardPasses::LoopUnrollID, 0, - StandardPass::Module, - StandardPass::OptimzationFlags(0, 0, StandardPass::UnrollLoops)); + DEFAULT_MODULE_PASS(LoopUnroll, + StandardPass::OptimzationFlags(0, 0, StandardPass::UnrollLoops)); // Remove redundancies - StandardPass::RegisterDefaultPass( - PassInfo::NormalCtor_t(createDefaultGVNPass), - &DefaultStandardPasses::GVNID, 0, - StandardPass::Module, StandardPass::OptimzationFlags(2)); + DEFAULT_MODULE_PASS(GVN, StandardPass::OptimzationFlags(2)); // Remove memcpy / form memset DEFAULT_MODULE_PASS(MemCpyOpt, 0); // Constant prop with SCCP @@ -223,7 +228,8 @@ #define DEFAULT_LTO_PASS(pass, flags)\ StandardPass::RegisterDefaultPass(\ - PassInfo::NormalCtor_t(create ## pass ## Pass), &DefaultStandardPasses::pass ## ID, 0, StandardPass::LTO, flags) + CreatePassFn,\ + &DefaultStandardPasses::pass ## ID, 0, StandardPass::LTO, flags) // LTO passes From cdavis at mines.edu Wed May 18 17:48:24 2011 From: cdavis at mines.edu (Charles Davis) Date: Wed, 18 May 2011 22:48:24 -0000 Subject: [llvm-commits] [llvm] r131593 - /llvm/trunk/include/llvm/MC/MCWin64EH.h Message-ID: <20110518224824.BF75D2A6C12C@llvm.org> Author: cdavis Date: Wed May 18 17:48:24 2011 New Revision: 131593 URL: http://llvm.org/viewvc/llvm-project?rev=131593&view=rev Log: Add a header patterned after MCDwarf.h for supporting Win64 exception handling under MC. Added: llvm/trunk/include/llvm/MC/MCWin64EH.h - copied, changed from r131510, llvm/trunk/include/llvm/MC/MCDwarf.h Copied: llvm/trunk/include/llvm/MC/MCWin64EH.h (from r131510, llvm/trunk/include/llvm/MC/MCDwarf.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCWin64EH.h?p2=llvm/trunk/include/llvm/MC/MCWin64EH.h&p1=llvm/trunk/include/llvm/MC/MCDwarf.h&r1=131510&r2=131593&rev=131593&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCDwarf.h (original) +++ llvm/trunk/include/llvm/MC/MCWin64EH.h Wed May 18 17:48:24 2011 @@ -1,4 +1,4 @@ -//===- MCDwarf.h - Machine Code Dwarf support -------------------*- C++ -*-===// +//===- MCWin64EH.h - Machine Code Win64 EH support --------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -12,279 +12,79 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_MC_MCDWARF_H -#define LLVM_MC_MCDWARF_H +#ifndef LLVM_MC_MCWIN64EH_H +#define LLVM_MC_MCWIN64EH_H -#include "llvm/ADT/StringRef.h" #include "llvm/CodeGen/MachineLocation.h" // FIXME -#include "llvm/MC/MCObjectWriter.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/Support/Dwarf.h" +#include "llvm/Support/Win64EH.h" #include namespace llvm { - class TargetAsmInfo; - class MachineMove; - class MCContext; - class MCExpr; - class MCSection; - class MCSectionData; class MCStreamer; class MCSymbol; - class MCObjectStreamer; - class raw_ostream; - - /// MCDwarfFile - Instances of this class represent the name of the dwarf - /// .file directive and its associated dwarf file number in the MC file, - /// and MCDwarfFile's are created and unique'd by the MCContext class where - /// the file number for each is its index into the vector of DwarfFiles (note - /// index 0 is not used and not a valid dwarf file number). - class MCDwarfFile { - // Name - the base name of the file without its directory path. - // The StringRef references memory allocated in the MCContext. - StringRef Name; - - // DirIndex - the index into the list of directory names for this file name. - unsigned DirIndex; - - private: // MCContext creates and uniques these. - friend class MCContext; - MCDwarfFile(StringRef name, unsigned dirIndex) - : Name(name), DirIndex(dirIndex) {} - - MCDwarfFile(const MCDwarfFile&); // DO NOT IMPLEMENT - void operator=(const MCDwarfFile&); // DO NOT IMPLEMENT - public: - /// getName - Get the base name of this MCDwarfFile. - StringRef getName() const { return Name; } - - /// getDirIndex - Get the dirIndex of this MCDwarfFile. - unsigned getDirIndex() const { return DirIndex; } - - - /// print - Print the value to the stream \arg OS. - void print(raw_ostream &OS) const; - - /// dump - Print the value to stderr. - void dump() const; - }; - - inline raw_ostream &operator<<(raw_ostream &OS, const MCDwarfFile &DwarfFile){ - DwarfFile.print(OS); - return OS; - } - - /// MCDwarfLoc - Instances of this class represent the information from a - /// dwarf .loc directive. - class MCDwarfLoc { - // FileNum - the file number. - unsigned FileNum; - // Line - the line number. - unsigned Line; - // Column - the column position. - unsigned Column; - // Flags (see #define's below) - unsigned Flags; - // Isa - unsigned Isa; - // Discriminator - unsigned Discriminator; - -// Flag that indicates the initial value of the is_stmt_start flag. -#define DWARF2_LINE_DEFAULT_IS_STMT 1 - -#define DWARF2_FLAG_IS_STMT (1 << 0) -#define DWARF2_FLAG_BASIC_BLOCK (1 << 1) -#define DWARF2_FLAG_PROLOGUE_END (1 << 2) -#define DWARF2_FLAG_EPILOGUE_BEGIN (1 << 3) - - private: // MCContext manages these - friend class MCContext; - friend class MCLineEntry; - MCDwarfLoc(unsigned fileNum, unsigned line, unsigned column, unsigned flags, - unsigned isa, unsigned discriminator) - : FileNum(fileNum), Line(line), Column(column), Flags(flags), Isa(isa), - Discriminator(discriminator) {} - - // Allow the default copy constructor and assignment operator to be used - // for an MCDwarfLoc object. - - public: - /// getFileNum - Get the FileNum of this MCDwarfLoc. - unsigned getFileNum() const { return FileNum; } - - /// getLine - Get the Line of this MCDwarfLoc. - unsigned getLine() const { return Line; } - - /// getColumn - Get the Column of this MCDwarfLoc. - unsigned getColumn() const { return Column; } - - /// getFlags - Get the Flags of this MCDwarfLoc. - unsigned getFlags() const { return Flags; } - - /// getIsa - Get the Isa of this MCDwarfLoc. - unsigned getIsa() const { return Isa; } - - /// getDiscriminator - Get the Discriminator of this MCDwarfLoc. - unsigned getDiscriminator() const { return Discriminator; } - - /// setFileNum - Set the FileNum of this MCDwarfLoc. - void setFileNum(unsigned fileNum) { FileNum = fileNum; } - - /// setLine - Set the Line of this MCDwarfLoc. - void setLine(unsigned line) { Line = line; } - - /// setColumn - Set the Column of this MCDwarfLoc. - void setColumn(unsigned column) { Column = column; } - - /// setFlags - Set the Flags of this MCDwarfLoc. - void setFlags(unsigned flags) { Flags = flags; } - - /// setIsa - Set the Isa of this MCDwarfLoc. - void setIsa(unsigned isa) { Isa = isa; } - - /// setDiscriminator - Set the Discriminator of this MCDwarfLoc. - void setDiscriminator(unsigned discriminator) { - Discriminator = discriminator; - } - }; - - /// MCLineEntry - Instances of this class represent the line information for - /// the dwarf line table entries. Which is created after a machine - /// instruction is assembled and uses an address from a temporary label - /// created at the current address in the current section and the info from - /// the last .loc directive seen as stored in the context. - class MCLineEntry : public MCDwarfLoc { - MCSymbol *Label; - - private: - // Allow the default copy constructor and assignment operator to be used - // for an MCLineEntry object. + class MCWin64EHInstruction { public: - // Constructor to create an MCLineEntry given a symbol and the dwarf loc. - MCLineEntry(MCSymbol *label, const MCDwarfLoc loc) : MCDwarfLoc(loc), - Label(label) {} - - MCSymbol *getLabel() const { return Label; } - - // This is called when an instruction is assembled into the specified - // section and if there is information from the last .loc directive that - // has yet to have a line entry made for it is made. - static void Make(MCStreamer *MCOS, const MCSection *Section); - }; - - /// MCLineSection - Instances of this class represent the line information - /// for a section where machine instructions have been assembled after seeing - /// .loc directives. This is the information used to build the dwarf line - /// table for a section. - class MCLineSection { - - private: - MCLineSection(const MCLineSection&); // DO NOT IMPLEMENT - void operator=(const MCLineSection&); // DO NOT IMPLEMENT - - public: - // Constructor to create an MCLineSection with an empty MCLineEntries - // vector. - MCLineSection() {} - - // addLineEntry - adds an entry to this MCLineSection's line entries - void addLineEntry(const MCLineEntry &LineEntry) { - MCLineEntries.push_back(LineEntry); - } - - typedef std::vector MCLineEntryCollection; - typedef MCLineEntryCollection::iterator iterator; - typedef MCLineEntryCollection::const_iterator const_iterator; - - private: - MCLineEntryCollection MCLineEntries; - - public: - const MCLineEntryCollection *getMCLineEntries() const { - return &MCLineEntries; - } - }; - - class MCDwarfFileTable { - public: - // - // This emits the Dwarf file and the line tables. - // - static void Emit(MCStreamer *MCOS); - }; - - class MCDwarfLineAddr { - public: - /// Utility function to encode a Dwarf pair of LineDelta and AddrDeltas. - static void Encode(int64_t LineDelta, uint64_t AddrDelta, raw_ostream &OS); - - /// Utility function to emit the encoding to a streamer. - static void Emit(MCStreamer *MCOS, - int64_t LineDelta,uint64_t AddrDelta); - - /// Utility function to write the encoding to an object writer. - static void Write(MCObjectWriter *OW, - int64_t LineDelta, uint64_t AddrDelta); - }; - - class MCCFIInstruction { - public: - enum OpType { SameValue, Remember, Restore, Move, RelMove }; + typedef Win64EH::UnwindOpcodes OpType; private: OpType Operation; - MCSymbol *Label; - // Move to & from location. + unsigned Offset; MachineLocation Destination; MachineLocation Source; public: - MCCFIInstruction(OpType Op, MCSymbol *L) - : Operation(Op), Label(L) { - assert(Op == Remember || Op == Restore); - } - MCCFIInstruction(OpType Op, MCSymbol *L, unsigned Register) - : Operation(Op), Label(L), Destination(Register) { - assert(Op == SameValue); - } - MCCFIInstruction(MCSymbol *L, const MachineLocation &D, - const MachineLocation &S) - : Operation(Move), Label(L), Destination(D), Source(S) { - } - MCCFIInstruction(OpType Op, MCSymbol *L, const MachineLocation &D, - const MachineLocation &S) - : Operation(Op), Label(L), Destination(D), Source(S) { - assert(Op == RelMove); + MCWin64EHInstruction(OpType Op, unsigned Register) + : Operation(Op), Offset(0), Destination(0), Source(S) { + assert(Op == Win64EH::UOP_PushNonVol); + } + MCWin64EHInstruction(unsigned Size) + : Operation(Size>128 ? Win64EH::UOP_AllocLarge : Win64EH::UOP_AllocSmall), + Offset(size) { } + MCWin64EHInstruction(unsigned Register, unsigned Off) + : Operation(Win64EH::UOP_SetFPReg), Offset(Off), Destination(Register) { } + MCWin64EHInstruction(OpType Op, const MachineLocation &D, + unsigned S) + : Operation(Op), Destination(D), Source(S) { + assert(Op == Win64EH::UOP_SaveNonVol || + Op == Win64EH::UOP_SaveNonVolBig || + Op == Win64EH::UOP_SaveXMM128 || + Op == Win64EH::UOP_SaveXMM128Big); + } + MCWin64EHInstruction(OpType Op, bool Code) + : Operation(Op), Offset(Code ? 1 : 0) { + assert(Op == Win64EH::UOP_PushMachFrame); } OpType getOperation() const { return Operation; } - MCSymbol *getLabel() const { return Label; } + unsigned getOffset() const { return Offset; } + unsigned getSize() const { return Offset; } + bool isPushCodeFrame() const { return Offset == 1; } const MachineLocation &getDestination() const { return Destination; } const MachineLocation &getSource() const { return Source; } }; - struct MCDwarfFrameInfo { - MCDwarfFrameInfo() : Begin(0), End(0), Personality(0), Lsda(0), - Function(0), Instructions(), PersonalityEncoding(), - LsdaEncoding(0) {} + struct MCWin64EHUnwindInfo { + MCWin64EHUnwindInfo() : Begin(0), End(0), ExceptionHandler(0), Lsda(0), + Function(0), UnwindOnly(false), LsdaSize(0), + PrologSize(0), LastFrameInst(-1), Chained(false) + Instructions() {} MCSymbol *Begin; MCSymbol *End; - const MCSymbol *Personality; + const MCSymbol *ExceptionHandler; const MCSymbol *Lsda; const MCSymbol *Function; - std::vector Instructions; - unsigned PersonalityEncoding; - unsigned LsdaEncoding; + bool UnwindOnly; + unsigned LsdaSize; + unsigned PrologSize; + int LastFrameInst; + bool Chained; + std::vector Instructions; }; - class MCDwarfFrameEmitter { + class MCWin64EHUnwindEmitter { public: // - // This emits the frame info section. + // This emits the unwind info section (.xdata in PE/COFF). // - static void Emit(MCStreamer &streamer, bool usingCFI, - bool isEH); - static void EmitAdvanceLoc(MCStreamer &Streamer, uint64_t AddrDelta); - static void EncodeAdvanceLoc(uint64_t AddrDelta, raw_ostream &OS); + static void Emit(MCStreamer &streamer); }; } // end namespace llvm From zwarich at apple.com Wed May 18 18:03:10 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 18 May 2011 23:03:10 -0000 Subject: [llvm-commits] [llvm] r131595 - /llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Message-ID: <20110518230310.9DBAC2A6C12C@llvm.org> Author: zwarich Date: Wed May 18 18:03:10 2011 New Revision: 131595 URL: http://llvm.org/viewvc/llvm-project?rev=131595&view=rev Log: Add missing mayLoad / mayStore flags to instruction definitions without patterns, which fixes all of the CodeGen/MBlaze verifier failures. Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td?rev=131595&r1=131594&r2=131595&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.td Wed May 18 18:03:10 2011 @@ -245,20 +245,25 @@ //===----------------------------------------------------------------------===// // Memory Access Instructions //===----------------------------------------------------------------------===// + +let mayLoad = 1 in { class LoadM op, bits<11> flags, string instr_asm> : TA; +} class LoadMI op, string instr_asm, PatFrag OpNode> : TB; +let mayStore = 1 in { class StoreM op, bits<11> flags, string instr_asm> : TA; +} class StoreMI op, string instr_asm, PatFrag OpNode> : TB Author: efriedma Date: Wed May 18 18:11:30 2011 New Revision: 131596 URL: http://llvm.org/viewvc/llvm-project?rev=131596&view=rev Log: More instcombine simplifications towards better debug locations. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=131596&r1=131595&r2=131596&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed May 18 18:11:30 2011 @@ -722,18 +722,39 @@ // Only handle register returns for now. if (!VA.isRegLoc()) return false; - // TODO: For now, don't try to handle cases where getLocInfo() - // says Full but the types don't match. - if (TLI.getValueType(RV->getType()) != VA.getValVT()) - return false; // The calling-convention tables for x87 returns don't tell // the whole story. if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) return false; - // Make the copy. unsigned SrcReg = Reg + VA.getValNo(); + EVT SrcVT = TLI.getValueType(RV->getType()); + EVT DstVT = VA.getValVT(); + // Special handling for extended integers. + if (SrcVT != DstVT) { + return false; + if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) + return false; + + if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) + return false; + + assert(DstVT == MVT::i32 && "X86 should always ext to i32"); + + if (SrcVT == MVT::i1) { + if (Outs[0].Flags.isSExt()) + return false; + SrcReg = FastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false); + SrcVT = MVT::i8; + } + unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : + ISD::SIGN_EXTEND; + SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, + SrcReg, /*TODO: Kill=*/false); + } + + // Make the copy. unsigned DstReg = VA.getLocReg(); const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); // Avoid a cross-class copy. This is very unlikely. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp?rev=131596&r1=131595&r2=131596&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp Wed May 18 18:11:30 2011 @@ -1684,8 +1684,7 @@ // If we found a path from the src to dest, create the getelementptr now. if (SrcElTy == DstElTy) { SmallVector Idxs(NumZeros+1, ZeroUInt); - return GetElementPtrInst::CreateInBounds(Src, Idxs.begin(), Idxs.end(),"", - ((Instruction*)NULL)); + return GetElementPtrInst::CreateInBounds(Src, Idxs.begin(), Idxs.end()); } } Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp?rev=131596&r1=131595&r2=131596&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCompares.cpp Wed May 18 18:11:30 2011 @@ -469,8 +469,7 @@ /// /// If we can't emit an optimized form for this expression, this returns null. /// -static Value *EvaluateGEPOffsetExpression(User *GEP, Instruction &I, - InstCombiner &IC) { +static Value *EvaluateGEPOffsetExpression(User *GEP, InstCombiner &IC) { TargetData &TD = *IC.getTargetData(); gep_type_iterator GTI = gep_type_begin(GEP); @@ -533,10 +532,10 @@ // Cast to intptrty in case a truncation occurs. If an extension is needed, // we don't need to bother extending: the extension won't affect where the // computation crosses zero. - if (VariableIdx->getType()->getPrimitiveSizeInBits() > IntPtrWidth) - VariableIdx = new TruncInst(VariableIdx, - TD.getIntPtrType(VariableIdx->getContext()), - VariableIdx->getName(), &I); + if (VariableIdx->getType()->getPrimitiveSizeInBits() > IntPtrWidth) { + const Type *IntPtrTy = TD.getIntPtrType(VariableIdx->getContext()); + VariableIdx = IC.Builder->CreateTrunc(VariableIdx, IntPtrTy); + } return VariableIdx; } @@ -558,11 +557,10 @@ // Okay, we can do this evaluation. Start by converting the index to intptr. const Type *IntPtrTy = TD.getIntPtrType(VariableIdx->getContext()); if (VariableIdx->getType() != IntPtrTy) - VariableIdx = CastInst::CreateIntegerCast(VariableIdx, IntPtrTy, - true /*SExt*/, - VariableIdx->getName(), &I); + VariableIdx = IC.Builder->CreateIntCast(VariableIdx, IntPtrTy, + true /*Signed*/); Constant *OffsetVal = ConstantInt::get(IntPtrTy, NewOffs); - return BinaryOperator::CreateAdd(VariableIdx, OffsetVal, "offset", &I); + return IC.Builder->CreateAdd(VariableIdx, OffsetVal, "offset"); } /// FoldGEPICmp - Fold comparisons between a GEP instruction and something @@ -580,7 +578,7 @@ // This transformation (ignoring the base and scales) is valid because we // know pointers can't overflow since the gep is inbounds. See if we can // output an optimized form. - Value *Offset = EvaluateGEPOffsetExpression(GEPLHS, I, *this); + Value *Offset = EvaluateGEPOffsetExpression(GEPLHS, *this); // If not, synthesize the offset the hard way. if (Offset == 0) From eli.friedman at gmail.com Wed May 18 18:13:10 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 23:13:10 -0000 Subject: [llvm-commits] [llvm] r131597 - /llvm/trunk/lib/Target/X86/X86FastISel.cpp Message-ID: <20110518231310.5AD7D2A6C12C@llvm.org> Author: efriedma Date: Wed May 18 18:13:10 2011 New Revision: 131597 URL: http://llvm.org/viewvc/llvm-project?rev=131597&view=rev Log: Revert unintentional commit. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=131597&r1=131596&r2=131597&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Wed May 18 18:13:10 2011 @@ -722,39 +722,18 @@ // Only handle register returns for now. if (!VA.isRegLoc()) return false; + // TODO: For now, don't try to handle cases where getLocInfo() + // says Full but the types don't match. + if (TLI.getValueType(RV->getType()) != VA.getValVT()) + return false; // The calling-convention tables for x87 returns don't tell // the whole story. if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) return false; - unsigned SrcReg = Reg + VA.getValNo(); - EVT SrcVT = TLI.getValueType(RV->getType()); - EVT DstVT = VA.getValVT(); - // Special handling for extended integers. - if (SrcVT != DstVT) { - return false; - if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) - return false; - - if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) - return false; - - assert(DstVT == MVT::i32 && "X86 should always ext to i32"); - - if (SrcVT == MVT::i1) { - if (Outs[0].Flags.isSExt()) - return false; - SrcReg = FastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false); - SrcVT = MVT::i8; - } - unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : - ISD::SIGN_EXTEND; - SrcReg = FastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, - SrcReg, /*TODO: Kill=*/false); - } - // Make the copy. + unsigned SrcReg = Reg + VA.getValNo(); unsigned DstReg = VA.getLocReg(); const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); // Avoid a cross-class copy. This is very unlikely. From dpatel at apple.com Wed May 18 18:18:48 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 23:18:48 -0000 Subject: [llvm-commits] [llvm] r131598 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110518231848.132F92A6C12C@llvm.org> Author: dpatel Date: Wed May 18 18:18:47 2011 New Revision: 131598 URL: http://llvm.org/viewvc/llvm-project?rev=131598&view=rev Log: Use IRBuilder while simplifying branch. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131598&r1=131597&r2=131598&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 18:18:47 2011 @@ -2023,7 +2023,8 @@ /// SimplifyBranchOnICmpChain - The specified branch is a conditional branch. /// Check to see if it is branching on an or/and chain of icmp instructions, and /// fold it into a switch instruction if so. -static bool SimplifyBranchOnICmpChain(BranchInst *BI, const TargetData *TD) { +static bool SimplifyBranchOnICmpChain(BranchInst *BI, const TargetData *TD, + IRBuilder<> &Builder) { Instruction *Cond = dyn_cast(BI->getCondition()); if (Cond == 0) return false; @@ -2079,11 +2080,12 @@ BasicBlock *NewBB = BB->splitBasicBlock(BI, "switch.early.test"); // Remove the uncond branch added to the old block. TerminatorInst *OldTI = BB->getTerminator(); - + Builder.SetInsertPoint(OldTI); + if (TrueWhenEqual) - BranchInst::Create(EdgeBB, NewBB, ExtraCase, OldTI); + Builder.CreateCondBr(ExtraCase, EdgeBB, NewBB); else - BranchInst::Create(NewBB, EdgeBB, ExtraCase, OldTI); + Builder.CreateCondBr(ExtraCase, NewBB, EdgeBB); OldTI->eraseFromParent(); @@ -2095,19 +2097,18 @@ << "\nEXTRABB = " << *BB); BB = NewBB; } - + + Builder.SetInsertPoint(BI); // Convert pointer to int before we switch. if (CompVal->getType()->isPointerTy()) { assert(TD && "Cannot switch on pointer without TargetData"); - CompVal = new PtrToIntInst(CompVal, - TD->getIntPtrType(CompVal->getContext()), - "magicptr", BI); - cast(CompVal)->setDebugLoc(BI->getDebugLoc()); + CompVal = Builder.CreatePtrToInt(CompVal, + TD->getIntPtrType(CompVal->getContext()), + "magicptr"); } // Create the new switch instruction now. - SwitchInst *New = SwitchInst::Create(CompVal, DefaultBB, Values.size(), BI); - New->setDebugLoc(BI->getDebugLoc()); + SwitchInst *New = Builder.CreateSwitch(CompVal, DefaultBB, Values.size()); // Add all of the 'cases' to the switch instruction. for (unsigned i = 0, e = Values.size(); i != e; ++i) @@ -2574,7 +2575,7 @@ } // Try to turn "br (X == 0 | X == 1), T, F" into a switch instruction. - if (SimplifyBranchOnICmpChain(BI, TD)) + if (SimplifyBranchOnICmpChain(BI, TD, Builder)) return true; // We have a conditional branch to two blocks that are only reachable From echristo at apple.com Wed May 18 18:24:33 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 18 May 2011 23:24:33 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r131599 - /llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Message-ID: <20110518232433.192412A6C12C@llvm.org> Author: echristo Date: Wed May 18 18:24:32 2011 New Revision: 131599 URL: http://llvm.org/viewvc/llvm-project?rev=131599&view=rev Log: Translate reg_names if necessary, otherwise preserve the register name that the user provided. Fixes part of rdar://9088139 Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=131599&r1=131598&r2=131599&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Wed May 18 18:24:32 2011 @@ -3600,12 +3600,13 @@ /* LLVM_GET_REG_NAME - The registers known to llvm as "r10", "r11", and "r12" may have different names in GCC. Register "r12" is called "ip", and on non-Darwin OSs, "r10" is "sl" and "r11" is "fp". Translate those names, - and use the default register names for everything else. */ + and use incoming register name if it exists otherwise since reg_names doesn't + distinguish between the q and d registers. */ #define LLVM_GET_REG_NAME(REG_NAME, REG_NUM) \ ((REG_NUM) == 10 ? "r10" \ : (REG_NUM) == 11 ? "r11" \ : (REG_NUM) == 12 ? "r12" \ - : reg_names[REG_NUM]) + : (REG_NAME ? REG_NAME : reg_names[REG_NUM])) #endif /* ENABLE_LLVM */ /* LLVM LOCAL end */ From rafael.espindola at gmail.com Wed May 18 18:30:29 2011 From: rafael.espindola at gmail.com (Rafael Avila de Espindola) Date: Wed, 18 May 2011 19:30:29 -0400 Subject: [llvm-commits] [llvm] r131576 - in /llvm/trunk: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll In-Reply-To: <20110518210219.1AD8A2A6C12C@llvm.org> References: <20110518210219.1AD8A2A6C12C@llvm.org> Message-ID: <4DD45695.8090303@gmail.com> On 11-05-18 05:02 PM, Dan Gohman wrote: > Author: djg > Date: Wed May 18 16:02:18 2011 > New Revision: 131576 > > URL: http://llvm.org/viewvc/llvm-project?rev=131576&view=rev > Log: > When forming an ICmpZero LSRUse, normalize the non-IV operand > of the comparison, so that the resulting expression is fully > normalized. This fixes PR9939. Thanks! > +; CHECK: %tmp2 = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast > +; CHECK: %tmp3 = lshr i64 %tmp2, 1 > +; CHECK: %tmp4 = mul i64 %tmp3, 2 > +; CHECK: br label %for.body > +; CHECK: for.body: > +; CHECK: %lsr.iv5 = phi i64 [ %lsr.iv.next, %for.body ], [ %tmp4, %for.body.lr.ph ] > +; CHECK: %lsr.iv.next = add i64 %lsr.iv5, -2 > +; CHECK: %lsr.iv.next6 = inttoptr i64 %lsr.iv.next to i16* > +; CHECK: %cmp27 = icmp eq i16* %lsr.iv.next6, null > Don't you want a CHECK-NEXT here to check that the old %tmp8 = add i64 %tmp7, -2 is not being created? Cheers, Rafael From jasonwkim at google.com Wed May 18 18:45:13 2011 From: jasonwkim at google.com (Jason Kim) Date: Wed, 18 May 2011 16:45:13 -0700 Subject: [llvm-commits] [llvm] r131205 - in /llvm/trunk/lib/MC: ELFObjectWriter.cpp ELFObjectWriter.h In-Reply-To: References: <20110511225306.571622A6C12C@llvm.org> Message-ID: On Wed, May 18, 2011 at 2:11 PM, Nick Lewycky wrote: > Jason, do you have a testcase for this? I'd like to figure out how GNU as > knows what to do so that we can remove the flag, but I can't be sure I'm > looking at the right thing without a testcase. I'll get you a test case - its in PNaCl land and requires comparing the text differences from multiple .o files for he MC.o versus MC.s->gas->.o path Thanks > > On 11 May 2011 15:53, Jason W Kim wrote: >> >> Author: jasonwkim >> Date: Wed May 11 17:53:06 2011 >> New Revision: 131205 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=131205&view=rev >> Log: >> Address the last bit of relocation flag related divergence betweeen >> LLVM and binutils. >> >> With this patch, there are no functional differences between the .o >> produced directly from LLVM versus the .s to .o via GNU as, for relocation >> tags >> at least, for both PIC and non-PIC modes. >> >> Because some non-PIC reloc tags are used (legally) on PIC, so IsPCRel flag >> is >> necessary but not sufficient to determine whether the overall codegen mode >> is >> PIC or not. Why is this necessary? There is an incompatibility of how >> relocs >> are emitted in the .rodata section. ?Binutils PIC likes to emit certain >> relocs >> as section relative offsets. ?Non-PIC does not do this. >> >> So I added a hidden switch on the ELFObjectwriter "-arm-elf-force-pic" >> which >> forces the objectwriter to pretend that all relocs are for PIC mode. >> >> >> Todo: Activate ForceARMElfPIC to true if -relocation-model=pic is selected >> on llc. >> >> Todo: There are probably more issues for PIC mode on ARM/MC/ELF... >> >> Todo: Existing tests in MC/ARM/elf-reloc*.ll need to be converted over to >> .s >> tests as well as expanded to cover the gamut. >> >> >> Modified: >> ? ?llvm/trunk/lib/MC/ELFObjectWriter.cpp >> ? ?llvm/trunk/lib/MC/ELFObjectWriter.h >> >> Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=131205&r1=131204&r2=131205&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) >> +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Wed May 11 17:53:06 2011 >> @@ -25,6 +25,8 @@ >> ?#include "llvm/Support/ELF.h" >> ?#include "llvm/Target/TargetAsmBackend.h" >> ?#include "llvm/ADT/StringSwitch.h" >> +#include "llvm/Support/CommandLine.h" >> +#include "llvm/ADT/Statistic.h" >> >> ?#include "../Target/X86/X86FixupKinds.h" >> ?#include "../Target/ARM/ARMFixupKinds.h" >> @@ -32,6 +34,16 @@ >> ?#include >> ?using namespace llvm; >> >> +#undef ?DEBUG_TYPE >> +#define DEBUG_TYPE "reloc-info" >> + >> +// Emulate the wierd behavior of GNU-as for relocation types >> +namespace llvm { >> +cl::opt >> +ForceARMElfPIC("arm-elf-force-pic", cl::Hidden, cl::init(false), >> + ? ? ? ? ? ? ? cl::desc("Force ELF emitter to emit PIC style >> relocations")); >> +} >> + >> ?bool ELFObjectWriter::isFixupKindPCRel(const MCAssembler &Asm, unsigned >> Kind) { >> ? const MCFixupKindInfo &FKI = >> ? ? Asm.getBackend().getFixupKindInfo((MCFixupKind) Kind); >> @@ -319,7 +331,9 @@ >> >> ?const MCSymbol *ELFObjectWriter::SymbolToReloc(const MCAssembler &Asm, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCValue &Target, >> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MCFragment &F) const >> { >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MCFragment &F, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MCFixup &Fixup, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool IsPCRel) const { >> ? const MCSymbol &Symbol = Target.getSymA()->getSymbol(); >> ? const MCSymbol &ASymbol = Symbol.AliasedSymbol(); >> ? const MCSymbol *Renamed = Renames.lookup(&Symbol); >> @@ -342,7 +356,7 @@ >> ? const SectionKind secKind = Section.getKind(); >> >> ? if (secKind.isBSS()) >> - ? ?return ExplicitRelSym(Asm, Target, F, true); >> + ? ?return ExplicitRelSym(Asm, Target, F, Fixup, IsPCRel); >> >> ? if (secKind.isThreadLocal()) { >> ? ? if (Renamed) >> @@ -365,13 +379,14 @@ >> >> ? if (Section.getFlags() & ELF::SHF_MERGE) { >> ? ? if (Target.getConstant() == 0) >> - ? ? ?return NULL; >> + ? ? ?return ExplicitRelSym(Asm, Target, F, Fixup, IsPCRel); >> ? ? if (Renamed) >> ? ? ? return Renamed; >> ? ? return &Symbol; >> ? } >> >> - ?return ExplicitRelSym(Asm, Target, F, false); >> + ?return ExplicitRelSym(Asm, Target, F, Fixup, IsPCRel); >> + >> ?} >> >> >> @@ -390,7 +405,7 @@ >> ? if (!Target.isAbsolute()) { >> ? ? const MCSymbol &Symbol = Target.getSymA()->getSymbol(); >> ? ? const MCSymbol &ASymbol = Symbol.AliasedSymbol(); >> - ? ?RelocSymbol = SymbolToReloc(Asm, Target, *Fragment); >> + ? ?RelocSymbol = SymbolToReloc(Asm, Target, *Fragment, Fixup, IsPCRel); >> >> ? ? if (const MCSymbolRefExpr *RefB = Target.getSymB()) { >> ? ? ? const MCSymbol &SymbolB = RefB->getSymbol(); >> @@ -1261,32 +1276,93 @@ >> >> ?// In ARM, _MergedGlobals and other most symbols get emitted directly. >> ?// I.e. not as an offset to a section symbol. >> -// This code is a first-cut approximation of what ARM/gcc does. >> +// This code is an approximation of what ARM/gcc does. >> + >> +STATISTIC(PCRelCount, "Total number of PIC Relocations"); >> +STATISTIC(NonPCRelCount, "Total number of non-PIC relocations"); >> >> ?const MCSymbol *ARMELFObjectWriter::ExplicitRelSym(const MCAssembler >> &Asm, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCValue &Target, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCFragment &F, >> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool IsBSS) const { >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MCFixup &Fixup, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool IsPCRel) const { >> ? const MCSymbol &Symbol = Target.getSymA()->getSymbol(); >> ? bool EmitThisSym = false; >> >> - ?if (IsBSS) { >> - ? ?EmitThisSym = StringSwitch(Symbol.getName()) >> - ? ? ?.Case("_MergedGlobals", true) >> - ? ? ?.Default(false); >> + ?const MCSectionELF &Section = >> + ? ?static_cast(Symbol.getSection()); >> + ?const SectionKind secKind = Section.getKind(); >> + ?const MCSymbolRefExpr::VariantKind Kind = Target.getSymA()->getKind(); >> + ?MCSymbolRefExpr::VariantKind Kind2; >> + ?Kind2 = Target.getSymB() ? ?Target.getSymB()->getKind() : >> + ? ?MCSymbolRefExpr::VK_None; >> + ?bool InNormalSection = true; >> + ?unsigned RelocType = 0; >> + ?RelocType = GetRelocTypeInner(Target, Fixup, IsPCRel); >> + >> + ?DEBUG(dbgs() << "considering symbol " >> + ? ? ? ?<< Section.getSectionName() << "/" >> + ? ? ? ?<< Symbol.getName() << "/" >> + ? ? ? ?<< " Rel:" << (unsigned)RelocType >> + ? ? ? ?<< " Kind: " << (int)Kind << "/" << (int)Kind2 >> + ? ? ? ?<< " Tmp:" >> + ? ? ? ?<< Symbol.isAbsolute() << "/" << Symbol.isDefined() << "/" >> + ? ? ? ?<< Symbol.isVariable() << "/" << Symbol.isTemporary() >> + ? ? ? ?<< " Counts:" << PCRelCount << "/" << NonPCRelCount << "\n"); >> + >> + ?if (IsPCRel || ForceARMElfPIC) { ++PCRelCount; >> + ? ?switch (RelocType) { >> + ? ?default: >> + ? ? ?// Most relocation types are emitted as explicit symbols >> + ? ? ?InNormalSection = >> + ? ? ? ?StringSwitch(Section.getSectionName()) >> + ? ? ? ?.Case(".data.rel.ro.local", false) >> + ? ? ? ?.Case(".data.rel", false) >> + ? ? ? ?.Case(".bss", false) >> + ? ? ? ?.Default(true); >> + ? ? ?EmitThisSym = true; >> + ? ? ?break; >> + ? ?case ELF::R_ARM_ABS32: >> + ? ? ?// But things get strange with R_ARM_ABS32 >> + ? ? ?// In this case, most things that go in .rodata show up >> + ? ? ?// as section relative relocations >> + ? ? ?InNormalSection = >> + ? ? ? ?StringSwitch(Section.getSectionName()) >> + ? ? ? ?.Case(".data.rel.ro.local", false) >> + ? ? ? ?.Case(".data.rel", false) >> + ? ? ? ?.Case(".rodata", false) >> + ? ? ? ?.Case(".bss", false) >> + ? ? ? ?.Default(true); >> + ? ? ?EmitThisSym = false; >> + ? ? ?break; >> + ? ?} >> ? } else { >> - ? ?EmitThisSym = StringSwitch(Symbol.getName()) >> - ? ? ?.Case("_MergedGlobals", true) >> - ? ? ?.StartsWith(".L.str", true) >> - ? ? ?.Default(false); >> + ? ?NonPCRelCount++; >> + ? ?InNormalSection = >> + ? ? ?StringSwitch(Section.getSectionName()) >> + ? ? ?.Case(".data.rel.ro.local", false) >> + ? ? ?.Case(".rodata", false) >> + ? ? ?.Case(".data.rel", false) >> + ? ? ?.Case(".bss", false) >> + ? ? ?.Default(true); >> + >> + ? ?switch (RelocType) { >> + ? ?default: EmitThisSym = true; break; >> + ? ?case ELF::R_ARM_ABS32: EmitThisSym = false; break; >> + ? ?} >> ? } >> + >> ? if (EmitThisSym) >> ? ? return &Symbol; >> - ?if (! Symbol.isTemporary()) >> + ?if (! Symbol.isTemporary() && InNormalSection) { >> ? ? return &Symbol; >> + ?} >> ? return NULL; >> ?} >> >> +// Need to examine the Fixup when determining whether to >> +// emit the relocation as an explicit symbol or as a section relative >> +// offset >> ?unsigned ARMELFObjectWriter::GetRelocType(const MCValue &Target, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MCFixup &Fixup, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool IsPCRel, >> @@ -1295,6 +1371,20 @@ >> ? MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? >> ? ? MCSymbolRefExpr::VK_None : Target.getSymA()->getKind(); >> >> + ?unsigned Type = GetRelocTypeInner(Target, Fixup, IsPCRel); >> + >> + ?if (RelocNeedsGOT(Modifier)) >> + ? ?NeedsGOT = true; >> + >> + ?return Type; >> +} >> + >> +unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MCFixup &Fixup, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool IsPCRel) const ?{ >> + ?MCSymbolRefExpr::VariantKind Modifier = Target.isAbsolute() ? >> + ? ?MCSymbolRefExpr::VK_None : Target.getSymA()->getKind(); >> + >> ? unsigned Type = 0; >> ? if (IsPCRel) { >> ? ? switch ((unsigned)Fixup.getKind()) { >> @@ -1303,7 +1393,7 @@ >> ? ? ? switch (Modifier) { >> ? ? ? default: llvm_unreachable("Unsupported Modifier"); >> ? ? ? case MCSymbolRefExpr::VK_None: >> - ? ? ? ?Type = ELF::R_ARM_BASE_PREL; >> + ? ? ? ?Type = ELF::R_ARM_REL32; >> ? ? ? ? break; >> ? ? ? case MCSymbolRefExpr::VK_ARM_TLSGD: >> ? ? ? ? assert(0 && "unimplemented"); >> @@ -1399,9 +1489,6 @@ >> ? ? } >> ? } >> >> - ?if (RelocNeedsGOT(Modifier)) >> - ? ?NeedsGOT = true; >> - >> ? return Type; >> ?} >> >> >> Modified: llvm/trunk/lib/MC/ELFObjectWriter.h >> URL: >> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.h?rev=131205&r1=131204&r2=131205&view=diff >> >> ============================================================================== >> --- llvm/trunk/lib/MC/ELFObjectWriter.h (original) >> +++ llvm/trunk/lib/MC/ELFObjectWriter.h Wed May 11 17:53:06 2011 >> @@ -140,15 +140,18 @@ >> ? ? unsigned ShstrtabIndex; >> >> >> - ? ?const MCSymbol *SymbolToReloc(const MCAssembler &Asm, >> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCValue &Target, >> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCFragment &F) const; >> + ? ?virtual const MCSymbol *SymbolToReloc(const MCAssembler &Asm, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCValue &Target, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCFragment &F, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCFixup &Fixup, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool IsPCRel) const; >> >> ? ? // For arch-specific emission of explicit reloc symbol >> ? ? virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCValue &Target, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCFragment &F, >> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool IsBSS) const { >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MCFixup &Fixup, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool IsPCRel) const { >> ? ? ? return NULL; >> ? ? } >> >> @@ -380,11 +383,16 @@ >> ? ? virtual const MCSymbol *ExplicitRelSym(const MCAssembler &Asm, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCValue &Target, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const MCFragment &F, >> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool IsBSS) const; >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MCFixup &Fixup, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool IsPCRel) const; >> >> ? ? virtual unsigned GetRelocType(const MCValue &Target, const MCFixup >> &Fixup, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool IsPCRel, bool IsRelocWithSymbol, >> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? int64_t Addend); >> + ?private: >> + ? ?unsigned GetRelocTypeInner(const MCValue &Target, >> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const MCFixup &Fixup, bool IsPCRel) const; >> + >> ? }; >> >> ? //===- MBlazeELFObjectWriter >> -------------------------------------------===// >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From eli.friedman at gmail.com Wed May 18 18:51:11 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 23:51:11 -0000 Subject: [llvm-commits] [llvm] r131600 - in /llvm/trunk/lib: Support/StandardPasses.cpp VMCore/CMakeLists.txt VMCore/StandardPasses.cpp Message-ID: <20110518235112.0C9902A6C12C@llvm.org> Author: efriedma Date: Wed May 18 18:51:11 2011 New Revision: 131600 URL: http://llvm.org/viewvc/llvm-project?rev=131600&view=rev Log: Shuffle StandardPasses.cpp into VMCore; add it to CMake. Added: llvm/trunk/lib/VMCore/StandardPasses.cpp - copied unchanged from r131597, llvm/trunk/lib/Support/StandardPasses.cpp Removed: llvm/trunk/lib/Support/StandardPasses.cpp Modified: llvm/trunk/lib/VMCore/CMakeLists.txt Removed: llvm/trunk/lib/Support/StandardPasses.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/StandardPasses.cpp?rev=131599&view=auto ============================================================================== --- llvm/trunk/lib/Support/StandardPasses.cpp (original) +++ llvm/trunk/lib/Support/StandardPasses.cpp (removed) @@ -1,247 +0,0 @@ -//===-- lib/Support/StandardPasses.cpp - Standard pass lists -----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines utility functions for creating a "standard" set of -// optimization passes, so that compilers and tools which use optimization -// passes use the same set of standard passes. -// -// This allows the creation of multiple standard sets, and their later -// modification by plugins and front ends. -// -//===----------------------------------------------------------------------===// - -#include "llvm/PassManager.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/ManagedStatic.h" -#include "llvm/DefaultPasses.h" -#include "llvm/Support/Mutex.h" - -using namespace llvm::DefaultStandardPasses; -using namespace llvm; - -namespace { - -/// Entry in the standard passes list. -struct StandardPassEntry { - /// Function called to create the pass - PassInfo::NormalCtor_t createPass; - /// Unique identifier for this pass - unsigned char *passID; - /// Flags specifying when this pass should be run - unsigned flags; - - StandardPassEntry(PassInfo::NormalCtor_t constructor, unsigned char *ID, - unsigned f) : createPass(constructor), passID(ID), flags(f) {}; -}; - -/// Standard alias analysis passes -static llvm::SmallVector AAPasses; -/// Standard function passes -static llvm::SmallVector FunctionPasses; -/// Standard module passes -static llvm::SmallVector ModulePasses; -/// Standard link-time optimization passes -static llvm::SmallVector LTOPasses; - -/// Entry in the unresolved standard pass list. IF a pass is inserted in front -/// of a pass that is not yet registered in the standard pass list then it is -/// stored in a separate list and resolved later. -struct UnresolvedStandardPass : public StandardPassEntry { - /// The set into which this is stored - StandardPass::StandardSet set; - /// The unique ID of the pass that should follow this one in the sequence - unsigned char *next; - UnresolvedStandardPass(PassInfo::NormalCtor_t constructor, - unsigned char *newPass, - unsigned char *oldPass, - StandardPass::StandardSet s, - unsigned f) : - StandardPassEntry(constructor, newPass, f), set(s), next(oldPass) {} -}; - -/// The passes that can not be inserted into the correct lists yet because of -/// their place in the sequence. -static llvm::SmallVector UnresolvedPasses; - -/// Returns a reference to the pass list for the corresponding set of -/// optimisations. -llvm::SmallVectorImpl& -PassList(StandardPass::StandardSet set) { - switch (set) { - case StandardPass::AliasAnalysis: return AAPasses; - case StandardPass::Function: return FunctionPasses; - case StandardPass::Module: return ModulePasses; - case StandardPass::LTO: return LTOPasses; - } - // We could use a map of standard pass lists to allow definition of new - // default sets - llvm_unreachable("Invalid standard optimization set requested"); -} - -static ManagedStatic > Lock; - -/// Registers the default set of standard passes. This is called lazily when -/// an attempt is made to read or modify the standard pass list -void RegisterDefaultStandardPasses(void(*doRegister)(void)) { - // Only initialize the standard passes once - static volatile bool initialized = false; - if (initialized) return; - - llvm::sys::SmartScopedLock Guard(*Lock); - if (initialized) return; - if (doRegister) { - assert("No passes registered before setting default passes" && - AAPasses.size() == 0 && - FunctionPasses.size() == 0 && - LTOPasses.size() == 0 && - ModulePasses.size() == 0); - - // We must set initialized to true before calling this function, because - // the doRegister() function will probably call RegisterDefaultPasses(), - // which will call this function, and we'd end up with infinite recursion - // and breakage if we didn't. - initialized = true; - doRegister(); - } -} - -} // Anonymous namespace - -void (*StandardPass::RegisterDefaultPasses)(void); -Pass* (*StandardPass::CreateVerifierPass)(void); - -void StandardPass::RegisterDefaultPass(PassInfo::NormalCtor_t constructor, - unsigned char *newPass, - unsigned char *oldPass, - StandardPass::StandardSet set, - unsigned flags) { - // Make sure that the standard sets are already regstered - RegisterDefaultStandardPasses(RegisterDefaultPasses); - // Get the correct list to modify - llvm::SmallVectorImpl& passList = PassList(set); - - // If there is no old pass specified, then we are adding a new final pass, so - // just push it onto the end. - if (!oldPass) { - StandardPassEntry pass(constructor, newPass, flags); - passList.push_back(pass); - return; - } - - // Find the correct place to insert the pass. This is a linear search, but - // this shouldn't be too slow since the SmallVector will store the values in - // a contiguous block of memory. Each entry is just three words of memory, so - // in most cases we are only going to be looking in one or two cache lines. - // The extra memory accesses from a more complex search structure would - // offset any performance gain (unless someone decides to add an insanely - // large set of standard passes to a set) - for (SmallVectorImpl::iterator i=passList.begin(), - e=passList.end() ; i!=e ; ++i) { - if (i->passID == oldPass) { - StandardPassEntry pass(constructor, newPass, flags); - passList.insert(i, pass); - // If we've added a new pass, then there may have gained the ability to - // insert one of the previously unresolved ones. If so, insert the new - // one. - for (SmallVectorImpl::iterator - u=UnresolvedPasses.begin(), eu=UnresolvedPasses.end() ; u!=eu ; ++u){ - if (u->next == newPass && u->set == set) { - UnresolvedStandardPass p = *u; - UnresolvedPasses.erase(u); - RegisterDefaultPass(p.createPass, p.passID, p.next, p.set, p.flags); - } - } - return; - } - } - // If we get to here, then we didn't find the correct place to insert the new - // pass - UnresolvedStandardPass pass(constructor, newPass, oldPass, set, flags); - UnresolvedPasses.push_back(pass); -} - -void StandardPass::AddPassesFromSet(PassManagerBase *PM, - StandardSet set, - unsigned flags, - bool VerifyEach, - Pass *inliner) { - RegisterDefaultStandardPasses(RegisterDefaultPasses); - unsigned level = OptimizationLevel(flags); - flags = RequiredFlags(flags); - llvm::SmallVectorImpl& passList = PassList(set); - - // Add all of the passes from this set - for (SmallVectorImpl::iterator i=passList.begin(), - e=passList.end() ; i!=e ; ++i) { - // Skip passes that don't have conditions that match the ones specified - // here. For a pass to match: - // - Its minimum optimisation level must be less than or equal to the - // specified level. - // - Its maximum optimisation level must be greater than or equal to the - // specified level - // - All of its required flags must be set - // - None of its disallowed flags may be set - if ((level >= OptimizationLevel(i->flags)) && - ((level <= MaxOptimizationLevel(i->flags)) - || MaxOptimizationLevel(i->flags) == 0) && - ((RequiredFlags(i->flags) & flags) == RequiredFlags(i->flags)) && - ((DisallowedFlags(i->flags) & flags) == 0)) { - // This is quite an ugly way of allowing us to specify an inliner pass to - // insert. Ideally, we'd replace this with a general mechanism allowing - // callers to replace arbitrary passes in the list. - Pass *p = 0; - if (&InlinerPlaceholderID == i->passID) { - p = inliner; - } else if (i->createPass) - p = i->createPass(); - if (p) { - PM->add(p); - if (VerifyEach) - PM->add(CreateVerifierPass()); - } - } - } -} - -unsigned char DefaultStandardPasses::AggressiveDCEID; -unsigned char DefaultStandardPasses::ArgumentPromotionID; -unsigned char DefaultStandardPasses::BasicAliasAnalysisID; -unsigned char DefaultStandardPasses::CFGSimplificationID; -unsigned char DefaultStandardPasses::ConstantMergeID; -unsigned char DefaultStandardPasses::CorrelatedValuePropagationID; -unsigned char DefaultStandardPasses::DeadArgEliminationID; -unsigned char DefaultStandardPasses::DeadStoreEliminationID; -unsigned char DefaultStandardPasses::DeadTypeEliminationID; -unsigned char DefaultStandardPasses::EarlyCSEID; -unsigned char DefaultStandardPasses::FunctionAttrsID; -unsigned char DefaultStandardPasses::FunctionInliningID; -unsigned char DefaultStandardPasses::GVNID; -unsigned char DefaultStandardPasses::GlobalDCEID; -unsigned char DefaultStandardPasses::GlobalOptimizerID; -unsigned char DefaultStandardPasses::GlobalsModRefID; -unsigned char DefaultStandardPasses::IPSCCPID; -unsigned char DefaultStandardPasses::IndVarSimplifyID; -unsigned char DefaultStandardPasses::InlinerPlaceholderID; -unsigned char DefaultStandardPasses::InstructionCombiningID; -unsigned char DefaultStandardPasses::JumpThreadingID; -unsigned char DefaultStandardPasses::LICMID; -unsigned char DefaultStandardPasses::LoopDeletionID; -unsigned char DefaultStandardPasses::LoopIdiomID; -unsigned char DefaultStandardPasses::LoopRotateID; -unsigned char DefaultStandardPasses::LoopUnrollID; -unsigned char DefaultStandardPasses::LoopUnswitchID; -unsigned char DefaultStandardPasses::MemCpyOptID; -unsigned char DefaultStandardPasses::PruneEHID; -unsigned char DefaultStandardPasses::ReassociateID; -unsigned char DefaultStandardPasses::SCCPID; -unsigned char DefaultStandardPasses::ScalarReplAggregatesID; -unsigned char DefaultStandardPasses::SimplifyLibCallsID; -unsigned char DefaultStandardPasses::StripDeadPrototypesID; -unsigned char DefaultStandardPasses::TailCallEliminationID; -unsigned char DefaultStandardPasses::TypeBasedAliasAnalysisID; Modified: llvm/trunk/lib/VMCore/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/CMakeLists.txt?rev=131600&r1=131599&r2=131600&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/CMakeLists.txt (original) +++ llvm/trunk/lib/VMCore/CMakeLists.txt Wed May 18 18:51:11 2011 @@ -28,6 +28,7 @@ PassManager.cpp PassRegistry.cpp PrintModulePass.cpp + StandardPasses.cpp Type.cpp TypeSymbolTable.cpp Use.cpp From grosbach at apple.com Wed May 18 18:53:21 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 18 May 2011 23:53:21 -0000 Subject: [llvm-commits] [llvm] r131601 - in /llvm/trunk/lib/ExecutionEngine/MCJIT: MCJIT.cpp MCJITMemoryManager.h Message-ID: <20110518235321.39C892A6C12C@llvm.org> Author: grosbach Date: Wed May 18 18:53:21 2011 New Revision: 131601 URL: http://llvm.org/viewvc/llvm-project?rev=131601&view=rev Log: Objective C functions may use a magic '\1' on the name. Handle that when dealing with them in the MCJIT. Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp?rev=131601&r1=131600&r2=131601&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Wed May 18 18:53:21 2011 @@ -102,7 +102,12 @@ return Addr; } - Twine Name = TM->getMCAsmInfo()->getGlobalPrefix() + F->getName(); + // FIXME: Should we be using the mangler for this? Probably. + StringRef BaseName = F->getName(); + if (BaseName[0] == '\1') + BaseName = BaseName.substr(1); + else + Twine Name = TM->getMCAsmInfo()->getGlobalPrefix() + BaseName; return (void*)Dyld.getSymbolAddress(Name.str()); } Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h?rev=131601&r1=131600&r2=131601&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h (original) +++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJITMemoryManager.h Wed May 18 18:53:21 2011 @@ -36,6 +36,11 @@ // prefix. if (Name[0] == '_') ++Name; Function *F = M->getFunction(Name); + // Some ObjC names have a prefixed \01 in the IR. If we failed to find + // the symbol and it's of the ObjC conventions (starts with "-"), try + // prepending a \01 and see if we can find it that way. + if (!F && Name[0] == '-') + F = M->getFunction((Twine("\1") + Name).str()); assert(F && "No matching function in JIT IR Module!"); return JMM->startFunctionBody(F, Size); } @@ -48,6 +53,11 @@ // prefix. if (Name[0] == '_') ++Name; Function *F = M->getFunction(Name); + // Some ObjC names have a prefixed \01 in the IR. If we failed to find + // the symbol and it's of the ObjC conventions (starts with "-"), try + // prepending a \01 and see if we can find it that way. + if (!F && Name[0] == '-') + F = M->getFunction((Twine("\1") + Name).str()); assert(F && "No matching function in JIT IR Module!"); JMM->endFunctionBody(F, FunctionStart, FunctionEnd); } From rafael.espindola at gmail.com Wed May 18 18:56:40 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 18 May 2011 23:56:40 -0000 Subject: [llvm-commits] [llvm] r131602 - in /llvm/trunk: cmake/modules/LLVMLibDeps.cmake lib/Support/CMakeLists.txt Message-ID: <20110518235640.322922A6C12C@llvm.org> Author: rafael Date: Wed May 18 18:56:40 2011 New Revision: 131602 URL: http://llvm.org/viewvc/llvm-project?rev=131602&view=rev Log: Fix the cmake build. Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake llvm/trunk/lib/Support/CMakeLists.txt Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=131602&r1=131601&r2=131602&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Wed May 18 18:56:40 2011 @@ -17,7 +17,7 @@ set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils) +set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMInstCombine LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils LLVMipa LLVMipo) set(MSVC_LIB_DEPS_LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport) Modified: llvm/trunk/lib/Support/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CMakeLists.txt?rev=131602&r1=131601&r2=131602&view=diff ============================================================================== --- llvm/trunk/lib/Support/CMakeLists.txt (original) +++ llvm/trunk/lib/Support/CMakeLists.txt Wed May 18 18:56:40 2011 @@ -35,6 +35,7 @@ SmallPtrSet.cpp SmallVector.cpp SourceMgr.cpp + StandardPasses.cpp Statistic.cpp StringExtras.cpp StringMap.cpp From grosbach at apple.com Wed May 18 18:56:43 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 18 May 2011 23:56:43 -0000 Subject: [llvm-commits] [llvm] r131603 - /llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Message-ID: <20110518235643.7F7962A6C12D@llvm.org> Author: grosbach Date: Wed May 18 18:56:43 2011 New Revision: 131603 URL: http://llvm.org/viewvc/llvm-project?rev=131603&view=rev Log: Restore sanity to 131601. Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp?rev=131603&r1=131602&r2=131603&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Wed May 18 18:56:43 2011 @@ -104,10 +104,11 @@ // FIXME: Should we be using the mangler for this? Probably. StringRef BaseName = F->getName(); + Twine Name; if (BaseName[0] == '\1') - BaseName = BaseName.substr(1); + Name = BaseName.substr(1); else - Twine Name = TM->getMCAsmInfo()->getGlobalPrefix() + BaseName; + Name = TM->getMCAsmInfo()->getGlobalPrefix() + BaseName; return (void*)Dyld.getSymbolAddress(Name.str()); } From nlewycky at google.com Wed May 18 19:03:16 2011 From: nlewycky at google.com (Nick Lewycky) Date: Wed, 18 May 2011 17:03:16 -0700 Subject: [llvm-commits] patch: make the inliner emit lifetime markers Message-ID: Hi, I'm starting to get serious about lifetime markers. The attached patch teaches the inliner to emit lifetime.start and lifetime.end markers for the alloca's that it hoists to the beginning of the function. Please review, or propose some testing that you'd like to see done on this patch! Nick -------------- next part -------------- An HTML attachment was scrubbed... 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Name: llvm-inline-lifetime-1.patch Type: text/x-patch Size: 2623 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110518/7e5951e1/attachment.bin From eli.friedman at gmail.com Wed May 18 18:58:37 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 23:58:37 -0000 Subject: [llvm-commits] [llvm] r131604 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineCalls.cpp lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp lib/Transforms/InstCombine/InstructionCombining.cpp test/Transforms/InstCombine/or.ll Message-ID: <20110518235837.4F9B62A6C12C@llvm.org> Author: efriedma Date: Wed May 18 18:58:37 2011 New Revision: 131604 URL: http://llvm.org/viewvc/llvm-project?rev=131604&view=rev Log: More instcombine cleanup, towards improving debug line info. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp llvm/trunk/test/Transforms/InstCombine/or.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=131604&r1=131603&r2=131604&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Wed May 18 18:58:37 2011 @@ -1212,7 +1212,7 @@ // Add the chain argument and attributes. Value *NestVal = Tramp->getArgOperand(2); if (NestVal->getType() != NestTy) - NestVal = new BitCastInst(NestVal, NestTy, "nest", Caller); + NestVal = Builder->CreateBitCast(NestVal, NestTy, "nest"); NewArgs.push_back(NestVal); NewAttrs.push_back(AttributeWithIndex::get(NestIdx, NestAttr)); } Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp?rev=131604&r1=131603&r2=131604&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp Wed May 18 18:58:37 2011 @@ -57,12 +57,14 @@ Value *Idx[2]; Idx[0] = NullIdx; Idx[1] = NullIdx; - Value *V = GetElementPtrInst::CreateInBounds(New, Idx, Idx + 2, - New->getName()+".sub", It); + Instruction *GEP = + GetElementPtrInst::CreateInBounds(New, Idx, Idx + 2, + New->getName()+".sub"); + InsertNewInstBefore(GEP, *It); // Now make everything use the getelementptr instead of the original // allocation. - return ReplaceInstUsesWith(AI, V); + return ReplaceInstUsesWith(AI, GEP); } else if (isa(AI.getArraySize())) { return ReplaceInstUsesWith(AI, Constant::getNullValue(AI.getType())); } Modified: llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp?rev=131604&r1=131603&r2=131604&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstructionCombining.cpp Wed May 18 18:58:37 2011 @@ -240,9 +240,9 @@ Constant *C2 = cast(Op1->getOperand(1)); Constant *Folded = ConstantExpr::get(Opcode, C1, C2); - Instruction *New = BinaryOperator::Create(Opcode, A, B, Op1->getName(), - &I); - Worklist.Add(New); + Instruction *New = BinaryOperator::Create(Opcode, A, B); + InsertNewInstBefore(New, I); + New->takeName(Op1); I.setOperand(0, New); I.setOperand(1, Folded); // Conservatively clear the optional flags, since they may not be @@ -599,7 +599,7 @@ } // Okay, we can do the transformation: create the new PHI node. - PHINode *NewPN = PHINode::Create(I.getType(), PN->getNumIncomingValues(), ""); + PHINode *NewPN = PHINode::Create(I.getType(), PN->getNumIncomingValues()); InsertNewInstBefore(NewPN, *PN); NewPN->takeName(PN); @@ -1088,8 +1088,8 @@ // free undef -> unreachable. if (isa(Op)) { // Insert a new store to null because we cannot modify the CFG here. - new StoreInst(ConstantInt::getTrue(FI.getContext()), - UndefValue::get(Type::getInt1PtrTy(FI.getContext())), &FI); + Builder->CreateStore(ConstantInt::getTrue(FI.getContext()), + UndefValue::get(Type::getInt1PtrTy(FI.getContext()))); return EraseInstFromFunction(FI); } Modified: llvm/trunk/test/Transforms/InstCombine/or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/or.ll?rev=131604&r1=131603&r2=131604&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/or.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/or.ll Wed May 18 18:58:37 2011 @@ -332,8 +332,8 @@ %F = or i64 %D, %E ret i64 %F ; CHECK: @test31 -; CHECK-NEXT: %E1 = and i64 %A, 4294908984 -; CHECK-NEXT: %F = or i64 %E1, 32962 +; CHECK-NEXT: %E = and i64 %A, 4294908984 +; CHECK-NEXT: %F = or i64 %E, 32962 ; CHECK-NEXT: ret i64 %F } From atrick at apple.com Wed May 18 19:03:56 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 18 May 2011 17:03:56 -0700 Subject: [llvm-commits] [llvm] r131186 - in /llvm/trunk: include/llvm/Support/Program.h lib/Support/Program.cpp lib/Support/Unix/Program.inc tools/bugpoint/ExecutionDriver.cpp tools/bugpoint/Miscompilation.cpp tools/bugpoint/ToolRunner.cpp In-Reply-To: References: <20110511163124.D83B82A6C12C@llvm.org> Message-ID: On May 18, 2011, at 2:42 PM, Dan Gohman wrote: >> --- llvm/trunk/include/llvm/Support/Program.h (original) >> +++ llvm/trunk/include/llvm/Support/Program.h Wed May 11 11:31:24 2011 >> @@ -96,9 +96,11 @@ >> ///< expires, the child is killed and this call returns. If zero, >> ///< this function will wait until the child finishes or forever if >> ///< it doesn't. >> - std::string* ErrMsg ///< If non-zero, provides a pointer to a string >> + std::string* ErrMsg, ///< If non-zero, provides a pointer to a string >> ///< instance in which error messages will be returned. If the string >> ///< is non-empty upon return an error occurred while waiting. >> + const char *SignalPrefix ///< If non-zero, provides a prefix to be >> + ///< prepended to ErrMsg if the process is terminated abnormally. >> ); > > This function is documented to return a negative value if the process is > terminated abnormally. Shouldn't the task of producing a pretty error > message belong to client code, rather than being built into these low-level > support functions? Ah. I knew I wouldn't get away with this for long. The docs don't cleanly specify the behavior. I needed a way in the client, many levels above to distinguish between signals and other sorts of abnormal events like timeouts and errors spawning the process. I was extremely paranoid about changing the return value and breaking other clients, which I don't know how to test and are likely outside the main source. So I went with an approach that I can prove is transparent to other clients. I'd be thrilled to drop SignalPrefix if anyone with more experience can tell me how to do it safely. -Andy From dpatel at apple.com Wed May 18 18:59:51 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 18 May 2011 23:59:51 -0000 Subject: [llvm-commits] [llvm] r131605 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110518235951.B5F7A2A6C12C@llvm.org> Author: dpatel Date: Wed May 18 18:59:51 2011 New Revision: 131605 URL: http://llvm.org/viewvc/llvm-project?rev=131605&view=rev Log: Use IRBuilder while simplifying conditional branch. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131605&r1=131604&r2=131605&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 18:59:51 2011 @@ -835,7 +835,7 @@ /// HoistThenElseCodeToIf - Given a conditional branch that goes to BB1 and /// BB2, hoist any common code in the two blocks up into the branch block. The /// caller of this function guarantees that BI's block dominates BB1 and BB2. -static bool HoistThenElseCodeToIf(BranchInst *BI) { +static bool HoistThenElseCodeToIf(BranchInst *BI, IRBuilder<> &Builder) { // This does very trivial matching, with limited scanning, to find identical // instructions in the two blocks. In particular, we don't want to get into // O(M*N) situations here where M and N are the sizes of BB1 and BB2. As @@ -908,6 +908,7 @@ NT->takeName(I1); } + Builder.SetInsertPoint(NT); // Hoisting one of the terminators from our successor is a great thing. // Unfortunately, the successors of the if/else blocks may have PHI nodes in // them. If they do, all PHI entries for BB1/BB2 must agree for all PHI @@ -924,11 +925,11 @@ // These values do not agree. Insert a select instruction before NT // that determines the right value. SelectInst *&SI = InsertedSelects[std::make_pair(BB1V, BB2V)]; - if (SI == 0) { - SI = SelectInst::Create(BI->getCondition(), BB1V, BB2V, - BB1V->getName()+"."+BB2V->getName(), NT); - SI->setDebugLoc(BI->getDebugLoc()); - } + if (SI == 0) + SI = cast + (Builder.CreateSelect(BI->getCondition(), BB1V, BB2V, + BB1V->getName()+"."+BB2V->getName())); + // Make the PHI node use the select for all incoming values for BB1/BB2 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) if (PN->getIncomingBlock(i) == BB1 || PN->getIncomingBlock(i) == BB2) @@ -948,7 +949,8 @@ /// and an BB2 and the only successor of BB1 is BB2, hoist simple code /// (for now, restricted to a single instruction that's side effect free) from /// the BB1 into the branch block to speculatively execute it. -static bool SpeculativelyExecuteBB(BranchInst *BI, BasicBlock *BB1) { +static bool SpeculativelyExecuteBB(BranchInst *BI, BasicBlock *BB1, + IRBuilder<> &Builder) { // Only speculatively execution a single instruction (not counting the // terminator) for now. Instruction *HInst = NULL; @@ -1086,14 +1088,16 @@ // Create a select whose true value is the speculatively executed value and // false value is the previously determined FalseV. + Builder.SetInsertPoint(BI); SelectInst *SI; if (Invert) - SI = SelectInst::Create(BrCond, FalseV, HInst, - FalseV->getName() + "." + HInst->getName(), BI); + SI = cast + (Builder.CreateSelect(BrCond, FalseV, HInst, + FalseV->getName() + "." + HInst->getName())); else - SI = SelectInst::Create(BrCond, HInst, FalseV, - HInst->getName() + "." + FalseV->getName(), BI); - SI->setDebugLoc(BI->getDebugLoc()); + SI = cast + (Builder.CreateSelect(BrCond, HInst, FalseV, + HInst->getName() + "." + FalseV->getName())); // Make the PHI node use the select for all incoming values for "then" and // "if" blocks. @@ -1460,6 +1464,7 @@ /// the predecessor and use logical operations to pick the right destination. bool llvm::FoldBranchToCommonDest(BranchInst *BI) { BasicBlock *BB = BI->getParent(); + Instruction *Cond = dyn_cast(BI->getCondition()); if (Cond == 0 || (!isa(Cond) && !isa(Cond)) || Cond->getParent() != BB || !Cond->hasOneUse()) @@ -1580,7 +1585,8 @@ } DEBUG(dbgs() << "FOLDING BRANCH TO COMMON DEST:\n" << *PBI << *BB); - + IRBuilder<> Builder(PBI); + // If we need to invert the condition in the pred block to match, do so now. if (InvertPredCond) { Value *NewCond = PBI->getCondition(); @@ -1589,8 +1595,8 @@ CmpInst *CI = cast(NewCond); CI->setPredicate(CI->getInversePredicate()); } else { - NewCond = BinaryOperator::CreateNot(NewCond, - PBI->getCondition()->getName()+".not", PBI); + NewCond = Builder.CreateNot(NewCond, + PBI->getCondition()->getName()+".not"); } PBI->setCondition(NewCond); @@ -1617,9 +1623,9 @@ New->takeName(Cond); Cond->setName(New->getName()+".old"); - Instruction *NewCond = BinaryOperator::Create(Opc, PBI->getCondition(), - New, "or.cond", PBI); - NewCond->setDebugLoc(PBI->getDebugLoc()); + Instruction *NewCond = + cast(Builder.CreateBinOp(Opc, PBI->getCondition(), + New, "or.cond")); PBI->setCondition(NewCond); if (PBI->getSuccessor(0) == BB) { AddPredecessorToBlock(TrueDest, PredBlock, BB); @@ -1762,23 +1768,22 @@ } DEBUG(dbgs() << *PBI->getParent()->getParent()); - + // BI may have other predecessors. Because of this, we leave // it alone, but modify PBI. // Make sure we get to CommonDest on True&True directions. Value *PBICond = PBI->getCondition(); + IRBuilder<> Builder(PBI); if (PBIOp) - PBICond = BinaryOperator::CreateNot(PBICond, - PBICond->getName()+".not", - PBI); + PBICond = Builder.CreateNot(PBICond, PBICond->getName()+".not"); + Value *BICond = BI->getCondition(); if (BIOp) - BICond = BinaryOperator::CreateNot(BICond, - BICond->getName()+".not", - PBI); + BICond = Builder.CreateNot(BICond, BICond->getName()+".not"); + // Merge the conditions. - Value *Cond = BinaryOperator::CreateOr(PBICond, BICond, "brmerge", PBI); + Value *Cond = Builder.CreateOr(PBICond, BICond, "brmerge"); // Modify PBI to branch on the new condition to the new dests. PBI->setCondition(Cond); @@ -1801,8 +1806,8 @@ Value *PBIV = PN->getIncomingValue(PBBIdx); if (BIV != PBIV) { // Insert a select in PBI to pick the right value. - Value *NV = SelectInst::Create(PBICond, PBIV, BIV, - PBIV->getName()+".mux", PBI); + Value *NV = cast + (Builder.CreateSelect(PBICond, PBIV, BIV, PBIV->getName()+".mux")); PN->setIncomingValue(PBBIdx, NV); } } @@ -2584,7 +2589,7 @@ // can hoist it up to the branching block. if (BI->getSuccessor(0)->getSinglePredecessor() != 0) { if (BI->getSuccessor(1)->getSinglePredecessor() != 0) { - if (HoistThenElseCodeToIf(BI)) + if (HoistThenElseCodeToIf(BI, Builder)) return SimplifyCFG(BB) | true; } else { // If Successor #1 has multiple preds, we may be able to conditionally @@ -2592,7 +2597,7 @@ TerminatorInst *Succ0TI = BI->getSuccessor(0)->getTerminator(); if (Succ0TI->getNumSuccessors() == 1 && Succ0TI->getSuccessor(0) == BI->getSuccessor(1)) - if (SpeculativelyExecuteBB(BI, BI->getSuccessor(0))) + if (SpeculativelyExecuteBB(BI, BI->getSuccessor(0), Builder)) return SimplifyCFG(BB) | true; } } else if (BI->getSuccessor(1)->getSinglePredecessor() != 0) { @@ -2601,7 +2606,7 @@ TerminatorInst *Succ1TI = BI->getSuccessor(1)->getTerminator(); if (Succ1TI->getNumSuccessors() == 1 && Succ1TI->getSuccessor(0) == BI->getSuccessor(0)) - if (SpeculativelyExecuteBB(BI, BI->getSuccessor(1))) + if (SpeculativelyExecuteBB(BI, BI->getSuccessor(1), Builder)) return SimplifyCFG(BB) | true; } From rafael.espindola at gmail.com Wed May 18 19:02:45 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 19 May 2011 00:02:45 -0000 Subject: [llvm-commits] [llvm] r131606 - in /llvm/trunk: cmake/modules/LLVMLibDeps.cmake lib/Support/CMakeLists.txt Message-ID: <20110519000246.641352A6C12C@llvm.org> Author: rafael Date: Wed May 18 19:02:45 2011 New Revision: 131606 URL: http://llvm.org/viewvc/llvm-project?rev=131606&view=rev Log: Revert my previous patch. The cmake build had already been fixed. Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake llvm/trunk/lib/Support/CMakeLists.txt Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=131606&r1=131605&r2=131606&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Wed May 18 19:02:45 2011 @@ -17,7 +17,7 @@ set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMInstCombine LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils LLVMipa LLVMipo) +set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils) set(MSVC_LIB_DEPS_LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport) Modified: llvm/trunk/lib/Support/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/CMakeLists.txt?rev=131606&r1=131605&r2=131606&view=diff ============================================================================== --- llvm/trunk/lib/Support/CMakeLists.txt (original) +++ llvm/trunk/lib/Support/CMakeLists.txt Wed May 18 19:02:45 2011 @@ -35,7 +35,6 @@ SmallPtrSet.cpp SmallVector.cpp SourceMgr.cpp - StandardPasses.cpp Statistic.cpp StringExtras.cpp StringMap.cpp From clattner at apple.com Wed May 18 19:14:02 2011 From: clattner at apple.com (Chris Lattner) Date: Wed, 18 May 2011 17:14:02 -0700 Subject: [llvm-commits] [llvm] r131603 - /llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp In-Reply-To: <20110518235643.7F7962A6C12D@llvm.org> References: <20110518235643.7F7962A6C12D@llvm.org> Message-ID: On May 18, 2011, at 4:56 PM, Jim Grosbach wrote: > Author: grosbach > Date: Wed May 18 18:56:43 2011 > New Revision: 131603 > > URL: http://llvm.org/viewvc/llvm-project?rev=131603&view=rev > Log: > Restore sanity to 131601. > > Modified: > llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp > > Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp?rev=131603&r1=131602&r2=131603&view=diff > ============================================================================== > --- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp (original) > +++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Wed May 18 18:56:43 2011 > @@ -104,10 +104,11 @@ > > // FIXME: Should we be using the mangler for this? Probably. > StringRef BaseName = F->getName(); > + Twine Name; > if (BaseName[0] == '\1') > - BaseName = BaseName.substr(1); > + Name = BaseName.substr(1); > else > - Twine Name = TM->getMCAsmInfo()->getGlobalPrefix() + BaseName; > + Name = TM->getMCAsmInfo()->getGlobalPrefix() + BaseName; > return (void*)Dyld.getSymbolAddress(Name.str()); > } Hi Jim, This code won't work. The temporary formed by the "+" in the second case dies too early. You need to do something like this: return (void*)Dyld.getSymbolAddress(TM->getMCAsmInfo()->getGlobalPrefix() + BaseName); -Chris From dpatel at apple.com Wed May 18 19:09:21 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 19 May 2011 00:09:21 -0000 Subject: [llvm-commits] [llvm] r131607 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110519000921.ECEA32A6C12C@llvm.org> Author: dpatel Date: Wed May 18 19:09:21 2011 New Revision: 131607 URL: http://llvm.org/viewvc/llvm-project?rev=131607&view=rev Log: Use IRBuilder while simplifying unreachable. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131607&r1=131606&r2=131607&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 19:09:21 2011 @@ -2270,7 +2270,7 @@ SmallVector Preds(pred_begin(BB), pred_end(BB)); for (unsigned i = 0, e = Preds.size(); i != e; ++i) { TerminatorInst *TI = Preds[i]->getTerminator(); - + IRBuilder<> Builder(TI); if (BranchInst *BI = dyn_cast(TI)) { if (BI->isUnconditional()) { if (BI->getSuccessor(0) == BB) { @@ -2280,10 +2280,10 @@ } } else { if (BI->getSuccessor(0) == BB) { - BranchInst::Create(BI->getSuccessor(1), BI); + Builder.CreateBr(BI->getSuccessor(1)); EraseTerminatorInstAndDCECond(BI); } else if (BI->getSuccessor(1) == BB) { - BranchInst::Create(BI->getSuccessor(0), BI); + Builder.CreateBr(BI->getSuccessor(0)); EraseTerminatorInstAndDCECond(BI); Changed = true; } @@ -2347,14 +2347,15 @@ if (II->getUnwindDest() == BB) { // Convert the invoke to a call instruction. This would be a good // place to note that the call does not throw though. - BranchInst *BI = BranchInst::Create(II->getNormalDest(), II); + BranchInst *BI = Builder.CreateBr(II->getNormalDest()); II->removeFromParent(); // Take out of symbol table // Insert the call now... SmallVector Args(II->op_begin(), II->op_end()-3); - CallInst *CI = CallInst::Create(II->getCalledValue(), - Args.begin(), Args.end(), - II->getName(), BI); + Builder.SetInsertPoint(BI); + CallInst *CI = Builder.CreateCall(II->getCalledValue(), + Args.begin(), Args.end(), + II->getName()); CI->setCallingConv(II->getCallingConv()); CI->setAttributes(II->getAttributes()); // If the invoke produced a value, the call does now instead. From rafael.espindola at gmail.com Wed May 18 19:13:04 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 19 May 2011 00:13:04 -0000 Subject: [llvm-commits] [llvm] r131608 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake Message-ID: <20110519001304.A731A2A6C12C@llvm.org> Author: rafael Date: Wed May 18 19:13:04 2011 New Revision: 131608 URL: http://llvm.org/viewvc/llvm-project?rev=131608&view=rev Log: Another try at fixing cmake. Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=131608&r1=131607&r2=131608&view=diff ============================================================================== --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Wed May 18 19:13:04 2011 @@ -17,7 +17,7 @@ set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport) set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport) -set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils) +set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMInstCombine LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils LLVMipa LLVMipo) set(MSVC_LIB_DEPS_LLVMCore LLVMSupport) set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMTarget) set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport) From dpatel at apple.com Wed May 18 19:13:33 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 19 May 2011 00:13:33 -0000 Subject: [llvm-commits] [llvm] r131609 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110519001333.C87912A6C12C@llvm.org> Author: dpatel Date: Wed May 18 19:13:33 2011 New Revision: 131609 URL: http://llvm.org/viewvc/llvm-project?rev=131609&view=rev Log: Use IRBuilder. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131609&r1=131608&r2=131609&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 19:13:33 2011 @@ -2404,8 +2404,8 @@ Value *Sub = SI->getCondition(); if (!Offset->isNullValue()) - Sub = BinaryOperator::CreateAdd(Sub, Offset, Sub->getName()+".off", SI); - Value *Cmp = new ICmpInst(SI, ICmpInst::ICMP_ULT, Sub, NumCases, "switch"); + Sub = Builder.CreateAdd(Sub, Offset, Sub->getName()+".off"); + Value *Cmp = Builder.CreateICmpULT(Sub, NumCases, "switch"); Builder.CreateCondBr(Cmp, SI->getSuccessor(1), SI->getDefaultDest()); // Prune obsolete incoming values off the successor's PHI nodes. From grosbach at apple.com Wed May 18 19:45:06 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 May 2011 00:45:06 -0000 Subject: [llvm-commits] [llvm] r131612 - /llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Message-ID: <20110519004506.0FBB22A6C12C@llvm.org> Author: grosbach Date: Wed May 18 19:45:05 2011 New Revision: 131612 URL: http://llvm.org/viewvc/llvm-project?rev=131612&view=rev Log: Avoid a Twine that referenced a tmp (which proceded to go out of scope before the Twine was used). Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp?rev=131612&r1=131611&r2=131612&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Wed May 18 19:45:05 2011 @@ -104,12 +104,10 @@ // FIXME: Should we be using the mangler for this? Probably. StringRef BaseName = F->getName(); - Twine Name; if (BaseName[0] == '\1') - Name = BaseName.substr(1); - else - Name = TM->getMCAsmInfo()->getGlobalPrefix() + BaseName; - return (void*)Dyld.getSymbolAddress(Name.str()); + return (void*)Dyld.getSymbolAddress(BaseName.substr(1)); + return (void*)Dyld.getSymbolAddress((TM->getMCAsmInfo()->getGlobalPrefix() + + BaseName).str()); } void *MCJIT::recompileAndRelinkFunction(Function *F) { From grosbach at apple.com Wed May 18 19:50:48 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 18 May 2011 17:50:48 -0700 Subject: [llvm-commits] [llvm] r131603 - /llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp In-Reply-To: References: <20110518235643.7F7962A6C12D@llvm.org> Message-ID: <90A37B5A-6F7E-4671-B54E-BCB3868D938A@apple.com> On May 18, 2011, at 5:14 PM, Chris Lattner wrote: > > On May 18, 2011, at 4:56 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Wed May 18 18:56:43 2011 >> New Revision: 131603 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=131603&view=rev >> Log: >> Restore sanity to 131601. >> >> Modified: >> llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp >> >> Modified: llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp?rev=131603&r1=131602&r2=131603&view=diff >> ============================================================================== >> --- llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp (original) >> +++ llvm/trunk/lib/ExecutionEngine/MCJIT/MCJIT.cpp Wed May 18 18:56:43 2011 >> @@ -104,10 +104,11 @@ >> >> // FIXME: Should we be using the mangler for this? Probably. >> StringRef BaseName = F->getName(); >> + Twine Name; >> if (BaseName[0] == '\1') >> - BaseName = BaseName.substr(1); >> + Name = BaseName.substr(1); >> else >> - Twine Name = TM->getMCAsmInfo()->getGlobalPrefix() + BaseName; >> + Name = TM->getMCAsmInfo()->getGlobalPrefix() + BaseName; >> return (void*)Dyld.getSymbolAddress(Name.str()); >> } > > Hi Jim, > > This code won't work. The temporary formed by the "+" in the second case dies too early. You need to do something like this: > > return (void*)Dyld.getSymbolAddress(TM->getMCAsmInfo()->getGlobalPrefix() + BaseName); Quite right. That would have been a nasty little thing to track down later. Thanks! r131612 -Jim From eli.friedman at gmail.com Wed May 18 20:01:42 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 18:01:42 -0700 Subject: [llvm-commits] [llvm] r131608 - /llvm/trunk/cmake/modules/LLVMLibDeps.cmake In-Reply-To: <20110519001304.A731A2A6C12C@llvm.org> References: <20110519001304.A731A2A6C12C@llvm.org> Message-ID: On Wed, May 18, 2011 at 5:13 PM, Rafael Espindola wrote: > Author: rafael > Date: Wed May 18 19:13:04 2011 > New Revision: 131608 > > URL: http://llvm.org/viewvc/llvm-project?rev=131608&view=rev > Log: > Another try at fixing cmake. > > Modified: > ? ?llvm/trunk/cmake/modules/LLVMLibDeps.cmake > > Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=131608&r1=131607&r2=131608&view=diff > ============================================================================== > --- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original) > +++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Wed May 18 19:13:04 2011 > @@ -17,7 +17,7 @@ > ?set(MSVC_LIB_DEPS_LLVMCBackendInfo LLVMMC LLVMSupport) > ?set(MSVC_LIB_DEPS_LLVMCellSPUCodeGen LLVMAsmPrinter LLVMCellSPUInfo LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget) > ?set(MSVC_LIB_DEPS_LLVMCellSPUInfo LLVMMC LLVMSupport) > -set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils) > +set(MSVC_LIB_DEPS_LLVMCodeGen LLVMAnalysis LLVMCore LLVMInstCombine LLVMMC LLVMScalarOpts LLVMSupport LLVMTarget LLVMTransformUtils LLVMipa LLVMipo) > ?set(MSVC_LIB_DEPS_LLVMCore LLVMSupport) > ?set(MSVC_LIB_DEPS_LLVMCppBackend LLVMCore LLVMCppBackendInfo LLVMSupport LLVMTarget) > ?set(MSVC_LIB_DEPS_LLVMCppBackendInfo LLVMMC LLVMSupport) Hmm... making anything that uses StandardPasses.h depend on every LLVM pass doesn't seem ideal; I guess it's not really a big deal, though. -Eli From eli.friedman at gmail.com Wed May 18 20:20:43 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 19 May 2011 01:20:43 -0000 Subject: [llvm-commits] [llvm] r131616 - in /llvm/trunk/lib/Transforms/InstCombine: InstCombine.h InstCombineSimplifyDemanded.cpp Message-ID: <20110519012043.1F8842A6C12C@llvm.org> Author: efriedma Date: Wed May 18 20:20:42 2011 New Revision: 131616 URL: http://llvm.org/viewvc/llvm-project?rev=131616&view=rev Log: Make the demanded bits/elements optimizations preserve debug line information. I'm not sure this is quite ideal, but I can't really think of any better way to do it. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombine.h llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombine.h?rev=131616&r1=131615&r2=131616&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombine.h (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombine.h Wed May 18 20:20:42 2011 @@ -233,7 +233,15 @@ Worklist.Add(New); return New; } - + + // InsertNewInstWith - same as InsertNewInstBefore, but also sets the + // debug loc. + // + Instruction *InsertNewInstWith(Instruction *New, Instruction &Old) { + New->setDebugLoc(Old.getDebugLoc()); + return InsertNewInstBefore(New, Old); + } + // ReplaceInstUsesWith - This method is to be used when an instruction is // found to be dead, replacable with another preexisting expression. Here // we add all uses of I to the worklist, replace all uses of I with the new Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp?rev=131616&r1=131615&r2=131616&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp Wed May 18 20:20:42 2011 @@ -313,7 +313,7 @@ Instruction *Or = BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1), I->getName()); - return InsertNewInstBefore(Or, *I); + return InsertNewInstWith(Or, *I); } // If all of the demanded bits on one side are known, and all of the set @@ -327,7 +327,7 @@ ~RHSKnownOne & DemandedMask); Instruction *And = BinaryOperator::CreateAnd(I->getOperand(0), AndC, "tmp"); - return InsertNewInstBefore(And, *I); + return InsertNewInstWith(And, *I); } } @@ -353,13 +353,13 @@ ConstantInt::get(I->getType(), NewMask & AndRHS->getValue()); Instruction *NewAnd = BinaryOperator::CreateAnd(I->getOperand(0), AndC, "tmp"); - InsertNewInstBefore(NewAnd, *I); + InsertNewInstWith(NewAnd, *I); Constant *XorC = ConstantInt::get(I->getType(), NewMask & XorRHS->getValue()); Instruction *NewXor = BinaryOperator::CreateXor(NewAnd, XorC, "tmp"); - return InsertNewInstBefore(NewXor, *I); + return InsertNewInstWith(NewXor, *I); } // Output known-0 bits are known if clear or set in both the LHS & RHS. @@ -472,7 +472,7 @@ if (KnownZero[SrcBitWidth-1] || (NewBits & ~DemandedMask) == NewBits) { // Convert to ZExt cast CastInst *NewCast = new ZExtInst(I->getOperand(0), VTy, I->getName()); - return InsertNewInstBefore(NewCast, *I); + return InsertNewInstWith(NewCast, *I); } else if (KnownOne[SrcBitWidth-1]) { // Input sign bit known set KnownOne |= NewBits; } @@ -515,7 +515,7 @@ Instruction *Or = BinaryOperator::CreateOr(I->getOperand(0), I->getOperand(1), I->getName()); - return InsertNewInstBefore(Or, *I); + return InsertNewInstWith(Or, *I); } // We can say something about the output known-zero and known-one bits, @@ -632,7 +632,7 @@ // Perform the logical shift right. Instruction *NewVal = BinaryOperator::CreateLShr( I->getOperand(0), I->getOperand(1), I->getName()); - return InsertNewInstBefore(NewVal, *I); + return InsertNewInstWith(NewVal, *I); } // If the sign bit is the only bit demanded by this ashr, then there is no @@ -676,7 +676,7 @@ // Perform the logical shift right. Instruction *NewVal = BinaryOperator::CreateLShr( I->getOperand(0), SA, I->getName()); - return InsertNewInstBefore(NewVal, *I); + return InsertNewInstWith(NewVal, *I); } else if ((KnownOne & SignBit) != 0) { // New bits are known one. KnownOne |= HighBits; } @@ -774,7 +774,7 @@ NewVal = BinaryOperator::CreateShl(II->getArgOperand(0), ConstantInt::get(I->getType(), ResultBit-InputBit)); NewVal->takeName(I); - return InsertNewInstBefore(NewVal, *I); + return InsertNewInstWith(NewVal, *I); } // TODO: Could compute known zero/one bits based on the input. @@ -1108,21 +1108,21 @@ Value *LHS = II->getArgOperand(0); Value *RHS = II->getArgOperand(1); // Extract the element as scalars. - LHS = InsertNewInstBefore(ExtractElementInst::Create(LHS, + LHS = InsertNewInstWith(ExtractElementInst::Create(LHS, ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II); - RHS = InsertNewInstBefore(ExtractElementInst::Create(RHS, + RHS = InsertNewInstWith(ExtractElementInst::Create(RHS, ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U)), *II); switch (II->getIntrinsicID()) { default: llvm_unreachable("Case stmts out of sync!"); case Intrinsic::x86_sse_sub_ss: case Intrinsic::x86_sse2_sub_sd: - TmpV = InsertNewInstBefore(BinaryOperator::CreateFSub(LHS, RHS, + TmpV = InsertNewInstWith(BinaryOperator::CreateFSub(LHS, RHS, II->getName()), *II); break; case Intrinsic::x86_sse_mul_ss: case Intrinsic::x86_sse2_mul_sd: - TmpV = InsertNewInstBefore(BinaryOperator::CreateFMul(LHS, RHS, + TmpV = InsertNewInstWith(BinaryOperator::CreateFMul(LHS, RHS, II->getName()), *II); break; } @@ -1132,7 +1132,7 @@ UndefValue::get(II->getType()), TmpV, ConstantInt::get(Type::getInt32Ty(I->getContext()), 0U, false), II->getName()); - InsertNewInstBefore(New, *II); + InsertNewInstWith(New, *II); return New; } } From pichet2000 at gmail.com Wed May 18 20:35:29 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Wed, 18 May 2011 21:35:29 -0400 Subject: [llvm-commits] [llvm] r131592 - /llvm/trunk/include/llvm/Support/StandardPasses.h In-Reply-To: <20110518224602.506AF2A6C12C@llvm.org> References: <20110518224602.506AF2A6C12C@llvm.org> Message-ID: On Wed, May 18, 2011 at 6:46 PM, David Chisnall wrote: > Author: theraven > Date: Wed May 18 17:46:02 2011 > New Revision: 131592 > > URL: http://llvm.org/viewvc/llvm-project?rev=131592&view=rev > Log: > Some better type safety enforcement in the standard pass list, along with some small tidies and some fixes for bugs that the stricter checking found. > > > Modified: > ? ?llvm/trunk/include/llvm/Support/StandardPasses.h > > Modified: llvm/trunk/include/llvm/Support/StandardPasses.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=131592&r1=131591&r2=131592&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) > +++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed May 18 17:46:02 2011 > @@ -27,6 +27,7 @@ > ?#include "llvm/Transforms/IPO.h" > > ?namespace llvm { > + ? ?//template static Pass *CreatePassFn(void) { return X(); } > > ? /// RegisterStandardPassLists solves a circular dependency problem. ?The > ? /// default list of passes has to live somewhere. ?It can't live in the core > @@ -42,23 +43,36 @@ > ? ? ? StandardPass::CreateVerifierPass = CreateVerifierPass; > ? ? } > ? ? private: > + ? ?/// Define a template function that does the casting for us, so that we can > + ? ?/// perform safe function pointer casts, but catch unsafe ones. > + ? ?template static llvm::Pass* > + ? ? ?CreatePassFn(void) { return X(); } > + ? ?template static llvm::Pass* > + ? ? ?CreatePassFn(void) { return X(); } > + ? ?template static llvm::Pass* > + ? ? ?CreatePassFn(void) { return X(); } > + ? ?template static llvm::Pass* > + ? ? ?CreatePassFn(void) { return X(); } > ? ? static llvm::Pass *CreateVerifierPass() { return createVerifierPass(); } Hi.. this is too much for MSVC 2010. It wont compile: This is a reduction of the problem: =========================== class A {}; class B {}; template static void CreatePassFn(void) { } template static void CreatePassFn(void) { } B* CreatePassX(void); int main() { CreatePassFn(); // <== error here. return 1; } =========================== This code will compile fine with clang and gcc 4.5. MSVC 2010 will fail. Seems like MSVC cannot deduce template arguments that are function and that differ only by return type. Anybody have an idea on how to redesign this to make it MSVC friendly? From isanbard at gmail.com Wed May 18 20:36:43 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 19 May 2011 01:36:43 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r131617 - /llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h Message-ID: <20110519013643.B5E482A6C12C@llvm.org> Author: void Date: Wed May 18 20:36:43 2011 New Revision: 131617 URL: http://llvm.org/viewvc/llvm-project?rev=131617&view=rev Log: Really, we want *all* C strings to be 1-byte aligned. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h Modified: llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h?rev=131617&r1=131616&r2=131617&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h Wed May 18 20:36:43 2011 @@ -388,3 +388,12 @@ flag_objc_legacy_dispatch = 1; \ } while (0) +/* Radar 8961909 */ +/* Align the C string to 1-bytes on ARM. */ +#undef TARGET_ADJUST_CSTRING_ALIGN +#define TARGET_ADJUST_CSTRING_ALIGN(GV) \ + do { \ + if (GV->hasInternalLinkage()) { \ + GV->setAlignment(1); \ + } \ + } while (0) From zwarich at apple.com Wed May 18 20:56:19 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 19 May 2011 01:56:19 -0000 Subject: [llvm-commits] [llvm] r131618 - /llvm/trunk/lib/CodeGen/MachineVerifier.cpp Message-ID: <20110519015619.588152A6C12C@llvm.org> Author: zwarich Date: Wed May 18 20:56:19 2011 New Revision: 131618 URL: http://llvm.org/viewvc/llvm-project?rev=131618&view=rev Log: Revert r128961 because it didn't include a test and causes the verifier to fail on CodeGen/X86/2007-05-07-InvokeSRet.ll. There is probably a bug here that was fixed by r128961, but since there is no test or reference to a source file I have to revert it. Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=131618&r1=131617&r2=131618&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Wed May 18 20:56:19 2011 @@ -410,11 +410,6 @@ SmallVector Cond; if (!TII->AnalyzeBranch(*const_cast(MBB), TBB, FBB, Cond)) { - // If the block branches directly to a landing pad successor, pretend that - // the landing pad is a normal block. - LandingPadSuccs.erase(TBB); - LandingPadSuccs.erase(FBB); - // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's // check whether its answers match up with reality. if (!TBB && !FBB) { From eli.friedman at gmail.com Wed May 18 21:02:08 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 18 May 2011 19:02:08 -0700 Subject: [llvm-commits] [llvm] r131592 - /llvm/trunk/include/llvm/Support/StandardPasses.h In-Reply-To: References: <20110518224602.506AF2A6C12C@llvm.org> Message-ID: On Wed, May 18, 2011 at 6:35 PM, Francois Pichet wrote: > On Wed, May 18, 2011 at 6:46 PM, David Chisnall wrote: >> Author: theraven >> Date: Wed May 18 17:46:02 2011 >> New Revision: 131592 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=131592&view=rev >> Log: >> Some better type safety enforcement in the standard pass list, along with some small tidies and some fixes for bugs that the stricter checking found. >> >> >> Modified: >> ? ?llvm/trunk/include/llvm/Support/StandardPasses.h >> >> Modified: llvm/trunk/include/llvm/Support/StandardPasses.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=131592&r1=131591&r2=131592&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) >> +++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed May 18 17:46:02 2011 >> @@ -27,6 +27,7 @@ >> ?#include "llvm/Transforms/IPO.h" >> >> ?namespace llvm { >> + ? ?//template static Pass *CreatePassFn(void) { return X(); } >> >> ? /// RegisterStandardPassLists solves a circular dependency problem. ?The >> ? /// default list of passes has to live somewhere. ?It can't live in the core >> @@ -42,23 +43,36 @@ >> ? ? ? StandardPass::CreateVerifierPass = CreateVerifierPass; >> ? ? } >> ? ? private: >> + ? ?/// Define a template function that does the casting for us, so that we can >> + ? ?/// perform safe function pointer casts, but catch unsafe ones. >> + ? ?template static llvm::Pass* >> + ? ? ?CreatePassFn(void) { return X(); } >> + ? ?template static llvm::Pass* >> + ? ? ?CreatePassFn(void) { return X(); } >> + ? ?template static llvm::Pass* >> + ? ? ?CreatePassFn(void) { return X(); } >> + ? ?template static llvm::Pass* >> + ? ? ?CreatePassFn(void) { return X(); } >> ? ? static llvm::Pass *CreateVerifierPass() { return createVerifierPass(); } > > > Hi.. this is too much for MSVC 2010. It wont compile: > > This is a reduction of the problem: > =========================== > class A {}; > class B {}; > > template static void CreatePassFn(void) { ?} > template static void CreatePassFn(void) { ?} > > B* CreatePassX(void); > > int main() > { > ? CreatePassFn(); // <== error here. > ? return 1; > } > =========================== > > This code will compile fine with clang and gcc 4.5. MSVC 2010 will fail. > Seems like MSVC cannot deduce template arguments that are function and > that differ only by return type. > > Anybody have an idea on how to redesign this to make it MSVC friendly? I suppose we could use something like the following instead: PassInfo::NormalCtor_t static getPassFn(llvm::ImmutablePass*(*X)(void)) { return reinterpret_cast(X); } PassInfo::NormalCtor_t static getPassFn(llvm::ModulePass*(*X)(void)) { return reinterpret_cast(X); } PassInfo::NormalCtor_t static getPassFn(llvm::FunctionPass*(*X)(void)) { return reinterpret_cast(X); } PassInfo::NormalCtor_t static getPassFn(llvm::Pass*(*X)(void)) { return reinterpret_cast(X); } Does that sort of thing work with MSVC? -Eli From zwarich at apple.com Wed May 18 21:18:27 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 19 May 2011 02:18:27 -0000 Subject: [llvm-commits] [llvm] r131619 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20110519021828.0B1512A6C12C@llvm.org> Author: zwarich Date: Wed May 18 21:18:27 2011 New Revision: 131619 URL: http://llvm.org/viewvc/llvm-project?rev=131619&view=rev Log: Correctly constrain a register class when computing frame offsets, as the Thumb2 add instruction takes an rGPR. This fixes the last of PR8825. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=131619&r1=131618&r2=131619&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed May 18 21:18:27 2011 @@ -1111,6 +1111,10 @@ if (Ins != MBB->end()) DL = Ins->getDebugLoc(); + const TargetInstrDesc &TID = TII.get(ADDriOpc); + MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); + MRI.constrainRegClass(BaseReg, TID.OpInfo[0].getRegClass(this)); + MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, TII.get(ADDriOpc), BaseReg) .addFrameIndex(FrameIdx).addImm(Offset); From rafael.espindola at gmail.com Wed May 18 21:26:30 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 19 May 2011 02:26:30 -0000 Subject: [llvm-commits] [llvm] r131620 - /llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Message-ID: <20110519022630.45C112A6C12C@llvm.org> Author: rafael Date: Wed May 18 21:26:30 2011 New Revision: 131620 URL: http://llvm.org/viewvc/llvm-project?rev=131620&view=rev Log: revert 131605 to fix PR9946. Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=131620&r1=131619&r2=131620&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed May 18 21:26:30 2011 @@ -835,7 +835,7 @@ /// HoistThenElseCodeToIf - Given a conditional branch that goes to BB1 and /// BB2, hoist any common code in the two blocks up into the branch block. The /// caller of this function guarantees that BI's block dominates BB1 and BB2. -static bool HoistThenElseCodeToIf(BranchInst *BI, IRBuilder<> &Builder) { +static bool HoistThenElseCodeToIf(BranchInst *BI) { // This does very trivial matching, with limited scanning, to find identical // instructions in the two blocks. In particular, we don't want to get into // O(M*N) situations here where M and N are the sizes of BB1 and BB2. As @@ -908,7 +908,6 @@ NT->takeName(I1); } - Builder.SetInsertPoint(NT); // Hoisting one of the terminators from our successor is a great thing. // Unfortunately, the successors of the if/else blocks may have PHI nodes in // them. If they do, all PHI entries for BB1/BB2 must agree for all PHI @@ -925,11 +924,11 @@ // These values do not agree. Insert a select instruction before NT // that determines the right value. SelectInst *&SI = InsertedSelects[std::make_pair(BB1V, BB2V)]; - if (SI == 0) - SI = cast - (Builder.CreateSelect(BI->getCondition(), BB1V, BB2V, - BB1V->getName()+"."+BB2V->getName())); - + if (SI == 0) { + SI = SelectInst::Create(BI->getCondition(), BB1V, BB2V, + BB1V->getName()+"."+BB2V->getName(), NT); + SI->setDebugLoc(BI->getDebugLoc()); + } // Make the PHI node use the select for all incoming values for BB1/BB2 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) if (PN->getIncomingBlock(i) == BB1 || PN->getIncomingBlock(i) == BB2) @@ -949,8 +948,7 @@ /// and an BB2 and the only successor of BB1 is BB2, hoist simple code /// (for now, restricted to a single instruction that's side effect free) from /// the BB1 into the branch block to speculatively execute it. -static bool SpeculativelyExecuteBB(BranchInst *BI, BasicBlock *BB1, - IRBuilder<> &Builder) { +static bool SpeculativelyExecuteBB(BranchInst *BI, BasicBlock *BB1) { // Only speculatively execution a single instruction (not counting the // terminator) for now. Instruction *HInst = NULL; @@ -1088,16 +1086,14 @@ // Create a select whose true value is the speculatively executed value and // false value is the previously determined FalseV. - Builder.SetInsertPoint(BI); SelectInst *SI; if (Invert) - SI = cast - (Builder.CreateSelect(BrCond, FalseV, HInst, - FalseV->getName() + "." + HInst->getName())); + SI = SelectInst::Create(BrCond, FalseV, HInst, + FalseV->getName() + "." + HInst->getName(), BI); else - SI = cast - (Builder.CreateSelect(BrCond, HInst, FalseV, - HInst->getName() + "." + FalseV->getName())); + SI = SelectInst::Create(BrCond, HInst, FalseV, + HInst->getName() + "." + FalseV->getName(), BI); + SI->setDebugLoc(BI->getDebugLoc()); // Make the PHI node use the select for all incoming values for "then" and // "if" blocks. @@ -1464,7 +1460,6 @@ /// the predecessor and use logical operations to pick the right destination. bool llvm::FoldBranchToCommonDest(BranchInst *BI) { BasicBlock *BB = BI->getParent(); - Instruction *Cond = dyn_cast(BI->getCondition()); if (Cond == 0 || (!isa(Cond) && !isa(Cond)) || Cond->getParent() != BB || !Cond->hasOneUse()) @@ -1585,8 +1580,7 @@ } DEBUG(dbgs() << "FOLDING BRANCH TO COMMON DEST:\n" << *PBI << *BB); - IRBuilder<> Builder(PBI); - + // If we need to invert the condition in the pred block to match, do so now. if (InvertPredCond) { Value *NewCond = PBI->getCondition(); @@ -1595,8 +1589,8 @@ CmpInst *CI = cast(NewCond); CI->setPredicate(CI->getInversePredicate()); } else { - NewCond = Builder.CreateNot(NewCond, - PBI->getCondition()->getName()+".not"); + NewCond = BinaryOperator::CreateNot(NewCond, + PBI->getCondition()->getName()+".not", PBI); } PBI->setCondition(NewCond); @@ -1623,9 +1617,9 @@ New->takeName(Cond); Cond->setName(New->getName()+".old"); - Instruction *NewCond = - cast(Builder.CreateBinOp(Opc, PBI->getCondition(), - New, "or.cond")); + Instruction *NewCond = BinaryOperator::Create(Opc, PBI->getCondition(), + New, "or.cond", PBI); + NewCond->setDebugLoc(PBI->getDebugLoc()); PBI->setCondition(NewCond); if (PBI->getSuccessor(0) == BB) { AddPredecessorToBlock(TrueDest, PredBlock, BB); @@ -1768,22 +1762,23 @@ } DEBUG(dbgs() << *PBI->getParent()->getParent()); - + // BI may have other predecessors. Because of this, we leave // it alone, but modify PBI. // Make sure we get to CommonDest on True&True directions. Value *PBICond = PBI->getCondition(); - IRBuilder<> Builder(PBI); if (PBIOp) - PBICond = Builder.CreateNot(PBICond, PBICond->getName()+".not"); - + PBICond = BinaryOperator::CreateNot(PBICond, + PBICond->getName()+".not", + PBI); Value *BICond = BI->getCondition(); if (BIOp) - BICond = Builder.CreateNot(BICond, BICond->getName()+".not"); - + BICond = BinaryOperator::CreateNot(BICond, + BICond->getName()+".not", + PBI); // Merge the conditions. - Value *Cond = Builder.CreateOr(PBICond, BICond, "brmerge"); + Value *Cond = BinaryOperator::CreateOr(PBICond, BICond, "brmerge", PBI); // Modify PBI to branch on the new condition to the new dests. PBI->setCondition(Cond); @@ -1806,8 +1801,8 @@ Value *PBIV = PN->getIncomingValue(PBBIdx); if (BIV != PBIV) { // Insert a select in PBI to pick the right value. - Value *NV = cast - (Builder.CreateSelect(PBICond, PBIV, BIV, PBIV->getName()+".mux")); + Value *NV = SelectInst::Create(PBICond, PBIV, BIV, + PBIV->getName()+".mux", PBI); PN->setIncomingValue(PBBIdx, NV); } } @@ -2590,7 +2585,7 @@ // can hoist it up to the branching block. if (BI->getSuccessor(0)->getSinglePredecessor() != 0) { if (BI->getSuccessor(1)->getSinglePredecessor() != 0) { - if (HoistThenElseCodeToIf(BI, Builder)) + if (HoistThenElseCodeToIf(BI)) return SimplifyCFG(BB) | true; } else { // If Successor #1 has multiple preds, we may be able to conditionally @@ -2598,7 +2593,7 @@ TerminatorInst *Succ0TI = BI->getSuccessor(0)->getTerminator(); if (Succ0TI->getNumSuccessors() == 1 && Succ0TI->getSuccessor(0) == BI->getSuccessor(1)) - if (SpeculativelyExecuteBB(BI, BI->getSuccessor(0), Builder)) + if (SpeculativelyExecuteBB(BI, BI->getSuccessor(0))) return SimplifyCFG(BB) | true; } } else if (BI->getSuccessor(1)->getSinglePredecessor() != 0) { @@ -2607,7 +2602,7 @@ TerminatorInst *Succ1TI = BI->getSuccessor(1)->getTerminator(); if (Succ1TI->getNumSuccessors() == 1 && Succ1TI->getSuccessor(0) == BI->getSuccessor(0)) - if (SpeculativelyExecuteBB(BI, BI->getSuccessor(1), Builder)) + if (SpeculativelyExecuteBB(BI, BI->getSuccessor(1))) return SimplifyCFG(BB) | true; } From rafael.espindola at gmail.com Wed May 18 21:35:26 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 19 May 2011 02:35:26 -0000 Subject: [llvm-commits] [llvm] r131621 - /llvm/trunk/test/Transforms/SimplifyCFG/PR9946.ll Message-ID: <20110519023527.0893B2A6C12C@llvm.org> Author: rafael Date: Wed May 18 21:35:26 2011 New Revision: 131621 URL: http://llvm.org/viewvc/llvm-project?rev=131621&view=rev Log: Add test for PR9946. Added: llvm/trunk/test/Transforms/SimplifyCFG/PR9946.ll Added: llvm/trunk/test/Transforms/SimplifyCFG/PR9946.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/PR9946.ll?rev=131621&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/PR9946.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/PR9946.ll Wed May 18 21:35:26 2011 @@ -0,0 +1,18 @@ +; RUN: opt %s -simplifycfg -disable-output + + at foo = external constant i32 + +define i32 @f() { +entry: + br i1 icmp eq (i64 and (i64 ptrtoint (i32* @foo to i64), i64 15), i64 0), label %if.end, label %if.then + +if.then: ; preds = %entry + br label %return + +if.end: ; preds = %entry + br label %return + +return: ; preds = %if.end, %if.then + %storemerge = phi i32 [ 1, %if.end ], [ 0, %if.then ] + ret i32 %storemerge +} From cdavis at mines.edu Wed May 18 21:47:23 2011 From: cdavis at mines.edu (Charles Davis) Date: Thu, 19 May 2011 02:47:23 -0000 Subject: [llvm-commits] [llvm] r131622 - in /llvm/trunk/include/llvm: MC/MCWin64EH.h Support/Win64EH.h Message-ID: <20110519024724.05C7A2A6C12C@llvm.org> Author: cdavis Date: Wed May 18 21:47:23 2011 New Revision: 131622 URL: http://llvm.org/viewvc/llvm-project?rev=131622&view=rev Log: Fix build issues with headers, which I discovered by actually using them. Also, convert all the inline functions on UnwindInfo into methods. Modified: llvm/trunk/include/llvm/MC/MCWin64EH.h llvm/trunk/include/llvm/Support/Win64EH.h Modified: llvm/trunk/include/llvm/MC/MCWin64EH.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCWin64EH.h?rev=131622&r1=131621&r2=131622&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCWin64EH.h (original) +++ llvm/trunk/include/llvm/MC/MCWin64EH.h Wed May 18 21:47:23 2011 @@ -33,12 +33,12 @@ MachineLocation Source; public: MCWin64EHInstruction(OpType Op, unsigned Register) - : Operation(Op), Offset(0), Destination(0), Source(S) { + : Operation(Op), Offset(0), Destination(0), Source(Register) { assert(Op == Win64EH::UOP_PushNonVol); } MCWin64EHInstruction(unsigned Size) : Operation(Size>128 ? Win64EH::UOP_AllocLarge : Win64EH::UOP_AllocSmall), - Offset(size) { } + Offset(Size) { } MCWin64EHInstruction(unsigned Register, unsigned Off) : Operation(Win64EH::UOP_SetFPReg), Offset(Off), Destination(Register) { } MCWin64EHInstruction(OpType Op, const MachineLocation &D, @@ -64,7 +64,7 @@ struct MCWin64EHUnwindInfo { MCWin64EHUnwindInfo() : Begin(0), End(0), ExceptionHandler(0), Lsda(0), Function(0), UnwindOnly(false), LsdaSize(0), - PrologSize(0), LastFrameInst(-1), Chained(false) + PrologSize(0), LastFrameInst(-1), Chained(false), Instructions() {} MCSymbol *Begin; MCSymbol *End; Modified: llvm/trunk/include/llvm/Support/Win64EH.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Win64EH.h?rev=131622&r1=131621&r2=131622&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/Win64EH.h (original) +++ llvm/trunk/include/llvm/Support/Win64EH.h Wed May 18 21:47:23 2011 @@ -40,7 +40,7 @@ uint8_t codeOffset; uint8_t unwindOp:4, opInfo:4; - }; + } u; uint16_t frameOffset; }; @@ -56,6 +56,13 @@ UNW_ChainInfo = 0x04 }; +/// RuntimeFunction - An entry in the table of functions with unwind info. +struct RuntimeFunction { + uint64_t startAddress; + uint64_t endAddress; + uint64_t unwindInfoOffset; +}; + /// UnwindInfo - An entry in the exception table. struct UnwindInfo { uint8_t version:3, @@ -65,30 +72,25 @@ uint8_t frameRegister:4, frameOffset:4; UnwindCode unwindCodes[1]; + + void *getLanguageSpecificData() { + return reinterpret_cast(&unwindCodes[(numCodes+1) & ~1]); + } + uint64_t getLanguageSpecificHandlerOffset() { + return *reinterpret_cast(getLanguageSpecificData()); + } + void setLanguageSpecificHandlerOffset(uint64_t offset) { + *reinterpret_cast(getLanguageSpecificData()) = offset; + } + RuntimeFunction *getChainedFunctionEntry() { + return reinterpret_cast(getLanguageSpecificData()); + } + void *getExceptionData() { + return reinterpret_cast(reinterpret_cast( + getLanguageSpecificData())+1); + } }; -inline UnwindCode &getUnwindCodeEntry(UnwindInfo &info, uint32_t index) { - return info.unwindCodes[index]; -} -inline void *getLanguageSpecificData(UnwindInfo &info) { - return reinterpret_cast(&getUnwindCodeEntry(info,info.numCodes+1)&~1); -} -inline uint64_t getLanguageSpecificHandlerOffset(UnwindInfo &info) { - return *reinterpret_cast(getLangaugeSpecificData(info)); -} -inline void setLanguageSpecificHandlerOffset(UnwindInfo &info, uint64_t offset){ - *reinterpret_cast(getLanguageSpecificData(info)) = offset; -} -inline uint64_t getChainedFunctionEntryOffset(UnwindInfo &info) { - return *reinterpret_cast(getLanguageSpecificData(info)); -} -inline void setChainedFunctionEntryOffset(UnwindInfo &info, uint64_t offset) { - *reinterpret_cast(getLanguageSpecificData(info)) = offset; -} -inline void *getExceptionData(UnwindInfo &info) { - return reinterpret_cast(reinterpret_cast( - getLanguageSpecificData(info))+1); -} } // End of namespace Win64EH } // End of namespace llvm From cdavis at mines.edu Wed May 18 21:49:00 2011 From: cdavis at mines.edu (Charles Davis) Date: Thu, 19 May 2011 02:49:00 -0000 Subject: [llvm-commits] [llvm] r131623 - in /llvm/trunk: include/llvm/MC/MCStreamer.h lib/MC/MCStreamer.cpp Message-ID: <20110519024900.E0ECF2A6C12C@llvm.org> Author: cdavis Date: Wed May 18 21:49:00 2011 New Revision: 131623 URL: http://llvm.org/viewvc/llvm-project?rev=131623&view=rev Log: Implement the StartProc and EndProc Win64 EH methods on the base MCStreamer. Based largely on Rafael Espindola's work on CFI. Other methods soon to follow. Modified: llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/lib/MC/MCStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=131623&r1=131622&r2=131623&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed May 18 21:49:00 2011 @@ -18,6 +18,7 @@ #include "llvm/Support/DataTypes.h" #include "llvm/MC/MCDirectives.h" #include "llvm/MC/MCDwarf.h" +#include "llvm/MC/MCWin64EH.h" namespace llvm { class MCAsmInfo; @@ -57,6 +58,10 @@ MCDwarfFrameInfo *getCurrentFrameInfo(); void EnsureValidFrame(); + std::vector W64UnwindInfos; + MCWin64EHUnwindInfo *getCurrentW64UnwindInfo(); + void EnsureValidW64UnwindInfo(); + const MCSymbol* LastNonPrivate; /// SectionStack - This is stack of current and previous section Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=131623&r1=131622&r2=131623&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Wed May 18 21:49:00 2011 @@ -310,16 +310,37 @@ CurFrame->Instructions.push_back(Instruction); } -void MCStreamer::EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler) -{ - errs() << "Not implemented yet\n"; - abort(); -} - -void MCStreamer::EmitWin64EHEndProc() -{ - errs() << "Not implemented yet\n"; - abort(); +MCWin64EHUnwindInfo *MCStreamer::getCurrentW64UnwindInfo() { + if (W64UnwindInfos.empty()) + return NULL; + return &W64UnwindInfos.back(); +} + +void MCStreamer::EnsureValidW64UnwindInfo() { + MCWin64EHUnwindInfo *CurFrame = getCurrentW64UnwindInfo(); + if (!CurFrame || CurFrame->End) + report_fatal_error("No open Win64 EH frame function!"); +} + +void MCStreamer::EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler) { + MCWin64EHUnwindInfo *CurFrame = getCurrentW64UnwindInfo(); + if (CurFrame && !CurFrame->End) + report_fatal_error("Starting a function before ending the previous one!"); + MCWin64EHUnwindInfo Frame; + Frame.Begin = getContext().CreateTempSymbol(); + Frame.Function = Symbol; + Frame.ExceptionHandler = EHandler; + EmitLabel(Frame.Begin); + W64UnwindInfos.push_back(Frame); +} + +void MCStreamer::EmitWin64EHEndProc() { + EnsureValidW64UnwindInfo(); + MCWin64EHUnwindInfo *CurFrame = getCurrentW64UnwindInfo(); + if (CurFrame->Chained) + report_fatal_error("Not all chained regions terminated!"); + CurFrame->End = getContext().CreateTempSymbol(); + EmitLabel(CurFrame->End); } void MCStreamer::EmitWin64EHStartChained() From pichet2000 at gmail.com Wed May 18 21:54:12 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Thu, 19 May 2011 02:54:12 -0000 Subject: [llvm-commits] [llvm] r131624 - /llvm/trunk/include/llvm/Support/StandardPasses.h Message-ID: <20110519025412.16B0B2A6C12C@llvm.org> Author: fpichet Date: Wed May 18 21:54:11 2011 New Revision: 131624 URL: http://llvm.org/viewvc/llvm-project?rev=131624&view=rev Log: Fix the MSVC build. Use a set of overloaded functions instead of template function for CreatePassFn. It seems that template deduction for functions type that differs only by return type doesn't work with MSVC. Modified: llvm/trunk/include/llvm/Support/StandardPasses.h Modified: llvm/trunk/include/llvm/Support/StandardPasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=131624&r1=131623&r2=131624&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) +++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed May 18 21:54:11 2011 @@ -43,16 +43,21 @@ StandardPass::CreateVerifierPass = CreateVerifierPass; } private: - /// Define a template function that does the casting for us, so that we can - /// perform safe function pointer casts, but catch unsafe ones. - template static llvm::Pass* - CreatePassFn(void) { return X(); } - template static llvm::Pass* - CreatePassFn(void) { return X(); } - template static llvm::Pass* - CreatePassFn(void) { return X(); } - template static llvm::Pass* - CreatePassFn(void) { return X(); } + /// Define a set of function overloads that does the casting for us, so + /// that we can perform safe function pointer casts, but catch unsafe ones. + PassInfo::NormalCtor_t static CreatePassFn(llvm::ImmutablePass*(*X)(void)) { + return reinterpret_cast(X); + } + PassInfo::NormalCtor_t static CreatePassFn(llvm::ModulePass*(*X)(void)) { + return reinterpret_cast(X); + } + PassInfo::NormalCtor_t static CreatePassFn(llvm::FunctionPass*(*X)(void)) { + return reinterpret_cast(X); + } + PassInfo::NormalCtor_t static CreatePassFn(llvm::Pass*(*X)(void)) { + return reinterpret_cast(X); + } + static llvm::Pass *CreateVerifierPass() { return createVerifierPass(); } /// Passes must be registered with functions that take no arguments, so we have /// to wrap their existing constructors. @@ -82,7 +87,7 @@ // support "obvious" type-punning idioms. #define DEFAULT_ALIAS_ANALYSIS_PASS(pass, flags)\ StandardPass::RegisterDefaultPass(\ - CreatePassFn,\ + CreatePassFn(create ## pass ## Pass),\ &DefaultStandardPasses::pass ## ID, (unsigned char*)0, StandardPass::AliasAnalysis, flags) DEFAULT_ALIAS_ANALYSIS_PASS(TypeBasedAliasAnalysis, 0); DEFAULT_ALIAS_ANALYSIS_PASS(BasicAliasAnalysis, 0); @@ -90,7 +95,7 @@ #define DEFAULT_FUNCTION_PASS(pass, flags)\ StandardPass::RegisterDefaultPass(\ - CreatePassFn,\ + CreatePassFn(create ## pass ## Pass),\ &DefaultStandardPasses::pass ## ID, 0, StandardPass::Function, flags) DEFAULT_FUNCTION_PASS(CFGSimplification, StandardPass::OptimzationFlags(1)); @@ -101,7 +106,7 @@ #define DEFAULT_MODULE_PASS(pass, flags)\ StandardPass::RegisterDefaultPass(\ - CreatePassFn,\ + CreatePassFn(create ## pass ## Pass),\ &DefaultStandardPasses::pass ## ID, 0, StandardPass::Module, flags) // Optimize out global vars DEFAULT_MODULE_PASS(GlobalOptimizer, @@ -228,7 +233,7 @@ #define DEFAULT_LTO_PASS(pass, flags)\ StandardPass::RegisterDefaultPass(\ - CreatePassFn,\ + CreatePassFn(create ## pass ## Pass),\ &DefaultStandardPasses::pass ## ID, 0, StandardPass::LTO, flags) // LTO passes From pichet2000 at gmail.com Wed May 18 22:00:23 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Wed, 18 May 2011 23:00:23 -0400 Subject: [llvm-commits] [llvm] r131592 - /llvm/trunk/include/llvm/Support/StandardPasses.h In-Reply-To: References: <20110518224602.506AF2A6C12C@llvm.org> Message-ID: On Wed, May 18, 2011 at 10:02 PM, Eli Friedman wrote: > On Wed, May 18, 2011 at 6:35 PM, Francois Pichet wrote: >> On Wed, May 18, 2011 at 6:46 PM, David Chisnall wrote: >>> Author: theraven >>> Date: Wed May 18 17:46:02 2011 >>> New Revision: 131592 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=131592&view=rev >>> Log: >>> Some better type safety enforcement in the standard pass list, along with some small tidies and some fixes for bugs that the stricter checking found. >>> >>> >>> Modified: >>> ? ?llvm/trunk/include/llvm/Support/StandardPasses.h >>> >>> Modified: llvm/trunk/include/llvm/Support/StandardPasses.h >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/StandardPasses.h?rev=131592&r1=131591&r2=131592&view=diff >>> ============================================================================== >>> --- llvm/trunk/include/llvm/Support/StandardPasses.h (original) >>> +++ llvm/trunk/include/llvm/Support/StandardPasses.h Wed May 18 17:46:02 2011 >>> @@ -27,6 +27,7 @@ >>> ?#include "llvm/Transforms/IPO.h" >>> >>> ?namespace llvm { >>> + ? ?//template static Pass *CreatePassFn(void) { return X(); } >>> >>> ? /// RegisterStandardPassLists solves a circular dependency problem. ?The >>> ? /// default list of passes has to live somewhere. ?It can't live in the core >>> @@ -42,23 +43,36 @@ >>> ? ? ? StandardPass::CreateVerifierPass = CreateVerifierPass; >>> ? ? } >>> ? ? private: >>> + ? ?/// Define a template function that does the casting for us, so that we can >>> + ? ?/// perform safe function pointer casts, but catch unsafe ones. >>> + ? ?template static llvm::Pass* >>> + ? ? ?CreatePassFn(void) { return X(); } >>> + ? ?template static llvm::Pass* >>> + ? ? ?CreatePassFn(void) { return X(); } >>> + ? ?template static llvm::Pass* >>> + ? ? ?CreatePassFn(void) { return X(); } >>> + ? ?template static llvm::Pass* >>> + ? ? ?CreatePassFn(void) { return X(); } >>> ? ? static llvm::Pass *CreateVerifierPass() { return createVerifierPass(); } >> >> >> Hi.. this is too much for MSVC 2010. It wont compile: >> >> This is a reduction of the problem: >> =========================== >> class A {}; >> class B {}; >> >> template static void CreatePassFn(void) { ?} >> template static void CreatePassFn(void) { ?} >> >> B* CreatePassX(void); >> >> int main() >> { >> ? CreatePassFn(); // <== error here. >> ? return 1; >> } >> =========================== >> >> This code will compile fine with clang and gcc 4.5. MSVC 2010 will fail. >> Seems like MSVC cannot deduce template arguments that are function and >> that differ only by return type. >> >> Anybody have an idea on how to redesign this to make it MSVC friendly? > > I suppose we could use something like the following instead: > PassInfo::NormalCtor_t static > getPassFn(llvm::ImmutablePass*(*X)(void)) { return > reinterpret_cast(X); } > PassInfo::NormalCtor_t static getPassFn(llvm::ModulePass*(*X)(void)) { > return reinterpret_cast(X); } > PassInfo::NormalCtor_t static getPassFn(llvm::FunctionPass*(*X)(void)) > { return reinterpret_cast(X); } > PassInfo::NormalCtor_t static getPassFn(llvm::Pass*(*X)(void)) { > return reinterpret_cast(X); } > > Does that sort of thing work with MSVC? > yes see r131624. Thank you for your solution. It really helped. From zwarich at apple.com Wed May 18 21:56:23 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 19 May 2011 02:56:23 -0000 Subject: [llvm-commits] [llvm] r131625 - /llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Message-ID: <20110519025623.D3D022A6C12C@llvm.org> Author: zwarich Date: Wed May 18 21:56:23 2011 New Revision: 131625 URL: http://llvm.org/viewvc/llvm-project?rev=131625&view=rev Log: Reuse the TargetInstrDesc. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=131625&r1=131624&r2=131625&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed May 18 21:56:23 2011 @@ -1115,8 +1115,7 @@ MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); MRI.constrainRegClass(BaseReg, TID.OpInfo[0].getRegClass(this)); - MachineInstrBuilder MIB = - BuildMI(*MBB, Ins, DL, TII.get(ADDriOpc), BaseReg) + MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, TID, BaseReg) .addFrameIndex(FrameIdx).addImm(Offset); if (!AFI->isThumb1OnlyFunction()) From zwarich at apple.com Wed May 18 21:56:28 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 19 May 2011 02:56:28 -0000 Subject: [llvm-commits] [llvm] r131626 - in /llvm/trunk/lib/Target/PowerPC: PPCISelDAGToDAG.cpp PPCInstr64Bit.td PPCInstrInfo.td Message-ID: <20110519025628.EA7882A6C12D@llvm.org> Author: zwarich Date: Wed May 18 21:56:28 2011 New Revision: 131626 URL: http://llvm.org/viewvc/llvm-project?rev=131626&view=rev Log: Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointless piclabel operand. The operand in the tablegen definition doesn't actually turn into an MI operand, so it just confuses anything checking the TargetInstrDesc for the number of operands. It suffices to just have an implicit def of LR. Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=131626&r1=131625&r2=131626&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Wed May 18 21:56:28 2011 @@ -240,11 +240,11 @@ if (PPCLowering.getPointerTy() == MVT::i32) { GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass); - BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR), PPC::LR); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); } else { GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass); - BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8), PPC::LR8); + BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8)); BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); } } Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=131626&r1=131625&r2=131626&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Wed May 18 21:56:28 2011 @@ -60,7 +60,7 @@ // let Defs = [LR8] in - def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "", []>, + def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>, PPC970_Unit_BRU; // Darwin ABI Calls. Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td?rev=131626&r1=131625&r2=131626&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.td Wed May 18 21:56:28 2011 @@ -300,7 +300,6 @@ def aaddr : Operand { let PrintMethod = "printAbsAddrOperand"; } -def piclabel: Operand {} def symbolHi: Operand { let PrintMethod = "printSymbolHi"; let EncoderMethod = "getHA16Encoding"; @@ -413,7 +412,7 @@ } let Defs = [LR] in - def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "", []>, + def MovePCtoLR : Pseudo<(outs), (ins), "", []>, PPC970_Unit_BRU; let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { From zwarich at apple.com Wed May 18 22:11:06 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 19 May 2011 03:11:06 -0000 Subject: [llvm-commits] [llvm] r131627 - /llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Message-ID: <20110519031106.BE25F2A6C12C@llvm.org> Author: zwarich Date: Wed May 18 22:11:06 2011 New Revision: 131627 URL: http://llvm.org/viewvc/llvm-project?rev=131627&view=rev Log: Make CodeGen/PowerPC/2007-09-11-RegCoalescerAssert.ll pass with the verifier. Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=131627&r1=131626&r2=131627&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Wed May 18 22:11:06 2011 @@ -1010,7 +1010,8 @@ short Imm; if (isIntS16Immediate(CN, Imm)) { Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy()); - Base = DAG.getRegister(PPC::R0, CN->getValueType(0)); + Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0, + CN->getValueType(0)); return true; } From cdavis at mines.edu Wed May 18 23:04:13 2011 From: cdavis at mines.edu (Charles Davis) Date: Thu, 19 May 2011 04:04:13 -0000 Subject: [llvm-commits] [llvm] r131629 - in /llvm/trunk: include/llvm/MC/MCStreamer.h include/llvm/MC/MCWin64EH.h lib/MC/MCStreamer.cpp Message-ID: <20110519040413.3727F2A6C12C@llvm.org> Author: cdavis Date: Wed May 18 23:04:13 2011 New Revision: 131629 URL: http://llvm.org/viewvc/llvm-project?rev=131629&view=rev Log: Implement the StartChained and EndChained Win64 EH methods on MCStreamer. Modified: llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/include/llvm/MC/MCWin64EH.h llvm/trunk/lib/MC/MCStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=131629&r1=131628&r2=131629&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Wed May 18 23:04:13 2011 @@ -59,7 +59,8 @@ void EnsureValidFrame(); std::vector W64UnwindInfos; - MCWin64EHUnwindInfo *getCurrentW64UnwindInfo(); + MCWin64EHUnwindInfo *CurrentW64UnwindInfo; + void setCurrentW64UnwindInfo(MCWin64EHUnwindInfo *Frame); void EnsureValidW64UnwindInfo(); const MCSymbol* LastNonPrivate; Modified: llvm/trunk/include/llvm/MC/MCWin64EH.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCWin64EH.h?rev=131629&r1=131628&r2=131629&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCWin64EH.h (original) +++ llvm/trunk/include/llvm/MC/MCWin64EH.h Wed May 18 23:04:13 2011 @@ -64,7 +64,7 @@ struct MCWin64EHUnwindInfo { MCWin64EHUnwindInfo() : Begin(0), End(0), ExceptionHandler(0), Lsda(0), Function(0), UnwindOnly(false), LsdaSize(0), - PrologSize(0), LastFrameInst(-1), Chained(false), + PrologSize(0), LastFrameInst(-1), ChainedParent(0), Instructions() {} MCSymbol *Begin; MCSymbol *End; @@ -75,7 +75,7 @@ unsigned LsdaSize; unsigned PrologSize; int LastFrameInst; - bool Chained; + MCWin64EHUnwindInfo *ChainedParent; std::vector Instructions; }; Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=131629&r1=131628&r2=131629&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Wed May 18 23:04:13 2011 @@ -310,20 +310,19 @@ CurFrame->Instructions.push_back(Instruction); } -MCWin64EHUnwindInfo *MCStreamer::getCurrentW64UnwindInfo() { - if (W64UnwindInfos.empty()) - return NULL; - return &W64UnwindInfos.back(); +void MCStreamer::setCurrentW64UnwindInfo(MCWin64EHUnwindInfo *Frame) { + W64UnwindInfos.push_back(*Frame); + CurrentW64UnwindInfo = &W64UnwindInfos.back(); } void MCStreamer::EnsureValidW64UnwindInfo() { - MCWin64EHUnwindInfo *CurFrame = getCurrentW64UnwindInfo(); + MCWin64EHUnwindInfo *CurFrame = CurrentW64UnwindInfo; if (!CurFrame || CurFrame->End) report_fatal_error("No open Win64 EH frame function!"); } void MCStreamer::EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler) { - MCWin64EHUnwindInfo *CurFrame = getCurrentW64UnwindInfo(); + MCWin64EHUnwindInfo *CurFrame = CurrentW64UnwindInfo; if (CurFrame && !CurFrame->End) report_fatal_error("Starting a function before ending the previous one!"); MCWin64EHUnwindInfo Frame; @@ -331,13 +330,13 @@ Frame.Function = Symbol; Frame.ExceptionHandler = EHandler; EmitLabel(Frame.Begin); - W64UnwindInfos.push_back(Frame); + setCurrentW64UnwindInfo(&Frame); } void MCStreamer::EmitWin64EHEndProc() { EnsureValidW64UnwindInfo(); - MCWin64EHUnwindInfo *CurFrame = getCurrentW64UnwindInfo(); - if (CurFrame->Chained) + MCWin64EHUnwindInfo *CurFrame = CurrentW64UnwindInfo; + if (CurFrame->ChainedParent) report_fatal_error("Not all chained regions terminated!"); CurFrame->End = getContext().CreateTempSymbol(); EmitLabel(CurFrame->End); @@ -345,14 +344,25 @@ void MCStreamer::EmitWin64EHStartChained() { - errs() << "Not implemented yet\n"; - abort(); + EnsureValidW64UnwindInfo(); + MCWin64EHUnwindInfo Frame; + MCWin64EHUnwindInfo *CurFrame = CurrentW64UnwindInfo; + Frame.Begin = getContext().CreateTempSymbol(); + Frame.Function = CurFrame->Function; + Frame.ChainedParent = CurFrame; + EmitLabel(Frame.Begin); + setCurrentW64UnwindInfo(&Frame); } void MCStreamer::EmitWin64EHEndChained() { - errs() << "Not implemented yet\n"; - abort(); + EnsureValidW64UnwindInfo(); + MCWin64EHUnwindInfo *CurFrame = CurrentW64UnwindInfo; + if (!CurFrame->ChainedParent) + report_fatal_error("End of a chained region outside a chained region!"); + CurFrame->End = getContext().CreateTempSymbol(); + EmitLabel(CurFrame->End); + CurrentW64UnwindInfo = CurFrame->ChainedParent; } void MCStreamer::EmitWin64EHUnwindOnly() From wangmp at apple.com Wed May 18 23:15:07 2011 From: wangmp at apple.com (Mon P Wang) Date: Thu, 19 May 2011 04:15:07 -0000 Subject: [llvm-commits] [llvm] r131630 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20110519041508.055B42A6C12C@llvm.org> Author: wangmp Date: Wed May 18 23:15:07 2011 New Revision: 131630 URL: http://llvm.org/viewvc/llvm-project?rev=131630&view=rev Log: Fixed sdiv and udiv for <4 x i16>. The test from r125402 still applies for this change. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=131630&r1=131629&r2=131630&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed May 18 23:15:07 2011 @@ -4663,10 +4663,10 @@ // Because short has a smaller range than ushort, we can actually get away // with only a single newton step. This requires that we use a weird bias // of 89, however (again, this has been exhaustively tested). - // float4 result = as_float4(as_int4(xf*recip) + 89); + // float4 result = as_float4(as_int4(xf*recip) + 0x89); N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); - N1 = DAG.getConstant(89, MVT::i32); + N1 = DAG.getConstant(0x89, MVT::i32); N1 = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, N1, N1, N1, N1); N0 = DAG.getNode(ISD::ADD, dl, MVT::v4i32, N0, N1); N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, N0); @@ -4753,26 +4753,26 @@ N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); N0 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N0); - N1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); + SDValue BN1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::v4f32, N1); // Use reciprocal estimate and two refinement steps. // float4 recip = vrecpeq_f32(yf); // recip *= vrecpsq_f32(yf, recip); // recip *= vrecpsq_f32(yf, recip); N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, - DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), N1); + DAG.getConstant(Intrinsic::arm_neon_vrecpe, MVT::i32), BN1); N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), - N1, N2); + BN1, N2); N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); N1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, DAG.getConstant(Intrinsic::arm_neon_vrecps, MVT::i32), - N1, N2); + BN1, N2); N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); // Simply multiplying by the reciprocal estimate can leave us a few ulps // too low, so we add 2 ulps (exhaustive testing shows that this is enough, // and that it will never cause us to return an answer too large). - // float4 result = as_float4(as_int4(xf*recip) + 89); + // float4 result = as_float4(as_int4(xf*recip) + 2); N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); N0 = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, N0); N1 = DAG.getConstant(2, MVT::i32); From zwarich at apple.com Wed May 18 23:44:19 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Thu, 19 May 2011 04:44:19 -0000 Subject: [llvm-commits] [llvm] r131631 - /llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Message-ID: <20110519044419.C79132A6C12C@llvm.org> Author: zwarich Date: Wed May 18 23:44:19 2011 New Revision: 131631 URL: http://llvm.org/viewvc/llvm-project?rev=131631&view=rev Log: Use the correct register class for Cell varargs spilling. This fixes all of the verifier failures in the CodeGen/CellSPU tests. Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=131631&r1=131630&r2=131631&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Wed May 18 23:44:19 2011 @@ -1215,7 +1215,7 @@ FuncInfo->setVarArgsFrameIndex( MFI->CreateFixedObject(StackSlotSize, ArgOffset, true)); SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT); - unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass); + unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::VECREGRegClass); SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8); SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, MachinePointerInfo(), false, false, 0); From stuart at apple.com Thu May 19 00:53:22 2011 From: stuart at apple.com (Stuart Hastings) Date: Thu, 19 May 2011 05:53:22 -0000 Subject: [llvm-commits] [llvm] r131634 - in /llvm/trunk/test: CodeGen/X86/vec_shuffle-36.ll Transforms/InstCombine/vec_demanded_elts.ll Message-ID: <20110519055322.AF2752A6C12C@llvm.org> Author: stuart Date: Thu May 19 00:53:22 2011 New Revision: 131634 URL: http://llvm.org/viewvc/llvm-project?rev=131634&view=rev Log: Move test to Transforms/InstCombine. Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts.ll Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll?rev=131634&r1=131633&r2=131634&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll (original) +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll Thu May 19 00:53:22 2011 @@ -1,5 +1,4 @@ ; RUN: llc < %s -march=x86-64 -mattr=sse41 | FileCheck %s -; RUN: opt -std-compile-opts < %s | llc -march=x86-64 -mattr=sse41 | FileCheck --check-prefix=CHECK_OPT_LLC %s define <8 x i16> @shuf6(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone { ; CHECK: pshufb @@ -15,21 +14,3 @@ %tmp10 = shufflevector <8 x i16> %t0, <8 x i16> undef, <8 x i32> < i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 undef, i32 undef > ret <8 x i16> %tmp10 } - - -; -define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind { -entry: -; CHECK_OPT_LLC: call{{.*nothing}} - call void @nothing() - %tmp = load <4 x i16>* %src - %tmp1 = load <8 x i16>* %foo -; pmovzxwd ignores the upper 64-bits of its input; everything between the call and pmovzxwd should be removed. - %tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> - %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> -; CHECK_OPT_LLC-NEXT: pmovzxwd - %0 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3) - ret <4 x i32> %0 -} -declare void @nothing() nounwind -declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone Modified: llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts.ll?rev=131634&r1=131633&r2=131634&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/vec_demanded_elts.ll Thu May 19 00:53:22 2011 @@ -136,3 +136,19 @@ declare i64 @llvm.x86.sse2.cvtsd2si64(<2 x double>) declare i32 @llvm.x86.sse2.cvttsd2si(<2 x double>) declare i64 @llvm.x86.sse2.cvttsd2si64(<2 x double>) + +; +define <4 x i32> @kernel3_vertical(<4 x i16> * %src, <8 x i16> * %foo) nounwind { +entry: + %tmp = load <4 x i16>* %src + %tmp1 = load <8 x i16>* %foo +; CHECK: %tmp2 = shufflevector + %tmp2 = shufflevector <4 x i16> %tmp, <4 x i16> undef, <8 x i32> +; pmovzxwd ignores the upper 64-bits of its input; -instcombine should remove this shuffle: +; CHECK-NOT: shufflevector + %tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> +; CHECK-NEXT: pmovzxwd + %0 = call <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16> %tmp3) + ret <4 x i32> %0 +} +declare <4 x i32> @llvm.x86.sse41.pmovzxwd(<8 x i16>) nounwind readnone From stuart at apple.com Thu May 19 00:59:44 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 18 May 2011 22:59:44 -0700 Subject: [llvm-commits] [llvm] r131539 - in /llvm/trunk/test/CodeGen/X86: 2011-05-17-pmovzxwd.ll vec_shuffle-36.ll In-Reply-To: References: <20110518170204.3E9F52A6C12C@llvm.org> Message-ID: On May 18, 2011, at 2:28 PM, Chris Lattner wrote: > On May 18, 2011, at 10:02 AM, Stuart Hastings wrote: >> URL: http://llvm.org/viewvc/llvm-project?rev=131539&view=rev >> Log: >> Merge pmovzx test case into existing file. > > One more thing: > >> +++ llvm/trunk/test/CodeGen/X86/vec_shuffle-36.ll Wed May 18 12:02:04 2011 >> @@ -1,4 +1,5 @@ >> ; RUN: llc < %s -march=x86-64 -mattr=sse41 | FileCheck %s >> +; RUN: opt -std-compile-opts < %s | llc -march=x86-64 -mattr=sse41 | FileCheck --check-prefix=CHECK_OPT_LLC %s > > Why are you running -std-compile-opts here? This is an instcombine patch, so the test should go in Transforms/Instcombine, and should *only* run instcombine. Done in 131634. stuart From baldrick at free.fr Thu May 19 04:39:04 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 19 May 2011 09:39:04 -0000 Subject: [llvm-commits] [dragonegg] r131635 - in /dragonegg/trunk/src/x86: Target.cpp x86_builtins Message-ID: <20110519093904.C08632A6C12C@llvm.org> Author: baldrick Date: Thu May 19 04:39:04 2011 New Revision: 131635 URL: http://llvm.org/viewvc/llvm-project?rev=131635&view=rev Log: Restore support for non-temporal vector moves (which was lost when the corresponding intrinsics were removed from LLVM). Modified: dragonegg/trunk/src/x86/Target.cpp dragonegg/trunk/src/x86/x86_builtins Modified: dragonegg/trunk/src/x86/Target.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/x86/Target.cpp?rev=131635&r1=131634&r2=131635&view=diff ============================================================================== --- dragonegg/trunk/src/x86/Target.cpp (original) +++ dragonegg/trunk/src/x86/Target.cpp Thu May 19 04:39:04 2011 @@ -753,6 +753,30 @@ return true; } } + case movntdq: + case movntdq256: + case movntdqa: + case movnti: + case movntpd: + case movntpd256: + case movntps: + case movntps256: + case movntq: + case movntsd: + case movntss: { + MDNode *Node = MDNode::get(Context, Builder.getInt32(1)); + + // Convert the type of the pointer to a pointer to the stored type. + unsigned AS = cast(Ops[0]->getType())->getAddressSpace(); + Value *Ptr = Builder.CreateBitCast(Ops[0], + PointerType::get(Ops[1]->getType(), AS), + "cast"); + + StoreInst *SI = Builder.CreateStore(Ops[1], Ptr); + SI->setMetadata(TheModule->getMDKindID("nontemporal"), Node); + SI->setAlignment(16); + return SI; + } } DieAbjectly("Builtin not implemented!", stmt); return false; Modified: dragonegg/trunk/src/x86/x86_builtins URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/x86/x86_builtins?rev=131635&r1=131634&r2=131635&view=diff ============================================================================== --- dragonegg/trunk/src/x86/x86_builtins (original) +++ dragonegg/trunk/src/x86/x86_builtins Thu May 19 04:39:04 2011 @@ -206,17 +206,17 @@ //DEFINE_BUILTIN(movmskpd256), //DEFINE_BUILTIN(movmskps), //DEFINE_BUILTIN(movmskps256), -//DEFINE_BUILTIN(movntdq), -//DEFINE_BUILTIN(movntdq256), -//DEFINE_BUILTIN(movntdqa), -//DEFINE_BUILTIN(movnti), -//DEFINE_BUILTIN(movntpd), -//DEFINE_BUILTIN(movntpd256), -//DEFINE_BUILTIN(movntps), -//DEFINE_BUILTIN(movntps256), -//DEFINE_BUILTIN(movntq), -//DEFINE_BUILTIN(movntsd), -//DEFINE_BUILTIN(movntss), +DEFINE_BUILTIN(movntdq), +DEFINE_BUILTIN(movntdq256), +DEFINE_BUILTIN(movntdqa), +DEFINE_BUILTIN(movnti), +DEFINE_BUILTIN(movntpd), +DEFINE_BUILTIN(movntpd256), +DEFINE_BUILTIN(movntps), +DEFINE_BUILTIN(movntps256), +DEFINE_BUILTIN(movntq), +DEFINE_BUILTIN(movntsd), +DEFINE_BUILTIN(movntss), DEFINE_BUILTIN(movq128), DEFINE_BUILTIN(movsd), DEFINE_BUILTIN(movshdup), From aggarwa4 at illinois.edu Thu May 19 10:01:13 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 19 May 2011 15:01:13 -0000 Subject: [llvm-commits] [poolalloc] r131638 - /poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp Message-ID: <20110519150113.D8A752A6C12C@llvm.org> Author: aggarwa4 Date: Thu May 19 10:01:13 2011 New Revision: 131638 URL: http://llvm.org/viewvc/llvm-project?rev=131638&view=rev Log: The cloned function created, should have internal linkage. Modified: poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp Modified: poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp?rev=131638&r1=131637&r2=131638&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp (original) +++ poolalloc/trunk/lib/AssistDS/StructReturnToPointer.cpp Thu May 19 10:01:13 2011 @@ -73,7 +73,9 @@ const FunctionType *NFTy = FunctionType::get(F->getReturnType(), TP, F->isVarArg()); // Create the new function body and insert it into the module. - Function *NF = Function::Create(NFTy, F->getLinkage(), F->getName(), &M); + Function *NF = Function::Create(NFTy, + GlobalValue::InternalLinkage, + F->getName(), &M); DenseMap ValueMap; Function::arg_iterator NI = NF->arg_begin(); NI->setName("ret"); From grosbach at apple.com Thu May 19 10:49:27 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 May 2011 08:49:27 -0700 Subject: [llvm-commits] [llvm] r131560 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/bool-zext.ll test/CodeGen/X86/vararg_tailcall.ll In-Reply-To: <20110518195950.8F2B62A6C12C@llvm.org> References: <20110518195950.8F2B62A6C12C@llvm.org> Message-ID: Hi Chad, There's a vararg tailcall testsuite failure on a MinGW buildbot that is likely related (http://google1.osuosl.org:8011/builders/llvm-gcc-native-mingw32-win7/builds/1942). Entirely possible the testcase just needs updated somehow to reflect your changes (maybe it needs a target triple specified?). Can you have a look? Thanks, -Jim On May 18, 2011, at 12:59 PM, Chad Rosier wrote: > Author: mcrosier > Date: Wed May 18 14:59:50 2011 > New Revision: 131560 > > URL: http://llvm.org/viewvc/llvm-project?rev=131560&view=rev > Log: > Enables vararg functions that pass all arguments via registers to be optimized into tail-calls when possible. > > Added: > llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll > Modified: > llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > llvm/trunk/test/CodeGen/X86/bool-zext.ll > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=131560&r1=131559&r2=131560&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed May 18 14:59:50 2011 > @@ -2525,16 +2525,29 @@ > if (RegInfo->needsStackRealignment(MF)) > return false; > > - // Do not sibcall optimize vararg calls unless the call site is not passing > - // any arguments. > - if (isVarArg && !Outs.empty()) > - return false; > - > // Also avoid sibcall optimization if either caller or callee uses struct > // return semantics. > if (isCalleeStructRet || isCallerStructRet) > return false; > > + // Do not sibcall optimize vararg calls unless all arguments are passed via > + // registers > + if (isVarArg && !Outs.empty()) { > + SmallVector ArgLocs; > + CCState CCInfo(CalleeCC, isVarArg, getTargetMachine(), > + ArgLocs, *DAG.getContext()); > + > + // Allocate shadow area for Win64 > + if (Subtarget->isTargetWin64()) { > + CCInfo.AllocateStack(32, 8); > + } > + > + CCInfo.AnalyzeCallOperands(Outs, CC_X86); > + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) > + if (!ArgLocs[i].isRegLoc()) > + return false; > + } > + > // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. > // Therefore if it's not used by the call it is not safe to optimize this into > // a sibcall. > > Modified: llvm/trunk/test/CodeGen/X86/bool-zext.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bool-zext.ll?rev=131560&r1=131559&r2=131560&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/bool-zext.ll (original) > +++ llvm/trunk/test/CodeGen/X86/bool-zext.ll Wed May 18 14:59:50 2011 > @@ -2,7 +2,7 @@ > > ; CHECK: @bar1 > ; CHECK: movzbl > -; CHECK: callq > +; CHECK: jmp > define void @bar1(i1 zeroext %v1) nounwind ssp { > entry: > %conv = zext i1 %v1 to i32 > @@ -12,7 +12,7 @@ > > ; CHECK: @bar2 > ; CHECK-NOT: movzbl > -; CHECK: callq > +; CHECK: jmp > define void @bar2(i8 zeroext %v1) nounwind ssp { > entry: > %conv = zext i8 %v1 to i32 > > Added: llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll?rev=131560&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll (added) > +++ llvm/trunk/test/CodeGen/X86/vararg_tailcall.ll Wed May 18 14:59:50 2011 > @@ -0,0 +1,85 @@ > +; RUN: llc < %s -march=x86-64 | FileCheck %s > + > + at .str = private unnamed_addr constant [5 x i8] c"%ld\0A\00" > + at sel = external global i8* > + at sel3 = external global i8* > + at sel4 = external global i8* > + at sel5 = external global i8* > + at sel6 = external global i8* > + at sel7 = external global i8* > + > +; CHECK: @foo > +; CHECK: jmp > +define void @foo(i64 %arg) nounwind optsize ssp noredzone { > +entry: > + %call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone > + ret void > +} > + > +declare i32 @printf(i8*, ...) optsize noredzone > + > +; CHECK: @bar > +; CHECK: jmp > +define void @bar(i64 %arg) nounwind optsize ssp noredzone { > +entry: > + tail call void @bar2(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %arg) nounwind optsize noredzone > + ret void > +} > + > +declare void @bar2(i8*, i64) optsize noredzone > + > +; CHECK: @foo2 > +; CHECK: jmp > +define i8* @foo2(i8* %arg) nounwind optsize ssp noredzone { > +entry: > + %tmp1 = load i8** @sel, align 8, !tbaa !0 > + %call = tail call i8* (i8*, i8*, ...)* @x2(i8* %arg, i8* %tmp1) nounwind optsize noredzone > + ret i8* %call > +} > + > +declare i8* @x2(i8*, i8*, ...) optsize noredzone > + > +; CHECK: @foo6 > +; CHECK: jmp > +define i8* @foo6(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { > +entry: > + %tmp2 = load i8** @sel3, align 8, !tbaa !0 > + %tmp3 = load i8** @sel4, align 8, !tbaa !0 > + %tmp4 = load i8** @sel5, align 8, !tbaa !0 > + %tmp5 = load i8** @sel6, align 8, !tbaa !0 > + %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5) nounwind optsize noredzone > + ret i8* %call > +} > + > +declare i8* @x3(i8*, i8*, i8*, ...) optsize noredzone > + > +; CHECK: @foo7 > +; CHECK: callq > +define i8* @foo7(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { > +entry: > + %tmp2 = load i8** @sel3, align 8, !tbaa !0 > + %tmp3 = load i8** @sel4, align 8, !tbaa !0 > + %tmp4 = load i8** @sel5, align 8, !tbaa !0 > + %tmp5 = load i8** @sel6, align 8, !tbaa !0 > + %tmp6 = load i8** @sel7, align 8, !tbaa !0 > + %call = tail call i8* (i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...)* @x7(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i8* %tmp6) nounwind optsize noredzone > + ret i8* %call > +} > + > +declare i8* @x7(i8*, i8*, i8*, i8*, i8*, i8*, i8*, ...) optsize noredzone > + > +; CHECK: @foo8 > +; CHECK: callq > +define i8* @foo8(i8* %arg1, i8* %arg2) nounwind optsize ssp noredzone { > +entry: > + %tmp2 = load i8** @sel3, align 8, !tbaa !0 > + %tmp3 = load i8** @sel4, align 8, !tbaa !0 > + %tmp4 = load i8** @sel5, align 8, !tbaa !0 > + %tmp5 = load i8** @sel6, align 8, !tbaa !0 > + %call = tail call i8* (i8*, i8*, i8*, ...)* @x3(i8* %arg1, i8* %arg2, i8* %tmp2, i8* %tmp3, i8* %tmp4, i8* %tmp5, i32 48879, i32 48879) nounwind optsize noredzone > + ret i8* %call > +} > + > +!0 = metadata !{metadata !"any pointer", metadata !1} > +!1 = metadata !{metadata !"omnipotent char", metadata !2} > +!2 = metadata !{metadata !"Simple C/C++ TBAA", null} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stuart at apple.com Thu May 19 11:59:50 2011 From: stuart at apple.com (Stuart Hastings) Date: Thu, 19 May 2011 16:59:50 -0000 Subject: [llvm-commits] [llvm] r131641 - in /llvm/trunk/lib/Target/X86: X86InstrCompiler.td X86InstrExtension.td X86MCInstLower.cpp Message-ID: <20110519165951.08EE22A6C12C@llvm.org> Author: stuart Date: Thu May 19 11:59:50 2011 New Revision: 131641 URL: http://llvm.org/viewvc/llvm-project?rev=131641&view=rev Log: Revise MOVSX16rr8/MOVZX16rr8 (and rm variants) to no longer be pseudos. rdar://problem/8614450 Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td llvm/trunk/lib/Target/X86/X86InstrExtension.td llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=131641&r1=131640&r2=131641&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Thu May 19 11:59:50 2011 @@ -997,7 +997,8 @@ // anyext. Define these to do an explicit zero-extend to // avoid partial-register updates. -def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>; +def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG + (MOVZX32rr8 GR8 :$src), sub_16bit)>; def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. @@ -1164,9 +1165,9 @@ Requires<[In32BitMode]>; // r & (2^8-1) ==> movz def : Pat<(and GR16:$src1, 0xff), - (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1, - GR16_ABCD)), - sub_8bit))>, + (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG + (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)), + sub_16bit)>, Requires<[In32BitMode]>; // r & (2^32-1) ==> movz @@ -1184,7 +1185,8 @@ Requires<[In64BitMode]>; // r & (2^8-1) ==> movz def : Pat<(and GR16:$src1, 0xff), - (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)))>, + (EXTRACT_SUBREG (MOVZX32rr8 (i8 + (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>, Requires<[In64BitMode]>; @@ -1196,10 +1198,11 @@ GR32_ABCD)), sub_8bit))>, Requires<[In32BitMode]>; + def : Pat<(sext_inreg GR16:$src, i8), - (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, - GR16_ABCD)), - sub_8bit))>, + (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG + (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))), + sub_16bit)>, Requires<[In32BitMode]>; def : Pat<(sext_inreg GR64:$src, i32), @@ -1212,10 +1215,10 @@ (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, Requires<[In64BitMode]>; def : Pat<(sext_inreg GR16:$src, i8), - (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, sub_8bit)))>, + (EXTRACT_SUBREG (MOVSX32rr8 + (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>, Requires<[In64BitMode]>; - // trunc patterns def : Pat<(i16 (trunc GR32:$src)), (EXTRACT_SUBREG GR32:$src, sub_16bit)>; Modified: llvm/trunk/lib/Target/X86/X86InstrExtension.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrExtension.td?rev=131641&r1=131640&r2=131641&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrExtension.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrExtension.td Thu May 19 11:59:50 2011 @@ -45,14 +45,12 @@ "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; - -// FIXME: Use a pat pattern or define a syntax here. -let isCodeGenOnly=1 in { def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), - "", [(set GR16:$dst, (sext GR8:$src))]>, TB; + "movs{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (sext GR8:$src))]>, TB; def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), - "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB; -} + "movs{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB; def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), "movs{bl|x}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (sext GR8:$src))]>, TB; @@ -73,13 +71,12 @@ "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; -// FIXME: Use a pat pattern or define a syntax here. -let isCodeGenOnly=1 in { def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), - "", [(set GR16:$dst, (zext GR8:$src))]>, TB; + "movz{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (zext GR8:$src))]>, TB; def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), - "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB; -} + "movz{bl|x}\t{$src, $dst|$dst, $src}", + [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB; def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), "movz{bl|x}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (zext GR8:$src))]>, TB; Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=131641&r1=131640&r2=131641&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Thu May 19 11:59:50 2011 @@ -355,10 +355,6 @@ assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && "LEA has segment specified!"); break; - case X86::MOVZX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break; - case X86::MOVZX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break; - case X86::MOVSX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break; - case X86::MOVSX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break; case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break; case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break; case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break; From ahatanak at gmail.com Thu May 19 12:21:09 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 19 May 2011 17:21:09 -0000 Subject: [llvm-commits] [llvm] r131642 - /llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Message-ID: <20110519172109.7CCD82A6C12C@llvm.org> Author: ahatanak Date: Thu May 19 12:21:09 2011 New Revision: 131642 URL: http://llvm.org/viewvc/llvm-project?rev=131642&view=rev Log: Fix data layout string. i64 is aligned to 64 bit boundaries. Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=131642&r1=131641&r2=131642&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Thu May 19 12:21:09 2011 @@ -38,8 +38,9 @@ bool isLittle=false): LLVMTargetMachine(T, TT), Subtarget(TT, FS, isLittle), - DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-n32") : - std::string("E-p:32:32:32-i8:8:32-i16:16:32-n32")), + DataLayout(isLittle ? + std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : + std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")), InstrInfo(*this), FrameLowering(Subtarget), TLInfo(*this), TSInfo(*this) { From joerg at bec.de Thu May 19 12:27:01 2011 From: joerg at bec.de (Joerg Sonnenberger) Date: Thu, 19 May 2011 17:27:01 -0000 Subject: [llvm-commits] [llvm] r131644 - in /llvm/trunk/lib/MC/MCParser: AsmParser.cpp DarwinAsmParser.cpp Message-ID: <20110519172701.A5B2B2A6C12C@llvm.org> Author: joerg Date: Thu May 19 12:27:01 2011 New Revision: 131644 URL: http://llvm.org/viewvc/llvm-project?rev=131644&view=rev Log: Introduce -fatal-assembler-warnings for the obvious purpose Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=131644&r1=131643&r2=131644&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu May 19 12:27:01 2011 @@ -27,6 +27,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCDwarf.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" @@ -36,6 +37,10 @@ #include using namespace llvm; +static cl::opt +FatalAssemblerWarnings("fatal-assembler-warnings", + cl::desc("Consider warnings as error")); + namespace { /// \brief Helper class for tracking macro definitions. @@ -128,7 +133,7 @@ virtual MCContext &getContext() { return Ctx; } virtual MCStreamer &getStreamer() { return Out; } - virtual void Warning(SMLoc L, const Twine &Meg); + virtual bool Warning(SMLoc L, const Twine &Meg); virtual bool Error(SMLoc L, const Twine &Msg); const AsmToken &Lex(); @@ -370,9 +375,12 @@ "note"); } -void AsmParser::Warning(SMLoc L, const Twine &Msg) { +bool AsmParser::Warning(SMLoc L, const Twine &Msg) { + if (FatalAssemblerWarnings) + return Error(L, Msg); PrintMessage(L, Msg, "warning"); PrintMacroInstantiations(); + return false; } bool AsmParser::Error(SMLoc L, const Twine &Msg) { @@ -1129,9 +1137,9 @@ if (!getTargetParser().ParseDirective(ID)) return false; - Warning(IDLoc, "ignoring directive for now"); + bool retval = Warning(IDLoc, "ignoring directive for now"); EatToEndOfStatement(); - return false; + return retval; } CheckForValidSection(); Modified: llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp?rev=131644&r1=131643&r2=131644&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp Thu May 19 12:27:01 2011 @@ -369,11 +369,9 @@ // FIXME: If/when .dump and .load are implemented they will be done in the // the assembly parser and not have any need for an MCStreamer API. if (IsDump) - Warning(IDLoc, "ignoring directive .dump for now"); + return Warning(IDLoc, "ignoring directive .dump for now"); else - Warning(IDLoc, "ignoring directive .load for now"); - - return false; + return Warning(IDLoc, "ignoring directive .load for now"); } /// ParseDirectiveLsym From gohman at apple.com Thu May 19 12:35:21 2011 From: gohman at apple.com (Dan Gohman) Date: Thu, 19 May 2011 10:35:21 -0700 Subject: [llvm-commits] [llvm] r131576 - in /llvm/trunk: lib/Transforms/Scalar/LoopStrengthReduce.cpp test/Transforms/LoopStrengthReduce/post-inc-icmpzero.ll In-Reply-To: <4DD45695.8090303@gmail.com> References: <20110518210219.1AD8A2A6C12C@llvm.org> <4DD45695.8090303@gmail.com> Message-ID: <0A611E9A-73E1-4AC8-B703-B36F0CE9BD2A@apple.com> On May 18, 2011, at 4:30 PM, Rafael Avila de Espindola wrote: > On 11-05-18 05:02 PM, Dan Gohman wrote: > >> +; CHECK: %tmp2 = sub i64 %sub.ptr.lhs.cast, %sub.ptr.rhs.cast >> +; CHECK: %tmp3 = lshr i64 %tmp2, 1 >> +; CHECK: %tmp4 = mul i64 %tmp3, 2 >> +; CHECK: br label %for.body >> +; CHECK: for.body: >> +; CHECK: %lsr.iv5 = phi i64 [ %lsr.iv.next, %for.body ], [ %tmp4, %for.body.lr.ph ] >> +; CHECK: %lsr.iv.next = add i64 %lsr.iv5, -2 >> +; CHECK: %lsr.iv.next6 = inttoptr i64 %lsr.iv.next to i16* >> +; CHECK: %cmp27 = icmp eq i16* %lsr.iv.next6, null >> > > Don't you want a CHECK-NEXT here to check that the old > > %tmp8 = add i64 %tmp7, -2 > > is not being created? If it somehow were created, something would have to reference it for it to matter, and that would break the pattern. Dan From grosbach at apple.com Thu May 19 12:34:53 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 19 May 2011 17:34:53 -0000 Subject: [llvm-commits] [llvm] r131649 - /llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Message-ID: <20110519173453.AA9552A6C12E@llvm.org> Author: grosbach Date: Thu May 19 12:34:53 2011 New Revision: 131649 URL: http://llvm.org/viewvc/llvm-project?rev=131649&view=rev Log: 80 columns. Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrFormats.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrFormats.td?rev=131649&r1=131648&r2=131649&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrFormats.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrFormats.td Thu May 19 12:34:53 2011 @@ -1750,9 +1750,10 @@ // NEON 3 vector register format. -class N3VCommon op21_20, bits<4> op11_8, bit op6, bit op4, - dag oops, dag iops, Format f, InstrItinClass itin, - string opc, string dt, string asm, string cstr, list pattern> +class N3VCommon op21_20, bits<4> op11_8, bit op6, + bit op4, dag oops, dag iops, Format f, InstrItinClass itin, + string opc, string dt, string asm, string cstr, + list pattern> : NDataI { let Inst{24} = op24; let Inst{23} = op23; @@ -1781,9 +1782,10 @@ let Inst{5} = Vm{4}; } -class N3VLane32 op21_20, bits<4> op11_8, bit op6, bit op4, - dag oops, dag iops, Format f, InstrItinClass itin, - string opc, string dt, string asm, string cstr, list pattern> +class N3VLane32 op21_20, bits<4> op11_8, bit op6, + bit op4, dag oops, dag iops, Format f, InstrItinClass itin, + string opc, string dt, string asm, string cstr, + list pattern> : N3VCommon { @@ -1801,9 +1803,10 @@ let Inst{5} = lane; } -class N3VLane16 op21_20, bits<4> op11_8, bit op6, bit op4, - dag oops, dag iops, Format f, InstrItinClass itin, - string opc, string dt, string asm, string cstr, list pattern> +class N3VLane16 op21_20, bits<4> op11_8, bit op6, + bit op4, dag oops, dag iops, Format f, InstrItinClass itin, + string opc, string dt, string asm, string cstr, + list pattern> : N3VCommon { From gohman at apple.com Thu May 19 12:50:55 2011 From: gohman at apple.com (Dan Gohman) Date: Thu, 19 May 2011 10:50:55 -0700 Subject: [llvm-commits] [llvm] r131186 - in /llvm/trunk: include/llvm/Support/Program.h lib/Support/Program.cpp lib/Support/Unix/Program.inc tools/bugpoint/ExecutionDriver.cpp tools/bugpoint/Miscompilation.cpp tools/bugpoint/ToolRunner.cpp In-Reply-To: References: <20110511163124.D83B82A6C12C@llvm.org> Message-ID: On May 18, 2011, at 5:03 PM, Andrew Trick wrote: > On May 18, 2011, at 2:42 PM, Dan Gohman wrote: > >>> --- llvm/trunk/include/llvm/Support/Program.h (original) >>> +++ llvm/trunk/include/llvm/Support/Program.h Wed May 11 11:31:24 2011 >>> @@ -96,9 +96,11 @@ >>> ///< expires, the child is killed and this call returns. If zero, >>> ///< this function will wait until the child finishes or forever if >>> ///< it doesn't. >>> - std::string* ErrMsg ///< If non-zero, provides a pointer to a string >>> + std::string* ErrMsg, ///< If non-zero, provides a pointer to a string >>> ///< instance in which error messages will be returned. If the string >>> ///< is non-empty upon return an error occurred while waiting. >>> + const char *SignalPrefix ///< If non-zero, provides a prefix to be >>> + ///< prepended to ErrMsg if the process is terminated abnormally. >>> ); >> >> This function is documented to return a negative value if the process is >> terminated abnormally. Shouldn't the task of producing a pretty error >> message belong to client code, rather than being built into these low-level >> support functions? > > > Ah. I knew I wouldn't get away with this for long. The docs don't cleanly specify the behavior. I needed a way in the client, many levels above to distinguish between signals and other sorts of abnormal events like timeouts and errors spawning the process. I was extremely paranoid about changing the return value and breaking other clients, which I don't know how to test and are likely outside the main source. So I went with an approach that I can prove is transparent to other clients. I'd be thrilled to drop SignalPrefix if anyone with more experience can tell me how to do it safely. Actually, it looks like Wait doesn't actually implement what its comment says. It never returns the signal number; it just returns -1 in the WIFSIGNALED case. So one solution would be to just change the documentation to match this, and then use -2 for your purposes. Dan From cdavis at mines.edu Thu May 19 12:46:39 2011 From: cdavis at mines.edu (Charles Davis) Date: Thu, 19 May 2011 17:46:39 -0000 Subject: [llvm-commits] [llvm] r131652 - in /llvm/trunk: include/llvm/MC/MCStreamer.h include/llvm/MC/MCWin64EH.h lib/MC/MCAsmStreamer.cpp lib/MC/MCStreamer.cpp Message-ID: <20110519174639.741202A6C12C@llvm.org> Author: cdavis Date: Thu May 19 12:46:39 2011 New Revision: 131652 URL: http://llvm.org/viewvc/llvm-project?rev=131652&view=rev Log: Turns out GAS does have Win64 EH directives. (It also supports WinCE EH.) Make ours compatible with GAS. In retrospect, I should have emailed binutils about this earlier. Thanks to Kai Tietz for pointing out that GAS already had SEH directives. Modified: llvm/trunk/include/llvm/MC/MCStreamer.h llvm/trunk/include/llvm/MC/MCWin64EH.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCStreamer.cpp Modified: llvm/trunk/include/llvm/MC/MCStreamer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCStreamer.h?rev=131652&r1=131651&r2=131652&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCStreamer.h (original) +++ llvm/trunk/include/llvm/MC/MCStreamer.h Thu May 19 12:46:39 2011 @@ -463,16 +463,18 @@ virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset); virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment); - virtual void EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler = 0); + virtual void EmitWin64EHStartProc(MCSymbol *Symbol); virtual void EmitWin64EHEndProc(); virtual void EmitWin64EHStartChained(); virtual void EmitWin64EHEndChained(); - virtual void EmitWin64EHUnwindOnly(); - virtual void EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size); + virtual void EmitWin64EHHandler(const MCSymbol *Sym, bool Unwind, + bool Except); + virtual void EmitWin64EHHandlerData(); virtual void EmitWin64EHPushReg(int64_t Register); virtual void EmitWin64EHSetFrame(int64_t Register, int64_t Offset); virtual void EmitWin64EHAllocStack(int64_t Size); virtual void EmitWin64EHSaveReg(int64_t Register, int64_t Offset); + virtual void EmitWin64EHSaveXMM(int64_t Register, int64_t Offset); virtual void EmitWin64EHPushFrame(bool Code); virtual void EmitWin64EHEndProlog(); Modified: llvm/trunk/include/llvm/MC/MCWin64EH.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCWin64EH.h?rev=131652&r1=131651&r2=131652&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCWin64EH.h (original) +++ llvm/trunk/include/llvm/MC/MCWin64EH.h Thu May 19 12:46:39 2011 @@ -62,17 +62,15 @@ }; struct MCWin64EHUnwindInfo { - MCWin64EHUnwindInfo() : Begin(0), End(0), ExceptionHandler(0), Lsda(0), - Function(0), UnwindOnly(false), LsdaSize(0), + MCWin64EHUnwindInfo() : Begin(0), End(0), ExceptionHandler(0), + Function(0), UnwindOnly(false), PrologSize(0), LastFrameInst(-1), ChainedParent(0), Instructions() {} MCSymbol *Begin; MCSymbol *End; const MCSymbol *ExceptionHandler; - const MCSymbol *Lsda; const MCSymbol *Function; bool UnwindOnly; - unsigned LsdaSize; unsigned PrologSize; int LastFrameInst; MCWin64EHUnwindInfo *ChainedParent; Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=131652&r1=131651&r2=131652&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Thu May 19 12:46:39 2011 @@ -208,16 +208,18 @@ virtual void EmitCFIRelOffset(int64_t Register, int64_t Offset); virtual void EmitCFIAdjustCfaOffset(int64_t Adjustment); - virtual void EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler = 0); + virtual void EmitWin64EHStartProc(MCSymbol *Symbol); virtual void EmitWin64EHEndProc(); virtual void EmitWin64EHStartChained(); virtual void EmitWin64EHEndChained(); - virtual void EmitWin64EHUnwindOnly(); - virtual void EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size); + virtual void EmitWin64EHHandler(const MCSymbol *Sym, bool Unwind, + bool Except); + virtual void EmitWin64EHHandlerData(); virtual void EmitWin64EHPushReg(int64_t Register); virtual void EmitWin64EHSetFrame(int64_t Register, int64_t Offset); virtual void EmitWin64EHAllocStack(int64_t Size); virtual void EmitWin64EHSaveReg(int64_t Register, int64_t Offset); + virtual void EmitWin64EHSaveXMM(int64_t Register, int64_t Offset); virtual void EmitWin64EHPushFrame(bool Code); virtual void EmitWin64EHEndProlog(); @@ -928,67 +930,75 @@ EmitEOL(); } -void MCAsmStreamer::EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler) { - OS << ".w64_startproc " << *Symbol; - if (EHandler) - OS << ", " << *EHandler; +void MCAsmStreamer::EmitWin64EHStartProc(MCSymbol *Symbol) { + OS << ".seh_proc " << *Symbol; EmitEOL(); } void MCAsmStreamer::EmitWin64EHEndProc() { - OS << "\t.w64_endproc"; + OS << "\t.seh_endproc"; EmitEOL(); } void MCAsmStreamer::EmitWin64EHStartChained() { - OS << "\t.w64_startchained"; + OS << "\t.seh_startchained"; EmitEOL(); } void MCAsmStreamer::EmitWin64EHEndChained() { - OS << "\t.w64_endchained"; + OS << "\t.seh_endchained"; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHUnwindOnly() { - OS << "\t.w64_unwind_only"; +void MCAsmStreamer::EmitWin64EHHandler(const MCSymbol *Sym, bool Unwind, + bool Except) { + OS << "\t.seh_handler " << *Sym; + if (Unwind) + OS << ", @unwind"; + if (Except) + OS << ", @except"; EmitEOL(); } -void MCAsmStreamer::EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size) { - OS << "\t.w64_lsda " << *Sym << ", " << Size; +void MCAsmStreamer::EmitWin64EHHandlerData() { + OS << "\t.seh_handlerdata"; EmitEOL(); } void MCAsmStreamer::EmitWin64EHPushReg(int64_t Register) { - OS << "\t.w64_pushreg " << Register; + OS << "\t.seh_pushreg " << Register; EmitEOL(); } void MCAsmStreamer::EmitWin64EHSetFrame(int64_t Register, int64_t Offset) { - OS << "\t.w64_setframe " << Register << ", " << Offset; + OS << "\t.seh_setframe " << Register << ", " << Offset; EmitEOL(); } void MCAsmStreamer::EmitWin64EHAllocStack(int64_t Size) { - OS << "\t.w64_allocstack " << Size; + OS << "\t.seh_stackalloc " << Size; EmitEOL(); } void MCAsmStreamer::EmitWin64EHSaveReg(int64_t Register, int64_t Offset) { - OS << "\t.w64_savereg " << Register << ", " << Offset; + OS << "\t.seh_savereg " << Register << ", " << Offset; + EmitEOL(); +} + +void MCAsmStreamer::EmitWin64EHSaveXMM(int64_t Register, int64_t Offset) { + OS << "\t.seh_savexmm " << Register << ", " << Offset; EmitEOL(); } void MCAsmStreamer::EmitWin64EHPushFrame(bool Code) { - OS << "\t.w64_pushframe"; + OS << "\t.seh_pushframe"; if (Code) - OS << " " << "code"; + OS << " @code"; EmitEOL(); } void MCAsmStreamer::EmitWin64EHEndProlog(void) { - OS << "\t.w64_endprolog"; + OS << "\t.seh_endprologue"; EmitEOL(); } Modified: llvm/trunk/lib/MC/MCStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCStreamer.cpp?rev=131652&r1=131651&r2=131652&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCStreamer.cpp Thu May 19 12:46:39 2011 @@ -321,14 +321,13 @@ report_fatal_error("No open Win64 EH frame function!"); } -void MCStreamer::EmitWin64EHStartProc(MCSymbol *Symbol, MCSymbol *EHandler) { +void MCStreamer::EmitWin64EHStartProc(MCSymbol *Symbol) { MCWin64EHUnwindInfo *CurFrame = CurrentW64UnwindInfo; if (CurFrame && !CurFrame->End) report_fatal_error("Starting a function before ending the previous one!"); MCWin64EHUnwindInfo Frame; Frame.Begin = getContext().CreateTempSymbol(); Frame.Function = Symbol; - Frame.ExceptionHandler = EHandler; EmitLabel(Frame.Begin); setCurrentW64UnwindInfo(&Frame); } @@ -342,8 +341,7 @@ EmitLabel(CurFrame->End); } -void MCStreamer::EmitWin64EHStartChained() -{ +void MCStreamer::EmitWin64EHStartChained() { EnsureValidW64UnwindInfo(); MCWin64EHUnwindInfo Frame; MCWin64EHUnwindInfo *CurFrame = CurrentW64UnwindInfo; @@ -354,8 +352,7 @@ setCurrentW64UnwindInfo(&Frame); } -void MCStreamer::EmitWin64EHEndChained() -{ +void MCStreamer::EmitWin64EHEndChained() { EnsureValidW64UnwindInfo(); MCWin64EHUnwindInfo *CurFrame = CurrentW64UnwindInfo; if (!CurFrame->ChainedParent) @@ -365,50 +362,53 @@ CurrentW64UnwindInfo = CurFrame->ChainedParent; } -void MCStreamer::EmitWin64EHUnwindOnly() -{ +void MCStreamer::EmitWin64EHHandler(const MCSymbol *Sym, bool Unwind, + bool Except) { + EnsureValidW64UnwindInfo(); + MCWin64EHUnwindInfo *CurFrame = CurrentW64UnwindInfo; + CurFrame->ExceptionHandler = Sym; + if (Unwind) + CurFrame->UnwindOnly = true; + else if (!Except) + report_fatal_error("Don't know what kind of handler this is!"); +} + +void MCStreamer::EmitWin64EHHandlerData() { errs() << "Not implemented yet\n"; abort(); } -void MCStreamer::EmitWin64EHLsda(const MCSymbol *Sym, int64_t Size) -{ +void MCStreamer::EmitWin64EHPushReg(int64_t Register) { errs() << "Not implemented yet\n"; abort(); } -void MCStreamer::EmitWin64EHPushReg(int64_t Register) -{ +void MCStreamer::EmitWin64EHSetFrame(int64_t Register, int64_t Offset) { errs() << "Not implemented yet\n"; abort(); } -void MCStreamer::EmitWin64EHSetFrame(int64_t Register, int64_t Offset) -{ +void MCStreamer::EmitWin64EHAllocStack(int64_t Size) { errs() << "Not implemented yet\n"; abort(); } -void MCStreamer::EmitWin64EHAllocStack(int64_t Size) -{ +void MCStreamer::EmitWin64EHSaveReg(int64_t Register, int64_t Offset) { errs() << "Not implemented yet\n"; abort(); } -void MCStreamer::EmitWin64EHSaveReg(int64_t Register, int64_t Offset) -{ +void MCStreamer::EmitWin64EHSaveXMM(int64_t Register, int64_t Offset) { errs() << "Not implemented yet\n"; abort(); } -void MCStreamer::EmitWin64EHPushFrame(bool Code) -{ +void MCStreamer::EmitWin64EHPushFrame(bool Code) { errs() << "Not implemented yet\n"; abort(); } -void MCStreamer::EmitWin64EHEndProlog() -{ +void MCStreamer::EmitWin64EHEndProlog() { errs() << "Not implemented yet\n"; abort(); } From eli.friedman at gmail.com Thu May 19 12:48:09 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 19 May 2011 17:48:09 -0000 Subject: [llvm-commits] [llvm] r131653 - in /llvm/trunk/lib/MC/MCParser: AsmParser.cpp DarwinAsmParser.cpp Message-ID: <20110519174809.75A2A2A6C12C@llvm.org> Author: efriedma Date: Thu May 19 12:48:09 2011 New Revision: 131653 URL: http://llvm.org/viewvc/llvm-project?rev=131653&view=rev Log: Revert r131644; it's breaking the build. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=131653&r1=131652&r2=131653&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu May 19 12:48:09 2011 @@ -27,7 +27,6 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCDwarf.h" -#include "llvm/Support/CommandLine.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" @@ -37,10 +36,6 @@ #include using namespace llvm; -static cl::opt -FatalAssemblerWarnings("fatal-assembler-warnings", - cl::desc("Consider warnings as error")); - namespace { /// \brief Helper class for tracking macro definitions. @@ -133,7 +128,7 @@ virtual MCContext &getContext() { return Ctx; } virtual MCStreamer &getStreamer() { return Out; } - virtual bool Warning(SMLoc L, const Twine &Meg); + virtual void Warning(SMLoc L, const Twine &Meg); virtual bool Error(SMLoc L, const Twine &Msg); const AsmToken &Lex(); @@ -375,12 +370,9 @@ "note"); } -bool AsmParser::Warning(SMLoc L, const Twine &Msg) { - if (FatalAssemblerWarnings) - return Error(L, Msg); +void AsmParser::Warning(SMLoc L, const Twine &Msg) { PrintMessage(L, Msg, "warning"); PrintMacroInstantiations(); - return false; } bool AsmParser::Error(SMLoc L, const Twine &Msg) { @@ -1137,9 +1129,9 @@ if (!getTargetParser().ParseDirective(ID)) return false; - bool retval = Warning(IDLoc, "ignoring directive for now"); + Warning(IDLoc, "ignoring directive for now"); EatToEndOfStatement(); - return retval; + return false; } CheckForValidSection(); Modified: llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp?rev=131653&r1=131652&r2=131653&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp Thu May 19 12:48:09 2011 @@ -369,9 +369,11 @@ // FIXME: If/when .dump and .load are implemented they will be done in the // the assembly parser and not have any need for an MCStreamer API. if (IsDump) - return Warning(IDLoc, "ignoring directive .dump for now"); + Warning(IDLoc, "ignoring directive .dump for now"); else - return Warning(IDLoc, "ignoring directive .load for now"); + Warning(IDLoc, "ignoring directive .load for now"); + + return false; } /// ParseDirectiveLsym From eli.friedman at gmail.com Thu May 19 12:54:02 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 19 May 2011 10:54:02 -0700 Subject: [llvm-commits] [llvm] r131644 - in /llvm/trunk/lib/MC/MCParser: AsmParser.cpp DarwinAsmParser.cpp In-Reply-To: <20110519172701.A5B2B2A6C12C@llvm.org> References: <20110519172701.A5B2B2A6C12C@llvm.org> Message-ID: On Thu, May 19, 2011 at 10:27 AM, Joerg Sonnenberger wrote: > Author: joerg > Date: Thu May 19 12:27:01 2011 > New Revision: 131644 > > URL: http://llvm.org/viewvc/llvm-project?rev=131644&view=rev > Log: > Introduce -fatal-assembler-warnings for the obvious purpose > > Modified: > ? ?llvm/trunk/lib/MC/MCParser/AsmParser.cpp > ? ?llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp Reverted in r131653; this commit was breaking the build. Maybe you missed a file? -Eli From stuart at apple.com Thu May 19 12:54:42 2011 From: stuart at apple.com (Stuart Hastings) Date: Thu, 19 May 2011 17:54:42 -0000 Subject: [llvm-commits] [llvm] r131654 - in /llvm/trunk/lib/Target/X86: X86InstrCompiler.td X86InstrExtension.td X86MCInstLower.cpp Message-ID: <20110519175442.E4C272A6C12C@llvm.org> Author: stuart Date: Thu May 19 12:54:42 2011 New Revision: 131654 URL: http://llvm.org/viewvc/llvm-project?rev=131654&view=rev Log: Reverting 131641 to investigate 'bot complaint. Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td llvm/trunk/lib/Target/X86/X86InstrExtension.td llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Modified: llvm/trunk/lib/Target/X86/X86InstrCompiler.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrCompiler.td?rev=131654&r1=131653&r2=131654&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrCompiler.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrCompiler.td Thu May 19 12:54:42 2011 @@ -997,8 +997,7 @@ // anyext. Define these to do an explicit zero-extend to // avoid partial-register updates. -def : Pat<(i16 (anyext GR8 :$src)), (EXTRACT_SUBREG - (MOVZX32rr8 GR8 :$src), sub_16bit)>; +def : Pat<(i16 (anyext GR8 :$src)), (MOVZX16rr8 GR8 :$src)>; def : Pat<(i32 (anyext GR8 :$src)), (MOVZX32rr8 GR8 :$src)>; // Except for i16 -> i32 since isel expect i16 ops to be promoted to i32. @@ -1165,9 +1164,9 @@ Requires<[In32BitMode]>; // r & (2^8-1) ==> movz def : Pat<(and GR16:$src1, 0xff), - (EXTRACT_SUBREG (MOVZX32rr8 (EXTRACT_SUBREG - (i16 (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD)), sub_8bit)), - sub_16bit)>, + (MOVZX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src1, + GR16_ABCD)), + sub_8bit))>, Requires<[In32BitMode]>; // r & (2^32-1) ==> movz @@ -1185,8 +1184,7 @@ Requires<[In64BitMode]>; // r & (2^8-1) ==> movz def : Pat<(and GR16:$src1, 0xff), - (EXTRACT_SUBREG (MOVZX32rr8 (i8 - (EXTRACT_SUBREG GR16:$src1, sub_8bit))), sub_16bit)>, + (MOVZX16rr8 (i8 (EXTRACT_SUBREG GR16:$src1, sub_8bit)))>, Requires<[In64BitMode]>; @@ -1198,11 +1196,10 @@ GR32_ABCD)), sub_8bit))>, Requires<[In32BitMode]>; - def : Pat<(sext_inreg GR16:$src, i8), - (EXTRACT_SUBREG (i32 (MOVSX32rr8 (EXTRACT_SUBREG - (i32 (COPY_TO_REGCLASS GR16:$src, GR16_ABCD)), sub_8bit))), - sub_16bit)>, + (MOVSX16rr8 (EXTRACT_SUBREG (i16 (COPY_TO_REGCLASS GR16:$src, + GR16_ABCD)), + sub_8bit))>, Requires<[In32BitMode]>; def : Pat<(sext_inreg GR64:$src, i32), @@ -1215,10 +1212,10 @@ (MOVSX32rr8 (EXTRACT_SUBREG GR32:$src, sub_8bit))>, Requires<[In64BitMode]>; def : Pat<(sext_inreg GR16:$src, i8), - (EXTRACT_SUBREG (MOVSX32rr8 - (EXTRACT_SUBREG GR16:$src, sub_8bit)), sub_16bit)>, + (MOVSX16rr8 (i8 (EXTRACT_SUBREG GR16:$src, sub_8bit)))>, Requires<[In64BitMode]>; + // trunc patterns def : Pat<(i16 (trunc GR32:$src)), (EXTRACT_SUBREG GR32:$src, sub_16bit)>; Modified: llvm/trunk/lib/Target/X86/X86InstrExtension.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrExtension.td?rev=131654&r1=131653&r2=131654&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrExtension.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrExtension.td Thu May 19 12:54:42 2011 @@ -45,12 +45,14 @@ "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; def MOVSX16rm8W : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; + +// FIXME: Use a pat pattern or define a syntax here. +let isCodeGenOnly=1 in { def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), - "movs{bl|x}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (sext GR8:$src))]>, TB; + "", [(set GR16:$dst, (sext GR8:$src))]>, TB; def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), - "movs{bl|x}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB; + "", [(set GR16:$dst, (sextloadi16i8 addr:$src))]>, TB; +} def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), "movs{bl|x}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (sext GR8:$src))]>, TB; @@ -71,12 +73,13 @@ "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; def MOVZX16rm8W : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src), "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize; +// FIXME: Use a pat pattern or define a syntax here. +let isCodeGenOnly=1 in { def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8 :$src), - "movz{bl|x}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (zext GR8:$src))]>, TB; + "", [(set GR16:$dst, (zext GR8:$src))]>, TB; def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem :$src), - "movz{bl|x}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB; + "", [(set GR16:$dst, (zextloadi16i8 addr:$src))]>, TB; +} def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src), "movz{bl|x}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (zext GR8:$src))]>, TB; Modified: llvm/trunk/lib/Target/X86/X86MCInstLower.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCInstLower.cpp?rev=131654&r1=131653&r2=131654&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCInstLower.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCInstLower.cpp Thu May 19 12:54:42 2011 @@ -355,6 +355,10 @@ assert(OutMI.getOperand(1+X86::AddrSegmentReg).getReg() == 0 && "LEA has segment specified!"); break; + case X86::MOVZX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rr8); break; + case X86::MOVZX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVZX32rm8); break; + case X86::MOVSX16rr8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rr8); break; + case X86::MOVSX16rm8: LowerSubReg32_Op0(OutMI, X86::MOVSX32rm8); break; case X86::MOVZX64rr32: LowerSubReg32_Op0(OutMI, X86::MOV32rr); break; case X86::MOVZX64rm32: LowerSubReg32_Op0(OutMI, X86::MOV32rm); break; case X86::MOV64ri64i32: LowerSubReg32_Op0(OutMI, X86::MOV32ri); break; From joerg at bec.de Thu May 19 13:00:14 2011 From: joerg at bec.de (Joerg Sonnenberger) Date: Thu, 19 May 2011 18:00:14 -0000 Subject: [llvm-commits] [llvm] r131655 - in /llvm/trunk: include/llvm/MC/MCParser/MCAsmParser.h include/llvm/MC/MCParser/MCAsmParserExtension.h lib/MC/MCParser/AsmParser.cpp lib/MC/MCParser/DarwinAsmParser.cpp Message-ID: <20110519180014.2D6982A6C12C@llvm.org> Author: joerg Date: Thu May 19 13:00:13 2011 New Revision: 131655 URL: http://llvm.org/viewvc/llvm-project?rev=131655&view=rev Log: Reapply 131644 including the missing header changes: Introduce -fatal-assembler-warnings for the obvious purpose Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h?rev=131655&r1=131654&r2=131655&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParser.h Thu May 19 13:00:13 2011 @@ -71,7 +71,9 @@ /// Warning - Emit a warning at the location \arg L, with the message \arg /// Msg. - virtual void Warning(SMLoc L, const Twine &Msg) = 0; + /// + /// \return The return value is true, if warnings are fatal. + virtual bool Warning(SMLoc L, const Twine &Msg) = 0; /// Error - Emit an error at the location \arg L, with the message \arg /// Msg. Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h?rev=131655&r1=131654&r2=131655&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmParserExtension.h Thu May 19 13:00:13 2011 @@ -56,7 +56,7 @@ MCAsmParser &getParser() { return *Parser; } SourceMgr &getSourceManager() { return getParser().getSourceManager(); } MCStreamer &getStreamer() { return getParser().getStreamer(); } - void Warning(SMLoc L, const Twine &Msg) { + bool Warning(SMLoc L, const Twine &Msg) { return getParser().Warning(L, Msg); } bool Error(SMLoc L, const Twine &Msg) { Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=131655&r1=131654&r2=131655&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu May 19 13:00:13 2011 @@ -27,6 +27,7 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCDwarf.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" @@ -36,6 +37,10 @@ #include using namespace llvm; +static cl::opt +FatalAssemblerWarnings("fatal-assembler-warnings", + cl::desc("Consider warnings as error")); + namespace { /// \brief Helper class for tracking macro definitions. @@ -128,7 +133,7 @@ virtual MCContext &getContext() { return Ctx; } virtual MCStreamer &getStreamer() { return Out; } - virtual void Warning(SMLoc L, const Twine &Meg); + virtual bool Warning(SMLoc L, const Twine &Meg); virtual bool Error(SMLoc L, const Twine &Msg); const AsmToken &Lex(); @@ -370,9 +375,12 @@ "note"); } -void AsmParser::Warning(SMLoc L, const Twine &Msg) { +bool AsmParser::Warning(SMLoc L, const Twine &Msg) { + if (FatalAssemblerWarnings) + return Error(L, Msg); PrintMessage(L, Msg, "warning"); PrintMacroInstantiations(); + return false; } bool AsmParser::Error(SMLoc L, const Twine &Msg) { @@ -1129,9 +1137,9 @@ if (!getTargetParser().ParseDirective(ID)) return false; - Warning(IDLoc, "ignoring directive for now"); + bool retval = Warning(IDLoc, "ignoring directive for now"); EatToEndOfStatement(); - return false; + return retval; } CheckForValidSection(); Modified: llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp?rev=131655&r1=131654&r2=131655&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/DarwinAsmParser.cpp Thu May 19 13:00:13 2011 @@ -369,11 +369,9 @@ // FIXME: If/when .dump and .load are implemented they will be done in the // the assembly parser and not have any need for an MCStreamer API. if (IsDump) - Warning(IDLoc, "ignoring directive .dump for now"); + return Warning(IDLoc, "ignoring directive .dump for now"); else - Warning(IDLoc, "ignoring directive .load for now"); - - return false; + return Warning(IDLoc, "ignoring directive .load for now"); } /// ParseDirectiveLsym From daniel at zuster.org Thu May 19 13:02:55 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Thu, 19 May 2011 18:02:55 -0000 Subject: [llvm-commits] [compiler-rt] r131656 - /compiler-rt/trunk/make/platform/clang_darwin.mk Message-ID: <20110519180255.B62A62A6C12C@llvm.org> Author: ddunbar Date: Thu May 19 13:02:55 2011 New Revision: 131656 URL: http://llvm.org/viewvc/llvm-project?rev=131656&view=rev Log: clang/darwin: Tweak CheckArches function to use CC and to not spew output. Modified: compiler-rt/trunk/make/platform/clang_darwin.mk Modified: compiler-rt/trunk/make/platform/clang_darwin.mk URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/clang_darwin.mk?rev=131656&r1=131655&r2=131656&view=diff ============================================================================== --- compiler-rt/trunk/make/platform/clang_darwin.mk (original) +++ compiler-rt/trunk/make/platform/clang_darwin.mk Thu May 19 13:02:55 2011 @@ -12,8 +12,9 @@ $(shell \ result=""; \ for arch in $(1); do \ - gcc -arch $$arch; \ - if test $$? == 1; then result="$$result$$arch "; fi; \ + if $(CC) -arch $$arch -dumpversion > /dev/null; then \ + result="$$result$$arch "; \ + fi; \ done; \ echo $$result) From ahatanak at gmail.com Thu May 19 13:06:05 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 19 May 2011 18:06:05 -0000 Subject: [llvm-commits] [llvm] r131657 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110519180606.003F52A6C12C@llvm.org> Author: ahatanak Date: Thu May 19 13:06:05 2011 New Revision: 131657 URL: http://llvm.org/viewvc/llvm-project?rev=131657&view=rev Log: Simplify CC_MipsO32 and merge it with CC_MipsO32_VarArgs. Patch by Sasa Stankovic. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=131657&r1=131656&r2=131657&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Thu May 19 13:06:05 2011 @@ -937,6 +937,8 @@ // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is // not used, it must be shadowed. If only A3 is avaiable, shadow it and // go to stack. +// +// For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. //===----------------------------------------------------------------------===// static bool CC_MipsO32(unsigned ValNo, MVT ValVT, @@ -955,90 +957,6 @@ Mips::D6, Mips::D7 }; - unsigned Reg = 0; - static bool IntRegUsed = false; - - // This must be the first arg of the call if no regs have been allocated. - // Initialize IntRegUsed in that case. - if (IntRegs[State.getFirstUnallocated(IntRegs, IntRegsSize)] == Mips::A0 && - F32Regs[State.getFirstUnallocated(F32Regs, FloatRegsSize)] == Mips::F12 && - F64Regs[State.getFirstUnallocated(F64Regs, FloatRegsSize)] == Mips::D6) - IntRegUsed = false; - - // Promote i8 and i16 - if (LocVT == MVT::i8 || LocVT == MVT::i16) { - LocVT = MVT::i32; - if (ArgFlags.isSExt()) - LocInfo = CCValAssign::SExt; - else if (ArgFlags.isZExt()) - LocInfo = CCValAssign::ZExt; - else - LocInfo = CCValAssign::AExt; - } - - if (ValVT == MVT::i32) { - Reg = State.AllocateReg(IntRegs, IntRegsSize); - IntRegUsed = true; - } else if (ValVT == MVT::f32) { - // An int reg has to be marked allocated regardless of whether or not - // IntRegUsed is true. - Reg = State.AllocateReg(IntRegs, IntRegsSize); - - if (IntRegUsed) { - if (Reg) // Int reg is available - LocVT = MVT::i32; - } else { - unsigned FReg = State.AllocateReg(F32Regs, FloatRegsSize); - if (FReg) // F32 reg is available - Reg = FReg; - else if (Reg) // No F32 regs are available, but an int reg is available. - LocVT = MVT::i32; - } - } else if (ValVT == MVT::f64) { - // Int regs have to be marked allocated regardless of whether or not - // IntRegUsed is true. - Reg = State.AllocateReg(IntRegs, IntRegsSize); - if (Reg == Mips::A1) - Reg = State.AllocateReg(IntRegs, IntRegsSize); - else if (Reg == Mips::A3) - Reg = 0; - State.AllocateReg(IntRegs, IntRegsSize); - - // At this point, Reg is A0, A2 or 0, and all the unavailable integer regs - // are marked as allocated. - if (IntRegUsed) { - if (Reg)// if int reg is available - LocVT = MVT::i32; - } else { - unsigned FReg = State.AllocateReg(F64Regs, FloatRegsSize); - if (FReg) // F64 reg is available. - Reg = FReg; - else if (Reg) // No F64 regs are available, but an int reg is available. - LocVT = MVT::i32; - } - } else - assert(false && "cannot handle this ValVT"); - - if (!Reg) { - unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; - unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes); - State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); - } else - State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); - - return false; // CC must always match -} - -static bool CC_MipsO32_VarArgs(unsigned ValNo, MVT ValVT, - MVT LocVT, CCValAssign::LocInfo LocInfo, - ISD::ArgFlagsTy ArgFlags, CCState &State) { - - static const unsigned IntRegsSize=4; - - static const unsigned IntRegs[] = { - Mips::A0, Mips::A1, Mips::A2, Mips::A3 - }; - // Promote i8 and i16 if (LocVT == MVT::i8 || LocVT == MVT::i16) { LocVT = MVT::i32; @@ -1052,15 +970,37 @@ unsigned Reg; - if (ValVT == MVT::i32 || ValVT == MVT::f32) { + // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following + // is true: function is vararg, argument is 3rd or higher, there is previous + // argument which is not f32 or f64. + bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 + || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; + + if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { Reg = State.AllocateReg(IntRegs, IntRegsSize); LocVT = MVT::i32; - } else if (ValVT == MVT::f64) { + } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { + // Allocate int register and shadow next int register. If first + // available register is Mips::A1 or Mips::A3, shadow it too. Reg = State.AllocateReg(IntRegs, IntRegsSize); if (Reg == Mips::A1 || Reg == Mips::A3) Reg = State.AllocateReg(IntRegs, IntRegsSize); State.AllocateReg(IntRegs, IntRegsSize); LocVT = MVT::i32; + } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { + // we are guaranteed to find an available float register + if (ValVT == MVT::f32) { + Reg = State.AllocateReg(F32Regs, FloatRegsSize); + // Shadow int register + State.AllocateReg(IntRegs, IntRegsSize); + } else { + Reg = State.AllocateReg(F64Regs, FloatRegsSize); + // Shadow int registers + unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); + if (Reg2 == Mips::A1 || Reg2 == Mips::A3) + State.AllocateReg(IntRegs, IntRegsSize); + State.AllocateReg(IntRegs, IntRegsSize); + } } else llvm_unreachable("Cannot handle this ValVT."); @@ -1107,8 +1047,7 @@ if (Subtarget->isABI_O32()) { int VTsize = MVT(MVT::i32).getSizeInBits()/8; MFI->CreateFixedObject(VTsize, (VTsize*3), true); - CCInfo.AnalyzeCallOperands(Outs, - isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32); + CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); } else CCInfo.AnalyzeCallOperands(Outs, CC_Mips); @@ -1369,8 +1308,7 @@ ArgLocs, *DAG.getContext()); if (Subtarget->isABI_O32()) - CCInfo.AnalyzeFormalArguments(Ins, - isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32); + CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); else CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); From evan.cheng at apple.com Thu May 19 13:18:39 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 19 May 2011 18:18:39 -0000 Subject: [llvm-commits] [llvm] r131659 - /llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Message-ID: <20110519181840.028232A6C12C@llvm.org> Author: evancheng Date: Thu May 19 13:18:39 2011 New Revision: 131659 URL: http://llvm.org/viewvc/llvm-project?rev=131659&view=rev Log: Add comment. Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=131659&r1=131658&r2=131659&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Thu May 19 13:18:39 2011 @@ -597,6 +597,7 @@ case Intrinsic::x86_sse41_pmovzxbw: case Intrinsic::x86_sse41_pmovzxwd: case Intrinsic::x86_sse41_pmovzxdq: { + // pmov{s|z}x ignores the upper half of their input vectors. unsigned VWidth = cast(II->getArgOperand(0)->getType())->getNumElements(); unsigned LowHalfElts = VWidth / 2; From ahatanak at gmail.com Thu May 19 13:25:03 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 19 May 2011 18:25:03 -0000 Subject: [llvm-commits] [llvm] r131660 - in /llvm/trunk/lib/Target/Mips: MipsRegisterInfo.cpp MipsRegisterInfo.td Message-ID: <20110519182503.50A5A2A6C12C@llvm.org> Author: ahatanak Date: Thu May 19 13:25:03 2011 New Revision: 131660 URL: http://llvm.org/viewvc/llvm-project?rev=131660&view=rev Log: Increase number of available registers when target is MIPS32. Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=131660&r1=131659&r2=131660&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu May 19 13:25:03 2011 @@ -110,8 +110,16 @@ Mips::F20, Mips::F22, Mips::F24, Mips::F26, Mips::F28, Mips::F30, 0 }; + static const unsigned Mips32CalleeSavedRegs[] = { + Mips::S0, Mips::S1, Mips::S2, Mips::S3, + Mips::S4, Mips::S5, Mips::S6, Mips::S7, + Mips::D10, Mips::D11, Mips::D12, Mips::D13, Mips::D14, Mips::D15, 0 + }; + if (Subtarget.isSingleFloat()) return SingleFloatOnlyCalleeSavedRegs; + else if (Subtarget.isMips32()) + return Mips32CalleeSavedRegs; else return BitMode32CalleeSavedRegs; } @@ -129,7 +137,7 @@ Reserved.set(Mips::RA); // SRV4 requires that odd register can't be used. - if (!Subtarget.isSingleFloat()) + if (!Subtarget.isSingleFloat() && !Subtarget.isMips32()) for (unsigned FReg=(Mips::F0)+1; FReg < Mips::F30; FReg+=2) Reserved.set(FReg); Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=131660&r1=131659&r2=131660&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Thu May 19 13:25:03 2011 @@ -214,7 +214,7 @@ const TargetMachine &TM = MF.getTarget(); const MipsSubtarget &Subtarget = TM.getSubtarget(); - if (Subtarget.isSingleFloat()) + if (Subtarget.isMips32() || Subtarget.isSingleFloat()) return MIPS_FGR32; else return MIPS_SVR4_FGR32; @@ -225,7 +225,7 @@ const TargetMachine &TM = MF.getTarget(); const MipsSubtarget &Subtarget = TM.getSubtarget(); - if (Subtarget.isSingleFloat()) + if (Subtarget.isMips32() || Subtarget.isSingleFloat()) return MIPS_FGR32 + (sizeof(MIPS_FGR32) / sizeof(unsigned)); else return MIPS_SVR4_FGR32 + (sizeof(MIPS_SVR4_FGR32) / sizeof(unsigned)); From atrick at apple.com Thu May 19 13:48:07 2011 From: atrick at apple.com (Andrew Trick) Date: Thu, 19 May 2011 11:48:07 -0700 Subject: [llvm-commits] [llvm] r131186 - in /llvm/trunk: include/llvm/Support/Program.h lib/Support/Program.cpp lib/Support/Unix/Program.inc tools/bugpoint/ExecutionDriver.cpp tools/bugpoint/Miscompilation.cpp tools/bugpoint/ToolRunner.cpp In-Reply-To: References: <20110511163124.D83B82A6C12C@llvm.org> Message-ID: On May 19, 2011, at 10:50 AM, Dan Gohman wrote: > > On May 18, 2011, at 5:03 PM, Andrew Trick wrote: > >> On May 18, 2011, at 2:42 PM, Dan Gohman wrote: >> >>>> --- llvm/trunk/include/llvm/Support/Program.h (original) >>>> +++ llvm/trunk/include/llvm/Support/Program.h Wed May 11 11:31:24 2011 >>>> @@ -96,9 +96,11 @@ >>>> ///< expires, the child is killed and this call returns. If zero, >>>> ///<