From rafael.espindola at gmail.com Mon May 30 10:56:04 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 30 May 2011 15:56:04 -0000 Subject: [llvm-commits] [llvm] r132312 - /llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td Message-ID: <20110530155604.DF4AF2A6C12C@llvm.org> Author: rafael Date: Mon May 30 10:56:04 2011 New Revision: 132312 URL: http://llvm.org/viewvc/llvm-project?rev=132312&view=rev Log: Remove the DwarfNumbers from the subregisters. They should use DW_OP_bit_piece and for now the generic dwarf emission will automatically use the superregister numbers. Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td?rev=132312&r1=132311&r2=132312&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.td Mon May 30 10:56:04 2011 @@ -61,22 +61,22 @@ } // General-purpose registers -def R0W : GPR32< 0, "r0">, DwarfRegNum<[0]>; -def R1W : GPR32< 1, "r1">, DwarfRegNum<[1]>; -def R2W : GPR32< 2, "r2">, DwarfRegNum<[2]>; -def R3W : GPR32< 3, "r3">, DwarfRegNum<[3]>; -def R4W : GPR32< 4, "r4">, DwarfRegNum<[4]>; -def R5W : GPR32< 5, "r5">, DwarfRegNum<[5]>; -def R6W : GPR32< 6, "r6">, DwarfRegNum<[6]>; -def R7W : GPR32< 7, "r7">, DwarfRegNum<[7]>; -def R8W : GPR32< 8, "r8">, DwarfRegNum<[8]>; -def R9W : GPR32< 9, "r9">, DwarfRegNum<[9]>; -def R10W : GPR32<10, "r10">, DwarfRegNum<[10]>; -def R11W : GPR32<11, "r11">, DwarfRegNum<[11]>; -def R12W : GPR32<12, "r12">, DwarfRegNum<[12]>; -def R13W : GPR32<13, "r13">, DwarfRegNum<[13]>; -def R14W : GPR32<14, "r14">, DwarfRegNum<[14]>; -def R15W : GPR32<15, "r15">, DwarfRegNum<[15]>; +def R0W : GPR32< 0, "r0">; +def R1W : GPR32< 1, "r1">; +def R2W : GPR32< 2, "r2">; +def R3W : GPR32< 3, "r3">; +def R4W : GPR32< 4, "r4">; +def R5W : GPR32< 5, "r5">; +def R6W : GPR32< 6, "r6">; +def R7W : GPR32< 7, "r7">; +def R8W : GPR32< 8, "r8">; +def R9W : GPR32< 9, "r9">; +def R10W : GPR32<10, "r10">; +def R11W : GPR32<11, "r11">; +def R12W : GPR32<12, "r12">; +def R13W : GPR32<13, "r13">; +def R14W : GPR32<14, "r14">; +def R15W : GPR32<15, "r15">; let SubRegIndices = [subreg_32bit] in { def R0D : GPR64< 0, "r0", [R0W]>, DwarfRegNum<[0]>; @@ -99,26 +99,26 @@ // Register pairs let SubRegIndices = [subreg_32bit, subreg_odd32] in { -def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>, DwarfRegNum<[0]>; -def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>, DwarfRegNum<[2]>; -def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>, DwarfRegNum<[4]>; -def R6P : GPR64< 6, "r6", [R6W, R7W], [R6D, R7D]>, DwarfRegNum<[6]>; -def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>, DwarfRegNum<[8]>; -def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>, DwarfRegNum<[10]>; -def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>, DwarfRegNum<[12]>; -def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>, DwarfRegNum<[14]>; +def R0P : GPR64< 0, "r0", [R0W, R1W], [R0D, R1D]>; +def R2P : GPR64< 2, "r2", [R2W, R3W], [R2D, R3D]>; +def R4P : GPR64< 4, "r4", [R4W, R5W], [R4D, R5D]>; +def R6P : GPR64< 6, "r6", [R6W, R7W], [R6D, R7D]>; +def R8P : GPR64< 8, "r8", [R8W, R9W], [R8D, R9D]>; +def R10P : GPR64<10, "r10", [R10W, R11W], [R10D, R11D]>; +def R12P : GPR64<12, "r12", [R12W, R13W], [R12D, R13D]>; +def R14P : GPR64<14, "r14", [R14W, R15W], [R14D, R15D]>; } let SubRegIndices = [subreg_even, subreg_odd], CompositeIndices = [(subreg_odd32 subreg_odd, subreg_32bit)] in { -def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>, DwarfRegNum<[0]>; -def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>, DwarfRegNum<[2]>; -def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>, DwarfRegNum<[4]>; -def R6Q : GPR128< 6, "r6", [R6D, R7D], [R6P]>, DwarfRegNum<[6]>; -def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>, DwarfRegNum<[8]>; -def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>, DwarfRegNum<[10]>; -def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>, DwarfRegNum<[12]>; -def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>, DwarfRegNum<[14]>; +def R0Q : GPR128< 0, "r0", [R0D, R1D], [R0P]>; +def R2Q : GPR128< 2, "r2", [R2D, R3D], [R2P]>; +def R4Q : GPR128< 4, "r4", [R4D, R5D], [R4P]>; +def R6Q : GPR128< 6, "r6", [R6D, R7D], [R6P]>; +def R8Q : GPR128< 8, "r8", [R8D, R9D], [R8P]>; +def R10Q : GPR128<10, "r10", [R10D, R11D], [R10P]>; +def R12Q : GPR128<12, "r12", [R12D, R13D], [R12P]>; +def R14Q : GPR128<14, "r14", [R14D, R15D], [R14P]>; } // Floating-point registers @@ -140,22 +140,22 @@ def F15S : FPRS<15, "f15">, DwarfRegNum<[31]>; let SubRegIndices = [subreg_32bit] in { -def F0L : FPRL< 0, "f0", [F0S]>, DwarfRegNum<[16]>; -def F1L : FPRL< 1, "f1", [F1S]>, DwarfRegNum<[17]>; -def F2L : FPRL< 2, "f2", [F2S]>, DwarfRegNum<[18]>; -def F3L : FPRL< 3, "f3", [F3S]>, DwarfRegNum<[19]>; -def F4L : FPRL< 4, "f4", [F4S]>, DwarfRegNum<[20]>; -def F5L : FPRL< 5, "f5", [F5S]>, DwarfRegNum<[21]>; -def F6L : FPRL< 6, "f6", [F6S]>, DwarfRegNum<[22]>; -def F7L : FPRL< 7, "f7", [F7S]>, DwarfRegNum<[23]>; -def F8L : FPRL< 8, "f8", [F8S]>, DwarfRegNum<[24]>; -def F9L : FPRL< 9, "f9", [F9S]>, DwarfRegNum<[25]>; -def F10L : FPRL<10, "f10", [F10S]>, DwarfRegNum<[26]>; -def F11L : FPRL<11, "f11", [F11S]>, DwarfRegNum<[27]>; -def F12L : FPRL<12, "f12", [F12S]>, DwarfRegNum<[28]>; -def F13L : FPRL<13, "f13", [F13S]>, DwarfRegNum<[29]>; -def F14L : FPRL<14, "f14", [F14S]>, DwarfRegNum<[30]>; -def F15L : FPRL<15, "f15", [F15S]>, DwarfRegNum<[31]>; +def F0L : FPRL< 0, "f0", [F0S]>; +def F1L : FPRL< 1, "f1", [F1S]>; +def F2L : FPRL< 2, "f2", [F2S]>; +def F3L : FPRL< 3, "f3", [F3S]>; +def F4L : FPRL< 4, "f4", [F4S]>; +def F5L : FPRL< 5, "f5", [F5S]>; +def F6L : FPRL< 6, "f6", [F6S]>; +def F7L : FPRL< 7, "f7", [F7S]>; +def F8L : FPRL< 8, "f8", [F8S]>; +def F9L : FPRL< 9, "f9", [F9S]>; +def F10L : FPRL<10, "f10", [F10S]>; +def F11L : FPRL<11, "f11", [F11S]>; +def F12L : FPRL<12, "f12", [F12S]>; +def F13L : FPRL<13, "f13", [F13S]>; +def F14L : FPRL<14, "f14", [F14S]>; +def F15L : FPRL<15, "f15", [F15S]>; } // Status register From rafael.espindola at gmail.com Mon May 30 11:04:55 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 30 May 2011 16:04:55 -0000 Subject: [llvm-commits] [llvm] r132313 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.td Message-ID: <20110530160455.12C5F2A6C12C@llvm.org> Author: rafael Date: Mon May 30 11:04:54 2011 New Revision: 132313 URL: http://llvm.org/viewvc/llvm-project?rev=132313&view=rev Log: Mark the 32 bit registers as invalid in 64 bit mode. In 64 bit mode they are subregisters of the 64 bit ones. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=132313&r1=132312&r2=132313&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Mon May 30 11:04:54 2011 @@ -97,15 +97,15 @@ } // 32-bit registers let SubRegIndices = [sub_16bit] in { - def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[0, 0, 0]>; - def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[1, 2, 2]>; - def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[2, 1, 1]>; - def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[3, 3, 3]>; - def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[4, 6, 6]>; - def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[5, 7, 7]>; - def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[6, 4, 5]>; - def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[7, 5, 4]>; - def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[16, 8, 8]>; + def EAX : RegisterWithSubRegs<"eax", [AX]>, DwarfRegNum<[-2, 0, 0]>; + def EDX : RegisterWithSubRegs<"edx", [DX]>, DwarfRegNum<[-2, 2, 2]>; + def ECX : RegisterWithSubRegs<"ecx", [CX]>, DwarfRegNum<[-2, 1, 1]>; + def EBX : RegisterWithSubRegs<"ebx", [BX]>, DwarfRegNum<[-2, 3, 3]>; + def ESI : RegisterWithSubRegs<"esi", [SI]>, DwarfRegNum<[-2, 6, 6]>; + def EDI : RegisterWithSubRegs<"edi", [DI]>, DwarfRegNum<[-2, 7, 7]>; + def EBP : RegisterWithSubRegs<"ebp", [BP]>, DwarfRegNum<[-2, 4, 5]>; + def ESP : RegisterWithSubRegs<"esp", [SP]>, DwarfRegNum<[-2, 5, 4]>; + def EIP : RegisterWithSubRegs<"eip", [IP]>, DwarfRegNum<[-2, 8, 8]>; // X86-64 only, requires REX let CostPerUse = 1 in { From bob.wilson at apple.com Mon May 30 11:38:49 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Mon, 30 May 2011 09:38:49 -0700 Subject: [llvm-commits] BlockWeight Analysis In-Reply-To: References: <3CF62A18-0618-4187-9C47-34C3DDA80110@apple.com> Message-ID: <3A242364-6CE4-4812-988B-6EBA99BE30D6@apple.com> On May 27, 2011, at 7:33 PM, Andrew Trick wrote: > On May 26, 2011, at 7:04 PM, Jakub Staszak wrote: > >> Hello, >> >> This patch introduces BlockWeight Analysis. This is the first from the series of patches which will improve general profiling info. >> >> Thanks! >> -- >> Jakub Staszak > > Hi Jakub, > > I don't have any objection to committing experimental code, but it would be premature to review the code in this form. We need to work on communicating the high level design and clarifying some terminology first. This still has the 8 bit values for edge weights. I thought we were going to increase that to at least 32 bits. ? From rafael.espindola at gmail.com Mon May 30 12:49:59 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 30 May 2011 17:49:59 -0000 Subject: [llvm-commits] [llvm] r132314 - in /llvm/trunk: include/llvm/Target/Target.td lib/Target/X86/X86RegisterInfo.td utils/TableGen/RegisterInfoEmitter.cpp Message-ID: <20110530174959.405602A6C12C@llvm.org> Author: rafael Date: Mon May 30 12:49:59 2011 New Revision: 132314 URL: http://llvm.org/viewvc/llvm-project?rev=132314&view=rev Log: Introduce the DwarfRegAlias class for declaring that two registers have the same dwarf number. This will be used for creating a dwarf number to register mapping. The only case that needs this so far is the XMM/YMM registers that unfortunately do have the same numbers. Modified: llvm/trunk/include/llvm/Target/Target.td llvm/trunk/lib/Target/X86/X86RegisterInfo.td llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=132314&r1=132313&r2=132314&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Mon May 30 12:49:59 2011 @@ -151,6 +151,14 @@ list DwarfNumbers = Numbers; } +// DwarfRegAlias - This class declares that a given register uses the same dwarf +// numbers as another one. This is useful for making it clear that the two +// registers do have the same number. It also lets us build a mapping +// from dwarf register number to llvm register. +class DwarfRegAlias { + Register DwarfAlias = reg; +} + //===----------------------------------------------------------------------===// // Pull in the common support for scheduling // Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=132314&r1=132313&r2=132314&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Mon May 30 12:49:59 2011 @@ -188,22 +188,22 @@ // YMM Registers, used by AVX instructions let SubRegIndices = [sub_xmm] in { - def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegNum<[17, 21, 21]>; - def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegNum<[18, 22, 22]>; - def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegNum<[19, 23, 23]>; - def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegNum<[20, 24, 24]>; - def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegNum<[21, 25, 25]>; - def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegNum<[22, 26, 26]>; - def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegNum<[23, 27, 27]>; - def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegNum<[24, 28, 28]>; - def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegNum<[25, -2, -2]>; - def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegNum<[26, -2, -2]>; - def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegNum<[27, -2, -2]>; - def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegNum<[28, -2, -2]>; - def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegNum<[29, -2, -2]>; - def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegNum<[30, -2, -2]>; - def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegNum<[31, -2, -2]>; - def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegNum<[32, -2, -2]>; + def YMM0: RegisterWithSubRegs<"ymm0", [XMM0]>, DwarfRegAlias; + def YMM1: RegisterWithSubRegs<"ymm1", [XMM1]>, DwarfRegAlias; + def YMM2: RegisterWithSubRegs<"ymm2", [XMM2]>, DwarfRegAlias; + def YMM3: RegisterWithSubRegs<"ymm3", [XMM3]>, DwarfRegAlias; + def YMM4: RegisterWithSubRegs<"ymm4", [XMM4]>, DwarfRegAlias; + def YMM5: RegisterWithSubRegs<"ymm5", [XMM5]>, DwarfRegAlias; + def YMM6: RegisterWithSubRegs<"ymm6", [XMM6]>, DwarfRegAlias; + def YMM7: RegisterWithSubRegs<"ymm7", [XMM7]>, DwarfRegAlias; + def YMM8: RegisterWithSubRegs<"ymm8", [XMM8]>, DwarfRegAlias; + def YMM9: RegisterWithSubRegs<"ymm9", [XMM9]>, DwarfRegAlias; + def YMM10: RegisterWithSubRegs<"ymm10", [XMM10]>, DwarfRegAlias; + def YMM11: RegisterWithSubRegs<"ymm11", [XMM11]>, DwarfRegAlias; + def YMM12: RegisterWithSubRegs<"ymm12", [XMM12]>, DwarfRegAlias; + def YMM13: RegisterWithSubRegs<"ymm13", [XMM13]>, DwarfRegAlias; + def YMM14: RegisterWithSubRegs<"ymm14", [XMM14]>, DwarfRegAlias; + def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegAlias; } // Floating point stack registers Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=132314&r1=132313&r2=132314&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Mon May 30 12:49:59 2011 @@ -989,6 +989,17 @@ for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) I->second.push_back(-1); + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + Record *Reg = Regs[i].TheDef; + const RecordVal *V = Reg->getValue("DwarfAlias"); + if (!V || !V->getValue()) + continue; + + DefInit *DI = dynamic_cast(V->getValue()); + Record *Alias = DI->getDef(); + DwarfRegNums[Reg] = DwarfRegNums[Alias]; + } + // Emit information about the dwarf register numbers. OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, " << "unsigned Flavour) const {\n" From rafael.espindola at gmail.com Mon May 30 13:24:44 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 30 May 2011 18:24:44 -0000 Subject: [llvm-commits] [llvm] r132315 - in /llvm/trunk/lib/Target/PowerPC: PPCRegisterInfo.cpp PPCRegisterInfo.td Message-ID: <20110530182444.DAF712A6C12C@llvm.org> Author: rafael Date: Mon May 30 13:24:44 2011 New Revision: 132315 URL: http://llvm.org/viewvc/llvm-project?rev=132315&view=rev Log: Split ppc dwarf regnums into ppc64 and ppc32 flavours. Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=132315&r1=132314&r2=132315&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon May 30 13:24:44 2011 @@ -686,9 +686,20 @@ return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4; } +/// DWARFFlavour - Flavour of dwarf regnumbers +/// +namespace DWARFFlavour { + enum { + PPC64 = 0, PPC32 = 1 + }; +} + int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { // FIXME: Most probably dwarf numbers differs for Linux and Darwin - return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); + unsigned Flavour = Subtarget.isPPC64() ? + DWARFFlavour::PPC64 : DWARFFlavour::PPC32; + + return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour); } #include "PPCGenRegisterInfo.inc" Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td?rev=132315&r1=132314&r2=132315&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.td Mon May 30 13:24:44 2011 @@ -65,140 +65,140 @@ // General-purpose registers -def R0 : GPR< 0, "r0">, DwarfRegNum<[0]>; -def R1 : GPR< 1, "r1">, DwarfRegNum<[1]>; -def R2 : GPR< 2, "r2">, DwarfRegNum<[2]>; -def R3 : GPR< 3, "r3">, DwarfRegNum<[3]>; -def R4 : GPR< 4, "r4">, DwarfRegNum<[4]>; -def R5 : GPR< 5, "r5">, DwarfRegNum<[5]>; -def R6 : GPR< 6, "r6">, DwarfRegNum<[6]>; -def R7 : GPR< 7, "r7">, DwarfRegNum<[7]>; -def R8 : GPR< 8, "r8">, DwarfRegNum<[8]>; -def R9 : GPR< 9, "r9">, DwarfRegNum<[9]>; -def R10 : GPR<10, "r10">, DwarfRegNum<[10]>; -def R11 : GPR<11, "r11">, DwarfRegNum<[11]>; -def R12 : GPR<12, "r12">, DwarfRegNum<[12]>; -def R13 : GPR<13, "r13">, DwarfRegNum<[13]>; -def R14 : GPR<14, "r14">, DwarfRegNum<[14]>; -def R15 : GPR<15, "r15">, DwarfRegNum<[15]>; -def R16 : GPR<16, "r16">, DwarfRegNum<[16]>; -def R17 : GPR<17, "r17">, DwarfRegNum<[17]>; -def R18 : GPR<18, "r18">, DwarfRegNum<[18]>; -def R19 : GPR<19, "r19">, DwarfRegNum<[19]>; -def R20 : GPR<20, "r20">, DwarfRegNum<[20]>; -def R21 : GPR<21, "r21">, DwarfRegNum<[21]>; -def R22 : GPR<22, "r22">, DwarfRegNum<[22]>; -def R23 : GPR<23, "r23">, DwarfRegNum<[23]>; -def R24 : GPR<24, "r24">, DwarfRegNum<[24]>; -def R25 : GPR<25, "r25">, DwarfRegNum<[25]>; -def R26 : GPR<26, "r26">, DwarfRegNum<[26]>; -def R27 : GPR<27, "r27">, DwarfRegNum<[27]>; -def R28 : GPR<28, "r28">, DwarfRegNum<[28]>; -def R29 : GPR<29, "r29">, DwarfRegNum<[29]>; -def R30 : GPR<30, "r30">, DwarfRegNum<[30]>; -def R31 : GPR<31, "r31">, DwarfRegNum<[31]>; +def R0 : GPR< 0, "r0">, DwarfRegNum<[-2, 0]>; +def R1 : GPR< 1, "r1">, DwarfRegNum<[-2, 1]>; +def R2 : GPR< 2, "r2">, DwarfRegNum<[-2, 2]>; +def R3 : GPR< 3, "r3">, DwarfRegNum<[-2, 3]>; +def R4 : GPR< 4, "r4">, DwarfRegNum<[-2, 4]>; +def R5 : GPR< 5, "r5">, DwarfRegNum<[-2, 5]>; +def R6 : GPR< 6, "r6">, DwarfRegNum<[-2, 6]>; +def R7 : GPR< 7, "r7">, DwarfRegNum<[-2, 7]>; +def R8 : GPR< 8, "r8">, DwarfRegNum<[-2, 8]>; +def R9 : GPR< 9, "r9">, DwarfRegNum<[-2, 9]>; +def R10 : GPR<10, "r10">, DwarfRegNum<[-2, 10]>; +def R11 : GPR<11, "r11">, DwarfRegNum<[-2, 11]>; +def R12 : GPR<12, "r12">, DwarfRegNum<[-2, 12]>; +def R13 : GPR<13, "r13">, DwarfRegNum<[-2, 13]>; +def R14 : GPR<14, "r14">, DwarfRegNum<[-2, 14]>; +def R15 : GPR<15, "r15">, DwarfRegNum<[-2, 15]>; +def R16 : GPR<16, "r16">, DwarfRegNum<[-2, 16]>; +def R17 : GPR<17, "r17">, DwarfRegNum<[-2, 17]>; +def R18 : GPR<18, "r18">, DwarfRegNum<[-2, 18]>; +def R19 : GPR<19, "r19">, DwarfRegNum<[-2, 19]>; +def R20 : GPR<20, "r20">, DwarfRegNum<[-2, 20]>; +def R21 : GPR<21, "r21">, DwarfRegNum<[-2, 21]>; +def R22 : GPR<22, "r22">, DwarfRegNum<[-2, 22]>; +def R23 : GPR<23, "r23">, DwarfRegNum<[-2, 23]>; +def R24 : GPR<24, "r24">, DwarfRegNum<[-2, 24]>; +def R25 : GPR<25, "r25">, DwarfRegNum<[-2, 25]>; +def R26 : GPR<26, "r26">, DwarfRegNum<[-2, 26]>; +def R27 : GPR<27, "r27">, DwarfRegNum<[-2, 27]>; +def R28 : GPR<28, "r28">, DwarfRegNum<[-2, 28]>; +def R29 : GPR<29, "r29">, DwarfRegNum<[-2, 29]>; +def R30 : GPR<30, "r30">, DwarfRegNum<[-2, 30]>; +def R31 : GPR<31, "r31">, DwarfRegNum<[-2, 31]>; // 64-bit General-purpose registers -def X0 : GP8< R0, "r0">, DwarfRegNum<[0]>; -def X1 : GP8< R1, "r1">, DwarfRegNum<[1]>; -def X2 : GP8< R2, "r2">, DwarfRegNum<[2]>; -def X3 : GP8< R3, "r3">, DwarfRegNum<[3]>; -def X4 : GP8< R4, "r4">, DwarfRegNum<[4]>; -def X5 : GP8< R5, "r5">, DwarfRegNum<[5]>; -def X6 : GP8< R6, "r6">, DwarfRegNum<[6]>; -def X7 : GP8< R7, "r7">, DwarfRegNum<[7]>; -def X8 : GP8< R8, "r8">, DwarfRegNum<[8]>; -def X9 : GP8< R9, "r9">, DwarfRegNum<[9]>; -def X10 : GP8, DwarfRegNum<[10]>; -def X11 : GP8, DwarfRegNum<[11]>; -def X12 : GP8, DwarfRegNum<[12]>; -def X13 : GP8, DwarfRegNum<[13]>; -def X14 : GP8, DwarfRegNum<[14]>; -def X15 : GP8, DwarfRegNum<[15]>; -def X16 : GP8, DwarfRegNum<[16]>; -def X17 : GP8, DwarfRegNum<[17]>; -def X18 : GP8, DwarfRegNum<[18]>; -def X19 : GP8, DwarfRegNum<[19]>; -def X20 : GP8, DwarfRegNum<[20]>; -def X21 : GP8, DwarfRegNum<[21]>; -def X22 : GP8, DwarfRegNum<[22]>; -def X23 : GP8, DwarfRegNum<[23]>; -def X24 : GP8, DwarfRegNum<[24]>; -def X25 : GP8, DwarfRegNum<[25]>; -def X26 : GP8, DwarfRegNum<[26]>; -def X27 : GP8, DwarfRegNum<[27]>; -def X28 : GP8, DwarfRegNum<[28]>; -def X29 : GP8, DwarfRegNum<[29]>; -def X30 : GP8, DwarfRegNum<[30]>; -def X31 : GP8, DwarfRegNum<[31]>; +def X0 : GP8< R0, "r0">, DwarfRegNum<[0, -2]>; +def X1 : GP8< R1, "r1">, DwarfRegNum<[1, -2]>; +def X2 : GP8< R2, "r2">, DwarfRegNum<[2, -2]>; +def X3 : GP8< R3, "r3">, DwarfRegNum<[3, -2]>; +def X4 : GP8< R4, "r4">, DwarfRegNum<[4, -2]>; +def X5 : GP8< R5, "r5">, DwarfRegNum<[5, -2]>; +def X6 : GP8< R6, "r6">, DwarfRegNum<[6, -2]>; +def X7 : GP8< R7, "r7">, DwarfRegNum<[7, -2]>; +def X8 : GP8< R8, "r8">, DwarfRegNum<[8, -2]>; +def X9 : GP8< R9, "r9">, DwarfRegNum<[9, -2]>; +def X10 : GP8, DwarfRegNum<[10, -2]>; +def X11 : GP8, DwarfRegNum<[11, -2]>; +def X12 : GP8, DwarfRegNum<[12, -2]>; +def X13 : GP8, DwarfRegNum<[13, -2]>; +def X14 : GP8, DwarfRegNum<[14, -2]>; +def X15 : GP8, DwarfRegNum<[15, -2]>; +def X16 : GP8, DwarfRegNum<[16, -2]>; +def X17 : GP8, DwarfRegNum<[17, -2]>; +def X18 : GP8, DwarfRegNum<[18, -2]>; +def X19 : GP8, DwarfRegNum<[19, -2]>; +def X20 : GP8, DwarfRegNum<[20, -2]>; +def X21 : GP8, DwarfRegNum<[21, -2]>; +def X22 : GP8, DwarfRegNum<[22, -2]>; +def X23 : GP8, DwarfRegNum<[23, -2]>; +def X24 : GP8, DwarfRegNum<[24, -2]>; +def X25 : GP8, DwarfRegNum<[25, -2]>; +def X26 : GP8, DwarfRegNum<[26, -2]>; +def X27 : GP8, DwarfRegNum<[27, -2]>; +def X28 : GP8, DwarfRegNum<[28, -2]>; +def X29 : GP8, DwarfRegNum<[29, -2]>; +def X30 : GP8, DwarfRegNum<[30, -2]>; +def X31 : GP8, DwarfRegNum<[31, -2]>; // Floating-point registers -def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>; -def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>; -def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>; -def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>; -def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>; -def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>; -def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>; -def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>; -def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>; -def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>; -def F10 : FPR<10, "f10">, DwarfRegNum<[42]>; -def F11 : FPR<11, "f11">, DwarfRegNum<[43]>; -def F12 : FPR<12, "f12">, DwarfRegNum<[44]>; -def F13 : FPR<13, "f13">, DwarfRegNum<[45]>; -def F14 : FPR<14, "f14">, DwarfRegNum<[46]>; -def F15 : FPR<15, "f15">, DwarfRegNum<[47]>; -def F16 : FPR<16, "f16">, DwarfRegNum<[48]>; -def F17 : FPR<17, "f17">, DwarfRegNum<[49]>; -def F18 : FPR<18, "f18">, DwarfRegNum<[50]>; -def F19 : FPR<19, "f19">, DwarfRegNum<[51]>; -def F20 : FPR<20, "f20">, DwarfRegNum<[52]>; -def F21 : FPR<21, "f21">, DwarfRegNum<[53]>; -def F22 : FPR<22, "f22">, DwarfRegNum<[54]>; -def F23 : FPR<23, "f23">, DwarfRegNum<[55]>; -def F24 : FPR<24, "f24">, DwarfRegNum<[56]>; -def F25 : FPR<25, "f25">, DwarfRegNum<[57]>; -def F26 : FPR<26, "f26">, DwarfRegNum<[58]>; -def F27 : FPR<27, "f27">, DwarfRegNum<[59]>; -def F28 : FPR<28, "f28">, DwarfRegNum<[60]>; -def F29 : FPR<29, "f29">, DwarfRegNum<[61]>; -def F30 : FPR<30, "f30">, DwarfRegNum<[62]>; -def F31 : FPR<31, "f31">, DwarfRegNum<[63]>; +def F0 : FPR< 0, "f0">, DwarfRegNum<[32, 32]>; +def F1 : FPR< 1, "f1">, DwarfRegNum<[33, 33]>; +def F2 : FPR< 2, "f2">, DwarfRegNum<[34, 34]>; +def F3 : FPR< 3, "f3">, DwarfRegNum<[35, 35]>; +def F4 : FPR< 4, "f4">, DwarfRegNum<[36, 36]>; +def F5 : FPR< 5, "f5">, DwarfRegNum<[37, 37]>; +def F6 : FPR< 6, "f6">, DwarfRegNum<[38, 38]>; +def F7 : FPR< 7, "f7">, DwarfRegNum<[39, 39]>; +def F8 : FPR< 8, "f8">, DwarfRegNum<[40, 40]>; +def F9 : FPR< 9, "f9">, DwarfRegNum<[41, 41]>; +def F10 : FPR<10, "f10">, DwarfRegNum<[42, 42]>; +def F11 : FPR<11, "f11">, DwarfRegNum<[43, 43]>; +def F12 : FPR<12, "f12">, DwarfRegNum<[44, 44]>; +def F13 : FPR<13, "f13">, DwarfRegNum<[45, 45]>; +def F14 : FPR<14, "f14">, DwarfRegNum<[46, 46]>; +def F15 : FPR<15, "f15">, DwarfRegNum<[47, 47]>; +def F16 : FPR<16, "f16">, DwarfRegNum<[48, 48]>; +def F17 : FPR<17, "f17">, DwarfRegNum<[49, 49]>; +def F18 : FPR<18, "f18">, DwarfRegNum<[50, 50]>; +def F19 : FPR<19, "f19">, DwarfRegNum<[51, 51]>; +def F20 : FPR<20, "f20">, DwarfRegNum<[52, 52]>; +def F21 : FPR<21, "f21">, DwarfRegNum<[53, 53]>; +def F22 : FPR<22, "f22">, DwarfRegNum<[54, 54]>; +def F23 : FPR<23, "f23">, DwarfRegNum<[55, 55]>; +def F24 : FPR<24, "f24">, DwarfRegNum<[56, 56]>; +def F25 : FPR<25, "f25">, DwarfRegNum<[57, 57]>; +def F26 : FPR<26, "f26">, DwarfRegNum<[58, 58]>; +def F27 : FPR<27, "f27">, DwarfRegNum<[59, 59]>; +def F28 : FPR<28, "f28">, DwarfRegNum<[60, 60]>; +def F29 : FPR<29, "f29">, DwarfRegNum<[61, 61]>; +def F30 : FPR<30, "f30">, DwarfRegNum<[62, 62]>; +def F31 : FPR<31, "f31">, DwarfRegNum<[63, 63]>; // Vector registers -def V0 : VR< 0, "v0">, DwarfRegNum<[77]>; -def V1 : VR< 1, "v1">, DwarfRegNum<[78]>; -def V2 : VR< 2, "v2">, DwarfRegNum<[79]>; -def V3 : VR< 3, "v3">, DwarfRegNum<[80]>; -def V4 : VR< 4, "v4">, DwarfRegNum<[81]>; -def V5 : VR< 5, "v5">, DwarfRegNum<[82]>; -def V6 : VR< 6, "v6">, DwarfRegNum<[83]>; -def V7 : VR< 7, "v7">, DwarfRegNum<[84]>; -def V8 : VR< 8, "v8">, DwarfRegNum<[85]>; -def V9 : VR< 9, "v9">, DwarfRegNum<[86]>; -def V10 : VR<10, "v10">, DwarfRegNum<[87]>; -def V11 : VR<11, "v11">, DwarfRegNum<[88]>; -def V12 : VR<12, "v12">, DwarfRegNum<[89]>; -def V13 : VR<13, "v13">, DwarfRegNum<[90]>; -def V14 : VR<14, "v14">, DwarfRegNum<[91]>; -def V15 : VR<15, "v15">, DwarfRegNum<[92]>; -def V16 : VR<16, "v16">, DwarfRegNum<[93]>; -def V17 : VR<17, "v17">, DwarfRegNum<[94]>; -def V18 : VR<18, "v18">, DwarfRegNum<[95]>; -def V19 : VR<19, "v19">, DwarfRegNum<[96]>; -def V20 : VR<20, "v20">, DwarfRegNum<[97]>; -def V21 : VR<21, "v21">, DwarfRegNum<[98]>; -def V22 : VR<22, "v22">, DwarfRegNum<[99]>; -def V23 : VR<23, "v23">, DwarfRegNum<[100]>; -def V24 : VR<24, "v24">, DwarfRegNum<[101]>; -def V25 : VR<25, "v25">, DwarfRegNum<[102]>; -def V26 : VR<26, "v26">, DwarfRegNum<[103]>; -def V27 : VR<27, "v27">, DwarfRegNum<[104]>; -def V28 : VR<28, "v28">, DwarfRegNum<[105]>; -def V29 : VR<29, "v29">, DwarfRegNum<[106]>; -def V30 : VR<30, "v30">, DwarfRegNum<[107]>; -def V31 : VR<31, "v31">, DwarfRegNum<[108]>; +def V0 : VR< 0, "v0">, DwarfRegNum<[77, 77]>; +def V1 : VR< 1, "v1">, DwarfRegNum<[78, 78]>; +def V2 : VR< 2, "v2">, DwarfRegNum<[79, 79]>; +def V3 : VR< 3, "v3">, DwarfRegNum<[80, 80]>; +def V4 : VR< 4, "v4">, DwarfRegNum<[81, 81]>; +def V5 : VR< 5, "v5">, DwarfRegNum<[82, 82]>; +def V6 : VR< 6, "v6">, DwarfRegNum<[83, 83]>; +def V7 : VR< 7, "v7">, DwarfRegNum<[84, 84]>; +def V8 : VR< 8, "v8">, DwarfRegNum<[85, 85]>; +def V9 : VR< 9, "v9">, DwarfRegNum<[86, 86]>; +def V10 : VR<10, "v10">, DwarfRegNum<[87, 87]>; +def V11 : VR<11, "v11">, DwarfRegNum<[88, 88]>; +def V12 : VR<12, "v12">, DwarfRegNum<[89, 89]>; +def V13 : VR<13, "v13">, DwarfRegNum<[90, 90]>; +def V14 : VR<14, "v14">, DwarfRegNum<[91, 91]>; +def V15 : VR<15, "v15">, DwarfRegNum<[92, 92]>; +def V16 : VR<16, "v16">, DwarfRegNum<[93, 93]>; +def V17 : VR<17, "v17">, DwarfRegNum<[94, 94]>; +def V18 : VR<18, "v18">, DwarfRegNum<[95, 95]>; +def V19 : VR<19, "v19">, DwarfRegNum<[96, 96]>; +def V20 : VR<20, "v20">, DwarfRegNum<[97, 97]>; +def V21 : VR<21, "v21">, DwarfRegNum<[98, 98]>; +def V22 : VR<22, "v22">, DwarfRegNum<[99, 99]>; +def V23 : VR<23, "v23">, DwarfRegNum<[100, 100]>; +def V24 : VR<24, "v24">, DwarfRegNum<[101, 101]>; +def V25 : VR<25, "v25">, DwarfRegNum<[102, 102]>; +def V26 : VR<26, "v26">, DwarfRegNum<[103, 103]>; +def V27 : VR<27, "v27">, DwarfRegNum<[104, 104]>; +def V28 : VR<28, "v28">, DwarfRegNum<[105, 105]>; +def V29 : VR<29, "v29">, DwarfRegNum<[106, 106]>; +def V30 : VR<30, "v30">, DwarfRegNum<[107, 107]>; +def V31 : VR<31, "v31">, DwarfRegNum<[108, 108]>; // Condition register bits def CR0LT : CRBIT< 0, "0">; @@ -236,24 +236,24 @@ // Condition registers let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in { -def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68]>; -def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69]>; -def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70]>; -def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71]>; -def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72]>; -def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73]>; -def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74]>; -def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75]>; +def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>; +def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>; +def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>; +def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>; +def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>; +def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>; +def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>; +def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>; } // Link register -def LR : SPR<8, "lr">, DwarfRegNum<[65]>; +def LR : SPR<8, "lr">, DwarfRegNum<[-2, 65]>; //let Aliases = [LR] in -def LR8 : SPR<8, "lr">, DwarfRegNum<[65]>; +def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>; // Count register -def CTR : SPR<9, "ctr">, DwarfRegNum<[66]>; -def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>; +def CTR : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>; +def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>; // VRsave register def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[109]>; From eli.friedman at gmail.com Mon May 30 13:41:53 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Mon, 30 May 2011 11:41:53 -0700 Subject: [llvm-commits] New clang builder In-Reply-To: References: Message-ID: On Thu, May 26, 2011 at 4:26 PM, Galina Kistanova wrote: > Hello, > > A new clang builder added to osusl buildbot: > > http://google1.osuosl.org:8011/builders/clang-native-arm-cortex-a9 > It's pandaboard with cortex-a9 runnibg Ubuntu 11.04. > > It builds Ok, but few test fail and need attention. > Please take a look and let me know if someone will need more > information or intermediate files to fix that. A bunch of the clang tests appear to be broken because your configure line disables the x86 backend; the tests should be fixed to take that into account. A bunch of the LLVM failures appear to be under the general category of "the JIT is broken"; not sure exactly what is going on here. It's possible it's actually just broken on ARM, because AFAIK nobody tests it regularly. Then there are a couple of misc other failures, which should be easy enough to fix. -Eli From stuart at apple.com Mon May 30 15:00:33 2011 From: stuart at apple.com (Stuart Hastings) Date: Mon, 30 May 2011 20:00:33 -0000 Subject: [llvm-commits] [llvm] r132316 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Message-ID: <20110530200034.07AEE2A6C12C@llvm.org> Author: stuart Date: Mon May 30 15:00:33 2011 New Revision: 132316 URL: http://llvm.org/viewvc/llvm-project?rev=132316&view=rev Log: (1 - X) * (-2) -> (x - 1) * 2, for all positive nonzero powers of 2 rdar://problem/6501862 Added: llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=132316&r1=132315&r2=132316&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Mon May 30 15:00:33 2011 @@ -135,6 +135,23 @@ return BinaryOperator::CreateAdd(Add, Builder->CreateMul(C1, CI)); } } + + // (1 - X) * (-2) -> (x - 1) * 2, for all positive nonzero powers of 2 + // The "* 2" thus becomes a potential shifting opportunity. + { + const APInt & Val = CI->getValue(); + const APInt &PosVal = Val.abs(); + if (Val.isNegative() && PosVal.isPowerOf2()) { + Value *X = 0; + if (match(Op0, m_Sub(m_One(), m_Value(X)))) { + // ConstantInt::get(Op0->getType(), 2); + Value *Sub = Builder->CreateSub(X, ConstantInt::get(X->getType(), 1), + "dec1"); + return BinaryOperator::CreateMul(Sub, ConstantInt::get(X->getType(), + PosVal)); + } + } + } } // Simplify mul instructions with a constant RHS. Added: llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll?rev=132316&view=auto ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll (added) +++ llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Mon May 30 15:00:33 2011 @@ -0,0 +1,24 @@ +; ModuleID = 'test1.c' +; RUN: opt -S -instcombine < %s | FileCheck %s +target triple = "x86_64-apple-macosx10.6.6" + +define zeroext i16 @foo(i32 %on_off, i16* %puls) nounwind uwtable ssp { +entry: + %on_off.addr = alloca i32, align 4 + %puls.addr = alloca i16*, align 8 + %a = alloca i32, align 4 + store i32 %on_off, i32* %on_off.addr, align 4 + store i16* %puls, i16** %puls.addr, align 8 + %tmp = load i32* %on_off.addr, align 4 +; CHECK-NOT: sub +; CHECK-NOT: mul +; (1 - %tmp) * (-2) -> (%tmp - 1) * 2 + %sub = sub i32 1, %tmp + %mul = mul i32 %sub, -2 +; CHECK: shl +; CHECK-NEXT: add + store i32 %mul, i32* %a, align 4 + %tmp1 = load i32* %a, align 4 + %conv = trunc i32 %tmp1 to i16 + ret i16 %conv +} From baldrick at free.fr Mon May 30 15:19:27 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 30 May 2011 22:19:27 +0200 Subject: [llvm-commits] [llvm] r132316 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/Transforms/InstCombine/2011-05-28-swapmulsub.ll In-Reply-To: <20110530200034.07AEE2A6C12C@llvm.org> References: <20110530200034.07AEE2A6C12C@llvm.org> Message-ID: <4DE3FBCF.7080903@free.fr> Hi Stuart, > @@ -135,6 +135,23 @@ > return BinaryOperator::CreateAdd(Add, Builder->CreateMul(C1, CI)); > } > } > + > + // (1 - X) * (-2) -> (x - 1) * 2, for all positive nonzero powers of 2 the big X becomes a little x later in the comment. It is not clear that the power of 2 comment is about 2 rather than about X. > + // The "* 2" thus becomes a potential shifting opportunity. > + { > + const APInt& Val = CI->getValue(); > + const APInt&PosVal = Val.abs(); > + if (Val.isNegative()&& PosVal.isPowerOf2()) { You should also check that Op0, aka (1-X), has only one use. Also, why does it matter that it is "1-X" specifically? Surely "Constant - X", "X - Constant", "Constant+X" and "X-Constant" are also fine, since you don't increase the amount of computation in any of these when you push the "*(-1)" into them? > + Value *X = 0; > + if (match(Op0, m_Sub(m_One(), m_Value(X)))) { > + // ConstantInt::get(Op0->getType(), 2); No need for this commented out line... Ciao, Duncan. From rafael.espindola at gmail.com Mon May 30 15:20:15 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Mon, 30 May 2011 20:20:15 -0000 Subject: [llvm-commits] [llvm] r132317 - in /llvm/trunk: include/llvm/Target/ lib/MC/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/PowerPC/InstPrinter/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/InstPrinter/ lib/Target/XCore/ test/CodeGen/X86/ utils/TableGen/ Message-ID: <20110530202016.00B822A6C12C@llvm.org> Author: rafael Date: Mon May 30 15:20:15 2011 New Revision: 132317 URL: http://llvm.org/viewvc/llvm-project?rev=132317&view=rev Log: Use the dwarf->llvm mapping to print register names in the cfi directives. Fixes PR9826. Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.h llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll llvm/trunk/test/CodeGen/X86/empty-functions.ll llvm/trunk/test/CodeGen/X86/pr9743.ll llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Mon May 30 15:20:15 2011 @@ -95,6 +95,10 @@ return TRI->getDwarfRegNum(RegNum, isEH); } + int getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const { + return TRI->getLLVMRegNum(DwarfRegNum, isEH); + } + int getSEHRegNum(unsigned RegNum) const { return TRI->getSEHRegNum(RegNum); } Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Mon May 30 15:20:15 2011 @@ -802,6 +802,8 @@ /// debugging info. virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; + virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0; + /// getFrameRegister - This method should return the register used as a base /// for values allocated in the current stack frame. virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Mon May 30 15:20:15 2011 @@ -54,6 +54,8 @@ bool needsSet(const MCExpr *Value); + void EmitRegisterName(int64_t Register); + public: MCAsmStreamer(MCContext &Context, formatted_raw_ostream &os, bool isVerboseAsm, bool useLoc, bool useCFI, @@ -819,13 +821,25 @@ EmitEOL(); } +void MCAsmStreamer::EmitRegisterName(int64_t Register) { + if (InstPrinter) { + const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo(); + unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true); + OS << '%' << InstPrinter->getRegName(LLVMRegister); + } else { + OS << Register; + } +} + void MCAsmStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) { MCStreamer::EmitCFIDefCfa(Register, Offset); if (!UseCFI) return; - OS << "\t.cfi_def_cfa " << Register << ", " << Offset; + OS << "\t.cfi_def_cfa "; + EmitRegisterName(Register); + OS << ", " << Offset; EmitEOL(); } @@ -845,7 +859,8 @@ if (!UseCFI) return; - OS << "\t.cfi_def_cfa_register " << Register; + OS << "\t.cfi_def_cfa_register "; + EmitRegisterName(Register); EmitEOL(); } @@ -855,7 +870,9 @@ if (!UseCFI) return; - OS << "\t.cfi_offset " << Register << ", " << Offset; + OS << "\t.cfi_offset "; + EmitRegisterName(Register); + OS << ", " << Offset; EmitEOL(); } @@ -906,7 +923,8 @@ if (!UseCFI) return; - OS << "\t.cfi_same_value " << Register; + OS << "\t.cfi_same_value "; + EmitRegisterName(Register); EmitEOL(); } @@ -916,7 +934,9 @@ if (!UseCFI) return; - OS << "\t.cfi_rel_offset " << Register << ", " << Offset; + OS << "\t.cfi_rel_offset "; + EmitRegisterName(Register); + OS << ", " << Offset; EmitEOL(); } Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -684,6 +684,10 @@ return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } +int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); +} + unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const { switch (Reg) { Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Mon May 30 15:20:15 2011 @@ -172,6 +172,7 @@ unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; bool isLowRegister(unsigned Reg) const; Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -199,6 +199,11 @@ return -1; } +int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const { + llvm_unreachable("What is the dwarf register number"); + return -1; +} + #include "AlphaGenRegisterInfo.inc" std::string AlphaRegisterInfo::getPrettyName(unsigned reg) Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h Mon May 30 15:20:15 2011 @@ -48,6 +48,7 @@ unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; static std::string getPrettyName(unsigned reg); }; Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -351,5 +351,11 @@ return -1; } +int BlackfinRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, + bool isEH) const { + llvm_unreachable("What is the dwarf register number"); + return -1; +} + #include "BlackfinGenRegisterInfo.inc" Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h Mon May 30 15:20:15 2011 @@ -60,6 +60,7 @@ unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; // Utility functions void adjustRegister(MachineBasicBlock &MBB, Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -328,6 +328,10 @@ return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } +int SPURegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { + return SPUGenRegisterInfo::getLLVMRegNumFull(RegNum, 0); +} + int SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const { Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h Mon May 30 15:20:15 2011 @@ -83,6 +83,7 @@ //! Get DWARF debugging register number int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; //! Convert D-form load/store to X-form load/store /*! Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -356,5 +356,9 @@ return MBlazeGenRegisterInfo::getDwarfRegNumFull(RegNo,0); } +int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); +} + #include "MBlazeGenRegisterInfo.inc" Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h Mon May 30 15:20:15 2011 @@ -75,6 +75,7 @@ unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -242,4 +242,9 @@ return 0; } +int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { + llvm_unreachable("Not implemented yet!"); + return 0; +} + #include "MSP430GenRegisterInfo.inc" Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h Mon May 30 15:20:15 2011 @@ -61,6 +61,7 @@ //! Get DWARF debugging register number int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -278,4 +278,8 @@ return MipsGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } +int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); +} + #include "MipsGenRegisterInfo.inc" Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Mon May 30 15:20:15 2011 @@ -63,6 +63,7 @@ unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h (original) +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h Mon May 30 15:20:15 2011 @@ -57,6 +57,9 @@ virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const { return PTXGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } + virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const { + return PTXGenRegisterInfo::getLLVMRegNumFull(RegNum, 0); + } }; // struct PTXRegisterInfo } // namespace llvm Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Mon May 30 15:20:15 2011 @@ -26,6 +26,9 @@ return getInstructionName(Opcode); } +StringRef PPCInstPrinter::getRegName(unsigned RegNo) const { + return getRegisterName(RegNo); +} void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { // Check for slwi/srwi mnemonics. Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h (original) +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h Mon May 30 15:20:15 2011 @@ -33,6 +33,7 @@ return SyntaxVariant == 1; } + StringRef getRegName(unsigned RegNo) const; virtual void printInst(const MCInst *MI, raw_ostream &O); virtual StringRef getOpcodeName(unsigned Opcode) const; Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Mon May 30 15:20:15 2011 @@ -487,6 +487,14 @@ int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); unsigned Reg = CSI[I].getReg(); if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; + + // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just + // subregisters of CR2. We just need to emit a move of CR2. + if (Reg == PPC::CR2LT || Reg == PPC::CR2GT || Reg == PPC::CR2EQ) + continue; + if (Reg == PPC::CR2UN) + Reg = PPC::CR2; + MachineLocation CSDst(MachineLocation::VirtualFP, Offset); MachineLocation CSSrc(Reg); Moves.push_back(MachineMove(Label, CSDst, CSSrc)); Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -702,4 +702,12 @@ return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour); } +int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { + // FIXME: Most probably dwarf numbers differs for Linux and Darwin + unsigned Flavour = Subtarget.isPPC64() ? + DWARFFlavour::PPC64 : DWARFFlavour::PPC32; + + return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour); +} + #include "PPCGenRegisterInfo.inc" Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Mon May 30 15:20:15 2011 @@ -68,6 +68,7 @@ unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -130,5 +130,9 @@ return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } +int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); +} + #include "SparcGenRegisterInfo.inc" Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Mon May 30 15:20:15 2011 @@ -52,6 +52,7 @@ unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -139,4 +139,10 @@ return -1; } +int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + assert(0 && "What is the dwarf register number"); + return -1; +} + + #include "SystemZGenRegisterInfo.inc" Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h Mon May 30 15:20:15 2011 @@ -54,6 +54,7 @@ unsigned getEHHandlerRegister() const; int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Mon May 30 15:20:15 2011 @@ -41,6 +41,10 @@ &TM.getSubtarget())); } +StringRef X86ATTInstPrinter::getRegName(unsigned RegNo) const { + return getRegisterName(RegNo); +} + void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { // Try to print any aliases first. if (!printAliasInstr(MI, OS)) Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Mon May 30 15:20:15 2011 @@ -26,6 +26,7 @@ public: X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI); + StringRef getRegName(unsigned RegNo) const; virtual void printInst(const MCInst *MI, raw_ostream &OS); virtual StringRef getOpcodeName(unsigned Opcode) const; Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Mon May 30 15:20:15 2011 @@ -29,6 +29,10 @@ #define GET_INSTRUCTION_NAME #include "X86GenAsmWriter1.inc" +StringRef X86IntelInstPrinter::getRegName(unsigned RegNo) const { + return getRegisterName(RegNo); +} + void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { printInstruction(MI, OS); Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h Mon May 30 15:20:15 2011 @@ -27,6 +27,7 @@ X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) : MCInstPrinter(MAI) {} + StringRef getRegName(unsigned RegNo) const; virtual void printInst(const MCInst *MI, raw_ostream &OS); virtual StringRef getOpcodeName(unsigned Opcode) const; Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -73,29 +73,40 @@ } } -/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF -/// specific numbering, used in debug info and exception tables. -int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const { - const X86Subtarget *Subtarget = &TM.getSubtarget(); - unsigned Flavour = DWARFFlavour::X86_64; - +static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) { if (!Subtarget->is64Bit()) { if (Subtarget->isTargetDarwin()) { if (isEH) - Flavour = DWARFFlavour::X86_32_DarwinEH; + return DWARFFlavour::X86_32_DarwinEH; else - Flavour = DWARFFlavour::X86_32_Generic; + return DWARFFlavour::X86_32_Generic; } else if (Subtarget->isTargetCygMing()) { // Unsupported by now, just quick fallback - Flavour = DWARFFlavour::X86_32_Generic; + return DWARFFlavour::X86_32_Generic; } else { - Flavour = DWARFFlavour::X86_32_Generic; + return DWARFFlavour::X86_32_Generic; } } + return DWARFFlavour::X86_64; +} + +/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF +/// specific numbering, used in debug info and exception tables. +int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const { + const X86Subtarget *Subtarget = &TM.getSubtarget(); + unsigned Flavour = getFlavour(Subtarget, isEH); return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour); } +/// getLLVMRegNum - This function maps DWARF register numbers to LLVM register. +int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + const X86Subtarget *Subtarget = &TM.getSubtarget(); + unsigned Flavour = getFlavour(Subtarget, isEH); + + return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour); +} + int X86RegisterInfo::getSEHRegNum(unsigned i) const { int reg = getX86RegNum(i); Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Mon May 30 15:20:15 2011 @@ -80,6 +80,7 @@ /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum /// (created by TableGen) for target dependencies. int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; // FIXME: This should be tablegen'd like getDwarfRegNum is int getSEHRegNum(unsigned i) const; Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Mon May 30 15:20:15 2011 @@ -315,6 +315,10 @@ return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); } +int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { + return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); +} + unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const { const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Mon May 30 15:20:15 2011 @@ -75,6 +75,7 @@ //! Get DWARF debugging register number int getDwarfRegNum(unsigned RegNum, bool isEH) const; + int getLLVMRegNum(unsigned RegNum, bool isEH) const; }; } // end namespace llvm Modified: llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll Mon May 30 15:20:15 2011 @@ -1,5 +1,5 @@ ; Check that eh_return & unwind_init were properly lowered -; RUN: llc < %s | grep %ebp | count 7 +; RUN: llc < %s | grep %ebp | count 9 ; RUN: llc < %s | grep %ecx | count 5 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" Modified: llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll Mon May 30 15:20:15 2011 @@ -1,5 +1,5 @@ ; Check that eh_return & unwind_init were properly lowered -; RUN: llc < %s | grep %rbp | count 5 +; RUN: llc < %s | grep %rbp | count 7 ; RUN: llc < %s | grep %rcx | count 3 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" Modified: llvm/trunk/test/CodeGen/X86/empty-functions.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/empty-functions.ll?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/empty-functions.ll (original) +++ llvm/trunk/test/CodeGen/X86/empty-functions.ll Mon May 30 15:20:15 2011 @@ -20,10 +20,10 @@ ; CHECK-FP-NEXT: : ; CHECK-FP-NEXT: .cfi_def_cfa_offset 16 ; CHECK-FP-NEXT: : -; CHECK-FP-NEXT: .cfi_offset 6, -16 +; CHECK-FP-NEXT: .cfi_offset %rbp, -16 ; CHECK-FP-NEXT: movq %rsp, %rbp ; CHECK-FP-NEXT: : -; CHECK-FP-NEXT: .cfi_def_cfa_register 6 +; CHECK-FP-NEXT: .cfi_def_cfa_register %rbp ; CHECK-FP-NEXT: nop ; CHECK-FP-NEXT: : ; CHECK-FP-NEXT: .cfi_endproc Modified: llvm/trunk/test/CodeGen/X86/pr9743.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr9743.ll?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr9743.ll (original) +++ llvm/trunk/test/CodeGen/X86/pr9743.ll Mon May 30 15:20:15 2011 @@ -9,9 +9,9 @@ ; CHECK-NEXT: : ; CHECK-NEXT: .cfi_def_cfa_offset 16 ; CHECK-NEXT: : -; CHECK-NEXT: .cfi_offset 6, -16 +; CHECK-NEXT: .cfi_offset %rbp, -16 ; CHECK-NEXT: movq %rsp, %rbp ; CHECK-NEXT: : -; CHECK-NEXT: .cfi_def_cfa_register 6 +; CHECK-NEXT: .cfi_def_cfa_register %rbp ; CHECK-NEXT: popq %rbp ; CHECK-NEXT: ret Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=132317&r1=132316&r2=132317&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Mon May 30 15:20:15 2011 @@ -80,6 +80,8 @@ << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" << " virtual int getDwarfRegNumFull(unsigned RegNum, " << "unsigned Flavour) const;\n" + << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " + << "unsigned Flavour) const;\n" << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" << " virtual bool needsStackRealignment(const MachineFunction &) const\n" << " { return false; }\n" @@ -989,6 +991,33 @@ for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) I->second.push_back(-1); + // Emit reverse information about the dwarf register numbers. + OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, " + << "unsigned Flavour) const {\n" + << " switch (Flavour) {\n" + << " default:\n" + << " assert(0 && \"Unknown DWARF flavour\");\n" + << " return -1;\n"; + + for (unsigned i = 0, e = maxLength; i != e; ++i) { + OS << " case " << i << ":\n" + << " switch (DwarfRegNum) {\n" + << " default:\n" + << " assert(0 && \"Invalid DwarfRegNum\");\n" + << " return -1;\n"; + + for (DwarfRegNumsMapTy::iterator + I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { + int DwarfRegNo = I->second[i]; + if (DwarfRegNo >= 0) + OS << " case " << DwarfRegNo << ":\n" + << " return " << getQualifiedName(I->first) << ";\n"; + } + OS << " };\n"; + } + + OS << " };\n}\n\n"; + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { Record *Reg = Regs[i].TheDef; const RecordVal *V = Reg->getValue("DwarfAlias"); From gkistanova at gmail.com Mon May 30 15:36:05 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Mon, 30 May 2011 20:36:05 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r132318 - in /llvm-gcc-4.2/trunk/libstdc++-v3/testsuite: Makefile.am Makefile.in Message-ID: <20110530203605.84C932A6C12C@llvm.org> Author: gkistanova Date: Mon May 30 15:36:05 2011 New Revision: 132318 URL: http://llvm.org/viewvc/llvm-project?rev=132318&view=rev Log: Removed duplicated lines. Modified: llvm-gcc-4.2/trunk/libstdc++-v3/testsuite/Makefile.am llvm-gcc-4.2/trunk/libstdc++-v3/testsuite/Makefile.in Modified: llvm-gcc-4.2/trunk/libstdc++-v3/testsuite/Makefile.am URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/libstdc%2B%2B-v3/testsuite/Makefile.am?rev=132318&r1=132317&r2=132318&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/libstdc++-v3/testsuite/Makefile.am (original) +++ llvm-gcc-4.2/trunk/libstdc++-v3/testsuite/Makefile.am Mon May 30 15:36:05 2011 @@ -57,7 +57,6 @@ @echo 'set host_triplet $(host_triplet)' >>site.tmp @echo 'set target_alias "$(target_alias)"' >>site.tmp @echo 'set target_triplet $(target_triplet)' >>site.tmp - @echo 'set target_triplet $(target_triplet)' >>site.tmp @echo 'set libiconv "$(LIBICONV)"' >>site.tmp @echo 'set baseline_file "$(baseline_file)"' >> site.tmp @echo '## All variables above are generated by configure. Do Not Edit ##' >>site.tmp Modified: llvm-gcc-4.2/trunk/libstdc++-v3/testsuite/Makefile.in URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/libstdc%2B%2B-v3/testsuite/Makefile.in?rev=132318&r1=132317&r2=132318&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/libstdc++-v3/testsuite/Makefile.in (original) +++ llvm-gcc-4.2/trunk/libstdc++-v3/testsuite/Makefile.in Mon May 30 15:36:05 2011 @@ -491,7 +491,6 @@ @echo 'set host_triplet $(host_triplet)' >>site.tmp @echo 'set target_alias "$(target_alias)"' >>site.tmp @echo 'set target_triplet $(target_triplet)' >>site.tmp - @echo 'set target_triplet $(target_triplet)' >>site.tmp @echo 'set libiconv "$(LIBICONV)"' >>site.tmp @echo 'set baseline_file "$(baseline_file)"' >> site.tmp @echo '## All variables above are generated by configure. Do Not Edit ##' >>site.tmp From fvbommel at gmail.com Mon May 30 16:52:55 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Mon, 30 May 2011 23:52:55 +0200 Subject: [llvm-commits] [llvm] r132316 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/Transforms/InstCombine/2011-05-28-swapmulsub.ll In-Reply-To: <4DE3FBCF.7080903@free.fr> References: <20110530200034.07AEE2A6C12C@llvm.org> <4DE3FBCF.7080903@free.fr> Message-ID: On Mon, May 30, 2011 at 10:19 PM, Duncan Sands wrote: >> + ? ?// The "* 2" thus becomes a potential shifting opportunity. >> + ? ?{ >> + ? ? ?const APInt& ? ?Val = CI->getValue(); >> + ? ? ?const APInt&PosVal = Val.abs(); >> + ? ? ?if (Val.isNegative()&& ?PosVal.isPowerOf2()) { > > You should also check that Op0, aka (1-X), has only one use. ?Also, why does it > matter that it is "1-X" specifically? ?Surely "Constant - X", "X - Constant", > "Constant+X" and "X-Constant" are also fine, since you don't increase the > amount of computation in any of these when you push the "*(-1)" into them? You mentioned "X-Constant" twice, but you probably meant "X+Constant" the second time. There's no need to match "Constant+X", since it will be turned into "X+Constant" by other parts of instcombine. I also don't think that for the subtraction case you even need either one to be a constant at all. -(X-Y) == (Y-X) even for non-constant X and Y. That leaves just the cases "(X-Y)*-PowerOfTwo" and "(X+Constant)*-PowerOfTwo" to consider. From bruno.cardoso at gmail.com Mon May 30 21:53:59 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 May 2011 02:53:59 -0000 Subject: [llvm-commits] [llvm] r132322 - in /llvm/trunk: lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/Mips/MipsInstrInfo.h lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsRegisterInfo.td test/CodeGen/Mips/tls.ll Message-ID: <20110531025359.2A6F32A6C12C@llvm.org> Author: bruno Date: Mon May 30 21:53:58 2011 New Revision: 132322 URL: http://llvm.org/viewvc/llvm-project?rev=132322&view=rev Log: This patch implements the thread local storage. Implemented are General Dynamic, Initial Exec and Local Exec TLS models. Patch by Sasa Stankovic Added: llvm/trunk/test/CodeGen/Mips/tls.ll Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.td llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=132322&r1=132321&r2=132322&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Mon May 30 21:53:58 2011 @@ -318,6 +318,10 @@ case MipsII::MO_GOT: O << "%got("; break; case MipsII::MO_ABS_HI: O << "%hi("; break; case MipsII::MO_ABS_LO: O << "%lo("; break; + case MipsII::MO_TLSGD: O << "%tlsgd("; break; + case MipsII::MO_GOTTPREL: O << "%gottprel("; break; + case MipsII::MO_TPREL_HI: O << "%tprel_hi("; break; + case MipsII::MO_TPREL_LO: O << "%tprel_lo("; break; } switch (MO.getType()) { Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=132322&r1=132321&r2=132322&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Mon May 30 21:53:58 2011 @@ -128,6 +128,11 @@ if ((Addr.getOpcode() == ISD::TargetExternalSymbol || Addr.getOpcode() == ISD::TargetGlobalAddress)) return false; + else if (Addr.getOpcode() == ISD::TargetGlobalTLSAddress) { + Base = CurDAG->getRegister(Mips::GP, MVT::i32); + Offset = Addr; + return true; + } } // Operand is a result from an ADD. @@ -441,6 +446,18 @@ return ResNode; // Other cases are autogenerated. break; + + case MipsISD::ThreadPointer: { + unsigned SrcReg = Mips::HWR29; + unsigned DestReg = Mips::V1; + SDNode *Rdhwr = CurDAG->getMachineNode(Mips::RDHWR, Node->getDebugLoc(), + Node->getValueType(0), CurDAG->getRegister(SrcReg, MVT::i32)); + SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, DestReg, + SDValue(Rdhwr, 0)); + SDValue ResNode = CurDAG->getCopyFromReg(Chain, dl, DestReg, MVT::i32); + ReplaceUses(SDValue(Node, 0), ResNode); + return ResNode.getNode(); + } } // Select the default instruction Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=132322&r1=132321&r2=132322&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon May 30 21:53:58 2011 @@ -41,6 +41,10 @@ case MipsISD::Hi: return "MipsISD::Hi"; case MipsISD::Lo: return "MipsISD::Lo"; case MipsISD::GPRel: return "MipsISD::GPRel"; + case MipsISD::TlsGd: return "MipsISD::TlsGd"; + case MipsISD::TprelHi: return "MipsISD::TprelHi"; + case MipsISD::TprelLo: return "MipsISD::TprelLo"; + case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; case MipsISD::Ret: return "MipsISD::Ret"; case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; case MipsISD::FPCmp: return "MipsISD::FPCmp"; @@ -822,8 +826,60 @@ SDValue MipsTargetLowering:: LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { - llvm_unreachable("TLS not implemented for MIPS."); - return SDValue(); // Not reached + // If the relocation model is PIC, use the General Dynamic TLS Model, + // otherwise use the Initial Exec or Local Exec TLS Model. + // TODO: implement Local Dynamic TLS model + + GlobalAddressSDNode *GA = cast(Op); + DebugLoc dl = GA->getDebugLoc(); + const GlobalValue *GV = GA->getGlobal(); + EVT PtrVT = getPointerTy(); + + if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { + // General Dynamic TLS Model + SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, + 0, MipsII::MO_TLSGD); + SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA); + SDValue GP = DAG.getRegister(Mips::GP, MVT::i32); + SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd); + + ArgListTy Args; + ArgListEntry Entry; + Entry.Node = Argument; + Entry.Ty = (const Type *) Type::getInt32Ty(*DAG.getContext()); + Args.push_back(Entry); + std::pair CallResult = + LowerCallTo(DAG.getEntryNode(), + (const Type *) Type::getInt32Ty(*DAG.getContext()), + false, false, false, false, + 0, CallingConv::C, false, true, + DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl); + + return CallResult.first; + } else { + SDValue Offset; + if (GV->isDeclaration()) { + // Initial Exec TLS Model + SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, + MipsII::MO_GOTTPREL); + Offset = DAG.getLoad(MVT::i32, dl, + DAG.getEntryNode(), TGA, MachinePointerInfo(), + false, false, 0); + } else { + // Local Exec TLS Model + SDVTList VTs = DAG.getVTList(MVT::i32); + SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, + MipsII::MO_TPREL_HI); + SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, + MipsII::MO_TPREL_LO); + SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1); + SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo); + Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); + } + + SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); + return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); + } } SDValue MipsTargetLowering:: Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=132322&r1=132321&r2=132322&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Mon May 30 21:53:58 2011 @@ -40,6 +40,16 @@ // Handle gp_rel (small data/bss sections) relocation. GPRel, + // General Dynamic TLS + TlsGd, + + // Local Exec TLS + TprelHi, + TprelLo, + + // Thread Pointer + ThreadPointer, + // Floating Point Branch Conditional FPBrcond, Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=132322&r1=132321&r2=132322&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Mon May 30 21:53:58 2011 @@ -146,7 +146,21 @@ /// MO_ABS_HI/LO - Represents the hi or low part of an absolute symbol /// address. MO_ABS_HI, - MO_ABS_LO + MO_ABS_LO, + + /// MO_TLSGD - Represents the offset into the global offset table at which + // the module ID and TSL block offset reside during execution (General + // Dynamic TLS). + MO_TLSGD, + + /// MO_GOTTPREL - Represents the offset from the thread pointer (Initial + // Exec TLS). + MO_GOTTPREL, + + /// MO_TPREL_HI/LO - Represents the hi and low part of the offset from + // the thread pointer (Local Exec TLS). + MO_TPREL_HI, + MO_TPREL_LO }; } Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=132322&r1=132321&r2=132322&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon May 30 21:53:58 2011 @@ -37,6 +37,8 @@ [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>]>; +def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>; + // Call def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, @@ -49,6 +51,16 @@ def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>; def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>; +// TlsGd node is used to handle General Dynamic TLS +def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>; + +// TprelHi and TprelLo nodes are used to handle Local Exec TLS +def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>; +def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>; + +// Thread pointer +def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>; + // Return def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain, SDNPOptInGlue]>; @@ -353,6 +365,13 @@ CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"), [], NoItinerary>; +// Read Hardware +class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src), + "rdhwr\t$dst, $src", [], IIAlu> { + let rs = 0; + let shamt = 0; +} + //===----------------------------------------------------------------------===// // Pseudo instructions //===----------------------------------------------------------------------===// @@ -540,6 +559,8 @@ // it is a real instruction. def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[IsMips32]>; +def RDHWR : ReadHardware; + //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// @@ -592,6 +613,15 @@ def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)), (ADDiu CPURegs:$gp, tconstpool:$in)>; +// tlsgd +def : Pat<(add CPURegs:$gp, (MipsTlsGd tglobaltlsaddr:$in)), + (ADDiu CPURegs:$gp, tglobaltlsaddr:$in)>; + +// tprel hi/lo +def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>; +def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)), + (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>; + // wrapper_pic class WrapperPICPat: Pat<(MipsWrapperPIC node:$in), Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td?rev=132322&r1=132321&r2=132322&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td Mon May 30 21:53:58 2011 @@ -44,6 +44,11 @@ let SubRegIndices = [sub_fpeven, sub_fpodd]; } +// Mips Hardware Registers +class HWR num, string n> : MipsReg { + let Num = num; +} + //===----------------------------------------------------------------------===// // Registers //===----------------------------------------------------------------------===// @@ -143,6 +148,9 @@ // Status flags register def FCR31 : Register<"31">; + + // Hardware register $29 + def HWR29 : Register<"29">; } //===----------------------------------------------------------------------===// @@ -262,3 +270,5 @@ // Hi/Lo Registers def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]>; +// Hardware registers +def HWRegs : RegisterClass<"Mips", [i32], 32, [HWR29]>; Added: llvm/trunk/test/CodeGen/Mips/tls.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/tls.ll?rev=132322&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/tls.ll (added) +++ llvm/trunk/test/CodeGen/Mips/tls.ll Mon May 30 21:53:58 2011 @@ -0,0 +1,46 @@ +; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s -check-prefix=PIC +; RUN: llc -march=mipsel -mcpu=mips2 -relocation-model=static < %s \ +; RUN: | FileCheck %s -check-prefix=STATIC + + + at t1 = thread_local global i32 0, align 4 + +define i32 @f1() nounwind { +entry: + %tmp = load i32* @t1, align 4 + ret i32 %tmp + +; CHECK: f1: + +; PIC: lw $25, %call16(__tls_get_addr)($gp) +; PIC: addiu $4, $gp, %tlsgd(t1) +; PIC: jalr $25 +; PIC: lw $2, 0($2) + +; STATIC: rdhwr $3, $29 +; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1) +; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1) +; STATIC: addu $[[R2:[0-9]+]], $3, $[[R1]] +; STATIC: lw $2, 0($[[R2]]) +} + + + at t2 = external thread_local global i32 + +define i32 @f2() nounwind { +entry: + %tmp = load i32* @t2, align 4 + ret i32 %tmp + +; CHECK: f2: + +; PIC: lw $25, %call16(__tls_get_addr)($gp) +; PIC: addiu $4, $gp, %tlsgd(t2) +; PIC: jalr $25 +; PIC: lw $2, 0($2) + +; STATIC: rdhwr $3, $29 +; STATIC: lw $[[R0:[0-9]+]], %gottprel(t2)($gp) +; STATIC: addu $[[R1:[0-9]+]], $3, $[[R0]] +; STATIC: lw $2, 0($[[R1]]) +} From bruno.cardoso at gmail.com Mon May 30 21:54:07 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 May 2011 02:54:07 -0000 Subject: [llvm-commits] [llvm] r132323 - in /llvm/trunk: lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsMachineFunction.h test/CodeGen/Mips/atomic.ll Message-ID: <20110531025407.95AF22A6C12C@llvm.org> Author: bruno Date: Mon May 30 21:54:07 2011 New Revision: 132323 URL: http://llvm.org/viewvc/llvm-project?rev=132323&view=rev Log: This patch implements atomic intrinsics atomic.load.add (sub,and,or,xor, nand), atomic.swap and atomic.cmp.swap, all in i8, i16 and i32 versions. The intrinsics are implemented by creating pseudo-instructions, which are then expanded in the method MipsTargetLowering::EmitInstrWithCustomInserter. Patch by Sasa Stankovic. Added: llvm/trunk/test/CodeGen/Mips/atomic.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.td llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=132323&r1=132322&r2=132323&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon May 30 21:54:07 2011 @@ -557,11 +557,6 @@ MachineBasicBlock * MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { - // There is no need to expand CMov instructions if target has - // conditional moves. - if (Subtarget->hasCondMov()) - return BB; - const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); bool isFPCmp = false; DebugLoc dl = MI->getDebugLoc(); @@ -569,6 +564,63 @@ switch (MI->getOpcode()) { default: assert(false && "Unexpected instr type to insert"); + + case Mips::ATOMIC_LOAD_ADD_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); + case Mips::ATOMIC_LOAD_ADD_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); + case Mips::ATOMIC_LOAD_ADD_I32: + return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); + + case Mips::ATOMIC_LOAD_AND_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); + case Mips::ATOMIC_LOAD_AND_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); + case Mips::ATOMIC_LOAD_AND_I32: + return EmitAtomicBinary(MI, BB, 4, Mips::AND); + + case Mips::ATOMIC_LOAD_OR_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); + case Mips::ATOMIC_LOAD_OR_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); + case Mips::ATOMIC_LOAD_OR_I32: + return EmitAtomicBinary(MI, BB, 4, Mips::OR); + + case Mips::ATOMIC_LOAD_XOR_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); + case Mips::ATOMIC_LOAD_XOR_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); + case Mips::ATOMIC_LOAD_XOR_I32: + return EmitAtomicBinary(MI, BB, 4, Mips::XOR); + + case Mips::ATOMIC_LOAD_NAND_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); + case Mips::ATOMIC_LOAD_NAND_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); + case Mips::ATOMIC_LOAD_NAND_I32: + return EmitAtomicBinary(MI, BB, 4, 0, true); + + case Mips::ATOMIC_LOAD_SUB_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); + case Mips::ATOMIC_LOAD_SUB_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); + case Mips::ATOMIC_LOAD_SUB_I32: + return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); + + case Mips::ATOMIC_SWAP_I8: + return EmitAtomicBinaryPartword(MI, BB, 1, 0); + case Mips::ATOMIC_SWAP_I16: + return EmitAtomicBinaryPartword(MI, BB, 2, 0); + case Mips::ATOMIC_SWAP_I32: + return EmitAtomicBinary(MI, BB, 4, 0); + + case Mips::ATOMIC_CMP_SWAP_I8: + return EmitAtomicCmpSwapPartword(MI, BB, 1); + case Mips::ATOMIC_CMP_SWAP_I16: + return EmitAtomicCmpSwapPartword(MI, BB, 2); + case Mips::ATOMIC_CMP_SWAP_I32: + return EmitAtomicCmpSwap(MI, BB, 4); + case Mips::MOVT: case Mips::MOVT_S: case Mips::MOVT_D: @@ -593,6 +645,11 @@ break; } + // There is no need to expand CMov instructions if target has + // conditional moves. + if (Subtarget->hasCondMov()) + return BB; + // To "insert" a SELECT_CC instruction, we actually have to insert the // diamond control-flow pattern. The incoming instruction knows the // destination vreg to set, the condition code register to branch on, the @@ -660,6 +717,471 @@ return BB; } +// This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and +// Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) +MachineBasicBlock * +MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, + unsigned Size, unsigned BinOpcode, bool Nand) const { + assert(Size == 4 && "Unsupported size for EmitAtomicBinary."); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &RegInfo = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + DebugLoc dl = MI->getDebugLoc(); + + unsigned Dest = MI->getOperand(0).getReg(); + unsigned Ptr = MI->getOperand(1).getReg(); + unsigned Incr = MI->getOperand(2).getReg(); + + unsigned Oldval = RegInfo.createVirtualRegister(RC); + unsigned Tmp1 = RegInfo.createVirtualRegister(RC); + unsigned Tmp2 = RegInfo.createVirtualRegister(RC); + + // insert new blocks after the current block + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineFunction::iterator It = BB; + ++It; + MF->insert(It, loopMBB); + MF->insert(It, exitMBB); + + // Transfer the remainder of BB and its successor edges to exitMBB. + exitMBB->splice(exitMBB->begin(), BB, + llvm::next(MachineBasicBlock::iterator(MI)), + BB->end()); + exitMBB->transferSuccessorsAndUpdatePHIs(BB); + + // thisMBB: + // ... + // sw incr, fi(sp) // store incr to stack (when BinOpcode == 0) + // fallthrough --> loopMBB + + // Note: for atomic.swap (when BinOpcode == 0), storing incr to stack before + // the loop and then loading it from stack in block loopMBB is necessary to + // prevent MachineLICM pass to hoist "or" instruction out of the block + // loopMBB. + + int fi; + if (BinOpcode == 0 && !Nand) { + // Get or create a temporary stack location. + MipsFunctionInfo *MipsFI = MF->getInfo(); + fi = MipsFI->getAtomicFrameIndex(); + if (fi == -1) { + fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false); + MipsFI->setAtomicFrameIndex(fi); + } + + BuildMI(BB, dl, TII->get(Mips::SW)) + .addReg(Incr).addImm(0).addFrameIndex(fi); + } + BB->addSuccessor(loopMBB); + + // loopMBB: + // ll oldval, 0(ptr) + // or dest, $0, oldval + // tmp1, oldval, incr + // sc tmp1, 0(ptr) + // beq tmp1, $0, loopMBB + BB = loopMBB; + BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addImm(0).addReg(Ptr); + BuildMI(BB, dl, TII->get(Mips::OR), Dest).addReg(Mips::ZERO).addReg(Oldval); + if (Nand) { + // and tmp2, oldval, incr + // nor tmp1, $0, tmp2 + BuildMI(BB, dl, TII->get(Mips::AND), Tmp2).addReg(Oldval).addReg(Incr); + BuildMI(BB, dl, TII->get(Mips::NOR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2); + } else if (BinOpcode) { + // tmp1, oldval, incr + BuildMI(BB, dl, TII->get(BinOpcode), Tmp1).addReg(Oldval).addReg(Incr); + } else { + // lw tmp2, fi(sp) // load incr from stack + // or tmp1, $zero, tmp2 + BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addImm(0).addFrameIndex(fi);; + BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2); + } + BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addImm(0).addReg(Ptr); + BuildMI(BB, dl, TII->get(Mips::BEQ)) + .addReg(Tmp1).addReg(Mips::ZERO).addMBB(loopMBB); + BB->addSuccessor(loopMBB); + BB->addSuccessor(exitMBB); + + MI->eraseFromParent(); // The instruction is gone now. + + return BB; +} + +MachineBasicBlock * +MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, + MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, + bool Nand) const { + assert((Size == 1 || Size == 2) && + "Unsupported size for EmitAtomicBinaryPartial."); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &RegInfo = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + DebugLoc dl = MI->getDebugLoc(); + + unsigned Dest = MI->getOperand(0).getReg(); + unsigned Ptr = MI->getOperand(1).getReg(); + unsigned Incr = MI->getOperand(2).getReg(); + + unsigned Addr = RegInfo.createVirtualRegister(RC); + unsigned Shift = RegInfo.createVirtualRegister(RC); + unsigned Mask = RegInfo.createVirtualRegister(RC); + unsigned Mask2 = RegInfo.createVirtualRegister(RC); + unsigned Newval = RegInfo.createVirtualRegister(RC); + unsigned Oldval = RegInfo.createVirtualRegister(RC); + unsigned Incr2 = RegInfo.createVirtualRegister(RC); + unsigned Tmp1 = RegInfo.createVirtualRegister(RC); + unsigned Tmp2 = RegInfo.createVirtualRegister(RC); + unsigned Tmp3 = RegInfo.createVirtualRegister(RC); + unsigned Tmp4 = RegInfo.createVirtualRegister(RC); + unsigned Tmp5 = RegInfo.createVirtualRegister(RC); + unsigned Tmp6 = RegInfo.createVirtualRegister(RC); + unsigned Tmp7 = RegInfo.createVirtualRegister(RC); + unsigned Tmp8 = RegInfo.createVirtualRegister(RC); + unsigned Tmp9 = RegInfo.createVirtualRegister(RC); + unsigned Tmp10 = RegInfo.createVirtualRegister(RC); + unsigned Tmp11 = RegInfo.createVirtualRegister(RC); + unsigned Tmp12 = RegInfo.createVirtualRegister(RC); + + // insert new blocks after the current block + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineFunction::iterator It = BB; + ++It; + MF->insert(It, loopMBB); + MF->insert(It, exitMBB); + + // Transfer the remainder of BB and its successor edges to exitMBB. + exitMBB->splice(exitMBB->begin(), BB, + llvm::next(MachineBasicBlock::iterator(MI)), + BB->end()); + exitMBB->transferSuccessorsAndUpdatePHIs(BB); + + // thisMBB: + // addiu tmp1,$0,-4 # 0xfffffffc + // and addr,ptr,tmp1 + // andi tmp2,ptr,3 + // sll shift,tmp2,3 + // ori tmp3,$0,255 # 0xff + // sll mask,tmp3,shift + // nor mask2,$0,mask + // andi tmp4,incr,255 + // sll incr2,tmp4,shift + // sw incr2, fi(sp) // store incr2 to stack (when BinOpcode == 0) + + // Note: for atomic.swap (when BinOpcode == 0), storing incr2 to stack before + // the loop and then loading it from stack in block loopMBB is necessary to + // prevent MachineLICM pass to hoist "or" instruction out of the block + // loopMBB. + + int64_t MaskImm = (Size == 1) ? 255 : 65535; + BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4); + BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1); + BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3); + BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3); + BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm); + BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift); + BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); + if (BinOpcode != Mips::SUBu) { + BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Incr).addImm(MaskImm); + BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp4).addReg(Shift); + } else { + BuildMI(BB, dl, TII->get(Mips::SUBu), Tmp4).addReg(Mips::ZERO).addReg(Incr); + BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Tmp4).addImm(MaskImm); + BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp5).addReg(Shift); + } + int fi; + if (BinOpcode == 0 && !Nand) { + // Get or create a temporary stack location. + MipsFunctionInfo *MipsFI = MF->getInfo(); + fi = MipsFI->getAtomicFrameIndex(); + if (fi == -1) { + fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false); + MipsFI->setAtomicFrameIndex(fi); + } + + BuildMI(BB, dl, TII->get(Mips::SW)) + .addReg(Incr2).addImm(0).addFrameIndex(fi); + } + BB->addSuccessor(loopMBB); + + // loopMBB: + // ll oldval,0(addr) + // binop tmp7,oldval,incr2 + // and newval,tmp7,mask + // and tmp8,oldval,mask2 + // or tmp9,tmp8,newval + // sc tmp9,0(addr) + // beq tmp9,$0,loopMBB + BB = loopMBB; + BuildMI(BB, dl, TII->get(Mips::LL), Oldval).addImm(0).addReg(Addr); + if (Nand) { + // and tmp6, oldval, incr2 + // nor tmp7, $0, tmp6 + BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval).addReg(Incr2); + BuildMI(BB, dl, TII->get(Mips::NOR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6); + } else if (BinOpcode == Mips::SUBu) { + // addu tmp7, oldval, incr2 + BuildMI(BB, dl, TII->get(Mips::ADDu), Tmp7).addReg(Oldval).addReg(Incr2); + } else if (BinOpcode) { + // tmp7, oldval, incr2 + BuildMI(BB, dl, TII->get(BinOpcode), Tmp7).addReg(Oldval).addReg(Incr2); + } else { + // lw tmp6, fi(sp) // load incr2 from stack + // or tmp7, $zero, tmp6 + BuildMI(BB, dl, TII->get(Mips::LW), Tmp6).addImm(0).addFrameIndex(fi);; + BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Mips::ZERO).addReg(Tmp6); + } + BuildMI(BB, dl, TII->get(Mips::AND), Newval).addReg(Tmp7).addReg(Mask); + BuildMI(BB, dl, TII->get(Mips::AND), Tmp8).addReg(Oldval).addReg(Mask2); + BuildMI(BB, dl, TII->get(Mips::OR), Tmp9).addReg(Tmp8).addReg(Newval); + BuildMI(BB, dl, TII->get(Mips::SC), Tmp9).addReg(Tmp9).addImm(0).addReg(Addr); + BuildMI(BB, dl, TII->get(Mips::BEQ)) + .addReg(Tmp9).addReg(Mips::ZERO).addMBB(loopMBB); + BB->addSuccessor(loopMBB); + BB->addSuccessor(exitMBB); + + // exitMBB: + // and tmp10,oldval,mask + // srl tmp11,tmp10,shift + // sll tmp12,tmp11,24 + // sra dest,tmp12,24 + BB = exitMBB; + int64_t ShiftImm = (Size == 1) ? 24 : 16; + // reverse order + BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest) + .addReg(Tmp12).addImm(ShiftImm); + BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp12) + .addReg(Tmp11).addImm(ShiftImm); + BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp11) + .addReg(Tmp10).addReg(Shift); + BuildMI(*BB, BB->begin(), dl, TII->get(Mips::AND), Tmp10) + .addReg(Oldval).addReg(Mask); + + MI->eraseFromParent(); // The instruction is gone now. + + return BB; +} + +MachineBasicBlock * +MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, + MachineBasicBlock *BB, + unsigned Size) const { + assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap."); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &RegInfo = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + DebugLoc dl = MI->getDebugLoc(); + + unsigned Dest = MI->getOperand(0).getReg(); + unsigned Ptr = MI->getOperand(1).getReg(); + unsigned Oldval = MI->getOperand(2).getReg(); + unsigned Newval = MI->getOperand(3).getReg(); + + unsigned Tmp1 = RegInfo.createVirtualRegister(RC); + unsigned Tmp2 = RegInfo.createVirtualRegister(RC); + + // insert new blocks after the current block + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineFunction::iterator It = BB; + ++It; + MF->insert(It, loop1MBB); + MF->insert(It, loop2MBB); + MF->insert(It, exitMBB); + + // Transfer the remainder of BB and its successor edges to exitMBB. + exitMBB->splice(exitMBB->begin(), BB, + llvm::next(MachineBasicBlock::iterator(MI)), + BB->end()); + exitMBB->transferSuccessorsAndUpdatePHIs(BB); + + // Get or create a temporary stack location. + MipsFunctionInfo *MipsFI = MF->getInfo(); + int fi = MipsFI->getAtomicFrameIndex(); + if (fi == -1) { + fi = MF->getFrameInfo()->CreateStackObject(Size, Size, false); + MipsFI->setAtomicFrameIndex(fi); + } + + // thisMBB: + // ... + // sw newval, fi(sp) // store newval to stack + // fallthrough --> loop1MBB + + // Note: storing newval to stack before the loop and then loading it from + // stack in block loop2MBB is necessary to prevent MachineLICM pass to + // hoist "or" instruction out of the block loop2MBB. + + BuildMI(BB, dl, TII->get(Mips::SW)) + .addReg(Newval).addImm(0).addFrameIndex(fi); + BB->addSuccessor(loop1MBB); + + // loop1MBB: + // ll dest, 0(ptr) + // bne dest, oldval, exitMBB + BB = loop1MBB; + BuildMI(BB, dl, TII->get(Mips::LL), Dest).addImm(0).addReg(Ptr); + BuildMI(BB, dl, TII->get(Mips::BNE)) + .addReg(Dest).addReg(Oldval).addMBB(exitMBB); + BB->addSuccessor(exitMBB); + BB->addSuccessor(loop2MBB); + + // loop2MBB: + // lw tmp2, fi(sp) // load newval from stack + // or tmp1, $0, tmp2 + // sc tmp1, 0(ptr) + // beq tmp1, $0, loop1MBB + BB = loop2MBB; + BuildMI(BB, dl, TII->get(Mips::LW), Tmp2).addImm(0).addFrameIndex(fi);; + BuildMI(BB, dl, TII->get(Mips::OR), Tmp1).addReg(Mips::ZERO).addReg(Tmp2); + BuildMI(BB, dl, TII->get(Mips::SC), Tmp1).addReg(Tmp1).addImm(0).addReg(Ptr); + BuildMI(BB, dl, TII->get(Mips::BEQ)) + .addReg(Tmp1).addReg(Mips::ZERO).addMBB(loop1MBB); + BB->addSuccessor(loop1MBB); + BB->addSuccessor(exitMBB); + + MI->eraseFromParent(); // The instruction is gone now. + + return BB; +} + +MachineBasicBlock * +MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, + MachineBasicBlock *BB, + unsigned Size) const { + assert((Size == 1 || Size == 2) && + "Unsupported size for EmitAtomicCmpSwapPartial."); + + MachineFunction *MF = BB->getParent(); + MachineRegisterInfo &RegInfo = MF->getRegInfo(); + const TargetRegisterClass *RC = getRegClassFor(MVT::i32); + const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); + DebugLoc dl = MI->getDebugLoc(); + + unsigned Dest = MI->getOperand(0).getReg(); + unsigned Ptr = MI->getOperand(1).getReg(); + unsigned Oldval = MI->getOperand(2).getReg(); + unsigned Newval = MI->getOperand(3).getReg(); + + unsigned Addr = RegInfo.createVirtualRegister(RC); + unsigned Shift = RegInfo.createVirtualRegister(RC); + unsigned Mask = RegInfo.createVirtualRegister(RC); + unsigned Mask2 = RegInfo.createVirtualRegister(RC); + unsigned Oldval2 = RegInfo.createVirtualRegister(RC); + unsigned Oldval3 = RegInfo.createVirtualRegister(RC); + unsigned Oldval4 = RegInfo.createVirtualRegister(RC); + unsigned Newval2 = RegInfo.createVirtualRegister(RC); + unsigned Tmp1 = RegInfo.createVirtualRegister(RC); + unsigned Tmp2 = RegInfo.createVirtualRegister(RC); + unsigned Tmp3 = RegInfo.createVirtualRegister(RC); + unsigned Tmp4 = RegInfo.createVirtualRegister(RC); + unsigned Tmp5 = RegInfo.createVirtualRegister(RC); + unsigned Tmp6 = RegInfo.createVirtualRegister(RC); + unsigned Tmp7 = RegInfo.createVirtualRegister(RC); + unsigned Tmp8 = RegInfo.createVirtualRegister(RC); + unsigned Tmp9 = RegInfo.createVirtualRegister(RC); + + // insert new blocks after the current block + const BasicBlock *LLVM_BB = BB->getBasicBlock(); + MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); + MachineFunction::iterator It = BB; + ++It; + MF->insert(It, loop1MBB); + MF->insert(It, loop2MBB); + MF->insert(It, exitMBB); + + // Transfer the remainder of BB and its successor edges to exitMBB. + exitMBB->splice(exitMBB->begin(), BB, + llvm::next(MachineBasicBlock::iterator(MI)), + BB->end()); + exitMBB->transferSuccessorsAndUpdatePHIs(BB); + + // thisMBB: + // addiu tmp1,$0,-4 # 0xfffffffc + // and addr,ptr,tmp1 + // andi tmp2,ptr,3 + // sll shift,tmp2,3 + // ori tmp3,$0,255 # 0xff + // sll mask,tmp3,shift + // nor mask2,$0,mask + // andi tmp4,oldval,255 + // sll oldval2,tmp4,shift + // andi tmp5,newval,255 + // sll newval2,tmp5,shift + int64_t MaskImm = (Size == 1) ? 255 : 65535; + BuildMI(BB, dl, TII->get(Mips::ADDiu), Tmp1).addReg(Mips::ZERO).addImm(-4); + BuildMI(BB, dl, TII->get(Mips::AND), Addr).addReg(Ptr).addReg(Tmp1); + BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp2).addReg(Ptr).addImm(3); + BuildMI(BB, dl, TII->get(Mips::SLL), Shift).addReg(Tmp2).addImm(3); + BuildMI(BB, dl, TII->get(Mips::ORi), Tmp3).addReg(Mips::ZERO).addImm(MaskImm); + BuildMI(BB, dl, TII->get(Mips::SLL), Mask).addReg(Tmp3).addReg(Shift); + BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); + BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp4).addReg(Oldval).addImm(MaskImm); + BuildMI(BB, dl, TII->get(Mips::SLL), Oldval2).addReg(Tmp4).addReg(Shift); + BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Newval).addImm(MaskImm); + BuildMI(BB, dl, TII->get(Mips::SLL), Newval2).addReg(Tmp5).addReg(Shift); + BB->addSuccessor(loop1MBB); + + // loop1MBB: + // ll oldval3,0(addr) + // and oldval4,oldval3,mask + // bne oldval4,oldval2,exitMBB + BB = loop1MBB; + BuildMI(BB, dl, TII->get(Mips::LL), Oldval3).addImm(0).addReg(Addr); + BuildMI(BB, dl, TII->get(Mips::AND), Oldval4).addReg(Oldval3).addReg(Mask); + BuildMI(BB, dl, TII->get(Mips::BNE)) + .addReg(Oldval4).addReg(Oldval2).addMBB(exitMBB); + BB->addSuccessor(exitMBB); + BB->addSuccessor(loop2MBB); + + // loop2MBB: + // and tmp6,oldval3,mask2 + // or tmp7,tmp6,newval2 + // sc tmp7,0(addr) + // beq tmp7,$0,loop1MBB + BB = loop2MBB; + BuildMI(BB, dl, TII->get(Mips::AND), Tmp6).addReg(Oldval3).addReg(Mask2); + BuildMI(BB, dl, TII->get(Mips::OR), Tmp7).addReg(Tmp6).addReg(Newval2); + BuildMI(BB, dl, TII->get(Mips::SC), Tmp7) + .addReg(Tmp7).addImm(0).addReg(Addr); + BuildMI(BB, dl, TII->get(Mips::BEQ)) + .addReg(Tmp7).addReg(Mips::ZERO).addMBB(loop1MBB); + BB->addSuccessor(loop1MBB); + BB->addSuccessor(exitMBB); + + // exitMBB: + // srl tmp8,oldval4,shift + // sll tmp9,tmp8,24 + // sra dest,tmp9,24 + BB = exitMBB; + int64_t ShiftImm = (Size == 1) ? 24 : 16; + // reverse order + BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRA), Dest) + .addReg(Tmp9).addImm(ShiftImm); + BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SLL), Tmp9) + .addReg(Tmp8).addImm(ShiftImm); + BuildMI(*BB, BB->begin(), dl, TII->get(Mips::SRL), Tmp8) + .addReg(Oldval4).addReg(Shift); + + MI->eraseFromParent(); // The instruction is gone now. + + return BB; +} + //===----------------------------------------------------------------------===// // Misc Lower Operation implementation //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=132323&r1=132322&r2=132323&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Mon May 30 21:54:07 2011 @@ -176,6 +176,16 @@ /// specified FP immediate natively. If false, the legalizer will /// materialize the FP immediate as a load from a constant pool. virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; + + MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, + unsigned Size, unsigned BinOpcode, bool Nand = false) const; + MachineBasicBlock *EmitAtomicBinaryPartword(MachineInstr *MI, + MachineBasicBlock *BB, unsigned Size, unsigned BinOpcode, + bool Nand = false) const; + MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI, + MachineBasicBlock *BB, unsigned Size) const; + MachineBasicBlock *EmitAtomicCmpSwapPartword(MachineInstr *MI, + MachineBasicBlock *BB, unsigned Size) const; }; } Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=132323&r1=132322&r2=132323&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon May 30 21:54:07 2011 @@ -405,6 +405,115 @@ def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>; def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc\n", []>; +let usesCustomInserter = 1 in { + def ATOMIC_LOAD_ADD_I8 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_add_8\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_add_8 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_ADD_I16 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_add_16\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_add_16 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_ADD_I32 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_add_32\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_add_32 CPURegs:$ptr, CPURegs:$incr))]>; + + def ATOMIC_LOAD_SUB_I8 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_sub_8\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_sub_8 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_SUB_I16 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_sub_16\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_sub_16 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_SUB_I32 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_sub_32\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_sub_32 CPURegs:$ptr, CPURegs:$incr))]>; + + def ATOMIC_LOAD_AND_I8 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_and_8\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_and_8 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_AND_I16 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_and_16\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_and_16 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_AND_I32 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_and_32\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_and_32 CPURegs:$ptr, CPURegs:$incr))]>; + + def ATOMIC_LOAD_OR_I8 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_or_8\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_or_8 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_OR_I16 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_or_16\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_or_16 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_OR_I32 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_or_32\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_or_32 CPURegs:$ptr, CPURegs:$incr))]>; + + def ATOMIC_LOAD_XOR_I8 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_xor_8\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_xor_8 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_XOR_I16 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_xor_16\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_xor_16 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_XOR_I32 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_xor_32\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_xor_32 CPURegs:$ptr, CPURegs:$incr))]>; + + def ATOMIC_LOAD_NAND_I8 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_nand_8\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_nand_8 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_NAND_I16 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_nand_16\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_nand_16 CPURegs:$ptr, CPURegs:$incr))]>; + def ATOMIC_LOAD_NAND_I32 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr), + "atomic_load_nand_32\t$dst, $ptr, $incr", + [(set CPURegs:$dst, (atomic_load_nand_32 CPURegs:$ptr, CPURegs:$incr))]>; + + def ATOMIC_SWAP_I8 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val), + "atomic_swap_8\t$dst, $ptr, $val", + [(set CPURegs:$dst, (atomic_swap_8 CPURegs:$ptr, CPURegs:$val))]>; + def ATOMIC_SWAP_I16 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val), + "atomic_swap_16\t$dst, $ptr, $val", + [(set CPURegs:$dst, (atomic_swap_16 CPURegs:$ptr, CPURegs:$val))]>; + def ATOMIC_SWAP_I32 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$val), + "atomic_swap_32\t$dst, $ptr, $val", + [(set CPURegs:$dst, (atomic_swap_32 CPURegs:$ptr, CPURegs:$val))]>; + + def ATOMIC_CMP_SWAP_I8 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval), + "atomic_cmp_swap_8\t$dst, $ptr, $oldval, $newval", + [(set CPURegs:$dst, + (atomic_cmp_swap_8 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>; + def ATOMIC_CMP_SWAP_I16 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval), + "atomic_cmp_swap_16\t$dst, $ptr, $oldval, $newval", + [(set CPURegs:$dst, + (atomic_cmp_swap_16 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>; + def ATOMIC_CMP_SWAP_I32 : MipsPseudo< + (outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval), + "atomic_cmp_swap_32\t$dst, $ptr, $oldval, $newval", + [(set CPURegs:$dst, + (atomic_cmp_swap_32 CPURegs:$ptr, CPURegs:$oldval, CPURegs:$newval))]>; +} + //===----------------------------------------------------------------------===// // Instruction definition //===----------------------------------------------------------------------===// @@ -459,6 +568,14 @@ def SH : StoreM<0x29, "sh", truncstorei16>; def SW : StoreM<0x2b, "sw", store>; +/// Load-linked, Store-conditional +let hasDelaySlot = 1 in + def LL : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr), + "ll\t$dst, $addr", [], IILoad>; +let Constraints = "$src = $dst" in + def SC : FI<0x38, (outs CPURegs:$dst), (ins CPURegs:$src, mem:$addr), + "sc\t$src, $addr", [], IIStore>; + /// Jump and Branch Instructions def J : JumpFJ<0x02, "j">; def JR : JumpFR<0x00, 0x08, "jr">; Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.h?rev=132323&r1=132322&r2=132323&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsMachineFunction.h (original) +++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Mon May 30 21:54:07 2011 @@ -48,11 +48,17 @@ std::pair InArgFIRange, OutArgFIRange; int GPFI; // Index of the frame object for restoring $gp unsigned MaxCallFrameSize; + + /// AtomicFrameIndex - To implement atomic.swap and atomic.cmp.swap + /// intrinsics, it is necessary to use a temporary stack location. + /// This field holds the frame index of this location. + int AtomicFrameIndex; public: MipsFunctionInfo(MachineFunction& MF) : SRetReturnReg(0), GlobalBaseReg(0), VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)), - OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), MaxCallFrameSize(0) + OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), MaxCallFrameSize(0), + AtomicFrameIndex(-1) {} bool isInArgFI(int FI) const { @@ -86,6 +92,9 @@ unsigned getMaxCallFrameSize() const { return MaxCallFrameSize; } void setMaxCallFrameSize(unsigned S) { MaxCallFrameSize = S; } + + int getAtomicFrameIndex() const { return AtomicFrameIndex; } + void setAtomicFrameIndex(int Index) { AtomicFrameIndex = Index; } }; } // end of namespace llvm Added: llvm/trunk/test/CodeGen/Mips/atomic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/atomic.ll?rev=132323&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/atomic.ll (added) +++ llvm/trunk/test/CodeGen/Mips/atomic.ll Mon May 30 21:54:07 2011 @@ -0,0 +1,253 @@ +; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s + + +declare i32 @llvm.atomic.load.add.i32.p0i32(i32* nocapture, i32) nounwind +declare i32 @llvm.atomic.load.nand.i32.p0i32(i32* nocapture, i32) nounwind +declare i32 @llvm.atomic.swap.i32.p0i32(i32* nocapture, i32) nounwind +declare i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* nocapture, i32, i32) nounwind + +declare i8 @llvm.atomic.load.add.i8.p0i8(i8* nocapture, i8) nounwind +declare i8 @llvm.atomic.load.sub.i8.p0i8(i8* nocapture, i8) nounwind +declare i8 @llvm.atomic.load.nand.i8.p0i8(i8* nocapture, i8) nounwind +declare i8 @llvm.atomic.swap.i8.p0i8(i8* nocapture, i8) nounwind +declare i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* nocapture, i8, i8) nounwind + + + at x = common global i32 0, align 4 + +define i32 @AtomicLoadAdd32(i32 %incr) nounwind { +entry: + %0 = call i32 @llvm.atomic.load.add.i32.p0i32(i32* @x, i32 %incr) + ret i32 %0 + +; CHECK: AtomicLoadAdd32: +; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) +; CHECK: or $2, $zero, $[[R1]] +; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4 +; CHECK: sc $[[R2]], 0($[[R0]]) +; CHECK: beq $[[R2]], $zero, $[[BB0]] +} + +define i32 @AtomicLoadNand32(i32 %incr) nounwind { +entry: + %0 = call i32 @llvm.atomic.load.nand.i32.p0i32(i32* @x, i32 %incr) + ret i32 %0 + +; CHECK: AtomicLoadNand32: +; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) +; CHECK: or $2, $zero, $[[R1]] +; CHECK: and $[[R1]], $[[R1]], $4 +; CHECK: nor $[[R2:[0-9]+]], $zero, $[[R1]] +; CHECK: sc $[[R2]], 0($[[R0]]) +; CHECK: beq $[[R2]], $zero, $[[BB0]] +} + +define i32 @AtomicSwap32(i32 %oldval) nounwind { +entry: + %0 = call i32 @llvm.atomic.swap.i32.p0i32(i32* @x, i32 %oldval) + ret i32 %0 + +; CHECK: AtomicSwap32: +; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: sw $4, [[OFFSET:[0-9]+]]($sp) +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]]) +; CHECK: or $2, $zero, $[[R1]] +; CHECK: lw $[[R2:[0-9]+]], [[OFFSET]]($sp) +; CHECK: or $[[R3:[0-9]+]], $zero, $[[R2]] +; CHECK: sc $[[R3]], 0($[[R0]]) +; CHECK: beq $[[R3]], $zero, $[[BB0]] +} + +define i32 @AtomicCmpSwap32(i32 %oldval, i32 %newval) nounwind { +entry: + %0 = call i32 @llvm.atomic.cmp.swap.i32.p0i32(i32* @x, i32 %oldval, i32 %newval) + ret i32 %0 + +; CHECK: AtomicCmpSwap32: +; CHECK: lw $[[R0:[0-9]+]], %got(x)($gp) +; CHECK: sw $5, [[OFFSET:[0-9]+]]($sp) +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $2, 0($[[R0]]) +; CHECK: bne $2, $4, $[[BB1:[A-Z_0-9]+]] +; CHECK: lw $[[R1:[0-9]+]], [[OFFSET]]($sp) +; CHECK: or $[[R2:[0-9]+]], $zero, $[[R1]] +; CHECK: sc $[[R2]], 0($[[R0]]) +; CHECK: beq $[[R2]], $zero, $[[BB0]] +; CHECK: $[[BB1]]: +} + + + + at y = common global i8 0, align 1 + +define signext i8 @AtomicLoadAdd8(i8 signext %incr) nounwind { +entry: + %0 = call i8 @llvm.atomic.load.add.i8.p0i8(i8* @y, i8 %incr) + ret i8 %0 + +; CHECK: AtomicLoadAdd8: +; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 +; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 +; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 +; CHECK: ori $[[R5:[0-9]+]], $zero, 255 +; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] +; CHECK: andi $[[R8:[0-9]+]], $4, 255 +; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] + +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) +; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] +; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] +; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] +; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] +; CHECK: sc $[[R14]], 0($[[R2]]) +; CHECK: beq $[[R14]], $zero, $[[BB0]] + +; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] +; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 +; CHECK: sra $2, $[[R17]], 24 +} + +define signext i8 @AtomicLoadSub8(i8 signext %incr) nounwind { +entry: + %0 = call i8 @llvm.atomic.load.sub.i8.p0i8(i8* @y, i8 %incr) + ret i8 %0 + +; CHECK: AtomicLoadSub8: +; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 +; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 +; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 +; CHECK: ori $[[R5:[0-9]+]], $zero, 255 +; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] +; CHECK: subu $[[R18:[0-9]+]], $zero, $4 +; CHECK: andi $[[R8:[0-9]+]], $[[R18]], 255 +; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] + +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) +; CHECK: addu $[[R11:[0-9]+]], $[[R10]], $[[R9]] +; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] +; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] +; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] +; CHECK: sc $[[R14]], 0($[[R2]]) +; CHECK: beq $[[R14]], $zero, $[[BB0]] + +; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] +; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 +; CHECK: sra $2, $[[R17]], 24 +} + +define signext i8 @AtomicLoadNand8(i8 signext %incr) nounwind { +entry: + %0 = call i8 @llvm.atomic.load.nand.i8.p0i8(i8* @y, i8 %incr) + ret i8 %0 + +; CHECK: AtomicLoadNand8: +; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 +; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 +; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 +; CHECK: ori $[[R5:[0-9]+]], $zero, 255 +; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] +; CHECK: andi $[[R8:[0-9]+]], $4, 255 +; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] + +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) +; CHECK: and $[[R18:[0-9]+]], $[[R10]], $[[R9]] +; CHECK: nor $[[R11:[0-9]+]], $zero, $[[R18]] +; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] +; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] +; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] +; CHECK: sc $[[R14]], 0($[[R2]]) +; CHECK: beq $[[R14]], $zero, $[[BB0]] + +; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] +; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 +; CHECK: sra $2, $[[R17]], 24 +} + +define signext i8 @AtomicSwap8(i8 signext %oldval) nounwind { +entry: + %0 = call i8 @llvm.atomic.swap.i8.p0i8(i8* @y, i8 %oldval) + ret i8 %0 + +; CHECK: AtomicSwap8: +; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 +; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 +; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 +; CHECK: ori $[[R5:[0-9]+]], $zero, 255 +; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] +; CHECK: andi $[[R8:[0-9]+]], $4, 255 +; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: sw $[[R9]], [[OFFSET:[0-9]+]]($sp) + +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R10:[0-9]+]], 0($[[R2]]) +; CHECK: lw $[[R18:[0-9]+]], [[OFFSET]]($sp) +; CHECK: or $[[R11:[0-9]+]], $zero, $[[R18]] +; CHECK: and $[[R12:[0-9]+]], $[[R11]], $[[R6]] +; CHECK: and $[[R13:[0-9]+]], $[[R10]], $[[R7]] +; CHECK: or $[[R14:[0-9]+]], $[[R13]], $[[R12]] +; CHECK: sc $[[R14]], 0($[[R2]]) +; CHECK: beq $[[R14]], $zero, $[[BB0]] + +; CHECK: and $[[R15:[0-9]+]], $[[R10]], $[[R6]] +; CHECK: srl $[[R16:[0-9]+]], $[[R15]], $[[R4]] +; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 +; CHECK: sra $2, $[[R17]], 24 +} + +define signext i8 @AtomicCmpSwap8(i8 signext %oldval, i8 signext %newval) nounwind { +entry: + %0 = call i8 @llvm.atomic.cmp.swap.i8.p0i8(i8* @y, i8 %oldval, i8 %newval) + ret i8 %0 + +; CHECK: AtomicCmpSwap8: +; CHECK: lw $[[R0:[0-9]+]], %got(y)($gp) +; CHECK: addiu $[[R1:[0-9]+]], $zero, -4 +; CHECK: and $[[R2:[0-9]+]], $[[R0]], $[[R1]] +; CHECK: andi $[[R3:[0-9]+]], $[[R0]], 3 +; CHECK: sll $[[R4:[0-9]+]], $[[R3]], 3 +; CHECK: ori $[[R5:[0-9]+]], $zero, 255 +; CHECK: sll $[[R6:[0-9]+]], $[[R5]], $[[R4]] +; CHECK: nor $[[R7:[0-9]+]], $zero, $[[R6]] +; CHECK: andi $[[R8:[0-9]+]], $4, 255 +; CHECK: sll $[[R9:[0-9]+]], $[[R8]], $[[R4]] +; CHECK: andi $[[R10:[0-9]+]], $5, 255 +; CHECK: sll $[[R11:[0-9]+]], $[[R10]], $[[R4]] + +; CHECK: $[[BB0:[A-Z_0-9]+]]: +; CHECK: ll $[[R12:[0-9]+]], 0($[[R2]]) +; CHECK: and $[[R13:[0-9]+]], $[[R12]], $[[R6]] +; CHECK: bne $[[R13]], $[[R9]], $[[BB1:[A-Z_0-9]+]] + +; CHECK: and $[[R14:[0-9]+]], $[[R12]], $[[R7]] +; CHECK: or $[[R15:[0-9]+]], $[[R14]], $[[R11]] +; CHECK: sc $[[R15]], 0($[[R2]]) +; CHECK: beq $[[R15]], $zero, $[[BB0]] + +; CHECK: $[[BB1]]: +; CHECK: srl $[[R16:[0-9]+]], $[[R13]], $[[R4]] +; CHECK: sll $[[R17:[0-9]+]], $[[R16]], 24 +; CHECK: sra $2, $[[R17]], 24 +} From david.majnemer at gmail.com Mon May 30 22:35:38 2011 From: david.majnemer at gmail.com (David Majnemer) Date: Mon, 30 May 2011 23:35:38 -0400 Subject: [llvm-commits] [PATCH] Implement a few missing InstCombine/InstSimplify optimizations Message-ID: This patch implements a few of the optimizations mentioned in http://www.nondot.org/sabre/LLVMNotes/InstCombine.txt specifically: if ((x & C) == 0) x |= C becomes x |= C if ((x & C) == 0) x &= ~C becomes nothing if (((1 << which_alternative) & 0x7)) becomes if (which_alternative < 3) if (!((1 << which_alternative) & 0x3)) becomes if (which_alternative >= 2) The patch also implements slightly more powerful variations of the first two, C need not be a constant. For those still using that file, note that the array indexing example seems to be optimized out. I have included several tests that verify that the transform is coming into effect, they seem to be comprehensive enough. If I have implemented something wrong/tested something wrong/broken something, I'll fix it ASAP One last thing, I believe that there were some redundant hasOneUse() calls in InstCombineCompares.cpp, I removed the ones that were nearby. -- David Majnemer -------------- next part -------------- A non-text attachment was scrubbed... Name: instcombine.patch Type: application/octet-stream Size: 5714 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110530/5a4fca12/attachment.obj From bruno.cardoso at gmail.com Mon May 30 22:33:28 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 May 2011 03:33:28 -0000 Subject: [llvm-commits] [llvm] r132324 - in /llvm/trunk: lib/Target/ARM/ARMCodeEmitter.cpp lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMMCCodeEmitter.cpp test/MC/ARM/arm_instructions.s test/MC/ARM/thumb2.s utils/TableGen/EDEmitter.cpp Message-ID: <20110531033328.3B8FF2A6C12C@llvm.org> Author: bruno Date: Mon May 30 22:33:27 2011 New Revision: 132324 URL: http://llvm.org/viewvc/llvm-project?rev=132324&view=rev Log: Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value must be encoded decremented by one. Only add encoding tests for ssat16 because ssat can't be parsed yet. Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp llvm/trunk/test/MC/ARM/arm_instructions.s llvm/trunk/test/MC/ARM/thumb2.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=132324&r1=132323&r2=132324&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Mon May 30 22:33:27 2011 @@ -232,6 +232,8 @@ unsigned Op) const { return 0; } unsigned getMsbOpValue(const MachineInstr &MI, unsigned Op) const { return 0; } + unsigned getSsatBitPosValue(const MachineInstr &MI, + unsigned Op) const { return 0; } uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx) const {return 0; } uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx) Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=132324&r1=132323&r2=132324&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon May 30 22:33:27 2011 @@ -475,6 +475,12 @@ let EncoderMethod = "getMsbOpValue"; } +def ssat_imm : Operand, ImmLeaf 0 && Imm <= 32; +}]> { + let EncoderMethod = "getSsatBitPosValue"; +} + // Define ARM specific addressing modes. def MemMode2AsmOperand : AsmOperandClass { @@ -2455,7 +2461,7 @@ // Signed/Unsigned saturate -- for disassembly only -def SSAT : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$a, shift_imm:$sh), +def SSAT : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$a, shift_imm:$sh), SatFrm, NoItinerary, "ssat", "\t$Rd, $sat_imm, $a$sh", [/* For disassembly only; pattern left blank */]> { bits<4> Rd; @@ -2471,7 +2477,7 @@ let Inst{3-0} = Rn; } -def SSAT16 : AI<(outs GPR:$Rd), (ins i32imm:$sat_imm, GPR:$Rn), SatFrm, +def SSAT16 : AI<(outs GPR:$Rd), (ins ssat_imm:$sat_imm, GPR:$Rn), SatFrm, NoItinerary, "ssat16", "\t$Rd, $sat_imm, $Rn", [/* For disassembly only; pattern left blank */]> { bits<4> Rd; Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=132324&r1=132323&r2=132324&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon May 30 22:33:27 2011 @@ -1973,9 +1973,9 @@ } def t2SSAT: T2SatI< - (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn, shift_imm:$sh), - NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", - [/* For disassembly only; pattern left blank */]> { + (outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn, shift_imm:$sh), + NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", + [/* For disassembly only; pattern left blank */]> { let Inst{31-27} = 0b11110; let Inst{25-22} = 0b1100; let Inst{20} = 0; @@ -1983,9 +1983,9 @@ } def t2SSAT16: T2SatI< - (outs rGPR:$Rd), (ins i32imm:$sat_imm, rGPR:$Rn), NoItinerary, - "ssat16", "\t$Rd, $sat_imm, $Rn", - [/* For disassembly only; pattern left blank */]> { + (outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn), NoItinerary, + "ssat16", "\t$Rd, $sat_imm, $Rn", + [/* For disassembly only; pattern left blank */]> { let Inst{31-27} = 0b11110; let Inst{25-22} = 0b1100; let Inst{20} = 0; Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=132324&r1=132323&r2=132324&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Mon May 30 22:33:27 2011 @@ -269,6 +269,9 @@ unsigned getMsbOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const; + unsigned getSsatBitPosValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const; + unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const; unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op, @@ -1124,6 +1127,13 @@ } unsigned ARMMCCodeEmitter:: +getSsatBitPosValue(const MCInst &MI, unsigned Op, + SmallVectorImpl &Fixups) const { + // For ssat instructions, the bit position should be encoded decremented by 1 + return MI.getOperand(Op).getImm()-1; +} + +unsigned ARMMCCodeEmitter:: getRegisterListOpValue(const MCInst &MI, unsigned Op, SmallVectorImpl &Fixups) const { // VLDM/VSTM: Modified: llvm/trunk/test/MC/ARM/arm_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=132324&r1=132323&r2=132324&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) +++ llvm/trunk/test/MC/ARM/arm_instructions.s Mon May 30 22:33:27 2011 @@ -312,3 +312,6 @@ @ CHECK: ldrexd r0, r1, [r0] @ encoding: [0x9f,0x0f,0xb0,0xe1] ldrexd r0, r1, [r0] +@ CHECK: ssat16 r0, #7, r0 @ encoding: [0x30,0x0f,0xa6,0xe6] + ssat16 r0, #7, r0 + Modified: llvm/trunk/test/MC/ARM/thumb2.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2.s?rev=132324&r1=132323&r2=132324&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/thumb2.s (original) +++ llvm/trunk/test/MC/ARM/thumb2.s Mon May 30 22:33:27 2011 @@ -300,3 +300,5 @@ ldrex r0, [r0] @ CHECK: ldrexd r0, r1, [r0] @ encoding: [0xd0,0xe8,0x7f,0x01] ldrexd r0, r1, [r0] +@ CHECK: ssat16 r0, #7, r0 @ encoding: [0x20,0xf3,0x06,0x00] + ssat16 r0, #7, r0 Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=132324&r1=132323&r2=132324&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon May 30 22:33:27 2011 @@ -596,6 +596,7 @@ IMM("t_adrlabel"); IMM("t2adrlabel"); IMM("shift_imm"); + IMM("ssat_imm"); IMM("neon_vcvt_imm32"); IMM("shr_imm8"); IMM("shr_imm16"); From akyrtzi at gmail.com Mon May 30 22:53:41 2011 From: akyrtzi at gmail.com (Argyrios Kyrtzidis) Date: Tue, 31 May 2011 03:53:41 -0000 Subject: [llvm-commits] [llvm] r132325 - /llvm/trunk/include/llvm/ADT/PackedVector.h Message-ID: <20110531035341.89BA52A6C12C@llvm.org> Author: akirtzidis Date: Mon May 30 22:53:41 2011 New Revision: 132325 URL: http://llvm.org/viewvc/llvm-project?rev=132325&view=rev Log: Introduce PackedVector, useful for storing a vector of values using a specific number of bits for each value. Both signed and unsigned types can be used, e.g PackedVector vec; will create a vector accepting values -2, -1, 0, 1. Any other value will hit an assertion. Added: llvm/trunk/include/llvm/ADT/PackedVector.h Added: llvm/trunk/include/llvm/ADT/PackedVector.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/PackedVector.h?rev=132325&view=auto ============================================================================== --- llvm/trunk/include/llvm/ADT/PackedVector.h (added) +++ llvm/trunk/include/llvm/ADT/PackedVector.h Mon May 30 22:53:41 2011 @@ -0,0 +1,158 @@ +//===- llvm/ADT/PackedVector.h - Packed values vector -----------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the PackedVector class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ADT_PACKEDVECTOR_H +#define LLVM_ADT_PACKEDVECTOR_H + +#include "llvm/ADT/BitVector.h" +#include + +namespace llvm { + +template +class PackedVectorBase; + +// This won't be necessary if we can specialize members without specializing +// the parent template. +template +class PackedVectorBase { +protected: + static T getValue(const llvm::BitVector &Bits, unsigned Idx) { + T val = T(); + for (unsigned i = 0; i != BitNum; ++i) + val = T(val | ((Bits[(Idx << (BitNum-1)) + i] ? 1UL : 0UL) << i)); + return val; + } + + static void setValue(llvm::BitVector &Bits, unsigned Idx, T val) { + assert((val >> BitNum) == 0 && "value is too big"); + for (unsigned i = 0; i != BitNum; ++i) + Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i); + } +}; + +template +class PackedVectorBase { +protected: + static T getValue(const llvm::BitVector &Bits, unsigned Idx) { + T val = T(); + for (unsigned i = 0; i != BitNum-1; ++i) + val = T(val | ((Bits[(Idx << (BitNum-1)) + i] ? 1UL : 0UL) << i)); + if (Bits[(Idx << (BitNum-1)) + BitNum-1]) + val = ~val; + return val; + } + + static void setValue(llvm::BitVector &Bits, unsigned Idx, T val) { + if (val < 0) { + val = ~val; + Bits.set((Idx << (BitNum-1)) + BitNum-1); + } + assert((val >> (BitNum-1)) == 0 && "value is too big"); + for (unsigned i = 0; i != BitNum-1; ++i) + Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i); + } +}; + +/// \brief Store a vector of values using a specific number of bits for each +/// value. Both signed and unsigned types can be used, e.g +/// @code +/// PackedVector vec; +/// @endcode +/// will create a vector accepting values -2, -1, 0, 1. Any other value will hit +/// an assertion. +template +class PackedVector : public PackedVectorBase::is_signed> { + llvm::BitVector Bits; + typedef PackedVectorBase::is_signed> base; + +public: + class reference { + PackedVector &Vec; + const unsigned Idx; + + reference(); // Undefined + public: + reference(PackedVector &vec, unsigned idx) : Vec(vec), Idx(idx) { } + + reference &operator=(T val) { + Vec.setValue(Vec.Bits, Idx, val); + return *this; + } + operator T() { + return Vec.getValue(Vec.Bits, Idx); + } + }; + + PackedVector() { } + explicit PackedVector(unsigned size) : Bits(size << (BitNum-1)) { } + + bool empty() const { return Bits.empty(); } + + unsigned size() const { return Bits.size() >> (BitNum-1); } + + void clear() { Bits.clear(); } + + void resize(unsigned N) { Bits.resize(N << (BitNum-1)); } + + void reserve(unsigned N) { Bits.reserve(N << (BitNum-1)); } + + PackedVector &reset() { + Bits.reset(); + return *this; + } + + void push_back(T val) { + resize(size()+1); + (*this)[size()-1] = val; + } + + reference operator[](unsigned Idx) { + return reference(*this, Idx); + } + + T operator[](unsigned Idx) const { + return base::getValue(Bits, Idx); + } + + bool operator==(const PackedVector &RHS) const { + return Bits == RHS.Bits; + } + + bool operator!=(const PackedVector &RHS) const { + return Bits != RHS.Bits; + } + + const PackedVector &operator=(const PackedVector &RHS) { + Bits = RHS.Bits; + return *this; + } + + PackedVector &operator|=(const PackedVector &RHS) { + Bits |= RHS.Bits; + return *this; + } + + void swap(PackedVector &RHS) { + Bits.swap(RHS.Bits); + } +}; + +// Leave BitNum=0 undefined. +template +class PackedVector; + +} // end llvm namespace + +#endif From chandlerc at google.com Mon May 30 23:38:46 2011 From: chandlerc at google.com (Chandler Carruth) Date: Mon, 30 May 2011 21:38:46 -0700 Subject: [llvm-commits] [llvm] r132325 - /llvm/trunk/include/llvm/ADT/PackedVector.h In-Reply-To: <20110531035341.89BA52A6C12C@llvm.org> References: <20110531035341.89BA52A6C12C@llvm.org> Message-ID: On Mon, May 30, 2011 at 8:53 PM, Argyrios Kyrtzidis wrote: > Author: akirtzidis > Date: Mon May 30 22:53:41 2011 > New Revision: 132325 > > URL: http://llvm.org/viewvc/llvm-project?rev=132325&view=rev > Log: > Introduce PackedVector, useful for storing a vector of values using a specific number of bits for each > value. Both signed and unsigned types can be used, e.g > > ? PackedVector vec; > > will create a vector accepting values -2, -1, 0, 1. Any other value will hit an assertion. Any chance we could get unit tests for this? It seems like a really good candidate. From akyrtzi at gmail.com Mon May 30 23:43:43 2011 From: akyrtzi at gmail.com (Argyrios Kyrtzidis) Date: Mon, 30 May 2011 21:43:43 -0700 Subject: [llvm-commits] [llvm] r132325 - /llvm/trunk/include/llvm/ADT/PackedVector.h In-Reply-To: References: <20110531035341.89BA52A6C12C@llvm.org> Message-ID: <366D4ED5-B0AB-4CF2-89F6-86A9D05588B8@gmail.com> On May 30, 2011, at 9:38 PM, Chandler Carruth wrote: > On Mon, May 30, 2011 at 8:53 PM, Argyrios Kyrtzidis wrote: >> Author: akirtzidis >> Date: Mon May 30 22:53:41 2011 >> New Revision: 132325 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132325&view=rev >> Log: >> Introduce PackedVector, useful for storing a vector of values using a specific number of bits for each >> value. Both signed and unsigned types can be used, e.g >> >> PackedVector vec; >> >> will create a vector accepting values -2, -1, 0, 1. Any other value will hit an assertion. > > Any chance we could get unit tests for this? It seems like a really > good candidate. Sure, on the TODO list :-) From baldrick at free.fr Tue May 31 01:28:31 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 31 May 2011 08:28:31 +0200 Subject: [llvm-commits] [PATCH] Implement a few missing InstCombine/InstSimplify optimizations In-Reply-To: References: Message-ID: <4DE48A8F.60804@free.fr> Hi David, > This patch implements a few of the optimizations mentioned in > http://www.nondot.org/sabre/LLVMNotes/InstCombine.txt > > specifically: > if ((x& C) == 0) x |= C becomes x |= C > if ((x& C) == 0) x&= ~C becomes nothing > if (((1<< which_alternative)& 0x7)) becomes if (which_alternative< 3) > if (!((1<< which_alternative)& 0x3)) becomes if (which_alternative>= 2) > > The patch also implements slightly more powerful variations of the > first two, C need not be a constant. unfortunately the first one is wrong if C is not a "single bit" (power of 2). Consider for example if ((x & C) == 0) x |= C Take x = 2 and C = 3. Then x&C=2, so (x&C)==0 is false. Thus the result is the original value of x, namely 2. You propose replacing x with x|C in this case which is equal to 3. So this changes the result from 2 to 3, which is wrong. Also, in this bit + ConstantInt *AndCI, *And2CI; + // Transform: "if ((x & C) == 0) x &= ~C" ==> x &= ~C + if (match(AndRHS, m_ConstantInt(AndCI)) && + match(TrueVal, m_And(m_Specific(FalseVal), m_ConstantInt(And2CI))) && + AndCI == ConstantExpr::getNot(And2CI)) { + return FalseVal; + } + // Transform: "if ((x & y) == 0) x &= ~y" ==> x &= ~y + if (match(TrueVal, m_And(m_Specific(FalseVal), m_Not(m_Specific(AndRHS))))) { + return FalseVal; + } the first part should be redundant, i.e. caught by the second part. If it is not then I think you would do better to enhance m_Not to make the second part catch everything. That said, I don't much like these changes to InstructionSimplify. What LLVM needs in general and InstructionSimplify in particular is a generic machinery for reasoning about simple implications. Consider "select Cond, TV, FV". If you can prove the implication "Cond => (TV == FV)" then you can replace the select with FV. Your code above is a special case of this. I would rather see a more general infrastructure for proving implications. Ciao, Duncan. From nicholas at mxc.ca Tue May 31 01:45:57 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 30 May 2011 23:45:57 -0700 Subject: [llvm-commits] [PATCH] Implement a few missing InstCombine/InstSimplify optimizations In-Reply-To: <4DE48A8F.60804@free.fr> References: <4DE48A8F.60804@free.fr> Message-ID: <4DE48EA5.5050802@mxc.ca> Duncan Sands wrote: > Hi David, > >> This patch implements a few of the optimizations mentioned in >> http://www.nondot.org/sabre/LLVMNotes/InstCombine.txt >> >> specifically: >> if ((x& C) == 0) x |= C becomes x |= C >> if ((x& C) == 0) x&= ~C becomes nothing >> if (((1<< which_alternative)& 0x7)) becomes if (which_alternative< 3) >> if (!((1<< which_alternative)& 0x3)) becomes if (which_alternative>= 2) >> >> The patch also implements slightly more powerful variations of the >> first two, C need not be a constant. > > unfortunately the first one is wrong if C is not a "single bit" (power of 2). > Consider for example > if ((x& C) == 0) x |= C > Take x = 2 and C = 3. Then x&C=2, so (x&C)==0 is false. Thus the result is > the original value of x, namely 2. You propose replacing x with x|C in this > case which is equal to 3. So this changes the result from 2 to 3, which is > wrong. > > Also, in this bit > > + ConstantInt *AndCI, *And2CI; > + // Transform: "if ((x& C) == 0) x&= ~C" ==> x&= ~C > + if (match(AndRHS, m_ConstantInt(AndCI))&& > + match(TrueVal, m_And(m_Specific(FalseVal), m_ConstantInt(And2CI)))&& > + AndCI == ConstantExpr::getNot(And2CI)) { > + return FalseVal; > + } > + // Transform: "if ((x& y) == 0) x&= ~y" ==> x&= ~y > + if (match(TrueVal, m_And(m_Specific(FalseVal), m_Not(m_Specific(AndRHS))))) { > + return FalseVal; > + } > > the first part should be redundant, i.e. caught by the second part. If it is > not then I think you would do better to enhance m_Not to make the second part > catch everything. Careful that you don't cause an infinite loop in the optimizer. It would be fine in this case where the argument is an m_Specific, but it's not clear to me how implementable that is. Nick > That said, I don't much like these changes to InstructionSimplify. What LLVM > needs in general and InstructionSimplify in particular is a generic machinery > for reasoning about simple implications. Consider "select Cond, TV, FV". If > you can prove the implication "Cond => (TV == FV)" then you can replace the > select with FV. Your code above is a special case of this. I would rather > see a more general infrastructure for proving implications. > > Ciao, Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From david.majnemer at gmail.com Tue May 31 01:53:51 2011 From: david.majnemer at gmail.com (David Majnemer) Date: Tue, 31 May 2011 02:53:51 -0400 Subject: [llvm-commits] [PATCH] Implement a few missing InstCombine/InstSimplify optimizations In-Reply-To: <4DE48A8F.60804@free.fr> References: <4DE48A8F.60804@free.fr> Message-ID: Hi Duncan, On Tue, May 31, 2011 at 2:28 AM, Duncan Sands wrote: > Hi David, > >> This patch implements a few of the optimizations mentioned in >> http://www.nondot.org/sabre/LLVMNotes/InstCombine.txt >> >> specifically: >> if ((x& ?C) == 0) x |= C ? ? ?becomes ? ? ? ? x |= C >> if ((x& ?C) == 0) x&= ~C ? ? ?becomes ? ? ? ? nothing >> if (((1<< ?which_alternative)& ?0x7)) becomes if (which_alternative< ?3) >> if (!((1<< ?which_alternative)& ?0x3)) becomes if (which_alternative>= 2) >> >> The patch also implements slightly more powerful variations of the >> first two, C need not be a constant. > > unfortunately the first one is wrong if C is not a "single bit" (power of 2). > Consider for example > ? if ((x & C) == 0) x |= C > Take x = 2 and C = 3. ?Then x&C=2, so (x&C)==0 is false. ?Thus the result is > the original value of x, namely 2. ?You propose replacing x with x|C in this > case which is equal to 3. ?So this changes the result from 2 to 3, which is > wrong. You are correct, I somehow transformed this in my head to if ((x & C) != C) x |= C, the transform must be more strict. > > Also, in this bit > > + ? ?ConstantInt *AndCI, *And2CI; > + ? ?// Transform: "if ((x & C) == 0) x &= ~C" ==> x &= ~C > + ? ?if (match(AndRHS, m_ConstantInt(AndCI)) && > + ? ? ? ?match(TrueVal, m_And(m_Specific(FalseVal), m_ConstantInt(And2CI))) && > + ? ? ? ?AndCI == ConstantExpr::getNot(And2CI)) { > + ? ? ?return FalseVal; > + ? ?} > + ? ?// Transform: "if ((x & y) == 0) x &= ~y" ==> x &= ~y > + ? ?if (match(TrueVal, m_And(m_Specific(FalseVal), m_Not(m_Specific(AndRHS))))) { > + ? ? ?return FalseVal; > + ? ?} > > the first part should be redundant, i.e. caught by the second part. ?If it is > not then I think you would do better to enhance m_Not to make the second part > catch everything. Just realized that those comments are wrong, it should be (x & y) != 0.... Yes, I also assumed that m_Not would match ConstantInt, however it does not. I considering making the change you recommended but decided that m_Not is used in quite a few places and changing the semantics of m_Not in this way would slow it down and potentially break things. I am guessing that most uses of m_Not that would hit ConstantInt would be smashed away by constant folding instead of being this case... With that in mind I am open to modifying m_Not, I just don't know how much the consumers of that match would like it. With that in mind "if ((x & y) != 0) x &= ~y" ==> "x &= ~y" is wrong while "if ((x & y) == 0) x &= ~y" ==> "x" is OK > > That said, I don't much like these changes to InstructionSimplify. ?What LLVM > needs in general and InstructionSimplify in particular is a generic machinery > for reasoning about simple implications. ?Consider "select Cond, TV, FV". ?If > you can prove the implication "Cond => (TV == FV)" then you can replace the > select with FV. ?Your code above is a special case of this. ?I would rather > see a more general infrastructure for proving implications. Hrm, that does sound useful but it also seems like a serious reworking of InstructionSimplify... > > Ciao, Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From baldrick at free.fr Tue May 31 02:05:50 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 31 May 2011 07:05:50 -0000 Subject: [llvm-commits] [dragonegg] r132328 - in /dragonegg/trunk: gcc_revision_tested_with src/Backend.cpp src/Convert.cpp Message-ID: <20110531070550.EEDF52A6C12C@llvm.org> Author: baldrick Date: Tue May 31 02:05:50 2011 New Revision: 132328 URL: http://llvm.org/viewvc/llvm-project?rev=132328&view=rev Log: Reapply commit 131965 now that the gcc-4.5 bug it exposed has been fixed. Make the buildbots use a version of gcc-4.5 with the fix. Original commit log: Unify function emission logic between the normal case and the case of running the GCC optimizers. In the normal case we would traverse the call graph at LTO time, outputting functions along with aliases. In the GCC optimization case this isn't possible because LTO time is too early: before most GCC optimizers run. So then we would simply replace RTL codegen with conversion of functions to IR. To unify these we now emit functions always in place of RTL codegen. As an added bonus this makes it possible to remove the special logic for outputting thunks: by telling cgraph that the target machine doesn't have special thunk support it kindly generates appropriate thunk function bodies for us which can be accessed at RTL codegen time. Modified: dragonegg/trunk/gcc_revision_tested_with dragonegg/trunk/src/Backend.cpp dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/gcc_revision_tested_with URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/gcc_revision_tested_with?rev=132328&r1=132327&r2=132328&view=diff ============================================================================== --- dragonegg/trunk/gcc_revision_tested_with (original) +++ dragonegg/trunk/gcc_revision_tested_with Tue May 31 02:05:50 2011 @@ -1 +1 @@ -173485 +174467 Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=132328&r1=132327&r2=132328&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Tue May 31 02:05:50 2011 @@ -1321,6 +1321,12 @@ } } +/// no_target_thunks - Hook for can_output_mi_thunk that always says "no". +static bool no_target_thunks(const_tree, HOST_WIDE_INT, HOST_WIDE_INT, + const_tree) { + return false; +} + //===----------------------------------------------------------------------===// // Plugin interface @@ -1354,6 +1360,13 @@ // Stop GCC outputting serious amounts of debug info. debug_hooks = &do_nothing_debug_hooks; + + // Adjust the target machine configuration for the fact that we are really + // targetting LLVM IR. + + // Ensure that thunks are turned into functions rather than output directly + // as assembler. + targetm.asm_out.can_output_mi_thunk = no_target_thunks; } @@ -1387,32 +1400,8 @@ } } -/// emit_function - Turn a gimple function into LLVM IR. This is called once -/// for each function in the compilation unit if GCC optimizations are disabled. -static void emit_function(struct cgraph_node *node) { - if (errorcount || sorrycount) - return; // Do not process broken code. - - tree function = node->decl; - struct function *fn = DECL_STRUCT_FUNCTION(function); - - // Set the current function to this one. - // TODO: Make it so we don't need to do this. - assert(current_function_decl == NULL_TREE && cfun == NULL && - "Current function already set!"); - current_function_decl = function; - push_cfun (fn); - - // Convert the function. - emit_current_function(); - - // Done with this function. - current_function_decl = NULL; - pop_cfun (); -} - -/// GetLinkageForAlias - The given GCC declaration is an alias or thunk. Return -/// the appropriate LLVM linkage type for it. +/// GetLinkageForAlias - The given GCC declaration is an alias. Return the +/// appropriate LLVM linkage type for it. static GlobalValue::LinkageTypes GetLinkageForAlias(tree decl) { if (DECL_COMDAT(decl)) // Need not be put out unless needed in this translation unit. @@ -1437,148 +1426,6 @@ return GlobalValue::ExternalLinkage; } -/// ApplyVirtualOffset - Adjust 'this' by a virtual offset. -static Value *ApplyVirtualOffset(Value *This, HOST_WIDE_INT virtual_value, - LLVMBuilder &Builder) { - LLVMContext &Context = getGlobalContext(); - const Type *BytePtrTy = Type::getInt8PtrTy(Context); // i8* - const Type *HandleTy = BytePtrTy->getPointerTo(); // i8** - const Type *IntPtrTy = TheTarget->getTargetData()->getIntPtrType(Context); - - // The vptr is always at offset zero in the object. - Value *VPtr = Builder.CreateBitCast(This, HandleTy->getPointerTo()); // i8*** - - // Form the vtable address. - Value *VTableAddr = Builder.CreateLoad(VPtr); // i8** - - // Find the entry with the vcall offset. - Value *VOffset = ConstantInt::get(IntPtrTy, virtual_value); - VTableAddr = Builder.CreateBitCast(VTableAddr, BytePtrTy); - VTableAddr = Builder.CreateInBoundsGEP(VTableAddr, VOffset); - VTableAddr = Builder.CreateBitCast(VTableAddr, HandleTy); // i8** - - // Get the offset itself. - Value *VCallOffset = Builder.CreateLoad(VTableAddr); // i8* - VCallOffset = Builder.CreatePtrToInt(VCallOffset, IntPtrTy); - - // Adjust the 'this' pointer. - Value *Adjusted = Builder.CreateBitCast(This, BytePtrTy); - Adjusted = Builder.CreateInBoundsGEP(Adjusted, VCallOffset); - return Builder.CreateBitCast(Adjusted, This->getType()); -} - -/// emit_thunk - Turn a thunk into LLVM IR. -static void emit_thunk(struct cgraph_node *node) { - if (errorcount || sorrycount) - return; // Do not process broken code. - - Function *Thunk = cast(DECL_LLVM(node->decl)); - if (Thunk->isVarArg()) { - sorry("thunks to varargs functions not supported"); - return; - } - - // Mark the thunk as written so gcc doesn't waste time outputting it. - TREE_ASM_WRITTEN(node->decl) = 1; - - // Set the linkage and visibility. - Thunk->setLinkage(GetLinkageForAlias(node->decl)); - handleVisibility(node->decl, Thunk); - - // Whether the thunk adjusts 'this' before calling the thunk alias (otherwise - // it is the value returned by the alias that is adjusted). - bool ThisAdjusting = node->thunk.this_adjusting; - - LLVMContext &Context = getGlobalContext(); - const Type *BytePtrTy = Type::getInt8Ty(Context)->getPointerTo(); - const Type *IntPtrTy = TheTarget->getTargetData()->getIntPtrType(Context); - LLVMBuilder Builder(Context, *TheFolder); - Builder.SetInsertPoint(BasicBlock::Create(Context, "entry", Thunk)); - - // Whether we found 'this' yet. When not 'this adjusting', setting this to - // 'true' means all parameters (including 'this') are passed through as is. - bool FoundThis = !ThisAdjusting; - - SmallVector Arguments; - for (Function::arg_iterator AI = Thunk->arg_begin(), AE = Thunk->arg_end(); - AI != AE; ++AI) { - // While 'this' is always the first GCC argument, we may have introduced - // additional artificial arguments for doing struct return or passing a - // nested function static chain. Look for 'this' while passing through - // all arguments except for 'this' unchanged. - if (FoundThis || AI->hasStructRetAttr() || AI->hasNestAttr()) { - Arguments.push_back(AI); - continue; - } - - FoundThis = true; // The current argument is 'this'. - assert(AI->getType()->isPointerTy() && "Wrong type for 'this'!"); - Value *This = AI; - - // Adjust 'this' according to the thunk offsets. First, the fixed offset. - if (node->thunk.fixed_offset) { - Value *Offset = ConstantInt::get(IntPtrTy, node->thunk.fixed_offset); - This = Builder.CreateBitCast(This, BytePtrTy); - This = Builder.CreateInBoundsGEP(This, Offset); - This = Builder.CreateBitCast(This, AI->getType()); - } - - // Then by the virtual offset, if any. - if (node->thunk.virtual_offset_p) - This = ApplyVirtualOffset(This, node->thunk.virtual_value, Builder); - - Arguments.push_back(This); - } - - CallInst *Call = Builder.CreateCall(DECL_LLVM(node->thunk.alias), - Arguments.begin(), Arguments.end()); - Call->setCallingConv(Thunk->getCallingConv()); - Call->setAttributes(Thunk->getAttributes()); - // All parameters except 'this' are passed on unchanged - this is a tail call. - Call->setTailCall(); - - if (ThisAdjusting) { - // Return the value unchanged. - if (Thunk->getReturnType()->isVoidTy()) - Builder.CreateRetVoid(); - else - Builder.CreateRet(Call); - return; - } - - // Covariant return thunk - adjust the returned value by the thunk offsets. - assert(Call->getType()->isPointerTy() && "Only know how to adjust pointers!"); - Value *RetVal = Call; - - // First check if the returned value is NULL. - Value *Zero = Constant::getNullValue(RetVal->getType()); - Value *isNull = Builder.CreateICmpEQ(RetVal, Zero); - - BasicBlock *isNullBB = BasicBlock::Create(Context, "isNull", Thunk); - BasicBlock *isNotNullBB = BasicBlock::Create(Context, "isNotNull", Thunk); - Builder.CreateCondBr(isNull, isNullBB, isNotNullBB); - - // If it is NULL, return it without any adjustment. - Builder.SetInsertPoint(isNullBB); - Builder.CreateRet(Zero); - - // Otherwise, first adjust by the virtual offset, if any. - Builder.SetInsertPoint(isNotNullBB); - if (node->thunk.virtual_offset_p) - RetVal = ApplyVirtualOffset(RetVal, node->thunk.virtual_value, Builder); - - // Then move 'this' by the fixed offset. - if (node->thunk.fixed_offset) { - Value *Offset = ConstantInt::get(IntPtrTy, node->thunk.fixed_offset); - RetVal = Builder.CreateBitCast(RetVal, BytePtrTy); - RetVal = Builder.CreateInBoundsGEP(RetVal, Offset); - RetVal = Builder.CreateBitCast(RetVal, Thunk->getReturnType()); - } - - // Return the adjusted value. - Builder.CreateRet(RetVal); -} - /// emit_alias - Given decl and target emit alias to target. static void emit_alias(tree decl, tree target) { if (errorcount || sorrycount) @@ -1686,37 +1533,30 @@ TheModule->appendModuleInlineAsm(TREE_STRING_POINTER (string)); } -/// emit_functions - Turn all functions in the compilation unit into LLVM IR. -static void emit_functions(cgraph_node_set set +/// emit_aliases - Convert same-body aliases and file-scope asm into LLVM IR. +static void emit_aliases(cgraph_node_set set #if (GCC_MINOR > 5) - , varpool_node_set /*vset*/ + , varpool_node_set /*vset*/ #endif - ) { + ) { if (errorcount || sorrycount) return; // Do not process broken code. InitializeBackend(); - // Visit each function with a body, outputting it only once (the same function - // can appear in multiple cgraph nodes due to cloning). + // Emit any same-body aliases in the order they were created. SmallPtrSet Visited; for (cgraph_node_set_iterator csi = csi_start(set); !csi_end_p(csi); csi_next(&csi)) { struct cgraph_node *node = csi_node(csi); - if (node->analyzed && Visited.insert(node->decl)) - // If GCC optimizations are enabled then functions are output later, in - // place of gimple to RTL conversion. - if (!EnableGCCOptimizations) - emit_function(node); + if (!Visited.insert(node->decl)) + continue; - // Output any same-body aliases or thunks in the order they were created. struct cgraph_node *alias, *next; for (alias = node->same_body; alias && alias->next; alias = alias->next) ; for (; alias; alias = next) { next = alias->previous; - if (alias->thunk.thunk_p) - emit_thunk(alias); - else + if (!alias->thunk.thunk_p) emit_same_body_alias(alias, node); } } @@ -1729,11 +1569,12 @@ cgraph_asm_nodes = NULL; } -/// pass_emit_functions - IPA pass that turns gimple functions into LLVM IR. -static struct ipa_opt_pass_d pass_emit_functions = { +/// pass_emit_aliases - IPA pass that converts same-body aliases and file-scope +/// asm into LLVM IR. +static struct ipa_opt_pass_d pass_emit_aliases = { { IPA_PASS, - "emit_functions", /* name */ + "emit_aliases", /* name */ gate_emission, /* gate */ NULL, /* execute */ NULL, /* sub */ @@ -1747,7 +1588,7 @@ 0 /* todo_flags_finish */ }, NULL, /* generate_summary */ - emit_functions, /* write_summary */ + emit_aliases, /* write_summary */ NULL, /* read_summary */ #if (GCC_MINOR > 5) NULL, /* write_optimization_summary */ @@ -1822,39 +1663,6 @@ NULL /* variable_transform */ }; -/// disable_rtl - Mark the current function as having been written to assembly. -static unsigned int disable_rtl(void) { - // Free any data structures. - execute_free_datastructures(); - - // Mark the function as written. - TREE_ASM_WRITTEN(current_function_decl) = 1; - - // That's all folks! - return 0; -} - -/// pass_disable_rtl - RTL pass that pretends to codegen functions, but actually -/// only does hoop jumping required by GCC. -static struct rtl_opt_pass pass_disable_rtl = -{ - { - RTL_PASS, - "disable_rtl", /* name */ - NULL, /* gate */ - disable_rtl, /* execute */ - NULL, /* sub */ - NULL, /* next */ - 0, /* static_pass_number */ - TV_NONE, /* tv_id */ - 0, /* properties_required */ - 0, /* properties_provided */ - PROP_ssa | PROP_trees, /* properties_destroyed */ - 0, /* todo_flags_start */ - 0 /* todo_flags_finish */ - } -}; - /// rtl_emit_function - Turn a gimple function into LLVM IR. This is called /// once for each function in the compilation unit if GCC optimizations are /// enabled. @@ -2390,17 +2198,16 @@ register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info); } - // Replace the LTO gimple pass. If GCC optimizations are disabled then this - // is where functions are converted to LLVM IR. When GCC optimizations are - // enabled then only aliases and thunks are output here, with functions being - // converted later after all tree optimizers have run. - pass_info.pass = &pass_emit_functions.pass; + // Replace the LTO gimple pass with a pass that converts same-body aliases and + // file-scope asm to LLVM IR. + pass_info.pass = &pass_emit_aliases.pass; pass_info.reference_pass_name = "lto_gimple_out"; pass_info.ref_pass_instance_number = 0; pass_info.pos_op = PASS_POS_REPLACE; register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info); - // Replace the LTO decls pass with conversion of global variables to LLVM IR. + // Replace the LTO decls pass with a pass that converts global variables to + // LLVM IR. pass_info.pass = &pass_emit_variables.pass; pass_info.reference_pass_name = "lto_decls_out"; pass_info.ref_pass_instance_number = 0; @@ -2476,23 +2283,12 @@ // TODO: Disable pass_warn_function_noreturn? } - // Replace rtl expansion. - if (!EnableGCCOptimizations) { - // Replace rtl expansion with a pass that pretends to codegen functions, but - // actually only does the hoop jumping that GCC requires at this point. - pass_info.pass = &pass_disable_rtl.pass; - pass_info.reference_pass_name = "expand"; - pass_info.ref_pass_instance_number = 0; - pass_info.pos_op = PASS_POS_REPLACE; - register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info); - } else { - // Replace rtl expansion with a pass that converts functions to LLVM IR. - pass_info.pass = &pass_rtl_emit_function.pass; - pass_info.reference_pass_name = "expand"; - pass_info.ref_pass_instance_number = 0; - pass_info.pos_op = PASS_POS_REPLACE; - register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info); - } + // Replace rtl expansion with a pass that converts functions to LLVM IR. + pass_info.pass = &pass_rtl_emit_function.pass; + pass_info.reference_pass_name = "expand"; + pass_info.ref_pass_instance_number = 0; + pass_info.pos_op = PASS_POS_REPLACE; + register_callback (plugin_name, PLUGIN_PASS_MANAGER_SETUP, NULL, &pass_info); // Turn off all other rtl passes. pass_info.pass = &pass_gimple_null.pass; Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=132328&r1=132327&r2=132328&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Tue May 31 02:05:50 2011 @@ -224,9 +224,13 @@ /// isLocalDecl - Whether this declaration is local to the current function. static bool isLocalDecl(tree decl) { assert(HAS_RTL_P(decl) && "Expected a declaration with RTL!"); - return DECL_CONTEXT(decl) == current_function_decl && - !TREE_STATIC(decl) && // Static variables not considered local. - TREE_CODE(decl) != FUNCTION_DECL; // Nested functions not considered local. + return + // GCC bug workaround: RESULT_DECL may not have DECL_CONTEXT set in thunks. + (!DECL_CONTEXT(decl) && TREE_CODE(decl) == RESULT_DECL) || + // Usual case. + (DECL_CONTEXT(decl) == current_function_decl && + !TREE_STATIC(decl) && // Static variables not considered local. + TREE_CODE(decl) != FUNCTION_DECL); // Nested functions not considered local. } /// set_decl_local - Remember the LLVM value for a GCC declaration. From david.majnemer at gmail.com Tue May 31 04:17:59 2011 From: david.majnemer at gmail.com (David Majnemer) Date: Tue, 31 May 2011 05:17:59 -0400 Subject: [llvm-commits] [PATCH] Implement a few missing InstCombine/InstSimplify optimizations In-Reply-To: References: <4DE48A8F.60804@free.fr> Message-ID: On Tue, May 31, 2011 at 2:53 AM, David Majnemer wrote: > Hi Duncan, > > On Tue, May 31, 2011 at 2:28 AM, Duncan Sands wrote: >> Hi David, >> >>> This patch implements a few of the optimizations mentioned in >>> http://www.nondot.org/sabre/LLVMNotes/InstCombine.txt >>> >>> specifically: >>> if ((x& ?C) == 0) x |= C ? ? ?becomes ? ? ? ? x |= C >>> if ((x& ?C) == 0) x&= ~C ? ? ?becomes ? ? ? ? nothing >>> if (((1<< ?which_alternative)& ?0x7)) becomes if (which_alternative< ?3) >>> if (!((1<< ?which_alternative)& ?0x3)) becomes if (which_alternative>= 2) >>> >>> The patch also implements slightly more powerful variations of the >>> first two, C need not be a constant. >> >> unfortunately the first one is wrong if C is not a "single bit" (power of 2). >> Consider for example >> ? if ((x & C) == 0) x |= C >> Take x = 2 and C = 3. ?Then x&C=2, so (x&C)==0 is false. ?Thus the result is >> the original value of x, namely 2. ?You propose replacing x with x|C in this >> case which is equal to 3. ?So this changes the result from 2 to 3, which is >> wrong. > You are correct, I somehow transformed this in my head to if ((x & C) > != C) x |= C, the transform must be more strict. > >> >> Also, in this bit >> >> + ? ?ConstantInt *AndCI, *And2CI; >> + ? ?// Transform: "if ((x & C) == 0) x &= ~C" ==> x &= ~C >> + ? ?if (match(AndRHS, m_ConstantInt(AndCI)) && >> + ? ? ? ?match(TrueVal, m_And(m_Specific(FalseVal), m_ConstantInt(And2CI))) && >> + ? ? ? ?AndCI == ConstantExpr::getNot(And2CI)) { >> + ? ? ?return FalseVal; >> + ? ?} >> + ? ?// Transform: "if ((x & y) == 0) x &= ~y" ==> x &= ~y >> + ? ?if (match(TrueVal, m_And(m_Specific(FalseVal), m_Not(m_Specific(AndRHS))))) { >> + ? ? ?return FalseVal; >> + ? ?} >> >> the first part should be redundant, i.e. caught by the second part. ?If it is >> not then I think you would do better to enhance m_Not to make the second part >> catch everything. > Just realized that those comments are wrong, it should be (x & y) != 0.... > > Yes, I also assumed that m_Not would match ConstantInt, however it > does not. I considering making the change you recommended but decided > that m_Not is used in quite a few places and changing the semantics of > m_Not in this way would slow it down and potentially break things. I > am guessing that most uses of m_Not that would hit ConstantInt would > be smashed away by constant folding instead of being this case... With > that in mind I am open to modifying m_Not, I just don't know how much > the consumers of that match would like it. > > With that in mind "if ((x & y) != 0) x &= ~y" ==> "x &= ~y" is wrong > while "if ((x & y) == 0) x &= ~y" ==> "x" is OK > >> >> That said, I don't much like these changes to InstructionSimplify. ?What LLVM >> needs in general and InstructionSimplify in particular is a generic machinery >> for reasoning about simple implications. ?Consider "select Cond, TV, FV". ?If >> you can prove the implication "Cond => (TV == FV)" then you can replace the >> select with FV. ?Your code above is a special case of this. ?I would rather >> see a more general infrastructure for proving implications. > Hrm, that does sound useful but it also seems like a serious reworking > of InstructionSimplify... >> >> Ciao, Duncan. >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > I have attached something that is correct save for any further issues. The only thing lingering is the mechanism to reason about simple implications... If it is necessary, a basic list of what is needed would be nice :) -- David Majnemer -------------- next part -------------- A non-text attachment was scrubbed... Name: instcombine2.patch Type: application/octet-stream Size: 5602 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110531/bf3a9cb0/attachment.obj From richard at xmos.com Tue May 31 09:00:06 2011 From: richard at xmos.com (Richard Osborne) Date: Tue, 31 May 2011 14:00:06 -0000 Subject: [llvm-commits] [llvm] r132335 - /llvm/trunk/test/CodeGen/XCore/bitrev.ll Message-ID: <20110531140006.263272A6C12C@llvm.org> Author: friedgold Date: Tue May 31 09:00:05 2011 New Revision: 132335 URL: http://llvm.org/viewvc/llvm-project?rev=132335&view=rev Log: Convert test to FileCheck. Modified: llvm/trunk/test/CodeGen/XCore/bitrev.ll Modified: llvm/trunk/test/CodeGen/XCore/bitrev.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/bitrev.ll?rev=132335&r1=132334&r2=132335&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/XCore/bitrev.ll (original) +++ llvm/trunk/test/CodeGen/XCore/bitrev.ll Tue May 31 09:00:05 2011 @@ -1,8 +1,9 @@ -; RUN: llc < %s -march=xcore > %t1.s -; RUN: grep bitrev %t1.s | count 1 +; RUN: llc < %s -march=xcore | FileCheck %s declare i32 @llvm.xcore.bitrev(i32) -define i32 @test(i32 %val) { +define i32 @bitrev(i32 %val) { +; CHECK: bitrev: +; CHECK: bitrev r0, r0 %result = call i32 @llvm.xcore.bitrev(i32 %val) ret i32 %result } From xerxes at zafena.se Tue May 31 09:12:04 2011 From: xerxes at zafena.se (Xerxes =?ISO-8859-1?Q?R=E5nby?=) Date: Tue, 31 May 2011 16:12:04 +0200 Subject: [llvm-commits] [llvm] r132135 - in /llvm/trunk/test/ExecutionEngine: 2002-12-16-ArgTest.ll 2003-01-04-ArgumentBug.ll 2003-01-04-LoopTest.ll 2003-01-15-AlignmentTest.ll 2003-05-06-LivenessClobber.ll 2003-05-07-ArgumentTest.ll 2003-08-21-Environmen In-Reply-To: References: <53F92A0F-81D4-4F48-8240-6FBE567C303F@apple.com> Message-ID: <1306851124.7244.9.camel@xranby-ESPRIMO-P7935> The reason why these tests fail on your machine are because your system are using Thumb2 and the jit are only functional in ARM mode. movw/movt are thumb2 instructions. The llvm jit runs in thumb2 mode on your machine are because lli -version report Host: thumb-unknown-linux-gnueabi The missing thumb2 implementation is a known limitation of the llvm JIT. http://llvm.org/bugs/show_bug.cgi?id=6223 The ARM JIT work when LLVM have been compiled in ARM mode and then lli -version report Host: arm-unknown-linux-gnueabi I noticed that you have marked ExecutionEngine/hello.ll as XFAIL on ARM, http://llvm.org/viewvc/llvm-project/?view=rev&revision=132135 this in not correct since the tests do pass on ARM when the jit are compiled in ARM mode. See: http://google1.osuosl.org:8011/builders/llvm-arm-linux This ARM builder test now fail because of all the added XFAILS. Cheers Xerxes tor 2011-05-26 klockan 14:42 -0700 skrev Galina Kistanova: > One of failed tests below. All in the attachment. > > Thanks > > Galina > > > ******************** TEST 'LLVM :: ExecutionEngine/hello.ll' FAILED > ********************Script: > -- > /home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/Release+Asserts/bin/lli > /home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/test/ExecutionEngine/hello.ll > > /dev/null > -- > Exit Code: 134 > Command Output (stderr): > -- > %R0Unsupported operand type for movw/movt > UNREACHABLE executed at ARMCodeEmitter.cpp:426! > Stack dump: > 0. Program arguments: > /home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/Release+Asserts/bin/lli > /home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/test/ExecutionEngine/hello.ll > 1. Running pass 'ARM Machine Code Emitter' on function '@main' > /home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/test/ExecutionEngine/Output/hello.ll.script: > line 2: 22987 Aborted > '/home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/Release+Asserts/bin/lli' > '/home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/test/ExecutionEngine/hello.ll' > > '/dev/null' > -- > > ******************** > > > > > On Thu, May 26, 2011 at 2:20 PM, Eric Christopher wrote: > > > > On May 26, 2011, at 2:15 PM, Galina Kistanova wrote: > > > >> I am about to add new builder to build clang on ARM. Some tests fail there. > >> If you need more info on failing tests, please let me know. > > > > How are the tests failing? Do you have any more information? > > > > -eric > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From richard at xmos.com Tue May 31 09:47:36 2011 From: richard at xmos.com (Richard Osborne) Date: Tue, 31 May 2011 14:47:36 -0000 Subject: [llvm-commits] [llvm] r132336 - in /llvm/trunk: include/llvm/IntrinsicsXCore.td lib/Target/XCore/XCoreInstrInfo.td test/CodeGen/XCore/bitrev.ll test/CodeGen/XCore/misc-intrinsics.ll Message-ID: <20110531144736.BCD3E2A6C12C@llvm.org> Author: friedgold Date: Tue May 31 09:47:36 2011 New Revision: 132336 URL: http://llvm.org/viewvc/llvm-project?rev=132336&view=rev Log: Add XCore intrinsic for crc32. Added: llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll - copied, changed from r132335, llvm/trunk/test/CodeGen/XCore/bitrev.ll Removed: llvm/trunk/test/CodeGen/XCore/bitrev.ll Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsXCore.td?rev=132336&r1=132335&r2=132336&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsXCore.td (original) +++ llvm/trunk/include/llvm/IntrinsicsXCore.td Tue May 31 09:47:36 2011 @@ -11,6 +11,7 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.". // Miscellaneous instructions. def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>; + def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrNoMem]>; def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>; def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>; def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>; Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=132336&r1=132335&r2=132336&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Tue May 31 09:47:36 2011 @@ -472,7 +472,13 @@ } def XOR_l3r : FL3R<"xor", xor>; defm ASHR : FL3R_L2RBITP<"ashr", sra>; -// TODO crc32, crc8, inpw, outpw + +let Constraints = "$src1 = $dst" in +def CRC_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), + "crc32 $dst, $src2, $src3", + [(set GRRegs:$dst, (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, GRRegs:$src3))]>; + +// TODO inpw, outpw let mayStore=1 in { def ST16_l3r : _FL3R<(outs), (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset), "st16 $val, $addr[$offset]", Removed: llvm/trunk/test/CodeGen/XCore/bitrev.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/bitrev.ll?rev=132335&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/XCore/bitrev.ll (original) +++ llvm/trunk/test/CodeGen/XCore/bitrev.ll (removed) @@ -1,9 +0,0 @@ -; RUN: llc < %s -march=xcore | FileCheck %s -declare i32 @llvm.xcore.bitrev(i32) - -define i32 @bitrev(i32 %val) { -; CHECK: bitrev: -; CHECK: bitrev r0, r0 - %result = call i32 @llvm.xcore.bitrev(i32 %val) - ret i32 %result -} Copied: llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll (from r132335, llvm/trunk/test/CodeGen/XCore/bitrev.ll) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll?p2=llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll&p1=llvm/trunk/test/CodeGen/XCore/bitrev.ll&r1=132335&r2=132336&rev=132336&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/XCore/bitrev.ll (original) +++ llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll Tue May 31 09:47:36 2011 @@ -1,5 +1,6 @@ ; RUN: llc < %s -march=xcore | FileCheck %s declare i32 @llvm.xcore.bitrev(i32) +declare i32 @llvm.xcore.crc32(i32, i32, i32) define i32 @bitrev(i32 %val) { ; CHECK: bitrev: @@ -7,3 +8,10 @@ %result = call i32 @llvm.xcore.bitrev(i32 %val) ret i32 %result } + +define i32 @crc32(i32 %crc, i32 %data, i32 %poly) { +; CHECK: crc32: +; CHECK: crc32 r0, r1, r2 + %result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly) + ret i32 %result +} From baldrick at free.fr Tue May 31 11:06:43 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 31 May 2011 16:06:43 -0000 Subject: [llvm-commits] [dragonegg] r132339 - in /dragonegg/trunk: include/dragonegg/Internals.h src/Convert.cpp Message-ID: <20110531160643.EB5562A6C12C@llvm.org> Author: baldrick Date: Tue May 31 11:06:43 2011 New Revision: 132339 URL: http://llvm.org/viewvc/llvm-project?rev=132339&view=rev Log: In practice VEC_RSHIFT_EXPR always shifts by a multiple of the element size, in which case it can be turned into a vector shuffle, resulting in nicer code. Modified: dragonegg/trunk/include/dragonegg/Internals.h dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/include/dragonegg/Internals.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Internals.h?rev=132339&r1=132338&r2=132339&view=diff ============================================================================== --- dragonegg/trunk/include/dragonegg/Internals.h (original) +++ dragonegg/trunk/include/dragonegg/Internals.h Tue May 31 11:06:43 2011 @@ -698,7 +698,7 @@ Value *EmitReg_RotateOp(tree_node *type, tree_node *op0, tree_node *op1, unsigned Opc1, unsigned Opc2); Value *EmitReg_ShiftOp(tree_node *op0, tree_node *op1, unsigned Opc); - Value *EmitReg_VecShiftOp(tree_node *op0, tree_node *op1, unsigned Opc); + Value *EmitReg_VecShiftOp(tree_node *op0, tree_node *op1, bool isLeftShift); Value *EmitReg_TruthOp(tree_node *type, tree_node *op0, tree_node *op1, unsigned Opc); Value *EmitReg_BIT_AND_EXPR(tree_node *op0, tree_node *op1); Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=132339&r1=132338&r2=132339&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Tue May 31 11:06:43 2011 @@ -6796,13 +6796,51 @@ return Builder.CreateBinOp((Instruction::BinaryOps)Opc, LHS, RHS); } -Value *TreeToLLVM::EmitReg_VecShiftOp(tree op0, tree op1, unsigned Opc) { +Value *TreeToLLVM::EmitReg_VecShiftOp(tree op0, tree op1, bool isLeftShift) { Value *LHS = EmitRegister(op0); // A vector. Value *Amt = EmitRegister(op1); // An integer. - const Type *VecTy = LHS->getType(); + const VectorType *VecTy = cast(LHS->getType()); + unsigned Bits = VecTy->getPrimitiveSizeInBits(); + + // If the shift is by a multiple of the element size then emit a shuffle. + if (ConstantInt *CI = dyn_cast(Amt)) { + // The GCC docs are not clear whether the bits shifted in must be zero or if + // they can be anything. Since these expressions are currently only used in + // situations which make no assumptions about the shifted in bits, we choose + // to consider them to be undefined since this results in better code. + unsigned ShiftAmt = CI->getLimitedValue(Bits); + if (ShiftAmt >= Bits) + // Shifting by more than the width of the vector is documented as giving + // an undefined result. + return UndefValue::get(VecTy); + unsigned EltBits = VecTy->getElementType()->getPrimitiveSizeInBits(); + if (!(ShiftAmt % EltBits)) { + // A shift by an integral number of elements. + unsigned EltOffset = ShiftAmt / EltBits; // Shift by this many elements. + // Shuffle the elements sideways by the appropriate number of elements. + unsigned Length = VecTy->getNumElements(); + SmallVector Mask; + Mask.reserve(Length); + const Type *Int32Ty = Type::getInt32Ty(Context); + if (isLeftShift) { + // shl <4 x i32> %v, 32 -> + // shufflevector <4 x i32> %v, <4 x i32> undef, + Mask.append(Length - EltOffset, UndefValue::get(Int32Ty)); + for (unsigned i = 0; i != EltOffset; ++i) + Mask.push_back(ConstantInt::get(Int32Ty, i)); + } else { + // shr <4 x i32> %v, 32 -> + // shufflevector <4 x i32> %v, <4 x i32> undef, <1, 2, 3, undef> + for (unsigned i = EltOffset; i != Length; ++i) + Mask.push_back(ConstantInt::get(Int32Ty, i)); + Mask.append(EltOffset, UndefValue::get(Int32Ty)); + } + return Builder.CreateShuffleVector(LHS, UndefValue::get(VecTy), + ConstantVector::get(Mask)); + } + } // Turn the vector into a mighty integer of the same size. - unsigned Bits = VecTy->getPrimitiveSizeInBits(); LHS = Builder.CreateBitCast(LHS, IntegerType::get(Context, Bits)); // Ensure the shift amount has the same type. @@ -6811,7 +6849,8 @@ Amt->getName()+".cast"); // Perform the shift. - LHS = Builder.CreateBinOp((Instruction::BinaryOps)Opc, LHS, Amt); + LHS = Builder.CreateBinOp(isLeftShift ? Instruction::Shl : Instruction::LShr, + LHS, Amt); // Turn the result back into a vector. return Builder.CreateBitCast(LHS, VecTy); @@ -8339,12 +8378,11 @@ case VEC_INTERLEAVE_LOW_EXPR: RHS = EmitReg_VEC_INTERLEAVE_LOW_EXPR(rhs1, rhs2); break; case VEC_LSHIFT_EXPR: - RHS = EmitReg_VecShiftOp(rhs1, rhs2, Instruction::Shl); break; + RHS = EmitReg_VecShiftOp(rhs1, rhs2, /*isLeftShift*/true); break; case VEC_PACK_TRUNC_EXPR: RHS = EmitReg_VEC_PACK_TRUNC_EXPR(type, rhs1, rhs2); break; case VEC_RSHIFT_EXPR: - RHS = EmitReg_VecShiftOp(rhs1, rhs2, Instruction::LShr); - break; + RHS = EmitReg_VecShiftOp(rhs1, rhs2, /*isLeftShift*/false); break; case VEC_UNPACK_HI_EXPR: RHS = EmitReg_VEC_UNPACK_HI_EXPR(type, rhs1); break; case VEC_UNPACK_LO_EXPR: From syoyofujita at gmail.com Tue May 31 11:27:37 2011 From: syoyofujita at gmail.com (Syoyo Fujita) Date: Wed, 1 Jun 2011 01:27:37 +0900 Subject: [llvm-commits] Fix sitofp and fpextend codegen for x86/AVX[PR9473] Message-ID: Attached are series of patch to fix sitofp and fpextend instruction isel for x86/AVX backend(mattr=+avx). The problem is reported here http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-March/038913.html and in bugzilla PR9473. Let me briefly explain what this patches do. sitofp instruction should be mapped to vcvtsitoss(or vcvtsitosd) assembler, and fpextend should be vcvtss2sd. These AVX instruction takes 2 input and 1 output in asm form, but for codegen(isel) form it should be 1 input and 1 output. It seems impossible to define DUMMY register in .td. So my solution is to separate .td definition into asm parser case(isAsmParserOnly=1) and codegen case(isCodeGenOnly =1) -- Syoyo -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Fix-isel-fail-for-fpext-instruction-codegen-with-x86.patch Type: application/octet-stream Size: 3187 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110601/d99d6db2/attachment.obj -------------- next part -------------- A non-text attachment was scrubbed... Name: 0002-Fix-sitofp-isel-codegen-for-x86-AVX-backend.patch Type: application/octet-stream Size: 3572 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110601/d99d6db2/attachment-0001.obj From richard at xmos.com Tue May 31 11:24:50 2011 From: richard at xmos.com (Richard Osborne) Date: Tue, 31 May 2011 16:24:50 -0000 Subject: [llvm-commits] [llvm] r132340 - in /llvm/trunk: include/llvm/IntrinsicsXCore.td lib/Target/XCore/XCoreISelDAGToDAG.cpp lib/Target/XCore/XCoreInstrInfo.td test/CodeGen/XCore/misc-intrinsics.ll Message-ID: <20110531162450.192112A6C12C@llvm.org> Author: friedgold Date: Tue May 31 11:24:49 2011 New Revision: 132340 URL: http://llvm.org/viewvc/llvm-project?rev=132340&view=rev Log: Add XCore intrinsic for crc8. Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsXCore.td?rev=132340&r1=132339&r2=132340&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsXCore.td (original) +++ llvm/trunk/include/llvm/IntrinsicsXCore.td Tue May 31 11:24:49 2011 @@ -11,6 +11,9 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.". // Miscellaneous instructions. def int_xcore_bitrev : Intrinsic<[llvm_i32_ty],[llvm_i32_ty],[IntrNoMem]>; + def int_xcore_crc8 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], + [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrNoMem]>; def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>; def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>; Modified: llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp?rev=132340&r1=132339&r2=132340&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelDAGToDAG.cpp Tue May 31 11:24:49 2011 @@ -205,6 +205,16 @@ return CurDAG->getMachineNode(XCore::LMUL_l6r, dl, MVT::i32, MVT::i32, Ops, 4); } + case ISD::INTRINSIC_WO_CHAIN: { + unsigned IntNo = cast(N->getOperand(0))->getZExtValue(); + switch (IntNo) { + case Intrinsic::xcore_crc8: + SDValue Ops[] = { N->getOperand(1), N->getOperand(2), N->getOperand(3) }; + return CurDAG->getMachineNode(XCore::CRC8_l4r, dl, MVT::i32, MVT::i32, + Ops, 3); + } + break; + } case ISD::BRIND: if (SDNode *ResNode = SelectBRIND(N)) return ResNode; Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=132340&r1=132339&r2=132340&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Tue May 31 11:24:49 2011 @@ -504,6 +504,12 @@ []>; } +let Constraints = "$src1 = $dst1" in +def CRC8_l4r : _L4R<(outs GRRegs:$dst1, GRRegs:$dst2), + (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), + "crc8 $dst1, $dst2, $src2, $src3", + []>; + // Five operand long def LADD_l5r : _L5R<(outs GRRegs:$dst1, GRRegs:$dst2), Modified: llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll?rev=132340&r1=132339&r2=132340&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll (original) +++ llvm/trunk/test/CodeGen/XCore/misc-intrinsics.ll Tue May 31 11:24:49 2011 @@ -1,6 +1,9 @@ ; RUN: llc < %s -march=xcore | FileCheck %s +%0 = type { i32, i32 } + declare i32 @llvm.xcore.bitrev(i32) declare i32 @llvm.xcore.crc32(i32, i32, i32) +declare %0 @llvm.xcore.crc8(i32, i32, i32) define i32 @bitrev(i32 %val) { ; CHECK: bitrev: @@ -15,3 +18,10 @@ %result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly) ret i32 %result } + +define %0 @crc8(i32 %crc, i32 %data, i32 %poly) { +; CHECK: crc8: +; CHECK: crc8 r0, r1, r1, r2 + %result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly) + ret %0 %result +} From richard at xmos.com Tue May 31 11:30:34 2011 From: richard at xmos.com (Richard Osborne) Date: Tue, 31 May 2011 16:30:34 -0000 Subject: [llvm-commits] [llvm] r132341 - in /llvm/trunk: include/llvm/IntrinsicsXCore.td lib/Target/XCore/XCoreInstrInfo.td Message-ID: <20110531163034.12AA92A6C12C@llvm.org> Author: friedgold Date: Tue May 31 11:30:33 2011 New Revision: 132341 URL: http://llvm.org/viewvc/llvm-project?rev=132341&view=rev Log: Fix 80 column violations. Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Modified: llvm/trunk/include/llvm/IntrinsicsXCore.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicsXCore.td?rev=132341&r1=132340&r2=132341&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicsXCore.td (original) +++ llvm/trunk/include/llvm/IntrinsicsXCore.td Tue May 31 11:30:33 2011 @@ -14,7 +14,9 @@ def int_xcore_crc8 : Intrinsic<[llvm_i32_ty, llvm_i32_ty], [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], [IntrNoMem]>; - def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrNoMem]>; + def int_xcore_crc32 : Intrinsic<[llvm_i32_ty], + [llvm_i32_ty,llvm_i32_ty,llvm_i32_ty], + [IntrNoMem]>; def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>; def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>; def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>; Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td?rev=132341&r1=132340&r2=132341&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.td Tue May 31 11:30:33 2011 @@ -474,9 +474,12 @@ defm ASHR : FL3R_L2RBITP<"ashr", sra>; let Constraints = "$src1 = $dst" in -def CRC_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), +def CRC_l3r : _FL3R<(outs GRRegs:$dst), + (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3), "crc32 $dst, $src2, $src3", - [(set GRRegs:$dst, (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, GRRegs:$src3))]>; + [(set GRRegs:$dst, + (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, + GRRegs:$src3))]>; // TODO inpw, outpw let mayStore=1 in { From aggarwa4 at illinois.edu Tue May 31 12:06:04 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 31 May 2011 17:06:04 -0000 Subject: [llvm-commits] [poolalloc] r132343 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp runtime/DynamicTypeChecks/TypeRuntime.c Message-ID: <20110531170604.AE7E72A6C12C@llvm.org> Author: aggarwa4 Date: Tue May 31 12:06:04 2011 New Revision: 132343 URL: http://llvm.org/viewvc/llvm-project?rev=132343&view=rev Log: Add a global that contains the metadata to type names map, for better output on mismatch. Also, some minor cleanup of code. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132343&r1=132342&r2=132343&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Tue May 31 12:06:04 2011 @@ -32,7 +32,10 @@ class TypeChecks : public ModulePass { private: std::map UsedTypes; - std::map VAListFunctions; + std::map VAListFunctionsMap; + std::list VAArgFunctions; + std::list VAListFunctions; + std::list ByValFunctions; // Analysis from other passes. TargetData *TD; @@ -53,6 +56,7 @@ bool initShadow(Module &M); bool unmapShadow(Module &M, Instruction &I); + void addTypeMapGlobal(Module &M) ; bool visitCallInst(Module &M, CallInst &CI); bool visitInvokeInst(Module &M, InvokeInst &CI); bool visitCallSite(Module &M, CallSite CS); Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132343&r1=132342&r2=132343&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue May 31 12:06:04 2011 @@ -77,6 +77,8 @@ UsedTypes.clear(); // Reset if run multiple times. VAListFunctions.clear(); + VAArgFunctions.clear(); + ByValFunctions.clear(); Function *MainF = M.getFunction("main"); if (MainF == 0 || MainF->isDeclaration()) { @@ -101,15 +103,43 @@ modified |= visitGlobal(M, *I, I->getInitializer(), *MainI, 0); } + // Iterate and find all byval argument functions + + // Iterate and find all varargs functions + for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { + Function &F = *MI; + if(F.isDeclaration()) + continue; + if(F.isVarArg()) { + VAArgFunctions.push_back(&F); + continue; + } + bool isVAListFunc = false; + const Type *ListType = M.getTypeByName("struct.__va_list_tag"); + if(!ListType) + continue; + + const Type *ListPtrType = ListType->getPointerTo(); + for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { + if(I->getType() == ListPtrType) { + isVAListFunc = true; + break; + } + } + if(isVAListFunc) { + VAListFunctions.push_back(&F); + continue; + } + } + + // Iterate and find all VAList functions std::vector toProcess; - std::vector toProcess1; for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; if(F.isDeclaration()) continue; // record all the original functions in the program toProcess.push_back(&F); - toProcess1.push_back(&F); // Loop over all of the instructions in the function, // adding their return type as well as the types of their operands. @@ -142,28 +172,87 @@ Function *F = toProcess.back(); toProcess.pop_back(); modified |= visitByValFunction(M, *F); + } + + // NOTE:must visit before VAArgFunctions, to populate the map with the + // correct cloned functions. + while(!VAListFunctions.empty()) { + Function *F = VAListFunctions.back(); + VAListFunctions.pop_back(); modified |= visitVAListFunction(M, *F); - // NOTE:must visit first } - + // iterate through all the VAList funtions and modify call sites // to call the new function - std::map::iterator FI = VAListFunctions.begin(), FE = VAListFunctions.end(); + std::map::iterator FI = VAListFunctionsMap.begin(), FE = VAListFunctionsMap.end(); for(; FI != FE; FI++) { visitVAListCall(FI->second); } - while(!toProcess1.empty()) { - Function *F = toProcess1.back(); - toProcess1.pop_back(); - if(F->isVarArg()) { - modified |= visitVarArgFunction(M, *F); - } + while(!VAArgFunctions.empty()) { + Function *F = VAArgFunctions.back(); + VAArgFunctions.pop_back(); + assert(F->isVarArg()); + modified |= visitVarArgFunction(M, *F); } + addTypeMapGlobal(M); numTypes += UsedTypes.size(); return modified; } + +void +TypeChecks::addTypeMapGlobal(Module &M) { + + // add a global that has the metadata -> typeString mapping + ArrayType* AType = ArrayType::get(VoidPtrTy, UsedTypes.size() + 1); + std::vector Values; + Values.reserve(UsedTypes.size() + 1); + std::vector Indices; + Indices.push_back(ConstantInt::get(Int32Ty,0)); + Indices.push_back(ConstantInt::get(Int32Ty,0)); + + // Add an entry for uninitialized(Type Number = 0) + + Constant *CA = ConstantArray::get(M.getContext(), "UNINIT", true); + GlobalVariable *GV = new GlobalVariable(M, + CA->getType(), + true, + GlobalValue::ExternalLinkage, + CA, + ""); + GV->setInitializer(CA); + Constant *C = ConstantExpr::getGetElementPtr(GV, &Indices[0], Indices.size()); + Values[0] = C; + + std::map::iterator TI = UsedTypes.begin(), TE = UsedTypes.end(); + for(;TI!=TE; ++TI) { + std::string *type = new std::string(); + llvm::raw_string_ostream *test = new llvm::raw_string_ostream(*type); + + WriteTypeSymbolic(*test, TI->first, &M); + Constant *CA = ConstantArray::get(M.getContext(), test->str(), true); + GlobalVariable *GV = new GlobalVariable(M, + CA->getType(), + true, + GlobalValue::ExternalLinkage, + CA, + ""); + GV->setInitializer(CA); + Constant *C = ConstantExpr::getGetElementPtr(GV, &Indices[0], Indices.size()); + Values[TI->second]= C; + } + + new GlobalVariable(M, + AType, + true, + GlobalValue::ExternalLinkage, + ConstantArray::get(AType, &Values[0], UsedTypes.size() + 1), + "typeNames" + ); + + return; +} void TypeChecks::visitVAListCall(Function *F) { @@ -173,7 +262,7 @@ if(!CI) continue; Function *CalledF = dyn_cast(CI->getCalledFunction()); - if(VAListFunctions.find(CalledF) == VAListFunctions.end()) + if(VAListFunctionsMap.find(CalledF) == VAListFunctionsMap.end()) continue; Function::arg_iterator NII = F->arg_begin(); std::vectorArgs; @@ -184,7 +273,7 @@ // Add the original argument Args.push_back(CI->getOperand(i)); } - CallInst *CINew = CallInst::Create(VAListFunctions[CalledF], Args.begin(), Args.end(), "", CI); + CallInst *CINew = CallInst::Create(VAListFunctionsMap[CalledF], Args.begin(), Args.end(), "", CI); CI->replaceAllUsesWith(CINew); CI->eraseFromParent(); } @@ -192,113 +281,111 @@ } bool -TypeChecks::visitVAListFunction(Module &M, Function &F_orig) { - if(!F_orig.hasInternalLinkage()) - return false; + TypeChecks::visitVAListFunction(Module &M, Function &F_orig) { + if(!F_orig.hasInternalLinkage()) + return false; - int VAListArgNum = 0; - // Check if one of the arguments is a va_list - bool isVAListFunc = false; - const Type *ListType = M.getTypeByName("struct.__va_list_tag"); - const Type *ListPtrType = ListType->getPointerTo(); - Argument *VAListArg = NULL; - for (Function::arg_iterator I = F_orig.arg_begin(), E = F_orig.arg_end(); I != E; ++I) { - VAListArgNum ++; - if(I->getType() == ListPtrType) { - VAListArg = I; - isVAListFunc = true; - break; + int VAListArgNum = 0; + // Check if one of the arguments is a va_list + const Type *ListType = M.getTypeByName("struct.__va_list_tag"); + if(!ListType) + return false; + const Type *ListPtrType = ListType->getPointerTo(); + Argument *VAListArg = NULL; + for (Function::arg_iterator I = F_orig.arg_begin(), E = F_orig.arg_end(); I != E; ++I) { + VAListArgNum ++; + if(I->getType() == ListPtrType) { + VAListArg = I; + break; + } } - } - if(!isVAListFunc) - return false; - - // Clone the function to add arguments for count, MD - - // 1. Create the new argument types vector - std::vectorTP; - TP.push_back(Int64Ty); // for count - TP.push_back(Int64Ty); // for count - TP.push_back(VoidPtrTy); // for MD - for (Function::arg_iterator I = F_orig.arg_begin(), E = F_orig.arg_end(); I != E; ++I) { - TP.push_back(I->getType()); - } - // 2. Create the new function prototype - const FunctionType *NewFTy = FunctionType::get(F_orig.getReturnType(), TP, false); - Function *F = Function::Create(NewFTy, - GlobalValue::InternalLinkage, - F_orig.getNameStr() + ".INT", - &M); - - // 3. Set the mapping for args - Function::arg_iterator NI = F->arg_begin(); - DenseMap ValueMap; - NI->setName("TotalCount"); - NI++; - NI->setName("CurrentCount"); - NI++; - NI->setName("MD"); - NI++; - for (Function::arg_iterator II = F_orig.arg_begin(); NI != F->arg_end(); ++II, ++NI) { - // Each new argument maps to the argument in the old function - // For these arguments, also copy over the attributes - ValueMap[II] = NI; - NI->setName(II->getName()); - NI->addAttr(F_orig.getAttributes().getParamAttributes(II->getArgNo() + 1)); - } - // 4. Copy over the attributes for the function. - F->setAttributes(F->getAttributes() - .addAttr(0, F_orig.getAttributes().getRetAttributes())); - F->setAttributes(F->getAttributes().addAttr(~0, F_orig.getAttributes().getFnAttributes())); + // Clone the function to add arguments for count, MD - // 5. Perform the cloning. - SmallVector Returns; - CloneFunctionInto(F, &F_orig, ValueMap, Returns); - - VAListFunctions[&F_orig] = F; - inst_iterator InsPt = inst_begin(F); - - // Store the information - Function::arg_iterator NII = F->arg_begin(); - AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt); - new StoreInst(NII, VASizeLoc, &*InsPt); - NII++; - AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt); - new StoreInst(NII, Counter, &*InsPt); - NII++; - AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt); - new StoreInst(NII, VAMDLoc, &*InsPt); - - // instrument va_arg to increment the counter - for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) { - for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { - VAArgInst *VI = dyn_cast(I++); - if(!VI) - continue; - Constant *One = ConstantInt::get(Int64Ty, 1); - LoadInst *OldValue = new LoadInst(Counter, "count", VI); - Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add, - OldValue, - One, - "count", - VI); - new StoreInst(NewValue, Counter, VI); - std::vector Args; - Instruction *VASize = new LoadInst(VASizeLoc, "", VI); - Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI); - Args.push_back(VASize); - Args.push_back(OldValue); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI->getType()))); - Args.push_back(VAMetaData); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *Func = M.getOrInsertFunction("compareTypeAndNumber", VoidTy, Int64Ty, Int64Ty, Int8Ty, VoidPtrTy, Int32Ty, NULL); - CallInst::Create(Func, Args.begin(), Args.end(), "", VI); + // 1. Create the new argument types vector + std::vectorTP; + TP.push_back(Int64Ty); // for count + TP.push_back(Int64Ty); // for count + TP.push_back(VoidPtrTy); // for MD + for (Function::arg_iterator I = F_orig.arg_begin(), E = F_orig.arg_end(); I != E; ++I) { + TP.push_back(I->getType()); + } + // 2. Create the new function prototype + const FunctionType *NewFTy = FunctionType::get(F_orig.getReturnType(), TP, false); + Function *F = Function::Create(NewFTy, + GlobalValue::InternalLinkage, + F_orig.getNameStr() + ".INT", + &M); + + // 3. Set the mapping for args + Function::arg_iterator NI = F->arg_begin(); + DenseMap ValueMap; + NI->setName("TotalCount"); + NI++; + NI->setName("CurrentCount"); + NI++; + NI->setName("MD"); + NI++; + for (Function::arg_iterator II = F_orig.arg_begin(); NI != F->arg_end(); ++II, ++NI) { + // Each new argument maps to the argument in the old function + // For these arguments, also copy over the attributes + ValueMap[II] = NI; + NI->setName(II->getName()); + NI->addAttr(F_orig.getAttributes().getParamAttributes(II->getArgNo() + 1)); + } + + // 4. Copy over the attributes for the function. + F->setAttributes(F->getAttributes() + .addAttr(0, F_orig.getAttributes().getRetAttributes())); + F->setAttributes(F->getAttributes().addAttr(~0, F_orig.getAttributes().getFnAttributes())); + + // 5. Perform the cloning. + SmallVector Returns; + CloneFunctionInto(F, &F_orig, ValueMap, Returns); + + VAListFunctionsMap[&F_orig] = F; + inst_iterator InsPt = inst_begin(F); + + // Store the information + Function::arg_iterator NII = F->arg_begin(); + AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt); + new StoreInst(NII, VASizeLoc, &*InsPt); + NII++; + AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt); + new StoreInst(NII, Counter, &*InsPt); + NII++; + AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt); + new StoreInst(NII, VAMDLoc, &*InsPt); + + // instrument va_arg to increment the counter + for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) { + for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { + VAArgInst *VI = dyn_cast(I++); + if(!VI) + continue; + Constant *One = ConstantInt::get(Int64Ty, 1); + LoadInst *OldValue = new LoadInst(Counter, "count", VI); + Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add, + OldValue, + One, + "count", + VI); + new StoreInst(NewValue, Counter, VI); + std::vector Args; + Instruction *VASize = new LoadInst(VASizeLoc, "", VI); + Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI); + Args.push_back(VASize); + Args.push_back(OldValue); + Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI->getType()))); + Args.push_back(VAMetaData); + Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Constant *Func = M.getOrInsertFunction("compareTypeAndNumber", VoidTy, Int64Ty, Int64Ty, Int8Ty, VoidPtrTy, Int32Ty, NULL); + CallInst::Create(Func, Args.begin(), Args.end(), "", VI); + } } - } -return true; -} + return true; + } // Transform Variable Argument functions, by also passing // the relavant metadata info @@ -419,7 +506,7 @@ if(!CI) continue; Function *CalledF = dyn_cast(CI->getCalledFunction()); - if(VAListFunctions.find(CalledF) == VAListFunctions.end()) + if(VAListFunctionsMap.find(CalledF) == VAListFunctionsMap.end()) continue; std::vectorArgs; Instruction *VASize = new LoadInst(VASizeLoc, "", CI); @@ -432,7 +519,7 @@ // Add the original argument Args.push_back(CI->getOperand(i)); } - CallInst *CINew = CallInst::Create(VAListFunctions[CalledF], Args.begin(), Args.end(), "", CI); + CallInst *CINew = CallInst::Create(VAListFunctionsMap[CalledF], Args.begin(), Args.end(), "", CI); CI->replaceAllUsesWith(CINew); CI->eraseFromParent(); } Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=132343&r1=132342&r2=132343&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Tue May 31 12:06:04 2011 @@ -19,6 +19,8 @@ uint8_t *shadow_begin; uint8_t *shadow_end; +extern char* typeNames[]; + void trackInitInst(void *ptr, uint64_t size, uint32_t tag); uintptr_t maskAddress(void *ptr) { @@ -116,7 +118,7 @@ */ void compareTypes(uint8_t typeNumberSrc, uint8_t typeNumberDest, uint32_t tag) { if(typeNumberSrc != typeNumberDest) { - printf("Type mismatch: detecting %u, expecting %u! %u \n", typeNumberDest, typeNumberSrc, tag); + printf("Type mismatch: detecting %u, expecting %u! %u %s, %s\n", typeNumberDest, typeNumberSrc, tag, typeNames[typeNumberDest], typeNames[typeNumberSrc]); } } @@ -150,9 +152,8 @@ /* Check if this an initialized but untyped memory.*/ if (typeNumber != shadow_begin[p]) { if (shadow_begin[p] != 0xFF) { - - printf("Type mismatch: detecting %p %u, expecting %u! %u \n", ptr, typeNumber, shadow_begin[p], tag); - i = size; + printf("Type mismatch: detecting %u, expecting %u! %u %s %s\n", typeNumber, shadow_begin[p], tag, typeNames[typeNumber], typeNames[shadow_begin[p]]); + return; } else { /* If so, set type to the type being read. Check that none of the bytes are typed.*/ From bruno.cardoso at gmail.com Tue May 31 12:23:06 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 May 2011 14:23:06 -0300 Subject: [llvm-commits] Fix sitofp and fpextend codegen for x86/AVX[PR9473] In-Reply-To: References: Message-ID: Hi Syoyo, On Tue, May 31, 2011 at 1:27 PM, Syoyo Fujita wrote: > Attached are series of patch to fix sitofp and fpextend instruction > isel for x86/AVX backend(mattr=+avx). > > The problem is reported here > > http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-March/038913.html > > and in bugzilla PR9473. > > > Let me briefly explain what this patches do. > > sitofp instruction should be mapped to vcvtsitoss(or vcvtsitosd) > assembler, and fpextend should be vcvtss2sd. > These AVX instruction takes 2 input and 1 output in asm form, but for > codegen(isel) form it should be 1 input and 1 output. > It seems impossible to define DUMMY register in .td. > > So my solution is to separate .td definition into asm parser > case(isAsmParserOnly=1) and codegen case(isCodeGenOnly =1) >From the intel manual: VCVTSS2SD- Convert one single-precision floating-point value in xmm3/m32 to one double-precision floating- point value and merge with high bits of xmm2. And, according to your patch: +let isAsmParserOnly = 1 in { + def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), + (ins FR32:$src1, f32mem:$src2), + "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", + []>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>; +} + +def VCVTSS2SDrm_alt : I<0x5A, MRMSrcMem, (outs FR64:$dst), + (ins f32mem:$src), + "vcvtss2sd\t{$src, $src, $dst|$dst, $src, $src}", + []>, XS, VEX, Requires<[HasAVX, OptForSize]>; The "alt" version is using a different encoding, this isn't correct, since there's only one encoding for the "rm" version, which is the "VEX_4V" one. There is no need for the "alt" version actually, but to follow the manual "merge with high bits of xmm2": Instead of doing: +def : Pat<(extloadf32 addr:$src), + (VCVTSS2SDrm_alt addr:$src)>, You can do: def : Pat<(extloadf32 addr:$src2), (VCVTSS2SDrm 0, addr:$src2)>, or something like that... A better solution, since this instruction is dealing with F32 reg classes and the high bits won't be touched, is to declare VCVTSS2SDrm as having Constraints = "$src1 = $dst", but keep printing its operands as usual. Also, you can do the pattern matching inline in the instruction definition, no need to do it as a Pat here. I believe you can do something similar to VCVTSI2SD_alt. -- Bruno Cardoso Lopes http://www.brunocardoso.cc From dpatel at apple.com Tue May 31 12:45:27 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 May 2011 17:45:27 -0000 Subject: [llvm-commits] [llvm] r132344 - /llvm/trunk/docs/SourceLevelDebugging.html Message-ID: <20110531174527.D85C72A6C12C@llvm.org> Author: dpatel Date: Tue May 31 12:45:27 2011 New Revision: 132344 URL: http://llvm.org/viewvc/llvm-project?rev=132344&view=rev Log: Clarify documentation and remove guarantees that are not fulfilled. Modified: llvm/trunk/docs/SourceLevelDebugging.html Modified: llvm/trunk/docs/SourceLevelDebugging.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=132344&r1=132343&r2=132344&view=diff ============================================================================== --- llvm/trunk/docs/SourceLevelDebugging.html (original) +++ llvm/trunk/docs/SourceLevelDebugging.html Tue May 31 12:45:27 2011 @@ -174,22 +174,15 @@ as setting program variables, or calling functions that have been deleted. -
  • LLVM optimizations gracefully interact with debugging information. If - they are not aware of debug information, they are automatically disabled - as necessary in the cases that would invalidate the debug info. This - retains the LLVM features, making it easy to write new - transformations.
    • -
  • As desired, LLVM optimizations can be upgraded to be aware of the LLVM debugging information, allowing them to update the debugging information as they perform aggressive optimizations. This means that, with effort, the LLVM optimizers could optimize debug code just as well as non-debug code.
    • -
  • LLVM debug information does not prevent many important optimizations from +
  • LLVM debug information does not prevent optimizations from happening (for example inlining, basic block reordering/merging/cleanup, - tail duplication, etc), further reducing the amount of the compiler that - eventually is "aware" of debugging information.
    • + tail duplication, etc).
  • LLVM debug information is automatically optimized along with the rest of the program, using existing facilities. For example, duplicate From dpatel at apple.com Tue May 31 13:06:14 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 May 2011 18:06:14 -0000 Subject: [llvm-commits] [llvm] r132345 - /llvm/trunk/docs/SourceLevelDebugging.html Message-ID: <20110531180614.9BB732A6C12C@llvm.org> Author: dpatel Date: Tue May 31 13:06:14 2011 New Revision: 132345 URL: http://llvm.org/viewvc/llvm-project?rev=132345&view=rev Log: Fix html formatting. Modified: llvm/trunk/docs/SourceLevelDebugging.html Modified: llvm/trunk/docs/SourceLevelDebugging.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/SourceLevelDebugging.html?rev=132345&r1=132344&r2=132345&view=diff ============================================================================== --- llvm/trunk/docs/SourceLevelDebugging.html (original) +++ llvm/trunk/docs/SourceLevelDebugging.html Tue May 31 13:06:14 2011 @@ -182,7 +182,7 @@
  • LLVM debug information does not prevent optimizations from happening (for example inlining, basic block reordering/merging/cleanup, - tail duplication, etc).
  • + tail duplication, etc).
  • LLVM debug information is automatically optimized along with the rest of the program, using existing facilities. For example, duplicate From aggarwa4 at illinois.edu Tue May 31 14:14:57 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 31 May 2011 19:14:57 -0000 Subject: [llvm-commits] [poolalloc] r132346 - in /poolalloc/trunk: include/dsa/TypeSafety.h lib/DSA/TypeSafety.cpp Message-ID: <20110531191457.809E42A6C12C@llvm.org> Author: aggarwa4 Date: Tue May 31 14:14:57 2011 New Revision: 132346 URL: http://llvm.org/viewvc/llvm-project?rev=132346&view=rev Log: Allow checking of typesafety of globals, without specifying a function context. Modified: poolalloc/trunk/include/dsa/TypeSafety.h poolalloc/trunk/lib/DSA/TypeSafety.cpp Modified: poolalloc/trunk/include/dsa/TypeSafety.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/dsa/TypeSafety.h?rev=132346&r1=132345&r2=132346&view=diff ============================================================================== --- poolalloc/trunk/include/dsa/TypeSafety.h (original) +++ poolalloc/trunk/include/dsa/TypeSafety.h Tue May 31 14:14:57 2011 @@ -43,6 +43,7 @@ protected: // Methods DSNodeHandle getDSNodeHandle (const Value * V, const Function * F); + DSNodeHandle getDSNodeHandle (const GlobalValue * V); void findTypeSafeDSNodes (const DSGraph * Graph); bool isTypeSafe (const DSNode * N); bool typeFieldsOverlap (const DSNode * N); @@ -76,6 +77,7 @@ // Methods for clients to use virtual bool isTypeSafe (const Value * V, const Function * F); + virtual bool isTypeSafe (const GlobalValue * V); }; } Modified: poolalloc/trunk/lib/DSA/TypeSafety.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/TypeSafety.cpp?rev=132346&r1=132345&r2=132346&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/TypeSafety.cpp (original) +++ poolalloc/trunk/lib/DSA/TypeSafety.cpp Tue May 31 14:14:57 2011 @@ -43,6 +43,47 @@ // Method: getDSNodeHandle() // // Description: +// This method looks up the DSNodeHandle for a given LLVM globalvalue. +// The value is looked up in the globals graph +// +// Return value: +// A DSNodeHandle for the value is returned. This DSNodeHandle is from +// the GlobalsGraph. Note that the DSNodeHandle may represent a NULL DSNode. +// +template DSNodeHandle +TypeSafety::getDSNodeHandle(const GlobalValue *V) { + DSNodeHandle DSH; + const DSGraph * GlobalsGraph = dsaPass->getGlobalsGraph (); + if(GlobalsGraph->hasNodeForValue(V)) { + DSH = GlobalsGraph->getNodeForValue(V); + } + // + // Try looking up this DSNode value in the globals graph. Note that + // globals are put into equivalence classes; we may need to first find the + // equivalence class to which our global belongs, find the global that + // represents all globals in that equivalence class, and then look up the + // DSNode Handle for *that* global. + // + if (DSH.isNull()) { + // + // DSA does not currently handle global aliases. + // + if (!isa(V)) { + // + // We have to dig into the globalEC of the DSGraph to find the DSNode. + // + const GlobalValue * GV = dyn_cast(V); + const GlobalValue * Leader; + Leader = GlobalsGraph->getGlobalECs().getLeaderValue(GV); + DSH = GlobalsGraph->getNodeForValue(Leader); + } + } + return DSH; +} + +// Method: getDSNodeHandle() +// +// Description: // This method looks up the DSNodeHandle for a given LLVM value. The context // of the value is the specified function, although if it is a global value, // the DSNodeHandle may exist within the global DSGraph. @@ -63,7 +104,7 @@ // Lookup the DSNode for the value in the function's DSGraph. // const DSGraph * TDG = dsaPass->getDSGraph(*F); - + DSNodeHandle DSH; if(TDG->hasNodeForValue(V)) DSH = TDG->getNodeForValue(V); @@ -80,24 +121,7 @@ // represents all globals in that equivalence class, and then look up the // DSNode Handle for *that* global. // - const DSGraph * GlobalsGraph = TDG->getGlobalsGraph (); - if(GlobalsGraph->hasNodeForValue(V)) { - DSH = GlobalsGraph->getNodeForValue(V); - } - if (DSH.isNull()) { - // - // DSA does not currently handle global aliases. - // - if (!isa(V)) { - // - // We have to dig into the globalEC of the DSGraph to find the DSNode. - // - const GlobalValue * GV = dyn_cast(V); - const GlobalValue * Leader; - Leader = GlobalsGraph->getGlobalECs().getLeaderValue(GV); - DSH = GlobalsGraph->getNodeForValue(Leader); - } - } + DSH = getDSNodeHandle(cast(V)); } return DSH; } @@ -125,6 +149,28 @@ return false; } +template bool +TypeSafety::isTypeSafe(const GlobalValue *V) { + // + // Get the DSNode for the specified value. + // + DSNodeHandle DH = getDSNodeHandle(V); + + // + // If there is no DSNode, claim that it is not typesafe. + // + if (DH.isNull()) + return false; + + // + // See if the DSNode is one that we think is type-safe. + // + if (TypeSafeNodes.count (DH.getNode())) + return true; + + return false; +} + // // Method: typeFieldsOverlap() // From aggarwa4 at illinois.edu Tue May 31 14:16:53 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 31 May 2011 19:16:53 -0000 Subject: [llvm-commits] [poolalloc] r132347 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110531191653.71E752A6C12C@llvm.org> Author: aggarwa4 Date: Tue May 31 14:16:53 2011 New Revision: 132347 URL: http://llvm.org/viewvc/llvm-project?rev=132347&view=rev Log: 1. Code clean up. 2. Move code to register globals into the global ctor. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132347&r1=132346&r2=132347&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue May 31 14:16:53 2011 @@ -92,28 +92,21 @@ // record argv modified |= visitMain(M, *MainF); - // record all globals - inst_iterator MainI = inst_begin(MainF); - for (Module::global_iterator I = M.global_begin(), E = M.global_end(); - I != E; ++I) { - if(!I->getNumUses() == 1) - continue; - if(!I->hasInitializer()) - continue; - modified |= visitGlobal(M, *I, I->getInitializer(), *MainI, 0); - } - - // Iterate and find all byval argument functions - - // Iterate and find all varargs functions for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; if(F.isDeclaration()) continue; + + std::string name = F.getName(); + + if (strncmp(name.c_str(), "tc.", 3) == 0) continue; + + // Iterate and find all varargs functions if(F.isVarArg()) { VAArgFunctions.push_back(&F); continue; } + // Iterate and find all VAList functions bool isVAListFunc = false; const Type *ListType = M.getTypeByName("struct.__va_list_tag"); if(!ListType) @@ -132,7 +125,6 @@ } } - // Iterate and find all VAList functions std::vector toProcess; for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; @@ -173,7 +165,7 @@ toProcess.pop_back(); modified |= visitByValFunction(M, *F); } - + // NOTE:must visit before VAArgFunctions, to populate the map with the // correct cloned functions. while(!VAListFunctions.empty()) { @@ -200,9 +192,8 @@ return modified; } - -void -TypeChecks::addTypeMapGlobal(Module &M) { + +void TypeChecks::addTypeMapGlobal(Module &M) { // add a global that has the metadata -> typeString mapping ArrayType* AType = ArrayType::get(VoidPtrTy, UsedTypes.size() + 1); @@ -254,8 +245,7 @@ return; } -void -TypeChecks::visitVAListCall(Function *F) { +void TypeChecks::visitVAListCall(Function *F) { for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) { for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { CallInst *CI = dyn_cast(I++); @@ -280,8 +270,7 @@ } } -bool - TypeChecks::visitVAListFunction(Module &M, Function &F_orig) { + bool TypeChecks::visitVAListFunction(Module &M, Function &F_orig) { if(!F_orig.hasInternalLinkage()) return false; @@ -389,8 +378,7 @@ // Transform Variable Argument functions, by also passing // the relavant metadata info -bool -TypeChecks::visitVarArgFunction(Module &M, Function &F) { +bool TypeChecks::visitVarArgFunction(Module &M, Function &F) { if(F.hasInternalLinkage()) { return visitInternalVarArgFunction(M, F); } @@ -425,8 +413,7 @@ // Aside from this, this function also transforms all // callsites of the var_arg function. -bool -TypeChecks::visitInternalVarArgFunction(Module &M, Function &F) { +bool TypeChecks::visitInternalVarArgFunction(Module &M, Function &F) { inst_iterator InsPt = inst_begin(F); @@ -462,7 +449,13 @@ Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI->getType()))); Args.push_back(VAMetaData); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *Func = M.getOrInsertFunction("compareTypeAndNumber", VoidTy, Int64Ty, Int64Ty, Int8Ty, VoidPtrTy, Int32Ty, NULL); + Constant *Func = M.getOrInsertFunction("compareTypeAndNumber", + VoidTy, + Int64Ty, + Int64Ty, + Int8Ty, + VoidPtrTy, + Int32Ty, NULL); CallInst::Create(Func, Args.begin(), Args.end(), "", VI); } } @@ -519,7 +512,8 @@ // Add the original argument Args.push_back(CI->getOperand(i)); } - CallInst *CINew = CallInst::Create(VAListFunctionsMap[CalledF], Args.begin(), Args.end(), "", CI); + CallInst *CINew = CallInst::Create(VAListFunctionsMap[CalledF], + Args.begin(), Args.end(), "", CI); CI->replaceAllUsesWith(CINew); CI->eraseFromParent(); } @@ -545,8 +539,13 @@ Value *Idx[2]; Idx[0] = ConstantInt::get(Int32Ty, j++); // For each vararg argument, also add its type information before it - GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, Idx, Idx + 1, "", CI); - new StoreInst(ConstantInt::get(Int8Ty, getTypeMarker(CI->getOperand(i)->getType())), GEP, CI); + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, + Idx, + Idx + 1, + "", CI); + Constant *C = ConstantInt::get(Int8Ty, + getTypeMarker(CI->getOperand(i)->getType())); + new StoreInst(C, GEP, CI); } for(i = 1 ;i < CI->getNumOperands(); i++) { @@ -561,15 +560,16 @@ } // Create the new call - CallInst *CI_New = CallInst::Create(CI->getCalledValue(), Args.begin(), Args.end(), "", CI); + CallInst *CI_New = CallInst::Create(CI->getCalledValue(), + Args.begin(), Args.end(), + "", CI); CI->replaceAllUsesWith(CI_New); CI->eraseFromParent(); } return true; } -bool -TypeChecks::visitByValFunction(Module &M, Function &F) { +bool TypeChecks::visitByValFunction(Module &M, Function &F) { // check for byval arguments bool hasByValArg = false; @@ -679,7 +679,10 @@ Args.push_back(BCI_Src); Args.push_back(AllocSize); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("copyTypeInfo", VoidTy, VoidPtrTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); + Constant *F = M.getOrInsertFunction("copyTypeInfo", + VoidTy, + VoidPtrTy, VoidPtrTy, Int64Ty, Int32Ty, + NULL); CallInst::Create(F, Args.begin(), Args.end(), "", InsertBefore); } } @@ -839,8 +842,26 @@ bool TypeChecks::initShadow(Module &M) { // Create the call to the runtime initialization function and place it before the store instruction. - Constant * RuntimeCtor = M.getOrInsertFunction("shadowInit", VoidTy, NULL); + Constant * RuntimeCtor = M.getOrInsertFunction("tc.init", VoidTy, NULL); + Constant * InitFn = M.getOrInsertFunction("shadowInit", VoidTy, NULL); + + //RuntimeCtor->setDoesNotThrow(); + //RuntimeCtor->setLinkage(GlobalValue::InternalLinkage); + + BasicBlock *BB = BasicBlock::Create(M.getContext(), "entry", cast(RuntimeCtor)); + CallInst::Create(InitFn, "", BB); + Instruction *InsertPt = ReturnInst::Create(M.getContext(), BB); + + // record all globals + for (Module::global_iterator I = M.global_begin(), E = M.global_end(); + I != E; ++I) { + if(I->use_empty()) + continue; + if(!I->hasInitializer()) + continue; + visitGlobal(M, *I, I->getInitializer(), *InsertPt, 0); + } // // Insert the run-time ctor into the ctor list. // @@ -932,10 +953,8 @@ bool TypeChecks::visitGlobal(Module &M, GlobalVariable &GV, Constant *C, Instruction &I, unsigned offset) { - // FIXME:This should maybe move into the global ctor. - if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(&GV, I.getParent()->getParent())) { + if(TS->isTypeSafe(&GV)) { return false; } } @@ -1105,6 +1124,7 @@ // Value *Callee = CS.getCalledValue()->stripPointerCasts(); Instruction *I = CS.getInstruction(); + Function *Caller = I->getParent()->getParent(); // Special case handling of certain libc allocation functions here. if (Function *F = dyn_cast(Callee)) { @@ -1114,7 +1134,7 @@ case Intrinsic::memmove: { if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(2), I->getParent()->getParent())) { + if(TS->isTypeSafe(I->getOperand(2), Caller)) { return false; } } @@ -1132,7 +1152,7 @@ case Intrinsic::memset: if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(1), I->getParent()->getParent())) { + if(TS->isTypeSafe(I->getOperand(1), Caller)) { return false; } } @@ -1171,7 +1191,7 @@ CallInst::Create(F, Args.begin(), Args.end(), "", I); } else if(F->getNameStr() == std::string("ftime")) { if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(1), I->getParent()->getParent())) { + if(TS->isTypeSafe(I->getOperand(1), Caller)) { return false; } } @@ -1188,7 +1208,7 @@ return true; } else if(F->getNameStr() == std::string("read")) { if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(2), I->getParent()->getParent())) { + if(TS->isTypeSafe(I->getOperand(2), Caller)) { return false; } } @@ -1204,7 +1224,7 @@ return true; } else if(F->getNameStr() == std::string("fread")) { if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(1), I->getParent()->getParent())) { + if(TS->isTypeSafe(I->getOperand(1), Caller)) { return false; } } @@ -1220,7 +1240,7 @@ return true; } else if(F->getNameStr() == std::string("calloc")) { if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I, I->getParent()->getParent())) { + if(TS->isTypeSafe(I, Caller)) { return false; } } @@ -1244,7 +1264,7 @@ return true; } else if(F->getNameStr() == std::string("realloc")) { if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I, I->getParent()->getParent())) { + if(TS->isTypeSafe(I, Caller)) { return false; } } @@ -1263,7 +1283,7 @@ return true; } else if(F->getNameStr() == std::string("fgets")) { if(EnableTypeSafeOpt) { - if(TS->isTypeSafe(I->getOperand(1), I->getParent()->getParent())) { + if(TS->isTypeSafe(I->getOperand(1), Caller)) { return true; } } From stuart at apple.com Tue May 31 14:29:55 2011 From: stuart at apple.com (Stuart Hastings) Date: Tue, 31 May 2011 19:29:55 -0000 Subject: [llvm-commits] [llvm] r132348 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Message-ID: <20110531192955.A7C392A6C12C@llvm.org> Author: stuart Date: Tue May 31 14:29:55 2011 New Revision: 132348 URL: http://llvm.org/viewvc/llvm-project?rev=132348&view=rev Log: Followup to 132316; accept arbitrary constants, add with a constant, sub with a non-constant. Fix comments, enlarge test case. rdar://problem/6501862 Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=132348&r1=132347&r2=132348&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Tue May 31 14:29:55 2011 @@ -136,19 +136,26 @@ } } - // (1 - X) * (-2) -> (x - 1) * 2, for all positive nonzero powers of 2 - // The "* 2" thus becomes a potential shifting opportunity. + // (Y - X) * (-(2**n)) -> (X - Y) * (2**n), for positive nonzero n + // (Y + const) * (-(2**n)) -> (-constY) * (2**n), for positive nonzero n + // The "* (2**n)" thus becomes a potential shifting opportunity. { const APInt & Val = CI->getValue(); const APInt &PosVal = Val.abs(); if (Val.isNegative() && PosVal.isPowerOf2()) { - Value *X = 0; - if (match(Op0, m_Sub(m_One(), m_Value(X)))) { - // ConstantInt::get(Op0->getType(), 2); - Value *Sub = Builder->CreateSub(X, ConstantInt::get(X->getType(), 1), - "dec1"); - return BinaryOperator::CreateMul(Sub, ConstantInt::get(X->getType(), - PosVal)); + Value *X = 0, *Y = 0; + ConstantInt *C1 = 0; + if (Op0->hasOneUse() && + (match(Op0, m_Sub(m_Value(Y), m_Value(X)))) || + (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1))))) { + Value *Sub; + if (C1) // Matched ADD of constant, negate both operands: + Sub = Builder->CreateSub(Builder->CreateNeg(C1), Y, "subc"); + else // Matched SUB, swap operands: + Sub = Builder->CreateSub(X, Y, "suba"); + return + BinaryOperator::CreateMul(Sub, + ConstantInt::get(X->getType(), PosVal)); } } } Modified: llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll?rev=132348&r1=132347&r2=132348&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Tue May 31 14:29:55 2011 @@ -2,18 +2,14 @@ ; RUN: opt -S -instcombine < %s | FileCheck %s target triple = "x86_64-apple-macosx10.6.6" -define zeroext i16 @foo(i32 %on_off, i16* %puls) nounwind uwtable ssp { +define zeroext i16 @foo1(i32 %on_off) nounwind uwtable ssp { entry: %on_off.addr = alloca i32, align 4 - %puls.addr = alloca i16*, align 8 %a = alloca i32, align 4 store i32 %on_off, i32* %on_off.addr, align 4 - store i16* %puls, i16** %puls.addr, align 8 %tmp = load i32* %on_off.addr, align 4 -; CHECK-NOT: sub -; CHECK-NOT: mul -; (1 - %tmp) * (-2) -> (%tmp - 1) * 2 %sub = sub i32 1, %tmp +; CHECK-NOT: mul i32 %mul = mul i32 %sub, -2 ; CHECK: shl ; CHECK-NEXT: add @@ -22,3 +18,40 @@ %conv = trunc i32 %tmp1 to i16 ret i16 %conv } + +define zeroext i16 @foo2(i32 %on_off, i32 %q) nounwind uwtable ssp { +entry: + %on_off.addr = alloca i32, align 4 + %q.addr = alloca i32, align 4 + %a = alloca i32, align 4 + store i32 %on_off, i32* %on_off.addr, align 4 + store i32 %q, i32* %q.addr, align 4 + %tmp = load i32* %q.addr, align 4 + %tmp1 = load i32* %on_off.addr, align 4 + %sub = sub i32 %tmp, %tmp1 +; CHECK-NOT: mul i32 + %mul = mul i32 %sub, -4 +; CHECK: sub i32 +; CHECK-NEXT: shl + store i32 %mul, i32* %a, align 4 + %tmp2 = load i32* %a, align 4 + %conv = trunc i32 %tmp2 to i16 + ret i16 %conv +} + +define zeroext i16 @foo3(i32 %on_off) nounwind uwtable ssp { +entry: + %on_off.addr = alloca i32, align 4 + %a = alloca i32, align 4 + store i32 %on_off, i32* %on_off.addr, align 4 + %tmp = load i32* %on_off.addr, align 4 + %sub = sub i32 7, %tmp +; CHECK-NOT: mul i32 + %mul = mul i32 %sub, -4 +; CHECK: shl +; CHECK-NEXT: add + store i32 %mul, i32* %a, align 4 + %tmp1 = load i32* %a, align 4 + %conv = trunc i32 %tmp1 to i16 + ret i16 %conv +} From stuart at apple.com Tue May 31 14:37:42 2011 From: stuart at apple.com (Stuart Hastings) Date: Tue, 31 May 2011 12:37:42 -0700 Subject: [llvm-commits] [llvm] r132316 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/Transforms/InstCombine/2011-05-28-swapmulsub.ll In-Reply-To: <4DE3FBCF.7080903@free.fr> References: <20110530200034.07AEE2A6C12C@llvm.org> <4DE3FBCF.7080903@free.fr> Message-ID: <40F7D364-8D0B-4D65-937D-A1402B86B0BD@apple.com> Agreed. Followup patch at 132348. Thank you both for the reviews, stuart On May 30, 2011, at 1:19 PM, Duncan Sands wrote: > Hi Stuart, > >> @@ -135,6 +135,23 @@ >> return BinaryOperator::CreateAdd(Add, Builder->CreateMul(C1, CI)); >> } >> } >> + >> + // (1 - X) * (-2) -> (x - 1) * 2, for all positive nonzero powers of 2 > > the big X becomes a little x later in the comment. It is not clear that the > power of 2 comment is about 2 rather than about X. > >> + // The "* 2" thus becomes a potential shifting opportunity. >> + { >> + const APInt& Val = CI->getValue(); >> + const APInt&PosVal = Val.abs(); >> + if (Val.isNegative()&& PosVal.isPowerOf2()) { > > You should also check that Op0, aka (1-X), has only one use. Also, why does it > matter that it is "1-X" specifically? Surely "Constant - X", "X - Constant", > "Constant+X" and "X-Constant" are also fine, since you don't increase the > amount of computation in any of these when you push the "*(-1)" into them? > >> + Value *X = 0; >> + if (match(Op0, m_Sub(m_One(), m_Value(X)))) { >> + // ConstantInt::get(Op0->getType(), 2); > > No need for this commented out line... > > Ciao, Duncan. > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > On Mon, May 30, 2011 at 10:19 PM, Duncan Sands wrote: >>> + // The "* 2" thus becomes a potential shifting opportunity. >>> + { >>> + const APInt& Val = CI->getValue(); >>> + const APInt&PosVal = Val.abs(); >>> + if (Val.isNegative()&& PosVal.isPowerOf2()) { >> >> You should also check that Op0, aka (1-X), has only one use. Also, why does it >> matter that it is "1-X" specifically? Surely "Constant - X", "X - Constant", >> "Constant+X" and "X-Constant" are also fine, since you don't increase the >> amount of computation in any of these when you push the "*(-1)" into them? > > You mentioned "X-Constant" twice, but you probably meant "X+Constant" > the second time. > > There's no need to match "Constant+X", since it will be turned into > "X+Constant" by other parts of instcombine. > > I also don't think that for the subtraction case you even need either > one to be a constant at all. -(X-Y) == (Y-X) even for non-constant X > and Y. > > That leaves just the cases "(X-Y)*-PowerOfTwo" and > "(X+Constant)*-PowerOfTwo" to consider. > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From nicholas at mxc.ca Tue May 31 14:53:26 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 31 May 2011 19:53:26 -0000 Subject: [llvm-commits] [llvm] r132349 - /llvm/trunk/tools/gold/Makefile Message-ID: <20110531195326.4ED8F2A6C12C@llvm.org> Author: nicholas Date: Tue May 31 14:53:26 2011 New Revision: 132349 URL: http://llvm.org/viewvc/llvm-project?rev=132349&view=rev Log: Make the gold plugin build on Cygwin as well as Linux. Patch by David Meyer! Modified: llvm/trunk/tools/gold/Makefile Modified: llvm/trunk/tools/gold/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/Makefile?rev=132349&r1=132348&r2=132349&view=diff ============================================================================== --- llvm/trunk/tools/gold/Makefile (original) +++ llvm/trunk/tools/gold/Makefile Tue May 31 14:53:26 2011 @@ -22,10 +22,10 @@ LOADABLE_MODULE = 1 LINK_COMPONENTS := support -LIBS += -llto # Because off_t is used in the public API, the largefile parts are required for # ABI compatibility. CXXFLAGS+=-I$(BINUTILS_INCDIR) -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -lLTO +CXXFLAGS+=$(SharedLibDir)/$(SharedPrefix)LTO$(SHLIBEXT) include $(LEVEL)/Makefile.common From stuart at apple.com Tue May 31 14:56:35 2011 From: stuart at apple.com (Stuart Hastings) Date: Tue, 31 May 2011 19:56:35 -0000 Subject: [llvm-commits] [llvm] r132351 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Message-ID: <20110531195635.4EE902A6C12C@llvm.org> Author: stuart Date: Tue May 31 14:56:35 2011 New Revision: 132351 URL: http://llvm.org/viewvc/llvm-project?rev=132351&view=rev Log: Revert to pacify a buildbot. rdar://problem/6501862 Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=132351&r1=132350&r2=132351&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Tue May 31 14:56:35 2011 @@ -136,26 +136,19 @@ } } - // (Y - X) * (-(2**n)) -> (X - Y) * (2**n), for positive nonzero n - // (Y + const) * (-(2**n)) -> (-constY) * (2**n), for positive nonzero n - // The "* (2**n)" thus becomes a potential shifting opportunity. + // (1 - X) * (-2) -> (x - 1) * 2, for all positive nonzero powers of 2 + // The "* 2" thus becomes a potential shifting opportunity. { const APInt & Val = CI->getValue(); const APInt &PosVal = Val.abs(); if (Val.isNegative() && PosVal.isPowerOf2()) { - Value *X = 0, *Y = 0; - ConstantInt *C1 = 0; - if (Op0->hasOneUse() && - (match(Op0, m_Sub(m_Value(Y), m_Value(X)))) || - (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1))))) { - Value *Sub; - if (C1) // Matched ADD of constant, negate both operands: - Sub = Builder->CreateSub(Builder->CreateNeg(C1), Y, "subc"); - else // Matched SUB, swap operands: - Sub = Builder->CreateSub(X, Y, "suba"); - return - BinaryOperator::CreateMul(Sub, - ConstantInt::get(X->getType(), PosVal)); + Value *X = 0; + if (match(Op0, m_Sub(m_One(), m_Value(X)))) { + // ConstantInt::get(Op0->getType(), 2); + Value *Sub = Builder->CreateSub(X, ConstantInt::get(X->getType(), 1), + "dec1"); + return BinaryOperator::CreateMul(Sub, ConstantInt::get(X->getType(), + PosVal)); } } } Modified: llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll?rev=132351&r1=132350&r2=132351&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Tue May 31 14:56:35 2011 @@ -2,14 +2,18 @@ ; RUN: opt -S -instcombine < %s | FileCheck %s target triple = "x86_64-apple-macosx10.6.6" -define zeroext i16 @foo1(i32 %on_off) nounwind uwtable ssp { +define zeroext i16 @foo(i32 %on_off, i16* %puls) nounwind uwtable ssp { entry: %on_off.addr = alloca i32, align 4 + %puls.addr = alloca i16*, align 8 %a = alloca i32, align 4 store i32 %on_off, i32* %on_off.addr, align 4 + store i16* %puls, i16** %puls.addr, align 8 %tmp = load i32* %on_off.addr, align 4 +; CHECK-NOT: sub +; CHECK-NOT: mul +; (1 - %tmp) * (-2) -> (%tmp - 1) * 2 %sub = sub i32 1, %tmp -; CHECK-NOT: mul i32 %mul = mul i32 %sub, -2 ; CHECK: shl ; CHECK-NEXT: add @@ -18,40 +22,3 @@ %conv = trunc i32 %tmp1 to i16 ret i16 %conv } - -define zeroext i16 @foo2(i32 %on_off, i32 %q) nounwind uwtable ssp { -entry: - %on_off.addr = alloca i32, align 4 - %q.addr = alloca i32, align 4 - %a = alloca i32, align 4 - store i32 %on_off, i32* %on_off.addr, align 4 - store i32 %q, i32* %q.addr, align 4 - %tmp = load i32* %q.addr, align 4 - %tmp1 = load i32* %on_off.addr, align 4 - %sub = sub i32 %tmp, %tmp1 -; CHECK-NOT: mul i32 - %mul = mul i32 %sub, -4 -; CHECK: sub i32 -; CHECK-NEXT: shl - store i32 %mul, i32* %a, align 4 - %tmp2 = load i32* %a, align 4 - %conv = trunc i32 %tmp2 to i16 - ret i16 %conv -} - -define zeroext i16 @foo3(i32 %on_off) nounwind uwtable ssp { -entry: - %on_off.addr = alloca i32, align 4 - %a = alloca i32, align 4 - store i32 %on_off, i32* %on_off.addr, align 4 - %tmp = load i32* %on_off.addr, align 4 - %sub = sub i32 7, %tmp -; CHECK-NOT: mul i32 - %mul = mul i32 %sub, -4 -; CHECK: shl -; CHECK-NEXT: add - store i32 %mul, i32* %a, align 4 - %tmp1 = load i32* %a, align 4 - %conv = trunc i32 %tmp1 to i16 - ret i16 %conv -} From nicholas at mxc.ca Tue May 31 15:00:45 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 31 May 2011 20:00:45 -0000 Subject: [llvm-commits] [llvm] r132352 - /llvm/trunk/tools/gold/Makefile Message-ID: <20110531200045.444482A6C12C@llvm.org> Author: nicholas Date: Tue May 31 15:00:45 2011 New Revision: 132352 URL: http://llvm.org/viewvc/llvm-project?rev=132352&view=rev Log: Also remove -lLTO which should have been in r132349. I failed to apply this from David Meyer's patch! Modified: llvm/trunk/tools/gold/Makefile Modified: llvm/trunk/tools/gold/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/gold/Makefile?rev=132352&r1=132351&r2=132352&view=diff ============================================================================== --- llvm/trunk/tools/gold/Makefile (original) +++ llvm/trunk/tools/gold/Makefile Tue May 31 15:00:45 2011 @@ -25,7 +25,7 @@ # Because off_t is used in the public API, the largefile parts are required for # ABI compatibility. -CXXFLAGS+=-I$(BINUTILS_INCDIR) -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 -lLTO +CXXFLAGS+=-I$(BINUTILS_INCDIR) -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64 CXXFLAGS+=$(SharedLibDir)/$(SharedPrefix)LTO$(SHLIBEXT) include $(LEVEL)/Makefile.common From eli.friedman at gmail.com Tue May 31 15:08:00 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 31 May 2011 13:08:00 -0700 Subject: [llvm-commits] [llvm] r132348 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/Transforms/InstCombine/2011-05-28-swapmulsub.ll In-Reply-To: <20110531192955.A7C392A6C12C@llvm.org> References: <20110531192955.A7C392A6C12C@llvm.org> Message-ID: On Tue, May 31, 2011 at 12:29 PM, Stuart Hastings wrote: > Author: stuart > Date: Tue May 31 14:29:55 2011 > New Revision: 132348 > > URL: http://llvm.org/viewvc/llvm-project?rev=132348&view=rev > Log: > Followup to 132316; accept arbitrary constants, add with a constant, > sub with a non-constant. ?Fix comments, enlarge test case. > rdar://problem/6501862 > > Modified: > ? ?llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp > ? ?llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll This appears to be breaking buildbots; see http://smooshlab.apple.com:8013/builders/lnt_clang-x86_64-darwin10-gcc42-RA_x86_64-O3/builds/3139 . -Eli From stuart at apple.com Tue May 31 15:09:10 2011 From: stuart at apple.com (Stuart Hastings) Date: Tue, 31 May 2011 13:09:10 -0700 Subject: [llvm-commits] [llvm] r132348 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/Transforms/InstCombine/2011-05-28-swapmulsub.ll In-Reply-To: References: <20110531192955.A7C392A6C12C@llvm.org> Message-ID: On May 31, 2011, at 1:08 PM, Eli Friedman wrote: > On Tue, May 31, 2011 at 12:29 PM, Stuart Hastings wrote: >> Author: stuart >> Date: Tue May 31 14:29:55 2011 >> New Revision: 132348 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132348&view=rev >> Log: >> Followup to 132316; accept arbitrary constants, add with a constant, >> sub with a non-constant. Fix comments, enlarge test case. >> rdar://problem/6501862 >> >> Modified: >> llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp >> llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll > > This appears to be breaking buildbots; see > http://smooshlab.apple.com:8013/builders/lnt_clang-x86_64-darwin10-gcc42-RA_x86_64-O3/builds/3139 > . Agreed, and reverted at 132351. Sorry 'bout that, stuart From eli.friedman at gmail.com Tue May 31 15:10:13 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 31 May 2011 13:10:13 -0700 Subject: [llvm-commits] [llvm] r132348 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/Transforms/InstCombine/2011-05-28-swapmulsub.ll In-Reply-To: References: <20110531192955.A7C392A6C12C@llvm.org> Message-ID: On Tue, May 31, 2011 at 1:08 PM, Eli Friedman wrote: > On Tue, May 31, 2011 at 12:29 PM, Stuart Hastings wrote: >> Author: stuart >> Date: Tue May 31 14:29:55 2011 >> New Revision: 132348 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132348&view=rev >> Log: >> Followup to 132316; accept arbitrary constants, add with a constant, >> sub with a non-constant. ?Fix comments, enlarge test case. >> rdar://problem/6501862 >> >> Modified: >> ? ?llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp >> ? ?llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll > > This appears to be breaking buildbots; see > http://smooshlab.apple.com:8013/builders/lnt_clang-x86_64-darwin10-gcc42-RA_x86_64-O3/builds/3139 > . Oh, missed your revert; never mind. -Eli From eli.friedman at gmail.com Tue May 31 15:12:07 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 31 May 2011 20:12:07 -0000 Subject: [llvm-commits] [llvm] r132353 - /llvm/trunk/lib/VMCore/Verifier.cpp Message-ID: <20110531201207.D9B402A6C12C@llvm.org> Author: efriedma Date: Tue May 31 15:12:07 2011 New Revision: 132353 URL: http://llvm.org/viewvc/llvm-project?rev=132353&view=rev Log: Add a minor missing -verify check. Found by inspection. Modified: llvm/trunk/lib/VMCore/Verifier.cpp Modified: llvm/trunk/lib/VMCore/Verifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=132353&r1=132352&r2=132353&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Verifier.cpp (original) +++ llvm/trunk/lib/VMCore/Verifier.cpp Tue May 31 15:12:07 2011 @@ -1645,6 +1645,9 @@ Assert1(isa(CI.getArgOperand(3)), "alignment argument of memory intrinsics must be a constant int", &CI); + Assert1(isa(CI.getArgOperand(4)), + "isvolatile argument of memory intrinsics must be a constant int", + &CI); break; case Intrinsic::gcroot: case Intrinsic::gcwrite: From bruno.cardoso at gmail.com Tue May 31 15:25:26 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 May 2011 20:25:26 -0000 Subject: [llvm-commits] [llvm] r132355 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110531202526.912972A6C12C@llvm.org> Author: bruno Date: Tue May 31 15:25:26 2011 New Revision: 132355 URL: http://llvm.org/viewvc/llvm-project?rev=132355&view=rev Log: Fix uninitialized variables and silence warnings Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=132355&r1=132354&r2=132355&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Tue May 31 15:25:26 2011 @@ -763,7 +763,7 @@ // prevent MachineLICM pass to hoist "or" instruction out of the block // loopMBB. - int fi; + int fi = 0; if (BinOpcode == 0 && !Nand) { // Get or create a temporary stack location. MipsFunctionInfo *MipsFI = MF->getInfo(); @@ -897,7 +897,8 @@ BuildMI(BB, dl, TII->get(Mips::ANDi), Tmp5).addReg(Tmp4).addImm(MaskImm); BuildMI(BB, dl, TII->get(Mips::SLL), Incr2).addReg(Tmp5).addReg(Shift); } - int fi; + + int fi = 0; if (BinOpcode == 0 && !Nand) { // Get or create a temporary stack location. MipsFunctionInfo *MipsFI = MF->getInfo(); From eli.friedman at gmail.com Tue May 31 15:40:16 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Tue, 31 May 2011 20:40:16 -0000 Subject: [llvm-commits] [llvm] r132356 - in /llvm/trunk: include/llvm/IntrinsicInst.h lib/Analysis/LazyValueInfo.cpp Message-ID: <20110531204016.4B53B2A6C12C@llvm.org> Author: efriedma Date: Tue May 31 15:40:16 2011 New Revision: 132356 URL: http://llvm.org/viewvc/llvm-project?rev=132356&view=rev Log: llvm.memcpy.* has two distinct associated address spaces; the source address space, and the destination address space. Fix up the interface on MemIntrinsic and MemTransferInst to make this clear, and fix InstructionDereferencesPointer in LazyValueInfo.cpp to use the interface properly. Modified: llvm/trunk/include/llvm/IntrinsicInst.h llvm/trunk/lib/Analysis/LazyValueInfo.cpp Modified: llvm/trunk/include/llvm/IntrinsicInst.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/IntrinsicInst.h?rev=132356&r1=132355&r2=132356&view=diff ============================================================================== --- llvm/trunk/include/llvm/IntrinsicInst.h (original) +++ llvm/trunk/include/llvm/IntrinsicInst.h Tue May 31 15:40:16 2011 @@ -139,7 +139,7 @@ return !getVolatileCst()->isZero(); } - unsigned getAddressSpace() const { + unsigned getDestAddressSpace() const { return cast(getRawDest()->getType())->getAddressSpace(); } @@ -227,6 +227,10 @@ /// value is guaranteed to be a pointer. Value *getSource() const { return getRawSource()->stripPointerCasts(); } + unsigned getSourceAddressSpace() const { + return cast(getRawSource()->getType())->getAddressSpace(); + } + void setSource(Value *Ptr) { assert(getRawSource()->getType() == Ptr->getType() && "setSource called with pointer of wrong type!"); Modified: llvm/trunk/lib/Analysis/LazyValueInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/LazyValueInfo.cpp?rev=132356&r1=132355&r2=132356&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/LazyValueInfo.cpp (original) +++ llvm/trunk/lib/Analysis/LazyValueInfo.cpp Tue May 31 15:40:16 2011 @@ -589,16 +589,18 @@ } if (MemIntrinsic *MI = dyn_cast(I)) { if (MI->isVolatile()) return false; - if (MI->getAddressSpace() != 0) return false; // FIXME: check whether it has a valuerange that excludes zero? ConstantInt *Len = dyn_cast(MI->getLength()); if (!Len || Len->isZero()) return false; - if (MI->getRawDest() == Ptr || MI->getDest() == Ptr) - return true; + if (MI->getDestAddressSpace() == 0) + if (MI->getRawDest() == Ptr || MI->getDest() == Ptr) + return true; if (MemTransferInst *MTI = dyn_cast(MI)) - return MTI->getRawSource() == Ptr || MTI->getSource() == Ptr; + if (MTI->getSourceAddressSpace() == 0) + if (MTI->getRawSource() == Ptr || MTI->getSource() == Ptr) + return true; } return false; } From stoklund at 2pi.dk Tue May 31 16:02:44 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 31 May 2011 21:02:44 -0000 Subject: [llvm-commits] [llvm] r132358 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Message-ID: <20110531210244.D57362A6C12C@llvm.org> Author: stoklund Date: Tue May 31 16:02:44 2011 New Revision: 132358 URL: http://llvm.org/viewvc/llvm-project?rev=132358&view=rev Log: Simplify the eviction policy by making the failsafe explicit. When assigned ranges are evicted, they are put in the RS_Evicted stage and are not allowed to evict anything else. That prevents looping automatically. When evicting ranges just to get a cheaper register, use only spill weights to find the possible candidates. Avoid breaking hints for this purpose, it is not worth it. Start implementing more complex eviction heuristics, guarded by the temporary -complex-eviction flag. The initial version permits a heavier range to be evicted if it doesn't have any uses where the evicting range is live. This makes it a good candidate for live ranfge splitting. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=132358&r1=132357&r2=132358&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue May 31 16:02:44 2011 @@ -39,6 +39,7 @@ #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/RegisterCoalescer.h" #include "llvm/Target/TargetOptions.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -52,6 +53,10 @@ STATISTIC(NumLocalSplits, "Number of split local live ranges"); STATISTIC(NumEvicted, "Number of interferences evicted"); +static cl::opt +ComplexEviction("complex-eviction", cl::Hidden, + cl::desc("Use complex eviction heuristics")); + static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator", createGreedyRegisterAllocator); @@ -94,7 +99,8 @@ enum LiveRangeStage { RS_New, ///< Never seen before. RS_First, ///< First time in the queue. - RS_Second, ///< Second time in the queue. + RS_Evicted, ///< Requeued after being evicted. + RS_Second, ///< Second time in the queue, ready for splitting. RS_Global, ///< Produced by global splitting. RS_Local, ///< Produced by local splitting. RS_Spill ///< Produced by spilling. @@ -118,15 +124,6 @@ } } - // Eviction. Sometimes an assigned live range can be evicted without - // conditions, but other times it must be split after being evicted to avoid - // infinite loops. - enum CanEvict { - CE_Never, ///< Can never evict. - CE_Always, ///< Can always evict. - CE_WithSplit ///< Can evict only if range is also split or spilled. - }; - // splitting state. std::auto_ptr SA; std::auto_ptr SE; @@ -198,8 +195,10 @@ SlotIndex getPrevMappedIndex(const MachineInstr*); void calcPrevSlots(); unsigned nextSplitPoint(unsigned); - CanEvict canEvict(LiveInterval &A, LiveInterval &B); - bool canEvictInterference(LiveInterval&, unsigned, float&); + bool hasDefInRange(const LiveInterval&, const LiveInterval&); + bool hasUseInRange(const LiveInterval&, const LiveInterval&); + bool canEvict(LiveInterval &A, LiveInterval &B); + bool canEvictInterference(LiveInterval&, unsigned, float&, bool); unsigned tryAssign(LiveInterval&, AllocationOrder&, SmallVectorImpl&); @@ -220,6 +219,7 @@ const char *const RAGreedy::StageName[] = { "RS_New", "RS_First", + "RS_Evicted", "RS_Second", "RS_Global", "RS_Local", @@ -401,18 +401,60 @@ // Interference eviction //===----------------------------------------------------------------------===// +/// hasDefInRange - Returns true when any def of A happens where B is live. +/// +/// The SSA form of live intervals guarantees: +/// +/// A.overlaps(B) == hasDefInRange(A, B) || hasDefInRange(B, A) +/// +bool RAGreedy::hasDefInRange(const LiveInterval &A, const LiveInterval &B) { + for (LiveInterval::const_vni_iterator I = A.vni_begin(), E = A.vni_end(); + I != E; ++I) { + const VNInfo *VNI = *I; + if (VNI->isUnused()) + continue; + if (B.liveAt(VNI->def)) + return true; + } + return false; +} + +/// hasUseInRange - Returns true when any def or use of A happens where B is +/// live. The following is always true: +/// +/// A.overlaps(B) == hasUseInRange(A, B) || hasUseInRange(B, A) +/// +bool RAGreedy::hasUseInRange(const LiveInterval &A, const LiveInterval &B) { + if (hasDefInRange(A, B)) + return true; + for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(A.reg), + E = MRI->use_nodbg_end(); I != E; ++I) { + if (I.getOperand().isUndef()) + continue; + SlotIndex Idx = Indexes->getInstructionIndex(&*I).getDefIndex(); + if (B.liveAt(Idx)) + return true; + } + return false; +} + /// canEvict - determine if A can evict the assigned live range B. The eviction /// policy defined by this function together with the allocation order defined /// by enqueue() decides which registers ultimately end up being split and /// spilled. /// -/// This function must define a non-circular relation when it returns CE_Always, -/// otherwise infinite eviction loops are possible. When evicting a <= RS_Second -/// range, it is possible to return CE_WithSplit which forces the evicted -/// register to be split or spilled before it can evict anything again. That -/// guarantees progress. -RAGreedy::CanEvict RAGreedy::canEvict(LiveInterval &A, LiveInterval &B) { - return A.weight > B.weight ? CE_Always : CE_Never; +/// Safeguards ensure that canEvict can never cause an infinite loop. +/// +bool RAGreedy::canEvict(LiveInterval &A, LiveInterval &B) { + if (!ComplexEviction) + return A.weight > B.weight; + + // Evict B if it has no uses in A's live range. + if (!hasUseInRange(B, A)) { + DEBUG(dbgs() << "Bypass: " << B << '\n'); + return true; + } + return A.weight > B.weight; } /// canEvict - Return true if all interferences between VirtReg and PhysReg can @@ -420,7 +462,7 @@ /// Return false if any interference is heavier than MaxWeight. /// On return, set MaxWeight to the maximal spill weight of an interference. bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, - float &MaxWeight) { + float &MaxWeight, bool OnlyCheap) { float Weight = 0; for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) { LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI); @@ -433,18 +475,22 @@ LiveInterval *Intf = Q.interferingVRegs()[i - 1]; if (TargetRegisterInfo::isPhysicalRegister(Intf->reg)) return false; - if (Intf->weight >= MaxWeight) + if (getStage(*Intf) == RS_Spill) return false; - switch (canEvict(VirtReg, *Intf)) { - case CE_Always: - break; - case CE_Never: + if (Intf->weight >= MaxWeight) return false; - case CE_WithSplit: - if (getStage(*Intf) > RS_Second) + // When we are simply looking for a cheaper alternative, don't try too + // hard. The evicted range shouldn't end up getting split. + if (OnlyCheap) { + // Don't evict something that won't be able to reevict something else. + if (getStage(*Intf) != RS_First) + return false; + // Don't break a satisfied hint. + if (VRM->getRegAllocPref(Intf->reg) == *AliasI) return false; - break; } + if (VirtReg.isSpillable() && !canEvict(VirtReg, *Intf)) + return false; Weight = std::max(Weight, Intf->weight); } } @@ -453,17 +499,28 @@ } /// tryEvict - Try to evict all interferences for a physreg. -/// @param VirtReg Currently unassigned virtual register. -/// @param Order Physregs to try. -/// @return Physreg to assign VirtReg, or 0. +/// @param VirtReg Currently unassigned virtual register. +/// @param Order Physregs to try. +/// @param CostPerUseLimit Only look at physregs below this cost per use. +/// @return Physreg to assign VirtReg, or 0. unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl &NewVRegs, unsigned CostPerUseLimit) { + // Ranges that may have been evicted or requeued for splitting may never evict + // other ranges. That could cause looping. + // Spill ranges can always evict. + LiveRangeStage Stage = getStage(VirtReg); + if (Stage >= RS_Evicted && VirtReg.isSpillable()) + return 0; NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled); + bool OnlyCheap = CostPerUseLimit != ~0u; + // Keep track of the lightest single interference seen so far. - float BestWeight = HUGE_VALF; + // When scavenging for a cheap register, never consider evicting heavier + // ranges. + float BestWeight = OnlyCheap ? VirtReg.weight : HUGE_VALF; unsigned BestPhys = 0; Order.rewind(); @@ -475,7 +532,7 @@ continue; float Weight = BestWeight; - if (!canEvictInterference(VirtReg, PhysReg, Weight)) + if (!canEvictInterference(VirtReg, PhysReg, Weight, OnlyCheap)) continue; // This is an eviction candidate. @@ -504,11 +561,11 @@ unassign(*Intf, VRM->getPhys(Intf->reg)); ++NumEvicted; NewVRegs.push_back(Intf); - // Prevent looping by forcing the evicted ranges to be split before they - // can evict anything else. - if (getStage(*Intf) < RS_Second && - canEvict(VirtReg, *Intf) == CE_WithSplit) - LRStage[Intf->reg] = RS_Second; + // Prevent looping by marking the evicted ranges as RS_Evicted. + // When OnlyCheap is set, Intf is guaranteed to have a smaller spill + // weight which also prevents looping. + if (!OnlyCheap && getStage(*Intf) < RS_Evicted) + LRStage[Intf->reg] = RS_Evicted; } } return BestPhys; @@ -1417,12 +1474,8 @@ LiveRangeStage Stage = getStage(VirtReg); DEBUG(dbgs() << StageName[Stage] << '\n'); - // Try to evict a less worthy live range, but only for ranges from the primary - // queue. The RS_Second ranges already failed to do this, and they should not - // get a second chance until they have been split. - if (Stage != RS_Second) - if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs)) - return PhysReg; + if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs)) + return PhysReg; assert(NewVRegs.empty() && "Cannot append to existing NewVRegs"); From atrick at apple.com Tue May 31 16:17:47 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 31 May 2011 21:17:47 -0000 Subject: [llvm-commits] [llvm] r132360 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Transforms/IndVarSimplify/elim-extend.ll Message-ID: <20110531211747.AC6D62A6C12C@llvm.org> Author: atrick Date: Tue May 31 16:17:47 2011 New Revision: 132360 URL: http://llvm.org/viewvc/llvm-project?rev=132360&view=rev Log: scev: Better sign-extend removal. Normalize postincrement recurrences so that their sign extended forms are congruent when no overflow occurs. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=132360&r1=132359&r2=132360&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Tue May 31 16:17:47 2011 @@ -1035,6 +1035,93 @@ return S; } +// Get the limit of a recurrence such that incrementing by Step cannot cause +// signed overflow as long as the value of the recurrence within the loop does +// not exceed this limit before incrementing. +static const SCEV *getOverflowLimitForStep(const SCEV *Step, + ICmpInst::Predicate *Pred, + ScalarEvolution *SE) { + unsigned BitWidth = SE->getTypeSizeInBits(Step->getType()); + if (SE->isKnownPositive(Step)) { + *Pred = ICmpInst::ICMP_SLT; + return SE->getConstant(APInt::getSignedMinValue(BitWidth) - + SE->getSignedRange(Step).getSignedMax()); + } + if (SE->isKnownNegative(Step)) { + *Pred = ICmpInst::ICMP_SGT; + return SE->getConstant(APInt::getSignedMaxValue(BitWidth) - + SE->getSignedRange(Step).getSignedMin()); + } + return 0; +} + +// The recurrence AR has been shown to have no signed wrap. Typically, if we can +// prove NSW for AR, then we can just as easily prove NSW for its preincrement +// or postincrement sibling. This allows normalizing a sign extended AddRec as +// such: {sext(Step + Start),+,Step} => {(Step + sext(Start),+,Step} As a +// result, the expression "Step + sext(PreIncAR)" is congruent with +// "sext(PostIncAR)" +static const SCEV *getPreStartForSignExtend(const SCEVAddRecExpr *AR, + const Type *Ty, + ScalarEvolution *SE) { + const Loop *L = AR->getLoop(); + const SCEV *Start = AR->getStart(); + const SCEV *Step = AR->getStepRecurrence(*SE); + + // Check for a simple looking step prior to loop entry. + const SCEVAddExpr *SA = dyn_cast(Start); + if (!SA || SA->getNumOperands() != 2 || SA->getOperand(0) != Step) + return 0; + + // This is a postinc AR. Check for overflow on the preinc recurrence using the + // same three conditions that getSignExtendedExpr checks. + + // 1. NSW flags on the step increment. + const SCEV *PreStart = SA->getOperand(1); + const SCEVAddRecExpr *PreAR = dyn_cast( + SE->getAddRecExpr(PreStart, Step, L, SCEV::FlagAnyWrap)); + + if (PreAR && PreAR->getNoWrapFlags(SCEV::FlagNSW)) { + return PreStart; + } + + // 2. Direct overflow check on the step operation's expression. + unsigned BitWidth = SE->getTypeSizeInBits(AR->getType()); + const Type *WideTy = IntegerType::get(SE->getContext(), BitWidth * 2); + const SCEV *OperandExtendedStart = + SE->getAddExpr(SE->getSignExtendExpr(PreStart, WideTy), + SE->getSignExtendExpr(Step, WideTy)); + if (SE->getSignExtendExpr(Start, WideTy) == OperandExtendedStart) { + // Cache knowledge of PreAR NSW. + if (PreAR) + const_cast(PreAR)->setNoWrapFlags(SCEV::FlagNSW); + // FIXME: this optimization needs a unit test + DEBUG(dbgs() << "SCEV: untested prestart overflow check\n"); + return PreStart; + } + + // 3. Loop precondition. + ICmpInst::Predicate Pred; + const SCEV *OverflowLimit = getOverflowLimitForStep(Step, &Pred, SE); + + if (SE->isLoopEntryGuardedByCond(L, Pred, PreStart, OverflowLimit)) { + return PreStart; + } + return 0; +} + +// Get the normalized sign-extended expression for this AddRec's Start. +static const SCEV *getSignExtendAddRecStart(const SCEVAddRecExpr *AR, + const Type *Ty, + ScalarEvolution *SE) { + const SCEV *PreStart = getPreStartForSignExtend(AR, Ty, SE); + if (!PreStart) + return SE->getSignExtendExpr(AR->getStart(), Ty); + + return SE->getAddExpr(SE->getSignExtendExpr(AR->getStepRecurrence(*SE), Ty), + SE->getSignExtendExpr(PreStart, Ty)); +} + const SCEV *ScalarEvolution::getSignExtendExpr(const SCEV *Op, const Type *Ty) { assert(getTypeSizeInBits(Op->getType()) < getTypeSizeInBits(Ty) && @@ -1097,7 +1184,7 @@ // If we have special knowledge that this addrec won't overflow, // we don't need to do any further analysis. if (AR->getNoWrapFlags(SCEV::FlagNSW)) - return getAddRecExpr(getSignExtendExpr(Start, Ty), + return getAddRecExpr(getSignExtendAddRecStart(AR, Ty, this), getSignExtendExpr(Step, Ty), L, SCEV::FlagNSW); @@ -1133,7 +1220,7 @@ // Cache knowledge of AR NSW, which is propagated to this AddRec. const_cast(AR)->setNoWrapFlags(SCEV::FlagNSW); // Return the expression with the addrec on the outside. - return getAddRecExpr(getSignExtendExpr(Start, Ty), + return getAddRecExpr(getSignExtendAddRecStart(AR, Ty, this), getSignExtendExpr(Step, Ty), L, AR->getNoWrapFlags()); } @@ -1149,7 +1236,7 @@ // Cache knowledge of AR NSW, which is propagated to this AddRec. const_cast(AR)->setNoWrapFlags(SCEV::FlagNSW); // Return the expression with the addrec on the outside. - return getAddRecExpr(getSignExtendExpr(Start, Ty), + return getAddRecExpr(getSignExtendAddRecStart(AR, Ty, this), getZeroExtendExpr(Step, Ty), L, AR->getNoWrapFlags()); } @@ -1159,34 +1246,18 @@ // the addrec is safe. Also, if the entry is guarded by a comparison // with the start value and the backedge is guarded by a comparison // with the post-inc value, the addrec is safe. - if (isKnownPositive(Step)) { - const SCEV *N = getConstant(APInt::getSignedMinValue(BitWidth) - - getSignedRange(Step).getSignedMax()); - if (isLoopBackedgeGuardedByCond(L, ICmpInst::ICMP_SLT, AR, N) || - (isLoopEntryGuardedByCond(L, ICmpInst::ICMP_SLT, Start, N) && - isLoopBackedgeGuardedByCond(L, ICmpInst::ICMP_SLT, - AR->getPostIncExpr(*this), N))) { - // Cache knowledge of AR NSW, which is propagated to this AddRec. - const_cast(AR)->setNoWrapFlags(SCEV::FlagNSW); - // Return the expression with the addrec on the outside. - return getAddRecExpr(getSignExtendExpr(Start, Ty), - getSignExtendExpr(Step, Ty), - L, AR->getNoWrapFlags()); - } - } else if (isKnownNegative(Step)) { - const SCEV *N = getConstant(APInt::getSignedMaxValue(BitWidth) - - getSignedRange(Step).getSignedMin()); - if (isLoopBackedgeGuardedByCond(L, ICmpInst::ICMP_SGT, AR, N) || - (isLoopEntryGuardedByCond(L, ICmpInst::ICMP_SGT, Start, N) && - isLoopBackedgeGuardedByCond(L, ICmpInst::ICMP_SGT, - AR->getPostIncExpr(*this), N))) { - // Cache knowledge of AR NSW, which is propagated to this AddRec. - const_cast(AR)->setNoWrapFlags(SCEV::FlagNSW); - // Return the expression with the addrec on the outside. - return getAddRecExpr(getSignExtendExpr(Start, Ty), - getSignExtendExpr(Step, Ty), - L, AR->getNoWrapFlags()); - } + ICmpInst::Predicate Pred; + const SCEV *OverflowLimit = getOverflowLimitForStep(Step, &Pred, this); + if (OverflowLimit && + (isLoopBackedgeGuardedByCond(L, Pred, AR, OverflowLimit) || + (isLoopEntryGuardedByCond(L, Pred, Start, OverflowLimit) && + isLoopBackedgeGuardedByCond(L, Pred, AR->getPostIncExpr(*this), + OverflowLimit)))) { + // Cache knowledge of AR NSW, then propagate NSW to the wide AddRec. + const_cast(AR)->setNoWrapFlags(SCEV::FlagNSW); + return getAddRecExpr(getSignExtendAddRecStart(AR, Ty, this), + getSignExtendExpr(Step, Ty), + L, AR->getNoWrapFlags()); } } } Modified: llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll?rev=132360&r1=132359&r2=132360&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll Tue May 31 16:17:47 2011 @@ -2,9 +2,8 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -; Test reusing the same IV with constant start for preinc and postinc values -; with and without NSW. -; IV rewrite only removes one sext. WidenIVs should remove all three. +; IV with constant start, preinc and postinc sign extends, with and without NSW. +; IV rewrite only removes one sext. WidenIVs removes all three. define void @postincConstIV(i8* %base, i32 %limit) nounwind { entry: br label %loop @@ -33,21 +32,19 @@ ret void } -; Test reusing the same IV with nonconstant start for preinc and postinc values +; IV with nonconstant start, preinc and postinc sign extends, ; with and without NSW. -; As with constant IV start, WidenIVs should remove all three. -; -; FIXME: WidenIVs should remove %postofs just like %postofsnsw +; As with postincConstIV, WidenIVs removes all three sexts. define void @postincVarIV(i8* %base, i32 %init, i32 %limit) nounwind { entry: - br label %loop + %precond = icmp sgt i32 %limit, %init + br i1 %precond, label %loop, label %return ; CHECK: loop: -; CHECK: sext ; CHECK-NOT: sext ; CHECK: exit: loop: %iv = phi i32 [ %postiv, %loop ], [ %init, %entry ] - %ivnsw = phi i32 [ %postivnsw, %loop ], [ 0, %entry ] + %ivnsw = phi i32 [ %postivnsw, %loop ], [ %init, %entry ] %preofs = sext i32 %iv to i64 %preadr = getelementptr i8* %base, i64 %preofs store i8 0, i8* %preadr @@ -59,7 +56,7 @@ %postofsnsw = sext i32 %postivnsw to i64 %postadrnsw = getelementptr i8* %base, i64 %postofsnsw store i8 0, i8* %postadrnsw - %cond = icmp sgt i32 %limit, %iv + %cond = icmp sgt i32 %limit, %postiv br i1 %cond, label %loop, label %exit exit: br label %return @@ -103,15 +100,13 @@ ; CHECK: innerloop: ; ; Eliminate %ofs2 after widening inneriv. +; Eliminate %ofs3 after normalizing sext(innerpostiv) ; CHECK-NOT: sext ; CHECK: getelementptr ; -; FIXME: We should not increase the number of IVs in this loop. -; sext elimination plus LFTR results in 3 final IVs. -; -; FIXME: eliminate %ofs3 based the loop pre/post conditions -; even though innerpostiv is not NSW, thus sign extending innerpostiv -; does not yield the same expression as incrementing the widened inneriv. +; FIXME: We should check that indvars does not increase the number of +; IVs in this loop. sext elimination plus LFTR currently results in 2 final +; IVs. Waiting to remove LFTR. innerloop: %inneriv = phi i32 [ %innerpostiv, %innerloop ], [ %innercount, %innerpreheader ] %innerpostiv = add i32 %inneriv, 1 From joerg at britannica.bec.de Tue May 31 16:26:49 2011 From: joerg at britannica.bec.de (Joerg Sonnenberger) Date: Tue, 31 May 2011 23:26:49 +0200 Subject: [llvm-commits] [PATCH] Dependency output for tblgen Message-ID: <20110531212649.GA30687@britannica.bec.de> Hi all, attached patch allows gcc -M -MF style dependency generation for tblgen. This proper updates when .td file change, Someone Else (TM) just has to hook it up into the Makefiles. Comments? Joerg -------------- next part -------------- A non-text attachment was scrubbed... Name: tblgen-dependencies.diff Type: text/x-diff Size: 8259 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110531/cce8e1aa/attachment.bin From aggarwa4 at illinois.edu Tue May 31 16:28:21 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 31 May 2011 21:28:21 -0000 Subject: [llvm-commits] [poolalloc] r132362 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110531212821.DD8572A6C12C@llvm.org> Author: aggarwa4 Date: Tue May 31 16:28:21 2011 New Revision: 132362 URL: http://llvm.org/viewvc/llvm-project?rev=132362&view=rev Log: Add an option to not differentiate between pointer types, when typechecking. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132362&r1=132361&r2=132362&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue May 31 16:28:21 2011 @@ -44,6 +44,10 @@ cl::desc("Use DSA pass"), cl::Hidden, cl::init(false)); + static cl::opt DisablePointerTypeChecks("disable-ptr-type-checks", + cl::desc("DONT Distinguish pointer types"), + cl::Hidden, + cl::init(false)); } static int tagCounter = 0; @@ -55,6 +59,11 @@ unsigned int TypeChecks::getTypeMarker(const Type * Ty) { + if(DisablePointerTypeChecks) { + if(Ty->isPointerTy()) { + Ty = VoidPtrTy; + } + } if(UsedTypes.find(Ty) == UsedTypes.end()) UsedTypes[Ty] = UsedTypes.size(); From evan.cheng at apple.com Tue May 31 16:40:02 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 31 May 2011 14:40:02 -0700 Subject: [llvm-commits] [PATCH] ARM pli builtin and intrinsic In-Reply-To: References: Message-ID: My preference is for the intrinsics to follow existing naming convention. In theory, other targets may have i-cache prefetching instructions. pli is too ARM specific to me. Evan On May 27, 2011, at 9:34 PM, Bruno Cardoso Lopes wrote: > Hi, > > Since llvm.prefetch can only be mapped now to ARM data prefetching > (pld), add support for instruction prefetching by adding an ARM pli > intrinsic. Another approach I could go for is to add one more argument > to @llvm.prefetch intrinsic. Let me know which one is preferred. > > Thanks > > -- > Bruno Cardoso Lopes > http://www.brunocardoso.cc > From gkistanova at gmail.com Tue May 31 16:50:33 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Tue, 31 May 2011 21:50:33 -0000 Subject: [llvm-commits] [llvm] r132364 - in /llvm/trunk/test/ExecutionEngine: 2002-12-16-ArgTest.ll 2003-01-04-ArgumentBug.ll 2003-01-04-LoopTest.ll 2003-01-15-AlignmentTest.ll 2003-05-06-LivenessClobber.ll 2003-05-07-ArgumentTest.ll 2003-08-21-EnvironmentTest.ll 2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll hello.ll hello2.ll simpletest.ll stubs.ll test-fp.ll test-loadstore.ll test-malloc.ll Message-ID: <20110531215036.149042A6C12C@llvm.org> Author: gkistanova Date: Tue May 31 16:50:33 2011 New Revision: 132364 URL: http://llvm.org/viewvc/llvm-project?rev=132364&view=rev Log: Reverted r132135 per Xerxes request. These tests are passing for his setup. Requires more research. Modified: llvm/trunk/test/ExecutionEngine/2002-12-16-ArgTest.ll llvm/trunk/test/ExecutionEngine/2003-01-04-ArgumentBug.ll llvm/trunk/test/ExecutionEngine/2003-01-04-LoopTest.ll llvm/trunk/test/ExecutionEngine/2003-01-15-AlignmentTest.ll llvm/trunk/test/ExecutionEngine/2003-05-06-LivenessClobber.ll llvm/trunk/test/ExecutionEngine/2003-05-07-ArgumentTest.ll llvm/trunk/test/ExecutionEngine/2003-08-21-EnvironmentTest.ll llvm/trunk/test/ExecutionEngine/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll llvm/trunk/test/ExecutionEngine/hello.ll llvm/trunk/test/ExecutionEngine/hello2.ll llvm/trunk/test/ExecutionEngine/simpletest.ll llvm/trunk/test/ExecutionEngine/stubs.ll llvm/trunk/test/ExecutionEngine/test-fp.ll llvm/trunk/test/ExecutionEngine/test-loadstore.ll llvm/trunk/test/ExecutionEngine/test-malloc.ll Modified: llvm/trunk/test/ExecutionEngine/2002-12-16-ArgTest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2002-12-16-ArgTest.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2002-12-16-ArgTest.ll (original) +++ llvm/trunk/test/ExecutionEngine/2002-12-16-ArgTest.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. @.LC0 = internal global [10 x i8] c"argc: %d\0A\00" ; <[10 x i8]*> [#uses=1] Modified: llvm/trunk/test/ExecutionEngine/2003-01-04-ArgumentBug.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2003-01-04-ArgumentBug.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2003-01-04-ArgumentBug.ll (original) +++ llvm/trunk/test/ExecutionEngine/2003-01-04-ArgumentBug.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. define i32 @foo(i32 %X, i32 %Y, double %A) { %cond212 = fcmp une double %A, 1.000000e+00 ; [#uses=1] Modified: llvm/trunk/test/ExecutionEngine/2003-01-04-LoopTest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2003-01-04-LoopTest.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2003-01-04-LoopTest.ll (original) +++ llvm/trunk/test/ExecutionEngine/2003-01-04-LoopTest.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. define i32 @main() { call i32 @mylog( i32 4 ) ; :1 [#uses=0] Modified: llvm/trunk/test/ExecutionEngine/2003-01-15-AlignmentTest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2003-01-15-AlignmentTest.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2003-01-15-AlignmentTest.ll (original) +++ llvm/trunk/test/ExecutionEngine/2003-01-15-AlignmentTest.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. define i32 @bar(i8* %X) { ; pointer should be 4 byte aligned! Modified: llvm/trunk/test/ExecutionEngine/2003-05-06-LivenessClobber.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2003-05-06-LivenessClobber.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2003-05-06-LivenessClobber.ll (original) +++ llvm/trunk/test/ExecutionEngine/2003-05-06-LivenessClobber.ll Tue May 31 16:50:33 2011 @@ -1,8 +1,6 @@ ; This testcase should return with an exit code of 1. ; ; RUN: not lli %s -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. @test = global i64 0 ; [#uses=1] Modified: llvm/trunk/test/ExecutionEngine/2003-05-07-ArgumentTest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2003-05-07-ArgumentTest.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2003-05-07-ArgumentTest.ll (original) +++ llvm/trunk/test/ExecutionEngine/2003-05-07-ArgumentTest.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s test -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. declare i32 @puts(i8*) Modified: llvm/trunk/test/ExecutionEngine/2003-08-21-EnvironmentTest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2003-08-21-EnvironmentTest.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2003-08-21-EnvironmentTest.ll (original) +++ llvm/trunk/test/ExecutionEngine/2003-08-21-EnvironmentTest.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. ; ; Regression Test: EnvironmentTest.ll Modified: llvm/trunk/test/ExecutionEngine/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll (original) +++ llvm/trunk/test/ExecutionEngine/2003-10-18-PHINode-ConstantExpr-CondCode-Failure.ll Tue May 31 16:50:33 2011 @@ -1,7 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. - @A = global i32 0 ; [#uses=1] Modified: llvm/trunk/test/ExecutionEngine/hello.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/hello.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/hello.ll (original) +++ llvm/trunk/test/ExecutionEngine/hello.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. @.LC0 = internal global [12 x i8] c"Hello World\00" ; <[12 x i8]*> [#uses=1] Modified: llvm/trunk/test/ExecutionEngine/hello2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/hello2.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/hello2.ll (original) +++ llvm/trunk/test/ExecutionEngine/hello2.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. @X = global i32 7 ; [#uses=0] @msg = internal global [13 x i8] c"Hello World\0A\00" ; <[13 x i8]*> [#uses=1] Modified: llvm/trunk/test/ExecutionEngine/simpletest.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/simpletest.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/simpletest.ll (original) +++ llvm/trunk/test/ExecutionEngine/simpletest.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. define i32 @bar() { ret i32 0 Modified: llvm/trunk/test/ExecutionEngine/stubs.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/stubs.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/stubs.ll (original) +++ llvm/trunk/test/ExecutionEngine/stubs.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli -disable-lazy-compilation=false %s -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. define i32 @main() nounwind { entry: Modified: llvm/trunk/test/ExecutionEngine/test-fp.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/test-fp.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/test-fp.ll (original) +++ llvm/trunk/test/ExecutionEngine/test-fp.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. define double @test(double* %DP, double %Arg) { %D = load double* %DP ; [#uses=1] Modified: llvm/trunk/test/ExecutionEngine/test-loadstore.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/test-loadstore.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/test-loadstore.ll (original) +++ llvm/trunk/test/ExecutionEngine/test-loadstore.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. define void @test(i8* %P, i16* %P.upgrd.1, i32* %P.upgrd.2, i64* %P.upgrd.3) { %V = load i8* %P ; [#uses=1] Modified: llvm/trunk/test/ExecutionEngine/test-malloc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/ExecutionEngine/test-malloc.ll?rev=132364&r1=132363&r2=132364&view=diff ============================================================================== --- llvm/trunk/test/ExecutionEngine/test-malloc.ll (original) +++ llvm/trunk/test/ExecutionEngine/test-malloc.ll Tue May 31 16:50:33 2011 @@ -1,6 +1,4 @@ ; RUN: lli %s > /dev/null -; XFAIL: arm -; FIXME: ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed. define i32 @main() { %X = malloc i32 ; [#uses=1] From stoklund at 2pi.dk Tue May 31 16:54:28 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 31 May 2011 21:54:28 -0000 Subject: [llvm-commits] [llvm] r132365 - /llvm/trunk/.gitignore Message-ID: <20110531215428.AACE32A6C12C@llvm.org> Author: stoklund Date: Tue May 31 16:54:28 2011 New Revision: 132365 URL: http://llvm.org/viewvc/llvm-project?rev=132365&view=rev Log: Ignore Vim swap files Modified: llvm/trunk/.gitignore Modified: llvm/trunk/.gitignore URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/.gitignore?rev=132365&r1=132364&r2=132365&view=diff ============================================================================== --- llvm/trunk/.gitignore (original) +++ llvm/trunk/.gitignore Tue May 31 16:54:28 2011 @@ -15,6 +15,8 @@ *.orig # Byte compiled python modules. *.pyc +# vim swap files +.*.swp #==============================================================================# # Explicit files to ignore (only matches one). From gkistanova at gmail.com Tue May 31 17:10:41 2011 From: gkistanova at gmail.com (Galina Kistanova) Date: Tue, 31 May 2011 15:10:41 -0700 Subject: [llvm-commits] [llvm] r132135 - in /llvm/trunk/test/ExecutionEngine: 2002-12-16-ArgTest.ll 2003-01-04-ArgumentBug.ll 2003-01-04-LoopTest.ll 2003-01-15-AlignmentTest.ll 2003-05-06-LivenessClobber.ll 2003-05-07-ArgumentTest.ll 2003-08-21-Environmen In-Reply-To: <1306851124.7244.9.camel@xranby-ESPRIMO-P7935> References: <53F92A0F-81D4-4F48-8240-6FBE567C303F@apple.com> <1306851124.7244.9.camel@xranby-ESPRIMO-P7935> Message-ID: Hello Xerxes, I revert the changes. Seems need more research on this. Not sure what make you think I using Thumb2: $ clang-native-arm-cortex-a9/llvm/Release+Asserts/bin/lli -version Low Level Virtual Machine (http://llvm.org/): llvm version 3.0svn Optimized build with assertions. Built May 31 2011 (12:25:45). Host: armv7l-unknown-linux-gnueabi Host CPU: (unknown) Registered Targets: arm - ARM thumb - Thumb Thanks Galina On Tue, May 31, 2011 at 7:12 AM, Xerxes R?nby wrote: > The reason why these tests fail on your machine are because your system > are using Thumb2 and the jit are only functional in ARM mode. movw/movt > are thumb2 instructions. > > The llvm jit runs in thumb2 mode on your machine are because lli > -version report > Host: thumb-unknown-linux-gnueabi > > The missing thumb2 implementation is a known limitation of the llvm JIT. > http://llvm.org/bugs/show_bug.cgi?id=6223 > > > The ARM JIT work when LLVM have been compiled in ARM mode and then lli > -version report > Host: arm-unknown-linux-gnueabi > > I noticed that you have marked ExecutionEngine/hello.ll as XFAIL on ARM, > http://llvm.org/viewvc/llvm-project/?view=rev&revision=132135 > ?this in not correct since the tests do pass on ARM when the jit are > compiled in ARM mode. See: > http://google1.osuosl.org:8011/builders/llvm-arm-linux > > This ARM builder test now fail because of all the added XFAILS. > > Cheers > Xerxes > > tor 2011-05-26 klockan 14:42 -0700 skrev Galina Kistanova: >> One of failed tests below. All in the attachment. >> >> Thanks >> >> Galina >> >> >> ******************** TEST 'LLVM :: ExecutionEngine/hello.ll' FAILED >> ********************Script: >> -- >> /home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/Release+Asserts/bin/lli >> /home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/test/ExecutionEngine/hello.ll >> > /dev/null >> -- >> Exit Code: 134 >> Command Output (stderr): >> -- >> %R0Unsupported operand type for movw/movt >> UNREACHABLE executed at ARMCodeEmitter.cpp:426! >> Stack dump: >> 0. ? ?Program arguments: >> /home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/Release+Asserts/bin/lli >> /home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/test/ExecutionEngine/hello.ll >> 1. ? ?Running pass 'ARM Machine Code Emitter' on function '@main' >> /home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/test/ExecutionEngine/Output/hello.ll.script: >> line 2: 22987 Aborted >> '/home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/Release+Asserts/bin/lli' >> '/home/buildslave/zorg/buildbot/osuosl/slave/clang-native-arm-cortex-a9-II/llvm/test/ExecutionEngine/hello.ll' >> > '/dev/null' >> -- >> >> ******************** >> >> >> >> >> On Thu, May 26, 2011 at 2:20 PM, Eric Christopher wrote: >> > >> > On May 26, 2011, at 2:15 PM, Galina Kistanova wrote: >> > >> >> I am about to add new builder to build clang on ARM. Some tests fail there. >> >> If you need more info on failing tests, please let me know. >> > >> > How are the tests failing? Do you have any more information? >> > >> > -eric >> > >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > From bruno.cardoso at gmail.com Tue May 31 17:11:17 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 May 2011 19:11:17 -0300 Subject: [llvm-commits] [PATCH] ARM pli builtin and intrinsic In-Reply-To: References: Message-ID: On Tue, May 31, 2011 at 6:40 PM, Evan Cheng wrote: > My preference is for the intrinsics to follow existing naming convention. In theory, other targets may have i-cache prefetching instructions. pli is too ARM specific to me. What about "@llvm.iprefetch"? -- Bruno Cardoso Lopes http://www.brunocardoso.cc From echristo at apple.com Tue May 31 17:08:30 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 31 May 2011 22:08:30 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r132366 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20110531220830.960642A6C12C@llvm.org> Author: echristo Date: Tue May 31 17:08:30 2011 New Revision: 132366 URL: http://llvm.org/viewvc/llvm-project?rev=132366&view=rev Log: Look through struct wrapped types when deciding whether or not it's a simple emit for the input constraints in an inline asm. Fixes rdar://9529215 Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=132366&r1=132365&r2=132366&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue May 31 17:08:30 2011 @@ -4978,7 +4978,9 @@ if (LLVM_IS_DECL_MMX_REGISTER(Val)) LLVMTy = Type::getX86_MMXTy(Context); const Type *OpTy = LLVMTy; - if (LLVMTy->isSingleValueType()) { + const StructType *STy = dyn_cast(OpTy); + if (LLVMTy->isSingleValueType() || + (STy && STy->getNumElements() == 1)) { if (TREE_CODE(Val)==ADDR_EXPR && TREE_CODE(TREE_OPERAND(Val,0))==LABEL_DECL) { // Emit the label, but do not assume it is going to be the target From evan.cheng at apple.com Tue May 31 17:21:16 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 31 May 2011 15:21:16 -0700 Subject: [llvm-commits] [PATCH] ARM pli builtin and intrinsic In-Reply-To: References: Message-ID: On May 31, 2011, at 3:11 PM, Bruno Cardoso Lopes wrote: > On Tue, May 31, 2011 at 6:40 PM, Evan Cheng wrote: >> My preference is for the intrinsics to follow existing naming convention. In theory, other targets may have i-cache prefetching instructions. pli is too ARM specific to me. > > What about "@llvm.iprefetch"? Adding another argument to @llvm.prefetch is fine. But what do you propose for C level builtin? Evan > > -- > Bruno Cardoso Lopes > http://www.brunocardoso.cc From bruno.cardoso at gmail.com Tue May 31 17:38:04 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 May 2011 19:38:04 -0300 Subject: [llvm-commits] [PATCH] ARM pli builtin and intrinsic In-Reply-To: References: Message-ID: > Adding another argument to @llvm.prefetch is fine. But what do you propose for C level builtin? __builtin_iprefetch or __builtin_icache_prefetch, with an address argument only, either are fine for me. What's your opinion? -- Bruno Cardoso Lopes http://www.brunocardoso.cc From dpatel at apple.com Tue May 31 17:56:51 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 May 2011 22:56:51 -0000 Subject: [llvm-commits] [llvm] r132371 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfCompileUnit.cpp DwarfDebug.cpp Message-ID: <20110531225652.0D9A72A6C12C@llvm.org> Author: dpatel Date: Tue May 31 17:56:51 2011 New Revision: 132371 URL: http://llvm.org/viewvc/llvm-project?rev=132371&view=rev Log: Include global types, that are referenced through local variables, in debug_pubtypes list. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=132371&r1=132370&r2=132371&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Tue May 31 17:56:51 2011 @@ -605,8 +605,14 @@ // Set up proxy. Entry = createDIEEntry(Buffer); insertDIEEntry(Ty, Entry); - Entity->addValue(dwarf::DW_AT_type, dwarf::DW_FORM_ref4, Entry); + + // If this is a complete composite type then include it in the + // list of global types. + DIDescriptor Context = Ty.getContext(); + if (Ty.isCompositeType() && !Ty.getName().empty() && !Ty.isForwardDecl() + && (Context.isCompileUnit() || Context.isFile() || Context.isNameSpace())) + addGlobalType(Ty.getName(), Entry->getEntry()); } /// addPubTypes - Add type for pubtypes section. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=132371&r1=132370&r2=132371&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Tue May 31 17:56:51 2011 @@ -985,12 +985,7 @@ getRealLinkageName(LinkageName)); // Add type. TheCU->addType(VariableDIE, GTy); - if (GTy.isCompositeType() && !GTy.getName().empty() - && !GTy.isForwardDecl()) { - DIEEntry *Entry = TheCU->getDIEEntry(GTy); - assert(Entry && "Missing global type!"); - TheCU->addGlobalType(GTy.getName(), Entry->getEntry()); - } + // Add scoping info. if (!GV.isLocalToUnit()) { TheCU->addUInt(VariableDIE, dwarf::DW_AT_external, dwarf::DW_FORM_flag, 1); From dpatel at apple.com Tue May 31 18:30:30 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 May 2011 23:30:30 -0000 Subject: [llvm-commits] [llvm] r132373 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfCompileUnit.cpp DwarfCompileUnit.h Message-ID: <20110531233030.B3A6B2A6C12C@llvm.org> Author: dpatel Date: Tue May 31 18:30:30 2011 New Revision: 132373 URL: http://llvm.org/viewvc/llvm-project?rev=132373&view=rev Log: Refactor. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=132373&r1=132372&r2=132373&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Tue May 31 18:30:30 2011 @@ -609,10 +609,16 @@ // If this is a complete composite type then include it in the // list of global types. + addGlobalType(Ty, Entry->getEntry()); +} + +/// addGlobalType - Add a new global type to the compile unit. +/// +void CompileUnit::addGlobalType(DIType Ty, DIE *Die) { DIDescriptor Context = Ty.getContext(); if (Ty.isCompositeType() && !Ty.getName().empty() && !Ty.isForwardDecl() && (Context.isCompileUnit() || Context.isFile() || Context.isNameSpace())) - addGlobalType(Ty.getName(), Entry->getEntry()); + GlobalTypes[Ty.getName()] = Die; } /// addPubTypes - Add type for pubtypes section. @@ -627,12 +633,7 @@ DIType ATy(Args.getElement(i)); if (!ATy.Verify()) continue; - DICompositeType CATy = getDICompositeType(ATy); - if (DIDescriptor(CATy).Verify() && !CATy.getName().empty() - && !CATy.isForwardDecl()) { - if (DIEEntry *Entry = getDIEEntry(CATy)) - addGlobalType(CATy.getName(), Entry->getEntry()); - } + addGlobalType(ATy, getDIEEntry(ATy)->getEntry()); } } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=132373&r1=132372&r2=132373&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Tue May 31 18:30:30 2011 @@ -87,9 +87,7 @@ /// addGlobalType - Add a new global type to the compile unit. /// - void addGlobalType(StringRef Name, DIE *Die) { - GlobalTypes[Name] = Die; - } + void addGlobalType(DIType Ty, DIE *Die); /// getDIE - Returns the debug information entry map slot for the /// specified debug variable. From evan.cheng at apple.com Tue May 31 18:46:02 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 31 May 2011 16:46:02 -0700 Subject: [llvm-commits] [PATCH] ARM pli builtin and intrinsic In-Reply-To: References: Message-ID: <9A520CD3-C0EC-4847-9912-13BCF7F2C1AE@apple.com> How about __builtin_instruction_prefetch? Or is too long? Evan On May 31, 2011, at 3:38 PM, Bruno Cardoso Lopes wrote: >> Adding another argument to @llvm.prefetch is fine. But what do you propose for C level builtin? > > __builtin_iprefetch or __builtin_icache_prefetch, with an address > argument only, either are fine for me. What's your opinion? > > > -- > Bruno Cardoso Lopes > http://www.brunocardoso.cc From echristo at apple.com Tue May 31 18:55:26 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 31 May 2011 16:55:26 -0700 Subject: [llvm-commits] [cfe-commits] [PATCH] ARM pli builtin and intrinsic In-Reply-To: <9A520CD3-C0EC-4847-9912-13BCF7F2C1AE@apple.com> References: <9A520CD3-C0EC-4847-9912-13BCF7F2C1AE@apple.com> Message-ID: On May 31, 2011, at 4:46 PM, Evan Cheng wrote: > How about __builtin_instruction_prefetch? Or is too long? > > Evan > > On May 31, 2011, at 3:38 PM, Bruno Cardoso Lopes wrote: > >>> Adding another argument to @llvm.prefetch is fine. But what do you propose for C level builtin? >> >> __builtin_iprefetch or __builtin_icache_prefetch, with an address >> argument only, either are fine for me. What's your opinion? >> FWIW I like __builtin_iprefetch. It's a shame the original prefetch wasn't __builtin_dprefetch. If we wanted some symmetry we could have both __builtin_icache_prefetch and __builtin_dcache_prefetch, the second being an alias to the existing __builtin_prefetch. -eric From dpatel at apple.com Tue May 31 18:57:48 2011 From: dpatel at apple.com (Devang Patel) Date: Tue, 31 May 2011 23:57:48 -0000 Subject: [llvm-commits] [debuginfo-tests] r132375 - in /debuginfo-tests/trunk: dbg-declare.ll dbg-declare2.ll local-var.ll local-var2.ll Message-ID: <20110531235748.EF0F12A6C12C@llvm.org> Author: dpatel Date: Tue May 31 18:57:48 2011 New Revision: 132375 URL: http://llvm.org/viewvc/llvm-project?rev=132375&view=rev Log: Remove working directory path from intermediate files. They are not checked in the output anyway. Modified: debuginfo-tests/trunk/dbg-declare.ll debuginfo-tests/trunk/dbg-declare2.ll debuginfo-tests/trunk/local-var.ll debuginfo-tests/trunk/local-var2.ll Modified: debuginfo-tests/trunk/dbg-declare.ll URL: http://llvm.org/viewvc/llvm-project/debuginfo-tests/trunk/dbg-declare.ll?rev=132375&r1=132374&r2=132375&view=diff ============================================================================== --- debuginfo-tests/trunk/dbg-declare.ll (original) +++ debuginfo-tests/trunk/dbg-declare.ll Tue May 31 18:57:48 2011 @@ -184,8 +184,8 @@ !llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} !0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 524329, metadata !"fastisel_arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"fastisel_arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] Modified: debuginfo-tests/trunk/dbg-declare2.ll URL: http://llvm.org/viewvc/llvm-project/debuginfo-tests/trunk/dbg-declare2.ll?rev=132375&r1=132374&r2=132375&view=diff ============================================================================== --- debuginfo-tests/trunk/dbg-declare2.ll (original) +++ debuginfo-tests/trunk/dbg-declare2.ll Tue May 31 18:57:48 2011 @@ -185,8 +185,8 @@ !llvm.dbg.sp = !{!0, !6, !7, !8, !9, !10, !11, !12, !13, !14, !15} !0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 11, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 (i32)* @f1} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"/Users/manav/dbg_info_bugs/fastisel_arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 524329, metadata !"fastisel_arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"fastisel_arg.c", metadata !"/private/tmp", metadata !"clang version 2.8 (trunk 112967)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] Modified: debuginfo-tests/trunk/local-var.ll URL: http://llvm.org/viewvc/llvm-project/debuginfo-tests/trunk/local-var.ll?rev=132375&r1=132374&r2=132375&view=diff ============================================================================== --- debuginfo-tests/trunk/local-var.ll (original) +++ debuginfo-tests/trunk/local-var.ll Tue May 31 18:57:48 2011 @@ -73,8 +73,8 @@ !llvm.dbg.sp = !{!0, !6, !7, !8, !9} !0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @f1} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"lv.c", metadata !"/Users/manav/dbg_info_bugs", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"lv.c", metadata !"/Users/manav/dbg_info_bugs", metadata !"clang version 2.9 (trunk 113428)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 524329, metadata !"lv.c", metadata !"dbg_info_bugs", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"lv.c", metadata !"dbg_info_bugs", metadata !"clang version 2.9 (trunk 113428)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] Modified: debuginfo-tests/trunk/local-var2.ll URL: http://llvm.org/viewvc/llvm-project/debuginfo-tests/trunk/local-var2.ll?rev=132375&r1=132374&r2=132375&view=diff ============================================================================== --- debuginfo-tests/trunk/local-var2.ll (original) +++ debuginfo-tests/trunk/local-var2.ll Tue May 31 18:57:48 2011 @@ -73,8 +73,8 @@ !llvm.dbg.sp = !{!0, !6, !7, !8, !9} !0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"f1", metadata !"f1", metadata !"f1", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 false, i32 ()* @f1} ; [ DW_TAG_subprogram ] -!1 = metadata !{i32 524329, metadata !"lv.c", metadata !"/Users/manav/dbg_info_bugs", metadata !2} ; [ DW_TAG_file_type ] -!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"lv.c", metadata !"/Users/manav/dbg_info_bugs", metadata !"clang version 2.9 (trunk 113428)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 524329, metadata !"lv.c", metadata !"dbg_info_bugs", metadata !2} ; [ DW_TAG_file_type ] +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"lv.c", metadata !"dbg_info_bugs", metadata !"clang version 2.9 (trunk 113428)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] !3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} ; [ DW_TAG_subroutine_type ] !4 = metadata !{metadata !5} !5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] From evan.cheng at apple.com Tue May 31 19:26:23 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 31 May 2011 17:26:23 -0700 Subject: [llvm-commits] [cfe-commits] [PATCH] ARM pli builtin and intrinsic In-Reply-To: References: <9A520CD3-C0EC-4847-9912-13BCF7F2C1AE@apple.com> Message-ID: On May 31, 2011, at 4:55 PM, Eric Christopher wrote: > > On May 31, 2011, at 4:46 PM, Evan Cheng wrote: > >> How about __builtin_instruction_prefetch? Or is too long? >> >> Evan >> >> On May 31, 2011, at 3:38 PM, Bruno Cardoso Lopes wrote: >> >>>> Adding another argument to @llvm.prefetch is fine. But what do you propose for C level builtin? >>> >>> __builtin_iprefetch or __builtin_icache_prefetch, with an address >>> argument only, either are fine for me. What's your opinion? >>> > > FWIW I like __builtin_iprefetch. It's a shame the original prefetch wasn't __builtin_dprefetch. > > If we wanted some symmetry we could have both __builtin_icache_prefetch and __builtin_dcache_prefetch, the second being an alias to the existing __builtin_prefetch. I don't have a strong preference. All of these names seem fine. Evan > > -eric > From dpatel at apple.com Tue May 31 19:23:24 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 01 Jun 2011 00:23:24 -0000 Subject: [llvm-commits] [llvm] r132377 - in /llvm/trunk/lib/CodeGen/AsmPrinter: DwarfCompileUnit.cpp DwarfCompileUnit.h Message-ID: <20110601002324.900742A6C12C@llvm.org> Author: dpatel Date: Tue May 31 19:23:24 2011 New Revision: 132377 URL: http://llvm.org/viewvc/llvm-project?rev=132377&view=rev Log: Incomplete type may not have corresponding DIE, so do not check DIEEntry eagerly. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=132377&r1=132376&r2=132377&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Tue May 31 19:23:24 2011 @@ -609,16 +609,17 @@ // If this is a complete composite type then include it in the // list of global types. - addGlobalType(Ty, Entry->getEntry()); + addGlobalType(Ty); } /// addGlobalType - Add a new global type to the compile unit. /// -void CompileUnit::addGlobalType(DIType Ty, DIE *Die) { +void CompileUnit::addGlobalType(DIType Ty) { DIDescriptor Context = Ty.getContext(); if (Ty.isCompositeType() && !Ty.getName().empty() && !Ty.isForwardDecl() && (Context.isCompileUnit() || Context.isFile() || Context.isNameSpace())) - GlobalTypes[Ty.getName()] = Die; + if (DIEEntry *Entry = getDIEEntry(Ty)) + GlobalTypes[Ty.getName()] = Entry->getEntry(); } /// addPubTypes - Add type for pubtypes section. @@ -633,7 +634,7 @@ DIType ATy(Args.getElement(i)); if (!ATy.Verify()) continue; - addGlobalType(ATy, getDIEEntry(ATy)->getEntry()); + addGlobalType(ATy); } } Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=132377&r1=132376&r2=132377&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Tue May 31 19:23:24 2011 @@ -87,7 +87,7 @@ /// addGlobalType - Add a new global type to the compile unit. /// - void addGlobalType(DIType Ty, DIE *Die); + void addGlobalType(DIType Ty); /// getDIE - Returns the debug information entry map slot for the /// specified debug variable. From aggarwa4 at illinois.edu Tue May 31 19:36:55 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 01 Jun 2011 00:36:55 -0000 Subject: [llvm-commits] [poolalloc] r132378 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110601003655.990ED2A6C12C@llvm.org> Author: aggarwa4 Date: Tue May 31 19:36:55 2011 New Revision: 132378 URL: http://llvm.org/viewvc/llvm-project?rev=132378&view=rev Log: Assume stdout,stderr and stdin have been initialized. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132378&r1=132377&r2=132378&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue May 31 19:36:55 2011 @@ -867,6 +867,20 @@ I != E; ++I) { if(I->use_empty()) continue; + if(I->getNameStr() == "stderr" || + I->getNameStr() == "stdout" || + I->getNameStr() == "stdin") { + // assume initialized + CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy, "", InsertPt); + std::vector Args; + Args.push_back(BCI); + unsigned int size = TD->getTypeStoreSize(I->getType()->getElementType()); + Args.push_back(ConstantInt::get(Int64Ty, size)); + Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Constant *F = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); + CallInst::Create(F, Args.begin(), Args.end(), "", InsertPt); + continue; + } if(!I->hasInitializer()) continue; visitGlobal(M, *I, I->getInitializer(), *InsertPt, 0); From ahatanak at gmail.com Tue May 31 20:05:37 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Tue, 31 May 2011 18:05:37 -0700 Subject: [llvm-commits] [patch] Drop DwarfRegNum from the D registers In-Reply-To: <4DDFC6CA.6030709@gmail.com> References: <4DDFC6CA.6030709@gmail.com> Message-ID: Could you tell me what I need to add/change in MipsFrameLowering::emitPrologue in order to emit the correct cfi_offset directives when double precision callee-saved registers are saved? Currently, the following directive gets emitted when double register $f20 is saved, .cfi_offset -1, -8 instead of something like this: .cfi_offset 53, -4 .cfi_offset 52, -8 Should I just push back two MachineMoves (one for each of the paired single precision registers)? Thank you. On Fri, May 27, 2011 at 8:44 AM, Rafael Avila de Espindola < rafael.espindola at gmail.com> wrote: > If I understand it correctly, the proper way to encode a D register in > DWARF is with something like > > DW_OP_reg 32 DW_OP_piece 4 DW_OP_reg 33 > > The attached patch drops the DwarfRegNum from the D registers. Is it OK? > > Cheers, > Rafael > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110531/f5d733ab/attachment.html From isanbard at gmail.com Tue May 31 20:49:35 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 01 Jun 2011 01:49:35 -0000 Subject: [llvm-commits] [llvm] r132381 - /llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Message-ID: <20110601014935.970632A6C12C@llvm.org> Author: void Date: Tue May 31 20:49:35 2011 New Revision: 132381 URL: http://llvm.org/viewvc/llvm-project?rev=132381&view=rev Log: The ARM stuff already calls the Resume function, not the Resume_or_Rethrow. It turns out that it could cause an infinite loop in some situations. If this code is triggered and it converts a cleanup into a catchall, but that cleanup was in already in a cleanup, then the _Unwind_SjLj_Resume could infinite loop. I.e., the code doesn't consume the exception object and passes it on to _Unwind_SjLj_Resume. But _USjLjR expects it to be consumed (since it's landing at a catchall instead of a cleanup). So it uses the values that are presently there, which are the values that tell it to jump to the fake landing pad. Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Modified: llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp?rev=132381&r1=132380&r2=132381&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp (original) +++ llvm/trunk/lib/CodeGen/DwarfEHPrepare.cpp Tue May 31 20:49:35 2011 @@ -252,10 +252,7 @@ if (!URoR) { URoR = F->getParent()->getFunction("_Unwind_Resume_or_Rethrow"); - if (!URoR) { - URoR = F->getParent()->getFunction("_Unwind_SjLj_Resume"); - if (!URoR) return CleanupSelectors(CatchAllSels); - } + if (!URoR) return CleanupSelectors(CatchAllSels); } SmallPtrSet URoRInvokes; From rjmccall at apple.com Tue May 31 21:17:11 2011 From: rjmccall at apple.com (John McCall) Date: Wed, 01 Jun 2011 02:17:11 -0000 Subject: [llvm-commits] [llvm] r132382 - in /llvm/trunk: lib/Transforms/Utils/InlineFunction.cpp test/Transforms/Inline/inline_invoke.ll Message-ID: <20110601021711.9260C2A6C12C@llvm.org> Author: rjmccall Date: Tue May 31 21:17:11 2011 New Revision: 132382 URL: http://llvm.org/viewvc/llvm-project?rev=132382&view=rev Log: First, do no harm -- even if we can't find a selector for an enclosing landing pad, forward llvm.eh.resume calls to it instead of turning them invalidly into invokes. Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp llvm/trunk/test/Transforms/Inline/inline_invoke.ll Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=132382&r1=132381&r2=132382&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Tue May 31 21:17:11 2011 @@ -214,13 +214,24 @@ /// at the end of the given block, as a branch to the inner unwind /// block. Returns true if the call was forwarded. bool InvokeInliningInfo::forwardEHResume(CallInst *call, BasicBlock *src) { + // First, check whether this is a call to the intrinsic. Function *fn = dyn_cast(call->getCalledValue()); if (!fn || fn->getName() != "llvm.eh.resume") return false; + + // At this point, we need to return true on all paths, because + // otherwise we'll construct an invoke of the intrinsic, which is + // not well-formed. - // If this fails, maybe it should be a fatal error. + // Try to find or make an inner unwind dest, which will fail if we + // can't find a selector call for the outer unwind dest. BasicBlock *dest = getInnerUnwindDest(); - if (!dest) return false; + bool hasSelector = (dest != 0); + + // If we failed, just use the outer unwind dest, dropping the + // exception and selector on the floor. + if (!hasSelector) + dest = OuterUnwindDest; // Make a branch. BranchInst::Create(dest, src); @@ -228,8 +239,11 @@ // Update the phis in the destination. They were inserted in an // order which makes this work. addIncomingPHIValuesForInto(src, dest); - InnerExceptionPHI->addIncoming(call->getArgOperand(0), src); - InnerSelectorPHI->addIncoming(call->getArgOperand(1), src); + + if (hasSelector) { + InnerExceptionPHI->addIncoming(call->getArgOperand(0), src); + InnerSelectorPHI->addIncoming(call->getArgOperand(1), src); + } return true; } Modified: llvm/trunk/test/Transforms/Inline/inline_invoke.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/Inline/inline_invoke.ll?rev=132382&r1=132381&r2=132382&view=diff ============================================================================== --- llvm/trunk/test/Transforms/Inline/inline_invoke.ll (original) +++ llvm/trunk/test/Transforms/Inline/inline_invoke.ll Tue May 31 21:17:11 2011 @@ -4,7 +4,7 @@ ; by appending selectors and forwarding _Unwind_Resume directly to the ; enclosing landing pad. -;; Test 1 - basic functionality. +;; Test 0 - basic functionality. %struct.A = type { i8 } @@ -112,7 +112,7 @@ ; CHECK-NEXT: call i32 @llvm.eh.typeid.for( -;; Test 2 - Correctly handle phis in outer landing pads. +;; Test 1 - Correctly handle phis in outer landing pads. define void @test1_out() uwtable ssp { entry: @@ -216,3 +216,30 @@ ; CHECK: call void @use(i32 [[YJ1]]) ; CHECK: call void @llvm.eh.resume(i8* [[EXNJ1]], i32 [[SELJ1]]) + +;; Test 2 - Don't make invalid IR for inlines into landing pads without eh.exception calls + +define void @test2_out() uwtable ssp { +entry: + invoke void @test0_in() + to label %ret unwind label %lpad + +ret: + ret void + +lpad: + call void @_ZSt9terminatev() + unreachable +} + +; CHECK: define void @test2_out() +; CHECK: [[A:%.*]] = alloca %struct.A, +; CHECK: [[B:%.*]] = alloca %struct.A, +; CHECK: invoke void @_ZN1AC1Ev(%struct.A* [[A]]) +; CHECK-NEXT: unwind label %[[LPAD:[^\s]+]] +; CHECK: invoke void @_ZN1AC1Ev(%struct.A* [[B]]) +; CHECK-NEXT: unwind label %[[LPAD2:[^\s]+]] +; CHECK: invoke void @_ZN1AD1Ev(%struct.A* [[B]]) +; CHECK-NEXT: unwind label %[[LPAD2]] +; CHECK: invoke void @_ZN1AD1Ev(%struct.A* [[A]]) +; CHECK-NEXT: unwind label %[[LPAD]] From bruno.cardoso at gmail.com Tue May 31 21:32:47 2011 From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes) Date: Tue, 31 May 2011 23:32:47 -0300 Subject: [llvm-commits] [cfe-commits] [PATCH] ARM pli builtin and intrinsic In-Reply-To: References: <9A520CD3-C0EC-4847-9912-13BCF7F2C1AE@apple.com> Message-ID: >> FWIW I like __builtin_iprefetch. It's a shame the original prefetch wasn't __builtin_dprefetch. Indeed. >> If we wanted some symmetry we could have both __builtin_icache_prefetch and __builtin_dcache_prefetch, the second being an alias to the existing __builtin_prefetch. I'm also fine with all options. Since I also like the __builtin_iprefetch, I'll pick it then, we can change it later if needed. > I don't have a strong preference. All of these names seem fine. Nice! -- Bruno Cardoso Lopes http://www.brunocardoso.cc From rafael.espindola at gmail.com Tue May 31 21:42:44 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 31 May 2011 22:42:44 -0400 Subject: [llvm-commits] [patch] Drop DwarfRegNum from the D registers In-Reply-To: References: <4DDFC6CA.6030709@gmail.com> Message-ID: <4DE5A724.3030004@gmail.com> On 11-05-31 9:05 PM, Akira Hatanaka wrote: > Could you tell me what I need to add/change in > MipsFrameLowering::emitPrologue in order to emit the correct cfi_offset > directives when double precision callee-saved registers are saved? > Currently, the following directive gets emitted when double register > $f20 is saved, > .cfi_offset -1, -8 > > instead of something like this: > .cfi_offset 53, -4 > .cfi_offset 52, -8 > > Should I just push back two MachineMoves (one for each of the paired > single precision registers)? I think so. The two options I can think of are creating two MachineMoves or expanding one into two cfi directives. We should probably move to model were the cfi instructions have a more direct representation in the machine instructions, so creating two MachineMoves is probably the right thing to do. > Thank you. Thanks, Rafael From aggarwa4 at illinois.edu Tue May 31 22:16:52 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 01 Jun 2011 03:16:52 -0000 Subject: [llvm-commits] [poolalloc] r132384 - in /poolalloc/trunk/test: TEST.types.Makefile TEST.types.report Message-ID: <20110601031652.DD7DC2A6C12C@llvm.org> Author: aggarwa4 Date: Tue May 31 22:16:52 2011 New Revision: 132384 URL: http://llvm.org/viewvc/llvm-project?rev=132384&view=rev Log: Add test run for disable-ptr-types Modified: poolalloc/trunk/test/TEST.types.Makefile poolalloc/trunk/test/TEST.types.report Modified: poolalloc/trunk/test/TEST.types.Makefile URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.types.Makefile?rev=132384&r1=132383&r2=132384&view=diff ============================================================================== --- poolalloc/trunk/test/TEST.types.Makefile (original) +++ poolalloc/trunk/test/TEST.types.Makefile Tue May 31 22:16:52 2011 @@ -61,6 +61,11 @@ -$(LLVMLD) -disable-opt -o $@.ld $@.temp $(TYPE_RT_BC) -$(LOPT) $(SAFE_OPTS) $@.ld.bc -o $@ -f +$(PROGRAMS_TO_TEST:%=Output/%.tcd.bc): \ +Output/%.tcd.bc: Output/%.opt.bc $(LOPT) $(ASSIST_SO) + -$(RUNOPT) -load $(ASSIST_SO) -typechecks -disable-ptr-type-checks -dce -ipsccp -dce -stats -info-output-file=$(CURDIR)/$@.info $< -f -o $@.temp + -$(LLVMLD) -disable-opt -o $@.ld $@.temp $(TYPE_RT_BC) + -$(LOPT) $(SAFE_OPTS) $@.ld.bc -o $@ -f $(PROGRAMS_TO_TEST:%=Output/%.tco.bc): \ Output/%.tco.bc: Output/%.opt.bc $(LOPT) $(ASSIST_SO) @@ -89,6 +94,9 @@ $(PROGRAMS_TO_TEST:%=Output/%.tc.s): \ Output/%.tc.s: Output/%.tc.bc $(LLC) -$(LLC) $< -o $@ +$(PROGRAMS_TO_TEST:%=Output/%.tcd.s): \ +Output/%.tcd.s: Output/%.tcd.bc $(LLC) + -$(LLC) $< -o $@ $(PROGRAMS_TO_TEST:%=Output/%.tco.s): \ Output/%.tco.s: Output/%.tco.bc $(LLC) -$(LLC) $< -o $@ @@ -102,6 +110,9 @@ $(PROGRAMS_TO_TEST:%=Output/%.tc): \ Output/%.tc: Output/%.tc.s $(TYPE_RT_O) -$(CC) $(CFLAGS) $< $(LLCLIBS) $(TYPE_RT_O) $(LDFLAGS) -o $@ +$(PROGRAMS_TO_TEST:%=Output/%.tcd): \ +Output/%.tcd: Output/%.tcd.s $(TYPE_RT_O) + -$(CC) $(CFLAGS) $< $(LLCLIBS) $(TYPE_RT_O) $(LDFLAGS) -o $@ $(PROGRAMS_TO_TEST:%=Output/%.tco): \ Output/%.tco: Output/%.tco.s $(TYPE_RT_O) -$(CC) $(CFLAGS) $< $(LLCLIBS) $(TYPE_RT_O) $(LDFLAGS) -o $@ @@ -137,6 +148,9 @@ $(PROGRAMS_TO_TEST:%=Output/%.out-tc): \ Output/%.out-tc: Output/%.tc -$(RUNSAFELY) $(STDIN_FILENAME) $@ $< $(RUN_OPTIONS) +$(PROGRAMS_TO_TEST:%=Output/%.out-tcd): \ +Output/%.out-tcd: Output/%.tcd + -$(RUNSAFELY) $(STDIN_FILENAME) $@ $< $(RUN_OPTIONS) $(PROGRAMS_TO_TEST:%=Output/%.out-tco): \ Output/%.out-tco: Output/%.tco -$(RUNSAFELY) $(STDIN_FILENAME) $@ $< $(RUN_OPTIONS) @@ -166,6 +180,13 @@ ../../$< $(RUN_OPTIONS) -(cd Output/tc-$(RUN_TYPE); cat $(LOCAL_OUTPUTS)) > $@ -cp Output/tc-$(RUN_TYPE)/$(STDOUT_FILENAME).time $@.time +$(PROGRAMS_TO_TEST:%=Output/%.out-tcd): \ +Output/%.out-tcd: Output/%.tcd + -$(SPEC_SANDBOX) tcd-$(RUN_TYPE) $@ $(REF_IN_DIR) \ + $(RUNSAFELY) $(STDIN_FILENAME) $(STDOUT_FILENAME) \ + ../../$< $(RUN_OPTIONS) + -(cd Output/tcd-$(RUN_TYPE); cat $(LOCAL_OUTPUTS)) > $@ + -cp Output/tcd-$(RUN_TYPE)/$(STDOUT_FILENAME).time $@.time $(PROGRAMS_TO_TEST:%=Output/%.out-tco): \ Output/%.out-tco: Output/%.tco -$(SPEC_SANDBOX) tco-$(RUN_TYPE) $@ $(REF_IN_DIR) \ @@ -207,6 +228,10 @@ Output/%.diff-tc: Output/%.out-nat Output/%.out-tc -$(DIFFPROG) tc $* $(HIDEDIFF) +$(PROGRAMS_TO_TEST:%=Output/%.diff-tcd): \ +Output/%.diff-tcd: Output/%.out-nat Output/%.out-tcd + -$(DIFFPROG) tcd $* $(HIDEDIFF) + $(PROGRAMS_TO_TEST:%=Output/%.diff-tco): \ Output/%.diff-tco: Output/%.out-nat Output/%.out-tco -$(DIFFPROG) tco $* $(HIDEDIFF) @@ -229,7 +254,7 @@ $(PROGRAMS_TO_TEST:%=Output/%.$(TEST).report.txt): \ -Output/%.$(TEST).report.txt: Output/%.opt.bc Output/%.LOC.txt $(LOPT) Output/%.out-nat Output/%.diff-llvm1 Output/%.diff-opt Output/%.diff-tc Output/%.diff-tco Output/%.diff-tcoo Output/%.diff-count Output/%.diff-count1 +Output/%.$(TEST).report.txt: Output/%.opt.bc Output/%.LOC.txt $(LOPT) Output/%.out-nat Output/%.diff-llvm1 Output/%.diff-opt Output/%.diff-tc Output/%.diff-tcd Output/%.diff-tco Output/%.diff-tcoo Output/%.diff-count Output/%.diff-count1 @# Gather data -($(RUNOPT) -dsa-$(PASS) -enable-type-inference-opts -dsa-stdlib-no-fold $(ANALYZE_OPTS) $<)> $@.time.1 2>&1 -($(RUNOPT) -dsa-$(PASS) $(ANALYZE_OPTS) $<)> $@.time.2 2>&1 @@ -331,6 +356,10 @@ printf "TC-RUN_TIME: " >> $@;\ grep 'program' Output/$*.out-tc.time >> $@;\ fi + @-if test -f Output/$*.diff-tcd; then \ + printf "TCD-RUN_TIME: " >> $@;\ + grep 'program' Output/$*.out-tcd.time >> $@;\ + fi @-if test -f Output/$*.diff-tco; then \ printf "TCO-RUN_TIME: " >> $@;\ grep 'program' Output/$*.out-tco.time >> $@;\ Modified: poolalloc/trunk/test/TEST.types.report URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.types.report?rev=132384&r1=132383&r2=132384&view=diff ============================================================================== --- poolalloc/trunk/test/TEST.types.report (original) +++ poolalloc/trunk/test/TEST.types.report Tue May 31 22:16:52 2011 @@ -143,11 +143,11 @@ [], ["TypeSafeO", "ACCESSES TYPED_O: *([0-9]+)"], ["NonTypeO", "ACCESSES UNTYPED_O: *([0-9]+)"], - ["TSO %" , sub { return TypeSafeRatio(@_); }], + ["TSO%" , sub { return TypeSafeRatio(@_); }], [], ["TypeSafe", "ACCESSES TYPED: *([0-9]+)"], ["NonType", "ACCESSES UNTYPED: *([0-9]+)"], - ["TS %" , sub { return TypeSafeRatio(@_); }], + ["TS%" , sub { return TypeSafeRatio(@_); }], [], ["Ign", "IGN: *([0-9]+)"], ["GEP-Ign", "GEPI: *([0-9]+)"], @@ -177,17 +177,18 @@ [], ["DTotal", "DTOTAL: *([0-9]+)"], ["DSafe", "DSAFE: *([0-9]+)"], - ["DTS %" , sub { return Ratio(@_); }], + ["DTS%" , sub { return Ratio(@_); }], [], ["DTotalO", "DTOTALO: *([0-9]+)"], ["DSafeO", "DSAFEO: *([0-9]+)"], - ["DTS %" , sub { return Ratio(@_); }], + ["DTS%" , sub { return Ratio(@_); }], #[], #["LoadChk", "LCHK: *([0-9]+)"], #["StoreChk", "SCHK: *([0-9]+)"], [], ["OptTime", "OPT-RUN_TIME: program *([.0-9]+)"], ["TcTime", "TC-RUN_TIME: program *([.0-9]+)"], + ["TcdTime", "TCD-RUN_TIME: program *([.0-9]+)"], ["TcoTime", "TCO-RUN_TIME: program *([.0-9]+)"], ["TcooTime", "TCOO-RUN_TIME: program *([.0-9]+)"], ); From atrick at apple.com Tue May 31 22:27:56 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 01 Jun 2011 03:27:56 -0000 Subject: [llvm-commits] [llvm] r132385 - /llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Message-ID: <20110601032756.306852A6C12C@llvm.org> Author: atrick Date: Tue May 31 22:27:56 2011 New Revision: 132385 URL: http://llvm.org/viewvc/llvm-project?rev=132385&view=rev Log: Add an issue width check to the postRA scheduler. Patch by Max Kazakov! For targets with no itinerary (x86) it is a nop by default. For targets with issue width already expressed in the itinerary (ARM) it bypasses a scoreboard check but otherwise does not affect the schedule. It does make the code more consistent and complete and allows new targets to specify their issue width in an arbitrary way. Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=132385&r1=132384&r2=132385&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Tue May 31 22:27:56 2011 @@ -661,6 +661,12 @@ ScheduleNodeTopDown(FoundSUnit, CurCycle); HazardRec->EmitInstruction(FoundSUnit); CycleHasInsts = true; + if (HazardRec->atIssueLimit()) { + DEBUG(dbgs() << "*** Max instructions per cycle " << CurCycle << '\n'); + HazardRec->AdvanceCycle(); + ++CurCycle; + CycleHasInsts = false; + } } else { if (CycleHasInsts) { DEBUG(dbgs() << "*** Finished cycle " << CurCycle << '\n'); From stuart at apple.com Tue May 31 23:39:42 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 04:39:42 -0000 Subject: [llvm-commits] [llvm] r132388 - in /llvm/trunk: include/llvm/Target/TargetSelectionDAG.td lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrSSE.td Message-ID: <20110601043943.36F4E2A6C12C@llvm.org> Author: stuart Date: Tue May 31 23:39:42 2011 New Revision: 132388 URL: http://llvm.org/viewvc/llvm-project?rev=132388&view=rev Log: FGETSIGN support for x86, using movmskps/pd. Will be enabled with a patch to TargetLowering.cpp. rdar://problem/5660695 Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrSSE.td Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=132388&r1=132387&r2=132388&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original) +++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Tue May 31 23:39:42 2011 @@ -354,6 +354,7 @@ def fdiv : SDNode<"ISD::FDIV" , SDTFPBinOp>; def frem : SDNode<"ISD::FREM" , SDTFPBinOp>; def fabs : SDNode<"ISD::FABS" , SDTFPUnaryOp>; +def fgetsign : SDNode<"ISD::FGETSIGN" , SDTFPToIntOp>; def fneg : SDNode<"ISD::FNEG" , SDTFPUnaryOp>; def fsqrt : SDNode<"ISD::FSQRT" , SDTFPUnaryOp>; def fsin : SDNode<"ISD::FSIN" , SDTFPUnaryOp>; Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=132388&r1=132387&r2=132388&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue May 31 23:39:42 2011 @@ -574,6 +574,10 @@ setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); + // Lower this to FGETSIGNx86 plus an AND. + setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); + setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); + // We don't support sin/cos/fmod setOperationAction(ISD::FSIN , MVT::f64, Expand); setOperationAction(ISD::FCOS , MVT::f64, Expand); @@ -7215,6 +7219,17 @@ return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); } +SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { + SDValue N0 = Op.getOperand(0); + DebugLoc dl = Op.getDebugLoc(); + EVT VT = Op.getValueType(); + + // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). + SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, + DAG.getConstant(1, VT)); + return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); +} + /// Emit nodes that will be selected as "test Op0,Op0", or something /// equivalent. SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, @@ -9186,6 +9201,7 @@ case ISD::FABS: return LowerFABS(Op, DAG); case ISD::FNEG: return LowerFNEG(Op, DAG); case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); + case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); case ISD::SETCC: return LowerSETCC(Op, DAG); case ISD::VSETCC: return LowerVSETCC(Op, DAG); case ISD::SELECT: return LowerSELECT(Op, DAG); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=132388&r1=132387&r2=132388&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Tue May 31 23:39:42 2011 @@ -94,6 +94,10 @@ // one's or all zero's. SETCC_CARRY, // R = carry_bit ? ~0 : 0 + /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, + /// result in an integer GPR. Needs masking for scalar result. + FGETSIGNx86, + /// X86 conditional moves. Operand 0 and operand 1 are the two values /// to select from. Operand 2 is the condition code, and operand 3 is the /// flag operand produced by a CMP or TEST instruction. It also writes a @@ -783,6 +787,7 @@ SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const; SDValue LowerToBT(SDValue And, ISD::CondCode CC, DebugLoc dl, SelectionDAG &DAG) const; SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const; Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=132388&r1=132387&r2=132388&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Tue May 31 23:39:42 2011 @@ -38,6 +38,7 @@ def X86frsqrt : SDNode<"X86ISD::FRSQRT", SDTFPUnaryOp>; def X86frcp : SDNode<"X86ISD::FRCP", SDTFPUnaryOp>; def X86fsrl : SDNode<"X86ISD::FSRL", SDTX86FPShiftOp>; +def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; def X86pshufb : SDNode<"X86ISD::PSHUFB", Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=132388&r1=132387&r2=132388&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue May 31 23:39:42 2011 @@ -1327,11 +1327,6 @@ } // Mask creation -defm MOVMSKPS : sse12_extr_sign_mask, TB; -defm MOVMSKPD : sse12_extr_sign_mask, TB, OpSize; - defm VMOVMSKPS : sse12_extr_sign_mask, VEX; defm VMOVMSKPD : sse12_extr_sign_mask, OpSize, VEX; +defm MOVMSKPS : sse12_extr_sign_mask, TB; +defm MOVMSKPD : sse12_extr_sign_mask, TB, OpSize; + +// X86fgetsign +def MOVMSKPDrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR64:$src), + "movmskpd\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize; +def MOVMSKPDrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR64:$src), + "movmskpd\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (X86fgetsign FR64:$src))], SSEPackedDouble>, TB, OpSize; +def MOVMSKPSrr32_alt : PI<0x50, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src), + "movmskps\t{$src, $dst|$dst, $src}", + [(set GR32:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB; +def MOVMSKPSrr64_alt : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins FR32:$src), + "movmskps\t{$src, $dst|$dst, $src}", + [(set GR64:$dst, (X86fgetsign FR32:$src))], SSEPackedSingle>, TB; // Assembler Only def VMOVMSKPSr64r : PI<0x50, MRMSrcReg, (outs GR64:$dst), (ins VR128:$src), From clattner at apple.com Wed Jun 1 00:49:08 2011 From: clattner at apple.com (Chris Lattner) Date: Tue, 31 May 2011 22:49:08 -0700 Subject: [llvm-commits] [PATCH] ARM pli builtin and intrinsic In-Reply-To: <9A520CD3-C0EC-4847-9912-13BCF7F2C1AE@apple.com> References: <9A520CD3-C0EC-4847-9912-13BCF7F2C1AE@apple.com> Message-ID: <807BF975-ADDC-4ABF-A813-A1037704C40E@apple.com> On May 31, 2011, at 4:46 PM, Evan Cheng wrote: > How about __builtin_instruction_prefetch? Or is too long? __builtin_prefetch_icache? -Chris > > Evan > > On May 31, 2011, at 3:38 PM, Bruno Cardoso Lopes wrote: > >>> Adding another argument to @llvm.prefetch is fine. But what do you propose for C level builtin? >> >> __builtin_iprefetch or __builtin_icache_prefetch, with an address >> argument only, either are fine for me. What's your opinion? >> >> >> -- >> Bruno Cardoso Lopes >> http://www.brunocardoso.cc > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From nadav.rotem at intel.com Wed Jun 1 01:39:22 2011 From: nadav.rotem at intel.com (Rotem, Nadav) Date: Wed, 1 Jun 2011 09:39:22 +0300 Subject: [llvm-commits] [PATCH] Type-legalizer - Add flag to enable new legalization kind Message-ID: <6594DDFF12B03D4E89690887C2486994027D91951A@hasmsx504.ger.corp.intel.com> Hi, This patch is another step in the direction of adding vector select[1]. The general direction is to add a new kind of type legalization: ?integer-promote? on vector elements. In this patch I added a flag to enable the new decision. In the next patches I will add the implementation to the new legalization in other parts of the kernel. This flag will be removed when the transition is complete. The implementation of the flag is a bit awkward?because we need to overcome the circular dependency problem. Nadav [1] - http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20110502/120445.html --------------------------------------------------------------------- Intel Israel (74) Limited This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). Any review or distribution by others is strictly prohibited. If you are not the intended recipient, please contact the sender and delete all copies. -------------- next part -------------- A non-text attachment was scrubbed... Name: llvm_flag.diff Type: application/octet-stream Size: 6733 bytes Desc: llvm_flag.diff Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110601/cc38a6eb/attachment.obj From baldrick at free.fr Wed Jun 1 01:56:44 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 01 Jun 2011 08:56:44 +0200 Subject: [llvm-commits] [llvm-gcc-4.2] r132366 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <20110531220830.960642A6C12C@llvm.org> References: <20110531220830.960642A6C12C@llvm.org> Message-ID: <4DE5E2AC.4060305@free.fr> Hi Eric, > Look through struct wrapped types when deciding whether or not it's a > simple emit for the input constraints in an inline asm. testcase? Ciao, Duncan. From baldrick at free.fr Wed Jun 1 02:24:32 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 01 Jun 2011 09:24:32 +0200 Subject: [llvm-commits] [llvm] r132360 - in /llvm/trunk: lib/Analysis/ScalarEvolution.cpp test/Transforms/IndVarSimplify/elim-extend.ll In-Reply-To: <20110531211747.AC6D62A6C12C@llvm.org> References: <20110531211747.AC6D62A6C12C@llvm.org> Message-ID: <4DE5E930.6020505@free.fr> Hi Andrew, > scev: Better sign-extend removal. Normalize postincrement recurrences > so that their sign extended forms are congruent when no overflow occurs. it looks like this broke the x86-64 dragonegg buildbot: http://google1.osuosl.org:8011/builders/dragonegg-x86_64-linux/builds/1606 You can reproduce the issue by running "opt -O2" on the attached IR. Ciao, Duncan. -------------- next part -------------- A non-text attachment was scrubbed... Name: dwarf2out.ll.gz Type: application/x-gzip Size: 1033923 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110601/0d66beed/attachment-0001.gz From baldrick at free.fr Wed Jun 1 06:04:23 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 01 Jun 2011 13:04:23 +0200 Subject: [llvm-commits] [PATCH] Type-legalizer - Add flag to enable new legalization kind In-Reply-To: <6594DDFF12B03D4E89690887C2486994027D91951A@hasmsx504.ger.corp.intel.com> References: <6594DDFF12B03D4E89690887C2486994027D91951A@hasmsx504.ger.corp.intel.com> Message-ID: <4DE61CB7.1070704@free.fr> Hi Nadav, > Index: ../llvm/test/CodeGen/Generic/promote-integers.ll > =================================================================== > --- ../llvm/test/CodeGen/Generic/promote-integers.ll (revision 0) > +++ ../llvm/test/CodeGen/Generic/promote-integers.ll (revision 0) > @@ -0,0 +1,15 @@ > +; Test that vectors are scalarized/lowered correctly. > +; RUN: llc -march=x86 -promote-elements < %s > + > +; This test is the poster-child for integer-element-promotion. > +; Until this feature is complete, we mark this test as expected to fail. > +; XFAIL: * > +; CHECK: vector_code > +; CHECK: ret since you are not running FileCheck, these CHECK lines are useless. > --- ../llvm/include/llvm/Target/TargetLowering.h (revision 132345) > +++ ../llvm/include/llvm/Target/TargetLowering.h (working copy) > @@ -35,6 +35,10 @@ > #include > #include > > + > + > + > + What's with the blank lines? > + // Try to promote the integer element types Missing full stop. Also, rather than just saying "try" please explain when this works and what is done when it fails. > + while (1) { > + // Promote the element type Missing full stop. Please explain how it is promoted: round the number of bits up to the next power of 2, or to 8 bits, whichever is larger. > + EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits() > + ).getRoundIntegerType(Context); > + > + // Stop trying when getting an illegal element type > + if (!EltVT.isSimple()) break; Maybe you should just loop over the simple integer types... > + // Empty comment. > + MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); > + if (ValueTypeActions.getTypeAction(NVT) == TypeLegal) { > + // Found a legal widended vector type Missing full stop. It's a promoted vector type, not a widened one. > + return LegalizeKind(TypePromoteInteger, > + EVT::getVectorVT(Context, EltVT, NumElts)); > + } There was no need for these curly brackets. > + } > + } > + > // Try to widen the vector until a legal type is found. > // If there is no wider legal type, split the vector. > while (1) { > --- ../llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (revision 132345) > +++ ../llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp (working copy) > @@ -814,6 +823,24 @@ > bool IsLegalWiderType = false; > for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { > EVT SVT = (MVT::SimpleValueType)nVT; > + > + // If we allow the promotion of vector elements using a flag, > + // then return TypePromoteInteger on vector elements. > + if (mayPromoteElements) { > + // Promote vectors of integers to vectors with the same number > + // of elements, with a wider element type. > + if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() > + && SVT.getVectorNumElements() == NElts && > + isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { > + TransformToType[i] = SVT; > + RegisterTypeForVT[i] = SVT; > + NumRegistersForVT[i] = 1; > + ValueTypeActions.setTypeAction(VT, TypePromoteInteger); > + IsLegalWiderType = true; > + break; > + } > + } > + > if (SVT.getVectorElementType() == EltVT && > SVT.getVectorNumElements() > NElts && > isTypeLegal(SVT)) { It would be great if all type computation logic could be unified... > @@ -3290,3 +3317,6 @@ > DAG.getConstant(magics.s-1, getShiftAmountTy(NPQ.getValueType()))); > } > } > + > + > + What's with the blank lines? Ciao, Duncan. From baldrick at free.fr Wed Jun 1 07:10:01 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 01 Jun 2011 12:10:01 -0000 Subject: [llvm-commits] [dragonegg] r132393 - in /dragonegg/trunk/src/x86: Target.cpp x86_builtins Message-ID: <20110601121001.609CC2A6C12C@llvm.org> Author: baldrick Date: Wed Jun 1 07:10:01 2011 New Revision: 132393 URL: http://llvm.org/viewvc/llvm-project?rev=132393&view=rev Log: GCC treats sqrtps_nr exactly the same as sqrtps, so do the same. Modified: dragonegg/trunk/src/x86/Target.cpp dragonegg/trunk/src/x86/x86_builtins Modified: dragonegg/trunk/src/x86/Target.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/x86/Target.cpp?rev=132393&r1=132392&r2=132393&view=diff ============================================================================== --- dragonegg/trunk/src/x86/Target.cpp (original) +++ dragonegg/trunk/src/x86/Target.cpp Wed Jun 1 07:10:01 2011 @@ -781,7 +781,10 @@ case sqrtps: case sqrtps256: case sqrtsd: - case sqrtss: { + case sqrtss: + // No need for a Newton-Raphson step - sqrtps is already accurate. + case sqrtps_nr: + case sqrtps_nr256: { const Type *Ty = Ops[0]->getType(); Function *sqrt = Intrinsic::getDeclaration(TheModule, Intrinsic::sqrt, &Ty, 1); Modified: dragonegg/trunk/src/x86/x86_builtins URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/x86/x86_builtins?rev=132393&r1=132392&r2=132393&view=diff ============================================================================== --- dragonegg/trunk/src/x86/x86_builtins (original) +++ dragonegg/trunk/src/x86/x86_builtins Wed Jun 1 07:10:01 2011 @@ -529,8 +529,8 @@ DEFINE_BUILTIN(sqrtpd256), DEFINE_BUILTIN(sqrtps), DEFINE_BUILTIN(sqrtps256), -//DEFINE_BUILTIN(sqrtps_nr), // With Newton-Raphson step -//DEFINE_BUILTIN(sqrtps_nr256), // With Newton-Raphson step +DEFINE_BUILTIN(sqrtps_nr), +DEFINE_BUILTIN(sqrtps_nr256), DEFINE_BUILTIN(sqrtsd), DEFINE_BUILTIN(sqrtss), DEFINE_BUILTIN(stmxcsr), From nadav.rotem at intel.com Wed Jun 1 07:51:47 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Wed, 01 Jun 2011 12:51:47 -0000 Subject: [llvm-commits] [llvm] r132394 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/TargetLowering.cpp test/CodeGen/Generic/promote-integers.ll Message-ID: <20110601125147.2AC1A2A6C12C@llvm.org> Author: nadav Date: Wed Jun 1 07:51:46 2011 New Revision: 132394 URL: http://llvm.org/viewvc/llvm-project?rev=132394&view=rev Log: This patch is another step in the direction of adding vector select. In this patch we add a flag to enable a new type legalization decision - to promote integer elements in vectors. Currently, the rest of the codegen does not support this kind of legalization. This flag will be removed when the transition is complete. Added: llvm/trunk/test/CodeGen/Generic/promote-integers.ll Modified: llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=132394&r1=132393&r2=132394&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Jun 1 07:51:46 2011 @@ -1597,6 +1597,13 @@ const TargetData *TD; const TargetLoweringObjectFile &TLOF; + /// We are in the process of implementing a new TypeLegalization action + /// which is the promotion of vector elements. This feature is under + /// development. Until this feature is complete, it is only enabled using a + /// flag. We pass this flag using a member because of circular dep issues. + /// This member will be removed with the flag once we complete the transition. + bool mayPromoteElements; + /// PointerTy - The type to use for pointers, usually i32 or i64. /// MVT PointerTy; @@ -1756,10 +1763,10 @@ EVT NVT = TransformToType[VT.getSimpleVT().SimpleTy]; LegalizeTypeAction LA = ValueTypeActions.getTypeAction(VT.getSimpleVT()); - assert((NVT.isSimple() && LA != TypeLegal )? - ValueTypeActions.getTypeAction( - NVT.getSimpleVT()) != TypePromoteInteger - : 1 && "Promote may not follow Expand or Promote"); + assert( + (!(NVT.isSimple() && LA != TypeLegal) || + ValueTypeActions.getTypeAction(NVT.getSimpleVT()) != TypePromoteInteger) + && "Promote may not follow Expand or Promote"); return LegalizeKind(LA, NVT); } @@ -1791,6 +1798,51 @@ if (NumElts == 1) return LegalizeKind(TypeScalarizeVector, EltVT); + // If we allow the promotion of vector elements using a flag, + // then try to widen vector elements until a legal type is found. + if (mayPromoteElements && EltVT.isInteger()) { + // Vectors with a number of elements that is not a power of two are always + // widened, for example <3 x float> -> <4 x float>. + if (!VT.isPow2VectorType()) { + NumElts = (unsigned)NextPowerOf2(NumElts); + EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts); + return LegalizeKind(TypeWidenVector, NVT); + } + + // Examine the element type. + LegalizeKind LK = getTypeConversion(Context, EltVT); + + // If type is to be expanded, split the vector. + // <4 x i140> -> <2 x i140> + if (LK.first == TypeExpandInteger) + return LegalizeKind(TypeSplitVector, + EVT::getVectorVT(Context, EltVT, NumElts / 2)); + + // Promote the integer element types until a legal vector type is found + // or until the element integer type is too big. If a legal type was not + // found, fallback to the usual mechanism of widening/splitting the + // vector. + while (1) { + // Increase the bitwidth of the element to the next pow-of-two + // (which is greater than 8 bits). + EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits() + ).getRoundIntegerType(Context); + + // Stop trying when getting a non-simple element type. + // Note that vector elements may be greater than legal vector element + // types. Example: X86 XMM registers hold 64bit element on 32bit systems. + if (!EltVT.isSimple()) break; + + // Build a new vector type and check if it is legal. + MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); + + // Found a legal promoted vector type. + if (ValueTypeActions.getTypeAction(NVT) == TypeLegal) + return LegalizeKind(TypePromoteInteger, + EVT::getVectorVT(Context, EltVT, NumElts)); + } + } + // Try to widen the vector until a legal type is found. // If there is no wider legal type, split the vector. while (1) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132394&r1=132393&r2=132394&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun 1 07:51:46 2011 @@ -26,11 +26,19 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/SelectionDAG.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include using namespace llvm; +/// We are in the process of implementing a new TypeLegalization action +/// - the promotion of vector elements. This feature is disabled by default +/// and only enabled using this flag. +static cl::opt +AllowPromoteIntElem("promote-elements", cl::Hidden, + cl::desc("Allow promotion of integer vector element types")); + namespace llvm { TLSModel::Model getTLSModel(const GlobalValue *GV, Reloc::Model reloc) { bool isLocal = GV->hasLocalLinkage(); @@ -528,7 +536,8 @@ /// NOTE: The constructor takes ownership of TLOF. TargetLowering::TargetLowering(const TargetMachine &tm, const TargetLoweringObjectFile *tlof) - : TM(tm), TD(TM.getTargetData()), TLOF(*tlof) { + : TM(tm), TD(TM.getTargetData()), TLOF(*tlof), + mayPromoteElements(AllowPromoteIntElem) { // All operations default to being supported. memset(OpActions, 0, sizeof(OpActions)); memset(LoadExtActions, 0, sizeof(LoadExtActions)); @@ -814,6 +823,24 @@ bool IsLegalWiderType = false; for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { EVT SVT = (MVT::SimpleValueType)nVT; + + // If we allow the promotion of vector elements using a flag, + // then return TypePromoteInteger on vector elements. + if (mayPromoteElements) { + // Promote vectors of integers to vectors with the same number + // of elements, with a wider element type. + if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() + && SVT.getVectorNumElements() == NElts && + isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { + TransformToType[i] = SVT; + RegisterTypeForVT[i] = SVT; + NumRegistersForVT[i] = 1; + ValueTypeActions.setTypeAction(VT, TypePromoteInteger); + IsLegalWiderType = true; + break; + } + } + if (SVT.getVectorElementType() == EltVT && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { Added: llvm/trunk/test/CodeGen/Generic/promote-integers.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/promote-integers.ll?rev=132394&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/promote-integers.ll (added) +++ llvm/trunk/test/CodeGen/Generic/promote-integers.ll Wed Jun 1 07:51:46 2011 @@ -0,0 +1,15 @@ +; Test that vectors are scalarized/lowered correctly. +; RUN: llc -march=x86 -promote-elements < %s | FileCheck %s + +; This test is the poster-child for integer-element-promotion. +; Until this feature is complete, we mark this test as expected to fail. +; XFAIL: * +; CHECK: vector_code +; CHECK: ret +define <4 x float> @vector_code(<4 x i64> %A, <4 x i64> %B, <4 x float> %R0, <4 x float> %R1 ) { + %C = icmp eq <4 x i64> %A, %B + %K = xor <4 x i1> , %C + %D = select <4 x i1> %K, <4 x float> %R1, <4 x float> %R0 + ret <4 x float> %D +} + From joerg at bec.de Wed Jun 1 08:10:15 2011 From: joerg at bec.de (Joerg Sonnenberger) Date: Wed, 01 Jun 2011 13:10:15 -0000 Subject: [llvm-commits] [llvm] r132395 - in /llvm/trunk: include/llvm/Support/SourceMgr.h lib/MC/MCParser/AsmParser.cpp lib/Support/SourceMgr.cpp utils/TableGen/TGLexer.cpp utils/TableGen/TGLexer.h utils/TableGen/TGParser.h utils/TableGen/TableGen.cpp Message-ID: <20110601131015.EEDBD2A6C12C@llvm.org> Author: joerg Date: Wed Jun 1 08:10:15 2011 New Revision: 132395 URL: http://llvm.org/viewvc/llvm-project?rev=132395&view=rev Log: Add new -d option to tblgen. It writes a make(1)-style dependency file. Modified: llvm/trunk/include/llvm/Support/SourceMgr.h llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/lib/Support/SourceMgr.cpp llvm/trunk/utils/TableGen/TGLexer.cpp llvm/trunk/utils/TableGen/TGLexer.h llvm/trunk/utils/TableGen/TGParser.h llvm/trunk/utils/TableGen/TableGen.cpp Modified: llvm/trunk/include/llvm/Support/SourceMgr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/SourceMgr.h?rev=132395&r1=132394&r2=132395&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/SourceMgr.h (original) +++ llvm/trunk/include/llvm/Support/SourceMgr.h Wed Jun 1 08:10:15 2011 @@ -106,7 +106,9 @@ /// AddIncludeFile - Search for a file with the specified name in the current /// directory or in one of the IncludeDirs. If no file is found, this returns /// ~0, otherwise it returns the buffer ID of the stacked file. - unsigned AddIncludeFile(const std::string &Filename, SMLoc IncludeLoc); + /// The full path to the included file can be found in IncludedFile. + unsigned AddIncludeFile(const std::string &Filename, SMLoc IncludeLoc, + std::string &IncludedFile); /// FindBufferContainingLoc - Return the ID of the buffer containing the /// specified location, returning -1 if not found. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=132395&r1=132394&r2=132395&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Wed Jun 1 08:10:15 2011 @@ -391,7 +391,8 @@ } bool AsmParser::EnterIncludeFile(const std::string &Filename) { - int NewBuf = SrcMgr.AddIncludeFile(Filename, Lexer.getLoc()); + std::string IncludedFile; + int NewBuf = SrcMgr.AddIncludeFile(Filename, Lexer.getLoc(), IncludedFile); if (NewBuf == -1) return true; Modified: llvm/trunk/lib/Support/SourceMgr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/SourceMgr.cpp?rev=132395&r1=132394&r2=132395&view=diff ============================================================================== --- llvm/trunk/lib/Support/SourceMgr.cpp (original) +++ llvm/trunk/lib/Support/SourceMgr.cpp Wed Jun 1 08:10:15 2011 @@ -49,14 +49,16 @@ /// directory or in one of the IncludeDirs. If no file is found, this returns /// ~0, otherwise it returns the buffer ID of the stacked file. unsigned SourceMgr::AddIncludeFile(const std::string &Filename, - SMLoc IncludeLoc) { + SMLoc IncludeLoc, + std::string &IncludedFile) { OwningPtr NewBuf; - MemoryBuffer::getFile(Filename.c_str(), NewBuf); + IncludedFile = Filename; + MemoryBuffer::getFile(IncludedFile.c_str(), NewBuf); // If the file didn't exist directly, see if it's in an include path. for (unsigned i = 0, e = IncludeDirectories.size(); i != e && !NewBuf; ++i) { - std::string IncFile = IncludeDirectories[i] + "/" + Filename; - MemoryBuffer::getFile(IncFile.c_str(), NewBuf); + IncludedFile = IncludeDirectories[i] + "/" + Filename; + MemoryBuffer::getFile(IncludedFile.c_str(), NewBuf); } if (NewBuf == 0) return ~0U; Modified: llvm/trunk/utils/TableGen/TGLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGLexer.cpp?rev=132395&r1=132394&r2=132395&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TGLexer.cpp (original) +++ llvm/trunk/utils/TableGen/TGLexer.cpp Wed Jun 1 08:10:15 2011 @@ -267,14 +267,17 @@ // Get the string. std::string Filename = CurStrVal; + std::string IncludedFile; - CurBuffer = SrcMgr.AddIncludeFile(Filename, SMLoc::getFromPointer(CurPtr)); + CurBuffer = SrcMgr.AddIncludeFile(Filename, SMLoc::getFromPointer(CurPtr), + IncludedFile); if (CurBuffer == -1) { PrintError(getLoc(), "Could not find include file '" + Filename + "'"); return true; } + Dependencies.push_back(IncludedFile); // Save the line number and lex buffer of the includer. CurBuf = SrcMgr.getMemoryBuffer(CurBuffer); CurPtr = CurBuf->getBufferStart(); Modified: llvm/trunk/utils/TableGen/TGLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGLexer.h?rev=132395&r1=132394&r2=132395&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TGLexer.h (original) +++ llvm/trunk/utils/TableGen/TGLexer.h Wed Jun 1 08:10:15 2011 @@ -16,6 +16,7 @@ #include "llvm/Support/DataTypes.h" #include +#include #include namespace llvm { @@ -71,6 +72,8 @@ /// CurBuffer - This is the current buffer index we're lexing from as managed /// by the SourceMgr object. int CurBuffer; + /// Dependencies - This is the list of all included files. + std::vector Dependencies; public: TGLexer(SourceMgr &SrcMgr); @@ -79,6 +82,10 @@ tgtok::TokKind Lex() { return CurCode = LexToken(); } + + const std::vector &getDependencies() const { + return Dependencies; + } tgtok::TokKind getCode() const { return CurCode; } Modified: llvm/trunk/utils/TableGen/TGParser.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGParser.h?rev=132395&r1=132394&r2=132395&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TGParser.h (original) +++ llvm/trunk/utils/TableGen/TGParser.h Wed Jun 1 08:10:15 2011 @@ -66,6 +66,9 @@ bool TokError(const Twine &Msg) const { return Error(Lex.getLoc(), Msg); } + const std::vector &getDependencies() const { + return Lex.getDependencies(); + } private: // Semantic analysis methods. bool AddValue(Record *TheRec, SMLoc Loc, const RecordVal &RV); bool SetValue(Record *TheRec, SMLoc Loc, const std::string &ValName, Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=132395&r1=132394&r2=132395&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Wed Jun 1 08:10:15 2011 @@ -173,6 +173,10 @@ cl::init("-")); cl::opt + DependFilename("d", cl::desc("Dependency filename"), cl::value_desc("filename"), + cl::init("")); + + cl::opt InputFilename(cl::Positional, cl::desc(""), cl::init("-")); cl::list @@ -192,34 +196,6 @@ SrcMgr.PrintMessage(ErrorLoc, Msg, "error"); } - - -/// ParseFile - this function begins the parsing of the specified tablegen -/// file. -static bool ParseFile(const std::string &Filename, - const std::vector &IncludeDirs, - SourceMgr &SrcMgr, - RecordKeeper &Records) { - OwningPtr File; - if (error_code ec = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), File)) { - errs() << "Could not open input file '" << Filename << "': " - << ec.message() <<"\n"; - return true; - } - MemoryBuffer *F = File.take(); - - // Tell SrcMgr about this buffer, which is what TGParser will pick up. - SrcMgr.AddNewSourceBuffer(F, SMLoc()); - - // Record the location of the include directory so that the lexer can find - // it later. - SrcMgr.setIncludeDirs(IncludeDirs); - - TGParser Parser(SrcMgr, Records); - - return Parser.ParseFile(); -} - int main(int argc, char **argv) { RecordKeeper Records; @@ -230,7 +206,24 @@ try { // Parse the input file. - if (ParseFile(InputFilename, IncludeDirs, SrcMgr, Records)) + OwningPtr File; + if (error_code ec = MemoryBuffer::getFileOrSTDIN(InputFilename.c_str(), File)) { + errs() << "Could not open input file '" << InputFilename << "': " + << ec.message() <<"\n"; + return 1; + } + MemoryBuffer *F = File.take(); + + // Tell SrcMgr about this buffer, which is what TGParser will pick up. + SrcMgr.AddNewSourceBuffer(F, SMLoc()); + + // Record the location of the include directory so that the lexer can find + // it later. + SrcMgr.setIncludeDirs(IncludeDirs); + + TGParser Parser(SrcMgr, Records); + + if (Parser.ParseFile()) return 1; std::string Error; @@ -240,6 +233,27 @@ << ":" << Error << "\n"; return 1; } + if (!DependFilename.empty()) { + if (OutputFilename == "-") { + errs() << argv[0] << ": the option -d must be used together with -o\n"; + return 1; + } + tool_output_file DepOut(DependFilename.c_str(), Error); + if (!Error.empty()) { + errs() << argv[0] << ": error opening " << DependFilename + << ":" << Error << "\n"; + return 1; + } + DepOut.os() << DependFilename << ":"; + const std::vector &Dependencies = Parser.getDependencies(); + for (std::vector::const_iterator I = Dependencies.begin(), + E = Dependencies.end(); + I != E; ++I) { + DepOut.os() << " " << (*I); + } + DepOut.os() << "\n"; + DepOut.keep(); + } switch (Action) { case PrintRecords: From stuart at apple.com Wed Jun 1 09:04:17 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 14:04:17 -0000 Subject: [llvm-commits] [llvm] r132396 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <20110601140417.DA76B2A6C12C@llvm.org> Author: stuart Date: Wed Jun 1 09:04:17 2011 New Revision: 132396 URL: http://llvm.org/viewvc/llvm-project?rev=132396&view=rev Log: Turn on FGETSIGN for x86. Followup to 132388. rdar://problem/5660695 Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132396&r1=132395&r2=132396&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun 1 09:04:17 2011 @@ -1754,27 +1754,23 @@ break; } case ISD::BITCAST: -#if 0 // If this is an FP->Int bitcast and if the sign bit is the only thing that // is demanded, turn this into a FGETSIGN. if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && Op.getOperand(0).getValueType().isFloatingPoint() && !Op.getOperand(0).getValueType().isVector()) { - // Only do this xform if FGETSIGN is valid or if before legalize. - if (TLO.isBeforeLegalize() || - isOperationLegal(ISD::FGETSIGN, Op.getValueType())) { + if (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) { // Make a FGETSIGN + SHL to move the sign bit into the appropriate // place. We expect the SHL to be eliminated by other optimizations. SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(), Op.getOperand(0)); unsigned ShVal = Op.getValueType().getSizeInBits()-1; - SDValue ShAmt = TLO.DAG.getConstant(ShVal, getShiftAmountTy()); + SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, Op.getValueType(), Sign, ShAmt)); } } -#endif break; case ISD::ADD: case ISD::MUL: From stoklund at 2pi.dk Wed Jun 1 10:32:10 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 01 Jun 2011 15:32:10 -0000 Subject: [llvm-commits] [llvm] r132398 - in /llvm/trunk: include/llvm/Target/TargetRegisterInfo.h lib/Target/X86/X86InstrInfo.cpp Message-ID: <20110601153210.ACA452A6C12C@llvm.org> Author: stoklund Date: Wed Jun 1 10:32:10 2011 New Revision: 132398 URL: http://llvm.org/viewvc/llvm-project?rev=132398&view=rev Log: Fix PR10059 and future variations by handling all register subclasses. Add TargetRegisterInfo::hasSubClassEq and use it to check for compatible register classes instead of trying to list all register classes in X86's getLoadStoreRegOpcode. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=132398&r1=132397&r2=132398&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Wed Jun 1 10:32:10 2011 @@ -182,6 +182,12 @@ return false; } + /// hasSubClassEq - Returns true if RC is a subclass of or equal to this + /// class. + bool hasSubClassEq(const TargetRegisterClass *RC) const { + return RC == this || hasSubClass(RC); + } + /// subclasses_begin / subclasses_end - Loop over all of the classes /// that are proper subsets of this register class. sc_iterator subclasses_begin() const { @@ -203,6 +209,12 @@ return false; } + /// hasSuperClassEq - Returns true if RC is a superclass of or equal to this + /// class. + bool hasSuperClassEq(const TargetRegisterClass *RC) const { + return RC == this || hasSuperClass(RC); + } + /// superclasses_begin / superclasses_end - Loop over all of the classes /// that are proper supersets of this register class. sc_iterator superclasses_begin() const { Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=132398&r1=132397&r2=132398&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Jun 1 10:32:10 2011 @@ -2015,62 +2015,48 @@ bool isStackAligned, const TargetMachine &TM, bool load) { - switch (RC->getID()) { + switch (RC->getSize()) { default: - llvm_unreachable("Unknown regclass"); - case X86::GR64RegClassID: - case X86::GR64_ABCDRegClassID: - case X86::GR64_NOREXRegClassID: - case X86::GR64_NOREX_NOSPRegClassID: - case X86::GR64_NOSPRegClassID: - case X86::GR64_TCRegClassID: - case X86::GR64_TCW64RegClassID: - return load ? X86::MOV64rm : X86::MOV64mr; - case X86::GR32RegClassID: - case X86::GR32_ABCDRegClassID: - case X86::GR32_ADRegClassID: - case X86::GR32_NOREXRegClassID: - case X86::GR32_NOSPRegClassID: - case X86::GR32_TCRegClassID: - return load ? X86::MOV32rm : X86::MOV32mr; - case X86::GR16RegClassID: - case X86::GR16_ABCDRegClassID: - case X86::GR16_NOREXRegClassID: - return load ? X86::MOV16rm : X86::MOV16mr; - case X86::GR8RegClassID: - // Copying to or from a physical H register on x86-64 requires a NOREX - // move. Otherwise use a normal move. - if (isHReg(Reg) && - TM.getSubtarget().is64Bit()) - return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; - else - return load ? X86::MOV8rm : X86::MOV8mr; - case X86::GR8_ABCD_LRegClassID: - case X86::GR8_NOREXRegClassID: - return load ? X86::MOV8rm :X86::MOV8mr; - case X86::GR8_ABCD_HRegClassID: + llvm_unreachable("Unknown spill size"); + case 1: + assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); if (TM.getSubtarget().is64Bit()) - return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; - else - return load ? X86::MOV8rm : X86::MOV8mr; - case X86::RFP80RegClassID: + // Copying to or from a physical H register on x86-64 requires a NOREX + // move. Otherwise use a normal move. + if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) + return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX; + return load ? X86::MOV8rm : X86::MOV8mr; + case 2: + assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); + return load ? X86::MOV16rm : X86::MOV16mr; + case 4: + if (X86::GR32RegClass.hasSubClassEq(RC)) + return load ? X86::MOV32rm : X86::MOV32mr; + if (X86::FR32RegClass.hasSubClassEq(RC)) + return load ? X86::MOVSSrm : X86::MOVSSmr; + if (X86::RFP32RegClass.hasSubClassEq(RC)) + return load ? X86::LD_Fp32m : X86::ST_Fp32m; + llvm_unreachable("Unknown 4-byte regclass"); + case 8: + if (X86::GR64RegClass.hasSubClassEq(RC)) + return load ? X86::MOV64rm : X86::MOV64mr; + if (X86::FR64RegClass.hasSubClassEq(RC)) + return load ? X86::MOVSDrm : X86::MOVSDmr; + if (X86::VR64RegClass.hasSubClassEq(RC)) + return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; + if (X86::RFP64RegClass.hasSubClassEq(RC)) + return load ? X86::LD_Fp64m : X86::ST_Fp64m; + llvm_unreachable("Unknown 8-byte regclass"); + case 10: + assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass"); return load ? X86::LD_Fp80m : X86::ST_FpP80m; - case X86::RFP64RegClassID: - return load ? X86::LD_Fp64m : X86::ST_Fp64m; - case X86::RFP32RegClassID: - return load ? X86::LD_Fp32m : X86::ST_Fp32m; - case X86::FR32RegClassID: - return load ? X86::MOVSSrm : X86::MOVSSmr; - case X86::FR64RegClassID: - return load ? X86::MOVSDrm : X86::MOVSDmr; - case X86::VR128RegClassID: + case 16: + assert(X86::VR128RegClass.hasSubClassEq(RC) && "Unknown 16-byte regclass"); // If stack is realigned we can use aligned stores. if (isStackAligned) return load ? X86::MOVAPSrm : X86::MOVAPSmr; else return load ? X86::MOVUPSrm : X86::MOVUPSmr; - case X86::VR64RegClassID: - return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr; } } From stuart at apple.com Wed Jun 1 10:50:29 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 15:50:29 -0000 Subject: [llvm-commits] [llvm] r132399 - /llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll Message-ID: <20110601155029.76A5C2A6C12C@llvm.org> Author: stuart Date: Wed Jun 1 10:50:29 2011 New Revision: 132399 URL: http://llvm.org/viewvc/llvm-project?rev=132399&view=rev Log: Test case for 132396. rdar://problem/5660695 Added: llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll Added: llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll?rev=132399&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll Wed Jun 1 10:50:29 2011 @@ -0,0 +1,99 @@ +; RUN: llc -mcpu=core2 < %s | FileCheck %s +; ModuleID = '' +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.6.6" + +%0 = type { double } +%union.anon = type { float } + +define i32 @double_signbit(double %d1) nounwind uwtable readnone ssp { +entry: + %__x.addr.i = alloca double, align 8 + %__u.i = alloca %0, align 8 + %0 = bitcast double* %__x.addr.i to i8* + call void @llvm.lifetime.start(i64 -1, i8* %0) + %1 = bitcast %0* %__u.i to i8* + call void @llvm.lifetime.start(i64 -1, i8* %1) + store double %d1, double* %__x.addr.i, align 8 + %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0 + store double %d1, double* %__f.i, align 8 + %tmp = bitcast double %d1 to i64 +; CHECK-NOT: shr +; CHECK: movmskpd +; CHECK-NEXT: and + %tmp1 = lshr i64 %tmp, 63 + %shr.i = trunc i64 %tmp1 to i32 + call void @llvm.lifetime.end(i64 -1, i8* %0) + call void @llvm.lifetime.end(i64 -1, i8* %1) + ret i32 %shr.i +} + +define i32 @double_add_signbit(double %d1, double %d2) nounwind uwtable readnone ssp { +entry: + %__x.addr.i = alloca double, align 8 + %__u.i = alloca %0, align 8 + %add = fadd double %d1, %d2 + %0 = bitcast double* %__x.addr.i to i8* + call void @llvm.lifetime.start(i64 -1, i8* %0) + %1 = bitcast %0* %__u.i to i8* + call void @llvm.lifetime.start(i64 -1, i8* %1) + store double %add, double* %__x.addr.i, align 8 + %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0 + store double %add, double* %__f.i, align 8 + %tmp = bitcast double %add to i64 +; CHECK-NOT: shr +; CHECK: movmskpd +; CHECK-NEXT: and + %tmp1 = lshr i64 %tmp, 63 + %shr.i = trunc i64 %tmp1 to i32 + call void @llvm.lifetime.end(i64 -1, i8* %0) + call void @llvm.lifetime.end(i64 -1, i8* %1) + ret i32 %shr.i +} + +define i32 @float_signbit(float %f1) nounwind uwtable readnone ssp { +entry: + %__x.addr.i = alloca float, align 4 + %__u.i = alloca %union.anon, align 4 + %0 = bitcast float* %__x.addr.i to i8* + call void @llvm.lifetime.start(i64 -1, i8* %0) + %1 = bitcast %union.anon* %__u.i to i8* + call void @llvm.lifetime.start(i64 -1, i8* %1) + store float %f1, float* %__x.addr.i, align 4 + %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0 + store float %f1, float* %__f.i, align 4 + %2 = bitcast float %f1 to i32 +; CHECK-NOT: shr +; CHECK: movmskps +; CHECK-NEXT: and + %shr.i = lshr i32 %2, 31 + call void @llvm.lifetime.end(i64 -1, i8* %0) + call void @llvm.lifetime.end(i64 -1, i8* %1) + ret i32 %shr.i +} + +define i32 @float_add_signbit(float %f1, float %f2) nounwind uwtable readnone ssp { +entry: + %__x.addr.i = alloca float, align 4 + %__u.i = alloca %union.anon, align 4 + %add = fadd float %f1, %f2 + %0 = bitcast float* %__x.addr.i to i8* + call void @llvm.lifetime.start(i64 -1, i8* %0) + %1 = bitcast %union.anon* %__u.i to i8* + call void @llvm.lifetime.start(i64 -1, i8* %1) + store float %add, float* %__x.addr.i, align 4 + %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0 + store float %add, float* %__f.i, align 4 + %2 = bitcast float %add to i32 +; CHECK-NOT: shr +; CHECK: movmskps +; CHECK-NEXT: and + %shr.i = lshr i32 %2, 31 + call void @llvm.lifetime.end(i64 -1, i8* %0) + call void @llvm.lifetime.end(i64 -1, i8* %1) + ret i32 %shr.i +} + +declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind + +declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind From stuart at apple.com Wed Jun 1 11:13:09 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 16:13:09 -0000 Subject: [llvm-commits] [llvm] r132401 - /llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll Message-ID: <20110601161309.57CB02A6C12C@llvm.org> Author: stuart Date: Wed Jun 1 11:13:09 2011 New Revision: 132401 URL: http://llvm.org/viewvc/llvm-project?rev=132401&view=rev Log: A forthcoming SSE patch will break this test; since the test is also valid for x87, re-target to x87. rdar://problem/5993888 Modified: llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll Modified: llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll?rev=132401&r1=132400&r2=132401&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll (original) +++ llvm/trunk/test/CodeGen/X86/2006-05-22-FPSetEQ.ll Wed Jun 1 11:13:09 2011 @@ -1,5 +1,5 @@ -; RUN: llc < %s -march=x86 | grep setnp -; RUN: llc < %s -march=x86 -enable-unsafe-fp-math -enable-no-nans-fp-math | \ +; RUN: llc < %s -march=x86 -mattr=-sse | grep setnp +; RUN: llc < %s -march=x86 -mattr=-sse -enable-unsafe-fp-math -enable-no-nans-fp-math | \ ; RUN: not grep setnp define i32 @test(float %f) { From stuart at apple.com Wed Jun 1 11:42:47 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 16:42:47 -0000 Subject: [llvm-commits] [llvm] r132402 - in /llvm/trunk: lib/Transforms/InstCombine/InstCombineMulDivRem.cpp test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Message-ID: <20110601164247.4F6952A6C12C@llvm.org> Author: stuart Date: Wed Jun 1 11:42:47 2011 New Revision: 132402 URL: http://llvm.org/viewvc/llvm-project?rev=132402&view=rev Log: Reapply 132348 with fixes. rdar://problem/6501862 Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp?rev=132402&r1=132401&r2=132402&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp (original) +++ llvm/trunk/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp Wed Jun 1 11:42:47 2011 @@ -136,19 +136,25 @@ } } - // (1 - X) * (-2) -> (x - 1) * 2, for all positive nonzero powers of 2 - // The "* 2" thus becomes a potential shifting opportunity. + // (Y - X) * (-(2**n)) -> (X - Y) * (2**n), for positive nonzero n + // (Y + const) * (-(2**n)) -> (-constY) * (2**n), for positive nonzero n + // The "* (2**n)" thus becomes a potential shifting opportunity. { const APInt & Val = CI->getValue(); const APInt &PosVal = Val.abs(); if (Val.isNegative() && PosVal.isPowerOf2()) { - Value *X = 0; - if (match(Op0, m_Sub(m_One(), m_Value(X)))) { - // ConstantInt::get(Op0->getType(), 2); - Value *Sub = Builder->CreateSub(X, ConstantInt::get(X->getType(), 1), - "dec1"); - return BinaryOperator::CreateMul(Sub, ConstantInt::get(X->getType(), - PosVal)); + Value *X = 0, *Y = 0; + if (Op0->hasOneUse()) { + ConstantInt *C1; + Value *Sub = 0; + if (match(Op0, m_Sub(m_Value(Y), m_Value(X)))) + Sub = Builder->CreateSub(X, Y, "suba"); + else if (match(Op0, m_Add(m_Value(Y), m_ConstantInt(C1)))) + Sub = Builder->CreateSub(Builder->CreateNeg(C1), Y, "subc"); + if (Sub) + return + BinaryOperator::CreateMul(Sub, + ConstantInt::get(Y->getType(), PosVal)); } } } Modified: llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll?rev=132402&r1=132401&r2=132402&view=diff ============================================================================== --- llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll (original) +++ llvm/trunk/test/Transforms/InstCombine/2011-05-28-swapmulsub.ll Wed Jun 1 11:42:47 2011 @@ -2,18 +2,14 @@ ; RUN: opt -S -instcombine < %s | FileCheck %s target triple = "x86_64-apple-macosx10.6.6" -define zeroext i16 @foo(i32 %on_off, i16* %puls) nounwind uwtable ssp { +define zeroext i16 @foo1(i32 %on_off) nounwind uwtable ssp { entry: %on_off.addr = alloca i32, align 4 - %puls.addr = alloca i16*, align 8 %a = alloca i32, align 4 store i32 %on_off, i32* %on_off.addr, align 4 - store i16* %puls, i16** %puls.addr, align 8 %tmp = load i32* %on_off.addr, align 4 -; CHECK-NOT: sub -; CHECK-NOT: mul -; (1 - %tmp) * (-2) -> (%tmp - 1) * 2 %sub = sub i32 1, %tmp +; CHECK-NOT: mul i32 %mul = mul i32 %sub, -2 ; CHECK: shl ; CHECK-NEXT: add @@ -22,3 +18,40 @@ %conv = trunc i32 %tmp1 to i16 ret i16 %conv } + +define zeroext i16 @foo2(i32 %on_off, i32 %q) nounwind uwtable ssp { +entry: + %on_off.addr = alloca i32, align 4 + %q.addr = alloca i32, align 4 + %a = alloca i32, align 4 + store i32 %on_off, i32* %on_off.addr, align 4 + store i32 %q, i32* %q.addr, align 4 + %tmp = load i32* %q.addr, align 4 + %tmp1 = load i32* %on_off.addr, align 4 + %sub = sub i32 %tmp, %tmp1 +; CHECK-NOT: mul i32 + %mul = mul i32 %sub, -4 +; CHECK: sub i32 +; CHECK-NEXT: shl + store i32 %mul, i32* %a, align 4 + %tmp2 = load i32* %a, align 4 + %conv = trunc i32 %tmp2 to i16 + ret i16 %conv +} + +define zeroext i16 @foo3(i32 %on_off) nounwind uwtable ssp { +entry: + %on_off.addr = alloca i32, align 4 + %a = alloca i32, align 4 + store i32 %on_off, i32* %on_off.addr, align 4 + %tmp = load i32* %on_off.addr, align 4 + %sub = sub i32 7, %tmp +; CHECK-NOT: mul i32 + %mul = mul i32 %sub, -4 +; CHECK: shl +; CHECK-NEXT: add + store i32 %mul, i32* %a, align 4 + %tmp1 = load i32* %a, align 4 + %conv = trunc i32 %tmp1 to i16 + ret i16 %conv +} From stuart at apple.com Wed Jun 1 12:17:46 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 17:17:46 -0000 Subject: [llvm-commits] [llvm] r132404 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/isint.ll test/CodeGen/X86/pr9127.ll test/CodeGen/X86/setoeq.ll Message-ID: <20110601171746.5992F2A6C12C@llvm.org> Author: stuart Date: Wed Jun 1 12:17:45 2011 New Revision: 132404 URL: http://llvm.org/viewvc/llvm-project?rev=132404&view=rev Log: Add support for x86 CMPEQSS and friends. These instructions do a floating-point comparison, generate a mask of 0s or 1s, and generally DTRT with NaNs. Only profitable when the user wants a materialized 0 or 1 at runtime. rdar://problem/5993888 Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/isint.ll llvm/trunk/test/CodeGen/X86/pr9127.ll llvm/trunk/test/CodeGen/X86/setoeq.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=132404&r1=132403&r2=132404&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jun 1 12:17:45 2011 @@ -9391,6 +9391,8 @@ case X86ISD::UCOMI: return "X86ISD::UCOMI"; case X86ISD::SETCC: return "X86ISD::SETCC"; case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; + case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; + case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; case X86ISD::CMOV: return "X86ISD::CMOV"; case X86ISD::BRCOND: return "X86ISD::BRCOND"; case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; @@ -11668,12 +11670,88 @@ } +// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) +// where both setccs reference the same FP CMP, and rewrite for CMPEQSS +// and friends. Likewise for OR -> CMPNEQSS. +static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const X86Subtarget *Subtarget) { + unsigned opcode; + + // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but + // we're requiring SSE2 for both. + if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + SDValue CMP = N0->getOperand(1); + SDValue CMP0 = CMP->getOperand(0); + SDValue CMP1 = CMP->getOperand(1); + bool isFP = CMP0.getValueType().isFloatingPoint(); + DebugLoc DL = N->getDebugLoc(); + + if (isFP) { + bool ExpectingFlags = false; + // Check for any users that want flags: + for (SDNode::use_iterator UI = N->use_begin(), + UE = N->use_end(); + !ExpectingFlags && UI != UE; ++UI) + switch (UI->getOpcode()) { + default: + case ISD::BR_CC: + case ISD::BRCOND: + case ISD::SELECT: + ExpectingFlags = true; + break; + case ISD::CopyToReg: + case ISD::SIGN_EXTEND: + case ISD::ZERO_EXTEND: + case ISD::ANY_EXTEND: + break; + } + + if (!ExpectingFlags) { + enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); + enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); + + if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { + X86::CondCode tmp = cc0; + cc0 = cc1; + cc1 = tmp; + } + + if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || + (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { + bool is64BitFP = (CMP0.getValueType() == MVT::f64); + X86ISD::NodeType NTOperator = is64BitFP ? + X86ISD::FSETCCsd : X86ISD::FSETCCss; + // FIXME: need symbolic constants for these magic numbers. + // See X86ATTInstPrinter.cpp:printSSECC(). + unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; + SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP0, CMP1, + DAG.getConstant(x86cc, MVT::i8)); + SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, + OnesOrZeroesF); + SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, + DAG.getConstant(1, MVT::i32)); + SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); + return OneBitOfTruth; + } + } + } + } + return SDValue(); +} + static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) { if (DCI.isBeforeLegalizeOps()) return SDValue(); + SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); + if (R.getNode()) + return R; + // Want to form PANDN nodes, in the hopes of then easily combining them with // OR and AND nodes to form PBLEND/PSIGN. EVT VT = N->getValueType(0); @@ -11703,6 +11781,10 @@ if (DCI.isBeforeLegalizeOps()) return SDValue(); + SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); + if (R.getNode()) + return R; + EVT VT = N->getValueType(0); if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) return SDValue(); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=132404&r1=132403&r2=132404&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Jun 1 12:17:45 2011 @@ -94,6 +94,11 @@ // one's or all zero's. SETCC_CARRY, // R = carry_bit ? ~0 : 0 + /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. + /// Operands are two FP values to compare; result is a mask of + /// 0s or 1s. Generally DTRT for C/C++ with NaNs. + FSETCCss, FSETCCsd, + /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, /// result in an integer GPR. Needs masking for scalar result. FGETSIGNx86, Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=132404&r1=132403&r2=132404&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Wed Jun 1 12:17:45 2011 @@ -41,6 +41,8 @@ def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; +def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>; +def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>; def X86pshufb : SDNode<"X86ISD::PSHUFB", SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>>; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=132404&r1=132403&r2=132404&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Jun 1 12:17:45 2011 @@ -23,6 +23,9 @@ def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; +def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; +def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; + def SDTX86Cmov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=132404&r1=132403&r2=132404&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jun 1 12:17:45 2011 @@ -1056,13 +1056,37 @@ XD, VEX_4V; } +let Constraints = "$src1 = $dst" in { +def CMPSSrr : SIi8<0xC2, MRMSrcReg, + (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc), + "cmp${cc}ss\t{$src2, $dst|$dst, $src2}", + [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS; +def CMPSSrm : SIi8<0xC2, MRMSrcMem, + (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc), + "cmp${cc}ss\t{$src2, $dst|$dst, $src2}", + [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS; +def CMPSDrr : SIi8<0xC2, MRMSrcReg, + (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc), + "cmp${cc}sd\t{$src2, $dst|$dst, $src2}", + [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD; +def CMPSDrm : SIi8<0xC2, MRMSrcMem, + (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc), + "cmp${cc}sd\t{$src2, $dst|$dst, $src2}", + [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD; +} let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in { - defm CMPSS : sse12_cmp_scalar, XS; - defm CMPSD : sse12_cmp_scalar, XD; +def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg, + (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2), + "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS; +def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem, + (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2), + "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS; +def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg, + (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2), + "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD; +def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem, + (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2), + "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD; } multiclass sse12_cmp_scalar_int %t -; RUN: not grep cmp %t -; RUN: not grep xor %t -; RUN: grep jne %t | count 1 -; RUN: grep jp %t | count 1 -; RUN: grep setnp %t | count 1 -; RUN: grep sete %t | count 1 -; RUN: grep and %t | count 1 -; RUN: grep cvt %t | count 4 +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s define i32 @isint_return(double %d) nounwind { +; CHECK-NOT: xor +; CHECK: cvt %i = fptosi double %d to i32 +; CHECK-NEXT: cvt %e = sitofp i32 %i to double +; CHECK: cmpeqsd %c = fcmp oeq double %d, %e +; CHECK-NEXT: movd +; CHECK-NEXT: andl %z = zext i1 %c to i32 ret i32 %z } @@ -19,9 +17,14 @@ declare void @foo() define void @isint_branch(double %d) nounwind { +; CHECK: cvt %i = fptosi double %d to i32 +; CHECK-NEXT: cvt %e = sitofp i32 %i to double +; CHECK: ucomisd %c = fcmp oeq double %d, %e +; CHECK-NEXT: jne +; CHECK-NEXT: jp br i1 %c, label %true, label %false true: call void @foo() Modified: llvm/trunk/test/CodeGen/X86/pr9127.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr9127.ll?rev=132404&r1=132403&r2=132404&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr9127.ll (original) +++ llvm/trunk/test/CodeGen/X86/pr9127.ll Wed Jun 1 12:17:45 2011 @@ -10,4 +10,4 @@ } ; test that the load is folded. -; CHECK: ucomisd (%{{rdi|rdx}}), %xmm0 +; CHECK: cmpeqsd (%{{rdi|rdx}}), %xmm0 Modified: llvm/trunk/test/CodeGen/X86/setoeq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setoeq.ll?rev=132404&r1=132403&r2=132404&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/setoeq.ll (original) +++ llvm/trunk/test/CodeGen/X86/setoeq.ll Wed Jun 1 12:17:45 2011 @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=x86 | grep set | count 2 -; RUN: llc < %s -march=x86 | grep and +; RUN: llc < %s -march=x86 | FileCheck %s define zeroext i8 @t(double %x) nounwind readnone { entry: @@ -7,5 +6,16 @@ %1 = sitofp i32 %0 to double ; [#uses=1] %2 = fcmp oeq double %1, %x ; [#uses=1] %retval12 = zext i1 %2 to i8 ; [#uses=1] +; CHECK: cmpeqsd + ret i8 %retval12 +} + +define zeroext i8 @u(double %x) nounwind readnone { +entry: + %0 = fptosi double %x to i32 ; [#uses=1] + %1 = sitofp i32 %0 to double ; [#uses=1] + %2 = fcmp une double %1, %x ; [#uses=1] + %retval12 = zext i1 %2 to i8 ; [#uses=1] +; CHECK: cmpneqsd ret i8 %retval12 } From benny.kra at googlemail.com Wed Jun 1 12:19:08 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 01 Jun 2011 17:19:08 -0000 Subject: [llvm-commits] [llvm] r132405 - /llvm/trunk/include/llvm/Target/TargetInstrItineraries.h Message-ID: <20110601171908.B97292A6C12C@llvm.org> Author: d0k Date: Wed Jun 1 12:19:08 2011 New Revision: 132405 URL: http://llvm.org/viewvc/llvm-project?rev=132405&view=rev Log: Initialize IssueWidth to zero. Fixes valgrind errors in the CellSPU backend. Modified: llvm/trunk/include/llvm/Target/TargetInstrItineraries.h Modified: llvm/trunk/include/llvm/Target/TargetInstrItineraries.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrItineraries.h?rev=132405&r1=132404&r2=132405&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrItineraries.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrItineraries.h Wed Jun 1 12:19:08 2011 @@ -122,7 +122,8 @@ InstrItineraryData(const InstrStage *S, const unsigned *OS, const unsigned *F, const InstrItinerary *I) - : Stages(S), OperandCycles(OS), Forwardings(F), Itineraries(I) {} + : Stages(S), OperandCycles(OS), Forwardings(F), Itineraries(I), + IssueWidth(0) {} /// isEmpty - Returns true if there are no itineraries. /// From evan.cheng at apple.com Wed Jun 1 12:47:27 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 01 Jun 2011 10:47:27 -0700 Subject: [llvm-commits] [llvm] r132399 - /llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll In-Reply-To: <20110601155029.76A5C2A6C12C@llvm.org> References: <20110601155029.76A5C2A6C12C@llvm.org> Message-ID: <4C0086A8-B73B-4FF9-B57D-ADD4EB9D6377@apple.com> Stuart, are the tests reduced? The lifetime markers are not necessary, right? Evan On Jun 1, 2011, at 8:50 AM, Stuart Hastings wrote: > Author: stuart > Date: Wed Jun 1 10:50:29 2011 > New Revision: 132399 > > URL: http://llvm.org/viewvc/llvm-project?rev=132399&view=rev > Log: > Test case for 132396. rdar://problem/5660695 > > Added: > llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll > > Added: llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll?rev=132399&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll (added) > +++ llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll Wed Jun 1 10:50:29 2011 > @@ -0,0 +1,99 @@ > +; RUN: llc -mcpu=core2 < %s | FileCheck %s > +; ModuleID = '' > +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" > +target triple = "x86_64-apple-macosx10.6.6" > + > +%0 = type { double } > +%union.anon = type { float } > + > +define i32 @double_signbit(double %d1) nounwind uwtable readnone ssp { > +entry: > + %__x.addr.i = alloca double, align 8 > + %__u.i = alloca %0, align 8 > + %0 = bitcast double* %__x.addr.i to i8* > + call void @llvm.lifetime.start(i64 -1, i8* %0) > + %1 = bitcast %0* %__u.i to i8* > + call void @llvm.lifetime.start(i64 -1, i8* %1) > + store double %d1, double* %__x.addr.i, align 8 > + %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0 > + store double %d1, double* %__f.i, align 8 > + %tmp = bitcast double %d1 to i64 > +; CHECK-NOT: shr > +; CHECK: movmskpd > +; CHECK-NEXT: and > + %tmp1 = lshr i64 %tmp, 63 > + %shr.i = trunc i64 %tmp1 to i32 > + call void @llvm.lifetime.end(i64 -1, i8* %0) > + call void @llvm.lifetime.end(i64 -1, i8* %1) > + ret i32 %shr.i > +} > + > +define i32 @double_add_signbit(double %d1, double %d2) nounwind uwtable readnone ssp { > +entry: > + %__x.addr.i = alloca double, align 8 > + %__u.i = alloca %0, align 8 > + %add = fadd double %d1, %d2 > + %0 = bitcast double* %__x.addr.i to i8* > + call void @llvm.lifetime.start(i64 -1, i8* %0) > + %1 = bitcast %0* %__u.i to i8* > + call void @llvm.lifetime.start(i64 -1, i8* %1) > + store double %add, double* %__x.addr.i, align 8 > + %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0 > + store double %add, double* %__f.i, align 8 > + %tmp = bitcast double %add to i64 > +; CHECK-NOT: shr > +; CHECK: movmskpd > +; CHECK-NEXT: and > + %tmp1 = lshr i64 %tmp, 63 > + %shr.i = trunc i64 %tmp1 to i32 > + call void @llvm.lifetime.end(i64 -1, i8* %0) > + call void @llvm.lifetime.end(i64 -1, i8* %1) > + ret i32 %shr.i > +} > + > +define i32 @float_signbit(float %f1) nounwind uwtable readnone ssp { > +entry: > + %__x.addr.i = alloca float, align 4 > + %__u.i = alloca %union.anon, align 4 > + %0 = bitcast float* %__x.addr.i to i8* > + call void @llvm.lifetime.start(i64 -1, i8* %0) > + %1 = bitcast %union.anon* %__u.i to i8* > + call void @llvm.lifetime.start(i64 -1, i8* %1) > + store float %f1, float* %__x.addr.i, align 4 > + %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0 > + store float %f1, float* %__f.i, align 4 > + %2 = bitcast float %f1 to i32 > +; CHECK-NOT: shr > +; CHECK: movmskps > +; CHECK-NEXT: and > + %shr.i = lshr i32 %2, 31 > + call void @llvm.lifetime.end(i64 -1, i8* %0) > + call void @llvm.lifetime.end(i64 -1, i8* %1) > + ret i32 %shr.i > +} > + > +define i32 @float_add_signbit(float %f1, float %f2) nounwind uwtable readnone ssp { > +entry: > + %__x.addr.i = alloca float, align 4 > + %__u.i = alloca %union.anon, align 4 > + %add = fadd float %f1, %f2 > + %0 = bitcast float* %__x.addr.i to i8* > + call void @llvm.lifetime.start(i64 -1, i8* %0) > + %1 = bitcast %union.anon* %__u.i to i8* > + call void @llvm.lifetime.start(i64 -1, i8* %1) > + store float %add, float* %__x.addr.i, align 4 > + %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0 > + store float %add, float* %__f.i, align 4 > + %2 = bitcast float %add to i32 > +; CHECK-NOT: shr > +; CHECK: movmskps > +; CHECK-NEXT: and > + %shr.i = lshr i32 %2, 31 > + call void @llvm.lifetime.end(i64 -1, i8* %0) > + call void @llvm.lifetime.end(i64 -1, i8* %1) > + ret i32 %shr.i > +} > + > +declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind > + > +declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stuart at apple.com Wed Jun 1 13:23:14 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 18:23:14 -0000 Subject: [llvm-commits] [llvm] r132408 - /llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll Message-ID: <20110601182314.B80492A6C12C@llvm.org> Author: stuart Date: Wed Jun 1 13:23:14 2011 New Revision: 132408 URL: http://llvm.org/viewvc/llvm-project?rev=132408&view=rev Log: Cleanup test case. rdar://problem/5660695 Modified: llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll Modified: llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll?rev=132408&r1=132407&r2=132408&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll (original) +++ llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll Wed Jun 1 13:23:14 2011 @@ -11,9 +11,7 @@ %__x.addr.i = alloca double, align 8 %__u.i = alloca %0, align 8 %0 = bitcast double* %__x.addr.i to i8* - call void @llvm.lifetime.start(i64 -1, i8* %0) %1 = bitcast %0* %__u.i to i8* - call void @llvm.lifetime.start(i64 -1, i8* %1) store double %d1, double* %__x.addr.i, align 8 %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0 store double %d1, double* %__f.i, align 8 @@ -23,8 +21,6 @@ ; CHECK-NEXT: and %tmp1 = lshr i64 %tmp, 63 %shr.i = trunc i64 %tmp1 to i32 - call void @llvm.lifetime.end(i64 -1, i8* %0) - call void @llvm.lifetime.end(i64 -1, i8* %1) ret i32 %shr.i } @@ -34,9 +30,7 @@ %__u.i = alloca %0, align 8 %add = fadd double %d1, %d2 %0 = bitcast double* %__x.addr.i to i8* - call void @llvm.lifetime.start(i64 -1, i8* %0) %1 = bitcast %0* %__u.i to i8* - call void @llvm.lifetime.start(i64 -1, i8* %1) store double %add, double* %__x.addr.i, align 8 %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0 store double %add, double* %__f.i, align 8 @@ -46,8 +40,6 @@ ; CHECK-NEXT: and %tmp1 = lshr i64 %tmp, 63 %shr.i = trunc i64 %tmp1 to i32 - call void @llvm.lifetime.end(i64 -1, i8* %0) - call void @llvm.lifetime.end(i64 -1, i8* %1) ret i32 %shr.i } @@ -56,9 +48,7 @@ %__x.addr.i = alloca float, align 4 %__u.i = alloca %union.anon, align 4 %0 = bitcast float* %__x.addr.i to i8* - call void @llvm.lifetime.start(i64 -1, i8* %0) %1 = bitcast %union.anon* %__u.i to i8* - call void @llvm.lifetime.start(i64 -1, i8* %1) store float %f1, float* %__x.addr.i, align 4 %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0 store float %f1, float* %__f.i, align 4 @@ -67,8 +57,6 @@ ; CHECK: movmskps ; CHECK-NEXT: and %shr.i = lshr i32 %2, 31 - call void @llvm.lifetime.end(i64 -1, i8* %0) - call void @llvm.lifetime.end(i64 -1, i8* %1) ret i32 %shr.i } @@ -78,9 +66,7 @@ %__u.i = alloca %union.anon, align 4 %add = fadd float %f1, %f2 %0 = bitcast float* %__x.addr.i to i8* - call void @llvm.lifetime.start(i64 -1, i8* %0) %1 = bitcast %union.anon* %__u.i to i8* - call void @llvm.lifetime.start(i64 -1, i8* %1) store float %add, float* %__x.addr.i, align 4 %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0 store float %add, float* %__f.i, align 4 @@ -89,11 +75,5 @@ ; CHECK: movmskps ; CHECK-NEXT: and %shr.i = lshr i32 %2, 31 - call void @llvm.lifetime.end(i64 -1, i8* %0) - call void @llvm.lifetime.end(i64 -1, i8* %1) ret i32 %shr.i } - -declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind - -declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind From echristo at apple.com Wed Jun 1 13:23:56 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 01 Jun 2011 18:23:56 -0000 Subject: [llvm-commits] [llvm] r132409 - /llvm/trunk/test/FrontendC/struct-matching-constraint.c Message-ID: <20110601182356.9A2372A6C12C@llvm.org> Author: echristo Date: Wed Jun 1 13:23:56 2011 New Revision: 132409 URL: http://llvm.org/viewvc/llvm-project?rev=132409&view=rev Log: Add a testcase, enabled only on arm, for llvm-gcc r132366. Added: llvm/trunk/test/FrontendC/struct-matching-constraint.c Added: llvm/trunk/test/FrontendC/struct-matching-constraint.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/struct-matching-constraint.c?rev=132409&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/struct-matching-constraint.c (added) +++ llvm/trunk/test/FrontendC/struct-matching-constraint.c Wed Jun 1 13:23:56 2011 @@ -0,0 +1,19 @@ +// RUN: %llvmgcc -S -march=armv7a %s + +// XFAIL: * +// XTARGET: arm + +typedef struct __simd128_uint16_t +{ + __neon_uint16x8_t val; +} uint16x8_t; + +void b(uint16x8_t sat, uint16x8_t luma) +{ + __asm__("vmov.16 %1, %0 \n\t" + "vtrn.16 %0, %1 \n\t" + :"=w"(luma), "=w"(sat) + :"0"(luma) + ); + +} From stuart at apple.com Wed Jun 1 13:30:35 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 11:30:35 -0700 Subject: [llvm-commits] [llvm] r132399 - /llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll In-Reply-To: <4C0086A8-B73B-4FF9-B57D-ADD4EB9D6377@apple.com> References: <20110601155029.76A5C2A6C12C@llvm.org> <4C0086A8-B73B-4FF9-B57D-ADD4EB9D6377@apple.com> Message-ID: <4FF70D44-E5CC-487E-AE24-38067E5B9200@apple.com> On Jun 1, 2011, at 10:47 AM, Evan Cheng wrote: > Stuart, are the tests reduced? The lifetime markers are not necessary, right? Right. My oversight. Fixed at 132408. stuart > > Evan > > On Jun 1, 2011, at 8:50 AM, Stuart Hastings wrote: > >> Author: stuart >> Date: Wed Jun 1 10:50:29 2011 >> New Revision: 132399 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132399&view=rev >> Log: >> Test case for 132396. rdar://problem/5660695 >> >> Added: >> llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll >> >> Added: llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll?rev=132399&view=auto >> ============================================================================== >> --- llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll (added) >> +++ llvm/trunk/test/CodeGen/X86/2011-05-31-movmsk.ll Wed Jun 1 10:50:29 2011 >> @@ -0,0 +1,99 @@ >> +; RUN: llc -mcpu=core2 < %s | FileCheck %s >> +; ModuleID = '' >> +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" >> +target triple = "x86_64-apple-macosx10.6.6" >> + >> +%0 = type { double } >> +%union.anon = type { float } >> + >> +define i32 @double_signbit(double %d1) nounwind uwtable readnone ssp { >> +entry: >> + %__x.addr.i = alloca double, align 8 >> + %__u.i = alloca %0, align 8 >> + %0 = bitcast double* %__x.addr.i to i8* >> + call void @llvm.lifetime.start(i64 -1, i8* %0) >> + %1 = bitcast %0* %__u.i to i8* >> + call void @llvm.lifetime.start(i64 -1, i8* %1) >> + store double %d1, double* %__x.addr.i, align 8 >> + %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0 >> + store double %d1, double* %__f.i, align 8 >> + %tmp = bitcast double %d1 to i64 >> +; CHECK-NOT: shr >> +; CHECK: movmskpd >> +; CHECK-NEXT: and >> + %tmp1 = lshr i64 %tmp, 63 >> + %shr.i = trunc i64 %tmp1 to i32 >> + call void @llvm.lifetime.end(i64 -1, i8* %0) >> + call void @llvm.lifetime.end(i64 -1, i8* %1) >> + ret i32 %shr.i >> +} >> + >> +define i32 @double_add_signbit(double %d1, double %d2) nounwind uwtable readnone ssp { >> +entry: >> + %__x.addr.i = alloca double, align 8 >> + %__u.i = alloca %0, align 8 >> + %add = fadd double %d1, %d2 >> + %0 = bitcast double* %__x.addr.i to i8* >> + call void @llvm.lifetime.start(i64 -1, i8* %0) >> + %1 = bitcast %0* %__u.i to i8* >> + call void @llvm.lifetime.start(i64 -1, i8* %1) >> + store double %add, double* %__x.addr.i, align 8 >> + %__f.i = getelementptr inbounds %0* %__u.i, i64 0, i32 0 >> + store double %add, double* %__f.i, align 8 >> + %tmp = bitcast double %add to i64 >> +; CHECK-NOT: shr >> +; CHECK: movmskpd >> +; CHECK-NEXT: and >> + %tmp1 = lshr i64 %tmp, 63 >> + %shr.i = trunc i64 %tmp1 to i32 >> + call void @llvm.lifetime.end(i64 -1, i8* %0) >> + call void @llvm.lifetime.end(i64 -1, i8* %1) >> + ret i32 %shr.i >> +} >> + >> +define i32 @float_signbit(float %f1) nounwind uwtable readnone ssp { >> +entry: >> + %__x.addr.i = alloca float, align 4 >> + %__u.i = alloca %union.anon, align 4 >> + %0 = bitcast float* %__x.addr.i to i8* >> + call void @llvm.lifetime.start(i64 -1, i8* %0) >> + %1 = bitcast %union.anon* %__u.i to i8* >> + call void @llvm.lifetime.start(i64 -1, i8* %1) >> + store float %f1, float* %__x.addr.i, align 4 >> + %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0 >> + store float %f1, float* %__f.i, align 4 >> + %2 = bitcast float %f1 to i32 >> +; CHECK-NOT: shr >> +; CHECK: movmskps >> +; CHECK-NEXT: and >> + %shr.i = lshr i32 %2, 31 >> + call void @llvm.lifetime.end(i64 -1, i8* %0) >> + call void @llvm.lifetime.end(i64 -1, i8* %1) >> + ret i32 %shr.i >> +} >> + >> +define i32 @float_add_signbit(float %f1, float %f2) nounwind uwtable readnone ssp { >> +entry: >> + %__x.addr.i = alloca float, align 4 >> + %__u.i = alloca %union.anon, align 4 >> + %add = fadd float %f1, %f2 >> + %0 = bitcast float* %__x.addr.i to i8* >> + call void @llvm.lifetime.start(i64 -1, i8* %0) >> + %1 = bitcast %union.anon* %__u.i to i8* >> + call void @llvm.lifetime.start(i64 -1, i8* %1) >> + store float %add, float* %__x.addr.i, align 4 >> + %__f.i = getelementptr inbounds %union.anon* %__u.i, i64 0, i32 0 >> + store float %add, float* %__f.i, align 4 >> + %2 = bitcast float %add to i32 >> +; CHECK-NOT: shr >> +; CHECK: movmskps >> +; CHECK-NEXT: and >> + %shr.i = lshr i32 %2, 31 >> + call void @llvm.lifetime.end(i64 -1, i8* %0) >> + call void @llvm.lifetime.end(i64 -1, i8* %1) >> + ret i32 %shr.i >> +} >> + >> +declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind >> + >> +declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From jasonwkim at google.com Wed Jun 1 13:36:53 2011 From: jasonwkim at google.com (Jason Kim) Date: Wed, 1 Jun 2011 11:36:53 -0700 Subject: [llvm-commits] [llvm] r131411 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp In-Reply-To: <4DE1ABD6.8050500@gmail.com> References: <20110516163521.E1B8B2A6C12C@llvm.org> <4DE1ABD6.8050500@gmail.com> Message-ID: On Sat, May 28, 2011 at 7:13 PM, Rafael ?vila de Esp?ndola wrote: > On 11-05-16 12:35 PM, Jason W Kim wrote: >> Author: jasonwkim >> Date: Mon May 16 11:35:21 2011 >> New Revision: 131411 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=131411&view=rev >> Log: >> Add a FIXME reminder to remove ForceARMElfPIC switch. > > Do you have an ETA? The option is a pretty bad violation of the MC design... Thanks for reminder. Its on todo queue. Sometime next week hopefully. -jason > > Cheers, > Rafael > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From stuart at apple.com Wed Jun 1 13:32:25 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 18:32:25 -0000 Subject: [llvm-commits] [llvm] r132411 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <20110601183225.4BFD12A6C12C@llvm.org> Author: stuart Date: Wed Jun 1 13:32:25 2011 New Revision: 132411 URL: http://llvm.org/viewvc/llvm-project?rev=132411&view=rev Log: Fix double FGETSIGN to work on x86_32; followup to 132396. rdar://problem/5660695 Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132411&r1=132410&r2=132411&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun 1 13:32:25 2011 @@ -1759,11 +1759,14 @@ if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && Op.getOperand(0).getValueType().isFloatingPoint() && !Op.getOperand(0).getValueType().isVector()) { - if (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) { + if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) { + EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ? + Op.getValueType() : MVT::i32; // Make a FGETSIGN + SHL to move the sign bit into the appropriate // place. We expect the SHL to be eliminated by other optimizations. - SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(), - Op.getOperand(0)); + SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); + if (Ty != Op.getValueType()) + Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); unsigned ShVal = Op.getValueType().getSizeInBits()-1; SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, From atrick at apple.com Wed Jun 1 13:45:25 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 01 Jun 2011 11:45:25 -0700 Subject: [llvm-commits] [llvm] r132405 - /llvm/trunk/include/llvm/Target/TargetInstrItineraries.h In-Reply-To: <20110601171908.B97292A6C12C@llvm.org> References: <20110601171908.B97292A6C12C@llvm.org> Message-ID: <9029090E-EA98-4946-BA67-F868E2AD0721@apple.com> Thanks much. I had the fix but got sidetracked just before checking in! -Andy On Jun 1, 2011, at 10:19 AM, Benjamin Kramer wrote: > Author: d0k > Date: Wed Jun 1 12:19:08 2011 > New Revision: 132405 > > URL: http://llvm.org/viewvc/llvm-project?rev=132405&view=rev > Log: > Initialize IssueWidth to zero. > > Fixes valgrind errors in the CellSPU backend. > > Modified: > llvm/trunk/include/llvm/Target/TargetInstrItineraries.h > > Modified: llvm/trunk/include/llvm/Target/TargetInstrItineraries.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrItineraries.h?rev=132405&r1=132404&r2=132405&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetInstrItineraries.h (original) > +++ llvm/trunk/include/llvm/Target/TargetInstrItineraries.h Wed Jun 1 12:19:08 2011 > @@ -122,7 +122,8 @@ > > InstrItineraryData(const InstrStage *S, const unsigned *OS, > const unsigned *F, const InstrItinerary *I) > - : Stages(S), OperandCycles(OS), Forwardings(F), Itineraries(I) {} > + : Stages(S), OperandCycles(OS), Forwardings(F), Itineraries(I), > + IssueWidth(0) {} > > /// isEmpty - Returns true if there are no itineraries. > /// > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Wed Jun 1 13:45:02 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 01 Jun 2011 18:45:02 -0000 Subject: [llvm-commits] [llvm] r132413 - /llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Message-ID: <20110601184502.679822A6C12C@llvm.org> Author: stoklund Date: Wed Jun 1 13:45:02 2011 New Revision: 132413 URL: http://llvm.org/viewvc/llvm-project?rev=132413&view=rev Log: Revert r132358 "Simplify the eviction policy by making the failsafe explicit." This commit caused regressions in i386 flops-[568], matrix, salsa20, 256.bzip2, and enc-md5. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=132413&r1=132412&r2=132413&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Wed Jun 1 13:45:02 2011 @@ -39,7 +39,6 @@ #include "llvm/CodeGen/RegAllocRegistry.h" #include "llvm/CodeGen/RegisterCoalescer.h" #include "llvm/Target/TargetOptions.h" -#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -53,10 +52,6 @@ STATISTIC(NumLocalSplits, "Number of split local live ranges"); STATISTIC(NumEvicted, "Number of interferences evicted"); -static cl::opt -ComplexEviction("complex-eviction", cl::Hidden, - cl::desc("Use complex eviction heuristics")); - static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator", createGreedyRegisterAllocator); @@ -99,8 +94,7 @@ enum LiveRangeStage { RS_New, ///< Never seen before. RS_First, ///< First time in the queue. - RS_Evicted, ///< Requeued after being evicted. - RS_Second, ///< Second time in the queue, ready for splitting. + RS_Second, ///< Second time in the queue. RS_Global, ///< Produced by global splitting. RS_Local, ///< Produced by local splitting. RS_Spill ///< Produced by spilling. @@ -124,6 +118,15 @@ } } + // Eviction. Sometimes an assigned live range can be evicted without + // conditions, but other times it must be split after being evicted to avoid + // infinite loops. + enum CanEvict { + CE_Never, ///< Can never evict. + CE_Always, ///< Can always evict. + CE_WithSplit ///< Can evict only if range is also split or spilled. + }; + // splitting state. std::auto_ptr SA; std::auto_ptr SE; @@ -195,10 +198,8 @@ SlotIndex getPrevMappedIndex(const MachineInstr*); void calcPrevSlots(); unsigned nextSplitPoint(unsigned); - bool hasDefInRange(const LiveInterval&, const LiveInterval&); - bool hasUseInRange(const LiveInterval&, const LiveInterval&); - bool canEvict(LiveInterval &A, LiveInterval &B); - bool canEvictInterference(LiveInterval&, unsigned, float&, bool); + CanEvict canEvict(LiveInterval &A, LiveInterval &B); + bool canEvictInterference(LiveInterval&, unsigned, float&); unsigned tryAssign(LiveInterval&, AllocationOrder&, SmallVectorImpl&); @@ -219,7 +220,6 @@ const char *const RAGreedy::StageName[] = { "RS_New", "RS_First", - "RS_Evicted", "RS_Second", "RS_Global", "RS_Local", @@ -401,60 +401,18 @@ // Interference eviction //===----------------------------------------------------------------------===// -/// hasDefInRange - Returns true when any def of A happens where B is live. -/// -/// The SSA form of live intervals guarantees: -/// -/// A.overlaps(B) == hasDefInRange(A, B) || hasDefInRange(B, A) -/// -bool RAGreedy::hasDefInRange(const LiveInterval &A, const LiveInterval &B) { - for (LiveInterval::const_vni_iterator I = A.vni_begin(), E = A.vni_end(); - I != E; ++I) { - const VNInfo *VNI = *I; - if (VNI->isUnused()) - continue; - if (B.liveAt(VNI->def)) - return true; - } - return false; -} - -/// hasUseInRange - Returns true when any def or use of A happens where B is -/// live. The following is always true: -/// -/// A.overlaps(B) == hasUseInRange(A, B) || hasUseInRange(B, A) -/// -bool RAGreedy::hasUseInRange(const LiveInterval &A, const LiveInterval &B) { - if (hasDefInRange(A, B)) - return true; - for (MachineRegisterInfo::use_nodbg_iterator I = MRI->use_nodbg_begin(A.reg), - E = MRI->use_nodbg_end(); I != E; ++I) { - if (I.getOperand().isUndef()) - continue; - SlotIndex Idx = Indexes->getInstructionIndex(&*I).getDefIndex(); - if (B.liveAt(Idx)) - return true; - } - return false; -} - /// canEvict - determine if A can evict the assigned live range B. The eviction /// policy defined by this function together with the allocation order defined /// by enqueue() decides which registers ultimately end up being split and /// spilled. /// -/// Safeguards ensure that canEvict can never cause an infinite loop. -/// -bool RAGreedy::canEvict(LiveInterval &A, LiveInterval &B) { - if (!ComplexEviction) - return A.weight > B.weight; - - // Evict B if it has no uses in A's live range. - if (!hasUseInRange(B, A)) { - DEBUG(dbgs() << "Bypass: " << B << '\n'); - return true; - } - return A.weight > B.weight; +/// This function must define a non-circular relation when it returns CE_Always, +/// otherwise infinite eviction loops are possible. When evicting a <= RS_Second +/// range, it is possible to return CE_WithSplit which forces the evicted +/// register to be split or spilled before it can evict anything again. That +/// guarantees progress. +RAGreedy::CanEvict RAGreedy::canEvict(LiveInterval &A, LiveInterval &B) { + return A.weight > B.weight ? CE_Always : CE_Never; } /// canEvict - Return true if all interferences between VirtReg and PhysReg can @@ -462,7 +420,7 @@ /// Return false if any interference is heavier than MaxWeight. /// On return, set MaxWeight to the maximal spill weight of an interference. bool RAGreedy::canEvictInterference(LiveInterval &VirtReg, unsigned PhysReg, - float &MaxWeight, bool OnlyCheap) { + float &MaxWeight) { float Weight = 0; for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) { LiveIntervalUnion::Query &Q = query(VirtReg, *AliasI); @@ -475,22 +433,18 @@ LiveInterval *Intf = Q.interferingVRegs()[i - 1]; if (TargetRegisterInfo::isPhysicalRegister(Intf->reg)) return false; - if (getStage(*Intf) == RS_Spill) - return false; if (Intf->weight >= MaxWeight) return false; - // When we are simply looking for a cheaper alternative, don't try too - // hard. The evicted range shouldn't end up getting split. - if (OnlyCheap) { - // Don't evict something that won't be able to reevict something else. - if (getStage(*Intf) != RS_First) - return false; - // Don't break a satisfied hint. - if (VRM->getRegAllocPref(Intf->reg) == *AliasI) + switch (canEvict(VirtReg, *Intf)) { + case CE_Always: + break; + case CE_Never: + return false; + case CE_WithSplit: + if (getStage(*Intf) > RS_Second) return false; + break; } - if (VirtReg.isSpillable() && !canEvict(VirtReg, *Intf)) - return false; Weight = std::max(Weight, Intf->weight); } } @@ -499,28 +453,17 @@ } /// tryEvict - Try to evict all interferences for a physreg. -/// @param VirtReg Currently unassigned virtual register. -/// @param Order Physregs to try. -/// @param CostPerUseLimit Only look at physregs below this cost per use. -/// @return Physreg to assign VirtReg, or 0. +/// @param VirtReg Currently unassigned virtual register. +/// @param Order Physregs to try. +/// @return Physreg to assign VirtReg, or 0. unsigned RAGreedy::tryEvict(LiveInterval &VirtReg, AllocationOrder &Order, SmallVectorImpl &NewVRegs, unsigned CostPerUseLimit) { - // Ranges that may have been evicted or requeued for splitting may never evict - // other ranges. That could cause looping. - // Spill ranges can always evict. - LiveRangeStage Stage = getStage(VirtReg); - if (Stage >= RS_Evicted && VirtReg.isSpillable()) - return 0; NamedRegionTimer T("Evict", TimerGroupName, TimePassesIsEnabled); - bool OnlyCheap = CostPerUseLimit != ~0u; - // Keep track of the lightest single interference seen so far. - // When scavenging for a cheap register, never consider evicting heavier - // ranges. - float BestWeight = OnlyCheap ? VirtReg.weight : HUGE_VALF; + float BestWeight = HUGE_VALF; unsigned BestPhys = 0; Order.rewind(); @@ -532,7 +475,7 @@ continue; float Weight = BestWeight; - if (!canEvictInterference(VirtReg, PhysReg, Weight, OnlyCheap)) + if (!canEvictInterference(VirtReg, PhysReg, Weight)) continue; // This is an eviction candidate. @@ -561,11 +504,11 @@ unassign(*Intf, VRM->getPhys(Intf->reg)); ++NumEvicted; NewVRegs.push_back(Intf); - // Prevent looping by marking the evicted ranges as RS_Evicted. - // When OnlyCheap is set, Intf is guaranteed to have a smaller spill - // weight which also prevents looping. - if (!OnlyCheap && getStage(*Intf) < RS_Evicted) - LRStage[Intf->reg] = RS_Evicted; + // Prevent looping by forcing the evicted ranges to be split before they + // can evict anything else. + if (getStage(*Intf) < RS_Second && + canEvict(VirtReg, *Intf) == CE_WithSplit) + LRStage[Intf->reg] = RS_Second; } } return BestPhys; @@ -1474,8 +1417,12 @@ LiveRangeStage Stage = getStage(VirtReg); DEBUG(dbgs() << StageName[Stage] << '\n'); - if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs)) - return PhysReg; + // Try to evict a less worthy live range, but only for ranges from the primary + // queue. The RS_Second ranges already failed to do this, and they should not + // get a second chance until they have been split. + if (Stage != RS_Second) + if (unsigned PhysReg = tryEvict(VirtReg, Order, NewVRegs)) + return PhysReg; assert(NewVRegs.empty() && "Cannot append to existing NewVRegs"); From evan.cheng at apple.com Wed Jun 1 13:56:41 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 01 Jun 2011 11:56:41 -0700 Subject: [llvm-commits] [llvm] r132411 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp In-Reply-To: <20110601183225.4BFD12A6C12C@llvm.org> References: <20110601183225.4BFD12A6C12C@llvm.org> Message-ID: <58DE98BF-15F3-4754-944A-E8F89BDBEB9D@apple.com> Stuart, why is this hard coded to i32? Is fgetsign double -> i64 legal? Evan On Jun 1, 2011, at 11:32 AM, Stuart Hastings wrote: > Author: stuart > Date: Wed Jun 1 13:32:25 2011 > New Revision: 132411 > > URL: http://llvm.org/viewvc/llvm-project?rev=132411&view=rev > Log: > Fix double FGETSIGN to work on x86_32; followup to 132396. > rdar://problem/5660695 > > Modified: > llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp > > Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132411&r1=132410&r2=132411&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) > +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun 1 13:32:25 2011 > @@ -1759,11 +1759,14 @@ > if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && > Op.getOperand(0).getValueType().isFloatingPoint() && > !Op.getOperand(0).getValueType().isVector()) { > - if (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) { > + if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) { > + EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ? > + Op.getValueType() : MVT::i32; > // Make a FGETSIGN + SHL to move the sign bit into the appropriate > // place. We expect the SHL to be eliminated by other optimizations. > - SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(), > - Op.getOperand(0)); > + SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); > + if (Ty != Op.getValueType()) > + Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); > unsigned ShVal = Op.getValueType().getSizeInBits()-1; > SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); > return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stuart at apple.com Wed Jun 1 14:01:17 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 12:01:17 -0700 Subject: [llvm-commits] [llvm] r132411 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp In-Reply-To: <58DE98BF-15F3-4754-944A-E8F89BDBEB9D@apple.com> References: <20110601183225.4BFD12A6C12C@llvm.org> <58DE98BF-15F3-4754-944A-E8F89BDBEB9D@apple.com> Message-ID: On Jun 1, 2011, at 11:56 AM, Evan Cheng wrote: > Stuart, why is this hard coded to i32? Is fgetsign double -> i64 legal? Yes, fgetsign of a double is not legal on x86_32 (because i64 isn't legal on x86_32). Is there a better way to do this? stuart > > Evan > > On Jun 1, 2011, at 11:32 AM, Stuart Hastings wrote: > >> Author: stuart >> Date: Wed Jun 1 13:32:25 2011 >> New Revision: 132411 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132411&view=rev >> Log: >> Fix double FGETSIGN to work on x86_32; followup to 132396. >> rdar://problem/5660695 >> >> Modified: >> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp >> >> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132411&r1=132410&r2=132411&view=diff >> ============================================================================== >> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) >> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun 1 13:32:25 2011 >> @@ -1759,11 +1759,14 @@ >> if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && >> Op.getOperand(0).getValueType().isFloatingPoint() && >> !Op.getOperand(0).getValueType().isVector()) { >> - if (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) { >> + if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) { >> + EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ? >> + Op.getValueType() : MVT::i32; >> // Make a FGETSIGN + SHL to move the sign bit into the appropriate >> // place. We expect the SHL to be eliminated by other optimizations. >> - SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(), >> - Op.getOperand(0)); >> + SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); >> + if (Ty != Op.getValueType()) >> + Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); >> unsigned ShVal = Op.getValueType().getSizeInBits()-1; >> SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); >> return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From atrick at apple.com Wed Jun 1 14:14:56 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 01 Jun 2011 19:14:56 -0000 Subject: [llvm-commits] [llvm] r132416 - /llvm/trunk/lib/Analysis/ScalarEvolution.cpp Message-ID: <20110601191456.62EFD2A6C12C@llvm.org> Author: atrick Date: Wed Jun 1 14:14:56 2011 New Revision: 132416 URL: http://llvm.org/viewvc/llvm-project?rev=132416&view=rev Log: SCEV: missing null check fix for r132360, dragonegg crash. Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolution.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolution.cpp?rev=132416&r1=132415&r2=132416&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolution.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolution.cpp Wed Jun 1 14:14:56 2011 @@ -1081,9 +1081,8 @@ const SCEVAddRecExpr *PreAR = dyn_cast( SE->getAddRecExpr(PreStart, Step, L, SCEV::FlagAnyWrap)); - if (PreAR && PreAR->getNoWrapFlags(SCEV::FlagNSW)) { + if (PreAR && PreAR->getNoWrapFlags(SCEV::FlagNSW)) return PreStart; - } // 2. Direct overflow check on the step operation's expression. unsigned BitWidth = SE->getTypeSizeInBits(AR->getType()); @@ -1104,7 +1103,8 @@ ICmpInst::Predicate Pred; const SCEV *OverflowLimit = getOverflowLimitForStep(Step, &Pred, SE); - if (SE->isLoopEntryGuardedByCond(L, Pred, PreStart, OverflowLimit)) { + if (OverflowLimit && + SE->isLoopEntryGuardedByCond(L, Pred, PreStart, OverflowLimit)) { return PreStart; } return 0; From evan.cheng at apple.com Wed Jun 1 14:43:30 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 01 Jun 2011 12:43:30 -0700 Subject: [llvm-commits] [llvm] r132411 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp In-Reply-To: References: <20110601183225.4BFD12A6C12C@llvm.org> <58DE98BF-15F3-4754-944A-E8F89BDBEB9D@apple.com> Message-ID: On Jun 1, 2011, at 12:01 PM, Stuart Hastings wrote: > > On Jun 1, 2011, at 11:56 AM, Evan Cheng wrote: > >> Stuart, why is this hard coded to i32? Is fgetsign double -> i64 legal? > > Yes, fgetsign of a double is not legal on x86_32 (because i64 isn't legal on x86_32). But your code first check isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32) So it's assuming if i64 fgetsign is legal then i32 fgetsign must be legal. This works for x86, but it may not work for some 64-bit arch which has no native support for i32. > > Is there a better way to do this? Your code should be restructured to check isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) first. If not, then it checks isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32) and generates a fgetsign + zero_extend if that's the case. Evan > > stuart > >> >> Evan >> >> On Jun 1, 2011, at 11:32 AM, Stuart Hastings wrote: >> >>> Author: stuart >>> Date: Wed Jun 1 13:32:25 2011 >>> New Revision: 132411 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=132411&view=rev >>> Log: >>> Fix double FGETSIGN to work on x86_32; followup to 132396. >>> rdar://problem/5660695 >>> >>> Modified: >>> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp >>> >>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp >>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132411&r1=132410&r2=132411&view=diff >>> ============================================================================== >>> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) >>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun 1 13:32:25 2011 >>> @@ -1759,11 +1759,14 @@ >>> if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && >>> Op.getOperand(0).getValueType().isFloatingPoint() && >>> !Op.getOperand(0).getValueType().isVector()) { >>> - if (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) { >>> + if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) { >>> + EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ? >>> + Op.getValueType() : MVT::i32; >>> // Make a FGETSIGN + SHL to move the sign bit into the appropriate >>> // place. We expect the SHL to be eliminated by other optimizations. >>> - SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(), >>> - Op.getOperand(0)); >>> + SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); >>> + if (Ty != Op.getValueType()) >>> + Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); >>> unsigned ShVal = Op.getValueType().getSizeInBits()-1; >>> SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); >>> return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, >>> >>> >>> _______________________________________________ >>> llvm-commits mailing list >>> llvm-commits at cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> > From nadav.rotem at intel.com Wed Jun 1 14:47:10 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Wed, 01 Jun 2011 19:47:10 -0000 Subject: [llvm-commits] [llvm] r132418 - in /llvm/trunk/lib/CodeGen/SelectionDAG: LegalizeIntegerTypes.cpp LegalizeTypes.cpp LegalizeTypes.h LegalizeTypesGeneric.cpp LegalizeVectorTypes.cpp Message-ID: <20110601194711.127662A6C12C@llvm.org> Author: nadav Date: Wed Jun 1 14:47:10 2011 New Revision: 132418 URL: http://llvm.org/viewvc/llvm-project?rev=132418&view=rev Log: Refactor LegalizeTypes: Erase LegalizeAction and make the type legalizer use the TargetLowering enum. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=132418&r1=132417&r2=132418&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Wed Jun 1 14:47:10 2011 @@ -174,24 +174,24 @@ default: assert(false && "Unknown type action!"); break; - case Legal: + case TargetLowering::TypeLegal: break; - case PromoteInteger: + case TargetLowering::TypePromoteInteger: if (NOutVT.bitsEq(NInVT)) // The input promotes to the same size. Convert the promoted value. return DAG.getNode(ISD::BITCAST, dl, NOutVT, GetPromotedInteger(InOp)); break; - case SoftenFloat: + case TargetLowering::TypeSoftenFloat: // Promote the integer operand by hand. return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, GetSoftenedFloat(InOp)); - case ExpandInteger: - case ExpandFloat: + case TargetLowering::TypeExpandInteger: + case TargetLowering::TypeExpandFloat: break; - case ScalarizeVector: + case TargetLowering::TypeScalarizeVector: // Convert the element to an integer and promote it by hand. return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT, BitConvertToInteger(GetScalarizedVector(InOp))); - case SplitVector: { + case TargetLowering::TypeSplitVector: { // For example, i32 = BITCAST v2i16 on alpha. Convert the split // pieces of the input into integers and reassemble in the final type. SDValue Lo, Hi; @@ -208,7 +208,7 @@ JoinIntegers(Lo, Hi)); return DAG.getNode(ISD::BITCAST, dl, NOutVT, InOp); } - case WidenVector: + case TargetLowering::TypeWidenVector: if (OutVT.bitsEq(NInVT)) // The input is widened to the same size. Convert to the widened value. return DAG.getNode(ISD::BITCAST, dl, OutVT, GetWidenedVector(InOp)); @@ -342,7 +342,8 @@ EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); DebugLoc dl = N->getDebugLoc(); - if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) { + if (getTypeAction(N->getOperand(0).getValueType()) + == TargetLowering::TypePromoteInteger) { SDValue Res = GetPromotedInteger(N->getOperand(0)); assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!"); @@ -507,11 +508,11 @@ switch (getTypeAction(N->getOperand(0).getValueType())) { default: llvm_unreachable("Unknown type action!"); - case Legal: - case ExpandInteger: + case TargetLowering::TypeLegal: + case TargetLowering::TypeExpandInteger: Res = N->getOperand(0); break; - case PromoteInteger: + case TargetLowering::TypePromoteInteger: Res = GetPromotedInteger(N->getOperand(0)); break; } @@ -1513,7 +1514,8 @@ } else { // For example, extension of an i48 to an i64. The operand type necessarily // promotes to the result type, so will end up being expanded too. - assert(getTypeAction(Op.getValueType()) == PromoteInteger && + assert(getTypeAction(Op.getValueType()) == + TargetLowering::TypePromoteInteger && "Only know how to promote this result!"); SDValue Res = GetPromotedInteger(Op); assert(Res.getValueType() == N->getValueType(0) && @@ -2030,7 +2032,8 @@ } else { // For example, extension of an i48 to an i64. The operand type necessarily // promotes to the result type, so will end up being expanded too. - assert(getTypeAction(Op.getValueType()) == PromoteInteger && + assert(getTypeAction(Op.getValueType()) == + TargetLowering::TypePromoteInteger && "Only know how to promote this result!"); SDValue Res = GetPromotedInteger(Op); assert(Res.getValueType() == N->getValueType(0) && @@ -2178,7 +2181,8 @@ } else { // For example, extension of an i48 to an i64. The operand type necessarily // promotes to the result type, so will end up being expanded too. - assert(getTypeAction(Op.getValueType()) == PromoteInteger && + assert(getTypeAction(Op.getValueType()) == + TargetLowering::TypePromoteInteger && "Only know how to promote this result!"); SDValue Res = GetPromotedInteger(Op); assert(Res.getValueType() == N->getValueType(0) && Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp?rev=132418&r1=132417&r2=132418&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp Wed Jun 1 14:47:10 2011 @@ -224,38 +224,38 @@ switch (getTypeAction(ResultVT)) { default: assert(false && "Unknown action!"); - case Legal: + case TargetLowering::TypeLegal: break; // The following calls must take care of *all* of the node's results, // not just the illegal result they were passed (this includes results // with a legal type). Results can be remapped using ReplaceValueWith, // or their promoted/expanded/etc values registered in PromotedIntegers, // ExpandedIntegers etc. - case PromoteInteger: + case TargetLowering::TypePromoteInteger: PromoteIntegerResult(N, i); Changed = true; goto NodeDone; - case ExpandInteger: + case TargetLowering::TypeExpandInteger: ExpandIntegerResult(N, i); Changed = true; goto NodeDone; - case SoftenFloat: + case TargetLowering::TypeSoftenFloat: SoftenFloatResult(N, i); Changed = true; goto NodeDone; - case ExpandFloat: + case TargetLowering::TypeExpandFloat: ExpandFloatResult(N, i); Changed = true; goto NodeDone; - case ScalarizeVector: + case TargetLowering::TypeScalarizeVector: ScalarizeVectorResult(N, i); Changed = true; goto NodeDone; - case SplitVector: + case TargetLowering::TypeSplitVector: SplitVectorResult(N, i); Changed = true; goto NodeDone; - case WidenVector: + case TargetLowering::TypeWidenVector: WidenVectorResult(N, i); Changed = true; goto NodeDone; @@ -277,36 +277,36 @@ switch (getTypeAction(OpVT)) { default: assert(false && "Unknown action!"); - case Legal: + case TargetLowering::TypeLegal: continue; // The following calls must either replace all of the node's results // using ReplaceValueWith, and return "false"; or update the node's // operands in place, and return "true". - case PromoteInteger: + case TargetLowering::TypePromoteInteger: NeedsReanalyzing = PromoteIntegerOperand(N, i); Changed = true; break; - case ExpandInteger: + case TargetLowering::TypeExpandInteger: NeedsReanalyzing = ExpandIntegerOperand(N, i); Changed = true; break; - case SoftenFloat: + case TargetLowering::TypeSoftenFloat: NeedsReanalyzing = SoftenFloatOperand(N, i); Changed = true; break; - case ExpandFloat: + case TargetLowering::TypeExpandFloat: NeedsReanalyzing = ExpandFloatOperand(N, i); Changed = true; break; - case ScalarizeVector: + case TargetLowering::TypeScalarizeVector: NeedsReanalyzing = ScalarizeVectorOperand(N, i); Changed = true; break; - case SplitVector: + case TargetLowering::TypeSplitVector: NeedsReanalyzing = SplitVectorOperand(N, i); Changed = true; break; - case WidenVector: + case TargetLowering::TypeWidenVector: NeedsReanalyzing = WidenVectorOperand(N, i); Changed = true; break; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h?rev=132418&r1=132417&r2=132418&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypes.h Wed Jun 1 14:47:10 2011 @@ -57,16 +57,6 @@ // 1+ - This is a node which has this many unprocessed operands. }; private: - enum LegalizeAction { - Legal, // The target natively supports this type. - PromoteInteger, // Replace this integer type with a larger one. - ExpandInteger, // Split this integer type into two of half the size. - SoftenFloat, // Convert this float type to a same size integer type. - ExpandFloat, // Split this float type into two of half the size. - ScalarizeVector, // Replace this one-element vector with its element type. - SplitVector, // Split this vector type into two of half the size. - WidenVector // This vector type should be widened into a larger vector. - }; /// ValueTypeActions - This is a bitvector that contains two bits for each /// simple value type, where the two bits correspond to the LegalizeAction @@ -74,27 +64,8 @@ TargetLowering::ValueTypeActionImpl ValueTypeActions; /// getTypeAction - Return how we should legalize values of this type. - LegalizeAction getTypeAction(EVT VT) const { - switch (TLI.getTypeAction(*DAG.getContext(), VT)) { - default: - assert(false && "Unknown legalize action!"); - case TargetLowering::Legal: - return Legal; - case TargetLowering::TypePromoteInteger: - return PromoteInteger; - case TargetLowering::TypeExpandInteger: - return ExpandInteger; - case TargetLowering::TypeExpandFloat: - return ExpandFloat; - case TargetLowering::TypeSoftenFloat: - return SoftenFloat; - case TargetLowering::TypeWidenVector: - return WidenVector; - case TargetLowering::TypeScalarizeVector: - return ScalarizeVector; - case TargetLowering::TypeSplitVector: - return SplitVector; - } + TargetLowering::LegalizeTypeAction getTypeAction(EVT VT) const { + return TLI.getTypeAction(*DAG.getContext(), VT); } /// isTypeLegal - Return true if this type is legal on this target. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp?rev=132418&r1=132417&r2=132418&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp Wed Jun 1 14:47:10 2011 @@ -43,36 +43,36 @@ switch (getTypeAction(InVT)) { default: assert(false && "Unknown type action!"); - case Legal: - case PromoteInteger: + case TargetLowering::TypeLegal: + case TargetLowering::TypePromoteInteger: break; - case SoftenFloat: + case TargetLowering::TypeSoftenFloat: // Convert the integer operand instead. SplitInteger(GetSoftenedFloat(InOp), Lo, Hi); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); return; - case ExpandInteger: - case ExpandFloat: + case TargetLowering::TypeExpandInteger: + case TargetLowering::TypeExpandFloat: // Convert the expanded pieces of the input. GetExpandedOp(InOp, Lo, Hi); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); return; - case SplitVector: + case TargetLowering::TypeSplitVector: GetSplitVector(InOp, Lo, Hi); if (TLI.isBigEndian()) std::swap(Lo, Hi); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); return; - case ScalarizeVector: + case TargetLowering::TypeScalarizeVector: // Convert the element instead. SplitInteger(BitConvertToInteger(GetScalarizedVector(InOp)), Lo, Hi); Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); Hi = DAG.getNode(ISD::BITCAST, dl, NOutVT, Hi); return; - case WidenVector: { + case TargetLowering::TypeWidenVector: { assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BITCAST"); InOp = GetWidenedVector(InOp); EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp?rev=132418&r1=132417&r2=132418&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp Wed Jun 1 14:47:10 2011 @@ -526,13 +526,13 @@ switch (getTypeAction(InVT)) { default: assert(false && "Unknown type action!"); - case Legal: - case PromoteInteger: - case SoftenFloat: - case ScalarizeVector: + case TargetLowering::TypeLegal: + case TargetLowering::TypePromoteInteger: + case TargetLowering::TypeSoftenFloat: + case TargetLowering::TypeScalarizeVector: break; - case ExpandInteger: - case ExpandFloat: + case TargetLowering::TypeExpandInteger: + case TargetLowering::TypeExpandFloat: // A scalar to vector conversion, where the scalar needs expansion. // If the vector is being split in two then we can just convert the // expanded pieces. @@ -545,7 +545,7 @@ return; } break; - case SplitVector: + case TargetLowering::TypeSplitVector: // If the input is a vector that needs to be split, convert each split // piece of the input now. GetSplitVector(InOp, Lo, Hi); @@ -774,7 +774,7 @@ EVT InVT = N->getOperand(0).getValueType(); switch (getTypeAction(InVT)) { default: llvm_unreachable("Unexpected type action!"); - case Legal: { + case TargetLowering::TypeLegal: { EVT InNVT = EVT::getVectorVT(*DAG.getContext(), InVT.getVectorElementType(), LoVT.getVectorNumElements()); Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0), @@ -783,10 +783,10 @@ DAG.getIntPtrConstant(InNVT.getVectorNumElements())); break; } - case SplitVector: + case TargetLowering::TypeSplitVector: GetSplitVector(N->getOperand(0), Lo, Hi); break; - case WidenVector: { + case TargetLowering::TypeWidenVector: { // If the result needs to be split and the input needs to be widened, // the two types must have different lengths. Use the widened result // and extract from it to do the split. @@ -1439,7 +1439,7 @@ unsigned Opcode = N->getOpcode(); unsigned InVTNumElts = InVT.getVectorNumElements(); - if (getTypeAction(InVT) == WidenVector) { + if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { InOp = GetWidenedVector(N->getOperand(0)); InVT = InOp.getValueType(); InVTNumElts = InVT.getVectorNumElements(); @@ -1515,7 +1515,7 @@ SDValue ShOp = N->getOperand(1); EVT ShVT = ShOp.getValueType(); - if (getTypeAction(ShVT) == WidenVector) { + if (getTypeAction(ShVT) == TargetLowering::TypeWidenVector) { ShOp = GetWidenedVector(ShOp); ShVT = ShOp.getValueType(); } @@ -1557,9 +1557,9 @@ default: assert(false && "Unknown type action!"); break; - case Legal: + case TargetLowering::TypeLegal: break; - case PromoteInteger: + case TargetLowering::TypePromoteInteger: // If the InOp is promoted to the same size, convert it. Otherwise, // fall out of the switch and widen the promoted input. InOp = GetPromotedInteger(InOp); @@ -1567,13 +1567,13 @@ if (WidenVT.bitsEq(InVT)) return DAG.getNode(ISD::BITCAST, dl, WidenVT, InOp); break; - case SoftenFloat: - case ExpandInteger: - case ExpandFloat: - case ScalarizeVector: - case SplitVector: + case TargetLowering::TypeSoftenFloat: + case TargetLowering::TypeExpandInteger: + case TargetLowering::TypeExpandFloat: + case TargetLowering::TypeScalarizeVector: + case TargetLowering::TypeSplitVector: break; - case WidenVector: + case TargetLowering::TypeWidenVector: // If the InOp is widened to the same size, convert it. Otherwise, fall // out of the switch and widen the widened input. InOp = GetWidenedVector(InOp); @@ -1653,7 +1653,7 @@ unsigned NumOperands = N->getNumOperands(); bool InputWidened = false; // Indicates we need to widen the input. - if (getTypeAction(InVT) != WidenVector) { + if (getTypeAction(InVT) != TargetLowering::TypeWidenVector) { if (WidenVT.getVectorNumElements() % InVT.getVectorNumElements() == 0) { // Add undef vectors to widen to correct length. unsigned NumConcat = WidenVT.getVectorNumElements() / @@ -1732,7 +1732,7 @@ ISD::CvtCode CvtCode = cast(N)->getCvtCode(); unsigned InVTNumElts = InVT.getVectorNumElements(); - if (getTypeAction(InVT) == WidenVector) { + if (getTypeAction(InVT) == TargetLowering::TypeWidenVector) { InOp = GetWidenedVector(InOp); InVT = InOp.getValueType(); InVTNumElts = InVT.getVectorNumElements(); @@ -1800,7 +1800,7 @@ SDValue Idx = N->getOperand(1); DebugLoc dl = N->getDebugLoc(); - if (getTypeAction(InOp.getValueType()) == WidenVector) + if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) InOp = GetWidenedVector(InOp); EVT InVT = InOp.getValueType(); @@ -1882,7 +1882,7 @@ EVT CondEltVT = CondVT.getVectorElementType(); EVT CondWidenVT = EVT::getVectorVT(*DAG.getContext(), CondEltVT, WidenNumElts); - if (getTypeAction(CondVT) == WidenVector) + if (getTypeAction(CondVT) == TargetLowering::TypeWidenVector) Cond1 = GetWidenedVector(Cond1); if (Cond1.getValueType() != CondWidenVT) @@ -2026,7 +2026,7 @@ DebugLoc dl = N->getDebugLoc(); unsigned NumElts = VT.getVectorNumElements(); SDValue InOp = N->getOperand(0); - if (getTypeAction(InOp.getValueType()) == WidenVector) + if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) InOp = GetWidenedVector(InOp); EVT InVT = InOp.getValueType(); EVT InEltVT = InVT.getVectorElementType(); @@ -2081,7 +2081,7 @@ unsigned NumOperands = N->getNumOperands(); for (unsigned i=0; i < NumOperands; ++i) { SDValue InOp = N->getOperand(i); - if (getTypeAction(InOp.getValueType()) == WidenVector) + if (getTypeAction(InOp.getValueType()) == TargetLowering::TypeWidenVector) InOp = GetWidenedVector(InOp); for (unsigned j=0; j < NumInElts; ++j) Ops[Idx++] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, InOp, From echristo at apple.com Wed Jun 1 14:53:27 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 01 Jun 2011 12:53:27 -0700 Subject: [llvm-commits] [llvm-gcc-4.2] r132366 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp In-Reply-To: <4DE5E2AC.4060305@free.fr> References: <20110531220830.960642A6C12C@llvm.org> <4DE5E2AC.4060305@free.fr> Message-ID: <67365CC3-F2BD-4230-B221-FC51ECBA2C77@apple.com> On May 31, 2011, at 11:56 PM, Duncan Sands wrote: > Hi Eric, > >> Look through struct wrapped types when deciding whether or not it's a >> simple emit for the input constraints in an inline asm. > > testcase? Sorry about that. Committed one :) Thanks! -eric From stuart at apple.com Wed Jun 1 14:53:44 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 12:53:44 -0700 Subject: [llvm-commits] [llvm] r132411 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp In-Reply-To: References: <20110601183225.4BFD12A6C12C@llvm.org> <58DE98BF-15F3-4754-944A-E8F89BDBEB9D@apple.com> Message-ID: <67205B70-8901-414A-8B55-89B56F08CC13@apple.com> On Jun 1, 2011, at 12:43 PM, Evan Cheng wrote: > > On Jun 1, 2011, at 12:01 PM, Stuart Hastings wrote: > >> >> On Jun 1, 2011, at 11:56 AM, Evan Cheng wrote: >> >>> Stuart, why is this hard coded to i32? Is fgetsign double -> i64 legal? >> >> Yes, fgetsign of a double is not legal on x86_32 (because i64 isn't legal on x86_32). > > But your code first check > isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32) > > So it's assuming if i64 fgetsign is legal then i32 fgetsign must be legal. This works for x86, but it may not work for some 64-bit arch which has no native support for i32. > >> >> Is there a better way to do this? > > Your code should be restructured to check isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) first. If not, then it checks isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32) and generates a fgetsign + zero_extend if that's the case. O.K., I'll fix it. Thank you, stuart > > Evan > >> >> stuart >> >>> >>> Evan >>> >>> On Jun 1, 2011, at 11:32 AM, Stuart Hastings wrote: >>> >>>> Author: stuart >>>> Date: Wed Jun 1 13:32:25 2011 >>>> New Revision: 132411 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=132411&view=rev >>>> Log: >>>> Fix double FGETSIGN to work on x86_32; followup to 132396. >>>> rdar://problem/5660695 >>>> >>>> Modified: >>>> llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp >>>> >>>> Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp >>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132411&r1=132410&r2=132411&view=diff >>>> ============================================================================== >>>> --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) >>>> +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun 1 13:32:25 2011 >>>> @@ -1759,11 +1759,14 @@ >>>> if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && >>>> Op.getOperand(0).getValueType().isFloatingPoint() && >>>> !Op.getOperand(0).getValueType().isVector()) { >>>> - if (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) { >>>> + if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) { >>>> + EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ? >>>> + Op.getValueType() : MVT::i32; >>>> // Make a FGETSIGN + SHL to move the sign bit into the appropriate >>>> // place. We expect the SHL to be eliminated by other optimizations. >>>> - SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Op.getValueType(), >>>> - Op.getOperand(0)); >>>> + SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); >>>> + if (Ty != Op.getValueType()) >>>> + Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); >>>> unsigned ShVal = Op.getValueType().getSizeInBits()-1; >>>> SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); >>>> return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, >>>> >>>> >>>> _______________________________________________ >>>> llvm-commits mailing list >>>> llvm-commits at cs.uiuc.edu >>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >>> >> > From stuart at apple.com Wed Jun 1 14:52:21 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 19:52:21 -0000 Subject: [llvm-commits] [llvm] r132419 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/isint.ll test/CodeGen/X86/pr9127.ll test/CodeGen/X86/setoeq.ll Message-ID: <20110601195221.9B6FB2A6C12C@llvm.org> Author: stuart Date: Wed Jun 1 14:52:20 2011 New Revision: 132419 URL: http://llvm.org/viewvc/llvm-project?rev=132419&view=rev Log: Revert 132404 to appease a buildbot. rdar://problem/5993888 Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/isint.ll llvm/trunk/test/CodeGen/X86/pr9127.ll llvm/trunk/test/CodeGen/X86/setoeq.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=132419&r1=132418&r2=132419&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jun 1 14:52:20 2011 @@ -9391,8 +9391,6 @@ case X86ISD::UCOMI: return "X86ISD::UCOMI"; case X86ISD::SETCC: return "X86ISD::SETCC"; case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; - case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; - case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; case X86ISD::CMOV: return "X86ISD::CMOV"; case X86ISD::BRCOND: return "X86ISD::BRCOND"; case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; @@ -11670,88 +11668,12 @@ } -// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) -// where both setccs reference the same FP CMP, and rewrite for CMPEQSS -// and friends. Likewise for OR -> CMPNEQSS. -static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, - TargetLowering::DAGCombinerInfo &DCI, - const X86Subtarget *Subtarget) { - unsigned opcode; - - // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but - // we're requiring SSE2 for both. - if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { - SDValue N0 = N->getOperand(0); - SDValue N1 = N->getOperand(1); - SDValue CMP = N0->getOperand(1); - SDValue CMP0 = CMP->getOperand(0); - SDValue CMP1 = CMP->getOperand(1); - bool isFP = CMP0.getValueType().isFloatingPoint(); - DebugLoc DL = N->getDebugLoc(); - - if (isFP) { - bool ExpectingFlags = false; - // Check for any users that want flags: - for (SDNode::use_iterator UI = N->use_begin(), - UE = N->use_end(); - !ExpectingFlags && UI != UE; ++UI) - switch (UI->getOpcode()) { - default: - case ISD::BR_CC: - case ISD::BRCOND: - case ISD::SELECT: - ExpectingFlags = true; - break; - case ISD::CopyToReg: - case ISD::SIGN_EXTEND: - case ISD::ZERO_EXTEND: - case ISD::ANY_EXTEND: - break; - } - - if (!ExpectingFlags) { - enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); - enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); - - if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { - X86::CondCode tmp = cc0; - cc0 = cc1; - cc1 = tmp; - } - - if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || - (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { - bool is64BitFP = (CMP0.getValueType() == MVT::f64); - X86ISD::NodeType NTOperator = is64BitFP ? - X86ISD::FSETCCsd : X86ISD::FSETCCss; - // FIXME: need symbolic constants for these magic numbers. - // See X86ATTInstPrinter.cpp:printSSECC(). - unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; - SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP0, CMP1, - DAG.getConstant(x86cc, MVT::i8)); - SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, - OnesOrZeroesF); - SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, - DAG.getConstant(1, MVT::i32)); - SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); - return OneBitOfTruth; - } - } - } - } - return SDValue(); -} - static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) { if (DCI.isBeforeLegalizeOps()) return SDValue(); - SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); - if (R.getNode()) - return R; - // Want to form PANDN nodes, in the hopes of then easily combining them with // OR and AND nodes to form PBLEND/PSIGN. EVT VT = N->getValueType(0); @@ -11781,10 +11703,6 @@ if (DCI.isBeforeLegalizeOps()) return SDValue(); - SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); - if (R.getNode()) - return R; - EVT VT = N->getValueType(0); if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) return SDValue(); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=132419&r1=132418&r2=132419&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Jun 1 14:52:20 2011 @@ -94,11 +94,6 @@ // one's or all zero's. SETCC_CARRY, // R = carry_bit ? ~0 : 0 - /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. - /// Operands are two FP values to compare; result is a mask of - /// 0s or 1s. Generally DTRT for C/C++ with NaNs. - FSETCCss, FSETCCsd, - /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, /// result in an integer GPR. Needs masking for scalar result. FGETSIGNx86, Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=132419&r1=132418&r2=132419&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Wed Jun 1 14:52:20 2011 @@ -41,8 +41,6 @@ def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; -def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>; -def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>; def X86pshufb : SDNode<"X86ISD::PSHUFB", SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>>; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=132419&r1=132418&r2=132419&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Jun 1 14:52:20 2011 @@ -23,9 +23,6 @@ def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; -def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; -def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; - def SDTX86Cmov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=132419&r1=132418&r2=132419&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jun 1 14:52:20 2011 @@ -1056,37 +1056,13 @@ XD, VEX_4V; } -let Constraints = "$src1 = $dst" in { -def CMPSSrr : SIi8<0xC2, MRMSrcReg, - (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc), - "cmp${cc}ss\t{$src2, $dst|$dst, $src2}", - [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS; -def CMPSSrm : SIi8<0xC2, MRMSrcMem, - (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc), - "cmp${cc}ss\t{$src2, $dst|$dst, $src2}", - [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS; -def CMPSDrr : SIi8<0xC2, MRMSrcReg, - (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc), - "cmp${cc}sd\t{$src2, $dst|$dst, $src2}", - [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD; -def CMPSDrm : SIi8<0xC2, MRMSrcMem, - (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc), - "cmp${cc}sd\t{$src2, $dst|$dst, $src2}", - [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD; -} let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in { -def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg, - (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2), - "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS; -def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem, - (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2), - "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS; -def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg, - (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2), - "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD; -def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem, - (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2), - "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD; + defm CMPSS : sse12_cmp_scalar, XS; + defm CMPSD : sse12_cmp_scalar, XD; } multiclass sse12_cmp_scalar_int %t +; RUN: not grep cmp %t +; RUN: not grep xor %t +; RUN: grep jne %t | count 1 +; RUN: grep jp %t | count 1 +; RUN: grep setnp %t | count 1 +; RUN: grep sete %t | count 1 +; RUN: grep and %t | count 1 +; RUN: grep cvt %t | count 4 define i32 @isint_return(double %d) nounwind { -; CHECK-NOT: xor -; CHECK: cvt %i = fptosi double %d to i32 -; CHECK-NEXT: cvt %e = sitofp i32 %i to double -; CHECK: cmpeqsd %c = fcmp oeq double %d, %e -; CHECK-NEXT: movd -; CHECK-NEXT: andl %z = zext i1 %c to i32 ret i32 %z } @@ -17,14 +19,9 @@ declare void @foo() define void @isint_branch(double %d) nounwind { -; CHECK: cvt %i = fptosi double %d to i32 -; CHECK-NEXT: cvt %e = sitofp i32 %i to double -; CHECK: ucomisd %c = fcmp oeq double %d, %e -; CHECK-NEXT: jne -; CHECK-NEXT: jp br i1 %c, label %true, label %false true: call void @foo() Modified: llvm/trunk/test/CodeGen/X86/pr9127.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr9127.ll?rev=132419&r1=132418&r2=132419&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr9127.ll (original) +++ llvm/trunk/test/CodeGen/X86/pr9127.ll Wed Jun 1 14:52:20 2011 @@ -10,4 +10,4 @@ } ; test that the load is folded. -; CHECK: cmpeqsd (%{{rdi|rdx}}), %xmm0 +; CHECK: ucomisd (%{{rdi|rdx}}), %xmm0 Modified: llvm/trunk/test/CodeGen/X86/setoeq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setoeq.ll?rev=132419&r1=132418&r2=132419&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/setoeq.ll (original) +++ llvm/trunk/test/CodeGen/X86/setoeq.ll Wed Jun 1 14:52:20 2011 @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -march=x86 | grep set | count 2 +; RUN: llc < %s -march=x86 | grep and define zeroext i8 @t(double %x) nounwind readnone { entry: @@ -6,16 +7,5 @@ %1 = sitofp i32 %0 to double ; [#uses=1] %2 = fcmp oeq double %1, %x ; [#uses=1] %retval12 = zext i1 %2 to i8 ; [#uses=1] -; CHECK: cmpeqsd - ret i8 %retval12 -} - -define zeroext i8 @u(double %x) nounwind readnone { -entry: - %0 = fptosi double %x to i32 ; [#uses=1] - %1 = sitofp i32 %0 to double ; [#uses=1] - %2 = fcmp une double %1, %x ; [#uses=1] - %retval12 = zext i1 %2 to i8 ; [#uses=1] -; CHECK: cmpneqsd ret i8 %retval12 } From echristo at apple.com Wed Jun 1 14:55:10 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 01 Jun 2011 19:55:10 -0000 Subject: [llvm-commits] [llvm] r132420 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp test/CodeGen/ARM/inlineasm3.ll Message-ID: <20110601195511.080892A6C12C@llvm.org> Author: echristo Date: Wed Jun 1 14:55:10 2011 New Revision: 132420 URL: http://llvm.org/viewvc/llvm-project?rev=132420&view=rev Log: Allow bitcasts between valid types of the same size and vector types if the vector type is legal. Fixes rdar://9306086 Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=132420&r1=132419&r2=132420&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jun 1 14:55:10 2011 @@ -282,6 +282,12 @@ // Vector/Vector bitcast. return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); } + + // Trivial bitcast if the types are the same size and the destination + // vector type is legal. + if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && + TLI.isTypeLegal(ValueVT)) + return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); assert(ValueVT.getVectorElementType() == PartVT && ValueVT.getVectorNumElements() == 1 && Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=132420&r1=132419&r2=132420&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original) +++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Wed Jun 1 14:55:10 2011 @@ -23,3 +23,13 @@ %asmtmp2 = tail call i32 asm sideeffect "vmov d30, $1\0Avmov.32 $0, d30[0]\0A", "=r,w,~{d30}"(<2 x i32> undef) nounwind ret void } + +; Radar 9306086 + +%0 = type { <8 x i8>, <16 x i8>* } + +define hidden void @conv4_8_E() nounwind { +entry: +%asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1, :128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind +unreachable +} From aggarwa4 at illinois.edu Wed Jun 1 16:29:59 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 01 Jun 2011 21:29:59 -0000 Subject: [llvm-commits] [poolalloc] r132423 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp Message-ID: <20110601212959.320F52A6C12C@llvm.org> Author: aggarwa4 Date: Wed Jun 1 16:29:58 2011 New Revision: 132423 URL: http://llvm.org/viewvc/llvm-project?rev=132423&view=rev Log: 1. Rename a few functions. 2. Recognize byval functions earlier. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132423&r1=132422&r2=132423&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Wed Jun 1 16:29:58 2011 @@ -61,8 +61,8 @@ bool visitInvokeInst(Module &M, InvokeInst &CI); bool visitCallSite(Module &M, CallSite CS); bool visitIndirectCallSite(Module &M, CallSite CS); - bool visitInternalFunction(Module &M, Function &F); - bool visitExternalFunction(Module &M, Function &F); + bool visitInternalByValFunction(Module &M, Function &F); + bool visitExternalByValFunction(Module &M, Function &F); bool visitByValFunction(Module &M, Function &F); bool visitMain(Module &M, Function &F); bool visitVarArgFunction(Module &M, Function &F); Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132423&r1=132422&r2=132423&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Wed Jun 1 16:29:58 2011 @@ -107,9 +107,20 @@ continue; std::string name = F.getName(); - if (strncmp(name.c_str(), "tc.", 3) == 0) continue; + // check for byval arguments + bool hasByValArg = false; + for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { + if (I->hasByValAttr()) { + hasByValArg = true; + break; + } + } + if(hasByValArg) { + ByValFunctions.push_back(&F); + } + // Iterate and find all varargs functions if(F.isVarArg()) { VAArgFunctions.push_back(&F); @@ -134,13 +145,11 @@ } } - std::vector toProcess; for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; if(F.isDeclaration()) continue; // record all the original functions in the program - toProcess.push_back(&F); // Loop over all of the instructions in the function, // adding their return type as well as the types of their operands. @@ -169,9 +178,9 @@ } } - while(!toProcess.empty()) { - Function *F = toProcess.back(); - toProcess.pop_back(); + while(!ByValFunctions.empty()) { + Function *F = ByValFunctions.back(); + ByValFunctions.pop_back(); modified |= visitByValFunction(M, *F); } @@ -580,24 +589,6 @@ bool TypeChecks::visitByValFunction(Module &M, Function &F) { - // check for byval arguments - bool hasByValArg = false; - for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { - if (I->hasByValAttr()) { - if(EnableTypeSafeOpt) { - if(!TS->isTypeSafe(cast(&I), &F)) { - hasByValArg = true; - break; - } - } else { - hasByValArg = true; - break; - } - } - } - if(!hasByValArg) - return false; - // For internal functions // Replace with a cloned function with extra arguments // That takes as argument the original pointers without a byval parameter too @@ -610,7 +601,7 @@ // To assume that the metadata for the byval arguments is TOP if(F.hasInternalLinkage()) { - visitInternalFunction(M, F); + visitInternalByValFunction(M, F); } else { // create internal clone Function *F_clone = CloneFunction(&F); @@ -618,13 +609,13 @@ F.setLinkage(GlobalValue::InternalLinkage); F.getParent()->getFunctionList().push_back(F_clone); F.replaceAllUsesWith(F_clone); - visitInternalFunction(M, *F_clone); - visitExternalFunction(M, F); + visitInternalByValFunction(M, *F_clone); + visitExternalByValFunction(M, F); } return true; } -bool TypeChecks::visitInternalFunction(Module &M, Function &F) { +bool TypeChecks::visitInternalByValFunction(Module &M, Function &F) { // Create a list of the argument types in the new function. std::vectorTP; @@ -777,7 +768,7 @@ return true; } -bool TypeChecks::visitExternalFunction(Module &M, Function &F) { +bool TypeChecks::visitExternalByValFunction(Module &M, Function &F) { // A list of the byval arguments that we are setting metadata for typedef SmallVector RegisteredArgTy; From stuart at apple.com Wed Jun 1 16:33:14 2011 From: stuart at apple.com (Stuart Hastings) Date: Wed, 01 Jun 2011 21:33:14 -0000 Subject: [llvm-commits] [llvm] r132424 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/isint.ll test/CodeGen/X86/pr9127.ll test/CodeGen/X86/setoeq.ll Message-ID: <20110601213314.C109B2A6C12E@llvm.org> Author: stuart Date: Wed Jun 1 16:33:14 2011 New Revision: 132424 URL: http://llvm.org/viewvc/llvm-project?rev=132424&view=rev Log: Recommit 132404 with fixes. rdar://problem/5993888 Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/isint.ll llvm/trunk/test/CodeGen/X86/pr9127.ll llvm/trunk/test/CodeGen/X86/setoeq.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132424&r1=132423&r2=132424&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun 1 16:33:14 2011 @@ -1759,13 +1759,14 @@ if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && Op.getOperand(0).getValueType().isFloatingPoint() && !Op.getOperand(0).getValueType().isVector()) { - if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) { - EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ? - Op.getValueType() : MVT::i32; + bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); + bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); + if (OpVTLegal || i32Legal) { + EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; // Make a FGETSIGN + SHL to move the sign bit into the appropriate // place. We expect the SHL to be eliminated by other optimizations. SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); - if (Ty != Op.getValueType()) + if (!OpVTLegal) Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); unsigned ShVal = Op.getValueType().getSizeInBits()-1; SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=132424&r1=132423&r2=132424&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jun 1 16:33:14 2011 @@ -9391,6 +9391,8 @@ case X86ISD::UCOMI: return "X86ISD::UCOMI"; case X86ISD::SETCC: return "X86ISD::SETCC"; case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; + case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; + case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; case X86ISD::CMOV: return "X86ISD::CMOV"; case X86ISD::BRCOND: return "X86ISD::BRCOND"; case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; @@ -11668,12 +11670,88 @@ } +// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) +// where both setccs reference the same FP CMP, and rewrite for CMPEQSS +// and friends. Likewise for OR -> CMPNEQSS. +static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const X86Subtarget *Subtarget) { + unsigned opcode; + + // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but + // we're requiring SSE2 for both. + if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + SDValue CMP = N0->getOperand(1); + SDValue CMP0 = CMP->getOperand(0); + SDValue CMP1 = CMP->getOperand(1); + EVT VT = CMP0.getValueType(); + DebugLoc DL = N->getDebugLoc(); + + if (VT == MVT::f32 || VT == MVT::f64) { + bool ExpectingFlags = false; + // Check for any users that want flags: + for (SDNode::use_iterator UI = N->use_begin(), + UE = N->use_end(); + !ExpectingFlags && UI != UE; ++UI) + switch (UI->getOpcode()) { + default: + case ISD::BR_CC: + case ISD::BRCOND: + case ISD::SELECT: + ExpectingFlags = true; + break; + case ISD::CopyToReg: + case ISD::SIGN_EXTEND: + case ISD::ZERO_EXTEND: + case ISD::ANY_EXTEND: + break; + } + + if (!ExpectingFlags) { + enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); + enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); + + if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { + X86::CondCode tmp = cc0; + cc0 = cc1; + cc1 = tmp; + } + + if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || + (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { + bool is64BitFP = (CMP0.getValueType() == MVT::f64); + X86ISD::NodeType NTOperator = is64BitFP ? + X86ISD::FSETCCsd : X86ISD::FSETCCss; + // FIXME: need symbolic constants for these magic numbers. + // See X86ATTInstPrinter.cpp:printSSECC(). + unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; + SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP0, CMP1, + DAG.getConstant(x86cc, MVT::i8)); + SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, + OnesOrZeroesF); + SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, + DAG.getConstant(1, MVT::i32)); + SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); + return OneBitOfTruth; + } + } + } + } + return SDValue(); +} + static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) { if (DCI.isBeforeLegalizeOps()) return SDValue(); + SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); + if (R.getNode()) + return R; + // Want to form PANDN nodes, in the hopes of then easily combining them with // OR and AND nodes to form PBLEND/PSIGN. EVT VT = N->getValueType(0); @@ -11703,6 +11781,10 @@ if (DCI.isBeforeLegalizeOps()) return SDValue(); + SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); + if (R.getNode()) + return R; + EVT VT = N->getValueType(0); if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) return SDValue(); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=132424&r1=132423&r2=132424&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Jun 1 16:33:14 2011 @@ -94,6 +94,11 @@ // one's or all zero's. SETCC_CARRY, // R = carry_bit ? ~0 : 0 + /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. + /// Operands are two FP values to compare; result is a mask of + /// 0s or 1s. Generally DTRT for C/C++ with NaNs. + FSETCCss, FSETCCsd, + /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, /// result in an integer GPR. Needs masking for scalar result. FGETSIGNx86, Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=132424&r1=132423&r2=132424&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Wed Jun 1 16:33:14 2011 @@ -41,6 +41,8 @@ def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; +def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>; +def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>; def X86pshufb : SDNode<"X86ISD::PSHUFB", SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>>; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=132424&r1=132423&r2=132424&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Wed Jun 1 16:33:14 2011 @@ -23,6 +23,9 @@ def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; +def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; +def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; + def SDTX86Cmov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=132424&r1=132423&r2=132424&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Wed Jun 1 16:33:14 2011 @@ -1056,13 +1056,37 @@ XD, VEX_4V; } +let Constraints = "$src1 = $dst" in { +def CMPSSrr : SIi8<0xC2, MRMSrcReg, + (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc), + "cmp${cc}ss\t{$src2, $dst|$dst, $src2}", + [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS; +def CMPSSrm : SIi8<0xC2, MRMSrcMem, + (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc), + "cmp${cc}ss\t{$src2, $dst|$dst, $src2}", + [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS; +def CMPSDrr : SIi8<0xC2, MRMSrcReg, + (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc), + "cmp${cc}sd\t{$src2, $dst|$dst, $src2}", + [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD; +def CMPSDrm : SIi8<0xC2, MRMSrcMem, + (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc), + "cmp${cc}sd\t{$src2, $dst|$dst, $src2}", + [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD; +} let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in { - defm CMPSS : sse12_cmp_scalar, XS; - defm CMPSD : sse12_cmp_scalar, XD; +def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg, + (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2), + "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS; +def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem, + (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2), + "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS; +def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg, + (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2), + "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD; +def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem, + (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2), + "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD; } multiclass sse12_cmp_scalar_int %t -; RUN: not grep cmp %t -; RUN: not grep xor %t -; RUN: grep jne %t | count 1 -; RUN: grep jp %t | count 1 -; RUN: grep setnp %t | count 1 -; RUN: grep sete %t | count 1 -; RUN: grep and %t | count 1 -; RUN: grep cvt %t | count 4 +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s define i32 @isint_return(double %d) nounwind { +; CHECK-NOT: xor +; CHECK: cvt %i = fptosi double %d to i32 +; CHECK-NEXT: cvt %e = sitofp i32 %i to double +; CHECK: cmpeqsd %c = fcmp oeq double %d, %e +; CHECK-NEXT: movd +; CHECK-NEXT: andl %z = zext i1 %c to i32 ret i32 %z } @@ -19,9 +17,14 @@ declare void @foo() define void @isint_branch(double %d) nounwind { +; CHECK: cvt %i = fptosi double %d to i32 +; CHECK-NEXT: cvt %e = sitofp i32 %i to double +; CHECK: ucomisd %c = fcmp oeq double %d, %e +; CHECK-NEXT: jne +; CHECK-NEXT: jp br i1 %c, label %true, label %false true: call void @foo() Modified: llvm/trunk/test/CodeGen/X86/pr9127.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr9127.ll?rev=132424&r1=132423&r2=132424&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr9127.ll (original) +++ llvm/trunk/test/CodeGen/X86/pr9127.ll Wed Jun 1 16:33:14 2011 @@ -10,4 +10,4 @@ } ; test that the load is folded. -; CHECK: ucomisd (%{{rdi|rdx}}), %xmm0 +; CHECK: cmpeqsd (%{{rdi|rdx}}), %xmm0 Modified: llvm/trunk/test/CodeGen/X86/setoeq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setoeq.ll?rev=132424&r1=132423&r2=132424&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/setoeq.ll (original) +++ llvm/trunk/test/CodeGen/X86/setoeq.ll Wed Jun 1 16:33:14 2011 @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=x86 | grep set | count 2 -; RUN: llc < %s -march=x86 | grep and +; RUN: llc < %s -march=x86 | FileCheck %s define zeroext i8 @t(double %x) nounwind readnone { entry: @@ -7,5 +6,16 @@ %1 = sitofp i32 %0 to double ; [#uses=1] %2 = fcmp oeq double %1, %x ; [#uses=1] %retval12 = zext i1 %2 to i8 ; [#uses=1] +; CHECK: cmpeqsd + ret i8 %retval12 +} + +define zeroext i8 @u(double %x) nounwind readnone { +entry: + %0 = fptosi double %x to i32 ; [#uses=1] + %1 = sitofp i32 %0 to double ; [#uses=1] + %2 = fcmp une double %1, %x ; [#uses=1] + %retval12 = zext i1 %2 to i8 ; [#uses=1] +; CHECK: cmpneqsd ret i8 %retval12 } From dpatel at apple.com Wed Jun 1 17:03:25 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 01 Jun 2011 22:03:25 -0000 Subject: [llvm-commits] [llvm] r132427 - in /llvm/trunk: lib/CodeGen/AsmPrinter/DwarfDebug.cpp lib/CodeGen/AsmPrinter/DwarfDebug.h test/CodeGen/X86/dbg-const.ll Message-ID: <20110601220325.A46C32A6C12C@llvm.org> Author: dpatel Date: Wed Jun 1 17:03:25 2011 New Revision: 132427 URL: http://llvm.org/viewvc/llvm-project?rev=132427&view=rev Log: Do not drop constant values when a variable's content is described using .debug_loc entries. Added: llvm/trunk/test/CodeGen/X86/dbg-const.ll Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=132427&r1=132426&r2=132427&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Jun 1 17:03:25 2011 @@ -1410,16 +1410,6 @@ HI = History.begin(), HE = History.end(); HI != HE; ++HI) { const MachineInstr *Begin = *HI; assert(Begin->isDebugValue() && "Invalid History entry"); - MachineLocation MLoc; - if (Begin->getNumOperands() == 3) { - if (Begin->getOperand(0).isReg() && Begin->getOperand(1).isImm()) - MLoc.set(Begin->getOperand(0).getReg(), Begin->getOperand(1).getImm()); - } else - MLoc = Asm->getDebugValueLocation(Begin); - - // FIXME: emitDebugLoc only understands registers. - if (!MLoc.getReg()) - continue; // Compute the range for a register location. const MCSymbol *FLabel = getLabelBeforeInsn(Begin); @@ -1442,7 +1432,25 @@ } // The value is valid until the next DBG_VALUE or clobber. - DotDebugLocEntries.push_back(DotDebugLocEntry(FLabel, SLabel, MLoc, Var)); + MachineLocation MLoc; + if (Begin->getNumOperands() == 3) { + if (Begin->getOperand(0).isReg() && Begin->getOperand(1).isImm()) { + MLoc.set(Begin->getOperand(0).getReg(), + Begin->getOperand(1).getImm()); + DotDebugLocEntries. + push_back(DotDebugLocEntry(FLabel, SLabel, MLoc, Var)); + } + // FIXME: Handle isFPImm also. + else if (Begin->getOperand(0).isImm()) { + DotDebugLocEntries. + push_back(DotDebugLocEntry(FLabel, SLabel, + Begin->getOperand(0).getImm())); + } + } else { + MLoc = Asm->getDebugValueLocation(Begin); + DotDebugLocEntries. + push_back(DotDebugLocEntry(FLabel, SLabel, MLoc, Var)); + } } DotDebugLocEntries.push_back(DotDebugLocEntry()); } @@ -2586,7 +2594,20 @@ MCSymbol *end = Asm->OutStreamer.getContext().CreateTempSymbol(); Asm->EmitLabelDifference(end, begin, 2); Asm->OutStreamer.EmitLabel(begin); - if (DV.hasComplexAddress()) { + if (Entry.isConstant()) { + DIBasicType BTy(DV.getType()); + if (BTy.Verify() && + (BTy.getEncoding() == dwarf::DW_ATE_signed + || BTy.getEncoding() == dwarf::DW_ATE_signed_char)) { + Asm->OutStreamer.AddComment("DW_OP_consts"); + Asm->EmitInt8(dwarf::DW_OP_consts); + Asm->EmitSLEB128(Entry.getConstant()); + } else { + Asm->OutStreamer.AddComment("DW_OP_constu"); + Asm->EmitInt8(dwarf::DW_OP_constu); + Asm->EmitULEB128(Entry.getConstant()); + } + } else if (DV.hasComplexAddress()) { unsigned N = DV.getNumAddrElements(); unsigned i = 0; if (N >= 2 && DV.getAddrElement(0) == DIBuilder::OpPlus) { @@ -2620,6 +2641,7 @@ else llvm_unreachable("unknown Opcode found in complex address"); } } else { + // Regular entry. Asm->EmitDwarfRegOp(Entry.Loc); } Asm->OutStreamer.EmitLabel(end); Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h?rev=132427&r1=132426&r2=132427&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.h Wed Jun 1 17:03:25 2011 @@ -68,10 +68,19 @@ MachineLocation Loc; const MDNode *Variable; bool Merged; - DotDebugLocEntry() : Begin(0), End(0), Variable(0), Merged(false) {} + bool Constant; + int64_t iConstant; + DotDebugLocEntry() + : Begin(0), End(0), Variable(0), Merged(false), + Constant(false), iConstant(0) {} DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, MachineLocation &L, const MDNode *V) - : Begin(B), End(E), Loc(L), Variable(V), Merged(false) {} + : Begin(B), End(E), Loc(L), Variable(V), Merged(false), + Constant(false), iConstant(0) {} + DotDebugLocEntry(const MCSymbol *B, const MCSymbol *E, int64_t i) + : Begin(B), End(E), Variable(0), Merged(false), + Constant(true), iConstant(i) {} + /// Empty entries are also used as a trigger to emit temp label. Such /// labels are referenced is used to find debug_loc offset for a given DIE. bool isEmpty() { return Begin == 0 && End == 0; } @@ -82,6 +91,8 @@ Next->Begin = Begin; Merged = true; } + bool isConstant() { return Constant; } + int64_t getConstant() { return iConstant; } } DotDebugLocEntry; //===----------------------------------------------------------------------===// Added: llvm/trunk/test/CodeGen/X86/dbg-const.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-const.ll?rev=132427&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-const.ll (added) +++ llvm/trunk/test/CodeGen/X86/dbg-const.ll Wed Jun 1 17:03:25 2011 @@ -0,0 +1,34 @@ +; RUN: llc < %s - | FileCheck %s +target triple = "x86_64-apple-darwin10.0.0" + +;CHECK: ## DW_OP_constu +;CHECK-NEXT: .byte 42 +define i32 @foobar() nounwind readonly noinline ssp { +entry: + %call = tail call i32 @bar(), !dbg !11 + tail call void @llvm.dbg.value(metadata !8, i64 0, metadata !6), !dbg !9 + %call2 = tail call i32 @bar(), !dbg !11 + tail call void @llvm.dbg.value(metadata !{i32 %call}, i64 0, metadata !6), !dbg !11 + %add = add nsw i32 %call2, %call, !dbg !12 + ret i32 %add, !dbg !10 +} + +declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone +declare i32 @bar() nounwind readnone + +!llvm.dbg.sp = !{!0} +!llvm.dbg.lv.foobar = !{!6} + +!0 = metadata !{i32 524334, i32 0, metadata !1, metadata !"foobar", metadata !"foobar", metadata !"foobar", metadata !1, i32 12, metadata !3, i1 false, i1 true, i32 0, i32 0, null, i1 false, i1 true, i32 ()* @foobar} +!1 = metadata !{i32 524329, metadata !"mu.c", metadata !"/private/tmp", metadata !2} +!2 = metadata !{i32 524305, i32 0, i32 12, metadata !"mu.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 114183)", i1 true, i1 true, metadata !"", i32 0} +!3 = metadata !{i32 524309, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !4, i32 0, null} +!4 = metadata !{metadata !5} +!5 = metadata !{i32 524324, metadata !1, metadata !"int", metadata !1, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} +!6 = metadata !{i32 524544, metadata !7, metadata !"j", metadata !1, i32 15, metadata !5} +!7 = metadata !{i32 524299, metadata !0, i32 12, i32 52, metadata !1, i32 0} +!8 = metadata !{i32 42} +!9 = metadata !{i32 15, i32 12, metadata !7, null} +!10 = metadata !{i32 23, i32 3, metadata !7, null} +!11 = metadata !{i32 17, i32 3, metadata !7, null} +!12 = metadata !{i32 18, i32 3, metadata !7, null} From dpatel at apple.com Wed Jun 1 18:00:17 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 01 Jun 2011 23:00:17 -0000 Subject: [llvm-commits] [llvm] r132433 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20110601230017.9AC2C2A6C12C@llvm.org> Author: dpatel Date: Wed Jun 1 18:00:17 2011 New Revision: 132433 URL: http://llvm.org/viewvc/llvm-project?rev=132433&view=rev Log: A DBG_VALUE that truncates a range does not start another dbg value range. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=132433&r1=132432&r2=132433&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Wed Jun 1 18:00:17 2011 @@ -1411,6 +1411,11 @@ const MachineInstr *Begin = *HI; assert(Begin->isDebugValue() && "Invalid History entry"); + // Check if DBG_VALUE is truncating a range. + if (Begin->getNumOperands() > 1 && Begin->getOperand(0).isReg() + && !Begin->getOperand(0).getReg()) + continue; + // Compute the range for a register location. const MCSymbol *FLabel = getLabelBeforeInsn(Begin); const MCSymbol *SLabel = 0; From eli.friedman at gmail.com Wed Jun 1 18:16:53 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 01 Jun 2011 23:16:53 -0000 Subject: [llvm-commits] [llvm] r132434 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Message-ID: <20110601231653.76ACC2A6C12C@llvm.org> Author: efriedma Date: Wed Jun 1 18:16:53 2011 New Revision: 132434 URL: http://llvm.org/viewvc/llvm-project?rev=132434&view=rev Log: In MemoryDependenceAnalysis::getNonLocalPointerDepFromBB, if a given block is is deemed unanalyzable (and we execute one of the "goto PredTranslationFailure" statements), make sure we don't put information about the predecessors of that block into the returned data structures; this can lead to, among other things, extraneous results (which will confuse passes using memdep). Fixes an assert in GVN compiling ruby. Part of rdar://problem/9521954 . Testcase coming up soon. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=132434&r1=132433&r2=132434&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Jun 1 18:16:53 2011 @@ -937,6 +937,9 @@ SmallVector Worklist; Worklist.push_back(StartBB); + // PredList used inside loop. + SmallVector, 16> PredList; + // Keep track of the entries that we know are sorted. Previously cached // entries will all be sorted. The entries we add we only sort on demand (we // don't insert every element into its sorted position). We know that we @@ -973,22 +976,29 @@ // the same Pointer. if (!Pointer.NeedsPHITranslationFromBlock(BB)) { SkipFirstBlock = false; + SmallVector NewBlocks; for (BasicBlock **PI = PredCache->GetPreds(BB); *PI; ++PI) { // Verify that we haven't looked at this block yet. std::pair::iterator, bool> InsertRes = Visited.insert(std::make_pair(*PI, Pointer.getAddr())); if (InsertRes.second) { // First time we've looked at *PI. - Worklist.push_back(*PI); + NewBlocks.push_back(*PI); continue; } // If we have seen this block before, but it was with a different // pointer then we have a phi translation failure and we have to treat // this as a clobber. - if (InsertRes.first->second != Pointer.getAddr()) + if (InsertRes.first->second != Pointer.getAddr()) { + // Make sure to clean up the Visited map before continuing on to + // PredTranslationFailure. + for (unsigned i = 0; i < NewBlocks.size(); i++) + Visited.erase(NewBlocks[i]); goto PredTranslationFailure; + } } + Worklist.append(NewBlocks.begin(), NewBlocks.end()); continue; } @@ -1007,13 +1017,15 @@ NumSortedEntries = Cache->size(); } Cache = 0; - + + PredList.clear(); for (BasicBlock **PI = PredCache->GetPreds(BB); *PI; ++PI) { BasicBlock *Pred = *PI; - + PredList.push_back(std::make_pair(Pred, Pointer)); + // Get the PHI translated pointer in this predecessor. This can fail if // not translatable, in which case the getAddr() returns null. - PHITransAddr PredPointer(Pointer); + PHITransAddr &PredPointer = PredList.back().second; PredPointer.PHITranslateValue(BB, Pred, 0); Value *PredPtrVal = PredPointer.getAddr(); @@ -1027,6 +1039,9 @@ InsertRes = Visited.insert(std::make_pair(Pred, PredPtrVal)); if (!InsertRes.second) { + // We found the pred; take it off the list of preds to visit. + PredList.pop_back(); + // If the predecessor was visited with PredPtr, then we already did // the analysis and can ignore it. if (InsertRes.first->second == PredPtrVal) @@ -1035,14 +1050,47 @@ // Otherwise, the block was previously analyzed with a different // pointer. We can't represent the result of this case, so we just // treat this as a phi translation failure. + + // Make sure to clean up the Visited map before continuing on to + // PredTranslationFailure. + for (unsigned i = 0; i < PredList.size(); i++) + Visited.erase(PredList[i].first); + goto PredTranslationFailure; } - + } + + // Actually process results here; this need to be a separate loop to avoid + // calling getNonLocalPointerDepFromBB for blocks we don't want to return + // any results for. (getNonLocalPointerDepFromBB will modify our + // datastructures in ways the code after the PredTranslationFailure label + // doesn't expect.) + for (unsigned i = 0; i < PredList.size(); i++) { + BasicBlock *Pred = PredList[i].first; + PHITransAddr &PredPointer = PredList[i].second; + Value *PredPtrVal = PredPointer.getAddr(); + + bool CanTranslate = true; // If PHI translation was unable to find an available pointer in this // predecessor, then we have to assume that the pointer is clobbered in // that predecessor. We can still do PRE of the load, which would insert // a computation of the pointer in this predecessor. - if (PredPtrVal == 0) { + if (PredPtrVal == 0) + CanTranslate = false; + + // FIXME: it is entirely possible that PHI translating will end up with + // the same value. Consider PHI translating something like: + // X = phi [x, bb1], [y, bb2]. PHI translating for bb1 doesn't *need* + // to recurse here, pedantically speaking. + + // If getNonLocalPointerDepFromBB fails here, that means the cached + // result conflicted with the Visited list; we have to conservatively + // assume a clobber, but this also does not block PRE of the load. + if (!CanTranslate || + getNonLocalPointerDepFromBB(PredPointer, + Loc.getWithNewPtr(PredPtrVal), + isLoad, Pred, + Result, Visited)) { // Add the entry to the Result list. NonLocalDepResult Entry(Pred, MemDepResult::getClobber(Pred->getTerminator()), @@ -1058,19 +1106,6 @@ NLPI.Pair = BBSkipFirstBlockPair(); continue; } - - // FIXME: it is entirely possible that PHI translating will end up with - // the same value. Consider PHI translating something like: - // X = phi [x, bb1], [y, bb2]. PHI translating for bb1 doesn't *need* - // to recurse here, pedantically speaking. - - // If we have a problem phi translating, fall through to the code below - // to handle the failure condition. - if (getNonLocalPointerDepFromBB(PredPointer, - Loc.getWithNewPtr(PredPointer.getAddr()), - isLoad, Pred, - Result, Visited)) - goto PredTranslationFailure; } // Refresh the CacheInfo/Cache pointer so that it isn't invalidated. @@ -1087,6 +1122,9 @@ continue; PredTranslationFailure: + // The following code is "failure"; we can't produce a sane translation + // for the given block. It assumes that we haven't modified any of + // our datastructures while processing the current block. if (Cache == 0) { // Refresh the CacheInfo/Cache pointer if it got invalidated. From jstaszak at apple.com Wed Jun 1 18:26:57 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 01 Jun 2011 16:26:57 -0700 Subject: [llvm-commits] Branch Probability Message-ID: <3472A9F9-7753-470D-9088-E284CEAE042C@apple.com> Hello, This patch introduces BranchProbabilityInfo for BasicBlocks. You can test with: opt -branch-prob -debug x.ll and see how heuristics calculate weight values. -- Jakub Staszak -------------- next part -------------- A non-text attachment was scrubbed... Name: kuba_bp3.patch Type: application/octet-stream Size: 14184 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110601/4c302bc8/attachment.obj From aggarwa4 at illinois.edu Wed Jun 1 18:29:37 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 01 Jun 2011 23:29:37 -0000 Subject: [llvm-commits] [poolalloc] r132436 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110601232937.928062A6C12C@llvm.org> Author: aggarwa4 Date: Wed Jun 1 18:29:37 2011 New Revision: 132436 URL: http://llvm.org/viewvc/llvm-project?rev=132436&view=rev Log: Do not pass extra arguments for byval arguments. Remove byval attribute, and add an explicit copy. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132436&r1=132435&r2=132436&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Wed Jun 1 18:29:37 2011 @@ -100,6 +100,7 @@ // record argv modified |= visitMain(M, *MainF); + for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; @@ -144,12 +145,17 @@ continue; } } + + while(!ByValFunctions.empty()) { + Function *F = ByValFunctions.back(); + ByValFunctions.pop_back(); + modified |= visitByValFunction(M, *F); + } for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; if(F.isDeclaration()) continue; - // record all the original functions in the program // Loop over all of the instructions in the function, // adding their return type as well as the types of their operands. @@ -178,11 +184,6 @@ } } - while(!ByValFunctions.empty()) { - Function *F = ByValFunctions.back(); - ByValFunctions.pop_back(); - modified |= visitByValFunction(M, *F); - } // NOTE:must visit before VAArgFunctions, to populate the map with the // correct cloned functions. @@ -478,6 +479,7 @@ } } + // store the metadata CallInst *VAStart = NULL; for (Function::iterator B = F.begin(), FE = F.end(); B != FE; ++B) { for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { @@ -510,7 +512,9 @@ SI3->insertAfter(SI2); } } + assert(VAStart && "Varargs function without a call to VAStart???"); + // modify calls to va list functions to pass the metadata for (Function::iterator B = F.begin(), FE = F.end(); B != FE; ++B) { for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { CallInst *CI = dyn_cast(I++); @@ -617,104 +621,24 @@ bool TypeChecks::visitInternalByValFunction(Module &M, Function &F) { - // Create a list of the argument types in the new function. - std::vectorTP; + // for every byval argument + // add an alloca, a load, and a store inst + Instruction * InsertBefore = &(F.getEntryBlock().front()); for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { - TP.push_back(I->getType()); - // for every byval argument, add a new argument that indicates the source of - // the metadata. It is of the same type as the byval argument. - if (I->hasByValAttr()) - TP.push_back(I->getType()); - } - // Create the new function prototype - const FunctionType *NewFTy = FunctionType::get(F.getReturnType(), TP, false); - Function *NewF = Function::Create(NewFTy, - GlobalValue::InternalLinkage, - F.getNameStr() + ".INT", - &M); - - Function::arg_iterator NI = NewF->arg_begin(); - DenseMap ValueMap; - for (Function::arg_iterator II = F.arg_begin(); NI != NewF->arg_end(); ++II, ++NI) { - // Each new argument maps to the argument in the old function - // For these arguments, also copy over the attributes - ValueMap[II] = NI; - NI->setName(II->getName()); - NI->addAttr(F.getAttributes().getParamAttributes(II->getArgNo() + 1)); - // If we have encountered a byval argument in the old function - // We must skip over the next argument in the new function, as that is - // the newly added source argument. - if(II->hasByValAttr()) { - NI++; - // Give this new argument some name, for clarity - NI->setName("src"); - } - } - // Copy over the attributes for the function. - NewF->setAttributes(NewF->getAttributes() - .addAttr(0, F.getAttributes().getRetAttributes())); - NewF->setAttributes(NewF->getAttributes().addAttr(~0, F.getAttributes().getFnAttributes())); - - // Perform the cloning. - SmallVector Returns; - CloneFunctionInto(NewF, &F, ValueMap, Returns); - - // Add calls to the runtime to copy metadata from source to the byval argument pointer. - typedef SmallVector RegisteredArgTy; - // Keep track of the byval arguments. - RegisteredArgTy registeredArguments; - for (Function::arg_iterator I = NewF->arg_begin(), E = NewF->arg_end(); I != E; ++I) { - if (I->hasByValAttr()) { - registeredArguments.push_back(&*I); - assert (isa(I->getType())); - const PointerType * PT = cast(I->getType()); - const Type * ET = PT->getElementType(); - Value * AllocSize = ConstantInt::get(Int64Ty, TD->getTypeAllocSize(ET)); - Instruction * InsertBefore = &(NewF->getEntryBlock().front()); - // If I is the byval argument, the next argument is the source - CastInst *BCI_Dest = BitCastInst::CreatePointerCast(I, VoidPtrTy, "", InsertBefore); - CastInst *BCI_Src = BitCastInst::CreatePointerCast(++I, VoidPtrTy, "", InsertBefore); - std::vector Args; - Args.push_back(BCI_Dest); - Args.push_back(BCI_Src); - Args.push_back(AllocSize); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("copyTypeInfo", - VoidTy, - VoidPtrTy, VoidPtrTy, Int64Ty, Int32Ty, - NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", InsertBefore); - } - } - - // Find all basic blocks which terminate the function. - std::set exitBlocks; - for (inst_iterator I = inst_begin(NewF), E = inst_end(NewF); I != E; ++I) { - if (isa(*I) || isa(*I)) { - exitBlocks.insert(I->getParent()); - } - } - - // At each function exit, insert code to set the metadata as uninitialized. - for (std::set::const_iterator BI = exitBlocks.begin(), - BE = exitBlocks.end(); - BI != BE; ++BI) { - for (RegisteredArgTy::const_iterator I = registeredArguments.begin(), - E = registeredArguments.end(); - I != E; ++I) { - SmallVector args; - Instruction * Pt = &((*BI)->back()); - const PointerType * PT = cast((*I)->getType()); - const Type * ET = PT->getElementType(); - Value * AllocSize = ConstantInt::get(Int64Ty, TD->getTypeAllocSize(ET)); - CastInst *BCI = BitCastInst::CreatePointerCast(*I, VoidPtrTy, "", Pt); - std::vector Args; - Args.push_back(BCI); - Args.push_back(AllocSize); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackUnInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", Pt); + if (!I->hasByValAttr()) + continue; + if(EnableTypeSafeOpt) { + if(TS->isTypeSafe(cast(I), &F)) { + continue; + } } + assert(I->getType()->isPointerTy()); + const Type *ETy = (cast(I->getType()))->getElementType(); + AllocaInst *AI = new AllocaInst(ETy, "", InsertBefore); + // Do this before add a load/store pair, so that those uses are not replaced. + I->replaceAllUsesWith(AI); + LoadInst *LI = new LoadInst(I, "", InsertBefore); + new StoreInst(LI, AI, InsertBefore); } // Update the call sites @@ -735,17 +659,24 @@ AttributesVec.push_back(AttributeWithIndex::get(0, RAttrs)); Function::arg_iterator II = F.arg_begin(); - for(unsigned j =1;jgetNumOperands();j++, II++) { // Add the original argument Args.push_back(CI->getOperand(j)); // If there are attributes on this argument, copy them to the correct // position in the AttributesVec - if (Attributes Attrs = CallPAL.getParamAttributes(j)) - AttributesVec.push_back(AttributeWithIndex::get(Args.size(), Attrs)); - // If it is a value passed as byval, add it again, as the source + if(EnableTypeSafeOpt) { + if(TS->isTypeSafe(II, CI->getParent()->getParent())) { + if (Attributes Attrs = CallPAL.getParamAttributes(j)) + AttributesVec.push_back(AttributeWithIndex::get(Args.size(), Attrs)); + continue; + } + } + //FIXME: copy the rest of the attributes. if(II->hasByValAttr()) - Args.push_back(CI->getOperand(j)); + continue; + if (Attributes Attrs = CallPAL.getParamAttributes(j)) { + AttributesVec.push_back(AttributeWithIndex::get(Args.size(), Attrs)); + } } // Create the new attributes vec. @@ -757,7 +688,7 @@ // Create the substitute call - CallInst *CallI = CallInst::Create(NewF,Args.begin(), Args.end(),"", CI); + CallInst *CallI = CallInst::Create(&F,Args.begin(), Args.end(),"", CI); CallI->setCallingConv(CI->getCallingConv()); CallI->setAttributes(NewCallPAL); CI->replaceAllUsesWith(CallI); @@ -765,11 +696,22 @@ } } } + + // remove the byval attribute from the function + for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { + if (!I->hasByValAttr()) + continue; + if(EnableTypeSafeOpt) { + if(TS->isTypeSafe(cast(I), &F)) { + continue; + } + } + I->removeAttr(llvm::Attribute::ByVal); + } return true; } bool TypeChecks::visitExternalByValFunction(Module &M, Function &F) { - // A list of the byval arguments that we are setting metadata for typedef SmallVector RegisteredArgTy; RegisteredArgTy registeredArguments; From mcrosier at apple.com Wed Jun 1 18:32:40 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 01 Jun 2011 23:32:40 -0000 Subject: [llvm-commits] [llvm] r132437 - in /llvm/trunk/include/llvm: CodeGen/PseudoSourceValue.h Metadata.h Message-ID: <20110601233240.905C82A6C12C@llvm.org> Author: mcrosier Date: Wed Jun 1 18:32:40 2011 New Revision: 132437 URL: http://llvm.org/viewvc/llvm-project?rev=132437&view=rev Log: Typos. Modified: llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h llvm/trunk/include/llvm/Metadata.h Modified: llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h?rev=132437&r1=132436&r2=132437&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h (original) +++ llvm/trunk/include/llvm/CodeGen/PseudoSourceValue.h Wed Jun 1 18:32:40 2011 @@ -21,7 +21,7 @@ class raw_ostream; /// PseudoSourceValue - Special value supplied for machine level alias - /// analysis. It indicates that the a memory access references the functions + /// analysis. It indicates that a memory access references the functions /// stack frame (e.g., a spill slot), below the stack frame (e.g., argument /// space), or constant pool. class PseudoSourceValue : public Value { Modified: llvm/trunk/include/llvm/Metadata.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Metadata.h?rev=132437&r1=132436&r2=132437&view=diff ============================================================================== --- llvm/trunk/include/llvm/Metadata.h (original) +++ llvm/trunk/include/llvm/Metadata.h Wed Jun 1 18:32:40 2011 @@ -34,7 +34,7 @@ //===----------------------------------------------------------------------===// /// MDString - a single uniqued string. /// These are used to efficiently contain a byte sequence for metadata. -/// MDString is always unnamd. +/// MDString is always unnamed. class MDString : public Value { MDString(const MDString &); // DO NOT IMPLEMENT From mcrosier at apple.com Wed Jun 1 18:45:16 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 01 Jun 2011 16:45:16 -0700 Subject: [llvm-commits] [llvm] r132434 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp In-Reply-To: <20110601231653.76ACC2A6C12C@llvm.org> References: <20110601231653.76ACC2A6C12C@llvm.org> Message-ID: On Jun 1, 2011, at 4:16 PM, Eli Friedman wrote: > Author: efriedma > Date: Wed Jun 1 18:16:53 2011 > New Revision: 132434 > > URL: http://llvm.org/viewvc/llvm-project?rev=132434&view=rev > Log: > In MemoryDependenceAnalysis::getNonLocalPointerDepFromBB, if a given block is is deemed unanalyzable (and we execute one of the "goto PredTranslationFailure" statements), make sure we don't put information about the predecessors of that block into the returned data structures; this can lead to, among other things, extraneous results (which will confuse passes using memdep). Fixes an assert in GVN compiling ruby. Part of rdar://problem/9521954 . Don't you mean Chad > Testcase coming up soon. > > > Modified: > llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp > > Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=132434&r1=132433&r2=132434&view=diff > ============================================================================== > --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) > +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Jun 1 18:16:53 2011 > @@ -937,6 +937,9 @@ > SmallVector Worklist; > Worklist.push_back(StartBB); > > + // PredList used inside loop. > + SmallVector, 16> PredList; > + > // Keep track of the entries that we know are sorted. Previously cached > // entries will all be sorted. The entries we add we only sort on demand (we > // don't insert every element into its sorted position). We know that we > @@ -973,22 +976,29 @@ > // the same Pointer. > if (!Pointer.NeedsPHITranslationFromBlock(BB)) { > SkipFirstBlock = false; > + SmallVector NewBlocks; > for (BasicBlock **PI = PredCache->GetPreds(BB); *PI; ++PI) { > // Verify that we haven't looked at this block yet. > std::pair::iterator, bool> > InsertRes = Visited.insert(std::make_pair(*PI, Pointer.getAddr())); > if (InsertRes.second) { > // First time we've looked at *PI. > - Worklist.push_back(*PI); > + NewBlocks.push_back(*PI); > continue; > } > > // If we have seen this block before, but it was with a different > // pointer then we have a phi translation failure and we have to treat > // this as a clobber. > - if (InsertRes.first->second != Pointer.getAddr()) > + if (InsertRes.first->second != Pointer.getAddr()) { > + // Make sure to clean up the Visited map before continuing on to > + // PredTranslationFailure. > + for (unsigned i = 0; i < NewBlocks.size(); i++) > + Visited.erase(NewBlocks[i]); > goto PredTranslationFailure; > + } > } > + Worklist.append(NewBlocks.begin(), NewBlocks.end()); > continue; > } > > @@ -1007,13 +1017,15 @@ > NumSortedEntries = Cache->size(); > } > Cache = 0; > - > + > + PredList.clear(); > for (BasicBlock **PI = PredCache->GetPreds(BB); *PI; ++PI) { > BasicBlock *Pred = *PI; > - > + PredList.push_back(std::make_pair(Pred, Pointer)); > + > // Get the PHI translated pointer in this predecessor. This can fail if > // not translatable, in which case the getAddr() returns null. > - PHITransAddr PredPointer(Pointer); > + PHITransAddr &PredPointer = PredList.back().second; > PredPointer.PHITranslateValue(BB, Pred, 0); > > Value *PredPtrVal = PredPointer.getAddr(); > @@ -1027,6 +1039,9 @@ > InsertRes = Visited.insert(std::make_pair(Pred, PredPtrVal)); > > if (!InsertRes.second) { > + // We found the pred; take it off the list of preds to visit. > + PredList.pop_back(); > + > // If the predecessor was visited with PredPtr, then we already did > // the analysis and can ignore it. > if (InsertRes.first->second == PredPtrVal) > @@ -1035,14 +1050,47 @@ > // Otherwise, the block was previously analyzed with a different > // pointer. We can't represent the result of this case, so we just > // treat this as a phi translation failure. > + > + // Make sure to clean up the Visited map before continuing on to > + // PredTranslationFailure. > + for (unsigned i = 0; i < PredList.size(); i++) > + Visited.erase(PredList[i].first); > + > goto PredTranslationFailure; > } > - > + } > + > + // Actually process results here; this need to be a separate loop to avoid > + // calling getNonLocalPointerDepFromBB for blocks we don't want to return > + // any results for. (getNonLocalPointerDepFromBB will modify our > + // datastructures in ways the code after the PredTranslationFailure label > + // doesn't expect.) > + for (unsigned i = 0; i < PredList.size(); i++) { > + BasicBlock *Pred = PredList[i].first; > + PHITransAddr &PredPointer = PredList[i].second; > + Value *PredPtrVal = PredPointer.getAddr(); > + > + bool CanTranslate = true; > // If PHI translation was unable to find an available pointer in this > // predecessor, then we have to assume that the pointer is clobbered in > // that predecessor. We can still do PRE of the load, which would insert > // a computation of the pointer in this predecessor. > - if (PredPtrVal == 0) { > + if (PredPtrVal == 0) > + CanTranslate = false; > + > + // FIXME: it is entirely possible that PHI translating will end up with > + // the same value. Consider PHI translating something like: > + // X = phi [x, bb1], [y, bb2]. PHI translating for bb1 doesn't *need* > + // to recurse here, pedantically speaking. > + > + // If getNonLocalPointerDepFromBB fails here, that means the cached > + // result conflicted with the Visited list; we have to conservatively > + // assume a clobber, but this also does not block PRE of the load. > + if (!CanTranslate || > + getNonLocalPointerDepFromBB(PredPointer, > + Loc.getWithNewPtr(PredPtrVal), > + isLoad, Pred, > + Result, Visited)) { > // Add the entry to the Result list. > NonLocalDepResult Entry(Pred, > MemDepResult::getClobber(Pred->getTerminator()), > @@ -1058,19 +1106,6 @@ > NLPI.Pair = BBSkipFirstBlockPair(); > continue; > } > - > - // FIXME: it is entirely possible that PHI translating will end up with > - // the same value. Consider PHI translating something like: > - // X = phi [x, bb1], [y, bb2]. PHI translating for bb1 doesn't *need* > - // to recurse here, pedantically speaking. > - > - // If we have a problem phi translating, fall through to the code below > - // to handle the failure condition. > - if (getNonLocalPointerDepFromBB(PredPointer, > - Loc.getWithNewPtr(PredPointer.getAddr()), > - isLoad, Pred, > - Result, Visited)) > - goto PredTranslationFailure; > } > > // Refresh the CacheInfo/Cache pointer so that it isn't invalidated. > @@ -1087,6 +1122,9 @@ > continue; > > PredTranslationFailure: > + // The following code is "failure"; we can't produce a sane translation > + // for the given block. It assumes that we haven't modified any of > + // our datastructures while processing the current block. > > if (Cache == 0) { > // Refresh the CacheInfo/Cache pointer if it got invalidated. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From eli.friedman at gmail.com Wed Jun 1 18:48:21 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Wed, 1 Jun 2011 16:48:21 -0700 Subject: [llvm-commits] [llvm] r132434 - /llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp In-Reply-To: References: <20110601231653.76ACC2A6C12C@llvm.org> Message-ID: On Wed, Jun 1, 2011 at 4:45 PM, Chad Rosier wrote: > > On Jun 1, 2011, at 4:16 PM, Eli Friedman wrote: > >> Author: efriedma >> Date: Wed Jun ?1 18:16:53 2011 >> New Revision: 132434 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132434&view=rev >> Log: >> In MemoryDependenceAnalysis::getNonLocalPointerDepFromBB, if a given block is is deemed unanalyzable (and we execute one of the "goto PredTranslationFailure" statements), make sure we don't put information about the predecessors of that block into the returned data structures; this can lead to, among other things, extraneous results (which will confuse passes using memdep). ?Fixes an assert in GVN compiling ruby. Part of rdar://problem/9521954 . > > Don't you mean Yes, I do. Thanks :) -Eli From jstaszak at apple.com Wed Jun 1 19:03:27 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Wed, 01 Jun 2011 17:03:27 -0700 Subject: [llvm-commits] Branch Probability Message-ID: <7028D329-7189-4511-8A9C-2AC55A2CD79B@apple.com> I just found a small bug. Fixed version attached. -------------- next part -------------- A non-text attachment was scrubbed... Name: kuba_bp3.patch Type: application/octet-stream Size: 14463 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110601/58f47c77/attachment.obj -------------- next part -------------- -- Jakub Staszak From eli.friedman at gmail.com Wed Jun 1 19:08:52 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 02 Jun 2011 00:08:52 -0000 Subject: [llvm-commits] [llvm] r132442 - in /llvm/trunk: lib/Analysis/MemoryDependenceAnalysis.cpp test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll Message-ID: <20110602000852.72FC32A6C12C@llvm.org> Author: efriedma Date: Wed Jun 1 19:08:52 2011 New Revision: 132442 URL: http://llvm.org/viewvc/llvm-project?rev=132442&view=rev Log: When marking a block as being unanalyzable, use "Clobber" on the terminator instead of the first instruction in the block. This is a bit of a hack; "Clobber" isn't really the right marking in the first place. memdep doesn't really have any way of properly expressing "unanalyzable" at the moment. Using it on the terminator is much less ambiguous than using it on an arbitrary instruction, though. In the given testcase, the "Clobber" was pointing to a load, and GVN was incorrectly assuming that meant that the "Clobber" load overlapped the load being analyzed (when they are actually unrelated). The included testcase tests both this commit and r132434. Part two of rdar://9429882. (r132434 was mislabeled.) Added: llvm/trunk/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=132442&r1=132441&r2=132442&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Wed Jun 1 19:08:52 2011 @@ -1155,8 +1155,8 @@ assert(I->getResult().isNonLocal() && "Should only be here with transparent block"); - I->setResult(MemDepResult::getClobber(BB->begin())); - ReverseNonLocalPtrDeps[BB->begin()].insert(CacheKey); + I->setResult(MemDepResult::getClobber(BB->getTerminator())); + ReverseNonLocalPtrDeps[BB->getTerminator()].insert(CacheKey); Result.push_back(NonLocalDepResult(I->getBB(), I->getResult(), Pointer.getAddr())); break; Added: llvm/trunk/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll?rev=132442&view=auto ============================================================================== --- llvm/trunk/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll (added) +++ llvm/trunk/test/Transforms/GVN/2011-06-01-NonLocalMemdepMiscompile.ll Wed Jun 1 19:08:52 2011 @@ -0,0 +1,61 @@ +; RUN: opt < %s -basicaa -gvn -S | FileCheck %s +; This test is checking that (a) this doesn't crash, and (b) we don't +; conclude the value of %tmp17 is available in bb1.bb15_crit_edge. +; rdar://9429882 + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.7.0" + +define i1 @rb_intern() nounwind ssp { +; CHECK: @rb_intern + +bb: + %tmp = alloca i8*, align 8 + store i8* null, i8** %tmp, align 8 + store i8 undef, i8* null, align 536870912 + br label %bb1 + +bb1: + br i1 undef, label %bb3, label %bb15 + +; CHECK: bb1: +; CHECK: %tmp16 = phi i8* [ getelementptr (i8* null, i64 undef), %bb10 ], [ null, %bb ] + +; CHECK: bb1.bb15_crit_edge: +; CHECK: %tmp17.pre = load i8* %tmp16, align 1 + +bb3: + call void @isalnum() + br i1 undef, label %bb10, label %bb5 + +bb5: + br i1 undef, label %bb10, label %bb6 + +bb6: + %tmp7 = load i8** %tmp, align 8 + %tmp8 = load i8* %tmp7, align 1 + %tmp9 = zext i8 %tmp8 to i64 + br i1 undef, label %bb15, label %bb10 + +bb10: + %tmp11 = load i8** %tmp, align 8 + %tmp12 = load i8* %tmp11, align 1 + %tmp13 = zext i8 %tmp12 to i64 + %tmp14 = getelementptr inbounds i8* null, i64 undef + store i8* %tmp14, i8** %tmp, align 8 + br label %bb1 + +bb15: + %tmp16 = load i8** %tmp, align 8 + %tmp17 = load i8* %tmp16, align 1 + %tmp18 = icmp eq i8 %tmp17, 0 + br label %bb19 + +; CHECK: bb15: +; CHECK: %tmp17 = phi i8 [ %tmp17.pre, %bb1.bb15_crit_edge ], [ %tmp8, %bb6 ] + +bb19: ; preds = %bb15 + ret i1 %tmp18 +} + +declare void @isalnum() nounwind inlinehint ssp From ahatanak at gmail.com Wed Jun 1 19:24:44 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 02 Jun 2011 00:24:44 -0000 Subject: [llvm-commits] [llvm] r132444 - in /llvm/trunk/lib/Target/Mips: MipsFrameLowering.cpp MipsISelLowering.cpp MipsISelLowering.h Message-ID: <20110602002444.B35EB2A6C12C@llvm.org> Author: ahatanak Date: Wed Jun 1 19:24:44 2011 New Revision: 132444 URL: http://llvm.org/viewvc/llvm-project?rev=132444&view=rev Log: Custom-lower FRAMEADDR. Patch by Sasa Stankovic. Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.h Modified: llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp?rev=132444&r1=132443&r2=132444&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsFrameLowering.cpp Wed Jun 1 19:24:44 2011 @@ -84,7 +84,8 @@ // if frame pointer elimination is disabled. bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects(); + return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects() + || MFI->isFrameAddressTaken(); } bool MipsFrameLowering::targetHandlesStackFrameRounding() const { Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=132444&r1=132443&r2=132444&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Jun 1 19:24:44 2011 @@ -523,6 +523,7 @@ case ISD::SELECT: return LowerSELECT(Op, DAG); case ISD::VASTART: return LowerVASTART(Op, DAG); case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); + case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); } return SDValue(); } @@ -1551,6 +1552,19 @@ return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle()); } +SDValue MipsTargetLowering:: +LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { + unsigned Depth = cast(Op.getOperand(0))->getZExtValue(); + assert((Depth == 0) && "Frame address can only be determined for current frame."); + + MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); + MFI->setFrameAddressIsTaken(true); + EVT VT = Op.getValueType(); + DebugLoc dl = Op.getDebugLoc(); + SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Mips::FP, VT); + return FrameAddr; +} + //===----------------------------------------------------------------------===// // Calling Convention Implementation //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=132444&r1=132443&r2=132444&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Wed Jun 1 19:24:44 2011 @@ -125,6 +125,7 @@ SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const; virtual SDValue LowerFormalArguments(SDValue Chain, From ahatanak at gmail.com Wed Jun 1 19:25:53 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 02 Jun 2011 00:25:53 -0000 Subject: [llvm-commits] [llvm] r132445 - /llvm/trunk/test/CodeGen/Mips/frame-address.ll Message-ID: <20110602002553.D8C602A6C12C@llvm.org> Author: ahatanak Date: Wed Jun 1 19:25:53 2011 New Revision: 132445 URL: http://llvm.org/viewvc/llvm-project?rev=132445&view=rev Log: Test case for r132444. Added: llvm/trunk/test/CodeGen/Mips/frame-address.ll Added: llvm/trunk/test/CodeGen/Mips/frame-address.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/frame-address.ll?rev=132445&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Mips/frame-address.ll (added) +++ llvm/trunk/test/CodeGen/Mips/frame-address.ll Wed Jun 1 19:25:53 2011 @@ -0,0 +1,12 @@ +; RUN: llc -march=mipsel -mcpu=mips2 < %s | FileCheck %s + +declare i8* @llvm.frameaddress(i32) nounwind readnone + +define i8* @f() nounwind { +entry: + %0 = call i8* @llvm.frameaddress(i32 0) + ret i8* %0 + +; CHECK: addu $fp, $sp, $zero +; CHECK: addu $2, $zero, $fp +} From grosbach at apple.com Wed Jun 1 19:44:00 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 01 Jun 2011 17:44:00 -0700 Subject: [llvm-commits] [llvm] r132317 - in /llvm/trunk: include/llvm/Target/ lib/MC/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/PowerPC/InstPrinter/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/InstPrinter/ lib/Target/XCore/ test/CodeGen/X86/ utils/TableGen/ In-Reply-To: <20110530202016.00B822A6C12C@llvm.org> References: <20110530202016.00B822A6C12C@llvm.org> Message-ID: <61D85BF4-C4C3-405E-8A77-BA5EB5159EED@apple.com> Rafael, This patch appears to assume that all backends format register names as "%" in their assembly, or at least can parse registers named as such. That's very much not true. The AsmStreamer shouldn't be hard-coding this sort of target specific logic. $ cat t.s .cfi_def_cfa %r0, 1 llvm-mc -triple armv7-apple-darwin10 t.s .section __TEXT,__text,regular,pure_instructions Assertion failed: (Tok.is(AsmToken::Identifier) && "Token is not an Identifier"), function TryParseRegister, file /Users/grosbaj/sources/llvm-a64/lib/Target/ARM/AsmParser/ARMAsmParser.cpp, line 909. 0 llvm-mc 0x0000000100f1a275 PrintStackTrace(void*) + 53 1 llvm-mc 0x0000000100f1a83b SignalHandler(int) + 379 2 libSystem.B.dylib 0x00007fff81abb66a _sigtramp + 26 3 libSystem.B.dylib 0x00007fff5fbfe750 _sigtramp + 3725865216 4 llvm-mc 0x000000010004308b raise + 27 5 llvm-mc 0x000000010004314a abort + 26 6 llvm-mc 0x0000000100043124 __assert_rtn + 132 7 llvm-mc 0x0000000100353750 (anonymous namespace)::ARMAsmParser::TryParseRegister() + 160 8 llvm-mc 0x000000010033ca21 (anonymous namespace)::ARMAsmParser::ParseRegister(unsigned int&, llvm::SMLoc&, llvm::SMLoc&) + 33 9 llvm-mc 0x00000001008e1fb4 (anonymous namespace)::GenericAsmParser::ParseRegisterOrRegisterNumber(long long&, llvm::SMLoc) + 132 10 llvm-mc 0x00000001008e321b (anonymous namespace)::GenericAsmParser::ParseDirectiveCFIDefCfa(llvm::StringRef, llvm::SMLoc) + 91 11 llvm-mc 0x00000001008e31ac bool llvm::MCAsmParserExtension::HandleDirective<(anonymous namespace)::GenericAsmParser, &((anonymous namespace)::GenericAsmParser::ParseDirectiveCFIDefCfa(llvm::StringRef, llvm::SMLoc))>(llvm::MCAsmParserExtension*, llvm::StringRef, llvm::SMLoc) + 172 12 llvm-mc 0x00000001008d7c4c (anonymous namespace)::AsmParser::ParseStatement() + 10652 13 llvm-mc 0x00000001008d23cc (anonymous namespace)::AsmParser::Run(bool, bool) + 236 14 llvm-mc 0x000000010004ce0a AssembleInput(char const*) + 3786 15 llvm-mc 0x000000010004ac59 main + 313 16 llvm-mc 0x0000000100045994 start + 52 17 llvm-mc 0x0000000000000004 start + 4294682276 Stack dump: 0. Program arguments: /Users/grosbaj/sources/build-llvm-a64/Debug+Asserts/bin/llvm-mc -triple armv7-apple-darwin10 t.s Illegal instruction -Jim On May 30, 2011, at 1:20 PM, Rafael Espindola wrote: > Author: rafael > Date: Mon May 30 15:20:15 2011 > New Revision: 132317 > > URL: http://llvm.org/viewvc/llvm-project?rev=132317&view=rev > Log: > Use the dwarf->llvm mapping to print register names in the cfi > directives. > > Fixes PR9826. > > Modified: > llvm/trunk/include/llvm/Target/TargetAsmInfo.h > llvm/trunk/include/llvm/Target/TargetRegisterInfo.h > llvm/trunk/lib/MC/MCAsmStreamer.cpp > llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp > llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h > llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp > llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h > llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp > llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h > llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp > llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h > llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp > llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h > llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp > llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h > llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp > llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h > llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h > llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp > llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h > llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp > llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp > llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h > llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp > llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h > llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp > llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h > llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp > llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h > llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp > llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h > llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp > llvm/trunk/lib/Target/X86/X86RegisterInfo.h > llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp > llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h > llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll > llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll > llvm/trunk/test/CodeGen/X86/empty-functions.ll > llvm/trunk/test/CodeGen/X86/pr9743.ll > llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp > > Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original) > +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Mon May 30 15:20:15 2011 > @@ -95,6 +95,10 @@ > return TRI->getDwarfRegNum(RegNum, isEH); > } > > + int getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const { > + return TRI->getLLVMRegNum(DwarfRegNum, isEH); > + } > + > int getSEHRegNum(unsigned RegNum) const { > return TRI->getSEHRegNum(RegNum); > } > > Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) > +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Mon May 30 15:20:15 2011 > @@ -802,6 +802,8 @@ > /// debugging info. > virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0; > > + virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0; > + > /// getFrameRegister - This method should return the register used as a base > /// for values allocated in the current stack frame. > virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0; > > Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) > +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Mon May 30 15:20:15 2011 > @@ -54,6 +54,8 @@ > > bool needsSet(const MCExpr *Value); > > + void EmitRegisterName(int64_t Register); > + > public: > MCAsmStreamer(MCContext &Context, formatted_raw_ostream &os, > bool isVerboseAsm, bool useLoc, bool useCFI, > @@ -819,13 +821,25 @@ > EmitEOL(); > } > > +void MCAsmStreamer::EmitRegisterName(int64_t Register) { > + if (InstPrinter) { > + const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo(); > + unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true); > + OS << '%' << InstPrinter->getRegName(LLVMRegister); > + } else { > + OS << Register; > + } > +} > + > void MCAsmStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) { > MCStreamer::EmitCFIDefCfa(Register, Offset); > > if (!UseCFI) > return; > > - OS << "\t.cfi_def_cfa " << Register << ", " << Offset; > + OS << "\t.cfi_def_cfa "; > + EmitRegisterName(Register); > + OS << ", " << Offset; > EmitEOL(); > } > > @@ -845,7 +859,8 @@ > if (!UseCFI) > return; > > - OS << "\t.cfi_def_cfa_register " << Register; > + OS << "\t.cfi_def_cfa_register "; > + EmitRegisterName(Register); > EmitEOL(); > } > > @@ -855,7 +870,9 @@ > if (!UseCFI) > return; > > - OS << "\t.cfi_offset " << Register << ", " << Offset; > + OS << "\t.cfi_offset "; > + EmitRegisterName(Register); > + OS << ", " << Offset; > EmitEOL(); > } > > @@ -906,7 +923,8 @@ > if (!UseCFI) > return; > > - OS << "\t.cfi_same_value " << Register; > + OS << "\t.cfi_same_value "; > + EmitRegisterName(Register); > EmitEOL(); > } > > @@ -916,7 +934,9 @@ > if (!UseCFI) > return; > > - OS << "\t.cfi_rel_offset " << Register << ", " << Offset; > + OS << "\t.cfi_rel_offset "; > + EmitRegisterName(Register); > + OS << ", " << Offset; > EmitEOL(); > } > > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -684,6 +684,10 @@ > return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); > } > > +int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { > + return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); > +} > + > unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg, > const MachineFunction &MF) const { > switch (Reg) { > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Mon May 30 15:20:15 2011 > @@ -172,6 +172,7 @@ > unsigned getEHHandlerRegister() const; > > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > > bool isLowRegister(unsigned Reg) const; > > > Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -199,6 +199,11 @@ > return -1; > } > > +int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const { > + llvm_unreachable("What is the dwarf register number"); > + return -1; > +} > + > #include "AlphaGenRegisterInfo.inc" > > std::string AlphaRegisterInfo::getPrettyName(unsigned reg) > > Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h Mon May 30 15:20:15 2011 > @@ -48,6 +48,7 @@ > unsigned getEHHandlerRegister() const; > > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > > static std::string getPrettyName(unsigned reg); > }; > > Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -351,5 +351,11 @@ > return -1; > } > > +int BlackfinRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, > + bool isEH) const { > + llvm_unreachable("What is the dwarf register number"); > + return -1; > +} > + > #include "BlackfinGenRegisterInfo.inc" > > > Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h Mon May 30 15:20:15 2011 > @@ -60,6 +60,7 @@ > unsigned getEHHandlerRegister() const; > > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > > // Utility functions > void adjustRegister(MachineBasicBlock &MBB, > > Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -328,6 +328,10 @@ > return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); > } > > +int SPURegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { > + return SPUGenRegisterInfo::getLLVMRegNumFull(RegNum, 0); > +} > + > int > SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const > { > > Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h (original) > +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h Mon May 30 15:20:15 2011 > @@ -83,6 +83,7 @@ > > //! Get DWARF debugging register number > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > > //! Convert D-form load/store to X-form load/store > /*! > > Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -356,5 +356,9 @@ > return MBlazeGenRegisterInfo::getDwarfRegNumFull(RegNo,0); > } > > +int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { > + return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); > +} > + > #include "MBlazeGenRegisterInfo.inc" > > > Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h Mon May 30 15:20:15 2011 > @@ -75,6 +75,7 @@ > unsigned getEHHandlerRegister() const; > > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > }; > > } // end namespace llvm > > Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -242,4 +242,9 @@ > return 0; > } > > +int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { > + llvm_unreachable("Not implemented yet!"); > + return 0; > +} > + > #include "MSP430GenRegisterInfo.inc" > > Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h (original) > +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h Mon May 30 15:20:15 2011 > @@ -61,6 +61,7 @@ > > //! Get DWARF debugging register number > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > }; > > } // end namespace llvm > > Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -278,4 +278,8 @@ > return MipsGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); > } > > +int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { > + return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); > +} > + > #include "MipsGenRegisterInfo.inc" > > Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Mon May 30 15:20:15 2011 > @@ -63,6 +63,7 @@ > unsigned getEHHandlerRegister() const; > > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > }; > > } // end namespace llvm > > Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h Mon May 30 15:20:15 2011 > @@ -57,6 +57,9 @@ > virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const { > return PTXGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); > } > + virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const { > + return PTXGenRegisterInfo::getLLVMRegNumFull(RegNum, 0); > + } > }; // struct PTXRegisterInfo > } // namespace llvm > > > Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Mon May 30 15:20:15 2011 > @@ -26,6 +26,9 @@ > return getInstructionName(Opcode); > } > > +StringRef PPCInstPrinter::getRegName(unsigned RegNo) const { > + return getRegisterName(RegNo); > +} > > void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { > // Check for slwi/srwi mnemonics. > > Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h (original) > +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h Mon May 30 15:20:15 2011 > @@ -33,6 +33,7 @@ > return SyntaxVariant == 1; > } > > + StringRef getRegName(unsigned RegNo) const; > virtual void printInst(const MCInst *MI, raw_ostream &O); > virtual StringRef getOpcodeName(unsigned Opcode) const; > > > Modified: llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCFrameLowering.cpp Mon May 30 15:20:15 2011 > @@ -487,6 +487,14 @@ > int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); > unsigned Reg = CSI[I].getReg(); > if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; > + > + // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just > + // subregisters of CR2. We just need to emit a move of CR2. > + if (Reg == PPC::CR2LT || Reg == PPC::CR2GT || Reg == PPC::CR2EQ) > + continue; > + if (Reg == PPC::CR2UN) > + Reg = PPC::CR2; > + > MachineLocation CSDst(MachineLocation::VirtualFP, Offset); > MachineLocation CSSrc(Reg); > Moves.push_back(MachineMove(Label, CSDst, CSSrc)); > > Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -702,4 +702,12 @@ > return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour); > } > > +int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const { > + // FIXME: Most probably dwarf numbers differs for Linux and Darwin > + unsigned Flavour = Subtarget.isPPC64() ? > + DWARFFlavour::PPC64 : DWARFFlavour::PPC32; > + > + return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour); > +} > + > #include "PPCGenRegisterInfo.inc" > > Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Mon May 30 15:20:15 2011 > @@ -68,6 +68,7 @@ > unsigned getEHHandlerRegister() const; > > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > }; > > } // end namespace llvm > > Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -130,5 +130,9 @@ > return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); > } > > +int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { > + return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); > +} > + > #include "SparcGenRegisterInfo.inc" > > > Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Mon May 30 15:20:15 2011 > @@ -52,6 +52,7 @@ > unsigned getEHHandlerRegister() const; > > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > }; > > } // end namespace llvm > > Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -139,4 +139,10 @@ > return -1; > } > > +int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { > + assert(0 && "What is the dwarf register number"); > + return -1; > +} > + > + > #include "SystemZGenRegisterInfo.inc" > > Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h Mon May 30 15:20:15 2011 > @@ -54,6 +54,7 @@ > unsigned getEHHandlerRegister() const; > > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > }; > > } // end namespace llvm > > Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Mon May 30 15:20:15 2011 > @@ -41,6 +41,10 @@ > &TM.getSubtarget())); > } > > +StringRef X86ATTInstPrinter::getRegName(unsigned RegNo) const { > + return getRegisterName(RegNo); > +} > + > void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { > // Try to print any aliases first. > if (!printAliasInstr(MI, OS)) > > Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original) > +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Mon May 30 15:20:15 2011 > @@ -26,6 +26,7 @@ > public: > X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI); > > + StringRef getRegName(unsigned RegNo) const; > virtual void printInst(const MCInst *MI, raw_ostream &OS); > virtual StringRef getOpcodeName(unsigned Opcode) const; > > > Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Mon May 30 15:20:15 2011 > @@ -29,6 +29,10 @@ > #define GET_INSTRUCTION_NAME > #include "X86GenAsmWriter1.inc" > > +StringRef X86IntelInstPrinter::getRegName(unsigned RegNo) const { > + return getRegisterName(RegNo); > +} > + > void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { > printInstruction(MI, OS); > > > Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h (original) > +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h Mon May 30 15:20:15 2011 > @@ -27,6 +27,7 @@ > X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) > : MCInstPrinter(MAI) {} > > + StringRef getRegName(unsigned RegNo) const; > virtual void printInst(const MCInst *MI, raw_ostream &OS); > virtual StringRef getOpcodeName(unsigned Opcode) const; > > > Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -73,29 +73,40 @@ > } > } > > -/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF > -/// specific numbering, used in debug info and exception tables. > -int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const { > - const X86Subtarget *Subtarget = &TM.getSubtarget(); > - unsigned Flavour = DWARFFlavour::X86_64; > - > +static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) { > if (!Subtarget->is64Bit()) { > if (Subtarget->isTargetDarwin()) { > if (isEH) > - Flavour = DWARFFlavour::X86_32_DarwinEH; > + return DWARFFlavour::X86_32_DarwinEH; > else > - Flavour = DWARFFlavour::X86_32_Generic; > + return DWARFFlavour::X86_32_Generic; > } else if (Subtarget->isTargetCygMing()) { > // Unsupported by now, just quick fallback > - Flavour = DWARFFlavour::X86_32_Generic; > + return DWARFFlavour::X86_32_Generic; > } else { > - Flavour = DWARFFlavour::X86_32_Generic; > + return DWARFFlavour::X86_32_Generic; > } > } > + return DWARFFlavour::X86_64; > +} > + > +/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF > +/// specific numbering, used in debug info and exception tables. > +int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const { > + const X86Subtarget *Subtarget = &TM.getSubtarget(); > + unsigned Flavour = getFlavour(Subtarget, isEH); > > return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour); > } > > +/// getLLVMRegNum - This function maps DWARF register numbers to LLVM register. > +int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { > + const X86Subtarget *Subtarget = &TM.getSubtarget(); > + unsigned Flavour = getFlavour(Subtarget, isEH); > + > + return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour); > +} > + > int > X86RegisterInfo::getSEHRegNum(unsigned i) const { > int reg = getX86RegNum(i); > > Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original) > +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Mon May 30 15:20:15 2011 > @@ -80,6 +80,7 @@ > /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum > /// (created by TableGen) for target dependencies. > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > > // FIXME: This should be tablegen'd like getDwarfRegNum is > int getSEHRegNum(unsigned i) const; > > Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Mon May 30 15:20:15 2011 > @@ -315,6 +315,10 @@ > return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0); > } > > +int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const { > + return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0); > +} > + > unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const { > const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); > > > Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h (original) > +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Mon May 30 15:20:15 2011 > @@ -75,6 +75,7 @@ > > //! Get DWARF debugging register number > int getDwarfRegNum(unsigned RegNum, bool isEH) const; > + int getLLVMRegNum(unsigned RegNum, bool isEH) const; > }; > > } // end namespace llvm > > Modified: llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN32.ll Mon May 30 15:20:15 2011 > @@ -1,5 +1,5 @@ > ; Check that eh_return & unwind_init were properly lowered > -; RUN: llc < %s | grep %ebp | count 7 > +; RUN: llc < %s | grep %ebp | count 9 > ; RUN: llc < %s | grep %ecx | count 5 > > target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" > > Modified: llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2008-08-31-EH_RETURN64.ll Mon May 30 15:20:15 2011 > @@ -1,5 +1,5 @@ > ; Check that eh_return & unwind_init were properly lowered > -; RUN: llc < %s | grep %rbp | count 5 > +; RUN: llc < %s | grep %rbp | count 7 > ; RUN: llc < %s | grep %rcx | count 3 > > target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128" > > Modified: llvm/trunk/test/CodeGen/X86/empty-functions.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/empty-functions.ll?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/empty-functions.ll (original) > +++ llvm/trunk/test/CodeGen/X86/empty-functions.ll Mon May 30 15:20:15 2011 > @@ -20,10 +20,10 @@ > ; CHECK-FP-NEXT: : > ; CHECK-FP-NEXT: .cfi_def_cfa_offset 16 > ; CHECK-FP-NEXT: : > -; CHECK-FP-NEXT: .cfi_offset 6, -16 > +; CHECK-FP-NEXT: .cfi_offset %rbp, -16 > ; CHECK-FP-NEXT: movq %rsp, %rbp > ; CHECK-FP-NEXT: : > -; CHECK-FP-NEXT: .cfi_def_cfa_register 6 > +; CHECK-FP-NEXT: .cfi_def_cfa_register %rbp > ; CHECK-FP-NEXT: nop > ; CHECK-FP-NEXT: : > ; CHECK-FP-NEXT: .cfi_endproc > > Modified: llvm/trunk/test/CodeGen/X86/pr9743.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr9743.ll?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/pr9743.ll (original) > +++ llvm/trunk/test/CodeGen/X86/pr9743.ll Mon May 30 15:20:15 2011 > @@ -9,9 +9,9 @@ > ; CHECK-NEXT: : > ; CHECK-NEXT: .cfi_def_cfa_offset 16 > ; CHECK-NEXT: : > -; CHECK-NEXT: .cfi_offset 6, -16 > +; CHECK-NEXT: .cfi_offset %rbp, -16 > ; CHECK-NEXT: movq %rsp, %rbp > ; CHECK-NEXT: : > -; CHECK-NEXT: .cfi_def_cfa_register 6 > +; CHECK-NEXT: .cfi_def_cfa_register %rbp > ; CHECK-NEXT: popq %rbp > ; CHECK-NEXT: ret > > Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=132317&r1=132316&r2=132317&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Mon May 30 15:20:15 2011 > @@ -80,6 +80,8 @@ > << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" > << " virtual int getDwarfRegNumFull(unsigned RegNum, " > << "unsigned Flavour) const;\n" > + << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " > + << "unsigned Flavour) const;\n" > << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" > << " virtual bool needsStackRealignment(const MachineFunction &) const\n" > << " { return false; }\n" > @@ -989,6 +991,33 @@ > for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) > I->second.push_back(-1); > > + // Emit reverse information about the dwarf register numbers. > + OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, " > + << "unsigned Flavour) const {\n" > + << " switch (Flavour) {\n" > + << " default:\n" > + << " assert(0 && \"Unknown DWARF flavour\");\n" > + << " return -1;\n"; > + > + for (unsigned i = 0, e = maxLength; i != e; ++i) { > + OS << " case " << i << ":\n" > + << " switch (DwarfRegNum) {\n" > + << " default:\n" > + << " assert(0 && \"Invalid DwarfRegNum\");\n" > + << " return -1;\n"; > + > + for (DwarfRegNumsMapTy::iterator > + I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { > + int DwarfRegNo = I->second[i]; > + if (DwarfRegNo >= 0) > + OS << " case " << DwarfRegNo << ":\n" > + << " return " << getQualifiedName(I->first) << ";\n"; > + } > + OS << " };\n"; > + } > + > + OS << " };\n}\n\n"; > + > for (unsigned i = 0, e = Regs.size(); i != e; ++i) { > Record *Reg = Regs[i].TheDef; > const RecordVal *V = Reg->getValue("DwarfAlias"); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From ahatanak at gmail.com Wed Jun 1 20:03:14 2011 From: ahatanak at gmail.com (Akira Hatanaka) Date: Thu, 02 Jun 2011 01:03:14 -0000 Subject: [llvm-commits] [llvm] r132448 - in /llvm/trunk: lib/Target/Mips/MipsISelDAGToDAG.cpp test/CodeGen/Mips/largeimmprinting.ll test/CodeGen/Mips/o32_cc_byval.ll Message-ID: <20110602010314.830CD2A6C12C@llvm.org> Author: ahatanak Date: Wed Jun 1 20:03:14 2011 New Revision: 132448 URL: http://llvm.org/viewvc/llvm-project?rev=132448&view=rev Log: Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic. Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=132448&r1=132447&r2=132448&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Wed Jun 1 20:03:14 2011 @@ -135,24 +135,25 @@ } } - // Operand is a result from an ADD. - if (Addr.getOpcode() == ISD::ADD) { - if (ConstantSDNode *CN = dyn_cast(Addr.getOperand(1))) { - if (isInt<16>(CN->getSExtValue())) { - - // If the first operand is a FI, get the TargetFI Node - if (FrameIndexSDNode *FIN = dyn_cast - (Addr.getOperand(0))) { - Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); - } else { - Base = Addr.getOperand(0); - } + // Addresses of the form FI+const or FI|const + if (CurDAG->isBaseWithConstantOffset(Addr)) { + ConstantSDNode *CN = dyn_cast(Addr.getOperand(1)); + if (isInt<16>(CN->getSExtValue())) { + + // If the first operand is a FI, get the TargetFI Node + if (FrameIndexSDNode *FIN = dyn_cast + (Addr.getOperand(0))) + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32); + else + Base = Addr.getOperand(0); - Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); - return true; - } + Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32); + return true; } + } + // Operand is a result from an ADD. + if (Addr.getOpcode() == ISD::ADD) { // When loading from constant pools, load the lower address part in // the instruction itself. Example, instead of: // lui $2, %hi($CPI1_0) Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=132448&r1=132447&r2=132448&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original) +++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Wed Jun 1 20:03:14 2011 @@ -8,7 +8,7 @@ entry: ; CHECK: lui $at, 65534 ; CHECK: addu $at, $sp, $at -; CHECK: addiu $sp, $at, -24 +; CHECK: addiu $sp, $at, -16 ; CHECK: .cprestore 65536 %agg.tmp = alloca %struct.S1, align 1 Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=132448&r1=132447&r2=132448&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original) +++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Wed Jun 1 20:03:14 2011 @@ -10,18 +10,16 @@ define void @f1() nounwind { entry: -; CHECK: lw $[[R0:[0-9]+]], %got(f1.s1)($gp) -; CHECK: addiu $[[R1:[0-9]+]], $sp, 16 -; CHECK: addiu $[[R0:[0-9]+]], $[[R0]], %lo(f1.s1) +; CHECK: lw $[[R1:[0-9]+]], %got(f1.s1)($gp) +; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1) ; CHECK: lw $[[R2:[0-9]+]], 8($[[R0]]) +; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) ; CHECK: lw $[[R3:[0-9]+]], 16($[[R0]]) ; CHECK: lw $[[R4:[0-9]+]], 20($[[R0]]) ; CHECK: lw $[[R5:[0-9]+]], 24($[[R0]]) ; CHECK: lw $[[R6:[0-9]+]], 28($[[R0]]) -; CHECK: lw $[[R7:[0-9]+]], 12($[[R0]]) -; CHECK: ori $[[R8:[0-9]+]], $[[R1]], 4 ; CHECK: sw $[[R2]], 16($sp) -; CHECK: sw $[[R7]], 0($[[R8]]) +; CHECK: sw $[[R7]], 20($sp) ; CHECK: sw $[[R3]], 24($sp) ; CHECK: sw $[[R4]], 28($sp) ; CHECK: sw $[[R5]], 32($sp) @@ -46,14 +44,11 @@ define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind { entry: ; CHECK: addiu $sp, $sp, -56 -; CHECK: addiu $[[R0:[0-9]+]], $sp, 64 -; CHECK: ori $[[R1:[0-9]+]], $[[R0]], 4 -; CHECK: ori $[[R0:[0-9]+]], $[[R0]], 2 ; CHECK: sw $6, 64($sp) -; CHECK: sw $7, 0($[[R1]]) +; CHECK: sw $7, 68($sp) ; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp) -; CHECK: lw $[[R2:[0-9]+]], 0($[[R1]]) -; CHECK: lh $[[R1:[0-9]+]], 0($[[R0]]) +; CHECK: lw $[[R2:[0-9]+]], 68($sp) +; CHECK: lh $[[R1:[0-9]+]], 66($sp) ; CHECK: lb $[[R0:[0-9]+]], 64($sp) ; CHECK: lw $[[R3:[0-9]+]], 72($sp) ; CHECK: lw $[[R4:[0-9]+]], 76($sp) @@ -86,10 +81,8 @@ define void @f3(%struct.S2* nocapture byval %s2) nounwind { entry: ; CHECK: addiu $sp, $sp, -56 -; CHECK: addiu $[[R0:[0-9]+]], $sp, 56 -; CHECK: ori $[[R0:[0-9]+]], $[[R0]], 4 ; CHECK: sw $4, 56($sp) -; CHECK: sw $5, 0($[[R0]]) +; CHECK: sw $5, 60($sp) ; CHECK: sw $6, 64($sp) ; CHECK: sw $7, 68($sp) ; CHECK: lw $[[R0:[0-9]+]], 68($sp) @@ -107,14 +100,12 @@ define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind { entry: ; CHECK: addiu $sp, $sp, -56 -; CHECK: addiu $[[R0:[0-9]+]], $sp, 64 -; CHECK: ori $[[R2:[0-9]+]], $[[R0]], 4 ; CHECK: sw $5, 60($sp) ; CHECK: sw $6, 64($sp) -; CHECK: sw $7, 0($[[R2]]) +; CHECK: sw $7, 68($sp) ; CHECK: lw $[[R1:[0-9]+]], 88($sp) ; CHECK: lb $[[R0:[0-9]+]], 60($sp) -; CHECK: lw $4, 0($[[R2]]) +; CHECK: lw $4, 68($sp) ; CHECK: sw $[[R1]], 24($sp) ; CHECK: sw $[[R0]], 32($sp) From rafael.espindola at gmail.com Wed Jun 1 20:48:07 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Wed, 01 Jun 2011 21:48:07 -0400 Subject: [llvm-commits] [llvm] r132317 - in /llvm/trunk: include/llvm/Target/ lib/MC/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/PowerPC/InstPrinter/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/InstPrinter/ lib/Target/XCore/ test/CodeGen/X86/ utils/TableGen/ In-Reply-To: <61D85BF4-C4C3-405E-8A77-BA5EB5159EED@apple.com> References: <20110530202016.00B822A6C12C@llvm.org> <61D85BF4-C4C3-405E-8A77-BA5EB5159EED@apple.com> Message-ID: <4DE6EBD7.7080409@gmail.com> On 11-06-01 8:44 PM, Jim Grosbach wrote: > Rafael, > > This patch appears to assume that all backends format register names as "%" in their assembly, or at least can parse registers named as such. That's very much not true. The AsmStreamer shouldn't be hard-coding this sort of target specific logic. > > $ cat t.s > .cfi_def_cfa %r0, 1 > > llvm-mc -triple armv7-apple-darwin10 t.s > .section __TEXT,__text,regular,pure_instructions > Assertion failed: (Tok.is(AsmToken::Identifier)&& "Token is not an Identifier"), function TryParseRegister, file /Users/grosbaj/sources/llvm-a64/lib/Target/ARM/AsmParser/ARMAsmParser.cpp, line 909. > 0 llvm-mc 0x0000000100f1a275 PrintStackTrace(void*) + 53 > 1 llvm-mc 0x0000000100f1a83b SignalHandler(int) + 379 > 2 libSystem.B.dylib 0x00007fff81abb66a _sigtramp + 26 > 3 libSystem.B.dylib 0x00007fff5fbfe750 _sigtramp + 3725865216 > 4 llvm-mc 0x000000010004308b raise + 27 > 5 llvm-mc 0x000000010004314a abort + 26 > 6 llvm-mc 0x0000000100043124 __assert_rtn + 132 > 7 llvm-mc 0x0000000100353750 (anonymous namespace)::ARMAsmParser::TryParseRegister() + 160 > 8 llvm-mc 0x000000010033ca21 (anonymous namespace)::ARMAsmParser::ParseRegister(unsigned int&, llvm::SMLoc&, llvm::SMLoc&) + 33 > 9 llvm-mc 0x00000001008e1fb4 (anonymous namespace)::GenericAsmParser::ParseRegisterOrRegisterNumber(long long&, llvm::SMLoc) + 132 > 10 llvm-mc 0x00000001008e321b (anonymous namespace)::GenericAsmParser::ParseDirectiveCFIDefCfa(llvm::StringRef, llvm::SMLoc) + 91 > 11 llvm-mc 0x00000001008e31ac bool llvm::MCAsmParserExtension::HandleDirective<(anonymous namespace)::GenericAsmParser,&((anonymous namespace)::GenericAsmParser::ParseDirectiveCFIDefCfa(llvm::StringRef, llvm::SMLoc))>(llvm::MCAsmParserExtension*, llvm::StringRef, llvm::SMLoc) + 172 > 12 llvm-mc 0x00000001008d7c4c (anonymous namespace)::AsmParser::ParseStatement() + 10652 > 13 llvm-mc 0x00000001008d23cc (anonymous namespace)::AsmParser::Run(bool, bool) + 236 > 14 llvm-mc 0x000000010004ce0a AssembleInput(char const*) + 3786 > 15 llvm-mc 0x000000010004ac59 main + 313 > 16 llvm-mc 0x0000000100045994 start + 52 > 17 llvm-mc 0x0000000000000004 start + 4294682276 > Stack dump: > 0. Program arguments: /Users/grosbaj/sources/build-llvm-a64/Debug+Asserts/bin/llvm-mc -triple armv7-apple-darwin10 t.s > Illegal instruction I will fix it, sorry. > -Jim > Cheers, Rafael From grosbach at apple.com Wed Jun 1 20:50:33 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 01 Jun 2011 18:50:33 -0700 Subject: [llvm-commits] [llvm] r132317 - in /llvm/trunk: include/llvm/Target/ lib/MC/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/PowerPC/InstPrinter/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/InstPrinter/ lib/Target/XCore/ test/CodeGen/X86/ utils/TableGen/ In-Reply-To: <4DE6EBD7.7080409@gmail.com> References: <20110530202016.00B822A6C12C@llvm.org> <61D85BF4-C4C3-405E-8A77-BA5EB5159EED@apple.com> <4DE6EBD7.7080409@gmail.com> Message-ID: <11453C19-643B-4C04-95B3-3E8E9814A64F@apple.com> On Jun 1, 2011, at 6:48 PM, Rafael ?vila de Esp?ndola wrote: > On 11-06-01 8:44 PM, Jim Grosbach wrote: >> Rafael, >> >> This patch appears to assume that all backends format register names as "%" in their assembly, or at least can parse registers named as such. That's very much not true. The AsmStreamer shouldn't be hard-coding this sort of target specific logic. >> > > I will fix it, sorry. No worries. Thanks! -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110601/a7947bf1/attachment.html From stoklund at 2pi.dk Wed Jun 1 21:19:35 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 02 Jun 2011 02:19:35 -0000 Subject: [llvm-commits] [llvm] r132450 - in /llvm/trunk/lib/CodeGen: CMakeLists.txt RegisterClassInfo.cpp RegisterClassInfo.h SimpleRegisterCoalescing.cpp SimpleRegisterCoalescing.h Message-ID: <20110602021935.E474E2A6C12C@llvm.org> Author: stoklund Date: Wed Jun 1 21:19:35 2011 New Revision: 132450 URL: http://llvm.org/viewvc/llvm-project?rev=132450&view=rev Log: Add a RegisterClassInfo class that lazily caches information about register classes. It provides information for each register class that cannot be determined statically, like: - The number of allocatable registers in a class after filtering out the reserved and invalid registers. - The preferred allocation order with registers that overlap callee-saved registers last. - The last callee-saved register that overlaps a given physical register. This information usually doesn't change between functions, so it is reused for compiling multiple functions when possible. The many possible combinations of reserved and callee saves registers makes it unfeasible to compute this information statically in TableGen. Use RegisterClassInfo to count available registers in various heuristics in SimpleRegisterCoalescing, making the pass run 4% faster. Added: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp llvm/trunk/lib/CodeGen/RegisterClassInfo.h Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=132450&r1=132449&r2=132450&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Wed Jun 1 21:19:35 2011 @@ -67,6 +67,7 @@ RegAllocGreedy.cpp RegAllocLinearScan.cpp RegAllocPBQP.cpp + RegisterClassInfo.cpp RegisterCoalescer.cpp RegisterScavenging.cpp RenderMachineFunction.cpp Added: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp?rev=132450&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp (added) +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Wed Jun 1 21:19:35 2011 @@ -0,0 +1,105 @@ +//===-- RegisterClassInfo.cpp - Dynamic Register Class Info ---------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the RegisterClassInfo class which provides dynamic +// information about target register classes. Callee saved and reserved +// registers depends on calling conventions and other dynamic information, so +// some things cannot be determined statically. +// +//===----------------------------------------------------------------------===// + +#include "RegisterClassInfo.h" +#include "llvm/CodeGen/MachineFunction.h" +#include "llvm/Target/TargetMachine.h" + +using namespace llvm; + +RegisterClassInfo::RegisterClassInfo() : Tag(0), TRI(0) {} + +void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { + bool Update = false; + MF = &mf; + + // Allocate new array the first time we see a new target. + if (MF->getTarget().getRegisterInfo() != TRI) { + TRI = MF->getTarget().getRegisterInfo(); + RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); + Update = true; + } + + // Does this MF have different CSRs? + const unsigned *CSR = TRI->getCalleeSavedRegs(MF); + if (CSR != CalleeSaved) { + // Build a CSRNum map. Every CSR alias gets an entry pointing to the last + // overlapping CSR. + CSRNum.reset(new uint8_t[TRI->getNumRegs()]); + for (unsigned N = 0; unsigned Reg = CSR[N]; ++N) + for (const unsigned *AS = TRI->getOverlaps(Reg); + unsigned Alias = *AS; ++AS) + CSRNum[Alias] = N + 1; // 0 means no CSR, 1 means CalleeSaved[0], ... + Update = true; + } + CalleeSaved = CSR; + + // Different reserved registers? + BitVector RR = TRI->getReservedRegs(*MF); + if (RR != Reserved) + Update = true; + Reserved = RR; + + // Invalidate cached information from previous function. + if (Update) + ++Tag; +} + +/// compute - Compute the preferred allocation order for RC with reserved +/// registers filtered out. Volatile registers come first followed by CSR +/// aliases ordered according to the CSR order specified by the target. +void RegisterClassInfo::compute(const TargetRegisterClass *RC) const { + RCInfo &RCI = RegClass[RC->getID()]; + + // Raw register count, including all reserved regs. + unsigned NumRegs = RC->getNumRegs(); + + if (!RCI.Order) + RCI.Order.reset(new unsigned[NumRegs]); + + unsigned N = 0; + SmallVector, 8> CSRAlias; + + // FIXME: Once targets reserve registers instead of removing them from the + // allocation order, we can simply use begin/end here. + TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF); + TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF); + + for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { + unsigned PhysReg = *I; + // Remove reserved registers from the allocation order. + if (Reserved.test(PhysReg)) + continue; + if (unsigned CSR = CSRNum[PhysReg]) + // PhysReg aliases a CSR, save it for later. + CSRAlias.push_back(std::make_pair(CSR, PhysReg)); + else + RCI.Order[N++] = PhysReg; + } + RCI.NumRegs = N + CSRAlias.size(); + assert (RCI.NumRegs <= NumRegs && "Allocation order larger than regclass"); + + // Sort CSR aliases acording to the CSR ordering. + if (CSRAlias.size() >= 2) + array_pod_sort(CSRAlias.begin(), CSRAlias.end()); + + for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) + RCI.Order[N++] = CSRAlias[i].second; + + // RCI is now up-to-date. + RCI.Tag = Tag; +} + Added: llvm/trunk/lib/CodeGen/RegisterClassInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.h?rev=132450&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.h (added) +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.h Wed Jun 1 21:19:35 2011 @@ -0,0 +1,102 @@ +//===-- RegisterClassInfo.h - Dynamic Register Class Info -*- C++ -*-------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the RegisterClassInfo class which provides dynamic +// information about target register classes. Callee saved and reserved +// registers depends on calling conventions and other dynamic information, so +// some things cannot be determined statically. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_REGISTERCLASSINFO_H +#define LLVM_CODEGEN_REGISTERCLASSINFO_H + +#include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/BitVector.h" +#include "llvm/ADT/OwningPtr.h" +#include "llvm/Target/TargetRegisterInfo.h" + +namespace llvm { + +class RegisterClassInfo { + struct RCInfo { + unsigned Tag; + unsigned NumRegs; + OwningArrayPtr Order; + + RCInfo() : Tag(0), NumRegs(0) {} + operator ArrayRef() const { + return ArrayRef(Order.get(), NumRegs); + } + }; + + // Brief cached information for each register class. + OwningArrayPtr RegClass; + + // Tag changes whenever cached information needs to be recomputed. An RCInfo + // entry is valid when its tag matches. + unsigned Tag; + + const MachineFunction *MF; + const TargetRegisterInfo *TRI; + + // Callee saved registers of last MF. Assumed to be valid until the next + // runOnFunction() call. + const unsigned *CalleeSaved; + + // Map register number to CalleeSaved index + 1; + OwningArrayPtr CSRNum; + + // Reserved registers in the current MF. + BitVector Reserved; + + // Compute all information about RC. + void compute(const TargetRegisterClass *RC) const; + + // Return an up-to-date RCInfo for RC. + const RCInfo &get(const TargetRegisterClass *RC) const { + const RCInfo &RCI = RegClass[RC->getID()]; + if (Tag != RCI.Tag) + compute(RC); + return RCI; + } + +public: + RegisterClassInfo(); + + /// runOnFunction - Prepare to answer questions about MF. This must be called + /// before any other methods are used. + void runOnMachineFunction(const MachineFunction &MF); + + /// getNumAllocatableRegs - Returns the number of actually allocatable + /// registers in RC in the current function. + unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { + return get(RC).NumRegs; + } + + /// getOrder - Returns the preferred allocation order for RC. The order + /// contains no reserved registers, and registers that alias callee saved + /// registers come last. + ArrayRef getOrder(const TargetRegisterClass *RC) const { + return get(RC); + } + + /// getLastCalleeSavedAlias - Returns the last callee saved register that + /// overlaps PhysReg, or 0 if Reg doesn't overlap a CSR. + unsigned getLastCalleeSavedAlias(unsigned PhysReg) const { + assert(TargetRegisterInfo::isPhysicalRegister(PhysReg)); + if (unsigned N = CSRNum[PhysReg]) + return CalleeSaved[N-1]; + return 0; + } +}; +} // end namespace llvm + +#endif + Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=132450&r1=132449&r2=132450&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Wed Jun 1 21:19:35 2011 @@ -772,7 +772,7 @@ // CodeGen/X86/phys_subreg_coalesce-3.ll needs it. if (!CP.isPartial()) { const TargetRegisterClass *RC = mri_->getRegClass(CP.getSrcReg()); - unsigned Threshold = allocatableRCRegs_[RC].count() * 2; + unsigned Threshold = RegClassInfo.getNumAllocatableRegs(RC) * 2; unsigned Length = li_->getApproximateInstructionCount(JoinVInt); if (Length > Threshold) { ++numAborts; @@ -791,7 +791,7 @@ const TargetRegisterClass *SrcRC, const TargetRegisterClass *DstRC, const TargetRegisterClass *NewRC) { - unsigned NewRCCount = allocatableRCRegs_[NewRC].count(); + unsigned NewRCCount = RegClassInfo.getNumAllocatableRegs(NewRC); // This heuristics is good enough in practice, but it's obviously not *right*. // 4 is a magic number that works well enough for x86, ARM, etc. It filter // out all but the most restrictive register classes. @@ -821,12 +821,12 @@ unsigned NewUses = SrcUses + DstUses; unsigned NewSize = SrcSize + DstSize; if (SrcRC != NewRC && SrcSize > ThresSize) { - unsigned SrcRCCount = allocatableRCRegs_[SrcRC].count(); + unsigned SrcRCCount = RegClassInfo.getNumAllocatableRegs(SrcRC); if (NewUses*SrcSize*SrcRCCount > 2*SrcUses*NewSize*NewRCCount) return false; } if (DstRC != NewRC && DstSize > ThresSize) { - unsigned DstRCCount = allocatableRCRegs_[DstRC].count(); + unsigned DstRCCount = RegClassInfo.getNumAllocatableRegs(DstRC); if (NewUses*DstSize*DstRCCount > 2*DstUses*NewSize*NewRCCount) return false; } @@ -1400,10 +1400,7 @@ if (VerifyCoalescing) mf_->verify(this, "Before register coalescing"); - for (TargetRegisterInfo::regclass_iterator I = tri_->regclass_begin(), - E = tri_->regclass_end(); I != E; ++I) - allocatableRCRegs_.insert(std::make_pair(*I, - tri_->getAllocatableSet(fn, *I))); + RegClassInfo.runOnMachineFunction(fn); // Join (coalesce) intervals if requested. if (EnableJoining) { Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=132450&r1=132449&r2=132450&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original) +++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Wed Jun 1 21:19:35 2011 @@ -17,7 +17,7 @@ #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/LiveIntervalAnalysis.h" #include "llvm/CodeGen/RegisterCoalescer.h" -#include "llvm/ADT/BitVector.h" +#include "RegisterClassInfo.h" namespace llvm { class SimpleRegisterCoalescing; @@ -47,8 +47,7 @@ LiveDebugVariables *ldv_; const MachineLoopInfo* loopInfo; AliasAnalysis *AA; - - DenseMap allocatableRCRegs_; + RegisterClassInfo RegClassInfo; /// JoinedCopies - Keep track of copies eliminated due to coalescing. /// From rafael.espindola at gmail.com Wed Jun 1 21:34:55 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 02 Jun 2011 02:34:55 -0000 Subject: [llvm-commits] [llvm] r132451 - in /llvm/trunk: include/llvm/MC/MCInstPrinter.h lib/MC/MCAsmStreamer.cpp lib/MC/MCInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp lib/Target/X86/InstPrinter/X86ATTInstPrinter.h lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp lib/Target/X86/InstPrinter/X86IntelInstPrinter.h Message-ID: <20110602023455.800242A6C12C@llvm.org> Author: rafael Date: Wed Jun 1 21:34:55 2011 New Revision: 132451 URL: http://llvm.org/viewvc/llvm-project?rev=132451&view=rev Log: Don't hardcode the %reg format in the streamer. Modified: llvm/trunk/include/llvm/MC/MCInstPrinter.h llvm/trunk/lib/MC/MCAsmStreamer.cpp llvm/trunk/lib/MC/MCInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h Modified: llvm/trunk/include/llvm/MC/MCInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInstPrinter.h (original) +++ llvm/trunk/include/llvm/MC/MCInstPrinter.h Wed Jun 1 21:34:55 2011 @@ -45,8 +45,8 @@ /// "MOV32ri") or empty if we can't resolve it. virtual StringRef getOpcodeName(unsigned Opcode) const; - /// getRegName - Return the assembler register name. - virtual StringRef getRegName(unsigned RegNo) const; + /// printRegName - Print the assembler register name. + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; unsigned getAvailableFeatures() const { return AvailableFeatures; } void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; } Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=132451&r1=132450&r2=132451&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Jun 1 21:34:55 2011 @@ -825,7 +825,7 @@ if (InstPrinter) { const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo(); unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true); - OS << '%' << InstPrinter->getRegName(LLVMRegister); + InstPrinter->printRegName(OS, LLVMRegister); } else { OS << Register; } @@ -1169,8 +1169,10 @@ } void MCAsmStreamer::EmitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset) { - OS << "\t.setfp\t" << InstPrinter->getRegName(FpReg) - << ", " << InstPrinter->getRegName(SpReg); + OS << "\t.setfp\t"; + InstPrinter->printRegName(OS, FpReg); + OS << ", "; + InstPrinter->printRegName(OS, SpReg); if (Offset) OS << ", #" << Offset; EmitEOL(); @@ -1189,10 +1191,12 @@ else OS << "\t.save\t{"; - OS << InstPrinter->getRegName(RegList[0]); + InstPrinter->printRegName(OS, RegList[0]); - for (unsigned i = 1, e = RegList.size(); i != e; ++i) - OS << ", " << InstPrinter->getRegName(RegList[i]); + for (unsigned i = 1, e = RegList.size(); i != e; ++i) { + OS << ", "; + InstPrinter->printRegName(OS, RegList[i]); + } OS << "}"; EmitEOL(); Modified: llvm/trunk/lib/MC/MCInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCInstPrinter.cpp (original) +++ llvm/trunk/lib/MC/MCInstPrinter.cpp Wed Jun 1 21:34:55 2011 @@ -20,7 +20,6 @@ return ""; } -StringRef MCInstPrinter::getRegName(unsigned RegNo) const { +void MCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { assert(0 && "Target should implement this"); - return ""; } Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Jun 1 21:34:55 2011 @@ -29,8 +29,8 @@ return getInstructionName(Opcode); } -StringRef ARMInstPrinter::getRegName(unsigned RegNo) const { - return getRegisterName(RegNo); +void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << getRegisterName(RegNo); } void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Wed Jun 1 21:34:55 2011 @@ -28,7 +28,7 @@ virtual void printInst(const MCInst *MI, raw_ostream &O); virtual StringRef getOpcodeName(unsigned Opcode) const; - virtual StringRef getRegName(unsigned RegNo) const; + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; static const char *getInstructionName(unsigned Opcode); Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Wed Jun 1 21:34:55 2011 @@ -26,8 +26,8 @@ return getInstructionName(Opcode); } -StringRef PPCInstPrinter::getRegName(unsigned RegNo) const { - return getRegisterName(RegNo); +void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << getRegisterName(RegNo); } void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h (original) +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h Wed Jun 1 21:34:55 2011 @@ -33,7 +33,7 @@ return SyntaxVariant == 1; } - StringRef getRegName(unsigned RegNo) const; + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; virtual void printInst(const MCInst *MI, raw_ostream &O); virtual StringRef getOpcodeName(unsigned Opcode) const; Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Wed Jun 1 21:34:55 2011 @@ -41,8 +41,9 @@ &TM.getSubtarget())); } -StringRef X86ATTInstPrinter::getRegName(unsigned RegNo) const { - return getRegisterName(RegNo); +void X86ATTInstPrinter::printRegName(raw_ostream &OS, + unsigned RegNo) const { + OS << '%' << getRegisterName(RegNo); } void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Wed Jun 1 21:34:55 2011 @@ -26,7 +26,7 @@ public: X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI); - StringRef getRegName(unsigned RegNo) const; + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; virtual void printInst(const MCInst *MI, raw_ostream &OS); virtual StringRef getOpcodeName(unsigned Opcode) const; Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Wed Jun 1 21:34:55 2011 @@ -29,8 +29,8 @@ #define GET_INSTRUCTION_NAME #include "X86GenAsmWriter1.inc" -StringRef X86IntelInstPrinter::getRegName(unsigned RegNo) const { - return getRegisterName(RegNo); +void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { + OS << getRegisterName(RegNo); } void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h Wed Jun 1 21:34:55 2011 @@ -27,7 +27,7 @@ X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) : MCInstPrinter(MAI) {} - StringRef getRegName(unsigned RegNo) const; + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; virtual void printInst(const MCInst *MI, raw_ostream &OS); virtual StringRef getOpcodeName(unsigned Opcode) const; From aggarwa4 at illinois.edu Wed Jun 1 23:40:10 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 02 Jun 2011 04:40:10 -0000 Subject: [llvm-commits] [poolalloc] r132453 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp Message-ID: <20110602044010.431DE2A6C12C@llvm.org> Author: aggarwa4 Date: Wed Jun 1 23:40:10 2011 New Revision: 132453 URL: http://llvm.org/viewvc/llvm-project?rev=132453&view=rev Log: Changed some function names Changed some comments For var arg functions, pass the count/metadata as the first 2 arguments. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132453&r1=132452&r2=132453&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Wed Jun 1 23:40:10 2011 @@ -56,7 +56,7 @@ bool initShadow(Module &M); bool unmapShadow(Module &M, Instruction &I); - void addTypeMapGlobal(Module &M) ; + void addTypeMap(Module &M) ; bool visitCallInst(Module &M, CallInst &CI); bool visitInvokeInst(Module &M, InvokeInst &CI); bool visitCallSite(Module &M, CallSite CS); Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132453&r1=132452&r2=132453&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Wed Jun 1 23:40:10 2011 @@ -100,7 +100,6 @@ // record argv modified |= visitMain(M, *MainF); - for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; @@ -110,7 +109,7 @@ std::string name = F.getName(); if (strncmp(name.c_str(), "tc.", 3) == 0) continue; - // check for byval arguments + // Iterate and find all byval functions bool hasByValArg = false; for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) { if (I->hasByValAttr()) { @@ -146,6 +145,7 @@ } } + // modify all byval functions while(!ByValFunctions.empty()) { Function *F = ByValFunctions.back(); ByValFunctions.pop_back(); @@ -184,7 +184,6 @@ } } - // NOTE:must visit before VAArgFunctions, to populate the map with the // correct cloned functions. while(!VAListFunctions.empty()) { @@ -206,18 +205,25 @@ modified |= visitVarArgFunction(M, *F); } - addTypeMapGlobal(M); + // add a global that contains the mapping from metadata to strings + addTypeMap(M); + + // Update stats numTypes += UsedTypes.size(); return modified; } -void TypeChecks::addTypeMapGlobal(Module &M) { - // add a global that has the metadata -> typeString mapping +// add a global that has the metadata -> typeString mapping +void TypeChecks::addTypeMap(Module &M) { + + // Declare the type of the global ArrayType* AType = ArrayType::get(VoidPtrTy, UsedTypes.size() + 1); std::vector Values; Values.reserve(UsedTypes.size() + 1); + + // Declare indices useful for creating a GEP std::vector Indices; Indices.push_back(ConstantInt::get(Int32Ty,0)); Indices.push_back(ConstantInt::get(Int32Ty,0)); @@ -235,6 +241,8 @@ Constant *C = ConstantExpr::getGetElementPtr(GV, &Indices[0], Indices.size()); Values[0] = C; + // For each used type, create a new entry. + // Also add these strings to the Values list std::map::iterator TI = UsedTypes.begin(), TE = UsedTypes.end(); for(;TI!=TE; ++TI) { std::string *type = new std::string(); @@ -260,8 +268,6 @@ ConstantArray::get(AType, &Values[0], UsedTypes.size() + 1), "typeNames" ); - - return; } void TypeChecks::visitVAListCall(Function *F) { @@ -275,7 +281,7 @@ continue; Function::arg_iterator NII = F->arg_begin(); std::vectorArgs; - Args.push_back(NII++); // toatl count + Args.push_back(NII++); // total count Args.push_back(NII++); // current count Args.push_back(NII); // MD for(unsigned i = 1 ;i < CI->getNumOperands(); i++) { @@ -289,112 +295,112 @@ } } - bool TypeChecks::visitVAListFunction(Module &M, Function &F_orig) { - if(!F_orig.hasInternalLinkage()) - return false; +bool TypeChecks::visitVAListFunction(Module &M, Function &F_orig) { + if(!F_orig.hasInternalLinkage()) + return false; - int VAListArgNum = 0; - // Check if one of the arguments is a va_list - const Type *ListType = M.getTypeByName("struct.__va_list_tag"); - if(!ListType) - return false; - const Type *ListPtrType = ListType->getPointerTo(); - Argument *VAListArg = NULL; - for (Function::arg_iterator I = F_orig.arg_begin(), E = F_orig.arg_end(); I != E; ++I) { - VAListArgNum ++; - if(I->getType() == ListPtrType) { - VAListArg = I; - break; - } + int VAListArgNum = 0; + // Check if one of the arguments is a va_list + const Type *ListType = M.getTypeByName("struct.__va_list_tag"); + if(!ListType) + return false; + const Type *ListPtrType = ListType->getPointerTo(); + Argument *VAListArg = NULL; + for (Function::arg_iterator I = F_orig.arg_begin(), E = F_orig.arg_end(); I != E; ++I) { + VAListArgNum ++; + if(I->getType() == ListPtrType) { + VAListArg = I; + break; } + } - // Clone the function to add arguments for count, MD + // Clone the function to add arguments for count, MD + + // 1. Create the new argument types vector + std::vectorTP; + TP.push_back(Int64Ty); // for count + TP.push_back(Int64Ty); // for count + TP.push_back(VoidPtrTy); // for MD + for (Function::arg_iterator I = F_orig.arg_begin(), E = F_orig.arg_end(); I != E; ++I) { + TP.push_back(I->getType()); + } + // 2. Create the new function prototype + const FunctionType *NewFTy = FunctionType::get(F_orig.getReturnType(), TP, false); + Function *F = Function::Create(NewFTy, + GlobalValue::InternalLinkage, + F_orig.getNameStr() + ".INT", + &M); + + // 3. Set the mapping for args + Function::arg_iterator NI = F->arg_begin(); + DenseMap ValueMap; + NI->setName("TotalCount"); + NI++; + NI->setName("CurrentCount"); + NI++; + NI->setName("MD"); + NI++; + for (Function::arg_iterator II = F_orig.arg_begin(); NI != F->arg_end(); ++II, ++NI) { + // Each new argument maps to the argument in the old function + // For these arguments, also copy over the attributes + ValueMap[II] = NI; + NI->setName(II->getName()); + NI->addAttr(F_orig.getAttributes().getParamAttributes(II->getArgNo() + 1)); + } + + // 4. Copy over the attributes for the function. + F->setAttributes(F->getAttributes() + .addAttr(0, F_orig.getAttributes().getRetAttributes())); + F->setAttributes(F->getAttributes().addAttr(~0, F_orig.getAttributes().getFnAttributes())); + + // 5. Perform the cloning. + SmallVector Returns; + CloneFunctionInto(F, &F_orig, ValueMap, Returns); - // 1. Create the new argument types vector - std::vectorTP; - TP.push_back(Int64Ty); // for count - TP.push_back(Int64Ty); // for count - TP.push_back(VoidPtrTy); // for MD - for (Function::arg_iterator I = F_orig.arg_begin(), E = F_orig.arg_end(); I != E; ++I) { - TP.push_back(I->getType()); - } - // 2. Create the new function prototype - const FunctionType *NewFTy = FunctionType::get(F_orig.getReturnType(), TP, false); - Function *F = Function::Create(NewFTy, - GlobalValue::InternalLinkage, - F_orig.getNameStr() + ".INT", - &M); - - // 3. Set the mapping for args - Function::arg_iterator NI = F->arg_begin(); - DenseMap ValueMap; - NI->setName("TotalCount"); - NI++; - NI->setName("CurrentCount"); - NI++; - NI->setName("MD"); - NI++; - for (Function::arg_iterator II = F_orig.arg_begin(); NI != F->arg_end(); ++II, ++NI) { - // Each new argument maps to the argument in the old function - // For these arguments, also copy over the attributes - ValueMap[II] = NI; - NI->setName(II->getName()); - NI->addAttr(F_orig.getAttributes().getParamAttributes(II->getArgNo() + 1)); - } - - // 4. Copy over the attributes for the function. - F->setAttributes(F->getAttributes() - .addAttr(0, F_orig.getAttributes().getRetAttributes())); - F->setAttributes(F->getAttributes().addAttr(~0, F_orig.getAttributes().getFnAttributes())); - - // 5. Perform the cloning. - SmallVector Returns; - CloneFunctionInto(F, &F_orig, ValueMap, Returns); - - VAListFunctionsMap[&F_orig] = F; - inst_iterator InsPt = inst_begin(F); - - // Store the information - Function::arg_iterator NII = F->arg_begin(); - AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt); - new StoreInst(NII, VASizeLoc, &*InsPt); - NII++; - AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt); - new StoreInst(NII, Counter, &*InsPt); - NII++; - AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt); - new StoreInst(NII, VAMDLoc, &*InsPt); - - // instrument va_arg to increment the counter - for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) { - for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { - VAArgInst *VI = dyn_cast(I++); - if(!VI) - continue; - Constant *One = ConstantInt::get(Int64Ty, 1); - LoadInst *OldValue = new LoadInst(Counter, "count", VI); - Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add, - OldValue, - One, - "count", - VI); - new StoreInst(NewValue, Counter, VI); - std::vector Args; - Instruction *VASize = new LoadInst(VASizeLoc, "", VI); - Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI); - Args.push_back(VASize); - Args.push_back(OldValue); - Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI->getType()))); - Args.push_back(VAMetaData); - Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *Func = M.getOrInsertFunction("compareTypeAndNumber", VoidTy, Int64Ty, Int64Ty, Int8Ty, VoidPtrTy, Int32Ty, NULL); - CallInst::Create(Func, Args.begin(), Args.end(), "", VI); - } - } + VAListFunctionsMap[&F_orig] = F; + inst_iterator InsPt = inst_begin(F); - return true; + // Store the information + Function::arg_iterator NII = F->arg_begin(); + AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt); + new StoreInst(NII, VASizeLoc, &*InsPt); + NII++; + AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt); + new StoreInst(NII, Counter, &*InsPt); + NII++; + AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt); + new StoreInst(NII, VAMDLoc, &*InsPt); + + // instrument va_arg to increment the counter + for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) { + for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { + VAArgInst *VI = dyn_cast(I++); + if(!VI) + continue; + Constant *One = ConstantInt::get(Int64Ty, 1); + LoadInst *OldValue = new LoadInst(Counter, "count", VI); + Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add, + OldValue, + One, + "count", + VI); + new StoreInst(NewValue, Counter, VI); + std::vector Args; + Instruction *VASize = new LoadInst(VASizeLoc, "", VI); + Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI); + Args.push_back(VASize); + Args.push_back(OldValue); + Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI->getType()))); + Args.push_back(VAMetaData); + Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Constant *Func = M.getOrInsertFunction("compareTypeAndNumber", VoidTy, Int64Ty, Int64Ty, Int8Ty, VoidPtrTy, Int32Ty, NULL); + CallInst::Create(Func, Args.begin(), Args.end(), "", VI); + } } + return true; +} + // Transform Variable Argument functions, by also passing // the relavant metadata info bool TypeChecks::visitVarArgFunction(Module &M, Function &F) { @@ -413,14 +419,12 @@ } // each vararg function is modified so that the first -// va_arg is the number of arguments in the va_list, +// argument is the number of arguments in the va_list, // and the second is a pointer to a metadata array, // containing type information for each of the arguments // in the va_list. -// These are read and stored on a call to va_start. -// There can be multiple calls to va_start in a given -// function, which is why these are stored in memory +// These are read and stored at the beginning of the function. // We keep a counter for the number of arguments accessed // from the va_list(Counter). It is incremented and @@ -434,20 +438,64 @@ bool TypeChecks::visitInternalVarArgFunction(Module &M, Function &F) { - inst_iterator InsPt = inst_begin(F); - + // Clone function + // 1. Create the new argument types vector + std::vector TP; + TP.push_back(Int64Ty); // for count + TP.push_back(VoidPtrTy); // for MD + for(Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I !=E; ++I) { + TP.push_back(I->getType()); + } + + // 2. Create the new function prototype + const FunctionType *NewFTy = FunctionType::get(F.getReturnType(), TP, true); + Function *NewF = Function::Create(NewFTy, + GlobalValue::InternalLinkage, + F.getNameStr() + ".mod", + &M); + + // 3. Set the mapping for the args + Function::arg_iterator NI = NewF->arg_begin(); + DenseMap ValueMap; + NI->setName("TotalCount"); + NI++; + NI->setName("MD"); + NI++; + for(Function::arg_iterator II = F.arg_begin(); NI!=NewF->arg_end(); ++II, ++NI) { + // Each new argument maps to the argument in the old function + // For each of these also copy attributes + ValueMap[II] = NI; + NI->setName(II->getName()); + NI->addAttr(F.getAttributes().getParamAttributes(II->getArgNo()+1)); + } + + // 4. Copy over attributes for the function + NewF->setAttributes(NewF->getAttributes() + .addAttr(0, F.getAttributes().getRetAttributes())); + NewF->setAttributes(NewF->getAttributes().addAttr(~0, F.getAttributes().getFnAttributes())); + + // 5. Perform the cloning + SmallVectorReturns; + CloneFunctionInto(NewF, &F, ValueMap, Returns); + + + // Store the information + inst_iterator InsPt = inst_begin(NewF); + Function::arg_iterator NII = NewF->arg_begin(); AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt); + new StoreInst(NII, VASizeLoc, &*InsPt); + NII++; AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt); - - // Modify function to add checks on every var_arg call to ensure that we - // are not accessing more arguments than we passed in. - + new StoreInst(NII, VAMDLoc, &*InsPt); // Add a counter variable to the function entry AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt); new StoreInst(ConstantInt::get(Int64Ty, 0), Counter, &*InsPt); + // Modify function to add checks on every var_arg call to ensure that we + // are not accessing more arguments than we passed in. + // Increment the counter - for (Function::iterator B = F.begin(), FE = F.end(); B != FE; ++B) { + for (Function::iterator B = NewF->begin(), FE = NewF->end(); B != FE; ++B) { for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { VAArgInst *VI = dyn_cast(I++); if(!VI) @@ -479,9 +527,9 @@ } } - // store the metadata + // visit all VAStarts and initialize the counter CallInst *VAStart = NULL; - for (Function::iterator B = F.begin(), FE = F.end(); B != FE; ++B) { + for (Function::iterator B = NewF->begin(), FE = NewF->end(); B != FE; ++B) { for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { CallInst *CI = dyn_cast(I++); if(!CI) @@ -494,28 +542,15 @@ if(CalledF->getIntrinsicID() != Intrinsic::vastart) continue; VAStart = CI; - // Modify the function to add a call to get the num of arguments - VAArgInst *VASize = new VAArgInst(CI->getOperand(1), Int64Ty, "NumArgs"); - // Modify the function to add a call to get the metadata array - VAArgInst *VAMetaData = new VAArgInst(CI->getOperand(1), VoidPtrTy, "MD"); - VASize->insertAfter(CI); - VAMetaData->insertAfter(VASize); - - // Store the metadata - StoreInst *SI1 = new StoreInst(VASize, VASizeLoc); - SI1->insertAfter(VAMetaData); - StoreInst *SI2 = new StoreInst(VAMetaData, VAMDLoc); - SI2->insertAfter(SI1); - // Reinitialize the counter StoreInst *SI3 = new StoreInst(ConstantInt::get(Int64Ty, 0), Counter); - SI3->insertAfter(SI2); + SI3->insertAfter(CI); } } assert(VAStart && "Varargs function without a call to VAStart???"); // modify calls to va list functions to pass the metadata - for (Function::iterator B = F.begin(), FE = F.end(); B != FE; ++B) { + for (Function::iterator B = NewF->begin(), FE = NewF->end(); B != FE; ++B) { for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { CallInst *CI = dyn_cast(I++); if(!CI) @@ -548,11 +583,9 @@ CallInst *CI = dyn_cast(ui++); if(!CI) continue; - if(CI->getNumOperands() - 1 <= F.arg_size()) - continue; std::vector Args; unsigned int i; - unsigned int NumVarArgs = CI->getNumOperands() -F.arg_size() - 1; + unsigned int NumVarArgs = CI->getNumOperands() - F.arg_size() - 1; Value *NumArgs = ConstantInt::get(Int32Ty, NumVarArgs); AllocaInst *AI = new AllocaInst(Int8Ty, NumArgs, "", CI); // set the metadata for the varargs in AI @@ -560,7 +593,7 @@ for(i = F.arg_size() + 1; i getNumOperands(); i++) { Value *Idx[2]; Idx[0] = ConstantInt::get(Int32Ty, j++); - // For each vararg argument, also add its type information before it + // For each vararg argument, also add its type information GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, Idx, Idx + 1, @@ -570,19 +603,17 @@ new StoreInst(C, GEP, CI); } + // As the first argument pass the number of var_arg arguments + Args.push_back(ConstantInt::get(Int64Ty, NumVarArgs)); + Args.push_back(AI); for(i = 1 ;i < CI->getNumOperands(); i++) { - // As the first vararg argument pass the number of var_arg arguments - if(i == F.arg_size() + 1) { - Args.push_back(ConstantInt::get(Int64Ty, NumVarArgs)); - Args.push_back(AI); - } - + CI->getOperand(i)->dump(); // Add the original argument Args.push_back(CI->getOperand(i)); } // Create the new call - CallInst *CI_New = CallInst::Create(CI->getCalledValue(), + CallInst *CI_New = CallInst::Create(NewF, Args.begin(), Args.end(), "", CI); CI->replaceAllUsesWith(CI_New); @@ -594,9 +625,8 @@ bool TypeChecks::visitByValFunction(Module &M, Function &F) { // For internal functions - // Replace with a cloned function with extra arguments - // That takes as argument the original pointers without a byval parameter too - // Use them to copy the metadata over to the byval arguments + // Replace with a function with a a new function with no byval attr. + // Add an explicity copy in the function // Also update all the call sites. // For external functions From stuart at apple.com Thu Jun 2 00:05:39 2011 From: stuart at apple.com (Stuart Hastings) Date: Thu, 02 Jun 2011 05:05:39 -0000 Subject: [llvm-commits] [llvm] r132454 - /llvm/trunk/test/CodeGen/X86/setoeq.ll Message-ID: <20110602050539.D18112A6C12C@llvm.org> Author: stuart Date: Thu Jun 2 00:05:39 2011 New Revision: 132454 URL: http://llvm.org/viewvc/llvm-project?rev=132454&view=rev Log: Tweak testcase for ARM bot. rdar://problem/5993888 Modified: llvm/trunk/test/CodeGen/X86/setoeq.ll Modified: llvm/trunk/test/CodeGen/X86/setoeq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setoeq.ll?rev=132454&r1=132453&r2=132454&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/setoeq.ll (original) +++ llvm/trunk/test/CodeGen/X86/setoeq.ll Thu Jun 2 00:05:39 2011 @@ -1,4 +1,4 @@ -; RUN: llc < %s -march=x86 | FileCheck %s +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s define zeroext i8 @t(double %x) nounwind readnone { entry: From stoklund at 2pi.dk Thu Jun 2 00:43:50 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 02 Jun 2011 05:43:50 -0000 Subject: [llvm-commits] [llvm] r132456 - /llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Message-ID: <20110602054350.20CEB2A6C12D@llvm.org> Author: stoklund Date: Thu Jun 2 00:43:49 2011 New Revision: 132456 URL: http://llvm.org/viewvc/llvm-project?rev=132456&view=rev Log: Initialize members to fix problem found by valgrind. Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp?rev=132456&r1=132455&r2=132456&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Thu Jun 2 00:43:49 2011 @@ -20,7 +20,8 @@ using namespace llvm; -RegisterClassInfo::RegisterClassInfo() : Tag(0), TRI(0) {} +RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0) +{} void RegisterClassInfo::runOnMachineFunction(const MachineFunction &mf) { bool Update = false; @@ -35,7 +36,7 @@ // Does this MF have different CSRs? const unsigned *CSR = TRI->getCalleeSavedRegs(MF); - if (CSR != CalleeSaved) { + if (Update || CSR != CalleeSaved) { // Build a CSRNum map. Every CSR alias gets an entry pointing to the last // overlapping CSR. CSRNum.reset(new uint8_t[TRI->getNumRegs()]); From stoklund at 2pi.dk Thu Jun 2 00:43:46 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 02 Jun 2011 05:43:46 -0000 Subject: [llvm-commits] [llvm] r132455 - in /llvm/trunk/lib: CodeGen/MachineVerifier.cpp CodeGen/SelectionDAG/InstrEmitter.cpp CodeGen/TargetInstrInfoImpl.cpp Target/ARM/Thumb1RegisterInfo.cpp Target/Blackfin/BlackfinISelDAGToDAG.cpp Target/Blackfin/BlackfinInstrInfo.cpp Target/X86/X86RegisterInfo.cpp Message-ID: <20110602054346.E8E242A6C12C@llvm.org> Author: stoklund Date: Thu Jun 2 00:43:46 2011 New Revision: 132455 URL: http://llvm.org/viewvc/llvm-project?rev=132455&view=rev Log: Use TRI::has{Sub,Super}ClassEq() where possible. No functional change. Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=132455&r1=132454&r2=132455&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Thu Jun 2 00:43:46 2011 @@ -744,7 +744,7 @@ RC = SRC; } if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) { - if (RC != DRC && !RC->hasSuperClass(DRC)) { + if (!RC->hasSuperClassEq(DRC)) { report("Illegal virtual register for instruction", MO, MONum); *OS << "Expected a " << DRC->getName() << " register, but got a " << RC->getName() << " register\n"; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=132455&r1=132454&r2=132455&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Thu Jun 2 00:43:46 2011 @@ -283,7 +283,7 @@ DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && "Don't have operand info for this instruction!"); - if (DstRC && SrcRC != DstRC && !SrcRC->hasSuperClass(DstRC)) { + if (DstRC && !SrcRC->hasSuperClassEq(DstRC)) { unsigned NewVReg = MRI->createVirtualRegister(DstRC); BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(), TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg); Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=132455&r1=132454&r2=132455&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Thu Jun 2 00:43:46 2011 @@ -212,8 +212,7 @@ if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg())) return RC->contains(LiveOp.getReg()) ? RC : 0; - const TargetRegisterClass *LiveRC = MRI.getRegClass(LiveReg); - if (RC == LiveRC || RC->hasSubClass(LiveRC)) + if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) return RC; // FIXME: Allow folding when register classes are memory compatible. Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=132455&r1=132454&r2=132455&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Thu Jun 2 00:43:46 2011 @@ -49,7 +49,7 @@ const TargetRegisterClass* Thumb1RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const { - if (RC == ARM::tGPRRegisterClass || RC->hasSuperClass(ARM::tGPRRegisterClass)) + if (ARM::tGPRRegClass.hasSubClassEq(RC)) return ARM::tGPRRegisterClass; return ARMBaseRegisterInfo::getLargestLegalSuperClass(RC); } Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp?rev=132455&r1=132454&r2=132455&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp Thu Jun 2 00:43:46 2011 @@ -117,11 +117,11 @@ } static inline bool isCC(const TargetRegisterClass *RC) { - return RC == &BF::AnyCCRegClass || BF::AnyCCRegClass.hasSubClass(RC); + return BF::AnyCCRegClass.hasSubClassEq(RC); } static inline bool isDCC(const TargetRegisterClass *RC) { - return RC == &BF::DRegClass || BF::DRegClass.hasSubClass(RC) || isCC(RC); + return BF::DRegClass.hasSubClassEq(RC) || isCC(RC); } static void UpdateNodeOperand(SelectionDAG &DAG, Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp?rev=132455&r1=132454&r2=132455&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp Thu Jun 2 00:43:46 2011 @@ -160,7 +160,7 @@ if (TargetRegisterInfo::isPhysicalRegister(Reg)) return Test.contains(Reg); else - return &Test==RC || Test.hasSubClass(RC); + return Test.hasSubClassEq(RC); } void Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=132455&r1=132454&r2=132455&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Jun 2 00:43:46 2011 @@ -261,8 +261,7 @@ } break; case X86::sub_8bit_hi: - if (B == &X86::GR8_ABCD_HRegClass || - B->hasSubClass(&X86::GR8_ABCD_HRegClass)) + if (B->hasSubClassEq(&X86::GR8_ABCD_HRegClass)) switch (A->getSize()) { case 2: return getCommonSubClass(A, &X86::GR16_ABCDRegClass); case 4: return getCommonSubClass(A, &X86::GR32_ABCDRegClass); From benny.kra at googlemail.com Thu Jun 2 07:07:45 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Thu, 02 Jun 2011 12:07:45 -0000 Subject: [llvm-commits] [llvm] r132457 - /llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Message-ID: <20110602120745.210A92A6C12D@llvm.org> Author: d0k Date: Thu Jun 2 07:07:44 2011 New Revision: 132457 URL: http://llvm.org/viewvc/llvm-project?rev=132457&view=rev Log: Start with a zeroed CSRNum map. Found by valgrind. Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp?rev=132457&r1=132456&r2=132457&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Thu Jun 2 07:07:44 2011 @@ -39,7 +39,7 @@ if (Update || CSR != CalleeSaved) { // Build a CSRNum map. Every CSR alias gets an entry pointing to the last // overlapping CSR. - CSRNum.reset(new uint8_t[TRI->getNumRegs()]); + CSRNum.reset(new uint8_t[TRI->getNumRegs()]()); for (unsigned N = 0; unsigned Reg = CSR[N]; ++N) for (const unsigned *AS = TRI->getOverlaps(Reg); unsigned Alias = *AS; ++AS) From grosbach at apple.com Thu Jun 2 11:01:36 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Jun 2011 09:01:36 -0700 Subject: [llvm-commits] [llvm] r132451 - in /llvm/trunk: include/llvm/MC/MCInstPrinter.h lib/MC/MCAsmStreamer.cpp lib/MC/MCInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp lib/Target/X86/InstPrinter/X86ATTInstPrinter.h lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp lib/Target/X86/InstPrinter/X86IntelInstPrinter.h In-Reply-To: <20110602023455.800242A6C12C@llvm.org> References: <20110602023455.800242A6C12C@llvm.org> Message-ID: <6BF75306-1630-494E-95CD-DCE5935039FC@apple.com> Hi Rafael, Thanks for the quick turnaround. That takes care of the crash, but we're not quite there yet. A few questions. $ llvm-mc -triple armv7-apple-darwin10 t.s .section __TEXT,__text,regular,pure_instructions t.s:1:14: error: expected absolute expression .cfi_def_cfa r0, 8 It looks like the % prefix is also expected in the parsing? For the printer methods, getRegisterName() isn't going to work. That expects the internal enum register number, but the CFI directives from the streamer have the dwarf register number instead. I confess I'm a little confused at this patch in general. I was under the (mistaken?) impression that the cfi directives referred to registers via dwarf register number. Is that not the case? Is there something about that solution that's insufficient? Thanks, Jim On Jun 1, 2011, at 7:34 PM, Rafael Espindola wrote: > Author: rafael > Date: Wed Jun 1 21:34:55 2011 > New Revision: 132451 > > URL: http://llvm.org/viewvc/llvm-project?rev=132451&view=rev > Log: > Don't hardcode the %reg format in the streamer. > > Modified: > llvm/trunk/include/llvm/MC/MCInstPrinter.h > llvm/trunk/lib/MC/MCAsmStreamer.cpp > llvm/trunk/lib/MC/MCInstPrinter.cpp > llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp > llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h > llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp > llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h > llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp > llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h > llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp > llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h > > Modified: llvm/trunk/include/llvm/MC/MCInstPrinter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/MC/MCInstPrinter.h (original) > +++ llvm/trunk/include/llvm/MC/MCInstPrinter.h Wed Jun 1 21:34:55 2011 > @@ -45,8 +45,8 @@ > /// "MOV32ri") or empty if we can't resolve it. > virtual StringRef getOpcodeName(unsigned Opcode) const; > > - /// getRegName - Return the assembler register name. > - virtual StringRef getRegName(unsigned RegNo) const; > + /// printRegName - Print the assembler register name. > + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; > > unsigned getAvailableFeatures() const { return AvailableFeatures; } > void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; } > > Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=132451&r1=132450&r2=132451&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) > +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Jun 1 21:34:55 2011 > @@ -825,7 +825,7 @@ > if (InstPrinter) { > const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo(); > unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true); > - OS << '%' << InstPrinter->getRegName(LLVMRegister); > + InstPrinter->printRegName(OS, LLVMRegister); > } else { > OS << Register; > } > @@ -1169,8 +1169,10 @@ > } > > void MCAsmStreamer::EmitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset) { > - OS << "\t.setfp\t" << InstPrinter->getRegName(FpReg) > - << ", " << InstPrinter->getRegName(SpReg); > + OS << "\t.setfp\t"; > + InstPrinter->printRegName(OS, FpReg); > + OS << ", "; > + InstPrinter->printRegName(OS, SpReg); > if (Offset) > OS << ", #" << Offset; > EmitEOL(); > @@ -1189,10 +1191,12 @@ > else > OS << "\t.save\t{"; > > - OS << InstPrinter->getRegName(RegList[0]); > + InstPrinter->printRegName(OS, RegList[0]); > > - for (unsigned i = 1, e = RegList.size(); i != e; ++i) > - OS << ", " << InstPrinter->getRegName(RegList[i]); > + for (unsigned i = 1, e = RegList.size(); i != e; ++i) { > + OS << ", "; > + InstPrinter->printRegName(OS, RegList[i]); > + } > > OS << "}"; > EmitEOL(); > > Modified: llvm/trunk/lib/MC/MCInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCInstPrinter.cpp (original) > +++ llvm/trunk/lib/MC/MCInstPrinter.cpp Wed Jun 1 21:34:55 2011 > @@ -20,7 +20,6 @@ > return ""; > } > > -StringRef MCInstPrinter::getRegName(unsigned RegNo) const { > +void MCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { > assert(0 && "Target should implement this"); > - return ""; > } > > Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Jun 1 21:34:55 2011 > @@ -29,8 +29,8 @@ > return getInstructionName(Opcode); > } > > -StringRef ARMInstPrinter::getRegName(unsigned RegNo) const { > - return getRegisterName(RegNo); > +void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { > + OS << getRegisterName(RegNo); > } > > void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { > > Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) > +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Wed Jun 1 21:34:55 2011 > @@ -28,7 +28,7 @@ > > virtual void printInst(const MCInst *MI, raw_ostream &O); > virtual StringRef getOpcodeName(unsigned Opcode) const; > - virtual StringRef getRegName(unsigned RegNo) const; > + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; > > static const char *getInstructionName(unsigned Opcode); > > > Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Wed Jun 1 21:34:55 2011 > @@ -26,8 +26,8 @@ > return getInstructionName(Opcode); > } > > -StringRef PPCInstPrinter::getRegName(unsigned RegNo) const { > - return getRegisterName(RegNo); > +void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { > + OS << getRegisterName(RegNo); > } > > void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { > > Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h (original) > +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h Wed Jun 1 21:34:55 2011 > @@ -33,7 +33,7 @@ > return SyntaxVariant == 1; > } > > - StringRef getRegName(unsigned RegNo) const; > + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; > virtual void printInst(const MCInst *MI, raw_ostream &O); > virtual StringRef getOpcodeName(unsigned Opcode) const; > > > Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Wed Jun 1 21:34:55 2011 > @@ -41,8 +41,9 @@ > &TM.getSubtarget())); > } > > -StringRef X86ATTInstPrinter::getRegName(unsigned RegNo) const { > - return getRegisterName(RegNo); > +void X86ATTInstPrinter::printRegName(raw_ostream &OS, > + unsigned RegNo) const { > + OS << '%' << getRegisterName(RegNo); > } > > void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { > > Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original) > +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Wed Jun 1 21:34:55 2011 > @@ -26,7 +26,7 @@ > public: > X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI); > > - StringRef getRegName(unsigned RegNo) const; > + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; > virtual void printInst(const MCInst *MI, raw_ostream &OS); > virtual StringRef getOpcodeName(unsigned Opcode) const; > > > Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp (original) > +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Wed Jun 1 21:34:55 2011 > @@ -29,8 +29,8 @@ > #define GET_INSTRUCTION_NAME > #include "X86GenAsmWriter1.inc" > > -StringRef X86IntelInstPrinter::getRegName(unsigned RegNo) const { > - return getRegisterName(RegNo); > +void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { > + OS << getRegisterName(RegNo); > } > > void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { > > Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h (original) > +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h Wed Jun 1 21:34:55 2011 > @@ -27,7 +27,7 @@ > X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) > : MCInstPrinter(MAI) {} > > - StringRef getRegName(unsigned RegNo) const; > + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; > virtual void printInst(const MCInst *MI, raw_ostream &OS); > virtual StringRef getOpcodeName(unsigned Opcode) const; > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stuart at apple.com Thu Jun 2 10:57:11 2011 From: stuart at apple.com (Stuart Hastings) Date: Thu, 02 Jun 2011 15:57:11 -0000 Subject: [llvm-commits] [llvm] r132458 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-06-01-fildll.ll Message-ID: <20110602155712.0FAA32A6C12C@llvm.org> Author: stuart Date: Thu Jun 2 10:57:11 2011 New Revision: 132458 URL: http://llvm.org/viewvc/llvm-project?rev=132458&view=rev Log: Omit unnecessary stack copy when x87 input is a load. rdar://problem/6373334 Added: llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=132458&r1=132457&r2=132458&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jun 2 10:57:11 2011 @@ -6700,6 +6700,11 @@ DebugLoc dl = Op.getDebugLoc(); unsigned Size = SrcVT.getSizeInBits()/8; MachineFunction &MF = DAG.getMachineFunction(); + + SDValue Addr = Op.getOperand(0); + if (Addr.getOpcode() == ISD::LOAD) + return BuildFILD(Op, SrcVT, DAG.getEntryNode(), Addr, DAG); + int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), @@ -6723,12 +6728,18 @@ unsigned ByteSize = SrcVT.getSizeInBits()/8; - int SSFI = cast(StackSlot)->getIndex(); - MachineMemOperand *MMO = - DAG.getMachineFunction() - .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), - MachineMemOperand::MOLoad, ByteSize, ByteSize); - + FrameIndexSDNode *FI = dyn_cast(StackSlot); + MachineMemOperand *MMO; + if (FI) { + int SSFI = FI->getIndex(); + MMO = + DAG.getMachineFunction() + .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), + MachineMemOperand::MOLoad, ByteSize, ByteSize); + } else { + MMO = cast(StackSlot)->getMemOperand(); + StackSlot = StackSlot.getOperand(1); + } SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : X86ISD::FILD, DL, Added: llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll?rev=132458&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll (added) +++ llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll Thu Jun 2 10:57:11 2011 @@ -0,0 +1,15 @@ +; RUN: llc %s -march=x86 +; ModuleID = '' +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-macosx10.6.6" + +define float @f(i64* nocapture %x) nounwind readonly ssp { +entry: +; CHECK: movl +; CHECK-NOT: movl + %tmp1 = load i64* %x, align 4 +; CHECK: fildll + %conv = sitofp i64 %tmp1 to float + %add = fadd float %conv, 1.000000e+00 + ret float %add +} From syoyofujita at gmail.com Thu Jun 2 11:12:49 2011 From: syoyofujita at gmail.com (Syoyo Fujita) Date: Fri, 3 Jun 2011 01:12:49 +0900 Subject: [llvm-commits] Fix sitofp and fpextend codegen for x86/AVX[PR9473] In-Reply-To: References: Message-ID: Hello Bruno, Thanks for the advice, > From the intel manual: > > VCVTSS2SD- Convert one single-precision floating-point value in > xmm3/m32 to one double-precision floating- point value and merge with > high bits of xmm2. > > And, according to your patch: > > +let isAsmParserOnly = 1 in { > + ?def VCVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), > + ? ? ? ? ? ? ? ? ? ? ?(ins FR32:$src1, f32mem:$src2), > + ? ? ? ? ? ? ? ? ? ? ?"vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}", > + ? ? ? ? ? ? ? ? ? ? ?[]>, XS, VEX_4V, Requires<[HasAVX, OptForSize]>; > +} > + > +def VCVTSS2SDrm_alt : I<0x5A, MRMSrcMem, (outs FR64:$dst), > + ? ? ? ? ? ? ? ? ? ?(ins f32mem:$src), > + ? ? ? ? ? ? ? ? ? ?"vcvtss2sd\t{$src, $src, $dst|$dst, $src, $src}", > + ? ? ? ? ? ? ? ? ? ?[]>, XS, VEX, Requires<[HasAVX, OptForSize]>; > > The "alt" version is using a different encoding, this isn't correct, > since there's only one encoding for the "rm" version, which is the > "VEX_4V" one. There is no need for the "alt" version actually, but to > follow the manual "merge with high bits of xmm2": > > Instead of doing: > > +def : Pat<(extloadf32 addr:$src), > + ? ? ? ? ?(VCVTSS2SDrm_alt addr:$src)>, > > You can do: > > def : Pat<(extloadf32 addr:$src2), > ? ? ? ? ?(VCVTSS2SDrm 0, addr:$src2)>, > > or something like that... Ah, Its new for me. Since I had no idea how to use 'dummy' rester in .td, I just tried to solve the problem as in my patch. I'll investigate to rewrite my patch with above expression('0' in input register) > A better solution, since this instruction is dealing with F32 reg > classes and the high bits won't be touched, is to declare VCVTSS2SDrm > as having Constraints = "$src1 = $dst", but keep printing its operands > as usual. Also, you can do the pattern matching inline in the > instruction definition, no need to do it as a Pat here. I believe you > can do something similar to VCVTSI2SD_alt. > Okay, I'll try it and resend my (modified) patch. -- Syoyo From grosbach at apple.com Thu Jun 2 11:53:45 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Jun 2011 09:53:45 -0700 Subject: [llvm-commits] [llvm] r132451 - in /llvm/trunk: include/llvm/MC/MCInstPrinter.h lib/MC/MCAsmStreamer.cpp lib/MC/MCInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp lib/Target/X86/InstPrinter/X86ATTInstPrinter.h lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp lib/Target/X86/InstPrinter/X86IntelInstPrinter.h In-Reply-To: <6BF75306-1630-494E-95CD-DCE5935039FC@apple.com> References: <20110602023455.800242A6C12C@llvm.org> <6BF75306-1630-494E-95CD-DCE5935039FC@apple.com> Message-ID: <451B875E-438E-4BCE-B39B-C5ED6A862E72@apple.com> On Jun 2, 2011, at 9:01 AM, Jim Grosbach wrote: > Hi Rafael, > > Thanks for the quick turnaround. That takes care of the crash, but we're not quite there yet. A few questions. > > $ llvm-mc -triple armv7-apple-darwin10 t.s > .section __TEXT,__text,regular,pure_instructions > t.s:1:14: error: expected absolute expression > .cfi_def_cfa r0, 8 > > It looks like the % prefix is also expected in the parsing? > > For the printer methods, getRegisterName() isn't going to work. That expects the internal enum register number, but the CFI directives from the streamer have the dwarf register number instead. > Never mind this bit. Looks like the streamer translates that prior to calling the hook. That does raise another question, though. In looking at this, I noticed that in an old patch (121471), the TargetAsmInfo class was introduced and it contains a pointer to a TargetRegisterInfo. That's a layering problem, as it forces anything MC based to link in the entire codegen backend (TargetRegisterInfo is part of the MachineInstr layer). Can we find a better way to do this? Some tablegenerated helper functions, perhaps? -Jim > I confess I'm a little confused at this patch in general. I was under the (mistaken?) impression that the cfi directives referred to registers via dwarf register number. Is that not the case? Is there something about that solution that's insufficient? > > Thanks, > Jim > > > On Jun 1, 2011, at 7:34 PM, Rafael Espindola wrote: > >> Author: rafael >> Date: Wed Jun 1 21:34:55 2011 >> New Revision: 132451 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132451&view=rev >> Log: >> Don't hardcode the %reg format in the streamer. >> >> Modified: >> llvm/trunk/include/llvm/MC/MCInstPrinter.h >> llvm/trunk/lib/MC/MCAsmStreamer.cpp >> llvm/trunk/lib/MC/MCInstPrinter.cpp >> llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp >> llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h >> llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp >> llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h >> llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp >> llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h >> llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp >> llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h >> >> Modified: llvm/trunk/include/llvm/MC/MCInstPrinter.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff >> ============================================================================== >> --- llvm/trunk/include/llvm/MC/MCInstPrinter.h (original) >> +++ llvm/trunk/include/llvm/MC/MCInstPrinter.h Wed Jun 1 21:34:55 2011 >> @@ -45,8 +45,8 @@ >> /// "MOV32ri") or empty if we can't resolve it. >> virtual StringRef getOpcodeName(unsigned Opcode) const; >> >> - /// getRegName - Return the assembler register name. >> - virtual StringRef getRegName(unsigned RegNo) const; >> + /// printRegName - Print the assembler register name. >> + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; >> >> unsigned getAvailableFeatures() const { return AvailableFeatures; } >> void setAvailableFeatures(unsigned Value) { AvailableFeatures = Value; } >> >> Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=132451&r1=132450&r2=132451&view=diff >> ============================================================================== >> --- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original) >> +++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Wed Jun 1 21:34:55 2011 >> @@ -825,7 +825,7 @@ >> if (InstPrinter) { >> const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo(); >> unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true); >> - OS << '%' << InstPrinter->getRegName(LLVMRegister); >> + InstPrinter->printRegName(OS, LLVMRegister); >> } else { >> OS << Register; >> } >> @@ -1169,8 +1169,10 @@ >> } >> >> void MCAsmStreamer::EmitSetFP(unsigned FpReg, unsigned SpReg, int64_t Offset) { >> - OS << "\t.setfp\t" << InstPrinter->getRegName(FpReg) >> - << ", " << InstPrinter->getRegName(SpReg); >> + OS << "\t.setfp\t"; >> + InstPrinter->printRegName(OS, FpReg); >> + OS << ", "; >> + InstPrinter->printRegName(OS, SpReg); >> if (Offset) >> OS << ", #" << Offset; >> EmitEOL(); >> @@ -1189,10 +1191,12 @@ >> else >> OS << "\t.save\t{"; >> >> - OS << InstPrinter->getRegName(RegList[0]); >> + InstPrinter->printRegName(OS, RegList[0]); >> >> - for (unsigned i = 1, e = RegList.size(); i != e; ++i) >> - OS << ", " << InstPrinter->getRegName(RegList[i]); >> + for (unsigned i = 1, e = RegList.size(); i != e; ++i) { >> + OS << ", "; >> + InstPrinter->printRegName(OS, RegList[i]); >> + } >> >> OS << "}"; >> EmitEOL(); >> >> Modified: llvm/trunk/lib/MC/MCInstPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff >> ============================================================================== >> --- llvm/trunk/lib/MC/MCInstPrinter.cpp (original) >> +++ llvm/trunk/lib/MC/MCInstPrinter.cpp Wed Jun 1 21:34:55 2011 >> @@ -20,7 +20,6 @@ >> return ""; >> } >> >> -StringRef MCInstPrinter::getRegName(unsigned RegNo) const { >> +void MCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { >> assert(0 && "Target should implement this"); >> - return ""; >> } >> >> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp Wed Jun 1 21:34:55 2011 >> @@ -29,8 +29,8 @@ >> return getInstructionName(Opcode); >> } >> >> -StringRef ARMInstPrinter::getRegName(unsigned RegNo) const { >> - return getRegisterName(RegNo); >> +void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { >> + OS << getRegisterName(RegNo); >> } >> >> void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { >> >> Modified: llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h (original) >> +++ llvm/trunk/lib/Target/ARM/InstPrinter/ARMInstPrinter.h Wed Jun 1 21:34:55 2011 >> @@ -28,7 +28,7 @@ >> >> virtual void printInst(const MCInst *MI, raw_ostream &O); >> virtual StringRef getOpcodeName(unsigned Opcode) const; >> - virtual StringRef getRegName(unsigned RegNo) const; >> + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; >> >> static const char *getInstructionName(unsigned Opcode); >> >> >> Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp (original) >> +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp Wed Jun 1 21:34:55 2011 >> @@ -26,8 +26,8 @@ >> return getInstructionName(Opcode); >> } >> >> -StringRef PPCInstPrinter::getRegName(unsigned RegNo) const { >> - return getRegisterName(RegNo); >> +void PPCInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { >> + OS << getRegisterName(RegNo); >> } >> >> void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) { >> >> Modified: llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h (original) >> +++ llvm/trunk/lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h Wed Jun 1 21:34:55 2011 >> @@ -33,7 +33,7 @@ >> return SyntaxVariant == 1; >> } >> >> - StringRef getRegName(unsigned RegNo) const; >> + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; >> virtual void printInst(const MCInst *MI, raw_ostream &O); >> virtual StringRef getOpcodeName(unsigned Opcode) const; >> >> >> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) >> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Wed Jun 1 21:34:55 2011 >> @@ -41,8 +41,9 @@ >> &TM.getSubtarget())); >> } >> >> -StringRef X86ATTInstPrinter::getRegName(unsigned RegNo) const { >> - return getRegisterName(RegNo); >> +void X86ATTInstPrinter::printRegName(raw_ostream &OS, >> + unsigned RegNo) const { >> + OS << '%' << getRegisterName(RegNo); >> } >> >> void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { >> >> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h (original) >> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.h Wed Jun 1 21:34:55 2011 >> @@ -26,7 +26,7 @@ >> public: >> X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI); >> >> - StringRef getRegName(unsigned RegNo) const; >> + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; >> virtual void printInst(const MCInst *MI, raw_ostream &OS); >> virtual StringRef getOpcodeName(unsigned Opcode) const; >> >> >> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp?rev=132451&r1=132450&r2=132451&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp (original) >> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Wed Jun 1 21:34:55 2011 >> @@ -29,8 +29,8 @@ >> #define GET_INSTRUCTION_NAME >> #include "X86GenAsmWriter1.inc" >> >> -StringRef X86IntelInstPrinter::getRegName(unsigned RegNo) const { >> - return getRegisterName(RegNo); >> +void X86IntelInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const { >> + OS << getRegisterName(RegNo); >> } >> >> void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) { >> >> Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h?rev=132451&r1=132450&r2=132451&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h (original) >> +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.h Wed Jun 1 21:34:55 2011 >> @@ -27,7 +27,7 @@ >> X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) >> : MCInstPrinter(MAI) {} >> >> - StringRef getRegName(unsigned RegNo) const; >> + virtual void printRegName(raw_ostream &OS, unsigned RegNo) const; >> virtual void printInst(const MCInst *MI, raw_ostream &OS); >> virtual StringRef getOpcodeName(unsigned Opcode) const; >> >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From aggarwa4 at illinois.edu Thu Jun 2 11:58:43 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 02 Jun 2011 16:58:43 -0000 Subject: [llvm-commits] [poolalloc] r132463 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110602165843.5F7982A6C12D@llvm.org> Author: aggarwa4 Date: Thu Jun 2 11:58:43 2011 New Revision: 132463 URL: http://llvm.org/viewvc/llvm-project?rev=132463&view=rev Log: Instead of passing the number of varargs, pass the number of total arguments. Each function, then subtracts the number of fixed arguments in its signature. Hence, the callee need not know the number of fixed args. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132463&r1=132462&r2=132463&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 2 11:58:43 2011 @@ -483,7 +483,14 @@ inst_iterator InsPt = inst_begin(NewF); Function::arg_iterator NII = NewF->arg_begin(); AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt); - new StoreInst(NII, VASizeLoc, &*InsPt); + // Subtract the number of initial arguments + Constant *InitialArgs = ConstantInt::get(Int64Ty, F.arg_size()); + Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Sub, + NII, + InitialArgs, + "varargs", + &*InsPt); + new StoreInst(NewValue, VASizeLoc, &*InsPt); NII++; AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt); new StoreInst(NII, VAMDLoc, &*InsPt); @@ -548,7 +555,6 @@ } } - assert(VAStart && "Varargs function without a call to VAStart???"); // modify calls to va list functions to pass the metadata for (Function::iterator B = NewF->begin(), FE = NewF->end(); B != FE; ++B) { for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) { @@ -585,9 +591,9 @@ continue; std::vector Args; unsigned int i; - unsigned int NumVarArgs = CI->getNumOperands() - F.arg_size() - 1; - Value *NumArgs = ConstantInt::get(Int32Ty, NumVarArgs); - AllocaInst *AI = new AllocaInst(Int8Ty, NumArgs, "", CI); + unsigned int NumArgs = CI->getNumOperands() - 1; + Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); + AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", CI); // set the metadata for the varargs in AI unsigned int j =0; for(i = F.arg_size() + 1; i getNumOperands(); i++) { @@ -604,10 +610,9 @@ } // As the first argument pass the number of var_arg arguments - Args.push_back(ConstantInt::get(Int64Ty, NumVarArgs)); + Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); Args.push_back(AI); for(i = 1 ;i < CI->getNumOperands(); i++) { - CI->getOperand(i)->dump(); // Add the original argument Args.push_back(CI->getOperand(i)); } From aggarwa4 at illinois.edu Thu Jun 2 12:10:43 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 02 Jun 2011 17:10:43 -0000 Subject: [llvm-commits] [poolalloc] r132464 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Message-ID: <20110602171043.92C6D2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 2 12:10:43 2011 New Revision: 132464 URL: http://llvm.org/viewvc/llvm-project?rev=132464&view=rev Log: Improve the error printing. Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=132464&r1=132463&r2=132464&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Thu Jun 2 12:10:43 2011 @@ -118,7 +118,7 @@ */ void compareTypes(uint8_t typeNumberSrc, uint8_t typeNumberDest, uint32_t tag) { if(typeNumberSrc != typeNumberDest) { - printf("Type mismatch: detecting %u, expecting %u! %u %s, %s\n", typeNumberDest, typeNumberSrc, tag, typeNames[typeNumberDest], typeNames[typeNumberSrc]); + printf("Type mismatch(%u): detecting %s, expecting %s! \n", tag, typeNames[typeNumberDest], typeNames[typeNumberSrc]); } } @@ -127,7 +127,7 @@ */ void compareNumber(uint64_t NumArgsPassed, uint64_t ArgAccessed, uint32_t tag){ if(ArgAccessed > NumArgsPassed) { - printf("Type mismatch: Accessing variable %lu, passed only %lu! %u \n", ArgAccessed, NumArgsPassed, tag); + printf("Type mismatch(%u): Accessing variable %lu, passed only %lu! \n", tag, ArgAccessed, NumArgsPassed); } } @@ -152,14 +152,14 @@ /* Check if this an initialized but untyped memory.*/ if (typeNumber != shadow_begin[p]) { if (shadow_begin[p] != 0xFF) { - printf("Type mismatch: detecting %u, expecting %u! %u %s %s\n", typeNumber, shadow_begin[p], tag, typeNames[typeNumber], typeNames[shadow_begin[p]]); + printf("Type mismatch(%u): detecting %s, expecting %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p]]); return; } else { /* If so, set type to the type being read. Check that none of the bytes are typed.*/ for (; i < size; ++i) { if (0xFF != shadow_begin[p + i]) { - printf("Type mismatch: detecting %u, expecting %u (0 != %u)! %u\n", typeNumber, shadow_begin[p+i], shadow_begin[p + i], tag); + printf("Type alignment mismatch(%u): detecting %s, expecting %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p+i]]); break; } } @@ -170,7 +170,7 @@ for (; i < size; ++i) { if (0 != shadow_begin[p + i]) { - printf("Type mismatch: detecting %u, expecting %u (0 != %u)!\n", typeNumber, shadow_begin[p], shadow_begin[p + i]); + printf("Type alignment mismatch(%u): detecting %s, expecting %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p]]); break; } } From aggarwa4 at illinois.edu Thu Jun 2 12:12:25 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 02 Jun 2011 17:12:25 -0000 Subject: [llvm-commits] [poolalloc] r132465 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Message-ID: <20110602171225.C948F2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 2 12:12:25 2011 New Revision: 132465 URL: http://llvm.org/viewvc/llvm-project?rev=132465&view=rev Log: Modify the error printing. Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=132465&r1=132464&r2=132465&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Thu Jun 2 12:12:25 2011 @@ -118,7 +118,7 @@ */ void compareTypes(uint8_t typeNumberSrc, uint8_t typeNumberDest, uint32_t tag) { if(typeNumberSrc != typeNumberDest) { - printf("Type mismatch(%u): detecting %s, expecting %s! \n", tag, typeNames[typeNumberDest], typeNames[typeNumberSrc]); + printf("Type mismatch(%u): expecting %s, found %s! \n", tag, typeNames[typeNumberDest], typeNames[typeNumberSrc]); } } @@ -152,14 +152,14 @@ /* Check if this an initialized but untyped memory.*/ if (typeNumber != shadow_begin[p]) { if (shadow_begin[p] != 0xFF) { - printf("Type mismatch(%u): detecting %s, expecting %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p]]); + printf("Type mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p]]); return; } else { /* If so, set type to the type being read. Check that none of the bytes are typed.*/ for (; i < size; ++i) { if (0xFF != shadow_begin[p + i]) { - printf("Type alignment mismatch(%u): detecting %s, expecting %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p+i]]); + printf("Type alignment mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p+i]]); break; } } @@ -170,7 +170,7 @@ for (; i < size; ++i) { if (0 != shadow_begin[p + i]) { - printf("Type alignment mismatch(%u): detecting %s, expecting %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p]]); + printf("Type alignment mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p]]); break; } } From grosbach at apple.com Thu Jun 2 12:14:04 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Jun 2011 17:14:04 -0000 Subject: [llvm-commits] [llvm] r132466 - /llvm/trunk/lib/MC/MCParser/AsmParser.cpp Message-ID: <20110602171404.EAFA92A6C12C@llvm.org> Author: grosbach Date: Thu Jun 2 12:14:04 2011 New Revision: 132466 URL: http://llvm.org/viewvc/llvm-project?rev=132466&view=rev Log: .cfi directive register parsing flexibility. Parsing a register name/number for .cfi directives can't assume that a register name starts with a '%' token. Be more flexible and check for a register number instead. Still unlikely to be perfect, but it allows us to parse both plain identifiers as register names and integers as register numbers, which is what we're wanting to support at this point. Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=132466&r1=132465&r2=132466&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Jun 2 12:14:04 2011 @@ -2330,7 +2330,7 @@ SMLoc DirectiveLoc) { unsigned RegNo; - if (getLexer().is(AsmToken::Percent)) { + if (getLexer().isNot(AsmToken::Integer)) { if (getParser().getTargetParser().ParseRegister(RegNo, DirectiveLoc, DirectiveLoc)) return true; From grosbach at apple.com Thu Jun 2 12:21:08 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Jun 2011 10:21:08 -0700 Subject: [llvm-commits] [llvm] r132466 - /llvm/trunk/lib/MC/MCParser/AsmParser.cpp In-Reply-To: <20110602171404.EAFA92A6C12C@llvm.org> References: <20110602171404.EAFA92A6C12C@llvm.org> Message-ID: Hi Rafael, I think this does the right thing for parsing register names vs. numbers in .cfi directives for the asm parser. Seem right to you? -Jim On Jun 2, 2011, at 10:14 AM, Jim Grosbach wrote: > Author: grosbach > Date: Thu Jun 2 12:14:04 2011 > New Revision: 132466 > > URL: http://llvm.org/viewvc/llvm-project?rev=132466&view=rev > Log: > .cfi directive register parsing flexibility. > > Parsing a register name/number for .cfi directives can't assume that a > register name starts with a '%' token. Be more flexible and check for a > register number instead. Still unlikely to be perfect, but it allows us > to parse both plain identifiers as register names and integers as register > numbers, which is what we're wanting to support at this point. > > > Modified: > llvm/trunk/lib/MC/MCParser/AsmParser.cpp > > Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=132466&r1=132465&r2=132466&view=diff > ============================================================================== > --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) > +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Thu Jun 2 12:14:04 2011 > @@ -2330,7 +2330,7 @@ > SMLoc DirectiveLoc) { > unsigned RegNo; > > - if (getLexer().is(AsmToken::Percent)) { > + if (getLexer().isNot(AsmToken::Integer)) { > if (getParser().getTargetParser().ParseRegister(RegNo, DirectiveLoc, > DirectiveLoc)) > return true; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From aggarwa4 at illinois.edu Thu Jun 2 12:19:32 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 02 Jun 2011 17:19:32 -0000 Subject: [llvm-commits] [poolalloc] r132467 - in /poolalloc/trunk/test/type_checks/error: indirect_simple.c misalign.c misalign1.c Message-ID: <20110602171932.DA27D2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 2 12:19:32 2011 New Revision: 132467 URL: http://llvm.org/viewvc/llvm-project?rev=132467&view=rev Log: More testcases. Added: poolalloc/trunk/test/type_checks/error/indirect_simple.c poolalloc/trunk/test/type_checks/error/misalign.c poolalloc/trunk/test/type_checks/error/misalign1.c Added: poolalloc/trunk/test/type_checks/error/indirect_simple.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/type_checks/error/indirect_simple.c?rev=132467&view=auto ============================================================================== --- poolalloc/trunk/test/type_checks/error/indirect_simple.c (added) +++ poolalloc/trunk/test/type_checks/error/indirect_simple.c Thu Jun 2 12:19:32 2011 @@ -0,0 +1,31 @@ +/* + * Build into bitcode + * RUN: llvm-gcc -O0 %s --emit-llvm -c -o %t.bc + * RUN: adsaopt -internalize -mem2reg -typechecks %t.bc -o %t.tc.bc + * RUN: tc-link %t.tc.bc -o %t.tc1.bc + * RUN: llc %t.tc1.bc -o %t.tc1.s + * RUN: llvm-gcc %t.tc1.s -o %t.tc2 + * Execute + * RUN: %t.tc2 >& %t.tc.out + */ +#include + +typedef int* (*funcptr)(double *); + +static int *foo(double *d) { + return (int*)d; +} +static int *bar(double *d) { + return (int*)(d+1); +} +int main(int argc, char **argv) +{ + + funcptr FP; + FP = &foo; + if(argc > 5) + FP = &bar; + double d = 5.0; + int *t = (*FP)(&d); + int v = *t; +} Added: poolalloc/trunk/test/type_checks/error/misalign.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/type_checks/error/misalign.c?rev=132467&view=auto ============================================================================== --- poolalloc/trunk/test/type_checks/error/misalign.c (added) +++ poolalloc/trunk/test/type_checks/error/misalign.c Thu Jun 2 12:19:32 2011 @@ -0,0 +1,34 @@ +/* + * Build into bitcode + * RUN: llvm-gcc -O0 %s --emit-llvm -c -o %t.bc + * RUN: adsaopt -internalize -mem2reg -typechecks %t.bc -o %t.tc.bc + * RUN: tc-link %t.tc.bc -o %t.tc1.bc + * RUN: llc %t.tc1.bc -o %t.tc1.s + * RUN: llvm-gcc %t.tc1.s -o %t.tc2 + * Execute + * RUN: %t.tc2 >& %t.tc.out + * ;XFAIL:* + */ + +#include + + +typedef unsigned char byte; //!< byte type definition + +int testEndian() +{ + short s; + byte *p; + + p=(byte*)&s; + + s=1; + + return (*(p+1)==0); +} + +int main() { + testEndian(); + return 0; +} + Added: poolalloc/trunk/test/type_checks/error/misalign1.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/type_checks/error/misalign1.c?rev=132467&view=auto ============================================================================== --- poolalloc/trunk/test/type_checks/error/misalign1.c (added) +++ poolalloc/trunk/test/type_checks/error/misalign1.c Thu Jun 2 12:19:32 2011 @@ -0,0 +1,34 @@ +/* + * Build into bitcode + * RUN: llvm-gcc -O0 %s --emit-llvm -c -o %t.bc + * RUN: adsaopt -internalize -mem2reg -typechecks %t.bc -o %t.tc.bc + * RUN: tc-link %t.tc.bc -o %t.tc1.bc + * RUN: llc %t.tc1.bc -o %t.tc1.s + * RUN: llvm-gcc %t.tc1.s -o %t.tc2 + * Execute + * RUN: %t.tc2 >& %t.tc.out + * ;XFAIL:* + */ + +#include + + +typedef unsigned char byte; //!< byte type definition + +int testEndian() +{ + short s; + byte *p; + + p=(byte*)&s; + + *(p+1)=1; + + return (s==0); +} + +int main() { + testEndian(); + return 0; +} + From aggarwa4 at illinois.edu Thu Jun 2 12:53:01 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 02 Jun 2011 17:53:01 -0000 Subject: [llvm-commits] [poolalloc] r132469 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110602175301.285CF2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 2 12:53:00 2011 New Revision: 132469 URL: http://llvm.org/viewvc/llvm-project?rev=132469&view=rev Log: Pass metadata for all the arguments to a vararg call. At the entry to the function, increment pointer by the number of initial fixed arguments. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132469&r1=132468&r2=132469&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 2 12:53:00 2011 @@ -152,6 +152,26 @@ modified |= visitByValFunction(M, *F); } + // NOTE:must visit before VAArgFunctions, to populate the map with the + // correct cloned functions. + while(!VAListFunctions.empty()) { + Function *F = VAListFunctions.back(); + VAListFunctions.pop_back(); + modified |= visitVAListFunction(M, *F); + } + + // iterate through all the VAList funtions and modify call sites + // to call the new function + std::map::iterator FI = VAListFunctionsMap.begin(), FE = VAListFunctionsMap.end(); + for(; FI != FE; FI++) { + visitVAListCall(FI->second); + } + while(!VAArgFunctions.empty()) { + Function *F = VAArgFunctions.back(); + VAArgFunctions.pop_back(); + assert(F->isVarArg()); + modified |= visitVarArgFunction(M, *F); + } for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; if(F.isDeclaration()) @@ -184,27 +204,6 @@ } } - // NOTE:must visit before VAArgFunctions, to populate the map with the - // correct cloned functions. - while(!VAListFunctions.empty()) { - Function *F = VAListFunctions.back(); - VAListFunctions.pop_back(); - modified |= visitVAListFunction(M, *F); - } - - // iterate through all the VAList funtions and modify call sites - // to call the new function - std::map::iterator FI = VAListFunctionsMap.begin(), FE = VAListFunctionsMap.end(); - for(; FI != FE; FI++) { - visitVAListCall(FI->second); - } - while(!VAArgFunctions.empty()) { - Function *F = VAArgFunctions.back(); - VAArgFunctions.pop_back(); - assert(F->isVarArg()); - modified |= visitVarArgFunction(M, *F); - } - // add a global that contains the mapping from metadata to strings addTypeMap(M); @@ -419,10 +418,9 @@ } // each vararg function is modified so that the first -// argument is the number of arguments in the va_list, +// argument is the number of arguments passed in, // and the second is a pointer to a metadata array, // containing type information for each of the arguments -// in the va_list. // These are read and stored at the beginning of the function. @@ -492,8 +490,18 @@ &*InsPt); new StoreInst(NewValue, VASizeLoc, &*InsPt); NII++; + AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt); - new StoreInst(NII, VAMDLoc, &*InsPt); + // Increment by the number of Initial Args, so as to not read the metadata + //for those. + Value *Idx[2]; + Idx[0] = InitialArgs; + // For each vararg argument, also add its type information + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(NII, + Idx, + Idx + 1, + "", &*InsPt); + new StoreInst(GEP, VAMDLoc, &*InsPt); // Add a counter variable to the function entry AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt); new StoreInst(ConstantInt::get(Int64Ty, 0), Counter, &*InsPt); @@ -596,7 +604,7 @@ AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", CI); // set the metadata for the varargs in AI unsigned int j =0; - for(i = F.arg_size() + 1; i getNumOperands(); i++) { + for(i = 1; i getNumOperands(); i++) { Value *Idx[2]; Idx[0] = ConstantInt::get(Int32Ty, j++); // For each vararg argument, also add its type information From rafael.espindola at gmail.com Thu Jun 2 13:01:35 2011 From: rafael.espindola at gmail.com (Rafael Avila de Espindola) Date: Thu, 02 Jun 2011 14:01:35 -0400 Subject: [llvm-commits] [llvm] r132466 - /llvm/trunk/lib/MC/MCParser/AsmParser.cpp In-Reply-To: References: <20110602171404.EAFA92A6C12C@llvm.org> Message-ID: <4DE7CFFF.10806@gmail.com> On 11-06-02 01:21 PM, Jim Grosbach wrote: > Hi Rafael, > > I think this does the right thing for parsing register names vs. numbers in .cfi directives for the asm parser. Seem right to you? I think so, Thanks! If I remember correctly, Roman was the one that added the support for parsing register names in cfi. > -Jim Cheers, Rafael From rafael.espindola at gmail.com Thu Jun 2 13:05:20 2011 From: rafael.espindola at gmail.com (Rafael Avila de Espindola) Date: Thu, 02 Jun 2011 14:05:20 -0400 Subject: [llvm-commits] [llvm] r132451 - in /llvm/trunk: include/llvm/MC/MCInstPrinter.h lib/MC/MCAsmStreamer.cpp lib/MC/MCInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp lib/Target/X86/InstPrinter/X86ATTInstPrinter.h lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp lib/Target/X86/InstPrinter/X86IntelInstPrinter.h In-Reply-To: <6BF75306-1630-494E-95CD-DCE5935039FC@apple.com> References: <20110602023455.800242A6C12C@llvm.org> <6BF75306-1630-494E-95CD-DCE5935039FC@apple.com> Message-ID: <4DE7D0E0.6000500@gmail.com> On 11-06-02 12:01 PM, Jim Grosbach wrote: > Hi Rafael, > > Thanks for the quick turnaround. That takes care of the crash, but > we're not quite there yet. A few questions. > > $ llvm-mc -triple armv7-apple-darwin10 t.s .section > __TEXT,__text,regular,pure_instructions t.s:1:14: error: expected > absolute expression .cfi_def_cfa r0, 8 > > It looks like the % prefix is also expected in the parsing? I see you just fixed it, thanks! > For the printer methods, getRegisterName() isn't going to work. That > expects the internal enum register number, but the CFI directives > from the streamer have the dwarf register number instead. It is mapped back to the internal numbers before passing it. I kept the interface taking a dwarf number so that the fast path (direct .o emission) stays as fast as possible. > I confess I'm a little confused at this patch in general. I was under > the (mistaken?) impression that the cfi directives referred to > registers via dwarf register number. Is that not the case? Is there > something about that solution that's insufficient? They do us dwarf register numbers... > Thanks, Jim > Cheers, Rafael From rafael.espindola at gmail.com Thu Jun 2 13:09:59 2011 From: rafael.espindola at gmail.com (Rafael Avila de Espindola) Date: Thu, 02 Jun 2011 14:09:59 -0400 Subject: [llvm-commits] [llvm] r132451 - in /llvm/trunk: include/llvm/MC/MCInstPrinter.h lib/MC/MCAsmStreamer.cpp lib/MC/MCInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp lib/Target/X86/InstPrinter/X86ATTInstPrinter.h lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp lib/Target/X86/InstPrinter/X86IntelInstPrinter.h In-Reply-To: <451B875E-438E-4BCE-B39B-C5ED6A862E72@apple.com> References: <20110602023455.800242A6C12C@llvm.org> <6BF75306-1630-494E-95CD-DCE5935039FC@apple.com> <451B875E-438E-4BCE-B39B-C5ED6A862E72@apple.com> Message-ID: <4DE7D1F7.7090003@gmail.com> > That does raise another question, though. In looking at this, I > noticed that in an old patch (121471), the TargetAsmInfo class was > introduced and it contains a pointer to a TargetRegisterInfo. That's > a layering problem, as it forces anything MC based to link in the > entire codegen backend (TargetRegisterInfo is part of the > MachineInstr layer). Can we find a better way to do this? Some > tablegenerated helper functions, perhaps? There was already a dependency, so TargetRegisterInfo looked like the smaller hack at the time. The reverse mapping is already tablegenerated and could be moved to MC. Unfortunately, there is still information that is used in MC and Codegen because of the old JIT. We could move it and break the MC -> CodeGen dependency, but the idea of changing soon to be dead code is not too attractive. Another option is just duplicating some info in MC and CodeGen for now. > -Jim Cheers, Rafael From grosbach at apple.com Thu Jun 2 13:17:40 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Jun 2011 11:17:40 -0700 Subject: [llvm-commits] [llvm] r132451 - in /llvm/trunk: include/llvm/MC/MCInstPrinter.h lib/MC/MCAsmStreamer.cpp lib/MC/MCInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp lib/Target/ARM/InstPrinter/ARMInstPrinter.h lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp lib/Target/X86/InstPrinter/X86ATTInstPrinter.h lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp lib/Target/X86/InstPrinter/X86IntelInstPrinter.h In-Reply-To: <4DE7D1F7.7090003@gmail.com> References: <20110602023455.800242A6C12C@llvm.org> <6BF75306-1630-494E-95CD-DCE5935039FC@apple.com> <451B875E-438E-4BCE-B39B-C5ED6A862E72@apple.com> <4DE7D1F7.7090003@gmail.com> Message-ID: <0ACB2106-1405-405E-BC24-00C3123DED2D@apple.com> On Jun 2, 2011, at 11:09 AM, Rafael Avila de Espindola wrote: >> That does raise another question, though. In looking at this, I >> noticed that in an old patch (121471), the TargetAsmInfo class was >> introduced and it contains a pointer to a TargetRegisterInfo. That's >> a layering problem, as it forces anything MC based to link in the >> entire codegen backend (TargetRegisterInfo is part of the >> MachineInstr layer). Can we find a better way to do this? Some >> tablegenerated helper functions, perhaps? > > There was already a dependency, so TargetRegisterInfo looked like the smaller hack at the time. > Yeah, there's unfortunately some nastiness that needs the targetmachine. The plan at this point is to work towards getting rid of that, but until then do our best not to add any additional linkages that make that process harder. > The reverse mapping is already tablegenerated and could be moved to MC. > > Unfortunately, there is still information that is used in MC and Codegen because of the old JIT. We could move it and break the MC -> CodeGen dependency, but the idea of changing soon to be dead code is not too attractive. > > Another option is just duplicating some info in MC and CodeGen for now. As long as the MC stuff has direct access without talking to the codegen layer, I'm not too concerned about the specifics, really. There's already some examples of duplicated helper functions (getARMRegisterNumbering() is the example that jumps immediately to mind, and is one that could be replaced by auto-generated bits). -Jim From eli.friedman at gmail.com Thu Jun 2 13:19:07 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 2 Jun 2011 11:19:07 -0700 Subject: [llvm-commits] [llvm] r132458 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-06-01-fildll.ll In-Reply-To: <20110602155712.0FAA32A6C12C@llvm.org> References: <20110602155712.0FAA32A6C12C@llvm.org> Message-ID: On Thu, Jun 2, 2011 at 8:57 AM, Stuart Hastings wrote: > Author: stuart > Date: Thu Jun ?2 10:57:11 2011 > New Revision: 132458 > > URL: http://llvm.org/viewvc/llvm-project?rev=132458&view=rev > Log: > Omit unnecessary stack copy when x87 input is a load. > rdar://problem/6373334 > > Added: > ? ?llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll > Modified: > ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > > Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=132458&r1=132457&r2=132458&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jun ?2 10:57:11 2011 > @@ -6700,6 +6700,11 @@ > ? DebugLoc dl = Op.getDebugLoc(); > ? unsigned Size = SrcVT.getSizeInBits()/8; > ? MachineFunction &MF = DAG.getMachineFunction(); > + > + ?SDValue Addr = Op.getOperand(0); > + ?if (Addr.getOpcode() == ISD::LOAD) > + ? ?return BuildFILD(Op, SrcVT, DAG.getEntryNode(), Addr, DAG); You're ignoring both the chain operand and chain result of the load here. This is also missing some safety checks; in particular, it doesn't check whether the load is an extload, or whether the load is volatile, or whether the load has multiple uses. -Eli > ? int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); > ? SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); > ? SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), > @@ -6723,12 +6728,18 @@ > > ? unsigned ByteSize = SrcVT.getSizeInBits()/8; > > - ?int SSFI = cast(StackSlot)->getIndex(); > - ?MachineMemOperand *MMO = > - ? ?DAG.getMachineFunction() > - ? ?.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), > - ? ? ? ? ? ? ? ? ? ? ? ? ?MachineMemOperand::MOLoad, ByteSize, ByteSize); > - > + ?FrameIndexSDNode *FI = dyn_cast(StackSlot); > + ?MachineMemOperand *MMO; > + ?if (FI) { > + ? ?int SSFI = FI->getIndex(); > + ? ?MMO = > + ? ? ?DAG.getMachineFunction() > + ? ? ?.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), > + ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineMemOperand::MOLoad, ByteSize, ByteSize); > + ?} else { > + ? ?MMO = cast(StackSlot)->getMemOperand(); > + ? ?StackSlot = StackSlot.getOperand(1); > + ?} > ? SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; > ? SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?X86ISD::FILD, DL, > > Added: llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll?rev=132458&view=auto > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll (added) > +++ llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll Thu Jun ?2 10:57:11 2011 > @@ -0,0 +1,15 @@ > +; RUN: llc %s -march=x86 > +; ModuleID = '' > +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" > +target triple = "i386-apple-macosx10.6.6" > + > +define float @f(i64* nocapture %x) nounwind readonly ssp { > +entry: > +; CHECK: movl > +; CHECK-NOT: movl > + ?%tmp1 = load i64* %x, align 4 > +; CHECK: fildll > + ?%conv = sitofp i64 %tmp1 to float > + ?%add = fadd float %conv, 1.000000e+00 > + ?ret float %add > +} > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From stoklund at 2pi.dk Thu Jun 2 13:34:01 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 02 Jun 2011 11:34:01 -0700 Subject: [llvm-commits] [llvm] r132458 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp test/CodeGen/X86/2011-06-01-fildll.ll In-Reply-To: <20110602155712.0FAA32A6C12C@llvm.org> References: <20110602155712.0FAA32A6C12C@llvm.org> Message-ID: On Jun 2, 2011, at 8:57 AM, Stuart Hastings wrote: > +; RUN: llc %s -march=x86 I think you meant: > RUN: llc < %s -march=x86 | FileCheck %s Without the stdin redirection, llc writes .s files to the test source directory. /jakob From stoklund at 2pi.dk Thu Jun 2 13:35:30 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 02 Jun 2011 18:35:30 -0000 Subject: [llvm-commits] [llvm] r132471 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp Message-ID: <20110602183530.79FA42A6C12C@llvm.org> Author: stoklund Date: Thu Jun 2 13:35:30 2011 New Revision: 132471 URL: http://llvm.org/viewvc/llvm-project?rev=132471&view=rev Log: Use RegisterClassInfo::getOrder in RAFast. This saves two virtual function calls and an Allocatable BitVector test, making RAFast run 2% faster. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=132471&r1=132470&r2=132471&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Thu Jun 2 13:35:30 2011 @@ -13,6 +13,7 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "regalloc" +#include "RegisterClassInfo.h" #include "llvm/BasicBlock.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineInstr.h" @@ -58,6 +59,7 @@ MachineRegisterInfo *MRI; const TargetRegisterInfo *TRI; const TargetInstrInfo *TII; + RegisterClassInfo RegClassInfo; // Basic block currently being allocated. MachineBasicBlock *MBB; @@ -499,14 +501,12 @@ } } - TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF); - TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF); + ArrayRef AO = RegClassInfo.getOrder(RC); // First try to find a completely free register. - for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { + for (ArrayRef::iterator I = AO.begin(), E = AO.end(); I != E; ++I) { unsigned PhysReg = *I; - if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg) && - Allocatable.test(PhysReg)) + if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg)) return assignVirtToPhysReg(LRE, PhysReg); } @@ -514,11 +514,7 @@ << RC->getName() << "\n"); unsigned BestReg = 0, BestCost = spillImpossible; - for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { - if (!Allocatable.test(*I)) { - DEBUG(dbgs() << "\tRegister " << *I << " is not allocatable.\n"); - continue; - } + for (ArrayRef::iterator I = AO.begin(), E = AO.end(); I != E; ++I) { unsigned Cost = calcSpillCost(*I); DEBUG(dbgs() << "\tRegister: " << *I << "\n"); DEBUG(dbgs() << "\tCost: " << Cost << "\n"); @@ -1048,6 +1044,7 @@ TM = &Fn.getTarget(); TRI = TM->getRegisterInfo(); TII = TM->getInstrInfo(); + RegClassInfo.runOnMachineFunction(Fn); UsedInInstr.resize(TRI->getNumRegs()); Allocatable = TRI->getAllocatableSet(*MF); From stuart at apple.com Thu Jun 2 13:44:05 2011 From: stuart at apple.com (Stuart Hastings) Date: Thu, 02 Jun 2011 18:44:05 -0000 Subject: [llvm-commits] [llvm] r132472 - /llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll Message-ID: <20110602184405.E6E782A6C12C@llvm.org> Author: stuart Date: Thu Jun 2 13:44:05 2011 New Revision: 132472 URL: http://llvm.org/viewvc/llvm-project?rev=132472&view=rev Log: Jakob pointed out a dumb omission in this test case. Thanks Jakob! Modified: llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll Modified: llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll?rev=132472&r1=132471&r2=132472&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll (original) +++ llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll Thu Jun 2 13:44:05 2011 @@ -1,4 +1,4 @@ -; RUN: llc %s -march=x86 +; RUN: llc %s -march=x86 | FileCheck %s ; ModuleID = '' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" target triple = "i386-apple-macosx10.6.6" From rdivacky at freebsd.org Thu Jun 2 13:55:16 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Thu, 2 Jun 2011 20:55:16 +0200 Subject: [llvm-commits] [llvm] r132466 - /llvm/trunk/lib/MC/MCParser/AsmParser.cpp In-Reply-To: <4DE7CFFF.10806@gmail.com> References: <20110602171404.EAFA92A6C12C@llvm.org> <4DE7CFFF.10806@gmail.com> Message-ID: <20110602185516.GA71353@freebsd.org> On Thu, Jun 02, 2011 at 02:01:35PM -0400, Rafael Avila de Espindola wrote: > On 11-06-02 01:21 PM, Jim Grosbach wrote: > >Hi Rafael, > > > >I think this does the right thing for parsing register names vs. numbers > >in .cfi directives for the asm parser. Seem right to you? > > I think so, Thanks! > > If I remember correctly, Roman was the one that added the support for > parsing register names in cfi. Looks ok to me. From aggarwa4 at illinois.edu Thu Jun 2 13:58:09 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 02 Jun 2011 18:58:09 -0000 Subject: [llvm-commits] [poolalloc] r132473 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp runtime/DynamicTypeChecks/TypeRuntime.c Message-ID: <20110602185809.3B5D22A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 2 13:58:09 2011 New Revision: 132473 URL: http://llvm.org/viewvc/llvm-project?rev=132473&view=rev Log: Clean up some functions. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132473&r1=132472&r2=132473&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Thu Jun 2 13:58:09 2011 @@ -55,7 +55,6 @@ } bool initShadow(Module &M); - bool unmapShadow(Module &M, Instruction &I); void addTypeMap(Module &M) ; bool visitCallInst(Module &M, CallInst &CI); bool visitInvokeInst(Module &M, InvokeInst &CI); Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132473&r1=132472&r2=132473&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 2 13:58:09 2011 @@ -56,6 +56,15 @@ static const Type *Int32Ty = 0; static const Type *Int64Ty = 0; static const PointerType *VoidPtrTy = 0; +static Constant *trackGlobal; +static Constant *trackArray; +static Constant *trackInitInst; +static Constant *trackUnInitInst; +static Constant *trackStoreInst; +static Constant *trackLoadInst; +static Constant *copyTypeInfo; +static Constant *RegisterArgv; +static Constant *compareTypeAndNumber; unsigned int TypeChecks::getTypeMarker(const Type * Ty) { @@ -84,6 +93,16 @@ Int64Ty = IntegerType::getInt64Ty(M.getContext()); VoidPtrTy = PointerType::getUnqual(Int8Ty); + RegisterArgv = M.getOrInsertFunction("trackArgvType", VoidTy, Int32Ty, VoidPtrTy->getPointerTo(), NULL); + trackGlobal = M.getOrInsertFunction("trackGlobal", VoidTy, VoidPtrTy, Int8Ty, Int64Ty, Int32Ty, NULL); + trackArray = M.getOrInsertFunction("trackArray", VoidTy, VoidPtrTy, Int64Ty, Int64Ty, Int32Ty, NULL); + trackInitInst = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); + trackUnInitInst = M.getOrInsertFunction("trackUnInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); + trackStoreInst = M.getOrInsertFunction("trackStoreInst", VoidTy, VoidPtrTy, Int8Ty, Int64Ty, Int32Ty, NULL); + trackLoadInst = M.getOrInsertFunction("trackLoadInst", VoidTy, VoidPtrTy, Int8Ty, Int64Ty, Int32Ty, NULL); + copyTypeInfo = M.getOrInsertFunction("copyTypeInfo", VoidTy, VoidPtrTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); + compareTypeAndNumber = M.getOrInsertFunction("compareTypeAndNumber", VoidTy, Int64Ty, Int64Ty, Int8Ty, VoidPtrTy, Int32Ty, NULL); + UsedTypes.clear(); // Reset if run multiple times. VAListFunctions.clear(); VAArgFunctions.clear(); @@ -392,8 +411,7 @@ Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI->getType()))); Args.push_back(VAMetaData); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *Func = M.getOrInsertFunction("compareTypeAndNumber", VoidTy, Int64Ty, Int64Ty, Int8Ty, VoidPtrTy, Int32Ty, NULL); - CallInst::Create(Func, Args.begin(), Args.end(), "", VI); + CallInst::Create(compareTypeAndNumber, Args.begin(), Args.end(), "", VI); } } @@ -531,14 +549,7 @@ Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(VI->getType()))); Args.push_back(VAMetaData); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *Func = M.getOrInsertFunction("compareTypeAndNumber", - VoidTy, - Int64Ty, - Int64Ty, - Int8Ty, - VoidPtrTy, - Int32Ty, NULL); - CallInst::Create(Func, Args.begin(), Args.end(), "", VI); + CallInst::Create(compareTypeAndNumber, Args.begin(), Args.end(), "", VI); } } @@ -771,8 +782,7 @@ Args.push_back(AllocSize); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); // Set the metadata for the byval argument to TOP/Initialized - Constant *F = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", InsertBefore); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", InsertBefore); registeredArguments.push_back(&*I); } } @@ -802,8 +812,7 @@ Args.push_back(BCI); Args.push_back(AllocSize); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackUnInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", Pt); + CallInst::Create(trackUnInitInst, Args.begin(), Args.end(), "", Pt); } } return true; @@ -853,8 +862,7 @@ unsigned int size = TD->getTypeStoreSize(I->getType()->getElementType()); Args.push_back(ConstantInt::get(Int64Ty, size)); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", InsertPt); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", InsertPt); continue; } if(!I->hasInitializer()) @@ -921,34 +929,24 @@ return true; } -// Initialize the shadow memory which contains the 1:1 mapping. -bool TypeChecks::unmapShadow(Module &M, Instruction &I) { - // Create the call to the runtime shadow memory unmap function and place it before any exiting instruction. - Constant *F = M.getOrInsertFunction("shadowUnmap", VoidTy, NULL); - CallInst::Create(F, "", &I); +bool TypeChecks::visitMain(Module &M, Function &MainFunc) { + if(MainFunc.arg_size() != 2) + // No need to register + return false; + + Function::arg_iterator AI = MainFunc.arg_begin(); + Value *Argc = AI; + Value *Argv = ++AI; + + Instruction *InsertPt = MainFunc.front().begin(); + std::vector fargs; + fargs.push_back (Argc); + fargs.push_back (Argv); + CallInst::Create (RegisterArgv, fargs.begin(), fargs.end(), "", InsertPt); return true; } - bool TypeChecks::visitMain(Module &M, Function &MainFunc) { - if(MainFunc.arg_size() != 2) - // No need to register - return false; - - Function::arg_iterator AI = MainFunc.arg_begin(); - Value *Argc = AI; - Value *Argv = ++AI; - - Instruction *InsertPt = MainFunc.front().begin(); - Constant * RegisterArgv = M.getOrInsertFunction("trackArgvType", VoidTy, Argc->getType(), Argv->getType(), NULL); - std::vector fargs; - fargs.push_back (Argc); - fargs.push_back (Argv); - CallInst::Create (RegisterArgv, fargs.begin(), fargs.end(), "", InsertPt); - - return true; - } - bool TypeChecks::visitGlobal(Module &M, GlobalVariable &GV, Constant *C, Instruction &I, unsigned offset) { @@ -973,8 +971,7 @@ Args.push_back(ConstantInt::get(Int64Ty, t)); Args.push_back(ConstantInt::get(Int64Ty, CA->getNumOperands())); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackGlobalArray", VoidTy, VoidPtrTy, Int64Ty, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", &I); + CallInst::Create(trackArray, Args.begin(), Args.end(), "", &I); } else if(ConstantStruct *CS = dyn_cast(C)) { // Create metadata for each field of the struct @@ -1001,8 +998,7 @@ Args.push_back(ConstantInt::get(Int64Ty, t)); Args.push_back(ConstantInt::get(Int64Ty, ATy->getNumElements())); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackGlobalArray", VoidTy, VoidPtrTy, Int64Ty, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", &I); + CallInst::Create(trackArray, Args.begin(), Args.end(), "", &I); } else if(const StructType *STy = dyn_cast(Ty)) { const StructLayout *SL = TD->getStructLayout(STy); for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { @@ -1024,8 +1020,7 @@ Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(CAZ->getType()))); Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(CAZ->getType()))); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackGlobal", VoidTy, VoidPtrTy, Int8Ty, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", &I); + CallInst::Create(trackGlobal, Args.begin(), Args.end(), "", &I); } } else { @@ -1041,8 +1036,7 @@ Args.push_back(ConstantInt::get(Int8Ty, getTypeMarker(C->getType()))); Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(C->getType()))); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackGlobal", VoidTy, VoidPtrTy, Int8Ty, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", &I); + CallInst::Create(trackGlobal, Args.begin(), Args.end(), "", &I); } return true; @@ -1092,16 +1086,14 @@ Args.push_back(BCI); Args.push_back(AllocSize); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackUnInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); + CallInst *CI = CallInst::Create(trackUnInitInst, Args.begin(), Args.end()); CI->insertAfter(BCI); std::vector Args1; Args1.push_back(BCI); Args1.push_back(AllocSize); - Args1.push_back(AI.getArraySize()); + Args1.push_back(ArraySize); Args1.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - F = M.getOrInsertFunction("trackGlobalArray", VoidTy, VoidPtrTy, Int64Ty, AI.getArraySize()->getType(), Int32Ty, NULL); - CallInst *CI_Arr = CallInst::Create(F, Args1.begin(), Args1.end()); + CallInst *CI_Arr = CallInst::Create(trackArray, Args1.begin(), Args1.end()); CI_Arr->insertAfter(CI); return true; @@ -1142,10 +1134,10 @@ std::vector Args; Args.push_back(BCI_Dest); Args.push_back(BCI_Src); - Args.push_back(I->getOperand(3)); + CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(3), Int64Ty, false, "", I); + Args.push_back(Size); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("copyTypeInfo", VoidTy, VoidPtrTy, VoidPtrTy, I->getOperand(3)->getType(), Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", I); + CallInst::Create(copyTypeInfo, Args.begin(), Args.end(), "", I); return true; } @@ -1158,10 +1150,10 @@ CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); std::vector Args; Args.push_back(BCI); - Args.push_back(I->getOperand(3)); + CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(3), Int64Ty, false, "", I); + Args.push_back(Size); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", I); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; } } else if (F->getNameStr() == std::string("__ctype_b_loc")) { @@ -1202,8 +1194,7 @@ Args.push_back(BCI); Args.push_back(ConstantInt::get(Int64Ty, t)); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", I); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; } else if(F->getNameStr() == std::string("read")) { if(EnableTypeSafeOpt) { @@ -1215,10 +1206,10 @@ BCI->insertAfter(I); std::vector Args; Args.push_back(BCI); - Args.push_back(I); + CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false, "", I); + Args.push_back(Size); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy, I->getType(), Int32Ty, NULL); - CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); + CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); CI->insertAfter(BCI); return true; } else if(F->getNameStr() == std::string("fread")) { @@ -1231,10 +1222,10 @@ BCI->insertAfter(I); std::vector Args; Args.push_back(BCI); - Args.push_back(I); + CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false, "", I); + Args.push_back(Size); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy, I->getType(), Int32Ty, NULL); - CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); + CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); CI->insertAfter(BCI); return true; } else if(F->getNameStr() == std::string("calloc")) { @@ -1247,18 +1238,18 @@ BCI->insertAfter(I); std::vector Args; Args.push_back(BCI); - Args.push_back(I->getOperand(2)); + CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(2), Int64Ty, false, "", I); + Args.push_back(Size); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy,I->getOperand(2)->getType(), Int32Ty, NULL); - CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); + CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); CI->insertAfter(BCI); std::vector Args1; Args1.push_back(BCI); - Args1.push_back(I->getOperand(2)); - Args1.push_back(I->getOperand(1)); + Args.push_back(Size); + CastInst *Num = CastInst::CreateIntegerCast(I->getOperand(1), Int64Ty, false, "", I); + Args.push_back(Num); Args1.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - F = M.getOrInsertFunction("trackGlobalArray", VoidTy, VoidPtrTy, I->getOperand(2)->getType(), I->getOperand(1)->getType(), Int32Ty, NULL); - CallInst *CI_Arr = CallInst::Create(F, Args1.begin(), Args1.end()); + CallInst *CI_Arr = CallInst::Create(trackArray, Args1.begin(), Args1.end()); CI_Arr->insertAfter(CI); return true; } else if(F->getNameStr() == std::string("realloc")) { @@ -1274,10 +1265,10 @@ std::vector Args; Args.push_back(BCI_Dest); Args.push_back(BCI_Src); - Args.push_back(I->getOperand(2)); + CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(2), Int64Ty, false, "", I); + Args.push_back(Size); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("copyTypeInfo", VoidTy, VoidPtrTy, VoidPtrTy, I->getOperand(2)->getType(), Int32Ty, NULL); - CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); + CallInst *CI = CallInst::Create(copyTypeInfo, Args.begin(), Args.end()); CI->insertAfter(BCI_Dest); return true; } else if(F->getNameStr() == std::string("fgets")) { @@ -1289,10 +1280,10 @@ CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); std::vector Args; Args.push_back(BCI); - Args.push_back(I->getOperand(2)); + CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(2), Int64Ty, false, "", I); + Args.push_back(Size); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy, I->getOperand(2)->getType(), Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", I); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; } else if(F->getNameStr() == std::string("sscanf")) { // FIXME: Need to look at the format string and check @@ -1335,8 +1326,7 @@ Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); // Create the call to the runtime check and place it before the store instruction. - Constant *F = M.getOrInsertFunction("trackStoreInst", VoidTy, VoidPtrTy, Int8Ty, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", CI); + CallInst::Create(trackStoreInst, Args.begin(), Args.end(), "", CI); return true; } @@ -1358,8 +1348,7 @@ Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); // Create the call to the runtime check and place it before the load instruction. - Constant *F = M.getOrInsertFunction("trackLoadInst", VoidTy, VoidPtrTy, Int8Ty, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", &LI); + CallInst::Create(trackLoadInst, Args.begin(), Args.end(), "", &LI); numLoadChecks++; return true; } @@ -1382,8 +1371,7 @@ Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); // Create the call to the runtime check and place it before the store instruction. - Constant *F = M.getOrInsertFunction("trackStoreInst", VoidTy, VoidPtrTy, Int8Ty, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", &SI); + CallInst::Create(trackStoreInst, Args.begin(), Args.end(), "", &SI); numStoreChecks++; return true; @@ -1407,8 +1395,7 @@ Args.push_back(BCI_Src); Args.push_back(ConstantInt::get(Int64Ty, TD->getTypeStoreSize(SI.getOperand(0)->getType()))); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - Constant *F = M.getOrInsertFunction("trackInitInst", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", &SI); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", &SI); } } @@ -1419,8 +1406,7 @@ Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); // Create the call to the runtime check and place it before the copying store instruction. - Constant *F = M.getOrInsertFunction("copyTypeInfo", VoidTy, VoidPtrTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); - CallInst::Create(F, Args.begin(), Args.end(), "", &SI); + CallInst::Create(copyTypeInfo, Args.begin(), Args.end(), "", &SI); numStoreChecks++; return true; Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=132473&r1=132472&r2=132473&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Thu Jun 2 13:58:09 2011 @@ -54,16 +54,6 @@ } /** - * Unmap the shadow memory which records the 1:1 mapping of addresses to types. - */ -void shadowUnmap() { - if (munmap(shadow_begin, SIZE) == -1) { - fprintf(stderr, "Failed to unmap the shadow memory!\n"); - fflush(stderr); - } -} - -/** * Copy arguments into a new array, and initialize * metadata for that location to TOP/initialized. */ @@ -90,7 +80,7 @@ /** * Record the type stored at ptr(of size size) and replicate it */ -void trackGlobalArray(void *ptr, uint64_t size, uint64_t count, uint32_t tag) { +void trackArray(void *ptr, uint64_t size, uint64_t count, uint32_t tag) { uintptr_t p = maskAddress(ptr); uintptr_t p1 = maskAddress(ptr); uint64_t i; From eli.friedman at gmail.com Thu Jun 2 14:11:47 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 2 Jun 2011 12:11:47 -0700 Subject: [llvm-commits] [llvm] r132472 - /llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll In-Reply-To: <20110602184405.E6E782A6C12C@llvm.org> References: <20110602184405.E6E782A6C12C@llvm.org> Message-ID: On Thu, Jun 2, 2011 at 11:44 AM, Stuart Hastings wrote: > Author: stuart > Date: Thu Jun ?2 13:44:05 2011 > New Revision: 132472 > > URL: http://llvm.org/viewvc/llvm-project?rev=132472&view=rev > Log: > Jakob pointed out a dumb omission in this test case. ?Thanks Jakob! > > Modified: > ? ?llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll > > Modified: llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll?rev=132472&r1=132471&r2=132472&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll (original) > +++ llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll Thu Jun ?2 13:44:05 2011 > @@ -1,4 +1,4 @@ > -; RUN: llc %s -march=x86 > +; RUN: llc %s -march=x86 | FileCheck %s That should be "llc < %s -march=x86 | FileCheck %s". See http://smooshlab.apple.com:8013/builders/clang-x86_64-darwin10-gcc42-RA/builds/3634/steps/run.llvm.tests/logs/LLVM%20%3A%3A%20CodeGen___X86___2011-06-01-fildll.ll . -Eli From echristo at apple.com Thu Jun 2 14:26:38 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 02 Jun 2011 19:26:38 -0000 Subject: [llvm-commits] [llvm] r132476 - /llvm/trunk/lib/VMCore/InlineAsm.cpp Message-ID: <20110602192638.0BAF62A6C12C@llvm.org> Author: echristo Date: Thu Jun 2 14:26:37 2011 New Revision: 132476 URL: http://llvm.org/viewvc/llvm-project?rev=132476&view=rev Log: Add a new parse hint for multi-letter constraints in inline asm. Testcase will come when we use it. Part of rdar://9119939 Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/InlineAsm.cpp?rev=132476&r1=132475&r2=132476&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/InlineAsm.cpp (original) +++ llvm/trunk/lib/VMCore/InlineAsm.cpp Thu Jun 2 14:26:37 2011 @@ -181,6 +181,15 @@ multipleAlternativeIndex++; pCodes = &multipleAlternatives[multipleAlternativeIndex].Codes; ++I; + } else if (*I == '^') { + // Multi-letter constraint + // These will only occur with the existing multiple alternative + // constraints and so we can use the isalpha loop below. + StringRef::iterator ConStart = I; + while (I != E && isalpha(*I)) + ++I; + pCodes->push_back(std::string(ConStart, I)); + ++I; } else { // Single letter constraint. pCodes->push_back(std::string(I, I+1)); From stuart at apple.com Thu Jun 2 14:26:50 2011 From: stuart at apple.com (Stuart Hastings) Date: Thu, 02 Jun 2011 19:26:50 -0000 Subject: [llvm-commits] [llvm] r132477 - /llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll Message-ID: <20110602192650.227862A6C12C@llvm.org> Author: stuart Date: Thu Jun 2 14:26:49 2011 New Revision: 132477 URL: http://llvm.org/viewvc/llvm-project?rev=132477&view=rev Log: Andy pointed out a dumb omission in this test case. Thanks Andy! Modified: llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll Modified: llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll?rev=132477&r1=132476&r2=132477&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll (original) +++ llvm/trunk/test/CodeGen/X86/2011-06-01-fildll.ll Thu Jun 2 14:26:49 2011 @@ -1,4 +1,4 @@ -; RUN: llc %s -march=x86 | FileCheck %s +; RUN: llc < %s -march=x86 | FileCheck %s ; ModuleID = '' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" target triple = "i386-apple-macosx10.6.6" From rdivacky at freebsd.org Thu Jun 2 14:44:12 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Thu, 2 Jun 2011 21:44:12 +0200 Subject: [llvm-commits] [PATCH]: PowerPC64, wrong mixing of CTR and CTR8 Message-ID: <20110602194412.GA75670@freebsd.org> Hi, On PowerPC64 when lowering BRIND (indirect branch) for PPC64 the "mtctr" instruction is pointed to a "wrong" bctr instruction. Ie. one that uses "CTR" instead of "CTR8". This causes http://llvm.org/bugs/show_bug.cgi?id=8487 . CTR8 is also omitted when seting HasCTRSet in hazard recognizer. And also wrong CTR variant is used when emitting indirect call on PPC64. The attached patch fixes all of that (+ test). We're now able to compile stuff like "ls" or "sh" on FreeBSD/PowerPC. OK to commit? roman -------------- next part -------------- A non-text attachment was scrubbed... Name: powerpc64.patch Type: text/x-diff Size: 4172 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110602/f2e5e994/attachment.bin From aggarwa4 at illinois.edu Thu Jun 2 14:53:41 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Thu, 02 Jun 2011 19:53:41 -0000 Subject: [llvm-commits] [poolalloc] r132478 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110602195341.9F3FE2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 2 14:53:41 2011 New Revision: 132478 URL: http://llvm.org/viewvc/llvm-project?rev=132478&view=rev Log: Insert the size instruction after the call instruction. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132478&r1=132477&r2=132478&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 2 14:53:41 2011 @@ -1206,7 +1206,8 @@ BCI->insertAfter(I); std::vector Args; Args.push_back(BCI); - CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false, "", I); + CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false); + Size->insertAfter(I); Args.push_back(Size); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); @@ -1222,7 +1223,8 @@ BCI->insertAfter(I); std::vector Args; Args.push_back(BCI); - CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false, "", I); + CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false); + Size->insertAfter(I); Args.push_back(Size); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); From rafael.espindola at gmail.com Thu Jun 2 14:57:47 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 02 Jun 2011 19:57:47 -0000 Subject: [llvm-commits] [llvm] r132479 - in /llvm/trunk: lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/isint.ll test/CodeGen/X86/pr9127.ll test/CodeGen/X86/setoeq.ll Message-ID: <20110602195748.0AA3B2A6C12C@llvm.org> Author: rafael Date: Thu Jun 2 14:57:47 2011 New Revision: 132479 URL: http://llvm.org/viewvc/llvm-project?rev=132479&view=rev Log: Revert 132424 to fix PR10068. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/isint.ll llvm/trunk/test/CodeGen/X86/pr9127.ll llvm/trunk/test/CodeGen/X86/setoeq.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132479&r1=132478&r2=132479&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jun 2 14:57:47 2011 @@ -1759,14 +1759,13 @@ if (NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && Op.getOperand(0).getValueType().isFloatingPoint() && !Op.getOperand(0).getValueType().isVector()) { - bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); - bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); - if (OpVTLegal || i32Legal) { - EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; + if (isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32)) { + EVT Ty = (isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType())) ? + Op.getValueType() : MVT::i32; // Make a FGETSIGN + SHL to move the sign bit into the appropriate // place. We expect the SHL to be eliminated by other optimizations. SDValue Sign = TLO.DAG.getNode(ISD::FGETSIGN, dl, Ty, Op.getOperand(0)); - if (!OpVTLegal) + if (Ty != Op.getValueType()) Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); unsigned ShVal = Op.getValueType().getSizeInBits()-1; SDValue ShAmt = TLO.DAG.getConstant(ShVal, Op.getValueType()); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=132479&r1=132478&r2=132479&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jun 2 14:57:47 2011 @@ -9402,8 +9402,6 @@ case X86ISD::UCOMI: return "X86ISD::UCOMI"; case X86ISD::SETCC: return "X86ISD::SETCC"; case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; - case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; - case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; case X86ISD::CMOV: return "X86ISD::CMOV"; case X86ISD::BRCOND: return "X86ISD::BRCOND"; case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; @@ -11681,88 +11679,12 @@ } -// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) -// where both setccs reference the same FP CMP, and rewrite for CMPEQSS -// and friends. Likewise for OR -> CMPNEQSS. -static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, - TargetLowering::DAGCombinerInfo &DCI, - const X86Subtarget *Subtarget) { - unsigned opcode; - - // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but - // we're requiring SSE2 for both. - if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { - SDValue N0 = N->getOperand(0); - SDValue N1 = N->getOperand(1); - SDValue CMP = N0->getOperand(1); - SDValue CMP0 = CMP->getOperand(0); - SDValue CMP1 = CMP->getOperand(1); - EVT VT = CMP0.getValueType(); - DebugLoc DL = N->getDebugLoc(); - - if (VT == MVT::f32 || VT == MVT::f64) { - bool ExpectingFlags = false; - // Check for any users that want flags: - for (SDNode::use_iterator UI = N->use_begin(), - UE = N->use_end(); - !ExpectingFlags && UI != UE; ++UI) - switch (UI->getOpcode()) { - default: - case ISD::BR_CC: - case ISD::BRCOND: - case ISD::SELECT: - ExpectingFlags = true; - break; - case ISD::CopyToReg: - case ISD::SIGN_EXTEND: - case ISD::ZERO_EXTEND: - case ISD::ANY_EXTEND: - break; - } - - if (!ExpectingFlags) { - enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); - enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); - - if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { - X86::CondCode tmp = cc0; - cc0 = cc1; - cc1 = tmp; - } - - if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || - (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { - bool is64BitFP = (CMP0.getValueType() == MVT::f64); - X86ISD::NodeType NTOperator = is64BitFP ? - X86ISD::FSETCCsd : X86ISD::FSETCCss; - // FIXME: need symbolic constants for these magic numbers. - // See X86ATTInstPrinter.cpp:printSSECC(). - unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; - SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP0, CMP1, - DAG.getConstant(x86cc, MVT::i8)); - SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, - OnesOrZeroesF); - SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, - DAG.getConstant(1, MVT::i32)); - SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); - return OneBitOfTruth; - } - } - } - } - return SDValue(); -} - static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) { if (DCI.isBeforeLegalizeOps()) return SDValue(); - SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); - if (R.getNode()) - return R; - // Want to form PANDN nodes, in the hopes of then easily combining them with // OR and AND nodes to form PBLEND/PSIGN. EVT VT = N->getValueType(0); @@ -11792,10 +11714,6 @@ if (DCI.isBeforeLegalizeOps()) return SDValue(); - SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); - if (R.getNode()) - return R; - EVT VT = N->getValueType(0); if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) return SDValue(); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=132479&r1=132478&r2=132479&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Jun 2 14:57:47 2011 @@ -94,11 +94,6 @@ // one's or all zero's. SETCC_CARRY, // R = carry_bit ? ~0 : 0 - /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. - /// Operands are two FP values to compare; result is a mask of - /// 0s or 1s. Generally DTRT for C/C++ with NaNs. - FSETCCss, FSETCCsd, - /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, /// result in an integer GPR. Needs masking for scalar result. FGETSIGNx86, Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=132479&r1=132478&r2=132479&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Thu Jun 2 14:57:47 2011 @@ -41,8 +41,6 @@ def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; -def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>; -def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>; def X86pshufb : SDNode<"X86ISD::PSHUFB", SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>>; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=132479&r1=132478&r2=132479&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Thu Jun 2 14:57:47 2011 @@ -23,9 +23,6 @@ def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; -def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; -def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; - def SDTX86Cmov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=132479&r1=132478&r2=132479&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jun 2 14:57:47 2011 @@ -1056,37 +1056,13 @@ XD, VEX_4V; } -let Constraints = "$src1 = $dst" in { -def CMPSSrr : SIi8<0xC2, MRMSrcReg, - (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc), - "cmp${cc}ss\t{$src2, $dst|$dst, $src2}", - [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS; -def CMPSSrm : SIi8<0xC2, MRMSrcMem, - (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc), - "cmp${cc}ss\t{$src2, $dst|$dst, $src2}", - [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS; -def CMPSDrr : SIi8<0xC2, MRMSrcReg, - (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc), - "cmp${cc}sd\t{$src2, $dst|$dst, $src2}", - [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD; -def CMPSDrm : SIi8<0xC2, MRMSrcMem, - (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc), - "cmp${cc}sd\t{$src2, $dst|$dst, $src2}", - [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD; -} let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in { -def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg, - (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2), - "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS; -def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem, - (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2), - "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS; -def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg, - (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2), - "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD; -def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem, - (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2), - "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD; + defm CMPSS : sse12_cmp_scalar, XS; + defm CMPSD : sse12_cmp_scalar, XD; } multiclass sse12_cmp_scalar_int %t +; RUN: not grep cmp %t +; RUN: not grep xor %t +; RUN: grep jne %t | count 1 +; RUN: grep jp %t | count 1 +; RUN: grep setnp %t | count 1 +; RUN: grep sete %t | count 1 +; RUN: grep and %t | count 1 +; RUN: grep cvt %t | count 4 define i32 @isint_return(double %d) nounwind { -; CHECK-NOT: xor -; CHECK: cvt %i = fptosi double %d to i32 -; CHECK-NEXT: cvt %e = sitofp i32 %i to double -; CHECK: cmpeqsd %c = fcmp oeq double %d, %e -; CHECK-NEXT: movd -; CHECK-NEXT: andl %z = zext i1 %c to i32 ret i32 %z } @@ -17,14 +19,9 @@ declare void @foo() define void @isint_branch(double %d) nounwind { -; CHECK: cvt %i = fptosi double %d to i32 -; CHECK-NEXT: cvt %e = sitofp i32 %i to double -; CHECK: ucomisd %c = fcmp oeq double %d, %e -; CHECK-NEXT: jne -; CHECK-NEXT: jp br i1 %c, label %true, label %false true: call void @foo() Modified: llvm/trunk/test/CodeGen/X86/pr9127.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr9127.ll?rev=132479&r1=132478&r2=132479&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr9127.ll (original) +++ llvm/trunk/test/CodeGen/X86/pr9127.ll Thu Jun 2 14:57:47 2011 @@ -10,4 +10,4 @@ } ; test that the load is folded. -; CHECK: cmpeqsd (%{{rdi|rdx}}), %xmm0 +; CHECK: ucomisd (%{{rdi|rdx}}), %xmm0 Modified: llvm/trunk/test/CodeGen/X86/setoeq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setoeq.ll?rev=132479&r1=132478&r2=132479&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/setoeq.ll (original) +++ llvm/trunk/test/CodeGen/X86/setoeq.ll Thu Jun 2 14:57:47 2011 @@ -1,4 +1,5 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s +; RUN: llc < %s -march=x86 | grep set | count 2 +; RUN: llc < %s -march=x86 | grep and define zeroext i8 @t(double %x) nounwind readnone { entry: @@ -6,16 +7,5 @@ %1 = sitofp i32 %0 to double ; [#uses=1] %2 = fcmp oeq double %1, %x ; [#uses=1] %retval12 = zext i1 %2 to i8 ; [#uses=1] -; CHECK: cmpeqsd - ret i8 %retval12 -} - -define zeroext i8 @u(double %x) nounwind readnone { -entry: - %0 = fptosi double %x to i32 ; [#uses=1] - %1 = sitofp i32 %0 to double ; [#uses=1] - %2 = fcmp une double %1, %x ; [#uses=1] - %retval12 = zext i1 %2 to i8 ; [#uses=1] -; CHECK: cmpneqsd ret i8 %retval12 } From rafael.espindola at gmail.com Thu Jun 2 15:02:48 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 02 Jun 2011 20:02:48 -0000 Subject: [llvm-commits] [llvm] r132482 - /llvm/trunk/test/CodeGen/X86/pr10068.ll Message-ID: <20110602200248.7CB482A6C12C@llvm.org> Author: rafael Date: Thu Jun 2 15:02:48 2011 New Revision: 132482 URL: http://llvm.org/viewvc/llvm-project?rev=132482&view=rev Log: Add test for PR10068. Added: llvm/trunk/test/CodeGen/X86/pr10068.ll Added: llvm/trunk/test/CodeGen/X86/pr10068.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr10068.ll?rev=132482&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr10068.ll (added) +++ llvm/trunk/test/CodeGen/X86/pr10068.ll Thu Jun 2 15:02:48 2011 @@ -0,0 +1,22 @@ +; RUN: llc < %s -march=x86 + +define void @foobar() { +entry: + %sub.i = trunc i64 undef to i32 + %shr80.i = ashr i32 %sub.i, 16 + %add82.i = add nsw i32 %shr80.i, 1 + %notlhs.i = icmp slt i32 %shr80.i, undef + %notrhs.i = icmp sgt i32 %add82.i, -1 + %or.cond.not.i = and i1 %notrhs.i, %notlhs.i + %cmp154.i = icmp slt i32 0, undef + %or.cond406.i = and i1 %or.cond.not.i, %cmp154.i + %or.cond406.not.i = xor i1 %or.cond406.i, true + %or.cond407.i = or i1 undef, %or.cond406.not.i + br i1 %or.cond407.i, label %if.then158.i, label %if.end163.i + +if.then158.i: + ret void + +if.end163.i: ; preds = %if.end67.i + ret void +} From dpatel at apple.com Thu Jun 2 15:07:12 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 02 Jun 2011 20:07:12 -0000 Subject: [llvm-commits] [llvm] r132483 - in /llvm/trunk: lib/CodeGen/ScheduleDAGInstrs.cpp lib/CodeGen/ScheduleDAGInstrs.h test/CodeGen/ARM/debug-info-branch-folding.ll Message-ID: <20110602200712.446422A6C12E@llvm.org> Author: dpatel Date: Thu Jun 2 15:07:12 2011 New Revision: 132483 URL: http://llvm.org/viewvc/llvm-project?rev=132483&view=rev Log: During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint! Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=132483&r1=132482&r2=132483&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Thu Jun 2 15:07:12 2011 @@ -35,8 +35,9 @@ const MachineDominatorTree &mdt) : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), InstrItins(mf.getTarget().getInstrItineraryData()), - Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()), LoopRegs(MLI, MDT) { - DbgValueVec.clear(); + Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()), + FirstDbgValue(0), LoopRegs(MLI, MDT) { + DbgValues.clear(); } /// Run - perform scheduling. @@ -200,11 +201,6 @@ std::map AliasMemDefs, NonAliasMemDefs; std::map > AliasMemUses, NonAliasMemUses; - // Keep track of dangling debug references to registers. - std::vector > - DanglingDebugValue(TRI->getNumRegs(), - std::make_pair(static_cast(0), 0)); - // Check to see if the scheduler cares about latencies. bool UnitLatencies = ForceUnitLatencies(); @@ -214,7 +210,8 @@ // Remove any stale debug info; sometimes BuildSchedGraph is called again // without emitting the info from the previous call. - DbgValueVec.clear(); + DbgValues.clear(); + FirstDbgValue = NULL; // Model data dependencies between instructions being scheduled and the // ExitSU. @@ -225,19 +222,20 @@ } // Walk the list of instructions, from bottom moving up. + MachineInstr *PrevMI = NULL; for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin; MII != MIE; --MII) { MachineInstr *MI = prior(MII); - // DBG_VALUE does not have SUnit's built, so just remember these for later - // reinsertion. + if (MI && PrevMI) { + DbgValues.push_back(std::make_pair(PrevMI, MI)); + PrevMI = NULL; + } + if (MI->isDebugValue()) { - if (MI->getNumOperands()==3 && MI->getOperand(0).isReg() && - MI->getOperand(0).getReg()) - DanglingDebugValue[MI->getOperand(0).getReg()] = - std::make_pair(MI, DbgValueVec.size()); - DbgValueVec.push_back(MI); + PrevMI = MI; continue; } + const TargetInstrDesc &TID = MI->getDesc(); assert(!TID.isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); @@ -261,12 +259,6 @@ assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!"); - if (MO.isDef() && DanglingDebugValue[Reg].first!=0) { - SU->DbgInstrList.push_back(DanglingDebugValue[Reg].first); - DbgValueVec[DanglingDebugValue[Reg].second] = 0; - DanglingDebugValue[Reg] = std::make_pair((MachineInstr*)0, 0); - } - std::vector &UseList = Uses[Reg]; // Defs are push in the order they are visited and never reordered. std::vector &DefList = Defs[Reg]; @@ -561,6 +553,8 @@ } } } + if (PrevMI) + FirstDbgValue = PrevMI; for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) { Defs[i].clear(); @@ -670,13 +664,9 @@ BB->remove(I); } - // First reinsert any remaining debug_values; these are either constants, - // or refer to live-in registers. The beginning of the block is the right - // place for the latter. The former might reasonably be placed elsewhere - // using some kind of ordering algorithm, but right now it doesn't matter. - for (int i = DbgValueVec.size()-1; i>=0; --i) - if (DbgValueVec[i]) - BB->insert(InsertPos, DbgValueVec[i]); + // If first instruction was a DBG_VALUE then put it back. + if (FirstDbgValue) + BB->insert(InsertPos, FirstDbgValue); // Then re-insert them according to the given schedule. for (unsigned i = 0, e = Sequence.size(); i != e; i++) { @@ -694,15 +684,18 @@ // Update the Begin iterator, as the first instruction in the block // may have been scheduled later. - if (!DbgValueVec.empty()) { - for (int i = DbgValueVec.size()-1; i>=0; --i) - if (DbgValueVec[i]!=0) { - Begin = DbgValueVec[DbgValueVec.size()-1]; - break; - } - } else if (!Sequence.empty()) + if (!Sequence.empty()) Begin = Sequence[0]->getInstr(); - DbgValueVec.clear(); + // Reinsert any remaining debug_values. + for (std::vector >::iterator + DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) { + std::pair P = *prior(DI); + MachineInstr *DbgValue = P.first; + MachineInstr *OrigPrivMI = P.second; + BB->insertAfter(OrigPrivMI, DbgValue); + } + DbgValues.clear(); + FirstDbgValue = NULL; return BB; } Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h?rev=132483&r1=132482&r2=132483&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h Thu Jun 2 15:07:12 2011 @@ -110,9 +110,9 @@ std::vector > Defs; std::vector > Uses; - /// DbgValueVec - Remember DBG_VALUEs that refer to a particular - /// register. - std::vectorDbgValueVec; + /// DbgValues - Remember instruction that preceeds DBG_VALUE. + std::vector >DbgValues; + MachineInstr *FirstDbgValue; /// PendingLoads - Remember where unknown loads are after the most recent /// unknown store, as we iterate. As with Defs and Uses, this is here Modified: llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll?rev=132483&r1=132482&r2=132483&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll (original) +++ llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll Thu Jun 2 15:07:12 2011 @@ -2,9 +2,11 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" target triple = "thumbv7-apple-macosx10.6.7" -;CHECK: Ltmp1: -;CHECK-NEXT: @DEBUG_VALUE: x <- Q4+0 -;CHECK-NEXT: adr r0, #LCPI0_0 +;CHECK: vadd.f32 q4, q8, q8 +;CHECK-NEXT: Ltmp +;CHECK-NEXT: @DEBUG_VALUE: y <- Q4+0 +;CHECK-NEXT: @DEBUG_VALUE: x <- Q4+0 + @.str = external constant [13 x i8] From eli.friedman at gmail.com Thu Jun 2 16:24:42 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 02 Jun 2011 21:24:42 -0000 Subject: [llvm-commits] [llvm] r132485 - in /llvm/trunk: lib/Transforms/Scalar/MemCpyOptimizer.cpp test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll Message-ID: <20110602212442.7B3072A6C12C@llvm.org> Author: efriedma Date: Thu Jun 2 16:24:42 2011 New Revision: 132485 URL: http://llvm.org/viewvc/llvm-project?rev=132485&view=rev Log: PR10067: Add missing safety check to call return transformation in MemCpyOpt::processStore. If something accesses the dest of the "copy" between the call and the copy, the performCallSlotOptzn transformation is not valid. Added: llvm/trunk/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Modified: llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp?rev=132485&r1=132484&r2=132485&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/MemCpyOptimizer.cpp Thu Jun 2 16:24:42 2011 @@ -488,11 +488,28 @@ // a memcpy. if (LoadInst *LI = dyn_cast(SI->getOperand(0))) { if (!LI->isVolatile() && LI->hasOneUse()) { - MemDepResult dep = MD->getDependency(LI); + MemDepResult ldep = MD->getDependency(LI); CallInst *C = 0; - if (dep.isClobber() && !isa(dep.getInst())) - C = dyn_cast(dep.getInst()); - + if (ldep.isClobber() && !isa(ldep.getInst())) + C = dyn_cast(ldep.getInst()); + + if (C) { + // Check that nothing touches the dest of the "copy" between + // the call and the store. + MemDepResult sdep = MD->getDependency(SI); + if (!sdep.isNonLocal()) { + bool FoundCall = false; + for (BasicBlock::iterator I = SI, E = sdep.getInst(); I != E; --I) { + if (&*I == C) { + FoundCall = true; + break; + } + } + if (!FoundCall) + C = 0; + } + } + if (C) { bool changed = performCallSlotOptzn(LI, SI->getPointerOperand()->stripPointerCasts(), Added: llvm/trunk/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll?rev=132485&view=auto ============================================================================== --- llvm/trunk/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll (added) +++ llvm/trunk/test/Transforms/MemCpyOpt/2011-06-02-CallSlotOverwritten.ll Thu Jun 2 16:24:42 2011 @@ -0,0 +1,36 @@ +; RUN: opt < %s -basicaa -memcpyopt -S | FileCheck %s +; PR10067 +; Make sure the call+copy isn't optimized in such a way that +; %ret ends up with the wrong value. + +target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32" +target triple = "i386-apple-darwin10" + +%struct1 = type { i32, i32 } +%struct2 = type { %struct1, i8* } + +declare void @bar(%struct1* nocapture sret %agg.result) nounwind + +define i32 @foo() nounwind { + %x = alloca %struct1, align 8 + %y = alloca %struct2, align 8 + call void @bar(%struct1* sret %x) nounwind +; CHECK: call void @bar(%struct1* sret %x) + + %gepn1 = getelementptr inbounds %struct2* %y, i32 0, i32 0, i32 0 + store i32 0, i32* %gepn1, align 8 + %gepn2 = getelementptr inbounds %struct2* %y, i32 0, i32 0, i32 1 + store i32 0, i32* %gepn2, align 4 + + %bit1 = bitcast %struct1* %x to i64* + %bit2 = bitcast %struct2* %y to i64* + %load = load i64* %bit1, align 8 + store i64 %load, i64* %bit2, align 8 + +; CHECK: %load = load i64* %bit1, align 8 +; CHECK: store i64 %load, i64* %bit2, align 8 + + %gep1 = getelementptr %struct2* %y, i32 0, i32 0, i32 0 + %ret = load i32* %gep1 + ret i32 %ret +} From tonic at nondot.org Thu Jun 2 16:25:24 2011 From: tonic at nondot.org (Tanya Lattner) Date: Thu, 02 Jun 2011 21:25:24 -0000 Subject: [llvm-commits] [llvm] r132486 - /llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Message-ID: <20110602212524.B22D72A6C12C@llvm.org> Author: tbrethou Date: Thu Jun 2 16:25:24 2011 New Revision: 132486 URL: http://llvm.org/viewvc/llvm-project?rev=132486&view=rev Log: Fix encoding for VEXTdf. Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrNEON.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrNEON.td?rev=132486&r1=132485&r2=132486&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrNEON.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrNEON.td Thu Jun 2 16:25:24 2011 @@ -4703,8 +4703,9 @@ let Inst{9-8} = 0b00; } def VEXTdf : VEXTd<"vext", "32", v2f32> { - let Inst{11} = index{0}; - let Inst{10-8} = 0b000; + let Inst{11-10} = index{1-0}; + let Inst{9-8} = 0b00; + } def VEXTq8 : VEXTq<"vext", "8", v16i8> { From dpatel at apple.com Thu Jun 2 16:26:52 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 02 Jun 2011 21:26:52 -0000 Subject: [llvm-commits] [llvm] r132487 - in /llvm/trunk/lib/CodeGen: AggressiveAntiDepBreaker.cpp AggressiveAntiDepBreaker.h AntiDepBreaker.h CriticalAntiDepBreaker.cpp CriticalAntiDepBreaker.h PostRASchedulerList.cpp ScheduleDAGInstrs.cpp ScheduleDAGInstrs.h Message-ID: <20110602212652.C3C832A6C12C@llvm.org> Author: dpatel Date: Thu Jun 2 16:26:52 2011 New Revision: 132487 URL: http://llvm.org/viewvc/llvm-project?rev=132487&view=rev Log: Update DBG_VALUEs while breaking anti dependencies. Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h llvm/trunk/lib/CodeGen/AntiDepBreaker.h llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=132487&r1=132486&r2=132487&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Thu Jun 2 16:26:52 2011 @@ -719,7 +719,9 @@ const std::vector& SUnits, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, - unsigned InsertPosIndex) { + unsigned InsertPosIndex, + DbgValueVector &DbgValues) { + std::vector &KillIndices = State->GetKillIndices(); std::vector &DefIndices = State->GetDefIndices(); std::multimap& @@ -923,14 +925,10 @@ // sure to update that as well. const SUnit *SU = MISUnitMap[Q->second.Operand->getParent()]; if (!SU) continue; - for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i) { - MachineInstr *DI = SU->DbgInstrList[i]; - assert (DI->getNumOperands()==3 && DI->getOperand(0).isReg() && - DI->getOperand(0).getReg() - && "Non register dbg_value attached to SUnit!"); - if (DI->getOperand(0).getReg() == AntiDepReg) - DI->getOperand(0).setReg(NewReg); - } + for (DbgValueVector::iterator DVI = DbgValues.begin(), + DVE = DbgValues.end(); DVI != DVE; ++DVI) + if (DVI->second == Q->second.Operand->getParent()) + UpdateDbgValue(DVI->first, AntiDepReg, NewReg); } // We just went back in time and modified history; the Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=132487&r1=132486&r2=132487&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Thu Jun 2 16:26:52 2011 @@ -146,7 +146,8 @@ unsigned BreakAntiDependencies(const std::vector& SUnits, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, - unsigned InsertPosIndex); + unsigned InsertPosIndex, + DbgValueVector &DbgValues); /// Observe - Update liveness information to account for the current /// instruction, which will not be scheduled. Modified: llvm/trunk/lib/CodeGen/AntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AntiDepBreaker.h?rev=132487&r1=132486&r2=132487&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/AntiDepBreaker.h Thu Jun 2 16:26:52 2011 @@ -30,6 +30,9 @@ /// anti-dependencies. class AntiDepBreaker { public: + typedef std::vector > + DbgValueVector; + virtual ~AntiDepBreaker(); /// Start - Initialize anti-dep breaking for a new basic block. @@ -40,9 +43,10 @@ /// the number of anti-dependencies broken. /// virtual unsigned BreakAntiDependencies(const std::vector& SUnits, - MachineBasicBlock::iterator Begin, - MachineBasicBlock::iterator End, - unsigned InsertPosIndex) =0; + MachineBasicBlock::iterator Begin, + MachineBasicBlock::iterator End, + unsigned InsertPosIndex, + DbgValueVector &DbgValues) = 0; /// Observe - Update liveness information to account for the current /// instruction, which will not be scheduled. @@ -52,6 +56,14 @@ /// Finish - Finish anti-dep breaking for a basic block. virtual void FinishBlock() =0; + + /// UpdateDbgValue - Update DBG_VALUE if dependency breaker is updating + /// other machine instruction to use NewReg. + void UpdateDbgValue(MachineInstr *MI, unsigned OldReg, unsigned NewReg) { + assert (MI->isDebugValue() && "MI is not DBG_VALUE!"); + if (MI && MI->getOperand(0).isReg() && MI->getOperand(0).getReg() == OldReg) + MI->getOperand(0).setReg(NewReg); + } }; } Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=132487&r1=132486&r2=132487&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Thu Jun 2 16:26:52 2011 @@ -421,7 +421,8 @@ BreakAntiDependencies(const std::vector& SUnits, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, - unsigned InsertPosIndex) { + unsigned InsertPosIndex, + DbgValueVector &DbgValues) { // The code below assumes that there is at least one instruction, // so just duck out immediately if the block is empty. if (SUnits.empty()) return 0; @@ -628,14 +629,10 @@ // as well. const SUnit *SU = MISUnitMap[Q->second->getParent()]; if (!SU) continue; - for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i) { - MachineInstr *DI = SU->DbgInstrList[i]; - assert (DI->getNumOperands()==3 && DI->getOperand(0).isReg() && - DI->getOperand(0).getReg() - && "Non register dbg_value attached to SUnit!"); - if (DI->getOperand(0).getReg() == AntiDepReg) - DI->getOperand(0).setReg(NewReg); - } + for (DbgValueVector::iterator DVI = DbgValues.begin(), + DVE = DbgValues.end(); DVI != DVE; ++DVI) + if (DVI->second == Q->second->getParent()) + UpdateDbgValue(DVI->first, AntiDepReg, NewReg); } // We just went back in time and modified history; the Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h?rev=132487&r1=132486&r2=132487&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.h Thu Jun 2 16:26:52 2011 @@ -79,7 +79,8 @@ unsigned BreakAntiDependencies(const std::vector& SUnits, MachineBasicBlock::iterator Begin, MachineBasicBlock::iterator End, - unsigned InsertPosIndex); + unsigned InsertPosIndex, + DbgValueVector &DbgValues); /// Observe - Update liveness information to account for the current /// instruction, which will not be scheduled. Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=132487&r1=132486&r2=132487&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original) +++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Thu Jun 2 16:26:52 2011 @@ -304,7 +304,7 @@ if (AntiDepBreak != NULL) { unsigned Broken = AntiDepBreak->BreakAntiDependencies(SUnits, Begin, InsertPos, - InsertPosIndex); + InsertPosIndex, DbgValues); if (Broken != 0) { // We made changes. Update the dependency graph. Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=132487&r1=132486&r2=132487&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Thu Jun 2 16:26:52 2011 @@ -36,7 +36,7 @@ : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), InstrItins(mf.getTarget().getInstrItineraryData()), Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()), - FirstDbgValue(0), LoopRegs(MLI, MDT) { + LoopRegs(MLI, MDT), FirstDbgValue(0) { DbgValues.clear(); } Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h?rev=132487&r1=132486&r2=132487&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h Thu Jun 2 16:26:52 2011 @@ -110,10 +110,6 @@ std::vector > Defs; std::vector > Uses; - /// DbgValues - Remember instruction that preceeds DBG_VALUE. - std::vector >DbgValues; - MachineInstr *FirstDbgValue; - /// PendingLoads - Remember where unknown loads are after the most recent /// unknown store, as we iterate. As with Defs and Uses, this is here /// to minimize construction/destruction. @@ -128,6 +124,14 @@ /// SmallSet LoopLiveInRegs; + protected: + + /// DbgValues - Remember instruction that preceeds DBG_VALUE. + typedef std::vector > + DbgValueVector; + DbgValueVector DbgValues; + MachineInstr *FirstDbgValue; + public: MachineBasicBlock::iterator Begin; // The beginning of the range to // be scheduled. The range extends From dpatel at apple.com Thu Jun 2 16:31:00 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 02 Jun 2011 21:31:00 -0000 Subject: [llvm-commits] [llvm] r132488 - in /llvm/trunk: include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/ScheduleDAGInstrs.cpp Message-ID: <20110602213100.8E0AC2A6C12C@llvm.org> Author: dpatel Date: Thu Jun 2 16:31:00 2011 New Revision: 132488 URL: http://llvm.org/viewvc/llvm-project?rev=132488&view=rev Log: Remove dead code. Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=132488&r1=132487&r2=132488&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Thu Jun 2 16:31:00 2011 @@ -265,7 +265,6 @@ bool isCloned : 1; // True if this node has been cloned. Sched::Preference SchedulingPref; // Scheduling preference. - SmallVector DbgInstrList; // dbg_values referencing this. private: bool isDepthCurrent : 1; // True if Depth is current. bool isHeightCurrent : 1; // True if Height is current. Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=132488&r1=132487&r2=132488&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Thu Jun 2 16:31:00 2011 @@ -670,16 +670,11 @@ // Then re-insert them according to the given schedule. for (unsigned i = 0, e = Sequence.size(); i != e; i++) { - SUnit *SU = Sequence[i]; - if (!SU) { + if (SUnit *SU = Sequence[i]) + BB->insert(InsertPos, SU->getInstr()); + else // Null SUnit* is a noop. EmitNoop(); - continue; - } - - BB->insert(InsertPos, SU->getInstr()); - for (unsigned i = 0, e = SU->DbgInstrList.size() ; i < e ; ++i) - BB->insert(InsertPos, SU->DbgInstrList[i]); } // Update the Begin iterator, as the first instruction in the block From eli.friedman at gmail.com Thu Jun 2 16:58:15 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Thu, 2 Jun 2011 14:58:15 -0700 Subject: [llvm-commits] [llvm] r132471 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp In-Reply-To: <20110602183530.79FA42A6C12C@llvm.org> References: <20110602183530.79FA42A6C12C@llvm.org> Message-ID: On Thu, Jun 2, 2011 at 11:35 AM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Thu Jun ?2 13:35:30 2011 > New Revision: 132471 > > URL: http://llvm.org/viewvc/llvm-project?rev=132471&view=rev > Log: > Use RegisterClassInfo::getOrder in RAFast. > > This saves two virtual function calls and an Allocatable BitVector test, > making RAFast run 2% faster. This appears to be responsible for the failures on http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA . -Eli > Modified: > ? ?llvm/trunk/lib/CodeGen/RegAllocFast.cpp > > Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=132471&r1=132470&r2=132471&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) > +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Thu Jun ?2 13:35:30 2011 > @@ -13,6 +13,7 @@ > ?//===----------------------------------------------------------------------===// > > ?#define DEBUG_TYPE "regalloc" > +#include "RegisterClassInfo.h" > ?#include "llvm/BasicBlock.h" > ?#include "llvm/CodeGen/MachineFunctionPass.h" > ?#include "llvm/CodeGen/MachineInstr.h" > @@ -58,6 +59,7 @@ > ? ? MachineRegisterInfo *MRI; > ? ? const TargetRegisterInfo *TRI; > ? ? const TargetInstrInfo *TII; > + ? ?RegisterClassInfo RegClassInfo; > > ? ? // Basic block currently being allocated. > ? ? MachineBasicBlock *MBB; > @@ -499,14 +501,12 @@ > ? ? } > ? } > > - ?TargetRegisterClass::iterator AOB = RC->allocation_order_begin(*MF); > - ?TargetRegisterClass::iterator AOE = RC->allocation_order_end(*MF); > + ?ArrayRef AO = RegClassInfo.getOrder(RC); > > ? // First try to find a completely free register. > - ?for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { > + ?for (ArrayRef::iterator I = AO.begin(), E = AO.end(); I != E; ++I) { > ? ? unsigned PhysReg = *I; > - ? ?if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg) && > - ? ? ? ?Allocatable.test(PhysReg)) > + ? ?if (PhysRegState[PhysReg] == regFree && !UsedInInstr.test(PhysReg)) > ? ? ? return assignVirtToPhysReg(LRE, PhysReg); > ? } > > @@ -514,11 +514,7 @@ > ? ? ? ? ? ? ? ?<< RC->getName() << "\n"); > > ? unsigned BestReg = 0, BestCost = spillImpossible; > - ?for (TargetRegisterClass::iterator I = AOB; I != AOE; ++I) { > - ? ?if (!Allocatable.test(*I)) { > - ? ? ?DEBUG(dbgs() << "\tRegister " << *I << " is not allocatable.\n"); > - ? ? ?continue; > - ? ?} > + ?for (ArrayRef::iterator I = AO.begin(), E = AO.end(); I != E; ++I) { > ? ? unsigned Cost = calcSpillCost(*I); > ? ? DEBUG(dbgs() << "\tRegister: " << *I << "\n"); > ? ? DEBUG(dbgs() << "\tCost: " << Cost << "\n"); > @@ -1048,6 +1044,7 @@ > ? TM = &Fn.getTarget(); > ? TRI = TM->getRegisterInfo(); > ? TII = TM->getInstrInfo(); > + ?RegClassInfo.runOnMachineFunction(Fn); > > ? UsedInInstr.resize(TRI->getNumRegs()); > ? Allocatable = TRI->getAllocatableSet(*MF); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From isanbard at gmail.com Thu Jun 2 17:11:17 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 02 Jun 2011 22:11:17 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r132493 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Message-ID: <20110602221118.0A9962A6C12C@llvm.org> Author: void Date: Thu Jun 2 17:11:17 2011 New Revision: 132493 URL: http://llvm.org/viewvc/llvm-project?rev=132493&view=rev Log: Don't mark everything as having 'unnamed_addr'. It doesn't make much sense for something that has external linkage. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=132493&r1=132492&r2=132493&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Jun 2 17:11:17 2011 @@ -1375,7 +1375,9 @@ // Set the initializer. GV->setInitializer(Init); - GV->setUnnamedAddr(true); + if (GV->hasHiddenVisibility() || GV->hasInternalLinkage() || + GV->hasPrivateLinkage()) + GV->setUnnamedAddr(true); } /// reset_type_and_initializer_llvm - Change the type and initializer for @@ -1396,7 +1398,9 @@ // Temporary to avoid infinite recursion (see comments emit_global_to_llvm) GV->setInitializer(UndefValue::get(GV->getType()->getElementType())); - GV->setUnnamedAddr(true); + if (GV->hasHiddenVisibility() || GV->hasInternalLinkage() || + GV->hasPrivateLinkage()) + GV->setUnnamedAddr(true); // Convert the initializer over. Constant *Init = TreeConstantToLLVM::Convert(DECL_INITIAL(decl)); @@ -1411,7 +1415,6 @@ GV->isConstant(), GV->getLinkage(), 0, GV->getName()); - NGV->setUnnamedAddr(true); NGV->setVisibility(GV->getVisibility()); NGV->setSection(GV->getSection()); NGV->setAlignment(GV->getAlignment()); @@ -1420,12 +1423,14 @@ changeLLVMConstant(GV, NGV); delete GV; SET_DECL_LLVM(decl, NGV); + if (NGV->hasHiddenVisibility() || NGV->hasInternalLinkage() || + NGV->hasPrivateLinkage()) + NGV->setUnnamedAddr(true); GV = NGV; } // Set the initializer. GV->setInitializer(Init); - GV->setUnnamedAddr(true); } /// emit_global_to_llvm - Emit the specified VAR_DECL or aggregate CONST_DECL to @@ -1477,7 +1482,9 @@ // this can happen for things like void *G = &G; // GV->setInitializer(UndefValue::get(GV->getType()->getElementType())); - GV->setUnnamedAddr(true); + if (GV->hasHiddenVisibility() || GV->hasInternalLinkage() || + GV->hasPrivateLinkage()) + GV->setUnnamedAddr(true); Init = TreeConstantToLLVM::Convert(DECL_INITIAL(decl)); } @@ -1491,7 +1498,6 @@ GV->isConstant(), GlobalValue::ExternalLinkage, 0, GV->getName()); - NGV->setUnnamedAddr(true); GV->replaceAllUsesWith(TheFolder->CreateBitCast(NGV, GV->getType())); changeLLVMConstant(GV, NGV); delete GV; @@ -1501,7 +1507,9 @@ // Set the initializer. GV->setInitializer(Init); - GV->setUnnamedAddr(true); + if (GV->hasHiddenVisibility() || GV->hasInternalLinkage() || + GV->hasPrivateLinkage()) + GV->setUnnamedAddr(true); // Set thread local (TLS) if (TREE_CODE(decl) == VAR_DECL && DECL_THREAD_LOCAL_P(decl)) @@ -1555,6 +1563,9 @@ #endif /* TARGET_ADJUST_LLVM_LINKAGE */ handleVisibility(decl, GV); + if (GV->hasHiddenVisibility() || GV->hasInternalLinkage() || + GV->hasPrivateLinkage()) + GV->setUnnamedAddr(true); // Set the section for the global. if (TREE_CODE(decl) == VAR_DECL) { @@ -1803,7 +1814,6 @@ if (Name[0] == 0) { // Global has no name. GV = new GlobalVariable(*TheModule, Ty, false, GlobalValue::ExternalLinkage, 0, ""); - GV->setUnnamedAddr(true); // Check for external weak linkage. if (DECL_EXTERNAL(decl) && DECL_WEAK(decl)) @@ -1814,6 +1824,9 @@ #endif /* TARGET_ADJUST_LLVM_LINKAGE */ handleVisibility(decl, GV); + if (GV->hasHiddenVisibility() || GV->hasInternalLinkage() || + GV->hasPrivateLinkage()) + GV->setUnnamedAddr(true); } else { // If the global has a name, prevent multiple vars with the same name from // being created. @@ -1823,7 +1836,6 @@ GV = new GlobalVariable(*TheModule, Ty, false, GlobalValue::ExternalLinkage, 0, Name); - GV->setUnnamedAddr(true); // Check for external weak linkage. if (DECL_EXTERNAL(decl) && DECL_WEAK(decl)) GV->setLinkage(GlobalValue::ExternalWeakLinkage); @@ -1834,6 +1846,10 @@ handleVisibility(decl, GV); + if (GV->hasHiddenVisibility() || GV->hasInternalLinkage() || + GV->hasPrivateLinkage()) + GV->setUnnamedAddr(true); + // If GV got renamed, then there is already an object with this name in // the symbol table. If this happens, the old one must be a forward // decl, just replace it with a cast of the new one. From isanbard at gmail.com Thu Jun 2 17:11:49 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 02 Jun 2011 22:11:49 -0000 Subject: [llvm-commits] [llvm] r132494 - /llvm/trunk/test/FrontendC/pr4349.c Message-ID: <20110602221149.5D3AA2A6C12C@llvm.org> Author: void Date: Thu Jun 2 17:11:49 2011 New Revision: 132494 URL: http://llvm.org/viewvc/llvm-project?rev=132494&view=rev Log: Update for r132493 change. Modified: llvm/trunk/test/FrontendC/pr4349.c Modified: llvm/trunk/test/FrontendC/pr4349.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/pr4349.c?rev=132494&r1=132493&r2=132494&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/pr4349.c (original) +++ llvm/trunk/test/FrontendC/pr4349.c Thu Jun 2 17:11:49 2011 @@ -16,22 +16,22 @@ { void *ptr; }; -// CHECK: @svars1 = unnamed_addr global [1 x %struct.svar] [%struct.svar { i8* bitcast (%struct.cpu* @cpu to i8*) }] +// CHECK: @svars1 = global [1 x %struct.svar] [%struct.svar { i8* bitcast (%struct.cpu* @cpu to i8*) }] struct svar svars1[] = { { &((cpu.pc).w[0]) } }; -// CHECK: @svars2 = unnamed_addr global [1 x %struct.svar] [%struct.svar { i8* getelementptr ([2 x i8]* bitcast (%struct.cpu* @cpu to [2 x i8]*), i{{[0-9]+}} 0, i{{[0-9]+}} 1) }] +// CHECK: @svars2 = global [1 x %struct.svar] [%struct.svar { i8* getelementptr ([2 x i8]* bitcast (%struct.cpu* @cpu to [2 x i8]*), i{{[0-9]+}} 0, i{{[0-9]+}} 1) }] struct svar svars2[] = { { &((cpu.pc).b[0][1]) } }; -// CHECK: @svars3 = unnamed_addr global [1 x %struct.svar] [%struct.svar { i8* bitcast (i16* getelementptr ([2 x i16]* bitcast (%struct.cpu* @cpu to [2 x i16]*), i{{[0-9]+}} 0, i{{[0-9]+}} 1) to i8*) }] +// CHECK: @svars3 = global [1 x %struct.svar] [%struct.svar { i8* bitcast (i16* getelementptr ([2 x i16]* bitcast (%struct.cpu* @cpu to [2 x i16]*), i{{[0-9]+}} 0, i{{[0-9]+}} 1) to i8*) }] struct svar svars3[] = { { &((cpu.pc).w[1]) } }; -// CHECK: @svars4 = unnamed_addr global [1 x %struct.svar] [%struct.svar { i8* getelementptr ([2 x [2 x i8]]* bitcast (%struct.cpu* @cpu to [2 x [2 x i8]]*), i{{[0-9]+}} 0, i{{[0-9]+}} 1, i{{[0-9]+}} 1) }] +// CHECK: @svars4 = global [1 x %struct.svar] [%struct.svar { i8* getelementptr ([2 x [2 x i8]]* bitcast (%struct.cpu* @cpu to [2 x [2 x i8]]*), i{{[0-9]+}} 0, i{{[0-9]+}} 1, i{{[0-9]+}} 1) }] struct svar svars4[] = { { &((cpu.pc).b[1][1]) } From isanbard at gmail.com Thu Jun 2 17:12:42 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 02 Jun 2011 22:12:42 -0000 Subject: [llvm-commits] [llvm] r132495 - /llvm/trunk/test/FrontendC/unnamed-addr.c Message-ID: <20110602221242.6757D2A6C12C@llvm.org> Author: void Date: Thu Jun 2 17:12:42 2011 New Revision: 132495 URL: http://llvm.org/viewvc/llvm-project?rev=132495&view=rev Log: Testcase for r132493. Added: llvm/trunk/test/FrontendC/unnamed-addr.c Added: llvm/trunk/test/FrontendC/unnamed-addr.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/unnamed-addr.c?rev=132495&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/unnamed-addr.c (added) +++ llvm/trunk/test/FrontendC/unnamed-addr.c Thu Jun 2 17:12:42 2011 @@ -0,0 +1,91 @@ +// RUN: %llvmgcc -S %s -o - | FileCheck %s +// +typedef struct __TestResult TestResult; +typedef struct __TestResult* TestResultRef; + +typedef struct __TestImplement TestImplement; +typedef struct __TestImplement* TestImplementRef; + +typedef char*(*TestNameFunction)(void*); +typedef void(*TestRunFunction)(void*,TestResult*); +typedef int(*TestCountTestCasesFunction)(void*); + +struct __TestImplement { + TestNameFunction name; + TestRunFunction run; + TestCountTestCasesFunction countTestCases; +}; + +typedef struct __Test Test; +typedef struct __Test* TestRef; + +struct __Test { + TestImplement* isa; +}; + +typedef struct __TestCase TestCase; +typedef struct __TestCase* TestCaseRef; + +struct __TestCase { + TestImplement* isa; + const char *name; + void(*setUp)(void); + void(*tearDown)(void); + void(*runTest)(void); +}; + +extern const TestImplement TestCaseImplement; + +typedef struct __TestFixture TestFixture; +typedef struct __TestFixture* TestFixtureRef; + +struct __TestFixture { + const char *name; + void(*test)(void); +}; + +typedef struct __TestCaller TestCaller; +typedef struct __TestCaller* TestCallerRef; + +struct __TestCaller { + TestImplement* isa; + const char *name; + void(*setUp)(void); + void(*tearDown)(void); + int numberOfFixtuers; + TestFixture *fixtuers; +}; + +extern const TestImplement TestCallerImplement; + +void PassToFunction(const TestImplement*); + +const char* TestCaller_name(TestCaller* self) { + return self->name; +} + +void TestCaller_run(TestCaller* self,TestResult* result) { + TestCase cs = { (TestImplement*)&TestCaseImplement, 0, 0, 0, 0, }; + int i; + cs.setUp = self->setUp; + cs.tearDown = self->tearDown; + for (i=0; inumberOfFixtuers; i++) { + cs.name = self->fixtuers[i].name; + cs.runTest = self->fixtuers[i].test; + ((Test*)(void *)&cs)->isa->run((void *)&cs,result); + } +} + +int TestCaller_countTestCases(TestCaller* self) { + PassToFunction(&TestCallerImplement); + return self->numberOfFixtuers; +} + +// CHECK: @C.0.1526 = internal unnamed_addr constant +// CHECK-NOT: @TestCaseImplement = external unnamed_addr constant %struct.TestImplement +// CHECK: @TestCaseImplement = external constant %struct.TestImplement +const TestImplement TestCallerImplement = { + (TestNameFunction)TestCaller_name, + (TestRunFunction)TestCaller_run, + (TestCountTestCasesFunction)TestCaller_countTestCases, +}; From stoklund at 2pi.dk Thu Jun 2 17:22:43 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 02 Jun 2011 22:22:43 -0000 Subject: [llvm-commits] [llvm] r132500 - in /llvm/trunk/lib/CodeGen: RegisterClassInfo.cpp RegisterClassInfo.h Message-ID: <20110602222243.E81CA2A6C12D@llvm.org> Author: stoklund Date: Thu Jun 2 17:22:43 2011 New Revision: 132500 URL: http://llvm.org/viewvc/llvm-project?rev=132500&view=rev Log: Just use a SmallVector. I was confused whether new uint8_t[] would zero-initialize the returned array, and it seems that so is gcc-4.0. This should fix the test failures on darwin 9. Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp llvm/trunk/lib/CodeGen/RegisterClassInfo.h Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp?rev=132500&r1=132499&r2=132500&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Thu Jun 2 17:22:43 2011 @@ -39,7 +39,8 @@ if (Update || CSR != CalleeSaved) { // Build a CSRNum map. Every CSR alias gets an entry pointing to the last // overlapping CSR. - CSRNum.reset(new uint8_t[TRI->getNumRegs()]()); + CSRNum.clear(); + CSRNum.resize(TRI->getNumRegs(), 0); for (unsigned N = 0; unsigned Reg = CSR[N]; ++N) for (const unsigned *AS = TRI->getOverlaps(Reg); unsigned Alias = *AS; ++AS) Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.h?rev=132500&r1=132499&r2=132500&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.h (original) +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.h Thu Jun 2 17:22:43 2011 @@ -51,7 +51,7 @@ const unsigned *CalleeSaved; // Map register number to CalleeSaved index + 1; - OwningArrayPtr CSRNum; + SmallVector CSRNum; // Reserved registers in the current MF. BitVector Reserved; From isanbard at gmail.com Thu Jun 2 17:26:15 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 02 Jun 2011 22:26:15 -0000 Subject: [llvm-commits] [llvm] r132504 - in /llvm/trunk/test: FrontendC++/unnamed-addr.cpp FrontendC/unnamed-addr.c Message-ID: <20110602222615.7723B2A6C12C@llvm.org> Author: void Date: Thu Jun 2 17:26:15 2011 New Revision: 132504 URL: http://llvm.org/viewvc/llvm-project?rev=132504&view=rev Log: This should have been a C++ testcase. Added: llvm/trunk/test/FrontendC++/unnamed-addr.cpp - copied, changed from r132495, llvm/trunk/test/FrontendC/unnamed-addr.c Removed: llvm/trunk/test/FrontendC/unnamed-addr.c Copied: llvm/trunk/test/FrontendC++/unnamed-addr.cpp (from r132495, llvm/trunk/test/FrontendC/unnamed-addr.c) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/unnamed-addr.cpp?p2=llvm/trunk/test/FrontendC%2B%2B/unnamed-addr.cpp&p1=llvm/trunk/test/FrontendC/unnamed-addr.c&r1=132495&r2=132504&rev=132504&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/unnamed-addr.c (original) +++ llvm/trunk/test/FrontendC++/unnamed-addr.cpp Thu Jun 2 17:26:15 2011 @@ -1,5 +1,6 @@ -// RUN: %llvmgcc -S %s -o - | FileCheck %s +// RUN: %llvmgxx -S %s -o - | FileCheck %s // +extern "C" { typedef struct __TestResult TestResult; typedef struct __TestResult* TestResultRef; @@ -57,6 +58,7 @@ }; extern const TestImplement TestCallerImplement; +} void PassToFunction(const TestImplement*); @@ -81,7 +83,7 @@ return self->numberOfFixtuers; } -// CHECK: @C.0.1526 = internal unnamed_addr constant +// CHECK: @_ZZ14TestCaller_runP12__TestCallerP12__TestResultE3C.0 = internal unnamed_addr constant // CHECK-NOT: @TestCaseImplement = external unnamed_addr constant %struct.TestImplement // CHECK: @TestCaseImplement = external constant %struct.TestImplement const TestImplement TestCallerImplement = { Removed: llvm/trunk/test/FrontendC/unnamed-addr.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/unnamed-addr.c?rev=132503&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/unnamed-addr.c (original) +++ llvm/trunk/test/FrontendC/unnamed-addr.c (removed) @@ -1,91 +0,0 @@ -// RUN: %llvmgcc -S %s -o - | FileCheck %s -// -typedef struct __TestResult TestResult; -typedef struct __TestResult* TestResultRef; - -typedef struct __TestImplement TestImplement; -typedef struct __TestImplement* TestImplementRef; - -typedef char*(*TestNameFunction)(void*); -typedef void(*TestRunFunction)(void*,TestResult*); -typedef int(*TestCountTestCasesFunction)(void*); - -struct __TestImplement { - TestNameFunction name; - TestRunFunction run; - TestCountTestCasesFunction countTestCases; -}; - -typedef struct __Test Test; -typedef struct __Test* TestRef; - -struct __Test { - TestImplement* isa; -}; - -typedef struct __TestCase TestCase; -typedef struct __TestCase* TestCaseRef; - -struct __TestCase { - TestImplement* isa; - const char *name; - void(*setUp)(void); - void(*tearDown)(void); - void(*runTest)(void); -}; - -extern const TestImplement TestCaseImplement; - -typedef struct __TestFixture TestFixture; -typedef struct __TestFixture* TestFixtureRef; - -struct __TestFixture { - const char *name; - void(*test)(void); -}; - -typedef struct __TestCaller TestCaller; -typedef struct __TestCaller* TestCallerRef; - -struct __TestCaller { - TestImplement* isa; - const char *name; - void(*setUp)(void); - void(*tearDown)(void); - int numberOfFixtuers; - TestFixture *fixtuers; -}; - -extern const TestImplement TestCallerImplement; - -void PassToFunction(const TestImplement*); - -const char* TestCaller_name(TestCaller* self) { - return self->name; -} - -void TestCaller_run(TestCaller* self,TestResult* result) { - TestCase cs = { (TestImplement*)&TestCaseImplement, 0, 0, 0, 0, }; - int i; - cs.setUp = self->setUp; - cs.tearDown = self->tearDown; - for (i=0; inumberOfFixtuers; i++) { - cs.name = self->fixtuers[i].name; - cs.runTest = self->fixtuers[i].test; - ((Test*)(void *)&cs)->isa->run((void *)&cs,result); - } -} - -int TestCaller_countTestCases(TestCaller* self) { - PassToFunction(&TestCallerImplement); - return self->numberOfFixtuers; -} - -// CHECK: @C.0.1526 = internal unnamed_addr constant -// CHECK-NOT: @TestCaseImplement = external unnamed_addr constant %struct.TestImplement -// CHECK: @TestCaseImplement = external constant %struct.TestImplement -const TestImplement TestCallerImplement = { - (TestNameFunction)TestCaller_name, - (TestRunFunction)TestCaller_run, - (TestCountTestCasesFunction)TestCaller_countTestCases, -}; From dpatel at apple.com Thu Jun 2 17:46:58 2011 From: dpatel at apple.com (Devang Patel) Date: Thu, 02 Jun 2011 22:46:58 -0000 Subject: [llvm-commits] [llvm] r132505 - /llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp Message-ID: <20110602224659.067462A6C12C@llvm.org> Author: dpatel Date: Thu Jun 2 17:46:58 2011 New Revision: 132505 URL: http://llvm.org/viewvc/llvm-project?rev=132505&view=rev Log: Preserve line number information while converting Invoke into a Call. Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp Modified: llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp?rev=132505&r1=132504&r2=132505&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/SimplifyCFGPass.cpp Thu Jun 2 17:46:58 2011 @@ -96,6 +96,7 @@ NewCall->takeName(II); NewCall->setCallingConv(II->getCallingConv()); NewCall->setAttributes(II->getAttributes()); + NewCall->setDebugLoc(II->getDebugLoc()); II->replaceAllUsesWith(NewCall); // Follow the call by a branch to the normal destination. From stoklund at 2pi.dk Thu Jun 2 18:07:20 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 02 Jun 2011 23:07:20 -0000 Subject: [llvm-commits] [llvm] r132508 - in /llvm/trunk: include/llvm/Target/Target.td include/llvm/Target/TargetRegisterInfo.h lib/CodeGen/MachineRegisterInfo.cpp lib/Target/TargetRegisterInfo.cpp utils/TableGen/CodeGenRegisters.h utils/TableGen/CodeGenTarget.cpp utils/TableGen/RegisterInfoEmitter.cpp Message-ID: <20110602230720.D7DDC2A6C12C@llvm.org> Author: stoklund Date: Thu Jun 2 18:07:20 2011 New Revision: 132508 URL: http://llvm.org/viewvc/llvm-project?rev=132508&view=rev Log: Make it possible to have unallocatable register classes. Some register classes are only used for instruction operand constraints. They should never be used for virtual registers. Previously, those register classes were given an empty allocation order, but now you can say 'let isAllocatable=0' in the register class definition. TableGen calculates if a register is part of any allocatable register class, and makes that information available in TargetRegisterDesc::inAllocatableClass. The goal here is to eliminate use cases for overriding allocation_order_* methods. Modified: llvm/trunk/include/llvm/Target/Target.td llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp llvm/trunk/lib/Target/TargetRegisterInfo.cpp llvm/trunk/utils/TableGen/CodeGenRegisters.h llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=132508&r1=132507&r2=132508&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Thu Jun 2 18:07:20 2011 @@ -128,6 +128,11 @@ // dags: (RegClass SubRegIndex, SubRegindex, ...) list SubRegClasses = []; + // isAllocatable - Specify that the register class can be used for virtual + // registers and register allocation. Some register classes are only used to + // model instruction operand constraints, and should have isAllocatable = 0. + bit isAllocatable = 1; + // MethodProtos/MethodBodies - These members can be used to insert arbitrary // code into a generated register class. The normal usage of this is to // overload virtual methods. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=132508&r1=132507&r2=132508&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu Jun 2 18:07:20 2011 @@ -47,6 +47,7 @@ const unsigned *SubRegs; // Sub-register set, described above const unsigned *SuperRegs; // Super-register set, described above unsigned CostPerUse; // Extra cost of instructions using register. + bool inAllocatableClass; // Register belongs to an allocatable regclass. }; class TargetRegisterClass { @@ -66,6 +67,7 @@ const sc_iterator SuperRegClasses; const unsigned RegSize, Alignment; // Size & Alignment of register in bytes const int CopyCost; + const bool Allocatable; const iterator RegsBegin, RegsEnd; DenseSet RegSet; public: @@ -76,11 +78,12 @@ const TargetRegisterClass * const *supcs, const TargetRegisterClass * const *subregcs, const TargetRegisterClass * const *superregcs, - unsigned RS, unsigned Al, int CC, + unsigned RS, unsigned Al, int CC, bool Allocable, iterator RB, iterator RE) : ID(id), Name(name), VTs(vts), SubClasses(subcs), SuperClasses(supcs), SubRegClasses(subregcs), SuperRegClasses(superregcs), - RegSize(RS), Alignment(Al), CopyCost(CC), RegsBegin(RB), RegsEnd(RE) { + RegSize(RS), Alignment(Al), CopyCost(CC), Allocatable(Allocable), + RegsBegin(RB), RegsEnd(RE) { for (iterator I = RegsBegin, E = RegsEnd; I != E; ++I) RegSet.insert(*I); } @@ -268,6 +271,10 @@ /// this class. A negative number means the register class is very expensive /// to copy e.g. status flag register classes. int getCopyCost() const { return CopyCost; } + + /// isAllocatable - Return true if this register class may be used to create + /// virtual registers. + bool isAllocatable() const { return Allocatable; } }; Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=132508&r1=132507&r2=132508&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Thu Jun 2 18:07:20 2011 @@ -79,6 +79,8 @@ unsigned MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ assert(RegClass && "Cannot create register without RegClass!"); + assert(RegClass->isAllocatable() && + "Virtual register RegClass must be allocatable."); // New virtual register number. unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=132508&r1=132507&r2=132508&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Thu Jun 2 18:07:20 2011 @@ -96,7 +96,8 @@ } else { for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I) - getAllocatableSetForRC(MF, *I, Allocatable); + if ((*I)->isAllocatable()) + getAllocatableSetForRC(MF, *I, Allocatable); } // Mask out the reserved registers Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.h?rev=132508&r1=132507&r2=132508&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenRegisters.h (original) +++ llvm/trunk/utils/TableGen/CodeGenRegisters.h Thu Jun 2 18:07:20 2011 @@ -43,6 +43,7 @@ unsigned SpillSize; unsigned SpillAlignment; int CopyCost; + bool Allocatable; // Map SubRegIndex -> RegisterClass DenseMap SubRegClasses; std::string MethodProtos, MethodBodies; Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=132508&r1=132507&r2=132508&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Thu Jun 2 18:07:20 2011 @@ -289,6 +289,7 @@ SpillSize = Size ? Size : EVT(VTs[0]).getSizeInBits(); SpillAlignment = R->getValueAsInt("Alignment"); CopyCost = R->getValueAsInt("CopyCost"); + Allocatable = R->getValueAsBit("isAllocatable"); MethodBodies = R->getValueAsCode("MethodBodies"); MethodProtos = R->getValueAsCode("MethodProtos"); } Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=132508&r1=132507&r2=132508&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Thu Jun 2 18:07:20 2011 @@ -342,24 +342,24 @@ OS << "namespace llvm {\n\n"; - // Start out by emitting each of the register classes... to do this, we build - // a set of registers which belong to a register class, this is to ensure that - // each register is only in a single register class. - // + // Start out by emitting each of the register classes. const std::vector &RegisterClasses = Target.getRegisterClasses(); + // Collect all registers belonging to any allocatable class. + std::set AllocatableRegs; + // Loop over all of the register classes... emitting each one. OS << "namespace { // Register classes...\n"; - // RegClassesBelongedTo - Keep track of which register classes each reg - // belongs to. - std::multimap RegClassesBelongedTo; - // Emit the register enum value arrays for each RegisterClass for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { const CodeGenRegisterClass &RC = RegisterClasses[rc]; + // Collect allocatable registers. + if (RC.Allocatable) + AllocatableRegs.insert(RC.Elements.begin(), RC.Elements.end()); + // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName(); @@ -370,9 +370,6 @@ for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { Record *Reg = RC.Elements[i]; OS << getQualifiedName(Reg) << ", "; - - // Keep track of which regclasses this register is in. - RegClassesBelongedTo.insert(std::make_pair(Reg, &RC)); } OS << "\n };\n\n"; } @@ -568,6 +565,7 @@ << RC.SpillSize/8 << ", " << RC.SpillAlignment/8 << ", " << RC.CopyCost << ", " + << RC.Allocatable << ", " << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size() << ") {}\n"; } @@ -842,7 +840,7 @@ } OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; - OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n"; + OS << " { \"NOREG\",\t0,\t0,\t0,\t0,\t0 },\n"; // Now that register alias and sub-registers sets have been emitted, emit the // register descriptors now. @@ -858,7 +856,8 @@ OS << Reg.getName() << "_SuperRegsSet,\t"; else OS << "Empty_SuperRegsSet,\t"; - OS << Reg.CostPerUse << " },\n"; + OS << Reg.CostPerUse << ",\t" + << int(AllocatableRegs.count(Reg.TheDef)) << " },\n"; } OS << " };\n"; // End of register descriptors... From stoklund at 2pi.dk Thu Jun 2 18:07:24 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 02 Jun 2011 23:07:24 -0000 Subject: [llvm-commits] [llvm] r132509 - in /llvm/trunk/lib/Target: ARM/ARMRegisterInfo.td X86/X86RegisterInfo.td XCore/XCoreRegisterInfo.td Message-ID: <20110602230724.B5D7B2A6C12D@llvm.org> Author: stoklund Date: Thu Jun 2 18:07:24 2011 New Revision: 132509 URL: http://llvm.org/viewvc/llvm-project?rev=132509&view=rev Log: Flag unallocatable register classes instead of giving them empty allocation orders. Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td llvm/trunk/lib/Target/X86/X86RegisterInfo.td llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=132509&r1=132508&r2=132509&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Thu Jun 2 18:07:24 2011 @@ -540,4 +540,6 @@ } // Condition code registers. -def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]>; +def CCR : RegisterClass<"ARM", [i32], 32, [CPSR]> { + let isAllocatable = 0; +} Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=132509&r1=132508&r2=132509&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Thu Jun 2 18:07:24 2011 @@ -681,15 +681,7 @@ // for transforming FPn allocations to STn registers) def RST : RegisterClass<"X86", [f80, f64, f32], 32, [ST0, ST1, ST2, ST3, ST4, ST5, ST6, ST7]> { - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - RSTClass::iterator - RSTClass::allocation_order_end(const MachineFunction &MF) const { - return begin(); - } - }]; + let isAllocatable = 0; } // Generic vector registers: VR64 and VR128. @@ -742,15 +734,5 @@ // Status flags registers. def CCR : RegisterClass<"X86", [i32], 32, [EFLAGS]> { let CopyCost = -1; // Don't allow copying of status registers. - - // EFLAGS is not allocatable. - let MethodProtos = [{ - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - CCRClass::iterator - CCRClass::allocation_order_end(const MachineFunction &MF) const { - return allocation_order_begin(MF); - } - }]; + let isAllocatable = 0; } Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td?rev=132509&r1=132508&r2=132509&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.td Thu Jun 2 18:07:24 2011 @@ -70,22 +70,7 @@ }]; } -def RRegs : RegisterClass<"XCore", [i32], 32, - // Reserved - [CP, DP, SP, LR]> { - let MethodProtos = [{ - iterator allocation_order_begin(const MachineFunction &MF) const; - iterator allocation_order_end(const MachineFunction &MF) const; - }]; - let MethodBodies = [{ - RRegsClass::iterator - RRegsClass::allocation_order_begin(const MachineFunction &MF) const { - return begin(); - } - RRegsClass::iterator - RRegsClass::allocation_order_end(const MachineFunction &MF) const { - // No allocatable registers - return begin(); - } - }]; +// Reserved +def RRegs : RegisterClass<"XCore", [i32], 32, [CP, DP, SP, LR]> { + let isAllocatable = 0; } From echristo at apple.com Thu Jun 2 18:16:43 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 02 Jun 2011 23:16:43 -0000 Subject: [llvm-commits] [llvm] r132510 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMISelLowering.h lib/Target/CellSPU/SPUISelLowering.cpp lib/Target/CellSPU/SPUISelLowering.h lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCISelLowering.h lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h Message-ID: <20110602231643.A85F82A6C12C@llvm.org> Author: echristo Date: Thu Jun 2 18:16:42 2011 New Revision: 132510 URL: http://llvm.org/viewvc/llvm-project?rev=132510&view=rev Log: Have LowerOperandForConstraint handle multiple character constraints. Part of rdar://9119939 Modified: llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=132510&r1=132509&r2=132510&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Thu Jun 2 18:16:42 2011 @@ -1449,7 +1449,7 @@ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. - virtual void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, + virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector &Ops, SelectionDAG &DAG) const; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=132510&r1=132509&r2=132510&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Thu Jun 2 18:16:42 2011 @@ -5936,7 +5936,7 @@ if (OpInfo.ConstraintType == TargetLowering::C_Other) { std::vector Ops; - TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], + TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, Ops, DAG); if (Ops.empty()) report_fatal_error("Invalid operand for inline asm constraint '" + Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132510&r1=132509&r2=132510&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Thu Jun 2 18:16:42 2011 @@ -2650,9 +2650,13 @@ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. void TargetLowering::LowerAsmOperandForConstraint(SDValue Op, - char ConstraintLetter, + std::string &Constraint, std::vector &Ops, SelectionDAG &DAG) const { + + if (Constraint.length() > 1) return; + + char ConstraintLetter = Constraint[0]; switch (ConstraintLetter) { default: break; case 'X': // Allows any operand; labels (basic block) use this. @@ -3091,7 +3095,7 @@ assert(OpInfo.Codes[i].size() == 1 && "Unhandled multi-letter 'other' constraint"); std::vector ResultOps; - TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i][0], + TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], ResultOps, *DAG); if (!ResultOps.empty()) { BestType = CType; Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=132510&r1=132509&r2=132510&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 2 18:16:42 2011 @@ -7376,12 +7376,16 @@ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, - char Constraint, + std::string &Constraint, std::vector&Ops, SelectionDAG &DAG) const { SDValue Result(0, 0); - switch (Constraint) { + // Currently only support length 1 constraints. + if (Constraint.length() != 1) return; + + char ConstraintLetter = Constraint[0]; + switch (ConstraintLetter) { default: break; case 'I': case 'J': case 'K': case 'L': case 'M': case 'N': case 'O': @@ -7396,7 +7400,7 @@ if (CVal != CVal64) return; - switch (Constraint) { + switch (ConstraintLetter) { case 'I': if (Subtarget->isThumb1Only()) { // This must be a constant between 0 and 255, for ADD Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=132510&r1=132509&r2=132510&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Thu Jun 2 18:16:42 2011 @@ -315,7 +315,7 @@ /// true it means one of the asm constraint of the inline asm instruction /// being processed is 'm'. virtual void LowerAsmOperandForConstraint(SDValue Op, - char ConstraintLetter, + std::string &Constraint, std::vector &Ops, SelectionDAG &DAG) const; Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp?rev=132510&r1=132509&r2=132510&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.cpp Thu Jun 2 18:16:42 2011 @@ -3204,11 +3204,11 @@ // LowerAsmOperandForConstraint void SPUTargetLowering::LowerAsmOperandForConstraint(SDValue Op, - char ConstraintLetter, + std::string &Constraint, std::vector &Ops, SelectionDAG &DAG) const { // Default, for the time being, to the base class handler - TargetLowering::LowerAsmOperandForConstraint(Op, ConstraintLetter, Ops, DAG); + TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); } /// isLegalAddressImmediate - Return true if the integer value can be used Modified: llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h?rev=132510&r1=132509&r2=132510&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUISelLowering.h Thu Jun 2 18:16:42 2011 @@ -141,7 +141,7 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; - void LowerAsmOperandForConstraint(SDValue Op, char ConstraintLetter, + void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint, std::vector &Ops, SelectionDAG &DAG) const; Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=132510&r1=132509&r2=132510&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Thu Jun 2 18:16:42 2011 @@ -5439,10 +5439,16 @@ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. -void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter, +void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, + std::string &Constraint, std::vector&Ops, SelectionDAG &DAG) const { SDValue Result(0,0); + + // Only support length 1 constraints. + if (Constraint.length() > 1) return; + + char Letter = Constraint[0]; switch (Letter) { default: break; case 'I': @@ -5498,7 +5504,7 @@ } // Handle standard constraint letters. - TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG); + TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); } // isLegalAddressingMode - Return true if the addressing mode represented Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h?rev=132510&r1=132509&r2=132510&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.h Thu Jun 2 18:16:42 2011 @@ -328,7 +328,7 @@ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. virtual void LowerAsmOperandForConstraint(SDValue Op, - char ConstraintLetter, + std::string &Constraint, std::vector &Ops, SelectionDAG &DAG) const; Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=132510&r1=132509&r2=132510&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jun 2 18:16:42 2011 @@ -12594,12 +12594,16 @@ /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, - char Constraint, + std::string &Constraint, std::vector&Ops, SelectionDAG &DAG) const { SDValue Result(0, 0); - switch (Constraint) { + // Only support length 1 constraints for now. + if (Constraint.length() > 1) return; + + char ConstraintLetter = Constraint[0]; + switch (ConstraintLetter) { default: break; case 'I': if (ConstantSDNode *C = dyn_cast(Op)) { Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=132510&r1=132509&r2=132510&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Jun 2 18:16:42 2011 @@ -596,7 +596,7 @@ /// true it means one of the asm constraint of the inline asm instruction /// being processed is 'm'. virtual void LowerAsmOperandForConstraint(SDValue Op, - char ConstraintLetter, + std::string &Constraint, std::vector &Ops, SelectionDAG &DAG) const; From stoklund at 2pi.dk Thu Jun 2 18:41:41 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 02 Jun 2011 23:41:41 -0000 Subject: [llvm-commits] [llvm] r132514 - in /llvm/trunk/lib/CodeGen: RegAllocFast.cpp RegisterClassInfo.h Message-ID: <20110602234141.13A392A6C12C@llvm.org> Author: stoklund Date: Thu Jun 2 18:41:40 2011 New Revision: 132514 URL: http://llvm.org/viewvc/llvm-project?rev=132514&view=rev Log: Avoid calling TRI->getAllocatableSet in RAFast. When compiling a program with lots of small functions like 483.xalancbmk, this makes RAFast 11% faster. Add some comments to clarify the difference between unallocatable and reserved registers. It's quite subtle. The fast register allocator depends on EFLAGS' not being allocatable on x86. That way it can completely avoid tracking liveness, and it won't mind when there are multiple uses of a single def. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp llvm/trunk/lib/CodeGen/RegisterClassInfo.h Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=132514&r1=132513&r2=132514&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Thu Jun 2 18:41:40 2011 @@ -115,9 +115,6 @@ // instruction, and so cannot be allocated. BitVector UsedInInstr; - // Allocatable - vector of allocatable physical registers. - BitVector Allocatable; - // SkippedInstrs - Descriptors of instructions whose clobber list was // ignored because all registers were spilled. It is still necessary to // mark all the clobbered registers as used by the function. @@ -485,7 +482,7 @@ // Ignore invalid hints. if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || - !RC->contains(Hint) || !Allocatable.test(Hint))) + !RC->contains(Hint) || !RegClassInfo.isAllocatable(Hint))) Hint = 0; // Take hint when possible. @@ -768,7 +765,7 @@ // Add live-in registers as live. for (MachineBasicBlock::livein_iterator I = MBB->livein_begin(), E = MBB->livein_end(); I != E; ++I) - if (Allocatable.test(*I)) + if (RegClassInfo.isAllocatable(*I)) definePhysReg(MII, *I, regReserved); SmallVector VirtDead; @@ -899,7 +896,7 @@ } continue; } - if (!Allocatable.test(Reg)) continue; + if (!RegClassInfo.isAllocatable(Reg)) continue; if (MO.isUse()) { usePhysReg(MO); } else if (MO.isEarlyClobber()) { @@ -988,7 +985,7 @@ unsigned Reg = MO.getReg(); if (TargetRegisterInfo::isPhysicalRegister(Reg)) { - if (!Allocatable.test(Reg)) continue; + if (!RegClassInfo.isAllocatable(Reg)) continue; definePhysReg(MI, Reg, (MO.isImplicit() || MO.isDead()) ? regFree : regReserved); continue; @@ -1045,9 +1042,7 @@ TRI = TM->getRegisterInfo(); TII = TM->getInstrInfo(); RegClassInfo.runOnMachineFunction(Fn); - UsedInInstr.resize(TRI->getNumRegs()); - Allocatable = TRI->getAllocatableSet(*MF); // initialize the virtual->physical register map to have a 'null' // mapping for all virtual registers Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.h?rev=132514&r1=132513&r2=132514&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.h (original) +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.h Thu Jun 2 18:41:40 2011 @@ -95,6 +95,25 @@ return CalleeSaved[N-1]; return 0; } + + /// isReserved - Returns true when PhysReg is a reserved register. + /// + /// Reserved registers may belong to an allocatable register class, but the + /// target has explicitly requested that they are not used. + /// + bool isReserved(unsigned PhysReg) const { + return Reserved.test(PhysReg); + } + + /// isAllocatable - Returns true when PhysReg belongs to an allocatable + /// register class and it hasn't been reserved. + /// + /// Allocatable registers may show up in the allocation order of some virtual + /// register, so a register allocator needs to track its liveness and + /// availability. + bool isAllocatable(unsigned PhysReg) const { + return TRI->get(PhysReg).inAllocatableClass && !isReserved(PhysReg); + } }; } // end namespace llvm From grosbach at apple.com Thu Jun 2 18:51:24 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 02 Jun 2011 16:51:24 -0700 Subject: [llvm-commits] [llvm] r132483 - in /llvm/trunk: lib/CodeGen/ScheduleDAGInstrs.cpp lib/CodeGen/ScheduleDAGInstrs.h test/CodeGen/ARM/debug-info-branch-folding.ll In-Reply-To: <20110602200712.446422A6C12E@llvm.org> References: <20110602200712.446422A6C12E@llvm.org> Message-ID: Yay! Very happy to see this. Should be some nice benefits for ARM debugging. Thanks, Devang! -Jim On Jun 2, 2011, at 1:07 PM, Devang Patel wrote: > Author: dpatel > Date: Thu Jun 2 15:07:12 2011 > New Revision: 132483 > > URL: http://llvm.org/viewvc/llvm-project?rev=132483&view=rev > Log: > During post RA scheduling, do not try to chase reg defs. to preserve DBG_VALUEs. This approach has several downsides, for example, it does not work when dbg value is a constant integer, it does not work if reg is defined more than once, it places end of debug value range markers in the wrong place. It even causes misleading incorrect debug info when duplicate DBG_VALUE instructions point to same reg def. > > Instead, use simpler approach and let DBG_VALUE follow its predecessor instruction. After live debug value analysis pass, all DBG_VALUE instruction are placed at the right place. Thanks Jakob for the hint! > > Modified: > llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp > llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h > llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll > > Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=132483&r1=132482&r2=132483&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) > +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Thu Jun 2 15:07:12 2011 > @@ -35,8 +35,9 @@ > const MachineDominatorTree &mdt) > : ScheduleDAG(mf), MLI(mli), MDT(mdt), MFI(mf.getFrameInfo()), > InstrItins(mf.getTarget().getInstrItineraryData()), > - Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()), LoopRegs(MLI, MDT) { > - DbgValueVec.clear(); > + Defs(TRI->getNumRegs()), Uses(TRI->getNumRegs()), > + FirstDbgValue(0), LoopRegs(MLI, MDT) { > + DbgValues.clear(); > } > > /// Run - perform scheduling. > @@ -200,11 +201,6 @@ > std::map AliasMemDefs, NonAliasMemDefs; > std::map > AliasMemUses, NonAliasMemUses; > > - // Keep track of dangling debug references to registers. > - std::vector > > - DanglingDebugValue(TRI->getNumRegs(), > - std::make_pair(static_cast(0), 0)); > - > // Check to see if the scheduler cares about latencies. > bool UnitLatencies = ForceUnitLatencies(); > > @@ -214,7 +210,8 @@ > > // Remove any stale debug info; sometimes BuildSchedGraph is called again > // without emitting the info from the previous call. > - DbgValueVec.clear(); > + DbgValues.clear(); > + FirstDbgValue = NULL; > > // Model data dependencies between instructions being scheduled and the > // ExitSU. > @@ -225,19 +222,20 @@ > } > > // Walk the list of instructions, from bottom moving up. > + MachineInstr *PrevMI = NULL; > for (MachineBasicBlock::iterator MII = InsertPos, MIE = Begin; > MII != MIE; --MII) { > MachineInstr *MI = prior(MII); > - // DBG_VALUE does not have SUnit's built, so just remember these for later > - // reinsertion. > + if (MI && PrevMI) { > + DbgValues.push_back(std::make_pair(PrevMI, MI)); > + PrevMI = NULL; > + } > + > if (MI->isDebugValue()) { > - if (MI->getNumOperands()==3 && MI->getOperand(0).isReg() && > - MI->getOperand(0).getReg()) > - DanglingDebugValue[MI->getOperand(0).getReg()] = > - std::make_pair(MI, DbgValueVec.size()); > - DbgValueVec.push_back(MI); > + PrevMI = MI; > continue; > } > + > const TargetInstrDesc &TID = MI->getDesc(); > assert(!TID.isTerminator() && !MI->isLabel() && > "Cannot schedule terminators or labels!"); > @@ -261,12 +259,6 @@ > > assert(TRI->isPhysicalRegister(Reg) && "Virtual register encountered!"); > > - if (MO.isDef() && DanglingDebugValue[Reg].first!=0) { > - SU->DbgInstrList.push_back(DanglingDebugValue[Reg].first); > - DbgValueVec[DanglingDebugValue[Reg].second] = 0; > - DanglingDebugValue[Reg] = std::make_pair((MachineInstr*)0, 0); > - } > - > std::vector &UseList = Uses[Reg]; > // Defs are push in the order they are visited and never reordered. > std::vector &DefList = Defs[Reg]; > @@ -561,6 +553,8 @@ > } > } > } > + if (PrevMI) > + FirstDbgValue = PrevMI; > > for (int i = 0, e = TRI->getNumRegs(); i != e; ++i) { > Defs[i].clear(); > @@ -670,13 +664,9 @@ > BB->remove(I); > } > > - // First reinsert any remaining debug_values; these are either constants, > - // or refer to live-in registers. The beginning of the block is the right > - // place for the latter. The former might reasonably be placed elsewhere > - // using some kind of ordering algorithm, but right now it doesn't matter. > - for (int i = DbgValueVec.size()-1; i>=0; --i) > - if (DbgValueVec[i]) > - BB->insert(InsertPos, DbgValueVec[i]); > + // If first instruction was a DBG_VALUE then put it back. > + if (FirstDbgValue) > + BB->insert(InsertPos, FirstDbgValue); > > // Then re-insert them according to the given schedule. > for (unsigned i = 0, e = Sequence.size(); i != e; i++) { > @@ -694,15 +684,18 @@ > > // Update the Begin iterator, as the first instruction in the block > // may have been scheduled later. > - if (!DbgValueVec.empty()) { > - for (int i = DbgValueVec.size()-1; i>=0; --i) > - if (DbgValueVec[i]!=0) { > - Begin = DbgValueVec[DbgValueVec.size()-1]; > - break; > - } > - } else if (!Sequence.empty()) > + if (!Sequence.empty()) > Begin = Sequence[0]->getInstr(); > > - DbgValueVec.clear(); > + // Reinsert any remaining debug_values. > + for (std::vector >::iterator > + DI = DbgValues.end(), DE = DbgValues.begin(); DI != DE; --DI) { > + std::pair P = *prior(DI); > + MachineInstr *DbgValue = P.first; > + MachineInstr *OrigPrivMI = P.second; > + BB->insertAfter(OrigPrivMI, DbgValue); > + } > + DbgValues.clear(); > + FirstDbgValue = NULL; > return BB; > } > > Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h?rev=132483&r1=132482&r2=132483&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h (original) > +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.h Thu Jun 2 15:07:12 2011 > @@ -110,9 +110,9 @@ > std::vector > Defs; > std::vector > Uses; > > - /// DbgValueVec - Remember DBG_VALUEs that refer to a particular > - /// register. > - std::vectorDbgValueVec; > + /// DbgValues - Remember instruction that preceeds DBG_VALUE. > + std::vector >DbgValues; > + MachineInstr *FirstDbgValue; > > /// PendingLoads - Remember where unknown loads are after the most recent > /// unknown store, as we iterate. As with Defs and Uses, this is here > > Modified: llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll?rev=132483&r1=132482&r2=132483&view=diff > ============================================================================== > --- llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll (original) > +++ llvm/trunk/test/CodeGen/ARM/debug-info-branch-folding.ll Thu Jun 2 15:07:12 2011 > @@ -2,9 +2,11 @@ > target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32" > target triple = "thumbv7-apple-macosx10.6.7" > > -;CHECK: Ltmp1: > -;CHECK-NEXT: @DEBUG_VALUE: x <- Q4+0 > -;CHECK-NEXT: adr r0, #LCPI0_0 > +;CHECK: vadd.f32 q4, q8, q8 > +;CHECK-NEXT: Ltmp > +;CHECK-NEXT: @DEBUG_VALUE: y <- Q4+0 > +;CHECK-NEXT: @DEBUG_VALUE: x <- Q4+0 > + > > @.str = external constant [13 x i8] > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Thu Jun 2 18:58:09 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 02 Jun 2011 16:58:09 -0700 Subject: [llvm-commits] [PATCH]: PowerPC64, wrong mixing of CTR and CTR8 In-Reply-To: <20110602194412.GA75670@freebsd.org> References: <20110602194412.GA75670@freebsd.org> Message-ID: <72631F83-143B-4527-A1E9-5AA873796EB1@2pi.dk> On Jun 2, 2011, at 12:44 PM, Roman Divacky wrote: > Hi, > > On PowerPC64 when lowering BRIND (indirect branch) for PPC64 the "mtctr" > instruction is pointed to a "wrong" bctr instruction. Ie. one that uses "CTR" > instead of "CTR8". This causes http://llvm.org/bugs/show_bug.cgi?id=8487 . > > CTR8 is also omitted when seting HasCTRSet in hazard recognizer. And also > wrong CTR variant is used when emitting indirect call on PPC64. > > The attached patch fixes all of that (+ test). We're now able to compile > stuff like "ls" or "sh" on FreeBSD/PowerPC. OK to commit? Very nice! LGTM. /jakob From atrick at apple.com Thu Jun 2 18:57:27 2011 From: atrick at apple.com (Andrew Trick) Date: Thu, 02 Jun 2011 23:57:27 -0000 Subject: [llvm-commits] [llvm] r132516 - /llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll Message-ID: <20110602235727.8E64E2A6C12C@llvm.org> Author: atrick Date: Thu Jun 2 18:57:27 2011 New Revision: 132516 URL: http://llvm.org/viewvc/llvm-project?rev=132516&view=rev Log: Test case pasto (failed when run with IR verifier). Modified: llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll Modified: llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll?rev=132516&r1=132515&r2=132516&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/elim-extend.ll Thu Jun 2 18:57:27 2011 @@ -138,11 +138,11 @@ %ofs4 = sext i32 %outercount to i64 %adr4 = getelementptr i8* %address, i64 %ofs4 - store i8 0, i8* %adr3 + store i8 0, i8* %adr4 %ofs5 = sext i32 %innercount.merge to i64 %adr5 = getelementptr i8* %address, i64 %ofs5 - store i8 0, i8* %adr4 + store i8 0, i8* %adr5 %outerpostcount = add i32 %outercount, 1 %tmp47 = icmp slt i32 %outerpostcount, %limit From nlewycky at google.com Thu Jun 2 19:18:59 2011 From: nlewycky at google.com (Nick Lewycky) Date: Thu, 2 Jun 2011 17:18:59 -0700 Subject: [llvm-commits] patch: refactor the asmparser a little Message-ID: The attached patch refactors the asm parsers' parsing of strings into a ReadString method and parsing of LocalVarName or GlobalVarName into ReadName(). No functionality change intended. I'm asking for review because the parser doesn't already have helper functions like these, and I wanted to check whether the error-reporting style (inconsistent between the two) is okay to commit or if anyone has suggestions. Nick -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110602/76a936fc/attachment.html -------------- next part -------------- A non-text attachment was scrubbed... Name: asmparser-refactor.patch Type: text/x-patch Size: 4104 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110602/76a936fc/attachment.bin From atrick at apple.com Thu Jun 2 19:44:32 2011 From: atrick at apple.com (Andrew Trick) Date: Fri, 03 Jun 2011 00:44:32 -0000 Subject: [llvm-commits] [llvm] r132519 - /llvm/trunk/lib/VMCore/PassManager.cpp Message-ID: <20110603004432.63C9D2A6C12C@llvm.org> Author: atrick Date: Thu Jun 2 19:44:32 2011 New Revision: 132519 URL: http://llvm.org/viewvc/llvm-project?rev=132519&view=rev Log: whitespace Modified: llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=132519&r1=132518&r2=132519&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Thu Jun 2 19:44:32 2011 @@ -449,9 +449,9 @@ static DebugInfoProbeInfo *TheDebugProbe; static void createDebugInfoProbe() { if (TheDebugProbe) return; - - // Constructed the first time this is called. This guarantees that the - // object will be constructed, if -enable-debug-info-probe is set, + + // Constructed the first time this is called. This guarantees that the + // object will be constructed, if -enable-debug-info-probe is set, // before static globals, thus it will be destroyed before them. static ManagedStatic DIP; TheDebugProbe = &*DIP; From atrick at apple.com Thu Jun 2 19:48:58 2011 From: atrick at apple.com (Andrew Trick) Date: Fri, 03 Jun 2011 00:48:58 -0000 Subject: [llvm-commits] [llvm] r132520 - /llvm/trunk/lib/VMCore/PassManager.cpp Message-ID: <20110603004858.2DEB02A6C12C@llvm.org> Author: atrick Date: Thu Jun 2 19:48:58 2011 New Revision: 132520 URL: http://llvm.org/viewvc/llvm-project?rev=132520&view=rev Log: Basic PassManager diagnostics. Added asserts whenever attempting to use a potentially uninitialized pass. This helps people trying to develop a new pass and people trying to understand the bug reports filed by the former people. Modified: llvm/trunk/lib/VMCore/PassManager.cpp Modified: llvm/trunk/lib/VMCore/PassManager.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=132520&r1=132519&r2=132520&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/PassManager.cpp (original) +++ llvm/trunk/lib/VMCore/PassManager.cpp Thu Jun 2 19:48:58 2011 @@ -632,6 +632,7 @@ Pass *AnalysisPass = findAnalysisPass(*I); if (!AnalysisPass) { const PassInfo *PI = PassRegistry::getPassRegistry()->getPassInfo(*I); + assert(PI && "Expected required passes to be initialized"); AnalysisPass = PI->createPass(); if (P->getPotentialPassManagerType () == AnalysisPass->getPotentialPassManagerType()) @@ -686,6 +687,7 @@ // If Pass not found then check the interfaces implemented by Immutable Pass const PassInfo *PassInf = PassRegistry::getPassRegistry()->getPassInfo(PI); + assert(PassInf && "Expected all immutable passes to be initialized"); const std::vector &ImmPI = PassInf->getInterfacesImplemented(); for (std::vector::const_iterator II = ImmPI.begin(), @@ -727,9 +729,11 @@ for (SmallVector::const_iterator I = ImmutablePasses.begin(), E = ImmutablePasses.end(); I != E; ++I) if (const PassInfo *PI = - PassRegistry::getPassRegistry()->getPassInfo((*I)->getPassID())) + PassRegistry::getPassRegistry()->getPassInfo((*I)->getPassID())) { + assert(PI && "Expected all immutable passes to be initialized"); if (!PI->isAnalysisGroup()) dbgs() << " -" << PI->getPassArgument(); + } for (SmallVector::const_iterator I = PassManagers.begin(), E = PassManagers.end(); I != E; ++I) (*I)->dumpPassArguments(); @@ -1183,6 +1187,12 @@ for (unsigned i = 0; i != Set.size(); ++i) { if (i) dbgs() << ','; const PassInfo *PInf = PassRegistry::getPassRegistry()->getPassInfo(Set[i]); + if (!PInf) { + // Some preserved passes, such as AliasAnalysis, may not be initialized by + // all drivers. + dbgs() << " Uninitialized Pass"; + continue; + } dbgs() << ' ' << PInf->getPassName(); } dbgs() << '\n'; From atrick at apple.com Thu Jun 2 19:58:36 2011 From: atrick at apple.com (Andrew Trick) Date: Thu, 02 Jun 2011 17:58:36 -0700 Subject: [llvm-commits] [llvm] r132520 - /llvm/trunk/lib/VMCore/PassManager.cpp In-Reply-To: <20110603004858.2DEB02A6C12C@llvm.org> References: <20110603004858.2DEB02A6C12C@llvm.org> Message-ID: <4C1741DB-A12D-4819-8900-0D0EC8DCF686@apple.com> Preemptive review: Sorry for the lack of test case. It didn't seem worth adding a fake driver to the llvm build! -Andy On Jun 2, 2011, at 5:48 PM, Andrew Trick wrote: > Author: atrick > Date: Thu Jun 2 19:48:58 2011 > New Revision: 132520 > > URL: http://llvm.org/viewvc/llvm-project?rev=132520&view=rev > Log: > Basic PassManager diagnostics. > > Added asserts whenever attempting to use a potentially > uninitialized pass. This helps people trying to develop a new pass and > people trying to understand the bug reports filed by the former people. > > Modified: > llvm/trunk/lib/VMCore/PassManager.cpp > > Modified: llvm/trunk/lib/VMCore/PassManager.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/PassManager.cpp?rev=132520&r1=132519&r2=132520&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/PassManager.cpp (original) > +++ llvm/trunk/lib/VMCore/PassManager.cpp Thu Jun 2 19:48:58 2011 > @@ -632,6 +632,7 @@ > Pass *AnalysisPass = findAnalysisPass(*I); > if (!AnalysisPass) { > const PassInfo *PI = PassRegistry::getPassRegistry()->getPassInfo(*I); > + assert(PI && "Expected required passes to be initialized"); > AnalysisPass = PI->createPass(); > if (P->getPotentialPassManagerType () == > AnalysisPass->getPotentialPassManagerType()) > @@ -686,6 +687,7 @@ > // If Pass not found then check the interfaces implemented by Immutable Pass > const PassInfo *PassInf = > PassRegistry::getPassRegistry()->getPassInfo(PI); > + assert(PassInf && "Expected all immutable passes to be initialized"); > const std::vector &ImmPI = > PassInf->getInterfacesImplemented(); > for (std::vector::const_iterator II = ImmPI.begin(), > @@ -727,9 +729,11 @@ > for (SmallVector::const_iterator I = > ImmutablePasses.begin(), E = ImmutablePasses.end(); I != E; ++I) > if (const PassInfo *PI = > - PassRegistry::getPassRegistry()->getPassInfo((*I)->getPassID())) > + PassRegistry::getPassRegistry()->getPassInfo((*I)->getPassID())) { > + assert(PI && "Expected all immutable passes to be initialized"); > if (!PI->isAnalysisGroup()) > dbgs() << " -" << PI->getPassArgument(); > + } > for (SmallVector::const_iterator I = PassManagers.begin(), > E = PassManagers.end(); I != E; ++I) > (*I)->dumpPassArguments(); > @@ -1183,6 +1187,12 @@ > for (unsigned i = 0; i != Set.size(); ++i) { > if (i) dbgs() << ','; > const PassInfo *PInf = PassRegistry::getPassRegistry()->getPassInfo(Set[i]); > + if (!PInf) { > + // Some preserved passes, such as AliasAnalysis, may not be initialized by > + // all drivers. > + dbgs() << " Uninitialized Pass"; > + continue; > + } > dbgs() << ' ' << PInf->getPassName(); > } > dbgs() << '\n'; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From eli.friedman at gmail.com Thu Jun 2 20:13:19 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 03 Jun 2011 01:13:19 -0000 Subject: [llvm-commits] [llvm] r132522 - in /llvm/trunk: lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel.ll Message-ID: <20110603011319.E33D62A6C12C@llvm.org> Author: efriedma Date: Thu Jun 2 20:13:19 2011 New Revision: 132522 URL: http://llvm.org/viewvc/llvm-project?rev=132522&view=rev Log: Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol. rdar://9431157 Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/test/CodeGen/ARM/fast-isel.ll Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=132522&r1=132521&r2=132522&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Thu Jun 2 20:13:19 2011 @@ -577,9 +577,6 @@ Reloc::Model RelocM = TM.getRelocationModel(); - // TODO: No external globals for now. - if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0; - // TODO: Need more magic for ARM PIC. if (!isThumb && (RelocM == Reloc::PIC_)) return 0; @@ -614,6 +611,23 @@ .addImm(0); } AddOptionalDefs(MIB); + + if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) { + unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); + if (isThumb) + MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::t2LDRi12), + NewDestReg) + .addReg(DestReg) + .addImm(0); + else + MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12), + NewDestReg) + .addReg(DestReg) + .addImm(0); + DestReg = NewDestReg; + AddOptionalDefs(MIB); + } + return DestReg; } Modified: llvm/trunk/test/CodeGen/ARM/fast-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/fast-isel.ll?rev=132522&r1=132521&r2=132522&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/fast-isel.ll (original) +++ llvm/trunk/test/CodeGen/ARM/fast-isel.ll Thu Jun 2 20:13:19 2011 @@ -131,4 +131,30 @@ ; ARM: sxth ; ARM: add ; ARM: sub -} \ No newline at end of file +} + +; Check loads/stores with globals + at test4g = external global i32 + +define void @test4() { + %a = load i32* @test4g + %b = add i32 %a, 1 + store i32 %b, i32* @test4g + ret void + +; THUMB: ldr.n r0, LCPI4_1 +; THUMB: ldr r0, [r0] +; THUMB: ldr r0, [r0] +; THUMB: adds r0, #1 +; THUMB: ldr.n r1, LCPI4_0 +; THUMB: ldr r1, [r1] +; THUMB: str r0, [r1] + +; ARM: ldr r0, LCPI4_1 +; ARM: ldr r0, [r0] +; ARM: ldr r0, [r0] +; ARM: add r0, r0, #1 +; ARM: ldr r1, LCPI4_0 +; ARM: ldr r1, [r1] +; ARM: str r0, [r1] +} From echristo at apple.com Thu Jun 2 20:51:56 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 02 Jun 2011 18:51:56 -0700 Subject: [llvm-commits] [llvm] r132522 - in /llvm/trunk: lib/Target/ARM/ARMFastISel.cpp test/CodeGen/ARM/fast-isel.ll In-Reply-To: <20110603011319.E33D62A6C12C@llvm.org> References: <20110603011319.E33D62A6C12C@llvm.org> Message-ID: On Jun 2, 2011, at 6:13 PM, Eli Friedman wrote: > Author: efriedma > Date: Thu Jun 2 20:13:19 2011 > New Revision: 132522 > > URL: http://llvm.org/viewvc/llvm-project?rev=132522&view=rev > Log: > Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol. > > rdar://9431157 > Thanks Eli! -eric From aggarwa4 at illinois.edu Thu Jun 2 21:14:26 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 03 Jun 2011 02:14:26 -0000 Subject: [llvm-commits] [poolalloc] r132525 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp Message-ID: <20110603021426.CD10C2A6C12C@llvm.org> Author: aggarwa4 Date: Thu Jun 2 21:14:26 2011 New Revision: 132525 URL: http://llvm.org/viewvc/llvm-project?rev=132525&view=rev Log: Add tracking on indirect call targets. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=132525&r1=132524&r2=132525&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Thu Jun 2 21:14:26 2011 @@ -16,6 +16,7 @@ #include "assistDS/TypeAnalysis.h" #include "dsa/TypeSafety.h" +#include "dsa/AddressTakenAnalysis.h" #include "llvm/Instructions.h" #include "llvm/Pass.h" @@ -33,14 +34,18 @@ private: std::map UsedTypes; std::map VAListFunctionsMap; + std::map IndFunctionsMap; std::list VAArgFunctions; std::list VAListFunctions; std::list ByValFunctions; + std::list AddressTakenFunctions; + std::set IndCalls; // Analysis from other passes. TargetData *TD; TypeAnalysis *TA; dsa::TypeSafety *TS; + AddressTakenAnalysis* addrAnalysis; public: static char ID; @@ -52,6 +57,7 @@ AU.addRequired(); AU.addRequired >(); AU.addRequired(); + AU.addRequired(); } bool initShadow(Module &M); @@ -59,12 +65,13 @@ bool visitCallInst(Module &M, CallInst &CI); bool visitInvokeInst(Module &M, InvokeInst &CI); bool visitCallSite(Module &M, CallSite CS); - bool visitIndirectCallSite(Module &M, CallSite CS); + bool visitIndirectCallSite(Module &M, Instruction *I); bool visitInternalByValFunction(Module &M, Function &F); bool visitExternalByValFunction(Module &M, Function &F); bool visitByValFunction(Module &M, Function &F); bool visitMain(Module &M, Function &F); bool visitVarArgFunction(Module &M, Function &F); + bool visitAddressTakenFunction(Module &M, Function &F); bool visitVAListFunction(Module &M, Function &F); bool visitInternalVarArgFunction(Module &M, Function &F); bool visitLoadInst(Module &M, LoadInst &LI); Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132525&r1=132524&r2=132525&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 2 21:14:26 2011 @@ -84,6 +84,7 @@ TD = &getAnalysis(); TA = &getAnalysis(); + addrAnalysis = &getAnalysis(); if(EnableTypeSafeOpt) TS = &getAnalysis >(); @@ -107,6 +108,7 @@ VAListFunctions.clear(); VAArgFunctions.clear(); ByValFunctions.clear(); + AddressTakenFunctions.clear(); Function *MainF = M.getFunction("main"); if (MainF == 0 || MainF->isDeclaration()) { @@ -140,6 +142,11 @@ ByValFunctions.push_back(&F); } + // Iterate and find all address taken functions + if(addrAnalysis->hasAddressTaken(&F)) { + AddressTakenFunctions.push_back(&F); + } + // Iterate and find all varargs functions if(F.isVarArg()) { VAArgFunctions.push_back(&F); @@ -185,12 +192,7 @@ for(; FI != FE; FI++) { visitVAListCall(FI->second); } - while(!VAArgFunctions.empty()) { - Function *F = VAArgFunctions.back(); - VAArgFunctions.pop_back(); - assert(F->isVarArg()); - modified |= visitVarArgFunction(M, *F); - } + for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { Function &F = *MI; if(F.isDeclaration()) @@ -198,7 +200,7 @@ // Loop over all of the instructions in the function, // adding their return type as well as the types of their operands. - for (inst_iterator II = inst_begin(F), IE = inst_end(F); II != IE; ++II) { + for (inst_iterator II = inst_begin(F), IE = inst_end(F); II != IE;++II) { Instruction &I = *II; if (StoreInst *SI = dyn_cast(&I)) { if (TA->isCopyingStore(SI)) { @@ -223,6 +225,35 @@ } } + while(!VAArgFunctions.empty()) { + Function *F = VAArgFunctions.back(); + VAArgFunctions.pop_back(); + assert(F->isVarArg()); + modified |= visitVarArgFunction(M, *F); + } + + while(!AddressTakenFunctions.empty()) { + Function *F = AddressTakenFunctions.back(); + AddressTakenFunctions.pop_back(); + errs() << F->getNameStr()<<"\n"; + if(F->isVarArg()) + continue; + visitAddressTakenFunction(M, *F); + } + + // visit all the uses of the address taken functions and modify if + // visit all the indirect call sites + for(std::set::iterator II = IndCalls.begin(); II != IndCalls.end(); ) { + Instruction *I = *II++; + modified |= visitIndirectCallSite(M,I); + } + FI = IndFunctionsMap.begin(), FE = IndFunctionsMap.end(); + for(;FI!=FE;++FI) { + Constant *C = ConstantExpr::getBitCast(FI->second, FI->first->getType()); + FI->first->replaceAllUsesWith(C); + } + + // add a global that contains the mapping from metadata to strings addTypeMap(M); @@ -418,6 +449,93 @@ return true; } +bool TypeChecks::visitAddressTakenFunction(Module &M, Function &F) { + // Clone function + // 1. Create the new argument types vector + std::vector TP; + TP.push_back(Int64Ty); // for count + TP.push_back(VoidPtrTy); // for MD + for(Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I !=E; ++I) { + TP.push_back(I->getType()); + } + + // 2. Create the new function prototype + const FunctionType *NewFTy = FunctionType::get(F.getReturnType(), TP, true); + Function *NewF = Function::Create(NewFTy, + GlobalValue::InternalLinkage, + F.getNameStr() + ".mod", + &M); + + // 3. Set the mapping for the args + Function::arg_iterator NI = NewF->arg_begin(); + DenseMap ValueMap; + NI->setName("TotalCount"); + NI++; + NI->setName("MD"); + NI++; + for(Function::arg_iterator II = F.arg_begin(); NI!=NewF->arg_end(); ++II, ++NI) { + // Each new argument maps to the argument in the old function + // For each of these also copy attributes + ValueMap[II] = NI; + NI->setName(II->getName()); + NI->addAttr(F.getAttributes().getParamAttributes(II->getArgNo()+1)); + } + + // 4. Copy over attributes for the function + NewF->setAttributes(NewF->getAttributes() + .addAttr(0, F.getAttributes().getRetAttributes())); + NewF->setAttributes(NewF->getAttributes().addAttr(~0, F.getAttributes().getFnAttributes())); + + // 5. Perform the cloning + SmallVectorReturns; + CloneFunctionInto(NewF, &F, ValueMap, Returns); + IndFunctionsMap[&F] = NewF; + + // Find all uses of the function + for(Value::use_iterator ui = F.use_begin(), ue = F.use_end(); + ui != ue;) { + // Check for call sites + CallInst *CI = dyn_cast(ui++); + if(!CI) + continue; + std::vector Args; + unsigned int i; + unsigned int NumArgs = CI->getNumOperands() - 1; + Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); + AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", CI); + // set the metadata for the varargs in AI + for(i = 1; i getNumOperands(); i++) { + Value *Idx[2]; + Idx[0] = ConstantInt::get(Int32Ty, i - 1 ); + // For each vararg argument, also add its type information + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, + Idx, + Idx + 1, + "", CI); + Constant *C = ConstantInt::get(Int8Ty, + getTypeMarker(CI->getOperand(i)->getType())); + new StoreInst(C, GEP, CI); + } + + // As the first argument pass the number of var_arg arguments + Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); + Args.push_back(AI); + for(i = 1 ;i < CI->getNumOperands(); i++) { + // Add the original argument + Args.push_back(CI->getOperand(i)); + } + + // Create the new call + CallInst *CI_New = CallInst::Create(NewF, + Args.begin(), Args.end(), + "", CI); + CI->replaceAllUsesWith(CI_New); + CI->eraseFromParent(); + } + + return true; +} + // Transform Variable Argument functions, by also passing // the relavant metadata info bool TypeChecks::visitVarArgFunction(Module &M, Function &F) { @@ -614,10 +732,9 @@ Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", CI); // set the metadata for the varargs in AI - unsigned int j =0; for(i = 1; i getNumOperands(); i++) { Value *Idx[2]; - Idx[0] = ConstantInt::get(Int32Ty, j++); + Idx[0] = ConstantInt::get(Int32Ty, i - 1 ); // For each vararg argument, also add its type information GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, Idx, @@ -643,6 +760,7 @@ CI->replaceAllUsesWith(CI_New); CI->eraseFromParent(); } + IndFunctionsMap[&F] = NewF; return true; } @@ -689,7 +807,7 @@ assert(I->getType()->isPointerTy()); const Type *ETy = (cast(I->getType()))->getElementType(); AllocaInst *AI = new AllocaInst(ETy, "", InsertBefore); - // Do this before add a load/store pair, so that those uses are not replaced. + // Do this before adding the load/store pair, so that those uses are not replaced. I->replaceAllUsesWith(AI); LoadInst *LI = new LoadInst(I, "", InsertBefore); new StoreInst(LI, AI, InsertBefore); @@ -1084,18 +1202,10 @@ std::vector Args; Args.push_back(BCI); - Args.push_back(AllocSize); + Args.push_back(Size); Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); CallInst *CI = CallInst::Create(trackUnInitInst, Args.begin(), Args.end()); - CI->insertAfter(BCI); - std::vector Args1; - Args1.push_back(BCI); - Args1.push_back(AllocSize); - Args1.push_back(ArraySize); - Args1.push_back(ConstantInt::get(Int32Ty, tagCounter++)); - CallInst *CI_Arr = CallInst::Create(trackArray, Args1.begin(), Args1.end()); - CI_Arr->insertAfter(CI); - + CI->insertAfter(CI_Init); return true; } @@ -1247,9 +1357,9 @@ CI->insertAfter(BCI); std::vector Args1; Args1.push_back(BCI); - Args.push_back(Size); + Args1.push_back(Size); CastInst *Num = CastInst::CreateIntegerCast(I->getOperand(1), Int64Ty, false, "", I); - Args.push_back(Num); + Args1.push_back(Num); Args1.push_back(ConstantInt::get(Int32Ty, tagCounter++)); CallInst *CI_Arr = CallInst::Create(trackArray, Args1.begin(), Args1.end()); CI_Arr->insertAfter(CI); @@ -1303,14 +1413,58 @@ } } else { // indirect call site - return visitIndirectCallSite(M, CS); + IndCalls.insert(CS.getInstruction()); + return false; } return false; } -bool TypeChecks::visitIndirectCallSite(Module &M, CallSite CS) { - Instruction *I = CS.getInstruction(); - I->dump(); +bool TypeChecks::visitIndirectCallSite(Module &M, Instruction *I) { + // add the number of arguments as the first argument + + unsigned int NumArgs = I->getNumOperands() - 1; + Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); + + AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", I); + for(unsigned int i = 1; i < I->getNumOperands(); i++) { + Value *Idx[2]; + Idx[0] = ConstantInt::get(Int32Ty, i-1); + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, + Idx, + Idx + 1, + "", I); + Constant *C = ConstantInt::get(Int8Ty, + getTypeMarker(I->getOperand(i)->getType())); + new StoreInst(C, GEP, I); + } + std::vector Args; + Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); + Args.push_back(AI); + + for(unsigned int i = 1; i < I->getNumOperands(); i++) + Args.push_back(I->getOperand(i)); + + const Type* OrigType = I->getOperand(0)->getType(); + assert(OrigType->isPointerTy()); + const FunctionType *FOldType = cast((cast(OrigType))->getElementType()); + std::vectorTP; + TP.push_back(Int64Ty); + TP.push_back(VoidPtrTy); + + for(llvm::FunctionType::param_iterator ArgI = FOldType->param_begin(); ArgI != FOldType->param_end(); ++ArgI) + TP.push_back(*ArgI); + + const FunctionType *FTy = FunctionType::get(FOldType->getReturnType(), TP, FOldType->isVarArg()); + CastInst *Func = CastInst::CreatePointerCast(I->getOperand(0), FTy->getPointerTo(), "", I); + CallInst *CI_New = CallInst::Create(Func, + Args.begin(), + Args.end(), + "", I); + I->replaceAllUsesWith(CI_New); + I->eraseFromParent(); + + + // add they types of the argument as the second argument return false; } From atrick at apple.com Thu Jun 2 21:16:53 2011 From: atrick at apple.com (Andrew Trick) Date: Fri, 03 Jun 2011 02:16:53 -0000 Subject: [llvm-commits] [llvm] r132526 - /llvm/trunk/docs/Projects.html Message-ID: <20110603021653.928D12A6C12C@llvm.org> Author: atrick Date: Thu Jun 2 21:16:53 2011 New Revision: 132526 URL: http://llvm.org/viewvc/llvm-project?rev=132526&view=rev Log: whitespace Modified: llvm/trunk/docs/Projects.html Modified: llvm/trunk/docs/Projects.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Projects.html?rev=132526&r1=132525&r2=132526&view=diff ============================================================================== --- llvm/trunk/docs/Projects.html (original) +++ llvm/trunk/docs/Projects.html Thu Jun 2 21:16:53 2011 @@ -49,7 +49,7 @@
  • PROJ_SRC_ROOT - The root of the project's source tree.
  • PROJ_OBJ_ROOT - The root of the project's object tree.
  • PROJ_INSTALL_ROOT - The root installation directory.
    • -
  • LEVEL - The relative path from the current directory to the +
  • LEVEL - The relative path from the current directory to the project's root ($PROJ_OBJ_ROOT).
  • Include Makefile.config from $(LLVM_OBJ_ROOT).
    • @@ -59,9 +59,9 @@

    There are two ways that you can set all of these variables:

    1. You can write your own Makefiles which hard-code these values.
      2. -
    2. You can use the pre-made LLVM sample project. This sample project - includes Makefiles, a configure script that can be used to configure the - location of LLVM, and the ability to support multiple object directories +
    3. You can use the pre-made LLVM sample project. This sample project + includes Makefiles, a configure script that can be used to configure the + location of LLVM, and the ability to support multiple object directories from a single source directory.
    @@ -88,9 +88,9 @@ the name of your project.
  • -If you downloaded LLVM using Subversion, remove all the directories named .svn -(and all the files therein) from your project's new source tree. This will -keep Subversion from thinking that your project is inside +If you downloaded LLVM using Subversion, remove all the directories named .svn +(and all the files therein) from your project's new source tree. This will +keep Subversion from thinking that your project is inside llvm/trunk/projects/sample.
  • Add your source code and Makefiles to your source tree.
    • @@ -139,7 +139,7 @@

    That's it! Now all you have to do is type gmake (or make -if your on a GNU/Linux system) in the root of your object directory, and your +if your on a GNU/Linux system) in the root of your object directory, and your project should build.

    @@ -209,7 +209,7 @@ test procedure uses RUN lines in the actual test case to determine how to run the test. See the TestingGuide for more details. You - can easily write Makefile support similar to the Makefiles in + can easily write Makefile support similar to the Makefiles in llvm/test to use Dejagnu to run your project's tests.
  • LLVM contains an optional package called llvm-test @@ -441,7 +441,7 @@ Mailing List.

    - +
    From atrick at apple.com Thu Jun 2 21:20:49 2011 From: atrick at apple.com (Andrew Trick) Date: Fri, 03 Jun 2011 02:20:49 -0000 Subject: [llvm-commits] [llvm] r132527 - /llvm/trunk/docs/Projects.html Message-ID: <20110603022049.E779E2A6C12C@llvm.org> Author: atrick Date: Thu Jun 2 21:20:48 2011 New Revision: 132527 URL: http://llvm.org/viewvc/llvm-project?rev=132527&view=rev Log: Corrections and additional information for "Creating and LLVM Project" documentation. This should now reflect the current state of LLVM Makefiles. Modified: llvm/trunk/docs/Projects.html Modified: llvm/trunk/docs/Projects.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/Projects.html?rev=132527&r1=132526&r2=132527&view=diff ============================================================================== --- llvm/trunk/docs/Projects.html (original) +++ llvm/trunk/docs/Projects.html Thu Jun 2 21:20:48 2011 @@ -339,16 +339,41 @@
    USEDLIBS
    - This variable holds a space separated list of libraries that - should be linked into the program. These libraries must either - be LLVM libraries or libraries that come from your lib - directory. The libraries must be specified by their base name. - For example, to link libsample.a, you would set USEDLIBS to - sample. + This variable holds a space separated list of libraries that should + be linked into the program. These libraries must be libraries that + come from your lib directory. The libraries must be + specified without their "lib" prefix. For example, to link + libsample.a, you would set USEDLIBS to + sample.a.

    Note that this works only for statically linked libraries.

    +

    LLVMLIBS +
    + This variable holds a space separated list of libraries that should + be linked into the program. These libraries must be LLVM libraries. + The libraries must be specified without their "lib" prefix. For + example, to link with a driver that performs an IR transformation + you might set LLVMLIBS to this minimal set of libraries + LLVMSupport.a LLVMCore.a LLVMBitReader.a LLVMAsmParser.a LLVMAnalysis.a LLVMTransformUtils.a LLVMScalarOpts.a LLVMTarget.a. +

    + Note that this works only for statically linked libraries. LLVM is + split into a large number of static libraries, and the list of libraries you + require may be much longer than the list above. To see a full list + of libraries use: + llvm-config --libs all. + Using LINK_COMPONENTS as described below, obviates the need to set LLVMLIBS. +

    + +

    LINK_COMPONENTS +
    This variable holds a space separated list of components that + the LLVM Makefiles pass to the llvm-config tool to generate + a link line for the program. For example, to link with all LLVM + libraries use + LINK_COMPONENTS = all. +

    +

    LIBS
    To link dynamic libraries, add -l<library base name> to @@ -361,6 +386,9 @@ LIBS += -lsample +

    + Note that LIBS must occur in the Makefile after the inclusion of Makefile.common. +

    From cdavis at mines.edu Fri Jun 3 00:09:12 2011 From: cdavis at mines.edu (Charles Davis) Date: Fri, 03 Jun 2011 05:09:12 -0000 Subject: [llvm-commits] [llvm] r132532 - /llvm/trunk/include/llvm/MC/MCAsmInfo.h Message-ID: <20110603050912.81FF32A6C12C@llvm.org> Author: cdavis Date: Fri Jun 3 00:09:12 2011 New Revision: 132532 URL: http://llvm.org/viewvc/llvm-project?rev=132532&view=rev Log: Treat Win64 EH as a DWARF EH scheme. For GCC-style exceptions, the layout of the handler's data area is similar to a DWARF-format LSDA. (It is, in fact, a 32-bit pointer to the personality routine followed by the DWARF LSDA.) Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h Modified: llvm/trunk/include/llvm/MC/MCAsmInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCAsmInfo.h?rev=132532&r1=132531&r2=132532&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCAsmInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCAsmInfo.h Fri Jun 3 00:09:12 2011 @@ -460,7 +460,8 @@ bool isExceptionHandlingDwarf() const { return (ExceptionsType == ExceptionHandling::DwarfCFI || - ExceptionsType == ExceptionHandling::ARM); + ExceptionsType == ExceptionHandling::ARM || + ExceptionsType == ExceptionHandling::Win64); } bool doesDwarfUsesInlineInfoSection() const { return DwarfUsesInlineInfoSection; From mcrosier at apple.com Fri Jun 3 00:09:12 2011 From: mcrosier at apple.com (Chad Rosier) Date: Fri, 03 Jun 2011 05:09:12 -0000 Subject: [llvm-commits] [llvm] r132533 - in /llvm/trunk/lib/Bitcode: Reader/BitcodeReader.cpp Writer/BitcodeWriter.cpp Writer/ValueEnumerator.cpp Writer/ValueEnumerator.h Message-ID: <20110603050913.21E6F2A6C12D@llvm.org> Author: mcrosier Date: Fri Jun 3 00:09:12 2011 New Revision: 132533 URL: http://llvm.org/viewvc/llvm-project?rev=132533&view=rev Log: Whitespace and other cleanup. Functionallity unchanged. Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=132533&r1=132532&r2=132533&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Fri Jun 3 00:09:12 2011 @@ -1852,7 +1852,6 @@ FunctionBBs[i] = BasicBlock::Create(Context, "", F); CurBB = FunctionBBs[0]; continue; - case bitc::FUNC_CODE_DEBUG_LOC_AGAIN: // DEBUG_LOC_AGAIN // This record indicates that the last instruction is at the same Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=132533&r1=132532&r2=132533&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Fri Jun 3 00:09:12 2011 @@ -100,8 +100,6 @@ } } - - static void WriteStringRecord(unsigned Code, const std::string &Str, unsigned AbbrevToUse, BitstreamWriter &Stream) { SmallVector Vals; @@ -447,7 +445,6 @@ Vals.clear(); } - // Emit the alias information. for (Module::const_alias_iterator AI = M->alias_begin(), E = M->alias_end(); AI != E; ++AI) { @@ -1208,7 +1205,7 @@ static void WriteFunction(const Function &F, ValueEnumerator &VE, BitstreamWriter &Stream) { Stream.EnterSubblock(bitc::FUNCTION_BLOCK_ID, 4); - VE.incorporateFunction(F); + VE.IncorporateFunction(F); SmallVector Vals; @@ -1272,7 +1269,7 @@ if (NeedsMetadataAttachment) WriteMetadataAttachment(F, VE, Stream); - VE.purgeFunction(); + VE.PurgeFunction(); Stream.ExitBlock(); } @@ -1512,9 +1509,9 @@ WriteModuleMetadata(M, VE, Stream); // Emit function bodies. - for (Module::const_iterator I = M->begin(), E = M->end(); I != E; ++I) - if (!I->isDeclaration()) - WriteFunction(*I, VE, Stream); + for (Module::const_iterator F = M->begin(), E = M->end(); F != E; ++F) + if (!F->isDeclaration()) + WriteFunction(*F, VE, Stream); // Emit metadata. WriteModuleMetadataStore(M, Stream); Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp?rev=132533&r1=132532&r2=132533&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp Fri Jun 3 00:09:12 2011 @@ -452,8 +452,7 @@ } } - -void ValueEnumerator::incorporateFunction(const Function &F) { +void ValueEnumerator::IncorporateFunction(const Function &F) { InstructionCount = 0; NumModuleValues = Values.size(); NumModuleMDValues = MDValues.size(); @@ -517,7 +516,7 @@ EnumerateFunctionLocalMetadata(FnLocalMDVector[i]); } -void ValueEnumerator::purgeFunction() { +void ValueEnumerator::PurgeFunction() { /// Remove purged values from the ValueMap. for (unsigned i = NumModuleValues, e = Values.size(); i != e; ++i) ValueMap.erase(Values[i].first); Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h?rev=132533&r1=132532&r2=132533&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h (original) +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h Fri Jun 3 00:09:12 2011 @@ -127,11 +127,11 @@ /// should only be used by rare constructs such as address-of-label. unsigned getGlobalBasicBlockID(const BasicBlock *BB) const; - /// incorporateFunction/purgeFunction - If you'd like to deal with a function, + /// IncorporateFunction/PurgeFunction - If you'd like to deal with a function, /// use these two methods to get its data into the ValueEnumerator! /// - void incorporateFunction(const Function &F); - void purgeFunction(); + void IncorporateFunction(const Function &F); + void PurgeFunction(); private: void OptimizeConstants(unsigned CstStart, unsigned CstEnd); From clattner at apple.com Fri Jun 3 01:07:02 2011 From: clattner at apple.com (Chris Lattner) Date: Thu, 02 Jun 2011 23:07:02 -0700 Subject: [llvm-commits] [llvm] r132533 - in /llvm/trunk/lib/Bitcode: Reader/BitcodeReader.cpp Writer/BitcodeWriter.cpp Writer/ValueEnumerator.cpp Writer/ValueEnumerator.h In-Reply-To: <20110603050913.21E6F2A6C12D@llvm.org> References: <20110603050913.21E6F2A6C12D@llvm.org> Message-ID: <9D5C371E-6985-4084-B274-D7022830D7F0@apple.com> On Jun 2, 2011, at 10:09 PM, Chad Rosier wrote: > Author: mcrosier > Date: Fri Jun 3 00:09:12 2011 > New Revision: 132533 > > URL: http://llvm.org/viewvc/llvm-project?rev=132533&view=rev > Log: > Whitespace and other cleanup. Functionallity unchanged. Hi Chad, FYI, the lowercase function names were intended. The naming convention (which was only recently adopted, thus the codebase is still not consistent) is described here: http://llvm.org/docs/CodingStandards.html#ll_naming -Chris > > Modified: > llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp > llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp > llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp > llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h > > Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=132533&r1=132532&r2=132533&view=diff > ============================================================================== > --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) > +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Fri Jun 3 00:09:12 2011 > @@ -1852,7 +1852,6 @@ > FunctionBBs[i] = BasicBlock::Create(Context, "", F); > CurBB = FunctionBBs[0]; > continue; > - > > case bitc::FUNC_CODE_DEBUG_LOC_AGAIN: // DEBUG_LOC_AGAIN > // This record indicates that the last instruction is at the same > > Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=132533&r1=132532&r2=132533&view=diff > ============================================================================== > --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) > +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Fri Jun 3 00:09:12 2011 > @@ -100,8 +100,6 @@ > } > } > > - > - > static void WriteStringRecord(unsigned Code, const std::string &Str, > unsigned AbbrevToUse, BitstreamWriter &Stream) { > SmallVector Vals; > @@ -447,7 +445,6 @@ > Vals.clear(); > } > > - > // Emit the alias information. > for (Module::const_alias_iterator AI = M->alias_begin(), E = M->alias_end(); > AI != E; ++AI) { > @@ -1208,7 +1205,7 @@ > static void WriteFunction(const Function &F, ValueEnumerator &VE, > BitstreamWriter &Stream) { > Stream.EnterSubblock(bitc::FUNCTION_BLOCK_ID, 4); > - VE.incorporateFunction(F); > + VE.IncorporateFunction(F); > > SmallVector Vals; > > @@ -1272,7 +1269,7 @@ > > if (NeedsMetadataAttachment) > WriteMetadataAttachment(F, VE, Stream); > - VE.purgeFunction(); > + VE.PurgeFunction(); > Stream.ExitBlock(); > } > > @@ -1512,9 +1509,9 @@ > WriteModuleMetadata(M, VE, Stream); > > // Emit function bodies. > - for (Module::const_iterator I = M->begin(), E = M->end(); I != E; ++I) > - if (!I->isDeclaration()) > - WriteFunction(*I, VE, Stream); > + for (Module::const_iterator F = M->begin(), E = M->end(); F != E; ++F) > + if (!F->isDeclaration()) > + WriteFunction(*F, VE, Stream); > > // Emit metadata. > WriteModuleMetadataStore(M, Stream); > > Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp?rev=132533&r1=132532&r2=132533&view=diff > ============================================================================== > --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp (original) > +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp Fri Jun 3 00:09:12 2011 > @@ -452,8 +452,7 @@ > } > } > > - > -void ValueEnumerator::incorporateFunction(const Function &F) { > +void ValueEnumerator::IncorporateFunction(const Function &F) { > InstructionCount = 0; > NumModuleValues = Values.size(); > NumModuleMDValues = MDValues.size(); > @@ -517,7 +516,7 @@ > EnumerateFunctionLocalMetadata(FnLocalMDVector[i]); > } > > -void ValueEnumerator::purgeFunction() { > +void ValueEnumerator::PurgeFunction() { > /// Remove purged values from the ValueMap. > for (unsigned i = NumModuleValues, e = Values.size(); i != e; ++i) > ValueMap.erase(Values[i].first); > > Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h?rev=132533&r1=132532&r2=132533&view=diff > ============================================================================== > --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h (original) > +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h Fri Jun 3 00:09:12 2011 > @@ -127,11 +127,11 @@ > /// should only be used by rare constructs such as address-of-label. > unsigned getGlobalBasicBlockID(const BasicBlock *BB) const; > > - /// incorporateFunction/purgeFunction - If you'd like to deal with a function, > + /// IncorporateFunction/PurgeFunction - If you'd like to deal with a function, > /// use these two methods to get its data into the ValueEnumerator! > /// > - void incorporateFunction(const Function &F); > - void purgeFunction(); > + void IncorporateFunction(const Function &F); > + void PurgeFunction(); > > private: > void OptimizeConstants(unsigned CstStart, unsigned CstEnd); > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From nicholas at mxc.ca Fri Jun 3 01:27:15 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 03 Jun 2011 06:27:15 -0000 Subject: [llvm-commits] [llvm] r132535 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnswitch.cpp test/Transforms/LoopUnswitch/2011-06-02-CritSwitch.ll Message-ID: <20110603062715.A48A72A6C12C@llvm.org> Author: nicholas Date: Fri Jun 3 01:27:15 2011 New Revision: 132535 URL: http://llvm.org/viewvc/llvm-project?rev=132535&view=rev Log: Bail on unswitching a switch statement for a case with a critical edge. We name which edge to split by pred/succ pair, which means that we can end up splitting the wrong edge (by case value) in the switch statement entirely. Fixes PR10031! Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-06-02-CritSwitch.ll Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=132535&r1=132534&r2=132535&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Fri Jun 3 01:27:15 2011 @@ -258,6 +258,7 @@ if (LoopCond && SI->getNumCases() > 1) { // Find a value to unswitch on: // FIXME: this should chose the most expensive case! + // FIXME: scan for a case with a non-critical edge? Constant *UnswitchVal = SI->getCaseValue(1); // Do not process same value again and again. if (!UnswitchedVals.insert(UnswitchVal)) @@ -560,6 +561,8 @@ BasicBlock *ExitBlock = ExitBlocks[i]; SmallVector Preds(pred_begin(ExitBlock), pred_end(ExitBlock)); + // Although SplitBlockPredecessors doesn't preserve loop-simplify in + // general, if we call it on all predecessors of all exits then it does. SplitBlockPredecessors(ExitBlock, Preds.data(), Preds.size(), ".us-lcssa", this); } @@ -915,10 +918,11 @@ // Found a dead case value. Don't remove PHI nodes in the // successor if they become single-entry, those PHI nodes may // be in the Users list. - + BasicBlock *Switch = SI->getParent(); BasicBlock *SISucc = SI->getSuccessor(DeadCase); BasicBlock *Latch = L->getLoopLatch(); + if (!SI->findCaseDest(SISucc)) continue; // Edge is critical. // If the DeadCase successor dominates the loop latch, then the // transformation isn't safe since it will delete the sole predecessor edge // to the latch. Added: llvm/trunk/test/Transforms/LoopUnswitch/2011-06-02-CritSwitch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopUnswitch/2011-06-02-CritSwitch.ll?rev=132535&view=auto ============================================================================== --- llvm/trunk/test/Transforms/LoopUnswitch/2011-06-02-CritSwitch.ll (added) +++ llvm/trunk/test/Transforms/LoopUnswitch/2011-06-02-CritSwitch.ll Fri Jun 3 01:27:15 2011 @@ -0,0 +1,28 @@ +; RUN: opt -loop-unswitch -disable-output +; PR10031 + +define i32 @test(i32 %command) { +entry: + br label %tailrecurse + +tailrecurse: ; preds = %if.then14, %tailrecurse, %entry + br i1 undef, label %if.then, label %tailrecurse + +if.then: ; preds = %tailrecurse + switch i32 %command, label %sw.bb [ + i32 2, label %land.lhs.true + i32 0, label %land.lhs.true + ] + +land.lhs.true: ; preds = %if.then, %if.then + br i1 undef, label %sw.bb, label %if.then14 + +if.then14: ; preds = %land.lhs.true + switch i32 %command, label %tailrecurse [ + i32 0, label %sw.bb + i32 1, label %sw.bb + ] + +sw.bb: ; preds = %if.then14 + unreachable +} From nicholas at mxc.ca Fri Jun 3 03:25:39 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 03 Jun 2011 08:25:39 -0000 Subject: [llvm-commits] [llvm] r132537 - /llvm/trunk/utils/TableGen/Record.cpp Message-ID: <20110603082539.3748D2A6C12C@llvm.org> Author: nicholas Date: Fri Jun 3 03:25:39 2011 New Revision: 132537 URL: http://llvm.org/viewvc/llvm-project?rev=132537&view=rev Log: Rework the logic to not rely on undefined behaviour (1LL << 64). Also simplify. Modified: llvm/trunk/utils/TableGen/Record.cpp Modified: llvm/trunk/utils/TableGen/Record.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=132537&r1=132536&r2=132537&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.cpp (original) +++ llvm/trunk/utils/TableGen/Record.cpp Fri Jun 3 03:25:39 2011 @@ -68,14 +68,9 @@ /// canFitInBitfield - Return true if the number of bits is large enough to hold /// the integer value. static bool canFitInBitfield(int64_t Value, unsigned NumBits) { - if (Value >= 0) { - if (Value & ~((1LL << NumBits) - 1)) - return false; - } else if ((Value >> NumBits) != -1 || (Value & (1LL << (NumBits-1))) == 0) { - return false; - } - - return true; + // For example, with NumBits == 4, we permit Values from [-7 .. 15]. + return (NumBits >= sizeof(Value) * 8) || + (Value >> NumBits == 0) || (Value >> (NumBits-1) == -1); } /// convertValue from Int initializer to bits type: Split the integer up into the From rdivacky at freebsd.org Fri Jun 3 10:47:49 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Fri, 03 Jun 2011 15:47:49 -0000 Subject: [llvm-commits] [llvm] r132552 - in /llvm/trunk: lib/Target/PowerPC/PPCHazardRecognizers.cpp lib/Target/PowerPC/PPCISelDAGToDAG.cpp lib/Target/PowerPC/PPCISelLowering.cpp lib/Target/PowerPC/PPCInstr64Bit.td test/CodeGen/PowerPC/indirectbr.ll Message-ID: <20110603154749.4F6CF2A6C12C@llvm.org> Author: rdivacky Date: Fri Jun 3 10:47:49 2011 New Revision: 132552 URL: http://llvm.org/viewvc/llvm-project?rev=132552&view=rev Log: Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant. - Check for MTCTR8 in addition to MTCTR when looking up a hazard. - When lowering an indirect call use CTR8 when targeting 64bit. - Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND. The last change fixes PR8487. With those changes, we are able to compile a running "ls" and "sh" on FreeBSD/PowerPC64. Modified: llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll Modified: llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp?rev=132552&r1=132551&r2=132552&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp Fri Jun 3 10:47:49 2011 @@ -233,7 +233,7 @@ unsigned Opcode = Node->getMachineOpcode(); // Update structural hazard information. - if (Opcode == PPC::MTCTR) HasCTRSet = true; + if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true; // Track the address stored to. if (isStore) { Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=132552&r1=132551&r2=132552&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Fri Jun 3 10:47:49 2011 @@ -1057,9 +1057,10 @@ SDValue Chain = N->getOperand(0); SDValue Target = N->getOperand(1); unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8; + unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8; Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target, Chain), 0); - return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain); + return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain); } } Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=132552&r1=132551&r2=132552&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Fri Jun 3 10:47:49 2011 @@ -2562,7 +2562,7 @@ Callee.setNode(0); // Add CTR register as callee so a bctr can be emitted later. if (isTailCall) - Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT)); + Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT)); } // If this is a direct call, pass the chain and the callee. Modified: llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td?rev=132552&r1=132551&r2=132552&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstr64Bit.td Fri Jun 3 10:47:49 2011 @@ -190,10 +190,15 @@ let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, - isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in -def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, - Requires<[In64BitMode]>; + isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in { + let isReturn = 1 in { + def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, + Requires<[In64BitMode]>; + } + def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, + Requires<[In64BitMode]>; +} let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, Modified: llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll?rev=132552&r1=132551&r2=132552&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll (original) +++ llvm/trunk/test/CodeGen/PowerPC/indirectbr.ll Fri Jun 3 10:47:49 2011 @@ -1,5 +1,6 @@ ; RUN: llc < %s -relocation-model=pic -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s -check-prefix=PIC ; RUN: llc < %s -relocation-model=static -march=ppc32 -mtriple=powerpc-apple-darwin | FileCheck %s -check-prefix=STATIC +; RUN: llc < %s -relocation-model=pic -march=ppc64 -mtriple=powerpc64-apple-darwin | FileCheck %s -check-prefix=PPC64 @nextaddr = global i8* null ; [#uses=2] @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1] @@ -7,6 +8,7 @@ define internal i32 @foo(i32 %i) nounwind { ; PIC: foo: ; STATIC: foo: +; PPC64: foo: entry: %0 = load i8** @nextaddr, align 4 ; [#uses=2] %1 = icmp eq i8* %0, null ; [#uses=1] @@ -18,6 +20,8 @@ ; PIC-NEXT: bctr ; STATIC: mtctr ; STATIC-NEXT: bctr +; PPC64: mtctr +; PPC64-NEXT: bctr indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1] bb3: ; preds = %entry From xuzhongxing at foxmail.com Fri Jun 3 03:29:51 2011 From: xuzhongxing at foxmail.com (Zhongxing Xu) Date: Fri, 03 Jun 2011 08:29:51 -0000 Subject: [llvm-commits] [llvm] r132538 - /llvm/trunk/lib/Support/FoldingSet.cpp Message-ID: <20110603082951.5E0C32A6C12C@llvm.org> Author: zhongxingxu Date: Fri Jun 3 03:29:51 2011 New Revision: 132538 URL: http://llvm.org/viewvc/llvm-project?rev=132538&view=rev Log: singed int causes signed extension, which contradicts the intention to pick up integers with high 32 bits being zero. Modified: llvm/trunk/lib/Support/FoldingSet.cpp Modified: llvm/trunk/lib/Support/FoldingSet.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FoldingSet.cpp?rev=132538&r1=132537&r2=132538&view=diff ============================================================================== --- llvm/trunk/lib/Support/FoldingSet.cpp (original) +++ llvm/trunk/lib/Support/FoldingSet.cpp Fri Jun 3 03:29:51 2011 @@ -92,7 +92,7 @@ } void FoldingSetNodeID::AddInteger(unsigned long long I) { AddInteger(unsigned(I)); - if ((uint64_t)(int)I != I) + if ((uint64_t)(unsigned)I != I) Bits.push_back(unsigned(I >> 32)); } From eli.friedman at gmail.com Fri Jun 3 12:00:20 2011 From: eli.friedman at gmail.com (Eli Friedman) Date: Fri, 3 Jun 2011 10:00:20 -0700 Subject: [llvm-commits] [llvm] r132504 - in /llvm/trunk/test: FrontendC++/unnamed-addr.cpp FrontendC/unnamed-addr.c In-Reply-To: <20110602222615.7723B2A6C12C@llvm.org> References: <20110602222615.7723B2A6C12C@llvm.org> Message-ID: On Thu, Jun 2, 2011 at 3:26 PM, Bill Wendling wrote: > Author: void > Date: Thu Jun ?2 17:26:15 2011 > New Revision: 132504 > > URL: http://llvm.org/viewvc/llvm-project?rev=132504&view=rev > Log: > This should have been a C++ testcase. > > Added: > ? ?llvm/trunk/test/FrontendC++/unnamed-addr.cpp > ? ? ?- copied, changed from r132495, llvm/trunk/test/FrontendC/unnamed-addr.c > Removed: > ? ?llvm/trunk/test/FrontendC/unnamed-addr.c > This test is apparently failing on Linux; see, for example, http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost/builds/2721/steps/test.llvm.stage2/logs/unnamed-addr.cpp . -Eli > Copied: llvm/trunk/test/FrontendC++/unnamed-addr.cpp (from r132495, llvm/trunk/test/FrontendC/unnamed-addr.c) > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/unnamed-addr.cpp?p2=llvm/trunk/test/FrontendC%2B%2B/unnamed-addr.cpp&p1=llvm/trunk/test/FrontendC/unnamed-addr.c&r1=132495&r2=132504&rev=132504&view=diff > ============================================================================== > --- llvm/trunk/test/FrontendC/unnamed-addr.c (original) > +++ llvm/trunk/test/FrontendC++/unnamed-addr.cpp Thu Jun ?2 17:26:15 2011 > @@ -1,5 +1,6 @@ > -// RUN: %llvmgcc -S %s -o - | FileCheck %s > +// RUN: %llvmgxx -S %s -o - | FileCheck %s > ?// > +extern "C" { > ?typedef struct __TestResult TestResult; > ?typedef struct __TestResult* TestResultRef; > > @@ -57,6 +58,7 @@ > ?}; > > ?extern const TestImplement TestCallerImplement; > +} > > ?void PassToFunction(const TestImplement*); > > @@ -81,7 +83,7 @@ > ? return self->numberOfFixtuers; > ?} > > -// CHECK: @C.0.1526 = internal unnamed_addr constant > +// CHECK: @_ZZ14TestCaller_runP12__TestCallerP12__TestResultE3C.0 = internal unnamed_addr constant > ?// CHECK-NOT: @TestCaseImplement = external unnamed_addr constant %struct.TestImplement > ?// CHECK: @TestCaseImplement = external constant %struct.TestImplement > ?const TestImplement TestCallerImplement = { > > Removed: llvm/trunk/test/FrontendC/unnamed-addr.c > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/unnamed-addr.c?rev=132503&view=auto > ============================================================================== > --- llvm/trunk/test/FrontendC/unnamed-addr.c (original) > +++ llvm/trunk/test/FrontendC/unnamed-addr.c (removed) > @@ -1,91 +0,0 @@ > -// RUN: %llvmgcc -S %s -o - | FileCheck %s > -// > -typedef struct __TestResult TestResult; > -typedef struct __TestResult* TestResultRef; > - > -typedef struct __TestImplement TestImplement; > -typedef struct __TestImplement* TestImplementRef; > - > -typedef char*(*TestNameFunction)(void*); > -typedef void(*TestRunFunction)(void*,TestResult*); > -typedef int(*TestCountTestCasesFunction)(void*); > - > -struct __TestImplement { > - ? ?TestNameFunction name; > - ? ?TestRunFunction run; > - ? ?TestCountTestCasesFunction countTestCases; > -}; > - > -typedef struct __Test Test; > -typedef struct __Test* TestRef; > - > -struct __Test { > - ? ?TestImplement* isa; > -}; > - > -typedef struct __TestCase TestCase; > -typedef struct __TestCase* TestCaseRef; > - > -struct __TestCase { > - ? ?TestImplement* isa; > - ? ?const char *name; > - ? ?void(*setUp)(void); > - ? ?void(*tearDown)(void); > - ? ?void(*runTest)(void); > -}; > - > -extern const TestImplement TestCaseImplement; > - > -typedef struct __TestFixture TestFixture; > -typedef struct __TestFixture* TestFixtureRef; > - > -struct __TestFixture { > - ? ?const char *name; > - ? ?void(*test)(void); > -}; > - > -typedef struct __TestCaller TestCaller; > -typedef struct __TestCaller* TestCallerRef; > - > -struct __TestCaller { > - ? ?TestImplement* isa; > - ? ?const char *name; > - ? ?void(*setUp)(void); > - ? ?void(*tearDown)(void); > - ? ?int numberOfFixtuers; > - ? ?TestFixture *fixtuers; > -}; > - > -extern const TestImplement TestCallerImplement; > - > -void PassToFunction(const TestImplement*); > - > -const char* TestCaller_name(TestCaller* self) { > - ?return self->name; > -} > - > -void TestCaller_run(TestCaller* self,TestResult* result) { > - ?TestCase cs = { (TestImplement*)&TestCaseImplement, 0, 0, 0, 0, }; > - ?int i; > - ?cs.setUp = self->setUp; > - ?cs.tearDown = self->tearDown; > - ?for (i=0; inumberOfFixtuers; i++) { > - ? ?cs.name = self->fixtuers[i].name; > - ? ?cs.runTest = self->fixtuers[i].test; > - ? ?((Test*)(void *)&cs)->isa->run((void *)&cs,result); > - ?} > -} > - > -int TestCaller_countTestCases(TestCaller* self) { > - ?PassToFunction(&TestCallerImplement); > - ?return self->numberOfFixtuers; > -} > - > -// CHECK: @C.0.1526 = internal unnamed_addr constant > -// CHECK-NOT: @TestCaseImplement = external unnamed_addr constant %struct.TestImplement > -// CHECK: @TestCaseImplement = external constant %struct.TestImplement > -const TestImplement TestCallerImplement = { > - ?(TestNameFunction)TestCaller_name, > - ?(TestRunFunction)TestCaller_run, > - ?(TestCountTestCasesFunction)TestCaller_countTestCases, > -}; > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From mcrosier at apple.com Fri Jun 3 12:02:19 2011 From: mcrosier at apple.com (Chad Rosier) Date: Fri, 03 Jun 2011 17:02:19 -0000 Subject: [llvm-commits] [llvm] r132555 - in /llvm/trunk/lib/Bitcode/Writer: BitcodeWriter.cpp ValueEnumerator.cpp ValueEnumerator.h Message-ID: <20110603170219.6A14F2A6C12C@llvm.org> Author: mcrosier Date: Fri Jun 3 12:02:19 2011 New Revision: 132555 URL: http://llvm.org/viewvc/llvm-project?rev=132555&view=rev Log: Revert name change from r132533. Lower case naming was intended per style guidelines. Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=132555&r1=132554&r2=132555&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Fri Jun 3 12:02:19 2011 @@ -1205,7 +1205,7 @@ static void WriteFunction(const Function &F, ValueEnumerator &VE, BitstreamWriter &Stream) { Stream.EnterSubblock(bitc::FUNCTION_BLOCK_ID, 4); - VE.IncorporateFunction(F); + VE.incorporateFunction(F); SmallVector Vals; @@ -1269,7 +1269,7 @@ if (NeedsMetadataAttachment) WriteMetadataAttachment(F, VE, Stream); - VE.PurgeFunction(); + VE.purgeFunction(); Stream.ExitBlock(); } Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp?rev=132555&r1=132554&r2=132555&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp (original) +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp Fri Jun 3 12:02:19 2011 @@ -452,7 +452,7 @@ } } -void ValueEnumerator::IncorporateFunction(const Function &F) { +void ValueEnumerator::incorporateFunction(const Function &F) { InstructionCount = 0; NumModuleValues = Values.size(); NumModuleMDValues = MDValues.size(); @@ -516,7 +516,7 @@ EnumerateFunctionLocalMetadata(FnLocalMDVector[i]); } -void ValueEnumerator::PurgeFunction() { +void ValueEnumerator::purgeFunction() { /// Remove purged values from the ValueMap. for (unsigned i = NumModuleValues, e = Values.size(); i != e; ++i) ValueMap.erase(Values[i].first); Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h?rev=132555&r1=132554&r2=132555&view=diff ============================================================================== --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h (original) +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h Fri Jun 3 12:02:19 2011 @@ -127,11 +127,11 @@ /// should only be used by rare constructs such as address-of-label. unsigned getGlobalBasicBlockID(const BasicBlock *BB) const; - /// IncorporateFunction/PurgeFunction - If you'd like to deal with a function, + /// incorporateFunction/purgeFunction - If you'd like to deal with a function, /// use these two methods to get its data into the ValueEnumerator! /// - void IncorporateFunction(const Function &F); - void PurgeFunction(); + void incorporateFunction(const Function &F); + void purgeFunction(); private: void OptimizeConstants(unsigned CstStart, unsigned CstEnd); From dpatel at apple.com Fri Jun 3 12:04:51 2011 From: dpatel at apple.com (Devang Patel) Date: Fri, 03 Jun 2011 17:04:51 -0000 Subject: [llvm-commits] [llvm] r132556 - in /llvm/trunk: include/llvm/Analysis/DIBuilder.h lib/Analysis/DIBuilder.cpp Message-ID: <20110603170451.D0CAD2A6C12C@llvm.org> Author: dpatel Date: Fri Jun 3 12:04:51 2011 New Revision: 132556 URL: http://llvm.org/viewvc/llvm-project?rev=132556&view=rev Log: A typedef's context is not the same as type's context. It is the context of typedef decl itself. Use extra parameter to communicate this to DIBuilder. Modified: llvm/trunk/include/llvm/Analysis/DIBuilder.h llvm/trunk/lib/Analysis/DIBuilder.cpp Modified: llvm/trunk/include/llvm/Analysis/DIBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DIBuilder.h?rev=132556&r1=132555&r2=132556&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/DIBuilder.h (original) +++ llvm/trunk/include/llvm/Analysis/DIBuilder.h Fri Jun 3 12:04:51 2011 @@ -117,8 +117,9 @@ /// @param Name Typedef name. /// @param File File where this type is defined. /// @param LineNo Line number. + /// @param Context The surrounding context for the typedef. DIType createTypedef(DIType Ty, StringRef Name, DIFile File, - unsigned LineNo); + unsigned LineNo, DIDescriptor Context); /// createFriend - Create debugging information entry for a 'friend'. DIType createFriend(DIType Ty, DIType FriendTy); Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=132556&r1=132555&r2=132556&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/DIBuilder.cpp (original) +++ llvm/trunk/lib/Analysis/DIBuilder.cpp Fri Jun 3 12:04:51 2011 @@ -160,12 +160,12 @@ /// createTypedef - Create debugging information entry for a typedef. DIType DIBuilder::createTypedef(DIType Ty, StringRef Name, DIFile File, - unsigned LineNo) { + unsigned LineNo, DIDescriptor Context) { // typedefs are encoded in DIDerivedType format. assert(Ty.Verify() && "Invalid typedef type!"); Value *Elts[] = { GetTagConstant(VMContext, dwarf::DW_TAG_typedef), - Ty.getContext(), + Context, MDString::get(VMContext, Name), File, ConstantInt::get(Type::getInt32Ty(VMContext), LineNo), From mcrosier at apple.com Fri Jun 3 12:10:23 2011 From: mcrosier at apple.com (Chad Rosier) Date: Fri, 03 Jun 2011 10:10:23 -0700 Subject: [llvm-commits] [llvm] r132533 - in /llvm/trunk/lib/Bitcode: Reader/BitcodeReader.cpp Writer/BitcodeWriter.cpp Writer/ValueEnumerator.cpp Writer/ValueEnumerator.h In-Reply-To: <9D5C371E-6985-4084-B274-D7022830D7F0@apple.com> References: <20110603050913.21E6F2A6C12D@llvm.org> <9D5C371E-6985-4084-B274-D7022830D7F0@apple.com> Message-ID: On Jun 2, 2011, at 11:07 PM, Chris Lattner wrote: > > On Jun 2, 2011, at 10:09 PM, Chad Rosier wrote: > >> Author: mcrosier >> Date: Fri Jun 3 00:09:12 2011 >> New Revision: 132533 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132533&view=rev >> Log: >> Whitespace and other cleanup. Functionallity unchanged. > > Hi Chad, > > FYI, the lowercase function names were intended. The naming convention (which was only recently adopted, thus the codebase is still not consistent) is described here: > http://llvm.org/docs/CodingStandards.html#ll_naming > Fixed in revision 132555. Chad > -Chris > > >> >> Modified: >> llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp >> llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp >> llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp >> llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h >> >> Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=132533&r1=132532&r2=132533&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original) >> +++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Fri Jun 3 00:09:12 2011 >> @@ -1852,7 +1852,6 @@ >> FunctionBBs[i] = BasicBlock::Create(Context, "", F); >> CurBB = FunctionBBs[0]; >> continue; >> - >> >> case bitc::FUNC_CODE_DEBUG_LOC_AGAIN: // DEBUG_LOC_AGAIN >> // This record indicates that the last instruction is at the same >> >> Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=132533&r1=132532&r2=132533&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original) >> +++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Fri Jun 3 00:09:12 2011 >> @@ -100,8 +100,6 @@ >> } >> } >> >> - >> - >> static void WriteStringRecord(unsigned Code, const std::string &Str, >> unsigned AbbrevToUse, BitstreamWriter &Stream) { >> SmallVector Vals; >> @@ -447,7 +445,6 @@ >> Vals.clear(); >> } >> >> - >> // Emit the alias information. >> for (Module::const_alias_iterator AI = M->alias_begin(), E = M->alias_end(); >> AI != E; ++AI) { >> @@ -1208,7 +1205,7 @@ >> static void WriteFunction(const Function &F, ValueEnumerator &VE, >> BitstreamWriter &Stream) { >> Stream.EnterSubblock(bitc::FUNCTION_BLOCK_ID, 4); >> - VE.incorporateFunction(F); >> + VE.IncorporateFunction(F); >> >> SmallVector Vals; >> >> @@ -1272,7 +1269,7 @@ >> >> if (NeedsMetadataAttachment) >> WriteMetadataAttachment(F, VE, Stream); >> - VE.purgeFunction(); >> + VE.PurgeFunction(); >> Stream.ExitBlock(); >> } >> >> @@ -1512,9 +1509,9 @@ >> WriteModuleMetadata(M, VE, Stream); >> >> // Emit function bodies. >> - for (Module::const_iterator I = M->begin(), E = M->end(); I != E; ++I) >> - if (!I->isDeclaration()) >> - WriteFunction(*I, VE, Stream); >> + for (Module::const_iterator F = M->begin(), E = M->end(); F != E; ++F) >> + if (!F->isDeclaration()) >> + WriteFunction(*F, VE, Stream); >> >> // Emit metadata. >> WriteModuleMetadataStore(M, Stream); >> >> Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp?rev=132533&r1=132532&r2=132533&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp (original) >> +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.cpp Fri Jun 3 00:09:12 2011 >> @@ -452,8 +452,7 @@ >> } >> } >> >> - >> -void ValueEnumerator::incorporateFunction(const Function &F) { >> +void ValueEnumerator::IncorporateFunction(const Function &F) { >> InstructionCount = 0; >> NumModuleValues = Values.size(); >> NumModuleMDValues = MDValues.size(); >> @@ -517,7 +516,7 @@ >> EnumerateFunctionLocalMetadata(FnLocalMDVector[i]); >> } >> >> -void ValueEnumerator::purgeFunction() { >> +void ValueEnumerator::PurgeFunction() { >> /// Remove purged values from the ValueMap. >> for (unsigned i = NumModuleValues, e = Values.size(); i != e; ++i) >> ValueMap.erase(Values[i].first); >> >> Modified: llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h?rev=132533&r1=132532&r2=132533&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h (original) >> +++ llvm/trunk/lib/Bitcode/Writer/ValueEnumerator.h Fri Jun 3 00:09:12 2011 >> @@ -127,11 +127,11 @@ >> /// should only be used by rare constructs such as address-of-label. >> unsigned getGlobalBasicBlockID(const BasicBlock *BB) const; >> >> - /// incorporateFunction/purgeFunction - If you'd like to deal with a function, >> + /// IncorporateFunction/PurgeFunction - If you'd like to deal with a function, >> /// use these two methods to get its data into the ValueEnumerator! >> /// >> - void incorporateFunction(const Function &F); >> - void purgeFunction(); >> + void IncorporateFunction(const Function &F); >> + void PurgeFunction(); >> >> private: >> void OptimizeConstants(unsigned CstStart, unsigned CstEnd); >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From hans at hanshq.net Fri Jun 3 12:15:37 2011 From: hans at hanshq.net (Hans Wennborg) Date: Fri, 03 Jun 2011 17:15:37 -0000 Subject: [llvm-commits] [llvm] r132558 - /llvm/trunk/lib/Analysis/Loads.cpp Message-ID: <20110603171537.882AA2A6C12C@llvm.org> Author: hans Date: Fri Jun 3 12:15:37 2011 New Revision: 132558 URL: http://llvm.org/viewvc/llvm-project?rev=132558&view=rev Log: Test commit. Modified: llvm/trunk/lib/Analysis/Loads.cpp Modified: llvm/trunk/lib/Analysis/Loads.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Loads.cpp?rev=132558&r1=132557&r2=132558&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/Loads.cpp (original) +++ llvm/trunk/lib/Analysis/Loads.cpp Fri Jun 3 12:15:37 2011 @@ -31,7 +31,7 @@ static bool AreEquivalentAddressValues(const Value *A, const Value *B) { // Test if the values are trivially equivalent. if (A == B) return true; - + // Test if the values come from identical arithmetic instructions. // Use isIdenticalToWhenDefined instead of isIdenticalTo because // this function is only used when one address use dominates the @@ -42,7 +42,7 @@ if (const Instruction *BI = dyn_cast(B)) if (cast(A)->isIdenticalToWhenDefined(BI)) return true; - + // Otherwise they may not be equivalent. return false; } From echristo at apple.com Fri Jun 3 12:21:23 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 03 Jun 2011 17:21:23 -0000 Subject: [llvm-commits] [llvm] r132559 - /llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Message-ID: <20110603172123.9AFF12A6C12C@llvm.org> Author: echristo Date: Fri Jun 3 12:21:23 2011 New Revision: 132559 URL: http://llvm.org/viewvc/llvm-project?rev=132559&view=rev Log: Add a TODO about memory operands. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=132559&r1=132558&r2=132559&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Fri Jun 3 12:21:23 2011 @@ -5735,7 +5735,11 @@ // Memory operands really want the address of the value. If we don't have // an indirect input, put it in the constpool if we can, otherwise spill // it to a stack slot. - + // TODO: This isn't quite right. We need to handle these according to + // the addressing mode that the constraint wants. Also, this may take + // an additional register for the computation and we don't want that + // either. + // If the operand is a float, integer, or vector constant, spill to a // constant pool entry to get its address. const Value *OpVal = OpInfo.CallOperandVal; From echristo at apple.com Fri Jun 3 12:24:37 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 03 Jun 2011 17:24:37 -0000 Subject: [llvm-commits] [llvm] r132561 - in /llvm/trunk: lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/inlineasm3.ll Message-ID: <20110603172437.7A5C22A6C12C@llvm.org> Author: echristo Date: Fri Jun 3 12:24:37 2011 New Revision: 132561 URL: http://llvm.org/viewvc/llvm-project?rev=132561&view=rev Log: Make the Uv constraint a memory operand. This doesn't solve the addressing mode problem mentioned in r132559. Backend part of rdar://9037836 and part of rdar://9119939 Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=132561&r1=132560&r2=132561&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 3 12:24:37 2011 @@ -7265,6 +7265,9 @@ case 'l': return C_RegisterClass; case 'w': return C_RegisterClass; } + } else { + if (Constraint == "Uv") + return C_Memory; } return TargetLowering::getConstraintType(Constraint); } Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=132561&r1=132560&r2=132561&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original) +++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Fri Jun 3 12:24:37 2011 @@ -33,3 +33,11 @@ %asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1, :128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind unreachable } + +; Radar 9037836 & 9119939 + +define i32 @t3() nounwind { +entry: +tail call void asm sideeffect "flds s15, $0 \0A", "^Uv|m,~{s15}"(float 1.000000e+00) nounwind +ret i32 0 +} From aggarwa4 at illinois.edu Fri Jun 3 13:17:04 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 03 Jun 2011 18:17:04 -0000 Subject: [llvm-commits] [poolalloc] r132567 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Message-ID: <20110603181704.176E02A6C12C@llvm.org> Author: aggarwa4 Date: Fri Jun 3 13:17:03 2011 New Revision: 132567 URL: http://llvm.org/viewvc/llvm-project?rev=132567&view=rev Log: In strcpy, account for the NULL terminator too. Improve some debug printing Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=132567&r1=132566&r2=132567&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Fri Jun 3 13:17:03 2011 @@ -142,7 +142,7 @@ /* Check if this an initialized but untyped memory.*/ if (typeNumber != shadow_begin[p]) { if (shadow_begin[p] != 0xFF) { - printf("Type mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p]]); + printf("Type mismatch(%u): %p expecting %s, found %s!\n", tag, ptr, typeNames[typeNumber], typeNames[shadow_begin[p]]); return; } else { /* If so, set type to the type being read. @@ -166,7 +166,7 @@ } #if DEBUG - printf("Load: %p, %p = actual: %u, expect: %u | %lu bytes\n", ptr, (void *)p, typeNumber, shadow_begin[p], size); + printf("Load: %p, %p = actual: %u, expect: %u | %lu bytes %d \n", ptr, (void *)p, typeNumber, shadow_begin[p], size, tag); #endif } @@ -201,7 +201,7 @@ uintptr_t s = maskAddress(srcptr); memcpy(&shadow_begin[d], &shadow_begin[s], size); #if DEBUG - printf("Copy: %p, %p = %u | %lu bytes | %u\n", dstptr, (void *)d, shadow_begin[s], size, tag); + printf("Copy: %p, %p = %u | %lu bytes | %u\n", dstptr, srcptr, shadow_begin[s], size, tag); #endif } @@ -226,5 +226,5 @@ * Initialize metadata for the dst pointer of strcpy */ void trackStrcpyInst(void *dst, void *src, uint32_t tag) { - copyTypeInfo(dst, src, strlen(src), tag); + copyTypeInfo(dst, src, strlen(src)+1, tag); } From aggarwa4 at illinois.edu Fri Jun 3 13:18:12 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 03 Jun 2011 18:18:12 -0000 Subject: [llvm-commits] [poolalloc] r132568 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110603181813.02D852A6C12C@llvm.org> Author: aggarwa4 Date: Fri Jun 3 13:18:12 2011 New Revision: 132568 URL: http://llvm.org/viewvc/llvm-project?rev=132568&view=rev Log: 1. visitAddressTakenFunctions, is only for non var-arg function. The new function created must also be non var-arg. 2. Handle sprintf. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132568&r1=132567&r2=132568&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Fri Jun 3 13:18:12 2011 @@ -460,7 +460,7 @@ } // 2. Create the new function prototype - const FunctionType *NewFTy = FunctionType::get(F.getReturnType(), TP, true); + const FunctionType *NewFTy = FunctionType::get(F.getReturnType(), TP, false); Function *NewF = Function::Create(NewFTy, GlobalValue::InternalLinkage, F.getNameStr() + ".mod", @@ -1397,6 +1397,21 @@ Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; + } else if(F->getNameStr() == std::string("sprintf")) { + CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); + std::vectorArgs; + Args.push_back(BCI); + CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false); + Size->insertAfter(I); + Constant *One = ConstantInt::get(Int64Ty, 1); + Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add, + Size, + One); + NewValue->insertAfter(Size); + Args.push_back(NewValue); + Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + CallInst *CINew = CallInst::Create(trackInitInst, Args.begin(), Args.end()); + CINew->insertAfter(NewValue); } else if(F->getNameStr() == std::string("sscanf")) { // FIXME: Need to look at the format string and check unsigned i = 3; From aggarwa4 at illinois.edu Fri Jun 3 13:28:57 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 03 Jun 2011 18:28:57 -0000 Subject: [llvm-commits] [poolalloc] r132569 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110603182857.0E8982A6C12C@llvm.org> Author: aggarwa4 Date: Fri Jun 3 13:28:56 2011 New Revision: 132569 URL: http://llvm.org/viewvc/llvm-project?rev=132569&view=rev Log: Add more ctype functions. Fixes 197.parser. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=132569&r1=132568&r2=132569&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Fri Jun 3 13:28:56 2011 @@ -1275,6 +1275,24 @@ Constant *F = M.getOrInsertFunction("trackctype", VoidTy, VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); + } else if (F->getNameStr() == std::string("__ctype_toupper_loc")) { + CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy); + BCI->insertAfter(I); + std::vectorArgs; + Args.push_back(BCI); + Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Constant *F = M.getOrInsertFunction("trackctype", VoidTy, VoidPtrTy, Int32Ty, NULL); + CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); + CI->insertAfter(BCI); + } else if (F->getNameStr() == std::string("__ctype_tolower_loc")) { + CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy); + BCI->insertAfter(I); + std::vectorArgs; + Args.push_back(BCI); + Args.push_back(ConstantInt::get(Int32Ty, tagCounter++)); + Constant *F = M.getOrInsertFunction("trackctype", VoidTy, VoidPtrTy, Int32Ty, NULL); + CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); + CI->insertAfter(BCI); } else if (F->getNameStr() == std::string("strcpy")) { std::vector Args; Args.push_back(I->getOperand(1)); From aggarwa4 at illinois.edu Fri Jun 3 13:43:01 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Fri, 03 Jun 2011 18:43:01 -0000 Subject: [llvm-commits] [poolalloc] r132574 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Message-ID: <20110603184301.4D7232A6C12E@llvm.org> Author: aggarwa4 Date: Fri Jun 3 13:43:01 2011 New Revision: 132574 URL: http://llvm.org/viewvc/llvm-project?rev=132574&view=rev Log: Make sure we copy type info for the Null terminator as well. Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=132574&r1=132573&r2=132574&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Fri Jun 3 13:43:01 2011 @@ -218,7 +218,7 @@ */ void trackStrncpyInst(void *dst, void *src, uint64_t size, uint32_t tag) { if(strlen(src) < size) - size = strlen(src); + size = strlen(src) + 1; copyTypeInfo(dst, src, size, tag); } From isanbard at gmail.com Fri Jun 3 14:21:05 2011 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 03 Jun 2011 19:21:05 -0000 Subject: [llvm-commits] [llvm] r132575 - /llvm/trunk/test/FrontendC++/unnamed-addr.cpp Message-ID: <20110603192105.35DBC2A6C12C@llvm.org> Author: void Date: Fri Jun 3 14:21:05 2011 New Revision: 132575 URL: http://llvm.org/viewvc/llvm-project?rev=132575&view=rev Log: Accomodate front-ends which use private instead of internal here. Modified: llvm/trunk/test/FrontendC++/unnamed-addr.cpp Modified: llvm/trunk/test/FrontendC++/unnamed-addr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/unnamed-addr.cpp?rev=132575&r1=132574&r2=132575&view=diff ============================================================================== --- llvm/trunk/test/FrontendC++/unnamed-addr.cpp (original) +++ llvm/trunk/test/FrontendC++/unnamed-addr.cpp Fri Jun 3 14:21:05 2011 @@ -83,7 +83,7 @@ return self->numberOfFixtuers; } -// CHECK: @_ZZ14TestCaller_runP12__TestCallerP12__TestResultE3C.0 = internal unnamed_addr constant +// CHECK: @_ZZ14TestCaller_runP12__TestCallerP12__TestResultE3C.0 = {{internal|private}} unnamed_addr constant // CHECK-NOT: @TestCaseImplement = external unnamed_addr constant %struct.TestImplement // CHECK: @TestCaseImplement = external constant %struct.TestImplement const TestImplement TestCallerImplement = { From isanbard at gmail.com Fri Jun 3 14:26:47 2011 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 3 Jun 2011 12:26:47 -0700 Subject: [llvm-commits] [llvm] r132504 - in /llvm/trunk/test: FrontendC++/unnamed-addr.cpp FrontendC/unnamed-addr.c In-Reply-To: References: <20110602222615.7723B2A6C12C@llvm.org> Message-ID: <28DED137-87AD-4FB3-8F60-49B9487C0271@gmail.com> Should be fixed by r132575. Sorry for the breakage! -bw On Jun 3, 2011, at 10:00 AM, Eli Friedman wrote: > On Thu, Jun 2, 2011 at 3:26 PM, Bill Wendling wrote: >> Author: void >> Date: Thu Jun 2 17:26:15 2011 >> New Revision: 132504 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=132504&view=rev >> Log: >> This should have been a C++ testcase. >> >> Added: >> llvm/trunk/test/FrontendC++/unnamed-addr.cpp >> - copied, changed from r132495, llvm/trunk/test/FrontendC/unnamed-addr.c >> Removed: >> llvm/trunk/test/FrontendC/unnamed-addr.c >> > > This test is apparently failing on Linux; see, for example, > http://google1.osuosl.org:8011/builders/llvm-gcc-i386-linux-selfhost/builds/2721/steps/test.llvm.stage2/logs/unnamed-addr.cpp > . > > -Eli > >> Copied: llvm/trunk/test/FrontendC++/unnamed-addr.cpp (from r132495, llvm/trunk/test/FrontendC/unnamed-addr.c) >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/unnamed-addr.cpp?p2=llvm/trunk/test/FrontendC%2B%2B/unnamed-addr.cpp&p1=llvm/trunk/test/FrontendC/unnamed-addr.c&r1=132495&r2=132504&rev=132504&view=diff >> ============================================================================== >> --- llvm/trunk/test/FrontendC/unnamed-addr.c (original) >> +++ llvm/trunk/test/FrontendC++/unnamed-addr.cpp Thu Jun 2 17:26:15 2011 >> @@ -1,5 +1,6 @@ >> -// RUN: %llvmgcc -S %s -o - | FileCheck %s >> +// RUN: %llvmgxx -S %s -o - | FileCheck %s >> // >> +extern "C" { >> typedef struct __TestResult TestResult; >> typedef struct __TestResult* TestResultRef; >> >> @@ -57,6 +58,7 @@ >> }; >> >> extern const TestImplement TestCallerImplement; >> +} >> >> void PassToFunction(const TestImplement*); >> >> @@ -81,7 +83,7 @@ >> return self->numberOfFixtuers; >> } >> >> -// CHECK: @C.0.1526 = internal unnamed_addr constant >> +// CHECK: @_ZZ14TestCaller_runP12__TestCallerP12__TestResultE3C.0 = internal unnamed_addr constant >> // CHECK-NOT: @TestCaseImplement = external unnamed_addr constant %struct.TestImplement >> // CHECK: @TestCaseImplement = external constant %struct.TestImplement >> const TestImplement TestCallerImplement = { >> >> Removed: llvm/trunk/test/FrontendC/unnamed-addr.c >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/unnamed-addr.c?rev=132503&view=auto >> ============================================================================== >> --- llvm/trunk/test/FrontendC/unnamed-addr.c (original) >> +++ llvm/trunk/test/FrontendC/unnamed-addr.c (removed) >> @@ -1,91 +0,0 @@ >> -// RUN: %llvmgcc -S %s -o - | FileCheck %s >> -// >> -typedef struct __TestResult TestResult; >> -typedef struct __TestResult* TestResultRef; >> - >> -typedef struct __TestImplement TestImplement; >> -typedef struct __TestImplement* TestImplementRef; >> - >> -typedef char*(*TestNameFunction)(void*); >> -typedef void(*TestRunFunction)(void*,TestResult*); >> -typedef int(*TestCountTestCasesFunction)(void*); >> - >> -struct __TestImplement { >> - TestNameFunction name; >> - TestRunFunction run; >> - TestCountTestCasesFunction countTestCases; >> -}; >> - >> -typedef struct __Test Test; >> -typedef struct __Test* TestRef; >> - >> -struct __Test { >> - TestImplement* isa; >> -}; >> - >> -typedef struct __TestCase TestCase; >> -typedef struct __TestCase* TestCaseRef; >> - >> -struct __TestCase { >> - TestImplement* isa; >> - const char *name; >> - void(*setUp)(void); >> - void(*tearDown)(void); >> - void(*runTest)(void); >> -}; >> - >> -extern const TestImplement TestCaseImplement; >> - >> -typedef struct __TestFixture TestFixture; >> -typedef struct __TestFixture* TestFixtureRef; >> - >> -struct __TestFixture { >> - const char *name; >> - void(*test)(void); >> -}; >> - >> -typedef struct __TestCaller TestCaller; >> -typedef struct __TestCaller* TestCallerRef; >> - >> -struct __TestCaller { >> - TestImplement* isa; >> - const char *name; >> - void(*setUp)(void); >> - void(*tearDown)(void); >> - int numberOfFixtuers; >> - TestFixture *fixtuers; >> -}; >> - >> -extern const TestImplement TestCallerImplement; >> - >> -void PassToFunction(const TestImplement*); >> - >> -const char* TestCaller_name(TestCaller* self) { >> - return self->name; >> -} >> - >> -void TestCaller_run(TestCaller* self,TestResult* result) { >> - TestCase cs = { (TestImplement*)&TestCaseImplement, 0, 0, 0, 0, }; >> - int i; >> - cs.setUp = self->setUp; >> - cs.tearDown = self->tearDown; >> - for (i=0; inumberOfFixtuers; i++) { >> - cs.name = self->fixtuers[i].name; >> - cs.runTest = self->fixtuers[i].test; >> - ((Test*)(void *)&cs)->isa->run((void *)&cs,result); >> - } >> -} >> - >> -int TestCaller_countTestCases(TestCaller* self) { >> - PassToFunction(&TestCallerImplement); >> - return self->numberOfFixtuers; >> -} >> - >> -// CHECK: @C.0.1526 = internal unnamed_addr constant >> -// CHECK-NOT: @TestCaseImplement = external unnamed_addr constant %struct.TestImplement >> -// CHECK: @TestCaseImplement = external constant %struct.TestImplement >> -const TestImplement TestCallerImplement = { >> - (TestNameFunction)TestCaller_name, >> - (TestRunFunction)TestCaller_run, >> - (TestCountTestCasesFunction)TestCaller_countTestCases, >> -}; >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> From dpatel at apple.com Fri Jun 3 14:46:20 2011 From: dpatel at apple.com (Devang Patel) Date: Fri, 03 Jun 2011 19:46:20 -0000 Subject: [llvm-commits] [llvm] r132578 - /llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Message-ID: <20110603194620.18CDE2A6C12C@llvm.org> Author: dpatel Date: Fri Jun 3 14:46:19 2011 New Revision: 132578 URL: http://llvm.org/viewvc/llvm-project?rev=132578&view=rev Log: Use IRBuilder, preserve line numbers. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=132578&r1=132577&r2=132578&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Fri Jun 3 14:46:19 2011 @@ -1840,9 +1840,10 @@ // %insert = insertvalue { i32, i32 } %insert.0, i32 %load.1, 1 // (Also works for arrays instead of structs) Value *Insert = UndefValue::get(LIType); + IRBuilder<> Builder(LI); for (unsigned i = 0, e = NewElts.size(); i != e; ++i) { - Value *Load = new LoadInst(NewElts[i], "load", LI); - Insert = InsertValueInst::Create(Insert, Load, i, "insert", LI); + Value *Load = Builder.CreateLoad(NewElts[i], "load"); + Insert = Builder.CreateInsertValue(Insert, Load, i, "insert"); } LI->replaceAllUsesWith(Insert); DeadInsts.push_back(LI); @@ -1867,9 +1868,10 @@ // %val.1 = extractvalue { i32, i32 } %val, 1 // store i32 %val.1, i32* %alloc.1 // (Also works for arrays instead of structs) + IRBuilder<> Builder(SI); for (unsigned i = 0, e = NewElts.size(); i != e; ++i) { - Value *Extract = ExtractValueInst::Create(Val, i, Val->getName(), SI); - new StoreInst(Extract, NewElts[i], SI); + Value *Extract = Builder.CreateExtractValue(Val, i, Val->getName()); + Builder.CreateStore(Extract, NewElts[i]); } DeadInsts.push_back(SI); } else if (SIType->isIntegerTy() && From gohman at apple.com Fri Jun 3 15:05:52 2011 From: gohman at apple.com (Dan Gohman) Date: Fri, 03 Jun 2011 13:05:52 -0700 Subject: [llvm-commits] [llvm] r132535 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnswitch.cpp test/Transforms/LoopUnswitch/2011-06-02-CritSwitch.ll In-Reply-To: <20110603062715.A48A72A6C12C@llvm.org> References: <20110603062715.A48A72A6C12C@llvm.org> Message-ID: <1A893105-EB3A-45AB-81DD-52D4BE784395@apple.com> On Jun 2, 2011, at 11:27 PM, Nick Lewycky wrote: > Author: nicholas > Date: Fri Jun 3 01:27:15 2011 > New Revision: 132535 > > URL: http://llvm.org/viewvc/llvm-project?rev=132535&view=rev > Log: > Bail on unswitching a switch statement for a case with a critical edge. We name > which edge to split by pred/succ pair, which means that we can end up splitting > the wrong edge (by case value) in the switch statement entirely. Fixes PR10031! Can this come up with branches instead of switches too? Branches where both arms go to the same destination are rare but possible. Dan From nlewycky at google.com Fri Jun 3 15:19:52 2011 From: nlewycky at google.com (Nick Lewycky) Date: Fri, 3 Jun 2011 13:19:52 -0700 Subject: [llvm-commits] [llvm] r132535 - in /llvm/trunk: lib/Transforms/Scalar/LoopUnswitch.cpp test/Transforms/LoopUnswitch/2011-06-02-CritSwitch.ll In-Reply-To: <1A893105-EB3A-45AB-81DD-52D4BE784395@apple.com> References: <20110603062715.A48A72A6C12C@llvm.org> <1A893105-EB3A-45AB-81DD-52D4BE784395@apple.com> Message-ID: On 3 June 2011 13:05, Dan Gohman wrote: > > On Jun 2, 2011, at 11:27 PM, Nick Lewycky wrote: > > > Author: nicholas > > Date: Fri Jun 3 01:27:15 2011 > > New Revision: 132535 > > > > URL: http://llvm.org/viewvc/llvm-project?rev=132535&view=rev > > Log: > > Bail on unswitching a switch statement for a case with a critical edge. > We name > > which edge to split by pred/succ pair, which means that we can end up > splitting > > the wrong edge (by case value) in the switch statement entirely. Fixes > PR10031! > > Can this come up with branches instead of switches too? Branches where both > arms go to the same destination are rare but possible. > No, the affected code in RewriteLoopBodyWithConditionConstant only handles switches. Branches are handled in the code right above it where it does a simple replacement on the condition with either true or false. It never touches the CFG. Nick -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110603/635e6510/attachment.html From gohman at apple.com Fri Jun 3 15:17:36 2011 From: gohman at apple.com (Dan Gohman) Date: Fri, 03 Jun 2011 20:17:36 -0000 Subject: [llvm-commits] [llvm] r132579 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/must-and-partial.ll Message-ID: <20110603201736.73ED32A6C12C@llvm.org> Author: djg Date: Fri Jun 3 15:17:36 2011 New Revision: 132579 URL: http://llvm.org/viewvc/llvm-project?rev=132579&view=rev Log: When merging MustAlias and PartialAlias, chose PartialAlias instead of conservatively choosing MayAlias. Added: llvm/trunk/test/Analysis/BasicAA/must-and-partial.ll Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=132579&r1=132578&r2=132579&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Fri Jun 3 15:17:36 2011 @@ -949,6 +949,19 @@ return MayAlias; } +static AliasAnalysis::AliasResult +MergeAliasResults(AliasAnalysis::AliasResult A, AliasAnalysis::AliasResult B) { + // If the results agree, take it. + if (A == B) + return A; + // A mix of PartialAlias and MustAlias is PartialAlias. + if ((A == AliasAnalysis::PartialAlias && B == AliasAnalysis::MustAlias) || + (B == AliasAnalysis::PartialAlias && A == AliasAnalysis::MustAlias)) + return AliasAnalysis::PartialAlias; + // Otherwise, we don't know anything. + return AliasAnalysis::MayAlias; +} + /// aliasSelect - Provide a bunch of ad-hoc rules to disambiguate a Select /// instruction against another. AliasAnalysis::AliasResult @@ -975,9 +988,7 @@ AliasResult ThisAlias = aliasCheck(SI->getFalseValue(), SISize, SITBAAInfo, SI2->getFalseValue(), V2Size, V2TBAAInfo); - if (ThisAlias != Alias) - return MayAlias; - return Alias; + return MergeAliasResults(ThisAlias, Alias); } // If both arms of the Select node NoAlias or MustAlias V2, then returns @@ -994,9 +1005,7 @@ AliasResult ThisAlias = aliasCheck(V2, V2Size, V2TBAAInfo, SI->getFalseValue(), SISize, SITBAAInfo); - if (ThisAlias != Alias) - return MayAlias; - return Alias; + return MergeAliasResults(ThisAlias, Alias); } // aliasPHI - Provide a bunch of ad-hoc rules to disambiguate a PHI instruction @@ -1026,8 +1035,9 @@ aliasCheck(PN->getIncomingValue(i), PNSize, PNTBAAInfo, PN2->getIncomingValueForBlock(PN->getIncomingBlock(i)), V2Size, V2TBAAInfo); - if (ThisAlias != Alias) - return MayAlias; + Alias = MergeAliasResults(ThisAlias, Alias); + if (Alias == MayAlias) + break; } return Alias; } @@ -1065,8 +1075,9 @@ AliasResult ThisAlias = aliasCheck(V2, V2Size, V2TBAAInfo, V, PNSize, PNTBAAInfo); - if (ThisAlias != Alias || ThisAlias == MayAlias) - return MayAlias; + Alias = MergeAliasResults(ThisAlias, Alias); + if (Alias == MayAlias) + break; } return Alias; Added: llvm/trunk/test/Analysis/BasicAA/must-and-partial.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/must-and-partial.ll?rev=132579&view=auto ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/must-and-partial.ll (added) +++ llvm/trunk/test/Analysis/BasicAA/must-and-partial.ll Fri Jun 3 15:17:36 2011 @@ -0,0 +1,39 @@ +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info |& FileCheck %s + +; When merging MustAlias and PartialAlias, merge to PartialAlias +; instead of MayAlias. + + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +; CHECK: PartialAlias: i16* %bigbase0, i8* %phi +define i8 @test0(i8* %base, i1 %x) { +entry: + %baseplusone = getelementptr i8* %base, i64 1 + br i1 %x, label %red, label %green +red: + br label %green +green: + %phi = phi i8* [ %baseplusone, %red ], [ %base, %entry ] + store i8 0, i8* %phi + + %bigbase0 = bitcast i8* %base to i16* + store i16 -1, i16* %bigbase0 + + %loaded = load i8* %phi + ret i8 %loaded +} + +; CHECK: PartialAlias: i16* %bigbase1, i8* %sel +define i8 @test1(i8* %base, i1 %x) { +entry: + %baseplusone = getelementptr i8* %base, i64 1 + %sel = select i1 %x, i8* %baseplusone, i8* %base + store i8 0, i8* %sel + + %bigbase1 = bitcast i8* %base to i16* + store i16 -1, i16* %bigbase1 + + %loaded = load i8* %sel + ret i8 %loaded +} From stoklund at 2pi.dk Fri Jun 3 15:34:50 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 03 Jun 2011 20:34:50 -0000 Subject: [llvm-commits] [llvm] r132580 - /llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Message-ID: <20110603203450.68A5B2A6C12C@llvm.org> Author: stoklund Date: Fri Jun 3 15:34:50 2011 New Revision: 132580 URL: http://llvm.org/viewvc/llvm-project?rev=132580&view=rev Log: Preserve the original ordering when a CSR has multiple aliases. Previously, these aliases would be ordered alphabetically. (BH, BL) Print out the computed allocation orders. Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp?rev=132580&r1=132579&r2=132580&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterClassInfo.cpp Fri Jun 3 15:34:50 2011 @@ -14,10 +14,14 @@ // //===----------------------------------------------------------------------===// +#define DEBUG_TYPE "regalloc" #include "RegisterClassInfo.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + using namespace llvm; RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0) @@ -86,8 +90,9 @@ if (Reserved.test(PhysReg)) continue; if (unsigned CSR = CSRNum[PhysReg]) - // PhysReg aliases a CSR, save it for later. - CSRAlias.push_back(std::make_pair(CSR, PhysReg)); + // PhysReg aliases a CSR, save it for later. Provide a (CSR, N) sort key + // to preserve the original ordering of multiple aliases of the same CSR. + CSRAlias.push_back(std::make_pair((CSR << 16) + (I - AOB), PhysReg)); else RCI.Order[N++] = PhysReg; } @@ -101,6 +106,13 @@ for (unsigned i = 0, e = CSRAlias.size(); i != e; ++i) RCI.Order[N++] = CSRAlias[i].second; + DEBUG({ + dbgs() << "AllocationOrder(" << RC->getName() << ") = ["; + for (unsigned I = 0; I != N; ++I) + dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); + dbgs() << " ]\n"; + }); + // RCI is now up-to-date. RCI.Tag = Tag; } From stoklund at 2pi.dk Fri Jun 3 15:34:54 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 03 Jun 2011 20:34:54 -0000 Subject: [llvm-commits] [llvm] r132581 - in /llvm/trunk: lib/CodeGen/AllocationOrder.cpp lib/CodeGen/AllocationOrder.h lib/CodeGen/RegAllocBase.h lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/RegAllocGreedy.cpp test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll Message-ID: <20110603203454.2E8092A6C12D@llvm.org> Author: stoklund Date: Fri Jun 3 15:34:53 2011 New Revision: 132581 URL: http://llvm.org/viewvc/llvm-project?rev=132581&view=rev Log: Switch AllocationOrder to using RegisterClassInfo instead of a BitVector of reserved registers. Use RegisterClassInfo in RABasic as well. This slightly changes som allocation orders because RegisterClassInfo puts CSR aliases last. Modified: llvm/trunk/lib/CodeGen/AllocationOrder.cpp llvm/trunk/lib/CodeGen/AllocationOrder.h llvm/trunk/lib/CodeGen/RegAllocBase.h llvm/trunk/lib/CodeGen/RegAllocBasic.cpp llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll Modified: llvm/trunk/lib/CodeGen/AllocationOrder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AllocationOrder.cpp?rev=132581&r1=132580&r2=132581&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AllocationOrder.cpp (original) +++ llvm/trunk/lib/CodeGen/AllocationOrder.cpp Fri Jun 3 15:34:53 2011 @@ -15,6 +15,7 @@ //===----------------------------------------------------------------------===// #include "AllocationOrder.h" +#include "RegisterClassInfo.h" #include "VirtRegMap.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -23,8 +24,8 @@ // Compare VirtRegMap::getRegAllocPref(). AllocationOrder::AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, - const BitVector &ReservedRegs) - : Pos(0), Reserved(ReservedRegs) { + const RegisterClassInfo &RegClassInfo) + : Pos(0), RCI(RegClassInfo) { const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); std::pair HintPair = VRM.getRegInfo().getRegAllocationHint(VirtReg); @@ -47,7 +48,7 @@ // The hint must be a valid physreg for allocation. if (Hint && (!TargetRegisterInfo::isPhysicalRegister(Hint) || - !RC->contains(Hint) || ReservedRegs.test(Hint))) + !RC->contains(Hint) || RCI.isReserved(Hint))) Hint = 0; } @@ -61,7 +62,7 @@ // Then look at the order from TRI. while(Pos != End) { unsigned Reg = *Pos++; - if (Reg != Hint && !Reserved.test(Reg)) + if (Reg != Hint && !RCI.isReserved(Reg)) return Reg; } return 0; Modified: llvm/trunk/lib/CodeGen/AllocationOrder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AllocationOrder.h?rev=132581&r1=132580&r2=132581&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AllocationOrder.h (original) +++ llvm/trunk/lib/CodeGen/AllocationOrder.h Fri Jun 3 15:34:53 2011 @@ -19,14 +19,14 @@ namespace llvm { -class BitVector; +class RegisterClassInfo; class VirtRegMap; class AllocationOrder { const unsigned *Begin; const unsigned *End; const unsigned *Pos; - const BitVector &Reserved; + const RegisterClassInfo &RCI; unsigned Hint; public: @@ -37,7 +37,7 @@ /// TargetRegisterInfo::getReservedRegs(). AllocationOrder(unsigned VirtReg, const VirtRegMap &VRM, - const BitVector &ReservedRegs); + const RegisterClassInfo &RegClassInfo); /// next - Return the next physical register in the allocation order, or 0. /// It is safe to call next again after it returned 0. Modified: llvm/trunk/lib/CodeGen/RegAllocBase.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBase.h?rev=132581&r1=132580&r2=132581&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBase.h (original) +++ llvm/trunk/lib/CodeGen/RegAllocBase.h Fri Jun 3 15:34:53 2011 @@ -39,6 +39,7 @@ #include "llvm/ADT/OwningPtr.h" #include "LiveIntervalUnion.h" +#include "RegisterClassInfo.h" namespace llvm { @@ -91,6 +92,7 @@ MachineRegisterInfo *MRI; VirtRegMap *VRM; LiveIntervals *LIS; + RegisterClassInfo RegClassInfo; LiveUnionArray PhysReg2LiveUnion; // Current queries, one per physreg. They must be reinitialized each time we Modified: llvm/trunk/lib/CodeGen/RegAllocBasic.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocBasic.cpp?rev=132581&r1=132580&r2=132581&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocBasic.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocBasic.cpp Fri Jun 3 15:34:53 2011 @@ -13,10 +13,10 @@ //===----------------------------------------------------------------------===// #define DEBUG_TYPE "regalloc" +#include "RegAllocBase.h" #include "LiveDebugVariables.h" #include "LiveIntervalUnion.h" #include "LiveRangeEdit.h" -#include "RegAllocBase.h" #include "RenderMachineFunction.h" #include "Spiller.h" #include "VirtRegMap.h" @@ -85,7 +85,6 @@ { // context MachineFunction *MF; - BitVector ReservedRegs; // analyses LiveStacks *LS; @@ -235,6 +234,8 @@ MRI = &vrm.getRegInfo(); VRM = &vrm; LIS = &lis; + RegClassInfo.runOnMachineFunction(vrm.getMachineFunction()); + const unsigned NumRegs = TRI->getNumRegs(); if (NumRegs != PhysReg2LiveUnion.numRegs()) { PhysReg2LiveUnion.init(UnionAllocator, NumRegs); @@ -479,14 +480,11 @@ SmallVector PhysRegSpillCands; // Check for an available register in this class. - const TargetRegisterClass *TRC = MRI->getRegClass(VirtReg.reg); - - for (TargetRegisterClass::iterator I = TRC->allocation_order_begin(*MF), - E = TRC->allocation_order_end(*MF); - I != E; ++I) { - + ArrayRef Order = + RegClassInfo.getOrder(MRI->getRegClass(VirtReg.reg)); + for (ArrayRef::iterator I = Order.begin(), E = Order.end(); I != E; + ++I) { unsigned PhysReg = *I; - if (ReservedRegs.test(PhysReg)) continue; // Check interference and as a side effect, intialize queries for this // VirtReg and its aliases. @@ -537,9 +535,6 @@ DEBUG(RMF = &getAnalysis()); RegAllocBase::init(getAnalysis(), getAnalysis()); - - ReservedRegs = TRI->getReservedRegs(*MF); - SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM)); allocatePhysRegs(); Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=132581&r1=132580&r2=132581&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Fri Jun 3 15:34:53 2011 @@ -62,7 +62,6 @@ // context MachineFunction *MF; - BitVector ReservedRegs; // analyses SlotIndexes *Indexes; @@ -1410,7 +1409,7 @@ unsigned RAGreedy::selectOrSplit(LiveInterval &VirtReg, SmallVectorImpl &NewVRegs) { // First try assigning a free register. - AllocationOrder Order(VirtReg.reg, *VRM, ReservedRegs); + AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); if (unsigned PhysReg = tryAssign(VirtReg, Order, NewVRegs)) return PhysReg; @@ -1472,7 +1471,6 @@ RegAllocBase::init(getAnalysis(), getAnalysis()); Indexes = &getAnalysis(); DomTree = &getAnalysis(); - ReservedRegs = TRI->getReservedRegs(*MF); SpillerInstance.reset(createInlineSpiller(*this, *MF, *VRM)); Loops = &getAnalysis(); LoopRanges = &getAnalysis(); Modified: llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll?rev=132581&r1=132580&r2=132581&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll Fri Jun 3 15:34:53 2011 @@ -12,7 +12,7 @@ define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string,std::allocator >"* %this, %"struct.std::basic_string,std::allocator >"* %__str) { ; CHECK: _ZNKSs7compareERKSs: ; CHECK: it eq -; CHECK-NEXT: subeq r0, r{{[0-9]+}}, r{{[0-9]+}} +; CHECK-NEXT: subeq{{(.w)?}} r0, r{{[0-9]+}}, r{{[0-9]+}} ; CHECK-NEXT: ldmia.w sp!, entry: %0 = tail call arm_aapcs_vfpcc i32 @_ZNKSs4sizeEv(%"struct.std::basic_string,std::allocator >"* %this) ; [#uses=3] From isanbard at gmail.com Fri Jun 3 15:43:58 2011 From: isanbard at gmail.com (Bill Wendling) Date: Fri, 03 Jun 2011 20:43:58 -0000 Subject: [llvm-commits] [llvm] r132589 - /llvm/trunk/test/FrontendC++/unnamed-addr.cpp Message-ID: <20110603204358.490892A6C12C@llvm.org> Author: void Date: Fri Jun 3 15:43:58 2011 New Revision: 132589 URL: http://llvm.org/viewvc/llvm-project?rev=132589&view=rev Log: Remove testcase. It's problematic for the buildbots. Removed: llvm/trunk/test/FrontendC++/unnamed-addr.cpp Removed: llvm/trunk/test/FrontendC++/unnamed-addr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC%2B%2B/unnamed-addr.cpp?rev=132588&view=auto ============================================================================== --- llvm/trunk/test/FrontendC++/unnamed-addr.cpp (original) +++ llvm/trunk/test/FrontendC++/unnamed-addr.cpp (removed) @@ -1,93 +0,0 @@ -// RUN: %llvmgxx -S %s -o - | FileCheck %s -// -extern "C" { -typedef struct __TestResult TestResult; -typedef struct __TestResult* TestResultRef; - -typedef struct __TestImplement TestImplement; -typedef struct __TestImplement* TestImplementRef; - -typedef char*(*TestNameFunction)(void*); -typedef void(*TestRunFunction)(void*,TestResult*); -typedef int(*TestCountTestCasesFunction)(void*); - -struct __TestImplement { - TestNameFunction name; - TestRunFunction run; - TestCountTestCasesFunction countTestCases; -}; - -typedef struct __Test Test; -typedef struct __Test* TestRef; - -struct __Test { - TestImplement* isa; -}; - -typedef struct __TestCase TestCase; -typedef struct __TestCase* TestCaseRef; - -struct __TestCase { - TestImplement* isa; - const char *name; - void(*setUp)(void); - void(*tearDown)(void); - void(*runTest)(void); -}; - -extern const TestImplement TestCaseImplement; - -typedef struct __TestFixture TestFixture; -typedef struct __TestFixture* TestFixtureRef; - -struct __TestFixture { - const char *name; - void(*test)(void); -}; - -typedef struct __TestCaller TestCaller; -typedef struct __TestCaller* TestCallerRef; - -struct __TestCaller { - TestImplement* isa; - const char *name; - void(*setUp)(void); - void(*tearDown)(void); - int numberOfFixtuers; - TestFixture *fixtuers; -}; - -extern const TestImplement TestCallerImplement; -} - -void PassToFunction(const TestImplement*); - -const char* TestCaller_name(TestCaller* self) { - return self->name; -} - -void TestCaller_run(TestCaller* self,TestResult* result) { - TestCase cs = { (TestImplement*)&TestCaseImplement, 0, 0, 0, 0, }; - int i; - cs.setUp = self->setUp; - cs.tearDown = self->tearDown; - for (i=0; inumberOfFixtuers; i++) { - cs.name = self->fixtuers[i].name; - cs.runTest = self->fixtuers[i].test; - ((Test*)(void *)&cs)->isa->run((void *)&cs,result); - } -} - -int TestCaller_countTestCases(TestCaller* self) { - PassToFunction(&TestCallerImplement); - return self->numberOfFixtuers; -} - -// CHECK: @_ZZ14TestCaller_runP12__TestCallerP12__TestResultE3C.0 = {{internal|private}} unnamed_addr constant -// CHECK-NOT: @TestCaseImplement = external unnamed_addr constant %struct.TestImplement -// CHECK: @TestCaseImplement = external constant %struct.TestImplement -const TestImplement TestCallerImplement = { - (TestNameFunction)TestCaller_name, - (TestRunFunction)TestCaller_run, - (TestCountTestCasesFunction)TestCaller_countTestCases, -}; From echristo at apple.com Fri Jun 3 15:44:53 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 03 Jun 2011 20:44:53 -0000 Subject: [llvm-commits] [llvm] r132590 - in /llvm/trunk: lib/VMCore/InlineAsm.cpp test/CodeGen/ARM/inlineasm3.ll Message-ID: <20110603204453.2BBDA2A6C12C@llvm.org> Author: echristo Date: Fri Jun 3 15:44:52 2011 New Revision: 132590 URL: http://llvm.org/viewvc/llvm-project?rev=132590&view=rev Log: Fix an off by one error. Part of rdar://9037836 and rdar://9119939 Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/InlineAsm.cpp?rev=132590&r1=132589&r2=132590&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/InlineAsm.cpp (original) +++ llvm/trunk/lib/VMCore/InlineAsm.cpp Fri Jun 3 15:44:52 2011 @@ -185,11 +185,10 @@ // Multi-letter constraint // These will only occur with the existing multiple alternative // constraints and so we can use the isalpha loop below. - StringRef::iterator ConStart = I; + StringRef::iterator ConStart = ++I; while (I != E && isalpha(*I)) ++I; pCodes->push_back(std::string(ConStart, I)); - ++I; } else { // Single letter constraint. pCodes->push_back(std::string(I, I+1)); Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=132590&r1=132589&r2=132590&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original) +++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Fri Jun 3 15:44:52 2011 @@ -41,3 +41,12 @@ tail call void asm sideeffect "flds s15, $0 \0A", "^Uv|m,~{s15}"(float 1.000000e+00) nounwind ret i32 0 } + +; Radar 9037836 & 9119939 + + at k.2126 = internal unnamed_addr global float 1.000000e+00 +define i32 @t4() nounwind { +entry: +call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(float* @k.2126) nounwind +ret i32 0 +} From echristo at apple.com Fri Jun 3 15:54:06 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 03 Jun 2011 20:54:06 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r132591 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20110603205407.0CED02A6C12C@llvm.org> Author: echristo Date: Fri Jun 3 15:54:06 2011 New Revision: 132591 URL: http://llvm.org/viewvc/llvm-project?rev=132591&view=rev Log: Prepend a parser helping character on multichar constraints. Part of rdar://9037836 and rdar://9119939 Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=132591&r1=132590&r2=132591&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Fri Jun 3 15:54:06 2011 @@ -4550,6 +4550,9 @@ } } + // If this constraint is multiple letters add a parsing helper prefix. + if (strlen(Constraint) > 1) Result += "^"; + while (*Constraint) { char ConstraintChar = *Constraint++; From echristo at apple.com Fri Jun 3 15:56:31 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 03 Jun 2011 20:56:31 -0000 Subject: [llvm-commits] [llvm] r132592 - /llvm/trunk/test/FrontendC/inline-asm-multichar.c Message-ID: <20110603205631.ECC442A6C12C@llvm.org> Author: echristo Date: Fri Jun 3 15:56:31 2011 New Revision: 132592 URL: http://llvm.org/viewvc/llvm-project?rev=132592&view=rev Log: Testcase for llvm-gcc commit r132591. Part of rdar://9037836 and rdar://9119939 Added: llvm/trunk/test/FrontendC/inline-asm-multichar.c Added: llvm/trunk/test/FrontendC/inline-asm-multichar.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/inline-asm-multichar.c?rev=132592&view=auto ============================================================================== --- llvm/trunk/test/FrontendC/inline-asm-multichar.c (added) +++ llvm/trunk/test/FrontendC/inline-asm-multichar.c Fri Jun 3 15:56:31 2011 @@ -0,0 +1,11 @@ +// RUN: %llvmgcc -S -march=armv7a %s + +// XFAIL: * +// XTARGET: arm + +int t1() { + static float k = 1.0f; +CHECK: call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}" + __asm__ volatile ("flds s15, %[k] \n" :: [k] "Uv,m" (k) : "s15"); + return 0; +} From echristo at apple.com Fri Jun 3 16:41:00 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 03 Jun 2011 21:41:00 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r132595 - /llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Message-ID: <20110603214100.719652A6C12C@llvm.org> Author: echristo Date: Fri Jun 3 16:41:00 2011 New Revision: 132595 URL: http://llvm.org/viewvc/llvm-project?rev=132595&view=rev Log: "mr" is a valid constraint for our purposes here, not one constraint. Use CONSTRAINT_LEN to get the real length of the constraint. Part of rdar://9037836 and rdar://9119939 Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=132595&r1=132594&r2=132595&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Fri Jun 3 16:41:00 2011 @@ -4551,7 +4551,7 @@ } // If this constraint is multiple letters add a parsing helper prefix. - if (strlen(Constraint) > 1) Result += "^"; + if (CONSTRAINT_LEN(*Constraint, Constraint) > 1) Result += "^"; while (*Constraint) { char ConstraintChar = *Constraint++; From echristo at apple.com Fri Jun 3 17:09:12 2011 From: echristo at apple.com (Eric Christopher) Date: Fri, 03 Jun 2011 22:09:12 -0000 Subject: [llvm-commits] [llvm] r132598 - in /llvm/trunk: lib/VMCore/InlineAsm.cpp test/CodeGen/ARM/inlineasm3.ll Message-ID: <20110603220912.8DD702A6C12C@llvm.org> Author: echristo Date: Fri Jun 3 17:09:12 2011 New Revision: 132598 URL: http://llvm.org/viewvc/llvm-project?rev=132598&view=rev Log: Another possible bug. Stopgap until we can autogenerate tables and constraint lengths. Part of rdar://9037836 and rdar://9119939 Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Modified: llvm/trunk/lib/VMCore/InlineAsm.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/InlineAsm.cpp?rev=132598&r1=132597&r2=132598&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/InlineAsm.cpp (original) +++ llvm/trunk/lib/VMCore/InlineAsm.cpp Fri Jun 3 17:09:12 2011 @@ -183,12 +183,9 @@ ++I; } else if (*I == '^') { // Multi-letter constraint - // These will only occur with the existing multiple alternative - // constraints and so we can use the isalpha loop below. - StringRef::iterator ConStart = ++I; - while (I != E && isalpha(*I)) - ++I; - pCodes->push_back(std::string(ConStart, I)); + // FIXME: For now assuming these are 2-character constraints. + pCodes->push_back(std::string(I+1, I+3)); + I += 3; } else { // Single letter constraint. pCodes->push_back(std::string(I, I+1)); Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=132598&r1=132597&r2=132598&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original) +++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Fri Jun 3 17:09:12 2011 @@ -50,3 +50,11 @@ call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}"(float* @k.2126) nounwind ret i32 0 } + +; Radar 9037836 & 9119939 + +define i32 @t5() nounwind { +entry: +call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind +ret i32 0 +} From stoklund at 2pi.dk Fri Jun 3 17:45:18 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 03 Jun 2011 22:45:18 -0000 Subject: [llvm-commits] [llvm] r132601 - in /llvm/trunk/lib/Target/Blackfin: BlackfinFrameLowering.cpp BlackfinFrameLowering.h BlackfinRegisterInfo.h Message-ID: <20110603224518.6F0642A6C12C@llvm.org> Author: stoklund Date: Fri Jun 3 17:45:18 2011 New Revision: 132601 URL: http://llvm.org/viewvc/llvm-project?rev=132601&view=rev Log: Blackfin always uses a reserved call frame. Materializing the stack pointer update before a call requires a scratch register that may not be available. Modified: llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h Modified: llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp?rev=132601&r1=132600&r2=132601&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.cpp Fri Jun 3 17:45:18 2011 @@ -31,6 +31,12 @@ MFI->adjustsStack() || MFI->hasVarSizedObjects(); } +// Always reserve a call frame. We dont have enough registers to adjust SP. +bool BlackfinFrameLowering:: +hasReservedCallFrame(const MachineFunction &MF) const { + return true; +} + // Emit a prologue that sets up a stack frame. // On function entry, R0-R2 and P0 may hold arguments. // R3, P1, and P2 may be used as scratch registers Modified: llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h?rev=132601&r1=132600&r2=132601&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinFrameLowering.h Fri Jun 3 17:45:18 2011 @@ -36,6 +36,7 @@ void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; bool hasFP(const MachineFunction &MF) const; + bool hasReservedCallFrame(const MachineFunction &MF) const; void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, RegScavenger *RS) const; Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h?rev=132601&r1=132600&r2=132601&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h Fri Jun 3 17:45:18 2011 @@ -41,8 +41,6 @@ return &BF::PRegClass; } - // bool hasReservedCallFrame(MachineFunction &MF) const; - bool requiresRegisterScavenging(const MachineFunction &MF) const; void eliminateCallFramePseudoInstr(MachineFunction &MF, From stoklund at 2pi.dk Fri Jun 3 17:45:21 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 03 Jun 2011 22:45:21 -0000 Subject: [llvm-commits] [llvm] r132602 - in /llvm/trunk/test/CodeGen/X86: dbg-value-isel.ll tailcallstack64.ll widen_load-0.ll win64_alloca_dynalloca.ll Message-ID: <20110603224521.644BB2A6C12D@llvm.org> Author: stoklund Date: Fri Jun 3 17:45:21 2011 New Revision: 132602 URL: http://llvm.org/viewvc/llvm-project?rev=132602&view=rev Log: Fix some tests that depend on register allocation. Modified: llvm/trunk/test/CodeGen/X86/dbg-value-isel.ll llvm/trunk/test/CodeGen/X86/tailcallstack64.ll llvm/trunk/test/CodeGen/X86/widen_load-0.ll llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll Modified: llvm/trunk/test/CodeGen/X86/dbg-value-isel.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-value-isel.ll?rev=132602&r1=132601&r2=132602&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-value-isel.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-value-isel.ll Fri Jun 3 17:45:21 2011 @@ -3,7 +3,7 @@ target triple = "x86_64-apple-darwin10.0.0" ; PR 9879 -; CHECK: ##DEBUG_VALUE: tid <- R14D+0 +; CHECK: ##DEBUG_VALUE: tid <- %0 = type { i8*, i8*, i8*, i8*, i32 } @sgv = internal addrspace(2) constant [1 x i8] zeroinitializer Modified: llvm/trunk/test/CodeGen/X86/tailcallstack64.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tailcallstack64.ll?rev=132602&r1=132601&r2=132602&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/tailcallstack64.ll (original) +++ llvm/trunk/test/CodeGen/X86/tailcallstack64.ll Fri Jun 3 17:45:21 2011 @@ -2,7 +2,7 @@ ; RUN: llc < %s -tailcallopt -mtriple=x86_64-win32 -post-RA-scheduler=true | FileCheck %s ; FIXME: Redundant unused stack allocation could be eliminated. -; CHECK: subq ${{24|72}}, %rsp +; CHECK: subq ${{24|72|80}}, %rsp ; Check that lowered arguments on the stack do not overwrite each other. ; Add %in1 %p1 to a different temporary register (%eax). Modified: llvm/trunk/test/CodeGen/X86/widen_load-0.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/widen_load-0.ll?rev=132602&r1=132601&r2=132602&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/widen_load-0.ll (original) +++ llvm/trunk/test/CodeGen/X86/widen_load-0.ll Fri Jun 3 17:45:21 2011 @@ -4,15 +4,15 @@ ; Both loads should happen before either store. -; CHECK: movl (%rdi), %eax -; CHECK: movl (%rsi), %ecx -; CHECK: movl %ecx, (%rdi) -; CHECK: movl %eax, (%rsi) +; CHECK: movl (%rdi), %[[R1:...]] +; CHECK: movl (%rsi), %[[R2:...]] +; CHECK: movl %[[R2]], (%rdi) +; CHECK: movl %[[R1]], (%rsi) -; WIN64: movl (%rcx), %eax -; WIN64: movl (%rdx), %esi -; WIN64: movl %esi, (%rcx) -; WIN64: movl %eax, (%rdx) +; WIN64: movl (%rcx), %[[R1:...]] +; WIN64: movl (%rdx), %[[R2:...]] +; WIN64: movl %[[R2]], (%rcx) +; WIN64: movl %[[R1]], (%rdx) define void @short2_int_swap(<2 x i16>* nocapture %b, i32* nocapture %c) nounwind { entry: Modified: llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll?rev=132602&r1=132601&r2=132602&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll (original) +++ llvm/trunk/test/CodeGen/X86/win64_alloca_dynalloca.ll Fri Jun 3 17:45:21 2011 @@ -43,9 +43,9 @@ ; W64: subq %rax, %rsp ; W64: movq %rsp, %rax -; EFI: leaq 15(%rcx), [[R1:%r..]] +; EFI: leaq 15(%rcx), [[R1:%r.*]] ; EFI: andq $-16, [[R1]] -; EFI: movq %rsp, [[R64:%r..]] +; EFI: movq %rsp, [[R64:%r.*]] ; EFI: subq [[R1]], [[R64]] ; EFI: movq [[R64]], %rsp From stuart at apple.com Fri Jun 3 18:53:54 2011 From: stuart at apple.com (Stuart Hastings) Date: Fri, 03 Jun 2011 23:53:54 -0000 Subject: [llvm-commits] [llvm] r132606 - in /llvm/trunk: lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86ISelLowering.h lib/Target/X86/X86InstrFragmentsSIMD.td lib/Target/X86/X86InstrInfo.td lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/isint.ll test/CodeGen/X86/pr9127.ll test/CodeGen/X86/setoeq.ll Message-ID: <20110603235355.28AE62A6C12C@llvm.org> Author: stuart Date: Fri Jun 3 18:53:54 2011 New Revision: 132606 URL: http://llvm.org/viewvc/llvm-project?rev=132606&view=rev Log: Reapply 132424 with fixes. This fixes PR10068. rdar://problem/5993888 Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td llvm/trunk/lib/Target/X86/X86InstrInfo.td llvm/trunk/lib/Target/X86/X86InstrSSE.td llvm/trunk/test/CodeGen/X86/isint.ll llvm/trunk/test/CodeGen/X86/pr9127.ll llvm/trunk/test/CodeGen/X86/setoeq.ll Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=132606&r1=132605&r2=132606&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 3 18:53:54 2011 @@ -9402,6 +9402,8 @@ case X86ISD::UCOMI: return "X86ISD::UCOMI"; case X86ISD::SETCC: return "X86ISD::SETCC"; case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; + case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; + case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; case X86ISD::CMOV: return "X86ISD::CMOV"; case X86ISD::BRCOND: return "X86ISD::BRCOND"; case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; @@ -11679,12 +11681,94 @@ } +// CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) +// where both setccs reference the same FP CMP, and rewrite for CMPEQSS +// and friends. Likewise for OR -> CMPNEQSS. +static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, + TargetLowering::DAGCombinerInfo &DCI, + const X86Subtarget *Subtarget) { + unsigned opcode; + + // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but + // we're requiring SSE2 for both. + if (Subtarget->hasSSE2() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { + SDValue N0 = N->getOperand(0); + SDValue N1 = N->getOperand(1); + SDValue CMP0 = N0->getOperand(1); + SDValue CMP1 = N1->getOperand(1); + DebugLoc DL = N->getDebugLoc(); + + // The SETCCs should both refer to the same CMP. + if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) + return SDValue(); + + SDValue CMP00 = CMP0->getOperand(0); + SDValue CMP01 = CMP0->getOperand(1); + EVT VT = CMP00.getValueType(); + + if (VT == MVT::f32 || VT == MVT::f64) { + bool ExpectingFlags = false; + // Check for any users that want flags: + for (SDNode::use_iterator UI = N->use_begin(), + UE = N->use_end(); + !ExpectingFlags && UI != UE; ++UI) + switch (UI->getOpcode()) { + default: + case ISD::BR_CC: + case ISD::BRCOND: + case ISD::SELECT: + ExpectingFlags = true; + break; + case ISD::CopyToReg: + case ISD::SIGN_EXTEND: + case ISD::ZERO_EXTEND: + case ISD::ANY_EXTEND: + break; + } + + if (!ExpectingFlags) { + enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); + enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); + + if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { + X86::CondCode tmp = cc0; + cc0 = cc1; + cc1 = tmp; + } + + if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || + (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { + bool is64BitFP = (CMP00.getValueType() == MVT::f64); + X86ISD::NodeType NTOperator = is64BitFP ? + X86ISD::FSETCCsd : X86ISD::FSETCCss; + // FIXME: need symbolic constants for these magic numbers. + // See X86ATTInstPrinter.cpp:printSSECC(). + unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; + SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, + DAG.getConstant(x86cc, MVT::i8)); + SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, + OnesOrZeroesF); + SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, + DAG.getConstant(1, MVT::i32)); + SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); + return OneBitOfTruth; + } + } + } + } + return SDValue(); +} + static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const X86Subtarget *Subtarget) { if (DCI.isBeforeLegalizeOps()) return SDValue(); + SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); + if (R.getNode()) + return R; + // Want to form PANDN nodes, in the hopes of then easily combining them with // OR and AND nodes to form PBLEND/PSIGN. EVT VT = N->getValueType(0); @@ -11714,6 +11798,10 @@ if (DCI.isBeforeLegalizeOps()) return SDValue(); + SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); + if (R.getNode()) + return R; + EVT VT = N->getValueType(0); if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) return SDValue(); Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=132606&r1=132605&r2=132606&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Fri Jun 3 18:53:54 2011 @@ -94,6 +94,11 @@ // one's or all zero's. SETCC_CARRY, // R = carry_bit ? ~0 : 0 + /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD. + /// Operands are two FP values to compare; result is a mask of + /// 0s or 1s. Generally DTRT for C/C++ with NaNs. + FSETCCss, FSETCCsd, + /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values, /// result in an integer GPR. Needs masking for scalar result. FGETSIGNx86, Modified: llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td?rev=132606&r1=132605&r2=132606&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFragmentsSIMD.td Fri Jun 3 18:53:54 2011 @@ -41,6 +41,8 @@ def X86fgetsign: SDNode<"X86ISD::FGETSIGNx86",SDTFPToIntOp>; def X86comi : SDNode<"X86ISD::COMI", SDTX86CmpTest>; def X86ucomi : SDNode<"X86ISD::UCOMI", SDTX86CmpTest>; +def X86cmpss : SDNode<"X86ISD::FSETCCss", SDTX86Cmpss>; +def X86cmpsd : SDNode<"X86ISD::FSETCCsd", SDTX86Cmpsd>; def X86pshufb : SDNode<"X86ISD::PSHUFB", SDTypeProfile<1, 2, [SDTCisVT<0, v16i8>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>>; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=132606&r1=132605&r2=132606&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri Jun 3 18:53:54 2011 @@ -23,6 +23,9 @@ def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisSameAs<1, 2>]>; +def SDTX86Cmpsd : SDTypeProfile<1, 3, [SDTCisVT<0, f64>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; +def SDTX86Cmpss : SDTypeProfile<1, 3, [SDTCisVT<0, f32>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>]>; + def SDTX86Cmov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=132606&r1=132605&r2=132606&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Fri Jun 3 18:53:54 2011 @@ -1056,13 +1056,37 @@ XD, VEX_4V; } +let Constraints = "$src1 = $dst" in { +def CMPSSrr : SIi8<0xC2, MRMSrcReg, + (outs FR32:$dst), (ins FR32:$src1, FR32:$src2, SSECC:$cc), + "cmp${cc}ss\t{$src2, $dst|$dst, $src2}", + [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), FR32:$src2, imm:$cc))]>, XS; +def CMPSSrm : SIi8<0xC2, MRMSrcMem, + (outs FR32:$dst), (ins FR32:$src1, f32mem:$src2, SSECC:$cc), + "cmp${cc}ss\t{$src2, $dst|$dst, $src2}", + [(set FR32:$dst, (X86cmpss (f32 FR32:$src1), (loadf32 addr:$src2), imm:$cc))]>, XS; +def CMPSDrr : SIi8<0xC2, MRMSrcReg, + (outs FR64:$dst), (ins FR64:$src1, FR64:$src2, SSECC:$cc), + "cmp${cc}sd\t{$src2, $dst|$dst, $src2}", + [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), FR64:$src2, imm:$cc))]>, XD; +def CMPSDrm : SIi8<0xC2, MRMSrcMem, + (outs FR64:$dst), (ins FR64:$src1, f64mem:$src2, SSECC:$cc), + "cmp${cc}sd\t{$src2, $dst|$dst, $src2}", + [(set FR64:$dst, (X86cmpsd (f64 FR64:$src1), (loadf64 addr:$src2), imm:$cc))]>, XD; +} let Constraints = "$src1 = $dst", neverHasSideEffects = 1 in { - defm CMPSS : sse12_cmp_scalar, XS; - defm CMPSD : sse12_cmp_scalar, XD; +def CMPSSrr_alt : SIi8<0xC2, MRMSrcReg, + (outs FR32:$dst), (ins FR32:$src1, FR32:$src, i8imm:$src2), + "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS; +def CMPSSrm_alt : SIi8<0xC2, MRMSrcMem, + (outs FR32:$dst), (ins FR32:$src1, f32mem:$src, i8imm:$src2), + "cmpss\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XS; +def CMPSDrr_alt : SIi8<0xC2, MRMSrcReg, + (outs FR64:$dst), (ins FR64:$src1, FR64:$src, i8imm:$src2), + "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD; +def CMPSDrm_alt : SIi8<0xC2, MRMSrcMem, + (outs FR64:$dst), (ins FR64:$src1, f64mem:$src, i8imm:$src2), + "cmpsd\t{$src2, $src, $dst|$dst, $src, $src2}", []>, XD; } multiclass sse12_cmp_scalar_int %t -; RUN: not grep cmp %t -; RUN: not grep xor %t -; RUN: grep jne %t | count 1 -; RUN: grep jp %t | count 1 -; RUN: grep setnp %t | count 1 -; RUN: grep sete %t | count 1 -; RUN: grep and %t | count 1 -; RUN: grep cvt %t | count 4 +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s define i32 @isint_return(double %d) nounwind { +; CHECK-NOT: xor +; CHECK: cvt %i = fptosi double %d to i32 +; CHECK-NEXT: cvt %e = sitofp i32 %i to double +; CHECK: cmpeqsd %c = fcmp oeq double %d, %e +; CHECK-NEXT: movd +; CHECK-NEXT: andl %z = zext i1 %c to i32 ret i32 %z } @@ -19,9 +17,14 @@ declare void @foo() define void @isint_branch(double %d) nounwind { +; CHECK: cvt %i = fptosi double %d to i32 +; CHECK-NEXT: cvt %e = sitofp i32 %i to double +; CHECK: ucomisd %c = fcmp oeq double %d, %e +; CHECK-NEXT: jne +; CHECK-NEXT: jp br i1 %c, label %true, label %false true: call void @foo() Modified: llvm/trunk/test/CodeGen/X86/pr9127.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr9127.ll?rev=132606&r1=132605&r2=132606&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr9127.ll (original) +++ llvm/trunk/test/CodeGen/X86/pr9127.ll Fri Jun 3 18:53:54 2011 @@ -10,4 +10,4 @@ } ; test that the load is folded. -; CHECK: ucomisd (%{{rdi|rdx}}), %xmm0 +; CHECK: cmpeqsd (%{{rdi|rdx}}), %xmm0 Modified: llvm/trunk/test/CodeGen/X86/setoeq.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/setoeq.ll?rev=132606&r1=132605&r2=132606&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/setoeq.ll (original) +++ llvm/trunk/test/CodeGen/X86/setoeq.ll Fri Jun 3 18:53:54 2011 @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=x86 | grep set | count 2 -; RUN: llc < %s -march=x86 | grep and +; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s define zeroext i8 @t(double %x) nounwind readnone { entry: @@ -7,5 +6,16 @@ %1 = sitofp i32 %0 to double ; [#uses=1] %2 = fcmp oeq double %1, %x ; [#uses=1] %retval12 = zext i1 %2 to i8 ; [#uses=1] +; CHECK: cmpeqsd + ret i8 %retval12 +} + +define zeroext i8 @u(double %x) nounwind readnone { +entry: + %0 = fptosi double %x to i32 ; [#uses=1] + %1 = sitofp i32 %0 to double ; [#uses=1] + %2 = fcmp une double %1, %x ; [#uses=1] + %retval12 = zext i1 %2 to i8 ; [#uses=1] +; CHECK: cmpneqsd ret i8 %retval12 } From gohman at apple.com Fri Jun 3 19:31:50 2011 From: gohman at apple.com (Dan Gohman) Date: Sat, 04 Jun 2011 00:31:50 -0000 Subject: [llvm-commits] [llvm] r132609 - in /llvm/trunk: include/llvm/Analysis/AliasAnalysis.h lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/dag.ll Message-ID: <20110604003150.56C652A6C12C@llvm.org> Author: djg Date: Fri Jun 3 19:31:50 2011 New Revision: 132609 URL: http://llvm.org/viewvc/llvm-project?rev=132609&view=rev Log: Fix BasicAA's recursion detection so that it doesn't pessimize queries in the case of a DAG, where a query reaches a node visited earlier, but it's not on a cycle. This avoids MayAlias results in cases where BasicAA is expected to return MustAlias or PartialAlias in order to protect TBAA. Added: llvm/trunk/test/Analysis/BasicAA/dag.ll Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Modified: llvm/trunk/include/llvm/Analysis/AliasAnalysis.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/AliasAnalysis.h?rev=132609&r1=132608&r2=132609&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/AliasAnalysis.h (original) +++ llvm/trunk/include/llvm/Analysis/AliasAnalysis.h Fri Jun 3 19:31:50 2011 @@ -38,6 +38,7 @@ #define LLVM_ANALYSIS_ALIAS_ANALYSIS_H #include "llvm/Support/CallSite.h" +#include "llvm/ADT/DenseMap.h" namespace llvm { @@ -488,6 +489,32 @@ } }; +// Specialize DenseMapInfo for Location. +template<> +struct DenseMapInfo { + static inline AliasAnalysis::Location getEmptyKey() { + return + AliasAnalysis::Location(DenseMapInfo::getEmptyKey(), + 0, 0); + } + static inline AliasAnalysis::Location getTombstoneKey() { + return + AliasAnalysis::Location(DenseMapInfo::getTombstoneKey(), + 0, 0); + } + static unsigned getHashValue(const AliasAnalysis::Location &Val) { + return DenseMapInfo::getHashValue(Val.Ptr) ^ + DenseMapInfo::getHashValue(Val.Size) ^ + DenseMapInfo::getHashValue(Val.TBAATag); + } + static bool isEqual(const AliasAnalysis::Location &LHS, + const AliasAnalysis::Location &RHS) { + return LHS.Ptr == RHS.Ptr && + LHS.Size == RHS.Size && + LHS.TBAATag == RHS.TBAATag; + } +}; + /// isNoAliasCall - Return true if this pointer is returned by a noalias /// function. bool isNoAliasCall(const Value *V); Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=132609&r1=132608&r2=132609&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Fri Jun 3 19:31:50 2011 @@ -465,12 +465,12 @@ virtual AliasResult alias(const Location &LocA, const Location &LocB) { - assert(Visited.empty() && "Visited must be cleared after use!"); + assert(AliasCache.empty() && "AliasCache must be cleared after use!"); assert(notDifferentParent(LocA.Ptr, LocB.Ptr) && "BasicAliasAnalysis doesn't support interprocedural queries."); AliasResult Alias = aliasCheck(LocA.Ptr, LocA.Size, LocA.TBAATag, LocB.Ptr, LocB.Size, LocB.TBAATag); - Visited.clear(); + AliasCache.clear(); return Alias; } @@ -506,7 +506,12 @@ } private: - // Visited - Track instructions visited by a aliasPHI, aliasSelect(), and aliasGEP(). + // AliasCache - Track alias queries to guard against recursion. + typedef std::pair LocPair; + typedef DenseMap AliasCacheTy; + AliasCacheTy AliasCache; + + // Visited - Track instructions visited by pointsToConstantMemory. SmallPtrSet Visited; // aliasGEP - Provide a bunch of ad-hoc rules to disambiguate a GEP @@ -822,13 +827,6 @@ const MDNode *V2TBAAInfo, const Value *UnderlyingV1, const Value *UnderlyingV2) { - // If this GEP has been visited before, we're on a use-def cycle. - // Such cycles are only valid when PHI nodes are involved or in unreachable - // code. The visitPHI function catches cycles containing PHIs, but there - // could still be a cycle without PHIs in unreachable code. - if (!Visited.insert(GEP1)) - return MayAlias; - int64_t GEP1BaseOffset; SmallVector GEP1VariableIndices; @@ -969,13 +967,6 @@ const MDNode *SITBAAInfo, const Value *V2, uint64_t V2Size, const MDNode *V2TBAAInfo) { - // If this select has been visited before, we're on a use-def cycle. - // Such cycles are only valid when PHI nodes are involved or in unreachable - // code. The visitPHI function catches cycles containing PHIs, but there - // could still be a cycle without PHIs in unreachable code. - if (!Visited.insert(SI)) - return MayAlias; - // If the values are Selects with the same condition, we can do a more precise // check: just check for aliases between the values on corresponding arms. if (const SelectInst *SI2 = dyn_cast(V2)) @@ -998,11 +989,6 @@ if (Alias == MayAlias) return MayAlias; - // If V2 is visited, the recursive case will have been caught in the - // above aliasCheck call, so these subsequent calls to aliasCheck - // don't need to assume that V2 is being visited recursively. - Visited.erase(V2); - AliasResult ThisAlias = aliasCheck(V2, V2Size, V2TBAAInfo, SI->getFalseValue(), SISize, SITBAAInfo); return MergeAliasResults(ThisAlias, Alias); @@ -1015,10 +1001,6 @@ const MDNode *PNTBAAInfo, const Value *V2, uint64_t V2Size, const MDNode *V2TBAAInfo) { - // The PHI node has already been visited, avoid recursion any further. - if (!Visited.insert(PN)) - return MayAlias; - // If the values are PHIs in the same block, we can do a more precise // as well as efficient check: just check for aliases between the values // on corresponding edges. @@ -1068,11 +1050,6 @@ for (unsigned i = 1, e = V1Srcs.size(); i != e; ++i) { Value *V = V1Srcs[i]; - // If V2 is visited, the recursive case will have been caught in the - // above aliasCheck call, so these subsequent calls to aliasCheck - // don't need to assume that V2 is being visited recursively. - Visited.erase(V2); - AliasResult ThisAlias = aliasCheck(V2, V2Size, V2TBAAInfo, V, PNSize, PNTBAAInfo); Alias = MergeAliasResults(ThisAlias, Alias); @@ -1162,6 +1139,17 @@ (V2Size != UnknownSize && isObjectSmallerThan(O1, V2Size, *TD))) return NoAlias; + // Check the cache before climbing up use-def chains. This also terminates + // otherwise infinitely recursive queries. + LocPair Locs(Location(V1, V1Size, V1TBAAInfo), + Location(V2, V2Size, V2TBAAInfo)); + if (V1 > V2) + std::swap(Locs.first, Locs.second); + std::pair Pair = + AliasCache.insert(std::make_pair(Locs, MayAlias)); + if (!Pair.second) + return Pair.first->second; + // FIXME: This isn't aggressively handling alias(GEP, PHI) for example: if the // GEP can't simplify, we don't even look at the PHI cases. if (!isa(V1) && isa(V2)) { @@ -1171,7 +1159,7 @@ } if (const GEPOperator *GV1 = dyn_cast(V1)) { AliasResult Result = aliasGEP(GV1, V1Size, V2, V2Size, V2TBAAInfo, O1, O2); - if (Result != MayAlias) return Result; + if (Result != MayAlias) return AliasCache[Locs] = Result; } if (isa(V2) && !isa(V1)) { @@ -1181,7 +1169,7 @@ if (const PHINode *PN = dyn_cast(V1)) { AliasResult Result = aliasPHI(PN, V1Size, V1TBAAInfo, V2, V2Size, V2TBAAInfo); - if (Result != MayAlias) return Result; + if (Result != MayAlias) return AliasCache[Locs] = Result; } if (isa(V2) && !isa(V1)) { @@ -1191,7 +1179,7 @@ if (const SelectInst *S1 = dyn_cast(V1)) { AliasResult Result = aliasSelect(S1, V1Size, V1TBAAInfo, V2, V2Size, V2TBAAInfo); - if (Result != MayAlias) return Result; + if (Result != MayAlias) return AliasCache[Locs] = Result; } // If both pointers are pointing into the same object and one of them @@ -1200,8 +1188,10 @@ if (TD && O1 == O2) if ((V1Size != UnknownSize && isObjectSize(O1, V1Size, *TD)) || (V2Size != UnknownSize && isObjectSize(O2, V2Size, *TD))) - return PartialAlias; + return AliasCache[Locs] = PartialAlias; - return AliasAnalysis::alias(Location(V1, V1Size, V1TBAAInfo), - Location(V2, V2Size, V2TBAAInfo)); + AliasResult Result = + AliasAnalysis::alias(Location(V1, V1Size, V1TBAAInfo), + Location(V2, V2Size, V2TBAAInfo)); + return AliasCache[Locs] = Result; } Added: llvm/trunk/test/Analysis/BasicAA/dag.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/dag.ll?rev=132609&view=auto ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/dag.ll (added) +++ llvm/trunk/test/Analysis/BasicAA/dag.ll Fri Jun 3 19:31:50 2011 @@ -0,0 +1,41 @@ +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info |& FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" + +; BasicAA's guard against use-def cycles shouldn't prevent it from +; analyzing use-def dags. + +; CHECK: MustAlias: i8* %base, i8* %phi +; CHECK: MustAlias: i8* %phi, i8* %wwa +; CHECK: MustAlias: i8* %phi, i8* %wwb +; CHECK: MustAlias: i16* %bigbase, i8* %phi +define i8 @foo(i8* %base, i1 %x, i1 %w) { +entry: + br i1 %w, label %wa, label %wb +wa: + %wwa = bitcast i8* %base to i8* + br label %wc +wb: + %wwb = bitcast i8* %base to i8* + br label %wc +wc: + %first = phi i8* [ %wwa, %wa ], [ %wwb, %wb ] + %fc = bitcast i8* %first to i8* + br i1 %x, label %xa, label %xb +xa: + %xxa = bitcast i8* %fc to i8* + br label %xc +xb: + %xxb = bitcast i8* %fc to i8* + br label %xc +xc: + %phi = phi i8* [ %xxa, %xa ], [ %xxb, %xb ] + + store i8 0, i8* %phi + + %bigbase = bitcast i8* %base to i16* + store i16 -1, i16* %bigbase + + %loaded = load i8* %phi + ret i8 %loaded +} From gohman at apple.com Fri Jun 3 19:46:32 2011 From: gohman at apple.com (Dan Gohman) Date: Sat, 04 Jun 2011 00:46:32 -0000 Subject: [llvm-commits] [llvm] r132611 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll Message-ID: <20110604004632.2125D2A6C12C@llvm.org> Author: djg Date: Fri Jun 3 19:46:31 2011 New Revision: 132611 URL: http://llvm.org/viewvc/llvm-project?rev=132611&view=rev Log: Reapply r131781 (revert r131809), now that some BasicAA shortcomings it exposed are fixed. Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll - copied unchanged from r131808, llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=132611&r1=132610&r2=132611&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Fri Jun 3 19:46:31 2011 @@ -944,7 +944,17 @@ return NoAlias; } - return MayAlias; + // Statically, we can see that the base objects are the same, but the + // pointers have dynamic offsets which we can't resolve. And none of our + // little tricks above worked. + // + // TODO: Returning PartialAlias instead of MayAlias is a mild hack; the + // practical effect of this is protecting TBAA in the case of dynamic + // indices into arrays of unions. An alternative way to solve this would + // be to have clang emit extra metadata for unions and/or union accesses. + // A union-specific solution wouldn't handle the problem for malloc'd + // memory however. + return PartialAlias; } static AliasAnalysis::AliasResult Modified: llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll?rev=132611&r1=132610&r2=132611&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll (original) +++ llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll Fri Jun 3 19:46:31 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {1 may alias} +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {1 partial alias} ; PR7959 target datalayout = "e-p:32:32:32" From atrick at apple.com Fri Jun 3 20:16:30 2011 From: atrick at apple.com (Andrew Trick) Date: Sat, 04 Jun 2011 01:16:30 -0000 Subject: [llvm-commits] [llvm] r132613 - in /llvm/trunk: include/llvm/Analysis/BranchProbabilityInfo.h include/llvm/InitializePasses.h lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp lib/Analysis/CMakeLists.txt Message-ID: <20110604011630.EB7B52A6C12C@llvm.org> Author: atrick Date: Fri Jun 3 20:16:30 2011 New Revision: 132613 URL: http://llvm.org/viewvc/llvm-project?rev=132613&view=rev Log: New BranchProbabilityInfo analysis. Patch by Jakub Staszak! BranchProbabilityInfo provides an interface for IR passes to query the likelihood that control follows a CFG edge. This patch provides an initial implementation of static branch predication that will populate BranchProbabilityInfo for branches with no external profile information using very simple heuristics. It currently isn't hooked up to any external profile data, so static prediction does all the work. Added: llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Modified: llvm/trunk/include/llvm/InitializePasses.h llvm/trunk/lib/Analysis/Analysis.cpp llvm/trunk/lib/Analysis/CMakeLists.txt Added: llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h?rev=132613&view=auto ============================================================================== --- llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h (added) +++ llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h Fri Jun 3 20:16:30 2011 @@ -0,0 +1,68 @@ +//===--- BranchProbabilityInfo.h - Branch Probability Analysis --*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This pass is used to evaluate branch probabilties. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_ANALYSIS_BRANCHPROBABILITYINFO_H +#define LLVM_ANALYSIS_BRANCHPROBABILITYINFO_H + +#include "llvm/InitializePasses.h" +#include "llvm/Analysis/LoopInfo.h" +#include "llvm/Support/Debug.h" + +namespace llvm { + +class BranchProbabilityInfo : public FunctionPass { + + // Default weight value. Used when we don't have information about the edge. + static const unsigned int DEFAULT_WEIGHT = 16; + + typedef std::pair Edge; + + DenseMap Weights; + +public: + static char ID; + + BranchProbabilityInfo() : FunctionPass(ID) { + initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); + } + + void getAnalysisUsage(AnalysisUsage &AU) const { + AU.addRequired(); + AU.setPreservesAll(); + } + + bool runOnFunction(Function &F); + + // Returned value is between 1 and UINT_MAX. Look at BranchProbabilityInfo.cpp + // for details. + unsigned getEdgeWeight(BasicBlock *Src, BasicBlock *Dst) const; + + // Look at BranchProbabilityInfo.cpp for details. Use it with caution! + void setEdgeWeight(BasicBlock *Src, BasicBlock *Dst, unsigned Weight); + + // A 'Hot' edge is an edge which probability is >= 80%. + bool isEdgeHot(BasicBlock *Src, BasicBlock *Dst) const; + + // Return a hot successor for the block BB or null if there isn't one. + BasicBlock *getHotSucc(BasicBlock *BB) const; + + // Print value between 0 (0% probability) and 1 (100% probability), + // however the value is never equal to 0, and can be 1 only iff SRC block + // has only one successor. + raw_ostream &printEdgeProbability(raw_ostream &OS, BasicBlock *Src, + BasicBlock *Dst) const; +}; + +} + +#endif Modified: llvm/trunk/include/llvm/InitializePasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=132613&r1=132612&r2=132613&view=diff ============================================================================== --- llvm/trunk/include/llvm/InitializePasses.h (original) +++ llvm/trunk/include/llvm/InitializePasses.h Fri Jun 3 20:16:30 2011 @@ -66,6 +66,7 @@ void initializeBasicCallGraphPass(PassRegistry&); void initializeBlockExtractorPassPass(PassRegistry&); void initializeBlockPlacementPass(PassRegistry&); +void initializeBranchProbabilityInfoPass(PassRegistry&); void initializeBreakCriticalEdgesPass(PassRegistry&); void initializeCFGOnlyPrinterPass(PassRegistry&); void initializeCFGOnlyViewerPass(PassRegistry&); Modified: llvm/trunk/lib/Analysis/Analysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Analysis.cpp?rev=132613&r1=132612&r2=132613&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/Analysis.cpp (original) +++ llvm/trunk/lib/Analysis/Analysis.cpp Fri Jun 3 20:16:30 2011 @@ -23,6 +23,7 @@ initializeAliasSetPrinterPass(Registry); initializeNoAAPass(Registry); initializeBasicAliasAnalysisPass(Registry); + initializeBranchProbabilityInfoPass(Registry); initializeCFGViewerPass(Registry); initializeCFGPrinterPass(Registry); initializeCFGOnlyViewerPass(Registry); Added: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=132613&view=auto ============================================================================== --- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (added) +++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Fri Jun 3 20:16:30 2011 @@ -0,0 +1,348 @@ +//===-- BranchProbabilityInfo.cpp - Branch Probability Analysis -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Loops should be simplified before this analysis. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Instructions.h" +#include "llvm/Analysis/BranchProbabilityInfo.h" + +using namespace llvm; + +INITIALIZE_PASS_BEGIN(BranchProbabilityInfo, "branch-prob", + "Branch Probability Analysis", false, true) +INITIALIZE_PASS_DEPENDENCY(LoopInfo) +INITIALIZE_PASS_END(BranchProbabilityInfo, "branch-prob", + "Branch Probability Analysis", false, true) + +char BranchProbabilityInfo::ID = 0; + + +// Please note that BranchProbabilityAnalysis is not a FunctionPass. +// It is created by BranchProbabilityInfo (which is a FunctionPass), which +// provides a clear interface. Thanks to that, all heuristics and other +// private methods are hidden in the .cpp file. +class BranchProbabilityAnalysis { + + typedef std::pair Edge; + + DenseMap *Weights; + + BranchProbabilityInfo *BP; + + LoopInfo *LI; + + + // Weights are for internal use only. They are used by heuristics to help to + // estimate edges' probability. Example: + // + // Using "Loop Branch Heuristics" we predict weights of edges for the + // block BB2. + // ... + // | + // V + // BB1<-+ + // | | + // | | (Weight = 128) + // V | + // BB2--+ + // | + // | (Weight = 4) + // V + // BB3 + // + // Probability of the edge BB2->BB1 = 128 / (128 + 4) = 0.9696.. + // Probability of the edge BB2->BB3 = 4 / (128 + 4) = 0.0303.. + + static const unsigned int LBH_TAKEN_WEIGHT = 128; + static const unsigned int LBH_NONTAKEN_WEIGHT = 4; + + // Standard weight value. Used when none of the heuristics set weight for + // the edge. + static const unsigned int NORMAL_WEIGHT = 16; + + // Minimum weight of an edge. Please note, that weight is NEVER 0. + static const unsigned int MIN_WEIGHT = 1; + + // Return TRUE if BB leads directly to a Return Instruction. + static bool isReturningBlock(BasicBlock *BB) { + SmallPtrSet Visited; + + while (true) { + TerminatorInst *TI = BB->getTerminator(); + if (isa(TI)) + return true; + + if (TI->getNumSuccessors() > 1) + break; + + // It is unreachable block which we can consider as a return instruction. + if (TI->getNumSuccessors() == 0) + return true; + + Visited.insert(BB); + BB = TI->getSuccessor(0); + + // Stop if cycle is detected. + if (Visited.count(BB)) + return false; + } + + return false; + } + + // Multiply Edge Weight by two. + void incEdgeWeight(BasicBlock *Src, BasicBlock *Dst) { + unsigned Weight = BP->getEdgeWeight(Src, Dst); + unsigned MaxWeight = getMaxWeightFor(Src); + + if (Weight * 2 > MaxWeight) + BP->setEdgeWeight(Src, Dst, MaxWeight); + else + BP->setEdgeWeight(Src, Dst, Weight * 2); + } + + // Divide Edge Weight by two. + void decEdgeWeight(BasicBlock *Src, BasicBlock *Dst) { + unsigned Weight = BP->getEdgeWeight(Src, Dst); + + assert(Weight > 0); + if (Weight / 2 < MIN_WEIGHT) + BP->setEdgeWeight(Src, Dst, MIN_WEIGHT); + else + BP->setEdgeWeight(Src, Dst, Weight / 2); + } + + + unsigned getMaxWeightFor(BasicBlock *BB) const { + return UINT_MAX / BB->getTerminator()->getNumSuccessors(); + } + +public: + BranchProbabilityAnalysis(DenseMap *W, + BranchProbabilityInfo *BP, LoopInfo *LI) + : Weights(W), BP(BP), LI(LI) { + } + + // Return Heuristics + void calcReturnHeuristics(BasicBlock *BB); + + // Pointer Heuristics + void calcPointerHeuristics(BasicBlock *BB); + + // Loop Branch Heuristics + void calcLoopBranchHeuristics(BasicBlock *BB); + + bool runOnFunction(Function &F); +}; + +// Calculate Edge Weights using "Return Heuristics". Predict a successor which +// leads directly to Return Instruction will not be taken. +void BranchProbabilityAnalysis::calcReturnHeuristics(BasicBlock *BB){ + if (BB->getTerminator()->getNumSuccessors() == 1) + return; + + for (succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) { + BasicBlock *Succ = *I; + if (isReturningBlock(Succ)) { + decEdgeWeight(BB, Succ); + } + } +} + +// Calculate Edge Weights using "Pointer Heuristics". Predict a comparsion +// between two pointer or pointer and NULL will fail. +void BranchProbabilityAnalysis::calcPointerHeuristics(BasicBlock *BB) { + BranchInst * BI = dyn_cast(BB->getTerminator()); + if (!BI || !BI->isConditional()) + return; + + Value *Cond = BI->getCondition(); + ICmpInst *CI = dyn_cast(Cond); + if (!CI) + return; + + Value *LHS = CI->getOperand(0); + Value *RHS = CI->getOperand(1); + + if (!LHS->getType()->isPointerTy()) + return; + + assert(RHS->getType()->isPointerTy()); + + BasicBlock *Taken = BI->getSuccessor(0); + BasicBlock *NonTaken = BI->getSuccessor(1); + + // p != 0 -> isProb = true + // p == 0 -> isProb = false + // p != q -> isProb = true + // p == q -> isProb = false; + bool isProb = !CI->isEquality(); + if (!isProb) + std::swap(Taken, NonTaken); + + incEdgeWeight(BB, Taken); + decEdgeWeight(BB, NonTaken); +} + +// Calculate Edge Weights using "Loop Branch Heuristics". Predict backedges +// as taken, exiting edges as not-taken. +void BranchProbabilityAnalysis::calcLoopBranchHeuristics(BasicBlock *BB) { + unsigned numSuccs = BB->getTerminator()->getNumSuccessors(); + + Loop *L = LI->getLoopFor(BB); + if (!L) + return; + + SmallVector BackEdges; + SmallVector ExitingEdges; + + for (succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) { + BasicBlock *Succ = *I; + Loop *SuccL = LI->getLoopFor(Succ); + if (SuccL != L) + ExitingEdges.push_back(Succ); + else if (Succ == L->getHeader()) + BackEdges.push_back(Succ); + } + + if (unsigned numBackEdges = BackEdges.size()) { + unsigned backWeight = LBH_TAKEN_WEIGHT / numBackEdges; + if (backWeight < NORMAL_WEIGHT) + backWeight = NORMAL_WEIGHT; + + for (SmallVector::iterator EI = BackEdges.begin(), + EE = BackEdges.end(); EI != EE; ++EI) { + BasicBlock *Back = *EI; + BP->setEdgeWeight(BB, Back, backWeight); + } + } + + unsigned numExitingEdges = ExitingEdges.size(); + if (unsigned numNonExitingEdges = numSuccs - numExitingEdges) { + unsigned exitWeight = LBH_NONTAKEN_WEIGHT / numNonExitingEdges; + if (exitWeight < MIN_WEIGHT) + exitWeight = MIN_WEIGHT; + + for (SmallVector::iterator EI = ExitingEdges.begin(), + EE = ExitingEdges.end(); EI != EE; ++EI) { + BasicBlock *Exiting = *EI; + BP->setEdgeWeight(BB, Exiting, exitWeight); + } + } +} + +bool BranchProbabilityAnalysis::runOnFunction(Function &F) { + + for (Function::iterator I = F.begin(), E = F.end(); I != E; ) { + BasicBlock *BB = I++; + + // Only LBH uses setEdgeWeight method. + calcLoopBranchHeuristics(BB); + + // PH and RH use only incEdgeWeight and decEwdgeWeight methods to + // not efface LBH results. + calcPointerHeuristics(BB); + calcReturnHeuristics(BB); + } + + return false; +} + + +bool BranchProbabilityInfo::runOnFunction(Function &F) { + LoopInfo &LI = getAnalysis(); + BranchProbabilityAnalysis BPA(&Weights, this, &LI); + bool ret = BPA.runOnFunction(F); + return ret; +} + +// TODO: This currently hardcodes 80% as a fraction 4/5. We will soon add a +// BranchProbability class to encapsulate the fractional probability and +// define a few static instances of the class for use as predefined thresholds. +bool BranchProbabilityInfo::isEdgeHot(BasicBlock *Src, BasicBlock *Dst) const { + unsigned Sum = 0; + for (succ_iterator I = succ_begin(Src), E = succ_end(Src); I != E; ++I) { + BasicBlock *Succ = *I; + unsigned Weight = getEdgeWeight(Src, Succ); + unsigned PrevSum = Sum; + + Sum += Weight; + assert(Sum > PrevSum); (void) PrevSum; + } + + return getEdgeWeight(Src, Dst) * 5 > Sum * 4; +} + +BasicBlock *BranchProbabilityInfo::getHotSucc(BasicBlock *BB) const { + unsigned Sum = 0; + unsigned MaxWeight = 0; + BasicBlock *MaxSucc = 0; + + for (succ_iterator I = succ_begin(BB), E = succ_end(BB); I != E; ++I) { + BasicBlock *Succ = *I; + unsigned Weight = getEdgeWeight(BB, Succ); + unsigned PrevSum = Sum; + + Sum += Weight; + assert(Sum > PrevSum); (void) PrevSum; + + if (Weight > MaxWeight) { + MaxWeight = Weight; + MaxSucc = Succ; + } + } + + if (MaxWeight * 5 > Sum * 4) + return MaxSucc; + + return 0; +} + +// Return edge's weight. If can't find it, return DEFAULT_WEIGHT value. +unsigned +BranchProbabilityInfo::getEdgeWeight(BasicBlock *Src, BasicBlock *Dst) const { + Edge E(Src, Dst); + DenseMap::const_iterator I = Weights.find(E); + + if (I != Weights.end()) + return I->second; + + return DEFAULT_WEIGHT; +} + +void BranchProbabilityInfo::setEdgeWeight(BasicBlock *Src, BasicBlock *Dst, + unsigned Weight) { + Weights[std::make_pair(Src, Dst)] = Weight; + DEBUG(dbgs() << "setEdgeWeight: " << Src->getNameStr() << " -> " + << Dst->getNameStr() << " to " << Weight + << (isEdgeHot(Src, Dst) ? " [is HOT now]\n" : "\n")); +} + +raw_ostream & +BranchProbabilityInfo::printEdgeProbability(raw_ostream &OS, BasicBlock *Src, + BasicBlock *Dst) const { + + unsigned Sum = 0; + for (succ_iterator I = succ_begin(Src), E = succ_end(Src); I != E; ++I) { + BasicBlock *Succ = *I; + unsigned Weight = getEdgeWeight(Src, Succ); + unsigned PrevSum = Sum; + + Sum += Weight; + assert(Sum > PrevSum); (void) PrevSum; + } + + double Prob = (double)getEdgeWeight(Src, Dst) / Sum; + OS << "probability (" << Src->getNameStr() << " --> " << Dst->getNameStr() + << ") = " << Prob << "\n"; + + return OS; +} Modified: llvm/trunk/lib/Analysis/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CMakeLists.txt?rev=132613&r1=132612&r2=132613&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/CMakeLists.txt (original) +++ llvm/trunk/lib/Analysis/CMakeLists.txt Fri Jun 3 20:16:30 2011 @@ -6,6 +6,7 @@ AliasSetTracker.cpp Analysis.cpp BasicAliasAnalysis.cpp + BranchProbabilityInfo.cpp CFGPrinter.cpp CaptureTracking.cpp ConstantFolding.cpp From atrick at apple.com Fri Jun 3 20:30:52 2011 From: atrick at apple.com (Andrew Trick) Date: Sat, 04 Jun 2011 01:30:52 -0000 Subject: [llvm-commits] [llvm] r132616 - /llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Message-ID: <20110604013052.937B12A6C12C@llvm.org> Author: atrick Date: Fri Jun 3 20:30:52 2011 New Revision: 132616 URL: http://llvm.org/viewvc/llvm-project?rev=132616&view=rev Log: Missing include of climits in the new BranchProbability pass. Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=132616&r1=132615&r2=132616&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original) +++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Fri Jun 3 20:30:52 2011 @@ -13,6 +13,7 @@ #include "llvm/Instructions.h" #include "llvm/Analysis/BranchProbabilityInfo.h" +#include using namespace llvm; From nicholas at mxc.ca Fri Jun 3 21:07:10 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Sat, 04 Jun 2011 02:07:10 -0000 Subject: [llvm-commits] [llvm] r132620 - /llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Message-ID: <20110604020710.BB0C12A6C12C@llvm.org> Author: nicholas Date: Fri Jun 3 21:07:10 2011 New Revision: 132620 URL: http://llvm.org/viewvc/llvm-project?rev=132620&view=rev Log: Fold assert-only-used variable into the assert. Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=132620&r1=132619&r2=132620&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original) +++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Fri Jun 3 21:07:10 2011 @@ -171,12 +171,11 @@ return; Value *LHS = CI->getOperand(0); - Value *RHS = CI->getOperand(1); if (!LHS->getType()->isPointerTy()) return; - assert(RHS->getType()->isPointerTy()); + assert(CI->getOperand(1)->getType()->isPointerTy()); BasicBlock *Taken = BI->getSuccessor(0); BasicBlock *NonTaken = BI->getSuccessor(1); From arplynn at gmail.com Fri Jun 3 21:29:51 2011 From: arplynn at gmail.com (Alistair Lynn) Date: Sat, 4 Jun 2011 03:29:51 +0100 Subject: [llvm-commits] [llvm] r132613 - in /llvm/trunk: include/llvm/Analysis/BranchProbabilityInfo.h include/llvm/InitializePasses.h lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp lib/Analysis/CMakeLists.txt In-Reply-To: <20110604011630.EB7B52A6C12C@llvm.org> References: <20110604011630.EB7B52A6C12C@llvm.org> Message-ID: <05052AFC-4F19-4689-8E3D-37B7A083C472@gmail.com> Hi- Given that > + // Returned value is between 1 and UINT_MAX. Look at BranchProbabilityInfo.cpp > + // for details. Is this function not prone to integer overflow issues? > +// TODO: This currently hardcodes 80% as a fraction 4/5. We will soon add a > +// BranchProbability class to encapsulate the fractional probability and > +// define a few static instances of the class for use as predefined thresholds. > +bool BranchProbabilityInfo::isEdgeHot(BasicBlock *Src, BasicBlock *Dst) const { > + unsigned Sum = 0; > + for (succ_iterator I = succ_begin(Src), E = succ_end(Src); I != E; ++I) { > + BasicBlock *Succ = *I; > + unsigned Weight = getEdgeWeight(Src, Succ); > + unsigned PrevSum = Sum; > + > + Sum += Weight; > + assert(Sum > PrevSum); (void) PrevSum; > + } > + > + return getEdgeWeight(Src, Dst) * 5 > Sum * 4; > +} The sum itself is checked for overflow in the assert, but surely there's nothing preventing overflow on the multiplies on the condition at the end? Alistair From stoklund at 2pi.dk Fri Jun 3 23:11:37 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 04 Jun 2011 04:11:37 -0000 Subject: [llvm-commits] [llvm] r132621 - in /llvm/trunk: test/TableGen/SetTheory.td utils/TableGen/CMakeLists.txt utils/TableGen/SetTheory.cpp utils/TableGen/SetTheory.h utils/TableGen/TableGen.cpp Message-ID: <20110604041137.924822A6C12C@llvm.org> Author: stoklund Date: Fri Jun 3 23:11:37 2011 New Revision: 132621 URL: http://llvm.org/viewvc/llvm-project?rev=132621&view=rev Log: Teach TableGen to evaluate DAG expressions as set operations. A TableGen backend can define how certain classes can be expanded into ordered sets of defs, typically by evaluating a specific field in the record. The SetTheory class can then evaluate DAG expressions that refer to these named sets. A number of standard set and list operations are predefined, and the backend can add more specialized operators if needed. The -print-sets backend is used by SetTheory.td to provide examples. This is intended to simplify how register classes are defined: def GR32_NOSP : RegisterClass<"X86", [i32], 32, (sub GR32, ESP)>; Added: llvm/trunk/test/TableGen/SetTheory.td llvm/trunk/utils/TableGen/SetTheory.cpp llvm/trunk/utils/TableGen/SetTheory.h Modified: llvm/trunk/utils/TableGen/CMakeLists.txt llvm/trunk/utils/TableGen/TableGen.cpp Added: llvm/trunk/test/TableGen/SetTheory.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/SetTheory.td?rev=132621&view=auto ============================================================================== --- llvm/trunk/test/TableGen/SetTheory.td (added) +++ llvm/trunk/test/TableGen/SetTheory.td Fri Jun 3 23:11:37 2011 @@ -0,0 +1,167 @@ +// Test evaluation of set operations in dags. +// RUN: tblgen -print-sets %s | FileCheck %s +// XFAIL: vg_leak +// +// The -print-sets driver configures a primitive SetTheory instance that +// understands these sets: + +class Set { + dag Elements = d; +} + +// It prints all Set instances and their ordered set interpretation. + +// Define some elements. +def a; +def b; +def c; +def d; + +// The 'add' operator evaluates and concatenates its arguments. +def add; +def S0a : Set<(add)>; +def S0b : Set<(add a)>; +def S0c : Set<(add a, b)>; +def S0d : Set<(add b, a)>; +def S0e : Set<(add a, a)>; +def S0f : Set<(add a, a, b, a, c, b, d, a)>; +def S0g : Set<(add b, a, b)>; +// CHECK: S0a = [ ] +// CHECK: S0b = [ a ] +// CHECK: S0c = [ a b ] +// CHECK: S0d = [ b a ] +// CHECK: S0e = [ a ] +// CHECK: S0f = [ a b c d ] +// CHECK: S0g = [ b a ] + +// Defs of Set class expand into their elements. +// Mixed sets and elements are flattened. +def S1a : Set<(add S0a)>; +def S1b : Set<(add S0a, S0a)>; +def S1c : Set<(add S0d, S0f)>; +def S1d : Set<(add d, S0d, S0f)>; +// CHECK: S1a = [ ] +// CHECK: S1b = [ ] +// CHECK: S1c = [ b a c d ] +// CHECK: S1d = [ d b a c ] + +// The 'sub' operator returns the first argument with the following arguments +// removed. +def sub; +def S2a : Set<(sub S1a, S1c)>; +def S2b : Set<(sub S1c, S1d)>; +def S2c : Set<(sub S1c, b)>; +def S2d : Set<(sub S1c, S0c)>; +def S2e : Set<(sub S1c, S2d)>; +// CHECK: S2a = [ ] +// CHECK: S2b = [ ] +// CHECK: S2c = [ a c d ] +// CHECK: S2d = [ c d ] +// CHECK: S2e = [ b a ] + +// The 'and' operator intersects two sets. The result has the same order as the +// first argument. +def and; +def S3a : Set<(and S2d, S2e)>; +def S3b : Set<(and S2d, S1d)>; +// CHECK: S3a = [ ] +// CHECK: S3b = [ c d ] + +// The 'shl' operator removes the first N elements. +def shl; +def S4a : Set<(shl S0f, 0)>; +def S4b : Set<(shl S0f, 1)>; +def S4c : Set<(shl S0f, 3)>; +def S4d : Set<(shl S0f, 4)>; +def S4e : Set<(shl S0f, 5)>; +// CHECK: S4a = [ a b c d ] +// CHECK: S4b = [ b c d ] +// CHECK: S4c = [ d ] +// CHECK: S4d = [ ] +// CHECK: S4e = [ ] + +// The 'trunc' operator truncates after the first N elements. +def trunc; +def S5a : Set<(trunc S0f, 0)>; +def S5b : Set<(trunc S0f, 1)>; +def S5c : Set<(trunc S0f, 3)>; +def S5d : Set<(trunc S0f, 4)>; +def S5e : Set<(trunc S0f, 5)>; +// CHECK: S5a = [ ] +// CHECK: S5b = [ a ] +// CHECK: S5c = [ a b c ] +// CHECK: S5d = [ a b c d ] +// CHECK: S5e = [ a b c d ] + +// The 'rotl' operator rotates left, but also accepts a negative shift. +def rotl; +def S6a : Set<(rotl S0f, 0)>; +def S6b : Set<(rotl S0f, 1)>; +def S6c : Set<(rotl S0f, 3)>; +def S6d : Set<(rotl S0f, 4)>; +def S6e : Set<(rotl S0f, 5)>; +def S6f : Set<(rotl S0f, -1)>; +def S6g : Set<(rotl S0f, -4)>; +def S6h : Set<(rotl S0f, -5)>; +// CHECK: S6a = [ a b c d ] +// CHECK: S6b = [ b c d a ] +// CHECK: S6c = [ d a b c ] +// CHECK: S6d = [ a b c d ] +// CHECK: S6e = [ b c d a ] +// CHECK: S6f = [ d a b c ] +// CHECK: S6g = [ a b c d ] +// CHECK: S6h = [ d a b c ] + +// The 'rotr' operator rotates right, but also accepts a negative shift. +def rotr; +def S7a : Set<(rotr S0f, 0)>; +def S7b : Set<(rotr S0f, 1)>; +def S7c : Set<(rotr S0f, 3)>; +def S7d : Set<(rotr S0f, 4)>; +def S7e : Set<(rotr S0f, 5)>; +def S7f : Set<(rotr S0f, -1)>; +def S7g : Set<(rotr S0f, -4)>; +def S7h : Set<(rotr S0f, -5)>; +// CHECK: S7a = [ a b c d ] +// CHECK: S7b = [ d a b c ] +// CHECK: S7c = [ b c d a ] +// CHECK: S7d = [ a b c d ] +// CHECK: S7e = [ d a b c ] +// CHECK: S7f = [ b c d a ] +// CHECK: S7g = [ a b c d ] +// CHECK: S7h = [ b c d a ] + +// The 'decimate' operator picks every N'th element. +def decimate; +def e0; +def e1; +def e2; +def e3; +def e4; +def e5; +def e6; +def e7; +def e8; +def e9; +def E : Set<(add e0, e1, e2, e3, e4, e5, e6, e7, e8, e9)>; +def S8a : Set<(decimate E, 3)>; +def S8b : Set<(decimate E, 9)>; +def S8c : Set<(decimate E, 10)>; +def S8d : Set<(decimate (rotl E, 1), 2)>; +def S8e : Set<(add (decimate E, 2), (decimate (rotl E, 1), 2))>; +// CHECK: S8a = [ e0 e3 e6 e9 ] +// CHECK: S8b = [ e0 e9 ] +// CHECK: S8c = [ e0 ] +// CHECK: S8d = [ e1 e3 e5 e7 e9 ] +// CHECK: S8e = [ e0 e2 e4 e6 e8 e1 e3 e5 e7 e9 ] + +// The 'sequence' operator finds a sequence of records from their name. +def sequence; +def S9a : Set<(sequence "e%u", 3, 7)>; +def S9b : Set<(sequence "e%u", 7, 3)>; +def S9c : Set<(sequence "e%u", 0, 0)>; +def S9d : Set<(sequence "S%ua", 7, 9)>; +// CHECK: S9a = [ e3 e4 e5 e6 e7 ] +// CHECK: S9b = [ e7 e6 e5 e4 e3 ] +// CHECK: S9c = [ e0 ] +// CHECK: S9d = [ a b c d e0 e3 e6 e9 e4 e5 e7 ] Modified: llvm/trunk/utils/TableGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=132621&r1=132620&r2=132621&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CMakeLists.txt (original) +++ llvm/trunk/utils/TableGen/CMakeLists.txt Fri Jun 3 23:11:37 2011 @@ -34,6 +34,7 @@ OptParserEmitter.cpp Record.cpp RegisterInfoEmitter.cpp + SetTheory.cpp StringMatcher.cpp SubtargetEmitter.cpp TGLexer.cpp Added: llvm/trunk/utils/TableGen/SetTheory.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SetTheory.cpp?rev=132621&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/SetTheory.cpp (added) +++ llvm/trunk/utils/TableGen/SetTheory.cpp Fri Jun 3 23:11:37 2011 @@ -0,0 +1,272 @@ +//===- SetTheory.cpp - Generate ordered sets from DAG expressions ---------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the SetTheory class that computes ordered sets of +// Records from DAG expressions. +// +//===----------------------------------------------------------------------===// + +#include "SetTheory.h" +#include "Record.h" +#include "llvm/Support/Format.h" + +using namespace llvm; + +// Define the standard operators. +namespace { + +typedef SetTheory::RecSet RecSet; +typedef SetTheory::RecVec RecVec; + +// (add a, b, ...) Evaluate and union all arguments. +struct AddOp : public SetTheory::Operator { + void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts) { + ST.evaluate(Expr->arg_begin(), Expr->arg_end(), Elts); + } +}; + +// (sub Add, Sub, ...) Set difference. +struct SubOp : public SetTheory::Operator { + void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts) { + if (Expr->arg_size() < 2) + throw "Set difference needs at least two arguments: " + + Expr->getAsString(); + RecSet Add, Sub; + ST.evaluate(*Expr->arg_begin(), Add); + ST.evaluate(Expr->arg_begin() + 1, Expr->arg_end(), Sub); + for (RecSet::iterator I = Add.begin(), E = Add.end(); I != E; ++I) + if (!Sub.count(*I)) + Elts.insert(*I); + } +}; + +// (and S1, S2) Set intersection. +struct AndOp : public SetTheory::Operator { + void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts) { + if (Expr->arg_size() != 2) + throw "Set intersection requires two arguments: " + Expr->getAsString(); + RecSet S1, S2; + ST.evaluate(Expr->arg_begin()[0], S1); + ST.evaluate(Expr->arg_begin()[1], S2); + for (RecSet::iterator I = S1.begin(), E = S1.end(); I != E; ++I) + if (S2.count(*I)) + Elts.insert(*I); + } +}; + +// SetIntBinOp - Abstract base class for (Op S, N) operators. +struct SetIntBinOp : public SetTheory::Operator { + virtual void apply(SetTheory &ST, DagInit *Expr, + RecSet &Set, int64_t N, + RecSet &Elts) =0; + + void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts) { + if (Expr->arg_size() != 2) + throw "Operator requires (Op Set, Int) arguments: " + Expr->getAsString(); + RecSet Set; + ST.evaluate(Expr->arg_begin()[0], Set); + IntInit *II = dynamic_cast(Expr->arg_begin()[1]); + if (!II) + throw "Second argument must be an integer: " + Expr->getAsString(); + apply(ST, Expr, Set, II->getValue(), Elts); + } +}; + +// (shl S, N) Shift left, remove the first N elements. +struct ShlOp : public SetIntBinOp { + void apply(SetTheory &ST, DagInit *Expr, + RecSet &Set, int64_t N, + RecSet &Elts) { + if (N < 0) + throw "Positive shift required: " + Expr->getAsString(); + if (unsigned(N) < Set.size()) + Elts.insert(Set.begin() + N, Set.end()); + } +}; + +// (trunc S, N) Truncate after the first N elements. +struct TruncOp : public SetIntBinOp { + void apply(SetTheory &ST, DagInit *Expr, + RecSet &Set, int64_t N, + RecSet &Elts) { + if (N < 0) + throw "Positive length required: " + Expr->getAsString(); + if (unsigned(N) > Set.size()) + N = Set.size(); + Elts.insert(Set.begin(), Set.begin() + N); + } +}; + +// Left/right rotation. +struct RotOp : public SetIntBinOp { + const bool Reverse; + + RotOp(bool Rev) : Reverse(Rev) {} + + void apply(SetTheory &ST, DagInit *Expr, + RecSet &Set, int64_t N, + RecSet &Elts) { + if (Reverse) + N = -N; + // N > 0 -> rotate left, N < 0 -> rotate right. + if (Set.empty()) + return; + if (N < 0) + N = Set.size() - (-N % Set.size()); + else + N %= Set.size(); + Elts.insert(Set.begin() + N, Set.end()); + Elts.insert(Set.begin(), Set.begin() + N); + } +}; + +// (decimate S, N) Pick every N'th element of S. +struct DecimateOp : public SetIntBinOp { + void apply(SetTheory &ST, DagInit *Expr, + RecSet &Set, int64_t N, + RecSet &Elts) { + if (N <= 0) + throw "Positive stride required: " + Expr->getAsString(); + for (unsigned I = 0; I < Set.size(); I += N) + Elts.insert(Set[I]); + } +}; + +// (sequence "Format", From, To) Generate a sequence of records by name. +struct SequenceOp : public SetTheory::Operator { + RecordKeeper &Records; + + SequenceOp(RecordKeeper&R) : Records(R) {} + + void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts) { + if (Expr->arg_size() != 3) + throw "Bad args to (sequence \"Format\", From, To): " + + Expr->getAsString(); + std::string Format; + if (StringInit *SI = dynamic_cast(Expr->arg_begin()[0])) + Format = SI->getValue(); + else + throw "Format must be a string: " + Expr->getAsString(); + + int64_t From, To; + if (IntInit *II = dynamic_cast(Expr->arg_begin()[1])) + From = II->getValue(); + else + throw "From must be an integer: " + Expr->getAsString(); + if (IntInit *II = dynamic_cast(Expr->arg_begin()[2])) + To = II->getValue(); + else + throw "From must be an integer: " + Expr->getAsString(); + + int Step = From <= To ? 1 : -1; + for (To += Step; From != To; From += Step) { + std::string Name; + raw_string_ostream OS(Name); + OS << format(Format.c_str(), From); + Record *Rec = Records.getDef(OS.str()); + if (!Rec) + throw "No def named '" + Name + "': " + Expr->getAsString(); + // Try to reevaluate Rec in case it is a set. + if (const RecVec *Result = ST.expand(Rec)) + Elts.insert(Result->begin(), Result->end()); + else + Elts.insert(Rec); + } + } +}; + +// Expand a Def into a set by evaluating one of its fields. +struct FieldExpander : public SetTheory::Expander { + StringRef FieldName; + + FieldExpander(StringRef fn) : FieldName(fn) {} + + void expand(SetTheory &ST, Record *Def, RecSet &Elts) { + ST.evaluate(Def->getValueInit(FieldName), Elts); + } +}; +} // end anonymous namespace + +SetTheory::SetTheory(RecordKeeper *Records) { + addOperator("add", new AddOp); + addOperator("sub", new SubOp); + addOperator("and", new AndOp); + addOperator("shl", new ShlOp); + addOperator("trunc", new TruncOp); + addOperator("rotl", new RotOp(false)); + addOperator("rotr", new RotOp(true)); + addOperator("decimate", new DecimateOp); + if (Records) + addOperator("sequence", new SequenceOp(*Records)); +} + +void SetTheory::addOperator(StringRef Name, Operator *Op) { + Operators[Name] = Op; +} + +void SetTheory::addExpander(StringRef ClassName, Expander *E) { + Expanders[ClassName] = E; +} + +void SetTheory::addFieldExpander(StringRef ClassName, StringRef FieldName) { + addExpander(ClassName, new FieldExpander(FieldName)); +} + +void SetTheory::evaluate(Init *Expr, RecSet &Elts) { + // A def in a list can be a just an element, or it may expand. + if (DefInit *Def = dynamic_cast(Expr)) { + if (const RecVec *Result = expand(Def->getDef())) + return Elts.insert(Result->begin(), Result->end()); + Elts.insert(Def->getDef()); + return; + } + + // Lists simply expand. + if (ListInit *LI = dynamic_cast(Expr)) + return evaluate(LI->begin(), LI->end(), Elts); + + // Anything else must be a DAG. + DagInit *DagExpr = dynamic_cast(Expr); + if (!DagExpr) + throw "Invalid set element: " + Expr->getAsString(); + DefInit *OpInit = dynamic_cast(DagExpr->getOperator()); + if (!OpInit) + throw "Bad set expression: " + Expr->getAsString(); + Operator *Op = Operators.lookup(OpInit->getDef()->getName()); + if (!Op) + throw "Unknown set operator: " + Expr->getAsString(); + Op->apply(*this, DagExpr, Elts); +} + +const RecVec *SetTheory::expand(Record *Set) { + // Check existing entries for Set and return early. + ExpandMap::iterator I = Expansions.find(Set); + if (I != Expansions.end()) + return &I->second; + + // This is the first time we see Set. Find a suitable expander. + try { + const std::vector &SC = Set->getSuperClasses(); + for (unsigned i = 0, e = SC.size(); i != e; ++i) + if (Expander *Exp = Expanders.lookup(SC[i]->getName())) { + // This breaks recursive definitions. + RecVec &EltVec = Expansions[Set]; + RecSet Elts; + Exp->expand(*this, Set, Elts); + EltVec.assign(Elts.begin(), Elts.end()); + return &EltVec; + } + } catch (const std::string &Error) { + throw TGError(Set->getLoc(), Error); + } + + // Set is not expandable. + return 0; +} + Added: llvm/trunk/utils/TableGen/SetTheory.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SetTheory.h?rev=132621&view=auto ============================================================================== --- llvm/trunk/utils/TableGen/SetTheory.h (added) +++ llvm/trunk/utils/TableGen/SetTheory.h Fri Jun 3 23:11:37 2011 @@ -0,0 +1,133 @@ +//===- SetTheory.h - Generate ordered sets from DAG expressions -*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file implements the SetTheory class that computes ordered sets of +// Records from DAG expressions. Operators for standard set operations are +// predefined, and it is possible to add special purpose set operators as well. +// +// The user may define named sets as Records of predefined classes. Set +// expanders can be added to a SetTheory instance to teach it how to find the +// elements of such a named set. +// +// These are the predefined operators. The argument lists can be individual +// elements (defs), other sets (defs of expandable classes), lists, or DAG +// expressions that are evaluated recursively. +// +// - (add S1, S2 ...) Union sets. This is also how sets are created from element +// lists. +// +// - (sub S1, S2, ...) Set difference. Every element in S1 except for the +// elements in S2, ... +// +// - (and S1, S2) Set intersection. Every element in S1 that is also in S2. +// +// - (shl S, N) Shift left. Remove the first N elements from S. +// +// - (trunc S, N) Truncate. The first N elements of S. +// +// - (rotl S, N) Rotate left. Same as (add (shl S, N), (trunc S, N)). +// +// - (rotr S, N) Rotate right. +// +// - (decimate S, N) Decimate S by picking every N'th element, starting with +// the first one. For instance, (decimate S, 2) returns the even elements of +// S. +// +// - (sequence "Format", From, To) Generate a sequence of defs with printf. +// For instance, (sequence "R%u", 0, 3) -> [ R0, R1, R2, R3 ] +// +//===----------------------------------------------------------------------===// + +#ifndef SETTHEORY_H +#define SETTHEORY_H + +#include "llvm/ADT/StringMap.h" +#include "llvm/ADT/SetVector.h" +#include +#include + +namespace llvm { + +class DagInit; +struct Init; +class Record; +class RecordKeeper; + +class SetTheory { +public: + typedef std::vector RecVec; + typedef SmallSetVector RecSet; + + /// Operator - A callback representing a DAG operator. + struct Operator { + /// apply - Apply this operator to Expr's arguments and insert the result + /// in Elts. + virtual void apply(SetTheory&, DagInit *Expr, RecSet &Elts) =0; + }; + + /// Expander - A callback function that can transform a Record representing a + /// set into a fully expanded list of elements. Expanders provide a way for + /// users to define named sets that can be used in DAG expressions. + struct Expander { + virtual void expand(SetTheory&, Record*, RecSet &Elts) =0; + }; + +private: + // Map set defs to their fully expanded contents. This serves as a memoization + // cache and it makes it possible to return const references on queries. + typedef std::map ExpandMap; + ExpandMap Expansions; + + // Known DAG operators by name. + StringMap Operators; + + // Typed expanders by class name. + StringMap Expanders; + +public: + /// Create a SetTheory instance with only the standard operators. + /// A 'sequence' operator will only be added if a RecordKeeper is given. + SetTheory(RecordKeeper *Records = 0); + + /// addExpander - Add an expander for Records with the named super class. + void addExpander(StringRef ClassName, Expander*); + + /// addFieldExpander - Add an expander for ClassName that simply evaluates + /// FieldName in the Record to get the set elements. That is all that is + /// needed for a class like: + /// + /// class Set { + /// dag Elts = d; + /// } + /// + void addFieldExpander(StringRef ClassName, StringRef FieldName); + + /// addOperator - Add a DAG operator. + void addOperator(StringRef Name, Operator*); + + /// evaluate - Evaluate Expr and append the resulting set to Elts. + void evaluate(Init *Expr, RecSet &Elts); + + /// evaluate - Evaluate a sequence of Inits and append to Elts. + template + void evaluate(Iter begin, Iter end, RecSet &Elts) { + while (begin != end) + evaluate(*begin++, Elts); + } + + /// expand - Expand a record into a set of elements if possible. Return a + /// pointer to the expanded elements, or NULL if Set cannot be expanded + /// further. + const RecVec *expand(Record *Set); +}; + +} // end namespace llvm + +#endif + Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=132621&r1=132620&r2=132621&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Fri Jun 3 23:11:37 2011 @@ -37,6 +37,7 @@ #include "RegisterInfoEmitter.h" #include "ARMDecoderEmitter.h" #include "SubtargetEmitter.h" +#include "SetTheory.h" #include "TGParser.h" #include "llvm/ADT/OwningPtr.h" #include "llvm/Support/CommandLine.h" @@ -80,7 +81,8 @@ GenArmNeon, GenArmNeonSema, GenArmNeonTest, - PrintEnums + PrintEnums, + PrintSets }; namespace { @@ -162,6 +164,8 @@ "Generate ARM NEON tests for clang"), clEnumValN(PrintEnums, "print-enums", "Print enum values for a class"), + clEnumValN(PrintSets, "print-sets", + "Print expanded sets for testing DAG exprs"), clEnumValEnd)); cl::opt @@ -374,6 +378,21 @@ Out.os() << "\n"; break; } + case PrintSets: + { + SetTheory Sets(&Records); + Sets.addFieldExpander("Set", "Elements"); + std::vector Recs = Records.getAllDerivedDefinitions("Set"); + for (unsigned i = 0, e = Recs.size(); i != e; ++i) { + Out.os() << Recs[i]->getName() << " = ["; + const std::vector *Elts = Sets.expand(Recs[i]); + assert(Elts && "Couldn't expand Set instance"); + for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei) + Out.os() << ' ' << (*Elts)[ei]->getName(); + Out.os() << " ]\n"; + } + break; + } default: assert(1 && "Invalid Action"); return 1; From scshunt at csclub.uwaterloo.ca Sat Jun 4 00:03:29 2011 From: scshunt at csclub.uwaterloo.ca (Sean Hunt) Date: Fri, 03 Jun 2011 22:03:29 -0700 Subject: [llvm-commits] [llvm] r132621 - in /llvm/trunk: test/TableGen/SetTheory.td utils/TableGen/CMakeLists.txt utils/TableGen/SetTheory.cpp utils/TableGen/SetTheory.h utils/TableGen/TableGen.cpp In-Reply-To: <20110604041137.924822A6C12C@llvm.org> References: <20110604041137.924822A6C12C@llvm.org> Message-ID: <4DE9BCA1.2020005@csclub.uwaterloo.ca> On 06/03/11 21:11, Jakob Stoklund Olesen wrote: > + /// Operator - A callback representing a DAG operator. > + struct Operator { > + /// apply - Apply this operator to Expr's arguments and insert the result > + /// in Elts. > + virtual void apply(SetTheory&, DagInit *Expr, RecSet&Elts) =0; > + }; > + > + /// Expander - A callback function that can transform a Record representing a > + /// set into a fully expanded list of elements. Expanders provide a way for > + /// users to define named sets that can be used in DAG expressions. > + struct Expander { > + virtual void expand(SetTheory&, Record*, RecSet&Elts) =0; > + }; These are triggering -Wno-virtual-destructor warnings. Sean From nicholas at mxc.ca Sat Jun 4 00:06:10 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Fri, 03 Jun 2011 22:06:10 -0700 Subject: [llvm-commits] [llvm] r132621 - in /llvm/trunk: test/TableGen/SetTheory.td utils/TableGen/CMakeLists.txt utils/TableGen/SetTheory.cpp utils/TableGen/SetTheory.h utils/TableGen/TableGen.cpp In-Reply-To: <4DE9BCA1.2020005@csclub.uwaterloo.ca> References: <20110604041137.924822A6C12C@llvm.org> <4DE9BCA1.2020005@csclub.uwaterloo.ca> Message-ID: <4DE9BD42.7000909@mxc.ca> Sean Hunt wrote: > On 06/03/11 21:11, Jakob Stoklund Olesen wrote: >> + /// Operator - A callback representing a DAG operator. >> + struct Operator { >> + /// apply - Apply this operator to Expr's arguments and insert the result >> + /// in Elts. >> + virtual void apply(SetTheory&, DagInit *Expr, RecSet&Elts) =0; >> + }; >> + >> + /// Expander - A callback function that can transform a Record representing a >> + /// set into a fully expanded list of elements. Expanders provide a way for >> + /// users to define named sets that can be used in DAG expressions. >> + struct Expander { >> + virtual void expand(SetTheory&, Record*, RecSet&Elts) =0; >> + }; > > These are triggering -Wno-virtual-destructor warnings. Furthermore, I'm seeing these: SetTheory.cpp:69:8: warning: ?virtual void::SetIntBinOp::apply(llvm::SetTheory&, llvm::DagInit*, ::RecSet&)? was hidden SetTheory.cpp:83:8: warning: by ?virtual void::ShlOp::apply(llvm::SetTheory&, llvm::DagInit*, ::RecSet&, int64_t, ::RecSet&)? SetTheory.cpp:69:8: warning: ?virtual void::SetIntBinOp::apply(llvm::SetTheory&, llvm::DagInit*, ::RecSet&)? was hidden SetTheory.cpp:95:8: warning: by ?virtual void::TruncOp::apply(llvm::SetTheory&, llvm::DagInit*, ::RecSet&, int64_t, ::RecSet&)? SetTheory.cpp:69:8: warning: ?virtual void::SetIntBinOp::apply(llvm::SetTheory&, llvm::DagInit*, ::RecSet&)? was hidden SetTheory.cpp:112:8: warning: by ?virtual void::RotOp::apply(llvm::SetTheory&, llvm::DagInit*, ::RecSet&, int64_t, ::RecSet&)? SetTheory.cpp:69:8: warning: ?virtual void::SetIntBinOp::apply(llvm::SetTheory&, llvm::DagInit*, ::RecSet&)? was hidden SetTheory.cpp:131:8: warning: by ?virtual void::DecimateOp::apply(llvm::SetTheory&, llvm::DagInit*, ::RecSet&, int64_t, ::RecSet&)? > > Sean > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From stoklund at 2pi.dk Sat Jun 4 00:09:37 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 04 Jun 2011 05:09:37 -0000 Subject: [llvm-commits] [llvm] r132624 - in /llvm/trunk/utils/TableGen: SetTheory.cpp SetTheory.h Message-ID: <20110604050937.2419D2A6C12C@llvm.org> Author: stoklund Date: Sat Jun 4 00:09:36 2011 New Revision: 132624 URL: http://llvm.org/viewvc/llvm-project?rev=132624&view=rev Log: Silence compiler warnings. Modified: llvm/trunk/utils/TableGen/SetTheory.cpp llvm/trunk/utils/TableGen/SetTheory.h Modified: llvm/trunk/utils/TableGen/SetTheory.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SetTheory.cpp?rev=132624&r1=132623&r2=132624&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SetTheory.cpp (original) +++ llvm/trunk/utils/TableGen/SetTheory.cpp Sat Jun 4 00:09:36 2011 @@ -62,7 +62,7 @@ // SetIntBinOp - Abstract base class for (Op S, N) operators. struct SetIntBinOp : public SetTheory::Operator { - virtual void apply(SetTheory &ST, DagInit *Expr, + virtual void apply2(SetTheory &ST, DagInit *Expr, RecSet &Set, int64_t N, RecSet &Elts) =0; @@ -74,13 +74,13 @@ IntInit *II = dynamic_cast(Expr->arg_begin()[1]); if (!II) throw "Second argument must be an integer: " + Expr->getAsString(); - apply(ST, Expr, Set, II->getValue(), Elts); + apply2(ST, Expr, Set, II->getValue(), Elts); } }; // (shl S, N) Shift left, remove the first N elements. struct ShlOp : public SetIntBinOp { - void apply(SetTheory &ST, DagInit *Expr, + void apply2(SetTheory &ST, DagInit *Expr, RecSet &Set, int64_t N, RecSet &Elts) { if (N < 0) @@ -92,7 +92,7 @@ // (trunc S, N) Truncate after the first N elements. struct TruncOp : public SetIntBinOp { - void apply(SetTheory &ST, DagInit *Expr, + void apply2(SetTheory &ST, DagInit *Expr, RecSet &Set, int64_t N, RecSet &Elts) { if (N < 0) @@ -109,7 +109,7 @@ RotOp(bool Rev) : Reverse(Rev) {} - void apply(SetTheory &ST, DagInit *Expr, + void apply2(SetTheory &ST, DagInit *Expr, RecSet &Set, int64_t N, RecSet &Elts) { if (Reverse) @@ -128,7 +128,7 @@ // (decimate S, N) Pick every N'th element of S. struct DecimateOp : public SetIntBinOp { - void apply(SetTheory &ST, DagInit *Expr, + void apply2(SetTheory &ST, DagInit *Expr, RecSet &Set, int64_t N, RecSet &Elts) { if (N <= 0) Modified: llvm/trunk/utils/TableGen/SetTheory.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SetTheory.h?rev=132624&r1=132623&r2=132624&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SetTheory.h (original) +++ llvm/trunk/utils/TableGen/SetTheory.h Sat Jun 4 00:09:36 2011 @@ -66,6 +66,8 @@ /// Operator - A callback representing a DAG operator. struct Operator { + virtual ~Operator() {} + /// apply - Apply this operator to Expr's arguments and insert the result /// in Elts. virtual void apply(SetTheory&, DagInit *Expr, RecSet &Elts) =0; @@ -75,6 +77,8 @@ /// set into a fully expanded list of elements. Expanders provide a way for /// users to define named sets that can be used in DAG expressions. struct Expander { + virtual ~Expander() {} + virtual void expand(SetTheory&, Record*, RecSet &Elts) =0; }; From stoklund at 2pi.dk Sat Jun 4 00:16:38 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Fri, 3 Jun 2011 22:16:38 -0700 Subject: [llvm-commits] [llvm] r132621 - in /llvm/trunk: test/TableGen/SetTheory.td utils/TableGen/CMakeLists.txt utils/TableGen/SetTheory.cpp utils/TableGen/SetTheory.h utils/TableGen/TableGen.cpp In-Reply-To: <4DE9BD42.7000909@mxc.ca> References: <20110604041137.924822A6C12C@llvm.org> <4DE9BCA1.2020005@csclub.uwaterloo.ca> <4DE9BD42.7000909@mxc.ca> Message-ID: <15467718-5FF2-4847-BE0E-865A155B9587@2pi.dk> On Jun 3, 2011, at 10:06 PM, Nick Lewycky wrote: > Sean Hunt wrote: >> >> These are triggering -Wno-virtual-destructor warnings. > > Furthermore, I'm seeing these: > > SetTheory.cpp:69:8: warning: ?virtual > void::SetIntBinOp::apply(llvm::SetTheory&, llvm::DagInit*, > ::RecSet&)? was hidden Both should be fixed in r132624, thanks! /jakob From gohman at apple.com Sat Jun 4 00:11:22 2011 From: gohman at apple.com (Dan Gohman) Date: Sat, 04 Jun 2011 05:11:22 -0000 Subject: [llvm-commits] [llvm] r132625 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll Message-ID: <20110604051122.650922A6C12C@llvm.org> Author: djg Date: Sat Jun 4 00:11:22 2011 New Revision: 132625 URL: http://llvm.org/viewvc/llvm-project?rev=132625&view=rev Log: Revert r131781 again. Apparently there is more going on here. Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=132625&r1=132624&r2=132625&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sat Jun 4 00:11:22 2011 @@ -944,17 +944,7 @@ return NoAlias; } - // Statically, we can see that the base objects are the same, but the - // pointers have dynamic offsets which we can't resolve. And none of our - // little tricks above worked. - // - // TODO: Returning PartialAlias instead of MayAlias is a mild hack; the - // practical effect of this is protecting TBAA in the case of dynamic - // indices into arrays of unions. An alternative way to solve this would - // be to have clang emit extra metadata for unions and/or union accesses. - // A union-specific solution wouldn't handle the problem for malloc'd - // memory however. - return PartialAlias; + return MayAlias; } static AliasAnalysis::AliasResult Modified: llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll?rev=132625&r1=132624&r2=132625&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll (original) +++ llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll Sat Jun 4 00:11:22 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {1 partial alias} +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {1 may alias} ; PR7959 target datalayout = "e-p:32:32:32" From rdivacky at freebsd.org Sat Jun 4 01:15:42 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Sat, 04 Jun 2011 06:15:42 -0000 Subject: [llvm-commits] [llvm] r132627 - /llvm/trunk/autoconf/config.guess Message-ID: <20110604061542.717AA2A6C12C@llvm.org> Author: rdivacky Date: Sat Jun 4 01:15:42 2011 New Revision: 132627 URL: http://llvm.org/viewvc/llvm-project?rev=132627&view=rev Log: Use processor name in the target triple. This fixes PowerPC64 to generate 64bit code for example. Modified: llvm/trunk/autoconf/config.guess Modified: llvm/trunk/autoconf/config.guess URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/config.guess?rev=132627&r1=132626&r2=132627&view=diff ============================================================================== --- llvm/trunk/autoconf/config.guess (original) +++ llvm/trunk/autoconf/config.guess Sat Jun 4 01:15:42 2011 @@ -789,13 +789,12 @@ echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} exit ;; *:FreeBSD:*:*) + UNAME_PROCESSOR=`/usr/bin/uname -p` case ${UNAME_MACHINE} in - pc98) - echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; amd64) echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; *) - echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; + echo ${UNAME_PROCESSOR}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; esac exit ;; i*:CYGWIN*:*) From gohman at apple.com Sat Jun 4 01:21:23 2011 From: gohman at apple.com (Dan Gohman) Date: Sat, 04 Jun 2011 06:21:23 -0000 Subject: [llvm-commits] [llvm] r132628 - /llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll Message-ID: <20110604062123.E6F7B2A6C12C@llvm.org> Author: djg Date: Sat Jun 4 01:21:23 2011 New Revision: 132628 URL: http://llvm.org/viewvc/llvm-project?rev=132628&view=rev Log: Remove this test, which should have been reverted along with r131781. Removed: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll Removed: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll?rev=132627&view=auto ============================================================================== --- llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll (original) +++ llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll (removed) @@ -1,131 +0,0 @@ -; RUN: opt -tbaa -basicaa -gvn -S < %s | FileCheck %s -; PR9971 - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" - -%struct.X = type { i32, float } -%union.vector_t = type { [2 x i64] } - -; Don't delete the load after the loop, because it loads values stored -; inside the loop. - -; CHECK: define void @vrlh( - -; CHECK: for.end: -; CHECK: %arrayidx31 = getelementptr inbounds %union.vector_t* %t, i64 0, i32 0, i64 1 -; CHECK: %tmp32 = load i64* %arrayidx31, align 8, !tbaa !3 - -define void @vrlh(%union.vector_t* %va, %union.vector_t* %vb, %union.vector_t* %vd) nounwind { -entry: - %t = alloca %union.vector_t, align 8 - br label %for.body - -for.body: ; preds = %entry, %for.body - %i.01 = phi i32 [ 0, %entry ], [ %inc, %for.body ] - %sub = sub nsw i32 7, %i.01 - %idxprom = sext i32 %sub to i64 - %half = bitcast %union.vector_t* %vb to [8 x i16]* - %arrayidx = getelementptr inbounds [8 x i16]* %half, i64 0, i64 %idxprom - %tmp4 = load i16* %arrayidx, align 2, !tbaa !0 - %conv = zext i16 %tmp4 to i32 - %and = and i32 %conv, 15 - %sub6 = sub nsw i32 7, %i.01 - %idxprom7 = sext i32 %sub6 to i64 - %half9 = bitcast %union.vector_t* %va to [8 x i16]* - %arrayidx10 = getelementptr inbounds [8 x i16]* %half9, i64 0, i64 %idxprom7 - %tmp11 = load i16* %arrayidx10, align 2, !tbaa !0 - %conv12 = zext i16 %tmp11 to i32 - %shl = shl i32 %conv12, %and - %sub15 = sub nsw i32 7, %i.01 - %idxprom16 = sext i32 %sub15 to i64 - %half18 = bitcast %union.vector_t* %va to [8 x i16]* - %arrayidx19 = getelementptr inbounds [8 x i16]* %half18, i64 0, i64 %idxprom16 - %tmp20 = load i16* %arrayidx19, align 2, !tbaa !0 - %conv21 = zext i16 %tmp20 to i32 - %sub23 = sub nsw i32 16, %and - %shr = lshr i32 %conv21, %sub23 - %or = or i32 %shl, %shr - %conv24 = trunc i32 %or to i16 - %sub26 = sub nsw i32 7, %i.01 - %idxprom27 = sext i32 %sub26 to i64 - %half28 = bitcast %union.vector_t* %t to [8 x i16]* - %arrayidx29 = getelementptr inbounds [8 x i16]* %half28, i64 0, i64 %idxprom27 - store i16 %conv24, i16* %arrayidx29, align 2, !tbaa !0 - %inc = add nsw i32 %i.01, 1 - %cmp = icmp slt i32 %inc, 8 - br i1 %cmp, label %for.body, label %for.end - -for.end: ; preds = %for.body - %arrayidx31 = getelementptr inbounds %union.vector_t* %t, i64 0, i32 0, i64 1 - %tmp32 = load i64* %arrayidx31, align 8, !tbaa !3 - %arrayidx35 = getelementptr inbounds %union.vector_t* %vd, i64 0, i32 0, i64 1 - store i64 %tmp32, i64* %arrayidx35, align 8, !tbaa !3 - %arrayidx37 = getelementptr inbounds %union.vector_t* %t, i64 0, i32 0, i64 0 - %tmp38 = load i64* %arrayidx37, align 8, !tbaa !3 - %arrayidx41 = getelementptr inbounds %union.vector_t* %vd, i64 0, i32 0, i64 0 - store i64 %tmp38, i64* %arrayidx41, align 8, !tbaa !3 - ret void -} - -; Do delete the load after the loop. - -; CHECK: define i32 @test0( - -; CHECK: ret i32 0 - -define i32 @test0(%struct.X* %a) nounwind { -entry: - %i = getelementptr inbounds %struct.X* %a, i64 0, i32 0 - store i32 0, i32* %i, align 4, !tbaa !4 - br label %for.body - -for.body: ; preds = %entry, %for.body - %i2.01 = phi i64 [ 0, %entry ], [ %inc, %for.body ] - %f = getelementptr inbounds %struct.X* %a, i64 %i2.01, i32 1 - %tmp6 = load float* %f, align 4, !tbaa !5 - %mul = fmul float %tmp6, 0x40019999A0000000 - store float %mul, float* %f, align 4, !tbaa !5 - %inc = add nsw i64 %i2.01, 1 - %cmp = icmp slt i64 %inc, 10000 - br i1 %cmp, label %for.body, label %for.end - -for.end: ; preds = %for.body - %i9 = getelementptr inbounds %struct.X* %a, i64 0, i32 0 - %tmp10 = load i32* %i9, align 4, !tbaa !4 - ret i32 %tmp10 -} - -; Do delete the load after the loop. - -; CHECK: define float @test1( - -; CHECK: ret float 0x3FD3333340000000 - -define float @test1(%struct.X* %a) nounwind { -entry: - %f = getelementptr inbounds %struct.X* %a, i64 0, i32 1 - store float 0x3FD3333340000000, float* %f, align 4, !tbaa !5 - br label %for.body - -for.body: ; preds = %entry, %for.body - %i.01 = phi i64 [ 0, %entry ], [ %inc, %for.body ] - %i5 = getelementptr inbounds %struct.X* %a, i64 %i.01, i32 0 - %tmp6 = load i32* %i5, align 4, !tbaa !4 - %mul = mul nsw i32 %tmp6, 3 - store i32 %mul, i32* %i5, align 4, !tbaa !4 - %inc = add nsw i64 %i.01, 1 - %cmp = icmp slt i64 %inc, 10000 - br i1 %cmp, label %for.body, label %for.end - -for.end: ; preds = %for.body - %f9 = getelementptr inbounds %struct.X* %a, i64 0, i32 1 - %tmp10 = load float* %f9, align 4, !tbaa !5 - ret float %tmp10 -} - -!0 = metadata !{metadata !"short", metadata !1} -!1 = metadata !{metadata !"omnipotent char", metadata !2} -!2 = metadata !{metadata !"Simple C/C++ TBAA", null} -!3 = metadata !{metadata !"long long", metadata !1} -!4 = metadata !{metadata !"int", metadata !1} -!5 = metadata !{metadata !"float", metadata !1} From gohman at apple.com Sat Jun 4 01:48:50 2011 From: gohman at apple.com (Dan Gohman) Date: Sat, 04 Jun 2011 06:48:50 -0000 Subject: [llvm-commits] [llvm] r132631 - in /llvm/trunk: lib/Analysis/MemoryDependenceAnalysis.cpp test/Transforms/GVN/rle.ll Message-ID: <20110604064850.47DCF2A6C12C@llvm.org> Author: djg Date: Sat Jun 4 01:48:50 2011 New Revision: 132631 URL: http://llvm.org/viewvc/llvm-project?rev=132631&view=rev Log: Disable the main feature of 130180, the elimination of loads that are redundant with partially-aliasing loads. When computing what portion of a clobbering load value is needed, it doesn't consider phi-translation which may have occurred between the clobbing load and the redundant load. Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp llvm/trunk/test/Transforms/GVN/rle.ll Modified: llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp?rev=132631&r1=132630&r2=132631&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/MemoryDependenceAnalysis.cpp Sat Jun 4 01:48:50 2011 @@ -374,10 +374,16 @@ if (R == AliasAnalysis::MustAlias) return MemDepResult::getDef(Inst); +#if 0 // FIXME: Temporarily disabled. GVN is cleverly rewriting loads + // in terms of clobbering loads, but since it does this by looking + // at the clobbering load directly, it doesn't know about any + // phi translation that may have happened along the way. + // If we have a partial alias, then return this as a clobber for the // client to handle. if (R == AliasAnalysis::PartialAlias) return MemDepResult::getClobber(Inst); +#endif // Random may-alias loads don't depend on each other without a // dependence. Modified: llvm/trunk/test/Transforms/GVN/rle.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/rle.ll?rev=132631&r1=132630&r2=132631&view=diff ============================================================================== --- llvm/trunk/test/Transforms/GVN/rle.ll (original) +++ llvm/trunk/test/Transforms/GVN/rle.ll Sat Jun 4 01:48:50 2011 @@ -562,14 +562,14 @@ %add = add nsw i32 %tmp2, %conv ret i32 %add -; CHECK: @load_load_partial_alias -; CHECK: load i32* -; CHECK-NOT: load -; CHECK: lshr i32 {{.*}}, 8 -; CHECK-NOT: load -; CHECK: trunc i32 {{.*}} to i8 -; CHECK-NOT: load -; CHECK: ret i32 +; TEMPORARILYDISABLED: @load_load_partial_alias +; TEMPORARILYDISABLED: load i32* +; TEMPORARILYDISABLED-NOT: load +; TEMPORARILYDISABLED: lshr i32 {{.*}}, 8 +; TEMPORARILYDISABLED-NOT: load +; TEMPORARILYDISABLED: trunc i32 {{.*}} to i8 +; TEMPORARILYDISABLED-NOT: load +; TEMPORARILYDISABLED: ret i32 } @@ -589,10 +589,10 @@ if.end: ret i32 52 -; CHECK: @load_load_partial_alias_cross_block -; CHECK: land.lhs.true: -; CHECK-NOT: load i8 -; CHECK: ret i32 %conv6 +; TEMPORARILY_DISABLED: @load_load_partial_alias_cross_block +; TEMPORARILY_DISABLED: land.lhs.true: +; TEMPORARILY_DISABLED-NOT: load i8 +; TEMPORARILY_DISABLED: ret i32 %conv6 } From gohman at apple.com Sat Jun 4 01:50:19 2011 From: gohman at apple.com (Dan Gohman) Date: Sat, 04 Jun 2011 06:50:19 -0000 Subject: [llvm-commits] [llvm] r132632 - in /llvm/trunk: lib/Analysis/BasicAliasAnalysis.cpp test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll Message-ID: <20110604065019.171A12A6C12C@llvm.org> Author: djg Date: Sat Jun 4 01:50:18 2011 New Revision: 132632 URL: http://llvm.org/viewvc/llvm-project?rev=132632&view=rev Log: Reapply r131781, now that the GVN bug with partially-aliasing loads is disabled. Added: llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll - copied unchanged from r132627, llvm/trunk/test/Analysis/TypeBasedAliasAnalysis/dynamic-indices.ll Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll Modified: llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp?rev=132632&r1=132631&r2=132632&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp (original) +++ llvm/trunk/lib/Analysis/BasicAliasAnalysis.cpp Sat Jun 4 01:50:18 2011 @@ -944,7 +944,17 @@ return NoAlias; } - return MayAlias; + // Statically, we can see that the base objects are the same, but the + // pointers have dynamic offsets which we can't resolve. And none of our + // little tricks above worked. + // + // TODO: Returning PartialAlias instead of MayAlias is a mild hack; the + // practical effect of this is protecting TBAA in the case of dynamic + // indices into arrays of unions. An alternative way to solve this would + // be to have clang emit extra metadata for unions and/or union accesses. + // A union-specific solution wouldn't handle the problem for malloc'd + // memory however. + return PartialAlias; } static AliasAnalysis::AliasResult Modified: llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll?rev=132632&r1=132631&r2=132632&view=diff ============================================================================== --- llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll (original) +++ llvm/trunk/test/Analysis/BasicAA/2010-09-15-GEP-SignedArithmetic.ll Sat Jun 4 01:50:18 2011 @@ -1,4 +1,4 @@ -; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {1 may alias} +; RUN: opt < %s -basicaa -aa-eval -print-all-alias-modref-info -disable-output |& grep {1 partial alias} ; PR7959 target datalayout = "e-p:32:32:32" From gohman at apple.com Sat Jun 4 02:05:05 2011 From: gohman at apple.com (Dan Gohman) Date: Sat, 04 Jun 2011 07:05:05 -0000 Subject: [llvm-commits] [llvm] r132633 - /llvm/trunk/test/Transforms/GVN/phi-translate-partial-alias.ll Message-ID: <20110604070505.B17C92A6C12C@llvm.org> Author: djg Date: Sat Jun 4 02:05:05 2011 New Revision: 132633 URL: http://llvm.org/viewvc/llvm-project?rev=132633&view=rev Log: Add a testcase to demonstrate the problem where phi translation is ignored for clobbering partial-alias loads. Added: llvm/trunk/test/Transforms/GVN/phi-translate-partial-alias.ll Added: llvm/trunk/test/Transforms/GVN/phi-translate-partial-alias.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/phi-translate-partial-alias.ll?rev=132633&view=auto ============================================================================== --- llvm/trunk/test/Transforms/GVN/phi-translate-partial-alias.ll (added) +++ llvm/trunk/test/Transforms/GVN/phi-translate-partial-alias.ll Sat Jun 4 02:05:05 2011 @@ -0,0 +1,27 @@ +; RUN: opt -basicaa -gvn -S < %s | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64" + +; GVN shouldn't PRE the load around the loop backedge because it's +; not actually redundant around the loop backedge, despite appearances +; if phi-translation is ignored. + +; CHECK: define void @test0(i8* %begin) +; CHECK: loop: +; CHECK: %l0 = load i8* %phi +; CHECK: call void @bar(i8 %l0) +; CHECK: %l1 = load i8* %phi +define void @test0(i8* %begin) { +entry: + br label %loop + +loop: + %phi = phi i8* [ %begin, %entry ], [ %next, %loop ] + %l0 = load i8* %phi + call void @bar(i8 %l0) + %l1 = load i8* %phi + %next = getelementptr inbounds i8* %phi, i8 %l1 + br label %loop +} + +declare void @bar(i8) From nicholas at mxc.ca Sat Jun 4 02:34:01 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Sat, 04 Jun 2011 00:34:01 -0700 Subject: [llvm-commits] patch: add support for GOTTPOFF in 32-bit mode Message-ID: <4DE9DFE9.1070400@mxc.ca> The attached patch maps VK_GOTTPOFF to R_386_TLS_IE_32. I'm not sure how right that is, but it does the same thing as GNU as on the testcase I have. Nick From nicholas at mxc.ca Sat Jun 4 02:36:58 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Sat, 04 Jun 2011 00:36:58 -0700 Subject: [llvm-commits] patch: add support for GOTTPOFF in 32-bit mode In-Reply-To: <4DE9DFE9.1070400@mxc.ca> References: <4DE9DFE9.1070400@mxc.ca> Message-ID: <4DE9E09A.6090801@mxc.ca> Once again, with patch. Nick Lewycky wrote: > The attached patch maps VK_GOTTPOFF to R_386_TLS_IE_32. I'm not sure how > right that is, but it does the same thing as GNU as on the testcase I have. > > Nick > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > -------------- next part -------------- A non-text attachment was scrubbed... Name: mc-i386-gottpoff.patch Type: text/x-patch Size: 1347 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110604/212b897f/attachment.bin From stoklund at 2pi.dk Sat Jun 4 02:49:55 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 04 Jun 2011 07:49:55 -0000 Subject: [llvm-commits] [llvm] r132636 - in /llvm/trunk/utils/TableGen: SetTheory.cpp SetTheory.h TableGen.cpp Message-ID: <20110604074957.913C82A6C12D@llvm.org> Author: stoklund Date: Sat Jun 4 02:49:55 2011 New Revision: 132636 URL: http://llvm.org/viewvc/llvm-project?rev=132636&view=rev Log: Drop a RecordKeeper reference that wasn't necessary. Modified: llvm/trunk/utils/TableGen/SetTheory.cpp llvm/trunk/utils/TableGen/SetTheory.h llvm/trunk/utils/TableGen/TableGen.cpp Modified: llvm/trunk/utils/TableGen/SetTheory.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SetTheory.cpp?rev=132636&r1=132635&r2=132636&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SetTheory.cpp (original) +++ llvm/trunk/utils/TableGen/SetTheory.cpp Sat Jun 4 02:49:55 2011 @@ -140,10 +140,6 @@ // (sequence "Format", From, To) Generate a sequence of records by name. struct SequenceOp : public SetTheory::Operator { - RecordKeeper &Records; - - SequenceOp(RecordKeeper&R) : Records(R) {} - void apply(SetTheory &ST, DagInit *Expr, RecSet &Elts) { if (Expr->arg_size() != 3) throw "Bad args to (sequence \"Format\", From, To): " + @@ -164,6 +160,9 @@ else throw "From must be an integer: " + Expr->getAsString(); + RecordKeeper &Records = + dynamic_cast(*Expr->getOperator()).getDef()->getRecords(); + int Step = From <= To ? 1 : -1; for (To += Step; From != To; From += Step) { std::string Name; @@ -193,7 +192,7 @@ }; } // end anonymous namespace -SetTheory::SetTheory(RecordKeeper *Records) { +SetTheory::SetTheory() { addOperator("add", new AddOp); addOperator("sub", new SubOp); addOperator("and", new AndOp); @@ -202,8 +201,7 @@ addOperator("rotl", new RotOp(false)); addOperator("rotr", new RotOp(true)); addOperator("decimate", new DecimateOp); - if (Records) - addOperator("sequence", new SequenceOp(*Records)); + addOperator("sequence", new SequenceOp); } void SetTheory::addOperator(StringRef Name, Operator *Op) { Modified: llvm/trunk/utils/TableGen/SetTheory.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SetTheory.h?rev=132636&r1=132635&r2=132636&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SetTheory.h (original) +++ llvm/trunk/utils/TableGen/SetTheory.h Sat Jun 4 02:49:55 2011 @@ -96,8 +96,7 @@ public: /// Create a SetTheory instance with only the standard operators. - /// A 'sequence' operator will only be added if a RecordKeeper is given. - SetTheory(RecordKeeper *Records = 0); + SetTheory(); /// addExpander - Add an expander for Records with the named super class. void addExpander(StringRef ClassName, Expander*); Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=132636&r1=132635&r2=132636&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Sat Jun 4 02:49:55 2011 @@ -380,7 +380,7 @@ } case PrintSets: { - SetTheory Sets(&Records); + SetTheory Sets; Sets.addFieldExpander("Set", "Elements"); std::vector Recs = Records.getAllDerivedDefinitions("Set"); for (unsigned i = 0, e = Recs.size(); i != e; ++i) { From fvbommel at gmail.com Sat Jun 4 02:56:22 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Sat, 4 Jun 2011 09:56:22 +0200 Subject: [llvm-commits] [llvm] r132613 - in /llvm/trunk: include/llvm/Analysis/BranchProbabilityInfo.h include/llvm/InitializePasses.h lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp lib/Analysis/CMakeLists.txt In-Reply-To: <20110604011630.EB7B52A6C12C@llvm.org> References: <20110604011630.EB7B52A6C12C@llvm.org> Message-ID: On 4 June 2011 03:16, Andrew Trick wrote: > + ?// Default weight value. Used when we don't have information about the edge. > + ?static const unsigned int DEFAULT_WEIGHT = 16; > + ?DenseMap Weights; > + ?unsigned getMaxWeightFor(BasicBlock *BB) const { > + ? ?return UINT_MAX / BB->getTerminator()->getNumSuccessors(); > + ?} (And many more instances...) Given that your design doc mailed to LLVMDev[1] talks about > Representation: Map of 32-bit unsigned int "edge weight" per CFG edge and > One of the goals of the branch profile framework is to keep the final output of compilation independent of floating point imprecision. In other words, we want LLVM to be a deterministic cross-compiler. Shouldn't you use 'uint32_t' instead of 'unsigned (int)' throughout (and UINT32_MAX instead of UINT_MAX, etc.)? As it is now, the edge weights might be different if LLVM is compiled on a machine where an unsigned int is e.g. 16 or 64 bits because they are dependent on the precision of unsigned integers instead of floating point numbers. This doesn't seem to fit with the goal of keeping the output the same over all platforms. [1]: http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-June/040491.html From stoklund at 2pi.dk Sat Jun 4 03:19:41 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 4 Jun 2011 01:19:41 -0700 Subject: [llvm-commits] [llvm] r132613 - in /llvm/trunk: include/llvm/Analysis/BranchProbabilityInfo.h include/llvm/InitializePasses.h lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp lib/Analysis/CMakeLists.txt In-Reply-To: References: <20110604011630.EB7B52A6C12C@llvm.org> Message-ID: <8A8469FC-8F84-4974-B227-3944E47B2301@2pi.dk> On Jun 4, 2011, at 12:56 AM, Frits van Bommel wrote: > Shouldn't you use 'uint32_t' instead of 'unsigned (int)' throughout > (and UINT32_MAX instead of UINT_MAX, etc.)? LLVM assumes that unsigned is 32 bits in *many* places. It won't work with any other int size. /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110604/01ec1b6d/attachment.html From fvbommel at gmail.com Sat Jun 4 03:50:04 2011 From: fvbommel at gmail.com (Frits van Bommel) Date: Sat, 4 Jun 2011 10:50:04 +0200 Subject: [llvm-commits] [llvm] r132613 - in /llvm/trunk: include/llvm/Analysis/BranchProbabilityInfo.h include/llvm/InitializePasses.h lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp lib/Analysis/CMakeLists.txt In-Reply-To: <8A8469FC-8F84-4974-B227-3944E47B2301@2pi.dk> References: <20110604011630.EB7B52A6C12C@llvm.org> <8A8469FC-8F84-4974-B227-3944E47B2301@2pi.dk> Message-ID: On 4 June 2011 10:19, Jakob Stoklund Olesen wrote: > On Jun 4, 2011, at 12:56 AM, Frits van Bommel wrote: >> Shouldn't you use 'uint32_t' instead of 'unsigned (int)' throughout >> (and UINT32_MAX instead of UINT_MAX, etc.)? > > LLVM assumes that unsigned is 32 bits in *many* places. It won't work with > any other int size. Do they assume it's 32 bits, or that it's *at least* 32 bits? Note that this code essentially assumes it's *exactly* 32 bits because its results depend on the exact value of UINT_MAX. But even if what you say is true, I don't consider that to be a good excuse to contribute to the problem. And many places in LLVM use (u)int32_t, too. If nothing else, uint32_t is more self-documenting. From isanbard at gmail.com Sat Jun 4 04:42:04 2011 From: isanbard at gmail.com (Bill Wendling) Date: Sat, 04 Jun 2011 09:42:04 -0000 Subject: [llvm-commits] [llvm] r132638 - in /llvm/trunk: lib/Transforms/Utils/SimplifyCFG.cpp test/Transforms/SimplifyCFG/indirectbr.ll Message-ID: <20110604094204.814362A6C12C@llvm.org> Author: void Date: Sat Jun 4 04:42:04 2011 New Revision: 132638 URL: http://llvm.org/viewvc/llvm-project?rev=132638&view=rev Log: If the block that we're threading through is jumped to by an indirect branch, then we don't want to set the destination in the indirect branch to the destination. This is because the indirect branch needs its destinations to have had their block addresses taken. This isn't so of the new critical edge that's split during this process. If it turns out that the destination block has only one predecessor, and that being a BB with an indirect branch, then it won't be marked as 'used' and may be removed. PR10072 Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp llvm/trunk/test/Transforms/SimplifyCFG/indirectbr.ll Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=132638&r1=132637&r2=132638&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Sat Jun 4 04:42:04 2011 @@ -1171,6 +1171,8 @@ BasicBlock *RealDest = BI->getSuccessor(!CB->getZExtValue()); if (RealDest == BB) continue; // Skip self loops. + // Skip if the predecessor's terminator is an indirect branch. + if (isa(PredBB->getTerminator())) continue; // The dest block might have PHI nodes, other predecessors and other // difficult cases. Instead of being smart about this, just insert a new @@ -1226,7 +1228,7 @@ BB->removePredecessor(PredBB); PredBBTI->setSuccessor(i, EdgeBB); } - + // Recurse, simplifying any other constants. return FoldCondBranchOnPHI(BI, TD) | true; } Modified: llvm/trunk/test/Transforms/SimplifyCFG/indirectbr.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/indirectbr.ll?rev=132638&r1=132637&r2=132638&view=diff ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/indirectbr.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/indirectbr.ll Sat Jun 4 04:42:04 2011 @@ -180,3 +180,72 @@ ; before SimplifyCFG even looks at the indirectbr. indirectbr i8* %anchor, [label %L1, label %L2] } + +; PR10072 + + at xblkx.bbs = internal unnamed_addr constant [9 x i8*] [i8* blockaddress(@indbrtest7, %xblkx.begin), i8* blockaddress(@indbrtest7, %xblkx.begin3), i8* blockaddress(@indbrtest7, %xblkx.begin4), i8* blockaddress(@indbrtest7, %xblkx.begin5), i8* blockaddress(@indbrtest7, %xblkx.begin6), i8* blockaddress(@indbrtest7, %xblkx.begin7), i8* blockaddress(@indbrtest7, %xblkx.begin8), i8* blockaddress(@indbrtest7, %xblkx.begin9), i8* blockaddress(@indbrtest7, %xblkx.end)] + +define void @indbrtest7() { +escape-string.top: + %xval202x = call i32 @xfunc5x() + br label %xlab5x + +xlab8x: ; preds = %xlab5x + %xvaluex = call i32 @xselectorx() + %xblkx.x = getelementptr [9 x i8*]* @xblkx.bbs, i32 0, i32 %xvaluex + %xblkx.load = load i8** %xblkx.x + indirectbr i8* %xblkx.load, [label %xblkx.begin, label %xblkx.begin3, label %xblkx.begin4, label %xblkx.begin5, label %xblkx.begin6, label %xblkx.begin7, label %xblkx.begin8, label %xblkx.begin9, label %xblkx.end] + +xblkx.begin: + br label %xblkx.end + +xblkx.begin3: + br label %xblkx.end + +xblkx.begin4: + br label %xblkx.end + +xblkx.begin5: + br label %xblkx.end + +xblkx.begin6: + br label %xblkx.end + +xblkx.begin7: + br label %xblkx.end + +xblkx.begin8: + br label %xblkx.end + +xblkx.begin9: + br label %xblkx.end + +xblkx.end: + %yes.0 = phi i1 [ false, %xblkx.begin ], [ true, %xlab8x ], [ false, %xblkx.begin9 ], [ false, %xblkx.begin8 ], [ false, %xblkx.begin7 ], [ false, %xblkx.begin6 ], [ false, %xblkx.begin5 ], [ true, %xblkx.begin4 ], [ false, %xblkx.begin3 ] + br i1 %yes.0, label %v2j, label %xlab17x + +v2j: +; CHECK: %xunusedx = call i32 @xactionx() + %xunusedx = call i32 @xactionx() + br label %xlab4x + +xlab17x: + br label %xlab4x + +xlab4x: + %incr19 = add i32 %xval704x.0, 1 + br label %xlab5x + +xlab5x: + %xval704x.0 = phi i32 [ 0, %escape-string.top ], [ %incr19, %xlab4x ] + %xval10x = icmp ult i32 %xval704x.0, %xval202x + br i1 %xval10x, label %xlab8x, label %xlab9x + +xlab9x: + ret void +} + +declare i32 @xfunc5x() +declare i8 @xfunc7x() +declare i32 @xselectorx() +declare i32 @xactionx() From rafael.espindola at gmail.com Sat Jun 4 09:53:00 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Sat, 04 Jun 2011 10:53:00 -0400 Subject: [llvm-commits] patch: refactor the asmparser a little In-Reply-To: References: Message-ID: <4DEA46CC.2070405@gmail.com> On 11-06-02 8:18 PM, Nick Lewycky wrote: > The attached patch refactors the asm parsers' parsing of strings into a > ReadString method and parsing of LocalVarName or GlobalVarName into > ReadName(). No functionality change intended. > > I'm asking for review because the parser doesn't already have helper > functions like these, and I wanted to check whether the error-reporting > style (inconsistent between the two) is okay to commit or if anyone has > suggestions. I am not familiar with this code, but the patch looks reasonable. The inconsistency is probably OK, since the functions have different uses. If you want to be a bit more consistent, you could do: lltok::Kind kind; if (ReadString(lltok::StringConstant, &kind)) return kind; > Nick Cheers, Rafael From rafael.espindola at gmail.com Sat Jun 4 10:06:09 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Sat, 04 Jun 2011 11:06:09 -0400 Subject: [llvm-commits] patch: add support for GOTTPOFF in 32-bit mode In-Reply-To: <4DE9E09A.6090801@mxc.ca> References: <4DE9DFE9.1070400@mxc.ca> <4DE9E09A.6090801@mxc.ca> Message-ID: <4DEA49E1.4030201@gmail.com> On 11-06-04 3:36 AM, Nick Lewycky wrote: > Once again, with patch. LGTM >> Nick Cheers, Rafael From hans at hanshq.net Sat Jun 4 11:00:19 2011 From: hans at hanshq.net (Hans Wennborg) Date: Sat, 04 Jun 2011 16:00:19 -0000 Subject: [llvm-commits] [llvm] r132641 - /llvm/trunk/include/llvm-c/Core.h Message-ID: <20110604160019.E531B2A6C12C@llvm.org> Author: hans Date: Sat Jun 4 11:00:19 2011 New Revision: 132641 URL: http://llvm.org/viewvc/llvm-project?rev=132641&view=rev Log: Cast unused parameter to void. Modified: llvm/trunk/include/llvm-c/Core.h Modified: llvm/trunk/include/llvm-c/Core.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm-c/Core.h?rev=132641&r1=132640&r2=132641&view=diff ============================================================================== --- llvm/trunk/include/llvm-c/Core.h (original) +++ llvm/trunk/include/llvm-c/Core.h Sat Jun 4 11:00:19 2011 @@ -1166,6 +1166,7 @@ for (LLVMValueRef *I = Vals, *E = Vals + Length; I != E; ++I) cast(*I); #endif + (void)Length; return reinterpret_cast(Vals); } From stoklund at 2pi.dk Sat Jun 4 11:53:26 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 4 Jun 2011 09:53:26 -0700 Subject: [llvm-commits] [llvm] r132613 - in /llvm/trunk: include/llvm/Analysis/BranchProbabilityInfo.h include/llvm/InitializePasses.h lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp lib/Analysis/CMakeLists.txt In-Reply-To: References: <20110604011630.EB7B52A6C12C@llvm.org> <8A8469FC-8F84-4974-B227-3944E47B2301@2pi.dk> Message-ID: <083E2883-621E-4E61-91D7-2CECD31D1F6A@2pi.dk> On Jun 4, 2011, at 1:50 AM, Frits van Bommel wrote: > On 4 June 2011 10:19, Jakob Stoklund Olesen wrote: >> On Jun 4, 2011, at 12:56 AM, Frits van Bommel wrote: >>> Shouldn't you use 'uint32_t' instead of 'unsigned (int)' throughout >>> (and UINT32_MAX instead of UINT_MAX, etc.)? >> >> LLVM assumes that unsigned is 32 bits in *many* places. It won't work with >> any other int size. > > Do they assume it's 32 bits, or that it's *at least* 32 bits? You can grep '~0' on the sources to get an idea, but I am sure most places would work with a larger int. > Note > that this code essentially assumes it's *exactly* 32 bits because its > results depend on the exact value of UINT_MAX. Sure, let's use UINT32_MAX for the exact value. > But even if what you say is true, I don't consider that to be a good > excuse to contribute to the problem. Which problem? 36-bit preparedness? > And many places in LLVM use > (u)int32_t, too. > > If nothing else, uint32_t is more self-documenting. If a C implementation decides to take on all the portability issues that come from having a 64-bit int, it has to be because 32-bit arithmetic performance is horrible. The uint32_t type makes sense when you need the compact size, or when you depend on modulo 2^32 arithmetic. /jakob From nicholas at mxc.ca Sat Jun 4 12:38:07 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Sat, 04 Jun 2011 17:38:07 -0000 Subject: [llvm-commits] [llvm] r132643 - in /llvm/trunk: lib/MC/ELFObjectWriter.cpp test/MC/ELF/relocation-386.s Message-ID: <20110604173807.515682A6C12C@llvm.org> Author: nicholas Date: Sat Jun 4 12:38:07 2011 New Revision: 132643 URL: http://llvm.org/viewvc/llvm-project?rev=132643&view=rev Log: Add support for @GOTPTOFF in i386 mode. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp llvm/trunk/test/MC/ELF/relocation-386.s Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=132643&r1=132642&r2=132643&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Sat Jun 4 12:38:07 2011 @@ -1720,6 +1720,9 @@ case MCSymbolRefExpr::VK_DTPOFF: Type = ELF::R_386_TLS_LDO_32; break; + case MCSymbolRefExpr::VK_GOTTPOFF: + Type = ELF::R_386_TLS_IE_32; + break; } break; case FK_Data_2: Type = ELF::R_386_16; break; Modified: llvm/trunk/test/MC/ELF/relocation-386.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ELF/relocation-386.s?rev=132643&r1=132642&r2=132643&view=diff ============================================================================== --- llvm/trunk/test/MC/ELF/relocation-386.s (original) +++ llvm/trunk/test/MC/ELF/relocation-386.s Sat Jun 4 12:38:07 2011 @@ -153,6 +153,13 @@ // CHECK-NEXT: ('r_sym', // CHECK-NEXT: ('r_type', 0x00000001) // CHECK-NEXT: ), +// Relocation 24 (foo at GOTTPOFF(%edx)) is of type R_386_TLS_IE_32 and uses the +// symbol +// CHECK-NEXT: Relocation 0x00000018 +// CHECK-NEXT: (('r_offset', 0x0000008e) +// CHECK-NEXT: ('r_sym', 0x0000000d) +// CHECK-NEXT: ('r_type', 0x00000021) +// CHECK-NEXT: ), // Section 4 is bss // CHECK: # Section 0x00000004 @@ -217,6 +224,7 @@ movl zed at TPOFF(%eax), %eax movl zed at DTPOFF(%eax), %eax pushl $bar + addl foo at GOTTPOFF(%edx), %eax .section zedsec,"awT", at progbits zed: From nicholas at mxc.ca Sat Jun 4 13:16:26 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Sat, 04 Jun 2011 18:16:26 -0000 Subject: [llvm-commits] [llvm] r132645 - in /llvm/trunk/lib/AsmParser: LLLexer.cpp LLLexer.h Message-ID: <20110604181626.75FA42A6C12C@llvm.org> Author: nicholas Date: Sat Jun 4 13:16:26 2011 New Revision: 132645 URL: http://llvm.org/viewvc/llvm-project?rev=132645&view=rev Log: Refactor parsing of variable names (ie., %foo and @foo) since they have the same rules. Also refactor "read string until quote" into its own function. No functionality change! Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp llvm/trunk/lib/AsmParser/LLLexer.h Modified: llvm/trunk/lib/AsmParser/LLLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.cpp?rev=132645&r1=132644&r2=132645&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLLexer.cpp (original) +++ llvm/trunk/lib/AsmParser/LLLexer.cpp Sat Jun 4 13:16:26 2011 @@ -308,16 +308,8 @@ } // Handle GlobalVarName: @[-a-zA-Z$._][-a-zA-Z$._0-9]* - if (isalpha(CurPtr[0]) || CurPtr[0] == '-' || CurPtr[0] == '$' || - CurPtr[0] == '.' || CurPtr[0] == '_') { - ++CurPtr; - while (isalnum(CurPtr[0]) || CurPtr[0] == '-' || CurPtr[0] == '$' || - CurPtr[0] == '.' || CurPtr[0] == '_') - ++CurPtr; - - StrVal.assign(TokStart+1, CurPtr); // Skip @ + if (ReadVarName()) return lltok::GlobalVar; - } // Handle GlobalVarID: @[0-9]+ if (isdigit(CurPtr[0])) { @@ -334,6 +326,39 @@ return lltok::Error; } +/// ReadString - Read a string until the closing quote. +lltok::Kind LLLexer::ReadString(lltok::Kind kind) { + const char *Start = CurPtr; + while (1) { + int CurChar = getNextChar(); + + if (CurChar == EOF) { + Error("end of file in string constant"); + return lltok::Error; + } + if (CurChar == '"') { + StrVal.assign(Start, CurPtr-1); + UnEscapeLexed(StrVal); + return kind; + } + } +} + +/// ReadVarName - Read the rest of a token containing a variable name. +bool LLLexer::ReadVarName() { + const char *NameStart = CurPtr; + if (isalpha(CurPtr[0]) || CurPtr[0] == '-' || CurPtr[0] == '$' || + CurPtr[0] == '.' || CurPtr[0] == '_') { + ++CurPtr; + while (isalnum(CurPtr[0]) || CurPtr[0] == '-' || CurPtr[0] == '$' || + CurPtr[0] == '.' || CurPtr[0] == '_') + ++CurPtr; + + StrVal.assign(NameStart, CurPtr); + return true; + } + return false; +} /// LexPercent - Lex all tokens that start with a % character: /// LocalVar ::= %\"[^\"]*\" @@ -343,33 +368,12 @@ // Handle LocalVarName: %\"[^\"]*\" if (CurPtr[0] == '"') { ++CurPtr; - - while (1) { - int CurChar = getNextChar(); - - if (CurChar == EOF) { - Error("end of file in string constant"); - return lltok::Error; - } - if (CurChar == '"') { - StrVal.assign(TokStart+2, CurPtr-1); - UnEscapeLexed(StrVal); - return lltok::LocalVar; - } - } + return ReadString(lltok::LocalVar); } // Handle LocalVarName: %[-a-zA-Z$._][-a-zA-Z$._0-9]* - if (isalpha(CurPtr[0]) || CurPtr[0] == '-' || CurPtr[0] == '$' || - CurPtr[0] == '.' || CurPtr[0] == '_') { - ++CurPtr; - while (isalnum(CurPtr[0]) || CurPtr[0] == '-' || CurPtr[0] == '$' || - CurPtr[0] == '.' || CurPtr[0] == '_') - ++CurPtr; - - StrVal.assign(TokStart+1, CurPtr); // Skip % + if (ReadVarName()) return lltok::LocalVar; - } // Handle LocalVarID: %[0-9]+ if (isdigit(CurPtr[0])) { @@ -390,27 +394,16 @@ /// QuoteLabel "[^"]+": /// StringConstant "[^"]*" lltok::Kind LLLexer::LexQuote() { - while (1) { - int CurChar = getNextChar(); - - if (CurChar == EOF) { - Error("end of file in quoted string"); - return lltok::Error; - } - - if (CurChar != '"') continue; - - if (CurPtr[0] != ':') { - StrVal.assign(TokStart+1, CurPtr-1); - UnEscapeLexed(StrVal); - return lltok::StringConstant; - } + lltok::Kind kind = ReadString(lltok::StringConstant); + if (kind == lltok::Error || kind == lltok::Eof) + return kind; + if (CurPtr[0] == ':') { ++CurPtr; - StrVal.assign(TokStart+1, CurPtr-2); - UnEscapeLexed(StrVal); - return lltok::LabelStr; + kind = lltok::LabelStr; } + + return kind; } static bool JustWhitespaceNewLine(const char *&Ptr) { Modified: llvm/trunk/lib/AsmParser/LLLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLLexer.h?rev=132645&r1=132644&r2=132645&view=diff ============================================================================== --- llvm/trunk/lib/AsmParser/LLLexer.h (original) +++ llvm/trunk/lib/AsmParser/LLLexer.h Sat Jun 4 13:16:26 2011 @@ -71,6 +71,9 @@ int getNextChar(); void SkipLineComment(); + lltok::Kind ReadString(lltok::Kind kind); + bool ReadVarName(); + lltok::Kind LexIdentifier(); lltok::Kind LexDigitOrNegative(); lltok::Kind LexPositive(); From nicholas at mxc.ca Sat Jun 4 13:24:28 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Sat, 04 Jun 2011 11:24:28 -0700 Subject: [llvm-commits] patch: refactor the asmparser a little In-Reply-To: <4DEA46CC.2070405@gmail.com> References: <4DEA46CC.2070405@gmail.com> Message-ID: <4DEA785C.2070003@mxc.ca> Rafael ?vila de Esp?ndola wrote: > On 11-06-02 8:18 PM, Nick Lewycky wrote: >> The attached patch refactors the asm parsers' parsing of strings into a >> ReadString method and parsing of LocalVarName or GlobalVarName into >> ReadName(). No functionality change intended. >> >> I'm asking for review because the parser doesn't already have helper >> functions like these, and I wanted to check whether the error-reporting >> style (inconsistent between the two) is okay to commit or if anyone has >> suggestions. > > I am not familiar with this code, but the patch looks reasonable. The > inconsistency is probably OK, since the functions have different uses. Good point. > If you want to be a bit more consistent, you could do: > > lltok::Kind kind; > if (ReadString(lltok::StringConstant,&kind)) > return kind; Mm, that doesn't solve the real problem which is that we want to report error (Error, Eof) which are token kinds, but don't yet know what token it is in the non-error case by the time ReadString has finished. In particular, that token could end up being a LabelStr, not a StringConstant. Thanks so much for the code review! Nick From yuri at rawbw.com Sat Jun 4 14:53:37 2011 From: yuri at rawbw.com (Yuri) Date: Sat, 04 Jun 2011 12:53:37 -0700 Subject: [llvm-commits] Fwd: Re: [LLVMdev] How to identify LLVM version? [updated patch] Message-ID: <4DEA8D41.8030007@rawbw.com> Forwarding the patch to commits so that it doesn't get lost. Yuri -------- Original Message -------- From: - Fri Jun 03 12:15:47 2011 X-Mozilla-Status: 0011 X-Mozilla-Status2: 10000000 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail1.rawbw.com X-Spam-Level: X-Spam-Status: No, score=-0.2 required=7.0 tests=AWL,HK_RANDOM_ENVFROM, J_CHICKENPOX_102,RCVD_IN_DNSWL_LOW,SPF_PASS,T_RP_MATCHES_RCVD autolearn=disabled version=3.3.1 Received: from dcs-maillist.cs.uiuc.edu (dcs-maillist.cs.uiuc.edu [128.174.252.7]) by mail1.rawbw.com (8.14.2/8.14.2) with ESMTP id p53JAr6i054359 for ; Fri, 3 Jun 2011 12:10:58 -0700 (PDT) (envelope-from llvmdev-bounces at cs.uiuc.edu) Received: from dcs-maillist.uiuc.edu (localhost.localdomain [127.0.0.1]) by dcs-maillist.cs.uiuc.edu (8.13.1/8.13.1) with ESMTP id p53J4o4h015655; Fri, 3 Jun 2011 14:04:56 -0500 Received: from dcs-mxgw.cs.uiuc.edu (dcs-mxgw.cs.uiuc.edu [128.174.252.111]) by dcs-maillist.cs.uiuc.edu (8.13.1/8.13.1) with ESMTP id p53J4nMs015652 for ; Fri, 3 Jun 2011 14:04:49 -0500 Received: from relay02.cites.uiuc.edu (relay02.cites.uiuc.edu [128.174.196.4]) by dcs-mxgw.cs.uiuc.edu (8.13.1/8.13.1) with ESMTP id p53J4m7r021034 for ; Fri, 3 Jun 2011 14:04:48 -0500 Received: from shell0.rawbw.com (shell0.rawbw.com [198.144.192.45]) by relay02.cites.uiuc.edu (8.14.4/8.14.2) with ESMTP id p53J4fMD001323 for ; Fri, 3 Jun 2011 14:04:48 -0500 (CDT) Received: from eagle.yuri.org (stunnel at localhost [127.0.0.1]) (authenticated bits=0) by shell0.rawbw.com (8.14.4/8.14.4) with ESMTP id p53Iwku1042934; Fri, 3 Jun 2011 11:58:47 -0700 (PDT) (envelope-from yuri at rawbw.com) Message-ID: <4DE93048.7070706 at rawbw.com> Date: Fri, 03 Jun 2011 12:04:40 -0700 From: Yuri User-Agent: Mozilla/5.0 (X11; U; FreeBSD amd64; en-US; rv:1.9.1.16) Gecko/20101211 Thunderbird/3.0.11 MIME-Version: 1.0 To: Duncan Sands References: <81AE5BE6-D456-472B-9AF3-1EF93FF17D23 at gmail.com> <87hb8a1xk8.fsf at wanadoo.es> <4DE54671.5080804 at free.fr> <4DE54F97.10004 at rawbw.com> <4DE64C80.1070900 at free.fr> In-Reply-To: <4DE64C80.1070900 at free.fr> Content-Type: multipart/mixed; boundary="------------040309060905060409090106" Cc: LLVM Developers Mailing List Subject: Re: [LLVMdev] How to identify LLVM version? [updated patch] X-BeenThere: llvmdev at cs.uiuc.edu X-Mailman-Version: 2.1.8 Precedence: list List-Id: LLVM Developers Mailing List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: llvmdev-bounces at cs.uiuc.edu Errors-To: llvmdev-bounces at cs.uiuc.edu Following the suggestions of Joachim Durchholz and Csaba Raduly, I submit the updated patch. Yuri -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110604/3b992e51/attachment.html -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: patch.txt Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110604/3b992e51/attachment.txt From nadav.rotem at intel.com Sat Jun 4 15:32:01 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Sat, 04 Jun 2011 20:32:01 -0000 Subject: [llvm-commits] [llvm] r132648 - /llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <20110604203201.37F1B2A6C12C@llvm.org> Author: nadav Date: Sat Jun 4 15:32:01 2011 New Revision: 132648 URL: http://llvm.org/viewvc/llvm-project?rev=132648&view=rev Log: TypeLegalizer: Fix a bug in the promotion of elements of integer vectors. (only happens when using the -promote-elements option). The correct legalization order is to first try to promote element. Next, we try to widen vectors. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=132648&r1=132647&r2=132648&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Sat Jun 4 15:32:01 2011 @@ -821,26 +821,32 @@ unsigned NElts = VT.getVectorNumElements(); if (NElts != 1) { bool IsLegalWiderType = false; + // If we allow the promotion of vector elements using a flag, + // then return TypePromoteInteger on vector elements. + // First try to promote the elements of integer vectors. If no legal + // promotion was found, fallback to the widen-vector method. + if (mayPromoteElements) for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { EVT SVT = (MVT::SimpleValueType)nVT; - - // If we allow the promotion of vector elements using a flag, - // then return TypePromoteInteger on vector elements. - if (mayPromoteElements) { - // Promote vectors of integers to vectors with the same number - // of elements, with a wider element type. - if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() - && SVT.getVectorNumElements() == NElts && - isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { - TransformToType[i] = SVT; - RegisterTypeForVT[i] = SVT; - NumRegistersForVT[i] = 1; - ValueTypeActions.setTypeAction(VT, TypePromoteInteger); - IsLegalWiderType = true; - break; - } + // Promote vectors of integers to vectors with the same number + // of elements, with a wider element type. + if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits() + && SVT.getVectorNumElements() == NElts && + isTypeLegal(SVT) && SVT.getScalarType().isInteger()) { + TransformToType[i] = SVT; + RegisterTypeForVT[i] = SVT; + NumRegistersForVT[i] = 1; + ValueTypeActions.setTypeAction(VT, TypePromoteInteger); + IsLegalWiderType = true; + break; } + } + + if (IsLegalWiderType) continue; + // Try to widen the vector. + for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) { + EVT SVT = (MVT::SimpleValueType)nVT; if (SVT.getVectorElementType() == EltVT && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) { From nadav.rotem at intel.com Sat Jun 4 15:58:08 2011 From: nadav.rotem at intel.com (Nadav Rotem) Date: Sat, 04 Jun 2011 20:58:08 -0000 Subject: [llvm-commits] [llvm] r132649 - in /llvm/trunk: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp test/CodeGen/Generic/basic-promote-integers.ll Message-ID: <20110604205808.6551A2A6C12C@llvm.org> Author: nadav Date: Sat Jun 4 15:58:08 2011 New Revision: 132649 URL: http://llvm.org/viewvc/llvm-project?rev=132649&view=rev Log: TypeLegalizer: Add support for passing of vector-promoted types in registers (copyFromParts/copyToParts). Added: llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=132649&r1=132648&r2=132649&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Sat Jun 4 15:58:08 2011 @@ -280,7 +280,28 @@ } // Vector/Vector bitcast. - return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); + if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) + return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); + + assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && + "Cannot handle this kind of promotion"); + // Promoted vector extract + unsigned NumElts = ValueVT.getVectorNumElements(); + SmallVector NewOps; + for (unsigned i = 0; i < NumElts; ++i) { + SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, + PartVT.getScalarType(), Val ,DAG.getIntPtrConstant(i)); + SDValue Cast; + + bool Smaller = ValueVT.bitsLE(PartVT); + + Cast = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), + DL, ValueVT.getScalarType(), Ext); + + NewOps.push_back(Cast); + } + return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, + &NewOps[0], NewOps.size()); } // Trivial bitcast if the types are the same size and the destination @@ -452,7 +473,24 @@ //SDValue UndefElts = DAG.getUNDEF(VectorTy); //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); - } else { + } else if (PartVT.isVector() && + PartVT.getVectorElementType().bitsGE( + ValueVT.getVectorElementType())&& + PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { + + // Promoted vector extract + unsigned NumElts = ValueVT.getVectorNumElements(); + SmallVector NewOps; + for (unsigned i = 0; i < NumElts; ++i) { + SDValue Ext = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, + ValueVT.getScalarType(), Val ,DAG.getIntPtrConstant(i)); + SDValue Cast = DAG.getNode(ISD::ANY_EXTEND, + DL, PartVT.getScalarType(), Ext); + NewOps.push_back(Cast); + } + Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, + &NewOps[0], NewOps.size()); + } else{ // Vector -> scalar conversion. assert(ValueVT.getVectorElementType() == PartVT && ValueVT.getVectorNumElements() == 1 && Added: llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll?rev=132649&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll (added) +++ llvm/trunk/test/CodeGen/Generic/basic-promote-integers.ll Sat Jun 4 15:58:08 2011 @@ -0,0 +1,20 @@ +; Test that vectors are scalarized/lowered correctly +; (with both legalization methods). +; RUN: llc -march=x86 -promote-elements < %s +; RUN: llc -march=x86 < %s + +; A simple test to check copyToParts and copyFromParts + +define <4 x i64> @test_param_0(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + ret <4 x i64> %A +} + +define <2 x i32> @test_param_1(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + ret <2 x i32> %B +} + +define <4 x i8> @test_param_2(<4 x i64> %A, <2 x i32> %B, <4 x i8> %C) { + ret <4 x i8> %C +} + + From stoklund at 2pi.dk Sat Jun 4 18:34:40 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Sat, 04 Jun 2011 23:34:40 -0000 Subject: [llvm-commits] [llvm] r132654 - /llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll Message-ID: <20110604233440.6A9872A6C12C@llvm.org> Author: stoklund Date: Sat Jun 4 18:34:40 2011 New Revision: 132654 URL: http://llvm.org/viewvc/llvm-project?rev=132654&view=rev Log: Fix a test that keeps breaking when allocation orders change. Who said FileCheck couldn't handle arbitrarily complex conditions? Modified: llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll Modified: llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll?rev=132654&r1=132653&r2=132654&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll (original) +++ llvm/trunk/test/CodeGen/X86/2008-09-18-inline-asm-2.ll Sat Jun 4 18:34:40 2011 @@ -1,12 +1,32 @@ -; RUN: llc < %s -march=x86 -regalloc=linearscan | grep "#%ebp %edi %ebx 8(%esi) %eax %dl" -; RUN: llc < %s -march=x86 -regalloc=fast | grep "#%ebx %esi %edi 8(%ebp) %eax %dl" -; RUN: llc < %s -march=x86 -regalloc=basic | grep "#%ebp %esi %edx 8(%edi) %eax %bl" -; RUN: llc < %s -march=x86 -regalloc=greedy | grep "#%edx %edi %ebp 8(%esi) %eax %bl" +; RUN: llc < %s -march=x86 -regalloc=linearscan | FileCheck %s +; RUN: llc < %s -march=x86 -regalloc=fast | FileCheck %s +; RUN: llc < %s -march=x86 -regalloc=basic | FileCheck %s +; RUN: llc < %s -march=x86 -regalloc=greedy | FileCheck %s -; The 1st, 2nd, 3rd and 5th registers above must all be different. The registers +; The 1st, 2nd, 3rd and 5th registers must all be different. The registers ; referenced in the 4th and 6th operands must not be the same as the 1st or 5th -; operand. There are many combinations that work; this is what llc puts out now. -; ModuleID = '' +; operand. +; +; CHECK: 1st=[[A1:%...]] +; CHECK-NOT: [[A1]] +; CHECK: 2nd=[[A2:%...]] +; CHECK-NOT: [[A1]] +; CHECK-NOT: [[A2]] +; CHECK: 3rd=[[A3:%...]] +; CHECK-NOT: [[A1]] +; CHECK-NOT: [[A2]] +; CHECK-NOT: [[A3]] +; CHECK: 5th=[[A5:%...]] +; CHECK-NOT: [[A1]] +; CHECK-NOT; [[A5]] +; CHECK: =4th + +; The 6th operand is an 8-bit register, and it mustn't alias the 1st and 5th. +; CHECK: 1%e[[S1:.]]x +; CHECK: 5%e[[S5:.]]x +; CHECK-NOT: %[[S1]] +; CHECK-NOT: %[[S5]] + target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128" target triple = "i386-apple-darwin8" %struct.foo = type { i32, i32, i8* } @@ -19,7 +39,7 @@ %3 = load i32* %0, align 4 ; [#uses=1] %4 = load i32* %1, align 4 ; [#uses=1] %5 = load i8* %state, align 1 ; [#uses=1] - %asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#$0 $1 $2 $3 $4 $5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3] + %asmtmp = tail call { i32, i32, i32, i32 } asm sideeffect "#1st=$0 $1 2nd=$1 $2 3rd=$2 $4 5th=$4 $3=4th 1$0 1%eXx 5$4 5%eXx 6th=$5", "=&r,=r,=r,=*m,=&q,=*imr,1,2,*m,5,~{dirflag},~{fpsr},~{flags},~{cx}"(i8** %2, i8* %state, i32 %3, i32 %4, i8** %2, i8 %5) nounwind ; <{ i32, i32, i32, i32 }> [#uses=3] %asmresult = extractvalue { i32, i32, i32, i32 } %asmtmp, 0 ; [#uses=1] %asmresult1 = extractvalue { i32, i32, i32, i32 } %asmtmp, 1 ; [#uses=1] store i32 %asmresult1, i32* %0 From rafael.espindola at gmail.com Sat Jun 4 20:20:07 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sun, 05 Jun 2011 01:20:07 -0000 Subject: [llvm-commits] [llvm] r132655 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp Message-ID: <20110605012007.21BB82A6C12C@llvm.org> Author: rafael Date: Sat Jun 4 20:20:06 2011 New Revision: 132655 URL: http://llvm.org/viewvc/llvm-project?rev=132655&view=rev Log: Produce an undefined reference to _GLOBAL_OFFSET_TABLE_ if we have a VK_GOTOFF reloc. This matches as' behavior, but it is not clear why the linker might need this, so I added a FIXME. I could test this by duplicating test/MC/ELF/got.s, but it doesn't look worthwhile. Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp Modified: llvm/trunk/lib/MC/ELFObjectWriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/ELFObjectWriter.cpp?rev=132655&r1=132654&r2=132655&view=diff ============================================================================== --- llvm/trunk/lib/MC/ELFObjectWriter.cpp (original) +++ llvm/trunk/lib/MC/ELFObjectWriter.cpp Sat Jun 4 20:20:06 2011 @@ -62,6 +62,7 @@ case MCSymbolRefExpr::VK_GOT: case MCSymbolRefExpr::VK_PLT: case MCSymbolRefExpr::VK_GOTPCREL: + case MCSymbolRefExpr::VK_GOTOFF: case MCSymbolRefExpr::VK_TPOFF: case MCSymbolRefExpr::VK_TLSGD: case MCSymbolRefExpr::VK_GOTTPOFF: @@ -556,6 +557,7 @@ RevGroupMapTy RevGroupMap, unsigned NumRegularSections) { // FIXME: Is this the correct place to do this? + // FIXME: Why is an undefined reference to _GLOBAL_OFFSET_TABLE_ needed? if (NeedsGOT) { llvm::StringRef Name = "_GLOBAL_OFFSET_TABLE_"; MCSymbol *Sym = Asm.getContext().GetOrCreateSymbol(Name); From ofv at wanadoo.es Sat Jun 4 21:25:14 2011 From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=) Date: Sun, 05 Jun 2011 04:25:14 +0200 Subject: [llvm-commits] [llvm] r132655 - /llvm/trunk/lib/MC/ELFObjectWriter.cpp References: <20110605012007.21BB82A6C12C@llvm.org> Message-ID: <874o4510c5.fsf@wanadoo.es> Rafael Espindola writes: > URL: http://llvm.org/viewvc/llvm-project?rev=132655&view=rev > Log: > Produce an undefined reference to _GLOBAL_OFFSET_TABLE_ if we have a > VK_GOTOFF reloc. This matches as' behavior, but it is not clear why the linker > might need this, so I added a FIXME. [snip] Another VK_GOTOFF mystery: http://llvm.org/bugs/show_bug.cgi?id=10022 [snip] From rafael.espindola at gmail.com Sat Jun 4 21:43:45 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Sun, 05 Jun 2011 02:43:45 -0000 Subject: [llvm-commits] [llvm] r132656 - in /llvm/trunk: include/llvm/MC/MCParser/MCAsmLexer.h lib/MC/MCParser/AsmLexer.cpp lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/macro-args.s Message-ID: <20110605024345.4D5162A6C12C@llvm.org> Author: rafael Date: Sat Jun 4 21:43:45 2011 New Revision: 132656 URL: http://llvm.org/viewvc/llvm-project?rev=132656&view=rev Log: Basic support for macros with explicit arguments. We still don't handle * default values * :req * :vararg * \() Added: llvm/trunk/test/MC/AsmParser/macro-args.s Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h llvm/trunk/lib/MC/MCParser/AsmLexer.cpp llvm/trunk/lib/MC/MCParser/AsmParser.cpp Modified: llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h?rev=132656&r1=132655&r2=132656&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h (original) +++ llvm/trunk/include/llvm/MC/MCParser/MCAsmLexer.h Sat Jun 4 21:43:45 2011 @@ -44,6 +44,7 @@ Colon, Plus, Minus, Tilde, Slash, // '/' + BackSlash, // '\' LParen, RParen, LBrac, RBrac, LCurly, RCurly, Star, Dot, Comma, Dollar, Equal, EqualEqual, Modified: llvm/trunk/lib/MC/MCParser/AsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmLexer.cpp?rev=132656&r1=132655&r2=132656&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmLexer.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmLexer.cpp Sat Jun 4 21:43:45 2011 @@ -388,6 +388,7 @@ case ',': return AsmToken(AsmToken::Comma, StringRef(TokStart, 1)); case '$': return AsmToken(AsmToken::Dollar, StringRef(TokStart, 1)); case '@': return AsmToken(AsmToken::At, StringRef(TokStart, 1)); + case '\\': return AsmToken(AsmToken::BackSlash, StringRef(TokStart, 1)); case '=': if (*CurPtr == '=') return ++CurPtr, AsmToken(AsmToken::EqualEqual, StringRef(TokStart, 2)); Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=132656&r1=132655&r2=132656&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Sat Jun 4 21:43:45 2011 @@ -47,9 +47,11 @@ struct Macro { StringRef Name; StringRef Body; + std::vector Parameters; public: - Macro(StringRef N, StringRef B) : Name(N), Body(B) {} + Macro(StringRef N, StringRef B, const std::vector &P) : + Name(N), Body(B), Parameters(P) {} }; /// \brief Helper class for storing information about an active macro @@ -69,7 +71,7 @@ public: MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL, - const std::vector > &A); + MemoryBuffer *I); }; /// \brief The concrete assembly parser instance. @@ -151,6 +153,10 @@ bool ParseStatement(); bool HandleMacroEntry(StringRef Name, SMLoc NameLoc, const Macro *M); + bool expandMacro(SmallString<256> &Buf, StringRef Body, + const std::vector &Parameters, + const std::vector > &A, + const SMLoc &L); void HandleMacroExit(); void PrintMacroInstantiations(); @@ -1183,27 +1189,33 @@ return false; } -MacroInstantiation::MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL, - const std::vector > &A) - : TheMacro(M), InstantiationLoc(IL), ExitLoc(EL) -{ - // Macro instantiation is lexical, unfortunately. We construct a new buffer - // to hold the macro body with substitutions. - SmallString<256> Buf; +bool AsmParser::expandMacro(SmallString<256> &Buf, StringRef Body, + const std::vector &Parameters, + const std::vector > &A, + const SMLoc &L) { raw_svector_ostream OS(Buf); + unsigned NParameters = Parameters.size(); + if (NParameters != 0 && NParameters != A.size()) + return Error(L, "Wrong number of arguments"); - StringRef Body = M->Body; while (!Body.empty()) { // Scan for the next substitution. std::size_t End = Body.size(), Pos = 0; for (; Pos != End; ++Pos) { // Check for a substitution or escape. - if (Body[Pos] != '$' || Pos + 1 == End) - continue; - - char Next = Body[Pos + 1]; - if (Next == '$' || Next == 'n' || isdigit(Next)) - break; + if (!NParameters) { + // This macro has no parameters, look for $0, $1, etc. + if (Body[Pos] != '$' || Pos + 1 == End) + continue; + + char Next = Body[Pos + 1]; + if (Next == '$' || Next == 'n' || isdigit(Next)) + break; + } else { + // This macro has parameters, look for \foo, \bar, etc. + if (Body[Pos] == '\\' && Pos + 1 != End) + break; + } } // Add the prefix. @@ -1213,41 +1225,69 @@ if (Pos == End) break; - switch (Body[Pos+1]) { - // $$ => $ - case '$': - OS << '$'; - break; + if (!NParameters) { + switch (Body[Pos+1]) { + // $$ => $ + case '$': + OS << '$'; + break; - // $n => number of arguments - case 'n': - OS << A.size(); - break; + // $n => number of arguments + case 'n': + OS << A.size(); + break; - // $[0-9] => argument - default: { - // Missing arguments are ignored. - unsigned Index = Body[Pos+1] - '0'; - if (Index >= A.size()) + // $[0-9] => argument + default: { + // Missing arguments are ignored. + unsigned Index = Body[Pos+1] - '0'; + if (Index >= A.size()) + break; + + // Otherwise substitute with the token values, with spaces eliminated. + for (std::vector::const_iterator it = A[Index].begin(), + ie = A[Index].end(); it != ie; ++it) + OS << it->getString(); break; + } + } + Pos += 2; + } else { + unsigned I = Pos + 1; + while (isalnum(Body[I]) && I + 1 != End) + ++I; + + const char *Begin = Body.data() + Pos +1; + StringRef Argument(Begin, I - (Pos +1)); + unsigned Index = 0; + for (; Index < NParameters; ++Index) + if (Parameters[Index] == Argument) + break; + + // FIXME: We should error at the macro definition. + if (Index == NParameters) + return Error(L, "Parameter not found"); - // Otherwise substitute with the token values, with spaces eliminated. for (std::vector::const_iterator it = A[Index].begin(), ie = A[Index].end(); it != ie; ++it) OS << it->getString(); - break; - } - } + Pos += 1 + Argument.size(); + } // Update the scan point. - Body = Body.substr(Pos + 2); + Body = Body.substr(Pos); } // We include the .endmacro in the buffer as our queue to exit the macro // instantiation. OS << ".endmacro\n"; + return false; +} - Instantiation = MemoryBuffer::getMemBufferCopy(OS.str(), ""); +MacroInstantiation::MacroInstantiation(const Macro *M, SMLoc IL, SMLoc EL, + MemoryBuffer *I) + : TheMacro(M), Instantiation(I), InstantiationLoc(IL), ExitLoc(EL) +{ } bool AsmParser::HandleMacroEntry(StringRef Name, SMLoc NameLoc, @@ -1284,11 +1324,22 @@ Lex(); } + // Macro instantiation is lexical, unfortunately. We construct a new buffer + // to hold the macro body with substitutions. + SmallString<256> Buf; + StringRef Body = M->Body; + + if (expandMacro(Buf, Body, M->Parameters, MacroArguments, getTok().getLoc())) + return true; + + MemoryBuffer *Instantiation = + MemoryBuffer::getMemBufferCopy(Buf.str(), ""); + // Create the macro instantiation object and add to the current macro // instantiation stack. MacroInstantiation *MI = new MacroInstantiation(M, NameLoc, getTok().getLoc(), - MacroArguments); + Instantiation); ActiveMacros.push_back(MI); // Jump to the macro instantiation and prime the lexer. @@ -2538,13 +2589,27 @@ } /// ParseDirectiveMacro -/// ::= .macro name +/// ::= .macro name [parameters] bool GenericAsmParser::ParseDirectiveMacro(StringRef Directive, SMLoc DirectiveLoc) { StringRef Name; if (getParser().ParseIdentifier(Name)) return TokError("expected identifier in directive"); + std::vector Parameters; + if (getLexer().isNot(AsmToken::EndOfStatement)) { + for(;;) { + StringRef Parameter; + if (getParser().ParseIdentifier(Parameter)) + return TokError("expected identifier in directive"); + Parameters.push_back(Parameter); + + if (getLexer().isNot(AsmToken::Comma)) + break; + Lex(); + } + } + if (getLexer().isNot(AsmToken::EndOfStatement)) return TokError("unexpected token in '.macro' directive"); @@ -2582,7 +2647,7 @@ const char *BodyStart = StartToken.getLoc().getPointer(); const char *BodyEnd = EndToken.getLoc().getPointer(); StringRef Body = StringRef(BodyStart, BodyEnd - BodyStart); - getParser().MacroMap[Name] = new Macro(Name, Body); + getParser().MacroMap[Name] = new Macro(Name, Body, Parameters); return false; } Added: llvm/trunk/test/MC/AsmParser/macro-args.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/macro-args.s?rev=132656&view=auto ============================================================================== --- llvm/trunk/test/MC/AsmParser/macro-args.s (added) +++ llvm/trunk/test/MC/AsmParser/macro-args.s Sat Jun 4 21:43:45 2011 @@ -0,0 +1,10 @@ +// RUN: llvm-mc -triple x86_64-apple-darwin10 %s | FileCheck %s + +.macro GET var,re2g + movl \var at GOTOFF(%ebx),\re2g +.endm + + +GET is_sse, %eax + +// CHECK: movl is_sse at GOTOFF(%ebx), %eax From pageexec at freemail.hu Sun Jun 5 08:15:00 2011 From: pageexec at freemail.hu (pageexec at freemail.hu) Date: Sun, 05 Jun 2011 15:15:00 +0200 Subject: [llvm-commits] problem with r132497 on linux Message-ID: <4DEB8154.1594.D6BD770@pageexec.freemail.hu> Hi, r132497 breaks clang on gentoo when one sets CXX_INCLUDE_ROOT as i do (to avoid all the guesswork regarding gcc paths). in particular, i set it to /usr/lib/gcc/i686-pc-linux-gnu/4.5.2/include/g++-v4 which doesn't match the pattern that this commit assumes and hence produces invalid paths for the linker. for now my workaround is below but i guess the proper solution is to explicitly pass linker paths to configure. Index: llvm/tools/clang/lib/Driver/ToolChains.cpp =================================================================== --- llvm/tools/clang/lib/Driver/ToolChains.cpp (revision 132660) +++ llvm/tools/clang/lib/Driver/ToolChains.cpp (working copy) @@ -1343,17 +1343,20 @@ llvm::SmallString<128> CxxIncludeRoot(CXX_INCLUDE_ROOT); if (CxxIncludeRoot != "") { // This is of the form /foo/bar/include/c++/4.5.2/ + // /usr/lib/gcc/i686-pc-linux-gnu/4.5.2/include/g++-v4 if (CxxIncludeRoot.back() == '/') llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the / - llvm::StringRef Version = llvm::sys::path::filename(CxxIncludeRoot); - llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the version - llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the c++ + llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the g++-v4 llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the include +// llvm::StringRef Version = llvm::sys::path::filename(CxxIncludeRoot); +// llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the version +// llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the c++ +// llvm::sys::path::remove_filename(CxxIncludeRoot); // remove the include std::string ret(CxxIncludeRoot.c_str()); - ret.append("/lib/gcc/"); - ret.append(CXX_INCLUDE_ARCH); - ret.append("/"); - ret.append(Version); +// ret.append("/lib/gcc/"); +// ret.append(CXX_INCLUDE_ARCH); +// ret.append("/"); +// ret.append(Version); return ret; } static const char* GccVersions[] = {"4.6.0", "4.6", From rafael.espindola at gmail.com Sun Jun 5 08:45:47 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Sun, 05 Jun 2011 09:45:47 -0400 Subject: [llvm-commits] problem with r132497 on linux In-Reply-To: <4DEB8154.1594.D6BD770@pageexec.freemail.hu> References: <4DEB8154.1594.D6BD770@pageexec.freemail.hu> Message-ID: <4DEB888B.8080109@gmail.com> On 11-06-05 9:15 AM, pageexec at freemail.hu wrote: > Hi, > > r132497 breaks clang on gentoo when one sets CXX_INCLUDE_ROOT as i do (to avoid > all the guesswork regarding gcc paths). in particular, i set it to > > /usr/lib/gcc/i686-pc-linux-gnu/4.5.2/include/g++-v4 > > which doesn't match the pattern that this commit assumes and hence produces invalid > paths for the linker. for now my workaround is below but i guess the proper solution > is to explicitly pass linker paths to configure. Linux distros are amazing! Chandler is refactoring this to support absolute and relative paths. I would suggest waiting for that to avoid conflicts and then add support for distinct include and lib roots (with one defaulting to the other). Cheers, Rafael From benny.kra at googlemail.com Sun Jun 5 09:36:47 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sun, 05 Jun 2011 14:36:47 -0000 Subject: [llvm-commits] [llvm] r132668 - /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Message-ID: <20110605143647.8767D2A6C12C@llvm.org> Author: d0k Date: Sun Jun 5 09:36:47 2011 New Revision: 132668 URL: http://llvm.org/viewvc/llvm-project?rev=132668&view=rev Log: Use path API for path concatenation. Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=132668&r1=132667&r2=132668&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original) +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Sun Jun 5 09:36:47 2011 @@ -819,11 +819,9 @@ return GetOrCreateSourceID("", StringRef()); // MCStream expects full path name as filename. - if (!DirName.empty() && !FileName.startswith("/")) { - std::string FullPathName(DirName.data()); - if (!DirName.endswith("/")) - FullPathName += "/"; - FullPathName += FileName.data(); + if (!DirName.empty() && !sys::path::is_absolute(FileName)) { + SmallString<128> FullPathName = DirName; + sys::path::append(FullPathName, FileName); // Here FullPathName will be copied into StringMap by GetOrCreateSourceID. return GetOrCreateSourceID(StringRef(FullPathName), StringRef()); } From baldrick at free.fr Sun Jun 5 11:25:07 2011 From: baldrick at free.fr (Duncan Sands) Date: Sun, 05 Jun 2011 16:25:07 -0000 Subject: [llvm-commits] [dragonegg] r132670 - in /dragonegg/trunk/src/x86: Target.cpp x86_builtins Message-ID: <20110605162507.DC1462A6C12C@llvm.org> Author: baldrick Date: Sun Jun 5 11:25:07 2011 New Revision: 132670 URL: http://llvm.org/viewvc/llvm-project?rev=132670&view=rev Log: Rather than turning sqrtps into llvm.sqrt, just turn it into the LLVM sqrtps intrinsic (this happens automagically), because llvm.sqrt does not have the same semantics. Turn sqrtps_nr into sqrtps, since this is what GCC does. Modified: dragonegg/trunk/src/x86/Target.cpp dragonegg/trunk/src/x86/x86_builtins Modified: dragonegg/trunk/src/x86/Target.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/x86/Target.cpp?rev=132670&r1=132669&r2=132670&view=diff ============================================================================== --- dragonegg/trunk/src/x86/Target.cpp (original) +++ dragonegg/trunk/src/x86/Target.cpp Sun Jun 5 11:25:07 2011 @@ -776,19 +776,12 @@ SI->setAlignment(16); return true; } - case sqrtpd: - case sqrtpd256: - case sqrtps: - case sqrtps256: - case sqrtsd: - case sqrtss: - // No need for a Newton-Raphson step - sqrtps is already accurate. - case sqrtps_nr: - case sqrtps_nr256: { - const Type *Ty = Ops[0]->getType(); - Function *sqrt = Intrinsic::getDeclaration(TheModule, Intrinsic::sqrt, &Ty, - 1); - Result = Builder.CreateCall(sqrt, Ops[0]); + case sqrtps_nr: { + // Turn this into sqrtps without a Newton-Raphson step - sqrtps is already + // accurate enough. + Function *sqrtps = Intrinsic::getDeclaration(TheModule, + Intrinsic::x86_sse_sqrt_ps); + Result = Builder.CreateCall(sqrtps, Ops[0]); return true; } } Modified: dragonegg/trunk/src/x86/x86_builtins URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/x86/x86_builtins?rev=132670&r1=132669&r2=132670&view=diff ============================================================================== --- dragonegg/trunk/src/x86/x86_builtins (original) +++ dragonegg/trunk/src/x86/x86_builtins Sun Jun 5 11:25:07 2011 @@ -525,14 +525,14 @@ //DEFINE_BUILTIN(shufps256), //DEFINE_BUILTIN(si256_si), //DEFINE_BUILTIN(si_si256), -DEFINE_BUILTIN(sqrtpd), -DEFINE_BUILTIN(sqrtpd256), -DEFINE_BUILTIN(sqrtps), -DEFINE_BUILTIN(sqrtps256), +//DEFINE_BUILTIN(sqrtpd), +//DEFINE_BUILTIN(sqrtpd256), +//DEFINE_BUILTIN(sqrtps), +//DEFINE_BUILTIN(sqrtps256), DEFINE_BUILTIN(sqrtps_nr), -DEFINE_BUILTIN(sqrtps_nr256), -DEFINE_BUILTIN(sqrtsd), -DEFINE_BUILTIN(sqrtss), +//DEFINE_BUILTIN(sqrtps_nr256), +//DEFINE_BUILTIN(sqrtsd), +//DEFINE_BUILTIN(sqrtss), DEFINE_BUILTIN(stmxcsr), DEFINE_BUILTIN(storedqu), //DEFINE_BUILTIN(storedqu256), From baldrick at free.fr Sun Jun 5 12:50:23 2011 From: baldrick at free.fr (Duncan Sands) Date: Sun, 05 Jun 2011 19:50:23 +0200 Subject: [llvm-commits] [llvm] r132538 - /llvm/trunk/lib/Support/FoldingSet.cpp In-Reply-To: <20110603082951.5E0C32A6C12C@llvm.org> References: <20110603082951.5E0C32A6C12C@llvm.org> Message-ID: <4DEBC1DF.5020302@free.fr> Hi, > singed int causes signed extension, which contradicts the intention to pick up > integers with high 32 bits being zero. do you have a testcase for this? Ciao, Duncan. > > Modified: > llvm/trunk/lib/Support/FoldingSet.cpp > > Modified: llvm/trunk/lib/Support/FoldingSet.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/FoldingSet.cpp?rev=132538&r1=132537&r2=132538&view=diff > ============================================================================== > --- llvm/trunk/lib/Support/FoldingSet.cpp (original) > +++ llvm/trunk/lib/Support/FoldingSet.cpp Fri Jun 3 03:29:51 2011 > @@ -92,7 +92,7 @@ > } > void FoldingSetNodeID::AddInteger(unsigned long long I) { > AddInteger(unsigned(I)); > - if ((uint64_t)(int)I != I) > + if ((uint64_t)(unsigned)I != I) > Bits.push_back(unsigned(I>> 32)); > } > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From benny.kra at googlemail.com Sun Jun 5 13:20:05 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Sun, 05 Jun 2011 18:20:05 -0000 Subject: [llvm-commits] [llvm] r132671 - /llvm/trunk/test/CodeGen/X86/dbg-file-name.ll Message-ID: <20110605182005.D5B652A6C12C@llvm.org> Author: d0k Date: Sun Jun 5 13:20:05 2011 New Revision: 132671 URL: http://llvm.org/viewvc/llvm-project?rev=132671&view=rev Log: Harden tests for windows path separators. Modified: llvm/trunk/test/CodeGen/X86/dbg-file-name.ll Modified: llvm/trunk/test/CodeGen/X86/dbg-file-name.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-file-name.ll?rev=132671&r1=132670&r2=132671&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-file-name.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-file-name.ll Sun Jun 5 13:20:05 2011 @@ -1,7 +1,7 @@ ; RUN: llc -mtriple x86_64-apple-darwin10.0.0 < %s | FileCheck %s ; Radar 8884898 -; CHECK: file 1 "/Users/manav/one/two/simple.c" +; CHECK: file 1 "/Users/manav/one/two{{/|\\\\}}simple.c" declare i32 @printf(i8*, ...) nounwind