TriedMerging;
class SameTailElt {
MPIterator MPIter;
Added: llvm/trunk/test/CodeGen/X86/tail-threshold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-threshold.ll?rev=132974&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-threshold.ll (added)
+++ llvm/trunk/test/CodeGen/X86/tail-threshold.ll Mon Jun 13 23:41:17 2011
@@ -0,0 +1,41 @@
+; RUN: llc %s -stats -tail-merge-threshold 2 -o /dev/null |& FileCheck %s
+
+; Test that we still do some merging if a block has more than
+; tail-merge-threshold predecessors.
+
+; CHECK: 2 branchfolding - Number of block tails merged
+
+declare void @bar()
+
+define void @foo(i32 %xxx) {
+entry:
+ switch i32 %xxx, label %bb4 [
+ i32 0, label %bb0
+ i32 1, label %bb1
+ i32 2, label %bb2
+ i32 3, label %bb3
+ ]
+
+bb0:
+ call void @bar()
+ br label %bb5
+
+bb1:
+ call void @bar()
+ br label %bb5
+
+bb2:
+ call void @bar()
+ br label %bb5
+
+bb3:
+ call void @bar()
+ br label %bb5
+
+bb4:
+ call void @bar()
+ br label %bb5
+
+bb5:
+ ret void
+}
From bruno.cardoso at gmail.com Mon Jun 13 23:58:37 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 14 Jun 2011 04:58:37 -0000
Subject: [llvm-commits] [llvm] r132976 - in /llvm/trunk: docs/LangRef.html
include/llvm/CodeGen/ISDOpcodes.h include/llvm/Intrinsics.td
include/llvm/Target/TargetSelectionDAG.td
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMInstrInfo.td
lib/Target/X86/X86InstrSSE.td lib/VMCore/AutoUpgrade.cpp
test/Assembler/AutoUpgradeIntrinsics.ll test/CodeGen/ARM/prefetch.ll
test/CodeGen/X86/prefetch.ll
Message-ID: <20110614045838.768612A6C12C@llvm.org>
Author: bruno
Date: Mon Jun 13 23:58:37 2011
New Revision: 132976
URL: http://llvm.org/viewvc/llvm-project?rev=132976&view=rev
Log:
Add one more argument to the prefetch intrinsic to indicate whether it's a data
or instruction cache access. Update the targets to match it and also teach
autoupgrade.
Modified:
llvm/trunk/docs/LangRef.html
llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h
llvm/trunk/include/llvm/Intrinsics.td
llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrSSE.td
llvm/trunk/lib/VMCore/AutoUpgrade.cpp
llvm/trunk/test/Assembler/AutoUpgradeIntrinsics.ll
llvm/trunk/test/CodeGen/ARM/prefetch.ll
llvm/trunk/test/CodeGen/X86/prefetch.ll
Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Mon Jun 13 23:58:37 2011
@@ -6064,7 +6064,7 @@
Syntax:
- declare void @llvm.prefetch(i8* <address>, i32 <rw>, i32 <locality>)
+ declare void @llvm.prefetch(i8* <address>, i32 <rw>, i32 <locality>, i32 <cache type>)
Overview:
@@ -6077,8 +6077,10 @@
address is the address to be prefetched, rw is the
specifier determining if the fetch should be for a read (0) or write (1),
and locality is a temporal locality specifier ranging from (0) - no
- locality, to (3) - extremely local keep in cache. The rw
- and locality arguments must be constant integers.
+ locality, to (3) - extremely local keep in cache. The cache type
+ specifies whether the prefetch is performed on the data (1) or instruction (0)
+ cache. The rw, locality and cache type arguments
+ must be constant integers.
Semantics:
This intrinsic does not modify the behavior of the program. In particular,
Modified: llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h (original)
+++ llvm/trunk/include/llvm/CodeGen/ISDOpcodes.h Mon Jun 13 23:58:37 2011
@@ -580,7 +580,8 @@
// PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are
// their first operand. The other operands are the address to prefetch,
- // read / write specifier, and locality specifier.
+ // read / write specifier, locality specifier and instruction / data cache
+ // specifier.
PREFETCH,
// OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
Modified: llvm/trunk/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Mon Jun 13 23:58:37 2011
@@ -211,7 +211,8 @@
// however it does conveniently prevent the prefetch from being reordered
// with respect to nearby accesses to the same memory.
def int_prefetch : Intrinsic<[],
- [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty],
+ [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty,
+ llvm_i32_ty],
[IntrReadWriteArgMem, NoCapture<0>]>;
def int_pcmarker : Intrinsic<[], [llvm_i32_ty]>;
Modified: llvm/trunk/include/llvm/Target/TargetSelectionDAG.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSelectionDAG.td?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSelectionDAG.td (original)
+++ llvm/trunk/include/llvm/Target/TargetSelectionDAG.td Mon Jun 13 23:58:37 2011
@@ -197,8 +197,8 @@
SDTCisSubVecOfVec<2, 1>, SDTCisSameAs<0,1>, SDTCisInt<3>
]>;
-def SDTPrefetch : SDTypeProfile<0, 3, [ // prefetch
- SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisInt<1>
+def SDTPrefetch : SDTypeProfile<0, 4, [ // prefetch
+ SDTCisPtrTy<0>, SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>, SDTCisInt<1>
]>;
def SDTMemBarrier : SDTypeProfile<0, 5, [ // memory barier
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Jun 13 23:58:37 2011
@@ -4788,15 +4788,16 @@
return implVisitAluOverflow(I, ISD::SMULO);
case Intrinsic::prefetch: {
- SDValue Ops[4];
+ SDValue Ops[5];
unsigned rw = cast(I.getArgOperand(1))->getZExtValue();
Ops[0] = getRoot();
Ops[1] = getValue(I.getArgOperand(0));
Ops[2] = getValue(I.getArgOperand(1));
Ops[3] = getValue(I.getArgOperand(2));
+ Ops[4] = getValue(I.getArgOperand(3));
DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl,
DAG.getVTList(MVT::Other),
- &Ops[0], 4,
+ &Ops[0], 5,
EVT::getIntegerVT(*Context, 8),
MachinePointerInfo(I.getArgOperand(0)),
0, /* align */
Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Mon Jun 13 23:58:37 2011
@@ -2281,12 +2281,13 @@
// ARMv7 with MP extension has PLDW.
return Op.getOperand(0);
- if (Subtarget->isThumb())
+ unsigned isData = cast(Op.getOperand(4))->getZExtValue();
+ if (Subtarget->isThumb()) {
// Invert the bits.
isRead = ~isRead & 1;
- unsigned isData = Subtarget->isThumb() ? 0 : 1;
+ isData = ~isData & 1;
+ }
- // Currently there is no intrinsic that matches pli.
return DAG.getNode(ARMISD::PRELOAD, dl, MVT::Other, Op.getOperand(0),
Op.getOperand(1), DAG.getConstant(isRead, MVT::i32),
DAG.getConstant(isData, MVT::i32));
Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jun 13 23:58:37 2011
@@ -62,6 +62,9 @@
def SDT_ARMMEMBARRIER : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
+def SDT_ARMPREFETCH : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisSameAs<1, 2>,
+ SDTCisInt<1>]>;
+
def SDT_ARMTCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
def SDT_ARMBFI : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
@@ -130,7 +133,7 @@
[SDNPHasChain]>;
def ARMMemBarrierMCR : SDNode<"ARMISD::MEMBARRIER_MCR", SDT_ARMMEMBARRIER,
[SDNPHasChain]>;
-def ARMPreload : SDNode<"ARMISD::PRELOAD", SDTPrefetch,
+def ARMPreload : SDNode<"ARMISD::PRELOAD", SDT_ARMPREFETCH,
[SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
def ARMrbit : SDNode<"ARMISD::RBIT", SDTIntUnaryOp>;
Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jun 13 23:58:37 2011
@@ -2006,13 +2006,13 @@
// Prefetch intrinsic.
def PREFETCHT0 : PSI<0x18, MRM1m, (outs), (ins i8mem:$src),
- "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3))]>;
+ "prefetcht0\t$src", [(prefetch addr:$src, imm, (i32 3), (i32 1))]>;
def PREFETCHT1 : PSI<0x18, MRM2m, (outs), (ins i8mem:$src),
- "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2))]>;
+ "prefetcht1\t$src", [(prefetch addr:$src, imm, (i32 2), (i32 1))]>;
def PREFETCHT2 : PSI<0x18, MRM3m, (outs), (ins i8mem:$src),
- "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1))]>;
+ "prefetcht2\t$src", [(prefetch addr:$src, imm, (i32 1), (i32 1))]>;
def PREFETCHNTA : PSI<0x18, MRM0m, (outs), (ins i8mem:$src),
- "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0))]>;
+ "prefetchnta\t$src", [(prefetch addr:$src, imm, (i32 0), (i32 1))]>;
// Load, store, and memory fence
def SFENCE : I<0xAE, MRM_F8, (outs), (ins), "sfence", [(int_x86_sse_sfence)]>,
Modified: llvm/trunk/lib/VMCore/AutoUpgrade.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AutoUpgrade.cpp?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AutoUpgrade.cpp (original)
+++ llvm/trunk/lib/VMCore/AutoUpgrade.cpp Mon Jun 13 23:58:37 2011
@@ -284,6 +284,30 @@
break;
}
+ // This upgrades the llvm.prefetch intrinsic to accept one more parameter,
+ // which is a instruction / data cache identifier. The old version only
+ // implicitly accepted the data version.
+ if (Name.compare(5,8,"prefetch",8) == 0) {
+ // Don't do anything if it has the correct number of arguments already
+ if (FTy->getNumParams() == 4)
+ break;
+
+ assert(FTy->getNumParams() == 3 && "old prefetch takes 3 args!");
+ // We first need to change the name of the old (bad) intrinsic, because
+ // its type is incorrect, but we cannot overload that name. We
+ // arbitrarily unique it here allowing us to construct a correctly named
+ // and typed function below.
+ F->setName("");
+ NewFn = cast(M->getOrInsertFunction(Name,
+ FTy->getReturnType(),
+ FTy->getParamType(0),
+ FTy->getParamType(1),
+ FTy->getParamType(2),
+ FTy->getParamType(2),
+ (Type*)0));
+ return true;
+ }
+
break;
case 'x':
// This fixes the poorly named crc32 intrinsics
@@ -1344,6 +1368,29 @@
CI->eraseFromParent();
break;
}
+ case Intrinsic::prefetch: {
+ IRBuilder<> Builder(C);
+ Builder.SetInsertPoint(CI->getParent(), CI);
+ const llvm::Type *I32Ty = llvm::Type::getInt32Ty(CI->getContext());
+
+ // Add the extra "data cache" argument
+ Value *Operands[4] = { CI->getArgOperand(0), CI->getArgOperand(1),
+ CI->getArgOperand(2),
+ llvm::ConstantInt::get(I32Ty, 1) };
+ CallInst *NewCI = CallInst::Create(NewFn, Operands, Operands+4,
+ CI->getName(), CI);
+ NewCI->setTailCall(CI->isTailCall());
+ NewCI->setCallingConv(CI->getCallingConv());
+ // Handle any uses of the old CallInst.
+ if (!CI->use_empty())
+ // Replace all uses of the old call with the new cast which has the
+ // correct type.
+ CI->replaceAllUsesWith(NewCI);
+
+ // Clean up the old call now that it has been completely upgraded.
+ CI->eraseFromParent();
+ break;
+ }
}
}
Modified: llvm/trunk/test/Assembler/AutoUpgradeIntrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Assembler/AutoUpgradeIntrinsics.ll?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/test/Assembler/AutoUpgradeIntrinsics.ll (original)
+++ llvm/trunk/test/Assembler/AutoUpgradeIntrinsics.ll Mon Jun 13 23:58:37 2011
@@ -109,3 +109,11 @@
call void @llvm.x86.sse2.movnt.i(i8* %B, i32 %D)
ret void
}
+
+declare void @llvm.prefetch(i8*, i32, i32) nounwind
+
+define void @p(i8* %ptr) {
+; CHECK: llvm.prefetch(i8* %ptr, i32 0, i32 1, i32 1)
+ tail call void @llvm.prefetch(i8* %ptr, i32 0, i32 1)
+ ret void
+}
Modified: llvm/trunk/test/CodeGen/ARM/prefetch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/prefetch.ll?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/prefetch.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/prefetch.ll Mon Jun 13 23:58:37 2011
@@ -17,8 +17,8 @@
; THUMB2: t1:
; THUMB2-NOT: pldw [r0]
; THUMB2: pld [r0]
- tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3 )
- tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
+ tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
+ tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
ret void
}
@@ -30,7 +30,7 @@
; THUMB2: t2:
; THUMB2: pld [r0, #1023]
%tmp = getelementptr i8* %ptr, i32 1023
- tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3 )
+ tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 )
ret void
}
@@ -45,7 +45,7 @@
%tmp1 = lshr i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
%tmp3 = inttoptr i32 %tmp2 to i8*
- tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
+ tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3, i32 1 )
ret void
}
@@ -59,8 +59,8 @@
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
%tmp3 = inttoptr i32 %tmp2 to i8*
- tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3 )
+ tail call void @llvm.prefetch( i8* %tmp3, i32 0, i32 3, i32 1 )
ret void
}
-declare void @llvm.prefetch(i8*, i32, i32) nounwind
+declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
Modified: llvm/trunk/test/CodeGen/X86/prefetch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/prefetch.ll?rev=132976&r1=132975&r2=132976&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/prefetch.ll (original)
+++ llvm/trunk/test/CodeGen/X86/prefetch.ll Mon Jun 13 23:58:37 2011
@@ -6,11 +6,11 @@
; CHECK: prefetcht1
; CHECK: prefetcht0
; CHECK: prefetchnta
- tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1 )
- tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2 )
- tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3 )
- tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0 )
+ tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 1, i32 1 )
+ tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 2, i32 1 )
+ tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 1 )
+ tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 0, i32 1 )
ret void
}
-declare void @llvm.prefetch(i8*, i32, i32) nounwind
+declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
From bruno.cardoso at gmail.com Tue Jun 14 00:11:46 2011
From: bruno.cardoso at gmail.com (Bruno Cardoso Lopes)
Date: Tue, 14 Jun 2011 05:11:46 -0000
Subject: [llvm-commits] [llvm] r132978 -
/llvm/trunk/test/CodeGen/ARM/prefetch.ll
Message-ID: <20110614051146.BC6A32A6C12C@llvm.org>
Author: bruno
Date: Tue Jun 14 00:11:46 2011
New Revision: 132978
URL: http://llvm.org/viewvc/llvm-project?rev=132978&view=rev
Log:
Since ARM's prefetch implementation predicted the presence of a instruction
cache prefetch and now that the info from "prefetch" to "ARMPreload" is present,
only add a testcase for PLI.
Modified:
llvm/trunk/test/CodeGen/ARM/prefetch.ll
Modified: llvm/trunk/test/CodeGen/ARM/prefetch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/prefetch.ll?rev=132978&r1=132977&r2=132978&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/prefetch.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/prefetch.ll Tue Jun 14 00:11:46 2011
@@ -64,3 +64,14 @@
}
declare void @llvm.prefetch(i8*, i32, i32, i32) nounwind
+
+define void @t5(i8* %ptr) nounwind {
+entry:
+; ARM: t5:
+; ARM: pli [r0]
+
+; THUMB2: t5:
+; THUMB2: pli [r0]
+ tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 )
+ ret void
+}
From rafael.espindola at gmail.com Tue Jun 14 01:08:32 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 14 Jun 2011 06:08:32 -0000
Subject: [llvm-commits] [llvm] r132981 - in /llvm/trunk:
lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/Thumb2/machine-licm.ll
Message-ID: <20110614060832.E6B3C2A6C132@llvm.org>
Author: rafael
Date: Tue Jun 14 01:08:32 2011
New Revision: 132981
URL: http://llvm.org/viewvc/llvm-project?rev=132981&view=rev
Log:
Implement Jakob's suggestion on how to detect fall thought without calling
AnalyzeBranch.
Modified:
llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=132981&r1=132980&r2=132981&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Tue Jun 14 01:08:32 2011
@@ -1934,19 +1934,26 @@
if (Pred->empty())
return true;
- // Otherwise, ask the backend.
- const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
- MachineBasicBlock *PredTBB = NULL, *PredFBB = NULL;
- SmallVector PredCond;
- if (TII->AnalyzeBranch(*Pred, PredTBB, PredFBB, PredCond))
- return false;
-
- if (PredTBB == MBB || PredFBB == MBB)
- return false;
-
- // This is a fall through if there is no conditions in the bb
- // or if there is no explicit false branch.
- return PredCond.empty() || !PredFBB;
+ // Check the terminators in the previous blocks
+ for (MachineBasicBlock::iterator II = Pred->getFirstTerminator(),
+ IE = Pred->end(); II != IE; ++II) {
+ MachineInstr &MI = *II;
+
+ // If it is not a simple branch, we are in a table somewhere.
+ if (!MI.getDesc().isBranch() || MI.getDesc().isIndirectBranch())
+ return false;
+
+ // If we are the operands of one of the branches, this is not
+ // a fall through.
+ for (MachineInstr::mop_iterator OI = MI.operands_begin(),
+ OE = MI.operands_end(); OI != OE; ++OI) {
+ const MachineOperand& OP = *OI;
+ if (OP.isMBB() && OP.getMBB() == MBB)
+ return false;
+ }
+ }
+
+ return true;
}
Modified: llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll?rev=132981&r1=132980&r2=132981&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/machine-licm.ll Tue Jun 14 01:08:32 2011
@@ -13,7 +13,7 @@
br i1 %0, label %return, label %bb.nph
bb.nph: ; preds = %entry
-; CHECK: LBB0_1:
+; CHECK: BB#1
; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr
; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr
; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]]
@@ -21,7 +21,7 @@
; CHECK: LBB0_2
; CHECK-NOT: LCPI0_0:
-; PIC: LBB0_1:
+; PIC: BB#1
; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4))
; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4))
; PIC: add r[[R2]], pc
From rafael.espindola at gmail.com Tue Jun 14 01:31:30 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Tue, 14 Jun 2011 02:31:30 -0400
Subject: [llvm-commits] [llvm] r132882 - in /llvm/trunk:
lib/CodeGen/AsmPrinter/AsmPrinter.cpp lib/Target/X86/X86InstrInfo.cpp
test/CodeGen/Thumb2/machine-licm.ll
In-Reply-To: <0222EB7F-4D75-4E46-B861-AB0385743715@2pi.dk>
References: <20110612032033.086FB2A6C12C@llvm.org>
<22E522CD-27D8-4C2D-A89E-3F9004CC9D3C@2pi.dk>
<4DF46CDA.9030509@gmail.com>
<5EA38794-3EAE-4F93-90AB-7683CEF05AFF@2pi.dk>
<40D8EA4F-144A-4668-B59F-F71585CBD8BB@apple.com>
<37EBA7B5-FE45-4ED2-8E79-DF8157E75C9E@2pi.dk>
<4DF6578C.8070606@gmail.com>
<0222EB7F-4D75-4E46-B861-AB0385743715@2pi.dk>
Message-ID: <4DF70042.1070002@gmail.com>
On 11-06-13 8:56 PM, Jakob Stoklund Olesen wrote:
>
> On Jun 13, 2011, at 11:31 AM, Rafael Avila de Espindola wrote:
>
>>> Rafael, are you emitting more labels now, or does the extra AnalyzeBranch call take care of that?
>>
>> On X86, yes. On ARM there was on test that AnalyzeBranch is bailing out, so we printed one extra label (machine-licm.ll).
>
> How about looking at the predecessor's terminator operands. If they mention the basic block or a jump table, add the label?
Done. Thanks!
> /jakob
>
Cheers,
Rafael
From zwarich at apple.com Tue Jun 14 01:33:52 2011
From: zwarich at apple.com (Cameron Zwarich)
Date: Tue, 14 Jun 2011 06:33:52 -0000
Subject: [llvm-commits] [llvm] r132982 -
/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
Message-ID: <20110614063352.2617B2A6C12E@llvm.org>
Author: zwarich
Date: Tue Jun 14 01:33:51 2011
New Revision: 132982
URL: http://llvm.org/viewvc/llvm-project?rev=132982&view=rev
Log:
Be more obvious about what is being tested.
Modified:
llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=132982&r1=132981&r2=132982&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Tue Jun 14 01:33:51 2011
@@ -300,7 +300,8 @@
// we just get a lot of insert/extracts. If at least one vector is
// involved, then we probably really do have a union of vector/array.
const Type *NewTy;
- if (VectorTy && ScalarKind != ImplicitVector) {
+ if (ScalarKind == Vector) {
+ assert(VectorTy && "Missing type for vector scalar.");
DEBUG(dbgs() << "CONVERT TO VECTOR: " << *AI << "\n TYPE = "
<< *VectorTy << '\n');
NewTy = VectorTy; // Use the vector type.
From nadav.rotem at intel.com Tue Jun 14 02:18:26 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Tue, 14 Jun 2011 07:18:26 -0000
Subject: [llvm-commits] [llvm] r132984 -
/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Message-ID: <20110614071827.012E92A6C12C@llvm.org>
Author: nadav
Date: Tue Jun 14 02:18:26 2011
New Revision: 132984
URL: http://llvm.org/viewvc/llvm-project?rev=132984&view=rev
Log:
Disable trunc-store simplification on vectors.
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=132984&r1=132983&r2=132984&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jun 14 02:18:26 2011
@@ -6425,7 +6425,7 @@
// FIXME: is there such a thing as a truncating indexed store?
if (ST->isTruncatingStore() && ST->isUnindexed() &&
- Value.getValueType().isInteger()) {
+ Value.getValueType().isInteger() && !Value.getValueType().isVector()) {
// See if we can simplify the input to this truncstore with knowledge that
// only the low bits are being used. For example:
// "truncstore (or (shl x, 8), y), i8" -> "truncstore y, i8"
From nadav.rotem at intel.com Tue Jun 14 03:11:52 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Tue, 14 Jun 2011 08:11:52 -0000
Subject: [llvm-commits] [llvm] r132985 - in /llvm/trunk:
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
test/CodeGen/X86/mem-promote-integers.ll
Message-ID: <20110614081152.A6B8F2A6C12D@llvm.org>
Author: nadav
Date: Tue Jun 14 03:11:52 2011
New Revision: 132985
URL: http://llvm.org/viewvc/llvm-project?rev=132985&view=rev
Log:
Add a testcase for checking the integer-promotion of many different vector
types (with power of two types such as 8,16,32 .. 512).
Fix a bug in the integer promotion of bitcast nodes. Enable integer expanding
only if the target of the conversion is an integer (when the type action is
scalarize).
Add handling to the legalization of vector load/store in cases where the saved
vector is integer-promoted.
Added:
llvm/trunk/test/CodeGen/X86/mem-promote-integers.ll
Modified:
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=132985&r1=132984&r2=132985&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Tue Jun 14 03:11:52 2011
@@ -1374,6 +1374,91 @@
Tmp2 = LegalizeOp(Load.getValue(1));
break;
}
+
+ // If this is a promoted vector load, and the vector element types are
+ // legal, then scalarize it.
+ if (ExtType == ISD::EXTLOAD && SrcVT.isVector() &&
+ isTypeLegal(Node->getValueType(0).getScalarType())) {
+ SmallVector LoadVals;
+ SmallVector LoadChains;
+ unsigned NumElem = SrcVT.getVectorNumElements();
+ unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
+
+ for (unsigned Idx=0; IdxgetValueType(0).getScalarType(),
+ Tmp1, Tmp2, LD->getPointerInfo().getWithOffset(Idx * Stride),
+ SrcVT.getScalarType(),
+ LD->isVolatile(), LD->isNonTemporal(),
+ LD->getAlignment());
+
+ LoadVals.push_back(ScalarLoad.getValue(0));
+ LoadChains.push_back(ScalarLoad.getValue(1));
+ }
+ Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ &LoadChains[0], LoadChains.size());
+ SDValue ValRes = DAG.getNode(ISD::BUILD_VECTOR, dl,
+ Node->getValueType(0), &LoadVals[0], LoadVals.size());
+
+ Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
+ Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
+ break;
+ }
+
+ // If this is a promoted vector load, and the vector element types are
+ // illegal, create the promoted vector from bitcasted segments.
+ if (ExtType == ISD::EXTLOAD && SrcVT.isVector()) {
+ EVT MemElemTy = Node->getValueType(0).getScalarType();
+ EVT SrcSclrTy = SrcVT.getScalarType();
+ unsigned SizeRatio =
+ (MemElemTy.getSizeInBits() / SrcSclrTy.getSizeInBits());
+
+ SmallVector LoadVals;
+ SmallVector LoadChains;
+ unsigned NumElem = SrcVT.getVectorNumElements();
+ unsigned Stride = SrcVT.getScalarType().getSizeInBits()/8;
+
+ for (unsigned Idx=0; IdxgetPointerInfo().getWithOffset(Idx * Stride),
+ SrcVT.getScalarType(),
+ LD->isVolatile(), LD->isNonTemporal(),
+ LD->getAlignment());
+ if (TLI.isBigEndian()) {
+ // MSB (which is garbage, comes first)
+ LoadVals.push_back(ScalarLoad.getValue(0));
+ for (unsigned i = 0; igetValueType(0), ValRes);
+
+ Tmp1 = LegalizeOp(ValRes); // Relegalize new nodes.
+ Tmp2 = LegalizeOp(Result.getValue(0)); // Relegalize new nodes.
+ break;
+
+ }
+
// FIXME: This does not work for vectors on most targets. Sign- and
// zero-extend operations are currently folded into extending loads,
// whether they are legal or not, and then we end up here without any
@@ -1549,6 +1634,88 @@
Result = TLI.LowerOperation(Result, DAG);
break;
case Expand:
+
+ EVT WideScalarVT = Tmp3.getValueType().getScalarType();
+ EVT NarrowScalarVT = StVT.getScalarType();
+
+ // The Store type is illegal, must scalarize the vector store.
+ SmallVector Stores;
+ bool ScalarLegal = isTypeLegal(WideScalarVT);
+ if (!isTypeLegal(StVT) && StVT.isVector() && ScalarLegal) {
+ unsigned NumElem = StVT.getVectorNumElements();
+
+ unsigned ScalarSize = StVT.getScalarType().getSizeInBits();
+ // Round odd types to the next pow of two.
+ if (!isPowerOf2_32(ScalarSize))
+ ScalarSize = NextPowerOf2(ScalarSize);
+ // Types smaller than 8 bits are promoted to 8 bits.
+ ScalarSize = std::max(ScalarSize, 8);
+ // Store stride
+ unsigned Stride = ScalarSize/8;
+ assert(isPowerOf2_32(Stride) && "Stride must be a power of two");
+
+ for (unsigned Idx=0; IdxgetPointerInfo().getWithOffset(Idx*Stride),
+ isVolatile, isNonTemporal, Alignment);
+ Stores.push_back(Store);
+ }
+ Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ &Stores[0], Stores.size());
+ break;
+ }
+
+ // The Store type is illegal, must scalarize the vector store.
+ // However, the scalar type is illegal. Must bitcast the result
+ // and store it in smaller parts.
+ if (!isTypeLegal(StVT) && StVT.isVector()) {
+ unsigned WideNumElem = StVT.getVectorNumElements();
+ unsigned Stride = NarrowScalarVT.getSizeInBits()/8;
+
+ unsigned SizeRatio =
+ (WideScalarVT.getSizeInBits() / NarrowScalarVT.getSizeInBits());
+
+ EVT CastValueVT = EVT::getVectorVT(*DAG.getContext(), NarrowScalarVT,
+ SizeRatio*WideNumElem);
+
+ // Cast the wide elem vector to wider vec with smaller elem type.
+ // Example <2 x i64> -> <4 x i32>
+ Tmp3 = DAG.getNode(ISD::BITCAST, dl, CastValueVT, Tmp3);
+
+ for (unsigned Idx=0; IdxgetPointerInfo().getWithOffset(Idx*Stride),
+ isVolatile, isNonTemporal, Alignment);
+ Stores.push_back(Store);
+ }
+ }
+ Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ &Stores[0], Stores.size());
+ break;
+ }
+
+
// TRUNCSTORE:i16 i32 -> STORE i16
assert(isTypeLegal(StVT) && "Do not know how to expand this store!");
Tmp3 = DAG.getNode(ISD::TRUNCATE, dl, StVT, Tmp3);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=132985&r1=132984&r2=132985&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Tue Jun 14 03:11:52 2011
@@ -204,8 +204,10 @@
break;
case TargetLowering::TypeScalarizeVector:
// Convert the element to an integer and promote it by hand.
- return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
- BitConvertToInteger(GetScalarizedVector(InOp)));
+ if (!NOutVT.isVector())
+ return DAG.getNode(ISD::ANY_EXTEND, dl, NOutVT,
+ BitConvertToInteger(GetScalarizedVector(InOp)));
+ break;
case TargetLowering::TypeSplitVector: {
// For example, i32 = BITCAST v2i16 on alpha. Convert the split
// pieces of the input into integers and reassemble in the final type.
Added: llvm/trunk/test/CodeGen/X86/mem-promote-integers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mem-promote-integers.ll?rev=132985&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mem-promote-integers.ll (added)
+++ llvm/trunk/test/CodeGen/X86/mem-promote-integers.ll Tue Jun 14 03:11:52 2011
@@ -0,0 +1,1467 @@
+; RUN: llc -march=x86 -promote-elements < %s
+; RUN: llc -march=x86 < %s
+; RUN: llc -march=x86-64 -promote-elements < %s
+; RUN: llc -march=x86-64 < %s
+
+define <1 x i8> @test_1xi8(<1 x i8> %x, <1 x i8>* %b) {
+ %bb = load <1 x i8>* %b
+ %tt = xor <1 x i8> %x, %bb
+ store <1 x i8> %tt, <1 x i8>* %b
+ br label %next
+
+next:
+ ret <1 x i8> %tt
+}
+
+
+define <1 x i16> @test_1xi16(<1 x i16> %x, <1 x i16>* %b) {
+ %bb = load <1 x i16>* %b
+ %tt = xor <1 x i16> %x, %bb
+ store <1 x i16> %tt, <1 x i16>* %b
+ br label %next
+
+next:
+ ret <1 x i16> %tt
+}
+
+
+define <1 x i32> @test_1xi32(<1 x i32> %x, <1 x i32>* %b) {
+ %bb = load <1 x i32>* %b
+ %tt = xor <1 x i32> %x, %bb
+ store <1 x i32> %tt, <1 x i32>* %b
+ br label %next
+
+next:
+ ret <1 x i32> %tt
+}
+
+
+define <1 x i64> @test_1xi64(<1 x i64> %x, <1 x i64>* %b) {
+ %bb = load <1 x i64>* %b
+ %tt = xor <1 x i64> %x, %bb
+ store <1 x i64> %tt, <1 x i64>* %b
+ br label %next
+
+next:
+ ret <1 x i64> %tt
+}
+
+
+define <1 x i128> @test_1xi128(<1 x i128> %x, <1 x i128>* %b) {
+ %bb = load <1 x i128>* %b
+ %tt = xor <1 x i128> %x, %bb
+ store <1 x i128> %tt, <1 x i128>* %b
+ br label %next
+
+next:
+ ret <1 x i128> %tt
+}
+
+
+define <1 x i256> @test_1xi256(<1 x i256> %x, <1 x i256>* %b) {
+ %bb = load <1 x i256>* %b
+ %tt = xor <1 x i256> %x, %bb
+ store <1 x i256> %tt, <1 x i256>* %b
+ br label %next
+
+next:
+ ret <1 x i256> %tt
+}
+
+
+define <1 x i512> @test_1xi512(<1 x i512> %x, <1 x i512>* %b) {
+ %bb = load <1 x i512>* %b
+ %tt = xor <1 x i512> %x, %bb
+ store <1 x i512> %tt, <1 x i512>* %b
+ br label %next
+
+next:
+ ret <1 x i512> %tt
+}
+
+
+define <2 x i8> @test_2xi8(<2 x i8> %x, <2 x i8>* %b) {
+ %bb = load <2 x i8>* %b
+ %tt = xor <2 x i8> %x, %bb
+ store <2 x i8> %tt, <2 x i8>* %b
+ br label %next
+
+next:
+ ret <2 x i8> %tt
+}
+
+
+define <2 x i16> @test_2xi16(<2 x i16> %x, <2 x i16>* %b) {
+ %bb = load <2 x i16>* %b
+ %tt = xor <2 x i16> %x, %bb
+ store <2 x i16> %tt, <2 x i16>* %b
+ br label %next
+
+next:
+ ret <2 x i16> %tt
+}
+
+
+define <2 x i32> @test_2xi32(<2 x i32> %x, <2 x i32>* %b) {
+ %bb = load <2 x i32>* %b
+ %tt = xor <2 x i32> %x, %bb
+ store <2 x i32> %tt, <2 x i32>* %b
+ br label %next
+
+next:
+ ret <2 x i32> %tt
+}
+
+
+define <2 x i64> @test_2xi64(<2 x i64> %x, <2 x i64>* %b) {
+ %bb = load <2 x i64>* %b
+ %tt = xor <2 x i64> %x, %bb
+ store <2 x i64> %tt, <2 x i64>* %b
+ br label %next
+
+next:
+ ret <2 x i64> %tt
+}
+
+
+define <2 x i128> @test_2xi128(<2 x i128> %x, <2 x i128>* %b) {
+ %bb = load <2 x i128>* %b
+ %tt = xor <2 x i128> %x, %bb
+ store <2 x i128> %tt, <2 x i128>* %b
+ br label %next
+
+next:
+ ret <2 x i128> %tt
+}
+
+
+define <2 x i256> @test_2xi256(<2 x i256> %x, <2 x i256>* %b) {
+ %bb = load <2 x i256>* %b
+ %tt = xor <2 x i256> %x, %bb
+ store <2 x i256> %tt, <2 x i256>* %b
+ br label %next
+
+next:
+ ret <2 x i256> %tt
+}
+
+
+define <2 x i512> @test_2xi512(<2 x i512> %x, <2 x i512>* %b) {
+ %bb = load <2 x i512>* %b
+ %tt = xor <2 x i512> %x, %bb
+ store <2 x i512> %tt, <2 x i512>* %b
+ br label %next
+
+next:
+ ret <2 x i512> %tt
+}
+
+
+define <3 x i8> @test_3xi8(<3 x i8> %x, <3 x i8>* %b) {
+ %bb = load <3 x i8>* %b
+ %tt = xor <3 x i8> %x, %bb
+ store <3 x i8> %tt, <3 x i8>* %b
+ br label %next
+
+next:
+ ret <3 x i8> %tt
+}
+
+
+define <3 x i16> @test_3xi16(<3 x i16> %x, <3 x i16>* %b) {
+ %bb = load <3 x i16>* %b
+ %tt = xor <3 x i16> %x, %bb
+ store <3 x i16> %tt, <3 x i16>* %b
+ br label %next
+
+next:
+ ret <3 x i16> %tt
+}
+
+
+define <3 x i32> @test_3xi32(<3 x i32> %x, <3 x i32>* %b) {
+ %bb = load <3 x i32>* %b
+ %tt = xor <3 x i32> %x, %bb
+ store <3 x i32> %tt, <3 x i32>* %b
+ br label %next
+
+next:
+ ret <3 x i32> %tt
+}
+
+
+define <3 x i64> @test_3xi64(<3 x i64> %x, <3 x i64>* %b) {
+ %bb = load <3 x i64>* %b
+ %tt = xor <3 x i64> %x, %bb
+ store <3 x i64> %tt, <3 x i64>* %b
+ br label %next
+
+next:
+ ret <3 x i64> %tt
+}
+
+
+define <3 x i128> @test_3xi128(<3 x i128> %x, <3 x i128>* %b) {
+ %bb = load <3 x i128>* %b
+ %tt = xor <3 x i128> %x, %bb
+ store <3 x i128> %tt, <3 x i128>* %b
+ br label %next
+
+next:
+ ret <3 x i128> %tt
+}
+
+
+define <3 x i256> @test_3xi256(<3 x i256> %x, <3 x i256>* %b) {
+ %bb = load <3 x i256>* %b
+ %tt = xor <3 x i256> %x, %bb
+ store <3 x i256> %tt, <3 x i256>* %b
+ br label %next
+
+next:
+ ret <3 x i256> %tt
+}
+
+
+define <3 x i512> @test_3xi512(<3 x i512> %x, <3 x i512>* %b) {
+ %bb = load <3 x i512>* %b
+ %tt = xor <3 x i512> %x, %bb
+ store <3 x i512> %tt, <3 x i512>* %b
+ br label %next
+
+next:
+ ret <3 x i512> %tt
+}
+
+
+define <4 x i8> @test_4xi8(<4 x i8> %x, <4 x i8>* %b) {
+ %bb = load <4 x i8>* %b
+ %tt = xor <4 x i8> %x, %bb
+ store <4 x i8> %tt, <4 x i8>* %b
+ br label %next
+
+next:
+ ret <4 x i8> %tt
+}
+
+
+define <4 x i16> @test_4xi16(<4 x i16> %x, <4 x i16>* %b) {
+ %bb = load <4 x i16>* %b
+ %tt = xor <4 x i16> %x, %bb
+ store <4 x i16> %tt, <4 x i16>* %b
+ br label %next
+
+next:
+ ret <4 x i16> %tt
+}
+
+
+define <4 x i32> @test_4xi32(<4 x i32> %x, <4 x i32>* %b) {
+ %bb = load <4 x i32>* %b
+ %tt = xor <4 x i32> %x, %bb
+ store <4 x i32> %tt, <4 x i32>* %b
+ br label %next
+
+next:
+ ret <4 x i32> %tt
+}
+
+
+define <4 x i64> @test_4xi64(<4 x i64> %x, <4 x i64>* %b) {
+ %bb = load <4 x i64>* %b
+ %tt = xor <4 x i64> %x, %bb
+ store <4 x i64> %tt, <4 x i64>* %b
+ br label %next
+
+next:
+ ret <4 x i64> %tt
+}
+
+
+define <4 x i128> @test_4xi128(<4 x i128> %x, <4 x i128>* %b) {
+ %bb = load <4 x i128>* %b
+ %tt = xor <4 x i128> %x, %bb
+ store <4 x i128> %tt, <4 x i128>* %b
+ br label %next
+
+next:
+ ret <4 x i128> %tt
+}
+
+
+define <4 x i256> @test_4xi256(<4 x i256> %x, <4 x i256>* %b) {
+ %bb = load <4 x i256>* %b
+ %tt = xor <4 x i256> %x, %bb
+ store <4 x i256> %tt, <4 x i256>* %b
+ br label %next
+
+next:
+ ret <4 x i256> %tt
+}
+
+
+define <4 x i512> @test_4xi512(<4 x i512> %x, <4 x i512>* %b) {
+ %bb = load <4 x i512>* %b
+ %tt = xor <4 x i512> %x, %bb
+ store <4 x i512> %tt, <4 x i512>* %b
+ br label %next
+
+next:
+ ret <4 x i512> %tt
+}
+
+
+define <5 x i8> @test_5xi8(<5 x i8> %x, <5 x i8>* %b) {
+ %bb = load <5 x i8>* %b
+ %tt = xor <5 x i8> %x, %bb
+ store <5 x i8> %tt, <5 x i8>* %b
+ br label %next
+
+next:
+ ret <5 x i8> %tt
+}
+
+
+define <5 x i16> @test_5xi16(<5 x i16> %x, <5 x i16>* %b) {
+ %bb = load <5 x i16>* %b
+ %tt = xor <5 x i16> %x, %bb
+ store <5 x i16> %tt, <5 x i16>* %b
+ br label %next
+
+next:
+ ret <5 x i16> %tt
+}
+
+
+define <5 x i32> @test_5xi32(<5 x i32> %x, <5 x i32>* %b) {
+ %bb = load <5 x i32>* %b
+ %tt = xor <5 x i32> %x, %bb
+ store <5 x i32> %tt, <5 x i32>* %b
+ br label %next
+
+next:
+ ret <5 x i32> %tt
+}
+
+
+define <5 x i64> @test_5xi64(<5 x i64> %x, <5 x i64>* %b) {
+ %bb = load <5 x i64>* %b
+ %tt = xor <5 x i64> %x, %bb
+ store <5 x i64> %tt, <5 x i64>* %b
+ br label %next
+
+next:
+ ret <5 x i64> %tt
+}
+
+
+define <5 x i128> @test_5xi128(<5 x i128> %x, <5 x i128>* %b) {
+ %bb = load <5 x i128>* %b
+ %tt = xor <5 x i128> %x, %bb
+ store <5 x i128> %tt, <5 x i128>* %b
+ br label %next
+
+next:
+ ret <5 x i128> %tt
+}
+
+
+define <5 x i256> @test_5xi256(<5 x i256> %x, <5 x i256>* %b) {
+ %bb = load <5 x i256>* %b
+ %tt = xor <5 x i256> %x, %bb
+ store <5 x i256> %tt, <5 x i256>* %b
+ br label %next
+
+next:
+ ret <5 x i256> %tt
+}
+
+
+define <5 x i512> @test_5xi512(<5 x i512> %x, <5 x i512>* %b) {
+ %bb = load <5 x i512>* %b
+ %tt = xor <5 x i512> %x, %bb
+ store <5 x i512> %tt, <5 x i512>* %b
+ br label %next
+
+next:
+ ret <5 x i512> %tt
+}
+
+
+define <6 x i8> @test_6xi8(<6 x i8> %x, <6 x i8>* %b) {
+ %bb = load <6 x i8>* %b
+ %tt = xor <6 x i8> %x, %bb
+ store <6 x i8> %tt, <6 x i8>* %b
+ br label %next
+
+next:
+ ret <6 x i8> %tt
+}
+
+
+define <6 x i16> @test_6xi16(<6 x i16> %x, <6 x i16>* %b) {
+ %bb = load <6 x i16>* %b
+ %tt = xor <6 x i16> %x, %bb
+ store <6 x i16> %tt, <6 x i16>* %b
+ br label %next
+
+next:
+ ret <6 x i16> %tt
+}
+
+
+define <6 x i32> @test_6xi32(<6 x i32> %x, <6 x i32>* %b) {
+ %bb = load <6 x i32>* %b
+ %tt = xor <6 x i32> %x, %bb
+ store <6 x i32> %tt, <6 x i32>* %b
+ br label %next
+
+next:
+ ret <6 x i32> %tt
+}
+
+
+define <6 x i64> @test_6xi64(<6 x i64> %x, <6 x i64>* %b) {
+ %bb = load <6 x i64>* %b
+ %tt = xor <6 x i64> %x, %bb
+ store <6 x i64> %tt, <6 x i64>* %b
+ br label %next
+
+next:
+ ret <6 x i64> %tt
+}
+
+
+define <6 x i128> @test_6xi128(<6 x i128> %x, <6 x i128>* %b) {
+ %bb = load <6 x i128>* %b
+ %tt = xor <6 x i128> %x, %bb
+ store <6 x i128> %tt, <6 x i128>* %b
+ br label %next
+
+next:
+ ret <6 x i128> %tt
+}
+
+
+define <6 x i256> @test_6xi256(<6 x i256> %x, <6 x i256>* %b) {
+ %bb = load <6 x i256>* %b
+ %tt = xor <6 x i256> %x, %bb
+ store <6 x i256> %tt, <6 x i256>* %b
+ br label %next
+
+next:
+ ret <6 x i256> %tt
+}
+
+
+define <6 x i512> @test_6xi512(<6 x i512> %x, <6 x i512>* %b) {
+ %bb = load <6 x i512>* %b
+ %tt = xor <6 x i512> %x, %bb
+ store <6 x i512> %tt, <6 x i512>* %b
+ br label %next
+
+next:
+ ret <6 x i512> %tt
+}
+
+
+define <7 x i8> @test_7xi8(<7 x i8> %x, <7 x i8>* %b) {
+ %bb = load <7 x i8>* %b
+ %tt = xor <7 x i8> %x, %bb
+ store <7 x i8> %tt, <7 x i8>* %b
+ br label %next
+
+next:
+ ret <7 x i8> %tt
+}
+
+
+define <7 x i16> @test_7xi16(<7 x i16> %x, <7 x i16>* %b) {
+ %bb = load <7 x i16>* %b
+ %tt = xor <7 x i16> %x, %bb
+ store <7 x i16> %tt, <7 x i16>* %b
+ br label %next
+
+next:
+ ret <7 x i16> %tt
+}
+
+
+define <7 x i32> @test_7xi32(<7 x i32> %x, <7 x i32>* %b) {
+ %bb = load <7 x i32>* %b
+ %tt = xor <7 x i32> %x, %bb
+ store <7 x i32> %tt, <7 x i32>* %b
+ br label %next
+
+next:
+ ret <7 x i32> %tt
+}
+
+
+define <7 x i64> @test_7xi64(<7 x i64> %x, <7 x i64>* %b) {
+ %bb = load <7 x i64>* %b
+ %tt = xor <7 x i64> %x, %bb
+ store <7 x i64> %tt, <7 x i64>* %b
+ br label %next
+
+next:
+ ret <7 x i64> %tt
+}
+
+
+define <7 x i128> @test_7xi128(<7 x i128> %x, <7 x i128>* %b) {
+ %bb = load <7 x i128>* %b
+ %tt = xor <7 x i128> %x, %bb
+ store <7 x i128> %tt, <7 x i128>* %b
+ br label %next
+
+next:
+ ret <7 x i128> %tt
+}
+
+
+define <7 x i256> @test_7xi256(<7 x i256> %x, <7 x i256>* %b) {
+ %bb = load <7 x i256>* %b
+ %tt = xor <7 x i256> %x, %bb
+ store <7 x i256> %tt, <7 x i256>* %b
+ br label %next
+
+next:
+ ret <7 x i256> %tt
+}
+
+
+define <7 x i512> @test_7xi512(<7 x i512> %x, <7 x i512>* %b) {
+ %bb = load <7 x i512>* %b
+ %tt = xor <7 x i512> %x, %bb
+ store <7 x i512> %tt, <7 x i512>* %b
+ br label %next
+
+next:
+ ret <7 x i512> %tt
+}
+
+
+define <8 x i8> @test_8xi8(<8 x i8> %x, <8 x i8>* %b) {
+ %bb = load <8 x i8>* %b
+ %tt = xor <8 x i8> %x, %bb
+ store <8 x i8> %tt, <8 x i8>* %b
+ br label %next
+
+next:
+ ret <8 x i8> %tt
+}
+
+
+define <8 x i16> @test_8xi16(<8 x i16> %x, <8 x i16>* %b) {
+ %bb = load <8 x i16>* %b
+ %tt = xor <8 x i16> %x, %bb
+ store <8 x i16> %tt, <8 x i16>* %b
+ br label %next
+
+next:
+ ret <8 x i16> %tt
+}
+
+
+define <8 x i32> @test_8xi32(<8 x i32> %x, <8 x i32>* %b) {
+ %bb = load <8 x i32>* %b
+ %tt = xor <8 x i32> %x, %bb
+ store <8 x i32> %tt, <8 x i32>* %b
+ br label %next
+
+next:
+ ret <8 x i32> %tt
+}
+
+
+define <8 x i64> @test_8xi64(<8 x i64> %x, <8 x i64>* %b) {
+ %bb = load <8 x i64>* %b
+ %tt = xor <8 x i64> %x, %bb
+ store <8 x i64> %tt, <8 x i64>* %b
+ br label %next
+
+next:
+ ret <8 x i64> %tt
+}
+
+
+define <8 x i128> @test_8xi128(<8 x i128> %x, <8 x i128>* %b) {
+ %bb = load <8 x i128>* %b
+ %tt = xor <8 x i128> %x, %bb
+ store <8 x i128> %tt, <8 x i128>* %b
+ br label %next
+
+next:
+ ret <8 x i128> %tt
+}
+
+
+define <8 x i256> @test_8xi256(<8 x i256> %x, <8 x i256>* %b) {
+ %bb = load <8 x i256>* %b
+ %tt = xor <8 x i256> %x, %bb
+ store <8 x i256> %tt, <8 x i256>* %b
+ br label %next
+
+next:
+ ret <8 x i256> %tt
+}
+
+
+define <8 x i512> @test_8xi512(<8 x i512> %x, <8 x i512>* %b) {
+ %bb = load <8 x i512>* %b
+ %tt = xor <8 x i512> %x, %bb
+ store <8 x i512> %tt, <8 x i512>* %b
+ br label %next
+
+next:
+ ret <8 x i512> %tt
+}
+
+
+define <9 x i8> @test_9xi8(<9 x i8> %x, <9 x i8>* %b) {
+ %bb = load <9 x i8>* %b
+ %tt = xor <9 x i8> %x, %bb
+ store <9 x i8> %tt, <9 x i8>* %b
+ br label %next
+
+next:
+ ret <9 x i8> %tt
+}
+
+
+define <9 x i16> @test_9xi16(<9 x i16> %x, <9 x i16>* %b) {
+ %bb = load <9 x i16>* %b
+ %tt = xor <9 x i16> %x, %bb
+ store <9 x i16> %tt, <9 x i16>* %b
+ br label %next
+
+next:
+ ret <9 x i16> %tt
+}
+
+
+define <9 x i32> @test_9xi32(<9 x i32> %x, <9 x i32>* %b) {
+ %bb = load <9 x i32>* %b
+ %tt = xor <9 x i32> %x, %bb
+ store <9 x i32> %tt, <9 x i32>* %b
+ br label %next
+
+next:
+ ret <9 x i32> %tt
+}
+
+
+define <9 x i64> @test_9xi64(<9 x i64> %x, <9 x i64>* %b) {
+ %bb = load <9 x i64>* %b
+ %tt = xor <9 x i64> %x, %bb
+ store <9 x i64> %tt, <9 x i64>* %b
+ br label %next
+
+next:
+ ret <9 x i64> %tt
+}
+
+
+define <9 x i128> @test_9xi128(<9 x i128> %x, <9 x i128>* %b) {
+ %bb = load <9 x i128>* %b
+ %tt = xor <9 x i128> %x, %bb
+ store <9 x i128> %tt, <9 x i128>* %b
+ br label %next
+
+next:
+ ret <9 x i128> %tt
+}
+
+
+define <9 x i256> @test_9xi256(<9 x i256> %x, <9 x i256>* %b) {
+ %bb = load <9 x i256>* %b
+ %tt = xor <9 x i256> %x, %bb
+ store <9 x i256> %tt, <9 x i256>* %b
+ br label %next
+
+next:
+ ret <9 x i256> %tt
+}
+
+
+define <9 x i512> @test_9xi512(<9 x i512> %x, <9 x i512>* %b) {
+ %bb = load <9 x i512>* %b
+ %tt = xor <9 x i512> %x, %bb
+ store <9 x i512> %tt, <9 x i512>* %b
+ br label %next
+
+next:
+ ret <9 x i512> %tt
+}
+
+
+define <10 x i8> @test_10xi8(<10 x i8> %x, <10 x i8>* %b) {
+ %bb = load <10 x i8>* %b
+ %tt = xor <10 x i8> %x, %bb
+ store <10 x i8> %tt, <10 x i8>* %b
+ br label %next
+
+next:
+ ret <10 x i8> %tt
+}
+
+
+define <10 x i16> @test_10xi16(<10 x i16> %x, <10 x i16>* %b) {
+ %bb = load <10 x i16>* %b
+ %tt = xor <10 x i16> %x, %bb
+ store <10 x i16> %tt, <10 x i16>* %b
+ br label %next
+
+next:
+ ret <10 x i16> %tt
+}
+
+
+define <10 x i32> @test_10xi32(<10 x i32> %x, <10 x i32>* %b) {
+ %bb = load <10 x i32>* %b
+ %tt = xor <10 x i32> %x, %bb
+ store <10 x i32> %tt, <10 x i32>* %b
+ br label %next
+
+next:
+ ret <10 x i32> %tt
+}
+
+
+define <10 x i64> @test_10xi64(<10 x i64> %x, <10 x i64>* %b) {
+ %bb = load <10 x i64>* %b
+ %tt = xor <10 x i64> %x, %bb
+ store <10 x i64> %tt, <10 x i64>* %b
+ br label %next
+
+next:
+ ret <10 x i64> %tt
+}
+
+
+define <10 x i128> @test_10xi128(<10 x i128> %x, <10 x i128>* %b) {
+ %bb = load <10 x i128>* %b
+ %tt = xor <10 x i128> %x, %bb
+ store <10 x i128> %tt, <10 x i128>* %b
+ br label %next
+
+next:
+ ret <10 x i128> %tt
+}
+
+
+define <10 x i256> @test_10xi256(<10 x i256> %x, <10 x i256>* %b) {
+ %bb = load <10 x i256>* %b
+ %tt = xor <10 x i256> %x, %bb
+ store <10 x i256> %tt, <10 x i256>* %b
+ br label %next
+
+next:
+ ret <10 x i256> %tt
+}
+
+
+define <10 x i512> @test_10xi512(<10 x i512> %x, <10 x i512>* %b) {
+ %bb = load <10 x i512>* %b
+ %tt = xor <10 x i512> %x, %bb
+ store <10 x i512> %tt, <10 x i512>* %b
+ br label %next
+
+next:
+ ret <10 x i512> %tt
+}
+
+
+define <11 x i8> @test_11xi8(<11 x i8> %x, <11 x i8>* %b) {
+ %bb = load <11 x i8>* %b
+ %tt = xor <11 x i8> %x, %bb
+ store <11 x i8> %tt, <11 x i8>* %b
+ br label %next
+
+next:
+ ret <11 x i8> %tt
+}
+
+
+define <11 x i16> @test_11xi16(<11 x i16> %x, <11 x i16>* %b) {
+ %bb = load <11 x i16>* %b
+ %tt = xor <11 x i16> %x, %bb
+ store <11 x i16> %tt, <11 x i16>* %b
+ br label %next
+
+next:
+ ret <11 x i16> %tt
+}
+
+
+define <11 x i32> @test_11xi32(<11 x i32> %x, <11 x i32>* %b) {
+ %bb = load <11 x i32>* %b
+ %tt = xor <11 x i32> %x, %bb
+ store <11 x i32> %tt, <11 x i32>* %b
+ br label %next
+
+next:
+ ret <11 x i32> %tt
+}
+
+
+define <11 x i64> @test_11xi64(<11 x i64> %x, <11 x i64>* %b) {
+ %bb = load <11 x i64>* %b
+ %tt = xor <11 x i64> %x, %bb
+ store <11 x i64> %tt, <11 x i64>* %b
+ br label %next
+
+next:
+ ret <11 x i64> %tt
+}
+
+
+define <11 x i128> @test_11xi128(<11 x i128> %x, <11 x i128>* %b) {
+ %bb = load <11 x i128>* %b
+ %tt = xor <11 x i128> %x, %bb
+ store <11 x i128> %tt, <11 x i128>* %b
+ br label %next
+
+next:
+ ret <11 x i128> %tt
+}
+
+
+define <11 x i256> @test_11xi256(<11 x i256> %x, <11 x i256>* %b) {
+ %bb = load <11 x i256>* %b
+ %tt = xor <11 x i256> %x, %bb
+ store <11 x i256> %tt, <11 x i256>* %b
+ br label %next
+
+next:
+ ret <11 x i256> %tt
+}
+
+
+define <11 x i512> @test_11xi512(<11 x i512> %x, <11 x i512>* %b) {
+ %bb = load <11 x i512>* %b
+ %tt = xor <11 x i512> %x, %bb
+ store <11 x i512> %tt, <11 x i512>* %b
+ br label %next
+
+next:
+ ret <11 x i512> %tt
+}
+
+
+define <12 x i8> @test_12xi8(<12 x i8> %x, <12 x i8>* %b) {
+ %bb = load <12 x i8>* %b
+ %tt = xor <12 x i8> %x, %bb
+ store <12 x i8> %tt, <12 x i8>* %b
+ br label %next
+
+next:
+ ret <12 x i8> %tt
+}
+
+
+define <12 x i16> @test_12xi16(<12 x i16> %x, <12 x i16>* %b) {
+ %bb = load <12 x i16>* %b
+ %tt = xor <12 x i16> %x, %bb
+ store <12 x i16> %tt, <12 x i16>* %b
+ br label %next
+
+next:
+ ret <12 x i16> %tt
+}
+
+
+define <12 x i32> @test_12xi32(<12 x i32> %x, <12 x i32>* %b) {
+ %bb = load <12 x i32>* %b
+ %tt = xor <12 x i32> %x, %bb
+ store <12 x i32> %tt, <12 x i32>* %b
+ br label %next
+
+next:
+ ret <12 x i32> %tt
+}
+
+
+define <12 x i64> @test_12xi64(<12 x i64> %x, <12 x i64>* %b) {
+ %bb = load <12 x i64>* %b
+ %tt = xor <12 x i64> %x, %bb
+ store <12 x i64> %tt, <12 x i64>* %b
+ br label %next
+
+next:
+ ret <12 x i64> %tt
+}
+
+
+define <12 x i128> @test_12xi128(<12 x i128> %x, <12 x i128>* %b) {
+ %bb = load <12 x i128>* %b
+ %tt = xor <12 x i128> %x, %bb
+ store <12 x i128> %tt, <12 x i128>* %b
+ br label %next
+
+next:
+ ret <12 x i128> %tt
+}
+
+
+define <12 x i256> @test_12xi256(<12 x i256> %x, <12 x i256>* %b) {
+ %bb = load <12 x i256>* %b
+ %tt = xor <12 x i256> %x, %bb
+ store <12 x i256> %tt, <12 x i256>* %b
+ br label %next
+
+next:
+ ret <12 x i256> %tt
+}
+
+
+define <12 x i512> @test_12xi512(<12 x i512> %x, <12 x i512>* %b) {
+ %bb = load <12 x i512>* %b
+ %tt = xor <12 x i512> %x, %bb
+ store <12 x i512> %tt, <12 x i512>* %b
+ br label %next
+
+next:
+ ret <12 x i512> %tt
+}
+
+
+define <13 x i8> @test_13xi8(<13 x i8> %x, <13 x i8>* %b) {
+ %bb = load <13 x i8>* %b
+ %tt = xor <13 x i8> %x, %bb
+ store <13 x i8> %tt, <13 x i8>* %b
+ br label %next
+
+next:
+ ret <13 x i8> %tt
+}
+
+
+define <13 x i16> @test_13xi16(<13 x i16> %x, <13 x i16>* %b) {
+ %bb = load <13 x i16>* %b
+ %tt = xor <13 x i16> %x, %bb
+ store <13 x i16> %tt, <13 x i16>* %b
+ br label %next
+
+next:
+ ret <13 x i16> %tt
+}
+
+
+define <13 x i32> @test_13xi32(<13 x i32> %x, <13 x i32>* %b) {
+ %bb = load <13 x i32>* %b
+ %tt = xor <13 x i32> %x, %bb
+ store <13 x i32> %tt, <13 x i32>* %b
+ br label %next
+
+next:
+ ret <13 x i32> %tt
+}
+
+
+define <13 x i64> @test_13xi64(<13 x i64> %x, <13 x i64>* %b) {
+ %bb = load <13 x i64>* %b
+ %tt = xor <13 x i64> %x, %bb
+ store <13 x i64> %tt, <13 x i64>* %b
+ br label %next
+
+next:
+ ret <13 x i64> %tt
+}
+
+
+define <13 x i128> @test_13xi128(<13 x i128> %x, <13 x i128>* %b) {
+ %bb = load <13 x i128>* %b
+ %tt = xor <13 x i128> %x, %bb
+ store <13 x i128> %tt, <13 x i128>* %b
+ br label %next
+
+next:
+ ret <13 x i128> %tt
+}
+
+
+define <13 x i256> @test_13xi256(<13 x i256> %x, <13 x i256>* %b) {
+ %bb = load <13 x i256>* %b
+ %tt = xor <13 x i256> %x, %bb
+ store <13 x i256> %tt, <13 x i256>* %b
+ br label %next
+
+next:
+ ret <13 x i256> %tt
+}
+
+
+define <13 x i512> @test_13xi512(<13 x i512> %x, <13 x i512>* %b) {
+ %bb = load <13 x i512>* %b
+ %tt = xor <13 x i512> %x, %bb
+ store <13 x i512> %tt, <13 x i512>* %b
+ br label %next
+
+next:
+ ret <13 x i512> %tt
+}
+
+
+define <14 x i8> @test_14xi8(<14 x i8> %x, <14 x i8>* %b) {
+ %bb = load <14 x i8>* %b
+ %tt = xor <14 x i8> %x, %bb
+ store <14 x i8> %tt, <14 x i8>* %b
+ br label %next
+
+next:
+ ret <14 x i8> %tt
+}
+
+
+define <14 x i16> @test_14xi16(<14 x i16> %x, <14 x i16>* %b) {
+ %bb = load <14 x i16>* %b
+ %tt = xor <14 x i16> %x, %bb
+ store <14 x i16> %tt, <14 x i16>* %b
+ br label %next
+
+next:
+ ret <14 x i16> %tt
+}
+
+
+define <14 x i32> @test_14xi32(<14 x i32> %x, <14 x i32>* %b) {
+ %bb = load <14 x i32>* %b
+ %tt = xor <14 x i32> %x, %bb
+ store <14 x i32> %tt, <14 x i32>* %b
+ br label %next
+
+next:
+ ret <14 x i32> %tt
+}
+
+
+define <14 x i64> @test_14xi64(<14 x i64> %x, <14 x i64>* %b) {
+ %bb = load <14 x i64>* %b
+ %tt = xor <14 x i64> %x, %bb
+ store <14 x i64> %tt, <14 x i64>* %b
+ br label %next
+
+next:
+ ret <14 x i64> %tt
+}
+
+
+define <14 x i128> @test_14xi128(<14 x i128> %x, <14 x i128>* %b) {
+ %bb = load <14 x i128>* %b
+ %tt = xor <14 x i128> %x, %bb
+ store <14 x i128> %tt, <14 x i128>* %b
+ br label %next
+
+next:
+ ret <14 x i128> %tt
+}
+
+
+define <14 x i256> @test_14xi256(<14 x i256> %x, <14 x i256>* %b) {
+ %bb = load <14 x i256>* %b
+ %tt = xor <14 x i256> %x, %bb
+ store <14 x i256> %tt, <14 x i256>* %b
+ br label %next
+
+next:
+ ret <14 x i256> %tt
+}
+
+
+define <14 x i512> @test_14xi512(<14 x i512> %x, <14 x i512>* %b) {
+ %bb = load <14 x i512>* %b
+ %tt = xor <14 x i512> %x, %bb
+ store <14 x i512> %tt, <14 x i512>* %b
+ br label %next
+
+next:
+ ret <14 x i512> %tt
+}
+
+
+define <15 x i8> @test_15xi8(<15 x i8> %x, <15 x i8>* %b) {
+ %bb = load <15 x i8>* %b
+ %tt = xor <15 x i8> %x, %bb
+ store <15 x i8> %tt, <15 x i8>* %b
+ br label %next
+
+next:
+ ret <15 x i8> %tt
+}
+
+
+define <15 x i16> @test_15xi16(<15 x i16> %x, <15 x i16>* %b) {
+ %bb = load <15 x i16>* %b
+ %tt = xor <15 x i16> %x, %bb
+ store <15 x i16> %tt, <15 x i16>* %b
+ br label %next
+
+next:
+ ret <15 x i16> %tt
+}
+
+
+define <15 x i32> @test_15xi32(<15 x i32> %x, <15 x i32>* %b) {
+ %bb = load <15 x i32>* %b
+ %tt = xor <15 x i32> %x, %bb
+ store <15 x i32> %tt, <15 x i32>* %b
+ br label %next
+
+next:
+ ret <15 x i32> %tt
+}
+
+
+define <15 x i64> @test_15xi64(<15 x i64> %x, <15 x i64>* %b) {
+ %bb = load <15 x i64>* %b
+ %tt = xor <15 x i64> %x, %bb
+ store <15 x i64> %tt, <15 x i64>* %b
+ br label %next
+
+next:
+ ret <15 x i64> %tt
+}
+
+
+define <15 x i128> @test_15xi128(<15 x i128> %x, <15 x i128>* %b) {
+ %bb = load <15 x i128>* %b
+ %tt = xor <15 x i128> %x, %bb
+ store <15 x i128> %tt, <15 x i128>* %b
+ br label %next
+
+next:
+ ret <15 x i128> %tt
+}
+
+
+define <15 x i256> @test_15xi256(<15 x i256> %x, <15 x i256>* %b) {
+ %bb = load <15 x i256>* %b
+ %tt = xor <15 x i256> %x, %bb
+ store <15 x i256> %tt, <15 x i256>* %b
+ br label %next
+
+next:
+ ret <15 x i256> %tt
+}
+
+
+define <15 x i512> @test_15xi512(<15 x i512> %x, <15 x i512>* %b) {
+ %bb = load <15 x i512>* %b
+ %tt = xor <15 x i512> %x, %bb
+ store <15 x i512> %tt, <15 x i512>* %b
+ br label %next
+
+next:
+ ret <15 x i512> %tt
+}
+
+
+define <16 x i8> @test_16xi8(<16 x i8> %x, <16 x i8>* %b) {
+ %bb = load <16 x i8>* %b
+ %tt = xor <16 x i8> %x, %bb
+ store <16 x i8> %tt, <16 x i8>* %b
+ br label %next
+
+next:
+ ret <16 x i8> %tt
+}
+
+
+define <16 x i16> @test_16xi16(<16 x i16> %x, <16 x i16>* %b) {
+ %bb = load <16 x i16>* %b
+ %tt = xor <16 x i16> %x, %bb
+ store <16 x i16> %tt, <16 x i16>* %b
+ br label %next
+
+next:
+ ret <16 x i16> %tt
+}
+
+
+define <16 x i32> @test_16xi32(<16 x i32> %x, <16 x i32>* %b) {
+ %bb = load <16 x i32>* %b
+ %tt = xor <16 x i32> %x, %bb
+ store <16 x i32> %tt, <16 x i32>* %b
+ br label %next
+
+next:
+ ret <16 x i32> %tt
+}
+
+
+define <16 x i64> @test_16xi64(<16 x i64> %x, <16 x i64>* %b) {
+ %bb = load <16 x i64>* %b
+ %tt = xor <16 x i64> %x, %bb
+ store <16 x i64> %tt, <16 x i64>* %b
+ br label %next
+
+next:
+ ret <16 x i64> %tt
+}
+
+
+define <16 x i128> @test_16xi128(<16 x i128> %x, <16 x i128>* %b) {
+ %bb = load <16 x i128>* %b
+ %tt = xor <16 x i128> %x, %bb
+ store <16 x i128> %tt, <16 x i128>* %b
+ br label %next
+
+next:
+ ret <16 x i128> %tt
+}
+
+
+define <16 x i256> @test_16xi256(<16 x i256> %x, <16 x i256>* %b) {
+ %bb = load <16 x i256>* %b
+ %tt = xor <16 x i256> %x, %bb
+ store <16 x i256> %tt, <16 x i256>* %b
+ br label %next
+
+next:
+ ret <16 x i256> %tt
+}
+
+
+define <16 x i512> @test_16xi512(<16 x i512> %x, <16 x i512>* %b) {
+ %bb = load <16 x i512>* %b
+ %tt = xor <16 x i512> %x, %bb
+ store <16 x i512> %tt, <16 x i512>* %b
+ br label %next
+
+next:
+ ret <16 x i512> %tt
+}
+
+
+define <17 x i8> @test_17xi8(<17 x i8> %x, <17 x i8>* %b) {
+ %bb = load <17 x i8>* %b
+ %tt = xor <17 x i8> %x, %bb
+ store <17 x i8> %tt, <17 x i8>* %b
+ br label %next
+
+next:
+ ret <17 x i8> %tt
+}
+
+
+define <17 x i16> @test_17xi16(<17 x i16> %x, <17 x i16>* %b) {
+ %bb = load <17 x i16>* %b
+ %tt = xor <17 x i16> %x, %bb
+ store <17 x i16> %tt, <17 x i16>* %b
+ br label %next
+
+next:
+ ret <17 x i16> %tt
+}
+
+
+define <17 x i32> @test_17xi32(<17 x i32> %x, <17 x i32>* %b) {
+ %bb = load <17 x i32>* %b
+ %tt = xor <17 x i32> %x, %bb
+ store <17 x i32> %tt, <17 x i32>* %b
+ br label %next
+
+next:
+ ret <17 x i32> %tt
+}
+
+
+define <17 x i64> @test_17xi64(<17 x i64> %x, <17 x i64>* %b) {
+ %bb = load <17 x i64>* %b
+ %tt = xor <17 x i64> %x, %bb
+ store <17 x i64> %tt, <17 x i64>* %b
+ br label %next
+
+next:
+ ret <17 x i64> %tt
+}
+
+
+define <17 x i128> @test_17xi128(<17 x i128> %x, <17 x i128>* %b) {
+ %bb = load <17 x i128>* %b
+ %tt = xor <17 x i128> %x, %bb
+ store <17 x i128> %tt, <17 x i128>* %b
+ br label %next
+
+next:
+ ret <17 x i128> %tt
+}
+
+
+define <17 x i256> @test_17xi256(<17 x i256> %x, <17 x i256>* %b) {
+ %bb = load <17 x i256>* %b
+ %tt = xor <17 x i256> %x, %bb
+ store <17 x i256> %tt, <17 x i256>* %b
+ br label %next
+
+next:
+ ret <17 x i256> %tt
+}
+
+
+define <17 x i512> @test_17xi512(<17 x i512> %x, <17 x i512>* %b) {
+ %bb = load <17 x i512>* %b
+ %tt = xor <17 x i512> %x, %bb
+ store <17 x i512> %tt, <17 x i512>* %b
+ br label %next
+
+next:
+ ret <17 x i512> %tt
+}
+
+
+define <18 x i8> @test_18xi8(<18 x i8> %x, <18 x i8>* %b) {
+ %bb = load <18 x i8>* %b
+ %tt = xor <18 x i8> %x, %bb
+ store <18 x i8> %tt, <18 x i8>* %b
+ br label %next
+
+next:
+ ret <18 x i8> %tt
+}
+
+
+define <18 x i16> @test_18xi16(<18 x i16> %x, <18 x i16>* %b) {
+ %bb = load <18 x i16>* %b
+ %tt = xor <18 x i16> %x, %bb
+ store <18 x i16> %tt, <18 x i16>* %b
+ br label %next
+
+next:
+ ret <18 x i16> %tt
+}
+
+
+define <18 x i32> @test_18xi32(<18 x i32> %x, <18 x i32>* %b) {
+ %bb = load <18 x i32>* %b
+ %tt = xor <18 x i32> %x, %bb
+ store <18 x i32> %tt, <18 x i32>* %b
+ br label %next
+
+next:
+ ret <18 x i32> %tt
+}
+
+
+define <18 x i64> @test_18xi64(<18 x i64> %x, <18 x i64>* %b) {
+ %bb = load <18 x i64>* %b
+ %tt = xor <18 x i64> %x, %bb
+ store <18 x i64> %tt, <18 x i64>* %b
+ br label %next
+
+next:
+ ret <18 x i64> %tt
+}
+
+
+define <18 x i128> @test_18xi128(<18 x i128> %x, <18 x i128>* %b) {
+ %bb = load <18 x i128>* %b
+ %tt = xor <18 x i128> %x, %bb
+ store <18 x i128> %tt, <18 x i128>* %b
+ br label %next
+
+next:
+ ret <18 x i128> %tt
+}
+
+
+define <18 x i256> @test_18xi256(<18 x i256> %x, <18 x i256>* %b) {
+ %bb = load <18 x i256>* %b
+ %tt = xor <18 x i256> %x, %bb
+ store <18 x i256> %tt, <18 x i256>* %b
+ br label %next
+
+next:
+ ret <18 x i256> %tt
+}
+
+
+define <18 x i512> @test_18xi512(<18 x i512> %x, <18 x i512>* %b) {
+ %bb = load <18 x i512>* %b
+ %tt = xor <18 x i512> %x, %bb
+ store <18 x i512> %tt, <18 x i512>* %b
+ br label %next
+
+next:
+ ret <18 x i512> %tt
+}
+
+
+define <19 x i8> @test_19xi8(<19 x i8> %x, <19 x i8>* %b) {
+ %bb = load <19 x i8>* %b
+ %tt = xor <19 x i8> %x, %bb
+ store <19 x i8> %tt, <19 x i8>* %b
+ br label %next
+
+next:
+ ret <19 x i8> %tt
+}
+
+
+define <19 x i16> @test_19xi16(<19 x i16> %x, <19 x i16>* %b) {
+ %bb = load <19 x i16>* %b
+ %tt = xor <19 x i16> %x, %bb
+ store <19 x i16> %tt, <19 x i16>* %b
+ br label %next
+
+next:
+ ret <19 x i16> %tt
+}
+
+
+define <19 x i32> @test_19xi32(<19 x i32> %x, <19 x i32>* %b) {
+ %bb = load <19 x i32>* %b
+ %tt = xor <19 x i32> %x, %bb
+ store <19 x i32> %tt, <19 x i32>* %b
+ br label %next
+
+next:
+ ret <19 x i32> %tt
+}
+
+
+define <19 x i64> @test_19xi64(<19 x i64> %x, <19 x i64>* %b) {
+ %bb = load <19 x i64>* %b
+ %tt = xor <19 x i64> %x, %bb
+ store <19 x i64> %tt, <19 x i64>* %b
+ br label %next
+
+next:
+ ret <19 x i64> %tt
+}
+
+
+define <19 x i128> @test_19xi128(<19 x i128> %x, <19 x i128>* %b) {
+ %bb = load <19 x i128>* %b
+ %tt = xor <19 x i128> %x, %bb
+ store <19 x i128> %tt, <19 x i128>* %b
+ br label %next
+
+next:
+ ret <19 x i128> %tt
+}
+
+
+define <19 x i256> @test_19xi256(<19 x i256> %x, <19 x i256>* %b) {
+ %bb = load <19 x i256>* %b
+ %tt = xor <19 x i256> %x, %bb
+ store <19 x i256> %tt, <19 x i256>* %b
+ br label %next
+
+next:
+ ret <19 x i256> %tt
+}
+
+
+define <19 x i512> @test_19xi512(<19 x i512> %x, <19 x i512>* %b) {
+ %bb = load <19 x i512>* %b
+ %tt = xor <19 x i512> %x, %bb
+ store <19 x i512> %tt, <19 x i512>* %b
+ br label %next
+
+next:
+ ret <19 x i512> %tt
+}
+
From nadav.rotem at intel.com Tue Jun 14 04:10:37 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Tue, 14 Jun 2011 09:10:37 -0000
Subject: [llvm-commits] [llvm] r132986 -
/llvm/trunk/test/CodeGen/X86/mem-promote-integers.ll
Message-ID: <20110614091037.6F59B2A6C12C@llvm.org>
Author: nadav
Date: Tue Jun 14 04:10:37 2011
New Revision: 132986
URL: http://llvm.org/viewvc/llvm-project?rev=132986&view=rev
Log:
This testcase cause a failure on some bots. Remove the failing test until
further investigation.
Modified:
llvm/trunk/test/CodeGen/X86/mem-promote-integers.ll
Modified: llvm/trunk/test/CodeGen/X86/mem-promote-integers.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/mem-promote-integers.ll?rev=132986&r1=132985&r2=132986&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/mem-promote-integers.ll (original)
+++ llvm/trunk/test/CodeGen/X86/mem-promote-integers.ll Tue Jun 14 04:10:37 2011
@@ -69,17 +69,6 @@
}
-define <1 x i512> @test_1xi512(<1 x i512> %x, <1 x i512>* %b) {
- %bb = load <1 x i512>* %b
- %tt = xor <1 x i512> %x, %bb
- store <1 x i512> %tt, <1 x i512>* %b
- br label %next
-
-next:
- ret <1 x i512> %tt
-}
-
-
define <2 x i8> @test_2xi8(<2 x i8> %x, <2 x i8>* %b) {
%bb = load <2 x i8>* %b
%tt = xor <2 x i8> %x, %bb
@@ -146,17 +135,6 @@
}
-define <2 x i512> @test_2xi512(<2 x i512> %x, <2 x i512>* %b) {
- %bb = load <2 x i512>* %b
- %tt = xor <2 x i512> %x, %bb
- store <2 x i512> %tt, <2 x i512>* %b
- br label %next
-
-next:
- ret <2 x i512> %tt
-}
-
-
define <3 x i8> @test_3xi8(<3 x i8> %x, <3 x i8>* %b) {
%bb = load <3 x i8>* %b
%tt = xor <3 x i8> %x, %bb
@@ -223,17 +201,6 @@
}
-define <3 x i512> @test_3xi512(<3 x i512> %x, <3 x i512>* %b) {
- %bb = load <3 x i512>* %b
- %tt = xor <3 x i512> %x, %bb
- store <3 x i512> %tt, <3 x i512>* %b
- br label %next
-
-next:
- ret <3 x i512> %tt
-}
-
-
define <4 x i8> @test_4xi8(<4 x i8> %x, <4 x i8>* %b) {
%bb = load <4 x i8>* %b
%tt = xor <4 x i8> %x, %bb
@@ -300,17 +267,6 @@
}
-define <4 x i512> @test_4xi512(<4 x i512> %x, <4 x i512>* %b) {
- %bb = load <4 x i512>* %b
- %tt = xor <4 x i512> %x, %bb
- store <4 x i512> %tt, <4 x i512>* %b
- br label %next
-
-next:
- ret <4 x i512> %tt
-}
-
-
define <5 x i8> @test_5xi8(<5 x i8> %x, <5 x i8>* %b) {
%bb = load <5 x i8>* %b
%tt = xor <5 x i8> %x, %bb
@@ -377,17 +333,6 @@
}
-define <5 x i512> @test_5xi512(<5 x i512> %x, <5 x i512>* %b) {
- %bb = load <5 x i512>* %b
- %tt = xor <5 x i512> %x, %bb
- store <5 x i512> %tt, <5 x i512>* %b
- br label %next
-
-next:
- ret <5 x i512> %tt
-}
-
-
define <6 x i8> @test_6xi8(<6 x i8> %x, <6 x i8>* %b) {
%bb = load <6 x i8>* %b
%tt = xor <6 x i8> %x, %bb
@@ -454,17 +399,6 @@
}
-define <6 x i512> @test_6xi512(<6 x i512> %x, <6 x i512>* %b) {
- %bb = load <6 x i512>* %b
- %tt = xor <6 x i512> %x, %bb
- store <6 x i512> %tt, <6 x i512>* %b
- br label %next
-
-next:
- ret <6 x i512> %tt
-}
-
-
define <7 x i8> @test_7xi8(<7 x i8> %x, <7 x i8>* %b) {
%bb = load <7 x i8>* %b
%tt = xor <7 x i8> %x, %bb
@@ -531,17 +465,6 @@
}
-define <7 x i512> @test_7xi512(<7 x i512> %x, <7 x i512>* %b) {
- %bb = load <7 x i512>* %b
- %tt = xor <7 x i512> %x, %bb
- store <7 x i512> %tt, <7 x i512>* %b
- br label %next
-
-next:
- ret <7 x i512> %tt
-}
-
-
define <8 x i8> @test_8xi8(<8 x i8> %x, <8 x i8>* %b) {
%bb = load <8 x i8>* %b
%tt = xor <8 x i8> %x, %bb
@@ -608,17 +531,6 @@
}
-define <8 x i512> @test_8xi512(<8 x i512> %x, <8 x i512>* %b) {
- %bb = load <8 x i512>* %b
- %tt = xor <8 x i512> %x, %bb
- store <8 x i512> %tt, <8 x i512>* %b
- br label %next
-
-next:
- ret <8 x i512> %tt
-}
-
-
define <9 x i8> @test_9xi8(<9 x i8> %x, <9 x i8>* %b) {
%bb = load <9 x i8>* %b
%tt = xor <9 x i8> %x, %bb
@@ -685,17 +597,6 @@
}
-define <9 x i512> @test_9xi512(<9 x i512> %x, <9 x i512>* %b) {
- %bb = load <9 x i512>* %b
- %tt = xor <9 x i512> %x, %bb
- store <9 x i512> %tt, <9 x i512>* %b
- br label %next
-
-next:
- ret <9 x i512> %tt
-}
-
-
define <10 x i8> @test_10xi8(<10 x i8> %x, <10 x i8>* %b) {
%bb = load <10 x i8>* %b
%tt = xor <10 x i8> %x, %bb
@@ -762,17 +663,6 @@
}
-define <10 x i512> @test_10xi512(<10 x i512> %x, <10 x i512>* %b) {
- %bb = load <10 x i512>* %b
- %tt = xor <10 x i512> %x, %bb
- store <10 x i512> %tt, <10 x i512>* %b
- br label %next
-
-next:
- ret <10 x i512> %tt
-}
-
-
define <11 x i8> @test_11xi8(<11 x i8> %x, <11 x i8>* %b) {
%bb = load <11 x i8>* %b
%tt = xor <11 x i8> %x, %bb
@@ -839,17 +729,6 @@
}
-define <11 x i512> @test_11xi512(<11 x i512> %x, <11 x i512>* %b) {
- %bb = load <11 x i512>* %b
- %tt = xor <11 x i512> %x, %bb
- store <11 x i512> %tt, <11 x i512>* %b
- br label %next
-
-next:
- ret <11 x i512> %tt
-}
-
-
define <12 x i8> @test_12xi8(<12 x i8> %x, <12 x i8>* %b) {
%bb = load <12 x i8>* %b
%tt = xor <12 x i8> %x, %bb
@@ -916,17 +795,6 @@
}
-define <12 x i512> @test_12xi512(<12 x i512> %x, <12 x i512>* %b) {
- %bb = load <12 x i512>* %b
- %tt = xor <12 x i512> %x, %bb
- store <12 x i512> %tt, <12 x i512>* %b
- br label %next
-
-next:
- ret <12 x i512> %tt
-}
-
-
define <13 x i8> @test_13xi8(<13 x i8> %x, <13 x i8>* %b) {
%bb = load <13 x i8>* %b
%tt = xor <13 x i8> %x, %bb
@@ -993,17 +861,6 @@
}
-define <13 x i512> @test_13xi512(<13 x i512> %x, <13 x i512>* %b) {
- %bb = load <13 x i512>* %b
- %tt = xor <13 x i512> %x, %bb
- store <13 x i512> %tt, <13 x i512>* %b
- br label %next
-
-next:
- ret <13 x i512> %tt
-}
-
-
define <14 x i8> @test_14xi8(<14 x i8> %x, <14 x i8>* %b) {
%bb = load <14 x i8>* %b
%tt = xor <14 x i8> %x, %bb
@@ -1070,17 +927,6 @@
}
-define <14 x i512> @test_14xi512(<14 x i512> %x, <14 x i512>* %b) {
- %bb = load <14 x i512>* %b
- %tt = xor <14 x i512> %x, %bb
- store <14 x i512> %tt, <14 x i512>* %b
- br label %next
-
-next:
- ret <14 x i512> %tt
-}
-
-
define <15 x i8> @test_15xi8(<15 x i8> %x, <15 x i8>* %b) {
%bb = load <15 x i8>* %b
%tt = xor <15 x i8> %x, %bb
@@ -1147,17 +993,6 @@
}
-define <15 x i512> @test_15xi512(<15 x i512> %x, <15 x i512>* %b) {
- %bb = load <15 x i512>* %b
- %tt = xor <15 x i512> %x, %bb
- store <15 x i512> %tt, <15 x i512>* %b
- br label %next
-
-next:
- ret <15 x i512> %tt
-}
-
-
define <16 x i8> @test_16xi8(<16 x i8> %x, <16 x i8>* %b) {
%bb = load <16 x i8>* %b
%tt = xor <16 x i8> %x, %bb
@@ -1224,17 +1059,6 @@
}
-define <16 x i512> @test_16xi512(<16 x i512> %x, <16 x i512>* %b) {
- %bb = load <16 x i512>* %b
- %tt = xor <16 x i512> %x, %bb
- store <16 x i512> %tt, <16 x i512>* %b
- br label %next
-
-next:
- ret <16 x i512> %tt
-}
-
-
define <17 x i8> @test_17xi8(<17 x i8> %x, <17 x i8>* %b) {
%bb = load <17 x i8>* %b
%tt = xor <17 x i8> %x, %bb
@@ -1301,17 +1125,6 @@
}
-define <17 x i512> @test_17xi512(<17 x i512> %x, <17 x i512>* %b) {
- %bb = load <17 x i512>* %b
- %tt = xor <17 x i512> %x, %bb
- store <17 x i512> %tt, <17 x i512>* %b
- br label %next
-
-next:
- ret <17 x i512> %tt
-}
-
-
define <18 x i8> @test_18xi8(<18 x i8> %x, <18 x i8>* %b) {
%bb = load <18 x i8>* %b
%tt = xor <18 x i8> %x, %bb
@@ -1378,17 +1191,6 @@
}
-define <18 x i512> @test_18xi512(<18 x i512> %x, <18 x i512>* %b) {
- %bb = load <18 x i512>* %b
- %tt = xor <18 x i512> %x, %bb
- store <18 x i512> %tt, <18 x i512>* %b
- br label %next
-
-next:
- ret <18 x i512> %tt
-}
-
-
define <19 x i8> @test_19xi8(<19 x i8> %x, <19 x i8>* %b) {
%bb = load <19 x i8>* %b
%tt = xor <19 x i8> %x, %bb
@@ -1455,13 +1257,3 @@
}
-define <19 x i512> @test_19xi512(<19 x i512> %x, <19 x i512>* %b) {
- %bb = load <19 x i512>* %b
- %tt = xor <19 x i512> %x, %bb
- store <19 x i512> %tt, <19 x i512>* %b
- br label %next
-
-next:
- ret <19 x i512> %tt
-}
-
From baldrick at free.fr Tue Jun 14 06:17:07 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 14 Jun 2011 11:17:07 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r132987 -
/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Message-ID: <20110614111707.18A5F2A6C12C@llvm.org>
Author: baldrick
Date: Tue Jun 14 06:17:06 2011
New Revision: 132987
URL: http://llvm.org/viewvc/llvm-project?rev=132987&view=rev
Log:
Port commit 132977 (prefetch intrinsic gained a new argument) from
clang. Compiles but otherwise untested.
Modified:
llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
Modified: llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp?rev=132987&r1=132986&r2=132987&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-convert.cpp Tue Jun 14 06:17:06 2011
@@ -6513,9 +6513,10 @@
Ptr = BitCastToType(Ptr, Type::getInt8PtrTy(Context));
- Value *Ops[3] = { Ptr, ReadWrite, Locality };
- Builder.CreateCall(Intrinsic::getDeclaration(TheModule, Intrinsic::prefetch),
- Ops, Ops+3);
+ Value *Data = ConstantInt::get(Type::getInt32Ty(Context), 1);
+
+ Builder.CreateCall4(Intrinsic::getDeclaration(TheModule, Intrinsic::prefetch),
+ Ptr, ReadWrite, Locality, Data);
return true;
}
From rafael.espindola at gmail.com Tue Jun 14 07:48:26 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Tue, 14 Jun 2011 12:48:26 -0000
Subject: [llvm-commits] [llvm] r132988 - in /llvm/trunk:
lib/CodeGen/BranchFolding.cpp lib/CodeGen/BranchFolding.h
test/CodeGen/X86/tail-threshold.ll
Message-ID: <20110614124826.9BBB02A6C12C@llvm.org>
Author: rafael
Date: Tue Jun 14 07:48:26 2011
New Revision: 132988
URL: http://llvm.org/viewvc/llvm-project?rev=132988&view=rev
Log:
revert 132986 to see if the bots go green.
Removed:
llvm/trunk/test/CodeGen/X86/tail-threshold.ll
Modified:
llvm/trunk/lib/CodeGen/BranchFolding.cpp
llvm/trunk/lib/CodeGen/BranchFolding.h
Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=132988&r1=132987&r2=132988&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Jun 14 07:48:26 2011
@@ -799,22 +799,14 @@
// First find blocks with no successors.
MergePotentials.clear();
- for (MachineFunction::iterator I = MF.begin(), E = MF.end();
- I != E && MergePotentials.size() < TailMergeThreshold; ++I) {
- if (TriedMerging.count(I))
- continue;
+ for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
if (I->succ_empty())
MergePotentials.push_back(MergePotentialsElt(HashEndOfMBB(I), I));
}
- // If this is a large problem, avoid visiting the same basic blocks
- // multiple times.
- if (MergePotentials.size() == TailMergeThreshold)
- for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i)
- TriedMerging.insert(MergePotentials[i].getBlock());
-
// See if we can do any tail merging on those.
- if (MergePotentials.size() >= 2)
+ if (MergePotentials.size() < TailMergeThreshold &&
+ MergePotentials.size() >= 2)
MadeChange |= TryTailMergeBlocks(NULL, NULL);
// Look at blocks (IBB) with multiple predecessors (PBB).
@@ -838,17 +830,15 @@
for (MachineFunction::iterator I = llvm::next(MF.begin()), E = MF.end();
I != E; ++I) {
- if (I->pred_size() >= 2) {
+ if (I->pred_size() >= 2 && I->pred_size() < TailMergeThreshold) {
SmallPtrSet UniquePreds;
MachineBasicBlock *IBB = I;
MachineBasicBlock *PredBB = prior(I);
MergePotentials.clear();
for (MachineBasicBlock::pred_iterator P = I->pred_begin(),
E2 = I->pred_end();
- P != E2 && MergePotentials.size() < TailMergeThreshold; ++P) {
+ P != E2; ++P) {
MachineBasicBlock *PBB = *P;
- if (TriedMerging.count(PBB))
- continue;
// Skip blocks that loop to themselves, can't tail merge these.
if (PBB == IBB)
continue;
@@ -901,12 +891,6 @@
MergePotentials.push_back(MergePotentialsElt(HashEndOfMBB(PBB), *P));
}
}
- // If this is a large problem, avoid visiting the same basic blocks
- // multiple times.
- if (MergePotentials.size() == TailMergeThreshold)
- for (unsigned i = 0, e = MergePotentials.size(); i != e; ++i)
- TriedMerging.insert(MergePotentials[i].getBlock());
-
if (MergePotentials.size() >= 2)
MadeChange |= TryTailMergeBlocks(IBB, PredBB);
// Reinsert an unconditional branch if needed.
Modified: llvm/trunk/lib/CodeGen/BranchFolding.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.h?rev=132988&r1=132987&r2=132988&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/BranchFolding.h (original)
+++ llvm/trunk/lib/CodeGen/BranchFolding.h Tue Jun 14 07:48:26 2011
@@ -10,7 +10,6 @@
#ifndef LLVM_CODEGEN_BRANCHFOLDING_HPP
#define LLVM_CODEGEN_BRANCHFOLDING_HPP
-#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include
@@ -48,7 +47,6 @@
};
typedef std::vector::iterator MPIterator;
std::vector MergePotentials;
- SmallPtrSet TriedMerging;
class SameTailElt {
MPIterator MPIter;
Removed: llvm/trunk/test/CodeGen/X86/tail-threshold.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-threshold.ll?rev=132987&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-threshold.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tail-threshold.ll (removed)
@@ -1,41 +0,0 @@
-; RUN: llc %s -stats -tail-merge-threshold 2 -o /dev/null |& FileCheck %s
-
-; Test that we still do some merging if a block has more than
-; tail-merge-threshold predecessors.
-
-; CHECK: 2 branchfolding - Number of block tails merged
-
-declare void @bar()
-
-define void @foo(i32 %xxx) {
-entry:
- switch i32 %xxx, label %bb4 [
- i32 0, label %bb0
- i32 1, label %bb1
- i32 2, label %bb2
- i32 3, label %bb3
- ]
-
-bb0:
- call void @bar()
- br label %bb5
-
-bb1:
- call void @bar()
- br label %bb5
-
-bb2:
- call void @bar()
- br label %bb5
-
-bb3:
- call void @bar()
- br label %bb5
-
-bb4:
- call void @bar()
- br label %bb5
-
-bb5:
- ret void
-}
From nadav.rotem at intel.com Tue Jun 14 08:23:10 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Tue, 14 Jun 2011 13:23:10 -0000
Subject: [llvm-commits] [llvm] r132991 -
/llvm/trunk/test/CodeGen/X86/4char-promote.ll
Message-ID: <20110614132310.78A662A6C12C@llvm.org>
Author: nadav
Date: Tue Jun 14 08:23:10 2011
New Revision: 132991
URL: http://llvm.org/viewvc/llvm-project?rev=132991&view=rev
Log:
Add a testcase for #9623
Added:
llvm/trunk/test/CodeGen/X86/4char-promote.ll
Added: llvm/trunk/test/CodeGen/X86/4char-promote.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/4char-promote.ll?rev=132991&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/4char-promote.ll (added)
+++ llvm/trunk/test/CodeGen/X86/4char-promote.ll Tue Jun 14 08:23:10 2011
@@ -0,0 +1,16 @@
+; A test for checking PR 9623
+;RUN: llc -march=x86-64 -promote-elements < %s | FileCheck %s
+
+
+; CHECK: pmulld
+; CHECK: paddd
+; CHECK: movdqa
+
+define <4 x i8> @foo(<4 x i8> %x, <4 x i8> %y) {
+entry:
+ %binop = mul <4 x i8> %x, %y
+ %binop6 = add <4 x i8> %binop, %x
+ ret <4 x i8> %binop6
+}
+
+
From aggarwa4 at illinois.edu Tue Jun 14 09:44:26 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 14 Jun 2011 14:44:26 -0000
Subject: [llvm-commits] [poolalloc] r132992 - in /poolalloc/trunk:
include/assistDS/SimplifyLoad.h lib/AssistDS/SimplifyLoad.cpp
Message-ID: <20110614144426.2D9492A6C12C@llvm.org>
Author: aggarwa4
Date: Tue Jun 14 09:44:26 2011
New Revision: 132992
URL: http://llvm.org/viewvc/llvm-project?rev=132992&view=rev
Log:
Simplify some special cases.
Added:
poolalloc/trunk/include/assistDS/SimplifyLoad.h
poolalloc/trunk/lib/AssistDS/SimplifyLoad.cpp
Added: poolalloc/trunk/include/assistDS/SimplifyLoad.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/SimplifyLoad.h?rev=132992&view=auto
==============================================================================
--- poolalloc/trunk/include/assistDS/SimplifyLoad.h (added)
+++ poolalloc/trunk/include/assistDS/SimplifyLoad.h Tue Jun 14 09:44:26 2011
@@ -0,0 +1,29 @@
+//===--------------- SimplifyLoad.cpp - Simplify load insts ---------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Derived from InstCombine
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Instructions.h"
+#include "llvm/Module.h"
+#include "llvm/Pass.h"
+
+namespace llvm {
+ //
+ // Class: SimplifyLoad
+ //
+ class SimplifyLoad : public ModulePass {
+ public:
+ static char ID;
+ SimplifyLoad() : ModulePass(&ID) {}
+ virtual bool runOnModule(Module& M);
+ };
+}
+
Added: poolalloc/trunk/lib/AssistDS/SimplifyLoad.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/SimplifyLoad.cpp?rev=132992&view=auto
==============================================================================
--- poolalloc/trunk/lib/AssistDS/SimplifyLoad.cpp (added)
+++ poolalloc/trunk/lib/AssistDS/SimplifyLoad.cpp Tue Jun 14 09:44:26 2011
@@ -0,0 +1,90 @@
+//===--------------- SimplifyLoad.cpp - Simplify load insts ---------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+// Derived from InstCombine
+//
+//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "simplifyload"
+
+#include "assistDS/SimplifyLoad.h"
+#include "llvm/Transforms/Utils/Cloning.h"
+#include "llvm/ADT/Statistic.h"
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/PatternMatch.h"
+#include "llvm/Target/TargetData.h"
+
+#include
+#include