[llvm-commits] [llvm] r133022 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/shl_undef.ll
clattner at apple.com
Thu Jun 16 12:28:34 CDT 2011
On Jun 16, 2011, at 2:23 AM, Jay Foad wrote:
>> When pattern matching during instruction selection make sure shl x,1 is not
>> converted to add x,x if x is a undef. add undef, undef does not guarantee
>> that the resulting low order bit is zero.
> IMO it would be better to change the Lang Ref so that the result of
> "shl undef, 1" is undef.
If we did that, we wouldn't be able to implement bitfields correctly. Inserting a value into an uninit bitfield requires shifts, and, or etc to be defined on the bits that are well specified.
> So according to the LLVM Language Reference Manual, "shl x, 1" and
> "mul x, 2" are both guaranteed to have the bottom bit zero. This seems
> like a horrible burden on the optimizers, if they are not allowed to
> freely convert between "add x, x" and "mul x, 2".
Eli's question is about codegen level issue, not an IR level issue. In IR, we always canonicalize "add x,x" -> "shl", and "mul x,2" -> "shl", so I don't see the issue here.
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