From pichet2000 at gmail.com  Mon Jun 20 00:19:38 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Mon, 20 Jun 2011 05:19:38 -0000
Subject: [llvm-commits] [llvm] r133416 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
Message-ID: <20110620051938.26D432A6C12C@llvm.org>

Author: fpichet
Date: Mon Jun 20 00:19:37 2011
New Revision: 133416

URL: http://llvm.org/viewvc/llvm-project?rev=133416&view=rev
Log:
Fix MSVC build. next() function already exists in the MSVC headers. This create a overload conflict. Make sure we pick up the llvm one.

Modified:
    llvm/trunk/lib/CodeGen/TailDuplication.cpp

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133416&r1=133415&r2=133416&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Mon Jun 20 00:19:37 2011
@@ -635,7 +635,7 @@
                  << "From simple Succ: " << *TailBB);
 
     MachineBasicBlock *NewTarget = *TailBB->succ_begin();
-    MachineBasicBlock *NextBB = next(MachineFunction::iterator(PredBB));
+    MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(PredBB));
 
     DenseMap<unsigned, unsigned> LocalVRMap;
     SmallVector<std::pair<unsigned,unsigned>, 4> CopyInfos;



From pichet2000 at gmail.com  Mon Jun 20 00:30:21 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Mon, 20 Jun 2011 01:30:21 -0400
Subject: [llvm-commits] [llvm] r133415 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
In-Reply-To: <20110620041635.302E52A6C12C@llvm.org>
References: <20110620041635.302E52A6C12C@llvm.org>
Message-ID: <BANLkTik_Nm29Baq53Cq5e=aW2Wp5yLubAA@mail.gmail.com>

On Mon, Jun 20, 2011 at 12:16 AM, Rafael Espindola
<rafael.espindola at gmail.com> wrote:
> Author: rafael
> Date: Sun Jun 19 23:16:35 2011
> New Revision: 133415
>
> URL: http://llvm.org/viewvc/llvm-project?rev=133415&view=rev
> Log:
> Teach early dup how to duplicate basic blocks with one successor and only phi instructions
> into more complex blocks.
>
> Modified:
> ? ?llvm/trunk/lib/CodeGen/TailDuplication.cpp
>
> Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133415&r1=133414&r2=133415&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
> +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Sun Jun 19 23:16:35 2011
> @@ -96,6 +96,12 @@
> ? ? bool TailDuplicateBlocks(MachineFunction &MF);
> ? ? bool shouldTailDuplicate(const MachineFunction &MF,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineBasicBlock &TailBB);
> + ? ?bool isSimpleBB(MachineBasicBlock *TailBB);
> + ? ?bool canCompletelyDuplicateSimpleBB(MachineBasicBlock &BB);
> + ? ?bool duplicateSimpleBB(MachineBasicBlock *TailBB,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? SmallVector<MachineBasicBlock*, 8> &TDBBs,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? const DenseSet<unsigned> &RegsUsedByPhi,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? SmallVector<MachineInstr*, 16> &Copies);
> ? ? bool TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF,
> ? ? ? ? ? ? ? ? ? ? ? ?SmallVector<MachineBasicBlock*, 8> &TDBBs,
> ? ? ? ? ? ? ? ? ? ? ? ?SmallVector<MachineInstr*, 16> &Copies);
> @@ -557,6 +563,136 @@
> ? return true;
> ?}
>
> +/// isSimpleBB - True if this BB has only one unconditional jump.
> +bool
> +TailDuplicatePass::isSimpleBB(MachineBasicBlock *TailBB) {
> + ?if (TailBB->succ_size() != 1)
> + ? ?return false;
> + ?MachineBasicBlock::iterator I = TailBB->getFirstNonPHI();
> + ?MachineBasicBlock::iterator E = TailBB->end();
> + ?while (I->isDebugValue() && I != E)
> + ? ?++I;
> + ?if (I == E)
> + ? ?return true;
> + ?return I->getDesc().isUnconditionalBranch();
> +}
> +
> +static bool
> +bothUsedInPHI(const MachineBasicBlock &A,
> + ? ? ? ? ? ? ?SmallPtrSet<MachineBasicBlock*, 8> SuccsB) {
> + ?for (MachineBasicBlock::const_succ_iterator SI = A.succ_begin(),
> + ? ? ? ? SE = A.succ_end(); SI != SE; ++SI) {
> + ? ?MachineBasicBlock *BB = *SI;
> + ? ?if (SuccsB.count(BB) && !BB->empty() && BB->begin()->isPHI())
> + ? ? ?return true;
> + ?}
> +
> + ?return false;
> +}
> +
> +bool
> +TailDuplicatePass::canCompletelyDuplicateSimpleBB(MachineBasicBlock &BB) {
> + ?SmallPtrSet<MachineBasicBlock*, 8> Succs(BB.succ_begin(), BB.succ_end());
> +
> + ?for (MachineBasicBlock::pred_iterator PI = BB.pred_begin(),
> + ? ? ? PE = BB.pred_end(); PI != PE; ++PI) {
> + ? ?MachineBasicBlock *PredBB = *PI;
> + ? ?if (PredBB->getLandingPadSuccessor())
> + ? ? ?return false;
> + ? ?if (bothUsedInPHI(*PredBB, Succs))
> + ? ? ?return false;
> + ? ?MachineBasicBlock *PredTBB = NULL, *PredFBB = NULL;
> + ? ?SmallVector<MachineOperand, 4> PredCond;
> + ? ?if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
> + ? ? ?return false;
> + ?}
> + ?return true;
> +}
> +
> +bool
> +TailDuplicatePass::duplicateSimpleBB(MachineBasicBlock *TailBB,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SmallVector<MachineBasicBlock*, 8> &TDBBs,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? const DenseSet<unsigned> &UsedByPhi,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SmallVector<MachineInstr*, 16> &Copies) {
> + ?if (!canCompletelyDuplicateSimpleBB(*TailBB))
> + ? ?return false;
> +
> + ?bool Changed = false;
> + ?SmallVector<MachineBasicBlock*, 8> Preds(TailBB->pred_begin(),
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TailBB->pred_end());
> + ?for (SmallSetVector<MachineBasicBlock *, 8>::iterator PI = Preds.begin(),
> + ? ? ? PE = Preds.end(); PI != PE; ++PI) {
> + ? ?MachineBasicBlock *PredBB = *PI;
> +
> + ? ?MachineBasicBlock *PredTBB = NULL, *PredFBB = NULL;
> + ? ?SmallVector<MachineOperand, 4> PredCond;
> + ? ?bool NotAnalyzable =
> + ? ? ?TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true);
> + ? ?(void)NotAnalyzable;
> + ? ?assert(!NotAnalyzable && "Cannot duplicate this!");
> +
> + ? ?DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
> + ? ? ? ? ? ? ? ? << "From simple Succ: " << *TailBB);
> +
> + ? ?MachineBasicBlock *NewTarget = *TailBB->succ_begin();
> + ? ?MachineBasicBlock *NextBB = next(MachineFunction::iterator(PredBB));

Hi,
I made a small change here for MSVC compatibility, See r133416


From nadav.rotem at intel.com  Mon Jun 20 02:15:58 2011
From: nadav.rotem at intel.com (Nadav Rotem)
Date: Mon, 20 Jun 2011 07:15:58 -0000
Subject: [llvm-commits] [llvm] r133424 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
 test/CodeGen/X86/promote-trunc.ll
Message-ID: <20110620071558.D31AE2A6C12C@llvm.org>

Author: nadav
Date: Mon Jun 20 02:15:58 2011
New Revision: 133424

URL: http://llvm.org/viewvc/llvm-project?rev=133424&view=rev
Log:
Fix PromoteIntRes_TRUNCATE: Add support for cases where the
source vector type is to be split while the target vector is to be promoted.
(eg: <4 x i64> -> <4 x i8> )

Added:
    llvm/trunk/test/CodeGen/X86/promote-trunc.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp?rev=133424&r1=133423&r2=133424&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp Mon Jun 20 02:15:58 2011
@@ -520,20 +520,44 @@
 SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   SDValue Res;
+  SDValue InOp = N->getOperand(0);
+  DebugLoc dl = N->getDebugLoc();
 
-  switch (getTypeAction(N->getOperand(0).getValueType())) {
+  switch (getTypeAction(InOp.getValueType())) {
   default: llvm_unreachable("Unknown type action!");
   case TargetLowering::TypeLegal:
   case TargetLowering::TypeExpandInteger:
-    Res = N->getOperand(0);
+    Res = InOp;
     break;
   case TargetLowering::TypePromoteInteger:
-    Res = GetPromotedInteger(N->getOperand(0));
+    Res = GetPromotedInteger(InOp);
     break;
+  case TargetLowering::TypeSplitVector:
+    EVT InVT = InOp.getValueType();
+    assert(InVT.isVector() && "Cannot split scalar types");
+    unsigned NumElts = InVT.getVectorNumElements();
+    assert(NumElts == NVT.getVectorNumElements() &&
+           "Dst and Src must have the same number of elements");
+    EVT EltVT = InVT.getScalarType();
+    assert(isPowerOf2_32(NumElts) &&
+           "Promoted vector type must be a power of two");
+
+    EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), EltVT, NumElts/2);
+    EVT HalfNVT = EVT::getVectorVT(*DAG.getContext(), NVT.getScalarType(),
+                                   NumElts/2);
+
+    SDValue EOp1 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
+                               DAG.getIntPtrConstant(0));
+    SDValue EOp2 = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HalfVT, InOp,
+                               DAG.getIntPtrConstant(NumElts/2));
+    EOp1 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp1);
+    EOp2 = DAG.getNode(ISD::TRUNCATE, dl, HalfNVT, EOp2);
+
+    return DAG.getNode(ISD::CONCAT_VECTORS, dl, NVT, EOp1, EOp2);
   }
 
   // Truncate to NVT instead of VT
-  return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), NVT, Res);
+  return DAG.getNode(ISD::TRUNCATE, dl, NVT, Res);
 }
 
 SDValue DAGTypeLegalizer::PromoteIntRes_UADDSUBO(SDNode *N, unsigned ResNo) {

Added: llvm/trunk/test/CodeGen/X86/promote-trunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/promote-trunc.ll?rev=133424&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/promote-trunc.ll (added)
+++ llvm/trunk/test/CodeGen/X86/promote-trunc.ll Mon Jun 20 02:15:58 2011
@@ -0,0 +1,11 @@
+; RUN: llc -promote-elements < %s -march=x86-64
+
+define<4 x i8> @func_8_64() {
+  %F = load <4 x i64>* undef
+  %G = trunc <4 x i64> %F to <4 x i8>
+  %H = load <4 x i64>* undef
+  %Y = trunc <4 x i64> %H to <4 x i8>
+  %T = add <4 x i8> %Y, %G
+  ret <4 x i8> %T
+}
+



From baldrick at free.fr  Mon Jun 20 02:29:30 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 20 Jun 2011 09:29:30 +0200
Subject: [llvm-commits] [llvm] r133285	-
	/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp
In-Reply-To: <54E09593-01A1-4936-AFF8-7AF19D2C6919@apple.com>
References: <20110617202152.D6B812A6C12C@llvm.org> <4DFDF276.5030703@free.fr>
	<54E09593-01A1-4936-AFF8-7AF19D2C6919@apple.com>
Message-ID: <4DFEF6DA.4030503@free.fr>

Hi John,

> On Jun 19, 2011, at 5:58 AM, Duncan Sands wrote:
>>> +  // Insist that the amount-to-allocate not overflow.
>>> +  OverflowingBinaryOperator *OBI = dyn_cast<OverflowingBinaryOperator>(Val);
>>> +  if (OBI&&   !OBI->hasNoUnsignedWrap()) return 0;
>>
>> I noticed you dropped the test for NSW.  I thought this was a problem because
>> front-ends generally don't ever produce NUW, though they may produce NSW...
>
> Stuart asked me to look at this, and I gave him a quick answer
> that it's generally correct for nuw arithmetic, but that I wasn't as
> certain for nsw arithmetic.  Now I think it's probably fine for either
> as long as it's homogenous throughout.
>
> The main restriction on the alloca size argument can be expressed as:
>    (N * sizeof(T)) udiv sizeof(T) == N
> However, there's a second restriction, which is that it's undefined
> behavior to allocate something too large for the stack.  Technically
> this is target-specific, but if we just assume by fiat that 2^31 is too large,
> then as long as the arithmetic is being done in some reasonable size
> then we know that N * sizeof(T) isn't permitted to signed overflow, either.

if you are willing to assume that then you don't need to check for nuw either...
I think I saw some GCC testcases fly by in which people were allocating stack
objects larger than 2^32, so I'm not sure that "N * sizeof(T) < 2^31" is a
reasonable assumption...

About nsw: if you assume than N and sizeof(T) are both less than 2^31, then they
are non-negative as signed numbers.  If you have the nsw flag then you know that
(N * sizeof(T)) is non-negative as a signed number.  This implies that there was
no unsigned wrap either, so all is OK.  I'm willing to assume that sizeof(T) is
less than 2^31, but I'm not sure about N.

Ciao, Duncan.

From baldrick at free.fr  Mon Jun 20 02:43:10 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 20 Jun 2011 07:43:10 -0000
Subject: [llvm-commits] [dragonegg] r133427 - in /dragonegg/trunk: Makefile
 README extras/do_self_strap gcc-patches/ www/index.html
Message-ID: <20110620074311.1AA7B2A6C12D@llvm.org>

Author: baldrick
Date: Mon Jun 20 02:43:10 2011
New Revision: 133427

URL: http://llvm.org/viewvc/llvm-project?rev=133427&view=rev
Log:
Dragonegg no longer requires a patched version of gcc.  Update the docs
to reflect that.  Also, change the Makefile so that it defaults to
building for "gcc" rather than "gcc-4.5".  Use the GCC variable to
override as explained in the README.

Removed:
    dragonegg/trunk/gcc-patches/
Modified:
    dragonegg/trunk/Makefile
    dragonegg/trunk/README
    dragonegg/trunk/extras/do_self_strap
    dragonegg/trunk/www/index.html

Modified: dragonegg/trunk/Makefile
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/Makefile?rev=133427&r1=133426&r2=133427&view=diff
==============================================================================
--- dragonegg/trunk/Makefile (original)
+++ dragonegg/trunk/Makefile Mon Jun 20 02:43:10 2011
@@ -1,5 +1,5 @@
 # Specify the gcc executable you will use the dragonegg plugin with here.
-GCC?=gcc-4.5
+GCC?=gcc
 
 # Specify the copy of LLVM you will build the plugin against by giving its
 # llvm-config here.  To use an installed copy of LLVM, specify the installed

Modified: dragonegg/trunk/README
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/README?rev=133427&r1=133426&r2=133427&view=diff
==============================================================================
--- dragonegg/trunk/README (original)
+++ dragonegg/trunk/README Mon Jun 20 02:43:10 2011
@@ -2,95 +2,60 @@
 - BUILD INSTRUCTIONS -
 ----------------------
 
-Step 0: Build and install llvm
-------------------------------
+Prerequisites
+-------------
 
-I'm assuming anyone reading this knows how to build and install llvm.
-You need the latest llvm from the subversion repository.
+The dragonegg plugin works with gcc 4.5 or gcc 4.6, so you will need to have one
+of these installed.  Many linux distributions ship one or both of them, perhaps
+as an addon package; binaries can be downloaded for most platforms.  Otherwise
+you can always build one of these gcc versions yourself.  Both plugin support
+(--enable-plugin) and support for link time optimization (--enable-lto) need
+to be enabled in gcc, but since they are enabled by default on most platforms
+this should be the case.
 
-Step 1: Build gcc
------------------
+Step 0: Build and install llvm
+------------------------------
 
-Obtain a copy of the source code for the gcc-4.5 release.  You can get it from
-one of the gcc mirrors, see http://gcc.gnu.org/mirrors.html.  Alternatively, you
-can use the gcc-4.5 branch of the gcc subversion repository:
-  svn checkout svn://gcc.gnu.org/svn/gcc/branches/gcc-4_5-branch SomeLocalDir
-If you are feeling brave then you can try gcc mainline:
-  svn checkout svn://gcc.gnu.org/svn/gcc/trunk SomeLocalDir
-Changes on gcc mainline occasionally break the plugin, so your mileage may vary.
-You can find a subversion revision number that is known to work well in the file
-gcc_revision_tested_with (in the same directory as this README).
-
-Apply the patches in the gcc-patches subdirectory, if any.  The following should
-do the trick ("SomeLocalDir" is where you checked/unpacked the gcc source):
-  cat gcc-patches/*.diff | patch -d SomeLocalDir -p1
-
-Configure gcc with your favorite options and also with --enable-plugin and
---enable-lto.  Build gcc and install it somewhere.  If you don't have libelf
-installed then the configure step may fail because the configure script thinks
-that LTO requires libelf, though in fact it does not when using dragonegg.  See
-  http://gcc.gnu.org/wiki/LinkTimeOptimization#Building_the_branch
-In theory the gcc you build can be a cross-compiler, and the plugin should work
-and build code for the targeted platform.  I don't think anyone has ever tried
-this though.
-
-Darwin special: the gcc configure script thinks darwin doesn't support dynamic
-libraries and concludes that plugins won't work.  You can find patches to fix
-this here:
-http://gcc.gnu.org/ml/gcc-patches/2010-04/msg00610.html
-NOTE: This may be fixed in gcc mainline (gcc 4.6).
-
-Darwin special 2: the gcc configure script thinks darwin doesn't support LTO
-because it is not an ELF platform.  Dragonegg repurposes the LTO infrastructure,
-and thus needs LTO support enabled, but it makes no use of the parts of LTO that
-require ELF.  You just need to turn off the ELF check in the configure script.
-If anyone has a patch to do this, I will be happy to add it here!
-NOTE: This is fixed in gcc mainline (gcc 4.6).
+I'm assuming anyone reading this knows how to build and install llvm.  The
+version of llvm must match the version of the plugin, so if you are building
+dragonegg-3.0 then you should use llvm-3.0, while if you are building the
+development version of dragonegg then use the development version of llvm.
 
 
-Step 2: Build the plugin
+Step 1: Build the plugin
 ------------------------
 
 Build the plugin like this:
-  GCC=PATH_TO_JUST_INSTALLED_GCC make
-This should be done in the directory containing this README.
+  GCC=PATH_TO_INSTALLED_GCC make
+This command should be executed in the directory containing this README.
 
 The plugin needs to know about the version of gcc it will be loaded into, which
-is why you need to specify the gcc installed in step 1 via the GCC variable like
-this.  If you have arranged for the new gcc to occur in your path with the name
-gcc-4.5 (using a symbolic link for example) then you can build the plugin using:
+is why you need to specify your version of gcc 4.5/4.6 via the GCC variable like
+this.  If you don't set the GCC variable then by default "gcc" is used, so you
+can just do
   make
+to build if your system gcc is gcc version 4.5 or 4.6.
+
 The plugin is compiled using the system compiler, and not with the gcc specified
-in the GCC variable (which wouldn't work if you built a cross compiler).  If you
-want to also compile the plugin with the new gcc, you can do:
-  CC=PATH_TO_JUST_INSTALLED_GCC CXX=PATH_TO_JUST_INSTALLED_GCC GCC=PATH_TO_JUST_INSTALLED_GCC make
+in the GCC variable (which wouldn't work if it is a cross compiler).  If you
+want to also compile the plugin with your copy gcc 4.5/4.6, you can do:
+  CC=PATH_TO_INSTALLED_GCC CXX=PATH_TO_INSTALLED_GCC GCC=PATH_TO_INSTALLED_GCC make
 
 The build system runs the "llvm-config" program (which should be in your path if
-you installed LLVM properly in step 0) to find out about the copy of LLVM you
+you installed llvm properly in step 0) to find out about the copy of LLVM you
 installed, so there is no need to tell the build system explicitly about LLVM.
 If llvm-config is not in your path then you can specify where to find it using
 the LLVM_CONFIG variable.
 
 The end result of the build is a shared library, dragonegg.so.
 
--------------------------
-- COMMON BUILD PROBLEMS -
--------------------------
-
-To build gcc-4.5 you need the GMP, MPC and MPFR libraries.  If you installed the
-libraries locally, so their header files are not in the standard system include
-path, then the dragonegg build will probably fail due to failing to find header
-files like mpc.h.  To solve this, use CPPFLAGS to add additional include paths,
-for example:
-  CPPFLAGS="-I/path/to/header/files" make
-
 
 ----------------------
 - USAGE INSTRUCTIONS -
 ----------------------
 
 Run gcc as usual, but pass -fplugin=./dragonegg.so as an extra command line
-argument.  Make sure you use the gcc you installed above, not the system gcc!
+argument.  Make sure you use the gcc you built dragonegg against (see step 1)!
 
 
 ------------------

Modified: dragonegg/trunk/extras/do_self_strap
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/extras/do_self_strap?rev=133427&r1=133426&r2=133427&view=diff
==============================================================================
--- dragonegg/trunk/extras/do_self_strap (original)
+++ dragonegg/trunk/extras/do_self_strap Mon Jun 20 02:43:10 2011
@@ -100,19 +100,11 @@
   svn co -r $GCC_REVISION svn://gcc.gnu.org/svn/gcc/branches/gcc-4_5-branch $GCC_SOURCE
 elif [ ! -L $GCC_SOURCE ] ; then	# Do not update symbolic links.  This is
 					# for the benefit of the buildbots.
-  echo "Reverting any applied patches"
-  svn revert -R $GCC_SOURCE/gcc
   echo "Updating GCC"
   svn update -r $GCC_REVISION $GCC_SOURCE
 fi
 
 
-# Apply any needed patches to GCC
-for PATCH in $DRAGONEGG_SOURCE/gcc-patches/*.diff ; do
-  echo "Applying patch $PATCH"
-  patch -d $GCC_SOURCE -p1 < $PATCH
-done
-
 PLUGIN_OPTION= # No plugin yet
 PREV_DRAGONEGG_BUILD= # No previous dragonegg
 for STAGE in $STAGES ; do

Modified: dragonegg/trunk/www/index.html
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/www/index.html?rev=133427&r1=133426&r2=133427&view=diff
==============================================================================
--- dragonegg/trunk/www/index.html (original)
+++ dragonegg/trunk/www/index.html Mon Jun 20 02:43:10 2011
@@ -37,19 +37,22 @@
   <!--=====================================================================-->
 
   <ul>
-  <li>C works well, for example you can build a working gcc using it</li>
+  <li>C works well, for example you can build a working gcc using it.</li>
   <li>C++ works fairly well, for example you can build LLVM, clang and boost
   with it (the resulting LLVM and clang work correctly; boost mostly works but
-  there are some mysterious failures)</li>
+  there are some mysterious failures).</li>
   <li>Fortran works fairly well, for example SPEC CPU mostly compiles and works,
-  but there are some failures</li>
+  but there are some failures.  These have all been fixed in the development
+  version.</li>
   <li>It can compile quite a lot of Ada, and the compiled code mostly seems to
-  work</li>
-  <li>It can compile a small amount of Obj-C and Obj-C++</li>
-  <li>It can compile simple Java programs</li>
-  <li>Limited debug info</li>
-  <li>Requires patching gcc</li>
-  <li>Only supports x86-32 and x86-64</li>
+  work.</li>
+  <li>It can compile a small amount of Obj-C and Obj-C++.</li>
+  <li>It can compile simple Java programs, but they don't execute properly
+  (this is a consequence of the java front-end not supporting GCC's LTO).</li>
+  <li>Limited debug info.</li>
+  <li>Versions 2.9 and earlier require patching gcc (the development version
+  does not).</li>
+  <li>Only supports x86-32 and x86-64.</li>
   <li>Only supports linux, darwin and freebsd (additional gcc patches may be
       needed on darwin, see the <tt>README</tt> file).
   </ul>
@@ -278,12 +281,7 @@
      <pre>	svn co http://llvm.org/svn/llvm-project/llvm/trunk llvm</pre>
   <p><a href="http://llvm.org/docs/GettingStarted.html">Build LLVM</a> in the
   usual way.</p>
-  <p>Get the <a href="http://gcc.gnu.org/gcc-4.5/">gcc-4.5 source code</a>:</p>
-     <pre>	svn co http://gcc.gnu.org/svn/gcc/branches/gcc-4_5-branch gcc-4.5</pre>
-  <p>Apply all of the patches in <tt>dragonegg/gcc-patches/</tt>, if any, to the
-     gcc-4.5 source. You need to pass the <tt>-p1</tt> option to <tt>patch</tt>.
-     <a href="http://gcc.gnu.org/install/">Build and install gcc-4.5</a> in the
-     usual way.</p>
+  <p>Install gcc-4.5 or gcc-4.6 (you do not need to build your own copy).</p>
   <p>Doing</p>
      <pre>	GCC=path_to_just_installed_gcc make</pre>
   <p>in the <tt>dragonegg</tt> directory should then build <tt>dragonegg.so</tt>.



From baldrick at free.fr  Mon Jun 20 04:26:23 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 20 Jun 2011 09:26:23 -0000
Subject: [llvm-commits] [llvm] r133430 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
Message-ID: <20110620092623.C8B2C2A6C12C@llvm.org>

Author: baldrick
Date: Mon Jun 20 04:26:23 2011
New Revision: 133430

URL: http://llvm.org/viewvc/llvm-project?rev=133430&view=rev
Log:
Disable the logic added by rafael in commit 133415 to see if it brings the
dragonegg buildbots back to life.  Original commit message:
Teach early dup how to duplicate basic blocks with one successor and only phi instructions
into more complex blocks.

Modified:
    llvm/trunk/lib/CodeGen/TailDuplication.cpp

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133430&r1=133429&r2=133430&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Mon Jun 20 04:26:23 2011
@@ -707,7 +707,7 @@
   DenseSet<unsigned> UsedByPhi;
   getRegsUsedByPHIs(*TailBB, &UsedByPhi);
 
-  if (isSimpleBB(TailBB))
+  if (0 && isSimpleBB(TailBB)) // Disabled to see if doing so fixes buildbots.
     return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
 
   // Iterate through all the unique predecessors and tail-duplicate this



From baldrick at free.fr  Mon Jun 20 05:02:06 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 20 Jun 2011 10:02:06 -0000
Subject: [llvm-commits] [dragonegg] r133431 - /dragonegg/trunk/src/Debug.cpp
Message-ID: <20110620100206.4410F2A6C12C@llvm.org>

Author: baldrick
Date: Mon Jun 20 05:02:06 2011
New Revision: 133431

URL: http://llvm.org/viewvc/llvm-project?rev=133431&view=rev
Log:
TYPE_DEBUG_REPRESENTATION_TYPE was removed in gcc-4.6.  Handle VECTOR_TYPE
directly.

Modified:
    dragonegg/trunk/src/Debug.cpp

Modified: dragonegg/trunk/src/Debug.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Debug.cpp?rev=133431&r1=133430&r2=133431&view=diff
==============================================================================
--- dragonegg/trunk/src/Debug.cpp (original)
+++ dragonegg/trunk/src/Debug.cpp Mon Jun 20 05:02:06 2011
@@ -619,9 +619,6 @@
     return DIType();
   }
 
-  if (TREE_CODE(type) == VECTOR_TYPE)
-    type = TREE_TYPE (TYPE_FIELDS (TYPE_DEBUG_REPRESENTATION_TYPE (type)));
-
   // Add the dimensions of the array.  FIXME: This loses CV qualifiers from
   // interior arrays, do we care?  Why aren't nested arrays represented the
   // obvious/recursive way?
@@ -629,24 +626,29 @@
 
   // There will be ARRAY_TYPE nodes for each rank.  Followed by the derived
   // type.
-  tree atype = type;
-  tree EltTy = TREE_TYPE(atype);
-  for (; TREE_CODE(atype) == ARRAY_TYPE;
-       atype = TREE_TYPE(atype)) {
-    tree Domain = TYPE_DOMAIN(atype);
-    if (Domain) {
-      // FIXME - handle dynamic ranges
-      tree MinValue = TYPE_MIN_VALUE(Domain);
-      tree MaxValue = TYPE_MAX_VALUE(Domain);
-      uint64_t Low = 0;
-      uint64_t Hi = 0;
-      if (isInt64(MinValue, false))
-        Low = getINTEGER_CSTVal(MinValue);
-      if (isInt64(MaxValue, false))
-        Hi = getINTEGER_CSTVal(MaxValue);
-      Subscripts.push_back(DebugFactory.GetOrCreateSubrange(Low, Hi));
+  tree EltTy = TREE_TYPE(type);
+  if (TREE_CODE(type) == ARRAY_TYPE) {
+    tree atype = type;
+    for (; TREE_CODE(atype) == ARRAY_TYPE; atype = TREE_TYPE(atype)) {
+      tree Domain = TYPE_DOMAIN(atype);
+      if (Domain) {
+        // FIXME - handle dynamic ranges
+        tree MinValue = TYPE_MIN_VALUE(Domain);
+        tree MaxValue = TYPE_MAX_VALUE(Domain);
+        uint64_t Low = 0;
+        uint64_t Hi = 0;
+        if (isInt64(MinValue, false))
+          Low = getINTEGER_CSTVal(MinValue);
+        if (isInt64(MaxValue, false))
+          Hi = getINTEGER_CSTVal(MaxValue);
+        Subscripts.push_back(DebugFactory.GetOrCreateSubrange(Low, Hi));
+      }
+      EltTy = TREE_TYPE(atype);
     }
-    EltTy = TREE_TYPE(atype);
+  } else {
+    assert(TREE_CODE(type) == VECTOR_TYPE && "Not an array or vector type!");
+    unsigned Length = TYPE_VECTOR_SUBPARTS(type);
+    Subscripts.push_back(DebugFactory.GetOrCreateSubrange(0, Length));
   }
 
   llvm::DIArray SubscriptArray =



From justin.holewinski at gmail.com  Mon Jun 20 07:53:26 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Mon, 20 Jun 2011 08:53:26 -0400
Subject: [llvm-commits] [PATCH][Target/PTX] Add address_size directive
	to PTX backend
In-Reply-To: <20110620015129.GA56262@cs.nctu.edu.tw>
References: <20110617073109.GA93378@cs.nctu.edu.tw>
	<CA57A5F6-2F8E-4AAC-B6E7-279DA5F2D8EE@gmail.com>
	<20110618065617.GA25444@cs.nctu.edu.tw>
	<B3C74E93-B790-4255-808D-DBB9E94278C6@gmail.com>
	<20110619121258.GA50677@cs.nctu.edu.tw>
	<347A9771-6ADD-4454-86D6-2842AEA82D44@gmail.com>
	<20110620015129.GA56262@cs.nctu.edu.tw>
Message-ID: <BD989BFB-373E-4577-8F21-C544F561DA49@gmail.com>


On Jun 19, 2011, at 9:51 PM, ??? wrote:

> Hi, Justin
> 
>>> What you want is removing FeatureAddrSize32/64 from PTX.td to avoid
>>> user intervention, right? PTXAddrSize is assigned accroding to the
>>> 32/64-bit flag,
>>> 
>>> // PTXSubtarget ctor in PTXSubtarget.cpp
>>> PTXAddrSize = is64Bit? PTX_AddrSize_64 : PTX_AddrSize_32;
>> 
>> Correct.
> 
>  Fixed.

I hate to nit-pick, but do we really need the address size field and associated enumeration?  It's always tied to the 64-bit flag, and we do not need to create any TableGen predicates from the value.

I think this patch can be as simple as:

if (ST.supportsPTX23()) {
  std::string addrSize = is64Bit() ? "64" : "32";
  OutStreamer.EmitRawText(Twine("\t.address_size " + addrSize));
}

? with the appropriate test cases.


> 
> Regards,
> chenwj
> 
> -- 
> Wei-Ren Chen (???)
> Computer Systems Lab, Institute of Information Science,
> Academia Sinica, Taiwan (R.O.C.)
> Tel:886-2-2788-3799 #1667
> <patch-llvm-133404.txt>

Thanks,

Justin Holewinski

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From rafael.espindola at gmail.com  Mon Jun 20 09:11:42 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Mon, 20 Jun 2011 14:11:42 -0000
Subject: [llvm-commits] [llvm] r133432 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
Message-ID: <20110620141142.A6EDD2A6C12C@llvm.org>

Author: rafael
Date: Mon Jun 20 09:11:42 2011
New Revision: 133432

URL: http://llvm.org/viewvc/llvm-project?rev=133432&view=rev
Log:
Re enable 133415 with two fixes
* Don't introduce a duplicated bb in the CFG
* When making a branch unconditional, clear the PredCond array so that it
  is really unconditional.

Modified:
    llvm/trunk/lib/CodeGen/TailDuplication.cpp

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133432&r1=133431&r2=133432&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Mon Jun 20 09:11:42 2011
@@ -669,8 +669,10 @@
       PredTBB = NewTarget;
 
     // Make the branch unconditional if possible
-    if (PredTBB == PredFBB)
+    if (PredTBB == PredFBB) {
+      PredCond.clear();
       PredFBB = NULL;
+    }
 
     // Avoid adding fall through branches.
     if (PredFBB == NextBB)
@@ -684,7 +686,10 @@
       TII->InsertBranch(*PredBB, PredTBB, PredFBB, PredCond, DebugLoc());
 
     PredBB->removeSuccessor(TailBB);
-    PredBB->addSuccessor(NewTarget);
+    unsigned NumSuccessors = PredBB->succ_size();
+    assert(NumSuccessors <= 1);
+    if (NumSuccessors == 0 || *PredBB->succ_begin() != NewTarget)
+      PredBB->addSuccessor(NewTarget);
 
     TDBBs.push_back(PredBB);
 
@@ -707,7 +712,7 @@
   DenseSet<unsigned> UsedByPhi;
   getRegsUsedByPHIs(*TailBB, &UsedByPhi);
 
-  if (0 && isSimpleBB(TailBB)) // Disabled to see if doing so fixes buildbots.
+  if (isSimpleBB(TailBB))
     return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
 
   // Iterate through all the unique predecessors and tail-duplicate this



From jay.foad at gmail.com  Mon Jun 20 09:12:33 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Mon, 20 Jun 2011 14:12:33 -0000
Subject: [llvm-commits] [llvm] r133433 - in /llvm/trunk: include/llvm/Use.h
 lib/VMCore/Use.cpp lib/VMCore/User.cpp
Message-ID: <20110620141233.7A0872A6C12C@llvm.org>

Author: foad
Date: Mon Jun 20 09:12:33 2011
New Revision: 133433

URL: http://llvm.org/viewvc/llvm-project?rev=133433&view=rev
Log:
Remove the AugmentedUse struct.

I don't think the AugmentedUse struct buys us much, either in
correctness or in ease of use. Ditch it, and simplify Use::getUser() and
User::allocHungoffUses().

Modified:
    llvm/trunk/include/llvm/Use.h
    llvm/trunk/lib/VMCore/Use.cpp
    llvm/trunk/lib/VMCore/User.cpp

Modified: llvm/trunk/include/llvm/Use.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Use.h?rev=133433&r1=133432&r2=133433&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Use.h (original)
+++ llvm/trunk/include/llvm/Use.h Mon Jun 20 09:12:33 2011
@@ -60,6 +60,10 @@
   /// that also works with less standard-compliant compilers
   void swap(Use &RHS);
 
+  // A type for the word following an array of hung-off Uses in memory, which is
+  // a pointer back to their User with the bottom bit set.
+  typedef PointerIntPair<User*, 1, unsigned> UserRef;
+
 private:
   /// Copy ctor - do not implement
   Use(const Use &U);
@@ -208,15 +212,6 @@
   unsigned getOperandNo() const;
 };
 
-//===----------------------------------------------------------------------===//
-//                         AugmentedUse layout struct
-//===----------------------------------------------------------------------===//
-
-struct AugmentedUse : public Use {
-  PointerIntPair<User*, 1, unsigned> ref;
-  AugmentedUse(); // not implemented
-};
-
 } // End llvm namespace
 
 #endif

Modified: llvm/trunk/lib/VMCore/Use.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Use.cpp?rev=133433&r1=133432&r2=133433&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Use.cpp (original)
+++ llvm/trunk/lib/VMCore/Use.cpp Mon Jun 20 09:12:33 2011
@@ -135,11 +135,9 @@
 
 User *Use::getUser() const {
   const Use *End = getImpliedUser();
-  const PointerIntPair<User*, 1, unsigned>&
-    ref(static_cast<const AugmentedUse*>(End - 1)->ref);
-  User *She = ref.getPointer();
-  return ref.getInt()
-    ? She
+  const UserRef *ref = reinterpret_cast<const UserRef*>(End);
+  return ref->getInt()
+    ? ref->getPointer()
     : (User*)End;
 }
 

Modified: llvm/trunk/lib/VMCore/User.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/User.cpp?rev=133433&r1=133432&r2=133433&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/User.cpp (original)
+++ llvm/trunk/lib/VMCore/User.cpp Mon Jun 20 09:12:33 2011
@@ -41,13 +41,9 @@
 
 Use *User::allocHungoffUses(unsigned N) const {
   Use *Begin = static_cast<Use*>(::operator new(sizeof(Use) * N
-                                                + sizeof(AugmentedUse)
-                                                - sizeof(Use)));
+                                                + sizeof(Use::UserRef)));
   Use *End = Begin + N;
-  PointerIntPair<User*, 1, unsigned>&
-    ref(static_cast<AugmentedUse&>(End[-1]).ref);
-  ref.setPointer(const_cast<User*>(this));
-  ref.setInt(1);
+  (void) new(End) Use::UserRef(const_cast<User*>(this), 1);
   return Use::initTags(Begin, End);
 }
 



From jay.foad at gmail.com  Mon Jun 20 09:18:48 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Mon, 20 Jun 2011 14:18:48 -0000
Subject: [llvm-commits] [llvm] r133434 - in /llvm/trunk/lib:
 Bitcode/Writer/BitcodeWriter.cpp Target/CppBackend/CPPBackend.cpp
 Transforms/Scalar/GVN.cpp Transforms/Scalar/LoopRotation.cpp
 VMCore/AsmWriter.cpp VMCore/BasicBlock.cpp VMCore/Verifier.cpp
Message-ID: <20110620141848.567952A6C12C@llvm.org>

Author: foad
Date: Mon Jun 20 09:18:48 2011
New Revision: 133434

URL: http://llvm.org/viewvc/llvm-project?rev=133434&view=rev
Log:
Make better use of the PHINode API.

Change various bits of code to make better use of the existing PHINode
API, to insulate them from forthcoming changes in how PHINodes store
their operands.

Modified:
    llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Transforms/Scalar/GVN.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp
    llvm/trunk/lib/VMCore/AsmWriter.cpp
    llvm/trunk/lib/VMCore/BasicBlock.cpp
    llvm/trunk/lib/VMCore/Verifier.cpp

Modified: llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp?rev=133434&r1=133433&r2=133434&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp (original)
+++ llvm/trunk/lib/Bitcode/Writer/BitcodeWriter.cpp Mon Jun 20 09:18:48 2011
@@ -1079,12 +1079,16 @@
     AbbrevToUse = FUNCTION_INST_UNREACHABLE_ABBREV;
     break;
 
-  case Instruction::PHI:
+  case Instruction::PHI: {
+    const PHINode &PN = cast<PHINode>(I);
     Code = bitc::FUNC_CODE_INST_PHI;
-    Vals.push_back(VE.getTypeID(I.getType()));
-    for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i)
-      Vals.push_back(VE.getValueID(I.getOperand(i)));
+    Vals.push_back(VE.getTypeID(PN.getType()));
+    for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
+      Vals.push_back(VE.getValueID(PN.getIncomingValue(i)));
+      Vals.push_back(VE.getValueID(PN.getIncomingBlock(i)));
+    }
     break;
+  }
 
   case Instruction::Alloca:
     Code = bitc::FUNC_CODE_INST_ALLOCA;

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=133434&r1=133433&r2=133434&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Jun 20 09:18:48 2011
@@ -1353,9 +1353,10 @@
     printEscapedString(phi->getName());
     Out << "\", " << bbname << ");";
     nl(Out);
-    for (unsigned i = 0; i < phi->getNumOperands(); i+=2) {
+    for (unsigned i = 0; i < phi->getNumIncomingValues(); ++i) {
       Out << iName << "->addIncoming("
-          << opNames[i] << ", " << opNames[i+1] << ");";
+          << opNames[PHINode::getOperandNumForIncomingValue(i)] << ", "
+          << opNames[PHINode::getOperandNumForIncomingBlock(i)] << ");";
       nl(Out);
     }
     break;

Modified: llvm/trunk/lib/Transforms/Scalar/GVN.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/GVN.cpp?rev=133434&r1=133433&r2=133434&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/GVN.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/GVN.cpp Mon Jun 20 09:18:48 2011
@@ -1190,8 +1190,10 @@
     // escaping uses to any values that are operands to these PHIs.
     for (unsigned i = 0, e = NewPHIs.size(); i != e; ++i) {
       PHINode *P = NewPHIs[i];
-      for (unsigned ii = 0, ee = P->getNumIncomingValues(); ii != ee; ++ii)
-        AA->addEscapingUse(P->getOperandUse(2*ii));
+      for (unsigned ii = 0, ee = P->getNumIncomingValues(); ii != ee; ++ii) {
+        unsigned jj = PHINode::getOperandNumForIncomingValue(ii);
+        AA->addEscapingUse(P->getOperandUse(jj));
+      }
     }
   }
 
@@ -2149,8 +2151,11 @@
         // Because we have added a PHI-use of the pointer value, it has now
         // "escaped" from alias analysis' perspective.  We need to inform
         // AA of this.
-        for (unsigned ii = 0, ee = Phi->getNumIncomingValues(); ii != ee; ++ii)
-          VN.getAliasAnalysis()->addEscapingUse(Phi->getOperandUse(2*ii));
+        for (unsigned ii = 0, ee = Phi->getNumIncomingValues(); ii != ee;
+             ++ii) {
+          unsigned jj = PHINode::getOperandNumForIncomingValue(ii);
+          VN.getAliasAnalysis()->addEscapingUse(Phi->getOperandUse(jj));
+        }
         
         if (MD)
           MD->invalidateCachedPointerInfo(Phi);

Modified: llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp?rev=133434&r1=133433&r2=133434&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopRotation.cpp Mon Jun 20 09:18:48 2011
@@ -220,7 +220,7 @@
   // For PHI nodes, the value available in OldPreHeader is just the
   // incoming value from OldPreHeader.
   for (; PHINode *PN = dyn_cast<PHINode>(I); ++I)
-    ValueMap[PN] = PN->getIncomingValue(PN->getBasicBlockIndex(OrigPreheader));
+    ValueMap[PN] = PN->getIncomingValueForBlock(OrigPreheader);
 
   // For the rest of the instructions, either hoist to the OrigPreheader if
   // possible or create a clone in the OldPreHeader if not.

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=133434&r1=133433&r2=133434&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Mon Jun 20 09:18:48 2011
@@ -1905,16 +1905,16 @@
       writeOperand(I.getOperand(i), true);
     }
     Out << ']';
-  } else if (isa<PHINode>(I)) {
+  } else if (const PHINode *PN = dyn_cast<PHINode>(&I)) {
     Out << ' ';
     TypePrinter.print(I.getType(), Out);
     Out << ' ';
 
-    for (unsigned op = 0, Eop = I.getNumOperands(); op < Eop; op += 2) {
+    for (unsigned op = 0, Eop = PN->getNumIncomingValues(); op < Eop; ++op) {
       if (op) Out << ", ";
       Out << "[ ";
-      writeOperand(I.getOperand(op  ), false); Out << ", ";
-      writeOperand(I.getOperand(op+1), false); Out << " ]";
+      writeOperand(PN->getIncomingValue(op), false); Out << ", ";
+      writeOperand(PN->getIncomingBlock(op), false); Out << " ]";
     }
   } else if (const ExtractValueInst *EVI = dyn_cast<ExtractValueInst>(&I)) {
     Out << ' ';

Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=133434&r1=133433&r2=133434&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/BasicBlock.cpp (original)
+++ llvm/trunk/lib/VMCore/BasicBlock.cpp Mon Jun 20 09:18:48 2011
@@ -227,8 +227,8 @@
 
       // If the PHI _HAD_ two uses, replace PHI node with its now *single* value
       if (max_idx == 2) {
-        if (PN->getOperand(0) != PN)
-          PN->replaceAllUsesWith(PN->getOperand(0));
+        if (PN->getIncomingValue(0) != PN)
+          PN->replaceAllUsesWith(PN->getIncomingValue(0));
         else
           // We are left with an infinite loop with no entries: kill the PHI.
           PN->replaceAllUsesWith(UndefValue::get(PN->getType()));

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=133434&r1=133433&r2=133434&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Jun 20 09:18:48 2011
@@ -1482,8 +1482,10 @@
         // PHI nodes differ from other nodes because they actually "use" the
         // value in the predecessor basic blocks they correspond to.
         BasicBlock *UseBlock = BB;
-        if (isa<PHINode>(I))
-          UseBlock = dyn_cast<BasicBlock>(I.getOperand(i+1));
+        if (PHINode *PN = dyn_cast<PHINode>(&I)) {
+          unsigned j = PHINode::getIncomingValueNumForOperand(i);
+          UseBlock = PN->getIncomingBlock(j);
+        }
         Assert2(UseBlock, "Invoke operand is PHI node with bad incoming-BB",
                 Op, &I);
 
@@ -1515,10 +1517,11 @@
                 return;
               }
         }
-      } else if (isa<PHINode>(I)) {
+      } else if (PHINode *PN = dyn_cast<PHINode>(&I)) {
         // PHI nodes are more difficult than other nodes because they actually
         // "use" the value in the predecessor basic blocks they correspond to.
-        BasicBlock *PredBB = dyn_cast<BasicBlock>(I.getOperand(i+1));
+        unsigned j = PHINode::getIncomingValueNumForOperand(i);
+        BasicBlock *PredBB = PN->getIncomingBlock(j);
         Assert2(PredBB && (DT->dominates(OpBlock, PredBB) ||
                            !DT->isReachableFromEntry(PredBB)),
                 "Instruction does not dominate all uses!", Op, &I);



From jay.foad at gmail.com  Mon Jun 20 09:38:01 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Mon, 20 Jun 2011 14:38:01 -0000
Subject: [llvm-commits] [llvm] r133435 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/Target/CppBackend/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
Message-ID: <20110620143801.6C0D72A6C124@llvm.org>

Author: foad
Date: Mon Jun 20 09:38:01 2011
New Revision: 133435

URL: http://llvm.org/viewvc/llvm-project?rev=133435&view=rev
Log:
Change how PHINodes store their operands.

Change PHINodes to store simple pointers to their incoming basic blocks,
instead of full-blown Uses.

Note that this loses an optimization in SplitCriticalEdge(), because we
can no longer walk the use list of a BasicBlock to find phi nodes. See
the comment I removed starting "However, the foreach loop is slow for
blocks with lots of predecessors".

Extend replaceAllUsesWith() on a BasicBlock to also update any phi
nodes in the block's successors. This mimics what would have happened
when PHINodes were proper Users of their incoming blocks. (Note that
this only works if OldBB->replaceAllUsesWith(NewBB) is called when
OldBB still has a terminator instruction, so it still has some
successors.)

Modified:
    llvm/trunk/include/llvm/BasicBlock.h
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/CFG.h
    llvm/trunk/include/llvm/Use.h
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
    llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
    llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp
    llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
    llvm/trunk/lib/Transforms/Utils/Local.cpp
    llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
    llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
    llvm/trunk/lib/VMCore/BasicBlock.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp
    llvm/trunk/lib/VMCore/User.cpp
    llvm/trunk/lib/VMCore/Value.cpp
    llvm/trunk/lib/VMCore/Verifier.cpp

Modified: llvm/trunk/include/llvm/BasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BasicBlock.h?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/include/llvm/BasicBlock.h (original)
+++ llvm/trunk/include/llvm/BasicBlock.h Mon Jun 20 09:38:01 2011
@@ -110,7 +110,7 @@
         Function *getParent()       { return Parent; }
 
   /// use_back - Specialize the methods defined in Value, as we know that an
-  /// BasicBlock can only be used by Users (specifically PHI nodes, terminators,
+  /// BasicBlock can only be used by Users (specifically terminators
   /// and BlockAddress's).
   User       *use_back()       { return cast<User>(*use_begin());}
   const User *use_back() const { return cast<User>(*use_begin());}
@@ -248,6 +248,10 @@
   /// other than direct branches, switches, etc. to it.
   bool hasAddressTaken() const { return getSubclassDataFromValue() != 0; }
 
+  /// replaceSuccessorsPhiUsesWith - Update all phi nodes in all our successors
+  /// to refer to basic block New instead of to us.
+  void replaceSuccessorsPhiUsesWith(BasicBlock *New);
+
 private:
   /// AdjustBlockAddressRefCount - BasicBlock stores the number of BlockAddress
   /// objects using it.  This is almost always 0, sometimes one, possibly but

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Mon Jun 20 09:38:01 2011
@@ -1814,7 +1814,7 @@
   explicit PHINode(const Type *Ty, unsigned NumReservedValues,
                    const Twine &NameStr = "", Instruction *InsertBefore = 0)
     : Instruction(Ty, Instruction::PHI, 0, 0, InsertBefore),
-      ReservedSpace(NumReservedValues * 2) {
+      ReservedSpace(NumReservedValues) {
     setName(NameStr);
     OperandList = allocHungoffUses(ReservedSpace);
   }
@@ -1822,11 +1822,16 @@
   PHINode(const Type *Ty, unsigned NumReservedValues, const Twine &NameStr,
           BasicBlock *InsertAtEnd)
     : Instruction(Ty, Instruction::PHI, 0, 0, InsertAtEnd),
-      ReservedSpace(NumReservedValues * 2) {
+      ReservedSpace(NumReservedValues) {
     setName(NameStr);
     OperandList = allocHungoffUses(ReservedSpace);
   }
 protected:
+  // allocHungoffUses - this is more complicated than the generic
+  // User::allocHungoffUses, because we have to allocate Uses for the incoming
+  // values and pointers to the incoming blocks, all in one allocation.
+  Use *allocHungoffUses(unsigned) const;
+
   virtual PHINode *clone_impl() const;
 public:
   /// Constructors - NumReservedValues is a hint for the number of incoming
@@ -1845,32 +1850,55 @@
   /// Provide fast operand accessors
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
 
+  // Block iterator interface. This provides access to the list of incoming
+  // basic blocks, which parallels the list of incoming values.
+
+  typedef BasicBlock **block_iterator;
+  typedef BasicBlock * const *const_block_iterator;
+
+  block_iterator block_begin() {
+    Use::UserRef *ref =
+      reinterpret_cast<Use::UserRef*>(op_begin() + ReservedSpace);
+    return reinterpret_cast<block_iterator>(ref + 1);
+  }
+
+  const_block_iterator block_begin() const {
+    const Use::UserRef *ref =
+      reinterpret_cast<const Use::UserRef*>(op_begin() + ReservedSpace);
+    return reinterpret_cast<const_block_iterator>(ref + 1);
+  }
+
+  block_iterator block_end() {
+    return block_begin() + getNumOperands();
+  }
+
+  const_block_iterator block_end() const {
+    return block_begin() + getNumOperands();
+  }
+
   /// getNumIncomingValues - Return the number of incoming edges
   ///
-  unsigned getNumIncomingValues() const { return getNumOperands()/2; }
+  unsigned getNumIncomingValues() const { return getNumOperands(); }
 
   /// getIncomingValue - Return incoming value number x
   ///
   Value *getIncomingValue(unsigned i) const {
-    assert(i*2 < getNumOperands() && "Invalid value number!");
-    return getOperand(i*2);
+    return getOperand(i);
   }
   void setIncomingValue(unsigned i, Value *V) {
-    assert(i*2 < getNumOperands() && "Invalid value number!");
-    setOperand(i*2, V);
+    setOperand(i, V);
   }
   static unsigned getOperandNumForIncomingValue(unsigned i) {
-    return i*2;
+    return i;
   }
   static unsigned getIncomingValueNumForOperand(unsigned i) {
-    assert(i % 2 == 0 && "Invalid incoming-value operand index!");
-    return i/2;
+    return i;
   }
 
   /// getIncomingBlock - Return incoming basic block number @p i.
   ///
   BasicBlock *getIncomingBlock(unsigned i) const {
-    return cast<BasicBlock>(getOperand(i*2+1));
+    return block_begin()[i];
   }
 
   /// getIncomingBlock - Return incoming basic block corresponding
@@ -1878,7 +1906,7 @@
   ///
   BasicBlock *getIncomingBlock(const Use &U) const {
     assert(this == U.getUser() && "Iterator doesn't point to PHI's Uses?");
-    return cast<BasicBlock>((&U + 1)->get());
+    return getIncomingBlock(&U - op_begin());
   }
 
   /// getIncomingBlock - Return incoming basic block corresponding
@@ -1889,16 +1917,8 @@
     return getIncomingBlock(I.getUse());
   }
 
-
   void setIncomingBlock(unsigned i, BasicBlock *BB) {
-    setOperand(i*2+1, (Value*)BB);
-  }
-  static unsigned getOperandNumForIncomingBlock(unsigned i) {
-    return i*2+1;
-  }
-  static unsigned getIncomingBlockNumForOperand(unsigned i) {
-    assert(i % 2 == 1 && "Invalid incoming-block operand index!");
-    return i/2;
+    block_begin()[i] = BB;
   }
 
   /// addIncoming - Add an incoming value to the end of the PHI list
@@ -1908,13 +1928,12 @@
     assert(BB && "PHI node got a null basic block!");
     assert(getType() == V->getType() &&
            "All operands to PHI node must be the same type as the PHI node!");
-    unsigned OpNo = NumOperands;
-    if (OpNo+2 > ReservedSpace)
+    if (NumOperands == ReservedSpace)
       growOperands();  // Get more space!
     // Initialize some new operands.
-    NumOperands = OpNo+2;
-    OperandList[OpNo] = V;
-    OperandList[OpNo+1] = (Value*)BB;
+    ++NumOperands;
+    setIncomingValue(NumOperands - 1, V);
+    setIncomingBlock(NumOperands - 1, BB);
   }
 
   /// removeIncomingValue - Remove an incoming value.  This is useful if a
@@ -1937,14 +1956,16 @@
   /// block in the value list for this PHI.  Returns -1 if no instance.
   ///
   int getBasicBlockIndex(const BasicBlock *BB) const {
-    Use *OL = OperandList;
-    for (unsigned i = 0, e = getNumOperands(); i != e; i += 2)
-      if (OL[i+1].get() == (const Value*)BB) return i/2;
+    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
+      if (block_begin()[i] == BB)
+        return i;
     return -1;
   }
 
   Value *getIncomingValueForBlock(const BasicBlock *BB) const {
-    return getIncomingValue(getBasicBlockIndex(BB));
+    int Idx = getBasicBlockIndex(BB);
+    assert(Idx >= 0 && "Invalid basic block argument!");
+    return getIncomingValue(Idx);
   }
 
   /// hasConstantValue - If the specified PHI node always merges together the

Modified: llvm/trunk/include/llvm/Support/CFG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CFG.h?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CFG.h (original)
+++ llvm/trunk/include/llvm/Support/CFG.h Mon Jun 20 09:38:01 2011
@@ -33,7 +33,7 @@
   USE_iterator It;
 
   inline void advancePastNonTerminators() {
-    // Loop to ignore non terminator uses (for example PHI nodes).
+    // Loop to ignore non terminator uses (for example BlockAddresses).
     while (!It.atEnd() && !isa<TerminatorInst>(*It))
       ++It;
   }

Modified: llvm/trunk/include/llvm/Use.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Use.h?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Use.h (original)
+++ llvm/trunk/include/llvm/Use.h Mon Jun 20 09:38:01 2011
@@ -112,13 +112,16 @@
   Use *getNext() const { return Next; }
 
   
+  /// initTags - initialize the waymarking tags on an array of Uses, so that
+  /// getUser() can find the User from any of those Uses.
+  static Use *initTags(Use *Start, Use *Stop);
+
   /// zap - This is used to destroy Use operands when the number of operands of
   /// a User changes.
   static void zap(Use *Start, const Use *Stop, bool del = false);
 
 private:
   const Use* getImpliedUser() const;
-  static Use *initTags(Use *Start, Use *Stop);
   
   Value *Val;
   Use *Next;
@@ -140,7 +143,6 @@
   }
 
   friend class Value;
-  friend class User;
 };
 
 // simplify_type - Allow clients to treat uses just like values when using

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Jun 20 09:38:01 2011
@@ -1356,7 +1356,7 @@
     for (unsigned i = 0; i < phi->getNumIncomingValues(); ++i) {
       Out << iName << "->addIncoming("
           << opNames[PHINode::getOperandNumForIncomingValue(i)] << ", "
-          << opNames[PHINode::getOperandNumForIncomingBlock(i)] << ");";
+          << getOpName(phi->getIncomingBlock(i)) << ");";
       nl(Out);
     }
     break;

Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Mon Jun 20 09:38:01 2011
@@ -1021,6 +1021,10 @@
         while (PHINode *PN = dyn_cast<PHINode>(Succ->begin()))
           ReplaceUsesOfWith(PN, PN->getIncomingValue(0), Worklist, L, LPM);
         
+        // If Succ has any successors with PHI nodes, update them to have
+        // entries coming from Pred instead of Succ.
+        Succ->replaceAllUsesWith(Pred);
+        
         // Move all of the successor contents from Succ to Pred.
         Pred->getInstList().splice(BI, Succ->getInstList(), Succ->begin(),
                                    Succ->end());
@@ -1028,10 +1032,6 @@
         BI->eraseFromParent();
         RemoveFromWorklist(BI, Worklist);
         
-        // If Succ has any successors with PHI nodes, update them to have
-        // entries coming from Pred instead of Succ.
-        Succ->replaceAllUsesWith(Pred);
-        
         // Remove Succ from the loop tree.
         LI->removeBlock(Succ);
         LPM->deleteSimpleAnalysisValue(Succ, L);

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Mon Jun 20 09:38:01 2011
@@ -153,13 +153,13 @@
   // Delete the unconditional branch from the predecessor...
   PredBB->getInstList().pop_back();
   
-  // Move all definitions in the successor to the predecessor...
-  PredBB->getInstList().splice(PredBB->end(), BB->getInstList());
-  
   // Make all PHI nodes that referred to BB now refer to Pred as their
   // source...
   BB->replaceAllUsesWith(PredBB);
   
+  // Move all definitions in the successor to the predecessor...
+  PredBB->getInstList().splice(PredBB->end(), BB->getInstList());
+  
   // Inherit predecessors name if it exists.
   if (!PredBB->hasName())
     PredBB->takeName(BB);

Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Mon Jun 20 09:38:01 2011
@@ -193,44 +193,22 @@
   
   // If there are any PHI nodes in DestBB, we need to update them so that they
   // merge incoming values from NewBB instead of from TIBB.
-  if (PHINode *APHI = dyn_cast<PHINode>(DestBB->begin())) {
-    // This conceptually does:
-    //  foreach (PHINode *PN in DestBB)
-    //    PN->setIncomingBlock(PN->getIncomingBlock(TIBB), NewBB);
-    // but is optimized for two cases.
-    
-    if (APHI->getNumIncomingValues() <= 8) {  // Small # preds case.
-      unsigned BBIdx = 0;
-      for (BasicBlock::iterator I = DestBB->begin(); isa<PHINode>(I); ++I) {
-        // We no longer enter through TIBB, now we come in through NewBB.
-        // Revector exactly one entry in the PHI node that used to come from
-        // TIBB to come from NewBB.
-        PHINode *PN = cast<PHINode>(I);
-        
-        // Reuse the previous value of BBIdx if it lines up.  In cases where we
-        // have multiple phi nodes with *lots* of predecessors, this is a speed
-        // win because we don't have to scan the PHI looking for TIBB.  This
-        // happens because the BB list of PHI nodes are usually in the same
-        // order.
-        if (PN->getIncomingBlock(BBIdx) != TIBB)
-          BBIdx = PN->getBasicBlockIndex(TIBB);
-        PN->setIncomingBlock(BBIdx, NewBB);
-      }
-    } else {
-      // However, the foreach loop is slow for blocks with lots of predecessors
-      // because PHINode::getIncomingBlock is O(n) in # preds.  Instead, walk
-      // the user list of TIBB to find the PHI nodes.
-      SmallPtrSet<PHINode*, 16> UpdatedPHIs;
-    
-      for (Value::use_iterator UI = TIBB->use_begin(), E = TIBB->use_end();
-           UI != E; ) {
-        Value::use_iterator Use = UI++;
-        if (PHINode *PN = dyn_cast<PHINode>(*Use)) {
-          // Remove one entry from each PHI.
-          if (PN->getParent() == DestBB && UpdatedPHIs.insert(PN))
-            PN->setOperand(Use.getOperandNo(), NewBB);
-        }
-      }
+  {
+    unsigned BBIdx = 0;
+    for (BasicBlock::iterator I = DestBB->begin(); isa<PHINode>(I); ++I) {
+      // We no longer enter through TIBB, now we come in through NewBB.
+      // Revector exactly one entry in the PHI node that used to come from
+      // TIBB to come from NewBB.
+      PHINode *PN = cast<PHINode>(I);
+
+      // Reuse the previous value of BBIdx if it lines up.  In cases where we
+      // have multiple phi nodes with *lots* of predecessors, this is a speed
+      // win because we don't have to scan the PHI looking for TIBB.  This
+      // happens because the BB list of PHI nodes are usually in the same
+      // order.
+      if (PN->getIncomingBlock(BBIdx) != TIBB)
+	BBIdx = PN->getBasicBlockIndex(TIBB);
+      PN->setIncomingBlock(BBIdx, NewBB);
     }
   }
    

Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Mon Jun 20 09:38:01 2011
@@ -572,12 +572,12 @@
     // removed, so we just need to splice the blocks.
     BI->eraseFromParent();
     
-    // Move all the instructions in the succ to the pred.
-    I->getInstList().splice(I->end(), Dest->getInstList());
-    
     // Make all PHI nodes that referred to Dest now refer to I as their source.
     Dest->replaceAllUsesWith(I);
 
+    // Move all the instructions in the succ to the pred.
+    I->getInstList().splice(I->end(), Dest->getInstList());
+    
     // Remove the dest block.
     Dest->eraseFromParent();
     

Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Mon Jun 20 09:38:01 2011
@@ -1097,15 +1097,15 @@
         TheCall->replaceAllUsesWith(Returns[0]->getReturnValue());
     }
 
+    // Update PHI nodes that use the ReturnBB to use the AfterCallBB.
+    BasicBlock *ReturnBB = Returns[0]->getParent();
+    ReturnBB->replaceAllUsesWith(AfterCallBB);
+
     // Splice the code from the return block into the block that it will return
     // to, which contains the code that was after the call.
-    BasicBlock *ReturnBB = Returns[0]->getParent();
     AfterCallBB->getInstList().splice(AfterCallBB->begin(),
                                       ReturnBB->getInstList());
 
-    // Update PHI nodes that use the ReturnBB to use the AfterCallBB.
-    ReturnBB->replaceAllUsesWith(AfterCallBB);
-
     // Delete the return instruction now and empty ReturnBB now.
     Returns[0]->eraseFromParent();
     ReturnBB->eraseFromParent();
@@ -1125,8 +1125,8 @@
 
   // Splice the code entry block into calling block, right before the
   // unconditional branch.
-  OrigBB->getInstList().splice(Br, CalleeEntry->getInstList());
   CalleeEntry->replaceAllUsesWith(OrigBB);  // Update PHI nodes
+  OrigBB->getInstList().splice(Br, CalleeEntry->getInstList());
 
   // Remove the unconditional branch.
   OrigBB->getInstList().erase(Br);

Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/Local.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/Local.cpp Mon Jun 20 09:38:01 2011
@@ -427,10 +427,6 @@
   BasicBlock *PredBB = DestBB->getSinglePredecessor();
   assert(PredBB && "Block doesn't have a single predecessor!");
   
-  // Splice all the instructions from PredBB to DestBB.
-  PredBB->getTerminator()->eraseFromParent();
-  DestBB->getInstList().splice(DestBB->begin(), PredBB->getInstList());
-
   // Zap anything that took the address of DestBB.  Not doing this will give the
   // address an invalid value.
   if (DestBB->hasAddressTaken()) {
@@ -445,6 +441,10 @@
   // Anything that branched to PredBB now branches to DestBB.
   PredBB->replaceAllUsesWith(DestBB);
   
+  // Splice all the instructions from PredBB to DestBB.
+  PredBB->getTerminator()->eraseFromParent();
+  DestBB->getInstList().splice(DestBB->begin(), PredBB->getInstList());
+
   if (P) {
     DominatorTree *DT = P->getAnalysisIfAvailable<DominatorTree>();
     if (DT) {
@@ -660,12 +660,17 @@
     // them, which helps expose duplicates, but we have to check all the
     // operands to be safe in case instcombine hasn't run.
     uintptr_t Hash = 0;
+    // This hash algorithm is quite weak as hash functions go, but it seems
+    // to do a good enough job for this particular purpose, and is very quick.
     for (User::op_iterator I = PN->op_begin(), E = PN->op_end(); I != E; ++I) {
-      // This hash algorithm is quite weak as hash functions go, but it seems
-      // to do a good enough job for this particular purpose, and is very quick.
       Hash ^= reinterpret_cast<uintptr_t>(static_cast<Value *>(*I));
       Hash = (Hash << 7) | (Hash >> (sizeof(uintptr_t) * CHAR_BIT - 7));
     }
+    for (PHINode::block_iterator I = PN->block_begin(), E = PN->block_end();
+         I != E; ++I) {
+      Hash ^= reinterpret_cast<uintptr_t>(static_cast<BasicBlock *>(*I));
+      Hash = (Hash << 7) | (Hash >> (sizeof(uintptr_t) * CHAR_BIT - 7));
+    }
     // Avoid colliding with the DenseMap sentinels ~0 and ~0-1.
     Hash >>= 1;
     // If we've never seen this hash value before, it's a unique PHI.

Modified: llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp Mon Jun 20 09:38:01 2011
@@ -47,6 +47,14 @@
     if (It != VMap.end())
       I->setOperand(op, It->second);
   }
+
+  if (PHINode *PN = dyn_cast<PHINode>(I)) {
+    for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
+      ValueToValueMapTy::iterator It = VMap.find(PN->getIncomingBlock(i));
+      if (It != VMap.end())
+        PN->setIncomingBlock(i, cast<BasicBlock>(It->second));
+    }
+  }
 }
 
 /// FoldBlockIntoPredecessor - Folds a basic block into its predecessor if it
@@ -75,13 +83,13 @@
   // Delete the unconditional branch from the predecessor...
   OnlyPred->getInstList().pop_back();
 
-  // Move all definitions in the successor to the predecessor...
-  OnlyPred->getInstList().splice(OnlyPred->end(), BB->getInstList());
-
   // Make all PHI nodes that referred to BB now refer to Pred as their
   // source...
   BB->replaceAllUsesWith(OnlyPred);
 
+  // Move all definitions in the successor to the predecessor...
+  OnlyPred->getInstList().splice(OnlyPred->end(), BB->getInstList());
+
   std::string OldName = BB->getName();
 
   // Erase basic block from the function...
@@ -247,16 +255,14 @@
       // the successor of the latch block.  The successor of the exit block will
       // be updated specially after unrolling all the way.
       if (*BB != LatchBlock)
-        for (Value::use_iterator UI = (*BB)->use_begin(), UE = (*BB)->use_end();
-             UI != UE;) {
-          Instruction *UseInst = cast<Instruction>(*UI);
-          ++UI;
-          if (isa<PHINode>(UseInst) && !L->contains(UseInst)) {
-            PHINode *phi = cast<PHINode>(UseInst);
-            Value *Incoming = phi->getIncomingValueForBlock(*BB);
-            phi->addIncoming(Incoming, New);
-          }
-        }
+        for (succ_iterator SI = succ_begin(*BB), SE = succ_end(*BB); SI != SE;
+             ++SI)
+          if (!L->contains(*SI))
+            for (BasicBlock::iterator BBI = (*SI)->begin(), BBE = (*SI)->end();
+                 PHINode *phi = dyn_cast<PHINode>(BBI); ++BBI) {
+              Value *Incoming = phi->getIncomingValueForBlock(*BB);
+              phi->addIncoming(Incoming, New);
+            }
 
       // Keep track of new headers and latches as we create them, so that
       // we can insert the proper branches later.
@@ -288,24 +294,20 @@
   // successor blocks, update them to use the appropriate values computed as the
   // last iteration of the loop.
   if (Count != 1) {
-    SmallPtrSet<PHINode*, 8> Users;
-    for (Value::use_iterator UI = LatchBlock->use_begin(),
-         UE = LatchBlock->use_end(); UI != UE; ++UI)
-      if (PHINode *phi = dyn_cast<PHINode>(*UI))
-        Users.insert(phi);
-    
     BasicBlock *LastIterationBB = cast<BasicBlock>(LastValueMap[LatchBlock]);
-    for (SmallPtrSet<PHINode*,8>::iterator SI = Users.begin(), SE = Users.end();
+    for (succ_iterator SI = succ_begin(LatchBlock), SE = succ_end(LatchBlock);
          SI != SE; ++SI) {
-      PHINode *PN = *SI;
-      Value *InVal = PN->removeIncomingValue(LatchBlock, false);
-      // If this value was defined in the loop, take the value defined by the
-      // last iteration of the loop.
-      if (Instruction *InValI = dyn_cast<Instruction>(InVal)) {
-        if (L->contains(InValI))
-          InVal = LastValueMap[InVal];
+      for (BasicBlock::iterator BBI = (*SI)->begin(), BBE = (*SI)->end();
+           PHINode *PN = dyn_cast<PHINode>(BBI); ++BBI) {
+        Value *InVal = PN->removeIncomingValue(LatchBlock, false);
+        // If this value was defined in the loop, take the value defined by the
+        // last iteration of the loop.
+        if (Instruction *InValI = dyn_cast<Instruction>(InVal)) {
+          if (L->contains(InValI))
+            InVal = LastValueMap[InVal];
+        }
+        PN->addIncoming(InVal, LastIterationBB);
       }
-      PN->addIncoming(InVal, LastIterationBB);
     }
   }
 
@@ -352,11 +354,16 @@
       // Replace the conditional branch with an unconditional one.
       BranchInst::Create(Dest, Term);
       Term->eraseFromParent();
-      // Merge adjacent basic blocks, if possible.
-      if (BasicBlock *Fold = FoldBlockIntoPredecessor(Dest, LI)) {
+    }
+  }
+
+  // Merge adjacent basic blocks, if possible.
+  for (unsigned i = 0, e = Latches.size(); i != e; ++i) {
+    BranchInst *Term = cast<BranchInst>(Latches[i]->getTerminator());
+    if (Term->isUnconditional()) {
+      BasicBlock *Dest = Term->getSuccessor(0);
+      if (BasicBlock *Fold = FoldBlockIntoPredecessor(Dest, LI))
         std::replace(Latches.begin(), Latches.end(), Dest, Fold);
-        std::replace(Headers.begin(), Headers.end(), Dest, Fold);
-      }
     }
   }
   

Modified: llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp Mon Jun 20 09:38:01 2011
@@ -16,6 +16,7 @@
 #include "llvm/Type.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
+#include "llvm/Instructions.h"
 #include "llvm/Metadata.h"
 #include "llvm/ADT/SmallVector.h"
 using namespace llvm;
@@ -128,6 +129,19 @@
              "Referenced value not in value map!");
   }
 
+  // Remap phi nodes' incoming blocks.
+  if (PHINode *PN = dyn_cast<PHINode>(I)) {
+    for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
+      Value *V = MapValue(PN->getIncomingBlock(i), VMap, Flags);
+      // If we aren't ignoring missing entries, assert that something happened.
+      if (V != 0)
+        PN->setIncomingBlock(i, cast<BasicBlock>(V));
+      else
+        assert((Flags & RF_IgnoreMissingEntries) &&
+               "Referenced block not in value map!");
+    }
+  }
+
   // Remap attached metadata.
   SmallVector<std::pair<unsigned, MDNode *>, 4> MDs;
   I->getAllMetadata(MDs);

Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/BasicBlock.cpp (original)
+++ llvm/trunk/lib/VMCore/BasicBlock.cpp Mon Jun 20 09:38:01 2011
@@ -308,3 +308,19 @@
   return New;
 }
 
+void BasicBlock::replaceSuccessorsPhiUsesWith(BasicBlock *New) {
+  TerminatorInst *TI = getTerminator();
+  if (!TI)
+    // Cope with being called on a BasicBlock that doesn't have a terminator
+    // yet. Clang's CodeGenFunction::EmitReturnBlock() likes to do this.
+    return;
+  for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) {
+    BasicBlock *Succ = TI->getSuccessor(i);
+    for (iterator II = Succ->begin(); PHINode *PN = dyn_cast<PHINode>(II);
+         ++II) {
+      int i;
+      while ((i = PN->getBasicBlockIndex(this)) >= 0)
+        PN->setIncomingBlock(i, New);
+    }
+  }
+}

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Jun 20 09:38:01 2011
@@ -87,11 +87,8 @@
   : Instruction(PN.getType(), Instruction::PHI,
                 allocHungoffUses(PN.getNumOperands()), PN.getNumOperands()),
     ReservedSpace(PN.getNumOperands()) {
-  Use *OL = OperandList;
-  for (unsigned i = 0, e = PN.getNumOperands(); i != e; i+=2) {
-    OL[i] = PN.getOperand(i);
-    OL[i+1] = PN.getOperand(i+1);
-  }
+  std::copy(PN.op_begin(), PN.op_end(), op_begin());
+  std::copy(PN.block_begin(), PN.block_end(), block_begin());
   SubclassOptionalData = PN.SubclassOptionalData;
 }
 
@@ -99,31 +96,37 @@
   dropHungoffUses();
 }
 
+Use *PHINode::allocHungoffUses(unsigned N) const {
+  // Allocate the array of Uses of the incoming values, followed by a pointer
+  // (with bottom bit set) to the User, followed by the array of pointers to
+  // the incoming basic blocks.
+  size_t size = N * sizeof(Use) + sizeof(Use::UserRef)
+    + N * sizeof(BasicBlock*);
+  Use *Begin = static_cast<Use*>(::operator new(size));
+  Use *End = Begin + N;
+  (void) new(End) Use::UserRef(const_cast<PHINode*>(this), 1);
+  return Use::initTags(Begin, End);
+}
+
 // removeIncomingValue - Remove an incoming value.  This is useful if a
 // predecessor basic block is deleted.
 Value *PHINode::removeIncomingValue(unsigned Idx, bool DeletePHIIfEmpty) {
-  unsigned NumOps = getNumOperands();
-  Use *OL = OperandList;
-  assert(Idx*2 < NumOps && "BB not in PHI node!");
-  Value *Removed = OL[Idx*2];
+  Value *Removed = getIncomingValue(Idx);
 
   // Move everything after this operand down.
   //
   // FIXME: we could just swap with the end of the list, then erase.  However,
-  // client might not expect this to happen.  The code as it is thrashes the
+  // clients might not expect this to happen.  The code as it is thrashes the
   // use/def lists, which is kinda lame.
-  for (unsigned i = (Idx+1)*2; i != NumOps; i += 2) {
-    OL[i-2] = OL[i];
-    OL[i-2+1] = OL[i+1];
-  }
+  std::copy(op_begin() + Idx + 1, op_end(), op_begin() + Idx);
+  std::copy(block_begin() + Idx + 1, block_end(), block_begin() + Idx);
 
   // Nuke the last value.
-  OL[NumOps-2].set(0);
-  OL[NumOps-2+1].set(0);
-  NumOperands = NumOps-2;
+  Op<-1>().set(0);
+  --NumOperands;
 
   // If the PHI node is dead, because it has zero entries, nuke it now.
-  if (NumOps == 2 && DeletePHIIfEmpty) {
+  if (getNumOperands() == 0 && DeletePHIIfEmpty) {
     // If anyone is using this PHI, make them use a dummy value instead...
     replaceAllUsesWith(UndefValue::get(getType()));
     eraseFromParent();
@@ -137,15 +140,18 @@
 ///
 void PHINode::growOperands() {
   unsigned e = getNumOperands();
-  // Multiply by 1.5 and round down so the result is still even.
-  unsigned NumOps = e + e / 4 * 2;
+  unsigned NumOps = e + e / 2;
   if (NumOps < 4) NumOps = 4;      // 4 op PHI nodes are VERY common.
 
+  Use *OldOps = op_begin();
+  BasicBlock **OldBlocks = block_begin();
+
   ReservedSpace = NumOps;
-  Use *OldOps = OperandList;
-  Use *NewOps = allocHungoffUses(NumOps);
-  std::copy(OldOps, OldOps + e, NewOps);
-  OperandList = NewOps;
+  OperandList = allocHungoffUses(ReservedSpace);
+
+  std::copy(OldOps, OldOps + e, op_begin());
+  std::copy(OldBlocks, OldBlocks + e, block_begin());
+
   Use::zap(OldOps, OldOps + e, true);
 }
 

Modified: llvm/trunk/lib/VMCore/User.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/User.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/User.cpp (original)
+++ llvm/trunk/lib/VMCore/User.cpp Mon Jun 20 09:38:01 2011
@@ -40,8 +40,10 @@
 //===----------------------------------------------------------------------===//
 
 Use *User::allocHungoffUses(unsigned N) const {
-  Use *Begin = static_cast<Use*>(::operator new(sizeof(Use) * N
-                                                + sizeof(Use::UserRef)));
+  // Allocate the array of Uses, followed by a pointer (with bottom bit set) to
+  // the User.
+  size_t size = N * sizeof(Use) + sizeof(Use::UserRef);
+  Use *Begin = static_cast<Use*>(::operator new(size));
   Use *End = Begin + N;
   (void) new(End) Use::UserRef(const_cast<User*>(this), 1);
   return Use::initTags(Begin, End);

Modified: llvm/trunk/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Value.cpp (original)
+++ llvm/trunk/lib/VMCore/Value.cpp Mon Jun 20 09:38:01 2011
@@ -305,6 +305,9 @@
 
     U.set(New);
   }
+
+  if (BasicBlock *BB = dyn_cast<BasicBlock>(this))
+    BB->replaceSuccessorsPhiUsesWith(cast<BasicBlock>(New));
 }
 
 void Value::replaceAllUsesWith(Value *New) {

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=133435&r1=133434&r2=133435&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Jun 20 09:38:01 2011
@@ -1139,9 +1139,6 @@
   for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
     Assert1(PN.getType() == PN.getIncomingValue(i)->getType(),
             "PHI node operands are not the same type as the result!", &PN);
-    Assert1(isa<BasicBlock>(PN.getOperand(
-                PHINode::getOperandNumForIncomingBlock(i))),
-            "PHI node incoming block is not a BasicBlock!", &PN);
   }
 
   // All other PHI node constraints are checked in the visitBasicBlock method.



From rafael.espindola at gmail.com  Mon Jun 20 09:46:12 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Mon, 20 Jun 2011 10:46:12 -0400
Subject: [llvm-commits] [dragonegg] r133427 - in /dragonegg/trunk:
 Makefile README extras/do_self_strap gcc-patches/ www/index.html
In-Reply-To: <20110620074311.1AA7B2A6C12D@llvm.org>
References: <20110620074311.1AA7B2A6C12D@llvm.org>
Message-ID: <4DFF5D34.4000501@gmail.com>

On 11-06-20 3:43 AM, Duncan Sands wrote:
> Author: baldrick
> Date: Mon Jun 20 02:43:10 2011
> New Revision: 133427
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133427&view=rev
> Log:
> Dragonegg no longer requires a patched version of gcc.  Update the docs
> to reflect that.  Also, change the Makefile so that it defaults to
> building for "gcc" rather than "gcc-4.5".  Use the GCC variable to
> override as explained in the README.

That is a big milestone, congratulations!

Cheers,
Rafael

From jay.foad at gmail.com  Mon Jun 20 09:46:47 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Mon, 20 Jun 2011 14:46:47 -0000
Subject: [llvm-commits] [llvm] r133436 -
	/llvm/trunk/test/Transforms/GVN/2011-04-27-phioperands.ll
Message-ID: <20110620144647.8ECCC2A6C12C@llvm.org>

Author: foad
Date: Mon Jun 20 09:46:47 2011
New Revision: 133436

URL: http://llvm.org/viewvc/llvm-project?rev=133436&view=rev
Log:
This is an automatically reduced test case that crashed in GVN, at some
point during the development of the phi operand changes.

Added:
    llvm/trunk/test/Transforms/GVN/2011-04-27-phioperands.ll

Added: llvm/trunk/test/Transforms/GVN/2011-04-27-phioperands.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/GVN/2011-04-27-phioperands.ll?rev=133436&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/GVN/2011-04-27-phioperands.ll (added)
+++ llvm/trunk/test/Transforms/GVN/2011-04-27-phioperands.ll Mon Jun 20 09:46:47 2011
@@ -0,0 +1,106 @@
+; RUN: opt %s -gvn -disable-output
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64"
+
+ at nuls = external global [10 x i8]
+
+define fastcc void @p_ere() nounwind {
+entry:
+  br label %"<bb 5>"
+
+"<L18>.i":
+  br i1 undef, label %"<bb 3>.i30.i", label %doemit.exit51.i
+
+"<bb 3>.i30.i":
+  unreachable
+
+doemit.exit51.i:
+  br label %"<bb 53>.i"
+
+"<L19>.i":
+  br i1 undef, label %"<bb 3>.i55.i", label %doemit.exit76.i
+
+"<bb 3>.i55.i":
+  unreachable
+
+doemit.exit76.i:
+  br label %"<bb 53>.i"
+
+"<L98>.i":
+  store i8* getelementptr inbounds ([10 x i8]* @nuls, i64 0, i64 0), i8** undef, align 8
+  br label %"<bb 53>.i"
+
+"<L99>.i":
+  br label %"<bb 53>.i"
+
+"<L24>.i":
+  br i1 undef, label %"<bb 53>.i", label %"<bb 35>.i"
+
+"<bb 35>.i":
+  br label %"<bb 53>.i"
+
+"<L28>.i":
+  br label %"<bb 53>.i"
+
+"<L29>.i":
+  br label %"<bb 53>.i"
+
+"<L39>.i":
+  br label %"<bb 53>.i"
+
+"<bb 53>.i":
+  %wascaret_2.i = phi i32 [ 0, %"<L39>.i" ], [ 0, %"<L29>.i" ], [ 0, %"<L28>.i" ], [ 0, %"<bb 35>.i" ], [ 0, %"<L99>.i" ], [ 0, %"<L98>.i" ], [ 0, %doemit.exit76.i ], [ 1, %doemit.exit51.i ], [ 0, %"<L24>.i" ]
+  %D.5496_84.i = load i8** undef, align 8
+  br i1 undef, label %"<bb 54>.i", label %"<bb 5>"
+
+"<bb 54>.i":
+  br i1 undef, label %"<bb 5>", label %"<bb 58>.i"
+
+"<bb 58>.i":
+  br i1 undef, label %"<bb 64>.i", label %"<bb 59>.i"
+
+"<bb 59>.i":
+  br label %"<bb 64>.i"
+
+"<bb 64>.i":
+  switch i32 undef, label %"<bb 5>" [
+    i32 42, label %"<L54>.i"
+    i32 43, label %"<L55>.i"
+    i32 63, label %"<L56>.i"
+    i32 123, label %"<bb 5>.i258.i"
+  ]
+
+"<L54>.i":
+  br i1 undef, label %"<bb 3>.i105.i", label %doemit.exit127.i
+
+"<bb 3>.i105.i":
+  unreachable
+
+doemit.exit127.i:
+  unreachable
+
+"<L55>.i":
+  br i1 undef, label %"<bb 3>.i157.i", label %"<bb 5>"
+
+"<bb 3>.i157.i":
+  unreachable
+
+"<L56>.i":
+  br label %"<bb 5>"
+
+"<bb 5>.i258.i":
+  unreachable
+
+"<bb 5>":
+  switch i32 undef, label %"<L39>.i" [
+    i32 36, label %"<L19>.i"
+    i32 94, label %"<L18>.i"
+    i32 124, label %"<L98>.i"
+    i32 42, label %"<L99>.i"
+    i32 43, label %"<L99>.i"
+    i32 46, label %"<L24>.i"
+    i32 63, label %"<L99>.i"
+    i32 91, label %"<L28>.i"
+    i32 92, label %"<L29>.i"
+  ]
+}



From baldrick at free.fr  Mon Jun 20 10:02:48 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 20 Jun 2011 17:02:48 +0200
Subject: [llvm-commits] [dragonegg] r133427 - in /dragonegg/trunk:
 Makefile README extras/do_self_strap gcc-patches/ www/index.html
In-Reply-To: <4DFF5D34.4000501@gmail.com>
References: <20110620074311.1AA7B2A6C12D@llvm.org> <4DFF5D34.4000501@gmail.com>
Message-ID: <4DFF6118.4030908@free.fr>

>> Dragonegg no longer requires a patched version of gcc.  Update the docs
>> to reflect that.  Also, change the Makefile so that it defaults to
>> building for "gcc" rather than "gcc-4.5".  Use the GCC variable to
>> override as explained in the README.
>
> That is a big milestone, congratulations!

Thanks Rafael :)  This should be a big improvement for users: no need to
build gcc, just use your system gcc [*].

Ciao, Duncan.

[*] That said I can't build yet against my system gcc yet, I think due to
Debian's multiarch changes :(

From rdivacky at freebsd.org  Mon Jun 20 10:28:39 2011
From: rdivacky at freebsd.org (Roman Divacky)
Date: Mon, 20 Jun 2011 15:28:39 -0000
Subject: [llvm-commits] [llvm] r133439 - in /llvm/trunk:
 lib/Target/PowerPC/PPCISelDAGToDAG.cpp
 test/CodeGen/PowerPC/ppc64-32bit-addic.ll
Message-ID: <20110620152839.F1FAE2A6C12C@llvm.org>

Author: rdivacky
Date: Mon Jun 20 10:28:39 2011
New Revision: 133439

URL: http://llvm.org/viewvc/llvm-project?rev=133439&view=rev
Log:
Don't apply on PPC64 the 32bit ADDIC optimizations as there's no overflow
with 32bit values.

Added:
    llvm/trunk/test/CodeGen/PowerPC/ppc64-32bit-addic.ll
Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=133439&r1=133438&r2=133439&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Mon Jun 20 10:28:39 2011
@@ -610,6 +610,9 @@
   DebugLoc dl = N->getDebugLoc();
   unsigned Imm;
   ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
+  EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
+  bool isPPC64 = (PtrVT == MVT::i64);
+
   if (isInt32Immediate(N->getOperand(1), Imm)) {
     // We can codegen setcc op, imm very efficiently compared to a brcond.
     // Check for those cases here.
@@ -624,6 +627,7 @@
         return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
       }
       case ISD::SETNE: {
+        if (isPPC64) break;
         SDValue AD =
           SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
                                          Op, getI32Imm(~0U)), 0);
@@ -647,6 +651,7 @@
       switch (CC) {
       default: break;
       case ISD::SETEQ:
+        if (isPPC64) break;
         Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
                                             Op, getI32Imm(1)), 0);
         return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
@@ -655,6 +660,7 @@
                                                              getI32Imm(0)), 0),
                                       Op.getValue(1));
       case ISD::SETNE: {
+        if (isPPC64) break;
         Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
         SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
                                             Op, getI32Imm(~0U));
@@ -996,22 +1002,25 @@
   }
   case ISD::SELECT_CC: {
     ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
+    EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
+    bool isPPC64 = (PtrVT == MVT::i64);
 
     // Handle the setcc cases here.  select_cc lhs, 0, 1, 0, cc
-    if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
-      if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
-        if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
-          if (N1C->isNullValue() && N3C->isNullValue() &&
-              N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
-              // FIXME: Implement this optzn for PPC64.
-              N->getValueType(0) == MVT::i32) {
-            SDNode *Tmp =
-              CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
-                                     N->getOperand(0), getI32Imm(~0U));
-            return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
-                                        SDValue(Tmp, 0), N->getOperand(0),
-                                        SDValue(Tmp, 1));
-          }
+    if (!isPPC64)
+      if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+        if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
+          if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
+            if (N1C->isNullValue() && N3C->isNullValue() &&
+                N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
+                // FIXME: Implement this optzn for PPC64.
+                N->getValueType(0) == MVT::i32) {
+              SDNode *Tmp =
+                CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
+                                       N->getOperand(0), getI32Imm(~0U));
+              return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
+                                          SDValue(Tmp, 0), N->getOperand(0),
+                                          SDValue(Tmp, 1));
+            }
 
     SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
     unsigned BROpc = getPredicateForSetCC(CC);

Added: llvm/trunk/test/CodeGen/PowerPC/ppc64-32bit-addic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc64-32bit-addic.ll?rev=133439&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/ppc64-32bit-addic.ll (added)
+++ llvm/trunk/test/CodeGen/PowerPC/ppc64-32bit-addic.ll Mon Jun 20 10:28:39 2011
@@ -0,0 +1,29 @@
+; Check that the ADDIC optimizations are not applied on PPC64
+; RUN: llc < %s | FileCheck %s
+; ModuleID = 'os_unix.c'
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-freebsd9.0"
+
+define i32 @notZero(i32 %call) nounwind {
+entry:
+; CHECK-NOT: addic
+  %not.tobool = icmp ne i32 %call, 0
+  %. = zext i1 %not.tobool to i32
+  ret i32 %.
+}
+
+define i32 @isMinusOne(i32 %call) nounwind {
+entry:
+; CHECK-NOT: addic
+  %not.tobool = icmp eq i32 %call, -1
+  %. = zext i1 %not.tobool to i32
+  ret i32 %.
+}
+
+define i32 @isNotMinusOne(i32 %call) nounwind {
+entry:
+; CHECK-NOT: addic
+  %not.tobool = icmp ne i32 %call, -1
+  %. = zext i1 %not.tobool to i32
+  ret i32 %.
+}



From jay.foad at gmail.com  Mon Jun 20 10:43:15 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Mon, 20 Jun 2011 16:43:15 +0100
Subject: [llvm-commits] [llvm] r133412 - in /llvm/trunk:
 include/llvm/Constants.h lib/Analysis/ConstantFolding.cpp
 lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp
 lib/CodeGen/ShadowStackGC.cpp lib/Transforms/IPO/GlobalOpt.cpp
 lib/Transform
Message-ID: <BANLkTimBn5-=U7Re=p4gkh7CE3A7N5gf=Y+w6MD2teoEXDer6Q@mail.gmail.com>

> It would be "really really nice" if the ConstantStruct::get and
> ConstantVector::get methods didn't make temporary std::vectors.

How about this then?

Patch 1 extends ConstantUniqueMap with a new template parameter
ValRefType, representing a const reference to ValType. Normally this
would just be const ValType&, but when ValType is a std::vector, we
want to use ArrayRef as the reference type.

I had to add a conversion operator to ArrayRef to get this to work. Is
this reasonable? (I've only been using C++ for 15 years so I haven't
really got the hang of it yet.) This also makes the existing
ArrayRef::vec() somewhat redundant, but I didn't remove it.

Patches 2/3/4 tidy up the get() methods of ConstantVector/Array/Struct
to use ArrayRef throughout.

Tested with "make all check-all", LLVM and Clang. I don't think
llvm-gcc-4.2 or dragonegg need any changes, based on a quick grep.

OK to commit?

Thanks,
Jay.
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From justin.holewinski at gmail.com  Mon Jun 20 10:56:20 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Mon, 20 Jun 2011 15:56:20 -0000
Subject: [llvm-commits] [llvm] r133443 - in /llvm/trunk/lib/Target/PTX:
 PTXAsmPrinter.cpp PTXInstrInfo.cpp PTXInstrInfo.h PTXInstrInfo.td
Message-ID: <20110620155620.D18072A6C12C@llvm.org>

Author: jholewinski
Date: Mon Jun 20 10:56:20 2011
New Revision: 133443

URL: http://llvm.org/viewvc/llvm-project?rev=133443&view=rev
Log:
PTX: Add basic register spilling code

The current implementation generates stack loads/stores, which are
really just mov instructions from/to "special" registers.  This may
not be the most efficient implementation, compared to an approach where
the stack registers are directly folded into instructions, but this is
easier to implement and I have yet to see a case where ptxas is unable
to see through this kind of register usage and know what is really
going on.

Modified:
    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.h
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.td

Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133443&r1=133442&r2=133443&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Mon Jun 20 10:56:20 2011
@@ -23,6 +23,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/CodeGen/AsmPrinter.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
@@ -194,6 +195,18 @@
     def += ';';
     OutStreamer.EmitRawText(Twine(def));
   }
+
+  const MachineFrameInfo* FrameInfo = MF->getFrameInfo();
+  DEBUG(dbgs() << "Have " << FrameInfo->getNumObjects() << " frame object(s)\n");
+  for (unsigned i = 0, e = FrameInfo->getNumObjects(); i != e; ++i) {
+    DEBUG(dbgs() << "Size of object: " << FrameInfo->getObjectSize(i) << "\n");
+    std::string def = "\t.reg .b";
+    def += utostr(FrameInfo->getObjectSize(i)*8); // Convert to bits
+    def += " s";
+    def += utostr(i);
+    def += ";";
+    OutStreamer.EmitRawText(Twine(def));
+  }
 }
 
 void PTXAsmPrinter::EmitInstruction(const MachineInstr *MI) {

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=133443&r1=133442&r2=133443&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Mon Jun 20 10:56:20 2011
@@ -288,6 +288,81 @@
   }
 }
 
+// Memory operand folding for spills
+void PTXInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
+                                       MachineBasicBlock::iterator MII,
+                                       unsigned SrcReg, bool isKill, int FrameIdx,
+                                       const TargetRegisterClass *RC,
+                                       const TargetRegisterInfo *TRI) const {
+  MachineInstr& MI = *MII;
+  DebugLoc DL = MI.getDebugLoc();
+
+  DEBUG(dbgs() << "storeRegToStackSlot: " << MI);
+
+  int OpCode;
+
+  // Select the appropriate opcode based on the register class
+  if (RC == PTX::RegI16RegisterClass) {
+    OpCode = PTX::STACKSTOREI16;
+  }
+  else if (RC == PTX::RegI32RegisterClass) {
+    OpCode = PTX::STACKSTOREI32;
+  }
+  else if (RC == PTX::RegI64RegisterClass) {
+    OpCode = PTX::STACKSTOREI32;
+  }
+  else if (RC == PTX::RegF32RegisterClass) {
+    OpCode = PTX::STACKSTOREF32;
+  }
+  else if (RC == PTX::RegF64RegisterClass) {
+    OpCode = PTX::STACKSTOREF64;
+  }
+
+  // Build the store instruction (really a mov)
+  MachineInstrBuilder MIB = BuildMI(MBB, MII, DL, get(OpCode));
+  MIB.addImm(FrameIdx);
+  MIB.addReg(SrcReg);
+
+  AddDefaultPredicate(MIB);
+}
+
+void PTXInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
+                                        MachineBasicBlock::iterator MII,
+                                        unsigned DestReg, int FrameIdx,
+                                        const TargetRegisterClass *RC,
+                                        const TargetRegisterInfo *TRI) const {
+  MachineInstr& MI = *MII;
+  DebugLoc DL = MI.getDebugLoc();
+
+  DEBUG(dbgs() << "loadRegToStackSlot: " << MI);
+
+  int OpCode;
+
+  // Select the appropriate opcode based on the register class
+  if (RC == PTX::RegI16RegisterClass) {
+    OpCode = PTX::STACKLOADI16;
+  }
+  else if (RC == PTX::RegI32RegisterClass) {
+    OpCode = PTX::STACKLOADI32;
+  }
+  else if (RC == PTX::RegI64RegisterClass) {
+    OpCode = PTX::STACKLOADI32;
+  }
+  else if (RC == PTX::RegF32RegisterClass) {
+    OpCode = PTX::STACKLOADF32;
+  }
+  else if (RC == PTX::RegF64RegisterClass) {
+    OpCode = PTX::STACKLOADF64;
+  }
+
+  // Build the load instruction (really a mov)
+  MachineInstrBuilder MIB = BuildMI(MBB, MII, DL, get(OpCode));
+  MIB.addReg(DestReg);
+  MIB.addImm(FrameIdx);
+
+  AddDefaultPredicate(MIB);
+}
+
 // static helper routines
 
 MachineSDNode *PTXInstrInfo::

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.h?rev=133443&r1=133442&r2=133443&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.h Mon Jun 20 10:56:20 2011
@@ -84,6 +84,29 @@
                                 const SmallVectorImpl<MachineOperand> &Cond,
                                 DebugLoc DL) const;
 
+  // Memory operand folding for spills
+  // TODO: Implement this eventually and get rid of storeRegToStackSlot and
+  //       loadRegFromStackSlot.  Doing so will get rid of the "stack" registers
+  //       we currently use to spill, though I doubt the overall effect on ptxas
+  //       output will be large.  I have yet to see a case where ptxas is unable
+  //       to see through the "stack" register usage and hence generates
+  //       efficient code anyway.
+  // virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
+  //                                             MachineInstr* MI,
+  //                                          const SmallVectorImpl<unsigned> &Ops,
+  //                                             int FrameIndex) const;
+
+  virtual void storeRegToStackSlot(MachineBasicBlock& MBB,
+                                   MachineBasicBlock::iterator MII,
+                                   unsigned SrcReg, bool isKill, int FrameIndex,
+                                   const TargetRegisterClass* RC,
+                                   const TargetRegisterInfo* TRI) const;
+  virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
+                                    MachineBasicBlock::iterator MII,
+                                    unsigned DestReg, int FrameIdx,
+                                    const TargetRegisterClass *RC,
+                                    const TargetRegisterInfo *TRI) const;
+
   // static helper routines
 
   static MachineSDNode *GetPTXMachineNode(SelectionDAG *DAG, unsigned Opcode,

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=133443&r1=133442&r2=133443&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Mon Jun 20 10:56:20 2011
@@ -977,6 +977,30 @@
   def RET  : InstPTX<(outs), (ins), "ret",  [(PTXret)]>;
 }
 
+///===- Spill Instructions ------------------------------------------------===//
+// Special instructions used for stack spilling
+def STACKSTOREI16 : InstPTX<(outs), (ins i32imm:$d, RegI16:$a),
+                            "mov.u16\ts$d, $a", []>;
+def STACKSTOREI32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
+                            "mov.u32\ts$d, $a", []>;
+def STACKSTOREI64 : InstPTX<(outs), (ins i32imm:$d, RegI64:$a),
+                            "mov.u64\ts$d, $a", []>;
+def STACKSTOREF32 : InstPTX<(outs), (ins i32imm:$d, RegF32:$a),
+                            "mov.f32\ts$d, $a", []>;
+def STACKSTOREF64 : InstPTX<(outs), (ins i32imm:$d, RegF64:$a),
+                            "mov.f64\ts$d, $a", []>;
+
+def STACKLOADI16 : InstPTX<(outs), (ins RegI16:$d, i32imm:$a),
+                           "mov.u16\t$d, s$a", []>;
+def STACKLOADI32 : InstPTX<(outs), (ins RegI32:$d, i32imm:$a),
+                           "mov.u32\t$d, s$a", []>;
+def STACKLOADI64 : InstPTX<(outs), (ins RegI64:$d, i32imm:$a),
+                           "mov.u64\t$d, s$a", []>;
+def STACKLOADF32 : InstPTX<(outs), (ins RegF32:$d, i32imm:$a),
+                           "mov.f32\t$d, s$a", []>;
+def STACKLOADF64 : InstPTX<(outs), (ins RegF64:$d, i32imm:$a),
+                           "mov.f64\t$d, s$a", []>;
+
 ///===- Intrinsic Instructions --------------------------------------------===//
 
 include "PTXIntrinsicInstrInfo.td"



From fvbommel at gmail.com  Mon Jun 20 11:03:14 2011
From: fvbommel at gmail.com (Frits van Bommel)
Date: Mon, 20 Jun 2011 18:03:14 +0200
Subject: [llvm-commits] [llvm] r133435 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/Target/CppBackend/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
In-Reply-To: <20110620143801.6C0D72A6C124@llvm.org>
References: <20110620143801.6C0D72A6C124@llvm.org>
Message-ID: <BANLkTim7oppnuuPYy-+QLtX9grqafusXFQ@mail.gmail.com>

> ?void PHINode::growOperands() {
> ? unsigned e = getNumOperands();
> - ?// Multiply by 1.5 and round down so the result is still even.
> - ?unsigned NumOps = e + e / 4 * 2;
> + ?unsigned NumOps = e + e / 2;
> ? if (NumOps < 4) NumOps = 4; ? ? ?// 4 op PHI nodes are VERY common.

Wouldn't it now be 2-op PHI nodes that are "VERY common"?
(since 2 of the ops used to be basic blocks)


From stoklund at 2pi.dk  Mon Jun 20 11:59:03 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 20 Jun 2011 09:59:03 -0700
Subject: [llvm-commits] [llvm] r133443 - in /llvm/trunk/lib/Target/PTX:
 PTXAsmPrinter.cpp PTXInstrInfo.cpp PTXInstrInfo.h PTXInstrInfo.td
In-Reply-To: <20110620155620.D18072A6C12C@llvm.org>
References: <20110620155620.D18072A6C12C@llvm.org>
Message-ID: <2C3AFB7B-D930-4B85-BFA7-5589ADCEF78E@2pi.dk>


On Jun 20, 2011, at 8:56 AM, Justin Holewinski wrote:

> +  int OpCode;
> +
> +  // Select the appropriate opcode based on the register class
> +  if (RC == PTX::RegI16RegisterClass) {
> +    OpCode = PTX::STACKSTOREI16;
> +  }
> +  else if (RC == PTX::RegI32RegisterClass) {
> +    OpCode = PTX::STACKSTOREI32;
> +  }
> +  else if (RC == PTX::RegI64RegisterClass) {
> +    OpCode = PTX::STACKSTOREI32;
> +  }
> +  else if (RC == PTX::RegF32RegisterClass) {
> +    OpCode = PTX::STACKSTOREF32;
> +  }
> +  else if (RC == PTX::RegF64RegisterClass) {
> +    OpCode = PTX::STACKSTOREF64;
> +  }

Please add an assertion for the unknown register class case.

Also, format your else-ifs like so:

} else if (..) {

/jakob


From aggarwa4 at illinois.edu  Mon Jun 20 11:55:27 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 20 Jun 2011 16:55:27 -0000
Subject: [llvm-commits] [poolalloc] r133444 -
	/poolalloc/trunk/lib/AssistDS/SimplifyLoad.cpp
Message-ID: <20110620165527.E6FC42A6C12C@llvm.org>

Author: aggarwa4
Date: Mon Jun 20 11:55:27 2011
New Revision: 133444

URL: http://llvm.org/viewvc/llvm-project?rev=133444&view=rev
Log:
Remove extraneous printing.

Modified:
    poolalloc/trunk/lib/AssistDS/SimplifyLoad.cpp

Modified: poolalloc/trunk/lib/AssistDS/SimplifyLoad.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/SimplifyLoad.cpp?rev=133444&r1=133443&r2=133444&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/SimplifyLoad.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/SimplifyLoad.cpp Mon Jun 20 11:55:27 2011
@@ -63,10 +63,6 @@
                   if(const PointerType *PTy = dyn_cast<PointerType>(CE->getOperand(0)->getType()))
                     if(PTy->getElementType() == CI->getType()) {
                       LoadInst *LINew = new LoadInst(CE->getOperand(0), "", LI);
-                      LINew->dump();
-                      LI->dump();
-                      CI->dump();
-                      CE->dump();
                       CI->replaceAllUsesWith(LINew);
                     }
                 }



From aggarwa4 at illinois.edu  Mon Jun 20 11:56:57 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 20 Jun 2011 16:56:57 -0000
Subject: [llvm-commits] [poolalloc] r133445 - in /poolalloc/trunk:
 include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp
Message-ID: <20110620165657.986972A6C12C@llvm.org>

Author: aggarwa4
Date: Mon Jun 20 11:56:57 2011
New Revision: 133445

URL: http://llvm.org/viewvc/llvm-project?rev=133445&view=rev
Log:
Handle calls to va_copy, and add a new counter for the
values in the copied va_list.

Modified:
    poolalloc/trunk/include/assistDS/TypeChecks.h
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp

Modified: poolalloc/trunk/include/assistDS/TypeChecks.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=133445&r1=133444&r2=133445&view=diff
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecks.h (original)
+++ poolalloc/trunk/include/assistDS/TypeChecks.h Mon Jun 20 11:56:57 2011
@@ -42,6 +42,8 @@
   std::list<Function *> ByValFunctions;
   std::list<Function *> AddressTakenFunctions;
   std::set<Instruction*> IndCalls;
+  // Map of VAList to current count
+  std::map<Value*, Value*> CounterMap;
 
   // Analysis from other passes.
   TargetData *TD;

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133445&r1=133444&r2=133445&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Mon Jun 20 11:56:57 2011
@@ -260,6 +260,7 @@
     ByValFunctions.pop_back();
     modified |= visitByValFunction(M, *F);
   }
+  
 
   // NOTE:must visit before VAArgFunctions, to populate the map with the
   // correct cloned functions.
@@ -468,10 +469,24 @@
       Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
       if(VAListFunctionsMap.find(CalledF) == VAListFunctionsMap.end())
         continue;
+      const Type *ListType  = F->getParent()->getTypeByName("struct.__va_list_tag");
+      const Type *ListPtrType = ListType->getPointerTo();
+      unsigned VAListArgNum = 0;
+      for (Function::arg_iterator I = CalledF->arg_begin(); 
+           I != CalledF->arg_end(); ++I) {
+        VAListArgNum ++;
+        if(I->getType() == ListPtrType) {
+          break;
+        }
+      }
+
       Function::arg_iterator NII = F->arg_begin();
       std::vector<Value *>Args;
       Args.push_back(NII++); // total count
-      Args.push_back(NII++); // current count
+      Value *CounterSrc = CounterMap[CI->getOperand(VAListArgNum)->stripPointerCasts()];
+      LoadInst *CountValue = new LoadInst(CounterSrc, "count", CI);
+      Args.push_back(CountValue); // current count
+      NII++;
       Args.push_back(NII); // MD
       for(unsigned i = 1 ;i < CI->getNumOperands(); i++) {
         // Add the original argument
@@ -559,6 +574,7 @@
   VAListFunctionsMap[&F_orig] =  F;
   inst_iterator InsPt = inst_begin(F);
 
+  
   // Store the information
   Function::arg_iterator NII = F->arg_begin();
   AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt);
@@ -566,9 +582,33 @@
   NII++;
   AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt);
   new StoreInst(NII, Counter, &*InsPt); 
+  CounterMap[NII] = Counter;
   NII++;
   AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt);
   new StoreInst(NII, VAMDLoc, &*InsPt);
+  
+  // Find all va_copy calls
+  for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
+    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;I++) {
+      CallInst *CI = dyn_cast<CallInst>(I);
+      if(!CI)
+        continue;
+      Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
+      if(!CalledF)
+        continue;
+      if(!CalledF->isIntrinsic())
+        continue;
+      if(CalledF->getIntrinsicID() != Intrinsic::vacopy) 
+        continue;
+      // Reinitialize the counter
+      AllocaInst *CounterDest = new AllocaInst(Int64Ty, "",&*InsPt);
+      Value *CounterSource = CounterMap[CI->getOperand(2)->stripPointerCasts()];
+      LoadInst *CurrentValue = new LoadInst(CounterSource, "count", CI);
+      new StoreInst(CurrentValue, CounterDest, CI);
+      CounterMap[CI->getOperand(1)->stripPointerCasts()] = CounterDest;
+    }
+  }
+
 
   // instrument va_arg to increment the counter
   for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
@@ -577,13 +617,14 @@
       if(!VI)
         continue;
       Constant *One = ConstantInt::get(Int64Ty, 1);
-      LoadInst *OldValue = new LoadInst(Counter, "count", VI);
+      Value *CounterSrc = CounterMap[VI->getOperand(0)->stripPointerCasts()];
+      LoadInst *OldValue = new LoadInst(CounterSrc, "count", VI);
       Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add,
                                                      OldValue,
                                                      One,
                                                      "count",
                                                      VI);
-      new StoreInst(NewValue, Counter, VI);
+      new StoreInst(NewValue, CounterSrc, VI);
       std::vector<Value *> Args;
       Instruction *VASize = new LoadInst(VASizeLoc, "", VI);
       Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI);
@@ -804,6 +845,49 @@
   AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt);
   new StoreInst(ConstantInt::get(Int64Ty, 0), Counter, &*InsPt); 
 
+
+  // visit all VAStarts and initialize the counter
+  for (Function::iterator B = NewF->begin(), FE = NewF->end(); B != FE; ++B) {
+    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;I++) {
+      CallInst *CI = dyn_cast<CallInst>(I);
+      if(!CI)
+        continue;
+      Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
+      if(!CalledF)
+        continue;
+      if(!CalledF->isIntrinsic())
+        continue;
+      if(CalledF->getIntrinsicID() != Intrinsic::vastart) 
+        continue;
+      // Reinitialize the counter
+      StoreInst *SI3 = new StoreInst(ConstantInt::get(Int64Ty, 0), Counter);
+      SI3->insertAfter(CI);
+      CounterMap[CI->getOperand(1)->stripPointerCasts()] = Counter;
+    }
+  }
+
+  // Find all va_copy calls
+  for (Function::iterator B = NewF->begin(), FE = NewF->end(); B != FE; ++B) {
+    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;I++) {
+      CallInst *CI = dyn_cast<CallInst>(I);
+      if(!CI)
+        continue;
+      Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
+      if(!CalledF)
+        continue;
+      if(!CalledF->isIntrinsic())
+        continue;
+      if(CalledF->getIntrinsicID() != Intrinsic::vacopy) 
+        continue;
+      // Reinitialize the counter
+      AllocaInst *CounterDest = new AllocaInst(Int64Ty, "",&*InsPt);
+      Value *CounterSource = CounterMap[CI->getOperand(2)->stripPointerCasts()];
+      LoadInst *CurrentValue = new LoadInst(CounterSource, "count", CI);
+      new StoreInst(CurrentValue, CounterDest, CI);
+      CounterMap[CI->getOperand(1)->stripPointerCasts()] = CounterDest;
+    }
+  }
+
   // Modify function to add checks on every var_arg call to ensure that we
   // are not accessing more arguments than we passed in.
 
@@ -814,13 +898,14 @@
       if(!VI)
         continue;
       Constant *One = ConstantInt::get(Int64Ty, 1);
-      LoadInst *OldValue = new LoadInst(Counter, "count", VI);
+      Value *CounterSrc = CounterMap[VI->getOperand(0)->stripPointerCasts()];
+      LoadInst *OldValue = new LoadInst(CounterSrc, "count", VI);
       Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add,
                                                      OldValue,
                                                      One,
                                                      "count",
                                                      VI);
-      new StoreInst(NewValue, Counter, VI);
+      new StoreInst(NewValue, CounterSrc, VI);
       std::vector<Value *> Args;
       Instruction *VASize = new LoadInst(VASizeLoc, "", VI);
       Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI);
@@ -836,26 +921,6 @@
     }
   }
 
-  // visit all VAStarts and initialize the counter
-  CallInst *VAStart = NULL;
-  for (Function::iterator B = NewF->begin(), FE = NewF->end(); B != FE; ++B) {
-    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
-      CallInst *CI = dyn_cast<CallInst>(I++);
-      if(!CI)
-        continue;
-      Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
-      if(!CalledF)
-        continue;
-      if(!CalledF->isIntrinsic())
-        continue;
-      if(CalledF->getIntrinsicID() != Intrinsic::vastart) 
-        continue;
-      VAStart = CI;
-      // Reinitialize the counter
-      StoreInst *SI3 = new StoreInst(ConstantInt::get(Int64Ty, 0), Counter);
-      SI3->insertAfter(CI);
-    }
-  }
 
   // modify calls to va list functions to pass the metadata
   for (Function::iterator B = NewF->begin(), FE = NewF->end(); B != FE; ++B) {
@@ -864,11 +929,24 @@
       if(!CI)
         continue;
       Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
+
       if(VAListFunctionsMap.find(CalledF) == VAListFunctionsMap.end())
         continue;
+      const Type *ListType  = M.getTypeByName("struct.__va_list_tag");
+      const Type *ListPtrType = ListType->getPointerTo();
+      unsigned VAListArgNum = 0;
+      for (Function::arg_iterator I = CalledF->arg_begin(); 
+           I != CalledF->arg_end(); ++I) {
+        VAListArgNum ++;
+        if(I->getType() == ListPtrType) {
+          break;
+        }
+      }
       std::vector<Value *>Args;
+
+      Value *CounterSrc = CounterMap[CI->getOperand(VAListArgNum)->stripPointerCasts()];
       Instruction *VASize = new LoadInst(VASizeLoc, "", CI);
-      Instruction *VACounter = new LoadInst(Counter, "", CI);
+      Instruction *VACounter = new LoadInst(CounterSrc, "", CI);
       Instruction *VAMetaData = new LoadInst(VAMDLoc, "", CI);
       Args.push_back(VASize); // toatl count
       Args.push_back(VACounter); // current count



From rafael.espindola at gmail.com  Mon Jun 20 12:04:09 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Mon, 20 Jun 2011 17:04:09 -0000
Subject: [llvm-commits] [llvm] r133446 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
Message-ID: <20110620170409.20E472A6C12C@llvm.org>

Author: rafael
Date: Mon Jun 20 12:04:08 2011
New Revision: 133446

URL: http://llvm.org/viewvc/llvm-project?rev=133446&view=rev
Log:
Disable again.

Modified:
    llvm/trunk/lib/CodeGen/TailDuplication.cpp

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133446&r1=133445&r2=133446&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Mon Jun 20 12:04:08 2011
@@ -712,7 +712,7 @@
   DenseSet<unsigned> UsedByPhi;
   getRegsUsedByPHIs(*TailBB, &UsedByPhi);
 
-  if (isSimpleBB(TailBB))
+  if (0 && isSimpleBB(TailBB))
     return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
 
   // Iterate through all the unique predecessors and tail-duplicate this



From justin.holewinski at gmail.com  Mon Jun 20 12:08:56 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Mon, 20 Jun 2011 17:08:56 -0000
Subject: [llvm-commits] [llvm] r133447 -
	/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
Message-ID: <20110620170856.D077F2A6C12C@llvm.org>

Author: jholewinski
Date: Mon Jun 20 12:08:56 2011
New Revision: 133447

URL: http://llvm.org/viewvc/llvm-project?rev=133447&view=rev
Log:
PTX: Fix if-then-else formatting and add missing asserts

Modified:
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=133447&r1=133446&r2=133447&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Mon Jun 20 12:08:56 2011
@@ -304,18 +304,16 @@
   // Select the appropriate opcode based on the register class
   if (RC == PTX::RegI16RegisterClass) {
     OpCode = PTX::STACKSTOREI16;
-  }
-  else if (RC == PTX::RegI32RegisterClass) {
+  }  else if (RC == PTX::RegI32RegisterClass) {
     OpCode = PTX::STACKSTOREI32;
-  }
-  else if (RC == PTX::RegI64RegisterClass) {
+  }  else if (RC == PTX::RegI64RegisterClass) {
     OpCode = PTX::STACKSTOREI32;
-  }
-  else if (RC == PTX::RegF32RegisterClass) {
+  }  else if (RC == PTX::RegF32RegisterClass) {
     OpCode = PTX::STACKSTOREF32;
-  }
-  else if (RC == PTX::RegF64RegisterClass) {
+  }  else if (RC == PTX::RegF64RegisterClass) {
     OpCode = PTX::STACKSTOREF64;
+  } else {
+    llvm_unreachable("Unknown PTX register class!");
   }
 
   // Build the store instruction (really a mov)
@@ -341,18 +339,16 @@
   // Select the appropriate opcode based on the register class
   if (RC == PTX::RegI16RegisterClass) {
     OpCode = PTX::STACKLOADI16;
-  }
-  else if (RC == PTX::RegI32RegisterClass) {
+  } else if (RC == PTX::RegI32RegisterClass) {
     OpCode = PTX::STACKLOADI32;
-  }
-  else if (RC == PTX::RegI64RegisterClass) {
+  } else if (RC == PTX::RegI64RegisterClass) {
     OpCode = PTX::STACKLOADI32;
-  }
-  else if (RC == PTX::RegF32RegisterClass) {
+  } else if (RC == PTX::RegF32RegisterClass) {
     OpCode = PTX::STACKLOADF32;
-  }
-  else if (RC == PTX::RegF64RegisterClass) {
+  } else if (RC == PTX::RegF64RegisterClass) {
     OpCode = PTX::STACKLOADF64;
+  } else {
+    llvm_unreachable("Unknown PTX register class!");
   }
 
   // Build the load instruction (really a mov)



From justin.holewinski at gmail.com  Mon Jun 20 12:15:48 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Mon, 20 Jun 2011 13:15:48 -0400
Subject: [llvm-commits] [llvm] r133443 - in /llvm/trunk/lib/Target/PTX:
	PTXAsmPrinter.cpp PTXInstrInfo.cpp PTXInstrInfo.h PTXInstrInfo.td
In-Reply-To: <2C3AFB7B-D930-4B85-BFA7-5589ADCEF78E@2pi.dk>
References: <20110620155620.D18072A6C12C@llvm.org>
	<2C3AFB7B-D930-4B85-BFA7-5589ADCEF78E@2pi.dk>
Message-ID: <AEABE971-32C7-453F-B341-AD81DB9F388A@gmail.com>


On Jun 20, 2011, at 12:59 PM, Jakob Stoklund Olesen wrote:

> 
> On Jun 20, 2011, at 8:56 AM, Justin Holewinski wrote:
> 
>> +  int OpCode;
>> +
>> +  // Select the appropriate opcode based on the register class
>> +  if (RC == PTX::RegI16RegisterClass) {
>> +    OpCode = PTX::STACKSTOREI16;
>> +  }
>> +  else if (RC == PTX::RegI32RegisterClass) {
>> +    OpCode = PTX::STACKSTOREI32;
>> +  }
>> +  else if (RC == PTX::RegI64RegisterClass) {
>> +    OpCode = PTX::STACKSTOREI32;
>> +  }
>> +  else if (RC == PTX::RegF32RegisterClass) {
>> +    OpCode = PTX::STACKSTOREF32;
>> +  }
>> +  else if (RC == PTX::RegF64RegisterClass) {
>> +    OpCode = PTX::STACKSTOREF64;
>> +  }
> 
> Please add an assertion for the unknown register class case.
> 
> Also, format your else-ifs like so:
> 
> } else if (..) {

Fixed in r133447.

> 
> /jakob
> 

Thanks,

Justin Holewinski

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From rjmccall at apple.com  Mon Jun 20 12:17:55 2011
From: rjmccall at apple.com (John McCall)
Date: Mon, 20 Jun 2011 10:17:55 -0700
Subject: [llvm-commits] [llvm] r133285	-
 /llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp
In-Reply-To: <4DFEF6DA.4030503@free.fr>
References: <20110617202152.D6B812A6C12C@llvm.org> <4DFDF276.5030703@free.fr>
	<54E09593-01A1-4936-AFF8-7AF19D2C6919@apple.com>
	<4DFEF6DA.4030503@free.fr>
Message-ID: <BEFDFA5B-4D83-47A5-A967-02ADE979F770@apple.com>


On Jun 20, 2011, at 12:29 AM, Duncan Sands wrote:

> Hi John,
> 
>> On Jun 19, 2011, at 5:58 AM, Duncan Sands wrote:
>>>> +  // Insist that the amount-to-allocate not overflow.
>>>> +  OverflowingBinaryOperator *OBI = dyn_cast<OverflowingBinaryOperator>(Val);
>>>> +  if (OBI&&   !OBI->hasNoUnsignedWrap()) return 0;
>>> 
>>> I noticed you dropped the test for NSW.  I thought this was a problem because
>>> front-ends generally don't ever produce NUW, though they may produce NSW...
>> 
>> Stuart asked me to look at this, and I gave him a quick answer
>> that it's generally correct for nuw arithmetic, but that I wasn't as
>> certain for nsw arithmetic.  Now I think it's probably fine for either
>> as long as it's homogenous throughout.
>> 
>> The main restriction on the alloca size argument can be expressed as:
>>   (N * sizeof(T)) udiv sizeof(T) == N
>> However, there's a second restriction, which is that it's undefined
>> behavior to allocate something too large for the stack.  Technically
>> this is target-specific, but if we just assume by fiat that 2^31 is too large,
>> then as long as the arithmetic is being done in some reasonable size
>> then we know that N * sizeof(T) isn't permitted to signed overflow, either.
> 
> if you are willing to assume that then you don't need to check for nuw either...

We can't *assume* it doesn't overflow.  That's the whole point of this discussion.
There's an implicit multiply in sizeof(sp) as part of the alloca instruction, and
it's undefined behavior if either
  - that multiply causes unsigned overflow or
  - either the input or output to that multiply is negative.
This ends up being equivalent to saying that it's nuw nsw and cannot have a
negative result.  Since transforms are not permitted to introduce undefined
behavior, that means that that this transform has to be forbidden unless we
can prove that the multiply we're factoring out will not cause a signed or
unsigned overflow, under the assumption that the end result doesn't end up
being negative.

Going back to Stuart's original test case, we can't apply the transform to this:
  %a = mul i32 16, %n
  %b = alloca i8, i32 %b
  %c = bitcast i8* %x to [16 x i8]*
as that might introduce undefined behavior, because the multiply in %a is
allowed to overflow, and the multiply in this:
  %c = alloca [16 x i8], i32 %n
is not.

> I think I saw some GCC testcases fly by in which people were allocating stack
> objects larger than 2^32, so I'm not sure that "N * sizeof(T) < 2^31" is a
> reasonable assumption...

Okay, so the semantics should be in terms of sizeof(sp).  I'm fine with that.

John.

From rjmccall at apple.com  Mon Jun 20 12:20:49 2011
From: rjmccall at apple.com (John McCall)
Date: Mon, 20 Jun 2011 10:20:49 -0700
Subject: [llvm-commits] [llvm] r133285	-
 /llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp
In-Reply-To: <4DFEF6DA.4030503@free.fr>
References: <20110617202152.D6B812A6C12C@llvm.org> <4DFDF276.5030703@free.fr>
	<54E09593-01A1-4936-AFF8-7AF19D2C6919@apple.com>
	<4DFEF6DA.4030503@free.fr>
Message-ID: <7CDAC10E-FAB7-4992-A41B-BF352B705921@apple.com>


On Jun 20, 2011, at 12:29 AM, Duncan Sands wrote:

> Hi John,
> 
>> On Jun 19, 2011, at 5:58 AM, Duncan Sands wrote:
>>>> +  // Insist that the amount-to-allocate not overflow.
>>>> +  OverflowingBinaryOperator *OBI = dyn_cast<OverflowingBinaryOperator>(Val);
>>>> +  if (OBI&&   !OBI->hasNoUnsignedWrap()) return 0;
>>> 
>>> I noticed you dropped the test for NSW.  I thought this was a problem because
>>> front-ends generally don't ever produce NUW, though they may produce NSW...
>> 
>> Stuart asked me to look at this, and I gave him a quick answer
>> that it's generally correct for nuw arithmetic, but that I wasn't as
>> certain for nsw arithmetic.  Now I think it's probably fine for either
>> as long as it's homogenous throughout.
>> 
>> The main restriction on the alloca size argument can be expressed as:
>>  (N * sizeof(T)) udiv sizeof(T) == N
>> However, there's a second restriction, which is that it's undefined
>> behavior to allocate something too large for the stack.  Technically
>> this is target-specific, but if we just assume by fiat that 2^31 is too large,
>> then as long as the arithmetic is being done in some reasonable size
>> then we know that N * sizeof(T) isn't permitted to signed overflow, either.
> 
> if you are willing to assume that then you don't need to check for nuw either...

We can't *assume* it doesn't overflow.  That's the whole point of this discussion.
There's an implicit multiply in sizeof(sp) as part of the alloca instruction, and
it's undefined behavior if either
 - that multiply causes unsigned overflow or
 - either the input or output to that multiply is negative.
This ends up being equivalent to saying that it's nuw nsw and cannot have a
negative result.  Since transforms are not permitted to introduce undefined
behavior, that means that that this transform has to be forbidden unless we
can prove that the multiply we're factoring out will not cause a signed or
unsigned overflow, under the assumption that the end result doesn't end up
being negative.

Going back to Stuart's original test case, we can't apply the transform to this:
 %a = mul i32 16, %n
 %b = alloca i8, i32 %b
 %c = bitcast i8* %x to [16 x i8]*
as that might introduce undefined behavior, because the multiply in %a is
allowed to overflow, and the multiply in this:
 %c = alloca [16 x i8], i32 %n
is not.

> I think I saw some GCC testcases fly by in which people were allocating stack
> objects larger than 2^32, so I'm not sure that "N * sizeof(T) < 2^31" is a
> reasonable assumption...

Okay, so the semantics should be in terms of sizeof(sp).  I'm fine with that.

John.

From jay.foad at gmail.com  Mon Jun 20 12:46:19 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Mon, 20 Jun 2011 17:46:19 -0000
Subject: [llvm-commits] [llvm] r133449 -
	/llvm/trunk/lib/VMCore/Instructions.cpp
Message-ID: <20110620174619.A9AE72A6C12C@llvm.org>

Author: foad
Date: Mon Jun 20 12:46:19 2011
New Revision: 133449

URL: http://llvm.org/viewvc/llvm-project?rev=133449&view=rev
Log:
Fix a check for PHINodes with two incoming values.

Modified:
    llvm/trunk/lib/VMCore/Instructions.cpp

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=133449&r1=133448&r2=133449&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Jun 20 12:46:19 2011
@@ -141,7 +141,7 @@
 void PHINode::growOperands() {
   unsigned e = getNumOperands();
   unsigned NumOps = e + e / 2;
-  if (NumOps < 4) NumOps = 4;      // 4 op PHI nodes are VERY common.
+  if (NumOps < 2) NumOps = 2;      // 2 op PHI nodes are VERY common.
 
   Use *OldOps = op_begin();
   BasicBlock **OldBlocks = block_begin();



From jay.foad at gmail.com  Mon Jun 20 12:52:53 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Mon, 20 Jun 2011 18:52:53 +0100
Subject: [llvm-commits] [llvm] r133435 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/Target/CppBackend/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
In-Reply-To: <BANLkTim7oppnuuPYy-+QLtX9grqafusXFQ@mail.gmail.com>
References: <20110620143801.6C0D72A6C124@llvm.org>
	<BANLkTim7oppnuuPYy-+QLtX9grqafusXFQ@mail.gmail.com>
Message-ID: <BANLkTim5YF9ZkEMNXrba0dQhm4m3UHWS7w@mail.gmail.com>

On 20 June 2011 17:03, Frits van Bommel <fvbommel at gmail.com> wrote:
>> ?void PHINode::growOperands() {
>> ? unsigned e = getNumOperands();
>> - ?// Multiply by 1.5 and round down so the result is still even.
>> - ?unsigned NumOps = e + e / 4 * 2;
>> + ?unsigned NumOps = e + e / 2;
>> ? if (NumOps < 4) NumOps = 4; ? ? ?// 4 op PHI nodes are VERY common.
>
> Wouldn't it now be 2-op PHI nodes that are "VERY common"?
> (since 2 of the ops used to be basic blocks)

Well spotted! I've fixed it now.

Jay.


From evan.cheng at apple.com  Mon Jun 20 13:22:26 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 20 Jun 2011 11:22:26 -0700
Subject: [llvm-commits] patch: use movd for 32-bits and movq for 64-bits
 consistently
In-Reply-To: <BANLkTim7UXnRDOazsr31-Gr8uV-u9AV_Y2ZZ3qG0GXsdhb385A@mail.gmail.com>
References: <BANLkTinLsbBa7_zq0J9O+eXKh7g0Oaj=PDm4RLg1c88X8dPNMw@mail.gmail.com>
	<BANLkTinqRkccLwt3OysTby3ORJUfk+EFcA@mail.gmail.com>
	<BANLkTi=v14gm7s_eGDenWQp6taQbWAzETg@mail.gmail.com>
	<BANLkTinJVPj_rx0igXiE-DHurNmpgvdOng@mail.gmail.com>
	<BANLkTikx=kHPmYSqOZ=u384UQvD93mQ4aA@mail.gmail.com>
	<BANLkTikNpNXwqnX-K4ys+mNJ=t6ZWYT5mVQh+5LJ+jt9HvOaBg@mail.gmail.com>
	<BANLkTiknspMbMUrMpAOvWesBX05BR1fEnA@mail.gmail.com>
	<BANLkTim7UXnRDOazsr31-Gr8uV-u9AV_Y2ZZ3qG0GXsdhb385A@mail.gmail.com>
Message-ID: <74360F14-FD32-455F-99C8-0D0C6039DBB1@apple.com>

LGTM. 

Evan

On Jun 16, 2011, at 4:15 PM, Nick Lewycky wrote:

> On 16 June 2011 15:37, Eli Friedman <eli.friedman at gmail.com> wrote:
> On Thu, Jun 16, 2011 at 3:35 PM, Nick Lewycky <nlewycky at google.com> wrote:
> > On 16 June 2011 15:29, Eli Friedman <eli.friedman at gmail.com> wrote:
> >>
> >> On Thu, Jun 16, 2011 at 2:33 PM, Anton Korobeynikov <asl at math.spbu.ru>
> >> wrote:
> >> >> IIRC, we do things the way we do (outside of parsing asm) because the
> >> >> old Darwin assembler wouldn't accept "movq %rax, %xmm0", and required
> >> >> "movd %rax, %xmm0" instead.  I don't recall all the details of that,
> >> >> though.
> >> > Yeah. Probably it's safe nowadays to get rid of this workaround?
> >>
> >> Note that even if we do decide to get rid of that workaround, we still
> >> need to do the right thing with "movd %rax, %xmm0".
> >
> > Reject it? Or accept it and assemble as "movq %rax, %xmm0" like GNU as
> > does? We've been pretty aggressive about rejecting bad assembly, regardless
> > of what as does.
> 
> Accept it; it would be weird to reject a construct that LLVM itself
> has been generating for a very long time.
> 
> Sound reasonable. Patch attached!
> 
> Nick
> 
> 
> <movd-movq.patch>

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From ganna at apple.com  Mon Jun 20 13:32:35 2011
From: ganna at apple.com (Anna Zaks)
Date: Mon, 20 Jun 2011 11:32:35 -0700
Subject: [llvm-commits] Adding add.with.overflow intrinsic support to
	CBackend.
In-Reply-To: <BANLkTim5YF9ZkEMNXrba0dQhm4m3UHWS7w@mail.gmail.com>
References: <20110620143801.6C0D72A6C124@llvm.org>
	<BANLkTim7oppnuuPYy-+QLtX9grqafusXFQ@mail.gmail.com>
	<BANLkTim5YF9ZkEMNXrba0dQhm4m3UHWS7w@mail.gmail.com>
Message-ID: <528BA51E-6300-4AB0-9EC9-345DC43CDD28@apple.com>

Hi,

Attached is a CBackend patch for review. It adds support for sadd.with.overflow and uadd.with.overflow intrinsics. Essentially, we emit implementation for each add.with.overflow intrinsic that occurs in the module. 

Issues are lack of support for arbitrary size integers and assumption about the two's compliment representation for integers (casts from signed to unsigned and backwards). However, it seems that these are the limitations of the current CBackend implementation as well.  

We know that the CBackend is no longer supported and might get completely rewritten, but this patch removes the known blockers for us and might be useful for someone else as well.

Thanks,
Anna.

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From nicholas at mxc.ca  Mon Jun 20 13:33:27 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Mon, 20 Jun 2011 18:33:27 -0000
Subject: [llvm-commits] [llvm] r133452 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/bitcast2.ll
 test/CodeGen/X86/vec_set-8.ll test/CodeGen/X86/vec_set-9.ll
 test/CodeGen/X86/vec_set-C.ll test/CodeGen/X86/vec_shuffle-14.ll
 test/CodeGen/X86/vec_shuffle-17.ll test/MC/X86/x86-64.s
 test/MC/X86/x86_64-avx-encoding.s
Message-ID: <20110620183327.3F55D2A6C12C@llvm.org>

Author: nicholas
Date: Mon Jun 20 13:33:26 2011
New Revision: 133452

URL: http://llvm.org/viewvc/llvm-project?rev=133452&view=rev
Log:
Emit movq for 64-bit register to XMM register moves, but continue to accept
movd when assembling.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/bitcast2.ll
    llvm/trunk/test/CodeGen/X86/vec_set-8.ll
    llvm/trunk/test/CodeGen/X86/vec_set-9.ll
    llvm/trunk/test/CodeGen/X86/vec_set-C.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll
    llvm/trunk/test/MC/X86/x86-64.s
    llvm/trunk/test/MC/X86/x86_64-avx-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=133452&r1=133451&r2=133452&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Mon Jun 20 13:33:26 2011
@@ -2850,11 +2850,11 @@
                       [(set VR128:$dst,
                         (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
-                        "mov{d|q}\t{$src, $dst|$dst, $src}",
+                        "movq\t{$src, $dst|$dst, $src}",
                         [(set VR128:$dst,
                           (v2i64 (scalar_to_vector GR64:$src)))]>;
 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
-                       "mov{d|q}\t{$src, $dst|$dst, $src}",
+                       "movq\t{$src, $dst|$dst, $src}",
                        [(set FR64:$dst, (bitconvert GR64:$src))]>;
 
 
@@ -2895,7 +2895,7 @@
                                      (iPTR 0))), addr:$dst)]>;
 
 def MOVPQIto64rr  : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
-                         "mov{d|q}\t{$src, $dst|$dst, $src}",
+                         "movq\t{$src, $dst|$dst, $src}",
                          [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
                                            (iPTR 0)))]>;
 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
@@ -2903,7 +2903,7 @@
                        [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
 
 def MOVSDto64rr  : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
-                        "mov{d|q}\t{$src, $dst|$dst, $src}",
+                        "movq\t{$src, $dst|$dst, $src}",
                         [(set GR64:$dst, (bitconvert FR64:$src))]>;
 def MOVSDto64mr  : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
                         "movq\t{$src, $dst|$dst, $src}",
@@ -2931,7 +2931,7 @@
                                       (v4i32 (scalar_to_vector GR32:$src)))))]>,
                                       VEX;
 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
-                       "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
+                       "movq\t{$src, $dst|$dst, $src}", // X86-64 only
                        [(set VR128:$dst, (v2i64 (X86vzmovl
                                       (v2i64 (scalar_to_vector GR64:$src)))))]>,
                                       VEX, VEX_W;
@@ -2942,7 +2942,7 @@
                        [(set VR128:$dst, (v4i32 (X86vzmovl
                                       (v4i32 (scalar_to_vector GR32:$src)))))]>;
 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
-                       "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
+                       "movq\t{$src, $dst|$dst, $src}", // X86-64 only
                        [(set VR128:$dst, (v2i64 (X86vzmovl
                                       (v2i64 (scalar_to_vector GR64:$src)))))]>;
 }
@@ -2968,6 +2968,21 @@
             (MOVZDI2PDIrm addr:$src)>;
 }
 
+// We used to emit this syntax to work around a bug in the Darwin assembler,
+// so we'll continue to assemble it.
+def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
+                (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
+def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
+                (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
+def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
+                (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
+def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
+                (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
+def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
+                (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
+def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
+                (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
+
 //===---------------------------------------------------------------------===//
 // SSE2 - Move Quadword
 //===---------------------------------------------------------------------===//

Modified: llvm/trunk/test/CodeGen/X86/bitcast2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast2.ll?rev=133452&r1=133451&r2=133452&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast2.ll Mon Jun 20 13:33:26 2011
@@ -1,13 +1,31 @@
-; RUN: llc < %s -march=x86-64 | grep movd | count 2
+; RUN: llc < %s -march=x86-64 | FileCheck %s
 ; RUN: llc < %s -march=x86-64 | not grep rsp
 
 define i64 @test1(double %A) {
+; CHECK: test1
+; CHECK: movq
    %B = bitcast double %A to i64
    ret i64 %B
 }
 
 define double @test2(i64 %A) {
+; CHECK: test2
+; CHECK: movq
    %B = bitcast i64 %A to double
    ret double %B
 }
 
+define i32 @test3(float %A) {
+; CHECK: test3
+; CHECK: movd
+   %B = bitcast float %A to i32
+   ret i32 %B
+}
+
+define float @test4(i32 %A) {
+; CHECK: test4
+; CHECK: movd
+   %B = bitcast i32 %A to float
+   ret float %B
+}
+

Modified: llvm/trunk/test/CodeGen/X86/vec_set-8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-8.ll?rev=133452&r1=133451&r2=133452&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-8.ll Mon Jun 20 13:33:26 2011
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
 ; CHECK-NOT: movsd
-; CHECK: movd {{%rdi|%rcx}}, %xmm0
+; CHECK: movq {{%rdi|%rcx}}, %xmm0
 ; CHECK-NOT: movsd
 
 define <2 x i64> @test(i64 %i) nounwind  {

Modified: llvm/trunk/test/CodeGen/X86/vec_set-9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-9.ll?rev=133452&r1=133451&r2=133452&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-9.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-9.ll Mon Jun 20 13:33:26 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 | grep movd | count 1
+; RUN: llc < %s -march=x86-64 | grep movq | count 1
 ; RUN: llc < %s -march=x86-64 | grep {movlhps.*%xmm0, %xmm0}
 
 define <2 x i64> @test3(i64 %A) nounwind {

Modified: llvm/trunk/test/CodeGen/X86/vec_set-C.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-C.ll?rev=133452&r1=133451&r2=133452&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-C.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-C.ll Mon Jun 20 13:33:26 2011
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mov | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq
 
 define <2 x i64> @t1(i64 %x) nounwind  {
 	%tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll?rev=133452&r1=133451&r2=133452&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll Mon Jun 20 13:33:26 2011
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 2
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 3
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 1
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 4
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xor
 
 define <4 x i32> @t1(i32 %a) nounwind  {

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll?rev=133452&r1=133451&r2=133452&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll Mon Jun 20 13:33:26 2011
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
 ; CHECK-NOT: xor
-; CHECK: movd {{%rdi|%rcx}}, %xmm0
+; CHECK: movq {{%rdi|%rcx}}, %xmm0
 ; CHECK-NOT: xor
 ; PR2108
 

Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=133452&r1=133451&r2=133452&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Mon Jun 20 13:33:26 2011
@@ -1128,3 +1128,11 @@
 // CHECK: strq
 // CHECK: encoding: [0x48,0x0f,0x00,0xc8]
 	str %rax
+
+// CHECK: movq %rdi, %xmm0
+// CHECK: encoding: [0x66,0x48,0x0f,0x6e,0xc7]
+	movq %rdi,%xmm0
+
+// CHECK: movq %rdi, %xmm0
+// CHECK: encoding: [0x66,0x48,0x0f,0x6e,0xc7]
+	movd %rdi,%xmm0

Modified: llvm/trunk/test/MC/X86/x86_64-avx-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-avx-encoding.s?rev=133452&r1=133451&r2=133452&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_64-avx-encoding.s (original)
+++ llvm/trunk/test/MC/X86/x86_64-avx-encoding.s Mon Jun 20 13:33:26 2011
@@ -1444,9 +1444,9 @@
 // CHECK: encoding: [0xc5,0x79,0x7e,0x30]
           vmovd  %xmm14, (%rax)
 
-// CHECK: vmovd  %rax, %xmm14
-// CHECK: encoding: [0xc4,0x61,0xf9,0x6e,0xf0]
-          vmovd  %rax, %xmm14
+// CHECK: vmovd  %eax, %xmm14
+// CHECK: encoding: [0xc5,0x79,0x6e,0xf0]
+          vmovd  %eax, %xmm14
 
 // CHECK: vmovq  %xmm14, (%rax)
 // CHECK: encoding: [0xc5,0x79,0xd6,0x30]



From justin.holewinski at gmail.com  Mon Jun 20 13:42:48 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Mon, 20 Jun 2011 18:42:48 -0000
Subject: [llvm-commits] [llvm] r133454 - in /llvm/trunk:
 lib/Target/PTX/PTXInstrInfo.td test/CodeGen/PTX/cvt.ll
 test/CodeGen/PTX/setp.ll
Message-ID: <20110620184248.C19182A6C12C@llvm.org>

Author: jholewinski
Date: Mon Jun 20 13:42:48 2011
New Revision: 133454

URL: http://llvm.org/viewvc/llvm-project?rev=133454&view=rev
Log:
PTX: Fix conversion between predicates and value types

Modified:
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
    llvm/trunk/test/CodeGen/PTX/cvt.ll
    llvm/trunk/test/CodeGen/PTX/setp.ll

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=133454&r1=133453&r2=133454&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Mon Jun 20 13:42:48 2011
@@ -826,31 +826,35 @@
 // TODO: Do something with st.param if/when it is needed.
 
 // Conversion to pred
-
+// PTX does not directly support converting to a predicate type, so we fake it
+// by performing a greater-than test between the value and zero.  This follows
+// the C convention that any non-zero value is equivalent to 'true'.
 def CVT_pred_u16
-  : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "cvt.pred.u16\t$d, $a",
+  : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.b16\t$d, $a, 0",
             [(set RegPred:$d, (trunc RegI16:$a))]>;
 
 def CVT_pred_u32
-  : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "cvt.pred.u32\t$d, $a",
+  : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.b32\t$d, $a, 0",
             [(set RegPred:$d, (trunc RegI32:$a))]>;
 
 def CVT_pred_u64
-  : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "cvt.pred.u64\t$d, $a",
+  : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.b64\t$d, $a, 0",
             [(set RegPred:$d, (trunc RegI64:$a))]>;
 
 def CVT_pred_f32
-  : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "cvt.rzi.pred.f32\t$d, $a",
+  : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.b32\t$d, $a, 0",
             [(set RegPred:$d, (fp_to_uint RegF32:$a))]>;
 
 def CVT_pred_f64
-  : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "cvt.rzi.pred.f64\t$d, $a",
+  : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.b64\t$d, $a, 0",
             [(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
 
 // Conversion to u16
-
+// PTX does not directly support converting a predicate to a value, so we
+// use a select instruction to select either 0 or 1 (integer or fp) based
+// on the truth value of the predicate.
 def CVT_u16_pred
-  : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "cvt.u16.pred\t$d, $a",
+  : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
             [(set RegI16:$d, (zext RegPred:$a))]>;
 
 def CVT_u16_u32
@@ -872,7 +876,7 @@
 // Conversion to u32
 
 def CVT_u32_pred
-  : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "cvt.u32.pred\t$d, $a",
+  : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
             [(set RegI32:$d, (zext RegPred:$a))]>;
 
 def CVT_u32_u16
@@ -894,7 +898,7 @@
 // Conversion to u64
 
 def CVT_u64_pred
-  : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "cvt.u64.pred\t$d, $a",
+  : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
             [(set RegI64:$d, (zext RegPred:$a))]>;
 
 def CVT_u64_u16
@@ -916,7 +920,8 @@
 // Conversion to f32
 
 def CVT_f32_pred
-  : InstPTX<(outs RegF32:$d), (ins RegPred:$a), "cvt.rn.f32.pred\t$d, $a",
+  : InstPTX<(outs RegF32:$d), (ins RegPred:$a),
+            "selp.f32\t$d, 0F3F800000, 0F00000000, $a",  // 1.0
             [(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
 
 def CVT_f32_u16
@@ -938,7 +943,8 @@
 // Conversion to f64
 
 def CVT_f64_pred
-  : InstPTX<(outs RegF64:$d), (ins RegPred:$a), "cvt.rn.f64.pred\t$d, $a",
+  : InstPTX<(outs RegF64:$d), (ins RegPred:$a), 
+            "selp.f64\t$d, 0D3F80000000000000, 0D0000000000000000, $a",  // 1.0
             [(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
 
 def CVT_f64_u16

Modified: llvm/trunk/test/CodeGen/PTX/cvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/cvt.ll?rev=133454&r1=133453&r2=133454&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/cvt.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/cvt.ll Mon Jun 20 13:42:48 2011
@@ -4,8 +4,10 @@
 ; (note: we convert back to i32 to return)
 
 define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) {
-; CHECK: cvt.pred.u16 p0, rh1;
-; CHECK: ret;
+; CHECK: setp.gt.b16 p0, rh1, 0
+; CHECK-NEXT: and.pred p0, p0, p1;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
 	%a = trunc i16 %x to i1
 	%b = and i1 %a, %y
 	%c = zext i1 %b to i32
@@ -13,8 +15,10 @@
 }
 
 define ptx_device i32 @cvt_pred_i32(i32 %x, i1 %y) {
-; CHECK: cvt.pred.u32 p0, r1;
-; CHECK: ret;
+; CHECK: setp.gt.b32 p0, r1, 0
+; CHECK-NEXT: and.pred p0, p0, p1;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
 	%a = trunc i32 %x to i1
 	%b = and i1 %a, %y
 	%c = zext i1 %b to i32
@@ -22,8 +26,10 @@
 }
 
 define ptx_device i32 @cvt_pred_i64(i64 %x, i1 %y) {
-; CHECK: cvt.pred.u64 p0, rd1;
-; CHECK: ret;
+; CHECK: setp.gt.b64 p0, rd1, 0
+; CHECK-NEXT: and.pred p0, p0, p1;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
 	%a = trunc i64 %x to i1
 	%b = and i1 %a, %y
 	%c = zext i1 %b to i32
@@ -31,8 +37,10 @@
 }
 
 define ptx_device i32 @cvt_pred_f32(float %x, i1 %y) {
-; CHECK: cvt.rzi.pred.f32 p0, r1;
-; CHECK: ret;
+; CHECK: setp.gt.b32 p0, r1, 0
+; CHECK-NEXT: and.pred p0, p0, p1;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
 	%a = fptoui float %x to i1
 	%b = and i1 %a, %y
 	%c = zext i1 %b to i32
@@ -40,8 +48,10 @@
 }
 
 define ptx_device i32 @cvt_pred_f64(double %x, i1 %y) {
-; CHECK: cvt.rzi.pred.f64 p0, rd1;
-; CHECK: ret;
+; CHECK: setp.gt.b64 p0, rd1, 0
+; CHECK-NEXT: and.pred p0, p0, p1;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
 	%a = fptoui double %x to i1
 	%b = and i1 %a, %y
 	%c = zext i1 %b to i32
@@ -51,36 +61,36 @@
 ; i16
 
 define ptx_device i16 @cvt_i16_preds(i1 %x) {
-; CHECK: cvt.u16.pred rh0, p1;
-; CHECK: ret;
+; CHECK: selp.u16 rh0, 1, 0, p1;
+; CHECK-NEXT: ret;
 	%a = zext i1 %x to i16
 	ret i16 %a
 }
 
 define ptx_device i16 @cvt_i16_i32(i32 %x) {
 ; CHECK: cvt.u16.u32 rh0, r1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = trunc i32 %x to i16
 	ret i16 %a
 }
 
 define ptx_device i16 @cvt_i16_i64(i64 %x) {
 ; CHECK: cvt.u16.u64 rh0, rd1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = trunc i64 %x to i16
 	ret i16 %a
 }
 
 define ptx_device i16 @cvt_i16_f32(float %x) {
 ; CHECK: cvt.rzi.u16.f32 rh0, r1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = fptoui float %x to i16
 	ret i16 %a
 }
 
 define ptx_device i16 @cvt_i16_f64(double %x) {
 ; CHECK: cvt.rzi.u16.f64 rh0, rd1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = fptoui double %x to i16
 	ret i16 %a
 }
@@ -88,36 +98,36 @@
 ; i32
 
 define ptx_device i32 @cvt_i32_preds(i1 %x) {
-; CHECK: cvt.u32.pred r0, p1;
-; CHECK: ret;
+; CHECK: selp.u32 r0, 1, 0, p1;
+; CHECK-NEXT: ret;
 	%a = zext i1 %x to i32
 	ret i32 %a
 }
 
 define ptx_device i32 @cvt_i32_i16(i16 %x) {
 ; CHECK: cvt.u32.u16 r0, rh1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = zext i16 %x to i32
 	ret i32 %a
 }
 
 define ptx_device i32 @cvt_i32_i64(i64 %x) {
 ; CHECK: cvt.u32.u64 r0, rd1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = trunc i64 %x to i32
 	ret i32 %a
 }
 
 define ptx_device i32 @cvt_i32_f32(float %x) {
 ; CHECK: cvt.rzi.u32.f32 r0, r1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = fptoui float %x to i32
 	ret i32 %a
 }
 
 define ptx_device i32 @cvt_i32_f64(double %x) {
 ; CHECK: cvt.rzi.u32.f64 r0, rd1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = fptoui double %x to i32
 	ret i32 %a
 }
@@ -125,29 +135,29 @@
 ; i64
 
 define ptx_device i64 @cvt_i64_preds(i1 %x) {
-; CHECK: cvt.u64.pred rd0, p1;
-; CHECK: ret;
+; CHECK: selp.u64 rd0, 1, 0, p1;
+; CHECK-NEXT: ret;
 	%a = zext i1 %x to i64
 	ret i64 %a
 }
 
 define ptx_device i64 @cvt_i64_i16(i16 %x) {
 ; CHECK: cvt.u64.u16 rd0, rh1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = zext i16 %x to i64
 	ret i64 %a
 }
 
 define ptx_device i64 @cvt_i64_i32(i32 %x) {
 ; CHECK: cvt.u64.u32 rd0, r1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = zext i32 %x to i64
 	ret i64 %a
 }
 
 define ptx_device i64 @cvt_i64_f32(float %x) {
 ; CHECK: cvt.rzi.u64.f32 rd0, r1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = fptoui float %x to i64
 	ret i64 %a
 }
@@ -162,36 +172,36 @@
 ; f32
 
 define ptx_device float @cvt_f32_preds(i1 %x) {
-; CHECK: cvt.rn.f32.pred r0, p1;
-; CHECK: ret;
+; CHECK: selp.f32 r0, 0F3F800000, 0F00000000, p1;
+; CHECK-NEXT: ret;
 	%a = uitofp i1 %x to float
 	ret float %a
 }
 
 define ptx_device float @cvt_f32_i16(i16 %x) {
 ; CHECK: cvt.rn.f32.u16 r0, rh1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = uitofp i16 %x to float
 	ret float %a
 }
 
 define ptx_device float @cvt_f32_i32(i32 %x) {
 ; CHECK: cvt.rn.f32.u32 r0, r1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = uitofp i32 %x to float
 	ret float %a
 }
 
 define ptx_device float @cvt_f32_i64(i64 %x) {
 ; CHECK: cvt.rn.f32.u64 r0, rd1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = uitofp i64 %x to float
 	ret float %a
 }
 
 define ptx_device float @cvt_f32_f64(double %x) {
 ; CHECK: cvt.rn.f32.f64 r0, rd1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = fptrunc double %x to float
 	ret float %a
 }
@@ -199,36 +209,36 @@
 ; f64
 
 define ptx_device double @cvt_f64_preds(i1 %x) {
-; CHECK: cvt.rn.f64.pred rd0, p1;
-; CHECK: ret;
+; CHECK: selp.f64 rd0, 0D3F80000000000000, 0D0000000000000000, p1;
+; CHECK-NEXT: ret;
 	%a = uitofp i1 %x to double
 	ret double %a
 }
 
 define ptx_device double @cvt_f64_i16(i16 %x) {
 ; CHECK: cvt.rn.f64.u16 rd0, rh1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = uitofp i16 %x to double
 	ret double %a
 }
 
 define ptx_device double @cvt_f64_i32(i32 %x) {
 ; CHECK: cvt.rn.f64.u32 rd0, r1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = uitofp i32 %x to double
 	ret double %a
 }
 
 define ptx_device double @cvt_f64_i64(i64 %x) {
 ; CHECK: cvt.rn.f64.u64 rd0, rd1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = uitofp i64 %x to double
 	ret double %a
 }
 
 define ptx_device double @cvt_f64_f32(float %x) {
 ; CHECK: cvt.f64.f32 rd0, r1;
-; CHECK: ret;
+; CHECK-NEXT: ret;
 	%a = fpext float %x to double
 	ret double %a
 }

Modified: llvm/trunk/test/CodeGen/PTX/setp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/setp.ll?rev=133454&r1=133453&r2=133454&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/setp.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/setp.ll Mon Jun 20 13:42:48 2011
@@ -2,7 +2,7 @@
 
 define ptx_device i32 @test_setp_eq_u32_rr(i32 %x, i32 %y) {
 ; CHECK: setp.eq.u32 p0, r1, r2;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp eq i32 %x, %y
 	%z = zext i1 %p to i32
@@ -11,7 +11,7 @@
 
 define ptx_device i32 @test_setp_ne_u32_rr(i32 %x, i32 %y) {
 ; CHECK: setp.ne.u32 p0, r1, r2;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp ne i32 %x, %y
 	%z = zext i1 %p to i32
@@ -20,7 +20,7 @@
 
 define ptx_device i32 @test_setp_lt_u32_rr(i32 %x, i32 %y) {
 ; CHECK: setp.lt.u32 p0, r1, r2;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp ult i32 %x, %y
 	%z = zext i1 %p to i32
@@ -29,7 +29,7 @@
 
 define ptx_device i32 @test_setp_le_u32_rr(i32 %x, i32 %y) {
 ; CHECK: setp.le.u32 p0, r1, r2;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp ule i32 %x, %y
 	%z = zext i1 %p to i32
@@ -38,7 +38,7 @@
 
 define ptx_device i32 @test_setp_gt_u32_rr(i32 %x, i32 %y) {
 ; CHECK: setp.gt.u32 p0, r1, r2;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp ugt i32 %x, %y
 	%z = zext i1 %p to i32
@@ -47,7 +47,7 @@
 
 define ptx_device i32 @test_setp_ge_u32_rr(i32 %x, i32 %y) {
 ; CHECK: setp.ge.u32 p0, r1, r2;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp uge i32 %x, %y
 	%z = zext i1 %p to i32
@@ -56,7 +56,7 @@
 
 define ptx_device i32 @test_setp_eq_u32_ri(i32 %x) {
 ; CHECK: setp.eq.u32 p0, r1, 1;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp eq i32 %x, 1
 	%z = zext i1 %p to i32
@@ -65,7 +65,7 @@
 
 define ptx_device i32 @test_setp_ne_u32_ri(i32 %x) {
 ; CHECK: setp.ne.u32 p0, r1, 1;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp ne i32 %x, 1
 	%z = zext i1 %p to i32
@@ -74,7 +74,7 @@
 
 define ptx_device i32 @test_setp_lt_u32_ri(i32 %x) {
 ; CHECK: setp.eq.u32 p0, r1, 0;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp ult i32 %x, 1
 	%z = zext i1 %p to i32
@@ -83,7 +83,7 @@
 
 define ptx_device i32 @test_setp_le_u32_ri(i32 %x) {
 ; CHECK: setp.lt.u32 p0, r1, 2;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp ule i32 %x, 1
 	%z = zext i1 %p to i32
@@ -92,7 +92,7 @@
 
 define ptx_device i32 @test_setp_gt_u32_ri(i32 %x) {
 ; CHECK: setp.gt.u32 p0, r1, 1;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp ugt i32 %x, 1
 	%z = zext i1 %p to i32
@@ -101,7 +101,7 @@
 
 define ptx_device i32 @test_setp_ge_u32_ri(i32 %x) {
 ; CHECK: setp.ne.u32 p0, r1, 0;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%p = icmp uge i32 %x, 1
 	%z = zext i1 %p to i32
@@ -111,7 +111,7 @@
 define ptx_device i32 @test_setp_4_op_format_1(i32 %x, i32 %y, i32 %u, i32 %v) {
 ; CHECK: setp.gt.u32 p0, r3, r4;
 ; CHECK-NEXT: setp.eq.and.u32 p0, r1, r2, p0;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%c = icmp eq i32 %x, %y
 	%d = icmp ugt i32 %u, %v
@@ -121,9 +121,9 @@
 }
 
 define ptx_device i32 @test_setp_4_op_format_2(i32 %x, i32 %y, i32 %w) {
-; CHECK: cvt.pred.u32 p0, r3;
+; CHECK: setp.gt.b32 p0, r3, 0;
 ; CHECK-NEXT: setp.eq.and.u32 p0, r1, r2, !p0;
-; CHECK-NEXT: cvt.u32.pred r0, p0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
 ; CHECK-NEXT: ret;
 	%c = trunc i32 %w to i1
 	%d = icmp eq i32 %x, %y



From baldrick at free.fr  Mon Jun 20 15:06:18 2011
From: baldrick at free.fr (Duncan Sands)
Date: Mon, 20 Jun 2011 20:06:18 -0000
Subject: [llvm-commits] [dragonegg] r133465 - /dragonegg/trunk/README
Message-ID: <20110620200618.43AA82A6C12C@llvm.org>

Author: baldrick
Date: Mon Jun 20 15:06:18 2011
New Revision: 133465

URL: http://llvm.org/viewvc/llvm-project?rev=133465&view=rev
Log:
I worked out how to build dragonegg against debian's gcc 4.5.

Modified:
    dragonegg/trunk/README

Modified: dragonegg/trunk/README
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/README?rev=133465&r1=133464&r2=133465&view=diff
==============================================================================
--- dragonegg/trunk/README (original)
+++ dragonegg/trunk/README Mon Jun 20 15:06:18 2011
@@ -28,6 +28,12 @@
 Build the plugin like this:
   GCC=PATH_TO_INSTALLED_GCC make
 This command should be executed in the directory containing this README.
+The plugin makes use of various gcc headers that are usually shipped with gcc.
+However some linux distributions, for example debian and ubuntu, have split the
+headers out of gcc into a separate package.  So if you get errors along the
+lines of "config.h not found", check whether gcc headers like "config.h" and
+"tree.h" are installed.  On debian the package containing headers is called
+gcc-4.5-plugin-dev or gcc-4.6-plugin-dev.
 
 The plugin needs to know about the version of gcc it will be loaded into, which
 is why you need to specify your version of gcc 4.5/4.6 via the GCC variable like



From stoklund at 2pi.dk  Mon Jun 20 15:56:05 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Mon, 20 Jun 2011 20:56:05 -0000
Subject: [llvm-commits] [llvm] r133470 -
	/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
Message-ID: <20110620205605.C13162A6C12C@llvm.org>

Author: stoklund
Date: Mon Jun 20 15:56:05 2011
New Revision: 133470

URL: http://llvm.org/viewvc/llvm-project?rev=133470&view=rev
Log:
Skip fields that don't exist in the Register class.

Modified:
    llvm/trunk/utils/TableGen/CodeGenRegisters.cpp

Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=133470&r1=133469&r2=133470&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Mon Jun 20 15:56:05 2011
@@ -236,7 +236,8 @@
         if (RV.getName() == "DwarfNumbers" ||
             RV.getName() == "DwarfAlias" ||
             RV.getName() == "Aliases") {
-          NewReg->addValue(*RegisterCl->getValue(RV.getName()));
+          if (const RecordVal *DefRV = RegisterCl->getValue(RV.getName()))
+            NewReg->addValue(*DefRV);
           continue;
         }
 



From isanbard at gmail.com  Mon Jun 20 17:12:25 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Mon, 20 Jun 2011 22:12:25 -0000
Subject: [llvm-commits] [llvm] r133473 - /llvm/trunk/lib/MC/MCAsmStreamer.cpp
Message-ID: <20110620221225.258DD2A6C12C@llvm.org>

Author: void
Date: Mon Jun 20 17:12:24 2011
New Revision: 133473

URL: http://llvm.org/viewvc/llvm-project?rev=133473&view=rev
Log:
Remove the subclassing. This will be moved to the ASM printer.

Modified:
    llvm/trunk/lib/MC/MCAsmStreamer.cpp

Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=133473&r1=133472&r2=133473&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Mon Jun 20 17:12:24 2011
@@ -1244,391 +1244,12 @@
   if (!UseCFI)
     EmitFrames(false);
 }
-
-//===----------------------------------------------------------------------===//
-/// MCLSDADecoderAsmStreamer - This is identical to the MCAsmStreamer, but
-/// outputs a description of the LSDA in a human readable format.
-///
-namespace {
-
-class MCLSDADecoderAsmStreamer : public MCAsmStreamer {
-  const MCSymbol *PersonalitySymbol;
-  const MCSymbol *LSDASymbol;
-  bool InLSDA;
-  bool ReadingULEB128;
-
-  uint64_t BytesRead;
-  uint64_t ActionTableBytes;
-  uint64_t LSDASize;
-
-  SmallVector<char, 2> ULEB128Value;
-  std::vector<int64_t> LSDAEncoding;
-  std::vector<const MCExpr*> Assignments;
-
-  /// GetULEB128Value - A helper function to convert the value in the
-  /// ULEB128Value vector into a uint64_t.
-  uint64_t GetULEB128Value(SmallVectorImpl<char> &ULEB128Value) {
-    uint64_t Val = 0;
-    for (unsigned i = 0, e = ULEB128Value.size(); i != e; ++i)
-      Val |= (ULEB128Value[i] & 0x7F) << (7 * i);
-    return Val;
-  }
-
-  /// ResetState - Reset the state variables.
-  void ResetState() {
-    PersonalitySymbol = 0;
-    LSDASymbol = 0;
-    LSDASize = 0;
-    BytesRead = 0;
-    ActionTableBytes = 0;
-    InLSDA = false;
-    ReadingULEB128 = false;
-    ULEB128Value.clear();
-    LSDAEncoding.clear();
-    Assignments.clear();
-  }
-
-  void EmitEHTableDescription();
-
-  const char *DecodeDWARFEncoding(unsigned Encoding) {
-    switch (Encoding) {
-    case dwarf::DW_EH_PE_absptr: return "absptr";
-    case dwarf::DW_EH_PE_omit:   return "omit";
-    case dwarf::DW_EH_PE_pcrel:  return "pcrel";
-    case dwarf::DW_EH_PE_udata4: return "udata4";
-    case dwarf::DW_EH_PE_udata8: return "udata8";
-    case dwarf::DW_EH_PE_sdata4: return "sdata4";
-    case dwarf::DW_EH_PE_sdata8: return "sdata8";
-    case dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_udata4: return "pcrel udata4";
-    case dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_sdata4: return "pcrel sdata4";
-    case dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_udata8: return "pcrel udata8";
-    case dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_sdata8: return "pcrel sdata8";
-    case dwarf::DW_EH_PE_indirect|dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_udata4:
-      return "indirect pcrel udata4";
-    case dwarf::DW_EH_PE_indirect|dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_sdata4:
-      return "indirect pcrel sdata4";
-    case dwarf::DW_EH_PE_indirect|dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_udata8:
-      return "indirect pcrel udata8";
-    case dwarf::DW_EH_PE_indirect|dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_sdata8:
-      return "indirect pcrel sdata8";
-    }
-  
-    return "<unknown encoding>";
-  }
-public:
-  MCLSDADecoderAsmStreamer(MCContext &Context, formatted_raw_ostream &os,
-                           bool isVerboseAsm, bool useLoc, bool useCFI,
-                           MCInstPrinter *printer, MCCodeEmitter *emitter,
-                           TargetAsmBackend *asmbackend,
-                           bool showInst)
-    : MCAsmStreamer(Context, os, isVerboseAsm, useLoc, useCFI,
-                    printer, emitter, asmbackend, showInst) {
-    ResetState();
-  }
-  ~MCLSDADecoderAsmStreamer() {}
-
-  virtual void Finish() {
-    ResetState();
-    MCAsmStreamer::Finish();
-  }
-
-  virtual void EmitLabel(MCSymbol *Symbol) {
-    if (Symbol == LSDASymbol)
-      InLSDA = true;
-    MCAsmStreamer::EmitLabel(Symbol);
-  }
-  virtual void EmitAssignment(MCSymbol *Symbol, const MCExpr *Value) {
-    if (InLSDA)
-      Assignments.push_back(Value);
-    MCAsmStreamer::EmitAssignment(Symbol, Value);
-  }
-  virtual void EmitBytes(StringRef Data, unsigned AddrSpace);
-  virtual void EmitIntValue(uint64_t Value, unsigned Size,
-                            unsigned AddrSpace = 0);
-  virtual void EmitValueImpl(const MCExpr *Value, unsigned Size,
-                             unsigned AddrSpace);
-  virtual void EmitFill(uint64_t NumBytes, uint8_t FillValue,
-                        unsigned AddrSpace);
-  virtual void EmitCFIPersonality(const MCSymbol *Sym, unsigned Encoding) {
-    PersonalitySymbol = Sym;
-    MCAsmStreamer::EmitCFIPersonality(Sym, Encoding);
-  }
-  virtual void EmitCFILsda(const MCSymbol *Sym, unsigned Encoding) {
-    LSDASymbol = Sym;
-    MCAsmStreamer::EmitCFILsda(Sym, Encoding);
-  }
-};
-
-} // end anonymous namespace
-
-void MCLSDADecoderAsmStreamer::EmitBytes(StringRef Data, unsigned AddrSpace) {
-  if (InLSDA && Data.size() == 1) {
-    LSDAEncoding.push_back((unsigned)(unsigned char)Data[0]);
-    ++BytesRead;
-
-    if (LSDAEncoding.size() == 4)
-      // The fourth value tells us where the bottom of the type table is.
-      LSDASize = BytesRead + LSDAEncoding[3];
-    else if (LSDAEncoding.size() == 6)
-      // The sixth value tells us where the start of the action table is.
-      ActionTableBytes = BytesRead;
-  }
-
-  MCAsmStreamer::EmitBytes(Data, AddrSpace);
-}
-
-void MCLSDADecoderAsmStreamer::EmitIntValue(uint64_t Value, unsigned Size,
-                                            unsigned AddrSpace) {
-  if (!InLSDA)
-    return MCAsmStreamer::EmitIntValue(Value, Size, AddrSpace);
-
-  BytesRead += Size;
-
-  // We place the LSDA into the LSDAEncoding vector for later analysis. If we
-  // have a ULEB128, we read that in separate iterations through here and then
-  // get its value.
-  if (!ReadingULEB128) {
-    LSDAEncoding.push_back(Value);
-    int EncodingSize = LSDAEncoding.size();
-
-    if (EncodingSize == 1 || EncodingSize == 3) {
-      // The LPStart and TType encodings.
-      if (Value != dwarf::DW_EH_PE_omit) {
-        // The encoding is next and is a ULEB128 value.
-        ReadingULEB128 = true;
-        ULEB128Value.clear();
-      } else {
-        // The encoding was omitted. Put a 0 here as a placeholder.
-        LSDAEncoding.push_back(0);
-      }
-    } else if (EncodingSize == 5) {
-      // The next value is a ULEB128 value that tells us how long the call site
-      // table is -- where the start of the action tab
-      ReadingULEB128 = true;
-      ULEB128Value.clear();
-    }
-
-    InLSDA = (LSDASize == 0 || BytesRead < LSDASize);
-  } else {
-    // We're reading a ULEB128. Make it so!
-    ULEB128Value.push_back(Value);
-
-    if ((Value & 0x80) == 0) {
-      uint64_t Val = GetULEB128Value(ULEB128Value);
-      LSDAEncoding.push_back(Val);
-      ULEB128Value.clear();
-      ReadingULEB128 = false;
-
-      if (LSDAEncoding.size() == 4)
-        // The fourth value tells us where the bottom of the type table is.
-        LSDASize = BytesRead + LSDAEncoding[3];
-      else if (LSDAEncoding.size() == 6)
-        // The sixth value tells us where the start of the action table is.
-        ActionTableBytes = BytesRead;
-    }
-  }
-
-  MCAsmStreamer::EmitValueImpl(MCConstantExpr::Create(Value, getContext()),
-                               Size, AddrSpace);
-
-  if (LSDASize != 0 && !InLSDA)
-    EmitEHTableDescription();
-}
-
-void MCLSDADecoderAsmStreamer::EmitValueImpl(const MCExpr *Value,
-                                             unsigned Size,
-                                             unsigned AddrSpace) {
-  if (InLSDA && LSDASize != 0) {
-    assert(BytesRead + Size <= LSDASize  && "EH table too small!");
-
-    if (BytesRead > uint64_t(LSDAEncoding[5]) + ActionTableBytes)
-      // Insert the type values.
-      Assignments.push_back(Value);
-
-    LSDAEncoding.push_back(Assignments.size());
-    BytesRead += Size;
-    InLSDA = (LSDASize == 0 || BytesRead < LSDASize);
-  }
-
-  MCAsmStreamer::EmitValueImpl(Value, Size, AddrSpace);
-
-  if (LSDASize != 0 && !InLSDA)
-    EmitEHTableDescription();
-}
-
-void MCLSDADecoderAsmStreamer::EmitFill(uint64_t NumBytes, uint8_t FillValue,
-                                        unsigned AddrSpace) {
-  if (InLSDA && ReadingULEB128) {
-    for (uint64_t I = NumBytes; I != 0; --I)
-      ULEB128Value.push_back(FillValue);
-
-    BytesRead += NumBytes;
-
-    if ((FillValue & 0x80) == 0) {
-      uint64_t Val = GetULEB128Value(ULEB128Value);
-      LSDAEncoding.push_back(Val);
-      ULEB128Value.clear();
-      ReadingULEB128 = false;
-
-      if (LSDAEncoding.size() == 4)
-        // The fourth value tells us where the bottom of the type table is.
-        LSDASize = BytesRead + LSDAEncoding[3];
-      else if (LSDAEncoding.size() == 6)
-        // The sixth value tells us where the start of the action table is.
-        ActionTableBytes = BytesRead;
-    }
-  }
-
-  MCAsmStreamer::EmitFill(NumBytes, FillValue, AddrSpace);
-}
-
-/// EmitEHTableDescription - Emit a human readable version of the LSDA.
-void MCLSDADecoderAsmStreamer::EmitEHTableDescription() {
-  assert(LSDAEncoding.size() > 6 && "Invalid LSDA!");
-
-  // Emit header information.
-  StringRef C = MAI.getCommentString();
-#define CMT OS << C << ' '
-  CMT << "Exception Handling Table: " << LSDASymbol->getName() << "\n";
-  CMT << " @LPStart Encoding: " << DecodeDWARFEncoding(LSDAEncoding[0]) << "\n";
-  if (LSDAEncoding[1])
-    CMT << "@LPStart: 0x" << LSDAEncoding[1] << "\n";
-  CMT << "   @TType Encoding: " << DecodeDWARFEncoding(LSDAEncoding[2]) << "\n";
-  CMT << "       @TType Base: " << LSDAEncoding[3] << " bytes\n";
-  CMT << "@CallSite Encoding: " << DecodeDWARFEncoding(LSDAEncoding[4]) << "\n";
-  CMT << "@Action Table Size: " << LSDAEncoding[5] << " bytes\n\n";
-
-  bool isSjLjEH = (MAI.getExceptionHandlingType() == ExceptionHandling::SjLj);
-
-  int64_t CallSiteTableSize = LSDAEncoding[5];
-  unsigned CallSiteEntrySize;
-  if (!isSjLjEH)
-    CallSiteEntrySize = 4 + // Region start.
-                        4 + // Region end.
-                        4 + // Landing pad.
-                        1;  // TType index.
-  else
-    CallSiteEntrySize = 1 + // Call index.
-                        1;  // TType index.
-
-  unsigned NumEntries = CallSiteTableSize / CallSiteEntrySize;
-  assert(CallSiteTableSize % CallSiteEntrySize == 0 &&
-         "The action table size is not a multiple of what it should be!");
-  unsigned TTypeIdx = 5 +              // Action table size index.
-     (isSjLjEH ? 2 : 4) * NumEntries + // Action table entries.
-                      1;               // Just because.
-
-  // Emit the action table.
-  unsigned Action = 1;
-  for (unsigned I = 6; I < TTypeIdx; ) {
-    CMT << "Action " << Action++ << ":\n";
-
-    // The beginning of the throwing region.
-    uint64_t Idx = LSDAEncoding[I++];
-
-    if (!isSjLjEH) {
-      CMT << "  A throw between "
-          << *cast<MCBinaryExpr>(Assignments[Idx - 1])->getLHS() << " and ";
-
-      // The end of the throwing region.
-      Idx = LSDAEncoding[I++];
-      OS << *cast<MCBinaryExpr>(Assignments[Idx - 1])->getLHS();
-
-      // The landing pad.
-      Idx = LSDAEncoding[I++];
-      if (Idx) {
-        OS << " jumps to "
-           << *cast<MCBinaryExpr>(Assignments[Idx - 1])->getLHS()
-           << " on an exception.\n";
-      } else {
-        OS << " does not have a landing pad.\n";
-        ++I;
-        continue;
-      }
-    } else {
-      CMT << "  A throw from call " << Idx << "\n";
-    }
-
-    // The index into the action table.
-    Idx = LSDAEncoding[I++];
-    if (!Idx) {
-      CMT << "    :cleanup:\n";
-      continue;
-    }
-
-    // A semi-graphical representation of what the different indexes are in the
-    // loop below.
-    //
-    //    Idx    - Index into the action table.
-    //    Action - Index into the type table from the type table base.
-    //    Next   - Offset from Idx to the next action type.
-    //
-    //                               Idx---.
-    //                                     |
-    //                                     v
-    //            [call site table] _1 _2 _3
-    // TTypeIdx--> .........................
-    //            [action 1] _1 _2
-    //            [action 2] _1 _2
-    //              ...
-    //            [action n] _1 _2
-    //            [type m]      ^
-    //              ...         |
-    //            [type 1]      `---Next
-    //
-
-    int Action = LSDAEncoding[TTypeIdx + Idx - 1];
-    if ((Action & 0x40) != 0)
-      // Ignore exception specifications.
-      continue;
-
-    // Emit the types that are caught by this exception.
-    CMT << "    For type(s): ";
-    for (;;) {
-      if ((Action & 0x40) != 0)
-        // Ignore exception specifications.
-        break;
-
-      if (uint64_t Ty = LSDAEncoding[LSDAEncoding.size() - Action]) {
-        OS << " " << *Assignments[Ty - 1];
-
-        // Types can be chained together. Typically, it's a negative offset from
-        // the current type to a different one in the type table.
-        int Next = LSDAEncoding[TTypeIdx + Idx];
-        if (Next == 0)
-          break;
-        if ((Next & 0x40) != 0)
-          Next = (int)(signed char)(Next | 0x80);
-        Idx += Next + 1;
-        Action = LSDAEncoding[TTypeIdx + Idx - 1];
-        continue;
-      } else {
-        OS << " :catchall:";
-      }
-      break;
-    }
-
-    OS << "\n";
-  }
-
-  OS << "\n";
-  ResetState();
-}
-
 MCStreamer *llvm::createAsmStreamer(MCContext &Context,
                                     formatted_raw_ostream &OS,
                                     bool isVerboseAsm, bool useLoc,
                                     bool useCFI, MCInstPrinter *IP,
                                     MCCodeEmitter *CE, TargetAsmBackend *TAB,
                                     bool ShowInst) {
-  ExceptionHandling::ExceptionsType ET =
-    Context.getAsmInfo().getExceptionHandlingType();
-
-  if (useCFI && isVerboseAsm &&
-      (ET == ExceptionHandling::SjLj || ET == ExceptionHandling::DwarfCFI))
-    return new MCLSDADecoderAsmStreamer(Context, OS, isVerboseAsm, useLoc,
-                                        useCFI, IP, CE, TAB, ShowInst);
-
   return new MCAsmStreamer(Context, OS, isVerboseAsm, useLoc, useCFI,
                            IP, CE, TAB, ShowInst);
 }



From aggarwa4 at illinois.edu  Mon Jun 20 17:22:32 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 20 Jun 2011 22:22:32 -0000
Subject: [llvm-commits] [poolalloc] r133474 -
 /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c
Message-ID: <20110620222232.CCBE32A6C12C@llvm.org>

Author: aggarwa4
Date: Mon Jun 20 17:22:32 2011
New Revision: 133474

URL: http://llvm.org/viewvc/llvm-project?rev=133474&view=rev
Log:
Break track Load into 2 parts, one that reads the
metadata and one that checks it. This is work to
break up the check on load to getting data at the load
and checking at the uses.

Modified:
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=133474&r1=133473&r2=133474&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Mon Jun 20 17:22:32 2011
@@ -150,29 +150,26 @@
   compareTypes(TypeAccessed, ((uint8_t*)MD)[ArgAccessed], tag);
 }
 
-/**
- * Check the loaded type against the type recorded in the shadow memory.
- */
-void trackLoadInst(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) {
-  uint8_t i = 1;
+void getTypeTag(void *ptr, uint64_t size, uint8_t *dest) {
   uintptr_t p = maskAddress(ptr);
   assert(p + size < SIZE);
 
-#if DEBUG
-  printf("Load(%d): %p, %p = actual: %u, expect: %u | %lu  bytes\n", tag, ptr, (void *)p, typeNumber, shadow_begin[p], size);
-#endif
+  memcpy(dest, &shadow_begin[p], size);
+}
 
+void checkType(uint8_t typeNumber, uint64_t size, uint8_t *metadata, void *ptr, uint32_t tag) {
+  uint8_t i = 1;
   /* Check if this an initialized but untyped memory.*/
-  if (typeNumber != shadow_begin[p]) {
-    if (shadow_begin[p] != 0xFF) {
-      printf("Type mismatch(%u): %p expecting %s, found %s!\n", tag, ptr, typeNames[typeNumber], typeNames[shadow_begin[p]]);
+  if (typeNumber != metadata[0]) {
+    if (metadata[0] != 0xFF) {
+      printf("Type mismatch(%u): %p expecting %s, found %s!\n", tag, ptr, typeNames[typeNumber], typeNames[metadata[0]]);
       return;
     } else {
       /* If so, set type to the type being read.
          Check that none of the bytes are typed.*/
       for (; i < size; ++i) {
-        if (0xFF != shadow_begin[p + i]) {
-          printf("Type alignment mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p+i]]);
+        if (0xFF != metadata[i]) {
+          printf("Type alignment mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[metadata[i]]);
           break;
         }
       }
@@ -182,12 +179,29 @@
   }
 
   for (; i < size; ++i) {
-    if (0 != shadow_begin[p + i]) {
-      printf("Type alignment mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[shadow_begin[p]]);
+    if (0 != metadata[i]) {
+      printf("Type alignment mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[metadata[0]]);
       break;
     }
   }
+
 }
+/**
+ * Check the loaded type against the type recorded in the shadow memory.
+ */
+void trackLoadInst(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) {
+  uint8_t *metadata = malloc(size);
+
+  getTypeTag(ptr, size, metadata);
+
+  checkType(typeNumber, size ,metadata, ptr, tag);
+#if DEBUG
+  printf("Load(%d): %p, %p = actual: %u, expect: %u | %lu  bytes\n", tag, ptr, (void *)p, typeNumber, shadow_begin[p], size);
+#endif
+
+  free(metadata);
+}
+
 
 /**
  *  For memset type instructions, that set values. 



From aggarwa4 at illinois.edu  Mon Jun 20 17:57:07 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Mon, 20 Jun 2011 22:57:07 -0000
Subject: [llvm-commits] [poolalloc] r133477 -
	/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
Message-ID: <20110620225708.045C32A6C12C@llvm.org>

Author: aggarwa4
Date: Mon Jun 20 17:57:07 2011
New Revision: 133477

URL: http://llvm.org/viewvc/llvm-project?rev=133477&view=rev
Log:
WIP: Break up the calls to track Load into 2 parts, one to get
the metadata, one to do check.

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133477&r1=133476&r2=133477&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Mon Jun 20 17:57:07 2011
@@ -63,6 +63,7 @@
 static Constant *RegisterArgv;
 static Constant *RegisterEnvp;
 static Constant *compareTypeAndNumber;
+static Constant *getTypeTag;
 
 unsigned int TypeChecks::getTypeMarker(const Type * Ty) {
   if(DisablePointerTypeChecks) {
@@ -156,11 +157,18 @@
                                          Int64Ty,/*size*/
                                          Int32Ty,/*tag*/
                                          NULL);
-  trackLoadInst = M.getOrInsertFunction("trackLoadInst",
+  getTypeTag = M.getOrInsertFunction("getTypeTag",
+                                     VoidTy,
+                                     VoidPtrTy, /*ptr*/
+                                     Int64Ty, /*size*/
+                                     VoidPtrTy, /*dest for type tag*/
+                                     NULL);
+  trackLoadInst = M.getOrInsertFunction("checkType",
                                         VoidTy,
-                                        VoidPtrTy,/*ptr*/
                                         Int8Ty,/*type*/
                                         Int64Ty,/*size*/
+                                        VoidPtrTy,
+                                        VoidPtrTy,/*ptr*/
                                         Int32Ty,/*tag*/
                                         NULL);
   copyTypeInfo = M.getOrInsertFunction("copyTypeInfo",
@@ -253,14 +261,14 @@
       continue;
     }
   }
-  
+
   // Modify all byval functions
   while(!ByValFunctions.empty()) {
     Function *F = ByValFunctions.back();
     ByValFunctions.pop_back();
     modified |= visitByValFunction(M, *F);
   }
-  
+
 
   // NOTE:must visit before VAArgFunctions, to populate the map with the
   // correct cloned functions.
@@ -273,7 +281,7 @@
   // iterate through all the VAList funtions and modify call sites
   // to call the new function 
   std::map<Function *, Function *>::iterator FI = VAListFunctionsMap.begin(), 
-                                             FE = VAListFunctionsMap.end();
+    FE = VAListFunctionsMap.end();
   for(; FI != FE; FI++) {
     visitVAListCall(FI->second);
   }
@@ -291,7 +299,7 @@
       continue;
     visitAddressTakenFunction(M, *F);
   }
-  
+
   for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) {
     Function &F = *MI;
     if(F.isDeclaration())
@@ -337,7 +345,7 @@
     Function *F = FI->first;
 
     Constant *CNew = ConstantExpr::getBitCast(FI->second, F->getType());
-    
+
     std::set<User *> toReplace;
     for(Function::use_iterator User = F->use_begin();
         User != F->use_end();++User) {
@@ -374,7 +382,7 @@
           // Temporary fix. Revisit.
           //
           //for (unsigned index = 0; index < ReplaceWorklist.size(); ++index) {
-            C->replaceUsesOfWithOnConstant(F, CNew, ReplaceWorklist[0]);
+          C->replaceUsesOfWithOnConstant(F, CNew, ReplaceWorklist[0]);
           //}
           continue;
         }
@@ -431,7 +439,7 @@
   // For each used type, create a new entry. 
   // Also add these strings to the Values list
   std::map<const Type*, unsigned int >::iterator TI = UsedTypes.begin(),
-                                                 TE = UsedTypes.end(); 
+    TE = UsedTypes.end(); 
   for(;TI!=TE; ++TI) {
     std::string *type = new std::string();
     llvm::raw_string_ostream *test = new llvm::raw_string_ostream(*type);
@@ -502,146 +510,146 @@
   }
 }
 
-bool TypeChecks::visitVAListFunction(Module &M, Function &F_orig) {
-  if(!F_orig.hasInternalLinkage())
-    return false;
+  bool TypeChecks::visitVAListFunction(Module &M, Function &F_orig) {
+    if(!F_orig.hasInternalLinkage())
+      return false;
 
-  int VAListArgNum = 0;
-  // Check if one of the arguments is a va_list
-  const Type *ListType  = M.getTypeByName("struct.__va_list_tag");
-  if(!ListType)
-    return false;
-  const Type *ListPtrType = ListType->getPointerTo();
-  Argument *VAListArg = NULL; 
-  for (Function::arg_iterator I = F_orig.arg_begin(); 
-       I != F_orig.arg_end(); ++I) {
-    VAListArgNum ++;
-    if(I->getType() == ListPtrType) {
-      VAListArg = I;
-      break;
+    int VAListArgNum = 0;
+    // Check if one of the arguments is a va_list
+    const Type *ListType  = M.getTypeByName("struct.__va_list_tag");
+    if(!ListType)
+      return false;
+    const Type *ListPtrType = ListType->getPointerTo();
+    Argument *VAListArg = NULL; 
+    for (Function::arg_iterator I = F_orig.arg_begin(); 
+         I != F_orig.arg_end(); ++I) {
+      VAListArgNum ++;
+      if(I->getType() == ListPtrType) {
+        VAListArg = I;
+        break;
+      }
     }
-  }
-
-  // Clone the function to add arguments for count, MD
-
-  // 1. Create the new argument types vector
-  std::vector<const Type*>TP;
-  TP.push_back(Int64Ty); // for count
-  TP.push_back(Int64Ty); // for count
-  TP.push_back(VoidPtrTy); // for MD
-  for (Function::arg_iterator I = F_orig.arg_begin();
-       I != F_orig.arg_end(); ++I) {
-    TP.push_back(I->getType());
-  }
-  // 2. Create the new function prototype
-  const FunctionType *NewFTy = FunctionType::get(F_orig.getReturnType(),
-                                                 TP,/*argument types*/
-                                                 false);/*vararg*/
-  Function *F = Function::Create(NewFTy,
-                                 GlobalValue::InternalLinkage,
-                                 F_orig.getNameStr() + ".INT",
-                                 &M);
-
-  // 3. Set the mapping for args
-  Function::arg_iterator NI = F->arg_begin();
-  DenseMap<const Value*, Value*> ValueMap;
-  NI->setName("TotalCount");
-  NI++;
-  NI->setName("CurrentCount");
-  NI++;
-  NI->setName("MD");
-  NI++;
-  for (Function::arg_iterator II = F_orig.arg_begin(); 
-       NI != F->arg_end(); ++II, ++NI) {
-    // Each new argument maps to the argument in the old function
-    // For these arguments, also copy over the attributes
-    ValueMap[II] = NI;
-    NI->setName(II->getName());
-    NI->addAttr(F_orig.getAttributes()
-                .getParamAttributes(II->getArgNo() + 1));
-  }
-
-  // 4. Copy over the attributes for the function.
-  F->setAttributes(F->getAttributes()
-                   .addAttr(0, F_orig.getAttributes().getRetAttributes()));
-  F->setAttributes(F->getAttributes()
-                   .addAttr(~0, F_orig.getAttributes().getFnAttributes()));
-
-  // 5. Perform the cloning.
-  SmallVector<ReturnInst*,100> Returns;
-  CloneFunctionInto(F, &F_orig, ValueMap, Returns);
 
-  VAListFunctionsMap[&F_orig] =  F;
-  inst_iterator InsPt = inst_begin(F);
+    // Clone the function to add arguments for count, MD
 
-  
-  // Store the information
-  Function::arg_iterator NII = F->arg_begin();
-  AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt);
-  new StoreInst(NII, VASizeLoc, &*InsPt);
-  NII++;
-  AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt);
-  new StoreInst(NII, Counter, &*InsPt); 
-  CounterMap[NII] = Counter;
-  NII++;
-  AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt);
-  new StoreInst(NII, VAMDLoc, &*InsPt);
-  
-  // Find all va_copy calls
-  for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
-    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;I++) {
-      CallInst *CI = dyn_cast<CallInst>(I);
-      if(!CI)
-        continue;
-      Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
-      if(!CalledF)
-        continue;
-      if(!CalledF->isIntrinsic())
-        continue;
-      if(CalledF->getIntrinsicID() != Intrinsic::vacopy) 
-        continue;
-      // Reinitialize the counter
-      AllocaInst *CounterDest = new AllocaInst(Int64Ty, "",&*InsPt);
-      Value *CounterSource = CounterMap[CI->getOperand(2)->stripPointerCasts()];
-      LoadInst *CurrentValue = new LoadInst(CounterSource, "count", CI);
-      new StoreInst(CurrentValue, CounterDest, CI);
-      CounterMap[CI->getOperand(1)->stripPointerCasts()] = CounterDest;
+    // 1. Create the new argument types vector
+    std::vector<const Type*>TP;
+    TP.push_back(Int64Ty); // for count
+    TP.push_back(Int64Ty); // for count
+    TP.push_back(VoidPtrTy); // for MD
+    for (Function::arg_iterator I = F_orig.arg_begin();
+         I != F_orig.arg_end(); ++I) {
+      TP.push_back(I->getType());
+    }
+    // 2. Create the new function prototype
+    const FunctionType *NewFTy = FunctionType::get(F_orig.getReturnType(),
+                                                   TP,/*argument types*/
+                                                   false);/*vararg*/
+    Function *F = Function::Create(NewFTy,
+                                   GlobalValue::InternalLinkage,
+                                   F_orig.getNameStr() + ".INT",
+                                   &M);
+
+    // 3. Set the mapping for args
+    Function::arg_iterator NI = F->arg_begin();
+    DenseMap<const Value*, Value*> ValueMap;
+    NI->setName("TotalCount");
+    NI++;
+    NI->setName("CurrentCount");
+    NI++;
+    NI->setName("MD");
+    NI++;
+    for (Function::arg_iterator II = F_orig.arg_begin(); 
+         NI != F->arg_end(); ++II, ++NI) {
+      // Each new argument maps to the argument in the old function
+      // For these arguments, also copy over the attributes
+      ValueMap[II] = NI;
+      NI->setName(II->getName());
+      NI->addAttr(F_orig.getAttributes()
+                  .getParamAttributes(II->getArgNo() + 1));
+    }
+
+    // 4. Copy over the attributes for the function.
+    F->setAttributes(F->getAttributes()
+                     .addAttr(0, F_orig.getAttributes().getRetAttributes()));
+    F->setAttributes(F->getAttributes()
+                     .addAttr(~0, F_orig.getAttributes().getFnAttributes()));
+
+    // 5. Perform the cloning.
+    SmallVector<ReturnInst*,100> Returns;
+    CloneFunctionInto(F, &F_orig, ValueMap, Returns);
+
+    VAListFunctionsMap[&F_orig] =  F;
+    inst_iterator InsPt = inst_begin(F);
+
+
+    // Store the information
+    Function::arg_iterator NII = F->arg_begin();
+    AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt);
+    new StoreInst(NII, VASizeLoc, &*InsPt);
+    NII++;
+    AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt);
+    new StoreInst(NII, Counter, &*InsPt); 
+    CounterMap[NII] = Counter;
+    NII++;
+    AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt);
+    new StoreInst(NII, VAMDLoc, &*InsPt);
+
+    // Find all va_copy calls
+    for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
+      for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;I++) {
+        CallInst *CI = dyn_cast<CallInst>(I);
+        if(!CI)
+          continue;
+        Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
+        if(!CalledF)
+          continue;
+        if(!CalledF->isIntrinsic())
+          continue;
+        if(CalledF->getIntrinsicID() != Intrinsic::vacopy) 
+          continue;
+        // Reinitialize the counter
+        AllocaInst *CounterDest = new AllocaInst(Int64Ty, "",&*InsPt);
+        Value *CounterSource = CounterMap[CI->getOperand(2)->stripPointerCasts()];
+        LoadInst *CurrentValue = new LoadInst(CounterSource, "count", CI);
+        new StoreInst(CurrentValue, CounterDest, CI);
+        CounterMap[CI->getOperand(1)->stripPointerCasts()] = CounterDest;
+      }
     }
-  }
 
 
-  // instrument va_arg to increment the counter
-  for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
-    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
-      VAArgInst *VI = dyn_cast<VAArgInst>(I++);
-      if(!VI)
-        continue;
-      Constant *One = ConstantInt::get(Int64Ty, 1);
-      Value *CounterSrc = CounterMap[VI->getOperand(0)->stripPointerCasts()];
-      LoadInst *OldValue = new LoadInst(CounterSrc, "count", VI);
-      Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add,
-                                                     OldValue,
-                                                     One,
-                                                     "count",
-                                                     VI);
-      new StoreInst(NewValue, CounterSrc, VI);
-      std::vector<Value *> Args;
-      Instruction *VASize = new LoadInst(VASizeLoc, "", VI);
-      Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI);
-      Args.push_back(VASize);
-      Args.push_back(OldValue);
-      Args.push_back(getTypeMarkerConstant(VI));
-      Args.push_back(VAMetaData);
-      Args.push_back(getTagCounter());
-      CallInst::Create(compareTypeAndNumber,
-                       Args.begin(),
-                       Args.end(),
-                       "", VI);
+    // instrument va_arg to increment the counter
+    for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
+      for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
+        VAArgInst *VI = dyn_cast<VAArgInst>(I++);
+        if(!VI)
+          continue;
+        Constant *One = ConstantInt::get(Int64Ty, 1);
+        Value *CounterSrc = CounterMap[VI->getOperand(0)->stripPointerCasts()];
+        LoadInst *OldValue = new LoadInst(CounterSrc, "count", VI);
+        Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add,
+                                                       OldValue,
+                                                       One,
+                                                       "count",
+                                                       VI);
+        new StoreInst(NewValue, CounterSrc, VI);
+        std::vector<Value *> Args;
+        Instruction *VASize = new LoadInst(VASizeLoc, "", VI);
+        Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI);
+        Args.push_back(VASize);
+        Args.push_back(OldValue);
+        Args.push_back(getTypeMarkerConstant(VI));
+        Args.push_back(VAMetaData);
+        Args.push_back(getTagCounter());
+        CallInst::Create(compareTypeAndNumber,
+                         Args.begin(),
+                         Args.end(),
+                         "", VI);
+      }
     }
-  }
 
-  return true;
-}
+    return true;
+  }
 
 bool TypeChecks::visitAddressTakenFunction(Module &M, Function &F) {
   // Clone function
@@ -1376,30 +1384,30 @@
   return true;
 }
 
-bool TypeChecks::visitMain(Module &M, Function &MainFunc) {
-  if(MainFunc.arg_size() < 2)
-    // No need to register
-    return false;
+  bool TypeChecks::visitMain(Module &M, Function &MainFunc) {
+    if(MainFunc.arg_size() < 2)
+      // No need to register
+      return false;
+
+    Function::arg_iterator AI = MainFunc.arg_begin();
+    Value *Argc = AI;
+    Value *Argv = ++AI;
+
+    Instruction *InsertPt = MainFunc.front().begin();
+    std::vector<Value *> fargs;
+    fargs.push_back (Argc);
+    fargs.push_back (Argv);
+    CallInst::Create (RegisterArgv, fargs.begin(), fargs.end(), "", InsertPt);
 
-  Function::arg_iterator AI = MainFunc.arg_begin();
-  Value *Argc = AI;
-  Value *Argv = ++AI;
-
-  Instruction *InsertPt = MainFunc.front().begin();
-  std::vector<Value *> fargs;
-  fargs.push_back (Argc);
-  fargs.push_back (Argv);
-  CallInst::Create (RegisterArgv, fargs.begin(), fargs.end(), "", InsertPt);
+    if(MainFunc.arg_size() < 3)
+      return true;
 
-  if(MainFunc.arg_size() < 3)
+    Value *Envp = ++AI;
+    std::vector<Value*> Args;
+    Args.push_back(Envp);
+    CallInst::Create(RegisterEnvp, Args.begin(), Args.end(), "", InsertPt);
     return true;
-
-  Value *Envp = ++AI;
-  std::vector<Value*> Args;
-  Args.push_back(Envp);
-  CallInst::Create(RegisterEnvp, Args.begin(), Args.end(), "", InsertPt);
-  return true;
-}
+  }
 
 bool TypeChecks::visitGlobal(Module &M, GlobalVariable &GV, 
                              Constant *C, Instruction &I, SmallVector<Value *,8> Indices) {
@@ -1956,17 +1964,40 @@
 
 // Insert runtime checks before all load instructions.
 bool TypeChecks::visitLoadInst(Module &M, LoadInst &LI) {
+  inst_iterator InsPt = inst_begin(LI.getParent()->getParent());
   // Cast the pointer operand to i8* for the runtime function.
   CastInst *BCI = BitCastInst::CreatePointerCast(LI.getPointerOperand(), VoidPtrTy, "", &LI);
 
+  Value *Size = ConstantInt::get(Int32Ty, getSize(LI.getType()));
+  AllocaInst *AI = new AllocaInst(Int8Ty, Size, "", &*InsPt);
+  CastInst *BCI_MD = BitCastInst::CreatePointerCast(AI, VoidPtrTy, "", &*InsPt);
+
+  std::vector<Value *>Args1;
+  Args1.push_back(BCI);
+  Args1.push_back(getSizeConstant(LI.getType()));
+  Args1.push_back(BCI_MD);
+  CallInst::Create(getTypeTag, Args1.begin(), Args1.end(), "", &LI);
   std::vector<Value *> Args;
-  Args.push_back(BCI);
   Args.push_back(getTypeMarkerConstant(&LI));
   Args.push_back(getSizeConstant(LI.getType()));
+  Args.push_back(BCI_MD);
+  Args.push_back(BCI);
   Args.push_back(getTagCounter());
+  CallInst::Create(trackLoadInst, Args.begin(), Args.end(), "", &LI);
+
+  /*for(Value::use_iterator II = LI.use_begin(); II != LI.use_end(); ++II) {
+
+    std::vector<Value *> Args;
+    Args.push_back(getTypeMarkerConstant(&LI));
+    Args.push_back(getSizeConstant(LI.getType()));
+    Args.push_back(BCI_MD);
+    Args.push_back(BCI);
+    Args.push_back(getTagCounter());
+    CallInst::Create(trackLoadInst, Args.begin(), Args.end(), "", cast<Instruction>(II.getUse().getUser()));
+  }*/
 
   // Create the call to the runtime check and place it before the load instruction.
-  CallInst::Create(trackLoadInst, Args.begin(), Args.end(), "", &LI);
+  //CallInst::Create(trackLoadInst, Args.begin(), Args.end(), "", &LI);
   numLoadChecks++;
   return true;
 }



From gohman at apple.com  Mon Jun 20 18:20:43 2011
From: gohman at apple.com (Dan Gohman)
Date: Mon, 20 Jun 2011 23:20:43 -0000
Subject: [llvm-commits] [llvm] r133478 -
	/llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp
Message-ID: <20110620232043.BE5F72A6C12C@llvm.org>

Author: djg
Date: Mon Jun 20 18:20:43 2011
New Revision: 133478

URL: http://llvm.org/viewvc/llvm-project?rev=133478&view=rev
Log:
Completely short-circuit out ARC optimization if the ARC runtime
functions do not appear in the module.

Modified:
    llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp?rev=133478&r1=133477&r2=133478&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ObjCARC.cpp Mon Jun 20 18:20:43 2011
@@ -33,6 +33,7 @@
 #include "llvm/Intrinsics.h"
 #include "llvm/GlobalVariable.h"
 #include "llvm/DerivedTypes.h"
+#include "llvm/Module.h"
 #include "llvm/Analysis/ValueTracking.h"
 #include "llvm/Transforms/Utils/Local.h"
 #include "llvm/Support/CallSite.h"
@@ -564,6 +565,29 @@
   return 0;
 }
 
+/// ModuleHasARC - Test if the given module looks interesting to run ARC
+/// optimization on.
+static bool ModuleHasARC(const Module &M) {
+  return
+    M.getNamedValue("objc_retain") ||
+    M.getNamedValue("objc_release") ||
+    M.getNamedValue("objc_autorelease") ||
+    M.getNamedValue("objc_retainAutoreleasedReturnValue") ||
+    M.getNamedValue("objc_retainBlock") ||
+    M.getNamedValue("objc_autoreleaseReturnValue") ||
+    M.getNamedValue("objc_autoreleasePoolPush") ||
+    M.getNamedValue("objc_loadWeakRetained") ||
+    M.getNamedValue("objc_loadWeak") ||
+    M.getNamedValue("objc_destroyWeak") ||
+    M.getNamedValue("objc_storeWeak") ||
+    M.getNamedValue("objc_initWeak") ||
+    M.getNamedValue("objc_moveWeak") ||
+    M.getNamedValue("objc_copyWeak") ||
+    M.getNamedValue("objc_retainedObject") ||
+    M.getNamedValue("objc_unretainedObject") ||
+    M.getNamedValue("objc_unretainedPointer");
+}
+
 //===----------------------------------------------------------------------===//
 // ARC AliasAnalysis.
 //===----------------------------------------------------------------------===//
@@ -749,8 +773,12 @@
   /// ObjCARCExpand - Early ARC transformations.
   class ObjCARCExpand : public FunctionPass {
     virtual void getAnalysisUsage(AnalysisUsage &AU) const;
+    virtual bool doInitialization(Module &M);
     virtual bool runOnFunction(Function &F);
 
+    /// Run - A flag indicating whether this optimization pass should run.
+    bool Run;
+
   public:
     static char ID;
     ObjCARCExpand() : FunctionPass(ID) {
@@ -771,10 +799,19 @@
   AU.setPreservesCFG();
 }
 
+bool ObjCARCExpand::doInitialization(Module &M) {
+  Run = ModuleHasARC(M);
+  return false;
+}
+
 bool ObjCARCExpand::runOnFunction(Function &F) {
   if (!EnableARCOpts)
     return false;
 
+  // If nothing in the Module uses ARC, don't do anything.
+  if (!Run)
+    return false;
+
   bool Changed = false;
 
   for (inst_iterator I = inst_begin(&F), E = inst_end(&F); I != E; ++I) {
@@ -840,8 +877,9 @@
 // usually can't sink them past other calls, which would be the main
 // case where it would be useful.
 
+/// TODO: The pointer returned from objc_loadWeakRetained is retained.
+
 #include "llvm/GlobalAlias.h"
-#include "llvm/Module.h"
 #include "llvm/Constants.h"
 #include "llvm/LLVMContext.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -1365,10 +1403,12 @@
     bool Changed;
     ProvenanceAnalysis PA;
 
+    /// Run - A flag indicating whether this optimization pass should run.
+    bool Run;
+
     /// RetainFunc, RelaseFunc - Declarations for objc_retain,
     /// objc_retainBlock, and objc_release.
-    Function *RetainFunc, *RetainBlockFunc, *RetainRVFunc, *ReleaseFunc,
-             *AutoreleaseFunc;
+    Function *RetainFunc, *RetainBlockFunc, *RetainRVFunc, *ReleaseFunc;
 
     /// RetainRVCallee, etc. - Declarations for ObjC runtime
     /// functions, for use in creating calls to them. These are initialized
@@ -3069,6 +3109,10 @@
   if (!EnableARCOpts)
     return false;
 
+  Run = ModuleHasARC(M);
+  if (!Run)
+    return false;
+
   // Identify the imprecise release metadata kind.
   ImpreciseReleaseMDKind =
     M.getContext().getMDKindID("clang.imprecise_release");
@@ -3078,7 +3122,6 @@
   RetainBlockFunc = M.getFunction("objc_retainBlock");
   RetainRVFunc = M.getFunction("objc_retainAutoreleasedReturnValue");
   ReleaseFunc = M.getFunction("objc_release");
-  AutoreleaseFunc = M.getFunction("objc_autorelease");
 
   // Intuitively, objc_retain and others are nocapture, however in practice
   // they are not, because they return their argument value. And objc_release
@@ -3098,6 +3141,10 @@
   if (!EnableARCOpts)
     return false;
 
+  // If nothing in the Module uses ARC, don't do anything.
+  if (!Run)
+    return false;
+
   Changed = false;
 
   PA.setAA(&getAnalysis<AliasAnalysis>());
@@ -3162,6 +3209,9 @@
     DominatorTree *DT;
     ProvenanceAnalysis PA;
 
+    /// Run - A flag indicating whether this optimization pass should run.
+    bool Run;
+
     /// StoreStrongCallee, etc. - Declarations for ObjC runtime
     /// functions, for use in creating calls to them. These are initialized
     /// lazily to avoid cluttering up the Module with unused declarations.
@@ -3384,6 +3434,10 @@
 }
 
 bool ObjCARCContract::doInitialization(Module &M) {
+  Run = ModuleHasARC(M);
+  if (!Run)
+    return false;
+
   // These are initialized lazily.
   StoreStrongCallee = 0;
   RetainAutoreleaseCallee = 0;
@@ -3407,6 +3461,10 @@
   if (!EnableARCOpts)
     return false;
 
+  // If nothing in the Module uses ARC, don't do anything.
+  if (!Run)
+    return false;
+
   Changed = false;
   AA = &getAnalysis<AliasAnalysis>();
   DT = &getAnalysis<DominatorTree>();



From kledzik at apple.com  Mon Jun 20 18:47:02 2011
From: kledzik at apple.com (Nick Kledzik)
Date: Mon, 20 Jun 2011 23:47:02 -0000
Subject: [llvm-commits] [compiler-rt] r133481 - in /compiler-rt/trunk/make:
	lib_info.mk options.mk
Message-ID: <20110620234702.2CF862A6C12C@llvm.org>

Author: kledzik
Date: Mon Jun 20 18:47:02 2011
New Revision: 133481

URL: http://llvm.org/viewvc/llvm-project?rev=133481&view=rev
Log:
add STRIP and LIPO as AvailableOptions

Modified:
    compiler-rt/trunk/make/lib_info.mk
    compiler-rt/trunk/make/options.mk

Modified: compiler-rt/trunk/make/lib_info.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/lib_info.mk?rev=133481&r1=133480&r2=133481&view=diff
==============================================================================
--- compiler-rt/trunk/make/lib_info.mk (original)
+++ compiler-rt/trunk/make/lib_info.mk Mon Jun 20 18:47:02 2011
@@ -48,4 +48,5 @@
                     CC CFLAGS FUNCTIONS OPTIMIZED \
                     RANLIB RANLIBFLAGS \
                     VISIBILITY_HIDDEN \
-                    KERNEL_USE
+                    KERNEL_USE \
+                    STRIP LIPO

Modified: compiler-rt/trunk/make/options.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/options.mk?rev=133481&r1=133480&r2=133481&view=diff
==============================================================================
--- compiler-rt/trunk/make/options.mk (original)
+++ compiler-rt/trunk/make/options.mk Mon Jun 20 18:47:02 2011
@@ -31,3 +31,6 @@
 RANLIB := ranlib
 # FIXME: Remove these pipes once ranlib errors are fixed.
 RANLIBFLAGS := 2> /dev/null
+
+STRIP := strip
+LIPO := lipo



From dpatel at apple.com  Mon Jun 20 18:55:02 2011
From: dpatel at apple.com (Devang Patel)
Date: Mon, 20 Jun 2011 23:55:02 -0000
Subject: [llvm-commits] [llvm-gcc-4.2] r133482 - in /llvm-gcc-4.2/trunk/gcc:
 c-pch.c llvm-backend.cpp llvm.h testsuite/g++.dg/pch/template-2.C
 testsuite/g++.dg/pch/template-2.Hs
Message-ID: <20110620235502.7B6F82A6C12C@llvm.org>

Author: dpatel
Date: Mon Jun 20 18:55:02 2011
New Revision: 133482

URL: http://llvm.org/viewvc/llvm-project?rev=133482&view=rev
Log:
If TypeUsers are lazily read from PCH only when a function is emitted then they may never happen. Read TypeUsers after reading PCH.

Added:
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.dg/pch/template-2.C
    llvm-gcc-4.2/trunk/gcc/testsuite/g++.dg/pch/template-2.Hs
Modified:
    llvm-gcc-4.2/trunk/gcc/c-pch.c
    llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
    llvm-gcc-4.2/trunk/gcc/llvm.h

Modified: llvm-gcc-4.2/trunk/gcc/c-pch.c
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/c-pch.c?rev=133482&r1=133481&r2=133482&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/c-pch.c (original)
+++ llvm-gcc-4.2/trunk/gcc/c-pch.c Mon Jun 20 18:55:02 2011
@@ -446,6 +446,12 @@
      been loaded.  */
   if (lang_post_pch_load)
     (*lang_post_pch_load) ();
+  /* LLVM LOCAL begin */
+#ifdef ENABLE_LLVM
+  llvm_post_pch_read();
+#endif
+  /* LLVM LOCAL end */
+
 }
 
 /* Indicate that no more PCH files should be read.  */

Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=133482&r1=133481&r2=133482&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Mon Jun 20 18:55:02 2011
@@ -633,6 +633,11 @@
   flag_llvm_pch_read = 1;
 }
 
+// Initialize remainign llvm specific data structures after pch is loaded.
+void llvm_post_pch_read() {
+  readLLVMTypeUsers();
+}
+
 /// llvm_pch_write_init - Initialize PCH writing. 
 void llvm_pch_write_init(void) {
   timevar_push(TV_LLVM_INIT);
@@ -1123,17 +1128,6 @@
     return;  // Do not process broken code.
   }
 
-  // Initial fill of TypeRefinementDatabase::TypeUsers[] if we're
-  // using a PCH.  Won't work until the GCC PCH has been read in and
-  // digested.
-  {
-    static bool done = false;
-    if (!done && flag_llvm_pch_read) {
-      readLLVMTypeUsers();
-      done = true;
-    }
-  }
-
   timevar_push(TV_LLVM_FUNCS);
 
   // Convert the AST to raw/ugly LLVM code.

Modified: llvm-gcc-4.2/trunk/gcc/llvm.h
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm.h?rev=133482&r1=133481&r2=133482&view=diff
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/llvm.h (original)
+++ llvm-gcc-4.2/trunk/gcc/llvm.h Mon Jun 20 18:55:02 2011
@@ -103,6 +103,9 @@
 /* Read bytecodes from PCH file.  */
 void llvm_pch_read(const unsigned char *, unsigned);
 
+/* Initialize remainign llvm specific data structures after pch is loaded.  */
+void llvm_post_pch_read(void);
+
 /* llvm_asm_file_start - Start the .s file. */
 void llvm_asm_file_start(void);
 

Added: llvm-gcc-4.2/trunk/gcc/testsuite/g++.dg/pch/template-2.C
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.dg/pch/template-2.C?rev=133482&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.dg/pch/template-2.C (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.dg/pch/template-2.C Mon Jun 20 18:55:02 2011
@@ -0,0 +1,2 @@
+/* { dg-options "-m32 -I." } */
+#include "template-2.H"

Added: llvm-gcc-4.2/trunk/gcc/testsuite/g++.dg/pch/template-2.Hs
URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/testsuite/g%2B%2B.dg/pch/template-2.Hs?rev=133482&view=auto
==============================================================================
--- llvm-gcc-4.2/trunk/gcc/testsuite/g++.dg/pch/template-2.Hs (added)
+++ llvm-gcc-4.2/trunk/gcc/testsuite/g++.dg/pch/template-2.Hs Mon Jun 20 18:55:02 2011
@@ -0,0 +1,34 @@
+/* { dg-options "-m32 -I." } */
+
+
+namespace ATL
+{
+
+typedef struct 
+{
+unsigned int size;
+} my_module;
+
+class CAM1;
+__attribute__((weak)) CAM1* _p1 = __null;
+class CAM1 : public my_module
+{
+};
+
+template <class T>
+class CAM1T : public CAM1
+{
+public :
+	CAM1T() throw() {}
+};
+
+class CAM2;
+__attribute__((weak)) CAM2* _pModule = __null;
+class CAM2 : public CAM1T<CAM2>
+{
+public :
+	CAM2() {}
+};
+
+}
+



From cdavis at mymail.mines.edu  Mon Jun 20 19:13:25 2011
From: cdavis at mymail.mines.edu (Charles Davis)
Date: Mon, 20 Jun 2011 18:13:25 -0600
Subject: [llvm-commits] [llvm] r133452 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/bitcast2.ll
 test/CodeGen/X86/vec_set-8.ll test/CodeGen/X86/vec_set-9.ll
 test/CodeGen/X86/vec_set-C.ll test/CodeGen/X86/vec_shuffle-14.ll
 test/CodeGen/X86/vec_shuffle-17.ll test/MC/X86/x86-64.s
 test/MC/X86/x86_64-avx-encoding.s
In-Reply-To: <20110620183327.3F55D2A6C12C@llvm.org>
References: <20110620183327.3F55D2A6C12C@llvm.org>
Message-ID: <4DFFE225.5010807@mymail.mines.edu>

On 6/20/11 12:33 PM, Nick Lewycky wrote:
> Author: nicholas
> Date: Mon Jun 20 13:33:26 2011
> New Revision: 133452
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133452&view=rev
> Log:
> Emit movq for 64-bit register to XMM register moves, but continue to accept
> movd when assembling.
This breaks compiling compiler-rt on Mac OS X like so:

/tmp/cc-E8HNBz.s:7:suffix or operands invalid for `movq'
clang: error: assembler command failed with exit code 1 (use -v to see
invocation)
make[5]: ***
[.../llvm/build1/tools/clang/runtime/compiler-rt/clang_darwin/cc_kext/x86_64/SubDir.lib/fixdfti.o]
Error 1

There are several more errors like that.

Xcode 4.0's assembler still has the movq bug. We still have to produce
movd on Darwin when not using the integrated assembler.

Chip

From kledzik at apple.com  Mon Jun 20 19:07:55 2011
From: kledzik at apple.com (Nick Kledzik)
Date: Tue, 21 Jun 2011 00:07:55 -0000
Subject: [llvm-commits] [compiler-rt] r133487 - in /compiler-rt/trunk/make:
 AppleBI.mk platform/darwin_bni.mk
Message-ID: <20110621000755.DC1D22A6C12C@llvm.org>

Author: kledzik
Date: Mon Jun 20 19:07:55 2011
New Revision: 133487

URL: http://llvm.org/viewvc/llvm-project?rev=133487&view=rev
Log:
<rdar://problem/9624306> clean up darwin platform to use xcrun. Set up variables in darwin_bni.mk.  Use GetCNAVar in AppleBI.mk

Modified:
    compiler-rt/trunk/make/AppleBI.mk
    compiler-rt/trunk/make/platform/darwin_bni.mk

Modified: compiler-rt/trunk/make/AppleBI.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/AppleBI.mk?rev=133487&r1=133486&r2=133487&view=diff
==============================================================================
--- compiler-rt/trunk/make/AppleBI.mk (original)
+++ compiler-rt/trunk/make/AppleBI.mk Mon Jun 20 19:07:55 2011
@@ -14,17 +14,12 @@
 
 ifeq (,$(SDKROOT))
 	INSTALL_TARGET = install-MacOSX
-    LD_OTHER_FLAGS =
 else
 	INSTALL_TARGET = install-iOS
-	CFLAGS.Release.armv6 := $(CFLAGS) -Wall -Os -fomit-frame-pointer -g -isysroot $(SDKROOT)
-	CFLAGS.Release.armv7 := $(CFLAGS) -Wall -Os -fomit-frame-pointer -g -isysroot $(SDKROOT)
-	CFLAGS.Static.armv6  := $(CFLAGS) -Wall -Os -fomit-frame-pointer -g -isysroot $(SDKROOT) -static 
-	CFLAGS.Static.armv7  := $(CFLAGS) -Wall -Os -fomit-frame-pointer -g -isysroot $(SDKROOT) -static 
-    LD_OTHER_FLAGS = -Wl,-alias_list,$(SRCROOT)/lib/arm/softfloat-alias.list -isysroot $(SDKROOT)
 endif
 
 
+
 # Log full compile lines in B&I logs and omit summary lines.
 Verb :=
 Summary := @true
@@ -49,7 +44,7 @@
 	cp $(SYMROOT)/libcompiler_rt-dyld.a  \
 				    $(DSTROOT)/usr/local/lib/dyld/libcompiler_rt.a
 	mkdir -p $(DSTROOT)/usr/lib/system
-	strip -S $(SYMROOT)/libcompiler_rt.dylib \
+	$(call GetCNAVar,STRIP,Platform.darwin_bni,Release,) -S $(SYMROOT)/libcompiler_rt.dylib \
 	    -o $(DSTROOT)/usr/lib/system/libcompiler_rt.dylib
 	cd $(DSTROOT)/usr/lib/system; \
 	    ln -s libcompiler_rt.dylib libcompiler_rt_profile.dylib; \
@@ -58,16 +53,17 @@
 # Rule to make each dylib slice
 $(OBJROOT)/libcompiler_rt-%.dylib : $(OBJROOT)/darwin_bni/Release/%/libcompiler_rt.a
 	echo "const char vers[] = \"@(#) $(RC_ProjectName)-$(RC_ProjectSourceVersion)\"; " > $(OBJROOT)/version.c
-	$(CC.Release) $(OBJROOT)/version.c -arch $* -dynamiclib \
+	$(call GetCNAVar,CC,Platform.darwin_bni,Release,$*) \
+	   $(OBJROOT)/version.c -arch $* -dynamiclib \
 	   -install_name /usr/lib/system/libcompiler_rt.dylib \
 	   -compatibility_version 1 -current_version $(RC_ProjectSourceVersion) \
 	   -nodefaultlibs -lSystem -umbrella System -dead_strip \
-	   $(LD_OTHER_FLAGS) -Wl,-force_load,$^ -o $@ 
+	   $(DYLIB_FLAGS) -Wl,-force_load,$^ -o $@ 
 
 # Rule to make fat dylib
 $(SYMROOT)/libcompiler_rt.dylib: $(foreach arch,$(RC_ARCHS), \
                                         $(OBJROOT)/libcompiler_rt-$(arch).dylib)
-	lipo -create $^ -o  $@
+	$(call GetCNAVar,LIPO,Platform.darwin_bni,Release,) -create $^ -o  $@
 
 
 
@@ -83,25 +79,27 @@
 	cp $(SYMROOT)/libcompiler_rt-dyld.a  \
 				    $(DSTROOT)/usr/local/lib/dyld/libcompiler_rt.a
 	mkdir -p $(DSTROOT)/usr/lib/system
-	strip -S $(SYMROOT)/libcompiler_rt.dylib \
+	$(call GetCNAVar,STRIP,Platform.darwin_bni,Release,) -S $(SYMROOT)/libcompiler_rt.dylib \
 	    -o $(DSTROOT)/usr/lib/system/libcompiler_rt.dylib
 
 	
 # Rule to make fat archive
 $(SYMROOT)/libcompiler_rt-static.a : $(foreach arch,$(RC_ARCHS), \
                          $(OBJROOT)/darwin_bni/Static/$(arch)/libcompiler_rt.a)
-	lipo -create $^ -o  $@
+	$(call GetCNAVar,LIPO,Platform.darwin_bni,Release,) -create $^ -o  $@
 
-# rule to make each archive slice for dyld
+# rule to make each archive slice for dyld (which removes a few archive members)
 $(OBJROOT)/libcompiler_rt-dyld-%.a : $(OBJROOT)/darwin_bni/Release/%/libcompiler_rt.a
 	cp $^ $@
-	ar -d $@ apple_versioning.o
-	ar -d $@ gcc_personality_v0.o
-	ar -d $@ eprintf.o
-	ranlib $@
+	DEL_LIST=`$(AR)  -t $@ | egrep 'apple_versioning|gcc_personality_v0|eprintf' | xargs echo` ; \
+	if [ -n "$${DEL_LIST}" ] ; \
+	then  \
+		$(call GetCNAVar,AR,Platform.darwin_bni,Release,) -d $@ $${DEL_LIST}; \
+		$(call GetCNAVar,RANLIB,Platform.darwin_bni,Release,) $@ ; \
+	fi
 
 # rule to make make archive for dyld
 $(SYMROOT)/libcompiler_rt-dyld.a : $(foreach arch,$(RC_ARCHS), \
                          $(OBJROOT)/libcompiler_rt-dyld-$(arch).a)
-	lipo -create $^ -o  $@
+	$(call GetCNAVar,LIPO,Platform.darwin_bni,Release,) -create $^ -o  $@
 

Modified: compiler-rt/trunk/make/platform/darwin_bni.mk
URL: http://llvm.org/viewvc/llvm-project/compiler-rt/trunk/make/platform/darwin_bni.mk?rev=133487&r1=133486&r2=133487&view=diff
==============================================================================
--- compiler-rt/trunk/make/platform/darwin_bni.mk (original)
+++ compiler-rt/trunk/make/platform/darwin_bni.mk Mon Jun 20 19:07:55 2011
@@ -8,17 +8,30 @@
 # and the resulting lib will just have generic versions for anything unknown.
 UniversalArchs := $(RC_ARCHS)
 
-ifeq (,$(SDKROOT))
-	CC.Release := $(CC)
-	CC.Static  := $(CC)
+ifneq (,$(SDKROOT))
+	override CC := $(shell xcrun -sdk $(SDKROOT) -find clang) 
+	AR := $(shell xcrun -sdk $(SDKROOT) -find ar) 
+	RANLIB := $(shell xcrun -sdk $(SDKROOT) -find ranlib) 
+	STRIP := $(shell xcrun -sdk $(SDKROOT) -find strip) 
+	LIPO := $(shell xcrun -sdk $(SDKROOT) -find lipo)
+endif
+
+ifneq ($(IPHONEOS_DEPLOYMENT_TARGET),)
+	DEPLOYMENT_FLAGS := -miphoneos-version-min=$(IPHONEOS_DEPLOYMENT_TARGET) 
 else
-	CC.Release := /Developer/Platforms/iPhoneOS.platform/Developer/usr/bin/cc
-	CC.Static  := /Developer/Platforms/iPhoneOS.platform/Developer/usr/bin/cc
+	ifneq ($(MACOSX_DEPLOYMENT_TARGET),)
+		DEPLOYMENT_FLAGS := -mmacosx-version-min=$(MACOSX_DEPLOYMENT_TARGET) 
+	endif
 endif
 
+ifneq (,$(SDKROOT))
+	DEPLOYMENT_FLAGS += -isysroot $(SDKROOT)
+endif
 
-CFLAGS := -Wall -Os -fomit-frame-pointer -g
-CFLAGS.Static := $(CFLAGS) -static
+CFLAGS := -Wall -Os -fomit-frame-pointer -g $(DEPLOYMENT_FLAGS)
+CFLAGS.Static := $(CFLAGS) -static  
+DYLIB_FLAGS := $(DEPLOYMENT_FLAGS) \
+		-Xarch_arm -Wl,-alias_list,$(SRCROOT)/lib/arm/softfloat-alias.list
 
 VISIBILITY_HIDDEN := 0
 VISIBILITY_HIDDEN.Static  := 1



From isanbard at gmail.com  Mon Jun 20 19:35:15 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 21 Jun 2011 00:35:15 -0000
Subject: [llvm-commits] [llvm] r133493 -
	/llvm/trunk/include/llvm/Intrinsics.td
Message-ID: <20110621003515.8595E2A6C12C@llvm.org>

Author: void
Date: Mon Jun 20 19:35:15 2011
New Revision: 133493

URL: http://llvm.org/viewvc/llvm-project?rev=133493&view=rev
Log:
Don't mark the eh.dispatch.setup with a memory access marker. We want this to
stick around even during fast isel.
<rdar://problem/9637156>

Modified:
    llvm/trunk/include/llvm/Intrinsics.td

Modified: llvm/trunk/include/llvm/Intrinsics.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Intrinsics.td?rev=133493&r1=133492&r2=133493&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Intrinsics.td (original)
+++ llvm/trunk/include/llvm/Intrinsics.td Mon Jun 20 19:35:15 2011
@@ -312,7 +312,7 @@
   def int_eh_sjlj_lsda    : Intrinsic<[llvm_ptr_ty]>;
   def int_eh_sjlj_callsite: Intrinsic<[], [llvm_i32_ty]>;
 }
-def int_eh_sjlj_dispatch_setup : Intrinsic<[], [llvm_i32_ty], [IntrReadMem]>;
+def int_eh_sjlj_dispatch_setup : Intrinsic<[], [llvm_i32_ty]>;
 def int_eh_sjlj_setjmp  : Intrinsic<[llvm_i32_ty], [llvm_ptr_ty]>;
 def int_eh_sjlj_longjmp : Intrinsic<[], [llvm_ptr_ty]>;
 



From ahatanak at gmail.com  Mon Jun 20 19:40:49 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Tue, 21 Jun 2011 00:40:49 -0000
Subject: [llvm-commits] [llvm] r133494 - in /llvm/trunk:
 lib/Target/Mips/MipsAsmPrinter.cpp lib/Target/Mips/MipsISelDAGToDAG.cpp
 lib/Target/Mips/MipsISelLowering.cpp lib/Target/Mips/MipsISelLowering.h
 lib/Target/Mips/MipsInstrInfo.td lib/Target/Mips/MipsMachineFunction.h
 lib/Target/Mips/MipsRegisterInfo.cpp test/CodeGen/Mips/alloca.ll
 test/CodeGen/Mips/inlineasmmemop.ll
Message-ID: <20110621004049.779FE2A6C12D@llvm.org>

Author: ahatanak
Date: Mon Jun 20 19:40:49 2011
New Revision: 133494

URL: http://llvm.org/viewvc/llvm-project?rev=133494&view=rev
Log:
Re-apply 132758 and 132768 which were speculatively reverted in 132777. 

Added:
    llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
Modified:
    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/lib/Target/Mips/MipsISelLowering.h
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
    llvm/trunk/lib/Target/Mips/MipsMachineFunction.h
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
    llvm/trunk/test/CodeGen/Mips/alloca.ll

Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=133494&r1=133493&r2=133494&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Mon Jun 20 19:40:49 2011
@@ -56,6 +56,9 @@
     bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
                          unsigned AsmVariant, const char *ExtraCode,
                          raw_ostream &O);
+    bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
+                               unsigned AsmVariant, const char *ExtraCode,
+                               raw_ostream &O);
     void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
     void printUnsignedImm(const MachineInstr *MI, int opNum, raw_ostream &O);
     void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
@@ -304,6 +307,19 @@
   return false;
 }
 
+bool MipsAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
+                                           unsigned OpNum, unsigned AsmVariant,
+                                           const char *ExtraCode,
+                                           raw_ostream &O) {
+  if (ExtraCode && ExtraCode[0])
+     return true; // Unknown modifier.
+   
+  const MachineOperand &MO = MI->getOperand(OpNum);
+  assert(MO.isReg() && "unexpected inline asm memory operand");
+  O << "0($" << MipsAsmPrinter::getRegisterName(MO.getReg()) << ")";
+  return false;
+}
+
 void MipsAsmPrinter::printOperand(const MachineInstr *MI, int opNum,
                                   raw_ostream &O) {
   const MachineOperand &MO = MI->getOperand(opNum);

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=133494&r1=133493&r2=133494&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Mon Jun 20 19:40:49 2011
@@ -94,6 +94,10 @@
   inline SDValue getI32Imm(unsigned Imm) {
     return CurDAG->getTargetConstant(Imm, MVT::i32);
   }
+
+  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                            char ConstraintCode,
+                                            std::vector<SDValue> &OutOps);
 };
 
 }
@@ -462,6 +466,14 @@
   return ResNode;
 }
 
+bool MipsDAGToDAGISel::
+SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
+                             std::vector<SDValue> &OutOps) {
+  assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
+  OutOps.push_back(Op);
+  return false;
+}
+
 /// createMipsISelDag - This pass converts a legalized DAG into a
 /// MIPS-specific DAG, ready for instruction scheduling.
 FunctionPass *llvm::createMipsISelDag(MipsTargetMachine &TM) {

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=133494&r1=133493&r2=133494&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Jun 20 19:40:49 2011
@@ -59,6 +59,7 @@
   case MipsISD::BuildPairF64:      return "MipsISD::BuildPairF64";
   case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64";
   case MipsISD::WrapperPIC:        return "MipsISD::WrapperPIC";
+  case MipsISD::DynAlloc:          return "MipsISD::DynAlloc";
   default:                         return NULL;
   }
 }
@@ -1189,9 +1190,10 @@
 SDValue MipsTargetLowering::
 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
 {
-  unsigned StackAlignment =
-    getTargetMachine().getFrameLowering()->getStackAlignment();
-  assert(StackAlignment >=
+  MachineFunction &MF = DAG.getMachineFunction();
+  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
+
+  assert(getTargetMachine().getFrameLowering()->getStackAlignment() >=
          cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() &&
          "Cannot lower if the alignment of the allocated space is larger than \
           that of the stack.");
@@ -1211,24 +1213,14 @@
   // must be placed in the stack pointer register.
   Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub,
                            SDValue());
-  // Retrieve updated $sp. There is a glue input to prevent instructions that
-  // clobber $sp from being inserted between copytoreg and copyfromreg.
-  SDValue NewSP = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32,
-                                     Chain.getValue(1));
-
-  // The stack space reserved by alloca is located right above the argument
-  // area. It is aligned on a boundary that is a multiple of StackAlignment.
-  MachineFunction &MF = DAG.getMachineFunction();
-  MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
-  unsigned SPOffset = (MipsFI->getMaxCallFrameSize() + StackAlignment - 1) /
-                      StackAlignment * StackAlignment;
-  SDValue AllocPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, NewSP,
-                                 DAG.getConstant(SPOffset, MVT::i32));
 
   // This node always has two return values: a new stack pointer
   // value and a chain
-  SDValue Ops[2] = { AllocPtr, NewSP.getValue(1) };
-  return DAG.getMergeValues(Ops, 2, dl);
+  SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other);
+  SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy());
+  SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) };
+
+  return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3);
 }
 
 SDValue MipsTargetLowering::
@@ -1770,6 +1762,10 @@
   if (IsPIC && !MipsFI->getGPFI())
     MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true));
 
+  // Get the frame index of the stack frame object that points to the location
+  // of dynamically allocated area on the stack.
+  int DynAllocFI = MipsFI->getDynAllocFI();
+
   // Update size of the maximum argument space.
   // For O32, a minimum of four words (16 bytes) of argument space is
   // allocated.
@@ -1781,14 +1777,17 @@
   if (MaxCallFrameSize < NextStackOffset) {
     MipsFI->setMaxCallFrameSize(NextStackOffset);
 
-    if (IsPIC) {
-      // $gp restore slot must be aligned.
-      unsigned StackAlignment = TFL->getStackAlignment();
-      NextStackOffset = (NextStackOffset + StackAlignment - 1) /
-                        StackAlignment * StackAlignment;
-      int GPFI = MipsFI->getGPFI();
-      MFI->setObjectOffset(GPFI, NextStackOffset);
-    }
+    // Set the offsets relative to $sp of the $gp restore slot and dynamically
+    // allocated stack space. These offsets must be aligned to a boundary
+    // determined by the stack alignment of the ABI.
+    unsigned StackAlignment = TFL->getStackAlignment();
+    NextStackOffset = (NextStackOffset + StackAlignment - 1) /
+                      StackAlignment * StackAlignment;
+
+    if (IsPIC)
+      MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset);
+
+    MFI->setObjectOffset(DynAllocFI, NextStackOffset);
   }
 
   // With EABI is it possible to have 16 args on registers.

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=133494&r1=133493&r2=133494&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Mon Jun 20 19:40:49 2011
@@ -79,7 +79,9 @@
       BuildPairF64,
       ExtractElementF64,
 
-      WrapperPIC
+      WrapperPIC,
+
+      DynAlloc
     };
   }
 

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.td?rev=133494&r1=133493&r2=133494&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td Mon Jun 20 19:40:49 2011
@@ -39,6 +39,9 @@
 
 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
 
+def SDT_MipsDynAlloc    : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
+                                               SDTCisVT<1, iPTR>]>;
+
 // Call
 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
                          [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
@@ -99,6 +102,10 @@
 
 def MipsWrapperPIC    : SDNode<"MipsISD::WrapperPIC",  SDTIntUnaryOp>;
 
+// Pointer to dynamically allocated stack area.
+def MipsDynAlloc  : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
+                           [SDNPHasChain, SDNPInGlue]>;
+
 //===----------------------------------------------------------------------===//
 // Mips Instruction Predicate Definitions.
 //===----------------------------------------------------------------------===//
@@ -675,6 +682,12 @@
 // can be matched. It's similar to Sparc LEA_ADDRi
 def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
 
+// DynAlloc node points to dynamically allocated stack space.
+// $sp is added to the list of implicitly used registers to prevent dead code
+// elimination from removing instructions that modify $sp.
+let Uses = [SP] in
+def DynAlloc : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
+
 // MADD*/MSUB*
 def MADD  : MArithR<0, "madd", MipsMAdd, 1>;
 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
@@ -852,6 +865,9 @@
 def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
           (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
 
+// select MipsDynAlloc
+def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
+
 //===----------------------------------------------------------------------===//
 // Floating Point Support
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/Mips/MipsMachineFunction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMachineFunction.h?rev=133494&r1=133493&r2=133494&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMachineFunction.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMachineFunction.h Mon Jun 20 19:40:49 2011
@@ -27,6 +27,7 @@
 class MipsFunctionInfo : public MachineFunctionInfo {
 
 private:
+  MachineFunction& MF;
   /// SRetReturnReg - Some subtargets require that sret lowering includes
   /// returning the value of the returned struct in a register. This field
   /// holds the virtual register into which the sret argument is passed.
@@ -47,6 +48,7 @@
   //                LowerCall except for the frame object for restoring $gp. 
   std::pair<int, int> InArgFIRange, OutArgFIRange;
   int GPFI; // Index of the frame object for restoring $gp 
+  mutable int DynAllocFI; // Frame index of dynamically allocated stack area.   
   unsigned MaxCallFrameSize;
 
   /// AtomicFrameIndex - To implement atomic.swap and atomic.cmp.swap
@@ -55,10 +57,10 @@
   int AtomicFrameIndex;
 public:
   MipsFunctionInfo(MachineFunction& MF)
-  : SRetReturnReg(0), GlobalBaseReg(0),
+  : MF(MF), SRetReturnReg(0), GlobalBaseReg(0),
     VarArgsFrameIndex(0), InArgFIRange(std::make_pair(-1, 0)),
-    OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), MaxCallFrameSize(0),
-    AtomicFrameIndex(-1)
+    OutArgFIRange(std::make_pair(-1, 0)), GPFI(0), DynAllocFI(0),
+    MaxCallFrameSize(0), AtomicFrameIndex(-1)
   {}
 
   bool isInArgFI(int FI) const {
@@ -81,6 +83,16 @@
   bool needGPSaveRestore() const { return getGPFI(); }
   bool isGPFI(int FI) const { return GPFI && GPFI == FI; }
 
+  // The first call to this function creates a frame object for dynamically
+  // allocated stack area.
+  int getDynAllocFI() const {
+    if (!DynAllocFI)
+      DynAllocFI = MF.getFrameInfo()->CreateFixedObject(4, 0, true);
+
+    return DynAllocFI;
+  }
+  bool isDynAllocFI(int FI) const { return DynAllocFI && DynAllocFI == FI; }
+
   unsigned getSRetReturnReg() const { return SRetReturnReg; }
   void setSRetReturnReg(unsigned Reg) { SRetReturnReg = Reg; }
 

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=133494&r1=133493&r2=133494&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon Jun 20 19:40:49 2011
@@ -179,12 +179,14 @@
   int Offset;
 
   // Calculate final offset.
-  // - There is no need to change the offset if the frame object is an outgoing
-  //   argument or a $gp restore location,
+  // - There is no need to change the offset if the frame object is one of the
+  //   following: an outgoing argument, pointer to a dynamically allocated
+  //   stack space or a $gp restore location,
   // - If the frame object is any of the following, its offset must be adjusted
   //   by adding the size of the stack:
   //   incoming argument, callee-saved register location or local variable.  
-  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex))
+  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
+      MipsFI->isDynAllocFI(FrameIndex))
     Offset = spOffset;
   else
     Offset = spOffset + stackSize;
@@ -213,7 +215,7 @@
   //  3. Locations for callee-saved registers.
   // Everything else is referenced relative to whatever register 
   // getFrameRegister() returns.
-  if (MipsFI->isOutArgFI(FrameIndex) ||
+  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
       (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
     FrameReg = Mips::SP;
   else

Modified: llvm/trunk/test/CodeGen/Mips/alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/alloca.ll?rev=133494&r1=133493&r2=133494&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/alloca.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/alloca.ll Mon Jun 20 19:40:49 2011
@@ -4,15 +4,15 @@
 entry:
 ; CHECK: subu  $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
 ; CHECK: addu  $sp, $zero, $[[T0]]
-; CHECK: addu  $[[SP1:[0-9]+]], $zero, $sp
-; CHECK: subu  $[[T1:[0-9]+]], $sp, $[[SZ]]
-; CHECK: addu  $sp, $zero, $[[T1]]
-; CHECK: addu  $[[SP2:[0-9]+]], $zero, $sp
+; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF:[0-9]+]]
+; CHECK: subu  $[[T2:[0-9]+]], $sp, $[[SZ]]
+; CHECK: addu  $sp, $zero, $[[T2]]
+; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]]
 ; CHECK: lw  $25, %call16(foo)($gp)
-; CHECK: addiu $4, $[[SP1]], 24
+; CHECK: addu $4, $zero, $[[T1]]
 ; CHECK: jalr  $25
 ; CHECK: lw  $25, %call16(foo)($gp)
-; CHECK: addiu $4, $[[SP2]], 24
+; CHECK: addu $4, $zero, $[[T3]]
 ; CHECK: jalr  $25
   %tmp1 = alloca i8, i32 %size, align 4
   %add.ptr = getelementptr inbounds i8* %tmp1, i32 5
@@ -29,3 +29,72 @@
 
 declare i32 @foo(i8*)
 
+ at .str = private unnamed_addr constant [22 x i8] c"%d %d %d %d %d %d %d\0A\00", align 1
+
+define i32 @alloca2(i32 %size) nounwind {
+entry:
+; dynamic allocated stack area and $gp restore slot have the same offsets
+; relative to $sp.
+;
+; CHECK: alloca2
+; CHECK: .cprestore [[OFF:[0-9]+]]
+; CHECK: subu  $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
+; CHECK: addu  $sp, $zero, $[[T0]]
+; CHECK: addiu $[[T1:[0-9]+]], $sp, [[OFF]]
+
+  %tmp1 = alloca i8, i32 %size, align 4
+  %0 = bitcast i8* %tmp1 to i32*
+  %cmp = icmp sgt i32 %size, 10
+  br i1 %cmp, label %if.then, label %if.else
+
+if.then:                                          ; preds = %entry
+; CHECK: addiu $4, $[[T1]], 40
+
+  %add.ptr = getelementptr inbounds i8* %tmp1, i32 40
+  %1 = bitcast i8* %add.ptr to i32*
+  call void @foo3(i32* %1) nounwind
+  %arrayidx15.pre = getelementptr inbounds i8* %tmp1, i32 12
+  %.pre = bitcast i8* %arrayidx15.pre to i32*
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+; CHECK: addiu $4, $[[T1]], 12
+
+  %add.ptr5 = getelementptr inbounds i8* %tmp1, i32 12
+  %2 = bitcast i8* %add.ptr5 to i32*
+  call void @foo3(i32* %2) nounwind
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+; CHECK: lw  $5, 0($[[T1]])
+; CHECK: lw  $25, %call16(printf)
+
+  %.pre-phi = phi i32* [ %2, %if.else ], [ %.pre, %if.then ]
+  %tmp7 = load i32* %0, align 4, !tbaa !0
+  %arrayidx9 = getelementptr inbounds i8* %tmp1, i32 4
+  %3 = bitcast i8* %arrayidx9 to i32*
+  %tmp10 = load i32* %3, align 4, !tbaa !0
+  %arrayidx12 = getelementptr inbounds i8* %tmp1, i32 8
+  %4 = bitcast i8* %arrayidx12 to i32*
+  %tmp13 = load i32* %4, align 4, !tbaa !0
+  %tmp16 = load i32* %.pre-phi, align 4, !tbaa !0
+  %arrayidx18 = getelementptr inbounds i8* %tmp1, i32 16
+  %5 = bitcast i8* %arrayidx18 to i32*
+  %tmp19 = load i32* %5, align 4, !tbaa !0
+  %arrayidx21 = getelementptr inbounds i8* %tmp1, i32 20
+  %6 = bitcast i8* %arrayidx21 to i32*
+  %tmp22 = load i32* %6, align 4, !tbaa !0
+  %arrayidx24 = getelementptr inbounds i8* %tmp1, i32 24
+  %7 = bitcast i8* %arrayidx24 to i32*
+  %tmp25 = load i32* %7, align 4, !tbaa !0
+  %call = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([22 x i8]* @.str, i32 0, i32 0), i32 %tmp7, i32 %tmp10, i32 %tmp13, i32 %tmp16, i32 %tmp19, i32 %tmp22, i32 %tmp25) nounwind
+  ret i32 0
+}
+
+declare void @foo3(i32*)
+
+declare i32 @printf(i8* nocapture, ...) nounwind
+
+!0 = metadata !{metadata !"int", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}

Added: llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll?rev=133494&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll (added)
+++ llvm/trunk/test/CodeGen/Mips/inlineasmmemop.ll Mon Jun 20 19:40:49 2011
@@ -0,0 +1,23 @@
+; RUN: llc -march=mipsel -mcpu=4ke < %s | FileCheck %s
+
+ at g1 = external global i32
+
+define i32 @f1(i32 %x) nounwind {
+entry:
+; CHECK: addiu $[[T0:[0-9]+]], $sp
+; CHECK: #APP
+; CHECK: sw $4, 0($[[T0]])
+; CHECK: #NO_APP
+; CHECK: lw  $[[T1:[0-9]+]], %got(g1)($gp)
+; CHECK: #APP
+; CHECK: lw $[[T3:[0-9]+]], 0($[[T0]])
+; CHECK: #NO_APP
+; CHECK: sw  $[[T3]], 0($[[T1]])
+
+  %l1 = alloca i32, align 4
+  call void asm "sw $1, $0", "=*m,r"(i32* %l1, i32 %x) nounwind
+  %0 = call i32 asm "lw $0, $1", "=r,*m"(i32* %l1) nounwind
+  store i32 %0, i32* @g1, align 4
+  ret i32 %0
+}
+



From ahatanak at gmail.com  Mon Jun 20 20:02:03 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Tue, 21 Jun 2011 01:02:03 -0000
Subject: [llvm-commits] [llvm] r133496 -
	/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
Message-ID: <20110621010203.65FFC2A6C12C@llvm.org>

Author: ahatanak
Date: Mon Jun 20 20:02:03 2011
New Revision: 133496

URL: http://llvm.org/viewvc/llvm-project?rev=133496&view=rev
Log:
Coding style fixes.

Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=133496&r1=133495&r2=133496&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Mon Jun 20 20:02:03 2011
@@ -1350,7 +1350,7 @@
   if (getTargetMachine().getRelocationModel() == Reloc::PIC_) {
     // General Dynamic TLS Model
     SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32,
-                                                 0, MipsII::MO_TLSGD);
+                                             0, MipsII::MO_TLSGD);
     SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA);
     SDValue GP = DAG.getRegister(Mips::GP, MVT::i32);
     SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd);
@@ -1362,36 +1362,36 @@
     Args.push_back(Entry);
     std::pair<SDValue, SDValue> CallResult =
         LowerCallTo(DAG.getEntryNode(),
-                 (const Type *) Type::getInt32Ty(*DAG.getContext()),
-                 false, false, false, false,
-                 0, CallingConv::C, false, true,
-                 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
+                    (const Type *) Type::getInt32Ty(*DAG.getContext()),
+                    false, false, false, false, 0, CallingConv::C, false, true,
+                    DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG,
+                    dl);
 
     return CallResult.first;
-  } else {
-    SDValue Offset;
-    if (GV->isDeclaration()) {
-      // Initial Exec TLS Model
-      SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
-                                              MipsII::MO_GOTTPREL);
-      Offset = DAG.getLoad(MVT::i32, dl,
-                                  DAG.getEntryNode(), TGA, MachinePointerInfo(),
-                                  false, false, 0);
-    } else {
-      // Local Exec TLS Model
-      SDVTList VTs = DAG.getVTList(MVT::i32);
-      SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
-                                              MipsII::MO_TPREL_HI);
-      SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
-                                              MipsII::MO_TPREL_LO);
-      SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1);
-      SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo);
-      Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
-    }
+  }
 
-    SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
-    return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
+  SDValue Offset;
+  if (GV->isDeclaration()) {
+    // Initial Exec TLS Model
+    SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
+                                             MipsII::MO_GOTTPREL);
+    Offset = DAG.getLoad(MVT::i32, dl,
+                         DAG.getEntryNode(), TGA, MachinePointerInfo(),
+                         false, false, 0);
+  } else {
+    // Local Exec TLS Model
+    SDVTList VTs = DAG.getVTList(MVT::i32);
+    SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
+                                               MipsII::MO_TPREL_HI);
+    SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
+                                               MipsII::MO_TPREL_LO);
+    SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1);
+    SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo);
+    Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo);
   }
+
+  SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT);
+  return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset);
 }
 
 SDValue MipsTargetLowering::
@@ -1964,7 +1964,8 @@
   InFlag = Chain.getValue(1);
 
   // Create the CALLSEQ_END node.
-  Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NextStackOffset, true),
+  Chain = DAG.getCALLSEQ_END(Chain,
+                             DAG.getIntPtrConstant(NextStackOffset, true),
                              DAG.getIntPtrConstant(0, true), InFlag);
   InFlag = Chain.getValue(1);
 



From ahatanak at gmail.com  Mon Jun 20 20:28:11 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Tue, 21 Jun 2011 01:28:11 -0000
Subject: [llvm-commits] [llvm] r133497 -
	/llvm/trunk/lib/Target/Mips/MipsCallingConv.td
Message-ID: <20110621012811.D62702A6C12C@llvm.org>

Author: ahatanak
Date: Mon Jun 20 20:28:11 2011
New Revision: 133497

URL: http://llvm.org/viewvc/llvm-project?rev=133497&view=rev
Log:
Add A0 and A1 to the list of registers used for returning a value in order to
handle functions with return type Complex long long.


Modified:
    llvm/trunk/lib/Target/Mips/MipsCallingConv.td

Modified: llvm/trunk/lib/Target/Mips/MipsCallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsCallingConv.td?rev=133497&r1=133496&r2=133497&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsCallingConv.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsCallingConv.td Mon Jun 20 20:28:11 2011
@@ -20,8 +20,8 @@
 // Only the return rules are defined here for O32. The rules for argument
 // passing are defined in MipsISelLowering.cpp.
 def RetCC_MipsO32 : CallingConv<[
-  // i32 are returned in registers V0, V1
-  CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
+  // i32 are returned in registers V0, V1, A0, A1
+  CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
 
   // f32 are returned in registers F0, F2
   CCIfType<[f32], CCAssignToReg<[F0, F2]>>,



From mcrosier at apple.com  Mon Jun 20 21:09:04 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Tue, 21 Jun 2011 02:09:04 -0000
Subject: [llvm-commits] [llvm] r133499 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/Target/CppBackend/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
Message-ID: <20110621020904.4CFD62A6C12C@llvm.org>

Author: mcrosier
Date: Mon Jun 20 21:09:03 2011
New Revision: 133499

URL: http://llvm.org/viewvc/llvm-project?rev=133499&view=rev
Log:
Revert r133435 and r133449 to appease buildbots.

Modified:
    llvm/trunk/include/llvm/BasicBlock.h
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/CFG.h
    llvm/trunk/include/llvm/Use.h
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
    llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
    llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp
    llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
    llvm/trunk/lib/Transforms/Utils/Local.cpp
    llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
    llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
    llvm/trunk/lib/VMCore/BasicBlock.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp
    llvm/trunk/lib/VMCore/User.cpp
    llvm/trunk/lib/VMCore/Value.cpp
    llvm/trunk/lib/VMCore/Verifier.cpp

Modified: llvm/trunk/include/llvm/BasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BasicBlock.h?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/include/llvm/BasicBlock.h (original)
+++ llvm/trunk/include/llvm/BasicBlock.h Mon Jun 20 21:09:03 2011
@@ -110,7 +110,7 @@
         Function *getParent()       { return Parent; }
 
   /// use_back - Specialize the methods defined in Value, as we know that an
-  /// BasicBlock can only be used by Users (specifically terminators
+  /// BasicBlock can only be used by Users (specifically PHI nodes, terminators,
   /// and BlockAddress's).
   User       *use_back()       { return cast<User>(*use_begin());}
   const User *use_back() const { return cast<User>(*use_begin());}
@@ -248,10 +248,6 @@
   /// other than direct branches, switches, etc. to it.
   bool hasAddressTaken() const { return getSubclassDataFromValue() != 0; }
 
-  /// replaceSuccessorsPhiUsesWith - Update all phi nodes in all our successors
-  /// to refer to basic block New instead of to us.
-  void replaceSuccessorsPhiUsesWith(BasicBlock *New);
-
 private:
   /// AdjustBlockAddressRefCount - BasicBlock stores the number of BlockAddress
   /// objects using it.  This is almost always 0, sometimes one, possibly but

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Mon Jun 20 21:09:03 2011
@@ -1814,7 +1814,7 @@
   explicit PHINode(const Type *Ty, unsigned NumReservedValues,
                    const Twine &NameStr = "", Instruction *InsertBefore = 0)
     : Instruction(Ty, Instruction::PHI, 0, 0, InsertBefore),
-      ReservedSpace(NumReservedValues) {
+      ReservedSpace(NumReservedValues * 2) {
     setName(NameStr);
     OperandList = allocHungoffUses(ReservedSpace);
   }
@@ -1822,16 +1822,11 @@
   PHINode(const Type *Ty, unsigned NumReservedValues, const Twine &NameStr,
           BasicBlock *InsertAtEnd)
     : Instruction(Ty, Instruction::PHI, 0, 0, InsertAtEnd),
-      ReservedSpace(NumReservedValues) {
+      ReservedSpace(NumReservedValues * 2) {
     setName(NameStr);
     OperandList = allocHungoffUses(ReservedSpace);
   }
 protected:
-  // allocHungoffUses - this is more complicated than the generic
-  // User::allocHungoffUses, because we have to allocate Uses for the incoming
-  // values and pointers to the incoming blocks, all in one allocation.
-  Use *allocHungoffUses(unsigned) const;
-
   virtual PHINode *clone_impl() const;
 public:
   /// Constructors - NumReservedValues is a hint for the number of incoming
@@ -1850,55 +1845,32 @@
   /// Provide fast operand accessors
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
 
-  // Block iterator interface. This provides access to the list of incoming
-  // basic blocks, which parallels the list of incoming values.
-
-  typedef BasicBlock **block_iterator;
-  typedef BasicBlock * const *const_block_iterator;
-
-  block_iterator block_begin() {
-    Use::UserRef *ref =
-      reinterpret_cast<Use::UserRef*>(op_begin() + ReservedSpace);
-    return reinterpret_cast<block_iterator>(ref + 1);
-  }
-
-  const_block_iterator block_begin() const {
-    const Use::UserRef *ref =
-      reinterpret_cast<const Use::UserRef*>(op_begin() + ReservedSpace);
-    return reinterpret_cast<const_block_iterator>(ref + 1);
-  }
-
-  block_iterator block_end() {
-    return block_begin() + getNumOperands();
-  }
-
-  const_block_iterator block_end() const {
-    return block_begin() + getNumOperands();
-  }
-
   /// getNumIncomingValues - Return the number of incoming edges
   ///
-  unsigned getNumIncomingValues() const { return getNumOperands(); }
+  unsigned getNumIncomingValues() const { return getNumOperands()/2; }
 
   /// getIncomingValue - Return incoming value number x
   ///
   Value *getIncomingValue(unsigned i) const {
-    return getOperand(i);
+    assert(i*2 < getNumOperands() && "Invalid value number!");
+    return getOperand(i*2);
   }
   void setIncomingValue(unsigned i, Value *V) {
-    setOperand(i, V);
+    assert(i*2 < getNumOperands() && "Invalid value number!");
+    setOperand(i*2, V);
   }
   static unsigned getOperandNumForIncomingValue(unsigned i) {
-    return i;
+    return i*2;
   }
   static unsigned getIncomingValueNumForOperand(unsigned i) {
-    return i;
+    assert(i % 2 == 0 && "Invalid incoming-value operand index!");
+    return i/2;
   }
 
   /// getIncomingBlock - Return incoming basic block number @p i.
   ///
   BasicBlock *getIncomingBlock(unsigned i) const {
-    return block_begin()[i];
+    return cast<BasicBlock>(getOperand(i*2+1));
   }
 
   /// getIncomingBlock - Return incoming basic block corresponding
@@ -1906,7 +1878,7 @@
   ///
   BasicBlock *getIncomingBlock(const Use &U) const {
     assert(this == U.getUser() && "Iterator doesn't point to PHI's Uses?");
-    return getIncomingBlock(&U - op_begin());
+    return cast<BasicBlock>((&U + 1)->get());
   }
 
   /// getIncomingBlock - Return incoming basic block corresponding
@@ -1917,8 +1889,16 @@
     return getIncomingBlock(I.getUse());
   }
 
+
   void setIncomingBlock(unsigned i, BasicBlock *BB) {
-    block_begin()[i] = BB;
+    setOperand(i*2+1, (Value*)BB);
+  }
+  static unsigned getOperandNumForIncomingBlock(unsigned i) {
+    return i*2+1;
+  }
+  static unsigned getIncomingBlockNumForOperand(unsigned i) {
+    assert(i % 2 == 1 && "Invalid incoming-block operand index!");
+    return i/2;
   }
 
   /// addIncoming - Add an incoming value to the end of the PHI list
@@ -1928,12 +1908,13 @@
     assert(BB && "PHI node got a null basic block!");
     assert(getType() == V->getType() &&
            "All operands to PHI node must be the same type as the PHI node!");
-    if (NumOperands == ReservedSpace)
+    unsigned OpNo = NumOperands;
+    if (OpNo+2 > ReservedSpace)
       growOperands();  // Get more space!
     // Initialize some new operands.
-    ++NumOperands;
-    setIncomingValue(NumOperands - 1, V);
-    setIncomingBlock(NumOperands - 1, BB);
+    NumOperands = OpNo+2;
+    OperandList[OpNo] = V;
+    OperandList[OpNo+1] = (Value*)BB;
   }
 
   /// removeIncomingValue - Remove an incoming value.  This is useful if a
@@ -1956,16 +1937,14 @@
   /// block in the value list for this PHI.  Returns -1 if no instance.
   ///
   int getBasicBlockIndex(const BasicBlock *BB) const {
-    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
-      if (block_begin()[i] == BB)
-        return i;
+    Use *OL = OperandList;
+    for (unsigned i = 0, e = getNumOperands(); i != e; i += 2)
+      if (OL[i+1].get() == (const Value*)BB) return i/2;
     return -1;
   }
 
   Value *getIncomingValueForBlock(const BasicBlock *BB) const {
-    int Idx = getBasicBlockIndex(BB);
-    assert(Idx >= 0 && "Invalid basic block argument!");
-    return getIncomingValue(Idx);
+    return getIncomingValue(getBasicBlockIndex(BB));
   }
 
   /// hasConstantValue - If the specified PHI node always merges together the

Modified: llvm/trunk/include/llvm/Support/CFG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CFG.h?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CFG.h (original)
+++ llvm/trunk/include/llvm/Support/CFG.h Mon Jun 20 21:09:03 2011
@@ -33,7 +33,7 @@
   USE_iterator It;
 
   inline void advancePastNonTerminators() {
-    // Loop to ignore non terminator uses (for example BlockAddresses).
+    // Loop to ignore non terminator uses (for example PHI nodes).
     while (!It.atEnd() && !isa<TerminatorInst>(*It))
       ++It;
   }

Modified: llvm/trunk/include/llvm/Use.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Use.h?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Use.h (original)
+++ llvm/trunk/include/llvm/Use.h Mon Jun 20 21:09:03 2011
@@ -112,16 +112,13 @@
   Use *getNext() const { return Next; }
 
   
-  /// initTags - initialize the waymarking tags on an array of Uses, so that
-  /// getUser() can find the User from any of those Uses.
-  static Use *initTags(Use *Start, Use *Stop);
-
   /// zap - This is used to destroy Use operands when the number of operands of
   /// a User changes.
   static void zap(Use *Start, const Use *Stop, bool del = false);
 
 private:
   const Use* getImpliedUser() const;
+  static Use *initTags(Use *Start, Use *Stop);
   
   Value *Val;
   Use *Next;
@@ -143,6 +140,7 @@
   }
 
   friend class Value;
+  friend class User;
 };
 
 // simplify_type - Allow clients to treat uses just like values when using

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Mon Jun 20 21:09:03 2011
@@ -1356,7 +1356,7 @@
     for (unsigned i = 0; i < phi->getNumIncomingValues(); ++i) {
       Out << iName << "->addIncoming("
           << opNames[PHINode::getOperandNumForIncomingValue(i)] << ", "
-          << getOpName(phi->getIncomingBlock(i)) << ");";
+          << opNames[PHINode::getOperandNumForIncomingBlock(i)] << ");";
       nl(Out);
     }
     break;

Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Mon Jun 20 21:09:03 2011
@@ -1021,10 +1021,6 @@
         while (PHINode *PN = dyn_cast<PHINode>(Succ->begin()))
           ReplaceUsesOfWith(PN, PN->getIncomingValue(0), Worklist, L, LPM);
         
-        // If Succ has any successors with PHI nodes, update them to have
-        // entries coming from Pred instead of Succ.
-        Succ->replaceAllUsesWith(Pred);
-        
         // Move all of the successor contents from Succ to Pred.
         Pred->getInstList().splice(BI, Succ->getInstList(), Succ->begin(),
                                    Succ->end());
@@ -1032,6 +1028,10 @@
         BI->eraseFromParent();
         RemoveFromWorklist(BI, Worklist);
         
+        // If Succ has any successors with PHI nodes, update them to have
+        // entries coming from Pred instead of Succ.
+        Succ->replaceAllUsesWith(Pred);
+        
         // Remove Succ from the loop tree.
         LI->removeBlock(Succ);
         LPM->deleteSimpleAnalysisValue(Succ, L);

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Mon Jun 20 21:09:03 2011
@@ -153,13 +153,13 @@
   // Delete the unconditional branch from the predecessor...
   PredBB->getInstList().pop_back();
   
+  // Move all definitions in the successor to the predecessor...
+  PredBB->getInstList().splice(PredBB->end(), BB->getInstList());
+  
   // Make all PHI nodes that referred to BB now refer to Pred as their
   // source...
   BB->replaceAllUsesWith(PredBB);
   
-  // Move all definitions in the successor to the predecessor...
-  PredBB->getInstList().splice(PredBB->end(), BB->getInstList());
-  
   // Inherit predecessors name if it exists.
   if (!PredBB->hasName())
     PredBB->takeName(BB);

Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Mon Jun 20 21:09:03 2011
@@ -193,22 +193,44 @@
   
   // If there are any PHI nodes in DestBB, we need to update them so that they
   // merge incoming values from NewBB instead of from TIBB.
-  {
-    unsigned BBIdx = 0;
-    for (BasicBlock::iterator I = DestBB->begin(); isa<PHINode>(I); ++I) {
-      // We no longer enter through TIBB, now we come in through NewBB.
-      // Revector exactly one entry in the PHI node that used to come from
-      // TIBB to come from NewBB.
-      PHINode *PN = cast<PHINode>(I);
-
-      // Reuse the previous value of BBIdx if it lines up.  In cases where we
-      // have multiple phi nodes with *lots* of predecessors, this is a speed
-      // win because we don't have to scan the PHI looking for TIBB.  This
-      // happens because the BB list of PHI nodes are usually in the same
-      // order.
-      if (PN->getIncomingBlock(BBIdx) != TIBB)
-	BBIdx = PN->getBasicBlockIndex(TIBB);
-      PN->setIncomingBlock(BBIdx, NewBB);
+  if (PHINode *APHI = dyn_cast<PHINode>(DestBB->begin())) {
+    // This conceptually does:
+    //  foreach (PHINode *PN in DestBB)
+    //    PN->setIncomingBlock(PN->getIncomingBlock(TIBB), NewBB);
+    // but is optimized for two cases.
+    
+    if (APHI->getNumIncomingValues() <= 8) {  // Small # preds case.
+      unsigned BBIdx = 0;
+      for (BasicBlock::iterator I = DestBB->begin(); isa<PHINode>(I); ++I) {
+        // We no longer enter through TIBB, now we come in through NewBB.
+        // Revector exactly one entry in the PHI node that used to come from
+        // TIBB to come from NewBB.
+        PHINode *PN = cast<PHINode>(I);
+        
+        // Reuse the previous value of BBIdx if it lines up.  In cases where we
+        // have multiple phi nodes with *lots* of predecessors, this is a speed
+        // win because we don't have to scan the PHI looking for TIBB.  This
+        // happens because the BB list of PHI nodes are usually in the same
+        // order.
+        if (PN->getIncomingBlock(BBIdx) != TIBB)
+          BBIdx = PN->getBasicBlockIndex(TIBB);
+        PN->setIncomingBlock(BBIdx, NewBB);
+      }
+    } else {
+      // However, the foreach loop is slow for blocks with lots of predecessors
+      // because PHINode::getIncomingBlock is O(n) in # preds.  Instead, walk
+      // the user list of TIBB to find the PHI nodes.
+      SmallPtrSet<PHINode*, 16> UpdatedPHIs;
+    
+      for (Value::use_iterator UI = TIBB->use_begin(), E = TIBB->use_end();
+           UI != E; ) {
+        Value::use_iterator Use = UI++;
+        if (PHINode *PN = dyn_cast<PHINode>(*Use)) {
+          // Remove one entry from each PHI.
+          if (PN->getParent() == DestBB && UpdatedPHIs.insert(PN))
+            PN->setOperand(Use.getOperandNo(), NewBB);
+        }
+      }
     }
   }
    

Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Mon Jun 20 21:09:03 2011
@@ -572,12 +572,12 @@
     // removed, so we just need to splice the blocks.
     BI->eraseFromParent();
     
-    // Make all PHI nodes that referred to Dest now refer to I as their source.
-    Dest->replaceAllUsesWith(I);
-
     // Move all the instructions in the succ to the pred.
     I->getInstList().splice(I->end(), Dest->getInstList());
     
+    // Make all PHI nodes that referred to Dest now refer to I as their source.
+    Dest->replaceAllUsesWith(I);
+
     // Remove the dest block.
     Dest->eraseFromParent();
     

Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Mon Jun 20 21:09:03 2011
@@ -1097,15 +1097,15 @@
         TheCall->replaceAllUsesWith(Returns[0]->getReturnValue());
     }
 
-    // Update PHI nodes that use the ReturnBB to use the AfterCallBB.
-    BasicBlock *ReturnBB = Returns[0]->getParent();
-    ReturnBB->replaceAllUsesWith(AfterCallBB);
-
     // Splice the code from the return block into the block that it will return
     // to, which contains the code that was after the call.
+    BasicBlock *ReturnBB = Returns[0]->getParent();
     AfterCallBB->getInstList().splice(AfterCallBB->begin(),
                                       ReturnBB->getInstList());
 
+    // Update PHI nodes that use the ReturnBB to use the AfterCallBB.
+    ReturnBB->replaceAllUsesWith(AfterCallBB);
+
     // Delete the return instruction now and empty ReturnBB now.
     Returns[0]->eraseFromParent();
     ReturnBB->eraseFromParent();
@@ -1125,8 +1125,8 @@
 
   // Splice the code entry block into calling block, right before the
   // unconditional branch.
-  CalleeEntry->replaceAllUsesWith(OrigBB);  // Update PHI nodes
   OrigBB->getInstList().splice(Br, CalleeEntry->getInstList());
+  CalleeEntry->replaceAllUsesWith(OrigBB);  // Update PHI nodes
 
   // Remove the unconditional branch.
   OrigBB->getInstList().erase(Br);

Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/Local.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/Local.cpp Mon Jun 20 21:09:03 2011
@@ -427,6 +427,10 @@
   BasicBlock *PredBB = DestBB->getSinglePredecessor();
   assert(PredBB && "Block doesn't have a single predecessor!");
   
+  // Splice all the instructions from PredBB to DestBB.
+  PredBB->getTerminator()->eraseFromParent();
+  DestBB->getInstList().splice(DestBB->begin(), PredBB->getInstList());
+
   // Zap anything that took the address of DestBB.  Not doing this will give the
   // address an invalid value.
   if (DestBB->hasAddressTaken()) {
@@ -441,10 +445,6 @@
   // Anything that branched to PredBB now branches to DestBB.
   PredBB->replaceAllUsesWith(DestBB);
   
-  // Splice all the instructions from PredBB to DestBB.
-  PredBB->getTerminator()->eraseFromParent();
-  DestBB->getInstList().splice(DestBB->begin(), PredBB->getInstList());
-
   if (P) {
     DominatorTree *DT = P->getAnalysisIfAvailable<DominatorTree>();
     if (DT) {
@@ -660,17 +660,12 @@
     // them, which helps expose duplicates, but we have to check all the
     // operands to be safe in case instcombine hasn't run.
     uintptr_t Hash = 0;
-    // This hash algorithm is quite weak as hash functions go, but it seems
-    // to do a good enough job for this particular purpose, and is very quick.
     for (User::op_iterator I = PN->op_begin(), E = PN->op_end(); I != E; ++I) {
+      // This hash algorithm is quite weak as hash functions go, but it seems
+      // to do a good enough job for this particular purpose, and is very quick.
       Hash ^= reinterpret_cast<uintptr_t>(static_cast<Value *>(*I));
       Hash = (Hash << 7) | (Hash >> (sizeof(uintptr_t) * CHAR_BIT - 7));
     }
-    for (PHINode::block_iterator I = PN->block_begin(), E = PN->block_end();
-         I != E; ++I) {
-      Hash ^= reinterpret_cast<uintptr_t>(static_cast<BasicBlock *>(*I));
-      Hash = (Hash << 7) | (Hash >> (sizeof(uintptr_t) * CHAR_BIT - 7));
-    }
     // Avoid colliding with the DenseMap sentinels ~0 and ~0-1.
     Hash >>= 1;
     // If we've never seen this hash value before, it's a unique PHI.

Modified: llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp Mon Jun 20 21:09:03 2011
@@ -47,14 +47,6 @@
     if (It != VMap.end())
       I->setOperand(op, It->second);
   }
-
-  if (PHINode *PN = dyn_cast<PHINode>(I)) {
-    for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
-      ValueToValueMapTy::iterator It = VMap.find(PN->getIncomingBlock(i));
-      if (It != VMap.end())
-        PN->setIncomingBlock(i, cast<BasicBlock>(It->second));
-    }
-  }
 }
 
 /// FoldBlockIntoPredecessor - Folds a basic block into its predecessor if it
@@ -83,13 +75,13 @@
   // Delete the unconditional branch from the predecessor...
   OnlyPred->getInstList().pop_back();
 
+  // Move all definitions in the successor to the predecessor...
+  OnlyPred->getInstList().splice(OnlyPred->end(), BB->getInstList());
+
   // Make all PHI nodes that referred to BB now refer to Pred as their
   // source...
   BB->replaceAllUsesWith(OnlyPred);
 
-  // Move all definitions in the successor to the predecessor...
-  OnlyPred->getInstList().splice(OnlyPred->end(), BB->getInstList());
-
   std::string OldName = BB->getName();
 
   // Erase basic block from the function...
@@ -255,14 +247,16 @@
       // the successor of the latch block.  The successor of the exit block will
       // be updated specially after unrolling all the way.
       if (*BB != LatchBlock)
-        for (succ_iterator SI = succ_begin(*BB), SE = succ_end(*BB); SI != SE;
-             ++SI)
-          if (!L->contains(*SI))
-            for (BasicBlock::iterator BBI = (*SI)->begin(), BBE = (*SI)->end();
-                 PHINode *phi = dyn_cast<PHINode>(BBI); ++BBI) {
-              Value *Incoming = phi->getIncomingValueForBlock(*BB);
-              phi->addIncoming(Incoming, New);
-            }
+        for (Value::use_iterator UI = (*BB)->use_begin(), UE = (*BB)->use_end();
+             UI != UE;) {
+          Instruction *UseInst = cast<Instruction>(*UI);
+          ++UI;
+          if (isa<PHINode>(UseInst) && !L->contains(UseInst)) {
+            PHINode *phi = cast<PHINode>(UseInst);
+            Value *Incoming = phi->getIncomingValueForBlock(*BB);
+            phi->addIncoming(Incoming, New);
+          }
+        }
 
       // Keep track of new headers and latches as we create them, so that
       // we can insert the proper branches later.
@@ -294,20 +288,24 @@
   // successor blocks, update them to use the appropriate values computed as the
   // last iteration of the loop.
   if (Count != 1) {
+    SmallPtrSet<PHINode*, 8> Users;
+    for (Value::use_iterator UI = LatchBlock->use_begin(),
+         UE = LatchBlock->use_end(); UI != UE; ++UI)
+      if (PHINode *phi = dyn_cast<PHINode>(*UI))
+        Users.insert(phi);
+    
     BasicBlock *LastIterationBB = cast<BasicBlock>(LastValueMap[LatchBlock]);
-    for (succ_iterator SI = succ_begin(LatchBlock), SE = succ_end(LatchBlock);
+    for (SmallPtrSet<PHINode*,8>::iterator SI = Users.begin(), SE = Users.end();
          SI != SE; ++SI) {
-      for (BasicBlock::iterator BBI = (*SI)->begin(), BBE = (*SI)->end();
-           PHINode *PN = dyn_cast<PHINode>(BBI); ++BBI) {
-        Value *InVal = PN->removeIncomingValue(LatchBlock, false);
-        // If this value was defined in the loop, take the value defined by the
-        // last iteration of the loop.
-        if (Instruction *InValI = dyn_cast<Instruction>(InVal)) {
-          if (L->contains(InValI))
-            InVal = LastValueMap[InVal];
-        }
-        PN->addIncoming(InVal, LastIterationBB);
+      PHINode *PN = *SI;
+      Value *InVal = PN->removeIncomingValue(LatchBlock, false);
+      // If this value was defined in the loop, take the value defined by the
+      // last iteration of the loop.
+      if (Instruction *InValI = dyn_cast<Instruction>(InVal)) {
+        if (L->contains(InValI))
+          InVal = LastValueMap[InVal];
       }
+      PN->addIncoming(InVal, LastIterationBB);
     }
   }
 
@@ -354,16 +352,11 @@
       // Replace the conditional branch with an unconditional one.
       BranchInst::Create(Dest, Term);
       Term->eraseFromParent();
-    }
-  }
-
-  // Merge adjacent basic blocks, if possible.
-  for (unsigned i = 0, e = Latches.size(); i != e; ++i) {
-    BranchInst *Term = cast<BranchInst>(Latches[i]->getTerminator());
-    if (Term->isUnconditional()) {
-      BasicBlock *Dest = Term->getSuccessor(0);
-      if (BasicBlock *Fold = FoldBlockIntoPredecessor(Dest, LI))
+      // Merge adjacent basic blocks, if possible.
+      if (BasicBlock *Fold = FoldBlockIntoPredecessor(Dest, LI)) {
         std::replace(Latches.begin(), Latches.end(), Dest, Fold);
+        std::replace(Headers.begin(), Headers.end(), Dest, Fold);
+      }
     }
   }
   

Modified: llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp Mon Jun 20 21:09:03 2011
@@ -16,7 +16,6 @@
 #include "llvm/Type.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
-#include "llvm/Instructions.h"
 #include "llvm/Metadata.h"
 #include "llvm/ADT/SmallVector.h"
 using namespace llvm;
@@ -129,19 +128,6 @@
              "Referenced value not in value map!");
   }
 
-  // Remap phi nodes' incoming blocks.
-  if (PHINode *PN = dyn_cast<PHINode>(I)) {
-    for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
-      Value *V = MapValue(PN->getIncomingBlock(i), VMap, Flags);
-      // If we aren't ignoring missing entries, assert that something happened.
-      if (V != 0)
-        PN->setIncomingBlock(i, cast<BasicBlock>(V));
-      else
-        assert((Flags & RF_IgnoreMissingEntries) &&
-               "Referenced block not in value map!");
-    }
-  }
-
   // Remap attached metadata.
   SmallVector<std::pair<unsigned, MDNode *>, 4> MDs;
   I->getAllMetadata(MDs);

Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/BasicBlock.cpp (original)
+++ llvm/trunk/lib/VMCore/BasicBlock.cpp Mon Jun 20 21:09:03 2011
@@ -308,19 +308,3 @@
   return New;
 }
 
-void BasicBlock::replaceSuccessorsPhiUsesWith(BasicBlock *New) {
-  TerminatorInst *TI = getTerminator();
-  if (!TI)
-    // Cope with being called on a BasicBlock that doesn't have a terminator
-    // yet. Clang's CodeGenFunction::EmitReturnBlock() likes to do this.
-    return;
-  for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) {
-    BasicBlock *Succ = TI->getSuccessor(i);
-    for (iterator II = Succ->begin(); PHINode *PN = dyn_cast<PHINode>(II);
-         ++II) {
-      int i;
-      while ((i = PN->getBasicBlockIndex(this)) >= 0)
-        PN->setIncomingBlock(i, New);
-    }
-  }
-}

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Mon Jun 20 21:09:03 2011
@@ -87,8 +87,11 @@
   : Instruction(PN.getType(), Instruction::PHI,
                 allocHungoffUses(PN.getNumOperands()), PN.getNumOperands()),
     ReservedSpace(PN.getNumOperands()) {
-  std::copy(PN.op_begin(), PN.op_end(), op_begin());
-  std::copy(PN.block_begin(), PN.block_end(), block_begin());
+  Use *OL = OperandList;
+  for (unsigned i = 0, e = PN.getNumOperands(); i != e; i+=2) {
+    OL[i] = PN.getOperand(i);
+    OL[i+1] = PN.getOperand(i+1);
+  }
   SubclassOptionalData = PN.SubclassOptionalData;
 }
 
@@ -96,37 +99,31 @@
   dropHungoffUses();
 }
 
-Use *PHINode::allocHungoffUses(unsigned N) const {
-  // Allocate the array of Uses of the incoming values, followed by a pointer
-  // (with bottom bit set) to the User, followed by the array of pointers to
-  // the incoming basic blocks.
-  size_t size = N * sizeof(Use) + sizeof(Use::UserRef)
-    + N * sizeof(BasicBlock*);
-  Use *Begin = static_cast<Use*>(::operator new(size));
-  Use *End = Begin + N;
-  (void) new(End) Use::UserRef(const_cast<PHINode*>(this), 1);
-  return Use::initTags(Begin, End);
-}
-
 // removeIncomingValue - Remove an incoming value.  This is useful if a
 // predecessor basic block is deleted.
 Value *PHINode::removeIncomingValue(unsigned Idx, bool DeletePHIIfEmpty) {
-  Value *Removed = getIncomingValue(Idx);
+  unsigned NumOps = getNumOperands();
+  Use *OL = OperandList;
+  assert(Idx*2 < NumOps && "BB not in PHI node!");
+  Value *Removed = OL[Idx*2];
 
   // Move everything after this operand down.
   //
   // FIXME: we could just swap with the end of the list, then erase.  However,
-  // clients might not expect this to happen.  The code as it is thrashes the
+  // client might not expect this to happen.  The code as it is thrashes the
   // use/def lists, which is kinda lame.
-  std::copy(op_begin() + Idx + 1, op_end(), op_begin() + Idx);
-  std::copy(block_begin() + Idx + 1, block_end(), block_begin() + Idx);
+  for (unsigned i = (Idx+1)*2; i != NumOps; i += 2) {
+    OL[i-2] = OL[i];
+    OL[i-2+1] = OL[i+1];
+  }
 
   // Nuke the last value.
-  Op<-1>().set(0);
-  --NumOperands;
+  OL[NumOps-2].set(0);
+  OL[NumOps-2+1].set(0);
+  NumOperands = NumOps-2;
 
   // If the PHI node is dead, because it has zero entries, nuke it now.
-  if (getNumOperands() == 0 && DeletePHIIfEmpty) {
+  if (NumOps == 2 && DeletePHIIfEmpty) {
     // If anyone is using this PHI, make them use a dummy value instead...
     replaceAllUsesWith(UndefValue::get(getType()));
     eraseFromParent();
@@ -140,18 +137,15 @@
 ///
 void PHINode::growOperands() {
   unsigned e = getNumOperands();
-  unsigned NumOps = e + e / 2;
-  if (NumOps < 2) NumOps = 2;      // 2 op PHI nodes are VERY common.
-
-  Use *OldOps = op_begin();
-  BasicBlock **OldBlocks = block_begin();
+  // Multiply by 1.5 and round down so the result is still even.
+  unsigned NumOps = e + e / 4 * 2;
+  if (NumOps < 4) NumOps = 4;      // 4 op PHI nodes are VERY common.
 
   ReservedSpace = NumOps;
-  OperandList = allocHungoffUses(ReservedSpace);
-
-  std::copy(OldOps, OldOps + e, op_begin());
-  std::copy(OldBlocks, OldBlocks + e, block_begin());
-
+  Use *OldOps = OperandList;
+  Use *NewOps = allocHungoffUses(NumOps);
+  std::copy(OldOps, OldOps + e, NewOps);
+  OperandList = NewOps;
   Use::zap(OldOps, OldOps + e, true);
 }
 

Modified: llvm/trunk/lib/VMCore/User.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/User.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/User.cpp (original)
+++ llvm/trunk/lib/VMCore/User.cpp Mon Jun 20 21:09:03 2011
@@ -40,10 +40,8 @@
 //===----------------------------------------------------------------------===//
 
 Use *User::allocHungoffUses(unsigned N) const {
-  // Allocate the array of Uses, followed by a pointer (with bottom bit set) to
-  // the User.
-  size_t size = N * sizeof(Use) + sizeof(Use::UserRef);
-  Use *Begin = static_cast<Use*>(::operator new(size));
+  Use *Begin = static_cast<Use*>(::operator new(sizeof(Use) * N
+                                                + sizeof(Use::UserRef)));
   Use *End = Begin + N;
   (void) new(End) Use::UserRef(const_cast<User*>(this), 1);
   return Use::initTags(Begin, End);

Modified: llvm/trunk/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Value.cpp (original)
+++ llvm/trunk/lib/VMCore/Value.cpp Mon Jun 20 21:09:03 2011
@@ -305,9 +305,6 @@
 
     U.set(New);
   }
-
-  if (BasicBlock *BB = dyn_cast<BasicBlock>(this))
-    BB->replaceSuccessorsPhiUsesWith(cast<BasicBlock>(New));
 }
 
 void Value::replaceAllUsesWith(Value *New) {

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=133499&r1=133498&r2=133499&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Mon Jun 20 21:09:03 2011
@@ -1139,6 +1139,9 @@
   for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
     Assert1(PN.getType() == PN.getIncomingValue(i)->getType(),
             "PHI node operands are not the same type as the result!", &PN);
+    Assert1(isa<BasicBlock>(PN.getOperand(
+                PHINode::getOperandNumForIncomingBlock(i))),
+            "PHI node incoming block is not a BasicBlock!", &PN);
   }
 
   // All other PHI node constraints are checked in the visitBasicBlock method.



From chenwj at iis.sinica.edu.tw  Mon Jun 20 20:36:34 2011
From: chenwj at iis.sinica.edu.tw (=?utf-8?B?6Zmz6Z+L5Lu7?=)
Date: Tue, 21 Jun 2011 09:36:34 +0800
Subject: [llvm-commits] [PATCH][Target/PTX] Add address_size directive
 to PTX backend
In-Reply-To: <BD989BFB-373E-4577-8F21-C544F561DA49@gmail.com>
References: <20110617073109.GA93378@cs.nctu.edu.tw>
	<CA57A5F6-2F8E-4AAC-B6E7-279DA5F2D8EE@gmail.com>
	<20110618065617.GA25444@cs.nctu.edu.tw>
	<B3C74E93-B790-4255-808D-DBB9E94278C6@gmail.com>
	<20110619121258.GA50677@cs.nctu.edu.tw>
	<347A9771-6ADD-4454-86D6-2842AEA82D44@gmail.com>
	<20110620015129.GA56262@cs.nctu.edu.tw>
	<BD989BFB-373E-4577-8F21-C544F561DA49@gmail.com>
Message-ID: <20110621013634.GA86556@cs.nctu.edu.tw>

> I hate to nit-pick, but do we really need the address size field and associated enumeration?  It's always tied to the 64-bit flag, and we do not need to create any TableGen predicates from the value.
> 
> I think this patch can be as simple as:
> 
> if (ST.supportsPTX23()) {
>   std::string addrSize = is64Bit() ? "64" : "32";
>   OutStreamer.EmitRawText(Twine("\t.address_size " + addrSize));
> }

  Done.

Regards,
chenwj

-- 
Wei-Ren Chen (???)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667
-------------- next part --------------
Index: test/CodeGen/PTX/options.ll
===================================================================
--- test/CodeGen/PTX/options.ll	(revision 133496)
+++ test/CodeGen/PTX/options.ll	(working copy)
@@ -5,6 +5,8 @@
 ; RUN: llc < %s -march=ptx32 -mattr=sm10 | grep ".target sm_10"
 ; RUN: llc < %s -march=ptx32 -mattr=sm13 | grep ".target sm_13"
 ; RUN: llc < %s -march=ptx32 -mattr=sm20 | grep ".target sm_20"
+; RUN: llc < %s -march=ptx32 -mattr=ptx23 | grep ".address_size 32"
+; RUN: llc < %s -march=ptx64 -mattr=ptx23 | grep ".address_size 64"
 
 define ptx_device void @t1() {
 	ret void
Index: lib/Target/PTX/PTXAsmPrinter.cpp
===================================================================
--- lib/Target/PTX/PTXAsmPrinter.cpp	(revision 133496)
+++ lib/Target/PTX/PTXAsmPrinter.cpp	(working copy)
@@ -163,6 +163,13 @@
   OutStreamer.EmitRawText(Twine("\t.target " + ST.getTargetString() +
                                 (ST.supportsDouble() ? ""
                                                      : ", map_f64_to_f32")));
+  // .address_size directive is optional, but it must immediately follow
+  // the .target directive if present within a module
+  if (ST.supportsPTX23()) {
+    std::string addrSize = ST.is64Bit() ? "64" : "32";
+    OutStreamer.EmitRawText(Twine("\t.address_size " + addrSize));
+  }
+
   OutStreamer.AddBlankLine();
 
   // declare global variables

From evan.cheng at apple.com  Mon Jun 20 21:41:38 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Mon, 20 Jun 2011 19:41:38 -0700
Subject: [llvm-commits] [llvm] r133289 - in /llvm/trunk:
 lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td
 test/CodeGen/ARM/rev.ll
In-Reply-To: <5FA0FBB4-F54C-4C4C-9C34-EB3EE73F6462@apple.com>
References: <20110617204721.8235E2A6C12C@llvm.org>
	<17797AD1-4AD0-4029-85E9-808F1E61821A@apple.com>
	<BANLkTimRpX_zhnAejkbp7zRhkRio4rzV8A@mail.gmail.com>
	<5FA0FBB4-F54C-4C4C-9C34-EB3EE73F6462@apple.com>
Message-ID: <BCF5546B-E356-4E3F-B742-D8A4A91362AA@apple.com>

I'm working on a fix.

Evan

On Jun 18, 2011, at 12:10 AM, Chris Lattner wrote:

> 
> On Jun 17, 2011, at 11:06 PM, Eli Friedman wrote:
> 
>> On Fri, Jun 17, 2011 at 9:53 PM, Chris Lattner <clattner at apple.com> wrote:
>>> 
>>> On Jun 17, 2011, at 1:47 PM, Evan Cheng wrote:
>>> 
>>>> Author: evancheng
>>>> Date: Fri Jun 17 15:47:21 2011
>>>> New Revision: 133289
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=133289&view=rev
>>>> Log:
>>>> Add an alternative rev16 pattern. We should figure out a better way to handle these complex rev patterns. rdar://9609108
>>> 
>>> Is rev16 just a bswap?
>> 
>> It's bswap+rotate by 16.
> 
> Ok, can/should the pattern be written in terms of bswap+rotate?
> 
> -Chris


From atrick at apple.com  Mon Jun 20 22:22:38 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 21 Jun 2011 03:22:38 -0000
Subject: [llvm-commits] [llvm] r133502 - in /llvm/trunk:
 lib/Transforms/Scalar/IndVarSimplify.cpp
 test/Transforms/IndVarSimplify/iv-zext.ll
Message-ID: <20110621032238.34E8D2A6C12C@llvm.org>

Author: atrick
Date: Mon Jun 20 22:22:38 2011
New Revision: 133502

URL: http://llvm.org/viewvc/llvm-project?rev=133502&view=rev
Log:
indvars -disable-iv-rewrite: Adds support for eliminating identity
ops.

This is a rewrite of the IV simplification algorithm used by
-disable-iv-rewrite. To avoid perturbing the default mode, I
temporarily split the driver and created SimplifyIVUsersNoRewrite. The
idea is to avoid doing opcode/pattern matching inside
IndVarSimplify. SCEV already does it. We want to optimize with the
full generality of SCEV, but optimize def-use chains top down on-demand rather
than rewriting the entire expression bottom-up. This was easy to do
for operations that SCEV can prove are identity function. So we're now
eliminating bitmasks and zero extends this way.

A result of this rewrite is that indvars -disable-iv-rewrite no longer
requires IVUsers.

Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
    llvm/trunk/test/Transforms/IndVarSimplify/iv-zext.ll

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=133502&r1=133501&r2=133502&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Jun 20 22:22:38 2011
@@ -62,14 +62,15 @@
 #include "llvm/ADT/STLExtras.h"
 using namespace llvm;
 
-STATISTIC(NumRemoved , "Number of aux indvars removed");
-STATISTIC(NumWidened , "Number of indvars widened");
-STATISTIC(NumInserted, "Number of canonical indvars added");
-STATISTIC(NumReplaced, "Number of exit values replaced");
-STATISTIC(NumLFTR    , "Number of loop exit tests replaced");
-STATISTIC(NumElimExt , "Number of IV sign/zero extends eliminated");
-STATISTIC(NumElimRem , "Number of IV remainder operations eliminated");
-STATISTIC(NumElimCmp , "Number of IV comparisons eliminated");
+STATISTIC(NumRemoved     , "Number of aux indvars removed");
+STATISTIC(NumWidened     , "Number of indvars widened");
+STATISTIC(NumInserted    , "Number of canonical indvars added");
+STATISTIC(NumReplaced    , "Number of exit values replaced");
+STATISTIC(NumLFTR        , "Number of loop exit tests replaced");
+STATISTIC(NumElimIdentity, "Number of IV identities eliminated");
+STATISTIC(NumElimExt     , "Number of IV sign/zero extends eliminated");
+STATISTIC(NumElimRem     , "Number of IV remainder operations eliminated");
+STATISTIC(NumElimCmp     , "Number of IV comparisons eliminated");
 
 // DisableIVRewrite mode currently affects IVUsers, so is defined in libAnalysis
 // and referenced here.
@@ -84,12 +85,22 @@
     ScalarEvolution *SE;
     DominatorTree   *DT;
     TargetData      *TD;
+
+    PHINode         *CurrIV; // Current IV being simplified.
+
+     // Instructions processed by SimplifyIVUsers for CurrIV.
+    SmallPtrSet<Instruction*,16> Simplified;
+
+    // Use-def pairs if IVUsers waiting to be processed for CurrIV.
+    SmallVector<std::pair<Instruction*, Instruction*>, 8> SimpleIVUsers;
+
     SmallVector<WeakVH, 16> DeadInsts;
     bool Changed;
   public:
 
     static char ID; // Pass identification, replacement for typeid
-    IndVarSimplify() : LoopPass(ID), IU(0), LI(0), SE(0), DT(0), TD(0) {
+    IndVarSimplify() : LoopPass(ID), IU(0), LI(0), SE(0), DT(0), TD(0),
+                       CurrIV(0), Changed(false) {
       initializeIndVarSimplifyPass(*PassRegistry::getPassRegistry());
     }
 
@@ -105,7 +116,8 @@
       AU.addPreserved<ScalarEvolution>();
       AU.addPreservedID(LoopSimplifyID);
       AU.addPreservedID(LCSSAID);
-      AU.addPreserved<IVUsers>();
+      if (!DisableIVRewrite)
+        AU.addPreserved<IVUsers>();
       AU.setPreservesCFG();
     }
 
@@ -113,11 +125,16 @@
     bool isValidRewrite(Value *FromVal, Value *ToVal);
 
     void SimplifyIVUsers(SCEVExpander &Rewriter);
+    void SimplifyIVUsersNoRewrite(Loop *L, SCEVExpander &Rewriter);
+
+    bool EliminateIVUser(Instruction *UseInst, Instruction *IVOperand);
     void EliminateIVComparison(ICmpInst *ICmp, Value *IVOperand);
     void EliminateIVRemainder(BinaryOperator *Rem,
                               Value *IVOperand,
                               bool IsSigned,
                               PHINode *IVPhi);
+    void pushIVUsers(Instruction *Def);
+    bool isSimpleIVUser(Instruction *I, const Loop *L);
     void RewriteNonIntegerIVs(Loop *L);
 
     ICmpInst *LinearFunctionTestReplace(Loop *L, const SCEV *BackedgeTakenCount,
@@ -483,6 +500,36 @@
     SE->forgetLoop(L);
 }
 
+/// SimplifyIVUsers - Iteratively perform simplification on IVUsers within this
+/// loop. IVUsers is treated as a worklist. Each successive simplification may
+/// push more users which may themselves be candidates for simplification.
+///
+/// This is the old approach to IV simplification to be replaced by
+/// SimplifyIVUsersNoRewrite.
+///
+void IndVarSimplify::SimplifyIVUsers(SCEVExpander &Rewriter) {
+  // Each round of simplification involves a round of eliminating operations
+  // followed by a round of widening IVs. A single IVUsers worklist is used
+  // across all rounds. The inner loop advances the user. If widening exposes
+  // more uses, then another pass through the outer loop is triggered.
+  for (IVUsers::iterator I = IU->begin(); I != IU->end(); ++I) {
+    Instruction *UseInst = I->getUser();
+    Value *IVOperand = I->getOperandValToReplace();
+
+    if (ICmpInst *ICmp = dyn_cast<ICmpInst>(UseInst)) {
+      EliminateIVComparison(ICmp, IVOperand);
+      continue;
+    }
+    if (BinaryOperator *Rem = dyn_cast<BinaryOperator>(UseInst)) {
+      bool IsSigned = Rem->getOpcode() == Instruction::SRem;
+      if (IsSigned || Rem->getOpcode() == Instruction::URem) {
+        EliminateIVRemainder(Rem, IVOperand, IsSigned, I->getPhi());
+        continue;
+      }
+    }
+  }
+}
+
 namespace {
   // Collect information about induction variables that are used by sign/zero
   // extend operations. This information is recorded by CollectExtend and
@@ -493,33 +540,30 @@
 
     WideIVInfo() : WidestNativeType(0), IsSigned(false) {}
   };
-  typedef std::map<PHINode *, WideIVInfo> WideIVMap;
 }
 
 /// CollectExtend - Update information about the induction variable that is
 /// extended by this sign or zero extend operation. This is used to determine
 /// the final width of the IV before actually widening it.
-static void CollectExtend(CastInst *Cast, PHINode *Phi, bool IsSigned,
-                          WideIVMap &IVMap, ScalarEvolution *SE,
-                          const TargetData *TD) {
+static void CollectExtend(CastInst *Cast, bool IsSigned, WideIVInfo &WI,
+                          ScalarEvolution *SE, const TargetData *TD) {
   const Type *Ty = Cast->getType();
   uint64_t Width = SE->getTypeSizeInBits(Ty);
   if (TD && !TD->isLegalInteger(Width))
     return;
 
-  WideIVInfo &IVInfo = IVMap[Phi];
-  if (!IVInfo.WidestNativeType) {
-    IVInfo.WidestNativeType = SE->getEffectiveSCEVType(Ty);
-    IVInfo.IsSigned = IsSigned;
+  if (!WI.WidestNativeType) {
+    WI.WidestNativeType = SE->getEffectiveSCEVType(Ty);
+    WI.IsSigned = IsSigned;
     return;
   }
 
   // We extend the IV to satisfy the sign of its first user, arbitrarily.
-  if (IVInfo.IsSigned != IsSigned)
+  if (WI.IsSigned != IsSigned)
     return;
 
-  if (Width > SE->getTypeSizeInBits(IVInfo.WidestNativeType))
-    IVInfo.WidestNativeType = SE->getEffectiveSCEVType(Ty);
+  if (Width > SE->getTypeSizeInBits(WI.WidestNativeType))
+    WI.WidestNativeType = SE->getEffectiveSCEVType(Ty);
 }
 
 namespace {
@@ -529,43 +573,44 @@
 /// inserting truncs whenever we stop propagating the type.
 ///
 class WidenIV {
+  // Parameters
   PHINode *OrigPhi;
   const Type *WideType;
   bool IsSigned;
 
-  IVUsers *IU;
-  LoopInfo *LI;
-  Loop *L;
+  // Context
+  LoopInfo        *LI;
+  Loop            *L;
   ScalarEvolution *SE;
-  DominatorTree *DT;
-  SmallVectorImpl<WeakVH> &DeadInsts;
+  DominatorTree   *DT;
 
+  // Result
   PHINode *WidePhi;
   Instruction *WideInc;
   const SCEV *WideIncExpr;
+  SmallVectorImpl<WeakVH> &DeadInsts;
 
-  SmallPtrSet<Instruction*,16> Processed;
+  SmallPtrSet<Instruction*,16> Widened;
 
 public:
-  WidenIV(PHINode *PN, const WideIVInfo &IVInfo, IVUsers *IUsers,
-          LoopInfo *LInfo, ScalarEvolution *SEv, DominatorTree *DTree,
+  WidenIV(PHINode *PN, const WideIVInfo &WI, LoopInfo *LInfo,
+          ScalarEvolution *SEv, DominatorTree *DTree,
           SmallVectorImpl<WeakVH> &DI) :
     OrigPhi(PN),
-    WideType(IVInfo.WidestNativeType),
-    IsSigned(IVInfo.IsSigned),
-    IU(IUsers),
+    WideType(WI.WidestNativeType),
+    IsSigned(WI.IsSigned),
     LI(LInfo),
     L(LI->getLoopFor(OrigPhi->getParent())),
     SE(SEv),
     DT(DTree),
-    DeadInsts(DI),
     WidePhi(0),
     WideInc(0),
-    WideIncExpr(0) {
+    WideIncExpr(0),
+    DeadInsts(DI) {
     assert(L->getHeader() == OrigPhi->getParent() && "Phi must be an IV");
   }
 
-  bool CreateWideIV(SCEVExpander &Rewriter);
+  PHINode *CreateWideIV(SCEVExpander &Rewriter);
 
 protected:
   Instruction *CloneIVUser(Instruction *NarrowUse,
@@ -580,52 +625,6 @@
 };
 } // anonymous namespace
 
-/// SimplifyIVUsers - Iteratively perform simplification on IVUsers within this
-/// loop. IVUsers is treated as a worklist. Each successive simplification may
-/// push more users which may themselves be candidates for simplification.
-///
-void IndVarSimplify::SimplifyIVUsers(SCEVExpander &Rewriter) {
-  WideIVMap IVMap;
-
-  // Each round of simplification involves a round of eliminating operations
-  // followed by a round of widening IVs. A single IVUsers worklist is used
-  // across all rounds. The inner loop advances the user. If widening exposes
-  // more uses, then another pass through the outer loop is triggered.
-  for (IVUsers::iterator I = IU->begin(), E = IU->end(); I != E;) {
-    for(; I != E; ++I) {
-      Instruction *UseInst = I->getUser();
-      Value *IVOperand = I->getOperandValToReplace();
-
-      if (DisableIVRewrite) {
-        if (CastInst *Cast = dyn_cast<CastInst>(UseInst)) {
-          bool IsSigned = Cast->getOpcode() == Instruction::SExt;
-          if (IsSigned || Cast->getOpcode() == Instruction::ZExt) {
-            CollectExtend(Cast, I->getPhi(), IsSigned, IVMap, SE, TD);
-            continue;
-          }
-        }
-      }
-      if (ICmpInst *ICmp = dyn_cast<ICmpInst>(UseInst)) {
-        EliminateIVComparison(ICmp, IVOperand);
-        continue;
-      }
-      if (BinaryOperator *Rem = dyn_cast<BinaryOperator>(UseInst)) {
-        bool IsSigned = Rem->getOpcode() == Instruction::SRem;
-        if (IsSigned || Rem->getOpcode() == Instruction::URem) {
-          EliminateIVRemainder(Rem, IVOperand, IsSigned, I->getPhi());
-          continue;
-        }
-      }
-    }
-    for (WideIVMap::const_iterator I = IVMap.begin(), E = IVMap.end();
-         I != E; ++I) {
-      WidenIV Widener(I->first, I->second, IU, LI, SE, DT, DeadInsts);
-      if (Widener.CreateWideIV(Rewriter))
-        Changed = true;
-    }
-  }
-}
-
 static Value *getExtend( Value *NarrowOper, const Type *WideType,
                                bool IsSigned, IRBuilder<> &Builder) {
   return IsSigned ? Builder.CreateSExt(NarrowOper, WideType) :
@@ -744,7 +743,7 @@
     return 0;
 
   // Handle data flow merges and bizarre phi cycles.
-  if (!Processed.insert(NarrowUse))
+  if (!Widened.insert(NarrowUse))
     return 0;
 
   // Our raison d'etre! Eliminate sign and zero extension.
@@ -775,9 +774,11 @@
       NarrowUse->replaceAllUsesWith(NewDef);
       DeadInsts.push_back(NarrowUse);
     }
-    // Now that the extend is gone, expose it's uses to IVUsers for potential
-    // further simplification within SimplifyIVUsers.
-    IU->AddUsersIfInteresting(WideDef, WidePhi);
+    // Now that the extend is gone, we want to expose it's uses for potential
+    // further simplification. We don't need to directly inform SimplifyIVUsers
+    // of the new users, because their parent IV will be processed later as a
+    // new loop phi. If we preserved IVUsers analysis, we would also want to
+    // push the uses of WideDef here.
 
     // No further widening is needed. The deceased [sz]ext had done it for us.
     return 0;
@@ -807,7 +808,7 @@
   // outside the loop without overflow. This suggests that the wide use
   // evaluates to the same expression as the extended narrow use, but doesn't
   // absolutely guarantee it. Hence the following failsafe check. In rare cases
-  // where it fails, we simple throw away the newly created wide use.
+  // where it fails, we simply throw away the newly created wide use.
   if (WideAddRec != SE->getSCEV(WideUse)) {
     DEBUG(dbgs() << "Wide use expression mismatch: " << *WideUse
           << ": " << *SE->getSCEV(WideUse) << " != " << *WideAddRec << "\n");
@@ -822,18 +823,18 @@
 /// CreateWideIV - Process a single induction variable. First use the
 /// SCEVExpander to create a wide induction variable that evaluates to the same
 /// recurrence as the original narrow IV. Then use a worklist to forward
-/// traverse the narrow IV's def-use chain. After WidenIVUse as processed all
+/// traverse the narrow IV's def-use chain. After WidenIVUse has processed all
 /// interesting IV users, the narrow IV will be isolated for removal by
 /// DeleteDeadPHIs.
 ///
 /// It would be simpler to delete uses as they are processed, but we must avoid
 /// invalidating SCEV expressions.
 ///
-bool WidenIV::CreateWideIV(SCEVExpander &Rewriter) {
+PHINode *WidenIV::CreateWideIV(SCEVExpander &Rewriter) {
   // Is this phi an induction variable?
   const SCEVAddRecExpr *AddRec = dyn_cast<SCEVAddRecExpr>(SE->getSCEV(OrigPhi));
   if (!AddRec)
-    return false;
+    return NULL;
 
   // Widen the induction variable expression.
   const SCEV *WideIVExpr = IsSigned ?
@@ -846,9 +847,9 @@
   // Can the IV be extended outside the loop without overflow?
   AddRec = dyn_cast<SCEVAddRecExpr>(WideIVExpr);
   if (!AddRec || AddRec->getLoop() != L)
-    return false;
+    return NULL;
 
-  // An AddRec must have loop-invariant operands. Since this AddRec it
+  // An AddRec must have loop-invariant operands. Since this AddRec is
   // materialized by a loop header phi, the expression cannot have any post-loop
   // operands, so they must dominate the loop header.
   assert(SE->properlyDominates(AddRec->getStart(), L->getHeader()) &&
@@ -876,7 +877,7 @@
   ++NumWidened;
 
   // Traverse the def-use chain using a worklist starting at the original IV.
-  assert(Processed.empty() && "expect initial state" );
+  assert(Widened.empty() && "expect initial state" );
 
   // Each worklist entry has a Narrow def-use link and Wide def.
   SmallVector<std::pair<Use *, Instruction *>, 8> NarrowIVUsers;
@@ -906,7 +907,7 @@
     if (NarrowDef->use_empty())
       DeadInsts.push_back(NarrowDef);
   }
-  return true;
+  return WidePhi;
 }
 
 void IndVarSimplify::EliminateIVComparison(ICmpInst *ICmp, Value *IVOperand) {
@@ -989,15 +990,144 @@
   }
 
   // Inform IVUsers about the new users.
-  if (Instruction *I = dyn_cast<Instruction>(Rem->getOperand(0)))
-    IU->AddUsersIfInteresting(I, IVPhi);
-
+  if (IU) {
+    if (Instruction *I = dyn_cast<Instruction>(Rem->getOperand(0)))
+      IU->AddUsersIfInteresting(I, IVPhi);
+  }
   DEBUG(dbgs() << "INDVARS: Simplified rem: " << *Rem << '\n');
   ++NumElimRem;
   Changed = true;
   DeadInsts.push_back(Rem);
 }
 
+/// EliminateIVUser - Eliminate an operation that consumes a simple IV and has
+/// no observable side-effect given the range of IV values.
+bool IndVarSimplify::EliminateIVUser(Instruction *UseInst,
+                                     Instruction *IVOperand) {
+  if (ICmpInst *ICmp = dyn_cast<ICmpInst>(UseInst)) {
+    EliminateIVComparison(ICmp, IVOperand);
+    return true;
+  }
+  if (BinaryOperator *Rem = dyn_cast<BinaryOperator>(UseInst)) {
+    bool IsSigned = Rem->getOpcode() == Instruction::SRem;
+    if (IsSigned || Rem->getOpcode() == Instruction::URem) {
+      EliminateIVRemainder(Rem, IVOperand, IsSigned, CurrIV);
+      return true;
+    }
+  }
+
+  // Eliminate any operation that SCEV can prove is an identity function.
+  if (!SE->isSCEVable(UseInst->getType()) ||
+      (SE->getSCEV(UseInst) != SE->getSCEV(IVOperand)))
+    return false;
+
+  UseInst->replaceAllUsesWith(IVOperand);
+
+  DEBUG(dbgs() << "INDVARS: Eliminated identity: " << *UseInst << '\n');
+  ++NumElimIdentity;
+  Changed = true;
+  DeadInsts.push_back(UseInst);
+  return true;
+}
+
+/// pushIVUsers - Add all uses of Def to the current IV's worklist.
+///
+void IndVarSimplify::pushIVUsers(Instruction *Def) {
+
+  for (Value::use_iterator UI = Def->use_begin(), E = Def->use_end();
+       UI != E; ++UI) {
+    Instruction *User = cast<Instruction>(*UI);
+
+    // Avoid infinite or exponential worklist processing.
+    // Also ensure unique worklist users.
+    if (Simplified.insert(User))
+      SimpleIVUsers.push_back(std::make_pair(User, Def));
+  }
+}
+
+/// isSimpleIVUser - Return true if this instruction generates a simple SCEV
+/// expression in terms of that IV.
+///
+/// This is similar to IVUsers' isInsteresting() but processes each instruction
+/// non-recursively when the operand is already known to be a simpleIVUser.
+///
+bool IndVarSimplify::isSimpleIVUser(Instruction *I, const Loop *L) {
+  if (!SE->isSCEVable(I->getType()))
+    return false;
+
+  // Get the symbolic expression for this instruction.
+  const SCEV *S = SE->getSCEV(I);
+
+  // Only consider affine recurrences.
+  const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(S);
+  if (AR && AR->getLoop() == L)
+    return true;
+
+  return false;
+}
+
+/// SimplifyIVUsersNoRewrite - Iteratively perform simplification on a worklist
+/// of IV users. Each successive simplification may push more users which may
+/// themselves be candidates for simplification.
+///
+/// The "NoRewrite" algorithm does not require IVUsers analysis. Instead, it
+/// simplifies instructions in-place during analysis. Rather than rewriting
+/// induction variables bottom-up from their users, it transforms a chain of
+/// IVUsers top-down, updating the IR only when it encouters a clear
+/// optimization opportunitiy. A SCEVExpander "Rewriter" instance is still
+/// needed, but only used to generate a new IV (phi) of wider type for sign/zero
+/// extend elimination.
+///
+/// Once DisableIVRewrite is default, LSR will be the only client of IVUsers.
+///
+void IndVarSimplify::SimplifyIVUsersNoRewrite(Loop *L, SCEVExpander &Rewriter) {
+  // Simplification is performed independently for each IV, as represented by a
+  // loop header phi. Each round of simplification first iterates through the
+  // SimplifyIVUsers worklist, then determines whether the current IV should be
+  // widened. Widening adds a new phi to LoopPhis, inducing another round of
+  // simplification on the wide IV.
+  SmallVector<PHINode*, 8> LoopPhis;
+  for (BasicBlock::iterator I = L->getHeader()->begin(); isa<PHINode>(I); ++I) {
+    LoopPhis.push_back(cast<PHINode>(I));
+  }
+  while (!LoopPhis.empty()) {
+    CurrIV = LoopPhis.pop_back_val();
+    Simplified.clear();
+    assert(SimpleIVUsers.empty() && "expect empty IV users list");
+
+    WideIVInfo WI;
+
+    pushIVUsers(CurrIV);
+
+    while (!SimpleIVUsers.empty()) {
+      Instruction *UseInst, *Operand;
+      tie(UseInst, Operand) = SimpleIVUsers.pop_back_val();
+
+      if (EliminateIVUser(UseInst, Operand)) {
+        pushIVUsers(Operand);
+        continue;
+      }
+      if (CastInst *Cast = dyn_cast<CastInst>(UseInst)) {
+        bool IsSigned = Cast->getOpcode() == Instruction::SExt;
+        if (IsSigned || Cast->getOpcode() == Instruction::ZExt) {
+          CollectExtend(Cast, IsSigned, WI, SE, TD);
+        }
+        continue;
+      }
+      if (isSimpleIVUser(UseInst, L)) {
+        pushIVUsers(UseInst);
+      }
+    }
+    if (WI.WidestNativeType) {
+      WidenIV Widener(CurrIV, WI, LI, SE, DT, DeadInsts);
+      if (PHINode *WidePhi = Widener.CreateWideIV(Rewriter)) {
+        Changed = true;
+        LoopPhis.push_back(WidePhi);
+      }
+    }
+  }
+}
+
 bool IndVarSimplify::runOnLoop(Loop *L, LPPassManager &LPM) {
   // If LoopSimplify form is not available, stay out of trouble. Some notes:
   //  - LSR currently only supports LoopSimplify-form loops. Indvars'
@@ -1010,12 +1140,15 @@
   if (!L->isLoopSimplifyForm())
     return false;
 
-  IU = &getAnalysis<IVUsers>();
+  if (!DisableIVRewrite)
+    IU = &getAnalysis<IVUsers>();
   LI = &getAnalysis<LoopInfo>();
   SE = &getAnalysis<ScalarEvolution>();
   DT = &getAnalysis<DominatorTree>();
   TD = getAnalysisIfAvailable<TargetData>();
 
+  CurrIV = NULL;
+  Simplified.clear();
   DeadInsts.clear();
   Changed = false;
 
@@ -1040,7 +1173,10 @@
     RewriteLoopExitValues(L, Rewriter);
 
   // Eliminate redundant IV users.
-  SimplifyIVUsers(Rewriter);
+  if (DisableIVRewrite)
+    SimplifyIVUsersNoRewrite(L, Rewriter);
+  else
+    SimplifyIVUsers(Rewriter);
 
   // Compute the type of the largest recurrence expression, and decide whether
   // a canonical induction variable should be inserted.
@@ -1146,7 +1282,7 @@
 
   // For completeness, inform IVUsers of the IV use in the newly-created
   // loop exit test instruction.
-  if (NewICmp)
+  if (NewICmp && IU)
     IU->AddUsersIfInteresting(cast<Instruction>(NewICmp->getOperand(0)),
                               IndVar);
 
@@ -1579,5 +1715,6 @@
   }
 
   // Add a new IVUsers entry for the newly-created integer PHI.
-  IU->AddUsersIfInteresting(NewPHI, NewPHI);
+  if (IU)
+    IU->AddUsersIfInteresting(NewPHI, NewPHI);
 }

Modified: llvm/trunk/test/Transforms/IndVarSimplify/iv-zext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/iv-zext.ll?rev=133502&r1=133501&r2=133502&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/iv-zext.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/iv-zext.ll Mon Jun 20 22:22:38 2011
@@ -1,4 +1,5 @@
 ; RUN: opt < %s -indvars -S | FileCheck %s
+; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s
 ; CHECK-NOT: and
 ; CHECK-NOT: zext
 



From nlewycky at google.com  Tue Jun 21 00:52:23 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Mon, 20 Jun 2011 22:52:23 -0700
Subject: [llvm-commits] patch: fix emission of npot vectors which need
	trailing padding
Message-ID: <BANLkTinhSx1XZV_6kDR8e3U=YP4V1rQuXA@mail.gmail.com>

Hi! This patch fixes an inconsistency that manifests like this:

typedef float float3 __attribute__((ext_vector_type(3)));

struct Foo {
  float3 x;
  float3 y;
};

struct Foo foo = { {0, 0, 0}, {1, 2, 3} };


This lowers to a struct with <3 x float>, which TargetData says is 16 bytes
on ARM. In LLVM IR, the first element becomes a constant aggregate zero,
which is emitted by looking at how many bytes it is (sixteen) and writing
out a zero-fill. The second element is emitted as three contiguous elements,
resulting in a total of 12 bytes.

The StructLayout object claims that each of those should be 16 bytes, so I
changed the AsmPrinter in CodeGen to apply padding to the end of an array to
match what TargetData thinks the length of the array is. Patch attached,
please review!

Nick
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From sabre at nondot.org  Tue Jun 21 01:00:04 2011
From: sabre at nondot.org (Chris Lattner)
Date: Mon, 20 Jun 2011 23:00:04 -0700
Subject: [llvm-commits] [llvm] r133412 - in /llvm/trunk:
	include/llvm/Constants.h lib/Analysis/ConstantFolding.cpp
	lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp
	lib/CodeGen/ShadowStackGC.cpp
	lib/Transforms/IPO/GlobalOpt.cpp lib/Transform
In-Reply-To: <BANLkTimBn5-=U7Re=p4gkh7CE3A7N5gf=Y+w6MD2teoEXDer6Q@mail.gmail.com>
References: <BANLkTimBn5-=U7Re=p4gkh7CE3A7N5gf=Y+w6MD2teoEXDer6Q@mail.gmail.com>
Message-ID: <6ACAF514-D83B-46F3-BBD9-13F295FB1FA2@nondot.org>


On Jun 20, 2011, at 8:43 AM, Jay Foad wrote:

>> It would be "really really nice" if the ConstantStruct::get and
>> ConstantVector::get methods didn't make temporary std::vectors.
> 
> How about this then?
> 
> Patch 1 extends ConstantUniqueMap with a new template parameter
> ValRefType, representing a const reference to ValType. Normally this
> would just be const ValType&, but when ValType is a std::vector, we
> want to use ArrayRef as the reference type.
> 
> I had to add a conversion operator to ArrayRef to get this to work. Is
> this reasonable? (I've only been using C++ for 15 years so I haven't
> really got the hang of it yet.) This also makes the existing
> ArrayRef::vec() somewhat redundant, but I didn't remove it.
> 
> Patches 2/3/4 tidy up the get() methods of ConstantVector/Array/Struct
> to use ArrayRef throughout.
> 
> Tested with "make all check-all", LLVM and Clang. I don't think
> llvm-gcc-4.2 or dragonegg need any changes, based on a quick grep.

Wow, looks great to me Jay, you're awesome!

-Chris

From clattner at apple.com  Tue Jun 21 01:01:26 2011
From: clattner at apple.com (Chris Lattner)
Date: Mon, 20 Jun 2011 23:01:26 -0700
Subject: [llvm-commits] Adding add.with.overflow intrinsic support
	to	CBackend.
In-Reply-To: <528BA51E-6300-4AB0-9EC9-345DC43CDD28@apple.com>
References: <20110620143801.6C0D72A6C124@llvm.org>
	<BANLkTim7oppnuuPYy-+QLtX9grqafusXFQ@mail.gmail.com>
	<BANLkTim5YF9ZkEMNXrba0dQhm4m3UHWS7w@mail.gmail.com>
	<528BA51E-6300-4AB0-9EC9-345DC43CDD28@apple.com>
Message-ID: <64948E02-0090-48D3-8427-72394EF982AF@apple.com>


On Jun 20, 2011, at 11:32 AM, Anna Zaks wrote:

> Hi,
> 
> Attached is a CBackend patch for review. It adds support for sadd.with.overflow and uadd.with.overflow intrinsics. Essentially, we emit implementation for each add.with.overflow intrinsic that occurs in the module. 
> 
> Issues are lack of support for arbitrary size integers and assumption about the two's compliment representation for integers (casts from signed to unsigned and backwards). However, it seems that these are the limitations of the current CBackend implementation as well.  
> 
> We know that the CBackend is no longer supported and might get completely rewritten, but this patch removes the known blockers for us and might be useful for someone else as well.

Sure, seems reasonable.  Please commit, thanks!

-Chris

From evan.cheng at apple.com  Tue Jun 21 01:01:08 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 21 Jun 2011 06:01:08 -0000
Subject: [llvm-commits] [llvm] r133503 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/Target/ARM/ARMInstrInfo.td
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMInstrThumb2.td
 test/CodeGen/ARM/rev.ll test/CodeGen/X86/bswap.ll
Message-ID: <20110621060108.6A5C22A6C12C@llvm.org>

Author: evancheng
Date: Tue Jun 21 01:01:08 2011
New Revision: 133503

URL: http://llvm.org/viewvc/llvm-project?rev=133503&view=rev
Log:
Teach dag combine to match halfword byteswap patterns.
1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
   => (bswap x) >> 16
2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
   => (rotl (bswap x) 16)

This allows us to eliminate most of the def : Pat patterns for ARM rev16
revsh instructions. It catches many more cases for ARM and x86.

rdar://9609108

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/CodeGen/ARM/rev.ll
    llvm/trunk/test/CodeGen/X86/bswap.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=133503&r1=133502&r2=133503&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Tue Jun 21 01:01:08 2011
@@ -238,6 +238,9 @@
     SDValue ConstantFoldBITCASTofBUILD_VECTOR(SDNode *, EVT);
     SDValue BuildSDIV(SDNode *N);
     SDValue BuildUDIV(SDNode *N);
+    SDValue MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
+                               bool DemandHighBits = true);
+    SDValue MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1);
     SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
     SDValue ReduceLoadWidth(SDNode *N);
     SDValue ReduceLoadOpStoreWidth(SDNode *N);
@@ -2512,6 +2515,244 @@
   return SDValue();
 }
 
+/// MatchBSwapHWord - Match (a >> 8) | (a << 8) as (bswap a) >> 16
+///
+SDValue DAGCombiner::MatchBSwapHWordLow(SDNode *N, SDValue N0, SDValue N1,
+                                        bool DemandHighBits) {
+  if (!LegalOperations)
+    return SDValue();
+
+  EVT VT = N->getValueType(0);
+  if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16)
+    return SDValue();
+  if (!TLI.isOperationLegal(ISD::BSWAP, VT))
+    return SDValue();
+
+  // Recognize (and (shl a, 8), 0xff), (and (srl a, 8), 0xff00)
+  bool LookPassAnd0 = false;
+  bool LookPassAnd1 = false;
+  if (N0.getOpcode() == ISD::AND && N0.getOperand(0).getOpcode() == ISD::SRL)
+      std::swap(N0, N1);
+  if (N1.getOpcode() == ISD::AND && N1.getOperand(0).getOpcode() == ISD::SHL)
+      std::swap(N0, N1);
+  if (N0.getOpcode() == ISD::AND) {
+    if (!N0.getNode()->hasOneUse())
+      return SDValue();
+    ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+    if (!N01C || N01C->getZExtValue() != 0xFF00)
+      return SDValue();
+    N0 = N0.getOperand(0);
+    LookPassAnd0 = true;
+  }
+
+  if (N1.getOpcode() == ISD::AND) {
+    if (!N1.getNode()->hasOneUse())
+      return SDValue();
+    ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
+    if (!N11C || N11C->getZExtValue() != 0xFF)
+      return SDValue();
+    N1 = N1.getOperand(0);
+    LookPassAnd1 = true;
+  }
+
+  if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL)
+    std::swap(N0, N1);
+  if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL)
+    return SDValue();
+  if (!N0.getNode()->hasOneUse() ||
+      !N1.getNode()->hasOneUse())
+    return SDValue();
+
+  ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+  ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
+  if (!N01C || !N11C)
+    return SDValue();
+  if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
+    return SDValue();
+
+  // Look for (shl (and a, 0xff), 8), (srl (and a, 0xff00), 8)
+  SDValue N00 = N0->getOperand(0);
+  if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
+    if (!N00.getNode()->hasOneUse())
+      return SDValue();
+    ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
+    if (!N001C || N001C->getZExtValue() != 0xFF)
+      return SDValue();
+    N00 = N00.getOperand(0);
+    LookPassAnd0 = true;
+  }
+
+  SDValue N10 = N1->getOperand(0);
+  if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
+    if (!N10.getNode()->hasOneUse())
+      return SDValue();
+    ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
+    if (!N101C || N101C->getZExtValue() != 0xFF00)
+      return SDValue();
+    N10 = N10.getOperand(0);
+    LookPassAnd1 = true;
+  }
+
+  if (N00 != N10)
+    return SDValue();
+
+  // Make sure everything beyond the low halfword is zero since the SRL 16
+  // will clear the top bits.
+  unsigned OpSizeInBits = VT.getSizeInBits();
+  if (DemandHighBits && OpSizeInBits > 16 &&
+      (!LookPassAnd0 || !LookPassAnd1) &&
+      !DAG.MaskedValueIsZero(N10, APInt::getHighBitsSet(OpSizeInBits, 16)))
+    return SDValue();
+  
+  SDValue Res = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT, N00);
+  if (OpSizeInBits > 16)
+    Res = DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, Res,
+                      DAG.getConstant(OpSizeInBits-16, getShiftAmountTy(VT)));
+  return Res;
+}
+
+/// isBSwapHWordElement - Return true if the specified node is an element
+/// that makes up a 32-bit packed halfword byteswap. i.e.
+/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
+static bool isBSwapHWordElement(SDValue N, SmallVector<SDNode*,4> &Parts) {
+  if (!N.getNode()->hasOneUse())
+    return false;
+
+  unsigned Opc = N.getOpcode();
+  if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
+    return false;
+
+  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
+  if (!N1C)
+    return false;
+
+  unsigned Num;
+  switch (N1C->getZExtValue()) {
+  default:
+    return false;
+  case 0xFF:       Num = 0; break;
+  case 0xFF00:     Num = 1; break;
+  case 0xFF0000:   Num = 2; break;
+  case 0xFF000000: Num = 3; break;
+  }
+
+  // Look for (x & 0xff) << 8 as well as ((x << 8) & 0xff00).
+  SDValue N0 = N.getOperand(0);
+  if (Opc == ISD::AND) {
+    if (Num == 0 || Num == 2) {
+      // (x >> 8) & 0xff
+      // (x >> 8) & 0xff0000
+      if (N0.getOpcode() != ISD::SRL)
+        return false;
+      ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+      if (!C || C->getZExtValue() != 8)
+        return false;
+    } else {
+      // (x << 8) & 0xff00
+      // (x << 8) & 0xff000000
+      if (N0.getOpcode() != ISD::SHL)
+        return false;
+      ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+      if (!C || C->getZExtValue() != 8)
+        return false;
+    }
+  } else if (Opc == ISD::SHL) {
+    // (x & 0xff) << 8
+    // (x & 0xff0000) << 8
+    if (Num != 0 && Num != 2)
+      return false;
+    ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
+    if (!C || C->getZExtValue() != 8)
+      return false;
+  } else { // Opc == ISD::SRL
+    // (x & 0xff00) >> 8
+    // (x & 0xff000000) >> 8
+    if (Num != 1 && Num != 3)
+      return false;
+    ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
+    if (!C || C->getZExtValue() != 8)
+      return false;
+  }
+
+  if (Parts[Num])
+    return false;
+
+  Parts[Num] = N0.getOperand(0).getNode();
+  return true;
+}
+
+/// MatchBSwapHWord - Match a 32-bit packed halfword bswap. That is
+/// ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0x00ff0000)<<8)|((x&0xff000000)>>8)
+/// => (rotl (bswap x), 16)
+SDValue DAGCombiner::MatchBSwapHWord(SDNode *N, SDValue N0, SDValue N1) {
+  if (!LegalOperations)
+    return SDValue();
+
+  EVT VT = N->getValueType(0);
+  if (VT != MVT::i32)
+    return SDValue();
+  if (!TLI.isOperationLegal(ISD::BSWAP, VT))
+    return SDValue();
+
+  SmallVector<SDNode*,4> Parts(4, (SDNode*)0);
+  // Look for either
+  // (or (or (and), (and)), (or (and), (and)))
+  // (or (or (or (and), (and)), (and)), (and))
+  if (N0.getOpcode() != ISD::OR)
+    return SDValue();
+  SDValue N00 = N0.getOperand(0);
+  SDValue N01 = N0.getOperand(1);
+
+  if (N1.getOpcode() == ISD::OR) {
+    // (or (or (and), (and)), (or (and), (and)))
+    SDValue N000 = N00.getOperand(0);
+    if (!isBSwapHWordElement(N000, Parts))
+      return SDValue();
+
+    SDValue N001 = N00.getOperand(1);
+    if (!isBSwapHWordElement(N001, Parts))
+      return SDValue();
+    SDValue N010 = N01.getOperand(0);
+    if (!isBSwapHWordElement(N010, Parts))
+      return SDValue();
+    SDValue N011 = N01.getOperand(1);
+    if (!isBSwapHWordElement(N011, Parts))
+      return SDValue();
+  } else {
+    // (or (or (or (and), (and)), (and)), (and))
+    if (!isBSwapHWordElement(N1, Parts))
+      return SDValue();
+    if (!isBSwapHWordElement(N01, Parts))
+      return SDValue();
+    if (N00.getOpcode() != ISD::OR)
+      return SDValue();
+    SDValue N000 = N00.getOperand(0);
+    if (!isBSwapHWordElement(N000, Parts))
+      return SDValue();
+    SDValue N001 = N00.getOperand(1);
+    if (!isBSwapHWordElement(N001, Parts))
+      return SDValue();
+  }
+
+  // Make sure the parts are all coming from the same node.
+  if (Parts[0] != Parts[1] || Parts[0] != Parts[2] || Parts[0] != Parts[3])
+    return SDValue();
+
+  SDValue BSwap = DAG.getNode(ISD::BSWAP, N->getDebugLoc(), VT,
+                              SDValue(Parts[0],0));
+
+  // Result of the bswap should be rotated by 16. If it's not legal, than
+  // do  (x << 16) | (x >> 16).
+  SDValue ShAmt = DAG.getConstant(16, getShiftAmountTy(VT));
+  if (TLI.isOperationLegalOrCustom(ISD::ROTL, VT))
+    return DAG.getNode(ISD::ROTL, N->getDebugLoc(), VT, BSwap, ShAmt);
+  else if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT))
+    return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt);
+  return DAG.getNode(ISD::OR, N->getDebugLoc(), VT,
+                     DAG.getNode(ISD::SHL, N->getDebugLoc(), VT, BSwap, ShAmt),
+                     DAG.getNode(ISD::SRL, N->getDebugLoc(), VT, BSwap, ShAmt));
+}
+
 SDValue DAGCombiner::visitOR(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
@@ -2547,6 +2788,15 @@
   // fold (or x, c) -> c iff (x & ~c) == 0
   if (N1C && DAG.MaskedValueIsZero(N0, ~N1C->getAPIntValue()))
     return N1;
+
+  // Recognize halfword bswaps as (bswap + rotl 16) or (bswap + shl 16)
+  SDValue BSwap = MatchBSwapHWord(N, N0, N1);
+  if (BSwap.getNode() != 0)
+    return BSwap;
+  BSwap = MatchBSwapHWordLow(N, N0, N1);
+  if (BSwap.getNode() != 0)
+    return BSwap;
+
   // reassociate or
   SDValue ROR = ReassociateOps(ISD::OR, N->getDebugLoc(), N0, N1);
   if (ROR.getNode() != 0)
@@ -4606,6 +4856,16 @@
     CombineTo(N0.getNode(), ExtLoad, ExtLoad.getValue(1));
     return SDValue(N, 0);   // Return N so it doesn't get rechecked!
   }
+
+  // Form (sext_inreg (bswap >> 16)) or (sext_inreg (rotl (bswap) 16))
+  if (EVTBits <= 16 && N0.getOpcode() == ISD::OR) {
+    SDValue BSwap = MatchBSwapHWordLow(N0.getNode(), N0.getOperand(0),
+                                       N0.getOperand(1), false);
+    if (BSwap.getNode() != 0)
+      return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
+                         BSwap, N1);
+  }
+
   return SDValue();
 }
 
@@ -5231,7 +5491,8 @@
   // fold (sint_to_fp c1) -> c1fp
   if (N0C && OpVT != MVT::ppcf128 &&
       // ...but only if the target supports immediate floating-point values
-      (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
+      (Level == llvm::Unrestricted ||
+       TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
     return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
 
   // If the input is a legal type, and SINT_TO_FP is not legal on this target,
@@ -5255,7 +5516,8 @@
   // fold (uint_to_fp c1) -> c1fp
   if (N0C && OpVT != MVT::ppcf128 &&
       // ...but only if the target supports immediate floating-point values
-      (Level == llvm::Unrestricted || TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
+      (Level == llvm::Unrestricted ||
+       TLI.isOperationLegalOrCustom(llvm::ISD::ConstantFP, VT)))
     return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
 
   // If the input is a legal type, and UINT_TO_FP is not legal on this target,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=133503&r1=133502&r2=133503&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Tue Jun 21 01:01:08 2011
@@ -3008,41 +3008,22 @@
               IIC_iUNAr, "rev", "\t$Rd, $Rm",
               [(set GPR:$Rd, (bswap GPR:$Rm))]>, Requires<[IsARM, HasV6]>;
 
+let AddedComplexity = 5 in
 def REV16 : AMiscA1I<0b01101011, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
                IIC_iUNAr, "rev16", "\t$Rd, $Rm",
-               [(set GPR:$Rd,
-                   (or (and (srl GPR:$Rm, (i32 8)), 0xFF),
-                       (or (and (shl GPR:$Rm, (i32 8)), 0xFF00),
-                           (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
-                               (and (shl GPR:$Rm, (i32 8)), 0xFF000000)))))]>,
+               [(set GPR:$Rd, (rotr (bswap GPR:$Rm), (i32 16)))]>,
                Requires<[IsARM, HasV6]>;
 
-def : ARMV6Pat<(or (or (or (and (srl GPR:$Rm, (i32 8)), 0xFF0000),
-                           (and (shl GPR:$Rm, (i32 8)), 0xFF000000)),
-                       (and (srl GPR:$Rm, (i32 8)), 0xFF)),
-                   (and (shl GPR:$Rm, (i32 8)), 0xFF00)),
-               (REV16 GPR:$Rm)>;
-
+let AddedComplexity = 5 in
 def REVSH : AMiscA1I<0b01101111, 0b1011, (outs GPR:$Rd), (ins GPR:$Rm),
                IIC_iUNAr, "revsh", "\t$Rd, $Rm",
-               [(set GPR:$Rd,
-                  (sext_inreg
-                    (or (srl GPR:$Rm, (i32 8)),
-                        (shl GPR:$Rm, (i32 8))), i16))]>,
+               [(set GPR:$Rd, (sra (bswap GPR:$Rm), (i32 16)))]>,
                Requires<[IsARM, HasV6]>;
 
-def : ARMV6Pat<(sext_inreg (or (srl (and GPR:$Rm, 0xFF00), (i32 8)),
-                               (shl GPR:$Rm, (i32 8))), i16),
-               (REVSH GPR:$Rm)>;
-
 def : ARMV6Pat<(or (sra (shl GPR:$Rm, (i32 24)), (i32 16)),
                    (and (srl GPR:$Rm, (i32 8)), 0xFF)),
                (REVSH GPR:$Rm)>;
 
-// Need the AddedComplexity or else MOVs + REV would be chosen.
-let AddedComplexity = 5 in
-def : ARMV6Pat<(sra (bswap GPR:$Rm), (i32 16)), (REVSH GPR:$Rm)>;
-
 def lsl_shift_imm : SDNodeXForm<imm, [{
   unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
   return CurDAG->getTargetConstant(Sh, MVT::i32);

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=133503&r1=133502&r2=133503&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Tue Jun 21 01:01:08 2011
@@ -1176,31 +1176,16 @@
   T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
                  IIC_iUNAr,
                  "rev16", "\t$Rd, $Rm",
-             [(set tGPR:$Rd,
-                   (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
-                       (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
-                           (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
-                               (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
+             [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
 
 def tREVSH :                    // A8.6.136
   T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
                  IIC_iUNAr,
                  "revsh", "\t$Rd, $Rm",
-                 [(set tGPR:$Rd,
-                       (sext_inreg
-                         (or (srl tGPR:$Rm, (i32 8)),
-                             (shl tGPR:$Rm, (i32 8))), i16))]>,
+                 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
                  Requires<[IsThumb, IsThumb1Only, HasV6]>;
 
-def : T1Pat<(sext_inreg (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
-                            (shl tGPR:$Rm, (i32 8))), i16),
-            (tREVSH tGPR:$Rm)>,
-      Requires<[IsThumb, IsThumb1Only, HasV6]>;
-
-def : T1Pat<(sra (bswap tGPR:$Rm), (i32 16)), (tREVSH tGPR:$Rm)>,
-      Requires<[IsThumb, IsThumb1Only, HasV6]>;
-
 // Rotate right register
 def tROR :                      // A8.6.139
   T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=133503&r1=133502&r2=133503&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun 21 01:01:08 2011
@@ -2587,35 +2587,16 @@
 
 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
                        "rev16", ".w\t$Rd, $Rm",
-                [(set rGPR:$Rd,
-                    (or (and (srl rGPR:$Rm, (i32 8)), 0xFF),
-                        (or (and (shl rGPR:$Rm, (i32 8)), 0xFF00),
-                            (or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
-                               (and (shl rGPR:$Rm, (i32 8)), 0xFF000000)))))]>;
-
-def : T2Pat<(or (or (or (and (srl rGPR:$Rm, (i32 8)), 0xFF0000),
-                        (and (shl rGPR:$Rm, (i32 8)), 0xFF000000)),
-                    (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
-                (and (shl rGPR:$Rm, (i32 8)), 0xFF00)),
-            (t2REV16 rGPR:$Rm)>;
+                [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>;
 
 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr,
                        "revsh", ".w\t$Rd, $Rm",
-                 [(set rGPR:$Rd,
-                    (sext_inreg
-                      (or (srl rGPR:$Rm, (i32 8)),
-                          (shl rGPR:$Rm, (i32 8))), i16))]>;
-
-def : T2Pat<(sext_inreg (or (srl (and rGPR:$Rm, 0xFF00), (i32 8)),
-                            (shl rGPR:$Rm, (i32 8))), i16),
-            (t2REVSH rGPR:$Rm)>;
+                 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>;
 
 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)),
-                   (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
+                (and (srl rGPR:$Rm, (i32 8)), 0xFF)),
             (t2REVSH rGPR:$Rm)>;
 
-def : T2Pat<(sra (bswap rGPR:$Rm), (i32 16)), (t2REVSH rGPR:$Rm)>;
-
 def t2PKHBT : T2ThreeReg<
             (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, shift_imm:$sh),
                   IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh",

Modified: llvm/trunk/test/CodeGen/ARM/rev.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/rev.ll?rev=133503&r1=133502&r2=133503&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/rev.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/rev.ll Tue Jun 21 01:01:08 2011
@@ -84,3 +84,43 @@
   %or10 = or i32 %or6, %shl
   ret i32 %or10
 }
+
+; rdar://9164521
+define i32 @test7(i32 %a) nounwind readnone {
+entry:
+; CHECK: test7
+; CHECK: rev r0, r0
+; CHECK: lsr r0, r0, #16
+  %and = lshr i32 %a, 8
+  %shr3 = and i32 %and, 255
+  %and2 = shl i32 %a, 8
+  %shl = and i32 %and2, 65280
+  %or = or i32 %shr3, %shl
+  ret i32 %or
+}
+
+define i32 @test8(i32 %a) nounwind readnone {
+entry:
+; CHECK: test8
+; CHECK: revsh r0, r0
+  %and = lshr i32 %a, 8
+  %shr4 = and i32 %and, 255
+  %and2 = shl i32 %a, 8
+  %or = or i32 %shr4, %and2
+  %sext = shl i32 %or, 16
+  %conv3 = ashr exact i32 %sext, 16
+  ret i32 %conv3
+}
+
+define zeroext i16 @test9(i16 zeroext %v) nounwind readnone {
+entry:
+; CHECK: test9
+; CHECK: rev r0, r0
+; CHECK: lsr r0, r0, #16
+  %conv = zext i16 %v to i32
+  %shr4 = lshr i32 %conv, 8
+  %shl = shl nuw nsw i32 %conv, 8
+  %or = or i32 %shr4, %shl
+  %conv3 = trunc i32 %or to i16
+  ret i16 %conv3
+}

Modified: llvm/trunk/test/CodeGen/X86/bswap.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bswap.ll?rev=133503&r1=133502&r2=133503&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bswap.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bswap.ll Tue Jun 21 01:01:08 2011
@@ -1,8 +1,6 @@
 ; bswap should be constant folded when it is passed a constant argument
 
-; RUN: llc < %s -march=x86 | \
-; RUN:   grep bswapl | count 3
-; RUN: llc < %s -march=x86 | grep rolw | count 1
+; RUN: llc < %s -march=x86 | FileCheck %s
 
 declare i16 @llvm.bswap.i16(i16)
 
@@ -11,17 +9,51 @@
 declare i64 @llvm.bswap.i64(i64)
 
 define i16 @W(i16 %A) {
+; CHECK: W:
+; CHECK: rolw $8, %ax
         %Z = call i16 @llvm.bswap.i16( i16 %A )         ; <i16> [#uses=1]
         ret i16 %Z
 }
 
 define i32 @X(i32 %A) {
+; CHECK: X:
+; CHECK: bswapl %eax
         %Z = call i32 @llvm.bswap.i32( i32 %A )         ; <i32> [#uses=1]
         ret i32 %Z
 }
 
 define i64 @Y(i64 %A) {
+; CHECK: Y:
+; CHECK: bswapl %eax
+; CHECK: bswapl %edx
         %Z = call i64 @llvm.bswap.i64( i64 %A )         ; <i64> [#uses=1]
         ret i64 %Z
 }
 
+; rdar://9164521
+define i32 @test1(i32 %a) nounwind readnone {
+entry:
+; CHECK: test1
+; CHECK: bswapl %eax
+; CHECK: shrl $16, %eax
+  %and = lshr i32 %a, 8
+  %shr3 = and i32 %and, 255
+  %and2 = shl i32 %a, 8
+  %shl = and i32 %and2, 65280
+  %or = or i32 %shr3, %shl
+  ret i32 %or
+}
+
+define i32 @test2(i32 %a) nounwind readnone {
+entry:
+; CHECK: test2
+; CHECK: bswapl %eax
+; CHECK: sarl $16, %eax
+  %and = lshr i32 %a, 8
+  %shr4 = and i32 %and, 255
+  %and2 = shl i32 %a, 8
+  %or = or i32 %shr4, %and2
+  %sext = shl i32 %or, 16
+  %conv3 = ashr exact i32 %sext, 16
+  ret i32 %conv3
+}



From sabre at nondot.org  Tue Jun 21 01:22:34 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Jun 2011 06:22:34 -0000
Subject: [llvm-commits] [llvm] r133504 -
	/llvm/trunk/include/llvm/ADT/StringMap.h
Message-ID: <20110621062234.20F6E2A6C12C@llvm.org>

Author: lattner
Date: Tue Jun 21 01:22:33 2011
New Revision: 133504

URL: http://llvm.org/viewvc/llvm-project?rev=133504&view=rev
Log:
use the MapEntryTy typedef instead of writing it out long form,
add some fixme's about methods that should be removed.

Merged from type-system-rewrite.

Modified:
    llvm/trunk/include/llvm/ADT/StringMap.h

Modified: llvm/trunk/include/llvm/ADT/StringMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringMap.h?rev=133504&r1=133503&r2=133504&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/StringMap.h (original)
+++ llvm/trunk/include/llvm/ADT/StringMap.h Tue Jun 21 01:22:33 2011
@@ -307,7 +307,7 @@
     return ValueTy();
   }
 
-  ValueTy& operator[](StringRef Key) {
+  ValueTy &operator[](StringRef Key) {
     return GetOrCreateValue(Key).getValue();
   }
 
@@ -355,8 +355,7 @@
   /// exists, return it.  Otherwise, default construct a value, insert it, and
   /// return.
   template <typename InitTy>
-  StringMapEntry<ValueTy> &GetOrCreateValue(StringRef Key,
-                                            InitTy Val) {
+  MapEntryTy &GetOrCreateValue(StringRef Key, InitTy Val) {
     unsigned BucketNo = LookupBucketFor(Key);
     ItemBucket &Bucket = TheTable[BucketNo];
     if (Bucket.Item && Bucket.Item != getTombstoneVal())
@@ -378,19 +377,19 @@
     return *NewItem;
   }
 
-  StringMapEntry<ValueTy> &GetOrCreateValue(StringRef Key) {
+  MapEntryTy &GetOrCreateValue(StringRef Key) {
     return GetOrCreateValue(Key, ValueTy());
   }
 
+  // FIXME: Remove this method.
   template <typename InitTy>
-  StringMapEntry<ValueTy> &GetOrCreateValue(const char *KeyStart,
-                                            const char *KeyEnd,
-                                            InitTy Val) {
+  MapEntryTy &GetOrCreateValue(const char *KeyStart, const char *KeyEnd,
+                               InitTy Val) {
     return GetOrCreateValue(StringRef(KeyStart, KeyEnd - KeyStart), Val);
   }
 
-  StringMapEntry<ValueTy> &GetOrCreateValue(const char *KeyStart,
-                                            const char *KeyEnd) {
+  // FIXME: Remove this method.
+  MapEntryTy &GetOrCreateValue(const char *KeyStart, const char *KeyEnd) {
     return GetOrCreateValue(StringRef(KeyStart, KeyEnd - KeyStart));
   }
 



From clattner at apple.com  Tue Jun 21 01:56:25 2011
From: clattner at apple.com (Chris Lattner)
Date: Mon, 20 Jun 2011 23:56:25 -0700
Subject: [llvm-commits] [llvm] r133503 - in /llvm/trunk:
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/Target/ARM/ARMInstrInfo.td
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMInstrThumb2.td
 test/CodeGen/ARM/rev.ll test/CodeGen/X86/bswap.ll
In-Reply-To: <20110621060108.6A5C22A6C12C@llvm.org>
References: <20110621060108.6A5C22A6C12C@llvm.org>
Message-ID: <F0F3C3B5-FD3C-4BAA-8EFD-50F374CB9144@apple.com>


On Jun 20, 2011, at 11:01 PM, Evan Cheng wrote:

> Author: evancheng
> Date: Tue Jun 21 01:01:08 2011
> New Revision: 133503
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133503&view=rev
> Log:
> Teach dag combine to match halfword byteswap patterns.
> 1. (((x) & 0xFF00) >> 8) | (((x) & 0x00FF) << 8)
>   => (bswap x) >> 16
> 2. ((x&0xff)<<8)|((x&0xff00)>>8)|((x&0xff000000)>>8)|((x&0x00ff0000)<<8))
>   => (rotl (bswap x) 16)
> 
> This allows us to eliminate most of the def : Pat patterns for ARM rev16
> revsh instructions. It catches many more cases for ARM and x86.

Nice!

-Chris

From jay.foad at gmail.com  Tue Jun 21 02:22:18 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 21 Jun 2011 08:22:18 +0100
Subject: [llvm-commits] [llvm] r133412 - in /llvm/trunk:
 include/llvm/Constants.h lib/Analysis/ConstantFolding.cpp
 lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp
 lib/CodeGen/ShadowStackGC.cpp lib/Transforms/IPO/GlobalOpt.cpp
 lib/Transform
In-Reply-To: <6ACAF514-D83B-46F3-BBD9-13F295FB1FA2@nondot.org>
References: <BANLkTimBn5-=U7Re=p4gkh7CE3A7N5gf=Y+w6MD2teoEXDer6Q@mail.gmail.com>
	<6ACAF514-D83B-46F3-BBD9-13F295FB1FA2@nondot.org>
Message-ID: <BANLkTi=KOpcn0CwHfObMA+Z7eakrgTWafwBPBt2XVjR36GTphA@mail.gmail.com>

>> Patch 1 extends ConstantUniqueMap with a new template parameter
>> ValRefType, representing a const reference to ValType. Normally this
>> would just be const ValType&, but when ValType is a std::vector, we
>> want to use ArrayRef as the reference type.

> Wow, looks great to me Jay

Just to double check, are you OK with me adding the conversion operator

  ArrayRef<T>::operator std::vector<T>() const;

And should I remove the now redundant method which just did the same thing:

  std::vector<T> ArrayRef<T>::vec() const;

?

Thanks,
Jay.

From jay.foad at gmail.com  Tue Jun 21 03:33:49 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 21 Jun 2011 08:33:49 -0000
Subject: [llvm-commits] [llvm] r133509 -
 /llvm/trunk/test/Transforms/LoopDeletion/2011-06-21-phioperands.ll
Message-ID: <20110621083349.391362A6C12C@llvm.org>

Author: foad
Date: Tue Jun 21 03:33:49 2011
New Revision: 133509

URL: http://llvm.org/viewvc/llvm-project?rev=133509&view=rev
Log:
Add a reduced test case for the buildbot failure (clang self-hosted
build) caused by r133435.

Added:
    llvm/trunk/test/Transforms/LoopDeletion/2011-06-21-phioperands.ll

Added: llvm/trunk/test/Transforms/LoopDeletion/2011-06-21-phioperands.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopDeletion/2011-06-21-phioperands.ll?rev=133509&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/LoopDeletion/2011-06-21-phioperands.ll (added)
+++ llvm/trunk/test/Transforms/LoopDeletion/2011-06-21-phioperands.ll Tue Jun 21 03:33:49 2011
@@ -0,0 +1,182 @@
+; RUN: opt %s -loop-deletion -disable-output
+
+target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
+
+%0 = type { %"class.llvm::SmallVectorImpl", [1 x %"union.llvm::SmallVectorBase::U"] }
+%"class.clang::SourceLocation" = type { i32 }
+%"class.clang::driver::Arg" = type { %"class.clang::driver::Option"*, %"class.clang::driver::Arg"*, i32, i8, %0 }
+%"class.clang::driver::Option" = type { i32 (...)**, i32, %"class.clang::SourceLocation", i8*, %"class.clang::driver::OptionGroup"*, %"class.clang::driver::Option"*, i8 }
+%"class.clang::driver::OptionGroup" = type { %"class.clang::driver::Option" }
+%"class.llvm::SmallVectorBase" = type { i8*, i8*, i8*, %"union.llvm::SmallVectorBase::U" }
+%"class.llvm::SmallVectorImpl" = type { %"class.llvm::SmallVectorTemplateBase" }
+%"class.llvm::SmallVectorTemplateBase" = type { %"class.llvm::SmallVectorTemplateCommon" }
+%"class.llvm::SmallVectorTemplateCommon" = type { %"class.llvm::SmallVectorBase" }
+%"union.llvm::SmallVectorBase::U" = type { x86_fp80 }
+
+define void @_ZNK5clang6driver7ArgList20AddAllArgsTranslatedERN4llvm11SmallVectorIPKcLj16EEENS0_12OptSpecifierES5_b(i1 zeroext %Joined) nounwind align 2 {
+entry:
+  br i1 undef, label %entry.split.us, label %entry.entry.split_crit_edge
+
+entry.entry.split_crit_edge:                      ; preds = %entry
+  br label %entry.split
+
+entry.split.us:                                   ; preds = %entry
+  br label %for.cond.i14.us
+
+for.cond.i14.us:                                  ; preds = %for.inc.i38.us, %entry.split.us
+  br i1 true, label %for.cond.i50.us-lcssa.us, label %if.end.i23.us
+
+for.inc.i38.us:                                   ; preds = %if.end.i23.us
+  br label %for.cond.i14.us
+
+if.end.i23.us:                                    ; preds = %for.cond.i14.us
+  br i1 true, label %for.cond.i50.us-lcssa.us, label %for.inc.i38.us
+
+for.cond.i50.us-lcssa.us:                         ; preds = %if.end.i23.us, %for.cond.i14.us
+  br label %for.cond.i50
+
+entry.split:                                      ; preds = %entry.entry.split_crit_edge
+  br label %for.cond.i14
+
+for.cond.i14:                                     ; preds = %for.inc.i38, %entry.split
+  br i1 undef, label %for.cond.i50.us-lcssa, label %if.end.i23
+
+if.end.i23:                                       ; preds = %for.cond.i14
+  br i1 undef, label %for.cond.i50.us-lcssa, label %for.inc.i38
+
+for.inc.i38:                                      ; preds = %if.end.i23
+  br label %for.cond.i14
+
+for.cond.i50.us-lcssa:                            ; preds = %if.end.i23, %for.cond.i14
+  br label %for.cond.i50
+
+for.cond.i50:                                     ; preds = %for.cond.i50.us-lcssa, %for.cond.i50.us-lcssa.us
+  br label %for.cond
+
+for.cond.loopexit.us-lcssa:                       ; preds = %if.end.i, %for.cond.i
+  br label %for.cond.loopexit
+
+for.cond.loopexit:                                ; preds = %for.cond.loopexit.us-lcssa.us, %for.cond.loopexit.us-lcssa
+  br label %for.cond
+
+for.cond:                                         ; preds = %for.cond.loopexit, %for.cond.i50
+  br i1 undef, label %for.end, label %for.body
+
+for.body:                                         ; preds = %for.cond
+  br i1 %Joined, label %if.then, label %if.else
+
+if.then:                                          ; preds = %for.body
+  br i1 undef, label %cond.false.i.i, label %_ZN4llvm9StringRefC1EPKc.exit
+
+cond.false.i.i:                                   ; preds = %if.then
+  unreachable
+
+_ZN4llvm9StringRefC1EPKc.exit:                    ; preds = %if.then
+  br i1 undef, label %_ZNK5clang6driver3Arg8getValueERKNS0_7ArgListEj.exit, label %cond.false.i.i91
+
+cond.false.i.i91:                                 ; preds = %_ZN4llvm9StringRefC1EPKc.exit
+  unreachable
+
+_ZNK5clang6driver3Arg8getValueERKNS0_7ArgListEj.exit: ; preds = %_ZN4llvm9StringRefC1EPKc.exit
+  br i1 undef, label %cond.false.i.i.i, label %if.end13.i.i.i.i
+
+if.end13.i.i.i.i:                                 ; preds = %_ZNK5clang6driver3Arg8getValueERKNS0_7ArgListEj.exit
+  br i1 undef, label %land.lhs.true16.i.i.i.i, label %if.end19.i.i.i.i
+
+land.lhs.true16.i.i.i.i:                          ; preds = %if.end13.i.i.i.i
+  br i1 undef, label %cond.false.i.i.i, label %_ZNK4llvm5Twine8isBinaryEv.exit8.i.i.i.i
+
+_ZNK4llvm5Twine8isBinaryEv.exit8.i.i.i.i:         ; preds = %land.lhs.true16.i.i.i.i
+  br i1 undef, label %cond.false.i.i.i, label %if.end19.i.i.i.i
+
+if.end19.i.i.i.i:                                 ; preds = %_ZNK4llvm5Twine8isBinaryEv.exit8.i.i.i.i, %if.end13.i.i.i.i
+  br i1 undef, label %land.lhs.true22.i.i.i.i, label %_ZN4llvmplERKNS_9StringRefEPKc.exit
+
+land.lhs.true22.i.i.i.i:                          ; preds = %if.end19.i.i.i.i
+  br i1 undef, label %cond.false.i.i.i, label %_ZNK4llvm5Twine8isBinaryEv.exit.i.i.i.i
+
+_ZNK4llvm5Twine8isBinaryEv.exit.i.i.i.i:          ; preds = %land.lhs.true22.i.i.i.i
+  br i1 undef, label %cond.false.i.i.i, label %_ZN4llvmplERKNS_9StringRefEPKc.exit
+
+cond.false.i.i.i:                                 ; preds = %_ZNK4llvm5Twine8isBinaryEv.exit.i.i.i.i, %land.lhs.true22.i.i.i.i, %_ZNK4llvm5Twine8isBinaryEv.exit8.i.i.i.i, %land.lhs.true16.i.i.i.i, %_ZNK5clang6driver3Arg8getValueERKNS0_7ArgListEj.exit
+  unreachable
+
+_ZN4llvmplERKNS_9StringRefEPKc.exit:              ; preds = %_ZNK4llvm5Twine8isBinaryEv.exit.i.i.i.i, %if.end19.i.i.i.i
+  br i1 undef, label %Retry.i, label %if.end.i99
+
+Retry.i:                                          ; preds = %if.end.i99, %_ZN4llvmplERKNS_9StringRefEPKc.exit
+  br i1 undef, label %_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit, label %new.notnull.i
+
+new.notnull.i:                                    ; preds = %Retry.i
+  br label %_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit
+
+if.end.i99:                                       ; preds = %_ZN4llvmplERKNS_9StringRefEPKc.exit
+  br label %Retry.i
+
+_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit: ; preds = %new.notnull.i, %Retry.i
+  br label %for.cond.i.preheader
+
+if.else:                                          ; preds = %for.body
+  br i1 undef, label %Retry.i108, label %if.end.i113
+
+Retry.i108:                                       ; preds = %if.end.i113, %if.else
+  br i1 undef, label %_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit114, label %new.notnull.i110
+
+new.notnull.i110:                                 ; preds = %Retry.i108
+  br label %_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit114
+
+if.end.i113:                                      ; preds = %if.else
+  br label %Retry.i108
+
+_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit114: ; preds = %new.notnull.i110, %Retry.i108
+  br i1 undef, label %_ZNK5clang6driver3Arg8getValueERKNS0_7ArgListEj.exit125, label %cond.false.i.i123
+
+cond.false.i.i123:                                ; preds = %_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit114
+  unreachable
+
+_ZNK5clang6driver3Arg8getValueERKNS0_7ArgListEj.exit125: ; preds = %_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit114
+  br i1 undef, label %Retry.i134, label %if.end.i139
+
+Retry.i134:                                       ; preds = %if.end.i139, %_ZNK5clang6driver3Arg8getValueERKNS0_7ArgListEj.exit125
+  br i1 undef, label %_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit140, label %new.notnull.i136
+
+new.notnull.i136:                                 ; preds = %Retry.i134
+  br label %_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit140
+
+if.end.i139:                                      ; preds = %_ZNK5clang6driver3Arg8getValueERKNS0_7ArgListEj.exit125
+  br label %Retry.i134
+
+_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit140: ; preds = %new.notnull.i136, %Retry.i134
+  br label %for.cond.i.preheader
+
+for.cond.i.preheader:                             ; preds = %_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit140, %_ZN4llvm15SmallVectorImplIPKcE9push_backERKS2_.exit
+  br i1 undef, label %for.cond.i.preheader.split.us, label %for.cond.i.preheader.for.cond.i.preheader.split_crit_edge
+
+for.cond.i.preheader.for.cond.i.preheader.split_crit_edge: ; preds = %for.cond.i.preheader
+  br label %for.cond.i.preheader.split
+
+for.cond.i.preheader.split.us:                    ; preds = %for.cond.i.preheader
+  br label %for.cond.i.us
+
+for.cond.i.us:                                    ; preds = %if.end.i.us, %for.cond.i.preheader.split.us
+  br i1 true, label %for.cond.loopexit.us-lcssa.us, label %if.end.i.us
+
+if.end.i.us:                                      ; preds = %for.cond.i.us
+  br i1 true, label %for.cond.loopexit.us-lcssa.us, label %for.cond.i.us
+
+for.cond.loopexit.us-lcssa.us:                    ; preds = %if.end.i.us, %for.cond.i.us
+  %tmp178218.us.lcssa = phi %"class.clang::driver::Arg"** [ undef, %if.end.i.us ], [ undef, %for.cond.i.us ]
+  br label %for.cond.loopexit
+
+for.cond.i.preheader.split:                       ; preds = %for.cond.i.preheader.for.cond.i.preheader.split_crit_edge
+  br label %for.cond.i
+
+for.cond.i:                                       ; preds = %if.end.i, %for.cond.i.preheader.split
+  br i1 undef, label %for.cond.loopexit.us-lcssa, label %if.end.i
+
+if.end.i:                                         ; preds = %for.cond.i
+  br i1 undef, label %for.cond.loopexit.us-lcssa, label %for.cond.i
+
+for.end:                                          ; preds = %for.cond
+  ret void
+}



From renato.golin at arm.com  Tue Jun 21 03:45:09 2011
From: renato.golin at arm.com (Renato Golin)
Date: Tue, 21 Jun 2011 09:45:09 +0100
Subject: [llvm-commits] patch: fix emission of npot vectors which need
 trailing padding
In-Reply-To: <BANLkTinhSx1XZV_6kDR8e3U=YP4V1rQuXA@mail.gmail.com>
References: <BANLkTinhSx1XZV_6kDR8e3U=YP4V1rQuXA@mail.gmail.com>
Message-ID: <BANLkTikqZYc=LyAbboTr=xHO2adgD4OfMw@mail.gmail.com>

On 21 June 2011 06:52, Nick Lewycky <nlewycky at google.com> wrote:
> This lowers to a struct with <3 x float>, which TargetData says is 16 bytes
> on ARM.

Hi Nick,

This only makes sense for ARM with NEON/VFP, unless selection-DAG
identifies it and remove the padding to avoid extra instructions being
generated for the CPU when NEON/VFP is not present.

Anyone knows if that's the case?


> In LLVM IR, the first element becomes a constant aggregate zero,
> which is emitted by looking at how many bytes it is (sixteen) and writing
> out a zero-fill. The second element is emitted as three contiguous elements,
> resulting in a total of 12 bytes.

I agree, we should have consistency here.


> The StructLayout object claims that each of those should be 16 bytes, so I
> changed the AsmPrinter in CodeGen to apply padding to the end of an array to
> match what TargetData thinks the length of the array is. Patch attached,
> please review!

Not sure you changed the right place. I agree that alignment is
important for all platforms but I wouldn't make such an assumption
without a set of tests for each one of them.

If everyone is happy that such padding needs to be dealt with by the
generic CodeGen, I won't oppose, but would be good to have at least
one test for each major architecture.

Otherwise, if you move it to ARMAsmPrinter, I still suggest you to
write a simple IR-to-ASM test and check data sizes.

cheers,
--renato

From baldrick at free.fr  Tue Jun 21 03:43:19 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 21 Jun 2011 08:43:19 -0000
Subject: [llvm-commits] [dragonegg] r133510 - /dragonegg/trunk/www/index.html
Message-ID: <20110621084319.5EF502A6C12C@llvm.org>

Author: baldrick
Date: Tue Jun 21 03:43:19 2011
New Revision: 133510

URL: http://llvm.org/viewvc/llvm-project?rev=133510&view=rev
Log:
Add debian note to web-page.

Modified:
    dragonegg/trunk/www/index.html

Modified: dragonegg/trunk/www/index.html
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/www/index.html?rev=133510&r1=133509&r2=133510&view=diff
==============================================================================
--- dragonegg/trunk/www/index.html (original)
+++ dragonegg/trunk/www/index.html Tue Jun 21 03:43:19 2011
@@ -281,7 +281,9 @@
      <pre>	svn co http://llvm.org/svn/llvm-project/llvm/trunk llvm</pre>
   <p><a href="http://llvm.org/docs/GettingStarted.html">Build LLVM</a> in the
   usual way.</p>
-  <p>Install gcc-4.5 or gcc-4.6 (you do not need to build your own copy).</p>
+  <p>Install gcc-4.5 or gcc-4.6 (you do not need to build your own copy).  On
+  debian and ubuntu you need to install the corresponding plugin-dev package
+  (gcc-4.5-plugin-dev or gcc-4.6-plugin-dev).</p>
   <p>Doing</p>
      <pre>	GCC=path_to_just_installed_gcc make</pre>
   <p>in the <tt>dragonegg</tt> directory should then build <tt>dragonegg.so</tt>.



From jay.foad at gmail.com  Tue Jun 21 05:02:43 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 21 Jun 2011 10:02:43 -0000
Subject: [llvm-commits] [llvm] r133512 -
	/llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp
Message-ID: <20110621100243.C70E02A6C12C@llvm.org>

Author: foad
Date: Tue Jun 21 05:02:43 2011
New Revision: 133512

URL: http://llvm.org/viewvc/llvm-project?rev=133512&view=rev
Log:
Don't use PN->replaceUsesOfWith() to change a PHINode's incoming blocks,
because it won't work after my phi operand changes, because the incoming
blocks will no longer be Uses.

Modified:
    llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp?rev=133512&r1=133511&r2=133512&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp Tue Jun 21 05:02:43 2011
@@ -190,7 +190,9 @@
   BasicBlock* exitingBlock = exitingBlocks[0];
   BasicBlock::iterator BI = exitBlock->begin();
   while (PHINode* P = dyn_cast<PHINode>(BI)) {
-    P->replaceUsesOfWith(exitingBlock, preheader);
+    int j = P->getBasicBlockIndex(exitingBlock);
+    assert(j >= 0 && "Can't find exiting block in exit block's phi node!");
+    P->setIncomingBlock(j, preheader);
     for (unsigned i = 1; i < exitingBlocks.size(); ++i)
       P->removeIncomingValue(exitingBlocks[i]);
     ++BI;



From jay.foad at gmail.com  Tue Jun 21 05:33:19 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 21 Jun 2011 10:33:19 -0000
Subject: [llvm-commits] [llvm] r133513 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/Target/CppBackend/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
Message-ID: <20110621103319.B0D332A6C12C@llvm.org>

Author: foad
Date: Tue Jun 21 05:33:19 2011
New Revision: 133513

URL: http://llvm.org/viewvc/llvm-project?rev=133513&view=rev
Log:
Reinstate r133435 and r133449 (reverted in r133499) now that the clang
self-hosted build failure has been fixed (r133512).

Modified:
    llvm/trunk/include/llvm/BasicBlock.h
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/CFG.h
    llvm/trunk/include/llvm/Use.h
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
    llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
    llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp
    llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
    llvm/trunk/lib/Transforms/Utils/Local.cpp
    llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
    llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
    llvm/trunk/lib/VMCore/BasicBlock.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp
    llvm/trunk/lib/VMCore/User.cpp
    llvm/trunk/lib/VMCore/Value.cpp
    llvm/trunk/lib/VMCore/Verifier.cpp

Modified: llvm/trunk/include/llvm/BasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BasicBlock.h?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/include/llvm/BasicBlock.h (original)
+++ llvm/trunk/include/llvm/BasicBlock.h Tue Jun 21 05:33:19 2011
@@ -110,7 +110,7 @@
         Function *getParent()       { return Parent; }
 
   /// use_back - Specialize the methods defined in Value, as we know that an
-  /// BasicBlock can only be used by Users (specifically PHI nodes, terminators,
+  /// BasicBlock can only be used by Users (specifically terminators
   /// and BlockAddress's).
   User       *use_back()       { return cast<User>(*use_begin());}
   const User *use_back() const { return cast<User>(*use_begin());}
@@ -248,6 +248,10 @@
   /// other than direct branches, switches, etc. to it.
   bool hasAddressTaken() const { return getSubclassDataFromValue() != 0; }
 
+  /// replaceSuccessorsPhiUsesWith - Update all phi nodes in all our successors
+  /// to refer to basic block New instead of to us.
+  void replaceSuccessorsPhiUsesWith(BasicBlock *New);
+
 private:
   /// AdjustBlockAddressRefCount - BasicBlock stores the number of BlockAddress
   /// objects using it.  This is almost always 0, sometimes one, possibly but

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Tue Jun 21 05:33:19 2011
@@ -1814,7 +1814,7 @@
   explicit PHINode(const Type *Ty, unsigned NumReservedValues,
                    const Twine &NameStr = "", Instruction *InsertBefore = 0)
     : Instruction(Ty, Instruction::PHI, 0, 0, InsertBefore),
-      ReservedSpace(NumReservedValues * 2) {
+      ReservedSpace(NumReservedValues) {
     setName(NameStr);
     OperandList = allocHungoffUses(ReservedSpace);
   }
@@ -1822,11 +1822,16 @@
   PHINode(const Type *Ty, unsigned NumReservedValues, const Twine &NameStr,
           BasicBlock *InsertAtEnd)
     : Instruction(Ty, Instruction::PHI, 0, 0, InsertAtEnd),
-      ReservedSpace(NumReservedValues * 2) {
+      ReservedSpace(NumReservedValues) {
     setName(NameStr);
     OperandList = allocHungoffUses(ReservedSpace);
   }
 protected:
+  // allocHungoffUses - this is more complicated than the generic
+  // User::allocHungoffUses, because we have to allocate Uses for the incoming
+  // values and pointers to the incoming blocks, all in one allocation.
+  Use *allocHungoffUses(unsigned) const;
+
   virtual PHINode *clone_impl() const;
 public:
   /// Constructors - NumReservedValues is a hint for the number of incoming
@@ -1845,32 +1850,55 @@
   /// Provide fast operand accessors
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
 
+  // Block iterator interface. This provides access to the list of incoming
+  // basic blocks, which parallels the list of incoming values.
+
+  typedef BasicBlock **block_iterator;
+  typedef BasicBlock * const *const_block_iterator;
+
+  block_iterator block_begin() {
+    Use::UserRef *ref =
+      reinterpret_cast<Use::UserRef*>(op_begin() + ReservedSpace);
+    return reinterpret_cast<block_iterator>(ref + 1);
+  }
+
+  const_block_iterator block_begin() const {
+    const Use::UserRef *ref =
+      reinterpret_cast<const Use::UserRef*>(op_begin() + ReservedSpace);
+    return reinterpret_cast<const_block_iterator>(ref + 1);
+  }
+
+  block_iterator block_end() {
+    return block_begin() + getNumOperands();
+  }
+
+  const_block_iterator block_end() const {
+    return block_begin() + getNumOperands();
+  }
+
   /// getNumIncomingValues - Return the number of incoming edges
   ///
-  unsigned getNumIncomingValues() const { return getNumOperands()/2; }
+  unsigned getNumIncomingValues() const { return getNumOperands(); }
 
   /// getIncomingValue - Return incoming value number x
   ///
   Value *getIncomingValue(unsigned i) const {
-    assert(i*2 < getNumOperands() && "Invalid value number!");
-    return getOperand(i*2);
+    return getOperand(i);
   }
   void setIncomingValue(unsigned i, Value *V) {
-    assert(i*2 < getNumOperands() && "Invalid value number!");
-    setOperand(i*2, V);
+    setOperand(i, V);
   }
   static unsigned getOperandNumForIncomingValue(unsigned i) {
-    return i*2;
+    return i;
   }
   static unsigned getIncomingValueNumForOperand(unsigned i) {
-    assert(i % 2 == 0 && "Invalid incoming-value operand index!");
-    return i/2;
+    return i;
   }
 
   /// getIncomingBlock - Return incoming basic block number @p i.
   ///
   BasicBlock *getIncomingBlock(unsigned i) const {
-    return cast<BasicBlock>(getOperand(i*2+1));
+    return block_begin()[i];
   }
 
   /// getIncomingBlock - Return incoming basic block corresponding
@@ -1878,7 +1906,7 @@
   ///
   BasicBlock *getIncomingBlock(const Use &U) const {
     assert(this == U.getUser() && "Iterator doesn't point to PHI's Uses?");
-    return cast<BasicBlock>((&U + 1)->get());
+    return getIncomingBlock(&U - op_begin());
   }
 
   /// getIncomingBlock - Return incoming basic block corresponding
@@ -1889,16 +1917,8 @@
     return getIncomingBlock(I.getUse());
   }
 
-
   void setIncomingBlock(unsigned i, BasicBlock *BB) {
-    setOperand(i*2+1, (Value*)BB);
-  }
-  static unsigned getOperandNumForIncomingBlock(unsigned i) {
-    return i*2+1;
-  }
-  static unsigned getIncomingBlockNumForOperand(unsigned i) {
-    assert(i % 2 == 1 && "Invalid incoming-block operand index!");
-    return i/2;
+    block_begin()[i] = BB;
   }
 
   /// addIncoming - Add an incoming value to the end of the PHI list
@@ -1908,13 +1928,12 @@
     assert(BB && "PHI node got a null basic block!");
     assert(getType() == V->getType() &&
            "All operands to PHI node must be the same type as the PHI node!");
-    unsigned OpNo = NumOperands;
-    if (OpNo+2 > ReservedSpace)
+    if (NumOperands == ReservedSpace)
       growOperands();  // Get more space!
     // Initialize some new operands.
-    NumOperands = OpNo+2;
-    OperandList[OpNo] = V;
-    OperandList[OpNo+1] = (Value*)BB;
+    ++NumOperands;
+    setIncomingValue(NumOperands - 1, V);
+    setIncomingBlock(NumOperands - 1, BB);
   }
 
   /// removeIncomingValue - Remove an incoming value.  This is useful if a
@@ -1937,14 +1956,16 @@
   /// block in the value list for this PHI.  Returns -1 if no instance.
   ///
   int getBasicBlockIndex(const BasicBlock *BB) const {
-    Use *OL = OperandList;
-    for (unsigned i = 0, e = getNumOperands(); i != e; i += 2)
-      if (OL[i+1].get() == (const Value*)BB) return i/2;
+    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
+      if (block_begin()[i] == BB)
+        return i;
     return -1;
   }
 
   Value *getIncomingValueForBlock(const BasicBlock *BB) const {
-    return getIncomingValue(getBasicBlockIndex(BB));
+    int Idx = getBasicBlockIndex(BB);
+    assert(Idx >= 0 && "Invalid basic block argument!");
+    return getIncomingValue(Idx);
   }
 
   /// hasConstantValue - If the specified PHI node always merges together the

Modified: llvm/trunk/include/llvm/Support/CFG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CFG.h?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CFG.h (original)
+++ llvm/trunk/include/llvm/Support/CFG.h Tue Jun 21 05:33:19 2011
@@ -33,7 +33,7 @@
   USE_iterator It;
 
   inline void advancePastNonTerminators() {
-    // Loop to ignore non terminator uses (for example PHI nodes).
+    // Loop to ignore non terminator uses (for example BlockAddresses).
     while (!It.atEnd() && !isa<TerminatorInst>(*It))
       ++It;
   }

Modified: llvm/trunk/include/llvm/Use.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Use.h?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Use.h (original)
+++ llvm/trunk/include/llvm/Use.h Tue Jun 21 05:33:19 2011
@@ -112,13 +112,16 @@
   Use *getNext() const { return Next; }
 
   
+  /// initTags - initialize the waymarking tags on an array of Uses, so that
+  /// getUser() can find the User from any of those Uses.
+  static Use *initTags(Use *Start, Use *Stop);
+
   /// zap - This is used to destroy Use operands when the number of operands of
   /// a User changes.
   static void zap(Use *Start, const Use *Stop, bool del = false);
 
 private:
   const Use* getImpliedUser() const;
-  static Use *initTags(Use *Start, Use *Stop);
   
   Value *Val;
   Use *Next;
@@ -140,7 +143,6 @@
   }
 
   friend class Value;
-  friend class User;
 };
 
 // simplify_type - Allow clients to treat uses just like values when using

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Tue Jun 21 05:33:19 2011
@@ -1356,7 +1356,7 @@
     for (unsigned i = 0; i < phi->getNumIncomingValues(); ++i) {
       Out << iName << "->addIncoming("
           << opNames[PHINode::getOperandNumForIncomingValue(i)] << ", "
-          << opNames[PHINode::getOperandNumForIncomingBlock(i)] << ");";
+          << getOpName(phi->getIncomingBlock(i)) << ");";
       nl(Out);
     }
     break;

Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Tue Jun 21 05:33:19 2011
@@ -1021,6 +1021,10 @@
         while (PHINode *PN = dyn_cast<PHINode>(Succ->begin()))
           ReplaceUsesOfWith(PN, PN->getIncomingValue(0), Worklist, L, LPM);
         
+        // If Succ has any successors with PHI nodes, update them to have
+        // entries coming from Pred instead of Succ.
+        Succ->replaceAllUsesWith(Pred);
+        
         // Move all of the successor contents from Succ to Pred.
         Pred->getInstList().splice(BI, Succ->getInstList(), Succ->begin(),
                                    Succ->end());
@@ -1028,10 +1032,6 @@
         BI->eraseFromParent();
         RemoveFromWorklist(BI, Worklist);
         
-        // If Succ has any successors with PHI nodes, update them to have
-        // entries coming from Pred instead of Succ.
-        Succ->replaceAllUsesWith(Pred);
-        
         // Remove Succ from the loop tree.
         LI->removeBlock(Succ);
         LPM->deleteSimpleAnalysisValue(Succ, L);

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Tue Jun 21 05:33:19 2011
@@ -153,13 +153,13 @@
   // Delete the unconditional branch from the predecessor...
   PredBB->getInstList().pop_back();
   
-  // Move all definitions in the successor to the predecessor...
-  PredBB->getInstList().splice(PredBB->end(), BB->getInstList());
-  
   // Make all PHI nodes that referred to BB now refer to Pred as their
   // source...
   BB->replaceAllUsesWith(PredBB);
   
+  // Move all definitions in the successor to the predecessor...
+  PredBB->getInstList().splice(PredBB->end(), BB->getInstList());
+  
   // Inherit predecessors name if it exists.
   if (!PredBB->hasName())
     PredBB->takeName(BB);

Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Tue Jun 21 05:33:19 2011
@@ -193,44 +193,22 @@
   
   // If there are any PHI nodes in DestBB, we need to update them so that they
   // merge incoming values from NewBB instead of from TIBB.
-  if (PHINode *APHI = dyn_cast<PHINode>(DestBB->begin())) {
-    // This conceptually does:
-    //  foreach (PHINode *PN in DestBB)
-    //    PN->setIncomingBlock(PN->getIncomingBlock(TIBB), NewBB);
-    // but is optimized for two cases.
-    
-    if (APHI->getNumIncomingValues() <= 8) {  // Small # preds case.
-      unsigned BBIdx = 0;
-      for (BasicBlock::iterator I = DestBB->begin(); isa<PHINode>(I); ++I) {
-        // We no longer enter through TIBB, now we come in through NewBB.
-        // Revector exactly one entry in the PHI node that used to come from
-        // TIBB to come from NewBB.
-        PHINode *PN = cast<PHINode>(I);
-        
-        // Reuse the previous value of BBIdx if it lines up.  In cases where we
-        // have multiple phi nodes with *lots* of predecessors, this is a speed
-        // win because we don't have to scan the PHI looking for TIBB.  This
-        // happens because the BB list of PHI nodes are usually in the same
-        // order.
-        if (PN->getIncomingBlock(BBIdx) != TIBB)
-          BBIdx = PN->getBasicBlockIndex(TIBB);
-        PN->setIncomingBlock(BBIdx, NewBB);
-      }
-    } else {
-      // However, the foreach loop is slow for blocks with lots of predecessors
-      // because PHINode::getIncomingBlock is O(n) in # preds.  Instead, walk
-      // the user list of TIBB to find the PHI nodes.
-      SmallPtrSet<PHINode*, 16> UpdatedPHIs;
-    
-      for (Value::use_iterator UI = TIBB->use_begin(), E = TIBB->use_end();
-           UI != E; ) {
-        Value::use_iterator Use = UI++;
-        if (PHINode *PN = dyn_cast<PHINode>(*Use)) {
-          // Remove one entry from each PHI.
-          if (PN->getParent() == DestBB && UpdatedPHIs.insert(PN))
-            PN->setOperand(Use.getOperandNo(), NewBB);
-        }
-      }
+  {
+    unsigned BBIdx = 0;
+    for (BasicBlock::iterator I = DestBB->begin(); isa<PHINode>(I); ++I) {
+      // We no longer enter through TIBB, now we come in through NewBB.
+      // Revector exactly one entry in the PHI node that used to come from
+      // TIBB to come from NewBB.
+      PHINode *PN = cast<PHINode>(I);
+
+      // Reuse the previous value of BBIdx if it lines up.  In cases where we
+      // have multiple phi nodes with *lots* of predecessors, this is a speed
+      // win because we don't have to scan the PHI looking for TIBB.  This
+      // happens because the BB list of PHI nodes are usually in the same
+      // order.
+      if (PN->getIncomingBlock(BBIdx) != TIBB)
+	BBIdx = PN->getBasicBlockIndex(TIBB);
+      PN->setIncomingBlock(BBIdx, NewBB);
     }
   }
    

Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Tue Jun 21 05:33:19 2011
@@ -572,12 +572,12 @@
     // removed, so we just need to splice the blocks.
     BI->eraseFromParent();
     
-    // Move all the instructions in the succ to the pred.
-    I->getInstList().splice(I->end(), Dest->getInstList());
-    
     // Make all PHI nodes that referred to Dest now refer to I as their source.
     Dest->replaceAllUsesWith(I);
 
+    // Move all the instructions in the succ to the pred.
+    I->getInstList().splice(I->end(), Dest->getInstList());
+    
     // Remove the dest block.
     Dest->eraseFromParent();
     

Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Tue Jun 21 05:33:19 2011
@@ -1097,15 +1097,15 @@
         TheCall->replaceAllUsesWith(Returns[0]->getReturnValue());
     }
 
+    // Update PHI nodes that use the ReturnBB to use the AfterCallBB.
+    BasicBlock *ReturnBB = Returns[0]->getParent();
+    ReturnBB->replaceAllUsesWith(AfterCallBB);
+
     // Splice the code from the return block into the block that it will return
     // to, which contains the code that was after the call.
-    BasicBlock *ReturnBB = Returns[0]->getParent();
     AfterCallBB->getInstList().splice(AfterCallBB->begin(),
                                       ReturnBB->getInstList());
 
-    // Update PHI nodes that use the ReturnBB to use the AfterCallBB.
-    ReturnBB->replaceAllUsesWith(AfterCallBB);
-
     // Delete the return instruction now and empty ReturnBB now.
     Returns[0]->eraseFromParent();
     ReturnBB->eraseFromParent();
@@ -1125,8 +1125,8 @@
 
   // Splice the code entry block into calling block, right before the
   // unconditional branch.
-  OrigBB->getInstList().splice(Br, CalleeEntry->getInstList());
   CalleeEntry->replaceAllUsesWith(OrigBB);  // Update PHI nodes
+  OrigBB->getInstList().splice(Br, CalleeEntry->getInstList());
 
   // Remove the unconditional branch.
   OrigBB->getInstList().erase(Br);

Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/Local.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/Local.cpp Tue Jun 21 05:33:19 2011
@@ -427,10 +427,6 @@
   BasicBlock *PredBB = DestBB->getSinglePredecessor();
   assert(PredBB && "Block doesn't have a single predecessor!");
   
-  // Splice all the instructions from PredBB to DestBB.
-  PredBB->getTerminator()->eraseFromParent();
-  DestBB->getInstList().splice(DestBB->begin(), PredBB->getInstList());
-
   // Zap anything that took the address of DestBB.  Not doing this will give the
   // address an invalid value.
   if (DestBB->hasAddressTaken()) {
@@ -445,6 +441,10 @@
   // Anything that branched to PredBB now branches to DestBB.
   PredBB->replaceAllUsesWith(DestBB);
   
+  // Splice all the instructions from PredBB to DestBB.
+  PredBB->getTerminator()->eraseFromParent();
+  DestBB->getInstList().splice(DestBB->begin(), PredBB->getInstList());
+
   if (P) {
     DominatorTree *DT = P->getAnalysisIfAvailable<DominatorTree>();
     if (DT) {
@@ -660,12 +660,17 @@
     // them, which helps expose duplicates, but we have to check all the
     // operands to be safe in case instcombine hasn't run.
     uintptr_t Hash = 0;
+    // This hash algorithm is quite weak as hash functions go, but it seems
+    // to do a good enough job for this particular purpose, and is very quick.
     for (User::op_iterator I = PN->op_begin(), E = PN->op_end(); I != E; ++I) {
-      // This hash algorithm is quite weak as hash functions go, but it seems
-      // to do a good enough job for this particular purpose, and is very quick.
       Hash ^= reinterpret_cast<uintptr_t>(static_cast<Value *>(*I));
       Hash = (Hash << 7) | (Hash >> (sizeof(uintptr_t) * CHAR_BIT - 7));
     }
+    for (PHINode::block_iterator I = PN->block_begin(), E = PN->block_end();
+         I != E; ++I) {
+      Hash ^= reinterpret_cast<uintptr_t>(static_cast<BasicBlock *>(*I));
+      Hash = (Hash << 7) | (Hash >> (sizeof(uintptr_t) * CHAR_BIT - 7));
+    }
     // Avoid colliding with the DenseMap sentinels ~0 and ~0-1.
     Hash >>= 1;
     // If we've never seen this hash value before, it's a unique PHI.

Modified: llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp Tue Jun 21 05:33:19 2011
@@ -47,6 +47,14 @@
     if (It != VMap.end())
       I->setOperand(op, It->second);
   }
+
+  if (PHINode *PN = dyn_cast<PHINode>(I)) {
+    for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
+      ValueToValueMapTy::iterator It = VMap.find(PN->getIncomingBlock(i));
+      if (It != VMap.end())
+        PN->setIncomingBlock(i, cast<BasicBlock>(It->second));
+    }
+  }
 }
 
 /// FoldBlockIntoPredecessor - Folds a basic block into its predecessor if it
@@ -75,13 +83,13 @@
   // Delete the unconditional branch from the predecessor...
   OnlyPred->getInstList().pop_back();
 
-  // Move all definitions in the successor to the predecessor...
-  OnlyPred->getInstList().splice(OnlyPred->end(), BB->getInstList());
-
   // Make all PHI nodes that referred to BB now refer to Pred as their
   // source...
   BB->replaceAllUsesWith(OnlyPred);
 
+  // Move all definitions in the successor to the predecessor...
+  OnlyPred->getInstList().splice(OnlyPred->end(), BB->getInstList());
+
   std::string OldName = BB->getName();
 
   // Erase basic block from the function...
@@ -247,16 +255,14 @@
       // the successor of the latch block.  The successor of the exit block will
       // be updated specially after unrolling all the way.
       if (*BB != LatchBlock)
-        for (Value::use_iterator UI = (*BB)->use_begin(), UE = (*BB)->use_end();
-             UI != UE;) {
-          Instruction *UseInst = cast<Instruction>(*UI);
-          ++UI;
-          if (isa<PHINode>(UseInst) && !L->contains(UseInst)) {
-            PHINode *phi = cast<PHINode>(UseInst);
-            Value *Incoming = phi->getIncomingValueForBlock(*BB);
-            phi->addIncoming(Incoming, New);
-          }
-        }
+        for (succ_iterator SI = succ_begin(*BB), SE = succ_end(*BB); SI != SE;
+             ++SI)
+          if (!L->contains(*SI))
+            for (BasicBlock::iterator BBI = (*SI)->begin(), BBE = (*SI)->end();
+                 PHINode *phi = dyn_cast<PHINode>(BBI); ++BBI) {
+              Value *Incoming = phi->getIncomingValueForBlock(*BB);
+              phi->addIncoming(Incoming, New);
+            }
 
       // Keep track of new headers and latches as we create them, so that
       // we can insert the proper branches later.
@@ -288,24 +294,20 @@
   // successor blocks, update them to use the appropriate values computed as the
   // last iteration of the loop.
   if (Count != 1) {
-    SmallPtrSet<PHINode*, 8> Users;
-    for (Value::use_iterator UI = LatchBlock->use_begin(),
-         UE = LatchBlock->use_end(); UI != UE; ++UI)
-      if (PHINode *phi = dyn_cast<PHINode>(*UI))
-        Users.insert(phi);
-    
     BasicBlock *LastIterationBB = cast<BasicBlock>(LastValueMap[LatchBlock]);
-    for (SmallPtrSet<PHINode*,8>::iterator SI = Users.begin(), SE = Users.end();
+    for (succ_iterator SI = succ_begin(LatchBlock), SE = succ_end(LatchBlock);
          SI != SE; ++SI) {
-      PHINode *PN = *SI;
-      Value *InVal = PN->removeIncomingValue(LatchBlock, false);
-      // If this value was defined in the loop, take the value defined by the
-      // last iteration of the loop.
-      if (Instruction *InValI = dyn_cast<Instruction>(InVal)) {
-        if (L->contains(InValI))
-          InVal = LastValueMap[InVal];
+      for (BasicBlock::iterator BBI = (*SI)->begin(), BBE = (*SI)->end();
+           PHINode *PN = dyn_cast<PHINode>(BBI); ++BBI) {
+        Value *InVal = PN->removeIncomingValue(LatchBlock, false);
+        // If this value was defined in the loop, take the value defined by the
+        // last iteration of the loop.
+        if (Instruction *InValI = dyn_cast<Instruction>(InVal)) {
+          if (L->contains(InValI))
+            InVal = LastValueMap[InVal];
+        }
+        PN->addIncoming(InVal, LastIterationBB);
       }
-      PN->addIncoming(InVal, LastIterationBB);
     }
   }
 
@@ -352,11 +354,16 @@
       // Replace the conditional branch with an unconditional one.
       BranchInst::Create(Dest, Term);
       Term->eraseFromParent();
-      // Merge adjacent basic blocks, if possible.
-      if (BasicBlock *Fold = FoldBlockIntoPredecessor(Dest, LI)) {
+    }
+  }
+
+  // Merge adjacent basic blocks, if possible.
+  for (unsigned i = 0, e = Latches.size(); i != e; ++i) {
+    BranchInst *Term = cast<BranchInst>(Latches[i]->getTerminator());
+    if (Term->isUnconditional()) {
+      BasicBlock *Dest = Term->getSuccessor(0);
+      if (BasicBlock *Fold = FoldBlockIntoPredecessor(Dest, LI))
         std::replace(Latches.begin(), Latches.end(), Dest, Fold);
-        std::replace(Headers.begin(), Headers.end(), Dest, Fold);
-      }
     }
   }
   

Modified: llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp Tue Jun 21 05:33:19 2011
@@ -16,6 +16,7 @@
 #include "llvm/Type.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
+#include "llvm/Instructions.h"
 #include "llvm/Metadata.h"
 #include "llvm/ADT/SmallVector.h"
 using namespace llvm;
@@ -128,6 +129,19 @@
              "Referenced value not in value map!");
   }
 
+  // Remap phi nodes' incoming blocks.
+  if (PHINode *PN = dyn_cast<PHINode>(I)) {
+    for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
+      Value *V = MapValue(PN->getIncomingBlock(i), VMap, Flags);
+      // If we aren't ignoring missing entries, assert that something happened.
+      if (V != 0)
+        PN->setIncomingBlock(i, cast<BasicBlock>(V));
+      else
+        assert((Flags & RF_IgnoreMissingEntries) &&
+               "Referenced block not in value map!");
+    }
+  }
+
   // Remap attached metadata.
   SmallVector<std::pair<unsigned, MDNode *>, 4> MDs;
   I->getAllMetadata(MDs);

Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/BasicBlock.cpp (original)
+++ llvm/trunk/lib/VMCore/BasicBlock.cpp Tue Jun 21 05:33:19 2011
@@ -308,3 +308,19 @@
   return New;
 }
 
+void BasicBlock::replaceSuccessorsPhiUsesWith(BasicBlock *New) {
+  TerminatorInst *TI = getTerminator();
+  if (!TI)
+    // Cope with being called on a BasicBlock that doesn't have a terminator
+    // yet. Clang's CodeGenFunction::EmitReturnBlock() likes to do this.
+    return;
+  for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) {
+    BasicBlock *Succ = TI->getSuccessor(i);
+    for (iterator II = Succ->begin(); PHINode *PN = dyn_cast<PHINode>(II);
+         ++II) {
+      int i;
+      while ((i = PN->getBasicBlockIndex(this)) >= 0)
+        PN->setIncomingBlock(i, New);
+    }
+  }
+}

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Tue Jun 21 05:33:19 2011
@@ -87,11 +87,8 @@
   : Instruction(PN.getType(), Instruction::PHI,
                 allocHungoffUses(PN.getNumOperands()), PN.getNumOperands()),
     ReservedSpace(PN.getNumOperands()) {
-  Use *OL = OperandList;
-  for (unsigned i = 0, e = PN.getNumOperands(); i != e; i+=2) {
-    OL[i] = PN.getOperand(i);
-    OL[i+1] = PN.getOperand(i+1);
-  }
+  std::copy(PN.op_begin(), PN.op_end(), op_begin());
+  std::copy(PN.block_begin(), PN.block_end(), block_begin());
   SubclassOptionalData = PN.SubclassOptionalData;
 }
 
@@ -99,31 +96,37 @@
   dropHungoffUses();
 }
 
+Use *PHINode::allocHungoffUses(unsigned N) const {
+  // Allocate the array of Uses of the incoming values, followed by a pointer
+  // (with bottom bit set) to the User, followed by the array of pointers to
+  // the incoming basic blocks.
+  size_t size = N * sizeof(Use) + sizeof(Use::UserRef)
+    + N * sizeof(BasicBlock*);
+  Use *Begin = static_cast<Use*>(::operator new(size));
+  Use *End = Begin + N;
+  (void) new(End) Use::UserRef(const_cast<PHINode*>(this), 1);
+  return Use::initTags(Begin, End);
+}
+
 // removeIncomingValue - Remove an incoming value.  This is useful if a
 // predecessor basic block is deleted.
 Value *PHINode::removeIncomingValue(unsigned Idx, bool DeletePHIIfEmpty) {
-  unsigned NumOps = getNumOperands();
-  Use *OL = OperandList;
-  assert(Idx*2 < NumOps && "BB not in PHI node!");
-  Value *Removed = OL[Idx*2];
+  Value *Removed = getIncomingValue(Idx);
 
   // Move everything after this operand down.
   //
   // FIXME: we could just swap with the end of the list, then erase.  However,
-  // client might not expect this to happen.  The code as it is thrashes the
+  // clients might not expect this to happen.  The code as it is thrashes the
   // use/def lists, which is kinda lame.
-  for (unsigned i = (Idx+1)*2; i != NumOps; i += 2) {
-    OL[i-2] = OL[i];
-    OL[i-2+1] = OL[i+1];
-  }
+  std::copy(op_begin() + Idx + 1, op_end(), op_begin() + Idx);
+  std::copy(block_begin() + Idx + 1, block_end(), block_begin() + Idx);
 
   // Nuke the last value.
-  OL[NumOps-2].set(0);
-  OL[NumOps-2+1].set(0);
-  NumOperands = NumOps-2;
+  Op<-1>().set(0);
+  --NumOperands;
 
   // If the PHI node is dead, because it has zero entries, nuke it now.
-  if (NumOps == 2 && DeletePHIIfEmpty) {
+  if (getNumOperands() == 0 && DeletePHIIfEmpty) {
     // If anyone is using this PHI, make them use a dummy value instead...
     replaceAllUsesWith(UndefValue::get(getType()));
     eraseFromParent();
@@ -137,15 +140,18 @@
 ///
 void PHINode::growOperands() {
   unsigned e = getNumOperands();
-  // Multiply by 1.5 and round down so the result is still even.
-  unsigned NumOps = e + e / 4 * 2;
-  if (NumOps < 4) NumOps = 4;      // 4 op PHI nodes are VERY common.
+  unsigned NumOps = e + e / 2;
+  if (NumOps < 2) NumOps = 2;      // 2 op PHI nodes are VERY common.
+
+  Use *OldOps = op_begin();
+  BasicBlock **OldBlocks = block_begin();
 
   ReservedSpace = NumOps;
-  Use *OldOps = OperandList;
-  Use *NewOps = allocHungoffUses(NumOps);
-  std::copy(OldOps, OldOps + e, NewOps);
-  OperandList = NewOps;
+  OperandList = allocHungoffUses(ReservedSpace);
+
+  std::copy(OldOps, OldOps + e, op_begin());
+  std::copy(OldBlocks, OldBlocks + e, block_begin());
+
   Use::zap(OldOps, OldOps + e, true);
 }
 

Modified: llvm/trunk/lib/VMCore/User.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/User.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/User.cpp (original)
+++ llvm/trunk/lib/VMCore/User.cpp Tue Jun 21 05:33:19 2011
@@ -40,8 +40,10 @@
 //===----------------------------------------------------------------------===//
 
 Use *User::allocHungoffUses(unsigned N) const {
-  Use *Begin = static_cast<Use*>(::operator new(sizeof(Use) * N
-                                                + sizeof(Use::UserRef)));
+  // Allocate the array of Uses, followed by a pointer (with bottom bit set) to
+  // the User.
+  size_t size = N * sizeof(Use) + sizeof(Use::UserRef);
+  Use *Begin = static_cast<Use*>(::operator new(size));
   Use *End = Begin + N;
   (void) new(End) Use::UserRef(const_cast<User*>(this), 1);
   return Use::initTags(Begin, End);

Modified: llvm/trunk/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Value.cpp (original)
+++ llvm/trunk/lib/VMCore/Value.cpp Tue Jun 21 05:33:19 2011
@@ -305,6 +305,9 @@
 
     U.set(New);
   }
+
+  if (BasicBlock *BB = dyn_cast<BasicBlock>(this))
+    BB->replaceSuccessorsPhiUsesWith(cast<BasicBlock>(New));
 }
 
 void Value::replaceAllUsesWith(Value *New) {

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=133513&r1=133512&r2=133513&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Tue Jun 21 05:33:19 2011
@@ -1139,9 +1139,6 @@
   for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
     Assert1(PN.getType() == PN.getIncomingValue(i)->getType(),
             "PHI node operands are not the same type as the result!", &PN);
-    Assert1(isa<BasicBlock>(PN.getOperand(
-                PHINode::getOperandNumForIncomingBlock(i))),
-            "PHI node incoming block is not a BasicBlock!", &PN);
   }
 
   // All other PHI node constraints are checked in the visitBasicBlock method.



From fvbommel at gmail.com  Tue Jun 21 06:41:35 2011
From: fvbommel at gmail.com (Frits van Bommel)
Date: Tue, 21 Jun 2011 13:41:35 +0200
Subject: [llvm-commits] [llvm] r133512 -
	/llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp
In-Reply-To: <20110621100243.C70E02A6C12C@llvm.org>
References: <20110621100243.C70E02A6C12C@llvm.org>
Message-ID: <BANLkTinFakMCAdTG4dLKhwFqTqDji4WhTw@mail.gmail.com>

On 21 June 2011 12:02, Jay Foad <jay.foad at gmail.com> wrote:
> Log:
> Don't use PN->replaceUsesOfWith() to change a PHINode's incoming blocks,
> because it won't work after my phi operand changes, because the incoming
> blocks will no longer be Uses.

> ? while (PHINode* P = dyn_cast<PHINode>(BI)) {
> - ? ?P->replaceUsesOfWith(exitingBlock, preheader);
> + ? ?int j = P->getBasicBlockIndex(exitingBlock);
> + ? ?assert(j >= 0 && "Can't find exiting block in exit block's phi node!");
> + ? ?P->setIncomingBlock(j, preheader);

replaceUsesOfWith() can handle multiple uses of the same value, but
this version only handles a single use. Are you sure there can only be
a single incoming edge from each basic block here?


From jay.foad at gmail.com  Tue Jun 21 06:57:35 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 21 Jun 2011 12:57:35 +0100
Subject: [llvm-commits] [llvm] r133512 -
	/llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp
In-Reply-To: <BANLkTinFakMCAdTG4dLKhwFqTqDji4WhTw@mail.gmail.com>
References: <20110621100243.C70E02A6C12C@llvm.org>
	<BANLkTinFakMCAdTG4dLKhwFqTqDji4WhTw@mail.gmail.com>
Message-ID: <BANLkTimmq-81aPbv0OAkiS13-0hwKbsx7h5=4N_npCreQS5L7Q@mail.gmail.com>

On 21 June 2011 12:41, Frits van Bommel <fvbommel at gmail.com> wrote:
> On 21 June 2011 12:02, Jay Foad <jay.foad at gmail.com> wrote:
>> Log:
>> Don't use PN->replaceUsesOfWith() to change a PHINode's incoming blocks,
>> because it won't work after my phi operand changes, because the incoming
>> blocks will no longer be Uses.
>
>> ? while (PHINode* P = dyn_cast<PHINode>(BI)) {
>> - ? ?P->replaceUsesOfWith(exitingBlock, preheader);
>> + ? ?int j = P->getBasicBlockIndex(exitingBlock);
>> + ? ?assert(j >= 0 && "Can't find exiting block in exit block's phi node!");
>> + ? ?P->setIncomingBlock(j, preheader);
>
> replaceUsesOfWith() can handle multiple uses of the same value, but
> this version only handles a single use. Are you sure there can only be
> a single incoming edge from each basic block here?

exitingBlock is an arbitrarily chosen member of exitingBlocks[]. The
code goes on to say:

    for (unsigned i = 1; i < exitingBlocks.size(); ++i)
      P->removeIncomingValue(exitingBlocks[i]);

which will only remove one incoming edge for each of the other members
of exitingBlocks[]. So yes, I'm fairly sure that either there's only a
single incoming edge from each exitingBlock, or the code was already
broken.


I did consider a completely different fix, which is to implement something like:

void PHINode::replaceUsesOfWith(Value *From, Value *To) {
  if (isa<BasicBlock>(From)) {
    assert(isa<BasicBlock>(To));
    for (block_iterator I = block_begin(), E = block_end(); I != E; ++I)
      if (*I == From)
        *I = To;
  } else {
    assert(!isa<BasicBlock>(To));
    User::replaceUsesOfWith(From, To);
  }
}

Would you prefer that?

Jay.


From baldrick at free.fr  Tue Jun 21 06:57:54 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 21 Jun 2011 13:57:54 +0200
Subject: [llvm-commits] [llvm] r133285	-
	/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp
In-Reply-To: <BEFDFA5B-4D83-47A5-A967-02ADE979F770@apple.com>
References: <20110617202152.D6B812A6C12C@llvm.org> <4DFDF276.5030703@free.fr>
	<54E09593-01A1-4936-AFF8-7AF19D2C6919@apple.com>
	<4DFEF6DA.4030503@free.fr>
	<BEFDFA5B-4D83-47A5-A967-02ADE979F770@apple.com>
Message-ID: <4E008742.9030700@free.fr>

Hi John,

>>> However, there's a second restriction, which is that it's undefined
>>> behavior to allocate something too large for the stack.  Technically
>>> this is target-specific, but if we just assume by fiat that 2^31 is too large,
>>> then as long as the arithmetic is being done in some reasonable size
>>> then we know that N * sizeof(T) isn't permitted to signed overflow, either.
>>
>> if you are willing to assume that then you don't need to check for nuw either...
>
> We can't *assume* it doesn't overflow.

I thought *you* were suggesting that we assume no overflow when you said "but
if we just assume by fiat that 2^31 is too large, then as long as the arithmetic
is being done in some reasonable size then we know that N * sizeof(T) isn't
permitted to signed overflow, either."  I guess I misunderstood.  I'm still not
sure what you were trying to say :)

   That's the whole point of this discussion.
> There's an implicit multiply in sizeof(sp) as part of the alloca instruction, and
> it's undefined behavior if either
>    - that multiply causes unsigned overflow or

Sure.

>    - either the input or output to that multiply is negative.

Why?  Are you saying that an alloca of 2^31 i8's should be considered to result
in undefined behaviour?  And what about this: alloca i8, i8 128

By the way, on a 64 bit machine I guess it costs nothing to change the type of
the alloca numelements parameter to i64, so if Stuart's testcase was on such a
platform then it could become: %c = alloca [16 x i8], i64 %N
where %N = zext i32 %n to i64.

> Going back to Stuart's original test case, we can't apply the transform to this:
>    %a = mul i32 16, %n
>    %b = alloca i8, i32 %b
>    %c = bitcast i8* %x to [16 x i8]*
> as that might introduce undefined behavior, because the multiply in %a is
> allowed to overflow, and the multiply in this:
>    %c = alloca [16 x i8], i32 %n
> is not.

Indeed.

Ciao, Duncan.

From fvbommel at gmail.com  Tue Jun 21 07:10:30 2011
From: fvbommel at gmail.com (Frits van Bommel)
Date: Tue, 21 Jun 2011 14:10:30 +0200
Subject: [llvm-commits] [llvm] r133512 -
	/llvm/trunk/lib/Transforms/Scalar/LoopDeletion.cpp
In-Reply-To: <BANLkTimmq-81aPbv0OAkiS13-0hwKbsx7h5=4N_npCreQS5L7Q@mail.gmail.com>
References: <20110621100243.C70E02A6C12C@llvm.org>
	<BANLkTinFakMCAdTG4dLKhwFqTqDji4WhTw@mail.gmail.com>
	<BANLkTimmq-81aPbv0OAkiS13-0hwKbsx7h5=4N_npCreQS5L7Q@mail.gmail.com>
Message-ID: <BANLkTi=iaEsJo2wU5UyMTo-Ny+jBriPOqw@mail.gmail.com>

On 21 June 2011 13:57, Jay Foad <jay.foad at gmail.com> wrote:
> On 21 June 2011 12:41, Frits van Bommel <fvbommel at gmail.com> wrote:
>> On 21 June 2011 12:02, Jay Foad <jay.foad at gmail.com> wrote:
>>> Log:
>>> Don't use PN->replaceUsesOfWith() to change a PHINode's incoming blocks,
>>> because it won't work after my phi operand changes, because the incoming
>>> blocks will no longer be Uses.
>>
>>> ? while (PHINode* P = dyn_cast<PHINode>(BI)) {
>>> - ? ?P->replaceUsesOfWith(exitingBlock, preheader);
>>> + ? ?int j = P->getBasicBlockIndex(exitingBlock);
>>> + ? ?assert(j >= 0 && "Can't find exiting block in exit block's phi node!");
>>> + ? ?P->setIncomingBlock(j, preheader);
>>
>> replaceUsesOfWith() can handle multiple uses of the same value, but
>> this version only handles a single use. Are you sure there can only be
>> a single incoming edge from each basic block here?
>
> exitingBlock is an arbitrarily chosen member of exitingBlocks[]. The
> code goes on to say:
>
> ? ?for (unsigned i = 1; i < exitingBlocks.size(); ++i)
> ? ? ?P->removeIncomingValue(exitingBlocks[i]);
>
> which will only remove one incoming edge for each of the other members
> of exitingBlocks[]. So yes, I'm fairly sure that either there's only a
> single incoming edge from each exitingBlock, or the code was already
> broken.

Huh. Don't know how I missed that. It's all right there in the diff, even.


From jay.foad at gmail.com  Tue Jun 21 07:57:18 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 21 Jun 2011 13:57:18 +0100
Subject: [llvm-commits] [PATCH 0/5] Reduce memory usage for phi operands
In-Reply-To: <4737089F-10B2-4D3F-A9C5-B26E2D405674@apple.com>
References: <1308222566-2451-1-git-send-email-jay.foad@gmail.com>
	<4737089F-10B2-4D3F-A9C5-B26E2D405674@apple.com>
Message-ID: <BANLkTinSB-6zzgpn3wHEw0fRjOEFt14AW42bTWb0my5HiF05Uw@mail.gmail.com>

> If you're interested in another project, PR1324 would be another great memory reduction for apps with lots of strings and tables.

This bug is about using a more compact representation of
ConstantArrays of ConstantInts. I think it will be easier to do this
for integers of a few pre-defined widths (i8. i16, i32, i64, maybe
even i1), rather than trying to handle arbitrarily wide integers. Does
this seem reasonable?

Thanks,
Jay.

From benny.kra at googlemail.com  Tue Jun 21 09:58:30 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Tue, 21 Jun 2011 14:58:30 -0000
Subject: [llvm-commits] [llvm] r133514 -
	/llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
Message-ID: <20110621145830.998B52A6C12C@llvm.org>

Author: d0k
Date: Tue Jun 21 09:58:30 2011
New Revision: 133514

URL: http://llvm.org/viewvc/llvm-project?rev=133514&view=rev
Log:
Remove unused variables.

Modified:
    llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp

Modified: llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp?rev=133514&r1=133513&r2=133514&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp Tue Jun 21 09:58:30 2011
@@ -258,7 +258,7 @@
         for (succ_iterator SI = succ_begin(*BB), SE = succ_end(*BB); SI != SE;
              ++SI)
           if (!L->contains(*SI))
-            for (BasicBlock::iterator BBI = (*SI)->begin(), BBE = (*SI)->end();
+            for (BasicBlock::iterator BBI = (*SI)->begin();
                  PHINode *phi = dyn_cast<PHINode>(BBI); ++BBI) {
               Value *Incoming = phi->getIncomingValueForBlock(*BB);
               phi->addIncoming(Incoming, New);
@@ -297,7 +297,7 @@
     BasicBlock *LastIterationBB = cast<BasicBlock>(LastValueMap[LatchBlock]);
     for (succ_iterator SI = succ_begin(LatchBlock), SE = succ_end(LatchBlock);
          SI != SE; ++SI) {
-      for (BasicBlock::iterator BBI = (*SI)->begin(), BBE = (*SI)->end();
+      for (BasicBlock::iterator BBI = (*SI)->begin();
            PHINode *PN = dyn_cast<PHINode>(BBI); ++BBI) {
         Value *InVal = PN->removeIncomingValue(LatchBlock, false);
         // If this value was defined in the loop, take the value defined by the



From jay.foad at gmail.com  Tue Jun 21 10:36:24 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 21 Jun 2011 15:36:24 -0000
Subject: [llvm-commits] [llvm] r133516 - /llvm/trunk/tools/lto/LTOModule.cpp
Message-ID: <20110621153624.604CB2A6C12C@llvm.org>

Author: foad
Date: Tue Jun 21 10:36:24 2011
New Revision: 133516

URL: http://llvm.org/viewvc/llvm-project?rev=133516&view=rev
Log:
Remove some unnecessary uses of c_str().

Modified:
    llvm/trunk/tools/lto/LTOModule.cpp

Modified: llvm/trunk/tools/lto/LTOModule.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=133516&r1=133515&r2=133516&view=diff
==============================================================================
--- llvm/trunk/tools/lto/LTOModule.cpp (original)
+++ llvm/trunk/tools/lto/LTOModule.cpp Tue Jun 21 10:36:24 2011
@@ -208,7 +208,7 @@
     if (objcClassNameFromExpression(c->getOperand(1), superclassName)) {
       NameAndAttributes info;
       StringMap<NameAndAttributes>::value_type &entry =
-        _undefines.GetOrCreateValue(superclassName.c_str());
+        _undefines.GetOrCreateValue(superclassName);
       if (!entry.getValue().name) {
         const char *symbolName = entry.getKey().data();
         info.name = symbolName;
@@ -220,7 +220,7 @@
     std::string className;
     if (objcClassNameFromExpression(c->getOperand(2), className)) {
       StringSet::value_type &entry =
-        _defines.GetOrCreateValue(className.c_str());
+        _defines.GetOrCreateValue(className);
       entry.setValue(1);
       NameAndAttributes info;
       info.name = entry.getKey().data();
@@ -243,7 +243,7 @@
       NameAndAttributes info;
 
       StringMap<NameAndAttributes>::value_type &entry =
-        _undefines.GetOrCreateValue(targetclassName.c_str());
+        _undefines.GetOrCreateValue(targetclassName);
 
       if (entry.getValue().name)
         return;
@@ -264,7 +264,7 @@
     NameAndAttributes info;
 
     StringMap<NameAndAttributes>::value_type &entry =
-      _undefines.GetOrCreateValue(targetclassName.c_str());
+      _undefines.GetOrCreateValue(targetclassName);
     if (entry.getValue().name)
       return;
 
@@ -375,7 +375,7 @@
 
   // add to table of symbols
   NameAndAttributes info;
-  StringSet::value_type &entry = _defines.GetOrCreateValue(Buffer.c_str());
+  StringSet::value_type &entry = _defines.GetOrCreateValue(Buffer);
   entry.setValue(1);
 
   StringRef Name = entry.getKey();
@@ -436,7 +436,7 @@
   mangler.getNameWithPrefix(name, decl, false);
 
   StringMap<NameAndAttributes>::value_type &entry =
-    _undefines.GetOrCreateValue(name.c_str());
+    _undefines.GetOrCreateValue(name);
 
   // we already have the symbol
   if (entry.getValue().name)



From jay.foad at gmail.com  Tue Jun 21 10:37:05 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 21 Jun 2011 15:37:05 -0000
Subject: [llvm-commits] [llvm] r133517 -
	/llvm/trunk/include/llvm/ADT/StringMap.h
Message-ID: <20110621153705.941BF2A6C12C@llvm.org>

Author: foad
Date: Tue Jun 21 10:37:05 2011
New Revision: 133517

URL: http://llvm.org/viewvc/llvm-project?rev=133517&view=rev
Log:
Remove deprecated forms of StringMap::GetOrCreateValue().

Modified:
    llvm/trunk/include/llvm/ADT/StringMap.h

Modified: llvm/trunk/include/llvm/ADT/StringMap.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/StringMap.h?rev=133517&r1=133516&r2=133517&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/StringMap.h (original)
+++ llvm/trunk/include/llvm/ADT/StringMap.h Tue Jun 21 10:37:05 2011
@@ -381,18 +381,6 @@
     return GetOrCreateValue(Key, ValueTy());
   }
 
-  // FIXME: Remove this method.
-  template <typename InitTy>
-  MapEntryTy &GetOrCreateValue(const char *KeyStart, const char *KeyEnd,
-                               InitTy Val) {
-    return GetOrCreateValue(StringRef(KeyStart, KeyEnd - KeyStart), Val);
-  }
-
-  // FIXME: Remove this method.
-  MapEntryTy &GetOrCreateValue(const char *KeyStart, const char *KeyEnd) {
-    return GetOrCreateValue(StringRef(KeyStart, KeyEnd - KeyStart));
-  }
-
   /// remove - Remove the specified key/value pair from the map, but do not
   /// erase it.  This aborts if the key is not in the map.
   void remove(MapEntryTy *KeyValue) {



From jay.foad at gmail.com  Tue Jun 21 10:43:52 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 21 Jun 2011 16:43:52 +0100
Subject: [llvm-commits] [llvm] r133504 -
	/llvm/trunk/include/llvm/ADT/StringMap.h
In-Reply-To: <20110621062234.20F6E2A6C12C@llvm.org>
References: <20110621062234.20F6E2A6C12C@llvm.org>
Message-ID: <BANLkTikAtMa+1ngXmqUZ9jNWiuMTa851+CU9d9CD9z69DMoPtw@mail.gmail.com>

On 21 June 2011 07:22, Chris Lattner <sabre at nondot.org> wrote:
> use the MapEntryTy typedef instead of writing it out long form,
> add some fixme's about methods that should be removed.

Removed in r133517 :)

Thanks,
Jay.

From atrick at apple.com  Tue Jun 21 10:43:53 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 21 Jun 2011 15:43:53 -0000
Subject: [llvm-commits] [llvm] r133518 - in /llvm/trunk:
 include/llvm/Analysis/IVUsers.h lib/Analysis/IVUsers.cpp
 lib/Transforms/Scalar/IndVarSimplify.cpp
 lib/Transforms/Scalar/LoopStrengthReduce.cpp
Message-ID: <20110621154353.295322A6C12C@llvm.org>

Author: atrick
Date: Tue Jun 21 10:43:52 2011
New Revision: 133518

URL: http://llvm.org/viewvc/llvm-project?rev=133518&view=rev
Log:
IVUsers no longer needs to record the phis.

Modified:
    llvm/trunk/include/llvm/Analysis/IVUsers.h
    llvm/trunk/lib/Analysis/IVUsers.cpp
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp

Modified: llvm/trunk/include/llvm/Analysis/IVUsers.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/IVUsers.h?rev=133518&r1=133517&r2=133518&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/IVUsers.h (original)
+++ llvm/trunk/include/llvm/Analysis/IVUsers.h Tue Jun 21 10:43:52 2011
@@ -37,8 +37,8 @@
 class IVStrideUse : public CallbackVH, public ilist_node<IVStrideUse> {
   friend class IVUsers;
 public:
-  IVStrideUse(IVUsers *P, Instruction* U, Value *O, Value *PN)
-    : CallbackVH(U), Parent(P), OperandValToReplace(O), Phi(PN) {
+  IVStrideUse(IVUsers *P, Instruction* U, Value *O)
+    : CallbackVH(U), Parent(P), OperandValToReplace(O) {
   }
 
   /// getUser - Return the user instruction for this use.
@@ -51,11 +51,6 @@
     setValPtr(NewUser);
   }
 
-  /// getPhi - Return the phi node that represents this IV.
-  PHINode *getPhi() const {
-    return cast<PHINode>(Phi);
-  }
-
   /// getOperandValToReplace - Return the Value of the operand in the user
   /// instruction that this IVStrideUse is representing.
   Value *getOperandValToReplace() const {
@@ -86,9 +81,6 @@
   /// that this IVStrideUse is representing.
   WeakVH OperandValToReplace;
 
-  /// Phi - The loop header phi that represents this IV.
-  WeakVH Phi;
-
   /// PostIncLoops - The set of loops for which Expr has been adjusted to
   /// use post-inc mode. This corresponds with SCEVExpander's post-inc concept.
   PostIncLoopSet PostIncLoops;
@@ -151,9 +143,9 @@
   /// AddUsersIfInteresting - Inspect the specified Instruction.  If it is a
   /// reducible SCEV, recursively add its users to the IVUsesByStride set and
   /// return true.  Otherwise, return false.
-  bool AddUsersIfInteresting(Instruction *I, PHINode *Phi);
+  bool AddUsersIfInteresting(Instruction *I);
 
-  IVStrideUse &AddUser(Instruction *User, Value *Operand, PHINode *Phi);
+  IVStrideUse &AddUser(Instruction *User, Value *Operand);
 
   /// getReplacementExpr - Return a SCEV expression which computes the
   /// value of the OperandValToReplace of the given IVStrideUse.

Modified: llvm/trunk/lib/Analysis/IVUsers.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IVUsers.cpp?rev=133518&r1=133517&r2=133518&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/IVUsers.cpp (original)
+++ llvm/trunk/lib/Analysis/IVUsers.cpp Tue Jun 21 10:43:52 2011
@@ -89,7 +89,7 @@
 /// AddUsersIfInteresting - Inspect the specified instruction.  If it is a
 /// reducible SCEV, recursively add its users to the IVUsesByStride set and
 /// return true.  Otherwise, return false.
-bool IVUsers::AddUsersIfInteresting(Instruction *I, PHINode *Phi) {
+bool IVUsers::AddUsersIfInteresting(Instruction *I) {
   if (!SE->isSCEVable(I->getType()))
     return false;   // Void and FP expressions cannot be reduced.
 
@@ -136,13 +136,12 @@
     bool AddUserToIVUsers = false;
     if (LI->getLoopFor(User->getParent()) != L) {
       if (isa<PHINode>(User) || Processed.count(User) ||
-          !AddUsersIfInteresting(User, Phi)) {
+          !AddUsersIfInteresting(User)) {
         DEBUG(dbgs() << "FOUND USER in other loop: " << *User << '\n'
                      << "   OF SCEV: " << *ISE << '\n');
         AddUserToIVUsers = true;
       }
-    } else if (Processed.count(User) ||
-               !AddUsersIfInteresting(User, Phi)) {
+    } else if (Processed.count(User) || !AddUsersIfInteresting(User)) {
       DEBUG(dbgs() << "FOUND USER: " << *User << '\n'
                    << "   OF SCEV: " << *ISE << '\n');
       AddUserToIVUsers = true;
@@ -150,7 +149,7 @@
 
     if (AddUserToIVUsers) {
       // Okay, we found a user that we cannot reduce.
-      IVUses.push_back(new IVStrideUse(this, User, I, Phi));
+      IVUses.push_back(new IVStrideUse(this, User, I));
       IVStrideUse &NewUse = IVUses.back();
       // Autodetect the post-inc loop set, populating NewUse.PostIncLoops.
       // The regular return value here is discarded; instead of recording
@@ -165,8 +164,8 @@
   return true;
 }
 
-IVStrideUse &IVUsers::AddUser(Instruction *User, Value *Operand, PHINode *Phi) {
-  IVUses.push_back(new IVStrideUse(this, User, Operand, Phi));
+IVStrideUse &IVUsers::AddUser(Instruction *User, Value *Operand) {
+  IVUses.push_back(new IVStrideUse(this, User, Operand));
   return IVUses.back();
 }
 
@@ -194,7 +193,7 @@
   // them by stride.  Start by finding all of the PHI nodes in the header for
   // this loop.  If they are induction variables, inspect their uses.
   for (BasicBlock::iterator I = L->getHeader()->begin(); isa<PHINode>(I); ++I)
-    (void)AddUsersIfInteresting(I, cast<PHINode>(I));
+    (void)AddUsersIfInteresting(I);
 
   return false;
 }

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=133518&r1=133517&r2=133518&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Jun 21 10:43:52 2011
@@ -131,8 +131,7 @@
     void EliminateIVComparison(ICmpInst *ICmp, Value *IVOperand);
     void EliminateIVRemainder(BinaryOperator *Rem,
                               Value *IVOperand,
-                              bool IsSigned,
-                              PHINode *IVPhi);
+                              bool IsSigned);
     void pushIVUsers(Instruction *Def);
     bool isSimpleIVUser(Instruction *I, const Loop *L);
     void RewriteNonIntegerIVs(Loop *L);
@@ -523,7 +522,7 @@
     if (BinaryOperator *Rem = dyn_cast<BinaryOperator>(UseInst)) {
       bool IsSigned = Rem->getOpcode() == Instruction::SRem;
       if (IsSigned || Rem->getOpcode() == Instruction::URem) {
-        EliminateIVRemainder(Rem, IVOperand, IsSigned, I->getPhi());
+        EliminateIVRemainder(Rem, IVOperand, IsSigned);
         continue;
       }
     }
@@ -946,8 +945,7 @@
 
 void IndVarSimplify::EliminateIVRemainder(BinaryOperator *Rem,
                                           Value *IVOperand,
-                                          bool IsSigned,
-                                          PHINode *IVPhi) {
+                                          bool IsSigned) {
   // We're only interested in the case where we know something about
   // the numerator.
   if (IVOperand != Rem->getOperand(0))
@@ -992,7 +990,7 @@
   // Inform IVUsers about the new users.
   if (IU) {
     if (Instruction *I = dyn_cast<Instruction>(Rem->getOperand(0)))
-      IU->AddUsersIfInteresting(I, IVPhi);
+      IU->AddUsersIfInteresting(I);
   }
   DEBUG(dbgs() << "INDVARS: Simplified rem: " << *Rem << '\n');
   ++NumElimRem;
@@ -1011,7 +1009,7 @@
   if (BinaryOperator *Rem = dyn_cast<BinaryOperator>(UseInst)) {
     bool IsSigned = Rem->getOpcode() == Instruction::SRem;
     if (IsSigned || Rem->getOpcode() == Instruction::URem) {
-      EliminateIVRemainder(Rem, IVOperand, IsSigned, CurrIV);
+      EliminateIVRemainder(Rem, IVOperand, IsSigned);
       return true;
     }
   }
@@ -1283,8 +1281,7 @@
   // For completeness, inform IVUsers of the IV use in the newly-created
   // loop exit test instruction.
   if (NewICmp && IU)
-    IU->AddUsersIfInteresting(cast<Instruction>(NewICmp->getOperand(0)),
-                              IndVar);
+    IU->AddUsersIfInteresting(cast<Instruction>(NewICmp->getOperand(0)));
 
   // Clean up dead instructions.
   Changed |= DeleteDeadPHIs(L->getHeader());
@@ -1716,5 +1713,5 @@
 
   // Add a new IVUsers entry for the newly-created integer PHI.
   if (IU)
-    IU->AddUsersIfInteresting(NewPHI, NewPHI);
+    IU->AddUsersIfInteresting(NewPHI);
 }

Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=133518&r1=133517&r2=133518&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Jun 21 10:43:52 2011
@@ -1804,8 +1804,7 @@
         ExitingBlock->getInstList().insert(TermBr, Cond);
 
         // Clone the IVUse, as the old use still exists!
-        CondUse = &IU.AddUser(Cond, CondUse->getOperandValToReplace(),
-                              CondUse->getPhi());
+        CondUse = &IU.AddUser(Cond, CondUse->getOperandValToReplace());
         TermBr->replaceUsesOfWith(OldCond, Cond);
       }
     }



From aggarwa4 at illinois.edu  Tue Jun 21 11:05:07 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 21 Jun 2011 16:05:07 -0000
Subject: [llvm-commits] [poolalloc] r133520 - in /poolalloc/trunk:
 include/assistDS/TypeAnalysis.h include/assistDS/TypeChecks.h
 include/assistDS/TypeChecksCmpOpt.h include/assistDS/TypeChecksOpt.h
 lib/AssistDS/TypeAnalysis.cpp lib/AssistDS/TypeChecks.cpp
 lib/AssistDS/TypeChecksCmpOpt.cpp lib/AssistDS/TypeChecksOpt.cpp
Message-ID: <20110621160507.284662A6C12C@llvm.org>

Author: aggarwa4
Date: Tue Jun 21 11:05:06 2011
New Revision: 133520

URL: http://llvm.org/viewvc/llvm-project?rev=133520&view=rev
Log:
Move some optimizations to the instrumentation pass
as options.
Delete the rest of the files.
Instrument the use of a load, instead of the load itself
with the check.


Removed:
    poolalloc/trunk/include/assistDS/TypeAnalysis.h
    poolalloc/trunk/include/assistDS/TypeChecksCmpOpt.h
    poolalloc/trunk/lib/AssistDS/TypeAnalysis.cpp
    poolalloc/trunk/lib/AssistDS/TypeChecksCmpOpt.cpp
Modified:
    poolalloc/trunk/include/assistDS/TypeChecks.h
    poolalloc/trunk/include/assistDS/TypeChecksOpt.h
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
    poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp

Removed: poolalloc/trunk/include/assistDS/TypeAnalysis.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeAnalysis.h?rev=133519&view=auto
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeAnalysis.h (original)
+++ poolalloc/trunk/include/assistDS/TypeAnalysis.h (removed)
@@ -1,41 +0,0 @@
-//===-- TypeAnalysis.h - Deciphers Types of loads and stores --------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This code defines a pass which clones functions which could potentially be
-// used in indirect function calls.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/Instructions.h"
-#include "llvm/Module.h"
-#include "llvm/Pass.h"
-
-namespace llvm {
-  //
-  // Class: TypeAnalysis 
-  //
-  // Description:
-  //  Implement an LLVM pass that analyses a file to say what
-  //  the type of a load/store instruction is.
-  //
-  class TypeAnalysis : public ModulePass {
-  public:
-    static char ID;
-    TypeAnalysis() : ModulePass(&ID) {}
-    virtual bool runOnModule(Module& M);
-    virtual void getAnalysisUsage(AnalysisUsage &Info) const;
-
-    const Type *getType(LoadInst *);
-    const Type *getType(StoreInst *);
-    bool isCopyingLoad(LoadInst *);
-    bool isCopyingStore(StoreInst *);
-    Value *getStoreSource(StoreInst *SI);
-  };
-}
-

Modified: poolalloc/trunk/include/assistDS/TypeChecks.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=133520&r1=133519&r2=133520&view=diff
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecks.h (original)
+++ poolalloc/trunk/include/assistDS/TypeChecks.h Tue Jun 21 11:05:06 2011
@@ -14,7 +14,6 @@
 #ifndef TYPE_CHECKS_H
 #define TYPE_CHECKS_H
 
-#include "assistDS/TypeAnalysis.h"
 #include "dsa/AddressTakenAnalysis.h"
 
 #include "llvm/Instructions.h"
@@ -47,7 +46,6 @@
 
   // Analysis from other passes.
   TargetData *TD;
-  TypeAnalysis *TA;
   AddressTakenAnalysis* addrAnalysis;
   
   unsigned int getTypeMarker(const Type*);
@@ -69,7 +67,6 @@
 
   bool visitLoadInst(Module &M, LoadInst &LI);
   bool visitStoreInst(Module &M, StoreInst &SI);
-  bool visitCopyingStoreInst(Module &M, StoreInst &SI, Value *SS);
   bool visitAllocaInst(Module &M, AllocaInst &AI);
 
   bool visitGlobal(Module &M, GlobalVariable &GV, 
@@ -97,7 +94,6 @@
 
   virtual void getAnalysisUsage(AnalysisUsage &AU) const {
     AU.addRequired<TargetData>();
-    AU.addRequired<TypeAnalysis>();
     AU.addRequired<AddressTakenAnalysis>();
   }
 

Removed: poolalloc/trunk/include/assistDS/TypeChecksCmpOpt.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecksCmpOpt.h?rev=133519&view=auto
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecksCmpOpt.h (original)
+++ poolalloc/trunk/include/assistDS/TypeChecksCmpOpt.h (removed)
@@ -1,46 +0,0 @@
-//=== TypeChecksCmpOpt.h - Remove runtime type checks for ptrs used in cmp ===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This pass removes type checks that are on values used in compares
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef TYPE_CHECKS_CMP_OPT_H
-#define TYPE_CHECKS_CMP_OPT_H
-
-#include "assistDS/TypeAnalysis.h"
-
-#include "llvm/Instructions.h"
-#include "llvm/Pass.h"
-#include "llvm/Target/TargetData.h"
-#include "llvm/Support/CallSite.h"
-
-#include <set>
-
-namespace llvm {
-
-class Type;
-class Value;
-
-class TypeChecksCmpOpt : public ModulePass {
-
-private:
-
-  std::set<Instruction *> toDelete;
-
-public:
-  static char ID;
-  TypeChecksCmpOpt() : ModulePass(&ID) {}
-  virtual bool runOnModule(Module &M);
-
-};
-
-} // End llvm namespace
-
-#endif

Modified: poolalloc/trunk/include/assistDS/TypeChecksOpt.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecksOpt.h?rev=133520&r1=133519&r2=133520&view=diff
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecksOpt.h (original)
+++ poolalloc/trunk/include/assistDS/TypeChecksOpt.h Tue Jun 21 11:05:06 2011
@@ -14,7 +14,6 @@
 #ifndef TYPE_CHECKS_OPT_H
 #define TYPE_CHECKS_OPT_H
 
-#include "assistDS/TypeAnalysis.h"
 #include "dsa/TypeSafety.h"
 #include "dsa/AddressTakenAnalysis.h"
 

Removed: poolalloc/trunk/lib/AssistDS/TypeAnalysis.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeAnalysis.cpp?rev=133519&view=auto
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeAnalysis.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeAnalysis.cpp (removed)
@@ -1,79 +0,0 @@
-//===-- TypeAnalysis.cpp - Clone Indirectly Called Functions --------------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "assistDS/TypeAnalysis.h"
-#include "llvm/Support/FormattedStream.h"
-#include "llvm/Support/Debug.h"
-
-#include <vector>
-
-using namespace llvm;
-
-// Pass ID variable
-char TypeAnalysis::ID = 0;
-
-// Register the Pass
-static RegisterPass<TypeAnalysis>
-X("type-analysis", "Get types for load/stores");
-
-//
-// Method: runOnModule()
-//
-bool
-TypeAnalysis::runOnModule(Module& M) {
-  return false;
-}
-
-const Type *
-TypeAnalysis::getType(LoadInst *LI){
-  return LI->getType();
-}
-
-const Type *
-TypeAnalysis::getType(StoreInst *SI){
-  return SI->getOperand(0)->getType();
-}
-
-bool
-TypeAnalysis::isCopyingLoad(LoadInst *LI){
-  if(LI->getNumUses() == 1) {
-    if(StoreInst *SI = dyn_cast<StoreInst>(LI->use_begin())) {
-      if(SI->getOperand(0) == LI) {
-        return true;
-      }
-    }
-  }
-  // chk if passed through argument, and then stored.
-  return false;
-}
-
-
-bool 
-TypeAnalysis::isCopyingStore(StoreInst *SI) {
-  if(SI->getOperand(0)->getNumUses() == 1) {
-    if(isa<LoadInst>(SI->getOperand(0))) {
-      return true;
-    }
-  }
-  return false;
-}
-
-Value *
-TypeAnalysis::getStoreSource(StoreInst *SI) {
-  if(LoadInst *LI = dyn_cast<LoadInst>(SI->getOperand(0))) {
-    return LI->getOperand(0);
-  }
-  return NULL;
-}
-
-
-void 
-TypeAnalysis::getAnalysisUsage(AnalysisUsage &AU) const {
-  AU.setPreservesAll();
-}

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133520&r1=133519&r2=133520&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue Jun 21 11:05:06 2011
@@ -44,6 +44,14 @@
          cl::desc("DONT Distinguish pointer types"),
          cl::Hidden,
          cl::init(false));
+  static cl::opt<bool> DisablePtrCmpChecks("no-ptr-cmp-checks",
+         cl::desc("Dont instrument cmp statements"),
+         cl::Hidden,
+         cl::init(false));
+  static cl::opt<bool> TrackAllLoads("track-all-loads",
+         cl::desc("Check at all loads irrespective of use"),
+         cl::Hidden,
+         cl::init(false));
 }
 
 static int tagCounter = 0;
@@ -58,8 +66,9 @@
 static Constant *trackInitInst;
 static Constant *trackUnInitInst;
 static Constant *trackStoreInst;
-static Constant *trackLoadInst;
+static Constant *checkTypeInst;
 static Constant *copyTypeInfo;
+static Constant *setTypeInfo;
 static Constant *RegisterArgv;
 static Constant *RegisterEnvp;
 static Constant *compareTypeAndNumber;
@@ -105,7 +114,6 @@
   bool modified = false; // Flags whether we modified the module.
 
   TD = &getAnalysis<TargetData>();
-  TA = &getAnalysis<TypeAnalysis>();
   addrAnalysis = &getAnalysis<AddressTakenAnalysis>();
 
   // Create the necessary prototypes
@@ -163,7 +171,7 @@
                                      Int64Ty, /*size*/
                                      VoidPtrTy, /*dest for type tag*/
                                      NULL);
-  trackLoadInst = M.getOrInsertFunction("checkType",
+  checkTypeInst = M.getOrInsertFunction("checkType",
                                         VoidTy,
                                         Int8Ty,/*type*/
                                         Int64Ty,/*size*/
@@ -171,6 +179,13 @@
                                         VoidPtrTy,/*ptr*/
                                         Int32Ty,/*tag*/
                                         NULL);
+  setTypeInfo = M.getOrInsertFunction("setTypeInfo",
+                                       VoidTy,
+                                       VoidPtrTy,/*dest ptr*/
+                                       VoidPtrTy,/*metadata*/
+                                       Int64Ty,/*size*/
+                                       Int32Ty,/*tag*/
+                                       NULL);
   copyTypeInfo = M.getOrInsertFunction("copyTypeInfo",
                                        VoidTy,
                                        VoidPtrTy,/*dest ptr*/
@@ -310,18 +325,10 @@
     for (inst_iterator II = inst_begin(F), IE = inst_end(F); II != IE;++II) {
       Instruction &I = *II;
       if (StoreInst *SI = dyn_cast<StoreInst>(&I)) {
-        if (TA->isCopyingStore(SI)) {
-          Value *SS = TA->getStoreSource(SI);
-          if (SS != NULL) {
-            modified |= visitCopyingStoreInst(M, *SI, SS);
-          }
-        } else {
+        if(!isa<LoadInst>(SI->getOperand(0)))
           modified |= visitStoreInst(M, *SI);
-        }
       } else if (LoadInst *LI = dyn_cast<LoadInst>(&I)) {
-        if (!TA->isCopyingLoad(LI)) {
           modified |= visitLoadInst(M, *LI);
-        }
       } else if (CallInst *CI = dyn_cast<CallInst>(&I)) {
         modified |= visitCallInst(M, *CI);
       } else if (InvokeInst *II = dyn_cast<InvokeInst>(&I)) {
@@ -590,11 +597,12 @@
     NII++;
     AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt);
     new StoreInst(NII, Counter, &*InsPt); 
-    CounterMap[NII] = Counter;
+    errs() << F->getNameStr() <<"\n";
     NII++;
     AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt);
     new StoreInst(NII, VAMDLoc, &*InsPt);
 
+    CounterMap[ValueMap[VAListArg]] = Counter;
     // Find all va_copy calls
     for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
       for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;I++) {
@@ -625,7 +633,9 @@
         if(!VI)
           continue;
         Constant *One = ConstantInt::get(Int64Ty, 1);
+        VI->getOperand(0)->stripPointerCasts()->dump();
         Value *CounterSrc = CounterMap[VI->getOperand(0)->stripPointerCasts()];
+        CounterSrc->dump();
         LoadInst *OldValue = new LoadInst(CounterSrc, "count", VI);
         Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add,
                                                        OldValue,
@@ -1976,28 +1986,56 @@
   Args1.push_back(BCI);
   Args1.push_back(getSizeConstant(LI.getType()));
   Args1.push_back(BCI_MD);
-  CallInst::Create(getTypeTag, Args1.begin(), Args1.end(), "", &LI);
-  std::vector<Value *> Args;
-  Args.push_back(getTypeMarkerConstant(&LI));
-  Args.push_back(getSizeConstant(LI.getType()));
-  Args.push_back(BCI_MD);
-  Args.push_back(BCI);
-  Args.push_back(getTagCounter());
-  CallInst::Create(trackLoadInst, Args.begin(), Args.end(), "", &LI);
-
-  /*for(Value::use_iterator II = LI.use_begin(); II != LI.use_end(); ++II) {
+  CallInst *getTypeCall = CallInst::Create(getTypeTag, Args1.begin(), Args1.end(), "", &LI);
+  if(TrackAllLoads) {
+    std::vector<Value *> Args;
+    Args.push_back(getTypeMarkerConstant(&LI));
+    Args.push_back(getSizeConstant(LI.getType()));
+    Args.push_back(BCI_MD);
+    Args.push_back(BCI);
+    Args.push_back(getTagCounter());
+    CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", &LI);
+  }
 
+  for(Value::use_iterator II = LI.use_begin(); II != LI.use_end(); ++II) {
+    if(DisablePtrCmpChecks) {
+      if(isa<CmpInst>(II)) {
+        if(LI.getType()->isPointerTy())
+          continue;
+      }
+    }
     std::vector<Value *> Args;
     Args.push_back(getTypeMarkerConstant(&LI));
     Args.push_back(getSizeConstant(LI.getType()));
     Args.push_back(BCI_MD);
     Args.push_back(BCI);
     Args.push_back(getTagCounter());
-    CallInst::Create(trackLoadInst, Args.begin(), Args.end(), "", cast<Instruction>(II.getUse().getUser()));
-  }*/
+    if(StoreInst *SI = dyn_cast<StoreInst>(II)) {
+      // Cast the pointer operand to i8* for the runtime function.
+      CastInst *BCI_Dest = BitCastInst::CreatePointerCast(SI->getPointerOperand(), VoidPtrTy, "", SI);
+
+      std::vector<Value *> Args;
+      Args.push_back(BCI_Dest);
+      Args.push_back(BCI_MD);
+      Args.push_back(getSizeConstant(SI->getOperand(0)->getType()));
+      Args.push_back(getTagCounter());
+      // Create the call to the runtime check and place it before the copying store instruction.
+      CallInst::Create(setTypeInfo, Args.begin(), Args.end(), "", SI);
+    }
+    else if(PHINode *PH = dyn_cast<PHINode>(II)) {
+      BasicBlock *BB = PH->getIncomingBlock(II);
+      CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", BB->getTerminator());
+    } else {
+      CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", cast<Instruction>(II.getUse().getUser()));
+    }
+  }
+  if(BCI_MD->getNumUses() == 1) {
+    // No uses needed checks
+    getTypeCall->eraseFromParent();
+  }
+
 
   // Create the call to the runtime check and place it before the load instruction.
-  //CallInst::Create(trackLoadInst, Args.begin(), Args.end(), "", &LI);
   numLoadChecks++;
   return true;
 }
@@ -2020,21 +2058,3 @@
   return true;
 }
 
-// Insert runtime checks before copying store instructions.
-bool TypeChecks::visitCopyingStoreInst(Module &M, StoreInst &SI, Value *SS) {
-  // Cast the pointer operand to i8* for the runtime function.
-  CastInst *BCI_Dest = BitCastInst::CreatePointerCast(SI.getPointerOperand(), VoidPtrTy, "", &SI);
-  CastInst *BCI_Src = BitCastInst::CreatePointerCast(SS, VoidPtrTy, "", &SI);
-
-  std::vector<Value *> Args;
-  Args.push_back(BCI_Dest);
-  Args.push_back(BCI_Src);
-  Args.push_back(getSizeConstant(SI.getOperand(0)->getType()));
-  Args.push_back(getTagCounter());
-
-  // Create the call to the runtime check and place it before the copying store instruction.
-  CallInst::Create(copyTypeInfo, Args.begin(), Args.end(), "", &SI);
-  numStoreChecks++;
-
-  return true;
-}

Removed: poolalloc/trunk/lib/AssistDS/TypeChecksCmpOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksCmpOpt.cpp?rev=133519&view=auto
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecksCmpOpt.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecksCmpOpt.cpp (removed)
@@ -1,97 +0,0 @@
-//===---------- TypeChecksOpt.h - Remove safe runtime type checks ---------===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This pass removes type checks that are statically proven safe
-//
-//===----------------------------------------------------------------------===//
-
-#include "assistDS/TypeChecksCmpOpt.h"
-#include "llvm/Constants.h"
-#include "llvm/Transforms/Utils/Cloning.h"
-#include "llvm/DerivedTypes.h"
-#include "llvm/Module.h"
-#include "llvm/Assembly/Writer.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/InstIterator.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Intrinsics.h"
-#include "llvm/Support/CommandLine.h"
-#include "llvm/ADT/Statistic.h"
-
-#include <set>
-#include <vector>
-
-using namespace llvm;
-
-char TypeChecksCmpOpt::ID = 0;
-
-static RegisterPass<TypeChecksCmpOpt> 
-TC("typechecks-cmp-opt", "Remove runtime type checks", false, true);
-
-// Pass statistics
-STATISTIC(numSafe,  "Number of type checks on loads used in Cmp");
-
-static const Type *VoidTy = 0;
-static const Type *Int8Ty = 0;
-static const Type *Int32Ty = 0;
-static const Type *Int64Ty = 0;
-static const PointerType *VoidPtrTy = 0;
-static Constant *trackLoadInst;
-
-bool TypeChecksCmpOpt::runOnModule(Module &M) {
-
-  // Create the necessary prototypes
-  VoidTy = IntegerType::getVoidTy(M.getContext());
-  Int8Ty = IntegerType::getInt8Ty(M.getContext());
-  Int32Ty = IntegerType::getInt32Ty(M.getContext());
-  Int64Ty = IntegerType::getInt64Ty(M.getContext());
-  VoidPtrTy = PointerType::getUnqual(Int8Ty);
-
-  trackLoadInst = M.getOrInsertFunction("trackLoadInst",
-                                        VoidTy,
-                                        VoidPtrTy,/*ptr*/
-                                        Int8Ty,/*type*/
-                                        Int64Ty,/*size*/
-                                        Int32Ty,/*tag*/
-                                        NULL);
-  for(Value::use_iterator User = trackLoadInst->use_begin(); User != trackLoadInst->use_end(); ++User) {
-    CallInst *CI = dyn_cast<CallInst>(User);
-    assert(CI);
-    Value *LPtr = CI->getOperand(1)->stripPointerCasts();
-    for(Value::use_iterator II = LPtr->use_begin(); II != LPtr->use_end(); ++II) {
-      if(LoadInst *LI = dyn_cast<LoadInst>(II)) {
-        if(LI->getOperand(0) == LPtr) {
-          if(LI->getType()->isPointerTy()) {
-            bool allIcmpUse = true;
-            for(Value::use_iterator EE = LI->use_begin(); EE != LI->use_end(); ++EE) {
-              if(!isa<ICmpInst>(EE)) {
-                allIcmpUse = false;
-                break;
-              }
-            }
-            if(allIcmpUse) {
-              toDelete.insert(CI);
-              LI->dump();
-            }
-          }
-        }
-      }
-    }
-  }
-
-  numSafe += toDelete.size();
-
-  std::set<Instruction*>::iterator II = toDelete.begin();
-  for(; II != toDelete.end();) {
-    Instruction *I = *II++;
-    I->eraseFromParent();
-  }
-  return (numSafe > 0);
-}
-

Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=133520&r1=133519&r2=133520&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Tue Jun 21 11:05:06 2011
@@ -49,6 +49,8 @@
 static Constant *trackStoreInst;
 static Constant *trackLoadInst;
 static Constant *copyTypeInfo;
+static Constant *setTypeInfo;
+static Constant *checkTypeInst;
 static Constant *MallocFunc;
 
 bool TypeChecksOpt::runOnModule(Module &M) {
@@ -94,6 +96,14 @@
                                          Int64Ty,/*size*/
                                          Int32Ty,/*tag*/
                                          NULL);
+  checkTypeInst = M.getOrInsertFunction("checkType",
+                                        VoidTy,
+                                        Int8Ty,/*type*/
+                                        Int64Ty,/*size*/
+                                        VoidPtrTy,
+                                        VoidPtrTy,/*ptr*/
+                                        Int32Ty,/*tag*/
+                                        NULL);
   trackLoadInst = M.getOrInsertFunction("trackLoadInst",
                                         VoidTy,
                                         VoidPtrTy,/*ptr*/
@@ -108,6 +118,13 @@
                                        Int64Ty,/*size*/
                                        Int32Ty,/*tag*/
                                        NULL);
+  setTypeInfo = M.getOrInsertFunction("setTypeInfo",
+                                       VoidTy,
+                                       VoidPtrTy,/*dest ptr*/
+                                       VoidPtrTy,/*metadata*/
+                                       Int64Ty,/*size*/
+                                       Int32Ty,/*tag*/
+                                       NULL);
   trackStringInput = M.getOrInsertFunction("trackStringInput",
                                            VoidTy,
                                            VoidPtrTy,
@@ -128,11 +145,11 @@
     }
   }
 
-  for(Value::use_iterator User = trackLoadInst->use_begin(); User != trackLoadInst->use_end(); ++User) {
+  for(Value::use_iterator User = checkTypeInst->use_begin(); User != checkTypeInst->use_end(); ++User) {
     CallInst *CI = dyn_cast<CallInst>(User);
     assert(CI);
     
-    if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) {
+    if(TS->isTypeSafe(CI->getOperand(4)->stripPointerCasts(), CI->getParent()->getParent())) {
       toDelete.push_back(CI);
     }
   }
@@ -195,6 +212,19 @@
       toDelete.push_back(CI);
     }
   }
+  for(Value::use_iterator User = setTypeInfo->use_begin(); User != setTypeInfo->use_end(); ++User) {
+    CallInst *CI = dyn_cast<CallInst>(User);
+    assert(CI);
+
+    if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) {
+      std::vector<Value*> Args;
+      Args.push_back(CI->getOperand(1));
+      Args.push_back(CI->getOperand(3)); // size
+      Args.push_back(CI->getOperand(4));
+      CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", CI);
+      toDelete.push_back(CI);
+    }
+  }
 
   numSafe += toDelete.size();
 



From rjmccall at apple.com  Tue Jun 21 12:00:06 2011
From: rjmccall at apple.com (John McCall)
Date: Tue, 21 Jun 2011 10:00:06 -0700
Subject: [llvm-commits] [llvm] r133285	-
 /llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp
In-Reply-To: <4E008742.9030700@free.fr>
References: <20110617202152.D6B812A6C12C@llvm.org> <4DFDF276.5030703@free.fr>
	<54E09593-01A1-4936-AFF8-7AF19D2C6919@apple.com>
	<4DFEF6DA.4030503@free.fr>
	<BEFDFA5B-4D83-47A5-A967-02ADE979F770@apple.com>
	<4E008742.9030700@free.fr>
Message-ID: <07078D47-26CC-49FB-B53F-478A74D8A0FB@apple.com>

On Jun 21, 2011, at 4:57 AM, Duncan Sands wrote:
> I thought *you* were suggesting that we assume no overflow when you said "but
> if we just assume by fiat that 2^31 is too large, then as long as the arithmetic
> is being done in some reasonable size then we know that N * sizeof(T) isn't
> permitted to signed overflow, either."  I guess I misunderstood.  I'm still not
> sure what you were trying to say :)

I was suggesting that we could make more aggressive restrictions on the
size input to alloca based on a basic assumption that you can't grow your stack
to >2GB, even on >32-bit architectures.  But if we want to support that, then
obviously this needs to be based on the pointer width.

>  That's the whole point of this discussion.
>> There's an implicit multiply in sizeof(sp) as part of the alloca instruction, and
>> it's undefined behavior if either
>>   - that multiply causes unsigned overflow or
> 
> Sure.
> 
>>   - either the input or output to that multiply is negative.
> 
> Why?  Are you saying that an alloca of 2^31 i8's should be considered to result
> in undefined behaviour?

On a 32-bit machine, yes.  Are you really saying that we need to
support any argument to alloca that's smaller than the addressable
space of the machine?

If so, this transformation is completely dead;  feel free to remove it.

>  And what about this: alloca i8, i8 128

I did say "in sizeof(sp)" above.

John.

From rjmccall at apple.com  Tue Jun 21 12:01:29 2011
From: rjmccall at apple.com (John McCall)
Date: Tue, 21 Jun 2011 10:01:29 -0700
Subject: [llvm-commits] [llvm] r133285	-
 /llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp
In-Reply-To: <4E008742.9030700@free.fr>
References: <20110617202152.D6B812A6C12C@llvm.org> <4DFDF276.5030703@free.fr>
	<54E09593-01A1-4936-AFF8-7AF19D2C6919@apple.com>
	<4DFEF6DA.4030503@free.fr>
	<BEFDFA5B-4D83-47A5-A967-02ADE979F770@apple.com>
	<4E008742.9030700@free.fr>
Message-ID: <44CEB331-FBEC-4A3F-B171-BCEFCED6A3D8@apple.com>

On Jun 21, 2011, at 4:57 AM, Duncan Sands wrote:
> I thought *you* were suggesting that we assume no overflow when you said "but
> if we just assume by fiat that 2^31 is too large, then as long as the arithmetic
> is being done in some reasonable size then we know that N * sizeof(T) isn't
> permitted to signed overflow, either."  I guess I misunderstood.  I'm still not
> sure what you were trying to say :)

I was suggesting that we could make more aggressive restrictions on the
size input to alloca based on a basic assumption that you can't grow your stack
to >2GB, even on >32-bit architectures.  But if we want to support that, then
obviously this needs to be based on the pointer width.

> That's the whole point of this discussion.
>> There's an implicit multiply in sizeof(sp) as part of the alloca instruction, and
>> it's undefined behavior if either
>>  - that multiply causes unsigned overflow or
> 
> Sure.
> 
>>  - either the input or output to that multiply is negative.
> 
> Why?  Are you saying that an alloca of 2^31 i8's should be considered to result
> in undefined behaviour?

On a 32-bit machine, yes.  Are you really saying that we need to
support any argument to alloca that's smaller than the addressable
space of the machine?

If so, this transformation is completely dead;  feel free to remove it.

> And what about this: alloca i8, i8 128

I did say "in sizeof(sp)" above.

John.

From rjmccall at apple.com  Tue Jun 21 12:09:18 2011
From: rjmccall at apple.com (John McCall)
Date: Tue, 21 Jun 2011 10:09:18 -0700
Subject: [llvm-commits] [llvm] r133412 - in /llvm/trunk:
 include/llvm/Constants.h lib/Analysis/ConstantFolding.cpp
 lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp
 lib/CodeGen/ShadowStackGC.cpp lib/Transforms/IPO/GlobalOpt.cpp
 lib/Transform
In-Reply-To: <BANLkTi=KOpcn0CwHfObMA+Z7eakrgTWafwBPBt2XVjR36GTphA@mail.gmail.com>
References: <BANLkTimBn5-=U7Re=p4gkh7CE3A7N5gf=Y+w6MD2teoEXDer6Q@mail.gmail.com>
	<6ACAF514-D83B-46F3-BBD9-13F295FB1FA2@nondot.org>
	<BANLkTi=KOpcn0CwHfObMA+Z7eakrgTWafwBPBt2XVjR36GTphA@mail.gmail.com>
Message-ID: <31BCDD79-78B7-4F94-AD16-AA8290D140D1@apple.com>

On Jun 21, 2011, at 12:22 AM, Jay Foad wrote:
>>> Patch 1 extends ConstantUniqueMap with a new template parameter
>>> ValRefType, representing a const reference to ValType. Normally this
>>> would just be const ValType&, but when ValType is a std::vector, we
>>> want to use ArrayRef as the reference type.
> 
>> Wow, looks great to me Jay
> 
> Just to double check, are you OK with me adding the conversion operator
> 
>  ArrayRef<T>::operator std::vector<T>() const;

This is best avoided if possible.

John.

From ganna at apple.com  Tue Jun 21 12:18:15 2011
From: ganna at apple.com (Anna Zaks)
Date: Tue, 21 Jun 2011 17:18:15 -0000
Subject: [llvm-commits] [llvm] r133522 - in /llvm/trunk:
 lib/Target/CBackend/CBackend.cpp
 test/CodeGen/CBackend/2011-06-08-addWithOverflow.ll
Message-ID: <20110621171815.3E9482A6C12C@llvm.org>

Author: zaks
Date: Tue Jun 21 12:18:15 2011
New Revision: 133522

URL: http://llvm.org/viewvc/llvm-project?rev=133522&view=rev
Log:
Add support for sadd.with.overflow and uadd.with.overflow intrinsics to the CBackend by emitting definitions for each intrinsic that occurs in the module.

Added:
    llvm/trunk/test/CodeGen/CBackend/2011-06-08-addWithOverflow.ll
Modified:
    llvm/trunk/lib/Target/CBackend/CBackend.cpp

Modified: llvm/trunk/lib/Target/CBackend/CBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CBackend.cpp?rev=133522&r1=133521&r2=133522&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CBackend/CBackend.cpp (original)
+++ llvm/trunk/lib/Target/CBackend/CBackend.cpp Tue Jun 21 12:18:15 2011
@@ -205,6 +205,9 @@
     std::string InterpretASMConstraint(InlineAsm::ConstraintInfo& c);
 
     void lowerIntrinsics(Function &F);
+    /// Prints the definition of the intrinsic function F. Supports the 
+    /// intrinsics which need to be explicitly defined in the CBackend.
+    void printIntrinsicDefinition(const Function &F, raw_ostream &Out);
 
     void printModuleTypes(const TypeSymbolTable &ST);
     void printContainedStructs(const Type *Ty, std::set<const Type *> &);
@@ -1777,6 +1780,7 @@
   Out << "/* Provide Declarations */\n";
   Out << "#include <stdarg.h>\n";      // Varargs support
   Out << "#include <setjmp.h>\n";      // Unwind support
+  Out << "#include <limits.h>\n";      // With overflow intrinsics support.
   generateCompilerSpecificCode(Out, TD);
 
   // Provide a definition for `bool' if not compiling with a C++ compiler.
@@ -1855,29 +1859,46 @@
   Out << "float fmodf(float, float);\n";
   Out << "long double fmodl(long double, long double);\n";
 
+  // Store the intrinsics which will be declared/defined below.
+  SmallVector<const Function*, 8> intrinsicsToDefine;
+
   for (Module::iterator I = M.begin(), E = M.end(); I != E; ++I) {
     // Don't print declarations for intrinsic functions.
-    if (!I->isIntrinsic() && I->getName() != "setjmp" &&
-        I->getName() != "longjmp" && I->getName() != "_setjmp") {
-      if (I->hasExternalWeakLinkage())
-        Out << "extern ";
-      printFunctionSignature(I, true);
-      if (I->hasWeakLinkage() || I->hasLinkOnceLinkage())
-        Out << " __ATTRIBUTE_WEAK__";
-      if (I->hasExternalWeakLinkage())
-        Out << " __EXTERNAL_WEAK__";
-      if (StaticCtors.count(I))
-        Out << " __ATTRIBUTE_CTOR__";
-      if (StaticDtors.count(I))
-        Out << " __ATTRIBUTE_DTOR__";
-      if (I->hasHiddenVisibility())
-        Out << " __HIDDEN__";
+    // Store the used intrinsics, which need to be explicitly defined.
+    if (I->isIntrinsic()) {
+      switch (I->getIntrinsicID()) {
+        default:
+          break;
+        case Intrinsic::uadd_with_overflow:
+        case Intrinsic::sadd_with_overflow:
+          intrinsicsToDefine.push_back(I);
+          break;
+      }
+      continue;
+    }
 
-      if (I->hasName() && I->getName()[0] == 1)
-        Out << " LLVM_ASM(\"" << I->getName().substr(1) << "\")";
+    if (I->getName() == "setjmp" ||
+        I->getName() == "longjmp" || I->getName() == "_setjmp")
+      continue;
+
+    if (I->hasExternalWeakLinkage())
+      Out << "extern ";
+    printFunctionSignature(I, true);
+    if (I->hasWeakLinkage() || I->hasLinkOnceLinkage())
+      Out << " __ATTRIBUTE_WEAK__";
+    if (I->hasExternalWeakLinkage())
+      Out << " __EXTERNAL_WEAK__";
+    if (StaticCtors.count(I))
+      Out << " __ATTRIBUTE_CTOR__";
+    if (StaticDtors.count(I))
+      Out << " __ATTRIBUTE_DTOR__";
+    if (I->hasHiddenVisibility())
+      Out << " __HIDDEN__";
 
-      Out << ";\n";
-    }
+    if (I->hasName() && I->getName()[0] == 1)
+      Out << " LLVM_ASM(\"" << I->getName().substr(1) << "\")";
+
+    Out << ";\n";
   }
 
   // Output the global variable declarations
@@ -2012,6 +2033,14 @@
   Out << "return X <= Y ; }\n";
   Out << "static inline int llvm_fcmp_oge(double X, double Y) { ";
   Out << "return X >= Y ; }\n";
+
+  // Emit definitions of the intrinsics.
+  for (SmallVector<const Function*, 8>::const_iterator
+       I = intrinsicsToDefine.begin(),
+       E = intrinsicsToDefine.end(); I != E; ++I) {
+    printIntrinsicDefinition(**I, Out);
+  }
+
   return false;
 }
 
@@ -2786,6 +2815,101 @@
   Out << "))";
 }
 
+// Returns the macro name or value of the max or min of an integer type
+// (as defined in limits.h).
+static void printLimitValue(const IntegerType &Ty, bool isSigned, bool isMax,
+                            raw_ostream &Out) {
+  const char* type;
+  const char* sprefix = "";
+
+  unsigned NumBits = Ty.getBitWidth();
+  if (NumBits <= 8) {
+    type = "CHAR";
+    sprefix = "S";
+  } else if (NumBits <= 16) {
+    type = "SHRT";
+  } else if (NumBits <= 32) {
+    type = "INT";
+  } else if (NumBits <= 64) {
+    type = "LLONG";
+  } else {
+    llvm_unreachable("Bit widths > 64 not implemented yet");
+  }
+
+  if (isSigned)
+    Out << sprefix << type << (isMax ? "_MAX" : "_MIN");
+  else
+    Out << "U" << type << (isMax ? "_MAX" : "0");
+}
+
+static bool isSupportedIntegerSize(const IntegerType &T) {
+  return T.getBitWidth() == 8 || T.getBitWidth() == 16 ||
+         T.getBitWidth() == 32 || T.getBitWidth() == 64;
+}
+
+void CWriter::printIntrinsicDefinition(const Function &F, raw_ostream &Out) {
+  const FunctionType *funT = F.getFunctionType();
+  const Type *retT = F.getReturnType();
+  const IntegerType *elemT = cast<IntegerType>(funT->getParamType(1));
+
+  assert(isSupportedIntegerSize(*elemT) &&
+         "CBackend does not support arbitrary size integers.");
+  assert(cast<StructType>(retT)->getElementType(0) == elemT &&
+         elemT == funT->getParamType(0) && funT->getNumParams() == 2);
+
+  switch (F.getIntrinsicID()) {
+  default:
+    llvm_unreachable("Unsupported Intrinsic.");
+  case Intrinsic::uadd_with_overflow:
+    // static inline Rty uadd_ixx(unsigned ixx a, unsigned ixx b) {
+    //   Rty r;
+    //   r.field0 = a + b;
+    //   r.field1 = (r.field0 < a);
+    //   return r;
+    // }
+    Out << "static inline ";
+    printType(Out, retT);
+    Out << GetValueName(&F);
+    Out << "(";
+    printSimpleType(Out, elemT, false);
+    Out << "a,";
+    printSimpleType(Out, elemT, false);
+    Out << "b) {\n  ";
+    printType(Out, retT);
+    Out << "r;\n";
+    Out << "  r.field0 = a + b;\n";
+    Out << "  r.field1 = (r.field0 < a);\n";
+    Out << "  return r;\n}\n";
+    break;
+    
+  case Intrinsic::sadd_with_overflow:            
+    // static inline Rty sadd_ixx(ixx a, ixx b) {
+    //   Rty r;
+    //   r.field1 = (b > 0 && a > XX_MAX - b) ||
+    //              (b < 0 && a < XX_MIN - b);
+    //   r.field0 = r.field1 ? 0 : a + b;
+    //   return r;
+    // }
+    Out << "static ";
+    printType(Out, retT);
+    Out << GetValueName(&F);
+    Out << "(";
+    printSimpleType(Out, elemT, true);
+    Out << "a,";
+    printSimpleType(Out, elemT, true);
+    Out << "b) {\n  ";
+    printType(Out, retT);
+    Out << "r;\n";
+    Out << "  r.field1 = (b > 0 && a > ";
+    printLimitValue(*elemT, true, true, Out);
+    Out << " - b) || (b < 0 && a < ";
+    printLimitValue(*elemT, true, false, Out);
+    Out << " - b);\n";
+    Out << "  r.field0 = r.field1 ? 0 : a + b;\n";
+    Out << "  return r;\n}\n";
+    break;
+  }
+}
 
 void CWriter::lowerIntrinsics(Function &F) {
   // This is used to keep track of intrinsics that get generated to a lowered
@@ -2816,6 +2940,8 @@
           case Intrinsic::x86_sse2_cmp_sd:
           case Intrinsic::x86_sse2_cmp_pd:
           case Intrinsic::ppc_altivec_lvsl:
+          case Intrinsic::uadd_with_overflow:
+          case Intrinsic::sadd_with_overflow:
               // We directly implement these intrinsics
             break;
           default:
@@ -3109,6 +3235,14 @@
     writeOperand(I.getArgOperand(0));
     Out << ")";
     return true;
+  case Intrinsic::uadd_with_overflow:
+  case Intrinsic::sadd_with_overflow:
+    Out << GetValueName(I.getCalledFunction()) << "(";
+    writeOperand(I.getArgOperand(0));
+    Out << ", ";
+    writeOperand(I.getArgOperand(1));
+    Out << ")";
+    return true;
   }
 }
 

Added: llvm/trunk/test/CodeGen/CBackend/2011-06-08-addWithOverflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/CBackend/2011-06-08-addWithOverflow.ll?rev=133522&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/CBackend/2011-06-08-addWithOverflow.ll (added)
+++ llvm/trunk/test/CodeGen/CBackend/2011-06-08-addWithOverflow.ll Tue Jun 21 12:18:15 2011
@@ -0,0 +1,35 @@
+; RUN: llc < %s -march=c
+; Check that uadd and sadd with overflow are handled by C Backend.
+
+%0 = type { i32, i1 }        ; type %0
+
+define i1 @func1(i32 zeroext %v1, i32 zeroext %v2) nounwind {
+entry:
+    %t = call %0 @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)     ; <%0> [#uses=1]
+    %obit = extractvalue %0 %t, 1       ; <i1> [#uses=1]
+    br i1 %obit, label %carry, label %normal
+
+normal:     ; preds = %entry
+    ret i1 true
+
+carry:      ; preds = %entry
+    ret i1 false
+}
+
+define i1 @func2(i32 signext %v1, i32 signext %v2) nounwind {
+entry:
+    %t = call %0 @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)     ; <%0> [#uses=1]
+    %obit = extractvalue %0 %t, 1       ; <i1> [#uses=1]
+    br i1 %obit, label %carry, label %normal
+
+normal:     ; preds = %entry
+    ret i1 true
+
+carry:      ; preds = %entry
+    ret i1 false
+}
+
+declare %0 @llvm.sadd.with.overflow.i32(i32, i32) nounwind
+
+declare %0 @llvm.uadd.with.overflow.i32(i32, i32) nounwind
+



From eli.friedman at gmail.com  Tue Jun 21 12:32:12 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 21 Jun 2011 10:32:12 -0700
Subject: [llvm-commits] [llvm] r133240 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
In-Reply-To: <20110617055451.24CFF2A6C12C@llvm.org>
References: <20110617055451.24CFF2A6C12C@llvm.org>
Message-ID: <BANLkTikGbW-G3soeku5b8U6mw31MOiE-=+LOqJ+jkbAjja0qAg@mail.gmail.com>

On Thu, Jun 16, 2011 at 10:54 PM, Rafael Espindola
<rafael.espindola at gmail.com> wrote:
> Author: rafael
> Date: Fri Jun 17 00:54:50 2011
> New Revision: 133240
>
> URL: http://llvm.org/viewvc/llvm-project?rev=133240&view=rev
> Log:
> Enable early duplication of small blocks. There are still improvements to
> be made, but this is already a win.
>
> Modified:
> ? ?llvm/trunk/lib/CodeGen/TailDuplication.cpp

This commit appears to be causing a significant performance regression
on a couple tests in the test-suite for x86-32;
test-suite/SingleSource/Benchmarks/Shootout-C++/matrix.cpp is a good
example (3.3s before, 4.1s after).  Would you mind taking a look to
see if anything unexpected is happening?

-Eli


From jay.foad at gmail.com  Tue Jun 21 12:34:11 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 21 Jun 2011 18:34:11 +0100
Subject: [llvm-commits] [llvm] r133412 - in /llvm/trunk:
 include/llvm/Constants.h lib/Analysis/ConstantFolding.cpp
 lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp
 lib/CodeGen/ShadowStackGC.cpp lib/Transforms/IPO/GlobalOpt.cpp
 lib/Transform
In-Reply-To: <31BCDD79-78B7-4F94-AD16-AA8290D140D1@apple.com>
References: <BANLkTimBn5-=U7Re=p4gkh7CE3A7N5gf=Y+w6MD2teoEXDer6Q@mail.gmail.com>
	<6ACAF514-D83B-46F3-BBD9-13F295FB1FA2@nondot.org>
	<BANLkTi=KOpcn0CwHfObMA+Z7eakrgTWafwBPBt2XVjR36GTphA@mail.gmail.com>
	<31BCDD79-78B7-4F94-AD16-AA8290D140D1@apple.com>
Message-ID: <BANLkTinL=WKbepnXXN+WRqjRRW0hCOr8MQ@mail.gmail.com>

On 21 June 2011 18:09, John McCall <rjmccall at apple.com> wrote:
> On Jun 21, 2011, at 12:22 AM, Jay Foad wrote:
>>>> Patch 1 extends ConstantUniqueMap with a new template parameter
>>>> ValRefType, representing a const reference to ValType. Normally this
>>>> would just be const ValType&, but when ValType is a std::vector, we
>>>> want to use ArrayRef as the reference type.
>>
>>> Wow, looks great to me Jay
>>
>> Just to double check, are you OK with me adding the conversion operator
>>
>> ?ArrayRef<T>::operator std::vector<T>() const;
>
> This is best avoided if possible.

Any particular reason? Any alternative suggestions?

Thanks,
Jay.


From bob.wilson at apple.com  Tue Jun 21 12:35:14 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 21 Jun 2011 17:35:14 -0000
Subject: [llvm-commits] [llvm] r133524 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/bitcast2.ll
 test/CodeGen/X86/vec_set-8.ll test/CodeGen/X86/vec_set-9.ll
 test/CodeGen/X86/vec_set-C.ll test/CodeGen/X86/vec_shuffle-14.ll
 test/CodeGen/X86/vec_shuffle-17.ll test/MC/X86/x86-64.s
 test/MC/X86/x86_64-avx-encoding.s
Message-ID: <20110621173514.37DDA2A6C12C@llvm.org>

Author: bwilson
Date: Tue Jun 21 12:35:13 2011
New Revision: 133524

URL: http://llvm.org/viewvc/llvm-project?rev=133524&view=rev
Log:
Revert r133452: "Emit movq for 64-bit register to XMM register moves..."

This is breaking compiler-rt and llvm-gcc builds on MacOSX when not using
the integrated assembler.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/CodeGen/X86/bitcast2.ll
    llvm/trunk/test/CodeGen/X86/vec_set-8.ll
    llvm/trunk/test/CodeGen/X86/vec_set-9.ll
    llvm/trunk/test/CodeGen/X86/vec_set-C.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll
    llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll
    llvm/trunk/test/MC/X86/x86-64.s
    llvm/trunk/test/MC/X86/x86_64-avx-encoding.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 21 12:35:13 2011
@@ -2850,11 +2850,11 @@
                       [(set VR128:$dst,
                         (v4i32 (scalar_to_vector (loadi32 addr:$src))))]>;
 def MOV64toPQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
-                        "movq\t{$src, $dst|$dst, $src}",
+                        "mov{d|q}\t{$src, $dst|$dst, $src}",
                         [(set VR128:$dst,
                           (v2i64 (scalar_to_vector GR64:$src)))]>;
 def MOV64toSDrr : RPDI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
-                       "movq\t{$src, $dst|$dst, $src}",
+                       "mov{d|q}\t{$src, $dst|$dst, $src}",
                        [(set FR64:$dst, (bitconvert GR64:$src))]>;
 
 
@@ -2895,7 +2895,7 @@
                                      (iPTR 0))), addr:$dst)]>;
 
 def MOVPQIto64rr  : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
-                         "movq\t{$src, $dst|$dst, $src}",
+                         "mov{d|q}\t{$src, $dst|$dst, $src}",
                          [(set GR64:$dst, (vector_extract (v2i64 VR128:$src),
                                            (iPTR 0)))]>;
 def MOV64toSDrm : S3SI<0x7E, MRMSrcMem, (outs FR64:$dst), (ins i64mem:$src),
@@ -2903,7 +2903,7 @@
                        [(set FR64:$dst, (bitconvert (loadi64 addr:$src)))]>;
 
 def MOVSDto64rr  : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
-                        "movq\t{$src, $dst|$dst, $src}",
+                        "mov{d|q}\t{$src, $dst|$dst, $src}",
                         [(set GR64:$dst, (bitconvert FR64:$src))]>;
 def MOVSDto64mr  : RPDI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
                         "movq\t{$src, $dst|$dst, $src}",
@@ -2931,7 +2931,7 @@
                                       (v4i32 (scalar_to_vector GR32:$src)))))]>,
                                       VEX;
 def VMOVZQI2PQIrr : VPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
-                       "movq\t{$src, $dst|$dst, $src}", // X86-64 only
+                       "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
                        [(set VR128:$dst, (v2i64 (X86vzmovl
                                       (v2i64 (scalar_to_vector GR64:$src)))))]>,
                                       VEX, VEX_W;
@@ -2942,7 +2942,7 @@
                        [(set VR128:$dst, (v4i32 (X86vzmovl
                                       (v4i32 (scalar_to_vector GR32:$src)))))]>;
 def MOVZQI2PQIrr : RPDI<0x6E, MRMSrcReg, (outs VR128:$dst), (ins GR64:$src),
-                       "movq\t{$src, $dst|$dst, $src}", // X86-64 only
+                       "mov{d|q}\t{$src, $dst|$dst, $src}", // X86-64 only
                        [(set VR128:$dst, (v2i64 (X86vzmovl
                                       (v2i64 (scalar_to_vector GR64:$src)))))]>;
 }
@@ -2968,21 +2968,6 @@
             (MOVZDI2PDIrm addr:$src)>;
 }
 
-// We used to emit this syntax to work around a bug in the Darwin assembler,
-// so we'll continue to assemble it.
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
-                (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
-                (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
-                (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
-                (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
-                (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
-def : InstAlias<"movd\t{$src, $dst|$dst, $src}",
-                (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
-
 //===---------------------------------------------------------------------===//
 // SSE2 - Move Quadword
 //===---------------------------------------------------------------------===//

Modified: llvm/trunk/test/CodeGen/X86/bitcast2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bitcast2.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bitcast2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bitcast2.ll Tue Jun 21 12:35:13 2011
@@ -1,31 +1,13 @@
-; RUN: llc < %s -march=x86-64 | FileCheck %s
+; RUN: llc < %s -march=x86-64 | grep movd | count 2
 ; RUN: llc < %s -march=x86-64 | not grep rsp
 
 define i64 @test1(double %A) {
-; CHECK: test1
-; CHECK: movq
    %B = bitcast double %A to i64
    ret i64 %B
 }
 
 define double @test2(i64 %A) {
-; CHECK: test2
-; CHECK: movq
    %B = bitcast i64 %A to double
    ret double %B
 }
 
-define i32 @test3(float %A) {
-; CHECK: test3
-; CHECK: movd
-   %B = bitcast float %A to i32
-   ret i32 %B
-}
-
-define float @test4(i32 %A) {
-; CHECK: test4
-; CHECK: movd
-   %B = bitcast i32 %A to float
-   ret float %B
-}
-

Modified: llvm/trunk/test/CodeGen/X86/vec_set-8.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-8.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-8.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-8.ll Tue Jun 21 12:35:13 2011
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
 ; CHECK-NOT: movsd
-; CHECK: movq {{%rdi|%rcx}}, %xmm0
+; CHECK: movd {{%rdi|%rcx}}, %xmm0
 ; CHECK-NOT: movsd
 
 define <2 x i64> @test(i64 %i) nounwind  {

Modified: llvm/trunk/test/CodeGen/X86/vec_set-9.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-9.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-9.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-9.ll Tue Jun 21 12:35:13 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=x86-64 | grep movq | count 1
+; RUN: llc < %s -march=x86-64 | grep movd | count 1
 ; RUN: llc < %s -march=x86-64 | grep {movlhps.*%xmm0, %xmm0}
 
 define <2 x i64> @test3(i64 %A) nounwind {

Modified: llvm/trunk/test/CodeGen/X86/vec_set-C.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_set-C.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_set-C.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_set-C.ll Tue Jun 21 12:35:13 2011
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movq
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep mov | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd
 
 define <2 x i64> @t1(i64 %x) nounwind  {
 	%tmp8 = insertelement <2 x i64> zeroinitializer, i64 %x, i32 0

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-14.ll Tue Jun 21 12:35:13 2011
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse2
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | grep movd | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 1
-; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 4
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movd | count 2
+; RUN: llc < %s -march=x86-64 -mattr=+sse2 | grep movq | count 3
 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep xor
 
 define <4 x i32> @t1(i32 %a) nounwind  {

Modified: llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll (original)
+++ llvm/trunk/test/CodeGen/X86/vec_shuffle-17.ll Tue Jun 21 12:35:13 2011
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=x86_64-linux | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s
 ; CHECK-NOT: xor
-; CHECK: movq {{%rdi|%rcx}}, %xmm0
+; CHECK: movd {{%rdi|%rcx}}, %xmm0
 ; CHECK-NOT: xor
 ; PR2108
 

Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Tue Jun 21 12:35:13 2011
@@ -1128,11 +1128,3 @@
 // CHECK: strq
 // CHECK: encoding: [0x48,0x0f,0x00,0xc8]
 	str %rax
-
-// CHECK: movq %rdi, %xmm0
-// CHECK: encoding: [0x66,0x48,0x0f,0x6e,0xc7]
-	movq %rdi,%xmm0
-
-// CHECK: movq %rdi, %xmm0
-// CHECK: encoding: [0x66,0x48,0x0f,0x6e,0xc7]
-	movd %rdi,%xmm0

Modified: llvm/trunk/test/MC/X86/x86_64-avx-encoding.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86_64-avx-encoding.s?rev=133524&r1=133523&r2=133524&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86_64-avx-encoding.s (original)
+++ llvm/trunk/test/MC/X86/x86_64-avx-encoding.s Tue Jun 21 12:35:13 2011
@@ -1444,9 +1444,9 @@
 // CHECK: encoding: [0xc5,0x79,0x7e,0x30]
           vmovd  %xmm14, (%rax)
 
-// CHECK: vmovd  %eax, %xmm14
-// CHECK: encoding: [0xc5,0x79,0x6e,0xf0]
-          vmovd  %eax, %xmm14
+// CHECK: vmovd  %rax, %xmm14
+// CHECK: encoding: [0xc4,0x61,0xf9,0x6e,0xf0]
+          vmovd  %rax, %xmm14
 
 // CHECK: vmovq  %xmm14, (%rax)
 // CHECK: encoding: [0xc5,0x79,0xd6,0x30]



From bob.wilson at apple.com  Tue Jun 21 12:41:28 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Tue, 21 Jun 2011 10:41:28 -0700
Subject: [llvm-commits] [llvm] r133452 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/CodeGen/X86/bitcast2.ll
 test/CodeGen/X86/vec_set-8.ll test/CodeGen/X86/vec_set-9.ll
 test/CodeGen/X86/vec_set-C.ll test/CodeGen/X86/vec_shuffle-14.ll
 test/CodeGen/X86/vec_shuffle-17.ll test/MC/X86/x86-64.s
 test/MC/X86/x86_64-avx-encoding.s
In-Reply-To: <4DFFE225.5010807@mymail.mines.edu>
References: <20110620183327.3F55D2A6C12C@llvm.org>
	<4DFFE225.5010807@mymail.mines.edu>
Message-ID: <717AC852-C537-4E0D-897A-A5CCD813C011@apple.com>


On Jun 20, 2011, at 5:13 PM, Charles Davis wrote:

> On 6/20/11 12:33 PM, Nick Lewycky wrote:
>> Author: nicholas
>> Date: Mon Jun 20 13:33:26 2011
>> New Revision: 133452
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=133452&view=rev
>> Log:
>> Emit movq for 64-bit register to XMM register moves, but continue to accept
>> movd when assembling.
> This breaks compiling compiler-rt on Mac OS X like so:
> 
> /tmp/cc-E8HNBz.s:7:suffix or operands invalid for `movq'
> clang: error: assembler command failed with exit code 1 (use -v to see
> invocation)
> make[5]: ***
> [.../llvm/build1/tools/clang/runtime/compiler-rt/clang_darwin/cc_kext/x86_64/SubDir.lib/fixdfti.o]
> Error 1
> 
> There are several more errors like that.
> 
> Xcode 4.0's assembler still has the movq bug. We still have to produce
> movd on Darwin when not using the integrated assembler.

Yes, it's also breaking llvm-gcc building.  I've reverted that change for now.

From rjmccall at apple.com  Tue Jun 21 12:45:38 2011
From: rjmccall at apple.com (John McCall)
Date: Tue, 21 Jun 2011 10:45:38 -0700
Subject: [llvm-commits] [llvm] r133412 - in /llvm/trunk:
 include/llvm/Constants.h lib/Analysis/ConstantFolding.cpp
 lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp
 lib/CodeGen/ShadowStackGC.cpp lib/Transforms/IPO/GlobalOpt.cpp
 lib/Transform
In-Reply-To: <BANLkTinL=WKbepnXXN+WRqjRRW0hCOr8MQ@mail.gmail.com>
References: <BANLkTimBn5-=U7Re=p4gkh7CE3A7N5gf=Y+w6MD2teoEXDer6Q@mail.gmail.com>
	<6ACAF514-D83B-46F3-BBD9-13F295FB1FA2@nondot.org>
	<BANLkTi=KOpcn0CwHfObMA+Z7eakrgTWafwBPBt2XVjR36GTphA@mail.gmail.com>
	<31BCDD79-78B7-4F94-AD16-AA8290D140D1@apple.com>
	<BANLkTinL=WKbepnXXN+WRqjRRW0hCOr8MQ@mail.gmail.com>
Message-ID: <180C211B-0D38-4314-959F-680AAA1A61D9@apple.com>


On Jun 21, 2011, at 10:34 AM, Jay Foad wrote:

> On 21 June 2011 18:09, John McCall <rjmccall at apple.com> wrote:
>> On Jun 21, 2011, at 12:22 AM, Jay Foad wrote:
>>>>> Patch 1 extends ConstantUniqueMap with a new template parameter
>>>>> ValRefType, representing a const reference to ValType. Normally this
>>>>> would just be const ValType&, but when ValType is a std::vector, we
>>>>> want to use ArrayRef as the reference type.
>>> 
>>>> Wow, looks great to me Jay
>>> 
>>> Just to double check, are you OK with me adding the conversion operator
>>> 
>>>  ArrayRef<T>::operator std::vector<T>() const;
>> 
>> This is best avoided if possible.
> 
> Any particular reason?

Mostly I'm just skeptical of having an O(n) implicit conversion, but it also seems
odd to privilege std::vector here.

Why is this necessary?  Template metaprogramming in the constants-map
implementation?

John.

From jay.foad at gmail.com  Tue Jun 21 13:35:28 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Tue, 21 Jun 2011 19:35:28 +0100
Subject: [llvm-commits] [llvm] r133412 - in /llvm/trunk:
 include/llvm/Constants.h lib/Analysis/ConstantFolding.cpp
 lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp
 lib/CodeGen/ShadowStackGC.cpp lib/Transforms/IPO/GlobalOpt.cpp
 lib/Transform
In-Reply-To: <180C211B-0D38-4314-959F-680AAA1A61D9@apple.com>
References: <BANLkTimBn5-=U7Re=p4gkh7CE3A7N5gf=Y+w6MD2teoEXDer6Q@mail.gmail.com>
	<6ACAF514-D83B-46F3-BBD9-13F295FB1FA2@nondot.org>
	<BANLkTi=KOpcn0CwHfObMA+Z7eakrgTWafwBPBt2XVjR36GTphA@mail.gmail.com>
	<31BCDD79-78B7-4F94-AD16-AA8290D140D1@apple.com>
	<BANLkTinL=WKbepnXXN+WRqjRRW0hCOr8MQ@mail.gmail.com>
	<180C211B-0D38-4314-959F-680AAA1A61D9@apple.com>
Message-ID: <BANLkTincArvmZ_bnrpGJ-OxVfShW4ckCXw@mail.gmail.com>

> Mostly I'm just skeptical of having an O(n) implicit conversion, but it also seems
> odd to privilege std::vector here.

I'm probably biased by what I'm trying to do now, but I'm thinking of
ArrayRef as a more flexible replacement for "const vector &". (More
flexible since it doesn't have to refer to a *vector*, it could refer
to a C array or other things.) Since "const vector &" implicitly
converts to vector, I don't see the problem with ArrayRef doing the
same.

> Why is this necessary? ?Template metaprogramming in the constants-map
> implementation?

Yes. We have something like:

template<class ValType, class ValRefType>
class ConstantUniqueMap {
  void doSomething(ValRefType v) {
    ValType myVal = v;
  }
}

The template class is instantiated with things like

ConstantUniqueMap<char, char>
ConstantUniqueMap<SomeClassType, const SomeClassType &>
ConstantUniqueMap<vector<Constant*>, ArrayRef<Constant*>>

In the last case, I want the flexibility of being able to pass
(anything convertible to) an ArrayRef into doSomething().

Thanks,
Jay.


From rjmccall at apple.com  Tue Jun 21 13:38:32 2011
From: rjmccall at apple.com (John McCall)
Date: Tue, 21 Jun 2011 11:38:32 -0700
Subject: [llvm-commits] [llvm] r133412 - in /llvm/trunk:
 include/llvm/Constants.h lib/Analysis/ConstantFolding.cpp
 lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp
 lib/CodeGen/ShadowStackGC.cpp lib/Transforms/IPO/GlobalOpt.cpp
 lib/Transform
In-Reply-To: <BANLkTincArvmZ_bnrpGJ-OxVfShW4ckCXw@mail.gmail.com>
References: <BANLkTimBn5-=U7Re=p4gkh7CE3A7N5gf=Y+w6MD2teoEXDer6Q@mail.gmail.com>
	<6ACAF514-D83B-46F3-BBD9-13F295FB1FA2@nondot.org>
	<BANLkTi=KOpcn0CwHfObMA+Z7eakrgTWafwBPBt2XVjR36GTphA@mail.gmail.com>
	<31BCDD79-78B7-4F94-AD16-AA8290D140D1@apple.com>
	<BANLkTinL=WKbepnXXN+WRqjRRW0hCOr8MQ@mail.gmail.com>
	<180C211B-0D38-4314-959F-680AAA1A61D9@apple.com>
	<BANLkTincArvmZ_bnrpGJ-OxVfShW4ckCXw@mail.gmail.com>
Message-ID: <C2B2487E-9D83-496C-88AA-2D0524DA811F@apple.com>


On Jun 21, 2011, at 11:35 AM, Jay Foad wrote:

>> Mostly I'm just skeptical of having an O(n) implicit conversion, but it also seems
>> odd to privilege std::vector here.
> 
> I'm probably biased by what I'm trying to do now, but I'm thinking of
> ArrayRef as a more flexible replacement for "const vector &". (More
> flexible since it doesn't have to refer to a *vector*, it could refer
> to a C array or other things.) Since "const vector &" implicitly
> converts to vector, I don't see the problem with ArrayRef doing the
> same.

Well, I'm worried it'll cause trouble down the road, but I guess it's fine for now.

John.

From sabre at nondot.org  Tue Jun 21 13:40:11 2011
From: sabre at nondot.org (Chris Lattner)
Date: Tue, 21 Jun 2011 11:40:11 -0700
Subject: [llvm-commits] [llvm] r133412 - in /llvm/trunk:
	include/llvm/Constants.h lib/Analysis/ConstantFolding.cpp
	lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp
	lib/CodeGen/ShadowStackGC.cpp
	lib/Transforms/IPO/GlobalOpt.cpp lib/Transform
In-Reply-To: <BANLkTi=KOpcn0CwHfObMA+Z7eakrgTWafwBPBt2XVjR36GTphA@mail.gmail.com>
References: <BANLkTimBn5-=U7Re=p4gkh7CE3A7N5gf=Y+w6MD2teoEXDer6Q@mail.gmail.com>
	<6ACAF514-D83B-46F3-BBD9-13F295FB1FA2@nondot.org>
	<BANLkTi=KOpcn0CwHfObMA+Z7eakrgTWafwBPBt2XVjR36GTphA@mail.gmail.com>
Message-ID: <87A7DCD7-1A1E-41F9-83EF-B675446B2830@nondot.org>


On Jun 21, 2011, at 12:22 AM, Jay Foad wrote:

>>> Patch 1 extends ConstantUniqueMap with a new template parameter
>>> ValRefType, representing a const reference to ValType. Normally this
>>> would just be const ValType&, but when ValType is a std::vector, we
>>> want to use ArrayRef as the reference type.
> 
>> Wow, looks great to me Jay
> 
> Just to double check, are you OK with me adding the conversion operator
> 
>  ArrayRef<T>::operator std::vector<T>() const;

I'm ok with it if there is no no other way, but..

> And should I remove the now redundant method which just did the same thing:
> 
>  std::vector<T> ArrayRef<T>::vec() const;

I'd prefer to keep this.

-Chris

From clattner at apple.com  Tue Jun 21 14:03:42 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 21 Jun 2011 12:03:42 -0700
Subject: [llvm-commits] [PATCH 0/5] Reduce memory usage for phi operands
In-Reply-To: <BANLkTinSB-6zzgpn3wHEw0fRjOEFt14AW42bTWb0my5HiF05Uw@mail.gmail.com>
References: <1308222566-2451-1-git-send-email-jay.foad@gmail.com>
	<4737089F-10B2-4D3F-A9C5-B26E2D405674@apple.com>
	<BANLkTinSB-6zzgpn3wHEw0fRjOEFt14AW42bTWb0my5HiF05Uw@mail.gmail.com>
Message-ID: <09AF2EF4-8552-4FB1-8540-12A508008B9C@apple.com>


On Jun 21, 2011, at 5:57 AM, Jay Foad wrote:

>> If you're interested in another project, PR1324 would be another great memory reduction for apps with lots of strings and tables.
> 
> This bug is about using a more compact representation of
> ConstantArrays of ConstantInts. I think it will be easier to do this
> for integers of a few pre-defined widths (i8. i16, i32, i64, maybe
> even i1), rather than trying to handle arbitrarily wide integers. Does
> this seem reasonable?

That would be very reasonable.  The biggest memory savings come from strings and other simple tables.  I think that it would make sense to handle the "common" datatypes: arrays of i8/i16/i32/i64/float/double, which are the most common thing you see in tables.  A sketch of the class could be something like:


class ConstantDataArray {
?

  // To be used on arrays of ints.
  uint64_t getIntElement(uint64_t idx)

  // To be used on arrays of floats/doubles.
  APFloat getFloatElement(uint64_t idx)

};

The actual data would then just be stored in a normal C array.

To get one of these, the ConstantArray::get method would form one when the elements are simple enough, and clients like clang can use ConstantDataArray::get() directly for string constants and other cases.  Using ConstantDataArray directly is useful because it avoids creating the Constant*'s for the elements at all.

-Chris

From evan.cheng at apple.com  Tue Jun 21 14:00:54 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Tue, 21 Jun 2011 19:00:54 -0000
Subject: [llvm-commits] [llvm] r133533 -
	/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
Message-ID: <20110621190054.740312A6C12C@llvm.org>

Author: evancheng
Date: Tue Jun 21 14:00:54 2011
New Revision: 133533

URL: http://llvm.org/viewvc/llvm-project?rev=133533&view=rev
Log:
Reorg. No functionality change.

Modified:
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=133533&r1=133532&r2=133533&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Tue Jun 21 14:00:54 2011
@@ -1206,29 +1206,6 @@
 }
 } // end isCodeGenOnly = 1
 
-// Signed and unsigned division on v7-M
-def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
-                 "sdiv", "\t$Rd, $Rn, $Rm",
-                 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
-                 Requires<[HasDivide, IsThumb2]> {
-  let Inst{31-27} = 0b11111;
-  let Inst{26-21} = 0b011100;
-  let Inst{20} = 0b1;
-  let Inst{15-12} = 0b1111;
-  let Inst{7-4} = 0b1111;
-}
-
-def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
-                 "udiv", "\t$Rd, $Rn, $Rm",
-                 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
-                 Requires<[HasDivide, IsThumb2]> {
-  let Inst{31-27} = 0b11111;
-  let Inst{26-21} = 0b011101;
-  let Inst{20} = 0b1;
-  let Inst{15-12} = 0b1111;
-  let Inst{7-4} = 0b1111;
-}
-
 //===----------------------------------------------------------------------===//
 //  Load / store Instructions.
 //
@@ -2560,6 +2537,32 @@
                         "\t$Ra, $Rd, $Rm, $Rn", []>;
 
 //===----------------------------------------------------------------------===//
+//  Division Instructions.
+//  Signed and unsigned division on v7-M
+//
+def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
+                 "sdiv", "\t$Rd, $Rn, $Rm",
+                 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>,
+                 Requires<[HasDivide, IsThumb2]> {
+  let Inst{31-27} = 0b11111;
+  let Inst{26-21} = 0b011100;
+  let Inst{20} = 0b1;
+  let Inst{15-12} = 0b1111;
+  let Inst{7-4} = 0b1111;
+}
+
+def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,
+                 "udiv", "\t$Rd, $Rn, $Rm",
+                 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>,
+                 Requires<[HasDivide, IsThumb2]> {
+  let Inst{31-27} = 0b11111;
+  let Inst{26-21} = 0b011101;
+  let Inst{20} = 0b1;
+  let Inst{15-12} = 0b1111;
+  let Inst{7-4} = 0b1111;
+}
+
+//===----------------------------------------------------------------------===//
 //  Misc. Arithmetic Instructions.
 //
 



From clattner at apple.com  Tue Jun 21 14:07:15 2011
From: clattner at apple.com (Chris Lattner)
Date: Tue, 21 Jun 2011 12:07:15 -0700
Subject: [llvm-commits] [PATCH 0/5] Reduce memory usage for phi operands
In-Reply-To: <09AF2EF4-8552-4FB1-8540-12A508008B9C@apple.com>
References: <1308222566-2451-1-git-send-email-jay.foad@gmail.com>
	<4737089F-10B2-4D3F-A9C5-B26E2D405674@apple.com>
	<BANLkTinSB-6zzgpn3wHEw0fRjOEFt14AW42bTWb0my5HiF05Uw@mail.gmail.com>
	<09AF2EF4-8552-4FB1-8540-12A508008B9C@apple.com>
Message-ID: <B386EFD0-B2D6-4C60-B2F9-DFC8BE751645@apple.com>


On Jun 21, 2011, at 12:03 PM, Chris Lattner wrote:
> class ConstantDataArray {
> ?
> 
>  // To be used on arrays of ints.
>  uint64_t getIntElement(uint64_t idx)
> 
>  // To be used on arrays of floats/doubles.
>  APFloat getFloatElement(uint64_t idx)

Actually, since the client needs to handle the various element types specially, it would be better to just do:

float getFloatElement(uint64_t idx)
double getDoubleElement(uint64_t idx)

directly,

-Chris

From dpatel at apple.com  Tue Jun 21 14:46:09 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 21 Jun 2011 19:46:09 -0000
Subject: [llvm-commits] [llvm] r133536 - /llvm/trunk/lib/VMCore/AsmWriter.cpp
Message-ID: <20110621194609.ED9AB2A6C12D@llvm.org>

Author: dpatel
Date: Tue Jun 21 14:46:09 2011
New Revision: 133536

URL: http://llvm.org/viewvc/llvm-project?rev=133536&view=rev
Log:
Remove r130409, as requested by Chris.

Modified:
    llvm/trunk/lib/VMCore/AsmWriter.cpp

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=133536&r1=133535&r2=133536&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Tue Jun 21 14:46:09 2011
@@ -32,7 +32,6 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/CFG.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Dwarf.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -42,11 +41,6 @@
 #include <cctype>
 using namespace llvm;
 
-static cl::opt<bool>
-EnableDebugInfoComment("enable-debug-info-comment", cl::Hidden,
-                       cl::desc("Enable debug info comments"));
-
-
 // Make virtual table appear in this compilation unit.
 AssemblyAnnotationWriter::~AssemblyAnnotationWriter() {}
 
@@ -1767,18 +1761,6 @@
   if (AnnotationWriter) AnnotationWriter->emitBasicBlockEndAnnot(BB, Out);
 }
 
-/// printDebugLoc - Print DebugLoc.
-static void printDebugLoc(const DebugLoc &DL, formatted_raw_ostream &OS) {
-  OS << DL.getLine() << ":" << DL.getCol();
-  if (MDNode *N = DL.getInlinedAt(getGlobalContext())) {
-    DebugLoc IDL = DebugLoc::getFromDILocation(N);
-    if (!IDL.isUnknown()) {
-      OS << "@";
-      printDebugLoc(IDL,OS);
-    }
-  }
-}
-
 /// printInfoComment - Print a little comment after the instruction indicating
 /// which slot it occupies.
 ///
@@ -1786,43 +1768,6 @@
   if (AnnotationWriter) {
     AnnotationWriter->printInfoComment(V, Out);
     return;
-  } else if (EnableDebugInfoComment) {
-    bool Padded = false;
-    if (const Instruction *I = dyn_cast<Instruction>(&V)) {
-      const DebugLoc &DL = I->getDebugLoc();
-      if (!DL.isUnknown()) {
-        if (!Padded) {
-          Out.PadToColumn(50);
-          Padded = true;
-          Out << ";";
-        }
-        Out << " [debug line = ";
-        printDebugLoc(DL,Out);
-        Out << "]";
-      }
-      if (const DbgDeclareInst *DDI = dyn_cast<DbgDeclareInst>(I)) {
-        const MDNode *Var = DDI->getVariable();
-        if (!Padded) {
-          Out.PadToColumn(50);
-          Padded = true;
-          Out << ";";
-        }
-        if (Var && Var->getNumOperands() >= 2)
-          if (MDString *MDS = dyn_cast_or_null<MDString>(Var->getOperand(2)))
-            Out << " [debug variable = " << MDS->getString() << "]";
-      }
-      else if (const DbgValueInst *DVI = dyn_cast<DbgValueInst>(I)) {
-        const MDNode *Var = DVI->getVariable();
-        if (!Padded) {
-          Out.PadToColumn(50);
-          Padded = true;
-          Out << ";";
-        }
-        if (Var && Var->getNumOperands() >= 2)
-          if (MDString *MDS = dyn_cast_or_null<MDString>(Var->getOperand(2)))
-            Out << " [debug variable = " << MDS->getString() << "]";
-      }
-    }
   }
 }
 



From daniel at zuster.org  Tue Jun 21 15:05:16 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Tue, 21 Jun 2011 13:05:16 -0700
Subject: [llvm-commits] [llvm] r133206 - in /llvm/trunk:
 Makefile.config.in Makefile.rules autoconf/configure.ac
In-Reply-To: <2123779D-92CE-47A4-A2D0-E5D0C1745948@apple.com>
References: <20110616223039.2FDCF2A6C12C@llvm.org>
	<2123779D-92CE-47A4-A2D0-E5D0C1745948@apple.com>
Message-ID: <BANLkTik=pWUgnVaE8AiqypQ0_+UFaCi43hgYvt_W+TMrCOupXA@mail.gmail.com>

On Thu, Jun 16, 2011 at 4:03 PM, Eric Christopher <echristo at apple.com> wrote:
>
> On Jun 16, 2011, at 3:30 PM, Daniel Dunbar wrote:
>
>> Author: ddunbar
>> Date: Thu Jun 16 17:30:38 2011
>> New Revision: 133206
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=133206&view=rev
>> Log:
>> build/configure: Add support for --with-extra-ld-options flag (to provide extra
>> options just to pass to ld).
>>
>
> LDFLAGS doesn't work? Or do we erroneously override it?

Didn't work for me. At least, I couldn't find a way to get what I
wanted which was add a set of flags that *only* get passed to the link
lines.

 - Daniel

>
> -eric
>
>> Modified:
>> ? ?llvm/trunk/Makefile.config.in
>> ? ?llvm/trunk/Makefile.rules
>> ? ?llvm/trunk/autoconf/configure.ac
>>
>> Modified: llvm/trunk/Makefile.config.in
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.config.in?rev=133206&r1=133205&r2=133206&view=diff
>> ==============================================================================
>> --- llvm/trunk/Makefile.config.in (original)
>> +++ llvm/trunk/Makefile.config.in Thu Jun 16 17:30:38 2011
>> @@ -123,6 +123,9 @@
>> # Extra options to compile LLVM with
>> EXTRA_OPTIONS=@EXTRA_OPTIONS@
>>
>> +# Extra options to link LLVM with
>> +EXTRA_LD_OPTIONS=@EXTRA_LD_OPTIONS@
>> +
>> # Endian-ness of the target
>> ENDIAN=@ENDIAN@
>>
>>
>> Modified: llvm/trunk/Makefile.rules
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=133206&r1=133205&r2=133206&view=diff
>> ==============================================================================
>> --- llvm/trunk/Makefile.rules (original)
>> +++ llvm/trunk/Makefile.rules Thu Jun 16 17:30:38 2011
>> @@ -582,6 +582,10 @@
>> # Options To Invoke Tools
>> #----------------------------------------------------------
>>
>> +ifdef EXTRA_LD_OPTIONS
>> +LD.Flags += $(EXTRA_LD_OPTIONS)
>> +endif
>> +
>> ifndef NO_PEDANTIC
>> CompileCommonOpts += -pedantic -Wno-long-long
>> endif
>>
>> Modified: llvm/trunk/autoconf/configure.ac
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/autoconf/configure.ac?rev=133206&r1=133205&r2=133206&view=diff
>> ==============================================================================
>> --- llvm/trunk/autoconf/configure.ac (original)
>> +++ llvm/trunk/autoconf/configure.ac Thu Jun 16 17:30:38 2011
>> @@ -831,6 +831,17 @@
>> esac
>> AC_SUBST(EXTRA_OPTIONS,$EXTRA_OPTIONS)
>>
>> +dnl Specify extra linker build options
>> +AC_ARG_WITH(extra-ld-options,
>> + ?AS_HELP_STRING([--with-extra-ld-options],
>> + ? ? ? ? ? ? ? ? [Specify additional options to link LLVM with]),,
>> + ? ? ? ? ? ? ? ? withval=default)
>> +case "$withval" in
>> + ?default) EXTRA_LD_OPTIONS= ;;
>> + ?*) EXTRA_LD_OPTIONS=$withval ;;
>> +esac
>> +AC_SUBST(EXTRA_LD_OPTIONS,$EXTRA_LD_OPTIONS)
>> +
>> dnl Allow specific bindings to be specified for building (or not)
>> AC_ARG_ENABLE([bindings],AS_HELP_STRING([--enable-bindings],
>> ? ? [Build specific language bindings: all,auto,none,{binding-name} (default=auto)]),,
>>
>>
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>


From rafael.espindola at gmail.com  Tue Jun 21 15:13:50 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Tue, 21 Jun 2011 16:13:50 -0400
Subject: [llvm-commits] [llvm] r133240 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
In-Reply-To: <BANLkTikGbW-G3soeku5b8U6mw31MOiE-=+LOqJ+jkbAjja0qAg@mail.gmail.com>
References: <20110617055451.24CFF2A6C12C@llvm.org>
	<BANLkTikGbW-G3soeku5b8U6mw31MOiE-=+LOqJ+jkbAjja0qAg@mail.gmail.com>
Message-ID: <4E00FB7E.5090206@gmail.com>

  > This commit appears to be causing a significant performance regression
> on a couple tests in the test-suite for x86-32;
> test-suite/SingleSource/Benchmarks/Shootout-C++/matrix.cpp is a good
> example (3.3s before, 4.1s after).  Would you mind taking a look to
> see if anything unexpected is happening?

I will take a look.

> -Eli

Cheers,
Rafael

From echristo at apple.com  Tue Jun 21 15:16:42 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 21 Jun 2011 13:16:42 -0700
Subject: [llvm-commits] [llvm] r133206 - in /llvm/trunk:
 Makefile.config.in Makefile.rules autoconf/configure.ac
In-Reply-To: <BANLkTik=pWUgnVaE8AiqypQ0_+UFaCi43hgYvt_W+TMrCOupXA@mail.gmail.com>
References: <20110616223039.2FDCF2A6C12C@llvm.org>
	<2123779D-92CE-47A4-A2D0-E5D0C1745948@apple.com>
	<BANLkTik=pWUgnVaE8AiqypQ0_+UFaCi43hgYvt_W+TMrCOupXA@mail.gmail.com>
Message-ID: <AEA258D2-5DE4-4074-A885-FFE1B1BBA786@apple.com>


On Jun 21, 2011, at 1:05 PM, Daniel Dunbar wrote:

> On Thu, Jun 16, 2011 at 4:03 PM, Eric Christopher <echristo at apple.com> wrote:
>> 
>> On Jun 16, 2011, at 3:30 PM, Daniel Dunbar wrote:
>> 
>>> Author: ddunbar
>>> Date: Thu Jun 16 17:30:38 2011
>>> New Revision: 133206
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=133206&view=rev
>>> Log:
>>> build/configure: Add support for --with-extra-ld-options flag (to provide extra
>>> options just to pass to ld).
>>> 
>> 
>> LDFLAGS doesn't work? Or do we erroneously override it?
> 
> Didn't work for me. At least, I couldn't find a way to get what I
> wanted which was add a set of flags that *only* get passed to the link
> lines.

Yeah, I'll take a look at it when I get a chance. Something weird is probably
going on or something. It _should_ be possible. I think.

-eric

From baldrick at free.fr  Tue Jun 21 15:35:41 2011
From: baldrick at free.fr (Duncan Sands)
Date: Tue, 21 Jun 2011 22:35:41 +0200
Subject: [llvm-commits] [llvm] r133285	-
	/llvm/trunk/lib/Transforms/InstCombine/InstCombineCasts.cpp
In-Reply-To: <07078D47-26CC-49FB-B53F-478A74D8A0FB@apple.com>
References: <20110617202152.D6B812A6C12C@llvm.org> <4DFDF276.5030703@free.fr>
	<54E09593-01A1-4936-AFF8-7AF19D2C6919@apple.com>
	<4DFEF6DA.4030503@free.fr>
	<BEFDFA5B-4D83-47A5-A967-02ADE979F770@apple.com>
	<4E008742.9030700@free.fr>
	<07078D47-26CC-49FB-B53F-478A74D8A0FB@apple.com>
Message-ID: <4E01009D.3040401@free.fr>

Hi John,

> I was suggesting that we could make more aggressive restrictions on the
> size input to alloca based on a basic assumption that you can't grow your stack
> to>2GB, even on>32-bit architectures.  But if we want to support that, then
> obviously this needs to be based on the pointer width.

I agree.

>> Why?  Are you saying that an alloca of 2^31 i8's should be considered to result
>> in undefined behaviour?
>
> On a 32-bit machine, yes.  Are you really saying that we need to
> support any argument to alloca that's smaller than the addressable
> space of the machine?
>
> If so, this transformation is completely dead;  feel free to remove it.
>
>>   And what about this: alloca i8, i8 128
>
> I did say "in sizeof(sp)" above.

I didn't know what you meant by sizeof(sp), so I just ignored that bit :)
For what it's worth I agree it should be fine to assume that the stack always
consumes less than half of the address space.

Ciao, Duncan.

From echristo at apple.com  Tue Jun 21 17:10:57 2011
From: echristo at apple.com (Eric Christopher)
Date: Tue, 21 Jun 2011 22:10:57 -0000
Subject: [llvm-commits] [llvm] r133553 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20110621221057.EFFD02A6C12C@llvm.org>

Author: echristo
Date: Tue Jun 21 17:10:57 2011
New Revision: 133553

URL: http://llvm.org/viewvc/llvm-project?rev=133553&view=rev
Log:
Handle the memory-ness of all U+ ARM constraints.

Noticed on inspection.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=133553&r1=133552&r2=133553&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jun 21 17:10:57 2011
@@ -7379,9 +7379,12 @@
     case 'l': return C_RegisterClass;
     case 'w': return C_RegisterClass;
     }
-  } else {
-    if (Constraint == "Uv")
-      return C_Memory;
+  } else if (Constraint.size() == 2) {
+    switch (Constraint[0]) {
+    default: break;
+    // All 'U+' constraints are addresses.
+    case 'U': return C_Memory;
+    }
   }
   return TargetLowering::getConstraintType(Constraint);
 }



From mttjwl at gmail.com  Tue Jun 21 17:12:50 2011
From: mttjwl at gmail.com (Matthew Wala)
Date: Tue, 21 Jun 2011 22:12:50 -0000
Subject: [llvm-commits] [poolalloc] r133555 - in /poolalloc/trunk/lib:
 DSA/StdLibPass.cpp PoolAllocate/PASimple.cpp
 PoolAllocate/TransformFunctionBody.cpp
Message-ID: <20110621221250.B3A282A6C12D@llvm.org>

Author: wala1
Date: Tue Jun 21 17:12:50 2011
New Revision: 133555

URL: http://llvm.org/viewvc/llvm-project?rev=133555&view=rev
Log:
Add support for SAFECode runtime format string functions and intrinsics.

Modified:
    poolalloc/trunk/lib/DSA/StdLibPass.cpp
    poolalloc/trunk/lib/PoolAllocate/PASimple.cpp
    poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp

Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=133555&r1=133554&r2=133555&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original)
+++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Tue Jun 21 17:12:50 2011
@@ -297,6 +297,11 @@
   {"pool_strncasecmp",{NRET_NNYARGS, NRET_NARGS,    NRET_NARGS, NRET_NARGS,   false}},
   {"pool_bcopy",      {NRET_NNYARGS, NRET_NNNYARGS, NRET_NARGS, NRET_NNYARGS,  true}},
   {"pool_bcmp",       {NRET_NNYARGS, NRET_NARGS,    NRET_NARGS, NRET_NARGS,    true}},
+
+  // format string intrinsics and functions
+  {"sc.fsparameter",  {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"sc.fscallinfo",   {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_printf",     {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   
   // Type Checks
   {"trackGlobal",          {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},

Modified: poolalloc/trunk/lib/PoolAllocate/PASimple.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/PASimple.cpp?rev=133555&r1=133554&r2=133555&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/PASimple.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/PASimple.cpp Tue Jun 21 17:12:50 2011
@@ -101,7 +101,8 @@
       (funcname == "sc.pool_unregister") ||
       (funcname == "sc.get_actual_val") ||
       (funcname == "__if_pool_get_label") ||
-      (funcname == "__if_pool_set_label")) {
+      (funcname == "__if_pool_set_label") ||
+      (funcname == "sc.fsparameter")) {
     return 1;
   }
   

Modified: poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp?rev=133555&r1=133554&r2=133555&view=diff
==============================================================================
--- poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp (original)
+++ poolalloc/trunk/lib/PoolAllocate/TransformFunctionBody.cpp Tue Jun 21 17:12:50 2011
@@ -874,7 +874,8 @@
                (CF->getName() == "sc.pool_unregister") ||
                (CF->getName() == "sc.get_actual_val") ||
                (CF->getName() == "__if_pool_get_label") ||
-               (CF->getName() == "__if_pool_set_label")) {
+               (CF->getName() == "__if_pool_set_label") ||
+               (CF->getName() == "sc.fsparameter")) {
       visitRuntimeCheck (CS);
     } else if ((argc = PAInfo.getCStdLibPoolArguments(CF->getName())) > 0) {
       visitCStdLibCheck(CS, argc);



From isanbard at gmail.com  Tue Jun 21 17:30:20 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 21 Jun 2011 22:30:20 -0000
Subject: [llvm-commits] [llvm] r133559 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
Message-ID: <20110621223020.CE29B2A6C12C@llvm.org>

Author: void
Date: Tue Jun 21 17:30:20 2011
New Revision: 133559

URL: http://llvm.org/viewvc/llvm-project?rev=133559&view=rev
Log:
Improve the comment printing for the EH table. This gives a much more detailed
explanation of what the EH table describes.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=133559&r1=133558&r2=133559&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Tue Jun 21 17:30:20 2011
@@ -512,6 +512,8 @@
     SizeAlign = 0;
   }
 
+  bool VerboseAsm = Asm->OutStreamer.isVerboseAsm();
+
   // SjLj Exception handling
   if (IsSJLJ) {
     Asm->EmitEncodingByte(dwarf::DW_EH_PE_udata4, "Call site");
@@ -527,7 +529,7 @@
 
       // Offset of the landing pad, counted in 16-byte bundles relative to the
       // @LPStart address.
-      Asm->EmitULEB128(idx, "Landing pad");
+      Asm->EmitULEB128(idx, "Call Site");
 
       // Offset of the first associated action record, relative to the start of
       // the action table. This value is biased by 1 (1 indicates the start of
@@ -562,6 +564,7 @@
     // Add extra padding if it wasn't added to the TType base offset.
     Asm->EmitULEB128(CallSiteTableLength, "Call site table length", SizeAlign);
 
+    unsigned Entry = 0;
     for (SmallVectorImpl<CallSiteEntry>::const_iterator
          I = CallSites.begin(), E = CallSites.end(); I != E; ++I) {
       const CallSiteEntry &S = *I;
@@ -576,19 +579,37 @@
       if (EndLabel == 0)
         EndLabel = Asm->GetTempSymbol("eh_func_end", Asm->getFunctionNumber());
 
+      if (VerboseAsm) {
+        // Emit comments that decode the call site.
+        Asm->OutStreamer.AddComment(Twine(">> Call Site ") +
+                                    llvm::utostr(++Entry) + " <<");
+        Asm->OutStreamer.AddComment(Twine("  Call between ") +
+                                    BeginLabel->getName() + " and " +
+                                    EndLabel->getName());
+        if (!S.PadLabel) {
+          Asm->OutStreamer.AddComment("    has no landing pad");
+        } else {
+          Asm->OutStreamer.AddComment(Twine("    jumps to ") +
+                                      S.PadLabel->getName());
+
+          if (S.Action == 0)
+            Asm->OutStreamer.AddComment("  On action: cleanup");
+          else
+            Asm->OutStreamer.AddComment(Twine("  On action: ") +
+                                        llvm::utostr((S.Action - 1) / 2 + 1));
+        }
+
+        Asm->OutStreamer.AddBlankLine();
+      }
+
       // Offset of the call site relative to the previous call site, counted in
       // number of 16-byte bundles. The first call site is counted relative to
       // the start of the procedure fragment.
-      Asm->OutStreamer.AddComment("Region start");
       Asm->EmitLabelDifference(BeginLabel, EHFuncBeginSym, 4);
-
-      Asm->OutStreamer.AddComment("Region length");
       Asm->EmitLabelDifference(EndLabel, BeginLabel, 4);
 
-
       // Offset of the landing pad, counted in 16-byte bundles relative to the
       // @LPStart address.
-      Asm->OutStreamer.AddComment("Landing pad");
       if (!S.PadLabel)
         Asm->OutStreamer.EmitIntValue(0, 4/*size*/, 0/*addrspace*/);
       else
@@ -597,45 +618,63 @@
       // Offset of the first associated action record, relative to the start of
       // the action table. This value is biased by 1 (1 indicates the start of
       // the action table), and 0 indicates that there are no actions.
-      Asm->EmitULEB128(S.Action, "Action");
+      Asm->EmitULEB128(S.Action);
     }
   }
 
   // Emit the Action Table.
-  if (Actions.size() != 0) {
-    Asm->OutStreamer.AddComment("-- Action Record Table --");
-    Asm->OutStreamer.AddBlankLine();
-  }
-
+  int Entry = 0;
   for (SmallVectorImpl<ActionEntry>::const_iterator
          I = Actions.begin(), E = Actions.end(); I != E; ++I) {
     const ActionEntry &Action = *I;
-    Asm->OutStreamer.AddComment("Action Record");
-    Asm->OutStreamer.AddBlankLine();
+
+    if (VerboseAsm) {
+      // Emit comments that decode the action table.
+      Asm->OutStreamer.AddComment(Twine(">> Action Record ") +
+                                  llvm::utostr(++Entry) + " <<");
+      if (Action.ValueForTypeID >= 0)
+        Asm->OutStreamer.AddComment(Twine("  Catch TypeInfo ") +
+                                    llvm::itostr(Action.ValueForTypeID));
+      else 
+        Asm->OutStreamer.AddComment(Twine("  Filter TypeInfo ") +
+                                    llvm::itostr(Action.ValueForTypeID));
+
+      if (Action.NextAction == 0) {
+        Asm->OutStreamer.AddComment("  No further actions");
+      } else {
+        unsigned NextAction = Entry + (Action.NextAction + 1) / 2;
+        Asm->OutStreamer.AddComment(Twine("  Continue to action ") +
+                                    llvm::utostr(NextAction));
+      }
+
+      Asm->OutStreamer.AddBlankLine();
+    }
 
     // Type Filter
     //
     //   Used by the runtime to match the type of the thrown exception to the
     //   type of the catch clauses or the types in the exception specification.
-    Asm->EmitSLEB128(Action.ValueForTypeID, "  TypeInfo index");
+    Asm->EmitSLEB128(Action.ValueForTypeID);
 
     // Action Record
     //
     //   Self-relative signed displacement in bytes of the next action record,
     //   or 0 if there is no next action record.
-    Asm->EmitSLEB128(Action.NextAction, "  Next action");
+    Asm->EmitSLEB128(Action.NextAction);
   }
 
   // Emit the Catch TypeInfos.
-  if (!TypeInfos.empty()) {
-    Asm->OutStreamer.AddComment("-- Catch TypeInfos --");
+  if (VerboseAsm && !TypeInfos.empty()) {
+    Asm->OutStreamer.AddComment(">> Catch TypeInfos <<");
     Asm->OutStreamer.AddBlankLine();
+    Entry = TypeInfos.size();
   }
+
   for (std::vector<const GlobalVariable *>::const_reverse_iterator
          I = TypeInfos.rbegin(), E = TypeInfos.rend(); I != E; ++I) {
     const GlobalVariable *GV = *I;
-
-    Asm->OutStreamer.AddComment("TypeInfo");
+    if (VerboseAsm)
+      Asm->OutStreamer.AddComment(Twine("TypeInfo ") + llvm::utostr(Entry--));
     if (GV)
       Asm->EmitReference(GV, TTypeEncoding);
     else
@@ -644,14 +683,21 @@
   }
 
   // Emit the Exception Specifications.
-  if (!FilterIds.empty()) {
-    Asm->OutStreamer.AddComment("-- Filter IDs --");
+  if (VerboseAsm && !FilterIds.empty()) {
+    Asm->OutStreamer.AddComment(">> Filter TypeInfos <<");
     Asm->OutStreamer.AddBlankLine();
+    Entry = 0;
   }
   for (std::vector<unsigned>::const_iterator
          I = FilterIds.begin(), E = FilterIds.end(); I < E; ++I) {
     unsigned TypeID = *I;
-    Asm->EmitULEB128(TypeID, TypeID != 0 ? "Exception specification" : 0);
+    if (VerboseAsm) {
+      --Entry;
+      if (TypeID != 0)
+        Asm->OutStreamer.AddComment(Twine("FilterInfo ") + llvm::itostr(Entry));
+    }
+
+    Asm->EmitULEB128(TypeID);
   }
 
   Asm->EmitAlignment(2);



From dpatel at apple.com  Tue Jun 21 17:36:03 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 21 Jun 2011 22:36:03 -0000
Subject: [llvm-commits] [llvm] r133560 -
	/llvm/trunk/lib/CodeGen/RegAllocFast.cpp
Message-ID: <20110621223603.68CB22A6C12C@llvm.org>

Author: dpatel
Date: Tue Jun 21 17:36:03 2011
New Revision: 133560

URL: http://llvm.org/viewvc/llvm-project?rev=133560&view=rev
Log:
There could be more than one DBG_VALUE instructions for variables where all of them have offset based on one register.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocFast.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=133560&r1=133559&r2=133560&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Jun 21 17:36:03 2011
@@ -86,7 +86,7 @@
     // that is currently available in a physical register.
     LiveRegMap LiveVirtRegs;
 
-    DenseMap<unsigned, MachineInstr *> LiveDbgValueMap;
+    DenseMap<unsigned, SmallVector<MachineInstr *, 4> > LiveDbgValueMap;
 
     // RegState - Track the state of a physical register.
     enum RegState {
@@ -272,7 +272,9 @@
     // If this register is used by DBG_VALUE then insert new DBG_VALUE to
     // identify spilled location as the place to find corresponding variable's
     // value.
-    if (MachineInstr *DBG = LiveDbgValueMap.lookup(LRI->first)) {
+    SmallVector<MachineInstr *, 4> &LRIDbgValues = LiveDbgValueMap[LRI->first];
+    for (unsigned li = 0, le = LRIDbgValues.size(); li != le; ++li) {
+      MachineInstr *DBG = LRIDbgValues[li];
       const MDNode *MDPtr =
         DBG->getOperand(DBG->getNumOperands()-1).getMetadata();
       int64_t Offset = 0;
@@ -291,7 +293,7 @@
         MachineBasicBlock *MBB = DBG->getParent();
         MBB->insert(MI, NewDV);
         DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
-        LiveDbgValueMap[LRI->first] = NewDV;
+        LRIDbgValues[li] = NewDV;
       }
     }
     if (SpillKill)
@@ -816,7 +818,7 @@
           if (!MO.isReg()) continue;
           unsigned Reg = MO.getReg();
           if (!TargetRegisterInfo::isVirtualRegister(Reg)) continue;
-          LiveDbgValueMap[Reg] = MI;
+          LiveDbgValueMap[Reg].push_back(MI);
           LiveRegMap::iterator LRI = LiveVirtRegs.find(Reg);
           if (LRI != LiveVirtRegs.end())
             setPhysReg(MI, i, LRI->second.PhysReg);



From isanbard at gmail.com  Tue Jun 21 17:40:24 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 21 Jun 2011 22:40:24 -0000
Subject: [llvm-commits] [llvm] r133561 -
	/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
Message-ID: <20110621224024.9A6412A6C12C@llvm.org>

Author: void
Date: Tue Jun 21 17:40:24 2011
New Revision: 133561

URL: http://llvm.org/viewvc/llvm-project?rev=133561&view=rev
Log:
Add verbose EH table printing to SjLj exception tables.

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=133561&r1=133560&r2=133561&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Tue Jun 21 17:40:24 2011
@@ -527,14 +527,30 @@
          I = CallSites.begin(), E = CallSites.end(); I != E; ++I, ++idx) {
       const CallSiteEntry &S = *I;
 
+      if (VerboseAsm) {
+        // Emit comments that decode the call site.
+        Asm->OutStreamer.AddComment(Twine(">> Call Site ") +
+                                    llvm::utostr(idx) + " <<");
+        Asm->OutStreamer.AddComment(Twine("  On exception at call site ") +
+                                    llvm::utostr(idx));
+
+        if (S.Action == 0)
+          Asm->OutStreamer.AddComment("  Action: cleanup");
+        else
+          Asm->OutStreamer.AddComment(Twine("  Action: ") +
+                                      llvm::utostr((S.Action - 1) / 2 + 1));
+
+        Asm->OutStreamer.AddBlankLine();
+      }
+
       // Offset of the landing pad, counted in 16-byte bundles relative to the
       // @LPStart address.
-      Asm->EmitULEB128(idx, "Call Site");
+      Asm->EmitULEB128(idx);
 
       // Offset of the first associated action record, relative to the start of
       // the action table. This value is biased by 1 (1 indicates the start of
       // the action table), and 0 indicates that there are no actions.
-      Asm->EmitULEB128(S.Action, "Action");
+      Asm->EmitULEB128(S.Action);
     }
   } else {
     // DWARF Exception handling
@@ -586,6 +602,7 @@
         Asm->OutStreamer.AddComment(Twine("  Call between ") +
                                     BeginLabel->getName() + " and " +
                                     EndLabel->getName());
+
         if (!S.PadLabel) {
           Asm->OutStreamer.AddComment("    has no landing pad");
         } else {



From aggarwa4 at illinois.edu  Tue Jun 21 17:43:09 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 21 Jun 2011 22:43:09 -0000
Subject: [llvm-commits] [poolalloc] r133563 -
	/poolalloc/trunk/lib/DSA/StdLibPass.cpp
Message-ID: <20110621224309.D7DD82A6C12C@llvm.org>

Author: aggarwa4
Date: Tue Jun 21 17:43:09 2011
New Revision: 133563

URL: http://llvm.org/viewvc/llvm-project?rev=133563&view=rev
Log:
Add entries for the new type check functions.

Modified:
    poolalloc/trunk/lib/DSA/StdLibPass.cpp

Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=133563&r1=133562&r2=133563&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original)
+++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Tue Jun 21 17:43:09 2011
@@ -306,8 +306,11 @@
   // Type Checks
   {"trackGlobal",          {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},
   {"trackLoadInst",        {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},
+  {"checkType",        {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},
+  {"getTypeTag",        {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},
   {"trackStoreInst",       {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},
   {"copyTypeInfo",         {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},
+  {"setTypeInfo",         {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},
   {"trackInitInst",        {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},
   {"trackUnInitInst",      {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},
   {"trackArray",           {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},



From aggarwa4 at illinois.edu  Tue Jun 21 17:44:02 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 21 Jun 2011 22:44:02 -0000
Subject: [llvm-commits] [poolalloc] r133564 -
 /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c
Message-ID: <20110621224402.B7FE72A6C12C@llvm.org>

Author: aggarwa4
Date: Tue Jun 21 17:44:02 2011
New Revision: 133564

URL: http://llvm.org/viewvc/llvm-project?rev=133564&view=rev
Log:
Add tracking for some more library functions.

Modified:
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=133564&r1=133563&r2=133564&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c Tue Jun 21 17:44:02 2011
@@ -4,6 +4,10 @@
 #include <stdio.h>
 #include <stdlib.h>
 #include <string.h>
+#include <netdb.h>
+#include <poll.h>
+#include <sys/types.h>
+#include <sys/socket.h>
 #include <sys/mman.h>
 
 #define DEBUG (0)
@@ -115,9 +119,7 @@
   uintptr_t p = maskAddress(ptr);
   shadow_begin[p] = typeNumber;
   memset(&shadow_begin[p + 1], 0, size - 1);
-#if DEBUG
   printf("Store(%d): %p, %p = %u | %lu bytes | \n", tag, ptr, (void *)p, typeNumber, size);
-#endif
 
 }
 
@@ -186,22 +188,6 @@
   }
 
 }
-/**
- * Check the loaded type against the type recorded in the shadow memory.
- */
-void trackLoadInst(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) {
-  uint8_t *metadata = malloc(size);
-
-  getTypeTag(ptr, size, metadata);
-
-  checkType(typeNumber, size ,metadata, ptr, tag);
-#if DEBUG
-  printf("Load(%d): %p, %p = actual: %u, expect: %u | %lu  bytes\n", tag, ptr, (void *)p, typeNumber, shadow_begin[p], size);
-#endif
-
-  free(metadata);
-}
-
 
 /**
  *  For memset type instructions, that set values. 
@@ -237,6 +223,10 @@
   printf("Copy(%d): %p, %p = %u | %lu bytes \n", tag, dstptr, srcptr, shadow_begin[s], size);
 #endif
 }
+void setTypeInfo(void *dstptr, void *metadata, uint64_t size, uint32_t tag) {
+  uintptr_t d = maskAddress(dstptr);
+  memcpy(&shadow_begin[d], metadata, size);
+}
 
 /**
  * Initialize metadata for the pointer returned by __ctype_b_loc
@@ -287,3 +277,27 @@
 void trackgethostname(void *ptr, uint32_t tag) {
   trackInitInst(ptr, strlen(ptr) + 1, tag);
 }
+
+void trackgetaddrinfo(void *ptr, uint32_t tag) {
+  struct addrinfo *res;
+  struct addrinfo ** result = (struct addrinfo **)ptr;
+  for(res = *result; res != NULL; res = res->ai_next) {
+    trackInitInst(res->ai_addr, sizeof(struct sockaddr), tag);
+    trackInitInst(res, sizeof(struct addrinfo), tag);
+  }
+
+  trackInitInst(result, sizeof(struct addrinfo*), tag);
+}
+
+void trackaccept(void *ptr, uint32_t tag) {
+  trackInitInst(ptr, sizeof(struct sockaddr), tag);
+}
+
+void trackpoll(void *ptr, uint64_t nfds, uint32_t tag) {
+  struct pollfd *fds = (struct pollfd *)ptr;
+  unsigned i = 0;
+  while (i < nfds) {
+    trackInitInst(&fds[i], sizeof(struct pollfd), tag);
+    i++;
+  }
+}



From grosbach at apple.com  Tue Jun 21 17:50:09 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 21 Jun 2011 15:50:09 -0700
Subject: [llvm-commits] [llvm] r133561 -
 /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
In-Reply-To: <20110621224024.9A6412A6C12C@llvm.org>
References: <20110621224024.9A6412A6C12C@llvm.org>
Message-ID: <8BD87ACA-1476-436B-8F59-06A45877992E@apple.com>

Yay! Thanks, Bill. This, together with your other annotation patches, is a huge help reading these things.
-j
On Jun 21, 2011, at 3:40 PM, Bill Wendling wrote:

> Author: void
> Date: Tue Jun 21 17:40:24 2011
> New Revision: 133561
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133561&view=rev
> Log:
> Add verbose EH table printing to SjLj exception tables.
> 
> Modified:
>    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp?rev=133561&r1=133560&r2=133561&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp (original)
> +++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp Tue Jun 21 17:40:24 2011
> @@ -527,14 +527,30 @@
>          I = CallSites.begin(), E = CallSites.end(); I != E; ++I, ++idx) {
>       const CallSiteEntry &S = *I;
> 
> +      if (VerboseAsm) {
> +        // Emit comments that decode the call site.
> +        Asm->OutStreamer.AddComment(Twine(">> Call Site ") +
> +                                    llvm::utostr(idx) + " <<");
> +        Asm->OutStreamer.AddComment(Twine("  On exception at call site ") +
> +                                    llvm::utostr(idx));
> +
> +        if (S.Action == 0)
> +          Asm->OutStreamer.AddComment("  Action: cleanup");
> +        else
> +          Asm->OutStreamer.AddComment(Twine("  Action: ") +
> +                                      llvm::utostr((S.Action - 1) / 2 + 1));
> +
> +        Asm->OutStreamer.AddBlankLine();
> +      }
> +
>       // Offset of the landing pad, counted in 16-byte bundles relative to the
>       // @LPStart address.
> -      Asm->EmitULEB128(idx, "Call Site");
> +      Asm->EmitULEB128(idx);
> 
>       // Offset of the first associated action record, relative to the start of
>       // the action table. This value is biased by 1 (1 indicates the start of
>       // the action table), and 0 indicates that there are no actions.
> -      Asm->EmitULEB128(S.Action, "Action");
> +      Asm->EmitULEB128(S.Action);
>     }
>   } else {
>     // DWARF Exception handling
> @@ -586,6 +602,7 @@
>         Asm->OutStreamer.AddComment(Twine("  Call between ") +
>                                     BeginLabel->getName() + " and " +
>                                     EndLabel->getName());
> +
>         if (!S.PadLabel) {
>           Asm->OutStreamer.AddComment("    has no landing pad");
>         } else {
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From nicholas at mxc.ca  Tue Jun 21 17:45:42 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Tue, 21 Jun 2011 22:45:42 -0000
Subject: [llvm-commits] [llvm] r133565 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/X86/x86-64.s
Message-ID: <20110621224542.29C4C2A6C12C@llvm.org>

Author: nicholas
Date: Tue Jun 21 17:45:41 2011
New Revision: 133565

URL: http://llvm.org/viewvc/llvm-project?rev=133565&view=rev
Log:
Add support for assembling "movq" when it's correct to do so, while continuing
to emit "movd" across the board to continue supporting a Darwin assembler bug.
This is the reincarnation of r133452.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/X86/x86-64.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=133565&r1=133564&r2=133565&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Tue Jun 21 17:45:41 2011
@@ -2968,6 +2968,22 @@
             (MOVZDI2PDIrm addr:$src)>;
 }
 
+// These are the correct encodings of the instructions so that we know how to
+// read correct assembly, even though we continue to emit the wrong ones for
+// compatibility with Darwin's buggy assembler.
+def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
+                (MOV64toPQIrr VR128:$dst, GR64:$src), 0>;
+def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
+                (MOV64toSDrr FR64:$dst, GR64:$src), 0>;
+def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
+                (MOVPQIto64rr GR64:$dst, VR128:$src), 0>;
+def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
+                (MOVSDto64rr GR64:$dst, FR64:$src), 0>;
+def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
+                (VMOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
+def : InstAlias<"movq\t{$src, $dst|$dst, $src}",
+                (MOVZQI2PQIrr VR128:$dst, GR64:$src), 0>;
+
 //===---------------------------------------------------------------------===//
 // SSE2 - Move Quadword
 //===---------------------------------------------------------------------===//

Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=133565&r1=133564&r2=133565&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Tue Jun 21 17:45:41 2011
@@ -1128,3 +1128,11 @@
 // CHECK: strq
 // CHECK: encoding: [0x48,0x0f,0x00,0xc8]
 	str %rax
+
+// CHECK: movd %rdi, %xmm0
+// CHECK: encoding: [0x66,0x48,0x0f,0x6e,0xc7]
+	movq %rdi,%xmm0
+
+// CHECK: movd %rdi, %xmm0
+// CHECK: encoding: [0x66,0x48,0x0f,0x6e,0xc7]
+	movd %rdi,%xmm0



From aggarwa4 at illinois.edu  Tue Jun 21 17:50:28 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Tue, 21 Jun 2011 22:50:28 -0000
Subject: [llvm-commits] [poolalloc] r133566 - in
 /poolalloc/trunk/lib/AssistDS: TypeChecks.cpp TypeChecksOpt.cpp
Message-ID: <20110621225028.5C41C2A6C12C@llvm.org>

Author: aggarwa4
Date: Tue Jun 21 17:50:28 2011
New Revision: 133566

URL: http://llvm.org/viewvc/llvm-project?rev=133566&view=rev
Log:
Remove references to trackLoadInst, which is now 
redundant

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
    poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133566&r1=133565&r2=133566&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue Jun 21 17:50:28 2011
@@ -1602,6 +1602,34 @@
         CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I);
         return true;
       }
+    } else if (F->getNameStr() == std::string("accept")) {
+      CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(2), VoidPtrTy);
+      BCI->insertAfter(I);
+      std::vector<Value *>Args;
+      Args.push_back(BCI);
+      Args.push_back(getTagCounter());
+      Constant *F = M.getOrInsertFunction("trackaccept", VoidTy, VoidPtrTy, Int32Ty, NULL);
+      CallInst *CI = CallInst::Create(F, Args.begin(), Args.end());
+      CI->insertAfter(BCI);
+    } else if (F->getNameStr() == std::string("poll")) {
+      CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy);
+      BCI->insertAfter(I);
+      std::vector<Value*>Args;
+      Args.push_back(BCI);
+      Args.push_back(I->getOperand(2));
+      Args.push_back(getTagCounter());
+      Constant *F = M.getOrInsertFunction("trackpoll", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL);
+      CallInst *CI = CallInst::Create(F, Args.begin(), Args.end());
+      CI->insertAfter(BCI);
+    } else if (F->getNameStr() == std::string("getaddrinfo")) {
+      CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(4), VoidPtrTy);
+      BCI->insertAfter(I);
+      std::vector<Value *>Args;
+      Args.push_back(BCI);
+      Args.push_back(getTagCounter());
+      Constant *F = M.getOrInsertFunction("trackgetaddrinfo", VoidTy, VoidPtrTy, Int32Ty, NULL);
+      CallInst *CI = CallInst::Create(F, Args.begin(), Args.end());
+      CI->insertAfter(BCI);
     } else if (F->getNameStr() == std::string("__strdup")) {
       CastInst *BCI_Dest = BitCastInst::CreatePointerCast(I, VoidPtrTy);
       BCI_Dest->insertAfter(I);
@@ -1743,7 +1771,8 @@
       Args.push_back(getTagCounter());
       Constant *F = M.getOrInsertFunction("trackStrncpyInst", VoidTy, VoidPtrTy, VoidPtrTy, I->getOperand(3)->getType(), Int32Ty, NULL);
       CallInst::Create(F, Args.begin(), Args.end(), "", I);
-    } else if(F->getNameStr() == std::string("ftime")) {
+    } else if(F->getNameStr() == std::string("ftime") ||
+              F->getNameStr() == std::string("gettimeofday")) {
       CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I);
       const PointerType *PTy = cast<PointerType>(I->getOperand(1)->getType());
       const Type * ElementType = PTy->getElementType();

Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=133566&r1=133565&r2=133566&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Tue Jun 21 17:50:28 2011
@@ -47,11 +47,11 @@
 static Constant *trackInitInst;
 static Constant *trackUnInitInst;
 static Constant *trackStoreInst;
-static Constant *trackLoadInst;
 static Constant *copyTypeInfo;
 static Constant *setTypeInfo;
 static Constant *checkTypeInst;
 static Constant *MallocFunc;
+static Constant *getTypeTag;
 
 bool TypeChecksOpt::runOnModule(Module &M) {
   TS = &getAnalysis<dsa::TypeSafety<TDDataStructures> >();
@@ -63,6 +63,12 @@
   Int64Ty = IntegerType::getInt64Ty(M.getContext());
   VoidPtrTy = PointerType::getUnqual(Int8Ty);
 
+  getTypeTag = M.getOrInsertFunction("getTypeTag",
+                                     VoidTy,
+                                     VoidPtrTy, /*ptr*/
+                                     Int64Ty, /*size*/
+                                     VoidPtrTy, /*dest for type tag*/
+                                     NULL);
   trackGlobal = M.getOrInsertFunction("trackGlobal",
                                       VoidTy,
                                       VoidPtrTy,/*ptr*/
@@ -104,13 +110,6 @@
                                         VoidPtrTy,/*ptr*/
                                         Int32Ty,/*tag*/
                                         NULL);
-  trackLoadInst = M.getOrInsertFunction("trackLoadInst",
-                                        VoidTy,
-                                        VoidPtrTy,/*ptr*/
-                                        Int8Ty,/*type*/
-                                        Int64Ty,/*size*/
-                                        Int32Ty,/*tag*/
-                                        NULL);
   copyTypeInfo = M.getOrInsertFunction("copyTypeInfo",
                                        VoidTy,
                                        VoidPtrTy,/*dest ptr*/



From resistor at mac.com  Tue Jun 21 17:54:23 2011
From: resistor at mac.com (Owen Anderson)
Date: Tue, 21 Jun 2011 22:54:23 -0000
Subject: [llvm-commits] [llvm] r133567 - in /llvm/trunk/lib:
 CodeGen/SelectionDAG/ScheduleDAGRRList.cpp VMCore/ValueTypes.cpp
Message-ID: <20110621225423.9A2DE2A6C12C@llvm.org>

Author: resistor
Date: Tue Jun 21 17:54:23 2011
New Revision: 133567

URL: http://llvm.org/viewvc/llvm-project?rev=133567&view=rev
Log:
Fix some trailing issues from my introduction of MVT::untyped and its use for REGISTER_SEQUENCE.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
    llvm/trunk/lib/VMCore/ValueTypes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=133567&r1=133566&r2=133567&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Jun 21 17:54:23 2011
@@ -290,7 +290,17 @@
   // Special handling for untyped values.  These values can only come from
   // the expansion of custom DAG-to-DAG patterns.
   if (VT == MVT::untyped) {
-    unsigned Opcode = RegDefPos.GetNode()->getMachineOpcode();
+    const SDNode *Node = RegDefPos.GetNode();
+    unsigned Opcode = Node->getMachineOpcode();
+
+    if (Opcode == TargetOpcode::REG_SEQUENCE) {
+      unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
+      const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
+      RegClass = RC->getID();
+      Cost = 1;
+      return;
+    }
+
     unsigned Idx = RegDefPos.GetIdx();
     const TargetInstrDesc Desc = TII->get(Opcode);
     const TargetRegisterClass *RC = Desc.getRegClass(Idx, TRI);

Modified: llvm/trunk/lib/VMCore/ValueTypes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ValueTypes.cpp?rev=133567&r1=133566&r2=133567&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ValueTypes.cpp (original)
+++ llvm/trunk/lib/VMCore/ValueTypes.cpp Tue Jun 21 17:54:23 2011
@@ -133,6 +133,7 @@
   case MVT::v2f64:   return "v2f64";
   case MVT::v4f64:   return "v4f64";
   case MVT::Metadata:return "Metadata";
+  case MVT::untyped: return "untyped";
   }
 }
 



From grosbach at apple.com  Tue Jun 21 17:55:51 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Tue, 21 Jun 2011 22:55:51 -0000
Subject: [llvm-commits] [llvm] r133568 - in /llvm/trunk/utils/TableGen:
 AsmMatcherEmitter.cpp AsmWriterEmitter.cpp CodeGenDAGPatterns.cpp
 CodeGenInstruction.cpp CodeGenRegisters.cpp DisassemblerEmitter.cpp
 Error.cpp Error.h FastISelEmitter.cpp NeonEmitter.cpp Record.cpp Record.h
 SetTheory.cpp TGLexer.cpp TGLexer.h TGParser.h TableGen.cpp
Message-ID: <20110621225551.3FD522A6C12C@llvm.org>

Author: grosbach
Date: Tue Jun 21 17:55:50 2011
New Revision: 133568

URL: http://llvm.org/viewvc/llvm-project?rev=133568&view=rev
Log:
Consolidate some TableGen diagnostic helper functions.

TableGen had diagnostic printers sprinkled about in a few places. Pull them
together into a single location in Error.cpp.


Added:
    llvm/trunk/utils/TableGen/Error.cpp
    llvm/trunk/utils/TableGen/Error.h
Modified:
    llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
    llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
    llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
    llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
    llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
    llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
    llvm/trunk/utils/TableGen/FastISelEmitter.cpp
    llvm/trunk/utils/TableGen/NeonEmitter.cpp
    llvm/trunk/utils/TableGen/Record.cpp
    llvm/trunk/utils/TableGen/Record.h
    llvm/trunk/utils/TableGen/SetTheory.cpp
    llvm/trunk/utils/TableGen/TGLexer.cpp
    llvm/trunk/utils/TableGen/TGLexer.h
    llvm/trunk/utils/TableGen/TGParser.h
    llvm/trunk/utils/TableGen/TableGen.cpp

Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Tue Jun 21 17:55:50 2011
@@ -98,6 +98,7 @@
 
 #include "AsmMatcherEmitter.h"
 #include "CodeGenTarget.h"
+#include "Error.h"
 #include "Record.h"
 #include "StringMatcher.h"
 #include "llvm/ADT/OwningPtr.h"

Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Tue Jun 21 17:55:50 2011
@@ -14,6 +14,7 @@
 
 #include "AsmWriterEmitter.h"
 #include "AsmWriterInst.h"
+#include "Error.h"
 #include "CodeGenTarget.h"
 #include "Record.h"
 #include "StringToOffsetTable.h"

Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Tue Jun 21 17:55:50 2011
@@ -13,6 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "CodeGenDAGPatterns.h"
+#include "Error.h"
 #include "Record.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/STLExtras.h"

Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Tue Jun 21 17:55:50 2011
@@ -13,6 +13,7 @@
 
 #include "CodeGenInstruction.h"
 #include "CodeGenTarget.h"
+#include "Error.h"
 #include "Record.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringMap.h"

Modified: llvm/trunk/utils/TableGen/CodeGenRegisters.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenRegisters.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CodeGenRegisters.cpp (original)
+++ llvm/trunk/utils/TableGen/CodeGenRegisters.cpp Tue Jun 21 17:55:50 2011
@@ -14,6 +14,7 @@
 
 #include "CodeGenRegisters.h"
 #include "CodeGenTarget.h"
+#include "Error.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"
 

Modified: llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/DisassemblerEmitter.cpp Tue Jun 21 17:55:50 2011
@@ -9,6 +9,7 @@
 
 #include "DisassemblerEmitter.h"
 #include "CodeGenTarget.h"
+#include "Error.h"
 #include "Record.h"
 #include "X86DisassemblerTables.h"
 #include "X86RecognizableInstr.h"

Added: llvm/trunk/utils/TableGen/Error.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Error.cpp?rev=133568&view=auto
==============================================================================
--- llvm/trunk/utils/TableGen/Error.cpp (added)
+++ llvm/trunk/utils/TableGen/Error.cpp Tue Jun 21 17:55:50 2011
@@ -0,0 +1,39 @@
+//===- Error.cpp - tblgen error handling helper routines --------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains error handling helper routines to pretty-print diagnostic
+// messages from tblgen.
+//
+//===----------------------------------------------------------------------===//
+
+#include "Error.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/Support/raw_ostream.h"
+
+namespace llvm {
+
+SourceMgr SrcMgr;
+
+void PrintError(SMLoc ErrorLoc, const Twine &Msg) {
+  SrcMgr.PrintMessage(ErrorLoc, Msg, "error");
+}
+
+void PrintError(const char *Loc, const Twine &Msg) {
+  SrcMgr.PrintMessage(SMLoc::getFromPointer(Loc), Msg, "error");
+}
+
+void PrintError(const Twine &Msg) {
+  errs() << "error:" << Msg << "\n";
+}
+
+void PrintError(const TGError &Error) {
+  PrintError(Error.getLoc(), Error.getMessage());
+}
+
+} // end namespace llvm

Added: llvm/trunk/utils/TableGen/Error.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Error.h?rev=133568&view=auto
==============================================================================
--- llvm/trunk/utils/TableGen/Error.h (added)
+++ llvm/trunk/utils/TableGen/Error.h Tue Jun 21 17:55:50 2011
@@ -0,0 +1,43 @@
+//===- Error.h - tblgen error handling helper routines ----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains error handling helper routines to pretty-print diagnostic
+// messages from tblgen.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef ERROR_H
+#define ERROR_H
+
+#include "llvm/Support/SourceMgr.h"
+
+namespace llvm {
+
+class TGError {
+  SMLoc Loc;
+  std::string Message;
+public:
+  TGError(SMLoc loc, const std::string &message) : Loc(loc), Message(message) {}
+
+  SMLoc getLoc() const { return Loc; }
+  const std::string &getMessage() const { return Message; }
+};
+
+void PrintError(SMLoc ErrorLoc, const Twine &Msg);
+void PrintError(const char *Loc, const Twine &Msg);
+void PrintError(const Twine &Msg);
+void PrintError(const TGError &Error);
+
+
+extern SourceMgr SrcMgr;
+
+
+} // end namespace "llvm"
+
+#endif

Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Tue Jun 21 17:55:50 2011
@@ -18,6 +18,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "FastISelEmitter.h"
+#include "Error.h"
 #include "Record.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/VectorExtras.h"

Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Tue Jun 21 17:55:50 2011
@@ -24,6 +24,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "NeonEmitter.h"
+#include "Error.h"
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringExtras.h"

Modified: llvm/trunk/utils/TableGen/Record.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/Record.cpp (original)
+++ llvm/trunk/utils/TableGen/Record.cpp Tue Jun 21 17:55:50 2011
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "Record.h"
+#include "Error.h"
 #include "llvm/Support/DataTypes.h"
 #include "llvm/Support/Format.h"
 #include "llvm/ADT/StringExtras.h"

Modified: llvm/trunk/utils/TableGen/Record.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/Record.h (original)
+++ llvm/trunk/utils/TableGen/Record.h Tue Jun 21 17:55:50 2011
@@ -1486,22 +1486,8 @@
   }
 };
 
-
-class TGError {
-  SMLoc Loc;
-  std::string Message;
-public:
-  TGError(SMLoc loc, const std::string &message) : Loc(loc), Message(message) {}
-
-  SMLoc getLoc() const { return Loc; }
-  const std::string &getMessage() const { return Message; }
-};
-
-
 raw_ostream &operator<<(raw_ostream &OS, const RecordKeeper &RK);
 
-void PrintError(SMLoc ErrorLoc, const Twine &Msg);
-
 } // End llvm namespace
 
 #endif

Modified: llvm/trunk/utils/TableGen/SetTheory.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SetTheory.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SetTheory.cpp (original)
+++ llvm/trunk/utils/TableGen/SetTheory.cpp Tue Jun 21 17:55:50 2011
@@ -13,6 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "SetTheory.h"
+#include "Error.h"
 #include "Record.h"
 #include "llvm/Support/Format.h"
 

Modified: llvm/trunk/utils/TableGen/TGLexer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGLexer.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TGLexer.cpp (original)
+++ llvm/trunk/utils/TableGen/TGLexer.cpp Tue Jun 21 17:55:50 2011
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "TGLexer.h"
+#include "Error.h"
 #include "llvm/Support/SourceMgr.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Config/config.h"
@@ -35,7 +36,6 @@
   return SMLoc::getFromPointer(TokStart);
 }
 
-
 /// ReturnError - Set the error to the specified string at the specified
 /// location.  This is defined to always return tgtok::Error.
 tgtok::TokKind TGLexer::ReturnError(const char *Loc, const Twine &Msg) {
@@ -43,16 +43,6 @@
   return tgtok::Error;
 }
 
-
-void TGLexer::PrintError(const char *Loc, const Twine &Msg) const {
-  SrcMgr.PrintMessage(SMLoc::getFromPointer(Loc), Msg, "error");
-}
-
-void TGLexer::PrintError(SMLoc Loc, const Twine &Msg) const {
-  SrcMgr.PrintMessage(Loc, Msg, "error");
-}
-
-
 int TGLexer::getNextChar() {
   char CurChar = *CurPtr++;
   switch (CurChar) {

Modified: llvm/trunk/utils/TableGen/TGLexer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGLexer.h?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TGLexer.h (original)
+++ llvm/trunk/utils/TableGen/TGLexer.h Tue Jun 21 17:55:50 2011
@@ -101,9 +101,6 @@
   }
 
   SMLoc getLoc() const;
-
-  void PrintError(const char *Loc, const Twine &Msg) const;
-  void PrintError(SMLoc Loc, const Twine &Msg) const;
   
 private:
   /// LexToken - Read the next token and return its code.

Modified: llvm/trunk/utils/TableGen/TGParser.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TGParser.h?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TGParser.h (original)
+++ llvm/trunk/utils/TableGen/TGParser.h Tue Jun 21 17:55:50 2011
@@ -15,6 +15,7 @@
 #define TGPARSER_H
 
 #include "TGLexer.h"
+#include "Error.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/SourceMgr.h"
 #include <map>
@@ -60,7 +61,7 @@
   bool ParseFile();
   
   bool Error(SMLoc L, const Twine &Msg) const {
-    Lex.PrintError(L, Msg);
+    PrintError(L, Msg);
     return true;
   }
   bool TokError(const Twine &Msg) const {

Modified: llvm/trunk/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=133568&r1=133567&r2=133568&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TableGen.cpp (original)
+++ llvm/trunk/utils/TableGen/TableGen.cpp Tue Jun 21 17:55:50 2011
@@ -26,6 +26,7 @@
 #include "DAGISelEmitter.h"
 #include "DisassemblerEmitter.h"
 #include "EDEmitter.h"
+#include "Error.h"
 #include "FastISelEmitter.h"
 #include "InstrEnumEmitter.h"
 #include "InstrInfoEmitter.h"
@@ -194,12 +195,6 @@
 }
 
 
-static SourceMgr SrcMgr;
-
-void llvm::PrintError(SMLoc ErrorLoc, const Twine &Msg) {
-  SrcMgr.PrintMessage(ErrorLoc, Msg, "error");
-}
-
 int main(int argc, char **argv) {
   RecordKeeper Records;
 
@@ -403,13 +398,11 @@
     return 0;
 
   } catch (const TGError &Error) {
-    errs() << argv[0] << ": error:\n";
-    PrintError(Error.getLoc(), Error.getMessage());
-
+    PrintError(Error);
   } catch (const std::string &Error) {
-    errs() << argv[0] << ": " << Error << "\n";
+    PrintError(Error);
   } catch (const char *Error) {
-    errs() << argv[0] << ": " << Error << "\n";
+    PrintError(Error);
   } catch (...) {
     errs() << argv[0] << ": Unknown unexpected exception occurred.\n";
   }



From isanbard at gmail.com  Tue Jun 21 18:02:38 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Tue, 21 Jun 2011 16:02:38 -0700
Subject: [llvm-commits] [llvm] r133561 -
 /llvm/trunk/lib/CodeGen/AsmPrinter/DwarfException.cpp
In-Reply-To: <8BD87ACA-1476-436B-8F59-06A45877992E@apple.com>
References: <20110621224024.9A6412A6C12C@llvm.org>
	<8BD87ACA-1476-436B-8F59-06A45877992E@apple.com>
Message-ID: <62AE249D-146C-4F65-82B4-45BED4BCC0BF@gmail.com>

On Jun 21, 2011, at 3:50 PM, Jim Grosbach wrote:

> Yay! Thanks, Bill. This, together with your other annotation patches, is a huge help reading these things.

Thanks! Though unfortunately the annotation patch didn't survive. Not only was it buggy, but as Chris pointed out having it in the AsmPrinter instead of the MC stuff made more sense. We lose the ability to annotate a .s file. But we should be analyzing only those .s files coming from clang, so ... :-)

-bw



From dpatel at apple.com  Tue Jun 21 18:02:36 2011
From: dpatel at apple.com (Devang Patel)
Date: Tue, 21 Jun 2011 23:02:36 -0000
Subject: [llvm-commits] [llvm] r133569 -
	/llvm/trunk/lib/CodeGen/RegAllocFast.cpp
Message-ID: <20110621230236.B4B2E2A6C12C@llvm.org>

Author: dpatel
Date: Tue Jun 21 18:02:36 2011
New Revision: 133569

URL: http://llvm.org/viewvc/llvm-project?rev=133569&view=rev
Log:
After register is spilled there should not be any DBG_VALUE referring the same register.

Modified:
    llvm/trunk/lib/CodeGen/RegAllocFast.cpp

Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=133569&r1=133568&r2=133569&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Jun 21 18:02:36 2011
@@ -293,9 +293,11 @@
         MachineBasicBlock *MBB = DBG->getParent();
         MBB->insert(MI, NewDV);
         DEBUG(dbgs() << "Inserting debug info due to spill:" << "\n" << *NewDV);
-        LRIDbgValues[li] = NewDV;
       }
     }
+    // Now this register is spilled there is should not be any DBG_VALUE pointing
+    // to this register because they are all pointing to spilled value now.
+    LRIDbgValues.clear();
     if (SpillKill)
       LR.LastUse = 0; // Don't kill register again
   }



From nlewycky at google.com  Tue Jun 21 18:19:01 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Tue, 21 Jun 2011 16:19:01 -0700
Subject: [llvm-commits] patch: fix emission of npot vectors which need
 trailing padding
In-Reply-To: <BANLkTikqZYc=LyAbboTr=xHO2adgD4OfMw@mail.gmail.com>
References: <BANLkTinhSx1XZV_6kDR8e3U=YP4V1rQuXA@mail.gmail.com>
	<BANLkTikqZYc=LyAbboTr=xHO2adgD4OfMw@mail.gmail.com>
Message-ID: <BANLkTikxRPdVZp6eVYunfzN9GyMfE_T7o2_Wgbi1pVFEKFdacQ@mail.gmail.com>

Hi Renato! Sorry, but I don't understand your reply at all.

The correctness of this patch is dependent on whether an LLVM vector should
ever have trailing padding (not element padding). If the answer is no
regardless of platform, then we should add an assertion in this spot instead
of code to write out padding.

There's nothing ARM-specific about this change, which is why it belongs in
generic CodeGen and shouldn't be in the ARMAsmPrinter. It just so happens
that <3 x float> on ARM provides a counter-example that would require this
padding or trigger this assertion.

If we agree that they should never be padded, then the backend would be
responsible for either expanding the <3 x float> into a <4 x float>, or else
breaking it into <2 x float> + float. Is that what you're arguing for?

Alternatively, if you want <3 x float> to be 12 bytes and densely packed,
that'd be an independent change. You'd want to modify what TargetData says
about the <3 x float>, so that the computation performed by GEP, etc., all
line up. Currently I'm just fixing EmitGlobalConstantVector to emit n-bytes
when target data says the vector is n-bytes long.

Nick

On 21 June 2011 01:45, Renato Golin <renato.golin at arm.com> wrote:

> On 21 June 2011 06:52, Nick Lewycky <nlewycky at google.com> wrote:
> > This lowers to a struct with <3 x float>, which TargetData says is 16
> bytes
> > on ARM.
>
> Hi Nick,
>
> This only makes sense for ARM with NEON/VFP, unless selection-DAG
> identifies it and remove the padding to avoid extra instructions being
> generated for the CPU when NEON/VFP is not present.
>
> Anyone knows if that's the case?
>
>
> > In LLVM IR, the first element becomes a constant aggregate zero,
> > which is emitted by looking at how many bytes it is (sixteen) and writing
> > out a zero-fill. The second element is emitted as three contiguous
> elements,
> > resulting in a total of 12 bytes.
>
> I agree, we should have consistency here.
>
>
> > The StructLayout object claims that each of those should be 16 bytes, so
> I
> > changed the AsmPrinter in CodeGen to apply padding to the end of an array
> to
> > match what TargetData thinks the length of the array is. Patch attached,
> > please review!
>
> Not sure you changed the right place. I agree that alignment is
> important for all platforms but I wouldn't make such an assumption
> without a set of tests for each one of them.
>
> If everyone is happy that such padding needs to be dealt with by the
> generic CodeGen, I won't oppose, but would be good to have at least
> one test for each major architecture.
>
> Otherwise, if you move it to ARMAsmPrinter, I still suggest you to
> write a simple IR-to-ASM test and check data sizes.
>
> cheers,
> --renato
>
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From pichet2000 at gmail.com  Tue Jun 21 18:19:23 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Tue, 21 Jun 2011 23:19:23 -0000
Subject: [llvm-commits] [llvm] r133574 -
	/llvm/trunk/utils/TableGen/CMakeLists.txt
Message-ID: <20110621231923.7B3E22A6C12C@llvm.org>

Author: fpichet
Date: Tue Jun 21 18:19:23 2011
New Revision: 133574

URL: http://llvm.org/viewvc/llvm-project?rev=133574&view=rev
Log:
Unbreak the CMake build

Modified:
    llvm/trunk/utils/TableGen/CMakeLists.txt

Modified: llvm/trunk/utils/TableGen/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CMakeLists.txt?rev=133574&r1=133573&r2=133574&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/CMakeLists.txt (original)
+++ llvm/trunk/utils/TableGen/CMakeLists.txt Tue Jun 21 18:19:23 2011
@@ -25,6 +25,7 @@
   DAGISelMatcher.cpp
   DisassemblerEmitter.cpp
   EDEmitter.cpp
+  Error.cpp
   FastISelEmitter.cpp
   FixedLenDecoderEmitter.cpp
   InstrEnumEmitter.cpp



From eli.friedman at gmail.com  Tue Jun 21 18:31:02 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Tue, 21 Jun 2011 16:31:02 -0700
Subject: [llvm-commits] patch: fix emission of npot vectors which need
 trailing padding
In-Reply-To: <BANLkTikxRPdVZp6eVYunfzN9GyMfE_T7o2_Wgbi1pVFEKFdacQ@mail.gmail.com>
References: <BANLkTinhSx1XZV_6kDR8e3U=YP4V1rQuXA@mail.gmail.com>
	<BANLkTikqZYc=LyAbboTr=xHO2adgD4OfMw@mail.gmail.com>
	<BANLkTikxRPdVZp6eVYunfzN9GyMfE_T7o2_Wgbi1pVFEKFdacQ@mail.gmail.com>
Message-ID: <BANLkTinjuEbbLpPeJyvqocrW_S7se5=xkw@mail.gmail.com>

On Tue, Jun 21, 2011 at 4:19 PM, Nick Lewycky <nlewycky at google.com> wrote:
> Hi Renato! Sorry, but I don't understand your reply at all.
> The correctness of this patch is dependent on whether an LLVM vector should
> ever have trailing padding (not element padding). If the answer is no
> regardless of platform, then we should add an assertion in this spot instead
> of code to write out padding.
> There's nothing ARM-specific about this change, which is why it belongs in
> generic CodeGen and shouldn't be in the ARMAsmPrinter.?It just so happens
> that <3 x float> on ARM provides a counter-example that would require this
> padding or trigger this assertion.

Take the following on x86:

typedef float float3 __attribute__((ext_vector_type(3)));
int printf(const char*,...);
struct Foo { float3 x, y; };
struct Foo foo = { {1,2,3}, {1, 2, 3} };
int main() { float3 y = foo.y; printf("%f\n", y[2]); return 0; }

It currently gets miscomputed because of this issue... so definitely
not ARM-specific.

-Eli


From tobias at grosser.es  Tue Jun 21 18:37:56 2011
From: tobias at grosser.es (Tobias Grosser)
Date: Tue, 21 Jun 2011 20:37:56 -0300
Subject: [llvm-commits] [polly] r133354
	-	/polly/trunk/www/documentation/memaccess.html
In-Reply-To: <20110618171716.444342A6C12C@llvm.org>
References: <20110618171716.444342A6C12C@llvm.org>
Message-ID: <4E012B54.3090403@grosser.es>

On 06/18/2011 02:17 PM, Raghesh Aloor wrote:
> Author: raghesh
> Date: Sat Jun 18 12:17:16 2011
> New Revision: 133354
>
> URL: http://llvm.org/viewvc/llvm-project?rev=133354&view=rev
> Log:
> www: Adding webpage to track memory access transformation

Hi Raghesh,

thanks for your work. I still have some comments:

You forgot to add the disclaimer that this is a work in progress 
project. Furthermore, the HTML you used is pretty noisy (details 
inline). The next time we should review it before committing.

> Added:
>      polly/trunk/www/documentation/memaccess.html
>
> Added: polly/trunk/www/documentation/memaccess.html
> URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/documentation/memaccess.html?rev=133354&view=auto
> ==============================================================================
> --- polly/trunk/www/documentation/memaccess.html (added)
> +++ polly/trunk/www/documentation/memaccess.html Sat Jun 18 12:17:16 2011
> @@ -0,0 +1,143 @@
> +<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
> +<html>
> +<head>
> +<meta content="text/html; charset=ISO-8859-1"
> + http-equiv="Content-Type">
> +<title>memaccess.html</title>

Can you use a title like 'Polly - Memory access optimizations'
You should include menu.css and content.css

I propose to just use the header from documention/passes.html as a 
template. (This is true for most of the comments I give)


<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
           "http://www.w3.org/TR/html4/strict.dtd">
<!-- Material used from: HTML 4.01 specs: http://www.w3.org/TR/html401/ -->
<html> 

<head> 

   <META http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
   <title>Polly - The available LLVM passes</title>
   <link type="text/css" rel="stylesheet" href="../menu.css">
   <link type="text/css" rel="stylesheet" href="../content.css">
</head>

> +</head>
> +<body>

You miss the line to include the menu.
<!--#include virtual="../menu.html.incl"-->

> +<div style="margin-left: 320px;"><small style="font-weight: bold;"><small><a><big><big><big>Support

Just create a large div with id="content" that includes the whole 
content of this page.

> +for
> +memory access
> +transformations in Polly</big></big></big></a></small></small><big><span
> + style="font-weight: bold;"></span></big><br>
Use <h1> for the header. All the other tags are just noise and disallow 
a consistent design.

> +<big><span style="font-weight: bold;"></span></big><br>
Useless noise.

> +<div style="text-align: left;">
This does not seem to be needed.

> +<strong></strong>
Useless noise.


> +This project adds
> +memory access transformations to Polly. In many cases<br>
<br> Not needed.

> +changing the memory access pattern yields to better data
> +locality or removes<br>
<br> not needed.

> +dependences that would otherwise block
> +transformations. They may also<br>
                   . Memory access transformations may also ...

<br> not needed

> +allow LLVM to use registers to store
> +certain values.<br>
<br> not needed

> +</div>
> +<br>
<br> not needed.

> +An examples which uses this feature is given below<br>
This seems to be a new paragraph. Put it in a <p></p> to get the newlines.

> +</div>
> +<div style="margin-left: 320px;"><br>
I do not see a reason for this <div>

> +Consider the following loop
> +<ul>
> +<ul>
> +</ul>
> +</ul>
Useless noise.

> +<div style="margin-left: 40px;"><small style="font-style: italic;">
Just use <pre> to format the code.

> + for
> +(i = 0; i&lt; 8; i++)</small><br>
> +<small style="font-style: italic;">sum += A[i];</small><br
> + style="font-style: italic;">
All this formatting and <br> not needed.

> +</div>
> +<br>
> +With support for memory access transformation this loop can be executed<br>
> +in parallel. It can be
> +transformed to

 > +<small style="font-style: italic;"><br>
> +<br>
> +</small>
Useless noise.

> +<div style="margin-left: 40px;">
<div> not needed.

 > +<small style="font-style: italic;">&lt;create
> +and
> +initialize an array 'tmp'
> +with size 4&gt;</small><br>
> +<small style="font-style: italic;">for (i = 0; i&lt; 8; i++) {</small><br>
> +<small style="font-style: italic;">tmp[i % 4] += A[i];</small><br>
> +<small style="font-style: italic;">}</small><small><span
> + style="font-style: italic;"></span></small><br>
> +<small><span style="font-style: italic;">sum = tmp[0] + tmp[1] + tmp[2]
> ++ tmp[3];</span></small><br>
All formatting not needed. Just use a big <pre> block.

> +</div>
> +<br>
> +With the help of some optimizer (like
> +PluTo) the following code can be<br>
<br> not needed.

"With the help of optimizers like PluTo the following

> +generated, where the outer loop is
> +parallel.
> +<p style="padding-left: 30px; font-style: italic;"><small>parfor (ii =
> +0; ii&lt; 4; ii++) {<br>
> +&nbsp;&nbsp; tmp[ii] = 0;<br>
> +&nbsp;&nbsp;&nbsp; for (i = ii * 2; i&lt; (ii+1) * 2; i++)<br>
> +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tmp[ii] += A[i];</small></p>
> +<p style="padding-left: 30px; font-style: italic; font-weight: bold;"><small><span
> + style="font-weight: normal;">}</span><br style="font-weight: normal;">
> +<span style="font-weight: normal;">sum = tmp[0] + tmp[1] + tmp[2] +
> +tmp[3];</span><br>
> +<strong></strong></small></p>
Useless style noise. Just use <pre>

> +<p><strong><span style="text-decoration: underline;">TODO<br>
> +</span></strong></p>
Do not use <strong><span><p> here. Just use <h2>

> +<p><strong><span style="text-decoration: underline;"><small>Step 1</small><br>
> +</span></strong></p>
Just use <h3>

> +Polly exports its polyhedral description in a JSCoP file. Define how
> +memory
 > +<small><br>
> +</small>
Useless noise. <br> not needed.

> +layout transformations are going to be expressed in Polly and
> +in
> +the JSCOP file.<br>

> +A simple example is given below.<br>
> +<br>
> +Consider the following loop.<br>
> +<br>
<br> not needed. Use <p> to mark a paragraph.

> +<div style="margin-left: 40px;"><small><span style="font-style: italic;">for
> +(i
> += 0; i&lt; 12; i++)</span><br style="font-style: italic;">
> +<span style="font-style: italic;">&nbsp;&nbsp;&nbsp;&nbsp; A[i] = 0;</span><br
> + style="font-style: italic;">
> +</small></div>
Useless style noise. Just use <pre>.

> +<br>
> +In the JSCOP file the memory is represented as follows.<br>
> +<br>
> +<div style="margin-left: 40px;"><small><span style="font-style: italic;">&nbsp;&nbsp;
> +"accesses":
> +[{</span></small><br style="font-style: italic;">
> +<small><span style="font-style: italic;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
> +"kind":
> +"write",</span></small><br style="font-style: italic;">
> +<small><span style="font-style: italic;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
> +"relation":
> +"{
> +Stmt[i] -&gt;</span><strong
> + style="font-style: italic; font-weight: bold;">A</strong><span
> + style="font-style: italic;"><span style="font-weight: bold;">[i]</span>
> +}"</span></small><br style="font-style: italic;">
> +<small><span style="font-style: italic;">&nbsp;&nbsp;&nbsp; }]</span></small><br
> + style="font-style: italic;">
> +</div>
Useless style noise and &nbsp;. Just use <pre>

> +<br>
> +Suppose
> +we want to perform a transformation such that the following<br>
> +code is generated<br>
> +<br>
Get rid of <br> and use a single <p>.

> +<div style="margin-left: 40px;"><small><span style="font-style: italic;">for
> +(i
> += 0; i&lt; 12; i++)</span><br style="font-style: italic;">
> +<span style="font-style: italic;">
> +&nbsp;&nbsp;&nbsp;&nbsp; A[0] = i;</span><br style="font-style: italic;">
> +</small></div>
Style noise. Use <pre>.

> +<br>
> +The corresponding JSCOP file represenation would be<br>
> +<br>
> +<div style="margin-left: 40px;"><small><span style="font-style: italic;">&nbsp;&nbsp;&nbsp;
> +"accesses":
> +[{</span><br style="font-style: italic;">
> +<span style="font-style: italic;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
> +"kind":
> +"read",</span><br style="font-style: italic;">
> +<span style="font-style: italic;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
Style and &nbsp; noise. Just use <pre>.

> +"relation":
> +"{
> +Stmt[i] -&gt;</span><strong
> + style="font-style: italic; font-weight: bold;">A</strong><span
Please don't use any inline style specifiers. If you want to highlight 
something use <em> or <b>. For anything else define a new style in the 
.css files after verifying something similar is not available.

> + style="font-style: italic;"><span style="font-weight: bold;">[0]</span>
> +}"</span><br style="font-style: italic;">
> +<span style="font-style: italic;">&nbsp;&nbsp;&nbsp; }]</span><br
> + style="font-style: italic;">
> +</small></div>
Style noise.

> +<br>
> +We need to detect this access function change.<br>
> +</div>
> +<span id="q_12f99e5de7fd0932_1" class="h4"></span>
Is this needed for anything?

> +</body>
> +</html>

Again, thanks for your work
Tobi

From dpatel at apple.com  Tue Jun 21 19:03:42 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 22 Jun 2011 00:03:42 -0000
Subject: [llvm-commits] [llvm] r133585 -
	/llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll
Message-ID: <20110622000343.08D202A6C12C@llvm.org>

Author: dpatel
Date: Tue Jun 21 19:03:42 2011
New Revision: 133585

URL: http://llvm.org/viewvc/llvm-project?rev=133585&view=rev
Log:
Test case for r133560.

Added:
    llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll

Added: llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll?rev=133585&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/debug-info-blocks.ll Tue Jun 21 19:03:42 2011
@@ -0,0 +1,245 @@
+; RUN: llc -O0 < %s | FileCheck %s
+; CHECK: @DEBUG_VALUE: mydata <- [sp+#8]+#0
+; Radar 9331779
+target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
+target triple = "thumbv7-apple-macosx10.7.0"
+
+%0 = type opaque
+%1 = type { [4 x i32] }
+%2 = type <{ i8*, i32, i32, i8*, %struct.Re*, i8*, %3*, %struct.my_struct* }>
+%3 = type opaque
+%struct.CP = type { float, float }
+%struct.CR = type { %struct.CP, %struct.CP }
+%struct.Re = type { i32, i32 }
+%struct.__block_byref_mydata = type { i8*, %struct.__block_byref_mydata*, i32, i32, i8*, i8*, %0* }
+%struct.my_struct = type opaque
+
+@"\01L_OBJC_SELECTOR_REFERENCES_13" = external hidden global i8*, section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
+@"OBJC_IVAR_$_MyWork._bounds" = external hidden global i32, section "__DATA, __objc_const", align 4
+@"OBJC_IVAR_$_MyWork._data" = external hidden global i32, section "__DATA, __objc_const", align 4
+@"\01L_OBJC_SELECTOR_REFERENCES_222" = external hidden global i8*, section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip"
+
+declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone
+
+declare i8* @objc_msgSend(i8*, i8*, ...)
+
+declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
+
+declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
+
+define hidden void @foobar_func_block_invoke_0(i8* %.block_descriptor, %0* %loadedMydata, [4 x i32] %bounds.coerce0, [4 x i32] %data.coerce0) ssp {
+  %1 = alloca %0*, align 4
+  %bounds = alloca %struct.CR, align 4
+  %data = alloca %struct.CR, align 4
+  call void @llvm.dbg.value(metadata !{i8* %.block_descriptor}, i64 0, metadata !27), !dbg !129
+  store %0* %loadedMydata, %0** %1, align 4
+  call void @llvm.dbg.declare(metadata !{%0** %1}, metadata !130), !dbg !131
+  %2 = bitcast %struct.CR* %bounds to %1*
+  %3 = getelementptr %1* %2, i32 0, i32 0
+  store [4 x i32] %bounds.coerce0, [4 x i32]* %3
+  call void @llvm.dbg.declare(metadata !{%struct.CR* %bounds}, metadata !132), !dbg !133
+  %4 = bitcast %struct.CR* %data to %1*
+  %5 = getelementptr %1* %4, i32 0, i32 0
+  store [4 x i32] %data.coerce0, [4 x i32]* %5
+  call void @llvm.dbg.declare(metadata !{%struct.CR* %data}, metadata !134), !dbg !135
+  %6 = bitcast i8* %.block_descriptor to %2*
+  %7 = getelementptr inbounds %2* %6, i32 0, i32 6
+  call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !136), !dbg !137
+  call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !138), !dbg !137
+  call void @llvm.dbg.declare(metadata !{%2* %6}, metadata !139), !dbg !140
+  %8 = load %0** %1, align 4, !dbg !141
+  %9 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_13", !dbg !141
+  %10 = bitcast %0* %8 to i8*, !dbg !141
+  %11 = call i8* bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to i8* (i8*, i8*)*)(i8* %10, i8* %9), !dbg !141
+  %12 = bitcast i8* %11 to %0*, !dbg !141
+  %13 = getelementptr inbounds %2* %6, i32 0, i32 5, !dbg !141
+  %14 = load i8** %13, !dbg !141
+  %15 = bitcast i8* %14 to %struct.__block_byref_mydata*, !dbg !141
+  %16 = getelementptr inbounds %struct.__block_byref_mydata* %15, i32 0, i32 1, !dbg !141
+  %17 = load %struct.__block_byref_mydata** %16, !dbg !141
+  %18 = getelementptr inbounds %struct.__block_byref_mydata* %17, i32 0, i32 6, !dbg !141
+  store %0* %12, %0** %18, align 4, !dbg !141
+  %19 = getelementptr inbounds %2* %6, i32 0, i32 6, !dbg !143
+  %20 = load %3** %19, align 4, !dbg !143
+  %21 = load i32* @"OBJC_IVAR_$_MyWork._data", !dbg !143
+  %22 = bitcast %3* %20 to i8*, !dbg !143
+  %23 = getelementptr inbounds i8* %22, i32 %21, !dbg !143
+  %24 = bitcast i8* %23 to %struct.CR*, !dbg !143
+  %25 = bitcast %struct.CR* %24 to i8*, !dbg !143
+  %26 = bitcast %struct.CR* %data to i8*, !dbg !143
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %25, i8* %26, i32 16, i32 4, i1 false), !dbg !143
+  %27 = getelementptr inbounds %2* %6, i32 0, i32 6, !dbg !144
+  %28 = load %3** %27, align 4, !dbg !144
+  %29 = load i32* @"OBJC_IVAR_$_MyWork._bounds", !dbg !144
+  %30 = bitcast %3* %28 to i8*, !dbg !144
+  %31 = getelementptr inbounds i8* %30, i32 %29, !dbg !144
+  %32 = bitcast i8* %31 to %struct.CR*, !dbg !144
+  %33 = bitcast %struct.CR* %32 to i8*, !dbg !144
+  %34 = bitcast %struct.CR* %bounds to i8*, !dbg !144
+  call void @llvm.memcpy.p0i8.p0i8.i32(i8* %33, i8* %34, i32 16, i32 4, i1 false), !dbg !144
+  %35 = getelementptr inbounds %2* %6, i32 0, i32 6, !dbg !145
+  %36 = load %3** %35, align 4, !dbg !145
+  %37 = getelementptr inbounds %2* %6, i32 0, i32 5, !dbg !145
+  %38 = load i8** %37, !dbg !145
+  %39 = bitcast i8* %38 to %struct.__block_byref_mydata*, !dbg !145
+  %40 = getelementptr inbounds %struct.__block_byref_mydata* %39, i32 0, i32 1, !dbg !145
+  %41 = load %struct.__block_byref_mydata** %40, !dbg !145
+  %42 = getelementptr inbounds %struct.__block_byref_mydata* %41, i32 0, i32 6, !dbg !145
+  %43 = load %0** %42, align 4, !dbg !145
+  %44 = load i8** @"\01L_OBJC_SELECTOR_REFERENCES_222", !dbg !145
+  %45 = bitcast %3* %36 to i8*, !dbg !145
+  call void bitcast (i8* (i8*, i8*, ...)* @objc_msgSend to void (i8*, i8*, %0*)*)(i8* %45, i8* %44, %0* %43), !dbg !145
+  ret void, !dbg !146
+}
+
+!llvm.dbg.cu = !{!0}
+!llvm.dbg.enum = !{!1, !1, !5, !5, !9, !14, !19, !19, !14, !14, !14, !19, !19, !19}
+!llvm.dbg.sp = !{!23}
+
+!0 = metadata !{i32 589841, i32 0, i32 16, metadata !"MyLibrary.i", metadata !"/Volumes/Sandbox/llvm", metadata !"Apple clang version 2.1", i1 true, i1 false, metadata !"", i32 2} ; [ DW_TAG_compile_unit ]
+!1 = metadata !{i32 589828, metadata !0, metadata !"", metadata !2, i32 248, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !3, i32 0, i32 0} ; [ DW_TAG_enumeration_type ]
+!2 = metadata !{i32 589865, metadata !"header.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ]
+!3 = metadata !{metadata !4}
+!4 = metadata !{i32 589864, metadata !"Ver1", i64 0} ; [ DW_TAG_enumerator ]
+!5 = metadata !{i32 589828, metadata !0, metadata !"Mode", metadata !6, i32 79, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !7, i32 0, i32 0} ; [ DW_TAG_enumeration_type ]
+!6 = metadata !{i32 589865, metadata !"header2.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ]
+!7 = metadata !{metadata !8}
+!8 = metadata !{i32 589864, metadata !"One", i64 0} ; [ DW_TAG_enumerator ]
+!9 = metadata !{i32 589828, metadata !0, metadata !"", metadata !10, i32 15, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !11, i32 0, i32 0} ; [ DW_TAG_enumeration_type ]
+!10 = metadata !{i32 589865, metadata !"header3.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ]
+!11 = metadata !{metadata !12, metadata !13}
+!12 = metadata !{i32 589864, metadata !"Unknown", i64 0} ; [ DW_TAG_enumerator ]
+!13 = metadata !{i32 589864, metadata !"Known", i64 1} ; [ DW_TAG_enumerator ]
+!14 = metadata !{i32 589828, metadata !0, metadata !"", metadata !15, i32 20, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !16, i32 0, i32 0} ; [ DW_TAG_enumeration_type ]
+!15 = metadata !{i32 589865, metadata !"Private.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ]
+!16 = metadata !{metadata !17, metadata !18}
+!17 = metadata !{i32 589864, metadata !"Single", i64 0} ; [ DW_TAG_enumerator ]
+!18 = metadata !{i32 589864, metadata !"Double", i64 1} ; [ DW_TAG_enumerator ]
+!19 = metadata !{i32 589828, metadata !0, metadata !"", metadata !20, i32 14, i64 32, i64 32, i32 0, i32 0, i32 0, metadata !21, i32 0, i32 0} ; [ DW_TAG_enumeration_type ]
+!20 = metadata !{i32 589865, metadata !"header4.h", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ]
+!21 = metadata !{metadata !22}
+!22 = metadata !{i32 589864, metadata !"Eleven", i64 0} ; [ DW_TAG_enumerator ]
+!23 = metadata !{i32 589870, i32 0, metadata !24, metadata !"foobar_func_block_invoke_0", metadata !"foobar_func_block_invoke_0", metadata !"", metadata !24, i32 609, metadata !25, i1 true, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, void (i8*, %0*, [4 x i32], [4 x i32])* @foobar_func_block_invoke_0, null, null} ; [ DW_TAG_subprogram ]
+!24 = metadata !{i32 589865, metadata !"MyLibrary.m", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ]
+!25 = metadata !{i32 589845, metadata !24, metadata !"", metadata !24, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !26, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
+!26 = metadata !{null}
+!27 = metadata !{i32 590081, metadata !23, metadata !".block_descriptor", metadata !24, i32 16777825, metadata !28, i32 64} ; [ DW_TAG_arg_variable ]
+!28 = metadata !{i32 589839, metadata !0, metadata !"", null, i32 0, i64 32, i64 0, i64 0, i32 0, metadata !29} ; [ DW_TAG_pointer_type ]
+!29 = metadata !{i32 589843, metadata !24, metadata !"__block_literal_14", metadata !24, i32 609, i64 256, i64 32, i32 0, i32 0, i32 0, metadata !30, i32 0, i32 0} ; [ DW_TAG_structure_type ]
+!30 = metadata !{metadata !31, metadata !33, metadata !35, metadata !36, metadata !37, metadata !48, metadata !89, metadata !124}
+!31 = metadata !{i32 589837, metadata !24, metadata !"__isa", metadata !24, i32 609, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_member ]
+!32 = metadata !{i32 589839, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, null} ; [ DW_TAG_pointer_type ]
+!33 = metadata !{i32 589837, metadata !24, metadata !"__flags", metadata !24, i32 609, i64 32, i64 32, i64 32, i32 0, metadata !34} ; [ DW_TAG_member ]
+!34 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!35 = metadata !{i32 589837, metadata !24, metadata !"__reserved", metadata !24, i32 609, i64 32, i64 32, i64 64, i32 0, metadata !34} ; [ DW_TAG_member ]
+!36 = metadata !{i32 589837, metadata !24, metadata !"__FuncPtr", metadata !24, i32 609, i64 32, i64 32, i64 96, i32 0, metadata !32} ; [ DW_TAG_member ]
+!37 = metadata !{i32 589837, metadata !24, metadata !"__descriptor", metadata !24, i32 609, i64 32, i64 32, i64 128, i32 0, metadata !38} ; [ DW_TAG_member ]
+!38 = metadata !{i32 589839, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !39} ; [ DW_TAG_pointer_type ]
+!39 = metadata !{i32 589843, metadata !0, metadata !"__block_descriptor_withcopydispose", metadata !40, i32 307, i64 128, i64 32, i32 0, i32 0, i32 0, metadata !41, i32 0, i32 0} ; [ DW_TAG_structure_type ]
+!40 = metadata !{i32 589865, metadata !"MyLibrary.i", metadata !"/Volumes/Sandbox/llvm", metadata !0} ; [ DW_TAG_file_type ]
+!41 = metadata !{metadata !42, metadata !44, metadata !45, metadata !47}
+!42 = metadata !{i32 589837, metadata !40, metadata !"reserved", metadata !40, i32 307, i64 32, i64 32, i64 0, i32 0, metadata !43} ; [ DW_TAG_member ]
+!43 = metadata !{i32 589860, metadata !0, metadata !"long unsigned int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 7} ; [ DW_TAG_base_type ]
+!44 = metadata !{i32 589837, metadata !40, metadata !"Size", metadata !40, i32 307, i64 32, i64 32, i64 32, i32 0, metadata !43} ; [ DW_TAG_member ]
+!45 = metadata !{i32 589837, metadata !40, metadata !"CopyFuncPtr", metadata !40, i32 307, i64 32, i64 32, i64 64, i32 0, metadata !46} ; [ DW_TAG_member ]
+!46 = metadata !{i32 589839, metadata !0, metadata !"", null, i32 0, i64 32, i64 32, i64 0, i32 0, metadata !32} ; [ DW_TAG_pointer_type ]
+!47 = metadata !{i32 589837, metadata !40, metadata !"DestroyFuncPtr", metadata !40, i32 307, i64 32, i64 32, i64 96, i32 0, metadata !46} ; [ DW_TAG_member ]
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From justin.holewinski at gmail.com  Tue Jun 21 19:43:56 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Wed, 22 Jun 2011 00:43:56 -0000
Subject: [llvm-commits] [llvm] r133589 - in /llvm/trunk:
 lib/Target/PTX/PTXAsmPrinter.cpp test/CodeGen/PTX/options.ll
Message-ID: <20110622004356.D0DE82A6C12C@llvm.org>

Author: jholewinski
Date: Tue Jun 21 19:43:56 2011
New Revision: 133589

URL: http://llvm.org/viewvc/llvm-project?rev=133589&view=rev
Log:
PTX: Add .address_size directive if PTX version >= 2.3

Patch by Wei-Ren Chen

Modified:
    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
    llvm/trunk/test/CodeGen/PTX/options.ll

Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133589&r1=133588&r2=133589&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Tue Jun 21 19:43:56 2011
@@ -163,6 +163,13 @@
   OutStreamer.EmitRawText(Twine("\t.target " + ST.getTargetString() +
                                 (ST.supportsDouble() ? ""
                                                      : ", map_f64_to_f32")));
+  // .address_size directive is optional, but it must immediately follow
+  // the .target directive if present within a module
+  if (ST.supportsPTX23()) {
+    std::string addrSize = ST.is64Bit() ? "64" : "32";
+    OutStreamer.EmitRawText(Twine("\t.address_size " + addrSize));
+  }
+
   OutStreamer.AddBlankLine();
 
   // declare global variables

Modified: llvm/trunk/test/CodeGen/PTX/options.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/options.ll?rev=133589&r1=133588&r2=133589&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/options.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/options.ll Tue Jun 21 19:43:56 2011
@@ -5,6 +5,8 @@
 ; RUN: llc < %s -march=ptx32 -mattr=sm10 | grep ".target sm_10"
 ; RUN: llc < %s -march=ptx32 -mattr=sm13 | grep ".target sm_13"
 ; RUN: llc < %s -march=ptx32 -mattr=sm20 | grep ".target sm_20"
+; RUN: llc < %s -march=ptx32 -mattr=ptx23 | grep ".address_size 32"
+; RUN: llc < %s -march=ptx64 -mattr=ptx23 | grep ".address_size 64"
 
 define ptx_device void @t1() {
 	ret void



From justin.holewinski at gmail.com  Tue Jun 21 19:53:57 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Tue, 21 Jun 2011 20:53:57 -0400
Subject: [llvm-commits] [PATCH][Target/PTX] Add address_size directive
	to PTX backend
In-Reply-To: <20110621013634.GA86556@cs.nctu.edu.tw>
References: <20110617073109.GA93378@cs.nctu.edu.tw>
	<CA57A5F6-2F8E-4AAC-B6E7-279DA5F2D8EE@gmail.com>
	<20110618065617.GA25444@cs.nctu.edu.tw>
	<B3C74E93-B790-4255-808D-DBB9E94278C6@gmail.com>
	<20110619121258.GA50677@cs.nctu.edu.tw>
	<347A9771-6ADD-4454-86D6-2842AEA82D44@gmail.com>
	<20110620015129.GA56262@cs.nctu.edu.tw>
	<BD989BFB-373E-4577-8F21-C544F561DA49@gmail.com>
	<20110621013634.GA86556@cs.nctu.edu.tw>
Message-ID: <6005FDC7-17E5-4E89-8561-5EC94F14DF34@gmail.com>


On Jun 20, 2011, at 9:36 PM, ??? wrote:

>> I hate to nit-pick, but do we really need the address size field and associated enumeration?  It's always tied to the 64-bit flag, and we do not need to create any TableGen predicates from the value.
>> 
>> I think this patch can be as simple as:
>> 
>> if (ST.supportsPTX23()) {
>>  std::string addrSize = is64Bit() ? "64" : "32";
>>  OutStreamer.EmitRawText(Twine("\t.address_size " + addrSize));
>> }
> 
>  Done.

Looks good!  Committed in r133589.

> 
> Regards,
> chenwj
> 
> -- 
> Wei-Ren Chen (???)
> Computer Systems Lab, Institute of Information Science,
> Academia Sinica, Taiwan (R.O.C.)
> Tel:886-2-2788-3799 #1667
> <patch-llvm-133496.txt>

Thanks,

Justin Holewinski

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From aggarwa4 at illinois.edu  Tue Jun 21 20:03:49 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Wed, 22 Jun 2011 01:03:49 -0000
Subject: [llvm-commits] [poolalloc] r133592 -
	/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
Message-ID: <20110622010349.63B022A6C12C@llvm.org>

Author: aggarwa4
Date: Tue Jun 21 20:03:49 2011
New Revision: 133592

URL: http://llvm.org/viewvc/llvm-project?rev=133592&view=rev
Log:
If we do not know where a va_list came from, do not
insert checks.

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133592&r1=133591&r2=133592&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue Jun 21 20:03:49 2011
@@ -495,6 +495,13 @@
         }
       }
 
+      if(CounterMap.find(CI->getOperand(VAListArgNum)->stripPointerCasts()) == CounterMap.end()) {
+        // If this is a va_list we do not know about,
+        // do not insert checks.
+
+        // FIXME: Handle cases where va_list is stored in memory
+         continue;
+      }
       Function::arg_iterator NII = F->arg_begin();
       std::vector<Value *>Args;
       Args.push_back(NII++); // total count
@@ -517,150 +524,162 @@
   }
 }
 
-  bool TypeChecks::visitVAListFunction(Module &M, Function &F_orig) {
-    if(!F_orig.hasInternalLinkage())
-      return false;
+bool TypeChecks::visitVAListFunction(Module &M, Function &F_orig) {
+  if(!F_orig.hasInternalLinkage())
+    return false;
 
-    int VAListArgNum = 0;
-    // Check if one of the arguments is a va_list
-    const Type *ListType  = M.getTypeByName("struct.__va_list_tag");
-    if(!ListType)
-      return false;
-    const Type *ListPtrType = ListType->getPointerTo();
-    Argument *VAListArg = NULL; 
-    for (Function::arg_iterator I = F_orig.arg_begin(); 
-         I != F_orig.arg_end(); ++I) {
-      VAListArgNum ++;
-      if(I->getType() == ListPtrType) {
-        VAListArg = I;
-        break;
-      }
-    }
-
-    // Clone the function to add arguments for count, MD
-
-    // 1. Create the new argument types vector
-    std::vector<const Type*>TP;
-    TP.push_back(Int64Ty); // for count
-    TP.push_back(Int64Ty); // for count
-    TP.push_back(VoidPtrTy); // for MD
-    for (Function::arg_iterator I = F_orig.arg_begin();
-         I != F_orig.arg_end(); ++I) {
-      TP.push_back(I->getType());
-    }
-    // 2. Create the new function prototype
-    const FunctionType *NewFTy = FunctionType::get(F_orig.getReturnType(),
-                                                   TP,/*argument types*/
-                                                   false);/*vararg*/
-    Function *F = Function::Create(NewFTy,
-                                   GlobalValue::InternalLinkage,
-                                   F_orig.getNameStr() + ".INT",
-                                   &M);
-
-    // 3. Set the mapping for args
-    Function::arg_iterator NI = F->arg_begin();
-    DenseMap<const Value*, Value*> ValueMap;
-    NI->setName("TotalCount");
-    NI++;
-    NI->setName("CurrentCount");
-    NI++;
-    NI->setName("MD");
-    NI++;
-    for (Function::arg_iterator II = F_orig.arg_begin(); 
-         NI != F->arg_end(); ++II, ++NI) {
-      // Each new argument maps to the argument in the old function
-      // For these arguments, also copy over the attributes
-      ValueMap[II] = NI;
-      NI->setName(II->getName());
-      NI->addAttr(F_orig.getAttributes()
-                  .getParamAttributes(II->getArgNo() + 1));
-    }
-
-    // 4. Copy over the attributes for the function.
-    F->setAttributes(F->getAttributes()
-                     .addAttr(0, F_orig.getAttributes().getRetAttributes()));
-    F->setAttributes(F->getAttributes()
-                     .addAttr(~0, F_orig.getAttributes().getFnAttributes()));
-
-    // 5. Perform the cloning.
-    SmallVector<ReturnInst*,100> Returns;
-    CloneFunctionInto(F, &F_orig, ValueMap, Returns);
-
-    VAListFunctionsMap[&F_orig] =  F;
-    inst_iterator InsPt = inst_begin(F);
-
-
-    // Store the information
-    Function::arg_iterator NII = F->arg_begin();
-    AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt);
-    new StoreInst(NII, VASizeLoc, &*InsPt);
-    NII++;
-    AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt);
-    new StoreInst(NII, Counter, &*InsPt); 
-    errs() << F->getNameStr() <<"\n";
-    NII++;
-    AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt);
-    new StoreInst(NII, VAMDLoc, &*InsPt);
-
-    CounterMap[ValueMap[VAListArg]] = Counter;
-    // Find all va_copy calls
-    for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
-      for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;I++) {
-        CallInst *CI = dyn_cast<CallInst>(I);
-        if(!CI)
-          continue;
-        Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
-        if(!CalledF)
-          continue;
-        if(!CalledF->isIntrinsic())
-          continue;
-        if(CalledF->getIntrinsicID() != Intrinsic::vacopy) 
-          continue;
-        // Reinitialize the counter
-        AllocaInst *CounterDest = new AllocaInst(Int64Ty, "",&*InsPt);
-        Value *CounterSource = CounterMap[CI->getOperand(2)->stripPointerCasts()];
-        LoadInst *CurrentValue = new LoadInst(CounterSource, "count", CI);
-        new StoreInst(CurrentValue, CounterDest, CI);
-        CounterMap[CI->getOperand(1)->stripPointerCasts()] = CounterDest;
-      }
+  int VAListArgNum = 0;
+  // Check if one of the arguments is a va_list
+  const Type *ListType  = M.getTypeByName("struct.__va_list_tag");
+  if(!ListType)
+    return false;
+  const Type *ListPtrType = ListType->getPointerTo();
+  Argument *VAListArg = NULL; 
+  for (Function::arg_iterator I = F_orig.arg_begin(); 
+       I != F_orig.arg_end(); ++I) {
+    VAListArgNum ++;
+    if(I->getType() == ListPtrType) {
+      VAListArg = I;
+      break;
     }
+  }
 
+  // Clone the function to add arguments for count, MD
 
-    // instrument va_arg to increment the counter
-    for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
-      for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
-        VAArgInst *VI = dyn_cast<VAArgInst>(I++);
-        if(!VI)
-          continue;
-        Constant *One = ConstantInt::get(Int64Ty, 1);
-        VI->getOperand(0)->stripPointerCasts()->dump();
-        Value *CounterSrc = CounterMap[VI->getOperand(0)->stripPointerCasts()];
-        CounterSrc->dump();
-        LoadInst *OldValue = new LoadInst(CounterSrc, "count", VI);
-        Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add,
-                                                       OldValue,
-                                                       One,
-                                                       "count",
-                                                       VI);
-        new StoreInst(NewValue, CounterSrc, VI);
-        std::vector<Value *> Args;
-        Instruction *VASize = new LoadInst(VASizeLoc, "", VI);
-        Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI);
-        Args.push_back(VASize);
-        Args.push_back(OldValue);
-        Args.push_back(getTypeMarkerConstant(VI));
-        Args.push_back(VAMetaData);
-        Args.push_back(getTagCounter());
-        CallInst::Create(compareTypeAndNumber,
-                         Args.begin(),
-                         Args.end(),
-                         "", VI);
+  // 1. Create the new argument types vector
+  std::vector<const Type*>TP;
+  TP.push_back(Int64Ty); // for count
+  TP.push_back(Int64Ty); // for count
+  TP.push_back(VoidPtrTy); // for MD
+  for (Function::arg_iterator I = F_orig.arg_begin();
+       I != F_orig.arg_end(); ++I) {
+    TP.push_back(I->getType());
+  }
+  // 2. Create the new function prototype
+  const FunctionType *NewFTy = FunctionType::get(F_orig.getReturnType(),
+                                                 TP,/*argument types*/
+                                                 false);/*vararg*/
+  Function *F = Function::Create(NewFTy,
+                                 GlobalValue::InternalLinkage,
+                                 F_orig.getNameStr() + ".INT",
+                                 &M);
+
+  // 3. Set the mapping for args
+  Function::arg_iterator NI = F->arg_begin();
+  DenseMap<const Value*, Value*> ValueMap;
+  NI->setName("TotalCount");
+  NI++;
+  NI->setName("CurrentCount");
+  NI++;
+  NI->setName("MD");
+  NI++;
+  for (Function::arg_iterator II = F_orig.arg_begin(); 
+       NI != F->arg_end(); ++II, ++NI) {
+    // Each new argument maps to the argument in the old function
+    // For these arguments, also copy over the attributes
+    ValueMap[II] = NI;
+    NI->setName(II->getName());
+    NI->addAttr(F_orig.getAttributes()
+                .getParamAttributes(II->getArgNo() + 1));
+  }
+
+  // 4. Copy over the attributes for the function.
+  F->setAttributes(F->getAttributes()
+                   .addAttr(0, F_orig.getAttributes().getRetAttributes()));
+  F->setAttributes(F->getAttributes()
+                   .addAttr(~0, F_orig.getAttributes().getFnAttributes()));
+
+  // 5. Perform the cloning.
+  SmallVector<ReturnInst*,100> Returns;
+  CloneFunctionInto(F, &F_orig, ValueMap, Returns);
+
+  VAListFunctionsMap[&F_orig] =  F;
+  inst_iterator InsPt = inst_begin(F);
+
+
+  // Store the information
+  Function::arg_iterator NII = F->arg_begin();
+  AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt);
+  new StoreInst(NII, VASizeLoc, &*InsPt);
+  NII++;
+  AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt);
+  new StoreInst(NII, Counter, &*InsPt); 
+  errs() << F->getNameStr() <<"\n";
+  NII++;
+  AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt);
+  new StoreInst(NII, VAMDLoc, &*InsPt);
+
+  CounterMap[ValueMap[VAListArg]] = Counter;
+  // Find all va_copy calls
+  for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
+    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;I++) {
+      CallInst *CI = dyn_cast<CallInst>(I);
+      if(!CI)
+        continue;
+      Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
+      if(!CalledF)
+        continue;
+      if(!CalledF->isIntrinsic())
+        continue;
+      if(CalledF->getIntrinsicID() != Intrinsic::vacopy) 
+        continue;
+      if(CounterMap.find(CI->getOperand(2)->stripPointerCasts()) == CounterMap.end()) {
+        // If this is a va_list we do not know about,
+        // do not insert checks.
+
+        // FIXME: Handle cases where va_list is stored in memory
+         continue;
       }
+      // Reinitialize the counter
+      AllocaInst *CounterDest = new AllocaInst(Int64Ty, "",&*InsPt);
+      Value *CounterSource = CounterMap[CI->getOperand(2)->stripPointerCasts()];
+      LoadInst *CurrentValue = new LoadInst(CounterSource, "count", CI);
+      new StoreInst(CurrentValue, CounterDest, CI);
+      CounterMap[CI->getOperand(1)->stripPointerCasts()] = CounterDest;
     }
+  }
 
-    return true;
+
+  // instrument va_arg to increment the counter
+  for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
+    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
+      VAArgInst *VI = dyn_cast<VAArgInst>(I++);
+      if(!VI)
+        continue;
+      if(CounterMap.find(VI->getOperand(0)->stripPointerCasts()) == CounterMap.end()) {
+        // If this is a va_list we do not know about,
+        // do not insert checks.
+
+        // FIXME: Handle cases where va_list is stored in memory
+         continue;
+      }
+      Constant *One = ConstantInt::get(Int64Ty, 1);
+      Value *CounterSrc = CounterMap[VI->getOperand(0)->stripPointerCasts()];
+      LoadInst *OldValue = new LoadInst(CounterSrc, "count", VI);
+      Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add,
+                                                     OldValue,
+                                                     One,
+                                                     "count",
+                                                     VI);
+      new StoreInst(NewValue, CounterSrc, VI);
+      std::vector<Value *> Args;
+      Instruction *VASize = new LoadInst(VASizeLoc, "", VI);
+      Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI);
+      Args.push_back(VASize);
+      Args.push_back(OldValue);
+      Args.push_back(getTypeMarkerConstant(VI));
+      Args.push_back(VAMetaData);
+      Args.push_back(getTagCounter());
+      CallInst::Create(compareTypeAndNumber,
+                       Args.begin(),
+                       Args.end(),
+                       "", VI);
+    }
   }
 
+  return true;
+}
+
 bool TypeChecks::visitAddressTakenFunction(Module &M, Function &F) {
   // Clone function
   // 1. Create the new argument types vector
@@ -915,6 +934,13 @@
       VAArgInst *VI = dyn_cast<VAArgInst>(I++);
       if(!VI)
         continue;
+      if(CounterMap.find(VI->getOperand(0)->stripPointerCasts()) == CounterMap.end()) {
+        // If this is a va_list we do not know about,
+        // do not insert checks.
+
+        // FIXME: Handle cases where va_list is stored in memory
+         continue;
+      }
       Constant *One = ConstantInt::get(Int64Ty, 1);
       Value *CounterSrc = CounterMap[VI->getOperand(0)->stripPointerCasts()];
       LoadInst *OldValue = new LoadInst(CounterSrc, "count", VI);



From jstaszak at apple.com  Tue Jun 21 20:10:59 2011
From: jstaszak at apple.com (Jakub Staszak)
Date: Tue, 21 Jun 2011 18:10:59 -0700
Subject: [llvm-commits] BlockFrequency for BasicBlocks
In-Reply-To: <F4C43975-C8E4-421F-84C0-39D23AACD036@apple.com>
References: <1E9CE6F5-A2AC-4A81-A001-D19DAB65255B@apple.com>
	<AB959C12-7AF3-4155-AC19-CA8F6116F710@apple.com>
	<E8A0D181-3AF7-4B5B-AA36-B210B721BAB4@apple.com>
	<F4C43975-C8E4-421F-84C0-39D23AACD036@apple.com>
Message-ID: <98818310-FEB0-4E4D-8B38-E14698BFD9BE@apple.com>

The new version attached. OK to commit now?

On Jun 17, 2011, at 4:10 PM, Andrew Trick wrote:

> Hi Kuba,
> 
> If you define the constructor and destructor in the .cpp, then do you still need to include InitializePasses.h from BlockFrequency.h.
Done, i also removed "LoopInfo.h"

> And do you really need a "deinit" method?
Yes, if I try to delete BFI in destructor I get a warning ("note: neither the destructor nor the class-specific operator delete will be called, even if they are declared when the class is defined.").

> The block frequency pass should only require a *single* CFG graph traversal. I'm not sure how to do that with LLVM's current rpot/pot iterators. Ideally, LLVM would have a DFSOrder analysis to order the blocks. That ordering will remain valid until some CFG transform.
I removed PO vector, so we have one RPO and one PO traversal now.

> For, now I think you can at least limit it to two traversals (one reverse postorder and one postorder) and add a FIXME so we remember to fold it into one traversal later. Subsequently whenever you need to visit blocks in RPO/PO order, just use the RPO/PO vectors directly.
> 
> Can you also comment that LoopSimplify can make the algorithm converge faster.
Done.

> Can frequency reach zero in divBlockFreq? Don't you want to saturate at 1?
I think it can, so i jest set it to 1/START_FREQ.

- Kuba
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From justin.holewinski at gmail.com  Tue Jun 21 21:09:50 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Wed, 22 Jun 2011 02:09:50 -0000
Subject: [llvm-commits] [llvm] r133599 - in /llvm/trunk:
 lib/Target/PTX/PTXInstrInfo.td test/CodeGen/PTX/setp.ll
Message-ID: <20110622020950.91E432A6C12C@llvm.org>

Author: jholewinski
Date: Tue Jun 21 21:09:50 2011
New Revision: 133599

URL: http://llvm.org/viewvc/llvm-project?rev=133599&view=rev
Log:
PTX: Add signed integer comparisons

Modified:
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
    llvm/trunk/test/CodeGen/PTX/setp.ll

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=133599&r1=133598&r2=133599&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Tue Jun 21 21:09:50 2011
@@ -696,6 +696,10 @@
 defm SETPLEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULE, "le">;
 defm SETPGTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGT, "gt">;
 defm SETPGEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETUGE, "ge">;
+defm SETPLTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLT,  "lt">;
+defm SETPLEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETLE,  "le">;
+defm SETPGTs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGT,  "gt">;
+defm SETPGEs16 : PTX_SETP_I<RegI16, "s16", i16imm, SETGE,  "ge">;
 
 // Compare u32
 
@@ -705,6 +709,10 @@
 defm SETPLEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULE, "le">;
 defm SETPGTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGT, "gt">;
 defm SETPGEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETUGE, "ge">;
+defm SETPLTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLT,  "lt">;
+defm SETPLEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETLE,  "le">;
+defm SETPGTs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGT,  "gt">;
+defm SETPGEs32 : PTX_SETP_I<RegI32, "s32", i32imm, SETGE,  "ge">;
 
 // Compare u64
 
@@ -714,6 +722,10 @@
 defm SETPLEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULE, "le">;
 defm SETPGTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGT, "gt">;
 defm SETPGEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETUGE, "ge">;
+defm SETPLTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLT,  "lt">;
+defm SETPLEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETLE,  "le">;
+defm SETPGTs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGT,  "gt">;
+defm SETPGEs64 : PTX_SETP_I<RegI64, "s64", i64imm, SETGE,  "ge">;
 
 // Compare f32
 

Modified: llvm/trunk/test/CodeGen/PTX/setp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/setp.ll?rev=133599&r1=133598&r2=133599&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/setp.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/setp.ll Tue Jun 21 21:09:50 2011
@@ -54,6 +54,42 @@
 	ret i32 %z
 }
 
+define ptx_device i32 @test_setp_lt_s32_rr(i32 %x, i32 %y) {
+; CHECK: setp.lt.s32 p0, r1, r2;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
+	%p = icmp slt i32 %x, %y
+	%z = zext i1 %p to i32
+	ret i32 %z
+}
+
+define ptx_device i32 @test_setp_le_s32_rr(i32 %x, i32 %y) {
+; CHECK: setp.le.s32 p0, r1, r2;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
+	%p = icmp sle i32 %x, %y
+	%z = zext i1 %p to i32
+	ret i32 %z
+}
+
+define ptx_device i32 @test_setp_gt_s32_rr(i32 %x, i32 %y) {
+; CHECK: setp.gt.s32 p0, r1, r2;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
+	%p = icmp sgt i32 %x, %y
+	%z = zext i1 %p to i32
+	ret i32 %z
+}
+
+define ptx_device i32 @test_setp_ge_s32_rr(i32 %x, i32 %y) {
+; CHECK: setp.ge.s32 p0, r1, r2;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
+	%p = icmp sge i32 %x, %y
+	%z = zext i1 %p to i32
+	ret i32 %z
+}
+
 define ptx_device i32 @test_setp_eq_u32_ri(i32 %x) {
 ; CHECK: setp.eq.u32 p0, r1, 1;
 ; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
@@ -108,6 +144,42 @@
 	ret i32 %z
 }
 
+define ptx_device i32 @test_setp_lt_s32_ri(i32 %x) {
+; CHECK: setp.lt.s32 p0, r1, 1;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
+	%p = icmp slt i32 %x, 1
+	%z = zext i1 %p to i32
+	ret i32 %z
+}
+
+define ptx_device i32 @test_setp_le_s32_ri(i32 %x) {
+; CHECK: setp.lt.s32 p0, r1, 2;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
+	%p = icmp sle i32 %x, 1
+	%z = zext i1 %p to i32
+	ret i32 %z
+}
+
+define ptx_device i32 @test_setp_gt_s32_ri(i32 %x) {
+; CHECK: setp.gt.s32 p0, r1, 1;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
+	%p = icmp sgt i32 %x, 1
+	%z = zext i1 %p to i32
+	ret i32 %z
+}
+
+define ptx_device i32 @test_setp_ge_s32_ri(i32 %x) {
+; CHECK: setp.gt.s32 p0, r1, 0;
+; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK-NEXT: ret;
+	%p = icmp sge i32 %x, 1
+	%z = zext i1 %p to i32
+	ret i32 %z
+}
+
 define ptx_device i32 @test_setp_4_op_format_1(i32 %x, i32 %y, i32 %u, i32 %v) {
 ; CHECK: setp.gt.u32 p0, r3, r4;
 ; CHECK-NEXT: setp.eq.and.u32 p0, r1, r2, p0;



From atrick at apple.com  Tue Jun 21 22:21:08 2011
From: atrick at apple.com (Andrew Trick)
Date: Tue, 21 Jun 2011 20:21:08 -0700
Subject: [llvm-commits] BlockFrequency for BasicBlocks
In-Reply-To: <98818310-FEB0-4E4D-8B38-E14698BFD9BE@apple.com>
References: <1E9CE6F5-A2AC-4A81-A001-D19DAB65255B@apple.com>
	<AB959C12-7AF3-4155-AC19-CA8F6116F710@apple.com>
	<E8A0D181-3AF7-4B5B-AA36-B210B721BAB4@apple.com>
	<F4C43975-C8E4-421F-84C0-39D23AACD036@apple.com>
	<98818310-FEB0-4E4D-8B38-E14698BFD9BE@apple.com>
Message-ID: <F378E692-08B3-4762-A96E-D74CAE11B44D@apple.com>

On Jun 21, 2011, at 6:10 PM, Jakub Staszak wrote:

> The new version attached. OK to commit now?
> 
> On Jun 17, 2011, at 4:10 PM, Andrew Trick wrote:
> 
>> Hi Kuba,
>> 
>> If you define the constructor and destructor in the .cpp, then do you still need to include InitializePasses.h from BlockFrequency.h.
> Done, i also removed "LoopInfo.h"
> 
>> And do you really need a "deinit" method?
> Yes, if I try to delete BFI in destructor I get a warning ("note: neither the destructor nor the class-specific operator delete will be called, even if they are declared when the class is defined.").

I'm unclear why you have the ctor/dtor defined in the header. Try moving them to the .cpp.
> 
>> The block frequency pass should only require a *single* CFG graph traversal. I'm not sure how to do that with LLVM's current rpot/pot iterators. Ideally, LLVM would have a DFSOrder analysis to order the blocks. That ordering will remain valid until some CFG transform.
> I removed PO vector, so we have one RPO and one PO traversal now.
> 
>> For, now I think you can at least limit it to two traversals (one reverse postorder and one postorder) and add a FIXME so we remember to fold it into one traversal later. Subsequently whenever you need to visit blocks in RPO/PO order, just use the RPO/PO vectors directly.
>> 
>> Can you also comment that LoopSimplify can make the algorithm converge faster.
> Done.
> 
>> Can frequency reach zero in divBlockFreq? Don't you want to saturate at 1?
> I think it can, so i jest set it to 1/START_FREQ.

Yes, by "1" I meant literal 1, not scaled 1. I think this could happen inside getEdgeFreq() when (N * getBlockFreq(Src)) < D. You should probably check for that case and return the smallest nonzero frequency.

You actually shouldn't have a problem in divBlockFreq, but somewhere you should assert that the input BranchProbability is well-formed (N < D).

-Andy


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From rafael.espindola at gmail.com  Tue Jun 21 23:01:59 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 22 Jun 2011 04:01:59 -0000
Subject: [llvm-commits] [llvm] r133607 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
Message-ID: <20110622040159.1F7682A6C12C@llvm.org>

Author: rafael
Date: Tue Jun 21 23:01:58 2011
New Revision: 133607

URL: http://llvm.org/viewvc/llvm-project?rev=133607&view=rev
Log:
Reenable the optimization added in 133415, but change the definition of a "simple" bb to
be one with only one unconditional branch and no phis. Duplicating the phis in this case
is possible, but requeres liveness analysis or breaking edges.

Modified:
    llvm/trunk/lib/CodeGen/TailDuplication.cpp

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133607&r1=133606&r2=133607&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Tue Jun 21 23:01:58 2011
@@ -568,9 +568,9 @@
 TailDuplicatePass::isSimpleBB(MachineBasicBlock *TailBB) {
   if (TailBB->succ_size() != 1)
     return false;
-  MachineBasicBlock::iterator I = TailBB->getFirstNonPHI();
+  MachineBasicBlock::iterator I = TailBB->begin();
   MachineBasicBlock::iterator E = TailBB->end();
-  while (I->isDebugValue() && I != E)
+  while (I != E && I->isDebugValue())
     ++I;
   if (I == E)
     return true;
@@ -712,7 +712,7 @@
   DenseSet<unsigned> UsedByPhi;
   getRegsUsedByPHIs(*TailBB, &UsedByPhi);
 
-  if (0 && isSimpleBB(TailBB))
+  if (isSimpleBB(TailBB))
     return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
 
   // Iterate through all the unique predecessors and tail-duplicate this



From atrick at apple.com  Wed Jun 22 00:43:36 2011
From: atrick at apple.com (Andrew Trick)
Date: Wed, 22 Jun 2011 05:43:36 -0000
Subject: [llvm-commits] [llvm] r133608 - /llvm/trunk/test/CMakeLists.txt
Message-ID: <20110622054336.66E7B2A6C12C@llvm.org>

Author: atrick
Date: Wed Jun 22 00:43:36 2011
New Revision: 133608

URL: http://llvm.org/viewvc/llvm-project?rev=133608&view=rev
Log:
Only do config-time substitution of LLVM_BUILD_MODE in
test/lit.site.cfg, not Unit/test/lit.site.cfg.

Modified:
    llvm/trunk/test/CMakeLists.txt

Modified: llvm/trunk/test/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CMakeLists.txt?rev=133608&r1=133607&r2=133608&view=diff
==============================================================================
--- llvm/trunk/test/CMakeLists.txt (original)
+++ llvm/trunk/test/CMakeLists.txt Wed Jun 22 00:43:36 2011
@@ -71,8 +71,6 @@
   MAKE_DIRECTORY(${CMAKE_CURRENT_BINARY_DIR}/Unit)
 
   # Configuration-time: See Unit/lit.site.cfg.in
-  set(LLVM_BUILD_MODE "${LLVM_BUILD_MODE}")
-
   set(LLVM_SOURCE_DIR ${LLVM_MAIN_SRC_DIR})
   set(LLVM_BINARY_DIR ${LLVM_BINARY_DIR})
   set(LLVM_TOOLS_DIR "${LLVM_TOOLS_BINARY_DIR}/%(build_config)s")
@@ -81,10 +79,17 @@
   set(ENABLE_SHARED ${LLVM_SHARED_LIBS_ENABLED})
   set(SHLIBPATH_VAR ${SHLIBPATH_VAR})
 
+  # lit.site.cfg uses the config-time build mode
+  set(LLVM_BUILD_MODE "${LLVM_BUILD_MODE}")
+
   configure_file(
     ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in
     ${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg
     @ONLY)
+
+  # Unit/lit.site.cfg substitutes the runtime build_mode
+  set(LLVM_BUILD_MODE "%(build_mode)s")
+
   configure_file(
     ${CMAKE_CURRENT_SOURCE_DIR}/Unit/lit.site.cfg.in
     ${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg



From raghesh.a at gmail.com  Wed Jun 22 02:25:12 2011
From: raghesh.a at gmail.com (raghesh)
Date: Wed, 22 Jun 2011 12:55:12 +0530
Subject: [llvm-commits] [polly] r133354 -
	/polly/trunk/www/documentation/memaccess.html
In-Reply-To: <4E012B54.3090403@grosser.es>
References: <20110618171716.444342A6C12C@llvm.org>
	<4E012B54.3090403@grosser.es>
Message-ID: <BANLkTim-dx90NTCw9Q64rw5i5rO+RGJyQA@mail.gmail.com>

Thanks a lot for the comments. In fact I didn't even look inside the
html source. That was a big mistake. I created it using iceape
composer. I will address these comments soon.

Regards,

On Wed, Jun 22, 2011 at 5:07 AM, Tobias Grosser <tobias at grosser.es> wrote:
> On 06/18/2011 02:17 PM, Raghesh Aloor wrote:
>>
>> Author: raghesh
>> Date: Sat Jun 18 12:17:16 2011
>> New Revision: 133354
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=133354&view=rev
>> Log:
>> www: Adding webpage to track memory access transformation
>
> Hi Raghesh,
>
> thanks for your work. I still have some comments:
>
> You forgot to add the disclaimer that this is a work in progress project.
> Furthermore, the HTML you used is pretty noisy (details inline). The next
> time we should review it before committing.
>
>> Added:
>> ? ? polly/trunk/www/documentation/memaccess.html
>>
>> Added: polly/trunk/www/documentation/memaccess.html
>> URL:
>> http://llvm.org/viewvc/llvm-project/polly/trunk/www/documentation/memaccess.html?rev=133354&view=auto
>>
>> ==============================================================================
>> --- polly/trunk/www/documentation/memaccess.html (added)
>> +++ polly/trunk/www/documentation/memaccess.html Sat Jun 18 12:17:16 2011
>> @@ -0,0 +1,143 @@
>> +<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
>> +<html>
>> +<head>
>> +<meta content="text/html; charset=ISO-8859-1"
>> + http-equiv="Content-Type">
>> +<title>memaccess.html</title>
>
> Can you use a title like 'Polly - Memory access optimizations'
> You should include menu.css and content.css
>
> I propose to just use the header from documention/passes.html as a template.
> (This is true for most of the comments I give)
>
>
> <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
> ? ? ? ? ?"http://www.w3.org/TR/html4/strict.dtd">
> <!-- Material used from: HTML 4.01 specs: http://www.w3.org/TR/html401/ -->
> <html>
> <head>
> ?<META http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
> ?<title>Polly - The available LLVM passes</title>
> ?<link type="text/css" rel="stylesheet" href="../menu.css">
> ?<link type="text/css" rel="stylesheet" href="../content.css">
> </head>
>
>> +</head>
>> +<body>
>
> You miss the line to include the menu.
> <!--#include virtual="../menu.html.incl"-->
>
>> +<div style="margin-left: 320px;"><small style="font-weight:
>> bold;"><small><a><big><big><big>Support
>
> Just create a large div with id="content" that includes the whole content of
> this page.
>
>> +for
>> +memory access
>> +transformations in Polly</big></big></big></a></small></small><big><span
>> + style="font-weight: bold;"></span></big><br>
>
> Use <h1> for the header. All the other tags are just noise and disallow a
> consistent design.
>
>> +<big><span style="font-weight: bold;"></span></big><br>
>
> Useless noise.
>
>> +<div style="text-align: left;">
>
> This does not seem to be needed.
>
>> +<strong></strong>
>
> Useless noise.
>
>
>> +This project adds
>> +memory access transformations to Polly. In many cases<br>
>
> <br> Not needed.
>
>> +changing the memory access pattern yields to better data
>> +locality or removes<br>
>
> <br> not needed.
>
>> +dependences that would otherwise block
>> +transformations. They may also<br>
>
> ? ? ? ? ? ? ? ? ?. Memory access transformations may also ...
>
> <br> not needed
>
>> +allow LLVM to use registers to store
>> +certain values.<br>
>
> <br> not needed
>
>> +</div>
>> +<br>
>
> <br> not needed.
>
>> +An examples which uses this feature is given below<br>
>
> This seems to be a new paragraph. Put it in a <p></p> to get the newlines.
>
>> +</div>
>> +<div style="margin-left: 320px;"><br>
>
> I do not see a reason for this <div>
>
>> +Consider the following loop
>> +<ul>
>> +<ul>
>> +</ul>
>> +</ul>
>
> Useless noise.
>
>> +<div style="margin-left: 40px;"><small style="font-style: italic;">
>
> Just use <pre> to format the code.
>
>> + for
>> +(i = 0; i&lt; 8; i++)</small><br>
>> +<small style="font-style: italic;">sum += A[i];</small><br
>> + style="font-style: italic;">
>
> All this formatting and <br> not needed.
>
>> +</div>
>> +<br>
>> +With support for memory access transformation this loop can be
>> executed<br>
>> +in parallel. It can be
>> +transformed to
>
>> +<small style="font-style: italic;"><br>
>>
>> +<br>
>> +</small>
>
> Useless noise.
>
>> +<div style="margin-left: 40px;">
>
> <div> not needed.
>
>> +<small style="font-style: italic;">&lt;create
>>
>> +and
>> +initialize an array 'tmp'
>> +with size 4&gt;</small><br>
>> +<small style="font-style: italic;">for (i = 0; i&lt; 8; i++)
>> {</small><br>
>> +<small style="font-style: italic;">tmp[i % 4] += A[i];</small><br>
>> +<small style="font-style: italic;">}</small><small><span
>> + style="font-style: italic;"></span></small><br>
>> +<small><span style="font-style: italic;">sum = tmp[0] + tmp[1] + tmp[2]
>> ++ tmp[3];</span></small><br>
>
> All formatting not needed. Just use a big <pre> block.
>
>> +</div>
>> +<br>
>> +With the help of some optimizer (like
>> +PluTo) the following code can be<br>
>
> <br> not needed.
>
> "With the help of optimizers like PluTo the following
>
>> +generated, where the outer loop is
>> +parallel.
>> +<p style="padding-left: 30px; font-style: italic;"><small>parfor (ii =
>> +0; ii&lt; 4; ii++) {<br>
>> +&nbsp;&nbsp; tmp[ii] = 0;<br>
>> +&nbsp;&nbsp;&nbsp; for (i = ii * 2; i&lt; (ii+1) * 2; i++)<br>
>> +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; tmp[ii] += A[i];</small></p>
>> +<p style="padding-left: 30px; font-style: italic; font-weight:
>> bold;"><small><span
>> + style="font-weight: normal;">}</span><br style="font-weight: normal;">
>> +<span style="font-weight: normal;">sum = tmp[0] + tmp[1] + tmp[2] +
>> +tmp[3];</span><br>
>> +<strong></strong></small></p>
>
> Useless style noise. Just use <pre>
>
>> +<p><strong><span style="text-decoration: underline;">TODO<br>
>> +</span></strong></p>
>
> Do not use <strong><span><p> here. Just use <h2>
>
>> +<p><strong><span style="text-decoration: underline;"><small>Step
>> 1</small><br>
>> +</span></strong></p>
>
> Just use <h3>
>
>> +Polly exports its polyhedral description in a JSCoP file. Define how
>> +memory
>
>> +<small><br>
>>
>> +</small>
>
> Useless noise. <br> not needed.
>
>> +layout transformations are going to be expressed in Polly and
>> +in
>> +the JSCOP file.<br>
>
>> +A simple example is given below.<br>
>> +<br>
>> +Consider the following loop.<br>
>> +<br>
>
> <br> not needed. Use <p> to mark a paragraph.
>
>> +<div style="margin-left: 40px;"><small><span style="font-style:
>> italic;">for
>> +(i
>> += 0; i&lt; 12; i++)</span><br style="font-style: italic;">
>> +<span style="font-style: italic;">&nbsp;&nbsp;&nbsp;&nbsp; A[i] =
>> 0;</span><br
>> + style="font-style: italic;">
>> +</small></div>
>
> Useless style noise. Just use <pre>.
>
>> +<br>
>> +In the JSCOP file the memory is represented as follows.<br>
>> +<br>
>> +<div style="margin-left: 40px;"><small><span style="font-style:
>> italic;">&nbsp;&nbsp;
>> +"accesses":
>> +[{</span></small><br style="font-style: italic;">
>> +<small><span style="font-style:
>> italic;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
>> +"kind":
>> +"write",</span></small><br style="font-style: italic;">
>> +<small><span style="font-style:
>> italic;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
>> +"relation":
>> +"{
>> +Stmt[i] -&gt;</span><strong
>> + style="font-style: italic; font-weight: bold;">A</strong><span
>> + style="font-style: italic;"><span style="font-weight: bold;">[i]</span>
>> +}"</span></small><br style="font-style: italic;">
>> +<small><span style="font-style: italic;">&nbsp;&nbsp;&nbsp;
>> }]</span></small><br
>> + style="font-style: italic;">
>> +</div>
>
> Useless style noise and &nbsp;. Just use <pre>
>
>> +<br>
>> +Suppose
>> +we want to perform a transformation such that the following<br>
>> +code is generated<br>
>> +<br>
>
> Get rid of <br> and use a single <p>.
>
>> +<div style="margin-left: 40px;"><small><span style="font-style:
>> italic;">for
>> +(i
>> += 0; i&lt; 12; i++)</span><br style="font-style: italic;">
>> +<span style="font-style: italic;">
>> +&nbsp;&nbsp;&nbsp;&nbsp; A[0] = i;</span><br style="font-style: italic;">
>> +</small></div>
>
> Style noise. Use <pre>.
>
>> +<br>
>> +The corresponding JSCOP file represenation would be<br>
>> +<br>
>> +<div style="margin-left: 40px;"><small><span style="font-style:
>> italic;">&nbsp;&nbsp;&nbsp;
>> +"accesses":
>> +[{</span><br style="font-style: italic;">
>> +<span style="font-style:
>> italic;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
>> +"kind":
>> +"read",</span><br style="font-style: italic;">
>> +<span style="font-style:
>> italic;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
>
> Style and &nbsp; noise. Just use <pre>.
>
>> +"relation":
>> +"{
>> +Stmt[i] -&gt;</span><strong
>> + style="font-style: italic; font-weight: bold;">A</strong><span
>
> Please don't use any inline style specifiers. If you want to highlight
> something use <em> or <b>. For anything else define a new style in the .css
> files after verifying something similar is not available.
>
>> + style="font-style: italic;"><span style="font-weight: bold;">[0]</span>
>> +}"</span><br style="font-style: italic;">
>> +<span style="font-style: italic;">&nbsp;&nbsp;&nbsp; }]</span><br
>> + style="font-style: italic;">
>> +</small></div>
>
> Style noise.
>
>> +<br>
>> +We need to detect this access function change.<br>
>> +</div>
>> +<span id="q_12f99e5de7fd0932_1" class="h4"></span>
>
> Is this needed for anything?
>
>> +</body>
>> +</html>
>
> Again, thanks for your work
> Tobi
>



-- 
Raghesh


From renato.golin at arm.com  Wed Jun 22 03:26:34 2011
From: renato.golin at arm.com (Renato Golin)
Date: Wed, 22 Jun 2011 09:26:34 +0100
Subject: [llvm-commits] patch: fix emission of npot vectors which need
 trailing padding
In-Reply-To: <BANLkTikxRPdVZp6eVYunfzN9GyMfE_T7o2_Wgbi1pVFEKFdacQ@mail.gmail.com>
References: <BANLkTinhSx1XZV_6kDR8e3U=YP4V1rQuXA@mail.gmail.com>
	<BANLkTikqZYc=LyAbboTr=xHO2adgD4OfMw@mail.gmail.com>
	<BANLkTikxRPdVZp6eVYunfzN9GyMfE_T7o2_Wgbi1pVFEKFdacQ@mail.gmail.com>
Message-ID: <BANLkTinhGxTkK1WgQwGQrd-ZHeTM6s5Rxg@mail.gmail.com>

On 22 June 2011 00:19, Nick Lewycky <nlewycky at google.com> wrote:
> Hi Renato! Sorry, but I don't understand your reply at all.

I think you did, and answered my question at the same time. ;)


> There's nothing ARM-specific about this change, which is why it belongs in
> generic CodeGen and shouldn't be in the ARMAsmPrinter.?It just so happens
> that <3 x float> on ARM provides a counter-example that would require this
> padding or trigger this assertion.

I was fooled by your comment on ARM's vector size and thought your
patch was in the wrong place. As you say (and Eli has shown), this is
not platform specific, so the patch is good.

Sorry about the confusion.

cheers,
--renato


From jay.foad at gmail.com  Wed Jun 22 03:50:07 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Wed, 22 Jun 2011 08:50:07 -0000
Subject: [llvm-commits] [llvm] r133611 - in /llvm/trunk:
 include/llvm/ADT/ArrayRef.h include/llvm/InlineAsm.h
 lib/VMCore/ConstantsContext.h lib/VMCore/LLVMContextImpl.h
Message-ID: <20110622085007.1A4BD2A6C12C@llvm.org>

Author: foad
Date: Wed Jun 22 03:50:06 2011
New Revision: 133611

URL: http://llvm.org/viewvc/llvm-project?rev=133611&view=rev
Log:
Extend ConstantUniqueMap with a new template parameter ValRefType,
representing a constant reference to ValType. Normally this is just
"const ValType &", but when ValType is a std::vector we want to use
ArrayRef as the reference type.

Modified:
    llvm/trunk/include/llvm/ADT/ArrayRef.h
    llvm/trunk/include/llvm/InlineAsm.h
    llvm/trunk/lib/VMCore/ConstantsContext.h
    llvm/trunk/lib/VMCore/LLVMContextImpl.h

Modified: llvm/trunk/include/llvm/ADT/ArrayRef.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/ADT/ArrayRef.h?rev=133611&r1=133610&r2=133611&view=diff
==============================================================================
--- llvm/trunk/include/llvm/ADT/ArrayRef.h (original)
+++ llvm/trunk/include/llvm/ADT/ArrayRef.h Wed Jun 22 03:50:06 2011
@@ -125,6 +125,13 @@
     }
     
     /// @}
+    /// @name Conversion operators
+    /// @{
+    operator std::vector<T>() const {
+      return std::vector<T>(Data, Data+Length);
+    }
+    
+    /// @}
   };
   
   // ArrayRefs can be treated like a POD type.

Modified: llvm/trunk/include/llvm/InlineAsm.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InlineAsm.h?rev=133611&r1=133610&r2=133611&view=diff
==============================================================================
--- llvm/trunk/include/llvm/InlineAsm.h (original)
+++ llvm/trunk/include/llvm/InlineAsm.h Wed Jun 22 03:50:06 2011
@@ -25,15 +25,16 @@
 class FunctionType;
 class Module;
 struct InlineAsmKeyType;
-template<class ValType, class TypeClass, class ConstantClass, bool HasLargeKey>
+template<class ValType, class ValRefType, class TypeClass, class ConstantClass,
+         bool HasLargeKey>
 class ConstantUniqueMap;
 template<class ConstantClass, class TypeClass, class ValType>
 struct ConstantCreator;
 
 class InlineAsm : public Value {
   friend struct ConstantCreator<InlineAsm, PointerType, InlineAsmKeyType>;
-  friend class ConstantUniqueMap<InlineAsmKeyType, PointerType, InlineAsm,
-                                 false>;
+  friend class ConstantUniqueMap<InlineAsmKeyType, const InlineAsmKeyType&,
+                                 PointerType, InlineAsm, false>;
 
   InlineAsm(const InlineAsm &);             // do not implement
   void operator=(const InlineAsm&);         // do not implement

Modified: llvm/trunk/lib/VMCore/ConstantsContext.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantsContext.h?rev=133611&r1=133610&r2=133611&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ConstantsContext.h (original)
+++ llvm/trunk/lib/VMCore/ConstantsContext.h Wed Jun 22 03:50:06 2011
@@ -568,7 +568,7 @@
   }
 };
 
-template<class ValType, class TypeClass, class ConstantClass,
+template<class ValType, class ValRefType, class TypeClass, class ConstantClass,
          bool HasLargeKey = false /*true for arrays and structs*/ >
 class ConstantUniqueMap : public AbstractTypeUser {
 public:
@@ -656,7 +656,7 @@
     }
   }
 
-  ConstantClass* Create(const TypeClass *Ty, const ValType &V,
+  ConstantClass* Create(const TypeClass *Ty, ValRefType V,
                         typename MapTy::iterator I) {
     ConstantClass* Result =
       ConstantCreator<ConstantClass,TypeClass,ValType>::create(Ty, V);
@@ -675,7 +675,7 @@
     
   /// getOrCreate - Return the specified constant from the map, creating it if
   /// necessary.
-  ConstantClass *getOrCreate(const TypeClass *Ty, const ValType &V) {
+  ConstantClass *getOrCreate(const TypeClass *Ty, ValRefType V) {
     MapKey Lookup(Ty, V);
     ConstantClass* Result = 0;
     

Modified: llvm/trunk/lib/VMCore/LLVMContextImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/LLVMContextImpl.h?rev=133611&r1=133610&r2=133611&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/LLVMContextImpl.h (original)
+++ llvm/trunk/lib/VMCore/LLVMContextImpl.h Wed Jun 22 03:50:06 2011
@@ -25,6 +25,7 @@
 #include "llvm/Support/ValueHandle.h"
 #include "llvm/ADT/APFloat.h"
 #include "llvm/ADT/APInt.h"
+#include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/FoldingSet.h"
 #include "llvm/ADT/SmallPtrSet.h"
@@ -138,27 +139,30 @@
   // on Context destruction.
   SmallPtrSet<MDNode*, 1> NonUniquedMDNodes;
   
-  ConstantUniqueMap<char, Type, ConstantAggregateZero> AggZeroConstants;
+  ConstantUniqueMap<char, char, Type, ConstantAggregateZero> AggZeroConstants;
 
-  typedef ConstantUniqueMap<std::vector<Constant*>, ArrayType,
-    ConstantArray, true /*largekey*/> ArrayConstantsTy;
+  typedef ConstantUniqueMap<std::vector<Constant*>, ArrayRef<Constant*>,
+    ArrayType, ConstantArray, true /*largekey*/> ArrayConstantsTy;
   ArrayConstantsTy ArrayConstants;
   
-  typedef ConstantUniqueMap<std::vector<Constant*>, StructType,
-    ConstantStruct, true /*largekey*/> StructConstantsTy;
+  typedef ConstantUniqueMap<std::vector<Constant*>, ArrayRef<Constant*>,
+    StructType, ConstantStruct, true /*largekey*/> StructConstantsTy;
   StructConstantsTy StructConstants;
   
-  typedef ConstantUniqueMap<std::vector<Constant*>, VectorType,
-                            ConstantVector> VectorConstantsTy;
+  typedef ConstantUniqueMap<std::vector<Constant*>, ArrayRef<Constant*>,
+                            VectorType, ConstantVector> VectorConstantsTy;
   VectorConstantsTy VectorConstants;
   
-  ConstantUniqueMap<char, PointerType, ConstantPointerNull> NullPtrConstants;
-  ConstantUniqueMap<char, Type, UndefValue> UndefValueConstants;
+  ConstantUniqueMap<char, char, PointerType, ConstantPointerNull>
+    NullPtrConstants;
+  ConstantUniqueMap<char, char, Type, UndefValue> UndefValueConstants;
   
   DenseMap<std::pair<Function*, BasicBlock*> , BlockAddress*> BlockAddresses;
-  ConstantUniqueMap<ExprMapKeyType, Type, ConstantExpr> ExprConstants;
+  ConstantUniqueMap<ExprMapKeyType, const ExprMapKeyType&, Type, ConstantExpr>
+    ExprConstants;
 
-  ConstantUniqueMap<InlineAsmKeyType, PointerType, InlineAsm> InlineAsms;
+  ConstantUniqueMap<InlineAsmKeyType, const InlineAsmKeyType&, PointerType,
+                    InlineAsm> InlineAsms;
   
   ConstantInt *TheTrueVal;
   ConstantInt *TheFalseVal;



From jay.foad at gmail.com  Wed Jun 22 03:56:57 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Wed, 22 Jun 2011 09:56:57 +0100
Subject: [llvm-commits] [llvm] r133412 - in /llvm/trunk:
 include/llvm/Constants.h lib/Analysis/ConstantFolding.cpp
 lib/AsmParser/LLParser.cpp lib/Bitcode/Reader/BitcodeReader.cpp
 lib/CodeGen/ShadowStackGC.cpp lib/Transforms/IPO/GlobalOpt.cpp
 lib/Transform
In-Reply-To: <87A7DCD7-1A1E-41F9-83EF-B675446B2830@nondot.org>
References: <BANLkTimBn5-=U7Re=p4gkh7CE3A7N5gf=Y+w6MD2teoEXDer6Q@mail.gmail.com>
	<6ACAF514-D83B-46F3-BBD9-13F295FB1FA2@nondot.org>
	<BANLkTi=KOpcn0CwHfObMA+Z7eakrgTWafwBPBt2XVjR36GTphA@mail.gmail.com>
	<87A7DCD7-1A1E-41F9-83EF-B675446B2830@nondot.org>
Message-ID: <BANLkTimeAsz9EkYXp=TvWphQwJcxyKTjL82ZkJ1YTFi_KcpU6Q@mail.gmail.com>

On 21 June 2011 19:40, Chris Lattner <sabre at nondot.org> wrote:
>
> On Jun 21, 2011, at 12:22 AM, Jay Foad wrote:
>
>>>> Patch 1 extends ConstantUniqueMap with a new template parameter
>>>> ValRefType, representing a const reference to ValType. Normally this
>>>> would just be const ValType&, but when ValType is a std::vector, we
>>>> want to use ArrayRef as the reference type.
>>
>>> Wow, looks great to me Jay
>>
>> Just to double check, are you OK with me adding the conversion operator
>>
>> ?ArrayRef<T>::operator std::vector<T>() const;
>
> I'm ok with it if there is no no other way

There's always another way; but I don't know what it is, so I've
committed my patch as-is.

Thanks,
Jay.


From jay.foad at gmail.com  Wed Jun 22 03:55:11 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Wed, 22 Jun 2011 08:55:11 -0000
Subject: [llvm-commits] [llvm] r133612 - /llvm/trunk/lib/VMCore/Constants.cpp
Message-ID: <20110622085512.0ABBE2A6C12C@llvm.org>

Author: foad
Date: Wed Jun 22 03:55:11 2011
New Revision: 133612

URL: http://llvm.org/viewvc/llvm-project?rev=133612&view=rev
Log:
Eliminate a temporary std::vector in ConstantStruct::get().

Modified:
    llvm/trunk/lib/VMCore/Constants.cpp

Modified: llvm/trunk/lib/VMCore/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=133612&r1=133611&r2=133612&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Constants.cpp (original)
+++ llvm/trunk/lib/VMCore/Constants.cpp Wed Jun 22 03:55:11 2011
@@ -666,10 +666,8 @@
   
   // Create a ConstantAggregateZero value if all elements are zeros.
   for (unsigned i = 0, e = V.size(); i != e; ++i)
-    if (!V[i]->isNullValue()) {
-      // FIXME: Eliminate temporary std::vector here!
-      return ST->getContext().pImpl->StructConstants.getOrCreate(ST, V.vec());
-    }
+    if (!V[i]->isNullValue())
+      return ST->getContext().pImpl->StructConstants.getOrCreate(ST, V);
 
   return ConstantAggregateZero::get(ST);
 }



From jay.foad at gmail.com  Wed Jun 22 04:10:20 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Wed, 22 Jun 2011 09:10:20 -0000
Subject: [llvm-commits] [llvm] r133614 - in /llvm/trunk:
 include/llvm/Constants.h lib/VMCore/ConstantFold.cpp
 lib/VMCore/Constants.cpp
Message-ID: <20110622091020.1BDAE2A6C12C@llvm.org>

Author: foad
Date: Wed Jun 22 04:10:19 2011
New Revision: 133614

URL: http://llvm.org/viewvc/llvm-project?rev=133614&view=rev
Log:
Make ConstantVector::get() always take an ArrayRef, never a std::vector.

Modified:
    llvm/trunk/include/llvm/Constants.h
    llvm/trunk/lib/VMCore/ConstantFold.cpp
    llvm/trunk/lib/VMCore/Constants.cpp

Modified: llvm/trunk/include/llvm/Constants.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=133614&r1=133613&r2=133614&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Constants.h (original)
+++ llvm/trunk/include/llvm/Constants.h Wed Jun 22 04:10:19 2011
@@ -491,8 +491,6 @@
 public:
   // ConstantVector accessors
   static Constant *get(ArrayRef<Constant*> V);
-  // FIXME: Eliminate this constructor form.
-  static Constant *get(const VectorType *T, const std::vector<Constant*> &V);
   
   /// Transparently provide more efficient getOperand methods.
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Constant);

Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=133614&r1=133613&r2=133614&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ConstantFold.cpp (original)
+++ llvm/trunk/lib/VMCore/ConstantFold.cpp Wed Jun 22 04:10:19 2011
@@ -559,7 +559,7 @@
       for (unsigned i = 0, e = CV->getType()->getNumElements(); i != e; ++i)
         res.push_back(ConstantExpr::getCast(opc,
                                             CV->getOperand(i), DstEltTy));
-      return ConstantVector::get(DestVecTy, res);
+      return ConstantVector::get(res);
     }
 
   // We actually have to do a cast now. Perform the cast according to the

Modified: llvm/trunk/lib/VMCore/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=133614&r1=133613&r2=133614&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Constants.cpp (original)
+++ llvm/trunk/lib/VMCore/Constants.cpp Wed Jun 22 04:10:19 2011
@@ -698,9 +698,9 @@
 }
 
 // ConstantVector accessors.
-Constant *ConstantVector::get(const VectorType *T,
-                              const std::vector<Constant*> &V) {
+Constant *ConstantVector::get(ArrayRef<Constant*> V) {
   assert(!V.empty() && "Vectors can't be empty");
+  const VectorType *T = VectorType::get(V.front()->getType(), V.size());
   LLVMContextImpl *pImpl = T->getContext().pImpl;
 
   // If this is an all-undef or all-zero vector, return a
@@ -725,12 +725,6 @@
   return pImpl->VectorConstants.getOrCreate(T, V);
 }
 
-Constant *ConstantVector::get(ArrayRef<Constant*> V) {
-  // FIXME: make this the primary ctor method.
-  assert(!V.empty() && "Vectors cannot be empty");
-  return get(VectorType::get(V.front()->getType(), V.size()), V.vec());
-}
-
 // Utility function for determining if a ConstantExpr is a CastOp or not. This
 // can't be inline because we don't want to #include Instruction.h into
 // Constant.h
@@ -2118,7 +2112,7 @@
     Values.push_back(Val);
   }
   
-  Constant *Replacement = get(cast<VectorType>(getRawType()), Values);
+  Constant *Replacement = get(Values);
   assert(Replacement != this && "I didn't contain From!");
   
   // Everyone using this now uses the replacement.



From jay.foad at gmail.com  Wed Jun 22 04:24:39 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Wed, 22 Jun 2011 09:24:39 -0000
Subject: [llvm-commits] [llvm] r133615 - in /llvm/trunk:
 include/llvm/Constants.h lib/AsmParser/LLParser.cpp
 lib/Bitcode/Reader/BitcodeReader.cpp
 lib/CodeGen/SelectionDAG/DAGCombiner.cpp lib/CodeGen/ShadowStackGC.cpp
 lib/Transforms/Instrumentation/GCOVProfiling.cpp lib/VMCore/Constants.cpp
 lib/VMCore/Core.cpp
Message-ID: <20110622092439.EE2DD2A6C124@llvm.org>

Author: foad
Date: Wed Jun 22 04:24:39 2011
New Revision: 133615

URL: http://llvm.org/viewvc/llvm-project?rev=133615&view=rev
Log:
Replace the existing forms of ConstantArray::get() with a single form
that takes an ArrayRef.

Modified:
    llvm/trunk/include/llvm/Constants.h
    llvm/trunk/lib/AsmParser/LLParser.cpp
    llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    llvm/trunk/lib/CodeGen/ShadowStackGC.cpp
    llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
    llvm/trunk/lib/VMCore/Constants.cpp
    llvm/trunk/lib/VMCore/Core.cpp

Modified: llvm/trunk/include/llvm/Constants.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=133615&r1=133614&r2=133615&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Constants.h (original)
+++ llvm/trunk/include/llvm/Constants.h Wed Jun 22 04:24:39 2011
@@ -350,9 +350,7 @@
   ConstantArray(const ArrayType *T, const std::vector<Constant*> &Val);
 public:
   // ConstantArray accessors
-  static Constant *get(const ArrayType *T, const std::vector<Constant*> &V);
-  static Constant *get(const ArrayType *T, Constant *const *Vals, 
-                       unsigned NumVals);
+  static Constant *get(const ArrayType *T, ArrayRef<Constant*> V);
                              
   /// This method constructs a ConstantArray and initializes it with a text
   /// string. The default behavior (AddNull==true) causes a null terminator to

Modified: llvm/trunk/lib/AsmParser/LLParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/AsmParser/LLParser.cpp?rev=133615&r1=133614&r2=133615&view=diff
==============================================================================
--- llvm/trunk/lib/AsmParser/LLParser.cpp (original)
+++ llvm/trunk/lib/AsmParser/LLParser.cpp Wed Jun 22 04:24:39 2011
@@ -2062,7 +2062,7 @@
                      " is not of type '" + getTypeString(Elts[0]->getType()));
     }
 
-    ID.ConstantVal = ConstantArray::get(ATy, Elts.data(), Elts.size());
+    ID.ConstantVal = ConstantArray::get(ATy, Elts);
     ID.Kind = ValID::t_Constant;
     return false;
   }

Modified: llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp?rev=133615&r1=133614&r2=133615&view=diff
==============================================================================
--- llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp (original)
+++ llvm/trunk/lib/Bitcode/Reader/BitcodeReader.cpp Wed Jun 22 04:24:39 2011
@@ -292,7 +292,7 @@
       // Make the new constant.
       Constant *NewC;
       if (ConstantArray *UserCA = dyn_cast<ConstantArray>(UserC)) {
-        NewC = ConstantArray::get(UserCA->getType(), &NewOps[0], NewOps.size());
+        NewC = ConstantArray::get(UserCA->getType(), NewOps);
       } else if (ConstantStruct *UserCS = dyn_cast<ConstantStruct>(UserC)) {
         NewC = ConstantStruct::get(UserCS->getType(), NewOps);
       } else if (isa<ConstantVector>(UserC)) {

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=133615&r1=133614&r2=133615&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jun 22 04:24:39 2011
@@ -7470,7 +7470,7 @@
         const TargetData &TD = *TLI.getTargetData();
 
         // Create a ConstantArray of the two constants.
-        Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts, 2);
+        Constant *CA = ConstantArray::get(ArrayType::get(FPTy, 2), Elts);
         SDValue CPIdx = DAG.getConstantPool(CA, TLI.getPointerTy(),
                                             TD.getPrefTypeAlignment(FPTy));
         unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment();

Modified: llvm/trunk/lib/CodeGen/ShadowStackGC.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ShadowStackGC.cpp?rev=133615&r1=133614&r2=133615&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ShadowStackGC.cpp (original)
+++ llvm/trunk/lib/CodeGen/ShadowStackGC.cpp Wed Jun 22 04:24:39 2011
@@ -201,6 +201,7 @@
       NumMeta = I + 1;
     Metadata.push_back(ConstantExpr::getBitCast(C, VoidPtr));
   }
+  Metadata.resize(NumMeta);
 
   const Type *Int32Ty = Type::getInt32Ty(F.getContext());
   
@@ -211,8 +212,7 @@
 
   Constant *DescriptorElts[] = {
     ConstantStruct::get(StructType::get(Int32Ty, Int32Ty, NULL), BaseElts),
-    ConstantArray::get(ArrayType::get(VoidPtr, NumMeta),
-                       Metadata.begin(), NumMeta)
+    ConstantArray::get(ArrayType::get(VoidPtr, NumMeta), Metadata)
   };
 
   Constant *FrameMap =

Modified: llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp?rev=133615&r1=133614&r2=133615&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp (original)
+++ llvm/trunk/lib/Transforms/Instrumentation/GCOVProfiling.cpp Wed Jun 22 04:24:39 2011
@@ -561,11 +561,11 @@
     Edge += Successors;
   }
 
+  ArrayRef<Constant*> V(&EdgeTable[0], Succs.size() * Preds.size());
   GlobalVariable *EdgeTableGV =
       new GlobalVariable(
           *M, EdgeTableTy, true, GlobalValue::InternalLinkage,
-          ConstantArray::get(EdgeTableTy,
-                             &EdgeTable[0], Succs.size() * Preds.size()),
+          ConstantArray::get(EdgeTableTy, V),
           "__llvm_gcda_edge_table");
   EdgeTableGV->setUnnamedAddr(true);
   return EdgeTableGV;

Modified: llvm/trunk/lib/VMCore/Constants.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=133615&r1=133614&r2=133615&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Constants.cpp (original)
+++ llvm/trunk/lib/VMCore/Constants.cpp Wed Jun 22 04:24:39 2011
@@ -571,8 +571,7 @@
   }
 }
 
-Constant *ConstantArray::get(const ArrayType *Ty, 
-                             const std::vector<Constant*> &V) {
+Constant *ConstantArray::get(const ArrayType *Ty, ArrayRef<Constant*> V) {
   for (unsigned i = 0, e = V.size(); i != e; ++i) {
     assert(V[i]->getType() == Ty->getElementType() &&
            "Wrong type in array element initializer");
@@ -592,13 +591,6 @@
   return ConstantAggregateZero::get(Ty);
 }
 
-
-Constant *ConstantArray::get(const ArrayType* T, Constant *const* Vals,
-                             unsigned NumVals) {
-  // FIXME: make this the primary ctor method.
-  return get(T, std::vector<Constant*>(Vals, Vals+NumVals));
-}
-
 /// ConstantArray::get(const string&) - Return an array that is initialized to
 /// contain the specified string.  If length is zero then a null terminator is 
 /// added to the specified string so that it may be used in a natural way. 

Modified: llvm/trunk/lib/VMCore/Core.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Core.cpp?rev=133615&r1=133614&r2=133615&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Core.cpp (original)
+++ llvm/trunk/lib/VMCore/Core.cpp Wed Jun 22 04:24:39 2011
@@ -625,9 +625,8 @@
 }
 LLVMValueRef LLVMConstArray(LLVMTypeRef ElementTy,
                             LLVMValueRef *ConstantVals, unsigned Length) {
-  return wrap(ConstantArray::get(ArrayType::get(unwrap(ElementTy), Length),
-                                 unwrap<Constant>(ConstantVals, Length),
-                                 Length));
+  ArrayRef<Constant*> V(unwrap<Constant>(ConstantVals, Length), Length);
+  return wrap(ConstantArray::get(ArrayType::get(unwrap(ElementTy), Length), V));
 }
 LLVMValueRef LLVMConstStruct(LLVMValueRef *ConstantVals, unsigned Count,
                              LLVMBool Packed) {



From nobled at dreamwidth.org  Wed Jun 22 07:18:46 2011
From: nobled at dreamwidth.org (nobled)
Date: Wed, 22 Jun 2011 08:18:46 -0400
Subject: [llvm-commits] [PATCHES] don't include config.h in public headers
Message-ID: <BANLkTim-9Bd1BirY57FbF0J0dY+MVykScw@mail.gmail.com>

llvm/Config/config.h contains a lot of standard macros like
PACKAGE_VERSION that don't make sense to expose to clients, who will
probably have their own private config.h with its own definition of
PACKAGE_VERSION et al. Right now, Klee runs into this and seems to be
working around it with #undef[1].

It's not actually needed in most cases, and these four patches remove
all the uses in llvm and clang headers. Unless it's also being
included in dragonegg or lldb sources or something, the file can
probably be excluded from `make install` entirely after this (but I'm
not sure how to do that). Okay to commit?

[1] http://llvm.org/viewvc/llvm-project/klee/trunk/lib/Core/ExternalDispatcher.cpp?r1=98467&r2=98466&pathrev=98467
-------------- next part --------------
From 96493bc1061dd38b05e63fcf99808de7ed7ae429 Mon Sep 17 00:00:00 2001
From: nobled <nobled at dreamwidth.org>
Date: Tue, 21 Jun 2011 07:25:37 +0000
Subject: [PATCH 1/3] Only use llvm-config.h in public headers

llvm-config.h defines most of the important macros "so that
they can be in exported headers and won't override package
specific directives." e.g., PACKAGE_NAME.

Endian.h wasn't using any macros at all though, so just delete
the include there instead.
---
 include/llvm/Support/Endian.h       |    1 -
 include/llvm/Support/system_error.h |    2 +-
 2 files changed, 1 insertions(+), 2 deletions(-)

diff --git a/include/llvm/Support/Endian.h b/include/llvm/Support/Endian.h
index f62eab0..af1b506 100644
--- a/include/llvm/Support/Endian.h
+++ b/include/llvm/Support/Endian.h
@@ -14,7 +14,6 @@
 #ifndef LLVM_SUPPORT_ENDIAN_H
 #define LLVM_SUPPORT_ENDIAN_H
 
-#include "llvm/Config/config.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/SwapByteOrder.h"
 #include "llvm/Support/type_traits.h"
diff --git a/include/llvm/Support/system_error.h b/include/llvm/Support/system_error.h
index b77030d..2c15b69 100644
--- a/include/llvm/Support/system_error.h
+++ b/include/llvm/Support/system_error.h
@@ -222,7 +222,7 @@ template <> struct hash<std::error_code>;
 
 */
 
-#include "llvm/Config/config.h"
+#include "llvm/Config/llvm-config.h"
 #include "llvm/Support/type_traits.h"
 #include <cerrno>
 #include <string>
-- 
1.7.0.4
-------------- next part --------------
From bbd1d7666736afe19b3b0c967666fab810e79aa7 Mon Sep 17 00:00:00 2001
From: nobled <nobled at dreamwidth.org>
Date: Tue, 21 Jun 2011 13:15:51 +0000
Subject: [PATCH] avoid using config.h in public headers

This is the only usage in clang's headers, and it's for a define
that only exists on CMake builds for the sake of the MSVC compiler,
so just use an ifdef instead.

Also add an include for config.h in a file that actually needs it,
but was picking it up by accident indirectly.
---
 include/clang/Basic/FileManager.h |    5 ++++-
 lib/Frontend/CompilerInstance.cpp |    1 +
 2 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/include/clang/Basic/FileManager.h b/include/clang/Basic/FileManager.h
index 2ca344d..1324533 100644
--- a/include/clang/Basic/FileManager.h
+++ b/include/clang/Basic/FileManager.h
@@ -21,10 +21,13 @@
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/OwningPtr.h"
 #include "llvm/Support/Allocator.h"
-#include "llvm/Config/config.h" // for mode_t
 // FIXME: Enhance libsystem to support inode and other fields in stat.
 #include <sys/types.h>
 
+#ifdef _MSC_VER
+typedef unsigned short mode_t;
+#endif
+
 struct stat;
 
 namespace llvm {
diff --git a/lib/Frontend/CompilerInstance.cpp b/lib/Frontend/CompilerInstance.cpp
index 38fcfe3..cb91c89 100644
--- a/lib/Frontend/CompilerInstance.cpp
+++ b/lib/Frontend/CompilerInstance.cpp
@@ -38,6 +38,7 @@
 #include "llvm/Support/Program.h"
 #include "llvm/Support/Signals.h"
 #include "llvm/Support/system_error.h"
+#include "llvm/Config/config.h"
 using namespace clang;
 
 CompilerInstance::CompilerInstance()
-- 
1.7.0.4
-------------- next part --------------
From fbc6303d169f7b50b4340c9380af66e00210ac0c Mon Sep 17 00:00:00 2001
From: nobled <nobled at dreamwidth.org>
Date: Tue, 21 Jun 2011 13:21:11 +0000
Subject: [PATCH 2/3] remove CMake mode_t define

It's now replaced with a simple ifdef _MSC_VER in the one
place it's needed (clang's FileManager.h header).
---
 cmake/config-ix.cmake              |    1 -
 include/llvm/Config/config.h.cmake |    3 ---
 2 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/cmake/config-ix.cmake b/cmake/config-ix.cmake
index c1b22d4..1a2cba5 100755
--- a/cmake/config-ix.cmake
+++ b/cmake/config-ix.cmake
@@ -349,7 +349,6 @@ endif( MINGW )
 
 if( MSVC )
   set(error_t int)
-  set(mode_t "unsigned short")
   set(LTDL_SHLIBPATH_VAR "PATH")
   set(LTDL_SYSSEARCHPATH "")
   set(LTDL_DLOPEN_DEPLIBS 1)
diff --git a/include/llvm/Config/config.h.cmake b/include/llvm/Config/config.h.cmake
index 755daa6..d07e0b2 100644
--- a/include/llvm/Config/config.h.cmake
+++ b/include/llvm/Config/config.h.cmake
@@ -686,9 +686,6 @@
    `char[]'. */
 #undef YYTEXT_POINTER
 
-/* Define to a type to use for `mode_t' if it is not otherwise available. */
-#cmakedefine mode_t ${mode_t}
-
 /* Define to a function replacing strtoll */
 #cmakedefine strtoll ${strtoll}
 
-- 
1.7.0.4
-------------- next part --------------
From e28c74fd0a90b02cf541450004e3d16fb3949bbd Mon Sep 17 00:00:00 2001
From: nobled <nobled at dreamwidth.org>
Date: Tue, 21 Jun 2011 07:30:57 +0000
Subject: [PATCH 3/3] make floating-exception header private

It has only one user. This eliminates the last include of
config.h from the public headers -- it should probably not
even be installed at `make install` time now.
---
 include/llvm/Support/FEnv.h      |   56 --------------------------------------
 lib/Analysis/ConstantFolding.cpp |    3 +-
 lib/Analysis/FEnv.h              |   56 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 58 insertions(+), 57 deletions(-)
 delete mode 100644 include/llvm/Support/FEnv.h
 create mode 100644 lib/Analysis/FEnv.h

diff --git a/include/llvm/Support/FEnv.h b/include/llvm/Support/FEnv.h
deleted file mode 100644
index f6f4333..0000000
--- a/include/llvm/Support/FEnv.h
+++ /dev/null
@@ -1,56 +0,0 @@
-//===- llvm/Support/FEnv.h - Host floating-point exceptions ------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides an operating system independent interface to
-// floating-point exception interfaces.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_SYSTEM_FENV_H
-#define LLVM_SYSTEM_FENV_H
-
-#include "llvm/Config/config.h"
-#include <cerrno>
-#ifdef HAVE_FENV_H
-#include <fenv.h>
-#endif
-
-// FIXME: Clang's #include handling apparently doesn't work for libstdc++'s
-// fenv.h; see PR6907 for details.
-#if defined(__clang__) && defined(_GLIBCXX_FENV_H)
-#undef HAVE_FENV_H
-#endif
-
-namespace llvm {
-namespace sys {
-
-/// llvm_fenv_clearexcept - Clear the floating-point exception state.
-static inline void llvm_fenv_clearexcept() {
-#ifdef HAVE_FENV_H
-  feclearexcept(FE_ALL_EXCEPT);
-#endif
-  errno = 0;
-}
-
-/// llvm_fenv_testexcept - Test if a floating-point exception was raised.
-static inline bool llvm_fenv_testexcept() {
-  int errno_val = errno;
-  if (errno_val == ERANGE || errno_val == EDOM)
-    return true;
-#ifdef HAVE_FENV_H
-  if (fetestexcept(FE_ALL_EXCEPT & ~FE_INEXACT))
-    return true;
-#endif
-  return false;
-}
-
-} // End sys namespace
-} // End llvm namespace
-
-#endif
diff --git a/lib/Analysis/ConstantFolding.cpp b/lib/Analysis/ConstantFolding.cpp
index b5fafd6..b64f3b9 100644
--- a/lib/Analysis/ConstantFolding.cpp
+++ b/lib/Analysis/ConstantFolding.cpp
@@ -31,9 +31,10 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/GetElementPtrTypeIterator.h"
 #include "llvm/Support/MathExtras.h"
-#include "llvm/Support/FEnv.h"
 #include <cerrno>
 #include <cmath>
+
+#include "FEnv.h"
 using namespace llvm;
 
 //===----------------------------------------------------------------------===//
diff --git a/lib/Analysis/FEnv.h b/lib/Analysis/FEnv.h
new file mode 100644
index 0000000..f6f4333
--- /dev/null
+++ b/lib/Analysis/FEnv.h
@@ -0,0 +1,56 @@
+//===- llvm/Support/FEnv.h - Host floating-point exceptions ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides an operating system independent interface to
+// floating-point exception interfaces.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SYSTEM_FENV_H
+#define LLVM_SYSTEM_FENV_H
+
+#include "llvm/Config/config.h"
+#include <cerrno>
+#ifdef HAVE_FENV_H
+#include <fenv.h>
+#endif
+
+// FIXME: Clang's #include handling apparently doesn't work for libstdc++'s
+// fenv.h; see PR6907 for details.
+#if defined(__clang__) && defined(_GLIBCXX_FENV_H)
+#undef HAVE_FENV_H
+#endif
+
+namespace llvm {
+namespace sys {
+
+/// llvm_fenv_clearexcept - Clear the floating-point exception state.
+static inline void llvm_fenv_clearexcept() {
+#ifdef HAVE_FENV_H
+  feclearexcept(FE_ALL_EXCEPT);
+#endif
+  errno = 0;
+}
+
+/// llvm_fenv_testexcept - Test if a floating-point exception was raised.
+static inline bool llvm_fenv_testexcept() {
+  int errno_val = errno;
+  if (errno_val == ERANGE || errno_val == EDOM)
+    return true;
+#ifdef HAVE_FENV_H
+  if (fetestexcept(FE_ALL_EXCEPT & ~FE_INEXACT))
+    return true;
+#endif
+  return false;
+}
+
+} // End sys namespace
+} // End llvm namespace
+
+#endif
-- 
1.7.0.4

From vanboxem.ruben at gmail.com  Wed Jun 22 10:28:22 2011
From: vanboxem.ruben at gmail.com (Ruben Van Boxem)
Date: Wed, 22 Jun 2011 17:28:22 +0200
Subject: [llvm-commits] [PATCH] Fix build on MinGW
Message-ID: <BANLkTimerx4TTm26eYkwfF7H9JRR14X4Nw@mail.gmail.com>

Hi,

Attached is a patch for MinGW.

The first bit selects the correct _mkdir function for all Windows platforms,
not just MSVC, which is wrong, and makes the MinGW build fail.

The second bit is about this bug: http://llvm.org/bugs/show_bug.cgi?id=8850
The patch only affects MinGW on x86_64, which is localized to exactly where
the crash occurs.

Please apply these as soon as you have time. Thanks!

Ruben
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From vanboxem.ruben at gmail.com  Wed Jun 22 10:33:52 2011
From: vanboxem.ruben at gmail.com (Ruben Van Boxem)
Date: Wed, 22 Jun 2011 17:33:52 +0200
Subject: [llvm-commits] [PATCH] Fix build on MinGW
In-Reply-To: <BANLkTimerx4TTm26eYkwfF7H9JRR14X4Nw@mail.gmail.com>
References: <BANLkTimerx4TTm26eYkwfF7H9JRR14X4Nw@mail.gmail.com>
Message-ID: <BANLkTi=wsrtcDVtDU7eVvmZ8_BUnetQ=3w@mail.gmail.com>

2011/6/22 Ruben Van Boxem <vanboxem.ruben at gmail.com>
>
> Hi,
>
> Attached is a patch for MinGW.
>
> The first bit selects the correct _mkdir function for all Windows platforms, not just MSVC, which is wrong, and makes the MinGW build fail.
>
> The second bit is about this bug: http://llvm.org/bugs/show_bug.cgi?id=8850
> The patch only affects MinGW on x86_64, which is localized to exactly where the crash occurs.
>
> Please apply these as soon as you have time. Thanks!
>
> Ruben

I'm terribly sorry, but the second bit was wrong in my first patch.
Attached is the correct version.

Ruben
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From stoklund at 2pi.dk  Wed Jun 22 10:46:37 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Wed, 22 Jun 2011 08:46:37 -0700
Subject: [llvm-commits] [LLVMdev] [PATCH] Get DCE to consider livein
	PhysRegs to successor basic blocks.
In-Reply-To: <4E00EBFF.1050205@playingwithpointers.com>
References: <4E004D97.2040707@playingwithpointers.com>
	<82C2784C-2409-4EFB-A59F-BAB30A22D5E2@2pi.dk>
	<4E00EBFF.1050205@playingwithpointers.com>
Message-ID: <058362BA-2F8A-4DFA-BA69-DFB5418AA685@2pi.dk>


On Jun 21, 2011, at 12:07 PM, Sanjoy Das wrote:

>> 
>> Looks good, but keep the comment (sans FIXME).
>> 
> 
> Revised patch attached.

Three nits:

-    // FIXME: Add live-ins from sucessors to LivePhysRegs. Normally, physregs
+    // Add live-ins from sucessors to LivePhysRegs. Normally, physregs
     // are not live across blocks, but some targets (x86) can have flags live
     // out of a block.
+    for (MachineBasicBlock::succ_iterator S = MBB->succ_begin();
+         S != MBB->succ_end(); S++) {
+      for (MachineBasicBlock::livein_iterator LI = (*S)->livein_begin();
+           LI != (*S)->livein_end(); LI++) {
+        LivePhysRegs.set(*LI);
+      }
+    }
 
1. Wrap the comment properly.
2. Use the standard LLVM idiom for evaluating the end() methods only once.
3. Don't use {} for single statements.

But note that you really shouldn't be depending on this patch for your work. Live physregs prevent code motion and (now) dead code elimination. Virtual registers are always better.

/jakob



From justin.holewinski at gmail.com  Wed Jun 22 11:07:04 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Wed, 22 Jun 2011 16:07:04 -0000
Subject: [llvm-commits] [llvm] r133619 - in /llvm/trunk/lib/Target/PTX:
 PTXAsmPrinter.cpp PTXInstrInfo.cpp PTXInstrInfo.h PTXRegisterInfo.cpp
 PTXRegisterInfo.h
Message-ID: <20110622160704.127662A6C12C@llvm.org>

Author: jholewinski
Date: Wed Jun 22 11:07:03 2011
New Revision: 133619

URL: http://llvm.org/viewvc/llvm-project?rev=133619&view=rev
Log:
PTX: Fix FrameIndex mapping bug

Modified:
    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.h
    llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp
    llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h

Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133619&r1=133618&r2=133619&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Wed Jun 22 11:07:03 2011
@@ -204,15 +204,18 @@
   }
 
   const MachineFrameInfo* FrameInfo = MF->getFrameInfo();
-  DEBUG(dbgs() << "Have " << FrameInfo->getNumObjects() << " frame object(s)\n");
+  DEBUG(dbgs() << "Have " << FrameInfo->getNumObjects()
+               << " frame object(s)\n");
   for (unsigned i = 0, e = FrameInfo->getNumObjects(); i != e; ++i) {
     DEBUG(dbgs() << "Size of object: " << FrameInfo->getObjectSize(i) << "\n");
-    std::string def = "\t.reg .b";
-    def += utostr(FrameInfo->getObjectSize(i)*8); // Convert to bits
-    def += " s";
-    def += utostr(i);
-    def += ";";
-    OutStreamer.EmitRawText(Twine(def));
+    if (FrameInfo->getObjectSize(i) > 0) {
+      std::string def = "\t.reg .b";
+      def += utostr(FrameInfo->getObjectSize(i)*8); // Convert to bits
+      def += " s";
+      def += utostr(i);
+      def += ";";
+      OutStreamer.EmitRawText(Twine(def));
+    }
   }
 }
 

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=133619&r1=133618&r2=133619&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Wed Jun 22 11:07:03 2011
@@ -291,7 +291,7 @@
 // Memory operand folding for spills
 void PTXInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MII,
-                                       unsigned SrcReg, bool isKill, int FrameIdx,
+                                     unsigned SrcReg, bool isKill, int FrameIdx,
                                        const TargetRegisterClass *RC,
                                        const TargetRegisterInfo *TRI) const {
   MachineInstr& MI = *MII;
@@ -318,7 +318,7 @@
 
   // Build the store instruction (really a mov)
   MachineInstrBuilder MIB = BuildMI(MBB, MII, DL, get(OpCode));
-  MIB.addImm(FrameIdx);
+  MIB.addFrameIndex(FrameIdx);
   MIB.addReg(SrcReg);
 
   AddDefaultPredicate(MIB);
@@ -354,7 +354,7 @@
   // Build the load instruction (really a mov)
   MachineInstrBuilder MIB = BuildMI(MBB, MII, DL, get(OpCode));
   MIB.addReg(DestReg);
-  MIB.addImm(FrameIdx);
+  MIB.addFrameIndex(FrameIdx);
 
   AddDefaultPredicate(MIB);
 }

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.h?rev=133619&r1=133618&r2=133619&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.h Wed Jun 22 11:07:03 2011
@@ -93,7 +93,7 @@
   //       efficient code anyway.
   // virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
   //                                             MachineInstr* MI,
-  //                                          const SmallVectorImpl<unsigned> &Ops,
+  //                                       const SmallVectorImpl<unsigned> &Ops,
   //                                             int FrameIndex) const;
 
   virtual void storeRegToStackSlot(MachineBasicBlock& MBB,

Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp?rev=133619&r1=133618&r2=133619&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp Wed Jun 22 11:07:03 2011
@@ -13,7 +13,34 @@
 
 #include "PTX.h"
 #include "PTXRegisterInfo.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 #include "PTXGenRegisterInfo.inc"
+
+
+void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+                                          int SPAdj,
+                                          RegScavenger *RS) const {
+  unsigned Index;
+  MachineInstr& MI = *II;
+
+  Index = 0;
+  while (!MI.getOperand(Index).isFI()) {
+    ++Index;
+    assert(Index < MI.getNumOperands() &&
+           "Instr does not have a FrameIndex operand!");
+  }
+
+  int FrameIndex = MI.getOperand(Index).getIndex();
+
+  DEBUG(dbgs() << "eliminateFrameIndex: " << MI);
+  DEBUG(dbgs() << "- SPAdj: " << SPAdj << "\n");
+  DEBUG(dbgs() << "- FrameIndex: " << FrameIndex << "\n");
+
+  // This frame index is post stack slot re-use assignments
+  MI.getOperand(Index).ChangeToImmediate(FrameIndex);
+}

Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h?rev=133619&r1=133618&r2=133619&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h Wed Jun 22 11:07:03 2011
@@ -38,11 +38,9 @@
     return Reserved; // reserve no regs
   }
 
-  virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
+  virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
                                    int SPAdj,
-                                   RegScavenger *RS = NULL) const {
-    llvm_unreachable("PTX does not support general function call");
-  }
+                                   RegScavenger *RS = NULL) const;
 
   virtual unsigned getFrameRegister(const MachineFunction &MF) const {
     llvm_unreachable("PTX does not have a frame register");



From dan at dneg.com  Wed Jun 22 04:04:31 2011
From: dan at dneg.com (Dan Bailey)
Date: Wed, 22 Jun 2011 09:04:31 -0000
Subject: [llvm-commits] [llvm] r133613 - /llvm/trunk/lib/Target/PTX/PTX.td
Message-ID: <20110622090431.18F192A6C12C@llvm.org>

Author: drb
Date: Wed Jun 22 04:04:30 2011
New Revision: 133613

URL: http://llvm.org/viewvc/llvm-project?rev=133613&view=rev
Log:
Test Commit.

Modified:
    llvm/trunk/lib/Target/PTX/PTX.td

Modified: llvm/trunk/lib/Target/PTX/PTX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.td?rev=133613&r1=133612&r2=133613&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTX.td (original)
+++ llvm/trunk/lib/Target/PTX/PTX.td Wed Jun 22 04:04:30 2011
@@ -16,7 +16,7 @@
 include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
-// Subtarget Features.
+// Subtarget Features
 //===----------------------------------------------------------------------===//
 
 //===- Architectural Features ---------------------------------------------===//
@@ -57,7 +57,7 @@
                                    [FeatureSM13]>;
 
 //===----------------------------------------------------------------------===//
-// PTX supported processors.
+// PTX supported processors
 //===----------------------------------------------------------------------===//
 
 class Proc<string Name, list<SubtargetFeature> Features>



From echristo at apple.com  Wed Jun 22 12:53:17 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 22 Jun 2011 10:53:17 -0700
Subject: [llvm-commits] [PATCHES] don't include config.h in public
	headers
In-Reply-To: <BANLkTim-9Bd1BirY57FbF0J0dY+MVykScw@mail.gmail.com>
References: <BANLkTim-9Bd1BirY57FbF0J0dY+MVykScw@mail.gmail.com>
Message-ID: <752F1885-24B8-4C7C-9324-0E8A06118031@apple.com>


On Jun 22, 2011, at 5:18 AM, nobled wrote:

> llvm/Config/config.h contains a lot of standard macros like
> PACKAGE_VERSION that don't make sense to expose to clients, who will
> probably have their own private config.h with its own definition of
> PACKAGE_VERSION et al. Right now, Klee runs into this and seems to be
> working around it with #undef[1].
> 
> It's not actually needed in most cases, and these four patches remove
> all the uses in llvm and clang headers. Unless it's also being
> included in dragonegg or lldb sources or something, the file can
> probably be excluded from `make install` entirely after this (but I'm
> not sure how to do that). Okay to commit?

Looks good to me. Thanks!

-eric

From echristo at apple.com  Wed Jun 22 12:53:33 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 22 Jun 2011 10:53:33 -0700
Subject: [llvm-commits] [cfe-commits] [PATCHES] don't include config.h
	in public headers
In-Reply-To: <BANLkTim-9Bd1BirY57FbF0J0dY+MVykScw@mail.gmail.com>
References: <BANLkTim-9Bd1BirY57FbF0J0dY+MVykScw@mail.gmail.com>
Message-ID: <3B3A865E-1550-47DB-B3FD-C1FB05734C76@apple.com>


On Jun 22, 2011, at 5:18 AM, nobled wrote:

> llvm/Config/config.h contains a lot of standard macros like
> PACKAGE_VERSION that don't make sense to expose to clients, who will
> probably have their own private config.h with its own definition of
> PACKAGE_VERSION et al. Right now, Klee runs into this and seems to be
> working around it with #undef[1].
> 
> It's not actually needed in most cases, and these four patches remove
> all the uses in llvm and clang headers. Unless it's also being
> included in dragonegg or lldb sources or something, the file can
> probably be excluded from `make install` entirely after this (but I'm
> not sure how to do that). Okay to commit?

Looks good to me.

Thanks!

-eric

From echristo at apple.com  Wed Jun 22 13:24:27 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 22 Jun 2011 11:24:27 -0700
Subject: [llvm-commits] [llvm] r133513 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/Target/CppBackend/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
In-Reply-To: <20110621103319.B0D332A6C12C@llvm.org>
References: <20110621103319.B0D332A6C12C@llvm.org>
Message-ID: <5AAC95DA-F372-4AC4-BF66-AF474C061E34@apple.com>


On Jun 21, 2011, at 3:33 AM, Jay Foad wrote:

> Author: foad
> Date: Tue Jun 21 05:33:19 2011
> New Revision: 133513
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133513&view=rev
> Log:
> Reinstate r133435 and r133449 (reverted in r133499) now that the clang
> self-hosted build failure has been fixed (r133512).
> 

This is causing some additional warnings:

/Developer/usr/local/include/llvm/Instructions.h: In member function 'llvm::BasicBlock* llvm::PHINode::getIncomingBlock(const llvm::Use&) const':
/Developer/usr/local/include/llvm/Instructions.h:1909: warning: implicit conversion shortens 64-bit value into a 32-bit value

To duplicate just turn on conversion warnings, in particular with llvm-gcc -Wshorten-64-to-32, in a file that includes Instructions.h.

Could you get these? Thanks.

-eric

From nicholas at mxc.ca  Wed Jun 22 13:55:03 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 22 Jun 2011 18:55:03 -0000
Subject: [llvm-commits] [llvm] r133631 - in /llvm/trunk:
 lib/CodeGen/AsmPrinter/AsmPrinter.cpp test/CodeGen/ARM/constants.ll
Message-ID: <20110622185503.95D912A6C12C@llvm.org>

Author: nicholas
Date: Wed Jun 22 13:55:03 2011
New Revision: 133631

URL: http://llvm.org/viewvc/llvm-project?rev=133631&view=rev
Log:
Emit trailing padding on constant vectors when TargetData says that the vector
is larger than the sum of the elements (including per-element padding).

Modified:
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/test/CodeGen/ARM/constants.ll

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=133631&r1=133630&r2=133631&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Wed Jun 22 13:55:03 2011
@@ -1516,6 +1516,13 @@
                                      unsigned AddrSpace, AsmPrinter &AP) {
   for (unsigned i = 0, e = CV->getType()->getNumElements(); i != e; ++i)
     EmitGlobalConstantImpl(CV->getOperand(i), AddrSpace, AP);
+
+  const TargetData &TD = *AP.TM.getTargetData();
+  unsigned Size = TD.getTypeAllocSize(CV->getType());
+  unsigned EmittedSize = TD.getTypeAllocSize(CV->getType()->getElementType()) *
+                         CV->getType()->getNumElements();
+  if (unsigned Padding = Size - EmittedSize)
+    AP.OutStreamer.EmitZeros(Padding, AddrSpace);
 }
 
 static void EmitGlobalConstantStruct(const ConstantStruct *CS,

Modified: llvm/trunk/test/CodeGen/ARM/constants.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/constants.ll?rev=133631&r1=133630&r2=133631&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/constants.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/constants.ll Wed Jun 22 13:55:03 2011
@@ -44,3 +44,16 @@
 r:
         ret void
 }
+
+%t1 = type { <3 x float>, <3 x float> }
+
+ at const1 = global %t1 { <3 x float> zeroinitializer,
+                       <3 x float> <float 1.000000e+00,
+                                    float 2.000000e+00,
+                                    float 3.000000e+00> }, align 16
+; CHECK: const1
+; CHECK: .zero 16
+; CHECK: float 1.0
+; CHECK: float 2.0
+; CHECK: float 3.0
+; CHECK: .zero 4



From nlewycky at google.com  Wed Jun 22 14:01:03 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Wed, 22 Jun 2011 12:01:03 -0700
Subject: [llvm-commits] patch: fix emission of npot vectors which need
 trailing padding
In-Reply-To: <BANLkTinhGxTkK1WgQwGQrd-ZHeTM6s5Rxg@mail.gmail.com>
References: <BANLkTinhSx1XZV_6kDR8e3U=YP4V1rQuXA@mail.gmail.com>
	<BANLkTikqZYc=LyAbboTr=xHO2adgD4OfMw@mail.gmail.com>
	<BANLkTikxRPdVZp6eVYunfzN9GyMfE_T7o2_Wgbi1pVFEKFdacQ@mail.gmail.com>
	<BANLkTinhGxTkK1WgQwGQrd-ZHeTM6s5Rxg@mail.gmail.com>
Message-ID: <BANLkTi=ysC==vymb_5SrLvsb7_xf0WP+TxR97jOVxo-D2cmFVA@mail.gmail.com>

On 22 June 2011 01:26, Renato Golin <renato.golin at arm.com> wrote:

> On 22 June 2011 00:19, Nick Lewycky <nlewycky at google.com> wrote:
> > Hi Renato! Sorry, but I don't understand your reply at all.
>
> I think you did, and answered my question at the same time. ;)
>
>
> > There's nothing ARM-specific about this change, which is why it belongs
> in
> > generic CodeGen and shouldn't be in the ARMAsmPrinter. It just so happens
> > that <3 x float> on ARM provides a counter-example that would require
> this
> > padding or trigger this assertion.
>
> I was fooled by your comment on ARM's vector size and thought your
> patch was in the wrong place. As you say (and Eli has shown), this is
> not platform specific, so the patch is good.
>
> Sorry about the confusion.
>

No problem, thanks for the review!

Nick
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From nicholas at mxc.ca  Wed Jun 22 14:42:14 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 22 Jun 2011 19:42:14 -0000
Subject: [llvm-commits] [llvm] r133634 -
	/llvm/trunk/test/CodeGen/ARM/constants.ll
Message-ID: <20110622194215.0289D2A6C12C@llvm.org>

Author: nicholas
Date: Wed Jun 22 14:42:14 2011
New Revision: 133634

URL: http://llvm.org/viewvc/llvm-project?rev=133634&view=rev
Log:
Needs a triple.

Modified:
    llvm/trunk/test/CodeGen/ARM/constants.ll

Modified: llvm/trunk/test/CodeGen/ARM/constants.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/constants.ll?rev=133634&r1=133633&r2=133634&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/constants.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/constants.ll Wed Jun 22 14:42:14 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -disable-cgp-branch-opts | FileCheck %s
+; RUN: llc < %s -mtriple=armv4t-unknown-linux-gnueabi -disable-cgp-branch-opts | FileCheck %s
 
 define i32 @f1() {
 ; CHECK: f1



From dpatel at apple.com  Wed Jun 22 14:52:37 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 22 Jun 2011 19:52:37 -0000
Subject: [llvm-commits] [llvm] r133636 -
	/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
Message-ID: <20110622195237.198C72A6C12C@llvm.org>

Author: dpatel
Date: Wed Jun 22 14:52:36 2011
New Revision: 133636

URL: http://llvm.org/viewvc/llvm-project?rev=133636&view=rev
Log:
Set debug loc.

Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=133636&r1=133635&r2=133636&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Wed Jun 22 14:52:36 2011
@@ -1400,6 +1400,8 @@
     // Patch the new value into place.
     if (Op->hasName())
       NewVal->takeName(Op);
+    if (Instruction *NewValI = dyn_cast<Instruction>(NewVal))
+      NewValI->setDebugLoc(User->getDebugLoc());
     User->replaceUsesOfWith(Op, NewVal);
     UI->setOperandValToReplace(NewVal);
 



From grosbach at apple.com  Wed Jun 22 15:14:52 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Jun 2011 20:14:52 -0000
Subject: [llvm-commits] [llvm] r133638 - in /llvm/trunk/lib/Target/ARM:
 ARM.h ARMAsmBackend.cpp ARMMachObjectWriter.cpp CMakeLists.txt
Message-ID: <20110622201452.7C55A2A6C12C@llvm.org>

Author: grosbach
Date: Wed Jun 22 15:14:52 2011
New Revision: 133638

URL: http://llvm.org/viewvc/llvm-project?rev=133638&view=rev
Log:
Move ARMMachObjectWriter to its own file.

Just tidy up a bit. No functional change.

Added:
    llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp
Modified:
    llvm/trunk/lib/Target/ARM/ARM.h
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
    llvm/trunk/lib/Target/ARM/CMakeLists.txt

Modified: llvm/trunk/lib/Target/ARM/ARM.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=133638&r1=133637&r2=133638&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.h (original)
+++ llvm/trunk/lib/Target/ARM/ARM.h Wed Jun 22 15:14:52 2011
@@ -27,6 +27,7 @@
 class JITCodeEmitter;
 class formatted_raw_ostream;
 class MCCodeEmitter;
+class MCObjectWriter;
 class TargetAsmBackend;
 class MachineInstr;
 class ARMAsmPrinter;
@@ -58,6 +59,12 @@
 void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
                                   ARMAsmPrinter &AP);
 
+/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
+MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
+                                          bool Is64Bit,
+                                          uint32_t CPUType,
+                                          uint32_t CPUSubtype);
+
 } // end namespace llvm;
 
 #endif

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=133638&r1=133637&r2=133638&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Wed Jun 22 15:14:52 2011
@@ -28,14 +28,6 @@
 using namespace llvm;
 
 namespace {
-class ARMMachObjectWriter : public MCMachObjectTargetWriter {
-public:
-  ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
-                      uint32_t CPUSubtype)
-    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
-                               /*UseAggressiveSymbolFolding=*/true) {}
-};
-
 class ARMELFObjectWriter : public MCELFObjectTargetWriter {
 public:
   ARMELFObjectWriter(Triple::OSType OSType)
@@ -423,12 +415,9 @@
     : ARMAsmBackend(T), Subtype(st) { }
 
   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
-    return createMachObjectWriter(new ARMMachObjectWriter(
-                                    /*Is64Bit=*/false,
-                                    object::mach::CTM_ARM,
-                                    Subtype),
-                                  OS,
-                                  /*IsLittleEndian=*/true);
+    return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
+                                     object::mach::CTM_ARM,
+                                     Subtype);
   }
 
   void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,

Added: llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp?rev=133638&view=auto
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp (added)
+++ llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp Wed Jun 22 15:14:52 2011
@@ -0,0 +1,32 @@
+//===-- ARMMachObjectWriter.cpp - ARM Mach Object Writer ------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "ARM.h"
+#include "llvm/MC/MCMachObjectWriter.h"
+using namespace llvm;
+
+namespace {
+class ARMMachObjectWriter : public MCMachObjectTargetWriter {
+public:
+  ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
+                      uint32_t CPUSubtype)
+    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
+                               /*UseAggressiveSymbolFolding=*/true) {}
+};
+}
+
+MCObjectWriter *llvm::createARMMachObjectWriter(raw_ostream &OS,
+                                                bool Is64Bit,
+                                                uint32_t CPUType,
+                                                uint32_t CPUSubtype) {
+  return createMachObjectWriter(new ARMMachObjectWriter(Is64Bit,
+                                                        CPUType,
+                                                        CPUSubtype),
+                                OS, /*IsLittleEndian=*/true);
+}

Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=133638&r1=133637&r2=133638&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Wed Jun 22 15:14:52 2011
@@ -34,6 +34,7 @@
   ARMISelLowering.cpp
   ARMInstrInfo.cpp
   ARMJITInfo.cpp
+  ARMMachObjectWriter.cpp
   ARMMCCodeEmitter.cpp
   ARMMCExpr.cpp
   ARMLoadStoreOptimizer.cpp



From nlewycky at google.com  Wed Jun 22 15:40:42 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Wed, 22 Jun 2011 13:40:42 -0700
Subject: [llvm-commits] [llvm] r133638 - in /llvm/trunk/lib/Target/ARM:
 ARM.h ARMAsmBackend.cpp ARMMachObjectWriter.cpp CMakeLists.txt
In-Reply-To: <20110622201452.7C55A2A6C12C@llvm.org>
References: <20110622201452.7C55A2A6C12C@llvm.org>
Message-ID: <BANLkTikKRqU-WxPwbDvwRB8xn74_qdPd-3iv+bK1qsz_NRFJRQ@mail.gmail.com>

Hi Jim,

ARMMachObjectWriter is missing #include "llvm/Support/DataTypes.h" for
uint32_t!

llvm[3]: Compiling ARMISelDAGToDAG.cpp for Debug+Asserts build
In file included from ARMAsmBackend.cpp:10:
ARM.h:65: error: ?uint32_t? has not been declared
ARM.h:66: error: ?uint32_t? has not been declared
In file included from ARMBaseRegisterInfo.cpp:14:
ARM.h:65: error: ?uint32_t? has not been declared
ARM.h:66: error: ?uint32_t? has not been declared
In file included from ARMExpandPseudoInsts.cpp:18:
ARM.h:65: error: ?uint32_t? has not been declared
ARM.h:66: error: ?uint32_t? has not been declared
In file included from ARMConstantIslandPass.cpp:17:
ARM.h:65: error: ?uint32_t? has not been declared
ARM.h:66: error: ?uint32_t? has not been declared
[...]

Nick

On 22 June 2011 13:14, Jim Grosbach <grosbach at apple.com> wrote:

> Author: grosbach
> Date: Wed Jun 22 15:14:52 2011
> New Revision: 133638
>
> URL: http://llvm.org/viewvc/llvm-project?rev=133638&view=rev
> Log:
> Move ARMMachObjectWriter to its own file.
>
> Just tidy up a bit. No functional change.
>
> Added:
>    llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp
> Modified:
>    llvm/trunk/lib/Target/ARM/ARM.h
>    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
>    llvm/trunk/lib/Target/ARM/CMakeLists.txt
>
> Modified: llvm/trunk/lib/Target/ARM/ARM.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=133638&r1=133637&r2=133638&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARM.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARM.h Wed Jun 22 15:14:52 2011
> @@ -27,6 +27,7 @@
>  class JITCodeEmitter;
>  class formatted_raw_ostream;
>  class MCCodeEmitter;
> +class MCObjectWriter;
>  class TargetAsmBackend;
>  class MachineInstr;
>  class ARMAsmPrinter;
> @@ -58,6 +59,12 @@
>  void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
>                                   ARMAsmPrinter &AP);
>
> +/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
> +MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
> +                                          bool Is64Bit,
> +                                          uint32_t CPUType,
> +                                          uint32_t CPUSubtype);
> +
>  } // end namespace llvm;
>
>  #endif
>
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=133638&r1=133637&r2=133638&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Wed Jun 22 15:14:52 2011
> @@ -28,14 +28,6 @@
>  using namespace llvm;
>
>  namespace {
> -class ARMMachObjectWriter : public MCMachObjectTargetWriter {
> -public:
> -  ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
> -                      uint32_t CPUSubtype)
> -    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
> -                               /*UseAggressiveSymbolFolding=*/true) {}
> -};
> -
>  class ARMELFObjectWriter : public MCELFObjectTargetWriter {
>  public:
>   ARMELFObjectWriter(Triple::OSType OSType)
> @@ -423,12 +415,9 @@
>     : ARMAsmBackend(T), Subtype(st) { }
>
>   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
> -    return createMachObjectWriter(new ARMMachObjectWriter(
> -                                    /*Is64Bit=*/false,
> -                                    object::mach::CTM_ARM,
> -                                    Subtype),
> -                                  OS,
> -                                  /*IsLittleEndian=*/true);
> +    return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
> +                                     object::mach::CTM_ARM,
> +                                     Subtype);
>   }
>
>   void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
>
> Added: llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp?rev=133638&view=auto
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp (added)
> +++ llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp Wed Jun 22 15:14:52
> 2011
> @@ -0,0 +1,32 @@
> +//===-- ARMMachObjectWriter.cpp - ARM Mach Object Writer
> ------------------===//
> +//
> +//                     The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
>
> +//===----------------------------------------------------------------------===//
> +
> +#include "ARM.h"
> +#include "llvm/MC/MCMachObjectWriter.h"
> +using namespace llvm;
> +
> +namespace {
> +class ARMMachObjectWriter : public MCMachObjectTargetWriter {
> +public:
> +  ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
> +                      uint32_t CPUSubtype)
> +    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
> +                               /*UseAggressiveSymbolFolding=*/true) {}
> +};
> +}
> +
> +MCObjectWriter *llvm::createARMMachObjectWriter(raw_ostream &OS,
> +                                                bool Is64Bit,
> +                                                uint32_t CPUType,
> +                                                uint32_t CPUSubtype) {
> +  return createMachObjectWriter(new ARMMachObjectWriter(Is64Bit,
> +                                                        CPUType,
> +                                                        CPUSubtype),
> +                                OS, /*IsLittleEndian=*/true);
> +}
>
> Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=133638&r1=133637&r2=133638&view=diff
>
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Wed Jun 22 15:14:52 2011
> @@ -34,6 +34,7 @@
>   ARMISelLowering.cpp
>   ARMInstrInfo.cpp
>   ARMJITInfo.cpp
> +  ARMMachObjectWriter.cpp
>   ARMMCCodeEmitter.cpp
>   ARMMCExpr.cpp
>   ARMLoadStoreOptimizer.cpp
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
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From mcrosier at apple.com  Wed Jun 22 15:44:25 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 22 Jun 2011 13:44:25 -0700
Subject: [llvm-commits] [llvm] r133607 -
 /llvm/trunk/lib/CodeGen/TailDuplication.cpp
In-Reply-To: <20110622040159.1F7682A6C12C@llvm.org>
References: <20110622040159.1F7682A6C12C@llvm.org>
Message-ID: <3C3F2F7A-B5FD-4157-91BA-7F0902CF54C6@apple.com>

Hi Rafael,
I'm seeing a failure in gccTestSuite for gcc.c-torture/compile/pr21356.c (errors below).  This is causing one of our internal buildbots to fail.  Would you mind taking a look?

 Regards,
  Chad 

Test Run By mcrosier on Wed Jun 22 13:32:56 2011
Native configuration is i386-apple-darwin10

                === gcc tests ===

Schedule of variations:
    unix

Running target unix
Using /usr/share/dejagnu/baseboards/unix.exp as board description file for target.
Using /usr/share/dejagnu/config/unix.exp as generic interface file for target.
Using /Users/mcrosier/clang-gcc-4_2-testsuite/src/config/default.exp as tool-and-target-specific interface file.
Running /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/compile.exp ...
Executing on host: /Users/mcrosier/llvm-clean/install/bin/clang   -O0  -w -fno-show-column -c  -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c    (timeout = 300)
spawn /Users/mcrosier/llvm-clean/install/bin/clang -O0 -w -fno-show-column -c -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c
PASS: gcc.c-torture/compile/pr21356.c  -O0  (test for excess errors)
Executing on host: /Users/mcrosier/llvm-clean/install/bin/clang   -O1  -w -fno-show-column -c  -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c    (timeout = 300)
spawn /Users/mcrosier/llvm-clean/install/bin/clang -O1 -w -fno-show-column -c -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp7'
compiler exited with status 1
output is:
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp7'

FAIL: gcc.c-torture/compile/pr21356.c  -O1  (test for excess errors)
Excess errors:
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp7'

Executing on host: /Users/mcrosier/llvm-clean/install/bin/clang   -O2  -w -fno-show-column -c  -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c    (timeout = 300)
spawn /Users/mcrosier/llvm-clean/install/bin/clang -O2 -w -fno-show-column -c -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp7'
compiler exited with status 1
output is:
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp7'

FAIL: gcc.c-torture/compile/pr21356.c  -O2  (test for excess errors)
Excess errors:
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp7'

Executing on host: /Users/mcrosier/llvm-clean/install/bin/clang   -O3 -fomit-frame-pointer  -w -fno-show-column -c  -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c    (timeout = 300)
spawn /Users/mcrosier/llvm-clean/install/bin/clang -O3 -fomit-frame-pointer -w -fno-show-column -c -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp2'
compiler exited with status 1
output is:
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp2'

FAIL: gcc.c-torture/compile/pr21356.c  -O3 -fomit-frame-pointer  (test for excess errors)
Excess errors:
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp2'

Executing on host: /Users/mcrosier/llvm-clean/install/bin/clang   -O3 -g  -w -fno-show-column -c  -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c    (timeout = 300)
spawn /Users/mcrosier/llvm-clean/install/bin/clang -O3 -g -w -fno-show-column -c -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp12'
compiler exited with status 1
output is:
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp12'

FAIL: gcc.c-torture/compile/pr21356.c  -O3 -g  (test for excess errors)
Excess errors:
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp12'

Executing on host: /Users/mcrosier/llvm-clean/install/bin/clang   -Os  -w -fno-show-column -c  -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c    (timeout = 300)
spawn /Users/mcrosier/llvm-clean/install/bin/clang -Os -w -fno-show-column -c -o pr21356.o /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/pr21356.c
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp7'
compiler exited with status 1
output is:
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp7'

FAIL: gcc.c-torture/compile/pr21356.c  -Os  (test for excess errors)
Excess errors:
fatal error: error in backend: unsupported relocation of undefined symbol 'Ltmp7'

testcase /Users/mcrosier/clang-gcc-4_2-testsuite/src/gcc.c-torture/compile/compile.exp completed in 0 seconds

                === gcc Summary ===

# of expected passes            1
# of unexpected failures        5
Executing on host: /Users/mcrosier/llvm-clean/install/bin/clang -v    (timeout = 300)
spawn /Users/mcrosier/llvm-clean/install/bin/clang -v
clang version 3.0 (trunk 133604)
Target: x86_64-apple-darwin
Thread model: posix
/Users/mcrosier/llvm-clean/install/bin/clang  version 3.0 (trunk 133604)

runtest completed at Wed Jun 22 13:32:59 2011


On Jun 21, 2011, at 9:01 PM, Rafael Espindola wrote:

> Author: rafael
> Date: Tue Jun 21 23:01:58 2011
> New Revision: 133607
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133607&view=rev
> Log:
> Reenable the optimization added in 133415, but change the definition of a "simple" bb to
> be one with only one unconditional branch and no phis. Duplicating the phis in this case
> is possible, but requeres liveness analysis or breaking edges.
> 
> Modified:
>    llvm/trunk/lib/CodeGen/TailDuplication.cpp
> 
> Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133607&r1=133606&r2=133607&view=diff
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
> +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Tue Jun 21 23:01:58 2011
> @@ -568,9 +568,9 @@
> TailDuplicatePass::isSimpleBB(MachineBasicBlock *TailBB) {
>   if (TailBB->succ_size() != 1)
>     return false;
> -  MachineBasicBlock::iterator I = TailBB->getFirstNonPHI();
> +  MachineBasicBlock::iterator I = TailBB->begin();
>   MachineBasicBlock::iterator E = TailBB->end();
> -  while (I->isDebugValue() && I != E)
> +  while (I != E && I->isDebugValue())
>     ++I;
>   if (I == E)
>     return true;
> @@ -712,7 +712,7 @@
>   DenseSet<unsigned> UsedByPhi;
>   getRegsUsedByPHIs(*TailBB, &UsedByPhi);
> 
> -  if (0 && isSimpleBB(TailBB))
> +  if (isSimpleBB(TailBB))
>     return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
> 
>   // Iterate through all the unique predecessors and tail-duplicate this
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From grosbach at apple.com  Wed Jun 22 15:40:30 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Jun 2011 20:40:30 -0000
Subject: [llvm-commits] [llvm] r133640 - /llvm/trunk/lib/Target/ARM/ARM.h
Message-ID: <20110622204030.CCB512A6C12C@llvm.org>

Author: grosbach
Date: Wed Jun 22 15:40:30 2011
New Revision: 133640

URL: http://llvm.org/viewvc/llvm-project?rev=133640&view=rev
Log:
Add missing header.

Modified:
    llvm/trunk/lib/Target/ARM/ARM.h

Modified: llvm/trunk/lib/Target/ARM/ARM.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=133640&r1=133639&r2=133640&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.h (original)
+++ llvm/trunk/lib/Target/ARM/ARM.h Wed Jun 22 15:40:30 2011
@@ -16,6 +16,7 @@
 #define TARGET_ARM_H
 
 #include "ARMBaseInfo.h"
+#include "llvm/Support/DataTypes.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetMachine.h"
 #include <cassert>



From grosbach at apple.com  Wed Jun 22 15:47:06 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Wed, 22 Jun 2011 13:47:06 -0700
Subject: [llvm-commits] [llvm] r133638 - in /llvm/trunk/lib/Target/ARM:
 ARM.h ARMAsmBackend.cpp ARMMachObjectWriter.cpp CMakeLists.txt
In-Reply-To: <BANLkTikKRqU-WxPwbDvwRB8xn74_qdPd-3iv+bK1qsz_NRFJRQ@mail.gmail.com>
References: <20110622201452.7C55A2A6C12C@llvm.org>
	<BANLkTikKRqU-WxPwbDvwRB8xn74_qdPd-3iv+bK1qsz_NRFJRQ@mail.gmail.com>
Message-ID: <FC96B463-E9D5-4B7C-A946-AF8620E3405A@apple.com>

Huh. Must be a difference in underlying headers on my system or something. Sorry for the breakage. Fixed in 133640.
-Jim
On Jun 22, 2011, at 1:40 PM, Nick Lewycky wrote:

> Hi Jim,
> 
> ARMMachObjectWriter is missing #include "llvm/Support/DataTypes.h" for uint32_t!
> 
> llvm[3]: Compiling ARMISelDAGToDAG.cpp for Debug+Asserts build
> In file included from ARMAsmBackend.cpp:10:
> ARM.h:65: error: ?uint32_t? has not been declared
> ARM.h:66: error: ?uint32_t? has not been declared
> In file included from ARMBaseRegisterInfo.cpp:14:
> ARM.h:65: error: ?uint32_t? has not been declared
> ARM.h:66: error: ?uint32_t? has not been declared
> In file included from ARMExpandPseudoInsts.cpp:18:
> ARM.h:65: error: ?uint32_t? has not been declared
> ARM.h:66: error: ?uint32_t? has not been declared
> In file included from ARMConstantIslandPass.cpp:17:
> ARM.h:65: error: ?uint32_t? has not been declared
> ARM.h:66: error: ?uint32_t? has not been declared
> [...]
> 
> Nick
> 
> On 22 June 2011 13:14, Jim Grosbach <grosbach at apple.com> wrote:
> Author: grosbach
> Date: Wed Jun 22 15:14:52 2011
> New Revision: 133638
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133638&view=rev
> Log:
> Move ARMMachObjectWriter to its own file.
> 
> Just tidy up a bit. No functional change.
> 
> Added:
>    llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp
> Modified:
>    llvm/trunk/lib/Target/ARM/ARM.h
>    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
>    llvm/trunk/lib/Target/ARM/CMakeLists.txt
> 
> Modified: llvm/trunk/lib/Target/ARM/ARM.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.h?rev=133638&r1=133637&r2=133638&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARM.h (original)
> +++ llvm/trunk/lib/Target/ARM/ARM.h Wed Jun 22 15:14:52 2011
> @@ -27,6 +27,7 @@
>  class JITCodeEmitter;
>  class formatted_raw_ostream;
>  class MCCodeEmitter;
> +class MCObjectWriter;
>  class TargetAsmBackend;
>  class MachineInstr;
>  class ARMAsmPrinter;
> @@ -58,6 +59,12 @@
>  void LowerARMMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
>                                   ARMAsmPrinter &AP);
> 
> +/// createARMMachObjectWriter - Construct an ARM Mach-O object writer.
> +MCObjectWriter *createARMMachObjectWriter(raw_ostream &OS,
> +                                          bool Is64Bit,
> +                                          uint32_t CPUType,
> +                                          uint32_t CPUSubtype);
> +
>  } // end namespace llvm;
> 
>  #endif
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=133638&r1=133637&r2=133638&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Wed Jun 22 15:14:52 2011
> @@ -28,14 +28,6 @@
>  using namespace llvm;
> 
>  namespace {
> -class ARMMachObjectWriter : public MCMachObjectTargetWriter {
> -public:
> -  ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
> -                      uint32_t CPUSubtype)
> -    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
> -                               /*UseAggressiveSymbolFolding=*/true) {}
> -};
> -
>  class ARMELFObjectWriter : public MCELFObjectTargetWriter {
>  public:
>   ARMELFObjectWriter(Triple::OSType OSType)
> @@ -423,12 +415,9 @@
>     : ARMAsmBackend(T), Subtype(st) { }
> 
>   MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
> -    return createMachObjectWriter(new ARMMachObjectWriter(
> -                                    /*Is64Bit=*/false,
> -                                    object::mach::CTM_ARM,
> -                                    Subtype),
> -                                  OS,
> -                                  /*IsLittleEndian=*/true);
> +    return createARMMachObjectWriter(OS, /*Is64Bit=*/false,
> +                                     object::mach::CTM_ARM,
> +                                     Subtype);
>   }
> 
>   void ApplyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
> 
> Added: llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp?rev=133638&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp (added)
> +++ llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp Wed Jun 22 15:14:52 2011
> @@ -0,0 +1,32 @@
> +//===-- ARMMachObjectWriter.cpp - ARM Mach Object Writer ------------------===//
> +//
> +//                     The LLVM Compiler Infrastructure
> +//
> +// This file is distributed under the University of Illinois Open Source
> +// License. See LICENSE.TXT for details.
> +//
> +//===----------------------------------------------------------------------===//
> +
> +#include "ARM.h"
> +#include "llvm/MC/MCMachObjectWriter.h"
> +using namespace llvm;
> +
> +namespace {
> +class ARMMachObjectWriter : public MCMachObjectTargetWriter {
> +public:
> +  ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
> +                      uint32_t CPUSubtype)
> +    : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
> +                               /*UseAggressiveSymbolFolding=*/true) {}
> +};
> +}
> +
> +MCObjectWriter *llvm::createARMMachObjectWriter(raw_ostream &OS,
> +                                                bool Is64Bit,
> +                                                uint32_t CPUType,
> +                                                uint32_t CPUSubtype) {
> +  return createMachObjectWriter(new ARMMachObjectWriter(Is64Bit,
> +                                                        CPUType,
> +                                                        CPUSubtype),
> +                                OS, /*IsLittleEndian=*/true);
> +}
> 
> Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=133638&r1=133637&r2=133638&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Wed Jun 22 15:14:52 2011
> @@ -34,6 +34,7 @@
>   ARMISelLowering.cpp
>   ARMInstrInfo.cpp
>   ARMJITInfo.cpp
> +  ARMMachObjectWriter.cpp
>   ARMMCCodeEmitter.cpp
>   ARMMCExpr.cpp
>   ARMLoadStoreOptimizer.cpp
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 



From daniel at zuster.org  Wed Jun 22 15:41:53 2011
From: daniel at zuster.org (Daniel Dunbar)
Date: Wed, 22 Jun 2011 20:41:53 -0000
Subject: [llvm-commits] [llvm] r133641 - /llvm/trunk/test/Unit/lit.cfg
Message-ID: <20110622204153.802F72A6C12C@llvm.org>

Author: ddunbar
Date: Wed Jun 22 15:41:53 2011
New Revision: 133641

URL: http://llvm.org/viewvc/llvm-project?rev=133641&view=rev
Log:
test/Unit: Fix enable shared test to follow check that we have actually loaded
the site config.

Modified:
    llvm/trunk/test/Unit/lit.cfg

Modified: llvm/trunk/test/Unit/lit.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Unit/lit.cfg?rev=133641&r1=133640&r2=133641&view=diff
==============================================================================
--- llvm/trunk/test/Unit/lit.cfg (original)
+++ llvm/trunk/test/Unit/lit.cfg Wed Jun 22 15:41:53 2011
@@ -30,14 +30,6 @@
 
 ###
 
-# If necessary, point the dynamic loader at libLLVM.so.
-if config.enable_shared:
-    shlibpath = config.environment.get(config.shlibpath_var,'')
-    if shlibpath:
-        shlibpath = os.pathsep + shlibpath
-    shlibpath = config.shlibdir + shlibpath
-    config.environment[config.shlibpath_var] = shlibpath
-
 # Check that the object root is known.
 if config.test_exec_root is None:
     # Otherwise, we haven't loaded the site specific configuration (the user is
@@ -81,3 +73,11 @@
     lit.note('using out-of-tree build at %r' % llvm_obj_root)
     lit.load_config(config, site_cfg)
     raise SystemExit
+
+# If necessary, point the dynamic loader at libLLVM.so.
+if config.enable_shared:
+    shlibpath = config.environment.get(config.shlibpath_var,'')
+    if shlibpath:
+        shlibpath = os.pathsep + shlibpath
+    shlibpath = config.shlibdir + shlibpath
+    config.environment[config.shlibpath_var] = shlibpath



From dpatel at apple.com  Wed Jun 22 15:56:56 2011
From: dpatel at apple.com (Devang Patel)
Date: Wed, 22 Jun 2011 20:56:56 -0000
Subject: [llvm-commits] [llvm] r133642 -
	/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
Message-ID: <20110622205656.816062A6C12C@llvm.org>

Author: dpatel
Date: Wed Jun 22 15:56:56 2011
New Revision: 133642

URL: http://llvm.org/viewvc/llvm-project?rev=133642&view=rev
Log:
New binops need debug loc.

Modified:
    llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp

Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=133642&r1=133641&r2=133642&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original)
+++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Wed Jun 22 15:56:56 2011
@@ -159,7 +159,8 @@
   }
 
   // If we haven't found this binop, insert it.
-  Value *BO = Builder.CreateBinOp(Opcode, LHS, RHS, "tmp");
+  Instruction *BO = cast<Instruction>(Builder.CreateBinOp(Opcode, LHS, RHS, "tmp"));
+  BO->setDebugLoc(SaveInsertPt->getDebugLoc());
   rememberInstruction(BO);
 
   // Restore the original insert point.
@@ -1155,6 +1156,7 @@
         Instruction *Add = BinaryOperator::CreateAdd(CanonicalIV, One,
                                                      "indvar.next",
                                                      HP->getTerminator());
+        Add->setDebugLoc(HP->getTerminator()->getDebugLoc());
         rememberInstruction(Add);
         CanonicalIV->addIncoming(Add, HP);
       } else {



From aggarwa4 at illinois.edu  Wed Jun 22 15:57:15 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Wed, 22 Jun 2011 20:57:15 -0000
Subject: [llvm-commits] [poolalloc] r133643 - in /poolalloc/trunk:
 include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp
 lib/AssistDS/TypeChecksOpt.cpp runtime/DynamicTypeChecks/Makefile
 runtime/DynamicTypeChecks/TypeRuntime.c
 runtime/DynamicTypeChecks/TypeRuntime.cpp
Message-ID: <20110622205715.47D362A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Jun 22 15:57:15 2011
New Revision: 133643

URL: http://llvm.org/viewvc/llvm-project?rev=133643&view=rev
Log:
Modify handling of va lists. Store the metadata(total
arguments, metadata for each, and number read) in 
a map in memory, instead of in SSA values. This makes
the handling much easier.

Also clean up a lot of dead code, caused by this and the
previous changes.


Added:
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
Removed:
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c
Modified:
    poolalloc/trunk/include/assistDS/TypeChecks.h
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
    poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
    poolalloc/trunk/runtime/DynamicTypeChecks/Makefile

Modified: poolalloc/trunk/include/assistDS/TypeChecks.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=133643&r1=133642&r2=133643&view=diff
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecks.h (original)
+++ poolalloc/trunk/include/assistDS/TypeChecks.h Wed Jun 22 15:57:15 2011
@@ -34,15 +34,11 @@
 class TypeChecks : public ModulePass {
 private:
   std::map<const Type *, unsigned int> UsedTypes;
-  std::map<Function *, Function *> VAListFunctionsMap;
   std::map<Function *, Function *> IndFunctionsMap;
   std::list<Function *> VAArgFunctions;
-  std::list<Function *> VAListFunctions;
   std::list<Function *> ByValFunctions;
   std::list<Function *> AddressTakenFunctions;
   std::set<Instruction*> IndCalls;
-  // Map of VAList to current count
-  std::map<Value*, Value*> CounterMap;
 
   // Analysis from other passes.
   TargetData *TD;
@@ -68,6 +64,7 @@
   bool visitLoadInst(Module &M, LoadInst &LI);
   bool visitStoreInst(Module &M, StoreInst &SI);
   bool visitAllocaInst(Module &M, AllocaInst &AI);
+  bool visitVAArgInst(Module &M, VAArgInst &VI);
 
   bool visitGlobal(Module &M, GlobalVariable &GV, 
                    Constant *C, Instruction &I, SmallVector<Value*,8>);
@@ -80,8 +77,6 @@
 
 
   bool visitVarArgFunction(Module &M, Function &F); 
-  bool visitVAListFunction(Module &M, Function &F); 
-  void visitVAListCall(Function *F);
   bool visitInternalVarArgFunction(Module &M, Function &F); 
 
   bool visitInputFunctionValue(Module &M, Value *V, Instruction *CI);

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133643&r1=133642&r2=133643&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Wed Jun 22 15:57:15 2011
@@ -60,19 +60,28 @@
 static const Type *Int32Ty = 0;
 static const Type *Int64Ty = 0;
 static const PointerType *VoidPtrTy = 0;
+static Constant *One = 0;
+static Constant *Zero = 0;
+static Constant *RegisterArgv;
+static Constant *RegisterEnvp;
+
 static Constant *trackGlobal;
+static Constant *trackStoreInst;
 static Constant *trackStringInput;
 static Constant *trackArray;
+
 static Constant *trackInitInst;
 static Constant *trackUnInitInst;
-static Constant *trackStoreInst;
+
+static Constant *getTypeTag;
 static Constant *checkTypeInst;
+
 static Constant *copyTypeInfo;
 static Constant *setTypeInfo;
-static Constant *RegisterArgv;
-static Constant *RegisterEnvp;
-static Constant *compareTypeAndNumber;
-static Constant *getTypeTag;
+
+static Constant *setVAInfo;
+static Constant *copyVAInfo;
+static Constant *checkVAArg;
 
 unsigned int TypeChecks::getTypeMarker(const Type * Ty) {
   if(DisablePointerTypeChecks) {
@@ -122,6 +131,8 @@
   Int32Ty = IntegerType::getInt32Ty(M.getContext());
   Int64Ty = IntegerType::getInt64Ty(M.getContext());
   VoidPtrTy = PointerType::getUnqual(Int8Ty);
+  One = ConstantInt::get(Int64Ty, 1);
+  Zero = ConstantInt::get(Int64Ty, 0);
 
   RegisterArgv = M.getOrInsertFunction("trackArgvType",
                                        VoidTy,
@@ -193,22 +204,33 @@
                                        Int64Ty,/*size*/
                                        Int32Ty,/*tag*/
                                        NULL);
-  compareTypeAndNumber = M.getOrInsertFunction("compareTypeAndNumber",
-                                               VoidTy,
-                                               Int64Ty,/*Total Args*/
-                                               Int64Ty,/*Arg accessed*/
-                                               Int8Ty,/*type*/
-                                               VoidPtrTy,/*metadata ptr*/
-                                               Int32Ty,/*tag*/
-                                               NULL);
   trackStringInput = M.getOrInsertFunction("trackStringInput",
                                            VoidTy,
                                            VoidPtrTy,
                                            Int32Ty,
                                            NULL);
+  setVAInfo = M.getOrInsertFunction("setVAInfo",
+                                    VoidTy,
+                                    VoidPtrTy,/*va_list ptr*/
+                                    Int64Ty,/*total num of elements in va_list */
+                                    VoidPtrTy,/*ptr to metadta*/
+                                    Int32Ty,/*tag*/
+                                    NULL);
+  copyVAInfo = M.getOrInsertFunction("copyVAInfo",
+                                     VoidTy,
+                                     VoidPtrTy,/*dst va_list*/
+                                     VoidPtrTy,/*src va_list */
+                                     Int32Ty,/*tag*/
+                                     NULL);
+  checkVAArg = M.getOrInsertFunction("checkVAArgType",
+                                     VoidTy,
+                                     VoidPtrTy,/*va_list ptr*/
+                                     Int8Ty,/*type*/
+                                     Int32Ty,/*tag*/
+                                     NULL);
+
 
   UsedTypes.clear(); // Reset if run multiple times.
-  VAListFunctions.clear();
   VAArgFunctions.clear();
   ByValFunctions.clear();
   AddressTakenFunctions.clear();
@@ -258,23 +280,6 @@
       VAArgFunctions.push_back(&F);
       continue;
     }
-    // Iterate and find all VAList functions
-    bool isVAListFunc = false;
-    const Type *ListType  = M.getTypeByName("struct.__va_list_tag");
-    if(!ListType)
-      continue;
-
-    const Type *ListPtrType = ListType->getPointerTo();
-    for (Function::arg_iterator I = F.arg_begin(); I != F.arg_end(); ++I) {
-      if(I->getType() == ListPtrType) {
-        isVAListFunc = true;
-        break;
-      }
-    }
-    if(isVAListFunc) {
-      VAListFunctions.push_back(&F);
-      continue;
-    }
   }
 
   // Modify all byval functions
@@ -285,21 +290,6 @@
   }
 
 
-  // NOTE:must visit before VAArgFunctions, to populate the map with the
-  // correct cloned functions.
-  while(!VAListFunctions.empty()) {
-    Function *F = VAListFunctions.back();
-    VAListFunctions.pop_back();
-    modified |= visitVAListFunction(M, *F);
-  }
-
-  // iterate through all the VAList funtions and modify call sites
-  // to call the new function 
-  std::map<Function *, Function *>::iterator FI = VAListFunctionsMap.begin(), 
-    FE = VAListFunctionsMap.end();
-  for(; FI != FE; FI++) {
-    visitVAListCall(FI->second);
-  }
   while(!VAArgFunctions.empty()) {
     Function *F = VAArgFunctions.back();
     VAArgFunctions.pop_back();
@@ -335,6 +325,8 @@
         modified |= visitInvokeInst(M, *II);
       } else if (AllocaInst *AI = dyn_cast<AllocaInst>(&I)) {
         modified |= visitAllocaInst(M, *AI);
+      } else if (VAArgInst *VI = dyn_cast<VAArgInst>(&I)) {
+        modified |= visitVAArgInst(M, *VI);
       }
     }
   }
@@ -347,7 +339,7 @@
     modified |= visitIndirectCallSite(M,I);
   }
 
-  FI = IndFunctionsMap.begin(), FE = IndFunctionsMap.end();
+  std::map<Function *, Function * >::iterator FI = IndFunctionsMap.begin(), FE = IndFunctionsMap.end();
   for(;FI!=FE;++FI) {
     Function *F = FI->first;
 
@@ -475,211 +467,6 @@
                     );
 }
 
-void TypeChecks::visitVAListCall(Function *F) {
-  for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
-    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
-      CallInst *CI = dyn_cast<CallInst>(I++);
-      if(!CI)
-        continue;
-      Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
-      if(VAListFunctionsMap.find(CalledF) == VAListFunctionsMap.end())
-        continue;
-      const Type *ListType  = F->getParent()->getTypeByName("struct.__va_list_tag");
-      const Type *ListPtrType = ListType->getPointerTo();
-      unsigned VAListArgNum = 0;
-      for (Function::arg_iterator I = CalledF->arg_begin(); 
-           I != CalledF->arg_end(); ++I) {
-        VAListArgNum ++;
-        if(I->getType() == ListPtrType) {
-          break;
-        }
-      }
-
-      if(CounterMap.find(CI->getOperand(VAListArgNum)->stripPointerCasts()) == CounterMap.end()) {
-        // If this is a va_list we do not know about,
-        // do not insert checks.
-
-        // FIXME: Handle cases where va_list is stored in memory
-         continue;
-      }
-      Function::arg_iterator NII = F->arg_begin();
-      std::vector<Value *>Args;
-      Args.push_back(NII++); // total count
-      Value *CounterSrc = CounterMap[CI->getOperand(VAListArgNum)->stripPointerCasts()];
-      LoadInst *CountValue = new LoadInst(CounterSrc, "count", CI);
-      Args.push_back(CountValue); // current count
-      NII++;
-      Args.push_back(NII); // MD
-      for(unsigned i = 1 ;i < CI->getNumOperands(); i++) {
-        // Add the original argument
-        Args.push_back(CI->getOperand(i));
-      }
-      CallInst *CINew = CallInst::Create(VAListFunctionsMap[CalledF], 
-                                         Args.begin(), 
-                                         Args.end(),
-                                         "", CI);
-      CI->replaceAllUsesWith(CINew);
-      CI->eraseFromParent();
-    }
-  }
-}
-
-bool TypeChecks::visitVAListFunction(Module &M, Function &F_orig) {
-  if(!F_orig.hasInternalLinkage())
-    return false;
-
-  int VAListArgNum = 0;
-  // Check if one of the arguments is a va_list
-  const Type *ListType  = M.getTypeByName("struct.__va_list_tag");
-  if(!ListType)
-    return false;
-  const Type *ListPtrType = ListType->getPointerTo();
-  Argument *VAListArg = NULL; 
-  for (Function::arg_iterator I = F_orig.arg_begin(); 
-       I != F_orig.arg_end(); ++I) {
-    VAListArgNum ++;
-    if(I->getType() == ListPtrType) {
-      VAListArg = I;
-      break;
-    }
-  }
-
-  // Clone the function to add arguments for count, MD
-
-  // 1. Create the new argument types vector
-  std::vector<const Type*>TP;
-  TP.push_back(Int64Ty); // for count
-  TP.push_back(Int64Ty); // for count
-  TP.push_back(VoidPtrTy); // for MD
-  for (Function::arg_iterator I = F_orig.arg_begin();
-       I != F_orig.arg_end(); ++I) {
-    TP.push_back(I->getType());
-  }
-  // 2. Create the new function prototype
-  const FunctionType *NewFTy = FunctionType::get(F_orig.getReturnType(),
-                                                 TP,/*argument types*/
-                                                 false);/*vararg*/
-  Function *F = Function::Create(NewFTy,
-                                 GlobalValue::InternalLinkage,
-                                 F_orig.getNameStr() + ".INT",
-                                 &M);
-
-  // 3. Set the mapping for args
-  Function::arg_iterator NI = F->arg_begin();
-  DenseMap<const Value*, Value*> ValueMap;
-  NI->setName("TotalCount");
-  NI++;
-  NI->setName("CurrentCount");
-  NI++;
-  NI->setName("MD");
-  NI++;
-  for (Function::arg_iterator II = F_orig.arg_begin(); 
-       NI != F->arg_end(); ++II, ++NI) {
-    // Each new argument maps to the argument in the old function
-    // For these arguments, also copy over the attributes
-    ValueMap[II] = NI;
-    NI->setName(II->getName());
-    NI->addAttr(F_orig.getAttributes()
-                .getParamAttributes(II->getArgNo() + 1));
-  }
-
-  // 4. Copy over the attributes for the function.
-  F->setAttributes(F->getAttributes()
-                   .addAttr(0, F_orig.getAttributes().getRetAttributes()));
-  F->setAttributes(F->getAttributes()
-                   .addAttr(~0, F_orig.getAttributes().getFnAttributes()));
-
-  // 5. Perform the cloning.
-  SmallVector<ReturnInst*,100> Returns;
-  CloneFunctionInto(F, &F_orig, ValueMap, Returns);
-
-  VAListFunctionsMap[&F_orig] =  F;
-  inst_iterator InsPt = inst_begin(F);
-
-
-  // Store the information
-  Function::arg_iterator NII = F->arg_begin();
-  AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt);
-  new StoreInst(NII, VASizeLoc, &*InsPt);
-  NII++;
-  AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt);
-  new StoreInst(NII, Counter, &*InsPt); 
-  errs() << F->getNameStr() <<"\n";
-  NII++;
-  AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt);
-  new StoreInst(NII, VAMDLoc, &*InsPt);
-
-  CounterMap[ValueMap[VAListArg]] = Counter;
-  // Find all va_copy calls
-  for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
-    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;I++) {
-      CallInst *CI = dyn_cast<CallInst>(I);
-      if(!CI)
-        continue;
-      Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
-      if(!CalledF)
-        continue;
-      if(!CalledF->isIntrinsic())
-        continue;
-      if(CalledF->getIntrinsicID() != Intrinsic::vacopy) 
-        continue;
-      if(CounterMap.find(CI->getOperand(2)->stripPointerCasts()) == CounterMap.end()) {
-        // If this is a va_list we do not know about,
-        // do not insert checks.
-
-        // FIXME: Handle cases where va_list is stored in memory
-         continue;
-      }
-      // Reinitialize the counter
-      AllocaInst *CounterDest = new AllocaInst(Int64Ty, "",&*InsPt);
-      Value *CounterSource = CounterMap[CI->getOperand(2)->stripPointerCasts()];
-      LoadInst *CurrentValue = new LoadInst(CounterSource, "count", CI);
-      new StoreInst(CurrentValue, CounterDest, CI);
-      CounterMap[CI->getOperand(1)->stripPointerCasts()] = CounterDest;
-    }
-  }
-
-
-  // instrument va_arg to increment the counter
-  for (Function::iterator B = F->begin(), FE = F->end(); B != FE; ++B) {
-    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
-      VAArgInst *VI = dyn_cast<VAArgInst>(I++);
-      if(!VI)
-        continue;
-      if(CounterMap.find(VI->getOperand(0)->stripPointerCasts()) == CounterMap.end()) {
-        // If this is a va_list we do not know about,
-        // do not insert checks.
-
-        // FIXME: Handle cases where va_list is stored in memory
-         continue;
-      }
-      Constant *One = ConstantInt::get(Int64Ty, 1);
-      Value *CounterSrc = CounterMap[VI->getOperand(0)->stripPointerCasts()];
-      LoadInst *OldValue = new LoadInst(CounterSrc, "count", VI);
-      Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add,
-                                                     OldValue,
-                                                     One,
-                                                     "count",
-                                                     VI);
-      new StoreInst(NewValue, CounterSrc, VI);
-      std::vector<Value *> Args;
-      Instruction *VASize = new LoadInst(VASizeLoc, "", VI);
-      Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI);
-      Args.push_back(VASize);
-      Args.push_back(OldValue);
-      Args.push_back(getTypeMarkerConstant(VI));
-      Args.push_back(VAMetaData);
-      Args.push_back(getTagCounter());
-      CallInst::Create(compareTypeAndNumber,
-                       Args.begin(),
-                       Args.end(),
-                       "", VI);
-    }
-  }
-
-  return true;
-}
-
 bool TypeChecks::visitAddressTakenFunction(Module &M, Function &F) {
   // Clone function
   // 1. Create the new argument types vector
@@ -823,13 +610,13 @@
                                                  true);
   Function *NewF = Function::Create(NewFTy,
                                     GlobalValue::InternalLinkage,
-                                    F.getNameStr() + ".mod",
+                                    F.getNameStr() + ".vararg",
                                     &M);
 
   // 3. Set the mapping for the args
   Function::arg_iterator NI = NewF->arg_begin();
   DenseMap<const Value *, Value*> ValueMap;
-  NI->setName("TotalCount");
+  NI->setName("TotalArgCount");
   NI++;
   NI->setName("MD");
   NI++;
@@ -856,7 +643,6 @@
   // Store the information
   inst_iterator InsPt = inst_begin(NewF);
   Function::arg_iterator NII = NewF->arg_begin();
-  AllocaInst *VASizeLoc = new AllocaInst(Int64Ty, "", &*InsPt);
   // Subtract the number of initial arguments
   Constant *InitialArgs = ConstantInt::get(Int64Ty, F.arg_size());
   Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Sub,
@@ -864,10 +650,8 @@
                                                  InitialArgs,
                                                  "varargs",
                                                  &*InsPt);
-  new StoreInst(NewValue, VASizeLoc, &*InsPt);
   NII++;
 
-  AllocaInst *VAMDLoc = new AllocaInst(VoidPtrTy, "", &*InsPt);
   // Increment by the number of Initial Args, so as to not read the metadata
   //for those.
   Value *Idx[2];
@@ -877,12 +661,6 @@
                                                              Idx, 
                                                              Idx + 1, 
                                                              "", &*InsPt);
-  new StoreInst(GEP, VAMDLoc, &*InsPt);
-  // Add a counter variable to the function entry
-  AllocaInst *Counter = new AllocaInst(Int64Ty, "",&*InsPt);
-  new StoreInst(ConstantInt::get(Int64Ty, 0), Counter, &*InsPt); 
-
-
   // visit all VAStarts and initialize the counter
   for (Function::iterator B = NewF->begin(), FE = NewF->end(); B != FE; ++B) {
     for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;I++) {
@@ -897,9 +675,13 @@
       if(CalledF->getIntrinsicID() != Intrinsic::vastart) 
         continue;
       // Reinitialize the counter
-      StoreInst *SI3 = new StoreInst(ConstantInt::get(Int64Ty, 0), Counter);
-      SI3->insertAfter(CI);
-      CounterMap[CI->getOperand(1)->stripPointerCasts()] = Counter;
+      CastInst *BCI = BitCastInst::CreatePointerCast(CI->getOperand(1), VoidPtrTy, "", CI);
+      std::vector<Value *> Args;
+      Args.push_back(BCI);
+      Args.push_back(NewValue);
+      Args.push_back(GEP);
+      Args.push_back(getTagCounter());
+      CallInst::Create(setVAInfo, Args.begin(), Args.end(), "", CI);
     }
   }
 
@@ -916,93 +698,13 @@
         continue;
       if(CalledF->getIntrinsicID() != Intrinsic::vacopy) 
         continue;
-      // Reinitialize the counter
-      AllocaInst *CounterDest = new AllocaInst(Int64Ty, "",&*InsPt);
-      Value *CounterSource = CounterMap[CI->getOperand(2)->stripPointerCasts()];
-      LoadInst *CurrentValue = new LoadInst(CounterSource, "count", CI);
-      new StoreInst(CurrentValue, CounterDest, CI);
-      CounterMap[CI->getOperand(1)->stripPointerCasts()] = CounterDest;
-    }
-  }
-
-  // Modify function to add checks on every var_arg call to ensure that we
-  // are not accessing more arguments than we passed in.
-
-  // Increment the counter
-  for (Function::iterator B = NewF->begin(), FE = NewF->end(); B != FE; ++B) {
-    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
-      VAArgInst *VI = dyn_cast<VAArgInst>(I++);
-      if(!VI)
-        continue;
-      if(CounterMap.find(VI->getOperand(0)->stripPointerCasts()) == CounterMap.end()) {
-        // If this is a va_list we do not know about,
-        // do not insert checks.
-
-        // FIXME: Handle cases where va_list is stored in memory
-         continue;
-      }
-      Constant *One = ConstantInt::get(Int64Ty, 1);
-      Value *CounterSrc = CounterMap[VI->getOperand(0)->stripPointerCasts()];
-      LoadInst *OldValue = new LoadInst(CounterSrc, "count", VI);
-      Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add,
-                                                     OldValue,
-                                                     One,
-                                                     "count",
-                                                     VI);
-      new StoreInst(NewValue, CounterSrc, VI);
+      CastInst *BCI_Src = BitCastInst::CreatePointerCast(CI->getOperand(2), VoidPtrTy, "", CI);
+      CastInst *BCI_Dest = BitCastInst::CreatePointerCast(CI->getOperand(1), VoidPtrTy, "", CI);
       std::vector<Value *> Args;
-      Instruction *VASize = new LoadInst(VASizeLoc, "", VI);
-      Instruction *VAMetaData = new LoadInst(VAMDLoc, "", VI);
-      Args.push_back(VASize);
-      Args.push_back(OldValue);
-      Args.push_back(getTypeMarkerConstant(VI));
-      Args.push_back(VAMetaData);
+      Args.push_back(BCI_Dest);
+      Args.push_back(BCI_Src);
       Args.push_back(getTagCounter());
-      CallInst::Create(compareTypeAndNumber,
-                       Args.begin(),
-                       Args.end(),
-                       "", VI);
-    }
-  }
-
-
-  // modify calls to va list functions to pass the metadata
-  for (Function::iterator B = NewF->begin(), FE = NewF->end(); B != FE; ++B) {
-    for (BasicBlock::iterator I = B->begin(), BE = B->end(); I != BE;) {
-      CallInst *CI = dyn_cast<CallInst>(I++);
-      if(!CI)
-        continue;
-      Function *CalledF = dyn_cast<Function>(CI->getCalledFunction());
-
-      if(VAListFunctionsMap.find(CalledF) == VAListFunctionsMap.end())
-        continue;
-      const Type *ListType  = M.getTypeByName("struct.__va_list_tag");
-      const Type *ListPtrType = ListType->getPointerTo();
-      unsigned VAListArgNum = 0;
-      for (Function::arg_iterator I = CalledF->arg_begin(); 
-           I != CalledF->arg_end(); ++I) {
-        VAListArgNum ++;
-        if(I->getType() == ListPtrType) {
-          break;
-        }
-      }
-      std::vector<Value *>Args;
-
-      Value *CounterSrc = CounterMap[CI->getOperand(VAListArgNum)->stripPointerCasts()];
-      Instruction *VASize = new LoadInst(VASizeLoc, "", CI);
-      Instruction *VACounter = new LoadInst(CounterSrc, "", CI);
-      Instruction *VAMetaData = new LoadInst(VAMDLoc, "", CI);
-      Args.push_back(VASize); // toatl count
-      Args.push_back(VACounter); // current count
-      Args.push_back(VAMetaData); // MD
-      for(unsigned i = 1 ;i < CI->getNumOperands(); i++) {
-        // Add the original argument
-        Args.push_back(CI->getOperand(i));
-      }
-      CallInst *CINew = CallInst::Create(VAListFunctionsMap[CalledF], 
-                                         Args.begin(), Args.end(), "", CI);
-      CI->replaceAllUsesWith(CINew);
-      CI->eraseFromParent();
+      CallInst::Create(copyVAInfo, Args.begin(), Args.end(), "", CI);
     }
   }
 
@@ -1357,7 +1059,7 @@
     if(!I->hasInitializer())
       continue;
     SmallVector<Value*,8>index;
-    index.push_back(ConstantInt::get(Int64Ty, 0));
+    index.push_back(Zero);
     visitGlobal(M, *I, I->getInitializer(), *InsertPt, index);
   }
   //
@@ -1538,6 +1240,17 @@
   }
   return true;
 }
+bool TypeChecks::visitVAArgInst(Module &M, VAArgInst &VI) {
+  if(!VI.getParent()->getParent()->hasInternalLinkage())
+    return false;
+  CastInst *BCI = BitCastInst::CreatePointerCast(VI.getOperand(0), VoidPtrTy, "", &VI);
+  std::vector<Value *>Args;
+  Args.push_back(BCI);
+  Args.push_back(getTypeMarkerConstant(&VI));
+  Args.push_back(getTagCounter());
+  CallInst::Create(checkVAArg, Args.begin(), Args.end(), "", &VI);
+  return false;
+}
 
 // Insert code to initialize meta data to bottom
 // Insert code to set objects to 0
@@ -1880,7 +1593,6 @@
       Args.push_back(BCI);
       CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false);
       Size->insertAfter(I);
-      Constant *One = ConstantInt::get(Int64Ty, 1);
       Instruction *NewValue = BinaryOperator::Create(BinaryOperator::Add,
                                                      Size,
                                                      One);
@@ -2112,4 +1824,3 @@
 
   return true;
 }
-

Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=133643&r1=133642&r2=133643&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Wed Jun 22 15:57:15 2011
@@ -43,7 +43,6 @@
 static const PointerType *VoidPtrTy = 0;
 static Constant *trackGlobal;
 static Constant *trackStringInput;
-static Constant *trackArray;
 static Constant *trackInitInst;
 static Constant *trackUnInitInst;
 static Constant *trackStoreInst;
@@ -51,7 +50,6 @@
 static Constant *setTypeInfo;
 static Constant *checkTypeInst;
 static Constant *MallocFunc;
-static Constant *getTypeTag;
 
 bool TypeChecksOpt::runOnModule(Module &M) {
   TS = &getAnalysis<dsa::TypeSafety<TDDataStructures> >();
@@ -63,12 +61,6 @@
   Int64Ty = IntegerType::getInt64Ty(M.getContext());
   VoidPtrTy = PointerType::getUnqual(Int8Ty);
 
-  getTypeTag = M.getOrInsertFunction("getTypeTag",
-                                     VoidTy,
-                                     VoidPtrTy, /*ptr*/
-                                     Int64Ty, /*size*/
-                                     VoidPtrTy, /*dest for type tag*/
-                                     NULL);
   trackGlobal = M.getOrInsertFunction("trackGlobal",
                                       VoidTy,
                                       VoidPtrTy,/*ptr*/
@@ -76,13 +68,6 @@
                                       Int64Ty,/*size*/
                                       Int32Ty,/*tag*/
                                       NULL);
-  trackArray = M.getOrInsertFunction("trackArray",
-                                     VoidTy,
-                                     VoidPtrTy,/*ptr*/
-                                     Int64Ty,/*size*/
-                                     Int64Ty,/*count*/
-                                     Int32Ty,/*tag*/
-                                     NULL);
   trackInitInst = M.getOrInsertFunction("trackInitInst",
                                         VoidTy,
                                         VoidPtrTy,/*ptr*/

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/Makefile?rev=133643&r1=133642&r2=133643&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/Makefile (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/Makefile Wed Jun 22 15:57:15 2011
@@ -8,6 +8,10 @@
 endif
 endif
 
+ifdef ENABLE_OPTIMIZED
+CXXFLAGS += -DNDEBUG=1
+endif
+
 include $(LEVEL)/Makefile.common
 
 # Always build optimized and debug versions

Removed: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c?rev=133642&view=auto
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.c (removed)
@@ -1,303 +0,0 @@
-#include <assert.h>
-#include <inttypes.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <netdb.h>
-#include <poll.h>
-#include <sys/types.h>
-#include <sys/socket.h>
-#include <sys/mman.h>
-
-#define DEBUG (0)
-
-/* Size of shadow memory.  We're hoping everything fits in 46bits. */
-#define SIZE ((size_t)(1L << 46))
-
-/* Fixed start of memory.  Needs to be page-aligned,
- * and it needs to be large enough that program itself is loaded below it
- * and so are the libraries. 
- * FIXME: This address has been picked for maute. Might not work on other
- * machines. Need a more robust way of picking base address.
- * For now, run a version of the tool without the base fixed, and 
- * choose address.
- #define BASE ((void *)(0x2aaaab2a5000))
- */
-#define BASE ((void *)(0x2aaaab88c000))
-/*
- * Do some macro magic to get mmap macros defined properly on all platforms.
- */
-#if defined(MAP_ANON) && !defined(MAP_ANONYMOUS)
-# define MAP_ANONYMOUS MAP_ANON
-#endif /* defined(MAP_ANON) && !defined(MAP_ANONYMOUS) */
-
-uint8_t * const shadow_begin = BASE;
-
-extern char* typeNames[];
-
-void trackInitInst(void *ptr, uint64_t size, uint32_t tag);
-
-inline uintptr_t maskAddress(void *ptr) {
-  uintptr_t p = (uintptr_t)ptr;
-  if (p >= (uintptr_t)BASE + SIZE) p -= SIZE;
-
-#if DEBUG
-  assert(p <= SIZE && "Pointer out of range!");
-#endif
-  return p;
-}
-
-
-void trackStringInput(void *ptr, uint32_t tag) {
-  trackInitInst(ptr, strlen(ptr) + 1, tag);
-}
-
-
-/**
- * Initialize the shadow memory which records the 1:1 mapping of addresses to types.
- */
-void shadowInit() {
-  char * res = mmap(BASE, SIZE, PROT_READ | PROT_WRITE, MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS | MAP_NORESERVE, -1, 0);
-
-  if (res == MAP_FAILED) {
-    fprintf(stderr, "Failed to map the shadow memory!\n");
-    fflush(stderr);
-    assert(0 && "MAP_FAILED");
-  }
-}
-
-/**
- * Copy arguments into a new array, and initialize
- * metadata for that location to TOP/initialized.
- */
-void trackArgvType(int argc, char **argv) {
-  int index = 0;
-  for (; index < argc; ++index) {
-    trackInitInst(argv[index], (strlen(argv[index]) + 1)*sizeof(char), 0);
-  }
-  trackInitInst(argv, (argc + 1)*sizeof(char*), 0);
-}
-
-void trackEnvpType(char **envp) {
-  int index = 0;
-  for(;envp[index] != NULL; ++index)
-    trackInitInst(envp[index], (strlen(envp[index]) + 1)*sizeof(char), 0);
-  trackInitInst(envp, (index )*sizeof(char*), 0);
-}
-
-/**
- * Record the global type and address in the shadow memory.
- */
-void trackGlobal(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) {
-  uintptr_t p = maskAddress(ptr);
-  shadow_begin[p] = typeNumber;
-  memset(&shadow_begin[p + 1], 0, size - 1);
-#if DEBUG
-  printf("Global(%d): %p, %p = %u | %lu bytes\n", tag, ptr, (void *)p, typeNumber, size);
-#endif
-}
-
-/**
- * Record the type stored at ptr(of size size) and replicate it
- */
-void trackArray(void *ptr, uint64_t size, uint64_t count, uint32_t tag) {
-  uintptr_t p = maskAddress(ptr);
-  uintptr_t p1 = maskAddress(ptr);
-  uint64_t i;
-
-  for (i = 1; i < count; ++i) {
-    p += size;
-    memcpy(&shadow_begin[p], &shadow_begin[p1], size);
-  }
-}
-
-/**
- * Record the stored type and address in the shadow memory.
- */
-void trackStoreInst(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) {
-  uintptr_t p = maskAddress(ptr);
-  shadow_begin[p] = typeNumber;
-  memset(&shadow_begin[p + 1], 0, size - 1);
-  printf("Store(%d): %p, %p = %u | %lu bytes | \n", tag, ptr, (void *)p, typeNumber, size);
-
-}
-
-/** 
- * Check that the two types match
- */
-void compareTypes(uint8_t typeNumberSrc, uint8_t typeNumberDest, uint32_t tag) {
-  if(typeNumberSrc != typeNumberDest) {
-    printf("Type mismatch(%u): expecting %s, found %s! \n", tag, typeNames[typeNumberDest], typeNames[typeNumberSrc]);
-  }
-}
-
-/**
- * Check that number of VAArg accessed is not greater than those passed
- */
-void compareNumber(uint64_t NumArgsPassed, uint64_t ArgAccessed, uint32_t tag){
-  if(ArgAccessed > NumArgsPassed) {
-    printf("Type mismatch(%u): Accessing variable %lu, passed only %lu! \n", tag, ArgAccessed, NumArgsPassed);
-  }
-}
-
-/**
- * Combined check for Va_arg. 
- * Check that no. of arguments is less than passed
- * Check that the type being accessed is correct
- * MD : pointer to array of metadata for each argument passed
- */
-void compareTypeAndNumber(uint64_t NumArgsPassed, uint64_t ArgAccessed, uint8_t TypeAccessed, void *MD, uint32_t tag) {
-  compareNumber(NumArgsPassed, ArgAccessed, tag);
-  compareTypes(TypeAccessed, ((uint8_t*)MD)[ArgAccessed], tag);
-}
-
-void getTypeTag(void *ptr, uint64_t size, uint8_t *dest) {
-  uintptr_t p = maskAddress(ptr);
-  assert(p + size < SIZE);
-
-  memcpy(dest, &shadow_begin[p], size);
-}
-
-void checkType(uint8_t typeNumber, uint64_t size, uint8_t *metadata, void *ptr, uint32_t tag) {
-  uint8_t i = 1;
-  /* Check if this an initialized but untyped memory.*/
-  if (typeNumber != metadata[0]) {
-    if (metadata[0] != 0xFF) {
-      printf("Type mismatch(%u): %p expecting %s, found %s!\n", tag, ptr, typeNames[typeNumber], typeNames[metadata[0]]);
-      return;
-    } else {
-      /* If so, set type to the type being read.
-         Check that none of the bytes are typed.*/
-      for (; i < size; ++i) {
-        if (0xFF != metadata[i]) {
-          printf("Type alignment mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[metadata[i]]);
-          break;
-        }
-      }
-      trackStoreInst(ptr, typeNumber, size, tag);
-      return ;
-    }
-  }
-
-  for (; i < size; ++i) {
-    if (0 != metadata[i]) {
-      printf("Type alignment mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[metadata[0]]);
-      break;
-    }
-  }
-
-}
-
-/**
- *  For memset type instructions, that set values. 
- *  0xFF type indicates that any type can be read, 
- */
-void trackInitInst(void *ptr, uint64_t size, uint32_t tag) {
-  uintptr_t p = maskAddress(ptr);
-  memset(&shadow_begin[p], 0xFF, size);
-#if DEBUG
-  printf("Initialize: %p, %p | %lu bytes | %u\n", ptr, (void *)p, size, tag);
-#endif
-}
-
-/**
- * Clear the metadata for given pointer
- */
-void trackUnInitInst(void *ptr, uint64_t size, uint32_t tag) {
-  uintptr_t p = maskAddress(ptr);
-  memset(&shadow_begin[p], 0x00, size);
-#if DEBUG
-  printf("Unitialize: %p, %p | %lu bytes | %u\n", ptr, (void *)p, size, tag);
-#endif
-}
-
-/**
- * Copy size bits of metadata from src ptr to dest ptr.
- */
-void copyTypeInfo(void *dstptr, void *srcptr, uint64_t size, uint32_t tag) {
-  uintptr_t d = maskAddress(dstptr);
-  uintptr_t s = maskAddress(srcptr);
-  memcpy(&shadow_begin[d], &shadow_begin[s], size);
-#if DEBUG
-  printf("Copy(%d): %p, %p = %u | %lu bytes \n", tag, dstptr, srcptr, shadow_begin[s], size);
-#endif
-}
-void setTypeInfo(void *dstptr, void *metadata, uint64_t size, uint32_t tag) {
-  uintptr_t d = maskAddress(dstptr);
-  memcpy(&shadow_begin[d], metadata, size);
-}
-
-/**
- * Initialize metadata for the pointer returned by __ctype_b_loc
- */
-void trackctype(void *ptr, uint32_t tag) {
-  short *p, *p1;
-  trackInitInst(ptr, sizeof(short*), tag);
-  p = *(short**)ptr;
-  p1 = p -128;
-  trackInitInst(p1, sizeof(short)*384, tag);
-}
-
-void trackctype_32(void *ptr, uint32_t tag) {
-  int *p, *p1;
-  trackInitInst(ptr, sizeof(int*), tag);
-  p = *(int**)ptr;
-  p1 = p -128 ;
-  trackInitInst(p1, sizeof(int)*384, tag);
-}
-
-/**
- * Initialize metadata for the dst pointer of strncpy
- */
-void trackStrncpyInst(void *dst, void *src, uint64_t size, uint32_t tag) {
-  if(strlen(src) < size)
-    size = strlen(src) + 1;
-  copyTypeInfo(dst, src, size, tag);
-}
-
-/**
- * Initialize metadata for the dst pointer of strcpy
- */
-void trackStrcpyInst(void *dst, void *src, uint32_t tag) {
-  copyTypeInfo(dst, src, strlen(src)+1, tag);
-}
-
-void trackStrcatInst(void *dst, void *src, uint32_t tag) {
-  uintptr_t dst_start = (uintptr_t)(dst) + strlen(dst) -1;
-  copyTypeInfo((void*)dst_start, src, strlen(src)+1, tag);
-}
-
-void trackgetcwd(void *ptr, uint32_t tag) {
-  if(!ptr)
-    return;
-  trackInitInst(ptr, strlen(ptr) + 1, tag);
-}
-
-void trackgethostname(void *ptr, uint32_t tag) {
-  trackInitInst(ptr, strlen(ptr) + 1, tag);
-}
-
-void trackgetaddrinfo(void *ptr, uint32_t tag) {
-  struct addrinfo *res;
-  struct addrinfo ** result = (struct addrinfo **)ptr;
-  for(res = *result; res != NULL; res = res->ai_next) {
-    trackInitInst(res->ai_addr, sizeof(struct sockaddr), tag);
-    trackInitInst(res, sizeof(struct addrinfo), tag);
-  }
-
-  trackInitInst(result, sizeof(struct addrinfo*), tag);
-}
-
-void trackaccept(void *ptr, uint32_t tag) {
-  trackInitInst(ptr, sizeof(struct sockaddr), tag);
-}
-
-void trackpoll(void *ptr, uint64_t nfds, uint32_t tag) {
-  struct pollfd *fds = (struct pollfd *)ptr;
-  unsigned i = 0;
-  while (i < nfds) {
-    trackInitInst(&fds[i], sizeof(struct pollfd), tag);
-    i++;
-  }
-}

Added: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=133643&view=auto
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (added)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Wed Jun 22 15:57:15 2011
@@ -0,0 +1,389 @@
+#include <assert.h>
+#include <inttypes.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <netdb.h>
+#include <poll.h>
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <sys/mman.h>
+
+#include <map>
+
+#define DEBUG (0)
+
+/* Size of shadow memory.  We're hoping everything fits in 46bits. */
+#define SIZE ((size_t)(1L << 46))
+
+/* Fixed start of memory.  Needs to be page-aligned,
+ * and it needs to be large enough that program itself is loaded below it
+ * and so are the libraries. 
+ * FIXME: This address has been picked for maute. Might not work on other
+ * machines. Need a more robust way of picking base address.
+ * For now, run a version of the tool without the base fixed, and 
+ * choose address.
+ */
+#define BASE ((uint8_t *)(0x2aaaab88c000))
+/*
+ * Do some macro magic to get mmap macros defined properly on all platforms.
+ */
+#if defined(MAP_ANON) && !defined(MAP_ANONYMOUS)
+# define MAP_ANONYMOUS MAP_ANON
+#endif /* defined(MAP_ANON) && !defined(MAP_ANONYMOUS) */
+
+struct va_info {
+  uint64_t numElements;
+  uint64_t counter;
+  uint8_t *metadata;
+};
+
+// Map to store info about va lists
+std::map<void *, struct va_info> VA_InfoMap;
+
+// Pointer to the shadow_memory
+uint8_t * const shadow_begin = BASE;
+
+// Map from type numbers to type names.
+extern char* typeNames[];
+
+extern "C" {
+  void trackInitInst(void *ptr, uint64_t size, uint32_t tag);
+  void shadowInit();
+  void trackArgvType(int argc, char **argv) ;
+  void trackEnvpType(char **envp) ;
+  void trackGlobal(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) ;
+  void trackArray(void *ptr, uint64_t size, uint64_t count, uint32_t tag) ;
+  void trackStoreInst(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) ;
+  void trackStringInput(void *ptr, uint32_t tag) ;
+  void compareTypes(uint8_t typeNumberSrc, uint8_t typeNumberDest, uint32_t tag) ;
+  void compareNumber(uint64_t NumArgsPassed, uint64_t ArgAccessed, uint32_t tag);
+  void compareTypeAndNumber(uint64_t NumArgsPassed, uint64_t ArgAccessed, uint8_t TypeAccessed, void *MD, uint32_t tag) ;
+  void checkVAArgType(void *va_list, uint8_t TypeAccessed, uint32_t tag) ;
+  void getTypeTag(void *ptr, uint64_t size, uint8_t *dest) ;
+  void checkType(uint8_t typeNumber, uint64_t size, uint8_t *metadata, void *ptr, uint32_t tag);
+  void trackInitInst(void *ptr, uint64_t size, uint32_t tag) ;
+  void trackUnInitInst(void *ptr, uint64_t size, uint32_t tag) ;
+  void copyTypeInfo(void *dstptr, void *srcptr, uint64_t size, uint32_t tag) ;
+  void setTypeInfo(void *dstptr, void *metadata, uint64_t size, uint32_t tag) ;
+  void setVAInfo(void *va_list, uint64_t totalCount, uint8_t *metadata_ptr) ;
+  void copyVAInfo(void *va_list_dst, uint8_t *va_list_src) ;
+  void trackctype(void *ptr, uint32_t tag) ;
+  void trackctype_32(void *ptr, uint32_t tag) ;
+  void trackStrncpyInst(void *dst, void *src, uint64_t size, uint32_t tag) ;
+  void trackStrcpyInst(void *dst, void *src, uint32_t tag) ;
+  void trackStrcatInst(void *dst, void *src, uint32_t tag) ;
+  void trackgetcwd(void *ptr, uint32_t tag) ;
+  void trackgethostname(void *ptr, uint32_t tag) ;
+  void trackgetaddrinfo(void *ptr, uint32_t tag) ;
+  void trackaccept(void *ptr, uint32_t tag) ;
+  void trackpoll(void *ptr, uint64_t nfds, uint32_t tag) ;
+}
+
+void trackInitInst(void *ptr, uint64_t size, uint32_t tag);
+
+inline uintptr_t maskAddress(void *ptr) {
+  uintptr_t p = (uintptr_t)ptr;
+  if (p >= (uintptr_t)BASE + SIZE) p -= SIZE;
+
+#if DEBUG
+  assert(p <= SIZE && "Pointer out of range!");
+#endif
+  return p;
+}
+
+/**
+ * Initialize the shadow memory which records the 1:1 mapping of addresses to types.
+ */
+void shadowInit() {
+  void * res = mmap(BASE, SIZE, PROT_READ | PROT_WRITE, MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS | MAP_NORESERVE, -1, 0);
+
+  if (res == MAP_FAILED) {
+    fprintf(stderr, "Failed to map the shadow memory!\n");
+    fflush(stderr);
+    assert(0 && "MAP_FAILED");
+  }
+  VA_InfoMap.clear();
+}
+
+/**
+ * initialize metadata to TOP/initialized.
+ */
+void trackArgvType(int argc, char **argv) {
+  int index = 0;
+  for (; index < argc; ++index) {
+    trackInitInst(argv[index], (strlen(argv[index]) + 1)*sizeof(char), 0);
+  }
+  trackInitInst(argv, (argc + 1)*sizeof(char*), 0);
+}
+
+/**
+ * initialize metadata to TOP/initialized.
+ */
+void trackEnvpType(char **envp) {
+  int index = 0;
+  for(;envp[index] != NULL; ++index)
+    trackInitInst(envp[index], (strlen(envp[index]) + 1)*sizeof(char), 0);
+  trackInitInst(envp, (index )*sizeof(char*), 0);
+}
+
+/**
+ * Record the global type and address in the shadow memory.
+ */
+void trackGlobal(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) {
+  uintptr_t p = maskAddress(ptr);
+  shadow_begin[p] = typeNumber;
+  memset(&shadow_begin[p + 1], 0, size - 1);
+#if DEBUG
+  printf("Global(%d): %p, %p = %u | %lu bytes\n", tag, ptr, (void *)p, typeNumber, size);
+#endif
+}
+
+/**
+ * Record the type stored at ptr(of size size) and replicate it
+ */
+void trackArray(void *ptr, uint64_t size, uint64_t count, uint32_t tag) {
+  uintptr_t p = maskAddress(ptr);
+  uintptr_t p1 = maskAddress(ptr);
+  uint64_t i;
+
+  for (i = 1; i < count; ++i) {
+    p += size;
+    memcpy(&shadow_begin[p], &shadow_begin[p1], size);
+  }
+}
+
+/**
+ * Record the stored type and address in the shadow memory.
+ */
+void trackStoreInst(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) {
+  uintptr_t p = maskAddress(ptr);
+  shadow_begin[p] = typeNumber;
+  memset(&shadow_begin[p + 1], 0, size - 1);
+#if DEBUG
+  printf("Store(%d): %p, %p = %u | %lu bytes | \n", tag, ptr, (void *)p, typeNumber, size);
+#endif
+
+}
+
+/**
+ * Record that a string is stored at ptr
+ */
+void trackStringInput(void *ptr, uint32_t tag) {
+  trackInitInst(ptr, strlen((const char *)ptr) + 1, tag);
+}
+
+/** 
+ * Check that the two types match
+ */
+void compareTypes(uint8_t typeNumberSrc, uint8_t typeNumberDest, uint32_t tag) {
+  if(typeNumberSrc != typeNumberDest) {
+    printf("Type mismatch(%u): expecting %s, found %s! \n", tag, typeNames[typeNumberDest], typeNames[typeNumberSrc]);
+  }
+}
+
+/**
+ * Check that number of VAArg accessed is not greater than those passed
+ */
+void compareNumber(uint64_t NumArgsPassed, uint64_t ArgAccessed, uint32_t tag){
+  if(ArgAccessed > NumArgsPassed) {
+    printf("Type mismatch(%u): Accessing variable %lu, passed only %lu! \n", tag, ArgAccessed, NumArgsPassed);
+  }
+}
+
+/**
+ * Combined check for Va_arg. 
+ * Check that no. of arguments is less than passed
+ * Check that the type being accessed is correct
+ */
+void checkVAArgType(void *va_list, uint8_t TypeAccessed, uint32_t tag) {
+  va_info v = VA_InfoMap[va_list];
+  compareNumber(v.numElements, v.counter, tag);
+  compareTypes(TypeAccessed, v.metadata[v.counter], tag);
+  v.counter++;
+  VA_InfoMap[va_list] = v;
+}
+
+/**
+ * For loads, return the metadata(for size bytes) stored at the ptr
+ * Store it in dest
+ */
+void getTypeTag(void *ptr, uint64_t size, uint8_t *dest) {
+  uintptr_t p = maskAddress(ptr);
+  assert(p + size < SIZE);
+
+  memcpy(dest, &shadow_begin[p], size);
+}
+
+/**
+ * Compare the typeNumber with the type info(for given size) stored at the metadata ptr.
+ * ptr and tag are for debugging
+ */
+void __attribute__((always_inline))
+checkType(uint8_t typeNumber, uint64_t size, uint8_t *metadata, void *ptr, uint32_t tag) {
+  /* Check if this an initialized but untyped memory.*/
+  if (typeNumber != metadata[0]) {
+    if (metadata[0] != 0xFF) {
+      printf("Type mismatch(%u): %p expecting %s, found %s!\n", tag, ptr, typeNames[typeNumber], typeNames[metadata[0]]);
+      return;
+    } else {
+      /* If so, set type to the type being read.
+         Check that none of the bytes are typed.*/
+      for (unsigned i = 1; i < size; ++i) {
+        if (0xFF != metadata[i]) {
+          printf("Type alignment mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[metadata[i]]);
+          break;
+        }
+      }
+      trackStoreInst(ptr, typeNumber, size, tag);
+      return ;
+    }
+  }
+
+  for (unsigned i = 1 ; i < size; ++i) {
+    if (0 != metadata[i]) {
+      printf("Type alignment mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[metadata[0]]);
+      break;
+    }
+  }
+}
+
+/**
+ *  For memset type instructions, that set values. 
+ *  0xFF type indicates that any type can be read, 
+ */
+void trackInitInst(void *ptr, uint64_t size, uint32_t tag) {
+  uintptr_t p = maskAddress(ptr);
+  memset(&shadow_begin[p], 0xFF, size);
+#if DEBUG
+  printf("Initialize: %p, %p | %lu bytes | %u\n", ptr, (void *)p, size, tag);
+#endif
+}
+
+/**
+ * Clear the metadata for given pointer
+ */
+void trackUnInitInst(void *ptr, uint64_t size, uint32_t tag) {
+  uintptr_t p = maskAddress(ptr);
+  memset(&shadow_begin[p], 0x00, size);
+#if DEBUG
+  printf("Unitialize: %p, %p | %lu bytes | %u\n", ptr, (void *)p, size, tag);
+#endif
+}
+
+/**
+ * Copy size bytes of metadata from src ptr to dest ptr.
+ */
+void copyTypeInfo(void *dstptr, void *srcptr, uint64_t size, uint32_t tag) {
+  uintptr_t d = maskAddress(dstptr);
+  uintptr_t s = maskAddress(srcptr);
+  memcpy(&shadow_begin[d], &shadow_begin[s], size);
+#if DEBUG
+  printf("Copy(%d): %p, %p = %u | %lu bytes \n", tag, dstptr, srcptr, shadow_begin[s], size);
+#endif
+}
+
+/**
+ * Copy size bytes of metadata from metadata to dest ptr
+ */
+void setTypeInfo(void *dstptr, void *metadata, uint64_t size, uint32_t tag) {
+  uintptr_t d = maskAddress(dstptr);
+  memcpy(&shadow_begin[d], metadata, size);
+}
+
+/**
+ * Initialize the metadata for a given VAList
+ */
+void setVAInfo(void *va_list, uint64_t totalCount, uint8_t *metadata_ptr, uint32_t tag) {
+  struct va_info v = {totalCount, 0, metadata_ptr};
+  VA_InfoMap[va_list] = v;
+}
+
+/**
+ * Copy va list metadata from one list to the other.
+ */
+void copyVAInfo(void *va_list_dst, uint8_t *va_list_src, uint32_t tag) {
+  VA_InfoMap[va_list_dst] = VA_InfoMap[va_list_src];
+}
+
+/**
+ * Initialize metadata for the pointer returned by __ctype_b_loc
+ */
+void trackctype(void *ptr, uint32_t tag) {
+  short *p, *p1;
+  trackInitInst(ptr, sizeof(short*), tag);
+  p = *(short**)ptr;
+  p1 = p -128;
+  trackInitInst(p1, sizeof(short)*384, tag);
+}
+
+void trackctype_32(void *ptr, uint32_t tag) {
+  int *p, *p1;
+  trackInitInst(ptr, sizeof(int*), tag);
+  p = *(int**)ptr;
+  p1 = p -128 ;
+  trackInitInst(p1, sizeof(int)*384, tag);
+}
+
+/**
+ * Initialize metadata for the dst pointer of strncpy
+ */
+void trackStrncpyInst(void *dst, void *src, uint64_t size, uint32_t tag) {
+  if(strlen((const char *)src) < size)
+    size = strlen((const char *)src) + 1;
+  copyTypeInfo(dst, src, size, tag);
+}
+
+/**
+ * Initialize metadata for the dst pointer of strcpy
+ */
+void trackStrcpyInst(void *dst, void *src, uint32_t tag) {
+  copyTypeInfo(dst, src, strlen((const char *)src)+1, tag);
+}
+
+/**
+ * Initialize the metadata fr dst pointer of strcap
+ */
+void trackStrcatInst(void *dst, void *src, uint32_t tag) {
+  uintptr_t dst_start = (uintptr_t)(dst) + strlen((const char *)dst) -1;
+  copyTypeInfo((void*)dst_start, src, strlen((const char *)src)+1, tag);
+}
+
+/**
+ * Initialize metadata for some library functions
+ */
+
+void trackgetcwd(void *ptr, uint32_t tag) {
+  if(!ptr)
+    return;
+  trackInitInst(ptr, strlen((const char *)ptr) + 1, tag);
+}
+
+void trackgethostname(void *ptr, uint32_t tag) {
+  trackInitInst(ptr, strlen((const char *)ptr) + 1, tag);
+}
+
+void trackgetaddrinfo(void *ptr, uint32_t tag) {
+  struct addrinfo *res;
+  struct addrinfo ** result = (struct addrinfo **)ptr;
+  for(res = *result; res != NULL; res = res->ai_next) {
+    trackInitInst(res->ai_addr, sizeof(struct sockaddr), tag);
+    trackInitInst(res, sizeof(struct addrinfo), tag);
+  }
+
+  trackInitInst(result, sizeof(struct addrinfo*), tag);
+}
+
+void trackaccept(void *ptr, uint32_t tag) {
+  trackInitInst(ptr, sizeof(struct sockaddr), tag);
+}
+
+void trackpoll(void *ptr, uint64_t nfds, uint32_t tag) {
+  struct pollfd *fds = (struct pollfd *)ptr;
+  unsigned i = 0;
+  while (i < nfds) {
+    trackInitInst(&fds[i], sizeof(struct pollfd), tag);
+    i++;
+  }
+}



From isanbard at gmail.com  Wed Jun 22 16:07:27 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 22 Jun 2011 21:07:27 -0000
Subject: [llvm-commits] [llvm] r133645 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20110622210727.E1FCA2A6C12C@llvm.org>

Author: void
Date: Wed Jun 22 16:07:27 2011
New Revision: 133645

URL: http://llvm.org/viewvc/llvm-project?rev=133645&view=rev
Log:
Move class methods out-of-line. This reduces the indentation, and is more in
line with LLVM's general coding style.
No functionality change.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=133645&r1=133644&r2=133645&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Wed Jun 22 16:07:27 2011
@@ -120,37 +120,8 @@
     return SectionAddress.lookup(SD);
   }
   uint64_t getSymbolAddress(const MCSymbolData* SD,
-                            const MCAsmLayout &Layout) const {
-    const MCSymbol &S = SD->getSymbol();
-
-    // If this is a variable, then recursively evaluate now.
-    if (S.isVariable()) {
-      MCValue Target;
-      if (!S.getVariableValue()->EvaluateAsRelocatable(Target, Layout))
-        report_fatal_error("unable to evaluate offset for variable '" +
-                           S.getName() + "'");
-
-      // Verify that any used symbols are defined.
-      if (Target.getSymA() && Target.getSymA()->getSymbol().isUndefined())
-        report_fatal_error("unable to evaluate offset to undefined symbol '" +
-                           Target.getSymA()->getSymbol().getName() + "'");
-      if (Target.getSymB() && Target.getSymB()->getSymbol().isUndefined())
-        report_fatal_error("unable to evaluate offset to undefined symbol '" +
-                           Target.getSymB()->getSymbol().getName() + "'");
-
-      uint64_t Address = Target.getConstant();
-      if (Target.getSymA())
-        Address += getSymbolAddress(&Layout.getAssembler().getSymbolData(
-                                      Target.getSymA()->getSymbol()), Layout);
-      if (Target.getSymB())
-        Address += getSymbolAddress(&Layout.getAssembler().getSymbolData(
-                                      Target.getSymB()->getSymbol()), Layout);
-      return Address;
-    }
+                            const MCAsmLayout &Layout) const;
 
-    return getSectionAddress(SD->getFragment()->getParent()) +
-      Layout.getSymbolOffset(SD);
-  }
   uint64_t getFragmentAddress(const MCFragment *Fragment,
                             const MCAsmLayout &Layout) const {
     return getSectionAddress(Fragment->getParent()) +
@@ -158,18 +129,7 @@
   }
 
   uint64_t getPaddingSize(const MCSectionData *SD,
-                          const MCAsmLayout &Layout) const {
-    uint64_t EndAddr = getSectionAddress(SD) + Layout.getSectionAddressSize(SD);
-    unsigned Next = SD->getLayoutOrder() + 1;
-    if (Next >= Layout.getSectionOrder().size())
-      return 0;
-
-    const MCSectionData &NextSD = *Layout.getSectionOrder()[Next];
-    if (NextSD.getSection().isVirtualSection())
-      return 0;
-    return OffsetToAlignment(EndAddr, NextSD.getAlignment());
-  }
-
+                          const MCAsmLayout &Layout) const;
 public:
   MachObjectWriter(MCMachObjectTargetWriter *MOTW, raw_ostream &_OS,
                    bool _IsLittleEndian)
@@ -188,33 +148,7 @@
   /// @}
 
   void WriteHeader(unsigned NumLoadCommands, unsigned LoadCommandsSize,
-                   bool SubsectionsViaSymbols) {
-    uint32_t Flags = 0;
-
-    if (SubsectionsViaSymbols)
-      Flags |= macho::HF_SubsectionsViaSymbols;
-
-    // struct mach_header (28 bytes) or
-    // struct mach_header_64 (32 bytes)
-
-    uint64_t Start = OS.tell();
-    (void) Start;
-
-    Write32(is64Bit() ? macho::HM_Object64 : macho::HM_Object32);
-
-    Write32(TargetObjectWriter->getCPUType());
-    Write32(TargetObjectWriter->getCPUSubtype());
-
-    Write32(macho::HFT_Object);
-    Write32(NumLoadCommands);
-    Write32(LoadCommandsSize);
-    Write32(Flags);
-    if (is64Bit())
-      Write32(0); // reserved
-
-    assert(OS.tell() - Start ==
-           (is64Bit() ? macho::Header64Size : macho::Header32Size));
-  }
+                   bool SubsectionsViaSymbols);
 
   /// WriteSegmentLoadCommand - Write a segment load command.
   ///
@@ -223,105 +157,15 @@
   void WriteSegmentLoadCommand(unsigned NumSections,
                                uint64_t VMSize,
                                uint64_t SectionDataStartOffset,
-                               uint64_t SectionDataSize) {
-    // struct segment_command (56 bytes) or
-    // struct segment_command_64 (72 bytes)
-
-    uint64_t Start = OS.tell();
-    (void) Start;
-
-    unsigned SegmentLoadCommandSize =
-      is64Bit() ? macho::SegmentLoadCommand64Size:
-      macho::SegmentLoadCommand32Size;
-    Write32(is64Bit() ? macho::LCT_Segment64 : macho::LCT_Segment);
-    Write32(SegmentLoadCommandSize +
-            NumSections * (is64Bit() ? macho::Section64Size :
-                           macho::Section32Size));
-
-    WriteBytes("", 16);
-    if (is64Bit()) {
-      Write64(0); // vmaddr
-      Write64(VMSize); // vmsize
-      Write64(SectionDataStartOffset); // file offset
-      Write64(SectionDataSize); // file size
-    } else {
-      Write32(0); // vmaddr
-      Write32(VMSize); // vmsize
-      Write32(SectionDataStartOffset); // file offset
-      Write32(SectionDataSize); // file size
-    }
-    Write32(0x7); // maxprot
-    Write32(0x7); // initprot
-    Write32(NumSections);
-    Write32(0); // flags
-
-    assert(OS.tell() - Start == SegmentLoadCommandSize);
-  }
+                               uint64_t SectionDataSize);
 
   void WriteSection(const MCAssembler &Asm, const MCAsmLayout &Layout,
                     const MCSectionData &SD, uint64_t FileOffset,
-                    uint64_t RelocationsStart, unsigned NumRelocations) {
-    uint64_t SectionSize = Layout.getSectionAddressSize(&SD);
-
-    // The offset is unused for virtual sections.
-    if (SD.getSection().isVirtualSection()) {
-      assert(Layout.getSectionFileSize(&SD) == 0 && "Invalid file size!");
-      FileOffset = 0;
-    }
-
-    // struct section (68 bytes) or
-    // struct section_64 (80 bytes)
-
-    uint64_t Start = OS.tell();
-    (void) Start;
-
-    const MCSectionMachO &Section = cast<MCSectionMachO>(SD.getSection());
-    WriteBytes(Section.getSectionName(), 16);
-    WriteBytes(Section.getSegmentName(), 16);
-    if (is64Bit()) {
-      Write64(getSectionAddress(&SD)); // address
-      Write64(SectionSize); // size
-    } else {
-      Write32(getSectionAddress(&SD)); // address
-      Write32(SectionSize); // size
-    }
-    Write32(FileOffset);
-
-    unsigned Flags = Section.getTypeAndAttributes();
-    if (SD.hasInstructions())
-      Flags |= MCSectionMachO::S_ATTR_SOME_INSTRUCTIONS;
-
-    assert(isPowerOf2_32(SD.getAlignment()) && "Invalid alignment!");
-    Write32(Log2_32(SD.getAlignment()));
-    Write32(NumRelocations ? RelocationsStart : 0);
-    Write32(NumRelocations);
-    Write32(Flags);
-    Write32(IndirectSymBase.lookup(&SD)); // reserved1
-    Write32(Section.getStubSize()); // reserved2
-    if (is64Bit())
-      Write32(0); // reserved3
-
-    assert(OS.tell() - Start == (is64Bit() ? macho::Section64Size :
-           macho::Section32Size));
-  }
+                    uint64_t RelocationsStart, unsigned NumRelocations);
 
   void WriteSymtabLoadCommand(uint32_t SymbolOffset, uint32_t NumSymbols,
                               uint32_t StringTableOffset,
-                              uint32_t StringTableSize) {
-    // struct symtab_command (24 bytes)
-
-    uint64_t Start = OS.tell();
-    (void) Start;
-
-    Write32(macho::LCT_Symtab);
-    Write32(macho::SymtabLoadCommandSize);
-    Write32(SymbolOffset);
-    Write32(NumSymbols);
-    Write32(StringTableOffset);
-    Write32(StringTableSize);
-
-    assert(OS.tell() - Start == macho::SymtabLoadCommandSize);
-  }
+                              uint32_t StringTableSize);
 
   void WriteDysymtabLoadCommand(uint32_t FirstLocalSymbol,
                                 uint32_t NumLocalSymbols,
@@ -330,100 +174,9 @@
                                 uint32_t FirstUndefinedSymbol,
                                 uint32_t NumUndefinedSymbols,
                                 uint32_t IndirectSymbolOffset,
-                                uint32_t NumIndirectSymbols) {
-    // struct dysymtab_command (80 bytes)
-
-    uint64_t Start = OS.tell();
-    (void) Start;
-
-    Write32(macho::LCT_Dysymtab);
-    Write32(macho::DysymtabLoadCommandSize);
-    Write32(FirstLocalSymbol);
-    Write32(NumLocalSymbols);
-    Write32(FirstExternalSymbol);
-    Write32(NumExternalSymbols);
-    Write32(FirstUndefinedSymbol);
-    Write32(NumUndefinedSymbols);
-    Write32(0); // tocoff
-    Write32(0); // ntoc
-    Write32(0); // modtaboff
-    Write32(0); // nmodtab
-    Write32(0); // extrefsymoff
-    Write32(0); // nextrefsyms
-    Write32(IndirectSymbolOffset);
-    Write32(NumIndirectSymbols);
-    Write32(0); // extreloff
-    Write32(0); // nextrel
-    Write32(0); // locreloff
-    Write32(0); // nlocrel
-
-    assert(OS.tell() - Start == macho::DysymtabLoadCommandSize);
-  }
-
-  void WriteNlist(MachSymbolData &MSD, const MCAsmLayout &Layout) {
-    MCSymbolData &Data = *MSD.SymbolData;
-    const MCSymbol &Symbol = Data.getSymbol();
-    uint8_t Type = 0;
-    uint16_t Flags = Data.getFlags();
-    uint32_t Address = 0;
-
-    // Set the N_TYPE bits. See <mach-o/nlist.h>.
-    //
-    // FIXME: Are the prebound or indirect fields possible here?
-    if (Symbol.isUndefined())
-      Type = macho::STT_Undefined;
-    else if (Symbol.isAbsolute())
-      Type = macho::STT_Absolute;
-    else
-      Type = macho::STT_Section;
-
-    // FIXME: Set STAB bits.
-
-    if (Data.isPrivateExtern())
-      Type |= macho::STF_PrivateExtern;
-
-    // Set external bit.
-    if (Data.isExternal() || Symbol.isUndefined())
-      Type |= macho::STF_External;
-
-    // Compute the symbol address.
-    if (Symbol.isDefined()) {
-      if (Symbol.isAbsolute()) {
-        Address = cast<MCConstantExpr>(Symbol.getVariableValue())->getValue();
-      } else {
-        Address = getSymbolAddress(&Data, Layout);
-      }
-    } else if (Data.isCommon()) {
-      // Common symbols are encoded with the size in the address
-      // field, and their alignment in the flags.
-      Address = Data.getCommonSize();
-
-      // Common alignment is packed into the 'desc' bits.
-      if (unsigned Align = Data.getCommonAlignment()) {
-        unsigned Log2Size = Log2_32(Align);
-        assert((1U << Log2Size) == Align && "Invalid 'common' alignment!");
-        if (Log2Size > 15)
-          report_fatal_error("invalid 'common' alignment '" +
-                            Twine(Align) + "'");
-        // FIXME: Keep this mask with the SymbolFlags enumeration.
-        Flags = (Flags & 0xF0FF) | (Log2Size << 8);
-      }
-    }
+                                uint32_t NumIndirectSymbols);
 
-    // struct nlist (12 bytes)
-
-    Write32(MSD.StringIndex);
-    Write8(Type);
-    Write8(MSD.SectionIndex);
-
-    // The Mach-O streamer uses the lowest 16-bits of the flags for the 'desc'
-    // value.
-    Write16(Flags);
-    if (is64Bit())
-      Write64(Address);
-    else
-      Write32(Address);
-  }
+  void WriteNlist(MachSymbolData &MSD, const MCAsmLayout &Layout);
 
   // FIXME: We really need to improve the relocation validation. Basically, we
   // want to implement a separate computation which evaluates the relocation
@@ -446,650 +199,453 @@
   void RecordX86_64Relocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
                               const MCFragment *Fragment,
                               const MCFixup &Fixup, MCValue Target,
-                              uint64_t &FixedValue) {
-    unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-    unsigned IsRIPRel = isFixupKindRIPRel(Fixup.getKind());
-    unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
-
-    // See <reloc.h>.
-    uint32_t FixupOffset =
-      Layout.getFragmentOffset(Fragment) + Fixup.getOffset();
-    uint32_t FixupAddress =
-      getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
-    int64_t Value = 0;
-    unsigned Index = 0;
-    unsigned IsExtern = 0;
-    unsigned Type = 0;
-
-    Value = Target.getConstant();
-
-    if (IsPCRel) {
-      // Compensate for the relocation offset, Darwin x86_64 relocations only
-      // have the addend and appear to have attempted to define it to be the
-      // actual expression addend without the PCrel bias. However, instructions
-      // with data following the relocation are not accommodated for (see comment
-      // below regarding SIGNED{1,2,4}), so it isn't exactly that either.
-      Value += 1LL << Log2Size;
-    }
-
-    if (Target.isAbsolute()) { // constant
-      // SymbolNum of 0 indicates the absolute section.
-      Type = macho::RIT_X86_64_Unsigned;
-      Index = 0;
-
-      // FIXME: I believe this is broken, I don't think the linker can
-      // understand it. I think it would require a local relocation, but I'm not
-      // sure if that would work either. The official way to get an absolute
-      // PCrel relocation is to use an absolute symbol (which we don't support
-      // yet).
-      if (IsPCRel) {
-        IsExtern = 1;
-        Type = macho::RIT_X86_64_Branch;
-      }
-    } else if (Target.getSymB()) { // A - B + constant
-      const MCSymbol *A = &Target.getSymA()->getSymbol();
-      MCSymbolData &A_SD = Asm.getSymbolData(*A);
-      const MCSymbolData *A_Base = Asm.getAtom(&A_SD);
-
-      const MCSymbol *B = &Target.getSymB()->getSymbol();
-      MCSymbolData &B_SD = Asm.getSymbolData(*B);
-      const MCSymbolData *B_Base = Asm.getAtom(&B_SD);
-
-      // Neither symbol can be modified.
-      if (Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None ||
-          Target.getSymB()->getKind() != MCSymbolRefExpr::VK_None)
-        report_fatal_error("unsupported relocation of modified symbol");
-
-      // We don't support PCrel relocations of differences. Darwin 'as' doesn't
-      // implement most of these correctly.
-      if (IsPCRel)
-        report_fatal_error("unsupported pc-relative relocation of difference");
-
-      // The support for the situation where one or both of the symbols would
-      // require a local relocation is handled just like if the symbols were
-      // external.  This is certainly used in the case of debug sections where
-      // the section has only temporary symbols and thus the symbols don't have
-      // base symbols.  This is encoded using the section ordinal and
-      // non-extern relocation entries.
-
-      // Darwin 'as' doesn't emit correct relocations for this (it ends up with
-      // a single SIGNED relocation); reject it for now.  Except the case where
-      // both symbols don't have a base, equal but both NULL.
-      if (A_Base == B_Base && A_Base)
-        report_fatal_error("unsupported relocation with identical base");
-
-      Value += getSymbolAddress(&A_SD, Layout) -
-        (A_Base == NULL ? 0 : getSymbolAddress(A_Base, Layout));
-      Value -= getSymbolAddress(&B_SD, Layout) -
-        (B_Base == NULL ? 0 : getSymbolAddress(B_Base, Layout));
-
-      if (A_Base) {
-        Index = A_Base->getIndex();
-        IsExtern = 1;
-      }
-      else {
-        Index = A_SD.getFragment()->getParent()->getOrdinal() + 1;
-        IsExtern = 0;
-      }
-      Type = macho::RIT_X86_64_Unsigned;
-
-      macho::RelocationEntry MRE;
-      MRE.Word0 = FixupOffset;
-      MRE.Word1 = ((Index     <<  0) |
-                   (IsPCRel   << 24) |
-                   (Log2Size  << 25) |
-                   (IsExtern  << 27) |
-                   (Type      << 28));
-      Relocations[Fragment->getParent()].push_back(MRE);
-
-      if (B_Base) {
-        Index = B_Base->getIndex();
-        IsExtern = 1;
-      }
-      else {
-        Index = B_SD.getFragment()->getParent()->getOrdinal() + 1;
-        IsExtern = 0;
-      }
-      Type = macho::RIT_X86_64_Subtractor;
-    } else {
-      const MCSymbol *Symbol = &Target.getSymA()->getSymbol();
-      MCSymbolData &SD = Asm.getSymbolData(*Symbol);
-      const MCSymbolData *Base = Asm.getAtom(&SD);
-
-      // Relocations inside debug sections always use local relocations when
-      // possible. This seems to be done because the debugger doesn't fully
-      // understand x86_64 relocation entries, and expects to find values that
-      // have already been fixed up.
-      if (Symbol->isInSection()) {
-        const MCSectionMachO &Section = static_cast<const MCSectionMachO&>(
-          Fragment->getParent()->getSection());
-        if (Section.hasAttribute(MCSectionMachO::S_ATTR_DEBUG))
-          Base = 0;
-      }
-
-      // x86_64 almost always uses external relocations, except when there is no
-      // symbol to use as a base address (a local symbol with no preceding
-      // non-local symbol).
-      if (Base) {
-        Index = Base->getIndex();
-        IsExtern = 1;
-
-        // Add the local offset, if needed.
-        if (Base != &SD)
-          Value += Layout.getSymbolOffset(&SD) - Layout.getSymbolOffset(Base);
-      } else if (Symbol->isInSection() && !Symbol->isVariable()) {
-        // The index is the section ordinal (1-based).
-        Index = SD.getFragment()->getParent()->getOrdinal() + 1;
-        IsExtern = 0;
-        Value += getSymbolAddress(&SD, Layout);
-
-        if (IsPCRel)
-          Value -= FixupAddress + (1 << Log2Size);
-      } else if (Symbol->isVariable()) {
-        const MCExpr *Value = Symbol->getVariableValue();
-        int64_t Res;
-        bool isAbs = Value->EvaluateAsAbsolute(Res, Layout, SectionAddress);
-        if (isAbs) {
-          FixedValue = Res;
-          return;
-        } else {
-          report_fatal_error("unsupported relocation of variable '" +
-                             Symbol->getName() + "'");
-        }
-      } else {
-        report_fatal_error("unsupported relocation of undefined symbol '" +
-                           Symbol->getName() + "'");
-      }
-
-      MCSymbolRefExpr::VariantKind Modifier = Target.getSymA()->getKind();
-      if (IsPCRel) {
-        if (IsRIPRel) {
-          if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
-            // x86_64 distinguishes movq foo at GOTPCREL so that the linker can
-            // rewrite the movq to an leaq at link time if the symbol ends up in
-            // the same linkage unit.
-            if (unsigned(Fixup.getKind()) == X86::reloc_riprel_4byte_movq_load)
-              Type = macho::RIT_X86_64_GOTLoad;
-            else
-              Type = macho::RIT_X86_64_GOT;
-          }  else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
-            Type = macho::RIT_X86_64_TLV;
-          }  else if (Modifier != MCSymbolRefExpr::VK_None) {
-            report_fatal_error("unsupported symbol modifier in relocation");
-          } else {
-            Type = macho::RIT_X86_64_Signed;
-
-            // The Darwin x86_64 relocation format has a problem where it cannot
-            // encode an address (L<foo> + <constant>) which is outside the atom
-            // containing L<foo>. Generally, this shouldn't occur but it does
-            // happen when we have a RIPrel instruction with data following the
-            // relocation entry (e.g., movb $012, L0(%rip)). Even with the PCrel
-            // adjustment Darwin x86_64 uses, the offset is still negative and
-            // the linker has no way to recognize this.
-            //
-            // To work around this, Darwin uses several special relocation types
-            // to indicate the offsets. However, the specification or
-            // implementation of these seems to also be incomplete; they should
-            // adjust the addend as well based on the actual encoded instruction
-            // (the additional bias), but instead appear to just look at the
-            // final offset.
-            switch (-(Target.getConstant() + (1LL << Log2Size))) {
-            case 1: Type = macho::RIT_X86_64_Signed1; break;
-            case 2: Type = macho::RIT_X86_64_Signed2; break;
-            case 4: Type = macho::RIT_X86_64_Signed4; break;
-            }
-          }
-        } else {
-          if (Modifier != MCSymbolRefExpr::VK_None)
-            report_fatal_error("unsupported symbol modifier in branch "
-                              "relocation");
-
-          Type = macho::RIT_X86_64_Branch;
-        }
-      } else {
-        if (Modifier == MCSymbolRefExpr::VK_GOT) {
-          Type = macho::RIT_X86_64_GOT;
-        } else if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
-          // GOTPCREL is allowed as a modifier on non-PCrel instructions, in
-          // which case all we do is set the PCrel bit in the relocation entry;
-          // this is used with exception handling, for example. The source is
-          // required to include any necessary offset directly.
-          Type = macho::RIT_X86_64_GOT;
-          IsPCRel = 1;
-        } else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
-          report_fatal_error("TLVP symbol modifier should have been rip-rel");
-        } else if (Modifier != MCSymbolRefExpr::VK_None)
-          report_fatal_error("unsupported symbol modifier in relocation");
-        else
-          Type = macho::RIT_X86_64_Unsigned;
-      }
-    }
-
-    // x86_64 always writes custom values into the fixups.
-    FixedValue = Value;
-
-    // struct relocation_info (8 bytes)
-    macho::RelocationEntry MRE;
-    MRE.Word0 = FixupOffset;
-    MRE.Word1 = ((Index     <<  0) |
-                 (IsPCRel   << 24) |
-                 (Log2Size  << 25) |
-                 (IsExtern  << 27) |
-                 (Type      << 28));
-    Relocations[Fragment->getParent()].push_back(MRE);
-  }
+                              uint64_t &FixedValue);
 
   void RecordScatteredRelocation(const MCAssembler &Asm,
                                  const MCAsmLayout &Layout,
                                  const MCFragment *Fragment,
                                  const MCFixup &Fixup, MCValue Target,
                                  unsigned Log2Size,
-                                 uint64_t &FixedValue) {
-    uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-    unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-    unsigned Type = macho::RIT_Vanilla;
-
-    // See <reloc.h>.
-    const MCSymbol *A = &Target.getSymA()->getSymbol();
-    MCSymbolData *A_SD = &Asm.getSymbolData(*A);
-
-    if (!A_SD->getFragment())
-      report_fatal_error("symbol '" + A->getName() +
-                        "' can not be undefined in a subtraction expression");
-
-    uint32_t Value = getSymbolAddress(A_SD, Layout);
-    uint64_t SecAddr = getSectionAddress(A_SD->getFragment()->getParent());
-    FixedValue += SecAddr;
-    uint32_t Value2 = 0;
-
-    if (const MCSymbolRefExpr *B = Target.getSymB()) {
-      MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
-
-      if (!B_SD->getFragment())
-        report_fatal_error("symbol '" + B->getSymbol().getName() +
-                          "' can not be undefined in a subtraction expression");
-
-      // Select the appropriate difference relocation type.
-      //
-      // Note that there is no longer any semantic difference between these two
-      // relocation types from the linkers point of view, this is done solely
-      // for pedantic compatibility with 'as'.
-      Type = A_SD->isExternal() ? (unsigned)macho::RIT_Difference :
-        (unsigned)macho::RIT_Generic_LocalDifference;
-      Value2 = getSymbolAddress(B_SD, Layout);
-      FixedValue -= getSectionAddress(B_SD->getFragment()->getParent());
-    }
-
-    // Relocations are written out in reverse order, so the PAIR comes first.
-    if (Type == macho::RIT_Difference ||
-        Type == macho::RIT_Generic_LocalDifference) {
-      macho::RelocationEntry MRE;
-      MRE.Word0 = ((0         <<  0) |
-                   (macho::RIT_Pair  << 24) |
-                   (Log2Size  << 28) |
-                   (IsPCRel   << 30) |
-                   macho::RF_Scattered);
-      MRE.Word1 = Value2;
-      Relocations[Fragment->getParent()].push_back(MRE);
-    }
-
-    macho::RelocationEntry MRE;
-    MRE.Word0 = ((FixupOffset <<  0) |
-                 (Type        << 24) |
-                 (Log2Size    << 28) |
-                 (IsPCRel     << 30) |
-                 macho::RF_Scattered);
-    MRE.Word1 = Value;
-    Relocations[Fragment->getParent()].push_back(MRE);
-  }
+                                 uint64_t &FixedValue);
 
   void RecordARMScatteredRelocation(const MCAssembler &Asm,
                                     const MCAsmLayout &Layout,
                                     const MCFragment *Fragment,
                                     const MCFixup &Fixup, MCValue Target,
                                     unsigned Log2Size,
-                                    uint64_t &FixedValue) {
-    uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-    unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-    unsigned Type = macho::RIT_Vanilla;
-
-    // See <reloc.h>.
-    const MCSymbol *A = &Target.getSymA()->getSymbol();
-    MCSymbolData *A_SD = &Asm.getSymbolData(*A);
-
-    if (!A_SD->getFragment())
-      report_fatal_error("symbol '" + A->getName() +
-                        "' can not be undefined in a subtraction expression");
-
-    uint32_t Value = getSymbolAddress(A_SD, Layout);
-    uint64_t SecAddr = getSectionAddress(A_SD->getFragment()->getParent());
-    FixedValue += SecAddr;
-    uint32_t Value2 = 0;
-
-    if (const MCSymbolRefExpr *B = Target.getSymB()) {
-      MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
-
-      if (!B_SD->getFragment())
-        report_fatal_error("symbol '" + B->getSymbol().getName() +
-                          "' can not be undefined in a subtraction expression");
-
-      // Select the appropriate difference relocation type.
-      Type = macho::RIT_Difference;
-      Value2 = getSymbolAddress(B_SD, Layout);
-      FixedValue -= getSectionAddress(B_SD->getFragment()->getParent());
-    }
-
-    // Relocations are written out in reverse order, so the PAIR comes first.
-    if (Type == macho::RIT_Difference ||
-        Type == macho::RIT_Generic_LocalDifference) {
-      macho::RelocationEntry MRE;
-      MRE.Word0 = ((0         <<  0) |
-                   (macho::RIT_Pair  << 24) |
-                   (Log2Size  << 28) |
-                   (IsPCRel   << 30) |
-                   macho::RF_Scattered);
-      MRE.Word1 = Value2;
-      Relocations[Fragment->getParent()].push_back(MRE);
-    }
-
-    macho::RelocationEntry MRE;
-    MRE.Word0 = ((FixupOffset <<  0) |
-                 (Type        << 24) |
-                 (Log2Size    << 28) |
-                 (IsPCRel     << 30) |
-                 macho::RF_Scattered);
-    MRE.Word1 = Value;
-    Relocations[Fragment->getParent()].push_back(MRE);
-  }
+                                    uint64_t &FixedValue);
 
   void RecordARMMovwMovtRelocation(const MCAssembler &Asm,
                                    const MCAsmLayout &Layout,
                                    const MCFragment *Fragment,
                                    const MCFixup &Fixup, MCValue Target,
-                                   uint64_t &FixedValue) {
-    uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-    unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-    unsigned Type = macho::RIT_ARM_Half;
+                                   uint64_t &FixedValue);
 
-    // See <reloc.h>.
-    const MCSymbol *A = &Target.getSymA()->getSymbol();
-    MCSymbolData *A_SD = &Asm.getSymbolData(*A);
+  void RecordTLVPRelocation(const MCAssembler &Asm,
+                            const MCAsmLayout &Layout,
+                            const MCFragment *Fragment,
+                            const MCFixup &Fixup, MCValue Target,
+                            uint64_t &FixedValue);
 
-    if (!A_SD->getFragment())
-      report_fatal_error("symbol '" + A->getName() +
-                        "' can not be undefined in a subtraction expression");
+  static bool getARMFixupKindMachOInfo(unsigned Kind, unsigned &RelocType,
+                                       unsigned &Log2Size);
 
-    uint32_t Value = getSymbolAddress(A_SD, Layout);
-    uint32_t Value2 = 0;
-    uint64_t SecAddr = getSectionAddress(A_SD->getFragment()->getParent());
-    FixedValue += SecAddr;
+  void RecordARMRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
+                           const MCFragment *Fragment, const MCFixup &Fixup,
+                           MCValue Target, uint64_t &FixedValue);
 
-    if (const MCSymbolRefExpr *B = Target.getSymB()) {
-      MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
+  void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
+                        const MCFragment *Fragment, const MCFixup &Fixup,
+                        MCValue Target, uint64_t &FixedValue);
 
-      if (!B_SD->getFragment())
-        report_fatal_error("symbol '" + B->getSymbol().getName() +
-                          "' can not be undefined in a subtraction expression");
+  void BindIndirectSymbols(MCAssembler &Asm);
 
-      // Select the appropriate difference relocation type.
-      Type = macho::RIT_ARM_HalfDifference;
-      Value2 = getSymbolAddress(B_SD, Layout);
-      FixedValue -= getSectionAddress(B_SD->getFragment()->getParent());
-    }
+  /// ComputeSymbolTable - Compute the symbol table data
+  ///
+  /// \param StringTable [out] - The string table data.
+  /// \param StringIndexMap [out] - Map from symbol names to offsets in the
+  /// string table.
+  void ComputeSymbolTable(MCAssembler &Asm, SmallString<256> &StringTable,
+                          std::vector<MachSymbolData> &LocalSymbolData,
+                          std::vector<MachSymbolData> &ExternalSymbolData,
+                          std::vector<MachSymbolData> &UndefinedSymbolData);
 
-    // Relocations are written out in reverse order, so the PAIR comes first.
-    // ARM_RELOC_HALF and ARM_RELOC_HALF_SECTDIFF abuse the r_length field:
-    //
-    // For these two r_type relocations they always have a pair following them
-    // and the r_length bits are used differently.  The encoding of the
-    // r_length is as follows:
-    // low bit of r_length:
-    //  0 - :lower16: for movw instructions
-    //  1 - :upper16: for movt instructions
-    // high bit of r_length:
-    //  0 - arm instructions
-    //  1 - thumb instructions
-    // the other half of the relocated expression is in the following pair
-    // relocation entry in the the low 16 bits of r_address field.
-    unsigned ThumbBit = 0;
-    unsigned MovtBit = 0;
-    switch ((unsigned)Fixup.getKind()) {
-    default: break;
-    case ARM::fixup_arm_movt_hi16:
-    case ARM::fixup_arm_movt_hi16_pcrel:
-      MovtBit = 1;
-      break;
-    case ARM::fixup_t2_movt_hi16:
-    case ARM::fixup_t2_movt_hi16_pcrel:
-      MovtBit = 1;
-      // Fallthrough
-    case ARM::fixup_t2_movw_lo16:
-    case ARM::fixup_t2_movw_lo16_pcrel:
-      ThumbBit = 1;
-      break;
-    }
+  void computeSectionAddresses(const MCAssembler &Asm,
+                               const MCAsmLayout &Layout);
 
+  void ExecutePostLayoutBinding(MCAssembler &Asm, const MCAsmLayout &Layout);
 
-    if (Type == macho::RIT_ARM_HalfDifference) {
-      uint32_t OtherHalf = MovtBit
-        ? (FixedValue & 0xffff) : ((FixedValue & 0xffff0000) >> 16);
-
-      macho::RelocationEntry MRE;
-      MRE.Word0 = ((OtherHalf       <<  0) |
-                   (macho::RIT_Pair << 24) |
-                   (MovtBit         << 28) |
-                   (ThumbBit        << 29) |
-                   (IsPCRel         << 30) |
-                   macho::RF_Scattered);
-      MRE.Word1 = Value2;
-      Relocations[Fragment->getParent()].push_back(MRE);
-    }
+  virtual bool IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm,
+                                                      const MCSymbolData &DataA,
+                                                      const MCFragment &FB,
+                                                      bool InSet,
+                                                      bool IsPCRel) const;
 
-    macho::RelocationEntry MRE;
-    MRE.Word0 = ((FixupOffset <<  0) |
-                 (Type        << 24) |
-                 (MovtBit     << 28) |
-                 (ThumbBit    << 29) |
-                 (IsPCRel     << 30) |
-                 macho::RF_Scattered);
-    MRE.Word1 = Value;
-    Relocations[Fragment->getParent()].push_back(MRE);
-  }
+  void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout);
+};
 
-  void RecordTLVPRelocation(const MCAssembler &Asm,
-                            const MCAsmLayout &Layout,
-                            const MCFragment *Fragment,
-                            const MCFixup &Fixup, MCValue Target,
-                            uint64_t &FixedValue) {
-    assert(Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP &&
-           !is64Bit() &&
-           "Should only be called with a 32-bit TLVP relocation!");
-
-    unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
-    uint32_t Value = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-    unsigned IsPCRel = 0;
-
-    // Get the symbol data.
-    MCSymbolData *SD_A = &Asm.getSymbolData(Target.getSymA()->getSymbol());
-    unsigned Index = SD_A->getIndex();
-
-    // We're only going to have a second symbol in pic mode and it'll be a
-    // subtraction from the picbase. For 32-bit pic the addend is the difference
-    // between the picbase and the next address.  For 32-bit static the addend
-    // is zero.
-    if (Target.getSymB()) {
-      // If this is a subtraction then we're pcrel.
-      uint32_t FixupAddress =
-        getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
-      MCSymbolData *SD_B = &Asm.getSymbolData(Target.getSymB()->getSymbol());
-      IsPCRel = 1;
-      FixedValue = (FixupAddress - getSymbolAddress(SD_B, Layout) +
-                    Target.getConstant());
-      FixedValue += 1ULL << Log2Size;
-    } else {
-      FixedValue = 0;
-    }
+} // end anonymous namespace
 
-    // struct relocation_info (8 bytes)
-    macho::RelocationEntry MRE;
-    MRE.Word0 = Value;
-    MRE.Word1 = ((Index                  <<  0) |
-                 (IsPCRel                << 24) |
-                 (Log2Size               << 25) |
-                 (1                      << 27) | // Extern
-                 (macho::RIT_Generic_TLV << 28)); // Type
-    Relocations[Fragment->getParent()].push_back(MRE);
+uint64_t MachObjectWriter::getSymbolAddress(const MCSymbolData* SD,
+                                            const MCAsmLayout &Layout) const {
+  const MCSymbol &S = SD->getSymbol();
+
+  // If this is a variable, then recursively evaluate now.
+  if (S.isVariable()) {
+    MCValue Target;
+    if (!S.getVariableValue()->EvaluateAsRelocatable(Target, Layout))
+      report_fatal_error("unable to evaluate offset for variable '" +
+                         S.getName() + "'");
+
+    // Verify that any used symbols are defined.
+    if (Target.getSymA() && Target.getSymA()->getSymbol().isUndefined())
+      report_fatal_error("unable to evaluate offset to undefined symbol '" +
+                         Target.getSymA()->getSymbol().getName() + "'");
+    if (Target.getSymB() && Target.getSymB()->getSymbol().isUndefined())
+      report_fatal_error("unable to evaluate offset to undefined symbol '" +
+                         Target.getSymB()->getSymbol().getName() + "'");
+
+    uint64_t Address = Target.getConstant();
+    if (Target.getSymA())
+      Address += getSymbolAddress(&Layout.getAssembler().getSymbolData(
+                                    Target.getSymA()->getSymbol()), Layout);
+    if (Target.getSymB())
+      Address += getSymbolAddress(&Layout.getAssembler().getSymbolData(
+                                    Target.getSymB()->getSymbol()), Layout);
+    return Address;
   }
 
-  static bool getARMFixupKindMachOInfo(unsigned Kind, unsigned &RelocType,
-                                       unsigned &Log2Size) {
-    RelocType = unsigned(macho::RIT_Vanilla);
-    Log2Size = ~0U;
+  return getSectionAddress(SD->getFragment()->getParent()) +
+    Layout.getSymbolOffset(SD);
+}
 
-    switch (Kind) {
-    default:
-      return false;
+uint64_t MachObjectWriter::getPaddingSize(const MCSectionData *SD,
+                                          const MCAsmLayout &Layout) const {
+  uint64_t EndAddr = getSectionAddress(SD) + Layout.getSectionAddressSize(SD);
+  unsigned Next = SD->getLayoutOrder() + 1;
+  if (Next >= Layout.getSectionOrder().size())
+    return 0;
+
+  const MCSectionData &NextSD = *Layout.getSectionOrder()[Next];
+  if (NextSD.getSection().isVirtualSection())
+    return 0;
+  return OffsetToAlignment(EndAddr, NextSD.getAlignment());
+}
 
-    case FK_Data_1:
-      Log2Size = llvm::Log2_32(1);
-      return true;
-    case FK_Data_2:
-      Log2Size = llvm::Log2_32(2);
-      return true;
-    case FK_Data_4:
-      Log2Size = llvm::Log2_32(4);
-      return true;
-    case FK_Data_8:
-      Log2Size = llvm::Log2_32(8);
-      return true;
+void MachObjectWriter::WriteHeader(unsigned NumLoadCommands,
+                                   unsigned LoadCommandsSize,
+                                   bool SubsectionsViaSymbols) {
+  uint32_t Flags = 0;
+
+  if (SubsectionsViaSymbols)
+    Flags |= macho::HF_SubsectionsViaSymbols;
+
+  // struct mach_header (28 bytes) or
+  // struct mach_header_64 (32 bytes)
+
+  uint64_t Start = OS.tell();
+  (void) Start;
+
+  Write32(is64Bit() ? macho::HM_Object64 : macho::HM_Object32);
+
+  Write32(TargetObjectWriter->getCPUType());
+  Write32(TargetObjectWriter->getCPUSubtype());
+
+  Write32(macho::HFT_Object);
+  Write32(NumLoadCommands);
+  Write32(LoadCommandsSize);
+  Write32(Flags);
+  if (is64Bit())
+    Write32(0); // reserved
 
-      // Handle 24-bit branch kinds.
-    case ARM::fixup_arm_ldst_pcrel_12:
-    case ARM::fixup_arm_pcrel_10:
-    case ARM::fixup_arm_adr_pcrel_12:
-    case ARM::fixup_arm_condbranch:
-    case ARM::fixup_arm_uncondbranch:
-      RelocType = unsigned(macho::RIT_ARM_Branch24Bit);
-      // Report as 'long', even though that is not quite accurate.
-      Log2Size = llvm::Log2_32(4);
-      return true;
+  assert(OS.tell() - Start ==
+         (is64Bit() ? macho::Header64Size : macho::Header32Size));
+}
 
-      // Handle Thumb branches.
-    case ARM::fixup_arm_thumb_br:
-      RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);
-      Log2Size = llvm::Log2_32(2);
-      return true;
-      
-    case ARM::fixup_arm_thumb_bl:
-    case ARM::fixup_arm_thumb_blx:
-      RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);
-      Log2Size = llvm::Log2_32(4);
-      return true;
+/// WriteSegmentLoadCommand - Write a segment load command.
+///
+/// \arg NumSections - The number of sections in this segment.
+/// \arg SectionDataSize - The total size of the sections.
+void MachObjectWriter::WriteSegmentLoadCommand(unsigned NumSections,
+                                               uint64_t VMSize,
+                                               uint64_t SectionDataStartOffset,
+                                               uint64_t SectionDataSize) {
+  // struct segment_command (56 bytes) or
+  // struct segment_command_64 (72 bytes)
+
+  uint64_t Start = OS.tell();
+  (void) Start;
+
+  unsigned SegmentLoadCommandSize =
+    is64Bit() ? macho::SegmentLoadCommand64Size:
+    macho::SegmentLoadCommand32Size;
+  Write32(is64Bit() ? macho::LCT_Segment64 : macho::LCT_Segment);
+  Write32(SegmentLoadCommandSize +
+          NumSections * (is64Bit() ? macho::Section64Size :
+                         macho::Section32Size));
+
+  WriteBytes("", 16);
+  if (is64Bit()) {
+    Write64(0); // vmaddr
+    Write64(VMSize); // vmsize
+    Write64(SectionDataStartOffset); // file offset
+    Write64(SectionDataSize); // file size
+  } else {
+    Write32(0); // vmaddr
+    Write32(VMSize); // vmsize
+    Write32(SectionDataStartOffset); // file offset
+    Write32(SectionDataSize); // file size
+  }
+  Write32(0x7); // maxprot
+  Write32(0x7); // initprot
+  Write32(NumSections);
+  Write32(0); // flags
 
-    case ARM::fixup_arm_movt_hi16:
-    case ARM::fixup_arm_movt_hi16_pcrel:
-    case ARM::fixup_t2_movt_hi16:
-    case ARM::fixup_t2_movt_hi16_pcrel:
-      RelocType = unsigned(macho::RIT_ARM_HalfDifference);
-      // Report as 'long', even though that is not quite accurate.
-      Log2Size = llvm::Log2_32(4);
-      return true;
+  assert(OS.tell() - Start == SegmentLoadCommandSize);
+}
 
-    case ARM::fixup_arm_movw_lo16:
-    case ARM::fixup_arm_movw_lo16_pcrel:
-    case ARM::fixup_t2_movw_lo16:
-    case ARM::fixup_t2_movw_lo16_pcrel:
-      RelocType = unsigned(macho::RIT_ARM_Half);
-      // Report as 'long', even though that is not quite accurate.
-      Log2Size = llvm::Log2_32(4);
-      return true;
+void MachObjectWriter::WriteSection(const MCAssembler &Asm,
+                                    const MCAsmLayout &Layout,
+                                    const MCSectionData &SD,
+                                    uint64_t FileOffset,
+                                    uint64_t RelocationsStart,
+                                    unsigned NumRelocations) {
+  uint64_t SectionSize = Layout.getSectionAddressSize(&SD);
+
+  // The offset is unused for virtual sections.
+  if (SD.getSection().isVirtualSection()) {
+    assert(Layout.getSectionFileSize(&SD) == 0 && "Invalid file size!");
+    FileOffset = 0;
+  }
+
+  // struct section (68 bytes) or
+  // struct section_64 (80 bytes)
+
+  uint64_t Start = OS.tell();
+  (void) Start;
+
+  const MCSectionMachO &Section = cast<MCSectionMachO>(SD.getSection());
+  WriteBytes(Section.getSectionName(), 16);
+  WriteBytes(Section.getSegmentName(), 16);
+  if (is64Bit()) {
+    Write64(getSectionAddress(&SD)); // address
+    Write64(SectionSize); // size
+  } else {
+    Write32(getSectionAddress(&SD)); // address
+    Write32(SectionSize); // size
+  }
+  Write32(FileOffset);
+
+  unsigned Flags = Section.getTypeAndAttributes();
+  if (SD.hasInstructions())
+    Flags |= MCSectionMachO::S_ATTR_SOME_INSTRUCTIONS;
+
+  assert(isPowerOf2_32(SD.getAlignment()) && "Invalid alignment!");
+  Write32(Log2_32(SD.getAlignment()));
+  Write32(NumRelocations ? RelocationsStart : 0);
+  Write32(NumRelocations);
+  Write32(Flags);
+  Write32(IndirectSymBase.lookup(&SD)); // reserved1
+  Write32(Section.getStubSize()); // reserved2
+  if (is64Bit())
+    Write32(0); // reserved3
+
+  assert(OS.tell() - Start == (is64Bit() ? macho::Section64Size :
+                               macho::Section32Size));
+}
+
+void MachObjectWriter::WriteSymtabLoadCommand(uint32_t SymbolOffset,
+                                              uint32_t NumSymbols,
+                                              uint32_t StringTableOffset,
+                                              uint32_t StringTableSize) {
+  // struct symtab_command (24 bytes)
+
+  uint64_t Start = OS.tell();
+  (void) Start;
+
+  Write32(macho::LCT_Symtab);
+  Write32(macho::SymtabLoadCommandSize);
+  Write32(SymbolOffset);
+  Write32(NumSymbols);
+  Write32(StringTableOffset);
+  Write32(StringTableSize);
+
+  assert(OS.tell() - Start == macho::SymtabLoadCommandSize);
+}
+
+void MachObjectWriter::WriteDysymtabLoadCommand(uint32_t FirstLocalSymbol,
+                                                uint32_t NumLocalSymbols,
+                                                uint32_t FirstExternalSymbol,
+                                                uint32_t NumExternalSymbols,
+                                                uint32_t FirstUndefinedSymbol,
+                                                uint32_t NumUndefinedSymbols,
+                                                uint32_t IndirectSymbolOffset,
+                                                uint32_t NumIndirectSymbols) {
+  // struct dysymtab_command (80 bytes)
+
+  uint64_t Start = OS.tell();
+  (void) Start;
+
+  Write32(macho::LCT_Dysymtab);
+  Write32(macho::DysymtabLoadCommandSize);
+  Write32(FirstLocalSymbol);
+  Write32(NumLocalSymbols);
+  Write32(FirstExternalSymbol);
+  Write32(NumExternalSymbols);
+  Write32(FirstUndefinedSymbol);
+  Write32(NumUndefinedSymbols);
+  Write32(0); // tocoff
+  Write32(0); // ntoc
+  Write32(0); // modtaboff
+  Write32(0); // nmodtab
+  Write32(0); // extrefsymoff
+  Write32(0); // nextrefsyms
+  Write32(IndirectSymbolOffset);
+  Write32(NumIndirectSymbols);
+  Write32(0); // extreloff
+  Write32(0); // nextrel
+  Write32(0); // locreloff
+  Write32(0); // nlocrel
+
+  assert(OS.tell() - Start == macho::DysymtabLoadCommandSize);
+}
+
+void MachObjectWriter::WriteNlist(MachSymbolData &MSD, const MCAsmLayout &Layout) {
+  MCSymbolData &Data = *MSD.SymbolData;
+  const MCSymbol &Symbol = Data.getSymbol();
+  uint8_t Type = 0;
+  uint16_t Flags = Data.getFlags();
+  uint32_t Address = 0;
+
+  // Set the N_TYPE bits. See <mach-o/nlist.h>.
+  //
+  // FIXME: Are the prebound or indirect fields possible here?
+  if (Symbol.isUndefined())
+    Type = macho::STT_Undefined;
+  else if (Symbol.isAbsolute())
+    Type = macho::STT_Absolute;
+  else
+    Type = macho::STT_Section;
+
+  // FIXME: Set STAB bits.
+
+  if (Data.isPrivateExtern())
+    Type |= macho::STF_PrivateExtern;
+
+  // Set external bit.
+  if (Data.isExternal() || Symbol.isUndefined())
+    Type |= macho::STF_External;
+
+  // Compute the symbol address.
+  if (Symbol.isDefined()) {
+    if (Symbol.isAbsolute()) {
+      Address = cast<MCConstantExpr>(Symbol.getVariableValue())->getValue();
+    } else {
+      Address = getSymbolAddress(&Data, Layout);
     }
-  }
-  void RecordARMRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
-                           const MCFragment *Fragment, const MCFixup &Fixup,
-                           MCValue Target, uint64_t &FixedValue) {
-    unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-    unsigned Log2Size;
-    unsigned RelocType = macho::RIT_Vanilla;
-    if (!getARMFixupKindMachOInfo(Fixup.getKind(), RelocType, Log2Size)) {
-      report_fatal_error("unknown ARM fixup kind!");
-      return;
-    }
-
-    // If this is a difference or a defined symbol plus an offset, then we need
-    // a scattered relocation entry.  Differences always require scattered
-    // relocations.
-    if (Target.getSymB()) {
-      if (RelocType == macho::RIT_ARM_Half ||
-          RelocType == macho::RIT_ARM_HalfDifference)
-        return RecordARMMovwMovtRelocation(Asm, Layout, Fragment, Fixup,
-                                           Target, FixedValue);
-      return RecordARMScatteredRelocation(Asm, Layout, Fragment, Fixup,
-                                          Target, Log2Size, FixedValue);
+  } else if (Data.isCommon()) {
+    // Common symbols are encoded with the size in the address
+    // field, and their alignment in the flags.
+    Address = Data.getCommonSize();
+
+    // Common alignment is packed into the 'desc' bits.
+    if (unsigned Align = Data.getCommonAlignment()) {
+      unsigned Log2Size = Log2_32(Align);
+      assert((1U << Log2Size) == Align && "Invalid 'common' alignment!");
+      if (Log2Size > 15)
+        report_fatal_error("invalid 'common' alignment '" +
+                           Twine(Align) + "'");
+      // FIXME: Keep this mask with the SymbolFlags enumeration.
+      Flags = (Flags & 0xF0FF) | (Log2Size << 8);
     }
+  }
 
-    // Get the symbol data, if any.
-    MCSymbolData *SD = 0;
-    if (Target.getSymA())
-      SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
+  // struct nlist (12 bytes)
+
+  Write32(MSD.StringIndex);
+  Write8(Type);
+  Write8(MSD.SectionIndex);
+
+  // The Mach-O streamer uses the lowest 16-bits of the flags for the 'desc'
+  // value.
+  Write16(Flags);
+  if (is64Bit())
+    Write64(Address);
+  else
+    Write32(Address);
+}
 
-    // FIXME: For other platforms, we need to use scattered relocations for
-    // internal relocations with offsets.  If this is an internal relocation
-    // with an offset, it also needs a scattered relocation entry.
-    //
-    // Is this right for ARM?
-    uint32_t Offset = Target.getConstant();
-    if (IsPCRel && RelocType == macho::RIT_Vanilla)
-      Offset += 1 << Log2Size;
-    if (Offset && SD && !doesSymbolRequireExternRelocation(SD))
-      return RecordARMScatteredRelocation(Asm, Layout, Fragment, Fixup, Target,
-                                          Log2Size, FixedValue);
-
-    // See <reloc.h>.
-    uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-    unsigned Index = 0;
-    unsigned IsExtern = 0;
-    unsigned Type = 0;
-
-    if (Target.isAbsolute()) { // constant
-      // FIXME!
-      report_fatal_error("FIXME: relocations to absolute targets "
-                         "not yet implemented");
-    } else {
-      // Resolve constant variables.
-      if (SD->getSymbol().isVariable()) {
-        int64_t Res;
-        if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute(
-              Res, Layout, SectionAddress)) {
-          FixedValue = Res;
-          return;
-        }
-      }
+void MachObjectWriter::RecordX86_64Relocation(const MCAssembler &Asm,
+                                              const MCAsmLayout &Layout,
+                                              const MCFragment *Fragment,
+                                              const MCFixup &Fixup,
+                                              MCValue Target,
+                                              uint64_t &FixedValue) {
+  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned IsRIPRel = isFixupKindRIPRel(Fixup.getKind());
+  unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
+
+  // See <reloc.h>.
+  uint32_t FixupOffset =
+    Layout.getFragmentOffset(Fragment) + Fixup.getOffset();
+  uint32_t FixupAddress =
+    getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
+  int64_t Value = 0;
+  unsigned Index = 0;
+  unsigned IsExtern = 0;
+  unsigned Type = 0;
+
+  Value = Target.getConstant();
+
+  if (IsPCRel) {
+    // Compensate for the relocation offset, Darwin x86_64 relocations only have
+    // the addend and appear to have attempted to define it to be the actual
+    // expression addend without the PCrel bias. However, instructions with data
+    // following the relocation are not accommodated for (see comment below
+    // regarding SIGNED{1,2,4}), so it isn't exactly that either.
+    Value += 1LL << Log2Size;
+  }
+
+  if (Target.isAbsolute()) { // constant
+    // SymbolNum of 0 indicates the absolute section.
+    Type = macho::RIT_X86_64_Unsigned;
+    Index = 0;
 
-      // Check whether we need an external or internal relocation.
-      if (doesSymbolRequireExternRelocation(SD)) {
-        IsExtern = 1;
-        Index = SD->getIndex();
-        // For external relocations, make sure to offset the fixup value to
-        // compensate for the addend of the symbol address, if it was
-        // undefined. This occurs with weak definitions, for example.
-        if (!SD->Symbol->isUndefined())
-          FixedValue -= Layout.getSymbolOffset(SD);
-      } else {
-        // The index is the section ordinal (1-based).
-        const MCSectionData &SymSD = Asm.getSectionData(
-          SD->getSymbol().getSection());
-        Index = SymSD.getOrdinal() + 1;
-        FixedValue += getSectionAddress(&SymSD);
-      }
-      if (IsPCRel)
-        FixedValue -= getSectionAddress(Fragment->getParent());
+    // FIXME: I believe this is broken, I don't think the linker can understand
+    // it. I think it would require a local relocation, but I'm not sure if that
+    // would work either. The official way to get an absolute PCrel relocation
+    // is to use an absolute symbol (which we don't support yet).
+    if (IsPCRel) {
+      IsExtern = 1;
+      Type = macho::RIT_X86_64_Branch;
+    }
+  } else if (Target.getSymB()) { // A - B + constant
+    const MCSymbol *A = &Target.getSymA()->getSymbol();
+    MCSymbolData &A_SD = Asm.getSymbolData(*A);
+    const MCSymbolData *A_Base = Asm.getAtom(&A_SD);
 
-      // The type is determined by the fixup kind.
-      Type = RelocType;
+    const MCSymbol *B = &Target.getSymB()->getSymbol();
+    MCSymbolData &B_SD = Asm.getSymbolData(*B);
+    const MCSymbolData *B_Base = Asm.getAtom(&B_SD);
+
+    // Neither symbol can be modified.
+    if (Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None ||
+        Target.getSymB()->getKind() != MCSymbolRefExpr::VK_None)
+      report_fatal_error("unsupported relocation of modified symbol");
+
+    // We don't support PCrel relocations of differences. Darwin 'as' doesn't
+    // implement most of these correctly.
+    if (IsPCRel)
+      report_fatal_error("unsupported pc-relative relocation of difference");
+
+    // The support for the situation where one or both of the symbols would
+    // require a local relocation is handled just like if the symbols were
+    // external.  This is certainly used in the case of debug sections where the
+    // section has only temporary symbols and thus the symbols don't have base
+    // symbols.  This is encoded using the section ordinal and non-extern
+    // relocation entries.
+
+    // Darwin 'as' doesn't emit correct relocations for this (it ends up with a
+    // single SIGNED relocation); reject it for now.  Except the case where both
+    // symbols don't have a base, equal but both NULL.
+    if (A_Base == B_Base && A_Base)
+      report_fatal_error("unsupported relocation with identical base");
+
+    Value += getSymbolAddress(&A_SD, Layout) -
+      (A_Base == NULL ? 0 : getSymbolAddress(A_Base, Layout));
+    Value -= getSymbolAddress(&B_SD, Layout) -
+      (B_Base == NULL ? 0 : getSymbolAddress(B_Base, Layout));
+
+    if (A_Base) {
+      Index = A_Base->getIndex();
+      IsExtern = 1;
+    }
+    else {
+      Index = A_SD.getFragment()->getParent()->getOrdinal() + 1;
+      IsExtern = 0;
     }
+    Type = macho::RIT_X86_64_Unsigned;
 
-    // struct relocation_info (8 bytes)
     macho::RelocationEntry MRE;
     MRE.Word0 = FixupOffset;
     MRE.Word1 = ((Index     <<  0) |
@@ -1098,523 +654,1088 @@
                  (IsExtern  << 27) |
                  (Type      << 28));
     Relocations[Fragment->getParent()].push_back(MRE);
-  }
 
-  void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
-                        const MCFragment *Fragment, const MCFixup &Fixup,
-                        MCValue Target, uint64_t &FixedValue) {
-    // FIXME: These needs to be factored into the target Mach-O writer.
-    if (isARM()) {
-      RecordARMRelocation(Asm, Layout, Fragment, Fixup, Target, FixedValue);
-      return;
-    }
-    if (is64Bit()) {
-      RecordX86_64Relocation(Asm, Layout, Fragment, Fixup, Target, FixedValue);
-      return;
-    }
-
-    unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-    unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
-
-    // If this is a 32-bit TLVP reloc it's handled a bit differently.
-    if (Target.getSymA() &&
-        Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP) {
-      RecordTLVPRelocation(Asm, Layout, Fragment, Fixup, Target, FixedValue);
-      return;
-    }
-
-    // If this is a difference or a defined symbol plus an offset, then we need
-    // a scattered relocation entry.
-    // Differences always require scattered relocations.
-    if (Target.getSymB())
-        return RecordScatteredRelocation(Asm, Layout, Fragment, Fixup,
-                                         Target, Log2Size, FixedValue);
-
-    // Get the symbol data, if any.
-    MCSymbolData *SD = 0;
-    if (Target.getSymA())
-      SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
+    if (B_Base) {
+      Index = B_Base->getIndex();
+      IsExtern = 1;
+    }
+    else {
+      Index = B_SD.getFragment()->getParent()->getOrdinal() + 1;
+      IsExtern = 0;
+    }
+    Type = macho::RIT_X86_64_Subtractor;
+  } else {
+    const MCSymbol *Symbol = &Target.getSymA()->getSymbol();
+    MCSymbolData &SD = Asm.getSymbolData(*Symbol);
+    const MCSymbolData *Base = Asm.getAtom(&SD);
+
+    // Relocations inside debug sections always use local relocations when
+    // possible. This seems to be done because the debugger doesn't fully
+    // understand x86_64 relocation entries, and expects to find values that
+    // have already been fixed up.
+    if (Symbol->isInSection()) {
+      const MCSectionMachO &Section = static_cast<const MCSectionMachO&>(
+        Fragment->getParent()->getSection());
+      if (Section.hasAttribute(MCSectionMachO::S_ATTR_DEBUG))
+        Base = 0;
+    }
+
+    // x86_64 almost always uses external relocations, except when there is no
+    // symbol to use as a base address (a local symbol with no preceding
+    // non-local symbol).
+    if (Base) {
+      Index = Base->getIndex();
+      IsExtern = 1;
+
+      // Add the local offset, if needed.
+      if (Base != &SD)
+        Value += Layout.getSymbolOffset(&SD) - Layout.getSymbolOffset(Base);
+    } else if (Symbol->isInSection() && !Symbol->isVariable()) {
+      // The index is the section ordinal (1-based).
+      Index = SD.getFragment()->getParent()->getOrdinal() + 1;
+      IsExtern = 0;
+      Value += getSymbolAddress(&SD, Layout);
 
-    // If this is an internal relocation with an offset, it also needs a
-    // scattered relocation entry.
-    uint32_t Offset = Target.getConstant();
-    if (IsPCRel)
-      Offset += 1 << Log2Size;
-    if (Offset && SD && !doesSymbolRequireExternRelocation(SD))
-      return RecordScatteredRelocation(Asm, Layout, Fragment, Fixup,
-                                       Target, Log2Size, FixedValue);
-
-    // See <reloc.h>.
-    uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-    unsigned Index = 0;
-    unsigned IsExtern = 0;
-    unsigned Type = 0;
-
-    if (Target.isAbsolute()) { // constant
-      // SymbolNum of 0 indicates the absolute section.
-      //
-      // FIXME: Currently, these are never generated (see code below). I cannot
-      // find a case where they are actually emitted.
-      Type = macho::RIT_Vanilla;
-    } else {
-      // Resolve constant variables.
-      if (SD->getSymbol().isVariable()) {
-        int64_t Res;
-        if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute(
-              Res, Layout, SectionAddress)) {
-          FixedValue = Res;
-          return;
-        }
+      if (IsPCRel)
+        Value -= FixupAddress + (1 << Log2Size);
+    } else if (Symbol->isVariable()) {
+      const MCExpr *Value = Symbol->getVariableValue();
+      int64_t Res;
+      bool isAbs = Value->EvaluateAsAbsolute(Res, Layout, SectionAddress);
+      if (isAbs) {
+        FixedValue = Res;
+        return;
+      } else {
+        report_fatal_error("unsupported relocation of variable '" +
+                           Symbol->getName() + "'");
       }
+    } else {
+      report_fatal_error("unsupported relocation of undefined symbol '" +
+                         Symbol->getName() + "'");
+    }
 
-      // Check whether we need an external or internal relocation.
-      if (doesSymbolRequireExternRelocation(SD)) {
-        IsExtern = 1;
-        Index = SD->getIndex();
-        // For external relocations, make sure to offset the fixup value to
-        // compensate for the addend of the symbol address, if it was
-        // undefined. This occurs with weak definitions, for example.
-        if (!SD->Symbol->isUndefined())
-          FixedValue -= Layout.getSymbolOffset(SD);
+    MCSymbolRefExpr::VariantKind Modifier = Target.getSymA()->getKind();
+    if (IsPCRel) {
+      if (IsRIPRel) {
+        if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
+          // x86_64 distinguishes movq foo at GOTPCREL so that the linker can
+          // rewrite the movq to an leaq at link time if the symbol ends up in
+          // the same linkage unit.
+          if (unsigned(Fixup.getKind()) == X86::reloc_riprel_4byte_movq_load)
+            Type = macho::RIT_X86_64_GOTLoad;
+          else
+            Type = macho::RIT_X86_64_GOT;
+        }  else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
+          Type = macho::RIT_X86_64_TLV;
+        }  else if (Modifier != MCSymbolRefExpr::VK_None) {
+          report_fatal_error("unsupported symbol modifier in relocation");
+        } else {
+          Type = macho::RIT_X86_64_Signed;
+
+          // The Darwin x86_64 relocation format has a problem where it cannot
+          // encode an address (L<foo> + <constant>) which is outside the atom
+          // containing L<foo>. Generally, this shouldn't occur but it does
+          // happen when we have a RIPrel instruction with data following the
+          // relocation entry (e.g., movb $012, L0(%rip)). Even with the PCrel
+          // adjustment Darwin x86_64 uses, the offset is still negative and the
+          // linker has no way to recognize this.
+          //
+          // To work around this, Darwin uses several special relocation types
+          // to indicate the offsets. However, the specification or
+          // implementation of these seems to also be incomplete; they should
+          // adjust the addend as well based on the actual encoded instruction
+          // (the additional bias), but instead appear to just look at the final
+          // offset.
+          switch (-(Target.getConstant() + (1LL << Log2Size))) {
+          case 1: Type = macho::RIT_X86_64_Signed1; break;
+          case 2: Type = macho::RIT_X86_64_Signed2; break;
+          case 4: Type = macho::RIT_X86_64_Signed4; break;
+          }
+        }
       } else {
-        // The index is the section ordinal (1-based).
-        const MCSectionData &SymSD = Asm.getSectionData(
-          SD->getSymbol().getSection());
-        Index = SymSD.getOrdinal() + 1;
-        FixedValue += getSectionAddress(&SymSD);
-      }
-      if (IsPCRel)
-        FixedValue -= getSectionAddress(Fragment->getParent());
+        if (Modifier != MCSymbolRefExpr::VK_None)
+          report_fatal_error("unsupported symbol modifier in branch "
+                             "relocation");
 
-      Type = macho::RIT_Vanilla;
+        Type = macho::RIT_X86_64_Branch;
+      }
+    } else {
+      if (Modifier == MCSymbolRefExpr::VK_GOT) {
+        Type = macho::RIT_X86_64_GOT;
+      } else if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
+        // GOTPCREL is allowed as a modifier on non-PCrel instructions, in which
+        // case all we do is set the PCrel bit in the relocation entry; this is
+        // used with exception handling, for example. The source is required to
+        // include any necessary offset directly.
+        Type = macho::RIT_X86_64_GOT;
+        IsPCRel = 1;
+      } else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
+        report_fatal_error("TLVP symbol modifier should have been rip-rel");
+      } else if (Modifier != MCSymbolRefExpr::VK_None)
+        report_fatal_error("unsupported symbol modifier in relocation");
+      else
+        Type = macho::RIT_X86_64_Unsigned;
     }
+  }
+
+  // x86_64 always writes custom values into the fixups.
+  FixedValue = Value;
+
+  // struct relocation_info (8 bytes)
+  macho::RelocationEntry MRE;
+  MRE.Word0 = FixupOffset;
+  MRE.Word1 = ((Index     <<  0) |
+               (IsPCRel   << 24) |
+               (Log2Size  << 25) |
+               (IsExtern  << 27) |
+               (Type      << 28));
+  Relocations[Fragment->getParent()].push_back(MRE);
+}
 
-    // struct relocation_info (8 bytes)
+void MachObjectWriter::RecordScatteredRelocation(const MCAssembler &Asm,
+                                                 const MCAsmLayout &Layout,
+                                                 const MCFragment *Fragment,
+                                                 const MCFixup &Fixup,
+                                                 MCValue Target,
+                                                 unsigned Log2Size,
+                                                 uint64_t &FixedValue) {
+  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned Type = macho::RIT_Vanilla;
+
+  // See <reloc.h>.
+  const MCSymbol *A = &Target.getSymA()->getSymbol();
+  MCSymbolData *A_SD = &Asm.getSymbolData(*A);
+
+  if (!A_SD->getFragment())
+    report_fatal_error("symbol '" + A->getName() +
+                       "' can not be undefined in a subtraction expression");
+
+  uint32_t Value = getSymbolAddress(A_SD, Layout);
+  uint64_t SecAddr = getSectionAddress(A_SD->getFragment()->getParent());
+  FixedValue += SecAddr;
+  uint32_t Value2 = 0;
+
+  if (const MCSymbolRefExpr *B = Target.getSymB()) {
+    MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
+
+    if (!B_SD->getFragment())
+      report_fatal_error("symbol '" + B->getSymbol().getName() +
+                         "' can not be undefined in a subtraction expression");
+
+    // Select the appropriate difference relocation type.
+    //
+    // Note that there is no longer any semantic difference between these two
+    // relocation types from the linkers point of view, this is done solely for
+    // pedantic compatibility with 'as'.
+    Type = A_SD->isExternal() ? (unsigned)macho::RIT_Difference :
+      (unsigned)macho::RIT_Generic_LocalDifference;
+    Value2 = getSymbolAddress(B_SD, Layout);
+    FixedValue -= getSectionAddress(B_SD->getFragment()->getParent());
+  }
+
+  // Relocations are written out in reverse order, so the PAIR comes first.
+  if (Type == macho::RIT_Difference ||
+      Type == macho::RIT_Generic_LocalDifference) {
     macho::RelocationEntry MRE;
-    MRE.Word0 = FixupOffset;
-    MRE.Word1 = ((Index     <<  0) |
-                 (IsPCRel   << 24) |
-                 (Log2Size  << 25) |
-                 (IsExtern  << 27) |
-                 (Type      << 28));
+    MRE.Word0 = ((0         <<  0) |
+                 (macho::RIT_Pair  << 24) |
+                 (Log2Size  << 28) |
+                 (IsPCRel   << 30) |
+                 macho::RF_Scattered);
+    MRE.Word1 = Value2;
     Relocations[Fragment->getParent()].push_back(MRE);
   }
 
-  void BindIndirectSymbols(MCAssembler &Asm) {
-    // This is the point where 'as' creates actual symbols for indirect symbols
-    // (in the following two passes). It would be easier for us to do this
-    // sooner when we see the attribute, but that makes getting the order in the
-    // symbol table much more complicated than it is worth.
-    //
-    // FIXME: Revisit this when the dust settles.
+  macho::RelocationEntry MRE;
+  MRE.Word0 = ((FixupOffset <<  0) |
+               (Type        << 24) |
+               (Log2Size    << 28) |
+               (IsPCRel     << 30) |
+               macho::RF_Scattered);
+  MRE.Word1 = Value;
+  Relocations[Fragment->getParent()].push_back(MRE);
+}
 
-    // Bind non lazy symbol pointers first.
-    unsigned IndirectIndex = 0;
-    for (MCAssembler::indirect_symbol_iterator it = Asm.indirect_symbol_begin(),
-           ie = Asm.indirect_symbol_end(); it != ie; ++it, ++IndirectIndex) {
-      const MCSectionMachO &Section =
-        cast<MCSectionMachO>(it->SectionData->getSection());
+void MachObjectWriter::RecordARMScatteredRelocation(const MCAssembler &Asm,
+                                                    const MCAsmLayout &Layout,
+                                                    const MCFragment *Fragment,
+                                                    const MCFixup &Fixup,
+                                                    MCValue Target,
+                                                    unsigned Log2Size,
+                                                    uint64_t &FixedValue) {
+  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned Type = macho::RIT_Vanilla;
+
+  // See <reloc.h>.
+  const MCSymbol *A = &Target.getSymA()->getSymbol();
+  MCSymbolData *A_SD = &Asm.getSymbolData(*A);
+
+  if (!A_SD->getFragment())
+    report_fatal_error("symbol '" + A->getName() +
+                       "' can not be undefined in a subtraction expression");
+
+  uint32_t Value = getSymbolAddress(A_SD, Layout);
+  uint64_t SecAddr = getSectionAddress(A_SD->getFragment()->getParent());
+  FixedValue += SecAddr;
+  uint32_t Value2 = 0;
+
+  if (const MCSymbolRefExpr *B = Target.getSymB()) {
+    MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
+
+    if (!B_SD->getFragment())
+      report_fatal_error("symbol '" + B->getSymbol().getName() +
+                         "' can not be undefined in a subtraction expression");
+
+    // Select the appropriate difference relocation type.
+    Type = macho::RIT_Difference;
+    Value2 = getSymbolAddress(B_SD, Layout);
+    FixedValue -= getSectionAddress(B_SD->getFragment()->getParent());
+  }
+
+  // Relocations are written out in reverse order, so the PAIR comes first.
+  if (Type == macho::RIT_Difference ||
+      Type == macho::RIT_Generic_LocalDifference) {
+    macho::RelocationEntry MRE;
+    MRE.Word0 = ((0         <<  0) |
+                 (macho::RIT_Pair  << 24) |
+                 (Log2Size  << 28) |
+                 (IsPCRel   << 30) |
+                 macho::RF_Scattered);
+    MRE.Word1 = Value2;
+    Relocations[Fragment->getParent()].push_back(MRE);
+  }
 
-      if (Section.getType() != MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS)
-        continue;
+  macho::RelocationEntry MRE;
+  MRE.Word0 = ((FixupOffset <<  0) |
+               (Type        << 24) |
+               (Log2Size    << 28) |
+               (IsPCRel     << 30) |
+               macho::RF_Scattered);
+  MRE.Word1 = Value;
+  Relocations[Fragment->getParent()].push_back(MRE);
+}
 
-      // Initialize the section indirect symbol base, if necessary.
-      if (!IndirectSymBase.count(it->SectionData))
-        IndirectSymBase[it->SectionData] = IndirectIndex;
+void MachObjectWriter::RecordARMMovwMovtRelocation(const MCAssembler &Asm,
+                                                   const MCAsmLayout &Layout,
+                                                   const MCFragment *Fragment,
+                                                   const MCFixup &Fixup,
+                                                   MCValue Target,
+                                                   uint64_t &FixedValue) {
+  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned Type = macho::RIT_ARM_Half;
+
+  // See <reloc.h>.
+  const MCSymbol *A = &Target.getSymA()->getSymbol();
+  MCSymbolData *A_SD = &Asm.getSymbolData(*A);
+
+  if (!A_SD->getFragment())
+    report_fatal_error("symbol '" + A->getName() +
+                       "' can not be undefined in a subtraction expression");
+
+  uint32_t Value = getSymbolAddress(A_SD, Layout);
+  uint32_t Value2 = 0;
+  uint64_t SecAddr = getSectionAddress(A_SD->getFragment()->getParent());
+  FixedValue += SecAddr;
+
+  if (const MCSymbolRefExpr *B = Target.getSymB()) {
+    MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
+
+    if (!B_SD->getFragment())
+      report_fatal_error("symbol '" + B->getSymbol().getName() +
+                         "' can not be undefined in a subtraction expression");
+
+    // Select the appropriate difference relocation type.
+    Type = macho::RIT_ARM_HalfDifference;
+    Value2 = getSymbolAddress(B_SD, Layout);
+    FixedValue -= getSectionAddress(B_SD->getFragment()->getParent());
+  }
 
-      Asm.getOrCreateSymbolData(*it->Symbol);
-    }
+  // Relocations are written out in reverse order, so the PAIR comes first.
+  // ARM_RELOC_HALF and ARM_RELOC_HALF_SECTDIFF abuse the r_length field:
+  //
+  // For these two r_type relocations they always have a pair following them and
+  // the r_length bits are used differently.  The encoding of the r_length is as
+  // follows:
+  //   low bit of r_length:
+  //      0 - :lower16: for movw instructions
+  //      1 - :upper16: for movt instructions
+  //   high bit of r_length:
+  //      0 - arm instructions
+  //      1 - thumb instructions
+  // the other half of the relocated expression is in the following pair
+  // relocation entry in the the low 16 bits of r_address field.
+  unsigned ThumbBit = 0;
+  unsigned MovtBit = 0;
+  switch ((unsigned)Fixup.getKind()) {
+  default: break;
+  case ARM::fixup_arm_movt_hi16:
+  case ARM::fixup_arm_movt_hi16_pcrel:
+    MovtBit = 1;
+    break;
+  case ARM::fixup_t2_movt_hi16:
+  case ARM::fixup_t2_movt_hi16_pcrel:
+    MovtBit = 1;
+    // Fallthrough
+  case ARM::fixup_t2_movw_lo16:
+  case ARM::fixup_t2_movw_lo16_pcrel:
+    ThumbBit = 1;
+    break;
+  }
 
-    // Then lazy symbol pointers and symbol stubs.
-    IndirectIndex = 0;
-    for (MCAssembler::indirect_symbol_iterator it = Asm.indirect_symbol_begin(),
-           ie = Asm.indirect_symbol_end(); it != ie; ++it, ++IndirectIndex) {
-      const MCSectionMachO &Section =
-        cast<MCSectionMachO>(it->SectionData->getSection());
 
-      if (Section.getType() != MCSectionMachO::S_LAZY_SYMBOL_POINTERS &&
-          Section.getType() != MCSectionMachO::S_SYMBOL_STUBS)
-        continue;
-
-      // Initialize the section indirect symbol base, if necessary.
-      if (!IndirectSymBase.count(it->SectionData))
-        IndirectSymBase[it->SectionData] = IndirectIndex;
-
-      // Set the symbol type to undefined lazy, but only on construction.
-      //
-      // FIXME: Do not hardcode.
-      bool Created;
-      MCSymbolData &Entry = Asm.getOrCreateSymbolData(*it->Symbol, &Created);
-      if (Created)
-        Entry.setFlags(Entry.getFlags() | 0x0001);
-    }
+  if (Type == macho::RIT_ARM_HalfDifference) {
+    uint32_t OtherHalf = MovtBit
+      ? (FixedValue & 0xffff) : ((FixedValue & 0xffff0000) >> 16);
+
+    macho::RelocationEntry MRE;
+    MRE.Word0 = ((OtherHalf       <<  0) |
+                 (macho::RIT_Pair << 24) |
+                 (MovtBit         << 28) |
+                 (ThumbBit        << 29) |
+                 (IsPCRel         << 30) |
+                 macho::RF_Scattered);
+    MRE.Word1 = Value2;
+    Relocations[Fragment->getParent()].push_back(MRE);
   }
 
-  /// ComputeSymbolTable - Compute the symbol table data
-  ///
-  /// \param StringTable [out] - The string table data.
-  /// \param StringIndexMap [out] - Map from symbol names to offsets in the
-  /// string table.
-  void ComputeSymbolTable(MCAssembler &Asm, SmallString<256> &StringTable,
-                          std::vector<MachSymbolData> &LocalSymbolData,
-                          std::vector<MachSymbolData> &ExternalSymbolData,
-                          std::vector<MachSymbolData> &UndefinedSymbolData) {
-    // Build section lookup table.
-    DenseMap<const MCSection*, uint8_t> SectionIndexMap;
-    unsigned Index = 1;
-    for (MCAssembler::iterator it = Asm.begin(),
-           ie = Asm.end(); it != ie; ++it, ++Index)
-      SectionIndexMap[&it->getSection()] = Index;
-    assert(Index <= 256 && "Too many sections!");
+  macho::RelocationEntry MRE;
+  MRE.Word0 = ((FixupOffset <<  0) |
+               (Type        << 24) |
+               (MovtBit     << 28) |
+               (ThumbBit    << 29) |
+               (IsPCRel     << 30) |
+               macho::RF_Scattered);
+  MRE.Word1 = Value;
+  Relocations[Fragment->getParent()].push_back(MRE);
+}
 
-    // Index 0 is always the empty string.
-    StringMap<uint64_t> StringIndexMap;
-    StringTable += '\x00';
+void MachObjectWriter::RecordTLVPRelocation(const MCAssembler &Asm,
+                                            const MCAsmLayout &Layout,
+                                            const MCFragment *Fragment,
+                                            const MCFixup &Fixup,
+                                            MCValue Target,
+                                            uint64_t &FixedValue) {
+  assert(Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP &&
+         !is64Bit() &&
+         "Should only be called with a 32-bit TLVP relocation!");
+
+  unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
+  uint32_t Value = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned IsPCRel = 0;
+
+  // Get the symbol data.
+  MCSymbolData *SD_A = &Asm.getSymbolData(Target.getSymA()->getSymbol());
+  unsigned Index = SD_A->getIndex();
+
+  // We're only going to have a second symbol in pic mode and it'll be a
+  // subtraction from the picbase. For 32-bit pic the addend is the difference
+  // between the picbase and the next address.  For 32-bit static the addend is
+  // zero.
+  if (Target.getSymB()) {
+    // If this is a subtraction then we're pcrel.
+    uint32_t FixupAddress =
+      getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
+    MCSymbolData *SD_B = &Asm.getSymbolData(Target.getSymB()->getSymbol());
+    IsPCRel = 1;
+    FixedValue = (FixupAddress - getSymbolAddress(SD_B, Layout) +
+                  Target.getConstant());
+    FixedValue += 1ULL << Log2Size;
+  } else {
+    FixedValue = 0;
+  }
+
+  // struct relocation_info (8 bytes)
+  macho::RelocationEntry MRE;
+  MRE.Word0 = Value;
+  MRE.Word1 = ((Index                  <<  0) |
+               (IsPCRel                << 24) |
+               (Log2Size               << 25) |
+               (1                      << 27) | // Extern
+               (macho::RIT_Generic_TLV << 28)); // Type
+  Relocations[Fragment->getParent()].push_back(MRE);
+}
 
-    // Build the symbol arrays and the string table, but only for non-local
-    // symbols.
-    //
-    // The particular order that we collect the symbols and create the string
-    // table, then sort the symbols is chosen to match 'as'. Even though it
-    // doesn't matter for correctness, this is important for letting us diff .o
-    // files.
-    for (MCAssembler::symbol_iterator it = Asm.symbol_begin(),
-           ie = Asm.symbol_end(); it != ie; ++it) {
-      const MCSymbol &Symbol = it->getSymbol();
-
-      // Ignore non-linker visible symbols.
-      if (!Asm.isSymbolLinkerVisible(it->getSymbol()))
-        continue;
-
-      if (!it->isExternal() && !Symbol.isUndefined())
-        continue;
-
-      uint64_t &Entry = StringIndexMap[Symbol.getName()];
-      if (!Entry) {
-        Entry = StringTable.size();
-        StringTable += Symbol.getName();
-        StringTable += '\x00';
-      }
+bool MachObjectWriter::getARMFixupKindMachOInfo(unsigned Kind, unsigned &RelocType,
+                                                unsigned &Log2Size) {
+  RelocType = unsigned(macho::RIT_Vanilla);
+  Log2Size = ~0U;
 
-      MachSymbolData MSD;
-      MSD.SymbolData = it;
-      MSD.StringIndex = Entry;
-
-      if (Symbol.isUndefined()) {
-        MSD.SectionIndex = 0;
-        UndefinedSymbolData.push_back(MSD);
-      } else if (Symbol.isAbsolute()) {
-        MSD.SectionIndex = 0;
-        ExternalSymbolData.push_back(MSD);
-      } else {
-        MSD.SectionIndex = SectionIndexMap.lookup(&Symbol.getSection());
-        assert(MSD.SectionIndex && "Invalid section index!");
-        ExternalSymbolData.push_back(MSD);
+  switch (Kind) {
+  default:
+    return false;
+
+  case FK_Data_1:
+    Log2Size = llvm::Log2_32(1);
+    return true;
+  case FK_Data_2:
+    Log2Size = llvm::Log2_32(2);
+    return true;
+  case FK_Data_4:
+    Log2Size = llvm::Log2_32(4);
+    return true;
+  case FK_Data_8:
+    Log2Size = llvm::Log2_32(8);
+    return true;
+
+    // Handle 24-bit branch kinds.
+  case ARM::fixup_arm_ldst_pcrel_12:
+  case ARM::fixup_arm_pcrel_10:
+  case ARM::fixup_arm_adr_pcrel_12:
+  case ARM::fixup_arm_condbranch:
+  case ARM::fixup_arm_uncondbranch:
+    RelocType = unsigned(macho::RIT_ARM_Branch24Bit);
+    // Report as 'long', even though that is not quite accurate.
+    Log2Size = llvm::Log2_32(4);
+    return true;
+
+    // Handle Thumb branches.
+  case ARM::fixup_arm_thumb_br:
+    RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);
+    Log2Size = llvm::Log2_32(2);
+    return true;
+      
+  case ARM::fixup_arm_thumb_bl:
+  case ARM::fixup_arm_thumb_blx:
+    RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);
+    Log2Size = llvm::Log2_32(4);
+    return true;
+
+  case ARM::fixup_arm_movt_hi16:
+  case ARM::fixup_arm_movt_hi16_pcrel:
+  case ARM::fixup_t2_movt_hi16:
+  case ARM::fixup_t2_movt_hi16_pcrel:
+    RelocType = unsigned(macho::RIT_ARM_HalfDifference);
+    // Report as 'long', even though that is not quite accurate.
+    Log2Size = llvm::Log2_32(4);
+    return true;
+
+  case ARM::fixup_arm_movw_lo16:
+  case ARM::fixup_arm_movw_lo16_pcrel:
+  case ARM::fixup_t2_movw_lo16:
+  case ARM::fixup_t2_movw_lo16_pcrel:
+    RelocType = unsigned(macho::RIT_ARM_Half);
+    // Report as 'long', even though that is not quite accurate.
+    Log2Size = llvm::Log2_32(4);
+    return true;
+  }
+}
+void MachObjectWriter::RecordARMRelocation(const MCAssembler &Asm,
+                                           const MCAsmLayout &Layout,
+                                           const MCFragment *Fragment,
+                                           const MCFixup &Fixup,
+                                           MCValue Target,
+                                           uint64_t &FixedValue) {
+  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned Log2Size;
+  unsigned RelocType = macho::RIT_Vanilla;
+  if (!getARMFixupKindMachOInfo(Fixup.getKind(), RelocType, Log2Size)) {
+    report_fatal_error("unknown ARM fixup kind!");
+    return;
+  }
+
+  // If this is a difference or a defined symbol plus an offset, then we need a
+  // scattered relocation entry.  Differences always require scattered
+  // relocations.
+  if (Target.getSymB()) {
+    if (RelocType == macho::RIT_ARM_Half ||
+        RelocType == macho::RIT_ARM_HalfDifference)
+      return RecordARMMovwMovtRelocation(Asm, Layout, Fragment, Fixup,
+                                         Target, FixedValue);
+    return RecordARMScatteredRelocation(Asm, Layout, Fragment, Fixup,
+                                        Target, Log2Size, FixedValue);
+  }
+
+  // Get the symbol data, if any.
+  MCSymbolData *SD = 0;
+  if (Target.getSymA())
+    SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
+
+  // FIXME: For other platforms, we need to use scattered relocations for
+  // internal relocations with offsets.  If this is an internal relocation with
+  // an offset, it also needs a scattered relocation entry.
+  //
+  // Is this right for ARM?
+  uint32_t Offset = Target.getConstant();
+  if (IsPCRel && RelocType == macho::RIT_Vanilla)
+    Offset += 1 << Log2Size;
+  if (Offset && SD && !doesSymbolRequireExternRelocation(SD))
+    return RecordARMScatteredRelocation(Asm, Layout, Fragment, Fixup, Target,
+                                        Log2Size, FixedValue);
+
+  // See <reloc.h>.
+  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned Index = 0;
+  unsigned IsExtern = 0;
+  unsigned Type = 0;
+
+  if (Target.isAbsolute()) { // constant
+    // FIXME!
+    report_fatal_error("FIXME: relocations to absolute targets "
+                       "not yet implemented");
+  } else {
+    // Resolve constant variables.
+    if (SD->getSymbol().isVariable()) {
+      int64_t Res;
+      if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute(
+            Res, Layout, SectionAddress)) {
+        FixedValue = Res;
+        return;
       }
     }
 
-    // Now add the data for local symbols.
-    for (MCAssembler::symbol_iterator it = Asm.symbol_begin(),
-           ie = Asm.symbol_end(); it != ie; ++it) {
-      const MCSymbol &Symbol = it->getSymbol();
-
-      // Ignore non-linker visible symbols.
-      if (!Asm.isSymbolLinkerVisible(it->getSymbol()))
-        continue;
-
-      if (it->isExternal() || Symbol.isUndefined())
-        continue;
-
-      uint64_t &Entry = StringIndexMap[Symbol.getName()];
-      if (!Entry) {
-        Entry = StringTable.size();
-        StringTable += Symbol.getName();
-        StringTable += '\x00';
-      }
+    // Check whether we need an external or internal relocation.
+    if (doesSymbolRequireExternRelocation(SD)) {
+      IsExtern = 1;
+      Index = SD->getIndex();
+
+      // For external relocations, make sure to offset the fixup value to
+      // compensate for the addend of the symbol address, if it was
+      // undefined. This occurs with weak definitions, for example.
+      if (!SD->Symbol->isUndefined())
+        FixedValue -= Layout.getSymbolOffset(SD);
+    } else {
+      // The index is the section ordinal (1-based).
+      const MCSectionData &SymSD = Asm.getSectionData(
+        SD->getSymbol().getSection());
+      Index = SymSD.getOrdinal() + 1;
+      FixedValue += getSectionAddress(&SymSD);
+    }
+    if (IsPCRel)
+      FixedValue -= getSectionAddress(Fragment->getParent());
 
-      MachSymbolData MSD;
-      MSD.SymbolData = it;
-      MSD.StringIndex = Entry;
-
-      if (Symbol.isAbsolute()) {
-        MSD.SectionIndex = 0;
-        LocalSymbolData.push_back(MSD);
-      } else {
-        MSD.SectionIndex = SectionIndexMap.lookup(&Symbol.getSection());
-        assert(MSD.SectionIndex && "Invalid section index!");
-        LocalSymbolData.push_back(MSD);
+    // The type is determined by the fixup kind.
+    Type = RelocType;
+  }
+
+  // struct relocation_info (8 bytes)
+  macho::RelocationEntry MRE;
+  MRE.Word0 = FixupOffset;
+  MRE.Word1 = ((Index     <<  0) |
+               (IsPCRel   << 24) |
+               (Log2Size  << 25) |
+               (IsExtern  << 27) |
+               (Type      << 28));
+  Relocations[Fragment->getParent()].push_back(MRE);
+}
+
+void MachObjectWriter::RecordRelocation(const MCAssembler &Asm,
+                                        const MCAsmLayout &Layout,
+                                        const MCFragment *Fragment,
+                                        const MCFixup &Fixup,
+                                        MCValue Target,
+                                        uint64_t &FixedValue) {
+  // FIXME: These needs to be factored into the target Mach-O writer.
+  if (isARM()) {
+    RecordARMRelocation(Asm, Layout, Fragment, Fixup, Target, FixedValue);
+    return;
+  }
+  if (is64Bit()) {
+    RecordX86_64Relocation(Asm, Layout, Fragment, Fixup, Target, FixedValue);
+    return;
+  }
+
+  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
+
+  // If this is a 32-bit TLVP reloc it's handled a bit differently.
+  if (Target.getSymA() &&
+      Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP) {
+    RecordTLVPRelocation(Asm, Layout, Fragment, Fixup, Target, FixedValue);
+    return;
+  }
+
+  // If this is a difference or a defined symbol plus an offset, then we need a
+  // scattered relocation entry. Differences always require scattered
+  // relocations.
+  if (Target.getSymB())
+    return RecordScatteredRelocation(Asm, Layout, Fragment, Fixup,
+                                     Target, Log2Size, FixedValue);
+
+  // Get the symbol data, if any.
+  MCSymbolData *SD = 0;
+  if (Target.getSymA())
+    SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
+
+  // If this is an internal relocation with an offset, it also needs a scattered
+  // relocation entry.
+  uint32_t Offset = Target.getConstant();
+  if (IsPCRel)
+    Offset += 1 << Log2Size;
+  if (Offset && SD && !doesSymbolRequireExternRelocation(SD))
+    return RecordScatteredRelocation(Asm, Layout, Fragment, Fixup,
+                                     Target, Log2Size, FixedValue);
+
+  // See <reloc.h>.
+  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned Index = 0;
+  unsigned IsExtern = 0;
+  unsigned Type = 0;
+
+  if (Target.isAbsolute()) { // constant
+    // SymbolNum of 0 indicates the absolute section.
+    //
+    // FIXME: Currently, these are never generated (see code below). I cannot
+    // find a case where they are actually emitted.
+    Type = macho::RIT_Vanilla;
+  } else {
+    // Resolve constant variables.
+    if (SD->getSymbol().isVariable()) {
+      int64_t Res;
+      if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute(
+            Res, Layout, SectionAddress)) {
+        FixedValue = Res;
+        return;
       }
     }
 
-    // External and undefined symbols are required to be in lexicographic order.
-    std::sort(ExternalSymbolData.begin(), ExternalSymbolData.end());
-    std::sort(UndefinedSymbolData.begin(), UndefinedSymbolData.end());
+    // Check whether we need an external or internal relocation.
+    if (doesSymbolRequireExternRelocation(SD)) {
+      IsExtern = 1;
+      Index = SD->getIndex();
+      // For external relocations, make sure to offset the fixup value to
+      // compensate for the addend of the symbol address, if it was
+      // undefined. This occurs with weak definitions, for example.
+      if (!SD->Symbol->isUndefined())
+        FixedValue -= Layout.getSymbolOffset(SD);
+    } else {
+      // The index is the section ordinal (1-based).
+      const MCSectionData &SymSD = Asm.getSectionData(
+        SD->getSymbol().getSection());
+      Index = SymSD.getOrdinal() + 1;
+      FixedValue += getSectionAddress(&SymSD);
+    }
+    if (IsPCRel)
+      FixedValue -= getSectionAddress(Fragment->getParent());
 
-    // Set the symbol indices.
-    Index = 0;
-    for (unsigned i = 0, e = LocalSymbolData.size(); i != e; ++i)
-      LocalSymbolData[i].SymbolData->setIndex(Index++);
-    for (unsigned i = 0, e = ExternalSymbolData.size(); i != e; ++i)
-      ExternalSymbolData[i].SymbolData->setIndex(Index++);
-    for (unsigned i = 0, e = UndefinedSymbolData.size(); i != e; ++i)
-      UndefinedSymbolData[i].SymbolData->setIndex(Index++);
+    Type = macho::RIT_Vanilla;
+  }
 
-    // The string table is padded to a multiple of 4.
-    while (StringTable.size() % 4)
-      StringTable += '\x00';
+  // struct relocation_info (8 bytes)
+  macho::RelocationEntry MRE;
+  MRE.Word0 = FixupOffset;
+  MRE.Word1 = ((Index     <<  0) |
+               (IsPCRel   << 24) |
+               (Log2Size  << 25) |
+               (IsExtern  << 27) |
+               (Type      << 28));
+  Relocations[Fragment->getParent()].push_back(MRE);
+}
+
+void MachObjectWriter::BindIndirectSymbols(MCAssembler &Asm) {
+  // This is the point where 'as' creates actual symbols for indirect symbols
+  // (in the following two passes). It would be easier for us to do this sooner
+  // when we see the attribute, but that makes getting the order in the symbol
+  // table much more complicated than it is worth.
+  //
+  // FIXME: Revisit this when the dust settles.
+
+  // Bind non lazy symbol pointers first.
+  unsigned IndirectIndex = 0;
+  for (MCAssembler::indirect_symbol_iterator it = Asm.indirect_symbol_begin(),
+         ie = Asm.indirect_symbol_end(); it != ie; ++it, ++IndirectIndex) {
+    const MCSectionMachO &Section =
+      cast<MCSectionMachO>(it->SectionData->getSection());
+
+    if (Section.getType() != MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS)
+      continue;
+
+    // Initialize the section indirect symbol base, if necessary.
+    if (!IndirectSymBase.count(it->SectionData))
+      IndirectSymBase[it->SectionData] = IndirectIndex;
+
+    Asm.getOrCreateSymbolData(*it->Symbol);
   }
 
-  void computeSectionAddresses(const MCAssembler &Asm,
-                               const MCAsmLayout &Layout) {
-    uint64_t StartAddress = 0;
-    const SmallVectorImpl<MCSectionData*> &Order = Layout.getSectionOrder();
-    for (int i = 0, n = Order.size(); i != n ; ++i) {
-      const MCSectionData *SD = Order[i];
-      StartAddress = RoundUpToAlignment(StartAddress, SD->getAlignment());
-      SectionAddress[SD] = StartAddress;
-      StartAddress += Layout.getSectionAddressSize(SD);
-      // Explicitly pad the section to match the alignment requirements of the
-      // following one. This is for 'gas' compatibility, it shouldn't
-      /// strictly be necessary.
-      StartAddress += getPaddingSize(SD, Layout);
-    }
+  // Then lazy symbol pointers and symbol stubs.
+  IndirectIndex = 0;
+  for (MCAssembler::indirect_symbol_iterator it = Asm.indirect_symbol_begin(),
+         ie = Asm.indirect_symbol_end(); it != ie; ++it, ++IndirectIndex) {
+    const MCSectionMachO &Section =
+      cast<MCSectionMachO>(it->SectionData->getSection());
+
+    if (Section.getType() != MCSectionMachO::S_LAZY_SYMBOL_POINTERS &&
+        Section.getType() != MCSectionMachO::S_SYMBOL_STUBS)
+      continue;
+
+    // Initialize the section indirect symbol base, if necessary.
+    if (!IndirectSymBase.count(it->SectionData))
+      IndirectSymBase[it->SectionData] = IndirectIndex;
+
+    // Set the symbol type to undefined lazy, but only on construction.
+    //
+    // FIXME: Do not hardcode.
+    bool Created;
+    MCSymbolData &Entry = Asm.getOrCreateSymbolData(*it->Symbol, &Created);
+    if (Created)
+      Entry.setFlags(Entry.getFlags() | 0x0001);
   }
+}
+
+/// ComputeSymbolTable - Compute the symbol table data
+///
+/// \param StringTable [out] - The string table data.
+/// \param StringIndexMap [out] - Map from symbol names to offsets in the
+/// string table.
+void MachObjectWriter::ComputeSymbolTable(MCAssembler &Asm, SmallString<256> &StringTable,
+                                          std::vector<MachSymbolData> &LocalSymbolData,
+                                          std::vector<MachSymbolData> &ExternalSymbolData,
+                                          std::vector<MachSymbolData> &UndefinedSymbolData) {
+  // Build section lookup table.
+  DenseMap<const MCSection*, uint8_t> SectionIndexMap;
+  unsigned Index = 1;
+  for (MCAssembler::iterator it = Asm.begin(),
+         ie = Asm.end(); it != ie; ++it, ++Index)
+    SectionIndexMap[&it->getSection()] = Index;
+  assert(Index <= 256 && "Too many sections!");
+
+  // Index 0 is always the empty string.
+  StringMap<uint64_t> StringIndexMap;
+  StringTable += '\x00';
+
+  // Build the symbol arrays and the string table, but only for non-local
+  // symbols.
+  //
+  // The particular order that we collect the symbols and create the string
+  // table, then sort the symbols is chosen to match 'as'. Even though it
+  // doesn't matter for correctness, this is important for letting us diff .o
+  // files.
+  for (MCAssembler::symbol_iterator it = Asm.symbol_begin(),
+         ie = Asm.symbol_end(); it != ie; ++it) {
+    const MCSymbol &Symbol = it->getSymbol();
+
+    // Ignore non-linker visible symbols.
+    if (!Asm.isSymbolLinkerVisible(it->getSymbol()))
+      continue;
+
+    if (!it->isExternal() && !Symbol.isUndefined())
+      continue;
+
+    uint64_t &Entry = StringIndexMap[Symbol.getName()];
+    if (!Entry) {
+      Entry = StringTable.size();
+      StringTable += Symbol.getName();
+      StringTable += '\x00';
+    }
 
-  void ExecutePostLayoutBinding(MCAssembler &Asm, const MCAsmLayout &Layout) {
-    computeSectionAddresses(Asm, Layout);
-
-    // Create symbol data for any indirect symbols.
-    BindIndirectSymbols(Asm);
-
-    // Compute symbol table information and bind symbol indices.
-    ComputeSymbolTable(Asm, StringTable, LocalSymbolData, ExternalSymbolData,
-                       UndefinedSymbolData);
+    MachSymbolData MSD;
+    MSD.SymbolData = it;
+    MSD.StringIndex = Entry;
+
+    if (Symbol.isUndefined()) {
+      MSD.SectionIndex = 0;
+      UndefinedSymbolData.push_back(MSD);
+    } else if (Symbol.isAbsolute()) {
+      MSD.SectionIndex = 0;
+      ExternalSymbolData.push_back(MSD);
+    } else {
+      MSD.SectionIndex = SectionIndexMap.lookup(&Symbol.getSection());
+      assert(MSD.SectionIndex && "Invalid section index!");
+      ExternalSymbolData.push_back(MSD);
+    }
   }
 
-  virtual bool IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm,
-                                                      const MCSymbolData &DataA,
-                                                      const MCFragment &FB,
-                                                      bool InSet,
-                                                      bool IsPCRel) const {
-    if (InSet)
-      return true;
+  // Now add the data for local symbols.
+  for (MCAssembler::symbol_iterator it = Asm.symbol_begin(),
+         ie = Asm.symbol_end(); it != ie; ++it) {
+    const MCSymbol &Symbol = it->getSymbol();
 
-    // The effective address is
-    //     addr(atom(A)) + offset(A)
-    //   - addr(atom(B)) - offset(B)
-    // and the offsets are not relocatable, so the fixup is fully resolved when
-    //  addr(atom(A)) - addr(atom(B)) == 0.
-    const MCSymbolData *A_Base = 0, *B_Base = 0;
-
-    const MCSymbol &SA = DataA.getSymbol().AliasedSymbol();
-    const MCSection &SecA = SA.getSection();
-    const MCSection &SecB = FB.getParent()->getSection();
+    // Ignore non-linker visible symbols.
+    if (!Asm.isSymbolLinkerVisible(it->getSymbol()))
+      continue;
 
-    if (IsPCRel) {
-      // The simple (Darwin, except on x86_64) way of dealing with this was to
-      // assume that any reference to a temporary symbol *must* be a temporary
-      // symbol in the same atom, unless the sections differ. Therefore, any
-      // PCrel relocation to a temporary symbol (in the same section) is fully
-      // resolved. This also works in conjunction with absolutized .set, which
-      // requires the compiler to use .set to absolutize the differences between
-      // symbols which the compiler knows to be assembly time constants, so we
-      // don't need to worry about considering symbol differences fully
-      // resolved.
-
-      if (!Asm.getBackend().hasReliableSymbolDifference()) {
-        if (!SA.isTemporary() || !SA.isInSection() || &SecA != &SecB)
-          return false;
-        return true;
-      }
+    if (it->isExternal() || Symbol.isUndefined())
+      continue;
+
+    uint64_t &Entry = StringIndexMap[Symbol.getName()];
+    if (!Entry) {
+      Entry = StringTable.size();
+      StringTable += Symbol.getName();
+      StringTable += '\x00';
+    }
+
+    MachSymbolData MSD;
+    MSD.SymbolData = it;
+    MSD.StringIndex = Entry;
+
+    if (Symbol.isAbsolute()) {
+      MSD.SectionIndex = 0;
+      LocalSymbolData.push_back(MSD);
     } else {
-      if (!TargetObjectWriter->useAggressiveSymbolFolding())
-        return false;
+      MSD.SectionIndex = SectionIndexMap.lookup(&Symbol.getSection());
+      assert(MSD.SectionIndex && "Invalid section index!");
+      LocalSymbolData.push_back(MSD);
     }
+  }
 
-    const MCFragment &FA = *Asm.getSymbolData(SA).getFragment();
+  // External and undefined symbols are required to be in lexicographic order.
+  std::sort(ExternalSymbolData.begin(), ExternalSymbolData.end());
+  std::sort(UndefinedSymbolData.begin(), UndefinedSymbolData.end());
+
+  // Set the symbol indices.
+  Index = 0;
+  for (unsigned i = 0, e = LocalSymbolData.size(); i != e; ++i)
+    LocalSymbolData[i].SymbolData->setIndex(Index++);
+  for (unsigned i = 0, e = ExternalSymbolData.size(); i != e; ++i)
+    ExternalSymbolData[i].SymbolData->setIndex(Index++);
+  for (unsigned i = 0, e = UndefinedSymbolData.size(); i != e; ++i)
+    UndefinedSymbolData[i].SymbolData->setIndex(Index++);
 
-    A_Base = FA.getAtom();
-    if (!A_Base)
-      return false;
+  // The string table is padded to a multiple of 4.
+  while (StringTable.size() % 4)
+    StringTable += '\x00';
+}
 
-    B_Base = FB.getAtom();
-    if (!B_Base)
-      return false;
+void MachObjectWriter::computeSectionAddresses(const MCAssembler &Asm,
+                                               const MCAsmLayout &Layout) {
+  uint64_t StartAddress = 0;
+  const SmallVectorImpl<MCSectionData*> &Order = Layout.getSectionOrder();
+  for (int i = 0, n = Order.size(); i != n ; ++i) {
+    const MCSectionData *SD = Order[i];
+    StartAddress = RoundUpToAlignment(StartAddress, SD->getAlignment());
+    SectionAddress[SD] = StartAddress;
+    StartAddress += Layout.getSectionAddressSize(SD);
+
+    // Explicitly pad the section to match the alignment requirements of the
+    // following one. This is for 'gas' compatibility, it shouldn't
+    /// strictly be necessary.
+    StartAddress += getPaddingSize(SD, Layout);
+  }
+}
+
+void MachObjectWriter::ExecutePostLayoutBinding(MCAssembler &Asm, const MCAsmLayout &Layout) {
+  computeSectionAddresses(Asm, Layout);
+
+  // Create symbol data for any indirect symbols.
+  BindIndirectSymbols(Asm);
+
+  // Compute symbol table information and bind symbol indices.
+  ComputeSymbolTable(Asm, StringTable, LocalSymbolData, ExternalSymbolData,
+                     UndefinedSymbolData);
+}
+
+bool MachObjectWriter::IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm,
+                                                              const MCSymbolData &DataA,
+                                                              const MCFragment &FB,
+                                                              bool InSet,
+                                                              bool IsPCRel) const {
+  if (InSet)
+    return true;
+
+  // The effective address is
+  //     addr(atom(A)) + offset(A)
+  //   - addr(atom(B)) - offset(B)
+  // and the offsets are not relocatable, so the fixup is fully resolved when
+  //  addr(atom(A)) - addr(atom(B)) == 0.
+  const MCSymbolData *A_Base = 0, *B_Base = 0;
+
+  const MCSymbol &SA = DataA.getSymbol().AliasedSymbol();
+  const MCSection &SecA = SA.getSection();
+  const MCSection &SecB = FB.getParent()->getSection();
+
+  if (IsPCRel) {
+    // The simple (Darwin, except on x86_64) way of dealing with this was to
+    // assume that any reference to a temporary symbol *must* be a temporary
+    // symbol in the same atom, unless the sections differ. Therefore, any PCrel
+    // relocation to a temporary symbol (in the same section) is fully
+    // resolved. This also works in conjunction with absolutized .set, which
+    // requires the compiler to use .set to absolutize the differences between
+    // symbols which the compiler knows to be assembly time constants, so we
+    // don't need to worry about considering symbol differences fully resolved.
 
-    // If the atoms are the same, they are guaranteed to have the same address.
-    if (A_Base == B_Base)
+    if (!Asm.getBackend().hasReliableSymbolDifference()) {
+      if (!SA.isTemporary() || !SA.isInSection() || &SecA != &SecB)
+        return false;
       return true;
+    }
+  } else {
+    if (!TargetObjectWriter->useAggressiveSymbolFolding())
+      return false;
+  }
+
+  const MCFragment &FA = *Asm.getSymbolData(SA).getFragment();
 
-    // Otherwise, we can't prove this is fully resolved.
+  A_Base = FA.getAtom();
+  if (!A_Base)
     return false;
-  }
 
-  void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout) {
-    unsigned NumSections = Asm.size();
+  B_Base = FB.getAtom();
+  if (!B_Base)
+    return false;
 
-    // The section data starts after the header, the segment load command (and
-    // section headers) and the symbol table.
-    unsigned NumLoadCommands = 1;
-    uint64_t LoadCommandsSize = is64Bit() ?
-      macho::SegmentLoadCommand64Size + NumSections * macho::Section64Size :
-      macho::SegmentLoadCommand32Size + NumSections * macho::Section32Size;
-
-    // Add the symbol table load command sizes, if used.
-    unsigned NumSymbols = LocalSymbolData.size() + ExternalSymbolData.size() +
-      UndefinedSymbolData.size();
-    if (NumSymbols) {
-      NumLoadCommands += 2;
-      LoadCommandsSize += (macho::SymtabLoadCommandSize +
-                           macho::DysymtabLoadCommandSize);
-    }
-
-    // Compute the total size of the section data, as well as its file size and
-    // vm size.
-    uint64_t SectionDataStart = (is64Bit() ? macho::Header64Size :
-                                 macho::Header32Size) + LoadCommandsSize;
-    uint64_t SectionDataSize = 0;
-    uint64_t SectionDataFileSize = 0;
-    uint64_t VMSize = 0;
-    for (MCAssembler::const_iterator it = Asm.begin(),
-           ie = Asm.end(); it != ie; ++it) {
-      const MCSectionData &SD = *it;
-      uint64_t Address = getSectionAddress(&SD);
-      uint64_t Size = Layout.getSectionAddressSize(&SD);
-      uint64_t FileSize = Layout.getSectionFileSize(&SD);
-      FileSize += getPaddingSize(&SD, Layout);
-
-      VMSize = std::max(VMSize, Address + Size);
+  // If the atoms are the same, they are guaranteed to have the same address.
+  if (A_Base == B_Base)
+    return true;
 
-      if (SD.getSection().isVirtualSection())
-        continue;
+  // Otherwise, we can't prove this is fully resolved.
+  return false;
+}
 
-      SectionDataSize = std::max(SectionDataSize, Address + Size);
-      SectionDataFileSize = std::max(SectionDataFileSize, Address + FileSize);
-    }
+void MachObjectWriter::WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout) {
+  unsigned NumSections = Asm.size();
 
-    // The section data is padded to 4 bytes.
-    //
-    // FIXME: Is this machine dependent?
-    unsigned SectionDataPadding = OffsetToAlignment(SectionDataFileSize, 4);
-    SectionDataFileSize += SectionDataPadding;
-
-    // Write the prolog, starting with the header and load command...
-    WriteHeader(NumLoadCommands, LoadCommandsSize,
-                Asm.getSubsectionsViaSymbols());
-    WriteSegmentLoadCommand(NumSections, VMSize,
-                            SectionDataStart, SectionDataSize);
-
-    // ... and then the section headers.
-    uint64_t RelocTableEnd = SectionDataStart + SectionDataFileSize;
-    for (MCAssembler::const_iterator it = Asm.begin(),
-           ie = Asm.end(); it != ie; ++it) {
-      std::vector<macho::RelocationEntry> &Relocs = Relocations[it];
-      unsigned NumRelocs = Relocs.size();
-      uint64_t SectionStart = SectionDataStart + getSectionAddress(it);
-      WriteSection(Asm, Layout, *it, SectionStart, RelocTableEnd, NumRelocs);
-      RelocTableEnd += NumRelocs * macho::RelocationInfoSize;
-    }
-
-    // Write the symbol table load command, if used.
-    if (NumSymbols) {
-      unsigned FirstLocalSymbol = 0;
-      unsigned NumLocalSymbols = LocalSymbolData.size();
-      unsigned FirstExternalSymbol = FirstLocalSymbol + NumLocalSymbols;
-      unsigned NumExternalSymbols = ExternalSymbolData.size();
-      unsigned FirstUndefinedSymbol = FirstExternalSymbol + NumExternalSymbols;
-      unsigned NumUndefinedSymbols = UndefinedSymbolData.size();
-      unsigned NumIndirectSymbols = Asm.indirect_symbol_size();
-      unsigned NumSymTabSymbols =
-        NumLocalSymbols + NumExternalSymbols + NumUndefinedSymbols;
-      uint64_t IndirectSymbolSize = NumIndirectSymbols * 4;
-      uint64_t IndirectSymbolOffset = 0;
-
-      // If used, the indirect symbols are written after the section data.
-      if (NumIndirectSymbols)
-        IndirectSymbolOffset = RelocTableEnd;
-
-      // The symbol table is written after the indirect symbol data.
-      uint64_t SymbolTableOffset = RelocTableEnd + IndirectSymbolSize;
-
-      // The string table is written after symbol table.
-      uint64_t StringTableOffset =
-        SymbolTableOffset + NumSymTabSymbols * (is64Bit() ? macho::Nlist64Size :
-                                                macho::Nlist32Size);
-      WriteSymtabLoadCommand(SymbolTableOffset, NumSymTabSymbols,
-                             StringTableOffset, StringTable.size());
-
-      WriteDysymtabLoadCommand(FirstLocalSymbol, NumLocalSymbols,
-                               FirstExternalSymbol, NumExternalSymbols,
-                               FirstUndefinedSymbol, NumUndefinedSymbols,
-                               IndirectSymbolOffset, NumIndirectSymbols);
-    }
-
-    // Write the actual section data.
-    for (MCAssembler::const_iterator it = Asm.begin(),
-           ie = Asm.end(); it != ie; ++it) {
-      Asm.WriteSectionData(it, Layout);
-
-      uint64_t Pad = getPaddingSize(it, Layout);
-      for (unsigned int i = 0; i < Pad; ++i)
-        Write8(0);
-    }
-
-    // Write the extra padding.
-    WriteZeros(SectionDataPadding);
-
-    // Write the relocation entries.
-    for (MCAssembler::const_iterator it = Asm.begin(),
-           ie = Asm.end(); it != ie; ++it) {
-      // Write the section relocation entries, in reverse order to match 'as'
-      // (approximately, the exact algorithm is more complicated than this).
-      std::vector<macho::RelocationEntry> &Relocs = Relocations[it];
-      for (unsigned i = 0, e = Relocs.size(); i != e; ++i) {
-        Write32(Relocs[e - i - 1].Word0);
-        Write32(Relocs[e - i - 1].Word1);
-      }
-    }
+  // The section data starts after the header, the segment load command (and
+  // section headers) and the symbol table.
+  unsigned NumLoadCommands = 1;
+  uint64_t LoadCommandsSize = is64Bit() ?
+    macho::SegmentLoadCommand64Size + NumSections * macho::Section64Size :
+    macho::SegmentLoadCommand32Size + NumSections * macho::Section32Size;
+
+  // Add the symbol table load command sizes, if used.
+  unsigned NumSymbols = LocalSymbolData.size() + ExternalSymbolData.size() +
+    UndefinedSymbolData.size();
+  if (NumSymbols) {
+    NumLoadCommands += 2;
+    LoadCommandsSize += (macho::SymtabLoadCommandSize +
+                         macho::DysymtabLoadCommandSize);
+  }
+
+  // Compute the total size of the section data, as well as its file size and vm
+  // size.
+  uint64_t SectionDataStart = (is64Bit() ? macho::Header64Size :
+                               macho::Header32Size) + LoadCommandsSize;
+  uint64_t SectionDataSize = 0;
+  uint64_t SectionDataFileSize = 0;
+  uint64_t VMSize = 0;
+  for (MCAssembler::const_iterator it = Asm.begin(),
+         ie = Asm.end(); it != ie; ++it) {
+    const MCSectionData &SD = *it;
+    uint64_t Address = getSectionAddress(&SD);
+    uint64_t Size = Layout.getSectionAddressSize(&SD);
+    uint64_t FileSize = Layout.getSectionFileSize(&SD);
+    FileSize += getPaddingSize(&SD, Layout);
+
+    VMSize = std::max(VMSize, Address + Size);
 
-    // Write the symbol table data, if used.
-    if (NumSymbols) {
-      // Write the indirect symbol entries.
-      for (MCAssembler::const_indirect_symbol_iterator
-             it = Asm.indirect_symbol_begin(),
-             ie = Asm.indirect_symbol_end(); it != ie; ++it) {
-        // Indirect symbols in the non lazy symbol pointer section have some
-        // special handling.
-        const MCSectionMachO &Section =
-          static_cast<const MCSectionMachO&>(it->SectionData->getSection());
-        if (Section.getType() == MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS) {
-          // If this symbol is defined and internal, mark it as such.
-          if (it->Symbol->isDefined() &&
-              !Asm.getSymbolData(*it->Symbol).isExternal()) {
-            uint32_t Flags = macho::ISF_Local;
-            if (it->Symbol->isAbsolute())
-              Flags |= macho::ISF_Absolute;
-            Write32(Flags);
-            continue;
-          }
-        }
+    if (SD.getSection().isVirtualSection())
+      continue;
+
+    SectionDataSize = std::max(SectionDataSize, Address + Size);
+    SectionDataFileSize = std::max(SectionDataFileSize, Address + FileSize);
+  }
 
-        Write32(Asm.getSymbolData(*it->Symbol).getIndex());
+  // The section data is padded to 4 bytes.
+  //
+  // FIXME: Is this machine dependent?
+  unsigned SectionDataPadding = OffsetToAlignment(SectionDataFileSize, 4);
+  SectionDataFileSize += SectionDataPadding;
+
+  // Write the prolog, starting with the header and load command...
+  WriteHeader(NumLoadCommands, LoadCommandsSize,
+              Asm.getSubsectionsViaSymbols());
+  WriteSegmentLoadCommand(NumSections, VMSize,
+                          SectionDataStart, SectionDataSize);
+
+  // ... and then the section headers.
+  uint64_t RelocTableEnd = SectionDataStart + SectionDataFileSize;
+  for (MCAssembler::const_iterator it = Asm.begin(),
+         ie = Asm.end(); it != ie; ++it) {
+    std::vector<macho::RelocationEntry> &Relocs = Relocations[it];
+    unsigned NumRelocs = Relocs.size();
+    uint64_t SectionStart = SectionDataStart + getSectionAddress(it);
+    WriteSection(Asm, Layout, *it, SectionStart, RelocTableEnd, NumRelocs);
+    RelocTableEnd += NumRelocs * macho::RelocationInfoSize;
+  }
+
+  // Write the symbol table load command, if used.
+  if (NumSymbols) {
+    unsigned FirstLocalSymbol = 0;
+    unsigned NumLocalSymbols = LocalSymbolData.size();
+    unsigned FirstExternalSymbol = FirstLocalSymbol + NumLocalSymbols;
+    unsigned NumExternalSymbols = ExternalSymbolData.size();
+    unsigned FirstUndefinedSymbol = FirstExternalSymbol + NumExternalSymbols;
+    unsigned NumUndefinedSymbols = UndefinedSymbolData.size();
+    unsigned NumIndirectSymbols = Asm.indirect_symbol_size();
+    unsigned NumSymTabSymbols =
+      NumLocalSymbols + NumExternalSymbols + NumUndefinedSymbols;
+    uint64_t IndirectSymbolSize = NumIndirectSymbols * 4;
+    uint64_t IndirectSymbolOffset = 0;
+
+    // If used, the indirect symbols are written after the section data.
+    if (NumIndirectSymbols)
+      IndirectSymbolOffset = RelocTableEnd;
+
+    // The symbol table is written after the indirect symbol data.
+    uint64_t SymbolTableOffset = RelocTableEnd + IndirectSymbolSize;
+
+    // The string table is written after symbol table.
+    uint64_t StringTableOffset =
+      SymbolTableOffset + NumSymTabSymbols * (is64Bit() ? macho::Nlist64Size :
+                                              macho::Nlist32Size);
+    WriteSymtabLoadCommand(SymbolTableOffset, NumSymTabSymbols,
+                           StringTableOffset, StringTable.size());
+
+    WriteDysymtabLoadCommand(FirstLocalSymbol, NumLocalSymbols,
+                             FirstExternalSymbol, NumExternalSymbols,
+                             FirstUndefinedSymbol, NumUndefinedSymbols,
+                             IndirectSymbolOffset, NumIndirectSymbols);
+  }
+
+  // Write the actual section data.
+  for (MCAssembler::const_iterator it = Asm.begin(),
+         ie = Asm.end(); it != ie; ++it) {
+    Asm.WriteSectionData(it, Layout);
+
+    uint64_t Pad = getPaddingSize(it, Layout);
+    for (unsigned int i = 0; i < Pad; ++i)
+      Write8(0);
+  }
+
+  // Write the extra padding.
+  WriteZeros(SectionDataPadding);
+
+  // Write the relocation entries.
+  for (MCAssembler::const_iterator it = Asm.begin(),
+         ie = Asm.end(); it != ie; ++it) {
+    // Write the section relocation entries, in reverse order to match 'as'
+    // (approximately, the exact algorithm is more complicated than this).
+    std::vector<macho::RelocationEntry> &Relocs = Relocations[it];
+    for (unsigned i = 0, e = Relocs.size(); i != e; ++i) {
+      Write32(Relocs[e - i - 1].Word0);
+      Write32(Relocs[e - i - 1].Word1);
+    }
+  }
+
+  // Write the symbol table data, if used.
+  if (NumSymbols) {
+    // Write the indirect symbol entries.
+    for (MCAssembler::const_indirect_symbol_iterator
+           it = Asm.indirect_symbol_begin(),
+           ie = Asm.indirect_symbol_end(); it != ie; ++it) {
+      // Indirect symbols in the non lazy symbol pointer section have some
+      // special handling.
+      const MCSectionMachO &Section =
+        static_cast<const MCSectionMachO&>(it->SectionData->getSection());
+      if (Section.getType() == MCSectionMachO::S_NON_LAZY_SYMBOL_POINTERS) {
+        // If this symbol is defined and internal, mark it as such.
+        if (it->Symbol->isDefined() &&
+            !Asm.getSymbolData(*it->Symbol).isExternal()) {
+          uint32_t Flags = macho::ISF_Local;
+          if (it->Symbol->isAbsolute())
+            Flags |= macho::ISF_Absolute;
+          Write32(Flags);
+          continue;
+        }
       }
 
-      // FIXME: Check that offsets match computed ones.
+      Write32(Asm.getSymbolData(*it->Symbol).getIndex());
+    }
 
-      // Write the symbol table entries.
-      for (unsigned i = 0, e = LocalSymbolData.size(); i != e; ++i)
-        WriteNlist(LocalSymbolData[i], Layout);
-      for (unsigned i = 0, e = ExternalSymbolData.size(); i != e; ++i)
-        WriteNlist(ExternalSymbolData[i], Layout);
-      for (unsigned i = 0, e = UndefinedSymbolData.size(); i != e; ++i)
-        WriteNlist(UndefinedSymbolData[i], Layout);
+    // FIXME: Check that offsets match computed ones.
 
-      // Write the string table.
-      OS << StringTable.str();
-    }
-  }
-};
+    // Write the symbol table entries.
+    for (unsigned i = 0, e = LocalSymbolData.size(); i != e; ++i)
+      WriteNlist(LocalSymbolData[i], Layout);
+    for (unsigned i = 0, e = ExternalSymbolData.size(); i != e; ++i)
+      WriteNlist(ExternalSymbolData[i], Layout);
+    for (unsigned i = 0, e = UndefinedSymbolData.size(); i != e; ++i)
+      WriteNlist(UndefinedSymbolData[i], Layout);
 
+    // Write the string table.
+    OS << StringTable.str();
+  }
 }
 
 MCObjectWriter *llvm::createMachObjectWriter(MCMachObjectTargetWriter *MOTW,



From mcrosier at apple.com  Wed Jun 22 16:13:23 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Wed, 22 Jun 2011 21:13:23 -0000
Subject: [llvm-commits] [llvm] r133646 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
Message-ID: <20110622211323.62F8C2A6C12C@llvm.org>

Author: mcrosier
Date: Wed Jun 22 16:13:23 2011
New Revision: 133646

URL: http://llvm.org/viewvc/llvm-project?rev=133646&view=rev
Log:
Revert r133607.  This is causing failures in the Clang gccTestSuite.
Specifically, gcc.c-torture/compile/pr21356.c.

Modified:
    llvm/trunk/lib/CodeGen/TailDuplication.cpp

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133646&r1=133645&r2=133646&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Wed Jun 22 16:13:23 2011
@@ -568,9 +568,9 @@
 TailDuplicatePass::isSimpleBB(MachineBasicBlock *TailBB) {
   if (TailBB->succ_size() != 1)
     return false;
-  MachineBasicBlock::iterator I = TailBB->begin();
+  MachineBasicBlock::iterator I = TailBB->getFirstNonPHI();
   MachineBasicBlock::iterator E = TailBB->end();
-  while (I != E && I->isDebugValue())
+  while (I->isDebugValue() && I != E)
     ++I;
   if (I == E)
     return true;
@@ -712,7 +712,7 @@
   DenseSet<unsigned> UsedByPhi;
   getRegsUsedByPHIs(*TailBB, &UsedByPhi);
 
-  if (isSimpleBB(TailBB))
+  if (0 && isSimpleBB(TailBB))
     return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
 
   // Iterate through all the unique predecessors and tail-duplicate this



From nicholas at mxc.ca  Wed Jun 22 16:13:46 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Wed, 22 Jun 2011 21:13:46 -0000
Subject: [llvm-commits] [llvm] r133648 - in /llvm/trunk:
 lib/Support/ConstantRange.cpp unittests/Support/ConstantRangeTest.cpp
Message-ID: <20110622211346.4EB992A6C12C@llvm.org>

Author: nicholas
Date: Wed Jun 22 16:13:46 2011
New Revision: 133648

URL: http://llvm.org/viewvc/llvm-project?rev=133648&view=rev
Log:
Fix the implementation of ConstantRange::sub(ConstantRange). Patch by Xi Wang!

Modified:
    llvm/trunk/lib/Support/ConstantRange.cpp
    llvm/trunk/unittests/Support/ConstantRangeTest.cpp

Modified: llvm/trunk/lib/Support/ConstantRange.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/ConstantRange.cpp?rev=133648&r1=133647&r2=133648&view=diff
==============================================================================
--- llvm/trunk/lib/Support/ConstantRange.cpp (original)
+++ llvm/trunk/lib/Support/ConstantRange.cpp Wed Jun 22 16:13:46 2011
@@ -529,8 +529,8 @@
     return ConstantRange(getBitWidth(), /*isFullSet=*/true);
 
   APInt Spread_X = getSetSize(), Spread_Y = Other.getSetSize();
-  APInt NewLower = getLower() - Other.getLower();
-  APInt NewUpper = getUpper() - Other.getUpper() + 1;
+  APInt NewLower = getLower() - Other.getUpper() + 1;
+  APInt NewUpper = getUpper() - Other.getLower();
   if (NewLower == NewUpper)
     return ConstantRange(getBitWidth(), /*isFullSet=*/true);
 

Modified: llvm/trunk/unittests/Support/ConstantRangeTest.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/unittests/Support/ConstantRangeTest.cpp?rev=133648&r1=133647&r2=133648&view=diff
==============================================================================
--- llvm/trunk/unittests/Support/ConstantRangeTest.cpp (original)
+++ llvm/trunk/unittests/Support/ConstantRangeTest.cpp Wed Jun 22 16:13:46 2011
@@ -299,6 +299,8 @@
   EXPECT_EQ(Empty.sub(APInt(16, 4)), Empty);
   EXPECT_EQ(Some.sub(APInt(16, 4)),
             ConstantRange(APInt(16, 0x6), APInt(16, 0xaa6)));
+  EXPECT_EQ(Some.sub(Some),
+            ConstantRange(APInt(16, 0xf561), APInt(16, 0xaa0)));
   EXPECT_EQ(Wrap.sub(APInt(16, 4)),
             ConstantRange(APInt(16, 0xaa6), APInt(16, 0x6)));
   EXPECT_EQ(One.sub(APInt(16, 4)),



From nlewycky at google.com  Wed Jun 22 16:19:38 2011
From: nlewycky at google.com (Nick Lewycky)
Date: Wed, 22 Jun 2011 14:19:38 -0700
Subject: [llvm-commits] [PATCH] ConstantRange::sub
In-Reply-To: <C2134A6C-D40F-4FB8-8E56-83FECE214028@gmail.com>
References: <01F9FA28-E4FB-4D8A-9A67-C445041842B9@gmail.com>
	<BANLkTi=+_0p=U2dWHwnjz-M2N3MtX5Z-DaFM7fQt+WD2J4e-RA@mail.gmail.com>
	<4B12B5B1-CFC3-40CA-9F02-D3D7D5378F5B@gmail.com>
	<BANLkTik5fX8V72x_in=7qXxqcOjBbVwdXWO3SrzLQdK9K_zwiQ@mail.gmail.com>
	<C2134A6C-D40F-4FB8-8E56-83FECE214028@gmail.com>
Message-ID: <BANLkTikMhJdcZedxB2SYmWviKPgP+jjU6Q57+ScYMZNRif27fw@mail.gmail.com>

On 22 June 2011 14:09, Xi Wang <xi.wang at gmail.com> wrote:

> Here goes the patch along with a test for ConstantRange::sub.  Thanks.
>

Thanks! Committed as r133648.

Nick


>
>
>
> On Jun 22, 2011, at 3:57 PM, Nick Lewycky wrote:
>
> > On 22 June 2011 12:51, Xi Wang <xi.wang at gmail.com> wrote:
> > Sure.  I will submit a patch.
> >
> > BTW, what's the difference between the bounds I was expecting
> >
> > APInt NewLower = getLower() - Other.getUpper() + 1;
> > APInt NewUpper = getUpper() - Other.getLower();
> >
> > and the two you mentioned
> >
> > NewLower = Lower - (Upper-1)
> > NewUpper = (Upper-1) - Lower + 1
> >
> > They look equivalent to me.  Did I miss anything?  Thanks.
> >
> > ... they are. Sorry, I was just surprised to see the +1 on the NewLower
> (it always goes on the NewUpper instead, right), but I didn't actually
> simplify the expressions.
> >
> > It sounds to me like you've got this one handled. :-)
> >
> > Nick
> >
> >
> > - xi
> >
> > On Jun 22, 2011, at 2:39 PM, Nick Lewycky wrote:
> >
> > > Thanks, I think you've found a serious bug!
> > >
> > > Would you be willing to fix it? Please add a test to
> unittests/Support/ConstantRangeTest.cpp and then mail llvm-commits with the
> patch to fix it and add the test.
> > >
> > > On 20 June 2011 23:09, Xi Wang <xi.wang at gmail.com> wrote:
> > > Hi,
> > >
> > > I have a question about ConstantRange::sub(const ConstantRange &Other)
> at lib/Support/ConstantRange.cpp:524.  The code computes the new bounds as
> follows.
> > >
> > >  APInt NewLower = getLower() - Other.getLower();
> > >  APInt NewUpper = getUpper() - Other.getUpper() + 1;
> > >
> > > Could someone explain this to me?  I was expecting something like
> > >
> > >  APInt NewLower = getLower() - Other.getUpper() + 1;
> > >  APInt NewUpper = getUpper() - Other.getLower();
> > >
> > > These aren't quite right, I think it should be:
> > >
> > > NewLower = Lower - (Upper-1)
> > > NewUpper = (Upper-1) - Lower + 1
> > >
> > > Constant ranges are stored half-open, [lower, upper) which means that
> the upper value is one past the end of the range. I often think of the
> formula as newmax = max - min --> newupper - 1 = ((getUpper() - 1) -
> Other.getLower(). min = lower, while max = upper - 1.
> > >
> > > Nick
> >
> >
>
>
>
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From aggarwa4 at illinois.edu  Wed Jun 22 16:17:19 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Wed, 22 Jun 2011 21:17:19 -0000
Subject: [llvm-commits] [poolalloc] r133650 - in /poolalloc/trunk:
 lib/AssistDS/TypeChecks.cpp runtime/DynamicTypeChecks/TypeRuntime.cpp
Message-ID: <20110622211719.49B7B2A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Jun 22 16:17:19 2011
New Revision: 133650

URL: http://llvm.org/viewvc/llvm-project?rev=133650&view=rev
Log:
Create a separate TypeTagTy, to make it more flexible.

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133650&r1=133649&r2=133650&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Wed Jun 22 16:17:19 2011
@@ -60,6 +60,10 @@
 static const Type *Int32Ty = 0;
 static const Type *Int64Ty = 0;
 static const PointerType *VoidPtrTy = 0;
+
+static const Type *TypeTagTy = 0;
+static const Type *TypeTagPtrTy = 0;
+
 static Constant *One = 0;
 static Constant *Zero = 0;
 static Constant *RegisterArgv;
@@ -112,11 +116,11 @@
 }
 
 Constant *TypeChecks::getTypeMarkerConstant(Value * V) {
-  return ConstantInt::get(Int8Ty, getTypeMarker(V));
+  return ConstantInt::get(TypeTagTy, getTypeMarker(V));
 }
 
 Constant *TypeChecks::getTypeMarkerConstant(const Type *T) {
-  return ConstantInt::get(Int8Ty, getTypeMarker(T));
+  return ConstantInt::get(TypeTagTy, getTypeMarker(T));
 }
 
 bool TypeChecks::runOnModule(Module &M) {
@@ -131,6 +135,10 @@
   Int32Ty = IntegerType::getInt32Ty(M.getContext());
   Int64Ty = IntegerType::getInt64Ty(M.getContext());
   VoidPtrTy = PointerType::getUnqual(Int8Ty);
+
+  TypeTagTy = Int8Ty;
+  TypeTagPtrTy = PointerType::getUnqual(TypeTagTy);
+
   One = ConstantInt::get(Int64Ty, 1);
   Zero = ConstantInt::get(Int64Ty, 0);
 
@@ -146,7 +154,7 @@
   trackGlobal = M.getOrInsertFunction("trackGlobal",
                                       VoidTy,
                                       VoidPtrTy,/*ptr*/
-                                      Int8Ty,/*type*/
+                                      TypeTagTy,/*type*/
                                       Int64Ty,/*size*/
                                       Int32Ty,/*tag*/
                                       NULL);
@@ -172,7 +180,7 @@
   trackStoreInst = M.getOrInsertFunction("trackStoreInst",
                                          VoidTy,
                                          VoidPtrTy,/*ptr*/
-                                         Int8Ty,/*type*/
+                                         TypeTagTy,/*type*/
                                          Int64Ty,/*size*/
                                          Int32Ty,/*tag*/
                                          NULL);
@@ -180,20 +188,20 @@
                                      VoidTy,
                                      VoidPtrTy, /*ptr*/
                                      Int64Ty, /*size*/
-                                     VoidPtrTy, /*dest for type tag*/
+                                     TypeTagPtrTy, /*dest for type tag*/
                                      NULL);
   checkTypeInst = M.getOrInsertFunction("checkType",
                                         VoidTy,
-                                        Int8Ty,/*type*/
+                                        TypeTagTy,/*type*/
                                         Int64Ty,/*size*/
-                                        VoidPtrTy,
+                                        TypeTagPtrTy,/*ptr to metadata*/
                                         VoidPtrTy,/*ptr*/
                                         Int32Ty,/*tag*/
                                         NULL);
   setTypeInfo = M.getOrInsertFunction("setTypeInfo",
                                        VoidTy,
                                        VoidPtrTy,/*dest ptr*/
-                                       VoidPtrTy,/*metadata*/
+                                       TypeTagPtrTy,/*metadata*/
                                        Int64Ty,/*size*/
                                        Int32Ty,/*tag*/
                                        NULL);
@@ -213,7 +221,7 @@
                                     VoidTy,
                                     VoidPtrTy,/*va_list ptr*/
                                     Int64Ty,/*total num of elements in va_list */
-                                    VoidPtrTy,/*ptr to metadta*/
+                                    TypeTagPtrTy,/*ptr to metadta*/
                                     Int32Ty,/*tag*/
                                     NULL);
   copyVAInfo = M.getOrInsertFunction("copyVAInfo",
@@ -225,7 +233,7 @@
   checkVAArg = M.getOrInsertFunction("checkVAArgType",
                                      VoidTy,
                                      VoidPtrTy,/*va_list ptr*/
-                                     Int8Ty,/*type*/
+                                     TypeTagTy,/*type*/
                                      Int32Ty,/*tag*/
                                      NULL);
 
@@ -527,7 +535,7 @@
     unsigned int NumArgs = CI->getNumOperands() - 1;
     inst_iterator InsPt = inst_begin(CI->getParent()->getParent());
     Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs);
-    AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt);
+    AllocaInst *AI = new AllocaInst(TypeTagTy, NumArgsVal, "", &*InsPt);
     // set the metadata for the varargs in AI
     for(i = 1; i <CI->getNumOperands(); i++) {
       Value *Idx[2];
@@ -599,7 +607,7 @@
   // 1. Create the new argument types vector
   std::vector<const Type*> TP;
   TP.push_back(Int64Ty); // for count
-  TP.push_back(VoidPtrTy); // for MD
+  TP.push_back(TypeTagPtrTy); // for MD
   for(Function::arg_iterator I = F.arg_begin(); I !=F.arg_end(); ++I) {
     TP.push_back(I->getType());
   }
@@ -719,7 +727,7 @@
       unsigned int i;
       unsigned int NumArgs = II->getNumOperands() - 3;
       Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs);
-      AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt);
+      AllocaInst *AI = new AllocaInst(TypeTagTy, NumArgsVal, "", &*InsPt);
       // set the metadata for the varargs in AI
       for(i = 3; i <II->getNumOperands(); i++) {
         Value *Idx[2];
@@ -755,7 +763,7 @@
       unsigned int i;
       unsigned int NumArgs = CI->getNumOperands() - 1;
       Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs);
-      AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt);
+      AllocaInst *AI = new AllocaInst(TypeTagTy, NumArgsVal, "", &*InsPt);
       // set the metadata for the varargs in AI
       for(i = 1; i <CI->getNumOperands(); i++) {
         Value *Idx[2];
@@ -1122,30 +1130,30 @@
   return true;
 }
 
-  bool TypeChecks::visitMain(Module &M, Function &MainFunc) {
-    if(MainFunc.arg_size() < 2)
-      // No need to register
-      return false;
-
-    Function::arg_iterator AI = MainFunc.arg_begin();
-    Value *Argc = AI;
-    Value *Argv = ++AI;
-
-    Instruction *InsertPt = MainFunc.front().begin();
-    std::vector<Value *> fargs;
-    fargs.push_back (Argc);
-    fargs.push_back (Argv);
-    CallInst::Create (RegisterArgv, fargs.begin(), fargs.end(), "", InsertPt);
+bool TypeChecks::visitMain(Module &M, Function &MainFunc) {
+  if(MainFunc.arg_size() < 2)
+    // No need to register
+    return false;
 
-    if(MainFunc.arg_size() < 3)
-      return true;
+  Function::arg_iterator AI = MainFunc.arg_begin();
+  Value *Argc = AI;
+  Value *Argv = ++AI;
+
+  Instruction *InsertPt = MainFunc.front().begin();
+  std::vector<Value *> fargs;
+  fargs.push_back (Argc);
+  fargs.push_back (Argv);
+  CallInst::Create (RegisterArgv, fargs.begin(), fargs.end(), "", InsertPt);
 
-    Value *Envp = ++AI;
-    std::vector<Value*> Args;
-    Args.push_back(Envp);
-    CallInst::Create(RegisterEnvp, Args.begin(), Args.end(), "", InsertPt);
+  if(MainFunc.arg_size() < 3)
     return true;
-  }
+
+  Value *Envp = ++AI;
+  std::vector<Value*> Args;
+  Args.push_back(Envp);
+  CallInst::Create(RegisterEnvp, Args.begin(), Args.end(), "", InsertPt);
+  return true;
+}
 
 bool TypeChecks::visitGlobal(Module &M, GlobalVariable &GV, 
                              Constant *C, Instruction &I, SmallVector<Value *,8> Indices) {
@@ -1240,17 +1248,17 @@
   }
   return true;
 }
-bool TypeChecks::visitVAArgInst(Module &M, VAArgInst &VI) {
-  if(!VI.getParent()->getParent()->hasInternalLinkage())
+  bool TypeChecks::visitVAArgInst(Module &M, VAArgInst &VI) {
+    if(!VI.getParent()->getParent()->hasInternalLinkage())
+      return false;
+    CastInst *BCI = BitCastInst::CreatePointerCast(VI.getOperand(0), VoidPtrTy, "", &VI);
+    std::vector<Value *>Args;
+    Args.push_back(BCI);
+    Args.push_back(getTypeMarkerConstant(&VI));
+    Args.push_back(getTagCounter());
+    CallInst::Create(checkVAArg, Args.begin(), Args.end(), "", &VI);
     return false;
-  CastInst *BCI = BitCastInst::CreatePointerCast(VI.getOperand(0), VoidPtrTy, "", &VI);
-  std::vector<Value *>Args;
-  Args.push_back(BCI);
-  Args.push_back(getTypeMarkerConstant(&VI));
-  Args.push_back(getTagCounter());
-  CallInst::Create(checkVAArg, Args.begin(), Args.end(), "", &VI);
-  return false;
-}
+  }
 
 // Insert code to initialize meta data to bottom
 // Insert code to set objects to 0
@@ -1630,7 +1638,7 @@
   const FunctionType *FOldType = cast<FunctionType>((cast<PointerType>(OrigType))->getElementType());
   std::vector<const Type*>TP;
   TP.push_back(Int64Ty);
-  TP.push_back(VoidPtrTy);
+  TP.push_back(TypeTagPtrTy);
 
   for(llvm::FunctionType::param_iterator ArgI = FOldType->param_begin(); ArgI != FOldType->param_end(); ++ArgI)
     TP.push_back(*ArgI);
@@ -1640,14 +1648,11 @@
 
   inst_iterator InsPt = inst_begin(I->getParent()->getParent());
 
-
-
-
   if(isa<CallInst>(I)) {
     unsigned int NumArgs = I->getNumOperands() - 1;
     Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs);
 
-    AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt);
+    AllocaInst *AI = new AllocaInst(TypeTagTy, NumArgsVal, "", &*InsPt);
     for(unsigned int i = 1; i < I->getNumOperands(); i++) {
       Value *Idx[2];
       Idx[0] = ConstantInt::get(Int32Ty, i-1);
@@ -1675,7 +1680,7 @@
     unsigned int NumArgs = I->getNumOperands() - 3;
     Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs);
 
-    AllocaInst *AI = new AllocaInst(Int8Ty, NumArgsVal, "", &*InsPt);
+    AllocaInst *AI = new AllocaInst(TypeTagTy, NumArgsVal, "", &*InsPt);
     for(unsigned int i = 3; i < I->getNumOperands(); i++) {
       Value *Idx[2];
       Idx[0] = ConstantInt::get(Int32Ty, i-3);
@@ -1746,7 +1751,7 @@
   CastInst *BCI = BitCastInst::CreatePointerCast(LI.getPointerOperand(), VoidPtrTy, "", &LI);
 
   Value *Size = ConstantInt::get(Int32Ty, getSize(LI.getType()));
-  AllocaInst *AI = new AllocaInst(Int8Ty, Size, "", &*InsPt);
+  AllocaInst *AI = new AllocaInst(TypeTagTy, Size, "", &*InsPt);
   CastInst *BCI_MD = BitCastInst::CreatePointerCast(AI, VoidPtrTy, "", &*InsPt);
 
   std::vector<Value *>Args1;
@@ -1801,7 +1806,6 @@
     getTypeCall->eraseFromParent();
   }
 
-
   // Create the call to the runtime check and place it before the load instruction.
   numLoadChecks++;
   return true;

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=133650&r1=133649&r2=133650&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Wed Jun 22 16:17:19 2011
@@ -25,7 +25,7 @@
  * For now, run a version of the tool without the base fixed, and 
  * choose address.
  */
-#define BASE ((uint8_t *)(0x2aaaab88c000))
+#define BASE ((TypeTagTy *)(0x2aaaab88c000))
 /*
  * Do some macro magic to get mmap macros defined properly on all platforms.
  */
@@ -33,17 +33,19 @@
 # define MAP_ANONYMOUS MAP_ANON
 #endif /* defined(MAP_ANON) && !defined(MAP_ANONYMOUS) */
 
+typedef uint8_t TypeTagTy ;
+
 struct va_info {
   uint64_t numElements;
   uint64_t counter;
-  uint8_t *metadata;
+  TypeTagTy *metadata;
 };
 
 // Map to store info about va lists
 std::map<void *, struct va_info> VA_InfoMap;
 
 // Pointer to the shadow_memory
-uint8_t * const shadow_begin = BASE;
+TypeTagTy * const shadow_begin = BASE;
 
 // Map from type numbers to type names.
 extern char* typeNames[];
@@ -53,22 +55,22 @@
   void shadowInit();
   void trackArgvType(int argc, char **argv) ;
   void trackEnvpType(char **envp) ;
-  void trackGlobal(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) ;
+  void trackGlobal(void *ptr, TypeTagTy typeNumber, uint64_t size, uint32_t tag) ;
   void trackArray(void *ptr, uint64_t size, uint64_t count, uint32_t tag) ;
-  void trackStoreInst(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) ;
+  void trackStoreInst(void *ptr, TypeTagTy typeNumber, uint64_t size, uint32_t tag) ;
   void trackStringInput(void *ptr, uint32_t tag) ;
-  void compareTypes(uint8_t typeNumberSrc, uint8_t typeNumberDest, uint32_t tag) ;
+  void compareTypes(TypeTagTy typeNumberSrc, TypeTagTy typeNumberDest, uint32_t tag) ;
   void compareNumber(uint64_t NumArgsPassed, uint64_t ArgAccessed, uint32_t tag);
   void compareTypeAndNumber(uint64_t NumArgsPassed, uint64_t ArgAccessed, uint8_t TypeAccessed, void *MD, uint32_t tag) ;
-  void checkVAArgType(void *va_list, uint8_t TypeAccessed, uint32_t tag) ;
-  void getTypeTag(void *ptr, uint64_t size, uint8_t *dest) ;
-  void checkType(uint8_t typeNumber, uint64_t size, uint8_t *metadata, void *ptr, uint32_t tag);
+  void checkVAArgType(void *va_list, TypeTagTy TypeAccessed, uint32_t tag) ;
+  void getTypeTag(void *ptr, uint64_t size, TypeTagTy *dest) ;
+  void checkType(TypeTagTy typeNumber, uint64_t size, TypeTagTy *metadata, void *ptr, uint32_t tag);
   void trackInitInst(void *ptr, uint64_t size, uint32_t tag) ;
   void trackUnInitInst(void *ptr, uint64_t size, uint32_t tag) ;
   void copyTypeInfo(void *dstptr, void *srcptr, uint64_t size, uint32_t tag) ;
   void setTypeInfo(void *dstptr, void *metadata, uint64_t size, uint32_t tag) ;
-  void setVAInfo(void *va_list, uint64_t totalCount, uint8_t *metadata_ptr) ;
-  void copyVAInfo(void *va_list_dst, uint8_t *va_list_src) ;
+  void setVAInfo(void *va_list, uint64_t totalCount, TypeTagTy *metadata_ptr) ;
+  void copyVAInfo(void *va_list_dst, void *va_list_src) ;
   void trackctype(void *ptr, uint32_t tag) ;
   void trackctype_32(void *ptr, uint32_t tag) ;
   void trackStrncpyInst(void *dst, void *src, uint64_t size, uint32_t tag) ;
@@ -131,7 +133,7 @@
 /**
  * Record the global type and address in the shadow memory.
  */
-void trackGlobal(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) {
+void trackGlobal(void *ptr, TypeTagTy typeNumber, uint64_t size, uint32_t tag) {
   uintptr_t p = maskAddress(ptr);
   shadow_begin[p] = typeNumber;
   memset(&shadow_begin[p + 1], 0, size - 1);
@@ -157,7 +159,7 @@
 /**
  * Record the stored type and address in the shadow memory.
  */
-void trackStoreInst(void *ptr, uint8_t typeNumber, uint64_t size, uint32_t tag) {
+void trackStoreInst(void *ptr, TypeTagTy typeNumber, uint64_t size, uint32_t tag) {
   uintptr_t p = maskAddress(ptr);
   shadow_begin[p] = typeNumber;
   memset(&shadow_begin[p + 1], 0, size - 1);
@@ -177,7 +179,7 @@
 /** 
  * Check that the two types match
  */
-void compareTypes(uint8_t typeNumberSrc, uint8_t typeNumberDest, uint32_t tag) {
+void compareTypes(TypeTagTy typeNumberSrc, TypeTagTy typeNumberDest, uint32_t tag) {
   if(typeNumberSrc != typeNumberDest) {
     printf("Type mismatch(%u): expecting %s, found %s! \n", tag, typeNames[typeNumberDest], typeNames[typeNumberSrc]);
   }
@@ -197,7 +199,7 @@
  * Check that no. of arguments is less than passed
  * Check that the type being accessed is correct
  */
-void checkVAArgType(void *va_list, uint8_t TypeAccessed, uint32_t tag) {
+void checkVAArgType(void *va_list, TypeTagTy TypeAccessed, uint32_t tag) {
   va_info v = VA_InfoMap[va_list];
   compareNumber(v.numElements, v.counter, tag);
   compareTypes(TypeAccessed, v.metadata[v.counter], tag);
@@ -209,7 +211,7 @@
  * For loads, return the metadata(for size bytes) stored at the ptr
  * Store it in dest
  */
-void getTypeTag(void *ptr, uint64_t size, uint8_t *dest) {
+void getTypeTag(void *ptr, uint64_t size, TypeTagTy *dest) {
   uintptr_t p = maskAddress(ptr);
   assert(p + size < SIZE);
 
@@ -221,7 +223,7 @@
  * ptr and tag are for debugging
  */
 void __attribute__((always_inline))
-checkType(uint8_t typeNumber, uint64_t size, uint8_t *metadata, void *ptr, uint32_t tag) {
+checkType(TypeTagTy typeNumber, uint64_t size, TypeTagTy *metadata, void *ptr, uint32_t tag) {
   /* Check if this an initialized but untyped memory.*/
   if (typeNumber != metadata[0]) {
     if (metadata[0] != 0xFF) {
@@ -295,7 +297,7 @@
 /**
  * Initialize the metadata for a given VAList
  */
-void setVAInfo(void *va_list, uint64_t totalCount, uint8_t *metadata_ptr, uint32_t tag) {
+void setVAInfo(void *va_list, uint64_t totalCount, TypeTagTy *metadata_ptr, uint32_t tag) {
   struct va_info v = {totalCount, 0, metadata_ptr};
   VA_InfoMap[va_list] = v;
 }
@@ -303,7 +305,7 @@
 /**
  * Copy va list metadata from one list to the other.
  */
-void copyVAInfo(void *va_list_dst, uint8_t *va_list_src, uint32_t tag) {
+void copyVAInfo(void *va_list_dst, void *va_list_src, uint32_t tag) {
   VA_InfoMap[va_list_dst] = VA_InfoMap[va_list_src];
 }
 



From aggarwa4 at illinois.edu  Wed Jun 22 16:31:41 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Wed, 22 Jun 2011 21:31:41 -0000
Subject: [llvm-commits] [poolalloc] r133651 - in /poolalloc/trunk:
 lib/AssistDS/TypeChecks.cpp test/TEST.types.Makefile
Message-ID: <20110622213141.8DC502A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Jun 22 16:31:41 2011
New Revision: 133651

URL: http://llvm.org/viewvc/llvm-project?rev=133651&view=rev
Log:
Switch flag.
Disable pointer type checks by default.

Reflect change in makefile

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
    poolalloc/trunk/test/TEST.types.Makefile

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133651&r1=133650&r2=133651&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Wed Jun 22 16:31:41 2011
@@ -40,8 +40,8 @@
 STATISTIC(numTypes, "Number of Types used in the module");
 
 namespace {
-  static cl::opt<bool> DisablePointerTypeChecks("disable-ptr-type-checks",
-         cl::desc("DONT Distinguish pointer types"),
+  static cl::opt<bool> EnablePointerTypeChecks("enable-ptr-type-checks",
+         cl::desc("Distinguish pointer types in loads"),
          cl::Hidden,
          cl::init(false));
   static cl::opt<bool> DisablePtrCmpChecks("no-ptr-cmp-checks",
@@ -88,7 +88,7 @@
 static Constant *checkVAArg;
 
 unsigned int TypeChecks::getTypeMarker(const Type * Ty) {
-  if(DisablePointerTypeChecks) {
+  if(!EnablePointerTypeChecks) {
     if(Ty->isPointerTy()) {
       Ty = VoidPtrTy;
     }

Modified: poolalloc/trunk/test/TEST.types.Makefile
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/test/TEST.types.Makefile?rev=133651&r1=133650&r2=133651&view=diff
==============================================================================
--- poolalloc/trunk/test/TEST.types.Makefile (original)
+++ poolalloc/trunk/test/TEST.types.Makefile Wed Jun 22 16:31:41 2011
@@ -13,8 +13,6 @@
 # Pathname to poolalloc object tree
 PADIR   := $(LLVM_OBJ_ROOT)/projects/poolalloc
 
-LLC := /localhome/aggarwa4/llvm29/llvm-obj/Debug+Asserts/bin/llc
-
 # Pathame to the DSA pass dynamic library
 DSA_SO   := $(PADIR)/$(CONFIGURATION)/lib/libLLVMDataStructure$(SHLIBEXT)
 ASSIST_SO := $(PADIR)/$(CONFIGURATION)/lib/libAssistDS$(SHLIBEXT)
@@ -33,6 +31,8 @@
 ANALYZE_OPTS +=  -instcount -disable-verify 
 MEM := -track-memory -time-passes -disable-output
 
+LDFLAGS += -lstdc++
+
 #SAFE_OPTS := -internalize -scalarrepl -deadargelim -globaldce -basiccg -inline 
 SAFE_OPTS := -internalize -mem2reg -constprop -ipsccp -dce -deadargelim -globaldce -basiccg -inline
 SAFE_OPTS1 := -internalize  -deadargelim -globaldce -basiccg -inline
@@ -66,7 +66,7 @@
 
 $(PROGRAMS_TO_TEST:%=Output/%.tcd.bc): \
 Output/%.tcd.bc: Output/%.opt.bc $(LOPT) $(ASSIST_SO)
-	-$(RUNOPT) -load $(ASSIST_SO)  -typechecks -disable-ptr-type-checks -dce -ipsccp -dce -stats -info-output-file=$(CURDIR)/$@.info $< -f -o $@.temp
+	-$(RUNOPT) -load $(ASSIST_SO)  -typechecks -enable-ptr-type-checks -dce -ipsccp -dce -stats -info-output-file=$(CURDIR)/$@.info $< -f -o $@.temp
 	-$(LLVMLD) -disable-opt -o $@.ld $@.temp $(TYPE_RT_BC)
 	-$(LOPT) $(SAFE_OPTS) $@.ld.bc -o $@ -f
 	#-$(RUNOPT) -load $(ASSIST_SO) $(SAFE_OPTS) -typechecks-runtime-opt $@.ld.bc -o $@ -f
@@ -87,7 +87,7 @@
 
 $(PROGRAMS_TO_TEST:%=Output/%.tcoo1.bc): \
 Output/%.tcoo1.bc: Output/%.opt.bc $(LOPT) $(ASSIST_SO)
-	-$(RUNOPT) -load $(ASSIST_SO) -typechecks  -enable-type-inference-opts -dsa-stdlib-no-fold -typechecks-opt -typechecks-cmp-opt -dce -ipsccp -dce -stats -info-output-file=$(CURDIR)/$@.info $< -f -o $@.temp 
+	-$(RUNOPT) -load $(ASSIST_SO) -typechecks  -no-ptr-cmp-checks -enable-type-inference-opts -dsa-stdlib-no-fold -typechecks-opt -dce -ipsccp -dce -stats -info-output-file=$(CURDIR)/$@.info $< -f -o $@.temp 
 	-$(LLVMLD) -disable-opt -o $@.ld $@.temp $(TYPE_RT_BC)
 	-$(LOPT) $(SAFE_OPTS) $@.ld.bc -o $@ -f
 	#-$(RUNOPT) -load $(ASSIST_SO) $(SAFE_OPTS) -typechecks-runtime-opt $@.ld.bc -o $@ -f
@@ -288,7 +288,7 @@
 
 
 $(PROGRAMS_TO_TEST:%=Output/%.$(TEST).report.txt): \
-Output/%.$(TEST).report.txt: Output/%.opt.bc Output/%.LOC.txt $(LOPT) Output/%.out-nat Output/%.diff-llvm1 Output/%.diff-opt Output/%.diff-tc Output/%.diff-tco Output/%.diff-tcoo Output/%.diff-tcd Output/%.diff-count Output/%.diff-count1
+Output/%.$(TEST).report.txt: Output/%.opt.bc Output/%.LOC.txt $(LOPT) Output/%.out-nat Output/%.diff-llvm1 Output/%.diff-opt Output/%.diff-tc Output/%.diff-tco Output/%.diff-tcoo Output/%.diff-tcd Output/%.diff-count Output/%.diff-count1 Output/%.diff-tcoo1
 	@# Gather data
 	-($(RUNOPT)  -dsa-$(PASS) -enable-type-inference-opts -dsa-stdlib-no-fold $(ANALYZE_OPTS) $<)> $@.time.1 2>&1
 	-($(RUNOPT)  -dsa-$(PASS)  $(ANALYZE_OPTS) $<)> $@.time.2 2>&1



From jstaszak at apple.com  Wed Jun 22 16:39:56 2011
From: jstaszak at apple.com (Jakub Staszak)
Date: Wed, 22 Jun 2011 14:39:56 -0700
Subject: [llvm-commits] BlockFrequency for BasicBlocks
In-Reply-To: <F378E692-08B3-4762-A96E-D74CAE11B44D@apple.com>
References: <1E9CE6F5-A2AC-4A81-A001-D19DAB65255B@apple.com>
	<AB959C12-7AF3-4155-AC19-CA8F6116F710@apple.com>
	<E8A0D181-3AF7-4B5B-AA36-B210B721BAB4@apple.com>
	<F4C43975-C8E4-421F-84C0-39D23AACD036@apple.com>
	<98818310-FEB0-4E4D-8B38-E14698BFD9BE@apple.com>
	<F378E692-08B3-4762-A96E-D74CAE11B44D@apple.com>
Message-ID: <51D0DA66-26B3-44D5-8384-A31CC30E14EB@apple.com>


On Jun 21, 2011, at 8:21 PM, Andrew Trick wrote:

> 
> Yes, by "1" I meant literal 1, not scaled 1. I think this could happen inside getEdgeFreq() when (N * getBlockFreq(Src)) < D. You should probably check for that case and return the smallest nonzero frequency.
> 
> You actually shouldn't have a problem in divBlockFreq, but somewhere you should assert that the input BranchProbability is well-formed (N < D).

The bug was in the complete different place. Instead of using backedge probability info (probability of getting to DST block through SRC block) i used edge probability. It caused some problem in very rare cases (only during benchmarking).


> -Andy
> 
> 
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From aggarwa4 at illinois.edu  Wed Jun 22 16:42:19 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Wed, 22 Jun 2011 21:42:19 -0000
Subject: [llvm-commits] [poolalloc] r133652 -
 /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
Message-ID: <20110622214219.D89872A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Jun 22 16:42:19 2011
New Revision: 133652

URL: http://llvm.org/viewvc/llvm-project?rev=133652&view=rev
Log:
Fix some prototypes.

Modified:
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=133652&r1=133651&r2=133652&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Wed Jun 22 16:42:19 2011
@@ -69,8 +69,8 @@
   void trackUnInitInst(void *ptr, uint64_t size, uint32_t tag) ;
   void copyTypeInfo(void *dstptr, void *srcptr, uint64_t size, uint32_t tag) ;
   void setTypeInfo(void *dstptr, void *metadata, uint64_t size, uint32_t tag) ;
-  void setVAInfo(void *va_list, uint64_t totalCount, TypeTagTy *metadata_ptr) ;
-  void copyVAInfo(void *va_list_dst, void *va_list_src) ;
+  void setVAInfo(void *va_list, uint64_t totalCount, TypeTagTy *metadata_ptr, uint32_t tag) ;
+  void copyVAInfo(void *va_list_dst, void *va_list_src, uint32_t tag) ;
   void trackctype(void *ptr, uint32_t tag) ;
   void trackctype_32(void *ptr, uint32_t tag) ;
   void trackStrncpyInst(void *dst, void *src, uint64_t size, uint32_t tag) ;



From isanbard at gmail.com  Wed Jun 22 17:22:25 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 22 Jun 2011 22:22:25 -0000
Subject: [llvm-commits] [llvm] r133658 - in /llvm/trunk:
 include/llvm/Target/TargetLoweringObjectFile.h
 lib/CodeGen/TargetLoweringObjectFileImpl.cpp
 lib/Target/TargetLoweringObjectFile.cpp
Message-ID: <20110622222225.128862A6C12C@llvm.org>

Author: void
Date: Wed Jun 22 17:22:24 2011
New Revision: 133658

URL: http://llvm.org/viewvc/llvm-project?rev=133658&view=rev
Log:
Add a __LD,__compact_unwind section.

If the linker supports it, this will hold the CIE and FDE information in a
compact format. The implementation of the compact unwinding emission is coming
soon.

Modified:
    llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h
    llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
    llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp

Modified: llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h?rev=133658&r1=133657&r2=133658&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h Wed Jun 22 17:22:24 2011
@@ -68,6 +68,11 @@
   /// LSDASection - If exception handling is supported by the target, this is
   /// the section the Language Specific Data Area information is emitted to.
   const MCSection *LSDASection;
+
+  /// CompactUnwindSection - If exception handling is supported by the target
+  /// and the target can support a compact representation of the CIE and FDE,
+  /// this is the section to emit them into.
+  const MCSection *CompactUnwindSection;
   
   // Dwarf sections for debug info.  If a target supports debug info, these must
   // be set.
@@ -132,6 +137,7 @@
   const MCSection *getStaticCtorSection() const { return StaticCtorSection; }
   const MCSection *getStaticDtorSection() const { return StaticDtorSection; }
   const MCSection *getLSDASection() const { return LSDASection; }
+  const MCSection *getCompactUnwindSection() const{return CompactUnwindSection;}
   virtual const MCSection *getEHFrameSection() const = 0;
   virtual void emitPersonalityValue(MCStreamer &Streamer,
                                     const TargetMachine &TM,

Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=133658&r1=133657&r2=133658&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Wed Jun 22 17:22:24 2011
@@ -605,6 +605,12 @@
   // Exception Handling.
   LSDASection = getContext().getMachOSection("__TEXT", "__gcc_except_tab", 0,
                                              SectionKind::getReadOnlyWithRel());
+
+  CompactUnwindSection =
+    getContext().getMachOSection("__LD", "__compact_unwind",
+                                 MCSectionMachO::S_ATTR_DEBUG,
+                                 SectionKind::getReadOnly());
+
   // Debug Information.
   DwarfAbbrevSection =
     getContext().getMachOSection("__DWARF", "__debug_abbrev",

Modified: llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp?rev=133658&r1=133657&r2=133658&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp (original)
+++ llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Wed Jun 22 17:22:24 2011
@@ -43,6 +43,7 @@
   StaticCtorSection = 0;
   StaticDtorSection = 0;
   LSDASection = 0;
+  CompactUnwindSection = 0;
 
   CommDirectiveSupportsAlignment = true;
   DwarfAbbrevSection = 0;



From rafael.espindola at gmail.com  Wed Jun 22 17:31:57 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Wed, 22 Jun 2011 22:31:57 -0000
Subject: [llvm-commits] [llvm] r133659 - in /llvm/trunk:
 lib/CodeGen/TailDuplication.cpp test/CodeGen/X86/tail-dup-addr.ll
Message-ID: <20110622223157.B82D62A6C12C@llvm.org>

Author: rafael
Date: Wed Jun 22 17:31:57 2011
New Revision: 133659

URL: http://llvm.org/viewvc/llvm-project?rev=133659&view=rev
Log:
Reenable tail duplication of bb with just an unconditional jump, but
don't remove blocks that have their address taken.

Added:
    llvm/trunk/test/CodeGen/X86/tail-dup-addr.ll
Modified:
    llvm/trunk/lib/CodeGen/TailDuplication.cpp

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133659&r1=133658&r2=133659&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Wed Jun 22 17:31:57 2011
@@ -207,7 +207,7 @@
       // TailBB's immediate successors are now successors of those predecessors
       // which duplicated TailBB. Add the predecessors as sources to the PHI
       // instructions.
-      bool isDead = MBB->pred_empty();
+      bool isDead = MBB->pred_empty() && !MBB->hasAddressTaken();
       if (PreRegAlloc)
         UpdateSuccessorsPHIs(MBB, isDead, TDBBs, Succs);
 
@@ -568,9 +568,9 @@
 TailDuplicatePass::isSimpleBB(MachineBasicBlock *TailBB) {
   if (TailBB->succ_size() != 1)
     return false;
-  MachineBasicBlock::iterator I = TailBB->getFirstNonPHI();
+  MachineBasicBlock::iterator I = TailBB->begin();
   MachineBasicBlock::iterator E = TailBB->end();
-  while (I->isDebugValue() && I != E)
+  while (I != E && I->isDebugValue())
     ++I;
   if (I == E)
     return true;
@@ -712,7 +712,7 @@
   DenseSet<unsigned> UsedByPhi;
   getRegsUsedByPHIs(*TailBB, &UsedByPhi);
 
-  if (0 && isSimpleBB(TailBB))
+  if (isSimpleBB(TailBB))
     return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
 
   // Iterate through all the unique predecessors and tail-duplicate this

Added: llvm/trunk/test/CodeGen/X86/tail-dup-addr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tail-dup-addr.ll?rev=133659&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tail-dup-addr.ll (added)
+++ llvm/trunk/test/CodeGen/X86/tail-dup-addr.ll Wed Jun 22 17:31:57 2011
@@ -0,0 +1,28 @@
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
+
+; Test that we don't drop a block that has its address taken.
+
+; CHECK: Ltmp1:                                  ## Block address taken
+; CHECK: Ltmp2:                                  ## Block address taken
+
+ at a = common global i32 0, align 4
+ at p = common global i8* null, align 8
+
+define void @foo() noreturn nounwind uwtable ssp {
+entry:
+  %tmp = load i32* @a, align 4
+  %foo = icmp eq i32 0, %tmp
+  br i1 %foo, label %sw.bb, label %sw.default
+
+sw.bb:                                            ; preds = %entry
+  store i8* blockaddress(@foo, %sw.bb1), i8** @p, align 8
+  br label %sw.bb1
+
+sw.bb1:                                           ; preds = %sw.default, %sw.bb, %entry
+  store i8* blockaddress(@foo, %sw.default), i8** @p, align 8
+  br label %sw.default
+
+sw.default:                                       ; preds = %sw.bb1, %entry
+  store i8* blockaddress(@foo, %sw.bb1), i8** @p, align 8
+  br label %sw.bb1
+}



From mttjwl at gmail.com  Wed Jun 22 17:57:27 2011
From: mttjwl at gmail.com (Matthew Wala)
Date: Wed, 22 Jun 2011 22:57:27 -0000
Subject: [llvm-commits] [poolalloc] r133661 -
	/poolalloc/trunk/lib/DSA/StdLibPass.cpp
Message-ID: <20110622225727.573FB2A6C12C@llvm.org>

Author: wala1
Date: Wed Jun 22 17:57:27 2011
New Revision: 133661

URL: http://llvm.org/viewvc/llvm-project?rev=133661&view=rev
Log:
Allow DSA to recognize pool_fprintf(), pool_sprintf(), pool_snprintf().

Modified:
    poolalloc/trunk/lib/DSA/StdLibPass.cpp

Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=133661&r1=133660&r2=133661&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original)
+++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Wed Jun 22 17:57:27 2011
@@ -302,6 +302,9 @@
   {"sc.fsparameter",  {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"sc.fscallinfo",   {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"pool_printf",     {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_fprintf",    {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_sprintf",    {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_snprintf",   {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   
   // Type Checks
   {"trackGlobal",          {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},



From xi.wang at gmail.com  Wed Jun 22 16:09:00 2011
From: xi.wang at gmail.com (Xi Wang)
Date: Wed, 22 Jun 2011 17:09:00 -0400
Subject: [llvm-commits] [PATCH] ConstantRange::sub
In-Reply-To: <BANLkTik5fX8V72x_in=7qXxqcOjBbVwdXWO3SrzLQdK9K_zwiQ@mail.gmail.com>
References: <01F9FA28-E4FB-4D8A-9A67-C445041842B9@gmail.com>
	<BANLkTi=+_0p=U2dWHwnjz-M2N3MtX5Z-DaFM7fQt+WD2J4e-RA@mail.gmail.com>
	<4B12B5B1-CFC3-40CA-9F02-D3D7D5378F5B@gmail.com>
	<BANLkTik5fX8V72x_in=7qXxqcOjBbVwdXWO3SrzLQdK9K_zwiQ@mail.gmail.com>
Message-ID: <C2134A6C-D40F-4FB8-8E56-83FECE214028@gmail.com>

Here goes the patch along with a test for ConstantRange::sub.  Thanks.

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On Jun 22, 2011, at 3:57 PM, Nick Lewycky wrote:

> On 22 June 2011 12:51, Xi Wang <xi.wang at gmail.com> wrote:
> Sure.  I will submit a patch.
> 
> BTW, what's the difference between the bounds I was expecting
> 
> APInt NewLower = getLower() - Other.getUpper() + 1;
> APInt NewUpper = getUpper() - Other.getLower();
> 
> and the two you mentioned
> 
> NewLower = Lower - (Upper-1)
> NewUpper = (Upper-1) - Lower + 1
> 
> They look equivalent to me.  Did I miss anything?  Thanks.
> 
> ... they are. Sorry, I was just surprised to see the +1 on the NewLower (it always goes on the NewUpper instead, right), but I didn't actually simplify the expressions.
> 
> It sounds to me like you've got this one handled. :-)
> 
> Nick
>  
> 
> - xi
> 
> On Jun 22, 2011, at 2:39 PM, Nick Lewycky wrote:
> 
> > Thanks, I think you've found a serious bug!
> >
> > Would you be willing to fix it? Please add a test to unittests/Support/ConstantRangeTest.cpp and then mail llvm-commits with the patch to fix it and add the test.
> >
> > On 20 June 2011 23:09, Xi Wang <xi.wang at gmail.com> wrote:
> > Hi,
> >
> > I have a question about ConstantRange::sub(const ConstantRange &Other) at lib/Support/ConstantRange.cpp:524.  The code computes the new bounds as follows.
> >
> >  APInt NewLower = getLower() - Other.getLower();
> >  APInt NewUpper = getUpper() - Other.getUpper() + 1;
> >
> > Could someone explain this to me?  I was expecting something like
> >
> >  APInt NewLower = getLower() - Other.getUpper() + 1;
> >  APInt NewUpper = getUpper() - Other.getLower();
> >
> > These aren't quite right, I think it should be:
> >
> > NewLower = Lower - (Upper-1)
> > NewUpper = (Upper-1) - Lower + 1
> >
> > Constant ranges are stored half-open, [lower, upper) which means that the upper value is one past the end of the range. I often think of the formula as newmax = max - min --> newupper - 1 = ((getUpper() - 1) - Other.getLower(). min = lower, while max = upper - 1.
> >
> > Nick
> 
> 


From isanbard at gmail.com  Wed Jun 22 18:16:51 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 22 Jun 2011 23:16:51 -0000
Subject: [llvm-commits] [llvm] r133662 - in /llvm/trunk:
 include/llvm/Target/TargetLoweringObjectFile.h
 lib/CodeGen/TargetLoweringObjectFileImpl.cpp
 lib/Target/TargetLoweringObjectFile.cpp
Message-ID: <20110622231651.3840E2A6C12C@llvm.org>

Author: void
Date: Wed Jun 22 18:16:51 2011
New Revision: 133662

URL: http://llvm.org/viewvc/llvm-project?rev=133662&view=rev
Log:
Add a flag that indicates whether a target supports compact unwind info or not.

Modified:
    llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h
    llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
    llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp

Modified: llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h?rev=133662&r1=133661&r2=133662&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h Wed Jun 22 18:16:51 2011
@@ -107,8 +107,12 @@
   /// private linkage, aka an L or .L label) or false if it should be a normal
   /// non-.globl label.  This defaults to true.
   bool IsFunctionEHFrameSymbolPrivate;
+
+  /// SupportsCompactUnwindInfo - This flag is set to true if the CIE and FDE
+  /// information should be emitted in a compact form.
+  bool SupportsCompactUnwindInfo;
+
 public:
-  
   MCContext &getContext() const { return *Ctx; }
   
   virtual ~TargetLoweringObjectFile();
@@ -126,10 +130,12 @@
   bool getSupportsWeakOmittedEHFrame() const {
     return SupportsWeakOmittedEHFrame;
   }
-  
   bool getCommDirectiveSupportsAlignment() const {
     return CommDirectiveSupportsAlignment;
   }
+  bool getSupportsCompactUnwindInfo() const {
+    return SupportsCompactUnwindInfo;
+  }
 
   const MCSection *getTextSection() const { return TextSection; }
   const MCSection *getDataSection() const { return DataSection; }

Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=133662&r1=133661&r2=133662&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Wed Jun 22 18:16:51 2011
@@ -487,8 +487,12 @@
 
   // .comm doesn't support alignment before Leopard.
   Triple T(((LLVMTargetMachine&)TM).getTargetTriple());
-  if (T.isMacOSX() && T.isMacOSXVersionLT(10, 5))
-    CommDirectiveSupportsAlignment = false;
+  if (T.isMacOSX()) {
+    if (T.isMacOSXVersionLT(10, 5))
+      CommDirectiveSupportsAlignment = false;
+    if (!T.isMacOSXVersionLT(10, 6))
+      SupportsCompactUnwindInfo = true;
+  }
 
   TargetLoweringObjectFile::Initialize(Ctx, TM);
 

Modified: llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp?rev=133662&r1=133661&r2=133662&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp (original)
+++ llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Wed Jun 22 18:16:51 2011
@@ -61,6 +61,7 @@
   
   IsFunctionEHFrameSymbolPrivate = true;
   SupportsWeakOmittedEHFrame = true;
+  SupportsCompactUnwindInfo = false;
 }
 
 TargetLoweringObjectFile::~TargetLoweringObjectFile() {



From atrick at apple.com  Wed Jun 22 18:23:19 2011
From: atrick at apple.com (Andrew Trick)
Date: Wed, 22 Jun 2011 23:23:19 -0000
Subject: [llvm-commits] [llvm] r133664 - in /llvm/trunk:
 cmake/modules/HandleLLVMOptions.cmake
 test/CodeGen/X86/2011-06-14-PreschedRegalias.ll test/Makefile test/lit.cfg
 test/lit.site.cfg.in utils/lit/lit/TestRunner.py
 utils/lit/lit/TestingConfig.py
Message-ID: <20110622232319.9B2BE2A6C12C@llvm.org>

Author: atrick
Date: Wed Jun 22 18:23:19 2011
New Revision: 133664

URL: http://llvm.org/viewvc/llvm-project?rev=133664&view=rev
Log:
lit support for REQUIRES: asserts.

Take #2. Don't piggyback on the existing config.build_mode. Instead,
define a new lit feature for each build feature we need (currently
just "asserts"). Teach both autoconf'd and cmake'd Makefiles to define
this feature within test/lit.site.cfg. This doesn't require any lit
harness changes and should be more robust across build systems.

Modified:
    llvm/trunk/cmake/modules/HandleLLVMOptions.cmake
    llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
    llvm/trunk/test/Makefile
    llvm/trunk/test/lit.cfg
    llvm/trunk/test/lit.site.cfg.in
    llvm/trunk/utils/lit/lit/TestRunner.py
    llvm/trunk/utils/lit/lit/TestingConfig.py

Modified: llvm/trunk/cmake/modules/HandleLLVMOptions.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/HandleLLVMOptions.cmake?rev=133664&r1=133663&r2=133664&view=diff
==============================================================================
--- llvm/trunk/cmake/modules/HandleLLVMOptions.cmake (original)
+++ llvm/trunk/cmake/modules/HandleLLVMOptions.cmake Wed Jun 22 18:23:19 2011
@@ -36,13 +36,8 @@
   # explicitly undefine it:
   if( uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" )
     add_definitions( -UNDEBUG )
-    set(LLVM_BUILD_MODE "Release")
-  else()
-    set(LLVM_BUILD_MODE "Debug")
   endif()
-  set(LLVM_BUILD_MODE "${LLVM_BUILD_MODE}+Asserts")
 else()
-  set(LLVM_BUILD_MODE "Release")
   if( NOT uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" )
     if( NOT MSVC_IDE AND NOT XCODE )
       add_definitions( -DNDEBUG )

Modified: llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll?rev=133664&r1=133663&r2=133664&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll (original)
+++ llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll Wed Jun 22 18:23:19 2011
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -march=x86-64 -stress-sched | FileCheck %s
-; REQUIRES: Asserts
+; REQUIRES: asserts
 ; Test interference between physreg aliases during preRAsched.
 ; mul wants an operand in AL, but call clobbers it.
 

Modified: llvm/trunk/test/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=133664&r1=133663&r2=133664&view=diff
==============================================================================
--- llvm/trunk/test/Makefile (original)
+++ llvm/trunk/test/Makefile Wed Jun 22 18:23:19 2011
@@ -171,15 +171,21 @@
 	@test ! -f site.exp || mv site.exp site.bak
 	@mv site.tmp site.exp
 
+ifeq ($(DISABLE_ASSERTIONS),1)
+ENABLE_ASSERTIONS=0
+else
+ENABLE_ASSERTIONS=1
+endif
+
 lit.site.cfg: site.exp
 	@echo "Making LLVM 'lit.site.cfg' file..."
 	@$(ECHOPATH) s=@LLVM_SOURCE_DIR@=$(LLVM_SRC_ROOT)=g > lit.tmp
 	@$(ECHOPATH) s=@LLVM_BINARY_DIR@=$(LLVM_OBJ_ROOT)=g >> lit.tmp
 	@$(ECHOPATH) s=@LLVM_TOOLS_DIR@=$(ToolDir)=g >> lit.tmp
-	@$(ECHOPATH) s=@LLVM_BUILD_MODE@=$(BuildMode)=g >> lit.tmp
 	@$(ECHOPATH) s=@LLVMGCCDIR@=$(LLVMGCCDIR)=g >> lit.tmp
 	@$(ECHOPATH) s=@PYTHON_EXECUTABLE@=python=g >> lit.tmp
 	@$(ECHOPATH) s=@ENABLE_SHARED@=$(ENABLE_SHARED)=g >> lit.tmp
+	@$(ECHOPATH) s=@LLVM_ENABLE_ASSERTIONS@=$(ENABLE_ASSERTIONS)=g >> lit.tmp
 	@sed -f lit.tmp $(PROJ_SRC_DIR)/lit.site.cfg.in > $@
 	@-rm -f lit.tmp
 

Modified: llvm/trunk/test/lit.cfg
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.cfg?rev=133664&r1=133663&r2=133664&view=diff
==============================================================================
--- llvm/trunk/test/lit.cfg (original)
+++ llvm/trunk/test/lit.cfg Wed Jun 22 18:23:19 2011
@@ -306,3 +306,6 @@
 
 if loadable_module:
     config.available_features.add('loadable_module')
+
+if config.enable_assertions:
+    config.available_features.add('asserts')

Modified: llvm/trunk/test/lit.site.cfg.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.site.cfg.in?rev=133664&r1=133663&r2=133664&view=diff
==============================================================================
--- llvm/trunk/test/lit.site.cfg.in (original)
+++ llvm/trunk/test/lit.site.cfg.in Wed Jun 22 18:23:19 2011
@@ -5,9 +5,9 @@
 config.llvm_tools_dir = "@LLVM_TOOLS_DIR@"
 config.llvmgcc_dir = "@LLVMGCCDIR@"
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"
-config.llvm_build_modes = "@LLVM_BUILD_MODE@".split('+')
 config.python_executable = "@PYTHON_EXECUTABLE@"
 config.enable_shared = @ENABLE_SHARED@
+config.enable_assertions = @LLVM_ENABLE_ASSERTIONS@
 
 # Support substitution of the tools_dir with user parameters. This is
 # used when we can't determine the tool dir at configuration time.

Modified: llvm/trunk/utils/lit/lit/TestRunner.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestRunner.py?rev=133664&r1=133663&r2=133664&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/TestRunner.py (original)
+++ llvm/trunk/utils/lit/lit/TestRunner.py Wed Jun 22 18:23:19 2011
@@ -473,11 +473,9 @@
     if script[-1][-1] == '\\':
         return (Test.UNRESOLVED, "Test has unterminated run lines (with '\\')")
 
-    # Check that we have the required features or build modes:
+    # Check that we have the required features:
     missing_required_features = [f for f in requires
-                                 if f not in test.config.available_features
-                                 and f not in test.config.llvm_build_modes]
-
+                                 if f not in test.config.available_features]
     if missing_required_features:
         msg = ', '.join(missing_required_features)
         return (Test.UNSUPPORTED,

Modified: llvm/trunk/utils/lit/lit/TestingConfig.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestingConfig.py?rev=133664&r1=133663&r2=133664&view=diff
==============================================================================
--- llvm/trunk/utils/lit/lit/TestingConfig.py (original)
+++ llvm/trunk/utils/lit/lit/TestingConfig.py Wed Jun 22 18:23:19 2011
@@ -74,7 +74,6 @@
 
     def clone(self, path):
         # FIXME: Chain implementations?
-        # See attribute chaining in finish()
         #
         # FIXME: Allow extra parameters?
         cfg = TestingConfig(self, self.name, self.suffixes, self.test_format,
@@ -102,9 +101,3 @@
             # files. Should we distinguish them?
             self.test_source_root = str(self.test_source_root)
         self.excludes = set(self.excludes)
-
-        # chain attributes by copying them
-        if self.parent:
-            for k,v in vars(self.parent).items():
-                if not hasattr(self, k):
-                    setattr(self, k, v)



From isanbard at gmail.com  Wed Jun 22 19:09:43 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 23 Jun 2011 00:09:43 -0000
Subject: [llvm-commits] [llvm] r133668 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20110623000943.9F9C12A6C12C@llvm.org>

Author: void
Date: Wed Jun 22 19:09:43 2011
New Revision: 133668

URL: http://llvm.org/viewvc/llvm-project?rev=133668&view=rev
Log:
80-column violations.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=133668&r1=133667&r2=133668&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Wed Jun 22 19:09:43 2011
@@ -490,7 +490,8 @@
   assert(OS.tell() - Start == macho::DysymtabLoadCommandSize);
 }
 
-void MachObjectWriter::WriteNlist(MachSymbolData &MSD, const MCAsmLayout &Layout) {
+void MachObjectWriter::WriteNlist(MachSymbolData &MSD,
+                                  const MCAsmLayout &Layout) {
   MCSymbolData &Data = *MSD.SymbolData;
   const MCSymbol &Symbol = Data.getSymbol();
   uint8_t Type = 0;
@@ -1058,7 +1059,8 @@
   Relocations[Fragment->getParent()].push_back(MRE);
 }
 
-bool MachObjectWriter::getARMFixupKindMachOInfo(unsigned Kind, unsigned &RelocType,
+bool MachObjectWriter::getARMFixupKindMachOInfo(unsigned Kind,
+                                                unsigned &RelocType,
                                                 unsigned &Log2Size) {
   RelocType = unsigned(macho::RIT_Vanilla);
   Log2Size = ~0U;
@@ -1379,10 +1381,11 @@
 /// \param StringTable [out] - The string table data.
 /// \param StringIndexMap [out] - Map from symbol names to offsets in the
 /// string table.
-void MachObjectWriter::ComputeSymbolTable(MCAssembler &Asm, SmallString<256> &StringTable,
-                                          std::vector<MachSymbolData> &LocalSymbolData,
-                                          std::vector<MachSymbolData> &ExternalSymbolData,
-                                          std::vector<MachSymbolData> &UndefinedSymbolData) {
+void MachObjectWriter::
+ComputeSymbolTable(MCAssembler &Asm, SmallString<256> &StringTable,
+                   std::vector<MachSymbolData> &LocalSymbolData,
+                   std::vector<MachSymbolData> &ExternalSymbolData,
+                   std::vector<MachSymbolData> &UndefinedSymbolData) {
   // Build section lookup table.
   DenseMap<const MCSection*, uint8_t> SectionIndexMap;
   unsigned Index = 1;
@@ -1505,7 +1508,8 @@
   }
 }
 
-void MachObjectWriter::ExecutePostLayoutBinding(MCAssembler &Asm, const MCAsmLayout &Layout) {
+void MachObjectWriter::ExecutePostLayoutBinding(MCAssembler &Asm,
+                                                const MCAsmLayout &Layout) {
   computeSectionAddresses(Asm, Layout);
 
   // Create symbol data for any indirect symbols.
@@ -1516,11 +1520,12 @@
                      UndefinedSymbolData);
 }
 
-bool MachObjectWriter::IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm,
-                                                              const MCSymbolData &DataA,
-                                                              const MCFragment &FB,
-                                                              bool InSet,
-                                                              bool IsPCRel) const {
+bool MachObjectWriter::
+IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm,
+                                       const MCSymbolData &DataA,
+                                       const MCFragment &FB,
+                                       bool InSet,
+                                       bool IsPCRel) const {
   if (InSet)
     return true;
 



From isanbard at gmail.com  Wed Jun 22 19:12:58 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 23 Jun 2011 00:12:58 -0000
Subject: [llvm-commits] [llvm] r133669 -
	/llvm/trunk/include/llvm/Target/TargetAsmInfo.h
Message-ID: <20110623001258.50ACE2A6C12C@llvm.org>

Author: void
Date: Wed Jun 22 19:12:58 2011
New Revision: 133669

URL: http://llvm.org/viewvc/llvm-project?rev=133669&view=rev
Log:
Allow the AsmInfo to query the TLOF to see if it supports compact unwind.

Modified:
    llvm/trunk/include/llvm/Target/TargetAsmInfo.h

Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=133669&r1=133668&r2=133669&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Wed Jun 22 19:12:58 2011
@@ -79,6 +79,10 @@
     return TLOF->isFunctionEHFrameSymbolPrivate();
   }
 
+  bool getSupportsCompactUnwindInfo() const {
+    return TLOF->getSupportsCompactUnwindInfo();
+  }
+
   const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const {
     return TRI->getCalleeSavedRegs(MF);
   }



From isanbard at gmail.com  Wed Jun 22 19:23:04 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 23 Jun 2011 00:23:04 -0000
Subject: [llvm-commits] [llvm] r133670 -
	/llvm/trunk/include/llvm/Target/TargetAsmInfo.h
Message-ID: <20110623002304.CBDD92A6C12C@llvm.org>

Author: void
Date: Wed Jun 22 19:23:04 2011
New Revision: 133670

URL: http://llvm.org/viewvc/llvm-project?rev=133670&view=rev
Log:
Allow the AsmInfo to query for the compact unwind section.

Modified:
    llvm/trunk/include/llvm/Target/TargetAsmInfo.h

Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=133670&r1=133669&r2=133670&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Wed Jun 22 19:23:04 2011
@@ -59,6 +59,10 @@
     return TLOF->getEHFrameSection();
   }
 
+  const MCSection *getCompactUnwindSection() const {
+    return TLOF->getCompactUnwindSection();
+  }
+
   const MCSection *getDwarfFrameSection() const {
     return TLOF->getDwarfFrameSection();
   }



From atrick at apple.com  Wed Jun 22 19:47:08 2011
From: atrick at apple.com (Andrew Trick)
Date: Wed, 22 Jun 2011 17:47:08 -0700
Subject: [llvm-commits] BlockFrequency for BasicBlocks
In-Reply-To: <51D0DA66-26B3-44D5-8384-A31CC30E14EB@apple.com>
References: <1E9CE6F5-A2AC-4A81-A001-D19DAB65255B@apple.com>
	<AB959C12-7AF3-4155-AC19-CA8F6116F710@apple.com>
	<E8A0D181-3AF7-4B5B-AA36-B210B721BAB4@apple.com>
	<F4C43975-C8E4-421F-84C0-39D23AACD036@apple.com>
	<98818310-FEB0-4E4D-8B38-E14698BFD9BE@apple.com>
	<F378E692-08B3-4762-A96E-D74CAE11B44D@apple.com>
	<51D0DA66-26B3-44D5-8384-A31CC30E14EB@apple.com>
Message-ID: <6926F677-27AA-4488-8AD8-E1ACE86A2E2A@apple.com>

Where do you check underflow of block frequency? It seems that 10 sequential branches with default weights would result in getEdgeFreq() returning zero.

I'm not sure what getBackSumForBlock() means. The previous code looks correct to me. Can you explain the problem that you're solving?

Thanks.

-Andy

On Jun 22, 2011, at 2:39 PM, Jakub Staszak wrote:

> 
> On Jun 21, 2011, at 8:21 PM, Andrew Trick wrote:
> 
>> 
>> Yes, by "1" I meant literal 1, not scaled 1. I think this could happen inside getEdgeFreq() when (N * getBlockFreq(Src)) < D. You should probably check for that case and return the smallest nonzero frequency.
>> 
>> You actually shouldn't have a problem in divBlockFreq, but somewhere you should assert that the input BranchProbability is well-formed (N < D).
> 
> The bug was in the complete different place. Instead of using backedge probability info (probability of getting to DST block through SRC block) i used edge probability. It caused some problem in very rare cases (only during benchmarking).
> 
> 
>> -Andy
>> 
>> 
> <bf4bb.5.patch>


From aggarwa4 at illinois.edu  Wed Jun 22 19:57:30 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 00:57:30 -0000
Subject: [llvm-commits] [poolalloc] r133675 -
	/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
Message-ID: <20110623005731.0B1E52A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Jun 22 19:57:30 2011
New Revision: 133675

URL: http://llvm.org/viewvc/llvm-project?rev=133675&view=rev
Log:
Use TypeTagTy

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=133675&r1=133674&r2=133675&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Wed Jun 22 19:57:30 2011
@@ -41,6 +41,8 @@
 static const Type *Int32Ty = 0;
 static const Type *Int64Ty = 0;
 static const PointerType *VoidPtrTy = 0;
+static const Type *TypeTagTy = 0;
+static const Type *TypeTagPtrTy = 0;
 static Constant *trackGlobal;
 static Constant *trackStringInput;
 static Constant *trackInitInst;
@@ -60,11 +62,13 @@
   Int32Ty = IntegerType::getInt32Ty(M.getContext());
   Int64Ty = IntegerType::getInt64Ty(M.getContext());
   VoidPtrTy = PointerType::getUnqual(Int8Ty);
+  TypeTagTy = Int8Ty;
+  TypeTagPtrTy = PointerType::getUnqual(TypeTagTy);
 
   trackGlobal = M.getOrInsertFunction("trackGlobal",
                                       VoidTy,
                                       VoidPtrTy,/*ptr*/
-                                      Int8Ty,/*type*/
+                                      TypeTagTy,/*type*/
                                       Int64Ty,/*size*/
                                       Int32Ty,/*tag*/
                                       NULL);
@@ -83,13 +87,13 @@
   trackStoreInst = M.getOrInsertFunction("trackStoreInst",
                                          VoidTy,
                                          VoidPtrTy,/*ptr*/
-                                         Int8Ty,/*type*/
+                                         TypeTagTy,/*type*/
                                          Int64Ty,/*size*/
                                          Int32Ty,/*tag*/
                                          NULL);
   checkTypeInst = M.getOrInsertFunction("checkType",
                                         VoidTy,
-                                        Int8Ty,/*type*/
+                                        TypeTagTy,/*type*/
                                         Int64Ty,/*size*/
                                         VoidPtrTy,
                                         VoidPtrTy,/*ptr*/
@@ -105,7 +109,7 @@
   setTypeInfo = M.getOrInsertFunction("setTypeInfo",
                                        VoidTy,
                                        VoidPtrTy,/*dest ptr*/
-                                       VoidPtrTy,/*metadata*/
+                                       TypeTagPtrTy,/*metadata*/
                                        Int64Ty,/*size*/
                                        Int32Ty,/*tag*/
                                        NULL);



From isanbard at gmail.com  Wed Jun 22 20:06:23 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 23 Jun 2011 01:06:23 -0000
Subject: [llvm-commits] [llvm] r133676 - /llvm/trunk/lib/MC/MCDwarf.cpp
Message-ID: <20110623010623.3DFB42A6C12C@llvm.org>

Author: void
Date: Wed Jun 22 20:06:23 2011
New Revision: 133676

URL: http://llvm.org/viewvc/llvm-project?rev=133676&view=rev
Log:
Some skeleton code to emit the compact unwind. If the information is unable to
be emitted in a compact way, we then default to emitting a CIE and FDE.

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=133676&r1=133675&r2=133676&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Wed Jun 22 20:06:23 2011
@@ -507,6 +507,12 @@
       SectionStart(sectionStart) {
     }
 
+    /// EmitCompactUnwind - Emit the unwind information in a compact way. If
+    /// we're successful, return 'true'. Otherwise, return 'false' and it will
+    /// emit the normal CIE and FDE.
+    bool EmitCompactUnwind(MCStreamer &streamer,
+                           const MCDwarfFrameInfo &frame);
+
     const MCSymbol &EmitCIE(MCStreamer &streamer,
                             const MCSymbol *personality,
                             unsigned personalityEncoding,
@@ -620,6 +626,55 @@
   }
 }
 
+/// EmitCompactUnwind - Emit the unwind information in a compact way. If we're
+/// successful, return 'true'. Otherwise, return 'false' and it will emit the
+/// normal CIE and FDE.
+bool FrameEmitterImpl::EmitCompactUnwind(MCStreamer &Streamer,
+                                         const MCDwarfFrameInfo &Frame) {
+#if 1
+  return false;
+#else
+  MCContext &Context = Streamer.getContext();
+  const TargetAsmInfo &TAI = Context.getTargetAsmInfo();
+  Streamer.SwitchSection(TAI.getCompactUnwindSection());
+
+  unsigned FDEEncoding = TAI.getFDEEncoding(UsingCFI);
+  unsigned Size = getSizeForEncoding(Streamer, FDEEncoding);
+
+  // range-start range-length  compact-unwind-enc personality-func   lsda
+  //  _foo       LfooEnd-_foo  0x00000023          0                 0
+  //  _bar       LbarEnd-_bar  0x00000025         __gxx_personality  except_tab1
+  //
+  //   .section __LD,__compact_unwind,regular,debug
+  //
+  //   # compact unwind for _foo
+  //   .quad _foo
+  //   .set L1,LfooEnd-_foo
+  //   .long L1
+  //   .long 0x01010001
+  //   .quad 0
+  //   .quad 0
+  //
+  //   # compact unwind for _bar
+  //   .quad _bar
+  //   .set L2,LbarEnd-_bar
+  //   .long L2
+  //   .long 0x01020011
+  //   .quad __gxx_personality
+  //   .quad except_tab1
+
+  // Range Start
+  EmitSymbol(Streamer, *Frame.Begin, FDEEncoding);
+
+  // Range Length
+  const MCExpr *Range = MakeStartMinusEndExpr(Streamer, *Frame.Begin,
+                                              *Frame.End, 0);
+  Streamer.EmitAbsValue(Range, Size);
+
+  return true;
+#endif
+}
+
 const MCSymbol &FrameEmitterImpl::EmitCIE(MCStreamer &streamer,
                                           const MCSymbol *personality,
                                           unsigned personalityEncoding,
@@ -846,7 +901,8 @@
   MCContext &context = streamer.getContext();
   const TargetAsmInfo &asmInfo = context.getTargetAsmInfo();
   const MCSection &section = isEH ?
-    *asmInfo.getEHFrameSection() : *asmInfo.getDwarfFrameSection();
+    *asmInfo.getEHFrameSection() :
+    *asmInfo.getDwarfFrameSection();
   streamer.SwitchSection(&section);
   MCSymbol *SectionStart = context.CreateTempSymbol();
   streamer.EmitLabel(SectionStart);
@@ -861,11 +917,17 @@
     CIEKey key(frame.Personality, frame.PersonalityEncoding,
                frame.LsdaEncoding);
     const MCSymbol *&cieStart = isEH ? CIEStarts[key] : DummyDebugKey;
+    if (isEH && asmInfo.getSupportsCompactUnwindInfo() &&
+        Emitter.EmitCompactUnwind(streamer, frame))
+      continue;
+
     if (!cieStart)
       cieStart = &Emitter.EmitCIE(streamer, frame.Personality,
                                   frame.PersonalityEncoding, frame.Lsda,
                                   frame.LsdaEncoding);
+
     fdeEnd = Emitter.EmitFDE(streamer, *cieStart, frame);
+
     if (i != n - 1)
       streamer.EmitLabel(fdeEnd);
   }



From jstaszak at apple.com  Wed Jun 22 20:16:13 2011
From: jstaszak at apple.com (Jakub Staszak)
Date: Wed, 22 Jun 2011 18:16:13 -0700
Subject: [llvm-commits] BlockFrequency for BasicBlocks
In-Reply-To: <6926F677-27AA-4488-8AD8-E1ACE86A2E2A@apple.com>
References: <1E9CE6F5-A2AC-4A81-A001-D19DAB65255B@apple.com>
	<AB959C12-7AF3-4155-AC19-CA8F6116F710@apple.com>
	<E8A0D181-3AF7-4B5B-AA36-B210B721BAB4@apple.com>
	<F4C43975-C8E4-421F-84C0-39D23AACD036@apple.com>
	<98818310-FEB0-4E4D-8B38-E14698BFD9BE@apple.com>
	<F378E692-08B3-4762-A96E-D74CAE11B44D@apple.com>
	<51D0DA66-26B3-44D5-8384-A31CC30E14EB@apple.com>
	<6926F677-27AA-4488-8AD8-E1ACE86A2E2A@apple.com>
Message-ID: <B393EF1C-C3DC-4A4C-8749-09762C429177@apple.com>

To the cyclic_probability we have to add backedge probability, it is probability of getting to the DST block through the SRC block. In the original algorithm we used floating point numbers, but here we use integers with START_FREQ = 1024, thus we have to "normalize" the value and look at it as a probability  where 1024 is equal to 1.0. 

Previously we used getEdgeFreq which is wrong, because sum of them for some BB from all its predecessors might be greater than START_FREQ.

BTW: I forgot to delete DSE.cpp part, which is use for the testing purpose.

-Kuba

On Jun 22, 2011, at 5:47 PM, Andrew Trick wrote:

> Where do you check underflow of block frequency? It seems that 10 sequential branches with default weights would result in getEdgeFreq() returning zero.
> 
> I'm not sure what getBackSumForBlock() means. The previous code looks correct to me. Can you explain the problem that you're solving?
> 
> Thanks.
> 
> -Andy
> 
> On Jun 22, 2011, at 2:39 PM, Jakub Staszak wrote:
> 
>> 
>> On Jun 21, 2011, at 8:21 PM, Andrew Trick wrote:
>> 
>>> 
>>> Yes, by "1" I meant literal 1, not scaled 1. I think this could happen inside getEdgeFreq() when (N * getBlockFreq(Src)) < D. You should probably check for that case and return the smallest nonzero frequency.
>>> 
>>> You actually shouldn't have a problem in divBlockFreq, but somewhere you should assert that the input BranchProbability is well-formed (N < D).
>> 
>> The bug was in the complete different place. Instead of using backedge probability info (probability of getting to DST block through SRC block) i used edge probability. It caused some problem in very rare cases (only during benchmarking).
>> 
>> 
>>> -Andy
>>> 
>>> 
>> <bf4bb.5.patch>
> 

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From rafael.espindola at gmail.com  Wed Jun 22 20:31:19 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Wed, 22 Jun 2011 21:31:19 -0400
Subject: [llvm-commits] [llvm] r133240 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
In-Reply-To: <BANLkTikGbW-G3soeku5b8U6mw31MOiE-=+LOqJ+jkbAjja0qAg@mail.gmail.com>
References: <20110617055451.24CFF2A6C12C@llvm.org>
	<BANLkTikGbW-G3soeku5b8U6mw31MOiE-=+LOqJ+jkbAjja0qAg@mail.gmail.com>
Message-ID: <4E029767.9060606@gmail.com>

> This commit appears to be causing a significant performance regression
> on a couple tests in the test-suite for x86-32;
> test-suite/SingleSource/Benchmarks/Shootout-C++/matrix.cpp is a good
> example (3.3s before, 4.1s after).  Would you mind taking a look to
> see if anything unexpected is happening?

It looks like a register allocation issue. On this benchmark, the hot
bb is not duplicated (or duplicated into), but gets a new phi node.
After register allocation, the start of the block goes from

	%ECX<def> = MOV32rm %EDI, 4, %EBX, 0, %noreg; mem:LD4[%scevgep9](tbaa=!"any pointer")
	%ECX<def> = MOV32rm %ECX<kill>, 4, %ESI, 0, %noreg; mem:LD4[%scevgep12](tbaa=!"int")
	%ECX<def> = IMUL32rm %ECX<kill>, %EDX, 4, %EBX, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%scevgep10](tbaa=!"int")

to

	%EDI<def> = MOV32rm <fi#2>, 1, %noreg, 0, %noreg; mem:LD4[FixedStack2]
	%EDI<def> = MOV32rm %EDI<kill>, 4, %EBX, 0, %noreg; mem:LD4[%scevgep9](tbaa=!"any pointer")
	%EDI<def> = MOV32rm %EDI<kill>, 4, %EAX, 0, %noreg; mem:LD4[%scevgep12](tbaa=!"int")
	%EDI<def> = IMUL32rm %EDI<kill>, %EDX, 4, %EBX, 0, %noreg, %EFLAGS<imp-def,dead>; mem:LD4[%scevgep10](tbaa=!"int")

Note that the value that before was in EDI at the start of the loop is now in fi#2.

I have placed the files (test.bc, no-tail-dup.log, tail-dup.log) in
http://people.mozilla.com/~respindola if you are interested. I will check if I
can make the early tail duplication a bit more conservative.
 
> -Eli

Cheers,
Rafael

From atrick at apple.com  Wed Jun 22 20:57:57 2011
From: atrick at apple.com (Andrew Trick)
Date: Wed, 22 Jun 2011 18:57:57 -0700
Subject: [llvm-commits] BlockFrequency for BasicBlocks
In-Reply-To: <B393EF1C-C3DC-4A4C-8749-09762C429177@apple.com>
References: <1E9CE6F5-A2AC-4A81-A001-D19DAB65255B@apple.com>
	<AB959C12-7AF3-4155-AC19-CA8F6116F710@apple.com>
	<E8A0D181-3AF7-4B5B-AA36-B210B721BAB4@apple.com>
	<F4C43975-C8E4-421F-84C0-39D23AACD036@apple.com>
	<98818310-FEB0-4E4D-8B38-E14698BFD9BE@apple.com>
	<F378E692-08B3-4762-A96E-D74CAE11B44D@apple.com>
	<51D0DA66-26B3-44D5-8384-A31CC30E14EB@apple.com>
	<6926F677-27AA-4488-8AD8-E1ACE86A2E2A@apple.com>
	<B393EF1C-C3DC-4A4C-8749-09762C429177@apple.com>
Message-ID: <C9D6C97D-5E02-43A7-A299-65C3D2797490@apple.com>

On Jun 22, 2011, at 6:16 PM, Jakub Staszak wrote:

> Previously we used getEdgeFreq which is wrong, because sum of them for some BB from all its predecessors might be greater than START_FREQ.

The algorithm assumes that will never happen when BB is the loop head currently being processed. If it does happen (irreducible inner loops?) then I don't know how to calculate cyclic probability. I would just pick a reasonably high value.

BTW: this problem could be solved by converted the irreducible graph to a reducible one, but you shouldn't worry about that for now.

-Andy

From evan.cheng at apple.com  Wed Jun 22 20:53:43 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 23 Jun 2011 01:53:43 -0000
Subject: [llvm-commits] [llvm] r133679 - in /llvm/trunk/lib/Target/X86:
 X86InstrInfo.cpp X86RegisterInfo.cpp X86RegisterInfo.h
Message-ID: <20110623015343.B7EEB2A6C12C@llvm.org>

Author: evancheng
Date: Wed Jun 22 20:53:43 2011
New Revision: 133679

URL: http://llvm.org/viewvc/llvm-project?rev=133679&view=rev
Log:
Get rid of one getStackAlignment(). RegisterInfo shouldn't need to know about stack alignment.

Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.h

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=133679&r1=133678&r2=133679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed Jun 22 20:53:43 2011
@@ -2082,7 +2082,8 @@
   const MachineFunction &MF = *MBB.getParent();
   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
          "Stack slot too small for store");
-  bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
+  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= 16) ||
+    RI.canRealignStack(MF);
   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, TM);
   DebugLoc DL = MBB.findDebugLoc(MI);
   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
@@ -2114,7 +2115,8 @@
                                         const TargetRegisterClass *RC,
                                         const TargetRegisterInfo *TRI) const {
   const MachineFunction &MF = *MBB.getParent();
-  bool isAligned = (RI.getStackAlignment() >= 16) || RI.canRealignStack(MF);
+  bool isAligned = (TM.getFrameLowering()->getStackAlignment() >= 16) ||
+    RI.canRealignStack(MF);
   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, TM);
   DebugLoc DL = MBB.findDebugLoc(MI);
   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=133679&r1=133678&r2=133679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Jun 22 20:53:43 2011
@@ -60,7 +60,6 @@
   const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
   Is64Bit = Subtarget->is64Bit();
   IsWin64 = Subtarget->isTargetWin64();
-  StackAlign = TM.getFrameLowering()->getStackAlignment();
 
   if (Is64Bit) {
     SlotSize = 8;
@@ -557,6 +556,7 @@
 bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   const Function *F = MF.getFunction();
+  unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
   bool requiresRealignment = ((MFI->getMaxAlignment() > StackAlign) ||
                                F->hasFnAttr(Attribute::StackAlignment));
 
@@ -632,6 +632,7 @@
     // We need to keep the stack aligned properly.  To do this, we round the
     // amount of space needed for the outgoing arguments up to the next
     // alignment boundary.
+    unsigned StackAlign = TM.getFrameLowering()->getStackAlignment();
     Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign;
 
     MachineInstr *New = 0;
@@ -927,10 +928,10 @@
     virtual bool runOnMachineFunction(MachineFunction &MF) {
       const X86TargetMachine *TM =
         static_cast<const X86TargetMachine *>(&MF.getTarget());
-      const X86RegisterInfo *X86RI = TM->getRegisterInfo();
+      const TargetFrameLowering *TFI = TM->getFrameLowering();
       MachineRegisterInfo &RI = MF.getRegInfo();
       X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
-      unsigned StackAlignment = X86RI->getStackAlignment();
+      unsigned StackAlignment = TFI->getStackAlignment();
 
       // Be over-conservative: scan over all vreg defs and find whether vector
       // registers are used. If yes, there is a possibility that vector register

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=133679&r1=133678&r2=133679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Wed Jun 22 20:53:43 2011
@@ -56,10 +56,6 @@
   ///
   unsigned SlotSize;
 
-  /// StackAlign - Default stack alignment.
-  ///
-  unsigned StackAlign;
-
   /// StackPtr - X86 physical register used as stack ptr.
   ///
   unsigned StackPtr;
@@ -75,8 +71,6 @@
   /// register identifier.
   static unsigned getX86RegNum(unsigned RegNo);
 
-  unsigned getStackAlignment() const { return StackAlign; }
-
   /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
   /// (created by TableGen) for target dependencies.
   int getDwarfRegNum(unsigned RegNum, bool isEH) const;



From jstaszak at apple.com  Wed Jun 22 21:42:30 2011
From: jstaszak at apple.com (Jakub Staszak)
Date: Wed, 22 Jun 2011 19:42:30 -0700
Subject: [llvm-commits] BlockFrequency for BasicBlocks
In-Reply-To: <C9D6C97D-5E02-43A7-A299-65C3D2797490@apple.com>
References: <1E9CE6F5-A2AC-4A81-A001-D19DAB65255B@apple.com>
	<AB959C12-7AF3-4155-AC19-CA8F6116F710@apple.com>
	<E8A0D181-3AF7-4B5B-AA36-B210B721BAB4@apple.com>
	<F4C43975-C8E4-421F-84C0-39D23AACD036@apple.com>
	<98818310-FEB0-4E4D-8B38-E14698BFD9BE@apple.com>
	<F378E692-08B3-4762-A96E-D74CAE11B44D@apple.com>
	<51D0DA66-26B3-44D5-8384-A31CC30E14EB@apple.com>
	<6926F677-27AA-4488-8AD8-E1ACE86A2E2A@apple.com>
	<B393EF1C-C3DC-4A4C-8749-09762C429177@apple.com>
	<C9D6C97D-5E02-43A7-A299-65C3D2797490@apple.com>
Message-ID: <E246EF61-489F-4BD5-A9B3-FCABD29CB694@apple.com>

On Jun 22, 2011, at 6:57 PM, Andrew Trick wrote:

> On Jun 22, 2011, at 6:16 PM, Jakub Staszak wrote:
> 
>> Previously we used getEdgeFreq which is wrong, because sum of them for some BB from all its predecessors might be greater than START_FREQ.
> 
> The algorithm assumes that will never happen when BB is the loop head currently being processed. If it does happen (irreducible inner loops?) then I don't know how to calculate cyclic probability. I would just pick a reasonably high value.

The previous version of the patch used to do this. We divided by pretty small number, but I think we didn't like it, did we? I don't know which version you prefer, I think I like the current one.

- Kuba


From aggarwa4 at illinois.edu  Wed Jun 22 22:24:32 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 03:24:32 -0000
Subject: [llvm-commits] [poolalloc] r133680 -
 /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
Message-ID: <20110623032432.3D1982A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Jun 22 22:24:32 2011
New Revision: 133680

URL: http://llvm.org/viewvc/llvm-project?rev=133680&view=rev
Log:
Add a few more functions, needed by newer version of sqlite.
Fix printing in VAArgCheck.

Modified:
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=133680&r1=133679&r2=133680&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Wed Jun 22 22:24:32 2011
@@ -6,6 +6,7 @@
 #include <string.h>
 #include <netdb.h>
 #include <poll.h>
+#include <pwd.h>
 #include <sys/types.h>
 #include <sys/socket.h>
 #include <sys/mman.h>
@@ -77,6 +78,7 @@
   void trackStrcpyInst(void *dst, void *src, uint32_t tag) ;
   void trackStrcatInst(void *dst, void *src, uint32_t tag) ;
   void trackgetcwd(void *ptr, uint32_t tag) ;
+  void trackgetpwuid(void *ptr, uint32_t tag) ;
   void trackgethostname(void *ptr, uint32_t tag) ;
   void trackgetaddrinfo(void *ptr, uint32_t tag) ;
   void trackaccept(void *ptr, uint32_t tag) ;
@@ -166,7 +168,6 @@
 #if DEBUG
   printf("Store(%d): %p, %p = %u | %lu bytes | \n", tag, ptr, (void *)p, typeNumber, size);
 #endif
-
 }
 
 /**
@@ -181,7 +182,7 @@
  */
 void compareTypes(TypeTagTy typeNumberSrc, TypeTagTy typeNumberDest, uint32_t tag) {
   if(typeNumberSrc != typeNumberDest) {
-    printf("Type mismatch(%u): expecting %s, found %s! \n", tag, typeNames[typeNumberDest], typeNames[typeNumberSrc]);
+    printf("Type mismatch(%u): expecting %s, found %s! \n", tag, typeNames[typeNumberSrc], typeNames[typeNumberDest]);
   }
 }
 
@@ -222,7 +223,7 @@
  * Compare the typeNumber with the type info(for given size) stored at the metadata ptr.
  * ptr and tag are for debugging
  */
-void __attribute__((always_inline))
+void 
 checkType(TypeTagTy typeNumber, uint64_t size, TypeTagTy *metadata, void *ptr, uint32_t tag) {
   /* Check if this an initialized but untyped memory.*/
   if (typeNumber != metadata[0]) {
@@ -362,6 +363,14 @@
   trackInitInst(ptr, strlen((const char *)ptr) + 1, tag);
 }
 
+void trackgetpwuid(void *ptr, uint32_t tag) {
+  struct passwd *p = (struct passwd *)ptr;
+  trackInitInst(p->pw_name, strlen(p->pw_name) + 1, tag);
+  trackInitInst(p->pw_dir, strlen(p->pw_dir) + 1, tag);
+  trackInitInst(p->pw_shell, strlen(p->pw_shell) + 1, tag);
+  trackInitInst(p, sizeof(struct passwd), tag);
+}
+
 void trackgethostname(void *ptr, uint32_t tag) {
   trackInitInst(ptr, strlen((const char *)ptr) + 1, tag);
 }



From aggarwa4 at illinois.edu  Wed Jun 22 22:25:37 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 03:25:37 -0000
Subject: [llvm-commits] [poolalloc] r133681 -
	/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
Message-ID: <20110623032537.510322A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Jun 22 22:25:37 2011
New Revision: 133681

URL: http://llvm.org/viewvc/llvm-project?rev=133681&view=rev
Log:
Add instrumentation for __errno_location.
Give getpwuid a separate function, which instruments
the pointers in its fields too.

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133681&r1=133680&r2=133681&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Wed Jun 22 22:25:37 2011
@@ -1401,10 +1401,19 @@
       Args.push_back(AllocSize);
       Args.push_back(getTagCounter());
       CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I);
-    } else if (F->getNameStr() == std::string("getpwuid") ||
-               F->getNameStr() == std::string("getgruid") ||
+    } else if (F->getNameStr() == std::string("getpwuid")) {
+      CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy);
+      BCI->insertAfter(I);
+      std::vector<Value *>Args;
+      Args.push_back(BCI);
+      Args.push_back(getTagCounter());
+      Constant *F = M.getOrInsertFunction("trackgetpwuid", VoidTy, VoidPtrTy, Int32Ty, NULL);
+      CallInst *CI = CallInst::Create(F, Args.begin(), Args.end());
+      CI->insertAfter(BCI);
+    } else if (F->getNameStr() == std::string("getgruid") ||
                F->getNameStr() == std::string("getgrnam") ||
-               F->getNameStr() == std::string("getpwnam")) {
+               F->getNameStr() == std::string("getpwnam") ||
+               F->getNameStr() == std::string("__errno_location")) {
       CastInst *BCI  = BitCastInst::CreatePointerCast(I, VoidPtrTy);
       assert (isa<PointerType>(I->getType()));
       const PointerType * PT = cast<PointerType>(I->getType());



From rafael.espindola at gmail.com  Wed Jun 22 22:41:29 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 23 Jun 2011 03:41:29 -0000
Subject: [llvm-commits] [llvm] r133682 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
Message-ID: <20110623034130.0384B2A6C12C@llvm.org>

Author: rafael
Date: Wed Jun 22 22:41:29 2011
New Revision: 133682

URL: http://llvm.org/viewvc/llvm-project?rev=133682&view=rev
Log:
Move more logic to shouldTailDuplicate and only duplicate regular bb before
register allocation if it has a indirectbr or if we can duplicate it to
every predecessor.

This fixes the SingleSource/Benchmarks/Shootout-C++/matrix.cpp regression but
keeps the previous improvements to sunspider.

Modified:
    llvm/trunk/lib/CodeGen/TailDuplication.cpp

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133682&r1=133681&r2=133682&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Wed Jun 22 22:41:29 2011
@@ -95,10 +95,10 @@
                               SmallSetVector<MachineBasicBlock*, 8> &Succs);
     bool TailDuplicateBlocks(MachineFunction &MF);
     bool shouldTailDuplicate(const MachineFunction &MF,
-                             MachineBasicBlock &TailBB);
+                             bool IsSimple, MachineBasicBlock &TailBB);
     bool isSimpleBB(MachineBasicBlock *TailBB);
-    bool canCompletelyDuplicateSimpleBB(MachineBasicBlock &BB);
-    bool duplicateSimpleBB(MachineBasicBlock *TailBB,
+    bool canCompletelyDuplicateBB(MachineBasicBlock &BB, bool IsSimple);
+    void duplicateSimpleBB(MachineBasicBlock *TailBB,
                            SmallVector<MachineBasicBlock*, 8> &TDBBs,
                            const DenseSet<unsigned> &RegsUsedByPhi,
                            SmallVector<MachineInstr*, 16> &Copies);
@@ -501,6 +501,7 @@
 /// shouldTailDuplicate - Determine if it is profitable to duplicate this block.
 bool
 TailDuplicatePass::shouldTailDuplicate(const MachineFunction &MF,
+                                       bool IsSimple,
                                        MachineBasicBlock &TailBB) {
   // Only duplicate blocks that end with unconditional branches.
   if (TailBB.canFallThrough())
@@ -526,10 +527,13 @@
   // to allow undoing the effects of tail merging and other optimizations
   // that rearrange the predecessors of the indirect branch.
 
+  bool hasIndirectBR = false;
   if (PreRegAlloc && !TailBB.empty()) {
     const TargetInstrDesc &TID = TailBB.back().getDesc();
-    if (TID.isIndirectBranch())
+    if (TID.isIndirectBranch()) {
       MaxDuplicateCount = 20;
+      hasIndirectBR = true;
+    }
   }
 
   // Check the instructions in the block to determine whether tail-duplication
@@ -560,7 +564,16 @@
       return false;
   }
 
-  return true;
+  if (hasIndirectBR)
+    return true;
+
+  if (IsSimple)
+    return canCompletelyDuplicateBB(TailBB, IsSimple);
+
+  if (!PreRegAlloc)
+    return true;
+
+  return canCompletelyDuplicateBB(TailBB, IsSimple);
 }
 
 /// isSimpleBB - True if this BB has only one unconditional jump.
@@ -568,6 +581,8 @@
 TailDuplicatePass::isSimpleBB(MachineBasicBlock *TailBB) {
   if (TailBB->succ_size() != 1)
     return false;
+  if (TailBB->pred_empty())
+    return false;
   MachineBasicBlock::iterator I = TailBB->begin();
   MachineBasicBlock::iterator E = TailBB->end();
   while (I != E && I->isDebugValue())
@@ -591,33 +606,40 @@
 }
 
 bool
-TailDuplicatePass::canCompletelyDuplicateSimpleBB(MachineBasicBlock &BB) {
+TailDuplicatePass::canCompletelyDuplicateBB(MachineBasicBlock &BB,
+                                            bool isSimple) {
   SmallPtrSet<MachineBasicBlock*, 8> Succs(BB.succ_begin(), BB.succ_end());
 
   for (MachineBasicBlock::pred_iterator PI = BB.pred_begin(),
        PE = BB.pred_end(); PI != PE; ++PI) {
     MachineBasicBlock *PredBB = *PI;
-    if (PredBB->getLandingPadSuccessor())
-      return false;
-    if (bothUsedInPHI(*PredBB, Succs))
-      return false;
+
+    if (isSimple) {
+      if (PredBB->getLandingPadSuccessor())
+        return false;
+      if (bothUsedInPHI(*PredBB, Succs))
+        return false;
+    } else {
+      if (PredBB->succ_size() > 1)
+        return false;
+    }
+
     MachineBasicBlock *PredTBB = NULL, *PredFBB = NULL;
     SmallVector<MachineOperand, 4> PredCond;
     if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
       return false;
+
+    if (!isSimple && !PredCond.empty())
+      return false;
   }
   return true;
 }
 
-bool
+void
 TailDuplicatePass::duplicateSimpleBB(MachineBasicBlock *TailBB,
                                      SmallVector<MachineBasicBlock*, 8> &TDBBs,
                                      const DenseSet<unsigned> &UsedByPhi,
                                      SmallVector<MachineInstr*, 16> &Copies) {
-  if (!canCompletelyDuplicateSimpleBB(*TailBB))
-    return false;
-
-  bool Changed = false;
   SmallVector<MachineBasicBlock*, 8> Preds(TailBB->pred_begin(),
                                            TailBB->pred_end());
   for (SmallSetVector<MachineBasicBlock *, 8>::iterator PI = Preds.begin(),
@@ -692,10 +714,7 @@
       PredBB->addSuccessor(NewTarget);
 
     TDBBs.push_back(PredBB);
-
-    Changed = true;
   }
-  return Changed;
 }
 
 /// TailDuplicate - If it is profitable, duplicate TailBB's contents in each
@@ -704,7 +723,9 @@
 TailDuplicatePass::TailDuplicate(MachineBasicBlock *TailBB, MachineFunction &MF,
                                  SmallVector<MachineBasicBlock*, 8> &TDBBs,
                                  SmallVector<MachineInstr*, 16> &Copies) {
-  if (!shouldTailDuplicate(MF, *TailBB))
+  bool IsSimple = isSimpleBB(TailBB);
+
+  if (!shouldTailDuplicate(MF, IsSimple, *TailBB))
     return false;
 
   DEBUG(dbgs() << "\n*** Tail-duplicating BB#" << TailBB->getNumber() << '\n');
@@ -712,8 +733,11 @@
   DenseSet<unsigned> UsedByPhi;
   getRegsUsedByPHIs(*TailBB, &UsedByPhi);
 
-  if (isSimpleBB(TailBB))
-    return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
+  if (IsSimple) {
+    duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
+    return true;
+  }
+
 
   // Iterate through all the unique predecessors and tail-duplicate this
   // block into them, if possible. Copying the list ahead of time also



From aggarwa4 at illinois.edu  Wed Jun 22 23:14:27 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 04:14:27 -0000
Subject: [llvm-commits] [poolalloc] r133683 - in /poolalloc/trunk:
 lib/AssistDS/TypeChecks.cpp runtime/DynamicTypeChecks/TypeRuntime.cpp
Message-ID: <20110623041427.AE7072A6C12C@llvm.org>

Author: aggarwa4
Date: Wed Jun 22 23:14:27 2011
New Revision: 133683

URL: http://llvm.org/viewvc/llvm-project?rev=133683&view=rev
Log:
Fix prototypes/arguments to be of the correct type

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133683&r1=133682&r2=133683&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Wed Jun 22 23:14:27 2011
@@ -1761,18 +1761,17 @@
 
   Value *Size = ConstantInt::get(Int32Ty, getSize(LI.getType()));
   AllocaInst *AI = new AllocaInst(TypeTagTy, Size, "", &*InsPt);
-  CastInst *BCI_MD = BitCastInst::CreatePointerCast(AI, VoidPtrTy, "", &*InsPt);
 
   std::vector<Value *>Args1;
   Args1.push_back(BCI);
   Args1.push_back(getSizeConstant(LI.getType()));
-  Args1.push_back(BCI_MD);
+  Args1.push_back(AI);
   CallInst *getTypeCall = CallInst::Create(getTypeTag, Args1.begin(), Args1.end(), "", &LI);
   if(TrackAllLoads) {
     std::vector<Value *> Args;
     Args.push_back(getTypeMarkerConstant(&LI));
     Args.push_back(getSizeConstant(LI.getType()));
-    Args.push_back(BCI_MD);
+    Args.push_back(AI);
     Args.push_back(BCI);
     Args.push_back(getTagCounter());
     CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", &LI);
@@ -1788,7 +1787,7 @@
     std::vector<Value *> Args;
     Args.push_back(getTypeMarkerConstant(&LI));
     Args.push_back(getSizeConstant(LI.getType()));
-    Args.push_back(BCI_MD);
+    Args.push_back(AI);
     Args.push_back(BCI);
     Args.push_back(getTagCounter());
     if(StoreInst *SI = dyn_cast<StoreInst>(II)) {
@@ -1797,7 +1796,7 @@
 
       std::vector<Value *> Args;
       Args.push_back(BCI_Dest);
-      Args.push_back(BCI_MD);
+      Args.push_back(AI);
       Args.push_back(getSizeConstant(SI->getOperand(0)->getType()));
       Args.push_back(getTagCounter());
       // Create the call to the runtime check and place it before the copying store instruction.
@@ -1810,7 +1809,7 @@
       CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", cast<Instruction>(II.getUse().getUser()));
     }
   }
-  if(BCI_MD->getNumUses() == 1) {
+  if(AI->getNumUses() == 1) {
     // No uses needed checks
     getTypeCall->eraseFromParent();
   }

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=133683&r1=133682&r2=133683&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Wed Jun 22 23:14:27 2011
@@ -69,7 +69,7 @@
   void trackInitInst(void *ptr, uint64_t size, uint32_t tag) ;
   void trackUnInitInst(void *ptr, uint64_t size, uint32_t tag) ;
   void copyTypeInfo(void *dstptr, void *srcptr, uint64_t size, uint32_t tag) ;
-  void setTypeInfo(void *dstptr, void *metadata, uint64_t size, uint32_t tag) ;
+  void setTypeInfo(void *dstptr, TypeTagTy *metadata, uint64_t size, uint32_t tag) ;
   void setVAInfo(void *va_list, uint64_t totalCount, TypeTagTy *metadata_ptr, uint32_t tag) ;
   void copyVAInfo(void *va_list_dst, void *va_list_src, uint32_t tag) ;
   void trackctype(void *ptr, uint32_t tag) ;
@@ -290,7 +290,7 @@
 /**
  * Copy size bytes of metadata from metadata to dest ptr
  */
-void setTypeInfo(void *dstptr, void *metadata, uint64_t size, uint32_t tag) {
+void setTypeInfo(void *dstptr, TypeTagTy *metadata, uint64_t size, uint32_t tag) {
   uintptr_t d = maskAddress(dstptr);
   memcpy(&shadow_begin[d], metadata, size);
 }



From clattner at apple.com  Wed Jun 22 23:39:31 2011
From: clattner at apple.com (Chris Lattner)
Date: Wed, 22 Jun 2011 21:39:31 -0700
Subject: [llvm-commits] [llvm] r133669 -
 /llvm/trunk/include/llvm/Target/TargetAsmInfo.h
In-Reply-To: <20110623001258.50ACE2A6C12C@llvm.org>
References: <20110623001258.50ACE2A6C12C@llvm.org>
Message-ID: <A78BC59B-CC3E-4157-AB29-143C97E0BC66@apple.com>


On Jun 22, 2011, at 5:12 PM, Bill Wendling wrote:

> Author: void
> Date: Wed Jun 22 19:12:58 2011
> New Revision: 133669
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133669&view=rev
> Log:
> Allow the AsmInfo to query the TLOF to see if it supports compact unwind.

Hi Bill,

Why have this *and* getCompactUnwindSection?  Can't getCompactUnwindSection just return null if there is no support?  If we need the predicate, it would be better to name this just "supportsCompactUnwindInfo() or better yet "hasCompactUnwindInfoSupport()"

-Chris

> 
> Modified:
>    llvm/trunk/include/llvm/Target/TargetAsmInfo.h
> 
> Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=133669&r1=133668&r2=133669&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
> +++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Wed Jun 22 19:12:58 2011
> @@ -79,6 +79,10 @@
>     return TLOF->isFunctionEHFrameSymbolPrivate();
>   }
> 
> +  bool getSupportsCompactUnwindInfo() const {
> +    return TLOF->getSupportsCompactUnwindInfo();
> +  }
> +
>   const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const {
>     return TRI->getCalleeSavedRegs(MF);
>   }
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From isanbard at gmail.com  Wed Jun 22 23:58:57 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Wed, 22 Jun 2011 21:58:57 -0700
Subject: [llvm-commits] [llvm] r133669 -
	/llvm/trunk/include/llvm/Target/TargetAsmInfo.h
In-Reply-To: <A78BC59B-CC3E-4157-AB29-143C97E0BC66@apple.com>
References: <20110623001258.50ACE2A6C12C@llvm.org>
	<A78BC59B-CC3E-4157-AB29-143C97E0BC66@apple.com>
Message-ID: <84C2641A-D017-4061-99B5-2357EB0172DD@gmail.com>

On Jun 22, 2011, at 9:39 PM, Chris Lattner wrote:

> On Jun 22, 2011, at 5:12 PM, Bill Wendling wrote:
> 
>> Author: void
>> Date: Wed Jun 22 19:12:58 2011
>> New Revision: 133669
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=133669&view=rev
>> Log:
>> Allow the AsmInfo to query the TLOF to see if it supports compact unwind.
> 
> Hi Bill,
> 
> Why have this *and* getCompactUnwindSection?  Can't getCompactUnwindSection just return null if there is no support?

I was thinking of that. I can't think of a reason to have both of them, so I'll opt for returning the MCSection pointer one. If it turns out that we need a predicate, it'll be easy to add later. :-)

> If we need the predicate, it would be better to name this just "supportsCompactUnwindInfo() or better yet "hasCompactUnwindInfoSupport()"

-bw



From isanbard at gmail.com  Thu Jun 23 00:13:28 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 23 Jun 2011 05:13:28 -0000
Subject: [llvm-commits] [llvm] r133685 - in /llvm/trunk:
 include/llvm/Target/TargetAsmInfo.h
 include/llvm/Target/TargetLoweringObjectFile.h
 lib/CodeGen/TargetLoweringObjectFileImpl.cpp lib/MC/MCDwarf.cpp
 lib/Target/TargetLoweringObjectFile.cpp
Message-ID: <20110623051328.8265A2A6C12C@llvm.org>

Author: void
Date: Thu Jun 23 00:13:28 2011
New Revision: 133685

URL: http://llvm.org/viewvc/llvm-project?rev=133685&view=rev
Log:
Use the presence of the __compact_unwind section to indicate that a target
supports compact unwind info instead of having a separate flag indicating this.

Modified:
    llvm/trunk/include/llvm/Target/TargetAsmInfo.h
    llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h
    llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
    llvm/trunk/lib/MC/MCDwarf.cpp
    llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp

Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=133685&r1=133684&r2=133685&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Thu Jun 23 00:13:28 2011
@@ -83,10 +83,6 @@
     return TLOF->isFunctionEHFrameSymbolPrivate();
   }
 
-  bool getSupportsCompactUnwindInfo() const {
-    return TLOF->getSupportsCompactUnwindInfo();
-  }
-
   const unsigned *getCalleeSavedRegs(MachineFunction *MF = 0) const {
     return TRI->getCalleeSavedRegs(MF);
   }

Modified: llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h?rev=133685&r1=133684&r2=133685&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLoweringObjectFile.h Thu Jun 23 00:13:28 2011
@@ -108,10 +108,6 @@
   /// non-.globl label.  This defaults to true.
   bool IsFunctionEHFrameSymbolPrivate;
 
-  /// SupportsCompactUnwindInfo - This flag is set to true if the CIE and FDE
-  /// information should be emitted in a compact form.
-  bool SupportsCompactUnwindInfo;
-
 public:
   MCContext &getContext() const { return *Ctx; }
   
@@ -133,9 +129,6 @@
   bool getCommDirectiveSupportsAlignment() const {
     return CommDirectiveSupportsAlignment;
   }
-  bool getSupportsCompactUnwindInfo() const {
-    return SupportsCompactUnwindInfo;
-  }
 
   const MCSection *getTextSection() const { return TextSection; }
   const MCSection *getDataSection() const { return DataSection; }

Modified: llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp?rev=133685&r1=133684&r2=133685&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringObjectFileImpl.cpp Thu Jun 23 00:13:28 2011
@@ -487,12 +487,8 @@
 
   // .comm doesn't support alignment before Leopard.
   Triple T(((LLVMTargetMachine&)TM).getTargetTriple());
-  if (T.isMacOSX()) {
-    if (T.isMacOSXVersionLT(10, 5))
-      CommDirectiveSupportsAlignment = false;
-    if (!T.isMacOSXVersionLT(10, 6))
-      SupportsCompactUnwindInfo = true;
-  }
+  if (T.isMacOSX() && T.isMacOSXVersionLT(10, 5))
+    CommDirectiveSupportsAlignment = false;
 
   TargetLoweringObjectFile::Initialize(Ctx, TM);
 
@@ -610,10 +606,11 @@
   LSDASection = getContext().getMachOSection("__TEXT", "__gcc_except_tab", 0,
                                              SectionKind::getReadOnlyWithRel());
 
-  CompactUnwindSection =
-    getContext().getMachOSection("__LD", "__compact_unwind",
-                                 MCSectionMachO::S_ATTR_DEBUG,
-                                 SectionKind::getReadOnly());
+  if (T.isMacOSX() && !T.isMacOSXVersionLT(10, 6))
+    CompactUnwindSection =
+      getContext().getMachOSection("__LD", "__compact_unwind",
+                                   MCSectionMachO::S_ATTR_DEBUG,
+                                   SectionKind::getReadOnly());
 
   // Debug Information.
   DwarfAbbrevSection =

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=133685&r1=133684&r2=133685&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Thu Jun 23 00:13:28 2011
@@ -917,7 +917,7 @@
     CIEKey key(frame.Personality, frame.PersonalityEncoding,
                frame.LsdaEncoding);
     const MCSymbol *&cieStart = isEH ? CIEStarts[key] : DummyDebugKey;
-    if (isEH && asmInfo.getSupportsCompactUnwindInfo() &&
+    if (isEH && asmInfo.getCompactUnwindSection() &&
         Emitter.EmitCompactUnwind(streamer, frame))
       continue;
 

Modified: llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp?rev=133685&r1=133684&r2=133685&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp (original)
+++ llvm/trunk/lib/Target/TargetLoweringObjectFile.cpp Thu Jun 23 00:13:28 2011
@@ -61,7 +61,6 @@
   
   IsFunctionEHFrameSymbolPrivate = true;
   SupportsWeakOmittedEHFrame = true;
-  SupportsCompactUnwindInfo = false;
 }
 
 TargetLoweringObjectFile::~TargetLoweringObjectFile() {



From aggarwa4 at illinois.edu  Thu Jun 23 00:28:17 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 05:28:17 -0000
Subject: [llvm-commits] [poolalloc] r133686 - in /poolalloc/trunk:
 lib/AssistDS/TypeChecks.cpp runtime/DynamicTypeChecks/TypeRuntime.cpp
Message-ID: <20110623052817.DA8D12A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Jun 23 00:28:17 2011
New Revision: 133686

URL: http://llvm.org/viewvc/llvm-project?rev=133686&view=rev
Log:
Add a tag to getTypeTag.

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133686&r1=133685&r2=133686&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 23 00:28:17 2011
@@ -189,6 +189,7 @@
                                      VoidPtrTy, /*ptr*/
                                      Int64Ty, /*size*/
                                      TypeTagPtrTy, /*dest for type tag*/
+                                     Int32Ty, /*tag*/
                                      NULL);
   checkTypeInst = M.getOrInsertFunction("checkType",
                                         VoidTy,
@@ -1766,6 +1767,7 @@
   Args1.push_back(BCI);
   Args1.push_back(getSizeConstant(LI.getType()));
   Args1.push_back(AI);
+  Args1.push_back(getTagCounter());
   CallInst *getTypeCall = CallInst::Create(getTypeTag, Args1.begin(), Args1.end(), "", &LI);
   if(TrackAllLoads) {
     std::vector<Value *> Args;

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=133686&r1=133685&r2=133686&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Thu Jun 23 00:28:17 2011
@@ -64,7 +64,7 @@
   void compareNumber(uint64_t NumArgsPassed, uint64_t ArgAccessed, uint32_t tag);
   void compareTypeAndNumber(uint64_t NumArgsPassed, uint64_t ArgAccessed, uint8_t TypeAccessed, void *MD, uint32_t tag) ;
   void checkVAArgType(void *va_list, TypeTagTy TypeAccessed, uint32_t tag) ;
-  void getTypeTag(void *ptr, uint64_t size, TypeTagTy *dest) ;
+  void getTypeTag(void *ptr, uint64_t size, TypeTagTy *dest, uint32_t tag) ;
   void checkType(TypeTagTy typeNumber, uint64_t size, TypeTagTy *metadata, void *ptr, uint32_t tag);
   void trackInitInst(void *ptr, uint64_t size, uint32_t tag) ;
   void trackUnInitInst(void *ptr, uint64_t size, uint32_t tag) ;
@@ -212,7 +212,7 @@
  * For loads, return the metadata(for size bytes) stored at the ptr
  * Store it in dest
  */
-void getTypeTag(void *ptr, uint64_t size, TypeTagTy *dest) {
+void getTypeTag(void *ptr, uint64_t size, TypeTagTy *dest, uint32_t tag) {
   uintptr_t p = maskAddress(ptr);
   assert(p + size < SIZE);
 



From aggarwa4 at illinois.edu  Thu Jun 23 00:29:26 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 05:29:26 -0000
Subject: [llvm-commits] [poolalloc] r133687 -
	/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
Message-ID: <20110623052926.C5E3E2A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Jun 23 00:29:26 2011
New Revision: 133687

URL: http://llvm.org/viewvc/llvm-project?rev=133687&view=rev
Log:
Remove calls to getTagType on optimization.

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=133687&r1=133686&r2=133687&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Thu Jun 23 00:29:26 2011
@@ -51,6 +51,7 @@
 static Constant *copyTypeInfo;
 static Constant *setTypeInfo;
 static Constant *checkTypeInst;
+static Constant *getTypeTag;
 static Constant *MallocFunc;
 
 bool TypeChecksOpt::runOnModule(Module &M) {
@@ -118,6 +119,12 @@
                                            VoidPtrTy,
                                            Int32Ty,
                                            NULL);
+  getTypeTag = M.getOrInsertFunction("getTypeTag",
+                                     VoidTy,
+                                     VoidPtrTy, /*ptr*/
+                                     Int64Ty, /*size*/
+                                     TypeTagPtrTy, /*dest for type tag*/
+                                     NULL);
   MallocFunc = M.getFunction("malloc");
 
   for(Value::use_iterator User = trackGlobal->use_begin(); User != trackGlobal->use_end(); ++User) {
@@ -214,6 +221,14 @@
     }
   }
 
+  for(Value::use_iterator User = getTypeTag->use_begin(); User != getTypeTag->use_end(); ++User) {
+    CallInst *CI = dyn_cast<CallInst>(User);
+    assert(CI);
+    if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) {
+      toDelete.push_back(CI);
+    }
+  }
+
   numSafe += toDelete.size();
 
   while(!toDelete.empty()) {



From echristo at apple.com  Thu Jun 23 01:24:53 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 23 Jun 2011 06:24:53 -0000
Subject: [llvm-commits] [llvm] r133700 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/MC/ lib/Target/CppBackend/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
Message-ID: <20110623062453.6C8DB2A6C12C@llvm.org>

Author: echristo
Date: Thu Jun 23 01:24:52 2011
New Revision: 133700

URL: http://llvm.org/viewvc/llvm-project?rev=133700&view=rev
Log:
Revert r133513:

"Reinstate r133435 and r133449 (reverted in r133499) now that the clang
self-hosted build failure has been fixed (r133512)."

Due to some additional warnings.


Modified:
    llvm/trunk/include/llvm/BasicBlock.h
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/CFG.h
    llvm/trunk/include/llvm/Use.h
    llvm/trunk/lib/MC/MCAsmStreamer.cpp
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
    llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
    llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp
    llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
    llvm/trunk/lib/Transforms/Utils/Local.cpp
    llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
    llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
    llvm/trunk/lib/VMCore/BasicBlock.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp
    llvm/trunk/lib/VMCore/User.cpp
    llvm/trunk/lib/VMCore/Value.cpp
    llvm/trunk/lib/VMCore/Verifier.cpp

Modified: llvm/trunk/include/llvm/BasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BasicBlock.h?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/include/llvm/BasicBlock.h (original)
+++ llvm/trunk/include/llvm/BasicBlock.h Thu Jun 23 01:24:52 2011
@@ -110,7 +110,7 @@
         Function *getParent()       { return Parent; }
 
   /// use_back - Specialize the methods defined in Value, as we know that an
-  /// BasicBlock can only be used by Users (specifically terminators
+  /// BasicBlock can only be used by Users (specifically PHI nodes, terminators,
   /// and BlockAddress's).
   User       *use_back()       { return cast<User>(*use_begin());}
   const User *use_back() const { return cast<User>(*use_begin());}
@@ -248,10 +248,6 @@
   /// other than direct branches, switches, etc. to it.
   bool hasAddressTaken() const { return getSubclassDataFromValue() != 0; }
 
-  /// replaceSuccessorsPhiUsesWith - Update all phi nodes in all our successors
-  /// to refer to basic block New instead of to us.
-  void replaceSuccessorsPhiUsesWith(BasicBlock *New);
-
 private:
   /// AdjustBlockAddressRefCount - BasicBlock stores the number of BlockAddress
   /// objects using it.  This is almost always 0, sometimes one, possibly but

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Thu Jun 23 01:24:52 2011
@@ -1814,7 +1814,7 @@
   explicit PHINode(const Type *Ty, unsigned NumReservedValues,
                    const Twine &NameStr = "", Instruction *InsertBefore = 0)
     : Instruction(Ty, Instruction::PHI, 0, 0, InsertBefore),
-      ReservedSpace(NumReservedValues) {
+      ReservedSpace(NumReservedValues * 2) {
     setName(NameStr);
     OperandList = allocHungoffUses(ReservedSpace);
   }
@@ -1822,16 +1822,11 @@
   PHINode(const Type *Ty, unsigned NumReservedValues, const Twine &NameStr,
           BasicBlock *InsertAtEnd)
     : Instruction(Ty, Instruction::PHI, 0, 0, InsertAtEnd),
-      ReservedSpace(NumReservedValues) {
+      ReservedSpace(NumReservedValues * 2) {
     setName(NameStr);
     OperandList = allocHungoffUses(ReservedSpace);
   }
 protected:
-  // allocHungoffUses - this is more complicated than the generic
-  // User::allocHungoffUses, because we have to allocate Uses for the incoming
-  // values and pointers to the incoming blocks, all in one allocation.
-  Use *allocHungoffUses(unsigned) const;
-
   virtual PHINode *clone_impl() const;
 public:
   /// Constructors - NumReservedValues is a hint for the number of incoming
@@ -1850,55 +1845,32 @@
   /// Provide fast operand accessors
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
 
-  // Block iterator interface. This provides access to the list of incoming
-  // basic blocks, which parallels the list of incoming values.
-
-  typedef BasicBlock **block_iterator;
-  typedef BasicBlock * const *const_block_iterator;
-
-  block_iterator block_begin() {
-    Use::UserRef *ref =
-      reinterpret_cast<Use::UserRef*>(op_begin() + ReservedSpace);
-    return reinterpret_cast<block_iterator>(ref + 1);
-  }
-
-  const_block_iterator block_begin() const {
-    const Use::UserRef *ref =
-      reinterpret_cast<const Use::UserRef*>(op_begin() + ReservedSpace);
-    return reinterpret_cast<const_block_iterator>(ref + 1);
-  }
-
-  block_iterator block_end() {
-    return block_begin() + getNumOperands();
-  }
-
-  const_block_iterator block_end() const {
-    return block_begin() + getNumOperands();
-  }
-
   /// getNumIncomingValues - Return the number of incoming edges
   ///
-  unsigned getNumIncomingValues() const { return getNumOperands(); }
+  unsigned getNumIncomingValues() const { return getNumOperands()/2; }
 
   /// getIncomingValue - Return incoming value number x
   ///
   Value *getIncomingValue(unsigned i) const {
-    return getOperand(i);
+    assert(i*2 < getNumOperands() && "Invalid value number!");
+    return getOperand(i*2);
   }
   void setIncomingValue(unsigned i, Value *V) {
-    setOperand(i, V);
+    assert(i*2 < getNumOperands() && "Invalid value number!");
+    setOperand(i*2, V);
   }
   static unsigned getOperandNumForIncomingValue(unsigned i) {
-    return i;
+    return i*2;
   }
   static unsigned getIncomingValueNumForOperand(unsigned i) {
-    return i;
+    assert(i % 2 == 0 && "Invalid incoming-value operand index!");
+    return i/2;
   }
 
   /// getIncomingBlock - Return incoming basic block number @p i.
   ///
   BasicBlock *getIncomingBlock(unsigned i) const {
-    return block_begin()[i];
+    return cast<BasicBlock>(getOperand(i*2+1));
   }
 
   /// getIncomingBlock - Return incoming basic block corresponding
@@ -1906,7 +1878,7 @@
   ///
   BasicBlock *getIncomingBlock(const Use &U) const {
     assert(this == U.getUser() && "Iterator doesn't point to PHI's Uses?");
-    return getIncomingBlock(&U - op_begin());
+    return cast<BasicBlock>((&U + 1)->get());
   }
 
   /// getIncomingBlock - Return incoming basic block corresponding
@@ -1917,8 +1889,16 @@
     return getIncomingBlock(I.getUse());
   }
 
+
   void setIncomingBlock(unsigned i, BasicBlock *BB) {
-    block_begin()[i] = BB;
+    setOperand(i*2+1, (Value*)BB);
+  }
+  static unsigned getOperandNumForIncomingBlock(unsigned i) {
+    return i*2+1;
+  }
+  static unsigned getIncomingBlockNumForOperand(unsigned i) {
+    assert(i % 2 == 1 && "Invalid incoming-block operand index!");
+    return i/2;
   }
 
   /// addIncoming - Add an incoming value to the end of the PHI list
@@ -1928,12 +1908,13 @@
     assert(BB && "PHI node got a null basic block!");
     assert(getType() == V->getType() &&
            "All operands to PHI node must be the same type as the PHI node!");
-    if (NumOperands == ReservedSpace)
+    unsigned OpNo = NumOperands;
+    if (OpNo+2 > ReservedSpace)
       growOperands();  // Get more space!
     // Initialize some new operands.
-    ++NumOperands;
-    setIncomingValue(NumOperands - 1, V);
-    setIncomingBlock(NumOperands - 1, BB);
+    NumOperands = OpNo+2;
+    OperandList[OpNo] = V;
+    OperandList[OpNo+1] = (Value*)BB;
   }
 
   /// removeIncomingValue - Remove an incoming value.  This is useful if a
@@ -1956,16 +1937,14 @@
   /// block in the value list for this PHI.  Returns -1 if no instance.
   ///
   int getBasicBlockIndex(const BasicBlock *BB) const {
-    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
-      if (block_begin()[i] == BB)
-        return i;
+    Use *OL = OperandList;
+    for (unsigned i = 0, e = getNumOperands(); i != e; i += 2)
+      if (OL[i+1].get() == (const Value*)BB) return i/2;
     return -1;
   }
 
   Value *getIncomingValueForBlock(const BasicBlock *BB) const {
-    int Idx = getBasicBlockIndex(BB);
-    assert(Idx >= 0 && "Invalid basic block argument!");
-    return getIncomingValue(Idx);
+    return getIncomingValue(getBasicBlockIndex(BB));
   }
 
   /// hasConstantValue - If the specified PHI node always merges together the

Modified: llvm/trunk/include/llvm/Support/CFG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CFG.h?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CFG.h (original)
+++ llvm/trunk/include/llvm/Support/CFG.h Thu Jun 23 01:24:52 2011
@@ -33,7 +33,7 @@
   USE_iterator It;
 
   inline void advancePastNonTerminators() {
-    // Loop to ignore non terminator uses (for example BlockAddresses).
+    // Loop to ignore non terminator uses (for example PHI nodes).
     while (!It.atEnd() && !isa<TerminatorInst>(*It))
       ++It;
   }

Modified: llvm/trunk/include/llvm/Use.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Use.h?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Use.h (original)
+++ llvm/trunk/include/llvm/Use.h Thu Jun 23 01:24:52 2011
@@ -112,16 +112,13 @@
   Use *getNext() const { return Next; }
 
   
-  /// initTags - initialize the waymarking tags on an array of Uses, so that
-  /// getUser() can find the User from any of those Uses.
-  static Use *initTags(Use *Start, Use *Stop);
-
   /// zap - This is used to destroy Use operands when the number of operands of
   /// a User changes.
   static void zap(Use *Start, const Use *Stop, bool del = false);
 
 private:
   const Use* getImpliedUser() const;
+  static Use *initTags(Use *Start, Use *Stop);
   
   Value *Val;
   Use *Next;
@@ -143,6 +140,7 @@
   }
 
   friend class Value;
+  friend class User;
 };
 
 // simplify_type - Allow clients to treat uses just like values when using

Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Thu Jun 23 01:24:52 2011
@@ -1119,7 +1119,7 @@
     } else {
       // Otherwise, write out in binary.
       OS << "0b";
-      for (unsigned j = 8; j--;) {
+      for (int j = 7; j >= 0; j--) {
         unsigned Bit = (Code[i] >> j) & 1;
 
         unsigned FixupBit;
@@ -1128,9 +1128,9 @@
         else
           FixupBit = i * 8 + (7-j);
 
-        if (uint8_t MapEntry = FixupMap[FixupBit]) {
-          assert(Bit == 0 && "Encoder wrote into fixed up bit!");
-          OS << char('A' + MapEntry - 1);
+        if (uint8_t FixupMapEntry = FixupMap[FixupBit]) {
+          //assert(Bit == 0 && "Encoder wrote into fixed up bit!");
+          OS << char('A' + FixupMapEntry - 1);
         } else
           OS << Bit;
       }

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Thu Jun 23 01:24:52 2011
@@ -1356,7 +1356,7 @@
     for (unsigned i = 0; i < phi->getNumIncomingValues(); ++i) {
       Out << iName << "->addIncoming("
           << opNames[PHINode::getOperandNumForIncomingValue(i)] << ", "
-          << getOpName(phi->getIncomingBlock(i)) << ");";
+          << opNames[PHINode::getOperandNumForIncomingBlock(i)] << ");";
       nl(Out);
     }
     break;

Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Thu Jun 23 01:24:52 2011
@@ -1021,10 +1021,6 @@
         while (PHINode *PN = dyn_cast<PHINode>(Succ->begin()))
           ReplaceUsesOfWith(PN, PN->getIncomingValue(0), Worklist, L, LPM);
         
-        // If Succ has any successors with PHI nodes, update them to have
-        // entries coming from Pred instead of Succ.
-        Succ->replaceAllUsesWith(Pred);
-        
         // Move all of the successor contents from Succ to Pred.
         Pred->getInstList().splice(BI, Succ->getInstList(), Succ->begin(),
                                    Succ->end());
@@ -1032,6 +1028,10 @@
         BI->eraseFromParent();
         RemoveFromWorklist(BI, Worklist);
         
+        // If Succ has any successors with PHI nodes, update them to have
+        // entries coming from Pred instead of Succ.
+        Succ->replaceAllUsesWith(Pred);
+        
         // Remove Succ from the loop tree.
         LI->removeBlock(Succ);
         LPM->deleteSimpleAnalysisValue(Succ, L);

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Thu Jun 23 01:24:52 2011
@@ -153,13 +153,13 @@
   // Delete the unconditional branch from the predecessor...
   PredBB->getInstList().pop_back();
   
+  // Move all definitions in the successor to the predecessor...
+  PredBB->getInstList().splice(PredBB->end(), BB->getInstList());
+  
   // Make all PHI nodes that referred to BB now refer to Pred as their
   // source...
   BB->replaceAllUsesWith(PredBB);
   
-  // Move all definitions in the successor to the predecessor...
-  PredBB->getInstList().splice(PredBB->end(), BB->getInstList());
-  
   // Inherit predecessors name if it exists.
   if (!PredBB->hasName())
     PredBB->takeName(BB);

Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Thu Jun 23 01:24:52 2011
@@ -193,22 +193,44 @@
   
   // If there are any PHI nodes in DestBB, we need to update them so that they
   // merge incoming values from NewBB instead of from TIBB.
-  {
-    unsigned BBIdx = 0;
-    for (BasicBlock::iterator I = DestBB->begin(); isa<PHINode>(I); ++I) {
-      // We no longer enter through TIBB, now we come in through NewBB.
-      // Revector exactly one entry in the PHI node that used to come from
-      // TIBB to come from NewBB.
-      PHINode *PN = cast<PHINode>(I);
-
-      // Reuse the previous value of BBIdx if it lines up.  In cases where we
-      // have multiple phi nodes with *lots* of predecessors, this is a speed
-      // win because we don't have to scan the PHI looking for TIBB.  This
-      // happens because the BB list of PHI nodes are usually in the same
-      // order.
-      if (PN->getIncomingBlock(BBIdx) != TIBB)
-	BBIdx = PN->getBasicBlockIndex(TIBB);
-      PN->setIncomingBlock(BBIdx, NewBB);
+  if (PHINode *APHI = dyn_cast<PHINode>(DestBB->begin())) {
+    // This conceptually does:
+    //  foreach (PHINode *PN in DestBB)
+    //    PN->setIncomingBlock(PN->getIncomingBlock(TIBB), NewBB);
+    // but is optimized for two cases.
+    
+    if (APHI->getNumIncomingValues() <= 8) {  // Small # preds case.
+      unsigned BBIdx = 0;
+      for (BasicBlock::iterator I = DestBB->begin(); isa<PHINode>(I); ++I) {
+        // We no longer enter through TIBB, now we come in through NewBB.
+        // Revector exactly one entry in the PHI node that used to come from
+        // TIBB to come from NewBB.
+        PHINode *PN = cast<PHINode>(I);
+        
+        // Reuse the previous value of BBIdx if it lines up.  In cases where we
+        // have multiple phi nodes with *lots* of predecessors, this is a speed
+        // win because we don't have to scan the PHI looking for TIBB.  This
+        // happens because the BB list of PHI nodes are usually in the same
+        // order.
+        if (PN->getIncomingBlock(BBIdx) != TIBB)
+          BBIdx = PN->getBasicBlockIndex(TIBB);
+        PN->setIncomingBlock(BBIdx, NewBB);
+      }
+    } else {
+      // However, the foreach loop is slow for blocks with lots of predecessors
+      // because PHINode::getIncomingBlock is O(n) in # preds.  Instead, walk
+      // the user list of TIBB to find the PHI nodes.
+      SmallPtrSet<PHINode*, 16> UpdatedPHIs;
+    
+      for (Value::use_iterator UI = TIBB->use_begin(), E = TIBB->use_end();
+           UI != E; ) {
+        Value::use_iterator Use = UI++;
+        if (PHINode *PN = dyn_cast<PHINode>(*Use)) {
+          // Remove one entry from each PHI.
+          if (PN->getParent() == DestBB && UpdatedPHIs.insert(PN))
+            PN->setOperand(Use.getOperandNo(), NewBB);
+        }
+      }
     }
   }
    

Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Thu Jun 23 01:24:52 2011
@@ -572,12 +572,12 @@
     // removed, so we just need to splice the blocks.
     BI->eraseFromParent();
     
-    // Make all PHI nodes that referred to Dest now refer to I as their source.
-    Dest->replaceAllUsesWith(I);
-
     // Move all the instructions in the succ to the pred.
     I->getInstList().splice(I->end(), Dest->getInstList());
     
+    // Make all PHI nodes that referred to Dest now refer to I as their source.
+    Dest->replaceAllUsesWith(I);
+
     // Remove the dest block.
     Dest->eraseFromParent();
     

Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Thu Jun 23 01:24:52 2011
@@ -1097,15 +1097,15 @@
         TheCall->replaceAllUsesWith(Returns[0]->getReturnValue());
     }
 
-    // Update PHI nodes that use the ReturnBB to use the AfterCallBB.
-    BasicBlock *ReturnBB = Returns[0]->getParent();
-    ReturnBB->replaceAllUsesWith(AfterCallBB);
-
     // Splice the code from the return block into the block that it will return
     // to, which contains the code that was after the call.
+    BasicBlock *ReturnBB = Returns[0]->getParent();
     AfterCallBB->getInstList().splice(AfterCallBB->begin(),
                                       ReturnBB->getInstList());
 
+    // Update PHI nodes that use the ReturnBB to use the AfterCallBB.
+    ReturnBB->replaceAllUsesWith(AfterCallBB);
+
     // Delete the return instruction now and empty ReturnBB now.
     Returns[0]->eraseFromParent();
     ReturnBB->eraseFromParent();
@@ -1125,8 +1125,8 @@
 
   // Splice the code entry block into calling block, right before the
   // unconditional branch.
-  CalleeEntry->replaceAllUsesWith(OrigBB);  // Update PHI nodes
   OrigBB->getInstList().splice(Br, CalleeEntry->getInstList());
+  CalleeEntry->replaceAllUsesWith(OrigBB);  // Update PHI nodes
 
   // Remove the unconditional branch.
   OrigBB->getInstList().erase(Br);

Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/Local.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/Local.cpp Thu Jun 23 01:24:52 2011
@@ -427,6 +427,10 @@
   BasicBlock *PredBB = DestBB->getSinglePredecessor();
   assert(PredBB && "Block doesn't have a single predecessor!");
   
+  // Splice all the instructions from PredBB to DestBB.
+  PredBB->getTerminator()->eraseFromParent();
+  DestBB->getInstList().splice(DestBB->begin(), PredBB->getInstList());
+
   // Zap anything that took the address of DestBB.  Not doing this will give the
   // address an invalid value.
   if (DestBB->hasAddressTaken()) {
@@ -441,10 +445,6 @@
   // Anything that branched to PredBB now branches to DestBB.
   PredBB->replaceAllUsesWith(DestBB);
   
-  // Splice all the instructions from PredBB to DestBB.
-  PredBB->getTerminator()->eraseFromParent();
-  DestBB->getInstList().splice(DestBB->begin(), PredBB->getInstList());
-
   if (P) {
     DominatorTree *DT = P->getAnalysisIfAvailable<DominatorTree>();
     if (DT) {
@@ -660,17 +660,12 @@
     // them, which helps expose duplicates, but we have to check all the
     // operands to be safe in case instcombine hasn't run.
     uintptr_t Hash = 0;
-    // This hash algorithm is quite weak as hash functions go, but it seems
-    // to do a good enough job for this particular purpose, and is very quick.
     for (User::op_iterator I = PN->op_begin(), E = PN->op_end(); I != E; ++I) {
+      // This hash algorithm is quite weak as hash functions go, but it seems
+      // to do a good enough job for this particular purpose, and is very quick.
       Hash ^= reinterpret_cast<uintptr_t>(static_cast<Value *>(*I));
       Hash = (Hash << 7) | (Hash >> (sizeof(uintptr_t) * CHAR_BIT - 7));
     }
-    for (PHINode::block_iterator I = PN->block_begin(), E = PN->block_end();
-         I != E; ++I) {
-      Hash ^= reinterpret_cast<uintptr_t>(static_cast<BasicBlock *>(*I));
-      Hash = (Hash << 7) | (Hash >> (sizeof(uintptr_t) * CHAR_BIT - 7));
-    }
     // Avoid colliding with the DenseMap sentinels ~0 and ~0-1.
     Hash >>= 1;
     // If we've never seen this hash value before, it's a unique PHI.

Modified: llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp Thu Jun 23 01:24:52 2011
@@ -47,14 +47,6 @@
     if (It != VMap.end())
       I->setOperand(op, It->second);
   }
-
-  if (PHINode *PN = dyn_cast<PHINode>(I)) {
-    for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
-      ValueToValueMapTy::iterator It = VMap.find(PN->getIncomingBlock(i));
-      if (It != VMap.end())
-        PN->setIncomingBlock(i, cast<BasicBlock>(It->second));
-    }
-  }
 }
 
 /// FoldBlockIntoPredecessor - Folds a basic block into its predecessor if it
@@ -83,13 +75,13 @@
   // Delete the unconditional branch from the predecessor...
   OnlyPred->getInstList().pop_back();
 
+  // Move all definitions in the successor to the predecessor...
+  OnlyPred->getInstList().splice(OnlyPred->end(), BB->getInstList());
+
   // Make all PHI nodes that referred to BB now refer to Pred as their
   // source...
   BB->replaceAllUsesWith(OnlyPred);
 
-  // Move all definitions in the successor to the predecessor...
-  OnlyPred->getInstList().splice(OnlyPred->end(), BB->getInstList());
-
   std::string OldName = BB->getName();
 
   // Erase basic block from the function...
@@ -129,14 +121,14 @@
 
   BasicBlock *Header = L->getHeader();
   BranchInst *BI = dyn_cast<BranchInst>(LatchBlock->getTerminator());
-  
+
   if (!BI || BI->isUnconditional()) {
     // The loop-rotate pass can be helpful to avoid this in many cases.
     DEBUG(dbgs() <<
              "  Can't unroll; loop not terminated by a conditional branch.\n");
     return false;
   }
-  
+
   if (Header->hasAddressTaken()) {
     // The loop-rotate pass can be helpful to avoid this in many cases.
     DEBUG(dbgs() <<
@@ -210,7 +202,7 @@
   for (BasicBlock::iterator I = Header->begin(); isa<PHINode>(I); ++I) {
     PHINode *PN = cast<PHINode>(I);
     OrigPHINode.push_back(PN);
-    if (Instruction *I = 
+    if (Instruction *I =
                 dyn_cast<Instruction>(PN->getIncomingValueForBlock(LatchBlock)))
       if (L->contains(I))
         LastValueMap[I] = I;
@@ -223,7 +215,7 @@
 
   for (unsigned It = 1; It != Count; ++It) {
     std::vector<BasicBlock*> NewBlocks;
-    
+
     for (std::vector<BasicBlock*>::iterator BB = LoopBlocks.begin(),
          E = LoopBlocks.end(); BB != E; ++BB) {
       ValueToValueMapTy VMap;
@@ -255,14 +247,16 @@
       // the successor of the latch block.  The successor of the exit block will
       // be updated specially after unrolling all the way.
       if (*BB != LatchBlock)
-        for (succ_iterator SI = succ_begin(*BB), SE = succ_end(*BB); SI != SE;
-             ++SI)
-          if (!L->contains(*SI))
-            for (BasicBlock::iterator BBI = (*SI)->begin();
-                 PHINode *phi = dyn_cast<PHINode>(BBI); ++BBI) {
-              Value *Incoming = phi->getIncomingValueForBlock(*BB);
-              phi->addIncoming(Incoming, New);
-            }
+        for (Value::use_iterator UI = (*BB)->use_begin(), UE = (*BB)->use_end();
+             UI != UE;) {
+          Instruction *UseInst = cast<Instruction>(*UI);
+          ++UI;
+          if (isa<PHINode>(UseInst) && !L->contains(UseInst)) {
+            PHINode *phi = cast<PHINode>(UseInst);
+            Value *Incoming = phi->getIncomingValueForBlock(*BB);
+            phi->addIncoming(Incoming, New);
+          }
+        }
 
       // Keep track of new headers and latches as we create them, so that
       // we can insert the proper branches later.
@@ -282,32 +276,36 @@
 
       NewBlocks.push_back(New);
     }
-    
+
     // Remap all instructions in the most recent iteration
     for (unsigned i = 0; i < NewBlocks.size(); ++i)
       for (BasicBlock::iterator I = NewBlocks[i]->begin(),
            E = NewBlocks[i]->end(); I != E; ++I)
         ::RemapInstruction(I, LastValueMap);
   }
-  
+
   // The latch block exits the loop.  If there are any PHI nodes in the
   // successor blocks, update them to use the appropriate values computed as the
   // last iteration of the loop.
   if (Count != 1) {
+    SmallPtrSet<PHINode*, 8> Users;
+    for (Value::use_iterator UI = LatchBlock->use_begin(),
+         UE = LatchBlock->use_end(); UI != UE; ++UI)
+      if (PHINode *phi = dyn_cast<PHINode>(*UI))
+        Users.insert(phi);
+
     BasicBlock *LastIterationBB = cast<BasicBlock>(LastValueMap[LatchBlock]);
-    for (succ_iterator SI = succ_begin(LatchBlock), SE = succ_end(LatchBlock);
+    for (SmallPtrSet<PHINode*,8>::iterator SI = Users.begin(), SE = Users.end();
          SI != SE; ++SI) {
-      for (BasicBlock::iterator BBI = (*SI)->begin();
-           PHINode *PN = dyn_cast<PHINode>(BBI); ++BBI) {
-        Value *InVal = PN->removeIncomingValue(LatchBlock, false);
-        // If this value was defined in the loop, take the value defined by the
-        // last iteration of the loop.
-        if (Instruction *InValI = dyn_cast<Instruction>(InVal)) {
-          if (L->contains(InValI))
-            InVal = LastValueMap[InVal];
-        }
-        PN->addIncoming(InVal, LastIterationBB);
+      PHINode *PN = *SI;
+      Value *InVal = PN->removeIncomingValue(LatchBlock, false);
+      // If this value was defined in the loop, take the value defined by the
+      // last iteration of the loop.
+      if (Instruction *InValI = dyn_cast<Instruction>(InVal)) {
+        if (L->contains(InValI))
+          InVal = LastValueMap[InVal];
       }
+      PN->addIncoming(InVal, LastIterationBB);
     }
   }
 
@@ -354,19 +352,14 @@
       // Replace the conditional branch with an unconditional one.
       BranchInst::Create(Dest, Term);
       Term->eraseFromParent();
-    }
-  }
-
-  // Merge adjacent basic blocks, if possible.
-  for (unsigned i = 0, e = Latches.size(); i != e; ++i) {
-    BranchInst *Term = cast<BranchInst>(Latches[i]->getTerminator());
-    if (Term->isUnconditional()) {
-      BasicBlock *Dest = Term->getSuccessor(0);
-      if (BasicBlock *Fold = FoldBlockIntoPredecessor(Dest, LI))
+      // Merge adjacent basic blocks, if possible.
+      if (BasicBlock *Fold = FoldBlockIntoPredecessor(Dest, LI)) {
         std::replace(Latches.begin(), Latches.end(), Dest, Fold);
+        std::replace(Headers.begin(), Headers.end(), Dest, Fold);
+      }
     }
   }
-  
+
   // At this point, the code is well formed.  We now do a quick sweep over the
   // inserted code, doing constant propagation and dead code elimination as we
   // go.

Modified: llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp Thu Jun 23 01:24:52 2011
@@ -16,7 +16,6 @@
 #include "llvm/Type.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
-#include "llvm/Instructions.h"
 #include "llvm/Metadata.h"
 #include "llvm/ADT/SmallVector.h"
 using namespace llvm;
@@ -129,19 +128,6 @@
              "Referenced value not in value map!");
   }
 
-  // Remap phi nodes' incoming blocks.
-  if (PHINode *PN = dyn_cast<PHINode>(I)) {
-    for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
-      Value *V = MapValue(PN->getIncomingBlock(i), VMap, Flags);
-      // If we aren't ignoring missing entries, assert that something happened.
-      if (V != 0)
-        PN->setIncomingBlock(i, cast<BasicBlock>(V));
-      else
-        assert((Flags & RF_IgnoreMissingEntries) &&
-               "Referenced block not in value map!");
-    }
-  }
-
   // Remap attached metadata.
   SmallVector<std::pair<unsigned, MDNode *>, 4> MDs;
   I->getAllMetadata(MDs);

Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/BasicBlock.cpp (original)
+++ llvm/trunk/lib/VMCore/BasicBlock.cpp Thu Jun 23 01:24:52 2011
@@ -308,19 +308,3 @@
   return New;
 }
 
-void BasicBlock::replaceSuccessorsPhiUsesWith(BasicBlock *New) {
-  TerminatorInst *TI = getTerminator();
-  if (!TI)
-    // Cope with being called on a BasicBlock that doesn't have a terminator
-    // yet. Clang's CodeGenFunction::EmitReturnBlock() likes to do this.
-    return;
-  for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) {
-    BasicBlock *Succ = TI->getSuccessor(i);
-    for (iterator II = Succ->begin(); PHINode *PN = dyn_cast<PHINode>(II);
-         ++II) {
-      int i;
-      while ((i = PN->getBasicBlockIndex(this)) >= 0)
-        PN->setIncomingBlock(i, New);
-    }
-  }
-}

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Thu Jun 23 01:24:52 2011
@@ -87,8 +87,11 @@
   : Instruction(PN.getType(), Instruction::PHI,
                 allocHungoffUses(PN.getNumOperands()), PN.getNumOperands()),
     ReservedSpace(PN.getNumOperands()) {
-  std::copy(PN.op_begin(), PN.op_end(), op_begin());
-  std::copy(PN.block_begin(), PN.block_end(), block_begin());
+  Use *OL = OperandList;
+  for (unsigned i = 0, e = PN.getNumOperands(); i != e; i+=2) {
+    OL[i] = PN.getOperand(i);
+    OL[i+1] = PN.getOperand(i+1);
+  }
   SubclassOptionalData = PN.SubclassOptionalData;
 }
 
@@ -96,37 +99,31 @@
   dropHungoffUses();
 }
 
-Use *PHINode::allocHungoffUses(unsigned N) const {
-  // Allocate the array of Uses of the incoming values, followed by a pointer
-  // (with bottom bit set) to the User, followed by the array of pointers to
-  // the incoming basic blocks.
-  size_t size = N * sizeof(Use) + sizeof(Use::UserRef)
-    + N * sizeof(BasicBlock*);
-  Use *Begin = static_cast<Use*>(::operator new(size));
-  Use *End = Begin + N;
-  (void) new(End) Use::UserRef(const_cast<PHINode*>(this), 1);
-  return Use::initTags(Begin, End);
-}
-
 // removeIncomingValue - Remove an incoming value.  This is useful if a
 // predecessor basic block is deleted.
 Value *PHINode::removeIncomingValue(unsigned Idx, bool DeletePHIIfEmpty) {
-  Value *Removed = getIncomingValue(Idx);
+  unsigned NumOps = getNumOperands();
+  Use *OL = OperandList;
+  assert(Idx*2 < NumOps && "BB not in PHI node!");
+  Value *Removed = OL[Idx*2];
 
   // Move everything after this operand down.
   //
   // FIXME: we could just swap with the end of the list, then erase.  However,
-  // clients might not expect this to happen.  The code as it is thrashes the
+  // client might not expect this to happen.  The code as it is thrashes the
   // use/def lists, which is kinda lame.
-  std::copy(op_begin() + Idx + 1, op_end(), op_begin() + Idx);
-  std::copy(block_begin() + Idx + 1, block_end(), block_begin() + Idx);
+  for (unsigned i = (Idx+1)*2; i != NumOps; i += 2) {
+    OL[i-2] = OL[i];
+    OL[i-2+1] = OL[i+1];
+  }
 
   // Nuke the last value.
-  Op<-1>().set(0);
-  --NumOperands;
+  OL[NumOps-2].set(0);
+  OL[NumOps-2+1].set(0);
+  NumOperands = NumOps-2;
 
   // If the PHI node is dead, because it has zero entries, nuke it now.
-  if (getNumOperands() == 0 && DeletePHIIfEmpty) {
+  if (NumOps == 2 && DeletePHIIfEmpty) {
     // If anyone is using this PHI, make them use a dummy value instead...
     replaceAllUsesWith(UndefValue::get(getType()));
     eraseFromParent();
@@ -140,18 +137,15 @@
 ///
 void PHINode::growOperands() {
   unsigned e = getNumOperands();
-  unsigned NumOps = e + e / 2;
-  if (NumOps < 2) NumOps = 2;      // 2 op PHI nodes are VERY common.
-
-  Use *OldOps = op_begin();
-  BasicBlock **OldBlocks = block_begin();
+  // Multiply by 1.5 and round down so the result is still even.
+  unsigned NumOps = e + e / 4 * 2;
+  if (NumOps < 4) NumOps = 4;      // 4 op PHI nodes are VERY common.
 
   ReservedSpace = NumOps;
-  OperandList = allocHungoffUses(ReservedSpace);
-
-  std::copy(OldOps, OldOps + e, op_begin());
-  std::copy(OldBlocks, OldBlocks + e, block_begin());
-
+  Use *OldOps = OperandList;
+  Use *NewOps = allocHungoffUses(NumOps);
+  std::copy(OldOps, OldOps + e, NewOps);
+  OperandList = NewOps;
   Use::zap(OldOps, OldOps + e, true);
 }
 

Modified: llvm/trunk/lib/VMCore/User.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/User.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/User.cpp (original)
+++ llvm/trunk/lib/VMCore/User.cpp Thu Jun 23 01:24:52 2011
@@ -40,10 +40,8 @@
 //===----------------------------------------------------------------------===//
 
 Use *User::allocHungoffUses(unsigned N) const {
-  // Allocate the array of Uses, followed by a pointer (with bottom bit set) to
-  // the User.
-  size_t size = N * sizeof(Use) + sizeof(Use::UserRef);
-  Use *Begin = static_cast<Use*>(::operator new(size));
+  Use *Begin = static_cast<Use*>(::operator new(sizeof(Use) * N
+                                                + sizeof(Use::UserRef)));
   Use *End = Begin + N;
   (void) new(End) Use::UserRef(const_cast<User*>(this), 1);
   return Use::initTags(Begin, End);

Modified: llvm/trunk/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Value.cpp (original)
+++ llvm/trunk/lib/VMCore/Value.cpp Thu Jun 23 01:24:52 2011
@@ -305,9 +305,6 @@
 
     U.set(New);
   }
-
-  if (BasicBlock *BB = dyn_cast<BasicBlock>(this))
-    BB->replaceSuccessorsPhiUsesWith(cast<BasicBlock>(New));
 }
 
 void Value::replaceAllUsesWith(Value *New) {

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=133700&r1=133699&r2=133700&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Thu Jun 23 01:24:52 2011
@@ -1139,6 +1139,9 @@
   for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
     Assert1(PN.getType() == PN.getIncomingValue(i)->getType(),
             "PHI node operands are not the same type as the result!", &PN);
+    Assert1(isa<BasicBlock>(PN.getOperand(
+                PHINode::getOperandNumForIncomingBlock(i))),
+            "PHI node incoming block is not a BasicBlock!", &PN);
   }
 
   // All other PHI node constraints are checked in the visitBasicBlock method.



From echristo at apple.com  Thu Jun 23 01:31:47 2011
From: echristo at apple.com (Eric Christopher)
Date: Wed, 22 Jun 2011 23:31:47 -0700
Subject: [llvm-commits] [llvm] r133513 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/Target/CppBackend/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
In-Reply-To: <5AAC95DA-F372-4AC4-BF66-AF474C061E34@apple.com>
References: <20110621103319.B0D332A6C12C@llvm.org>
	<5AAC95DA-F372-4AC4-BF66-AF474C061E34@apple.com>
Message-ID: <184C58B8-49B3-40A8-A0EF-7718C77C9FB7@apple.com>


On Jun 22, 2011, at 11:24 AM, Eric Christopher wrote:

> 
> On Jun 21, 2011, at 3:33 AM, Jay Foad wrote:
> 
>> Author: foad
>> Date: Tue Jun 21 05:33:19 2011
>> New Revision: 133513
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=133513&view=rev
>> Log:
>> Reinstate r133435 and r133449 (reverted in r133499) now that the clang
>> self-hosted build failure has been fixed (r133512).
>> 
> 
> This is causing some additional warnings:
> 
> /Developer/usr/local/include/llvm/Instructions.h: In member function 'llvm::BasicBlock* llvm::PHINode::getIncomingBlock(const llvm::Use&) const':
> /Developer/usr/local/include/llvm/Instructions.h:1909: warning: implicit conversion shortens 64-bit value into a 32-bit value
> 
> To duplicate just turn on conversion warnings, in particular with llvm-gcc -Wshorten-64-to-32, in a file that includes Instructions.h.
> 
> Could you get these? Thanks.

I've gone ahead and reverted your patch in r133700 for the time being, should be an easy reapply after you fix the new header warnings :)

Thanks!

-eric

From isanbard at gmail.com  Thu Jun 23 02:44:54 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 23 Jun 2011 07:44:54 -0000
Subject: [llvm-commits] [llvm] r133706 - /llvm/trunk/lib/MC/MCDwarf.cpp
Message-ID: <20110623074454.606762A6C12D@llvm.org>

Author: void
Date: Thu Jun 23 02:44:54 2011
New Revision: 133706

URL: http://llvm.org/viewvc/llvm-project?rev=133706&view=rev
Log:
Formatting changes. No functionality change.

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=133706&r1=133705&r2=133706&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Thu Jun 23 02:44:54 2011
@@ -50,8 +50,7 @@
 
 // Note: when DWARF2_LINE_MIN_INSN_LENGTH == 1 which is the current setting,
 // this routine is a nop and will be optimized away.
-static inline uint64_t ScaleAddrDelta(uint64_t AddrDelta)
-{
+static inline uint64_t ScaleAddrDelta(uint64_t AddrDelta) {
   if (DWARF2_LINE_MIN_INSN_LENGTH == 1)
     return AddrDelta;
   if (AddrDelta % DWARF2_LINE_MIN_INSN_LENGTH != 0) {
@@ -895,46 +894,45 @@
   };
 }
 
-void MCDwarfFrameEmitter::Emit(MCStreamer &streamer,
-                               bool usingCFI,
-                               bool isEH) {
-  MCContext &context = streamer.getContext();
-  const TargetAsmInfo &asmInfo = context.getTargetAsmInfo();
-  const MCSection &section = isEH ?
-    *asmInfo.getEHFrameSection() :
-    *asmInfo.getDwarfFrameSection();
-  streamer.SwitchSection(&section);
-  MCSymbol *SectionStart = context.CreateTempSymbol();
-  streamer.EmitLabel(SectionStart);
+void MCDwarfFrameEmitter::Emit(MCStreamer &Streamer,
+                               bool UsingCFI,
+                               bool IsEH) {
+  MCContext &Context = Streamer.getContext();
+  const TargetAsmInfo &AsmInfo = Context.getTargetAsmInfo();
+  const MCSection &Section = IsEH ? *AsmInfo.getEHFrameSection() :
+                                    *AsmInfo.getDwarfFrameSection();
+  Streamer.SwitchSection(&Section);
+  MCSymbol *SectionStart = Context.CreateTempSymbol();
+  Streamer.EmitLabel(SectionStart);
 
-  MCSymbol *fdeEnd = NULL;
+  MCSymbol *FDEEnd = NULL;
   DenseMap<CIEKey, const MCSymbol*> CIEStarts;
-  FrameEmitterImpl Emitter(usingCFI, isEH, SectionStart);
+  FrameEmitterImpl Emitter(UsingCFI, IsEH, SectionStart);
 
   const MCSymbol *DummyDebugKey = NULL;
-  for (unsigned i = 0, n = streamer.getNumFrameInfos(); i < n; ++i) {
-    const MCDwarfFrameInfo &frame = streamer.getFrameInfo(i);
-    CIEKey key(frame.Personality, frame.PersonalityEncoding,
-               frame.LsdaEncoding);
-    const MCSymbol *&cieStart = isEH ? CIEStarts[key] : DummyDebugKey;
-    if (isEH && asmInfo.getCompactUnwindSection() &&
-        Emitter.EmitCompactUnwind(streamer, frame))
+  for (unsigned i = 0, n = Streamer.getNumFrameInfos(); i < n; ++i) {
+    const MCDwarfFrameInfo &Frame = Streamer.getFrameInfo(i);
+    if (IsEH && AsmInfo.getCompactUnwindSection() &&
+        Emitter.EmitCompactUnwind(Streamer, Frame))
       continue;
 
-    if (!cieStart)
-      cieStart = &Emitter.EmitCIE(streamer, frame.Personality,
-                                  frame.PersonalityEncoding, frame.Lsda,
-                                  frame.LsdaEncoding);
+    CIEKey Key(Frame.Personality, Frame.PersonalityEncoding,
+               Frame.LsdaEncoding);
+    const MCSymbol *&CIEStart = IsEH ? CIEStarts[Key] : DummyDebugKey;
+    if (!CIEStart)
+      CIEStart = &Emitter.EmitCIE(Streamer, Frame.Personality,
+                                  Frame.PersonalityEncoding, Frame.Lsda,
+                                  Frame.LsdaEncoding);
 
-    fdeEnd = Emitter.EmitFDE(streamer, *cieStart, frame);
+    FDEEnd = Emitter.EmitFDE(Streamer, *CIEStart, Frame);
 
     if (i != n - 1)
-      streamer.EmitLabel(fdeEnd);
+      Streamer.EmitLabel(FDEEnd);
   }
 
-  streamer.EmitValueToAlignment(asmInfo.getPointerSize());
-  if (fdeEnd)
-    streamer.EmitLabel(fdeEnd);
+  Streamer.EmitValueToAlignment(AsmInfo.getPointerSize());
+  if (FDEEnd)
+    Streamer.EmitLabel(FDEEnd);
 }
 
 void MCDwarfFrameEmitter::EmitAdvanceLoc(MCStreamer &Streamer,



From isanbard at gmail.com  Thu Jun 23 02:55:41 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 23 Jun 2011 07:55:41 -0000
Subject: [llvm-commits] [llvm] r133707 - /llvm/trunk/lib/MC/MCDwarf.cpp
Message-ID: <20110623075541.DD1762A6C12D@llvm.org>

Author: void
Date: Thu Jun 23 02:55:41 2011
New Revision: 133707

URL: http://llvm.org/viewvc/llvm-project?rev=133707&view=rev
Log:
Use a reference. Don't make a useless copy of the vector.

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=133707&r1=133706&r2=133707&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Thu Jun 23 02:55:41 2011
@@ -759,7 +759,7 @@
 
   // Initial Instructions
 
-  const std::vector<MachineMove> Moves = asmInfo.getInitialFrameState();
+  const std::vector<MachineMove> &Moves = asmInfo.getInitialFrameState();
   std::vector<MCCFIInstruction> Instructions;
 
   for (int i = 0, n = Moves.size(); i != n; ++i) {



From jay.foad at gmail.com  Thu Jun 23 04:09:15 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 23 Jun 2011 09:09:15 -0000
Subject: [llvm-commits] [llvm] r133708 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/MC/ lib/Target/CppBackend/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
Message-ID: <20110623090916.87EFD2A6C12C@llvm.org>

Author: foad
Date: Thu Jun 23 04:09:15 2011
New Revision: 133708

URL: http://llvm.org/viewvc/llvm-project?rev=133708&view=rev
Log:
Reinstate r133513 (reverted in r133700) with an additional fix for a
-Wshorten-64-to-32 warning in Instructions.h.

Modified:
    llvm/trunk/include/llvm/BasicBlock.h
    llvm/trunk/include/llvm/Instructions.h
    llvm/trunk/include/llvm/Support/CFG.h
    llvm/trunk/include/llvm/Use.h
    llvm/trunk/lib/MC/MCAsmStreamer.cpp
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
    llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
    llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
    llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
    llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp
    llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
    llvm/trunk/lib/Transforms/Utils/Local.cpp
    llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
    llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
    llvm/trunk/lib/VMCore/BasicBlock.cpp
    llvm/trunk/lib/VMCore/Instructions.cpp
    llvm/trunk/lib/VMCore/User.cpp
    llvm/trunk/lib/VMCore/Value.cpp
    llvm/trunk/lib/VMCore/Verifier.cpp

Modified: llvm/trunk/include/llvm/BasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BasicBlock.h?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/include/llvm/BasicBlock.h (original)
+++ llvm/trunk/include/llvm/BasicBlock.h Thu Jun 23 04:09:15 2011
@@ -110,7 +110,7 @@
         Function *getParent()       { return Parent; }
 
   /// use_back - Specialize the methods defined in Value, as we know that an
-  /// BasicBlock can only be used by Users (specifically PHI nodes, terminators,
+  /// BasicBlock can only be used by Users (specifically terminators
   /// and BlockAddress's).
   User       *use_back()       { return cast<User>(*use_begin());}
   const User *use_back() const { return cast<User>(*use_begin());}
@@ -248,6 +248,10 @@
   /// other than direct branches, switches, etc. to it.
   bool hasAddressTaken() const { return getSubclassDataFromValue() != 0; }
 
+  /// replaceSuccessorsPhiUsesWith - Update all phi nodes in all our successors
+  /// to refer to basic block New instead of to us.
+  void replaceSuccessorsPhiUsesWith(BasicBlock *New);
+
 private:
   /// AdjustBlockAddressRefCount - BasicBlock stores the number of BlockAddress
   /// objects using it.  This is almost always 0, sometimes one, possibly but

Modified: llvm/trunk/include/llvm/Instructions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Instructions.h?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Instructions.h (original)
+++ llvm/trunk/include/llvm/Instructions.h Thu Jun 23 04:09:15 2011
@@ -1814,7 +1814,7 @@
   explicit PHINode(const Type *Ty, unsigned NumReservedValues,
                    const Twine &NameStr = "", Instruction *InsertBefore = 0)
     : Instruction(Ty, Instruction::PHI, 0, 0, InsertBefore),
-      ReservedSpace(NumReservedValues * 2) {
+      ReservedSpace(NumReservedValues) {
     setName(NameStr);
     OperandList = allocHungoffUses(ReservedSpace);
   }
@@ -1822,11 +1822,16 @@
   PHINode(const Type *Ty, unsigned NumReservedValues, const Twine &NameStr,
           BasicBlock *InsertAtEnd)
     : Instruction(Ty, Instruction::PHI, 0, 0, InsertAtEnd),
-      ReservedSpace(NumReservedValues * 2) {
+      ReservedSpace(NumReservedValues) {
     setName(NameStr);
     OperandList = allocHungoffUses(ReservedSpace);
   }
 protected:
+  // allocHungoffUses - this is more complicated than the generic
+  // User::allocHungoffUses, because we have to allocate Uses for the incoming
+  // values and pointers to the incoming blocks, all in one allocation.
+  Use *allocHungoffUses(unsigned) const;
+
   virtual PHINode *clone_impl() const;
 public:
   /// Constructors - NumReservedValues is a hint for the number of incoming
@@ -1845,32 +1850,55 @@
   /// Provide fast operand accessors
   DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value);
 
+  // Block iterator interface. This provides access to the list of incoming
+  // basic blocks, which parallels the list of incoming values.
+
+  typedef BasicBlock **block_iterator;
+  typedef BasicBlock * const *const_block_iterator;
+
+  block_iterator block_begin() {
+    Use::UserRef *ref =
+      reinterpret_cast<Use::UserRef*>(op_begin() + ReservedSpace);
+    return reinterpret_cast<block_iterator>(ref + 1);
+  }
+
+  const_block_iterator block_begin() const {
+    const Use::UserRef *ref =
+      reinterpret_cast<const Use::UserRef*>(op_begin() + ReservedSpace);
+    return reinterpret_cast<const_block_iterator>(ref + 1);
+  }
+
+  block_iterator block_end() {
+    return block_begin() + getNumOperands();
+  }
+
+  const_block_iterator block_end() const {
+    return block_begin() + getNumOperands();
+  }
+
   /// getNumIncomingValues - Return the number of incoming edges
   ///
-  unsigned getNumIncomingValues() const { return getNumOperands()/2; }
+  unsigned getNumIncomingValues() const { return getNumOperands(); }
 
   /// getIncomingValue - Return incoming value number x
   ///
   Value *getIncomingValue(unsigned i) const {
-    assert(i*2 < getNumOperands() && "Invalid value number!");
-    return getOperand(i*2);
+    return getOperand(i);
   }
   void setIncomingValue(unsigned i, Value *V) {
-    assert(i*2 < getNumOperands() && "Invalid value number!");
-    setOperand(i*2, V);
+    setOperand(i, V);
   }
   static unsigned getOperandNumForIncomingValue(unsigned i) {
-    return i*2;
+    return i;
   }
   static unsigned getIncomingValueNumForOperand(unsigned i) {
-    assert(i % 2 == 0 && "Invalid incoming-value operand index!");
-    return i/2;
+    return i;
   }
 
   /// getIncomingBlock - Return incoming basic block number @p i.
   ///
   BasicBlock *getIncomingBlock(unsigned i) const {
-    return cast<BasicBlock>(getOperand(i*2+1));
+    return block_begin()[i];
   }
 
   /// getIncomingBlock - Return incoming basic block corresponding
@@ -1878,7 +1906,7 @@
   ///
   BasicBlock *getIncomingBlock(const Use &U) const {
     assert(this == U.getUser() && "Iterator doesn't point to PHI's Uses?");
-    return cast<BasicBlock>((&U + 1)->get());
+    return getIncomingBlock(unsigned(&U - op_begin()));
   }
 
   /// getIncomingBlock - Return incoming basic block corresponding
@@ -1889,16 +1917,8 @@
     return getIncomingBlock(I.getUse());
   }
 
-
   void setIncomingBlock(unsigned i, BasicBlock *BB) {
-    setOperand(i*2+1, (Value*)BB);
-  }
-  static unsigned getOperandNumForIncomingBlock(unsigned i) {
-    return i*2+1;
-  }
-  static unsigned getIncomingBlockNumForOperand(unsigned i) {
-    assert(i % 2 == 1 && "Invalid incoming-block operand index!");
-    return i/2;
+    block_begin()[i] = BB;
   }
 
   /// addIncoming - Add an incoming value to the end of the PHI list
@@ -1908,13 +1928,12 @@
     assert(BB && "PHI node got a null basic block!");
     assert(getType() == V->getType() &&
            "All operands to PHI node must be the same type as the PHI node!");
-    unsigned OpNo = NumOperands;
-    if (OpNo+2 > ReservedSpace)
+    if (NumOperands == ReservedSpace)
       growOperands();  // Get more space!
     // Initialize some new operands.
-    NumOperands = OpNo+2;
-    OperandList[OpNo] = V;
-    OperandList[OpNo+1] = (Value*)BB;
+    ++NumOperands;
+    setIncomingValue(NumOperands - 1, V);
+    setIncomingBlock(NumOperands - 1, BB);
   }
 
   /// removeIncomingValue - Remove an incoming value.  This is useful if a
@@ -1937,14 +1956,16 @@
   /// block in the value list for this PHI.  Returns -1 if no instance.
   ///
   int getBasicBlockIndex(const BasicBlock *BB) const {
-    Use *OL = OperandList;
-    for (unsigned i = 0, e = getNumOperands(); i != e; i += 2)
-      if (OL[i+1].get() == (const Value*)BB) return i/2;
+    for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
+      if (block_begin()[i] == BB)
+        return i;
     return -1;
   }
 
   Value *getIncomingValueForBlock(const BasicBlock *BB) const {
-    return getIncomingValue(getBasicBlockIndex(BB));
+    int Idx = getBasicBlockIndex(BB);
+    assert(Idx >= 0 && "Invalid basic block argument!");
+    return getIncomingValue(Idx);
   }
 
   /// hasConstantValue - If the specified PHI node always merges together the

Modified: llvm/trunk/include/llvm/Support/CFG.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/CFG.h?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/CFG.h (original)
+++ llvm/trunk/include/llvm/Support/CFG.h Thu Jun 23 04:09:15 2011
@@ -33,7 +33,7 @@
   USE_iterator It;
 
   inline void advancePastNonTerminators() {
-    // Loop to ignore non terminator uses (for example PHI nodes).
+    // Loop to ignore non terminator uses (for example BlockAddresses).
     while (!It.atEnd() && !isa<TerminatorInst>(*It))
       ++It;
   }

Modified: llvm/trunk/include/llvm/Use.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Use.h?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Use.h (original)
+++ llvm/trunk/include/llvm/Use.h Thu Jun 23 04:09:15 2011
@@ -112,13 +112,16 @@
   Use *getNext() const { return Next; }
 
   
+  /// initTags - initialize the waymarking tags on an array of Uses, so that
+  /// getUser() can find the User from any of those Uses.
+  static Use *initTags(Use *Start, Use *Stop);
+
   /// zap - This is used to destroy Use operands when the number of operands of
   /// a User changes.
   static void zap(Use *Start, const Use *Stop, bool del = false);
 
 private:
   const Use* getImpliedUser() const;
-  static Use *initTags(Use *Start, Use *Stop);
   
   Value *Val;
   Use *Next;
@@ -140,7 +143,6 @@
   }
 
   friend class Value;
-  friend class User;
 };
 
 // simplify_type - Allow clients to treat uses just like values when using

Modified: llvm/trunk/lib/MC/MCAsmStreamer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCAsmStreamer.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCAsmStreamer.cpp (original)
+++ llvm/trunk/lib/MC/MCAsmStreamer.cpp Thu Jun 23 04:09:15 2011
@@ -1119,7 +1119,7 @@
     } else {
       // Otherwise, write out in binary.
       OS << "0b";
-      for (int j = 7; j >= 0; j--) {
+      for (unsigned j = 8; j--;) {
         unsigned Bit = (Code[i] >> j) & 1;
 
         unsigned FixupBit;
@@ -1128,9 +1128,9 @@
         else
           FixupBit = i * 8 + (7-j);
 
-        if (uint8_t FixupMapEntry = FixupMap[FixupBit]) {
-          //assert(Bit == 0 && "Encoder wrote into fixed up bit!");
-          OS << char('A' + FixupMapEntry - 1);
+        if (uint8_t MapEntry = FixupMap[FixupBit]) {
+          assert(Bit == 0 && "Encoder wrote into fixed up bit!");
+          OS << char('A' + MapEntry - 1);
         } else
           OS << Bit;
       }

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Thu Jun 23 04:09:15 2011
@@ -1356,7 +1356,7 @@
     for (unsigned i = 0; i < phi->getNumIncomingValues(); ++i) {
       Out << iName << "->addIncoming("
           << opNames[PHINode::getOperandNumForIncomingValue(i)] << ", "
-          << opNames[PHINode::getOperandNumForIncomingBlock(i)] << ");";
+          << getOpName(phi->getIncomingBlock(i)) << ");";
       nl(Out);
     }
     break;

Modified: llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/LoopUnswitch.cpp Thu Jun 23 04:09:15 2011
@@ -1021,6 +1021,10 @@
         while (PHINode *PN = dyn_cast<PHINode>(Succ->begin()))
           ReplaceUsesOfWith(PN, PN->getIncomingValue(0), Worklist, L, LPM);
         
+        // If Succ has any successors with PHI nodes, update them to have
+        // entries coming from Pred instead of Succ.
+        Succ->replaceAllUsesWith(Pred);
+        
         // Move all of the successor contents from Succ to Pred.
         Pred->getInstList().splice(BI, Succ->getInstList(), Succ->begin(),
                                    Succ->end());
@@ -1028,10 +1032,6 @@
         BI->eraseFromParent();
         RemoveFromWorklist(BI, Worklist);
         
-        // If Succ has any successors with PHI nodes, update them to have
-        // entries coming from Pred instead of Succ.
-        Succ->replaceAllUsesWith(Pred);
-        
         // Remove Succ from the loop tree.
         LI->removeBlock(Succ);
         LPM->deleteSimpleAnalysisValue(Succ, L);

Modified: llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BasicBlockUtils.cpp Thu Jun 23 04:09:15 2011
@@ -153,13 +153,13 @@
   // Delete the unconditional branch from the predecessor...
   PredBB->getInstList().pop_back();
   
-  // Move all definitions in the successor to the predecessor...
-  PredBB->getInstList().splice(PredBB->end(), BB->getInstList());
-  
   // Make all PHI nodes that referred to BB now refer to Pred as their
   // source...
   BB->replaceAllUsesWith(PredBB);
   
+  // Move all definitions in the successor to the predecessor...
+  PredBB->getInstList().splice(PredBB->end(), BB->getInstList());
+  
   // Inherit predecessors name if it exists.
   if (!PredBB->hasName())
     PredBB->takeName(BB);

Modified: llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/BreakCriticalEdges.cpp Thu Jun 23 04:09:15 2011
@@ -193,44 +193,22 @@
   
   // If there are any PHI nodes in DestBB, we need to update them so that they
   // merge incoming values from NewBB instead of from TIBB.
-  if (PHINode *APHI = dyn_cast<PHINode>(DestBB->begin())) {
-    // This conceptually does:
-    //  foreach (PHINode *PN in DestBB)
-    //    PN->setIncomingBlock(PN->getIncomingBlock(TIBB), NewBB);
-    // but is optimized for two cases.
-    
-    if (APHI->getNumIncomingValues() <= 8) {  // Small # preds case.
-      unsigned BBIdx = 0;
-      for (BasicBlock::iterator I = DestBB->begin(); isa<PHINode>(I); ++I) {
-        // We no longer enter through TIBB, now we come in through NewBB.
-        // Revector exactly one entry in the PHI node that used to come from
-        // TIBB to come from NewBB.
-        PHINode *PN = cast<PHINode>(I);
-        
-        // Reuse the previous value of BBIdx if it lines up.  In cases where we
-        // have multiple phi nodes with *lots* of predecessors, this is a speed
-        // win because we don't have to scan the PHI looking for TIBB.  This
-        // happens because the BB list of PHI nodes are usually in the same
-        // order.
-        if (PN->getIncomingBlock(BBIdx) != TIBB)
-          BBIdx = PN->getBasicBlockIndex(TIBB);
-        PN->setIncomingBlock(BBIdx, NewBB);
-      }
-    } else {
-      // However, the foreach loop is slow for blocks with lots of predecessors
-      // because PHINode::getIncomingBlock is O(n) in # preds.  Instead, walk
-      // the user list of TIBB to find the PHI nodes.
-      SmallPtrSet<PHINode*, 16> UpdatedPHIs;
-    
-      for (Value::use_iterator UI = TIBB->use_begin(), E = TIBB->use_end();
-           UI != E; ) {
-        Value::use_iterator Use = UI++;
-        if (PHINode *PN = dyn_cast<PHINode>(*Use)) {
-          // Remove one entry from each PHI.
-          if (PN->getParent() == DestBB && UpdatedPHIs.insert(PN))
-            PN->setOperand(Use.getOperandNo(), NewBB);
-        }
-      }
+  {
+    unsigned BBIdx = 0;
+    for (BasicBlock::iterator I = DestBB->begin(); isa<PHINode>(I); ++I) {
+      // We no longer enter through TIBB, now we come in through NewBB.
+      // Revector exactly one entry in the PHI node that used to come from
+      // TIBB to come from NewBB.
+      PHINode *PN = cast<PHINode>(I);
+
+      // Reuse the previous value of BBIdx if it lines up.  In cases where we
+      // have multiple phi nodes with *lots* of predecessors, this is a speed
+      // win because we don't have to scan the PHI looking for TIBB.  This
+      // happens because the BB list of PHI nodes are usually in the same
+      // order.
+      if (PN->getIncomingBlock(BBIdx) != TIBB)
+	BBIdx = PN->getBasicBlockIndex(TIBB);
+      PN->setIncomingBlock(BBIdx, NewBB);
     }
   }
    

Modified: llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/CloneFunction.cpp Thu Jun 23 04:09:15 2011
@@ -572,12 +572,12 @@
     // removed, so we just need to splice the blocks.
     BI->eraseFromParent();
     
-    // Move all the instructions in the succ to the pred.
-    I->getInstList().splice(I->end(), Dest->getInstList());
-    
     // Make all PHI nodes that referred to Dest now refer to I as their source.
     Dest->replaceAllUsesWith(I);
 
+    // Move all the instructions in the succ to the pred.
+    I->getInstList().splice(I->end(), Dest->getInstList());
+    
     // Remove the dest block.
     Dest->eraseFromParent();
     

Modified: llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/InlineFunction.cpp Thu Jun 23 04:09:15 2011
@@ -1097,15 +1097,15 @@
         TheCall->replaceAllUsesWith(Returns[0]->getReturnValue());
     }
 
+    // Update PHI nodes that use the ReturnBB to use the AfterCallBB.
+    BasicBlock *ReturnBB = Returns[0]->getParent();
+    ReturnBB->replaceAllUsesWith(AfterCallBB);
+
     // Splice the code from the return block into the block that it will return
     // to, which contains the code that was after the call.
-    BasicBlock *ReturnBB = Returns[0]->getParent();
     AfterCallBB->getInstList().splice(AfterCallBB->begin(),
                                       ReturnBB->getInstList());
 
-    // Update PHI nodes that use the ReturnBB to use the AfterCallBB.
-    ReturnBB->replaceAllUsesWith(AfterCallBB);
-
     // Delete the return instruction now and empty ReturnBB now.
     Returns[0]->eraseFromParent();
     ReturnBB->eraseFromParent();
@@ -1125,8 +1125,8 @@
 
   // Splice the code entry block into calling block, right before the
   // unconditional branch.
-  OrigBB->getInstList().splice(Br, CalleeEntry->getInstList());
   CalleeEntry->replaceAllUsesWith(OrigBB);  // Update PHI nodes
+  OrigBB->getInstList().splice(Br, CalleeEntry->getInstList());
 
   // Remove the unconditional branch.
   OrigBB->getInstList().erase(Br);

Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/Local.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/Local.cpp Thu Jun 23 04:09:15 2011
@@ -427,10 +427,6 @@
   BasicBlock *PredBB = DestBB->getSinglePredecessor();
   assert(PredBB && "Block doesn't have a single predecessor!");
   
-  // Splice all the instructions from PredBB to DestBB.
-  PredBB->getTerminator()->eraseFromParent();
-  DestBB->getInstList().splice(DestBB->begin(), PredBB->getInstList());
-
   // Zap anything that took the address of DestBB.  Not doing this will give the
   // address an invalid value.
   if (DestBB->hasAddressTaken()) {
@@ -445,6 +441,10 @@
   // Anything that branched to PredBB now branches to DestBB.
   PredBB->replaceAllUsesWith(DestBB);
   
+  // Splice all the instructions from PredBB to DestBB.
+  PredBB->getTerminator()->eraseFromParent();
+  DestBB->getInstList().splice(DestBB->begin(), PredBB->getInstList());
+
   if (P) {
     DominatorTree *DT = P->getAnalysisIfAvailable<DominatorTree>();
     if (DT) {
@@ -660,12 +660,17 @@
     // them, which helps expose duplicates, but we have to check all the
     // operands to be safe in case instcombine hasn't run.
     uintptr_t Hash = 0;
+    // This hash algorithm is quite weak as hash functions go, but it seems
+    // to do a good enough job for this particular purpose, and is very quick.
     for (User::op_iterator I = PN->op_begin(), E = PN->op_end(); I != E; ++I) {
-      // This hash algorithm is quite weak as hash functions go, but it seems
-      // to do a good enough job for this particular purpose, and is very quick.
       Hash ^= reinterpret_cast<uintptr_t>(static_cast<Value *>(*I));
       Hash = (Hash << 7) | (Hash >> (sizeof(uintptr_t) * CHAR_BIT - 7));
     }
+    for (PHINode::block_iterator I = PN->block_begin(), E = PN->block_end();
+         I != E; ++I) {
+      Hash ^= reinterpret_cast<uintptr_t>(static_cast<BasicBlock *>(*I));
+      Hash = (Hash << 7) | (Hash >> (sizeof(uintptr_t) * CHAR_BIT - 7));
+    }
     // Avoid colliding with the DenseMap sentinels ~0 and ~0-1.
     Hash >>= 1;
     // If we've never seen this hash value before, it's a unique PHI.

Modified: llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/LoopUnroll.cpp Thu Jun 23 04:09:15 2011
@@ -47,6 +47,14 @@
     if (It != VMap.end())
       I->setOperand(op, It->second);
   }
+
+  if (PHINode *PN = dyn_cast<PHINode>(I)) {
+    for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
+      ValueToValueMapTy::iterator It = VMap.find(PN->getIncomingBlock(i));
+      if (It != VMap.end())
+        PN->setIncomingBlock(i, cast<BasicBlock>(It->second));
+    }
+  }
 }
 
 /// FoldBlockIntoPredecessor - Folds a basic block into its predecessor if it
@@ -75,13 +83,13 @@
   // Delete the unconditional branch from the predecessor...
   OnlyPred->getInstList().pop_back();
 
-  // Move all definitions in the successor to the predecessor...
-  OnlyPred->getInstList().splice(OnlyPred->end(), BB->getInstList());
-
   // Make all PHI nodes that referred to BB now refer to Pred as their
   // source...
   BB->replaceAllUsesWith(OnlyPred);
 
+  // Move all definitions in the successor to the predecessor...
+  OnlyPred->getInstList().splice(OnlyPred->end(), BB->getInstList());
+
   std::string OldName = BB->getName();
 
   // Erase basic block from the function...
@@ -121,14 +129,14 @@
 
   BasicBlock *Header = L->getHeader();
   BranchInst *BI = dyn_cast<BranchInst>(LatchBlock->getTerminator());
-
+  
   if (!BI || BI->isUnconditional()) {
     // The loop-rotate pass can be helpful to avoid this in many cases.
     DEBUG(dbgs() <<
              "  Can't unroll; loop not terminated by a conditional branch.\n");
     return false;
   }
-
+  
   if (Header->hasAddressTaken()) {
     // The loop-rotate pass can be helpful to avoid this in many cases.
     DEBUG(dbgs() <<
@@ -202,7 +210,7 @@
   for (BasicBlock::iterator I = Header->begin(); isa<PHINode>(I); ++I) {
     PHINode *PN = cast<PHINode>(I);
     OrigPHINode.push_back(PN);
-    if (Instruction *I =
+    if (Instruction *I = 
                 dyn_cast<Instruction>(PN->getIncomingValueForBlock(LatchBlock)))
       if (L->contains(I))
         LastValueMap[I] = I;
@@ -215,7 +223,7 @@
 
   for (unsigned It = 1; It != Count; ++It) {
     std::vector<BasicBlock*> NewBlocks;
-
+    
     for (std::vector<BasicBlock*>::iterator BB = LoopBlocks.begin(),
          E = LoopBlocks.end(); BB != E; ++BB) {
       ValueToValueMapTy VMap;
@@ -247,16 +255,14 @@
       // the successor of the latch block.  The successor of the exit block will
       // be updated specially after unrolling all the way.
       if (*BB != LatchBlock)
-        for (Value::use_iterator UI = (*BB)->use_begin(), UE = (*BB)->use_end();
-             UI != UE;) {
-          Instruction *UseInst = cast<Instruction>(*UI);
-          ++UI;
-          if (isa<PHINode>(UseInst) && !L->contains(UseInst)) {
-            PHINode *phi = cast<PHINode>(UseInst);
-            Value *Incoming = phi->getIncomingValueForBlock(*BB);
-            phi->addIncoming(Incoming, New);
-          }
-        }
+        for (succ_iterator SI = succ_begin(*BB), SE = succ_end(*BB); SI != SE;
+             ++SI)
+          if (!L->contains(*SI))
+            for (BasicBlock::iterator BBI = (*SI)->begin();
+                 PHINode *phi = dyn_cast<PHINode>(BBI); ++BBI) {
+              Value *Incoming = phi->getIncomingValueForBlock(*BB);
+              phi->addIncoming(Incoming, New);
+            }
 
       // Keep track of new headers and latches as we create them, so that
       // we can insert the proper branches later.
@@ -276,36 +282,32 @@
 
       NewBlocks.push_back(New);
     }
-
+    
     // Remap all instructions in the most recent iteration
     for (unsigned i = 0; i < NewBlocks.size(); ++i)
       for (BasicBlock::iterator I = NewBlocks[i]->begin(),
            E = NewBlocks[i]->end(); I != E; ++I)
         ::RemapInstruction(I, LastValueMap);
   }
-
+  
   // The latch block exits the loop.  If there are any PHI nodes in the
   // successor blocks, update them to use the appropriate values computed as the
   // last iteration of the loop.
   if (Count != 1) {
-    SmallPtrSet<PHINode*, 8> Users;
-    for (Value::use_iterator UI = LatchBlock->use_begin(),
-         UE = LatchBlock->use_end(); UI != UE; ++UI)
-      if (PHINode *phi = dyn_cast<PHINode>(*UI))
-        Users.insert(phi);
-
     BasicBlock *LastIterationBB = cast<BasicBlock>(LastValueMap[LatchBlock]);
-    for (SmallPtrSet<PHINode*,8>::iterator SI = Users.begin(), SE = Users.end();
+    for (succ_iterator SI = succ_begin(LatchBlock), SE = succ_end(LatchBlock);
          SI != SE; ++SI) {
-      PHINode *PN = *SI;
-      Value *InVal = PN->removeIncomingValue(LatchBlock, false);
-      // If this value was defined in the loop, take the value defined by the
-      // last iteration of the loop.
-      if (Instruction *InValI = dyn_cast<Instruction>(InVal)) {
-        if (L->contains(InValI))
-          InVal = LastValueMap[InVal];
+      for (BasicBlock::iterator BBI = (*SI)->begin();
+           PHINode *PN = dyn_cast<PHINode>(BBI); ++BBI) {
+        Value *InVal = PN->removeIncomingValue(LatchBlock, false);
+        // If this value was defined in the loop, take the value defined by the
+        // last iteration of the loop.
+        if (Instruction *InValI = dyn_cast<Instruction>(InVal)) {
+          if (L->contains(InValI))
+            InVal = LastValueMap[InVal];
+        }
+        PN->addIncoming(InVal, LastIterationBB);
       }
-      PN->addIncoming(InVal, LastIterationBB);
     }
   }
 
@@ -352,14 +354,19 @@
       // Replace the conditional branch with an unconditional one.
       BranchInst::Create(Dest, Term);
       Term->eraseFromParent();
-      // Merge adjacent basic blocks, if possible.
-      if (BasicBlock *Fold = FoldBlockIntoPredecessor(Dest, LI)) {
-        std::replace(Latches.begin(), Latches.end(), Dest, Fold);
-        std::replace(Headers.begin(), Headers.end(), Dest, Fold);
-      }
     }
   }
 
+  // Merge adjacent basic blocks, if possible.
+  for (unsigned i = 0, e = Latches.size(); i != e; ++i) {
+    BranchInst *Term = cast<BranchInst>(Latches[i]->getTerminator());
+    if (Term->isUnconditional()) {
+      BasicBlock *Dest = Term->getSuccessor(0);
+      if (BasicBlock *Fold = FoldBlockIntoPredecessor(Dest, LI))
+        std::replace(Latches.begin(), Latches.end(), Dest, Fold);
+    }
+  }
+  
   // At this point, the code is well formed.  We now do a quick sweep over the
   // inserted code, doing constant propagation and dead code elimination as we
   // go.

Modified: llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/ValueMapper.cpp Thu Jun 23 04:09:15 2011
@@ -16,6 +16,7 @@
 #include "llvm/Type.h"
 #include "llvm/Constants.h"
 #include "llvm/Function.h"
+#include "llvm/Instructions.h"
 #include "llvm/Metadata.h"
 #include "llvm/ADT/SmallVector.h"
 using namespace llvm;
@@ -128,6 +129,19 @@
              "Referenced value not in value map!");
   }
 
+  // Remap phi nodes' incoming blocks.
+  if (PHINode *PN = dyn_cast<PHINode>(I)) {
+    for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
+      Value *V = MapValue(PN->getIncomingBlock(i), VMap, Flags);
+      // If we aren't ignoring missing entries, assert that something happened.
+      if (V != 0)
+        PN->setIncomingBlock(i, cast<BasicBlock>(V));
+      else
+        assert((Flags & RF_IgnoreMissingEntries) &&
+               "Referenced block not in value map!");
+    }
+  }
+
   // Remap attached metadata.
   SmallVector<std::pair<unsigned, MDNode *>, 4> MDs;
   I->getAllMetadata(MDs);

Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/BasicBlock.cpp (original)
+++ llvm/trunk/lib/VMCore/BasicBlock.cpp Thu Jun 23 04:09:15 2011
@@ -308,3 +308,19 @@
   return New;
 }
 
+void BasicBlock::replaceSuccessorsPhiUsesWith(BasicBlock *New) {
+  TerminatorInst *TI = getTerminator();
+  if (!TI)
+    // Cope with being called on a BasicBlock that doesn't have a terminator
+    // yet. Clang's CodeGenFunction::EmitReturnBlock() likes to do this.
+    return;
+  for (unsigned i = 0, e = TI->getNumSuccessors(); i != e; ++i) {
+    BasicBlock *Succ = TI->getSuccessor(i);
+    for (iterator II = Succ->begin(); PHINode *PN = dyn_cast<PHINode>(II);
+         ++II) {
+      int i;
+      while ((i = PN->getBasicBlockIndex(this)) >= 0)
+        PN->setIncomingBlock(i, New);
+    }
+  }
+}

Modified: llvm/trunk/lib/VMCore/Instructions.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Instructions.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Instructions.cpp (original)
+++ llvm/trunk/lib/VMCore/Instructions.cpp Thu Jun 23 04:09:15 2011
@@ -87,11 +87,8 @@
   : Instruction(PN.getType(), Instruction::PHI,
                 allocHungoffUses(PN.getNumOperands()), PN.getNumOperands()),
     ReservedSpace(PN.getNumOperands()) {
-  Use *OL = OperandList;
-  for (unsigned i = 0, e = PN.getNumOperands(); i != e; i+=2) {
-    OL[i] = PN.getOperand(i);
-    OL[i+1] = PN.getOperand(i+1);
-  }
+  std::copy(PN.op_begin(), PN.op_end(), op_begin());
+  std::copy(PN.block_begin(), PN.block_end(), block_begin());
   SubclassOptionalData = PN.SubclassOptionalData;
 }
 
@@ -99,31 +96,37 @@
   dropHungoffUses();
 }
 
+Use *PHINode::allocHungoffUses(unsigned N) const {
+  // Allocate the array of Uses of the incoming values, followed by a pointer
+  // (with bottom bit set) to the User, followed by the array of pointers to
+  // the incoming basic blocks.
+  size_t size = N * sizeof(Use) + sizeof(Use::UserRef)
+    + N * sizeof(BasicBlock*);
+  Use *Begin = static_cast<Use*>(::operator new(size));
+  Use *End = Begin + N;
+  (void) new(End) Use::UserRef(const_cast<PHINode*>(this), 1);
+  return Use::initTags(Begin, End);
+}
+
 // removeIncomingValue - Remove an incoming value.  This is useful if a
 // predecessor basic block is deleted.
 Value *PHINode::removeIncomingValue(unsigned Idx, bool DeletePHIIfEmpty) {
-  unsigned NumOps = getNumOperands();
-  Use *OL = OperandList;
-  assert(Idx*2 < NumOps && "BB not in PHI node!");
-  Value *Removed = OL[Idx*2];
+  Value *Removed = getIncomingValue(Idx);
 
   // Move everything after this operand down.
   //
   // FIXME: we could just swap with the end of the list, then erase.  However,
-  // client might not expect this to happen.  The code as it is thrashes the
+  // clients might not expect this to happen.  The code as it is thrashes the
   // use/def lists, which is kinda lame.
-  for (unsigned i = (Idx+1)*2; i != NumOps; i += 2) {
-    OL[i-2] = OL[i];
-    OL[i-2+1] = OL[i+1];
-  }
+  std::copy(op_begin() + Idx + 1, op_end(), op_begin() + Idx);
+  std::copy(block_begin() + Idx + 1, block_end(), block_begin() + Idx);
 
   // Nuke the last value.
-  OL[NumOps-2].set(0);
-  OL[NumOps-2+1].set(0);
-  NumOperands = NumOps-2;
+  Op<-1>().set(0);
+  --NumOperands;
 
   // If the PHI node is dead, because it has zero entries, nuke it now.
-  if (NumOps == 2 && DeletePHIIfEmpty) {
+  if (getNumOperands() == 0 && DeletePHIIfEmpty) {
     // If anyone is using this PHI, make them use a dummy value instead...
     replaceAllUsesWith(UndefValue::get(getType()));
     eraseFromParent();
@@ -137,15 +140,18 @@
 ///
 void PHINode::growOperands() {
   unsigned e = getNumOperands();
-  // Multiply by 1.5 and round down so the result is still even.
-  unsigned NumOps = e + e / 4 * 2;
-  if (NumOps < 4) NumOps = 4;      // 4 op PHI nodes are VERY common.
+  unsigned NumOps = e + e / 2;
+  if (NumOps < 2) NumOps = 2;      // 2 op PHI nodes are VERY common.
+
+  Use *OldOps = op_begin();
+  BasicBlock **OldBlocks = block_begin();
 
   ReservedSpace = NumOps;
-  Use *OldOps = OperandList;
-  Use *NewOps = allocHungoffUses(NumOps);
-  std::copy(OldOps, OldOps + e, NewOps);
-  OperandList = NewOps;
+  OperandList = allocHungoffUses(ReservedSpace);
+
+  std::copy(OldOps, OldOps + e, op_begin());
+  std::copy(OldBlocks, OldBlocks + e, block_begin());
+
   Use::zap(OldOps, OldOps + e, true);
 }
 

Modified: llvm/trunk/lib/VMCore/User.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/User.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/User.cpp (original)
+++ llvm/trunk/lib/VMCore/User.cpp Thu Jun 23 04:09:15 2011
@@ -40,8 +40,10 @@
 //===----------------------------------------------------------------------===//
 
 Use *User::allocHungoffUses(unsigned N) const {
-  Use *Begin = static_cast<Use*>(::operator new(sizeof(Use) * N
-                                                + sizeof(Use::UserRef)));
+  // Allocate the array of Uses, followed by a pointer (with bottom bit set) to
+  // the User.
+  size_t size = N * sizeof(Use) + sizeof(Use::UserRef);
+  Use *Begin = static_cast<Use*>(::operator new(size));
   Use *End = Begin + N;
   (void) new(End) Use::UserRef(const_cast<User*>(this), 1);
   return Use::initTags(Begin, End);

Modified: llvm/trunk/lib/VMCore/Value.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Value.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Value.cpp (original)
+++ llvm/trunk/lib/VMCore/Value.cpp Thu Jun 23 04:09:15 2011
@@ -305,6 +305,9 @@
 
     U.set(New);
   }
+
+  if (BasicBlock *BB = dyn_cast<BasicBlock>(this))
+    BB->replaceSuccessorsPhiUsesWith(cast<BasicBlock>(New));
 }
 
 void Value::replaceAllUsesWith(Value *New) {

Modified: llvm/trunk/lib/VMCore/Verifier.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Verifier.cpp?rev=133708&r1=133707&r2=133708&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/Verifier.cpp (original)
+++ llvm/trunk/lib/VMCore/Verifier.cpp Thu Jun 23 04:09:15 2011
@@ -1139,9 +1139,6 @@
   for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
     Assert1(PN.getType() == PN.getIncomingValue(i)->getType(),
             "PHI node operands are not the same type as the result!", &PN);
-    Assert1(isa<BasicBlock>(PN.getOperand(
-                PHINode::getOperandNumForIncomingBlock(i))),
-            "PHI node incoming block is not a BasicBlock!", &PN);
   }
 
   // All other PHI node constraints are checked in the visitBasicBlock method.



From jay.foad at gmail.com  Thu Jun 23 04:17:57 2011
From: jay.foad at gmail.com (Jay Foad)
Date: Thu, 23 Jun 2011 10:17:57 +0100
Subject: [llvm-commits] [llvm] r133513 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/Target/CppBackend/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
In-Reply-To: <184C58B8-49B3-40A8-A0EF-7718C77C9FB7@apple.com>
References: <20110621103319.B0D332A6C12C@llvm.org>
	<5AAC95DA-F372-4AC4-BF66-AF474C061E34@apple.com>
	<184C58B8-49B3-40A8-A0EF-7718C77C9FB7@apple.com>
Message-ID: <BANLkTi=f+tVOvb8kFC5WsHvuYwdT9g4rntcDO+79i6p6tihMzQ@mail.gmail.com>

On 23 June 2011 07:31, Eric Christopher <echristo at apple.com> wrote:
>
> On Jun 22, 2011, at 11:24 AM, Eric Christopher wrote:
>
>>
>> On Jun 21, 2011, at 3:33 AM, Jay Foad wrote:
>>
>>> Author: foad
>>> Date: Tue Jun 21 05:33:19 2011
>>> New Revision: 133513
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=133513&view=rev
>>> Log:
>>> Reinstate r133435 and r133449 (reverted in r133499) now that the clang
>>> self-hosted build failure has been fixed (r133512).
>>>
>>
>> This is causing some additional warnings:
>>
>> /Developer/usr/local/include/llvm/Instructions.h: In member function 'llvm::BasicBlock* llvm::PHINode::getIncomingBlock(const llvm::Use&) const':
>> /Developer/usr/local/include/llvm/Instructions.h:1909: warning: implicit conversion shortens 64-bit value into a 32-bit value

I've fixed this one...

>> To duplicate just turn on conversion warnings, in particular with llvm-gcc -Wshorten-64-to-32, in a file that includes Instructions.h.

(I can't tell if there are any others, because if I build with clang
-Wshorten-64-to-32 I get loads of unrelated warnings)

> I've gone ahead and reverted your patch in r133700 for the time being, should be an easy reapply after you fix the new header warnings :)

... and re-reinstated my patch in r133708.

Thanks,
Jay.

From nobled at dreamwidth.org  Thu Jun 23 07:11:37 2011
From: nobled at dreamwidth.org (Dylan Noblesmith)
Date: Thu, 23 Jun 2011 12:11:37 -0000
Subject: [llvm-commits] [llvm] r133709 -
	/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
Message-ID: <20110623121137.45EC52A6C12C@llvm.org>

Author: nobled
Date: Thu Jun 23 07:11:37 2011
New Revision: 133709

URL: http://llvm.org/viewvc/llvm-project?rev=133709&view=rev
Log:
CppBackend: fixup for api change

This broke after r133364.


Modified:
    llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp

Modified: llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp?rev=133709&r1=133708&r2=133709&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp (original)
+++ llvm/trunk/lib/Target/CppBackend/CPPBackend.cpp Thu Jun 23 07:11:37 2011
@@ -586,7 +586,6 @@
       nl(Out);
     }
     Out << "StructType* " << typeName << " = StructType::get("
-        << "mod->getContext(), "
         << typeName << "_fields, /*isPacked=*/"
         << (ST->isPacked() ? "true" : "false") << ");";
     nl(Out);



From nobled at dreamwidth.org  Thu Jun 23 07:21:34 2011
From: nobled at dreamwidth.org (Dylan Noblesmith)
Date: Thu, 23 Jun 2011 12:21:34 -0000
Subject: [llvm-commits] [llvm] r133711 - in /llvm/trunk:
 cmake/config-ix.cmake include/llvm/Config/config.h.cmake
Message-ID: <20110623122134.22CC12A6C12C@llvm.org>

Author: nobled
Date: Thu Jun 23 07:21:33 2011
New Revision: 133711

URL: http://llvm.org/viewvc/llvm-project?rev=133711&view=rev
Log:
remove CMake mode_t define

It's now replaced with a simple ifdef _MSC_VER in the one
place it's needed (clang's FileManager.h header).


Modified:
    llvm/trunk/cmake/config-ix.cmake
    llvm/trunk/include/llvm/Config/config.h.cmake

Modified: llvm/trunk/cmake/config-ix.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/config-ix.cmake?rev=133711&r1=133710&r2=133711&view=diff
==============================================================================
--- llvm/trunk/cmake/config-ix.cmake (original)
+++ llvm/trunk/cmake/config-ix.cmake Thu Jun 23 07:21:33 2011
@@ -349,7 +349,6 @@
 
 if( MSVC )
   set(error_t int)
-  set(mode_t "unsigned short")
   set(LTDL_SHLIBPATH_VAR "PATH")
   set(LTDL_SYSSEARCHPATH "")
   set(LTDL_DLOPEN_DEPLIBS 1)

Modified: llvm/trunk/include/llvm/Config/config.h.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Config/config.h.cmake?rev=133711&r1=133710&r2=133711&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Config/config.h.cmake (original)
+++ llvm/trunk/include/llvm/Config/config.h.cmake Thu Jun 23 07:21:33 2011
@@ -686,9 +686,6 @@
    `char[]'. */
 #undef YYTEXT_POINTER
 
-/* Define to a type to use for `mode_t' if it is not otherwise available. */
-#cmakedefine mode_t ${mode_t}
-
 /* Define to a function replacing strtoll */
 #cmakedefine strtoll ${strtoll}
 



From nobled at dreamwidth.org  Thu Jun 23 07:34:31 2011
From: nobled at dreamwidth.org (Dylan Noblesmith)
Date: Thu, 23 Jun 2011 12:34:31 -0000
Subject: [llvm-commits] [llvm] r133712 - in
	/llvm/trunk/include/llvm/Support: Endian.h system_error.h
Message-ID: <20110623123431.C49C42A6C12C@llvm.org>

Author: nobled
Date: Thu Jun 23 07:34:31 2011
New Revision: 133712

URL: http://llvm.org/viewvc/llvm-project?rev=133712&view=rev
Log:
Don't include config.h in public headers

Replace it with llvm-config.h, which defines a subset of
config.h's macros "so that they can be in exported headers 
and won't override package specific directives", e.g.,
PACKAGE_NAME.

Endian.h wasn't using any macros at all though, so just delete
the include there instead.

Modified:
    llvm/trunk/include/llvm/Support/Endian.h
    llvm/trunk/include/llvm/Support/system_error.h

Modified: llvm/trunk/include/llvm/Support/Endian.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/Endian.h?rev=133712&r1=133711&r2=133712&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/Endian.h (original)
+++ llvm/trunk/include/llvm/Support/Endian.h Thu Jun 23 07:34:31 2011
@@ -14,7 +14,6 @@
 #ifndef LLVM_SUPPORT_ENDIAN_H
 #define LLVM_SUPPORT_ENDIAN_H
 
-#include "llvm/Config/config.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Support/SwapByteOrder.h"
 #include "llvm/Support/type_traits.h"

Modified: llvm/trunk/include/llvm/Support/system_error.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/system_error.h?rev=133712&r1=133711&r2=133712&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/system_error.h (original)
+++ llvm/trunk/include/llvm/Support/system_error.h Thu Jun 23 07:34:31 2011
@@ -222,7 +222,7 @@
 
 */
 
-#include "llvm/Config/config.h"
+#include "llvm/Config/llvm-config.h"
 #include "llvm/Support/type_traits.h"
 #include <cerrno>
 #include <string>



From nobled at dreamwidth.org  Thu Jun 23 07:45:54 2011
From: nobled at dreamwidth.org (Dylan Noblesmith)
Date: Thu, 23 Jun 2011 12:45:54 -0000
Subject: [llvm-commits] [llvm] r133713 - in /llvm/trunk:
 include/llvm/Support/FEnv.h lib/Analysis/ConstantFolding.cpp
 lib/Analysis/FEnv.h
Message-ID: <20110623124554.7EFA12A6C12C@llvm.org>

Author: nobled
Date: Thu Jun 23 07:45:54 2011
New Revision: 133713

URL: http://llvm.org/viewvc/llvm-project?rev=133713&view=rev
Log:
Support: make floating-exception header private

It has only one user. This eliminates the last include of
config.h from the public headers -- ideally, config.h
shouldn't even be installed by `make install` anymore.


Added:
    llvm/trunk/lib/Analysis/FEnv.h
      - copied, changed from r133709, llvm/trunk/include/llvm/Support/FEnv.h
Removed:
    llvm/trunk/include/llvm/Support/FEnv.h
Modified:
    llvm/trunk/lib/Analysis/ConstantFolding.cpp

Removed: llvm/trunk/include/llvm/Support/FEnv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/FEnv.h?rev=133712&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Support/FEnv.h (original)
+++ llvm/trunk/include/llvm/Support/FEnv.h (removed)
@@ -1,56 +0,0 @@
-//===- llvm/Support/FEnv.h - Host floating-point exceptions ------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides an operating system independent interface to
-// floating-point exception interfaces.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_SYSTEM_FENV_H
-#define LLVM_SYSTEM_FENV_H
-
-#include "llvm/Config/config.h"
-#include <cerrno>
-#ifdef HAVE_FENV_H
-#include <fenv.h>
-#endif
-
-// FIXME: Clang's #include handling apparently doesn't work for libstdc++'s
-// fenv.h; see PR6907 for details.
-#if defined(__clang__) && defined(_GLIBCXX_FENV_H)
-#undef HAVE_FENV_H
-#endif
-
-namespace llvm {
-namespace sys {
-
-/// llvm_fenv_clearexcept - Clear the floating-point exception state.
-static inline void llvm_fenv_clearexcept() {
-#ifdef HAVE_FENV_H
-  feclearexcept(FE_ALL_EXCEPT);
-#endif
-  errno = 0;
-}
-
-/// llvm_fenv_testexcept - Test if a floating-point exception was raised.
-static inline bool llvm_fenv_testexcept() {
-  int errno_val = errno;
-  if (errno_val == ERANGE || errno_val == EDOM)
-    return true;
-#ifdef HAVE_FENV_H
-  if (fetestexcept(FE_ALL_EXCEPT & ~FE_INEXACT))
-    return true;
-#endif
-  return false;
-}
-
-} // End sys namespace
-} // End llvm namespace
-
-#endif

Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=133713&r1=133712&r2=133713&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)
+++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Thu Jun 23 07:45:54 2011
@@ -31,9 +31,10 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/GetElementPtrTypeIterator.h"
 #include "llvm/Support/MathExtras.h"
-#include "llvm/Support/FEnv.h"
 #include <cerrno>
 #include <cmath>
+
+#include "FEnv.h"
 using namespace llvm;
 
 //===----------------------------------------------------------------------===//

Copied: llvm/trunk/lib/Analysis/FEnv.h (from r133709, llvm/trunk/include/llvm/Support/FEnv.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/FEnv.h?p2=llvm/trunk/lib/Analysis/FEnv.h&p1=llvm/trunk/include/llvm/Support/FEnv.h&r1=133709&r2=133713&rev=133713&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/FEnv.h (original)
+++ llvm/trunk/lib/Analysis/FEnv.h Thu Jun 23 07:45:54 2011
@@ -1,4 +1,4 @@
-//===- llvm/Support/FEnv.h - Host floating-point exceptions ------*- C++ -*-===//
+//===- FEnv.h - Host floating-point exceptions ------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //



From rafael.espindola at gmail.com  Thu Jun 23 08:37:38 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 23 Jun 2011 13:37:38 -0000
Subject: [llvm-commits] [llvm] r133714 - in /llvm/trunk/lib/Analysis:
	ConstantFolding.cpp FEnv.h
Message-ID: <20110623133738.492242A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 23 08:37:38 2011
New Revision: 133714

URL: http://llvm.org/viewvc/llvm-project?rev=133714&view=rev
Log:
133713 broke the build, revert it.

Removed:
    llvm/trunk/lib/Analysis/FEnv.h
Modified:
    llvm/trunk/lib/Analysis/ConstantFolding.cpp

Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=133714&r1=133713&r2=133714&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)
+++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Thu Jun 23 08:37:38 2011
@@ -31,10 +31,9 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/GetElementPtrTypeIterator.h"
 #include "llvm/Support/MathExtras.h"
+#include "llvm/Support/FEnv.h"
 #include <cerrno>
 #include <cmath>
-
-#include "FEnv.h"
 using namespace llvm;
 
 //===----------------------------------------------------------------------===//

Removed: llvm/trunk/lib/Analysis/FEnv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/FEnv.h?rev=133713&view=auto
==============================================================================
--- llvm/trunk/lib/Analysis/FEnv.h (original)
+++ llvm/trunk/lib/Analysis/FEnv.h (removed)
@@ -1,56 +0,0 @@
-//===- FEnv.h - Host floating-point exceptions ------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides an operating system independent interface to
-// floating-point exception interfaces.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_SYSTEM_FENV_H
-#define LLVM_SYSTEM_FENV_H
-
-#include "llvm/Config/config.h"
-#include <cerrno>
-#ifdef HAVE_FENV_H
-#include <fenv.h>
-#endif
-
-// FIXME: Clang's #include handling apparently doesn't work for libstdc++'s
-// fenv.h; see PR6907 for details.
-#if defined(__clang__) && defined(_GLIBCXX_FENV_H)
-#undef HAVE_FENV_H
-#endif
-
-namespace llvm {
-namespace sys {
-
-/// llvm_fenv_clearexcept - Clear the floating-point exception state.
-static inline void llvm_fenv_clearexcept() {
-#ifdef HAVE_FENV_H
-  feclearexcept(FE_ALL_EXCEPT);
-#endif
-  errno = 0;
-}
-
-/// llvm_fenv_testexcept - Test if a floating-point exception was raised.
-static inline bool llvm_fenv_testexcept() {
-  int errno_val = errno;
-  if (errno_val == ERANGE || errno_val == EDOM)
-    return true;
-#ifdef HAVE_FENV_H
-  if (fetestexcept(FE_ALL_EXCEPT & ~FE_INEXACT))
-    return true;
-#endif
-  return false;
-}
-
-} // End sys namespace
-} // End llvm namespace
-
-#endif



From justin.holewinski at gmail.com  Thu Jun 23 09:01:37 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Thu, 23 Jun 2011 10:01:37 -0400
Subject: [llvm-commits] [llvm] r133714 - in /llvm/trunk/lib/Analysis:
	ConstantFolding.cpp FEnv.h
In-Reply-To: <20110623133738.492242A6C12C@llvm.org>
References: <20110623133738.492242A6C12C@llvm.org>
Message-ID: <D178C902-E059-49BC-827E-A2670A0CFC69@gmail.com>

I'm still getting build errors:

/Volumes/Data/projects/llvm-work/lib/Analysis/ConstantFolding.cpp:34:10: fatal error: 'llvm/Support/FEnv.h' file not found
#include "llvm/Support/FEnv.h"

On Jun 23, 2011, at 9:37 AM, Rafael Espindola wrote:

> Author: rafael
> Date: Thu Jun 23 08:37:38 2011
> New Revision: 133714
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133714&view=rev
> Log:
> 133713 broke the build, revert it.
> 
> Removed:
>    llvm/trunk/lib/Analysis/FEnv.h
> Modified:
>    llvm/trunk/lib/Analysis/ConstantFolding.cpp
> 
> Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=133714&r1=133713&r2=133714&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)
> +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Thu Jun 23 08:37:38 2011
> @@ -31,10 +31,9 @@
> #include "llvm/Support/ErrorHandling.h"
> #include "llvm/Support/GetElementPtrTypeIterator.h"
> #include "llvm/Support/MathExtras.h"
> +#include "llvm/Support/FEnv.h"
> #include <cerrno>
> #include <cmath>
> -
> -#include "FEnv.h"
> using namespace llvm;
> 
> //===----------------------------------------------------------------------===//
> 
> Removed: llvm/trunk/lib/Analysis/FEnv.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/FEnv.h?rev=133713&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Analysis/FEnv.h (original)
> +++ llvm/trunk/lib/Analysis/FEnv.h (removed)
> @@ -1,56 +0,0 @@
> -//===- FEnv.h - Host floating-point exceptions ------------------*- C++ -*-===//
> -//
> -//                     The LLVM Compiler Infrastructure
> -//
> -// This file is distributed under the University of Illinois Open Source
> -// License. See LICENSE.TXT for details.
> -//
> -//===----------------------------------------------------------------------===//
> -//
> -// This file provides an operating system independent interface to
> -// floating-point exception interfaces.
> -//
> -//===----------------------------------------------------------------------===//
> -
> -#ifndef LLVM_SYSTEM_FENV_H
> -#define LLVM_SYSTEM_FENV_H
> -
> -#include "llvm/Config/config.h"
> -#include <cerrno>
> -#ifdef HAVE_FENV_H
> -#include <fenv.h>
> -#endif
> -
> -// FIXME: Clang's #include handling apparently doesn't work for libstdc++'s
> -// fenv.h; see PR6907 for details.
> -#if defined(__clang__) && defined(_GLIBCXX_FENV_H)
> -#undef HAVE_FENV_H
> -#endif
> -
> -namespace llvm {
> -namespace sys {
> -
> -/// llvm_fenv_clearexcept - Clear the floating-point exception state.
> -static inline void llvm_fenv_clearexcept() {
> -#ifdef HAVE_FENV_H
> -  feclearexcept(FE_ALL_EXCEPT);
> -#endif
> -  errno = 0;
> -}
> -
> -/// llvm_fenv_testexcept - Test if a floating-point exception was raised.
> -static inline bool llvm_fenv_testexcept() {
> -  int errno_val = errno;
> -  if (errno_val == ERANGE || errno_val == EDOM)
> -    return true;
> -#ifdef HAVE_FENV_H
> -  if (fetestexcept(FE_ALL_EXCEPT & ~FE_INEXACT))
> -    return true;
> -#endif
> -  return false;
> -}
> -
> -} // End sys namespace
> -} // End llvm namespace
> -
> -#endif
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

Thanks,

Justin Holewinski

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From nobled at dreamwidth.org  Thu Jun 23 08:56:02 2011
From: nobled at dreamwidth.org (Dylan Noblesmith)
Date: Thu, 23 Jun 2011 13:56:02 -0000
Subject: [llvm-commits] [llvm] r133716 - in /llvm/trunk/lib/Analysis:
	ConstantFolding.cpp FEnv.h
Message-ID: <20110623135602.12BDB2A6C12C@llvm.org>

Author: nobled
Date: Thu Jun 23 08:56:01 2011
New Revision: 133716

URL: http://llvm.org/viewvc/llvm-project?rev=133716&view=rev
Log:
revert 133714

It broke the build worse.


Added:
    llvm/trunk/lib/Analysis/FEnv.h
      - copied unchanged from r133713, llvm/trunk/lib/Analysis/FEnv.h
Modified:
    llvm/trunk/lib/Analysis/ConstantFolding.cpp

Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=133716&r1=133715&r2=133716&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)
+++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Thu Jun 23 08:56:01 2011
@@ -31,9 +31,10 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/GetElementPtrTypeIterator.h"
 #include "llvm/Support/MathExtras.h"
-#include "llvm/Support/FEnv.h"
 #include <cerrno>
 #include <cmath>
+
+#include "FEnv.h"
 using namespace llvm;
 
 //===----------------------------------------------------------------------===//



From rafael.espindola at gmail.com  Thu Jun 23 09:02:13 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 23 Jun 2011 14:02:13 -0000
Subject: [llvm-commits] [llvm] r133717 -
	/llvm/trunk/include/llvm/Support/FEnv.h
Message-ID: <20110623140213.C4C682A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 23 09:02:13 2011
New Revision: 133717

URL: http://llvm.org/viewvc/llvm-project?rev=133717&view=rev
Log:
Add missing file.

Added:
    llvm/trunk/include/llvm/Support/FEnv.h

Added: llvm/trunk/include/llvm/Support/FEnv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/FEnv.h?rev=133717&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Support/FEnv.h (added)
+++ llvm/trunk/include/llvm/Support/FEnv.h Thu Jun 23 09:02:13 2011
@@ -0,0 +1,56 @@
+//===- llvm/Support/FEnv.h - Host floating-point exceptions ------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides an operating system independent interface to
+// floating-point exception interfaces.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_SYSTEM_FENV_H
+#define LLVM_SYSTEM_FENV_H
+
+#include "llvm/Config/config.h"
+#include <cerrno>
+#ifdef HAVE_FENV_H
+#include <fenv.h>
+#endif
+
+// FIXME: Clang's #include handling apparently doesn't work for libstdc++'s
+// fenv.h; see PR6907 for details.
+#if defined(__clang__) && defined(_GLIBCXX_FENV_H)
+#undef HAVE_FENV_H
+#endif
+
+namespace llvm {
+namespace sys {
+
+/// llvm_fenv_clearexcept - Clear the floating-point exception state.
+static inline void llvm_fenv_clearexcept() {
+#ifdef HAVE_FENV_H
+  feclearexcept(FE_ALL_EXCEPT);
+#endif
+  errno = 0;
+}
+
+/// llvm_fenv_testexcept - Test if a floating-point exception was raised.
+static inline bool llvm_fenv_testexcept() {
+  int errno_val = errno;
+  if (errno_val == ERANGE || errno_val == EDOM)
+    return true;
+#ifdef HAVE_FENV_H
+  if (fetestexcept(FE_ALL_EXCEPT & ~FE_INEXACT))
+    return true;
+#endif
+  return false;
+}
+
+} // End sys namespace
+} // End llvm namespace
+
+#endif



From benny.kra at googlemail.com  Thu Jun 23 09:16:27 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Thu, 23 Jun 2011 16:16:27 +0200
Subject: [llvm-commits] [llvm] r133713 - in /llvm/trunk:
	include/llvm/Support/FEnv.h lib/Analysis/ConstantFolding.cpp
	lib/Analysis/FEnv.h
In-Reply-To: <20110623124554.7EFA12A6C12C@llvm.org>
References: <20110623124554.7EFA12A6C12C@llvm.org>
Message-ID: <DDCE6862-85D9-464F-8FD0-3AC62FEAB48F@googlemail.com>


On 23.06.2011, at 14:45, Dylan Noblesmith wrote:

> Author: nobled
> Date: Thu Jun 23 07:45:54 2011
> New Revision: 133713
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133713&view=rev
> Log:
> Support: make floating-exception header private
> 
> It has only one user. This eliminates the last include of
> config.h from the public headers -- ideally, config.h
> shouldn't even be installed by `make install` anymore.

In case you didn't figure out why this is breaking the build yet:

1. the current source dir (in this case llvm/lib/Analysis) is in the include path.
2. on a case-insensitive file system FEnv.h just includes itself, not the system fenv.h.

The easy fix would be to rename FEnv.h. I don't know why the current source dir is in the include path
maybe that should be changed.

- Benjamin



From rafael.espindola at gmail.com  Thu Jun 23 09:19:39 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 23 Jun 2011 14:19:39 -0000
Subject: [llvm-commits] [llvm] r133718 - in /llvm/trunk/lib/Analysis:
	ConstantFolding.cpp FEnv.h
Message-ID: <20110623141939.372BB2A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 23 09:19:39 2011
New Revision: 133718

URL: http://llvm.org/viewvc/llvm-project?rev=133718&view=rev
Log:
Revert "revert 133714"

This reverts commit e8e00f5efb4a22238f2407bf813de4606f30c5aa.

The cmake build on OS X is still broken.

Removed:
    llvm/trunk/lib/Analysis/FEnv.h
Modified:
    llvm/trunk/lib/Analysis/ConstantFolding.cpp

Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=133718&r1=133717&r2=133718&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)
+++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Thu Jun 23 09:19:39 2011
@@ -31,10 +31,9 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/GetElementPtrTypeIterator.h"
 #include "llvm/Support/MathExtras.h"
+#include "llvm/Support/FEnv.h"
 #include <cerrno>
 #include <cmath>
-
-#include "FEnv.h"
 using namespace llvm;
 
 //===----------------------------------------------------------------------===//

Removed: llvm/trunk/lib/Analysis/FEnv.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/FEnv.h?rev=133717&view=auto
==============================================================================
--- llvm/trunk/lib/Analysis/FEnv.h (original)
+++ llvm/trunk/lib/Analysis/FEnv.h (removed)
@@ -1,56 +0,0 @@
-//===- FEnv.h - Host floating-point exceptions ------------------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file provides an operating system independent interface to
-// floating-point exception interfaces.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_SYSTEM_FENV_H
-#define LLVM_SYSTEM_FENV_H
-
-#include "llvm/Config/config.h"
-#include <cerrno>
-#ifdef HAVE_FENV_H
-#include <fenv.h>
-#endif
-
-// FIXME: Clang's #include handling apparently doesn't work for libstdc++'s
-// fenv.h; see PR6907 for details.
-#if defined(__clang__) && defined(_GLIBCXX_FENV_H)
-#undef HAVE_FENV_H
-#endif
-
-namespace llvm {
-namespace sys {
-
-/// llvm_fenv_clearexcept - Clear the floating-point exception state.
-static inline void llvm_fenv_clearexcept() {
-#ifdef HAVE_FENV_H
-  feclearexcept(FE_ALL_EXCEPT);
-#endif
-  errno = 0;
-}
-
-/// llvm_fenv_testexcept - Test if a floating-point exception was raised.
-static inline bool llvm_fenv_testexcept() {
-  int errno_val = errno;
-  if (errno_val == ERANGE || errno_val == EDOM)
-    return true;
-#ifdef HAVE_FENV_H
-  if (fetestexcept(FE_ALL_EXCEPT & ~FE_INEXACT))
-    return true;
-#endif
-  return false;
-}
-
-} // End sys namespace
-} // End llvm namespace
-
-#endif



From justin.holewinski at gmail.com  Thu Jun 23 09:54:33 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Thu, 23 Jun 2011 10:54:33 -0400
Subject: [llvm-commits] [llvm] r133718 - in /llvm/trunk/lib/Analysis:
	ConstantFolding.cpp FEnv.h
In-Reply-To: <20110623141939.372BB2A6C12C@llvm.org>
References: <20110623141939.372BB2A6C12C@llvm.org>
Message-ID: <C38DB8DE-996C-473F-87F6-18DAC288DDA0@gmail.com>


On Jun 23, 2011, at 10:19 AM, Rafael Espindola wrote:

> Author: rafael
> Date: Thu Jun 23 09:19:39 2011
> New Revision: 133718
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133718&view=rev
> Log:
> Revert "revert 133714"
> 
> This reverts commit e8e00f5efb4a22238f2407bf813de4606f30c5aa.
> 
> The cmake build on OS X is still broken.

What's wrong with the CMake build?  This commit fixes the build for me with 10.7 + Xcode 4.2 + CMake 2.8.4.  I build LLVM and Clang together.

> 
> Removed:
>    llvm/trunk/lib/Analysis/FEnv.h
> Modified:
>    llvm/trunk/lib/Analysis/ConstantFolding.cpp
> 
> Modified: llvm/trunk/lib/Analysis/ConstantFolding.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ConstantFolding.cpp?rev=133718&r1=133717&r2=133718&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/ConstantFolding.cpp (original)
> +++ llvm/trunk/lib/Analysis/ConstantFolding.cpp Thu Jun 23 09:19:39 2011
> @@ -31,10 +31,9 @@
> #include "llvm/Support/ErrorHandling.h"
> #include "llvm/Support/GetElementPtrTypeIterator.h"
> #include "llvm/Support/MathExtras.h"
> +#include "llvm/Support/FEnv.h"
> #include <cerrno>
> #include <cmath>
> -
> -#include "FEnv.h"
> using namespace llvm;
> 
> //===----------------------------------------------------------------------===//
> 
> Removed: llvm/trunk/lib/Analysis/FEnv.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/FEnv.h?rev=133717&view=auto
> ==============================================================================
> --- llvm/trunk/lib/Analysis/FEnv.h (original)
> +++ llvm/trunk/lib/Analysis/FEnv.h (removed)
> @@ -1,56 +0,0 @@
> -//===- FEnv.h - Host floating-point exceptions ------------------*- C++ -*-===//
> -//
> -//                     The LLVM Compiler Infrastructure
> -//
> -// This file is distributed under the University of Illinois Open Source
> -// License. See LICENSE.TXT for details.
> -//
> -//===----------------------------------------------------------------------===//
> -//
> -// This file provides an operating system independent interface to
> -// floating-point exception interfaces.
> -//
> -//===----------------------------------------------------------------------===//
> -
> -#ifndef LLVM_SYSTEM_FENV_H
> -#define LLVM_SYSTEM_FENV_H
> -
> -#include "llvm/Config/config.h"
> -#include <cerrno>
> -#ifdef HAVE_FENV_H
> -#include <fenv.h>
> -#endif
> -
> -// FIXME: Clang's #include handling apparently doesn't work for libstdc++'s
> -// fenv.h; see PR6907 for details.
> -#if defined(__clang__) && defined(_GLIBCXX_FENV_H)
> -#undef HAVE_FENV_H
> -#endif
> -
> -namespace llvm {
> -namespace sys {
> -
> -/// llvm_fenv_clearexcept - Clear the floating-point exception state.
> -static inline void llvm_fenv_clearexcept() {
> -#ifdef HAVE_FENV_H
> -  feclearexcept(FE_ALL_EXCEPT);
> -#endif
> -  errno = 0;
> -}
> -
> -/// llvm_fenv_testexcept - Test if a floating-point exception was raised.
> -static inline bool llvm_fenv_testexcept() {
> -  int errno_val = errno;
> -  if (errno_val == ERANGE || errno_val == EDOM)
> -    return true;
> -#ifdef HAVE_FENV_H
> -  if (fetestexcept(FE_ALL_EXCEPT & ~FE_INEXACT))
> -    return true;
> -#endif
> -  return false;
> -}
> -
> -} // End sys namespace
> -} // End llvm namespace
> -
> -#endif
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

Thanks,

Justin Holewinski

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From aggarwa4 at illinois.edu  Thu Jun 23 10:12:30 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 15:12:30 -0000
Subject: [llvm-commits] [poolalloc] r133719 -
	/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
Message-ID: <20110623151231.03B792A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Jun 23 10:12:30 2011
New Revision: 133719

URL: http://llvm.org/viewvc/llvm-project?rev=133719&view=rev
Log:
Fix prototype for getTypeTag.

Also, if the src pointer for the getTypeTag is 
typesafe, set the metadata to TOP.

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=133719&r1=133718&r2=133719&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Thu Jun 23 10:12:30 2011
@@ -124,6 +124,7 @@
                                      VoidPtrTy, /*ptr*/
                                      Int64Ty, /*size*/
                                      TypeTagPtrTy, /*dest for type tag*/
+                                     Int32Ty, /*tag*/
                                      NULL);
   MallocFunc = M.getFunction("malloc");
 
@@ -225,6 +226,20 @@
     CallInst *CI = dyn_cast<CallInst>(User);
     assert(CI);
     if(TS->isTypeSafe(CI->getOperand(1)->stripPointerCasts(), CI->getParent()->getParent())) {
+      Constant *memsetF = M.getOrInsertFunction ("llvm.memset.i64", VoidTy,
+                                                 VoidPtrTy,
+                                                 Int8Ty,
+                                                 Int64Ty,
+                                                 Int32Ty,
+                                                 NULL);
+      AllocaInst *AI = dyn_cast<AllocaInst>(CI->getOperand(3)->stripPointerCasts());
+      assert(AI);
+      std::vector<Value*>Args;
+      Args.push_back(CI->getOperand(3));
+      Args.push_back(ConstantInt::get(Int8Ty, 1));
+      Args.push_back(CI->getOperand(2));
+      Args.push_back(ConstantInt::get(Int32Ty, AI->getAlignment()));
+      CallInst::Create(memsetF, Args.begin(), Args.end(), "", CI);
       toDelete.push_back(CI);
     }
   }



From aggarwa4 at illinois.edu  Thu Jun 23 10:12:56 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 15:12:56 -0000
Subject: [llvm-commits] [poolalloc] r133720 -
 /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
Message-ID: <20110623151256.866992A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Jun 23 10:12:56 2011
New Revision: 133720

URL: http://llvm.org/viewvc/llvm-project?rev=133720&view=rev
Log:
Add some debug printing.

Modified:
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=133720&r1=133719&r2=133720&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Thu Jun 23 10:12:56 2011
@@ -293,6 +293,9 @@
 void setTypeInfo(void *dstptr, TypeTagTy *metadata, uint64_t size, uint32_t tag) {
   uintptr_t d = maskAddress(dstptr);
   memcpy(&shadow_begin[d], metadata, size);
+#if DEBUG
+  printf("Set(%d): %p, %p | %lu bytes \n", tag, dstptr, metadata, size);
+#endif
 }
 
 /**



From rafael.espindola at gmail.com  Thu Jun 23 10:27:28 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Thu, 23 Jun 2011 11:27:28 -0400
Subject: [llvm-commits] [llvm] r133718 - in /llvm/trunk/lib/Analysis:
 ConstantFolding.cpp FEnv.h
In-Reply-To: <C38DB8DE-996C-473F-87F6-18DAC288DDA0@gmail.com>
References: <20110623141939.372BB2A6C12C@llvm.org>
	<C38DB8DE-996C-473F-87F6-18DAC288DDA0@gmail.com>
Message-ID: <4E035B60.6000402@gmail.com>

On 11-06-23 10:54 AM, Justin Holewinski wrote:
>
> On Jun 23, 2011, at 10:19 AM, Rafael Espindola wrote:
>
>> Author: rafael
>> Date: Thu Jun 23 09:19:39 2011
>> New Revision: 133718
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=133718&view=rev
>> <http://llvm.org/viewvc/llvm-project?rev=133718&view=rev>
>> Log:
>> Revert "revert 133714"
>>
>> This reverts commit e8e00f5efb4a22238f2407bf813de4606f30c5aa.
>>
>> The cmake build on OS X is still broken.
>
> What's wrong with the CMake build? This commit fixes the build for me
> with 10.7 + Xcode 4.2 + CMake 2.8.4. I build LLVM and Clang together.

The error was:

In file included from 
/Users/espindola/llvm/llvm/lib/Analysis/ConstantFolding.cpp:37:
/Users/espindola/llvm/llvm/lib/Analysis/FEnv.h:36:17: error: use of 
undeclared identifier 'FE_ALL_EXCEPT'
   feclearexcept(FE_ALL_EXCEPT);
                 ^
/Users/espindola/llvm/llvm/lib/Analysis/FEnv.h:47:20: error: use of 
undeclared identifier 'FE_ALL_EXCEPT'
   if (fetestexcept(FE_ALL_EXCEPT & ~FE_INEXACT))
                    ^
/Users/espindola/llvm/llvm/lib/Analysis/FEnv.h:47:37: error: use of 
undeclared identifier 'FE_INEXACT'
   if (fetestexcept(FE_ALL_EXCEPT & ~FE_INEXACT))
                                     ^

10.6, xcode 4.0.

>
> Thanks,
>
> Justin Holewinski
>

Cheers,
Rafael

From justin.holewinski at gmail.com  Thu Jun 23 11:09:30 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Thu, 23 Jun 2011 12:09:30 -0400
Subject: [llvm-commits] [llvm] r133664 - in /llvm/trunk:
	cmake/modules/HandleLLVMOptions.cmake
	test/CodeGen/X86/2011-06-14-PreschedRegalias.ll test/Makefile
	test/lit.cfg test/lit.site.cfg.in utils/lit/lit/TestRunner.py
	utils/lit/lit/TestingConfig.py
In-Reply-To: <20110622232319.9B2BE2A6C12C@llvm.org>
References: <20110622232319.9B2BE2A6C12C@llvm.org>
Message-ID: <C563B360-C5D2-467B-A7FA-B46D47DC24F0@gmail.com>

This seems to be breaking the regression tests for me on OS X, with Python 2.7 and CMake 2.8.4.  Specifically, the line:

config.enable_assertions = @LLVM_ENABLE_ASSERTIONS@

For me, this is being configured as:

config.enable_assertions = ON

which is invalid Python (symbol 'ON' does not exist).  Manually changing this to:

config.enable_assertions = 1

fixes the issue.


Seems to be a CMake naming issue (using ON instead of 1)

On Jun 22, 2011, at 7:23 PM, Andrew Trick wrote:

> Author: atrick
> Date: Wed Jun 22 18:23:19 2011
> New Revision: 133664
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133664&view=rev
> Log:
> lit support for REQUIRES: asserts.
> 
> Take #2. Don't piggyback on the existing config.build_mode. Instead,
> define a new lit feature for each build feature we need (currently
> just "asserts"). Teach both autoconf'd and cmake'd Makefiles to define
> this feature within test/lit.site.cfg. This doesn't require any lit
> harness changes and should be more robust across build systems.
> 
> Modified:
>    llvm/trunk/cmake/modules/HandleLLVMOptions.cmake
>    llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
>    llvm/trunk/test/Makefile
>    llvm/trunk/test/lit.cfg
>    llvm/trunk/test/lit.site.cfg.in
>    llvm/trunk/utils/lit/lit/TestRunner.py
>    llvm/trunk/utils/lit/lit/TestingConfig.py
> 
> Modified: llvm/trunk/cmake/modules/HandleLLVMOptions.cmake
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/HandleLLVMOptions.cmake?rev=133664&r1=133663&r2=133664&view=diff
> ==============================================================================
> --- llvm/trunk/cmake/modules/HandleLLVMOptions.cmake (original)
> +++ llvm/trunk/cmake/modules/HandleLLVMOptions.cmake Wed Jun 22 18:23:19 2011
> @@ -36,13 +36,8 @@
>   # explicitly undefine it:
>   if( uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" )
>     add_definitions( -UNDEBUG )
> -    set(LLVM_BUILD_MODE "Release")
> -  else()
> -    set(LLVM_BUILD_MODE "Debug")
>   endif()
> -  set(LLVM_BUILD_MODE "${LLVM_BUILD_MODE}+Asserts")
> else()
> -  set(LLVM_BUILD_MODE "Release")
>   if( NOT uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" )
>     if( NOT MSVC_IDE AND NOT XCODE )
>       add_definitions( -DNDEBUG )
> 
> Modified: llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll?rev=133664&r1=133663&r2=133664&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll Wed Jun 22 18:23:19 2011
> @@ -1,5 +1,5 @@
> ; RUN: llc < %s -march=x86-64 -stress-sched | FileCheck %s
> -; REQUIRES: Asserts
> +; REQUIRES: asserts
> ; Test interference between physreg aliases during preRAsched.
> ; mul wants an operand in AL, but call clobbers it.
> 
> 
> Modified: llvm/trunk/test/Makefile
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=133664&r1=133663&r2=133664&view=diff
> ==============================================================================
> --- llvm/trunk/test/Makefile (original)
> +++ llvm/trunk/test/Makefile Wed Jun 22 18:23:19 2011
> @@ -171,15 +171,21 @@
> 	@test ! -f site.exp || mv site.exp site.bak
> 	@mv site.tmp site.exp
> 
> +ifeq ($(DISABLE_ASSERTIONS),1)
> +ENABLE_ASSERTIONS=0
> +else
> +ENABLE_ASSERTIONS=1
> +endif
> +
> lit.site.cfg: site.exp
> 	@echo "Making LLVM 'lit.site.cfg' file..."
> 	@$(ECHOPATH) s=@LLVM_SOURCE_DIR@=$(LLVM_SRC_ROOT)=g > lit.tmp
> 	@$(ECHOPATH) s=@LLVM_BINARY_DIR@=$(LLVM_OBJ_ROOT)=g >> lit.tmp
> 	@$(ECHOPATH) s=@LLVM_TOOLS_DIR@=$(ToolDir)=g >> lit.tmp
> -	@$(ECHOPATH) s=@LLVM_BUILD_MODE@=$(BuildMode)=g >> lit.tmp
> 	@$(ECHOPATH) s=@LLVMGCCDIR@=$(LLVMGCCDIR)=g >> lit.tmp
> 	@$(ECHOPATH) s=@PYTHON_EXECUTABLE@=python=g >> lit.tmp
> 	@$(ECHOPATH) s=@ENABLE_SHARED@=$(ENABLE_SHARED)=g >> lit.tmp
> +	@$(ECHOPATH) s=@LLVM_ENABLE_ASSERTIONS@=$(ENABLE_ASSERTIONS)=g >> lit.tmp
> 	@sed -f lit.tmp $(PROJ_SRC_DIR)/lit.site.cfg.in > $@
> 	@-rm -f lit.tmp
> 
> 
> Modified: llvm/trunk/test/lit.cfg
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.cfg?rev=133664&r1=133663&r2=133664&view=diff
> ==============================================================================
> --- llvm/trunk/test/lit.cfg (original)
> +++ llvm/trunk/test/lit.cfg Wed Jun 22 18:23:19 2011
> @@ -306,3 +306,6 @@
> 
> if loadable_module:
>     config.available_features.add('loadable_module')
> +
> +if config.enable_assertions:
> +    config.available_features.add('asserts')
> 
> Modified: llvm/trunk/test/lit.site.cfg.in
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.site.cfg.in?rev=133664&r1=133663&r2=133664&view=diff
> ==============================================================================
> --- llvm/trunk/test/lit.site.cfg.in (original)
> +++ llvm/trunk/test/lit.site.cfg.in Wed Jun 22 18:23:19 2011
> @@ -5,9 +5,9 @@
> config.llvm_tools_dir = "@LLVM_TOOLS_DIR@"
> config.llvmgcc_dir = "@LLVMGCCDIR@"
> config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"
> -config.llvm_build_modes = "@LLVM_BUILD_MODE@".split('+')
> config.python_executable = "@PYTHON_EXECUTABLE@"
> config.enable_shared = @ENABLE_SHARED@
> +config.enable_assertions = @LLVM_ENABLE_ASSERTIONS@
> 
> # Support substitution of the tools_dir with user parameters. This is
> # used when we can't determine the tool dir at configuration time.
> 
> Modified: llvm/trunk/utils/lit/lit/TestRunner.py
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestRunner.py?rev=133664&r1=133663&r2=133664&view=diff
> ==============================================================================
> --- llvm/trunk/utils/lit/lit/TestRunner.py (original)
> +++ llvm/trunk/utils/lit/lit/TestRunner.py Wed Jun 22 18:23:19 2011
> @@ -473,11 +473,9 @@
>     if script[-1][-1] == '\\':
>         return (Test.UNRESOLVED, "Test has unterminated run lines (with '\\')")
> 
> -    # Check that we have the required features or build modes:
> +    # Check that we have the required features:
>     missing_required_features = [f for f in requires
> -                                 if f not in test.config.available_features
> -                                 and f not in test.config.llvm_build_modes]
> -
> +                                 if f not in test.config.available_features]
>     if missing_required_features:
>         msg = ', '.join(missing_required_features)
>         return (Test.UNSUPPORTED,
> 
> Modified: llvm/trunk/utils/lit/lit/TestingConfig.py
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestingConfig.py?rev=133664&r1=133663&r2=133664&view=diff
> ==============================================================================
> --- llvm/trunk/utils/lit/lit/TestingConfig.py (original)
> +++ llvm/trunk/utils/lit/lit/TestingConfig.py Wed Jun 22 18:23:19 2011
> @@ -74,7 +74,6 @@
> 
>     def clone(self, path):
>         # FIXME: Chain implementations?
> -        # See attribute chaining in finish()
>         #
>         # FIXME: Allow extra parameters?
>         cfg = TestingConfig(self, self.name, self.suffixes, self.test_format,
> @@ -102,9 +101,3 @@
>             # files. Should we distinguish them?
>             self.test_source_root = str(self.test_source_root)
>         self.excludes = set(self.excludes)
> -
> -        # chain attributes by copying them
> -        if self.parent:
> -            for k,v in vars(self.parent).items():
> -                if not hasattr(self, k):
> -                    setattr(self, k, v)
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

Thanks,

Justin Holewinski

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From echristo at apple.com  Thu Jun 23 11:40:39 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 23 Jun 2011 09:40:39 -0700
Subject: [llvm-commits] [llvm] r133513 - in /llvm/trunk: include/llvm/
 include/llvm/Support/ lib/Target/CppBackend/ lib/Transforms/Scalar/
 lib/Transforms/Utils/ lib/VMCore/
In-Reply-To: <BANLkTi=f+tVOvb8kFC5WsHvuYwdT9g4rntcDO+79i6p6tihMzQ@mail.gmail.com>
References: <20110621103319.B0D332A6C12C@llvm.org>
	<5AAC95DA-F372-4AC4-BF66-AF474C061E34@apple.com>
	<184C58B8-49B3-40A8-A0EF-7718C77C9FB7@apple.com>
	<BANLkTi=f+tVOvb8kFC5WsHvuYwdT9g4rntcDO+79i6p6tihMzQ@mail.gmail.com>
Message-ID: <B0E33888-CF36-4FBC-9614-34979E90D041@apple.com>


On Jun 23, 2011, at 2:17 AM, Jay Foad wrote:

> On 23 June 2011 07:31, Eric Christopher <echristo at apple.com> wrote:
>> 
>> On Jun 22, 2011, at 11:24 AM, Eric Christopher wrote:
>> 
>>> 
>>> On Jun 21, 2011, at 3:33 AM, Jay Foad wrote:
>>> 
>>>> Author: foad
>>>> Date: Tue Jun 21 05:33:19 2011
>>>> New Revision: 133513
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=133513&view=rev
>>>> Log:
>>>> Reinstate r133435 and r133449 (reverted in r133499) now that the clang
>>>> self-hosted build failure has been fixed (r133512).
>>>> 
>>> 
>>> This is causing some additional warnings:
>>> 
>>> /Developer/usr/local/include/llvm/Instructions.h: In member function 'llvm::BasicBlock* llvm::PHINode::getIncomingBlock(const llvm::Use&) const':
>>> /Developer/usr/local/include/llvm/Instructions.h:1909: warning: implicit conversion shortens 64-bit value into a 32-bit value
> 
> I've fixed this one...

Thanks :)

> 
>>> To duplicate just turn on conversion warnings, in particular with llvm-gcc -Wshorten-64-to-32, in a file that includes Instructions.h.
> 
> (I can't tell if there are any others, because if I build with clang
> -Wshorten-64-to-32 I get loads of unrelated warnings)
> 

Yeah. It's near the end of a very long list of things for me. :(

>> I've gone ahead and reverted your patch in r133700 for the time being, should be an easy reapply after you fix the new header warnings :)
> 
> ... and re-reinstated my patch in r133708.

Thank you very much :)

-eric

From aggarwa4 at illinois.edu  Thu Jun 23 11:59:23 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 16:59:23 -0000
Subject: [llvm-commits] [poolalloc] r133722 -
	/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
Message-ID: <20110623165924.0618C2A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Jun 23 11:59:23 2011
New Revision: 133722

URL: http://llvm.org/viewvc/llvm-project?rev=133722&view=rev
Log:
When setting to TOP use 0xFF.

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=133722&r1=133721&r2=133722&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Thu Jun 23 11:59:23 2011
@@ -236,7 +236,7 @@
       assert(AI);
       std::vector<Value*>Args;
       Args.push_back(CI->getOperand(3));
-      Args.push_back(ConstantInt::get(Int8Ty, 1));
+      Args.push_back(ConstantInt::get(Int8Ty, 255));
       Args.push_back(CI->getOperand(2));
       Args.push_back(ConstantInt::get(Int32Ty, AI->getAlignment()));
       CallInst::Create(memsetF, Args.begin(), Args.end(), "", CI);



From aggarwa4 at illinois.edu  Thu Jun 23 12:00:32 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 17:00:32 -0000
Subject: [llvm-commits] [poolalloc] r133723 -
	/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
Message-ID: <20110623170032.33B0C2A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Jun 23 12:00:32 2011
New Revision: 133723

URL: http://llvm.org/viewvc/llvm-project?rev=133723&view=rev
Log:
Push checks on bitcasts to their uses. A bitcast is not 
really a use.

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133723&r1=133722&r2=133723&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 23 12:00:32 2011
@@ -1778,17 +1778,31 @@
     Args.push_back(getTagCounter());
     CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", &LI);
   }
+  visitUses(&LI, AI, BCI);
 
-  for(Value::use_iterator II = LI.use_begin(); II != LI.use_end(); ++II) {
+  if(AI->getNumUses() == 1) {
+    // No uses needed checks
+    getTypeCall->eraseFromParent();
+  }
+
+  // Create the call to the runtime check and place it before the load instruction.
+  numLoadChecks++;
+  return true;
+}
+// AI - metadata
+// BCI - ptr
+bool TypeChecks::visitUses(Instruction *I, AllocaInst *AI, CastInst *BCI) {
+  for(Value::use_iterator II = I->use_begin(); II != I->use_end(); ++II) {
     if(DisablePtrCmpChecks) {
       if(isa<CmpInst>(II)) {
-        if(LI.getType()->isPointerTy())
+        if(I->getType()->isPointerTy())
           continue;
       }
     }
+
     std::vector<Value *> Args;
-    Args.push_back(getTypeMarkerConstant(&LI));
-    Args.push_back(getSizeConstant(LI.getType()));
+    Args.push_back(getTypeMarkerConstant(I));
+    Args.push_back(getSizeConstant(I->getType()));
     Args.push_back(AI);
     Args.push_back(BCI);
     Args.push_back(getTagCounter());
@@ -1803,24 +1817,18 @@
       Args.push_back(getTagCounter());
       // Create the call to the runtime check and place it before the copying store instruction.
       CallInst::Create(setTypeInfo, Args.begin(), Args.end(), "", SI);
-    }
-    else if(PHINode *PH = dyn_cast<PHINode>(II)) {
+    } else if(PHINode *PH = dyn_cast<PHINode>(II)) {
       BasicBlock *BB = PH->getIncomingBlock(II);
       CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", BB->getTerminator());
+    } else if(BitCastInst *BI = dyn_cast<BitCastInst>(II)) {
+      visitUses(BI, AI, BCI);
+      //CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", cast<Instruction>(II.getUse().getUser()));
     } else {
       CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", cast<Instruction>(II.getUse().getUser()));
     }
   }
-  if(AI->getNumUses() == 1) {
-    // No uses needed checks
-    getTypeCall->eraseFromParent();
-  }
-
-  // Create the call to the runtime check and place it before the load instruction.
-  numLoadChecks++;
   return true;
 }
-
 // Insert runtime checks before all store instructions.
 bool TypeChecks::visitStoreInst(Module &M, StoreInst &SI) {
   // Cast the pointer operand to i8* for the runtime function.



From atrick at apple.com  Thu Jun 23 12:52:36 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 23 Jun 2011 17:52:36 -0000
Subject: [llvm-commits] [llvm] r133725 - in /llvm/trunk/test: CMakeLists.txt
	Makefile lit.site.cfg.in
Message-ID: <20110623175236.F35D82A6C12C@llvm.org>

Author: atrick
Date: Thu Jun 23 12:52:36 2011
New Revision: 133725

URL: http://llvm.org/viewvc/llvm-project?rev=133725&view=rev
Log:
cmake+lit: handle ENABLE_ASSERTIONS feature properly.

Modified:
    llvm/trunk/test/CMakeLists.txt
    llvm/trunk/test/Makefile
    llvm/trunk/test/lit.site.cfg.in

Modified: llvm/trunk/test/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CMakeLists.txt?rev=133725&r1=133724&r2=133725&view=diff
==============================================================================
--- llvm/trunk/test/CMakeLists.txt (original)
+++ llvm/trunk/test/CMakeLists.txt Thu Jun 23 12:52:36 2011
@@ -79,6 +79,12 @@
   set(ENABLE_SHARED ${LLVM_SHARED_LIBS_ENABLED})
   set(SHLIBPATH_VAR ${SHLIBPATH_VAR})
 
+  if(LLVM_ENABLE_ASSERTIONS)
+    set(ENABLE_ASSERTIONS "1")
+  else()
+    set(ENABLE_ASSERTIONS "0")
+  endif(LLVM_ENABLE_ASSERTIONS)
+
   # lit.site.cfg uses the config-time build mode
   set(LLVM_BUILD_MODE "${LLVM_BUILD_MODE}")
 

Modified: llvm/trunk/test/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=133725&r1=133724&r2=133725&view=diff
==============================================================================
--- llvm/trunk/test/Makefile (original)
+++ llvm/trunk/test/Makefile Thu Jun 23 12:52:36 2011
@@ -185,7 +185,7 @@
 	@$(ECHOPATH) s=@LLVMGCCDIR@=$(LLVMGCCDIR)=g >> lit.tmp
 	@$(ECHOPATH) s=@PYTHON_EXECUTABLE@=python=g >> lit.tmp
 	@$(ECHOPATH) s=@ENABLE_SHARED@=$(ENABLE_SHARED)=g >> lit.tmp
-	@$(ECHOPATH) s=@LLVM_ENABLE_ASSERTIONS@=$(ENABLE_ASSERTIONS)=g >> lit.tmp
+	@$(ECHOPATH) s=@ENABLE_ASSERTIONS@=$(ENABLE_ASSERTIONS)=g >> lit.tmp
 	@sed -f lit.tmp $(PROJ_SRC_DIR)/lit.site.cfg.in > $@
 	@-rm -f lit.tmp
 

Modified: llvm/trunk/test/lit.site.cfg.in
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.site.cfg.in?rev=133725&r1=133724&r2=133725&view=diff
==============================================================================
--- llvm/trunk/test/lit.site.cfg.in (original)
+++ llvm/trunk/test/lit.site.cfg.in Thu Jun 23 12:52:36 2011
@@ -7,7 +7,7 @@
 config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"
 config.python_executable = "@PYTHON_EXECUTABLE@"
 config.enable_shared = @ENABLE_SHARED@
-config.enable_assertions = @LLVM_ENABLE_ASSERTIONS@
+config.enable_assertions = @ENABLE_ASSERTIONS@
 
 # Support substitution of the tools_dir with user parameters. This is
 # used when we can't determine the tool dir at configuration time.



From evan.cheng at apple.com  Thu Jun 23 12:54:54 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 23 Jun 2011 17:54:54 -0000
Subject: [llvm-commits] [llvm] r133726 - in /llvm/trunk/lib/Target/X86:
 X86FastISel.cpp X86ISelLowering.cpp X86ISelLowering.h X86Subtarget.cpp
 X86Subtarget.h X86TargetMachine.cpp
Message-ID: <20110623175454.AE28F2A6C12C@llvm.org>

Author: evancheng
Date: Thu Jun 23 12:54:54 2011
New Revision: 133726

URL: http://llvm.org/viewvc/llvm-project?rev=133726&view=rev
Log:
Remove TargetOptions.h dependency from X86Subtarget.

Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
    llvm/trunk/lib/Target/X86/X86ISelLowering.h
    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
    llvm/trunk/lib/Target/X86/X86Subtarget.h
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=133726&r1=133725&r2=133726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Jun 23 12:54:54 2011
@@ -15,6 +15,7 @@
 
 #include "X86.h"
 #include "X86InstrBuilder.h"
+#include "X86ISelLowering.h"
 #include "X86RegisterInfo.h"
 #include "X86Subtarget.h"
 #include "X86TargetMachine.h"
@@ -1493,7 +1494,8 @@
     return false;
 
   // Fast-isel doesn't know about callee-pop yet.
-  if (Subtarget->IsCalleePop(isVarArg, CC))
+  if (X86::isCalleePop(CC, Subtarget->is64Bit(), isVarArg,
+                       GuaranteedTailCallOpt))
     return false;
 
   // Check whether the function can return without sret-demotion.

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=133726&r1=133725&r2=133726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Thu Jun 23 12:54:54 2011
@@ -1898,7 +1898,7 @@
   }
 
   // Some CCs need callee pop.
-  if (Subtarget->IsCalleePop(isVarArg, CallConv)) {
+  if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) {
     FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything.
   } else {
     FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing.
@@ -2383,7 +2383,7 @@
 
   // Create the CALLSEQ_END node.
   unsigned NumBytesForCalleeToPush;
-  if (Subtarget->IsCalleePop(isVarArg, CallConv))
+  if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt))
     NumBytesForCalleeToPush = NumBytes;    // Callee pops everything
   else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet)
     // If this is a call to a struct-return function, the callee
@@ -2876,6 +2876,29 @@
   return false;
 }
 
+/// isCalleePop - Determines whether the callee is required to pop its
+/// own arguments. Callee pop is necessary to support tail calls.
+bool X86::isCalleePop(CallingConv::ID CallingConv,
+                      bool is64Bit, bool IsVarArg, bool TailCallOpt) {
+  if (IsVarArg)
+    return false;
+
+  switch (CallingConv) {
+  default:
+    return false;
+  case CallingConv::X86_StdCall:
+    return !is64Bit;
+  case CallingConv::X86_FastCall:
+    return !is64Bit;
+  case CallingConv::X86_ThisCall:
+    return !is64Bit;
+  case CallingConv::Fast:
+    return TailCallOpt;
+  case CallingConv::GHC:
+    return TailCallOpt;
+  }
+}
+
 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86
 /// specific condition code, returning the condition code and the LHS/RHS of the
 /// comparison to make.

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=133726&r1=133725&r2=133726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Thu Jun 23 12:54:54 2011
@@ -466,6 +466,12 @@
     /// fit into displacement field of the instruction.
     bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
                                       bool hasSymbolicDisplacement = true);
+
+
+    /// isCalleePop - Determines whether the callee is required to pop its
+    /// own arguments. Callee pop is necessary to support tail calls.
+    bool isCalleePop(CallingConv::ID CallingConv,
+                     bool is64Bit, bool IsVarArg, bool TailCallOpt);
   }
 
   //===--------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=133726&r1=133725&r2=133726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Thu Jun 23 12:54:54 2011
@@ -20,7 +20,6 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/SmallVector.h"
 using namespace llvm;
 
@@ -286,7 +285,7 @@
 }
 
 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS, 
-                           bool is64Bit)
+                           bool is64Bit, unsigned StackAlignOverride)
   : PICStyle(PICStyles::None)
   , X86SSELevel(NoMMXSSE)
   , X863DNowLevel(NoThreeDNow)
@@ -308,10 +307,6 @@
   , TargetTriple(TT)
   , Is64Bit(is64Bit) {
 
-  // default to hard float ABI
-  if (FloatABIType == FloatABI::Default)
-    FloatABIType = FloatABI::Hard;
-    
   // Determine default and user specified characteristics
   if (!FS.empty()) {
     // If feature string is not empty, parse features string.
@@ -346,33 +341,9 @@
 
   // Stack alignment is 16 bytes on Darwin, FreeBSD, Linux and Solaris (both
   // 32 and 64 bit) and for all 64-bit targets.
-  if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
-      isTargetSolaris() || Is64Bit)
+  if (StackAlignOverride)
+    stackAlignment = StackAlignOverride;
+  else if (isTargetDarwin() || isTargetFreeBSD() || isTargetLinux() ||
+           isTargetSolaris() || Is64Bit)
     stackAlignment = 16;
-
-  if (StackAlignment)
-    stackAlignment = StackAlignment;
-}
-
-/// IsCalleePop - Determines whether the callee is required to pop its
-/// own arguments. Callee pop is necessary to support tail calls.
-bool X86Subtarget::IsCalleePop(bool IsVarArg,
-                               CallingConv::ID CallingConv) const {
-  if (IsVarArg)
-    return false;
-
-  switch (CallingConv) {
-  default:
-    return false;
-  case CallingConv::X86_StdCall:
-    return !is64Bit();
-  case CallingConv::X86_FastCall:
-    return !is64Bit();
-  case CallingConv::X86_ThisCall:
-    return !is64Bit();
-  case CallingConv::Fast:
-    return GuaranteedTailCallOpt;
-  case CallingConv::GHC:
-    return GuaranteedTailCallOpt;
-  }
 }

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=133726&r1=133725&r2=133726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Thu Jun 23 12:54:54 2011
@@ -117,7 +117,8 @@
   /// This constructor initializes the data members to match that
   /// of the specified triple.
   ///
-  X86Subtarget(const std::string &TT, const std::string &FS, bool is64Bit);
+  X86Subtarget(const std::string &TT, const std::string &FS, bool is64Bit,
+               unsigned StackAlignOverride);
 
   /// getStackAlignment - Returns the minimum alignment known to hold of the
   /// stack frame on entry to the function and which must be maintained by every
@@ -248,9 +249,6 @@
   /// indicating the number of scheduling cycles of backscheduling that
   /// should be attempted.
   unsigned getSpecialAddressLatency() const;
-
-  /// IsCalleePop - Test whether a function should pop its own arguments.
-  bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
 };
 
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=133726&r1=133725&r2=133726&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Jun 23 12:54:54 2011
@@ -117,7 +117,7 @@
 X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
                                    const std::string &FS, bool is64Bit)
   : LLVMTargetMachine(T, TT),
-    Subtarget(TT, FS, is64Bit),
+    Subtarget(TT, FS, is64Bit, StackAlignment),
     FrameLowering(*this, Subtarget),
     ELFWriterInfo(is64Bit, true) {
   DefRelocModel = getRelocationModel();
@@ -182,6 +182,10 @@
   // Finally, if we have "none" as our PIC style, force to static mode.
   if (Subtarget.getPICStyle() == PICStyles::None)
     setRelocationModel(Reloc::Static);
+
+  // default to hard float ABI
+  if (FloatABIType == FloatABI::Default)
+    FloatABIType = FloatABI::Hard;    
 }
 
 //===----------------------------------------------------------------------===//



From atrick at apple.com  Thu Jun 23 13:00:32 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 23 Jun 2011 18:00:32 -0000
Subject: [llvm-commits] [llvm] r133729 - /llvm/trunk/test/CMakeLists.txt
Message-ID: <20110623180032.6F2522A6C12C@llvm.org>

Author: atrick
Date: Thu Jun 23 13:00:32 2011
New Revision: 133729

URL: http://llvm.org/viewvc/llvm-project?rev=133729&view=rev
Log:
cmake+lit: final cleanup related to the recent churn

Modified:
    llvm/trunk/test/CMakeLists.txt

Modified: llvm/trunk/test/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CMakeLists.txt?rev=133729&r1=133728&r2=133729&view=diff
==============================================================================
--- llvm/trunk/test/CMakeLists.txt (original)
+++ llvm/trunk/test/CMakeLists.txt Thu Jun 23 13:00:32 2011
@@ -71,6 +71,8 @@
   MAKE_DIRECTORY(${CMAKE_CURRENT_BINARY_DIR}/Unit)
 
   # Configuration-time: See Unit/lit.site.cfg.in
+  set(LLVM_BUILD_MODE "%(build_mode)s")
+
   set(LLVM_SOURCE_DIR ${LLVM_MAIN_SRC_DIR})
   set(LLVM_BINARY_DIR ${LLVM_BINARY_DIR})
   set(LLVM_TOOLS_DIR "${LLVM_TOOLS_BINARY_DIR}/%(build_config)s")
@@ -85,17 +87,10 @@
     set(ENABLE_ASSERTIONS "0")
   endif(LLVM_ENABLE_ASSERTIONS)
 
-  # lit.site.cfg uses the config-time build mode
-  set(LLVM_BUILD_MODE "${LLVM_BUILD_MODE}")
-
   configure_file(
     ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in
     ${CMAKE_CURRENT_BINARY_DIR}/lit.site.cfg
     @ONLY)
-
-  # Unit/lit.site.cfg substitutes the runtime build_mode
-  set(LLVM_BUILD_MODE "%(build_mode)s")
-
   configure_file(
     ${CMAKE_CURRENT_SOURCE_DIR}/Unit/lit.site.cfg.in
     ${CMAKE_CURRENT_BINARY_DIR}/Unit/lit.site.cfg



From justin.holewinski at gmail.com  Thu Jun 23 13:10:03 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Thu, 23 Jun 2011 18:10:03 -0000
Subject: [llvm-commits] [llvm] r133732 - in /llvm/trunk/lib/Target/PTX:
 PTXAsmPrinter.cpp PTXISelDAGToDAG.cpp PTXISelLowering.cpp PTXISelLowering.h
 PTXInstrInfo.td PTXSubtarget.h
Message-ID: <20110623181003.5C0A42A6C12C@llvm.org>

Author: jholewinski
Date: Thu Jun 23 13:10:03 2011
New Revision: 133732

URL: http://llvm.org/viewvc/llvm-project?rev=133732&view=rev
Log:
PTX: Use .param space for parameters in device functions for SM >= 2.0

FIXME: DCE is eliminating the final st.param.x calls, figure out why

Modified:
    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
    llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp
    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
    llvm/trunk/lib/Target/PTX/PTXISelLowering.h
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
    llvm/trunk/lib/Target/PTX/PTXSubtarget.h

Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133732&r1=133731&r2=133732&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Thu Jun 23 13:10:03 2011
@@ -417,6 +417,7 @@
 
   const PTXMachineFunctionInfo *MFI = MF->getInfo<PTXMachineFunctionInfo>();
   const bool isKernel = MFI->isKernel();
+  const PTXSubtarget& ST = TM.getSubtarget<PTXSubtarget>();
 
   std::string decl = isKernel ? ".entry" : ".func";
 
@@ -452,7 +453,7 @@
     if (i != b) {
       decl += ", ";
     }
-    if (isKernel) {
+    if (isKernel || ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
       decl += ".param .b";
       decl += utostr(*i);
       decl += " ";

Modified: llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp?rev=133732&r1=133731&r2=133732&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp Thu Jun 23 13:10:03 2011
@@ -15,6 +15,7 @@
 #include "PTXTargetMachine.h"
 #include "llvm/CodeGen/SelectionDAGISel.h"
 #include "llvm/DerivedTypes.h"
+#include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
@@ -42,7 +43,8 @@
 
   private:
     SDNode *SelectREAD_PARAM(SDNode *Node);
-
+    //SDNode *SelectSTORE_PARAM(SDNode *Node);
+    
     // We need this only because we can't match intruction BRAdp
     // pattern (PTXbrcond bb:$d, ...) in PTXInstrInfo.td
     SDNode *SelectBRCOND(SDNode *Node);
@@ -69,6 +71,8 @@
   switch (Node->getOpcode()) {
     case PTXISD::READ_PARAM:
       return SelectREAD_PARAM(Node);
+    // case PTXISD::STORE_PARAM:
+    //   return SelectSTORE_PARAM(Node);
     case ISD::BRCOND:
       return SelectBRCOND(Node);
     default:
@@ -86,20 +90,15 @@
 
   if (Node->getValueType(0) == MVT::i16) {
     opcode = PTX::LDpiU16;
-  }
-  else if (Node->getValueType(0) == MVT::i32) {
+  } else if (Node->getValueType(0) == MVT::i32) {
     opcode = PTX::LDpiU32;
-  }
-  else if (Node->getValueType(0) == MVT::i64) {
+  } else if (Node->getValueType(0) == MVT::i64) {
     opcode = PTX::LDpiU64;
-  }
-  else if (Node->getValueType(0) == MVT::f32) {
+  } else if (Node->getValueType(0) == MVT::f32) {
     opcode = PTX::LDpiF32;
-  }
-  else if (Node->getValueType(0) == MVT::f64) {
+  } else if (Node->getValueType(0) == MVT::f64) {
     opcode = PTX::LDpiF64;
-  }
-  else {
+  } else {
     llvm_unreachable("Unknown parameter type for ld.param");
   }
 
@@ -107,6 +106,42 @@
     GetPTXMachineNode(CurDAG, opcode, dl, Node->getValueType(0), index);
 }
 
+// SDNode *PTXDAGToDAGISel::SelectSTORE_PARAM(SDNode *Node) {
+//   SDValue  Chain = Node->getOperand(0);
+//   SDValue  index = Node->getOperand(1);
+//   SDValue  value = Node->getOperand(2);
+//   DebugLoc dl    = Node->getDebugLoc();
+//   unsigned opcode;
+
+//   if (index.getOpcode() != ISD::TargetConstant)
+//     llvm_unreachable("STORE_PARAM: index is not ISD::TargetConstant");
+
+//   if (value->getValueType(0) == MVT::i16) {
+//     opcode = PTX::STpiU16;
+//   } else if (value->getValueType(0) == MVT::i32) {
+//     opcode = PTX::STpiU32;
+//   } else if (value->getValueType(0) == MVT::i64) {
+//     opcode = PTX::STpiU64;
+//   } else if (value->getValueType(0) == MVT::f32) {
+//     opcode = PTX::STpiF32;
+//   } else if (value->getValueType(0) == MVT::f64) {
+//     opcode = PTX::STpiF64;
+//   } else {
+//     llvm_unreachable("Unknown parameter type for st.param");
+//   }
+
+//   SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
+//   SDValue PredReg = CurDAG->getRegister(PTX::NoRegister, MVT::i1);
+//   SDValue PredOp = CurDAG->getTargetConstant(PTX::PRED_NORMAL, MVT::i32);
+//   SDValue Ops[] = { Chain, index, value, PredReg, PredOp };
+//   //SDNode *RetNode = PTXInstrInfo::
+//   //  GetPTXMachineNode(CurDAG, opcode, dl, VTs, index, value);
+//   SDNode *RetNode = CurDAG->getMachineNode(opcode, dl, VTs, Ops, array_lengthof(Ops));
+//   DEBUG(dbgs() << "SelectSTORE_PARAM: Selected: ");
+//   RetNode->dumpr(CurDAG);
+//   return RetNode;
+// }
+
 SDNode *PTXDAGToDAGISel::SelectBRCOND(SDNode *Node) {
   assert(Node->getNumOperands() >= 3);
 

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=133732&r1=133731&r2=133732&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Thu Jun 23 13:10:03 2011
@@ -15,6 +15,7 @@
 #include "PTXISelLowering.h"
 #include "PTXMachineFunctionInfo.h"
 #include "PTXRegisterInfo.h"
+#include "PTXSubtarget.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineFunction.h"
@@ -106,6 +107,8 @@
       return "PTXISD::COPY_ADDRESS";
     case PTXISD::READ_PARAM:
       return "PTXISD::READ_PARAM";
+    case PTXISD::STORE_PARAM:
+      return "PTXISD::STORE_PARAM";
     case PTXISD::EXIT:
       return "PTXISD::EXIT";
     case PTXISD::RET:
@@ -192,6 +195,7 @@
   if (isVarArg) llvm_unreachable("PTX does not support varargs");
 
   MachineFunction &MF = DAG.getMachineFunction();
+  const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
   PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
 
   switch (CallConv) {
@@ -206,11 +210,16 @@
       break;
   }
 
-  if (MFI->isKernel()) {
-    // For kernel functions, we just need to emit the proper READ_PARAM ISDs
+  // We do one of two things here:
+  // IsKernel || SM >= 2.0  ->  Use param space for arguments
+  // SM < 2.0               ->  Use registers for arguments
+  
+  if (MFI->isKernel() || ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
+    // We just need to emit the proper READ_PARAM ISDs
     for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
 
-      assert(Ins[i].VT != MVT::i1 && "Kernels cannot take pred operands");
+      assert((!MFI->isKernel() || Ins[i].VT != MVT::i1) &&
+             "Kernels cannot take pred operands");
 
       SDValue ArgValue = DAG.getNode(PTXISD::READ_PARAM, dl, Ins[i].VT, Chain,
                                      DAG.getTargetConstant(i, MVT::i32));
@@ -299,31 +308,49 @@
 
   MachineFunction& MF = DAG.getMachineFunction();
   PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
-  SmallVector<CCValAssign, 16> RVLocs;
-  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
-                 getTargetMachine(), RVLocs, *DAG.getContext());
+  const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
 
   SDValue Flag;
 
-  CCInfo.AnalyzeReturn(Outs, RetCC_PTX);
+  if (ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
+    // For SM 2.0+, we return arguments in the param space
+    for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
+      SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
+      SDValue ParamIndex = DAG.getTargetConstant(i, MVT::i32);
+      SDValue Ops[] = { Chain, ParamIndex, OutVals[i], Flag };
+      Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, VTs, Ops,
+                          Flag.getNode() ? 4 : 3);
+      Flag = Chain.getValue(1);
+      // Instead of storing a physical register in our argument list, we just
+      // store the total size of the parameter, in bits.  The ASM printer
+      // knows how to process this.
+      MFI->addRetReg(Outs[i].VT.getStoreSizeInBits());
+    }
+  } else {
+    // For SM < 2.0, we return arguments in registers
+    SmallVector<CCValAssign, 16> RVLocs;
+    CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
+    getTargetMachine(), RVLocs, *DAG.getContext());
 
-  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
+    CCInfo.AnalyzeReturn(Outs, RetCC_PTX);
 
-    CCValAssign& VA  = RVLocs[i];
+    for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
+      CCValAssign& VA  = RVLocs[i];
 
-    assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
+      assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
 
-    unsigned Reg = VA.getLocReg();
+      unsigned Reg = VA.getLocReg();
 
-    DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
+      DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
 
-    Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag);
+      Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag);
 
-    // Guarantee that all emitted copies are stuck together,
-    // avoiding something bad
-    Flag = Chain.getValue(1);
+      // Guarantee that all emitted copies are stuck together,
+      // avoiding something bad
+      Flag = Chain.getValue(1);
 
-    MFI->addRetReg(Reg);
+      MFI->addRetReg(Reg);
+    }
   }
 
   if (Flag.getNode() == 0) {

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.h?rev=133732&r1=133731&r2=133732&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.h Thu Jun 23 13:10:03 2011
@@ -25,11 +25,12 @@
   enum NodeType {
     FIRST_NUMBER = ISD::BUILTIN_OP_END,
     READ_PARAM,
+    STORE_PARAM,
     EXIT,
     RET,
     COPY_ADDRESS
   };
-} // namespace PTXISD
+}                               // namespace PTXISD
 
 class PTXTargetLowering : public TargetLowering {
   public:

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=133732&r1=133731&r2=133732&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Thu Jun 23 13:10:03 2011
@@ -180,10 +180,15 @@
 def PTXexit
   : SDNode<"PTXISD::EXIT", SDTNone, [SDNPHasChain]>;
 def PTXret
-  : SDNode<"PTXISD::RET",  SDTNone, [SDNPHasChain]>;
+  : SDNode<"PTXISD::RET",  SDTNone,
+           [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
 def PTXcopyaddress
   : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
 
+def PTXstoreparam
+  : SDNode<"PTXISD::STORE_PARAM", SDTypeProfile<0, 2, [SDTCisVT<0, i32>]>,
+           [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
+
 //===----------------------------------------------------------------------===//
 // Instruction Class Templates
 //===----------------------------------------------------------------------===//
@@ -816,7 +821,7 @@
 defm LDl : PTX_LD_ALL<"ld.local",  load_local>;
 defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
 
-// This is a special instruction that is manually inserted for kernel parameters
+// This is a special instruction that is manually inserted for parameters
 def LDpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
                       "ld.param.u16\t$d, [$a]", []>;
 def LDpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a),
@@ -828,6 +833,23 @@
 def LDpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a),
                       "ld.param.f64\t$d, [$a]", []>;
 
+// def STpiPred : InstPTX<(outs), (ins i1imm:$d, RegPred:$a),
+//                        "st.param.pred\t[$d], $a",
+//                        [(PTXstoreparam imm:$d, RegPred:$a)]>;
+// def STpiU16 : InstPTX<(outs), (ins i16imm:$d, RegI16:$a),
+//                       "st.param.u16\t[$d], $a",
+//                       [(PTXstoreparam imm:$d, RegI16:$a)]>;
+def STpiU32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
+                      "st.param.u32\t[$d], $a",
+                      [(PTXstoreparam timm:$d, RegI32:$a)]>;
+// def STpiU64 : InstPTX<(outs), (ins i64imm:$d, RegI64:$a),
+//                       "st.param.u64\t[$d], $a",
+//                       [(PTXstoreparam imm:$d, RegI64:$a)]>;
+// def STpiF32 : InstPTX<(outs), (ins MEMpi:$d, RegF32:$a),
+//                       "st.param.f32\t[$d], $a", []>;
+// def STpiF64 : InstPTX<(outs), (ins MEMpi:$d, RegF64:$a),
+//                       "st.param.f64\t[$d], $a", []>;
+
 // Stores
 defm STg : PTX_ST_ALL<"st.global", store_global>;
 defm STl : PTX_ST_ALL<"st.local",  store_local>;

Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.h?rev=133732&r1=133731&r2=133732&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXSubtarget.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXSubtarget.h Thu Jun 23 13:10:03 2011
@@ -18,7 +18,7 @@
 
 namespace llvm {
   class PTXSubtarget : public TargetSubtarget {
-    private:
+    public:
 
       /**
        * Enumeration of Shader Models supported by the back-end.
@@ -41,6 +41,8 @@
         PTX_VERSION_2_3   /*< PTX Version 2.3 */
       };
 
+  private:
+
       /// Shader Model supported on the target GPU.
       PTXShaderModelEnum PTXShaderModel;
 
@@ -58,8 +60,10 @@
       bool Is64Bit;
 
     public:
+
       PTXSubtarget(const std::string &TT, const std::string &FS, bool is64Bit);
 
+      // Target architecture accessors
       std::string getTargetString() const;
 
       std::string getPTXVersionString() const;
@@ -80,6 +84,9 @@
 
       bool supportsPTX23() const { return PTXVersion >= PTX_VERSION_2_3; }
 
+      PTXShaderModelEnum getShaderModel() const { return PTXShaderModel; }
+
+
       std::string ParseSubtargetFeatures(const std::string &FS,
                                          const std::string &CPU);
   }; // class PTXSubtarget



From justin.holewinski at gmail.com  Thu Jun 23 13:10:05 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Thu, 23 Jun 2011 18:10:05 -0000
Subject: [llvm-commits] [llvm] r133733 - in /llvm/trunk/lib/Target/PTX:
 PTXAsmPrinter.cpp PTXISelDAGToDAG.cpp PTXISelLowering.cpp PTXISelLowering.h
 PTXInstrInfo.td
Message-ID: <20110623181005.8BAD62A6C12D@llvm.org>

Author: jholewinski
Date: Thu Jun 23 13:10:05 2011
New Revision: 133733

URL: http://llvm.org/viewvc/llvm-project?rev=133733&view=rev
Log:
PTX: Prevent DCE from eliminating st.param calls, and unify the handling of
     st.param and ld.param

FIXME: Test cases still need to be updated

Modified:
    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
    llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp
    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
    llvm/trunk/lib/Target/PTX/PTXISelLowering.h
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.td

Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133733&r1=133732&r2=133733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Thu Jun 23 13:10:05 2011
@@ -63,6 +63,8 @@
                        const char *Modifier = 0);
   void printParamOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
                          const char *Modifier = 0);
+  void printReturnOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
+                          const char *Modifier = 0); 
   void printPredicateOperand(const MachineInstr *MI, raw_ostream &O);
 
   // autogen'd.
@@ -76,6 +78,7 @@
 } // namespace
 
 static const char PARAM_PREFIX[] = "__param_";
+static const char RETURN_PREFIX[] = "__ret_";
 
 static const char *getRegisterTypeName(unsigned RegNo) {
 #define TEST_REGCLS(cls, clsstr)                \
@@ -298,6 +301,11 @@
   OS << PARAM_PREFIX << (int) MI->getOperand(opNum).getImm() + 1;
 }
 
+void PTXAsmPrinter::printReturnOperand(const MachineInstr *MI, int opNum,
+                                       raw_ostream &OS, const char *Modifier) {
+  OS << RETURN_PREFIX << (int) MI->getOperand(opNum).getImm() + 1;
+}
+
 void PTXAsmPrinter::EmitVariableDeclaration(const GlobalVariable *gv) {
   // Check to see if this is a special global used by LLVM, if so, emit it.
   if (EmitSpecialLLVMGlobal(gv))
@@ -421,6 +429,8 @@
 
   std::string decl = isKernel ? ".entry" : ".func";
 
+  unsigned cnt = 0;
+
   if (!isKernel) {
     decl += " (";
 
@@ -430,10 +440,18 @@
       if (i != b) {
         decl += ", ";
       }
-      decl += ".reg .";
-      decl += getRegisterTypeName(*i);
-      decl += " ";
-      decl += getRegisterName(*i);
+      if (ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
+        decl += ".param .b";
+        decl += utostr(*i);
+        decl += " ";
+        decl += RETURN_PREFIX;
+        decl += utostr(++cnt);
+      } else {
+        decl += ".reg .";
+        decl += getRegisterTypeName(*i);
+        decl += " ";
+        decl += getRegisterName(*i);
+      }
     }
     decl += ")";
   }
@@ -444,7 +462,7 @@
 
   decl += " (";
 
-  unsigned cnt = 0;
+  cnt = 0;
 
   // Print parameters
   for (PTXMachineFunctionInfo::reg_iterator

Modified: llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp?rev=133733&r1=133732&r2=133733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelDAGToDAG.cpp Thu Jun 23 13:10:05 2011
@@ -42,9 +42,6 @@
 #include "PTXGenDAGISel.inc"
 
   private:
-    SDNode *SelectREAD_PARAM(SDNode *Node);
-    //SDNode *SelectSTORE_PARAM(SDNode *Node);
-    
     // We need this only because we can't match intruction BRAdp
     // pattern (PTXbrcond bb:$d, ...) in PTXInstrInfo.td
     SDNode *SelectBRCOND(SDNode *Node);
@@ -69,10 +66,6 @@
 
 SDNode *PTXDAGToDAGISel::Select(SDNode *Node) {
   switch (Node->getOpcode()) {
-    case PTXISD::READ_PARAM:
-      return SelectREAD_PARAM(Node);
-    // case PTXISD::STORE_PARAM:
-    //   return SelectSTORE_PARAM(Node);
     case ISD::BRCOND:
       return SelectBRCOND(Node);
     default:
@@ -80,68 +73,6 @@
   }
 }
 
-SDNode *PTXDAGToDAGISel::SelectREAD_PARAM(SDNode *Node) {
-  SDValue  index = Node->getOperand(1);
-  DebugLoc dl    = Node->getDebugLoc();
-  unsigned opcode;
-
-  if (index.getOpcode() != ISD::TargetConstant)
-    llvm_unreachable("READ_PARAM: index is not ISD::TargetConstant");
-
-  if (Node->getValueType(0) == MVT::i16) {
-    opcode = PTX::LDpiU16;
-  } else if (Node->getValueType(0) == MVT::i32) {
-    opcode = PTX::LDpiU32;
-  } else if (Node->getValueType(0) == MVT::i64) {
-    opcode = PTX::LDpiU64;
-  } else if (Node->getValueType(0) == MVT::f32) {
-    opcode = PTX::LDpiF32;
-  } else if (Node->getValueType(0) == MVT::f64) {
-    opcode = PTX::LDpiF64;
-  } else {
-    llvm_unreachable("Unknown parameter type for ld.param");
-  }
-
-  return PTXInstrInfo::
-    GetPTXMachineNode(CurDAG, opcode, dl, Node->getValueType(0), index);
-}
-
-// SDNode *PTXDAGToDAGISel::SelectSTORE_PARAM(SDNode *Node) {
-//   SDValue  Chain = Node->getOperand(0);
-//   SDValue  index = Node->getOperand(1);
-//   SDValue  value = Node->getOperand(2);
-//   DebugLoc dl    = Node->getDebugLoc();
-//   unsigned opcode;
-
-//   if (index.getOpcode() != ISD::TargetConstant)
-//     llvm_unreachable("STORE_PARAM: index is not ISD::TargetConstant");
-
-//   if (value->getValueType(0) == MVT::i16) {
-//     opcode = PTX::STpiU16;
-//   } else if (value->getValueType(0) == MVT::i32) {
-//     opcode = PTX::STpiU32;
-//   } else if (value->getValueType(0) == MVT::i64) {
-//     opcode = PTX::STpiU64;
-//   } else if (value->getValueType(0) == MVT::f32) {
-//     opcode = PTX::STpiF32;
-//   } else if (value->getValueType(0) == MVT::f64) {
-//     opcode = PTX::STpiF64;
-//   } else {
-//     llvm_unreachable("Unknown parameter type for st.param");
-//   }
-
-//   SDVTList VTs = CurDAG->getVTList(MVT::Other, MVT::Glue);
-//   SDValue PredReg = CurDAG->getRegister(PTX::NoRegister, MVT::i1);
-//   SDValue PredOp = CurDAG->getTargetConstant(PTX::PRED_NORMAL, MVT::i32);
-//   SDValue Ops[] = { Chain, index, value, PredReg, PredOp };
-//   //SDNode *RetNode = PTXInstrInfo::
-//   //  GetPTXMachineNode(CurDAG, opcode, dl, VTs, index, value);
-//   SDNode *RetNode = CurDAG->getMachineNode(opcode, dl, VTs, Ops, array_lengthof(Ops));
-//   DEBUG(dbgs() << "SelectSTORE_PARAM: Selected: ");
-//   RetNode->dumpr(CurDAG);
-//   return RetNode;
-// }
-
 SDNode *PTXDAGToDAGISel::SelectBRCOND(SDNode *Node) {
   assert(Node->getNumOperands() >= 3);
 

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=133733&r1=133732&r2=133733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Thu Jun 23 13:10:05 2011
@@ -105,8 +105,8 @@
       llvm_unreachable("Unknown opcode");
     case PTXISD::COPY_ADDRESS:
       return "PTXISD::COPY_ADDRESS";
-    case PTXISD::READ_PARAM:
-      return "PTXISD::READ_PARAM";
+    case PTXISD::LOAD_PARAM:
+      return "PTXISD::LOAD_PARAM";
     case PTXISD::STORE_PARAM:
       return "PTXISD::STORE_PARAM";
     case PTXISD::EXIT:
@@ -215,13 +215,13 @@
   // SM < 2.0               ->  Use registers for arguments
   
   if (MFI->isKernel() || ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
-    // We just need to emit the proper READ_PARAM ISDs
+    // We just need to emit the proper LOAD_PARAM ISDs
     for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
 
       assert((!MFI->isKernel() || Ins[i].VT != MVT::i1) &&
              "Kernels cannot take pred operands");
 
-      SDValue ArgValue = DAG.getNode(PTXISD::READ_PARAM, dl, Ins[i].VT, Chain,
+      SDValue ArgValue = DAG.getNode(PTXISD::LOAD_PARAM, dl, Ins[i].VT, Chain,
                                      DAG.getTargetConstant(i, MVT::i32));
       InVals.push_back(ArgValue);
 

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.h?rev=133733&r1=133732&r2=133733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.h Thu Jun 23 13:10:05 2011
@@ -24,7 +24,7 @@
 namespace PTXISD {
   enum NodeType {
     FIRST_NUMBER = ISD::BUILTIN_OP_END,
-    READ_PARAM,
+    LOAD_PARAM,
     STORE_PARAM,
     EXIT,
     RET,

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=133733&r1=133732&r2=133733&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Thu Jun 23 13:10:05 2011
@@ -163,6 +163,10 @@
   let PrintMethod = "printParamOperand";
   let MIOperandInfo = (ops i32imm);
 }
+def MEMret : Operand<i32> {
+  let PrintMethod = "printReturnOperand";
+  let MIOperandInfo = (ops i32imm);
+}
 
 // Branch & call targets have OtherVT type.
 def brtarget   : Operand<OtherVT>;
@@ -185,6 +189,10 @@
 def PTXcopyaddress
   : SDNode<"PTXISD::COPY_ADDRESS", SDTypeProfile<1, 1, []>, []>;
 
+// Load/store .param space
+def PTXloadparam
+  : SDNode<"PTXISD::LOAD_PARAM", SDTypeProfile<1, 1, [SDTCisVT<1, i32>]>,
+           [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
 def PTXstoreparam
   : SDNode<"PTXISD::STORE_PARAM", SDTypeProfile<0, 2, [SDTCisVT<0, i32>]>,
            [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue]>;
@@ -821,34 +829,48 @@
 defm LDl : PTX_LD_ALL<"ld.local",  load_local>;
 defm LDs : PTX_LD_ALL<"ld.shared", load_shared>;
 
-// This is a special instruction that is manually inserted for parameters
-def LDpiU16 : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
-                      "ld.param.u16\t$d, [$a]", []>;
-def LDpiU32 : InstPTX<(outs RegI32:$d), (ins MEMpi:$a),
-                      "ld.param.u32\t$d, [$a]", []>;
-def LDpiU64 : InstPTX<(outs RegI64:$d), (ins MEMpi:$a),
-                      "ld.param.u64\t$d, [$a]", []>;
-def LDpiF32 : InstPTX<(outs RegF32:$d), (ins MEMpi:$a),
-                      "ld.param.f32\t$d, [$a]", []>;
-def LDpiF64 : InstPTX<(outs RegF64:$d), (ins MEMpi:$a),
-                      "ld.param.f64\t$d, [$a]", []>;
-
-// def STpiPred : InstPTX<(outs), (ins i1imm:$d, RegPred:$a),
-//                        "st.param.pred\t[$d], $a",
-//                        [(PTXstoreparam imm:$d, RegPred:$a)]>;
-// def STpiU16 : InstPTX<(outs), (ins i16imm:$d, RegI16:$a),
-//                       "st.param.u16\t[$d], $a",
-//                       [(PTXstoreparam imm:$d, RegI16:$a)]>;
-def STpiU32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
-                      "st.param.u32\t[$d], $a",
-                      [(PTXstoreparam timm:$d, RegI32:$a)]>;
-// def STpiU64 : InstPTX<(outs), (ins i64imm:$d, RegI64:$a),
-//                       "st.param.u64\t[$d], $a",
-//                       [(PTXstoreparam imm:$d, RegI64:$a)]>;
-// def STpiF32 : InstPTX<(outs), (ins MEMpi:$d, RegF32:$a),
-//                       "st.param.f32\t[$d], $a", []>;
-// def STpiF64 : InstPTX<(outs), (ins MEMpi:$d, RegF64:$a),
-//                       "st.param.f64\t[$d], $a", []>;
+// These instructions are used to load/store from the .param space for
+// device and kernel parameters
+
+let hasSideEffects = 1 in {
+  def LDpiPred : InstPTX<(outs RegPred:$d), (ins MEMpi:$a),
+                         "ld.param.pred\t$d, [$a]",
+                         [(set RegPred:$d, (PTXloadparam timm:$a))]>;
+  def LDpiU16  : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
+                         "ld.param.u16\t$d, [$a]",
+                         [(set RegI16:$d, (PTXloadparam timm:$a))]>;
+  def LDpiU32  : InstPTX<(outs RegI32:$d), (ins MEMpi:$a),
+                         "ld.param.u32\t$d, [$a]",
+                         [(set RegI32:$d, (PTXloadparam timm:$a))]>;
+  def LDpiU64  : InstPTX<(outs RegI64:$d), (ins MEMpi:$a),
+                         "ld.param.u64\t$d, [$a]",
+                         [(set RegI64:$d, (PTXloadparam timm:$a))]>;
+  def LDpiF32  : InstPTX<(outs RegF32:$d), (ins MEMpi:$a),
+                         "ld.param.f32\t$d, [$a]",
+                         [(set RegF32:$d, (PTXloadparam timm:$a))]>;
+  def LDpiF64  : InstPTX<(outs RegF64:$d), (ins MEMpi:$a),
+                         "ld.param.f64\t$d, [$a]",
+                         [(set RegF64:$d, (PTXloadparam timm:$a))]>;
+
+  def STpiPred : InstPTX<(outs), (ins MEMret:$d, RegPred:$a),
+                         "st.param.pred\t[$d], $a",
+                         [(PTXstoreparam timm:$d, RegPred:$a)]>;
+  def STpiU16  : InstPTX<(outs), (ins MEMret:$d, RegI16:$a),
+                         "st.param.u16\t[$d], $a",
+                         [(PTXstoreparam timm:$d, RegI16:$a)]>;
+  def STpiU32  : InstPTX<(outs), (ins MEMret:$d, RegI32:$a),
+                         "st.param.u32\t[$d], $a",
+                         [(PTXstoreparam timm:$d, RegI32:$a)]>;
+  def STpiU64  : InstPTX<(outs), (ins MEMret:$d, RegI64:$a),
+                         "st.param.u64\t[$d], $a",
+                         [(PTXstoreparam timm:$d, RegI64:$a)]>;
+  def STpiF32  : InstPTX<(outs), (ins MEMret:$d, RegF32:$a),
+                         "st.param.f32\t[$d], $a",
+                         [(PTXstoreparam timm:$d, RegF32:$a)]>;
+  def STpiF64  : InstPTX<(outs), (ins MEMret:$d, RegF64:$a),
+                         "st.param.f64\t[$d], $a",
+                         [(PTXstoreparam timm:$d, RegF64:$a)]>;
+}
 
 // Stores
 defm STg : PTX_ST_ALL<"st.global", store_global>;



From justin.holewinski at gmail.com  Thu Jun 23 13:10:07 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Thu, 23 Jun 2011 18:10:07 -0000
Subject: [llvm-commits] [llvm] r133734 - in /llvm/trunk/lib/Target/PTX:
 PTXAsmPrinter.cpp PTXISelLowering.cpp
Message-ID: <20110623181007.57C972A6C12E@llvm.org>

Author: jholewinski
Date: Thu Jun 23 13:10:07 2011
New Revision: 133734

URL: http://llvm.org/viewvc/llvm-project?rev=133734&view=rev
Log:
PTX: Whitespace fixes and remove commented out code

Modified:
    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp

Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133734&r1=133733&r2=133734&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Thu Jun 23 13:10:07 2011
@@ -486,41 +486,6 @@
   }
   decl += ")";
 
-  // // Print parameter list
-  // if (!MFI->argRegEmpty()) {
-  //   decl += " (";
-  //   if (isKernel) {
-  //     unsigned cnt = 0;
-  //     for(PTXMachineFunctionInfo::reg_iterator
-  //         i = MFI->argRegBegin(), e = MFI->argRegEnd(), b = i;
-  //         i != e; ++i) {
-  //       reg = *i;
-  //       assert(reg != PTX::NoRegister && "Not a valid register!");
-  //       if (i != b)
-  //         decl += ", ";
-  //       decl += ".param .";
-  //       decl += getRegisterTypeName(reg);
-  //       decl += " ";
-  //       decl += PARAM_PREFIX;
-  //       decl += utostr(++cnt);
-  //     }
-  //   } else {
-  //     for (PTXMachineFunctionInfo::reg_iterator
-  //          i = MFI->argRegBegin(), e = MFI->argRegEnd(), b = i;
-  //          i != e; ++i) {
-  //       reg = *i;
-  //       assert(reg != PTX::NoRegister && "Not a valid register!");
-  //       if (i != b)
-  //         decl += ", ";
-  //       decl += ".reg .";
-  //       decl += getRegisterTypeName(reg);
-  //       decl += " ";
-  //       decl += getRegisterName(reg);
-  //     }
-  //   }
-  //   decl += ")";
-  // }
-
   OutStreamer.EmitRawText(Twine(decl));
 }
 

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=133734&r1=133733&r2=133734&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Thu Jun 23 13:10:07 2011
@@ -213,7 +213,6 @@
   // We do one of two things here:
   // IsKernel || SM >= 2.0  ->  Use param space for arguments
   // SM < 2.0               ->  Use registers for arguments
-  
   if (MFI->isKernel() || ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
     // We just need to emit the proper LOAD_PARAM ISDs
     for (unsigned i = 0, e = Ins.size(); i != e; ++i) {



From justin.holewinski at gmail.com  Thu Jun 23 13:10:08 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Thu, 23 Jun 2011 18:10:08 -0000
Subject: [llvm-commits] [llvm] r133735 - in /llvm/trunk/test/CodeGen/PTX:
 intrinsic.ll llvm-intrinsic.ll
Message-ID: <20110623181008.E59492A6C12F@llvm.org>

Author: jholewinski
Date: Thu Jun 23 13:10:08 2011
New Revision: 133735

URL: http://llvm.org/viewvc/llvm-project?rev=133735&view=rev
Log:
PTX: Fixup test cases for device param changes

Modified:
    llvm/trunk/test/CodeGen/PTX/intrinsic.ll
    llvm/trunk/test/CodeGen/PTX/llvm-intrinsic.ll

Modified: llvm/trunk/test/CodeGen/PTX/intrinsic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/intrinsic.ll?rev=133735&r1=133734&r2=133735&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/intrinsic.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/intrinsic.ll Thu Jun 23 13:10:08 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20 | FileCheck %s
+; RUN: llc < %s -march=ptx32 -mattr=+ptx20 | FileCheck %s
 
 define ptx_device i32 @test_tid_x() {
 ; CHECK: mov.u32 r0, %tid.x;

Modified: llvm/trunk/test/CodeGen/PTX/llvm-intrinsic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/llvm-intrinsic.ll?rev=133735&r1=133734&r2=133735&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/llvm-intrinsic.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/llvm-intrinsic.ll Thu Jun 23 13:10:08 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=ptx32 -mattr=+ptx20,+sm20 | FileCheck %s
+; RUN: llc < %s -march=ptx32 -mattr=+ptx20 | FileCheck %s
 
 define ptx_device float @test_sqrt_f32(float %x) {
 entry:



From justin.holewinski at gmail.com  Thu Jun 23 13:10:13 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Thu, 23 Jun 2011 18:10:13 -0000
Subject: [llvm-commits] [llvm] r133736 - in /llvm/trunk: lib/Target/PTX/
	test/CodeGen/PTX/
Message-ID: <20110623181013.801072A6C12C@llvm.org>

Author: jholewinski
Date: Thu Jun 23 13:10:13 2011
New Revision: 133736

URL: http://llvm.org/viewvc/llvm-project?rev=133736&view=rev
Log:
PTX: Always use registers for return values, but use .param space for device
     parameters if SM >= 2.0

- Update test cases to be more robust against register allocation changes
- Bump up the number of registers to 128 per type
- Include Python script to re-generate register file with any number of
  registers

Added:
    llvm/trunk/lib/Target/PTX/generate-register-td.py   (with props)
    llvm/trunk/test/CodeGen/PTX/aggregates.ll
Modified:
    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
    llvm/trunk/lib/Target/PTX/PTXCallingConv.td
    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
    llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h
    llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td
    llvm/trunk/test/CodeGen/PTX/add.ll
    llvm/trunk/test/CodeGen/PTX/bitwise.ll
    llvm/trunk/test/CodeGen/PTX/bra.ll
    llvm/trunk/test/CodeGen/PTX/cvt.ll
    llvm/trunk/test/CodeGen/PTX/fdiv-sm10.ll
    llvm/trunk/test/CodeGen/PTX/fdiv-sm13.ll
    llvm/trunk/test/CodeGen/PTX/fneg.ll
    llvm/trunk/test/CodeGen/PTX/ld.ll
    llvm/trunk/test/CodeGen/PTX/llvm-intrinsic.ll
    llvm/trunk/test/CodeGen/PTX/mad.ll
    llvm/trunk/test/CodeGen/PTX/mov.ll
    llvm/trunk/test/CodeGen/PTX/mul.ll
    llvm/trunk/test/CodeGen/PTX/parameter-order.ll
    llvm/trunk/test/CodeGen/PTX/selp.ll
    llvm/trunk/test/CodeGen/PTX/setp.ll
    llvm/trunk/test/CodeGen/PTX/shl.ll
    llvm/trunk/test/CodeGen/PTX/shr.ll
    llvm/trunk/test/CodeGen/PTX/st.ll
    llvm/trunk/test/CodeGen/PTX/sub.ll

Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Thu Jun 23 13:10:13 2011
@@ -433,25 +433,16 @@
 
   if (!isKernel) {
     decl += " (";
-
     for (PTXMachineFunctionInfo::ret_iterator
          i = MFI->retRegBegin(), e = MFI->retRegEnd(), b = i;
          i != e; ++i) {
       if (i != b) {
         decl += ", ";
       }
-      if (ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
-        decl += ".param .b";
-        decl += utostr(*i);
-        decl += " ";
-        decl += RETURN_PREFIX;
-        decl += utostr(++cnt);
-      } else {
-        decl += ".reg .";
-        decl += getRegisterTypeName(*i);
-        decl += " ";
-        decl += getRegisterName(*i);
-      }
+      decl += ".reg .";
+      decl += getRegisterTypeName(*i);
+      decl += " ";
+      decl += getRegisterName(*i);
     }
     decl += ")";
   }

Modified: llvm/trunk/lib/Target/PTX/PTXCallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXCallingConv.td?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXCallingConv.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXCallingConv.td Thu Jun 23 13:10:13 2011
@@ -1,3 +1,4 @@
+
 //===--- PTXCallingConv.td - Calling Conventions -----------*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
@@ -11,26 +12,18 @@
 //
 //===----------------------------------------------------------------------===//
 
-// Currently, we reserve one register of each type for return values and let
-// the rest be used for parameters.  This is a dirty hack, but I am not sure
-// how to tell LLVM that registers used for parameter passing cannot be used
-// for return values.
-
-// PTX Calling Conventions
+// PTX Formal Parameter Calling Convention
 def CC_PTX : CallingConv<[
-  CCIfType<[i1], CCAssignToReg<[P1, P2, P3, P4, P5, P6, P7]>>,
-  CCIfType<[i16], CCAssignToReg<[RH1, RH2, RH3, RH4, RH5, RH6, RH7]>>,
-  CCIfType<[i32, f32], CCAssignToReg<[R1, R2, R3, R4, R5, R6, R7]>>,
-  CCIfType<[i64, f64], CCAssignToReg<[RD1, RD2, RD3, RD4, RD5, RD6, RD7]>>
+  CCIfType<[i1],      CCAssignToReg<[P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, P36, P37, P38, P39, P40, P41, P42, P43, P44, P45, P46, P47, P48, P49, P50, P51, P52, P53, P54, P55, P56, P57, P58, P59, P60, P61, P62, P63, P64, P65, P66, P67, P68, P69, P70, P71, P72, P73, P74, P75, P76, P77, P78, P79, P80, P81, P82, P83, P84, P85, P86, P87, P88, P89, P90, P91, P92, P93, P94, P95, P96, P97, P98, P99, P100, P101, P102, P103, P104, P105, P106, P107, P108, P109, P110, P111, P112, P113, P114, P115, P116, P117, P118, P119, P120, P121, P122, P123, P124, P125, P126, P127]>>,
+  CCIfType<[i16],     CCAssignToReg<[RH12, RH13, RH14, RH15, RH16, RH17, RH18, RH19, RH20, RH21, RH22, RH23, RH24, RH25, RH26, RH27, RH28, RH29, RH30, RH31, RH32, RH33, RH34, RH35, RH36, RH37, RH38, RH39, RH40, RH41, RH42, RH43, RH44, RH45, RH46, RH47, RH48, RH49, RH50, RH51, RH52, RH53, RH54, RH55, RH56, RH57, RH58, RH59, RH60, RH61, RH62, RH63, RH64, RH65, RH66, RH67, RH68, RH69, RH70, RH71, RH72, RH73, RH74, RH75, RH76, RH77, RH78, RH79, RH80, RH81, RH82, RH83, RH84, RH85, RH86, RH87, RH88, RH89, RH90, RH91, RH92, RH93, RH94, RH95, RH96, RH97, RH98, RH99, RH100, RH101, RH102, RH103, RH104, RH105, RH106, RH107, RH108, RH109, RH110, RH111, RH112, RH113, RH114, RH115, RH116, RH117, RH118, RH119, RH120, RH121, RH122, RH123, RH124, RH125, RH126, RH127]>>,
+  CCIfType<[i32,f32], CCAssignToReg<[R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127]>>,
+  CCIfType<[i64,f64], CCAssignToReg<[RD12, RD13, RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26, RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35, RD36, RD37, RD38, RD39, RD40, RD41, RD42, RD43, RD44, RD45, RD46, RD47, RD48, RD49, RD50, RD51, RD52, RD53, RD54, RD55, RD56, RD57, RD58, RD59, RD60, RD61, RD62, RD63, RD64, RD65, RD66, RD67, RD68, RD69, RD70, RD71, RD72, RD73, RD74, RD75, RD76, RD77, RD78, RD79, RD80, RD81, RD82, RD83, RD84, RD85, RD86, RD87, RD88, RD89, RD90, RD91, RD92, RD93, RD94, RD95, RD96, RD97, RD98, RD99, RD100, RD101, RD102, RD103, RD104, RD105, RD106, RD107, RD108, RD109, RD110, RD111, RD112, RD113, RD114, RD115, RD116, RD117, RD118, RD119, RD120, RD121, RD122, RD123, RD124, RD125, RD126, RD127]>>
 ]>;
 
-//===----------------------------------------------------------------------===//
-// Return Value Calling Conventions
-//===----------------------------------------------------------------------===//
-
+// PTX Return Value Calling Convention
 def RetCC_PTX : CallingConv<[
-  CCIfType<[i1], CCAssignToReg<[P0]>>,
-  CCIfType<[i16], CCAssignToReg<[RH0]>>,
-  CCIfType<[i32, f32], CCAssignToReg<[R0]>>,
-  CCIfType<[i64, f64], CCAssignToReg<[RD0]>>
+  CCIfType<[i1],      CCAssignToReg<[P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11]>>,
+  CCIfType<[i16],     CCAssignToReg<[RH0, RH1, RH2, RH3, RH4, RH5, RH6, RH7, RH8, RH9, RH10, RH11]>>,
+  CCIfType<[i32,f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11]>>,
+  CCIfType<[i64,f64], CCAssignToReg<[RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11]>>
 ]>;

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Thu Jun 23 13:10:13 2011
@@ -307,49 +307,35 @@
 
   MachineFunction& MF = DAG.getMachineFunction();
   PTXMachineFunctionInfo *MFI = MF.getInfo<PTXMachineFunctionInfo>();
-  const PTXSubtarget& ST = getTargetMachine().getSubtarget<PTXSubtarget>();
 
   SDValue Flag;
 
-  if (ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
-    // For SM 2.0+, we return arguments in the param space
-    for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
-      SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
-      SDValue ParamIndex = DAG.getTargetConstant(i, MVT::i32);
-      SDValue Ops[] = { Chain, ParamIndex, OutVals[i], Flag };
-      Chain = DAG.getNode(PTXISD::STORE_PARAM, dl, VTs, Ops,
-                          Flag.getNode() ? 4 : 3);
-      Flag = Chain.getValue(1);
-      // Instead of storing a physical register in our argument list, we just
-      // store the total size of the parameter, in bits.  The ASM printer
-      // knows how to process this.
-      MFI->addRetReg(Outs[i].VT.getStoreSizeInBits());
-    }
-  } else {
-    // For SM < 2.0, we return arguments in registers
-    SmallVector<CCValAssign, 16> RVLocs;
-    CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
-    getTargetMachine(), RVLocs, *DAG.getContext());
-
-    CCInfo.AnalyzeReturn(Outs, RetCC_PTX);
-
-    for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
-      CCValAssign& VA  = RVLocs[i];
-
-      assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
-
-      unsigned Reg = VA.getLocReg();
-
-      DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
-
-      Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag);
-
-      // Guarantee that all emitted copies are stuck together,
-      // avoiding something bad
-      Flag = Chain.getValue(1);
+  // Even though we could use the .param space for return arguments for
+  // device functions if SM >= 2.0 and the number of return arguments is
+  // only 1, we just always use registers since this makes the codegen
+  // easier.
+  SmallVector<CCValAssign, 16> RVLocs;
+  CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
+  getTargetMachine(), RVLocs, *DAG.getContext());
 
-      MFI->addRetReg(Reg);
-    }
+  CCInfo.AnalyzeReturn(Outs, RetCC_PTX);
+
+  for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
+    CCValAssign& VA  = RVLocs[i];
+
+    assert(VA.isRegLoc() && "CCValAssign must be RegLoc");
+
+    unsigned Reg = VA.getLocReg();
+
+    DAG.getMachineFunction().getRegInfo().addLiveOut(Reg);
+
+    Chain = DAG.getCopyToReg(Chain, dl, Reg, OutVals[i], Flag);
+
+    // Guarantee that all emitted copies are stuck together,
+    // avoiding something bad
+    Flag = Chain.getValue(1);
+
+    MFI->addRetReg(Reg);
   }
 
   if (Flag.getNode() == 0) {

Modified: llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXMachineFunctionInfo.h Thu Jun 23 13:10:13 2011
@@ -26,7 +26,7 @@
 private:
   bool is_kernel;
   std::vector<unsigned> reg_arg, reg_local_var;
-  DenseSet<unsigned> reg_ret;
+  std::vector<unsigned> reg_ret;
   bool _isDoneAddArg;
 
 public:
@@ -40,7 +40,11 @@
 
   void addArgReg(unsigned reg) { reg_arg.push_back(reg); }
   void addLocalVarReg(unsigned reg) { reg_local_var.push_back(reg); }
-  void addRetReg(unsigned reg) { reg_ret.insert(reg); }
+  void addRetReg(unsigned reg) {
+    if (!isRetReg(reg)) {
+      reg_ret.push_back(reg);
+    }
+  }
 
   void doneAddArg(void) {
     _isDoneAddArg = true;
@@ -51,7 +55,7 @@
 
   typedef std::vector<unsigned>::const_iterator         reg_iterator;
   typedef std::vector<unsigned>::const_reverse_iterator reg_reverse_iterator;
-  typedef DenseSet<unsigned>::const_iterator            ret_iterator;
+  typedef std::vector<unsigned>::const_iterator         ret_iterator;
 
   bool         argRegEmpty() const { return reg_arg.empty(); }
   int          getNumArg() const { return reg_arg.size(); }

Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td Thu Jun 23 13:10:13 2011
@@ -1,3 +1,4 @@
+
 //===- PTXRegisterInfo.td - PTX Register defs ----------------*- tblgen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
@@ -21,55 +22,534 @@
 
 ///===- Predicate Registers -----------------------------------------------===//
 
-def P0  : PTXReg<"p0">;
-def P1  : PTXReg<"p1">;
-def P2  : PTXReg<"p2">;
-def P3  : PTXReg<"p3">;
-def P4  : PTXReg<"p4">;
-def P5  : PTXReg<"p5">;
-def P6  : PTXReg<"p6">;
-def P7  : PTXReg<"p7">;
-
-///===- 16-bit Integer Registers ------------------------------------------===//
-
-def RH0  : PTXReg<"rh0">;
-def RH1  : PTXReg<"rh1">;
-def RH2  : PTXReg<"rh2">;
-def RH3  : PTXReg<"rh3">;
-def RH4  : PTXReg<"rh4">;
-def RH5  : PTXReg<"rh5">;
-def RH6  : PTXReg<"rh6">;
-def RH7  : PTXReg<"rh7">;
-
-///===- 32-bit Integer Registers ------------------------------------------===//
-
-def R0  : PTXReg<"r0">;
-def R1  : PTXReg<"r1">;
-def R2  : PTXReg<"r2">;
-def R3  : PTXReg<"r3">;
-def R4  : PTXReg<"r4">;
-def R5  : PTXReg<"r5">;
-def R6  : PTXReg<"r6">;
-def R7  : PTXReg<"r7">;
-
-///===- 64-bit Integer Registers ------------------------------------------===//
-
-def RD0  : PTXReg<"rd0">;
-def RD1  : PTXReg<"rd1">;
-def RD2  : PTXReg<"rd2">;
-def RD3  : PTXReg<"rd3">;
-def RD4  : PTXReg<"rd4">;
-def RD5  : PTXReg<"rd5">;
-def RD6  : PTXReg<"rd6">;
-def RD7  : PTXReg<"rd7">;
+def P0 : PTXReg<"p0">;
+def P1 : PTXReg<"p1">;
+def P2 : PTXReg<"p2">;
+def P3 : PTXReg<"p3">;
+def P4 : PTXReg<"p4">;
+def P5 : PTXReg<"p5">;
+def P6 : PTXReg<"p6">;
+def P7 : PTXReg<"p7">;
+def P8 : PTXReg<"p8">;
+def P9 : PTXReg<"p9">;
+def P10 : PTXReg<"p10">;
+def P11 : PTXReg<"p11">;
+def P12 : PTXReg<"p12">;
+def P13 : PTXReg<"p13">;
+def P14 : PTXReg<"p14">;
+def P15 : PTXReg<"p15">;
+def P16 : PTXReg<"p16">;
+def P17 : PTXReg<"p17">;
+def P18 : PTXReg<"p18">;
+def P19 : PTXReg<"p19">;
+def P20 : PTXReg<"p20">;
+def P21 : PTXReg<"p21">;
+def P22 : PTXReg<"p22">;
+def P23 : PTXReg<"p23">;
+def P24 : PTXReg<"p24">;
+def P25 : PTXReg<"p25">;
+def P26 : PTXReg<"p26">;
+def P27 : PTXReg<"p27">;
+def P28 : PTXReg<"p28">;
+def P29 : PTXReg<"p29">;
+def P30 : PTXReg<"p30">;
+def P31 : PTXReg<"p31">;
+def P32 : PTXReg<"p32">;
+def P33 : PTXReg<"p33">;
+def P34 : PTXReg<"p34">;
+def P35 : PTXReg<"p35">;
+def P36 : PTXReg<"p36">;
+def P37 : PTXReg<"p37">;
+def P38 : PTXReg<"p38">;
+def P39 : PTXReg<"p39">;
+def P40 : PTXReg<"p40">;
+def P41 : PTXReg<"p41">;
+def P42 : PTXReg<"p42">;
+def P43 : PTXReg<"p43">;
+def P44 : PTXReg<"p44">;
+def P45 : PTXReg<"p45">;
+def P46 : PTXReg<"p46">;
+def P47 : PTXReg<"p47">;
+def P48 : PTXReg<"p48">;
+def P49 : PTXReg<"p49">;
+def P50 : PTXReg<"p50">;
+def P51 : PTXReg<"p51">;
+def P52 : PTXReg<"p52">;
+def P53 : PTXReg<"p53">;
+def P54 : PTXReg<"p54">;
+def P55 : PTXReg<"p55">;
+def P56 : PTXReg<"p56">;
+def P57 : PTXReg<"p57">;
+def P58 : PTXReg<"p58">;
+def P59 : PTXReg<"p59">;
+def P60 : PTXReg<"p60">;
+def P61 : PTXReg<"p61">;
+def P62 : PTXReg<"p62">;
+def P63 : PTXReg<"p63">;
+def P64 : PTXReg<"p64">;
+def P65 : PTXReg<"p65">;
+def P66 : PTXReg<"p66">;
+def P67 : PTXReg<"p67">;
+def P68 : PTXReg<"p68">;
+def P69 : PTXReg<"p69">;
+def P70 : PTXReg<"p70">;
+def P71 : PTXReg<"p71">;
+def P72 : PTXReg<"p72">;
+def P73 : PTXReg<"p73">;
+def P74 : PTXReg<"p74">;
+def P75 : PTXReg<"p75">;
+def P76 : PTXReg<"p76">;
+def P77 : PTXReg<"p77">;
+def P78 : PTXReg<"p78">;
+def P79 : PTXReg<"p79">;
+def P80 : PTXReg<"p80">;
+def P81 : PTXReg<"p81">;
+def P82 : PTXReg<"p82">;
+def P83 : PTXReg<"p83">;
+def P84 : PTXReg<"p84">;
+def P85 : PTXReg<"p85">;
+def P86 : PTXReg<"p86">;
+def P87 : PTXReg<"p87">;
+def P88 : PTXReg<"p88">;
+def P89 : PTXReg<"p89">;
+def P90 : PTXReg<"p90">;
+def P91 : PTXReg<"p91">;
+def P92 : PTXReg<"p92">;
+def P93 : PTXReg<"p93">;
+def P94 : PTXReg<"p94">;
+def P95 : PTXReg<"p95">;
+def P96 : PTXReg<"p96">;
+def P97 : PTXReg<"p97">;
+def P98 : PTXReg<"p98">;
+def P99 : PTXReg<"p99">;
+def P100 : PTXReg<"p100">;
+def P101 : PTXReg<"p101">;
+def P102 : PTXReg<"p102">;
+def P103 : PTXReg<"p103">;
+def P104 : PTXReg<"p104">;
+def P105 : PTXReg<"p105">;
+def P106 : PTXReg<"p106">;
+def P107 : PTXReg<"p107">;
+def P108 : PTXReg<"p108">;
+def P109 : PTXReg<"p109">;
+def P110 : PTXReg<"p110">;
+def P111 : PTXReg<"p111">;
+def P112 : PTXReg<"p112">;
+def P113 : PTXReg<"p113">;
+def P114 : PTXReg<"p114">;
+def P115 : PTXReg<"p115">;
+def P116 : PTXReg<"p116">;
+def P117 : PTXReg<"p117">;
+def P118 : PTXReg<"p118">;
+def P119 : PTXReg<"p119">;
+def P120 : PTXReg<"p120">;
+def P121 : PTXReg<"p121">;
+def P122 : PTXReg<"p122">;
+def P123 : PTXReg<"p123">;
+def P124 : PTXReg<"p124">;
+def P125 : PTXReg<"p125">;
+def P126 : PTXReg<"p126">;
+def P127 : PTXReg<"p127">;
+
+///===- 16-Bit Registers --------------------------------------------------===//
+
+def RH0 : PTXReg<"rh0">;
+def RH1 : PTXReg<"rh1">;
+def RH2 : PTXReg<"rh2">;
+def RH3 : PTXReg<"rh3">;
+def RH4 : PTXReg<"rh4">;
+def RH5 : PTXReg<"rh5">;
+def RH6 : PTXReg<"rh6">;
+def RH7 : PTXReg<"rh7">;
+def RH8 : PTXReg<"rh8">;
+def RH9 : PTXReg<"rh9">;
+def RH10 : PTXReg<"rh10">;
+def RH11 : PTXReg<"rh11">;
+def RH12 : PTXReg<"rh12">;
+def RH13 : PTXReg<"rh13">;
+def RH14 : PTXReg<"rh14">;
+def RH15 : PTXReg<"rh15">;
+def RH16 : PTXReg<"rh16">;
+def RH17 : PTXReg<"rh17">;
+def RH18 : PTXReg<"rh18">;
+def RH19 : PTXReg<"rh19">;
+def RH20 : PTXReg<"rh20">;
+def RH21 : PTXReg<"rh21">;
+def RH22 : PTXReg<"rh22">;
+def RH23 : PTXReg<"rh23">;
+def RH24 : PTXReg<"rh24">;
+def RH25 : PTXReg<"rh25">;
+def RH26 : PTXReg<"rh26">;
+def RH27 : PTXReg<"rh27">;
+def RH28 : PTXReg<"rh28">;
+def RH29 : PTXReg<"rh29">;
+def RH30 : PTXReg<"rh30">;
+def RH31 : PTXReg<"rh31">;
+def RH32 : PTXReg<"rh32">;
+def RH33 : PTXReg<"rh33">;
+def RH34 : PTXReg<"rh34">;
+def RH35 : PTXReg<"rh35">;
+def RH36 : PTXReg<"rh36">;
+def RH37 : PTXReg<"rh37">;
+def RH38 : PTXReg<"rh38">;
+def RH39 : PTXReg<"rh39">;
+def RH40 : PTXReg<"rh40">;
+def RH41 : PTXReg<"rh41">;
+def RH42 : PTXReg<"rh42">;
+def RH43 : PTXReg<"rh43">;
+def RH44 : PTXReg<"rh44">;
+def RH45 : PTXReg<"rh45">;
+def RH46 : PTXReg<"rh46">;
+def RH47 : PTXReg<"rh47">;
+def RH48 : PTXReg<"rh48">;
+def RH49 : PTXReg<"rh49">;
+def RH50 : PTXReg<"rh50">;
+def RH51 : PTXReg<"rh51">;
+def RH52 : PTXReg<"rh52">;
+def RH53 : PTXReg<"rh53">;
+def RH54 : PTXReg<"rh54">;
+def RH55 : PTXReg<"rh55">;
+def RH56 : PTXReg<"rh56">;
+def RH57 : PTXReg<"rh57">;
+def RH58 : PTXReg<"rh58">;
+def RH59 : PTXReg<"rh59">;
+def RH60 : PTXReg<"rh60">;
+def RH61 : PTXReg<"rh61">;
+def RH62 : PTXReg<"rh62">;
+def RH63 : PTXReg<"rh63">;
+def RH64 : PTXReg<"rh64">;
+def RH65 : PTXReg<"rh65">;
+def RH66 : PTXReg<"rh66">;
+def RH67 : PTXReg<"rh67">;
+def RH68 : PTXReg<"rh68">;
+def RH69 : PTXReg<"rh69">;
+def RH70 : PTXReg<"rh70">;
+def RH71 : PTXReg<"rh71">;
+def RH72 : PTXReg<"rh72">;
+def RH73 : PTXReg<"rh73">;
+def RH74 : PTXReg<"rh74">;
+def RH75 : PTXReg<"rh75">;
+def RH76 : PTXReg<"rh76">;
+def RH77 : PTXReg<"rh77">;
+def RH78 : PTXReg<"rh78">;
+def RH79 : PTXReg<"rh79">;
+def RH80 : PTXReg<"rh80">;
+def RH81 : PTXReg<"rh81">;
+def RH82 : PTXReg<"rh82">;
+def RH83 : PTXReg<"rh83">;
+def RH84 : PTXReg<"rh84">;
+def RH85 : PTXReg<"rh85">;
+def RH86 : PTXReg<"rh86">;
+def RH87 : PTXReg<"rh87">;
+def RH88 : PTXReg<"rh88">;
+def RH89 : PTXReg<"rh89">;
+def RH90 : PTXReg<"rh90">;
+def RH91 : PTXReg<"rh91">;
+def RH92 : PTXReg<"rh92">;
+def RH93 : PTXReg<"rh93">;
+def RH94 : PTXReg<"rh94">;
+def RH95 : PTXReg<"rh95">;
+def RH96 : PTXReg<"rh96">;
+def RH97 : PTXReg<"rh97">;
+def RH98 : PTXReg<"rh98">;
+def RH99 : PTXReg<"rh99">;
+def RH100 : PTXReg<"rh100">;
+def RH101 : PTXReg<"rh101">;
+def RH102 : PTXReg<"rh102">;
+def RH103 : PTXReg<"rh103">;
+def RH104 : PTXReg<"rh104">;
+def RH105 : PTXReg<"rh105">;
+def RH106 : PTXReg<"rh106">;
+def RH107 : PTXReg<"rh107">;
+def RH108 : PTXReg<"rh108">;
+def RH109 : PTXReg<"rh109">;
+def RH110 : PTXReg<"rh110">;
+def RH111 : PTXReg<"rh111">;
+def RH112 : PTXReg<"rh112">;
+def RH113 : PTXReg<"rh113">;
+def RH114 : PTXReg<"rh114">;
+def RH115 : PTXReg<"rh115">;
+def RH116 : PTXReg<"rh116">;
+def RH117 : PTXReg<"rh117">;
+def RH118 : PTXReg<"rh118">;
+def RH119 : PTXReg<"rh119">;
+def RH120 : PTXReg<"rh120">;
+def RH121 : PTXReg<"rh121">;
+def RH122 : PTXReg<"rh122">;
+def RH123 : PTXReg<"rh123">;
+def RH124 : PTXReg<"rh124">;
+def RH125 : PTXReg<"rh125">;
+def RH126 : PTXReg<"rh126">;
+def RH127 : PTXReg<"rh127">;
+
+///===- 32-Bit Registers --------------------------------------------------===//
+
+def R0 : PTXReg<"r0">;
+def R1 : PTXReg<"r1">;
+def R2 : PTXReg<"r2">;
+def R3 : PTXReg<"r3">;
+def R4 : PTXReg<"r4">;
+def R5 : PTXReg<"r5">;
+def R6 : PTXReg<"r6">;
+def R7 : PTXReg<"r7">;
+def R8 : PTXReg<"r8">;
+def R9 : PTXReg<"r9">;
+def R10 : PTXReg<"r10">;
+def R11 : PTXReg<"r11">;
+def R12 : PTXReg<"r12">;
+def R13 : PTXReg<"r13">;
+def R14 : PTXReg<"r14">;
+def R15 : PTXReg<"r15">;
+def R16 : PTXReg<"r16">;
+def R17 : PTXReg<"r17">;
+def R18 : PTXReg<"r18">;
+def R19 : PTXReg<"r19">;
+def R20 : PTXReg<"r20">;
+def R21 : PTXReg<"r21">;
+def R22 : PTXReg<"r22">;
+def R23 : PTXReg<"r23">;
+def R24 : PTXReg<"r24">;
+def R25 : PTXReg<"r25">;
+def R26 : PTXReg<"r26">;
+def R27 : PTXReg<"r27">;
+def R28 : PTXReg<"r28">;
+def R29 : PTXReg<"r29">;
+def R30 : PTXReg<"r30">;
+def R31 : PTXReg<"r31">;
+def R32 : PTXReg<"r32">;
+def R33 : PTXReg<"r33">;
+def R34 : PTXReg<"r34">;
+def R35 : PTXReg<"r35">;
+def R36 : PTXReg<"r36">;
+def R37 : PTXReg<"r37">;
+def R38 : PTXReg<"r38">;
+def R39 : PTXReg<"r39">;
+def R40 : PTXReg<"r40">;
+def R41 : PTXReg<"r41">;
+def R42 : PTXReg<"r42">;
+def R43 : PTXReg<"r43">;
+def R44 : PTXReg<"r44">;
+def R45 : PTXReg<"r45">;
+def R46 : PTXReg<"r46">;
+def R47 : PTXReg<"r47">;
+def R48 : PTXReg<"r48">;
+def R49 : PTXReg<"r49">;
+def R50 : PTXReg<"r50">;
+def R51 : PTXReg<"r51">;
+def R52 : PTXReg<"r52">;
+def R53 : PTXReg<"r53">;
+def R54 : PTXReg<"r54">;
+def R55 : PTXReg<"r55">;
+def R56 : PTXReg<"r56">;
+def R57 : PTXReg<"r57">;
+def R58 : PTXReg<"r58">;
+def R59 : PTXReg<"r59">;
+def R60 : PTXReg<"r60">;
+def R61 : PTXReg<"r61">;
+def R62 : PTXReg<"r62">;
+def R63 : PTXReg<"r63">;
+def R64 : PTXReg<"r64">;
+def R65 : PTXReg<"r65">;
+def R66 : PTXReg<"r66">;
+def R67 : PTXReg<"r67">;
+def R68 : PTXReg<"r68">;
+def R69 : PTXReg<"r69">;
+def R70 : PTXReg<"r70">;
+def R71 : PTXReg<"r71">;
+def R72 : PTXReg<"r72">;
+def R73 : PTXReg<"r73">;
+def R74 : PTXReg<"r74">;
+def R75 : PTXReg<"r75">;
+def R76 : PTXReg<"r76">;
+def R77 : PTXReg<"r77">;
+def R78 : PTXReg<"r78">;
+def R79 : PTXReg<"r79">;
+def R80 : PTXReg<"r80">;
+def R81 : PTXReg<"r81">;
+def R82 : PTXReg<"r82">;
+def R83 : PTXReg<"r83">;
+def R84 : PTXReg<"r84">;
+def R85 : PTXReg<"r85">;
+def R86 : PTXReg<"r86">;
+def R87 : PTXReg<"r87">;
+def R88 : PTXReg<"r88">;
+def R89 : PTXReg<"r89">;
+def R90 : PTXReg<"r90">;
+def R91 : PTXReg<"r91">;
+def R92 : PTXReg<"r92">;
+def R93 : PTXReg<"r93">;
+def R94 : PTXReg<"r94">;
+def R95 : PTXReg<"r95">;
+def R96 : PTXReg<"r96">;
+def R97 : PTXReg<"r97">;
+def R98 : PTXReg<"r98">;
+def R99 : PTXReg<"r99">;
+def R100 : PTXReg<"r100">;
+def R101 : PTXReg<"r101">;
+def R102 : PTXReg<"r102">;
+def R103 : PTXReg<"r103">;
+def R104 : PTXReg<"r104">;
+def R105 : PTXReg<"r105">;
+def R106 : PTXReg<"r106">;
+def R107 : PTXReg<"r107">;
+def R108 : PTXReg<"r108">;
+def R109 : PTXReg<"r109">;
+def R110 : PTXReg<"r110">;
+def R111 : PTXReg<"r111">;
+def R112 : PTXReg<"r112">;
+def R113 : PTXReg<"r113">;
+def R114 : PTXReg<"r114">;
+def R115 : PTXReg<"r115">;
+def R116 : PTXReg<"r116">;
+def R117 : PTXReg<"r117">;
+def R118 : PTXReg<"r118">;
+def R119 : PTXReg<"r119">;
+def R120 : PTXReg<"r120">;
+def R121 : PTXReg<"r121">;
+def R122 : PTXReg<"r122">;
+def R123 : PTXReg<"r123">;
+def R124 : PTXReg<"r124">;
+def R125 : PTXReg<"r125">;
+def R126 : PTXReg<"r126">;
+def R127 : PTXReg<"r127">;
+
+///===- 64-Bit Registers --------------------------------------------------===//
+
+def RD0 : PTXReg<"rd0">;
+def RD1 : PTXReg<"rd1">;
+def RD2 : PTXReg<"rd2">;
+def RD3 : PTXReg<"rd3">;
+def RD4 : PTXReg<"rd4">;
+def RD5 : PTXReg<"rd5">;
+def RD6 : PTXReg<"rd6">;
+def RD7 : PTXReg<"rd7">;
+def RD8 : PTXReg<"rd8">;
+def RD9 : PTXReg<"rd9">;
+def RD10 : PTXReg<"rd10">;
+def RD11 : PTXReg<"rd11">;
+def RD12 : PTXReg<"rd12">;
+def RD13 : PTXReg<"rd13">;
+def RD14 : PTXReg<"rd14">;
+def RD15 : PTXReg<"rd15">;
+def RD16 : PTXReg<"rd16">;
+def RD17 : PTXReg<"rd17">;
+def RD18 : PTXReg<"rd18">;
+def RD19 : PTXReg<"rd19">;
+def RD20 : PTXReg<"rd20">;
+def RD21 : PTXReg<"rd21">;
+def RD22 : PTXReg<"rd22">;
+def RD23 : PTXReg<"rd23">;
+def RD24 : PTXReg<"rd24">;
+def RD25 : PTXReg<"rd25">;
+def RD26 : PTXReg<"rd26">;
+def RD27 : PTXReg<"rd27">;
+def RD28 : PTXReg<"rd28">;
+def RD29 : PTXReg<"rd29">;
+def RD30 : PTXReg<"rd30">;
+def RD31 : PTXReg<"rd31">;
+def RD32 : PTXReg<"rd32">;
+def RD33 : PTXReg<"rd33">;
+def RD34 : PTXReg<"rd34">;
+def RD35 : PTXReg<"rd35">;
+def RD36 : PTXReg<"rd36">;
+def RD37 : PTXReg<"rd37">;
+def RD38 : PTXReg<"rd38">;
+def RD39 : PTXReg<"rd39">;
+def RD40 : PTXReg<"rd40">;
+def RD41 : PTXReg<"rd41">;
+def RD42 : PTXReg<"rd42">;
+def RD43 : PTXReg<"rd43">;
+def RD44 : PTXReg<"rd44">;
+def RD45 : PTXReg<"rd45">;
+def RD46 : PTXReg<"rd46">;
+def RD47 : PTXReg<"rd47">;
+def RD48 : PTXReg<"rd48">;
+def RD49 : PTXReg<"rd49">;
+def RD50 : PTXReg<"rd50">;
+def RD51 : PTXReg<"rd51">;
+def RD52 : PTXReg<"rd52">;
+def RD53 : PTXReg<"rd53">;
+def RD54 : PTXReg<"rd54">;
+def RD55 : PTXReg<"rd55">;
+def RD56 : PTXReg<"rd56">;
+def RD57 : PTXReg<"rd57">;
+def RD58 : PTXReg<"rd58">;
+def RD59 : PTXReg<"rd59">;
+def RD60 : PTXReg<"rd60">;
+def RD61 : PTXReg<"rd61">;
+def RD62 : PTXReg<"rd62">;
+def RD63 : PTXReg<"rd63">;
+def RD64 : PTXReg<"rd64">;
+def RD65 : PTXReg<"rd65">;
+def RD66 : PTXReg<"rd66">;
+def RD67 : PTXReg<"rd67">;
+def RD68 : PTXReg<"rd68">;
+def RD69 : PTXReg<"rd69">;
+def RD70 : PTXReg<"rd70">;
+def RD71 : PTXReg<"rd71">;
+def RD72 : PTXReg<"rd72">;
+def RD73 : PTXReg<"rd73">;
+def RD74 : PTXReg<"rd74">;
+def RD75 : PTXReg<"rd75">;
+def RD76 : PTXReg<"rd76">;
+def RD77 : PTXReg<"rd77">;
+def RD78 : PTXReg<"rd78">;
+def RD79 : PTXReg<"rd79">;
+def RD80 : PTXReg<"rd80">;
+def RD81 : PTXReg<"rd81">;
+def RD82 : PTXReg<"rd82">;
+def RD83 : PTXReg<"rd83">;
+def RD84 : PTXReg<"rd84">;
+def RD85 : PTXReg<"rd85">;
+def RD86 : PTXReg<"rd86">;
+def RD87 : PTXReg<"rd87">;
+def RD88 : PTXReg<"rd88">;
+def RD89 : PTXReg<"rd89">;
+def RD90 : PTXReg<"rd90">;
+def RD91 : PTXReg<"rd91">;
+def RD92 : PTXReg<"rd92">;
+def RD93 : PTXReg<"rd93">;
+def RD94 : PTXReg<"rd94">;
+def RD95 : PTXReg<"rd95">;
+def RD96 : PTXReg<"rd96">;
+def RD97 : PTXReg<"rd97">;
+def RD98 : PTXReg<"rd98">;
+def RD99 : PTXReg<"rd99">;
+def RD100 : PTXReg<"rd100">;
+def RD101 : PTXReg<"rd101">;
+def RD102 : PTXReg<"rd102">;
+def RD103 : PTXReg<"rd103">;
+def RD104 : PTXReg<"rd104">;
+def RD105 : PTXReg<"rd105">;
+def RD106 : PTXReg<"rd106">;
+def RD107 : PTXReg<"rd107">;
+def RD108 : PTXReg<"rd108">;
+def RD109 : PTXReg<"rd109">;
+def RD110 : PTXReg<"rd110">;
+def RD111 : PTXReg<"rd111">;
+def RD112 : PTXReg<"rd112">;
+def RD113 : PTXReg<"rd113">;
+def RD114 : PTXReg<"rd114">;
+def RD115 : PTXReg<"rd115">;
+def RD116 : PTXReg<"rd116">;
+def RD117 : PTXReg<"rd117">;
+def RD118 : PTXReg<"rd118">;
+def RD119 : PTXReg<"rd119">;
+def RD120 : PTXReg<"rd120">;
+def RD121 : PTXReg<"rd121">;
+def RD122 : PTXReg<"rd122">;
+def RD123 : PTXReg<"rd123">;
+def RD124 : PTXReg<"rd124">;
+def RD125 : PTXReg<"rd125">;
+def RD126 : PTXReg<"rd126">;
+def RD127 : PTXReg<"rd127">;
 
 //===----------------------------------------------------------------------===//
 //  Register classes
 //===----------------------------------------------------------------------===//
-
-def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%u", 0, 7)>;
-def RegI16  : RegisterClass<"PTX", [i16], 16, (sequence "RH%u", 0, 7)>;
-def RegI32  : RegisterClass<"PTX", [i32], 32, (sequence "R%u",  0, 7)>;
-def RegI64  : RegisterClass<"PTX", [i64], 64, (sequence "RD%u", 0, 7)>;
-def RegF32  : RegisterClass<"PTX", [f32], 32, (sequence "R%u",  0, 7)>;
-def RegF64  : RegisterClass<"PTX", [f64], 64, (sequence "RD%u", 0, 7)>;
+def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%u", 0, 127)>;
+def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%u", 0, 127)>;
+def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%u", 0, 127)>;
+def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%u", 0, 127)>;
+def RegF32 : RegisterClass<"PTX", [f32], 32, (sequence "R%u", 0, 127)>;
+def RegF64 : RegisterClass<"PTX", [f64], 64, (sequence "RD%u", 0, 127)>;

Added: llvm/trunk/lib/Target/PTX/generate-register-td.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/generate-register-td.py?rev=133736&view=auto
==============================================================================
--- llvm/trunk/lib/Target/PTX/generate-register-td.py (added)
+++ llvm/trunk/lib/Target/PTX/generate-register-td.py Thu Jun 23 13:10:13 2011
@@ -0,0 +1,163 @@
+#!/usr/bin/env python
+##===- generate-register-td.py --------------------------------*-python-*--===##
+##
+##                     The LLVM Compiler Infrastructure
+##
+## This file is distributed under the University of Illinois Open Source
+## License. See LICENSE.TXT for details.
+##
+##===----------------------------------------------------------------------===##
+##
+## This file describes the PTX register file generator.
+##
+##===----------------------------------------------------------------------===##
+
+from sys import argv, exit, stdout
+
+
+if len(argv) != 5:
+    print('Usage: generate-register-td.py <num_preds> <num_16> <num_32> <num_64>')
+    exit(1)
+
+try:
+    num_pred  = int(argv[1])
+    num_16bit = int(argv[2])
+    num_32bit = int(argv[3])
+    num_64bit = int(argv[4])
+except:
+    print('ERROR: Invalid integer parameter')
+    exit(1)
+
+## Print the register definition file
+td_file = open('PTXRegisterInfo.td', 'w')
+
+td_file.write('''
+//===- PTXRegisterInfo.td - PTX Register defs ----------------*- tblgen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+//  Declarations that describe the PTX register file
+//===----------------------------------------------------------------------===//
+
+class PTXReg<string n> : Register<n> {
+  let Namespace = "PTX";
+}
+
+//===----------------------------------------------------------------------===//
+//  Registers
+//===----------------------------------------------------------------------===//
+''')
+
+
+# Print predicate registers
+td_file.write('\n///===- Predicate Registers -----------------------------------------------===//\n\n')
+for r in range(0, num_pred):
+    td_file.write('def P%d : PTXReg<"p%d">;\n' % (r, r))
+
+# Print 16-bit registers
+td_file.write('\n///===- 16-Bit Registers --------------------------------------------------===//\n\n')
+for r in range(0, num_16bit):
+    td_file.write('def RH%d : PTXReg<"rh%d">;\n' % (r, r))
+
+# Print 32-bit registers
+td_file.write('\n///===- 32-Bit Registers --------------------------------------------------===//\n\n')
+for r in range(0, num_32bit):
+    td_file.write('def R%d : PTXReg<"r%d">;\n' % (r, r))
+
+# Print 64-bit registers
+td_file.write('\n///===- 64-Bit Registers --------------------------------------------------===//\n\n')
+for r in range(0, num_64bit):
+    td_file.write('def RD%d : PTXReg<"rd%d">;\n' % (r, r))
+
+
+td_file.write('''
+//===----------------------------------------------------------------------===//
+//  Register classes
+//===----------------------------------------------------------------------===//
+''')
+
+
+# Print register classes
+
+td_file.write('def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%%u", 0, %d)>;\n' % (num_pred-1))
+td_file.write('def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%%u", 0, %d)>;\n' % (num_16bit-1))
+td_file.write('def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
+td_file.write('def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
+td_file.write('def RegF32 : RegisterClass<"PTX", [f32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
+td_file.write('def RegF64 : RegisterClass<"PTX", [f64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
+
+
+td_file.close()
+
+## Now write the PTXCallingConv.td file
+td_file = open('PTXCallingConv.td', 'w')
+
+# Reserve 10% of the available registers for return values, and the other 90%
+# for parameters
+num_ret_pred    = int(0.1 * num_pred)
+num_ret_16bit   = int(0.1 * num_16bit)
+num_ret_32bit   = int(0.1 * num_32bit)
+num_ret_64bit   = int(0.1 * num_64bit)
+num_param_pred  = num_pred - num_ret_pred
+num_param_16bit = num_16bit - num_ret_16bit
+num_param_32bit = num_32bit - num_ret_32bit
+num_param_64bit = num_64bit - num_ret_64bit
+
+param_regs_pred  = [('P%d' % (i+num_ret_pred)) for i in range(0, num_param_pred)]
+ret_regs_pred    = ['P%d' % i for i in range(0, num_ret_pred)]
+param_regs_16bit = [('RH%d' % (i+num_ret_16bit)) for i in range(0, num_param_16bit)]
+ret_regs_16bit   = ['RH%d' % i for i in range(0, num_ret_16bit)]
+param_regs_32bit = [('R%d' % (i+num_ret_32bit)) for i in range(0, num_param_32bit)]
+ret_regs_32bit   = ['R%d' % i for i in range(0, num_ret_32bit)]
+param_regs_64bit = [('RD%d' % (i+num_ret_64bit)) for i in range(0, num_param_64bit)]
+ret_regs_64bit   = ['RD%d' % i for i in range(0, num_ret_64bit)]
+
+param_list_pred  = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_pred)
+ret_list_pred    = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_pred)
+param_list_16bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_16bit)
+ret_list_16bit   = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_16bit)
+param_list_32bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_32bit)
+ret_list_32bit   = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_32bit)
+param_list_64bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_64bit)
+ret_list_64bit   = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_64bit)
+
+td_file.write('''
+//===--- PTXCallingConv.td - Calling Conventions -----------*- tablegen -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This describes the calling conventions for the PTX architecture.
+//
+//===----------------------------------------------------------------------===//
+
+// PTX Formal Parameter Calling Convention
+def CC_PTX : CallingConv<[
+  CCIfType<[i1],      CCAssignToReg<[%s]>>,
+  CCIfType<[i16],     CCAssignToReg<[%s]>>,
+  CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
+  CCIfType<[i64,f64], CCAssignToReg<[%s]>>
+]>;
+
+// PTX Return Value Calling Convention
+def RetCC_PTX : CallingConv<[
+  CCIfType<[i1],      CCAssignToReg<[%s]>>,
+  CCIfType<[i16],     CCAssignToReg<[%s]>>,
+  CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
+  CCIfType<[i64,f64], CCAssignToReg<[%s]>>
+]>;
+''' % (param_list_pred, param_list_16bit, param_list_32bit, param_list_64bit,
+       ret_list_pred, ret_list_16bit, ret_list_32bit, ret_list_64bit))
+
+
+td_file.close()

Propchange: llvm/trunk/lib/Target/PTX/generate-register-td.py
------------------------------------------------------------------------------
    svn:executable = *

Modified: llvm/trunk/test/CodeGen/PTX/add.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/add.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/add.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/add.ll Thu Jun 23 13:10:13 2011
@@ -1,70 +1,70 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
 define ptx_device i16 @t1_u16(i16 %x, i16 %y) {
-; CHECK: add.u16 rh0, rh1, rh2;
+; CHECK: add.u16 rh{{[0-9]+}}, rh{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%z = add i16 %x, %y
 	ret i16 %z
 }
 
 define ptx_device i32 @t1_u32(i32 %x, i32 %y) {
-; CHECK: add.u32 r0, r1, r2;
+; CHECK: add.u32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%z = add i32 %x, %y
 	ret i32 %z
 }
 
 define ptx_device i64 @t1_u64(i64 %x, i64 %y) {
-; CHECK: add.u64 rd0, rd1, rd2;
+; CHECK: add.u64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%z = add i64 %x, %y
 	ret i64 %z
 }
 
 define ptx_device float @t1_f32(float %x, float %y) {
-; CHECK: add.rn.f32 r0, r1, r2
+; CHECK: add.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-NEXT: ret;
   %z = fadd float %x, %y
   ret float %z
 }
 
 define ptx_device double @t1_f64(double %x, double %y) {
-; CHECK: add.rn.f64 rd0, rd1, rd2
+; CHECK: add.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}
 ; CHECK-NEXT: ret;
   %z = fadd double %x, %y
   ret double %z
 }
 
 define ptx_device i16 @t2_u16(i16 %x) {
-; CHECK: add.u16 rh0, rh1, 1;
+; CHECK: add.u16 rh{{[0-9]+}}, rh{{[0-9]+}}, 1;
 ; CHECK-NEXT: ret;
 	%z = add i16 %x, 1
 	ret i16 %z
 }
 
 define ptx_device i32 @t2_u32(i32 %x) {
-; CHECK: add.u32 r0, r1, 1;
+; CHECK: add.u32 r{{[0-9]+}}, r{{[0-9]+}}, 1;
 ; CHECK-NEXT: ret;
 	%z = add i32 %x, 1
 	ret i32 %z
 }
 
 define ptx_device i64 @t2_u64(i64 %x) {
-; CHECK: add.u64 rd0, rd1, 1;
+; CHECK: add.u64 rd{{[0-9]+}}, rd{{[0-9]+}}, 1;
 ; CHECK-NEXT: ret;
 	%z = add i64 %x, 1
 	ret i64 %z
 }
 
 define ptx_device float @t2_f32(float %x) {
-; CHECK: add.rn.f32 r0, r1, 0F3F800000;
+; CHECK: add.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, 0F3F800000;
 ; CHECK-NEXT: ret;
   %z = fadd float %x, 1.0
   ret float %z
 }
 
 define ptx_device double @t2_f64(double %x) {
-; CHECK: add.rn.f64 rd0, rd1, 0D3FF0000000000000;
+; CHECK: add.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, 0D3FF0000000000000;
 ; CHECK-NEXT: ret;
   %z = fadd double %x, 1.0
   ret double %z

Added: llvm/trunk/test/CodeGen/PTX/aggregates.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/aggregates.ll?rev=133736&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/aggregates.ll (added)
+++ llvm/trunk/test/CodeGen/PTX/aggregates.ll Thu Jun 23 13:10:13 2011
@@ -0,0 +1,23 @@
+; RUN: llc < %s -march=ptx32 -mattr=sm20 | FileCheck %s
+
+%complex = type { float, float }
+
+define ptx_device %complex @complex_add(%complex %a, %complex %b) {
+entry:
+; CHECK:      ld.param.f32	r[[R0:[0-9]+]], [__param_1];
+; CHECK-NEXT:	ld.param.f32	r[[R2:[0-9]+]], [__param_3];
+; CHECK-NEXT:	ld.param.f32	r[[R1:[0-9]+]], [__param_2];
+; CHECK-NEXT:	ld.param.f32	r[[R3:[0-9]+]], [__param_4];
+; CHECK-NEXT:	add.rn.f32	r[[R0]], r[[R0]], r[[R2]];
+; CHECK-NEXT:	add.rn.f32	r[[R1]], r[[R1]], r[[R3]];
+; CHECK-NEXT:	ret;
+  %a.real = extractvalue %complex %a, 0
+  %a.imag = extractvalue %complex %a, 1
+  %b.real = extractvalue %complex %b, 0
+  %b.imag = extractvalue %complex %b, 1
+  %ret.real = fadd float %a.real, %b.real
+  %ret.imag = fadd float %a.imag, %b.imag
+  %ret.0 = insertvalue %complex undef, float %ret.real, 0
+  %ret.1 = insertvalue %complex %ret.0, float %ret.imag, 1
+  ret %complex %ret.1
+}

Modified: llvm/trunk/test/CodeGen/PTX/bitwise.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/bitwise.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/bitwise.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/bitwise.ll Thu Jun 23 13:10:13 2011
@@ -3,21 +3,21 @@
 ; preds
 
 define ptx_device i32 @t1_and_preds(i1 %x, i1 %y) {
-; CHECK: and.pred p0, p1, p2
+; CHECK: and.pred p{{[0-9]+}}, p{{[0-9]+}}, p{{[0-9]+}}
   %c = and i1 %x, %y
   %d = zext i1 %c to i32 
   ret i32 %d
 }
 
 define ptx_device i32 @t1_or_preds(i1 %x, i1 %y) {
-; CHECK: or.pred p0, p1, p2
+; CHECK: or.pred p{{[0-9]+}}, p{{[0-9]+}}, p{{[0-9]+}}
   %a = or i1 %x, %y
   %b = zext i1 %a to i32 
   ret i32 %b
 }
 
 define ptx_device i32 @t1_xor_preds(i1 %x, i1 %y) {
-; CHECK: xor.pred p0, p1, p2
+; CHECK: xor.pred p{{[0-9]+}}, p{{[0-9]+}}, p{{[0-9]+}}
   %a = xor i1 %x, %y
   %b = zext i1 %a to i32 
   ret i32 %b

Modified: llvm/trunk/test/CodeGen/PTX/bra.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/bra.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/bra.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/bra.ll Thu Jun 23 13:10:13 2011
@@ -10,15 +10,15 @@
 
 define ptx_device i32 @test_bra_cond_direct(i32 %x, i32 %y) {
 entry:
-; CHECK: setp.le.u32 p0, r1, r2
+; CHECK: setp.le.u32 p0, r[[R0:[0-9]+]], r[[R1:[0-9]+]]
 	%p = icmp ugt i32 %x, %y
 ; CHECK-NEXT: @p0 bra
 ; CHECK-NOT: bra
 	br i1 %p, label %clause.if, label %clause.else
 clause.if:
-; CHECK: mov.u32 r0, r1
+; CHECK: mov.u32 r{{[0-9]+}}, r[[R0]]
 	ret i32 %x
 clause.else:
-; CHECK: mov.u32 r0, r2
+; CHECK: mov.u32 r{{[0-9]+}}, r[[R1]]
 	ret i32 %y
 }

Modified: llvm/trunk/test/CodeGen/PTX/cvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/cvt.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/cvt.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/cvt.ll Thu Jun 23 13:10:13 2011
@@ -4,9 +4,9 @@
 ; (note: we convert back to i32 to return)
 
 define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) {
-; CHECK: setp.gt.b16 p0, rh1, 0
-; CHECK-NEXT: and.pred p0, p0, p1;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.b16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0
+; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
 ; CHECK-NEXT: ret;
 	%a = trunc i16 %x to i1
 	%b = and i1 %a, %y
@@ -15,9 +15,9 @@
 }
 
 define ptx_device i32 @cvt_pred_i32(i32 %x, i1 %y) {
-; CHECK: setp.gt.b32 p0, r1, 0
-; CHECK-NEXT: and.pred p0, p0, p1;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0
+; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
 ; CHECK-NEXT: ret;
 	%a = trunc i32 %x to i1
 	%b = and i1 %a, %y
@@ -26,9 +26,9 @@
 }
 
 define ptx_device i32 @cvt_pred_i64(i64 %x, i1 %y) {
-; CHECK: setp.gt.b64 p0, rd1, 0
-; CHECK-NEXT: and.pred p0, p0, p1;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.b64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0
+; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
 ; CHECK-NEXT: ret;
 	%a = trunc i64 %x to i1
 	%b = and i1 %a, %y
@@ -37,9 +37,9 @@
 }
 
 define ptx_device i32 @cvt_pred_f32(float %x, i1 %y) {
-; CHECK: setp.gt.b32 p0, r1, 0
-; CHECK-NEXT: and.pred p0, p0, p1;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0
+; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
 ; CHECK-NEXT: ret;
 	%a = fptoui float %x to i1
 	%b = and i1 %a, %y
@@ -48,9 +48,9 @@
 }
 
 define ptx_device i32 @cvt_pred_f64(double %x, i1 %y) {
-; CHECK: setp.gt.b64 p0, rd1, 0
-; CHECK-NEXT: and.pred p0, p0, p1;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.b64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0
+; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
 ; CHECK-NEXT: ret;
 	%a = fptoui double %x to i1
 	%b = and i1 %a, %y
@@ -61,35 +61,35 @@
 ; i16
 
 define ptx_device i16 @cvt_i16_preds(i1 %x) {
-; CHECK: selp.u16 rh0, 1, 0, p1;
+; CHECK: selp.u16 rh{{[0-9]+}}, 1, 0, p{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = zext i1 %x to i16
 	ret i16 %a
 }
 
 define ptx_device i16 @cvt_i16_i32(i32 %x) {
-; CHECK: cvt.u16.u32 rh0, r1;
+; CHECK: cvt.u16.u32 rh{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = trunc i32 %x to i16
 	ret i16 %a
 }
 
 define ptx_device i16 @cvt_i16_i64(i64 %x) {
-; CHECK: cvt.u16.u64 rh0, rd1;
+; CHECK: cvt.u16.u64 rh{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = trunc i64 %x to i16
 	ret i16 %a
 }
 
 define ptx_device i16 @cvt_i16_f32(float %x) {
-; CHECK: cvt.rzi.u16.f32 rh0, r1;
+; CHECK: cvt.rzi.u16.f32 rh{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fptoui float %x to i16
 	ret i16 %a
 }
 
 define ptx_device i16 @cvt_i16_f64(double %x) {
-; CHECK: cvt.rzi.u16.f64 rh0, rd1;
+; CHECK: cvt.rzi.u16.f64 rh{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fptoui double %x to i16
 	ret i16 %a
@@ -98,35 +98,35 @@
 ; i32
 
 define ptx_device i32 @cvt_i32_preds(i1 %x) {
-; CHECK: selp.u32 r0, 1, 0, p1;
+; CHECK: selp.u32 r{{[0-9]+}}, 1, 0, p{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = zext i1 %x to i32
 	ret i32 %a
 }
 
 define ptx_device i32 @cvt_i32_i16(i16 %x) {
-; CHECK: cvt.u32.u16 r0, rh1;
+; CHECK: cvt.u32.u16 r{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = zext i16 %x to i32
 	ret i32 %a
 }
 
 define ptx_device i32 @cvt_i32_i64(i64 %x) {
-; CHECK: cvt.u32.u64 r0, rd1;
+; CHECK: cvt.u32.u64 r{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = trunc i64 %x to i32
 	ret i32 %a
 }
 
 define ptx_device i32 @cvt_i32_f32(float %x) {
-; CHECK: cvt.rzi.u32.f32 r0, r1;
+; CHECK: cvt.rzi.u32.f32 r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fptoui float %x to i32
 	ret i32 %a
 }
 
 define ptx_device i32 @cvt_i32_f64(double %x) {
-; CHECK: cvt.rzi.u32.f64 r0, rd1;
+; CHECK: cvt.rzi.u32.f64 r{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fptoui double %x to i32
 	ret i32 %a
@@ -135,35 +135,35 @@
 ; i64
 
 define ptx_device i64 @cvt_i64_preds(i1 %x) {
-; CHECK: selp.u64 rd0, 1, 0, p1;
+; CHECK: selp.u64 rd{{[0-9]+}}, 1, 0, p{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = zext i1 %x to i64
 	ret i64 %a
 }
 
 define ptx_device i64 @cvt_i64_i16(i16 %x) {
-; CHECK: cvt.u64.u16 rd0, rh1;
+; CHECK: cvt.u64.u16 rd{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = zext i16 %x to i64
 	ret i64 %a
 }
 
 define ptx_device i64 @cvt_i64_i32(i32 %x) {
-; CHECK: cvt.u64.u32 rd0, r1;
+; CHECK: cvt.u64.u32 rd{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = zext i32 %x to i64
 	ret i64 %a
 }
 
 define ptx_device i64 @cvt_i64_f32(float %x) {
-; CHECK: cvt.rzi.u64.f32 rd0, r1;
+; CHECK: cvt.rzi.u64.f32 rd{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fptoui float %x to i64
 	ret i64 %a
 }
 
 define ptx_device i64 @cvt_i64_f64(double %x) {
-; CHECK: cvt.rzi.u64.f64 rd0, rd1;
+; CHECK: cvt.rzi.u64.f64 rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK: ret;
 	%a = fptoui double %x to i64
 	ret i64 %a
@@ -172,35 +172,35 @@
 ; f32
 
 define ptx_device float @cvt_f32_preds(i1 %x) {
-; CHECK: selp.f32 r0, 0F3F800000, 0F00000000, p1;
+; CHECK: selp.f32 r{{[0-9]+}}, 0F3F800000, 0F00000000, p{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = uitofp i1 %x to float
 	ret float %a
 }
 
 define ptx_device float @cvt_f32_i16(i16 %x) {
-; CHECK: cvt.rn.f32.u16 r0, rh1;
+; CHECK: cvt.rn.f32.u16 r{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = uitofp i16 %x to float
 	ret float %a
 }
 
 define ptx_device float @cvt_f32_i32(i32 %x) {
-; CHECK: cvt.rn.f32.u32 r0, r1;
+; CHECK: cvt.rn.f32.u32 r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = uitofp i32 %x to float
 	ret float %a
 }
 
 define ptx_device float @cvt_f32_i64(i64 %x) {
-; CHECK: cvt.rn.f32.u64 r0, rd1;
+; CHECK: cvt.rn.f32.u64 r{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = uitofp i64 %x to float
 	ret float %a
 }
 
 define ptx_device float @cvt_f32_f64(double %x) {
-; CHECK: cvt.rn.f32.f64 r0, rd1;
+; CHECK: cvt.rn.f32.f64 r{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fptrunc double %x to float
 	ret float %a
@@ -209,35 +209,35 @@
 ; f64
 
 define ptx_device double @cvt_f64_preds(i1 %x) {
-; CHECK: selp.f64 rd0, 0D3F80000000000000, 0D0000000000000000, p1;
+; CHECK: selp.f64 rd{{[0-9]+}}, 0D3F80000000000000, 0D0000000000000000, p{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = uitofp i1 %x to double
 	ret double %a
 }
 
 define ptx_device double @cvt_f64_i16(i16 %x) {
-; CHECK: cvt.rn.f64.u16 rd0, rh1;
+; CHECK: cvt.rn.f64.u16 rd{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = uitofp i16 %x to double
 	ret double %a
 }
 
 define ptx_device double @cvt_f64_i32(i32 %x) {
-; CHECK: cvt.rn.f64.u32 rd0, r1;
+; CHECK: cvt.rn.f64.u32 rd{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = uitofp i32 %x to double
 	ret double %a
 }
 
 define ptx_device double @cvt_f64_i64(i64 %x) {
-; CHECK: cvt.rn.f64.u64 rd0, rd1;
+; CHECK: cvt.rn.f64.u64 rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = uitofp i64 %x to double
 	ret double %a
 }
 
 define ptx_device double @cvt_f64_f32(float %x) {
-; CHECK: cvt.f64.f32 rd0, r1;
+; CHECK: cvt.f64.f32 rd{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fpext float %x to double
 	ret double %a

Modified: llvm/trunk/test/CodeGen/PTX/fdiv-sm10.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/fdiv-sm10.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/fdiv-sm10.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/fdiv-sm10.ll Thu Jun 23 13:10:13 2011
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=ptx32 -mattr=+sm10 | FileCheck %s
 
 define ptx_device float @t1_f32(float %x, float %y) {
-; CHECK: div.f32 r0, r1, r2;
+; CHECK: div.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fdiv float %x, %y
 	ret float %a
 }
 
 define ptx_device double @t1_f64(double %x, double %y) {
-; CHECK: div.f64 rd0, rd1, rd2;
+; CHECK: div.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fdiv double %x, %y
 	ret double %a

Modified: llvm/trunk/test/CodeGen/PTX/fdiv-sm13.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/fdiv-sm13.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/fdiv-sm13.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/fdiv-sm13.ll Thu Jun 23 13:10:13 2011
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=ptx32 -mattr=+sm13 | FileCheck %s
 
 define ptx_device float @t1_f32(float %x, float %y) {
-; CHECK: div.rn.f32 r0, r1, r2;
+; CHECK: div.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fdiv float %x, %y
 	ret float %a
 }
 
 define ptx_device double @t1_f64(double %x, double %y) {
-; CHECK: div.rn.f64 rd0, rd1, rd2;
+; CHECK: div.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fdiv double %x, %y
 	ret double %a

Modified: llvm/trunk/test/CodeGen/PTX/fneg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/fneg.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/fneg.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/fneg.ll Thu Jun 23 13:10:13 2011
@@ -1,14 +1,14 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
 define ptx_device float @t1_f32(float %x) {
-; CHECK: neg.f32 r0, r1;
+; CHECK: neg.f32 r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%y = fsub float -0.000000e+00, %x
 	ret float %y
 }
 
 define ptx_device double @t1_f64(double %x) {
-; CHECK: neg.f64 rd0, rd1;
+; CHECK: neg.f64 rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%y = fsub double -0.000000e+00, %x
 	ret double %y

Modified: llvm/trunk/test/CodeGen/PTX/ld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/ld.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/ld.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/ld.ll Thu Jun 23 13:10:13 2011
@@ -63,7 +63,7 @@
 
 define ptx_device i16 @t1_u16(i16* %p) {
 entry:
-;CHECK: ld.global.u16 rh0, [r1];
+;CHECK: ld.global.u16 rh{{[0-9]+}}, [r{{[0-9]+}}];
 ;CHECK-NEXT: ret;
   %x = load i16* %p
   ret i16 %x
@@ -71,7 +71,7 @@
 
 define ptx_device i32 @t1_u32(i32* %p) {
 entry:
-;CHECK: ld.global.u32 r0, [r1];
+;CHECK: ld.global.u32 r{{[0-9]+}}, [r{{[0-9]+}}];
 ;CHECK-NEXT: ret;
   %x = load i32* %p
   ret i32 %x
@@ -79,7 +79,7 @@
 
 define ptx_device i64 @t1_u64(i64* %p) {
 entry:
-;CHECK: ld.global.u64 rd0, [r1];
+;CHECK: ld.global.u64 rd{{[0-9]+}}, [r{{[0-9]+}}];
 ;CHECK-NEXT: ret;
   %x = load i64* %p
   ret i64 %x
@@ -87,7 +87,7 @@
 
 define ptx_device float @t1_f32(float* %p) {
 entry:
-;CHECK: ld.global.f32 r0, [r1];
+;CHECK: ld.global.f32 r{{[0-9]+}}, [r{{[0-9]+}}];
 ;CHECK-NEXT: ret;
   %x = load float* %p
   ret float %x
@@ -95,7 +95,7 @@
 
 define ptx_device double @t1_f64(double* %p) {
 entry:
-;CHECK: ld.global.f64 rd0, [r1];
+;CHECK: ld.global.f64 rd{{[0-9]+}}, [r{{[0-9]+}}];
 ;CHECK-NEXT: ret;
   %x = load double* %p
   ret double %x
@@ -103,7 +103,7 @@
 
 define ptx_device i16 @t2_u16(i16* %p) {
 entry:
-;CHECK: ld.global.u16 rh0, [r1+2];
+;CHECK: ld.global.u16 rh{{[0-9]+}}, [r{{[0-9]+}}+2];
 ;CHECK-NEXT: ret;
   %i = getelementptr i16* %p, i32 1
   %x = load i16* %i
@@ -112,7 +112,7 @@
 
 define ptx_device i32 @t2_u32(i32* %p) {
 entry:
-;CHECK: ld.global.u32 r0, [r1+4];
+;CHECK: ld.global.u32 r{{[0-9]+}}, [r{{[0-9]+}}+4];
 ;CHECK-NEXT: ret;
   %i = getelementptr i32* %p, i32 1
   %x = load i32* %i
@@ -121,7 +121,7 @@
 
 define ptx_device i64 @t2_u64(i64* %p) {
 entry:
-;CHECK: ld.global.u64 rd0, [r1+8];
+;CHECK: ld.global.u64 rd{{[0-9]+}}, [r{{[0-9]+}}+8];
 ;CHECK-NEXT: ret;
   %i = getelementptr i64* %p, i32 1
   %x = load i64* %i
@@ -130,7 +130,7 @@
 
 define ptx_device float @t2_f32(float* %p) {
 entry:
-;CHECK: ld.global.f32 r0, [r1+4];
+;CHECK: ld.global.f32 r{{[0-9]+}}, [r{{[0-9]+}}+4];
 ;CHECK-NEXT: ret;
   %i = getelementptr float* %p, i32 1
   %x = load float* %i
@@ -139,7 +139,7 @@
 
 define ptx_device double @t2_f64(double* %p) {
 entry:
-;CHECK: ld.global.f64 rd0, [r1+8];
+;CHECK: ld.global.f64 rd{{[0-9]+}}, [r{{[0-9]+}}+8];
 ;CHECK-NEXT: ret;
   %i = getelementptr double* %p, i32 1
   %x = load double* %i
@@ -148,9 +148,9 @@
 
 define ptx_device i16 @t3_u16(i16* %p, i32 %q) {
 entry:
-;CHECK: shl.b32 r0, r2, 1;
-;CHECK-NEXT: add.u32 r0, r1, r0;
-;CHECK-NEXT: ld.global.u16 rh0, [r0];
+;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 1;
+;CHECK-NEXT: add.u32 r[[R0]], r{{[0-9]+}}, r[[R0]];
+;CHECK-NEXT: ld.global.u16 rh{{[0-9]+}}, [r[[R0]]];
   %i = getelementptr i16* %p, i32 %q
   %x = load i16* %i
   ret i16 %x
@@ -158,9 +158,9 @@
 
 define ptx_device i32 @t3_u32(i32* %p, i32 %q) {
 entry:
-;CHECK: shl.b32 r0, r2, 2;
-;CHECK-NEXT: add.u32 r0, r1, r0;
-;CHECK-NEXT: ld.global.u32 r0, [r0];
+;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 2;
+;CHECK-NEXT: add.u32 r[[R0]], r{{[0-9]+}}, r[[R0]];
+;CHECK-NEXT: ld.global.u32 r{{[0-9]+}}, [r[[R0]]];
   %i = getelementptr i32* %p, i32 %q
   %x = load i32* %i
   ret i32 %x
@@ -168,9 +168,9 @@
 
 define ptx_device i64 @t3_u64(i64* %p, i32 %q) {
 entry:
-;CHECK: shl.b32 r0, r2, 3;
-;CHECK-NEXT: add.u32 r0, r1, r0;
-;CHECK-NEXT: ld.global.u64 rd0, [r0];
+;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 3;
+;CHECK-NEXT: add.u32 r[[R0]], r{{[0-9]+}}, r[[R0]];
+;CHECK-NEXT: ld.global.u64 rd{{[0-9]+}}, [r[[R0]]];
   %i = getelementptr i64* %p, i32 %q
   %x = load i64* %i
   ret i64 %x
@@ -178,9 +178,9 @@
 
 define ptx_device float @t3_f32(float* %p, i32 %q) {
 entry:
-;CHECK: shl.b32 r0, r2, 2;
-;CHECK-NEXT: add.u32 r0, r1, r0;
-;CHECK-NEXT: ld.global.f32 r0, [r0];
+;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 2;
+;CHECK-NEXT: add.u32 r[[R0]], r{{[0-9]+}}, r[[R0]];
+;CHECK-NEXT: ld.global.f32 r{{[0-9]+}}, [r[[R0]]];
   %i = getelementptr float* %p, i32 %q
   %x = load float* %i
   ret float %x
@@ -188,9 +188,9 @@
 
 define ptx_device double @t3_f64(double* %p, i32 %q) {
 entry:
-;CHECK: shl.b32 r0, r2, 3;
-;CHECK-NEXT: add.u32 r0, r1, r0;
-;CHECK-NEXT: ld.global.f64 rd0, [r0];
+;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 3;
+;CHECK-NEXT: add.u32 r[[R0]], r{{[0-9]+}}, r[[R0]];
+;CHECK-NEXT: ld.global.f64 rd{{[0-9]+}}, [r[[R0]]];
   %i = getelementptr double* %p, i32 %q
   %x = load double* %i
   ret double %x
@@ -198,8 +198,8 @@
 
 define ptx_device i16 @t4_global_u16() {
 entry:
-;CHECK: mov.u32 r0, array_i16;
-;CHECK-NEXT: ld.global.u16 rh0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
+;CHECK-NEXT: ld.global.u16 rh{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i16]* @array_i16, i32 0, i32 0
   %x = load i16* %i
@@ -208,8 +208,8 @@
 
 define ptx_device i32 @t4_global_u32() {
 entry:
-;CHECK: mov.u32 r0, array_i32;
-;CHECK-NEXT: ld.global.u32 r0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i32;
+;CHECK-NEXT: ld.global.u32 r{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 0
   %x = load i32* %i
@@ -218,8 +218,8 @@
 
 define ptx_device i64 @t4_global_u64() {
 entry:
-;CHECK: mov.u32 r0, array_i64;
-;CHECK-NEXT: ld.global.u64 rd0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i64;
+;CHECK-NEXT: ld.global.u64 rd{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 0
   %x = load i64* %i
@@ -228,8 +228,8 @@
 
 define ptx_device float @t4_global_f32() {
 entry:
-;CHECK: mov.u32 r0, array_float;
-;CHECK-NEXT: ld.global.f32 r0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_float;
+;CHECK-NEXT: ld.global.f32 r{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x float]* @array_float, i32 0, i32 0
   %x = load float* %i
@@ -238,8 +238,8 @@
 
 define ptx_device double @t4_global_f64() {
 entry:
-;CHECK: mov.u32 r0, array_double;
-;CHECK-NEXT: ld.global.f64 rd0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_double;
+;CHECK-NEXT: ld.global.f64 rd{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x double]* @array_double, i32 0, i32 0
   %x = load double* %i
@@ -248,8 +248,8 @@
 
 define ptx_device i16 @t4_const_u16() {
 entry:
-;CHECK: mov.u32 r0, array_constant_i16;
-;CHECK-NEXT: ld.const.u16 rh0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_constant_i16;
+;CHECK-NEXT: ld.const.u16 rh{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i16] addrspace(1)* @array_constant_i16, i32 0, i32 0
   %x = load i16 addrspace(1)* %i
@@ -258,8 +258,8 @@
 
 define ptx_device i32 @t4_const_u32() {
 entry:
-;CHECK: mov.u32 r0, array_constant_i32;
-;CHECK-NEXT: ld.const.u32 r0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_constant_i32;
+;CHECK-NEXT: ld.const.u32 r{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i32] addrspace(1)* @array_constant_i32, i32 0, i32 0
   %x = load i32 addrspace(1)* %i
@@ -268,8 +268,8 @@
 
 define ptx_device i64 @t4_const_u64() {
 entry:
-;CHECK: mov.u32 r0, array_constant_i64;
-;CHECK-NEXT: ld.const.u64 rd0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_constant_i64;
+;CHECK-NEXT: ld.const.u64 rd{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i64] addrspace(1)* @array_constant_i64, i32 0, i32 0
   %x = load i64 addrspace(1)* %i
@@ -278,8 +278,8 @@
 
 define ptx_device float @t4_const_f32() {
 entry:
-;CHECK: mov.u32 r0, array_constant_float;
-;CHECK-NEXT: ld.const.f32 r0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_constant_float;
+;CHECK-NEXT: ld.const.f32 r{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x float] addrspace(1)* @array_constant_float, i32 0, i32 0
   %x = load float addrspace(1)* %i
@@ -288,8 +288,8 @@
 
 define ptx_device double @t4_const_f64() {
 entry:
-;CHECK: mov.u32 r0, array_constant_double;
-;CHECK-NEXT: ld.const.f64 rd0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_constant_double;
+;CHECK-NEXT: ld.const.f64 rd{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x double] addrspace(1)* @array_constant_double, i32 0, i32 0
   %x = load double addrspace(1)* %i
@@ -298,8 +298,8 @@
 
 define ptx_device i16 @t4_local_u16() {
 entry:
-;CHECK: mov.u32 r0, array_local_i16;
-;CHECK-NEXT: ld.local.u16 rh0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i16;
+;CHECK-NEXT: ld.local.u16 rh{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i16] addrspace(2)* @array_local_i16, i32 0, i32 0
   %x = load i16 addrspace(2)* %i
@@ -308,8 +308,8 @@
 
 define ptx_device i32 @t4_local_u32() {
 entry:
-;CHECK: mov.u32 r0, array_local_i32;
-;CHECK-NEXT: ld.local.u32 r0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i32;
+;CHECK-NEXT: ld.local.u32 r{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i32] addrspace(2)* @array_local_i32, i32 0, i32 0
   %x = load i32 addrspace(2)* %i
@@ -318,8 +318,8 @@
 
 define ptx_device i64 @t4_local_u64() {
 entry:
-;CHECK: mov.u32 r0, array_local_i64;
-;CHECK-NEXT: ld.local.u64 rd0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i64;
+;CHECK-NEXT: ld.local.u64 rd{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i64] addrspace(2)* @array_local_i64, i32 0, i32 0
   %x = load i64 addrspace(2)* %i
@@ -328,8 +328,8 @@
 
 define ptx_device float @t4_local_f32() {
 entry:
-;CHECK: mov.u32 r0, array_local_float;
-;CHECK-NEXT: ld.local.f32 r0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_float;
+;CHECK-NEXT: ld.local.f32 r{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x float] addrspace(2)* @array_local_float, i32 0, i32 0
   %x = load float addrspace(2)* %i
@@ -338,8 +338,8 @@
 
 define ptx_device double @t4_local_f64() {
 entry:
-;CHECK: mov.u32 r0, array_local_double;
-;CHECK-NEXT: ld.local.f64 rd0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_double;
+;CHECK-NEXT: ld.local.f64 rd{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x double] addrspace(2)* @array_local_double, i32 0, i32 0
   %x = load double addrspace(2)* %i
@@ -348,8 +348,8 @@
 
 define ptx_device i16 @t4_shared_u16() {
 entry:
-;CHECK: mov.u32 r0, array_shared_i16;
-;CHECK-NEXT: ld.shared.u16 rh0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i16;
+;CHECK-NEXT: ld.shared.u16 rh{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i16] addrspace(4)* @array_shared_i16, i32 0, i32 0
   %x = load i16 addrspace(4)* %i
@@ -358,8 +358,8 @@
 
 define ptx_device i32 @t4_shared_u32() {
 entry:
-;CHECK: mov.u32 r0, array_shared_i32;
-;CHECK-NEXT: ld.shared.u32 r0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i32;
+;CHECK-NEXT: ld.shared.u32 r{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i32] addrspace(4)* @array_shared_i32, i32 0, i32 0
   %x = load i32 addrspace(4)* %i
@@ -368,8 +368,8 @@
 
 define ptx_device i64 @t4_shared_u64() {
 entry:
-;CHECK: mov.u32 r0, array_shared_i64;
-;CHECK-NEXT: ld.shared.u64 rd0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i64;
+;CHECK-NEXT: ld.shared.u64 rd{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i64] addrspace(4)* @array_shared_i64, i32 0, i32 0
   %x = load i64 addrspace(4)* %i
@@ -378,8 +378,8 @@
 
 define ptx_device float @t4_shared_f32() {
 entry:
-;CHECK: mov.u32 r0, array_shared_float;
-;CHECK-NEXT: ld.shared.f32 r0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_float;
+;CHECK-NEXT: ld.shared.f32 r{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x float] addrspace(4)* @array_shared_float, i32 0, i32 0
   %x = load float addrspace(4)* %i
@@ -388,8 +388,8 @@
 
 define ptx_device double @t4_shared_f64() {
 entry:
-;CHECK: mov.u32 r0, array_shared_double;
-;CHECK-NEXT: ld.shared.f64 rd0, [r0];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_double;
+;CHECK-NEXT: ld.shared.f64 rd{{[0-9]+}}, [r[[R0]]];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x double] addrspace(4)* @array_shared_double, i32 0, i32 0
   %x = load double addrspace(4)* %i
@@ -398,8 +398,8 @@
 
 define ptx_device i16 @t5_u16() {
 entry:
-;CHECK: mov.u32 r0, array_i16;
-;CHECK-NEXT: ld.global.u16 rh0, [r0+2];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
+;CHECK-NEXT: ld.global.u16 rh{{[0-9]+}}, [r[[R0]]+2];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i16]* @array_i16, i32 0, i32 1
   %x = load i16* %i
@@ -408,8 +408,8 @@
 
 define ptx_device i32 @t5_u32() {
 entry:
-;CHECK: mov.u32 r0, array_i32;
-;CHECK-NEXT: ld.global.u32 r0, [r0+4];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i32;
+;CHECK-NEXT: ld.global.u32 r{{[0-9]+}}, [r[[R0]]+4];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 1
   %x = load i32* %i
@@ -418,8 +418,8 @@
 
 define ptx_device i64 @t5_u64() {
 entry:
-;CHECK: mov.u32 r0, array_i64;
-;CHECK-NEXT: ld.global.u64 rd0, [r0+8];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i64;
+;CHECK-NEXT: ld.global.u64 rd{{[0-9]+}}, [r[[R0]]+8];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 1
   %x = load i64* %i
@@ -428,8 +428,8 @@
 
 define ptx_device float @t5_f32() {
 entry:
-;CHECK: mov.u32 r0, array_float;
-;CHECK-NEXT: ld.global.f32 r0, [r0+4];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_float;
+;CHECK-NEXT: ld.global.f32 r{{[0-9]+}}, [r[[R0]]+4];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x float]* @array_float, i32 0, i32 1
   %x = load float* %i
@@ -438,8 +438,8 @@
 
 define ptx_device double @t5_f64() {
 entry:
-;CHECK: mov.u32 r0, array_double;
-;CHECK-NEXT: ld.global.f64 rd0, [r0+8];
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_double;
+;CHECK-NEXT: ld.global.f64 rd{{[0-9]+}}, [r[[R0]]+8];
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x double]* @array_double, i32 0, i32 1
   %x = load double* %i

Modified: llvm/trunk/test/CodeGen/PTX/llvm-intrinsic.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/llvm-intrinsic.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/llvm-intrinsic.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/llvm-intrinsic.ll Thu Jun 23 13:10:13 2011
@@ -2,7 +2,7 @@
 
 define ptx_device float @test_sqrt_f32(float %x) {
 entry:
-; CHECK: sqrt.rn.f32 r0, r1;
+; CHECK: sqrt.rn.f32 r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
   %y = call float @llvm.sqrt.f32(float %x)
   ret float %y
@@ -10,7 +10,7 @@
 
 define ptx_device double @test_sqrt_f64(double %x) {
 entry:
-; CHECK: sqrt.rn.f64 rd0, rd1;
+; CHECK: sqrt.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
   %y = call double @llvm.sqrt.f64(double %x)
   ret double %y
@@ -18,7 +18,7 @@
 
 define ptx_device float @test_sin_f32(float %x) {
 entry:
-; CHECK: sin.approx.f32 r0, r1;
+; CHECK: sin.approx.f32 r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
   %y = call float @llvm.sin.f32(float %x)
   ret float %y
@@ -26,7 +26,7 @@
 
 define ptx_device double @test_sin_f64(double %x) {
 entry:
-; CHECK: sin.approx.f64 rd0, rd1;
+; CHECK: sin.approx.f64 rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
   %y = call double @llvm.sin.f64(double %x)
   ret double %y
@@ -34,7 +34,7 @@
 
 define ptx_device float @test_cos_f32(float %x) {
 entry:
-; CHECK: cos.approx.f32 r0, r1;
+; CHECK: cos.approx.f32 r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
   %y = call float @llvm.cos.f32(float %x)
   ret float %y
@@ -42,7 +42,7 @@
 
 define ptx_device double @test_cos_f64(double %x) {
 entry:
-; CHECK: cos.approx.f64 rd0, rd1;
+; CHECK: cos.approx.f64 rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
   %y = call double @llvm.cos.f64(double %x)
   ret double %y

Modified: llvm/trunk/test/CodeGen/PTX/mad.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mad.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/mad.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/mad.ll Thu Jun 23 13:10:13 2011
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=ptx32 -mattr=+sm13 | FileCheck %s
 
 define ptx_device float @t1_f32(float %x, float %y, float %z) {
-; CHECK: mad.rn.f32 r0, r1, r2, r3;
+; CHECK: mad.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fmul float %x, %y
   %b = fadd float %a, %z
@@ -9,7 +9,7 @@
 }
 
 define ptx_device double @t1_f64(double %x, double %y, double %z) {
-; CHECK: mad.rn.f64 rd0, rd1, rd2, rd3;
+; CHECK: mad.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%a = fmul double %x, %y
   %b = fadd double %a, %z

Modified: llvm/trunk/test/CodeGen/PTX/mov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mov.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/mov.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/mov.ll Thu Jun 23 13:10:13 2011
@@ -1,61 +1,61 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
 define ptx_device i16 @t1_u16() {
-; CHECK: mov.u16 rh0, 0;
+; CHECK: mov.u16 rh{{[0-9]+}}, 0;
 ; CHECK: ret;
 	ret i16 0
 }
 
 define ptx_device i32 @t1_u32() {
-; CHECK: mov.u32 r0, 0;
+; CHECK: mov.u32 r{{[0-9]+}}, 0;
 ; CHECK: ret;
 	ret i32 0
 }
 
 define ptx_device i64 @t1_u64() {
-; CHECK: mov.u64 rd0, 0;
+; CHECK: mov.u64 rd{{[0-9]+}}, 0;
 ; CHECK: ret;
 	ret i64 0
 }
 
 define ptx_device float @t1_f32() {
-; CHECK: mov.f32 r0, 0F00000000;
+; CHECK: mov.f32 r{{[0-9]+}}, 0F00000000;
 ; CHECK: ret;
 	ret float 0.0
 }
 
 define ptx_device double @t1_f64() {
-; CHECK: mov.f64 rd0, 0D0000000000000000;
+; CHECK: mov.f64 rd{{[0-9]+}}, 0D0000000000000000;
 ; CHECK: ret;
 	ret double 0.0
 }
 
 define ptx_device i16 @t2_u16(i16 %x) {
-; CHECK: mov.u16 rh0, rh1;
+; CHECK: mov.u16 rh{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK: ret;
 	ret i16 %x
 }
 
 define ptx_device i32 @t2_u32(i32 %x) {
-; CHECK: mov.u32 r0, r1;
+; CHECK: mov.u32 r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK: ret;
 	ret i32 %x
 }
 
 define ptx_device i64 @t2_u64(i64 %x) {
-; CHECK: mov.u64 rd0, rd1;
+; CHECK: mov.u64 rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK: ret;
 	ret i64 %x
 }
 
 define ptx_device float @t3_f32(float %x) {
-; CHECK: mov.u32 r0, r1;
+; CHECK: mov.u32 r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	ret float %x
 }
 
 define ptx_device double @t3_f64(double %x) {
-; CHECK: mov.u64 rd0, rd1;
+; CHECK: mov.u64 rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	ret double %x
 }

Modified: llvm/trunk/test/CodeGen/PTX/mul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mul.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/mul.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/mul.ll Thu Jun 23 13:10:13 2011
@@ -11,28 +11,28 @@
 ;}
 
 define ptx_device float @t1_f32(float %x, float %y) {
-; CHECK: mul.rn.f32 r0, r1, r2
+; CHECK: mul.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-NEXT: ret;
   %z = fmul float %x, %y
   ret float %z
 }
 
 define ptx_device double @t1_f64(double %x, double %y) {
-; CHECK: mul.rn.f64 rd0, rd1, rd2
+; CHECK: mul.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}
 ; CHECK-NEXT: ret;
   %z = fmul double %x, %y
   ret double %z
 }
 
 define ptx_device float @t2_f32(float %x) {
-; CHECK: mul.rn.f32 r0, r1, 0F40A00000;
+; CHECK: mul.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, 0F40A00000;
 ; CHECK-NEXT: ret;
   %z = fmul float %x, 5.0
   ret float %z
 }
 
 define ptx_device double @t2_f64(double %x) {
-; CHECK: mul.rn.f64 rd0, rd1, 0D4014000000000000;
+; CHECK: mul.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, 0D4014000000000000;
 ; CHECK-NEXT: ret;
   %z = fmul double %x, 5.0
   ret double %z

Modified: llvm/trunk/test/CodeGen/PTX/parameter-order.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/parameter-order.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/parameter-order.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/parameter-order.ll Thu Jun 23 13:10:13 2011
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
-; CHECK: .func (.reg .b32 r0) test_parameter_order (.reg .b32 r1, .reg .b32 r2, .reg .b32 r3, .reg .b32 r4)
+; CHECK: .func (.reg .b32 r{{[0-9]+}}) test_parameter_order (.reg .b32 r{{[0-9]+}}, .reg .b32 r{{[0-9]+}}, .reg .b32 r{{[0-9]+}}, .reg .b32 r{{[0-9]+}})
 define ptx_device i32 @test_parameter_order(float %a, i32 %b, i32 %c, float %d) {
-; CHECK: sub.u32 r0, r2, r3
+; CHECK: sub.u32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 	%result = sub i32 %b, %c
 	ret i32 %result
 }

Modified: llvm/trunk/test/CodeGen/PTX/selp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/selp.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/selp.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/selp.ll Thu Jun 23 13:10:13 2011
@@ -1,25 +1,25 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
 define ptx_device i32 @test_selp_i32(i1 %x, i32 %y, i32 %z) {
-; CHECK: selp.u32 r0, r1, r2, p1;
+; CHECK: selp.u32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, p{{[0-9]+}};
 	%a = select i1 %x, i32 %y, i32 %z
 	ret i32 %a
 }
 
 define ptx_device i64 @test_selp_i64(i1 %x, i64 %y, i64 %z) {
-; CHECK: selp.u64 rd0, rd1, rd2, p1;
+; CHECK: selp.u64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}, p{{[0-9]+}};
 	%a = select i1 %x, i64 %y, i64 %z
 	ret i64 %a
 }
 
 define ptx_device float @test_selp_f32(i1 %x, float %y, float %z) {
-; CHECK: selp.f32 r0, r1, r2, p1;
+; CHECK: selp.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}, p{{[0-9]+}};
 	%a = select i1 %x, float %y, float %z
 	ret float %a
 }
 
 define ptx_device double @test_selp_f64(i1 %x, double %y, double %z) {
-; CHECK: selp.f64 rd0, rd1, rd2, p1;
+; CHECK: selp.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}, p{{[0-9]+}};
 	%a = select i1 %x, double %y, double %z
 	ret double %a
 }

Modified: llvm/trunk/test/CodeGen/PTX/setp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/setp.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/setp.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/setp.ll Thu Jun 23 13:10:13 2011
@@ -1,8 +1,8 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
 define ptx_device i32 @test_setp_eq_u32_rr(i32 %x, i32 %y) {
-; CHECK: setp.eq.u32 p0, r1, r2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.eq.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp eq i32 %x, %y
 	%z = zext i1 %p to i32
@@ -10,8 +10,8 @@
 }
 
 define ptx_device i32 @test_setp_ne_u32_rr(i32 %x, i32 %y) {
-; CHECK: setp.ne.u32 p0, r1, r2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.ne.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp ne i32 %x, %y
 	%z = zext i1 %p to i32
@@ -19,8 +19,8 @@
 }
 
 define ptx_device i32 @test_setp_lt_u32_rr(i32 %x, i32 %y) {
-; CHECK: setp.lt.u32 p0, r1, r2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.lt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp ult i32 %x, %y
 	%z = zext i1 %p to i32
@@ -28,8 +28,8 @@
 }
 
 define ptx_device i32 @test_setp_le_u32_rr(i32 %x, i32 %y) {
-; CHECK: setp.le.u32 p0, r1, r2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.le.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp ule i32 %x, %y
 	%z = zext i1 %p to i32
@@ -37,8 +37,8 @@
 }
 
 define ptx_device i32 @test_setp_gt_u32_rr(i32 %x, i32 %y) {
-; CHECK: setp.gt.u32 p0, r1, r2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp ugt i32 %x, %y
 	%z = zext i1 %p to i32
@@ -46,8 +46,8 @@
 }
 
 define ptx_device i32 @test_setp_ge_u32_rr(i32 %x, i32 %y) {
-; CHECK: setp.ge.u32 p0, r1, r2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.ge.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp uge i32 %x, %y
 	%z = zext i1 %p to i32
@@ -55,8 +55,8 @@
 }
 
 define ptx_device i32 @test_setp_lt_s32_rr(i32 %x, i32 %y) {
-; CHECK: setp.lt.s32 p0, r1, r2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.lt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp slt i32 %x, %y
 	%z = zext i1 %p to i32
@@ -64,8 +64,8 @@
 }
 
 define ptx_device i32 @test_setp_le_s32_rr(i32 %x, i32 %y) {
-; CHECK: setp.le.s32 p0, r1, r2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.le.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp sle i32 %x, %y
 	%z = zext i1 %p to i32
@@ -73,8 +73,8 @@
 }
 
 define ptx_device i32 @test_setp_gt_s32_rr(i32 %x, i32 %y) {
-; CHECK: setp.gt.s32 p0, r1, r2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp sgt i32 %x, %y
 	%z = zext i1 %p to i32
@@ -82,8 +82,8 @@
 }
 
 define ptx_device i32 @test_setp_ge_s32_rr(i32 %x, i32 %y) {
-; CHECK: setp.ge.s32 p0, r1, r2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.ge.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp sge i32 %x, %y
 	%z = zext i1 %p to i32
@@ -91,8 +91,8 @@
 }
 
 define ptx_device i32 @test_setp_eq_u32_ri(i32 %x) {
-; CHECK: setp.eq.u32 p0, r1, 1;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.eq.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp eq i32 %x, 1
 	%z = zext i1 %p to i32
@@ -100,8 +100,8 @@
 }
 
 define ptx_device i32 @test_setp_ne_u32_ri(i32 %x) {
-; CHECK: setp.ne.u32 p0, r1, 1;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.ne.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp ne i32 %x, 1
 	%z = zext i1 %p to i32
@@ -109,8 +109,8 @@
 }
 
 define ptx_device i32 @test_setp_lt_u32_ri(i32 %x) {
-; CHECK: setp.eq.u32 p0, r1, 0;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.eq.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp ult i32 %x, 1
 	%z = zext i1 %p to i32
@@ -118,8 +118,8 @@
 }
 
 define ptx_device i32 @test_setp_le_u32_ri(i32 %x) {
-; CHECK: setp.lt.u32 p0, r1, 2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.lt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 2;
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp ule i32 %x, 1
 	%z = zext i1 %p to i32
@@ -127,8 +127,8 @@
 }
 
 define ptx_device i32 @test_setp_gt_u32_ri(i32 %x) {
-; CHECK: setp.gt.u32 p0, r1, 1;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp ugt i32 %x, 1
 	%z = zext i1 %p to i32
@@ -136,8 +136,8 @@
 }
 
 define ptx_device i32 @test_setp_ge_u32_ri(i32 %x) {
-; CHECK: setp.ne.u32 p0, r1, 0;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.ne.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp uge i32 %x, 1
 	%z = zext i1 %p to i32
@@ -145,8 +145,8 @@
 }
 
 define ptx_device i32 @test_setp_lt_s32_ri(i32 %x) {
-; CHECK: setp.lt.s32 p0, r1, 1;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.lt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp slt i32 %x, 1
 	%z = zext i1 %p to i32
@@ -154,8 +154,8 @@
 }
 
 define ptx_device i32 @test_setp_le_s32_ri(i32 %x) {
-; CHECK: setp.lt.s32 p0, r1, 2;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.lt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 2;
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp sle i32 %x, 1
 	%z = zext i1 %p to i32
@@ -163,8 +163,8 @@
 }
 
 define ptx_device i32 @test_setp_gt_s32_ri(i32 %x) {
-; CHECK: setp.gt.s32 p0, r1, 1;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp sgt i32 %x, 1
 	%z = zext i1 %p to i32
@@ -172,8 +172,8 @@
 }
 
 define ptx_device i32 @test_setp_ge_s32_ri(i32 %x) {
-; CHECK: setp.gt.s32 p0, r1, 0;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%p = icmp sge i32 %x, 1
 	%z = zext i1 %p to i32
@@ -181,9 +181,9 @@
 }
 
 define ptx_device i32 @test_setp_4_op_format_1(i32 %x, i32 %y, i32 %u, i32 %v) {
-; CHECK: setp.gt.u32 p0, r3, r4;
-; CHECK-NEXT: setp.eq.and.u32 p0, r1, r2, p0;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: setp.eq.and.u32 p[[P0]], r{{[0-9]+}}, r{{[0-9]+}}, p[[P0]];
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%c = icmp eq i32 %x, %y
 	%d = icmp ugt i32 %u, %v
@@ -193,9 +193,9 @@
 }
 
 define ptx_device i32 @test_setp_4_op_format_2(i32 %x, i32 %y, i32 %w) {
-; CHECK: setp.gt.b32 p0, r3, 0;
-; CHECK-NEXT: setp.eq.and.u32 p0, r1, r2, !p0;
-; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
+; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
+; CHECK-NEXT: setp.eq.and.u32 p[[P0]], r{{[0-9]+}}, r{{[0-9]+}}, !p[[P0]];
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;
 	%c = trunc i32 %w to i1
 	%d = icmp eq i32 %x, %y

Modified: llvm/trunk/test/CodeGen/PTX/shl.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/shl.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/shl.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/shl.ll Thu Jun 23 13:10:13 2011
@@ -1,21 +1,21 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
 define ptx_device i32 @t1(i32 %x, i32 %y) {
-; CHECK: shl.b32 r0, r1, r2
+; CHECK: shl.b32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 	%z = shl i32 %x, %y
 ; CHECK: ret;
 	ret i32 %z
 }
 
 define ptx_device i32 @t2(i32 %x) {
-; CHECK: shl.b32 r0, r1, 3
+; CHECK: shl.b32 r{{[0-9]+}}, r{{[0-9]+}}, 3
 	%z = shl i32 %x, 3
 ; CHECK: ret;
 	ret i32 %z
 }
 
 define ptx_device i32 @t3(i32 %x) {
-; CHECK: shl.b32 r0, 3, r1
+; CHECK: shl.b32 r{{[0-9]+}}, 3, r{{[0-9]+}}
 	%z = shl i32 3, %x
 ; CHECK: ret;
 	ret i32 %z

Modified: llvm/trunk/test/CodeGen/PTX/shr.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/shr.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/shr.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/shr.ll Thu Jun 23 13:10:13 2011
@@ -1,42 +1,42 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
 define ptx_device i32 @t1(i32 %x, i32 %y) {
-; CHECK: shr.u32 r0, r1, r2
+; CHECK: shr.u32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 	%z = lshr i32 %x, %y
 ; CHECK: ret;
 	ret i32 %z
 }
 
 define ptx_device i32 @t2(i32 %x) {
-; CHECK: shr.u32 r0, r1, 3
+; CHECK: shr.u32 r{{[0-9]+}}, r{{[0-9]+}}, 3
 	%z = lshr i32 %x, 3
 ; CHECK: ret;
 	ret i32 %z
 }
 
 define ptx_device i32 @t3(i32 %x) {
-; CHECK: shr.u32 r0, 3, r1
+; CHECK: shr.u32 r{{[0-9]+}}, 3, r{{[0-9]+}}
 	%z = lshr i32 3, %x
 ; CHECK: ret;
 	ret i32 %z
 }
 
 define ptx_device i32 @t4(i32 %x, i32 %y) {
-; CHECK: shr.s32 r0, r1, r2
+; CHECK: shr.s32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 	%z = ashr i32 %x, %y
 ; CHECK: ret;
 	ret i32 %z
 }
 
 define ptx_device i32 @t5(i32 %x) {
-; CHECK: shr.s32 r0, r1, 3
+; CHECK: shr.s32 r{{[0-9]+}}, r{{[0-9]+}}, 3
 	%z = ashr i32 %x, 3
 ; CHECK: ret;
 	ret i32 %z
 }
 
 define ptx_device i32 @t6(i32 %x) {
-; CHECK: shr.s32 r0, -3, r1
+; CHECK: shr.s32 r{{[0-9]+}}, -3, r{{[0-9]+}}
 	%z = ashr i32 -3, %x
 ; CHECK: ret;
 	ret i32 %z

Modified: llvm/trunk/test/CodeGen/PTX/st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/st.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/st.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/st.ll Thu Jun 23 13:10:13 2011
@@ -63,7 +63,7 @@
 
 define ptx_device void @t1_u16(i16* %p, i16 %x) {
 entry:
-;CHECK: st.global.u16 [r1], rh1;
+;CHECK: st.global.u16 [r{{[0-9]+}}], rh{{[0-9]+}};
 ;CHECK-NEXT: ret;
   store i16 %x, i16* %p
   ret void
@@ -71,7 +71,7 @@
 
 define ptx_device void @t1_u32(i32* %p, i32 %x) {
 entry:
-;CHECK: st.global.u32 [r1], r2;
+;CHECK: st.global.u32 [r{{[0-9]+}}], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   store i32 %x, i32* %p
   ret void
@@ -79,7 +79,7 @@
 
 define ptx_device void @t1_u64(i64* %p, i64 %x) {
 entry:
-;CHECK: st.global.u64 [r1], rd1;
+;CHECK: st.global.u64 [r{{[0-9]+}}], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   store i64 %x, i64* %p
   ret void
@@ -87,7 +87,7 @@
 
 define ptx_device void @t1_f32(float* %p, float %x) {
 entry:
-;CHECK: st.global.f32 [r1], r2;
+;CHECK: st.global.f32 [r{{[0-9]+}}], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   store float %x, float* %p
   ret void
@@ -95,7 +95,7 @@
 
 define ptx_device void @t1_f64(double* %p, double %x) {
 entry:
-;CHECK: st.global.f64 [r1], rd1;
+;CHECK: st.global.f64 [r{{[0-9]+}}], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   store double %x, double* %p
   ret void
@@ -103,7 +103,7 @@
 
 define ptx_device void @t2_u16(i16* %p, i16 %x) {
 entry:
-;CHECK: st.global.u16 [r1+2], rh1;
+;CHECK: st.global.u16 [r{{[0-9]+}}+2], rh{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr i16* %p, i32 1
   store i16 %x, i16* %i
@@ -112,7 +112,7 @@
 
 define ptx_device void @t2_u32(i32* %p, i32 %x) {
 entry:
-;CHECK: st.global.u32 [r1+4], r2;
+;CHECK: st.global.u32 [r{{[0-9]+}}+4], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr i32* %p, i32 1
   store i32 %x, i32* %i
@@ -121,7 +121,7 @@
 
 define ptx_device void @t2_u64(i64* %p, i64 %x) {
 entry:
-;CHECK: st.global.u64 [r1+8], rd1;
+;CHECK: st.global.u64 [r{{[0-9]+}}+8], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr i64* %p, i32 1
   store i64 %x, i64* %i
@@ -130,7 +130,7 @@
 
 define ptx_device void @t2_f32(float* %p, float %x) {
 entry:
-;CHECK: st.global.f32 [r1+4], r2;
+;CHECK: st.global.f32 [r{{[0-9]+}}+4], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr float* %p, i32 1
   store float %x, float* %i
@@ -139,7 +139,7 @@
 
 define ptx_device void @t2_f64(double* %p, double %x) {
 entry:
-;CHECK: st.global.f64 [r1+8], rd1;
+;CHECK: st.global.f64 [r{{[0-9]+}}+8], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr double* %p, i32 1
   store double %x, double* %i
@@ -148,9 +148,9 @@
 
 define ptx_device void @t3_u16(i16* %p, i32 %q, i16 %x) {
 entry:
-;CHECK: shl.b32 r0, r2, 1;
-;CHECK-NEXT: add.u32 r0, r1, r0;
-;CHECK-NEXT: st.global.u16 [r0], rh1;
+;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 1;
+;CHECK-NEXT: add.u32 r[[R0]], r{{[0-9]+}}, r[[R0]];
+;CHECK-NEXT: st.global.u16 [r[[R0]]], rh{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr i16* %p, i32 %q
   store i16 %x, i16* %i
@@ -159,9 +159,9 @@
 
 define ptx_device void @t3_u32(i32* %p, i32 %q, i32 %x) {
 entry:
-;CHECK: shl.b32 r0, r2, 2;
-;CHECK-NEXT: add.u32 r0, r1, r0;
-;CHECK-NEXT: st.global.u32 [r0], r3;
+;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 2;
+;CHECK-NEXT: add.u32 r[[R0]], r{{[0-9]+}}, r[[R0]];
+;CHECK-NEXT: st.global.u32 [r[[R0]]], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr i32* %p, i32 %q
   store i32 %x, i32* %i
@@ -170,9 +170,9 @@
 
 define ptx_device void @t3_u64(i64* %p, i32 %q, i64 %x) {
 entry:
-;CHECK: shl.b32 r0, r2, 3;
-;CHECK-NEXT: add.u32 r0, r1, r0;
-;CHECK-NEXT: st.global.u64 [r0], rd1;
+;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 3;
+;CHECK-NEXT: add.u32 r[[R0]], r{{[0-9]+}}, r[[R0]];
+;CHECK-NEXT: st.global.u64 [r[[R0]]], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr i64* %p, i32 %q
   store i64 %x, i64* %i
@@ -181,9 +181,9 @@
 
 define ptx_device void @t3_f32(float* %p, i32 %q, float %x) {
 entry:
-;CHECK: shl.b32 r0, r2, 2;
-;CHECK-NEXT: add.u32 r0, r1, r0;
-;CHECK-NEXT: st.global.f32 [r0], r3;
+;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 2;
+;CHECK-NEXT: add.u32 r[[R0]], r{{[0-9]+}}, r[[R0]];
+;CHECK-NEXT: st.global.f32 [r[[R0]]], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr float* %p, i32 %q
   store float %x, float* %i
@@ -192,9 +192,9 @@
 
 define ptx_device void @t3_f64(double* %p, i32 %q, double %x) {
 entry:
-;CHECK: shl.b32 r0, r2, 3;
-;CHECK-NEXT: add.u32 r0, r1, r0;
-;CHECK-NEXT: st.global.f64 [r0], rd1;
+;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 3;
+;CHECK-NEXT: add.u32 r[[R0]], r{{[0-9]+}}, r[[R0]];
+;CHECK-NEXT: st.global.f64 [r[[R0]]], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr double* %p, i32 %q
   store double %x, double* %i
@@ -203,8 +203,8 @@
 
 define ptx_device void @t4_global_u16(i16 %x) {
 entry:
-;CHECK: mov.u32 r0, array_i16;
-;CHECK-NEXT: st.global.u16 [r0], rh1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
+;CHECK-NEXT: st.global.u16 [r[[R0]]], rh{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i16]* @array_i16, i16 0, i16 0
   store i16 %x, i16* %i
@@ -213,8 +213,8 @@
 
 define ptx_device void @t4_global_u32(i32 %x) {
 entry:
-;CHECK: mov.u32 r0, array_i32;
-;CHECK-NEXT: st.global.u32 [r0], r1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i32;
+;CHECK-NEXT: st.global.u32 [r[[R0]]], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 0
   store i32 %x, i32* %i
@@ -223,8 +223,8 @@
 
 define ptx_device void @t4_global_u64(i64 %x) {
 entry:
-;CHECK: mov.u32 r0, array_i64;
-;CHECK-NEXT: st.global.u64 [r0], rd1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i64;
+;CHECK-NEXT: st.global.u64 [r[[R0]]], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 0
   store i64 %x, i64* %i
@@ -233,8 +233,8 @@
 
 define ptx_device void @t4_global_f32(float %x) {
 entry:
-;CHECK: mov.u32 r0, array_float;
-;CHECK-NEXT: st.global.f32 [r0], r1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_float;
+;CHECK-NEXT: st.global.f32 [r[[R0]]], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x float]* @array_float, i32 0, i32 0
   store float %x, float* %i
@@ -243,8 +243,8 @@
 
 define ptx_device void @t4_global_f64(double %x) {
 entry:
-;CHECK: mov.u32 r0, array_double;
-;CHECK-NEXT: st.global.f64 [r0], rd1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_double;
+;CHECK-NEXT: st.global.f64 [r[[R0]]], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x double]* @array_double, i32 0, i32 0
   store double %x, double* %i
@@ -253,8 +253,8 @@
 
 define ptx_device void @t4_local_u16(i16 %x) {
 entry:
-;CHECK: mov.u32 r0, array_local_i16;
-;CHECK-NEXT: st.local.u16 [r0], rh1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i16;
+;CHECK-NEXT: st.local.u16 [r[[R0]]], rh{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i16] addrspace(2)* @array_local_i16, i32 0, i32 0
   store i16 %x, i16 addrspace(2)* %i
@@ -263,8 +263,8 @@
 
 define ptx_device void @t4_local_u32(i32 %x) {
 entry:
-;CHECK: mov.u32 r0, array_local_i32;
-;CHECK-NEXT: st.local.u32 [r0], r1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i32;
+;CHECK-NEXT: st.local.u32 [r[[R0]]], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i32] addrspace(2)* @array_local_i32, i32 0, i32 0
   store i32 %x, i32 addrspace(2)* %i
@@ -273,8 +273,8 @@
 
 define ptx_device void @t4_local_u64(i64 %x) {
 entry:
-;CHECK: mov.u32 r0, array_local_i64;
-;CHECK-NEXT: st.local.u64 [r0], rd1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i64;
+;CHECK-NEXT: st.local.u64 [r[[R0]]], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i64] addrspace(2)* @array_local_i64, i32 0, i32 0
   store i64 %x, i64 addrspace(2)* %i
@@ -283,8 +283,8 @@
 
 define ptx_device void @t4_local_f32(float %x) {
 entry:
-;CHECK: mov.u32 r0, array_local_float;
-;CHECK-NEXT: st.local.f32 [r0], r1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_float;
+;CHECK-NEXT: st.local.f32 [r[[R0]]], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x float] addrspace(2)* @array_local_float, i32 0, i32 0
   store float %x, float addrspace(2)* %i
@@ -293,8 +293,8 @@
 
 define ptx_device void @t4_local_f64(double %x) {
 entry:
-;CHECK: mov.u32 r0, array_local_double;
-;CHECK-NEXT: st.local.f64 [r0], rd1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_double;
+;CHECK-NEXT: st.local.f64 [r[[R0]]], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x double] addrspace(2)* @array_local_double, i32 0, i32 0
   store double %x, double addrspace(2)* %i
@@ -303,8 +303,8 @@
 
 define ptx_device void @t4_shared_u16(i16 %x) {
 entry:
-;CHECK: mov.u32 r0, array_shared_i16;
-;CHECK-NEXT: st.shared.u16 [r0], rh1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i16;
+;CHECK-NEXT: st.shared.u16 [r[[R0]]], rh{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i16] addrspace(4)* @array_shared_i16, i32 0, i32 0
   store i16 %x, i16 addrspace(4)* %i
@@ -313,8 +313,8 @@
 
 define ptx_device void @t4_shared_u32(i32 %x) {
 entry:
-;CHECK: mov.u32 r0, array_shared_i32;
-;CHECK-NEXT: st.shared.u32 [r0], r1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i32;
+;CHECK-NEXT: st.shared.u32 [r[[R0]]], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i32] addrspace(4)* @array_shared_i32, i32 0, i32 0
   store i32 %x, i32 addrspace(4)* %i
@@ -323,8 +323,8 @@
 
 define ptx_device void @t4_shared_u64(i64 %x) {
 entry:
-;CHECK: mov.u32 r0, array_shared_i64;
-;CHECK-NEXT: st.shared.u64 [r0], rd1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i64;
+;CHECK-NEXT: st.shared.u64 [r[[R0]]], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i64] addrspace(4)* @array_shared_i64, i32 0, i32 0
   store i64 %x, i64 addrspace(4)* %i
@@ -333,8 +333,8 @@
 
 define ptx_device void @t4_shared_f32(float %x) {
 entry:
-;CHECK: mov.u32 r0, array_shared_float;
-;CHECK-NEXT: st.shared.f32 [r0], r1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_float;
+;CHECK-NEXT: st.shared.f32 [r[[R0]]], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x float] addrspace(4)* @array_shared_float, i32 0, i32 0
   store float %x, float addrspace(4)* %i
@@ -343,8 +343,8 @@
 
 define ptx_device void @t4_shared_f64(double %x) {
 entry:
-;CHECK: mov.u32 r0, array_shared_double;
-;CHECK-NEXT: st.shared.f64 [r0], rd1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_double;
+;CHECK-NEXT: st.shared.f64 [r[[R0]]], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x double] addrspace(4)* @array_shared_double, i32 0, i32 0
   store double %x, double addrspace(4)* %i
@@ -353,8 +353,8 @@
 
 define ptx_device void @t5_u16(i16 %x) {
 entry:
-;CHECK: mov.u32 r0, array_i16;
-;CHECK-NEXT: st.global.u16 [r0+2], rh1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
+;CHECK-NEXT: st.global.u16 [r[[R0]]+2], rh{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i16]* @array_i16, i32 0, i32 1
   store i16 %x, i16* %i
@@ -363,8 +363,8 @@
 
 define ptx_device void @t5_u32(i32 %x) {
 entry:
-;CHECK: mov.u32 r0, array_i32;
-;CHECK-NEXT: st.global.u32 [r0+4], r1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i32;
+;CHECK-NEXT: st.global.u32 [r[[R0]]+4], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i32]* @array_i32, i32 0, i32 1
   store i32 %x, i32* %i
@@ -373,8 +373,8 @@
 
 define ptx_device void @t5_u64(i64 %x) {
 entry:
-;CHECK: mov.u32 r0, array_i64;
-;CHECK-NEXT: st.global.u64 [r0+8], rd1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i64;
+;CHECK-NEXT: st.global.u64 [r[[R0]]+8], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x i64]* @array_i64, i32 0, i32 1
   store i64 %x, i64* %i
@@ -383,8 +383,8 @@
 
 define ptx_device void @t5_f32(float %x) {
 entry:
-;CHECK: mov.u32 r0, array_float;
-;CHECK-NEXT: st.global.f32 [r0+4], r1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_float;
+;CHECK-NEXT: st.global.f32 [r[[R0]]+4], r{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x float]* @array_float, i32 0, i32 1
   store float %x, float* %i
@@ -393,8 +393,8 @@
 
 define ptx_device void @t5_f64(double %x) {
 entry:
-;CHECK: mov.u32 r0, array_double;
-;CHECK-NEXT: st.global.f64 [r0+8], rd1;
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_double;
+;CHECK-NEXT: st.global.f64 [r[[R0]]+8], rd{{[0-9]+}};
 ;CHECK-NEXT: ret;
   %i = getelementptr [10 x double]* @array_double, i32 0, i32 1
   store double %x, double* %i

Modified: llvm/trunk/test/CodeGen/PTX/sub.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/sub.ll?rev=133736&r1=133735&r2=133736&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/sub.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/sub.ll Thu Jun 23 13:10:13 2011
@@ -1,70 +1,70 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
 define ptx_device i16 @t1_u16(i16 %x, i16 %y) {
-; CHECK: sub.u16 rh0, rh1, rh2;
+; CHECK: sub.u16 rh{{[0-9]+}}, rh{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%z = sub i16 %x, %y
 	ret i16 %z
 }
 
 define ptx_device i32 @t1_u32(i32 %x, i32 %y) {
-; CHECK: sub.u32 r0, r1, r2;
+; CHECK: sub.u32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%z = sub i32 %x, %y
 	ret i32 %z
 }
 
 define ptx_device i64 @t1_u64(i64 %x, i64 %y) {
-; CHECK: sub.u64 rd0, rd1, rd2;
+; CHECK: sub.u64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}};
 ; CHECK-NEXT: ret;
 	%z = sub i64 %x, %y
 	ret i64 %z
 }
 
 define ptx_device float @t1_f32(float %x, float %y) {
-; CHECK: sub.rn.f32 r0, r1, r2
+; CHECK: sub.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, r{{[0-9]+}}
 ; CHECK-NEXT: ret;
   %z = fsub float %x, %y
   ret float %z
 }
 
 define ptx_device double @t1_f64(double %x, double %y) {
-; CHECK: sub.rn.f64 rd0, rd1, rd2
+; CHECK: sub.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, rd{{[0-9]+}}
 ; CHECK-NEXT: ret;
   %z = fsub double %x, %y
   ret double %z
 }
 
 define ptx_device i16 @t2_u16(i16 %x) {
-; CHECK: add.u16 rh0, rh1, -1;
+; CHECK: add.u16 rh{{[0-9]+}}, rh{{[0-9]+}}, -1;
 ; CHECK-NEXT: ret;
 	%z = sub i16 %x, 1
 	ret i16 %z
 }
 
 define ptx_device i32 @t2_u32(i32 %x) {
-; CHECK: add.u32 r0, r1, -1;
+; CHECK: add.u32 r{{[0-9]+}}, r{{[0-9]+}}, -1;
 ; CHECK-NEXT: ret;
 	%z = sub i32 %x, 1
 	ret i32 %z
 }
 
 define ptx_device i64 @t2_u64(i64 %x) {
-; CHECK: add.u64 rd0, rd1, -1;
+; CHECK: add.u64 rd{{[0-9]+}}, rd{{[0-9]+}}, -1;
 ; CHECK-NEXT: ret;
 	%z = sub i64 %x, 1
 	ret i64 %z
 }
 
 define ptx_device float @t2_f32(float %x) {
-; CHECK: add.rn.f32 r0, r1, 0FBF800000;
+; CHECK: add.rn.f32 r{{[0-9]+}}, r{{[0-9]+}}, 0FBF800000;
 ; CHECK-NEXT: ret;
   %z = fsub float %x, 1.0
   ret float %z
 }
 
 define ptx_device double @t2_f64(double %x) {
-; CHECK: add.rn.f64 rd0, rd1, 0DBFF0000000000000;
+; CHECK: add.rn.f64 rd{{[0-9]+}}, rd{{[0-9]+}}, 0DBFF0000000000000;
 ; CHECK-NEXT: ret;
   %z = fsub double %x, 1.0
   ret double %z



From evan.cheng at apple.com  Thu Jun 23 13:15:17 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 23 Jun 2011 18:15:17 -0000
Subject: [llvm-commits] [llvm] r133738 - in /llvm/trunk/lib/Target/ARM:
 ARMSubtarget.cpp ARMTargetMachine.cpp
Message-ID: <20110623181517.8C1B32A6C12C@llvm.org>

Author: evancheng
Date: Thu Jun 23 13:15:17 2011
New Revision: 133738

URL: http://llvm.org/viewvc/llvm-project?rev=133738&view=rev
Log:
Remove TargetOptions.h dependency from ARMSubtarget.

Modified:
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
    llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=133738&r1=133737&r2=133738&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Thu Jun 23 13:15:17 2011
@@ -15,7 +15,6 @@
 #include "ARMGenSubtarget.inc"
 #include "ARMBaseRegisterInfo.h"
 #include "llvm/GlobalValue.h"
-#include "llvm/Target/TargetOptions.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/ADT/SmallVector.h"
 using namespace llvm;
@@ -60,10 +59,6 @@
   , CPUString("generic")
   , TargetTriple(TT)
   , TargetABI(ARM_ABI_APCS) {
-  // Default to soft float ABI
-  if (FloatABIType == FloatABI::Default)
-    FloatABIType = FloatABI::Soft;
-
   // Determine default and user specified characteristics
 
   // When no arch is specified either by CPU or by attributes, make the default

Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=133738&r1=133737&r2=133738&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Thu Jun 23 13:15:17 2011
@@ -85,6 +85,10 @@
     JITInfo(),
     InstrItins(Subtarget.getInstrItineraryData()) {
   DefRelocModel = getRelocationModel();
+
+  // Default to soft float ABI
+  if (FloatABIType == FloatABI::Default)
+    FloatABIType = FloatABI::Soft;
 }
 
 ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT,



From evan.cheng at apple.com  Thu Jun 23 13:15:48 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 23 Jun 2011 18:15:48 -0000
Subject: [llvm-commits] [llvm] r133739 - in /llvm/trunk:
 include/llvm/Target/TargetOptions.h lib/Target/TargetMachine.cpp
 lib/Target/X86/X86TargetMachine.cpp
Message-ID: <20110623181548.4536A2A6C12C@llvm.org>

Author: evancheng
Date: Thu Jun 23 13:15:47 2011
New Revision: 133739

URL: http://llvm.org/viewvc/llvm-project?rev=133739&view=rev
Log:
Rename TargetOptions::StackAlignment to StackAlignmentOverride.

Modified:
    llvm/trunk/include/llvm/Target/TargetOptions.h
    llvm/trunk/lib/Target/TargetMachine.cpp
    llvm/trunk/lib/Target/X86/X86TargetMachine.cpp

Modified: llvm/trunk/include/llvm/Target/TargetOptions.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetOptions.h?rev=133739&r1=133738&r2=133739&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetOptions.h (original)
+++ llvm/trunk/include/llvm/Target/TargetOptions.h Thu Jun 23 13:15:47 2011
@@ -133,8 +133,8 @@
   /// as their parent function, etc.), using an alternate ABI if necessary.
   extern bool GuaranteedTailCallOpt;
 
-  /// StackAlignment - Override default stack alignment for target.
-  extern unsigned StackAlignment;
+  /// StackAlignmentOverride - Override default stack alignment for target.
+  extern unsigned StackAlignmentOverride;
 
   /// RealignStack - This flag indicates whether the stack should be
   /// automatically realigned, if needed.

Modified: llvm/trunk/lib/Target/TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetMachine.cpp?rev=133739&r1=133738&r2=133739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/TargetMachine.cpp Thu Jun 23 13:15:47 2011
@@ -43,7 +43,7 @@
   Reloc::Model RelocationModel;
   CodeModel::Model CMModel;
   bool GuaranteedTailCallOpt;
-  unsigned StackAlignment;
+  unsigned StackAlignmentOverride;
   bool RealignStack;
   bool DisableJumpTables;
   bool StrongPHIElim;
@@ -183,7 +183,7 @@
 static cl::opt<unsigned, true>
 OverrideStackAlignment("stack-alignment",
   cl::desc("Override default stack alignment"),
-  cl::location(StackAlignment),
+  cl::location(StackAlignmentOverride),
   cl::init(0));
 static cl::opt<bool, true>
 EnableRealignStack("realign-stack",

Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=133739&r1=133738&r2=133739&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Thu Jun 23 13:15:47 2011
@@ -117,7 +117,7 @@
 X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT,
                                    const std::string &FS, bool is64Bit)
   : LLVMTargetMachine(T, TT),
-    Subtarget(TT, FS, is64Bit, StackAlignment),
+    Subtarget(TT, FS, is64Bit, StackAlignmentOverride),
     FrameLowering(*this, Subtarget),
     ELFWriterInfo(is64Bit, true) {
   DefRelocModel = getRelocationModel();



From atrick at apple.com  Thu Jun 23 13:23:10 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 23 Jun 2011 11:23:10 -0700
Subject: [llvm-commits] [llvm] r133664 - in /llvm/trunk:
 cmake/modules/HandleLLVMOptions.cmake
 test/CodeGen/X86/2011-06-14-PreschedRegalias.ll test/Makefile test/lit.cfg
 test/lit.site.cfg.in utils/lit/lit/TestRunner.py
 utils/lit/lit/TestingConfig.py
In-Reply-To: <C563B360-C5D2-467B-A7FA-B46D47DC24F0@gmail.com>
References: <20110622232319.9B2BE2A6C12C@llvm.org>
	<C563B360-C5D2-467B-A7FA-B46D47DC24F0@gmail.com>
Message-ID: <E144830B-B9B8-49B1-A027-8A9638807947@apple.com>

Thanks Justin. I was mistakenly testing cmake by explicitly setting the option to 0/1 on the command line. 

r133725 should fix it.

-Andy

On Jun 23, 2011, at 9:09 AM, Justin Holewinski wrote:

> This seems to be breaking the regression tests for me on OS X, with Python 2.7 and CMake 2.8.4.  Specifically, the line:
> 
> config.enable_assertions = @LLVM_ENABLE_ASSERTIONS@
> 
> For me, this is being configured as:
> 
> config.enable_assertions = ON
> 
> which is invalid Python (symbol 'ON' does not exist).  Manually changing this to:
> 
> config.enable_assertions = 1
> 
> fixes the issue.
> 
> 
> Seems to be a CMake naming issue (using ON instead of 1)
> 
> On Jun 22, 2011, at 7:23 PM, Andrew Trick wrote:
> 
>> Author: atrick
>> Date: Wed Jun 22 18:23:19 2011
>> New Revision: 133664
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=133664&view=rev
>> Log:
>> lit support for REQUIRES: asserts.
>> 
>> Take #2. Don't piggyback on the existing config.build_mode. Instead,
>> define a new lit feature for each build feature we need (currently
>> just "asserts"). Teach both autoconf'd and cmake'd Makefiles to define
>> this feature within test/lit.site.cfg. This doesn't require any lit
>> harness changes and should be more robust across build systems.
>> 
>> Modified:
>>    llvm/trunk/cmake/modules/HandleLLVMOptions.cmake
>>    llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
>>    llvm/trunk/test/Makefile
>>    llvm/trunk/test/lit.cfg
>>    llvm/trunk/test/lit.site.cfg.in
>>    llvm/trunk/utils/lit/lit/TestRunner.py
>>    llvm/trunk/utils/lit/lit/TestingConfig.py
>> 
>> Modified: llvm/trunk/cmake/modules/HandleLLVMOptions.cmake
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/HandleLLVMOptions.cmake?rev=133664&r1=133663&r2=133664&view=diff
>> ==============================================================================
>> --- llvm/trunk/cmake/modules/HandleLLVMOptions.cmake (original)
>> +++ llvm/trunk/cmake/modules/HandleLLVMOptions.cmake Wed Jun 22 18:23:19 2011
>> @@ -36,13 +36,8 @@
>>   # explicitly undefine it:
>>   if( uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" )
>>     add_definitions( -UNDEBUG )
>> -    set(LLVM_BUILD_MODE "Release")
>> -  else()
>> -    set(LLVM_BUILD_MODE "Debug")
>>   endif()
>> -  set(LLVM_BUILD_MODE "${LLVM_BUILD_MODE}+Asserts")
>> else()
>> -  set(LLVM_BUILD_MODE "Release")
>>   if( NOT uppercase_CMAKE_BUILD_TYPE STREQUAL "RELEASE" )
>>     if( NOT MSVC_IDE AND NOT XCODE )
>>       add_definitions( -DNDEBUG )
>> 
>> Modified: llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll?rev=133664&r1=133663&r2=133664&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll (original)
>> +++ llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll Wed Jun 22 18:23:19 2011
>> @@ -1,5 +1,5 @@
>> ; RUN: llc < %s -march=x86-64 -stress-sched | FileCheck %s
>> -; REQUIRES: Asserts
>> +; REQUIRES: asserts
>> ; Test interference between physreg aliases during preRAsched.
>> ; mul wants an operand in AL, but call clobbers it.
>> 
>> 
>> Modified: llvm/trunk/test/Makefile
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Makefile?rev=133664&r1=133663&r2=133664&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/Makefile (original)
>> +++ llvm/trunk/test/Makefile Wed Jun 22 18:23:19 2011
>> @@ -171,15 +171,21 @@
>> 	@test ! -f site.exp || mv site.exp site.bak
>> 	@mv site.tmp site.exp
>> 
>> +ifeq ($(DISABLE_ASSERTIONS),1)
>> +ENABLE_ASSERTIONS=0
>> +else
>> +ENABLE_ASSERTIONS=1
>> +endif
>> +
>> lit.site.cfg: site.exp
>> 	@echo "Making LLVM 'lit.site.cfg' file..."
>> 	@$(ECHOPATH) s=@LLVM_SOURCE_DIR@=$(LLVM_SRC_ROOT)=g > lit.tmp
>> 	@$(ECHOPATH) s=@LLVM_BINARY_DIR@=$(LLVM_OBJ_ROOT)=g >> lit.tmp
>> 	@$(ECHOPATH) s=@LLVM_TOOLS_DIR@=$(ToolDir)=g >> lit.tmp
>> -	@$(ECHOPATH) s=@LLVM_BUILD_MODE@=$(BuildMode)=g >> lit.tmp
>> 	@$(ECHOPATH) s=@LLVMGCCDIR@=$(LLVMGCCDIR)=g >> lit.tmp
>> 	@$(ECHOPATH) s=@PYTHON_EXECUTABLE@=python=g >> lit.tmp
>> 	@$(ECHOPATH) s=@ENABLE_SHARED@=$(ENABLE_SHARED)=g >> lit.tmp
>> +	@$(ECHOPATH) s=@LLVM_ENABLE_ASSERTIONS@=$(ENABLE_ASSERTIONS)=g >> lit.tmp
>> 	@sed -f lit.tmp $(PROJ_SRC_DIR)/lit.site.cfg.in > $@
>> 	@-rm -f lit.tmp
>> 
>> 
>> Modified: llvm/trunk/test/lit.cfg
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.cfg?rev=133664&r1=133663&r2=133664&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/lit.cfg (original)
>> +++ llvm/trunk/test/lit.cfg Wed Jun 22 18:23:19 2011
>> @@ -306,3 +306,6 @@
>> 
>> if loadable_module:
>>     config.available_features.add('loadable_module')
>> +
>> +if config.enable_assertions:
>> +    config.available_features.add('asserts')
>> 
>> Modified: llvm/trunk/test/lit.site.cfg.in
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/lit.site.cfg.in?rev=133664&r1=133663&r2=133664&view=diff
>> ==============================================================================
>> --- llvm/trunk/test/lit.site.cfg.in (original)
>> +++ llvm/trunk/test/lit.site.cfg.in Wed Jun 22 18:23:19 2011
>> @@ -5,9 +5,9 @@
>> config.llvm_tools_dir = "@LLVM_TOOLS_DIR@"
>> config.llvmgcc_dir = "@LLVMGCCDIR@"
>> config.lit_tools_dir = "@LLVM_LIT_TOOLS_DIR@"
>> -config.llvm_build_modes = "@LLVM_BUILD_MODE@".split('+')
>> config.python_executable = "@PYTHON_EXECUTABLE@"
>> config.enable_shared = @ENABLE_SHARED@
>> +config.enable_assertions = @LLVM_ENABLE_ASSERTIONS@
>> 
>> # Support substitution of the tools_dir with user parameters. This is
>> # used when we can't determine the tool dir at configuration time.
>> 
>> Modified: llvm/trunk/utils/lit/lit/TestRunner.py
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestRunner.py?rev=133664&r1=133663&r2=133664&view=diff
>> ==============================================================================
>> --- llvm/trunk/utils/lit/lit/TestRunner.py (original)
>> +++ llvm/trunk/utils/lit/lit/TestRunner.py Wed Jun 22 18:23:19 2011
>> @@ -473,11 +473,9 @@
>>     if script[-1][-1] == '\\':
>>         return (Test.UNRESOLVED, "Test has unterminated run lines (with '\\')")
>> 
>> -    # Check that we have the required features or build modes:
>> +    # Check that we have the required features:
>>     missing_required_features = [f for f in requires
>> -                                 if f not in test.config.available_features
>> -                                 and f not in test.config.llvm_build_modes]
>> -
>> +                                 if f not in test.config.available_features]
>>     if missing_required_features:
>>         msg = ', '.join(missing_required_features)
>>         return (Test.UNSUPPORTED,
>> 
>> Modified: llvm/trunk/utils/lit/lit/TestingConfig.py
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/lit/lit/TestingConfig.py?rev=133664&r1=133663&r2=133664&view=diff
>> ==============================================================================
>> --- llvm/trunk/utils/lit/lit/TestingConfig.py (original)
>> +++ llvm/trunk/utils/lit/lit/TestingConfig.py Wed Jun 22 18:23:19 2011
>> @@ -74,7 +74,6 @@
>> 
>>     def clone(self, path):
>>         # FIXME: Chain implementations?
>> -        # See attribute chaining in finish()
>>         #
>>         # FIXME: Allow extra parameters?
>>         cfg = TestingConfig(self, self.name, self.suffixes, self.test_format,
>> @@ -102,9 +101,3 @@
>>             # files. Should we distinguish them?
>>             self.test_source_root = str(self.test_source_root)
>>         self.excludes = set(self.excludes)
>> -
>> -        # chain attributes by copying them
>> -        if self.parent:
>> -            for k,v in vars(self.parent).items():
>> -                if not hasattr(self, k):
>> -                    setattr(self, k, v)
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
> 
> Thanks,
> 
> Justin Holewinski
> 

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From eli.friedman at gmail.com  Thu Jun 23 13:24:27 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 23 Jun 2011 18:24:27 -0000
Subject: [llvm-commits] [llvm] r133741 -
	/llvm/trunk/runtime/libprofile/GCDAProfiling.c
Message-ID: <20110623182427.E42242A6C12C@llvm.org>

Author: efriedma
Date: Thu Jun 23 13:24:27 2011
New Revision: 133741

URL: http://llvm.org/viewvc/llvm-project?rev=133741&view=rev
Log:
Fix build for (some versions of?) MinGW.  Patch by Ruben Van Boxem.


Modified:
    llvm/trunk/runtime/libprofile/GCDAProfiling.c

Modified: llvm/trunk/runtime/libprofile/GCDAProfiling.c
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/runtime/libprofile/GCDAProfiling.c?rev=133741&r1=133740&r2=133741&view=diff
==============================================================================
--- llvm/trunk/runtime/libprofile/GCDAProfiling.c (original)
+++ llvm/trunk/runtime/libprofile/GCDAProfiling.c Thu Jun 23 13:24:27 2011
@@ -89,7 +89,7 @@
       pathname = malloc(i + 1);
       strncpy(pathname, filename, i);
       pathname[i] = '\0';
-#ifdef _MSC_VER
+#ifdef _WIN32
       _mkdir(pathname);
 #else
       mkdir(pathname, 0750);  /* some of these will fail, ignore it. */



From eli.friedman at gmail.com  Thu Jun 23 13:33:22 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 23 Jun 2011 11:33:22 -0700
Subject: [llvm-commits] [PATCH] Fix build on MinGW
In-Reply-To: <BANLkTi=wsrtcDVtDU7eVvmZ8_BUnetQ=3w@mail.gmail.com>
References: <BANLkTimerx4TTm26eYkwfF7H9JRR14X4Nw@mail.gmail.com>
	<BANLkTi=wsrtcDVtDU7eVvmZ8_BUnetQ=3w@mail.gmail.com>
Message-ID: <BANLkTimB82+WC2rK2ScBNmqoTHdvZBGsHg@mail.gmail.com>

On Wed, Jun 22, 2011 at 8:33 AM, Ruben Van Boxem
<vanboxem.ruben at gmail.com> wrote:
> 2011/6/22 Ruben Van Boxem <vanboxem.ruben at gmail.com>
>>
>> Hi,
>>
>> Attached is a patch for MinGW.
>>
>> The first bit selects the correct _mkdir function for all Windows platforms, not just MSVC, which is wrong, and makes the MinGW build fail.
>>
>> The second bit is about this bug: http://llvm.org/bugs/show_bug.cgi?id=8850
>> The patch only affects MinGW on x86_64, which is localized to exactly where the crash occurs.
>>
>> Please apply these as soon as you have time. Thanks!
>>
>> Ruben
>
> I'm terribly sorry, but the second bit was wrong in my first patch.
> Attached is the correct version.

Applied the first bit; in the future, please say something sooner if
someone says "please commit" and you don't have commit rights. :)

As for the second bit, the proposed fix is really just a workaround...
I would prefer some analysis of why exactly TableGen needs so much
stack space.

-Eli

From aggarwa4 at illinois.edu  Thu Jun 23 14:54:44 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 19:54:44 -0000
Subject: [llvm-commits] [poolalloc] r133748 -
	/poolalloc/trunk/include/assistDS/TypeChecks.h
Message-ID: <20110623195444.1768D2A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Jun 23 14:54:43 2011
New Revision: 133748

URL: http://llvm.org/viewvc/llvm-project?rev=133748&view=rev
Log:
Forgot header.Sorry!

Modified:
    poolalloc/trunk/include/assistDS/TypeChecks.h

Modified: poolalloc/trunk/include/assistDS/TypeChecks.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=133748&r1=133747&r2=133748&view=diff
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecks.h (original)
+++ poolalloc/trunk/include/assistDS/TypeChecks.h Thu Jun 23 14:54:43 2011
@@ -65,6 +65,8 @@
   bool visitStoreInst(Module &M, StoreInst &SI);
   bool visitAllocaInst(Module &M, AllocaInst &AI);
   bool visitVAArgInst(Module &M, VAArgInst &VI);
+  
+  bool visitUses(Instruction *I, AllocaInst *AI, CastInst *BCI);
 
   bool visitGlobal(Module &M, GlobalVariable &GV, 
                    Constant *C, Instruction &I, SmallVector<Value*,8>);



From mttjwl at gmail.com  Thu Jun 23 15:21:53 2011
From: mttjwl at gmail.com (Matthew Wala)
Date: Thu, 23 Jun 2011 20:21:53 -0000
Subject: [llvm-commits] [poolalloc] r133752 -
	/poolalloc/trunk/lib/DSA/StdLibPass.cpp
Message-ID: <20110623202153.8A3C92A6C12C@llvm.org>

Author: wala1
Date: Thu Jun 23 15:21:53 2011
New Revision: 133752

URL: http://llvm.org/viewvc/llvm-project?rev=133752&view=rev
Log:
Allow DSA to recognize more transformed format string functions:
pool_err(), pool_errx(), pool_warn(), pool_warnx(), pool_syslog()

Modified:
    poolalloc/trunk/lib/DSA/StdLibPass.cpp

Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=133752&r1=133751&r2=133752&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original)
+++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Thu Jun 23 15:21:53 2011
@@ -305,6 +305,11 @@
   {"pool_fprintf",    {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"pool_sprintf",    {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"pool_snprintf",   {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_err",        {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_errx",       {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_warn",       {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_warnx",      {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_syslog",     {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   
   // Type Checks
   {"trackGlobal",          {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},



From aggarwa4 at illinois.edu  Thu Jun 23 15:29:21 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 20:29:21 -0000
Subject: [llvm-commits] [poolalloc] r133754 - in /poolalloc/trunk:
 include/assistDS/TypeChecks.h include/assistDS/TypeChecksOpt.h
 lib/AssistDS/TypeChecks.cpp lib/AssistDS/TypeChecksOpt.cpp
Message-ID: <20110623202921.3E4932A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Jun 23 15:29:21 2011
New Revision: 133754

URL: http://llvm.org/viewvc/llvm-project?rev=133754&view=rev
Log:
Fix prototype.
Remove extra includes.
Add a function to remove extra load checks, using 
DominatorTree.

Modified:
    poolalloc/trunk/include/assistDS/TypeChecks.h
    poolalloc/trunk/include/assistDS/TypeChecksOpt.h
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
    poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp

Modified: poolalloc/trunk/include/assistDS/TypeChecks.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=133754&r1=133753&r2=133754&view=diff
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecks.h (original)
+++ poolalloc/trunk/include/assistDS/TypeChecks.h Thu Jun 23 15:29:21 2011
@@ -21,6 +21,7 @@
 #include "llvm/Pass.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Support/CallSite.h"
+#include "llvm/Analysis/Dominators.h"
 
 #include <map>
 #include <list>
@@ -53,6 +54,7 @@
   
   bool initShadow(Module &M);
   void addTypeMap(Module &M) ;
+  void optimizeChecks(Module &M);
   
   bool visitMain(Module &M, Function &F); 
 
@@ -91,6 +93,7 @@
 
   virtual void getAnalysisUsage(AnalysisUsage &AU) const {
     AU.addRequired<TargetData>();
+    AU.addRequired<DominatorTree>();
     AU.addRequired<AddressTakenAnalysis>();
   }
 

Modified: poolalloc/trunk/include/assistDS/TypeChecksOpt.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecksOpt.h?rev=133754&r1=133753&r2=133754&view=diff
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecksOpt.h (original)
+++ poolalloc/trunk/include/assistDS/TypeChecksOpt.h Thu Jun 23 15:29:21 2011
@@ -15,14 +15,13 @@
 #define TYPE_CHECKS_OPT_H
 
 #include "dsa/TypeSafety.h"
-#include "dsa/AddressTakenAnalysis.h"
 
 #include "llvm/Instructions.h"
 #include "llvm/Pass.h"
 #include "llvm/Target/TargetData.h"
 #include "llvm/Support/CallSite.h"
 
-#include <map>
+#include <list>
 
 namespace llvm {
 

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133754&r1=133753&r2=133754&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 23 15:29:21 2011
@@ -298,7 +298,6 @@
     modified |= visitByValFunction(M, *F);
   }
 
-
   while(!VAArgFunctions.empty()) {
     Function *F = VAArgFunctions.back();
     VAArgFunctions.pop_back();
@@ -405,6 +404,7 @@
     }
   }
 
+  optimizeChecks(M);
 
   // add a global that contains the mapping from metadata to strings
   addTypeMap(M);
@@ -415,6 +415,46 @@
   return modified;
 }
 
+void TypeChecks::optimizeChecks(Module &M) {
+  for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) {
+    Function &F = *MI;
+    if(F.isDeclaration())
+      continue;
+    for (Function::iterator B = F.begin(), FE = F.end(); B != FE; ++B) {
+      DominatorTree & DT = getAnalysis<DominatorTree>(F);
+      for (BasicBlock::iterator bi = B->begin(); bi != B->end(); ++bi) {
+        CallInst *CI = dyn_cast<CallInst>(bi);
+        if(!CI)
+          continue;
+        if(CI->getCalledFunction() != checkTypeInst)
+          continue;
+        std::list<Instruction *>toDelete;
+        for(Value::use_iterator User = checkTypeInst->use_begin(); User != checkTypeInst->use_end(); ++User) {
+          CallInst *CI2 = dyn_cast<CallInst>(User);
+          if(CI2 == CI)
+            continue;
+          if(CI2->getParent()->getParent() != &F)
+            continue;
+          if(CI->getOperand(4) != CI2->getOperand(4))
+            continue;
+          if(CI->getOperand(3) != CI2->getOperand(3))
+            continue;
+          if(!DT.dominates(CI, CI2))
+            continue;
+          CI->dump();
+          CI2->dump();
+          toDelete.push_back(CI2);
+        }
+        while(!toDelete.empty()) {
+          Instruction *I = toDelete.back();
+          toDelete.pop_back();
+          I->eraseFromParent();
+        }
+      }
+    }
+  }
+
+}
 
 // add a global that has the metadata -> typeString mapping
 void TypeChecks::addTypeMap(Module &M) {

Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=133754&r1=133753&r2=133754&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Thu Jun 23 15:29:21 2011
@@ -96,7 +96,7 @@
                                         VoidTy,
                                         TypeTagTy,/*type*/
                                         Int64Ty,/*size*/
-                                        VoidPtrTy,
+                                        TypeTagPtrTy,
                                         VoidPtrTy,/*ptr*/
                                         Int32Ty,/*tag*/
                                         NULL);



From eli.friedman at gmail.com  Thu Jun 23 15:40:24 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 23 Jun 2011 20:40:24 -0000
Subject: [llvm-commits] [llvm] r133756 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstCombineSelect.cpp
 test/Transforms/InstCombine/select-crash.ll
Message-ID: <20110623204024.1B1392A6C12C@llvm.org>

Author: efriedma
Date: Thu Jun 23 15:40:23 2011
New Revision: 133756

URL: http://llvm.org/viewvc/llvm-project?rev=133756&view=rev
Log:
PR10180: Fix a instcombine crash with FP vectors.


Modified:
    llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp
    llvm/trunk/test/Transforms/InstCombine/select-crash.ll

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp?rev=133756&r1=133755&r2=133756&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineSelect.cpp Thu Jun 23 15:40:23 2011
@@ -796,7 +796,7 @@
             // So at this point we know we have (Y -> OtherAddOp):
             //        select C, (add X, Y), (sub X, Z)
             Value *NegVal;  // Compute -Z
-            if (SI.getType()->isFloatingPointTy()) {
+            if (SI.getType()->isFPOrFPVectorTy()) {
               NegVal = Builder->CreateFNeg(SubOp->getOperand(1));
             } else {
               NegVal = Builder->CreateNeg(SubOp->getOperand(1));
@@ -810,7 +810,7 @@
               Builder->CreateSelect(CondVal, NewTrueOp,
                                     NewFalseOp, SI.getName() + ".p");
 
-            if (SI.getType()->isFloatingPointTy())
+            if (SI.getType()->isFPOrFPVectorTy())
               return BinaryOperator::CreateFAdd(SubOp->getOperand(0), NewSel);
             else
               return BinaryOperator::CreateAdd(SubOp->getOperand(0), NewSel);

Modified: llvm/trunk/test/Transforms/InstCombine/select-crash.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstCombine/select-crash.ll?rev=133756&r1=133755&r2=133756&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstCombine/select-crash.ll (original)
+++ llvm/trunk/test/Transforms/InstCombine/select-crash.ll Thu Jun 23 15:40:23 2011
@@ -18,3 +18,15 @@
   %add94 = fadd double undef, %mul91
   ret double %add94
 }
+
+; PR10180: same crash, but with vectors
+define <4 x float> @foo(i1 %b, <4 x float> %x, <4 x float> %y, <4 x float> %z) {
+; CHECK: @foo
+; CHECK: fsub <4 x float>
+; CHECK: select
+; CHECK: fadd <4 x float>
+  %a = fadd <4 x float> %x, %y
+  %sub = fsub <4 x float> %x, %z
+  %sel = select i1 %b, <4 x float> %a, <4 x float> %sub 
+  ret <4 x float> %sel
+}



From eli.friedman at gmail.com  Thu Jun 23 16:07:47 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 23 Jun 2011 21:07:47 -0000
Subject: [llvm-commits] [llvm] r133759 - in /llvm/trunk:
 lib/Target/X86/X86InstrSSE.td test/MC/X86/x86-32-coverage.s
 test/MC/X86/x86-64.s
Message-ID: <20110623210748.2C0F72A6C12C@llvm.org>

Author: efriedma
Date: Thu Jun 23 16:07:47 2011
New Revision: 133759

URL: http://llvm.org/viewvc/llvm-project?rev=133759&view=rev
Log:
Add support for movntil/movntiq mnemonics.  Reported on llvmdev.


Modified:
    llvm/trunk/lib/Target/X86/X86InstrSSE.td
    llvm/trunk/test/MC/X86/x86-32-coverage.s
    llvm/trunk/test/MC/X86/x86-64.s

Modified: llvm/trunk/lib/Target/X86/X86InstrSSE.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSSE.td?rev=133759&r1=133758&r2=133759&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSSE.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSSE.td Thu Jun 23 16:07:47 2011
@@ -1991,11 +1991,11 @@
 
 // There is no AVX form for instructions below this point
 def MOVNTImr : I<0xC3, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
-                 "movnti\t{$src, $dst|$dst, $src}",
+                 "movnti{l}\t{$src, $dst|$dst, $src}",
                  [(nontemporalstore (i32 GR32:$src), addr:$dst)]>,
                TB, Requires<[HasSSE2]>;
 def MOVNTI_64mr : RI<0xC3, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
-                     "movnti\t{$src, $dst|$dst, $src}",
+                     "movnti{q}\t{$src, $dst|$dst, $src}",
                      [(nontemporalstore (i64 GR64:$src), addr:$dst)]>,
                   TB, Requires<[HasSSE2]>;
 }

Modified: llvm/trunk/test/MC/X86/x86-32-coverage.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-32-coverage.s?rev=133759&r1=133758&r2=133759&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-32-coverage.s (original)
+++ llvm/trunk/test/MC/X86/x86-32-coverage.s Thu Jun 23 16:07:47 2011
@@ -503,7 +503,7 @@
 // CHECK: 	ud2
         	ud2
 
-// CHECK: 	movnti	%ecx, 3735928559(%ebx,%ecx,8)
+// CHECK: 	movntil	%ecx, 3735928559(%ebx,%ecx,8)
         	movnti	%ecx,0xdeadbeef(%ebx,%ecx,8)
 
 // CHECK: 	clflush	3735928559(%ebx,%ecx,8)
@@ -4505,23 +4505,23 @@
 // CHECK:  encoding: [0xdf,0xea]
         	fucomip	%st(2),%st
 
-// CHECK: movnti	%ecx, 3735928559(%ebx,%ecx,8)
+// CHECK: movntil	%ecx, 3735928559(%ebx,%ecx,8)
 // CHECK:  encoding: [0x0f,0xc3,0x8c,0xcb,0xef,0xbe,0xad,0xde]
         	movnti	%ecx,0xdeadbeef(%ebx,%ecx,8)
 
-// CHECK: movnti	%ecx, 69
+// CHECK: movntil	%ecx, 69
 // CHECK:  encoding: [0x0f,0xc3,0x0d,0x45,0x00,0x00,0x00]
         	movnti	%ecx,0x45
 
-// CHECK: movnti	%ecx, 32493
+// CHECK: movntil	%ecx, 32493
 // CHECK:  encoding: [0x0f,0xc3,0x0d,0xed,0x7e,0x00,0x00]
         	movnti	%ecx,0x7eed
 
-// CHECK: movnti	%ecx, 3133065982
+// CHECK: movntil	%ecx, 3133065982
 // CHECK:  encoding: [0x0f,0xc3,0x0d,0xfe,0xca,0xbe,0xba]
         	movnti	%ecx,0xbabecafe
 
-// CHECK: movnti	%ecx, 305419896
+// CHECK: movntil	%ecx, 305419896
 // CHECK:  encoding: [0x0f,0xc3,0x0d,0x78,0x56,0x34,0x12]
         	movnti	%ecx,0x12345678
 
@@ -14177,19 +14177,19 @@
 // CHECK: 	fucompi	%st(2)
         	fucomip	%st(2),%st
 
-// CHECK: 	movnti	%ecx, 3735928559(%ebx,%ecx,8)
+// CHECK: 	movntil	%ecx, 3735928559(%ebx,%ecx,8)
         	movnti	%ecx,0xdeadbeef(%ebx,%ecx,8)
 
-// CHECK: 	movnti	%ecx, 69
-        	movnti	%ecx,0x45
+// CHECK: 	movntil	%ecx, 69
+        	movntil	%ecx,0x45
 
-// CHECK: 	movnti	%ecx, 32493
+// CHECK: 	movntil	%ecx, 32493
         	movnti	%ecx,0x7eed
 
-// CHECK: 	movnti	%ecx, 3133065982
+// CHECK: 	movntil	%ecx, 3133065982
         	movnti	%ecx,0xbabecafe
 
-// CHECK: 	movnti	%ecx, 305419896
+// CHECK: 	movntil	%ecx, 305419896
         	movnti	%ecx,0x12345678
 
 // CHECK: 	clflush	3735928559(%ebx,%ecx,8)

Modified: llvm/trunk/test/MC/X86/x86-64.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/x86-64.s?rev=133759&r1=133758&r2=133759&view=diff
==============================================================================
--- llvm/trunk/test/MC/X86/x86-64.s (original)
+++ llvm/trunk/test/MC/X86/x86-64.s Thu Jun 23 16:07:47 2011
@@ -1136,3 +1136,15 @@
 // CHECK: movd %rdi, %xmm0
 // CHECK: encoding: [0x66,0x48,0x0f,0x6e,0xc7]
 	movd %rdi,%xmm0
+
+// CHECK: movntil %eax, (%rdi)
+// CHECK: encoding: [0x0f,0xc3,0x07]
+// CHECK: movntil
+movntil %eax, (%rdi)
+movnti %eax, (%rdi)
+
+// CHECK: movntiq %rax, (%rdi)
+// CHECK: encoding: [0x48,0x0f,0xc3,0x07]
+// CHECK: movntiq
+movntiq %rax, (%rdi)
+movnti %rax, (%rdi)



From jstaszak at apple.com  Thu Jun 23 16:45:20 2011
From: jstaszak at apple.com (Jakub Staszak)
Date: Thu, 23 Jun 2011 21:45:20 -0000
Subject: [llvm-commits] [llvm] r133766 - in /llvm/trunk:
 include/llvm/Analysis/BranchProbabilityInfo.h
 include/llvm/InitializePasses.h include/llvm/Support/BranchProbability.h
 lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp
 lib/Analysis/CMakeLists.txt
Message-ID: <20110623214520.7638D2A6C12C@llvm.org>

Author: kuba
Date: Thu Jun 23 16:45:20 2011
New Revision: 133766

URL: http://llvm.org/viewvc/llvm-project?rev=133766&view=rev
Log:
Introduce BlockFrequency analysis for BasicBlocks.

Modified:
    llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
    llvm/trunk/include/llvm/InitializePasses.h
    llvm/trunk/include/llvm/Support/BranchProbability.h
    llvm/trunk/lib/Analysis/Analysis.cpp
    llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
    llvm/trunk/lib/Analysis/CMakeLists.txt

Modified: llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h?rev=133766&r1=133765&r2=133766&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h Thu Jun 23 16:45:20 2011
@@ -39,6 +39,9 @@
   // Get sum of the block successors' weights.
   uint32_t getSumForBlock(BasicBlock *BB) const;
 
+  // Get sum of the edge weights going to the BB block.
+  uint32_t getBackSumForBlock(BasicBlock *BB) const;
+
 public:
   static char ID;
 
@@ -71,6 +74,13 @@
   // only iff SRC block has only one successor.
   BranchProbability getEdgeProbability(BasicBlock *Src, BasicBlock *Dst) const;
 
+  // Return a probability of getting to the DST block through SRC->DST edge.
+  // Returned value is a fraction between 0 (0% probability) and
+  // 1 (100% probability), however the value is never equal to 0, and can be 1
+  // only iff DST block has only one predecesor.
+  BranchProbability getBackEdgeProbability(BasicBlock *Src,
+                                           BasicBlock *Dst) const;
+
   // Print value between 0 (0% probability) and 1 (100% probability),
   // however the value is never equal to 0, and can be 1 only iff SRC block
   // has only one successor.

Modified: llvm/trunk/include/llvm/InitializePasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=133766&r1=133765&r2=133766&view=diff
==============================================================================
--- llvm/trunk/include/llvm/InitializePasses.h (original)
+++ llvm/trunk/include/llvm/InitializePasses.h Thu Jun 23 16:45:20 2011
@@ -65,6 +65,7 @@
 void initializeBasicAliasAnalysisPass(PassRegistry&);
 void initializeBasicCallGraphPass(PassRegistry&);
 void initializeBlockExtractorPassPass(PassRegistry&);
+void initializeBlockFrequencyPass(PassRegistry&);
 void initializeBlockPlacementPass(PassRegistry&);
 void initializeBranchProbabilityInfoPass(PassRegistry&);
 void initializeBreakCriticalEdgesPass(PassRegistry&);

Modified: llvm/trunk/include/llvm/Support/BranchProbability.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/BranchProbability.h?rev=133766&r1=133765&r2=133766&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Support/BranchProbability.h (original)
+++ llvm/trunk/include/llvm/Support/BranchProbability.h Thu Jun 23 16:45:20 2011
@@ -18,13 +18,17 @@
 
 namespace llvm {
 
-class raw_ostream;
+template<class BlockT, class FunctionT, class BranchProbInfoT>
+class BlockFrequencyImpl;
 class BranchProbabilityInfo;
 class MachineBranchProbabilityInfo;
 class MachineBasicBlock;
+class raw_ostream;
 
 // This class represents Branch Probability as a non-negative fraction.
 class BranchProbability {
+  template<class BlockT, class FunctionT, class BranchProbInfoT>
+  friend class BlockFrequencyImpl;
   friend class BranchProbabilityInfo;
   friend class MachineBranchProbabilityInfo;
   friend class MachineBasicBlock;
@@ -38,6 +42,10 @@
   BranchProbability(uint32_t n, uint32_t d);
 
 public:
+
+  uint32_t getNumerator() const { return N; }
+  uint32_t getDenominator() const { return D; }
+
   raw_ostream &print(raw_ostream &OS) const;
 
   void dump() const;

Modified: llvm/trunk/lib/Analysis/Analysis.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Analysis.cpp?rev=133766&r1=133765&r2=133766&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/Analysis.cpp (original)
+++ llvm/trunk/lib/Analysis/Analysis.cpp Thu Jun 23 16:45:20 2011
@@ -23,6 +23,7 @@
   initializeAliasSetPrinterPass(Registry);
   initializeNoAAPass(Registry);
   initializeBasicAliasAnalysisPass(Registry);
+  initializeBlockFrequencyPass(Registry);
   initializeBranchProbabilityInfoPass(Registry);
   initializeCFGViewerPass(Registry);
   initializeCFGPrinterPass(Registry);

Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=133766&r1=133765&r2=133766&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Thu Jun 23 16:45:20 2011
@@ -279,6 +279,21 @@
   return Sum;
 }
 
+uint32_t BranchProbabilityInfo::getBackSumForBlock(BasicBlock *BB) const {
+  uint32_t Sum = 0;
+
+  for (pred_iterator I = pred_begin(BB), E = pred_end(BB); I != E; ++I) {
+    BasicBlock *Pred = *I;
+    uint32_t Weight = getEdgeWeight(Pred, BB);
+    uint32_t PrevSum = Sum;
+
+    Sum += Weight;
+    assert(Sum > PrevSum); (void) PrevSum;
+  }
+
+  return Sum;
+}
+
 bool BranchProbabilityInfo::isEdgeHot(BasicBlock *Src, BasicBlock *Dst) const {
   // Hot probability is at least 4/5 = 80%
   uint32_t Weight = getEdgeWeight(Src, Dst);
@@ -345,6 +360,15 @@
   return BranchProbability(N, D);
 }
 
+BranchProbability BranchProbabilityInfo::
+getBackEdgeProbability(BasicBlock *Src, BasicBlock *Dst) const {
+
+  uint32_t N = getEdgeWeight(Src, Dst);
+  uint32_t D = getBackSumForBlock(Dst);
+
+  return BranchProbability(N, D);
+}
+
 raw_ostream &
 BranchProbabilityInfo::printEdgeProbability(raw_ostream &OS, BasicBlock *Src,
                                             BasicBlock *Dst) const {

Modified: llvm/trunk/lib/Analysis/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CMakeLists.txt?rev=133766&r1=133765&r2=133766&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/CMakeLists.txt (original)
+++ llvm/trunk/lib/Analysis/CMakeLists.txt Thu Jun 23 16:45:20 2011
@@ -6,6 +6,7 @@
   AliasSetTracker.cpp
   Analysis.cpp
   BasicAliasAnalysis.cpp
+  BlockFrequency.cpp
   BranchProbabilityInfo.cpp
   CFGPrinter.cpp
   CaptureTracking.cpp



From matthewbg at google.com  Thu Jun 23 17:02:04 2011
From: matthewbg at google.com (Matt Beaumont-Gay)
Date: Thu, 23 Jun 2011 15:02:04 -0700
Subject: [llvm-commits] [llvm] r133766 - in /llvm/trunk:
 include/llvm/Analysis/BranchProbabilityInfo.h
 include/llvm/InitializePasses.h include/llvm/Support/BranchProbability.h
 lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp
 lib/Analysis/C
Message-ID: <BANLkTim+2s_iqPD7VTmDXzF_MTYsZ9Ke=gms8skegJr1qNjMDQ@mail.gmail.com>

On Thu, Jun 23, 2011 at 14:45, Jakub Staszak <jstaszak at apple.com> wrote:
> Author: kuba
> Date: Thu Jun 23 16:45:20 2011
> New Revision: 133766
>
> URL: http://llvm.org/viewvc/llvm-project?rev=133766&view=rev
> Log:
> Introduce BlockFrequency analysis for BasicBlocks.
>
> Modified:
> ? ?llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
> ? ?llvm/trunk/include/llvm/InitializePasses.h
> ? ?llvm/trunk/include/llvm/Support/BranchProbability.h
> ? ?llvm/trunk/lib/Analysis/Analysis.cpp
> ? ?llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
> ? ?llvm/trunk/lib/Analysis/CMakeLists.txt
>
> Modified: llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h?rev=133766&r1=133765&r2=133766&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h (original)
> +++ llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h Thu Jun 23 16:45:20 2011
> @@ -39,6 +39,9 @@
> ? // Get sum of the block successors' weights.
> ? uint32_t getSumForBlock(BasicBlock *BB) const;
>
> + ?// Get sum of the edge weights going to the BB block.
> + ?uint32_t getBackSumForBlock(BasicBlock *BB) const;
> +
> ?public:
> ? static char ID;
>
> @@ -71,6 +74,13 @@
> ? // only iff SRC block has only one successor.
> ? BranchProbability getEdgeProbability(BasicBlock *Src, BasicBlock *Dst) const;
>
> + ?// Return a probability of getting to the DST block through SRC->DST edge.
> + ?// Returned value is a fraction between 0 (0% probability) and
> + ?// 1 (100% probability), however the value is never equal to 0, and can be 1
> + ?// only iff DST block has only one predecesor.
> + ?BranchProbability getBackEdgeProbability(BasicBlock *Src,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? BasicBlock *Dst) const;
> +
> ? // Print value between 0 (0% probability) and 1 (100% probability),
> ? // however the value is never equal to 0, and can be 1 only iff SRC block
> ? // has only one successor.
>
> Modified: llvm/trunk/include/llvm/InitializePasses.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=133766&r1=133765&r2=133766&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/InitializePasses.h (original)
> +++ llvm/trunk/include/llvm/InitializePasses.h Thu Jun 23 16:45:20 2011
> @@ -65,6 +65,7 @@
> ?void initializeBasicAliasAnalysisPass(PassRegistry&);
> ?void initializeBasicCallGraphPass(PassRegistry&);
> ?void initializeBlockExtractorPassPass(PassRegistry&);
> +void initializeBlockFrequencyPass(PassRegistry&);
> ?void initializeBlockPlacementPass(PassRegistry&);
> ?void initializeBranchProbabilityInfoPass(PassRegistry&);
> ?void initializeBreakCriticalEdgesPass(PassRegistry&);
>
> Modified: llvm/trunk/include/llvm/Support/BranchProbability.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/BranchProbability.h?rev=133766&r1=133765&r2=133766&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Support/BranchProbability.h (original)
> +++ llvm/trunk/include/llvm/Support/BranchProbability.h Thu Jun 23 16:45:20 2011
> @@ -18,13 +18,17 @@
>
> ?namespace llvm {
>
> -class raw_ostream;
> +template<class BlockT, class FunctionT, class BranchProbInfoT>
> +class BlockFrequencyImpl;
> ?class BranchProbabilityInfo;
> ?class MachineBranchProbabilityInfo;
> ?class MachineBasicBlock;
> +class raw_ostream;
>
> ?// This class represents Branch Probability as a non-negative fraction.
> ?class BranchProbability {
> + ?template<class BlockT, class FunctionT, class BranchProbInfoT>
> + ?friend class BlockFrequencyImpl;
> ? friend class BranchProbabilityInfo;
> ? friend class MachineBranchProbabilityInfo;
> ? friend class MachineBasicBlock;
> @@ -38,6 +42,10 @@
> ? BranchProbability(uint32_t n, uint32_t d);
>
> ?public:
> +
> + ?uint32_t getNumerator() const { return N; }
> + ?uint32_t getDenominator() const { return D; }
> +
> ? raw_ostream &print(raw_ostream &OS) const;
>
> ? void dump() const;
>
> Modified: llvm/trunk/lib/Analysis/Analysis.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/Analysis.cpp?rev=133766&r1=133765&r2=133766&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/Analysis.cpp (original)
> +++ llvm/trunk/lib/Analysis/Analysis.cpp Thu Jun 23 16:45:20 2011
> @@ -23,6 +23,7 @@
> ? initializeAliasSetPrinterPass(Registry);
> ? initializeNoAAPass(Registry);
> ? initializeBasicAliasAnalysisPass(Registry);
> + ?initializeBlockFrequencyPass(Registry);
> ? initializeBranchProbabilityInfoPass(Registry);
> ? initializeCFGViewerPass(Registry);
> ? initializeCFGPrinterPass(Registry);
>
> Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=133766&r1=133765&r2=133766&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original)
> +++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Thu Jun 23 16:45:20 2011
> @@ -279,6 +279,21 @@
> ? return Sum;
> ?}
>
> +uint32_t BranchProbabilityInfo::getBackSumForBlock(BasicBlock *BB) const {
> + ?uint32_t Sum = 0;
> +
> + ?for (pred_iterator I = pred_begin(BB), E = pred_end(BB); I != E; ++I) {
> + ? ?BasicBlock *Pred = *I;
> + ? ?uint32_t Weight = getEdgeWeight(Pred, BB);
> + ? ?uint32_t PrevSum = Sum;
> +
> + ? ?Sum += Weight;
> + ? ?assert(Sum > PrevSum); (void) PrevSum;
> + ?}
> +
> + ?return Sum;
> +}
> +
> ?bool BranchProbabilityInfo::isEdgeHot(BasicBlock *Src, BasicBlock *Dst) const {
> ? // Hot probability is at least 4/5 = 80%
> ? uint32_t Weight = getEdgeWeight(Src, Dst);
> @@ -345,6 +360,15 @@
> ? return BranchProbability(N, D);
> ?}
>
> +BranchProbability BranchProbabilityInfo::
> +getBackEdgeProbability(BasicBlock *Src, BasicBlock *Dst) const {
> +
> + ?uint32_t N = getEdgeWeight(Src, Dst);
> + ?uint32_t D = getBackSumForBlock(Dst);
> +
> + ?return BranchProbability(N, D);
> +}
> +
> ?raw_ostream &
> ?BranchProbabilityInfo::printEdgeProbability(raw_ostream &OS, BasicBlock *Src,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? BasicBlock *Dst) const {
>
> Modified: llvm/trunk/lib/Analysis/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/CMakeLists.txt?rev=133766&r1=133765&r2=133766&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Analysis/CMakeLists.txt Thu Jun 23 16:45:20 2011
> @@ -6,6 +6,7 @@
> ? AliasSetTracker.cpp
> ? Analysis.cpp
> ? BasicAliasAnalysis.cpp
> + ?BlockFrequency.cpp

Looks like you forgot to add this file?


From jstaszak at apple.com  Thu Jun 23 16:57:00 2011
From: jstaszak at apple.com (Jakub Staszak)
Date: Thu, 23 Jun 2011 21:57:00 -0000
Subject: [llvm-commits] [llvm] r133767 - in /llvm/trunk:
 include/llvm/Analysis/BlockFrequency.h
 include/llvm/Analysis/BlockFrequencyImpl.h lib/Analysis/BlockFrequency.cpp
Message-ID: <20110623215700.1C7A32A6C12C@llvm.org>

Author: kuba
Date: Thu Jun 23 16:56:59 2011
New Revision: 133767

URL: http://llvm.org/viewvc/llvm-project?rev=133767&view=rev
Log:
Missing files for the BlockFrequency analysis added.

Added:
    llvm/trunk/include/llvm/Analysis/BlockFrequency.h
    llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h
    llvm/trunk/lib/Analysis/BlockFrequency.cpp

Added: llvm/trunk/include/llvm/Analysis/BlockFrequency.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequency.h?rev=133767&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Analysis/BlockFrequency.h (added)
+++ llvm/trunk/include/llvm/Analysis/BlockFrequency.h Thu Jun 23 16:56:59 2011
@@ -0,0 +1,53 @@
+//========-------- BlockFrequency.h - Block Frequency Analysis -------========//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Loops should be simplified before this analysis.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_ANALYSIS_BLOCKFREQUENCY_H
+#define LLVM_ANALYSIS_BLOCKFREQUENCY_H
+
+#include "llvm/Pass.h"
+#include <climits>
+
+namespace llvm {
+
+class BranchProbabilityInfo;
+template<class BlockT, class FunctionT, class BranchProbInfoT>
+class BlockFrequencyImpl;
+
+/// BlockFrequency pass uses BlockFrequencyImpl implementation to estimate
+/// IR basic block frequencies.
+class BlockFrequency : public FunctionPass {
+
+  BlockFrequencyImpl<BasicBlock, Function, BranchProbabilityInfo> *BFI;
+
+public:
+  static char ID;
+
+  BlockFrequency();
+
+  ~BlockFrequency();
+
+  void getAnalysisUsage(AnalysisUsage &AU) const;
+
+  bool runOnFunction(Function &F);
+
+  /// getblockFreq - Return block frequency. Never return 0, value must be
+  /// positive. Please note that initial frequency is equal to 1024. It means
+  /// that we should not rely on the value itself, but only on the comparison to
+  /// the other block frequencies. We do this to avoid using of the floating
+  /// points.
+  uint32_t getBlockFreq(BasicBlock *BB);
+};
+
+}
+
+#endif

Added: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h?rev=133767&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h (added)
+++ llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h Thu Jun 23 16:56:59 2011
@@ -0,0 +1,336 @@
+//===---- BlockFrequencyImpl.h - Machine Block Frequency Implementation ---===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Shared implementation of BlockFrequency for IR and Machine Instructions.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_ANALYSIS_BLOCKFREQUENCYIMPL_H
+#define LLVM_ANALYSIS_BLOCKFREQUENCYIMPL_H
+
+#include "llvm/BasicBlock.h"
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/PostOrderIterator.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/Support/BranchProbability.h"
+#include "llvm/Support/Debug.h"
+#include <vector>
+#include <sstream>
+#include <string>
+
+namespace llvm {
+
+
+class BlockFrequency;
+/// BlockFrequencyImpl implements block frequency algorithm for IR and
+/// Machine Instructions. Algorithm starts with value 1024 (START_FREQ)
+/// for the entry block and then propagates frequencies using branch weights
+/// from (Machine)BranchProbabilityInfo. LoopInfo is not required because
+/// algorithm can find "backedges" by itself.
+template<class BlockT, class FunctionT, class BlockProbInfoT>
+class BlockFrequencyImpl {
+
+  DenseMap<BlockT *, uint32_t> Freqs;
+
+  BlockProbInfoT *BPI;
+
+  FunctionT *Fn;
+
+  typedef GraphTraits< Inverse<BlockT *> > GT;
+
+  static const uint32_t START_FREQ = 1024;
+
+  std::string getBlockName(BasicBlock *BB) const {
+    return BB->getNameStr();
+  }
+
+  std::string getBlockName(MachineBasicBlock *MBB) const {
+    std::stringstream ss;
+    ss << "BB#" << MBB->getNumber();
+    const BasicBlock *BB = MBB->getBasicBlock();
+
+    if (BB)
+      ss << " derived from LLVM BB " << BB->getNameStr();
+
+    return ss.str();
+  }
+
+  void setBlockFreq(BlockT *BB, uint32_t Freq) {
+    Freqs[BB] = Freq;
+    DEBUG(dbgs() << "Frequency(" << getBlockName(BB) << ") = " << Freq << "\n");
+  }
+
+  /// getEdgeFreq - Return edge frequency based on SRC frequency and Src -> Dst
+  /// edge probability.
+  uint32_t getEdgeFreq(BlockT *Src, BlockT *Dst) const {
+    BranchProbability Prob = BPI->getEdgeProbability(Src, Dst);
+    uint64_t N = Prob.getNumerator();
+    uint64_t D = Prob.getDenominator();
+    uint64_t Res = (N * getBlockFreq(Src)) / D;
+
+    assert(Res <= UINT32_MAX);
+    return (uint32_t) Res;
+  }
+
+  /// incBlockFreq - Increase BB block frequency by FREQ.
+  ///
+  void incBlockFreq(BlockT *BB, uint32_t Freq) {
+    Freqs[BB] += Freq;
+    DEBUG(dbgs() << "Frequency(" << getBlockName(BB) << ") += " << Freq
+                 << " --> " << Freqs[BB] << "\n");
+  }
+
+  /// divBlockFreq - Divide BB block frequency by PROB. If Prob = 0 do nothing.
+  ///
+  void divBlockFreq(BlockT *BB, BranchProbability Prob) {
+    uint64_t N = Prob.getNumerator();
+    assert(N && "Illegal division by zero!");
+    uint64_t D = Prob.getDenominator();
+    uint64_t Freq = (Freqs[BB] * D) / N;
+
+    // Should we assert it?
+    if (Freq > UINT32_MAX)
+      Freq = UINT32_MAX;
+
+    Freqs[BB] = (uint32_t) Freq;
+    DEBUG(dbgs() << "Frequency(" << getBlockName(BB) << ") /= (" << Prob
+                 << ") --> " << Freqs[BB] << "\n");
+  }
+
+  // All blocks in postorder.
+  std::vector<BlockT *> POT;
+
+  // Map Block -> Position in reverse-postorder list.
+  DenseMap<BlockT *, unsigned> RPO;
+
+  // Cycle Probability for each bloch.
+  DenseMap<BlockT *, uint32_t> CycleProb;
+
+  // (reverse-)postorder traversal iterators.
+  typedef typename std::vector<BlockT *>::iterator pot_iterator;
+  typedef typename std::vector<BlockT *>::reverse_iterator rpot_iterator;
+
+  pot_iterator pot_begin() { return POT.begin(); }
+  pot_iterator pot_end() { return POT.end(); }
+
+  rpot_iterator rpot_begin() { return POT.rbegin(); }
+  rpot_iterator rpot_end() { return POT.rend(); }
+
+  rpot_iterator rpot_at(BlockT *BB) {
+    rpot_iterator I = rpot_begin();
+    unsigned idx = RPO[BB];
+    assert(idx);
+    std::advance(I, idx - 1);
+
+    assert(*I == BB);
+    return I;
+  }
+
+
+  /// isReachable - Returns if BB block is reachable from the entry.
+  ///
+  bool isReachable(BlockT *BB) {
+    return RPO.count(BB);
+  }
+
+  /// isBackedge - Return if edge Src -> Dst is a backedge.
+  ///
+  bool isBackedge(BlockT *Src, BlockT *Dst) {
+    assert(isReachable(Src));
+    assert(isReachable(Dst));
+
+    unsigned a = RPO[Src];
+    unsigned b = RPO[Dst];
+
+    return a > b;
+  }
+
+  /// getSingleBlockPred - return single BB block predecessor or NULL if
+  /// BB has none or more predecessors.
+  BlockT *getSingleBlockPred(BlockT *BB) {
+    typename GT::ChildIteratorType
+      PI = GraphTraits< Inverse<BlockT *> >::child_begin(BB),
+      PE = GraphTraits< Inverse<BlockT *> >::child_end(BB);
+
+    if (PI == PE)
+      return 0;
+
+    BlockT *Pred = *PI;
+
+    ++PI;
+    if (PI != PE)
+      return 0;
+
+    return Pred;
+  }
+
+  void doBlock(BlockT *BB, BlockT *LoopHead,
+               SmallPtrSet<BlockT *, 8> &BlocksInLoop) {
+
+    DEBUG(dbgs() << "doBlock(" << getBlockName(BB) << ")\n");
+    setBlockFreq(BB, 0);
+
+    if (BB == LoopHead) {
+      setBlockFreq(BB, START_FREQ);
+      return;
+    }
+
+    if(BlockT *Pred = getSingleBlockPred(BB)) {
+      if (BlocksInLoop.count(Pred))
+        setBlockFreq(BB, getEdgeFreq(Pred, BB));
+      // TODO: else? irreducible, ignore it for now.
+      return;
+    }
+
+    bool isInLoop = false;
+    bool isLoopHead = false;
+
+    for (typename GT::ChildIteratorType
+         PI = GraphTraits< Inverse<BlockT *> >::child_begin(BB),
+         PE = GraphTraits< Inverse<BlockT *> >::child_end(BB);
+         PI != PE; ++PI) {
+      BlockT *Pred = *PI;
+
+      if (isReachable(Pred) && isBackedge(Pred, BB)) {
+        isLoopHead = true;
+      } else if (BlocksInLoop.count(Pred)) {
+        incBlockFreq(BB, getEdgeFreq(Pred, BB));
+        isInLoop = true;
+      }
+      // TODO: else? irreducible.
+    }
+
+    if (!isInLoop)
+      return;
+
+    if (!isLoopHead)
+      return;
+
+    assert(START_FREQ >= CycleProb[BB]);
+    divBlockFreq(BB, BranchProbability(START_FREQ - CycleProb[BB], START_FREQ));
+  }
+
+  /// doLoop - Propagate block frequency down throught the loop.
+  void doLoop(BlockT *Head, BlockT *Tail) {
+    DEBUG(dbgs() << "doLoop(" << getBlockName(Head) << ", "
+                 << getBlockName(Tail) << ")\n");
+
+    SmallPtrSet<BlockT *, 8> BlocksInLoop;
+
+    for (rpot_iterator I = rpot_at(Head), E = rpot_end(); I != E; ++I) {
+      BlockT *BB = *I;
+      doBlock(BB, Head, BlocksInLoop);
+
+      BlocksInLoop.insert(BB);
+    }
+
+    // Compute loop's cyclic probability using backedges probabilities.
+    for (typename GT::ChildIteratorType
+         PI = GraphTraits< Inverse<BlockT *> >::child_begin(Head),
+         PE = GraphTraits< Inverse<BlockT *> >::child_end(Head);
+         PI != PE; ++PI) {
+      BlockT *Pred = *PI;
+      assert(Pred);
+      if (isReachable(Pred) && isBackedge(Pred, Head)) {
+        BranchProbability Prob = BPI->getBackEdgeProbability(Pred, Head);
+        uint64_t N = Prob.getNumerator();
+        uint64_t D = Prob.getDenominator();
+        uint64_t Res = (N * START_FREQ) / D;
+
+        // CycleProb[Head] += getEdgeFreq(Pred, Head);
+        assert(Res <= UINT32_MAX);
+        CycleProb[Head] += (uint32_t) Res;
+      }
+    }
+  }
+
+
+  friend class BlockFrequency;
+
+  void doFunction(FunctionT *fn, BlockProbInfoT *bpi) {
+    Fn = fn;
+    BPI = bpi;
+
+    // Clear everything.
+    RPO.clear();
+    POT.clear();
+    CycleProb.clear();
+    Freqs.clear();
+
+    BlockT *EntryBlock = fn->begin();
+
+    copy(po_begin(EntryBlock), po_end(EntryBlock), back_inserter(POT));
+
+    unsigned RPOidx = 0;
+    for (rpot_iterator I = rpot_begin(), E = rpot_end(); I != E; ++I) {
+      BlockT *BB = *I;
+      RPO[BB] = ++RPOidx;
+      DEBUG(dbgs() << "RPO[" << getBlockName(BB) << "] = " << RPO[BB] << "\n");
+    }
+
+    // Travel over all blocks in postorder.
+    for (pot_iterator I = pot_begin(), E = pot_end(); I != E; ++I) {
+      BlockT *BB = *I;
+      BlockT *LastTail = 0;
+      DEBUG(dbgs() << "POT: " << getBlockName(BB) << "\n");
+
+      for (typename GT::ChildIteratorType
+           PI = GraphTraits< Inverse<BlockT *> >::child_begin(BB),
+           PE = GraphTraits< Inverse<BlockT *> >::child_end(BB);
+           PI != PE; ++PI) {
+
+        BlockT *Pred = *PI;
+        if (isReachable(Pred) && isBackedge(Pred, BB)
+            && (!LastTail || RPO[Pred] > RPO[LastTail]))
+          LastTail = Pred;
+      }
+
+      if (LastTail)
+        doLoop(BB, LastTail);
+    }
+
+    // At the end assume the whole function as a loop, and travel over it once
+    // again.
+    doLoop(*(rpot_begin()), *(pot_begin()));
+  }
+
+public:
+  /// getBlockFreq - Return block frequency. Never return 0, value must be
+  /// positive.
+  uint32_t getBlockFreq(BlockT *BB) const {
+    typename DenseMap<BlockT *, uint32_t>::const_iterator I = Freqs.find(BB);
+    if (I != Freqs.end())
+      return I->second ? I->second : 1;
+    return 1;
+  }
+
+  void print(raw_ostream &OS) const {
+    OS << "\n\n---- Block Freqs ----\n";
+    for (typename FunctionT::iterator I = Fn->begin(), E = Fn->end(); I != E;) {
+      BlockT *BB = I++;
+      OS << " " << getBlockName(BB) << " = " << getBlockFreq(BB) << "\n";
+
+      for (typename GraphTraits<BlockT *>::ChildIteratorType
+           SI = GraphTraits<BlockT *>::child_begin(BB),
+           SE = GraphTraits<BlockT *>::child_end(BB); SI != SE; ++SI) {
+        BlockT *Succ = *SI;
+        OS << "  " << getBlockName(BB) << " -> " << getBlockName(Succ)
+           << " = " << getEdgeFreq(BB, Succ) << "\n";
+      }
+    }
+  }
+
+  void dump() const {
+    print(dbgs());
+  }
+};
+
+}
+
+#endif

Added: llvm/trunk/lib/Analysis/BlockFrequency.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BlockFrequency.cpp?rev=133767&view=auto
==============================================================================
--- llvm/trunk/lib/Analysis/BlockFrequency.cpp (added)
+++ llvm/trunk/lib/Analysis/BlockFrequency.cpp Thu Jun 23 16:56:59 2011
@@ -0,0 +1,59 @@
+//=======-------- BlockFrequency.cpp - Block Frequency Analysis -------=======//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// Loops should be simplified before this analysis.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/InitializePasses.h"
+#include "llvm/Analysis/BlockFrequencyImpl.h"
+#include "llvm/Analysis/BlockFrequency.h"
+#include "llvm/Analysis/LoopInfo.h"
+#include "llvm/Analysis/Passes.h"
+#include "llvm/Analysis/BranchProbabilityInfo.h"
+
+using namespace llvm;
+
+INITIALIZE_PASS_BEGIN(BlockFrequency, "block-freq", "Block Frequency Analysis",
+                      true, true)
+INITIALIZE_PASS_DEPENDENCY(BranchProbabilityInfo)
+INITIALIZE_PASS_END(BlockFrequency, "block-freq", "Block Frequency Analysis",
+                    true, true)
+
+char BlockFrequency::ID = 0;
+
+
+BlockFrequency::BlockFrequency() : FunctionPass(ID) {
+  initializeBlockFrequencyPass(*PassRegistry::getPassRegistry());
+  BFI = new BlockFrequencyImpl<BasicBlock, Function, BranchProbabilityInfo>();
+}
+
+BlockFrequency::~BlockFrequency() {
+  delete BFI;
+}
+
+void BlockFrequency::getAnalysisUsage(AnalysisUsage &AU) const {
+  AU.addRequired<BranchProbabilityInfo>();
+  AU.setPreservesAll();
+}
+
+bool BlockFrequency::runOnFunction(Function &F) {
+  BranchProbabilityInfo &BPI = getAnalysis<BranchProbabilityInfo>();
+  BFI->doFunction(&F, &BPI);
+  return false;
+}
+
+/// getblockFreq - Return block frequency. Never return 0, value must be
+/// positive. Please note that initial frequency is equal to 1024. It means that
+/// we should not rely on the value itself, but only on the comparison to the
+/// other block frequencies. We do this to avoid using of floating points.
+///
+uint32_t BlockFrequency::getBlockFreq(BasicBlock *BB) {
+  return BFI->getBlockFreq(BB);
+}



From grosbach at apple.com  Thu Jun 23 17:29:01 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 23 Jun 2011 22:29:01 -0000
Subject: [llvm-commits] [llvm] r133770 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20110623222901.0CF212A6C12D@llvm.org>

Author: grosbach
Date: Thu Jun 23 17:29:00 2011
New Revision: 133770

URL: http://llvm.org/viewvc/llvm-project?rev=133770&view=rev
Log:
Tidy up.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=133770&r1=133769&r2=133770&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Thu Jun 23 17:29:00 2011
@@ -123,7 +123,7 @@
                             const MCAsmLayout &Layout) const;
 
   uint64_t getFragmentAddress(const MCFragment *Fragment,
-                            const MCAsmLayout &Layout) const {
+                              const MCAsmLayout &Layout) const {
     return getSectionAddress(Fragment->getParent()) +
       Layout.getFragmentOffset(Fragment);
   }



From aggarwa4 at illinois.edu  Thu Jun 23 17:29:18 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 23 Jun 2011 22:29:18 -0000
Subject: [llvm-commits] [poolalloc] r133771 -
 /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
Message-ID: <20110623222918.11A542A6C12D@llvm.org>

Author: aggarwa4
Date: Thu Jun 23 17:29:17 2011
New Revision: 133771

URL: http://llvm.org/viewvc/llvm-project?rev=133771&view=rev
Log:
Fix the printing functions.

Modified:
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=133771&r1=133770&r2=133771&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Thu Jun 23 17:29:17 2011
@@ -2,6 +2,7 @@
 #include <inttypes.h>
 #include <stdint.h>
 #include <stdio.h>
+#include <iostream.h>
 #include <stdlib.h>
 #include <string.h>
 #include <netdb.h>
@@ -140,7 +141,7 @@
   shadow_begin[p] = typeNumber;
   memset(&shadow_begin[p + 1], 0, size - 1);
 #if DEBUG
-  printf("Global(%d): %p, %p = %u | %lu bytes\n", tag, ptr, (void *)p, typeNumber, size);
+  cerr << "Global(" << tag << "): " << ptr << "= " << typeNumber << " " << size << "bytes\n";
 #endif
 }
 
@@ -166,7 +167,7 @@
   shadow_begin[p] = typeNumber;
   memset(&shadow_begin[p + 1], 0, size - 1);
 #if DEBUG
-  printf("Store(%d): %p, %p = %u | %lu bytes | \n", tag, ptr, (void *)p, typeNumber, size);
+  cerr << "Store(" << tag << "): " << ptr << "= " << typeNumber << " " << size << "bytes\n";
 #endif
 }
 
@@ -191,7 +192,7 @@
  */
 void compareNumber(uint64_t NumArgsPassed, uint64_t ArgAccessed, uint32_t tag){
   if(ArgAccessed > NumArgsPassed) {
-    printf("Type mismatch(%u): Accessing variable %lu, passed only %lu! \n", tag, ArgAccessed, NumArgsPassed);
+    cerr << "Type mismatch " << tag << "Accessing variable " << ArgAccessed << "passed only " << NumArgsPassed;
   }
 }
 
@@ -260,7 +261,7 @@
   uintptr_t p = maskAddress(ptr);
   memset(&shadow_begin[p], 0xFF, size);
 #if DEBUG
-  printf("Initialize: %p, %p | %lu bytes | %u\n", ptr, (void *)p, size, tag);
+  cerr << "Initialize(" << tag << "): " << ptr << " " << size << "bytes\n";
 #endif
 }
 
@@ -271,7 +272,7 @@
   uintptr_t p = maskAddress(ptr);
   memset(&shadow_begin[p], 0x00, size);
 #if DEBUG
-  printf("Unitialize: %p, %p | %lu bytes | %u\n", ptr, (void *)p, size, tag);
+  cerr << "Uninitialize(" << tag << "): " << ptr << " " << size << "bytes\n";
 #endif
 }
 
@@ -283,7 +284,7 @@
   uintptr_t s = maskAddress(srcptr);
   memcpy(&shadow_begin[d], &shadow_begin[s], size);
 #if DEBUG
-  printf("Copy(%d): %p, %p = %u | %lu bytes \n", tag, dstptr, srcptr, shadow_begin[s], size);
+  cerr << "Copy(" << tag << "): Dest = " << dstptr << " Source = " << srcptr << " " << size << "bytes\n";
 #endif
 }
 
@@ -294,7 +295,7 @@
   uintptr_t d = maskAddress(dstptr);
   memcpy(&shadow_begin[d], metadata, size);
 #if DEBUG
-  printf("Set(%d): %p, %p | %lu bytes \n", tag, dstptr, metadata, size);
+  cerr << "Set(" << tag << "): Dest = " << dstptr << " Source = " << metadata << " " << size << "bytes\n";
 #endif
 }
 



From stoklund at 2pi.dk  Thu Jun 23 17:39:33 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 23 Jun 2011 15:39:33 -0700
Subject: [llvm-commits] [llvm] r133766 - in /llvm/trunk:
 include/llvm/Analysis/BranchProbabilityInfo.h
 include/llvm/InitializePasses.h include/llvm/Support/BranchProbability.h
 lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp
 lib/Analysis/CMakeLists.txt
In-Reply-To: <20110623214520.7638D2A6C12C@llvm.org>
References: <20110623214520.7638D2A6C12C@llvm.org>
Message-ID: <70E0F015-544D-4A39-BDD2-511C4E3A39FA@2pi.dk>


On Jun 23, 2011, at 2:45 PM, Jakub Staszak wrote:

> +  // Get sum of the edge weights going to the BB block.
> +  uint32_t getBackSumForBlock(BasicBlock *BB) const;

This function doesn't make sense. The weights in different predecessors are unrelated, adding them doesn't give you a useful result.

> +  // Return a probability of getting to the DST block through SRC->DST edge.
> +  // Returned value is a fraction between 0 (0% probability) and
> +  // 1 (100% probability), however the value is never equal to 0, and can be 1
> +  // only iff DST block has only one predecesor.
> +  BranchProbability getBackEdgeProbability(BasicBlock *Src,
> +                                           BasicBlock *Dst) const;

Which means that this function is returning nonsense.

/jakob



From jstaszak at apple.com  Thu Jun 23 18:01:29 2011
From: jstaszak at apple.com (Jakub Staszak)
Date: Thu, 23 Jun 2011 16:01:29 -0700
Subject: [llvm-commits] [llvm] r133766 - in /llvm/trunk:
 include/llvm/Analysis/BranchProbabilityInfo.h
 include/llvm/InitializePasses.h include/llvm/Support/BranchProbability.h
 lib/Analysis/Analysis.cpp lib/Analysis/BranchProbabilityInfo.cpp
 lib/Analysis/CMakeLists.txt
In-Reply-To: <70E0F015-544D-4A39-BDD2-511C4E3A39FA@2pi.dk>
References: <20110623214520.7638D2A6C12C@llvm.org>
	<70E0F015-544D-4A39-BDD2-511C4E3A39FA@2pi.dk>
Message-ID: <33CCF9C8-CFCC-440A-B4E3-D6656DB3F517@apple.com>

Hi Jacob,

You are right. It makes sense only if we have profile info, it other case it wouldn't work fine. I'm working on the fix now.

-Kuba

On Jun 23, 2011, at 3:39 PM, Jakob Stoklund Olesen wrote:

> 
> On Jun 23, 2011, at 2:45 PM, Jakub Staszak wrote:
> 
>> +  // Get sum of the edge weights going to the BB block.
>> +  uint32_t getBackSumForBlock(BasicBlock *BB) const;
> 
> This function doesn't make sense. The weights in different predecessors are unrelated, adding them doesn't give you a useful result.
> 
>> +  // Return a probability of getting to the DST block through SRC->DST edge.
>> +  // Returned value is a fraction between 0 (0% probability) and
>> +  // 1 (100% probability), however the value is never equal to 0, and can be 1
>> +  // only iff DST block has only one predecesor.
>> +  BranchProbability getBackEdgeProbability(BasicBlock *Src,
>> +                                           BasicBlock *Dst) const;
> 
> Which means that this function is returning nonsense.
> 
> /jakob
> 
> 

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From jstaszak at apple.com  Thu Jun 23 18:52:11 2011
From: jstaszak at apple.com (Jakub Staszak)
Date: Thu, 23 Jun 2011 23:52:11 -0000
Subject: [llvm-commits] [llvm] r133776 - in /llvm/trunk:
 include/llvm/Analysis/BlockFrequencyImpl.h
 include/llvm/Analysis/BranchProbabilityInfo.h
 lib/Analysis/BranchProbabilityInfo.cpp
Message-ID: <20110623235211.A5CA82A6C12C@llvm.org>

Author: kuba
Date: Thu Jun 23 18:52:11 2011
New Revision: 133776

URL: http://llvm.org/viewvc/llvm-project?rev=133776&view=rev
Log:
Calculate backedge probability correctly.

Modified:
    llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h
    llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
    llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp

Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h?rev=133776&r1=133775&r2=133776&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h (original)
+++ llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h Thu Jun 23 18:52:11 2011
@@ -133,6 +133,15 @@
   }
 
 
+  /// Return a probability of getting to the DST block through SRC->DST edge.
+  ///
+  BranchProbability getBackEdgeProbability(BlockT *Src, BlockT *Dst) const {
+    uint32_t N = getEdgeFreq(Src, Dst);
+    uint32_t D = getBlockFreq(Dst);
+
+    return BranchProbability(N, D);
+  }
+
   /// isReachable - Returns if BB block is reachable from the entry.
   ///
   bool isReachable(BlockT *BB) {
@@ -213,7 +222,9 @@
       return;
 
     assert(START_FREQ >= CycleProb[BB]);
-    divBlockFreq(BB, BranchProbability(START_FREQ - CycleProb[BB], START_FREQ));
+    uint32_t CProb = CycleProb[BB];
+    uint32_t Numerator = START_FREQ - CProb ? START_FREQ - CProb : 1;
+    divBlockFreq(BB, BranchProbability(Numerator, START_FREQ));
   }
 
   /// doLoop - Propagate block frequency down throught the loop.
@@ -238,19 +249,17 @@
       BlockT *Pred = *PI;
       assert(Pred);
       if (isReachable(Pred) && isBackedge(Pred, Head)) {
-        BranchProbability Prob = BPI->getBackEdgeProbability(Pred, Head);
+        BranchProbability Prob = getBackEdgeProbability(Pred, Head);
         uint64_t N = Prob.getNumerator();
         uint64_t D = Prob.getDenominator();
         uint64_t Res = (N * START_FREQ) / D;
 
-        // CycleProb[Head] += getEdgeFreq(Pred, Head);
         assert(Res <= UINT32_MAX);
         CycleProb[Head] += (uint32_t) Res;
       }
     }
   }
 
-
   friend class BlockFrequency;
 
   void doFunction(FunctionT *fn, BlockProbInfoT *bpi) {

Modified: llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h?rev=133776&r1=133775&r2=133776&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h (original)
+++ llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h Thu Jun 23 18:52:11 2011
@@ -39,9 +39,6 @@
   // Get sum of the block successors' weights.
   uint32_t getSumForBlock(BasicBlock *BB) const;
 
-  // Get sum of the edge weights going to the BB block.
-  uint32_t getBackSumForBlock(BasicBlock *BB) const;
-
 public:
   static char ID;
 
@@ -74,13 +71,6 @@
   // only iff SRC block has only one successor.
   BranchProbability getEdgeProbability(BasicBlock *Src, BasicBlock *Dst) const;
 
-  // Return a probability of getting to the DST block through SRC->DST edge.
-  // Returned value is a fraction between 0 (0% probability) and
-  // 1 (100% probability), however the value is never equal to 0, and can be 1
-  // only iff DST block has only one predecesor.
-  BranchProbability getBackEdgeProbability(BasicBlock *Src,
-                                           BasicBlock *Dst) const;
-
   // Print value between 0 (0% probability) and 1 (100% probability),
   // however the value is never equal to 0, and can be 1 only iff SRC block
   // has only one successor.

Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=133776&r1=133775&r2=133776&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original)
+++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Thu Jun 23 18:52:11 2011
@@ -279,21 +279,6 @@
   return Sum;
 }
 
-uint32_t BranchProbabilityInfo::getBackSumForBlock(BasicBlock *BB) const {
-  uint32_t Sum = 0;
-
-  for (pred_iterator I = pred_begin(BB), E = pred_end(BB); I != E; ++I) {
-    BasicBlock *Pred = *I;
-    uint32_t Weight = getEdgeWeight(Pred, BB);
-    uint32_t PrevSum = Sum;
-
-    Sum += Weight;
-    assert(Sum > PrevSum); (void) PrevSum;
-  }
-
-  return Sum;
-}
-
 bool BranchProbabilityInfo::isEdgeHot(BasicBlock *Src, BasicBlock *Dst) const {
   // Hot probability is at least 4/5 = 80%
   uint32_t Weight = getEdgeWeight(Src, Dst);
@@ -360,15 +345,6 @@
   return BranchProbability(N, D);
 }
 
-BranchProbability BranchProbabilityInfo::
-getBackEdgeProbability(BasicBlock *Src, BasicBlock *Dst) const {
-
-  uint32_t N = getEdgeWeight(Src, Dst);
-  uint32_t D = getBackSumForBlock(Dst);
-
-  return BranchProbability(N, D);
-}
-
 raw_ostream &
 BranchProbabilityInfo::printEdgeProbability(raw_ostream &OS, BasicBlock *Src,
                                             BasicBlock *Dst) const {



From evan.cheng at apple.com  Thu Jun 23 20:44:41 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Jun 2011 01:44:41 -0000
Subject: [llvm-commits] [llvm] r133782 - in /llvm/trunk: ./ include/llvm/MC/
 include/llvm/Target/ lib/CodeGen/ lib/Target/ lib/Target/ARM/
 lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/
 lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/
 lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/
 lib/Target/X86/TargetDesc/ lib/Target/XCore/ utils/TableGen/
Message-ID: <20110624014442.9ECEB2A6C12C@llvm.org>

Author: evancheng
Date: Thu Jun 23 20:44:41 2011
New Revision: 133782

URL: http://llvm.org/viewvc/llvm-project?rev=133782&view=rev
Log:
Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.

First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.

Added:
    llvm/trunk/include/llvm/MC/MCRegisterInfo.h
    llvm/trunk/lib/Target/X86/TargetDesc/
    llvm/trunk/lib/Target/X86/TargetDesc/Makefile
    llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp
    llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h
Modified:
    llvm/trunk/Makefile.rules
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/include/llvm/Target/TargetRegistry.h
    llvm/trunk/lib/CodeGen/RegisterClassInfo.h
    llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/CMakeLists.txt
    llvm/trunk/lib/Target/ARM/Makefile
    llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
    llvm/trunk/lib/Target/Alpha/CMakeLists.txt
    llvm/trunk/lib/Target/Alpha/Makefile
    llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
    llvm/trunk/lib/Target/Blackfin/CMakeLists.txt
    llvm/trunk/lib/Target/Blackfin/Makefile
    llvm/trunk/lib/Target/CellSPU/Makefile
    llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
    llvm/trunk/lib/Target/MBlaze/CMakeLists.txt
    llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
    llvm/trunk/lib/Target/MBlaze/Makefile
    llvm/trunk/lib/Target/MSP430/CMakeLists.txt
    llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
    llvm/trunk/lib/Target/MSP430/Makefile
    llvm/trunk/lib/Target/Mips/CMakeLists.txt
    llvm/trunk/lib/Target/Mips/Makefile
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
    llvm/trunk/lib/Target/PTX/CMakeLists.txt
    llvm/trunk/lib/Target/PTX/Makefile
    llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp
    llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h
    llvm/trunk/lib/Target/PowerPC/CMakeLists.txt
    llvm/trunk/lib/Target/PowerPC/Makefile
    llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
    llvm/trunk/lib/Target/Sparc/CMakeLists.txt
    llvm/trunk/lib/Target/Sparc/Makefile
    llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
    llvm/trunk/lib/Target/SystemZ/CMakeLists.txt
    llvm/trunk/lib/Target/SystemZ/Makefile
    llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
    llvm/trunk/lib/Target/TargetRegisterInfo.cpp
    llvm/trunk/lib/Target/X86/CMakeLists.txt
    llvm/trunk/lib/Target/X86/Makefile
    llvm/trunk/lib/Target/X86/X86.h
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/XCore/CMakeLists.txt
    llvm/trunk/lib/Target/XCore/Makefile
    llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.h
    llvm/trunk/utils/TableGen/TableGen.cpp

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Thu Jun 23 20:44:41 2011
@@ -1725,15 +1725,20 @@
 	$(Echo) "Building $(<F) register names with tblgen"
 	$(Verb) $(TableGen) -gen-register-enums -o $(call SYSPATH, $@) $<
 
+$(TARGET:%=$(ObjDir)/%GenRegisterDesc.inc.tmp): \
+$(ObjDir)/%GenRegisterDesc.inc.tmp : %.td $(ObjDir)/.dir
+	$(Echo) "Building $(<F) register descriptions with tblgen"
+	$(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $<
+
 $(TARGET:%=$(ObjDir)/%GenRegisterInfo.h.inc.tmp): \
 $(ObjDir)/%GenRegisterInfo.h.inc.tmp : %.td $(ObjDir)/.dir
 	$(Echo) "Building $(<F) register information header with tblgen"
-	$(Verb) $(TableGen) -gen-register-desc-header -o $(call SYSPATH, $@) $<
+	$(Verb) $(TableGen) -gen-register-info-header -o $(call SYSPATH, $@) $<
 
 $(TARGET:%=$(ObjDir)/%GenRegisterInfo.inc.tmp): \
 $(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir
 	$(Echo) "Building $(<F) register info implementation with tblgen"
-	$(Verb) $(TableGen) -gen-register-desc -o $(call SYSPATH, $@) $<
+	$(Verb) $(TableGen) -gen-register-info -o $(call SYSPATH, $@) $<
 
 $(TARGET:%=$(ObjDir)/%GenInstrNames.inc.tmp): \
 $(ObjDir)/%GenInstrNames.inc.tmp : %.td $(ObjDir)/.dir

Added: llvm/trunk/include/llvm/MC/MCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCRegisterInfo.h?rev=133782&view=auto
==============================================================================
--- llvm/trunk/include/llvm/MC/MCRegisterInfo.h (added)
+++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Thu Jun 23 20:44:41 2011
@@ -0,0 +1,123 @@
+//=== MC/MCRegisterInfo.h - Target Register Description ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes an abstract interface used to get information about a
+// target machines register file.  This information is used for a variety of
+// purposed, especially register allocation.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MC_MCREGISTERINFO_H
+#define LLVM_MC_MCREGISTERINFO_H
+
+#include <cassert>
+
+namespace llvm {
+
+/// TargetRegisterDesc - This record contains all of the information known about
+/// a particular register.  The Overlaps field contains a pointer to a zero
+/// terminated array of registers that this register aliases, starting with
+/// itself. This is needed for architectures like X86 which have AL alias AX
+/// alias EAX. The SubRegs field is a zero terminated array of registers that
+/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
+/// AX. The SuperRegs field is a zero terminated array of registers that are
+/// super-registers of the specific register, e.g. RAX, EAX, are super-registers
+/// of AX.
+///
+struct TargetRegisterDesc {
+  const char     *Name;         // Printable name for the reg (for debugging)
+  const unsigned *Overlaps;     // Overlapping registers, described above
+  const unsigned *SubRegs;      // Sub-register set, described above
+  const unsigned *SuperRegs;    // Super-register set, described above
+};
+
+/// MCRegisterInfo base class - We assume that the target defines a static
+/// array of TargetRegisterDesc objects that represent all of the machine
+/// registers that the target has.  As such, we simply have to track a pointer
+/// to this array so that we can turn register number into a register
+/// descriptor.
+///
+class MCRegisterInfo {
+private:
+  const TargetRegisterDesc *Desc;             // Pointer to the descriptor array
+  unsigned NumRegs;                           // Number of entries in the array
+
+public:
+  /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
+  /// auto-generated routines. *DO NOT USE*.
+  void InitMCRegisterInfo(const TargetRegisterDesc *D, unsigned NR) {
+    Desc = D;
+    NumRegs = NR;
+  }
+    
+  const TargetRegisterDesc &operator[](unsigned RegNo) const {
+    assert(RegNo < NumRegs &&
+           "Attempting to access record for invalid register number!");
+    return Desc[RegNo];
+  }
+
+  /// Provide a get method, equivalent to [], but more useful if we have a
+  /// pointer to this object.
+  ///
+  const TargetRegisterDesc &get(unsigned RegNo) const {
+    return operator[](RegNo);
+  }
+
+  /// getAliasSet - Return the set of registers aliased by the specified
+  /// register, or a null list of there are none.  The list returned is zero
+  /// terminated.
+  ///
+  const unsigned *getAliasSet(unsigned RegNo) const {
+    // The Overlaps set always begins with Reg itself.
+    return get(RegNo).Overlaps + 1;
+  }
+
+  /// getOverlaps - Return a list of registers that overlap Reg, including
+  /// itself. This is the same as the alias set except Reg is included in the
+  /// list.
+  /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
+  ///
+  const unsigned *getOverlaps(unsigned RegNo) const {
+    return get(RegNo).Overlaps;
+  }
+
+  /// getSubRegisters - Return the list of registers that are sub-registers of
+  /// the specified register, or a null list of there are none. The list
+  /// returned is zero terminated and sorted according to super-sub register
+  /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
+  ///
+  const unsigned *getSubRegisters(unsigned RegNo) const {
+    return get(RegNo).SubRegs;
+  }
+
+  /// getSuperRegisters - Return the list of registers that are super-registers
+  /// of the specified register, or a null list of there are none. The list
+  /// returned is zero terminated and sorted according to super-sub register
+  /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
+  ///
+  const unsigned *getSuperRegisters(unsigned RegNo) const {
+    return get(RegNo).SuperRegs;
+  }
+
+  /// getName - Return the human-readable symbolic target-specific name for the
+  /// specified physical register.
+  const char *getName(unsigned RegNo) const {
+    return get(RegNo).Name;
+  }
+
+  /// getNumRegs - Return the number of registers this target has (useful for
+  /// sizing arrays holding per register information)
+  unsigned getNumRegs() const {
+    return NumRegs;
+  }
+};
+ 
+} // End llvm namespace
+
+#endif

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu Jun 23 20:44:41 2011
@@ -16,6 +16,7 @@
 #ifndef LLVM_TARGET_TARGETREGISTERINFO_H
 #define LLVM_TARGET_TARGETREGISTERINFO_H
 
+#include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/ValueTypes.h"
 #include "llvm/ADT/ArrayRef.h"
@@ -32,25 +33,6 @@
 template<class T> class SmallVectorImpl;
 class raw_ostream;
 
-/// TargetRegisterDesc - This record contains all of the information known about
-/// a particular register.  The Overlaps field contains a pointer to a zero
-/// terminated array of registers that this register aliases, starting with
-/// itself. This is needed for architectures like X86 which have AL alias AX
-/// alias EAX. The SubRegs field is a zero terminated array of registers that
-/// are sub-registers of the specific register, e.g. AL, AH are sub-registers of
-/// AX. The SuperRegs field is a zero terminated array of registers that are
-/// super-registers of the specific register, e.g. RAX, EAX, are super-registers
-/// of AX.
-///
-struct TargetRegisterDesc {
-  const char     *Name;         // Printable name for the reg (for debugging)
-  const unsigned *Overlaps;     // Overlapping registers, described above
-  const unsigned *SubRegs;      // Sub-register set, described above
-  const unsigned *SuperRegs;    // Super-register set, described above
-  unsigned CostPerUse;          // Extra cost of instructions using register.
-  bool inAllocatableClass;      // Register belongs to an allocatable regclass.
-};
-
 class TargetRegisterClass {
 public:
   typedef const unsigned* iterator;
@@ -274,6 +256,12 @@
   bool isAllocatable() const { return Allocatable; }
 };
 
+/// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
+/// registers. These are used by codegen, not by MC.
+struct TargetRegisterInfoDesc {
+  unsigned CostPerUse;          // Extra cost of instructions using register.
+  bool inAllocatableClass;      // Register belongs to an allocatable regclass.
+};
 
 /// TargetRegisterInfo base class - We assume that the target defines a static
 /// array of TargetRegisterDesc objects that represent all of the machine
@@ -281,20 +269,17 @@
 /// to this array so that we can turn register number into a register
 /// descriptor.
 ///
-class TargetRegisterInfo {
+class TargetRegisterInfo : public MCRegisterInfo {
 public:
   typedef const TargetRegisterClass * const * regclass_iterator;
 private:
-  const TargetRegisterDesc *Desc;             // Pointer to the descriptor array
+  const TargetRegisterInfoDesc *InfoDesc;     // Extra desc array for codegen
   const char *const *SubRegIndexNames;        // Names of subreg indexes.
-  unsigned NumRegs;                           // Number of entries in the array
-
   regclass_iterator RegClassBegin, RegClassEnd;   // List of regclasses
-
   int CallFrameSetupOpcode, CallFrameDestroyOpcode;
 
 protected:
-  TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
+  TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
                      regclass_iterator RegClassBegin,
                      regclass_iterator RegClassEnd,
                      const char *const *subregindexnames,
@@ -379,71 +364,16 @@
   BitVector getAllocatableSet(const MachineFunction &MF,
                               const TargetRegisterClass *RC = NULL) const;
 
-  const TargetRegisterDesc &operator[](unsigned RegNo) const {
-    assert(RegNo < NumRegs &&
-           "Attempting to access record for invalid register number!");
-    return Desc[RegNo];
-  }
-
-  /// Provide a get method, equivalent to [], but more useful if we have a
-  /// pointer to this object.
-  ///
-  const TargetRegisterDesc &get(unsigned RegNo) const {
-    return operator[](RegNo);
-  }
-
-  /// getAliasSet - Return the set of registers aliased by the specified
-  /// register, or a null list of there are none.  The list returned is zero
-  /// terminated.
-  ///
-  const unsigned *getAliasSet(unsigned RegNo) const {
-    // The Overlaps set always begins with Reg itself.
-    return get(RegNo).Overlaps + 1;
-  }
-
-  /// getOverlaps - Return a list of registers that overlap Reg, including
-  /// itself. This is the same as the alias set except Reg is included in the
-  /// list.
-  /// These are exactly the registers in { x | regsOverlap(x, Reg) }.
-  ///
-  const unsigned *getOverlaps(unsigned RegNo) const {
-    return get(RegNo).Overlaps;
-  }
-
-  /// getSubRegisters - Return the list of registers that are sub-registers of
-  /// the specified register, or a null list of there are none. The list
-  /// returned is zero terminated and sorted according to super-sub register
-  /// relations. e.g. X86::RAX's sub-register list is EAX, AX, AL, AH.
-  ///
-  const unsigned *getSubRegisters(unsigned RegNo) const {
-    return get(RegNo).SubRegs;
-  }
-
-  /// getSuperRegisters - Return the list of registers that are super-registers
-  /// of the specified register, or a null list of there are none. The list
-  /// returned is zero terminated and sorted according to super-sub register
-  /// relations. e.g. X86::AL's super-register list is AX, EAX, RAX.
-  ///
-  const unsigned *getSuperRegisters(unsigned RegNo) const {
-    return get(RegNo).SuperRegs;
-  }
-
-  /// getName - Return the human-readable symbolic target-specific name for the
-  /// specified physical register.
-  const char *getName(unsigned RegNo) const {
-    return get(RegNo).Name;
-  }
-
   /// getCostPerUse - Return the additional cost of using this register instead
   /// of other registers in its class.
   unsigned getCostPerUse(unsigned RegNo) const {
-    return get(RegNo).CostPerUse;
+    return InfoDesc[RegNo].CostPerUse;
   }
 
-  /// getNumRegs - Return the number of registers this target has (useful for
-  /// sizing arrays holding per register information)
-  unsigned getNumRegs() const {
-    return NumRegs;
+  /// isInAllocatableClass - Return true if the register is in the allocation
+  /// of any register class.
+  bool isInAllocatableClass(unsigned RegNo) const {
+    return InfoDesc[RegNo].inAllocatableClass;
   }
 
   /// getSubRegIndexName - Return the human-readable symbolic target-specific

Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegistry.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegistry.h Thu Jun 23 20:44:41 2011
@@ -33,6 +33,7 @@
   class MCContext;
   class MCDisassembler;
   class MCInstPrinter;
+  class MCRegisterInfo;
   class MCStreamer;
   class TargetAsmBackend;
   class TargetAsmLexer;
@@ -64,7 +65,9 @@
     typedef unsigned (*TripleMatchQualityFnTy)(const std::string &TT);
 
     typedef MCAsmInfo *(*AsmInfoCtorFnTy)(const Target &T,
-                                                StringRef TT);
+                                          StringRef TT);
+    typedef MCRegisterInfo *(*RegInfoCtorFnTy)(const Target &T,
+                                               StringRef TT);
     typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
                                                   const std::string &TT,
                                                   const std::string &Features);
@@ -120,8 +123,14 @@
     /// HasJIT - Whether this target supports the JIT.
     bool HasJIT;
 
+    /// AsmInfoCtorFn - Constructor function for this target's MCAsmInfo, if
+    /// registered.
     AsmInfoCtorFnTy AsmInfoCtorFn;
 
+    /// RegInfoCtorFn - Constructor function for this target's MCRegisterInfo,
+    /// if registered.
+    RegInfoCtorFnTy RegInfoCtorFn;
+
     /// TargetMachineCtorFn - Construction function for this target's
     /// TargetMachine, if registered.
     TargetMachineCtorTy TargetMachineCtorFn;
@@ -231,6 +240,19 @@
       return AsmInfoCtorFn(*this, Triple);
     }
 
+    /// createRegInfo - Create a MCRegisterInfo implementation for the specified
+    /// target triple.
+    ///
+    /// \arg Triple - This argument is used to determine the target machine
+    /// feature set; it should always be provided. Generally this should be
+    /// either the target triple from the module, or the target triple of the
+    /// host if that does not exist.
+    MCRegisterInfo *createRegInfo(StringRef Triple) const {
+      if (!RegInfoCtorFn)
+        return 0;
+      return RegInfoCtorFn(*this, Triple);
+    }
+
     /// createTargetMachine - Create a target specific machine implementation
     /// for the specified \arg Triple.
     ///
@@ -444,6 +466,21 @@
         T.AsmInfoCtorFn = Fn;
     }
 
+    /// RegisterRegInfo - Register a MCRegisterInfo implementation for the
+    /// given target.
+    ///
+    /// Clients are responsible for ensuring that registration doesn't occur
+    /// while another thread is attempting to access the registry. Typically
+    /// this is done by initializing all targets at program startup.
+    ///
+    /// @param T - The target being registered.
+    /// @param Fn - A function to construct a MCRegisterInfo for the target.
+    static void RegisterRegInfo(Target &T, Target::RegInfoCtorFnTy Fn) {
+      // Ignore duplicate registration.
+      if (!T.RegInfoCtorFn)
+        T.RegInfoCtorFn = Fn;
+    }
+
     /// RegisterTargetMachine - Register a TargetMachine implementation for the
     /// given target.
     ///

Modified: llvm/trunk/lib/CodeGen/RegisterClassInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterClassInfo.h?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterClassInfo.h (original)
+++ llvm/trunk/lib/CodeGen/RegisterClassInfo.h Thu Jun 23 20:44:41 2011
@@ -112,7 +112,7 @@
   /// register, so a register allocator needs to track its liveness and
   /// availability.
   bool isAllocatable(unsigned PhysReg) const {
-    return TRI->get(PhysReg).inAllocatableClass && !isReserved(PhysReg);
+    return TRI->isInAllocatableClass(PhysReg) && !isReserved(PhysReg);
   }
 };
 } // end namespace llvm

Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -39,6 +39,8 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Support/CommandLine.h"
+#include "ARMGenRegisterDesc.inc"
+#include "ARMGenRegisterInfo.inc"
 
 using namespace llvm;
 
@@ -54,7 +56,8 @@
 
 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
                                          const ARMSubtarget &sti)
-  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
+  : ARMGenRegisterInfo(ARMRegDesc, ARMRegInfoDesc,
+                       ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
     TII(tii), STI(sti),
     FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
     BasePtr(ARM::R6) {
@@ -1287,5 +1290,3 @@
       MI.setDesc(TII.get(ARM::t2SUBri));
   }
 }
-
-#include "ARMGenRegisterInfo.inc"

Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS ARM.td)
 
-tablegen(ARMGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(ARMGenRegisterNames.inc -gen-register-enums)
-tablegen(ARMGenRegisterInfo.inc -gen-register-desc)
+tablegen(ARMGenRegisterDesc.inc -gen-register-desc)
+tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(ARMGenRegisterInfo.inc -gen-register-info)
 tablegen(ARMGenInstrNames.inc -gen-instr-enums)
 tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
 tablegen(ARMGenCodeEmitter.inc -gen-emitter)

Modified: llvm/trunk/lib/Target/ARM/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Makefile (original)
+++ llvm/trunk/lib/Target/ARM/Makefile Thu Jun 23 20:44:41 2011
@@ -12,9 +12,10 @@
 TARGET = ARM
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = ARMGenRegisterInfo.h.inc ARMGenRegisterNames.inc \
-                ARMGenRegisterInfo.inc ARMGenInstrNames.inc \
-                ARMGenInstrInfo.inc ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
+BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \
+                ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \
+		ARMGenInstrNames.inc ARMGenInstrInfo.inc \
+		ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
                 ARMGenDAGISel.inc ARMGenSubtarget.inc \
                 ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
                 ARMGenDecoderTables.inc ARMGenEDInfo.inc \

Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -33,10 +33,13 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include <cstdlib>
+#include "AlphaGenRegisterDesc.inc"
+#include "AlphaGenRegisterInfo.inc"
 using namespace llvm;
 
 AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii)
-  : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
+  : AlphaGenRegisterInfo(AlphaRegDesc, AlphaRegInfoDesc,
+                         Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
     TII(tii) {
 }
 
@@ -204,10 +207,8 @@
   return -1;
 }
 
-#include "AlphaGenRegisterInfo.inc"
-
 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
 {
-  std::string s(RegisterDescriptors[reg].Name);
+  std::string s(AlphaRegDesc[reg].Name);
   return s;
 }

Modified: llvm/trunk/lib/Target/Alpha/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Alpha/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS Alpha.td)
 
-tablegen(AlphaGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
-tablegen(AlphaGenRegisterInfo.inc -gen-register-desc)
+tablegen(AlphaGenRegisterDesc.inc -gen-register-desc)
+tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
 tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
 tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
 tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)

Modified: llvm/trunk/lib/Target/Alpha/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/Makefile (original)
+++ llvm/trunk/lib/Target/Alpha/Makefile Thu Jun 23 20:44:41 2011
@@ -12,9 +12,9 @@
 TARGET = Alpha
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = AlphaGenRegisterInfo.h.inc AlphaGenRegisterNames.inc \
-                AlphaGenRegisterInfo.inc AlphaGenInstrNames.inc \
-                AlphaGenInstrInfo.inc \
+BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \
+                AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \
+		AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \
                 AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
                 AlphaGenCallingConv.inc AlphaGenSubtarget.inc
 

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -29,11 +29,14 @@
 #include "llvm/Type.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "BlackfinGenRegisterDesc.inc"
+#include "BlackfinGenRegisterInfo.inc"
 using namespace llvm;
 
 BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st,
                                            const TargetInstrInfo &tii)
-  : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
+  : BlackfinGenRegisterInfo(BlackfinRegDesc, BlackfinRegInfoDesc,
+                            BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
     Subtarget(st),
     TII(tii) {}
 
@@ -356,6 +359,3 @@
   llvm_unreachable("What is the dwarf register number");
   return -1;
 }
-
-#include "BlackfinGenRegisterInfo.inc"
-

Modified: llvm/trunk/lib/Target/Blackfin/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Blackfin/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS Blackfin.td)
 
-tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(BlackfinGenRegisterNames.inc -gen-register-enums)
-tablegen(BlackfinGenRegisterInfo.inc -gen-register-desc)
+tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc)
+tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
 tablegen(BlackfinGenInstrNames.inc -gen-instr-enums)
 tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc)
 tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)

Modified: llvm/trunk/lib/Target/Blackfin/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/Makefile (original)
+++ llvm/trunk/lib/Target/Blackfin/Makefile Thu Jun 23 20:44:41 2011
@@ -12,8 +12,9 @@
 TARGET = Blackfin
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterNames.inc \
-                BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \
+BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \
+		BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \
+		BlackfinGenInstrNames.inc \
                 BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \
                 BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
 		BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc

Modified: llvm/trunk/lib/Target/CellSPU/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/Makefile (original)
+++ llvm/trunk/lib/Target/CellSPU/Makefile Thu Jun 23 20:44:41 2011
@@ -10,8 +10,9 @@
 LEVEL = ../../..
 LIBRARYNAME = LLVMCellSPUCodeGen
 TARGET = SPU
-BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterNames.inc \
+BUILT_SOURCES = SPUGenInstrNames.inc \
 		SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
+		SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \
 		SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \
 		SPUGenInstrInfo.inc SPUGenDAGISel.inc \
 		SPUGenSubtarget.inc SPUGenCallingConv.inc

Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -42,6 +42,8 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include <cstdlib>
+#include "SPUGenRegisterDesc.inc"
+#include "SPUGenRegisterInfo.inc"
 
 using namespace llvm;
 
@@ -185,7 +187,8 @@
 
 SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget,
                                  const TargetInstrInfo &tii) :
-  SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
+  SPUGenRegisterInfo(SPURegDesc, SPURegInfoDesc,
+                     SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
   Subtarget(subtarget),
   TII(tii)
 {
@@ -371,5 +374,3 @@
   assert( Reg && "Register scavenger failed");
   return Reg;
 }
-
-#include "SPUGenRegisterInfo.inc"

Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS MBlaze.td)
 
-tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(MBlazeGenRegisterNames.inc -gen-register-enums)
-tablegen(MBlazeGenRegisterInfo.inc -gen-register-desc)
+tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc)
+tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
 tablegen(MBlazeGenInstrNames.inc -gen-instr-enums)
 tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc)
 tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -36,12 +36,14 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
-
+#include "MBlazeGenRegisterDesc.inc"
+#include "MBlazeGenRegisterInfo.inc"
 using namespace llvm;
 
 MBlazeRegisterInfo::
 MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
-  : MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
+  : MBlazeGenRegisterInfo(MBlazeRegDesc, MBlazeRegInfoDesc,
+                          MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
     Subtarget(ST), TII(tii) {}
 
 /// getRegisterNumbering - Given the enum value for some register, e.g.
@@ -359,6 +361,3 @@
 int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
   return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
 }
-
-#include "MBlazeGenRegisterInfo.inc"
-

Modified: llvm/trunk/lib/Target/MBlaze/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Makefile (original)
+++ llvm/trunk/lib/Target/MBlaze/Makefile Thu Jun 23 20:44:41 2011
@@ -12,12 +12,13 @@
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \
-								MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \
-								MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
-								MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
-								MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
-								MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
-								MBlazeGenEDInfo.inc
+                MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \
+                MBlazeGenInstrNames.inc \
+                MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \
+                MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
+                MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
+                MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
+                MBlazeGenEDInfo.inc
 
 DIRS = InstPrinter AsmParser Disassembler TargetInfo
 

Modified: llvm/trunk/lib/Target/MSP430/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/MSP430/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS MSP430.td)
 
-tablegen(MSP430GenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(MSP430GenRegisterNames.inc -gen-register-enums)
-tablegen(MSP430GenRegisterInfo.inc -gen-register-desc)
+tablegen(MSP430GenRegisterDesc.inc -gen-register-desc)
+tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
 tablegen(MSP430GenInstrNames.inc -gen-instr-enums)
 tablegen(MSP430GenInstrInfo.inc -gen-instr-desc)
 tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)

Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -25,13 +25,16 @@
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/Support/ErrorHandling.h"
+#include "MSP430GenRegisterDesc.inc"
+#include "MSP430GenRegisterInfo.inc"
 
 using namespace llvm;
 
 // FIXME: Provide proper call frame setup / destroy opcodes.
 MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
                                        const TargetInstrInfo &tii)
-  : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
+  : MSP430GenRegisterInfo(MSP430RegDesc, MSP430RegInfoDesc,
+                          MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
     TM(tm), TII(tii) {
   StackAlign = TM.getFrameLowering()->getStackAlignment();
 }
@@ -250,5 +253,3 @@
   llvm_unreachable("Not implemented yet!");
   return 0;
 }
-
-#include "MSP430GenRegisterInfo.inc"

Modified: llvm/trunk/lib/Target/MSP430/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/Makefile (original)
+++ llvm/trunk/lib/Target/MSP430/Makefile Thu Jun 23 20:44:41 2011
@@ -13,7 +13,8 @@
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \
-		MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \
+		MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \
+		MSP430GenInstrNames.inc \
 		MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \
 		MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
 		MSP430GenSubtarget.inc

Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS Mips.td)
 
-tablegen(MipsGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(MipsGenRegisterNames.inc -gen-register-enums)
-tablegen(MipsGenRegisterInfo.inc -gen-register-desc)
+tablegen(MipsGenRegisterDesc.inc -gen-register-desc)
+tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(MipsGenRegisterInfo.inc -gen-register-info)
 tablegen(MipsGenInstrNames.inc -gen-instr-enums)
 tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
 tablegen(MipsGenAsmWriter.inc -gen-asm-writer)

Modified: llvm/trunk/lib/Target/Mips/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Makefile (original)
+++ llvm/trunk/lib/Target/Mips/Makefile Thu Jun 23 20:44:41 2011
@@ -13,7 +13,8 @@
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \
-                MipsGenRegisterInfo.inc MipsGenInstrNames.inc \
+                MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \
+		MipsGenInstrNames.inc \
                 MipsGenInstrInfo.inc MipsGenAsmWriter.inc \
                 MipsGenDAGISel.inc MipsGenCallingConv.inc \
                 MipsGenSubtarget.inc

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -35,12 +35,15 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "MipsGenRegisterDesc.inc"
+#include "MipsGenRegisterInfo.inc"
 
 using namespace llvm;
 
 MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST,
                                    const TargetInstrInfo &tii)
-  : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
+  : MipsGenRegisterInfo(MipsRegDesc, MipsRegInfoDesc,
+                        Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
     Subtarget(ST), TII(tii) {}
 
 /// getRegisterNumbering - Given the enum value for some register, e.g.
@@ -285,5 +288,3 @@
 int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
   return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
 }
-
-#include "MipsGenRegisterInfo.inc"

Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -5,8 +5,9 @@
 tablegen(PTXGenDAGISel.inc -gen-dag-isel)
 tablegen(PTXGenInstrInfo.inc -gen-instr-desc)
 tablegen(PTXGenInstrNames.inc -gen-instr-enums)
-tablegen(PTXGenRegisterInfo.inc -gen-register-desc)
-tablegen(PTXGenRegisterInfo.h.inc -gen-register-desc-header)
+tablegen(PTXGenRegisterDesc.inc -gen-register-desc)
+tablegen(PTXGenRegisterInfo.inc -gen-register-info)
+tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header)
 tablegen(PTXGenRegisterNames.inc -gen-register-enums)
 tablegen(PTXGenSubtarget.inc -gen-subtarget)
 

Modified: llvm/trunk/lib/Target/PTX/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/Makefile (original)
+++ llvm/trunk/lib/Target/PTX/Makefile Thu Jun 23 20:44:41 2011
@@ -17,6 +17,7 @@
 		PTXGenDAGISel.inc \
 		PTXGenInstrInfo.inc \
 		PTXGenInstrNames.inc \
+		PTXGenRegisterDesc.inc \
 		PTXGenRegisterInfo.inc \
 		PTXGenRegisterInfo.h.inc \
 		PTXGenRegisterNames.inc \

Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -19,9 +19,15 @@
 
 using namespace llvm;
 
+#include "PTXGenRegisterDesc.inc"
 #include "PTXGenRegisterInfo.inc"
 
 
+PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM,
+                                 const TargetInstrInfo &TII)
+  : PTXGenRegisterInfo(PTXRegDesc, PTXRegInfoDesc) {
+}
+
 void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                           int SPAdj,
                                           RegScavenger *RS) const {

Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h Thu Jun 23 20:44:41 2011
@@ -25,7 +25,7 @@
 
 struct PTXRegisterInfo : public PTXGenRegisterInfo {
   PTXRegisterInfo(PTXTargetMachine &TM,
-                  const TargetInstrInfo &TII) {}
+                  const TargetInstrInfo &TII);
 
   virtual const unsigned
     *getCalleeSavedRegs(const MachineFunction *MF = 0) const {

Modified: llvm/trunk/lib/Target/PowerPC/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/PowerPC/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -5,8 +5,9 @@
 tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
 tablegen(PPCGenCodeEmitter.inc -gen-emitter)
 tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
-tablegen(PPCGenRegisterInfo.h.inc -gen-register-desc-header)
-tablegen(PPCGenRegisterInfo.inc -gen-register-desc)
+tablegen(PPCGenRegisterDesc.inc -gen-register-desc)
+tablegen(PPCGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(PPCGenRegisterInfo.inc -gen-register-info)
 tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
 tablegen(PPCGenDAGISel.inc -gen-dag-isel)
 tablegen(PPCGenCallingConv.inc -gen-callingconv)

Modified: llvm/trunk/lib/Target/PowerPC/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/Makefile (original)
+++ llvm/trunk/lib/Target/PowerPC/Makefile Thu Jun 23 20:44:41 2011
@@ -14,6 +14,7 @@
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \
                 PPCGenAsmWriter.inc  PPCGenCodeEmitter.inc \
+		PPCGenRegisterDesc.inc \
                 PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \
                 PPCGenInstrInfo.inc PPCGenDAGISel.inc \
                 PPCGenSubtarget.inc PPCGenCallingConv.inc \

Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -43,6 +43,8 @@
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
 #include <cstdlib>
+#include "PPCGenRegisterDesc.inc"
+#include "PPCGenRegisterInfo.inc"
 
 // FIXME (64-bit): Eventually enable by default.
 namespace llvm {
@@ -110,7 +112,8 @@
 
 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST,
                                  const TargetInstrInfo &tii)
-  : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
+  : PPCGenRegisterInfo(PPCRegDesc, PPCRegInfoDesc,
+                       PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
     Subtarget(ST), TII(tii) {
   ImmToIdxMap[PPC::LD]   = PPC::LDX;    ImmToIdxMap[PPC::STD]  = PPC::STDX;
   ImmToIdxMap[PPC::LBZ]  = PPC::LBZX;   ImmToIdxMap[PPC::STB]  = PPC::STBX;
@@ -710,5 +713,3 @@
 
   return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour);
 }
-
-#include "PPCGenRegisterInfo.inc"

Modified: llvm/trunk/lib/Target/Sparc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Sparc/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS Sparc.td)
 
-tablegen(SparcGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(SparcGenRegisterNames.inc -gen-register-enums)
-tablegen(SparcGenRegisterInfo.inc -gen-register-desc)
+tablegen(SparcGenRegisterDesc.inc -gen-register-desc)
+tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(SparcGenRegisterInfo.inc -gen-register-info)
 tablegen(SparcGenInstrNames.inc -gen-instr-enums)
 tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
 tablegen(SparcGenAsmWriter.inc -gen-asm-writer)

Modified: llvm/trunk/lib/Target/Sparc/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/Makefile (original)
+++ llvm/trunk/lib/Target/Sparc/Makefile Thu Jun 23 20:44:41 2011
@@ -13,7 +13,8 @@
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \
-                SparcGenRegisterInfo.inc SparcGenInstrNames.inc \
+                SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \
+		SparcGenInstrNames.inc \
                 SparcGenInstrInfo.inc SparcGenAsmWriter.inc \
                 SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc
 

Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -23,11 +23,14 @@
 #include "llvm/Type.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "SparcGenRegisterDesc.inc"
+#include "SparcGenRegisterInfo.inc"
 using namespace llvm;
 
 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
                                      const TargetInstrInfo &tii)
-  : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
+  : SparcGenRegisterInfo(SparcRegDesc, SparcRegInfoDesc,
+                         SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
     Subtarget(st), TII(tii) {
 }
 
@@ -135,6 +138,3 @@
 int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
   return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
 }
-
-#include "SparcGenRegisterInfo.inc"
-

Modified: llvm/trunk/lib/Target/SystemZ/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/SystemZ/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS SystemZ.td)
 
-tablegen(SystemZGenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(SystemZGenRegisterNames.inc -gen-register-enums)
-tablegen(SystemZGenRegisterInfo.inc -gen-register-desc)
+tablegen(SystemZGenRegisterDesc.inc -gen-register-desc)
+tablegen(SystemZGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
 tablegen(SystemZGenInstrNames.inc -gen-instr-enums)
 tablegen(SystemZGenInstrInfo.inc -gen-instr-desc)
 tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)

Modified: llvm/trunk/lib/Target/SystemZ/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/Makefile (original)
+++ llvm/trunk/lib/Target/SystemZ/Makefile Thu Jun 23 20:44:41 2011
@@ -13,7 +13,8 @@
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \
-                SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \
+                SystemZGenRegisterInfo.inc SystemZGenRegisterDesc.inc \
+		SystemZGenInstrNames.inc \
                 SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \
                 SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc
 

Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -25,11 +25,14 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 #include "llvm/ADT/BitVector.h"
+#include "SystemZGenRegisterDesc.inc"
+#include "SystemZGenRegisterInfo.inc"
 using namespace llvm;
 
 SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm,
                                          const SystemZInstrInfo &tii)
-  : SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
+  : SystemZGenRegisterInfo(SystemZRegDesc, SystemZRegInfoDesc,
+                           SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
     TM(tm), TII(tii) {
 }
 
@@ -153,6 +156,3 @@
   assert(0 && "What is the dwarf register number");
   return -1;
 }
-
-
-#include "SystemZGenRegisterInfo.inc"

Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -20,15 +20,12 @@
 
 using namespace llvm;
 
-TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
+TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
                              regclass_iterator RCB, regclass_iterator RCE,
                              const char *const *subregindexnames,
                              int CFSO, int CFDO)
-  : Desc(D), SubRegIndexNames(subregindexnames), NumRegs(NR),
+  : InfoDesc(ID), SubRegIndexNames(subregindexnames),
     RegClassBegin(RCB), RegClassEnd(RCE) {
-  assert(isPhysicalRegister(NumRegs) &&
-         "Target has too many physical registers!");
-
   CallFrameSetupOpcode   = CFSO;
   CallFrameDestroyOpcode = CFDO;
 }
@@ -86,7 +83,7 @@
 
 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF,
                                           const TargetRegisterClass *RC) const {
-  BitVector Allocatable(NumRegs);
+  BitVector Allocatable(getNumRegs());
   if (RC) {
     getAllocatableSetForRC(MF, RC, Allocatable);
   } else {

Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/X86/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -1,8 +1,9 @@
 set(LLVM_TARGET_DEFINITIONS X86.td)
 
-tablegen(X86GenRegisterInfo.h.inc -gen-register-desc-header)
 tablegen(X86GenRegisterNames.inc -gen-register-enums)
-tablegen(X86GenRegisterInfo.inc -gen-register-desc)
+tablegen(X86GenRegisterDesc.inc -gen-register-desc)
+tablegen(X86GenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(X86GenRegisterInfo.inc -gen-register-info)
 tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
 tablegen(X86GenInstrNames.inc -gen-instr-enums)
 tablegen(X86GenInstrInfo.inc -gen-instr-desc)

Modified: llvm/trunk/lib/Target/X86/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Makefile (original)
+++ llvm/trunk/lib/Target/X86/Makefile Thu Jun 23 20:44:41 2011
@@ -12,14 +12,15 @@
 TARGET = X86
 
 # Make sure that tblgen is run, first thing.
-BUILT_SOURCES = X86GenRegisterInfo.h.inc X86GenRegisterNames.inc \
-                X86GenRegisterInfo.inc X86GenInstrNames.inc \
-                X86GenInstrInfo.inc X86GenAsmWriter.inc X86GenAsmMatcher.inc \
+BUILT_SOURCES = X86GenRegisterNames.inc X86GenRegisterDesc.inc \
+		X86GenRegisterInfo.h.inc X86GenRegisterInfo.inc \
+		X86GenInstrNames.inc X86GenInstrInfo.inc \
+		X86GenAsmWriter.inc X86GenAsmMatcher.inc \
                 X86GenAsmWriter1.inc X86GenDAGISel.inc  \
                 X86GenDisassemblerTables.inc X86GenFastISel.inc \
                 X86GenCallingConv.inc X86GenSubtarget.inc \
 		X86GenEDInfo.inc
 
-DIRS = InstPrinter AsmParser Disassembler TargetInfo Utils
+DIRS = InstPrinter AsmParser Disassembler TargetInfo TargetDesc Utils
 
 include $(LEVEL)/Makefile.common

Added: llvm/trunk/lib/Target/X86/TargetDesc/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/TargetDesc/Makefile?rev=133782&view=auto
==============================================================================
--- llvm/trunk/lib/Target/X86/TargetDesc/Makefile (added)
+++ llvm/trunk/lib/Target/X86/TargetDesc/Makefile Thu Jun 23 20:44:41 2011
@@ -0,0 +1,16 @@
+##===- lib/Target/X86/TargetDesc/Makefile ------------------*- Makefile -*-===##
+#
+#                     The LLVM Compiler Infrastructure
+#
+# This file is distributed under the University of Illinois Open Source
+# License. See LICENSE.TXT for details.
+#
+##===----------------------------------------------------------------------===##
+
+LEVEL = ../../../..
+LIBRARYNAME = LLVMX86Desc
+
+# Hack: we need to include 'main' target directory to grab private headers
+CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/..
+
+include $(LEVEL)/Makefile.common

Added: llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp?rev=133782&view=auto
==============================================================================
--- llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp (added)
+++ llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp Thu Jun 23 20:44:41 2011
@@ -0,0 +1,23 @@
+//===-- X86TargetDesc.cpp - X86 Target Descriptions -------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides X86 specific target descriptions.
+//
+//===----------------------------------------------------------------------===//
+
+#include "X86TargetDesc.h"
+#include "llvm/MC/MCRegisterInfo.h"
+#include "X86GenRegisterDesc.inc"
+using namespace llvm;
+
+MCRegisterInfo *createX86MCRegisterInfo() {
+  MCRegisterInfo *X = new MCRegisterInfo();
+  InitX86MCRegisterInfo(X);
+  return X;
+}

Added: llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h?rev=133782&view=auto
==============================================================================
--- llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h (added)
+++ llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h Thu Jun 23 20:44:41 2011
@@ -0,0 +1,17 @@
+//===-- X86TargetDesc.h - X86 Target Descriptions ---------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides X86 specific target descriptions.
+//
+//===----------------------------------------------------------------------===//
+
+// Defines symbolic names for X86 registers.  This defines a mapping from
+// register name to register number.
+//
+#include "X86GenRegisterNames.inc"

Modified: llvm/trunk/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.h (original)
+++ llvm/trunk/lib/Target/X86/X86.h Thu Jun 23 20:44:41 2011
@@ -88,10 +88,7 @@
 
 } // End llvm namespace
 
-// Defines symbolic names for X86 registers.  This defines a mapping from
-// register name to register number.
-//
-#include "X86GenRegisterNames.inc"
+#include "TargetDesc/X86TargetDesc.h"
 
 // Defines symbolic names for the X86 instructions.
 //

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -39,6 +39,8 @@
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/CommandLine.h"
+#include "X86GenRegisterDesc.inc"
+#include "X86GenRegisterInfo.inc"
 using namespace llvm;
 
 cl::opt<bool>
@@ -49,7 +51,8 @@
 
 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
                                  const TargetInstrInfo &tii)
-  : X86GenRegisterInfo(tm.getSubtarget<X86Subtarget>().is64Bit() ?
+  : X86GenRegisterInfo(X86RegDesc, X86RegInfoDesc,
+                       tm.getSubtarget<X86Subtarget>().is64Bit() ?
                          X86::ADJCALLSTACKDOWN64 :
                          X86::ADJCALLSTACKDOWN32,
                        tm.getSubtarget<X86Subtarget>().is64Bit() ?
@@ -918,8 +921,6 @@
 }
 }
 
-#include "X86GenRegisterInfo.inc"
-
 namespace {
   struct MSAH : public MachineFunctionPass {
     static char ID;

Modified: llvm/trunk/lib/Target/XCore/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/CMakeLists.txt?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/XCore/CMakeLists.txt Thu Jun 23 20:44:41 2011
@@ -1,8 +1,8 @@
 set(LLVM_TARGET_DEFINITIONS XCore.td)
 
-tablegen(XCoreGenRegisterInfo.h.inc -gen-register-desc-header)
-tablegen(XCoreGenRegisterNames.inc -gen-register-enums)
-tablegen(XCoreGenRegisterInfo.inc -gen-register-desc)
+tablegen(XCoreGenRegisterDesc.inc -gen-register-desc)
+tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
 tablegen(XCoreGenInstrNames.inc -gen-instr-enums)
 tablegen(XCoreGenInstrInfo.inc -gen-instr-desc)
 tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)

Modified: llvm/trunk/lib/Target/XCore/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/Makefile?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/Makefile (original)
+++ llvm/trunk/lib/Target/XCore/Makefile Thu Jun 23 20:44:41 2011
@@ -13,7 +13,8 @@
 
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \
-                XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \
+                XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \
+		XCoreGenInstrNames.inc \
                 XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \
                 XCoreGenDAGISel.inc XCoreGenCallingConv.inc \
 		XCoreGenSubtarget.inc

Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Thu Jun 23 20:44:41 2011
@@ -32,11 +32,13 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/raw_ostream.h"
-
+#include "XCoreGenRegisterDesc.inc"
+#include "XCoreGenRegisterInfo.inc"
 using namespace llvm;
 
 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
-  : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
+  : XCoreGenRegisterInfo(XCoreRegDesc, XCoreRegInfoDesc,
+                         XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
     TII(tii) {
 }
 
@@ -328,6 +330,3 @@
 unsigned XCoreRegisterInfo::getRARegister() const {
   return XCore::LR;
 }
-
-#include "XCoreGenRegisterInfo.inc"
-

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Thu Jun 23 20:44:41 2011
@@ -79,7 +79,8 @@
 
   OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
      << "  explicit " << ClassName
-     << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
+     << "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
+     << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
      << "  virtual int getDwarfRegNumFull(unsigned RegNum, "
      << "unsigned Flavour) const;\n"
      << "  virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
@@ -140,8 +141,6 @@
   CodeGenTarget Target(Records);
   CodeGenRegBank &RegBank = Target.getRegBank();
   RegBank.computeDerivedInfo();
-  std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
-  RegBank.computeOverlaps(Overlaps);
 
   EmitSourceFileHeader("Register Information Source Fragment", OS);
 
@@ -407,78 +406,22 @@
        << "RegClass,\n";
   OS << "  };\n";
 
-  typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
-  DwarfRegNumsMapTy DwarfRegNums;
-  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
-
-  // Emit an overlap list for all registers.
-  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
-    const CodeGenRegister *Reg = Regs[i];
-    const CodeGenRegister::Set &O = Overlaps[Reg];
-    // Move Reg to the front so TRI::getAliasSet can share the list.
-    OS << "  const unsigned " << Reg->getName() << "_Overlaps[] = { "
-       << getQualifiedName(Reg->TheDef) << ", ";
-    for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
-         I != E; ++I)
-      if (*I != Reg)
-        OS << getQualifiedName((*I)->TheDef) << ", ";
-    OS << "0 };\n";
-  }
-
-  // Emit the empty sub-registers list
-  OS << "  const unsigned Empty_SubRegsSet[] = { 0 };\n";
-  // Loop over all of the registers which have sub-registers, emitting the
-  // sub-registers list to memory.
-  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
-    const CodeGenRegister &Reg = *Regs[i];
-    if (Reg.getSubRegs().empty())
-     continue;
-    // getSubRegs() orders by SubRegIndex. We want a topological order.
-    SetVector<CodeGenRegister*> SR;
-    Reg.addSubRegsPreOrder(SR);
-    OS << "  const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
-    for (unsigned j = 0, je = SR.size(); j != je; ++j)
-      OS << getQualifiedName(SR[j]->TheDef) << ", ";
-    OS << "0 };\n";
-  }
-
-  // Emit the empty super-registers list
-  OS << "  const unsigned Empty_SuperRegsSet[] = { 0 };\n";
-  // Loop over all of the registers which have super-registers, emitting the
-  // super-registers list to memory.
-  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
-    const CodeGenRegister &Reg = *Regs[i];
-    const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
-    if (SR.empty())
-      continue;
-    OS << "  const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
-    for (unsigned j = 0, je = SR.size(); j != je; ++j)
-      OS << getQualifiedName(SR[j]->TheDef) << ", ";
-    OS << "0 };\n";
-  }
-
-  OS<<"\n  const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
-  OS << "    { \"NOREG\",\t0,\t0,\t0,\t0,\t0 },\n";
+  // Emit extra information about registers.
+  OS << "\n  static const TargetRegisterInfoDesc "
+     << Target.getName() << "RegInfoDesc[] = "
+     << "{ // Extra Descriptors\n";
+  OS << "    { 0, 0 },\n";
 
-  // Now that register alias and sub-registers sets have been emitted, emit the
-  // register descriptors now.
+  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
   for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
     const CodeGenRegister &Reg = *Regs[i];
-    OS << "    { \"";
-    OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
-    if (!Reg.getSubRegs().empty())
-      OS << Reg.getName() << "_SubRegsSet,\t";
-    else
-      OS << "Empty_SubRegsSet,\t";
-    if (!Reg.getSuperRegs().empty())
-      OS << Reg.getName() << "_SuperRegsSet,\t";
-    else
-      OS << "Empty_SuperRegsSet,\t";
-    OS << Reg.CostPerUse << ",\t"
+    OS << "    { ";
+    OS << Reg.CostPerUse << ", "
        << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
   }
   OS << "  };\n";      // End of register descriptors...
 
+
   // Calculate the mapping of subregister+index pairs to physical registers.
   // This will also create further anonymous indexes.
   unsigned NamedIndices = RegBank.getNumNamedIndices();
@@ -575,14 +518,18 @@
 
   // Emit the constructor of the class...
   OS << ClassName << "::" << ClassName
-     << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
-     << "  : TargetRegisterInfo(RegisterDescriptors, " << Regs.size()+1
+     << "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
+     << "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
+     << "  : TargetRegisterInfo(ID"
      << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
      << "                 SubRegIndexTable,\n"
      << "                 CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n"
+     << "  InitMCRegisterInfo(D, " << Regs.size()+1 << ");\n"
      << "}\n\n";
 
   // Collect all information about dwarf register numbers
+  typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
+  DwarfRegNumsMapTy DwarfRegNums;
 
   // First, just pull all provided information to the map
   unsigned maxLength = 0;
@@ -671,3 +618,101 @@
 
   OS << "} // End llvm namespace \n";
 }
+
+void RegisterInfoEmitter::runDesc(raw_ostream &OS) {
+  CodeGenTarget Target(Records);
+  CodeGenRegBank &RegBank = Target.getRegBank();
+  RegBank.computeDerivedInfo();
+  std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
+  RegBank.computeOverlaps(Overlaps);
+
+  OS << "namespace llvm {\n\n";
+
+  const std::string &TargetName = Target.getName();
+  std::string ClassName = TargetName + "GenMCRegisterInfo";
+  OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
+     << "  explicit " << ClassName << "(const TargetRegisterDesc *D);\n";
+  OS << "};\n";
+
+  OS << "\nnamespace {\n";
+
+  const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
+
+  // Emit an overlap list for all registers.
+  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+    const CodeGenRegister *Reg = Regs[i];
+    const CodeGenRegister::Set &O = Overlaps[Reg];
+    // Move Reg to the front so TRI::getAliasSet can share the list.
+    OS << "  const unsigned " << Reg->getName() << "_Overlaps[] = { "
+       << getQualifiedName(Reg->TheDef) << ", ";
+    for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
+         I != E; ++I)
+      if (*I != Reg)
+        OS << getQualifiedName((*I)->TheDef) << ", ";
+    OS << "0 };\n";
+  }
+
+  // Emit the empty sub-registers list
+  OS << "  const unsigned Empty_SubRegsSet[] = { 0 };\n";
+  // Loop over all of the registers which have sub-registers, emitting the
+  // sub-registers list to memory.
+  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+    const CodeGenRegister &Reg = *Regs[i];
+    if (Reg.getSubRegs().empty())
+     continue;
+    // getSubRegs() orders by SubRegIndex. We want a topological order.
+    SetVector<CodeGenRegister*> SR;
+    Reg.addSubRegsPreOrder(SR);
+    OS << "  const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
+    for (unsigned j = 0, je = SR.size(); j != je; ++j)
+      OS << getQualifiedName(SR[j]->TheDef) << ", ";
+    OS << "0 };\n";
+  }
+
+  // Emit the empty super-registers list
+  OS << "  const unsigned Empty_SuperRegsSet[] = { 0 };\n";
+  // Loop over all of the registers which have super-registers, emitting the
+  // super-registers list to memory.
+  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+    const CodeGenRegister &Reg = *Regs[i];
+    const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
+    if (SR.empty())
+      continue;
+    OS << "  const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
+    for (unsigned j = 0, je = SR.size(); j != je; ++j)
+      OS << getQualifiedName(SR[j]->TheDef) << ", ";
+    OS << "0 };\n";
+  }
+
+  OS << "\n  const TargetRegisterDesc " << TargetName
+     << "RegDesc[] = { // Descriptors\n";
+  OS << "    { \"NOREG\",\t0,\t0,\t0 },\n";
+
+  // Now that register alias and sub-registers sets have been emitted, emit the
+  // register descriptors now.
+  for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+    const CodeGenRegister &Reg = *Regs[i];
+    OS << "    { \"";
+    OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
+    if (!Reg.getSubRegs().empty())
+      OS << Reg.getName() << "_SubRegsSet,\t";
+    else
+      OS << "Empty_SubRegsSet,\t";
+    if (!Reg.getSuperRegs().empty())
+      OS << Reg.getName() << "_SuperRegsSet";
+    else
+      OS << "Empty_SuperRegsSet";
+    OS << " },\n";
+  }
+  OS << "  };\n";      // End of register descriptors...
+
+  OS << "}\n\n";       // End of anonymous namespace...
+
+  // MCRegisterInfo initialization routine.
+  OS << "void " << "Init" << TargetName
+     << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
+  OS << "  RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
+     << Regs.size()+1 << ");\n}\n\n";
+
+  OS << "} // End llvm namespace \n";
+}

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.h?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.h (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.h Thu Jun 23 20:44:41 2011
@@ -33,6 +33,9 @@
 
   // runEnums - Print out enum values for all of the registers.
   void runEnums(raw_ostream &o);
+
+  // runDesc - Print out register descriptions.
+  void runDesc(raw_ostream &o);
 };
 
 } // End llvm namespace

Modified: llvm/trunk/utils/TableGen/TableGen.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=133782&r1=133781&r2=133782&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/TableGen.cpp (original)
+++ llvm/trunk/utils/TableGen/TableGen.cpp Thu Jun 23 20:44:41 2011
@@ -54,7 +54,7 @@
 enum ActionType {
   PrintRecords,
   GenEmitter,
-  GenRegisterEnums, GenRegister, GenRegisterHeader,
+  GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader,
   GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher,
   GenARMDecoder,
   GenDisassembler,
@@ -95,10 +95,12 @@
                                "Generate machine code emitter"),
                     clEnumValN(GenRegisterEnums, "gen-register-enums",
                                "Generate enum values for registers"),
-                    clEnumValN(GenRegister, "gen-register-desc",
-                               "Generate a register info description"),
-                    clEnumValN(GenRegisterHeader, "gen-register-desc-header",
-                               "Generate a register info description header"),
+                    clEnumValN(GenRegisterDesc, "gen-register-desc",
+                               "Generate register descriptions"),
+                    clEnumValN(GenRegisterInfo, "gen-register-info",
+                               "Generate registers & reg-classes info"),
+                    clEnumValN(GenRegisterInfoHeader, "gen-register-info-header",
+                               "Generate registers & reg-classes info header"),
                     clEnumValN(GenInstrEnums, "gen-instr-enums",
                                "Generate enum values for instructions"),
                     clEnumValN(GenInstrs, "gen-instr-desc",
@@ -261,14 +263,16 @@
     case GenEmitter:
       CodeEmitterGen(Records).run(Out.os());
       break;
-
     case GenRegisterEnums:
       RegisterInfoEmitter(Records).runEnums(Out.os());
       break;
-    case GenRegister:
+    case GenRegisterDesc:
+      RegisterInfoEmitter(Records).runDesc(Out.os());
+      break;
+    case GenRegisterInfo:
       RegisterInfoEmitter(Records).run(Out.os());
       break;
-    case GenRegisterHeader:
+    case GenRegisterInfoHeader:
       RegisterInfoEmitter(Records).runHeader(Out.os());
       break;
     case GenInstrEnums:



From aggarwa4 at illinois.edu  Thu Jun 23 20:53:30 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Fri, 24 Jun 2011 01:53:30 -0000
Subject: [llvm-commits] [poolalloc] r133783 - in /poolalloc/trunk:
 include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp
Message-ID: <20110624015330.739952A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Jun 23 20:53:30 2011
New Revision: 133783

URL: http://llvm.org/viewvc/llvm-project?rev=133783&view=rev
Log:
Some refactoring.
Visit basic blocks in dominator tree order, when trying
to delete checks.

Modified:
    poolalloc/trunk/include/assistDS/TypeChecks.h
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp

Modified: poolalloc/trunk/include/assistDS/TypeChecks.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=133783&r1=133782&r2=133783&view=diff
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecks.h (original)
+++ poolalloc/trunk/include/assistDS/TypeChecks.h Thu Jun 23 20:53:30 2011
@@ -55,6 +55,7 @@
   bool initShadow(Module &M);
   void addTypeMap(Module &M) ;
   void optimizeChecks(Module &M);
+  void initRuntimeCheckPrototypes(Module &M);
   
   bool visitMain(Module &M, Function &F); 
 

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133783&r1=133782&r2=133783&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 23 20:53:30 2011
@@ -26,6 +26,7 @@
 
 #include <set>
 #include <vector>
+#include <deque>
 
 using namespace llvm;
 
@@ -66,6 +67,7 @@
 
 static Constant *One = 0;
 static Constant *Zero = 0;
+
 static Constant *RegisterArgv;
 static Constant *RegisterEnvp;
 
@@ -96,6 +98,7 @@
   if(UsedTypes.find(Ty) == UsedTypes.end())
     UsedTypes[Ty] = UsedTypes.size();
 
+  assert((UsedTypes.size() < 254) && "Too many types found. Not enough metadata bits");
   return UsedTypes[Ty];
 }
 
@@ -142,102 +145,8 @@
   One = ConstantInt::get(Int64Ty, 1);
   Zero = ConstantInt::get(Int64Ty, 0);
 
-  RegisterArgv = M.getOrInsertFunction("trackArgvType",
-                                       VoidTy,
-                                       Int32Ty, /*argc */
-                                       VoidPtrTy->getPointerTo(),/*argv*/
-                                       NULL);
-  RegisterEnvp = M.getOrInsertFunction("trackEnvpType",
-                                       VoidTy,
-                                       VoidPtrTy->getPointerTo(),/*envp*/
-                                       NULL);
-  trackGlobal = M.getOrInsertFunction("trackGlobal",
-                                      VoidTy,
-                                      VoidPtrTy,/*ptr*/
-                                      TypeTagTy,/*type*/
-                                      Int64Ty,/*size*/
-                                      Int32Ty,/*tag*/
-                                      NULL);
-  trackArray = M.getOrInsertFunction("trackArray",
-                                     VoidTy,
-                                     VoidPtrTy,/*ptr*/
-                                     Int64Ty,/*size*/
-                                     Int64Ty,/*count*/
-                                     Int32Ty,/*tag*/
-                                     NULL);
-  trackInitInst = M.getOrInsertFunction("trackInitInst",
-                                        VoidTy,
-                                        VoidPtrTy,/*ptr*/
-                                        Int64Ty,/*size*/
-                                        Int32Ty,/*tag*/
-                                        NULL);
-  trackUnInitInst = M.getOrInsertFunction("trackUnInitInst",
-                                          VoidTy,
-                                          VoidPtrTy,/*ptr*/
-                                          Int64Ty,/*size*/
-                                          Int32Ty,/*tag*/
-                                          NULL);
-  trackStoreInst = M.getOrInsertFunction("trackStoreInst",
-                                         VoidTy,
-                                         VoidPtrTy,/*ptr*/
-                                         TypeTagTy,/*type*/
-                                         Int64Ty,/*size*/
-                                         Int32Ty,/*tag*/
-                                         NULL);
-  getTypeTag = M.getOrInsertFunction("getTypeTag",
-                                     VoidTy,
-                                     VoidPtrTy, /*ptr*/
-                                     Int64Ty, /*size*/
-                                     TypeTagPtrTy, /*dest for type tag*/
-                                     Int32Ty, /*tag*/
-                                     NULL);
-  checkTypeInst = M.getOrInsertFunction("checkType",
-                                        VoidTy,
-                                        TypeTagTy,/*type*/
-                                        Int64Ty,/*size*/
-                                        TypeTagPtrTy,/*ptr to metadata*/
-                                        VoidPtrTy,/*ptr*/
-                                        Int32Ty,/*tag*/
-                                        NULL);
-  setTypeInfo = M.getOrInsertFunction("setTypeInfo",
-                                       VoidTy,
-                                       VoidPtrTy,/*dest ptr*/
-                                       TypeTagPtrTy,/*metadata*/
-                                       Int64Ty,/*size*/
-                                       Int32Ty,/*tag*/
-                                       NULL);
-  copyTypeInfo = M.getOrInsertFunction("copyTypeInfo",
-                                       VoidTy,
-                                       VoidPtrTy,/*dest ptr*/
-                                       VoidPtrTy,/*src ptr*/
-                                       Int64Ty,/*size*/
-                                       Int32Ty,/*tag*/
-                                       NULL);
-  trackStringInput = M.getOrInsertFunction("trackStringInput",
-                                           VoidTy,
-                                           VoidPtrTy,
-                                           Int32Ty,
-                                           NULL);
-  setVAInfo = M.getOrInsertFunction("setVAInfo",
-                                    VoidTy,
-                                    VoidPtrTy,/*va_list ptr*/
-                                    Int64Ty,/*total num of elements in va_list */
-                                    TypeTagPtrTy,/*ptr to metadta*/
-                                    Int32Ty,/*tag*/
-                                    NULL);
-  copyVAInfo = M.getOrInsertFunction("copyVAInfo",
-                                     VoidTy,
-                                     VoidPtrTy,/*dst va_list*/
-                                     VoidPtrTy,/*src va_list */
-                                     Int32Ty,/*tag*/
-                                     NULL);
-  checkVAArg = M.getOrInsertFunction("checkVAArgType",
-                                     VoidTy,
-                                     VoidPtrTy,/*va_list ptr*/
-                                     TypeTagTy,/*type*/
-                                     Int32Ty,/*tag*/
-                                     NULL);
-
+  // Add prototypes for the dynamic type checking functions
+  initRuntimeCheckPrototypes(M);
 
   UsedTypes.clear(); // Reset if run multiple times.
   VAArgFunctions.clear();
@@ -254,7 +163,7 @@
   // Insert the shadow initialization function.
   modified |= initShadow(M);
 
-  // Record argv
+  // Record argv/envp
   modified |= visitMain(M, *MainF);
 
   // Recognize special cases
@@ -298,6 +207,7 @@
     modified |= visitByValFunction(M, *F);
   }
 
+  // Modify all the var arg functions
   while(!VAArgFunctions.empty()) {
     Function *F = VAArgFunctions.back();
     VAArgFunctions.pop_back();
@@ -305,6 +215,7 @@
     modified |= visitVarArgFunction(M, *F);
   }
 
+  // Modify all the address taken functions
   while(!AddressTakenFunctions.empty()) {
     Function *F = AddressTakenFunctions.back();
     AddressTakenFunctions.pop_back();
@@ -318,8 +229,8 @@
     if(F.isDeclaration())
       continue;
 
-    // Loop over all of the instructions in the function, 
-    // adding their return type as well as the types of their operands.
+    // Loop over all of the instructions in the function,
+    // adding instrumentation where needed.
     for (inst_iterator II = inst_begin(F), IE = inst_end(F); II != IE;++II) {
       Instruction &I = *II;
       if (StoreInst *SI = dyn_cast<StoreInst>(&I)) {
@@ -339,7 +250,6 @@
     }
   }
 
-  // visit all the uses of the address taken functions and modify if
   // visit all the indirect call sites
   std::set<Instruction*>::iterator II = IndCalls.begin();
   for(; II != IndCalls.end();) {
@@ -347,6 +257,8 @@
     modified |= visitIndirectCallSite(M,I);
   }
 
+  // visit all the uses of the address taken functions and modify if
+  // not being passed to external code
   std::map<Function *, Function * >::iterator FI = IndFunctionsMap.begin(), FE = IndFunctionsMap.end();
   for(;FI!=FE;++FI) {
     Function *F = FI->first;
@@ -404,6 +316,8 @@
     }
   }
 
+  // remove redundant checks, caused due to insturmenting uses of loads
+  // Remove a check if it is dominated by another check for the same instruction
   optimizeChecks(M);
 
   // add a global that contains the mapping from metadata to strings
@@ -415,7 +329,118 @@
   return modified;
 }
 
+void TypeChecks::initRuntimeCheckPrototypes(Module &M) {
+  
+  RegisterArgv = M.getOrInsertFunction("trackArgvType",
+                                       VoidTy,
+                                       Int32Ty, /*argc */
+                                       VoidPtrTy->getPointerTo(),/*argv*/
+                                       NULL);
+
+  RegisterEnvp = M.getOrInsertFunction("trackEnvpType",
+                                       VoidTy,
+                                       VoidPtrTy->getPointerTo(),/*envp*/
+                                       NULL);
+  
+  trackGlobal = M.getOrInsertFunction("trackGlobal",
+                                      VoidTy,
+                                      VoidPtrTy,/*ptr*/
+                                      TypeTagTy,/*type*/
+                                      Int64Ty,/*size*/
+                                      Int32Ty,/*tag*/
+                                      NULL);
+
+  trackArray = M.getOrInsertFunction("trackArray",
+                                     VoidTy,
+                                     VoidPtrTy,/*ptr*/
+                                     Int64Ty,/*size*/
+                                     Int64Ty,/*count*/
+                                     Int32Ty,/*tag*/
+                                     NULL);
+  
+  trackInitInst = M.getOrInsertFunction("trackInitInst",
+                                        VoidTy,
+                                        VoidPtrTy,/*ptr*/
+                                        Int64Ty,/*size*/
+                                        Int32Ty,/*tag*/
+                                        NULL);
+
+  trackUnInitInst = M.getOrInsertFunction("trackUnInitInst",
+                                          VoidTy,
+                                          VoidPtrTy,/*ptr*/
+                                          Int64Ty,/*size*/
+                                          Int32Ty,/*tag*/
+                                          NULL);
+
+  trackStoreInst = M.getOrInsertFunction("trackStoreInst",
+                                         VoidTy,
+                                         VoidPtrTy,/*ptr*/
+                                         TypeTagTy,/*type*/
+                                         Int64Ty,/*size*/
+                                         Int32Ty,/*tag*/
+                                         NULL);
+  getTypeTag = M.getOrInsertFunction("getTypeTag",
+                                     VoidTy,
+                                     VoidPtrTy, /*ptr*/
+                                     Int64Ty, /*size*/
+                                     TypeTagPtrTy, /*dest for type tag*/
+                                     Int32Ty, /*tag*/
+                                     NULL);
+  checkTypeInst = M.getOrInsertFunction("checkType",
+                                        VoidTy,
+                                        TypeTagTy,/*type*/
+                                        Int64Ty,/*size*/
+                                        TypeTagPtrTy,/*ptr to metadata*/
+                                        VoidPtrTy,/*ptr*/
+                                        Int32Ty,/*tag*/
+                                        NULL);
+  setTypeInfo = M.getOrInsertFunction("setTypeInfo",
+                                       VoidTy,
+                                       VoidPtrTy,/*dest ptr*/
+                                       TypeTagPtrTy,/*metadata*/
+                                       Int64Ty,/*size*/
+                                       Int32Ty,/*tag*/
+                                       NULL);
+  copyTypeInfo = M.getOrInsertFunction("copyTypeInfo",
+                                       VoidTy,
+                                       VoidPtrTy,/*dest ptr*/
+                                       VoidPtrTy,/*src ptr*/
+                                       Int64Ty,/*size*/
+                                       Int32Ty,/*tag*/
+                                       NULL);
+  trackStringInput = M.getOrInsertFunction("trackStringInput",
+                                           VoidTy,
+                                           VoidPtrTy,
+                                           Int32Ty,
+                                           NULL);
+  setVAInfo = M.getOrInsertFunction("setVAInfo",
+                                    VoidTy,
+                                    VoidPtrTy,/*va_list ptr*/
+                                    Int64Ty,/*total num of elements in va_list */
+                                    TypeTagPtrTy,/*ptr to metadta*/
+                                    Int32Ty,/*tag*/
+                                    NULL);
+  copyVAInfo = M.getOrInsertFunction("copyVAInfo",
+                                     VoidTy,
+                                     VoidPtrTy,/*dst va_list*/
+                                     VoidPtrTy,/*src va_list */
+                                     Int32Ty,/*tag*/
+                                     NULL);
+  checkVAArg = M.getOrInsertFunction("checkVAArgType",
+                                     VoidTy,
+                                     VoidPtrTy,/*va_list ptr*/
+                                     TypeTagTy,/*type*/
+                                     Int32Ty,/*tag*/
+                                     NULL);
+
+}
+
+// Delete checks, if it is dominated by another check for the same value.
+// We might get multiple checks on a path, if there are multiple uses of
+// a load inst.
+/*
 void TypeChecks::optimizeChecks(Module &M) {
+  // TODO: visit in dominator tree order
   for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) {
     Function &F = *MI;
     if(F.isDeclaration())
@@ -435,13 +460,15 @@
             continue;
           if(CI2->getParent()->getParent() != &F)
             continue;
+          // Check that they are refering to the same pointer
           if(CI->getOperand(4) != CI2->getOperand(4))
             continue;
+          // Check that they are using the same metadata for comparison.
           if(CI->getOperand(3) != CI2->getOperand(3))
             continue;
+          // if CI, dominates CI2, delete CI2
           if(!DT.dominates(CI, CI2))
             continue;
-          CI->dump();
           CI2->dump();
           toDelete.push_back(CI2);
         }
@@ -453,7 +480,53 @@
       }
     }
   }
+}*/
 
+void TypeChecks::optimizeChecks(Module &M) {
+  for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) {
+    Function &F = *MI;
+    if(F.isDeclaration())
+      continue;
+    DominatorTree & DT = getAnalysis<DominatorTree>(F);
+    std::deque<DomTreeNode *> Worklist;
+    Worklist.push_back (DT.getRootNode());
+    while(Worklist.size()) {
+      DomTreeNode * Node = Worklist.front();
+      Worklist.pop_front();
+      BasicBlock *BB = Node->getBlock();
+      for (BasicBlock::iterator bi = BB->begin(); bi != BB->end(); ++bi) {
+        CallInst *CI = dyn_cast<CallInst>(bi);
+        if(!CI)
+          continue;
+        if(CI->getCalledFunction() != checkTypeInst)
+          continue;
+        std::list<Instruction *>toDelete;
+        for(Value::use_iterator User = checkTypeInst->use_begin(); User != checkTypeInst->use_end(); ++User) {
+          CallInst *CI2 = dyn_cast<CallInst>(User);
+          if(CI2 == CI)
+            continue;
+          if(CI2->getParent()->getParent() != &F)
+            continue;
+          // Check that they are refering to the same pointer
+          if(CI->getOperand(4) != CI2->getOperand(4))
+            continue;
+          // Check that they are using the same metadata for comparison.
+          if(CI->getOperand(3) != CI2->getOperand(3))
+            continue;
+          // if CI, dominates CI2, delete CI2
+          if(!DT.dominates(CI, CI2))
+            continue;
+          toDelete.push_back(CI2);
+        }
+        while(!toDelete.empty()) {
+          Instruction *I = toDelete.back();
+          toDelete.pop_back();
+          I->eraseFromParent();
+        }
+      }
+      Worklist.insert(Worklist.end(), Node->begin(), Node->end());
+    }
+  }
 }
 
 // add a global that has the metadata -> typeString mapping
@@ -516,6 +589,9 @@
                     );
 }
 
+// For each address taken function, create a clone
+// that takes 2 extra arguments(same as a var arg function).
+// Modify call sites.
 bool TypeChecks::visitAddressTakenFunction(Module &M, Function &F) {
   // Clone function
   // 1. Create the new argument types vector
@@ -560,11 +636,16 @@
   // 5. Perform the cloning
   SmallVector<ReturnInst*, 100>Returns;
   CloneFunctionInto(NewF, &F, ValueMap, Returns);
+  // Store in the map of original -> cloned function
   IndFunctionsMap[&F] = NewF;
 
   // Find all uses of the function
   for(Value::use_iterator ui = F.use_begin(), ue = F.use_end();
       ui != ue;)  {
+    if(isa<InvokeInst>(ui)) {
+      ui->dump();
+      assert(0 && "Handle invoke inst here");
+    }
     // Check for call sites
     CallInst *CI = dyn_cast<CallInst>(ui++);
     if(!CI)
@@ -1067,6 +1148,7 @@
   for (; I != E; ++I) {
     OS << "  ";
     WriteTypeSymbolic(OS, I->first, M);
+    OS << " : " << I->second;
     OS << '\n';
   }
 
@@ -1681,6 +1763,7 @@
   return false;
 }
 
+// Add extra arguments to each indirect call site
 bool TypeChecks::visitIndirectCallSite(Module &M, Instruction *I) {
   // add the number of arguments as the first argument
   const Type* OrigType = I->getOperand(0)->getType();
@@ -1759,10 +1842,7 @@
     I->eraseFromParent();
 
   }
-
-
-  // add they types of the argument as the second argument
-  return false;
+  return true;
 }
 
 bool TypeChecks::visitInputFunctionValue(Module &M, Value *V, Instruction *CI) {
@@ -1829,8 +1909,10 @@
   numLoadChecks++;
   return true;
 }
+
 // AI - metadata
 // BCI - ptr
+// I - instruction whose uses to instrument
 bool TypeChecks::visitUses(Instruction *I, AllocaInst *AI, CastInst *BCI) {
   for(Value::use_iterator II = I->use_begin(); II != I->use_end(); ++II) {
     if(DisablePtrCmpChecks) {
@@ -1869,6 +1951,7 @@
   }
   return true;
 }
+
 // Insert runtime checks before all store instructions.
 bool TypeChecks::visitStoreInst(Module &M, StoreInst &SI) {
   // Cast the pointer operand to i8* for the runtime function.



From scshunt at csclub.uwaterloo.ca  Thu Jun 23 21:21:44 2011
From: scshunt at csclub.uwaterloo.ca (Sean Hunt)
Date: Thu, 23 Jun 2011 19:21:44 -0700
Subject: [llvm-commits] [llvm] r133782 - in /llvm/trunk: ./
 include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/Target/
 lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/
 lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/
 lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/
 lib/Target/X86/TargetDesc/ lib/Target/XCore/ utils/TableGen/
In-Reply-To: <20110624014442.9ECEB2A6C12C@llvm.org>
References: <20110624014442.9ECEB2A6C12C@llvm.org>
Message-ID: <4E03F4B8.90805@csclub.uwaterloo.ca>

On 06/23/11 18:44, Evan Cheng wrote:
> Author: evancheng
> Date: Thu Jun 23 20:44:41 2011
> New Revision: 133782
>
> URL: http://llvm.org/viewvc/llvm-project?rev=133782&view=rev
> Log:
> Starting to refactor Target to separate out code that's needed to fully describe
> target machine from those that are only needed by codegen. The goal is to
> sink the essential target description into MC layer so we can start building
> MC based tools without needing to link in the entire codegen.
>
> First step is to refactor TargetRegisterInfo. This patch added a base class
> MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
> separate register description from the rest of the stuff.

Can you please update lib/Target/CellSPU/CMakeLists.txt?

Thanks,
Sean

From evan.cheng at apple.com  Fri Jun 24 00:04:49 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Jun 2011 05:04:49 -0000
Subject: [llvm-commits] [llvm] r133787 -
	/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt
Message-ID: <20110624050449.184482A6C12C@llvm.org>

Author: evancheng
Date: Fri Jun 24 00:04:48 2011
New Revision: 133787

URL: http://llvm.org/viewvc/llvm-project?rev=133787&view=rev
Log:
Fix CellSPU CMakeLists.txt

Modified:
    llvm/trunk/lib/Target/CellSPU/CMakeLists.txt

Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt?rev=133787&r1=133786&r2=133787&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/CellSPU/CMakeLists.txt Fri Jun 24 00:04:48 2011
@@ -4,8 +4,9 @@
 tablegen(SPUGenRegisterNames.inc -gen-register-enums)
 tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
 tablegen(SPUGenCodeEmitter.inc -gen-emitter)
-tablegen(SPUGenRegisterInfo.h.inc -gen-register-desc-header)
-tablegen(SPUGenRegisterInfo.inc -gen-register-desc)
+tablegen(SPUGenRegisterDesc.inc -gen-register-info)
+tablegen(SPUGenRegisterInfo.h.inc -gen-register-info-header)
+tablegen(SPUGenRegisterInfo.inc -gen-register-info)
 tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
 tablegen(SPUGenDAGISel.inc -gen-dag-isel)
 tablegen(SPUGenSubtarget.inc -gen-subtarget)



From atrick at apple.com  Fri Jun 24 00:24:32 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 23 Jun 2011 22:24:32 -0700
Subject: [llvm-commits] [llvm] r133776 - in /llvm/trunk:
 include/llvm/Analysis/BlockFrequencyImpl.h
 include/llvm/Analysis/BranchProbabilityInfo.h
 lib/Analysis/BranchProbabilityInfo.cpp
In-Reply-To: <20110623235211.A5CA82A6C12C@llvm.org>
References: <20110623235211.A5CA82A6C12C@llvm.org>
Message-ID: <6A7ABB0D-FBB1-440C-8257-586286D2C6E0@apple.com>

This is now identical to the original implementation whenever the frequency of the current loop header is START_FREQ (which it is always supposed to be). i.e. you have
Res = (N * START_FREQ) / D = (EdgeFreq(src, dst) * START_FREQ) / START_FREQ.

So it seems to be doing unnecessary computation and complicating the code for no benefit.

If the current loop head is not START_FREQ, then you have a bug somewhere else. It's better to leave the assert in place until you know what the problem is.

You also made this change, which may have fixed the original problem:
> uint32_t Numerator = START_FREQ - CProb ? START_FREQ - CProb : 1;

To me that implies a loop with zero probability of exiting. If so, please comment.

-Andy

On Jun 23, 2011, at 4:52 PM, Jakub Staszak wrote:

> Author: kuba
> Date: Thu Jun 23 18:52:11 2011
> New Revision: 133776
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133776&view=rev
> Log:
> Calculate backedge probability correctly.
> 
> Modified:
>    llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h
>    llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
>    llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
> 
> Modified: llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h?rev=133776&r1=133775&r2=133776&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h (original)
> +++ llvm/trunk/include/llvm/Analysis/BlockFrequencyImpl.h Thu Jun 23 18:52:11 2011
> @@ -133,6 +133,15 @@
>   }
> 
> 
> +  /// Return a probability of getting to the DST block through SRC->DST edge.
> +  ///
> +  BranchProbability getBackEdgeProbability(BlockT *Src, BlockT *Dst) const {
> +    uint32_t N = getEdgeFreq(Src, Dst);
> +    uint32_t D = getBlockFreq(Dst);
> +
> +    return BranchProbability(N, D);
> +  }
> +
>   /// isReachable - Returns if BB block is reachable from the entry.
>   ///
>   bool isReachable(BlockT *BB) {
> @@ -213,7 +222,9 @@
>       return;
> 
>     assert(START_FREQ >= CycleProb[BB]);
> -    divBlockFreq(BB, BranchProbability(START_FREQ - CycleProb[BB], START_FREQ));
> +    uint32_t CProb = CycleProb[BB];
> +    uint32_t Numerator = START_FREQ - CProb ? START_FREQ - CProb : 1;
> +    divBlockFreq(BB, BranchProbability(Numerator, START_FREQ));
>   }
> 
>   /// doLoop - Propagate block frequency down throught the loop.
> @@ -238,19 +249,17 @@
>       BlockT *Pred = *PI;
>       assert(Pred);
>       if (isReachable(Pred) && isBackedge(Pred, Head)) {
> -        BranchProbability Prob = BPI->getBackEdgeProbability(Pred, Head);
> +        BranchProbability Prob = getBackEdgeProbability(Pred, Head);
>         uint64_t N = Prob.getNumerator();
>         uint64_t D = Prob.getDenominator();
>         uint64_t Res = (N * START_FREQ) / D;
> 
> -        // CycleProb[Head] += getEdgeFreq(Pred, Head);
>         assert(Res <= UINT32_MAX);
>         CycleProb[Head] += (uint32_t) Res;
>       }
>     }
>   }
> 
> -
>   friend class BlockFrequency;
> 
>   void doFunction(FunctionT *fn, BlockProbInfoT *bpi) {
> 
> Modified: llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h?rev=133776&r1=133775&r2=133776&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h (original)
> +++ llvm/trunk/include/llvm/Analysis/BranchProbabilityInfo.h Thu Jun 23 18:52:11 2011
> @@ -39,9 +39,6 @@
>   // Get sum of the block successors' weights.
>   uint32_t getSumForBlock(BasicBlock *BB) const;
> 
> -  // Get sum of the edge weights going to the BB block.
> -  uint32_t getBackSumForBlock(BasicBlock *BB) const;
> -
> public:
>   static char ID;
> 
> @@ -74,13 +71,6 @@
>   // only iff SRC block has only one successor.
>   BranchProbability getEdgeProbability(BasicBlock *Src, BasicBlock *Dst) const;
> 
> -  // Return a probability of getting to the DST block through SRC->DST edge.
> -  // Returned value is a fraction between 0 (0% probability) and
> -  // 1 (100% probability), however the value is never equal to 0, and can be 1
> -  // only iff DST block has only one predecesor.
> -  BranchProbability getBackEdgeProbability(BasicBlock *Src,
> -                                           BasicBlock *Dst) const;
> -
>   // Print value between 0 (0% probability) and 1 (100% probability),
>   // however the value is never equal to 0, and can be 1 only iff SRC block
>   // has only one successor.
> 
> Modified: llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp?rev=133776&r1=133775&r2=133776&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp (original)
> +++ llvm/trunk/lib/Analysis/BranchProbabilityInfo.cpp Thu Jun 23 18:52:11 2011
> @@ -279,21 +279,6 @@
>   return Sum;
> }
> 
> -uint32_t BranchProbabilityInfo::getBackSumForBlock(BasicBlock *BB) const {
> -  uint32_t Sum = 0;
> -
> -  for (pred_iterator I = pred_begin(BB), E = pred_end(BB); I != E; ++I) {
> -    BasicBlock *Pred = *I;
> -    uint32_t Weight = getEdgeWeight(Pred, BB);
> -    uint32_t PrevSum = Sum;
> -
> -    Sum += Weight;
> -    assert(Sum > PrevSum); (void) PrevSum;
> -  }
> -
> -  return Sum;
> -}
> -
> bool BranchProbabilityInfo::isEdgeHot(BasicBlock *Src, BasicBlock *Dst) const {
>   // Hot probability is at least 4/5 = 80%
>   uint32_t Weight = getEdgeWeight(Src, Dst);
> @@ -360,15 +345,6 @@
>   return BranchProbability(N, D);
> }
> 
> -BranchProbability BranchProbabilityInfo::
> -getBackEdgeProbability(BasicBlock *Src, BasicBlock *Dst) const {
> -
> -  uint32_t N = getEdgeWeight(Src, Dst);
> -  uint32_t D = getBackSumForBlock(Dst);
> -
> -  return BranchProbability(N, D);
> -}
> -
> raw_ostream &
> BranchProbabilityInfo::printEdgeProbability(raw_ostream &OS, BasicBlock *Src,
>                                             BasicBlock *Dst) const {
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From x.tong at utoronto.ca  Thu Jun 23 21:32:53 2011
From: x.tong at utoronto.ca (Xin Tong Utoronto)
Date: Thu, 23 Jun 2011 22:32:53 -0400
Subject: [llvm-commits] LLVM JIT Adaptive Compilation Patch
Message-ID: <BANLkTikF-SbCB1F7b9OK7GiM3UhMkaTmqA@mail.gmail.com>

One of the current drawbacks of the LLVM JIT is the lack of an
adaptive compilation system. All the non-adaptive bits are already
there in LLVM: optimizing compiler with the different types of
instruction selectors, register allocators, preRA schedulers, etc. and
a full set of optimizations changeable at runtime. What's left is a
system that can keep track of and dynamically look-up the hotness of
methods and re-compile with more expensive optimizations as the
methods are executed over and over. This should improve program
startup time and execution time and will bring great benefits to all
ported languages that intend to use LLVM JIT as one of the execution
methods.

The implementation of the adaptive compilation framework is one of the
Google Summer of Code 2011 project
(http://www.google-melange.com/gsoc/project/google/gsoc2011/timexerox/8001).
This patch is intended to provide the basic infrastructure for the
adaptive compilation framework. Code for specific platforms are
currently being developed. This patch is generate against the LLVM
trunk and using GIT.


-- 
Kind Regards

Xin Tong
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From baldrick at free.fr  Fri Jun 24 02:58:51 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 24 Jun 2011 09:58:51 +0200
Subject: [llvm-commits] [llvm] r133756 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstCombineSelect.cpp
 test/Transforms/InstCombine/select-crash.ll
In-Reply-To: <20110623204024.1B1392A6C12C@llvm.org>
References: <20110623204024.1B1392A6C12C@llvm.org>
Message-ID: <4E0443BB.1070306@free.fr>

Hi Eli,

> PR10180: Fix a instcombine crash with FP vectors.

maybe it would be better if the IRBuilder got a CreateAnyAdd method that
handles both fp and integers.

Ciao, Duncan.

From benny.kra at googlemail.com  Fri Jun 24 06:03:31 2011
From: benny.kra at googlemail.com (Benjamin Kramer)
Date: Fri, 24 Jun 2011 11:03:31 -0000
Subject: [llvm-commits] [llvm] r133791 -
	/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Message-ID: <20110624110331.D0EC32A6C12C@llvm.org>

Author: d0k
Date: Fri Jun 24 06:03:31 2011
New Revision: 133791

URL: http://llvm.org/viewvc/llvm-project?rev=133791&view=rev
Log:
Make the generated InitXXXMCRegisterInfo function "static inline", so it doesn't get emitted into multiple object files.

This caused linker errors when linking both libLLVMX86Desc and libLLVMX86CodeGen
into a single binary (for example when building a monolithic libLLVM shared library).

Modified:
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=133791&r1=133790&r2=133791&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Jun 24 06:03:31 2011
@@ -709,7 +709,7 @@
   OS << "}\n\n";       // End of anonymous namespace...
 
   // MCRegisterInfo initialization routine.
-  OS << "void " << "Init" << TargetName
+  OS << "static inline void Init" << TargetName
      << "MCRegisterInfo(MCRegisterInfo *RI) {\n";
   OS << "  RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
      << Regs.size()+1 << ");\n}\n\n";



From ofv at wanadoo.es  Fri Jun 24 07:11:51 2011
From: ofv at wanadoo.es (=?utf-8?Q?=C3=93scar_Fuentes?=)
Date: Fri, 24 Jun 2011 14:11:51 +0200
Subject: [llvm-commits] [llvm] r133787 -
	/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt
References: <20110624050449.184482A6C12C@llvm.org>
Message-ID: <87k4cbv37c.fsf@wanadoo.es>


> Author: evancheng
> Date: Fri Jun 24 00:04:48 2011
> New Revision: 133787
>
> URL: http://llvm.org/viewvc/llvm-project?rev=133787&view=rev
> Log:
> Fix CellSPU CMakeLists.txt
>
> Modified:
>     llvm/trunk/lib/Target/CellSPU/CMakeLists.txt
>
> Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt?rev=133787&r1=133786&r2=133787&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/CellSPU/CMakeLists.txt (original)
> +++ llvm/trunk/lib/Target/CellSPU/CMakeLists.txt Fri Jun 24 00:04:48 2011
> @@ -4,8 +4,9 @@
>  tablegen(SPUGenRegisterNames.inc -gen-register-enums)
>  tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
>  tablegen(SPUGenCodeEmitter.inc -gen-emitter)
> -tablegen(SPUGenRegisterInfo.h.inc -gen-register-desc-header)
> -tablegen(SPUGenRegisterInfo.inc -gen-register-desc)
> +tablegen(SPUGenRegisterDesc.inc -gen-register-info)
> +tablegen(SPUGenRegisterInfo.h.inc -gen-register-info-header)
> +tablegen(SPUGenRegisterInfo.inc -gen-register-info)

Is this correct? SPUGenRegisterDesc.inc and SPUGenRegisterInfo.inc are
both generated with -gen-register-info, which yields the same contents
for both files.

I could implement on CMake tblgen argument inference from the generated
file name, as the Makefile build does. Is the feature valuabe enough to
care?  (OTOH, why the feature is not implemented on tblgen itself?)


From rafael.espindola at gmail.com  Fri Jun 24 08:58:45 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 24 Jun 2011 13:58:45 -0000
Subject: [llvm-commits] [llvm] r133792 -
	/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt
Message-ID: <20110624135845.8DE202A6C12C@llvm.org>

Author: rafael
Date: Fri Jun 24 08:58:45 2011
New Revision: 133792

URL: http://llvm.org/viewvc/llvm-project?rev=133792&view=rev
Log:
Fix CellSPU CMakeList.txt.

Modified:
    llvm/trunk/lib/Target/CellSPU/CMakeLists.txt

Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt?rev=133792&r1=133791&r2=133792&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/CellSPU/CMakeLists.txt Fri Jun 24 08:58:45 2011
@@ -4,7 +4,7 @@
 tablegen(SPUGenRegisterNames.inc -gen-register-enums)
 tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
 tablegen(SPUGenCodeEmitter.inc -gen-emitter)
-tablegen(SPUGenRegisterDesc.inc -gen-register-info)
+tablegen(SPUGenRegisterDesc.inc -gen-register-desc)
 tablegen(SPUGenRegisterInfo.h.inc -gen-register-info-header)
 tablegen(SPUGenRegisterInfo.inc -gen-register-info)
 tablegen(SPUGenInstrInfo.inc -gen-instr-desc)



From rafael.espindola at gmail.com  Fri Jun 24 09:04:13 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 24 Jun 2011 14:04:13 -0000
Subject: [llvm-commits] [llvm] r133793 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
Message-ID: <20110624140413.659D52A6C12C@llvm.org>

Author: rafael
Date: Fri Jun 24 09:04:13 2011
New Revision: 133793

URL: http://llvm.org/viewvc/llvm-project?rev=133793&view=rev
Log:
Simplify now that blocks with phis are not considered simple.

Modified:
    llvm/trunk/lib/CodeGen/TailDuplication.cpp

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133793&r1=133792&r2=133793&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Fri Jun 24 09:04:13 2011
@@ -659,21 +659,6 @@
     MachineBasicBlock *NewTarget = *TailBB->succ_begin();
     MachineBasicBlock *NextBB = llvm::next(MachineFunction::iterator(PredBB));
 
-    DenseMap<unsigned, unsigned> LocalVRMap;
-    SmallVector<std::pair<unsigned,unsigned>, 4> CopyInfos;
-    for (MachineBasicBlock::iterator I = TailBB->begin();
-         I != TailBB->end() && I->isPHI();) {
-      MachineInstr *MI = &*I;
-      ++I;
-      ProcessPHI(MI, TailBB, PredBB, LocalVRMap, CopyInfos, UsedByPhi, true);
-    }
-    MachineBasicBlock::iterator Loc = PredBB->getFirstTerminator();
-    for (unsigned i = 0, e = CopyInfos.size(); i != e; ++i) {
-      Copies.push_back(BuildMI(*PredBB, Loc, DebugLoc(),
-                               TII->get(TargetOpcode::COPY),
-                               CopyInfos[i].first).addReg(CopyInfos[i].second));
-    }
-
     // Make PredFBB explicit.
     if (PredCond.empty())
       PredFBB = PredTBB;



From aggarwa4 at illinois.edu  Fri Jun 24 10:04:00 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Fri, 24 Jun 2011 15:04:00 -0000
Subject: [llvm-commits] [poolalloc] r133795 -
	/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
Message-ID: <20110624150400.C9E0A2A6C12C@llvm.org>

Author: aggarwa4
Date: Fri Jun 24 10:04:00 2011
New Revision: 133795

URL: http://llvm.org/viewvc/llvm-project?rev=133795&view=rev
Log:
Instead of visiting all calls to checkType, only
visit the ones using the same metadata value.

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133795&r1=133794&r2=133795&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Fri Jun 24 10:04:00 2011
@@ -501,11 +501,11 @@
         if(CI->getCalledFunction() != checkTypeInst)
           continue;
         std::list<Instruction *>toDelete;
-        for(Value::use_iterator User = checkTypeInst->use_begin(); User != checkTypeInst->use_end(); ++User) {
+        for(Value::use_iterator User = CI->getOperand(3)->use_begin(); User != CI->getOperand(3)->use_end(); ++User) {
           CallInst *CI2 = dyn_cast<CallInst>(User);
-          if(CI2 == CI)
+          if(!CI2)
             continue;
-          if(CI2->getParent()->getParent() != &F)
+          if(CI2 == CI)
             continue;
           // Check that they are refering to the same pointer
           if(CI->getOperand(4) != CI2->getOperand(4))
@@ -513,9 +513,9 @@
           // Check that they are using the same metadata for comparison.
           if(CI->getOperand(3) != CI2->getOperand(3))
             continue;
-          // if CI, dominates CI2, delete CI2
           if(!DT.dominates(CI, CI2))
             continue;
+          // if CI, dominates CI2, delete CI2
           toDelete.push_back(CI2);
         }
         while(!toDelete.empty()) {



From aggarwa4 at illinois.edu  Fri Jun 24 10:04:29 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Fri, 24 Jun 2011 15:04:29 -0000
Subject: [llvm-commits] [poolalloc] r133796 -
 /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
Message-ID: <20110624150429.62CA52A6C12C@llvm.org>

Author: aggarwa4
Date: Fri Jun 24 10:04:29 2011
New Revision: 133796

URL: http://llvm.org/viewvc/llvm-project?rev=133796&view=rev
Log:
Use 0xFE to indicate the middle of an object, instead of 0xOO

Modified:
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=133796&r1=133795&r2=133796&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Fri Jun 24 10:04:29 2011
@@ -139,7 +139,7 @@
 void trackGlobal(void *ptr, TypeTagTy typeNumber, uint64_t size, uint32_t tag) {
   uintptr_t p = maskAddress(ptr);
   shadow_begin[p] = typeNumber;
-  memset(&shadow_begin[p + 1], 0, size - 1);
+  memset(&shadow_begin[p + 1], 0xFE, size - 1);
 #if DEBUG
   cerr << "Global(" << tag << "): " << ptr << "= " << typeNumber << " " << size << "bytes\n";
 #endif
@@ -165,7 +165,7 @@
 void trackStoreInst(void *ptr, TypeTagTy typeNumber, uint64_t size, uint32_t tag) {
   uintptr_t p = maskAddress(ptr);
   shadow_begin[p] = typeNumber;
-  memset(&shadow_begin[p + 1], 0, size - 1);
+  memset(&shadow_begin[p + 1], 0xFE, size - 1);
 #if DEBUG
   cerr << "Store(" << tag << "): " << ptr << "= " << typeNumber << " " << size << "bytes\n";
 #endif
@@ -227,7 +227,7 @@
 void 
 checkType(TypeTagTy typeNumber, uint64_t size, TypeTagTy *metadata, void *ptr, uint32_t tag) {
   /* Check if this an initialized but untyped memory.*/
-  if (typeNumber != metadata[0]) {
+  if (typeNumber != metadata[0] && metadata[0] != 0xFE) {
     if (metadata[0] != 0xFF) {
       printf("Type mismatch(%u): %p expecting %s, found %s!\n", tag, ptr, typeNames[typeNumber], typeNames[metadata[0]]);
       return;
@@ -246,7 +246,7 @@
   }
 
   for (unsigned i = 1 ; i < size; ++i) {
-    if (0 != metadata[i]) {
+    if (0xFE != metadata[i]) {
       printf("Type alignment mismatch(%u): expecting %s, found %s!\n", tag, typeNames[typeNumber], typeNames[metadata[0]]);
       break;
     }



From jstaszak at apple.com  Fri Jun 24 10:29:27 2011
From: jstaszak at apple.com (Jakub Staszak)
Date: Fri, 24 Jun 2011 08:29:27 -0700
Subject: [llvm-commits] [llvm] r133776 - in /llvm/trunk:
 include/llvm/Analysis/BlockFrequencyImpl.h
 include/llvm/Analysis/BranchProbabilityInfo.h
 lib/Analysis/BranchProbabilityInfo.cpp
In-Reply-To: <6A7ABB0D-FBB1-440C-8257-586286D2C6E0@apple.com>
References: <20110623235211.A5CA82A6C12C@llvm.org>
	<6A7ABB0D-FBB1-440C-8257-586286D2C6E0@apple.com>
Message-ID: <45DA4075-E8A3-47F4-AF1B-F69A38A67294@apple.com>


On Jun 23, 2011, at 10:24 PM, Andrew Trick wrote:

> This is now identical to the original implementation whenever the frequency of the current loop header is START_FREQ (which it is always supposed to be). i.e. you have
> Res = (N * START_FREQ) / D = (EdgeFreq(src, dst) * START_FREQ) / START_FREQ.

The original implementation used only branch probability. Now we also use block frequency to calculate backedge probability.

-Kuba

From rafael.espindola at gmail.com  Fri Jun 24 10:47:41 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 24 Jun 2011 15:47:41 -0000
Subject: [llvm-commits] [llvm] r133797 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
Message-ID: <20110624154741.5B48F2A6C12C@llvm.org>

Author: rafael
Date: Fri Jun 24 10:47:41 2011
New Revision: 133797

URL: http://llvm.org/viewvc/llvm-project?rev=133797&view=rev
Log:
Now that bb with phis are not considered simple, duplicate them even if
we cannot duplicate to every predecessor.

Modified:
    llvm/trunk/lib/CodeGen/TailDuplication.cpp

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133797&r1=133796&r2=133797&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Fri Jun 24 10:47:41 2011
@@ -98,7 +98,7 @@
                              bool IsSimple, MachineBasicBlock &TailBB);
     bool isSimpleBB(MachineBasicBlock *TailBB);
     bool canCompletelyDuplicateBB(MachineBasicBlock &BB, bool IsSimple);
-    void duplicateSimpleBB(MachineBasicBlock *TailBB,
+    bool duplicateSimpleBB(MachineBasicBlock *TailBB,
                            SmallVector<MachineBasicBlock*, 8> &TDBBs,
                            const DenseSet<unsigned> &RegsUsedByPhi,
                            SmallVector<MachineInstr*, 16> &Copies);
@@ -568,7 +568,7 @@
     return true;
 
   if (IsSimple)
-    return canCompletelyDuplicateBB(TailBB, IsSimple);
+    return true;
 
   if (!PreRegAlloc)
     return true;
@@ -635,24 +635,32 @@
   return true;
 }
 
-void
+bool
 TailDuplicatePass::duplicateSimpleBB(MachineBasicBlock *TailBB,
                                      SmallVector<MachineBasicBlock*, 8> &TDBBs,
                                      const DenseSet<unsigned> &UsedByPhi,
                                      SmallVector<MachineInstr*, 16> &Copies) {
+  SmallPtrSet<MachineBasicBlock*, 8> Succs(TailBB->succ_begin(),
+                                           TailBB->succ_end());
   SmallVector<MachineBasicBlock*, 8> Preds(TailBB->pred_begin(),
                                            TailBB->pred_end());
+  bool Changed = false;
   for (SmallSetVector<MachineBasicBlock *, 8>::iterator PI = Preds.begin(),
        PE = Preds.end(); PI != PE; ++PI) {
     MachineBasicBlock *PredBB = *PI;
 
+    if (PredBB->getLandingPadSuccessor())
+      continue;
+
+    if (bothUsedInPHI(*PredBB, Succs))
+      continue;
+
     MachineBasicBlock *PredTBB = NULL, *PredFBB = NULL;
     SmallVector<MachineOperand, 4> PredCond;
-    bool NotAnalyzable =
-      TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true);
-    (void)NotAnalyzable;
-    assert(!NotAnalyzable && "Cannot duplicate this!");
+    if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
+      continue;
 
+    Changed = true;
     DEBUG(dbgs() << "\nTail-duplicating into PredBB: " << *PredBB
                  << "From simple Succ: " << *TailBB);
 
@@ -700,6 +708,7 @@
 
     TDBBs.push_back(PredBB);
   }
+  return Changed;
 }
 
 /// TailDuplicate - If it is profitable, duplicate TailBB's contents in each
@@ -718,11 +727,8 @@
   DenseSet<unsigned> UsedByPhi;
   getRegsUsedByPHIs(*TailBB, &UsedByPhi);
 
-  if (IsSimple) {
-    duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
-    return true;
-  }
-
+  if (IsSimple)
+    return duplicateSimpleBB(TailBB, TDBBs, UsedByPhi, Copies);
 
   // Iterate through all the unique predecessors and tail-duplicate this
   // block into them, if possible. Copying the list ahead of time also



From rafael.espindola at gmail.com  Fri Jun 24 10:50:56 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 24 Jun 2011 15:50:56 -0000
Subject: [llvm-commits] [llvm] r133798 -
	/llvm/trunk/lib/CodeGen/TailDuplication.cpp
Message-ID: <20110624155056.8C91A2A6C12C@llvm.org>

Author: rafael
Date: Fri Jun 24 10:50:56 2011
New Revision: 133798

URL: http://llvm.org/viewvc/llvm-project?rev=133798&view=rev
Log:
Simplify

Modified:
    llvm/trunk/lib/CodeGen/TailDuplication.cpp

Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=133798&r1=133797&r2=133798&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original)
+++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Fri Jun 24 10:50:56 2011
@@ -97,7 +97,7 @@
     bool shouldTailDuplicate(const MachineFunction &MF,
                              bool IsSimple, MachineBasicBlock &TailBB);
     bool isSimpleBB(MachineBasicBlock *TailBB);
-    bool canCompletelyDuplicateBB(MachineBasicBlock &BB, bool IsSimple);
+    bool canCompletelyDuplicateBB(MachineBasicBlock &BB);
     bool duplicateSimpleBB(MachineBasicBlock *TailBB,
                            SmallVector<MachineBasicBlock*, 8> &TDBBs,
                            const DenseSet<unsigned> &RegsUsedByPhi,
@@ -573,7 +573,7 @@
   if (!PreRegAlloc)
     return true;
 
-  return canCompletelyDuplicateBB(TailBB, IsSimple);
+  return canCompletelyDuplicateBB(TailBB);
 }
 
 /// isSimpleBB - True if this BB has only one unconditional jump.
@@ -606,30 +606,22 @@
 }
 
 bool
-TailDuplicatePass::canCompletelyDuplicateBB(MachineBasicBlock &BB,
-                                            bool isSimple) {
+TailDuplicatePass::canCompletelyDuplicateBB(MachineBasicBlock &BB) {
   SmallPtrSet<MachineBasicBlock*, 8> Succs(BB.succ_begin(), BB.succ_end());
 
   for (MachineBasicBlock::pred_iterator PI = BB.pred_begin(),
        PE = BB.pred_end(); PI != PE; ++PI) {
     MachineBasicBlock *PredBB = *PI;
 
-    if (isSimple) {
-      if (PredBB->getLandingPadSuccessor())
-        return false;
-      if (bothUsedInPHI(*PredBB, Succs))
-        return false;
-    } else {
-      if (PredBB->succ_size() > 1)
-        return false;
-    }
+    if (PredBB->succ_size() > 1)
+      return false;
 
     MachineBasicBlock *PredTBB = NULL, *PredFBB = NULL;
     SmallVector<MachineOperand, 4> PredCond;
     if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true))
       return false;
 
-    if (!isSimple && !PredCond.empty())
+    if (!PredCond.empty())
       return false;
   }
   return true;



From justin.holewinski at gmail.com  Fri Jun 24 11:27:49 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Fri, 24 Jun 2011 16:27:49 -0000
Subject: [llvm-commits] [llvm] r133799 - in /llvm/trunk/lib/Target/PTX:
 PTX.td PTXAsmPrinter.cpp PTXISelLowering.cpp PTXInstrInfo.td
 PTXSubtarget.cpp PTXSubtarget.h
Message-ID: <20110624162749.D656E2A6C12C@llvm.org>

Author: jholewinski
Date: Fri Jun 24 11:27:49 2011
New Revision: 133799

URL: http://llvm.org/viewvc/llvm-project?rev=133799&view=rev
Log:
PTX: Re-work target sm/compute selection and add some basic GPU
     targets: g80, gt200, gf100(fermi)

Modified:
    llvm/trunk/lib/Target/PTX/PTX.td
    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
    llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp
    llvm/trunk/lib/Target/PTX/PTXSubtarget.h

Modified: llvm/trunk/lib/Target/PTX/PTX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.td?rev=133799&r1=133798&r2=133799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTX.td (original)
+++ llvm/trunk/lib/Target/PTX/PTX.td Fri Jun 24 11:27:49 2011
@@ -30,31 +30,51 @@
 //===- PTX Version --------------------------------------------------------===//
 
 def FeaturePTX20 : SubtargetFeature<"ptx20", "PTXVersion", "PTX_VERSION_2_0",
-                                    "Use PTX Language Version 2.0",
-                                    []>;
+                                    "Use PTX Language Version 2.0">;
 
 def FeaturePTX21 : SubtargetFeature<"ptx21", "PTXVersion", "PTX_VERSION_2_1",
-                                    "Use PTX Language Version 2.1",
-                                    [FeaturePTX20]>;
+                                    "Use PTX Language Version 2.1">;
 
 def FeaturePTX22 : SubtargetFeature<"ptx22", "PTXVersion", "PTX_VERSION_2_2",
-                                    "Use PTX Language Version 2.2",
-                                    [FeaturePTX21]>;
+                                    "Use PTX Language Version 2.2">;
 
 def FeaturePTX23 : SubtargetFeature<"ptx23", "PTXVersion", "PTX_VERSION_2_3",
-                                    "Use PTX Language Version 2.3",
-                                    [FeaturePTX22]>;
+                                    "Use PTX Language Version 2.3">;
 
-//===- PTX Shader Model ---------------------------------------------------===//
+//===- PTX Target ---------------------------------------------------------===//
 
-def FeatureSM10 : SubtargetFeature<"sm10", "PTXShaderModel", "PTX_SM_1_0",
-                                   "Enable Shader Model 1.0 compliance">;
-def FeatureSM13 : SubtargetFeature<"sm13", "PTXShaderModel", "PTX_SM_1_3",
-                                   "Enable Shader Model 1.3 compliance",
-                                   [FeatureSM10, FeatureDouble]>;
-def FeatureSM20 : SubtargetFeature<"sm20", "PTXShaderModel", "PTX_SM_2_0",
-                                   "Enable Shader Model 2.0 compliance",
-                                   [FeatureSM13]>;
+def FeatureSM10 : SubtargetFeature<"sm10", "PTXTarget", "PTX_SM_1_0",
+                                   "Use Shader Model 1.0">;
+def FeatureSM11 : SubtargetFeature<"sm11", "PTXTarget", "PTX_SM_1_1",
+                                   "Use Shader Model 1.1">;
+def FeatureSM12 : SubtargetFeature<"sm12", "PTXTarget", "PTX_SM_1_2",
+                                   "Use Shader Model 1.2">;
+def FeatureSM13 : SubtargetFeature<"sm13", "PTXTarget", "PTX_SM_1_3",
+                                   "Use Shader Model 1.3">;
+def FeatureSM20 : SubtargetFeature<"sm20", "PTXTarget", "PTX_SM_2_0",
+                                   "Use Shader Model 2.0">;
+def FeatureSM21 : SubtargetFeature<"sm21", "PTXTarget", "PTX_SM_2_1",
+                                   "Use Shader Model 2.1">;
+def FeatureSM22 : SubtargetFeature<"sm22", "PTXTarget", "PTX_SM_2_2",
+                                   "Use Shader Model 2.2">;
+def FeatureSM23 : SubtargetFeature<"sm23", "PTXTarget", "PTX_SM_2_3",
+                                   "Use Shader Model 2.3">;
+
+def FeatureCOMPUTE10 : SubtargetFeature<"compute10", "PTXTarget",
+                                        "PTX_COMPUTE_1_0",
+                                        "Use Compute Compatibility 1.0">;
+def FeatureCOMPUTE11 : SubtargetFeature<"compute11", "PTXTarget",
+                                        "PTX_COMPUTE_1_1",
+                                        "Use Compute Compatibility 1.1">;
+def FeatureCOMPUTE12 : SubtargetFeature<"compute12", "PTXTarget",
+                                        "PTX_COMPUTE_1_2",
+                                        "Use Compute Compatibility 1.2">;
+def FeatureCOMPUTE13 : SubtargetFeature<"compute13", "PTXTarget",
+                                        "PTX_COMPUTE_1_3",
+                                        "Use Compute Compatibility 1.3">;
+def FeatureCOMPUTE20 : SubtargetFeature<"compute20", "PTXTarget",
+                                        "PTX_COMPUTE_2_0",
+                                        "Use Compute Compatibility 2.0">;
 
 //===----------------------------------------------------------------------===//
 // PTX supported processors
@@ -65,6 +85,27 @@
 
 def : Proc<"generic", []>;
 
+// Processor definitions for compute/shader models
+def : Proc<"compute_10", [FeatureCOMPUTE10]>;
+def : Proc<"compute_11", [FeatureCOMPUTE11]>;
+def : Proc<"compute_12", [FeatureCOMPUTE12]>;
+def : Proc<"compute_13", [FeatureCOMPUTE13]>;
+def : Proc<"compute_20", [FeatureCOMPUTE20]>;
+def : Proc<"sm_10",      [FeatureSM10]>;
+def : Proc<"sm_11",      [FeatureSM11]>;
+def : Proc<"sm_12",      [FeatureSM12]>;
+def : Proc<"sm_13",      [FeatureSM13]>;
+def : Proc<"sm_20",      [FeatureSM20]>;
+def : Proc<"sm_21",      [FeatureSM21]>;
+def : Proc<"sm_22",      [FeatureSM22]>;
+def : Proc<"sm_23",      [FeatureSM23]>;
+
+// Processor definitions for common GPU architectures
+def : Proc<"g80",        [FeatureSM10]>;
+def : Proc<"gt200",      [FeatureSM13]>;
+def : Proc<"gf100",      [FeatureSM20, FeatureDouble]>;
+def : Proc<"fermi",      [FeatureSM20, FeatureDouble]>;
+
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133799&r1=133798&r2=133799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Fri Jun 24 11:27:49 2011
@@ -462,7 +462,7 @@
     if (i != b) {
       decl += ", ";
     }
-    if (isKernel || ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
+    if (isKernel || ST.useParamSpaceForDeviceArgs()) {
       decl += ".param .b";
       decl += utostr(*i);
       decl += " ";

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=133799&r1=133798&r2=133799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Fri Jun 24 11:27:49 2011
@@ -213,7 +213,7 @@
   // We do one of two things here:
   // IsKernel || SM >= 2.0  ->  Use param space for arguments
   // SM < 2.0               ->  Use registers for arguments
-  if (MFI->isKernel() || ST.getShaderModel() >= PTXSubtarget::PTX_SM_2_0) {
+  if (MFI->isKernel() || ST.useParamSpaceForDeviceArgs()) {
     // We just need to emit the proper LOAD_PARAM ISDs
     for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
 

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=133799&r1=133798&r2=133799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Fri Jun 24 11:27:49 2011
@@ -26,10 +26,10 @@
 def Use64BitAddresses : Predicate<"getSubtarget().is64Bit()">;
 
 // Shader Model Support
-def SupportsSM13       : Predicate<"getSubtarget().supportsSM13()">;
-def DoesNotSupportSM13 : Predicate<"!getSubtarget().supportsSM13()">;
-def SupportsSM20       : Predicate<"getSubtarget().supportsSM20()">;
-def DoesNotSupportSM20 : Predicate<"!getSubtarget().supportsSM20()">;
+def FDivNeedsRoundingMode : Predicate<"getSubtarget().fdivNeedsRoundingMode()">;
+def FDivNoRoundingMode : Predicate<"!getSubtarget().fdivNeedsRoundingMode()">;
+def FMadNeedsRoundingMode : Predicate<"getSubtarget().fmadNeedsRoundingMode()">;
+def FMadNoRoundingMode : Predicate<"!getSubtarget().fmadNeedsRoundingMode()">;
 
 // PTX Version Support
 def SupportsPTX21       : Predicate<"getSubtarget().supportsPTX21()">;
@@ -613,43 +613,43 @@
                        (ins RegF32:$a, RegF32:$b),
                        "div.rn.f32\t$d, $a, $b",
                        [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
-                   Requires<[SupportsSM13]>;
+                   Requires<[FDivNeedsRoundingMode]>;
 def FDIVri32SM13 : InstPTX<(outs RegF32:$d),
                        (ins RegF32:$a, f32imm:$b),
                        "div.rn.f32\t$d, $a, $b",
                        [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
-                   Requires<[SupportsSM13]>;
+                   Requires<[FDivNeedsRoundingMode]>;
 def FDIVrr32SM10 : InstPTX<(outs RegF32:$d),
                        (ins RegF32:$a, RegF32:$b),
                        "div.f32\t$d, $a, $b",
                        [(set RegF32:$d, (fdiv RegF32:$a, RegF32:$b))]>,
-                   Requires<[DoesNotSupportSM13]>;
+                   Requires<[FDivNoRoundingMode]>;
 def FDIVri32SM10 : InstPTX<(outs RegF32:$d),
                        (ins RegF32:$a, f32imm:$b),
                        "div.f32\t$d, $a, $b",
                        [(set RegF32:$d, (fdiv RegF32:$a, fpimm:$b))]>,
-                   Requires<[DoesNotSupportSM13]>;
+                   Requires<[FDivNoRoundingMode]>;
 
 def FDIVrr64SM13 : InstPTX<(outs RegF64:$d),
                            (ins RegF64:$a, RegF64:$b),
                            "div.rn.f64\t$d, $a, $b",
                            [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
-                   Requires<[SupportsSM13]>;
+                   Requires<[FDivNeedsRoundingMode]>;
 def FDIVri64SM13 : InstPTX<(outs RegF64:$d),
                            (ins RegF64:$a, f64imm:$b),
                            "div.rn.f64\t$d, $a, $b",
                            [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
-                   Requires<[SupportsSM13]>;
+                   Requires<[FDivNeedsRoundingMode]>;
 def FDIVrr64SM10 : InstPTX<(outs RegF64:$d),
                            (ins RegF64:$a, RegF64:$b),
                            "div.f64\t$d, $a, $b",
                            [(set RegF64:$d, (fdiv RegF64:$a, RegF64:$b))]>,
-                   Requires<[DoesNotSupportSM13]>;
+                   Requires<[FDivNoRoundingMode]>;
 def FDIVri64SM10 : InstPTX<(outs RegF64:$d),
                            (ins RegF64:$a, f64imm:$b),
                            "div.f64\t$d, $a, $b",
                            [(set RegF64:$d, (fdiv RegF64:$a, fpimm:$b))]>,
-                   Requires<[DoesNotSupportSM13]>;
+                   Requires<[FDivNoRoundingMode]>;
 
 
 
@@ -661,8 +661,10 @@
 // In the short term, mad is supported on all PTX versions and we use a
 // default rounding mode no matter what shader model or PTX version.
 // TODO: Allow the rounding mode to be selectable through llc.
-defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>, Requires<[SupportsSM13, SupportsFMA]>;
-defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>, Requires<[DoesNotSupportSM13, SupportsFMA]>;
+defm FMADSM13 : PTX_FLOAT_4OP<"mad.rn", fmul, fadd>,
+                Requires<[FMadNeedsRoundingMode, SupportsFMA]>;
+defm FMAD : PTX_FLOAT_4OP<"mad", fmul, fadd>,
+            Requires<[FMadNoRoundingMode, SupportsFMA]>;
 
 ///===- Floating-Point Intrinsic Instructions -----------------------------===//
 

Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=133799&r1=133798&r2=133799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Fri Jun 24 11:27:49 2011
@@ -18,21 +18,31 @@
 
 PTXSubtarget::PTXSubtarget(const std::string &TT, const std::string &FS,
                            bool is64Bit)
-  : PTXShaderModel(PTX_SM_1_0),
+  : PTXTarget(PTX_COMPUTE_1_0),
     PTXVersion(PTX_VERSION_2_0),
     SupportsDouble(false),
     SupportsFMA(true),
-    Is64Bit(is64Bit) {	
+    Is64Bit(is64Bit) {
   std::string TARGET = "generic";
   ParseSubtargetFeatures(FS, TARGET);
 }
 
 std::string PTXSubtarget::getTargetString() const {
-  switch(PTXShaderModel) {
-    default: llvm_unreachable("Unknown shader model");
+  switch(PTXTarget) {
+    default: llvm_unreachable("Unknown PTX target");
     case PTX_SM_1_0: return "sm_10";
+    case PTX_SM_1_1: return "sm_11";
+    case PTX_SM_1_2: return "sm_12";
     case PTX_SM_1_3: return "sm_13";
     case PTX_SM_2_0: return "sm_20";
+    case PTX_SM_2_1: return "sm_21";
+    case PTX_SM_2_2: return "sm_22";
+    case PTX_SM_2_3: return "sm_23";
+    case PTX_COMPUTE_1_0: return "compute_10";
+    case PTX_COMPUTE_1_1: return "compute_11";
+    case PTX_COMPUTE_1_2: return "compute_12";
+    case PTX_COMPUTE_1_3: return "compute_13";
+    case PTX_COMPUTE_2_0: return "compute_20";
   }
 }
 

Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.h?rev=133799&r1=133798&r2=133799&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXSubtarget.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXSubtarget.h Fri Jun 24 11:27:49 2011
@@ -23,10 +23,23 @@
       /**
        * Enumeration of Shader Models supported by the back-end.
        */
-      enum PTXShaderModelEnum {
+      enum PTXTargetEnum {
+        PTX_COMPUTE_1_0, /*< Compute Compatibility 1.0 */
+        PTX_COMPUTE_1_1, /*< Compute Compatibility 1.1 */
+        PTX_COMPUTE_1_2, /*< Compute Compatibility 1.2 */
+        PTX_COMPUTE_1_3, /*< Compute Compatibility 1.3 */
+        PTX_COMPUTE_2_0, /*< Compute Compatibility 2.0 */
+        PTX_LAST_COMPUTE,
+
         PTX_SM_1_0, /*< Shader Model 1.0 */
+        PTX_SM_1_1, /*< Shader Model 1.1 */
+        PTX_SM_1_2, /*< Shader Model 1.2 */
         PTX_SM_1_3, /*< Shader Model 1.3 */
-        PTX_SM_2_0  /*< Shader Model 2.0 */
+        PTX_SM_2_0, /*< Shader Model 2.0 */
+        PTX_SM_2_1, /*< Shader Model 2.1 */
+        PTX_SM_2_2, /*< Shader Model 2.2 */
+        PTX_SM_2_3, /*< Shader Model 2.3 */
+        PTX_LAST_SM
       };
 
       /**
@@ -44,7 +57,7 @@
   private:
 
       /// Shader Model supported on the target GPU.
-      PTXShaderModelEnum PTXShaderModel;
+      PTXTargetEnum PTXTarget;
 
       /// PTX Language Version.
       PTXVersionEnum PTXVersion;
@@ -74,18 +87,26 @@
 
       bool supportsFMA() const { return SupportsFMA; }
 
-      bool supportsSM13() const { return PTXShaderModel >= PTX_SM_1_3; }
-
-      bool supportsSM20() const { return PTXShaderModel >= PTX_SM_2_0; }
-
       bool supportsPTX21() const { return PTXVersion >= PTX_VERSION_2_1; }
 
       bool supportsPTX22() const { return PTXVersion >= PTX_VERSION_2_2; }
 
       bool supportsPTX23() const { return PTXVersion >= PTX_VERSION_2_3; }
 
-      PTXShaderModelEnum getShaderModel() const { return PTXShaderModel; }
-
+      bool fdivNeedsRoundingMode() const {
+        return (PTXTarget >= PTX_SM_1_3 && PTXTarget < PTX_LAST_SM) ||
+               (PTXTarget >= PTX_COMPUTE_1_3 && PTXTarget < PTX_LAST_COMPUTE);
+      }
+
+      bool fmadNeedsRoundingMode() const {
+        return (PTXTarget >= PTX_SM_1_3 && PTXTarget < PTX_LAST_SM) ||
+               (PTXTarget >= PTX_COMPUTE_1_3 && PTXTarget < PTX_LAST_COMPUTE);
+      }
+
+      bool useParamSpaceForDeviceArgs() const {
+        return (PTXTarget >= PTX_SM_2_0 && PTXTarget < PTX_LAST_SM) ||
+               (PTXTarget >= PTX_COMPUTE_2_0 && PTXTarget < PTX_LAST_COMPUTE);
+      }
 
       std::string ParseSubtargetFeatures(const std::string &FS,
                                          const std::string &CPU);



From jstaszak at apple.com  Fri Jun 24 11:41:49 2011
From: jstaszak at apple.com (Jakub Staszak)
Date: Fri, 24 Jun 2011 09:41:49 -0700
Subject: [llvm-commits] [llvm] r133776 - in /llvm/trunk:
 include/llvm/Analysis/BlockFrequencyImpl.h
 include/llvm/Analysis/BranchProbabilityInfo.h
 lib/Analysis/BranchProbabilityInfo.cpp
In-Reply-To: <6A7ABB0D-FBB1-440C-8257-586286D2C6E0@apple.com>
References: <20110623235211.A5CA82A6C12C@llvm.org>
	<6A7ABB0D-FBB1-440C-8257-586286D2C6E0@apple.com>
Message-ID: <4DFE7777-735C-486C-897D-868E56C02EA7@apple.com>


On Jun 23, 2011, at 10:24 PM, Andrew Trick wrote:

> You also made this change, which may have fixed the original problem:
>> uint32_t Numerator = START_FREQ - CProb ? START_FREQ - CProb : 1;
> 
> To me that implies a loop with zero probability of exiting. If so, please comment.

Yes, it means infinite loop. I will comment that.

-Kuba

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From ahatanak at gmail.com  Fri Jun 24 12:55:19 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 24 Jun 2011 17:55:19 -0000
Subject: [llvm-commits] [llvm] r133803 - in /llvm/trunk:
 lib/Target/Mips/MipsISelDAGToDAG.cpp
 test/CodeGen/Mips/2008-07-15-SmallSection.ll
 test/CodeGen/Mips/internalfunc.ll test/CodeGen/Mips/o32_cc_byval.ll
Message-ID: <20110624175519.8FE352A6C12C@llvm.org>

Author: ahatanak
Date: Fri Jun 24 12:55:19 2011
New Revision: 133803

URL: http://llvm.org/viewvc/llvm-project?rev=133803&view=rev
Log:
Prevent generation of redundant addiu instructions that compute address of 
static variables or functions. 



Modified:
    llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll
    llvm/trunk/test/CodeGen/Mips/internalfunc.ll
    llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll

Modified: llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp?rev=133803&r1=133802&r2=133803&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelDAGToDAG.cpp Fri Jun 24 12:55:19 2011
@@ -170,7 +170,8 @@
          Addr.getOperand(0).getOpcode() == ISD::LOAD) &&
         Addr.getOperand(1).getOpcode() == MipsISD::Lo) {
       SDValue LoVal = Addr.getOperand(1);
-      if (dyn_cast<ConstantPoolSDNode>(LoVal.getOperand(0))) {
+      if (isa<ConstantPoolSDNode>(LoVal.getOperand(0)) || 
+          isa<GlobalAddressSDNode>(LoVal.getOperand(0))) {
         Base = Addr.getOperand(0);
         Offset = LoVal.getOperand(0);
         return true;

Modified: llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll?rev=133803&r1=133802&r2=133803&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/2008-07-15-SmallSection.ll Fri Jun 24 12:55:19 2011
@@ -7,7 +7,7 @@
 ; RUN: not grep {sbss} %t1 
 ; RUN: not grep {gp_rel} %t1
 ; RUN: grep {\%hi} %t1 | count 2
-; RUN: grep {\%lo} %t1 | count 2
+; RUN: grep {\%lo} %t1 | count 3
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "mipsallegrexel-unknown-psp-elf"

Modified: llvm/trunk/test/CodeGen/Mips/internalfunc.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/internalfunc.ll?rev=133803&r1=133802&r2=133803&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/internalfunc.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/internalfunc.ll Fri Jun 24 12:55:19 2011
@@ -15,7 +15,7 @@
 define void @caller(i32 %a0, i32 %a1) nounwind {
 entry:
 ; CHECK: lw  $[[R1:[0-9]+]], %got(caller.sf1)($gp)
-; CHECK: addiu ${{[0-9]+}}, $[[R1]], %lo(caller.sf1)
+; CHECK: lw  $25, %lo(caller.sf1)($[[R1]])
   %tobool = icmp eq i32 %a1, 0
   br i1 %tobool, label %if.end, label %if.then
 
@@ -26,9 +26,9 @@
 
 if.end:                                           ; preds = %entry, %if.then
 ; CHECK: lw  $[[R2:[0-9]+]], %got(sf2)($gp)
-; CHECK: lw  $[[R3:[0-9]+]], %got(caller.sf1)($gp)
 ; CHECK: addiu ${{[0-9]+}}, $[[R2]], %lo(sf2)
-; CHECK: addiu ${{[0-9]+}}, $[[R3]], %lo(caller.sf1)
+; CHECK: lw  $[[R3:[0-9]+]], %got(caller.sf1)($gp)
+; CHECK: sw  ${{[0-9]+}}, %lo(caller.sf1)($[[R3]])
   %tobool3 = icmp ne i32 %a0, 0
   %tmp4 = load void (...)** @gf1, align 4
   %cond = select i1 %tobool3, void (...)* %tmp4, void (...)* bitcast (void ()* @sf2 to void (...)*)

Modified: llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll?rev=133803&r1=133802&r2=133803&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/o32_cc_byval.ll Fri Jun 24 12:55:19 2011
@@ -24,7 +24,7 @@
 ; CHECK: sw  $[[R4]], 28($sp)
 ; CHECK: sw  $[[R5]], 32($sp)
 ; CHECK: sw  $[[R6]], 36($sp)
-; CHECK: lw  $6, 0($[[R0]])
+; CHECK: lw  $6, %lo(f1.s1)($[[R1]])
 ; CHECK: lw  $7, 4($[[R0]])
   %agg.tmp10 = alloca %struct.S3, align 4
   call void @callee1(float 2.000000e+01, %struct.S1* byval bitcast (%0* @f1.s1 to %struct.S1*)) nounwind



From echristo at apple.com  Fri Jun 24 13:30:09 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 24 Jun 2011 11:30:09 -0700
Subject: [llvm-commits] LLVM JIT Adaptive Compilation Patch
In-Reply-To: <BANLkTikF-SbCB1F7b9OK7GiM3UhMkaTmqA@mail.gmail.com>
References: <BANLkTikF-SbCB1F7b9OK7GiM3UhMkaTmqA@mail.gmail.com>
Message-ID: <2894FE3F-99D2-4FEC-95FA-5F92B638E907@apple.com>


On Jun 23, 2011, at 7:32 PM, Xin Tong Utoronto wrote:

> One of the current drawbacks of the LLVM JIT is the lack of an adaptive compilation system. All the non-adaptive bits are already there in LLVM: optimizing compiler with the different types of instruction selectors, register allocators, preRA schedulers, etc. and a full set of optimizations changeable at runtime. What's left is a system that can keep track of and dynamically look-up the hotness of methods and re-compile with more expensive optimizations as the methods are executed over and over. This should improve program startup time and execution time and will bring great benefits to all ported languages that intend to use LLVM JIT as one of the execution methods. 
> The implementation of the adaptive compilation framework is one of the Google Summer of Code 2011 project (http://www.google-melange.com/gsoc/project/google/gsoc2011/timexerox/8001). This patch is intended to provide the basic infrastructure for the adaptive compilation framework. Code for specific platforms are currently being developed. This patch is generate against the LLVM trunk and using GIT.

I realize I've looked at this already, but more eyes would be good. I'll also give it a bit more testing shortly.

That said can you provide some more information with this for everyone? What tests is gives a performance win on and what tests we can expect to see regressions on? Some of the logic behind some of your decisions etc?

Thanks!

-eric

From grosbach at apple.com  Fri Jun 24 13:48:32 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 24 Jun 2011 18:48:32 -0000
Subject: [llvm-commits] [llvm] r133808 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20110624184832.A09822A6C12C@llvm.org>

Author: grosbach
Date: Fri Jun 24 13:48:32 2011
New Revision: 133808

URL: http://llvm.org/viewvc/llvm-project?rev=133808&view=rev
Log:
Fixup info for Thumb2 unconditional branch.

rdar://9667872

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=133808&r1=133807&r2=133808&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Fri Jun 24 13:48:32 2011
@@ -1099,6 +1099,7 @@
     Log2Size = llvm::Log2_32(2);
     return true;
       
+  case ARM::fixup_t2_uncondbranch:
   case ARM::fixup_arm_thumb_bl:
   case ARM::fixup_arm_thumb_blx:
     RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);



From ahatanak at gmail.com  Fri Jun 24 14:01:25 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 24 Jun 2011 19:01:25 -0000
Subject: [llvm-commits] [llvm] r133811 - in /llvm/trunk:
 lib/Target/Mips/MipsISelLowering.cpp test/CodeGen/Mips/alloca.ll
 test/CodeGen/Mips/i64arg.ll test/CodeGen/Mips/largeimmprinting.ll
Message-ID: <20110624190125.9F1C52A6C12C@llvm.org>

Author: ahatanak
Date: Fri Jun 24 14:01:25 2011
New Revision: 133811

URL: http://llvm.org/viewvc/llvm-project?rev=133811&view=rev
Log:
Change the chain input of nodes that load the address of a function. This change
 enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a
pre-existing node instead of redundantly create a new node every time it is
called.



Modified:
    llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
    llvm/trunk/test/CodeGen/Mips/alloca.ll
    llvm/trunk/test/CodeGen/Mips/i64arg.ll
    llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll

Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=133811&r1=133810&r2=133811&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Fri Jun 24 14:01:25 2011
@@ -1911,7 +1911,7 @@
     if (LoadSymAddr) {
       // Load callee address
       Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee);
-      SDValue LoadValue = DAG.getLoad(MVT::i32, dl, Chain, Callee,
+      SDValue LoadValue = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), Callee,
                                       MachinePointerInfo::getGOT(),
                                       false, false, 0);
 
@@ -1921,9 +1921,6 @@
         Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo);
       } else
         Callee = LoadValue;
-
-      // Use chain output from LoadValue
-      Chain = LoadValue.getValue(1);
     }
 
     // copy to T9

Modified: llvm/trunk/test/CodeGen/Mips/alloca.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/alloca.ll?rev=133811&r1=133810&r2=133811&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/alloca.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/alloca.ll Fri Jun 24 14:01:25 2011
@@ -8,11 +8,9 @@
 ; CHECK: subu  $[[T2:[0-9]+]], $sp, $[[SZ]]
 ; CHECK: addu  $sp, $zero, $[[T2]]
 ; CHECK: addiu $[[T3:[0-9]+]], $sp, [[OFF]]
-; CHECK: lw  $25, %call16(foo)($gp)
-; CHECK: addu $4, $zero, $[[T1]]
-; CHECK: jalr  $25
-; CHECK: lw  $25, %call16(foo)($gp)
-; CHECK: addu $4, $zero, $[[T3]]
+; CHECK: lw    $[[T4:[0-9]+]], %call16(foo)($gp)
+; CHECK: addu  $25, $zero, $[[T4]]
+; CHECK: addu  $4, $zero, $[[T1]]
 ; CHECK: jalr  $25
   %tmp1 = alloca i8, i32 %size, align 4
   %add.ptr = getelementptr inbounds i8* %tmp1, i32 5

Modified: llvm/trunk/test/CodeGen/Mips/i64arg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/i64arg.ll?rev=133811&r1=133810&r2=133811&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/i64arg.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/i64arg.ll Fri Jun 24 14:01:25 2011
@@ -10,8 +10,8 @@
 ; CHECK: jalr
   tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind
 ; CHECK: lw $25, %call16(ff2)
-; CHECK: lw $[[R2:[0-9]+]], 80($sp)
-; CHECK: lw $[[R3:[0-9]+]], 84($sp)
+; CHECK: lw $[[R2:[0-9]+]], 88($sp)
+; CHECK: lw $[[R3:[0-9]+]], 92($sp)
 ; CHECK: addu $4, $zero, $[[R2]]
 ; CHECK: addu $5, $zero, $[[R3]]
 ; CHECK: jalr $25

Modified: llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll?rev=133811&r1=133810&r2=133811&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll (original)
+++ llvm/trunk/test/CodeGen/Mips/largeimmprinting.ll Fri Jun 24 14:01:25 2011
@@ -8,7 +8,7 @@
 entry:
 ; CHECK:  lui $at, 65534
 ; CHECK:  addu  $at, $sp, $at
-; CHECK:  addiu $sp, $at, -16
+; CHECK:  addiu $sp, $at, -24
 ; CHECK:  .cprestore  65536
 
   %agg.tmp = alloca %struct.S1, align 1



From justin.holewinski at gmail.com  Fri Jun 24 14:19:18 2011
From: justin.holewinski at gmail.com (Justin Holewinski)
Date: Fri, 24 Jun 2011 19:19:18 -0000
Subject: [llvm-commits] [llvm] r133812 -
	/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
Message-ID: <20110624191918.DBBFA2A6C12C@llvm.org>

Author: jholewinski
Date: Fri Jun 24 14:19:18 2011
New Revision: 133812

URL: http://llvm.org/viewvc/llvm-project?rev=133812&view=rev
Log:
PTX: Add preliminary support for outputting debug information in the form of
     .file and .loc directives.

Ideally, we would utilize the existing support in AsmPrinter for this, but
I cannot find a way to get .file and .loc directives to print without the
rest of the associated DWARF sections, which ptxas cannot handle.

Modified:
    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133812&r1=133811&r2=133812&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Fri Jun 24 14:19:18 2011
@@ -22,10 +22,12 @@
 #include "llvm/ADT/SmallString.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Twine.h"
+#include "llvm/Analysis/DebugInfo.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Target/Mangler.h"
@@ -35,6 +37,7 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MathExtras.h"
+#include "llvm/Support/Path.h"
 #include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
@@ -67,6 +70,9 @@
                           const char *Modifier = 0); 
   void printPredicateOperand(const MachineInstr *MI, raw_ostream &O);
 
+  unsigned GetOrCreateSourceID(StringRef FileName,
+                               StringRef DirName);
+
   // autogen'd.
   void printInstruction(const MachineInstr *MI, raw_ostream &OS);
   static const char *getRegisterName(unsigned RegNo);
@@ -74,6 +80,8 @@
 private:
   void EmitVariableDeclaration(const GlobalVariable *gv);
   void EmitFunctionDeclaration();
+
+  StringMap<unsigned> SourceIdMap;
 }; // class PTXAsmPrinter
 } // namespace
 
@@ -175,6 +183,20 @@
 
   OutStreamer.AddBlankLine();
 
+  // Define any .file directives
+  DebugInfoFinder DbgFinder;
+  DbgFinder.processModule(M);
+
+  for (DebugInfoFinder::iterator I = DbgFinder.compile_unit_begin(),
+       E = DbgFinder.compile_unit_end(); I != E; ++I) {
+    DICompileUnit DIUnit(*I);
+    StringRef FN = DIUnit.getFilename();
+    StringRef Dir = DIUnit.getDirectory();
+    GetOrCreateSourceID(FN, Dir);
+  }
+
+  OutStreamer.AddBlankLine();
+
   // declare global variables
   for (Module::const_global_iterator i = M.global_begin(), e = M.global_end();
        i != e; ++i)
@@ -228,6 +250,54 @@
 
   raw_string_ostream OS(str);
 
+  DebugLoc DL = MI->getDebugLoc();
+  if (!DL.isUnknown()) {
+
+    const MDNode *S = DL.getScope(MF->getFunction()->getContext());
+
+    // This is taken from DwarfDebug.cpp, which is conveniently not a public
+    // LLVM class.
+    StringRef Fn;
+    StringRef Dir;
+    unsigned Src = 1;
+    if (S) {
+      DIDescriptor Scope(S);
+      if (Scope.isCompileUnit()) {
+        DICompileUnit CU(S);
+        Fn = CU.getFilename();
+        Dir = CU.getDirectory();
+      } else if (Scope.isFile()) {
+        DIFile F(S);
+        Fn = F.getFilename();
+        Dir = F.getDirectory();
+      } else if (Scope.isSubprogram()) {
+        DISubprogram SP(S);
+        Fn = SP.getFilename();
+        Dir = SP.getDirectory();
+      } else if (Scope.isLexicalBlock()) {
+        DILexicalBlock DB(S);
+        Fn = DB.getFilename();
+        Dir = DB.getDirectory();
+      } else
+        assert(0 && "Unexpected scope info");
+
+      Src = GetOrCreateSourceID(Fn, Dir);
+    }
+    OutStreamer.EmitDwarfLocDirective(Src, DL.getLine(), DL.getCol(),
+                                     0, 0, 0, Fn);
+
+    const MCDwarfLoc& MDL = OutContext.getCurrentDwarfLoc();
+
+    OS << "\t.loc ";
+    OS << utostr(MDL.getFileNum());
+    OS << " ";
+    OS << utostr(MDL.getLine());
+    OS << " ";
+    OS << utostr(MDL.getColumn());
+    OS << "\n";
+  }
+
+
   // Emit predicate
   printPredicateOperand(MI, OS);
 
@@ -499,6 +569,33 @@
   }
 }
 
+unsigned PTXAsmPrinter::GetOrCreateSourceID(StringRef FileName,
+                                            StringRef DirName) {
+  // If FE did not provide a file name, then assume stdin.
+  if (FileName.empty())
+    return GetOrCreateSourceID("<stdin>", StringRef());
+
+  // MCStream expects full path name as filename.
+  if (!DirName.empty() && !sys::path::is_absolute(FileName)) {
+    SmallString<128> FullPathName = DirName;
+    sys::path::append(FullPathName, FileName);
+    // Here FullPathName will be copied into StringMap by GetOrCreateSourceID.
+    return GetOrCreateSourceID(StringRef(FullPathName), StringRef());
+  }
+
+  StringMapEntry<unsigned> &Entry = SourceIdMap.GetOrCreateValue(FileName);
+  if (Entry.getValue())
+    return Entry.getValue();
+
+  unsigned SrcId = SourceIdMap.size();
+  Entry.setValue(SrcId);
+
+  // Print out a .file directive to specify files for .loc directives.
+  OutStreamer.EmitDwarfFileDirective(SrcId, Entry.getKey());
+
+  return SrcId;
+}
+
 #include "PTXGenAsmWriter.inc"
 
 // Force static initialization.



From mcrosier at apple.com  Fri Jun 24 14:23:04 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Fri, 24 Jun 2011 19:23:04 -0000
Subject: [llvm-commits] [llvm] r133813 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vcvt_combine.ll
 test/CodeGen/ARM/vdiv_combine.ll
Message-ID: <20110624192304.BAAB22A6C12C@llvm.org>

Author: mcrosier
Date: Fri Jun 24 14:23:04 2011
New Revision: 133813

URL: http://llvm.org/viewvc/llvm-project?rev=133813&view=rev
Log:
The Neon VCVT (between floating-point and fixed-point, Advanced SIMD) 
instructions can be used to match combinations of multiply/divide and VCVT 
(between floating-point and integer, Advanced SIMD).  Basically the VCVT 
immediate operand that specifies the number of fraction bits corresponds to a 
floating-point multiply or divide by the corresponding power of 2.

For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a 
combination of VMUL and VCVT (floating-point to integer) as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vmul.f32        d16, d17, d16
  vcvt.s32.f32    d16, d16
becomes:
  vcvt.s32.f32    d16, d16, #3

Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a 
combinations of VCVT (integer to floating-point) and VDIV as follows:

Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
  vcvt.f32.s32    d16, d16
  vdiv.f32        d16, d17, d16
becomes:
  vcvt.f32.s32    d16, d16, #3

Added:
    llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll
    llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=133813&r1=133812&r2=133813&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 24 14:23:04 2011
@@ -506,6 +506,9 @@
     setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
     setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
     setTargetDAGCombine(ISD::STORE);
+    setTargetDAGCombine(ISD::FP_TO_SINT);
+    setTargetDAGCombine(ISD::FP_TO_UINT);
+    setTargetDAGCombine(ISD::FDIV);
   }
 
   computeRegisterProperties();
@@ -6479,7 +6482,104 @@
   return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
 }
 
-/// getVShiftImm - Check if this is a valid build_vector for the immediate
+// isConstVecPow2 - Return true if each vector element is a power of 2, all 
+// elements are the same constant, C, and Log2(C) ranges from 1 to 32.
+static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
+{
+  integerPart c0, cN;
+  for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
+       I != E; I++) {
+    ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
+    if (!C)
+      return false;
+
+    bool isExact;    
+    APFloat APF = C->getValueAPF();
+    if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
+        != APFloat::opOK || !isExact)
+      return false;
+
+    c0 = (I == 0) ? cN : c0;
+    if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
+      return false;
+  }
+  C = c0;
+  return true;
+}
+
+/// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
+/// can replace combinations of VMUL and VCVT (floating-point to integer)
+/// when the VMUL has a constant operand that is a power of 2.
+///
+/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
+///  vmul.f32        d16, d17, d16
+///  vcvt.s32.f32    d16, d16
+/// becomes:
+///  vcvt.s32.f32    d16, d16, #3
+static SDValue PerformVCVTCombine(SDNode *N,
+                                  TargetLowering::DAGCombinerInfo &DCI,
+                                  const ARMSubtarget *Subtarget) {
+  SelectionDAG &DAG = DCI.DAG;
+  SDValue Op = N->getOperand(0);
+
+  if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
+      Op.getOpcode() != ISD::FMUL)
+    return SDValue();
+
+  uint64_t C;
+  SDValue N0 = Op->getOperand(0);
+  SDValue ConstVec = Op->getOperand(1);
+  bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
+
+  if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 
+      !isConstVecPow2(ConstVec, isSigned, C))
+    return SDValue();
+
+  unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
+    Intrinsic::arm_neon_vcvtfp2fxu;
+  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
+                     N->getValueType(0),
+                     DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, 
+                     DAG.getConstant(Log2_64(C), MVT::i32));
+}
+
+/// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
+/// can replace combinations of VCVT (integer to floating-point) and VDIV
+/// when the VDIV has a constant operand that is a power of 2.
+///
+/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
+///  vcvt.f32.s32    d16, d16
+///  vdiv.f32        d16, d17, d16
+/// becomes:
+///  vcvt.f32.s32    d16, d16, #3
+static SDValue PerformVDIVCombine(SDNode *N,
+                                  TargetLowering::DAGCombinerInfo &DCI,
+                                  const ARMSubtarget *Subtarget) {
+  SelectionDAG &DAG = DCI.DAG;
+  SDValue Op = N->getOperand(0);
+  unsigned OpOpcode = Op.getNode()->getOpcode();
+
+  if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
+      (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
+    return SDValue();
+
+  uint64_t C;
+  SDValue ConstVec = N->getOperand(1);
+  bool isSigned = OpOpcode == ISD::SINT_TO_FP;
+
+  if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
+      !isConstVecPow2(ConstVec, isSigned, C))
+    return SDValue();
+
+  unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : 
+    Intrinsic::arm_neon_vcvtfxu2fp;
+  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
+                     Op.getValueType(),
+                     DAG.getConstant(IntrinsicOpcode, MVT::i32), 
+                     Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32));
+}
+
+/// Getvshiftimm - Check if this is a valid build_vector for the immediate
 /// operand of a vector shift operation, where all the elements of the
 /// build_vector must have the same constant integer value.
 static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
@@ -6868,6 +6968,9 @@
   case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
   case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
   case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
+  case ISD::FP_TO_SINT:
+  case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
+  case ISD::FDIV:       return PerformVDIVCombine(N, DCI, Subtarget);
   case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
   case ISD::SHL:
   case ISD::SRA:

Added: llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll?rev=133813&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll Fri Jun 24 14:23:04 2011
@@ -0,0 +1,99 @@
+; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
+
+ at in = global float 0x400921FA00000000, align 4
+
+; Test signed conversion.
+; CHECK: t0
+; CHECK-NOT: vmul
+define void @t0() nounwind {
+entry:
+  %tmp = load float* @in, align 4, !tbaa !0
+  %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
+  %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
+  %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00>
+  %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
+  tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
+  ret void
+}
+
+declare void @foo_int32x2_t(<2 x i32>)
+
+; Test unsigned conversion.
+; CHECK: t1
+; CHECK-NOT: vmul
+define void @t1() nounwind {
+entry:
+  %tmp = load float* @in, align 4, !tbaa !0
+  %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
+  %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
+  %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00>
+  %vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
+  tail call void @foo_uint32x2_t(<2 x i32> %vcvt.i) nounwind
+  ret void
+}
+
+declare void @foo_uint32x2_t(<2 x i32>)
+
+; Test which should not fold due to non-power of 2.
+; CHECK: t2
+; CHECK: vmul
+define void @t2() nounwind {
+entry:
+  %tmp = load float* @in, align 4, !tbaa !0
+  %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
+  %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
+  %mul.i = fmul <2 x float> %vecinit2.i, <float 0x401B333340000000, float 0x401B333340000000>
+  %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
+  tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
+  ret void
+}
+
+; Test which should not fold due to power of 2 out of range.
+; CHECK: t3
+; CHECK: vmul
+define void @t3() nounwind {
+entry:
+  %tmp = load float* @in, align 4, !tbaa !0
+  %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
+  %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
+  %mul.i = fmul <2 x float> %vecinit2.i, <float 0x4200000000000000, float 0x4200000000000000>
+  %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
+  tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
+  ret void
+}
+
+; Test which case where const is max power of 2 (i.e., 2^32).
+; CHECK: t4
+; CHECK-NOT: vmul
+define void @t4() nounwind {
+entry:
+  %tmp = load float* @in, align 4, !tbaa !0
+  %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
+  %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
+  %mul.i = fmul <2 x float> %vecinit2.i, <float 0x41F0000000000000, float 0x41F0000000000000>
+  %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
+  tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
+  ret void
+}
+
+; Test quadword.
+; CHECK: t5
+; CHECK-NOT: vmul
+define void @t5() nounwind {
+entry:
+  %tmp = load float* @in, align 4, !tbaa !0
+  %vecinit.i = insertelement <4 x float> undef, float %tmp, i32 0
+  %vecinit2.i = insertelement <4 x float> %vecinit.i, float %tmp, i32 1
+  %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %tmp, i32 2
+  %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %tmp, i32 3
+  %mul.i = fmul <4 x float> %vecinit6.i, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
+  %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32>
+  tail call void @foo_int32x4_t(<4 x i32> %vcvt.i) nounwind
+  ret void
+}
+
+declare void @foo_int32x4_t(<4 x i32>)
+
+!0 = metadata !{metadata !"float", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}

Added: llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll?rev=133813&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll Fri Jun 24 14:23:04 2011
@@ -0,0 +1,102 @@
+; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
+
+ at in = global float 0x400921FA00000000, align 4
+ at iin = global i32 -1023, align 4
+ at uin = global i32 1023, align 4
+
+declare void @foo_int32x4_t(<4 x i32>)
+
+; Test signed conversion.
+; CHECK: t1
+; CHECK-NOT: vdiv
+define void @t1() nounwind {
+entry:
+  %tmp = load i32* @iin, align 4, !tbaa !3
+  %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
+  %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
+  %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
+  %div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>
+  tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
+  ret void
+}
+
+declare void @foo_float32x2_t(<2 x float>)
+
+; Test unsigned conversion.
+; CHECK: t2
+; CHECK-NOT: vdiv
+define void @t2() nounwind {
+entry:
+  %tmp = load i32* @uin, align 4, !tbaa !3
+  %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
+  %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
+  %vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float>
+  %div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>
+  tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
+  ret void
+}
+
+; Test which should not fold due to non-power of 2.
+; CHECK: t3
+; CHECK: vdiv
+define void @t3() nounwind {
+entry:
+  %tmp = load i32* @iin, align 4, !tbaa !3
+  %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
+  %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
+  %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
+  %div.i = fdiv <2 x float> %vcvt.i, <float 0x401B333340000000, float 0x401B333340000000>
+  tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
+  ret void
+}
+
+; Test which should not fold due to power of 2 out of range.
+; CHECK: t4
+; CHECK: vdiv
+define void @t4() nounwind {
+entry:
+  %tmp = load i32* @iin, align 4, !tbaa !3
+  %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
+  %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
+  %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
+  %div.i = fdiv <2 x float> %vcvt.i, <float 0x4200000000000000, float 0x4200000000000000>
+  tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
+  ret void
+}
+
+; Test case where const is max power of 2 (i.e., 2^32).
+; CHECK: t5
+; CHECK-NOT: vdiv
+define void @t5() nounwind {
+entry:
+  %tmp = load i32* @iin, align 4, !tbaa !3
+  %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
+  %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
+  %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
+  %div.i = fdiv <2 x float> %vcvt.i, <float 0x41F0000000000000, float 0x41F0000000000000>
+  tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
+  ret void
+}
+
+; Test quadword.
+; CHECK: t6
+; CHECK-NOT: vdiv
+define void @t6() nounwind {
+entry:
+  %tmp = load i32* @iin, align 4, !tbaa !3
+  %vecinit.i = insertelement <4 x i32> undef, i32 %tmp, i32 0
+  %vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %tmp, i32 1
+  %vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %tmp, i32 2
+  %vecinit6.i = insertelement <4 x i32> %vecinit4.i, i32 %tmp, i32 3
+  %vcvt.i = sitofp <4 x i32> %vecinit6.i to <4 x float>
+  %div.i = fdiv <4 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
+  tail call void @foo_float32x4_t(<4 x float> %div.i) nounwind
+  ret void
+}
+
+declare void @foo_float32x4_t(<4 x float>)
+
+!0 = metadata !{metadata !"float", metadata !1}
+!1 = metadata !{metadata !"omnipotent char", metadata !2}
+!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
+!3 = metadata !{metadata !"int", metadata !1}



From dan at dneg.com  Fri Jun 24 14:27:10 2011
From: dan at dneg.com (Dan Bailey)
Date: Fri, 24 Jun 2011 19:27:10 -0000
Subject: [llvm-commits] [llvm] r133814 - in /llvm/trunk:
 lib/Target/PTX/PTXAsmPrinter.cpp lib/Target/PTX/PTXCallingConv.td
 lib/Target/PTX/PTXISelLowering.cpp lib/Target/PTX/PTXInstrInfo.cpp
 lib/Target/PTX/PTXInstrInfo.td lib/Target/PTX/PTXRegisterInfo.td
 lib/Target/PTX/generate-register-td.py test/CodeGen/PTX/cvt.ll
 test/CodeGen/PTX/ld.ll test/CodeGen/PTX/mov.ll test/CodeGen/PTX/st.ll
Message-ID: <20110624192710.812C72A6C12C@llvm.org>

Author: drb
Date: Fri Jun 24 14:27:10 2011
New Revision: 133814

URL: http://llvm.org/viewvc/llvm-project?rev=133814&view=rev
Log:
PTX: Add support for i8 type and introduce associated .b8 registers

The i8 type is required for boolean values, but can only use ld, st and mov instructions. The i1 type continues to be used for predicates.


Modified:
    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
    llvm/trunk/lib/Target/PTX/PTXCallingConv.td
    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
    llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td
    llvm/trunk/lib/Target/PTX/generate-register-td.py
    llvm/trunk/test/CodeGen/PTX/cvt.ll
    llvm/trunk/test/CodeGen/PTX/ld.ll
    llvm/trunk/test/CodeGen/PTX/mov.ll
    llvm/trunk/test/CodeGen/PTX/st.ll

Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133814&r1=133813&r2=133814&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Fri Jun 24 14:27:10 2011
@@ -92,6 +92,7 @@
 #define TEST_REGCLS(cls, clsstr)                \
   if (PTX::cls ## RegisterClass->contains(RegNo)) return # clsstr;
   TEST_REGCLS(RegPred, pred);
+  TEST_REGCLS(RegI8,  b8);
   TEST_REGCLS(RegI16, b16);
   TEST_REGCLS(RegI32, b32);
   TEST_REGCLS(RegI64, b64);
@@ -124,6 +125,7 @@
       case Type::IntegerTyID:
         switch (type->getPrimitiveSizeInBits()) {
           default: llvm_unreachable("Unknown integer bit-width");
+          case 8:  return ".u8";
           case 16: return ".u16";
           case 32: return ".u32";
           case 64: return ".u64";

Modified: llvm/trunk/lib/Target/PTX/PTXCallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXCallingConv.td?rev=133814&r1=133813&r2=133814&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXCallingConv.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXCallingConv.td Fri Jun 24 14:27:10 2011
@@ -15,6 +15,7 @@
 // PTX Formal Parameter Calling Convention
 def CC_PTX : CallingConv<[
   CCIfType<[i1],      CCAssignToReg<[P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, P36, P37, P38, P39, P40, P41, P42, P43, P44, P45, P46, P47, P48, P49, P50, P51, P52, P53, P54, P55, P56, P57, P58, P59, P60, P61, P62, P63, P64, P65, P66, P67, P68, P69, P70, P71, P72, P73, P74, P75, P76, P77, P78, P79, P80, P81, P82, P83, P84, P85, P86, P87, P88, P89, P90, P91, P92, P93, P94, P95, P96, P97, P98, P99, P100, P101, P102, P103, P104, P105, P106, P107, P108, P109, P110, P111, P112, P113, P114, P115, P116, P117, P118, P119, P120, P121, P122, P123, P124, P125, P126, P127]>>,
+  CCIfType<[i8],      CCAssignToReg<[RQ12, RQ13, RQ14, RQ15, RQ16, RQ17, RQ18, RQ19, RQ20, RQ21, RQ22, RQ23, RQ24, RQ25, RQ26, RQ27, RQ28, RQ29, RQ30, RQ31, RQ32, RQ33, RQ34, RQ35, RQ36, RQ37, RQ38, RQ39, RQ40, RQ41, RQ42, RQ43, RQ44, RQ45, RQ46, RQ47, RQ48, RQ49, RQ50, RQ51, RQ52, RQ53, RQ54, RQ55, RQ56, RQ57, RQ58, RQ59, RQ60, RQ61, RQ62, RQ63, RQ64, RQ65, RQ66, RQ67, RQ68, RQ69, RQ70, RQ71, RQ72, RQ73, RQ74, RQ75, RQ76, RQ77, RQ78, RQ79, RQ80, RQ81, RQ82, RQ83, RQ84, RQ85, RQ86, RQ87, RQ88, RQ89, RQ90, RQ91, RQ92, RQ93, RQ94, RQ95, RQ96, RQ97, RQ98, RQ99, RQ100, RQ101, RQ102, RQ103, RQ104, RQ105, RQ106, RQ107, RQ108, RQ109, RQ110, RQ111, RQ112, RQ113, RQ114, RQ115, RQ116, RQ117, RQ118, RQ119, RQ120, RQ121, RQ122, RQ123, RQ124, RQ125, RQ126, RQ127]>>,
   CCIfType<[i16],     CCAssignToReg<[RH12, RH13, RH14, RH15, RH16, RH17, RH18, RH19, RH20, RH21, RH22, RH23, RH24, RH25, RH26, RH27, RH28, RH29, RH30, RH31, RH32, RH33, RH34, RH35, RH36, RH37, RH38, RH39, RH40, RH41, RH42, RH43, RH44, RH45, RH46, RH47, RH48, RH49, RH50, RH51, RH52, RH53, RH54, RH55, RH56, RH57, RH58, RH59, RH60, RH61, RH62, RH63, RH64, RH65, RH66, RH67, RH68, RH69, RH70, RH71, RH72, RH73, RH74, RH75, RH76, RH77, RH78, RH79, RH80, RH81, RH82, RH83, RH84, RH85, RH86, RH87, RH88, RH89, RH90, RH91, RH92, RH93, RH94, RH95, RH96, RH97, RH98, RH99, RH100, RH101, RH102, RH103, RH104, RH105, RH106, RH107, RH108, RH109, RH110, RH111, RH112, RH113, RH114, RH115, RH116, RH117, RH118, RH119, RH120, RH121, RH122, RH123, RH124, RH125, RH126, RH127]>>,
   CCIfType<[i32,f32], CCAssignToReg<[R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127]>>,
   CCIfType<[i64,f64], CCAssignToReg<[RD12, RD13, RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26, RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35, RD36, RD37, RD38, RD39, RD40, RD41, RD42, RD43, RD44, RD45, RD46, RD47, RD48, RD49, RD50, RD51, RD52, RD53, RD54, RD55, RD56, RD57, RD58, RD59, RD60, RD61, RD62, RD63, RD64, RD65, RD66, RD67, RD68, RD69, RD70, RD71, RD72, RD73, RD74, RD75, RD76, RD77, RD78, RD79, RD80, RD81, RD82, RD83, RD84, RD85, RD86, RD87, RD88, RD89, RD90, RD91, RD92, RD93, RD94, RD95, RD96, RD97, RD98, RD99, RD100, RD101, RD102, RD103, RD104, RD105, RD106, RD107, RD108, RD109, RD110, RD111, RD112, RD113, RD114, RD115, RD116, RD117, RD118, RD119, RD120, RD121, RD122, RD123, RD124, RD125, RD126, RD127]>>
@@ -23,6 +24,7 @@
 // PTX Return Value Calling Convention
 def RetCC_PTX : CallingConv<[
   CCIfType<[i1],      CCAssignToReg<[P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11]>>,
+  CCIfType<[i8],      CCAssignToReg<[RQ0, RQ1, RQ2, RQ3, RQ4, RQ5, RQ6, RQ7, RQ8, RQ9, RQ10, RQ11]>>,
   CCIfType<[i16],     CCAssignToReg<[RH0, RH1, RH2, RH3, RH4, RH5, RH6, RH7, RH8, RH9, RH10, RH11]>>,
   CCIfType<[i32,f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11]>>,
   CCIfType<[i64,f64], CCAssignToReg<[RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11]>>

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=133814&r1=133813&r2=133814&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Fri Jun 24 14:27:10 2011
@@ -40,6 +40,7 @@
   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
   // Set up the register classes.
   addRegisterClass(MVT::i1,  PTX::RegPredRegisterClass);
+  addRegisterClass(MVT::i8,  PTX::RegI8RegisterClass);
   addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
   addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
   addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
@@ -52,10 +53,20 @@
 
   setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
   setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
-
+  
+  // Promote i1 type
+  setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
+  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+  
+  setTruncStoreAction(MVT::i8, MVT::i1, Promote);
+  
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+  
   // Turn i16 (z)extload into load + (z)extend
   setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
   setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
+  setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
 
   // Turn f32 extload into load + fextend
   setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
@@ -176,6 +187,7 @@
   bool operator==(MVT::SimpleValueType _VT) const { return VT == _VT; }
 } argmap[] = {
   argmap_entry(MVT::i1,  PTX::RegPredRegisterClass),
+  argmap_entry(MVT::i8,  PTX::RegI8RegisterClass),
   argmap_entry(MVT::i16, PTX::RegI16RegisterClass),
   argmap_entry(MVT::i32, PTX::RegI32RegisterClass),
   argmap_entry(MVT::i64, PTX::RegI64RegisterClass),
@@ -252,6 +264,9 @@
       if (RegVT == MVT::i1) {
         TRC = PTX::RegPredRegisterClass;
       }
+      else if (RegVT == MVT::i8) {
+        TRC = PTX::RegI8RegisterClass;
+      }
       else if (RegVT == MVT::i16) {
         TRC = PTX::RegI16RegisterClass;
       }

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=133814&r1=133813&r2=133814&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Fri Jun 24 14:27:10 2011
@@ -33,6 +33,7 @@
   const TargetRegisterClass *cls;
   const int opcode;
 } map[] = {
+  { &PTX::RegI8RegClass,  PTX::MOVU8rr },
   { &PTX::RegI16RegClass, PTX::MOVU16rr },
   { &PTX::RegI32RegClass, PTX::MOVU32rr },
   { &PTX::RegI64RegClass, PTX::MOVU64rr },
@@ -302,7 +303,9 @@
   int OpCode;
 
   // Select the appropriate opcode based on the register class
-  if (RC == PTX::RegI16RegisterClass) {
+  if (RC == PTX::RegI8RegisterClass) {
+    OpCode = PTX::STACKSTOREI8;
+  } else if (RC == PTX::RegI16RegisterClass) {
     OpCode = PTX::STACKSTOREI16;
   }  else if (RC == PTX::RegI32RegisterClass) {
     OpCode = PTX::STACKSTOREI32;
@@ -337,7 +340,9 @@
   int OpCode;
 
   // Select the appropriate opcode based on the register class
-  if (RC == PTX::RegI16RegisterClass) {
+  if (RC == PTX::RegI8RegisterClass) {
+    OpCode = PTX::STACKLOADI8;
+  } else if (RC == PTX::RegI16RegisterClass) {
     OpCode = PTX::STACKLOADI16;
   } else if (RC == PTX::RegI32RegisterClass) {
     OpCode = PTX::STACKLOADI32;

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=133814&r1=133813&r2=133814&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Fri Jun 24 14:27:10 2011
@@ -537,6 +537,7 @@
 }
 
 multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
+  defm u8  : PTX_LD<opstr, ".u8",  RegI8,  pat_load>;
   defm u16 : PTX_LD<opstr, ".u16", RegI16, pat_load>;
   defm u32 : PTX_LD<opstr, ".u32", RegI32, pat_load>;
   defm u64 : PTX_LD<opstr, ".u64", RegI64, pat_load>;
@@ -572,6 +573,7 @@
 }
 
 multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
+  defm u8  : PTX_ST<opstr, ".u8",  RegI8,  pat_store>;
   defm u16 : PTX_ST<opstr, ".u16", RegI16, pat_store>;
   defm u32 : PTX_ST<opstr, ".u32", RegI32, pat_store>;
   defm u64 : PTX_ST<opstr, ".u64", RegI64, pat_store>;
@@ -783,22 +785,27 @@
 let neverHasSideEffects = 1 in {
   def MOVPREDrr
     : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
+  def MOVU8rr
+    : InstPTX<(outs RegI8:$d),   (ins RegI8:$a),   "mov.u8\t$d, $a",  []>;
   def MOVU16rr
-    : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
+    : InstPTX<(outs RegI16:$d),  (ins RegI16:$a),  "mov.u16\t$d, $a", []>;
   def MOVU32rr
-    : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
+    : InstPTX<(outs RegI32:$d),  (ins RegI32:$a),  "mov.u32\t$d, $a", []>;
   def MOVU64rr
-    : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
+    : InstPTX<(outs RegI64:$d),  (ins RegI64:$a),  "mov.u64\t$d, $a", []>;
   def MOVF32rr
-    : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
+    : InstPTX<(outs RegF32:$d),  (ins RegF32:$a),  "mov.f32\t$d, $a", []>;
   def MOVF64rr
-    : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
+    : InstPTX<(outs RegF64:$d),  (ins RegF64:$a),  "mov.f64\t$d, $a", []>;
 }
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
   def MOVPREDri
     : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
               [(set RegPred:$d, imm:$a)]>;
+  def MOVU8ri
+    : InstPTX<(outs RegI8:$d),  (ins i8imm:$a),  "mov.u8\t$d, $a",
+              [(set RegI8:$d, imm:$a)]>;
   def MOVU16ri
     : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
               [(set RegI16:$d, imm:$a)]>;
@@ -838,6 +845,9 @@
   def LDpiPred : InstPTX<(outs RegPred:$d), (ins MEMpi:$a),
                          "ld.param.pred\t$d, [$a]",
                          [(set RegPred:$d, (PTXloadparam timm:$a))]>;
+  def LDpiU8   : InstPTX<(outs RegI8:$d), (ins MEMpi:$a),
+                         "ld.param.u8\t$d, [$a]",
+                         [(set RegI8:$d,  (PTXloadparam timm:$a))]>;
   def LDpiU16  : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
                          "ld.param.u16\t$d, [$a]",
                          [(set RegI16:$d, (PTXloadparam timm:$a))]>;
@@ -857,6 +867,9 @@
   def STpiPred : InstPTX<(outs), (ins MEMret:$d, RegPred:$a),
                          "st.param.pred\t[$d], $a",
                          [(PTXstoreparam timm:$d, RegPred:$a)]>;
+  def STpiU8   : InstPTX<(outs), (ins MEMret:$d, RegI8:$a),
+                         "st.param.u8\t[$d], $a",
+                         [(PTXstoreparam timm:$d, RegI8:$a)]>;
   def STpiU16  : InstPTX<(outs), (ins MEMret:$d, RegI16:$a),
                          "st.param.u16\t[$d], $a",
                          [(PTXstoreparam timm:$d, RegI16:$a)]>;
@@ -887,6 +900,10 @@
 // PTX does not directly support converting to a predicate type, so we fake it
 // by performing a greater-than test between the value and zero.  This follows
 // the C convention that any non-zero value is equivalent to 'true'.
+def CVT_pred_u8
+  : InstPTX<(outs RegPred:$d), (ins RegI8:$a), "setp.gt.b8\t$d, $a, 0",
+            [(set RegPred:$d, (trunc RegI8:$a))]>;
+
 def CVT_pred_u16
   : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.b16\t$d, $a, 0",
             [(set RegPred:$d, (trunc RegI16:$a))]>;
@@ -907,6 +924,34 @@
   : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.b64\t$d, $a, 0",
             [(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
 
+// Conversion to u8
+// PTX does not directly support converting a predicate to a value, so we
+// use a select instruction to select either 0 or 1 (integer or fp) based
+// on the truth value of the predicate.
+def CVT_u8_pred
+  : InstPTX<(outs RegI8:$d), (ins RegPred:$a), "selp.u8\t$d, 1, 0, $a",
+            [(set RegI8:$d, (zext RegPred:$a))]>;
+
+def CVT_u8_preds
+  : InstPTX<(outs RegI8:$d), (ins RegPred:$a), "selp.u8\t$d, 1, 0, $a",
+            [(set RegI8:$d, (sext RegPred:$a))]>;
+
+def CVT_u8_u32
+  : InstPTX<(outs RegI8:$d), (ins RegI32:$a), "cvt.u8.u32\t$d, $a",
+            [(set RegI8:$d, (trunc RegI32:$a))]>;
+
+def CVT_u8_u64
+  : InstPTX<(outs RegI8:$d), (ins RegI64:$a), "cvt.u8.u64\t$d, $a",
+            [(set RegI8:$d, (trunc RegI64:$a))]>;
+
+def CVT_u8_f32
+  : InstPTX<(outs RegI8:$d), (ins RegF32:$a), "cvt.rzi.u8.f32\t$d, $a",
+            [(set RegI8:$d, (fp_to_uint RegF32:$a))]>;
+
+def CVT_u8_f64
+  : InstPTX<(outs RegI8:$d), (ins RegF64:$a), "cvt.rzi.u8.f64\t$d, $a",
+            [(set RegI8:$d, (fp_to_uint RegF64:$a))]>;
+
 // Conversion to u16
 // PTX does not directly support converting a predicate to a value, so we
 // use a select instruction to select either 0 or 1 (integer or fp) based
@@ -915,6 +960,18 @@
   : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
             [(set RegI16:$d, (zext RegPred:$a))]>;
 
+def CVT_u16_preds
+  : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
+            [(set RegI16:$d, (sext RegPred:$a))]>;
+
+def CVT_u16_u8
+  : InstPTX<(outs RegI16:$d), (ins RegI8:$a), "cvt.u16.u8\t$d, $a",
+            [(set RegI16:$d, (zext RegI8:$a))]>;
+
+def CVT_u16_s8
+  : InstPTX<(outs RegI16:$d), (ins RegI8:$a), "cvt.u16.s8\t$d, $a",
+            [(set RegI16:$d, (sext RegI8:$a))]>;
+
 def CVT_u16_u32
   : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a",
             [(set RegI16:$d, (trunc RegI32:$a))]>;
@@ -937,10 +994,26 @@
   : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
             [(set RegI32:$d, (zext RegPred:$a))]>;
 
+def CVT_u32_u8
+  : InstPTX<(outs RegI32:$d), (ins RegI8:$a), "cvt.u32.u8\t$d, $a",
+            [(set RegI32:$d, (zext RegI8:$a))]>;
+
 def CVT_u32_u16
   : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
             [(set RegI32:$d, (zext RegI16:$a))]>;
 
+def CVT_u32_preds
+  : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
+            [(set RegI32:$d, (sext RegPred:$a))]>;
+
+def CVT_u32_s8
+  : InstPTX<(outs RegI32:$d), (ins RegI8:$a), "cvt.u32.s8\t$d, $a",
+            [(set RegI32:$d, (zext RegI8:$a))]>;
+
+def CVT_u32_s16
+  : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.s16\t$d, $a",
+            [(set RegI32:$d, (sext RegI16:$a))]>;
+
 def CVT_u32_u64
   : InstPTX<(outs RegI32:$d), (ins RegI64:$a), "cvt.u32.u64\t$d, $a",
             [(set RegI32:$d, (trunc RegI64:$a))]>;
@@ -959,6 +1032,10 @@
   : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
             [(set RegI64:$d, (zext RegPred:$a))]>;
 
+def CVT_u64_u8
+  : InstPTX<(outs RegI64:$d), (ins RegI8:$a), "cvt.u64.u8\t$d, $a",
+            [(set RegI64:$d, (zext RegI8:$a))]>;
+
 def CVT_u64_u16
   : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
             [(set RegI64:$d, (zext RegI16:$a))]>;
@@ -967,6 +1044,22 @@
   : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
             [(set RegI64:$d, (zext RegI32:$a))]>;
 
+def CVT_u64_preds
+  : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
+            [(set RegI64:$d, (sext RegPred:$a))]>;
+
+def CVT_u64_s8
+  : InstPTX<(outs RegI64:$d), (ins RegI8:$a), "cvt.u64.s8\t$d, $a",
+            [(set RegI64:$d, (zext RegI8:$a))]>;
+
+def CVT_u64_s16
+  : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.s16\t$d, $a",
+            [(set RegI64:$d, (sext RegI16:$a))]>;
+
+def CVT_u64_s32
+  : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.s32\t$d, $a",
+            [(set RegI64:$d, (sext RegI32:$a))]>;
+
 def CVT_u64_f32
   : InstPTX<(outs RegI64:$d), (ins RegF32:$a), "cvt.rzi.u64.f32\t$d, $a",
             [(set RegI64:$d, (fp_to_uint RegF32:$a))]>;
@@ -982,6 +1075,10 @@
             "selp.f32\t$d, 0F3F800000, 0F00000000, $a",  // 1.0
             [(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
 
+def CVT_f32_u8
+  : InstPTX<(outs RegF32:$d), (ins RegI8:$a), "cvt.rn.f32.u8\t$d, $a",
+            [(set RegF32:$d, (uint_to_fp RegI8:$a))]>;
+
 def CVT_f32_u16
   : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a",
             [(set RegF32:$d, (uint_to_fp RegI16:$a))]>;
@@ -1005,6 +1102,10 @@
             "selp.f64\t$d, 0D3F80000000000000, 0D0000000000000000, $a",  // 1.0
             [(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
 
+def CVT_f64_u8
+  : InstPTX<(outs RegF64:$d), (ins RegI8:$a), "cvt.rn.f64.u8\t$d, $a",
+            [(set RegF64:$d, (uint_to_fp RegI8:$a))]>;
+
 def CVT_f64_u16
   : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a",
             [(set RegF64:$d, (uint_to_fp RegI16:$a))]>;
@@ -1043,6 +1144,8 @@
 
 ///===- Spill Instructions ------------------------------------------------===//
 // Special instructions used for stack spilling
+def STACKSTOREI8  : InstPTX<(outs), (ins i32imm:$d, RegI8:$a),
+                            "mov.u8\ts$d, $a", []>;
 def STACKSTOREI16 : InstPTX<(outs), (ins i32imm:$d, RegI16:$a),
                             "mov.u16\ts$d, $a", []>;
 def STACKSTOREI32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
@@ -1054,6 +1157,8 @@
 def STACKSTOREF64 : InstPTX<(outs), (ins i32imm:$d, RegF64:$a),
                             "mov.f64\ts$d, $a", []>;
 
+def STACKLOADI8  : InstPTX<(outs), (ins RegI8:$d, i32imm:$a),
+                           "mov.u8\t$d, s$a", []>;
 def STACKLOADI16 : InstPTX<(outs), (ins RegI16:$d, i32imm:$a),
                            "mov.u16\t$d, s$a", []>;
 def STACKLOADI32 : InstPTX<(outs), (ins RegI32:$d, i32imm:$a),

Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td?rev=133814&r1=133813&r2=133814&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td Fri Jun 24 14:27:10 2011
@@ -151,6 +151,137 @@
 def P126 : PTXReg<"p126">;
 def P127 : PTXReg<"p127">;
 
+///===- 8-Bit Registers --------------------------------------------------===//
+
+def RQ0 : PTXReg<"rq0">;
+def RQ1 : PTXReg<"rq1">;
+def RQ2 : PTXReg<"rq2">;
+def RQ3 : PTXReg<"rq3">;
+def RQ4 : PTXReg<"rq4">;
+def RQ5 : PTXReg<"rq5">;
+def RQ6 : PTXReg<"rq6">;
+def RQ7 : PTXReg<"rq7">;
+def RQ8 : PTXReg<"rq8">;
+def RQ9 : PTXReg<"rq9">;
+def RQ10 : PTXReg<"rq10">;
+def RQ11 : PTXReg<"rq11">;
+def RQ12 : PTXReg<"rq12">;
+def RQ13 : PTXReg<"rq13">;
+def RQ14 : PTXReg<"rq14">;
+def RQ15 : PTXReg<"rq15">;
+def RQ16 : PTXReg<"rq16">;
+def RQ17 : PTXReg<"rq17">;
+def RQ18 : PTXReg<"rq18">;
+def RQ19 : PTXReg<"rq19">;
+def RQ20 : PTXReg<"rq20">;
+def RQ21 : PTXReg<"rq21">;
+def RQ22 : PTXReg<"rq22">;
+def RQ23 : PTXReg<"rq23">;
+def RQ24 : PTXReg<"rq24">;
+def RQ25 : PTXReg<"rq25">;
+def RQ26 : PTXReg<"rq26">;
+def RQ27 : PTXReg<"rq27">;
+def RQ28 : PTXReg<"rq28">;
+def RQ29 : PTXReg<"rq29">;
+def RQ30 : PTXReg<"rq30">;
+def RQ31 : PTXReg<"rq31">;
+def RQ32 : PTXReg<"rq32">;
+def RQ33 : PTXReg<"rq33">;
+def RQ34 : PTXReg<"rq34">;
+def RQ35 : PTXReg<"rq35">;
+def RQ36 : PTXReg<"rq36">;
+def RQ37 : PTXReg<"rq37">;
+def RQ38 : PTXReg<"rq38">;
+def RQ39 : PTXReg<"rq39">;
+def RQ40 : PTXReg<"rq40">;
+def RQ41 : PTXReg<"rq41">;
+def RQ42 : PTXReg<"rq42">;
+def RQ43 : PTXReg<"rq43">;
+def RQ44 : PTXReg<"rq44">;
+def RQ45 : PTXReg<"rq45">;
+def RQ46 : PTXReg<"rq46">;
+def RQ47 : PTXReg<"rq47">;
+def RQ48 : PTXReg<"rq48">;
+def RQ49 : PTXReg<"rq49">;
+def RQ50 : PTXReg<"rq50">;
+def RQ51 : PTXReg<"rq51">;
+def RQ52 : PTXReg<"rq52">;
+def RQ53 : PTXReg<"rq53">;
+def RQ54 : PTXReg<"rq54">;
+def RQ55 : PTXReg<"rq55">;
+def RQ56 : PTXReg<"rq56">;
+def RQ57 : PTXReg<"rq57">;
+def RQ58 : PTXReg<"rq58">;
+def RQ59 : PTXReg<"rq59">;
+def RQ60 : PTXReg<"rq60">;
+def RQ61 : PTXReg<"rq61">;
+def RQ62 : PTXReg<"rq62">;
+def RQ63 : PTXReg<"rq63">;
+def RQ64 : PTXReg<"rq64">;
+def RQ65 : PTXReg<"rq65">;
+def RQ66 : PTXReg<"rq66">;
+def RQ67 : PTXReg<"rq67">;
+def RQ68 : PTXReg<"rq68">;
+def RQ69 : PTXReg<"rq69">;
+def RQ70 : PTXReg<"rq70">;
+def RQ71 : PTXReg<"rq71">;
+def RQ72 : PTXReg<"rq72">;
+def RQ73 : PTXReg<"rq73">;
+def RQ74 : PTXReg<"rq74">;
+def RQ75 : PTXReg<"rq75">;
+def RQ76 : PTXReg<"rq76">;
+def RQ77 : PTXReg<"rq77">;
+def RQ78 : PTXReg<"rq78">;
+def RQ79 : PTXReg<"rq79">;
+def RQ80 : PTXReg<"rq80">;
+def RQ81 : PTXReg<"rq81">;
+def RQ82 : PTXReg<"rq82">;
+def RQ83 : PTXReg<"rq83">;
+def RQ84 : PTXReg<"rq84">;
+def RQ85 : PTXReg<"rq85">;
+def RQ86 : PTXReg<"rq86">;
+def RQ87 : PTXReg<"rq87">;
+def RQ88 : PTXReg<"rq88">;
+def RQ89 : PTXReg<"rq89">;
+def RQ90 : PTXReg<"rq90">;
+def RQ91 : PTXReg<"rq91">;
+def RQ92 : PTXReg<"rq92">;
+def RQ93 : PTXReg<"rq93">;
+def RQ94 : PTXReg<"rq94">;
+def RQ95 : PTXReg<"rq95">;
+def RQ96 : PTXReg<"rq96">;
+def RQ97 : PTXReg<"rq97">;
+def RQ98 : PTXReg<"rq98">;
+def RQ99 : PTXReg<"rq99">;
+def RQ100 : PTXReg<"rq100">;
+def RQ101 : PTXReg<"rq101">;
+def RQ102 : PTXReg<"rq102">;
+def RQ103 : PTXReg<"rq103">;
+def RQ104 : PTXReg<"rq104">;
+def RQ105 : PTXReg<"rq105">;
+def RQ106 : PTXReg<"rq106">;
+def RQ107 : PTXReg<"rq107">;
+def RQ108 : PTXReg<"rq108">;
+def RQ109 : PTXReg<"rq109">;
+def RQ110 : PTXReg<"rq110">;
+def RQ111 : PTXReg<"rq111">;
+def RQ112 : PTXReg<"rq112">;
+def RQ113 : PTXReg<"rq113">;
+def RQ114 : PTXReg<"rq114">;
+def RQ115 : PTXReg<"rq115">;
+def RQ116 : PTXReg<"rq116">;
+def RQ117 : PTXReg<"rq117">;
+def RQ118 : PTXReg<"rq118">;
+def RQ119 : PTXReg<"rq119">;
+def RQ120 : PTXReg<"rq120">;
+def RQ121 : PTXReg<"rq121">;
+def RQ122 : PTXReg<"rq122">;
+def RQ123 : PTXReg<"rq123">;
+def RQ124 : PTXReg<"rq124">;
+def RQ125 : PTXReg<"rq125">;
+def RQ126 : PTXReg<"rq126">;
+def RQ127 : PTXReg<"rq127">;
+
 ///===- 16-Bit Registers --------------------------------------------------===//
 
 def RH0 : PTXReg<"rh0">;
@@ -548,6 +679,7 @@
 //  Register classes
 //===----------------------------------------------------------------------===//
 def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%u", 0, 127)>;
+def RegI8  : RegisterClass<"PTX", [i8],  8, (sequence "RQ%u", 0, 127)>;
 def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%u", 0, 127)>;
 def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%u", 0, 127)>;
 def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%u", 0, 127)>;

Modified: llvm/trunk/lib/Target/PTX/generate-register-td.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/generate-register-td.py?rev=133814&r1=133813&r2=133814&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/generate-register-td.py (original)
+++ llvm/trunk/lib/Target/PTX/generate-register-td.py Fri Jun 24 14:27:10 2011
@@ -15,15 +15,16 @@
 from sys import argv, exit, stdout
 
 
-if len(argv) != 5:
-    print('Usage: generate-register-td.py <num_preds> <num_16> <num_32> <num_64>')
+if len(argv) != 6:
+    print('Usage: generate-register-td.py <num_preds> <num_8> <num_16> <num_32> <num_64>')
     exit(1)
 
 try:
     num_pred  = int(argv[1])
-    num_16bit = int(argv[2])
-    num_32bit = int(argv[3])
-    num_64bit = int(argv[4])
+    num_8bit  = int(argv[2])
+    num_16bit = int(argv[3])
+    num_32bit = int(argv[4])
+    num_64bit = int(argv[5])
 except:
     print('ERROR: Invalid integer parameter')
     exit(1)
@@ -60,6 +61,11 @@
 for r in range(0, num_pred):
     td_file.write('def P%d : PTXReg<"p%d">;\n' % (r, r))
 
+# Print 8-bit registers
+td_file.write('\n///===- 8-Bit Registers --------------------------------------------------===//\n\n')
+for r in range(0, num_8bit):
+    td_file.write('def RQ%d : PTXReg<"rq%d">;\n' % (r, r))
+
 # Print 16-bit registers
 td_file.write('\n///===- 16-Bit Registers --------------------------------------------------===//\n\n')
 for r in range(0, num_16bit):
@@ -86,6 +92,7 @@
 # Print register classes
 
 td_file.write('def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%%u", 0, %d)>;\n' % (num_pred-1))
+td_file.write('def RegI8  : RegisterClass<"PTX", [i8],  8, (sequence "RQ%%u", 0, %d)>;\n' % (num_8bit-1))
 td_file.write('def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%%u", 0, %d)>;\n' % (num_16bit-1))
 td_file.write('def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
 td_file.write('def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
@@ -101,16 +108,20 @@
 # Reserve 10% of the available registers for return values, and the other 90%
 # for parameters
 num_ret_pred    = int(0.1 * num_pred)
+num_ret_8bit    = int(0.1 * num_8bit)
 num_ret_16bit   = int(0.1 * num_16bit)
 num_ret_32bit   = int(0.1 * num_32bit)
 num_ret_64bit   = int(0.1 * num_64bit)
 num_param_pred  = num_pred - num_ret_pred
+num_param_8bit = num_8bit - num_ret_8bit
 num_param_16bit = num_16bit - num_ret_16bit
 num_param_32bit = num_32bit - num_ret_32bit
 num_param_64bit = num_64bit - num_ret_64bit
 
 param_regs_pred  = [('P%d' % (i+num_ret_pred)) for i in range(0, num_param_pred)]
 ret_regs_pred    = ['P%d' % i for i in range(0, num_ret_pred)]
+param_regs_8bit  = [('RQ%d' % (i+num_ret_8bit)) for i in range(0, num_param_8bit)]
+ret_regs_8bit    = ['RQ%d' % i for i in range(0, num_ret_8bit)]
 param_regs_16bit = [('RH%d' % (i+num_ret_16bit)) for i in range(0, num_param_16bit)]
 ret_regs_16bit   = ['RH%d' % i for i in range(0, num_ret_16bit)]
 param_regs_32bit = [('R%d' % (i+num_ret_32bit)) for i in range(0, num_param_32bit)]
@@ -120,6 +131,8 @@
 
 param_list_pred  = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_pred)
 ret_list_pred    = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_pred)
+param_list_8bit  = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_8bit)
+ret_list_8bit    = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_8bit)
 param_list_16bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_16bit)
 ret_list_16bit   = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_16bit)
 param_list_32bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_32bit)
@@ -144,6 +157,7 @@
 // PTX Formal Parameter Calling Convention
 def CC_PTX : CallingConv<[
   CCIfType<[i1],      CCAssignToReg<[%s]>>,
+  CCIfType<[i8],      CCAssignToReg<[%s]>>,
   CCIfType<[i16],     CCAssignToReg<[%s]>>,
   CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
   CCIfType<[i64,f64], CCAssignToReg<[%s]>>
@@ -152,12 +166,13 @@
 // PTX Return Value Calling Convention
 def RetCC_PTX : CallingConv<[
   CCIfType<[i1],      CCAssignToReg<[%s]>>,
+  CCIfType<[i8],      CCAssignToReg<[%s]>>,
   CCIfType<[i16],     CCAssignToReg<[%s]>>,
   CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
   CCIfType<[i64,f64], CCAssignToReg<[%s]>>
 ]>;
-''' % (param_list_pred, param_list_16bit, param_list_32bit, param_list_64bit,
-       ret_list_pred, ret_list_16bit, ret_list_32bit, ret_list_64bit))
+''' % (param_list_pred, param_list_8bit, param_list_16bit, param_list_32bit, param_list_64bit,
+       ret_list_pred, ret_list_8bit, ret_list_16bit, ret_list_32bit, ret_list_64bit))
 
 
 td_file.close()

Modified: llvm/trunk/test/CodeGen/PTX/cvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/cvt.ll?rev=133814&r1=133813&r2=133814&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/cvt.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/cvt.ll Fri Jun 24 14:27:10 2011
@@ -3,6 +3,17 @@
 ; preds 
 ; (note: we convert back to i32 to return)
 
+define ptx_device i32 @cvt_pred_i8(i8 %x, i1 %y) {
+; CHECK: setp.gt.b8 p[[P0:[0-9]+]], rq{{[0-9]+}}, 0
+; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
+; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
+; CHECK-NEXT: ret;
+	%a = trunc i8 %x to i1
+	%b = and i1 %a, %y
+	%c = zext i1 %b to i32
+	ret i32 %c
+}
+
 define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) {
 ; CHECK: setp.gt.b16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0
 ; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
@@ -58,6 +69,43 @@
 	ret i32 %c
 }
 
+; i8
+
+define ptx_device i8 @cvt_i8_preds(i1 %x) {
+; CHECK: selp.u8 rq{{[0-9]+}}, 1, 0, p{{[0-9]+}};
+; CHECK-NEXT: ret;
+	%a = zext i1 %x to i8
+	ret i8 %a
+}
+
+define ptx_device i8 @cvt_i8_i32(i32 %x) {
+; CHECK: cvt.u8.u32 rq{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: ret;
+	%a = trunc i32 %x to i8
+	ret i8 %a
+}
+
+define ptx_device i8 @cvt_i8_i64(i64 %x) {
+; CHECK: cvt.u8.u64 rq{{[0-9]+}}, rd{{[0-9]+}};
+; CHECK-NEXT: ret;
+	%a = trunc i64 %x to i8
+	ret i8 %a
+}
+
+define ptx_device i8 @cvt_i8_f32(float %x) {
+; CHECK: cvt.rzi.u8.f32 rq{{[0-9]+}}, r{{[0-9]+}};
+; CHECK-NEXT: ret;
+	%a = fptoui float %x to i8
+	ret i8 %a
+}
+
+define ptx_device i8 @cvt_i8_f64(double %x) {
+; CHECK: cvt.rzi.u8.f64 rq{{[0-9]+}}, rd{{[0-9]+}};
+; CHECK-NEXT: ret;
+	%a = fptoui double %x to i8
+	ret i8 %a
+}
+
 ; i16
 
 define ptx_device i16 @cvt_i16_preds(i1 %x) {
@@ -67,6 +115,13 @@
 	ret i16 %a
 }
 
+define ptx_device i16 @cvt_i16_i8(i8 %x) {
+; CHECK: cvt.u16.u8 rh{{[0-9]+}}, rq{{[0-9]+}};
+; CHECK-NEXT: ret;
+	%a = zext i8 %x to i16
+	ret i16 %a
+}
+
 define ptx_device i16 @cvt_i16_i32(i32 %x) {
 ; CHECK: cvt.u16.u32 rh{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
@@ -104,6 +159,13 @@
 	ret i32 %a
 }
 
+define ptx_device i32 @cvt_i32_i8(i8 %x) {
+; CHECK: cvt.u32.u8 r{{[0-9]+}}, rq{{[0-9]+}};
+; CHECK-NEXT: ret;
+	%a = zext i8 %x to i32
+	ret i32 %a
+}
+
 define ptx_device i32 @cvt_i32_i16(i16 %x) {
 ; CHECK: cvt.u32.u16 r{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
@@ -141,6 +203,13 @@
 	ret i64 %a
 }
 
+define ptx_device i64 @cvt_i64_i8(i8 %x) {
+; CHECK: cvt.u64.u8 rd{{[0-9]+}}, rq{{[0-9]+}};
+; CHECK-NEXT: ret;
+	%a = zext i8 %x to i64
+	ret i64 %a
+}
+
 define ptx_device i64 @cvt_i64_i16(i16 %x) {
 ; CHECK: cvt.u64.u16 rd{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
@@ -178,6 +247,13 @@
 	ret float %a
 }
 
+define ptx_device float @cvt_f32_i8(i8 %x) {
+; CHECK: cvt.rn.f32.u8 r{{[0-9]+}}, rq{{[0-9]+}};
+; CHECK-NEXT: ret;
+	%a = uitofp i8 %x to float
+	ret float %a
+}
+
 define ptx_device float @cvt_f32_i16(i16 %x) {
 ; CHECK: cvt.rn.f32.u16 r{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
@@ -215,6 +291,13 @@
 	ret double %a
 }
 
+define ptx_device double @cvt_f64_i8(i8 %x) {
+; CHECK: cvt.rn.f64.u8 rd{{[0-9]+}}, rq{{[0-9]+}};
+; CHECK-NEXT: ret;
+	%a = uitofp i8 %x to double
+	ret double %a
+}
+
 define ptx_device double @cvt_f64_i16(i16 %x) {
 ; CHECK: cvt.rn.f64.u16 rd{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;

Modified: llvm/trunk/test/CodeGen/PTX/ld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/ld.ll?rev=133814&r1=133813&r2=133814&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/ld.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/ld.ll Fri Jun 24 14:27:10 2011
@@ -1,5 +1,17 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
+;CHECK: .extern .global .b8 array_i8[10];
+ at array_i8 = external global [10 x i8]
+
+;CHECK: .extern .const .b8 array_constant_i8[10];
+ at array_constant_i8 = external addrspace(1) constant [10 x i8]
+
+;CHECK: .extern .local .b8 array_local_i8[10];
+ at array_local_i8 = external addrspace(2) global [10 x i8]
+
+;CHECK: .extern .shared .b8 array_shared_i8[10];
+ at array_shared_i8 = external addrspace(4) global [10 x i8]
+
 ;CHECK: .extern .global .b8 array_i16[20];
 @array_i16 = external global [10 x i16]
 
@@ -60,6 +72,13 @@
 ;CHECK: .extern .shared .b8 array_shared_double[80];
 @array_shared_double = external addrspace(4) global [10 x double]
 
+define ptx_device i8 @t1_u8(i8* %p) {
+entry:
+;CHECK: ld.global.u8 rq{{[0-9]+}}, [r{{[0-9]+}}];
+;CHECK-NEXT: ret;
+  %x = load i8* %p
+  ret i8 %x
+}
 
 define ptx_device i16 @t1_u16(i16* %p) {
 entry:
@@ -101,6 +120,15 @@
   ret double %x
 }
 
+define ptx_device i8 @t2_u8(i8* %p) {
+entry:
+;CHECK: ld.global.u8 rq{{[0-9]+}}, [r{{[0-9]+}}+1];
+;CHECK-NEXT: ret;
+  %i = getelementptr i8* %p, i32 1
+  %x = load i8* %i
+  ret i8 %x
+}
+
 define ptx_device i16 @t2_u16(i16* %p) {
 entry:
 ;CHECK: ld.global.u16 rh{{[0-9]+}}, [r{{[0-9]+}}+2];
@@ -146,6 +174,15 @@
   ret double %x
 }
 
+define ptx_device i8 @t3_u8(i8* %p, i32 %q) {
+entry:
+;CHECK: add.u32 r[[R0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]];
+  %i = getelementptr i8* %p, i32 %q
+  %x = load i8* %i
+  ret i8 %x
+}
+
 define ptx_device i16 @t3_u16(i16* %p, i32 %q) {
 entry:
 ;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 1;
@@ -196,6 +233,16 @@
   ret double %x
 }
 
+define ptx_device i8 @t4_global_u8() {
+entry:
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
+;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]];
+;CHECK-NEXT: ret;
+  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 0
+  %x = load i8* %i
+  ret i8 %x
+}
+
 define ptx_device i16 @t4_global_u16() {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
@@ -296,6 +343,16 @@
   ret double %x
 }
 
+define ptx_device i8 @t4_local_u8() {
+entry:
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i8;
+;CHECK-NEXT: ld.local.u8 rq{{[0-9]+}}, [r[[R0]]];
+;CHECK-NEXT: ret;
+  %i = getelementptr [10 x i8] addrspace(2)* @array_local_i8, i32 0, i32 0
+  %x = load i8 addrspace(2)* %i
+  ret i8 %x
+}
+
 define ptx_device i16 @t4_local_u16() {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i16;
@@ -346,6 +403,16 @@
   ret double %x
 }
 
+define ptx_device i8 @t4_shared_u8() {
+entry:
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i8;
+;CHECK-NEXT: ld.shared.u8 rq{{[0-9]+}}, [r[[R0]]];
+;CHECK-NEXT: ret;
+  %i = getelementptr [10 x i8] addrspace(4)* @array_shared_i8, i32 0, i32 0
+  %x = load i8 addrspace(4)* %i
+  ret i8 %x
+}
+
 define ptx_device i16 @t4_shared_u16() {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i16;
@@ -396,6 +463,16 @@
   ret double %x
 }
 
+define ptx_device i8 @t5_u8() {
+entry:
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
+;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]+1];
+;CHECK-NEXT: ret;
+  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 1
+  %x = load i8* %i
+  ret i8 %x
+}
+
 define ptx_device i16 @t5_u16() {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;

Modified: llvm/trunk/test/CodeGen/PTX/mov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mov.ll?rev=133814&r1=133813&r2=133814&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/mov.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/mov.ll Fri Jun 24 14:27:10 2011
@@ -1,5 +1,11 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
+define ptx_device i8 @t1_u8() {
+; CHECK: mov.u8 rq{{[0-9]+}}, 0;
+; CHECK: ret;
+	ret i8 0
+}
+
 define ptx_device i16 @t1_u16() {
 ; CHECK: mov.u16 rh{{[0-9]+}}, 0;
 ; CHECK: ret;
@@ -30,6 +36,12 @@
 	ret double 0.0
 }
 
+define ptx_device i8 @t2_u8(i8 %x) {
+; CHECK: mov.u8 rq{{[0-9]+}}, rq{{[0-9]+}};
+; CHECK: ret;
+	ret i8 %x
+}
+
 define ptx_device i16 @t2_u16(i16 %x) {
 ; CHECK: mov.u16 rh{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK: ret;

Modified: llvm/trunk/test/CodeGen/PTX/st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/st.ll?rev=133814&r1=133813&r2=133814&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/st.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/st.ll Fri Jun 24 14:27:10 2011
@@ -1,5 +1,17 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
+;CHECK: .extern .global .b8 array_i8[10];
+ at array_i8 = external global [10 x i8]
+
+;CHECK: .extern .const .b8 array_constant_i8[10];
+ at array_constant_i8 = external addrspace(1) constant [10 x i8]
+
+;CHECK: .extern .local .b8 array_local_i8[10];
+ at array_local_i8 = external addrspace(2) global [10 x i8]
+
+;CHECK: .extern .shared .b8 array_shared_i8[10];
+ at array_shared_i8 = external addrspace(4) global [10 x i8]
+
 ;CHECK: .extern .global .b8 array_i16[20];
 @array_i16 = external global [10 x i16]
 
@@ -60,6 +72,13 @@
 ;CHECK: .extern .shared .b8 array_shared_double[80];
 @array_shared_double = external addrspace(4) global [10 x double]
 
+define ptx_device void @t1_u8(i8* %p, i8 %x) {
+entry:
+;CHECK: st.global.u8 [r{{[0-9]+}}], rq{{[0-9]+}};
+;CHECK-NEXT: ret;
+  store i8 %x, i8* %p
+  ret void
+}
 
 define ptx_device void @t1_u16(i16* %p, i16 %x) {
 entry:
@@ -101,6 +120,15 @@
   ret void
 }
 
+define ptx_device void @t2_u8(i8* %p, i8 %x) {
+entry:
+;CHECK: st.global.u8 [r{{[0-9]+}}+1], rq{{[0-9]+}};
+;CHECK-NEXT: ret;
+  %i = getelementptr i8* %p, i32 1
+  store i8 %x, i8* %i
+  ret void
+}
+
 define ptx_device void @t2_u16(i16* %p, i16 %x) {
 entry:
 ;CHECK: st.global.u16 [r{{[0-9]+}}+2], rh{{[0-9]+}};
@@ -146,6 +174,16 @@
   ret void
 }
 
+define ptx_device void @t3_u8(i8* %p, i32 %q, i8 %x) {
+entry:
+;CHECK: add.u32 r[[R0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
+;CHECK-NEXT: st.global.u8 [r[[R0]]], rq{{[0-9]+}};
+;CHECK-NEXT: ret;
+  %i = getelementptr i8* %p, i32 %q
+  store i8 %x, i8* %i
+  ret void
+}
+
 define ptx_device void @t3_u16(i16* %p, i32 %q, i16 %x) {
 entry:
 ;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 1;
@@ -201,6 +239,16 @@
   ret void
 }
 
+define ptx_device void @t4_global_u8(i8 %x) {
+entry:
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
+;CHECK-NEXT: st.global.u8 [r[[R0]]], rq{{[0-9]+}};
+;CHECK-NEXT: ret;
+  %i = getelementptr [10 x i8]* @array_i8, i8 0, i8 0
+  store i8 %x, i8* %i
+  ret void
+}
+
 define ptx_device void @t4_global_u16(i16 %x) {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
@@ -251,6 +299,16 @@
   ret void
 }
 
+define ptx_device void @t4_local_u8(i8 %x) {
+entry:
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i8;
+;CHECK-NEXT: st.local.u8 [r[[R0]]], rq{{[0-9]+}};
+;CHECK-NEXT: ret;
+  %i = getelementptr [10 x i8] addrspace(2)* @array_local_i8, i32 0, i32 0
+  store i8 %x, i8 addrspace(2)* %i
+  ret void
+}
+
 define ptx_device void @t4_local_u16(i16 %x) {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i16;
@@ -301,6 +359,16 @@
   ret void
 }
 
+define ptx_device void @t4_shared_u8(i8 %x) {
+entry:
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i8;
+;CHECK-NEXT: st.shared.u8 [r[[R0]]], rq{{[0-9]+}};
+;CHECK-NEXT: ret;
+  %i = getelementptr [10 x i8] addrspace(4)* @array_shared_i8, i32 0, i32 0
+  store i8 %x, i8 addrspace(4)* %i
+  ret void
+}
+
 define ptx_device void @t4_shared_u16(i16 %x) {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i16;
@@ -351,6 +419,16 @@
   ret void
 }
 
+define ptx_device void @t5_u8(i8 %x) {
+entry:
+;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
+;CHECK-NEXT: st.global.u8 [r[[R0]]+1], rq{{[0-9]+}};
+;CHECK-NEXT: ret;
+  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 1
+  store i8 %x, i8* %i
+  ret void
+}
+
 define ptx_device void @t5_u16(i16 %x) {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;



From grosbach at apple.com  Fri Jun 24 14:43:28 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 24 Jun 2011 19:43:28 -0000
Subject: [llvm-commits] [llvm] r133815 -
	/llvm/trunk/lib/MC/MachObjectWriter.cpp
Message-ID: <20110624194328.1379C2A6C12C@llvm.org>

Author: grosbach
Date: Fri Jun 24 14:43:27 2011
New Revision: 133815

URL: http://llvm.org/viewvc/llvm-project?rev=133815&view=rev
Log:
tidy up whitespace.

Modified:
    llvm/trunk/lib/MC/MachObjectWriter.cpp

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=133815&r1=133814&r2=133815&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Fri Jun 24 14:43:27 2011
@@ -1098,7 +1098,7 @@
     RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);
     Log2Size = llvm::Log2_32(2);
     return true;
-      
+
   case ARM::fixup_t2_uncondbranch:
   case ARM::fixup_arm_thumb_bl:
   case ARM::fixup_arm_thumb_blx:



From grosbach at apple.com  Fri Jun 24 15:06:59 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 24 Jun 2011 20:06:59 -0000
Subject: [llvm-commits] [llvm] r133818 -
	/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
Message-ID: <20110624200659.724882A6C12C@llvm.org>

Author: grosbach
Date: Fri Jun 24 15:06:59 2011
New Revision: 133818

URL: http://llvm.org/viewvc/llvm-project?rev=133818&view=rev
Log:
ARM movw/movt fixups need to mask the high bits.

The fixup value comes in as the whole 32-bit value, so for the lo16 fixup,
the upper bits need to be masked off. Previously we assumed the masking had
already been done and asserted.

rdar://9635991

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp?rev=133818&r1=133817&r2=133818&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmBackend.cpp Fri Jun 24 15:06:59 2011
@@ -174,7 +174,8 @@
     Value >>= 16;
     // Fallthrough
   case ARM::fixup_t2_movw_lo16:
-  case ARM::fixup_t2_movt_hi16_pcrel:
+  case ARM::fixup_t2_movt_hi16_pcrel:  //FIXME: Shouldn't this be shifted like
+                                       // the other hi16 fixup?
   case ARM::fixup_t2_movw_lo16_pcrel: {
     unsigned Hi4 = (Value & 0xF000) >> 12;
     unsigned i = (Value & 0x800) >> 11;
@@ -184,8 +185,10 @@
     // inst{26} = i;
     // inst{14-12} = Mid3;
     // inst{7-0} = Lo8;
-    assert ((((int64_t)Value) >= -0x8000) && (((int64_t)Value) <= 0x7fff) &&
-            "Out of range pc-relative fixup value!");
+    // The value comes in as the whole thing, not just the portion required
+    // for this fixup, so we need to mask off the bits not handled by this
+    // portion (lo vs. hi).
+    Value &= 0xffff;
     Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8);
     uint64_t swapped = (Value & 0xFFFF0000) >> 16;
     swapped |= (Value & 0x0000FFFF) << 16;



From evan.cheng at apple.com  Fri Jun 24 15:42:09 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Jun 2011 20:42:09 -0000
Subject: [llvm-commits] [llvm] r133820 - in /llvm/trunk:
 include/llvm/MC/MCRegisterInfo.h include/llvm/Target/TargetRegisterInfo.h
 include/llvm/Target/TargetRegistry.h
 lib/Target/X86/TargetDesc/X86TargetDesc.cpp
 lib/Target/X86/TargetDesc/X86TargetDesc.h
 utils/TableGen/RegisterInfoEmitter.cpp
Message-ID: <20110624204209.54C652A6C12C@llvm.org>

Author: evancheng
Date: Fri Jun 24 15:42:09 2011
New Revision: 133820

URL: http://llvm.org/viewvc/llvm-project?rev=133820&view=rev
Log:
- Add MCRegisterInfo registration machinery. Also added x86 registration routines.
- Rename TargetRegisterDesc to MCRegisterDesc.

Modified:
    llvm/trunk/include/llvm/MC/MCRegisterInfo.h
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/include/llvm/Target/TargetRegistry.h
    llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp
    llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/MC/MCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCRegisterInfo.h?rev=133820&r1=133819&r2=133820&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Fri Jun 24 15:42:09 2011
@@ -30,7 +30,7 @@
 /// super-registers of the specific register, e.g. RAX, EAX, are super-registers
 /// of AX.
 ///
-struct TargetRegisterDesc {
+struct MCRegisterDesc {
   const char     *Name;         // Printable name for the reg (for debugging)
   const unsigned *Overlaps;     // Overlapping registers, described above
   const unsigned *SubRegs;      // Sub-register set, described above
@@ -43,20 +43,26 @@
 /// to this array so that we can turn register number into a register
 /// descriptor.
 ///
+/// Note this class is designed to be a base class of TargetRegisterInfo, which
+/// is the interface used by codegen. However, specific targets *should never*
+/// specialize this class. MCRegisterInfo should only contain getters to access
+/// TableGen generated physical register data. It must not be extended with
+/// virtual methods.
+///
 class MCRegisterInfo {
 private:
-  const TargetRegisterDesc *Desc;             // Pointer to the descriptor array
+  const MCRegisterDesc *Desc;             // Pointer to the descriptor array
   unsigned NumRegs;                           // Number of entries in the array
 
 public:
   /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
   /// auto-generated routines. *DO NOT USE*.
-  void InitMCRegisterInfo(const TargetRegisterDesc *D, unsigned NR) {
+  void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR) {
     Desc = D;
     NumRegs = NR;
   }
     
-  const TargetRegisterDesc &operator[](unsigned RegNo) const {
+  const MCRegisterDesc &operator[](unsigned RegNo) const {
     assert(RegNo < NumRegs &&
            "Attempting to access record for invalid register number!");
     return Desc[RegNo];
@@ -65,7 +71,7 @@
   /// Provide a get method, equivalent to [], but more useful if we have a
   /// pointer to this object.
   ///
-  const TargetRegisterDesc &get(unsigned RegNo) const {
+  const MCRegisterDesc &get(unsigned RegNo) const {
     return operator[](RegNo);
   }
 

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=133820&r1=133819&r2=133820&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Jun 24 15:42:09 2011
@@ -256,6 +256,9 @@
   bool isAllocatable() const { return Allocatable; }
 };
 
+/// TargetRegisterDesc - It's just an alias of MCRegisterDesc.
+typedef MCRegisterDesc TargetRegisterDesc;
+
 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
 /// registers. These are used by codegen, not by MC.
 struct TargetRegisterInfoDesc {

Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=133820&r1=133819&r2=133820&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegistry.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegistry.h Fri Jun 24 15:42:09 2011
@@ -66,8 +66,7 @@
 
     typedef MCAsmInfo *(*AsmInfoCtorFnTy)(const Target &T,
                                           StringRef TT);
-    typedef MCRegisterInfo *(*RegInfoCtorFnTy)(const Target &T,
-                                               StringRef TT);
+    typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
     typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
                                                   const std::string &TT,
                                                   const std::string &Features);
@@ -127,9 +126,9 @@
     /// registered.
     AsmInfoCtorFnTy AsmInfoCtorFn;
 
-    /// RegInfoCtorFn - Constructor function for this target's MCRegisterInfo,
+    /// MCRegInfoCtorFn - Constructor function for this target's MCRegisterInfo,
     /// if registered.
-    RegInfoCtorFnTy RegInfoCtorFn;
+    MCRegInfoCtorFnTy MCRegInfoCtorFn;
 
     /// TargetMachineCtorFn - Construction function for this target's
     /// TargetMachine, if registered.
@@ -240,17 +239,12 @@
       return AsmInfoCtorFn(*this, Triple);
     }
 
-    /// createRegInfo - Create a MCRegisterInfo implementation for the specified
-    /// target triple.
+    /// createMCRegInfo - Create a MCRegisterInfo implementation.
     ///
-    /// \arg Triple - This argument is used to determine the target machine
-    /// feature set; it should always be provided. Generally this should be
-    /// either the target triple from the module, or the target triple of the
-    /// host if that does not exist.
-    MCRegisterInfo *createRegInfo(StringRef Triple) const {
-      if (!RegInfoCtorFn)
+    MCRegisterInfo *createMCRegInfo() const {
+      if (!MCRegInfoCtorFn)
         return 0;
-      return RegInfoCtorFn(*this, Triple);
+      return MCRegInfoCtorFn();
     }
 
     /// createTargetMachine - Create a target specific machine implementation
@@ -466,7 +460,7 @@
         T.AsmInfoCtorFn = Fn;
     }
 
-    /// RegisterRegInfo - Register a MCRegisterInfo implementation for the
+    /// RegisterMCRegInfo - Register a MCRegisterInfo implementation for the
     /// given target.
     ///
     /// Clients are responsible for ensuring that registration doesn't occur
@@ -475,10 +469,10 @@
     ///
     /// @param T - The target being registered.
     /// @param Fn - A function to construct a MCRegisterInfo for the target.
-    static void RegisterRegInfo(Target &T, Target::RegInfoCtorFnTy Fn) {
+    static void RegisterMCRegInfo(Target &T, Target::MCRegInfoCtorFnTy Fn) {
       // Ignore duplicate registration.
-      if (!T.RegInfoCtorFn)
-        T.RegInfoCtorFn = Fn;
+      if (!T.MCRegInfoCtorFn)
+        T.MCRegInfoCtorFn = Fn;
     }
 
     /// RegisterTargetMachine - Register a TargetMachine implementation for the
@@ -691,6 +685,38 @@
     }
   };
 
+  /// RegisterMCRegInfo - Helper template for registering a target register info
+  /// implementation.  This invokes the static "Create" method on the class to
+  /// actually do the construction.  Usage:
+  ///
+  /// extern "C" void LLVMInitializeFooTarget() {
+  ///   extern Target TheFooTarget;
+  ///   RegisterMCRegInfo<FooMCRegInfo> X(TheFooTarget);
+  /// }
+  template<class MCRegisterInfoImpl>
+  struct RegisterMCRegInfo {
+    RegisterMCRegInfo(Target &T) {
+      TargetRegistry::RegisterMCRegInfo(T, &Allocator);
+    }
+  private:
+    static MCRegisterInfo *Allocator() {
+      return new MCRegisterInfoImpl();
+    }
+  };
+
+  /// RegisterMCRegInfoFn - Helper template for registering a target register
+  /// info implementation.  This invokes the specified function to do the
+  /// construction.  Usage:
+  ///
+  /// extern "C" void LLVMInitializeFooTarget() {
+  ///   extern Target TheFooTarget;
+  ///   RegisterMCRegInfoFn X(TheFooTarget, TheFunction);
+  /// }
+  struct RegisterMCRegInfoFn {
+    RegisterMCRegInfoFn(Target &T, Target::MCRegInfoCtorFnTy Fn) {
+      TargetRegistry::RegisterMCRegInfo(T, Fn);
+    }
+  };
 
   /// RegisterTargetMachine - Helper template for registering a target machine
   /// implementation, for use in the target machine initialization

Modified: llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp?rev=133820&r1=133819&r2=133820&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp Fri Jun 24 15:42:09 2011
@@ -13,6 +13,7 @@
 
 #include "X86TargetDesc.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/Target/TargetRegistry.h"
 #include "X86GenRegisterDesc.inc"
 using namespace llvm;
 
@@ -21,3 +22,12 @@
   InitX86MCRegisterInfo(X);
   return X;
 }
+
+// Force static initialization.
+extern "C" void LLVMInitializeX86MCRegInfo() {
+  RegisterMCRegInfo<MCRegisterInfo> X(TheX86_32Target);
+  RegisterMCRegInfo<MCRegisterInfo> Y(TheX86_64Target);
+
+  TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
+  TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
+}

Modified: llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h?rev=133820&r1=133819&r2=133820&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h (original)
+++ llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h Fri Jun 24 15:42:09 2011
@@ -11,6 +11,12 @@
 //
 //===----------------------------------------------------------------------===//
 
+namespace llvm {
+class Target;
+
+extern Target TheX86_32Target, TheX86_64Target;
+} // End llvm namespace
+
 // Defines symbolic names for X86 registers.  This defines a mapping from
 // register name to register number.
 //

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=133820&r1=133819&r2=133820&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Jun 24 15:42:09 2011
@@ -631,7 +631,7 @@
   const std::string &TargetName = Target.getName();
   std::string ClassName = TargetName + "GenMCRegisterInfo";
   OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
-     << "  explicit " << ClassName << "(const TargetRegisterDesc *D);\n";
+     << "  explicit " << ClassName << "(const MCRegisterDesc *D);\n";
   OS << "};\n";
 
   OS << "\nnamespace {\n";
@@ -684,7 +684,7 @@
     OS << "0 };\n";
   }
 
-  OS << "\n  const TargetRegisterDesc " << TargetName
+  OS << "\n  const MCRegisterDesc " << TargetName
      << "RegDesc[] = { // Descriptors\n";
   OS << "    { \"NOREG\",\t0,\t0,\t0 },\n";
 



From mcrosier at apple.com  Fri Jun 24 15:51:38 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Fri, 24 Jun 2011 13:51:38 -0700
Subject: [llvm-commits] [llvm] r133813 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/vcvt_combine.ll
 test/CodeGen/ARM/vdiv_combine.ll
In-Reply-To: <20110624192304.BAAB22A6C12C@llvm.org>
References: <20110624192304.BAAB22A6C12C@llvm.org>
Message-ID: <3C9CE13B-F95B-4E59-B6CE-21D8B7EF8F93@apple.com>

This commit is for rdar://9603036.  The radar number was accidentally omitted in the svn commit message, so I thought it would be best to at least document it here.

 Chad

On Jun 24, 2011, at 12:23 PM, Chad Rosier wrote:

> Author: mcrosier
> Date: Fri Jun 24 14:23:04 2011
> New Revision: 133813
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133813&view=rev
> Log:
> The Neon VCVT (between floating-point and fixed-point, Advanced SIMD) 
> instructions can be used to match combinations of multiply/divide and VCVT 
> (between floating-point and integer, Advanced SIMD).  Basically the VCVT 
> immediate operand that specifies the number of fraction bits corresponds to a 
> floating-point multiply or divide by the corresponding power of 2.
> 
> For example, VCVT (floating-point to fixed-point, Advanced SIMD) can replace a 
> combination of VMUL and VCVT (floating-point to integer) as follows:
> 
> Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
>  vmul.f32        d16, d17, d16
>  vcvt.s32.f32    d16, d16
> becomes:
>  vcvt.s32.f32    d16, d16, #3
> 
> Similarly, VCVT (fixed-point to floating-point, Advanced SIMD) can replace a 
> combinations of VCVT (integer to floating-point) and VDIV as follows:
> 
> Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
>  vcvt.f32.s32    d16, d16
>  vdiv.f32        d16, d17, d16
> becomes:
>  vcvt.f32.s32    d16, d16, #3
> 
> Added:
>    llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll
>    llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=133813&r1=133812&r2=133813&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jun 24 14:23:04 2011
> @@ -506,6 +506,9 @@
>     setTargetDAGCombine(ISD::VECTOR_SHUFFLE);
>     setTargetDAGCombine(ISD::INSERT_VECTOR_ELT);
>     setTargetDAGCombine(ISD::STORE);
> +    setTargetDAGCombine(ISD::FP_TO_SINT);
> +    setTargetDAGCombine(ISD::FP_TO_UINT);
> +    setTargetDAGCombine(ISD::FDIV);
>   }
> 
>   computeRegisterProperties();
> @@ -6479,7 +6482,104 @@
>   return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op);
> }
> 
> -/// getVShiftImm - Check if this is a valid build_vector for the immediate
> +// isConstVecPow2 - Return true if each vector element is a power of 2, all 
> +// elements are the same constant, C, and Log2(C) ranges from 1 to 32.
> +static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C)
> +{
> +  integerPart c0, cN;
> +  for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements();
> +       I != E; I++) {
> +    ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(ConstVec.getOperand(I));
> +    if (!C)
> +      return false;
> +
> +    bool isExact;    
> +    APFloat APF = C->getValueAPF();
> +    if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact)
> +        != APFloat::opOK || !isExact)
> +      return false;
> +
> +    c0 = (I == 0) ? cN : c0;
> +    if (!isPowerOf2_64(cN) || c0 != cN || Log2_64(c0) < 1 || Log2_64(c0) > 32)
> +      return false;
> +  }
> +  C = c0;
> +  return true;
> +}
> +
> +/// PerformVCVTCombine - VCVT (floating-point to fixed-point, Advanced SIMD)
> +/// can replace combinations of VMUL and VCVT (floating-point to integer)
> +/// when the VMUL has a constant operand that is a power of 2.
> +///
> +/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
> +///  vmul.f32        d16, d17, d16
> +///  vcvt.s32.f32    d16, d16
> +/// becomes:
> +///  vcvt.s32.f32    d16, d16, #3
> +static SDValue PerformVCVTCombine(SDNode *N,
> +                                  TargetLowering::DAGCombinerInfo &DCI,
> +                                  const ARMSubtarget *Subtarget) {
> +  SelectionDAG &DAG = DCI.DAG;
> +  SDValue Op = N->getOperand(0);
> +
> +  if (!Subtarget->hasNEON() || !Op.getValueType().isVector() ||
> +      Op.getOpcode() != ISD::FMUL)
> +    return SDValue();
> +
> +  uint64_t C;
> +  SDValue N0 = Op->getOperand(0);
> +  SDValue ConstVec = Op->getOperand(1);
> +  bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
> +
> +  if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || 
> +      !isConstVecPow2(ConstVec, isSigned, C))
> +    return SDValue();
> +
> +  unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfp2fxs :
> +    Intrinsic::arm_neon_vcvtfp2fxu;
> +  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
> +                     N->getValueType(0),
> +                     DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, 
> +                     DAG.getConstant(Log2_64(C), MVT::i32));
> +}
> +
> +/// PerformVDIVCombine - VCVT (fixed-point to floating-point, Advanced SIMD)
> +/// can replace combinations of VCVT (integer to floating-point) and VDIV
> +/// when the VDIV has a constant operand that is a power of 2.
> +///
> +/// Example (assume d17 = <float 8.000000e+00, float 8.000000e+00>):
> +///  vcvt.f32.s32    d16, d16
> +///  vdiv.f32        d16, d17, d16
> +/// becomes:
> +///  vcvt.f32.s32    d16, d16, #3
> +static SDValue PerformVDIVCombine(SDNode *N,
> +                                  TargetLowering::DAGCombinerInfo &DCI,
> +                                  const ARMSubtarget *Subtarget) {
> +  SelectionDAG &DAG = DCI.DAG;
> +  SDValue Op = N->getOperand(0);
> +  unsigned OpOpcode = Op.getNode()->getOpcode();
> +
> +  if (!Subtarget->hasNEON() || !N->getValueType(0).isVector() ||
> +      (OpOpcode != ISD::SINT_TO_FP && OpOpcode != ISD::UINT_TO_FP))
> +    return SDValue();
> +
> +  uint64_t C;
> +  SDValue ConstVec = N->getOperand(1);
> +  bool isSigned = OpOpcode == ISD::SINT_TO_FP;
> +
> +  if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
> +      !isConstVecPow2(ConstVec, isSigned, C))
> +    return SDValue();
> +
> +  unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : 
> +    Intrinsic::arm_neon_vcvtfxu2fp;
> +  return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(),
> +                     Op.getValueType(),
> +                     DAG.getConstant(IntrinsicOpcode, MVT::i32), 
> +                     Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32));
> +}
> +
> +/// Getvshiftimm - Check if this is a valid build_vector for the immediate
> /// operand of a vector shift operation, where all the elements of the
> /// build_vector must have the same constant integer value.
> static bool getVShiftImm(SDValue Op, unsigned ElementBits, int64_t &Cnt) {
> @@ -6868,6 +6968,9 @@
>   case ISD::INSERT_VECTOR_ELT: return PerformInsertEltCombine(N, DCI);
>   case ISD::VECTOR_SHUFFLE: return PerformVECTOR_SHUFFLECombine(N, DCI.DAG);
>   case ARMISD::VDUPLANE: return PerformVDUPLANECombine(N, DCI);
> +  case ISD::FP_TO_SINT:
> +  case ISD::FP_TO_UINT: return PerformVCVTCombine(N, DCI, Subtarget);
> +  case ISD::FDIV:       return PerformVDIVCombine(N, DCI, Subtarget);
>   case ISD::INTRINSIC_WO_CHAIN: return PerformIntrinsicCombine(N, DCI.DAG);
>   case ISD::SHL:
>   case ISD::SRA:
> 
> Added: llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll?rev=133813&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/vcvt_combine.ll Fri Jun 24 14:23:04 2011
> @@ -0,0 +1,99 @@
> +; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
> +
> + at in = global float 0x400921FA00000000, align 4
> +
> +; Test signed conversion.
> +; CHECK: t0
> +; CHECK-NOT: vmul
> +define void @t0() nounwind {
> +entry:
> +  %tmp = load float* @in, align 4, !tbaa !0
> +  %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
> +  %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
> +  %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00>
> +  %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
> +  tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
> +  ret void
> +}
> +
> +declare void @foo_int32x2_t(<2 x i32>)
> +
> +; Test unsigned conversion.
> +; CHECK: t1
> +; CHECK-NOT: vmul
> +define void @t1() nounwind {
> +entry:
> +  %tmp = load float* @in, align 4, !tbaa !0
> +  %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
> +  %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
> +  %mul.i = fmul <2 x float> %vecinit2.i, <float 8.000000e+00, float 8.000000e+00>
> +  %vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
> +  tail call void @foo_uint32x2_t(<2 x i32> %vcvt.i) nounwind
> +  ret void
> +}
> +
> +declare void @foo_uint32x2_t(<2 x i32>)
> +
> +; Test which should not fold due to non-power of 2.
> +; CHECK: t2
> +; CHECK: vmul
> +define void @t2() nounwind {
> +entry:
> +  %tmp = load float* @in, align 4, !tbaa !0
> +  %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
> +  %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
> +  %mul.i = fmul <2 x float> %vecinit2.i, <float 0x401B333340000000, float 0x401B333340000000>
> +  %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
> +  tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
> +  ret void
> +}
> +
> +; Test which should not fold due to power of 2 out of range.
> +; CHECK: t3
> +; CHECK: vmul
> +define void @t3() nounwind {
> +entry:
> +  %tmp = load float* @in, align 4, !tbaa !0
> +  %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
> +  %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
> +  %mul.i = fmul <2 x float> %vecinit2.i, <float 0x4200000000000000, float 0x4200000000000000>
> +  %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
> +  tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
> +  ret void
> +}
> +
> +; Test which case where const is max power of 2 (i.e., 2^32).
> +; CHECK: t4
> +; CHECK-NOT: vmul
> +define void @t4() nounwind {
> +entry:
> +  %tmp = load float* @in, align 4, !tbaa !0
> +  %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
> +  %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
> +  %mul.i = fmul <2 x float> %vecinit2.i, <float 0x41F0000000000000, float 0x41F0000000000000>
> +  %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
> +  tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
> +  ret void
> +}
> +
> +; Test quadword.
> +; CHECK: t5
> +; CHECK-NOT: vmul
> +define void @t5() nounwind {
> +entry:
> +  %tmp = load float* @in, align 4, !tbaa !0
> +  %vecinit.i = insertelement <4 x float> undef, float %tmp, i32 0
> +  %vecinit2.i = insertelement <4 x float> %vecinit.i, float %tmp, i32 1
> +  %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %tmp, i32 2
> +  %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %tmp, i32 3
> +  %mul.i = fmul <4 x float> %vecinit6.i, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
> +  %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32>
> +  tail call void @foo_int32x4_t(<4 x i32> %vcvt.i) nounwind
> +  ret void
> +}
> +
> +declare void @foo_int32x4_t(<4 x i32>)
> +
> +!0 = metadata !{metadata !"float", metadata !1}
> +!1 = metadata !{metadata !"omnipotent char", metadata !2}
> +!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
> 
> Added: llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll?rev=133813&view=auto
> ==============================================================================
> --- llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll (added)
> +++ llvm/trunk/test/CodeGen/ARM/vdiv_combine.ll Fri Jun 24 14:23:04 2011
> @@ -0,0 +1,102 @@
> +; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
> +
> + at in = global float 0x400921FA00000000, align 4
> + at iin = global i32 -1023, align 4
> + at uin = global i32 1023, align 4
> +
> +declare void @foo_int32x4_t(<4 x i32>)
> +
> +; Test signed conversion.
> +; CHECK: t1
> +; CHECK-NOT: vdiv
> +define void @t1() nounwind {
> +entry:
> +  %tmp = load i32* @iin, align 4, !tbaa !3
> +  %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
> +  %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
> +  %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
> +  %div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>
> +  tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
> +  ret void
> +}
> +
> +declare void @foo_float32x2_t(<2 x float>)
> +
> +; Test unsigned conversion.
> +; CHECK: t2
> +; CHECK-NOT: vdiv
> +define void @t2() nounwind {
> +entry:
> +  %tmp = load i32* @uin, align 4, !tbaa !3
> +  %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
> +  %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
> +  %vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float>
> +  %div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>
> +  tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
> +  ret void
> +}
> +
> +; Test which should not fold due to non-power of 2.
> +; CHECK: t3
> +; CHECK: vdiv
> +define void @t3() nounwind {
> +entry:
> +  %tmp = load i32* @iin, align 4, !tbaa !3
> +  %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
> +  %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
> +  %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
> +  %div.i = fdiv <2 x float> %vcvt.i, <float 0x401B333340000000, float 0x401B333340000000>
> +  tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
> +  ret void
> +}
> +
> +; Test which should not fold due to power of 2 out of range.
> +; CHECK: t4
> +; CHECK: vdiv
> +define void @t4() nounwind {
> +entry:
> +  %tmp = load i32* @iin, align 4, !tbaa !3
> +  %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
> +  %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
> +  %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
> +  %div.i = fdiv <2 x float> %vcvt.i, <float 0x4200000000000000, float 0x4200000000000000>
> +  tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
> +  ret void
> +}
> +
> +; Test case where const is max power of 2 (i.e., 2^32).
> +; CHECK: t5
> +; CHECK-NOT: vdiv
> +define void @t5() nounwind {
> +entry:
> +  %tmp = load i32* @iin, align 4, !tbaa !3
> +  %vecinit.i = insertelement <2 x i32> undef, i32 %tmp, i32 0
> +  %vecinit2.i = insertelement <2 x i32> %vecinit.i, i32 %tmp, i32 1
> +  %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
> +  %div.i = fdiv <2 x float> %vcvt.i, <float 0x41F0000000000000, float 0x41F0000000000000>
> +  tail call void @foo_float32x2_t(<2 x float> %div.i) nounwind
> +  ret void
> +}
> +
> +; Test quadword.
> +; CHECK: t6
> +; CHECK-NOT: vdiv
> +define void @t6() nounwind {
> +entry:
> +  %tmp = load i32* @iin, align 4, !tbaa !3
> +  %vecinit.i = insertelement <4 x i32> undef, i32 %tmp, i32 0
> +  %vecinit2.i = insertelement <4 x i32> %vecinit.i, i32 %tmp, i32 1
> +  %vecinit4.i = insertelement <4 x i32> %vecinit2.i, i32 %tmp, i32 2
> +  %vecinit6.i = insertelement <4 x i32> %vecinit4.i, i32 %tmp, i32 3
> +  %vcvt.i = sitofp <4 x i32> %vecinit6.i to <4 x float>
> +  %div.i = fdiv <4 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00, float 8.000000e+00, float 8.000000e+00>
> +  tail call void @foo_float32x4_t(<4 x float> %div.i) nounwind
> +  ret void
> +}
> +
> +declare void @foo_float32x4_t(<4 x float>)
> +
> +!0 = metadata !{metadata !"float", metadata !1}
> +!1 = metadata !{metadata !"omnipotent char", metadata !2}
> +!2 = metadata !{metadata !"Simple C/C++ TBAA", null}
> +!3 = metadata !{metadata !"int", metadata !1}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From dpatel at apple.com  Fri Jun 24 15:46:11 2011
From: dpatel at apple.com (Devang Patel)
Date: Fri, 24 Jun 2011 20:46:11 -0000
Subject: [llvm-commits] [llvm] r133821 - in /llvm/trunk:
 include/llvm/CodeGen/ lib/CodeGen/ lib/CodeGen/AsmPrinter/
 lib/CodeGen/SelectionDAG/ lib/VMCore/ test/CodeGen/Generic/
 test/CodeGen/X86/
Message-ID: <20110624204611.8534A2A6C12C@llvm.org>

Author: dpatel
Date: Fri Jun 24 15:46:11 2011
New Revision: 133821

URL: http://llvm.org/viewvc/llvm-project?rev=133821&view=rev
Log:
Handle debug info for  i128 constants.

Added:
    llvm/trunk/test/CodeGen/X86/dbg-i128-const.ll
Removed:
    llvm/trunk/test/CodeGen/Generic/legalize-dbg-value.ll
Modified:
    llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
    llvm/trunk/include/llvm/CodeGen/MachineOperand.h
    llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
    llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
    llvm/trunk/lib/CodeGen/MachineInstr.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
    llvm/trunk/lib/VMCore/AsmWriter.cpp
    llvm/trunk/lib/VMCore/DebugInfoProbe.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=133821&r1=133820&r2=133821&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Fri Jun 24 15:46:11 2011
@@ -77,6 +77,11 @@
     return *this;
   }
 
+  const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
+    MI->addOperand(MachineOperand::CreateCImm(Val));
+    return *this;
+  }
+
   const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
     MI->addOperand(MachineOperand::CreateFPImm(Val));
     return *this;

Modified: llvm/trunk/include/llvm/CodeGen/MachineOperand.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineOperand.h?rev=133821&r1=133820&r2=133821&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineOperand.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineOperand.h Fri Jun 24 15:46:11 2011
@@ -21,6 +21,7 @@
 
 class BlockAddress;
 class ConstantFP;
+class ConstantInt;
 class GlobalValue;
 class MachineBasicBlock;
 class MachineInstr;
@@ -38,6 +39,7 @@
   enum MachineOperandType {
     MO_Register,               ///< Register operand.
     MO_Immediate,              ///< Immediate operand
+    MO_CImmediate,             ///< Immediate >64bit operand
     MO_FPImmediate,            ///< Floating-point immediate operand
     MO_MachineBasicBlock,      ///< MachineBasicBlock reference
     MO_FrameIndex,             ///< Abstract Stack Frame Index
@@ -111,6 +113,7 @@
   union {
     MachineBasicBlock *MBB;   // For MO_MachineBasicBlock.
     const ConstantFP *CFP;    // For MO_FPImmediate.
+    const ConstantInt *CI;    // For MO_CImmediate. Integers > 64bit.
     int64_t ImmVal;           // For MO_Immediate.
     const MDNode *MD;         // For MO_Metadata.
     MCSymbol *Sym;            // For MO_MCSymbol
@@ -173,6 +176,8 @@
   bool isReg() const { return OpKind == MO_Register; }
   /// isImm - Tests if this is a MO_Immediate operand.
   bool isImm() const { return OpKind == MO_Immediate; }
+  /// isCImm - Test if t his is a MO_CImmediate operand.
+  bool isCImm() const { return OpKind == MO_CImmediate; }
   /// isFPImm - Tests if this is a MO_FPImmediate operand.
   bool isFPImm() const { return OpKind == MO_FPImmediate; }
   /// isMBB - Tests if this is a MO_MachineBasicBlock operand.
@@ -333,6 +338,11 @@
     return Contents.ImmVal;
   }
 
+  const ConstantInt *getCImm() const {
+    assert(isCImm() && "Wrong MachineOperand accessor");
+    return Contents.CI;
+  }
+
   const ConstantFP *getFPImm() const {
     assert(isFPImm() && "Wrong MachineOperand accessor");
     return Contents.CFP;
@@ -440,6 +450,12 @@
     return Op;
   }
 
+  static MachineOperand CreateCImm(const ConstantInt *CI) {
+    MachineOperand Op(MachineOperand::MO_CImmediate);
+    Op.Contents.CI = CI;
+    return Op;
+  }
+
   static MachineOperand CreateFPImm(const ConstantFP *CFP) {
     MachineOperand Op(MachineOperand::MO_FPImmediate);
     Op.Contents.CFP = CFP;

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp?rev=133821&r1=133820&r2=133821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/AsmPrinter.cpp Fri Jun 24 15:46:11 2011
@@ -575,6 +575,8 @@
     }
   } else if (MI->getOperand(0).isImm()) {
     OS << MI->getOperand(0).getImm();
+  } else if (MI->getOperand(0).isCImm()) {
+    MI->getOperand(0).getCImm()->getValue().print(OS, false /*isSigned*/);
   } else {
     assert(MI->getOperand(0).isReg() && "Unknown operand type");
     if (MI->getOperand(0).getReg() == 0) {

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp?rev=133821&r1=133820&r2=133821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp Fri Jun 24 15:46:11 2011
@@ -491,7 +491,7 @@
 }
 
 /// addConstantValue - Add constant value entry in variable DIE.
-bool CompileUnit::addConstantValue(DIE *Die, ConstantInt *CI,
+bool CompileUnit::addConstantValue(DIE *Die, const ConstantInt *CI,
                                    bool Unsigned) {
   unsigned CIBitWidth = CI->getBitWidth();
   if (CIBitWidth <= 64) {

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h?rev=133821&r1=133820&r2=133821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h Fri Jun 24 15:46:11 2011
@@ -181,7 +181,7 @@
 
   /// addConstantValue - Add constant value entry in variable DIE.
   bool addConstantValue(DIE *Die, const MachineOperand &MO, DIType Ty);
-  bool addConstantValue(DIE *Die, ConstantInt *CI, bool Unsigned);
+  bool addConstantValue(DIE *Die, const ConstantInt *CI, bool Unsigned);
 
   /// addConstantFPValue - Add constant value entry in variable DIE.
   bool addConstantFPValue(DIE *Die, const MachineOperand &MO);

Modified: llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp?rev=133821&r1=133820&r2=133821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp (original)
+++ llvm/trunk/lib/CodeGen/AsmPrinter/DwarfDebug.cpp Fri Jun 24 15:46:11 2011
@@ -618,6 +618,21 @@
   return ScopeDIE;
 }
 
+/// isUnsignedDIType - Return true if type encoding is unsigned.
+static bool isUnsignedDIType(DIType Ty) {
+  DIDerivedType DTy(Ty);
+  if (DTy.Verify())
+    return isUnsignedDIType(DTy.getTypeDerivedFrom());
+
+  DIBasicType BTy(Ty);
+  if (BTy.Verify()) {
+    unsigned Encoding = BTy.getEncoding();
+    if (Encoding == dwarf::DW_ATE_unsigned ||
+        Encoding == dwarf::DW_ATE_unsigned_char)
+      return true;
+  }
+  return false;
+}
 
 /// constructVariableDIE - Construct a DIE for the given DbgVariable.
 DIE *DwarfDebug::constructVariableDIE(DbgVariable *DV, DbgScope *Scope) {
@@ -718,6 +733,11 @@
       else if (DVInsn->getOperand(0).isFPImm())
         updated =
           VariableCU->addConstantFPValue(VariableDie, DVInsn->getOperand(0));
+      else if (DVInsn->getOperand(0).isCImm())
+        updated =
+          VariableCU->addConstantValue(VariableDie, 
+                                       DVInsn->getOperand(0).getCImm(),
+                                       isUnsignedDIType(DV->getType()));
     } else {
       VariableCU->addVariableAddress(DV, VariableDie, 
                                      Asm->getDebugValueLocation(DVInsn));
@@ -913,22 +933,6 @@
   return I->second;
 }
 
-/// isUnsignedDIType - Return true if type encoding is unsigned.
-static bool isUnsignedDIType(DIType Ty) {
-  DIDerivedType DTy(Ty);
-  if (DTy.Verify())
-    return isUnsignedDIType(DTy.getTypeDerivedFrom());
-
-  DIBasicType BTy(Ty);
-  if (BTy.Verify()) {
-    unsigned Encoding = BTy.getEncoding();
-    if (Encoding == dwarf::DW_ATE_unsigned ||
-        Encoding == dwarf::DW_ATE_unsigned_char)
-      return true;
-  }
-  return false;
-}
-
 // Return const exprssion if value is a GEP to access merged global
 // constant. e.g.
 // i8* getelementptr ({ i8, i8, i8, i8 }* @_MergedGlobals, i32 0, i32 0)
@@ -1017,7 +1021,7 @@
     } else {
       TheCU->addBlock(VariableDIE, dwarf::DW_AT_location, 0, Block);
     } 
-  } else if (ConstantInt *CI = 
+  } else if (const ConstantInt *CI = 
              dyn_cast_or_null<ConstantInt>(GV.getConstant()))
     TheCU->addConstantValue(VariableDIE, CI, isUnsignedDIType(GTy));
   else if (const ConstantExpr *CE = getMergedGlobalExpr(N->getOperand(11))) {

Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=133821&r1=133820&r2=133821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original)
+++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Fri Jun 24 15:46:11 2011
@@ -267,6 +267,9 @@
   case MachineOperand::MO_Immediate:
     OS << getImm();
     break;
+  case MachineOperand::MO_CImmediate:
+    getCImm()->getValue().print(OS, false);
+    break;
   case MachineOperand::MO_FPImmediate:
     if (getFPImm()->getType()->isFloatTy())
       OS << getFPImm()->getValueAPF().convertToFloat();

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=133821&r1=133820&r2=133821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Fri Jun 24 15:46:11 2011
@@ -556,9 +556,14 @@
         .addReg(0U).addImm(DI->getOffset())
         .addMetadata(DI->getVariable());
     } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
-      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
-        .addImm(CI->getZExtValue()).addImm(DI->getOffset())
-        .addMetadata(DI->getVariable());
+      if (CI->getBitWidth() > 64)
+        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
+          .addCImm(CI).addImm(DI->getOffset())
+          .addMetadata(DI->getVariable());
+      else 
+        BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
+          .addImm(CI->getZExtValue()).addImm(DI->getOffset())
+          .addMetadata(DI->getVariable());
     } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
         .addFPImm(CF).addImm(DI->getOffset())

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=133821&r1=133820&r2=133821&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Fri Jun 24 15:46:11 2011
@@ -616,12 +616,8 @@
   } else if (SD->getKind() == SDDbgValue::CONST) {
     const Value *V = SD->getConst();
     if (const ConstantInt *CI = dyn_cast<ConstantInt>(V)) {
-      // FIXME: SDDbgValue constants aren't updated with legalization, so it's 
-      // possible to have i128 constants in them at this point. Dwarf writer
-      // does not handle i128 constants at the moment so, as a crude workaround,
-      // just drop the debug info if this happens.
-      if (!CI->getValue().isSignedIntN(64))
-        MIB.addReg(0U);
+      if (CI->getBitWidth() > 64)
+        MIB.addCImm(CI);
       else
         MIB.addImm(CI->getSExtValue());
     } else if (const ConstantFP *CF = dyn_cast<ConstantFP>(V)) {

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=133821&r1=133820&r2=133821&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Fri Jun 24 15:46:11 2011
@@ -32,6 +32,7 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/CFG.h"
+#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Dwarf.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -41,6 +42,11 @@
 #include <cctype>
 using namespace llvm;
 
+static cl::opt<bool>
+EnableDebugInfoComment("enable-debug-info-comment", cl::Hidden,
+                       cl::desc("Enable debug info comments"));
+
+
 // Make virtual table appear in this compilation unit.
 AssemblyAnnotationWriter::~AssemblyAnnotationWriter() {}
 
@@ -1761,6 +1767,18 @@
   if (AnnotationWriter) AnnotationWriter->emitBasicBlockEndAnnot(BB, Out);
 }
 
+/// printDebugLoc - Print DebugLoc.
+static void printDebugLoc(const DebugLoc &DL, formatted_raw_ostream &OS) {
+  OS << DL.getLine() << ":" << DL.getCol();
+  if (MDNode *N = DL.getInlinedAt(getGlobalContext())) {
+    DebugLoc IDL = DebugLoc::getFromDILocation(N);
+    if (!IDL.isUnknown()) {
+      OS << "@";
+      printDebugLoc(IDL,OS);
+    }
+  }
+}
+
 /// printInfoComment - Print a little comment after the instruction indicating
 /// which slot it occupies.
 ///
@@ -1768,6 +1786,43 @@
   if (AnnotationWriter) {
     AnnotationWriter->printInfoComment(V, Out);
     return;
+  } else if (EnableDebugInfoComment) {
+    bool Padded = false;
+    if (const Instruction *I = dyn_cast<Instruction>(&V)) {
+      const DebugLoc &DL = I->getDebugLoc();
+      if (!DL.isUnknown()) {
+        if (!Padded) {
+          Out.PadToColumn(50);
+          Padded = true;
+          Out << ";";
+        }
+        Out << " [debug line = ";
+        printDebugLoc(DL,Out);
+        Out << "]";
+      }
+      if (const DbgDeclareInst *DDI = dyn_cast<DbgDeclareInst>(I)) {
+        const MDNode *Var = DDI->getVariable();
+        if (!Padded) {
+          Out.PadToColumn(50);
+          Padded = true;
+          Out << ";";
+        }
+        if (Var && Var->getNumOperands() >= 2)
+          if (MDString *MDS = dyn_cast_or_null<MDString>(Var->getOperand(2)))
+            Out << " [debug variable = " << MDS->getString() << "]";
+      }
+      else if (const DbgValueInst *DVI = dyn_cast<DbgValueInst>(I)) {
+        const MDNode *Var = DVI->getVariable();
+        if (!Padded) {
+          Out.PadToColumn(50);
+          Padded = true;
+          Out << ";";
+        }
+        if (Var && Var->getNumOperands() >= 2)
+          if (MDString *MDS = dyn_cast_or_null<MDString>(Var->getOperand(2)))
+            Out << " [debug variable = " << MDS->getString() << "]";
+      }
+    }
   }
 }
 

Modified: llvm/trunk/lib/VMCore/DebugInfoProbe.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/DebugInfoProbe.cpp?rev=133821&r1=133820&r2=133821&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/DebugInfoProbe.cpp (original)
+++ llvm/trunk/lib/VMCore/DebugInfoProbe.cpp Fri Jun 24 15:46:11 2011
@@ -53,6 +53,7 @@
     Function *TheFn;
     std::set<MDNode *> DbgVariables;
     std::set<Instruction *> MissingDebugLoc;
+    std::set<unsigned> LineNos;
   };
 }
 
@@ -66,14 +67,19 @@
 
   DbgVariables.clear();
   MissingDebugLoc.clear();
+  LineNos.clear();
   TheFn = &F;
 
   for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
     for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); 
          BI != BE; ++BI) {
-      if (!isa<PHINode>(BI) && BI->getDebugLoc().isUnknown())
-        MissingDebugLoc.insert(BI);
-      if (!isa<DbgInfoIntrinsic>(BI)) continue;
+      DebugLoc DL = BI->getDebugLoc();
+      if (DL.isUnknown()) {
+        if (!isa<PHINode>(BI))
+          MissingDebugLoc.insert(BI);
+      } else
+        LineNos.insert(DL.getLine());
+       if (!isa<DbgInfoIntrinsic>(BI)) continue;
       Value *Addr = NULL;
       MDNode *Node = NULL;
       if (DbgDeclareInst *DDI = dyn_cast<DbgDeclareInst>(BI)) {
@@ -114,16 +120,20 @@
   assert (TheFn == &F && "Invalid function to measure!");
 
   std::set<MDNode *>DbgVariables2;
+  std::set<unsigned>LineNos2;
   for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
     for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); 
          BI != BE; ++BI) {
-      if (!isa<PHINode>(BI) && BI->getDebugLoc().isUnknown() &&
-          MissingDebugLoc.count(BI) == 0) {
-        ++NumDbgLineLost;
-        DEBUG(dbgs() << "DebugInfoProbe (" << PassName << "): --- ");
-        DEBUG(BI->print(dbgs()));
-        DEBUG(dbgs() << "\n");
-      }
+      DebugLoc DL = BI->getDebugLoc();
+      if (DL.isUnknown()) {
+        if (!isa<PHINode>(BI) && MissingDebugLoc.count(BI) == 0) {
+          ++NumDbgLineLost;
+          DEBUG(dbgs() << "DebugInfoProbe (" << PassName << "): --- ");
+          DEBUG(BI->print(dbgs()));
+          DEBUG(dbgs() << "\n");
+        }
+      } else
+        LineNos2.insert(DL.getLine());
       if (!isa<DbgInfoIntrinsic>(BI)) continue;
       Value *Addr = NULL;
       MDNode *Node = NULL;
@@ -138,6 +148,12 @@
         DbgVariables2.insert(Node);
     }
 
+  for (std::set<unsigned>::iterator I = LineNos.begin(),
+         E = LineNos.end(); I != E; ++I) {
+    unsigned LNO = *I;
+    if (LineNos2.count(LNO) == 0)
+      DEBUG(dbgs() << "DebugInfoProbe dropping line number " << LNO << "\n");
+  }
   for (std::set<MDNode *>::iterator I = DbgVariables.begin(), 
          E = DbgVariables.end(); I != E; ++I) {
     if (DbgVariables2.count(*I) == 0 && (*I)->getNumOperands() >= 2) {

Removed: llvm/trunk/test/CodeGen/Generic/legalize-dbg-value.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Generic/legalize-dbg-value.ll?rev=133820&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Generic/legalize-dbg-value.ll (original)
+++ llvm/trunk/test/CodeGen/Generic/legalize-dbg-value.ll (removed)
@@ -1,25 +0,0 @@
-; RUN: llc < %s -o /dev/null
-
-; llvm.dbg.value instructions can have types which are not legal for the
-; target. CodeGen should handle this.
-
-define i128 @__mulvti3(i128 %a, i128 %b) nounwind {
-entry:
-  tail call void @llvm.dbg.value(metadata !0, i64 0, metadata !1), !dbg !11
-  unreachable
-}
-
-declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
-
-!0 = metadata !{i128 170141183460469231731687303715884105727} 
-!1 = metadata !{i32 524544, metadata !2, metadata !"MAX", metadata !4, i32 29, metadata !8} ; [ DW_TAG_auto_variable ]
-!2 = metadata !{i32 524299, metadata !3, i32 26, i32 0} ; [ DW_TAG_lexical_block ]
-!3 = metadata !{i32 524334, i32 0, metadata !4, metadata !"__mulvti3", metadata !"__mulvti3", metadata !"__mulvti3", metadata !4, i32 26, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
-!4 = metadata !{i32 524329, metadata !"mulvti3.c", metadata !"/Volumes/Sandbox/llvm/swb/Libcompiler_rt-6.roots/Libcompiler_rt-6/lib", metadata !5} ; [ DW_TAG_file_type ]
-!5 = metadata !{i32 524305, i32 0, i32 1, metadata !"mulvti3.c", metadata !"/Volumes/Sandbox/llvm/swb/Libcompiler_rt-6.roots/Libcompiler_rt-6/lib", metadata !"4.2.1 (Based on Apple Inc. build 5658) (LLVM build 2328)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
-!6 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
-!7 = metadata !{metadata !8, metadata !8, metadata !8}
-!8 = metadata !{i32 524310, metadata !4, metadata !"ti_int", metadata !9, i32 78, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ]
-!9 = metadata !{i32 524329, metadata !"int_lib.h", metadata !"/Volumes/Sandbox/llvm/swb/Libcompiler_rt-6.roots/Libcompiler_rt-6/lib", metadata !5} ; [ DW_TAG_file_type ]
-!10 = metadata !{i32 524324, metadata !4, metadata !"", metadata !4, i32 0, i64 128, i64 128, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
-!11 = metadata !{i32 29, i32 0, metadata !2, null}

Added: llvm/trunk/test/CodeGen/X86/dbg-i128-const.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-i128-const.ll?rev=133821&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/dbg-i128-const.ll (added)
+++ llvm/trunk/test/CodeGen/X86/dbg-i128-const.ll Fri Jun 24 15:46:11 2011
@@ -0,0 +1,26 @@
+; RUN: llc < %s | FileCheck %s
+
+; CHECK: DW_AT_const_value
+; CHECK-NEXT: 42
+
+define i128 @__foo(i128 %a, i128 %b) nounwind {
+entry:
+  tail call void @llvm.dbg.value(metadata !0, i64 0, metadata !1), !dbg !11
+  %add = add i128 %a, %b, !dbg !11
+  ret i128 %add, !dbg !11
+}
+
+declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
+
+!0 = metadata !{i128 42 }
+!1 = metadata !{i32 524544, metadata !2, metadata !"MAX", metadata !4, i32 29, metadata !8} ; [ DW_TAG_auto_variable ]
+!2 = metadata !{i32 524299, metadata !3, i32 26, i32 0} ; [ DW_TAG_lexical_block ]
+!3 = metadata !{i32 524334, i32 0, metadata !4, metadata !"__foo", metadata !"__foo", metadata !"__foo", metadata !4, i32 26, metadata !6, i1 false, i1 true, i32 0, i32 0, null, i1 false} ; [ DW_TAG_subprogram ]
+!4 = metadata !{i32 524329, metadata !"foo.c", metadata !"/tmp", metadata !5} ; [ DW_TAG_file_type ]
+!5 = metadata !{i32 524305, i32 0, i32 1, metadata !"foo.c", metadata !"/tmp", metadata !"clang", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
+!6 = metadata !{i32 524309, metadata !4, metadata !"", metadata !4, i32 0, i64 0, i64 0, i64 0, i32 0, null, metadata !7, i32 0, null} ; [ DW_TAG_subroutine_type ]
+!7 = metadata !{metadata !8, metadata !8, metadata !8}
+!8 = metadata !{i32 524310, metadata !4, metadata !"ti_int", metadata !9, i32 78, i64 0, i64 0, i64 0, i32 0, metadata !10} ; [ DW_TAG_typedef ]
+!9 = metadata !{i32 524329, metadata !"myint.h", metadata !"/tmp", metadata !5} ; [ DW_TAG_file_type ]
+!10 = metadata !{i32 524324, metadata !4, metadata !"", metadata !4, i32 0, i64 128, i64 128, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
+!11 = metadata !{i32 29, i32 0, metadata !2, null}



From dpatel at apple.com  Fri Jun 24 15:48:14 2011
From: dpatel at apple.com (Devang Patel)
Date: Fri, 24 Jun 2011 20:48:14 -0000
Subject: [llvm-commits] [llvm] r133822 - in /llvm/trunk/lib/VMCore:
	AsmWriter.cpp DebugInfoProbe.cpp
Message-ID: <20110624204814.945452A6C12C@llvm.org>

Author: dpatel
Date: Fri Jun 24 15:48:14 2011
New Revision: 133822

URL: http://llvm.org/viewvc/llvm-project?rev=133822&view=rev
Log:
Revert unintentional check-in.

Modified:
    llvm/trunk/lib/VMCore/AsmWriter.cpp
    llvm/trunk/lib/VMCore/DebugInfoProbe.cpp

Modified: llvm/trunk/lib/VMCore/AsmWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/AsmWriter.cpp?rev=133822&r1=133821&r2=133822&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/AsmWriter.cpp (original)
+++ llvm/trunk/lib/VMCore/AsmWriter.cpp Fri Jun 24 15:48:14 2011
@@ -32,7 +32,6 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/STLExtras.h"
 #include "llvm/Support/CFG.h"
-#include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Dwarf.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -42,11 +41,6 @@
 #include <cctype>
 using namespace llvm;
 
-static cl::opt<bool>
-EnableDebugInfoComment("enable-debug-info-comment", cl::Hidden,
-                       cl::desc("Enable debug info comments"));
-
-
 // Make virtual table appear in this compilation unit.
 AssemblyAnnotationWriter::~AssemblyAnnotationWriter() {}
 
@@ -1767,18 +1761,6 @@
   if (AnnotationWriter) AnnotationWriter->emitBasicBlockEndAnnot(BB, Out);
 }
 
-/// printDebugLoc - Print DebugLoc.
-static void printDebugLoc(const DebugLoc &DL, formatted_raw_ostream &OS) {
-  OS << DL.getLine() << ":" << DL.getCol();
-  if (MDNode *N = DL.getInlinedAt(getGlobalContext())) {
-    DebugLoc IDL = DebugLoc::getFromDILocation(N);
-    if (!IDL.isUnknown()) {
-      OS << "@";
-      printDebugLoc(IDL,OS);
-    }
-  }
-}
-
 /// printInfoComment - Print a little comment after the instruction indicating
 /// which slot it occupies.
 ///
@@ -1786,43 +1768,6 @@
   if (AnnotationWriter) {
     AnnotationWriter->printInfoComment(V, Out);
     return;
-  } else if (EnableDebugInfoComment) {
-    bool Padded = false;
-    if (const Instruction *I = dyn_cast<Instruction>(&V)) {
-      const DebugLoc &DL = I->getDebugLoc();
-      if (!DL.isUnknown()) {
-        if (!Padded) {
-          Out.PadToColumn(50);
-          Padded = true;
-          Out << ";";
-        }
-        Out << " [debug line = ";
-        printDebugLoc(DL,Out);
-        Out << "]";
-      }
-      if (const DbgDeclareInst *DDI = dyn_cast<DbgDeclareInst>(I)) {
-        const MDNode *Var = DDI->getVariable();
-        if (!Padded) {
-          Out.PadToColumn(50);
-          Padded = true;
-          Out << ";";
-        }
-        if (Var && Var->getNumOperands() >= 2)
-          if (MDString *MDS = dyn_cast_or_null<MDString>(Var->getOperand(2)))
-            Out << " [debug variable = " << MDS->getString() << "]";
-      }
-      else if (const DbgValueInst *DVI = dyn_cast<DbgValueInst>(I)) {
-        const MDNode *Var = DVI->getVariable();
-        if (!Padded) {
-          Out.PadToColumn(50);
-          Padded = true;
-          Out << ";";
-        }
-        if (Var && Var->getNumOperands() >= 2)
-          if (MDString *MDS = dyn_cast_or_null<MDString>(Var->getOperand(2)))
-            Out << " [debug variable = " << MDS->getString() << "]";
-      }
-    }
   }
 }
 

Modified: llvm/trunk/lib/VMCore/DebugInfoProbe.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/DebugInfoProbe.cpp?rev=133822&r1=133821&r2=133822&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/DebugInfoProbe.cpp (original)
+++ llvm/trunk/lib/VMCore/DebugInfoProbe.cpp Fri Jun 24 15:48:14 2011
@@ -53,7 +53,6 @@
     Function *TheFn;
     std::set<MDNode *> DbgVariables;
     std::set<Instruction *> MissingDebugLoc;
-    std::set<unsigned> LineNos;
   };
 }
 
@@ -67,19 +66,14 @@
 
   DbgVariables.clear();
   MissingDebugLoc.clear();
-  LineNos.clear();
   TheFn = &F;
 
   for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
     for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); 
          BI != BE; ++BI) {
-      DebugLoc DL = BI->getDebugLoc();
-      if (DL.isUnknown()) {
-        if (!isa<PHINode>(BI))
-          MissingDebugLoc.insert(BI);
-      } else
-        LineNos.insert(DL.getLine());
-       if (!isa<DbgInfoIntrinsic>(BI)) continue;
+      if (!isa<PHINode>(BI) && BI->getDebugLoc().isUnknown())
+        MissingDebugLoc.insert(BI);
+      if (!isa<DbgInfoIntrinsic>(BI)) continue;
       Value *Addr = NULL;
       MDNode *Node = NULL;
       if (DbgDeclareInst *DDI = dyn_cast<DbgDeclareInst>(BI)) {
@@ -120,20 +114,16 @@
   assert (TheFn == &F && "Invalid function to measure!");
 
   std::set<MDNode *>DbgVariables2;
-  std::set<unsigned>LineNos2;
   for (Function::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI)
     for (BasicBlock::iterator BI = FI->begin(), BE = FI->end(); 
          BI != BE; ++BI) {
-      DebugLoc DL = BI->getDebugLoc();
-      if (DL.isUnknown()) {
-        if (!isa<PHINode>(BI) && MissingDebugLoc.count(BI) == 0) {
-          ++NumDbgLineLost;
-          DEBUG(dbgs() << "DebugInfoProbe (" << PassName << "): --- ");
-          DEBUG(BI->print(dbgs()));
-          DEBUG(dbgs() << "\n");
-        }
-      } else
-        LineNos2.insert(DL.getLine());
+      if (!isa<PHINode>(BI) && BI->getDebugLoc().isUnknown() &&
+          MissingDebugLoc.count(BI) == 0) {
+        ++NumDbgLineLost;
+        DEBUG(dbgs() << "DebugInfoProbe (" << PassName << "): --- ");
+        DEBUG(BI->print(dbgs()));
+        DEBUG(dbgs() << "\n");
+      }
       if (!isa<DbgInfoIntrinsic>(BI)) continue;
       Value *Addr = NULL;
       MDNode *Node = NULL;
@@ -148,12 +138,6 @@
         DbgVariables2.insert(Node);
     }
 
-  for (std::set<unsigned>::iterator I = LineNos.begin(),
-         E = LineNos.end(); I != E; ++I) {
-    unsigned LNO = *I;
-    if (LineNos2.count(LNO) == 0)
-      DEBUG(dbgs() << "DebugInfoProbe dropping line number " << LNO << "\n");
-  }
   for (std::set<MDNode *>::iterator I = DbgVariables.begin(), 
          E = DbgVariables.end(); I != E; ++I) {
     if (DbgVariables2.count(*I) == 0 && (*I)->getNumOperands() >= 2) {



From grosbach at apple.com  Fri Jun 24 15:59:01 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 24 Jun 2011 20:59:01 -0000
Subject: [llvm-commits] [llvm] r133823 -
	/llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
Message-ID: <20110624205901.C88722A6C12C@llvm.org>

Author: grosbach
Date: Fri Jun 24 15:59:01 2011
New Revision: 133823

URL: http://llvm.org/viewvc/llvm-project?rev=133823&view=rev
Log:
Testcase for r133818

Added:
    llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s

Added: llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s?rev=133823&view=auto
==============================================================================
--- llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s (added)
+++ llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s Fri Jun 24 15:59:01 2011
@@ -0,0 +1,17 @@
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-apple-darwin10 -filetype=obj -o - < %s | macho-dump | FileCheck %s
+
+_fred:
+	movt	r3, :upper16:(_wilma-(LPC0_0+4))
+LPC0_0:
+
+_wilma:
+  .long 0
+
+@ CHECK:  ('_relocations', [
+@ CHECK:    # Relocation 0
+@ CHECK:    (('word-0', 0xb9000000),
+@ CHECK:     ('word-1', 0x4)),
+@ CHECK:    # Relocation 1
+@ CHECK:    (('word-0', 0xb100fffc),
+@ CHECK:     ('word-1', 0x4)),
+



From stoklund at 2pi.dk  Fri Jun 24 16:09:33 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 24 Jun 2011 14:09:33 -0700
Subject: [llvm-commits] [llvm] r133820 - in /llvm/trunk:
 include/llvm/MC/MCRegisterInfo.h include/llvm/Target/TargetRegisterInfo.h
 include/llvm/Target/TargetRegistry.h
 lib/Target/X86/TargetDesc/X86TargetDesc.cpp
 lib/Target/X86/TargetDesc/X86TargetDesc.h
 utils/TableGen/RegisterInfoEmitter.cpp
In-Reply-To: <20110624204209.54C652A6C12C@llvm.org>
References: <20110624204209.54C652A6C12C@llvm.org>
Message-ID: <5BD729A3-8606-46B8-A1BF-ED876875A2AA@2pi.dk>


On Jun 24, 2011, at 1:42 PM, Evan Cheng wrote:

> +/// TargetRegisterDesc - It's just an alias of MCRegisterDesc.
> +typedef MCRegisterDesc TargetRegisterDesc;
> +

I don't think there are many references to TargetRegisterDesc, you can probably just change all of them.

/jakob


From clattner at apple.com  Fri Jun 24 16:15:57 2011
From: clattner at apple.com (Chris Lattner)
Date: Fri, 24 Jun 2011 14:15:57 -0700
Subject: [llvm-commits] [llvm] r133782 - in /llvm/trunk: ./
 include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/Target/
 lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/
 lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/
 lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/
 lib/Target/X86/TargetDesc/ lib/Target/XCore/ utils/TableGen/
In-Reply-To: <20110624014442.9ECEB2A6C12C@llvm.org>
References: <20110624014442.9ECEB2A6C12C@llvm.org>
Message-ID: <2965F433-661A-4133-AB82-A5A36A22F271@apple.com>

On Jun 23, 2011, at 6:44 PM, Evan Cheng wrote:
> URL: http://llvm.org/viewvc/llvm-project?rev=133782&view=rev
> Log:
> Starting to refactor Target to separate out code that's needed to fully describe
> target machine from those that are only needed by codegen. The goal is to
> sink the essential target description into MC layer so we can start building
> MC based tools without needing to link in the entire codegen.
> 
> First step is to refactor TargetRegisterInfo. This patch added a base class
> MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
> separate register description from the rest of the stuff.



> +++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Thu Jun 23 20:44:41 2011
> 

Looks very nice!

> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Jun 23 20:44:41 2011
> @@ -39,6 +39,8 @@
> #include "llvm/ADT/BitVector.h"
> #include "llvm/ADT/SmallVector.h"
> #include "llvm/Support/CommandLine.h"
> +#include "ARMGenRegisterDesc.inc"
> +#include "ARMGenRegisterInfo.inc"

Can these two .inc files get merged?  It would be nice to have one tblgen output file for registers that contains everything in one file.  Basically all the -gen-register* tblgen backends can be merged to produce one output file.

> MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
> -  : MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
> +  : MBlazeGenRegisterInfo(MBlazeRegDesc, MBlazeRegInfoDesc,
> +                          MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
>     Subtarget(ST), TII(tii) {}

Incidentally, (and I know this isn't your fault) the ADJCALLSTACKDOWN stuff should be in InstrInfo, not register info :)

> +++ llvm/trunk/lib/Target/X86/TargetDesc/Makefile Thu Jun 23 20:44:41 2011
> @@ -0,0 +1,16 @@
> +##===- lib/Target/X86/TargetDesc/Makefile ------------------*- Makefile -*-===##

Random picky thing: should this be "X86/MCTargetDesc"?  That would make it very clearly part of the MC layer.

Overall, this is really great work,

-Chris

From mcrosier at apple.com  Fri Jun 24 16:15:36 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Fri, 24 Jun 2011 21:15:36 -0000
Subject: [llvm-commits] [llvm] r133824 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20110624211536.EE02E2A6C12C@llvm.org>

Author: mcrosier
Date: Fri Jun 24 16:15:36 2011
New Revision: 133824

URL: http://llvm.org/viewvc/llvm-project?rev=133824&view=rev
Log:
Hoist simple check above more complex checking to avoid unnecessary 
overheads.  No functional change intended.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=133824&r1=133823&r2=133824&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 24 16:15:36 2011
@@ -2556,6 +2556,11 @@
   if (isCalleeStructRet || isCallerStructRet)
     return false;
 
+  // An stdcall caller is expected to clean up its arguments; the callee
+  // isn't going to do that.
+  if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
+    return false;
+
   // Do not sibcall optimize vararg calls unless all arguments are passed via
   // registers.
   if (isVarArg && !Outs.empty()) {
@@ -2692,11 +2697,6 @@
     }
   }
 
-  // An stdcall caller is expected to clean up its arguments; the callee
-  // isn't going to do that.
-  if (!CCMatch && CallerCC==CallingConv::X86_StdCall)
-    return false;
-
   return true;
 }
 



From bob.wilson at apple.com  Fri Jun 24 16:32:40 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 24 Jun 2011 21:32:40 -0000
Subject: [llvm-commits] [llvm] r133825 -
	/llvm/trunk/utils/TableGen/NeonEmitter.cpp
Message-ID: <20110624213240.3E46F2A6C12C@llvm.org>

Author: bwilson
Date: Fri Jun 24 16:32:40 2011
New Revision: 133825

URL: http://llvm.org/viewvc/llvm-project?rev=133825&view=rev
Log:
Shorten some ARM builtin names by removing unnecessary "neon" prefix.

Modified:
    llvm/trunk/utils/TableGen/NeonEmitter.cpp

Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=133825&r1=133824&r2=133825&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Fri Jun 24 16:32:40 2011
@@ -889,7 +889,7 @@
   return ret;
 }
 
-// Generate the definition for this intrinsic, e.g. __builtin_neon_cls(a)
+// Generate the definition for this intrinsic.
 static std::string GenBuiltin(const std::string &name, const std::string &proto,
                               StringRef typestr, ClassKind ck) {
   std::string s;
@@ -923,7 +923,7 @@
 
   bool splat = proto.find('a') != std::string::npos;
 
-  s += "__builtin_neon_";
+  s += "__builtin_";
   if (splat) {
     // Call the non-splat builtin: chop off the "_n" suffix from the name.
     std::string vname(name, 0, name.size()-2);
@@ -1009,7 +1009,7 @@
 static std::string GenBuiltinDef(const std::string &name,
                                  const std::string &proto,
                                  StringRef typestr, ClassKind ck) {
-  std::string s("BUILTIN(__builtin_neon_");
+  std::string s("BUILTIN(__builtin_");
 
   // If all types are the same size, bitcasting the args will take care
   // of arg checking.  The actual signedness etc. will be taken care of with
@@ -1354,11 +1354,11 @@
       }
     }
     if (mask)
-      OS << "case ARM::BI__builtin_neon_"
+      OS << "case ARM::BI__builtin_"
          << MangleName(name, TypeVec[si], ClassB)
          << ": mask = " << "0x" << utohexstr(mask) << "; break;\n";
     if (qmask)
-      OS << "case ARM::BI__builtin_neon_"
+      OS << "case ARM::BI__builtin_"
          << MangleName(name, TypeVec[qi], ClassB)
          << ": mask = " << "0x" << utohexstr(qmask) << "; break;\n";
   }
@@ -1446,7 +1446,7 @@
           case 'i': ie = ii + 1; break;
         }
       }
-      OS << "case ARM::BI__builtin_neon_" << MangleName(name, TypeVec[ti], ck)
+      OS << "case ARM::BI__builtin_" << MangleName(name, TypeVec[ti], ck)
          << ": i = " << immidx << "; " << rangestr << "; break;\n";
     }
   }



From dpatel at apple.com  Fri Jun 24 17:00:39 2011
From: dpatel at apple.com (Devang Patel)
Date: Fri, 24 Jun 2011 22:00:39 -0000
Subject: [llvm-commits] [llvm] r133828 - in /llvm/trunk:
 include/llvm/Analysis/DIBuilder.h lib/Analysis/DIBuilder.cpp
Message-ID: <20110624220039.A05432A6C12C@llvm.org>

Author: dpatel
Date: Fri Jun 24 17:00:39 2011
New Revision: 133828

URL: http://llvm.org/viewvc/llvm-project?rev=133828&view=rev
Log:
Fix struct member's scope. Patch by Xi Wang.

Modified:
    llvm/trunk/include/llvm/Analysis/DIBuilder.h
    llvm/trunk/lib/Analysis/DIBuilder.cpp

Modified: llvm/trunk/include/llvm/Analysis/DIBuilder.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/DIBuilder.h?rev=133828&r1=133827&r2=133828&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Analysis/DIBuilder.h (original)
+++ llvm/trunk/include/llvm/Analysis/DIBuilder.h Fri Jun 24 17:00:39 2011
@@ -135,6 +135,7 @@
                              unsigned Flags);
 
     /// createMemberType - Create debugging information entry for a member.
+    /// @param Scope        Member scope.
     /// @param Name         Member name.
     /// @param File         File where this member is defined.
     /// @param LineNo       Line number.
@@ -143,7 +144,7 @@
     /// @param OffsetInBits Member offset.
     /// @param Flags        Flags to encode member attribute, e.g. private
     /// @param Ty           Parent type.
-    DIType createMemberType(StringRef Name, DIFile File,
+    DIType createMemberType(DIDescriptor Scope, StringRef Name, DIFile File,
                             unsigned LineNo, uint64_t SizeInBits, 
                             uint64_t AlignInBits, uint64_t OffsetInBits, 
                             unsigned Flags, DIType Ty);

Modified: llvm/trunk/lib/Analysis/DIBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/DIBuilder.cpp?rev=133828&r1=133827&r2=133828&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/DIBuilder.cpp (original)
+++ llvm/trunk/lib/Analysis/DIBuilder.cpp Fri Jun 24 17:00:39 2011
@@ -219,7 +219,7 @@
 }
 
 /// createMemberType - Create debugging information entry for a member.
-DIType DIBuilder::createMemberType(StringRef Name, 
+DIType DIBuilder::createMemberType(DIDescriptor Scope, StringRef Name, 
                                    DIFile File, unsigned LineNumber, 
                                    uint64_t SizeInBits, uint64_t AlignInBits,
                                    uint64_t OffsetInBits, unsigned Flags, 
@@ -227,7 +227,7 @@
   // TAG_member is encoded in DIDerivedType format.
   Value *Elts[] = {
     GetTagConstant(VMContext, dwarf::DW_TAG_member),
-    File, // Or TheCU ? Ty ?
+    Scope,
     MDString::get(VMContext, Name),
     File,
     ConstantInt::get(Type::getInt32Ty(VMContext), LineNumber),



From rafael.espindola at gmail.com  Fri Jun 24 17:01:28 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 24 Jun 2011 22:01:28 -0000
Subject: [llvm-commits] [llvm] r133830 - in /llvm/trunk:
 cmake/modules/LLVMLibDeps.cmake lib/Target/XCore/CMakeLists.txt
Message-ID: <20110624220128.75B782A6C12C@llvm.org>

Author: rafael
Date: Fri Jun 24 17:01:28 2011
New Revision: 133830

URL: http://llvm.org/viewvc/llvm-project?rev=133830&view=rev
Log:
Fix cmake build.

Modified:
    llvm/trunk/cmake/modules/LLVMLibDeps.cmake
    llvm/trunk/lib/Target/XCore/CMakeLists.txt

Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=133830&r1=133829&r2=133830&view=diff
==============================================================================
--- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original)
+++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Fri Jun 24 17:01:28 2011
@@ -42,7 +42,7 @@
 set(MSVC_LIB_DEPS_LLVMMipsCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMMipsInfo LLVMSelectionDAG LLVMSupport LLVMTarget)
 set(MSVC_LIB_DEPS_LLVMMipsInfo LLVMMC LLVMSupport)
 set(MSVC_LIB_DEPS_LLVMObject LLVMSupport)
-set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMTarget)
+set(MSVC_LIB_DEPS_LLVMPTXCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPTXInfo LLVMSelectionDAG LLVMSupport LLVMTarget)
 set(MSVC_LIB_DEPS_LLVMPTXInfo LLVMMC LLVMSupport)
 set(MSVC_LIB_DEPS_LLVMPowerPCAsmPrinter LLVMMC LLVMSupport)
 set(MSVC_LIB_DEPS_LLVMPowerPCCodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMPowerPCAsmPrinter LLVMPowerPCInfo LLVMSelectionDAG LLVMSupport LLVMTarget)

Modified: llvm/trunk/lib/Target/XCore/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/CMakeLists.txt?rev=133830&r1=133829&r2=133830&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/XCore/CMakeLists.txt Fri Jun 24 17:01:28 2011
@@ -1,5 +1,6 @@
 set(LLVM_TARGET_DEFINITIONS XCore.td)
 
+tablegen(XCoreGenRegisterNames.inc -gen-register-enums)
 tablegen(XCoreGenRegisterDesc.inc -gen-register-desc)
 tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header)
 tablegen(XCoreGenRegisterInfo.inc -gen-register-info)



From bob.wilson at apple.com  Fri Jun 24 17:13:18 2011
From: bob.wilson at apple.com (Bob Wilson)
Date: Fri, 24 Jun 2011 22:13:18 -0000
Subject: [llvm-commits] [llvm] r133832 -
	/llvm/trunk/utils/TableGen/NeonEmitter.cpp
Message-ID: <20110624221318.262AF2A6C12C@llvm.org>

Author: bwilson
Date: Fri Jun 24 17:13:17 2011
New Revision: 133832

URL: http://llvm.org/viewvc/llvm-project?rev=133832&view=rev
Log:
Revert "Shorten some ARM builtin names by removing unnecessary "neon" prefix."
Sorry, this was a bad idea.  Within clang these builtins are in a separate
"ARM" namespace, but the actual builtin names should clearly distinguish that
they are target specific.

Modified:
    llvm/trunk/utils/TableGen/NeonEmitter.cpp

Modified: llvm/trunk/utils/TableGen/NeonEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/NeonEmitter.cpp?rev=133832&r1=133831&r2=133832&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/NeonEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/NeonEmitter.cpp Fri Jun 24 17:13:17 2011
@@ -889,7 +889,7 @@
   return ret;
 }
 
-// Generate the definition for this intrinsic.
+// Generate the definition for this intrinsic, e.g. __builtin_neon_cls(a)
 static std::string GenBuiltin(const std::string &name, const std::string &proto,
                               StringRef typestr, ClassKind ck) {
   std::string s;
@@ -923,7 +923,7 @@
 
   bool splat = proto.find('a') != std::string::npos;
 
-  s += "__builtin_";
+  s += "__builtin_neon_";
   if (splat) {
     // Call the non-splat builtin: chop off the "_n" suffix from the name.
     std::string vname(name, 0, name.size()-2);
@@ -1009,7 +1009,7 @@
 static std::string GenBuiltinDef(const std::string &name,
                                  const std::string &proto,
                                  StringRef typestr, ClassKind ck) {
-  std::string s("BUILTIN(__builtin_");
+  std::string s("BUILTIN(__builtin_neon_");
 
   // If all types are the same size, bitcasting the args will take care
   // of arg checking.  The actual signedness etc. will be taken care of with
@@ -1354,11 +1354,11 @@
       }
     }
     if (mask)
-      OS << "case ARM::BI__builtin_"
+      OS << "case ARM::BI__builtin_neon_"
          << MangleName(name, TypeVec[si], ClassB)
          << ": mask = " << "0x" << utohexstr(mask) << "; break;\n";
     if (qmask)
-      OS << "case ARM::BI__builtin_"
+      OS << "case ARM::BI__builtin_neon_"
          << MangleName(name, TypeVec[qi], ClassB)
          << ": mask = " << "0x" << utohexstr(qmask) << "; break;\n";
   }
@@ -1446,7 +1446,7 @@
           case 'i': ie = ii + 1; break;
         }
       }
-      OS << "case ARM::BI__builtin_" << MangleName(name, TypeVec[ti], ck)
+      OS << "case ARM::BI__builtin_neon_" << MangleName(name, TypeVec[ti], ck)
          << ": i = " << immidx << "; " << rangestr << "; break;\n";
     }
   }



From clattner at apple.com  Fri Jun 24 17:35:43 2011
From: clattner at apple.com (Chris Lattner)
Date: Fri, 24 Jun 2011 15:35:43 -0700
Subject: [llvm-commits] [llvm] r133820 - in /llvm/trunk:
 include/llvm/MC/MCRegisterInfo.h include/llvm/Target/TargetRegisterInfo.h
 include/llvm/Target/TargetRegistry.h
 lib/Target/X86/TargetDesc/X86TargetDesc.cpp
 lib/Target/X86/TargetDesc/X86TargetDesc.h
 utils/TableGen/RegisterInfoEmitter.cpp
In-Reply-To: <5BD729A3-8606-46B8-A1BF-ED876875A2AA@2pi.dk>
References: <20110624204209.54C652A6C12C@llvm.org>
	<5BD729A3-8606-46B8-A1BF-ED876875A2AA@2pi.dk>
Message-ID: <CE41CF2C-993B-44B2-BECB-D10D07CB4A5B@apple.com>


On Jun 24, 2011, at 2:09 PM, Jakob Stoklund Olesen wrote:

> 
> On Jun 24, 2011, at 1:42 PM, Evan Cheng wrote:
> 
>> +/// TargetRegisterDesc - It's just an alias of MCRegisterDesc.
>> +typedef MCRegisterDesc TargetRegisterDesc;
>> +
> 
> I don't think there are many references to TargetRegisterDesc, you can probably just change all of them.

Yeah, please do.  Typedefs like this just make things harder to understand :)

-Chris

From resistor at mac.com  Fri Jun 24 18:02:22 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 24 Jun 2011 23:02:22 -0000
Subject: [llvm-commits] [llvm] r133838 -
	/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
Message-ID: <20110624230222.942B02A6C12C@llvm.org>

Author: resistor
Date: Fri Jun 24 18:02:22 2011
New Revision: 133838

URL: http://llvm.org/viewvc/llvm-project?rev=133838&view=rev
Log:
The scheduler needs to be aware on the existence of untyped nodes when it performs type propagation for EXTRACT_SUBREG.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=133838&r1=133837&r2=133838&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Fri Jun 24 18:02:22 2011
@@ -521,7 +521,8 @@
       if (!Node->hasAnyUseOfValue(DefIdx))
         continue;
       if (Node->isMachineOpcode() &&
-          Node->getMachineOpcode() == TargetOpcode::EXTRACT_SUBREG) {
+          Node->getMachineOpcode() == TargetOpcode::EXTRACT_SUBREG &&
+          Node->getOperand(0).getValueType() != MVT::untyped) {
         // Propagate the incoming (full-register) type. I doubt it's needed.
         ValueType = Node->getOperand(0).getValueType();
       }



From evan.cheng at apple.com  Fri Jun 24 18:48:46 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Jun 2011 16:48:46 -0700
Subject: [llvm-commits] [llvm] r133782 - in /llvm/trunk: ./
 include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/Target/
 lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/
 lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/
 lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/
 lib/Target/X86/TargetDesc/ lib/Target/XCore/ utils/TableGen/
In-Reply-To: <2965F433-661A-4133-AB82-A5A36A22F271@apple.com>
References: <20110624014442.9ECEB2A6C12C@llvm.org>
	<2965F433-661A-4133-AB82-A5A36A22F271@apple.com>
Message-ID: <9F0B4011-D1D7-480C-9FA5-AA7E61300643@apple.com>


On Jun 24, 2011, at 2:15 PM, Chris Lattner wrote:

> On Jun 23, 2011, at 6:44 PM, Evan Cheng wrote:
>> URL: http://llvm.org/viewvc/llvm-project?rev=133782&view=rev
>> Log:
>> Starting to refactor Target to separate out code that's needed to fully describe
>> target machine from those that are only needed by codegen. The goal is to
>> sink the essential target description into MC layer so we can start building
>> MC based tools without needing to link in the entire codegen.
>> 
>> First step is to refactor TargetRegisterInfo. This patch added a base class
>> MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
>> separate register description from the rest of the stuff.
> 
> 
> 
>> +++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Thu Jun 23 20:44:41 2011
>> 
> 
> Looks very nice!
> 
>> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Thu Jun 23 20:44:41 2011
>> @@ -39,6 +39,8 @@
>> #include "llvm/ADT/BitVector.h"
>> #include "llvm/ADT/SmallVector.h"
>> #include "llvm/Support/CommandLine.h"
>> +#include "ARMGenRegisterDesc.inc"
>> +#include "ARMGenRegisterInfo.inc"
> 
> Can these two .inc files get merged?  It would be nice to have one tblgen output file for registers that contains everything in one file.  Basically all the -gen-register* tblgen backends can be merged to produce one output file.

I'll deal with this later.

> 
>> MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii)
>> -  : MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
>> +  : MBlazeGenRegisterInfo(MBlazeRegDesc, MBlazeRegInfoDesc,
>> +                          MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
>>    Subtarget(ST), TII(tii) {}
> 
> Incidentally, (and I know this isn't your fault) the ADJCALLSTACKDOWN stuff should be in InstrInfo, not register info :)
> 
>> +++ llvm/trunk/lib/Target/X86/TargetDesc/Makefile Thu Jun 23 20:44:41 2011
>> @@ -0,0 +1,16 @@
>> +##===- lib/Target/X86/TargetDesc/Makefile ------------------*- Makefile -*-===##
> 
> Random picky thing: should this be "X86/MCTargetDesc"?  That would make it very clearly part of the MC layer.

Sure.

Evan

> 
> Overall, this is really great work,
> 
> -Chris


From grosbach at apple.com  Fri Jun 24 18:44:37 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 24 Jun 2011 23:44:37 -0000
Subject: [llvm-commits] [llvm] r133844 - in /llvm/trunk:
 include/llvm/MC/MCMachObjectWriter.h lib/MC/MachObjectWriter.cpp
 lib/Target/ARM/ARMMachObjectWriter.cpp lib/Target/PowerPC/PPCAsmBackend.cpp
 lib/Target/X86/X86MachObjectWriter.cpp
Message-ID: <20110624234437.6A95A2A6C12C@llvm.org>

Author: grosbach
Date: Fri Jun 24 18:44:37 2011
New Revision: 133844

URL: http://llvm.org/viewvc/llvm-project?rev=133844&view=rev
Log:
Refactor MachO relocation generaration into the Target directories.

Move the target-specific RecordRelocation logic out of the generic MC
MachObjectWriter and into the target-specific object writers. This allows
nuking quite a bit of target knowledge from the supposedly target-independent
bits in lib/MC.

Modified:
    llvm/trunk/include/llvm/MC/MCMachObjectWriter.h
    llvm/trunk/lib/MC/MachObjectWriter.cpp
    llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp
    llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
    llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp

Modified: llvm/trunk/include/llvm/MC/MCMachObjectWriter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCMachObjectWriter.h?rev=133844&r1=133843&r2=133844&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCMachObjectWriter.h (original)
+++ llvm/trunk/include/llvm/MC/MCMachObjectWriter.h Fri Jun 24 18:44:37 2011
@@ -10,11 +10,20 @@
 #ifndef LLVM_MC_MCMACHOBJECTWRITER_H
 #define LLVM_MC_MCMACHOBJECTWRITER_H
 
+#include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/OwningPtr.h"
+#include "llvm/ADT/SmallString.h"
+#include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCObjectWriter.h"
+#include "llvm/Object/MachOFormat.h"
 #include "llvm/Support/DataTypes.h"
+#include <vector>
 
 namespace llvm {
 
+class MCSectionData;
+class MachObjectWriter;
+
 class MCMachObjectTargetWriter {
   const unsigned Is64Bit : 1;
   const uint32_t CPUType;
@@ -48,8 +57,191 @@
   }
 
   /// @}
+
+  /// @name API
+  /// @{
+
+  virtual void RecordRelocation(MachObjectWriter *Writer,
+                                const MCAssembler &Asm,
+                                const MCAsmLayout &Layout,
+                                const MCFragment *Fragment,
+                                const MCFixup &Fixup,
+                                MCValue Target,
+                                uint64_t &FixedValue) = 0;
+
+  /// @}
 };
 
+class MachObjectWriter : public MCObjectWriter {
+  /// MachSymbolData - Helper struct for containing some precomputed information
+  /// on symbols.
+  struct MachSymbolData {
+    MCSymbolData *SymbolData;
+    uint64_t StringIndex;
+    uint8_t SectionIndex;
+
+    // Support lexicographic sorting.
+    bool operator<(const MachSymbolData &RHS) const;
+  };
+
+  /// The target specific Mach-O writer instance.
+  llvm::OwningPtr<MCMachObjectTargetWriter> TargetObjectWriter;
+
+  /// @name Relocation Data
+  /// @{
+
+  llvm::DenseMap<const MCSectionData*,
+                 std::vector<object::macho::RelocationEntry> > Relocations;
+  llvm::DenseMap<const MCSectionData*, unsigned> IndirectSymBase;
+
+  /// @}
+  /// @name Symbol Table Data
+  /// @{
+
+  SmallString<256> StringTable;
+  std::vector<MachSymbolData> LocalSymbolData;
+  std::vector<MachSymbolData> ExternalSymbolData;
+  std::vector<MachSymbolData> UndefinedSymbolData;
+
+  /// @}
+
+public:
+  MachObjectWriter(MCMachObjectTargetWriter *MOTW, raw_ostream &_OS,
+                   bool _IsLittleEndian)
+    : MCObjectWriter(_OS, _IsLittleEndian), TargetObjectWriter(MOTW) {
+  }
+
+  /// @name Utility Methods
+  /// @{
+
+  bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind);
+
+  SectionAddrMap SectionAddress;
+
+  SectionAddrMap &getSectionAddressMap() { return SectionAddress; }
+
+  uint64_t getSectionAddress(const MCSectionData* SD) const {
+    return SectionAddress.lookup(SD);
+  }
+  uint64_t getSymbolAddress(const MCSymbolData* SD,
+                            const MCAsmLayout &Layout) const;
+
+  uint64_t getFragmentAddress(const MCFragment *Fragment,
+                              const MCAsmLayout &Layout) const;
+
+  uint64_t getPaddingSize(const MCSectionData *SD,
+                          const MCAsmLayout &Layout) const;
+
+  bool doesSymbolRequireExternRelocation(const MCSymbolData *SD);
+
+  /// @}
+
+  /// @name Target Writer Proxy Accessors
+  /// @{
+
+  bool is64Bit() const { return TargetObjectWriter->is64Bit(); }
+  bool isARM() const {
+    uint32_t CPUType = TargetObjectWriter->getCPUType() &
+      ~object::mach::CTFM_ArchMask;
+    return CPUType == object::mach::CTM_ARM;
+  }
+
+  /// @}
+
+  void WriteHeader(unsigned NumLoadCommands, unsigned LoadCommandsSize,
+                   bool SubsectionsViaSymbols);
+
+  /// WriteSegmentLoadCommand - Write a segment load command.
+  ///
+  /// \arg NumSections - The number of sections in this segment.
+  /// \arg SectionDataSize - The total size of the sections.
+  void WriteSegmentLoadCommand(unsigned NumSections,
+                               uint64_t VMSize,
+                               uint64_t SectionDataStartOffset,
+                               uint64_t SectionDataSize);
+
+  void WriteSection(const MCAssembler &Asm, const MCAsmLayout &Layout,
+                    const MCSectionData &SD, uint64_t FileOffset,
+                    uint64_t RelocationsStart, unsigned NumRelocations);
+
+  void WriteSymtabLoadCommand(uint32_t SymbolOffset, uint32_t NumSymbols,
+                              uint32_t StringTableOffset,
+                              uint32_t StringTableSize);
+
+  void WriteDysymtabLoadCommand(uint32_t FirstLocalSymbol,
+                                uint32_t NumLocalSymbols,
+                                uint32_t FirstExternalSymbol,
+                                uint32_t NumExternalSymbols,
+                                uint32_t FirstUndefinedSymbol,
+                                uint32_t NumUndefinedSymbols,
+                                uint32_t IndirectSymbolOffset,
+                                uint32_t NumIndirectSymbols);
+
+  void WriteNlist(MachSymbolData &MSD, const MCAsmLayout &Layout);
+
+  // FIXME: We really need to improve the relocation validation. Basically, we
+  // want to implement a separate computation which evaluates the relocation
+  // entry as the linker would, and verifies that the resultant fixup value is
+  // exactly what the encoder wanted. This will catch several classes of
+  // problems:
+  //
+  //  - Relocation entry bugs, the two algorithms are unlikely to have the same
+  //    exact bug.
+  //
+  //  - Relaxation issues, where we forget to relax something.
+  //
+  //  - Input errors, where something cannot be correctly encoded. 'as' allows
+  //    these through in many cases.
+
+  void addRelocation(const MCSectionData *SD,
+                     object::macho::RelocationEntry &MRE) {
+    Relocations[SD].push_back(MRE);
+  }
+
+  void RecordScatteredRelocation(const MCAssembler &Asm,
+                                 const MCAsmLayout &Layout,
+                                 const MCFragment *Fragment,
+                                 const MCFixup &Fixup, MCValue Target,
+                                 unsigned Log2Size,
+                                 uint64_t &FixedValue);
+
+  void RecordTLVPRelocation(const MCAssembler &Asm,
+                            const MCAsmLayout &Layout,
+                            const MCFragment *Fragment,
+                            const MCFixup &Fixup, MCValue Target,
+                            uint64_t &FixedValue);
+
+  void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
+                        const MCFragment *Fragment, const MCFixup &Fixup,
+                        MCValue Target, uint64_t &FixedValue);
+
+  void BindIndirectSymbols(MCAssembler &Asm);
+
+  /// ComputeSymbolTable - Compute the symbol table data
+  ///
+  /// \param StringTable [out] - The string table data.
+  /// \param StringIndexMap [out] - Map from symbol names to offsets in the
+  /// string table.
+  void ComputeSymbolTable(MCAssembler &Asm, SmallString<256> &StringTable,
+                          std::vector<MachSymbolData> &LocalSymbolData,
+                          std::vector<MachSymbolData> &ExternalSymbolData,
+                          std::vector<MachSymbolData> &UndefinedSymbolData);
+
+  void computeSectionAddresses(const MCAssembler &Asm,
+                               const MCAsmLayout &Layout);
+
+  void ExecutePostLayoutBinding(MCAssembler &Asm, const MCAsmLayout &Layout);
+
+  virtual bool IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm,
+                                                      const MCSymbolData &DataA,
+                                                      const MCFragment &FB,
+                                                      bool InSet,
+                                                      bool IsPCRel) const;
+
+  void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout);
+};
+
+
 /// \brief Construct a new Mach-O writer instance.
 ///
 /// This routine takes ownership of the target writer subclass.

Modified: llvm/trunk/lib/MC/MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MachObjectWriter.cpp?rev=133844&r1=133843&r2=133844&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/MC/MachObjectWriter.cpp Fri Jun 24 18:44:37 2011
@@ -23,34 +23,12 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Target/TargetAsmBackend.h"
 
-// FIXME: Gross.
-#include "../Target/ARM/ARMFixupKinds.h"
-#include "../Target/X86/X86FixupKinds.h"
-
 #include <vector>
 using namespace llvm;
 using namespace llvm::object;
 
-// FIXME: this has been copied from (or to) X86AsmBackend.cpp
-static unsigned getFixupKindLog2Size(unsigned Kind) {
-  switch (Kind) {
-  default:
-    llvm_unreachable("invalid fixup kind!");
-  case FK_PCRel_1:
-  case FK_Data_1: return 0;
-  case FK_PCRel_2:
-  case FK_Data_2: return 1;
-  case FK_PCRel_4:
-    // FIXME: Remove these!!!
-  case X86::reloc_riprel_4byte:
-  case X86::reloc_riprel_4byte_movq_load:
-  case X86::reloc_signed_4byte:
-  case FK_Data_4: return 2;
-  case FK_Data_8: return 3;
-  }
-}
-
-static bool doesSymbolRequireExternRelocation(MCSymbolData *SD) {
+bool MachObjectWriter::
+doesSymbolRequireExternRelocation(const MCSymbolData *SD) {
   // Undefined symbols are always extern.
   if (SD->Symbol->isUndefined())
     return true;
@@ -64,207 +42,24 @@
   return false;
 }
 
-namespace {
-
-class MachObjectWriter : public MCObjectWriter {
-  /// MachSymbolData - Helper struct for containing some precomputed information
-  /// on symbols.
-  struct MachSymbolData {
-    MCSymbolData *SymbolData;
-    uint64_t StringIndex;
-    uint8_t SectionIndex;
-
-    // Support lexicographic sorting.
-    bool operator<(const MachSymbolData &RHS) const {
-      return SymbolData->getSymbol().getName() <
-             RHS.SymbolData->getSymbol().getName();
-    }
-  };
-
-  /// The target specific Mach-O writer instance.
-  llvm::OwningPtr<MCMachObjectTargetWriter> TargetObjectWriter;
-
-  /// @name Relocation Data
-  /// @{
-
-  llvm::DenseMap<const MCSectionData*,
-                 std::vector<macho::RelocationEntry> > Relocations;
-  llvm::DenseMap<const MCSectionData*, unsigned> IndirectSymBase;
-
-  /// @}
-  /// @name Symbol Table Data
-  /// @{
-
-  SmallString<256> StringTable;
-  std::vector<MachSymbolData> LocalSymbolData;
-  std::vector<MachSymbolData> ExternalSymbolData;
-  std::vector<MachSymbolData> UndefinedSymbolData;
-
-  /// @}
-
-private:
-  /// @name Utility Methods
-  /// @{
-
-  bool isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind) {
-    const MCFixupKindInfo &FKI = Asm.getBackend().getFixupKindInfo(
-      (MCFixupKind) Kind);
-
-    return FKI.Flags & MCFixupKindInfo::FKF_IsPCRel;
-  }
-
-  /// @}
-
-  SectionAddrMap SectionAddress;
-  uint64_t getSectionAddress(const MCSectionData* SD) const {
-    return SectionAddress.lookup(SD);
-  }
-  uint64_t getSymbolAddress(const MCSymbolData* SD,
-                            const MCAsmLayout &Layout) const;
-
-  uint64_t getFragmentAddress(const MCFragment *Fragment,
-                              const MCAsmLayout &Layout) const {
-    return getSectionAddress(Fragment->getParent()) +
-      Layout.getFragmentOffset(Fragment);
-  }
-
-  uint64_t getPaddingSize(const MCSectionData *SD,
-                          const MCAsmLayout &Layout) const;
-public:
-  MachObjectWriter(MCMachObjectTargetWriter *MOTW, raw_ostream &_OS,
-                   bool _IsLittleEndian)
-    : MCObjectWriter(_OS, _IsLittleEndian), TargetObjectWriter(MOTW) {
-  }
-
-  /// @name Target Writer Proxy Accessors
-  /// @{
-
-  bool is64Bit() const { return TargetObjectWriter->is64Bit(); }
-  bool isARM() const {
-    uint32_t CPUType = TargetObjectWriter->getCPUType() & ~mach::CTFM_ArchMask;
-    return CPUType == mach::CTM_ARM;
-  }
-
-  /// @}
-
-  void WriteHeader(unsigned NumLoadCommands, unsigned LoadCommandsSize,
-                   bool SubsectionsViaSymbols);
-
-  /// WriteSegmentLoadCommand - Write a segment load command.
-  ///
-  /// \arg NumSections - The number of sections in this segment.
-  /// \arg SectionDataSize - The total size of the sections.
-  void WriteSegmentLoadCommand(unsigned NumSections,
-                               uint64_t VMSize,
-                               uint64_t SectionDataStartOffset,
-                               uint64_t SectionDataSize);
-
-  void WriteSection(const MCAssembler &Asm, const MCAsmLayout &Layout,
-                    const MCSectionData &SD, uint64_t FileOffset,
-                    uint64_t RelocationsStart, unsigned NumRelocations);
-
-  void WriteSymtabLoadCommand(uint32_t SymbolOffset, uint32_t NumSymbols,
-                              uint32_t StringTableOffset,
-                              uint32_t StringTableSize);
-
-  void WriteDysymtabLoadCommand(uint32_t FirstLocalSymbol,
-                                uint32_t NumLocalSymbols,
-                                uint32_t FirstExternalSymbol,
-                                uint32_t NumExternalSymbols,
-                                uint32_t FirstUndefinedSymbol,
-                                uint32_t NumUndefinedSymbols,
-                                uint32_t IndirectSymbolOffset,
-                                uint32_t NumIndirectSymbols);
-
-  void WriteNlist(MachSymbolData &MSD, const MCAsmLayout &Layout);
-
-  // FIXME: We really need to improve the relocation validation. Basically, we
-  // want to implement a separate computation which evaluates the relocation
-  // entry as the linker would, and verifies that the resultant fixup value is
-  // exactly what the encoder wanted. This will catch several classes of
-  // problems:
-  //
-  //  - Relocation entry bugs, the two algorithms are unlikely to have the same
-  //    exact bug.
-  //
-  //  - Relaxation issues, where we forget to relax something.
-  //
-  //  - Input errors, where something cannot be correctly encoded. 'as' allows
-  //    these through in many cases.
-
-  static bool isFixupKindRIPRel(unsigned Kind) {
-    return Kind == X86::reloc_riprel_4byte ||
-      Kind == X86::reloc_riprel_4byte_movq_load;
-  }
-  void RecordX86_64Relocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
-                              const MCFragment *Fragment,
-                              const MCFixup &Fixup, MCValue Target,
-                              uint64_t &FixedValue);
-
-  void RecordScatteredRelocation(const MCAssembler &Asm,
-                                 const MCAsmLayout &Layout,
-                                 const MCFragment *Fragment,
-                                 const MCFixup &Fixup, MCValue Target,
-                                 unsigned Log2Size,
-                                 uint64_t &FixedValue);
+bool MachObjectWriter::
+MachSymbolData::operator<(const MachSymbolData &RHS) const {
+  return SymbolData->getSymbol().getName() <
+    RHS.SymbolData->getSymbol().getName();
+}
 
-  void RecordARMScatteredRelocation(const MCAssembler &Asm,
-                                    const MCAsmLayout &Layout,
-                                    const MCFragment *Fragment,
-                                    const MCFixup &Fixup, MCValue Target,
-                                    unsigned Log2Size,
-                                    uint64_t &FixedValue);
-
-  void RecordARMMovwMovtRelocation(const MCAssembler &Asm,
-                                   const MCAsmLayout &Layout,
-                                   const MCFragment *Fragment,
-                                   const MCFixup &Fixup, MCValue Target,
-                                   uint64_t &FixedValue);
-
-  void RecordTLVPRelocation(const MCAssembler &Asm,
-                            const MCAsmLayout &Layout,
-                            const MCFragment *Fragment,
-                            const MCFixup &Fixup, MCValue Target,
-                            uint64_t &FixedValue);
-
-  static bool getARMFixupKindMachOInfo(unsigned Kind, unsigned &RelocType,
-                                       unsigned &Log2Size);
-
-  void RecordARMRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
-                           const MCFragment *Fragment, const MCFixup &Fixup,
-                           MCValue Target, uint64_t &FixedValue);
-
-  void RecordRelocation(const MCAssembler &Asm, const MCAsmLayout &Layout,
-                        const MCFragment *Fragment, const MCFixup &Fixup,
-                        MCValue Target, uint64_t &FixedValue);
-
-  void BindIndirectSymbols(MCAssembler &Asm);
-
-  /// ComputeSymbolTable - Compute the symbol table data
-  ///
-  /// \param StringTable [out] - The string table data.
-  /// \param StringIndexMap [out] - Map from symbol names to offsets in the
-  /// string table.
-  void ComputeSymbolTable(MCAssembler &Asm, SmallString<256> &StringTable,
-                          std::vector<MachSymbolData> &LocalSymbolData,
-                          std::vector<MachSymbolData> &ExternalSymbolData,
-                          std::vector<MachSymbolData> &UndefinedSymbolData);
-
-  void computeSectionAddresses(const MCAssembler &Asm,
-                               const MCAsmLayout &Layout);
-
-  void ExecutePostLayoutBinding(MCAssembler &Asm, const MCAsmLayout &Layout);
-
-  virtual bool IsSymbolRefDifferenceFullyResolvedImpl(const MCAssembler &Asm,
-                                                      const MCSymbolData &DataA,
-                                                      const MCFragment &FB,
-                                                      bool InSet,
-                                                      bool IsPCRel) const;
+bool MachObjectWriter::isFixupKindPCRel(const MCAssembler &Asm, unsigned Kind) {
+  const MCFixupKindInfo &FKI = Asm.getBackend().getFixupKindInfo(
+    (MCFixupKind) Kind);
 
-  void WriteObject(MCAssembler &Asm, const MCAsmLayout &Layout);
-};
+  return FKI.Flags & MCFixupKindInfo::FKF_IsPCRel;
+}
 
-} // end anonymous namespace
+uint64_t MachObjectWriter::getFragmentAddress(const MCFragment *Fragment,
+                                              const MCAsmLayout &Layout) const {
+  return getSectionAddress(Fragment->getParent()) +
+    Layout.getFragmentOffset(Fragment);
+}
 
 uint64_t MachObjectWriter::getSymbolAddress(const MCSymbolData* SD,
                                             const MCAsmLayout &Layout) const {
@@ -556,775 +351,14 @@
     Write32(Address);
 }
 
-void MachObjectWriter::RecordX86_64Relocation(const MCAssembler &Asm,
-                                              const MCAsmLayout &Layout,
-                                              const MCFragment *Fragment,
-                                              const MCFixup &Fixup,
-                                              MCValue Target,
-                                              uint64_t &FixedValue) {
-  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-  unsigned IsRIPRel = isFixupKindRIPRel(Fixup.getKind());
-  unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
-
-  // See <reloc.h>.
-  uint32_t FixupOffset =
-    Layout.getFragmentOffset(Fragment) + Fixup.getOffset();
-  uint32_t FixupAddress =
-    getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
-  int64_t Value = 0;
-  unsigned Index = 0;
-  unsigned IsExtern = 0;
-  unsigned Type = 0;
-
-  Value = Target.getConstant();
-
-  if (IsPCRel) {
-    // Compensate for the relocation offset, Darwin x86_64 relocations only have
-    // the addend and appear to have attempted to define it to be the actual
-    // expression addend without the PCrel bias. However, instructions with data
-    // following the relocation are not accommodated for (see comment below
-    // regarding SIGNED{1,2,4}), so it isn't exactly that either.
-    Value += 1LL << Log2Size;
-  }
-
-  if (Target.isAbsolute()) { // constant
-    // SymbolNum of 0 indicates the absolute section.
-    Type = macho::RIT_X86_64_Unsigned;
-    Index = 0;
-
-    // FIXME: I believe this is broken, I don't think the linker can understand
-    // it. I think it would require a local relocation, but I'm not sure if that
-    // would work either. The official way to get an absolute PCrel relocation
-    // is to use an absolute symbol (which we don't support yet).
-    if (IsPCRel) {
-      IsExtern = 1;
-      Type = macho::RIT_X86_64_Branch;
-    }
-  } else if (Target.getSymB()) { // A - B + constant
-    const MCSymbol *A = &Target.getSymA()->getSymbol();
-    MCSymbolData &A_SD = Asm.getSymbolData(*A);
-    const MCSymbolData *A_Base = Asm.getAtom(&A_SD);
-
-    const MCSymbol *B = &Target.getSymB()->getSymbol();
-    MCSymbolData &B_SD = Asm.getSymbolData(*B);
-    const MCSymbolData *B_Base = Asm.getAtom(&B_SD);
-
-    // Neither symbol can be modified.
-    if (Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None ||
-        Target.getSymB()->getKind() != MCSymbolRefExpr::VK_None)
-      report_fatal_error("unsupported relocation of modified symbol");
-
-    // We don't support PCrel relocations of differences. Darwin 'as' doesn't
-    // implement most of these correctly.
-    if (IsPCRel)
-      report_fatal_error("unsupported pc-relative relocation of difference");
-
-    // The support for the situation where one or both of the symbols would
-    // require a local relocation is handled just like if the symbols were
-    // external.  This is certainly used in the case of debug sections where the
-    // section has only temporary symbols and thus the symbols don't have base
-    // symbols.  This is encoded using the section ordinal and non-extern
-    // relocation entries.
-
-    // Darwin 'as' doesn't emit correct relocations for this (it ends up with a
-    // single SIGNED relocation); reject it for now.  Except the case where both
-    // symbols don't have a base, equal but both NULL.
-    if (A_Base == B_Base && A_Base)
-      report_fatal_error("unsupported relocation with identical base");
-
-    Value += getSymbolAddress(&A_SD, Layout) -
-      (A_Base == NULL ? 0 : getSymbolAddress(A_Base, Layout));
-    Value -= getSymbolAddress(&B_SD, Layout) -
-      (B_Base == NULL ? 0 : getSymbolAddress(B_Base, Layout));
-
-    if (A_Base) {
-      Index = A_Base->getIndex();
-      IsExtern = 1;
-    }
-    else {
-      Index = A_SD.getFragment()->getParent()->getOrdinal() + 1;
-      IsExtern = 0;
-    }
-    Type = macho::RIT_X86_64_Unsigned;
-
-    macho::RelocationEntry MRE;
-    MRE.Word0 = FixupOffset;
-    MRE.Word1 = ((Index     <<  0) |
-                 (IsPCRel   << 24) |
-                 (Log2Size  << 25) |
-                 (IsExtern  << 27) |
-                 (Type      << 28));
-    Relocations[Fragment->getParent()].push_back(MRE);
-
-    if (B_Base) {
-      Index = B_Base->getIndex();
-      IsExtern = 1;
-    }
-    else {
-      Index = B_SD.getFragment()->getParent()->getOrdinal() + 1;
-      IsExtern = 0;
-    }
-    Type = macho::RIT_X86_64_Subtractor;
-  } else {
-    const MCSymbol *Symbol = &Target.getSymA()->getSymbol();
-    MCSymbolData &SD = Asm.getSymbolData(*Symbol);
-    const MCSymbolData *Base = Asm.getAtom(&SD);
-
-    // Relocations inside debug sections always use local relocations when
-    // possible. This seems to be done because the debugger doesn't fully
-    // understand x86_64 relocation entries, and expects to find values that
-    // have already been fixed up.
-    if (Symbol->isInSection()) {
-      const MCSectionMachO &Section = static_cast<const MCSectionMachO&>(
-        Fragment->getParent()->getSection());
-      if (Section.hasAttribute(MCSectionMachO::S_ATTR_DEBUG))
-        Base = 0;
-    }
-
-    // x86_64 almost always uses external relocations, except when there is no
-    // symbol to use as a base address (a local symbol with no preceding
-    // non-local symbol).
-    if (Base) {
-      Index = Base->getIndex();
-      IsExtern = 1;
-
-      // Add the local offset, if needed.
-      if (Base != &SD)
-        Value += Layout.getSymbolOffset(&SD) - Layout.getSymbolOffset(Base);
-    } else if (Symbol->isInSection() && !Symbol->isVariable()) {
-      // The index is the section ordinal (1-based).
-      Index = SD.getFragment()->getParent()->getOrdinal() + 1;
-      IsExtern = 0;
-      Value += getSymbolAddress(&SD, Layout);
-
-      if (IsPCRel)
-        Value -= FixupAddress + (1 << Log2Size);
-    } else if (Symbol->isVariable()) {
-      const MCExpr *Value = Symbol->getVariableValue();
-      int64_t Res;
-      bool isAbs = Value->EvaluateAsAbsolute(Res, Layout, SectionAddress);
-      if (isAbs) {
-        FixedValue = Res;
-        return;
-      } else {
-        report_fatal_error("unsupported relocation of variable '" +
-                           Symbol->getName() + "'");
-      }
-    } else {
-      report_fatal_error("unsupported relocation of undefined symbol '" +
-                         Symbol->getName() + "'");
-    }
-
-    MCSymbolRefExpr::VariantKind Modifier = Target.getSymA()->getKind();
-    if (IsPCRel) {
-      if (IsRIPRel) {
-        if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
-          // x86_64 distinguishes movq foo at GOTPCREL so that the linker can
-          // rewrite the movq to an leaq at link time if the symbol ends up in
-          // the same linkage unit.
-          if (unsigned(Fixup.getKind()) == X86::reloc_riprel_4byte_movq_load)
-            Type = macho::RIT_X86_64_GOTLoad;
-          else
-            Type = macho::RIT_X86_64_GOT;
-        }  else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
-          Type = macho::RIT_X86_64_TLV;
-        }  else if (Modifier != MCSymbolRefExpr::VK_None) {
-          report_fatal_error("unsupported symbol modifier in relocation");
-        } else {
-          Type = macho::RIT_X86_64_Signed;
-
-          // The Darwin x86_64 relocation format has a problem where it cannot
-          // encode an address (L<foo> + <constant>) which is outside the atom
-          // containing L<foo>. Generally, this shouldn't occur but it does
-          // happen when we have a RIPrel instruction with data following the
-          // relocation entry (e.g., movb $012, L0(%rip)). Even with the PCrel
-          // adjustment Darwin x86_64 uses, the offset is still negative and the
-          // linker has no way to recognize this.
-          //
-          // To work around this, Darwin uses several special relocation types
-          // to indicate the offsets. However, the specification or
-          // implementation of these seems to also be incomplete; they should
-          // adjust the addend as well based on the actual encoded instruction
-          // (the additional bias), but instead appear to just look at the final
-          // offset.
-          switch (-(Target.getConstant() + (1LL << Log2Size))) {
-          case 1: Type = macho::RIT_X86_64_Signed1; break;
-          case 2: Type = macho::RIT_X86_64_Signed2; break;
-          case 4: Type = macho::RIT_X86_64_Signed4; break;
-          }
-        }
-      } else {
-        if (Modifier != MCSymbolRefExpr::VK_None)
-          report_fatal_error("unsupported symbol modifier in branch "
-                             "relocation");
-
-        Type = macho::RIT_X86_64_Branch;
-      }
-    } else {
-      if (Modifier == MCSymbolRefExpr::VK_GOT) {
-        Type = macho::RIT_X86_64_GOT;
-      } else if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
-        // GOTPCREL is allowed as a modifier on non-PCrel instructions, in which
-        // case all we do is set the PCrel bit in the relocation entry; this is
-        // used with exception handling, for example. The source is required to
-        // include any necessary offset directly.
-        Type = macho::RIT_X86_64_GOT;
-        IsPCRel = 1;
-      } else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
-        report_fatal_error("TLVP symbol modifier should have been rip-rel");
-      } else if (Modifier != MCSymbolRefExpr::VK_None)
-        report_fatal_error("unsupported symbol modifier in relocation");
-      else
-        Type = macho::RIT_X86_64_Unsigned;
-    }
-  }
-
-  // x86_64 always writes custom values into the fixups.
-  FixedValue = Value;
-
-  // struct relocation_info (8 bytes)
-  macho::RelocationEntry MRE;
-  MRE.Word0 = FixupOffset;
-  MRE.Word1 = ((Index     <<  0) |
-               (IsPCRel   << 24) |
-               (Log2Size  << 25) |
-               (IsExtern  << 27) |
-               (Type      << 28));
-  Relocations[Fragment->getParent()].push_back(MRE);
-}
-
-void MachObjectWriter::RecordScatteredRelocation(const MCAssembler &Asm,
-                                                 const MCAsmLayout &Layout,
-                                                 const MCFragment *Fragment,
-                                                 const MCFixup &Fixup,
-                                                 MCValue Target,
-                                                 unsigned Log2Size,
-                                                 uint64_t &FixedValue) {
-  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-  unsigned Type = macho::RIT_Vanilla;
-
-  // See <reloc.h>.
-  const MCSymbol *A = &Target.getSymA()->getSymbol();
-  MCSymbolData *A_SD = &Asm.getSymbolData(*A);
-
-  if (!A_SD->getFragment())
-    report_fatal_error("symbol '" + A->getName() +
-                       "' can not be undefined in a subtraction expression");
-
-  uint32_t Value = getSymbolAddress(A_SD, Layout);
-  uint64_t SecAddr = getSectionAddress(A_SD->getFragment()->getParent());
-  FixedValue += SecAddr;
-  uint32_t Value2 = 0;
-
-  if (const MCSymbolRefExpr *B = Target.getSymB()) {
-    MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
-
-    if (!B_SD->getFragment())
-      report_fatal_error("symbol '" + B->getSymbol().getName() +
-                         "' can not be undefined in a subtraction expression");
-
-    // Select the appropriate difference relocation type.
-    //
-    // Note that there is no longer any semantic difference between these two
-    // relocation types from the linkers point of view, this is done solely for
-    // pedantic compatibility with 'as'.
-    Type = A_SD->isExternal() ? (unsigned)macho::RIT_Difference :
-      (unsigned)macho::RIT_Generic_LocalDifference;
-    Value2 = getSymbolAddress(B_SD, Layout);
-    FixedValue -= getSectionAddress(B_SD->getFragment()->getParent());
-  }
-
-  // Relocations are written out in reverse order, so the PAIR comes first.
-  if (Type == macho::RIT_Difference ||
-      Type == macho::RIT_Generic_LocalDifference) {
-    macho::RelocationEntry MRE;
-    MRE.Word0 = ((0         <<  0) |
-                 (macho::RIT_Pair  << 24) |
-                 (Log2Size  << 28) |
-                 (IsPCRel   << 30) |
-                 macho::RF_Scattered);
-    MRE.Word1 = Value2;
-    Relocations[Fragment->getParent()].push_back(MRE);
-  }
-
-  macho::RelocationEntry MRE;
-  MRE.Word0 = ((FixupOffset <<  0) |
-               (Type        << 24) |
-               (Log2Size    << 28) |
-               (IsPCRel     << 30) |
-               macho::RF_Scattered);
-  MRE.Word1 = Value;
-  Relocations[Fragment->getParent()].push_back(MRE);
-}
-
-void MachObjectWriter::RecordARMScatteredRelocation(const MCAssembler &Asm,
-                                                    const MCAsmLayout &Layout,
-                                                    const MCFragment *Fragment,
-                                                    const MCFixup &Fixup,
-                                                    MCValue Target,
-                                                    unsigned Log2Size,
-                                                    uint64_t &FixedValue) {
-  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-  unsigned Type = macho::RIT_Vanilla;
-
-  // See <reloc.h>.
-  const MCSymbol *A = &Target.getSymA()->getSymbol();
-  MCSymbolData *A_SD = &Asm.getSymbolData(*A);
-
-  if (!A_SD->getFragment())
-    report_fatal_error("symbol '" + A->getName() +
-                       "' can not be undefined in a subtraction expression");
-
-  uint32_t Value = getSymbolAddress(A_SD, Layout);
-  uint64_t SecAddr = getSectionAddress(A_SD->getFragment()->getParent());
-  FixedValue += SecAddr;
-  uint32_t Value2 = 0;
-
-  if (const MCSymbolRefExpr *B = Target.getSymB()) {
-    MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
-
-    if (!B_SD->getFragment())
-      report_fatal_error("symbol '" + B->getSymbol().getName() +
-                         "' can not be undefined in a subtraction expression");
-
-    // Select the appropriate difference relocation type.
-    Type = macho::RIT_Difference;
-    Value2 = getSymbolAddress(B_SD, Layout);
-    FixedValue -= getSectionAddress(B_SD->getFragment()->getParent());
-  }
-
-  // Relocations are written out in reverse order, so the PAIR comes first.
-  if (Type == macho::RIT_Difference ||
-      Type == macho::RIT_Generic_LocalDifference) {
-    macho::RelocationEntry MRE;
-    MRE.Word0 = ((0         <<  0) |
-                 (macho::RIT_Pair  << 24) |
-                 (Log2Size  << 28) |
-                 (IsPCRel   << 30) |
-                 macho::RF_Scattered);
-    MRE.Word1 = Value2;
-    Relocations[Fragment->getParent()].push_back(MRE);
-  }
-
-  macho::RelocationEntry MRE;
-  MRE.Word0 = ((FixupOffset <<  0) |
-               (Type        << 24) |
-               (Log2Size    << 28) |
-               (IsPCRel     << 30) |
-               macho::RF_Scattered);
-  MRE.Word1 = Value;
-  Relocations[Fragment->getParent()].push_back(MRE);
-}
-
-void MachObjectWriter::RecordARMMovwMovtRelocation(const MCAssembler &Asm,
-                                                   const MCAsmLayout &Layout,
-                                                   const MCFragment *Fragment,
-                                                   const MCFixup &Fixup,
-                                                   MCValue Target,
-                                                   uint64_t &FixedValue) {
-  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-  unsigned Type = macho::RIT_ARM_Half;
-
-  // See <reloc.h>.
-  const MCSymbol *A = &Target.getSymA()->getSymbol();
-  MCSymbolData *A_SD = &Asm.getSymbolData(*A);
-
-  if (!A_SD->getFragment())
-    report_fatal_error("symbol '" + A->getName() +
-                       "' can not be undefined in a subtraction expression");
-
-  uint32_t Value = getSymbolAddress(A_SD, Layout);
-  uint32_t Value2 = 0;
-  uint64_t SecAddr = getSectionAddress(A_SD->getFragment()->getParent());
-  FixedValue += SecAddr;
-
-  if (const MCSymbolRefExpr *B = Target.getSymB()) {
-    MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
-
-    if (!B_SD->getFragment())
-      report_fatal_error("symbol '" + B->getSymbol().getName() +
-                         "' can not be undefined in a subtraction expression");
-
-    // Select the appropriate difference relocation type.
-    Type = macho::RIT_ARM_HalfDifference;
-    Value2 = getSymbolAddress(B_SD, Layout);
-    FixedValue -= getSectionAddress(B_SD->getFragment()->getParent());
-  }
-
-  // Relocations are written out in reverse order, so the PAIR comes first.
-  // ARM_RELOC_HALF and ARM_RELOC_HALF_SECTDIFF abuse the r_length field:
-  //
-  // For these two r_type relocations they always have a pair following them and
-  // the r_length bits are used differently.  The encoding of the r_length is as
-  // follows:
-  //   low bit of r_length:
-  //      0 - :lower16: for movw instructions
-  //      1 - :upper16: for movt instructions
-  //   high bit of r_length:
-  //      0 - arm instructions
-  //      1 - thumb instructions
-  // the other half of the relocated expression is in the following pair
-  // relocation entry in the the low 16 bits of r_address field.
-  unsigned ThumbBit = 0;
-  unsigned MovtBit = 0;
-  switch ((unsigned)Fixup.getKind()) {
-  default: break;
-  case ARM::fixup_arm_movt_hi16:
-  case ARM::fixup_arm_movt_hi16_pcrel:
-    MovtBit = 1;
-    break;
-  case ARM::fixup_t2_movt_hi16:
-  case ARM::fixup_t2_movt_hi16_pcrel:
-    MovtBit = 1;
-    // Fallthrough
-  case ARM::fixup_t2_movw_lo16:
-  case ARM::fixup_t2_movw_lo16_pcrel:
-    ThumbBit = 1;
-    break;
-  }
-
-
-  if (Type == macho::RIT_ARM_HalfDifference) {
-    uint32_t OtherHalf = MovtBit
-      ? (FixedValue & 0xffff) : ((FixedValue & 0xffff0000) >> 16);
-
-    macho::RelocationEntry MRE;
-    MRE.Word0 = ((OtherHalf       <<  0) |
-                 (macho::RIT_Pair << 24) |
-                 (MovtBit         << 28) |
-                 (ThumbBit        << 29) |
-                 (IsPCRel         << 30) |
-                 macho::RF_Scattered);
-    MRE.Word1 = Value2;
-    Relocations[Fragment->getParent()].push_back(MRE);
-  }
-
-  macho::RelocationEntry MRE;
-  MRE.Word0 = ((FixupOffset <<  0) |
-               (Type        << 24) |
-               (MovtBit     << 28) |
-               (ThumbBit    << 29) |
-               (IsPCRel     << 30) |
-               macho::RF_Scattered);
-  MRE.Word1 = Value;
-  Relocations[Fragment->getParent()].push_back(MRE);
-}
-
-void MachObjectWriter::RecordTLVPRelocation(const MCAssembler &Asm,
-                                            const MCAsmLayout &Layout,
-                                            const MCFragment *Fragment,
-                                            const MCFixup &Fixup,
-                                            MCValue Target,
-                                            uint64_t &FixedValue) {
-  assert(Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP &&
-         !is64Bit() &&
-         "Should only be called with a 32-bit TLVP relocation!");
-
-  unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
-  uint32_t Value = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-  unsigned IsPCRel = 0;
-
-  // Get the symbol data.
-  MCSymbolData *SD_A = &Asm.getSymbolData(Target.getSymA()->getSymbol());
-  unsigned Index = SD_A->getIndex();
-
-  // We're only going to have a second symbol in pic mode and it'll be a
-  // subtraction from the picbase. For 32-bit pic the addend is the difference
-  // between the picbase and the next address.  For 32-bit static the addend is
-  // zero.
-  if (Target.getSymB()) {
-    // If this is a subtraction then we're pcrel.
-    uint32_t FixupAddress =
-      getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
-    MCSymbolData *SD_B = &Asm.getSymbolData(Target.getSymB()->getSymbol());
-    IsPCRel = 1;
-    FixedValue = (FixupAddress - getSymbolAddress(SD_B, Layout) +
-                  Target.getConstant());
-    FixedValue += 1ULL << Log2Size;
-  } else {
-    FixedValue = 0;
-  }
-
-  // struct relocation_info (8 bytes)
-  macho::RelocationEntry MRE;
-  MRE.Word0 = Value;
-  MRE.Word1 = ((Index                  <<  0) |
-               (IsPCRel                << 24) |
-               (Log2Size               << 25) |
-               (1                      << 27) | // Extern
-               (macho::RIT_Generic_TLV << 28)); // Type
-  Relocations[Fragment->getParent()].push_back(MRE);
-}
-
-bool MachObjectWriter::getARMFixupKindMachOInfo(unsigned Kind,
-                                                unsigned &RelocType,
-                                                unsigned &Log2Size) {
-  RelocType = unsigned(macho::RIT_Vanilla);
-  Log2Size = ~0U;
-
-  switch (Kind) {
-  default:
-    return false;
-
-  case FK_Data_1:
-    Log2Size = llvm::Log2_32(1);
-    return true;
-  case FK_Data_2:
-    Log2Size = llvm::Log2_32(2);
-    return true;
-  case FK_Data_4:
-    Log2Size = llvm::Log2_32(4);
-    return true;
-  case FK_Data_8:
-    Log2Size = llvm::Log2_32(8);
-    return true;
-
-    // Handle 24-bit branch kinds.
-  case ARM::fixup_arm_ldst_pcrel_12:
-  case ARM::fixup_arm_pcrel_10:
-  case ARM::fixup_arm_adr_pcrel_12:
-  case ARM::fixup_arm_condbranch:
-  case ARM::fixup_arm_uncondbranch:
-    RelocType = unsigned(macho::RIT_ARM_Branch24Bit);
-    // Report as 'long', even though that is not quite accurate.
-    Log2Size = llvm::Log2_32(4);
-    return true;
-
-    // Handle Thumb branches.
-  case ARM::fixup_arm_thumb_br:
-    RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);
-    Log2Size = llvm::Log2_32(2);
-    return true;
-
-  case ARM::fixup_t2_uncondbranch:
-  case ARM::fixup_arm_thumb_bl:
-  case ARM::fixup_arm_thumb_blx:
-    RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);
-    Log2Size = llvm::Log2_32(4);
-    return true;
-
-  case ARM::fixup_arm_movt_hi16:
-  case ARM::fixup_arm_movt_hi16_pcrel:
-  case ARM::fixup_t2_movt_hi16:
-  case ARM::fixup_t2_movt_hi16_pcrel:
-    RelocType = unsigned(macho::RIT_ARM_HalfDifference);
-    // Report as 'long', even though that is not quite accurate.
-    Log2Size = llvm::Log2_32(4);
-    return true;
-
-  case ARM::fixup_arm_movw_lo16:
-  case ARM::fixup_arm_movw_lo16_pcrel:
-  case ARM::fixup_t2_movw_lo16:
-  case ARM::fixup_t2_movw_lo16_pcrel:
-    RelocType = unsigned(macho::RIT_ARM_Half);
-    // Report as 'long', even though that is not quite accurate.
-    Log2Size = llvm::Log2_32(4);
-    return true;
-  }
-}
-void MachObjectWriter::RecordARMRelocation(const MCAssembler &Asm,
-                                           const MCAsmLayout &Layout,
-                                           const MCFragment *Fragment,
-                                           const MCFixup &Fixup,
-                                           MCValue Target,
-                                           uint64_t &FixedValue) {
-  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-  unsigned Log2Size;
-  unsigned RelocType = macho::RIT_Vanilla;
-  if (!getARMFixupKindMachOInfo(Fixup.getKind(), RelocType, Log2Size)) {
-    report_fatal_error("unknown ARM fixup kind!");
-    return;
-  }
-
-  // If this is a difference or a defined symbol plus an offset, then we need a
-  // scattered relocation entry.  Differences always require scattered
-  // relocations.
-  if (Target.getSymB()) {
-    if (RelocType == macho::RIT_ARM_Half ||
-        RelocType == macho::RIT_ARM_HalfDifference)
-      return RecordARMMovwMovtRelocation(Asm, Layout, Fragment, Fixup,
-                                         Target, FixedValue);
-    return RecordARMScatteredRelocation(Asm, Layout, Fragment, Fixup,
-                                        Target, Log2Size, FixedValue);
-  }
-
-  // Get the symbol data, if any.
-  MCSymbolData *SD = 0;
-  if (Target.getSymA())
-    SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
-
-  // FIXME: For other platforms, we need to use scattered relocations for
-  // internal relocations with offsets.  If this is an internal relocation with
-  // an offset, it also needs a scattered relocation entry.
-  //
-  // Is this right for ARM?
-  uint32_t Offset = Target.getConstant();
-  if (IsPCRel && RelocType == macho::RIT_Vanilla)
-    Offset += 1 << Log2Size;
-  if (Offset && SD && !doesSymbolRequireExternRelocation(SD))
-    return RecordARMScatteredRelocation(Asm, Layout, Fragment, Fixup, Target,
-                                        Log2Size, FixedValue);
-
-  // See <reloc.h>.
-  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-  unsigned Index = 0;
-  unsigned IsExtern = 0;
-  unsigned Type = 0;
-
-  if (Target.isAbsolute()) { // constant
-    // FIXME!
-    report_fatal_error("FIXME: relocations to absolute targets "
-                       "not yet implemented");
-  } else {
-    // Resolve constant variables.
-    if (SD->getSymbol().isVariable()) {
-      int64_t Res;
-      if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute(
-            Res, Layout, SectionAddress)) {
-        FixedValue = Res;
-        return;
-      }
-    }
-
-    // Check whether we need an external or internal relocation.
-    if (doesSymbolRequireExternRelocation(SD)) {
-      IsExtern = 1;
-      Index = SD->getIndex();
-
-      // For external relocations, make sure to offset the fixup value to
-      // compensate for the addend of the symbol address, if it was
-      // undefined. This occurs with weak definitions, for example.
-      if (!SD->Symbol->isUndefined())
-        FixedValue -= Layout.getSymbolOffset(SD);
-    } else {
-      // The index is the section ordinal (1-based).
-      const MCSectionData &SymSD = Asm.getSectionData(
-        SD->getSymbol().getSection());
-      Index = SymSD.getOrdinal() + 1;
-      FixedValue += getSectionAddress(&SymSD);
-    }
-    if (IsPCRel)
-      FixedValue -= getSectionAddress(Fragment->getParent());
-
-    // The type is determined by the fixup kind.
-    Type = RelocType;
-  }
-
-  // struct relocation_info (8 bytes)
-  macho::RelocationEntry MRE;
-  MRE.Word0 = FixupOffset;
-  MRE.Word1 = ((Index     <<  0) |
-               (IsPCRel   << 24) |
-               (Log2Size  << 25) |
-               (IsExtern  << 27) |
-               (Type      << 28));
-  Relocations[Fragment->getParent()].push_back(MRE);
-}
-
 void MachObjectWriter::RecordRelocation(const MCAssembler &Asm,
                                         const MCAsmLayout &Layout,
                                         const MCFragment *Fragment,
                                         const MCFixup &Fixup,
                                         MCValue Target,
                                         uint64_t &FixedValue) {
-  // FIXME: These needs to be factored into the target Mach-O writer.
-  if (isARM()) {
-    RecordARMRelocation(Asm, Layout, Fragment, Fixup, Target, FixedValue);
-    return;
-  }
-  if (is64Bit()) {
-    RecordX86_64Relocation(Asm, Layout, Fragment, Fixup, Target, FixedValue);
-    return;
-  }
-
-  unsigned IsPCRel = isFixupKindPCRel(Asm, Fixup.getKind());
-  unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
-
-  // If this is a 32-bit TLVP reloc it's handled a bit differently.
-  if (Target.getSymA() &&
-      Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP) {
-    RecordTLVPRelocation(Asm, Layout, Fragment, Fixup, Target, FixedValue);
-    return;
-  }
-
-  // If this is a difference or a defined symbol plus an offset, then we need a
-  // scattered relocation entry. Differences always require scattered
-  // relocations.
-  if (Target.getSymB())
-    return RecordScatteredRelocation(Asm, Layout, Fragment, Fixup,
-                                     Target, Log2Size, FixedValue);
-
-  // Get the symbol data, if any.
-  MCSymbolData *SD = 0;
-  if (Target.getSymA())
-    SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
-
-  // If this is an internal relocation with an offset, it also needs a scattered
-  // relocation entry.
-  uint32_t Offset = Target.getConstant();
-  if (IsPCRel)
-    Offset += 1 << Log2Size;
-  if (Offset && SD && !doesSymbolRequireExternRelocation(SD))
-    return RecordScatteredRelocation(Asm, Layout, Fragment, Fixup,
-                                     Target, Log2Size, FixedValue);
-
-  // See <reloc.h>.
-  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
-  unsigned Index = 0;
-  unsigned IsExtern = 0;
-  unsigned Type = 0;
-
-  if (Target.isAbsolute()) { // constant
-    // SymbolNum of 0 indicates the absolute section.
-    //
-    // FIXME: Currently, these are never generated (see code below). I cannot
-    // find a case where they are actually emitted.
-    Type = macho::RIT_Vanilla;
-  } else {
-    // Resolve constant variables.
-    if (SD->getSymbol().isVariable()) {
-      int64_t Res;
-      if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute(
-            Res, Layout, SectionAddress)) {
-        FixedValue = Res;
-        return;
-      }
-    }
-
-    // Check whether we need an external or internal relocation.
-    if (doesSymbolRequireExternRelocation(SD)) {
-      IsExtern = 1;
-      Index = SD->getIndex();
-      // For external relocations, make sure to offset the fixup value to
-      // compensate for the addend of the symbol address, if it was
-      // undefined. This occurs with weak definitions, for example.
-      if (!SD->Symbol->isUndefined())
-        FixedValue -= Layout.getSymbolOffset(SD);
-    } else {
-      // The index is the section ordinal (1-based).
-      const MCSectionData &SymSD = Asm.getSectionData(
-        SD->getSymbol().getSection());
-      Index = SymSD.getOrdinal() + 1;
-      FixedValue += getSectionAddress(&SymSD);
-    }
-    if (IsPCRel)
-      FixedValue -= getSectionAddress(Fragment->getParent());
-
-    Type = macho::RIT_Vanilla;
-  }
-
-  // struct relocation_info (8 bytes)
-  macho::RelocationEntry MRE;
-  MRE.Word0 = FixupOffset;
-  MRE.Word1 = ((Index     <<  0) |
-               (IsPCRel   << 24) |
-               (Log2Size  << 25) |
-               (IsExtern  << 27) |
-               (Type      << 28));
-  Relocations[Fragment->getParent()].push_back(MRE);
+  TargetObjectWriter->RecordRelocation(this, Asm, Layout, Fragment, Fixup,
+                                       Target, FixedValue);
 }
 
 void MachObjectWriter::BindIndirectSymbols(MCAssembler &Asm) {

Modified: llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp?rev=133844&r1=133843&r2=133844&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMMachObjectWriter.cpp Fri Jun 24 18:44:37 2011
@@ -8,19 +8,376 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARM.h"
+#include "ARMFixupKinds.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCAsmLayout.h"
 #include "llvm/MC/MCMachObjectWriter.h"
+#include "llvm/MC/MCExpr.h"
+#include "llvm/MC/MCFixup.h"
+#include "llvm/MC/MCFixupKindInfo.h"
+#include "llvm/MC/MCValue.h"
+#include "llvm/Object/MachOFormat.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Target/TargetAsmBackend.h"
 using namespace llvm;
+using namespace llvm::object;
 
 namespace {
 class ARMMachObjectWriter : public MCMachObjectTargetWriter {
+  void RecordARMScatteredRelocation(MachObjectWriter *Writer,
+                                    const MCAssembler &Asm,
+                                    const MCAsmLayout &Layout,
+                                    const MCFragment *Fragment,
+                                    const MCFixup &Fixup,
+                                    MCValue Target,
+                                    unsigned Log2Size,
+                                    uint64_t &FixedValue);
+  void RecordARMMovwMovtRelocation(MachObjectWriter *Writer,
+                                   const MCAssembler &Asm,
+                                   const MCAsmLayout &Layout,
+                                   const MCFragment *Fragment,
+                                   const MCFixup &Fixup, MCValue Target,
+                                   uint64_t &FixedValue);
+
 public:
   ARMMachObjectWriter(bool Is64Bit, uint32_t CPUType,
                       uint32_t CPUSubtype)
     : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
                                /*UseAggressiveSymbolFolding=*/true) {}
+
+  void RecordRelocation(MachObjectWriter *Writer,
+                        const MCAssembler &Asm, const MCAsmLayout &Layout,
+                        const MCFragment *Fragment, const MCFixup &Fixup,
+                        MCValue Target, uint64_t &FixedValue);
 };
 }
 
+static bool getARMFixupKindMachOInfo(unsigned Kind, unsigned &RelocType,
+                              unsigned &Log2Size) {
+  RelocType = unsigned(macho::RIT_Vanilla);
+  Log2Size = ~0U;
+
+  switch (Kind) {
+  default:
+    return false;
+
+  case FK_Data_1:
+    Log2Size = llvm::Log2_32(1);
+    return true;
+  case FK_Data_2:
+    Log2Size = llvm::Log2_32(2);
+    return true;
+  case FK_Data_4:
+    Log2Size = llvm::Log2_32(4);
+    return true;
+  case FK_Data_8:
+    Log2Size = llvm::Log2_32(8);
+    return true;
+
+    // Handle 24-bit branch kinds.
+  case ARM::fixup_arm_ldst_pcrel_12:
+  case ARM::fixup_arm_pcrel_10:
+  case ARM::fixup_arm_adr_pcrel_12:
+  case ARM::fixup_arm_condbranch:
+  case ARM::fixup_arm_uncondbranch:
+    RelocType = unsigned(macho::RIT_ARM_Branch24Bit);
+    // Report as 'long', even though that is not quite accurate.
+    Log2Size = llvm::Log2_32(4);
+    return true;
+
+    // Handle Thumb branches.
+  case ARM::fixup_arm_thumb_br:
+    RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);
+    Log2Size = llvm::Log2_32(2);
+    return true;
+
+  case ARM::fixup_t2_uncondbranch:
+  case ARM::fixup_arm_thumb_bl:
+  case ARM::fixup_arm_thumb_blx:
+    RelocType = unsigned(macho::RIT_ARM_ThumbBranch22Bit);
+    Log2Size = llvm::Log2_32(4);
+    return true;
+
+  case ARM::fixup_arm_movt_hi16:
+  case ARM::fixup_arm_movt_hi16_pcrel:
+  case ARM::fixup_t2_movt_hi16:
+  case ARM::fixup_t2_movt_hi16_pcrel:
+    RelocType = unsigned(macho::RIT_ARM_HalfDifference);
+    // Report as 'long', even though that is not quite accurate.
+    Log2Size = llvm::Log2_32(4);
+    return true;
+
+  case ARM::fixup_arm_movw_lo16:
+  case ARM::fixup_arm_movw_lo16_pcrel:
+  case ARM::fixup_t2_movw_lo16:
+  case ARM::fixup_t2_movw_lo16_pcrel:
+    RelocType = unsigned(macho::RIT_ARM_Half);
+    // Report as 'long', even though that is not quite accurate.
+    Log2Size = llvm::Log2_32(4);
+    return true;
+  }
+}
+
+void ARMMachObjectWriter::
+RecordARMMovwMovtRelocation(MachObjectWriter *Writer,
+                            const MCAssembler &Asm,
+                            const MCAsmLayout &Layout,
+                            const MCFragment *Fragment,
+                            const MCFixup &Fixup,
+                            MCValue Target,
+                            uint64_t &FixedValue) {
+  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned Type = macho::RIT_ARM_Half;
+
+  // See <reloc.h>.
+  const MCSymbol *A = &Target.getSymA()->getSymbol();
+  MCSymbolData *A_SD = &Asm.getSymbolData(*A);
+
+  if (!A_SD->getFragment())
+    report_fatal_error("symbol '" + A->getName() +
+                       "' can not be undefined in a subtraction expression");
+
+  uint32_t Value = Writer->getSymbolAddress(A_SD, Layout);
+  uint32_t Value2 = 0;
+  uint64_t SecAddr =
+    Writer->getSectionAddress(A_SD->getFragment()->getParent());
+  FixedValue += SecAddr;
+
+  if (const MCSymbolRefExpr *B = Target.getSymB()) {
+    MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
+
+    if (!B_SD->getFragment())
+      report_fatal_error("symbol '" + B->getSymbol().getName() +
+                         "' can not be undefined in a subtraction expression");
+
+    // Select the appropriate difference relocation type.
+    Type = macho::RIT_ARM_HalfDifference;
+    Value2 = Writer->getSymbolAddress(B_SD, Layout);
+    FixedValue -= Writer->getSectionAddress(B_SD->getFragment()->getParent());
+  }
+
+  // Relocations are written out in reverse order, so the PAIR comes first.
+  // ARM_RELOC_HALF and ARM_RELOC_HALF_SECTDIFF abuse the r_length field:
+  //
+  // For these two r_type relocations they always have a pair following them and
+  // the r_length bits are used differently.  The encoding of the r_length is as
+  // follows:
+  //   low bit of r_length:
+  //      0 - :lower16: for movw instructions
+  //      1 - :upper16: for movt instructions
+  //   high bit of r_length:
+  //      0 - arm instructions
+  //      1 - thumb instructions
+  // the other half of the relocated expression is in the following pair
+  // relocation entry in the the low 16 bits of r_address field.
+  unsigned ThumbBit = 0;
+  unsigned MovtBit = 0;
+  switch ((unsigned)Fixup.getKind()) {
+  default: break;
+  case ARM::fixup_arm_movt_hi16:
+  case ARM::fixup_arm_movt_hi16_pcrel:
+    MovtBit = 1;
+    break;
+  case ARM::fixup_t2_movt_hi16:
+  case ARM::fixup_t2_movt_hi16_pcrel:
+    MovtBit = 1;
+    // Fallthrough
+  case ARM::fixup_t2_movw_lo16:
+  case ARM::fixup_t2_movw_lo16_pcrel:
+    ThumbBit = 1;
+    break;
+  }
+
+
+  if (Type == macho::RIT_ARM_HalfDifference) {
+    uint32_t OtherHalf = MovtBit
+      ? (FixedValue & 0xffff) : ((FixedValue & 0xffff0000) >> 16);
+
+    macho::RelocationEntry MRE;
+    MRE.Word0 = ((OtherHalf       <<  0) |
+                 (macho::RIT_Pair << 24) |
+                 (MovtBit         << 28) |
+                 (ThumbBit        << 29) |
+                 (IsPCRel         << 30) |
+                 macho::RF_Scattered);
+    MRE.Word1 = Value2;
+    Writer->addRelocation(Fragment->getParent(), MRE);
+  }
+
+  macho::RelocationEntry MRE;
+  MRE.Word0 = ((FixupOffset <<  0) |
+               (Type        << 24) |
+               (MovtBit     << 28) |
+               (ThumbBit    << 29) |
+               (IsPCRel     << 30) |
+               macho::RF_Scattered);
+  MRE.Word1 = Value;
+  Writer->addRelocation(Fragment->getParent(), MRE);
+}
+
+void ARMMachObjectWriter::RecordARMScatteredRelocation(MachObjectWriter *Writer,
+                                                    const MCAssembler &Asm,
+                                                    const MCAsmLayout &Layout,
+                                                    const MCFragment *Fragment,
+                                                    const MCFixup &Fixup,
+                                                    MCValue Target,
+                                                    unsigned Log2Size,
+                                                    uint64_t &FixedValue) {
+  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned Type = macho::RIT_Vanilla;
+
+  // See <reloc.h>.
+  const MCSymbol *A = &Target.getSymA()->getSymbol();
+  MCSymbolData *A_SD = &Asm.getSymbolData(*A);
+
+  if (!A_SD->getFragment())
+    report_fatal_error("symbol '" + A->getName() +
+                       "' can not be undefined in a subtraction expression");
+
+  uint32_t Value = Writer->getSymbolAddress(A_SD, Layout);
+  uint64_t SecAddr = Writer->getSectionAddress(A_SD->getFragment()->getParent());
+  FixedValue += SecAddr;
+  uint32_t Value2 = 0;
+
+  if (const MCSymbolRefExpr *B = Target.getSymB()) {
+    MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
+
+    if (!B_SD->getFragment())
+      report_fatal_error("symbol '" + B->getSymbol().getName() +
+                         "' can not be undefined in a subtraction expression");
+
+    // Select the appropriate difference relocation type.
+    Type = macho::RIT_Difference;
+    Value2 = Writer->getSymbolAddress(B_SD, Layout);
+    FixedValue -= Writer->getSectionAddress(B_SD->getFragment()->getParent());
+  }
+
+  // Relocations are written out in reverse order, so the PAIR comes first.
+  if (Type == macho::RIT_Difference ||
+      Type == macho::RIT_Generic_LocalDifference) {
+    macho::RelocationEntry MRE;
+    MRE.Word0 = ((0         <<  0) |
+                 (macho::RIT_Pair  << 24) |
+                 (Log2Size  << 28) |
+                 (IsPCRel   << 30) |
+                 macho::RF_Scattered);
+    MRE.Word1 = Value2;
+    Writer->addRelocation(Fragment->getParent(), MRE);
+  }
+
+  macho::RelocationEntry MRE;
+  MRE.Word0 = ((FixupOffset <<  0) |
+               (Type        << 24) |
+               (Log2Size    << 28) |
+               (IsPCRel     << 30) |
+               macho::RF_Scattered);
+  MRE.Word1 = Value;
+  Writer->addRelocation(Fragment->getParent(), MRE);
+}
+
+void ARMMachObjectWriter::RecordRelocation(MachObjectWriter *Writer,
+                                           const MCAssembler &Asm,
+                                           const MCAsmLayout &Layout,
+                                           const MCFragment *Fragment,
+                                           const MCFixup &Fixup,
+                                           MCValue Target,
+                                           uint64_t &FixedValue) {
+  unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned Log2Size;
+  unsigned RelocType = macho::RIT_Vanilla;
+  if (!getARMFixupKindMachOInfo(Fixup.getKind(), RelocType, Log2Size)) {
+    report_fatal_error("unknown ARM fixup kind!");
+    return;
+  }
+
+  // If this is a difference or a defined symbol plus an offset, then we need a
+  // scattered relocation entry.  Differences always require scattered
+  // relocations.
+  if (Target.getSymB()) {
+    if (RelocType == macho::RIT_ARM_Half ||
+        RelocType == macho::RIT_ARM_HalfDifference)
+      return RecordARMMovwMovtRelocation(Writer, Asm, Layout, Fragment, Fixup,
+                                         Target, FixedValue);
+    return RecordARMScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
+                                        Target, Log2Size, FixedValue);
+  }
+
+  // Get the symbol data, if any.
+  MCSymbolData *SD = 0;
+  if (Target.getSymA())
+    SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
+
+  // FIXME: For other platforms, we need to use scattered relocations for
+  // internal relocations with offsets.  If this is an internal relocation with
+  // an offset, it also needs a scattered relocation entry.
+  //
+  // Is this right for ARM?
+  uint32_t Offset = Target.getConstant();
+  if (IsPCRel && RelocType == macho::RIT_Vanilla)
+    Offset += 1 << Log2Size;
+  if (Offset && SD && !Writer->doesSymbolRequireExternRelocation(SD))
+    return RecordARMScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
+                                        Target, Log2Size, FixedValue);
+
+  // See <reloc.h>.
+  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned Index = 0;
+  unsigned IsExtern = 0;
+  unsigned Type = 0;
+
+  if (Target.isAbsolute()) { // constant
+    // FIXME!
+    report_fatal_error("FIXME: relocations to absolute targets "
+                       "not yet implemented");
+  } else {
+    // Resolve constant variables.
+    if (SD->getSymbol().isVariable()) {
+      int64_t Res;
+      if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute(
+            Res, Layout, Writer->getSectionAddressMap())) {
+        FixedValue = Res;
+        return;
+      }
+    }
+
+    // Check whether we need an external or internal relocation.
+    if (Writer->doesSymbolRequireExternRelocation(SD)) {
+      IsExtern = 1;
+      Index = SD->getIndex();
+
+      // For external relocations, make sure to offset the fixup value to
+      // compensate for the addend of the symbol address, if it was
+      // undefined. This occurs with weak definitions, for example.
+      if (!SD->Symbol->isUndefined())
+        FixedValue -= Layout.getSymbolOffset(SD);
+    } else {
+      // The index is the section ordinal (1-based).
+      const MCSectionData &SymSD = Asm.getSectionData(
+        SD->getSymbol().getSection());
+      Index = SymSD.getOrdinal() + 1;
+      FixedValue += Writer->getSectionAddress(&SymSD);
+    }
+    if (IsPCRel)
+      FixedValue -= Writer->getSectionAddress(Fragment->getParent());
+
+    // The type is determined by the fixup kind.
+    Type = RelocType;
+  }
+
+  // struct relocation_info (8 bytes)
+  macho::RelocationEntry MRE;
+  MRE.Word0 = FixupOffset;
+  MRE.Word1 = ((Index     <<  0) |
+               (IsPCRel   << 24) |
+               (Log2Size  << 25) |
+               (IsExtern  << 27) |
+               (Type      << 28));
+  Writer->addRelocation(Fragment->getParent(), MRE);
+}
+
 MCObjectWriter *llvm::createARMMachObjectWriter(raw_ostream &OS,
                                                 bool Is64Bit,
                                                 uint32_t CPUType,

Modified: llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp?rev=133844&r1=133843&r2=133844&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCAsmBackend.cpp Fri Jun 24 18:44:37 2011
@@ -13,6 +13,7 @@
 #include "llvm/MC/MCMachObjectWriter.h"
 #include "llvm/MC/MCSectionMachO.h"
 #include "llvm/MC/MCObjectWriter.h"
+#include "llvm/MC/MCValue.h"
 #include "llvm/Object/MachOFormat.h"
 #include "llvm/Target/TargetRegistry.h"
 using namespace llvm;
@@ -23,6 +24,11 @@
   PPCMachObjectWriter(bool Is64Bit, uint32_t CPUType,
                       uint32_t CPUSubtype)
     : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {}
+
+  void RecordRelocation(MachObjectWriter *Writer,
+                        const MCAssembler &Asm, const MCAsmLayout &Layout,
+                        const MCFragment *Fragment, const MCFixup &Fixup,
+                        MCValue Target, uint64_t &FixedValue) {}
 };
 
 class PPCAsmBackend : public TargetAsmBackend {

Modified: llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp?rev=133844&r1=133843&r2=133844&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86MachObjectWriter.cpp Fri Jun 24 18:44:37 2011
@@ -8,19 +8,541 @@
 //===----------------------------------------------------------------------===//
 
 #include "X86.h"
+#include "X86FixupKinds.h"
+#include "llvm/ADT/Twine.h"
+#include "llvm/MC/MCAssembler.h"
+#include "llvm/MC/MCAsmLayout.h"
 #include "llvm/MC/MCMachObjectWriter.h"
+#include "llvm/MC/MCSectionMachO.h"
+#include "llvm/MC/MCValue.h"
+#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Object/MachOFormat.h"
+
 using namespace llvm;
+using namespace llvm::object;
 
 namespace {
 class X86MachObjectWriter : public MCMachObjectTargetWriter {
+  void RecordScatteredRelocation(MachObjectWriter *Writer,
+                                 const MCAssembler &Asm,
+                                 const MCAsmLayout &Layout,
+                                 const MCFragment *Fragment,
+                                 const MCFixup &Fixup,
+                                 MCValue Target,
+                                 unsigned Log2Size,
+                                 uint64_t &FixedValue);
+  void RecordTLVPRelocation(MachObjectWriter *Writer,
+                            const MCAssembler &Asm,
+                            const MCAsmLayout &Layout,
+                            const MCFragment *Fragment,
+                            const MCFixup &Fixup,
+                            MCValue Target,
+                            uint64_t &FixedValue);
+
+  void RecordX86Relocation(MachObjectWriter *Writer,
+                              const MCAssembler &Asm,
+                              const MCAsmLayout &Layout,
+                              const MCFragment *Fragment,
+                              const MCFixup &Fixup,
+                              MCValue Target,
+                              uint64_t &FixedValue);
+  void RecordX86_64Relocation(MachObjectWriter *Writer,
+                              const MCAssembler &Asm,
+                              const MCAsmLayout &Layout,
+                              const MCFragment *Fragment,
+                              const MCFixup &Fixup,
+                              MCValue Target,
+                              uint64_t &FixedValue);
 public:
   X86MachObjectWriter(bool Is64Bit, uint32_t CPUType,
                       uint32_t CPUSubtype)
     : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype,
                                /*UseAggressiveSymbolFolding=*/Is64Bit) {}
+
+  void RecordRelocation(MachObjectWriter *Writer,
+                        const MCAssembler &Asm, const MCAsmLayout &Layout,
+                        const MCFragment *Fragment, const MCFixup &Fixup,
+                        MCValue Target, uint64_t &FixedValue) {
+    if (Writer->is64Bit())
+      RecordX86_64Relocation(Writer, Asm, Layout, Fragment, Fixup, Target,
+                             FixedValue);
+    else
+      RecordX86Relocation(Writer, Asm, Layout, Fragment, Fixup, Target,
+                          FixedValue);
+  }
 };
 }
 
+static bool isFixupKindRIPRel(unsigned Kind) {
+  return Kind == X86::reloc_riprel_4byte ||
+    Kind == X86::reloc_riprel_4byte_movq_load;
+}
+
+static unsigned getFixupKindLog2Size(unsigned Kind) {
+  switch (Kind) {
+  default:
+    llvm_unreachable("invalid fixup kind!");
+  case FK_PCRel_1:
+  case FK_Data_1: return 0;
+  case FK_PCRel_2:
+  case FK_Data_2: return 1;
+  case FK_PCRel_4:
+    // FIXME: Remove these!!!
+  case X86::reloc_riprel_4byte:
+  case X86::reloc_riprel_4byte_movq_load:
+  case X86::reloc_signed_4byte:
+  case FK_Data_4: return 2;
+  case FK_Data_8: return 3;
+  }
+}
+
+void X86MachObjectWriter::RecordX86_64Relocation(MachObjectWriter *Writer,
+                                                 const MCAssembler &Asm,
+                                                 const MCAsmLayout &Layout,
+                                                 const MCFragment *Fragment,
+                                                 const MCFixup &Fixup,
+                                                 MCValue Target,
+                                                 uint64_t &FixedValue) {
+  unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned IsRIPRel = isFixupKindRIPRel(Fixup.getKind());
+  unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
+
+  // See <reloc.h>.
+  uint32_t FixupOffset =
+    Layout.getFragmentOffset(Fragment) + Fixup.getOffset();
+  uint32_t FixupAddress =
+    Writer->getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
+  int64_t Value = 0;
+  unsigned Index = 0;
+  unsigned IsExtern = 0;
+  unsigned Type = 0;
+
+  Value = Target.getConstant();
+
+  if (IsPCRel) {
+    // Compensate for the relocation offset, Darwin x86_64 relocations only have
+    // the addend and appear to have attempted to define it to be the actual
+    // expression addend without the PCrel bias. However, instructions with data
+    // following the relocation are not accommodated for (see comment below
+    // regarding SIGNED{1,2,4}), so it isn't exactly that either.
+    Value += 1LL << Log2Size;
+  }
+
+  if (Target.isAbsolute()) { // constant
+    // SymbolNum of 0 indicates the absolute section.
+    Type = macho::RIT_X86_64_Unsigned;
+    Index = 0;
+
+    // FIXME: I believe this is broken, I don't think the linker can understand
+    // it. I think it would require a local relocation, but I'm not sure if that
+    // would work either. The official way to get an absolute PCrel relocation
+    // is to use an absolute symbol (which we don't support yet).
+    if (IsPCRel) {
+      IsExtern = 1;
+      Type = macho::RIT_X86_64_Branch;
+    }
+  } else if (Target.getSymB()) { // A - B + constant
+    const MCSymbol *A = &Target.getSymA()->getSymbol();
+    MCSymbolData &A_SD = Asm.getSymbolData(*A);
+    const MCSymbolData *A_Base = Asm.getAtom(&A_SD);
+
+    const MCSymbol *B = &Target.getSymB()->getSymbol();
+    MCSymbolData &B_SD = Asm.getSymbolData(*B);
+    const MCSymbolData *B_Base = Asm.getAtom(&B_SD);
+
+    // Neither symbol can be modified.
+    if (Target.getSymA()->getKind() != MCSymbolRefExpr::VK_None ||
+        Target.getSymB()->getKind() != MCSymbolRefExpr::VK_None)
+      report_fatal_error("unsupported relocation of modified symbol");
+
+    // We don't support PCrel relocations of differences. Darwin 'as' doesn't
+    // implement most of these correctly.
+    if (IsPCRel)
+      report_fatal_error("unsupported pc-relative relocation of difference");
+
+    // The support for the situation where one or both of the symbols would
+    // require a local relocation is handled just like if the symbols were
+    // external.  This is certainly used in the case of debug sections where the
+    // section has only temporary symbols and thus the symbols don't have base
+    // symbols.  This is encoded using the section ordinal and non-extern
+    // relocation entries.
+
+    // Darwin 'as' doesn't emit correct relocations for this (it ends up with a
+    // single SIGNED relocation); reject it for now.  Except the case where both
+    // symbols don't have a base, equal but both NULL.
+    if (A_Base == B_Base && A_Base)
+      report_fatal_error("unsupported relocation with identical base");
+
+    Value += Writer->getSymbolAddress(&A_SD, Layout) -
+      (A_Base == NULL ? 0 : Writer->getSymbolAddress(A_Base, Layout));
+    Value -= Writer->getSymbolAddress(&B_SD, Layout) -
+      (B_Base == NULL ? 0 : Writer->getSymbolAddress(B_Base, Layout));
+
+    if (A_Base) {
+      Index = A_Base->getIndex();
+      IsExtern = 1;
+    }
+    else {
+      Index = A_SD.getFragment()->getParent()->getOrdinal() + 1;
+      IsExtern = 0;
+    }
+    Type = macho::RIT_X86_64_Unsigned;
+
+    macho::RelocationEntry MRE;
+    MRE.Word0 = FixupOffset;
+    MRE.Word1 = ((Index     <<  0) |
+                 (IsPCRel   << 24) |
+                 (Log2Size  << 25) |
+                 (IsExtern  << 27) |
+                 (Type      << 28));
+    Writer->addRelocation(Fragment->getParent(), MRE);
+
+    if (B_Base) {
+      Index = B_Base->getIndex();
+      IsExtern = 1;
+    }
+    else {
+      Index = B_SD.getFragment()->getParent()->getOrdinal() + 1;
+      IsExtern = 0;
+    }
+    Type = macho::RIT_X86_64_Subtractor;
+  } else {
+    const MCSymbol *Symbol = &Target.getSymA()->getSymbol();
+    MCSymbolData &SD = Asm.getSymbolData(*Symbol);
+    const MCSymbolData *Base = Asm.getAtom(&SD);
+
+    // Relocations inside debug sections always use local relocations when
+    // possible. This seems to be done because the debugger doesn't fully
+    // understand x86_64 relocation entries, and expects to find values that
+    // have already been fixed up.
+    if (Symbol->isInSection()) {
+      const MCSectionMachO &Section = static_cast<const MCSectionMachO&>(
+        Fragment->getParent()->getSection());
+      if (Section.hasAttribute(MCSectionMachO::S_ATTR_DEBUG))
+        Base = 0;
+    }
+
+    // x86_64 almost always uses external relocations, except when there is no
+    // symbol to use as a base address (a local symbol with no preceding
+    // non-local symbol).
+    if (Base) {
+      Index = Base->getIndex();
+      IsExtern = 1;
+
+      // Add the local offset, if needed.
+      if (Base != &SD)
+        Value += Layout.getSymbolOffset(&SD) - Layout.getSymbolOffset(Base);
+    } else if (Symbol->isInSection() && !Symbol->isVariable()) {
+      // The index is the section ordinal (1-based).
+      Index = SD.getFragment()->getParent()->getOrdinal() + 1;
+      IsExtern = 0;
+      Value += Writer->getSymbolAddress(&SD, Layout);
+
+      if (IsPCRel)
+        Value -= FixupAddress + (1 << Log2Size);
+    } else if (Symbol->isVariable()) {
+      const MCExpr *Value = Symbol->getVariableValue();
+      int64_t Res;
+      bool isAbs = Value->EvaluateAsAbsolute(Res, Layout,
+                                             Writer->getSectionAddressMap());
+      if (isAbs) {
+        FixedValue = Res;
+        return;
+      } else {
+        report_fatal_error("unsupported relocation of variable '" +
+                           Symbol->getName() + "'");
+      }
+    } else {
+      report_fatal_error("unsupported relocation of undefined symbol '" +
+                         Symbol->getName() + "'");
+    }
+
+    MCSymbolRefExpr::VariantKind Modifier = Target.getSymA()->getKind();
+    if (IsPCRel) {
+      if (IsRIPRel) {
+        if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
+          // x86_64 distinguishes movq foo at GOTPCREL so that the linker can
+          // rewrite the movq to an leaq at link time if the symbol ends up in
+          // the same linkage unit.
+          if (unsigned(Fixup.getKind()) == X86::reloc_riprel_4byte_movq_load)
+            Type = macho::RIT_X86_64_GOTLoad;
+          else
+            Type = macho::RIT_X86_64_GOT;
+        }  else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
+          Type = macho::RIT_X86_64_TLV;
+        }  else if (Modifier != MCSymbolRefExpr::VK_None) {
+          report_fatal_error("unsupported symbol modifier in relocation");
+        } else {
+          Type = macho::RIT_X86_64_Signed;
+
+          // The Darwin x86_64 relocation format has a problem where it cannot
+          // encode an address (L<foo> + <constant>) which is outside the atom
+          // containing L<foo>. Generally, this shouldn't occur but it does
+          // happen when we have a RIPrel instruction with data following the
+          // relocation entry (e.g., movb $012, L0(%rip)). Even with the PCrel
+          // adjustment Darwin x86_64 uses, the offset is still negative and the
+          // linker has no way to recognize this.
+          //
+          // To work around this, Darwin uses several special relocation types
+          // to indicate the offsets. However, the specification or
+          // implementation of these seems to also be incomplete; they should
+          // adjust the addend as well based on the actual encoded instruction
+          // (the additional bias), but instead appear to just look at the final
+          // offset.
+          switch (-(Target.getConstant() + (1LL << Log2Size))) {
+          case 1: Type = macho::RIT_X86_64_Signed1; break;
+          case 2: Type = macho::RIT_X86_64_Signed2; break;
+          case 4: Type = macho::RIT_X86_64_Signed4; break;
+          }
+        }
+      } else {
+        if (Modifier != MCSymbolRefExpr::VK_None)
+          report_fatal_error("unsupported symbol modifier in branch "
+                             "relocation");
+
+        Type = macho::RIT_X86_64_Branch;
+      }
+    } else {
+      if (Modifier == MCSymbolRefExpr::VK_GOT) {
+        Type = macho::RIT_X86_64_GOT;
+      } else if (Modifier == MCSymbolRefExpr::VK_GOTPCREL) {
+        // GOTPCREL is allowed as a modifier on non-PCrel instructions, in which
+        // case all we do is set the PCrel bit in the relocation entry; this is
+        // used with exception handling, for example. The source is required to
+        // include any necessary offset directly.
+        Type = macho::RIT_X86_64_GOT;
+        IsPCRel = 1;
+      } else if (Modifier == MCSymbolRefExpr::VK_TLVP) {
+        report_fatal_error("TLVP symbol modifier should have been rip-rel");
+      } else if (Modifier != MCSymbolRefExpr::VK_None)
+        report_fatal_error("unsupported symbol modifier in relocation");
+      else
+        Type = macho::RIT_X86_64_Unsigned;
+    }
+  }
+
+  // x86_64 always writes custom values into the fixups.
+  FixedValue = Value;
+
+  // struct relocation_info (8 bytes)
+  macho::RelocationEntry MRE;
+  MRE.Word0 = FixupOffset;
+  MRE.Word1 = ((Index     <<  0) |
+               (IsPCRel   << 24) |
+               (Log2Size  << 25) |
+               (IsExtern  << 27) |
+               (Type      << 28));
+  Writer->addRelocation(Fragment->getParent(), MRE);
+}
+
+void X86MachObjectWriter::RecordScatteredRelocation(MachObjectWriter *Writer,
+                                                    const MCAssembler &Asm,
+                                                    const MCAsmLayout &Layout,
+                                                    const MCFragment *Fragment,
+                                                    const MCFixup &Fixup,
+                                                    MCValue Target,
+                                                    unsigned Log2Size,
+                                                    uint64_t &FixedValue) {
+  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned Type = macho::RIT_Vanilla;
+
+  // See <reloc.h>.
+  const MCSymbol *A = &Target.getSymA()->getSymbol();
+  MCSymbolData *A_SD = &Asm.getSymbolData(*A);
+
+  if (!A_SD->getFragment())
+    report_fatal_error("symbol '" + A->getName() +
+                       "' can not be undefined in a subtraction expression");
+
+  uint32_t Value = Writer->getSymbolAddress(A_SD, Layout);
+  uint64_t SecAddr = Writer->getSectionAddress(A_SD->getFragment()->getParent());
+  FixedValue += SecAddr;
+  uint32_t Value2 = 0;
+
+  if (const MCSymbolRefExpr *B = Target.getSymB()) {
+    MCSymbolData *B_SD = &Asm.getSymbolData(B->getSymbol());
+
+    if (!B_SD->getFragment())
+      report_fatal_error("symbol '" + B->getSymbol().getName() +
+                         "' can not be undefined in a subtraction expression");
+
+    // Select the appropriate difference relocation type.
+    //
+    // Note that there is no longer any semantic difference between these two
+    // relocation types from the linkers point of view, this is done solely for
+    // pedantic compatibility with 'as'.
+    Type = A_SD->isExternal() ? (unsigned)macho::RIT_Difference :
+      (unsigned)macho::RIT_Generic_LocalDifference;
+    Value2 = Writer->getSymbolAddress(B_SD, Layout);
+    FixedValue -= Writer->getSectionAddress(B_SD->getFragment()->getParent());
+  }
+
+  // Relocations are written out in reverse order, so the PAIR comes first.
+  if (Type == macho::RIT_Difference ||
+      Type == macho::RIT_Generic_LocalDifference) {
+    macho::RelocationEntry MRE;
+    MRE.Word0 = ((0         <<  0) |
+                 (macho::RIT_Pair  << 24) |
+                 (Log2Size  << 28) |
+                 (IsPCRel   << 30) |
+                 macho::RF_Scattered);
+    MRE.Word1 = Value2;
+    Writer->addRelocation(Fragment->getParent(), MRE);
+  }
+
+  macho::RelocationEntry MRE;
+  MRE.Word0 = ((FixupOffset <<  0) |
+               (Type        << 24) |
+               (Log2Size    << 28) |
+               (IsPCRel     << 30) |
+               macho::RF_Scattered);
+  MRE.Word1 = Value;
+  Writer->addRelocation(Fragment->getParent(), MRE);
+}
+
+void X86MachObjectWriter::RecordTLVPRelocation(MachObjectWriter *Writer,
+                                               const MCAssembler &Asm,
+                                               const MCAsmLayout &Layout,
+                                               const MCFragment *Fragment,
+                                               const MCFixup &Fixup,
+                                               MCValue Target,
+                                               uint64_t &FixedValue) {
+  assert(Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP &&
+         !is64Bit() &&
+         "Should only be called with a 32-bit TLVP relocation!");
+
+  unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
+  uint32_t Value = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned IsPCRel = 0;
+
+  // Get the symbol data.
+  MCSymbolData *SD_A = &Asm.getSymbolData(Target.getSymA()->getSymbol());
+  unsigned Index = SD_A->getIndex();
+
+  // We're only going to have a second symbol in pic mode and it'll be a
+  // subtraction from the picbase. For 32-bit pic the addend is the difference
+  // between the picbase and the next address.  For 32-bit static the addend is
+  // zero.
+  if (Target.getSymB()) {
+    // If this is a subtraction then we're pcrel.
+    uint32_t FixupAddress =
+      Writer->getFragmentAddress(Fragment, Layout) + Fixup.getOffset();
+    MCSymbolData *SD_B = &Asm.getSymbolData(Target.getSymB()->getSymbol());
+    IsPCRel = 1;
+    FixedValue = (FixupAddress - Writer->getSymbolAddress(SD_B, Layout) +
+                  Target.getConstant());
+    FixedValue += 1ULL << Log2Size;
+  } else {
+    FixedValue = 0;
+  }
+
+  // struct relocation_info (8 bytes)
+  macho::RelocationEntry MRE;
+  MRE.Word0 = Value;
+  MRE.Word1 = ((Index                  <<  0) |
+               (IsPCRel                << 24) |
+               (Log2Size               << 25) |
+               (1                      << 27) | // Extern
+               (macho::RIT_Generic_TLV << 28)); // Type
+  Writer->addRelocation(Fragment->getParent(), MRE);
+}
+
+void X86MachObjectWriter::RecordX86Relocation(MachObjectWriter *Writer,
+                                              const MCAssembler &Asm,
+                                              const MCAsmLayout &Layout,
+                                              const MCFragment *Fragment,
+                                              const MCFixup &Fixup,
+                                              MCValue Target,
+                                              uint64_t &FixedValue) {
+  unsigned IsPCRel = Writer->isFixupKindPCRel(Asm, Fixup.getKind());
+  unsigned Log2Size = getFixupKindLog2Size(Fixup.getKind());
+
+  // If this is a 32-bit TLVP reloc it's handled a bit differently.
+  if (Target.getSymA() &&
+      Target.getSymA()->getKind() == MCSymbolRefExpr::VK_TLVP) {
+    RecordTLVPRelocation(Writer, Asm, Layout, Fragment, Fixup, Target,
+                         FixedValue);
+    return;
+  }
+
+  // If this is a difference or a defined symbol plus an offset, then we need a
+  // scattered relocation entry. Differences always require scattered
+  // relocations.
+  if (Target.getSymB())
+    return RecordScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
+                                     Target, Log2Size, FixedValue);
+
+  // Get the symbol data, if any.
+  MCSymbolData *SD = 0;
+  if (Target.getSymA())
+    SD = &Asm.getSymbolData(Target.getSymA()->getSymbol());
+
+  // If this is an internal relocation with an offset, it also needs a scattered
+  // relocation entry.
+  uint32_t Offset = Target.getConstant();
+  if (IsPCRel)
+    Offset += 1 << Log2Size;
+  if (Offset && SD && !Writer->doesSymbolRequireExternRelocation(SD))
+    return RecordScatteredRelocation(Writer, Asm, Layout, Fragment, Fixup,
+                                     Target, Log2Size, FixedValue);
+
+  // See <reloc.h>.
+  uint32_t FixupOffset = Layout.getFragmentOffset(Fragment)+Fixup.getOffset();
+  unsigned Index = 0;
+  unsigned IsExtern = 0;
+  unsigned Type = 0;
+
+  if (Target.isAbsolute()) { // constant
+    // SymbolNum of 0 indicates the absolute section.
+    //
+    // FIXME: Currently, these are never generated (see code below). I cannot
+    // find a case where they are actually emitted.
+    Type = macho::RIT_Vanilla;
+  } else {
+    // Resolve constant variables.
+    if (SD->getSymbol().isVariable()) {
+      int64_t Res;
+      if (SD->getSymbol().getVariableValue()->EvaluateAsAbsolute(
+            Res, Layout, Writer->getSectionAddressMap())) {
+        FixedValue = Res;
+        return;
+      }
+    }
+
+    // Check whether we need an external or internal relocation.
+    if (Writer->doesSymbolRequireExternRelocation(SD)) {
+      IsExtern = 1;
+      Index = SD->getIndex();
+      // For external relocations, make sure to offset the fixup value to
+      // compensate for the addend of the symbol address, if it was
+      // undefined. This occurs with weak definitions, for example.
+      if (!SD->Symbol->isUndefined())
+        FixedValue -= Layout.getSymbolOffset(SD);
+    } else {
+      // The index is the section ordinal (1-based).
+      const MCSectionData &SymSD = Asm.getSectionData(
+        SD->getSymbol().getSection());
+      Index = SymSD.getOrdinal() + 1;
+      FixedValue += Writer->getSectionAddress(&SymSD);
+    }
+    if (IsPCRel)
+      FixedValue -= Writer->getSectionAddress(Fragment->getParent());
+
+    Type = macho::RIT_Vanilla;
+  }
+
+  // struct relocation_info (8 bytes)
+  macho::RelocationEntry MRE;
+  MRE.Word0 = FixupOffset;
+  MRE.Word1 = ((Index     <<  0) |
+               (IsPCRel   << 24) |
+               (Log2Size  << 25) |
+               (IsExtern  << 27) |
+               (Type      << 28));
+  Writer->addRelocation(Fragment->getParent(), MRE);
+}
+
 MCObjectWriter *llvm::createX86MachObjectWriter(raw_ostream &OS,
                                                 bool Is64Bit,
                                                 uint32_t CPUType,



From evan.cheng at apple.com  Fri Jun 24 18:44:48 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Jun 2011 23:44:48 -0000
Subject: [llvm-commits] [llvm] r133845 - in /llvm/trunk:
 include/llvm/MC/MCRegisterInfo.h include/llvm/Target/TargetRegisterInfo.h
 utils/TableGen/RegisterInfoEmitter.cpp
Message-ID: <20110624234448.3BDF72A6C12C@llvm.org>

Author: evancheng
Date: Fri Jun 24 18:44:48 2011
New Revision: 133845

URL: http://llvm.org/viewvc/llvm-project?rev=133845&view=rev
Log:
Rename TargetRegisterDesc to MCRegisterDesc

Modified:
    llvm/trunk/include/llvm/MC/MCRegisterInfo.h
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/MC/MCRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCRegisterInfo.h?rev=133845&r1=133844&r2=133845&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/MCRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Fri Jun 24 18:44:48 2011
@@ -20,7 +20,7 @@
 
 namespace llvm {
 
-/// TargetRegisterDesc - This record contains all of the information known about
+/// MCRegisterDesc - This record contains all of the information known about
 /// a particular register.  The Overlaps field contains a pointer to a zero
 /// terminated array of registers that this register aliases, starting with
 /// itself. This is needed for architectures like X86 which have AL alias AX
@@ -38,7 +38,7 @@
 };
 
 /// MCRegisterInfo base class - We assume that the target defines a static
-/// array of TargetRegisterDesc objects that represent all of the machine
+/// array of MCRegisterDesc objects that represent all of the machine
 /// registers that the target has.  As such, we simply have to track a pointer
 /// to this array so that we can turn register number into a register
 /// descriptor.

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=133845&r1=133844&r2=133845&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Fri Jun 24 18:44:48 2011
@@ -256,9 +256,6 @@
   bool isAllocatable() const { return Allocatable; }
 };
 
-/// TargetRegisterDesc - It's just an alias of MCRegisterDesc.
-typedef MCRegisterDesc TargetRegisterDesc;
-
 /// TargetRegisterInfoDesc - Extra information, not in MCRegisterDesc, about
 /// registers. These are used by codegen, not by MC.
 struct TargetRegisterInfoDesc {

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=133845&r1=133844&r2=133845&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Jun 24 18:44:48 2011
@@ -79,7 +79,7 @@
 
   OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
      << "  explicit " << ClassName
-     << "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
+     << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
      << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
      << "  virtual int getDwarfRegNumFull(unsigned RegNum, "
      << "unsigned Flavour) const;\n"
@@ -518,7 +518,7 @@
 
   // Emit the constructor of the class...
   OS << ClassName << "::" << ClassName
-     << "(const TargetRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
+     << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, "
      << "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
      << "  : TargetRegisterInfo(ID"
      << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"



From evan.cheng at apple.com  Fri Jun 24 18:53:20 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Jun 2011 23:53:20 -0000
Subject: [llvm-commits] [llvm] r133846 - in /llvm/trunk/lib/Target/X86:
 CMakeLists.txt MCTargetDesc/ MCTargetDesc/X86TargetDesc.cpp
 MCTargetDesc/X86TargetDesc.h Makefile TargetDesc/ X86.h
Message-ID: <20110624235320.395A82A6C12C@llvm.org>

Author: evancheng
Date: Fri Jun 24 18:53:19 2011
New Revision: 133846

URL: http://llvm.org/viewvc/llvm-project?rev=133846&view=rev
Log:
Rename TargetDesc to MCTargetDesc

Added:
    llvm/trunk/lib/Target/X86/MCTargetDesc/
      - copied from r133805, llvm/trunk/lib/Target/X86/TargetDesc/
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
      - copied unchanged from r133820, llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
      - copied unchanged from r133820, llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h
Removed:
    llvm/trunk/lib/Target/X86/TargetDesc/
Modified:
    llvm/trunk/lib/Target/X86/CMakeLists.txt
    llvm/trunk/lib/Target/X86/Makefile
    llvm/trunk/lib/Target/X86/X86.h

Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=133846&r1=133845&r2=133846&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/X86/CMakeLists.txt Fri Jun 24 18:53:19 2011
@@ -61,5 +61,6 @@
 add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)
 add_subdirectory(InstPrinter)
+add_subdirectory(MCTargetDesc)
 add_subdirectory(TargetInfo)
 add_subdirectory(Utils)

Modified: llvm/trunk/lib/Target/X86/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Makefile?rev=133846&r1=133845&r2=133846&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Makefile (original)
+++ llvm/trunk/lib/Target/X86/Makefile Fri Jun 24 18:53:19 2011
@@ -21,6 +21,6 @@
                 X86GenCallingConv.inc X86GenSubtarget.inc \
 		X86GenEDInfo.inc
 
-DIRS = InstPrinter AsmParser Disassembler TargetInfo TargetDesc Utils
+DIRS = InstPrinter AsmParser Disassembler TargetInfo MCTargetDesc Utils
 
 include $(LEVEL)/Makefile.common

Modified: llvm/trunk/lib/Target/X86/X86.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=133846&r1=133845&r2=133846&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.h (original)
+++ llvm/trunk/lib/Target/X86/X86.h Fri Jun 24 18:53:19 2011
@@ -84,11 +84,9 @@
                                           uint32_t CPUType,
                                           uint32_t CPUSubtype);
 
-extern Target TheX86_32Target, TheX86_64Target;
-
 } // End llvm namespace
 
-#include "TargetDesc/X86TargetDesc.h"
+#include "MCTargetDesc/X86TargetDesc.h"
 
 // Defines symbolic names for the X86 instructions.
 //



From echristo at apple.com  Fri Jun 24 19:04:45 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 24 Jun 2011 17:04:45 -0700
Subject: [llvm-commits] [llvm] r133844 - in /llvm/trunk:
 include/llvm/MC/MCMachObjectWriter.h lib/MC/MachObjectWriter.cpp
 lib/Target/ARM/ARMMachObjectWriter.cpp lib/Target/PowerPC/PPCAsmBackend.cpp
 lib/Target/X86/X86MachObjectWriter.cpp
In-Reply-To: <20110624234437.6A95A2A6C12C@llvm.org>
References: <20110624234437.6A95A2A6C12C@llvm.org>
Message-ID: <E8149C79-3ABE-4700-8F10-16E8F3BEB3CD@apple.com>


On Jun 24, 2011, at 4:44 PM, Jim Grosbach wrote:

> Refactor MachO relocation generaration into the Target directories.
> 
> Move the target-specific RecordRelocation logic out of the generic MC
> MachObjectWriter and into the target-specific object writers. This allows
> nuking quite a bit of target knowledge from the supposedly target-independent
> bits in lib/MC.

Oh, excellent.

-eric

From eli.friedman at gmail.com  Fri Jun 24 19:05:46 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Fri, 24 Jun 2011 17:05:46 -0700
Subject: [llvm-commits] [llvm] r133756 - in /llvm/trunk:
 lib/Transforms/InstCombine/InstCombineSelect.cpp
 test/Transforms/InstCombine/select-crash.ll
In-Reply-To: <4E0443BB.1070306@free.fr>
References: <20110623204024.1B1392A6C12C@llvm.org> <4E0443BB.1070306@free.fr>
Message-ID: <BANLkTi=euFd2kgEhM4P-7qdi2w=UogPMBA@mail.gmail.com>

On Fri, Jun 24, 2011 at 12:58 AM, Duncan Sands <baldrick at free.fr> wrote:
> Hi Eli,
>
>> PR10180: Fix a instcombine crash with FP vectors.
>
> maybe it would be better if the IRBuilder got a CreateAnyAdd method that
> handles both fp and integers.

Hmm... I think it's better to be explicit here; the two kinds of
addition are only very loosely related.

-Eli

From evan.cheng at apple.com  Fri Jun 24 18:59:54 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 24 Jun 2011 23:59:54 -0000
Subject: [llvm-commits] [llvm] r133847 -
	/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
Message-ID: <20110624235954.375742A6C12C@llvm.org>

Author: evancheng
Date: Fri Jun 24 18:59:54 2011
New Revision: 133847

URL: http://llvm.org/viewvc/llvm-project?rev=133847&view=rev
Log:
Add include guard.

Modified:
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h?rev=133847&r1=133846&r2=133847&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h Fri Jun 24 18:59:54 2011
@@ -11,6 +11,9 @@
 //
 //===----------------------------------------------------------------------===//
 
+#ifndef X86TARGETDESC_H
+#define X86TARGETDESC_H
+
 namespace llvm {
 class Target;
 
@@ -21,3 +24,5 @@
 // register name to register number.
 //
 #include "X86GenRegisterNames.inc"
+
+#endif



From evan.cheng at apple.com  Fri Jun 24 19:27:17 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Sat, 25 Jun 2011 00:27:17 -0000
Subject: [llvm-commits] [llvm] r133851 -
	/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
Message-ID: <20110625002717.B939F2A6C12C@llvm.org>

Author: evancheng
Date: Fri Jun 24 19:27:17 2011
New Revision: 133851

URL: http://llvm.org/viewvc/llvm-project?rev=133851&view=rev
Log:
Remove dead typedefs.

Modified:
    llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=133851&r1=133850&r2=133851&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Fri Jun 24 19:27:17 2011
@@ -131,9 +131,6 @@
   OS << "} // End llvm namespace \n";
 }
 
-typedef std::pair<unsigned, unsigned> UUPair;
-typedef std::vector<UUPair> UUVector;
-
 //
 // RegisterInfoEmitter::run - Main register file description emitter.
 //



From dgregor at apple.com  Fri Jun 24 19:48:48 2011
From: dgregor at apple.com (Douglas Gregor)
Date: Fri, 24 Jun 2011 17:48:48 -0700
Subject: [llvm-commits] [llvm] r133846 - in /llvm/trunk/lib/Target/X86:
 CMakeLists.txt MCTargetDesc/ MCTargetDesc/X86TargetDesc.cpp
 MCTargetDesc/X86TargetDesc.h Makefile TargetDesc/ X86.h
In-Reply-To: <20110624235320.395A82A6C12C@llvm.org>
References: <20110624235320.395A82A6C12C@llvm.org>
Message-ID: <0ABEA6B1-815A-4C96-8D43-DD1CE8F2D5DF@apple.com>


On Jun 24, 2011, at 4:53 PM, Evan Cheng wrote:

> Author: evancheng
> Date: Fri Jun 24 18:53:19 2011
> New Revision: 133846
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133846&view=rev
> Log:
> Rename TargetDesc to MCTargetDesc
> 
> Added:
>    llvm/trunk/lib/Target/X86/MCTargetDesc/
>      - copied from r133805, llvm/trunk/lib/Target/X86/TargetDesc/
>    llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
>      - copied unchanged from r133820, llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp
>    llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
>      - copied unchanged from r133820, llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h
> Removed:
>    llvm/trunk/lib/Target/X86/TargetDesc/
> Modified:
>    llvm/trunk/lib/Target/X86/CMakeLists.txt
>    llvm/trunk/lib/Target/X86/Makefile
>    llvm/trunk/lib/Target/X86/X86.h

It looks like we're missing a CMakeLists.txt file in the MCTargetDesc subdirectory?

	- Doug

From dgregor at apple.com  Fri Jun 24 19:51:50 2011
From: dgregor at apple.com (Douglas Gregor)
Date: Sat, 25 Jun 2011 00:51:50 -0000
Subject: [llvm-commits] [llvm] r133853 -
	/llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt
Message-ID: <20110625005150.3F0FA2A6C12C@llvm.org>

Author: dgregor
Date: Fri Jun 24 19:51:50 2011
New Revision: 133853

URL: http://llvm.org/viewvc/llvm-project?rev=133853&view=rev
Log:
Unbreak CMake build

Added:
    llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt

Added: llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt?rev=133853&view=auto
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt (added)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/CMakeLists.txt Fri Jun 24 19:51:50 2011
@@ -0,0 +1,2 @@
+add_llvm_library(LLVMX86Desc X86TargetDesc.cpp)
+



From dgregor at apple.com  Fri Jun 24 19:57:56 2011
From: dgregor at apple.com (Douglas Gregor)
Date: Fri, 24 Jun 2011 17:57:56 -0700
Subject: [llvm-commits] [llvm] r133846 - in /llvm/trunk/lib/Target/X86:
 CMakeLists.txt MCTargetDesc/ MCTargetDesc/X86TargetDesc.cpp
 MCTargetDesc/X86TargetDesc.h Makefile TargetDesc/ X86.h
In-Reply-To: <0ABEA6B1-815A-4C96-8D43-DD1CE8F2D5DF@apple.com>
References: <20110624235320.395A82A6C12C@llvm.org>
	<0ABEA6B1-815A-4C96-8D43-DD1CE8F2D5DF@apple.com>
Message-ID: <D0A1E9EC-8876-4C67-9FE2-9A8383E93878@apple.com>


On Jun 24, 2011, at 5:48 PM, Douglas Gregor wrote:

> 
> On Jun 24, 2011, at 4:53 PM, Evan Cheng wrote:
> 
>> Author: evancheng
>> Date: Fri Jun 24 18:53:19 2011
>> New Revision: 133846
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=133846&view=rev
>> Log:
>> Rename TargetDesc to MCTargetDesc
>> 
>> Added:
>>   llvm/trunk/lib/Target/X86/MCTargetDesc/
>>     - copied from r133805, llvm/trunk/lib/Target/X86/TargetDesc/
>>   llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
>>     - copied unchanged from r133820, llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.cpp
>>   llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h
>>     - copied unchanged from r133820, llvm/trunk/lib/Target/X86/TargetDesc/X86TargetDesc.h
>> Removed:
>>   llvm/trunk/lib/Target/X86/TargetDesc/
>> Modified:
>>   llvm/trunk/lib/Target/X86/CMakeLists.txt
>>   llvm/trunk/lib/Target/X86/Makefile
>>   llvm/trunk/lib/Target/X86/X86.h
> 
> It looks like we're missing a CMakeLists.txt file in the MCTargetDesc subdirectory?


Meh, I fixed it.

	- Doug

From pichet2000 at gmail.com  Fri Jun 24 20:01:19 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Fri, 24 Jun 2011 21:01:19 -0400
Subject: [llvm-commits] [llvm] r133823 -
	/llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
In-Reply-To: <20110624205901.C88722A6C12C@llvm.org>
References: <20110624205901.C88722A6C12C@llvm.org>
Message-ID: <BANLkTinpazPw-YCH8E=Td2_0wz=SQgapHQ@mail.gmail.com>

On Fri, Jun 24, 2011 at 4:59 PM, Jim Grosbach <grosbach at apple.com> wrote:
> Author: grosbach
> Date: Fri Jun 24 15:59:01 2011
> New Revision: 133823
>
> URL: http://llvm.org/viewvc/llvm-project?rev=133823&view=rev
> Log:
> Testcase for r133818
>
> Added:
> ? ?llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
>
> Added: llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s?rev=133823&view=auto
> ==============================================================================
> --- llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s (added)
> +++ llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s Fri Jun 24 15:59:01 2011
> @@ -0,0 +1,17 @@
> +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-apple-darwin10 -filetype=obj -o - < %s | macho-dump | FileCheck %s
> +
> +_fred:
> + ? ? ? movt ? ?r3, :upper16:(_wilma-(LPC0_0+4))
> +LPC0_0:
> +
> +_wilma:
> + ?.long 0
> +
> +@ CHECK: ?('_relocations', [
> +@ CHECK: ? ?# Relocation 0
> +@ CHECK: ? ?(('word-0', 0xb9000000),
> +@ CHECK: ? ? ('word-1', 0x4)),
> +@ CHECK: ? ?# Relocation 1
> +@ CHECK: ? ?(('word-0', 0xb100fffc),
> +@ CHECK: ? ? ('word-1', 0x4)),
> +
>

This fails on Windows (MSVC 2010), any idea?

here is the log:

1>  ********************
1>  FAIL: LLVM :: MC/MachO/thumb2-movt-fixup.s (7522 of 9308)
1>  ******************** TEST 'LLVM :: MC/MachO/thumb2-movt-fixup.s'
FAILED ********************
1>  Script:
1>  --
1>  C:/dev/llvm/llvm_trunk2/bin/Release/llvm-mc.EXE -mcpu=cortex-a8
-triple thumbv7-apple-darwin10 -filetype=obj -o - <
C:/dev/llvm/llvm_trunk2/test/MC/MachO/thumb2-movt-fixup.s |
C:/dev/llvm/llvm_trunk2/bin/Release/macho-dump.EXE |
C:/dev/llvm/llvm_trunk2/bin/Release/FileCheck.EXE
C:/dev/llvm/llvm_trunk2/test/MC/MachO/thumb2-movt-fixup.s
1>  --
1>  Exit Code: 1
1>  Command Output (stdout):
1>  --
1>  Command 0: "C:/dev/llvm/llvm_trunk2/bin/Release/llvm-mc.EXE"
"-mcpu=cortex-a8" "-triple" "thumbv7-apple-darwin10" "-filetype=obj"
"-o" "-"
1>  Command 0 Result: 1
1>  Command 0 Output:
1>
1>
1>  Command 0 Stderr:
1>C:/dev/llvm/llvm_trunk2/bin/Release/llvm-mc.EXE : error : unable to
get target for 'thumbv7-apple-darwin10', see --version and --triple.
1>
1>
1>  Command 1: "C:/dev/llvm/llvm_trunk2/bin/Release/macho-dump.EXE"
1>  Command 1 Result: 1
1>  Command 1 Output:
1>
1>
1>  Command 1 Stderr:
1>C:/dev/llvm/llvm_trunk2/bin/Release/macho-dump.EXE : error : unable
to load object: 'not a Mach object file (invalid magic)'
1>
1>
1>  Command 2: "C:/dev/llvm/llvm_trunk2/bin/Release/FileCheck.EXE"
"C:/dev/llvm/llvm_trunk2/test/MC/MachO/thumb2-movt-fixup.s"
1>  Command 2 Result: 1
1>  Command 2 Output:
1>
1>
1>  Command 2 Stderr:
1>CUSTOMBUILD : FileCheck error : '-' is empty.
1>


From grosbach at apple.com  Fri Jun 24 20:15:41 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 24 Jun 2011 18:15:41 -0700
Subject: [llvm-commits] [llvm] r133823 -
 /llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
In-Reply-To: <BANLkTinpazPw-YCH8E=Td2_0wz=SQgapHQ@mail.gmail.com>
References: <20110624205901.C88722A6C12C@llvm.org>
	<BANLkTinpazPw-YCH8E=Td2_0wz=SQgapHQ@mail.gmail.com>
Message-ID: <0FD5E8B4-07A7-47DB-8AC3-DAF79F4D3B1C@apple.com>

The key thing seems to be:
1>C:/dev/llvm/llvm_trunk2/bin/Release/llvm-mc.EXE : error : unable to
get target for 'thumbv7-apple-darwin10', see --version and --triple.

Is this builder building with all targets enabled? If not, that's an easy answer. I'd've expected other tests in that directory to fail, too, though, were that the case.

What happens if you run the same command directly on a command line?

-Jim

On Jun 24, 2011, at 6:01 PM, Francois Pichet wrote:

> On Fri, Jun 24, 2011 at 4:59 PM, Jim Grosbach <grosbach at apple.com> wrote:
>> Author: grosbach
>> Date: Fri Jun 24 15:59:01 2011
>> New Revision: 133823
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=133823&view=rev
>> Log:
>> Testcase for r133818
>> 
>> Added:
>>    llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
>> 
>> Added: llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s?rev=133823&view=auto
>> ==============================================================================
>> --- llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s (added)
>> +++ llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s Fri Jun 24 15:59:01 2011
>> @@ -0,0 +1,17 @@
>> +@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-apple-darwin10 -filetype=obj -o - < %s | macho-dump | FileCheck %s
>> +
>> +_fred:
>> +       movt    r3, :upper16:(_wilma-(LPC0_0+4))
>> +LPC0_0:
>> +
>> +_wilma:
>> +  .long 0
>> +
>> +@ CHECK:  ('_relocations', [
>> +@ CHECK:    # Relocation 0
>> +@ CHECK:    (('word-0', 0xb9000000),
>> +@ CHECK:     ('word-1', 0x4)),
>> +@ CHECK:    # Relocation 1
>> +@ CHECK:    (('word-0', 0xb100fffc),
>> +@ CHECK:     ('word-1', 0x4)),
>> +
>> 
> 
> This fails on Windows (MSVC 2010), any idea?
> 
> here is the log:
> 
> 1>  ********************
> 1>  FAIL: LLVM :: MC/MachO/thumb2-movt-fixup.s (7522 of 9308)
> 1>  ******************** TEST 'LLVM :: MC/MachO/thumb2-movt-fixup.s'
> FAILED ********************
> 1>  Script:
> 1>  --
> 1>  C:/dev/llvm/llvm_trunk2/bin/Release/llvm-mc.EXE -mcpu=cortex-a8
> -triple thumbv7-apple-darwin10 -filetype=obj -o - <
> C:/dev/llvm/llvm_trunk2/test/MC/MachO/thumb2-movt-fixup.s |
> C:/dev/llvm/llvm_trunk2/bin/Release/macho-dump.EXE |
> C:/dev/llvm/llvm_trunk2/bin/Release/FileCheck.EXE
> C:/dev/llvm/llvm_trunk2/test/MC/MachO/thumb2-movt-fixup.s
> 1>  --
> 1>  Exit Code: 1
> 1>  Command Output (stdout):
> 1>  --
> 1>  Command 0: "C:/dev/llvm/llvm_trunk2/bin/Release/llvm-mc.EXE"
> "-mcpu=cortex-a8" "-triple" "thumbv7-apple-darwin10" "-filetype=obj"
> "-o" "-"
> 1>  Command 0 Result: 1
> 1>  Command 0 Output:
> 1>
> 1>
> 1>  Command 0 Stderr:
> 1>C:/dev/llvm/llvm_trunk2/bin/Release/llvm-mc.EXE : error : unable to
> get target for 'thumbv7-apple-darwin10', see --version and --triple.
> 1>
> 1>
> 1>  Command 1: "C:/dev/llvm/llvm_trunk2/bin/Release/macho-dump.EXE"
> 1>  Command 1 Result: 1
> 1>  Command 1 Output:
> 1>
> 1>
> 1>  Command 1 Stderr:
> 1>C:/dev/llvm/llvm_trunk2/bin/Release/macho-dump.EXE : error : unable
> to load object: 'not a Mach object file (invalid magic)'
> 1>
> 1>
> 1>  Command 2: "C:/dev/llvm/llvm_trunk2/bin/Release/FileCheck.EXE"
> "C:/dev/llvm/llvm_trunk2/test/MC/MachO/thumb2-movt-fixup.s"
> 1>  Command 2 Result: 1
> 1>  Command 2 Output:
> 1>
> 1>
> 1>  Command 2 Stderr:
> 1>CUSTOMBUILD : FileCheck error : '-' is empty.
> 1>


From pichet2000 at gmail.com  Fri Jun 24 20:17:07 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Fri, 24 Jun 2011 21:17:07 -0400
Subject: [llvm-commits] [llvm] r133063 - in /llvm/trunk:
 include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/ScheduleDAG.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
 test/CodeGen/X86/2011-06-14-PreschedRega
Message-ID: <BANLkTikmt=JQ4_1EvFXSmfo-g5CErGpOwQ@mail.gmail.com>

This is sad, I recently took the habit of running the llvm tests at
least once a day on Windows (MSVC 2010) and this test is the only one
that constantly fails. I run them in in Release because a Debug run
takes forever and there is no Release+Assert on Windows.

Just saying....

On Wed, Jun 15, 2011 at 1:56 PM, Andrew Trick <atrick at apple.com> wrote:
> Self review: This test will fail in the no-Asserts build because -stress-sched is unavailable. It seems that llvm-lit always picks up the Asserts build. But is there some formal way to indicate that the test should not be run unless built with Asserts?
>
> -Andy
>
> On Jun 15, 2011, at 10:16 AM, Andrew Trick wrote:
>
>> Author: atrick
>> Date: Wed Jun 15 12:16:12 2011
>> New Revision: 133063
>>
>> URL: http://llvm.org/viewvc/llvm-project?rev=133063&view=rev
>> Log:
>> Added -stress-sched flag in the Asserts build.
>> Added a test case for handling physreg aliases during pre-RA-sched.
>>
>> Added:
>> ? ?llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
>> Modified:
>> ? ?llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
>> ? ?llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
>> ? ?llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>> ? ?llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
>>


From pichet2000 at gmail.com  Fri Jun 24 20:23:41 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Fri, 24 Jun 2011 21:23:41 -0400
Subject: [llvm-commits] [llvm] r133823 -
	/llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
In-Reply-To: <0FD5E8B4-07A7-47DB-8AC3-DAF79F4D3B1C@apple.com>
References: <20110624205901.C88722A6C12C@llvm.org>
	<BANLkTinpazPw-YCH8E=Td2_0wz=SQgapHQ@mail.gmail.com>
	<0FD5E8B4-07A7-47DB-8AC3-DAF79F4D3B1C@apple.com>
Message-ID: <BANLkTinC7iWgcPRYpZxEDOb8R3XyYDnRsg@mail.gmail.com>

On Fri, Jun 24, 2011 at 9:15 PM, Jim Grosbach <grosbach at apple.com> wrote:
> The key thing seems to be:
> 1>C:/dev/llvm/llvm_trunk2/bin/Release/llvm-mc.EXE : error : unable to
> get target for 'thumbv7-apple-darwin10', see --version and --triple.
>
> Is this builder building with all targets enabled? If not, that's an easy answer. I'd've expected other tests in that directory to fail, too, though, were that the case.

No only the x86 target is built. Nevertheless all the other tests pass.

>
> What happens if you run the same command directly on a command line?
>
> -Jim
>
> On Jun 24, 2011, at 6:01 PM, Francois Pichet wrote:
>
>> On Fri, Jun 24, 2011 at 4:59 PM, Jim Grosbach <grosbach at apple.com> wrote:
>>> Author: grosbach
>>> Date: Fri Jun 24 15:59:01 2011
>>> New Revision: 133823
>>>
>>> URL: http://llvm.org/viewvc/llvm-project?rev=133823&view=rev

From atrick at apple.com  Fri Jun 24 20:36:41 2011
From: atrick at apple.com (Andrew Trick)
Date: Fri, 24 Jun 2011 18:36:41 -0700
Subject: [llvm-commits] [llvm] r133063 - in /llvm/trunk:
 include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/ScheduleDAG.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
 test/CodeGen/X86/2011-06-14-PreschedRega
In-Reply-To: <BANLkTikmt=JQ4_1EvFXSmfo-g5CErGpOwQ@mail.gmail.com>
References: <BANLkTikmt=JQ4_1EvFXSmfo-g5CErGpOwQ@mail.gmail.com>
Message-ID: <10BEB288-2174-4180-BD44-DFB1C91C6560@apple.com>

Running the tests with the release build is fine. You should not see any failures. This particular test should be skipped as unsupported.

If you're on r133725+, cmake should set the following line in lit "site config" (test/lit.site.cfg)

config.enable_assertions = 0

If you still have a problem, send me the details or file a bug. It should be easy to fix, the only issue here is that I don't have MSVC for testing.

You can disregard my "self-review" comment below. I disabled the test shortly after checking it in until I believed the build system was handling it.

-Andy

On Jun 24, 2011, at 6:17 PM, Francois Pichet wrote:

> This is sad, I recently took the habit of running the llvm tests at
> least once a day on Windows (MSVC 2010) and this test is the only one
> that constantly fails. I run them in in Release because a Debug run
> takes forever and there is no Release+Assert on Windows.
> 
> Just saying....
> 
> On Wed, Jun 15, 2011 at 1:56 PM, Andrew Trick <atrick at apple.com> wrote:
>> Self review: This test will fail in the no-Asserts build because -stress-sched is unavailable. It seems that llvm-lit always picks up the Asserts build. But is there some formal way to indicate that the test should not be run unless built with Asserts?
>> 
>> -Andy
>> 
>> On Jun 15, 2011, at 10:16 AM, Andrew Trick wrote:
>> 
>>> Author: atrick
>>> Date: Wed Jun 15 12:16:12 2011
>>> New Revision: 133063
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=133063&view=rev
>>> Log:
>>> Added -stress-sched flag in the Asserts build.
>>> Added a test case for handling physreg aliases during pre-RA-sched.
>>> 
>>> Added:
>>>    llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
>>> Modified:
>>>    llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
>>>    llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
>>>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>>    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
>>> 


From grosbach at apple.com  Fri Jun 24 20:38:53 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 24 Jun 2011 18:38:53 -0700
Subject: [llvm-commits] [llvm] r133823 -
 /llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
In-Reply-To: <BANLkTinC7iWgcPRYpZxEDOb8R3XyYDnRsg@mail.gmail.com>
References: <20110624205901.C88722A6C12C@llvm.org>
	<BANLkTinpazPw-YCH8E=Td2_0wz=SQgapHQ@mail.gmail.com>
	<0FD5E8B4-07A7-47DB-8AC3-DAF79F4D3B1C@apple.com>
	<BANLkTinC7iWgcPRYpZxEDOb8R3XyYDnRsg@mail.gmail.com>
Message-ID: <13C1DDA4-137A-4551-BBE4-B7DB285A23FE@apple.com>



On Jun 24, 2011, at 6:23 PM, Francois Pichet <pichet2000 at gmail.com> wrote:

> On Fri, Jun 24, 2011 at 9:15 PM, Jim Grosbach <grosbach at apple.com> wrote:
>> The key thing seems to be:
>> 1>C:/dev/llvm/llvm_trunk2/bin/Release/llvm-mc.EXE : error : unable to
>> get target for 'thumbv7-apple-darwin10', see --version and --triple.
>> 
>> Is this builder building with all targets enabled? If not, that's an easy answer. I'd've expected other tests in that directory to fail, too, though, were that the case.
> 
> No only the x86 target is built. Nevertheless all the other tests pass.


Ok. They're probably explicitly disabled. I'll have a look. Thanks!
> 
>> 
>> What happens if you run the same command directly on a command line?
>> 
>> -Jim
>> 
>> On Jun 24, 2011, at 6:01 PM, Francois Pichet wrote:
>> 
>>> On Fri, Jun 24, 2011 at 4:59 PM, Jim Grosbach <grosbach at apple.com> wrote:
>>>> Author: grosbach
>>>> Date: Fri Jun 24 15:59:01 2011
>>>> New Revision: 133823
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=133823&view=rev

From pichet2000 at gmail.com  Fri Jun 24 20:58:36 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Fri, 24 Jun 2011 21:58:36 -0400
Subject: [llvm-commits] [llvm] r133063 - in /llvm/trunk:
 include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/ScheduleDAG.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
 test/CodeGen/X86/2011-06-14-PreschedRega
In-Reply-To: <10BEB288-2174-4180-BD44-DFB1C91C6560@apple.com>
References: <BANLkTikmt=JQ4_1EvFXSmfo-g5CErGpOwQ@mail.gmail.com>
	<10BEB288-2174-4180-BD44-DFB1C91C6560@apple.com>
Message-ID: <BANLkTino0yJbNCdjPr3HSAtocgEbjOK_RA@mail.gmail.com>

ok the error is:
1>  Command 0 Stderr:
1>  llc.EXE: Unknown command line argument '-stress-sched'.  Try:
'C:/dev/llvm/llvm_trunk2/bin/Release/llc.EXE -help'
1>  llc.EXE: Did you mean '-pre-RA-sched'?

I am always using latest svn.
Seems like the ENABLE_ASSERTIONS thing is not working on MSVC.


On Fri, Jun 24, 2011 at 9:36 PM, Andrew Trick <atrick at apple.com> wrote:
> Running the tests with the release build is fine. You should not see any failures. This particular test should be skipped as unsupported.
>
> If you're on r133725+, cmake should set the following line in lit "site config" (test/lit.site.cfg)
>
> config.enable_assertions = 0
>
> If you still have a problem, send me the details or file a bug. It should be easy to fix, the only issue here is that I don't have MSVC for testing.
>
> You can disregard my "self-review" comment below. I disabled the test shortly after checking it in until I believed the build system was handling it.
>
> -Andy
>
> On Jun 24, 2011, at 6:17 PM, Francois Pichet wrote:
>
>> This is sad, I recently took the habit of running the llvm tests at
>> least once a day on Windows (MSVC 2010) and this test is the only one
>> that constantly fails. I run them in in Release because a Debug run
>> takes forever and there is no Release+Assert on Windows.
>>
>> Just saying....
>>
>> On Wed, Jun 15, 2011 at 1:56 PM, Andrew Trick <atrick at apple.com> wrote:
>>> Self review: This test will fail in the no-Asserts build because -stress-sched is unavailable. It seems that llvm-lit always picks up the Asserts build. But is there some formal way to indicate that the test should not be run unless built with Asserts?
>>>
>>> -Andy
>>>
>>> On Jun 15, 2011, at 10:16 AM, Andrew Trick wrote:
>>>
>>>> Author: atrick
>>>> Date: Wed Jun 15 12:16:12 2011
>>>> New Revision: 133063
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=133063&view=rev
>>>> Log:
>>>> Added -stress-sched flag in the Asserts build.
>>>> Added a test case for handling physreg aliases during pre-RA-sched.
>>>>
>>>> Added:
>>>> ? ?llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
>>>> Modified:
>>>> ? ?llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
>>>> ? ?llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
>>>> ? ?llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>>> ? ?llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
>>>>
>
>


From grosbach at apple.com  Fri Jun 24 20:53:17 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Sat, 25 Jun 2011 01:53:17 -0000
Subject: [llvm-commits] [llvm] r133856 - in /llvm/trunk/test/MC:
 ARM/thumb2-movt-fixup.s MachO/thumb2-movt-fixup.s
Message-ID: <20110625015317.5E0DF2A6C12C@llvm.org>

Author: grosbach
Date: Fri Jun 24 20:53:17 2011
New Revision: 133856

URL: http://llvm.org/viewvc/llvm-project?rev=133856&view=rev
Log:
Move ARM-specific test to ARM directory.

Hopefully make the x86-target-only Windows bots happy.

Added:
    llvm/trunk/test/MC/ARM/thumb2-movt-fixup.s
      - copied unchanged from r133855, llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
Removed:
    llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s

Removed: llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s?rev=133855&view=auto
==============================================================================
--- llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s (original)
+++ llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s (removed)
@@ -1,17 +0,0 @@
-@ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7-apple-darwin10 -filetype=obj -o - < %s | macho-dump | FileCheck %s
-
-_fred:
-	movt	r3, :upper16:(_wilma-(LPC0_0+4))
-LPC0_0:
-
-_wilma:
-  .long 0
-
-@ CHECK:  ('_relocations', [
-@ CHECK:    # Relocation 0
-@ CHECK:    (('word-0', 0xb9000000),
-@ CHECK:     ('word-1', 0x4)),
-@ CHECK:    # Relocation 1
-@ CHECK:    (('word-0', 0xb100fffc),
-@ CHECK:     ('word-1', 0x4)),
-



From grosbach at apple.com  Fri Jun 24 20:59:42 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 24 Jun 2011 18:59:42 -0700
Subject: [llvm-commits] [llvm] r133823 -
 /llvm/trunk/test/MC/MachO/thumb2-movt-fixup.s
In-Reply-To: <BANLkTinC7iWgcPRYpZxEDOb8R3XyYDnRsg@mail.gmail.com>
References: <20110624205901.C88722A6C12C@llvm.org>
	<BANLkTinpazPw-YCH8E=Td2_0wz=SQgapHQ@mail.gmail.com>
	<0FD5E8B4-07A7-47DB-8AC3-DAF79F4D3B1C@apple.com>
	<BANLkTinC7iWgcPRYpZxEDOb8R3XyYDnRsg@mail.gmail.com>
Message-ID: <B571B8A5-E0C8-4141-95FA-588D4EE7C5B4@apple.com>

Fixed in r133856, I believe. Let me know if there's further problems. Thanks for your help.

-Jim

On Jun 24, 2011, at 6:23 PM, Francois Pichet wrote:

> On Fri, Jun 24, 2011 at 9:15 PM, Jim Grosbach <grosbach at apple.com> wrote:
>> The key thing seems to be:
>> 1>C:/dev/llvm/llvm_trunk2/bin/Release/llvm-mc.EXE : error : unable to
>> get target for 'thumbv7-apple-darwin10', see --version and --triple.
>> 
>> Is this builder building with all targets enabled? If not, that's an easy answer. I'd've expected other tests in that directory to fail, too, though, were that the case.
> 
> No only the x86 target is built. Nevertheless all the other tests pass.
> 
>> 
>> What happens if you run the same command directly on a command line?
>> 
>> -Jim
>> 
>> On Jun 24, 2011, at 6:01 PM, Francois Pichet wrote:
>> 
>>> On Fri, Jun 24, 2011 at 4:59 PM, Jim Grosbach <grosbach at apple.com> wrote:
>>>> Author: grosbach
>>>> Date: Fri Jun 24 15:59:01 2011
>>>> New Revision: 133823
>>>> 
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=133823&view=rev


From mcrosier at apple.com  Fri Jun 24 21:04:56 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Sat, 25 Jun 2011 02:04:56 -0000
Subject: [llvm-commits] [llvm] r133858 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20110625020456.B3EE22A6C12C@llvm.org>

Author: mcrosier
Date: Fri Jun 24 21:04:56 2011
New Revision: 133858

URL: http://llvm.org/viewvc/llvm-project?rev=133858&view=rev
Log:
Enable tail call optimization in the presence of a byval (x86-32 and x86-64).
<rdar://problem/9483883>

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=133858&r1=133857&r2=133858&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 24 21:04:56 2011
@@ -2505,6 +2505,10 @@
     if (!FINode)
       return false;
     FI = FINode->getIndex();
+  } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
+    FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Arg);
+    FI = FINode->getIndex();
+    Bytes = Flags.getByValSize();
   } else
     return false;
 



From ofv at wanadoo.es  Fri Jun 24 21:10:19 2011
From: ofv at wanadoo.es (Oscar Fuentes)
Date: Sat, 25 Jun 2011 02:10:19 -0000
Subject: [llvm-commits] [llvm] r133859 -
	/llvm/trunk/cmake/modules/LLVMLibDeps.cmake
Message-ID: <20110625021019.6A24C2A6C12C@llvm.org>

Author: ofv
Date: Fri Jun 24 21:10:19 2011
New Revision: 133859

URL: http://llvm.org/viewvc/llvm-project?rev=133859&view=rev
Log:
Update CMake library dependencies.

Modified:
    llvm/trunk/cmake/modules/LLVMLibDeps.cmake

Modified: llvm/trunk/cmake/modules/LLVMLibDeps.cmake
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/cmake/modules/LLVMLibDeps.cmake?rev=133859&r1=133858&r2=133859&view=diff
==============================================================================
--- llvm/trunk/cmake/modules/LLVMLibDeps.cmake (original)
+++ llvm/trunk/cmake/modules/LLVMLibDeps.cmake Fri Jun 24 21:10:19 2011
@@ -60,6 +60,7 @@
 set(MSVC_LIB_DEPS_LLVMX86AsmParser LLVMMC LLVMMCParser LLVMSupport LLVMTarget LLVMX86Info)
 set(MSVC_LIB_DEPS_LLVMX86AsmPrinter LLVMMC LLVMSupport LLVMX86Utils)
 set(MSVC_LIB_DEPS_LLVMX86CodeGen LLVMAnalysis LLVMAsmPrinter LLVMCodeGen LLVMCore LLVMMC LLVMSelectionDAG LLVMSupport LLVMTarget LLVMX86AsmPrinter LLVMX86Info LLVMX86Utils)
+set(MSVC_LIB_DEPS_LLVMX86Desc LLVMX86Info)
 set(MSVC_LIB_DEPS_LLVMX86Disassembler LLVMMC LLVMSupport LLVMX86Info)
 set(MSVC_LIB_DEPS_LLVMX86Info LLVMMC LLVMSupport)
 set(MSVC_LIB_DEPS_LLVMX86Utils LLVMCore LLVMSupport)



From mcrosier at apple.com  Fri Jun 24 21:44:56 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Sat, 25 Jun 2011 02:44:56 -0000
Subject: [llvm-commits] [llvm] r133863 -
	/llvm/trunk/test/CodeGen/X86/sibcall-byval.ll
Message-ID: <20110625024456.7B2FF2A6C12C@llvm.org>

Author: mcrosier
Date: Fri Jun 24 21:44:56 2011
New Revision: 133863

URL: http://llvm.org/viewvc/llvm-project?rev=133863&view=rev
Log:
Test case for r133858 (tail call optimize in the presence of byval).

Added:
    llvm/trunk/test/CodeGen/X86/sibcall-byval.ll

Added: llvm/trunk/test/CodeGen/X86/sibcall-byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/sibcall-byval.ll?rev=133863&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/sibcall-byval.ll (added)
+++ llvm/trunk/test/CodeGen/X86/sibcall-byval.ll Fri Jun 24 21:44:56 2011
@@ -0,0 +1,31 @@
+; RUN: llc < %s -mtriple=i386-apple-darwin   | FileCheck %s -check-prefix=32
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s -check-prefix=64
+
+%struct.p = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 }
+
+define i32 @f(%struct.p* byval align 4 %q) nounwind ssp {
+entry:
+; 32: _f:
+; 32: jmp L_g$stub
+
+; 64: _f:
+; 64: jmp _g
+  %call = tail call i32 @g(%struct.p* byval align 4 %q) nounwind
+  ret i32 %call
+}
+
+declare i32 @g(%struct.p* byval align 4)
+
+define i32 @h(%struct.p* byval align 4 %q, i32 %r) nounwind ssp {
+entry:
+; 32: _h:
+; 32: jmp L_i$stub
+
+; 64: _h:
+; 64: jmp _i
+
+  %call = tail call i32 @i(%struct.p* byval align 4 %q, i32 %r) nounwind
+  ret i32 %call
+}
+
+declare i32 @i(%struct.p* byval align 4, i32)



From sanjoy at playingwithpointers.com  Fri Jun 24 07:40:40 2011
From: sanjoy at playingwithpointers.com (Sanjoy Das)
Date: Fri, 24 Jun 2011 18:10:40 +0530
Subject: [llvm-commits] [LLVMdev] [PATCH] Get DCE to consider livein
 PhysRegs to successor basic blocks.
In-Reply-To: <058362BA-2F8A-4DFA-BA69-DFB5418AA685@2pi.dk>
References: <4E004D97.2040707@playingwithpointers.com>
	<82C2784C-2409-4EFB-A59F-BAB30A22D5E2@2pi.dk>
	<4E00EBFF.1050205@playingwithpointers.com>
	<058362BA-2F8A-4DFA-BA69-DFB5418AA685@2pi.dk>
Message-ID: <4E0485C8.8000300@playingwithpointers.com>

Hi!

> Three nits:

Fixed, new patch attached.

> But note that you really shouldn't be depending on this patch for your work. Live physregs prevent code motion and (now) dead code elimination. Virtual registers are always better.

I've re-written my code to leverage off the register allocator. Thanks! :)

-- 
Sanjoy Das
http://playingwithpointers.com

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From yan at matasano.com  Fri Jun 24 17:26:43 2011
From: yan at matasano.com (Yan Ivnitskiy)
Date: Fri, 24 Jun 2011 18:26:43 -0400
Subject: [llvm-commits] BitstreamReader patch
Message-ID: <EA9523C1-056F-442D-ABA1-C9E74A0EFAD8@matasano.com>

Hello,

Attached is a patch for the SkipBlock method for the BitstreamCursor class that sanity checks the length of words to skip. If the NumWords value is large enough, it is possible to overflow the amount of bytes to skip, and reset the bitstream cursor to any (4-byte aligned) address that is lower than the start of the mapped bitcode file.

Thanks,
Yan 

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From eli.friedman at gmail.com  Fri Jun 24 22:44:32 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Fri, 24 Jun 2011 20:44:32 -0700
Subject: [llvm-commits] [llvm] r133858 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
In-Reply-To: <20110625020456.B3EE22A6C12C@llvm.org>
References: <20110625020456.B3EE22A6C12C@llvm.org>
Message-ID: <BANLkTi=fAwYPxn+BDWDdPFPikPYTjuhqbK6VF8oF5TGOyXguMQ@mail.gmail.com>

On Fri, Jun 24, 2011 at 7:04 PM, Chad Rosier <mcrosier at apple.com> wrote:
> Author: mcrosier
> Date: Fri Jun 24 21:04:56 2011
> New Revision: 133858
>
> URL: http://llvm.org/viewvc/llvm-project?rev=133858&view=rev
> Log:
> Enable tail call optimization in the presence of a byval (x86-32 and x86-64).
> <rdar://problem/9483883>
>
> Modified:
> ? ?llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=133858&r1=133857&r2=133858&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 24 21:04:56 2011
> @@ -2505,6 +2505,10 @@
> ? ? if (!FINode)
> ? ? ? return false;
> ? ? FI = FINode->getIndex();
> + ?} else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
> + ? ?FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Arg);
> + ? ?FI = FINode->getIndex();
> + ? ?Bytes = Flags.getByValSize();
> ? } else
> ? ? return false;

An interesting side-note: byval+tail calls was already partially
working, but before this commit it only worked outside the entry
block. :)

-Eli


From mcrosier at apple.com  Fri Jun 24 23:15:22 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Fri, 24 Jun 2011 21:15:22 -0700
Subject: [llvm-commits] [llvm] r133858 -
 /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
In-Reply-To: <BANLkTi=fAwYPxn+BDWDdPFPikPYTjuhqbK6VF8oF5TGOyXguMQ@mail.gmail.com>
References: <20110625020456.B3EE22A6C12C@llvm.org>
	<BANLkTi=fAwYPxn+BDWDdPFPikPYTjuhqbK6VF8oF5TGOyXguMQ@mail.gmail.com>
Message-ID: <7FEE66C9-5DB6-4554-B464-98322868521E@apple.com>

On Jun 24, 2011, at 8:44 PM, Eli Friedman wrote:

> On Fri, Jun 24, 2011 at 7:04 PM, Chad Rosier <mcrosier at apple.com> wrote:
>> Author: mcrosier
>> Date: Fri Jun 24 21:04:56 2011
>> New Revision: 133858
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=133858&view=rev
>> Log:
>> Enable tail call optimization in the presence of a byval (x86-32 and x86-64).
>> <rdar://problem/9483883>
>> 
>> Modified:
>>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> 
>> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=133858&r1=133857&r2=133858&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Fri Jun 24 21:04:56 2011
>> @@ -2505,6 +2505,10 @@
>>     if (!FINode)
>>       return false;
>>     FI = FINode->getIndex();
>> +  } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
>> +    FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Arg);
>> +    FI = FINode->getIndex();
>> +    Bytes = Flags.getByValSize();
>>   } else
>>     return false;
> 
> An interesting side-note: byval+tail calls was already partially
> working, but before this commit it only worked outside the entry
> block. :)

Makes sense given the minimal amount of effort to get this going.

 Chad

> -Eli


From rafael.espindola at gmail.com  Sat Jun 25 00:10:36 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Sat, 25 Jun 2011 01:10:36 -0400
Subject: [llvm-commits] [patch] Enable simplifycfg in bb with only a
	lifetime intrinsic
Message-ID: <4E056DCC.3050107@gmail.com>

I noticed that simplify cfg would fail to simplify bbs like

bb:
  call void @llvm.lifetime.end(i64 -1, i8* %a) nounwind
  br label %bb1

The attached patch enables that. It can cause a llvm.lifetime.* to be lost,
but if I understand the manual correctly, that is fine: the argument now
has a larger life range.

Cheers,
Rafael
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From fvbommel at gmail.com  Sat Jun 25 04:23:40 2011
From: fvbommel at gmail.com (Frits van Bommel)
Date: Sat, 25 Jun 2011 11:23:40 +0200
Subject: [llvm-commits] [llvm] r133858 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
In-Reply-To: <20110625020456.B3EE22A6C12C@llvm.org>
References: <20110625020456.B3EE22A6C12C@llvm.org>
Message-ID: <BANLkTikJpH35Zx23NCfmWWPF=E8_yYo3+g@mail.gmail.com>

On 25 June 2011 04:04, Chad Rosier <mcrosier at apple.com> wrote:
> + ?} else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
> + ? ?FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Arg);
> + ? ?FI = FINode->getIndex();

That dyn_cast<> should probably be a cast<>, because
1) if it fails it's an error anyway, and
2) you're already checking that it can't fail beforehand.


From chenwj at iis.sinica.edu.tw  Sat Jun 25 05:54:41 2011
From: chenwj at iis.sinica.edu.tw (=?utf-8?B?6Zmz6Z+L5Lu7?=)
Date: Sat, 25 Jun 2011 18:54:41 +0800
Subject: [llvm-commits] [llvm] r133799 - in /llvm/trunk/lib/Target/PTX:
 PTX.td PTXAsmPrinter.cpp PTXISelLowering.cpp PTXInstrInfo.td
 PTXSubtarget.cpp PTXSubtarget.h
In-Reply-To: <20110624162749.D656E2A6C12C@llvm.org>
References: <20110624162749.D656E2A6C12C@llvm.org>
Message-ID: <20110625105441.GA74873@cs.nctu.edu.tw>

Hi, Justin

> +      bool fdivNeedsRoundingMode() const {
> +        return (PTXTarget >= PTX_SM_1_3 && PTXTarget < PTX_LAST_SM) ||
> +               (PTXTarget >= PTX_COMPUTE_1_3 && PTXTarget < PTX_LAST_COMPUTE);
> +      }
> +
> +      bool fmadNeedsRoundingMode() const {
> +        return (PTXTarget >= PTX_SM_1_3 && PTXTarget < PTX_LAST_SM) ||
> +               (PTXTarget >= PTX_COMPUTE_1_3 && PTXTarget < PTX_LAST_COMPUTE);
> +      }

  Do we need two seperate functions to decide fdiv/fmad rounding mode?

Regards,
chenwj

-- 
Wei-Ren Chen (???)
Computer Systems Lab, Institute of Information Science,
Academia Sinica, Taiwan (R.O.C.)
Tel:886-2-2788-3799 #1667


From atrick at apple.com  Sat Jun 25 11:23:13 2011
From: atrick at apple.com (Andrew Trick)
Date: Sat, 25 Jun 2011 09:23:13 -0700
Subject: [llvm-commits] [llvm] r133063 - in /llvm/trunk:
 include/llvm/CodeGen/ScheduleDAG.h lib/CodeGen/ScheduleDAG.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
 lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
 test/CodeGen/X86/2011-06-14-PreschedRega
In-Reply-To: <BANLkTino0yJbNCdjPr3HSAtocgEbjOK_RA@mail.gmail.com>
References: <BANLkTikmt=JQ4_1EvFXSmfo-g5CErGpOwQ@mail.gmail.com>
	<10BEB288-2174-4180-BD44-DFB1C91C6560@apple.com>
	<BANLkTino0yJbNCdjPr3HSAtocgEbjOK_RA@mail.gmail.com>
Message-ID: <81872ACD-C5E1-4BD6-AEB8-83367C2D3276@apple.com>

Can you see a project option titled LLVM_ENABLE_ASSERTIONS? Turning that OFF should disable the test as I explained. If that is ON then please verify that the compile line contains -UNDEBUG after any occurence of -DNDEBUG? If not, then that is a LLVM cmake bug that we can easily fix. I just need someone to verify it.

-Andy

On Jun 24, 2011, at 6:58 PM, Francois Pichet wrote:

> ok the error is:
> 1>  Command 0 Stderr:
> 1>  llc.EXE: Unknown command line argument '-stress-sched'.  Try:
> 'C:/dev/llvm/llvm_trunk2/bin/Release/llc.EXE -help'
> 1>  llc.EXE: Did you mean '-pre-RA-sched'?
> 
> I am always using latest svn.
> Seems like the ENABLE_ASSERTIONS thing is not working on MSVC.
> 
> 
> On Fri, Jun 24, 2011 at 9:36 PM, Andrew Trick <atrick at apple.com> wrote:
>> Running the tests with the release build is fine. You should not see any failures. This particular test should be skipped as unsupported.
>> 
>> If you're on r133725+, cmake should set the following line in lit "site config" (test/lit.site.cfg)
>> 
>> config.enable_assertions = 0
>> 
>> If you still have a problem, send me the details or file a bug. It should be easy to fix, the only issue here is that I don't have MSVC for testing.
>> 
>> You can disregard my "self-review" comment below. I disabled the test shortly after checking it in until I believed the build system was handling it.
>> 
>> -Andy
>> 
>> On Jun 24, 2011, at 6:17 PM, Francois Pichet wrote:
>> 
>>> This is sad, I recently took the habit of running the llvm tests at
>>> least once a day on Windows (MSVC 2010) and this test is the only one
>>> that constantly fails. I run them in in Release because a Debug run
>>> takes forever and there is no Release+Assert on Windows.
>>> 
>>> Just saying....
>>> 
>>> On Wed, Jun 15, 2011 at 1:56 PM, Andrew Trick <atrick at apple.com> wrote:
>>>> Self review: This test will fail in the no-Asserts build because -stress-sched is unavailable. It seems that llvm-lit always picks up the Asserts build. But is there some formal way to indicate that the test should not be run unless built with Asserts?
>>>> 
>>>> -Andy
>>>> 
>>>> On Jun 15, 2011, at 10:16 AM, Andrew Trick wrote:
>>>> 
>>>>> Author: atrick
>>>>> Date: Wed Jun 15 12:16:12 2011
>>>>> New Revision: 133063
>>>>> 
>>>>> URL: http://llvm.org/viewvc/llvm-project?rev=133063&view=rev
>>>>> Log:
>>>>> Added -stress-sched flag in the Asserts build.
>>>>> Added a test case for handling physreg aliases during pre-RA-sched.
>>>>> 
>>>>> Added:
>>>>>   llvm/trunk/test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
>>>>> Modified:
>>>>>   llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h
>>>>>   llvm/trunk/lib/CodeGen/ScheduleDAG.cpp
>>>>>   llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
>>>>>   llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
>>>>> 
>> 
>> 


From nicholas at mxc.ca  Sat Jun 25 12:08:50 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Sat, 25 Jun 2011 17:08:50 -0000
Subject: [llvm-commits] [llvm] r133867 -
	/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
Message-ID: <20110625170851.08C232A6C12C@llvm.org>

Author: nicholas
Date: Sat Jun 25 12:08:50 2011
New Revision: 133867

URL: http://llvm.org/viewvc/llvm-project?rev=133867&view=rev
Log:
Enhance the sanity check for block sizes; check that the resulting pointer is
pointing to the range [first character, last character] instead of just not
after the last character. Patch by Yan Ivnitskiy!

Modified:
    llvm/trunk/include/llvm/Bitcode/BitstreamReader.h

Modified: llvm/trunk/include/llvm/Bitcode/BitstreamReader.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Bitcode/BitstreamReader.h?rev=133867&r1=133866&r2=133867&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Bitcode/BitstreamReader.h (original)
+++ llvm/trunk/include/llvm/Bitcode/BitstreamReader.h Sat Jun 25 12:08:50 2011
@@ -375,10 +375,12 @@
 
     // Check that the block wasn't partially defined, and that the offset isn't
     // bogus.
-    if (AtEndOfStream() || NextChar+NumWords*4 > BitStream->getLastChar())
+    const unsigned char *const SkipTo = NextChar + NumWords*4;
+    if (AtEndOfStream() || SkipTo > BitStream->getLastChar() ||
+                           SkipTo < BitStream->getFirstChar())
       return true;
 
-    NextChar += NumWords*4;
+    NextChar = SkipTo;
     return false;
   }
 



From nicholas at mxc.ca  Sat Jun 25 12:16:48 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Sat, 25 Jun 2011 10:16:48 -0700
Subject: [llvm-commits] BitstreamReader patch
In-Reply-To: <EA9523C1-056F-442D-ABA1-C9E74A0EFAD8@matasano.com>
References: <EA9523C1-056F-442D-ABA1-C9E74A0EFAD8@matasano.com>
Message-ID: <4E061800.1020703@mxc.ca>

Yan Ivnitskiy wrote:
> Hello,
>
> Attached is a patch for the SkipBlock method for the BitstreamCursor class that sanity checks the length of words to skip. If the NumWords value is large enough, it is possible to overflow the amount of bytes to skip, and reset the bitstream cursor to any (4-byte aligned) address that is lower than the start of the mapped bitcode file.

Thanks! Patch applied in r133867.

Nick

From bigcheesegs at gmail.com  Sat Jun 25 12:42:56 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Sat, 25 Jun 2011 17:42:56 -0000
Subject: [llvm-commits] [llvm] r133868 - in /llvm/trunk:
 include/llvm/Object/Error.h lib/Object/CMakeLists.txt lib/Object/Error.cpp
Message-ID: <20110625174256.5EDA82A6C12C@llvm.org>

Author: mspencer
Date: Sat Jun 25 12:42:56 2011
New Revision: 133868

URL: http://llvm.org/viewvc/llvm-project?rev=133868&view=rev
Log:
Add Object/Error.

Added:
    llvm/trunk/include/llvm/Object/Error.h
    llvm/trunk/lib/Object/Error.cpp
Modified:
    llvm/trunk/lib/Object/CMakeLists.txt

Added: llvm/trunk/include/llvm/Object/Error.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/Error.h?rev=133868&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Object/Error.h (added)
+++ llvm/trunk/include/llvm/Object/Error.h Sat Jun 25 12:42:56 2011
@@ -0,0 +1,49 @@
+//===- Error.h - system_error extensions for Object -------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This declares a new error_category for the Object library.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_OBJECT_ERROR_H
+#define LLVM_OBJECT_ERROR_H
+
+#include "llvm/Support/system_error.h"
+
+namespace llvm {
+namespace object {
+
+const error_category &object_category();
+
+struct object_error {
+enum _ {
+  success = 0,
+  invalid_file_type,
+  parse_failed
+};
+  _ v_;
+
+  object_error(_ v) : v_(v) {}
+  explicit object_error(int v) : v_(_(v)) {}
+  operator int() const {return v_;}
+};
+
+inline error_code make_error_code(object_error e) {
+  return error_code(static_cast<int>(e), object_category());
+}
+
+} // end namespace object.
+
+template <> struct is_error_code_enum<object::object_error> : true_type { };
+
+template <> struct is_error_code_enum<object::object_error::_> : true_type { };
+
+} // end namespace llvm.
+
+#endif

Modified: llvm/trunk/lib/Object/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/CMakeLists.txt?rev=133868&r1=133867&r2=133868&view=diff
==============================================================================
--- llvm/trunk/lib/Object/CMakeLists.txt (original)
+++ llvm/trunk/lib/Object/CMakeLists.txt Sat Jun 25 12:42:56 2011
@@ -1,6 +1,7 @@
 add_llvm_library(LLVMObject
   COFFObjectFile.cpp
   ELFObjectFile.cpp
+  Error.cpp
   MachOObject.cpp
   MachOObjectFile.cpp
   Object.cpp

Added: llvm/trunk/lib/Object/Error.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/Error.cpp?rev=133868&view=auto
==============================================================================
--- llvm/trunk/lib/Object/Error.cpp (added)
+++ llvm/trunk/lib/Object/Error.cpp Sat Jun 25 12:42:56 2011
@@ -0,0 +1,55 @@
+//===- Error.cpp - system_error extensions for Object -----------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This defines a new error_category for the Object library.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Object/Error.h"
+#include "llvm/Support/ErrorHandling.h"
+
+using namespace llvm;
+using namespace object;
+
+namespace {
+class _object_error_category : public _do_message {
+public:
+  virtual const char* name() const;
+  virtual std::string message(int ev) const;
+  virtual error_condition default_error_condition(int ev) const;
+};
+}
+
+const char *_object_error_category::name() const {
+  return "llvm.object";
+}
+
+std::string _object_error_category::message(int ev) const {
+  switch (ev) {
+  case object_error::success: return "Success";
+  case object_error::invalid_file_type:
+    return "The file was not recognized as a valid object file";
+  case object_error::parse_failed:
+    return "Invalid data was encountered while parsing the file";
+  default:
+    llvm_unreachable("An enumerator of object_error does not have a message "
+                     "defined.");
+  }
+}
+
+error_condition _object_error_category::default_error_condition(int ev) const {
+  if (ev == object_error::success)
+    return errc::success;
+  return errc::invalid_argument;
+}
+
+const error_category &object::object_category() {
+  static _object_error_category o;
+  return o;
+}



From bigcheesegs at gmail.com  Sat Jun 25 12:54:29 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Sat, 25 Jun 2011 17:54:29 -0000
Subject: [llvm-commits] [llvm] r133869 - in /llvm/trunk:
 include/llvm/Object/Binary.h lib/Object/Binary.cpp
 lib/Object/CMakeLists.txt
Message-ID: <20110625175429.96D7D2A6C12C@llvm.org>

Author: mspencer
Date: Sat Jun 25 12:54:29 2011
New Revision: 133869

URL: http://llvm.org/viewvc/llvm-project?rev=133869&view=rev
Log:
Add Binary class. This is a cleaner parent than ObjectFile.

Added:
    llvm/trunk/include/llvm/Object/Binary.h
    llvm/trunk/lib/Object/Binary.cpp
Modified:
    llvm/trunk/lib/Object/CMakeLists.txt

Added: llvm/trunk/include/llvm/Object/Binary.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/Binary.h?rev=133869&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Object/Binary.h (added)
+++ llvm/trunk/include/llvm/Object/Binary.h Sat Jun 25 12:54:29 2011
@@ -0,0 +1,64 @@
+//===- Binary.h - A generic binary file -------------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the Binary class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_OBJECT_BINARY_H
+#define LLVM_OBJECT_BINARY_H
+
+#include "llvm/ADT/OwningPtr.h"
+#include "llvm/Object/Error.h"
+
+namespace llvm {
+
+class MemoryBuffer;
+class StringRef;
+
+namespace object {
+
+class Binary {
+private:
+  Binary(); // = delete
+  Binary(const Binary &other); // = delete
+
+  unsigned int TypeID;
+
+protected:
+  MemoryBuffer *Data;
+
+  Binary(unsigned int Type, MemoryBuffer *Source);
+
+  enum {
+    isArchive,
+    isCOFF,
+    isELF,
+    isMachO,
+    isObject
+  };
+
+public:
+  virtual ~Binary();
+
+  StringRef getData() const;
+  StringRef getFileName() const;
+
+  // Cast methods.
+  unsigned int getType() const { return TypeID; }
+  static inline bool classof(Binary const *v) { return true; }
+};
+
+error_code createBinary(MemoryBuffer *Source, OwningPtr<Binary> &Result);
+error_code createBinary(StringRef Path, OwningPtr<Binary> &Result);
+
+}
+}
+
+#endif

Added: llvm/trunk/lib/Object/Binary.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/Binary.cpp?rev=133869&view=auto
==============================================================================
--- llvm/trunk/lib/Object/Binary.cpp (added)
+++ llvm/trunk/lib/Object/Binary.cpp Sat Jun 25 12:54:29 2011
@@ -0,0 +1,50 @@
+//===- Binary.cpp - A generic binary file -----------------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines the Binary class.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Object/Binary.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Support/MemoryBuffer.h"
+#include "llvm/Support/Path.h"
+
+using namespace llvm;
+using namespace object;
+
+Binary::~Binary() {
+  delete Data;
+}
+
+Binary::Binary(unsigned int Type, MemoryBuffer *Source)
+  : TypeID(Type)
+  , Data(Source) {}
+
+StringRef Binary::getData() const {
+  return Data->getBuffer();
+}
+
+StringRef Binary::getFileName() const {
+  return Data->getBufferIdentifier();
+}
+
+error_code object::createBinary(MemoryBuffer *Source,
+                                OwningPtr<Binary> &Result) {
+  // We don't support any at the moment.
+  delete Source;
+  return object_error::invalid_file_type;
+}
+
+error_code object::createBinary(StringRef Path, OwningPtr<Binary> &Result) {
+  OwningPtr<MemoryBuffer> File;
+  if (error_code ec = MemoryBuffer::getFile(Path, File))
+    return ec;
+  return createBinary(File.take(), Result);
+}

Modified: llvm/trunk/lib/Object/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/CMakeLists.txt?rev=133869&r1=133868&r2=133869&view=diff
==============================================================================
--- llvm/trunk/lib/Object/CMakeLists.txt (original)
+++ llvm/trunk/lib/Object/CMakeLists.txt Sat Jun 25 12:54:29 2011
@@ -1,4 +1,5 @@
 add_llvm_library(LLVMObject
+  Binary.cpp
   COFFObjectFile.cpp
   ELFObjectFile.cpp
   Error.cpp



From bigcheesegs at gmail.com  Sat Jun 25 12:54:51 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Sat, 25 Jun 2011 17:54:51 -0000
Subject: [llvm-commits] [llvm] r133870 - in /llvm/trunk:
 include/llvm/Object/Binary.h include/llvm/Object/COFF.h
 include/llvm/Object/ObjectFile.h lib/Object/Binary.cpp
 lib/Object/COFFObjectFile.cpp lib/Object/ELFObjectFile.cpp
 lib/Object/MachOObjectFile.cpp lib/Object/ObjectFile.cpp
 tools/llvm-nm/llvm-nm.cpp
Message-ID: <20110625175451.3B99A2A6C12C@llvm.org>

Author: mspencer
Date: Sat Jun 25 12:54:50 2011
New Revision: 133870

URL: http://llvm.org/viewvc/llvm-project?rev=133870&view=rev
Log:
Make Binary the parent of ObjectFile and update children to new interface.

Added:
    llvm/trunk/include/llvm/Object/COFF.h
Modified:
    llvm/trunk/include/llvm/Object/Binary.h
    llvm/trunk/include/llvm/Object/ObjectFile.h
    llvm/trunk/lib/Object/Binary.cpp
    llvm/trunk/lib/Object/COFFObjectFile.cpp
    llvm/trunk/lib/Object/ELFObjectFile.cpp
    llvm/trunk/lib/Object/MachOObjectFile.cpp
    llvm/trunk/lib/Object/ObjectFile.cpp
    llvm/trunk/tools/llvm-nm/llvm-nm.cpp

Modified: llvm/trunk/include/llvm/Object/Binary.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/Binary.h?rev=133870&r1=133869&r2=133870&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/Binary.h (original)
+++ llvm/trunk/include/llvm/Object/Binary.h Sat Jun 25 12:54:50 2011
@@ -38,10 +38,13 @@
 
   enum {
     isArchive,
+
+    // Object and children.
+    isObject,
     isCOFF,
     isELF,
     isMachO,
-    isObject
+    lastObject
   };
 
 public:
@@ -52,7 +55,7 @@
 
   // Cast methods.
   unsigned int getType() const { return TypeID; }
-  static inline bool classof(Binary const *v) { return true; }
+  static inline bool classof(const Binary *v) { return true; }
 };
 
 error_code createBinary(MemoryBuffer *Source, OwningPtr<Binary> &Result);

Added: llvm/trunk/include/llvm/Object/COFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=133870&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Object/COFF.h (added)
+++ llvm/trunk/include/llvm/Object/COFF.h Sat Jun 25 12:54:50 2011
@@ -0,0 +1,111 @@
+//===- COFF.h - COFF object file implementation -----------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file declares the COFFObjectFile class.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_OBJECT_COFF_H
+#define LLVM_OBJECT_COFF_H
+
+#include "llvm/Object/ObjectFile.h"
+#include "llvm/Support/COFF.h"
+#include "llvm/Support/Endian.h"
+
+namespace llvm {
+namespace object {
+
+struct coff_file_header {
+  support::ulittle16_t Machine;
+  support::ulittle16_t NumberOfSections;
+  support::ulittle32_t TimeDateStamp;
+  support::ulittle32_t PointerToSymbolTable;
+  support::ulittle32_t NumberOfSymbols;
+  support::ulittle16_t SizeOfOptionalHeader;
+  support::ulittle16_t Characteristics;
+};
+
+struct coff_symbol {
+  struct StringTableOffset {
+    support::ulittle32_t Zeroes;
+    support::ulittle32_t Offset;
+  };
+
+  union {
+    char ShortName[8];
+    StringTableOffset Offset;
+  } Name;
+
+  support::ulittle32_t Value;
+  support::little16_t SectionNumber;
+
+  struct {
+    support::ulittle8_t BaseType;
+    support::ulittle8_t ComplexType;
+  } Type;
+
+  support::ulittle8_t  StorageClass;
+  support::ulittle8_t  NumberOfAuxSymbols;
+};
+
+struct coff_section {
+  char Name[8];
+  support::ulittle32_t VirtualSize;
+  support::ulittle32_t VirtualAddress;
+  support::ulittle32_t SizeOfRawData;
+  support::ulittle32_t PointerToRawData;
+  support::ulittle32_t PointerToRelocations;
+  support::ulittle32_t PointerToLinenumbers;
+  support::ulittle16_t NumberOfRelocations;
+  support::ulittle16_t NumberOfLinenumbers;
+  support::ulittle32_t Characteristics;
+};
+
+class COFFObjectFile : public ObjectFile {
+private:
+        uint64_t         HeaderOff;
+  const coff_file_header *Header;
+  const coff_section     *SectionTable;
+  const coff_symbol      *SymbolTable;
+  const char             *StringTable;
+
+  const coff_section     *getSection(std::size_t index) const;
+  const char             *getString(std::size_t offset) const;
+
+protected:
+  virtual SymbolRef getSymbolNext(DataRefImpl Symb) const;
+  virtual StringRef getSymbolName(DataRefImpl Symb) const;
+  virtual uint64_t  getSymbolAddress(DataRefImpl Symb) const;
+  virtual uint64_t  getSymbolSize(DataRefImpl Symb) const;
+  virtual char      getSymbolNMTypeChar(DataRefImpl Symb) const;
+  virtual bool      isSymbolInternal(DataRefImpl Symb) const;
+
+  virtual SectionRef getSectionNext(DataRefImpl Sec) const;
+  virtual StringRef  getSectionName(DataRefImpl Sec) const;
+  virtual uint64_t   getSectionAddress(DataRefImpl Sec) const;
+  virtual uint64_t   getSectionSize(DataRefImpl Sec) const;
+  virtual StringRef  getSectionContents(DataRefImpl Sec) const;
+  virtual bool       isSectionText(DataRefImpl Sec) const;
+
+public:
+  COFFObjectFile(MemoryBuffer *Object, error_code &ec);
+  virtual symbol_iterator begin_symbols() const;
+  virtual symbol_iterator end_symbols() const;
+  virtual section_iterator begin_sections() const;
+  virtual section_iterator end_sections() const;
+
+  virtual uint8_t getBytesInAddress() const;
+  virtual StringRef getFileFormatName() const;
+  virtual unsigned getArch() const;
+};
+
+}
+}
+
+#endif

Modified: llvm/trunk/include/llvm/Object/ObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=133870&r1=133869&r2=133870&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/ObjectFile.h (original)
+++ llvm/trunk/include/llvm/Object/ObjectFile.h Sat Jun 25 12:54:50 2011
@@ -14,15 +14,13 @@
 #ifndef LLVM_OBJECT_OBJECT_FILE_H
 #define LLVM_OBJECT_OBJECT_FILE_H
 
+#include "llvm/Object/Binary.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/DataTypes.h"
+#include "llvm/Support/MemoryBuffer.h"
 #include <cstring>
 
 namespace llvm {
-
-class MemoryBuffer;
-class StringRef;
-
 namespace object {
 
 class ObjectFile;
@@ -93,16 +91,17 @@
 /// ObjectFile - This class is the base class for all object file types.
 /// Concrete instances of this object are created by createObjectFile, which
 /// figure out which type to create.
-class ObjectFile {
+class ObjectFile : public Binary {
 private:
   ObjectFile(); // = delete
   ObjectFile(const ObjectFile &other); // = delete
 
 protected:
-  MemoryBuffer *MapFile;
-  const uint8_t *base;
+  ObjectFile(unsigned int Type, MemoryBuffer *source, error_code &ec);
 
-  ObjectFile(MemoryBuffer *Object);
+  const uint8_t *base() const {
+    return reinterpret_cast<const uint8_t *>(Data->getBufferStart());
+  }
 
   // These functions are for SymbolRef to call internally. The main goal of
   // this is to allow SymbolRef::SymbolPimpl to point directly to the symbol
@@ -156,8 +155,6 @@
   typedef content_iterator<SymbolRef> symbol_iterator;
   typedef content_iterator<SectionRef> section_iterator;
 
-  virtual ~ObjectFile();
-
   virtual symbol_iterator begin_symbols() const = 0;
   virtual symbol_iterator end_symbols() const = 0;
 
@@ -171,8 +168,6 @@
   virtual StringRef getFileFormatName() const = 0;
   virtual /* Triple::ArchType */ unsigned getArch() const = 0;
 
-  StringRef getFilename() const;
-
   /// @returns Pointer to ObjectFile subclass to handle this type of object.
   /// @param ObjectPath The path to the object file. ObjectPath.isObject must
   ///        return true.
@@ -180,12 +175,16 @@
   static ObjectFile *createObjectFile(StringRef ObjectPath);
   static ObjectFile *createObjectFile(MemoryBuffer *Object);
 
-private:
+  static inline bool classof(const Binary *v) {
+    return v->getType() >= isObject &&
+           v->getType() < lastObject;
+  }
+  static inline bool classof(const ObjectFile *v) { return true; }
+
+public:
   static ObjectFile *createCOFFObjectFile(MemoryBuffer *Object);
   static ObjectFile *createELFObjectFile(MemoryBuffer *Object);
   static ObjectFile *createMachOObjectFile(MemoryBuffer *Object);
-  static ObjectFile *createArchiveObjectFile(MemoryBuffer *Object);
-  static ObjectFile *createLibObjectFile(MemoryBuffer *Object);
 };
 
 // Inline function definitions.

Modified: llvm/trunk/lib/Object/Binary.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/Binary.cpp?rev=133870&r1=133869&r2=133870&view=diff
==============================================================================
--- llvm/trunk/lib/Object/Binary.cpp (original)
+++ llvm/trunk/lib/Object/Binary.cpp Sat Jun 25 12:54:50 2011
@@ -16,6 +16,10 @@
 #include "llvm/Support/MemoryBuffer.h"
 #include "llvm/Support/Path.h"
 
+// Include headers for createBinary.
+#include "llvm/Object/ObjectFile.h"
+#include "llvm/Object/COFF.h"
+
 using namespace llvm;
 using namespace object;
 
@@ -37,9 +41,51 @@
 
 error_code object::createBinary(MemoryBuffer *Source,
                                 OwningPtr<Binary> &Result) {
-  // We don't support any at the moment.
-  delete Source;
-  return object_error::invalid_file_type;
+  OwningPtr<MemoryBuffer> scopedSource(Source);
+  if (!Source)
+    return make_error_code(errc::invalid_argument);
+  if (Source->getBufferSize() < 64)
+    return object_error::invalid_file_type;
+  sys::LLVMFileType type = sys::IdentifyFileType(Source->getBufferStart(),
+                                static_cast<unsigned>(Source->getBufferSize()));
+  error_code ec;
+  switch (type) {
+    case sys::ELF_Relocatable_FileType:
+    case sys::ELF_Executable_FileType:
+    case sys::ELF_SharedObject_FileType:
+    case sys::ELF_Core_FileType: {
+      OwningPtr<Binary> ret(
+        ObjectFile::createELFObjectFile(scopedSource.take()));
+      if (!ret)
+        return object_error::invalid_file_type;
+      Result.swap(ret);
+      return object_error::success;
+    }
+    case sys::Mach_O_Object_FileType:
+    case sys::Mach_O_Executable_FileType:
+    case sys::Mach_O_FixedVirtualMemorySharedLib_FileType:
+    case sys::Mach_O_Core_FileType:
+    case sys::Mach_O_PreloadExecutable_FileType:
+    case sys::Mach_O_DynamicallyLinkedSharedLib_FileType:
+    case sys::Mach_O_DynamicLinker_FileType:
+    case sys::Mach_O_Bundle_FileType:
+    case sys::Mach_O_DynamicallyLinkedSharedLibStub_FileType: {
+      OwningPtr<Binary> ret(
+        ObjectFile::createMachOObjectFile(scopedSource.take()));
+      if (!ret)
+        return object_error::invalid_file_type;
+      Result.swap(ret);
+      return object_error::success;
+    }
+    case sys::COFF_FileType: {
+      OwningPtr<Binary> ret(new COFFObjectFile(scopedSource.take(), ec));
+      if (ec) return ec;
+      Result.swap(ret);
+      return object_error::success;
+    }
+    default: // Unrecognized object file format.
+      return object_error::invalid_file_type;
+  }
 }
 
 error_code object::createBinary(StringRef Path, OwningPtr<Binary> &Result) {

Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=133870&r1=133869&r2=133870&view=diff
==============================================================================
--- llvm/trunk/lib/Object/COFFObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/COFFObjectFile.cpp Sat Jun 25 12:54:50 2011
@@ -11,11 +11,9 @@
 //
 //===----------------------------------------------------------------------===//
 
+#include "llvm/Object/COFF.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
-#include "llvm/Object/ObjectFile.h"
-#include "llvm/Support/COFF.h"
-#include "llvm/Support/Endian.h"
 
 using namespace llvm;
 using namespace object;
@@ -27,107 +25,6 @@
 using support::little16_t;
 }
 
-namespace {
-struct coff_file_header {
-  ulittle16_t Machine;
-  ulittle16_t NumberOfSections;
-  ulittle32_t TimeDateStamp;
-  ulittle32_t PointerToSymbolTable;
-  ulittle32_t NumberOfSymbols;
-  ulittle16_t SizeOfOptionalHeader;
-  ulittle16_t Characteristics;
-};
-}
-
-extern char coff_file_header_layout_static_assert
-            [sizeof(coff_file_header) == 20 ? 1 : -1];
-
-namespace {
-struct coff_symbol {
-  struct StringTableOffset {
-    ulittle32_t Zeroes;
-    ulittle32_t Offset;
-  };
-
-  union {
-    char ShortName[8];
-    StringTableOffset Offset;
-  } Name;
-
-  ulittle32_t Value;
-  little16_t SectionNumber;
-
-  struct {
-    ulittle8_t BaseType;
-    ulittle8_t ComplexType;
-  } Type;
-
-  ulittle8_t  StorageClass;
-  ulittle8_t  NumberOfAuxSymbols;
-};
-}
-
-extern char coff_coff_symbol_layout_static_assert
-            [sizeof(coff_symbol) == 18 ? 1 : -1];
-
-namespace {
-struct coff_section {
-  char Name[8];
-  ulittle32_t VirtualSize;
-  ulittle32_t VirtualAddress;
-  ulittle32_t SizeOfRawData;
-  ulittle32_t PointerToRawData;
-  ulittle32_t PointerToRelocations;
-  ulittle32_t PointerToLinenumbers;
-  ulittle16_t NumberOfRelocations;
-  ulittle16_t NumberOfLinenumbers;
-  ulittle32_t Characteristics;
-};
-}
-
-extern char coff_coff_section_layout_static_assert
-            [sizeof(coff_section) == 40 ? 1 : -1];
-
-namespace {
-class COFFObjectFile : public ObjectFile {
-private:
-        uint64_t         HeaderOff;
-  const coff_file_header *Header;
-  const coff_section     *SectionTable;
-  const coff_symbol      *SymbolTable;
-  const char             *StringTable;
-
-  const coff_section     *getSection(std::size_t index) const;
-  const char             *getString(std::size_t offset) const;
-
-protected:
-  virtual SymbolRef getSymbolNext(DataRefImpl Symb) const;
-  virtual StringRef getSymbolName(DataRefImpl Symb) const;
-  virtual uint64_t  getSymbolAddress(DataRefImpl Symb) const;
-  virtual uint64_t  getSymbolSize(DataRefImpl Symb) const;
-  virtual char      getSymbolNMTypeChar(DataRefImpl Symb) const;
-  virtual bool      isSymbolInternal(DataRefImpl Symb) const;
-
-  virtual SectionRef getSectionNext(DataRefImpl Sec) const;
-  virtual StringRef  getSectionName(DataRefImpl Sec) const;
-  virtual uint64_t   getSectionAddress(DataRefImpl Sec) const;
-  virtual uint64_t   getSectionSize(DataRefImpl Sec) const;
-  virtual StringRef  getSectionContents(DataRefImpl Sec) const;
-  virtual bool       isSectionText(DataRefImpl Sec) const;
-
-public:
-  COFFObjectFile(MemoryBuffer *Object);
-  virtual symbol_iterator begin_symbols() const;
-  virtual symbol_iterator end_symbols() const;
-  virtual section_iterator begin_sections() const;
-  virtual section_iterator end_sections() const;
-
-  virtual uint8_t getBytesInAddress() const;
-  virtual StringRef getFileFormatName() const;
-  virtual unsigned getArch() const;
-};
-} // end namespace
-
 SymbolRef COFFObjectFile::getSymbolNext(DataRefImpl Symb) const {
   const coff_symbol *symb = reinterpret_cast<const coff_symbol*>(Symb.p);
   symb += 1 + symb->NumberOfAuxSymbols;
@@ -274,7 +171,8 @@
 
 StringRef COFFObjectFile::getSectionContents(DataRefImpl Sec) const {
   const coff_section *sec = reinterpret_cast<const coff_section*>(Sec.p);
-  return StringRef(reinterpret_cast<const char *>(base + sec->PointerToRawData),
+  return StringRef(reinterpret_cast<const char *>(base()
+                   + sec->PointerToRawData),
                    sec->SizeOfRawData);
 }
 
@@ -283,29 +181,30 @@
   return sec->Characteristics & COFF::IMAGE_SCN_CNT_CODE;
 }
 
-COFFObjectFile::COFFObjectFile(MemoryBuffer *Object)
-  : ObjectFile(Object) {
+COFFObjectFile::COFFObjectFile(MemoryBuffer *Object, error_code &ec)
+  : ObjectFile(Binary::isCOFF, Object, ec) {
 
   HeaderOff = 0;
 
-  if (base[0] == 0x4d && base[1] == 0x5a) {
+  if (base()[0] == 0x4d && base()[1] == 0x5a) {
     // PE/COFF, seek through MS-DOS compatibility stub and 4-byte
     // PE signature to find 'normal' COFF header.
-    HeaderOff += *reinterpret_cast<const ulittle32_t *>(base + 0x3c);
+    HeaderOff += *reinterpret_cast<const ulittle32_t *>(base() + 0x3c);
     HeaderOff += 4;
   }
 
-  Header = reinterpret_cast<const coff_file_header *>(base + HeaderOff);
+  Header = reinterpret_cast<const coff_file_header *>(base() + HeaderOff);
   SectionTable =
-    reinterpret_cast<const coff_section *>( base
+    reinterpret_cast<const coff_section *>( base()
                                           + HeaderOff
                                           + sizeof(coff_file_header)
                                           + Header->SizeOfOptionalHeader);
   SymbolTable =
-    reinterpret_cast<const coff_symbol *>(base + Header->PointerToSymbolTable);
+    reinterpret_cast<const coff_symbol *>(base()
+    + Header->PointerToSymbolTable);
 
   // Find string table.
-  StringTable = reinterpret_cast<const char *>(base)
+  StringTable = reinterpret_cast<const char *>(base())
               + Header->PointerToSymbolTable
               + Header->NumberOfSymbols * 18;
 }
@@ -382,7 +281,8 @@
 namespace llvm {
 
   ObjectFile *ObjectFile::createCOFFObjectFile(MemoryBuffer *Object) {
-    return new COFFObjectFile(Object);
+    error_code ec;
+    return new COFFObjectFile(Object, ec);
   }
 
 } // end namespace llvm

Modified: llvm/trunk/lib/Object/ELFObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ELFObjectFile.cpp?rev=133870&r1=133869&r2=133870&view=diff
==============================================================================
--- llvm/trunk/lib/Object/ELFObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/ELFObjectFile.cpp Sat Jun 25 12:54:50 2011
@@ -237,7 +237,7 @@
   virtual bool       isSectionText(DataRefImpl Sec) const;
 
 public:
-  ELFObjectFile(MemoryBuffer *Object);
+  ELFObjectFile(MemoryBuffer *Object, error_code &ec);
   virtual symbol_iterator begin_symbols() const;
   virtual symbol_iterator end_symbols() const;
   virtual section_iterator begin_sections() const;
@@ -259,9 +259,9 @@
   //        an error object around.
   if (!(  symb
         && SymbolTableSection
-        && symb >= (const Elf_Sym*)(base
+        && symb >= (const Elf_Sym*)(base()
                    + SymbolTableSection->sh_offset)
-        && symb <  (const Elf_Sym*)(base
+        && symb <  (const Elf_Sym*)(base()
                    + SymbolTableSection->sh_offset
                    + SymbolTableSection->sh_size)))
     // FIXME: Proper error handling.
@@ -444,7 +444,7 @@
 StringRef ELFObjectFile<target_endianness, is64Bits>
                        ::getSectionContents(DataRefImpl Sec) const {
   const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
-  const char *start = (char*)base + sec->sh_offset;
+  const char *start = (char*)base() + sec->sh_offset;
   return StringRef(start, sec->sh_size);
 }
 
@@ -458,21 +458,22 @@
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-ELFObjectFile<target_endianness, is64Bits>::ELFObjectFile(MemoryBuffer *Object)
-  : ObjectFile(Object)
+ELFObjectFile<target_endianness, is64Bits>::ELFObjectFile(MemoryBuffer *Object
+                                                          , error_code &ec)
+  : ObjectFile(Binary::isELF, Object, ec)
   , SectionHeaderTable(0)
   , dot_shstrtab_sec(0)
   , dot_strtab_sec(0) {
-  Header = reinterpret_cast<const Elf_Ehdr *>(base);
+  Header = reinterpret_cast<const Elf_Ehdr *>(base());
 
   if (Header->e_shoff == 0)
     return;
 
   SectionHeaderTable =
-    reinterpret_cast<const Elf_Shdr *>(base + Header->e_shoff);
+    reinterpret_cast<const Elf_Shdr *>(base() + Header->e_shoff);
   uint32_t SectionTableSize = Header->e_shnum * Header->e_shentsize;
   if (!(  (const uint8_t *)SectionHeaderTable + SectionTableSize
-         <= base + MapFile->getBufferSize()))
+         <= base() + Data->getBufferSize()))
     // FIXME: Proper error handling.
     report_fatal_error("Section table goes past end of file!");
 
@@ -491,7 +492,7 @@
   dot_shstrtab_sec = getSection(Header->e_shstrndx);
   if (dot_shstrtab_sec) {
     // Verify that the last byte in the string table in a null.
-    if (((const char*)base + dot_shstrtab_sec->sh_offset)
+    if (((const char*)base() + dot_shstrtab_sec->sh_offset)
         [dot_shstrtab_sec->sh_size - 1] != 0)
       // FIXME: Proper error handling.
       report_fatal_error("String table must end with a null terminator!");
@@ -509,7 +510,7 @@
           // FIXME: Proper error handling.
           report_fatal_error("Already found section named .strtab!");
         dot_strtab_sec = sh;
-        const char *dot_strtab = (const char*)base + sh->sh_offset;
+        const char *dot_strtab = (const char*)base() + sh->sh_offset;
           if (dot_strtab[sh->sh_size - 1] != 0)
             // FIXME: Proper error handling.
             report_fatal_error("String table must end with a null terminator!");
@@ -548,7 +549,7 @@
                                           ::begin_sections() const {
   DataRefImpl ret;
   memset(&ret, 0, sizeof(DataRefImpl));
-  ret.p = reinterpret_cast<intptr_t>(base + Header->e_shoff);
+  ret.p = reinterpret_cast<intptr_t>(base() + Header->e_shoff);
   return section_iterator(SectionRef(ret, this));
 }
 
@@ -557,7 +558,7 @@
                                           ::end_sections() const {
   DataRefImpl ret;
   memset(&ret, 0, sizeof(DataRefImpl));
-  ret.p = reinterpret_cast<intptr_t>(base
+  ret.p = reinterpret_cast<intptr_t>(base()
                                      + Header->e_shoff
                                      + (Header->e_shentsize * Header->e_shnum));
   return section_iterator(SectionRef(ret, this));
@@ -613,7 +614,7 @@
 ELFObjectFile<target_endianness, is64Bits>::getSymbol(DataRefImpl Symb) const {
   const Elf_Shdr *sec = SymbolTableSections[Symb.d.b];
   return reinterpret_cast<const Elf_Sym *>(
-           base
+           base()
            + sec->sh_offset
            + (Symb.d.a * sec->sh_entsize));
 }
@@ -656,8 +657,8 @@
   assert(section && section->sh_type == ELF::SHT_STRTAB && "Invalid section!");
   if (offset >= section->sh_size)
     // FIXME: Proper error handling.
-    report_fatal_error("Sybol name offset outside of string table!");
-  return (const char *)base + section->sh_offset + offset;
+    report_fatal_error("Symbol name offset outside of string table!");
+  return (const char *)base() + section->sh_offset + offset;
 }
 
 // EI_CLASS, EI_DATA.
@@ -673,14 +674,15 @@
 
   ObjectFile *ObjectFile::createELFObjectFile(MemoryBuffer *Object) {
     std::pair<unsigned char, unsigned char> Ident = getElfArchType(Object);
+    error_code ec;
     if (Ident.first == ELF::ELFCLASS32 && Ident.second == ELF::ELFDATA2LSB)
-      return new ELFObjectFile<support::little, false>(Object);
+      return new ELFObjectFile<support::little, false>(Object, ec);
     else if (Ident.first == ELF::ELFCLASS32 && Ident.second == ELF::ELFDATA2MSB)
-      return new ELFObjectFile<support::big, false>(Object);
+      return new ELFObjectFile<support::big, false>(Object, ec);
     else if (Ident.first == ELF::ELFCLASS64 && Ident.second == ELF::ELFDATA2LSB)
-      return new ELFObjectFile<support::little, true>(Object);
+      return new ELFObjectFile<support::little, true>(Object, ec);
     else if (Ident.first == ELF::ELFCLASS64 && Ident.second == ELF::ELFDATA2MSB)
-      return new ELFObjectFile<support::big, true>(Object);
+      return new ELFObjectFile<support::big, true>(Object, ec);
     // FIXME: Proper error handling.
     report_fatal_error("Not an ELF object file!");
   }

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=133870&r1=133869&r2=133870&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Sat Jun 25 12:54:50 2011
@@ -32,8 +32,8 @@
 
 class MachOObjectFile : public ObjectFile {
 public:
-  MachOObjectFile(MemoryBuffer *Object, MachOObject *MOO)
-    : ObjectFile(Object),
+  MachOObjectFile(MemoryBuffer *Object, MachOObject *MOO, error_code &ec)
+    : ObjectFile(Binary::isMachO, Object, ec),
       MachOObj(MOO),
       RegisteredStringTable(std::numeric_limits<uint32_t>::max()) {}
 
@@ -73,11 +73,12 @@
 };
 
 ObjectFile *ObjectFile::createMachOObjectFile(MemoryBuffer *Buffer) {
+  error_code ec;
   std::string Err;
   MachOObject *MachOObj = MachOObject::LoadFromBuffer(Buffer, &Err);
   if (!MachOObj)
     return NULL;
-  return new MachOObjectFile(Buffer, MachOObj);
+  return new MachOObjectFile(Buffer, MachOObj, ec);
 }
 
 /*===-- Symbols -----------------------------------------------------------===*/

Modified: llvm/trunk/lib/Object/ObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ObjectFile.cpp?rev=133870&r1=133869&r2=133870&view=diff
==============================================================================
--- llvm/trunk/lib/Object/ObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/ObjectFile.cpp Sat Jun 25 12:54:50 2011
@@ -21,18 +21,8 @@
 using namespace llvm;
 using namespace object;
 
-ObjectFile::ObjectFile(MemoryBuffer *Object)
-  : MapFile(Object) {
-  assert(MapFile && "Must be a valid MemoryBuffer!");
-  base = reinterpret_cast<const uint8_t *>(MapFile->getBufferStart());
-}
-
-ObjectFile::~ObjectFile() {
-  delete MapFile;
-}
-
-StringRef ObjectFile::getFilename() const {
-  return MapFile->getBufferIdentifier();
+ObjectFile::ObjectFile(unsigned int Type, MemoryBuffer *source, error_code &ec)
+  : Binary(Type, source) {
 }
 
 ObjectFile *ObjectFile::createObjectFile(MemoryBuffer *Object) {

Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=133870&r1=133869&r2=133870&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
+++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Sat Jun 25 12:54:50 2011
@@ -277,7 +277,7 @@
     SymbolList.push_back(s);
   }
 
-  CurrentFilename = obj->getFilename();
+  CurrentFilename = obj->getFileName();
   SortAndPrintSymbolList();
 }
 



From bigcheesegs at gmail.com  Sat Jun 25 12:54:59 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Sat, 25 Jun 2011 17:54:59 -0000
Subject: [llvm-commits] [llvm] r133871 -
	/llvm/trunk/tools/llvm-nm/llvm-nm.cpp
Message-ID: <20110625175500.0D7CA2A6C12C@llvm.org>

Author: mspencer
Date: Sat Jun 25 12:54:59 2011
New Revision: 133871

URL: http://llvm.org/viewvc/llvm-project?rev=133871&view=rev
Log:
Modify llvm-nm to use new Binary creation method.

Modified:
    llvm/trunk/tools/llvm-nm/llvm-nm.cpp

Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=133871&r1=133870&r2=133871&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
+++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Sat Jun 25 12:54:59 2011
@@ -317,13 +317,13 @@
     MultipleFiles = true;
     std::for_each (Modules.begin(), Modules.end(), DumpSymbolNamesFromModule);
   } else if (aPath.isObjectFile()) {
-    std::auto_ptr<ObjectFile> obj(ObjectFile::createObjectFile(aPath.str()));
-    if (!obj.get()) {
-      errs() << ToolName << ": " << Filename << ": "
-             << "Failed to open object file\n";
+    OwningPtr<Binary> obj;
+    if (error_code ec = object::createBinary(aPath.str(), obj)) {
+      errs() << ToolName << ": " << Filename << ": " << ec.message() << ".\n";
       return;
     }
-    DumpSymbolNamesFromObject(obj.get());
+    if (object::ObjectFile *o = dyn_cast<ObjectFile>(obj.get()))
+      DumpSymbolNamesFromObject(o);
   } else {
     errs() << ToolName << ": " << Filename << ": "
            << "unrecognizable file type\n";



From bigcheesegs at gmail.com  Sat Jun 25 12:55:24 2011
From: bigcheesegs at gmail.com (Michael J. Spencer)
Date: Sat, 25 Jun 2011 17:55:24 -0000
Subject: [llvm-commits] [llvm] r133872 - in /llvm/trunk:
 include/llvm/Object/COFF.h include/llvm/Object/Error.h
 include/llvm/Object/ObjectFile.h lib/Object/COFFObjectFile.cpp
 lib/Object/ELFObjectFile.cpp lib/Object/Error.cpp
 lib/Object/MachOObjectFile.cpp lib/Object/Object.cpp
 tools/llvm-nm/llvm-nm.cpp tools/llvm-objdump/llvm-objdump.cpp
Message-ID: <20110625175524.211DA2A6C12C@llvm.org>

Author: mspencer
Date: Sat Jun 25 12:55:23 2011
New Revision: 133872

URL: http://llvm.org/viewvc/llvm-project?rev=133872&view=rev
Log:
Object: Add proper error handling.

Modified:
    llvm/trunk/include/llvm/Object/COFF.h
    llvm/trunk/include/llvm/Object/Error.h
    llvm/trunk/include/llvm/Object/ObjectFile.h
    llvm/trunk/lib/Object/COFFObjectFile.cpp
    llvm/trunk/lib/Object/ELFObjectFile.cpp
    llvm/trunk/lib/Object/Error.cpp
    llvm/trunk/lib/Object/MachOObjectFile.cpp
    llvm/trunk/lib/Object/Object.cpp
    llvm/trunk/tools/llvm-nm/llvm-nm.cpp
    llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp

Modified: llvm/trunk/include/llvm/Object/COFF.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/COFF.h?rev=133872&r1=133871&r2=133872&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/COFF.h (original)
+++ llvm/trunk/include/llvm/Object/COFF.h Sat Jun 25 12:55:23 2011
@@ -69,29 +69,33 @@
 
 class COFFObjectFile : public ObjectFile {
 private:
-        uint64_t         HeaderOff;
   const coff_file_header *Header;
   const coff_section     *SectionTable;
   const coff_symbol      *SymbolTable;
   const char             *StringTable;
+        uint32_t          StringTableSize;
 
-  const coff_section     *getSection(std::size_t index) const;
-  const char             *getString(std::size_t offset) const;
+        error_code        getSection(int32_t index,
+                                     const coff_section *&Res) const;
+        error_code        getString(uint32_t offset, StringRef &Res) const;
+
+  const coff_symbol      *toSymb(DataRefImpl Symb) const;
+  const coff_section     *toSec(DataRefImpl Sec) const;
 
 protected:
-  virtual SymbolRef getSymbolNext(DataRefImpl Symb) const;
-  virtual StringRef getSymbolName(DataRefImpl Symb) const;
-  virtual uint64_t  getSymbolAddress(DataRefImpl Symb) const;
-  virtual uint64_t  getSymbolSize(DataRefImpl Symb) const;
-  virtual char      getSymbolNMTypeChar(DataRefImpl Symb) const;
-  virtual bool      isSymbolInternal(DataRefImpl Symb) const;
-
-  virtual SectionRef getSectionNext(DataRefImpl Sec) const;
-  virtual StringRef  getSectionName(DataRefImpl Sec) const;
-  virtual uint64_t   getSectionAddress(DataRefImpl Sec) const;
-  virtual uint64_t   getSectionSize(DataRefImpl Sec) const;
-  virtual StringRef  getSectionContents(DataRefImpl Sec) const;
-  virtual bool       isSectionText(DataRefImpl Sec) const;
+  virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
+  virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;
+  virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) const;
+  virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
+  virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const;
+  virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const;
+
+  virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const;
+  virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
+  virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) const;
+  virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
+  virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) const;
+  virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
 
 public:
   COFFObjectFile(MemoryBuffer *Object, error_code &ec);

Modified: llvm/trunk/include/llvm/Object/Error.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/Error.h?rev=133872&r1=133871&r2=133872&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/Error.h (original)
+++ llvm/trunk/include/llvm/Object/Error.h Sat Jun 25 12:55:23 2011
@@ -25,7 +25,8 @@
 enum _ {
   success = 0,
   invalid_file_type,
-  parse_failed
+  parse_failed,
+  unexpected_eof
 };
   _ v_;
 

Modified: llvm/trunk/include/llvm/Object/ObjectFile.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Object/ObjectFile.h?rev=133872&r1=133871&r2=133872&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Object/ObjectFile.h (original)
+++ llvm/trunk/include/llvm/Object/ObjectFile.h Sat Jun 25 12:55:23 2011
@@ -17,6 +17,7 @@
 #include "llvm/Object/Binary.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/DataTypes.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MemoryBuffer.h"
 #include <cstring>
 
@@ -29,7 +30,7 @@
   struct {
     uint32_t a, b;
   } d;
-  intptr_t p;
+  uintptr_t p;
 };
 
 static bool operator ==(const DataRefImpl &a, const DataRefImpl &b) {
@@ -38,6 +39,19 @@
   return std::memcmp(&a, &b, sizeof(DataRefImpl)) == 0;
 }
 
+class RelocationRef {
+  DataRefImpl RelocationPimpl;
+  const ObjectFile *OwningObject;
+
+public:
+  RelocationRef() : OwningObject(NULL) { std::memset(&RelocationPimpl, 0, sizeof(RelocationPimpl)); }
+  RelocationRef(DataRefImpl RelocationP, const ObjectFile *Owner);
+
+  bool operator==(const RelocationRef &Other) const;
+
+  error_code getNext(RelocationRef &Result);
+};
+
 /// SymbolRef - This is a value type class that represents a single symbol in
 /// the list of symbols in the object file.
 class SymbolRef {
@@ -45,23 +59,24 @@
   const ObjectFile *OwningObject;
 
 public:
+  SymbolRef() : OwningObject(NULL) { std::memset(&SymbolPimpl, 0, sizeof(SymbolPimpl)); }
   SymbolRef(DataRefImpl SymbolP, const ObjectFile *Owner);
 
   bool operator==(const SymbolRef &Other) const;
 
-  SymbolRef getNext() const;
+  error_code getNext(SymbolRef &Result) const;
 
-  StringRef getName() const;
-  uint64_t  getAddress() const;
-  uint64_t  getSize() const;
+  error_code getName(StringRef &Result) const;
+  error_code getAddress(uint64_t &Result) const;
+  error_code getSize(uint64_t &Result) const;
 
   /// Returns the ascii char that should be displayed in a symbol table dump via
   /// nm for this symbol.
-  char      getNMTypeChar() const;
+  error_code getNMTypeChar(char &Result) const;
 
   /// Returns true for symbols that are internal to the object file format such
   /// as section symbols.
-  bool      isInternal() const;
+  error_code isInternal(bool &Result) const;
 };
 
 /// SectionRef - This is a value type class that represents a single section in
@@ -71,19 +86,20 @@
   const ObjectFile *OwningObject;
 
 public:
+  SectionRef() : OwningObject(NULL) { std::memset(&SectionPimpl, 0, sizeof(SectionPimpl)); }
   SectionRef(DataRefImpl SectionP, const ObjectFile *Owner);
 
   bool operator==(const SectionRef &Other) const;
 
-  SectionRef getNext() const;
+  error_code getNext(SectionRef &Result) const;
 
-  StringRef getName() const;
-  uint64_t  getAddress() const;
-  uint64_t  getSize() const;
-  StringRef getContents() const;
+  error_code getName(StringRef &Result) const;
+  error_code getAddress(uint64_t &Result) const;
+  error_code getSize(uint64_t &Result) const;
+  error_code getContents(StringRef &Result) const;
 
   // FIXME: Move to the normalization layer when it's created.
-  bool      isText() const;
+  error_code isText(bool &Result) const;
 };
 
 const uint64_t UnknownAddressOrSize = ~0ULL;
@@ -108,22 +124,25 @@
   // entry in the memory mapped object file. SymbolPimpl cannot contain any
   // virtual functions because then it could not point into the memory mapped
   // file.
+  //
+  // Implementations assume that the DataRefImpl is valid and has not been
+  // modified externally. It's UB otherwise.
   friend class SymbolRef;
-  virtual SymbolRef getSymbolNext(DataRefImpl Symb) const = 0;
-  virtual StringRef getSymbolName(DataRefImpl Symb) const = 0;
-  virtual uint64_t  getSymbolAddress(DataRefImpl Symb) const = 0;
-  virtual uint64_t  getSymbolSize(DataRefImpl Symb) const = 0;
-  virtual char      getSymbolNMTypeChar(DataRefImpl Symb) const = 0;
-  virtual bool      isSymbolInternal(DataRefImpl Symb) const = 0;
+  virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const = 0;
+  virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const = 0;
+  virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) const =0;
+  virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const = 0;
+  virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const = 0;
+  virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const = 0;
 
   // Same as above for SectionRef.
   friend class SectionRef;
-  virtual SectionRef getSectionNext(DataRefImpl Sec) const = 0;
-  virtual StringRef  getSectionName(DataRefImpl Sec) const = 0;
-  virtual uint64_t   getSectionAddress(DataRefImpl Sec) const = 0;
-  virtual uint64_t   getSectionSize(DataRefImpl Sec) const = 0;
-  virtual StringRef  getSectionContents(DataRefImpl Sec) const = 0;
-  virtual bool       isSectionText(DataRefImpl Sec) const = 0;
+  virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const = 0;
+  virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const = 0;
+  virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) const =0;
+  virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const = 0;
+  virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res)const=0;
+  virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const = 0;
 
 
 public:
@@ -146,8 +165,12 @@
       return !(*this == other);
     }
 
-    content_iterator& operator++() {  // Preincrement
-      Current = Current.getNext();
+    content_iterator& increment(error_code &err) {
+      content_type next;
+      if (error_code ec = Current.getNext(next))
+        err = ec;
+      else
+        Current = next;
       return *this;
     }
   };
@@ -196,28 +219,28 @@
   return SymbolPimpl == Other.SymbolPimpl;
 }
 
-inline SymbolRef SymbolRef::getNext() const {
-  return OwningObject->getSymbolNext(SymbolPimpl);
+inline error_code SymbolRef::getNext(SymbolRef &Result) const {
+  return OwningObject->getSymbolNext(SymbolPimpl, Result);
 }
 
-inline StringRef SymbolRef::getName() const {
-  return OwningObject->getSymbolName(SymbolPimpl);
+inline error_code SymbolRef::getName(StringRef &Result) const {
+  return OwningObject->getSymbolName(SymbolPimpl, Result);
 }
 
-inline uint64_t SymbolRef::getAddress() const {
-  return OwningObject->getSymbolAddress(SymbolPimpl);
+inline error_code SymbolRef::getAddress(uint64_t &Result) const {
+  return OwningObject->getSymbolAddress(SymbolPimpl, Result);
 }
 
-inline uint64_t SymbolRef::getSize() const {
-  return OwningObject->getSymbolSize(SymbolPimpl);
+inline error_code SymbolRef::getSize(uint64_t &Result) const {
+  return OwningObject->getSymbolSize(SymbolPimpl, Result);
 }
 
-inline char SymbolRef::getNMTypeChar() const {
-  return OwningObject->getSymbolNMTypeChar(SymbolPimpl);
+inline error_code SymbolRef::getNMTypeChar(char &Result) const {
+  return OwningObject->getSymbolNMTypeChar(SymbolPimpl, Result);
 }
 
-inline bool SymbolRef::isInternal() const {
-  return OwningObject->isSymbolInternal(SymbolPimpl);
+inline error_code SymbolRef::isInternal(bool &Result) const {
+  return OwningObject->isSymbolInternal(SymbolPimpl, Result);
 }
 
 
@@ -231,28 +254,28 @@
   return SectionPimpl == Other.SectionPimpl;
 }
 
-inline SectionRef SectionRef::getNext() const {
-  return OwningObject->getSectionNext(SectionPimpl);
+inline error_code SectionRef::getNext(SectionRef &Result) const {
+  return OwningObject->getSectionNext(SectionPimpl, Result);
 }
 
-inline StringRef SectionRef::getName() const {
-  return OwningObject->getSectionName(SectionPimpl);
+inline error_code SectionRef::getName(StringRef &Result) const {
+  return OwningObject->getSectionName(SectionPimpl, Result);
 }
 
-inline uint64_t SectionRef::getAddress() const {
-  return OwningObject->getSectionAddress(SectionPimpl);
+inline error_code SectionRef::getAddress(uint64_t &Result) const {
+  return OwningObject->getSectionAddress(SectionPimpl, Result);
 }
 
-inline uint64_t SectionRef::getSize() const {
-  return OwningObject->getSectionSize(SectionPimpl);
+inline error_code SectionRef::getSize(uint64_t &Result) const {
+  return OwningObject->getSectionSize(SectionPimpl, Result);
 }
 
-inline StringRef SectionRef::getContents() const {
-  return OwningObject->getSectionContents(SectionPimpl);
+inline error_code SectionRef::getContents(StringRef &Result) const {
+  return OwningObject->getSectionContents(SectionPimpl, Result);
 }
 
-inline bool SectionRef::isText() const {
-  return OwningObject->isSectionText(SectionPimpl);
+inline error_code SectionRef::isText(bool &Result) const {
+  return OwningObject->isSectionText(SectionPimpl, Result);
 }
 
 } // end namespace object

Modified: llvm/trunk/lib/Object/COFFObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/COFFObjectFile.cpp?rev=133872&r1=133871&r2=133872&view=diff
==============================================================================
--- llvm/trunk/lib/Object/COFFObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/COFFObjectFile.cpp Sat Jun 25 12:55:23 2011
@@ -25,74 +25,165 @@
 using support::little16_t;
 }
 
-SymbolRef COFFObjectFile::getSymbolNext(DataRefImpl Symb) const {
-  const coff_symbol *symb = reinterpret_cast<const coff_symbol*>(Symb.p);
+namespace {
+// Returns false if size is greater than the buffer size. And sets ec.
+bool checkSize(const MemoryBuffer *m, error_code &ec, uint64_t size) {
+  if (m->getBufferSize() < size) {
+    ec = object_error::unexpected_eof;
+    return false;
+  }
+  return true;
+}
+
+// Returns false if any bytes in [addr, addr + size) fall outsize of m.
+bool checkAddr(const MemoryBuffer *m,
+               error_code &ec,
+               uintptr_t addr,
+               uint64_t size) {
+  if (addr + size < addr ||
+      addr + size < size ||
+      addr + size > uintptr_t(m->getBufferEnd())) {
+    ec = object_error::unexpected_eof;
+    return false;
+  }
+  return true;
+}
+}
+
+const coff_symbol *COFFObjectFile::toSymb(DataRefImpl Symb) const {
+  const coff_symbol *addr = reinterpret_cast<const coff_symbol*>(Symb.p);
+
+# ifndef NDEBUG
+  // Verify that the symbol points to a valid entry in the symbol table.
+  uintptr_t offset = uintptr_t(addr) - uintptr_t(base());
+  if (offset < Header->PointerToSymbolTable
+      || offset >= Header->PointerToSymbolTable
+         + (Header->NumberOfSymbols * sizeof(coff_symbol)))
+    report_fatal_error("Symbol was outside of symbol table.");
+
+  assert((offset - Header->PointerToSymbolTable) % sizeof(coff_symbol)
+         == 0 && "Symbol did not point to the beginning of a symbol");
+# endif
+
+  return addr;
+}
+
+const coff_section *COFFObjectFile::toSec(DataRefImpl Sec) const {
+  const coff_section *addr = reinterpret_cast<const coff_section*>(Sec.p);
+
+# ifndef NDEBUG
+  // Verify that the section points to a valid entry in the section table.
+  if (addr < SectionTable
+      || addr >= (SectionTable + Header->NumberOfSections))
+    report_fatal_error("Section was outside of section table.");
+
+  uintptr_t offset = uintptr_t(addr) - uintptr_t(SectionTable);
+  assert(offset % sizeof(coff_section) == 0 &&
+         "Section did not point to the beginning of a section");
+# endif
+
+  return addr;
+}
+
+error_code COFFObjectFile::getSymbolNext(DataRefImpl Symb,
+                                         SymbolRef &Result) const {
+  const coff_symbol *symb = toSymb(Symb);
   symb += 1 + symb->NumberOfAuxSymbols;
-  Symb.p = reinterpret_cast<intptr_t>(symb);
-  return SymbolRef(Symb, this);
+  Symb.p = reinterpret_cast<uintptr_t>(symb);
+  Result = SymbolRef(Symb, this);
+  return object_error::success;
 }
 
-StringRef COFFObjectFile::getSymbolName(DataRefImpl Symb) const {
-  const coff_symbol *symb = reinterpret_cast<const coff_symbol*>(Symb.p);
+ error_code COFFObjectFile::getSymbolName(DataRefImpl Symb,
+                                          StringRef &Result) const {
+  const coff_symbol *symb = toSymb(Symb);
   // Check for string table entry. First 4 bytes are 0.
   if (symb->Name.Offset.Zeroes == 0) {
     uint32_t Offset = symb->Name.Offset.Offset;
-    return StringRef(getString(Offset));
+    if (error_code ec = getString(Offset, Result))
+      return ec;
+    return object_error::success;
   }
 
   if (symb->Name.ShortName[7] == 0)
     // Null terminated, let ::strlen figure out the length.
-    return StringRef(symb->Name.ShortName);
-  // Not null terminated, use all 8 bytes.
-  return StringRef(symb->Name.ShortName, 8);
+    Result = StringRef(symb->Name.ShortName);
+  else
+    // Not null terminated, use all 8 bytes.
+    Result = StringRef(symb->Name.ShortName, 8);
+  return object_error::success;
 }
 
-uint64_t COFFObjectFile::getSymbolAddress(DataRefImpl Symb) const {
-  const coff_symbol *symb = reinterpret_cast<const coff_symbol*>(Symb.p);
-  const coff_section *Section = getSection(symb->SectionNumber);
-  char Type = getSymbolNMTypeChar(Symb);
+error_code COFFObjectFile::getSymbolAddress(DataRefImpl Symb,
+                                            uint64_t &Result) const {
+  const coff_symbol *symb = toSymb(Symb);
+  const coff_section *Section;
+  if (error_code ec = getSection(symb->SectionNumber, Section))
+    return ec;
+  char Type;
+  if (error_code ec = getSymbolNMTypeChar(Symb, Type))
+    return ec;
   if (Type == 'U' || Type == 'w')
-    return UnknownAddressOrSize;
-  if (Section)
-    return Section->VirtualAddress + symb->Value;
-  return symb->Value;
+    Result = UnknownAddressOrSize;
+  else if (Section)
+    Result = Section->VirtualAddress + symb->Value;
+  else
+    Result = symb->Value;
+  return object_error::success;
 }
 
-uint64_t COFFObjectFile::getSymbolSize(DataRefImpl Symb) const {
+error_code COFFObjectFile::getSymbolSize(DataRefImpl Symb,
+                                         uint64_t &Result) const {
   // FIXME: Return the correct size. This requires looking at all the symbols
   //        in the same section as this symbol, and looking for either the next
   //        symbol, or the end of the section.
-  const coff_symbol *symb = reinterpret_cast<const coff_symbol*>(Symb.p);
-  const coff_section *Section = getSection(symb->SectionNumber);
-  char Type = getSymbolNMTypeChar(Symb);
+  const coff_symbol *symb = toSymb(Symb);
+  const coff_section *Section;
+  if (error_code ec = getSection(symb->SectionNumber, Section))
+    return ec;
+  char Type;
+  if (error_code ec = getSymbolNMTypeChar(Symb, Type))
+    return ec;
   if (Type == 'U' || Type == 'w')
-    return UnknownAddressOrSize;
-  if (Section)
-    return Section->SizeOfRawData - symb->Value;
-  return 0;
+    Result = UnknownAddressOrSize;
+  else if (Section)
+    Result = Section->SizeOfRawData - symb->Value;
+  else
+    Result = 0;
+  return object_error::success;
 }
 
-char COFFObjectFile::getSymbolNMTypeChar(DataRefImpl Symb) const {
-  const coff_symbol *symb = reinterpret_cast<const coff_symbol*>(Symb.p);
-  char ret = StringSwitch<char>(getSymbolName(Symb))
+error_code COFFObjectFile::getSymbolNMTypeChar(DataRefImpl Symb,
+                                               char &Result) const {
+  const coff_symbol *symb = toSymb(Symb);
+  StringRef name;
+  if (error_code ec = getSymbolName(Symb, name))
+    return ec;
+  char ret = StringSwitch<char>(name)
     .StartsWith(".debug", 'N')
     .StartsWith(".sxdata", 'N')
     .Default('?');
 
-  if (ret != '?')
-    return ret;
+  if (ret != '?') {
+    Result = ret;
+    return object_error::success;
+  }
 
   uint32_t Characteristics = 0;
-  if (const coff_section *Section = getSection(symb->SectionNumber)) {
+  if (symb->SectionNumber > 0) {
+    const coff_section *Section;
+    if (error_code ec = getSection(symb->SectionNumber, Section))
+      return ec;
     Characteristics = Section->Characteristics;
   }
 
   switch (symb->SectionNumber) {
   case COFF::IMAGE_SYM_UNDEFINED:
     // Check storage classes.
-    if (symb->StorageClass == COFF::IMAGE_SYM_CLASS_WEAK_EXTERNAL)
-      return 'w'; // Don't do ::toupper.
-    else
+    if (symb->StorageClass == COFF::IMAGE_SYM_CLASS_WEAK_EXTERNAL) {
+      Result = 'w';
+      return object_error::success; // Don't do ::toupper.
+    } else
       ret = 'u';
     break;
   case COFF::IMAGE_SYM_ABSOLUTE:
@@ -124,22 +215,28 @@
   if (symb->StorageClass == COFF::IMAGE_SYM_CLASS_EXTERNAL)
     ret = ::toupper(ret);
 
-  return ret;
+  Result = ret;
+  return object_error::success;
 }
 
-bool COFFObjectFile::isSymbolInternal(DataRefImpl Symb) const {
-  return false;
+error_code COFFObjectFile::isSymbolInternal(DataRefImpl Symb,
+                                            bool &Result) const {
+  Result = false;
+  return object_error::success;
 }
 
-SectionRef COFFObjectFile::getSectionNext(DataRefImpl Sec) const {
-  const coff_section *sec = reinterpret_cast<const coff_section*>(Sec.p);
+error_code COFFObjectFile::getSectionNext(DataRefImpl Sec,
+                                          SectionRef &Result) const {
+  const coff_section *sec = toSec(Sec);
   sec += 1;
-  Sec.p = reinterpret_cast<intptr_t>(sec);
-  return SectionRef(Sec, this);
+  Sec.p = reinterpret_cast<uintptr_t>(sec);
+  Result = SectionRef(Sec, this);
+  return object_error::success;
 }
 
-StringRef COFFObjectFile::getSectionName(DataRefImpl Sec) const {
-  const coff_section *sec = reinterpret_cast<const coff_section*>(Sec.p);
+error_code COFFObjectFile::getSectionName(DataRefImpl Sec,
+                                          StringRef &Result) const {
+  const coff_section *sec = toSec(Sec);
   StringRef name;
   if (sec->Name[7] == 0)
     // Null terminated, let ::strlen figure out the length.
@@ -152,66 +249,117 @@
   if (name[0] == '/') {
     uint32_t Offset;
     name.substr(1).getAsInteger(10, Offset);
-    return StringRef(getString(Offset));
+    if (error_code ec = getString(Offset, name))
+      return ec;
   }
 
-  // It's just a normal name.
-  return name;
-}
-
-uint64_t COFFObjectFile::getSectionAddress(DataRefImpl Sec) const {
-  const coff_section *sec = reinterpret_cast<const coff_section*>(Sec.p);
-  return sec->VirtualAddress;
-}
-
-uint64_t COFFObjectFile::getSectionSize(DataRefImpl Sec) const {
-  const coff_section *sec = reinterpret_cast<const coff_section*>(Sec.p);
-  return sec->SizeOfRawData;
-}
-
-StringRef COFFObjectFile::getSectionContents(DataRefImpl Sec) const {
-  const coff_section *sec = reinterpret_cast<const coff_section*>(Sec.p);
-  return StringRef(reinterpret_cast<const char *>(base()
-                   + sec->PointerToRawData),
-                   sec->SizeOfRawData);
+  Result = name;
+  return object_error::success;
 }
 
-bool COFFObjectFile::isSectionText(DataRefImpl Sec) const {
-  const coff_section *sec = reinterpret_cast<const coff_section*>(Sec.p);
-  return sec->Characteristics & COFF::IMAGE_SCN_CNT_CODE;
+error_code COFFObjectFile::getSectionAddress(DataRefImpl Sec,
+                                             uint64_t &Result) const {
+  const coff_section *sec = toSec(Sec);
+  Result = sec->VirtualAddress;
+  return object_error::success;
+}
+
+error_code COFFObjectFile::getSectionSize(DataRefImpl Sec,
+                                          uint64_t &Result) const {
+  const coff_section *sec = toSec(Sec);
+  Result = sec->SizeOfRawData;
+  return object_error::success;
+}
+
+error_code COFFObjectFile::getSectionContents(DataRefImpl Sec,
+                                              StringRef &Result) const {
+  const coff_section *sec = toSec(Sec);
+  // The only thing that we need to verify is that the contents is contained
+  // within the file bounds. We don't need to make sure it doesn't cover other
+  // data, as there's nothing that says that is not allowed.
+  uintptr_t con_start = uintptr_t(base()) + sec->PointerToRawData;
+  uintptr_t con_end = con_start + sec->SizeOfRawData;
+  if (con_end >= uintptr_t(Data->getBufferEnd()))
+    return object_error::parse_failed;
+  Result = StringRef(reinterpret_cast<const char*>(con_start),
+                     sec->SizeOfRawData);
+  return object_error::success;
+}
+
+error_code COFFObjectFile::isSectionText(DataRefImpl Sec,
+                                         bool &Result) const {
+  const coff_section *sec = toSec(Sec);
+  Result = sec->Characteristics & COFF::IMAGE_SCN_CNT_CODE;
+  return object_error::success;
 }
 
 COFFObjectFile::COFFObjectFile(MemoryBuffer *Object, error_code &ec)
   : ObjectFile(Binary::isCOFF, Object, ec) {
+  // Check that we at least have enough room for a header.
+  if (!checkSize(Data, ec, sizeof(coff_file_header))) return;
 
-  HeaderOff = 0;
+  // The actual starting location of the COFF header in the file. This can be
+  // non-zero in PE/COFF files.
+  uint64_t HeaderStart = 0;
 
+  // Check if this is a PE/COFF file.
   if (base()[0] == 0x4d && base()[1] == 0x5a) {
     // PE/COFF, seek through MS-DOS compatibility stub and 4-byte
     // PE signature to find 'normal' COFF header.
-    HeaderOff += *reinterpret_cast<const ulittle32_t *>(base() + 0x3c);
-    HeaderOff += 4;
+    if (!checkSize(Data, ec, 0x3c + 8)) return;
+    HeaderStart += *reinterpret_cast<const ulittle32_t *>(base() + 0x3c);
+    // Check the PE header. ("PE\0\0")
+    if (StringRef(reinterpret_cast<const char *>(base() + HeaderStart), 4)
+        != "PE\0\0") {
+      ec = object_error::parse_failed;
+      return;
+    }
+    HeaderStart += 4; // Skip the PE Header.
   }
 
-  Header = reinterpret_cast<const coff_file_header *>(base() + HeaderOff);
+  Header = reinterpret_cast<const coff_file_header *>(base() + HeaderStart);
+  if (!checkAddr(Data, ec, uintptr_t(Header), sizeof(coff_file_header)))
+    return;
+  
   SectionTable =
     reinterpret_cast<const coff_section *>( base()
-                                          + HeaderOff
+                                          + HeaderStart
                                           + sizeof(coff_file_header)
                                           + Header->SizeOfOptionalHeader);
+  if (!checkAddr(Data, ec, uintptr_t(SectionTable),
+                 Header->NumberOfSections * sizeof(coff_section)))
+    return;
+
   SymbolTable =
     reinterpret_cast<const coff_symbol *>(base()
-    + Header->PointerToSymbolTable);
+                                          + Header->PointerToSymbolTable);
+  if (!checkAddr(Data, ec, uintptr_t(SymbolTable),
+                 Header->NumberOfSymbols * sizeof(coff_symbol)))
+    return;
 
   // Find string table.
   StringTable = reinterpret_cast<const char *>(base())
-              + Header->PointerToSymbolTable
-              + Header->NumberOfSymbols * 18;
+                + Header->PointerToSymbolTable
+                + Header->NumberOfSymbols * sizeof(coff_symbol);
+  if (!checkAddr(Data, ec, uintptr_t(StringTable), sizeof(ulittle32_t)))
+    return;
+
+  StringTableSize = *reinterpret_cast<const ulittle32_t *>(StringTable);
+  if (!checkAddr(Data, ec, uintptr_t(StringTable), StringTableSize))
+    return;
+  // Check that the string table is null terminated if has any in it.
+  if (StringTableSize < 4
+      || (StringTableSize > 4 && StringTable[StringTableSize - 1] != 0)) {
+    ec = object_error::parse_failed;
+    return;
+  }
+  
+  ec = object_error::success;
 }
 
 ObjectFile::symbol_iterator COFFObjectFile::begin_symbols() const {
   DataRefImpl ret;
-  memset(&ret, 0, sizeof(DataRefImpl));
+  std::memset(&ret, 0, sizeof(DataRefImpl));
   ret.p = reinterpret_cast<intptr_t>(SymbolTable);
   return symbol_iterator(SymbolRef(ret, this));
 }
@@ -219,21 +367,21 @@
 ObjectFile::symbol_iterator COFFObjectFile::end_symbols() const {
   // The symbol table ends where the string table begins.
   DataRefImpl ret;
-  memset(&ret, 0, sizeof(DataRefImpl));
+  std::memset(&ret, 0, sizeof(DataRefImpl));
   ret.p = reinterpret_cast<intptr_t>(StringTable);
   return symbol_iterator(SymbolRef(ret, this));
 }
 
 ObjectFile::section_iterator COFFObjectFile::begin_sections() const {
   DataRefImpl ret;
-  memset(&ret, 0, sizeof(DataRefImpl));
+  std::memset(&ret, 0, sizeof(DataRefImpl));
   ret.p = reinterpret_cast<intptr_t>(SectionTable);
   return section_iterator(SectionRef(ret, this));
 }
 
 ObjectFile::section_iterator COFFObjectFile::end_sections() const {
   DataRefImpl ret;
-  memset(&ret, 0, sizeof(DataRefImpl));
+  std::memset(&ret, 0, sizeof(DataRefImpl));
   ret.p = reinterpret_cast<intptr_t>(SectionTable + Header->NumberOfSections);
   return section_iterator(SectionRef(ret, this));
 }
@@ -264,18 +412,30 @@
   }
 }
 
-const coff_section *COFFObjectFile::getSection(std::size_t index) const {
-  if (index > 0 && index <= Header->NumberOfSections)
-    return SectionTable + (index - 1);
-  return 0;
+error_code COFFObjectFile::getSection(int32_t index,
+                                      const coff_section *&Result) const {
+  // Check for special index values.
+  if (index == COFF::IMAGE_SYM_UNDEFINED ||
+      index == COFF::IMAGE_SYM_ABSOLUTE ||
+      index == COFF::IMAGE_SYM_DEBUG)
+    Result = NULL;
+  else if (index > 0 && index <= Header->NumberOfSections)
+    // We already verified the section table data, so no need to check again.
+    Result = SectionTable + (index - 1);
+  else
+    return object_error::parse_failed;
+  return object_error::success;
 }
 
-const char *COFFObjectFile::getString(std::size_t offset) const {
-  const ulittle32_t *StringTableSize =
-    reinterpret_cast<const ulittle32_t *>(StringTable);
-  if (offset < *StringTableSize)
-    return StringTable + offset;
-  return 0;
+error_code COFFObjectFile::getString(uint32_t offset,
+                                     StringRef &Result) const {
+  if (StringTableSize <= 4)
+    // Tried to get a string from an empty string table.
+    return object_error::parse_failed;
+  if (offset >= StringTableSize)
+    return object_error::unexpected_eof;
+  Result = StringRef(StringTable + offset);
+  return object_error::success;
 }
 
 namespace llvm {

Modified: llvm/trunk/lib/Object/ELFObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/ELFObjectFile.cpp?rev=133872&r1=133871&r2=133872&view=diff
==============================================================================
--- llvm/trunk/lib/Object/ELFObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/ELFObjectFile.cpp Sat Jun 25 12:55:23 2011
@@ -222,19 +222,19 @@
   const char     *getString(const Elf_Shdr *section, uint32_t offset) const;
 
 protected:
-  virtual SymbolRef getSymbolNext(DataRefImpl Symb) const;
-  virtual StringRef getSymbolName(DataRefImpl Symb) const;
-  virtual uint64_t  getSymbolAddress(DataRefImpl Symb) const;
-  virtual uint64_t  getSymbolSize(DataRefImpl Symb) const;
-  virtual char      getSymbolNMTypeChar(DataRefImpl Symb) const;
-  virtual bool      isSymbolInternal(DataRefImpl Symb) const;
-
-  virtual SectionRef getSectionNext(DataRefImpl Sec) const;
-  virtual StringRef  getSectionName(DataRefImpl Sec) const;
-  virtual uint64_t   getSectionAddress(DataRefImpl Sec) const;
-  virtual uint64_t   getSectionSize(DataRefImpl Sec) const;
-  virtual StringRef  getSectionContents(DataRefImpl Sec) const;
-  virtual bool       isSectionText(DataRefImpl Sec) const;
+  virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
+  virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;
+  virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) const;
+  virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
+  virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const;
+  virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const;
+
+  virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const;
+  virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
+  virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) const;
+  virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
+  virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) const;
+  virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
 
 public:
   ELFObjectFile(MemoryBuffer *Object, error_code &ec);
@@ -269,8 +269,9 @@
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-SymbolRef ELFObjectFile<target_endianness, is64Bits>
-                       ::getSymbolNext(DataRefImpl Symb) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getSymbolNext(DataRefImpl Symb,
+                                        SymbolRef &Result) const {
   validateSymbol(Symb);
   const Elf_Shdr *SymbolTableSection = SymbolTableSections[Symb.d.b];
 
@@ -287,63 +288,80 @@
     }
   }
 
-  return SymbolRef(Symb, this);
+  Result = SymbolRef(Symb, this);
+  return object_error::success;
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-StringRef ELFObjectFile<target_endianness, is64Bits>
-                       ::getSymbolName(DataRefImpl Symb) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getSymbolName(DataRefImpl Symb,
+                                        StringRef &Result) const {
   validateSymbol(Symb);
   const Elf_Sym  *symb = getSymbol(Symb);
   if (symb->st_name == 0) {
     const Elf_Shdr *section = getSection(symb->st_shndx);
     if (!section)
-      return "";
-    return getString(dot_shstrtab_sec, section->sh_name);
+      Result = "";
+    else
+      Result = getString(dot_shstrtab_sec, section->sh_name);
+    return object_error::success;
   }
 
   // Use the default symbol table name section.
-  return getString(dot_strtab_sec, symb->st_name);
+  Result = getString(dot_strtab_sec, symb->st_name);
+  return object_error::success;
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-uint64_t ELFObjectFile<target_endianness, is64Bits>
-                      ::getSymbolAddress(DataRefImpl Symb) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getSymbolAddress(DataRefImpl Symb,
+                                           uint64_t &Result) const {
   validateSymbol(Symb);
   const Elf_Sym  *symb = getSymbol(Symb);
   const Elf_Shdr *Section;
   switch (symb->st_shndx) {
   case ELF::SHN_COMMON:
    // Undefined symbols have no address yet.
-  case ELF::SHN_UNDEF: return UnknownAddressOrSize;
-  case ELF::SHN_ABS: return symb->st_value;
+  case ELF::SHN_UNDEF:
+    Result = UnknownAddressOrSize;
+    return object_error::success;
+  case ELF::SHN_ABS:
+    Result = symb->st_value;
+    return object_error::success;
   default: Section = getSection(symb->st_shndx);
   }
 
   switch (symb->getType()) {
-  case ELF::STT_SECTION: return Section ? Section->sh_addr
-                                        : UnknownAddressOrSize;
+  case ELF::STT_SECTION:
+    Result = Section ? Section->sh_addr : UnknownAddressOrSize;
+    return object_error::success;
   case ELF::STT_FUNC:
   case ELF::STT_OBJECT:
   case ELF::STT_NOTYPE:
-    return symb->st_value;
-  default: return UnknownAddressOrSize;
+    Result = symb->st_value;
+    return object_error::success;
+  default:
+    Result = UnknownAddressOrSize;
+    return object_error::success;
   }
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-uint64_t ELFObjectFile<target_endianness, is64Bits>
-                      ::getSymbolSize(DataRefImpl Symb) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getSymbolSize(DataRefImpl Symb,
+                                        uint64_t &Result) const {
   validateSymbol(Symb);
   const Elf_Sym  *symb = getSymbol(Symb);
   if (symb->st_size == 0)
-    return UnknownAddressOrSize;
-  return symb->st_size;
+    Result = UnknownAddressOrSize;
+  Result = symb->st_size;
+  return object_error::success;
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-char ELFObjectFile<target_endianness, is64Bits>
-                  ::getSymbolNMTypeChar(DataRefImpl Symb) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getSymbolNMTypeChar(DataRefImpl Symb,
+                                              char &Result) const {
   validateSymbol(Symb);
   const Elf_Sym  *symb = getSymbol(Symb);
   const Elf_Shdr *Section = getSection(symb->st_shndx);
@@ -390,71 +408,91 @@
         ret = 'W';
   }
 
-  if (ret == '?' && symb->getType() == ELF::STT_SECTION)
-    return StringSwitch<char>(getSymbolName(Symb))
+  if (ret == '?' && symb->getType() == ELF::STT_SECTION) {
+    StringRef name;
+    if (error_code ec = getSymbolName(Symb, name))
+      return ec;
+    Result = StringSwitch<char>(name)
       .StartsWith(".debug", 'N')
       .StartsWith(".note", 'n');
+    return object_error::success;
+  }
 
-  return ret;
+  Result = ret;
+  return object_error::success;
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-bool ELFObjectFile<target_endianness, is64Bits>
-                  ::isSymbolInternal(DataRefImpl Symb) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::isSymbolInternal(DataRefImpl Symb,
+                                           bool &Result) const {
   validateSymbol(Symb);
   const Elf_Sym  *symb = getSymbol(Symb);
 
   if (  symb->getType() == ELF::STT_FILE
      || symb->getType() == ELF::STT_SECTION)
-    return true;
-  return false;
+    Result = true;
+  Result = false;
+  return object_error::success;
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-SectionRef ELFObjectFile<target_endianness, is64Bits>
-                        ::getSectionNext(DataRefImpl Sec) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getSectionNext(DataRefImpl Sec, SectionRef &Result) const {
   const uint8_t *sec = reinterpret_cast<const uint8_t *>(Sec.p);
   sec += Header->e_shentsize;
   Sec.p = reinterpret_cast<intptr_t>(sec);
-  return SectionRef(Sec, this);
+  Result = SectionRef(Sec, this);
+  return object_error::success;
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-StringRef ELFObjectFile<target_endianness, is64Bits>
-                       ::getSectionName(DataRefImpl Sec) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getSectionName(DataRefImpl Sec,
+                                         StringRef &Result) const {
   const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
-  return StringRef(getString(dot_shstrtab_sec, sec->sh_name));
+  Result = StringRef(getString(dot_shstrtab_sec, sec->sh_name));
+  return object_error::success;
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-uint64_t ELFObjectFile<target_endianness, is64Bits>
-                      ::getSectionAddress(DataRefImpl Sec) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getSectionAddress(DataRefImpl Sec,
+                                            uint64_t &Result) const {
   const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
-  return sec->sh_addr;
+  Result = sec->sh_addr;
+  return object_error::success;
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-uint64_t ELFObjectFile<target_endianness, is64Bits>
-                      ::getSectionSize(DataRefImpl Sec) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getSectionSize(DataRefImpl Sec,
+                                         uint64_t &Result) const {
   const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
-  return sec->sh_size;
+  Result = sec->sh_size;
+  return object_error::success;
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-StringRef ELFObjectFile<target_endianness, is64Bits>
-                       ::getSectionContents(DataRefImpl Sec) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::getSectionContents(DataRefImpl Sec,
+                                             StringRef &Result) const {
   const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
-  const char *start = (char*)base() + sec->sh_offset;
-  return StringRef(start, sec->sh_size);
+  const char *start = (const char*)base() + sec->sh_offset;
+  Result = StringRef(start, sec->sh_size);
+  return object_error::success;
 }
 
 template<support::endianness target_endianness, bool is64Bits>
-bool ELFObjectFile<target_endianness, is64Bits>
-                  ::isSectionText(DataRefImpl Sec) const {
+error_code ELFObjectFile<target_endianness, is64Bits>
+                        ::isSectionText(DataRefImpl Sec,
+                                        bool &Result) const {
   const Elf_Shdr *sec = reinterpret_cast<const Elf_Shdr *>(Sec.p);
   if (sec->sh_flags & ELF::SHF_EXECINSTR)
-    return true;
-  return false;
+    Result = true;
+  else
+    Result = false;
+  return object_error::success;
 }
 
 template<support::endianness target_endianness, bool is64Bits>

Modified: llvm/trunk/lib/Object/Error.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/Error.cpp?rev=133872&r1=133871&r2=133872&view=diff
==============================================================================
--- llvm/trunk/lib/Object/Error.cpp (original)
+++ llvm/trunk/lib/Object/Error.cpp Sat Jun 25 12:55:23 2011
@@ -37,6 +37,8 @@
     return "The file was not recognized as a valid object file";
   case object_error::parse_failed:
     return "Invalid data was encountered while parsing the file";
+  case object_error::unexpected_eof:
+    return "The end of the file was unexpectedly encountered";
   default:
     llvm_unreachable("An enumerator of object_error does not have a message "
                      "defined.");

Modified: llvm/trunk/lib/Object/MachOObjectFile.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/MachOObjectFile.cpp?rev=133872&r1=133871&r2=133872&view=diff
==============================================================================
--- llvm/trunk/lib/Object/MachOObjectFile.cpp (original)
+++ llvm/trunk/lib/Object/MachOObjectFile.cpp Sat Jun 25 12:55:23 2011
@@ -47,19 +47,19 @@
   virtual unsigned getArch() const;
 
 protected:
-  virtual SymbolRef getSymbolNext(DataRefImpl Symb) const;
-  virtual StringRef getSymbolName(DataRefImpl Symb) const;
-  virtual uint64_t  getSymbolAddress(DataRefImpl Symb) const;
-  virtual uint64_t  getSymbolSize(DataRefImpl Symb) const;
-  virtual char      getSymbolNMTypeChar(DataRefImpl Symb) const;
-  virtual bool      isSymbolInternal(DataRefImpl Symb) const;
-
-  virtual SectionRef getSectionNext(DataRefImpl Sec) const;
-  virtual StringRef  getSectionName(DataRefImpl Sec) const;
-  virtual uint64_t   getSectionAddress(DataRefImpl Sec) const;
-  virtual uint64_t   getSectionSize(DataRefImpl Sec) const;
-  virtual StringRef  getSectionContents(DataRefImpl Sec) const;
-  virtual bool       isSectionText(DataRefImpl Sec) const;
+  virtual error_code getSymbolNext(DataRefImpl Symb, SymbolRef &Res) const;
+  virtual error_code getSymbolName(DataRefImpl Symb, StringRef &Res) const;
+  virtual error_code getSymbolAddress(DataRefImpl Symb, uint64_t &Res) const;
+  virtual error_code getSymbolSize(DataRefImpl Symb, uint64_t &Res) const;
+  virtual error_code getSymbolNMTypeChar(DataRefImpl Symb, char &Res) const;
+  virtual error_code isSymbolInternal(DataRefImpl Symb, bool &Res) const;
+
+  virtual error_code getSectionNext(DataRefImpl Sec, SectionRef &Res) const;
+  virtual error_code getSectionName(DataRefImpl Sec, StringRef &Res) const;
+  virtual error_code getSectionAddress(DataRefImpl Sec, uint64_t &Res) const;
+  virtual error_code getSectionSize(DataRefImpl Sec, uint64_t &Res) const;
+  virtual error_code getSectionContents(DataRefImpl Sec, StringRef &Res) const;
+  virtual error_code isSectionText(DataRefImpl Sec, bool &Res) const;
 
 private:
   MachOObject *MachOObj;
@@ -115,29 +115,38 @@
 }
 
 
-SymbolRef MachOObjectFile::getSymbolNext(DataRefImpl DRI) const {
+error_code MachOObjectFile::getSymbolNext(DataRefImpl DRI,
+                                          SymbolRef &Result) const {
   DRI.d.b++;
   moveToNextSymbol(DRI);
-  return SymbolRef(DRI, this);
+  Result = SymbolRef(DRI, this);
+  return object_error::success;
 }
 
-StringRef MachOObjectFile::getSymbolName(DataRefImpl DRI) const {
+error_code MachOObjectFile::getSymbolName(DataRefImpl DRI,
+                                          StringRef &Result) const {
   InMemoryStruct<macho::SymbolTableEntry> Entry;
   getSymbolTableEntry(DRI, Entry);
-  return MachOObj->getStringAtIndex(Entry->StringIndex);
+  Result = MachOObj->getStringAtIndex(Entry->StringIndex);
+  return object_error::success;
 }
 
-uint64_t MachOObjectFile::getSymbolAddress(DataRefImpl DRI) const {
+error_code MachOObjectFile::getSymbolAddress(DataRefImpl DRI,
+                                             uint64_t &Result) const {
   InMemoryStruct<macho::SymbolTableEntry> Entry;
   getSymbolTableEntry(DRI, Entry);
-  return Entry->Value;
+  Result = Entry->Value;
+  return object_error::success;
 }
 
-uint64_t MachOObjectFile::getSymbolSize(DataRefImpl DRI) const {
-  return UnknownAddressOrSize;
+error_code MachOObjectFile::getSymbolSize(DataRefImpl DRI,
+                                          uint64_t &Result) const {
+  Result = UnknownAddressOrSize;
+  return object_error::success;
 }
 
-char MachOObjectFile::getSymbolNMTypeChar(DataRefImpl DRI) const {
+error_code MachOObjectFile::getSymbolNMTypeChar(DataRefImpl DRI,
+                                                char &Result) const {
   InMemoryStruct<macho::SymbolTableEntry> Entry;
   getSymbolTableEntry(DRI, Entry);
 
@@ -157,13 +166,16 @@
 
   if (Entry->Flags & (macho::STF_External | macho::STF_PrivateExtern))
     Char = toupper(Char);
-  return Char;
+  Result = Char;
+  return object_error::success;
 }
 
-bool MachOObjectFile::isSymbolInternal(DataRefImpl DRI) const {
+error_code MachOObjectFile::isSymbolInternal(DataRefImpl DRI,
+                                             bool &Result) const {
   InMemoryStruct<macho::SymbolTableEntry> Entry;
   getSymbolTableEntry(DRI, Entry);
-  return Entry->Flags & macho::STF_StabsEntryMask;
+  Result = Entry->Flags & macho::STF_StabsEntryMask;
+  return object_error::success;
 }
 
 ObjectFile::symbol_iterator MachOObjectFile::begin_symbols() const {
@@ -205,10 +217,12 @@
   }
 }
 
-SectionRef MachOObjectFile::getSectionNext(DataRefImpl DRI) const {
+error_code MachOObjectFile::getSectionNext(DataRefImpl DRI,
+                                           SectionRef &Result) const {
   DRI.d.b++;
   moveToNextSection(DRI);
-  return SectionRef(DRI, this);
+  Result = SectionRef(DRI, this);
+  return object_error::success;
 }
 
 void
@@ -220,43 +234,53 @@
   MachOObj->ReadSection(LCI, DRI.d.b, Res);
 }
 
-StringRef MachOObjectFile::getSectionName(DataRefImpl DRI) const {
+error_code MachOObjectFile::getSectionName(DataRefImpl DRI,
+                                           StringRef &Result) const {
   InMemoryStruct<macho::SegmentLoadCommand> SLC;
   LoadCommandInfo LCI = MachOObj->getLoadCommandInfo(DRI.d.a);
   MachOObj->ReadSegmentLoadCommand(LCI, SLC);
   InMemoryStruct<macho::Section> Sect;
   MachOObj->ReadSection(LCI, DRI.d.b, Sect);
 
-  static char Result[34];
-  strcpy(Result, SLC->Name);
-  strcat(Result, ",");
-  strcat(Result, Sect->Name);
-  return StringRef(Result);
+  static char result[34];
+  strcpy(result, SLC->Name);
+  strcat(result, ",");
+  strcat(result, Sect->Name);
+  Result = StringRef(result);
+  return object_error::success;
 }
 
-uint64_t MachOObjectFile::getSectionAddress(DataRefImpl DRI) const {
+error_code MachOObjectFile::getSectionAddress(DataRefImpl DRI,
+                                              uint64_t &Result) const {
   InMemoryStruct<macho::Section> Sect;
   getSection(DRI, Sect);
-  return Sect->Address;
+  Result = Sect->Address;
+  return object_error::success;
 }
 
-uint64_t MachOObjectFile::getSectionSize(DataRefImpl DRI) const {
+error_code MachOObjectFile::getSectionSize(DataRefImpl DRI,
+                                           uint64_t &Result) const {
   InMemoryStruct<macho::Section> Sect;
   getSection(DRI, Sect);
-  return Sect->Size;
+  Result = Sect->Size;
+  return object_error::success;
 }
 
-StringRef MachOObjectFile::getSectionContents(DataRefImpl DRI) const {
+error_code MachOObjectFile::getSectionContents(DataRefImpl DRI,
+                                               StringRef &Result) const {
   InMemoryStruct<macho::Section> Sect;
   getSection(DRI, Sect);
-  return MachOObj->getData(Sect->Offset, Sect->Size);
+  Result = MachOObj->getData(Sect->Offset, Sect->Size);
+  return object_error::success;
 }
 
-bool MachOObjectFile::isSectionText(DataRefImpl DRI) const {
+error_code MachOObjectFile::isSectionText(DataRefImpl DRI,
+                                          bool &Result) const {
   InMemoryStruct<macho::SegmentLoadCommand> SLC;
   LoadCommandInfo LCI = MachOObj->getLoadCommandInfo(DRI.d.a);
   MachOObj->ReadSegmentLoadCommand(LCI, SLC);
-  return !strcmp(SLC->Name, "__TEXT");
+  Result = !strcmp(SLC->Name, "__TEXT");
+  return object_error::success;
 }
 
 ObjectFile::section_iterator MachOObjectFile::begin_sections() const {

Modified: llvm/trunk/lib/Object/Object.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Object/Object.cpp?rev=133872&r1=133871&r2=133872&view=diff
==============================================================================
--- llvm/trunk/lib/Object/Object.cpp (original)
+++ llvm/trunk/lib/Object/Object.cpp Sat Jun 25 12:55:23 2011
@@ -41,19 +41,28 @@
 }
 
 void LLVMMoveToNextSection(LLVMSectionIteratorRef SI) {
-  // We can't use unwrap() here because the argument to ++ must be an lvalue.
-  ++*reinterpret_cast<ObjectFile::section_iterator*>(SI);
+  error_code ec;
+  unwrap(SI)->increment(ec);
+  if (ec) report_fatal_error("LLVMMoveToNextSection failed: " + ec.message());
 }
 
 const char *LLVMGetSectionName(LLVMSectionIteratorRef SI) {
-  return (*unwrap(SI))->getName().data();
+  StringRef ret;
+  if (error_code ec = (*unwrap(SI))->getName(ret))
+   report_fatal_error(ec.message());
+  return ret.data();
 }
 
 uint64_t LLVMGetSectionSize(LLVMSectionIteratorRef SI) {
-  return (*unwrap(SI))->getSize();
+  uint64_t ret;
+  if (error_code ec = (*unwrap(SI))->getSize(ret))
+    report_fatal_error(ec.message());
+  return ret;
 }
 
 const char *LLVMGetSectionContents(LLVMSectionIteratorRef SI) {
-  return (*unwrap(SI))->getContents().data();
+  StringRef ret;
+  if (error_code ec = (*unwrap(SI))->getContents(ret))
+    report_fatal_error(ec.message());
+  return ret.data();
 }
-

Modified: llvm/trunk/tools/llvm-nm/llvm-nm.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-nm/llvm-nm.cpp?rev=133872&r1=133871&r2=133872&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-nm/llvm-nm.cpp (original)
+++ llvm/trunk/tools/llvm-nm/llvm-nm.cpp Sat Jun 25 12:55:23 2011
@@ -143,6 +143,14 @@
   StringRef CurrentFilename;
   typedef std::vector<NMSymbol> SymbolListT;
   SymbolListT SymbolList;
+
+  bool error(error_code ec) {
+    if (!ec) return false;
+
+    outs() << ToolName << ": error reading file: " << ec.message() << ".\n";
+    outs().flush();
+    return true;
+  }
 }
 
 static void SortAndPrintSymbolList() {
@@ -261,19 +269,25 @@
 }
 
 static void DumpSymbolNamesFromObject(ObjectFile *obj) {
+  error_code ec;
   for (ObjectFile::symbol_iterator i = obj->begin_symbols(),
-                                   e = obj->end_symbols(); i != e; ++i) {
-    if (!DebugSyms && i->isInternal())
+                                   e = obj->end_symbols();
+                                   i != e; i.increment(ec)) {
+    if (error(ec)) break;
+    bool internal;
+    if (error(i->isInternal(internal))) break;
+    if (!DebugSyms && internal)
       continue;
     NMSymbol s;
     s.Size = object::UnknownAddressOrSize;
     s.Address = object::UnknownAddressOrSize;
-    if (PrintSize || SizeSort)
-      s.Size = i->getSize();
+    if (PrintSize || SizeSort) {
+      if (error(i->getSize(s.Size))) break;
+    }
     if (PrintAddress)
-      s.Address = i->getAddress();
-    s.TypeChar = i->getNMTypeChar();
-    s.Name     = i->getName();
+      if (error(i->getAddress(s.Address))) break;
+    if (error(i->getNMTypeChar(s.TypeChar))) break;
+    if (error(i->getName(s.Name))) break;
     SymbolList.push_back(s);
   }
 

Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=133872&r1=133871&r2=133872&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original)
+++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Sat Jun 25 12:55:23 2011
@@ -69,6 +69,14 @@
                             "see -version for available targets"));
 
   StringRef ToolName;
+
+  bool error(error_code ec) {
+    if (!ec) return false;
+
+    outs() << ToolName << ": error reading file: " << ec.message() << ".\n";
+    outs().flush();
+    return true;
+  }
 }
 
 static const Target *GetTarget(const ObjectFile *Obj = NULL) {
@@ -161,12 +169,18 @@
   outs() << Filename
          << ":\tfile format " << Obj->getFileFormatName() << "\n\n\n";
 
+  error_code ec;
   for (ObjectFile::section_iterator i = Obj->begin_sections(),
                                     e = Obj->end_sections();
-                                    i != e; ++i) {
-    if (!i->isText())
-      continue;
-    outs() << "Disassembly of section " << i->getName() << ":\n\n";
+                                    i != e; i.increment(ec)) {
+    if (error(ec)) break;
+    bool text;
+    if (error(i->isText(text))) break;
+    if (!text) continue;
+
+    StringRef name;
+    if (error(i->getName(name))) break;
+    outs() << "Disassembly of section " << name << ":\n\n";
 
     // Set up disassembler.
     OwningPtr<const MCAsmInfo> AsmInfo(TheTarget->createAsmInfo(TripleName));
@@ -202,7 +216,8 @@
       return;
     }
 
-    StringRef Bytes = i->getContents();
+    StringRef Bytes;
+    if (error(i->getContents(Bytes))) break;
     StringRefMemoryObject memoryObject(Bytes);
     uint64_t Size;
     uint64_t Index;
@@ -217,7 +232,9 @@
 #     endif
 
       if (DisAsm->getInstruction(Inst, Size, memoryObject, Index, DebugOut)) {
-        outs() << format("%8x:\t", i->getAddress() + Index);
+        uint64_t addr;
+        if (error(i->getAddress(addr))) break;
+        outs() << format("%8x:\t", addr + Index);
         DumpBytes(StringRef(Bytes.data() + Index, Size));
         IP->printInst(&Inst, outs());
         outs() << "\n";



From dan at dneg.com  Sat Jun 25 13:16:28 2011
From: dan at dneg.com (Dan Bailey)
Date: Sat, 25 Jun 2011 18:16:28 -0000
Subject: [llvm-commits] [llvm] r133873 - in /llvm/trunk:
 lib/Target/PTX/PTXAsmPrinter.cpp lib/Target/PTX/PTXCallingConv.td
 lib/Target/PTX/PTXISelLowering.cpp lib/Target/PTX/PTXInstrInfo.cpp
 lib/Target/PTX/PTXInstrInfo.td lib/Target/PTX/PTXRegisterInfo.td
 lib/Target/PTX/generate-register-td.py test/CodeGen/PTX/cvt.ll
 test/CodeGen/PTX/ld.ll test/CodeGen/PTX/mov.ll test/CodeGen/PTX/st.ll
Message-ID: <20110625181629.0E99A2A6C12C@llvm.org>

Author: drb
Date: Sat Jun 25 13:16:28 2011
New Revision: 133873

URL: http://llvm.org/viewvc/llvm-project?rev=133873&view=rev
Log:
PTX: Reverting implementation of i8.

The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is
not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support
boolean values.


Modified:
    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
    llvm/trunk/lib/Target/PTX/PTXCallingConv.td
    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
    llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td
    llvm/trunk/lib/Target/PTX/generate-register-td.py
    llvm/trunk/test/CodeGen/PTX/cvt.ll
    llvm/trunk/test/CodeGen/PTX/ld.ll
    llvm/trunk/test/CodeGen/PTX/mov.ll
    llvm/trunk/test/CodeGen/PTX/st.ll

Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133873&r1=133872&r2=133873&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Sat Jun 25 13:16:28 2011
@@ -92,7 +92,6 @@
 #define TEST_REGCLS(cls, clsstr)                \
   if (PTX::cls ## RegisterClass->contains(RegNo)) return # clsstr;
   TEST_REGCLS(RegPred, pred);
-  TEST_REGCLS(RegI8,  b8);
   TEST_REGCLS(RegI16, b16);
   TEST_REGCLS(RegI32, b32);
   TEST_REGCLS(RegI64, b64);
@@ -125,7 +124,6 @@
       case Type::IntegerTyID:
         switch (type->getPrimitiveSizeInBits()) {
           default: llvm_unreachable("Unknown integer bit-width");
-          case 8:  return ".u8";
           case 16: return ".u16";
           case 32: return ".u32";
           case 64: return ".u64";

Modified: llvm/trunk/lib/Target/PTX/PTXCallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXCallingConv.td?rev=133873&r1=133872&r2=133873&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXCallingConv.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXCallingConv.td Sat Jun 25 13:16:28 2011
@@ -15,7 +15,6 @@
 // PTX Formal Parameter Calling Convention
 def CC_PTX : CallingConv<[
   CCIfType<[i1],      CCAssignToReg<[P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, P36, P37, P38, P39, P40, P41, P42, P43, P44, P45, P46, P47, P48, P49, P50, P51, P52, P53, P54, P55, P56, P57, P58, P59, P60, P61, P62, P63, P64, P65, P66, P67, P68, P69, P70, P71, P72, P73, P74, P75, P76, P77, P78, P79, P80, P81, P82, P83, P84, P85, P86, P87, P88, P89, P90, P91, P92, P93, P94, P95, P96, P97, P98, P99, P100, P101, P102, P103, P104, P105, P106, P107, P108, P109, P110, P111, P112, P113, P114, P115, P116, P117, P118, P119, P120, P121, P122, P123, P124, P125, P126, P127]>>,
-  CCIfType<[i8],      CCAssignToReg<[RQ12, RQ13, RQ14, RQ15, RQ16, RQ17, RQ18, RQ19, RQ20, RQ21, RQ22, RQ23, RQ24, RQ25, RQ26, RQ27, RQ28, RQ29, RQ30, RQ31, RQ32, RQ33, RQ34, RQ35, RQ36, RQ37, RQ38, RQ39, RQ40, RQ41, RQ42, RQ43, RQ44, RQ45, RQ46, RQ47, RQ48, RQ49, RQ50, RQ51, RQ52, RQ53, RQ54, RQ55, RQ56, RQ57, RQ58, RQ59, RQ60, RQ61, RQ62, RQ63, RQ64, RQ65, RQ66, RQ67, RQ68, RQ69, RQ70, RQ71, RQ72, RQ73, RQ74, RQ75, RQ76, RQ77, RQ78, RQ79, RQ80, RQ81, RQ82, RQ83, RQ84, RQ85, RQ86, RQ87, RQ88, RQ89, RQ90, RQ91, RQ92, RQ93, RQ94, RQ95, RQ96, RQ97, RQ98, RQ99, RQ100, RQ101, RQ102, RQ103, RQ104, RQ105, RQ106, RQ107, RQ108, RQ109, RQ110, RQ111, RQ112, RQ113, RQ114, RQ115, RQ116, RQ117, RQ118, RQ119, RQ120, RQ121, RQ122, RQ123, RQ124, RQ125, RQ126, RQ127]>>,
   CCIfType<[i16],     CCAssignToReg<[RH12, RH13, RH14, RH15, RH16, RH17, RH18, RH19, RH20, RH21, RH22, RH23, RH24, RH25, RH26, RH27, RH28, RH29, RH30, RH31, RH32, RH33, RH34, RH35, RH36, RH37, RH38, RH39, RH40, RH41, RH42, RH43, RH44, RH45, RH46, RH47, RH48, RH49, RH50, RH51, RH52, RH53, RH54, RH55, RH56, RH57, RH58, RH59, RH60, RH61, RH62, RH63, RH64, RH65, RH66, RH67, RH68, RH69, RH70, RH71, RH72, RH73, RH74, RH75, RH76, RH77, RH78, RH79, RH80, RH81, RH82, RH83, RH84, RH85, RH86, RH87, RH88, RH89, RH90, RH91, RH92, RH93, RH94, RH95, RH96, RH97, RH98, RH99, RH100, RH101, RH102, RH103, RH104, RH105, RH106, RH107, RH108, RH109, RH110, RH111, RH112, RH113, RH114, RH115, RH116, RH117, RH118, RH119, RH120, RH121, RH122, RH123, RH124, RH125, RH126, RH127]>>,
   CCIfType<[i32,f32], CCAssignToReg<[R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127]>>,
   CCIfType<[i64,f64], CCAssignToReg<[RD12, RD13, RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26, RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35, RD36, RD37, RD38, RD39, RD40, RD41, RD42, RD43, RD44, RD45, RD46, RD47, RD48, RD49, RD50, RD51, RD52, RD53, RD54, RD55, RD56, RD57, RD58, RD59, RD60, RD61, RD62, RD63, RD64, RD65, RD66, RD67, RD68, RD69, RD70, RD71, RD72, RD73, RD74, RD75, RD76, RD77, RD78, RD79, RD80, RD81, RD82, RD83, RD84, RD85, RD86, RD87, RD88, RD89, RD90, RD91, RD92, RD93, RD94, RD95, RD96, RD97, RD98, RD99, RD100, RD101, RD102, RD103, RD104, RD105, RD106, RD107, RD108, RD109, RD110, RD111, RD112, RD113, RD114, RD115, RD116, RD117, RD118, RD119, RD120, RD121, RD122, RD123, RD124, RD125, RD126, RD127]>>
@@ -24,7 +23,6 @@
 // PTX Return Value Calling Convention
 def RetCC_PTX : CallingConv<[
   CCIfType<[i1],      CCAssignToReg<[P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11]>>,
-  CCIfType<[i8],      CCAssignToReg<[RQ0, RQ1, RQ2, RQ3, RQ4, RQ5, RQ6, RQ7, RQ8, RQ9, RQ10, RQ11]>>,
   CCIfType<[i16],     CCAssignToReg<[RH0, RH1, RH2, RH3, RH4, RH5, RH6, RH7, RH8, RH9, RH10, RH11]>>,
   CCIfType<[i32,f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11]>>,
   CCIfType<[i64,f64], CCAssignToReg<[RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11]>>

Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=133873&r1=133872&r2=133873&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Sat Jun 25 13:16:28 2011
@@ -40,7 +40,6 @@
   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
   // Set up the register classes.
   addRegisterClass(MVT::i1,  PTX::RegPredRegisterClass);
-  addRegisterClass(MVT::i8,  PTX::RegI8RegisterClass);
   addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
   addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
   addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
@@ -48,48 +47,59 @@
   addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
 
   setBooleanContents(ZeroOrOneBooleanContent);
-
-  setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
-
-  setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
-  setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
-  
-  // Promote i1 type
-  setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
-  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
-  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
+  setMinFunctionAlignment(2);
   
-  setTruncStoreAction(MVT::i8, MVT::i1, Promote);
+  ////////////////////////////////////
+  /////////// Expansion //////////////
+  ////////////////////////////////////
   
-  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+  // (any/zero/sign) extload => load + (any/zero/sign) extend
   
-  // Turn i16 (z)extload into load + (z)extend
   setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
   setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
   setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
-
-  // Turn f32 extload into load + fextend
-  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
-
-  // Turn f64 truncstore into trunc + store.
-  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
-
-  // Customize translation of memory addresses
-  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
-  setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
-
-  // Expand BR_CC into BRCOND
+  
+  // f32 extload => load + fextend
+  
+  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);  
+  
+  // f64 truncstore => trunc + store
+  
+  setTruncStoreAction(MVT::f64, MVT::f32, Expand); 
+  
+  // sign_extend_inreg => sign_extend
+  
+  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
+  
+  // br_cc => brcond
+  
   setOperationAction(ISD::BR_CC, MVT::Other, Expand);
 
-  // Expand SELECT_CC into SETCC
+  // select_cc => setcc
+  
   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
   setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
-
-  // need to lower SETCC of RegPred into bitwise logic
+  
+  ////////////////////////////////////
+  //////////// Legal /////////////////
+  ////////////////////////////////////
+  
+  setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
+  setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
+  
+  ////////////////////////////////////
+  //////////// Custom ////////////////
+  ////////////////////////////////////
+  
+  // customise setcc to use bitwise logic if possible
+  
   setOperationAction(ISD::SETCC, MVT::i1, Custom);
 
-  setMinFunctionAlignment(2);
+  // customize translation of memory addresses
+  
+  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
+  setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
 
   // Compute derived properties from the register classes
   computeRegisterProperties();
@@ -187,7 +197,6 @@
   bool operator==(MVT::SimpleValueType _VT) const { return VT == _VT; }
 } argmap[] = {
   argmap_entry(MVT::i1,  PTX::RegPredRegisterClass),
-  argmap_entry(MVT::i8,  PTX::RegI8RegisterClass),
   argmap_entry(MVT::i16, PTX::RegI16RegisterClass),
   argmap_entry(MVT::i32, PTX::RegI32RegisterClass),
   argmap_entry(MVT::i64, PTX::RegI64RegisterClass),
@@ -264,9 +273,6 @@
       if (RegVT == MVT::i1) {
         TRC = PTX::RegPredRegisterClass;
       }
-      else if (RegVT == MVT::i8) {
-        TRC = PTX::RegI8RegisterClass;
-      }
       else if (RegVT == MVT::i16) {
         TRC = PTX::RegI16RegisterClass;
       }

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=133873&r1=133872&r2=133873&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Sat Jun 25 13:16:28 2011
@@ -33,7 +33,6 @@
   const TargetRegisterClass *cls;
   const int opcode;
 } map[] = {
-  { &PTX::RegI8RegClass,  PTX::MOVU8rr },
   { &PTX::RegI16RegClass, PTX::MOVU16rr },
   { &PTX::RegI32RegClass, PTX::MOVU32rr },
   { &PTX::RegI64RegClass, PTX::MOVU64rr },
@@ -303,9 +302,7 @@
   int OpCode;
 
   // Select the appropriate opcode based on the register class
-  if (RC == PTX::RegI8RegisterClass) {
-    OpCode = PTX::STACKSTOREI8;
-  } else if (RC == PTX::RegI16RegisterClass) {
+  if (RC == PTX::RegI16RegisterClass) {
     OpCode = PTX::STACKSTOREI16;
   }  else if (RC == PTX::RegI32RegisterClass) {
     OpCode = PTX::STACKSTOREI32;
@@ -340,9 +337,7 @@
   int OpCode;
 
   // Select the appropriate opcode based on the register class
-  if (RC == PTX::RegI8RegisterClass) {
-    OpCode = PTX::STACKLOADI8;
-  } else if (RC == PTX::RegI16RegisterClass) {
+  if (RC == PTX::RegI16RegisterClass) {
     OpCode = PTX::STACKLOADI16;
   } else if (RC == PTX::RegI32RegisterClass) {
     OpCode = PTX::STACKLOADI32;

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=133873&r1=133872&r2=133873&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Sat Jun 25 13:16:28 2011
@@ -537,7 +537,6 @@
 }
 
 multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
-  defm u8  : PTX_LD<opstr, ".u8",  RegI8,  pat_load>;
   defm u16 : PTX_LD<opstr, ".u16", RegI16, pat_load>;
   defm u32 : PTX_LD<opstr, ".u32", RegI32, pat_load>;
   defm u64 : PTX_LD<opstr, ".u64", RegI64, pat_load>;
@@ -573,7 +572,6 @@
 }
 
 multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
-  defm u8  : PTX_ST<opstr, ".u8",  RegI8,  pat_store>;
   defm u16 : PTX_ST<opstr, ".u16", RegI16, pat_store>;
   defm u32 : PTX_ST<opstr, ".u32", RegI32, pat_store>;
   defm u64 : PTX_ST<opstr, ".u64", RegI64, pat_store>;
@@ -785,27 +783,22 @@
 let neverHasSideEffects = 1 in {
   def MOVPREDrr
     : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
-  def MOVU8rr
-    : InstPTX<(outs RegI8:$d),   (ins RegI8:$a),   "mov.u8\t$d, $a",  []>;
   def MOVU16rr
-    : InstPTX<(outs RegI16:$d),  (ins RegI16:$a),  "mov.u16\t$d, $a", []>;
+    : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
   def MOVU32rr
-    : InstPTX<(outs RegI32:$d),  (ins RegI32:$a),  "mov.u32\t$d, $a", []>;
+    : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
   def MOVU64rr
-    : InstPTX<(outs RegI64:$d),  (ins RegI64:$a),  "mov.u64\t$d, $a", []>;
+    : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
   def MOVF32rr
-    : InstPTX<(outs RegF32:$d),  (ins RegF32:$a),  "mov.f32\t$d, $a", []>;
+    : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
   def MOVF64rr
-    : InstPTX<(outs RegF64:$d),  (ins RegF64:$a),  "mov.f64\t$d, $a", []>;
+    : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
 }
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
   def MOVPREDri
     : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
               [(set RegPred:$d, imm:$a)]>;
-  def MOVU8ri
-    : InstPTX<(outs RegI8:$d),  (ins i8imm:$a),  "mov.u8\t$d, $a",
-              [(set RegI8:$d, imm:$a)]>;
   def MOVU16ri
     : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
               [(set RegI16:$d, imm:$a)]>;
@@ -845,9 +838,6 @@
   def LDpiPred : InstPTX<(outs RegPred:$d), (ins MEMpi:$a),
                          "ld.param.pred\t$d, [$a]",
                          [(set RegPred:$d, (PTXloadparam timm:$a))]>;
-  def LDpiU8   : InstPTX<(outs RegI8:$d), (ins MEMpi:$a),
-                         "ld.param.u8\t$d, [$a]",
-                         [(set RegI8:$d,  (PTXloadparam timm:$a))]>;
   def LDpiU16  : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
                          "ld.param.u16\t$d, [$a]",
                          [(set RegI16:$d, (PTXloadparam timm:$a))]>;
@@ -867,9 +857,6 @@
   def STpiPred : InstPTX<(outs), (ins MEMret:$d, RegPred:$a),
                          "st.param.pred\t[$d], $a",
                          [(PTXstoreparam timm:$d, RegPred:$a)]>;
-  def STpiU8   : InstPTX<(outs), (ins MEMret:$d, RegI8:$a),
-                         "st.param.u8\t[$d], $a",
-                         [(PTXstoreparam timm:$d, RegI8:$a)]>;
   def STpiU16  : InstPTX<(outs), (ins MEMret:$d, RegI16:$a),
                          "st.param.u16\t[$d], $a",
                          [(PTXstoreparam timm:$d, RegI16:$a)]>;
@@ -900,62 +887,34 @@
 // PTX does not directly support converting to a predicate type, so we fake it
 // by performing a greater-than test between the value and zero.  This follows
 // the C convention that any non-zero value is equivalent to 'true'.
-def CVT_pred_u8
-  : InstPTX<(outs RegPred:$d), (ins RegI8:$a), "setp.gt.b8\t$d, $a, 0",
-            [(set RegPred:$d, (trunc RegI8:$a))]>;
-
 def CVT_pred_u16
-  : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.b16\t$d, $a, 0",
+  : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.u16\t$d, $a, 0",
             [(set RegPred:$d, (trunc RegI16:$a))]>;
 
 def CVT_pred_u32
-  : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.b32\t$d, $a, 0",
+  : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.u32\t$d, $a, 0",
             [(set RegPred:$d, (trunc RegI32:$a))]>;
 
 def CVT_pred_u64
-  : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.b64\t$d, $a, 0",
+  : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.u64\t$d, $a, 0",
             [(set RegPred:$d, (trunc RegI64:$a))]>;
 
 def CVT_pred_f32
-  : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.b32\t$d, $a, 0",
+  : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.f32\t$d, $a, 0",
             [(set RegPred:$d, (fp_to_uint RegF32:$a))]>;
 
 def CVT_pred_f64
-  : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.b64\t$d, $a, 0",
+  : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.f64\t$d, $a, 0",
             [(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
 
-// Conversion to u8
-// PTX does not directly support converting a predicate to a value, so we
-// use a select instruction to select either 0 or 1 (integer or fp) based
-// on the truth value of the predicate.
-def CVT_u8_pred
-  : InstPTX<(outs RegI8:$d), (ins RegPred:$a), "selp.u8\t$d, 1, 0, $a",
-            [(set RegI8:$d, (zext RegPred:$a))]>;
-
-def CVT_u8_preds
-  : InstPTX<(outs RegI8:$d), (ins RegPred:$a), "selp.u8\t$d, 1, 0, $a",
-            [(set RegI8:$d, (sext RegPred:$a))]>;
-
-def CVT_u8_u32
-  : InstPTX<(outs RegI8:$d), (ins RegI32:$a), "cvt.u8.u32\t$d, $a",
-            [(set RegI8:$d, (trunc RegI32:$a))]>;
-
-def CVT_u8_u64
-  : InstPTX<(outs RegI8:$d), (ins RegI64:$a), "cvt.u8.u64\t$d, $a",
-            [(set RegI8:$d, (trunc RegI64:$a))]>;
-
-def CVT_u8_f32
-  : InstPTX<(outs RegI8:$d), (ins RegF32:$a), "cvt.rzi.u8.f32\t$d, $a",
-            [(set RegI8:$d, (fp_to_uint RegF32:$a))]>;
-
-def CVT_u8_f64
-  : InstPTX<(outs RegI8:$d), (ins RegF64:$a), "cvt.rzi.u8.f64\t$d, $a",
-            [(set RegI8:$d, (fp_to_uint RegF64:$a))]>;
-
 // Conversion to u16
 // PTX does not directly support converting a predicate to a value, so we
 // use a select instruction to select either 0 or 1 (integer or fp) based
 // on the truth value of the predicate.
+def CVT_u16_preda
+  : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
+            [(set RegI16:$d, (anyext RegPred:$a))]>;
+
 def CVT_u16_pred
   : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
             [(set RegI16:$d, (zext RegPred:$a))]>;
@@ -964,14 +923,6 @@
   : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
             [(set RegI16:$d, (sext RegPred:$a))]>;
 
-def CVT_u16_u8
-  : InstPTX<(outs RegI16:$d), (ins RegI8:$a), "cvt.u16.u8\t$d, $a",
-            [(set RegI16:$d, (zext RegI8:$a))]>;
-
-def CVT_u16_s8
-  : InstPTX<(outs RegI16:$d), (ins RegI8:$a), "cvt.u16.s8\t$d, $a",
-            [(set RegI16:$d, (sext RegI8:$a))]>;
-
 def CVT_u16_u32
   : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a",
             [(set RegI16:$d, (trunc RegI32:$a))]>;
@@ -994,9 +945,9 @@
   : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
             [(set RegI32:$d, (zext RegPred:$a))]>;
 
-def CVT_u32_u8
-  : InstPTX<(outs RegI32:$d), (ins RegI8:$a), "cvt.u32.u8\t$d, $a",
-            [(set RegI32:$d, (zext RegI8:$a))]>;
+def CVT_u32_b16
+  : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
+            [(set RegI32:$d, (anyext RegI16:$a))]>;
 
 def CVT_u32_u16
   : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
@@ -1006,10 +957,6 @@
   : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
             [(set RegI32:$d, (sext RegPred:$a))]>;
 
-def CVT_u32_s8
-  : InstPTX<(outs RegI32:$d), (ins RegI8:$a), "cvt.u32.s8\t$d, $a",
-            [(set RegI32:$d, (zext RegI8:$a))]>;
-
 def CVT_u32_s16
   : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.s16\t$d, $a",
             [(set RegI32:$d, (sext RegI16:$a))]>;
@@ -1032,30 +979,22 @@
   : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
             [(set RegI64:$d, (zext RegPred:$a))]>;
 
-def CVT_u64_u8
-  : InstPTX<(outs RegI64:$d), (ins RegI8:$a), "cvt.u64.u8\t$d, $a",
-            [(set RegI64:$d, (zext RegI8:$a))]>;
-
-def CVT_u64_u16
-  : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
-            [(set RegI64:$d, (zext RegI16:$a))]>;
-
-def CVT_u64_u32
-  : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
-            [(set RegI64:$d, (zext RegI32:$a))]>;
-
 def CVT_u64_preds
   : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
             [(set RegI64:$d, (sext RegPred:$a))]>;
 
-def CVT_u64_s8
-  : InstPTX<(outs RegI64:$d), (ins RegI8:$a), "cvt.u64.s8\t$d, $a",
-            [(set RegI64:$d, (zext RegI8:$a))]>;
+def CVT_u64_u16
+  : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
+            [(set RegI64:$d, (zext RegI16:$a))]>;
 
 def CVT_u64_s16
   : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.s16\t$d, $a",
             [(set RegI64:$d, (sext RegI16:$a))]>;
 
+def CVT_u64_u32
+  : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
+            [(set RegI64:$d, (zext RegI32:$a))]>;
+
 def CVT_u64_s32
   : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.s32\t$d, $a",
             [(set RegI64:$d, (sext RegI32:$a))]>;
@@ -1075,10 +1014,6 @@
             "selp.f32\t$d, 0F3F800000, 0F00000000, $a",  // 1.0
             [(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
 
-def CVT_f32_u8
-  : InstPTX<(outs RegF32:$d), (ins RegI8:$a), "cvt.rn.f32.u8\t$d, $a",
-            [(set RegF32:$d, (uint_to_fp RegI8:$a))]>;
-
 def CVT_f32_u16
   : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a",
             [(set RegF32:$d, (uint_to_fp RegI16:$a))]>;
@@ -1102,10 +1037,6 @@
             "selp.f64\t$d, 0D3F80000000000000, 0D0000000000000000, $a",  // 1.0
             [(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
 
-def CVT_f64_u8
-  : InstPTX<(outs RegF64:$d), (ins RegI8:$a), "cvt.rn.f64.u8\t$d, $a",
-            [(set RegF64:$d, (uint_to_fp RegI8:$a))]>;
-
 def CVT_f64_u16
   : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a",
             [(set RegF64:$d, (uint_to_fp RegI16:$a))]>;
@@ -1144,8 +1075,6 @@
 
 ///===- Spill Instructions ------------------------------------------------===//
 // Special instructions used for stack spilling
-def STACKSTOREI8  : InstPTX<(outs), (ins i32imm:$d, RegI8:$a),
-                            "mov.u8\ts$d, $a", []>;
 def STACKSTOREI16 : InstPTX<(outs), (ins i32imm:$d, RegI16:$a),
                             "mov.u16\ts$d, $a", []>;
 def STACKSTOREI32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
@@ -1157,8 +1086,6 @@
 def STACKSTOREF64 : InstPTX<(outs), (ins i32imm:$d, RegF64:$a),
                             "mov.f64\ts$d, $a", []>;
 
-def STACKLOADI8  : InstPTX<(outs), (ins RegI8:$d, i32imm:$a),
-                           "mov.u8\t$d, s$a", []>;
 def STACKLOADI16 : InstPTX<(outs), (ins RegI16:$d, i32imm:$a),
                            "mov.u16\t$d, s$a", []>;
 def STACKLOADI32 : InstPTX<(outs), (ins RegI32:$d, i32imm:$a),

Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td?rev=133873&r1=133872&r2=133873&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td Sat Jun 25 13:16:28 2011
@@ -151,137 +151,6 @@
 def P126 : PTXReg<"p126">;
 def P127 : PTXReg<"p127">;
 
-///===- 8-Bit Registers --------------------------------------------------===//
-
-def RQ0 : PTXReg<"rq0">;
-def RQ1 : PTXReg<"rq1">;
-def RQ2 : PTXReg<"rq2">;
-def RQ3 : PTXReg<"rq3">;
-def RQ4 : PTXReg<"rq4">;
-def RQ5 : PTXReg<"rq5">;
-def RQ6 : PTXReg<"rq6">;
-def RQ7 : PTXReg<"rq7">;
-def RQ8 : PTXReg<"rq8">;
-def RQ9 : PTXReg<"rq9">;
-def RQ10 : PTXReg<"rq10">;
-def RQ11 : PTXReg<"rq11">;
-def RQ12 : PTXReg<"rq12">;
-def RQ13 : PTXReg<"rq13">;
-def RQ14 : PTXReg<"rq14">;
-def RQ15 : PTXReg<"rq15">;
-def RQ16 : PTXReg<"rq16">;
-def RQ17 : PTXReg<"rq17">;
-def RQ18 : PTXReg<"rq18">;
-def RQ19 : PTXReg<"rq19">;
-def RQ20 : PTXReg<"rq20">;
-def RQ21 : PTXReg<"rq21">;
-def RQ22 : PTXReg<"rq22">;
-def RQ23 : PTXReg<"rq23">;
-def RQ24 : PTXReg<"rq24">;
-def RQ25 : PTXReg<"rq25">;
-def RQ26 : PTXReg<"rq26">;
-def RQ27 : PTXReg<"rq27">;
-def RQ28 : PTXReg<"rq28">;
-def RQ29 : PTXReg<"rq29">;
-def RQ30 : PTXReg<"rq30">;
-def RQ31 : PTXReg<"rq31">;
-def RQ32 : PTXReg<"rq32">;
-def RQ33 : PTXReg<"rq33">;
-def RQ34 : PTXReg<"rq34">;
-def RQ35 : PTXReg<"rq35">;
-def RQ36 : PTXReg<"rq36">;
-def RQ37 : PTXReg<"rq37">;
-def RQ38 : PTXReg<"rq38">;
-def RQ39 : PTXReg<"rq39">;
-def RQ40 : PTXReg<"rq40">;
-def RQ41 : PTXReg<"rq41">;
-def RQ42 : PTXReg<"rq42">;
-def RQ43 : PTXReg<"rq43">;
-def RQ44 : PTXReg<"rq44">;
-def RQ45 : PTXReg<"rq45">;
-def RQ46 : PTXReg<"rq46">;
-def RQ47 : PTXReg<"rq47">;
-def RQ48 : PTXReg<"rq48">;
-def RQ49 : PTXReg<"rq49">;
-def RQ50 : PTXReg<"rq50">;
-def RQ51 : PTXReg<"rq51">;
-def RQ52 : PTXReg<"rq52">;
-def RQ53 : PTXReg<"rq53">;
-def RQ54 : PTXReg<"rq54">;
-def RQ55 : PTXReg<"rq55">;
-def RQ56 : PTXReg<"rq56">;
-def RQ57 : PTXReg<"rq57">;
-def RQ58 : PTXReg<"rq58">;
-def RQ59 : PTXReg<"rq59">;
-def RQ60 : PTXReg<"rq60">;
-def RQ61 : PTXReg<"rq61">;
-def RQ62 : PTXReg<"rq62">;
-def RQ63 : PTXReg<"rq63">;
-def RQ64 : PTXReg<"rq64">;
-def RQ65 : PTXReg<"rq65">;
-def RQ66 : PTXReg<"rq66">;
-def RQ67 : PTXReg<"rq67">;
-def RQ68 : PTXReg<"rq68">;
-def RQ69 : PTXReg<"rq69">;
-def RQ70 : PTXReg<"rq70">;
-def RQ71 : PTXReg<"rq71">;
-def RQ72 : PTXReg<"rq72">;
-def RQ73 : PTXReg<"rq73">;
-def RQ74 : PTXReg<"rq74">;
-def RQ75 : PTXReg<"rq75">;
-def RQ76 : PTXReg<"rq76">;
-def RQ77 : PTXReg<"rq77">;
-def RQ78 : PTXReg<"rq78">;
-def RQ79 : PTXReg<"rq79">;
-def RQ80 : PTXReg<"rq80">;
-def RQ81 : PTXReg<"rq81">;
-def RQ82 : PTXReg<"rq82">;
-def RQ83 : PTXReg<"rq83">;
-def RQ84 : PTXReg<"rq84">;
-def RQ85 : PTXReg<"rq85">;
-def RQ86 : PTXReg<"rq86">;
-def RQ87 : PTXReg<"rq87">;
-def RQ88 : PTXReg<"rq88">;
-def RQ89 : PTXReg<"rq89">;
-def RQ90 : PTXReg<"rq90">;
-def RQ91 : PTXReg<"rq91">;
-def RQ92 : PTXReg<"rq92">;
-def RQ93 : PTXReg<"rq93">;
-def RQ94 : PTXReg<"rq94">;
-def RQ95 : PTXReg<"rq95">;
-def RQ96 : PTXReg<"rq96">;
-def RQ97 : PTXReg<"rq97">;
-def RQ98 : PTXReg<"rq98">;
-def RQ99 : PTXReg<"rq99">;
-def RQ100 : PTXReg<"rq100">;
-def RQ101 : PTXReg<"rq101">;
-def RQ102 : PTXReg<"rq102">;
-def RQ103 : PTXReg<"rq103">;
-def RQ104 : PTXReg<"rq104">;
-def RQ105 : PTXReg<"rq105">;
-def RQ106 : PTXReg<"rq106">;
-def RQ107 : PTXReg<"rq107">;
-def RQ108 : PTXReg<"rq108">;
-def RQ109 : PTXReg<"rq109">;
-def RQ110 : PTXReg<"rq110">;
-def RQ111 : PTXReg<"rq111">;
-def RQ112 : PTXReg<"rq112">;
-def RQ113 : PTXReg<"rq113">;
-def RQ114 : PTXReg<"rq114">;
-def RQ115 : PTXReg<"rq115">;
-def RQ116 : PTXReg<"rq116">;
-def RQ117 : PTXReg<"rq117">;
-def RQ118 : PTXReg<"rq118">;
-def RQ119 : PTXReg<"rq119">;
-def RQ120 : PTXReg<"rq120">;
-def RQ121 : PTXReg<"rq121">;
-def RQ122 : PTXReg<"rq122">;
-def RQ123 : PTXReg<"rq123">;
-def RQ124 : PTXReg<"rq124">;
-def RQ125 : PTXReg<"rq125">;
-def RQ126 : PTXReg<"rq126">;
-def RQ127 : PTXReg<"rq127">;
-
 ///===- 16-Bit Registers --------------------------------------------------===//
 
 def RH0 : PTXReg<"rh0">;
@@ -679,7 +548,6 @@
 //  Register classes
 //===----------------------------------------------------------------------===//
 def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%u", 0, 127)>;
-def RegI8  : RegisterClass<"PTX", [i8],  8, (sequence "RQ%u", 0, 127)>;
 def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%u", 0, 127)>;
 def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%u", 0, 127)>;
 def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%u", 0, 127)>;

Modified: llvm/trunk/lib/Target/PTX/generate-register-td.py
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/generate-register-td.py?rev=133873&r1=133872&r2=133873&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/generate-register-td.py (original)
+++ llvm/trunk/lib/Target/PTX/generate-register-td.py Sat Jun 25 13:16:28 2011
@@ -15,16 +15,15 @@
 from sys import argv, exit, stdout
 
 
-if len(argv) != 6:
-    print('Usage: generate-register-td.py <num_preds> <num_8> <num_16> <num_32> <num_64>')
+if len(argv) != 5:
+    print('Usage: generate-register-td.py <num_preds> <num_16> <num_32> <num_64>')
     exit(1)
 
 try:
     num_pred  = int(argv[1])
-    num_8bit  = int(argv[2])
-    num_16bit = int(argv[3])
-    num_32bit = int(argv[4])
-    num_64bit = int(argv[5])
+    num_16bit = int(argv[2])
+    num_32bit = int(argv[3])
+    num_64bit = int(argv[4])
 except:
     print('ERROR: Invalid integer parameter')
     exit(1)
@@ -61,11 +60,6 @@
 for r in range(0, num_pred):
     td_file.write('def P%d : PTXReg<"p%d">;\n' % (r, r))
 
-# Print 8-bit registers
-td_file.write('\n///===- 8-Bit Registers --------------------------------------------------===//\n\n')
-for r in range(0, num_8bit):
-    td_file.write('def RQ%d : PTXReg<"rq%d">;\n' % (r, r))
-
 # Print 16-bit registers
 td_file.write('\n///===- 16-Bit Registers --------------------------------------------------===//\n\n')
 for r in range(0, num_16bit):
@@ -92,7 +86,6 @@
 # Print register classes
 
 td_file.write('def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%%u", 0, %d)>;\n' % (num_pred-1))
-td_file.write('def RegI8  : RegisterClass<"PTX", [i8],  8, (sequence "RQ%%u", 0, %d)>;\n' % (num_8bit-1))
 td_file.write('def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%%u", 0, %d)>;\n' % (num_16bit-1))
 td_file.write('def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
 td_file.write('def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
@@ -108,20 +101,16 @@
 # Reserve 10% of the available registers for return values, and the other 90%
 # for parameters
 num_ret_pred    = int(0.1 * num_pred)
-num_ret_8bit    = int(0.1 * num_8bit)
 num_ret_16bit   = int(0.1 * num_16bit)
 num_ret_32bit   = int(0.1 * num_32bit)
 num_ret_64bit   = int(0.1 * num_64bit)
 num_param_pred  = num_pred - num_ret_pred
-num_param_8bit = num_8bit - num_ret_8bit
 num_param_16bit = num_16bit - num_ret_16bit
 num_param_32bit = num_32bit - num_ret_32bit
 num_param_64bit = num_64bit - num_ret_64bit
 
 param_regs_pred  = [('P%d' % (i+num_ret_pred)) for i in range(0, num_param_pred)]
 ret_regs_pred    = ['P%d' % i for i in range(0, num_ret_pred)]
-param_regs_8bit  = [('RQ%d' % (i+num_ret_8bit)) for i in range(0, num_param_8bit)]
-ret_regs_8bit    = ['RQ%d' % i for i in range(0, num_ret_8bit)]
 param_regs_16bit = [('RH%d' % (i+num_ret_16bit)) for i in range(0, num_param_16bit)]
 ret_regs_16bit   = ['RH%d' % i for i in range(0, num_ret_16bit)]
 param_regs_32bit = [('R%d' % (i+num_ret_32bit)) for i in range(0, num_param_32bit)]
@@ -131,8 +120,6 @@
 
 param_list_pred  = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_pred)
 ret_list_pred    = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_pred)
-param_list_8bit  = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_8bit)
-ret_list_8bit    = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_8bit)
 param_list_16bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_16bit)
 ret_list_16bit   = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_16bit)
 param_list_32bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_32bit)
@@ -157,7 +144,6 @@
 // PTX Formal Parameter Calling Convention
 def CC_PTX : CallingConv<[
   CCIfType<[i1],      CCAssignToReg<[%s]>>,
-  CCIfType<[i8],      CCAssignToReg<[%s]>>,
   CCIfType<[i16],     CCAssignToReg<[%s]>>,
   CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
   CCIfType<[i64,f64], CCAssignToReg<[%s]>>
@@ -166,13 +152,12 @@
 // PTX Return Value Calling Convention
 def RetCC_PTX : CallingConv<[
   CCIfType<[i1],      CCAssignToReg<[%s]>>,
-  CCIfType<[i8],      CCAssignToReg<[%s]>>,
   CCIfType<[i16],     CCAssignToReg<[%s]>>,
   CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
   CCIfType<[i64,f64], CCAssignToReg<[%s]>>
 ]>;
-''' % (param_list_pred, param_list_8bit, param_list_16bit, param_list_32bit, param_list_64bit,
-       ret_list_pred, ret_list_8bit, ret_list_16bit, ret_list_32bit, ret_list_64bit))
+''' % (param_list_pred, param_list_16bit, param_list_32bit, param_list_64bit,
+       ret_list_pred, ret_list_16bit, ret_list_32bit, ret_list_64bit))
 
 
 td_file.close()

Modified: llvm/trunk/test/CodeGen/PTX/cvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/cvt.ll?rev=133873&r1=133872&r2=133873&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/cvt.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/cvt.ll Sat Jun 25 13:16:28 2011
@@ -3,17 +3,6 @@
 ; preds 
 ; (note: we convert back to i32 to return)
 
-define ptx_device i32 @cvt_pred_i8(i8 %x, i1 %y) {
-; CHECK: setp.gt.b8 p[[P0:[0-9]+]], rq{{[0-9]+}}, 0
-; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
-; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
-; CHECK-NEXT: ret;
-	%a = trunc i8 %x to i1
-	%b = and i1 %a, %y
-	%c = zext i1 %b to i32
-	ret i32 %c
-}
-
 define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) {
 ; CHECK: setp.gt.b16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0
 ; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
@@ -69,43 +58,6 @@
 	ret i32 %c
 }
 
-; i8
-
-define ptx_device i8 @cvt_i8_preds(i1 %x) {
-; CHECK: selp.u8 rq{{[0-9]+}}, 1, 0, p{{[0-9]+}};
-; CHECK-NEXT: ret;
-	%a = zext i1 %x to i8
-	ret i8 %a
-}
-
-define ptx_device i8 @cvt_i8_i32(i32 %x) {
-; CHECK: cvt.u8.u32 rq{{[0-9]+}}, r{{[0-9]+}};
-; CHECK-NEXT: ret;
-	%a = trunc i32 %x to i8
-	ret i8 %a
-}
-
-define ptx_device i8 @cvt_i8_i64(i64 %x) {
-; CHECK: cvt.u8.u64 rq{{[0-9]+}}, rd{{[0-9]+}};
-; CHECK-NEXT: ret;
-	%a = trunc i64 %x to i8
-	ret i8 %a
-}
-
-define ptx_device i8 @cvt_i8_f32(float %x) {
-; CHECK: cvt.rzi.u8.f32 rq{{[0-9]+}}, r{{[0-9]+}};
-; CHECK-NEXT: ret;
-	%a = fptoui float %x to i8
-	ret i8 %a
-}
-
-define ptx_device i8 @cvt_i8_f64(double %x) {
-; CHECK: cvt.rzi.u8.f64 rq{{[0-9]+}}, rd{{[0-9]+}};
-; CHECK-NEXT: ret;
-	%a = fptoui double %x to i8
-	ret i8 %a
-}
-
 ; i16
 
 define ptx_device i16 @cvt_i16_preds(i1 %x) {
@@ -115,13 +67,6 @@
 	ret i16 %a
 }
 
-define ptx_device i16 @cvt_i16_i8(i8 %x) {
-; CHECK: cvt.u16.u8 rh{{[0-9]+}}, rq{{[0-9]+}};
-; CHECK-NEXT: ret;
-	%a = zext i8 %x to i16
-	ret i16 %a
-}
-
 define ptx_device i16 @cvt_i16_i32(i32 %x) {
 ; CHECK: cvt.u16.u32 rh{{[0-9]+}}, r{{[0-9]+}};
 ; CHECK-NEXT: ret;
@@ -159,13 +104,6 @@
 	ret i32 %a
 }
 
-define ptx_device i32 @cvt_i32_i8(i8 %x) {
-; CHECK: cvt.u32.u8 r{{[0-9]+}}, rq{{[0-9]+}};
-; CHECK-NEXT: ret;
-	%a = zext i8 %x to i32
-	ret i32 %a
-}
-
 define ptx_device i32 @cvt_i32_i16(i16 %x) {
 ; CHECK: cvt.u32.u16 r{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
@@ -203,13 +141,6 @@
 	ret i64 %a
 }
 
-define ptx_device i64 @cvt_i64_i8(i8 %x) {
-; CHECK: cvt.u64.u8 rd{{[0-9]+}}, rq{{[0-9]+}};
-; CHECK-NEXT: ret;
-	%a = zext i8 %x to i64
-	ret i64 %a
-}
-
 define ptx_device i64 @cvt_i64_i16(i16 %x) {
 ; CHECK: cvt.u64.u16 rd{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
@@ -247,13 +178,6 @@
 	ret float %a
 }
 
-define ptx_device float @cvt_f32_i8(i8 %x) {
-; CHECK: cvt.rn.f32.u8 r{{[0-9]+}}, rq{{[0-9]+}};
-; CHECK-NEXT: ret;
-	%a = uitofp i8 %x to float
-	ret float %a
-}
-
 define ptx_device float @cvt_f32_i16(i16 %x) {
 ; CHECK: cvt.rn.f32.u16 r{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;
@@ -291,13 +215,6 @@
 	ret double %a
 }
 
-define ptx_device double @cvt_f64_i8(i8 %x) {
-; CHECK: cvt.rn.f64.u8 rd{{[0-9]+}}, rq{{[0-9]+}};
-; CHECK-NEXT: ret;
-	%a = uitofp i8 %x to double
-	ret double %a
-}
-
 define ptx_device double @cvt_f64_i16(i16 %x) {
 ; CHECK: cvt.rn.f64.u16 rd{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK-NEXT: ret;

Modified: llvm/trunk/test/CodeGen/PTX/ld.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/ld.ll?rev=133873&r1=133872&r2=133873&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/ld.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/ld.ll Sat Jun 25 13:16:28 2011
@@ -1,17 +1,5 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
-;CHECK: .extern .global .b8 array_i8[10];
- at array_i8 = external global [10 x i8]
-
-;CHECK: .extern .const .b8 array_constant_i8[10];
- at array_constant_i8 = external addrspace(1) constant [10 x i8]
-
-;CHECK: .extern .local .b8 array_local_i8[10];
- at array_local_i8 = external addrspace(2) global [10 x i8]
-
-;CHECK: .extern .shared .b8 array_shared_i8[10];
- at array_shared_i8 = external addrspace(4) global [10 x i8]
-
 ;CHECK: .extern .global .b8 array_i16[20];
 @array_i16 = external global [10 x i16]
 
@@ -72,13 +60,6 @@
 ;CHECK: .extern .shared .b8 array_shared_double[80];
 @array_shared_double = external addrspace(4) global [10 x double]
 
-define ptx_device i8 @t1_u8(i8* %p) {
-entry:
-;CHECK: ld.global.u8 rq{{[0-9]+}}, [r{{[0-9]+}}];
-;CHECK-NEXT: ret;
-  %x = load i8* %p
-  ret i8 %x
-}
 
 define ptx_device i16 @t1_u16(i16* %p) {
 entry:
@@ -120,15 +101,6 @@
   ret double %x
 }
 
-define ptx_device i8 @t2_u8(i8* %p) {
-entry:
-;CHECK: ld.global.u8 rq{{[0-9]+}}, [r{{[0-9]+}}+1];
-;CHECK-NEXT: ret;
-  %i = getelementptr i8* %p, i32 1
-  %x = load i8* %i
-  ret i8 %x
-}
-
 define ptx_device i16 @t2_u16(i16* %p) {
 entry:
 ;CHECK: ld.global.u16 rh{{[0-9]+}}, [r{{[0-9]+}}+2];
@@ -174,15 +146,6 @@
   ret double %x
 }
 
-define ptx_device i8 @t3_u8(i8* %p, i32 %q) {
-entry:
-;CHECK: add.u32 r[[R0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
-;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]];
-  %i = getelementptr i8* %p, i32 %q
-  %x = load i8* %i
-  ret i8 %x
-}
-
 define ptx_device i16 @t3_u16(i16* %p, i32 %q) {
 entry:
 ;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 1;
@@ -233,16 +196,6 @@
   ret double %x
 }
 
-define ptx_device i8 @t4_global_u8() {
-entry:
-;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
-;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]];
-;CHECK-NEXT: ret;
-  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 0
-  %x = load i8* %i
-  ret i8 %x
-}
-
 define ptx_device i16 @t4_global_u16() {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
@@ -343,16 +296,6 @@
   ret double %x
 }
 
-define ptx_device i8 @t4_local_u8() {
-entry:
-;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i8;
-;CHECK-NEXT: ld.local.u8 rq{{[0-9]+}}, [r[[R0]]];
-;CHECK-NEXT: ret;
-  %i = getelementptr [10 x i8] addrspace(2)* @array_local_i8, i32 0, i32 0
-  %x = load i8 addrspace(2)* %i
-  ret i8 %x
-}
-
 define ptx_device i16 @t4_local_u16() {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i16;
@@ -403,16 +346,6 @@
   ret double %x
 }
 
-define ptx_device i8 @t4_shared_u8() {
-entry:
-;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i8;
-;CHECK-NEXT: ld.shared.u8 rq{{[0-9]+}}, [r[[R0]]];
-;CHECK-NEXT: ret;
-  %i = getelementptr [10 x i8] addrspace(4)* @array_shared_i8, i32 0, i32 0
-  %x = load i8 addrspace(4)* %i
-  ret i8 %x
-}
-
 define ptx_device i16 @t4_shared_u16() {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i16;
@@ -463,16 +396,6 @@
   ret double %x
 }
 
-define ptx_device i8 @t5_u8() {
-entry:
-;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
-;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]+1];
-;CHECK-NEXT: ret;
-  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 1
-  %x = load i8* %i
-  ret i8 %x
-}
-
 define ptx_device i16 @t5_u16() {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;

Modified: llvm/trunk/test/CodeGen/PTX/mov.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mov.ll?rev=133873&r1=133872&r2=133873&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/mov.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/mov.ll Sat Jun 25 13:16:28 2011
@@ -1,11 +1,5 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
-define ptx_device i8 @t1_u8() {
-; CHECK: mov.u8 rq{{[0-9]+}}, 0;
-; CHECK: ret;
-	ret i8 0
-}
-
 define ptx_device i16 @t1_u16() {
 ; CHECK: mov.u16 rh{{[0-9]+}}, 0;
 ; CHECK: ret;
@@ -36,12 +30,6 @@
 	ret double 0.0
 }
 
-define ptx_device i8 @t2_u8(i8 %x) {
-; CHECK: mov.u8 rq{{[0-9]+}}, rq{{[0-9]+}};
-; CHECK: ret;
-	ret i8 %x
-}
-
 define ptx_device i16 @t2_u16(i16 %x) {
 ; CHECK: mov.u16 rh{{[0-9]+}}, rh{{[0-9]+}};
 ; CHECK: ret;

Modified: llvm/trunk/test/CodeGen/PTX/st.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/st.ll?rev=133873&r1=133872&r2=133873&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/st.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/st.ll Sat Jun 25 13:16:28 2011
@@ -1,17 +1,5 @@
 ; RUN: llc < %s -march=ptx32 | FileCheck %s
 
-;CHECK: .extern .global .b8 array_i8[10];
- at array_i8 = external global [10 x i8]
-
-;CHECK: .extern .const .b8 array_constant_i8[10];
- at array_constant_i8 = external addrspace(1) constant [10 x i8]
-
-;CHECK: .extern .local .b8 array_local_i8[10];
- at array_local_i8 = external addrspace(2) global [10 x i8]
-
-;CHECK: .extern .shared .b8 array_shared_i8[10];
- at array_shared_i8 = external addrspace(4) global [10 x i8]
-
 ;CHECK: .extern .global .b8 array_i16[20];
 @array_i16 = external global [10 x i16]
 
@@ -72,13 +60,6 @@
 ;CHECK: .extern .shared .b8 array_shared_double[80];
 @array_shared_double = external addrspace(4) global [10 x double]
 
-define ptx_device void @t1_u8(i8* %p, i8 %x) {
-entry:
-;CHECK: st.global.u8 [r{{[0-9]+}}], rq{{[0-9]+}};
-;CHECK-NEXT: ret;
-  store i8 %x, i8* %p
-  ret void
-}
 
 define ptx_device void @t1_u16(i16* %p, i16 %x) {
 entry:
@@ -120,15 +101,6 @@
   ret void
 }
 
-define ptx_device void @t2_u8(i8* %p, i8 %x) {
-entry:
-;CHECK: st.global.u8 [r{{[0-9]+}}+1], rq{{[0-9]+}};
-;CHECK-NEXT: ret;
-  %i = getelementptr i8* %p, i32 1
-  store i8 %x, i8* %i
-  ret void
-}
-
 define ptx_device void @t2_u16(i16* %p, i16 %x) {
 entry:
 ;CHECK: st.global.u16 [r{{[0-9]+}}+2], rh{{[0-9]+}};
@@ -174,16 +146,6 @@
   ret void
 }
 
-define ptx_device void @t3_u8(i8* %p, i32 %q, i8 %x) {
-entry:
-;CHECK: add.u32 r[[R0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
-;CHECK-NEXT: st.global.u8 [r[[R0]]], rq{{[0-9]+}};
-;CHECK-NEXT: ret;
-  %i = getelementptr i8* %p, i32 %q
-  store i8 %x, i8* %i
-  ret void
-}
-
 define ptx_device void @t3_u16(i16* %p, i32 %q, i16 %x) {
 entry:
 ;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 1;
@@ -239,16 +201,6 @@
   ret void
 }
 
-define ptx_device void @t4_global_u8(i8 %x) {
-entry:
-;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
-;CHECK-NEXT: st.global.u8 [r[[R0]]], rq{{[0-9]+}};
-;CHECK-NEXT: ret;
-  %i = getelementptr [10 x i8]* @array_i8, i8 0, i8 0
-  store i8 %x, i8* %i
-  ret void
-}
-
 define ptx_device void @t4_global_u16(i16 %x) {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
@@ -299,16 +251,6 @@
   ret void
 }
 
-define ptx_device void @t4_local_u8(i8 %x) {
-entry:
-;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i8;
-;CHECK-NEXT: st.local.u8 [r[[R0]]], rq{{[0-9]+}};
-;CHECK-NEXT: ret;
-  %i = getelementptr [10 x i8] addrspace(2)* @array_local_i8, i32 0, i32 0
-  store i8 %x, i8 addrspace(2)* %i
-  ret void
-}
-
 define ptx_device void @t4_local_u16(i16 %x) {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i16;
@@ -359,16 +301,6 @@
   ret void
 }
 
-define ptx_device void @t4_shared_u8(i8 %x) {
-entry:
-;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i8;
-;CHECK-NEXT: st.shared.u8 [r[[R0]]], rq{{[0-9]+}};
-;CHECK-NEXT: ret;
-  %i = getelementptr [10 x i8] addrspace(4)* @array_shared_i8, i32 0, i32 0
-  store i8 %x, i8 addrspace(4)* %i
-  ret void
-}
-
 define ptx_device void @t4_shared_u16(i16 %x) {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i16;
@@ -419,16 +351,6 @@
   ret void
 }
 
-define ptx_device void @t5_u8(i8 %x) {
-entry:
-;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
-;CHECK-NEXT: st.global.u8 [r[[R0]]+1], rq{{[0-9]+}};
-;CHECK-NEXT: ret;
-  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 1
-  store i8 %x, i8* %i
-  ret void
-}
-
 define ptx_device void @t5_u16(i16 %x) {
 entry:
 ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;



From mcrosier at apple.com  Sat Jun 25 13:49:41 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Sat, 25 Jun 2011 11:49:41 -0700
Subject: [llvm-commits] [llvm] r133873 - in /llvm/trunk:
 lib/Target/PTX/PTXAsmPrinter.cpp lib/Target/PTX/PTXCallingConv.td
 lib/Target/PTX/PTXISelLowering.cpp lib/Target/PTX/PTXInstrInfo.cpp
 lib/Target/PTX/PTXInstrInfo.td lib/Target/PTX/PTXRegisterInfo.td
 lib/Target/PTX/generate-register-td.py test/CodeGen/PTX/cvt.ll
 test/CodeGen/PTX/ld.ll test/CodeGen/PTX/mov.ll test/CodeGen/PTX/st.ll
In-Reply-To: <20110625181629.0E99A2A6C12C@llvm.org>
References: <20110625181629.0E99A2A6C12C@llvm.org>
Message-ID: <C11B2CF8-13AE-4A9A-ACCA-E227BF5E6315@apple.com>

Dan,
It looks like cvt.ll and step.ll are failing.  Can you please take a look when you have a moment?

 Regards,
  Chad

******************** TEST 'LLVM :: CodeGen/PTX/cvt.ll' FAILED ********************
Script:
--
/home/baldrick/osuosl/slave/llvm-x86_64/llvm/Debug+Asserts/bin/llc < /home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/cvt.ll -march=ptx32 | /home/baldrick/osuosl/slave/llvm-x86_64/llvm/Debug+Asserts/bin/FileCheck /home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/cvt.ll
--
Exit Code: 1
Command Output (stderr):
--
/home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/cvt.ll:7:10: error: expected string not found in input
; CHECK: setp.gt.b16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0
         ^
<stdin>:1:2: note: scanning from here
 .version 2.0
 ^
<stdin>:9:2: note: possible intended match here
 setp.gt.u16 p0, rh12, 0;
 ^
--

********************
******************** TEST 'LLVM :: CodeGen/PTX/setp.ll' FAILED ********************
Script:
--
/home/baldrick/osuosl/slave/llvm-x86_64/llvm/Debug+Asserts/bin/llc < /home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/setp.ll -march=ptx32 | /home/baldrick/osuosl/slave/llvm-x86_64/llvm/Debug+Asserts/bin/FileCheck /home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/setp.ll
--
Exit Code: 1
Command Output (stderr):
--
/home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/setp.ll:196:10: error: expected string not found in input
; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
         ^
<stdin>:193:1: note: scanning from here
}
^
<stdin>:199:2: note: possible intended match here
 setp.gt.u32 p0, r14, 0;
 ^
--

********************



On Jun 25, 2011, at 11:16 AM, Dan Bailey wrote:

> Author: drb
> Date: Sat Jun 25 13:16:28 2011
> New Revision: 133873
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=133873&view=rev
> Log:
> PTX: Reverting implementation of i8.
> 
> The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is
> not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support
> boolean values.
> 
> 
> Modified:
>    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
>    llvm/trunk/lib/Target/PTX/PTXCallingConv.td
>    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
>    llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
>    llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
>    llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td
>    llvm/trunk/lib/Target/PTX/generate-register-td.py
>    llvm/trunk/test/CodeGen/PTX/cvt.ll
>    llvm/trunk/test/CodeGen/PTX/ld.ll
>    llvm/trunk/test/CodeGen/PTX/mov.ll
>    llvm/trunk/test/CodeGen/PTX/st.ll
> 
> Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133873&r1=133872&r2=133873&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Sat Jun 25 13:16:28 2011
> @@ -92,7 +92,6 @@
> #define TEST_REGCLS(cls, clsstr)                \
>   if (PTX::cls ## RegisterClass->contains(RegNo)) return # clsstr;
>   TEST_REGCLS(RegPred, pred);
> -  TEST_REGCLS(RegI8,  b8);
>   TEST_REGCLS(RegI16, b16);
>   TEST_REGCLS(RegI32, b32);
>   TEST_REGCLS(RegI64, b64);
> @@ -125,7 +124,6 @@
>       case Type::IntegerTyID:
>         switch (type->getPrimitiveSizeInBits()) {
>           default: llvm_unreachable("Unknown integer bit-width");
> -          case 8:  return ".u8";
>           case 16: return ".u16";
>           case 32: return ".u32";
>           case 64: return ".u64";
> 
> Modified: llvm/trunk/lib/Target/PTX/PTXCallingConv.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXCallingConv.td?rev=133873&r1=133872&r2=133873&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/PTXCallingConv.td (original)
> +++ llvm/trunk/lib/Target/PTX/PTXCallingConv.td Sat Jun 25 13:16:28 2011
> @@ -15,7 +15,6 @@
> // PTX Formal Parameter Calling Convention
> def CC_PTX : CallingConv<[
>   CCIfType<[i1],      CCAssignToReg<[P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, P36, P37, P38, P39, P40, P41, P42, P43, P44, P45, P46, P47, P48, P49, P50, P51, P52, P53, P54, P55, P56, P57, P58, P59, P60, P61, P62, P63, P64, P65, P66, P67, P68, P69, P70, P71, P72, P73, P74, P75, P76, P77, P78, P79, P80, P81, P82, P83, P84, P85, P86, P87, P88, P89, P90, P91, P92, P93, P94, P95, P96, P97, P98, P99, P100, P101, P102, P103, P104, P105, P106, P107, P108, P109, P110, P111, P112, P113, P114, P115, P116, P117, P118, P119, P120, P121, P122, P123, P124, P125, P126, P127]>>,
> -  CCIfType<[i8],      CCAssignToReg<[RQ12, RQ13, RQ14, RQ15, RQ16, RQ17, RQ18, RQ19, RQ20, RQ21, RQ22, RQ23, RQ24, RQ25, RQ26, RQ27, RQ28, RQ29, RQ30, RQ31, RQ32, RQ33, RQ34, RQ35, RQ36, RQ37, RQ38, RQ39, RQ40, RQ41, RQ42, RQ43, RQ44, RQ45, RQ46, RQ47, RQ48, RQ49, RQ50, RQ51, RQ52, RQ53, RQ54, RQ55, RQ56, RQ57, RQ58, RQ59, RQ60, RQ61, RQ62, RQ63, RQ64, RQ65, RQ66, RQ67, RQ68, RQ69, RQ70, RQ71, RQ72, RQ73, RQ74, RQ75, RQ76, RQ77, RQ78, RQ79, RQ80, RQ81, RQ82, RQ83, RQ84, RQ85, RQ86, RQ87, RQ88, RQ89, RQ90, RQ91, RQ92, RQ93, RQ94, RQ95, RQ96, RQ97, RQ98, RQ99, RQ100, RQ101, RQ102, RQ103, RQ104, RQ105, RQ106, RQ107, RQ108, RQ109, RQ110, RQ111, RQ112, RQ113, RQ114, RQ115, RQ116, RQ117, RQ118, RQ119, RQ120, RQ121, RQ122, RQ123, RQ124, RQ125, RQ126, RQ127]>>,
>   CCIfType<[i16],     CCAssignToReg<[RH12, RH13, RH14, RH15, RH16, RH17, RH18, RH19, RH20, RH21, RH22, RH23, RH24, RH25, RH26, RH27, RH28, RH29, RH30, RH31, RH32, RH33, RH34, RH35, RH36, RH37, RH38, RH39, RH40, RH41, RH42, RH43, RH44, RH45, RH46, RH47, RH48, RH49, RH50, RH51, RH52, RH53, RH54, RH55, RH56, RH57, RH58, RH59, RH60, RH61, RH62, RH63, RH64, RH65, RH66, RH67, RH68, RH69, RH70, RH71, RH72, RH73, RH74, RH75, RH76, RH77, RH78, RH79, RH80, RH81, RH82, RH83, RH84, RH85, RH86, RH87, RH88, RH89, RH90, RH91, RH92, RH93, RH94, RH95, RH96, RH97, RH98, RH99, RH100, RH101, RH102, RH103, RH104, RH105, RH106, RH107, RH108, RH109, RH110, RH111, RH112, RH113, RH114, RH115, RH116, RH117, RH118, RH119, RH120, RH121, RH122, RH123, RH124, RH125, RH126, RH127]>>,
>   CCIfType<[i32,f32], CCAssignToReg<[R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127]>>,
>   CCIfType<[i64,f64], CCAssignToReg<[RD12, RD13, RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26, RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35, RD36, RD37, RD38, RD39, RD40, RD41, RD42, RD43, RD44, RD45, RD46, RD47, RD48, RD49, RD50, RD51, RD52, RD53, RD54, RD55, RD56, RD57, RD58, RD59, RD60, RD61, RD62, RD63, RD64, RD65, RD66, RD67, RD68, RD69, RD70, RD71, RD72, RD73, RD74, RD75, RD76, RD77, RD78, RD79, RD80, RD81, RD82, RD83, RD84, RD85, RD86, RD87, RD88, RD89, RD90, RD91, RD92, RD93, RD94, RD95, RD96, RD97, RD98, RD99, RD100, RD101, RD102, RD103, RD104, RD105, RD106, RD107, RD108, RD109, RD110, RD111, RD112, RD113, RD114, RD115, RD116, RD117, RD118, RD119, RD120, RD121, RD122, RD123, RD124, RD125, RD126, RD127]>>
> @@ -24,7 +23,6 @@
> // PTX Return Value Calling Convention
> def RetCC_PTX : CallingConv<[
>   CCIfType<[i1],      CCAssignToReg<[P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11]>>,
> -  CCIfType<[i8],      CCAssignToReg<[RQ0, RQ1, RQ2, RQ3, RQ4, RQ5, RQ6, RQ7, RQ8, RQ9, RQ10, RQ11]>>,
>   CCIfType<[i16],     CCAssignToReg<[RH0, RH1, RH2, RH3, RH4, RH5, RH6, RH7, RH8, RH9, RH10, RH11]>>,
>   CCIfType<[i32,f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11]>>,
>   CCIfType<[i64,f64], CCAssignToReg<[RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11]>>
> 
> Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=133873&r1=133872&r2=133873&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Sat Jun 25 13:16:28 2011
> @@ -40,7 +40,6 @@
>   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
>   // Set up the register classes.
>   addRegisterClass(MVT::i1,  PTX::RegPredRegisterClass);
> -  addRegisterClass(MVT::i8,  PTX::RegI8RegisterClass);
>   addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
>   addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
>   addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
> @@ -48,48 +47,59 @@
>   addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
> 
>   setBooleanContents(ZeroOrOneBooleanContent);
> -
> -  setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
> -
> -  setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
> -  setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
> -  
> -  // Promote i1 type
> -  setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
> -  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
> -  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
> +  setMinFunctionAlignment(2);
> 
> -  setTruncStoreAction(MVT::i8, MVT::i1, Promote);
> +  ////////////////////////////////////
> +  /////////// Expansion //////////////
> +  ////////////////////////////////////
> 
> -  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
> +  // (any/zero/sign) extload => load + (any/zero/sign) extend
> 
> -  // Turn i16 (z)extload into load + (z)extend
>   setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
>   setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
>   setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
> -
> -  // Turn f32 extload into load + fextend
> -  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
> -
> -  // Turn f64 truncstore into trunc + store.
> -  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
> -
> -  // Customize translation of memory addresses
> -  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
> -  setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
> -
> -  // Expand BR_CC into BRCOND
> +  
> +  // f32 extload => load + fextend
> +  
> +  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);  
> +  
> +  // f64 truncstore => trunc + store
> +  
> +  setTruncStoreAction(MVT::f64, MVT::f32, Expand); 
> +  
> +  // sign_extend_inreg => sign_extend
> +  
> +  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
> +  
> +  // br_cc => brcond
> +  
>   setOperationAction(ISD::BR_CC, MVT::Other, Expand);
> 
> -  // Expand SELECT_CC into SETCC
> +  // select_cc => setcc
> +  
>   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
>   setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
>   setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
> -
> -  // need to lower SETCC of RegPred into bitwise logic
> +  
> +  ////////////////////////////////////
> +  //////////// Legal /////////////////
> +  ////////////////////////////////////
> +  
> +  setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
> +  setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
> +  
> +  ////////////////////////////////////
> +  //////////// Custom ////////////////
> +  ////////////////////////////////////
> +  
> +  // customise setcc to use bitwise logic if possible
> +  
>   setOperationAction(ISD::SETCC, MVT::i1, Custom);
> 
> -  setMinFunctionAlignment(2);
> +  // customize translation of memory addresses
> +  
> +  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
> +  setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
> 
>   // Compute derived properties from the register classes
>   computeRegisterProperties();
> @@ -187,7 +197,6 @@
>   bool operator==(MVT::SimpleValueType _VT) const { return VT == _VT; }
> } argmap[] = {
>   argmap_entry(MVT::i1,  PTX::RegPredRegisterClass),
> -  argmap_entry(MVT::i8,  PTX::RegI8RegisterClass),
>   argmap_entry(MVT::i16, PTX::RegI16RegisterClass),
>   argmap_entry(MVT::i32, PTX::RegI32RegisterClass),
>   argmap_entry(MVT::i64, PTX::RegI64RegisterClass),
> @@ -264,9 +273,6 @@
>       if (RegVT == MVT::i1) {
>         TRC = PTX::RegPredRegisterClass;
>       }
> -      else if (RegVT == MVT::i8) {
> -        TRC = PTX::RegI8RegisterClass;
> -      }
>       else if (RegVT == MVT::i16) {
>         TRC = PTX::RegI16RegisterClass;
>       }
> 
> Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=133873&r1=133872&r2=133873&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Sat Jun 25 13:16:28 2011
> @@ -33,7 +33,6 @@
>   const TargetRegisterClass *cls;
>   const int opcode;
> } map[] = {
> -  { &PTX::RegI8RegClass,  PTX::MOVU8rr },
>   { &PTX::RegI16RegClass, PTX::MOVU16rr },
>   { &PTX::RegI32RegClass, PTX::MOVU32rr },
>   { &PTX::RegI64RegClass, PTX::MOVU64rr },
> @@ -303,9 +302,7 @@
>   int OpCode;
> 
>   // Select the appropriate opcode based on the register class
> -  if (RC == PTX::RegI8RegisterClass) {
> -    OpCode = PTX::STACKSTOREI8;
> -  } else if (RC == PTX::RegI16RegisterClass) {
> +  if (RC == PTX::RegI16RegisterClass) {
>     OpCode = PTX::STACKSTOREI16;
>   }  else if (RC == PTX::RegI32RegisterClass) {
>     OpCode = PTX::STACKSTOREI32;
> @@ -340,9 +337,7 @@
>   int OpCode;
> 
>   // Select the appropriate opcode based on the register class
> -  if (RC == PTX::RegI8RegisterClass) {
> -    OpCode = PTX::STACKLOADI8;
> -  } else if (RC == PTX::RegI16RegisterClass) {
> +  if (RC == PTX::RegI16RegisterClass) {
>     OpCode = PTX::STACKLOADI16;
>   } else if (RC == PTX::RegI32RegisterClass) {
>     OpCode = PTX::STACKLOADI32;
> 
> Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=133873&r1=133872&r2=133873&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
> +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Sat Jun 25 13:16:28 2011
> @@ -537,7 +537,6 @@
> }
> 
> multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
> -  defm u8  : PTX_LD<opstr, ".u8",  RegI8,  pat_load>;
>   defm u16 : PTX_LD<opstr, ".u16", RegI16, pat_load>;
>   defm u32 : PTX_LD<opstr, ".u32", RegI32, pat_load>;
>   defm u64 : PTX_LD<opstr, ".u64", RegI64, pat_load>;
> @@ -573,7 +572,6 @@
> }
> 
> multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
> -  defm u8  : PTX_ST<opstr, ".u8",  RegI8,  pat_store>;
>   defm u16 : PTX_ST<opstr, ".u16", RegI16, pat_store>;
>   defm u32 : PTX_ST<opstr, ".u32", RegI32, pat_store>;
>   defm u64 : PTX_ST<opstr, ".u64", RegI64, pat_store>;
> @@ -785,27 +783,22 @@
> let neverHasSideEffects = 1 in {
>   def MOVPREDrr
>     : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
> -  def MOVU8rr
> -    : InstPTX<(outs RegI8:$d),   (ins RegI8:$a),   "mov.u8\t$d, $a",  []>;
>   def MOVU16rr
> -    : InstPTX<(outs RegI16:$d),  (ins RegI16:$a),  "mov.u16\t$d, $a", []>;
> +    : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
>   def MOVU32rr
> -    : InstPTX<(outs RegI32:$d),  (ins RegI32:$a),  "mov.u32\t$d, $a", []>;
> +    : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
>   def MOVU64rr
> -    : InstPTX<(outs RegI64:$d),  (ins RegI64:$a),  "mov.u64\t$d, $a", []>;
> +    : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
>   def MOVF32rr
> -    : InstPTX<(outs RegF32:$d),  (ins RegF32:$a),  "mov.f32\t$d, $a", []>;
> +    : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
>   def MOVF64rr
> -    : InstPTX<(outs RegF64:$d),  (ins RegF64:$a),  "mov.f64\t$d, $a", []>;
> +    : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
> }
> 
> let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
>   def MOVPREDri
>     : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
>               [(set RegPred:$d, imm:$a)]>;
> -  def MOVU8ri
> -    : InstPTX<(outs RegI8:$d),  (ins i8imm:$a),  "mov.u8\t$d, $a",
> -              [(set RegI8:$d, imm:$a)]>;
>   def MOVU16ri
>     : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
>               [(set RegI16:$d, imm:$a)]>;
> @@ -845,9 +838,6 @@
>   def LDpiPred : InstPTX<(outs RegPred:$d), (ins MEMpi:$a),
>                          "ld.param.pred\t$d, [$a]",
>                          [(set RegPred:$d, (PTXloadparam timm:$a))]>;
> -  def LDpiU8   : InstPTX<(outs RegI8:$d), (ins MEMpi:$a),
> -                         "ld.param.u8\t$d, [$a]",
> -                         [(set RegI8:$d,  (PTXloadparam timm:$a))]>;
>   def LDpiU16  : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
>                          "ld.param.u16\t$d, [$a]",
>                          [(set RegI16:$d, (PTXloadparam timm:$a))]>;
> @@ -867,9 +857,6 @@
>   def STpiPred : InstPTX<(outs), (ins MEMret:$d, RegPred:$a),
>                          "st.param.pred\t[$d], $a",
>                          [(PTXstoreparam timm:$d, RegPred:$a)]>;
> -  def STpiU8   : InstPTX<(outs), (ins MEMret:$d, RegI8:$a),
> -                         "st.param.u8\t[$d], $a",
> -                         [(PTXstoreparam timm:$d, RegI8:$a)]>;
>   def STpiU16  : InstPTX<(outs), (ins MEMret:$d, RegI16:$a),
>                          "st.param.u16\t[$d], $a",
>                          [(PTXstoreparam timm:$d, RegI16:$a)]>;
> @@ -900,62 +887,34 @@
> // PTX does not directly support converting to a predicate type, so we fake it
> // by performing a greater-than test between the value and zero.  This follows
> // the C convention that any non-zero value is equivalent to 'true'.
> -def CVT_pred_u8
> -  : InstPTX<(outs RegPred:$d), (ins RegI8:$a), "setp.gt.b8\t$d, $a, 0",
> -            [(set RegPred:$d, (trunc RegI8:$a))]>;
> -
> def CVT_pred_u16
> -  : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.b16\t$d, $a, 0",
> +  : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.u16\t$d, $a, 0",
>             [(set RegPred:$d, (trunc RegI16:$a))]>;
> 
> def CVT_pred_u32
> -  : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.b32\t$d, $a, 0",
> +  : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.u32\t$d, $a, 0",
>             [(set RegPred:$d, (trunc RegI32:$a))]>;
> 
> def CVT_pred_u64
> -  : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.b64\t$d, $a, 0",
> +  : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.u64\t$d, $a, 0",
>             [(set RegPred:$d, (trunc RegI64:$a))]>;
> 
> def CVT_pred_f32
> -  : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.b32\t$d, $a, 0",
> +  : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.f32\t$d, $a, 0",
>             [(set RegPred:$d, (fp_to_uint RegF32:$a))]>;
> 
> def CVT_pred_f64
> -  : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.b64\t$d, $a, 0",
> +  : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.f64\t$d, $a, 0",
>             [(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
> 
> -// Conversion to u8
> -// PTX does not directly support converting a predicate to a value, so we
> -// use a select instruction to select either 0 or 1 (integer or fp) based
> -// on the truth value of the predicate.
> -def CVT_u8_pred
> -  : InstPTX<(outs RegI8:$d), (ins RegPred:$a), "selp.u8\t$d, 1, 0, $a",
> -            [(set RegI8:$d, (zext RegPred:$a))]>;
> -
> -def CVT_u8_preds
> -  : InstPTX<(outs RegI8:$d), (ins RegPred:$a), "selp.u8\t$d, 1, 0, $a",
> -            [(set RegI8:$d, (sext RegPred:$a))]>;
> -
> -def CVT_u8_u32
> -  : InstPTX<(outs RegI8:$d), (ins RegI32:$a), "cvt.u8.u32\t$d, $a",
> -            [(set RegI8:$d, (trunc RegI32:$a))]>;
> -
> -def CVT_u8_u64
> -  : InstPTX<(outs RegI8:$d), (ins RegI64:$a), "cvt.u8.u64\t$d, $a",
> -            [(set RegI8:$d, (trunc RegI64:$a))]>;
> -
> -def CVT_u8_f32
> -  : InstPTX<(outs RegI8:$d), (ins RegF32:$a), "cvt.rzi.u8.f32\t$d, $a",
> -            [(set RegI8:$d, (fp_to_uint RegF32:$a))]>;
> -
> -def CVT_u8_f64
> -  : InstPTX<(outs RegI8:$d), (ins RegF64:$a), "cvt.rzi.u8.f64\t$d, $a",
> -            [(set RegI8:$d, (fp_to_uint RegF64:$a))]>;
> -
> // Conversion to u16
> // PTX does not directly support converting a predicate to a value, so we
> // use a select instruction to select either 0 or 1 (integer or fp) based
> // on the truth value of the predicate.
> +def CVT_u16_preda
> +  : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
> +            [(set RegI16:$d, (anyext RegPred:$a))]>;
> +
> def CVT_u16_pred
>   : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
>             [(set RegI16:$d, (zext RegPred:$a))]>;
> @@ -964,14 +923,6 @@
>   : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
>             [(set RegI16:$d, (sext RegPred:$a))]>;
> 
> -def CVT_u16_u8
> -  : InstPTX<(outs RegI16:$d), (ins RegI8:$a), "cvt.u16.u8\t$d, $a",
> -            [(set RegI16:$d, (zext RegI8:$a))]>;
> -
> -def CVT_u16_s8
> -  : InstPTX<(outs RegI16:$d), (ins RegI8:$a), "cvt.u16.s8\t$d, $a",
> -            [(set RegI16:$d, (sext RegI8:$a))]>;
> -
> def CVT_u16_u32
>   : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a",
>             [(set RegI16:$d, (trunc RegI32:$a))]>;
> @@ -994,9 +945,9 @@
>   : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
>             [(set RegI32:$d, (zext RegPred:$a))]>;
> 
> -def CVT_u32_u8
> -  : InstPTX<(outs RegI32:$d), (ins RegI8:$a), "cvt.u32.u8\t$d, $a",
> -            [(set RegI32:$d, (zext RegI8:$a))]>;
> +def CVT_u32_b16
> +  : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
> +            [(set RegI32:$d, (anyext RegI16:$a))]>;
> 
> def CVT_u32_u16
>   : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
> @@ -1006,10 +957,6 @@
>   : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
>             [(set RegI32:$d, (sext RegPred:$a))]>;
> 
> -def CVT_u32_s8
> -  : InstPTX<(outs RegI32:$d), (ins RegI8:$a), "cvt.u32.s8\t$d, $a",
> -            [(set RegI32:$d, (zext RegI8:$a))]>;
> -
> def CVT_u32_s16
>   : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.s16\t$d, $a",
>             [(set RegI32:$d, (sext RegI16:$a))]>;
> @@ -1032,30 +979,22 @@
>   : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
>             [(set RegI64:$d, (zext RegPred:$a))]>;
> 
> -def CVT_u64_u8
> -  : InstPTX<(outs RegI64:$d), (ins RegI8:$a), "cvt.u64.u8\t$d, $a",
> -            [(set RegI64:$d, (zext RegI8:$a))]>;
> -
> -def CVT_u64_u16
> -  : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
> -            [(set RegI64:$d, (zext RegI16:$a))]>;
> -
> -def CVT_u64_u32
> -  : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
> -            [(set RegI64:$d, (zext RegI32:$a))]>;
> -
> def CVT_u64_preds
>   : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
>             [(set RegI64:$d, (sext RegPred:$a))]>;
> 
> -def CVT_u64_s8
> -  : InstPTX<(outs RegI64:$d), (ins RegI8:$a), "cvt.u64.s8\t$d, $a",
> -            [(set RegI64:$d, (zext RegI8:$a))]>;
> +def CVT_u64_u16
> +  : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
> +            [(set RegI64:$d, (zext RegI16:$a))]>;
> 
> def CVT_u64_s16
>   : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.s16\t$d, $a",
>             [(set RegI64:$d, (sext RegI16:$a))]>;
> 
> +def CVT_u64_u32
> +  : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
> +            [(set RegI64:$d, (zext RegI32:$a))]>;
> +
> def CVT_u64_s32
>   : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.s32\t$d, $a",
>             [(set RegI64:$d, (sext RegI32:$a))]>;
> @@ -1075,10 +1014,6 @@
>             "selp.f32\t$d, 0F3F800000, 0F00000000, $a",  // 1.0
>             [(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
> 
> -def CVT_f32_u8
> -  : InstPTX<(outs RegF32:$d), (ins RegI8:$a), "cvt.rn.f32.u8\t$d, $a",
> -            [(set RegF32:$d, (uint_to_fp RegI8:$a))]>;
> -
> def CVT_f32_u16
>   : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a",
>             [(set RegF32:$d, (uint_to_fp RegI16:$a))]>;
> @@ -1102,10 +1037,6 @@
>             "selp.f64\t$d, 0D3F80000000000000, 0D0000000000000000, $a",  // 1.0
>             [(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
> 
> -def CVT_f64_u8
> -  : InstPTX<(outs RegF64:$d), (ins RegI8:$a), "cvt.rn.f64.u8\t$d, $a",
> -            [(set RegF64:$d, (uint_to_fp RegI8:$a))]>;
> -
> def CVT_f64_u16
>   : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a",
>             [(set RegF64:$d, (uint_to_fp RegI16:$a))]>;
> @@ -1144,8 +1075,6 @@
> 
> ///===- Spill Instructions ------------------------------------------------===//
> // Special instructions used for stack spilling
> -def STACKSTOREI8  : InstPTX<(outs), (ins i32imm:$d, RegI8:$a),
> -                            "mov.u8\ts$d, $a", []>;
> def STACKSTOREI16 : InstPTX<(outs), (ins i32imm:$d, RegI16:$a),
>                             "mov.u16\ts$d, $a", []>;
> def STACKSTOREI32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
> @@ -1157,8 +1086,6 @@
> def STACKSTOREF64 : InstPTX<(outs), (ins i32imm:$d, RegF64:$a),
>                             "mov.f64\ts$d, $a", []>;
> 
> -def STACKLOADI8  : InstPTX<(outs), (ins RegI8:$d, i32imm:$a),
> -                           "mov.u8\t$d, s$a", []>;
> def STACKLOADI16 : InstPTX<(outs), (ins RegI16:$d, i32imm:$a),
>                            "mov.u16\t$d, s$a", []>;
> def STACKLOADI32 : InstPTX<(outs), (ins RegI32:$d, i32imm:$a),
> 
> Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td?rev=133873&r1=133872&r2=133873&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td Sat Jun 25 13:16:28 2011
> @@ -151,137 +151,6 @@
> def P126 : PTXReg<"p126">;
> def P127 : PTXReg<"p127">;
> 
> -///===- 8-Bit Registers --------------------------------------------------===//
> -
> -def RQ0 : PTXReg<"rq0">;
> -def RQ1 : PTXReg<"rq1">;
> -def RQ2 : PTXReg<"rq2">;
> -def RQ3 : PTXReg<"rq3">;
> -def RQ4 : PTXReg<"rq4">;
> -def RQ5 : PTXReg<"rq5">;
> -def RQ6 : PTXReg<"rq6">;
> -def RQ7 : PTXReg<"rq7">;
> -def RQ8 : PTXReg<"rq8">;
> -def RQ9 : PTXReg<"rq9">;
> -def RQ10 : PTXReg<"rq10">;
> -def RQ11 : PTXReg<"rq11">;
> -def RQ12 : PTXReg<"rq12">;
> -def RQ13 : PTXReg<"rq13">;
> -def RQ14 : PTXReg<"rq14">;
> -def RQ15 : PTXReg<"rq15">;
> -def RQ16 : PTXReg<"rq16">;
> -def RQ17 : PTXReg<"rq17">;
> -def RQ18 : PTXReg<"rq18">;
> -def RQ19 : PTXReg<"rq19">;
> -def RQ20 : PTXReg<"rq20">;
> -def RQ21 : PTXReg<"rq21">;
> -def RQ22 : PTXReg<"rq22">;
> -def RQ23 : PTXReg<"rq23">;
> -def RQ24 : PTXReg<"rq24">;
> -def RQ25 : PTXReg<"rq25">;
> -def RQ26 : PTXReg<"rq26">;
> -def RQ27 : PTXReg<"rq27">;
> -def RQ28 : PTXReg<"rq28">;
> -def RQ29 : PTXReg<"rq29">;
> -def RQ30 : PTXReg<"rq30">;
> -def RQ31 : PTXReg<"rq31">;
> -def RQ32 : PTXReg<"rq32">;
> -def RQ33 : PTXReg<"rq33">;
> -def RQ34 : PTXReg<"rq34">;
> -def RQ35 : PTXReg<"rq35">;
> -def RQ36 : PTXReg<"rq36">;
> -def RQ37 : PTXReg<"rq37">;
> -def RQ38 : PTXReg<"rq38">;
> -def RQ39 : PTXReg<"rq39">;
> -def RQ40 : PTXReg<"rq40">;
> -def RQ41 : PTXReg<"rq41">;
> -def RQ42 : PTXReg<"rq42">;
> -def RQ43 : PTXReg<"rq43">;
> -def RQ44 : PTXReg<"rq44">;
> -def RQ45 : PTXReg<"rq45">;
> -def RQ46 : PTXReg<"rq46">;
> -def RQ47 : PTXReg<"rq47">;
> -def RQ48 : PTXReg<"rq48">;
> -def RQ49 : PTXReg<"rq49">;
> -def RQ50 : PTXReg<"rq50">;
> -def RQ51 : PTXReg<"rq51">;
> -def RQ52 : PTXReg<"rq52">;
> -def RQ53 : PTXReg<"rq53">;
> -def RQ54 : PTXReg<"rq54">;
> -def RQ55 : PTXReg<"rq55">;
> -def RQ56 : PTXReg<"rq56">;
> -def RQ57 : PTXReg<"rq57">;
> -def RQ58 : PTXReg<"rq58">;
> -def RQ59 : PTXReg<"rq59">;
> -def RQ60 : PTXReg<"rq60">;
> -def RQ61 : PTXReg<"rq61">;
> -def RQ62 : PTXReg<"rq62">;
> -def RQ63 : PTXReg<"rq63">;
> -def RQ64 : PTXReg<"rq64">;
> -def RQ65 : PTXReg<"rq65">;
> -def RQ66 : PTXReg<"rq66">;
> -def RQ67 : PTXReg<"rq67">;
> -def RQ68 : PTXReg<"rq68">;
> -def RQ69 : PTXReg<"rq69">;
> -def RQ70 : PTXReg<"rq70">;
> -def RQ71 : PTXReg<"rq71">;
> -def RQ72 : PTXReg<"rq72">;
> -def RQ73 : PTXReg<"rq73">;
> -def RQ74 : PTXReg<"rq74">;
> -def RQ75 : PTXReg<"rq75">;
> -def RQ76 : PTXReg<"rq76">;
> -def RQ77 : PTXReg<"rq77">;
> -def RQ78 : PTXReg<"rq78">;
> -def RQ79 : PTXReg<"rq79">;
> -def RQ80 : PTXReg<"rq80">;
> -def RQ81 : PTXReg<"rq81">;
> -def RQ82 : PTXReg<"rq82">;
> -def RQ83 : PTXReg<"rq83">;
> -def RQ84 : PTXReg<"rq84">;
> -def RQ85 : PTXReg<"rq85">;
> -def RQ86 : PTXReg<"rq86">;
> -def RQ87 : PTXReg<"rq87">;
> -def RQ88 : PTXReg<"rq88">;
> -def RQ89 : PTXReg<"rq89">;
> -def RQ90 : PTXReg<"rq90">;
> -def RQ91 : PTXReg<"rq91">;
> -def RQ92 : PTXReg<"rq92">;
> -def RQ93 : PTXReg<"rq93">;
> -def RQ94 : PTXReg<"rq94">;
> -def RQ95 : PTXReg<"rq95">;
> -def RQ96 : PTXReg<"rq96">;
> -def RQ97 : PTXReg<"rq97">;
> -def RQ98 : PTXReg<"rq98">;
> -def RQ99 : PTXReg<"rq99">;
> -def RQ100 : PTXReg<"rq100">;
> -def RQ101 : PTXReg<"rq101">;
> -def RQ102 : PTXReg<"rq102">;
> -def RQ103 : PTXReg<"rq103">;
> -def RQ104 : PTXReg<"rq104">;
> -def RQ105 : PTXReg<"rq105">;
> -def RQ106 : PTXReg<"rq106">;
> -def RQ107 : PTXReg<"rq107">;
> -def RQ108 : PTXReg<"rq108">;
> -def RQ109 : PTXReg<"rq109">;
> -def RQ110 : PTXReg<"rq110">;
> -def RQ111 : PTXReg<"rq111">;
> -def RQ112 : PTXReg<"rq112">;
> -def RQ113 : PTXReg<"rq113">;
> -def RQ114 : PTXReg<"rq114">;
> -def RQ115 : PTXReg<"rq115">;
> -def RQ116 : PTXReg<"rq116">;
> -def RQ117 : PTXReg<"rq117">;
> -def RQ118 : PTXReg<"rq118">;
> -def RQ119 : PTXReg<"rq119">;
> -def RQ120 : PTXReg<"rq120">;
> -def RQ121 : PTXReg<"rq121">;
> -def RQ122 : PTXReg<"rq122">;
> -def RQ123 : PTXReg<"rq123">;
> -def RQ124 : PTXReg<"rq124">;
> -def RQ125 : PTXReg<"rq125">;
> -def RQ126 : PTXReg<"rq126">;
> -def RQ127 : PTXReg<"rq127">;
> -
> ///===- 16-Bit Registers --------------------------------------------------===//
> 
> def RH0 : PTXReg<"rh0">;
> @@ -679,7 +548,6 @@
> //  Register classes
> //===----------------------------------------------------------------------===//
> def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%u", 0, 127)>;
> -def RegI8  : RegisterClass<"PTX", [i8],  8, (sequence "RQ%u", 0, 127)>;
> def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%u", 0, 127)>;
> def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%u", 0, 127)>;
> def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%u", 0, 127)>;
> 
> Modified: llvm/trunk/lib/Target/PTX/generate-register-td.py
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/generate-register-td.py?rev=133873&r1=133872&r2=133873&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/PTX/generate-register-td.py (original)
> +++ llvm/trunk/lib/Target/PTX/generate-register-td.py Sat Jun 25 13:16:28 2011
> @@ -15,16 +15,15 @@
> from sys import argv, exit, stdout
> 
> 
> -if len(argv) != 6:
> -    print('Usage: generate-register-td.py <num_preds> <num_8> <num_16> <num_32> <num_64>')
> +if len(argv) != 5:
> +    print('Usage: generate-register-td.py <num_preds> <num_16> <num_32> <num_64>')
>     exit(1)
> 
> try:
>     num_pred  = int(argv[1])
> -    num_8bit  = int(argv[2])
> -    num_16bit = int(argv[3])
> -    num_32bit = int(argv[4])
> -    num_64bit = int(argv[5])
> +    num_16bit = int(argv[2])
> +    num_32bit = int(argv[3])
> +    num_64bit = int(argv[4])
> except:
>     print('ERROR: Invalid integer parameter')
>     exit(1)
> @@ -61,11 +60,6 @@
> for r in range(0, num_pred):
>     td_file.write('def P%d : PTXReg<"p%d">;\n' % (r, r))
> 
> -# Print 8-bit registers
> -td_file.write('\n///===- 8-Bit Registers --------------------------------------------------===//\n\n')
> -for r in range(0, num_8bit):
> -    td_file.write('def RQ%d : PTXReg<"rq%d">;\n' % (r, r))
> -
> # Print 16-bit registers
> td_file.write('\n///===- 16-Bit Registers --------------------------------------------------===//\n\n')
> for r in range(0, num_16bit):
> @@ -92,7 +86,6 @@
> # Print register classes
> 
> td_file.write('def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%%u", 0, %d)>;\n' % (num_pred-1))
> -td_file.write('def RegI8  : RegisterClass<"PTX", [i8],  8, (sequence "RQ%%u", 0, %d)>;\n' % (num_8bit-1))
> td_file.write('def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%%u", 0, %d)>;\n' % (num_16bit-1))
> td_file.write('def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
> td_file.write('def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
> @@ -108,20 +101,16 @@
> # Reserve 10% of the available registers for return values, and the other 90%
> # for parameters
> num_ret_pred    = int(0.1 * num_pred)
> -num_ret_8bit    = int(0.1 * num_8bit)
> num_ret_16bit   = int(0.1 * num_16bit)
> num_ret_32bit   = int(0.1 * num_32bit)
> num_ret_64bit   = int(0.1 * num_64bit)
> num_param_pred  = num_pred - num_ret_pred
> -num_param_8bit = num_8bit - num_ret_8bit
> num_param_16bit = num_16bit - num_ret_16bit
> num_param_32bit = num_32bit - num_ret_32bit
> num_param_64bit = num_64bit - num_ret_64bit
> 
> param_regs_pred  = [('P%d' % (i+num_ret_pred)) for i in range(0, num_param_pred)]
> ret_regs_pred    = ['P%d' % i for i in range(0, num_ret_pred)]
> -param_regs_8bit  = [('RQ%d' % (i+num_ret_8bit)) for i in range(0, num_param_8bit)]
> -ret_regs_8bit    = ['RQ%d' % i for i in range(0, num_ret_8bit)]
> param_regs_16bit = [('RH%d' % (i+num_ret_16bit)) for i in range(0, num_param_16bit)]
> ret_regs_16bit   = ['RH%d' % i for i in range(0, num_ret_16bit)]
> param_regs_32bit = [('R%d' % (i+num_ret_32bit)) for i in range(0, num_param_32bit)]
> @@ -131,8 +120,6 @@
> 
> param_list_pred  = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_pred)
> ret_list_pred    = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_pred)
> -param_list_8bit  = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_8bit)
> -ret_list_8bit    = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_8bit)
> param_list_16bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_16bit)
> ret_list_16bit   = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_16bit)
> param_list_32bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_32bit)
> @@ -157,7 +144,6 @@
> // PTX Formal Parameter Calling Convention
> def CC_PTX : CallingConv<[
>   CCIfType<[i1],      CCAssignToReg<[%s]>>,
> -  CCIfType<[i8],      CCAssignToReg<[%s]>>,
>   CCIfType<[i16],     CCAssignToReg<[%s]>>,
>   CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
>   CCIfType<[i64,f64], CCAssignToReg<[%s]>>
> @@ -166,13 +152,12 @@
> // PTX Return Value Calling Convention
> def RetCC_PTX : CallingConv<[
>   CCIfType<[i1],      CCAssignToReg<[%s]>>,
> -  CCIfType<[i8],      CCAssignToReg<[%s]>>,
>   CCIfType<[i16],     CCAssignToReg<[%s]>>,
>   CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
>   CCIfType<[i64,f64], CCAssignToReg<[%s]>>
> ]>;
> -''' % (param_list_pred, param_list_8bit, param_list_16bit, param_list_32bit, param_list_64bit,
> -       ret_list_pred, ret_list_8bit, ret_list_16bit, ret_list_32bit, ret_list_64bit))
> +''' % (param_list_pred, param_list_16bit, param_list_32bit, param_list_64bit,
> +       ret_list_pred, ret_list_16bit, ret_list_32bit, ret_list_64bit))
> 
> 
> td_file.close()
> 
> Modified: llvm/trunk/test/CodeGen/PTX/cvt.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/cvt.ll?rev=133873&r1=133872&r2=133873&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PTX/cvt.ll (original)
> +++ llvm/trunk/test/CodeGen/PTX/cvt.ll Sat Jun 25 13:16:28 2011
> @@ -3,17 +3,6 @@
> ; preds 
> ; (note: we convert back to i32 to return)
> 
> -define ptx_device i32 @cvt_pred_i8(i8 %x, i1 %y) {
> -; CHECK: setp.gt.b8 p[[P0:[0-9]+]], rq{{[0-9]+}}, 0
> -; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
> -; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
> -; CHECK-NEXT: ret;
> -	%a = trunc i8 %x to i1
> -	%b = and i1 %a, %y
> -	%c = zext i1 %b to i32
> -	ret i32 %c
> -}
> -
> define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) {
> ; CHECK: setp.gt.b16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0
> ; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
> @@ -69,43 +58,6 @@
> 	ret i32 %c
> }
> 
> -; i8
> -
> -define ptx_device i8 @cvt_i8_preds(i1 %x) {
> -; CHECK: selp.u8 rq{{[0-9]+}}, 1, 0, p{{[0-9]+}};
> -; CHECK-NEXT: ret;
> -	%a = zext i1 %x to i8
> -	ret i8 %a
> -}
> -
> -define ptx_device i8 @cvt_i8_i32(i32 %x) {
> -; CHECK: cvt.u8.u32 rq{{[0-9]+}}, r{{[0-9]+}};
> -; CHECK-NEXT: ret;
> -	%a = trunc i32 %x to i8
> -	ret i8 %a
> -}
> -
> -define ptx_device i8 @cvt_i8_i64(i64 %x) {
> -; CHECK: cvt.u8.u64 rq{{[0-9]+}}, rd{{[0-9]+}};
> -; CHECK-NEXT: ret;
> -	%a = trunc i64 %x to i8
> -	ret i8 %a
> -}
> -
> -define ptx_device i8 @cvt_i8_f32(float %x) {
> -; CHECK: cvt.rzi.u8.f32 rq{{[0-9]+}}, r{{[0-9]+}};
> -; CHECK-NEXT: ret;
> -	%a = fptoui float %x to i8
> -	ret i8 %a
> -}
> -
> -define ptx_device i8 @cvt_i8_f64(double %x) {
> -; CHECK: cvt.rzi.u8.f64 rq{{[0-9]+}}, rd{{[0-9]+}};
> -; CHECK-NEXT: ret;
> -	%a = fptoui double %x to i8
> -	ret i8 %a
> -}
> -
> ; i16
> 
> define ptx_device i16 @cvt_i16_preds(i1 %x) {
> @@ -115,13 +67,6 @@
> 	ret i16 %a
> }
> 
> -define ptx_device i16 @cvt_i16_i8(i8 %x) {
> -; CHECK: cvt.u16.u8 rh{{[0-9]+}}, rq{{[0-9]+}};
> -; CHECK-NEXT: ret;
> -	%a = zext i8 %x to i16
> -	ret i16 %a
> -}
> -
> define ptx_device i16 @cvt_i16_i32(i32 %x) {
> ; CHECK: cvt.u16.u32 rh{{[0-9]+}}, r{{[0-9]+}};
> ; CHECK-NEXT: ret;
> @@ -159,13 +104,6 @@
> 	ret i32 %a
> }
> 
> -define ptx_device i32 @cvt_i32_i8(i8 %x) {
> -; CHECK: cvt.u32.u8 r{{[0-9]+}}, rq{{[0-9]+}};
> -; CHECK-NEXT: ret;
> -	%a = zext i8 %x to i32
> -	ret i32 %a
> -}
> -
> define ptx_device i32 @cvt_i32_i16(i16 %x) {
> ; CHECK: cvt.u32.u16 r{{[0-9]+}}, rh{{[0-9]+}};
> ; CHECK-NEXT: ret;
> @@ -203,13 +141,6 @@
> 	ret i64 %a
> }
> 
> -define ptx_device i64 @cvt_i64_i8(i8 %x) {
> -; CHECK: cvt.u64.u8 rd{{[0-9]+}}, rq{{[0-9]+}};
> -; CHECK-NEXT: ret;
> -	%a = zext i8 %x to i64
> -	ret i64 %a
> -}
> -
> define ptx_device i64 @cvt_i64_i16(i16 %x) {
> ; CHECK: cvt.u64.u16 rd{{[0-9]+}}, rh{{[0-9]+}};
> ; CHECK-NEXT: ret;
> @@ -247,13 +178,6 @@
> 	ret float %a
> }
> 
> -define ptx_device float @cvt_f32_i8(i8 %x) {
> -; CHECK: cvt.rn.f32.u8 r{{[0-9]+}}, rq{{[0-9]+}};
> -; CHECK-NEXT: ret;
> -	%a = uitofp i8 %x to float
> -	ret float %a
> -}
> -
> define ptx_device float @cvt_f32_i16(i16 %x) {
> ; CHECK: cvt.rn.f32.u16 r{{[0-9]+}}, rh{{[0-9]+}};
> ; CHECK-NEXT: ret;
> @@ -291,13 +215,6 @@
> 	ret double %a
> }
> 
> -define ptx_device double @cvt_f64_i8(i8 %x) {
> -; CHECK: cvt.rn.f64.u8 rd{{[0-9]+}}, rq{{[0-9]+}};
> -; CHECK-NEXT: ret;
> -	%a = uitofp i8 %x to double
> -	ret double %a
> -}
> -
> define ptx_device double @cvt_f64_i16(i16 %x) {
> ; CHECK: cvt.rn.f64.u16 rd{{[0-9]+}}, rh{{[0-9]+}};
> ; CHECK-NEXT: ret;
> 
> Modified: llvm/trunk/test/CodeGen/PTX/ld.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/ld.ll?rev=133873&r1=133872&r2=133873&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PTX/ld.ll (original)
> +++ llvm/trunk/test/CodeGen/PTX/ld.ll Sat Jun 25 13:16:28 2011
> @@ -1,17 +1,5 @@
> ; RUN: llc < %s -march=ptx32 | FileCheck %s
> 
> -;CHECK: .extern .global .b8 array_i8[10];
> - at array_i8 = external global [10 x i8]
> -
> -;CHECK: .extern .const .b8 array_constant_i8[10];
> - at array_constant_i8 = external addrspace(1) constant [10 x i8]
> -
> -;CHECK: .extern .local .b8 array_local_i8[10];
> - at array_local_i8 = external addrspace(2) global [10 x i8]
> -
> -;CHECK: .extern .shared .b8 array_shared_i8[10];
> - at array_shared_i8 = external addrspace(4) global [10 x i8]
> -
> ;CHECK: .extern .global .b8 array_i16[20];
> @array_i16 = external global [10 x i16]
> 
> @@ -72,13 +60,6 @@
> ;CHECK: .extern .shared .b8 array_shared_double[80];
> @array_shared_double = external addrspace(4) global [10 x double]
> 
> -define ptx_device i8 @t1_u8(i8* %p) {
> -entry:
> -;CHECK: ld.global.u8 rq{{[0-9]+}}, [r{{[0-9]+}}];
> -;CHECK-NEXT: ret;
> -  %x = load i8* %p
> -  ret i8 %x
> -}
> 
> define ptx_device i16 @t1_u16(i16* %p) {
> entry:
> @@ -120,15 +101,6 @@
>   ret double %x
> }
> 
> -define ptx_device i8 @t2_u8(i8* %p) {
> -entry:
> -;CHECK: ld.global.u8 rq{{[0-9]+}}, [r{{[0-9]+}}+1];
> -;CHECK-NEXT: ret;
> -  %i = getelementptr i8* %p, i32 1
> -  %x = load i8* %i
> -  ret i8 %x
> -}
> -
> define ptx_device i16 @t2_u16(i16* %p) {
> entry:
> ;CHECK: ld.global.u16 rh{{[0-9]+}}, [r{{[0-9]+}}+2];
> @@ -174,15 +146,6 @@
>   ret double %x
> }
> 
> -define ptx_device i8 @t3_u8(i8* %p, i32 %q) {
> -entry:
> -;CHECK: add.u32 r[[R0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
> -;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]];
> -  %i = getelementptr i8* %p, i32 %q
> -  %x = load i8* %i
> -  ret i8 %x
> -}
> -
> define ptx_device i16 @t3_u16(i16* %p, i32 %q) {
> entry:
> ;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 1;
> @@ -233,16 +196,6 @@
>   ret double %x
> }
> 
> -define ptx_device i8 @t4_global_u8() {
> -entry:
> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
> -;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]];
> -;CHECK-NEXT: ret;
> -  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 0
> -  %x = load i8* %i
> -  ret i8 %x
> -}
> -
> define ptx_device i16 @t4_global_u16() {
> entry:
> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
> @@ -343,16 +296,6 @@
>   ret double %x
> }
> 
> -define ptx_device i8 @t4_local_u8() {
> -entry:
> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i8;
> -;CHECK-NEXT: ld.local.u8 rq{{[0-9]+}}, [r[[R0]]];
> -;CHECK-NEXT: ret;
> -  %i = getelementptr [10 x i8] addrspace(2)* @array_local_i8, i32 0, i32 0
> -  %x = load i8 addrspace(2)* %i
> -  ret i8 %x
> -}
> -
> define ptx_device i16 @t4_local_u16() {
> entry:
> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i16;
> @@ -403,16 +346,6 @@
>   ret double %x
> }
> 
> -define ptx_device i8 @t4_shared_u8() {
> -entry:
> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i8;
> -;CHECK-NEXT: ld.shared.u8 rq{{[0-9]+}}, [r[[R0]]];
> -;CHECK-NEXT: ret;
> -  %i = getelementptr [10 x i8] addrspace(4)* @array_shared_i8, i32 0, i32 0
> -  %x = load i8 addrspace(4)* %i
> -  ret i8 %x
> -}
> -
> define ptx_device i16 @t4_shared_u16() {
> entry:
> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i16;
> @@ -463,16 +396,6 @@
>   ret double %x
> }
> 
> -define ptx_device i8 @t5_u8() {
> -entry:
> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
> -;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]+1];
> -;CHECK-NEXT: ret;
> -  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 1
> -  %x = load i8* %i
> -  ret i8 %x
> -}
> -
> define ptx_device i16 @t5_u16() {
> entry:
> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
> 
> Modified: llvm/trunk/test/CodeGen/PTX/mov.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mov.ll?rev=133873&r1=133872&r2=133873&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PTX/mov.ll (original)
> +++ llvm/trunk/test/CodeGen/PTX/mov.ll Sat Jun 25 13:16:28 2011
> @@ -1,11 +1,5 @@
> ; RUN: llc < %s -march=ptx32 | FileCheck %s
> 
> -define ptx_device i8 @t1_u8() {
> -; CHECK: mov.u8 rq{{[0-9]+}}, 0;
> -; CHECK: ret;
> -	ret i8 0
> -}
> -
> define ptx_device i16 @t1_u16() {
> ; CHECK: mov.u16 rh{{[0-9]+}}, 0;
> ; CHECK: ret;
> @@ -36,12 +30,6 @@
> 	ret double 0.0
> }
> 
> -define ptx_device i8 @t2_u8(i8 %x) {
> -; CHECK: mov.u8 rq{{[0-9]+}}, rq{{[0-9]+}};
> -; CHECK: ret;
> -	ret i8 %x
> -}
> -
> define ptx_device i16 @t2_u16(i16 %x) {
> ; CHECK: mov.u16 rh{{[0-9]+}}, rh{{[0-9]+}};
> ; CHECK: ret;
> 
> Modified: llvm/trunk/test/CodeGen/PTX/st.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/st.ll?rev=133873&r1=133872&r2=133873&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/PTX/st.ll (original)
> +++ llvm/trunk/test/CodeGen/PTX/st.ll Sat Jun 25 13:16:28 2011
> @@ -1,17 +1,5 @@
> ; RUN: llc < %s -march=ptx32 | FileCheck %s
> 
> -;CHECK: .extern .global .b8 array_i8[10];
> - at array_i8 = external global [10 x i8]
> -
> -;CHECK: .extern .const .b8 array_constant_i8[10];
> - at array_constant_i8 = external addrspace(1) constant [10 x i8]
> -
> -;CHECK: .extern .local .b8 array_local_i8[10];
> - at array_local_i8 = external addrspace(2) global [10 x i8]
> -
> -;CHECK: .extern .shared .b8 array_shared_i8[10];
> - at array_shared_i8 = external addrspace(4) global [10 x i8]
> -
> ;CHECK: .extern .global .b8 array_i16[20];
> @array_i16 = external global [10 x i16]
> 
> @@ -72,13 +60,6 @@
> ;CHECK: .extern .shared .b8 array_shared_double[80];
> @array_shared_double = external addrspace(4) global [10 x double]
> 
> -define ptx_device void @t1_u8(i8* %p, i8 %x) {
> -entry:
> -;CHECK: st.global.u8 [r{{[0-9]+}}], rq{{[0-9]+}};
> -;CHECK-NEXT: ret;
> -  store i8 %x, i8* %p
> -  ret void
> -}
> 
> define ptx_device void @t1_u16(i16* %p, i16 %x) {
> entry:
> @@ -120,15 +101,6 @@
>   ret void
> }
> 
> -define ptx_device void @t2_u8(i8* %p, i8 %x) {
> -entry:
> -;CHECK: st.global.u8 [r{{[0-9]+}}+1], rq{{[0-9]+}};
> -;CHECK-NEXT: ret;
> -  %i = getelementptr i8* %p, i32 1
> -  store i8 %x, i8* %i
> -  ret void
> -}
> -
> define ptx_device void @t2_u16(i16* %p, i16 %x) {
> entry:
> ;CHECK: st.global.u16 [r{{[0-9]+}}+2], rh{{[0-9]+}};
> @@ -174,16 +146,6 @@
>   ret void
> }
> 
> -define ptx_device void @t3_u8(i8* %p, i32 %q, i8 %x) {
> -entry:
> -;CHECK: add.u32 r[[R0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
> -;CHECK-NEXT: st.global.u8 [r[[R0]]], rq{{[0-9]+}};
> -;CHECK-NEXT: ret;
> -  %i = getelementptr i8* %p, i32 %q
> -  store i8 %x, i8* %i
> -  ret void
> -}
> -
> define ptx_device void @t3_u16(i16* %p, i32 %q, i16 %x) {
> entry:
> ;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 1;
> @@ -239,16 +201,6 @@
>   ret void
> }
> 
> -define ptx_device void @t4_global_u8(i8 %x) {
> -entry:
> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
> -;CHECK-NEXT: st.global.u8 [r[[R0]]], rq{{[0-9]+}};
> -;CHECK-NEXT: ret;
> -  %i = getelementptr [10 x i8]* @array_i8, i8 0, i8 0
> -  store i8 %x, i8* %i
> -  ret void
> -}
> -
> define ptx_device void @t4_global_u16(i16 %x) {
> entry:
> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
> @@ -299,16 +251,6 @@
>   ret void
> }
> 
> -define ptx_device void @t4_local_u8(i8 %x) {
> -entry:
> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i8;
> -;CHECK-NEXT: st.local.u8 [r[[R0]]], rq{{[0-9]+}};
> -;CHECK-NEXT: ret;
> -  %i = getelementptr [10 x i8] addrspace(2)* @array_local_i8, i32 0, i32 0
> -  store i8 %x, i8 addrspace(2)* %i
> -  ret void
> -}
> -
> define ptx_device void @t4_local_u16(i16 %x) {
> entry:
> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i16;
> @@ -359,16 +301,6 @@
>   ret void
> }
> 
> -define ptx_device void @t4_shared_u8(i8 %x) {
> -entry:
> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i8;
> -;CHECK-NEXT: st.shared.u8 [r[[R0]]], rq{{[0-9]+}};
> -;CHECK-NEXT: ret;
> -  %i = getelementptr [10 x i8] addrspace(4)* @array_shared_i8, i32 0, i32 0
> -  store i8 %x, i8 addrspace(4)* %i
> -  ret void
> -}
> -
> define ptx_device void @t4_shared_u16(i16 %x) {
> entry:
> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i16;
> @@ -419,16 +351,6 @@
>   ret void
> }
> 
> -define ptx_device void @t5_u8(i8 %x) {
> -entry:
> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
> -;CHECK-NEXT: st.global.u8 [r[[R0]]+1], rq{{[0-9]+}};
> -;CHECK-NEXT: ret;
> -  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 1
> -  store i8 %x, i8* %i
> -  ret void
> -}
> -
> define ptx_device void @t5_u16(i16 %x) {
> entry:
> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From mcrosier at apple.com  Sat Jun 25 13:51:28 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Sat, 25 Jun 2011 18:51:28 -0000
Subject: [llvm-commits] [llvm] r133874 -
	/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
Message-ID: <20110625185128.79CDB2A6C12C@llvm.org>

Author: mcrosier
Date: Sat Jun 25 13:51:28 2011
New Revision: 133874

URL: http://llvm.org/viewvc/llvm-project?rev=133874&view=rev
Log:
Replace dyn_cast<> with cast<> since the cast is already guarded by the necessary check.

Modified:
    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=133874&r1=133873&r2=133874&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Sat Jun 25 13:51:28 2011
@@ -2506,7 +2506,7 @@
       return false;
     FI = FINode->getIndex();
   } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
-    FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Arg);
+    FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg);
     FI = FINode->getIndex();
     Bytes = Flags.getByValSize();
   } else



From mcrosier at apple.com  Sat Jun 25 13:58:03 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Sat, 25 Jun 2011 11:58:03 -0700
Subject: [llvm-commits] [llvm] r133858 -
 /llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
In-Reply-To: <BANLkTikJpH35Zx23NCfmWWPF=E8_yYo3+g@mail.gmail.com>
References: <20110625020456.B3EE22A6C12C@llvm.org>
	<BANLkTikJpH35Zx23NCfmWWPF=E8_yYo3+g@mail.gmail.com>
Message-ID: <72CF932B-D8CC-48F0-ADE1-7598D71ADAE3@apple.com>

You are correct!  Thanks Frits.  Committed revision 133874.

 Chad


On Jun 25, 2011, at 2:23 AM, Frits van Bommel wrote:

> On 25 June 2011 04:04, Chad Rosier <mcrosier at apple.com> wrote:
>> +  } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) {
>> +    FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Arg);
>> +    FI = FINode->getIndex();
> 
> That dyn_cast<> should probably be a cast<>, because
> 1) if it fails it's an error anyway, and
> 2) you're already checking that it can't fail beforehand.


From dan at dneg.com  Sat Jun 25 14:41:17 2011
From: dan at dneg.com (Dan Bailey)
Date: Sat, 25 Jun 2011 19:41:17 -0000
Subject: [llvm-commits] [llvm] r133875 - in /llvm/trunk/test/CodeGen/PTX:
	cvt.ll setp.ll
Message-ID: <20110625194117.E67E52A6C12C@llvm.org>

Author: drb
Date: Sat Jun 25 14:41:17 2011
New Revision: 133875

URL: http://llvm.org/viewvc/llvm-project?rev=133875&view=rev
Log:
PTX: corrected tests that were failing

Modified:
    llvm/trunk/test/CodeGen/PTX/cvt.ll
    llvm/trunk/test/CodeGen/PTX/setp.ll

Modified: llvm/trunk/test/CodeGen/PTX/cvt.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/cvt.ll?rev=133875&r1=133874&r2=133875&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/cvt.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/cvt.ll Sat Jun 25 14:41:17 2011
@@ -4,7 +4,7 @@
 ; (note: we convert back to i32 to return)
 
 define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) {
-; CHECK: setp.gt.b16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0
+; CHECK: setp.gt.u16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0
 ; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
 ; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
 ; CHECK-NEXT: ret;
@@ -15,7 +15,7 @@
 }
 
 define ptx_device i32 @cvt_pred_i32(i32 %x, i1 %y) {
-; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0
+; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0
 ; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
 ; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
 ; CHECK-NEXT: ret;
@@ -26,7 +26,7 @@
 }
 
 define ptx_device i32 @cvt_pred_i64(i64 %x, i1 %y) {
-; CHECK: setp.gt.b64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0
+; CHECK: setp.gt.u64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0
 ; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
 ; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
 ; CHECK-NEXT: ret;
@@ -37,7 +37,7 @@
 }
 
 define ptx_device i32 @cvt_pred_f32(float %x, i1 %y) {
-; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0
+; CHECK: setp.gt.f32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0
 ; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
 ; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
 ; CHECK-NEXT: ret;
@@ -48,7 +48,7 @@
 }
 
 define ptx_device i32 @cvt_pred_f64(double %x, i1 %y) {
-; CHECK: setp.gt.b64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0
+; CHECK: setp.gt.f64 p[[P0:[0-9]+]], rd{{[0-9]+}}, 0
 ; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
 ; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
 ; CHECK-NEXT: ret;

Modified: llvm/trunk/test/CodeGen/PTX/setp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/setp.ll?rev=133875&r1=133874&r2=133875&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PTX/setp.ll (original)
+++ llvm/trunk/test/CodeGen/PTX/setp.ll Sat Jun 25 14:41:17 2011
@@ -193,7 +193,7 @@
 }
 
 define ptx_device i32 @test_setp_4_op_format_2(i32 %x, i32 %y, i32 %w) {
-; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
+; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
 ; CHECK-NEXT: setp.eq.and.u32 p[[P0]], r{{[0-9]+}}, r{{[0-9]+}}, !p[[P0]];
 ; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
 ; CHECK-NEXT: ret;



From dan at dneg.com  Sat Jun 25 14:50:03 2011
From: dan at dneg.com (Dan Bailey)
Date: Sat, 25 Jun 2011 20:50:03 +0100
Subject: [llvm-commits] [llvm] r133873 - in /llvm/trunk:
 lib/Target/PTX/PTXAsmPrinter.cpp lib/Target/PTX/PTXCallingConv.td
 lib/Target/PTX/PTXISelLowering.cpp lib/Target/PTX/PTXInstrInfo.cpp
 lib/Target/PTX/PTXInstrInfo.td lib/Target/PTX/PTXRegisterInfo.td
 lib/Target/PTX/generate-register-td.py test/CodeGen/PTX/cvt.ll
 test/CodeGen/PTX/ld.ll test/CodeGen/PTX/mov.ll test/CodeGen/PTX/st.ll
In-Reply-To: <C11B2CF8-13AE-4A9A-ACCA-E227BF5E6315@apple.com>
References: <20110625181629.0E99A2A6C12C@llvm.org>
	<C11B2CF8-13AE-4A9A-ACCA-E227BF5E6315@apple.com>
Message-ID: <4E063BEB.3070806@dneg.com>

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From mcrosier at apple.com  Sat Jun 25 14:50:46 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Sat, 25 Jun 2011 12:50:46 -0700
Subject: [llvm-commits] [llvm] r133873 - in /llvm/trunk:
 lib/Target/PTX/PTXAsmPrinter.cpp lib/Target/PTX/PTXCallingConv.td
 lib/Target/PTX/PTXISelLowering.cpp lib/Target/PTX/PTXInstrInfo.cpp
 lib/Target/PTX/PTXInstrInfo.td lib/Target/PTX/PTXRegisterInfo.td
 lib/Target/PTX/generate-register-td.py test/CodeGen/PTX/cvt.ll
 test/CodeGen/PTX/ld.ll test/CodeGen/PTX/mov.ll test/CodeGen/PTX/st.ll
In-Reply-To: <4E063BEB.3070806@dneg.com>
References: <20110625181629.0E99A2A6C12C@llvm.org>
	<C11B2CF8-13AE-4A9A-ACCA-E227BF5E6315@apple.com>
	<4E063BEB.3070806@dneg.com>
Message-ID: <23E8F04A-2ADC-411F-B6B3-7B90530434EA@apple.com>

Thanks Dan!

On Jun 25, 2011, at 12:50 PM, Dan Bailey wrote:

> Sorry about that, I've corrected the tests in r133875. Think I was picking up a different build by accident.
> 
> All should be well now.
> 
> Dan
> 
> Chad Rosier wrote:
>> 
>> Dan,
>> It looks like cvt.ll and step.ll are failing.  Can you please take a look when you have a moment?
>> 
>>  Regards,
>>   Chad
>> 
>>  ******************** TEST 'LLVM :: CodeGen/PTX/cvt.ll' FAILED ********************
>> Script:
>> --
>> /home/baldrick/osuosl/slave/llvm-x86_64/llvm/Debug+Asserts/bin/llc < /home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/cvt.ll -march=ptx32 | /home/baldrick/osuosl/slave/llvm-x86_64/llvm/Debug+Asserts/bin/FileCheck /home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/cvt.ll
>> --
>> Exit Code: 1
>> Command Output (stderr):
>> --
>> /home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/cvt.ll:7:10: error: expected string not found in input
>> ; CHECK: setp.gt.b16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0
>>          ^
>> <stdin>:1:2: note: scanning from here
>>  .version 2.0
>>  ^
>> <stdin>:9:2: note: possible intended match here
>>  setp.gt.u16 p0, rh12, 0;
>>  ^
>> --
>> 
>> ********************
>>  ******************** TEST 'LLVM :: CodeGen/PTX/setp.ll' FAILED ********************
>> Script:
>> --
>> /home/baldrick/osuosl/slave/llvm-x86_64/llvm/Debug+Asserts/bin/llc < /home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/setp.ll -march=ptx32 | /home/baldrick/osuosl/slave/llvm-x86_64/llvm/Debug+Asserts/bin/FileCheck /home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/setp.ll
>> --
>> Exit Code: 1
>> Command Output (stderr):
>> --
>> /home/baldrick/osuosl/slave/llvm-x86_64/llvm/test/CodeGen/PTX/setp.ll:196:10: error: expected string not found in input
>> ; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
>>          ^
>> <stdin>:193:1: note: scanning from here
>> }
>> ^
>> <stdin>:199:2: note: possible intended match here
>>  setp.gt.u32 p0, r14, 0;
>>  ^
>> --
>> 
>> ********************
>> 
>> 
>> 
>> On Jun 25, 2011, at 11:16 AM, Dan Bailey wrote:
>> 
>>> Author: drb
>>> Date: Sat Jun 25 13:16:28 2011
>>> New Revision: 133873
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=133873&view=rev
>>> Log:
>>> PTX: Reverting implementation of i8.
>>> 
>>> The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is
>>> not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support
>>> boolean values.
>>> 
>>> 
>>> Modified:
>>>    llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
>>>    llvm/trunk/lib/Target/PTX/PTXCallingConv.td
>>>    llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
>>>    llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
>>>    llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
>>>    llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td
>>>    llvm/trunk/lib/Target/PTX/generate-register-td.py
>>>    llvm/trunk/test/CodeGen/PTX/cvt.ll
>>>    llvm/trunk/test/CodeGen/PTX/ld.ll
>>>    llvm/trunk/test/CodeGen/PTX/mov.ll
>>>    llvm/trunk/test/CodeGen/PTX/st.ll
>>> 
>>> Modified: llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp?rev=133873&r1=133872&r2=133873&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp (original)
>>> +++ llvm/trunk/lib/Target/PTX/PTXAsmPrinter.cpp Sat Jun 25 13:16:28 2011
>>> @@ -92,7 +92,6 @@
>>> #define TEST_REGCLS(cls, clsstr)                \
>>>   if (PTX::cls ## RegisterClass->contains(RegNo)) return # clsstr;
>>>   TEST_REGCLS(RegPred, pred);
>>> -  TEST_REGCLS(RegI8,  b8);
>>>   TEST_REGCLS(RegI16, b16);
>>>   TEST_REGCLS(RegI32, b32);
>>>   TEST_REGCLS(RegI64, b64);
>>> @@ -125,7 +124,6 @@
>>>       case Type::IntegerTyID:
>>>         switch (type->getPrimitiveSizeInBits()) {
>>>           default: llvm_unreachable("Unknown integer bit-width");
>>> -          case 8:  return ".u8";
>>>           case 16: return ".u16";
>>>           case 32: return ".u32";
>>>           case 64: return ".u64";
>>> 
>>> Modified: llvm/trunk/lib/Target/PTX/PTXCallingConv.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXCallingConv.td?rev=133873&r1=133872&r2=133873&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/PTX/PTXCallingConv.td (original)
>>> +++ llvm/trunk/lib/Target/PTX/PTXCallingConv.td Sat Jun 25 13:16:28 2011
>>> @@ -15,7 +15,6 @@
>>> // PTX Formal Parameter Calling Convention
>>> def CC_PTX : CallingConv<[
>>>   CCIfType<[i1],      CCAssignToReg<[P12, P13, P14, P15, P16, P17, P18, P19, P20, P21, P22, P23, P24, P25, P26, P27, P28, P29, P30, P31, P32, P33, P34, P35, P36, P37, P38, P39, P40, P41, P42, P43, P44, P45, P46, P47, P48, P49, P50, P51, P52, P53, P54, P55, P56, P57, P58, P59, P60, P61, P62, P63, P64, P65, P66, P67, P68, P69, P70, P71, P72, P73, P74, P75, P76, P77, P78, P79, P80, P81, P82, P83, P84, P85, P86, P87, P88, P89, P90, P91, P92, P93, P94, P95, P96, P97, P98, P99, P100, P101, P102, P103, P104, P105, P106, P107, P108, P109, P110, P111, P112, P113, P114, P115, P116, P117, P118, P119, P120, P121, P122, P123, P124, P125, P126, P127]>>,
>>> -  CCIfType<[i8],      CCAssignToReg<[RQ12, RQ13, RQ14, RQ15, RQ16, RQ17, RQ18, RQ19, RQ20, RQ21, RQ22, RQ23, RQ24, RQ25, RQ26, RQ27, RQ28, RQ29, RQ30, RQ31, RQ32, RQ33, RQ34, RQ35, RQ36, RQ37, RQ38, RQ39, RQ40, RQ41, RQ42, RQ43, RQ44, RQ45, RQ46, RQ47, RQ48, RQ49, RQ50, RQ51, RQ52, RQ53, RQ54, RQ55, RQ56, RQ57, RQ58, RQ59, RQ60, RQ61, RQ62, RQ63, RQ64, RQ65, RQ66, RQ67, RQ68, RQ69, RQ70, RQ71, RQ72, RQ73, RQ74, RQ75, RQ76, RQ77, RQ78, RQ79, RQ80, RQ81, RQ82, RQ83, RQ84, RQ85, RQ86, RQ87, RQ88, RQ89, RQ90, RQ91, RQ92, RQ93, RQ94, RQ95, RQ96, RQ97, RQ98, RQ99, RQ100, RQ101, RQ102, RQ103, RQ104, RQ105, RQ106, RQ107, RQ108, RQ109, RQ110, RQ111, RQ112, RQ113, RQ114, RQ115, RQ116, RQ117, RQ118, RQ119, RQ120, RQ121, RQ122, RQ123, RQ124, RQ125, RQ126, RQ127]>>,
>>>   CCIfType<[i16],     CCAssignToReg<[RH12, RH13, RH14, RH15, RH16, RH17, RH18, RH19, RH20, RH21, RH22, RH23, RH24, RH25, RH26, RH27, RH28, RH29, RH30, RH31, RH32, RH33, RH34, RH35, RH36, RH37, RH38, RH39, RH40, RH41, RH42, RH43, RH44, RH45, RH46, RH47, RH48, RH49, RH50, RH51, RH52, RH53, RH54, RH55, RH56, RH57, RH58, RH59, RH60, RH61, RH62, RH63, RH64, RH65, RH66, RH67, RH68, RH69, RH70, RH71, RH72, RH73, RH74, RH75, RH76, RH77, RH78, RH79, RH80, RH81, RH82, RH83, RH84, RH85, RH86, RH87, RH88, RH89, RH90, RH91, RH92, RH93, RH94, RH95, RH96, RH97, RH98, RH99, RH100, RH101, RH102, RH103, RH104, RH105, RH106, RH107, RH108, RH109, RH110, RH111, RH112, RH113, RH114, RH115, RH116, RH117, RH118, RH119, RH120, RH121, RH122, RH123, RH124, RH125, RH126, RH127]>>,
>>>   CCIfType<[i32,f32], CCAssignToReg<[R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127]>>,
>>>   CCIfType<[i64,f64], CCAssignToReg<[RD12, RD13, RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26, RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35, RD36, RD37, RD38, RD39, RD40, RD41, RD42, RD43, RD44, RD45, RD46, RD47, RD48, RD49, RD50, RD51, RD52, RD53, RD54, RD55, RD56, RD57, RD58, RD59, RD60, RD61, RD62, RD63, RD64, RD65, RD66, RD67, RD68, RD69, RD70, RD71, RD72, RD73, RD74, RD75, RD76, RD77, RD78, RD79, RD80, RD81, RD82, RD83, RD84, RD85, RD86, RD87, RD88, RD89, RD90, RD91, RD92, RD93, RD94, RD95, RD96, RD97, RD98, RD99, RD100, RD101, RD102, RD103, RD104, RD105, RD106, RD107, RD108, RD109, RD110, RD111, RD112, RD113, RD114, RD115, RD116, RD117, RD118, RD119, RD120, RD121, RD122, RD123, RD124, RD125, RD126, RD127]>>
>>> @@ -24,7 +23,6 @@
>>> // PTX Return Value Calling Convention
>>> def RetCC_PTX : CallingConv<[
>>>   CCIfType<[i1],      CCAssignToReg<[P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11]>>,
>>> -  CCIfType<[i8],      CCAssignToReg<[RQ0, RQ1, RQ2, RQ3, RQ4, RQ5, RQ6, RQ7, RQ8, RQ9, RQ10, RQ11]>>,
>>>   CCIfType<[i16],     CCAssignToReg<[RH0, RH1, RH2, RH3, RH4, RH5, RH6, RH7, RH8, RH9, RH10, RH11]>>,
>>>   CCIfType<[i32,f32], CCAssignToReg<[R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11]>>,
>>>   CCIfType<[i64,f64], CCAssignToReg<[RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11]>>
>>> 
>>> Modified: llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp?rev=133873&r1=133872&r2=133873&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp (original)
>>> +++ llvm/trunk/lib/Target/PTX/PTXISelLowering.cpp Sat Jun 25 13:16:28 2011
>>> @@ -40,7 +40,6 @@
>>>   : TargetLowering(TM, new TargetLoweringObjectFileELF()) {
>>>   // Set up the register classes.
>>>   addRegisterClass(MVT::i1,  PTX::RegPredRegisterClass);
>>> -  addRegisterClass(MVT::i8,  PTX::RegI8RegisterClass);
>>>   addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
>>>   addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
>>>   addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
>>> @@ -48,48 +47,59 @@
>>>   addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
>>> 
>>>   setBooleanContents(ZeroOrOneBooleanContent);
>>> -
>>> -  setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
>>> -
>>> -  setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
>>> -  setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
>>> -  
>>> -  // Promote i1 type
>>> -  setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
>>> -  setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
>>> -  setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
>>> +  setMinFunctionAlignment(2);
>>> 
>>> -  setTruncStoreAction(MVT::i8, MVT::i1, Promote);
>>> +  ////////////////////////////////////
>>> +  /////////// Expansion //////////////
>>> +  ////////////////////////////////////
>>> 
>>> -  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
>>> +  // (any/zero/sign) extload => load + (any/zero/sign) extend
>>> 
>>> -  // Turn i16 (z)extload into load + (z)extend
>>>   setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
>>>   setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
>>>   setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
>>> -
>>> -  // Turn f32 extload into load + fextend
>>> -  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
>>> -
>>> -  // Turn f64 truncstore into trunc + store.
>>> -  setTruncStoreAction(MVT::f64, MVT::f32, Expand);
>>> -
>>> -  // Customize translation of memory addresses
>>> -  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
>>> -  setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
>>> -
>>> -  // Expand BR_CC into BRCOND
>>> +  
>>> +  // f32 extload => load + fextend
>>> +  
>>> +  setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);  
>>> +  
>>> +  // f64 truncstore => trunc + store
>>> +  
>>> +  setTruncStoreAction(MVT::f64, MVT::f32, Expand); 
>>> +  
>>> +  // sign_extend_inreg => sign_extend
>>> +  
>>> +  setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
>>> +  
>>> +  // br_cc => brcond
>>> +  
>>>   setOperationAction(ISD::BR_CC, MVT::Other, Expand);
>>> 
>>> -  // Expand SELECT_CC into SETCC
>>> +  // select_cc => setcc
>>> +  
>>>   setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
>>>   setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
>>>   setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
>>> -
>>> -  // need to lower SETCC of RegPred into bitwise logic
>>> +  
>>> +  ////////////////////////////////////
>>> +  //////////// Legal /////////////////
>>> +  ////////////////////////////////////
>>> +  
>>> +  setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
>>> +  setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
>>> +  
>>> +  ////////////////////////////////////
>>> +  //////////// Custom ////////////////
>>> +  ////////////////////////////////////
>>> +  
>>> +  // customise setcc to use bitwise logic if possible
>>> +  
>>>   setOperationAction(ISD::SETCC, MVT::i1, Custom);
>>> 
>>> -  setMinFunctionAlignment(2);
>>> +  // customize translation of memory addresses
>>> +  
>>> +  setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
>>> +  setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
>>> 
>>>   // Compute derived properties from the register classes
>>>   computeRegisterProperties();
>>> @@ -187,7 +197,6 @@
>>>   bool operator==(MVT::SimpleValueType _VT) const { return VT == _VT; }
>>> } argmap[] = {
>>>   argmap_entry(MVT::i1,  PTX::RegPredRegisterClass),
>>> -  argmap_entry(MVT::i8,  PTX::RegI8RegisterClass),
>>>   argmap_entry(MVT::i16, PTX::RegI16RegisterClass),
>>>   argmap_entry(MVT::i32, PTX::RegI32RegisterClass),
>>>   argmap_entry(MVT::i64, PTX::RegI64RegisterClass),
>>> @@ -264,9 +273,6 @@
>>>       if (RegVT == MVT::i1) {
>>>         TRC = PTX::RegPredRegisterClass;
>>>       }
>>> -      else if (RegVT == MVT::i8) {
>>> -        TRC = PTX::RegI8RegisterClass;
>>> -      }
>>>       else if (RegVT == MVT::i16) {
>>>         TRC = PTX::RegI16RegisterClass;
>>>       }
>>> 
>>> Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=133873&r1=133872&r2=133873&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original)
>>> +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Sat Jun 25 13:16:28 2011
>>> @@ -33,7 +33,6 @@
>>>   const TargetRegisterClass *cls;
>>>   const int opcode;
>>> } map[] = {
>>> -  { &PTX::RegI8RegClass,  PTX::MOVU8rr },
>>>   { &PTX::RegI16RegClass, PTX::MOVU16rr },
>>>   { &PTX::RegI32RegClass, PTX::MOVU32rr },
>>>   { &PTX::RegI64RegClass, PTX::MOVU64rr },
>>> @@ -303,9 +302,7 @@
>>>   int OpCode;
>>> 
>>>   // Select the appropriate opcode based on the register class
>>> -  if (RC == PTX::RegI8RegisterClass) {
>>> -    OpCode = PTX::STACKSTOREI8;
>>> -  } else if (RC == PTX::RegI16RegisterClass) {
>>> +  if (RC == PTX::RegI16RegisterClass) {
>>>     OpCode = PTX::STACKSTOREI16;
>>>   }  else if (RC == PTX::RegI32RegisterClass) {
>>>     OpCode = PTX::STACKSTOREI32;
>>> @@ -340,9 +337,7 @@
>>>   int OpCode;
>>> 
>>>   // Select the appropriate opcode based on the register class
>>> -  if (RC == PTX::RegI8RegisterClass) {
>>> -    OpCode = PTX::STACKLOADI8;
>>> -  } else if (RC == PTX::RegI16RegisterClass) {
>>> +  if (RC == PTX::RegI16RegisterClass) {
>>>     OpCode = PTX::STACKLOADI16;
>>>   } else if (RC == PTX::RegI32RegisterClass) {
>>>     OpCode = PTX::STACKLOADI32;
>>> 
>>> Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.td?rev=133873&r1=133872&r2=133873&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.td (original)
>>> +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.td Sat Jun 25 13:16:28 2011
>>> @@ -537,7 +537,6 @@
>>> }
>>> 
>>> multiclass PTX_LD_ALL<string opstr, PatFrag pat_load> {
>>> -  defm u8  : PTX_LD<opstr, ".u8",  RegI8,  pat_load>;
>>>   defm u16 : PTX_LD<opstr, ".u16", RegI16, pat_load>;
>>>   defm u32 : PTX_LD<opstr, ".u32", RegI32, pat_load>;
>>>   defm u64 : PTX_LD<opstr, ".u64", RegI64, pat_load>;
>>> @@ -573,7 +572,6 @@
>>> }
>>> 
>>> multiclass PTX_ST_ALL<string opstr, PatFrag pat_store> {
>>> -  defm u8  : PTX_ST<opstr, ".u8",  RegI8,  pat_store>;
>>>   defm u16 : PTX_ST<opstr, ".u16", RegI16, pat_store>;
>>>   defm u32 : PTX_ST<opstr, ".u32", RegI32, pat_store>;
>>>   defm u64 : PTX_ST<opstr, ".u64", RegI64, pat_store>;
>>> @@ -785,27 +783,22 @@
>>> let neverHasSideEffects = 1 in {
>>>   def MOVPREDrr
>>>     : InstPTX<(outs RegPred:$d), (ins RegPred:$a), "mov.pred\t$d, $a", []>;
>>> -  def MOVU8rr
>>> -    : InstPTX<(outs RegI8:$d),   (ins RegI8:$a),   "mov.u8\t$d, $a",  []>;
>>>   def MOVU16rr
>>> -    : InstPTX<(outs RegI16:$d),  (ins RegI16:$a),  "mov.u16\t$d, $a", []>;
>>> +    : InstPTX<(outs RegI16:$d), (ins RegI16:$a), "mov.u16\t$d, $a", []>;
>>>   def MOVU32rr
>>> -    : InstPTX<(outs RegI32:$d),  (ins RegI32:$a),  "mov.u32\t$d, $a", []>;
>>> +    : InstPTX<(outs RegI32:$d), (ins RegI32:$a), "mov.u32\t$d, $a", []>;
>>>   def MOVU64rr
>>> -    : InstPTX<(outs RegI64:$d),  (ins RegI64:$a),  "mov.u64\t$d, $a", []>;
>>> +    : InstPTX<(outs RegI64:$d), (ins RegI64:$a), "mov.u64\t$d, $a", []>;
>>>   def MOVF32rr
>>> -    : InstPTX<(outs RegF32:$d),  (ins RegF32:$a),  "mov.f32\t$d, $a", []>;
>>> +    : InstPTX<(outs RegF32:$d), (ins RegF32:$a), "mov.f32\t$d, $a", []>;
>>>   def MOVF64rr
>>> -    : InstPTX<(outs RegF64:$d),  (ins RegF64:$a),  "mov.f64\t$d, $a", []>;
>>> +    : InstPTX<(outs RegF64:$d), (ins RegF64:$a), "mov.f64\t$d, $a", []>;
>>> }
>>> 
>>> let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
>>>   def MOVPREDri
>>>     : InstPTX<(outs RegPred:$d), (ins i1imm:$a), "mov.pred\t$d, $a",
>>>               [(set RegPred:$d, imm:$a)]>;
>>> -  def MOVU8ri
>>> -    : InstPTX<(outs RegI8:$d),  (ins i8imm:$a),  "mov.u8\t$d, $a",
>>> -              [(set RegI8:$d, imm:$a)]>;
>>>   def MOVU16ri
>>>     : InstPTX<(outs RegI16:$d), (ins i16imm:$a), "mov.u16\t$d, $a",
>>>               [(set RegI16:$d, imm:$a)]>;
>>> @@ -845,9 +838,6 @@
>>>   def LDpiPred : InstPTX<(outs RegPred:$d), (ins MEMpi:$a),
>>>                          "ld.param.pred\t$d, [$a]",
>>>                          [(set RegPred:$d, (PTXloadparam timm:$a))]>;
>>> -  def LDpiU8   : InstPTX<(outs RegI8:$d), (ins MEMpi:$a),
>>> -                         "ld.param.u8\t$d, [$a]",
>>> -                         [(set RegI8:$d,  (PTXloadparam timm:$a))]>;
>>>   def LDpiU16  : InstPTX<(outs RegI16:$d), (ins MEMpi:$a),
>>>                          "ld.param.u16\t$d, [$a]",
>>>                          [(set RegI16:$d, (PTXloadparam timm:$a))]>;
>>> @@ -867,9 +857,6 @@
>>>   def STpiPred : InstPTX<(outs), (ins MEMret:$d, RegPred:$a),
>>>                          "st.param.pred\t[$d], $a",
>>>                          [(PTXstoreparam timm:$d, RegPred:$a)]>;
>>> -  def STpiU8   : InstPTX<(outs), (ins MEMret:$d, RegI8:$a),
>>> -                         "st.param.u8\t[$d], $a",
>>> -                         [(PTXstoreparam timm:$d, RegI8:$a)]>;
>>>   def STpiU16  : InstPTX<(outs), (ins MEMret:$d, RegI16:$a),
>>>                          "st.param.u16\t[$d], $a",
>>>                          [(PTXstoreparam timm:$d, RegI16:$a)]>;
>>> @@ -900,62 +887,34 @@
>>> // PTX does not directly support converting to a predicate type, so we fake it
>>> // by performing a greater-than test between the value and zero.  This follows
>>> // the C convention that any non-zero value is equivalent to 'true'.
>>> -def CVT_pred_u8
>>> -  : InstPTX<(outs RegPred:$d), (ins RegI8:$a), "setp.gt.b8\t$d, $a, 0",
>>> -            [(set RegPred:$d, (trunc RegI8:$a))]>;
>>> -
>>> def CVT_pred_u16
>>> -  : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.b16\t$d, $a, 0",
>>> +  : InstPTX<(outs RegPred:$d), (ins RegI16:$a), "setp.gt.u16\t$d, $a, 0",
>>>             [(set RegPred:$d, (trunc RegI16:$a))]>;
>>> 
>>> def CVT_pred_u32
>>> -  : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.b32\t$d, $a, 0",
>>> +  : InstPTX<(outs RegPred:$d), (ins RegI32:$a), "setp.gt.u32\t$d, $a, 0",
>>>             [(set RegPred:$d, (trunc RegI32:$a))]>;
>>> 
>>> def CVT_pred_u64
>>> -  : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.b64\t$d, $a, 0",
>>> +  : InstPTX<(outs RegPred:$d), (ins RegI64:$a), "setp.gt.u64\t$d, $a, 0",
>>>             [(set RegPred:$d, (trunc RegI64:$a))]>;
>>> 
>>> def CVT_pred_f32
>>> -  : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.b32\t$d, $a, 0",
>>> +  : InstPTX<(outs RegPred:$d), (ins RegF32:$a), "setp.gt.f32\t$d, $a, 0",
>>>             [(set RegPred:$d, (fp_to_uint RegF32:$a))]>;
>>> 
>>> def CVT_pred_f64
>>> -  : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.b64\t$d, $a, 0",
>>> +  : InstPTX<(outs RegPred:$d), (ins RegF64:$a), "setp.gt.f64\t$d, $a, 0",
>>>             [(set RegPred:$d, (fp_to_uint RegF64:$a))]>;
>>> 
>>> -// Conversion to u8
>>> -// PTX does not directly support converting a predicate to a value, so we
>>> -// use a select instruction to select either 0 or 1 (integer or fp) based
>>> -// on the truth value of the predicate.
>>> -def CVT_u8_pred
>>> -  : InstPTX<(outs RegI8:$d), (ins RegPred:$a), "selp.u8\t$d, 1, 0, $a",
>>> -            [(set RegI8:$d, (zext RegPred:$a))]>;
>>> -
>>> -def CVT_u8_preds
>>> -  : InstPTX<(outs RegI8:$d), (ins RegPred:$a), "selp.u8\t$d, 1, 0, $a",
>>> -            [(set RegI8:$d, (sext RegPred:$a))]>;
>>> -
>>> -def CVT_u8_u32
>>> -  : InstPTX<(outs RegI8:$d), (ins RegI32:$a), "cvt.u8.u32\t$d, $a",
>>> -            [(set RegI8:$d, (trunc RegI32:$a))]>;
>>> -
>>> -def CVT_u8_u64
>>> -  : InstPTX<(outs RegI8:$d), (ins RegI64:$a), "cvt.u8.u64\t$d, $a",
>>> -            [(set RegI8:$d, (trunc RegI64:$a))]>;
>>> -
>>> -def CVT_u8_f32
>>> -  : InstPTX<(outs RegI8:$d), (ins RegF32:$a), "cvt.rzi.u8.f32\t$d, $a",
>>> -            [(set RegI8:$d, (fp_to_uint RegF32:$a))]>;
>>> -
>>> -def CVT_u8_f64
>>> -  : InstPTX<(outs RegI8:$d), (ins RegF64:$a), "cvt.rzi.u8.f64\t$d, $a",
>>> -            [(set RegI8:$d, (fp_to_uint RegF64:$a))]>;
>>> -
>>> // Conversion to u16
>>> // PTX does not directly support converting a predicate to a value, so we
>>> // use a select instruction to select either 0 or 1 (integer or fp) based
>>> // on the truth value of the predicate.
>>> +def CVT_u16_preda
>>> +  : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
>>> +            [(set RegI16:$d, (anyext RegPred:$a))]>;
>>> +
>>> def CVT_u16_pred
>>>   : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
>>>             [(set RegI16:$d, (zext RegPred:$a))]>;
>>> @@ -964,14 +923,6 @@
>>>   : InstPTX<(outs RegI16:$d), (ins RegPred:$a), "selp.u16\t$d, 1, 0, $a",
>>>             [(set RegI16:$d, (sext RegPred:$a))]>;
>>> 
>>> -def CVT_u16_u8
>>> -  : InstPTX<(outs RegI16:$d), (ins RegI8:$a), "cvt.u16.u8\t$d, $a",
>>> -            [(set RegI16:$d, (zext RegI8:$a))]>;
>>> -
>>> -def CVT_u16_s8
>>> -  : InstPTX<(outs RegI16:$d), (ins RegI8:$a), "cvt.u16.s8\t$d, $a",
>>> -            [(set RegI16:$d, (sext RegI8:$a))]>;
>>> -
>>> def CVT_u16_u32
>>>   : InstPTX<(outs RegI16:$d), (ins RegI32:$a), "cvt.u16.u32\t$d, $a",
>>>             [(set RegI16:$d, (trunc RegI32:$a))]>;
>>> @@ -994,9 +945,9 @@
>>>   : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
>>>             [(set RegI32:$d, (zext RegPred:$a))]>;
>>> 
>>> -def CVT_u32_u8
>>> -  : InstPTX<(outs RegI32:$d), (ins RegI8:$a), "cvt.u32.u8\t$d, $a",
>>> -            [(set RegI32:$d, (zext RegI8:$a))]>;
>>> +def CVT_u32_b16
>>> +  : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
>>> +            [(set RegI32:$d, (anyext RegI16:$a))]>;
>>> 
>>> def CVT_u32_u16
>>>   : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.u16\t$d, $a",
>>> @@ -1006,10 +957,6 @@
>>>   : InstPTX<(outs RegI32:$d), (ins RegPred:$a), "selp.u32\t$d, 1, 0, $a",
>>>             [(set RegI32:$d, (sext RegPred:$a))]>;
>>> 
>>> -def CVT_u32_s8
>>> -  : InstPTX<(outs RegI32:$d), (ins RegI8:$a), "cvt.u32.s8\t$d, $a",
>>> -            [(set RegI32:$d, (zext RegI8:$a))]>;
>>> -
>>> def CVT_u32_s16
>>>   : InstPTX<(outs RegI32:$d), (ins RegI16:$a), "cvt.u32.s16\t$d, $a",
>>>             [(set RegI32:$d, (sext RegI16:$a))]>;
>>> @@ -1032,30 +979,22 @@
>>>   : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
>>>             [(set RegI64:$d, (zext RegPred:$a))]>;
>>> 
>>> -def CVT_u64_u8
>>> -  : InstPTX<(outs RegI64:$d), (ins RegI8:$a), "cvt.u64.u8\t$d, $a",
>>> -            [(set RegI64:$d, (zext RegI8:$a))]>;
>>> -
>>> -def CVT_u64_u16
>>> -  : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
>>> -            [(set RegI64:$d, (zext RegI16:$a))]>;
>>> -
>>> -def CVT_u64_u32
>>> -  : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
>>> -            [(set RegI64:$d, (zext RegI32:$a))]>;
>>> -
>>> def CVT_u64_preds
>>>   : InstPTX<(outs RegI64:$d), (ins RegPred:$a), "selp.u64\t$d, 1, 0, $a",
>>>             [(set RegI64:$d, (sext RegPred:$a))]>;
>>> 
>>> -def CVT_u64_s8
>>> -  : InstPTX<(outs RegI64:$d), (ins RegI8:$a), "cvt.u64.s8\t$d, $a",
>>> -            [(set RegI64:$d, (zext RegI8:$a))]>;
>>> +def CVT_u64_u16
>>> +  : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.u16\t$d, $a",
>>> +            [(set RegI64:$d, (zext RegI16:$a))]>;
>>> 
>>> def CVT_u64_s16
>>>   : InstPTX<(outs RegI64:$d), (ins RegI16:$a), "cvt.u64.s16\t$d, $a",
>>>             [(set RegI64:$d, (sext RegI16:$a))]>;
>>> 
>>> +def CVT_u64_u32
>>> +  : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.u32\t$d, $a",
>>> +            [(set RegI64:$d, (zext RegI32:$a))]>;
>>> +
>>> def CVT_u64_s32
>>>   : InstPTX<(outs RegI64:$d), (ins RegI32:$a), "cvt.u64.s32\t$d, $a",
>>>             [(set RegI64:$d, (sext RegI32:$a))]>;
>>> @@ -1075,10 +1014,6 @@
>>>             "selp.f32\t$d, 0F3F800000, 0F00000000, $a",  // 1.0
>>>             [(set RegF32:$d, (uint_to_fp RegPred:$a))]>;
>>> 
>>> -def CVT_f32_u8
>>> -  : InstPTX<(outs RegF32:$d), (ins RegI8:$a), "cvt.rn.f32.u8\t$d, $a",
>>> -            [(set RegF32:$d, (uint_to_fp RegI8:$a))]>;
>>> -
>>> def CVT_f32_u16
>>>   : InstPTX<(outs RegF32:$d), (ins RegI16:$a), "cvt.rn.f32.u16\t$d, $a",
>>>             [(set RegF32:$d, (uint_to_fp RegI16:$a))]>;
>>> @@ -1102,10 +1037,6 @@
>>>             "selp.f64\t$d, 0D3F80000000000000, 0D0000000000000000, $a",  // 1.0
>>>             [(set RegF64:$d, (uint_to_fp RegPred:$a))]>;
>>> 
>>> -def CVT_f64_u8
>>> -  : InstPTX<(outs RegF64:$d), (ins RegI8:$a), "cvt.rn.f64.u8\t$d, $a",
>>> -            [(set RegF64:$d, (uint_to_fp RegI8:$a))]>;
>>> -
>>> def CVT_f64_u16
>>>   : InstPTX<(outs RegF64:$d), (ins RegI16:$a), "cvt.rn.f64.u16\t$d, $a",
>>>             [(set RegF64:$d, (uint_to_fp RegI16:$a))]>;
>>> @@ -1144,8 +1075,6 @@
>>> 
>>> ///===- Spill Instructions ------------------------------------------------===//
>>> // Special instructions used for stack spilling
>>> -def STACKSTOREI8  : InstPTX<(outs), (ins i32imm:$d, RegI8:$a),
>>> -                            "mov.u8\ts$d, $a", []>;
>>> def STACKSTOREI16 : InstPTX<(outs), (ins i32imm:$d, RegI16:$a),
>>>                             "mov.u16\ts$d, $a", []>;
>>> def STACKSTOREI32 : InstPTX<(outs), (ins i32imm:$d, RegI32:$a),
>>> @@ -1157,8 +1086,6 @@
>>> def STACKSTOREF64 : InstPTX<(outs), (ins i32imm:$d, RegF64:$a),
>>>                             "mov.f64\ts$d, $a", []>;
>>> 
>>> -def STACKLOADI8  : InstPTX<(outs), (ins RegI8:$d, i32imm:$a),
>>> -                           "mov.u8\t$d, s$a", []>;
>>> def STACKLOADI16 : InstPTX<(outs), (ins RegI16:$d, i32imm:$a),
>>>                            "mov.u16\t$d, s$a", []>;
>>> def STACKLOADI32 : InstPTX<(outs), (ins RegI32:$d, i32imm:$a),
>>> 
>>> Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td?rev=133873&r1=133872&r2=133873&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td (original)
>>> +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.td Sat Jun 25 13:16:28 2011
>>> @@ -151,137 +151,6 @@
>>> def P126 : PTXReg<"p126">;
>>> def P127 : PTXReg<"p127">;
>>> 
>>> -///===- 8-Bit Registers --------------------------------------------------===//
>>> -
>>> -def RQ0 : PTXReg<"rq0">;
>>> -def RQ1 : PTXReg<"rq1">;
>>> -def RQ2 : PTXReg<"rq2">;
>>> -def RQ3 : PTXReg<"rq3">;
>>> -def RQ4 : PTXReg<"rq4">;
>>> -def RQ5 : PTXReg<"rq5">;
>>> -def RQ6 : PTXReg<"rq6">;
>>> -def RQ7 : PTXReg<"rq7">;
>>> -def RQ8 : PTXReg<"rq8">;
>>> -def RQ9 : PTXReg<"rq9">;
>>> -def RQ10 : PTXReg<"rq10">;
>>> -def RQ11 : PTXReg<"rq11">;
>>> -def RQ12 : PTXReg<"rq12">;
>>> -def RQ13 : PTXReg<"rq13">;
>>> -def RQ14 : PTXReg<"rq14">;
>>> -def RQ15 : PTXReg<"rq15">;
>>> -def RQ16 : PTXReg<"rq16">;
>>> -def RQ17 : PTXReg<"rq17">;
>>> -def RQ18 : PTXReg<"rq18">;
>>> -def RQ19 : PTXReg<"rq19">;
>>> -def RQ20 : PTXReg<"rq20">;
>>> -def RQ21 : PTXReg<"rq21">;
>>> -def RQ22 : PTXReg<"rq22">;
>>> -def RQ23 : PTXReg<"rq23">;
>>> -def RQ24 : PTXReg<"rq24">;
>>> -def RQ25 : PTXReg<"rq25">;
>>> -def RQ26 : PTXReg<"rq26">;
>>> -def RQ27 : PTXReg<"rq27">;
>>> -def RQ28 : PTXReg<"rq28">;
>>> -def RQ29 : PTXReg<"rq29">;
>>> -def RQ30 : PTXReg<"rq30">;
>>> -def RQ31 : PTXReg<"rq31">;
>>> -def RQ32 : PTXReg<"rq32">;
>>> -def RQ33 : PTXReg<"rq33">;
>>> -def RQ34 : PTXReg<"rq34">;
>>> -def RQ35 : PTXReg<"rq35">;
>>> -def RQ36 : PTXReg<"rq36">;
>>> -def RQ37 : PTXReg<"rq37">;
>>> -def RQ38 : PTXReg<"rq38">;
>>> -def RQ39 : PTXReg<"rq39">;
>>> -def RQ40 : PTXReg<"rq40">;
>>> -def RQ41 : PTXReg<"rq41">;
>>> -def RQ42 : PTXReg<"rq42">;
>>> -def RQ43 : PTXReg<"rq43">;
>>> -def RQ44 : PTXReg<"rq44">;
>>> -def RQ45 : PTXReg<"rq45">;
>>> -def RQ46 : PTXReg<"rq46">;
>>> -def RQ47 : PTXReg<"rq47">;
>>> -def RQ48 : PTXReg<"rq48">;
>>> -def RQ49 : PTXReg<"rq49">;
>>> -def RQ50 : PTXReg<"rq50">;
>>> -def RQ51 : PTXReg<"rq51">;
>>> -def RQ52 : PTXReg<"rq52">;
>>> -def RQ53 : PTXReg<"rq53">;
>>> -def RQ54 : PTXReg<"rq54">;
>>> -def RQ55 : PTXReg<"rq55">;
>>> -def RQ56 : PTXReg<"rq56">;
>>> -def RQ57 : PTXReg<"rq57">;
>>> -def RQ58 : PTXReg<"rq58">;
>>> -def RQ59 : PTXReg<"rq59">;
>>> -def RQ60 : PTXReg<"rq60">;
>>> -def RQ61 : PTXReg<"rq61">;
>>> -def RQ62 : PTXReg<"rq62">;
>>> -def RQ63 : PTXReg<"rq63">;
>>> -def RQ64 : PTXReg<"rq64">;
>>> -def RQ65 : PTXReg<"rq65">;
>>> -def RQ66 : PTXReg<"rq66">;
>>> -def RQ67 : PTXReg<"rq67">;
>>> -def RQ68 : PTXReg<"rq68">;
>>> -def RQ69 : PTXReg<"rq69">;
>>> -def RQ70 : PTXReg<"rq70">;
>>> -def RQ71 : PTXReg<"rq71">;
>>> -def RQ72 : PTXReg<"rq72">;
>>> -def RQ73 : PTXReg<"rq73">;
>>> -def RQ74 : PTXReg<"rq74">;
>>> -def RQ75 : PTXReg<"rq75">;
>>> -def RQ76 : PTXReg<"rq76">;
>>> -def RQ77 : PTXReg<"rq77">;
>>> -def RQ78 : PTXReg<"rq78">;
>>> -def RQ79 : PTXReg<"rq79">;
>>> -def RQ80 : PTXReg<"rq80">;
>>> -def RQ81 : PTXReg<"rq81">;
>>> -def RQ82 : PTXReg<"rq82">;
>>> -def RQ83 : PTXReg<"rq83">;
>>> -def RQ84 : PTXReg<"rq84">;
>>> -def RQ85 : PTXReg<"rq85">;
>>> -def RQ86 : PTXReg<"rq86">;
>>> -def RQ87 : PTXReg<"rq87">;
>>> -def RQ88 : PTXReg<"rq88">;
>>> -def RQ89 : PTXReg<"rq89">;
>>> -def RQ90 : PTXReg<"rq90">;
>>> -def RQ91 : PTXReg<"rq91">;
>>> -def RQ92 : PTXReg<"rq92">;
>>> -def RQ93 : PTXReg<"rq93">;
>>> -def RQ94 : PTXReg<"rq94">;
>>> -def RQ95 : PTXReg<"rq95">;
>>> -def RQ96 : PTXReg<"rq96">;
>>> -def RQ97 : PTXReg<"rq97">;
>>> -def RQ98 : PTXReg<"rq98">;
>>> -def RQ99 : PTXReg<"rq99">;
>>> -def RQ100 : PTXReg<"rq100">;
>>> -def RQ101 : PTXReg<"rq101">;
>>> -def RQ102 : PTXReg<"rq102">;
>>> -def RQ103 : PTXReg<"rq103">;
>>> -def RQ104 : PTXReg<"rq104">;
>>> -def RQ105 : PTXReg<"rq105">;
>>> -def RQ106 : PTXReg<"rq106">;
>>> -def RQ107 : PTXReg<"rq107">;
>>> -def RQ108 : PTXReg<"rq108">;
>>> -def RQ109 : PTXReg<"rq109">;
>>> -def RQ110 : PTXReg<"rq110">;
>>> -def RQ111 : PTXReg<"rq111">;
>>> -def RQ112 : PTXReg<"rq112">;
>>> -def RQ113 : PTXReg<"rq113">;
>>> -def RQ114 : PTXReg<"rq114">;
>>> -def RQ115 : PTXReg<"rq115">;
>>> -def RQ116 : PTXReg<"rq116">;
>>> -def RQ117 : PTXReg<"rq117">;
>>> -def RQ118 : PTXReg<"rq118">;
>>> -def RQ119 : PTXReg<"rq119">;
>>> -def RQ120 : PTXReg<"rq120">;
>>> -def RQ121 : PTXReg<"rq121">;
>>> -def RQ122 : PTXReg<"rq122">;
>>> -def RQ123 : PTXReg<"rq123">;
>>> -def RQ124 : PTXReg<"rq124">;
>>> -def RQ125 : PTXReg<"rq125">;
>>> -def RQ126 : PTXReg<"rq126">;
>>> -def RQ127 : PTXReg<"rq127">;
>>> -
>>> ///===- 16-Bit Registers --------------------------------------------------===//
>>> 
>>> def RH0 : PTXReg<"rh0">;
>>> @@ -679,7 +548,6 @@
>>> //  Register classes
>>> //===----------------------------------------------------------------------===//
>>> def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%u", 0, 127)>;
>>> -def RegI8  : RegisterClass<"PTX", [i8],  8, (sequence "RQ%u", 0, 127)>;
>>> def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%u", 0, 127)>;
>>> def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%u", 0, 127)>;
>>> def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%u", 0, 127)>;
>>> 
>>> Modified: llvm/trunk/lib/Target/PTX/generate-register-td.py
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/generate-register-td.py?rev=133873&r1=133872&r2=133873&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/PTX/generate-register-td.py (original)
>>> +++ llvm/trunk/lib/Target/PTX/generate-register-td.py Sat Jun 25 13:16:28 2011
>>> @@ -15,16 +15,15 @@
>>> from sys import argv, exit, stdout
>>> 
>>> 
>>> -if len(argv) != 6:
>>> -    print('Usage: generate-register-td.py <num_preds> <num_8> <num_16> <num_32> <num_64>')
>>> +if len(argv) != 5:
>>> +    print('Usage: generate-register-td.py <num_preds> <num_16> <num_32> <num_64>')
>>>     exit(1)
>>> 
>>> try:
>>>     num_pred  = int(argv[1])
>>> -    num_8bit  = int(argv[2])
>>> -    num_16bit = int(argv[3])
>>> -    num_32bit = int(argv[4])
>>> -    num_64bit = int(argv[5])
>>> +    num_16bit = int(argv[2])
>>> +    num_32bit = int(argv[3])
>>> +    num_64bit = int(argv[4])
>>> except:
>>>     print('ERROR: Invalid integer parameter')
>>>     exit(1)
>>> @@ -61,11 +60,6 @@
>>> for r in range(0, num_pred):
>>>     td_file.write('def P%d : PTXReg<"p%d">;\n' % (r, r))
>>> 
>>> -# Print 8-bit registers
>>> -td_file.write('\n///===- 8-Bit Registers --------------------------------------------------===//\n\n')
>>> -for r in range(0, num_8bit):
>>> -    td_file.write('def RQ%d : PTXReg<"rq%d">;\n' % (r, r))
>>> -
>>> # Print 16-bit registers
>>> td_file.write('\n///===- 16-Bit Registers --------------------------------------------------===//\n\n')
>>> for r in range(0, num_16bit):
>>> @@ -92,7 +86,6 @@
>>> # Print register classes
>>> 
>>> td_file.write('def RegPred : RegisterClass<"PTX", [i1], 8, (sequence "P%%u", 0, %d)>;\n' % (num_pred-1))
>>> -td_file.write('def RegI8  : RegisterClass<"PTX", [i8],  8, (sequence "RQ%%u", 0, %d)>;\n' % (num_8bit-1))
>>> td_file.write('def RegI16 : RegisterClass<"PTX", [i16], 16, (sequence "RH%%u", 0, %d)>;\n' % (num_16bit-1))
>>> td_file.write('def RegI32 : RegisterClass<"PTX", [i32], 32, (sequence "R%%u", 0, %d)>;\n' % (num_32bit-1))
>>> td_file.write('def RegI64 : RegisterClass<"PTX", [i64], 64, (sequence "RD%%u", 0, %d)>;\n' % (num_64bit-1))
>>> @@ -108,20 +101,16 @@
>>> # Reserve 10% of the available registers for return values, and the other 90%
>>> # for parameters
>>> num_ret_pred    = int(0.1 * num_pred)
>>> -num_ret_8bit    = int(0.1 * num_8bit)
>>> num_ret_16bit   = int(0.1 * num_16bit)
>>> num_ret_32bit   = int(0.1 * num_32bit)
>>> num_ret_64bit   = int(0.1 * num_64bit)
>>> num_param_pred  = num_pred - num_ret_pred
>>> -num_param_8bit = num_8bit - num_ret_8bit
>>> num_param_16bit = num_16bit - num_ret_16bit
>>> num_param_32bit = num_32bit - num_ret_32bit
>>> num_param_64bit = num_64bit - num_ret_64bit
>>> 
>>> param_regs_pred  = [('P%d' % (i+num_ret_pred)) for i in range(0, num_param_pred)]
>>> ret_regs_pred    = ['P%d' % i for i in range(0, num_ret_pred)]
>>> -param_regs_8bit  = [('RQ%d' % (i+num_ret_8bit)) for i in range(0, num_param_8bit)]
>>> -ret_regs_8bit    = ['RQ%d' % i for i in range(0, num_ret_8bit)]
>>> param_regs_16bit = [('RH%d' % (i+num_ret_16bit)) for i in range(0, num_param_16bit)]
>>> ret_regs_16bit   = ['RH%d' % i for i in range(0, num_ret_16bit)]
>>> param_regs_32bit = [('R%d' % (i+num_ret_32bit)) for i in range(0, num_param_32bit)]
>>> @@ -131,8 +120,6 @@
>>> 
>>> param_list_pred  = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_pred)
>>> ret_list_pred    = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_pred)
>>> -param_list_8bit  = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_8bit)
>>> -ret_list_8bit    = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_8bit)
>>> param_list_16bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_16bit)
>>> ret_list_16bit   = reduce(lambda x, y: '%s, %s' % (x, y), ret_regs_16bit)
>>> param_list_32bit = reduce(lambda x, y: '%s, %s' % (x, y), param_regs_32bit)
>>> @@ -157,7 +144,6 @@
>>> // PTX Formal Parameter Calling Convention
>>> def CC_PTX : CallingConv<[
>>>   CCIfType<[i1],      CCAssignToReg<[%s]>>,
>>> -  CCIfType<[i8],      CCAssignToReg<[%s]>>,
>>>   CCIfType<[i16],     CCAssignToReg<[%s]>>,
>>>   CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
>>>   CCIfType<[i64,f64], CCAssignToReg<[%s]>>
>>> @@ -166,13 +152,12 @@
>>> // PTX Return Value Calling Convention
>>> def RetCC_PTX : CallingConv<[
>>>   CCIfType<[i1],      CCAssignToReg<[%s]>>,
>>> -  CCIfType<[i8],      CCAssignToReg<[%s]>>,
>>>   CCIfType<[i16],     CCAssignToReg<[%s]>>,
>>>   CCIfType<[i32,f32], CCAssignToReg<[%s]>>,
>>>   CCIfType<[i64,f64], CCAssignToReg<[%s]>>
>>> ]>;
>>> -''' % (param_list_pred, param_list_8bit, param_list_16bit, param_list_32bit, param_list_64bit,
>>> -       ret_list_pred, ret_list_8bit, ret_list_16bit, ret_list_32bit, ret_list_64bit))
>>> +''' % (param_list_pred, param_list_16bit, param_list_32bit, param_list_64bit,
>>> +       ret_list_pred, ret_list_16bit, ret_list_32bit, ret_list_64bit))
>>> 
>>> 
>>> td_file.close()
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PTX/cvt.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/cvt.ll?rev=133873&r1=133872&r2=133873&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PTX/cvt.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PTX/cvt.ll Sat Jun 25 13:16:28 2011
>>> @@ -3,17 +3,6 @@
>>> ; preds 
>>> ; (note: we convert back to i32 to return)
>>> 
>>> -define ptx_device i32 @cvt_pred_i8(i8 %x, i1 %y) {
>>> -; CHECK: setp.gt.b8 p[[P0:[0-9]+]], rq{{[0-9]+}}, 0
>>> -; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
>>> -; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0:[0-9]+]];
>>> -; CHECK-NEXT: ret;
>>> - %a = trunc i8 %x to i1
>>> - %b = and i1 %a, %y
>>> - %c = zext i1 %b to i32
>>> - ret i32 %c
>>> -}
>>> -
>>> define ptx_device i32 @cvt_pred_i16(i16 %x, i1 %y) {
>>> ; CHECK: setp.gt.b16 p[[P0:[0-9]+]], rh{{[0-9]+}}, 0
>>> ; CHECK-NEXT: and.pred p0, p[[P0:[0-9]+]], p{{[0-9]+}};
>>> @@ -69,43 +58,6 @@
>>>  ret i32 %c
>>> }
>>> 
>>> -; i8
>>> -
>>> -define ptx_device i8 @cvt_i8_preds(i1 %x) {
>>> -; CHECK: selp.u8 rq{{[0-9]+}}, 1, 0, p{{[0-9]+}};
>>> -; CHECK-NEXT: ret;
>>> - %a = zext i1 %x to i8
>>> - ret i8 %a
>>> -}
>>> -
>>> -define ptx_device i8 @cvt_i8_i32(i32 %x) {
>>> -; CHECK: cvt.u8.u32 rq{{[0-9]+}}, r{{[0-9]+}};
>>> -; CHECK-NEXT: ret;
>>> - %a = trunc i32 %x to i8
>>> - ret i8 %a
>>> -}
>>> -
>>> -define ptx_device i8 @cvt_i8_i64(i64 %x) {
>>> -; CHECK: cvt.u8.u64 rq{{[0-9]+}}, rd{{[0-9]+}};
>>> -; CHECK-NEXT: ret;
>>> - %a = trunc i64 %x to i8
>>> - ret i8 %a
>>> -}
>>> -
>>> -define ptx_device i8 @cvt_i8_f32(float %x) {
>>> -; CHECK: cvt.rzi.u8.f32 rq{{[0-9]+}}, r{{[0-9]+}};
>>> -; CHECK-NEXT: ret;
>>> - %a = fptoui float %x to i8
>>> - ret i8 %a
>>> -}
>>> -
>>> -define ptx_device i8 @cvt_i8_f64(double %x) {
>>> -; CHECK: cvt.rzi.u8.f64 rq{{[0-9]+}}, rd{{[0-9]+}};
>>> -; CHECK-NEXT: ret;
>>> - %a = fptoui double %x to i8
>>> - ret i8 %a
>>> -}
>>> -
>>> ; i16
>>> 
>>> define ptx_device i16 @cvt_i16_preds(i1 %x) {
>>> @@ -115,13 +67,6 @@
>>>  ret i16 %a
>>> }
>>> 
>>> -define ptx_device i16 @cvt_i16_i8(i8 %x) {
>>> -; CHECK: cvt.u16.u8 rh{{[0-9]+}}, rq{{[0-9]+}};
>>> -; CHECK-NEXT: ret;
>>> - %a = zext i8 %x to i16
>>> - ret i16 %a
>>> -}
>>> -
>>> define ptx_device i16 @cvt_i16_i32(i32 %x) {
>>> ; CHECK: cvt.u16.u32 rh{{[0-9]+}}, r{{[0-9]+}};
>>> ; CHECK-NEXT: ret;
>>> @@ -159,13 +104,6 @@
>>>  ret i32 %a
>>> }
>>> 
>>> -define ptx_device i32 @cvt_i32_i8(i8 %x) {
>>> -; CHECK: cvt.u32.u8 r{{[0-9]+}}, rq{{[0-9]+}};
>>> -; CHECK-NEXT: ret;
>>> - %a = zext i8 %x to i32
>>> - ret i32 %a
>>> -}
>>> -
>>> define ptx_device i32 @cvt_i32_i16(i16 %x) {
>>> ; CHECK: cvt.u32.u16 r{{[0-9]+}}, rh{{[0-9]+}};
>>> ; CHECK-NEXT: ret;
>>> @@ -203,13 +141,6 @@
>>>  ret i64 %a
>>> }
>>> 
>>> -define ptx_device i64 @cvt_i64_i8(i8 %x) {
>>> -; CHECK: cvt.u64.u8 rd{{[0-9]+}}, rq{{[0-9]+}};
>>> -; CHECK-NEXT: ret;
>>> - %a = zext i8 %x to i64
>>> - ret i64 %a
>>> -}
>>> -
>>> define ptx_device i64 @cvt_i64_i16(i16 %x) {
>>> ; CHECK: cvt.u64.u16 rd{{[0-9]+}}, rh{{[0-9]+}};
>>> ; CHECK-NEXT: ret;
>>> @@ -247,13 +178,6 @@
>>>  ret float %a
>>> }
>>> 
>>> -define ptx_device float @cvt_f32_i8(i8 %x) {
>>> -; CHECK: cvt.rn.f32.u8 r{{[0-9]+}}, rq{{[0-9]+}};
>>> -; CHECK-NEXT: ret;
>>> - %a = uitofp i8 %x to float
>>> - ret float %a
>>> -}
>>> -
>>> define ptx_device float @cvt_f32_i16(i16 %x) {
>>> ; CHECK: cvt.rn.f32.u16 r{{[0-9]+}}, rh{{[0-9]+}};
>>> ; CHECK-NEXT: ret;
>>> @@ -291,13 +215,6 @@
>>>  ret double %a
>>> }
>>> 
>>> -define ptx_device double @cvt_f64_i8(i8 %x) {
>>> -; CHECK: cvt.rn.f64.u8 rd{{[0-9]+}}, rq{{[0-9]+}};
>>> -; CHECK-NEXT: ret;
>>> - %a = uitofp i8 %x to double
>>> - ret double %a
>>> -}
>>> -
>>> define ptx_device double @cvt_f64_i16(i16 %x) {
>>> ; CHECK: cvt.rn.f64.u16 rd{{[0-9]+}}, rh{{[0-9]+}};
>>> ; CHECK-NEXT: ret;
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PTX/ld.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/ld.ll?rev=133873&r1=133872&r2=133873&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PTX/ld.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PTX/ld.ll Sat Jun 25 13:16:28 2011
>>> @@ -1,17 +1,5 @@
>>> ; RUN: llc < %s -march=ptx32 | FileCheck %s
>>> 
>>> -;CHECK: .extern .global .b8 array_i8[10];
>>> - at array_i8 = external global [10 x i8]
>>> -
>>> -;CHECK: .extern .const .b8 array_constant_i8[10];
>>> - at array_constant_i8 = external addrspace(1) constant [10 x i8]
>>> -
>>> -;CHECK: .extern .local .b8 array_local_i8[10];
>>> - at array_local_i8 = external addrspace(2) global [10 x i8]
>>> -
>>> -;CHECK: .extern .shared .b8 array_shared_i8[10];
>>> - at array_shared_i8 = external addrspace(4) global [10 x i8]
>>> -
>>> ;CHECK: .extern .global .b8 array_i16[20];
>>> @array_i16 = external global [10 x i16]
>>> 
>>> @@ -72,13 +60,6 @@
>>> ;CHECK: .extern .shared .b8 array_shared_double[80];
>>> @array_shared_double = external addrspace(4) global [10 x double]
>>> 
>>> -define ptx_device i8 @t1_u8(i8* %p) {
>>> -entry:
>>> -;CHECK: ld.global.u8 rq{{[0-9]+}}, [r{{[0-9]+}}];
>>> -;CHECK-NEXT: ret;
>>> -  %x = load i8* %p
>>> -  ret i8 %x
>>> -}
>>> 
>>> define ptx_device i16 @t1_u16(i16* %p) {
>>> entry:
>>> @@ -120,15 +101,6 @@
>>>   ret double %x
>>> }
>>> 
>>> -define ptx_device i8 @t2_u8(i8* %p) {
>>> -entry:
>>> -;CHECK: ld.global.u8 rq{{[0-9]+}}, [r{{[0-9]+}}+1];
>>> -;CHECK-NEXT: ret;
>>> -  %i = getelementptr i8* %p, i32 1
>>> -  %x = load i8* %i
>>> -  ret i8 %x
>>> -}
>>> -
>>> define ptx_device i16 @t2_u16(i16* %p) {
>>> entry:
>>> ;CHECK: ld.global.u16 rh{{[0-9]+}}, [r{{[0-9]+}}+2];
>>> @@ -174,15 +146,6 @@
>>>   ret double %x
>>> }
>>> 
>>> -define ptx_device i8 @t3_u8(i8* %p, i32 %q) {
>>> -entry:
>>> -;CHECK: add.u32 r[[R0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
>>> -;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]];
>>> -  %i = getelementptr i8* %p, i32 %q
>>> -  %x = load i8* %i
>>> -  ret i8 %x
>>> -}
>>> -
>>> define ptx_device i16 @t3_u16(i16* %p, i32 %q) {
>>> entry:
>>> ;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 1;
>>> @@ -233,16 +196,6 @@
>>>   ret double %x
>>> }
>>> 
>>> -define ptx_device i8 @t4_global_u8() {
>>> -entry:
>>> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
>>> -;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]];
>>> -;CHECK-NEXT: ret;
>>> -  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 0
>>> -  %x = load i8* %i
>>> -  ret i8 %x
>>> -}
>>> -
>>> define ptx_device i16 @t4_global_u16() {
>>> entry:
>>> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
>>> @@ -343,16 +296,6 @@
>>>   ret double %x
>>> }
>>> 
>>> -define ptx_device i8 @t4_local_u8() {
>>> -entry:
>>> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i8;
>>> -;CHECK-NEXT: ld.local.u8 rq{{[0-9]+}}, [r[[R0]]];
>>> -;CHECK-NEXT: ret;
>>> -  %i = getelementptr [10 x i8] addrspace(2)* @array_local_i8, i32 0, i32 0
>>> -  %x = load i8 addrspace(2)* %i
>>> -  ret i8 %x
>>> -}
>>> -
>>> define ptx_device i16 @t4_local_u16() {
>>> entry:
>>> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i16;
>>> @@ -403,16 +346,6 @@
>>>   ret double %x
>>> }
>>> 
>>> -define ptx_device i8 @t4_shared_u8() {
>>> -entry:
>>> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i8;
>>> -;CHECK-NEXT: ld.shared.u8 rq{{[0-9]+}}, [r[[R0]]];
>>> -;CHECK-NEXT: ret;
>>> -  %i = getelementptr [10 x i8] addrspace(4)* @array_shared_i8, i32 0, i32 0
>>> -  %x = load i8 addrspace(4)* %i
>>> -  ret i8 %x
>>> -}
>>> -
>>> define ptx_device i16 @t4_shared_u16() {
>>> entry:
>>> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i16;
>>> @@ -463,16 +396,6 @@
>>>   ret double %x
>>> }
>>> 
>>> -define ptx_device i8 @t5_u8() {
>>> -entry:
>>> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
>>> -;CHECK-NEXT: ld.global.u8 rq{{[0-9]+}}, [r[[R0]]+1];
>>> -;CHECK-NEXT: ret;
>>> -  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 1
>>> -  %x = load i8* %i
>>> -  ret i8 %x
>>> -}
>>> -
>>> define ptx_device i16 @t5_u16() {
>>> entry:
>>> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PTX/mov.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/mov.ll?rev=133873&r1=133872&r2=133873&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PTX/mov.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PTX/mov.ll Sat Jun 25 13:16:28 2011
>>> @@ -1,11 +1,5 @@
>>> ; RUN: llc < %s -march=ptx32 | FileCheck %s
>>> 
>>> -define ptx_device i8 @t1_u8() {
>>> -; CHECK: mov.u8 rq{{[0-9]+}}, 0;
>>> -; CHECK: ret;
>>> - ret i8 0
>>> -}
>>> -
>>> define ptx_device i16 @t1_u16() {
>>> ; CHECK: mov.u16 rh{{[0-9]+}}, 0;
>>> ; CHECK: ret;
>>> @@ -36,12 +30,6 @@
>>>  ret double 0.0
>>> }
>>> 
>>> -define ptx_device i8 @t2_u8(i8 %x) {
>>> -; CHECK: mov.u8 rq{{[0-9]+}}, rq{{[0-9]+}};
>>> -; CHECK: ret;
>>> - ret i8 %x
>>> -}
>>> -
>>> define ptx_device i16 @t2_u16(i16 %x) {
>>> ; CHECK: mov.u16 rh{{[0-9]+}}, rh{{[0-9]+}};
>>> ; CHECK: ret;
>>> 
>>> Modified: llvm/trunk/test/CodeGen/PTX/st.ll
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PTX/st.ll?rev=133873&r1=133872&r2=133873&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/test/CodeGen/PTX/st.ll (original)
>>> +++ llvm/trunk/test/CodeGen/PTX/st.ll Sat Jun 25 13:16:28 2011
>>> @@ -1,17 +1,5 @@
>>> ; RUN: llc < %s -march=ptx32 | FileCheck %s
>>> 
>>> -;CHECK: .extern .global .b8 array_i8[10];
>>> - at array_i8 = external global [10 x i8]
>>> -
>>> -;CHECK: .extern .const .b8 array_constant_i8[10];
>>> - at array_constant_i8 = external addrspace(1) constant [10 x i8]
>>> -
>>> -;CHECK: .extern .local .b8 array_local_i8[10];
>>> - at array_local_i8 = external addrspace(2) global [10 x i8]
>>> -
>>> -;CHECK: .extern .shared .b8 array_shared_i8[10];
>>> - at array_shared_i8 = external addrspace(4) global [10 x i8]
>>> -
>>> ;CHECK: .extern .global .b8 array_i16[20];
>>> @array_i16 = external global [10 x i16]
>>> 
>>> @@ -72,13 +60,6 @@
>>> ;CHECK: .extern .shared .b8 array_shared_double[80];
>>> @array_shared_double = external addrspace(4) global [10 x double]
>>> 
>>> -define ptx_device void @t1_u8(i8* %p, i8 %x) {
>>> -entry:
>>> -;CHECK: st.global.u8 [r{{[0-9]+}}], rq{{[0-9]+}};
>>> -;CHECK-NEXT: ret;
>>> -  store i8 %x, i8* %p
>>> -  ret void
>>> -}
>>> 
>>> define ptx_device void @t1_u16(i16* %p, i16 %x) {
>>> entry:
>>> @@ -120,15 +101,6 @@
>>>   ret void
>>> }
>>> 
>>> -define ptx_device void @t2_u8(i8* %p, i8 %x) {
>>> -entry:
>>> -;CHECK: st.global.u8 [r{{[0-9]+}}+1], rq{{[0-9]+}};
>>> -;CHECK-NEXT: ret;
>>> -  %i = getelementptr i8* %p, i32 1
>>> -  store i8 %x, i8* %i
>>> -  ret void
>>> -}
>>> -
>>> define ptx_device void @t2_u16(i16* %p, i16 %x) {
>>> entry:
>>> ;CHECK: st.global.u16 [r{{[0-9]+}}+2], rh{{[0-9]+}};
>>> @@ -174,16 +146,6 @@
>>>   ret void
>>> }
>>> 
>>> -define ptx_device void @t3_u8(i8* %p, i32 %q, i8 %x) {
>>> -entry:
>>> -;CHECK: add.u32 r[[R0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
>>> -;CHECK-NEXT: st.global.u8 [r[[R0]]], rq{{[0-9]+}};
>>> -;CHECK-NEXT: ret;
>>> -  %i = getelementptr i8* %p, i32 %q
>>> -  store i8 %x, i8* %i
>>> -  ret void
>>> -}
>>> -
>>> define ptx_device void @t3_u16(i16* %p, i32 %q, i16 %x) {
>>> entry:
>>> ;CHECK: shl.b32 r[[R0:[0-9]+]], r{{[0-9]+}}, 1;
>>> @@ -239,16 +201,6 @@
>>>   ret void
>>> }
>>> 
>>> -define ptx_device void @t4_global_u8(i8 %x) {
>>> -entry:
>>> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
>>> -;CHECK-NEXT: st.global.u8 [r[[R0]]], rq{{[0-9]+}};
>>> -;CHECK-NEXT: ret;
>>> -  %i = getelementptr [10 x i8]* @array_i8, i8 0, i8 0
>>> -  store i8 %x, i8* %i
>>> -  ret void
>>> -}
>>> -
>>> define ptx_device void @t4_global_u16(i16 %x) {
>>> entry:
>>> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
>>> @@ -299,16 +251,6 @@
>>>   ret void
>>> }
>>> 
>>> -define ptx_device void @t4_local_u8(i8 %x) {
>>> -entry:
>>> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i8;
>>> -;CHECK-NEXT: st.local.u8 [r[[R0]]], rq{{[0-9]+}};
>>> -;CHECK-NEXT: ret;
>>> -  %i = getelementptr [10 x i8] addrspace(2)* @array_local_i8, i32 0, i32 0
>>> -  store i8 %x, i8 addrspace(2)* %i
>>> -  ret void
>>> -}
>>> -
>>> define ptx_device void @t4_local_u16(i16 %x) {
>>> entry:
>>> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_local_i16;
>>> @@ -359,16 +301,6 @@
>>>   ret void
>>> }
>>> 
>>> -define ptx_device void @t4_shared_u8(i8 %x) {
>>> -entry:
>>> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i8;
>>> -;CHECK-NEXT: st.shared.u8 [r[[R0]]], rq{{[0-9]+}};
>>> -;CHECK-NEXT: ret;
>>> -  %i = getelementptr [10 x i8] addrspace(4)* @array_shared_i8, i32 0, i32 0
>>> -  store i8 %x, i8 addrspace(4)* %i
>>> -  ret void
>>> -}
>>> -
>>> define ptx_device void @t4_shared_u16(i16 %x) {
>>> entry:
>>> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_shared_i16;
>>> @@ -419,16 +351,6 @@
>>>   ret void
>>> }
>>> 
>>> -define ptx_device void @t5_u8(i8 %x) {
>>> -entry:
>>> -;CHECK: mov.u32 r[[R0:[0-9]+]], array_i8;
>>> -;CHECK-NEXT: st.global.u8 [r[[R0]]+1], rq{{[0-9]+}};
>>> -;CHECK-NEXT: ret;
>>> -  %i = getelementptr [10 x i8]* @array_i8, i32 0, i32 1
>>> -  store i8 %x, i8* %i
>>> -  ret void
>>> -}
>>> -
>>> define ptx_device void @t5_u16(i16 %x) {
>>> entry:
>>> ;CHECK: mov.u32 r[[R0:[0-9]+]], array_i16;
>>> 
>>> 
>>> _______________________________________________
>>> llvm-commits mailing list
>>> llvm-commits at cs.uiuc.edu
>>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 

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From x.tong at utoronto.ca  Sun Jun 26 09:52:05 2011
From: x.tong at utoronto.ca (Xin Tong Utoronto)
Date: Sun, 26 Jun 2011 10:52:05 -0400
Subject: [llvm-commits] LLVM JIT Adaptive Compilation Patch
In-Reply-To: <2894FE3F-99D2-4FEC-95FA-5F92B638E907@apple.com>
References: <BANLkTikF-SbCB1F7b9OK7GiM3UhMkaTmqA@mail.gmail.com>
	<2894FE3F-99D2-4FEC-95FA-5F92B638E907@apple.com>
Message-ID: <BANLkTinc2sq6M+h9+=aUf9_9US3B1aKxfA@mail.gmail.com>

Adaptive compilation attempts to detect hot functions in the program and
recompile them at a higher optimization level.  Currently, I have an
adaptive compilation framework ready in LLVM and X86 support for it. I ran
the llvm test-suite with lli -Ox  and lli -adaptive-comp and following is
the result i got on a Intel i5, Ubuntu 32bits machine. Currently, LLVM
adaptive compilation inserts instrumentational code ( invocation counters )
into the function stub and when a function reaches a compilation threshold,
it is recompiled. We would expect adaptive-comp to perform well on large
test cases with hotspots. The benefit of adaptive compilation is not clearly
shown in the llvm test-suite as the test cases are generally small and
short.  Currently the threshold for recompilation is

enum JITReCompCount {
     CompilationNone = 1000,        // Compile at -O0
     CompilationLess = 5000,        // Compile at -O1
     CompilationDefault = 10000,    // Compile at -O2
     CompilationAggressive = 100000 // Compile at -O3
 };

lli -O0
Total Time is 1068.37

lli -O1
Total Time is 1395.68

lli -O2
Total Time is 1394.81

lli -O3
Total Time is 1395.76

lli -adaptive-comp
Total Time is 1119.23


Thanks


Xin



On Fri, Jun 24, 2011 at 2:30 PM, Eric Christopher <echristo at apple.com>wrote:

>
> On Jun 23, 2011, at 7:32 PM, Xin Tong Utoronto wrote:
>
> > One of the current drawbacks of the LLVM JIT is the lack of an adaptive
> compilation system. All the non-adaptive bits are already there in LLVM:
> optimizing compiler with the different types of instruction selectors,
> register allocators, preRA schedulers, etc. and a full set of optimizations
> changeable at runtime. What's left is a system that can keep track of and
> dynamically look-up the hotness of methods and re-compile with more
> expensive optimizations as the methods are executed over and over. This
> should improve program startup time and execution time and will bring great
> benefits to all ported languages that intend to use LLVM JIT as one of the
> execution methods.
> > The implementation of the adaptive compilation framework is one of the
> Google Summer of Code 2011 project (
> http://www.google-melange.com/gsoc/project/google/gsoc2011/timexerox/8001).
> This patch is intended to provide the basic infrastructure for the adaptive
> compilation framework. Code for specific platforms are currently being
> developed. This patch is generate against the LLVM trunk and using GIT.
>
> I realize I've looked at this already, but more eyes would be good. I'll
> also give it a bit more testing shortly.
>
> That said can you provide some more information with this for everyone?
> What tests is gives a performance win on and what tests we can expect to see
> regressions on? Some of the logic behind some of your decisions etc?
>
> Thanks!
>
> -eric
>



-- 
Kind Regards

Xin Tong
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From baldrick at free.fr  Sun Jun 26 14:42:22 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 26 Jun 2011 19:42:22 -0000
Subject: [llvm-commits] [dragonegg] r133885 - in /dragonegg/trunk:
 include/dragonegg/Internals.h src/Convert.cpp
Message-ID: <20110626194222.7597C2A6C12C@llvm.org>

Author: baldrick
Date: Sun Jun 26 14:42:21 2011
New Revision: 133885

URL: http://llvm.org/viewvc/llvm-project?rev=133885&view=rev
Log:
Add support for MEM_REF, a new construct that gcc-4.6 uses all over
the place.

Modified:
    dragonegg/trunk/include/dragonegg/Internals.h
    dragonegg/trunk/src/Convert.cpp

Modified: dragonegg/trunk/include/dragonegg/Internals.h
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Internals.h?rev=133885&r1=133884&r2=133885&view=diff
==============================================================================
--- dragonegg/trunk/include/dragonegg/Internals.h (original)
+++ dragonegg/trunk/include/dragonegg/Internals.h Sun Jun 26 14:42:21 2011
@@ -268,8 +268,11 @@
 /// INT_MAX if there is no such LLVM field.
 int GetFieldIndex(tree_node *decl, const Type *Ty);
 
+/// getIntegerValue - Return the specified INTEGER_CST as an APInt.
+APInt getIntegerValue(tree_node *exp);
+
 /// getINTEGER_CSTVal - Return the specified INTEGER_CST value as a uint64_t.
-///
+/// TODO: Remove this and use getIntegerValue instead.
 uint64_t getINTEGER_CSTVal(tree_node *exp);
 
 /// isInt64 - Return true if t is an INTEGER_CST that fits in a 64 bit integer.
@@ -805,6 +808,9 @@
   LValue EmitLV_COMPONENT_REF(tree_node *exp);
   LValue EmitLV_DECL(tree_node *exp);
   LValue EmitLV_INDIRECT_REF(tree_node *exp);
+#if (GCC_MINOR > 5)
+  LValue EmitLV_MEM_REF(tree_node *exp);
+#endif
 #if (GCC_MINOR < 6)
   LValue EmitLV_MISALIGNED_INDIRECT_REF(tree_node *exp);
 #endif

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=133885&r1=133884&r2=133885&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Sun Jun 26 14:42:21 2011
@@ -80,6 +80,20 @@
 STATISTIC(NumBasicBlocks, "Number of basic blocks converted");
 STATISTIC(NumStatements,  "Number of gimple statements converted");
 
+/// getIntegerValue - Return the specified INTEGER_CST as an APInt.
+APInt getIntegerValue(tree exp) {
+  double_int val = tree_to_double_int(exp);
+  unsigned NumBits = TYPE_PRECISION(TREE_TYPE(exp));
+
+  if (integerPartWidth == HOST_BITS_PER_WIDE_INT)
+    return APInt(NumBits, /*numWords*/2, (integerPart*)&val);
+  assert(integerPartWidth == 2 * HOST_BITS_PER_WIDE_INT &&
+         "Unsupported host integer width!");
+  unsigned ShiftAmt = HOST_BITS_PER_WIDE_INT;
+  integerPart Part = integerPart(val.low) + (integerPart(val.high) << ShiftAmt);
+  return APInt(NumBits, Part);
+}
+
 /// getINTEGER_CSTVal - Return the specified INTEGER_CST value as a uint64_t.
 ///
 uint64_t getINTEGER_CSTVal(tree exp) {
@@ -1286,6 +1300,11 @@
   case SSA_NAME:
     LV = EmitLV_SSA_NAME(exp);
     break;
+#if (GCC_MINOR > 5)
+  case MEM_REF:
+    LV = EmitLV_MEM_REF(exp);
+    break;
+#endif
   case TARGET_MEM_REF:
     LV = EmitLV_TARGET_MEM_REF(exp);
     break;
@@ -5986,6 +6005,29 @@
   return LV;
 }
 
+#if (GCC_MINOR > 5)
+LValue TreeToLLVM::EmitLV_MEM_REF(tree exp) {
+  // The address is the first operand offset in bytes by the second.
+  Value *Addr = EmitRegister(TREE_OPERAND(exp, 0));
+  if (!integer_zerop(TREE_OPERAND(exp, 1))) {
+    // Convert to a byte pointer and displace by the offset.
+    Addr = Builder.CreateBitCast(Addr, GetUnitPointerType(Context));
+    APInt Offset = getIntegerValue(TREE_OPERAND(exp, 1));
+    // The address is always inside the referenced object, so "inbounds".
+    Addr = Builder.CreateInBoundsGEP(Addr, ConstantInt::get(Context, Offset));
+  }
+
+  // Ensure the pointer has the right type.
+  Addr = Builder.CreateBitCast(Addr,
+                               ConvertType(TREE_TYPE(exp))->getPointerTo());
+  unsigned Alignment = std::max(TYPE_ALIGN(TREE_TYPE (exp)),
+                                get_object_alignment(exp, BIGGEST_ALIGNMENT));
+  bool Volatile = TREE_THIS_VOLATILE(exp);
+
+  return LValue(Addr, Alignment / 8, Volatile);
+}
+#endif
+
 #if (GCC_MINOR < 6)
 LValue TreeToLLVM::EmitLV_MISALIGNED_INDIRECT_REF(tree exp) {
   // The lvalue is just the address.  The alignment is given by operand 1.
@@ -8514,6 +8556,9 @@
   case COMPONENT_REF:
   case IMAGPART_EXPR:
   case INDIRECT_REF:
+#if (GCC_MINOR > 5)
+  case MEM_REF:
+#endif
 #if (GCC_MINOR < 6)
   case MISALIGNED_INDIRECT_REF:
 #endif



From rafael.espindola at gmail.com  Sun Jun 26 14:47:37 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Sun, 26 Jun 2011 19:47:37 -0000
Subject: [llvm-commits] [llvm] r133886 - in /llvm/trunk/lib/CodeGen:
 SimpleRegisterCoalescing.cpp SimpleRegisterCoalescing.h
Message-ID: <20110626194737.14E2E2A6C12C@llvm.org>

Author: rafael
Date: Sun Jun 26 14:47:36 2011
New Revision: 133886

URL: http://llvm.org/viewvc/llvm-project?rev=133886&view=rev
Log:
Remove unnecessary wrapper.

Modified:
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp?rev=133886&r1=133885&r2=133886&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp Sun Jun 26 14:47:36 2011
@@ -839,8 +839,7 @@
 /// if the copy was successfully coalesced away. If it is not currently
 /// possible to coalesce this interval, but it may be possible if other
 /// things get coalesced, then it returns true by reference in 'Again'.
-bool SimpleRegisterCoalescing::JoinCopy(CopyRec &TheCopy, bool &Again) {
-  MachineInstr *CopyMI = TheCopy.MI;
+bool SimpleRegisterCoalescing::JoinCopy(MachineInstr *CopyMI, bool &Again) {
 
   Again = false;
   if (JoinedCopies.count(CopyMI) || ReMatCopies.count(CopyMI))
@@ -1268,12 +1267,12 @@
 }
 
 void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
-                                               std::vector<CopyRec> &TryAgain) {
+                                            std::vector<MachineInstr*> &TryAgain) {
   DEBUG(dbgs() << MBB->getName() << ":\n");
 
-  SmallVector<CopyRec, 8> VirtCopies;
-  SmallVector<CopyRec, 8> PhysCopies;
-  SmallVector<CopyRec, 8> ImpDefCopies;
+  SmallVector<MachineInstr*, 8> VirtCopies;
+  SmallVector<MachineInstr*, 8> PhysCopies;
+  SmallVector<MachineInstr*, 8> ImpDefCopies;
   for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
        MII != E;) {
     MachineInstr *Inst = MII++;
@@ -1292,32 +1291,32 @@
     bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
     bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
     if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
-      ImpDefCopies.push_back(CopyRec(Inst, 0));
+      ImpDefCopies.push_back(Inst);
     else if (SrcIsPhys || DstIsPhys)
-      PhysCopies.push_back(CopyRec(Inst, 0));
+      PhysCopies.push_back(Inst);
     else
-      VirtCopies.push_back(CopyRec(Inst, 0));
+      VirtCopies.push_back(Inst);
   }
 
   // Try coalescing implicit copies and insert_subreg <undef> first,
   // followed by copies to / from physical registers, then finally copies
   // from virtual registers to virtual registers.
   for (unsigned i = 0, e = ImpDefCopies.size(); i != e; ++i) {
-    CopyRec &TheCopy = ImpDefCopies[i];
+    MachineInstr *TheCopy = ImpDefCopies[i];
     bool Again = false;
     if (!JoinCopy(TheCopy, Again))
       if (Again)
         TryAgain.push_back(TheCopy);
   }
   for (unsigned i = 0, e = PhysCopies.size(); i != e; ++i) {
-    CopyRec &TheCopy = PhysCopies[i];
+    MachineInstr *TheCopy = PhysCopies[i];
     bool Again = false;
     if (!JoinCopy(TheCopy, Again))
       if (Again)
         TryAgain.push_back(TheCopy);
   }
   for (unsigned i = 0, e = VirtCopies.size(); i != e; ++i) {
-    CopyRec &TheCopy = VirtCopies[i];
+    MachineInstr *TheCopy = VirtCopies[i];
     bool Again = false;
     if (!JoinCopy(TheCopy, Again))
       if (Again)
@@ -1328,7 +1327,7 @@
 void SimpleRegisterCoalescing::joinIntervals() {
   DEBUG(dbgs() << "********** JOINING INTERVALS ***********\n");
 
-  std::vector<CopyRec> TryAgainList;
+  std::vector<MachineInstr*> TryAgainList;
   if (loopInfo->empty()) {
     // If there are no loops in the function, join intervals in function order.
     for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
@@ -1362,14 +1361,14 @@
     ProgressMade = false;
 
     for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
-      CopyRec &TheCopy = TryAgainList[i];
-      if (!TheCopy.MI)
+      MachineInstr *&TheCopy = TryAgainList[i];
+      if (!TheCopy)
         continue;
 
       bool Again = false;
       bool Success = JoinCopy(TheCopy, Again);
       if (Success || !Again) {
-        TheCopy.MI = 0;   // Mark this one as done.
+        TheCopy= 0;   // Mark this one as done.
         ProgressMade = true;
       }
     }

Modified: llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h?rev=133886&r1=133885&r2=133886&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h (original)
+++ llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h Sun Jun 26 14:47:36 2011
@@ -27,15 +27,6 @@
   class VirtRegMap;
   class MachineLoopInfo;
 
-  /// CopyRec - Representation for copy instructions in coalescer queue.
-  ///
-  struct CopyRec {
-    MachineInstr *MI;
-    unsigned LoopDepth;
-    CopyRec(MachineInstr *mi, unsigned depth)
-      : MI(mi), LoopDepth(depth) {}
-  };
-
   class SimpleRegisterCoalescing : public MachineFunctionPass,
                                    public RegisterCoalescer {
     MachineFunction* mf_;
@@ -88,14 +79,14 @@
     /// CopyCoalesceInMBB - Coalesce copies in the specified MBB, putting
     /// copies that cannot yet be coalesced into the "TryAgain" list.
     void CopyCoalesceInMBB(MachineBasicBlock *MBB,
-                           std::vector<CopyRec> &TryAgain);
+                           std::vector<MachineInstr*> &TryAgain);
 
     /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
     /// which are the src/dst of the copy instruction CopyMI.  This returns true
     /// if the copy was successfully coalesced away. If it is not currently
     /// possible to coalesce this interval, but it may be possible if other
     /// things get coalesced, then it returns true by reference in 'Again'.
-    bool JoinCopy(CopyRec &TheCopy, bool &Again);
+    bool JoinCopy(MachineInstr *TheCopy, bool &Again);
 
     /// JoinIntervals - Attempt to join these two intervals.  On failure, this
     /// returns false.  The output "SrcInt" will not have been modified, so we can



From baldrick at free.fr  Sun Jun 26 15:14:11 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 26 Jun 2011 20:14:11 -0000
Subject: [llvm-commits] [dragonegg] r133887 -
	/dragonegg/trunk/src/x86/Target.cpp
Message-ID: <20110626201411.5CF032A6C12C@llvm.org>

Author: baldrick
Date: Sun Jun 26 15:14:11 2011
New Revision: 133887

URL: http://llvm.org/viewvc/llvm-project?rev=133887&view=rev
Log:
Remove some pointless namespace qualifiers.

Modified:
    dragonegg/trunk/src/x86/Target.cpp

Modified: dragonegg/trunk/src/x86/Target.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/x86/Target.cpp?rev=133887&r1=133886&r2=133887&view=diff
==============================================================================
--- dragonegg/trunk/src/x86/Target.cpp (original)
+++ dragonegg/trunk/src/x86/Target.cpp Sun Jun 26 15:14:11 2011
@@ -661,9 +661,9 @@
       // If palignr is shifting the pair of input vectors less than 9 bytes,
       // emit a shuffle instruction.
       if (shiftVal <= 8) {
-        const llvm::Type *IntTy = Type::getInt32Ty(Context);
-        const llvm::Type *EltTy = Type::getInt8Ty(Context);
-        const llvm::Type *VecTy = VectorType::get(EltTy, 8);
+        const Type *IntTy = Type::getInt32Ty(Context);
+        const Type *EltTy = Type::getInt8Ty(Context);
+        const Type *VecTy = VectorType::get(EltTy, 8);
 
         Ops[1] = Builder.CreateBitCast(Ops[1], VecTy);
         Ops[0] = Builder.CreateBitCast(Ops[0], VecTy);
@@ -681,8 +681,8 @@
       // than 16 bytes, emit a logical right shift of the destination.
       if (shiftVal < 16) {
         // MMX has these as 1 x i64 vectors for some odd optimization reasons.
-        const llvm::Type *EltTy = Type::getInt64Ty(Context);
-        const llvm::Type *VecTy = VectorType::get(EltTy, 1);
+        const Type *EltTy = Type::getInt64Ty(Context);
+        const Type *VecTy = VectorType::get(EltTy, 1);
 
         Ops[0] = Builder.CreateBitCast(Ops[0], VecTy, "cast");
         Ops[1] = ConstantInt::get(VecTy, (shiftVal-8) * 8);
@@ -713,14 +713,14 @@
       // If palignr is shifting the pair of input vectors less than 17 bytes,
       // emit a shuffle instruction.
       if (shiftVal <= 16) {
-        const llvm::Type *IntTy = Type::getInt32Ty(Context);
-        const llvm::Type *EltTy = Type::getInt8Ty(Context);
-        const llvm::Type *VecTy = VectorType::get(EltTy, 16);
+        const Type *IntTy = Type::getInt32Ty(Context);
+        const Type *EltTy = Type::getInt8Ty(Context);
+        const Type *VecTy = VectorType::get(EltTy, 16);
 
         Ops[1] = Builder.CreateBitCast(Ops[1], VecTy);
         Ops[0] = Builder.CreateBitCast(Ops[0], VecTy);
 
-        llvm::SmallVector<Constant*, 16> Indices;
+        SmallVector<Constant*, 16> Indices;
         for (unsigned i = 0; i != 16; ++i)
           Indices.push_back(ConstantInt::get(IntTy, shiftVal + i));
 
@@ -732,16 +732,16 @@
       // If palignr is shifting the pair of input vectors more than 16 but less
       // than 32 bytes, emit a logical right shift of the destination.
       if (shiftVal < 32) {
-        const llvm::Type *EltTy = Type::getInt64Ty(Context);
-        const llvm::Type *VecTy = VectorType::get(EltTy, 2);
-        const llvm::Type *IntTy = Type::getInt32Ty(Context);
+        const Type *EltTy = Type::getInt64Ty(Context);
+        const Type *VecTy = VectorType::get(EltTy, 2);
+        const Type *IntTy = Type::getInt32Ty(Context);
 
         Ops[0] = Builder.CreateBitCast(Ops[0], VecTy, "cast");
         Ops[1] = ConstantInt::get(IntTy, (shiftVal-16) * 8);
 
         // create i32 constant
-        llvm::Function *F = Intrinsic::getDeclaration(TheModule,
-                                                  Intrinsic::x86_sse2_psrl_dq);
+        Function *F = Intrinsic::getDeclaration(TheModule,
+                                                Intrinsic::x86_sse2_psrl_dq);
         Result = Builder.CreateCall(F, &Ops[0], &Ops[0] + 2, "palignr");
         return true;
       }
@@ -1551,10 +1551,10 @@
                                                bool isVolatile) {
   Value *EVI = Builder.CreateExtractValue(Src, SrcFieldNo, "mrv_gr");
   const StructType *STy = cast<StructType>(Src->getType());
-  llvm::Value *Idxs[3];
-  Idxs[0] = ConstantInt::get(llvm::Type::getInt32Ty(Context), 0);
-  Idxs[1] = ConstantInt::get(llvm::Type::getInt32Ty(Context), DestFieldNo);
-  Idxs[2] = ConstantInt::get(llvm::Type::getInt32Ty(Context), DestElemNo);
+  Value *Idxs[3];
+  Idxs[0] = ConstantInt::get(Type::getInt32Ty(Context), 0);
+  Idxs[1] = ConstantInt::get(Type::getInt32Ty(Context), DestFieldNo);
+  Idxs[2] = ConstantInt::get(Type::getInt32Ty(Context), DestElemNo);
   Value *GEP = Builder.CreateGEP(Dest, Idxs, Idxs+3, "mrv_gep");
   if (STy->getElementType(SrcFieldNo)->isVectorTy()) {
     Value *ElemIndex = ConstantInt::get(Type::getInt32Ty(Context), SrcElemNo);
@@ -1621,17 +1621,17 @@
 
     // Special treatement for _Complex.
     if (DestElemType->isStructTy()) {
-      llvm::Value *Idxs[3];
-      Idxs[0] = ConstantInt::get(llvm::Type::getInt32Ty(Context), 0);
-      Idxs[1] = ConstantInt::get(llvm::Type::getInt32Ty(Context), DNO);
+      Value *Idxs[3];
+      Idxs[0] = ConstantInt::get(Type::getInt32Ty(Context), 0);
+      Idxs[1] = ConstantInt::get(Type::getInt32Ty(Context), DNO);
 
-      Idxs[2] = ConstantInt::get(llvm::Type::getInt32Ty(Context), 0);
+      Idxs[2] = ConstantInt::get(Type::getInt32Ty(Context), 0);
       Value *GEP = Builder.CreateGEP(Dest, Idxs, Idxs+3, "mrv_gep");
       Value *EVI = Builder.CreateExtractValue(Src, 0, "mrv_gr");
       Builder.CreateStore(EVI, GEP, isVolatile);
       ++SNO;
 
-      Idxs[2] = ConstantInt::get(llvm::Type::getInt32Ty(Context), 1);
+      Idxs[2] = ConstantInt::get(Type::getInt32Ty(Context), 1);
       GEP = Builder.CreateGEP(Dest, Idxs, Idxs+3, "mrv_gep");
       EVI = Builder.CreateExtractValue(Src, 1, "mrv_gr");
       Builder.CreateStore(EVI, GEP, isVolatile);



From baldrick at free.fr  Sun Jun 26 15:14:34 2011
From: baldrick at free.fr (Duncan Sands)
Date: Sun, 26 Jun 2011 20:14:34 -0000
Subject: [llvm-commits] [dragonegg] r133888 -
	/dragonegg/trunk/src/Convert.cpp
Message-ID: <20110626201434.9EF532A6C12C@llvm.org>

Author: baldrick
Date: Sun Jun 26 15:14:34 2011
New Revision: 133888

URL: http://llvm.org/viewvc/llvm-project?rev=133888&view=rev
Log:
Turn some uses of std::vector into SmallVector.

Modified:
    dragonegg/trunk/src/Convert.cpp

Modified: dragonegg/trunk/src/Convert.cpp
URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=133888&r1=133887&r2=133888&view=diff
==============================================================================
--- dragonegg/trunk/src/Convert.cpp (original)
+++ dragonegg/trunk/src/Convert.cpp Sun Jun 26 15:14:34 2011
@@ -3659,7 +3659,7 @@
 
   // If this is a constant vector, create a ConstantVector.
   if (AllConstants) {
-    std::vector<Constant*> CstOps;
+    SmallVector<Constant*, 16> CstOps;
     for (unsigned i = 0, e = Ops.size(); i != e; ++i)
       CstOps.push_back(cast<Constant>(Ops[i]));
     return ConstantVector::get(CstOps);
@@ -3704,7 +3704,7 @@
   unsigned NumElements = cast<VectorType>(InVec1->getType())->getNumElements();
 
   // Get all the indexes from varargs.
-  std::vector<Constant*> Idxs;
+  SmallVector<Constant*, 16> Idxs;
   va_list VA;
   va_start(VA, InVec2);
   for (unsigned i = 0; i != NumElements; ++i) {
@@ -6346,7 +6346,7 @@
     return getDefaultValue(getRegType(TREE_TYPE(reg)));
 
   // Convert the elements.
-  SmallVector<Constant*, 8> Elts;
+  SmallVector<Constant*, 16> Elts;
   const IntegerType *IntTy = getTargetData().getIntPtrType(Context);
   for (tree elt = TREE_VECTOR_CST_ELTS(reg); elt; elt = TREE_CHAIN(elt)) {
     Constant *Elt = EmitRegisterConstant(TREE_VALUE(elt));



From rafael.espindola at gmail.com  Sun Jun 26 16:41:06 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Sun, 26 Jun 2011 21:41:06 -0000
Subject: [llvm-commits] [llvm] r133895 - in /llvm/trunk:
 include/llvm/CodeGen/RegisterCoalescer.h lib/CodeGen/PreAllocSplitting.cpp
 lib/CodeGen/RegAllocBasic.cpp lib/CodeGen/RegAllocGreedy.cpp
 lib/CodeGen/RegAllocLinearScan.cpp lib/CodeGen/RegAllocPBQP.cpp
 lib/CodeGen/RegisterCoalescer.cpp lib/CodeGen/RegisterCoalescer.h
 lib/CodeGen/SimpleRegisterCoalescing.cpp
 lib/CodeGen/SimpleRegisterCoalescing.h
Message-ID: <20110626214106.8A6092A6C12C@llvm.org>

Author: rafael
Date: Sun Jun 26 16:41:06 2011
New Revision: 133895

URL: http://llvm.org/viewvc/llvm-project?rev=133895&view=rev
Log:
Move RegisterCoalescer.h to lib/CodeGen.

Added:
    llvm/trunk/lib/CodeGen/RegisterCoalescer.h
      - copied, changed from r133886, llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h
Removed:
    llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h
Modified:
    llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp
    llvm/trunk/lib/CodeGen/RegAllocBasic.cpp
    llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp
    llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp
    llvm/trunk/lib/CodeGen/RegAllocPBQP.cpp
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.cpp
    llvm/trunk/lib/CodeGen/SimpleRegisterCoalescing.h

Removed: llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h?rev=133894&view=auto
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h (original)
+++ llvm/trunk/include/llvm/CodeGen/RegisterCoalescer.h (removed)
@@ -1,244 +0,0 @@
-//===-- RegisterCoalescer.h - Register Coalescing Interface ------*- C++ -*-===//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the abstract interface for register coalescers, 
-// allowing them to interact with and query register allocators.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/Support/IncludeFile.h"
-#include "llvm/CodeGen/LiveInterval.h"
-#include "llvm/ADT/SmallPtrSet.h"
-
-#ifndef LLVM_CODEGEN_REGISTER_COALESCER_H
-#define LLVM_CODEGEN_REGISTER_COALESCER_H
-
-namespace llvm {
-
-  class MachineFunction;
-  class RegallocQuery;
-  class AnalysisUsage;
-  class MachineInstr;
-  class TargetRegisterInfo;
-  class TargetRegisterClass;
-  class TargetInstrInfo;
-
-  /// An abstract interface for register coalescers.  Coalescers must
-  /// implement this interface to be part of the coalescer analysis
-  /// group.
-  class RegisterCoalescer {
-  public:
-    static char ID; // Class identification, replacement for typeinfo
-    RegisterCoalescer() {}
-    virtual ~RegisterCoalescer();  // We want to be subclassed
-
-    /// Run the coalescer on this function, providing interference
-    /// data to query.  Return whether we removed any copies.
-    virtual bool coalesceFunction(MachineFunction &mf,
-                                  RegallocQuery &ifd) = 0;
-
-    /// Reset state.  Can be used to allow a coalescer run by
-    /// PassManager to be run again by the register allocator.
-    virtual void reset(MachineFunction &mf) {}
-
-    /// Register allocators must call this from their own
-    /// getAnalysisUsage to cover the case where the coalescer is not
-    /// a Pass in the proper sense and isn't managed by PassManager.
-    /// PassManager needs to know which analyses to make available and
-    /// which to invalidate when running the register allocator or any
-    /// pass that might call coalescing.  The long-term solution is to
-    /// allow hierarchies of PassManagers.
-    virtual void getAnalysisUsage(AnalysisUsage &AU) const {}
-  }; 
-
-  /// An abstract interface for register allocators to interact with
-  /// coalescers
-  ///
-  /// Example:
-  ///
-  /// This is simply an example of how to use the RegallocQuery
-  /// interface.  It is not meant to be used in production.
-  ///
-  ///   class LinearScanRegallocQuery : public RegallocQuery {
-  ///   private:
-  ///     const LiveIntervals \&li;
-  ///
-  ///   public:
-  ///     LinearScanRegallocQuery(LiveIntervals &intervals) 
-  ///         : li(intervals) {}
-  ///
-  ///     /// This is pretty slow and conservative, but since linear scan
-  ///     /// allocation doesn't pre-compute interference information it's
-  ///     /// the best we can do.  Coalescers are always free to ignore this
-  ///     /// and implement their own discovery strategy.  See
-  ///     /// SimpleRegisterCoalescing for an example.
-  ///     void getInterferences(IntervalSet &interferences,
-  ///                           const LiveInterval &a) const {
-  ///       for(LiveIntervals::const_iterator iv = li.begin(),
-  ///             ivend = li.end();
-  ///           iv != ivend;
-  ///           ++iv) {
-  ///         if (interfere(a, iv->second)) {
-  ///           interferences.insert(&iv->second);
-  ///         }
-  ///       }
-  ///     }
-  ///
-  ///     /// This is *really* slow and stupid.  See above.
-  ///     int getNumberOfInterferences(const LiveInterval &a) const {
-  ///       IntervalSet intervals;
-  ///       getInterferences(intervals, a);
-  ///       return intervals.size();
-  ///     }
-  ///   };  
-  ///
-  ///   In the allocator:
-  ///
-  ///   RegisterCoalescer &coalescer = getAnalysis<RegisterCoalescer>();
-  ///
-  ///   // We don't reset the coalescer so if it's already been run this
-  ///   // takes almost no time.
-  ///   LinearScanRegallocQuery ifd(*li_);
-  ///   coalescer.coalesceFunction(fn, ifd);
-  ///
-  class RegallocQuery {
-  public:
-    typedef SmallPtrSet<const LiveInterval *, 8> IntervalSet;
-
-    virtual ~RegallocQuery() {}
-    
-    /// Return whether two live ranges interfere.
-    virtual bool interfere(const LiveInterval &a,
-                           const LiveInterval &b) const {
-      // A naive test
-      return a.overlaps(b);
-    }
-
-    /// Return the set of intervals that interfere with this one.
-    virtual void getInterferences(IntervalSet &interferences,
-                                  const LiveInterval &a) const = 0;
-
-    /// This can often be cheaper than actually returning the
-    /// interferences.
-    virtual int getNumberOfInterferences(const LiveInterval &a) const = 0;
-
-    /// Make any data structure updates necessary to reflect
-    /// coalescing or other modifications.
-    virtual void updateDataForMerge(const LiveInterval &a,
-                                    const LiveInterval &b,
-                                    const MachineInstr &copy) {}
-
-    /// Allow the register allocator to communicate when it doesn't
-    /// want a copy coalesced.  This may be due to assumptions made by
-    /// the allocator about various invariants and so this question is
-    /// a matter of legality, no