From nicholas at mxc.ca Mon Jun 27 00:40:02 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 27 Jun 2011 05:40:02 -0000 Subject: [llvm-commits] [llvm] r133905 - in /llvm/trunk: lib/Transforms/Scalar/ScalarReplAggregates.cpp test/Transforms/ScalarRepl/memcpy-from-global.ll Message-ID: <20110627054002.9D97E2A6C12C@llvm.org> Author: nicholas Date: Mon Jun 27 00:40:02 2011 New Revision: 133905 URL: http://llvm.org/viewvc/llvm-project?rev=133905&view=rev Log: Teach one piece of scalarrepl to handle lifetime markers. When transforming an alloca that only holds a copy of a global and we're going to replace the users of the alloca with that global, just nuke the lifetime intrinsics. Part of PR10121. Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp llvm/trunk/test/Transforms/ScalarRepl/memcpy-from-global.ll Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=133905&r1=133904&r2=133905&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Mon Jun 27 00:40:02 2011 @@ -152,7 +152,8 @@ void RewriteLoadUserOfWholeAlloca(LoadInst *LI, AllocaInst *AI, SmallVector &NewElts); - static MemTransferInst *isOnlyCopiedFromConstantGlobal(AllocaInst *AI); + static MemTransferInst *isOnlyCopiedFromConstantGlobal( + AllocaInst *AI, SmallVector &ToDelete); }; // SROA_DT - SROA that uses DominatorTree. @@ -1443,8 +1444,8 @@ // performScalarRepl - This algorithm is a simple worklist driven algorithm, -// which runs on all of the malloc/alloca instructions in the function, removing -// them if they are only used by getelementptr instructions. +// which runs on all of the alloca instructions in the function, removing them +// if they are only used by getelementptr instructions. // bool SROA::performScalarRepl(Function &F) { std::vector WorkList; @@ -1478,12 +1479,15 @@ // the constant global instead. This is commonly produced by the CFE by // constructs like "void foo() { int A[] = {1,2,3,4,5,6,7,8,9...}; }" if 'A' // is only subsequently read. - if (MemTransferInst *TheCopy = isOnlyCopiedFromConstantGlobal(AI)) { + SmallVector ToDelete; + if (MemTransferInst *Copy = isOnlyCopiedFromConstantGlobal(AI, ToDelete)) { DEBUG(dbgs() << "Found alloca equal to global: " << *AI << '\n'); - DEBUG(dbgs() << " memcpy = " << *TheCopy << '\n'); - Constant *TheSrc = cast(TheCopy->getSource()); + DEBUG(dbgs() << " memcpy = " << *Copy << '\n'); + for (unsigned i = 0, e = ToDelete.size(); i != e; ++i) + ToDelete[i]->eraseFromParent(); + Constant *TheSrc = cast(Copy->getSource()); AI->replaceAllUsesWith(ConstantExpr::getBitCast(TheSrc, AI->getType())); - TheCopy->eraseFromParent(); // Don't mutate the global. + Copy->eraseFromParent(); // Don't mutate the global. AI->eraseFromParent(); ++NumGlobals; Changed = true; @@ -2507,8 +2511,14 @@ /// the uses. If we see a memcpy/memmove that targets an unoffseted pointer to /// the alloca, and if the source pointer is a pointer to a constant global, we /// can optimize this. -static bool isOnlyCopiedFromConstantGlobal(Value *V, MemTransferInst *&TheCopy, - bool isOffset) { +static bool +isOnlyCopiedFromConstantGlobal(Value *V, MemTransferInst *&TheCopy, + bool isOffset, + SmallVector &LifetimeMarkers) { + // We track lifetime intrinsics as we encounter them. If we decide to go + // ahead and replace the value with the global, this lets the caller quickly + // eliminate the markers. + for (Value::use_iterator UI = V->use_begin(), E = V->use_end(); UI!=E; ++UI) { User *U = cast(*UI); @@ -2520,7 +2530,8 @@ if (BitCastInst *BCI = dyn_cast(U)) { // If uses of the bitcast are ok, we are ok. - if (!isOnlyCopiedFromConstantGlobal(BCI, TheCopy, isOffset)) + if (!isOnlyCopiedFromConstantGlobal(BCI, TheCopy, isOffset, + LifetimeMarkers)) return false; continue; } @@ -2528,7 +2539,8 @@ // If the GEP has all zero indices, it doesn't offset the pointer. If it // doesn't, it does. if (!isOnlyCopiedFromConstantGlobal(GEP, TheCopy, - isOffset || !GEP->hasAllZeroIndices())) + isOffset || !GEP->hasAllZeroIndices(), + LifetimeMarkers)) return false; continue; } @@ -2554,6 +2566,16 @@ continue; } + // Lifetime intrinsics can be handled by the caller. + if (IntrinsicInst *II = dyn_cast(U)) { + if (II->getIntrinsicID() == Intrinsic::lifetime_start || + II->getIntrinsicID() == Intrinsic::lifetime_end) { + assert(II->use_empty() && "Lifetime markers have no result to use!"); + LifetimeMarkers.push_back(II); + continue; + } + } + // If this is isn't our memcpy/memmove, reject it as something we can't // handle. MemTransferInst *MI = dyn_cast(U); @@ -2590,9 +2612,11 @@ /// isOnlyCopiedFromConstantGlobal - Return true if the specified alloca is only /// modified by a copy from a constant global. If we can prove this, we can /// replace any uses of the alloca with uses of the global directly. -MemTransferInst *SROA::isOnlyCopiedFromConstantGlobal(AllocaInst *AI) { +MemTransferInst * +SROA::isOnlyCopiedFromConstantGlobal(AllocaInst *AI, + SmallVector &ToDelete) { MemTransferInst *TheCopy = 0; - if (::isOnlyCopiedFromConstantGlobal(AI, TheCopy, false)) + if (::isOnlyCopiedFromConstantGlobal(AI, TheCopy, false, ToDelete)) return TheCopy; return 0; } Modified: llvm/trunk/test/Transforms/ScalarRepl/memcpy-from-global.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/ScalarRepl/memcpy-from-global.ll?rev=133905&r1=133904&r2=133905&view=diff ============================================================================== --- llvm/trunk/test/Transforms/ScalarRepl/memcpy-from-global.ll (original) +++ llvm/trunk/test/Transforms/ScalarRepl/memcpy-from-global.ll Mon Jun 27 00:40:02 2011 @@ -93,4 +93,18 @@ ret void } +declare void @llvm.lifetime.start(i64, i8*) +define void @test5() { + %A = alloca %T + %a = bitcast %T* %A to i8* + call void @llvm.lifetime.start(i64 -1, i8* %a) + call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* bitcast (%T* @G to i8*), i64 124, i32 4, i1 false) + call void @baz(i8* byval %a) +; CHECK: @test5 +; CHECK-NEXT: %a = bitcast %T* @G to i8* +; CHECK-NEXT: call void @baz(i8* byval %a) + ret void +} + + declare void @baz(i8* byval) From jay.foad at gmail.com Mon Jun 27 03:10:13 2011 From: jay.foad at gmail.com (Jay Foad) Date: Mon, 27 Jun 2011 09:10:13 +0100 Subject: [llvm-commits] [llvm] r133708 - in /llvm/trunk: include/llvm/ include/llvm/Support/ lib/MC/ lib/Target/CppBackend/ lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/ In-Reply-To: References: <20110623090916.87EFD2A6C12C@llvm.org> Message-ID: On 27 June 2011 00:57, Francois Pichet wrote: > On Thu, Jun 23, 2011 at 5:09 AM, Jay Foad wrote: >> Author: foad >> Date: Thu Jun 23 04:09:15 2011 >> New Revision: 133708 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=133708&view=rev >> Log: >> Reinstate r133513 (reverted in r133700) with an additional fix for a >> -Wshorten-64-to-32 warning in Instructions.h. > > Hi Jay, This commit creates a very weird problem on MSVC where clang > test /CodeGen/vla.c stalls in release mode. (but not in debug). > > I suspect a subtle memory corruption issue that doesn't show up on the > various unixes system because we get lucky. Windows .exe are generally > easier to crash if there is a memory corruption issue. Hi Francois, I've tried running that test under valgrind on Linux, but it doesn't show anything. I'll try building on Windows. What version of MSVC are you using? 32 or 64 bit? Do you do a Release or Release+Asserts build? Do you use cmake? Thanks, Jay. From geek4civic at gmail.com Mon Jun 27 04:39:13 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Mon, 27 Jun 2011 18:39:13 +0900 Subject: [llvm-commits] [llvm] r133708 - in /llvm/trunk: include/llvm/ include/llvm/Support/ lib/MC/ lib/Target/CppBackend/ lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/ In-Reply-To: References: <20110623090916.87EFD2A6C12C@llvm.org> Message-ID: 2011/6/27 Jay Foad : > I'll try building on Windows. What version of MSVC are you using? 32 > or 64 bit? Do you do a Release or Release+Asserts build? Do you use > cmake? FYI, I am using, Visual Studio 10 SP1 (Japanese), Release build. From pichet2000 at gmail.com Mon Jun 27 08:14:38 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Mon, 27 Jun 2011 09:14:38 -0400 Subject: [llvm-commits] [llvm] r133708 - in /llvm/trunk: include/llvm/ include/llvm/Support/ lib/MC/ lib/Target/CppBackend/ lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/ In-Reply-To: References: <20110623090916.87EFD2A6C12C@llvm.org> Message-ID: On Mon, Jun 27, 2011 at 4:10 AM, Jay Foad wrote: > On 27 June 2011 00:57, Francois Pichet wrote: >> On Thu, Jun 23, 2011 at 5:09 AM, Jay Foad wrote: >>> Author: foad >>> Date: Thu Jun 23 04:09:15 2011 >>> New Revision: 133708 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=133708&view=rev >>> Log: >>> Reinstate r133513 (reverted in r133700) with an additional fix for a >>> -Wshorten-64-to-32 warning in Instructions.h. >> >> Hi Jay, This commit creates a very weird problem on MSVC where clang >> test /CodeGen/vla.c stalls in release mode. (but not in debug). >> >> I suspect a subtle memory corruption issue that doesn't show up on the >> various unixes system because we get lucky. Windows .exe are generally >> easier to crash if there is a memory corruption issue. > > Hi Francois, > > I've tried running that test under valgrind on Linux, but it doesn't > show anything. > > I'll try building on Windows. What version of MSVC are you using? 32 > or 64 bit? Do you do a Release or Release+Asserts build? Do you use > cmake? > I can reproduce the problem with MSVC2010 SP1 and MSVC 2008. Targeting win32, Release without assert, with cmake. (cmake is mandatory if you use MSVC). on msvc 2010 CodeGen/vla.c is stuck on msvc 2008 CodeGenObjC/arc.m If I run the tests from the command line instead of from VisualStudio I get a different test who is stuck but the failing test is always within clang/test/CodeGen*/* You have to run all the tests to get the failure. Individual run will pass. From baldrick at free.fr Mon Jun 27 08:52:25 2011 From: baldrick at free.fr (Duncan Sands) Date: Mon, 27 Jun 2011 13:52:25 -0000 Subject: [llvm-commits] [dragonegg] r133908 - in /dragonegg/trunk: include/dragonegg/Internals.h include/dragonegg/Trees.h src/Backend.cpp src/Convert.cpp src/Debug.cpp src/Trees.cpp Message-ID: <20110627135225.E45B42A6C12C@llvm.org> Author: baldrick Date: Mon Jun 27 08:52:25 2011 New Revision: 133908 URL: http://llvm.org/viewvc/llvm-project?rev=133908&view=rev Log: Remove getINTEGER_CSTVal, which was not used much, in favour of getInt64. This required some changes to the debug info logic, which are hopefully correct... Move getIntegerValue and friends into Trees.cpp. Modified: dragonegg/trunk/include/dragonegg/Internals.h dragonegg/trunk/include/dragonegg/Trees.h dragonegg/trunk/src/Backend.cpp dragonegg/trunk/src/Convert.cpp dragonegg/trunk/src/Debug.cpp dragonegg/trunk/src/Trees.cpp Modified: dragonegg/trunk/include/dragonegg/Internals.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Internals.h?rev=133908&r1=133907&r2=133908&view=diff ============================================================================== --- dragonegg/trunk/include/dragonegg/Internals.h (original) +++ dragonegg/trunk/include/dragonegg/Internals.h Mon Jun 27 08:52:25 2011 @@ -268,25 +268,6 @@ /// INT_MAX if there is no such LLVM field. int GetFieldIndex(tree_node *decl, const Type *Ty); -/// getIntegerValue - Return the specified INTEGER_CST as an APInt. -APInt getIntegerValue(tree_node *exp); - -/// getINTEGER_CSTVal - Return the specified INTEGER_CST value as a uint64_t. -/// TODO: Remove this and use getIntegerValue instead. -uint64_t getINTEGER_CSTVal(tree_node *exp); - -/// isInt64 - Return true if t is an INTEGER_CST that fits in a 64 bit integer. -/// If Unsigned is false, returns whether it fits in a int64_t. If Unsigned is -/// true, returns whether the value is non-negative and fits in a uint64_t. -/// Always returns false for overflowed constants or if t is NULL. -bool isInt64(tree_node *t, bool Unsigned); - -/// getInt64 - Extract the value of an INTEGER_CST as a 64 bit integer. If -/// Unsigned is false, the value must fit in a int64_t. If Unsigned is true, -/// the value must be non-negative and fit in a uint64_t. Must not be used on -/// overflowed constants. These conditions can be checked by calling isInt64. -uint64_t getInt64(tree_node *t, bool Unsigned); - /// isPassedByInvisibleReference - Return true if the specified type should be /// passed by 'invisible reference'. In other words, instead of passing the /// thing by value, pass the address of a temporary. Modified: dragonegg/trunk/include/dragonegg/Trees.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Trees.h?rev=133908&r1=133907&r2=133908&view=diff ============================================================================== --- dragonegg/trunk/include/dragonegg/Trees.h (original) +++ dragonegg/trunk/include/dragonegg/Trees.h Mon Jun 27 08:52:25 2011 @@ -23,6 +23,9 @@ #ifndef DRAGONEGG_TREES_H #define DRAGONEGG_TREES_H +// LLVM headers +#include "llvm/ADT/APInt.h" + // System headers #include @@ -41,4 +44,19 @@ /// in undefined behaviour. bool hasNSW(tree_node *type); +/// getIntegerValue - Return the specified INTEGER_CST as an APInt. +llvm::APInt getIntegerValue(tree_node *exp); + +/// isInt64 - Return true if t is an INTEGER_CST that fits in a 64 bit integer. +/// If Unsigned is false, returns whether it fits in a int64_t. If Unsigned is +/// true, returns whether the value is non-negative and fits in a uint64_t. +/// Always returns false for overflowed constants or if t is NULL. +bool isInt64(tree_node *t, bool Unsigned); + +/// getInt64 - Extract the value of an INTEGER_CST as a 64 bit integer. If +/// Unsigned is false, the value must fit in a int64_t. If Unsigned is true, +/// the value must be non-negative and fit in a uint64_t. Must not be used on +/// overflowed constants. These conditions can be checked by calling isInt64. +uint64_t getInt64(tree_node *t, bool Unsigned); + #endif /* DRAGONEGG_TREES_H */ Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=133908&r1=133907&r2=133908&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Mon Jun 27 08:52:25 2011 @@ -29,6 +29,7 @@ #include "dragonegg/Debug.h" #include "dragonegg/OS.h" #include "dragonegg/Target.h" +#include "dragonegg/Trees.h" // LLVM headers #define DEBUG_TYPE "plugin" Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=133908&r1=133907&r2=133908&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Mon Jun 27 08:52:25 2011 @@ -80,64 +80,6 @@ STATISTIC(NumBasicBlocks, "Number of basic blocks converted"); STATISTIC(NumStatements, "Number of gimple statements converted"); -/// getIntegerValue - Return the specified INTEGER_CST as an APInt. -APInt getIntegerValue(tree exp) { - double_int val = tree_to_double_int(exp); - unsigned NumBits = TYPE_PRECISION(TREE_TYPE(exp)); - - if (integerPartWidth == HOST_BITS_PER_WIDE_INT) - return APInt(NumBits, /*numWords*/2, (integerPart*)&val); - assert(integerPartWidth == 2 * HOST_BITS_PER_WIDE_INT && - "Unsupported host integer width!"); - unsigned ShiftAmt = HOST_BITS_PER_WIDE_INT; - integerPart Part = integerPart(val.low) + (integerPart(val.high) << ShiftAmt); - return APInt(NumBits, Part); -} - -/// getINTEGER_CSTVal - Return the specified INTEGER_CST value as a uint64_t. -/// -uint64_t getINTEGER_CSTVal(tree exp) { - unsigned HOST_WIDE_INT LO = (unsigned HOST_WIDE_INT)TREE_INT_CST_LOW(exp); - if (HOST_BITS_PER_WIDE_INT == 64) { - return (uint64_t)LO; - } else { - assert(HOST_BITS_PER_WIDE_INT == 32 && - "Only 32- and 64-bit hosts supported!"); - unsigned HOST_WIDE_INT HI = (unsigned HOST_WIDE_INT)TREE_INT_CST_HIGH(exp); - return ((uint64_t)HI << 32) | (uint64_t)LO; - } -} - -/// isInt64 - Return true if t is an INTEGER_CST that fits in a 64 bit integer. -/// If Unsigned is false, returns whether it fits in a int64_t. If Unsigned is -/// true, returns whether the value is non-negative and fits in a uint64_t. -/// Always returns false for overflowed constants. -bool isInt64(tree t, bool Unsigned) { - if (!t) - return false; - if (HOST_BITS_PER_WIDE_INT == 64) - return host_integerp(t, Unsigned) && !TREE_OVERFLOW (t); - assert(HOST_BITS_PER_WIDE_INT == 32 && - "Only 32- and 64-bit hosts supported!"); - return - (TREE_CODE (t) == INTEGER_CST && !TREE_OVERFLOW (t)) - && ((TYPE_UNSIGNED(TREE_TYPE(t)) == Unsigned) || - // If the constant is signed and we want an unsigned result, check - // that the value is non-negative. If the constant is unsigned and - // we want a signed result, check it fits in 63 bits. - (HOST_WIDE_INT)TREE_INT_CST_HIGH(t) >= 0); -} - -/// getInt64 - Extract the value of an INTEGER_CST as a 64 bit integer. If -/// Unsigned is false, the value must fit in a int64_t. If Unsigned is true, -/// the value must be non-negative and fit in a uint64_t. Must not be used on -/// overflowed constants. These conditions can be checked by calling isInt64. -uint64_t getInt64(tree t, bool Unsigned) { - assert(isInt64(t, Unsigned) && "invalid constant!"); - (void)Unsigned; // Otherwise unused if asserts off - avoid compiler warning. - return getINTEGER_CSTVal(t); -} - /// getPointerAlignment - Return the alignment in bytes of exp, a pointer valued /// expression, or 1 if the alignment is not known. static unsigned int getPointerAlignment(tree exp) { Modified: dragonegg/trunk/src/Debug.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Debug.cpp?rev=133908&r1=133907&r2=133908&view=diff ============================================================================== --- dragonegg/trunk/src/Debug.cpp (original) +++ dragonegg/trunk/src/Debug.cpp Mon Jun 27 08:52:25 2011 @@ -23,6 +23,7 @@ // Plugin headers #include "dragonegg/Debug.h" +#include "dragonegg/Trees.h" // LLVM headers #include "llvm/Module.h" @@ -89,15 +90,15 @@ } else if (TYPE_P(Node)) { if (TYPE_SIZE(Node) == NULL_TREE) return 0; - else if (isInt64(TYPE_SIZE(Node), 1)) - return getINTEGER_CSTVal(TYPE_SIZE(Node)); + else if (isInt64(TYPE_SIZE(Node), true)) + return getInt64(TYPE_SIZE(Node), true); else return TYPE_ALIGN(Node); } else if (DECL_P(Node)) { if (DECL_SIZE(Node) == NULL_TREE) return 0; else if (isInt64(DECL_SIZE(Node), 1)) - return getINTEGER_CSTVal(DECL_SIZE(Node)); + return getInt64(DECL_SIZE(Node), 1); else return DECL_ALIGN(Node); } @@ -635,12 +636,12 @@ // FIXME - handle dynamic ranges tree MinValue = TYPE_MIN_VALUE(Domain); tree MaxValue = TYPE_MAX_VALUE(Domain); - uint64_t Low = 0; - uint64_t Hi = 0; + int64_t Low = 0; + int64_t Hi = 0; if (isInt64(MinValue, false)) - Low = getINTEGER_CSTVal(MinValue); + Low = getInt64(MinValue, false); if (isInt64(MaxValue, false)) - Hi = getINTEGER_CSTVal(MaxValue); + Hi = getInt64(MaxValue, false); Subscripts.push_back(DebugFactory.GetOrCreateSubrange(Low, Hi)); } EltTy = TREE_TYPE(atype); @@ -674,7 +675,7 @@ tree EnumValue = TREE_VALUE(Link); if (TREE_CODE(EnumValue) == CONST_DECL) EnumValue = DECL_INITIAL(EnumValue); - int64_t Value = getINTEGER_CSTVal(EnumValue); + int64_t Value = getInt64(EnumValue, false); const char *EnumName = IDENTIFIER_POINTER(TREE_PURPOSE(Link)); Elements.push_back(DebugFactory.CreateEnumerator(EnumName, Value)); } @@ -793,10 +794,10 @@ // Check for zero BINFO_OFFSET. // FIXME : Is this correct ? unsigned Offset = BINFO_OFFSET(BInfo) ? - getINTEGER_CSTVal(BINFO_OFFSET(BInfo))*8 : 0; + getInt64(BINFO_OFFSET(BInfo), true)*8 : 0; if (BINFO_VIRTUAL_P (BInfo)) - Offset = 0 - getINTEGER_CSTVal(BINFO_VPTR_FIELD (BInfo)); + Offset = 0 - getInt64(BINFO_VPTR_FIELD (BInfo), false); // FIXME : name, size, align etc... DIType DTy = DebugFactory.CreateDerivedType(DW_TAG_inheritance, Modified: dragonegg/trunk/src/Trees.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Trees.cpp?rev=133908&r1=133907&r2=133908&view=diff ============================================================================== --- dragonegg/trunk/src/Trees.cpp (original) +++ dragonegg/trunk/src/Trees.cpp Mon Jun 27 08:52:25 2011 @@ -141,3 +141,55 @@ bool hasNSW(tree type) { return !TYPE_UNSIGNED(type) && !TYPE_OVERFLOW_WRAPS(type); } + +/// getIntegerValue - Return the specified INTEGER_CST as an APInt. +APInt getIntegerValue(tree exp) { + double_int val = tree_to_double_int(exp); + unsigned NumBits = TYPE_PRECISION(TREE_TYPE(exp)); + + if (integerPartWidth == HOST_BITS_PER_WIDE_INT) + return APInt(NumBits, /*numWords*/2, (integerPart*)&val); + assert(integerPartWidth == 2 * HOST_BITS_PER_WIDE_INT && + "Unsupported host integer width!"); + unsigned ShiftAmt = HOST_BITS_PER_WIDE_INT; + integerPart Part = integerPart(val.low) + (integerPart(val.high) << ShiftAmt); + return APInt(NumBits, Part); +} + +/// isInt64 - Return true if t is an INTEGER_CST that fits in a 64 bit integer. +/// If Unsigned is false, returns whether it fits in a int64_t. If Unsigned is +/// true, returns whether the value is non-negative and fits in a uint64_t. +/// Always returns false for overflowed constants. +bool isInt64(tree t, bool Unsigned) { + if (!t) + return false; + if (HOST_BITS_PER_WIDE_INT == 64) + return host_integerp(t, Unsigned) && !TREE_OVERFLOW (t); + assert(HOST_BITS_PER_WIDE_INT == 32 && + "Only 32- and 64-bit hosts supported!"); + return + (TREE_CODE (t) == INTEGER_CST && !TREE_OVERFLOW (t)) + && ((TYPE_UNSIGNED(TREE_TYPE(t)) == Unsigned) || + // If the constant is signed and we want an unsigned result, check + // that the value is non-negative. If the constant is unsigned and + // we want a signed result, check it fits in 63 bits. + (HOST_WIDE_INT)TREE_INT_CST_HIGH(t) >= 0); +} + +/// getInt64 - Extract the value of an INTEGER_CST as a 64 bit integer. If +/// Unsigned is false, the value must fit in a int64_t. If Unsigned is true, +/// the value must be non-negative and fit in a uint64_t. Must not be used on +/// overflowed constants. These conditions can be checked by calling isInt64. +uint64_t getInt64(tree t, bool Unsigned) { + assert(isInt64(t, Unsigned) && "invalid constant!"); + (void)Unsigned; // Otherwise unused if asserts off - avoid compiler warning. + unsigned HOST_WIDE_INT LO = (unsigned HOST_WIDE_INT)TREE_INT_CST_LOW(t); + if (HOST_BITS_PER_WIDE_INT == 64) { + return (uint64_t)LO; + } else { + assert(HOST_BITS_PER_WIDE_INT == 32 && + "Only 32- and 64-bit hosts supported!"); + unsigned HOST_WIDE_INT HI = (unsigned HOST_WIDE_INT)TREE_INT_CST_HIGH(t); + return ((uint64_t)HI << 32) | (uint64_t)LO; + } +} From stoklund at 2pi.dk Mon Jun 27 10:00:36 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 27 Jun 2011 15:00:36 -0000 Subject: [llvm-commits] [llvm] r133910 - /llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp Message-ID: <20110627150036.4F29B2A6C12C@llvm.org> Author: stoklund Date: Mon Jun 27 10:00:36 2011 New Revision: 133910 URL: http://llvm.org/viewvc/llvm-project?rev=133910&view=rev Log: Track live-out physical registers in MachineDCE. Patch by Sanjoy Das! Modified: llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp Modified: llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp?rev=133910&r1=133909&r2=133910&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp (original) +++ llvm/trunk/lib/CodeGen/DeadMachineInstructionElim.cpp Mon Jun 27 10:00:36 2011 @@ -110,9 +110,14 @@ LivePhysRegs.set(Reg); } - // FIXME: Add live-ins from sucessors to LivePhysRegs. Normally, physregs - // are not live across blocks, but some targets (x86) can have flags live - // out of a block. + // Add live-ins from sucessors to LivePhysRegs. Normally, physregs are not + // live across blocks, but some targets (x86) can have flags live out of a + // block. + for (MachineBasicBlock::succ_iterator S = MBB->succ_begin(), + E = MBB->succ_end(); S != E; S++) + for (MachineBasicBlock::livein_iterator LI = (*S)->livein_begin(); + LI != (*S)->livein_end(); LI++) + LivePhysRegs.set(*LI); // Now scan the instructions and delete dead ones, tracking physreg // liveness as we go. From sanjoy at playingwithpointers.com Mon Jun 27 09:23:45 2011 From: sanjoy at playingwithpointers.com (Sanjoy Das) Date: Mon, 27 Jun 2011 19:53:45 +0530 Subject: [llvm-commits] Segmented stacks, current status. Message-ID: <4E089271.40607@playingwithpointers.com> Hi! I am a GSoC student, working on implementing segmented stacks for LLVM. I have attached a set of patches that add preliminary support for segmented stacks and variable length allocas for review. The code is also available on Github [1]. The code, in the current state, does not support varargs. Thanks! [1] https://github.com/sanjoy/llvm/tree/segmented-stacks -- Sanjoy Das http://playingwithpointers.com -------------- next part -------------- A non-text attachment was scrubbed... Name: 0001-Adds-a-command-line-option-to-enable-segmented-stack.patch Type: text/x-diff Size: 1623 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110627/811245f9/attachment.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0002-Adds-a-StackSegmenter-pass.patch Type: text/x-diff Size: 6933 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110627/811245f9/attachment-0001.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0003-Implements-prologue-code-emission-for-X86.patch Type: text/x-diff Size: 10023 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110627/811245f9/attachment-0002.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0004-Adds-a-new-SelectionDAG-node-two-pseudo-instructions.patch Type: text/x-diff Size: 4352 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110627/811245f9/attachment-0003.bin -------------- next part -------------- A non-text attachment was scrubbed... Name: 0005-Adds-support-for-variable-sized-allocas.patch Type: text/x-diff Size: 9432 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110627/811245f9/attachment-0004.bin From anton at korobeynikov.info Mon Jun 27 10:10:58 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Mon, 27 Jun 2011 19:10:58 +0400 Subject: [llvm-commits] Segmented stacks, current status. In-Reply-To: <4E089271.40607@playingwithpointers.com> References: <4E089271.40607@playingwithpointers.com> Message-ID: Hello Sanjoy, > I am a GSoC student, working on implementing segmented stacks for LLVM. > I have attached a set of patches that add preliminary support for > segmented stacks and variable length allocas for review. I did only quick scan over the patches (I'm planning to review them later), but this hunk looks really suspicious: + TlsReg = X86::FS; + TlsOffset = 0x70; + ... + } else { + TlsReg = X86::GS; + TlsOffset = 0x30; Are you sure this will work on all subtargets we support? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From rdivacky at freebsd.org Mon Jun 27 12:00:07 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Mon, 27 Jun 2011 19:00:07 +0200 Subject: [llvm-commits] [PATCH]: ppc32 va_arg() implementation In-Reply-To: <20110614194727.GA84755@freebsd.org> References: <20110614194727.GA84755@freebsd.org> Message-ID: <20110627170007.GA93136@freebsd.org> Now with a test case, the testcase tests i32 (uses gpr_index). f32 (uses fpr_index) and i64 (uses aligned gpr_index). OK to commit? On Tue, Jun 14, 2011 at 09:47:27PM +0200, Roman Divacky wrote: > Hi, > > the attached patch implements va_arg() lowering on ppc32. > Ints (8, 16, 32 and also 64 bits that need special treatment) work, > floats don't work (neither with gcc - we should warn when someone tries > to use them on ppc32 probably), doubles do work. Both passing via > register_save_area and overflow_area works. > > I tried with stuff like > > foo(1, 7, 0xf00ba4cafeLL, 3.0f, 2, 4, 5, (6LL << 32) + 5LL, 7, 8, 9, 10, 11, 0); > bar(1, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 0.0); > > I'll have some test cases soon too. > > This only works at -O0 because of unrelated bugs in the PowerPC backend. > > Comments? > > roman > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- ; RUN: llc -O0 < %s | FileCheck %s ;ModuleID = 'test.c' target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" target triple = "powerpc-unknown-freebsd9.0" %struct.__va_list_tag = type { i8, i8, i16, i8*, i8* } @var1 = common global i64 0, align 8 @var2 = common global double 0.0, align 8 @var3 = common global i32 0, align 4 define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind { entry: %x = va_arg %struct.__va_list_tag* %ap, i64; Get from r5,r6 ; CHECK: lbz 4, 0(3) ; CHECK-NEXT: lwz 5, 4(3) ; CHECK-NEXT: rlwinm 6, 4, 0, 31, 31 ; CHECK-NEXT: cmplwi 0, 6, 0 ; CHECK-NEXT: addi 6, 4, 1 ; CHECK-NEXT: stw 3, -4(1) ; CHECK-NEXT: stw 6, -8(1) ; CHECK-NEXT: stw 4, -12(1) ; CHECK-NEXT: stw 5, -16(1) ; CHECK-NEXT: bne 0, .LBB0_2 ; CHECK-NEXT: # BB#1: # %entry ; CHECK-NEXT: lwz 3, -12(1) ; CHECK-NEXT: stw 3, -8(1) ; CHECK-NEXT: .LBB0_2: # %entry ; CHECK-NEXT: lwz 3, -8(1) ; CHECK-NEXT: lwz 4, -4(1) ; CHECK-NEXT: lwz 5, 8(4) ; CHECK-NEXT: slwi 6, 3, 2 ; CHECK-NEXT: addi 7, 3, 2 ; CHECK-NEXT: cmpwi 0, 3, 8 ; CHECK-NEXT: lwz 3, -16(1) ; CHECK-NEXT: addi 8, 3, 4 ; CHECK-NEXT: add 5, 5, 6 ; CHECK-NEXT: mfcr 0 # cr0 ; CHECK-NEXT: stw 0, -20(1) ; CHECK-NEXT: stw 5, -24(1) ; CHECK-NEXT: stw 3, -28(1) ; CHECK-NEXT: stw 7, -32(1) ; CHECK-NEXT: stw 8, -36(1) ; CHECK-NEXT: blt 0, .LBB0_4 ; CHECK-NEXT: # BB#3: # %entry ; CHECK-NEXT: lwz 3, -36(1) ; CHECK-NEXT: stw 3, -28(1) ; CHECK-NEXT: .LBB0_4: # %entry ; CHECK-NEXT: lwz 3, -28(1) ; CHECK-NEXT: lwz 4, -32(1) ; CHECK-NEXT: lwz 5, -4(1) ; CHECK-NEXT: stb 4, 0(5) ; CHECK-NEXT: lwz 4, -24(1) ; CHECK-NEXT: lwz 0, -20(1) ; CHECK-NEXT: mtcrf 128, 0 ; CHECK-NEXT: stw 3, -40(1) ; CHECK-NEXT: stw 4, -44(1) ; CHECK-NEXT: blt 0, .LBB0_6 ; CHECK-NEXT: # BB#5: # %entry ; CHECK-NEXT: lwz 3, -16(1) ; CHECK-NEXT: stw 3, -44(1) ; CHECK-NEXT: .LBB0_6: # %entry ; CHECK-NEXT: lwz 3, -44(1) ; CHECK-NEXT: lwz 4, -40(1) ; CHECK-NEXT: lwz 5, -4(1) ; CHECK-NEXT: stw 4, 4(5) store i64 %x, i64* @var1, align 8 ; CHECK-NEXT: lis 4, var1 at ha ; CHECK-NEXT: lwz 6, 4(3) ; CHECK-NEXT: lwz 3, 0(3) ; CHECK-NEXT: la 7, var1 at l(4) ; CHECK-NEXT: stw 3, var1 at l(4) ; CHECK-NEXT: stw 6, 4(7) %y = va_arg %struct.__va_list_tag* %ap, double; From f1 ; CHECK-NEXT: lbz 3, 1(5) ; CHECK-NEXT: lwz 4, 4(5) ; CHECK-NEXT: lwz 6, 8(5) ; CHECK-NEXT: slwi 7, 3, 3 ; CHECK-NEXT: add 6, 6, 7 ; CHECK-NEXT: addi 7, 3, 1 ; CHECK-NEXT: cmpwi 0, 3, 8 ; CHECK-NEXT: addi 3, 4, 8 ; CHECK-NEXT: addi 6, 6, 32 ; CHECK-NEXT: mr 8, 4 ; CHECK-NEXT: mfcr 0 # cr0 ; CHECK-NEXT: stw 0, -48(1) ; CHECK-NEXT: stw 4, -52(1) ; CHECK-NEXT: stw 6, -56(1) ; CHECK-NEXT: stw 7, -60(1) ; CHECK-NEXT: stw 3, -64(1) ; CHECK-NEXT: stw 8, -68(1) ; CHECK-NEXT: blt 0, .LBB0_8 ; CHECK-NEXT: # BB#7: # %entry ; CHECK-NEXT: lwz 3, -64(1) ; CHECK-NEXT: stw 3, -68(1) ; CHECK-NEXT: .LBB0_8: # %entry ; CHECK-NEXT: lwz 3, -68(1) ; CHECK-NEXT: lwz 4, -60(1) ; CHECK-NEXT: lwz 5, -4(1) ; CHECK-NEXT: stb 4, 1(5) ; CHECK-NEXT: lwz 4, -56(1) ; CHECK-NEXT: lwz 0, -48(1) ; CHECK-NEXT: mtcrf 128, 0 ; CHECK-NEXT: stw 4, -72(1) ; CHECK-NEXT: stw 3, -76(1) ; CHECK-NEXT: blt 0, .LBB0_10 ; CHECK-NEXT: # BB#9: # %entry ; CHECK-NEXT: lwz 3, -52(1) ; CHECK-NEXT: stw 3, -72(1) ; CHECK-NEXT: .LBB0_10: # %entry ; CHECK-NEXT: lwz 3, -72(1) ; CHECK-NEXT: lwz 4, -76(1) ; CHECK-NEXT: lwz 5, -4(1) ; CHECK-NEXT: stw 4, 4(5) ; CHECK-NEXT: lfd 0, 0(3) store double %y, double* @var2, align 8 ; CHECK-NEXT: lis 3, var2 at ha ; CHECK-NEXT: stfd 0, var2 at l(3) %z = va_arg %struct.__va_list_tag* %ap, i32; From r7 ; CHECK-NEXT: lbz 3, 0(5) ; CHECK-NEXT: lwz 4, 4(5) ; CHECK-NEXT: lwz 6, 8(5) ; CHECK-NEXT: slwi 7, 3, 2 ; CHECK-NEXT: addi 8, 3, 1 ; CHECK-NEXT: cmpwi 0, 3, 8 ; CHECK-NEXT: addi 3, 4, 4 ; CHECK-NEXT: add 6, 6, 7 ; CHECK-NEXT: mr 7, 4 ; CHECK-NEXT: stw 6, -80(1) ; CHECK-NEXT: stw 8, -84(1) ; CHECK-NEXT: stw 3, -88(1) ; CHECK-NEXT: stw 4, -92(1) ; CHECK-NEXT: stw 7, -96(1) ; CHECK-NEXT: mfcr 0 # cr0 ; CHECK-NEXT: stw 0, -100(1) ; CHECK-NEXT: blt 0, .LBB0_12 ; CHECK-NEXT: # BB#11: # %entry ; CHECK-NEXT: lwz 3, -88(1) ; CHECK-NEXT: stw 3, -96(1) ; CHECK-NEXT: .LBB0_12: # %entry ; CHECK-NEXT: lwz 3, -96(1) ; CHECK-NEXT: lwz 4, -84(1) ; CHECK-NEXT: lwz 5, -4(1) ; CHECK-NEXT: stb 4, 0(5) ; CHECK-NEXT: lwz 4, -80(1) ; CHECK-NEXT: lwz 0, -100(1) ; CHECK-NEXT: mtcrf 128, 0 ; CHECK-NEXT: stw 4, -104(1) ; CHECK-NEXT: stw 3, -108(1) ; CHECK-NEXT: blt 0, .LBB0_14 ; CHECK-NEXT: # BB#13: # %entry ; CHECK-NEXT: lwz 3, -92(1) ; CHECK-NEXT: stw 3, -104(1) ; CHECK-NEXT: .LBB0_14: # %entry ; CHECK-NEXT: lwz 3, -104(1) ; CHECK-NEXT: lwz 4, -108(1) ; CHECK-NEXT: lwz 5, -4(1) ; CHECK-NEXT: stw 4, 4(5) ; CHECK-NEXT: lwz 3, 0(3) store i32 %z, i32* @var3, align 4 ; CHECK-NEXT: lis 4, var3 at ha ; CHECK-NEXT: stw 3, var3 at l(4) ret void ; CHECK-NEXT: stw 5, -112(1) ; CHECK-NEXT: blr } -------------- next part -------------- A non-text attachment was scrubbed... Name: powerpc32-vaarg.patch Type: text/x-diff Size: 6973 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110627/31242106/attachment.bin From aggarwa4 at illinois.edu Mon Jun 27 12:11:55 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Mon, 27 Jun 2011 17:11:55 -0000 Subject: [llvm-commits] [poolalloc] r133914 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Message-ID: <20110627171155.93F012A6C12C@llvm.org> Author: aggarwa4 Date: Mon Jun 27 12:11:55 2011 New Revision: 133914 URL: http://llvm.org/viewvc/llvm-project?rev=133914&view=rev Log: 1. Metadata can be NULL in checkType, for say select Inst, for values that do not need a check. Ignore the check in such a case. 2. Do not allow reading from middle of an object. We must first track integer/float types for implementing this. Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=133914&r1=133913&r2=133914&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Mon Jun 27 12:11:55 2011 @@ -53,7 +53,6 @@ extern char* typeNames[]; extern "C" { - void trackInitInst(void *ptr, uint64_t size, uint32_t tag); void shadowInit(); void trackArgvType(int argc, char **argv) ; void trackEnvpType(char **envp) ; @@ -226,10 +225,16 @@ */ void checkType(TypeTagTy typeNumber, uint64_t size, TypeTagTy *metadata, void *ptr, uint32_t tag) { + if(metadata == NULL) + return; /* Check if this an initialized but untyped memory.*/ - if (typeNumber != metadata[0] && metadata[0] != 0xFE) { + if (typeNumber != metadata[0]) { if (metadata[0] != 0xFF) { - printf("Type mismatch(%u): %p expecting %s, found %s!\n", tag, ptr, typeNames[typeNumber], typeNames[metadata[0]]); + if(metadata[0] == 0xFE) { + printf("Type alignment mismatch(%u): %p expecting %s, found MOb!\n", tag, ptr, typeNames[typeNumber]); + } else { + printf("Type mismatch(%u): %p expecting %s, found %s!\n", tag, ptr, typeNames[typeNumber], typeNames[metadata[0]]); + } return; } else { /* If so, set type to the type being read. From aggarwa4 at illinois.edu Mon Jun 27 12:15:40 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Mon, 27 Jun 2011 17:15:40 -0000 Subject: [llvm-commits] [poolalloc] r133915 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp Message-ID: <20110627171540.59DA32A6C12C@llvm.org> Author: aggarwa4 Date: Mon Jun 27 12:15:40 2011 New Revision: 133915 URL: http://llvm.org/viewvc/llvm-project?rev=133915&view=rev Log: 1. Handle times() library function 2. Fix fread. It returns the number of elements read, multiply by size of each element to get bytes. 3. Remove dead optimize function. 4. Handle invokeInst, when used in direct calls to address taken functions. Needed by spec2006/471.omnetpp 5. Push checks on select inst to the use of the selectInst. Choose the metadata to check, based on the condition in the select inst. If the value comes from an SSA value, set the metadata to NULL, which skips the check. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=133915&r1=133914&r2=133915&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Mon Jun 27 12:15:40 2011 @@ -40,6 +40,7 @@ std::list ByValFunctions; std::list AddressTakenFunctions; std::set IndCalls; + std::map SelectInst_MD_Map; // Analysis from other passes. TargetData *TD; @@ -69,7 +70,7 @@ bool visitAllocaInst(Module &M, AllocaInst &AI); bool visitVAArgInst(Module &M, VAArgInst &VI); - bool visitUses(Instruction *I, AllocaInst *AI, CastInst *BCI); + bool visitUses(Instruction *I, Instruction *AI, CastInst *BCI); bool visitGlobal(Module &M, GlobalVariable &GV, Constant *C, Instruction &I, SmallVector); Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133915&r1=133914&r2=133915&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Mon Jun 27 12:15:40 2011 @@ -438,49 +438,6 @@ // Delete checks, if it is dominated by another check for the same value. // We might get multiple checks on a path, if there are multiple uses of // a load inst. -/* -void TypeChecks::optimizeChecks(Module &M) { - // TODO: visit in dominator tree order - for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { - Function &F = *MI; - if(F.isDeclaration()) - continue; - for (Function::iterator B = F.begin(), FE = F.end(); B != FE; ++B) { - DominatorTree & DT = getAnalysis(F); - for (BasicBlock::iterator bi = B->begin(); bi != B->end(); ++bi) { - CallInst *CI = dyn_cast(bi); - if(!CI) - continue; - if(CI->getCalledFunction() != checkTypeInst) - continue; - std::listtoDelete; - for(Value::use_iterator User = checkTypeInst->use_begin(); User != checkTypeInst->use_end(); ++User) { - CallInst *CI2 = dyn_cast(User); - if(CI2 == CI) - continue; - if(CI2->getParent()->getParent() != &F) - continue; - // Check that they are refering to the same pointer - if(CI->getOperand(4) != CI2->getOperand(4)) - continue; - // Check that they are using the same metadata for comparison. - if(CI->getOperand(3) != CI2->getOperand(3)) - continue; - // if CI, dominates CI2, delete CI2 - if(!DT.dominates(CI, CI2)) - continue; - CI2->dump(); - toDelete.push_back(CI2); - } - while(!toDelete.empty()) { - Instruction *I = toDelete.back(); - toDelete.pop_back(); - I->eraseFromParent(); - } - } - } - } -}*/ void TypeChecks::optimizeChecks(Module &M) { for (Module::iterator MI = M.begin(), ME = M.end(); MI != ME; ++MI) { @@ -639,52 +596,95 @@ // Store in the map of original -> cloned function IndFunctionsMap[&F] = NewF; + std::vectortoDelete; // Find all uses of the function for(Value::use_iterator ui = F.use_begin(), ue = F.use_end(); - ui != ue;) { - if(isa(ui)) { - ui->dump(); - assert(0 && "Handle invoke inst here"); + ui != ue;++ui) { + if(InvokeInst *II = dyn_cast(ui)) { + if(II->getCalledValue()->stripPointerCasts() != &F) + continue; + std::vector Args; + inst_iterator InsPt = inst_begin(II->getParent()->getParent()); + unsigned int i; + unsigned int NumArgs = II->getNumOperands() - 3; + Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); + AllocaInst *AI = new AllocaInst(TypeTagTy, NumArgsVal, "", &*InsPt); + // set the metadata for the varargs in AI + for(i = 3; i getNumOperands(); i++) { + Value *Idx[2]; + Idx[0] = ConstantInt::get(Int32Ty, i - 3 ); + // For each vararg argument, also add its type information + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, + Idx, + Idx + 1, + "", II); + Constant *C = getTypeMarkerConstant(II->getOperand(i)); + new StoreInst(C, GEP, II); + } + + // As the first argument pass the number of var_arg arguments + Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); + Args.push_back(AI); + for(i = 3 ;i < II->getNumOperands(); i++) { + // Add the original argument + Args.push_back(II->getOperand(i)); + } + + II->dump(); + errs()<getType()->dump(); + // Create the new call + InvokeInst *II_New = InvokeInst::Create(NewF, + II->getNormalDest(), + II->getUnwindDest(), + Args.begin(), Args.end(), + "", II); + II->replaceAllUsesWith(II_New); + toDelete.push_back(II); } // Check for call sites - CallInst *CI = dyn_cast(ui++); - if(!CI) - continue; - if(CI->getCalledValue()->stripPointerCasts() != &F) - continue; - std::vector Args; - unsigned int i; - unsigned int NumArgs = CI->getNumOperands() - 1; - inst_iterator InsPt = inst_begin(CI->getParent()->getParent()); - Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); - AllocaInst *AI = new AllocaInst(TypeTagTy, NumArgsVal, "", &*InsPt); - // set the metadata for the varargs in AI - for(i = 1; i getNumOperands(); i++) { - Value *Idx[2]; - Idx[0] = ConstantInt::get(Int32Ty, i - 1 ); - // For each vararg argument, also add its type information - GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, - Idx, - Idx + 1, - "", CI); - Constant *C = getTypeMarkerConstant(CI->getOperand(i)); - new StoreInst(C, GEP, CI); - } + else if(CallInst *CI = dyn_cast(ui)) { + if(CI->getCalledValue()->stripPointerCasts() != &F) + continue; + std::vector Args; + unsigned int i; + unsigned int NumArgs = CI->getNumOperands() - 1; + inst_iterator InsPt = inst_begin(CI->getParent()->getParent()); + Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); + AllocaInst *AI = new AllocaInst(TypeTagTy, NumArgsVal, "", &*InsPt); + // set the metadata for the varargs in AI + for(i = 1; i getNumOperands(); i++) { + Value *Idx[2]; + Idx[0] = ConstantInt::get(Int32Ty, i - 1 ); + // For each vararg argument, also add its type information + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, + Idx, + Idx + 1, + "", CI); + Constant *C = getTypeMarkerConstant(CI->getOperand(i)); + new StoreInst(C, GEP, CI); + } - // As the first argument pass the number of var_arg arguments - Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); - Args.push_back(AI); - for(i = 1 ;i < CI->getNumOperands(); i++) { - // Add the original argument - Args.push_back(CI->getOperand(i)); - } + // As the first argument pass the number of var_arg arguments + Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); + Args.push_back(AI); + for(i = 1 ;i < CI->getNumOperands(); i++) { + // Add the original argument + Args.push_back(CI->getOperand(i)); + } - // Create the new call - CallInst *CI_New = CallInst::Create(NewF, - Args.begin(), Args.end(), - "", CI); - CI->replaceAllUsesWith(CI_New); - CI->eraseFromParent(); + // Create the new call + CallInst *CI_New = CallInst::Create(NewF, + Args.begin(), Args.end(), + "", CI); + CI->replaceAllUsesWith(CI_New); + toDelete.push_back(CI); + } + } + while(!toDelete.empty()) { + Instruction *I = toDelete.back(); + toDelete.pop_back(); + I->eraseFromParent(); } return true; @@ -1253,30 +1253,30 @@ return true; } -bool TypeChecks::visitMain(Module &M, Function &MainFunc) { - if(MainFunc.arg_size() < 2) - // No need to register - return false; + bool TypeChecks::visitMain(Module &M, Function &MainFunc) { + if(MainFunc.arg_size() < 2) + // No need to register + return false; - Function::arg_iterator AI = MainFunc.arg_begin(); - Value *Argc = AI; - Value *Argv = ++AI; - - Instruction *InsertPt = MainFunc.front().begin(); - std::vector fargs; - fargs.push_back (Argc); - fargs.push_back (Argv); - CallInst::Create (RegisterArgv, fargs.begin(), fargs.end(), "", InsertPt); + Function::arg_iterator AI = MainFunc.arg_begin(); + Value *Argc = AI; + Value *Argv = ++AI; + + Instruction *InsertPt = MainFunc.front().begin(); + std::vector fargs; + fargs.push_back (Argc); + fargs.push_back (Argv); + CallInst::Create (RegisterArgv, fargs.begin(), fargs.end(), "", InsertPt); - if(MainFunc.arg_size() < 3) - return true; + if(MainFunc.arg_size() < 3) + return true; - Value *Envp = ++AI; - std::vector Args; - Args.push_back(Envp); - CallInst::Create(RegisterEnvp, Args.begin(), Args.end(), "", InsertPt); - return true; -} + Value *Envp = ++AI; + std::vector Args; + Args.push_back(Envp); + CallInst::Create(RegisterEnvp, Args.begin(), Args.end(), "", InsertPt); + return true; + } bool TypeChecks::visitGlobal(Module &M, GlobalVariable &GV, Constant *C, Instruction &I, SmallVector Indices) { @@ -1513,7 +1513,8 @@ CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI_Src); } else if (F->getNameStr() == std::string("gettimeofday") || - F->getNameStr() == std::string("time")) { + F->getNameStr() == std::string("time") || + F->getNameStr() == std::string("times")) { CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); assert (isa(I->getOperand(1)->getType())); const PointerType * PT = cast(I->getOperand(1)->getType()); @@ -1678,8 +1679,10 @@ BCI->insertAfter(I); std::vector Args; Args.push_back(BCI); - CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false); - Size->insertAfter(I); + CastInst *Elem = CastInst::CreateIntegerCast(I, Int64Ty, false); + BinaryOperator *Size = BinaryOperator::Create(Instruction::Mul, Elem, I->getOperand(2)); + Elem->insertAfter(I); + Size->insertAfter(Elem); Args.push_back(Size); Args.push_back(getTagCounter()); CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); @@ -1913,7 +1916,7 @@ // AI - metadata // BCI - ptr // I - instruction whose uses to instrument -bool TypeChecks::visitUses(Instruction *I, AllocaInst *AI, CastInst *BCI) { +bool TypeChecks::visitUses(Instruction *I, Instruction *AI, CastInst *BCI) { for(Value::use_iterator II = I->use_begin(); II != I->use_end(); ++II) { if(DisablePtrCmpChecks) { if(isa(II)) { @@ -1939,6 +1942,32 @@ Args.push_back(getTagCounter()); // Create the call to the runtime check and place it before the copying store instruction. CallInst::Create(setTypeInfo, Args.begin(), Args.end(), "", SI); + } else if(SelectInst *SelI = dyn_cast(II)) { + SelectInst *Prev = NULL; + if(SelectInst_MD_Map.find(SelI) != SelectInst_MD_Map.end()) { + Prev = SelectInst_MD_Map[SelI]; + } + SelectInst *AI_New; + if(SelI->getTrueValue() == I) { + if(!Prev) { + AI_New = SelectInst::Create(SelI->getCondition(), AI, Constant::getNullValue(AI->getType()), "", SelI); + } else { + AI_New = SelectInst::Create(SelI->getCondition(), AI, Prev->getFalseValue(), "", SelI); + Prev->replaceAllUsesWith(AI_New); + } + } + else { + if(!Prev) { + AI_New = SelectInst::Create(SelI->getCondition(), Constant::getNullValue(AI->getType()), AI, "", SelI); + } else { + AI_New = SelectInst::Create(SelI->getCondition(), Prev->getTrueValue(), AI, "", SelI); + Prev->replaceAllUsesWith(AI_New); + } + } + SelectInst_MD_Map[SelI] = AI_New; + AI_New->dump(); + if(!Prev) + visitUses(SelI, AI_New, BCI); } else if(PHINode *PH = dyn_cast(II)) { BasicBlock *BB = PH->getIncomingBlock(II); CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", BB->getTerminator()); From stoklund at 2pi.dk Mon Jun 27 12:27:37 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Mon, 27 Jun 2011 17:27:37 -0000 Subject: [llvm-commits] [llvm] r133916 - in /llvm/trunk/test/CodeGen/X86: inline-asm-fpstack.ll inline-asm-fpstack2.ll inline-asm-fpstack3.ll inline-asm-fpstack4.ll inline-asm-fpstack5.ll Message-ID: <20110627172737.7903C2A6C12C@llvm.org> Author: stoklund Date: Mon Jun 27 12:27:37 2011 New Revision: 133916 URL: http://llvm.org/viewvc/llvm-project?rev=133916&view=rev Log: Move all inline-asm-fpstack tests to a single file. Also fix some of the tests that were actually testing wrong behavior - An input operand in {st} is only popped by the inline asm when {st} is also in the clobber list. The original bug reports all had ~{st} clobbers as they should. Removed: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack2.ll llvm/trunk/test/CodeGen/X86/inline-asm-fpstack3.ll llvm/trunk/test/CodeGen/X86/inline-asm-fpstack4.ll llvm/trunk/test/CodeGen/X86/inline-asm-fpstack5.ll Modified: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll Modified: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll?rev=133916&r1=133915&r2=133916&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll (original) +++ llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll Mon Jun 27 12:27:37 2011 @@ -26,7 +26,7 @@ ; CHECK-NOT: fstp ; CHECK: ret define void @test3(x86_fp80 %X) { - call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( x86_fp80 %X) + call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( x86_fp80 %X) ret void } @@ -37,7 +37,7 @@ ; CHECK-NOT: fstp ; CHECK: ret define void @test4(double %X) { - call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( double %X) + call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( double %X) ret void } @@ -49,7 +49,7 @@ ; CHECK: ret define void @test5(double %X) { %Y = fadd double %X, 123.0 - call void asm sideeffect "frob ", "{st(0)},~{dirflag},~{fpsr},~{flags}"( double %Y) + call void asm sideeffect "frob ", "{st(0)},~{st},~{dirflag},~{fpsr},~{flags}"( double %Y) ret void } @@ -86,3 +86,77 @@ ret void } +; PR4185 +; Passing a non-killed value to asm in {st}. +; Make sure it is duped before. +; asm kills st(0), so we shouldn't pop anything +; CHECK: testPR4185 +; CHECK: fld %st(0) +; CHECK: fistpl +; CHECK-NOT: fstp +; CHECK: fistpl +; CHECK-NOT: fstp +; CHECK: ret +; A valid alternative would be to remat the constant pool load before each +; inline asm. +define void @testPR4185() { +return: + call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06) + call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06) + ret void +} + +; PR4459 +; The return value from ceil must be duped before being consumed by asm. +; CHECK: testPR4459 +; CHECK: ceil +; CHECK: fld %st(0) +; CHECK-NOT: fxch +; CHECK: fistpl +; CHECK-NOT: fxch +; CHECK: fstpt +; CHECK: test +define void @testPR4459(x86_fp80 %a) { +entry: + %0 = call x86_fp80 @ceil(x86_fp80 %a) + call void asm sideeffect "fistpl $0", "{st},~{st}"( x86_fp80 %0) + call void @test3(x86_fp80 %0 ) + ret void +} +declare x86_fp80 @ceil(x86_fp80) + +; PR4484 +; test1 leaves a value on the stack that is needed after the asm. +; CHECK: testPR4484 +; CHECK: test1 +; CHECK-NOT: fstp +; Load %a from stack after ceil +; CHECK: fldt +; CHECK-NOT: fxch +; CHECK: fistpl +; CHECK-NOT: fstp +; Set up call to test. +; CHECK: fstpt +; CHECK: test +define void @testPR4484(x86_fp80 %a) { +entry: + %0 = call x86_fp80 @test1() + call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %a) + call void @test3(x86_fp80 %0) + ret void +} + +; PR4485 +; CHECK: testPR4485 +define void @testPR4485(x86_fp80* %a) { +entry: + %0 = load x86_fp80* %a, align 16 + %1 = fmul x86_fp80 %0, 0xK4006B400000000000000 + %2 = fmul x86_fp80 %1, 0xK4012F424000000000000 + tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %2) + %3 = load x86_fp80* %a, align 16 + %4 = fmul x86_fp80 %3, 0xK4006B400000000000000 + %5 = fmul x86_fp80 %4, 0xK4012F424000000000000 + tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %5) + ret void +} Removed: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack2.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack2.ll?rev=133915&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/inline-asm-fpstack2.ll (original) +++ llvm/trunk/test/CodeGen/X86/inline-asm-fpstack2.ll (removed) @@ -1,21 +0,0 @@ -; RUN: llc < %s -march=x86 | FileCheck %s -; PR4185 - -; Passing a non-killed value to asm in {st}. -; Make sure it is duped before. -; asm kills st(0), so we shouldn't pop anything -; CHECK: fld %st(0) -; CHECK: fistpl -; CHECK-NOT: fstp -; CHECK: fistpl -; CHECK-NOT: fstp -; CHECK: ret -define void @test() { -return: - call void asm sideeffect "fistpl $0", "{st}"(double 1.000000e+06) - call void asm sideeffect "fistpl $0", "{st}"(double 1.000000e+06) - ret void -} - -; A valid alternative would be to remat the constant pool load before each -; inline asm. Removed: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack3.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack3.ll?rev=133915&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/inline-asm-fpstack3.ll (original) +++ llvm/trunk/test/CodeGen/X86/inline-asm-fpstack3.ll (removed) @@ -1,20 +0,0 @@ -; RUN: llc < %s -march=x86 | FileCheck %s -; PR4459 - -; The return value from ceil must be duped before being consumed by asm. -; CHECK: ceil -; CHECK: fld %st(0) -; CHECK-NOT: fxch -; CHECK: fistpl -; CHECK-NOT: fxch -; CHECK: fstpt -; CHECK: test -define void @test2(x86_fp80 %a) { -entry: - %0 = call x86_fp80 @ceil(x86_fp80 %a) - call void asm sideeffect "fistpl $0", "{st}"( x86_fp80 %0) - call void @test(x86_fp80 %0 ) - ret void -} -declare x86_fp80 @ceil(x86_fp80) -declare void @test(x86_fp80) Removed: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack4.ll?rev=133915&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/inline-asm-fpstack4.ll (original) +++ llvm/trunk/test/CodeGen/X86/inline-asm-fpstack4.ll (removed) @@ -1,24 +0,0 @@ -; RUN: llc < %s -march=x86 | FileCheck %s -; PR4484 - -; ceil leaves a value on the stack that is needed after the asm. -; CHECK: ceil -; CHECK-NOT: fstp -; Load %a from stack after ceil -; CHECK: fldt -; CHECK-NOT: fxch -; CHECK: fistpl -; CHECK-NOT: fstp -; Set up call to test. -; CHECK: fstpt -; CHECK: test -define void @test2(x86_fp80 %a) { -entry: - %0 = call x86_fp80 @ceil() - call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %a) - call void @test(x86_fp80 %0) - ret void -} - -declare x86_fp80 @ceil() -declare void @test(x86_fp80) Removed: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack5.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack5.ll?rev=133915&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/inline-asm-fpstack5.ll (original) +++ llvm/trunk/test/CodeGen/X86/inline-asm-fpstack5.ll (removed) @@ -1,15 +0,0 @@ -; RUN: llc < %s -march=x86 -; PR4485 - -define void @test(x86_fp80* %a) { -entry: - %0 = load x86_fp80* %a, align 16 - %1 = fmul x86_fp80 %0, 0xK4006B400000000000000 - %2 = fmul x86_fp80 %1, 0xK4012F424000000000000 - tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %2) - %3 = load x86_fp80* %a, align 16 - %4 = fmul x86_fp80 %3, 0xK4006B400000000000000 - %5 = fmul x86_fp80 %4, 0xK4012F424000000000000 - tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %5) - ret void -} From atrick at apple.com Mon Jun 27 13:01:20 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 27 Jun 2011 18:01:20 -0000 Subject: [llvm-commits] [llvm] r133917 - in /llvm/trunk/lib/CodeGen/SelectionDAG: ScheduleDAGRRList.cpp ScheduleDAGSDNodes.cpp Message-ID: <20110627180120.82FE32A6C12C@llvm.org> Author: atrick Date: Mon Jun 27 13:01:20 2011 New Revision: 133917 URL: http://llvm.org/viewvc/llvm-project?rev=133917&view=rev Log: pre-RA-sched: Cleanup register pressure tracking. Removed the check that peeks past EXTRA_SUBREG, which I don't think makes sense any more. Intead treat it as a normal register def. No significant affect on x86 or ARM benchmarks. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=133917&r1=133916&r2=133917&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Jun 27 13:01:20 2011 @@ -2029,13 +2029,9 @@ unsigned POpc = PN->getMachineOpcode(); if (POpc == TargetOpcode::IMPLICIT_DEF) continue; - if (POpc == TargetOpcode::EXTRACT_SUBREG) { - EVT VT = PN->getOperand(0).getValueType(); - unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); - RegPressure[RCId] += TLI->getRepRegClassCostFor(VT); - continue; - } else if (POpc == TargetOpcode::INSERT_SUBREG || - POpc == TargetOpcode::SUBREG_TO_REG) { + if (POpc == TargetOpcode::EXTRACT_SUBREG || + POpc == TargetOpcode::INSERT_SUBREG || + POpc == TargetOpcode::SUBREG_TO_REG) { EVT VT = PN->getValueType(0); unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); RegPressure[RCId] += TLI->getRepRegClassCostFor(VT); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=133917&r1=133916&r2=133917&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Mon Jun 27 13:01:20 2011 @@ -520,15 +520,7 @@ for (;DefIdx < NodeNumDefs; ++DefIdx) { if (!Node->hasAnyUseOfValue(DefIdx)) continue; - if (Node->isMachineOpcode() && - Node->getMachineOpcode() == TargetOpcode::EXTRACT_SUBREG && - Node->getOperand(0).getValueType() != MVT::untyped) { - // Propagate the incoming (full-register) type. I doubt it's needed. - ValueType = Node->getOperand(0).getValueType(); - } - else { - ValueType = Node->getValueType(DefIdx); - } + ValueType = Node->getValueType(DefIdx); ++DefIdx; return; // Found a normal regdef. } From evan.cheng at apple.com Mon Jun 27 13:32:37 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 27 Jun 2011 18:32:37 -0000 Subject: [llvm-commits] [llvm] r133922 - in /llvm/trunk: lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/Disassembler/ lib/Target/X86/InstPrinter/ lib/Target/X86/MCTargetDesc/ lib/Target/XCore/ utils/TableGen/ Message-ID: <20110627183238.9EB2B2A6C12C@llvm.org> Author: evancheng Date: Mon Jun 27 13:32:37 2011 New Revision: 133922 URL: http://llvm.org/viewvc/llvm-project?rev=133922&view=rev Log: Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc into XXXGenRegisterInfo.inc. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/lib/Target/ARM/Makefile llvm/trunk/lib/Target/Alpha/Alpha.h llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h llvm/trunk/lib/Target/Alpha/CMakeLists.txt llvm/trunk/lib/Target/Alpha/Makefile llvm/trunk/lib/Target/Blackfin/Blackfin.h llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h llvm/trunk/lib/Target/Blackfin/CMakeLists.txt llvm/trunk/lib/Target/Blackfin/Makefile llvm/trunk/lib/Target/CellSPU/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/Makefile llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h llvm/trunk/lib/Target/MBlaze/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/MBlaze.h llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h llvm/trunk/lib/Target/MBlaze/Makefile llvm/trunk/lib/Target/MSP430/CMakeLists.txt llvm/trunk/lib/Target/MSP430/MSP430.h llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h llvm/trunk/lib/Target/MSP430/Makefile llvm/trunk/lib/Target/Mips/CMakeLists.txt llvm/trunk/lib/Target/Mips/Makefile llvm/trunk/lib/Target/Mips/Mips.h llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h llvm/trunk/lib/Target/PTX/CMakeLists.txt llvm/trunk/lib/Target/PTX/Makefile llvm/trunk/lib/Target/PTX/PTX.h llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h llvm/trunk/lib/Target/PowerPC/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/Makefile llvm/trunk/lib/Target/PowerPC/PPC.h llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h llvm/trunk/lib/Target/Sparc/CMakeLists.txt llvm/trunk/lib/Target/Sparc/Makefile llvm/trunk/lib/Target/Sparc/Sparc.h llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h llvm/trunk/lib/Target/SystemZ/CMakeLists.txt llvm/trunk/lib/Target/SystemZ/Makefile llvm/trunk/lib/Target/SystemZ/SystemZ.h llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h llvm/trunk/lib/Target/X86/Makefile llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.h llvm/trunk/lib/Target/XCore/CMakeLists.txt llvm/trunk/lib/Target/XCore/Makefile llvm/trunk/lib/Target/XCore/XCore.h llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp llvm/trunk/utils/TableGen/RegisterInfoEmitter.h llvm/trunk/utils/TableGen/TableGen.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInfo.h Mon Jun 27 13:32:37 2011 @@ -25,7 +25,8 @@ // Defines symbolic names for ARM registers. This defines a mapping from // register name to register number. // -#include "ARMGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "ARMGenRegisterInfo.inc" // Defines symbolic names for the ARM instructions. // Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -39,7 +39,9 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Support/CommandLine.h" -#include "ARMGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "ARMGenRegisterInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -16,7 +16,9 @@ #include "ARM.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "ARMGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "ARMGenRegisterInfo.inc" namespace llvm { class ARMSubtarget; Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS ARM.td) -tablegen(ARMGenRegisterNames.inc -gen-register-enums) -tablegen(ARMGenRegisterDesc.inc -gen-register-desc) -tablegen(ARMGenRegisterInfo.h.inc -gen-register-info-header) tablegen(ARMGenRegisterInfo.inc -gen-register-info) tablegen(ARMGenInstrNames.inc -gen-instr-enums) tablegen(ARMGenInstrInfo.inc -gen-instr-desc) Modified: llvm/trunk/lib/Target/ARM/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Makefile (original) +++ llvm/trunk/lib/Target/ARM/Makefile Mon Jun 27 13:32:37 2011 @@ -12,8 +12,7 @@ TARGET = ARM # Make sure that tblgen is run, first thing. -BUILT_SOURCES = ARMGenRegisterNames.inc ARMGenRegisterDesc.inc \ - ARMGenRegisterInfo.h.inc ARMGenRegisterInfo.inc \ +BUILT_SOURCES = ARMGenRegisterInfo.inc \ ARMGenInstrNames.inc ARMGenInstrInfo.inc \ ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \ ARMGenDAGISel.inc ARMGenSubtarget.inc \ Modified: llvm/trunk/lib/Target/Alpha/Alpha.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Alpha.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/Alpha.h (original) +++ llvm/trunk/lib/Target/Alpha/Alpha.h Mon Jun 27 13:32:37 2011 @@ -44,7 +44,9 @@ // Defines symbolic names for Alpha registers. This defines a mapping from // register name to register number. // -#include "AlphaGenRegisterNames.inc" + +#define GET_REGINFO_ENUM +#include "AlphaGenRegisterInfo.inc" // Defines symbolic names for the Alpha instructions. // Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -33,8 +33,11 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include -#include "AlphaGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "AlphaGenRegisterInfo.inc" + using namespace llvm; AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -15,7 +15,9 @@ #define ALPHAREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "AlphaGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "AlphaGenRegisterInfo.inc" namespace llvm { Modified: llvm/trunk/lib/Target/Alpha/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Alpha/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Alpha.td) -tablegen(AlphaGenRegisterNames.inc -gen-register-enums) -tablegen(AlphaGenRegisterDesc.inc -gen-register-desc) -tablegen(AlphaGenRegisterInfo.h.inc -gen-register-info-header) tablegen(AlphaGenRegisterInfo.inc -gen-register-info) tablegen(AlphaGenInstrNames.inc -gen-instr-enums) tablegen(AlphaGenInstrInfo.inc -gen-instr-desc) Modified: llvm/trunk/lib/Target/Alpha/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/Makefile (original) +++ llvm/trunk/lib/Target/Alpha/Makefile Mon Jun 27 13:32:37 2011 @@ -12,8 +12,7 @@ TARGET = Alpha # Make sure that tblgen is run, first thing. -BUILT_SOURCES = AlphaGenRegisterNames.inc AlphaGenRegisterDesc.inc \ - AlphaGenRegisterInfo.h.inc AlphaGenRegisterInfo.inc \ +BUILT_SOURCES = AlphaGenRegisterInfo.inc \ AlphaGenInstrNames.inc AlphaGenInstrInfo.inc \ AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \ AlphaGenCallingConv.inc AlphaGenSubtarget.inc Modified: llvm/trunk/lib/Target/Blackfin/Blackfin.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/Blackfin.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/Blackfin.h (original) +++ llvm/trunk/lib/Target/Blackfin/Blackfin.h Mon Jun 27 13:32:37 2011 @@ -30,7 +30,8 @@ // Defines symbolic names for Blackfin registers. This defines a mapping from // register name to register number. -#include "BlackfinGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "BlackfinGenRegisterInfo.inc" // Defines symbolic names for the Blackfin instructions. #include "BlackfinGenInstrNames.inc" Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -29,8 +29,11 @@ #include "llvm/Type.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "BlackfinGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "BlackfinGenRegisterInfo.inc" + using namespace llvm; BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st, Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -16,7 +16,9 @@ #define BLACKFINREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "BlackfinGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "BlackfinGenRegisterInfo.inc" namespace llvm { Modified: llvm/trunk/lib/Target/Blackfin/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Blackfin/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Blackfin.td) -tablegen(BlackfinGenRegisterNames.inc -gen-register-enums) -tablegen(BlackfinGenRegisterDesc.inc -gen-register-desc) -tablegen(BlackfinGenRegisterInfo.h.inc -gen-register-info-header) tablegen(BlackfinGenRegisterInfo.inc -gen-register-info) tablegen(BlackfinGenInstrNames.inc -gen-instr-enums) tablegen(BlackfinGenInstrInfo.inc -gen-instr-desc) Modified: llvm/trunk/lib/Target/Blackfin/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/Makefile (original) +++ llvm/trunk/lib/Target/Blackfin/Makefile Mon Jun 27 13:32:37 2011 @@ -12,9 +12,7 @@ TARGET = Blackfin # Make sure that tblgen is run, first thing. -BUILT_SOURCES = BlackfinGenRegisterNames.inc BlackfinGenRegisterDesc.inc \ - BlackfinGenRegisterInfo.h.inc BlackfinGenRegisterInfo.inc \ - BlackfinGenInstrNames.inc \ +BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrNames.inc \ BlackfinGenInstrInfo.inc BlackfinGenAsmWriter.inc \ BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \ BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CellSPU/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,11 +1,8 @@ set(LLVM_TARGET_DEFINITIONS SPU.td) tablegen(SPUGenInstrNames.inc -gen-instr-enums) -tablegen(SPUGenRegisterNames.inc -gen-register-enums) tablegen(SPUGenAsmWriter.inc -gen-asm-writer) tablegen(SPUGenCodeEmitter.inc -gen-emitter) -tablegen(SPUGenRegisterDesc.inc -gen-register-desc) -tablegen(SPUGenRegisterInfo.h.inc -gen-register-info-header) tablegen(SPUGenRegisterInfo.inc -gen-register-info) tablegen(SPUGenInstrInfo.inc -gen-instr-desc) tablegen(SPUGenDAGISel.inc -gen-dag-isel) Modified: llvm/trunk/lib/Target/CellSPU/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/Makefile (original) +++ llvm/trunk/lib/Target/CellSPU/Makefile Mon Jun 27 13:32:37 2011 @@ -10,10 +10,8 @@ LEVEL = ../../.. LIBRARYNAME = LLVMCellSPUCodeGen TARGET = SPU -BUILT_SOURCES = SPUGenInstrNames.inc \ +BUILT_SOURCES = SPUGenInstrNames.inc SPUGenRegisterInfo.inc \ SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \ - SPUGenRegisterNames.inc SPUGenRegisterDesc.inc \ - SPUGenRegisterInfo.h.inc SPUGenRegisterInfo.inc \ SPUGenInstrInfo.inc SPUGenDAGISel.inc \ SPUGenSubtarget.inc SPUGenCallingConv.inc Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -42,7 +42,9 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include -#include "SPUGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "SPUGenRegisterInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -16,7 +16,9 @@ #define SPU_REGISTERINFO_H #include "SPU.h" -#include "SPUGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "SPUGenRegisterInfo.inc" namespace llvm { class SPUSubtarget; Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterNames.h Mon Jun 27 13:32:37 2011 @@ -13,6 +13,7 @@ // Define symbolic names for Cell registers. This defines a mapping from // register name to register number. // -#include "SPUGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "SPUGenRegisterInfo.inc" #endif Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,9 +1,6 @@ set(LLVM_TARGET_DEFINITIONS MBlaze.td) -tablegen(MBlazeGenRegisterNames.inc -gen-register-enums) -tablegen(MBlazeGenRegisterDesc.inc -gen-register-desc) tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header) -tablegen(MBlazeGenRegisterInfo.inc -gen-register-info) tablegen(MBlazeGenInstrNames.inc -gen-instr-enums) tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc) tablegen(MBlazeGenCodeEmitter.inc -gen-emitter) Modified: llvm/trunk/lib/Target/MBlaze/MBlaze.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlaze.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlaze.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlaze.h Mon Jun 27 13:32:37 2011 @@ -39,7 +39,8 @@ // Defines symbolic names for MBlaze registers. This defines a mapping from // register name to register number. -#include "MBlazeGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "MBlazeGenRegisterInfo.inc" // Defines symbolic names for the MBlaze instructions. #include "MBlazeGenInstrNames.inc" Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -36,8 +36,11 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "MBlazeGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "MBlazeGenRegisterInfo.inc" + using namespace llvm; MBlazeRegisterInfo:: Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -17,7 +17,9 @@ #include "MBlaze.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "MBlazeGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "MBlazeGenRegisterInfo.inc" namespace llvm { class MBlazeSubtarget; Modified: llvm/trunk/lib/Target/MBlaze/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/Makefile (original) +++ llvm/trunk/lib/Target/MBlaze/Makefile Mon Jun 27 13:32:37 2011 @@ -11,9 +11,7 @@ TARGET = MBlaze # Make sure that tblgen is run, first thing. -BUILT_SOURCES = MBlazeGenRegisterInfo.h.inc MBlazeGenRegisterNames.inc \ - MBlazeGenRegisterInfo.inc MBlazeGenRegisterDesc.inc \ - MBlazeGenInstrNames.inc \ +BUILT_SOURCES = MBlazeGenRegisterInfo.inc MBlazeGenInstrNames.inc \ MBlazeGenInstrInfo.inc MBlazeGenAsmWriter.inc \ MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \ MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \ Modified: llvm/trunk/lib/Target/MSP430/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MSP430/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS MSP430.td) -tablegen(MSP430GenRegisterNames.inc -gen-register-enums) -tablegen(MSP430GenRegisterDesc.inc -gen-register-desc) -tablegen(MSP430GenRegisterInfo.h.inc -gen-register-info-header) tablegen(MSP430GenRegisterInfo.inc -gen-register-info) tablegen(MSP430GenInstrNames.inc -gen-instr-enums) tablegen(MSP430GenInstrInfo.inc -gen-instr-desc) Modified: llvm/trunk/lib/Target/MSP430/MSP430.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430.h Mon Jun 27 13:32:37 2011 @@ -47,7 +47,8 @@ // Defines symbolic names for MSP430 registers. // This defines a mapping from register name to register number. -#include "MSP430GenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "MSP430GenRegisterInfo.inc" // Defines symbolic names for the MSP430 instructions. #include "MSP430GenInstrNames.inc" Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -25,7 +25,9 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" #include "llvm/Support/ErrorHandling.h" -#include "MSP430GenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "MSP430GenRegisterInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -15,7 +15,9 @@ #define LLVM_TARGET_MSP430REGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "MSP430GenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "MSP430GenRegisterInfo.inc" namespace llvm { Modified: llvm/trunk/lib/Target/MSP430/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/Makefile (original) +++ llvm/trunk/lib/Target/MSP430/Makefile Mon Jun 27 13:32:37 2011 @@ -12,9 +12,7 @@ TARGET = MSP430 # Make sure that tblgen is run, first thing. -BUILT_SOURCES = MSP430GenRegisterInfo.h.inc MSP430GenRegisterNames.inc \ - MSP430GenRegisterInfo.inc MSP430GenRegisterDesc.inc \ - MSP430GenInstrNames.inc \ +BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrNames.inc \ MSP430GenInstrInfo.inc MSP430GenAsmWriter.inc \ MSP430GenDAGISel.inc MSP430GenCallingConv.inc \ MSP430GenSubtarget.inc Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Mips.td) -tablegen(MipsGenRegisterNames.inc -gen-register-enums) -tablegen(MipsGenRegisterDesc.inc -gen-register-desc) -tablegen(MipsGenRegisterInfo.h.inc -gen-register-info-header) tablegen(MipsGenRegisterInfo.inc -gen-register-info) tablegen(MipsGenInstrNames.inc -gen-instr-enums) tablegen(MipsGenInstrInfo.inc -gen-instr-desc) Modified: llvm/trunk/lib/Target/Mips/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Makefile (original) +++ llvm/trunk/lib/Target/Mips/Makefile Mon Jun 27 13:32:37 2011 @@ -12,9 +12,7 @@ TARGET = Mips # Make sure that tblgen is run, first thing. -BUILT_SOURCES = MipsGenRegisterInfo.h.inc MipsGenRegisterNames.inc \ - MipsGenRegisterInfo.inc MipsGenRegisterDesc.inc \ - MipsGenInstrNames.inc \ +BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrNames.inc \ MipsGenInstrInfo.inc MipsGenAsmWriter.inc \ MipsGenDAGISel.inc MipsGenCallingConv.inc \ MipsGenSubtarget.inc Modified: llvm/trunk/lib/Target/Mips/Mips.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/Mips.h (original) +++ llvm/trunk/lib/Target/Mips/Mips.h Mon Jun 27 13:32:37 2011 @@ -35,7 +35,8 @@ // Defines symbolic names for Mips registers. This defines a mapping from // register name to register number. -#include "MipsGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "MipsGenRegisterInfo.inc" // Defines symbolic names for the Mips instructions. #include "MipsGenInstrNames.inc" Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -35,7 +35,9 @@ #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "MipsGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "MipsGenRegisterInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -16,7 +16,9 @@ #include "Mips.h" #include "llvm/Target/TargetRegisterInfo.h" -#include "MipsGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "MipsGenRegisterInfo.inc" namespace llvm { class MipsSubtarget; Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -5,10 +5,7 @@ tablegen(PTXGenDAGISel.inc -gen-dag-isel) tablegen(PTXGenInstrInfo.inc -gen-instr-desc) tablegen(PTXGenInstrNames.inc -gen-instr-enums) -tablegen(PTXGenRegisterDesc.inc -gen-register-desc) tablegen(PTXGenRegisterInfo.inc -gen-register-info) -tablegen(PTXGenRegisterInfo.h.inc -gen-register-info-header) -tablegen(PTXGenRegisterNames.inc -gen-register-enums) tablegen(PTXGenSubtarget.inc -gen-subtarget) add_llvm_target(PTXCodeGen Modified: llvm/trunk/lib/Target/PTX/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/Makefile (original) +++ llvm/trunk/lib/Target/PTX/Makefile Mon Jun 27 13:32:37 2011 @@ -17,10 +17,7 @@ PTXGenDAGISel.inc \ PTXGenInstrInfo.inc \ PTXGenInstrNames.inc \ - PTXGenRegisterDesc.inc \ PTXGenRegisterInfo.inc \ - PTXGenRegisterInfo.h.inc \ - PTXGenRegisterNames.inc \ PTXGenSubtarget.inc DIRS = TargetInfo Modified: llvm/trunk/lib/Target/PTX/PTX.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTX.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTX.h (original) +++ llvm/trunk/lib/Target/PTX/PTX.h Mon Jun 27 13:32:37 2011 @@ -47,7 +47,8 @@ } // namespace llvm; // Defines symbolic names for PTX registers. -#include "PTXGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "PTXGenRegisterInfo.inc" // Defines symbolic names for the PTX instructions. #include "PTXGenInstrNames.inc" Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -17,11 +17,11 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" -using namespace llvm; - -#include "PTXGenRegisterDesc.inc" +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "PTXGenRegisterInfo.inc" +using namespace llvm; PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM, const TargetInstrInfo &TII) Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h (original) +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -17,7 +17,8 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/ADT/BitVector.h" -#include "PTXGenRegisterInfo.h.inc" +#define GET_REGINFO_HEADER +#include "PTXGenRegisterInfo.inc" namespace llvm { class PTXTargetMachine; Modified: llvm/trunk/lib/Target/PowerPC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/PowerPC/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,12 +1,9 @@ set(LLVM_TARGET_DEFINITIONS PPC.td) tablegen(PPCGenInstrNames.inc -gen-instr-enums) -tablegen(PPCGenRegisterNames.inc -gen-register-enums) tablegen(PPCGenAsmWriter.inc -gen-asm-writer) tablegen(PPCGenCodeEmitter.inc -gen-emitter) tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter) -tablegen(PPCGenRegisterDesc.inc -gen-register-desc) -tablegen(PPCGenRegisterInfo.h.inc -gen-register-info-header) tablegen(PPCGenRegisterInfo.inc -gen-register-info) tablegen(PPCGenInstrInfo.inc -gen-instr-desc) tablegen(PPCGenDAGISel.inc -gen-dag-isel) Modified: llvm/trunk/lib/Target/PowerPC/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/Makefile (original) +++ llvm/trunk/lib/Target/PowerPC/Makefile Mon Jun 27 13:32:37 2011 @@ -12,10 +12,8 @@ TARGET = PPC # Make sure that tblgen is run, first thing. -BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterNames.inc \ +BUILT_SOURCES = PPCGenInstrNames.inc PPCGenRegisterInfo.inc \ PPCGenAsmWriter.inc PPCGenCodeEmitter.inc \ - PPCGenRegisterDesc.inc \ - PPCGenRegisterInfo.h.inc PPCGenRegisterInfo.inc \ PPCGenInstrInfo.inc PPCGenDAGISel.inc \ PPCGenSubtarget.inc PPCGenCallingConv.inc \ PPCGenMCCodeEmitter.inc Modified: llvm/trunk/lib/Target/PowerPC/PPC.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPC.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPC.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPC.h Mon Jun 27 13:32:37 2011 @@ -84,7 +84,8 @@ // Defines symbolic names for PowerPC registers. This defines a mapping from // register name to register number. // -#include "PPCGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "PPCGenRegisterInfo.inc" // Defines symbolic names for the PowerPC instructions. // Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -43,7 +43,9 @@ #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" #include -#include "PPCGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "PPCGenRegisterInfo.inc" // FIXME (64-bit): Eventually enable by default. Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -16,9 +16,11 @@ #define POWERPC32_REGISTERINFO_H #include "PPC.h" -#include "PPCGenRegisterInfo.h.inc" #include +#define GET_REGINFO_HEADER +#include "PPCGenRegisterInfo.inc" + namespace llvm { class PPCSubtarget; class TargetInstrInfo; Modified: llvm/trunk/lib/Target/Sparc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Sparc/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td) -tablegen(SparcGenRegisterNames.inc -gen-register-enums) -tablegen(SparcGenRegisterDesc.inc -gen-register-desc) -tablegen(SparcGenRegisterInfo.h.inc -gen-register-info-header) tablegen(SparcGenRegisterInfo.inc -gen-register-info) tablegen(SparcGenInstrNames.inc -gen-instr-enums) tablegen(SparcGenInstrInfo.inc -gen-instr-desc) Modified: llvm/trunk/lib/Target/Sparc/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/Makefile (original) +++ llvm/trunk/lib/Target/Sparc/Makefile Mon Jun 27 13:32:37 2011 @@ -12,9 +12,7 @@ TARGET = Sparc # Make sure that tblgen is run, first thing. -BUILT_SOURCES = SparcGenRegisterInfo.h.inc SparcGenRegisterNames.inc \ - SparcGenRegisterInfo.inc SparcGenRegisterDesc.inc \ - SparcGenInstrNames.inc \ +BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \ SparcGenInstrInfo.inc SparcGenAsmWriter.inc \ SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc Modified: llvm/trunk/lib/Target/Sparc/Sparc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/Sparc.h (original) +++ llvm/trunk/lib/Target/Sparc/Sparc.h Mon Jun 27 13:32:37 2011 @@ -36,7 +36,8 @@ // Defines symbolic names for Sparc registers. This defines a mapping from // register name to register number. // -#include "SparcGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "SparcGenRegisterInfo.inc" // Defines symbolic names for the Sparc instructions. // Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -23,8 +23,11 @@ #include "llvm/Type.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" -#include "SparcGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "SparcGenRegisterInfo.inc" + using namespace llvm; SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -15,7 +15,9 @@ #define SPARCREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "SparcGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "SparcGenRegisterInfo.inc" namespace llvm { Modified: llvm/trunk/lib/Target/SystemZ/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/SystemZ/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS SystemZ.td) -tablegen(SystemZGenRegisterNames.inc -gen-register-enums) -tablegen(SystemZGenRegisterDesc.inc -gen-register-desc) -tablegen(SystemZGenRegisterInfo.h.inc -gen-register-info-header) tablegen(SystemZGenRegisterInfo.inc -gen-register-info) tablegen(SystemZGenInstrNames.inc -gen-instr-enums) tablegen(SystemZGenInstrInfo.inc -gen-instr-desc) Modified: llvm/trunk/lib/Target/SystemZ/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/Makefile (original) +++ llvm/trunk/lib/Target/SystemZ/Makefile Mon Jun 27 13:32:37 2011 @@ -12,9 +12,7 @@ TARGET = SystemZ # Make sure that tblgen is run, first thing. -BUILT_SOURCES = SystemZGenRegisterInfo.h.inc SystemZGenRegisterNames.inc \ - SystemZGenRegisterInfo.inc SystemZGenRegisterDesc.inc \ - SystemZGenInstrNames.inc \ +BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \ SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \ SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc Modified: llvm/trunk/lib/Target/SystemZ/SystemZ.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZ.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZ.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZ.h Mon Jun 27 13:32:37 2011 @@ -53,7 +53,8 @@ // Defines symbolic names for SystemZ registers. // This defines a mapping from register name to register number. -#include "SystemZGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "SystemZGenRegisterInfo.inc" // Defines symbolic names for the SystemZ instructions. #include "SystemZGenInstrNames.inc" Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -25,8 +25,11 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" -#include "SystemZGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "SystemZGenRegisterInfo.inc" + using namespace llvm; SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm, Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -15,7 +15,9 @@ #define SystemZREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "SystemZGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "SystemZGenRegisterInfo.inc" namespace llvm { Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS X86.td) -tablegen(X86GenRegisterNames.inc -gen-register-enums) -tablegen(X86GenRegisterDesc.inc -gen-register-desc) -tablegen(X86GenRegisterInfo.h.inc -gen-register-info-header) tablegen(X86GenRegisterInfo.inc -gen-register-info) tablegen(X86GenDisassemblerTables.inc -gen-disassembler) tablegen(X86GenInstrNames.inc -gen-instr-enums) Modified: llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp (original) +++ llvm/trunk/lib/Target/X86/Disassembler/X86Disassembler.cpp Mon Jun 27 13:32:37 2011 @@ -26,7 +26,8 @@ #include "llvm/Support/MemoryObject.h" #include "llvm/Support/raw_ostream.h" -#include "X86GenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" #include "X86GenEDInfo.inc" using namespace llvm; Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Mon Jun 27 13:32:37 2011 @@ -27,12 +27,11 @@ using namespace llvm; // Include the auto-generated portion of the assembly writer. +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" #define GET_INSTRUCTION_NAME #define PRINT_ALIAS_INSTR -#include "X86GenRegisterNames.inc" #include "X86GenAsmWriter.inc" -#undef PRINT_ALIAS_INSTR -#undef GET_INSTRUCTION_NAME X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI) : MCInstPrinter(MAI) { Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp Mon Jun 27 13:32:37 2011 @@ -14,7 +14,9 @@ #include "X86TargetDesc.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Target/TargetRegistry.h" -#include "X86GenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#include "X86GenRegisterInfo.inc" using namespace llvm; MCRegisterInfo *createX86MCRegisterInfo() { Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h Mon Jun 27 13:32:37 2011 @@ -23,6 +23,7 @@ // Defines symbolic names for X86 registers. This defines a mapping from // register name to register number. // -#include "X86GenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "X86GenRegisterInfo.inc" #endif Modified: llvm/trunk/lib/Target/X86/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Makefile (original) +++ llvm/trunk/lib/Target/X86/Makefile Mon Jun 27 13:32:37 2011 @@ -12,8 +12,7 @@ TARGET = X86 # Make sure that tblgen is run, first thing. -BUILT_SOURCES = X86GenRegisterNames.inc X86GenRegisterDesc.inc \ - X86GenRegisterInfo.h.inc X86GenRegisterInfo.inc \ +BUILT_SOURCES = X86GenRegisterInfo.inc \ X86GenInstrNames.inc X86GenInstrInfo.inc \ X86GenAsmWriter.inc X86GenAsmMatcher.inc \ X86GenAsmWriter1.inc X86GenDAGISel.inc \ Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -39,8 +39,11 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/CommandLine.h" -#include "X86GenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "X86GenRegisterInfo.inc" + using namespace llvm; cl::opt Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -15,7 +15,9 @@ #define X86REGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "X86GenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "X86GenRegisterInfo.inc" namespace llvm { class Type; Modified: llvm/trunk/lib/Target/XCore/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/CMakeLists.txt?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/XCore/CMakeLists.txt Mon Jun 27 13:32:37 2011 @@ -1,8 +1,5 @@ set(LLVM_TARGET_DEFINITIONS XCore.td) -tablegen(XCoreGenRegisterNames.inc -gen-register-enums) -tablegen(XCoreGenRegisterDesc.inc -gen-register-desc) -tablegen(XCoreGenRegisterInfo.h.inc -gen-register-info-header) tablegen(XCoreGenRegisterInfo.inc -gen-register-info) tablegen(XCoreGenInstrNames.inc -gen-instr-enums) tablegen(XCoreGenInstrInfo.inc -gen-instr-desc) Modified: llvm/trunk/lib/Target/XCore/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/Makefile?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/Makefile (original) +++ llvm/trunk/lib/Target/XCore/Makefile Mon Jun 27 13:32:37 2011 @@ -12,9 +12,7 @@ TARGET = XCore # Make sure that tblgen is run, first thing. -BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \ - XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \ - XCoreGenInstrNames.inc \ +BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \ XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \ XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ XCoreGenSubtarget.inc Modified: llvm/trunk/lib/Target/XCore/XCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCore.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCore.h (original) +++ llvm/trunk/lib/Target/XCore/XCore.h Mon Jun 27 13:32:37 2011 @@ -32,7 +32,8 @@ // Defines symbolic names for XCore registers. This defines a mapping from // register name to register number. // -#include "XCoreGenRegisterNames.inc" +#define GET_REGINFO_ENUM +#include "XCoreGenRegisterInfo.inc" // Defines symbolic names for the XCore instructions. // Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Mon Jun 27 13:32:37 2011 @@ -32,8 +32,11 @@ #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" -#include "XCoreGenRegisterDesc.inc" + +#define GET_REGINFO_MC_DESC +#define GET_REGINFO_TARGET_DESC #include "XCoreGenRegisterInfo.inc" + using namespace llvm; XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii) Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.h Mon Jun 27 13:32:37 2011 @@ -15,7 +15,9 @@ #define XCOREREGISTERINFO_H #include "llvm/Target/TargetRegisterInfo.h" -#include "XCoreGenRegisterInfo.h.inc" + +#define GET_REGINFO_HEADER +#include "XCoreGenRegisterInfo.inc" namespace llvm { Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Mon Jun 27 13:32:37 2011 @@ -25,14 +25,18 @@ using namespace llvm; // runEnums - Print out enum values for all of the registers. -void RegisterInfoEmitter::runEnums(raw_ostream &OS) { - CodeGenTarget Target(Records); - CodeGenRegBank &Bank = Target.getRegBank(); +void +RegisterInfoEmitter::runEnums(raw_ostream &OS, + CodeGenTarget &Target, CodeGenRegBank &Bank) { const std::vector &Registers = Bank.getRegisters(); std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace"); EmitSourceFileHeader("Target Register Enum Values", OS); + + OS << "\n#ifdef GET_REGINFO_ENUM\n"; + OS << "#undef GET_REGINFO_ENUM\n"; + OS << "namespace llvm {\n\n"; if (!Namespace.empty()) @@ -63,12 +67,33 @@ if (!Namespace.empty()) OS << "}\n"; } + + const std::vector &RegisterClasses = + Target.getRegisterClasses(); + + if (!RegisterClasses.empty()) { + OS << "\n// Register classes\n"; + OS << "namespace " << RegisterClasses[0].Namespace << " {\n"; + OS << "enum {\n"; + for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { + if (i) OS << ",\n"; + OS << " " << RegisterClasses[i].getName() << "RegClassID"; + OS << " = " << i; + } + OS << "\n };\n"; + OS << "}\n"; + } + OS << "} // End llvm namespace \n"; + OS << "#endif // GET_REGINFO_ENUM\n\n"; } -void RegisterInfoEmitter::runHeader(raw_ostream &OS) { +void RegisterInfoEmitter::runHeader(raw_ostream &OS, CodeGenTarget &Target) { EmitSourceFileHeader("Register Information Header Fragment", OS); - CodeGenTarget Target(Records); + + OS << "\n#ifdef GET_REGINFO_HEADER\n"; + OS << "#undef GET_REGINFO_HEADER\n"; + const std::string &TargetName = Target.getName(); std::string ClassName = TargetName + "GenRegisterInfo"; @@ -100,14 +125,6 @@ OS << "namespace " << RegisterClasses[0].Namespace << " { // Register classes\n"; - OS << " enum {\n"; - for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { - if (i) OS << ",\n"; - OS << " " << RegisterClasses[i].getName() << "RegClassID"; - OS << " = " << i; - } - OS << "\n };\n\n"; - for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { const CodeGenRegisterClass &RC = RegisterClasses[i]; const std::string &Name = RC.getName(); @@ -129,17 +146,125 @@ OS << "} // end of namespace " << TargetName << "\n\n"; } OS << "} // End llvm namespace \n"; + OS << "#endif // GET_REGINFO_HEADER\n\n"; } // -// RegisterInfoEmitter::run - Main register file description emitter. +// runMCDesc - Print out MC register descriptions. // -void RegisterInfoEmitter::run(raw_ostream &OS) { - CodeGenTarget Target(Records); - CodeGenRegBank &RegBank = Target.getRegBank(); - RegBank.computeDerivedInfo(); +void +RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target, + CodeGenRegBank &RegBank) { + EmitSourceFileHeader("MC Register Information", OS); + + OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; + OS << "#undef GET_REGINFO_MC_DESC\n"; + + std::map Overlaps; + RegBank.computeOverlaps(Overlaps); + + OS << "namespace llvm {\n\n"; + + const std::string &TargetName = Target.getName(); + std::string ClassName = TargetName + "GenMCRegisterInfo"; + OS << "struct " << ClassName << " : public MCRegisterInfo {\n" + << " explicit " << ClassName << "(const MCRegisterDesc *D);\n"; + OS << "};\n"; + + OS << "\nnamespace {\n"; + + const std::vector &Regs = RegBank.getRegisters(); + + // Emit an overlap list for all registers. + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister *Reg = Regs[i]; + const CodeGenRegister::Set &O = Overlaps[Reg]; + // Move Reg to the front so TRI::getAliasSet can share the list. + OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { " + << getQualifiedName(Reg->TheDef) << ", "; + for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); + I != E; ++I) + if (*I != Reg) + OS << getQualifiedName((*I)->TheDef) << ", "; + OS << "0 };\n"; + } + + // Emit the empty sub-registers list + OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; + // Loop over all of the registers which have sub-registers, emitting the + // sub-registers list to memory. + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister &Reg = *Regs[i]; + if (Reg.getSubRegs().empty()) + continue; + // getSubRegs() orders by SubRegIndex. We want a topological order. + SetVector SR; + Reg.addSubRegsPreOrder(SR); + OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { "; + for (unsigned j = 0, je = SR.size(); j != je; ++j) + OS << getQualifiedName(SR[j]->TheDef) << ", "; + OS << "0 };\n"; + } + + // Emit the empty super-registers list + OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; + // Loop over all of the registers which have super-registers, emitting the + // super-registers list to memory. + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister &Reg = *Regs[i]; + const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs(); + if (SR.empty()) + continue; + OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { "; + for (unsigned j = 0, je = SR.size(); j != je; ++j) + OS << getQualifiedName(SR[j]->TheDef) << ", "; + OS << "0 };\n"; + } + + OS << "\n const MCRegisterDesc " << TargetName + << "RegDesc[] = { // Descriptors\n"; + OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; + + // Now that register alias and sub-registers sets have been emitted, emit the + // register descriptors now. + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister &Reg = *Regs[i]; + OS << " { \""; + OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; + if (!Reg.getSubRegs().empty()) + OS << Reg.getName() << "_SubRegsSet,\t"; + else + OS << "Empty_SubRegsSet,\t"; + if (!Reg.getSuperRegs().empty()) + OS << Reg.getName() << "_SuperRegsSet"; + else + OS << "Empty_SuperRegsSet"; + OS << " },\n"; + } + OS << " };\n"; // End of register descriptors... + + OS << "}\n\n"; // End of anonymous namespace... + + // MCRegisterInfo initialization routine. + OS << "static inline void Init" << TargetName + << "MCRegisterInfo(MCRegisterInfo *RI) {\n"; + OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " + << Regs.size()+1 << ");\n}\n\n"; + + OS << "} // End llvm namespace \n"; + OS << "#endif // GET_REGINFO_MC_DESC\n\n"; +} - EmitSourceFileHeader("Register Information Source Fragment", OS); +// +// runTargetDesc - Output the target register and register file descriptions. +// +void +RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target, + CodeGenRegBank &RegBank){ + EmitSourceFileHeader("Target Register and Register Classes Information", OS); + + OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; + OS << "#undef GET_REGINFO_TARGET_DESC\n"; OS << "namespace llvm {\n\n"; @@ -614,102 +739,16 @@ OS << " };\n}\n\n"; OS << "} // End llvm namespace \n"; + OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; } -void RegisterInfoEmitter::runDesc(raw_ostream &OS) { +void RegisterInfoEmitter::run(raw_ostream &OS) { CodeGenTarget Target(Records); CodeGenRegBank &RegBank = Target.getRegBank(); RegBank.computeDerivedInfo(); - std::map Overlaps; - RegBank.computeOverlaps(Overlaps); - - OS << "namespace llvm {\n\n"; - - const std::string &TargetName = Target.getName(); - std::string ClassName = TargetName + "GenMCRegisterInfo"; - OS << "struct " << ClassName << " : public MCRegisterInfo {\n" - << " explicit " << ClassName << "(const MCRegisterDesc *D);\n"; - OS << "};\n"; - OS << "\nnamespace {\n"; - - const std::vector &Regs = RegBank.getRegisters(); - - // Emit an overlap list for all registers. - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - const CodeGenRegister *Reg = Regs[i]; - const CodeGenRegister::Set &O = Overlaps[Reg]; - // Move Reg to the front so TRI::getAliasSet can share the list. - OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { " - << getQualifiedName(Reg->TheDef) << ", "; - for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end(); - I != E; ++I) - if (*I != Reg) - OS << getQualifiedName((*I)->TheDef) << ", "; - OS << "0 };\n"; - } - - // Emit the empty sub-registers list - OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; - // Loop over all of the registers which have sub-registers, emitting the - // sub-registers list to memory. - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - const CodeGenRegister &Reg = *Regs[i]; - if (Reg.getSubRegs().empty()) - continue; - // getSubRegs() orders by SubRegIndex. We want a topological order. - SetVector SR; - Reg.addSubRegsPreOrder(SR); - OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { "; - for (unsigned j = 0, je = SR.size(); j != je; ++j) - OS << getQualifiedName(SR[j]->TheDef) << ", "; - OS << "0 };\n"; - } - - // Emit the empty super-registers list - OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; - // Loop over all of the registers which have super-registers, emitting the - // super-registers list to memory. - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - const CodeGenRegister &Reg = *Regs[i]; - const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs(); - if (SR.empty()) - continue; - OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { "; - for (unsigned j = 0, je = SR.size(); j != je; ++j) - OS << getQualifiedName(SR[j]->TheDef) << ", "; - OS << "0 };\n"; - } - - OS << "\n const MCRegisterDesc " << TargetName - << "RegDesc[] = { // Descriptors\n"; - OS << " { \"NOREG\",\t0,\t0,\t0 },\n"; - - // Now that register alias and sub-registers sets have been emitted, emit the - // register descriptors now. - for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - const CodeGenRegister &Reg = *Regs[i]; - OS << " { \""; - OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; - if (!Reg.getSubRegs().empty()) - OS << Reg.getName() << "_SubRegsSet,\t"; - else - OS << "Empty_SubRegsSet,\t"; - if (!Reg.getSuperRegs().empty()) - OS << Reg.getName() << "_SuperRegsSet"; - else - OS << "Empty_SuperRegsSet"; - OS << " },\n"; - } - OS << " };\n"; // End of register descriptors... - - OS << "}\n\n"; // End of anonymous namespace... - - // MCRegisterInfo initialization routine. - OS << "static inline void Init" << TargetName - << "MCRegisterInfo(MCRegisterInfo *RI) {\n"; - OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " - << Regs.size()+1 << ");\n}\n\n"; - - OS << "} // End llvm namespace \n"; + runEnums(OS, Target, RegBank); + runHeader(OS, Target); + runMCDesc(OS, Target, RegBank); + runTargetDesc(OS, Target, RegBank); } Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.h?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.h (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.h Mon Jun 27 13:32:37 2011 @@ -20,22 +20,28 @@ namespace llvm { +class CodeGenRegBank; +class CodeGenTarget; + class RegisterInfoEmitter : public TableGenBackend { RecordKeeper &Records; public: RegisterInfoEmitter(RecordKeeper &R) : Records(R) {} - // run - Output the register file description, returning true on failure. - void run(raw_ostream &o); + // runEnums - Print out enum values for all of the registers. + void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); // runHeader - Emit a header fragment for the register info emitter. - void runHeader(raw_ostream &o); + void runHeader(raw_ostream &o, CodeGenTarget &Target); - // runEnums - Print out enum values for all of the registers. - void runEnums(raw_ostream &o); + // runMCDesc - Print out MC register descriptions. + void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); + + // runTargetDesc - Output the target register and register file descriptions. + void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); - // runDesc - Print out register descriptions. - void runDesc(raw_ostream &o); + // run - Output the register file description. + void run(raw_ostream &o); }; } // End llvm namespace Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=133922&r1=133921&r2=133922&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Mon Jun 27 13:32:37 2011 @@ -54,7 +54,7 @@ enum ActionType { PrintRecords, GenEmitter, - GenRegisterEnums, GenRegisterDesc, GenRegisterInfo, GenRegisterInfoHeader, + GenRegisterInfo, GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher, GenARMDecoder, GenDisassembler, @@ -93,14 +93,8 @@ "Print all records to stdout (default)"), clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"), - clEnumValN(GenRegisterEnums, "gen-register-enums", - "Generate enum values for registers"), - clEnumValN(GenRegisterDesc, "gen-register-desc", - "Generate register descriptions"), clEnumValN(GenRegisterInfo, "gen-register-info", - "Generate registers & reg-classes info"), - clEnumValN(GenRegisterInfoHeader, "gen-register-info-header", - "Generate registers & reg-classes info header"), + "Generate registers and register classes info"), clEnumValN(GenInstrEnums, "gen-instr-enums", "Generate enum values for instructions"), clEnumValN(GenInstrs, "gen-instr-desc", @@ -263,18 +257,9 @@ case GenEmitter: CodeEmitterGen(Records).run(Out.os()); break; - case GenRegisterEnums: - RegisterInfoEmitter(Records).runEnums(Out.os()); - break; - case GenRegisterDesc: - RegisterInfoEmitter(Records).runDesc(Out.os()); - break; case GenRegisterInfo: RegisterInfoEmitter(Records).run(Out.os()); break; - case GenRegisterInfoHeader: - RegisterInfoEmitter(Records).runHeader(Out.os()); - break; case GenInstrEnums: InstrEnumEmitter(Records).run(Out.os()); break; From resistor at mac.com Mon Jun 27 13:34:12 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 27 Jun 2011 18:34:12 -0000 Subject: [llvm-commits] [llvm] r133923 - /llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h Message-ID: <20110627183412.9FA9D2A6C12C@llvm.org> Author: resistor Date: Mon Jun 27 13:34:12 2011 New Revision: 133923 URL: http://llvm.org/viewvc/llvm-project?rev=133923&view=rev Log: The index stored in the RegDefIter is one after the current index. When getting the index, decrement it so that it points to the current element. Fixes an off-by-one bug encountered when trying to make use of MVT::untyped. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h?rev=133923&r1=133922&r2=133923&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h Mon Jun 27 13:34:12 2011 @@ -140,7 +140,7 @@ } unsigned GetIdx() const { - return DefIdx; + return DefIdx-1; } void Advance(); From grosbach at apple.com Mon Jun 27 14:09:15 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 27 Jun 2011 19:09:15 -0000 Subject: [llvm-commits] [llvm] r133925 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/arm-arithmetic-aliases.s Message-ID: <20110627190915.3E9B42A6C12C@llvm.org> Author: grosbach Date: Mon Jun 27 14:09:15 2011 New Revision: 133925 URL: http://llvm.org/viewvc/llvm-project?rev=133925&view=rev Log: ARM Assembly syntax support for arithmetic implied dest operand. When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: sub r2, r2, #6 sub r2, #6 rdar://9682597 Added: llvm/trunk/test/MC/ARM/arm-arithmetic-aliases.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=133925&r1=133924&r2=133925&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jun 27 14:09:15 2011 @@ -676,7 +676,7 @@ /// binop that produces a value. multiclass AsI1_bin_irs opcod, string opc, InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, - PatFrag opnode, bit Commutable = 0> { + PatFrag opnode, string baseOpc, bit Commutable = 0> { // The register-immediate version is re-materializable. This is useful // in particular for taking the address of a local. let isReMaterializable = 1 in { @@ -716,6 +716,24 @@ let Inst{15-12} = Rd; let Inst{11-0} = shift; } + + // Assembly aliases for optional destination operand when it's the same + // as the source operand. + def : InstAlias(!strconcat(baseOpc, "ri")) GPR:$Rdn, GPR:$Rdn, + so_imm:$imm, pred:$p, + cc_out:$s)>, + Requires<[IsARM]>; + def : InstAlias(!strconcat(baseOpc, "rr")) GPR:$Rdn, GPR:$Rdn, + GPR:$Rm, pred:$p, + cc_out:$s)>, + Requires<[IsARM]>; + def : InstAlias(!strconcat(baseOpc, "rs")) GPR:$Rdn, GPR:$Rdn, + so_reg:$shift, pred:$p, + cc_out:$s)>, + Requires<[IsARM]>; } /// AI1_bin_s_irs - Similar to AsI1_bin_irs except it sets the 's' bit so the @@ -2205,10 +2223,10 @@ defm ADD : AsI1_bin_irs<0b0100, "add", IIC_iALUi, IIC_iALUr, IIC_iALUsr, - BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; + BinOpFrag<(add node:$LHS, node:$RHS)>, "ADD", 1>; defm SUB : AsI1_bin_irs<0b0010, "sub", IIC_iALUi, IIC_iALUr, IIC_iALUsr, - BinOpFrag<(sub node:$LHS, node:$RHS)>>; + BinOpFrag<(sub node:$LHS, node:$RHS)>, "SUB">; // ADD and SUB with 's' bit set. defm ADDS : AI1_bin_s_irs<0b0100, "adds", @@ -2531,16 +2549,16 @@ defm AND : AsI1_bin_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsr, - BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; + BinOpFrag<(and node:$LHS, node:$RHS)>, "AND", 1>; defm ORR : AsI1_bin_irs<0b1100, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsr, - BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; + BinOpFrag<(or node:$LHS, node:$RHS)>, "ORR", 1>; defm EOR : AsI1_bin_irs<0b0001, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsr, - BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; + BinOpFrag<(xor node:$LHS, node:$RHS)>, "EOR", 1>; defm BIC : AsI1_bin_irs<0b1110, "bic", IIC_iBITi, IIC_iBITr, IIC_iBITsr, - BinOpFrag<(and node:$LHS, (not node:$RHS))>>; + BinOpFrag<(and node:$LHS, (not node:$RHS))>, "BIC">; def BFC : I<(outs GPR:$Rd), (ins GPR:$src, bf_inv_mask_imm:$imm), AddrMode1, Size4Bytes, IndexModeNone, DPFrm, IIC_iUNAsi, Added: llvm/trunk/test/MC/ARM/arm-arithmetic-aliases.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm-arithmetic-aliases.s?rev=133925&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/arm-arithmetic-aliases.s (added) +++ llvm/trunk/test/MC/ARM/arm-arithmetic-aliases.s Mon Jun 27 14:09:15 2011 @@ -0,0 +1,126 @@ +@ RUN: llvm-mc -triple arm-unknown-unknown -show-encoding < %s | FileCheck %s + +foo: +@ CHECK: foo + +sub r2, r2, #6 +sub r2, #6 +sub r2, r2, r3 +sub r2, r3 + +@ CHECK: sub r2, r2, #6 @ encoding: [0x06,0x20,0x42,0xe2] +@ CHECK: sub r2, r2, #6 @ encoding: [0x06,0x20,0x42,0xe2] +@ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0] +@ CHECK: sub r2, r2, r3 @ encoding: [0x03,0x20,0x42,0xe0] + +add r2, r2, #6 +add r2, #6 +add r2, r2, r3 +add r2, r3 + +@ CHECK: add r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe2] +@ CHECK: add r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe2] +@ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0] +@ CHECK: add r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe0] + +and r2, r2, #6 +and r2, #6 +and r2, r2, r3 +and r2, r3 + +@ CHECK: and r2, r2, #6 @ encoding: [0x06,0x20,0x02,0xe2] +@ CHECK: and r2, r2, #6 @ encoding: [0x06,0x20,0x02,0xe2] +@ CHECK: and r2, r2, r3 @ encoding: [0x03,0x20,0x02,0xe0] +@ CHECK: and r2, r2, r3 @ encoding: [0x03,0x20,0x02,0xe0] + +orr r2, r2, #6 +orr r2, #6 +orr r2, r2, r3 +orr r2, r3 + +@ CHECK: orr r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe3] +@ CHECK: orr r2, r2, #6 @ encoding: [0x06,0x20,0x82,0xe3] +@ CHECK: orr r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe1] +@ CHECK: orr r2, r2, r3 @ encoding: [0x03,0x20,0x82,0xe1] + +eor r2, r2, #6 +eor r2, #6 +eor r2, r2, r3 +eor r2, r3 + +@ CHECK: eor r2, r2, #6 @ encoding: [0x06,0x20,0x22,0xe2] +@ CHECK: eor r2, r2, #6 @ encoding: [0x06,0x20,0x22,0xe2] +@ CHECK: eor r2, r2, r3 @ encoding: [0x03,0x20,0x22,0xe0] +@ CHECK: eor r2, r2, r3 @ encoding: [0x03,0x20,0x22,0xe0] + +bic r2, r2, #6 +bic r2, #6 +bic r2, r2, r3 +bic r2, r3 + +@ CHECK: bic r2, r2, #6 @ encoding: [0x06,0x20,0xc2,0xe3] +@ CHECK: bic r2, r2, #6 @ encoding: [0x06,0x20,0xc2,0xe3] +@ CHECK: bic r2, r2, r3 @ encoding: [0x03,0x20,0xc2,0xe1] +@ CHECK: bic r2, r2, r3 @ encoding: [0x03,0x20,0xc2,0xe1] + + +@ Also check that we handle the predicate and cc_out operands. +subseq r2, r2, #6 +subseq r2, #6 +subseq r2, r2, r3 +subseq r2, r3 + +@ CHECK: subseq r2, r2, #6 @ encoding: [0x06,0x20,0x52,0x02] +@ CHECK: subseq r2, r2, #6 @ encoding: [0x06,0x20,0x52,0x02] +@ CHECK: subseq r2, r2, r3 @ encoding: [0x03,0x20,0x52,0x00] +@ CHECK: subseq r2, r2, r3 @ encoding: [0x03,0x20,0x52,0x00] + +addseq r2, r2, #6 +addseq r2, #6 +addseq r2, r2, r3 +addseq r2, r3 + +@ CHECK: addseq r2, r2, #6 @ encoding: [0x06,0x20,0x92,0x02] +@ CHECK: addseq r2, r2, #6 @ encoding: [0x06,0x20,0x92,0x02] +@ CHECK: addseq r2, r2, r3 @ encoding: [0x03,0x20,0x92,0x00] +@ CHECK: addseq r2, r2, r3 @ encoding: [0x03,0x20,0x92,0x00] + +andseq r2, r2, #6 +andseq r2, #6 +andseq r2, r2, r3 +andseq r2, r3 + +@ CHECK: andseq r2, r2, #6 @ encoding: [0x06,0x20,0x12,0x02] +@ CHECK: andseq r2, r2, #6 @ encoding: [0x06,0x20,0x12,0x02] +@ CHECK: andseq r2, r2, r3 @ encoding: [0x03,0x20,0x12,0x00] +@ CHECK: andseq r2, r2, r3 @ encoding: [0x03,0x20,0x12,0x00] + +orrseq r2, r2, #6 +orrseq r2, #6 +orrseq r2, r2, r3 +orrseq r2, r3 + +@ CHECK: orrseq r2, r2, #6 @ encoding: [0x06,0x20,0x92,0x03] +@ CHECK: orrseq r2, r2, #6 @ encoding: [0x06,0x20,0x92,0x03] +@ CHECK: orrseq r2, r2, r3 @ encoding: [0x03,0x20,0x92,0x01] +@ CHECK: orrseq r2, r2, r3 @ encoding: [0x03,0x20,0x92,0x01] + +eorseq r2, r2, #6 +eorseq r2, #6 +eorseq r2, r2, r3 +eorseq r2, r3 + +@ CHECK: eorseq r2, r2, #6 @ encoding: [0x06,0x20,0x32,0x02] +@ CHECK: eorseq r2, r2, #6 @ encoding: [0x06,0x20,0x32,0x02] +@ CHECK: eorseq r2, r2, r3 @ encoding: [0x03,0x20,0x32,0x00] +@ CHECK: eorseq r2, r2, r3 @ encoding: [0x03,0x20,0x32,0x00] + +bicseq r2, r2, #6 +bicseq r2, #6 +bicseq r2, r2, r3 +bicseq r2, r3 + +@ CHECK: bicseq r2, r2, #6 @ encoding: [0x06,0x20,0xd2,0x03] +@ CHECK: bicseq r2, r2, #6 @ encoding: [0x06,0x20,0xd2,0x03] +@ CHECK: bicseq r2, r2, r3 @ encoding: [0x03,0x20,0xd2,0x01] +@ CHECK: bicseq r2, r2, r3 @ encoding: [0x03,0x20,0xd2,0x01] From evan.cheng at apple.com Mon Jun 27 14:24:13 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 27 Jun 2011 19:24:13 -0000 Subject: [llvm-commits] [llvm] r133927 - in /llvm/trunk/utils/TableGen: RegisterInfoEmitter.cpp RegisterInfoEmitter.h Message-ID: <20110627192413.888F32A6C12C@llvm.org> Author: evancheng Date: Mon Jun 27 14:24:13 2011 New Revision: 133927 URL: http://llvm.org/viewvc/llvm-project?rev=133927&view=rev Log: More refactoring. MC doesn't need know about subreg indices. Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp llvm/trunk/utils/TableGen/RegisterInfoEmitter.h Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=133927&r1=133926&r2=133927&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Mon Jun 27 14:24:13 2011 @@ -53,24 +53,8 @@ if (!Namespace.empty()) OS << "}\n"; - const std::vector &SubRegIndices = Bank.getSubRegIndices(); - if (!SubRegIndices.empty()) { - OS << "\n// Subregister indices\n"; - Namespace = SubRegIndices[0]->getValueAsString("Namespace"); - if (!Namespace.empty()) - OS << "namespace " << Namespace << " {\n"; - OS << "enum {\n NoSubRegister,\n"; - for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i) - OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; - OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; - OS << "};\n"; - if (!Namespace.empty()) - OS << "}\n"; - } - const std::vector &RegisterClasses = Target.getRegisterClasses(); - if (!RegisterClasses.empty()) { OS << "\n// Register classes\n"; OS << "namespace " << RegisterClasses[0].Namespace << " {\n"; @@ -88,67 +72,6 @@ OS << "#endif // GET_REGINFO_ENUM\n\n"; } -void RegisterInfoEmitter::runHeader(raw_ostream &OS, CodeGenTarget &Target) { - EmitSourceFileHeader("Register Information Header Fragment", OS); - - OS << "\n#ifdef GET_REGINFO_HEADER\n"; - OS << "#undef GET_REGINFO_HEADER\n"; - - const std::string &TargetName = Target.getName(); - std::string ClassName = TargetName + "GenRegisterInfo"; - - OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; - OS << "#include \n\n"; - - OS << "namespace llvm {\n\n"; - - OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" - << " explicit " << ClassName - << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, " - << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" - << " virtual int getDwarfRegNumFull(unsigned RegNum, " - << "unsigned Flavour) const;\n" - << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " - << "unsigned Flavour) const;\n" - << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" - << " virtual bool needsStackRealignment(const MachineFunction &) const\n" - << " { return false; }\n" - << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" - << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n" - << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" - << "};\n\n"; - - const std::vector &RegisterClasses = - Target.getRegisterClasses(); - - if (!RegisterClasses.empty()) { - OS << "namespace " << RegisterClasses[0].Namespace - << " { // Register classes\n"; - - for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { - const CodeGenRegisterClass &RC = RegisterClasses[i]; - const std::string &Name = RC.getName(); - - // Output the register class definition. - OS << " struct " << Name << "Class : public TargetRegisterClass {\n" - << " " << Name << "Class();\n"; - if (!RC.AltOrderSelect.empty()) - OS << " ArrayRef " - "getRawAllocationOrder(const MachineFunction&) const;\n"; - OS << " };\n"; - - // Output the extern for the instance. - OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; - // Output the extern for the pointer to the instance (should remove). - OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" - << Name << "RegClass;\n"; - } - OS << "} // end of namespace " << TargetName << "\n\n"; - } - OS << "} // End llvm namespace \n"; - OS << "#endif // GET_REGINFO_HEADER\n\n"; -} - // // runMCDesc - Print out MC register descriptions. // @@ -255,6 +178,84 @@ OS << "#endif // GET_REGINFO_MC_DESC\n\n"; } +void +RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target, + CodeGenRegBank &RegBank) { + EmitSourceFileHeader("Register Information Header Fragment", OS); + + OS << "\n#ifdef GET_REGINFO_HEADER\n"; + OS << "#undef GET_REGINFO_HEADER\n"; + + const std::string &TargetName = Target.getName(); + std::string ClassName = TargetName + "GenRegisterInfo"; + + OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; + OS << "#include \n\n"; + + OS << "namespace llvm {\n\n"; + + OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" + << " explicit " << ClassName + << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, " + << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" + << " virtual int getDwarfRegNumFull(unsigned RegNum, " + << "unsigned Flavour) const;\n" + << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " + << "unsigned Flavour) const;\n" + << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" + << " virtual bool needsStackRealignment(const MachineFunction &) const\n" + << " { return false; }\n" + << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" + << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n" + << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" + << "};\n\n"; + + const std::vector &SubRegIndices = RegBank.getSubRegIndices(); + if (!SubRegIndices.empty()) { + OS << "\n// Subregister indices\n"; + std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace"); + if (!Namespace.empty()) + OS << "namespace " << Namespace << " {\n"; + OS << "enum {\n NoSubRegister,\n"; + for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i) + OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n"; + OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n"; + OS << "};\n"; + if (!Namespace.empty()) + OS << "}\n"; + } + + const std::vector &RegisterClasses = + Target.getRegisterClasses(); + + if (!RegisterClasses.empty()) { + OS << "namespace " << RegisterClasses[0].Namespace + << " { // Register classes\n"; + + for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { + const CodeGenRegisterClass &RC = RegisterClasses[i]; + const std::string &Name = RC.getName(); + + // Output the register class definition. + OS << " struct " << Name << "Class : public TargetRegisterClass {\n" + << " " << Name << "Class();\n"; + if (!RC.AltOrderSelect.empty()) + OS << " ArrayRef " + "getRawAllocationOrder(const MachineFunction&) const;\n"; + OS << " };\n"; + + // Output the extern for the instance. + OS << " extern " << Name << "Class\t" << Name << "RegClass;\n"; + // Output the extern for the pointer to the instance (should remove). + OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &" + << Name << "RegClass;\n"; + } + OS << "} // end of namespace " << TargetName << "\n\n"; + } + OS << "} // End llvm namespace \n"; + OS << "#endif // GET_REGINFO_HEADER\n\n"; +} + // // runTargetDesc - Output the target register and register file descriptions. // @@ -748,7 +749,7 @@ RegBank.computeDerivedInfo(); runEnums(OS, Target, RegBank); - runHeader(OS, Target); runMCDesc(OS, Target, RegBank); + runTargetHeader(OS, Target, RegBank); runTargetDesc(OS, Target, RegBank); } Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.h?rev=133927&r1=133926&r2=133927&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.h (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.h Mon Jun 27 14:24:13 2011 @@ -31,14 +31,16 @@ // runEnums - Print out enum values for all of the registers. void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); - // runHeader - Emit a header fragment for the register info emitter. - void runHeader(raw_ostream &o, CodeGenTarget &Target); - // runMCDesc - Print out MC register descriptions. void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); + // runTargetHeader - Emit a header fragment for the register info emitter. + void runTargetHeader(raw_ostream &o, CodeGenTarget &Target, + CodeGenRegBank &Bank); + // runTargetDesc - Output the target register and register file descriptions. - void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank); + void runTargetDesc(raw_ostream &o, CodeGenTarget &Target, + CodeGenRegBank &Bank); // run - Output the register file description. void run(raw_ostream &o); From evan.cheng at apple.com Mon Jun 27 14:41:39 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 27 Jun 2011 19:41:39 -0000 Subject: [llvm-commits] [llvm] r133928 - /llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Message-ID: <20110627194139.7434D2A6C12C@llvm.org> Author: evancheng Date: Mon Jun 27 14:41:39 2011 New Revision: 133928 URL: http://llvm.org/viewvc/llvm-project?rev=133928&view=rev Log: Rename unnecessary forward declaration. Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=133928&r1=133927&r2=133928&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Mon Jun 27 14:41:39 2011 @@ -28,7 +28,6 @@ class BitVector; class MachineFunction; -class MachineMove; class RegScavenger; template class SmallVectorImpl; class raw_ostream; From grosbach at apple.com Mon Jun 27 15:00:07 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 27 Jun 2011 20:00:07 -0000 Subject: [llvm-commits] [llvm] r133932 - in /llvm/trunk: lib/Target/ARM/ARMInstrVFP.td test/MC/ARM/vpush-vpop.s Message-ID: <20110627200007.9E0CF2A6C12C@llvm.org> Author: grosbach Date: Mon Jun 27 15:00:07 2011 New Revision: 133932 URL: http://llvm.org/viewvc/llvm-project?rev=133932&view=rev Log: ARM assembler support for vpush/vpop. Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple writeback instructions w/ SP as the base pointer. rdar://9683231 Added: llvm/trunk/test/MC/ARM/vpush-vpop.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Modified: llvm/trunk/lib/Target/ARM/ARMInstrVFP.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrVFP.td?rev=133932&r1=133931&r2=133932&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrVFP.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrVFP.td Mon Jun 27 15:00:07 2011 @@ -166,6 +166,15 @@ def : MnemonicAlias<"vldm", "vldmia">; def : MnemonicAlias<"vstm", "vstmia">; +def : InstAlias<"vpush${p} $r", (VSTMDDB_UPD SP, pred:$p, dpr_reglist:$r)>, + Requires<[HasVFP2]>; +def : InstAlias<"vpush${p} $r", (VSTMSDB_UPD SP, pred:$p, spr_reglist:$r)>, + Requires<[HasVFP2]>; +def : InstAlias<"vpop${p} $r", (VLDMDIA_UPD SP, pred:$p, dpr_reglist:$r)>, + Requires<[HasVFP2]>; +def : InstAlias<"vpop${p} $r", (VLDMSIA_UPD SP, pred:$p, spr_reglist:$r)>, + Requires<[HasVFP2]>; + // FLDMX, FSTMX - mixing S/D registers for pre-armv6 cores //===----------------------------------------------------------------------===// Added: llvm/trunk/test/MC/ARM/vpush-vpop.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/vpush-vpop.s?rev=133932&view=auto ============================================================================== --- llvm/trunk/test/MC/ARM/vpush-vpop.s (added) +++ llvm/trunk/test/MC/ARM/vpush-vpop.s Mon Jun 27 15:00:07 2011 @@ -0,0 +1,19 @@ +@ RUN: llvm-mc -triple armv7-unknown-unknown -show-encoding < %s | FileCheck --check-prefix=CHECK-ARM %s +@ RUN: llvm-mc -triple thumbv7-unknown-unknown -show-encoding < %s | FileCheck --check-prefix=CHECK-THUMB %s + +foo: +@ CHECK: foo + vpush {d8, d9, d10, d11, d12} + vpush {s8, s9, s10, s11, s12} + vpop {d8, d9, d10, d11, d12} + vpop {s8, s9, s10, s11, s12} + +@ CHECK-THUMB: vpush {d8, d9, d10, d11, d12} @ encoding: [0x2d,0xed,0x0a,0x8b] +@ CHECK-THUMB: vpush {s8, s9, s10, s11, s12} @ encoding: [0x2d,0xed,0x05,0x4a] +@ CHECK-THUMB: vpop {d8, d9, d10, d11, d12} @ encoding: [0xbd,0xec,0x0a,0x8b] +@ CHECK-THUMB: vpop {s8, s9, s10, s11, s12} @ encoding: [0xbd,0xec,0x05,0x4a] + +@ CHECK-ARM: vpush {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0x2d,0xed] +@ CHECK-ARM: vpush {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0x2d,0xed] +@ CHECK-ARM: vpop {d8, d9, d10, d11, d12} @ encoding: [0x0a,0x8b,0xbd,0xec] +@ CHECK-ARM: vpop {s8, s9, s10, s11, s12} @ encoding: [0x05,0x4a,0xbd,0xec] From echristo at apple.com Mon Jun 27 15:31:02 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 27 Jun 2011 20:31:02 -0000 Subject: [llvm-commits] [llvm] r133935 - /llvm/trunk/test/CodeGen/ARM/arm-modifier.ll Message-ID: <20110627203102.2AC832A6C12C@llvm.org> Author: echristo Date: Mon Jun 27 15:31:01 2011 New Revision: 133935 URL: http://llvm.org/viewvc/llvm-project?rev=133935&view=rev Log: Allow lr in the register options here. Modified: llvm/trunk/test/CodeGen/ARM/arm-modifier.ll Modified: llvm/trunk/test/CodeGen/ARM/arm-modifier.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/arm-modifier.ll?rev=133935&r1=133934&r2=133935&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/arm-modifier.ll (original) +++ llvm/trunk/test/CodeGen/ARM/arm-modifier.ll Mon Jun 27 15:31:01 2011 @@ -46,9 +46,9 @@ define void @f3() nounwind { entry: ; CHECK: f3 -; CHECK: stm r{{[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}} -; CHECK: adds lr, [[REG1]] -; CHECK: ldm r{{[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}} +; CHECK: stm {{lr|r[0-9]+}}, {[[REG1:(r[0-9]+)]], r{{[0-9]+}}} +; CHECK: adds {{lr|r[0-9]+}}, [[REG1]] +; CHECK: ldm {{lr|r[0-9]+}}, {r{{[0-9]+}}, r{{[0-9]+}}} %tmp = load i64* @f3_var, align 4 %tmp1 = load i64* @f3_var2, align 4 %0 = call i64 asm sideeffect "stm ${0:m}, ${1:M}\0A\09adds $3, $1\0A\09", "=*m,=r,1,r"(i64** @f3_ptr, i64 %tmp, i64 %tmp1) nounwind From grosbach at apple.com Mon Jun 27 15:32:18 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 27 Jun 2011 20:32:18 -0000 Subject: [llvm-commits] [llvm] r133936 - in /llvm/trunk: lib/Target/ARM/ARMInstrInfo.td test/MC/ARM/arm_instructions.s Message-ID: <20110627203218.46DA12A6C12C@llvm.org> Author: grosbach Date: Mon Jun 27 15:32:18 2011 New Revision: 133936 URL: http://llvm.org/viewvc/llvm-project?rev=133936&view=rev Log: ARM assembler support for ldmfd/stmfd mnemonics. Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td llvm/trunk/test/MC/ARM/arm_instructions.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=133936&r1=133935&r2=133936&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Mon Jun 27 15:32:18 2011 @@ -2006,6 +2006,8 @@ } // neverHasSideEffects // Load / Store Multiple Mnemonic Aliases +def : MnemonicAlias<"ldmfd", "ldmia">; +def : MnemonicAlias<"stmfd", "stmdb">; def : MnemonicAlias<"ldm", "ldmia">; def : MnemonicAlias<"stm", "stmia">; Modified: llvm/trunk/test/MC/ARM/arm_instructions.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/arm_instructions.s?rev=133936&r1=133935&r2=133936&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/arm_instructions.s (original) +++ llvm/trunk/test/MC/ARM/arm_instructions.s Mon Jun 27 15:32:18 2011 @@ -21,22 +21,30 @@ vqdmull.s32 q8, d17, d16 @ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] +@ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] @ CHECK: ldmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe9] @ CHECK: ldmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe8] @ CHECK: ldmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x12,0xe9] +@ CHECK: ldmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x92,0xe8] + ldm r2, {r1,r3-r6,sp} ldmia r2, {r1,r3-r6,sp} ldmib r2, {r1,r3-r6,sp} ldmda r2, {r1,r3-r6,sp} ldmdb r2, {r1,r3-r6,sp} + ldmfd r2, {r1,r3-r6,sp} @ CHECK: stmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] +@ CHECK: stmia r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe8] @ CHECK: stmib r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x82,0xe9] @ CHECK: stmda r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe8] @ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9] +@ CHECK: stmdb r2, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0x02,0xe9] + stm r2, {r1,r3-r6,sp} stmia r2, {r1,r3-r6,sp} stmib r2, {r1,r3-r6,sp} stmda r2, {r1,r3-r6,sp} stmdb r2, {r1,r3-r6,sp} + stmfd r2, {r1,r3-r6,sp} @ CHECK: ldmia r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe8] @ CHECK: ldmib r2!, {r1, r3, r4, r5, r6, sp} @ encoding: [0x7a,0x20,0xb2,0xe9] From grosbach at apple.com Mon Jun 27 15:40:30 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 27 Jun 2011 20:40:30 -0000 Subject: [llvm-commits] [llvm] r133938 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110627204030.1F00E2A6C12C@llvm.org> Author: grosbach Date: Mon Jun 27 15:40:29 2011 New Revision: 133938 URL: http://llvm.org/viewvc/llvm-project?rev=133938&view=rev Log: ARM assembly carry set/clear condition code aliases for 'hi/lo' Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=133938&r1=133937&r2=133938&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jun 27 15:40:29 2011 @@ -1769,7 +1769,9 @@ .Case("eq", ARMCC::EQ) .Case("ne", ARMCC::NE) .Case("hs", ARMCC::HS) + .Case("cs", ARMCC::HS) .Case("lo", ARMCC::LO) + .Case("cc", ARMCC::LO) .Case("mi", ARMCC::MI) .Case("pl", ARMCC::PL) .Case("vs", ARMCC::VS) From grosbach at apple.com Mon Jun 27 15:59:10 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 27 Jun 2011 20:59:10 -0000 Subject: [llvm-commits] [llvm] r133939 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110627205910.D23322A6C12C@llvm.org> Author: grosbach Date: Mon Jun 27 15:59:10 2011 New Revision: 133939 URL: http://llvm.org/viewvc/llvm-project?rev=133939&view=rev Log: Add exception necessitated by 133938. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=133939&r1=133938&r2=133939&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jun 27 15:59:10 2011 @@ -1761,7 +1761,7 @@ Mnemonic == "vcle" || (Mnemonic == "smlal" || Mnemonic == "umaal" || Mnemonic == "umlal" || Mnemonic == "vabal" || Mnemonic == "vmlal" || Mnemonic == "vpadal" || - Mnemonic == "vqdmlal")) + Mnemonic == "vqdmlal" || Mnemonic == "bics")) return Mnemonic; // First, split out any predication code. From resistor at mac.com Mon Jun 27 16:06:21 2011 From: resistor at mac.com (Owen Anderson) Date: Mon, 27 Jun 2011 21:06:21 -0000 Subject: [llvm-commits] [llvm] r133940 - in /llvm/trunk: include/llvm/Target/ utils/TableGen/ Message-ID: <20110627210622.127C32A6C12C@llvm.org> Author: resistor Date: Mon Jun 27 16:06:21 2011 New Revision: 133940 URL: http://llvm.org/viewvc/llvm-project?rev=133940&view=rev Log: Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. Patch by Jim Grosbach. Modified: llvm/trunk/include/llvm/Target/Target.td llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp llvm/trunk/utils/TableGen/CodeGenInstruction.cpp llvm/trunk/utils/TableGen/CodeGenTarget.cpp llvm/trunk/utils/TableGen/CodeGenTarget.h llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp llvm/trunk/utils/TableGen/FastISelEmitter.cpp llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp llvm/trunk/utils/TableGen/Record.cpp llvm/trunk/utils/TableGen/Record.h llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/Target.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/Target.td?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/Target.td (original) +++ llvm/trunk/include/llvm/Target/Target.td Mon Jun 27 16:06:21 2011 @@ -26,11 +26,19 @@ string Namespace = ""; } +// RegAltNameIndex - The alternate name set to use for register operands of +// this register class when printing. +class RegAltNameIndex { + string Namespace = ""; +} +def NoRegAltName : RegAltNameIndex; + // Register - You should define one instance of this class for each register // in the target machine. String n will become the "name" of the register. -class Register { +class Register altNames = []> { string Namespace = ""; string AsmName = n; + list AltNames = altNames; // Aliases - A list of registers that this register overlaps with. A read or // modification of this register can potentially read or modify the aliased @@ -48,6 +56,10 @@ // SubRegs. list SubRegIndices = []; + // RegAltNameIndices - The alternate name indices which are valid for this + // register. + list RegAltNameIndices = []; + // CompositeIndices - Specify subreg indices that don't correspond directly to // a register in SubRegs and are not inherited. The following formats are // supported: @@ -92,7 +104,7 @@ // registers by register allocators. // class RegisterClass regTypes, int alignment, - dag regList> { + dag regList, RegAltNameIndex idx = NoRegAltName> { string Namespace = namespace; // RegType - Specify the list ValueType of the registers in this register @@ -124,6 +136,11 @@ // dag MemberList = regList; + // AltNameIndex - The alternate register name to use when printing operands + // of this register class. Every register in the register class must have + // a valid alternate name for the given index. + RegAltNameIndex altNameIndex = idx; + // SubRegClasses - Specify the register class of subregisters as a list of // dags: (RegClass SubRegIndex, SubRegindex, ...) list SubRegClasses = []; @@ -466,6 +483,24 @@ AsmOperandClass ParserMatchClass = ImmAsmOperand; } +class RegisterOperand { + // RegClass - The register class of the operand. + RegisterClass RegClass = regclass; + // PrintMethod - The target method to call to print register operands of + // this type. The method normally will just use an alt-name index to look + // up the name to print. Default to the generic printOperand(). + string PrintMethod = pm; + // ParserMatchClass - The "match class" that operands of this type fit + // in. Match classes are used to define the order in which instructions are + // match, to ensure that which instructions gets matched is deterministic. + // + // The target specific parser must be able to classify an parsed operand into + // a unique class, which does not partially overlap with any other classes. It + // can match a subset of some other class, in which case the AsmOperandClass + // should declare the other operand as one of its super classes. + AsmOperandClass ParserMatchClass; +} + def i1imm : Operand; def i8imm : Operand; def i16imm : Operand; Modified: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp Mon Jun 27 16:06:21 2011 @@ -871,6 +871,31 @@ if (SubOpIdx != -1) Rec = dynamic_cast(OI.MIOperandInfo->getArg(SubOpIdx))->getDef(); + if (Rec->isSubClassOf("RegisterOperand")) { + // RegisterOperand may have an associated ParserMatchClass. If it does, + // use it, else just fall back to the underlying register class. + const RecordVal *R = Rec->getValue("ParserMatchClass"); + if (R == 0 || R->getValue() == 0) + throw "Record `" + Rec->getName() + + "' does not have a ParserMatchClass!\n"; + + if (DefInit *DI= dynamic_cast(R->getValue())) { + Record *MatchClass = DI->getDef(); + if (ClassInfo *CI = AsmOperandClasses[MatchClass]) + return CI; + } + + // No custom match class. Just use the register class. + Record *ClassRec = Rec->getValueAsDef("RegClass"); + if (!ClassRec) + throw TGError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() + + "' has no associated register class!\n"); + if (ClassInfo *CI = RegisterClassClasses[ClassRec]) + return CI; + throw TGError(Rec->getLoc(), "register class has no class info!"); + } + + if (Rec->isSubClassOf("RegisterClass")) { if (ClassInfo *CI = RegisterClassClasses[Rec]) return CI; Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Mon Jun 27 16:06:21 2011 @@ -18,6 +18,7 @@ #include "CodeGenTarget.h" #include "Record.h" #include "StringToOffsetTable.h" +#include "llvm/ADT/Twine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/MathExtras.h" #include @@ -458,6 +459,58 @@ O << "}\n"; } +static void +emitRegisterNameString(raw_ostream &O, StringRef AltName, + const std::vector &Registers) { + StringToOffsetTable StringTable; + O << " static const unsigned RegAsmOffset" << AltName << "[] = {\n "; + for (unsigned i = 0, e = Registers.size(); i != e; ++i) { + const CodeGenRegister &Reg = *Registers[i]; + + StringRef AsmName; + // "NoRegAltName" is special. We don't need to do a lookup for that, + // as it's just a reference to the default register name. + if (AltName == "" || AltName == "NoRegAltName") { + AsmName = Reg.TheDef->getValueAsString("AsmName"); + if (AsmName.empty()) + AsmName = Reg.getName(); + } else { + // Make sure the register has an alternate name for this index. + std::vector AltNameList = + Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices"); + unsigned Idx = 0, e; + for (e = AltNameList.size(); + Idx < e && (AltNameList[Idx]->getName() != AltName); + ++Idx) + ; + // If the register has an alternate name for this index, use it. + // Otherwise, leave it empty as an error flag. + if (Idx < e) { + std::vector AltNames = + Reg.TheDef->getValueAsListOfStrings("AltNames"); + if (AltNames.size() <= Idx) + throw TGError(Reg.TheDef->getLoc(), + (Twine("Register definition missing alt name for '") + + AltName + "'.").str()); + AsmName = AltNames[Idx]; + } + } + + O << StringTable.GetOrAddStringOffset(AsmName); + if (((i + 1) % 14) == 0) + O << ",\n "; + else + O << ", "; + + } + O << "0\n" + << " };\n" + << "\n"; + + O << " const char *AsmStrs" << AltName << " =\n"; + StringTable.EmitString(O); + O << ";\n"; +} void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { CodeGenTarget Target(Records); @@ -465,40 +518,48 @@ std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); const std::vector &Registers = Target.getRegBank().getRegisters(); + std::vector AltNameIndices = Target.getRegAltNameIndices(); + bool hasAltNames = AltNameIndices.size() > 1; - StringToOffsetTable StringTable; O << "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" "/// from the register set description. This returns the assembler name\n" "/// for the specified register.\n" - "const char *" << Target.getName() << ClassName - << "::getRegisterName(unsigned RegNo) {\n" - << " assert(RegNo && RegNo < " << (Registers.size()+1) - << " && \"Invalid register number!\");\n" - << "\n" - << " static const unsigned RegAsmOffset[] = {"; - for (unsigned i = 0, e = Registers.size(); i != e; ++i) { - const CodeGenRegister &Reg = *Registers[i]; - - std::string AsmName = Reg.TheDef->getValueAsString("AsmName"); - if (AsmName.empty()) - AsmName = Reg.getName(); - - - if ((i % 14) == 0) - O << "\n "; - - O << StringTable.GetOrAddStringOffset(AsmName) << ", "; - } - O << "0\n" - << " };\n" + "const char *" << Target.getName() << ClassName << "::"; + if (hasAltNames) + O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; + else + O << "getRegisterName(unsigned RegNo) {\n"; + O << " assert(RegNo && RegNo < " << (Registers.size()+1) + << " && \"Invalid register number!\");\n" << "\n"; - O << " const char *AsmStrs =\n"; - StringTable.EmitString(O); - O << ";\n"; + if (hasAltNames) { + for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) + emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers); + } else + emitRegisterNameString(O, "", Registers); + + if (hasAltNames) { + O << " const unsigned *RegAsmOffset;\n" + << " const char *AsmStrs;\n" + << " switch(AltIdx) {\n" + << " default: assert(0 && \"Invalid register alt name index!\");\n"; + for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) { + StringRef Namespace = AltNameIndices[1]->getValueAsString("Namespace"); + StringRef AltName(AltNameIndices[i]->getName()); + O << " case " << Namespace << "::" << AltName + << ":\n" + << " AsmStrs = AsmStrs" << AltName << ";\n" + << " RegAsmOffset = RegAsmOffset" << AltName << ";\n" + << " break;\n"; + } + O << "}\n"; + } - O << " return AsmStrs+RegAsmOffset[RegNo-1];\n" + O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" + << " \"Invalid alt name index for register!\");\n" + << " return AsmStrs+RegAsmOffset[RegNo-1];\n" << "}\n"; } @@ -936,6 +997,9 @@ const Record *Rec = RO.getRecord(); StringRef ROName = RO.getName(); + + if (Rec->isSubClassOf("RegisterOperand")) + Rec = Rec->getValueAsDef("RegClass"); if (Rec->isSubClassOf("RegisterClass")) { Cond = std::string("MI->getOperand(")+llvm::utostr(i)+").isReg()"; IAP->addCond(Cond); Modified: llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp Mon Jun 27 16:06:21 2011 @@ -1242,6 +1242,16 @@ /// static EEVT::TypeSet getImplicitType(Record *R, unsigned ResNo, bool NotRegisters, TreePattern &TP) { + // Check to see if this is a register operand. + if (R->isSubClassOf("RegisterOperand")) { + assert(ResNo == 0 && "Regoperand ref only has one result!"); + if (NotRegisters) + return EEVT::TypeSet(); // Unknown. + Record *RegClass = R->getValueAsDef("RegClass"); + const CodeGenTarget &T = TP.getDAGPatterns().getTargetInfo(); + return EEVT::TypeSet(T.getRegisterClass(RegClass).getValueTypes()); + } + // Check to see if this is a register or a register class. if (R->isSubClassOf("RegisterClass")) { assert(ResNo == 0 && "Regclass ref only has one result!"); @@ -1524,6 +1534,11 @@ if (ResultNode->isSubClassOf("PointerLikeRegClass")) { MadeChange |= UpdateNodeType(ResNo, MVT::iPTR, TP); + } else if (ResultNode->isSubClassOf("RegisterOperand")) { + Record *RegClass = ResultNode->getValueAsDef("RegClass"); + const CodeGenRegisterClass &RC = + CDP.getTargetInfo().getRegisterClass(RegClass); + MadeChange |= UpdateNodeType(ResNo, RC.getValueTypes(), TP); } else if (ResultNode->getName() == "unknown") { // Nothing to do. } else { @@ -1582,6 +1597,11 @@ const CodeGenRegisterClass &RC = CDP.getTargetInfo().getRegisterClass(OperandNode); MadeChange |= Child->UpdateNodeType(ChildResNo, RC.getValueTypes(), TP); + } else if (OperandNode->isSubClassOf("RegisterOperand")) { + Record *RegClass = OperandNode->getValueAsDef("RegClass"); + const CodeGenRegisterClass &RC = + CDP.getTargetInfo().getRegisterClass(RegClass); + MadeChange |= Child->UpdateNodeType(ChildResNo, RC.getValueTypes(), TP); } else if (OperandNode->isSubClassOf("Operand")) { VT = getValueType(OperandNode->getValueAsDef("Type")); MadeChange |= Child->UpdateNodeType(ChildResNo, VT, TP); @@ -1928,7 +1948,8 @@ // def : Pat<(v1i64 (bitconvert(v2i32 DPR:$src))), (v1i64 DPR:$src)>; if (Nodes[i] == Trees[0] && Nodes[i]->isLeaf()) { DefInit *DI = dynamic_cast(Nodes[i]->getLeafValue()); - if (DI && DI->getDef()->isSubClassOf("RegisterClass")) + if (DI && (DI->getDef()->isSubClassOf("RegisterClass") || + DI->getDef()->isSubClassOf("RegisterOperand"))) continue; } @@ -2211,7 +2232,8 @@ if (Pat->getName().empty()) { if (Pat->isLeaf()) { DefInit *DI = dynamic_cast(Pat->getLeafValue()); - if (DI && DI->getDef()->isSubClassOf("RegisterClass")) + if (DI && (DI->getDef()->isSubClassOf("RegisterClass") || + DI->getDef()->isSubClassOf("RegisterOperand"))) I->error("Input " + DI->getDef()->getName() + " must be named!"); } return false; @@ -2318,6 +2340,7 @@ I->error("set destination should be a register!"); if (Val->getDef()->isSubClassOf("RegisterClass") || + Val->getDef()->isSubClassOf("RegisterOperand") || Val->getDef()->isSubClassOf("PointerLikeRegClass")) { if (Dest->getName().empty()) I->error("set destination must have a name!"); Modified: llvm/trunk/utils/TableGen/CodeGenInstruction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenInstruction.cpp?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenInstruction.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenInstruction.cpp Mon Jun 27 16:06:21 2011 @@ -69,7 +69,9 @@ std::string EncoderMethod; unsigned NumOps = 1; DagInit *MIOpInfo = 0; - if (Rec->isSubClassOf("Operand")) { + if (Rec->isSubClassOf("RegisterOperand")) { + PrintMethod = Rec->getValueAsString("PrintMethod"); + } else if (Rec->isSubClassOf("Operand")) { PrintMethod = Rec->getValueAsString("PrintMethod"); // If there is an explicit encoder method, use it. EncoderMethod = Rec->getValueAsString("EncoderMethod"); @@ -415,6 +417,9 @@ // Handle explicit registers. if (ADI && ADI->getDef()->isSubClassOf("Register")) { + if (InstOpRec->isSubClassOf("RegisterOperand")) + InstOpRec = InstOpRec->getValueAsDef("RegClass"); + if (!InstOpRec->isSubClassOf("RegisterClass")) return false; Modified: llvm/trunk/utils/TableGen/CodeGenTarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.cpp?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.cpp (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.cpp Mon Jun 27 16:06:21 2011 @@ -164,6 +164,11 @@ return *RegBank; } +void CodeGenTarget::ReadRegAltNameIndices() const { + RegAltNameIndices = Records.getAllDerivedDefinitions("RegAltNameIndex"); + std::sort(RegAltNameIndices.begin(), RegAltNameIndices.end(), LessRecord()); +} + /// getRegisterByName - If there is a register with the specific AsmName, /// return it. const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const { Modified: llvm/trunk/utils/TableGen/CodeGenTarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/CodeGenTarget.h?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/CodeGenTarget.h (original) +++ llvm/trunk/utils/TableGen/CodeGenTarget.h Mon Jun 27 16:06:21 2011 @@ -66,7 +66,9 @@ mutable DenseMap Instructions; mutable CodeGenRegBank *RegBank; + mutable std::vector RegAltNameIndices; mutable std::vector LegalValueTypes; + void ReadRegAltNameIndices() const; void ReadInstructions() const; void ReadLegalValueTypes() const; @@ -100,6 +102,11 @@ /// return it. const CodeGenRegister *getRegisterByName(StringRef Name) const; + const std::vector &getRegAltNameIndices() const { + if (RegAltNameIndices.empty()) ReadRegAltNameIndices(); + return RegAltNameIndices; + } + const std::vector &getRegisterClasses() const { return getRegBank().getRegClasses(); } Modified: llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp (original) +++ llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp Mon Jun 27 16:06:21 2011 @@ -224,6 +224,7 @@ Record *LeafRec = DI->getDef(); if (// Handle register references. Nothing to do here, they always match. LeafRec->isSubClassOf("RegisterClass") || + LeafRec->isSubClassOf("RegisterOperand") || LeafRec->isSubClassOf("PointerLikeRegClass") || LeafRec->isSubClassOf("SubRegIndex") || // Place holder for SRCVALUE nodes. Nothing to do here. @@ -579,15 +580,16 @@ // If this is an explicit register reference, handle it. if (DefInit *DI = dynamic_cast(N->getLeafValue())) { - if (DI->getDef()->isSubClassOf("Register")) { + Record *Def = DI->getDef(); + if (Def->isSubClassOf("Register")) { const CodeGenRegister *Reg = - CGP.getTargetInfo().getRegBank().getReg(DI->getDef()); + CGP.getTargetInfo().getRegBank().getReg(Def); AddMatcher(new EmitRegisterMatcher(Reg, N->getType(0))); ResultOps.push_back(NextRecordedOperandNo++); return; } - if (DI->getDef()->getName() == "zero_reg") { + if (Def->getName() == "zero_reg") { AddMatcher(new EmitRegisterMatcher(0, N->getType(0))); ResultOps.push_back(NextRecordedOperandNo++); return; @@ -595,16 +597,18 @@ // Handle a reference to a register class. This is used // in COPY_TO_SUBREG instructions. - if (DI->getDef()->isSubClassOf("RegisterClass")) { - std::string Value = getQualifiedName(DI->getDef()) + "RegClassID"; + if (Def->isSubClassOf("RegisterOperand")) + Def = Def->getValueAsDef("RegClass"); + if (Def->isSubClassOf("RegisterClass")) { + std::string Value = getQualifiedName(Def) + "RegClassID"; AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32)); ResultOps.push_back(NextRecordedOperandNo++); return; } // Handle a subregister index. This is used for INSERT_SUBREG etc. - if (DI->getDef()->isSubClassOf("SubRegIndex")) { - std::string Value = getQualifiedName(DI->getDef()); + if (Def->isSubClassOf("SubRegIndex")) { + std::string Value = getQualifiedName(Def); AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32)); ResultOps.push_back(NextRecordedOperandNo++); return; Modified: llvm/trunk/utils/TableGen/FastISelEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FastISelEmitter.cpp?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/FastISelEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/FastISelEmitter.cpp Mon Jun 27 16:06:21 2011 @@ -248,6 +248,8 @@ // For now, the only other thing we accept is register operands. const CodeGenRegisterClass *RC = 0; + if (OpLeafRec->isSubClassOf("RegisterOperand")) + OpLeafRec = OpLeafRec->getValueAsDef("RegClass"); if (OpLeafRec->isSubClassOf("RegisterClass")) RC = &Target.getRegisterClass(OpLeafRec); else if (OpLeafRec->isSubClassOf("Register")) @@ -454,6 +456,8 @@ std::string SubRegNo; if (Op->getName() != "EXTRACT_SUBREG") { Record *Op0Rec = II.Operands[0].Rec; + if (Op0Rec->isSubClassOf("RegisterOperand")) + Op0Rec = Op0Rec->getValueAsDef("RegClass"); if (!Op0Rec->isSubClassOf("RegisterClass")) continue; DstRC = &Target.getRegisterClass(Op0Rec); Modified: llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp Mon Jun 27 16:06:21 2011 @@ -1305,8 +1305,10 @@ RecordRecTy *Type = dynamic_cast(TI->getType()); Record *TypeRecord = Type->getRecord(); bool isReg = false; + if (TypeRecord->isSubClassOf("RegisterOperand")) + TypeRecord = TypeRecord->getValueAsDef("RegClass"); if (TypeRecord->isSubClassOf("RegisterClass")) { - Decoder = "Decode" + Type->getRecord()->getName() + "RegisterClass"; + Decoder = "Decode" + TypeRecord->getName() + "RegisterClass"; isReg = true; } Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Mon Jun 27 16:06:21 2011 @@ -43,10 +43,10 @@ std::vector DefList = Records.getAllDerivedDefinitions("InstrItinClass"); std::sort(DefList.begin(), DefList.end(), LessRecord()); - + for (unsigned i = 0, N = DefList.size(); i < N; i++) ItinClassMap[DefList[i]->getName()] = i; -} +} unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) { return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()]; @@ -59,7 +59,7 @@ std::vector InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { std::vector Result; - + for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) { // Handle aggregate operands and normal operands the same way by expanding // either case into a list of operands for this op. @@ -70,7 +70,7 @@ // operand, which has a single operand, but no declared class for the // operand. DagInit *MIOI = Inst.Operands[i].MIOperandInfo; - + if (!MIOI || MIOI->getNumArgs() == 0) { // Single, anonymous, operand. OperandList.push_back(Inst.Operands[i]); @@ -86,7 +86,9 @@ for (unsigned j = 0, e = OperandList.size(); j != e; ++j) { Record *OpR = OperandList[j].Rec; std::string Res; - + + if (OpR->isSubClassOf("RegisterOperand")) + OpR = OpR->getValueAsDef("RegClass"); if (OpR->isSubClassOf("RegisterClass")) Res += getQualifiedName(OpR) + "RegClassID, "; else if (OpR->isSubClassOf("PointerLikeRegClass")) @@ -94,10 +96,10 @@ else // -1 means the operand does not have a fixed register class. Res += "-1, "; - + // Fill in applicable flags. Res += "0"; - + // Ptr value whose register class is resolved via callback. if (OpR->isSubClassOf("PointerLikeRegClass")) Res += "|(1<isSubClassOf("PredicateOperand")) Res += "|(1<isSubClassOf("OptionalDefOperand")) @@ -114,7 +116,7 @@ // Fill in constraint info. Res += ", "; - + const CGIOperandList::ConstraintInfo &Constraint = Inst.Operands[i].Constraints[j]; if (Constraint.isNone()) @@ -126,7 +128,7 @@ Res += "((" + utostr(Constraint.getTiedOperand()) + " << 16) | (1 << TOI::TIED_TO))"; } - + Result.push_back(Res); } } @@ -134,12 +136,12 @@ return Result; } -void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, +void InstrInfoEmitter::EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs) { // ID #0 is for no operand info. unsigned OperandListNum = 0; OperandInfoIDs[std::vector()] = ++OperandListNum; - + OS << "\n"; const CodeGenTarget &Target = CDP.getTargetInfo(); for (CodeGenTarget::inst_iterator II = Target.inst_begin(), @@ -147,7 +149,7 @@ std::vector OperandInfo = GetOperandInfo(**II); unsigned &N = OperandInfoIDs[OperandInfo]; if (N != 0) continue; - + N = ++OperandListNum; OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { "; for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) @@ -205,7 +207,7 @@ std::map, unsigned> EmittedBarriers; unsigned BarrierNumber = 0; std::map BarriersMap; - + // Emit all of the instruction's implicit uses and defs. for (CodeGenTarget::inst_iterator II = Target.inst_begin(), E = Target.inst_end(); II != E; ++II) { @@ -231,10 +233,10 @@ } OperandInfoMapTy OperandInfoIDs; - + // Emit all of the operand info records. EmitOperandInfo(OS, OperandInfoIDs); - + // Emit all of the TargetInstrDesc records in their ENUM ordering. // OS << "\nstatic const TargetInstrDesc " << TargetName Modified: llvm/trunk/utils/TableGen/Record.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.cpp?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.cpp (original) +++ llvm/trunk/utils/TableGen/Record.cpp Mon Jun 27 16:06:21 2011 @@ -1443,6 +1443,25 @@ return Ints; } +/// getValueAsListOfStrings - This method looks up the specified field and +/// returns its value as a vector of strings, throwing an exception if the +/// field does not exist or if the value is not the right type. +/// +std::vector +Record::getValueAsListOfStrings(StringRef FieldName) const { + ListInit *List = getValueAsListInit(FieldName); + std::vector Strings; + for (unsigned i = 0; i < List->getSize(); i++) { + if (StringInit *II = dynamic_cast(List->getElement(i))) { + Strings.push_back(II->getValue()); + } else { + throw "Record `" + getName() + "', field `" + FieldName.str() + + "' does not have a list of strings initializer!"; + } + } + return Strings; +} + /// getValueAsDef - This method looks up the specified field and returns its /// value as a Record, throwing an exception if the field does not exist or if /// the value is not the right type. Modified: llvm/trunk/utils/TableGen/Record.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/Record.h?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/Record.h (original) +++ llvm/trunk/utils/TableGen/Record.h Mon Jun 27 16:06:21 2011 @@ -1368,6 +1368,12 @@ /// std::vector getValueAsListOfInts(StringRef FieldName) const; + /// getValueAsListOfStrings - This method looks up the specified field and + /// returns its value as a vector of strings, throwing an exception if the + /// field does not exist or if the value is not the right type. + /// + std::vector getValueAsListOfStrings(StringRef FieldName) const; + /// getValueAsDef - This method looks up the specified field and returns its /// value as a Record, throwing an exception if the field does not exist or if /// the value is not the right type. Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=133940&r1=133939&r2=133940&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Mon Jun 27 16:06:21 2011 @@ -112,6 +112,18 @@ OS << "0 };\n"; } + const std::vector RegAltNameIndices = Target.getRegAltNameIndices(); + // If the only definition is the default NoRegAltName, we don't need to + // emit anything. + if (RegAltNameIndices.size() > 1) { + OS << "\n// Register alternate name indices\n"; + OS << "enum {\n"; + for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) + OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; + OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; + OS << "};\n"; + } + // Emit the empty sub-registers list OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; // Loop over all of the registers which have sub-registers, emitting the From evan.cheng at apple.com Mon Jun 27 16:26:13 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 27 Jun 2011 21:26:13 -0000 Subject: [llvm-commits] [llvm] r133944 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/Blackfin/ lib/Target/X86/ Message-ID: <20110627212613.E74242A6C12C@llvm.org> Author: evancheng Date: Mon Jun 27 16:26:13 2011 New Revision: 133944 URL: http://llvm.org/viewvc/llvm-project?rev=133944&view=rev Log: More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo. Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp llvm/trunk/lib/CodeGen/MachineLICM.cpp llvm/trunk/lib/CodeGen/MachineVerifier.cpp llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/lib/CodeGen/StackSlotColoring.cpp llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp llvm/trunk/lib/Target/TargetInstrInfo.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Mon Jun 27 16:26:13 2011 @@ -52,9 +52,6 @@ /// if the operand is a register. If isLookupPtrRegClass is set, then this is /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to /// get a dynamic register class. - /// - /// NOTE: This member should be considered to be private, all access should go - /// through "getRegClass(TRI)" below. short RegClass; /// Flags - These are flags from the TOI::OperandFlags enum. @@ -65,12 +62,6 @@ unsigned Constraints; /// Currently no other information. - /// getRegClass - Get the register class for the operand, handling resolution - /// of "symbolic" pointer register classes etc. If this is not a register - /// operand, this returns null. - const TargetRegisterClass *getRegClass(const TargetRegisterInfo *TRI) const; - - /// isLookupPtrRegClass - Set if this operand is a pointer value and it /// requires a callback to look up its register class. bool isLookupPtrRegClass() const { return Flags&(1 <getDesc().getNumOperands()) - RC = MI->getDesc().OpInfo[i].getRegClass(TRI); + RC = TII->getRegClass(MI->getDesc(), i, TRI); AggressiveAntiDepState::RegisterReference RR = { &MO, RC }; RegRefs.insert(std::make_pair(Reg, RR)); } @@ -479,7 +479,7 @@ // Note register reference... const TargetRegisterClass *RC = NULL; if (i < MI->getDesc().getNumOperands()) - RC = MI->getDesc().OpInfo[i].getRegClass(TRI); + RC = TII->getRegClass(MI->getDesc(), i, TRI); AggressiveAntiDepState::RegisterReference RR = { &MO, RC }; RegRefs.insert(std::make_pair(Reg, RR)); } Modified: llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp (original) +++ llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp Mon Jun 27 16:26:13 2011 @@ -188,6 +188,7 @@ void VirtRegAuxInfo::CalculateRegClass(unsigned reg) { MachineRegisterInfo &MRI = MF.getRegInfo(); + const TargetInstrInfo *TII = MF.getTarget().getInstrInfo(); const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); const TargetRegisterClass *OldRC = MRI.getRegClass(reg); const TargetRegisterClass *NewRC = TRI->getLargestLegalSuperClass(OldRC); @@ -203,7 +204,7 @@ if (I.getOperand().getSubReg()) return; const TargetRegisterClass *OpRC = - I->getDesc().getRegClass(I.getOperandNo(), TRI); + TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI); if (OpRC) NewRC = getCommonSubClass(NewRC, OpRC); if (!NewRC || NewRC == OldRC) Modified: llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp (original) +++ llvm/trunk/lib/CodeGen/CriticalAntiDepBreaker.cpp Mon Jun 27 16:26:13 2011 @@ -207,7 +207,7 @@ const TargetRegisterClass *NewRC = 0; if (i < MI->getDesc().getNumOperands()) - NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI); + NewRC = TII->getRegClass(MI->getDesc(), i, TRI); // For now, only allow the register to be changed if its register // class is consistent across all uses. @@ -295,7 +295,7 @@ const TargetRegisterClass *NewRC = 0; if (i < MI->getDesc().getNumOperands()) - NewRC = MI->getDesc().OpInfo[i].getRegClass(TRI); + NewRC = TII->getRegClass(MI->getDesc(), i, TRI); // For now, only allow the register to be changed if its register // class is consistent across all uses. Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Mon Jun 27 16:26:13 2011 @@ -1020,7 +1020,7 @@ if (NewOpc == 0) return 0; const TargetInstrDesc &TID = TII->get(NewOpc); if (TID.getNumDefs() != 1) return 0; - const TargetRegisterClass *RC = TID.OpInfo[LoadRegIndex].getRegClass(TRI); + const TargetRegisterClass *RC = TII->getRegClass(TID, LoadRegIndex, TRI); // Ok, we're unfolding. Create a temporary register and do the unfold. unsigned Reg = MRI->createVirtualRegister(RC); Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Mon Jun 27 16:26:13 2011 @@ -62,6 +62,7 @@ raw_ostream *OS; const MachineFunction *MF; const TargetMachine *TM; + const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; const MachineRegisterInfo *MRI; @@ -255,6 +256,7 @@ this->MF = &MF; TM = &MF.getTarget(); + TII = TM->getInstrInfo(); TRI = TM->getRegisterInfo(); MRI = &MF.getRegInfo(); @@ -387,8 +389,6 @@ void MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { - const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); - // Count the number of landing pad successors. SmallPtrSet LandingPadSuccs; for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(), @@ -723,7 +723,7 @@ } sr = s; } - if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) { + if (const TargetRegisterClass *DRC = TII->getRegClass(TI, MONum, TRI)) { if (!DRC->contains(sr)) { report("Illegal physical register for instruction", MO, MONum); *OS << TRI->getName(sr) << " is not a " @@ -743,7 +743,7 @@ } RC = SRC; } - if (const TargetRegisterClass *DRC = TOI.getRegClass(TRI)) { + if (const TargetRegisterClass *DRC = TII->getRegClass(TI, MONum, TRI)) { if (!RC->hasSuperClassEq(DRC)) { report("Illegal virtual register for instruction", MO, MONum); *OS << "Expected a " << DRC->getName() << " register, but got a " Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Mon Jun 27 16:26:13 2011 @@ -701,7 +701,7 @@ // Make sure the copy destination register class fits the instruction // definition register class. The mismatch can happen as a result of earlier // extract_subreg, insert_subreg, subreg_to_reg coalescing. - const TargetRegisterClass *RC = TID.OpInfo[0].getRegClass(tri_); + const TargetRegisterClass *RC = tii_->getRegClass(TID, 0, tri_); if (TargetRegisterInfo::isVirtualRegister(DstReg)) { if (mri_->getRegClass(DstReg) != RC) return false; @@ -718,7 +718,7 @@ const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg); const TargetRegisterClass *DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx); - const TargetRegisterClass *DefRC = TID.OpInfo[0].getRegClass(tri_); + const TargetRegisterClass *DefRC = tii_->getRegClass(TID, 0, tri_); if (DefRC == DstRC) DstSubIdx = 0; else if (DefRC != DstSubRC) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Mon Jun 27 16:26:13 2011 @@ -109,7 +109,7 @@ const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); const TargetRegisterClass *RC = 0; if (i+II.getNumDefs() < II.getNumOperands()) - RC = II.OpInfo[i+II.getNumDefs()].getRegClass(TRI); + RC = TII->getRegClass(II, i+II.getNumDefs(), TRI); if (!UseRC) UseRC = RC; else if (RC) { @@ -189,7 +189,7 @@ // is a vreg in the same register class, use the CopyToReg'd destination // register instead of creating a new vreg. unsigned VRBase = 0; - const TargetRegisterClass *RC = II.OpInfo[i].getRegClass(TRI); + const TargetRegisterClass *RC = TII->getRegClass(II, i, TRI); if (II.OpInfo[i].isOptionalDef()) { // Optional def must be a physical register. unsigned NumResults = CountResults(Node); @@ -285,7 +285,7 @@ const TargetRegisterClass *SrcRC = MRI->getRegClass(VReg); const TargetRegisterClass *DstRC = 0; if (IIOpNum < II->getNumOperands()) - DstRC = II->OpInfo[IIOpNum].getRegClass(TRI); + DstRC = TII->getRegClass(*II, IIOpNum, TRI); assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && "Don't have operand info for this instruction!"); if (DstRC && !SrcRC->hasSuperClassEq(DstRC)) { Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Mon Jun 27 16:26:13 2011 @@ -303,7 +303,7 @@ unsigned Idx = RegDefPos.GetIdx(); const TargetInstrDesc Desc = TII->get(Opcode); - const TargetRegisterClass *RC = Desc.getRegClass(Idx, TRI); + const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI); RegClass = RC->getID(); // FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a // better way to determine it. Modified: llvm/trunk/lib/CodeGen/StackSlotColoring.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackSlotColoring.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/StackSlotColoring.cpp (original) +++ llvm/trunk/lib/CodeGen/StackSlotColoring.cpp Mon Jun 27 16:26:13 2011 @@ -521,7 +521,7 @@ if (MO.getSubReg() || MII->isSubregToReg()) return false; - const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI); + const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI); if (RC && !RC->contains(NewReg)) return false; @@ -583,7 +583,7 @@ if (MO.getSubReg()) return false; - const TargetRegisterClass *RC = TID.OpInfo[i].getRegClass(TRI); + const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI); if (RC && !RC->contains(NewReg)) return false; if (MO.isKill()) Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Mon Jun 27 16:26:13 2011 @@ -943,7 +943,7 @@ // Unfold the load. DEBUG(dbgs() << "2addr: UNFOLDING: " << *mi); const TargetRegisterClass *RC = - UnfoldTID.OpInfo[LoadRegIndex].getRegClass(TRI); + TII->getRegClass(UnfoldTID, LoadRegIndex, TRI); unsigned Reg = MRI->createVirtualRegister(RC); SmallVector NewMIs; if (!TII->unfoldMemoryOperand(MF, mi, Reg, Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Mon Jun 27 16:26:13 2011 @@ -1112,7 +1112,7 @@ const TargetInstrDesc &TID = TII.get(ADDriOpc); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); - MRI.constrainRegClass(BaseReg, TID.OpInfo[0].getRegClass(this)); + MRI.constrainRegClass(BaseReg, TII.getRegClass(TID, 0, this)); MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, TID, BaseReg) .addFrameIndex(FrameIdx).addImm(Offset); Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Mon Jun 27 16:26:13 2011 @@ -1673,7 +1673,7 @@ Ops.pop_back(); const TargetInstrDesc &TID = TII->get(NewOpc); - const TargetRegisterClass *TRC = TID.OpInfo[0].getRegClass(TRI); + const TargetRegisterClass *TRC = TII->getRegClass(TID, 0, TRI); MRI->constrainRegClass(EvenReg, TRC); MRI->constrainRegClass(OddReg, TRC); Modified: llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp Mon Jun 27 16:26:13 2011 @@ -220,7 +220,7 @@ const TargetInstrDesc &TID1 = TII->get(MulOpc); const TargetInstrDesc &TID2 = TII->get(AddSubOpc); - unsigned TmpReg = MRI->createVirtualRegister(TID1.getRegClass(0, TRI)); + unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(TID1, 0, TRI)); MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), TID1, TmpReg) .addReg(Src1Reg, getKillRegState(Src1Kill)) Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp Mon Jun 27 16:26:13 2011 @@ -154,13 +154,13 @@ if (UI.getUse().getResNo() >= DefTID.getNumDefs()) continue; const TargetRegisterClass *DefRC = - DefTID.OpInfo[UI.getUse().getResNo()].getRegClass(TRI); + TII.getRegClass(DefTID, UI.getUse().getResNo(), TRI); const TargetInstrDesc &UseTID = TII.get(UI->getMachineOpcode()); if (UseTID.getNumDefs()+UI.getOperandNo() >= UseTID.getNumOperands()) continue; const TargetRegisterClass *UseRC = - UseTID.OpInfo[UseTID.getNumDefs()+UI.getOperandNo()].getRegClass(TRI); + TII.getRegClass(UseTID, UseTID.getNumDefs()+UI.getOperandNo(), TRI); if (!DefRC || !UseRC) continue; // We cannot copy CC <-> !(CC/D) Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Mon Jun 27 16:26:13 2011 @@ -21,24 +21,6 @@ using namespace llvm; //===----------------------------------------------------------------------===// -// TargetOperandInfo -//===----------------------------------------------------------------------===// - -/// getRegClass - Get the register class for the operand, handling resolution -/// of "symbolic" pointer register classes etc. If this is not a register -/// operand, this returns null. -const TargetRegisterClass * -TargetOperandInfo::getRegClass(const TargetRegisterInfo *TRI) const { - if (isLookupPtrRegClass()) - return TRI->getPointerRegClass(RegClass); - // Instructions like INSERT_SUBREG do not have fixed register classes. - if (RegClass < 0) - return 0; - // Otherwise just look it up normally. - return TRI->getRegClass(RegClass); -} - -//===----------------------------------------------------------------------===// // TargetInstrInfo //===----------------------------------------------------------------------===// @@ -50,6 +32,24 @@ TargetInstrInfo::~TargetInstrInfo() { } +const TargetRegisterClass* +TargetInstrInfo::getRegClass(const TargetInstrDesc &TID, unsigned OpNum, + const TargetRegisterInfo *TRI) const { + if (OpNum >= TID.getNumOperands()) + return 0; + + short RegClass = TID.OpInfo[OpNum].RegClass; + if (TID.OpInfo[OpNum].isLookupPtrRegClass()) + return TRI->getPointerRegClass(RegClass); + + // Instructions like INSERT_SUBREG do not have fixed register classes. + if (RegClass < 0) + return 0; + + // Otherwise just look it up normally. + return TRI->getRegClass(RegClass); +} + unsigned TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData, const MachineInstr *MI) const { Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=133944&r1=133943&r2=133944&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Jun 27 16:26:13 2011 @@ -2274,7 +2274,7 @@ return NULL; bool NarrowToMOV32rm = false; if (Size) { - unsigned RCSize = MI->getDesc().OpInfo[i].getRegClass(&RI)->getSize(); + unsigned RCSize = getRegClass(MI->getDesc(), i, &RI)->getSize(); if (Size < RCSize) { // Check if it's safe to fold the load. If the size of the object is // narrower than the load width, then it's not. @@ -2590,8 +2590,7 @@ UnfoldStore &= FoldedStore; const TargetInstrDesc &TID = get(Opc); - const TargetOperandInfo &TOI = TID.OpInfo[Index]; - const TargetRegisterClass *RC = TOI.getRegClass(&RI); + const TargetRegisterClass *RC = getRegClass(TID, Index, &RI); if (!MI->hasOneMemOperand() && RC == &X86::VR128RegClass && !TM.getSubtarget().isUnalignedMemAccessFast()) @@ -2686,7 +2685,7 @@ // Emit the store instruction. if (UnfoldStore) { - const TargetRegisterClass *DstRC = TID.OpInfo[0].getRegClass(&RI); + const TargetRegisterClass *DstRC = getRegClass(TID, 0, &RI); std::pair MMOs = MF.extractStoreMemRefs(MI->memoperands_begin(), @@ -2712,7 +2711,7 @@ bool FoldedLoad = I->second.second & (1 << 4); bool FoldedStore = I->second.second & (1 << 5); const TargetInstrDesc &TID = get(Opc); - const TargetRegisterClass *RC = TID.OpInfo[Index].getRegClass(&RI); + const TargetRegisterClass *RC = getRegClass(TID, Index, &RI); unsigned NumDefs = TID.NumDefs; std::vector AddrOps; std::vector BeforeOps; @@ -2758,7 +2757,7 @@ std::vector VTs; const TargetRegisterClass *DstRC = 0; if (TID.getNumDefs() > 0) { - DstRC = TID.OpInfo[0].getRegClass(&RI); + DstRC = getRegClass(TID, 0, &RI); VTs.push_back(*DstRC->vt_begin()); } for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { From grosbach at apple.com Mon Jun 27 16:38:03 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 27 Jun 2011 21:38:03 -0000 Subject: [llvm-commits] [llvm] r133945 - /llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Message-ID: <20110627213803.3C2C92A6C12C@llvm.org> Author: grosbach Date: Mon Jun 27 16:38:03 2011 New Revision: 133945 URL: http://llvm.org/viewvc/llvm-project?rev=133945&view=rev Log: ARM Asm parsing of Thumb2 move immediate. Thumb2 MOV mnemonic can accept both cc_out and predication. We don't (yet) encode the instruction properly, but this gets the parsing part. Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=133945&r1=133944&r2=133945&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jun 27 16:38:03 2011 @@ -1826,6 +1826,7 @@ void ARMAsmParser:: GetMnemonicAcceptInfo(StringRef Mnemonic, bool &CanAcceptCarrySet, bool &CanAcceptPredicationCode) { + bool isThumbOne = TM.getSubtarget().isThumb1Only(); bool isThumb = TM.getSubtarget().isThumb(); if (Mnemonic == "and" || Mnemonic == "lsl" || Mnemonic == "lsr" || @@ -1836,7 +1837,7 @@ Mnemonic == "rsb" || Mnemonic == "rsc" || Mnemonic == "orn" || Mnemonic == "sbc" || Mnemonic == "mla" || Mnemonic == "umull" || Mnemonic == "eor" || Mnemonic == "smlal" || - (Mnemonic == "mov" && !isThumb)) { + (Mnemonic == "mov" && !isThumbOne)) { CanAcceptCarrySet = true; } else { CanAcceptCarrySet = false; @@ -1856,7 +1857,7 @@ if (isThumb) if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" || Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp" || - Mnemonic == "mov") + (Mnemonic == "mov" && isThumbOne)) CanAcceptPredicationCode = false; } From jstaszak at apple.com Mon Jun 27 16:51:12 2011 From: jstaszak at apple.com (Jakub Staszak) Date: Mon, 27 Jun 2011 21:51:12 -0000 Subject: [llvm-commits] [llvm] r133946 - /llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Message-ID: <20110627215112.D41C52A6C12C@llvm.org> Author: kuba Date: Mon Jun 27 16:51:12 2011 New Revision: 133946 URL: http://llvm.org/viewvc/llvm-project?rev=133946&view=rev Log: Calculate GetBestDestForJumpOnUndef correctly. Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Modified: llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp?rev=133946&r1=133945&r2=133946&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/JumpThreading.cpp Mon Jun 27 16:51:12 2011 @@ -600,8 +600,10 @@ for (unsigned i = 1, e = BBTerm->getNumSuccessors(); i != e; ++i) { TestBB = BBTerm->getSuccessor(i); unsigned NumPreds = std::distance(pred_begin(TestBB), pred_end(TestBB)); - if (NumPreds < MinNumPreds) + if (NumPreds < MinNumPreds) { MinSucc = i; + MinNumPreds = NumPreds; + } } return MinSucc; From echristo at apple.com Mon Jun 27 17:30:14 2011 From: echristo at apple.com (Eric Christopher) Date: Mon, 27 Jun 2011 22:30:14 -0000 Subject: [llvm-commits] [llvm] r133952 - /llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c Message-ID: <20110627223014.B839E2A6C12C@llvm.org> Author: echristo Date: Mon Jun 27 17:30:14 2011 New Revision: 133952 URL: http://llvm.org/viewvc/llvm-project?rev=133952&view=rev Log: Fix this test to actually check something and be able to be compiled. Modified: llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c Modified: llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c?rev=133952&r1=133951&r2=133952&view=diff ============================================================================== --- llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c (original) +++ llvm/trunk/test/FrontendC/ARM/inline-asm-multichar.c Mon Jun 27 17:30:14 2011 @@ -1,11 +1,11 @@ -// RUN: %llvmgcc -S -march=armv7a %s +// RUN: %llvmgcc -S -march=armv7a %s | FileCheck %s // XFAIL: * // XTARGET: arm int t1() { static float k = 1.0f; -CHECK: call void asm sideeffect "flds s15, $0 \0A", "*^Uv,~{s15}" + // CHECK: "flds s15, $0 \0A", "*^Uv,~{s15}" __asm__ volatile ("flds s15, %[k] \n" :: [k] "Uv,m" (k) : "s15"); return 0; } From dpatel at apple.com Mon Jun 27 17:32:04 2011 From: dpatel at apple.com (Devang Patel) Date: Mon, 27 Jun 2011 22:32:04 -0000 Subject: [llvm-commits] [llvm] r133953 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp test/CodeGen/X86/dbg-materialized-reg-loc.ll Message-ID: <20110627223204.E98672A6C12C@llvm.org> Author: dpatel Date: Mon Jun 27 17:32:04 2011 New Revision: 133953 URL: http://llvm.org/viewvc/llvm-project?rev=133953&view=rev Log: During bottom up fast-isel, instructions emitted to materalize registers are at top of basic block and do not have debug location. This may misguide debugger while entering the basic block and sometimes debugger provides semi useful view of current location to developer by picking up previous known location as current location. Assign a sensible location to the first instruction in a basic block, if it does not have one location derived from source file, so that debugger can provide meaningful user experience to developers in edge cases. Added: llvm/trunk/test/CodeGen/X86/dbg-materialized-reg-loc.ll Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=133953&r1=133952&r2=133953&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Mon Jun 27 17:32:04 2011 @@ -118,6 +118,10 @@ DebugLoc DL; }; + /// recomputeDebugLocForMaterializedRegs - Recompute debug location for + /// very first instruction in a basic block. + void recomputeDebugLocForMaterializedRegs(); + /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions /// into the local value area and return the old insert position. SavePoint enterLocalValueArea(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=133953&r1=133952&r2=133953&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Mon Jun 27 17:32:04 2011 @@ -292,6 +292,28 @@ ++FuncInfo.InsertPt; } +/// recomputeDebugLocForMaterializedRegs - Recompute debug location for +/// very first instruction in a basic block. All instructions emitted +/// to materialize registers do not have location information, see +/// enterLocalValueArea(), becase they may not be emited at the right +/// location. +void FastISel::recomputeDebugLocForMaterializedRegs() { + if (!getLastLocalValue()) + return; + MachineInstr *First = FuncInfo.MBB->getFirstNonPHI(); + if (!First->getDebugLoc().isUnknown()) + return; + + for (MachineBasicBlock::iterator I = FuncInfo.MBB->begin(), + E = FuncInfo.MBB->end(); I != E; ++I) { + DebugLoc DL = I->getDebugLoc(); + if (!DL.isUnknown()) { + First->setDebugLoc(DL); + return; + } + } +} + FastISel::SavePoint FastISel::enterLocalValueArea() { MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; DebugLoc OldDL = DL; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=133953&r1=133952&r2=133953&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Mon Jun 27 17:32:04 2011 @@ -964,6 +964,8 @@ else ++NumFastIselBlocks; + if (FastIS) + FastIS->recomputeDebugLocForMaterializedRegs(); if (Begin != BI) { // Run SelectionDAG instruction selection on the remainder of the block // not handled by FastISel. If FastISel is not run, this is the entire Added: llvm/trunk/test/CodeGen/X86/dbg-materialized-reg-loc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-materialized-reg-loc.ll?rev=133953&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-materialized-reg-loc.ll (added) +++ llvm/trunk/test/CodeGen/X86/dbg-materialized-reg-loc.ll Mon Jun 27 17:32:04 2011 @@ -0,0 +1,120 @@ +; RUN: llc -O0 < %s | FileCheck %s +; Radar 9223880 +; CHECK: .loc 1 17 64 +; CHECK: movl $0, %esi + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" +target triple = "x86_64-apple-macosx10.7.0" + +%class.LanguageRuntime = type opaque +%class.Process = type { i8 } + +define zeroext i1 @_Z15SetDynamicValuev() uwtable ssp { +entry: + %retval = alloca i1, align 1 + %process = alloca %class.Process*, align 8 + %cpp_runtime = alloca %class.LanguageRuntime*, align 8 + %objc_runtime = alloca %class.LanguageRuntime*, align 8 + %call = call zeroext i1 @_Z24IsPointerOrReferenceTypev(), !dbg !15 + br i1 %call, label %if.end, label %if.then, !dbg !15 + +if.then: ; preds = %entry + store i1 false, i1* %retval, !dbg !17 + br label %return, !dbg !17 + +if.end: ; preds = %entry + call void @llvm.dbg.declare(metadata !{%class.Process** %process}, metadata !18), !dbg !20 + %call1 = call %class.Process* @_Z10GetProcessv(), !dbg !21 + store %class.Process* %call1, %class.Process** %process, align 8, !dbg !21 + %tmp = load %class.Process** %process, align 8, !dbg !22 + %tobool = icmp ne %class.Process* %tmp, null, !dbg !22 + br i1 %tobool, label %if.end3, label %if.then2, !dbg !22 + +if.then2: ; preds = %if.end + store i1 false, i1* %retval, !dbg !23 + br label %return, !dbg !23 + +if.end3: ; preds = %if.end + call void @llvm.dbg.declare(metadata !{%class.LanguageRuntime** %cpp_runtime}, metadata !24), !dbg !25 + %tmp5 = load %class.Process** %process, align 8, !dbg !26 + %call6 = call %class.LanguageRuntime* @_ZN7Process18GetLanguageRuntimeEi(%class.Process* %tmp5, i32 0), !dbg !26 + store %class.LanguageRuntime* %call6, %class.LanguageRuntime** %cpp_runtime, align 8, !dbg !26 + %tmp7 = load %class.LanguageRuntime** %cpp_runtime, align 8, !dbg !27 + %tobool8 = icmp ne %class.LanguageRuntime* %tmp7, null, !dbg !27 + br i1 %tobool8, label %if.then9, label %if.end10, !dbg !27 + +if.then9: ; preds = %if.end3 + store i1 true, i1* %retval, !dbg !28 + br label %return, !dbg !28 + +if.end10: ; preds = %if.end3 + call void @llvm.dbg.declare(metadata !{%class.LanguageRuntime** %objc_runtime}, metadata !30), !dbg !31 + %tmp12 = load %class.Process** %process, align 8, !dbg !32 + %call13 = call %class.LanguageRuntime* @_ZN7Process18GetLanguageRuntimeEi(%class.Process* %tmp12, i32 1), !dbg !32 + store %class.LanguageRuntime* %call13, %class.LanguageRuntime** %objc_runtime, align 8, !dbg !32 + %tmp14 = load %class.LanguageRuntime** %objc_runtime, align 8, !dbg !33 + %tobool15 = icmp ne %class.LanguageRuntime* %tmp14, null, !dbg !33 + br i1 %tobool15, label %if.then16, label %if.end17, !dbg !33 + +if.then16: ; preds = %if.end10 + store i1 true, i1* %retval, !dbg !34 + br label %return, !dbg !34 + +if.end17: ; preds = %if.end10 + store i1 false, i1* %retval, !dbg !36 + br label %return, !dbg !36 + +return: ; preds = %if.end17, %if.then16, %if.then9, %if.then2, %if.then + %0 = load i1* %retval, !dbg !37 + ret i1 %0, !dbg !37 +} + +declare zeroext i1 @_Z24IsPointerOrReferenceTypev() + +declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone + +declare %class.Process* @_Z10GetProcessv() + +declare %class.LanguageRuntime* @_ZN7Process18GetLanguageRuntimeEi(%class.Process*, i32) + +!llvm.dbg.cu = !{!0} +!llvm.dbg.sp = !{!1, !6} + +!0 = metadata !{i32 589841, i32 0, i32 4, metadata !"my_vo.cpp", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 133629)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] +!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"SetDynamicValue", metadata !"SetDynamicValue", metadata !"_Z15SetDynamicValuev", metadata !2, i32 9, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i1 ()* @_Z15SetDynamicValuev, null, null} ; [ DW_TAG_subprogram ] +!2 = metadata !{i32 589865, metadata !"my_vo.cpp", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] +!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!4 = metadata !{metadata !5} +!5 = metadata !{i32 589860, metadata !0, metadata !"bool", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] +!6 = metadata !{i32 589870, i32 0, metadata !7, metadata !"GetLanguageRuntime", metadata !"GetLanguageRuntime", metadata !"_ZN7Process18GetLanguageRuntimeEi", metadata !2, i32 4, metadata !9, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null} ; [ DW_TAG_subprogram ] +!7 = metadata !{i32 589826, metadata !0, metadata !"Process", metadata !2, i32 2, i64 8, i64 8, i32 0, i32 0, null, metadata !8, i32 0, null, null} ; [ DW_TAG_class_type ] +!8 = metadata !{metadata !6} +!9 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !10, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] +!10 = metadata !{metadata !11, metadata !13, metadata !14} +!11 = metadata !{i32 589839, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ] +!12 = metadata !{i32 589843, metadata !0, metadata !"LanguageRuntime", metadata !2, i32 1, i64 0, i64 0, i32 0, i32 4, i32 0, null, i32 0, i32 0} ; [ DW_TAG_structure_type ] +!13 = metadata !{i32 589839, metadata !0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !7} ; [ DW_TAG_pointer_type ] +!14 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] +!15 = metadata !{i32 10, i32 3, metadata !16, null} +!16 = metadata !{i32 589835, metadata !1, i32 9, i32 24, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] +!17 = metadata !{i32 11, i32 5, metadata !16, null} +!18 = metadata !{i32 590080, metadata !16, metadata !"process", metadata !2, i32 13, metadata !19, i32 0} ; [ DW_TAG_auto_variable ] +!19 = metadata !{i32 589839, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ] +!20 = metadata !{i32 13, i32 12, metadata !16, null} +!21 = metadata !{i32 13, i32 34, metadata !16, null} +!22 = metadata !{i32 14, i32 3, metadata !16, null} +!23 = metadata !{i32 15, i32 5, metadata !16, null} +!24 = metadata !{i32 590080, metadata !16, metadata !"cpp_runtime", metadata !2, i32 17, metadata !11, i32 0} ; [ DW_TAG_auto_variable ] +!25 = metadata !{i32 17, i32 20, metadata !16, null} +!26 = metadata !{i32 17, i32 64, metadata !16, null} +!27 = metadata !{i32 18, i32 3, metadata !16, null} +!28 = metadata !{i32 19, i32 5, metadata !29, null} +!29 = metadata !{i32 589835, metadata !16, i32 18, i32 20, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] +!30 = metadata !{i32 590080, metadata !16, metadata !"objc_runtime", metadata !2, i32 22, metadata !11, i32 0} ; [ DW_TAG_auto_variable ] +!31 = metadata !{i32 22, i32 20, metadata !16, null} +!32 = metadata !{i32 22, i32 65, metadata !16, null} +!33 = metadata !{i32 23, i32 3, metadata !16, null} +!34 = metadata !{i32 24, i32 5, metadata !35, null} +!35 = metadata !{i32 589835, metadata !16, i32 23, i32 21, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] +!36 = metadata !{i32 26, i32 3, metadata !16, null} +!37 = metadata !{i32 27, i32 1, metadata !16, null} From mcrosier at apple.com Mon Jun 27 17:54:29 2011 From: mcrosier at apple.com (Chad Rosier) Date: Mon, 27 Jun 2011 22:54:29 -0000 Subject: [llvm-commits] [llvm] r133955 - /llvm/trunk/tools/lto/LTOModule.cpp Message-ID: <20110627225429.CBE652A6C12C@llvm.org> Author: mcrosier Date: Mon Jun 27 17:54:29 2011 New Revision: 133955 URL: http://llvm.org/viewvc/llvm-project?rev=133955&view=rev Log: Revert r133516 "Remove some unnecessary uses of c_str()." This was causing compile-time failures for some of the Objc and Obj-C++ benchmarks. The specific errors were of the form: "ld: duplicate symbol ?" rdar://9660124 Modified: llvm/trunk/tools/lto/LTOModule.cpp Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=133955&r1=133954&r2=133955&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Mon Jun 27 17:54:29 2011 @@ -208,7 +208,7 @@ if (objcClassNameFromExpression(c->getOperand(1), superclassName)) { NameAndAttributes info; StringMap::value_type &entry = - _undefines.GetOrCreateValue(superclassName); + _undefines.GetOrCreateValue(superclassName.c_str()); if (!entry.getValue().name) { const char *symbolName = entry.getKey().data(); info.name = symbolName; @@ -220,7 +220,7 @@ std::string className; if (objcClassNameFromExpression(c->getOperand(2), className)) { StringSet::value_type &entry = - _defines.GetOrCreateValue(className); + _defines.GetOrCreateValue(className.c_str()); entry.setValue(1); NameAndAttributes info; info.name = entry.getKey().data(); @@ -243,7 +243,7 @@ NameAndAttributes info; StringMap::value_type &entry = - _undefines.GetOrCreateValue(targetclassName); + _undefines.GetOrCreateValue(targetclassName.c_str()); if (entry.getValue().name) return; @@ -264,7 +264,7 @@ NameAndAttributes info; StringMap::value_type &entry = - _undefines.GetOrCreateValue(targetclassName); + _undefines.GetOrCreateValue(targetclassName.c_str()); if (entry.getValue().name) return; @@ -375,7 +375,7 @@ // add to table of symbols NameAndAttributes info; - StringSet::value_type &entry = _defines.GetOrCreateValue(Buffer); + StringSet::value_type &entry = _defines.GetOrCreateValue(Buffer.c_str()); entry.setValue(1); StringRef Name = entry.getKey(); @@ -436,7 +436,7 @@ mangler.getNameWithPrefix(name, decl, false); StringMap::value_type &entry = - _undefines.GetOrCreateValue(name); + _undefines.GetOrCreateValue(name.c_str()); // we already have the symbol if (entry.getValue().name) From atrick at apple.com Mon Jun 27 18:17:44 2011 From: atrick at apple.com (Andrew Trick) Date: Mon, 27 Jun 2011 23:17:44 -0000 Subject: [llvm-commits] [llvm] r133959 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110627231744.D38E62A6C12C@llvm.org> Author: atrick Date: Mon Jun 27 18:17:44 2011 New Revision: 133959 URL: http://llvm.org/viewvc/llvm-project?rev=133959&view=rev Log: indvars -disable-iv-rewrite: run RLEV after SimplifyIVUsers for a bit more control over the order SCEVs are evaluated. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=133959&r1=133958&r2=133959&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Jun 27 18:17:44 2011 @@ -1158,8 +1158,12 @@ // Create a rewriter object which we'll use to transform the code with. SCEVExpander Rewriter(*SE); - if (DisableIVRewrite) + + // Eliminate redundant IV users. + if (DisableIVRewrite) { Rewriter.disableCanonicalMode(); + SimplifyIVUsersNoRewrite(L, Rewriter); + } // Check to see if this loop has a computable loop-invariant execution count. // If so, this means that we can compute the final value of any expressions @@ -1171,9 +1175,7 @@ RewriteLoopExitValues(L, Rewriter); // Eliminate redundant IV users. - if (DisableIVRewrite) - SimplifyIVUsersNoRewrite(L, Rewriter); - else + if (!DisableIVRewrite) SimplifyIVUsers(Rewriter); // Compute the type of the largest recurrence expression, and decide whether From sanjoy at playingwithpointers.com Mon Jun 27 11:37:52 2011 From: sanjoy at playingwithpointers.com (Sanjoy Das) Date: Mon, 27 Jun 2011 22:07:52 +0530 Subject: [llvm-commits] Segmented stacks, current status. In-Reply-To: References: <4E089271.40607@playingwithpointers.com> Message-ID: <4E08B1E0.1040200@playingwithpointers.com> Hi! > > + TlsReg = X86::FS; > + TlsOffset = 0x70; > + > ... > + } else { > + TlsReg = X86::GS; > + TlsOffset = 0x30; > > Are you sure this will work on all subtargets we support? > Now that you point it out, I think these will only work on GNU/Linux. The actual slot in the TCB is currently dictated by libgcc; on which I'm relying heavily for runtime support. Perhaps it would be a good idea to not have non linux support for the time being; with llvm displaying an error in case -segmented-stacks is used on Windows or something equivalent (I'll add this in the next iteration). If need arises, support for other platforms can be added by either patching libgcc, or by adding a similar interface to compiler-rt. -- Sanjoy Das http://playingwithpointers.com From evan.cheng at apple.com Mon Jun 27 18:40:45 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 27 Jun 2011 23:40:45 -0000 Subject: [llvm-commits] [llvm] r133962 - in /llvm/trunk: include/llvm/CodeGen/Passes.h include/llvm/InitializePasses.h lib/CodeGen/CodeGen.cpp lib/CodeGen/PreAllocSplitting.cpp lib/CodeGen/RegAllocLinearScan.cpp test/CodeGen/X86/pre-split1.ll test/CodeGen/X86/pre-split10.ll test/CodeGen/X86/pre-split11.ll test/CodeGen/X86/pre-split4.ll test/CodeGen/X86/pre-split5.ll test/CodeGen/X86/pre-split6.ll test/CodeGen/X86/pre-split7.ll test/CodeGen/X86/pre-split8.ll test/CodeGen/X86/pre-split9.ll Message-ID: <20110627234045.665462A6C12C@llvm.org> Author: evancheng Date: Mon Jun 27 18:40:45 2011 New Revision: 133962 URL: http://llvm.org/viewvc/llvm-project?rev=133962&view=rev Log: Remove the experimental (and unused) pre-ra splitting pass. Greedy regalloc can split live ranges. Removed: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp llvm/trunk/test/CodeGen/X86/pre-split1.ll llvm/trunk/test/CodeGen/X86/pre-split10.ll llvm/trunk/test/CodeGen/X86/pre-split11.ll llvm/trunk/test/CodeGen/X86/pre-split4.ll llvm/trunk/test/CodeGen/X86/pre-split5.ll llvm/trunk/test/CodeGen/X86/pre-split6.ll llvm/trunk/test/CodeGen/X86/pre-split7.ll llvm/trunk/test/CodeGen/X86/pre-split8.ll llvm/trunk/test/CodeGen/X86/pre-split9.ll Modified: llvm/trunk/include/llvm/CodeGen/Passes.h llvm/trunk/include/llvm/InitializePasses.h llvm/trunk/lib/CodeGen/CodeGen.cpp llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Modified: llvm/trunk/include/llvm/CodeGen/Passes.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/Passes.h?rev=133962&r1=133961&r2=133962&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/Passes.h (original) +++ llvm/trunk/include/llvm/CodeGen/Passes.h Mon Jun 27 18:40:45 2011 @@ -73,8 +73,6 @@ /// This pass is still in development extern char &StrongPHIEliminationID; - extern char &PreAllocSplittingID; - /// LiveStacks pass. An analysis keeping track of the liveness of stack slots. extern char &LiveStacksID; Modified: llvm/trunk/include/llvm/InitializePasses.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/InitializePasses.h?rev=133962&r1=133961&r2=133962&view=diff ============================================================================== --- llvm/trunk/include/llvm/InitializePasses.h (original) +++ llvm/trunk/include/llvm/InitializePasses.h Mon Jun 27 18:40:45 2011 @@ -177,7 +177,6 @@ void initializePostDomPrinterPass(PassRegistry&); void initializePostDomViewerPass(PassRegistry&); void initializePostDominatorTreePass(PassRegistry&); -void initializePreAllocSplittingPass(PassRegistry&); void initializePreVerifierPass(PassRegistry&); void initializePrintDbgInfoPass(PassRegistry&); void initializePrintFunctionPassPass(PassRegistry&); Modified: llvm/trunk/lib/CodeGen/CodeGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CodeGen.cpp?rev=133962&r1=133961&r2=133962&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CodeGen.cpp (original) +++ llvm/trunk/lib/CodeGen/CodeGen.cpp Mon Jun 27 18:40:45 2011 @@ -37,7 +37,6 @@ initializeOptimizePHIsPass(Registry); initializePHIEliminationPass(Registry); initializePeepholeOptimizerPass(Registry); - initializePreAllocSplittingPass(Registry); initializeProcessImplicitDefsPass(Registry); initializePEIPass(Registry); initializeRALinScanPass(Registry); Removed: llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp?rev=133961&view=auto ============================================================================== --- llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (original) +++ llvm/trunk/lib/CodeGen/PreAllocSplitting.cpp (removed) @@ -1,1430 +0,0 @@ -//===-- PreAllocSplitting.cpp - Pre-allocation Interval Spltting Pass. ----===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the machine instruction level pre-register allocation -// live interval splitting pass. It finds live interval barriers, i.e. -// instructions which will kill all physical registers in certain register -// classes, and split all live intervals which cross the barrier. -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "pre-alloc-split" -#include "VirtRegMap.h" -#include "RegisterCoalescer.h" -#include "llvm/CodeGen/CalcSpillWeights.h" -#include "llvm/CodeGen/LiveIntervalAnalysis.h" -#include "llvm/CodeGen/LiveStackAnalysis.h" -#include "llvm/CodeGen/MachineDominators.h" -#include "llvm/CodeGen/MachineFrameInfo.h" -#include "llvm/CodeGen/MachineFunctionPass.h" -#include "llvm/CodeGen/MachineLoopInfo.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetMachine.h" -#include "llvm/Target/TargetOptions.h" -#include "llvm/Target/TargetRegisterInfo.h" -#include "llvm/Support/CommandLine.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/ErrorHandling.h" -#include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/DepthFirstIterator.h" -#include "llvm/ADT/SmallPtrSet.h" -#include "llvm/ADT/Statistic.h" -using namespace llvm; - -static cl::opt PreSplitLimit("pre-split-limit", cl::init(-1), cl::Hidden); -static cl::opt DeadSplitLimit("dead-split-limit", cl::init(-1), - cl::Hidden); -static cl::opt RestoreFoldLimit("restore-fold-limit", cl::init(-1), - cl::Hidden); - -STATISTIC(NumSplits, "Number of intervals split"); -STATISTIC(NumRemats, "Number of intervals split by rematerialization"); -STATISTIC(NumFolds, "Number of intervals split with spill folding"); -STATISTIC(NumRestoreFolds, "Number of intervals split with restore folding"); -STATISTIC(NumRenumbers, "Number of intervals renumbered into new registers"); -STATISTIC(NumDeadSpills, "Number of dead spills removed"); - -namespace { - class PreAllocSplitting : public MachineFunctionPass { - MachineFunction *CurrMF; - const TargetMachine *TM; - const TargetInstrInfo *TII; - const TargetRegisterInfo* TRI; - MachineFrameInfo *MFI; - MachineRegisterInfo *MRI; - SlotIndexes *SIs; - LiveIntervals *LIs; - LiveStacks *LSs; - VirtRegMap *VRM; - - // Barrier - Current barrier being processed. - MachineInstr *Barrier; - - // BarrierMBB - Basic block where the barrier resides in. - MachineBasicBlock *BarrierMBB; - - // Barrier - Current barrier index. - SlotIndex BarrierIdx; - - // CurrLI - Current live interval being split. - LiveInterval *CurrLI; - - // CurrSLI - Current stack slot live interval. - LiveInterval *CurrSLI; - - // CurrSValNo - Current val# for the stack slot live interval. - VNInfo *CurrSValNo; - - // IntervalSSMap - A map from live interval to spill slots. - DenseMap IntervalSSMap; - - // Def2SpillMap - A map from a def instruction index to spill index. - DenseMap Def2SpillMap; - - public: - static char ID; - PreAllocSplitting() : MachineFunctionPass(ID) { - initializePreAllocSplittingPass(*PassRegistry::getPassRegistry()); - } - - virtual bool runOnMachineFunction(MachineFunction &MF); - - virtual void getAnalysisUsage(AnalysisUsage &AU) const { - AU.setPreservesCFG(); - AU.addRequired(); - AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); - AU.addRequired(); - AU.addPreserved(); - AU.addPreserved(); - AU.addPreserved(); - AU.addPreservedID(StrongPHIEliminationID); - AU.addPreservedID(PHIEliminationID); - AU.addRequired(); - AU.addRequired(); - AU.addRequired(); - AU.addPreserved(); - AU.addPreserved(); - AU.addPreserved(); - MachineFunctionPass::getAnalysisUsage(AU); - } - - virtual void releaseMemory() { - IntervalSSMap.clear(); - Def2SpillMap.clear(); - } - - virtual const char *getPassName() const { - return "Pre-Register Allocaton Live Interval Splitting"; - } - - /// print - Implement the dump method. - virtual void print(raw_ostream &O, const Module* M = 0) const { - LIs->print(O, M); - } - - - private: - - MachineBasicBlock::iterator - findSpillPoint(MachineBasicBlock*, MachineInstr*, MachineInstr*, - SmallPtrSet&); - - MachineBasicBlock::iterator - findRestorePoint(MachineBasicBlock*, MachineInstr*, SlotIndex, - SmallPtrSet&); - - int CreateSpillStackSlot(unsigned, const TargetRegisterClass *); - - bool IsAvailableInStack(MachineBasicBlock*, unsigned, - SlotIndex, SlotIndex, - SlotIndex&, int&) const; - - void UpdateSpillSlotInterval(VNInfo*, SlotIndex, SlotIndex); - - bool SplitRegLiveInterval(LiveInterval*); - - bool SplitRegLiveIntervals(const TargetRegisterClass **, - SmallPtrSet&); - - bool createsNewJoin(LiveRange* LR, MachineBasicBlock* DefMBB, - MachineBasicBlock* BarrierMBB); - bool Rematerialize(unsigned vreg, VNInfo* ValNo, - MachineInstr* DefMI, - MachineBasicBlock::iterator RestorePt, - SmallPtrSet& RefsInMBB); - MachineInstr* FoldSpill(unsigned vreg, const TargetRegisterClass* RC, - MachineInstr* DefMI, - MachineInstr* Barrier, - MachineBasicBlock* MBB, - int& SS, - SmallPtrSet& RefsInMBB); - MachineInstr* FoldRestore(unsigned vreg, - const TargetRegisterClass* RC, - MachineInstr* Barrier, - MachineBasicBlock* MBB, - int SS, - SmallPtrSet& RefsInMBB); - void RenumberValno(VNInfo* VN); - void ReconstructLiveInterval(LiveInterval* LI); - bool removeDeadSpills(SmallPtrSet& split); - unsigned getNumberOfNonSpills(SmallPtrSet& MIs, - unsigned Reg, int FrameIndex, bool& TwoAddr); - VNInfo* PerformPHIConstruction(MachineBasicBlock::iterator Use, - MachineBasicBlock* MBB, LiveInterval* LI, - SmallPtrSet& Visited, - DenseMap >& Defs, - DenseMap >& Uses, - DenseMap& NewVNs, - DenseMap& LiveOut, - DenseMap& Phis, - bool IsTopLevel, bool IsIntraBlock); - VNInfo* PerformPHIConstructionFallBack(MachineBasicBlock::iterator Use, - MachineBasicBlock* MBB, LiveInterval* LI, - SmallPtrSet& Visited, - DenseMap >& Defs, - DenseMap >& Uses, - DenseMap& NewVNs, - DenseMap& LiveOut, - DenseMap& Phis, - bool IsTopLevel, bool IsIntraBlock); -}; -} // end anonymous namespace - -char PreAllocSplitting::ID = 0; - -INITIALIZE_PASS_BEGIN(PreAllocSplitting, "pre-alloc-splitting", - "Pre-Register Allocation Live Interval Splitting", - false, false) -INITIALIZE_PASS_DEPENDENCY(SlotIndexes) -INITIALIZE_PASS_DEPENDENCY(LiveIntervals) -INITIALIZE_PASS_DEPENDENCY(LiveStacks) -INITIALIZE_PASS_DEPENDENCY(MachineDominatorTree) -INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) -INITIALIZE_PASS_DEPENDENCY(VirtRegMap) -INITIALIZE_PASS_END(PreAllocSplitting, "pre-alloc-splitting", - "Pre-Register Allocation Live Interval Splitting", - false, false) - -char &llvm::PreAllocSplittingID = PreAllocSplitting::ID; - -/// findSpillPoint - Find a gap as far away from the given MI that's suitable -/// for spilling the current live interval. The index must be before any -/// defs and uses of the live interval register in the mbb. Return begin() if -/// none is found. -MachineBasicBlock::iterator -PreAllocSplitting::findSpillPoint(MachineBasicBlock *MBB, MachineInstr *MI, - MachineInstr *DefMI, - SmallPtrSet &RefsInMBB) { - MachineBasicBlock::iterator Pt = MBB->begin(); - - MachineBasicBlock::iterator MII = MI; - MachineBasicBlock::iterator EndPt = DefMI - ? MachineBasicBlock::iterator(DefMI) : MBB->begin(); - - while (MII != EndPt && !RefsInMBB.count(MII) && - MII->getOpcode() != TRI->getCallFrameSetupOpcode()) - --MII; - if (MII == EndPt || RefsInMBB.count(MII)) return Pt; - - while (MII != EndPt && !RefsInMBB.count(MII)) { - // We can't insert the spill between the barrier (a call), and its - // corresponding call frame setup. - if (MII->getOpcode() == TRI->getCallFrameDestroyOpcode()) { - while (MII->getOpcode() != TRI->getCallFrameSetupOpcode()) { - --MII; - if (MII == EndPt) { - return Pt; - } - } - continue; - } else { - Pt = MII; - } - - if (RefsInMBB.count(MII)) - return Pt; - - - --MII; - } - - return Pt; -} - -/// findRestorePoint - Find a gap in the instruction index map that's suitable -/// for restoring the current live interval value. The index must be before any -/// uses of the live interval register in the mbb. Return end() if none is -/// found. -MachineBasicBlock::iterator -PreAllocSplitting::findRestorePoint(MachineBasicBlock *MBB, MachineInstr *MI, - SlotIndex LastIdx, - SmallPtrSet &RefsInMBB) { - // FIXME: Allow spill to be inserted to the beginning of the mbb. Update mbb - // begin index accordingly. - MachineBasicBlock::iterator Pt = MBB->end(); - MachineBasicBlock::iterator EndPt = MBB->getFirstTerminator(); - - // We start at the call, so walk forward until we find the call frame teardown - // since we can't insert restores before that. Bail if we encounter a use - // during this time. - MachineBasicBlock::iterator MII = MI; - if (MII == EndPt) return Pt; - - while (MII != EndPt && !RefsInMBB.count(MII) && - MII->getOpcode() != TRI->getCallFrameDestroyOpcode()) - ++MII; - if (MII == EndPt || RefsInMBB.count(MII)) return Pt; - ++MII; - - // FIXME: Limit the number of instructions to examine to reduce - // compile time? - while (MII != EndPt) { - SlotIndex Index = LIs->getInstructionIndex(MII); - if (Index > LastIdx) - break; - - // We can't insert a restore between the barrier (a call) and its - // corresponding call frame teardown. - if (MII->getOpcode() == TRI->getCallFrameSetupOpcode()) { - do { - if (MII == EndPt || RefsInMBB.count(MII)) return Pt; - ++MII; - } while (MII->getOpcode() != TRI->getCallFrameDestroyOpcode()); - } else { - Pt = MII; - } - - if (RefsInMBB.count(MII)) - return Pt; - - ++MII; - } - - return Pt; -} - -/// CreateSpillStackSlot - Create a stack slot for the live interval being -/// split. If the live interval was previously split, just reuse the same -/// slot. -int PreAllocSplitting::CreateSpillStackSlot(unsigned Reg, - const TargetRegisterClass *RC) { - int SS; - DenseMap::iterator I = IntervalSSMap.find(Reg); - if (I != IntervalSSMap.end()) { - SS = I->second; - } else { - SS = MFI->CreateSpillStackObject(RC->getSize(), RC->getAlignment()); - IntervalSSMap[Reg] = SS; - } - - // Create live interval for stack slot. - CurrSLI = &LSs->getOrCreateInterval(SS, RC); - if (CurrSLI->hasAtLeastOneValue()) - CurrSValNo = CurrSLI->getValNumInfo(0); - else - CurrSValNo = CurrSLI->getNextValue(SlotIndex(), 0, - LSs->getVNInfoAllocator()); - return SS; -} - -/// IsAvailableInStack - Return true if register is available in a split stack -/// slot at the specified index. -bool -PreAllocSplitting::IsAvailableInStack(MachineBasicBlock *DefMBB, - unsigned Reg, SlotIndex DefIndex, - SlotIndex RestoreIndex, - SlotIndex &SpillIndex, - int& SS) const { - if (!DefMBB) - return false; - - DenseMap::const_iterator I = IntervalSSMap.find(Reg); - if (I == IntervalSSMap.end()) - return false; - DenseMap::const_iterator - II = Def2SpillMap.find(DefIndex); - if (II == Def2SpillMap.end()) - return false; - - // If last spill of def is in the same mbb as barrier mbb (where restore will - // be), make sure it's not below the intended restore index. - // FIXME: Undo the previous spill? - assert(LIs->getMBBFromIndex(II->second) == DefMBB); - if (DefMBB == BarrierMBB && II->second >= RestoreIndex) - return false; - - SS = I->second; - SpillIndex = II->second; - return true; -} - -/// UpdateSpillSlotInterval - Given the specified val# of the register live -/// interval being split, and the spill and restore indicies, update the live -/// interval of the spill stack slot. -void -PreAllocSplitting::UpdateSpillSlotInterval(VNInfo *ValNo, SlotIndex SpillIndex, - SlotIndex RestoreIndex) { - assert(LIs->getMBBFromIndex(RestoreIndex) == BarrierMBB && - "Expect restore in the barrier mbb"); - - MachineBasicBlock *MBB = LIs->getMBBFromIndex(SpillIndex); - if (MBB == BarrierMBB) { - // Intra-block spill + restore. We are done. - LiveRange SLR(SpillIndex, RestoreIndex, CurrSValNo); - CurrSLI->addRange(SLR); - return; - } - - SmallPtrSet Processed; - SlotIndex EndIdx = LIs->getMBBEndIdx(MBB); - LiveRange SLR(SpillIndex, EndIdx, CurrSValNo); - CurrSLI->addRange(SLR); - Processed.insert(MBB); - - // Start from the spill mbb, figure out the extend of the spill slot's - // live interval. - SmallVector WorkList; - const LiveRange *LR = CurrLI->getLiveRangeContaining(SpillIndex); - if (LR->end > EndIdx) - // If live range extend beyond end of mbb, add successors to work list. - for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), - SE = MBB->succ_end(); SI != SE; ++SI) - WorkList.push_back(*SI); - - while (!WorkList.empty()) { - MachineBasicBlock *MBB = WorkList.back(); - WorkList.pop_back(); - if (Processed.count(MBB)) - continue; - SlotIndex Idx = LIs->getMBBStartIdx(MBB); - LR = CurrLI->getLiveRangeContaining(Idx); - if (LR && LR->valno == ValNo) { - EndIdx = LIs->getMBBEndIdx(MBB); - if (Idx <= RestoreIndex && RestoreIndex < EndIdx) { - // Spill slot live interval stops at the restore. - LiveRange SLR(Idx, RestoreIndex, CurrSValNo); - CurrSLI->addRange(SLR); - } else if (LR->end > EndIdx) { - // Live range extends beyond end of mbb, process successors. - LiveRange SLR(Idx, EndIdx.getNextIndex(), CurrSValNo); - CurrSLI->addRange(SLR); - for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(), - SE = MBB->succ_end(); SI != SE; ++SI) - WorkList.push_back(*SI); - } else { - LiveRange SLR(Idx, LR->end, CurrSValNo); - CurrSLI->addRange(SLR); - } - Processed.insert(MBB); - } - } -} - -/// PerformPHIConstruction - From properly set up use and def lists, use a PHI -/// construction algorithm to compute the ranges and valnos for an interval. -VNInfo* -PreAllocSplitting::PerformPHIConstruction(MachineBasicBlock::iterator UseI, - MachineBasicBlock* MBB, LiveInterval* LI, - SmallPtrSet& Visited, - DenseMap >& Defs, - DenseMap >& Uses, - DenseMap& NewVNs, - DenseMap& LiveOut, - DenseMap& Phis, - bool IsTopLevel, bool IsIntraBlock) { - // Return memoized result if it's available. - if (IsTopLevel && Visited.count(UseI) && NewVNs.count(UseI)) - return NewVNs[UseI]; - else if (!IsTopLevel && IsIntraBlock && NewVNs.count(UseI)) - return NewVNs[UseI]; - else if (!IsIntraBlock && LiveOut.count(MBB)) - return LiveOut[MBB]; - - // Check if our block contains any uses or defs. - bool ContainsDefs = Defs.count(MBB); - bool ContainsUses = Uses.count(MBB); - - VNInfo* RetVNI = 0; - - // Enumerate the cases of use/def contaning blocks. - if (!ContainsDefs && !ContainsUses) { - return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, Uses, - NewVNs, LiveOut, Phis, - IsTopLevel, IsIntraBlock); - } else if (ContainsDefs && !ContainsUses) { - SmallPtrSet& BlockDefs = Defs[MBB]; - - // Search for the def in this block. If we don't find it before the - // instruction we care about, go to the fallback case. Note that that - // should never happen: this cannot be intrablock, so use should - // always be an end() iterator. - assert(UseI == MBB->end() && "No use marked in intrablock"); - - MachineBasicBlock::iterator Walker = UseI; - --Walker; - while (Walker != MBB->begin()) { - if (BlockDefs.count(Walker)) - break; - --Walker; - } - - // Once we've found it, extend its VNInfo to our instruction. - SlotIndex DefIndex = LIs->getInstructionIndex(Walker); - DefIndex = DefIndex.getDefIndex(); - SlotIndex EndIndex = LIs->getMBBEndIdx(MBB); - - RetVNI = NewVNs[Walker]; - LI->addRange(LiveRange(DefIndex, EndIndex, RetVNI)); - } else if (!ContainsDefs && ContainsUses) { - SmallPtrSet& BlockUses = Uses[MBB]; - - // Search for the use in this block that precedes the instruction we care - // about, going to the fallback case if we don't find it. - MachineBasicBlock::iterator Walker = UseI; - bool found = false; - while (Walker != MBB->begin()) { - --Walker; - if (BlockUses.count(Walker)) { - found = true; - break; - } - } - - if (!found) - return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, - Uses, NewVNs, LiveOut, Phis, - IsTopLevel, IsIntraBlock); - - SlotIndex UseIndex = LIs->getInstructionIndex(Walker); - UseIndex = UseIndex.getUseIndex(); - SlotIndex EndIndex; - if (IsIntraBlock) { - EndIndex = LIs->getInstructionIndex(UseI).getDefIndex(); - } else - EndIndex = LIs->getMBBEndIdx(MBB); - - // Now, recursively phi construct the VNInfo for the use we found, - // and then extend it to include the instruction we care about - RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses, - NewVNs, LiveOut, Phis, false, true); - - LI->addRange(LiveRange(UseIndex, EndIndex, RetVNI)); - - // FIXME: Need to set kills properly for inter-block stuff. - } else if (ContainsDefs && ContainsUses) { - SmallPtrSet& BlockDefs = Defs[MBB]; - SmallPtrSet& BlockUses = Uses[MBB]; - - // This case is basically a merging of the two preceding case, with the - // special note that checking for defs must take precedence over checking - // for uses, because of two-address instructions. - MachineBasicBlock::iterator Walker = UseI; - bool foundDef = false; - bool foundUse = false; - while (Walker != MBB->begin()) { - --Walker; - if (BlockDefs.count(Walker)) { - foundDef = true; - break; - } else if (BlockUses.count(Walker)) { - foundUse = true; - break; - } - } - - if (!foundDef && !foundUse) - return PerformPHIConstructionFallBack(UseI, MBB, LI, Visited, Defs, - Uses, NewVNs, LiveOut, Phis, - IsTopLevel, IsIntraBlock); - - SlotIndex StartIndex = LIs->getInstructionIndex(Walker); - StartIndex = foundDef ? StartIndex.getDefIndex() : StartIndex.getUseIndex(); - SlotIndex EndIndex; - if (IsIntraBlock) { - EndIndex = LIs->getInstructionIndex(UseI).getDefIndex(); - } else - EndIndex = LIs->getMBBEndIdx(MBB); - - if (foundDef) - RetVNI = NewVNs[Walker]; - else - RetVNI = PerformPHIConstruction(Walker, MBB, LI, Visited, Defs, Uses, - NewVNs, LiveOut, Phis, false, true); - - LI->addRange(LiveRange(StartIndex, EndIndex, RetVNI)); - } - - // Memoize results so we don't have to recompute them. - if (!IsIntraBlock) LiveOut[MBB] = RetVNI; - else { - if (!NewVNs.count(UseI)) - NewVNs[UseI] = RetVNI; - Visited.insert(UseI); - } - - return RetVNI; -} - -/// PerformPHIConstructionFallBack - PerformPHIConstruction fall back path. -/// -VNInfo* -PreAllocSplitting::PerformPHIConstructionFallBack(MachineBasicBlock::iterator UseI, - MachineBasicBlock* MBB, LiveInterval* LI, - SmallPtrSet& Visited, - DenseMap >& Defs, - DenseMap >& Uses, - DenseMap& NewVNs, - DenseMap& LiveOut, - DenseMap& Phis, - bool IsTopLevel, bool IsIntraBlock) { - // NOTE: Because this is the fallback case from other cases, we do NOT - // assume that we are not intrablock here. - if (Phis.count(MBB)) return Phis[MBB]; - - SlotIndex StartIndex = LIs->getMBBStartIdx(MBB); - VNInfo *RetVNI = Phis[MBB] = - LI->getNextValue(SlotIndex(), /*FIXME*/ 0, - LIs->getVNInfoAllocator()); - - if (!IsIntraBlock) LiveOut[MBB] = RetVNI; - - // If there are no uses or defs between our starting point and the - // beginning of the block, then recursive perform phi construction - // on our predecessors. - DenseMap IncomingVNs; - for (MachineBasicBlock::pred_iterator PI = MBB->pred_begin(), - PE = MBB->pred_end(); PI != PE; ++PI) { - VNInfo* Incoming = PerformPHIConstruction((*PI)->end(), *PI, LI, - Visited, Defs, Uses, NewVNs, - LiveOut, Phis, false, false); - if (Incoming != 0) - IncomingVNs[*PI] = Incoming; - } - - if (MBB->pred_size() == 1 && !RetVNI->hasPHIKill()) { - VNInfo* OldVN = RetVNI; - VNInfo* NewVN = IncomingVNs.begin()->second; - VNInfo* MergedVN = LI->MergeValueNumberInto(OldVN, NewVN); - if (MergedVN == OldVN) std::swap(OldVN, NewVN); - - for (DenseMap::iterator LOI = LiveOut.begin(), - LOE = LiveOut.end(); LOI != LOE; ++LOI) - if (LOI->second == OldVN) - LOI->second = MergedVN; - for (DenseMap::iterator NVI = NewVNs.begin(), - NVE = NewVNs.end(); NVI != NVE; ++NVI) - if (NVI->second == OldVN) - NVI->second = MergedVN; - for (DenseMap::iterator PI = Phis.begin(), - PE = Phis.end(); PI != PE; ++PI) - if (PI->second == OldVN) - PI->second = MergedVN; - RetVNI = MergedVN; - } else { - // Otherwise, merge the incoming VNInfos with a phi join. Create a new - // VNInfo to represent the joined value. - for (DenseMap::iterator I = - IncomingVNs.begin(), E = IncomingVNs.end(); I != E; ++I) { - I->second->setHasPHIKill(true); - } - } - - SlotIndex EndIndex; - if (IsIntraBlock) { - EndIndex = LIs->getInstructionIndex(UseI).getDefIndex(); - } else - EndIndex = LIs->getMBBEndIdx(MBB); - LI->addRange(LiveRange(StartIndex, EndIndex, RetVNI)); - - // Memoize results so we don't have to recompute them. - if (!IsIntraBlock) - LiveOut[MBB] = RetVNI; - else { - if (!NewVNs.count(UseI)) - NewVNs[UseI] = RetVNI; - Visited.insert(UseI); - } - - return RetVNI; -} - -/// ReconstructLiveInterval - Recompute a live interval from scratch. -void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) { - VNInfo::Allocator& Alloc = LIs->getVNInfoAllocator(); - - // Clear the old ranges and valnos; - LI->clear(); - - // Cache the uses and defs of the register - typedef DenseMap > RegMap; - RegMap Defs, Uses; - - // Keep track of the new VNs we're creating. - DenseMap NewVNs; - SmallPtrSet PhiVNs; - - // Cache defs, and create a new VNInfo for each def. - for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg), - DE = MRI->def_end(); DI != DE; ++DI) { - Defs[(*DI).getParent()].insert(&*DI); - - SlotIndex DefIdx = LIs->getInstructionIndex(&*DI); - DefIdx = DefIdx.getDefIndex(); - - assert(!DI->isPHI() && "PHI instr in code during pre-alloc splitting."); - VNInfo* NewVN = LI->getNextValue(DefIdx, 0, Alloc); - - // If the def is a move, set the copy field. - if (DI->isCopyLike() && DI->getOperand(0).getReg() == LI->reg) - NewVN->setCopy(&*DI); - - NewVNs[&*DI] = NewVN; - } - - // Cache uses as a separate pass from actually processing them. - for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg), - UE = MRI->use_end(); UI != UE; ++UI) - Uses[(*UI).getParent()].insert(&*UI); - - // Now, actually process every use and use a phi construction algorithm - // to walk from it to its reaching definitions, building VNInfos along - // the way. - DenseMap LiveOut; - DenseMap Phis; - SmallPtrSet Visited; - for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(LI->reg), - UE = MRI->use_end(); UI != UE; ++UI) { - PerformPHIConstruction(&*UI, UI->getParent(), LI, Visited, Defs, - Uses, NewVNs, LiveOut, Phis, true, true); - } - - // Add ranges for dead defs - for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(LI->reg), - DE = MRI->def_end(); DI != DE; ++DI) { - SlotIndex DefIdx = LIs->getInstructionIndex(&*DI); - DefIdx = DefIdx.getDefIndex(); - - if (LI->liveAt(DefIdx)) continue; - - VNInfo* DeadVN = NewVNs[&*DI]; - LI->addRange(LiveRange(DefIdx, DefIdx.getNextSlot(), DeadVN)); - } -} - -/// RenumberValno - Split the given valno out into a new vreg, allowing it to -/// be allocated to a different register. This function creates a new vreg, -/// copies the valno and its live ranges over to the new vreg's interval, -/// removes them from the old interval, and rewrites all uses and defs of -/// the original reg to the new vreg within those ranges. -void PreAllocSplitting::RenumberValno(VNInfo* VN) { - SmallVector Stack; - SmallVector VNsToCopy; - Stack.push_back(VN); - - // Walk through and copy the valno we care about, and any other valnos - // that are two-address redefinitions of the one we care about. These - // will need to be rewritten as well. We also check for safety of the - // renumbering here, by making sure that none of the valno involved has - // phi kills. - while (!Stack.empty()) { - VNInfo* OldVN = Stack.back(); - Stack.pop_back(); - - // Bail out if we ever encounter a valno that has a PHI kill. We can't - // renumber these. - if (OldVN->hasPHIKill()) return; - - VNsToCopy.push_back(OldVN); - - // Locate two-address redefinitions - for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(CurrLI->reg), - DE = MRI->def_end(); DI != DE; ++DI) { - if (!DI->isRegTiedToUseOperand(DI.getOperandNo())) continue; - SlotIndex DefIdx = LIs->getInstructionIndex(&*DI).getDefIndex(); - VNInfo* NextVN = CurrLI->findDefinedVNInfoForRegInt(DefIdx); - if (std::find(VNsToCopy.begin(), VNsToCopy.end(), NextVN) != - VNsToCopy.end()) - Stack.push_back(NextVN); - } - } - - // Create the new vreg - unsigned NewVReg = MRI->createVirtualRegister(MRI->getRegClass(CurrLI->reg)); - - // Create the new live interval - LiveInterval& NewLI = LIs->getOrCreateInterval(NewVReg); - - for (SmallVector::iterator OI = VNsToCopy.begin(), OE = - VNsToCopy.end(); OI != OE; ++OI) { - VNInfo* OldVN = *OI; - - // Copy the valno over - VNInfo* NewVN = NewLI.createValueCopy(OldVN, LIs->getVNInfoAllocator()); - NewLI.MergeValueInAsValue(*CurrLI, OldVN, NewVN); - - // Remove the valno from the old interval - CurrLI->removeValNo(OldVN); - } - - // Rewrite defs and uses. This is done in two stages to avoid invalidating - // the reg_iterator. - SmallVector, 8> OpsToChange; - - for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg), - E = MRI->reg_end(); I != E; ++I) { - MachineOperand& MO = I.getOperand(); - SlotIndex InstrIdx = LIs->getInstructionIndex(&*I); - - if ((MO.isUse() && NewLI.liveAt(InstrIdx.getUseIndex())) || - (MO.isDef() && NewLI.liveAt(InstrIdx.getDefIndex()))) - OpsToChange.push_back(std::make_pair(&*I, I.getOperandNo())); - } - - for (SmallVector, 8>::iterator I = - OpsToChange.begin(), E = OpsToChange.end(); I != E; ++I) { - MachineInstr* Inst = I->first; - unsigned OpIdx = I->second; - MachineOperand& MO = Inst->getOperand(OpIdx); - MO.setReg(NewVReg); - } - - // Grow the VirtRegMap, since we've created a new vreg. - VRM->grow(); - - // The renumbered vreg shares a stack slot with the old register. - if (IntervalSSMap.count(CurrLI->reg)) - IntervalSSMap[NewVReg] = IntervalSSMap[CurrLI->reg]; - - ++NumRenumbers; -} - -bool PreAllocSplitting::Rematerialize(unsigned VReg, VNInfo* ValNo, - MachineInstr* DefMI, - MachineBasicBlock::iterator RestorePt, - SmallPtrSet& RefsInMBB) { - MachineBasicBlock& MBB = *RestorePt->getParent(); - - MachineBasicBlock::iterator KillPt = BarrierMBB->end(); - if (!DefMI || DefMI->getParent() == BarrierMBB) - KillPt = findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB); - else - KillPt = llvm::next(MachineBasicBlock::iterator(DefMI)); - - if (KillPt == DefMI->getParent()->end()) - return false; - - TII->reMaterialize(MBB, RestorePt, VReg, 0, DefMI, *TRI); - SlotIndex RematIdx = LIs->InsertMachineInstrInMaps(prior(RestorePt)); - - ReconstructLiveInterval(CurrLI); - RematIdx = RematIdx.getDefIndex(); - RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RematIdx)); - - ++NumSplits; - ++NumRemats; - return true; -} - -MachineInstr* PreAllocSplitting::FoldSpill(unsigned vreg, - const TargetRegisterClass* RC, - MachineInstr* DefMI, - MachineInstr* Barrier, - MachineBasicBlock* MBB, - int& SS, - SmallPtrSet& RefsInMBB) { - // Go top down if RefsInMBB is empty. - if (RefsInMBB.empty()) - return 0; - - MachineBasicBlock::iterator FoldPt = Barrier; - while (&*FoldPt != DefMI && FoldPt != MBB->begin() && - !RefsInMBB.count(FoldPt)) - --FoldPt; - - int OpIdx = FoldPt->findRegisterDefOperandIdx(vreg); - if (OpIdx == -1) - return 0; - - SmallVector Ops; - Ops.push_back(OpIdx); - - if (!TII->canFoldMemoryOperand(FoldPt, Ops)) - return 0; - - DenseMap::iterator I = IntervalSSMap.find(vreg); - if (I != IntervalSSMap.end()) { - SS = I->second; - } else { - SS = MFI->CreateSpillStackObject(RC->getSize(), RC->getAlignment()); - } - - MachineInstr* FMI = TII->foldMemoryOperand(FoldPt, Ops, SS); - - if (FMI) { - LIs->ReplaceMachineInstrInMaps(FoldPt, FMI); - FoldPt->eraseFromParent(); - ++NumFolds; - - IntervalSSMap[vreg] = SS; - CurrSLI = &LSs->getOrCreateInterval(SS, RC); - if (CurrSLI->hasAtLeastOneValue()) - CurrSValNo = CurrSLI->getValNumInfo(0); - else - CurrSValNo = CurrSLI->getNextValue(SlotIndex(), 0, - LSs->getVNInfoAllocator()); - } - - return FMI; -} - -MachineInstr* PreAllocSplitting::FoldRestore(unsigned vreg, - const TargetRegisterClass* RC, - MachineInstr* Barrier, - MachineBasicBlock* MBB, - int SS, - SmallPtrSet& RefsInMBB) { - if ((int)RestoreFoldLimit != -1 && RestoreFoldLimit == (int)NumRestoreFolds) - return 0; - - // Go top down if RefsInMBB is empty. - if (RefsInMBB.empty()) - return 0; - - // Can't fold a restore between a call stack setup and teardown. - MachineBasicBlock::iterator FoldPt = Barrier; - - // Advance from barrier to call frame teardown. - while (FoldPt != MBB->getFirstTerminator() && - FoldPt->getOpcode() != TRI->getCallFrameDestroyOpcode()) { - if (RefsInMBB.count(FoldPt)) - return 0; - - ++FoldPt; - } - - if (FoldPt == MBB->getFirstTerminator()) - return 0; - else - ++FoldPt; - - // Now find the restore point. - while (FoldPt != MBB->getFirstTerminator() && !RefsInMBB.count(FoldPt)) { - if (FoldPt->getOpcode() == TRI->getCallFrameSetupOpcode()) { - while (FoldPt != MBB->getFirstTerminator() && - FoldPt->getOpcode() != TRI->getCallFrameDestroyOpcode()) { - if (RefsInMBB.count(FoldPt)) - return 0; - - ++FoldPt; - } - - if (FoldPt == MBB->getFirstTerminator()) - return 0; - } - - ++FoldPt; - } - - if (FoldPt == MBB->getFirstTerminator()) - return 0; - - int OpIdx = FoldPt->findRegisterUseOperandIdx(vreg, true); - if (OpIdx == -1) - return 0; - - SmallVector Ops; - Ops.push_back(OpIdx); - - if (!TII->canFoldMemoryOperand(FoldPt, Ops)) - return 0; - - MachineInstr* FMI = TII->foldMemoryOperand(FoldPt, Ops, SS); - - if (FMI) { - LIs->ReplaceMachineInstrInMaps(FoldPt, FMI); - FoldPt->eraseFromParent(); - ++NumRestoreFolds; - } - - return FMI; -} - -/// SplitRegLiveInterval - Split (spill and restore) the given live interval -/// so it would not cross the barrier that's being processed. Shrink wrap -/// (minimize) the live interval to the last uses. -bool PreAllocSplitting::SplitRegLiveInterval(LiveInterval *LI) { - DEBUG(dbgs() << "Pre-alloc splitting " << LI->reg << " for " << *Barrier - << " result: "); - - CurrLI = LI; - - // Find live range where current interval cross the barrier. - LiveInterval::iterator LR = - CurrLI->FindLiveRangeContaining(BarrierIdx.getUseIndex()); - VNInfo *ValNo = LR->valno; - - assert(!ValNo->isUnused() && "Val# is defined by a dead def?"); - - MachineInstr *DefMI = LIs->getInstructionFromIndex(ValNo->def); - - // If this would create a new join point, do not split. - if (DefMI && createsNewJoin(LR, DefMI->getParent(), Barrier->getParent())) { - DEBUG(dbgs() << "FAILED (would create a new join point).\n"); - return false; - } - - // Find all references in the barrier mbb. - SmallPtrSet RefsInMBB; - for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(CurrLI->reg), - E = MRI->reg_end(); I != E; ++I) { - MachineInstr *RefMI = &*I; - if (RefMI->getParent() == BarrierMBB) - RefsInMBB.insert(RefMI); - } - - // Find a point to restore the value after the barrier. - MachineBasicBlock::iterator RestorePt = - findRestorePoint(BarrierMBB, Barrier, LR->end, RefsInMBB); - if (RestorePt == BarrierMBB->end()) { - DEBUG(dbgs() << "FAILED (could not find a suitable restore point).\n"); - return false; - } - - if (DefMI && LIs->isReMaterializable(*LI, ValNo, DefMI)) - if (Rematerialize(LI->reg, ValNo, DefMI, RestorePt, RefsInMBB)) { - DEBUG(dbgs() << "success (remat).\n"); - return true; - } - - // Add a spill either before the barrier or after the definition. - MachineBasicBlock *DefMBB = DefMI ? DefMI->getParent() : NULL; - const TargetRegisterClass *RC = MRI->getRegClass(CurrLI->reg); - SlotIndex SpillIndex; - MachineInstr *SpillMI = NULL; - int SS = -1; - if (!DefMI) { - // If we don't know where the def is we must split just before the barrier. - if ((SpillMI = FoldSpill(LI->reg, RC, 0, Barrier, - BarrierMBB, SS, RefsInMBB))) { - SpillIndex = LIs->getInstructionIndex(SpillMI); - } else { - MachineBasicBlock::iterator SpillPt = - findSpillPoint(BarrierMBB, Barrier, NULL, RefsInMBB); - if (SpillPt == BarrierMBB->begin()) { - DEBUG(dbgs() << "FAILED (could not find a suitable spill point).\n"); - return false; // No gap to insert spill. - } - // Add spill. - - SS = CreateSpillStackSlot(CurrLI->reg, RC); - TII->storeRegToStackSlot(*BarrierMBB, SpillPt, CurrLI->reg, true, SS, RC, - TRI); - SpillMI = prior(SpillPt); - SpillIndex = LIs->InsertMachineInstrInMaps(SpillMI); - } - } else if (!IsAvailableInStack(DefMBB, CurrLI->reg, ValNo->def, - LIs->getZeroIndex(), SpillIndex, SS)) { - // If it's already split, just restore the value. There is no need to spill - // the def again. - if (!DefMI) { - DEBUG(dbgs() << "FAILED (def is dead).\n"); - return false; // Def is dead. Do nothing. - } - - if ((SpillMI = FoldSpill(LI->reg, RC, DefMI, Barrier, - BarrierMBB, SS, RefsInMBB))) { - SpillIndex = LIs->getInstructionIndex(SpillMI); - } else { - // Check if it's possible to insert a spill after the def MI. - MachineBasicBlock::iterator SpillPt; - if (DefMBB == BarrierMBB) { - // Add spill after the def and the last use before the barrier. - SpillPt = findSpillPoint(BarrierMBB, Barrier, DefMI, - RefsInMBB); - if (SpillPt == DefMBB->begin()) { - DEBUG(dbgs() << "FAILED (could not find a suitable spill point).\n"); - return false; // No gap to insert spill. - } - } else { - SpillPt = llvm::next(MachineBasicBlock::iterator(DefMI)); - if (SpillPt == DefMBB->end()) { - DEBUG(dbgs() << "FAILED (could not find a suitable spill point).\n"); - return false; // No gap to insert spill. - } - } - // Add spill. - SS = CreateSpillStackSlot(CurrLI->reg, RC); - TII->storeRegToStackSlot(*DefMBB, SpillPt, CurrLI->reg, false, SS, RC, - TRI); - SpillMI = prior(SpillPt); - SpillIndex = LIs->InsertMachineInstrInMaps(SpillMI); - } - } - - // Remember def instruction index to spill index mapping. - if (DefMI && SpillMI) - Def2SpillMap[ValNo->def] = SpillIndex; - - // Add restore. - bool FoldedRestore = false; - SlotIndex RestoreIndex; - if (MachineInstr* LMI = FoldRestore(CurrLI->reg, RC, Barrier, - BarrierMBB, SS, RefsInMBB)) { - RestorePt = LMI; - RestoreIndex = LIs->getInstructionIndex(RestorePt); - FoldedRestore = true; - } else { - TII->loadRegFromStackSlot(*BarrierMBB, RestorePt, CurrLI->reg, SS, RC, TRI); - MachineInstr *LoadMI = prior(RestorePt); - RestoreIndex = LIs->InsertMachineInstrInMaps(LoadMI); - } - - // Update spill stack slot live interval. - UpdateSpillSlotInterval(ValNo, SpillIndex.getUseIndex().getNextSlot(), - RestoreIndex.getDefIndex()); - - ReconstructLiveInterval(CurrLI); - - if (!FoldedRestore) { - SlotIndex RestoreIdx = LIs->getInstructionIndex(prior(RestorePt)); - RestoreIdx = RestoreIdx.getDefIndex(); - RenumberValno(CurrLI->findDefinedVNInfoForRegInt(RestoreIdx)); - } - - ++NumSplits; - DEBUG(dbgs() << "success.\n"); - return true; -} - -/// SplitRegLiveIntervals - Split all register live intervals that cross the -/// barrier that's being processed. -bool -PreAllocSplitting::SplitRegLiveIntervals(const TargetRegisterClass **RCs, - SmallPtrSet& Split) { - // First find all the virtual registers whose live intervals are intercepted - // by the current barrier. - SmallVector Intervals; - for (const TargetRegisterClass **RC = RCs; *RC; ++RC) { - // FIXME: If it's not safe to move any instruction that defines the barrier - // register class, then it means there are some special dependencies which - // codegen is not modelling. Ignore these barriers for now. - if (!TII->isSafeToMoveRegClassDefs(*RC)) - continue; - const std::vector &VRs = MRI->getRegClassVirtRegs(*RC); - for (unsigned i = 0, e = VRs.size(); i != e; ++i) { - unsigned Reg = VRs[i]; - if (!LIs->hasInterval(Reg)) - continue; - LiveInterval *LI = &LIs->getInterval(Reg); - if (LI->liveAt(BarrierIdx) && !Barrier->readsRegister(Reg)) - // Virtual register live interval is intercepted by the barrier. We - // should split and shrink wrap its interval if possible. - Intervals.push_back(LI); - } - } - - // Process the affected live intervals. - bool Change = false; - while (!Intervals.empty()) { - if (PreSplitLimit != -1 && (int)NumSplits == PreSplitLimit) - break; - LiveInterval *LI = Intervals.back(); - Intervals.pop_back(); - bool result = SplitRegLiveInterval(LI); - if (result) Split.insert(LI); - Change |= result; - } - - return Change; -} - -unsigned PreAllocSplitting::getNumberOfNonSpills( - SmallPtrSet& MIs, - unsigned Reg, int FrameIndex, - bool& FeedsTwoAddr) { - unsigned NonSpills = 0; - for (SmallPtrSet::iterator UI = MIs.begin(), UE = MIs.end(); - UI != UE; ++UI) { - int StoreFrameIndex; - unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex); - if (StoreVReg != Reg || StoreFrameIndex != FrameIndex) - ++NonSpills; - - int DefIdx = (*UI)->findRegisterDefOperandIdx(Reg); - if (DefIdx != -1 && (*UI)->isRegTiedToUseOperand(DefIdx)) - FeedsTwoAddr = true; - } - - return NonSpills; -} - -/// removeDeadSpills - After doing splitting, filter through all intervals we've -/// split, and see if any of the spills are unnecessary. If so, remove them. -bool PreAllocSplitting::removeDeadSpills(SmallPtrSet& split) { - bool changed = false; - - // Walk over all of the live intervals that were touched by the splitter, - // and see if we can do any DCE and/or folding. - for (SmallPtrSet::iterator LI = split.begin(), - LE = split.end(); LI != LE; ++LI) { - DenseMap > VNUseCount; - - // First, collect all the uses of the vreg, and sort them by their - // reaching definition (VNInfo). - for (MachineRegisterInfo::use_iterator UI = MRI->use_begin((*LI)->reg), - UE = MRI->use_end(); UI != UE; ++UI) { - SlotIndex index = LIs->getInstructionIndex(&*UI); - index = index.getUseIndex(); - - const LiveRange* LR = (*LI)->getLiveRangeContaining(index); - VNUseCount[LR->valno].insert(&*UI); - } - - // Now, take the definitions (VNInfo's) one at a time and try to DCE - // and/or fold them away. - for (LiveInterval::vni_iterator VI = (*LI)->vni_begin(), - VE = (*LI)->vni_end(); VI != VE; ++VI) { - - if (DeadSplitLimit != -1 && (int)NumDeadSpills == DeadSplitLimit) - return changed; - - VNInfo* CurrVN = *VI; - - // We don't currently try to handle definitions with PHI kills, because - // it would involve processing more than one VNInfo at once. - if (CurrVN->hasPHIKill()) continue; - - // We also don't try to handle the results of PHI joins, since there's - // no defining instruction to analyze. - MachineInstr* DefMI = LIs->getInstructionFromIndex(CurrVN->def); - if (!DefMI || CurrVN->isUnused()) continue; - - // We're only interested in eliminating cruft introduced by the splitter, - // is of the form load-use or load-use-store. First, check that the - // definition is a load, and remember what stack slot we loaded it from. - int FrameIndex; - if (!TII->isLoadFromStackSlot(DefMI, FrameIndex)) continue; - - // If the definition has no uses at all, just DCE it. - if (VNUseCount[CurrVN].size() == 0) { - LIs->RemoveMachineInstrFromMaps(DefMI); - (*LI)->removeValNo(CurrVN); - DefMI->eraseFromParent(); - VNUseCount.erase(CurrVN); - ++NumDeadSpills; - changed = true; - continue; - } - - // Second, get the number of non-store uses of the definition, as well as - // a flag indicating whether it feeds into a later two-address definition. - bool FeedsTwoAddr = false; - unsigned NonSpillCount = getNumberOfNonSpills(VNUseCount[CurrVN], - (*LI)->reg, FrameIndex, - FeedsTwoAddr); - - // If there's one non-store use and it doesn't feed a two-addr, then - // this is a load-use-store case that we can try to fold. - if (NonSpillCount == 1 && !FeedsTwoAddr) { - // Start by finding the non-store use MachineInstr. - SmallPtrSet::iterator UI = VNUseCount[CurrVN].begin(); - int StoreFrameIndex; - unsigned StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex); - while (UI != VNUseCount[CurrVN].end() && - (StoreVReg == (*LI)->reg && StoreFrameIndex == FrameIndex)) { - ++UI; - if (UI != VNUseCount[CurrVN].end()) - StoreVReg = TII->isStoreToStackSlot(*UI, StoreFrameIndex); - } - if (UI == VNUseCount[CurrVN].end()) continue; - - MachineInstr* use = *UI; - - // Attempt to fold it away! - int OpIdx = use->findRegisterUseOperandIdx((*LI)->reg, false); - if (OpIdx == -1) continue; - SmallVector Ops; - Ops.push_back(OpIdx); - if (!TII->canFoldMemoryOperand(use, Ops)) continue; - - MachineInstr* NewMI = TII->foldMemoryOperand(use, Ops, FrameIndex); - - if (!NewMI) continue; - - // Update relevant analyses. - LIs->RemoveMachineInstrFromMaps(DefMI); - LIs->ReplaceMachineInstrInMaps(use, NewMI); - (*LI)->removeValNo(CurrVN); - - DefMI->eraseFromParent(); - use->eraseFromParent(); - VNUseCount[CurrVN].erase(use); - - // Remove deleted instructions. Note that we need to remove them from - // the VNInfo->use map as well, just to be safe. - for (SmallPtrSet::iterator II = - VNUseCount[CurrVN].begin(), IE = VNUseCount[CurrVN].end(); - II != IE; ++II) { - for (DenseMap >::iterator - VNI = VNUseCount.begin(), VNE = VNUseCount.end(); VNI != VNE; - ++VNI) - if (VNI->first != CurrVN) - VNI->second.erase(*II); - LIs->RemoveMachineInstrFromMaps(*II); - (*II)->eraseFromParent(); - } - - VNUseCount.erase(CurrVN); - - for (DenseMap >::iterator - VI = VNUseCount.begin(), VE = VNUseCount.end(); VI != VE; ++VI) - if (VI->second.erase(use)) - VI->second.insert(NewMI); - - ++NumDeadSpills; - changed = true; - continue; - } - - // If there's more than one non-store instruction, we can't profitably - // fold it, so bail. - if (NonSpillCount) continue; - - // Otherwise, this is a load-store case, so DCE them. - for (SmallPtrSet::iterator UI = - VNUseCount[CurrVN].begin(), UE = VNUseCount[CurrVN].end(); - UI != UE; ++UI) { - LIs->RemoveMachineInstrFromMaps(*UI); - (*UI)->eraseFromParent(); - } - - VNUseCount.erase(CurrVN); - - LIs->RemoveMachineInstrFromMaps(DefMI); - (*LI)->removeValNo(CurrVN); - DefMI->eraseFromParent(); - ++NumDeadSpills; - changed = true; - } - } - - return changed; -} - -bool PreAllocSplitting::createsNewJoin(LiveRange* LR, - MachineBasicBlock* DefMBB, - MachineBasicBlock* BarrierMBB) { - if (DefMBB == BarrierMBB) - return false; - - if (LR->valno->hasPHIKill()) - return false; - - SlotIndex MBBEnd = LIs->getMBBEndIdx(BarrierMBB); - if (LR->end < MBBEnd) - return false; - - MachineLoopInfo& MLI = getAnalysis(); - if (MLI.getLoopFor(DefMBB) != MLI.getLoopFor(BarrierMBB)) - return true; - - MachineDominatorTree& MDT = getAnalysis(); - SmallPtrSet Visited; - typedef std::pair ItPair; - SmallVector Stack; - Stack.push_back(std::make_pair(BarrierMBB, BarrierMBB->succ_begin())); - - while (!Stack.empty()) { - ItPair P = Stack.back(); - Stack.pop_back(); - - MachineBasicBlock* PredMBB = P.first; - MachineBasicBlock::succ_iterator S = P.second; - - if (S == PredMBB->succ_end()) - continue; - else if (Visited.count(*S)) { - Stack.push_back(std::make_pair(PredMBB, ++S)); - continue; - } else - Stack.push_back(std::make_pair(PredMBB, S+1)); - - MachineBasicBlock* MBB = *S; - Visited.insert(MBB); - - if (MBB == BarrierMBB) - return true; - - MachineDomTreeNode* DefMDTN = MDT.getNode(DefMBB); - MachineDomTreeNode* BarrierMDTN = MDT.getNode(BarrierMBB); - MachineDomTreeNode* MDTN = MDT.getNode(MBB)->getIDom(); - while (MDTN) { - if (MDTN == DefMDTN) - return true; - else if (MDTN == BarrierMDTN) - break; - MDTN = MDTN->getIDom(); - } - - MBBEnd = LIs->getMBBEndIdx(MBB); - if (LR->end > MBBEnd) - Stack.push_back(std::make_pair(MBB, MBB->succ_begin())); - } - - return false; -} - - -bool PreAllocSplitting::runOnMachineFunction(MachineFunction &MF) { - CurrMF = &MF; - TM = &MF.getTarget(); - TRI = TM->getRegisterInfo(); - TII = TM->getInstrInfo(); - MFI = MF.getFrameInfo(); - MRI = &MF.getRegInfo(); - SIs = &getAnalysis(); - LIs = &getAnalysis(); - LSs = &getAnalysis(); - VRM = &getAnalysis(); - - bool MadeChange = false; - - // Make sure blocks are numbered in order. - MF.RenumberBlocks(); - - MachineBasicBlock *Entry = MF.begin(); - SmallPtrSet Visited; - - SmallPtrSet Split; - - for (df_ext_iterator > - DFI = df_ext_begin(Entry, Visited), E = df_ext_end(Entry, Visited); - DFI != E; ++DFI) { - BarrierMBB = *DFI; - for (MachineBasicBlock::iterator I = BarrierMBB->begin(), - E = BarrierMBB->end(); I != E; ++I) { - Barrier = &*I; - const TargetRegisterClass **BarrierRCs = - Barrier->getDesc().getRegClassBarriers(); - if (!BarrierRCs) - continue; - BarrierIdx = LIs->getInstructionIndex(Barrier); - MadeChange |= SplitRegLiveIntervals(BarrierRCs, Split); - } - } - - MadeChange |= removeDeadSpills(Split); - - return MadeChange; -} Modified: llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp?rev=133962&r1=133961&r2=133962&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocLinearScan.cpp Mon Jun 27 18:40:45 2011 @@ -58,11 +58,6 @@ cl::init(false), cl::Hidden); static cl::opt -PreSplitIntervals("pre-alloc-split", - cl::desc("Pre-register allocation live interval splitting"), - cl::init(false), cl::Hidden); - -static cl::opt TrivCoalesceEnds("trivial-coalesce-ends", cl::desc("Attempt trivial coalescing of interval ends"), cl::init(false), cl::Hidden); @@ -104,7 +99,6 @@ initializeRegisterCoalescerPass( *PassRegistry::getPassRegistry()); initializeCalculateSpillWeightsPass(*PassRegistry::getPassRegistry()); - initializePreAllocSplittingPass(*PassRegistry::getPassRegistry()); initializeLiveStacksPass(*PassRegistry::getPassRegistry()); initializeMachineDominatorTreePass(*PassRegistry::getPassRegistry()); initializeMachineLoopInfoPass(*PassRegistry::getPassRegistry()); @@ -217,8 +211,6 @@ // to coalescing and which analyses coalescing invalidates. AU.addRequiredTransitive(); AU.addRequired(); - if (PreSplitIntervals) - AU.addRequiredID(PreAllocSplittingID); AU.addRequiredID(LiveStacksID); AU.addPreservedID(LiveStacksID); AU.addRequired(); @@ -401,7 +393,6 @@ INITIALIZE_PASS_DEPENDENCY(LiveIntervals) INITIALIZE_PASS_DEPENDENCY(StrongPHIElimination) INITIALIZE_PASS_DEPENDENCY(CalculateSpillWeights) -INITIALIZE_PASS_DEPENDENCY(PreAllocSplitting) INITIALIZE_PASS_DEPENDENCY(LiveStacks) INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo) INITIALIZE_PASS_DEPENDENCY(VirtRegMap) Removed: llvm/trunk/test/CodeGen/X86/pre-split1.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split1.ll?rev=133961&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pre-split1.ll (original) +++ llvm/trunk/test/CodeGen/X86/pre-split1.ll (removed) @@ -1,24 +0,0 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \ -; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1 -; XFAIL: * - -define void @test(double* %P, i32 %cond) nounwind { -entry: - %0 = load double* %P, align 8 ; [#uses=1] - %1 = fadd double %0, 4.000000e+00 ; [#uses=2] - %2 = icmp eq i32 %cond, 0 ; [#uses=1] - br i1 %2, label %bb1, label %bb - -bb: ; preds = %entry - %3 = fadd double %1, 4.000000e+00 ; [#uses=1] - br label %bb1 - -bb1: ; preds = %bb, %entry - %A.0 = phi double [ %3, %bb ], [ %1, %entry ] ; [#uses=1] - %4 = fmul double %A.0, 4.000000e+00 ; [#uses=1] - %5 = tail call i32 (...)* @bar() nounwind ; [#uses=0] - store double %4, double* %P, align 8 - ret void -} - -declare i32 @bar(...) Removed: llvm/trunk/test/CodeGen/X86/pre-split10.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split10.ll?rev=133961&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pre-split10.ll (original) +++ llvm/trunk/test/CodeGen/X86/pre-split10.ll (removed) @@ -1,51 +0,0 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan - -define i32 @main(i32 %argc, i8** %argv) nounwind { -entry: - br label %bb14.i - -bb14.i: ; preds = %bb14.i, %entry - %i8.0.reg2mem.0.i = phi i32 [ 0, %entry ], [ %0, %bb14.i ] ; [#uses=1] - %0 = add i32 %i8.0.reg2mem.0.i, 1 ; [#uses=2] - %1 = fadd double 0.000000e+00, 0.000000e+00 ; [#uses=1] - %2 = fadd double 0.000000e+00, 0.000000e+00 ; [#uses=1] - %3 = fadd double 0.000000e+00, 0.000000e+00 ; [#uses=1] - %exitcond75.i = icmp eq i32 %0, 32 ; [#uses=1] - br i1 %exitcond75.i, label %bb24.i, label %bb14.i - -bb24.i: ; preds = %bb14.i - %4 = fdiv double 0.000000e+00, 0.000000e+00 ; [#uses=1] - %5 = fdiv double %1, 0.000000e+00 ; [#uses=1] - %6 = fdiv double %2, 0.000000e+00 ; [#uses=1] - %7 = fdiv double %3, 0.000000e+00 ; [#uses=1] - br label %bb31.i - -bb31.i: ; preds = %bb31.i, %bb24.i - %tmp.0.reg2mem.0.i = phi i32 [ 0, %bb24.i ], [ %indvar.next64.i, %bb31.i ] ; [#uses=1] - %indvar.next64.i = add i32 %tmp.0.reg2mem.0.i, 1 ; [#uses=2] - %exitcond65.i = icmp eq i32 %indvar.next64.i, 64 ; [#uses=1] - br i1 %exitcond65.i, label %bb33.i, label %bb31.i - -bb33.i: ; preds = %bb31.i - br label %bb35.preheader.i - -bb5.i.i: ; preds = %bb35.preheader.i - %8 = call double @floor(double 0.000000e+00) nounwind readnone ; [#uses=0] - br label %bb7.i.i - -bb7.i.i: ; preds = %bb35.preheader.i, %bb5.i.i - br label %bb35.preheader.i - -bb35.preheader.i: ; preds = %bb7.i.i, %bb33.i - %9 = fsub double 0.000000e+00, %4 ; [#uses=1] - store double %9, double* null, align 8 - %10 = fsub double 0.000000e+00, %5 ; [#uses=1] - store double %10, double* null, align 8 - %11 = fsub double 0.000000e+00, %6 ; [#uses=1] - store double %11, double* null, align 8 - %12 = fsub double 0.000000e+00, %7 ; [#uses=1] - store double %12, double* null, align 8 - br i1 false, label %bb7.i.i, label %bb5.i.i -} - -declare double @floor(double) nounwind readnone Removed: llvm/trunk/test/CodeGen/X86/pre-split11.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split11.ll?rev=133961&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pre-split11.ll (original) +++ llvm/trunk/test/CodeGen/X86/pre-split11.ll (removed) @@ -1,34 +0,0 @@ -; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+sse2 -pre-alloc-split -regalloc=linearscan | FileCheck %s - - at .str = private constant [28 x i8] c"\0A\0ADOUBLE D = %f\0A\00", align 1 ; <[28 x i8]*> [#uses=1] - at .str1 = private constant [37 x i8] c"double to long l1 = %ld\09\09(0x%lx)\0A\00", align 8 ; <[37 x i8]*> [#uses=1] - at .str2 = private constant [35 x i8] c"double to uint ui1 = %u\09\09(0x%x)\0A\00", align 8 ; <[35 x i8]*> [#uses=1] - at .str3 = private constant [37 x i8] c"double to ulong ul1 = %lu\09\09(0x%lx)\0A\00", align 8 ; <[37 x i8]*> [#uses=1] - -define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp { -; CHECK: movsd %xmm0, (%rsp) -entry: - %0 = icmp sgt i32 %argc, 4 ; [#uses=1] - br i1 %0, label %bb, label %bb2 - -bb: ; preds = %entry - %1 = getelementptr inbounds i8** %argv, i64 4 ; [#uses=1] - %2 = load i8** %1, align 8 ; [#uses=1] - %3 = tail call double @atof(i8* %2) nounwind ; [#uses=1] - br label %bb2 - -bb2: ; preds = %bb, %entry - %storemerge = phi double [ %3, %bb ], [ 2.000000e+00, %entry ] ; [#uses=4] - %4 = fptoui double %storemerge to i32 ; [#uses=2] - %5 = fptoui double %storemerge to i64 ; [#uses=2] - %6 = fptosi double %storemerge to i64 ; [#uses=2] - %7 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([28 x i8]* @.str, i64 0, i64 0), double %storemerge) nounwind ; [#uses=0] - %8 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([37 x i8]* @.str1, i64 0, i64 0), i64 %6, i64 %6) nounwind ; [#uses=0] - %9 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([35 x i8]* @.str2, i64 0, i64 0), i32 %4, i32 %4) nounwind ; [#uses=0] - %10 = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([37 x i8]* @.str3, i64 0, i64 0), i64 %5, i64 %5) nounwind ; [#uses=0] - ret i32 0 -} - -declare double @atof(i8* nocapture) nounwind readonly - -declare i32 @printf(i8* nocapture, ...) nounwind Removed: llvm/trunk/test/CodeGen/X86/pre-split4.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split4.ll?rev=133961&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pre-split4.ll (original) +++ llvm/trunk/test/CodeGen/X86/pre-split4.ll (removed) @@ -1,26 +0,0 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \ -; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 2 - -define i32 @main(i32 %argc, i8** %argv) nounwind { -entry: - br label %bb - -bb: ; preds = %bb, %entry - %k.0.reg2mem.0 = phi double [ 1.000000e+00, %entry ], [ %6, %bb ] ; [#uses=2] - %Flint.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %5, %bb ] ; [#uses=1] - %twoThrd.0.reg2mem.0 = phi double [ 0.000000e+00, %entry ], [ %1, %bb ] ; [#uses=1] - %0 = tail call double @llvm.pow.f64(double 0x3FE5555555555555, double 0.000000e+00) ; [#uses=1] - %1 = fadd double %0, %twoThrd.0.reg2mem.0 ; [#uses=1] - %2 = tail call double @sin(double %k.0.reg2mem.0) nounwind readonly ; [#uses=1] - %3 = fmul double 0.000000e+00, %2 ; [#uses=1] - %4 = fdiv double 1.000000e+00, %3 ; [#uses=1] - store double %Flint.0.reg2mem.0, double* null - store double %twoThrd.0.reg2mem.0, double* null - %5 = fadd double %4, %Flint.0.reg2mem.0 ; [#uses=1] - %6 = fadd double %k.0.reg2mem.0, 1.000000e+00 ; [#uses=1] - br label %bb -} - -declare double @llvm.pow.f64(double, double) nounwind readonly - -declare double @sin(double) nounwind readonly Removed: llvm/trunk/test/CodeGen/X86/pre-split5.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split5.ll?rev=133961&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pre-split5.ll (original) +++ llvm/trunk/test/CodeGen/X86/pre-split5.ll (removed) @@ -1,56 +0,0 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan - -target triple = "i386-apple-darwin9.5" - %struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 } - %struct.__sFILEX = type opaque - %struct.__sbuf = type { i8*, i32 } -@"\01LC1" = external constant [48 x i8] ; <[48 x i8]*> [#uses=1] - -define i32 @main() nounwind { -entry: - br label %bb5.us - -bb5.us: ; preds = %bb8.split, %bb5.us, %entry - %i.0.reg2mem.0.ph = phi i32 [ 0, %entry ], [ %indvar.next53, %bb8.split ], [ %i.0.reg2mem.0.ph, %bb5.us ] ; [#uses=2] - %j.0.reg2mem.0.us = phi i32 [ %indvar.next47, %bb5.us ], [ 0, %bb8.split ], [ 0, %entry ] ; [#uses=1] - %indvar.next47 = add i32 %j.0.reg2mem.0.us, 1 ; [#uses=2] - %exitcond48 = icmp eq i32 %indvar.next47, 256 ; [#uses=1] - br i1 %exitcond48, label %bb8.split, label %bb5.us - -bb8.split: ; preds = %bb5.us - %indvar.next53 = add i32 %i.0.reg2mem.0.ph, 1 ; [#uses=2] - %exitcond54 = icmp eq i32 %indvar.next53, 256 ; [#uses=1] - br i1 %exitcond54, label %bb11, label %bb5.us - -bb11: ; preds = %bb11, %bb8.split - %i.1.reg2mem.0 = phi i32 [ %indvar.next44, %bb11 ], [ 0, %bb8.split ] ; [#uses=1] - %indvar.next44 = add i32 %i.1.reg2mem.0, 1 ; [#uses=2] - %exitcond45 = icmp eq i32 %indvar.next44, 63 ; [#uses=1] - br i1 %exitcond45, label %bb14, label %bb11 - -bb14: ; preds = %bb14, %bb11 - %indvar = phi i32 [ %indvar.next40, %bb14 ], [ 0, %bb11 ] ; [#uses=1] - %indvar.next40 = add i32 %indvar, 1 ; [#uses=2] - %exitcond41 = icmp eq i32 %indvar.next40, 32768 ; [#uses=1] - br i1 %exitcond41, label %bb28, label %bb14 - -bb28: ; preds = %bb14 - %0 = fdiv double 2.550000e+02, 0.000000e+00 ; [#uses=1] - br label %bb30 - -bb30: ; preds = %bb36, %bb28 - %m.1.reg2mem.0 = phi i32 [ %m.0, %bb36 ], [ 0, %bb28 ] ; [#uses=1] - %1 = fmul double 0.000000e+00, %0 ; [#uses=1] - %2 = fptosi double %1 to i32 ; [#uses=1] - br i1 false, label %bb36, label %bb35 - -bb35: ; preds = %bb30 - %3 = tail call i32 (%struct.FILE*, i8*, ...)* @fprintf(%struct.FILE* null, i8* getelementptr ([48 x i8]* @"\01LC1", i32 0, i32 0), i32 0, i32 0, i32 0, i32 %2) nounwind ; [#uses=0] - br label %bb36 - -bb36: ; preds = %bb35, %bb30 - %m.0 = phi i32 [ 0, %bb35 ], [ %m.1.reg2mem.0, %bb30 ] ; [#uses=1] - br label %bb30 -} - -declare i32 @fprintf(%struct.FILE*, i8*, ...) nounwind Removed: llvm/trunk/test/CodeGen/X86/pre-split6.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split6.ll?rev=133961&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pre-split6.ll (original) +++ llvm/trunk/test/CodeGen/X86/pre-split6.ll (removed) @@ -1,36 +0,0 @@ -; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+sse2 -pre-alloc-split -regalloc=linearscan | grep {divsd 24} | count 1 - - at current_surfaces.b = external global i1 ; [#uses=1] - -declare double @sin(double) nounwind readonly - -declare double @asin(double) nounwind readonly - -define fastcc void @trace_line(i32 %line) nounwind { -entry: - %.b3 = load i1* @current_surfaces.b ; [#uses=1] - br i1 %.b3, label %bb.nph, label %return - -bb.nph: ; preds = %entry - %0 = load double* null, align 8 ; [#uses=1] - %1 = load double* null, align 8 ; [#uses=2] - %2 = fcmp une double %0, 0.000000e+00 ; [#uses=1] - br i1 %2, label %bb9.i, label %bb13.i - -bb9.i: ; preds = %bb.nph - %3 = tail call double @asin(double 0.000000e+00) nounwind readonly ; [#uses=0] - %4 = fdiv double 1.000000e+00, %1 ; [#uses=1] - %5 = fmul double %4, 0.000000e+00 ; [#uses=1] - %6 = tail call double @asin(double %5) nounwind readonly ; [#uses=0] - unreachable - -bb13.i: ; preds = %bb.nph - %7 = fdiv double 1.000000e+00, %1 ; [#uses=1] - %8 = tail call double @sin(double 0.000000e+00) nounwind readonly ; [#uses=1] - %9 = fmul double %7, %8 ; [#uses=1] - %10 = tail call double @asin(double %9) nounwind readonly ; [#uses=0] - unreachable - -return: ; preds = %entry - ret void -} Removed: llvm/trunk/test/CodeGen/X86/pre-split7.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split7.ll?rev=133961&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pre-split7.ll (original) +++ llvm/trunk/test/CodeGen/X86/pre-split7.ll (removed) @@ -1,34 +0,0 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan - - at object_distance = external global double, align 8 ; [#uses=1] - at axis_slope_angle = external global double, align 8 ; [#uses=1] - at current_surfaces.b = external global i1 ; [#uses=1] - -declare double @sin(double) nounwind readonly - -declare double @asin(double) nounwind readonly - -declare double @tan(double) nounwind readonly - -define fastcc void @trace_line(i32 %line) nounwind { -entry: - %.b3 = load i1* @current_surfaces.b ; [#uses=1] - br i1 %.b3, label %bb, label %return - -bb: ; preds = %bb, %entry - %0 = tail call double @asin(double 0.000000e+00) nounwind readonly ; [#uses=1] - %1 = fadd double 0.000000e+00, %0 ; [#uses=2] - %2 = tail call double @asin(double 0.000000e+00) nounwind readonly ; [#uses=1] - %3 = fsub double %1, %2 ; [#uses=2] - store double %3, double* @axis_slope_angle, align 8 - %4 = fdiv double %1, 2.000000e+00 ; [#uses=1] - %5 = tail call double @sin(double %4) nounwind readonly ; [#uses=1] - %6 = fmul double 0.000000e+00, %5 ; [#uses=1] - %7 = tail call double @tan(double %3) nounwind readonly ; [#uses=0] - %8 = fadd double 0.000000e+00, %6 ; [#uses=1] - store double %8, double* @object_distance, align 8 - br label %bb - -return: ; preds = %entry - ret void -} Removed: llvm/trunk/test/CodeGen/X86/pre-split8.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split8.ll?rev=133961&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pre-split8.ll (original) +++ llvm/trunk/test/CodeGen/X86/pre-split8.ll (removed) @@ -1,35 +0,0 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \ -; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1 - - at current_surfaces.b = external global i1 ; [#uses=1] - -declare double @asin(double) nounwind readonly - -declare double @tan(double) nounwind readonly - -define fastcc void @trace_line(i32 %line) nounwind { -entry: - %.b3 = load i1* @current_surfaces.b ; [#uses=1] - br i1 %.b3, label %bb, label %return - -bb: ; preds = %bb9.i, %entry - %.rle4 = phi double [ %7, %bb9.i ], [ 0.000000e+00, %entry ] ; [#uses=1] - %0 = load double* null, align 8 ; [#uses=3] - %1 = fcmp une double %0, 0.000000e+00 ; [#uses=1] - br i1 %1, label %bb9.i, label %bb13.i - -bb9.i: ; preds = %bb - %2 = fsub double %.rle4, %0 ; [#uses=0] - %3 = tail call double @asin(double %.rle4) nounwind readonly ; [#uses=0] - %4 = fmul double 0.000000e+00, %0 ; [#uses=1] - %5 = tail call double @tan(double 0.000000e+00) nounwind readonly ; [#uses=0] - %6 = fmul double %4, 0.000000e+00 ; [#uses=1] - %7 = fadd double %6, 0.000000e+00 ; [#uses=1] - br i1 false, label %return, label %bb - -bb13.i: ; preds = %bb - unreachable - -return: ; preds = %bb9.i, %entry - ret void -} Removed: llvm/trunk/test/CodeGen/X86/pre-split9.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pre-split9.ll?rev=133961&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/pre-split9.ll (original) +++ llvm/trunk/test/CodeGen/X86/pre-split9.ll (removed) @@ -1,38 +0,0 @@ -; RUN: llc < %s -march=x86 -mattr=+sse2 -pre-alloc-split -regalloc=linearscan -stats |& \ -; RUN: grep {pre-alloc-split} | grep {Number of intervals split} | grep 1 - - at current_surfaces.b = external global i1 ; [#uses=1] - -declare double @sin(double) nounwind readonly - -declare double @asin(double) nounwind readonly - -declare double @tan(double) nounwind readonly - -define fastcc void @trace_line(i32 %line) nounwind { -entry: - %.b3 = load i1* @current_surfaces.b ; [#uses=1] - br i1 %.b3, label %bb, label %return - -bb: ; preds = %bb9.i, %entry - %.rle4 = phi double [ %8, %bb9.i ], [ 0.000000e+00, %entry ] ; [#uses=1] - %0 = load double* null, align 8 ; [#uses=3] - %1 = fcmp une double %0, 0.000000e+00 ; [#uses=1] - br i1 %1, label %bb9.i, label %bb13.i - -bb9.i: ; preds = %bb - %2 = fsub double %.rle4, %0 ; [#uses=0] - %3 = tail call double @asin(double %.rle4) nounwind readonly ; [#uses=0] - %4 = tail call double @sin(double 0.000000e+00) nounwind readonly ; [#uses=1] - %5 = fmul double %4, %0 ; [#uses=1] - %6 = tail call double @tan(double 0.000000e+00) nounwind readonly ; [#uses=0] - %7 = fmul double %5, 0.000000e+00 ; [#uses=1] - %8 = fadd double %7, 0.000000e+00 ; [#uses=1] - br i1 false, label %return, label %bb - -bb13.i: ; preds = %bb - unreachable - -return: ; preds = %bb9.i, %entry - ret void -} From evan.cheng at apple.com Mon Jun 27 18:47:21 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 27 Jun 2011 23:47:21 -0000 Subject: [llvm-commits] [llvm] r133964 - in /llvm/trunk: include/llvm/Target/TargetInstrDesc.h utils/TableGen/InstrInfoEmitter.cpp utils/TableGen/InstrInfoEmitter.h Message-ID: <20110627234721.990172A6C12C@llvm.org> Author: evancheng Date: Mon Jun 27 18:47:21 2011 New Revision: 133964 URL: http://llvm.org/viewvc/llvm-project?rev=133964&view=rev Log: Remove RCBarriers from TargetInstrDesc. Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp llvm/trunk/utils/TableGen/InstrInfoEmitter.h Modified: llvm/trunk/include/llvm/Target/TargetInstrDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=133964&r1=133963&r2=133964&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h Mon Jun 27 18:47:21 2011 @@ -130,7 +130,6 @@ uint64_t TSFlags; // Target Specific Flag values const unsigned *ImplicitUses; // Registers implicitly read by this instr const unsigned *ImplicitDefs; // Registers implicitly defined by this instr - const TargetRegisterClass **RCBarriers; // Reg classes completely "clobbered" const TargetOperandInfo *OpInfo; // 'NumOperands' entries about operands /// getOperandConstraint - Returns the value of the specific constraint if @@ -251,17 +250,6 @@ return false; } - /// getRegClassBarriers - Return a list of register classes that are - /// completely clobbered by this machine instruction. For example, on X86 - /// the call instructions will completely clobber all the registers in the - /// fp stack and XMM classes. - /// - /// This method returns null if the instruction doesn't completely clobber - /// any register class. - const TargetRegisterClass **getRegClassBarriers() const { - return RCBarriers; - } - /// getSchedClass - Return the scheduling class for this instruction. The /// scheduling class is an index into the InstrItineraryData table. This /// returns zero if there is no known scheduling information for the Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=133964&r1=133963&r2=133964&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Mon Jun 27 18:47:21 2011 @@ -27,14 +27,6 @@ OS << "0 };\n"; } -static void PrintBarriers(std::vector &Barriers, - unsigned Num, raw_ostream &OS) { - OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { "; - for (unsigned i = 0, e = Barriers.size(); i != e; ++i) - OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, "; - OS << "NULL };\n"; -} - //===----------------------------------------------------------------------===// // Instruction Itinerary Information. //===----------------------------------------------------------------------===// @@ -158,33 +150,6 @@ } } -void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector &Defs, - const std::vector &RCs, - std::vector &Barriers) { - std::set DefSet; - unsigned NumDefs = Defs.size(); - for (unsigned i = 0; i < NumDefs; ++i) - DefSet.insert(Defs[i]); - - for (unsigned i = 0, e = RCs.size(); i != e; ++i) { - const CodeGenRegisterClass &RC = RCs[i]; - ArrayRef Order = RC.getOrder(); - if (Order.size() > NumDefs) - continue; // Can't possibly clobber this RC. - - bool Clobber = true; - for (unsigned j = 0; j < Order.size(); ++j) { - Record *Reg = Order[j]; - if (!DefSet.count(Reg)) { - Clobber = false; - break; - } - } - if (Clobber) - Barriers.push_back(RC.TheDef); - } -} - //===----------------------------------------------------------------------===// // Main Output. //===----------------------------------------------------------------------===// @@ -199,14 +164,10 @@ CodeGenTarget &Target = CDP.getTargetInfo(); const std::string &TargetName = Target.getName(); Record *InstrInfo = Target.getInstructionSet(); - const std::vector &RCs = Target.getRegisterClasses(); // Keep track of all of the def lists we have emitted already. std::map, unsigned> EmittedLists; unsigned ListNumber = 0; - std::map, unsigned> EmittedBarriers; - unsigned BarrierNumber = 0; - std::map BarriersMap; // Emit all of the instruction's implicit uses and defs. for (CodeGenTarget::inst_iterator II = Target.inst_begin(), @@ -219,14 +180,6 @@ } std::vector Defs = Inst->getValueAsListOfDefs("Defs"); if (!Defs.empty()) { - std::vector RCBarriers; - DetectRegisterClassBarriers(Defs, RCs, RCBarriers); - if (!RCBarriers.empty()) { - unsigned &IB = EmittedBarriers[RCBarriers]; - if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS); - BarriersMap.insert(std::make_pair(Inst, IB)); - } - unsigned &IL = EmittedLists[Defs]; if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); } @@ -246,7 +199,7 @@ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, - BarriersMap, OperandInfoIDs, OS); + OperandInfoIDs, OS); OS << "};\n"; OS << "} // End llvm namespace \n"; } @@ -254,7 +207,6 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map, unsigned> &EmittedLists, - std::map &BarriersMap, const OperandInfoMapTy &OpInfo, raw_ostream &OS) { int MinOperands = 0; @@ -322,12 +274,6 @@ else OS << "ImplicitList" << EmittedLists[DefList] << ", "; - std::map::iterator BI = BarriersMap.find(Inst.TheDef); - if (BI == BarriersMap.end()) - OS << "NULL, "; - else - OS << "Barriers" << BI->second << ", "; - // Emit the operand info. std::vector OperandInfo = GetOperandInfo(Inst); if (OperandInfo.empty()) Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.h?rev=133964&r1=133963&r2=133964&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.h (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.h Mon Jun 27 18:47:21 2011 @@ -44,7 +44,6 @@ void emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map, unsigned> &EL, - std::map &BM, const OperandInfoMapTy &OpInfo, raw_ostream &OS); From sabre at nondot.org Mon Jun 27 18:52:55 2011 From: sabre at nondot.org (Chris Lattner) Date: Mon, 27 Jun 2011 16:52:55 -0700 Subject: [llvm-commits] [PATCH]: ppc32 va_arg() implementation In-Reply-To: <20110627170007.GA93136@freebsd.org> References: <20110614194727.GA84755@freebsd.org> <20110627170007.GA93136@freebsd.org> Message-ID: <849D311C-3603-4FA1-83CD-221B9C115B8A@nondot.org> On Jun 27, 2011, at 10:00 AM, Roman Divacky wrote: > Now with a test case, the testcase tests i32 (uses gpr_index). > f32 (uses fpr_index) and i64 (uses aligned gpr_index). I'm really not the best person to review this, but I don't have any objections to it. -Chris > > OK to commit? > > On Tue, Jun 14, 2011 at 09:47:27PM +0200, Roman Divacky wrote: >> Hi, >> >> the attached patch implements va_arg() lowering on ppc32. >> Ints (8, 16, 32 and also 64 bits that need special treatment) work, >> floats don't work (neither with gcc - we should warn when someone tries >> to use them on ppc32 probably), doubles do work. Both passing via >> register_save_area and overflow_area works. >> >> I tried with stuff like >> >> foo(1, 7, 0xf00ba4cafeLL, 3.0f, 2, 4, 5, (6LL << 32) + 5LL, 7, 8, 9, 10, 11, 0); >> bar(1, 1.0, 2.0, 3.0, 4.0, 5.0, 6.0, 7.0, 8.0, 9.0, 10.0, 11.0, 0.0); >> >> I'll have some test cases soon too. >> >> This only works at -O0 because of unrelated bugs in the PowerPC backend. >> >> Comments? >> >> roman > > >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > From grosbach at apple.com Mon Jun 27 18:54:07 2011 From: grosbach at apple.com (Jim Grosbach) Date: Mon, 27 Jun 2011 23:54:07 -0000 Subject: [llvm-commits] [llvm] r133966 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp test/MC/ARM/thumb2.s utils/TableGen/EDEmitter.cpp Message-ID: <20110627235407.141DC2A6C12C@llvm.org> Author: grosbach Date: Mon Jun 27 18:54:06 2011 New Revision: 133966 URL: http://llvm.org/viewvc/llvm-project?rev=133966&view=rev Log: ARM Assembly support for Thumb mov-immediate. Correctly parse the forms of the Thumb mov-immediate instruction: 1. 8-bit immediate 0-255. 2. 12-bit shifted-immediate. The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic, but is not yet supported. More parser logic necessary there due to fixups. Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp llvm/trunk/test/MC/ARM/thumb2.s llvm/trunk/utils/TableGen/EDEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=133966&r1=133965&r2=133966&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Mon Jun 27 18:54:06 2011 @@ -34,9 +34,10 @@ return (uint32_t)-N->getZExtValue() < 8; }], imm_neg_XFORM>; -def imm0_255 : ImmLeaf= 0 && Imm < 256; -}]>; +def imm0_255_asmoperand : AsmOperandClass { let Name = "Imm0_255"; } +def imm0_255 : Operand, ImmLeaf= 0 && Imm < 256; }]> { + let ParserMatchClass = imm0_255_asmoperand; +} def imm0_255_comp : PatLeaf<(i32 imm), [{ return ~((uint32_t)N->getZExtValue()) < 256; }]>; @@ -1072,7 +1073,7 @@ // Move register let isMoveImm = 1 in -def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi, +def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, "mov", "\t$Rd, $imm8", [(set tGPR:$Rd, imm0_255:$imm8)]>, T1General<{1,0,0,?,?}> { Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=133966&r1=133965&r2=133966&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Jun 27 18:54:06 2011 @@ -44,9 +44,11 @@ // t2_so_imm - Match a 32-bit immediate operand, which is an // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit // immediate splatted into multiple bytes of the word. +def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; } def t2_so_imm : Operand, ImmLeaf { + let ParserMatchClass = t2_so_imm_asmoperand; let EncoderMethod = "getT2SOImmOpValue"; } @@ -1645,6 +1647,10 @@ let Inst{15} = 0; } +def : InstAlias<"mov${s}${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, + pred:$p, cc_out:$s)>, + Requires<[IsThumb2]>; + let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins i32imm_hilo16:$imm), IIC_iMOVi, "movw", "\t$Rd, $imm", @@ -2709,6 +2715,8 @@ let Inst{7-4} = 0b0000; } +// FIXME: Pseudo-ize these. For now, just mark codegen only. +let isCodeGenOnly = 1 in { let isMoveImm = 1 in def t2MOVCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm), IIC_iCMOVi, "mov", ".w\t$Rd, $imm", @@ -2789,6 +2797,7 @@ IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>, RegConstraint<"$false = $Rd">; } // neverHasSideEffects +} // isCodeGenOnly = 1 //===----------------------------------------------------------------------===// // Atomic operations intrinsics Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=133966&r1=133965&r2=133966&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Mon Jun 27 18:54:06 2011 @@ -350,6 +350,22 @@ bool isCondCode() const { return Kind == CondCode; } bool isCCOut() const { return Kind == CCOut; } bool isImm() const { return Kind == Immediate; } + bool isImm0_255() const { + if (Kind != Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return Value >= 0 && Value < 256; + } + bool isT2SOImm() const { + if (Kind != Immediate) + return false; + const MCConstantExpr *CE = dyn_cast(getImm()); + if (!CE) return false; + int64_t Value = CE->getValue(); + return ARM_AM::getT2SOImmVal(Value) != -1; + } bool isReg() const { return Kind == Register; } bool isRegList() const { return Kind == RegisterList; } bool isDPRRegList() const { return Kind == DPRRegisterList; } @@ -515,6 +531,16 @@ addExpr(Inst, getImm()); } + void addImm0_255Operands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); + } + + void addT2SOImmOperands(MCInst &Inst, unsigned N) const { + assert(N == 1 && "Invalid number of operands!"); + addExpr(Inst, getImm()); + } + void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const { assert(N == 1 && "Invalid number of operands!"); Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt()))); Modified: llvm/trunk/test/MC/ARM/thumb2.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2.s?rev=133966&r1=133965&r2=133966&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/thumb2.s (original) +++ llvm/trunk/test/MC/ARM/thumb2.s Mon Jun 27 18:54:06 2011 @@ -49,6 +49,22 @@ @ CHECK: mov.w r0, #66846720 @ encoding: [0x7f,0x70,0x4f,0xf0] mov.w r0, #66846720 +@ Aliases w/ the vanilla 'mov' mnemonic, and explicit alternative selection. + mov r2, #0xbf000000 + mov r1, #0x100 + mov r3, #32 + mov.w r3, #32 + movw r3, #32 + +@ CHECK: mov.w r2, #3204448256 @ encoding: [0x4f,0xf0,0x3f,0x42] +@ CHECK: mov.w r1, #256 @ encoding: [0x4f,0xf4,0x80,0x71] +@ CHECK: mov r3, #32 @ encoding: [0x20,0x23] +@ CHECK: mov.w r3, #32 @ encoding: [0x4f,0xf0,0x20,0x03] +@ CHECK: movw r3, #32 @ encoding: [0x40,0xf2,0x20,0x03] + + + + @ CHECK: rrx r0, r0 @ encoding: [0x30,0x00,0x4f,0xea] rrx r0, r0 Modified: llvm/trunk/utils/TableGen/EDEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/EDEmitter.cpp?rev=133966&r1=133965&r2=133966&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/EDEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/EDEmitter.cpp Mon Jun 27 18:54:06 2011 @@ -588,6 +588,7 @@ IMM("imm0_31"); IMM("imm0_31_m1"); IMM("nModImm"); + IMM("imm0_255"); IMM("imm0_4095"); IMM("jt2block_operand"); IMM("t_imm_s4"); From evan.cheng at apple.com Mon Jun 27 18:54:40 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Mon, 27 Jun 2011 23:54:40 -0000 Subject: [llvm-commits] [llvm] r133967 - in /llvm/trunk: include/llvm/CodeGen/MachineRegisterInfo.h lib/CodeGen/MachineRegisterInfo.cpp Message-ID: <20110627235440.4C6CB2A6C12C@llvm.org> Author: evancheng Date: Mon Jun 27 18:54:40 2011 New Revision: 133967 URL: http://llvm.org/viewvc/llvm-project?rev=133967&view=rev Log: Remove RegClass2VRegMap from MachineRegisterInfo. Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Modified: llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h?rev=133967&r1=133966&r2=133967&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineRegisterInfo.h Mon Jun 27 18:54:40 2011 @@ -32,11 +32,6 @@ IndexedMap, VirtReg2IndexFunctor> VRegInfo; - /// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to - /// virtual registers. For each target register class, it keeps a list of - /// virtual registers belonging to the class. - std::vector *RegClass2VRegMap; - /// RegAllocHints - This vector records register allocation hints for virtual /// registers. For each virtual register, it keeps a register and hint type /// pair making up the allocation hint. Hint type is target specific except @@ -216,13 +211,6 @@ /// unsigned getNumVirtRegs() const { return VRegInfo.size(); } - /// getRegClassVirtRegs - Return the list of virtual registers of the given - /// target register class. - const std::vector & - getRegClassVirtRegs(const TargetRegisterClass *RC) const { - return RegClass2VRegMap[RC->getID()]; - } - /// setRegAllocationHint - Specify a register allocation hint for the /// specified virtual register. void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { Modified: llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp?rev=133967&r1=133966&r2=133967&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineRegisterInfo.cpp Mon Jun 27 18:54:40 2011 @@ -20,7 +20,6 @@ MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { VRegInfo.reserve(256); RegAllocHints.reserve(256); - RegClass2VRegMap = new std::vector[TRI.getNumRegClasses()]; UsedPhysRegs.resize(TRI.getNumRegs()); // Create the physreg use/def lists. @@ -38,25 +37,13 @@ "PhysRegUseDefLists has entries after all instructions are deleted"); #endif delete [] PhysRegUseDefLists; - delete [] RegClass2VRegMap; } /// setRegClass - Set the register class of the specified virtual register. /// void MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { - const TargetRegisterClass *OldRC = VRegInfo[Reg].first; VRegInfo[Reg].first = RC; - - // Remove from old register class's vregs list. This may be slow but - // fortunately this operation is rarely needed. - std::vector &VRegs = RegClass2VRegMap[OldRC->getID()]; - std::vector::iterator I = - std::find(VRegs.begin(), VRegs.end(), Reg); - VRegs.erase(I); - - // Add to new register class's vregs list. - RegClass2VRegMap[RC->getID()].push_back(Reg); } const TargetRegisterClass * @@ -95,7 +82,6 @@ if (ArrayBase && &VRegInfo[FirstVirtReg] != ArrayBase) // The vector reallocated, handle this now. HandleVRegListReallocation(); - RegClass2VRegMap[RegClass->getID()].push_back(Reg); return Reg; } From grosbach at apple.com Mon Jun 27 19:19:13 2011 From: grosbach at apple.com (Jim Grosbach) Date: Tue, 28 Jun 2011 00:19:13 -0000 Subject: [llvm-commits] [llvm] r133973 - in /llvm/trunk: lib/Target/ARM/ARMInstrThumb2.td test/MC/ARM/thumb2.s Message-ID: <20110628001913.B4EAF2A6C12C@llvm.org> Author: grosbach Date: Mon Jun 27 19:19:13 2011 New Revision: 133973 URL: http://llvm.org/viewvc/llvm-project?rev=133973&view=rev Log: ARM Thumb2 asm syntax optional destination operand for binary operators. When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: and r1, #ff and r1, r1, #ff rdar://9672867 Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/test/MC/ARM/thumb2.s Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=133973&r1=133972&r2=133973&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Mon Jun 27 19:19:13 2011 @@ -465,7 +465,8 @@ /// changed to modify CPSR. multiclass T2I_bin_irs opcod, string opc, InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, - PatFrag opnode, bit Commutable = 0, string wide = ""> { + PatFrag opnode, string baseOpc, bit Commutable = 0, + string wide = ""> { // shifted imm def ri : T2sTwoRegImm< (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii, @@ -497,14 +498,31 @@ let Inst{26-25} = 0b01; let Inst{24-21} = opcod; } + // Assembly aliases for optional destination operand when it's the same + // as the source operand. + def : InstAlias(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, + t2_so_imm:$imm, pred:$p, + cc_out:$s)>, + Requires<[IsThumb2]>; + def : InstAlias(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, + rGPR:$Rm, pred:$p, + cc_out:$s)>, + Requires<[IsThumb2]>; + def : InstAlias(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn, + t2_so_reg:$shift, pred:$p, + cc_out:$s)>, + Requires<[IsThumb2]>; } /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need -// the ".w" prefix to indicate that they are wide. +// the ".w" suffix to indicate that they are wide. multiclass T2I_bin_w_irs opcod, string opc, InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, - PatFrag opnode, bit Commutable = 0> : - T2I_bin_irs; + PatFrag opnode, string baseOpc, bit Commutable = 0> : + T2I_bin_irs; /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are /// reversed. The 'rr' form is only defined for the disassembler; for codegen @@ -2069,17 +2087,18 @@ defm t2AND : T2I_bin_w_irs<0b0000, "and", IIC_iBITi, IIC_iBITr, IIC_iBITsi, - BinOpFrag<(and node:$LHS, node:$RHS)>, 1>; + BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>; defm t2ORR : T2I_bin_w_irs<0b0010, "orr", IIC_iBITi, IIC_iBITr, IIC_iBITsi, - BinOpFrag<(or node:$LHS, node:$RHS)>, 1>; + BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>; defm t2EOR : T2I_bin_w_irs<0b0100, "eor", IIC_iBITi, IIC_iBITr, IIC_iBITsi, - BinOpFrag<(xor node:$LHS, node:$RHS)>, 1>; + BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>; defm t2BIC : T2I_bin_w_irs<0b0001, "bic", IIC_iBITi, IIC_iBITr, IIC_iBITsi, - BinOpFrag<(and node:$LHS, (not node:$RHS))>>; + BinOpFrag<(and node:$LHS, (not node:$RHS))>, + "t2BIC">; class T2BitFI pattern> @@ -2179,7 +2198,8 @@ defm t2ORN : T2I_bin_irs<0b0011, "orn", IIC_iBITi, IIC_iBITr, IIC_iBITsi, - BinOpFrag<(or node:$LHS, (not node:$RHS))>, 0, "">; + BinOpFrag<(or node:$LHS, (not node:$RHS))>, + "t2ORN", 0, "">; // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version let AddedComplexity = 1 in Modified: llvm/trunk/test/MC/ARM/thumb2.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/ARM/thumb2.s?rev=133973&r1=133972&r2=133973&view=diff ============================================================================== --- llvm/trunk/test/MC/ARM/thumb2.s (original) +++ llvm/trunk/test/MC/ARM/thumb2.s Mon Jun 27 19:19:13 2011 @@ -318,3 +318,23 @@ ldrexd r0, r1, [r0] @ CHECK: ssat16 r0, #7, r0 @ encoding: [0x20,0xf3,0x06,0x00] ssat16 r0, #7, r0 + + and r1, #0xff + and r1, r1, #0xff + orr r1, 0x100 + orr r1, r1, 0x100 + eor r1, 0x100 + eor r1, r1, 0x100 + bic r1, 0x100 + bic r1, r1, 0x100 + +@ CHECK: and r1, r1, #255 @ encoding: [0x01,0xf0,0xff,0x01] +@ CHECK: and r1, r1, #255 @ encoding: [0x01,0xf0,0xff,0x01] +@ CHECK: orr r1, r1, #256 @ encoding: [0x41,0xf4,0x80,0x71] +@ CHECK: orr r1, r1, #256 @ encoding: [0x41,0xf4,0x80,0x71] +@ CHECK: eor r1, r1, #256 @ encoding: [0x81,0xf4,0x80,0x71] +@ CHECK: eor r1, r1, #256 @ encoding: [0x81,0xf4,0x80,0x71] +@ CHECK: bic r1, r1, #256 @ encoding: [0x21,0xf4,0x80,0x71] +@ CHECK: bic r1, r1, #256 @ encoding: [0x21,0xf4,0x80,0x71] + + From aggarwa4 at illinois.edu Mon Jun 27 19:19:33 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 28 Jun 2011 00:19:33 -0000 Subject: [llvm-commits] [poolalloc] r133974 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Message-ID: <20110628001933.33D5B2A6C12C@llvm.org> Author: aggarwa4 Date: Mon Jun 27 19:19:33 2011 New Revision: 133974 URL: http://llvm.org/viewvc/llvm-project?rev=133974&view=rev Log: For the cases of SelectInst/PHINode, where in some cases metadata might be NULL(if value came from SSA variable), set type, to ttype of SSA variable Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=133974&r1=133973&r2=133974&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Mon Jun 27 19:19:33 2011 @@ -69,7 +69,7 @@ void trackInitInst(void *ptr, uint64_t size, uint32_t tag) ; void trackUnInitInst(void *ptr, uint64_t size, uint32_t tag) ; void copyTypeInfo(void *dstptr, void *srcptr, uint64_t size, uint32_t tag) ; - void setTypeInfo(void *dstptr, TypeTagTy *metadata, uint64_t size, uint32_t tag) ; + void setTypeInfo(void *dstptr, TypeTagTy *metadata, uint64_t size, TypeTagTy type, uint32_t tag) ; void setVAInfo(void *va_list, uint64_t totalCount, TypeTagTy *metadata_ptr, uint32_t tag) ; void copyVAInfo(void *va_list_dst, void *va_list_src, uint32_t tag) ; void trackctype(void *ptr, uint32_t tag) ; @@ -225,8 +225,10 @@ */ void checkType(TypeTagTy typeNumber, uint64_t size, TypeTagTy *metadata, void *ptr, uint32_t tag) { - if(metadata == NULL) + if(metadata == NULL) { + assert(ptr == NULL); return; + } /* Check if this an initialized but untyped memory.*/ if (typeNumber != metadata[0]) { if (metadata[0] != 0xFF) { @@ -296,7 +298,11 @@ /** * Copy size bytes of metadata from metadata to dest ptr */ -void setTypeInfo(void *dstptr, TypeTagTy *metadata, uint64_t size, uint32_t tag) { +void setTypeInfo(void *dstptr, TypeTagTy *metadata, uint64_t size, TypeTagTy type, uint32_t tag) { + if(metadata == NULL) { + trackStoreInst(dstptr, type, size, tag); + return; + } uintptr_t d = maskAddress(dstptr); memcpy(&shadow_begin[d], metadata, size); #if DEBUG From aggarwa4 at illinois.edu Mon Jun 27 19:19:55 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 28 Jun 2011 00:19:55 -0000 Subject: [llvm-commits] [poolalloc] r133975 - /poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Message-ID: <20110628001955.9B2572A6C12C@llvm.org> Author: aggarwa4 Date: Mon Jun 27 19:19:55 2011 New Revision: 133975 URL: http://llvm.org/viewvc/llvm-project?rev=133975&view=rev Log: Change prototype, as per last commit. Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=133975&r1=133974&r2=133975&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Mon Jun 27 19:19:55 2011 @@ -112,6 +112,7 @@ VoidPtrTy,/*dest ptr*/ TypeTagPtrTy,/*metadata*/ Int64Ty,/*size*/ + TypeTagTy, Int32Ty,/*tag*/ NULL); trackStringInput = M.getOrInsertFunction("trackStringInput", From aggarwa4 at illinois.edu Mon Jun 27 19:22:03 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 28 Jun 2011 00:22:03 -0000 Subject: [llvm-commits] [poolalloc] r133976 - in /poolalloc/trunk: include/assistDS/TypeChecks.h lib/AssistDS/TypeChecks.cpp Message-ID: <20110628002203.730502A6C12C@llvm.org> Author: aggarwa4 Date: Mon Jun 27 19:22:03 2011 New Revision: 133976 URL: http://llvm.org/viewvc/llvm-project?rev=133976&view=rev Log: 1. Change prototype for setTypeInfo, also, add the correct argument. 2. Add support for some C++ functions, for 471.omnetpp. 3. Use CallSite while handling library functions, useful if called using invoke. 4. Add support for moving checks on PHI to the uses of the PHI value, instead of at the PHI. Modified: poolalloc/trunk/include/assistDS/TypeChecks.h poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/include/assistDS/TypeChecks.h URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=133976&r1=133975&r2=133976&view=diff ============================================================================== --- poolalloc/trunk/include/assistDS/TypeChecks.h (original) +++ poolalloc/trunk/include/assistDS/TypeChecks.h Mon Jun 27 19:22:03 2011 @@ -41,6 +41,9 @@ std::list AddressTakenFunctions; std::set IndCalls; std::map SelectInst_MD_Map; + std::map SelectInst_BasePtr_Map; + std::map PHINode_MD_Map; + std::map PHINode_BasePtr_Map; // Analysis from other passes. TargetData *TD; @@ -70,7 +73,7 @@ bool visitAllocaInst(Module &M, AllocaInst &AI); bool visitVAArgInst(Module &M, VAArgInst &VI); - bool visitUses(Instruction *I, Instruction *AI, CastInst *BCI); + bool visitUses(Instruction *I, Instruction *AI, Instruction *BCI); bool visitGlobal(Module &M, GlobalVariable &GV, Constant *C, Instruction &I, SmallVector); Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=133976&r1=133975&r2=133976&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Mon Jun 27 19:22:03 2011 @@ -399,6 +399,7 @@ VoidPtrTy,/*dest ptr*/ TypeTagPtrTy,/*metadata*/ Int64Ty,/*size*/ + TypeTagTy, Int32Ty,/*tag*/ NULL); copyTypeInfo = M.getOrInsertFunction("copyTypeInfo", @@ -630,9 +631,6 @@ Args.push_back(II->getOperand(i)); } - II->dump(); - errs()<getType()->dump(); // Create the new call InvokeInst *II_New = InvokeInst::Create(NewF, II->getNormalDest(), @@ -1450,12 +1448,12 @@ case Intrinsic::memcpy: case Intrinsic::memmove: { - CastInst *BCI_Src = BitCastInst::CreatePointerCast(I->getOperand(2), VoidPtrTy, "", I); - CastInst *BCI_Dest = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); + CastInst *BCI_Src = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy, "", I); + CastInst *BCI_Dest = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I); std::vector Args; Args.push_back(BCI_Dest); Args.push_back(BCI_Src); - CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(3), Int64Ty, false, "", I); + CastInst *Size = CastInst::CreateIntegerCast(CS.getArgument(2), Int64Ty, false, "", I); Args.push_back(Size); Args.push_back(getTagCounter()); CallInst::Create(copyTypeInfo, Args.begin(), Args.end(), "", I); @@ -1463,17 +1461,46 @@ } case Intrinsic::memset: - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I); std::vector Args; Args.push_back(BCI); - CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(3), Int64Ty, false, "", I); + CastInst *Size = CastInst::CreateIntegerCast(CS.getArgument(2), Int64Ty, false, "", I); Args.push_back(Size); Args.push_back(getTagCounter()); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; } + } else if (F->getNameStr() == std::string("_ZNKSs5c_strEv")) { //c_str + std::vectorArgs; + Args.push_back(I); + Args.push_back(getTagCounter()); + Constant *F = M.getOrInsertFunction("trackgetcwd", VoidTy, VoidPtrTy, Int32Ty, NULL); + CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); + Instruction *InsertPt = I; + if (InvokeInst *II = dyn_cast(InsertPt)) { + InsertPt = II->getNormalDest()->begin(); + while (isa(InsertPt)) + ++InsertPt; + } else + ++InsertPt; + CI->insertBefore(InsertPt); + } else if (F->getNameStr() == std::string("_ZNSsC1EPKcRKSaIcE")) { //c_str() + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I); + std::vectorArgs; + Args.push_back(BCI); + Args.push_back(getTagCounter()); + Constant *F = M.getOrInsertFunction("trackgetcwd", VoidTy, VoidPtrTy, Int32Ty, NULL); + CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); + Instruction *InsertPt = I; + if (InvokeInst *II = dyn_cast(InsertPt)) { + InsertPt = II->getNormalDest()->begin(); + while (isa(InsertPt)) + ++InsertPt; + } else + ++InsertPt; + CI->insertBefore(InsertPt); } else if (F->getNameStr() == std::string("accept")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(2), VoidPtrTy); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy); BCI->insertAfter(I); std::vectorArgs; Args.push_back(BCI); @@ -1482,17 +1509,17 @@ CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); } else if (F->getNameStr() == std::string("poll")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy); BCI->insertAfter(I); std::vectorArgs; Args.push_back(BCI); - Args.push_back(I->getOperand(2)); + Args.push_back(CS.getArgument(1)); Args.push_back(getTagCounter()); Constant *F = M.getOrInsertFunction("trackpoll", VoidTy, VoidPtrTy, Int64Ty, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); } else if (F->getNameStr() == std::string("getaddrinfo")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(4), VoidPtrTy); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(3), VoidPtrTy); BCI->insertAfter(I); std::vectorArgs; Args.push_back(BCI); @@ -1503,7 +1530,7 @@ } else if (F->getNameStr() == std::string("__strdup")) { CastInst *BCI_Dest = BitCastInst::CreatePointerCast(I, VoidPtrTy); BCI_Dest->insertAfter(I); - CastInst *BCI_Src = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy); + CastInst *BCI_Src = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy); BCI_Src->insertAfter(BCI_Dest); std::vector Args; Args.push_back(BCI_Dest); @@ -1515,9 +1542,9 @@ } else if (F->getNameStr() == std::string("gettimeofday") || F->getNameStr() == std::string("time") || F->getNameStr() == std::string("times")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); - assert (isa(I->getOperand(1)->getType())); - const PointerType * PT = cast(I->getOperand(1)->getType()); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I); + assert (isa(CS.getArgument(0)->getType())); + const PointerType * PT = cast(CS.getArgument(0)->getType()); const Type * ET = PT->getElementType(); Value * AllocSize = ConstantInt::get(Int64Ty, TD->getTypeAllocSize(ET)); std::vectorArgs; @@ -1551,7 +1578,7 @@ CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); CI->insertAfter(BCI); } else if (F->getNameStr() == std::string("gethostname")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy); BCI->insertAfter(I); std::vectorArgs; Args.push_back(BCI); @@ -1581,9 +1608,9 @@ F->getNameStr() == std::string("getrlimit") || F->getNameStr() == std::string("stat") || F->getNameStr() == std::string("fstat")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(2), VoidPtrTy, "", I); - assert (isa(I->getOperand(2)->getType())); - const PointerType * PT = cast(I->getOperand(2)->getType()); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy, "", I); + assert (isa(CS.getArgument(1)->getType())); + const PointerType * PT = cast(CS.getArgument(1)->getType()); const Type * ET = PT->getElementType(); Value * AllocSize = ConstantInt::get(Int64Ty, TD->getTypeAllocSize(ET)); std::vectorArgs; @@ -1592,9 +1619,9 @@ Args.push_back(getTagCounter()); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); } else if (F->getNameStr() == std::string("sigaction")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(3), VoidPtrTy, "", I); - assert (isa(I->getOperand(3)->getType())); - const PointerType * PT = cast(I->getOperand(3)->getType()); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(2), VoidPtrTy, "", I); + assert (isa(CS.getArgument(2)->getType())); + const PointerType * PT = cast(CS.getArgument(2)->getType()); const Type * ET = PT->getElementType(); Value * AllocSize = ConstantInt::get(Int64Ty, TD->getTypeAllocSize(ET)); std::vectorArgs; @@ -1629,32 +1656,35 @@ Constant *F = M.getOrInsertFunction("trackctype_32", VoidTy, VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); - } else if (F->getNameStr() == std::string("strcat")) { + } else if (F->getNameStr() == std::string("strcat") || + F->getNameStr() == std::string("_ZNSspLEPKc")) { + CastInst *BCI_Src = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy, "", I); + CastInst *BCI_Dest = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I); std::vector Args; - Args.push_back(I->getOperand(1)); - Args.push_back(I->getOperand(2)); + Args.push_back(BCI_Dest); + Args.push_back(BCI_Src); Args.push_back(getTagCounter()); Constant *F = M.getOrInsertFunction("trackStrcatInst", VoidTy, VoidPtrTy, VoidPtrTy, Int32Ty, NULL); CallInst::Create(F, Args.begin(), Args.end(), "", I); } else if (F->getNameStr() == std::string("strcpy")) { std::vector Args; - Args.push_back(I->getOperand(1)); - Args.push_back(I->getOperand(2)); + Args.push_back(CS.getArgument(0)); + Args.push_back(CS.getArgument(1)); Args.push_back(getTagCounter()); Constant *F = M.getOrInsertFunction("trackStrcpyInst", VoidTy, VoidPtrTy, VoidPtrTy, Int32Ty, NULL); CallInst::Create(F, Args.begin(), Args.end(), "", I); } else if (F->getNameStr() == std::string("strncpy")) { std::vectorArgs; - Args.push_back(I->getOperand(1)); - Args.push_back(I->getOperand(2)); - Args.push_back(I->getOperand(3)); + Args.push_back(CS.getArgument(0)); + Args.push_back(CS.getArgument(1)); + Args.push_back(CS.getArgument(2)); Args.push_back(getTagCounter()); Constant *F = M.getOrInsertFunction("trackStrncpyInst", VoidTy, VoidPtrTy, VoidPtrTy, I->getOperand(3)->getType(), Int32Ty, NULL); CallInst::Create(F, Args.begin(), Args.end(), "", I); } else if(F->getNameStr() == std::string("ftime") || F->getNameStr() == std::string("gettimeofday")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); - const PointerType *PTy = cast(I->getOperand(1)->getType()); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I); + const PointerType *PTy = cast(CS.getArgument(0)->getType()); const Type * ElementType = PTy->getElementType(); std::vector Args; Args.push_back(BCI); @@ -1663,7 +1693,7 @@ CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; } else if(F->getNameStr() == std::string("read")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(2), VoidPtrTy); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy); BCI->insertAfter(I); std::vector Args; Args.push_back(BCI); @@ -1675,12 +1705,12 @@ CI->insertAfter(BCI); return true; } else if(F->getNameStr() == std::string("fread")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy); BCI->insertAfter(I); std::vector Args; Args.push_back(BCI); CastInst *Elem = CastInst::CreateIntegerCast(I, Int64Ty, false); - BinaryOperator *Size = BinaryOperator::Create(Instruction::Mul, Elem, I->getOperand(2)); + BinaryOperator *Size = BinaryOperator::Create(Instruction::Mul, Elem, CS.getArgument(1)); Elem->insertAfter(I); Size->insertAfter(Elem); Args.push_back(Size); @@ -1693,7 +1723,7 @@ BCI->insertAfter(I); std::vector Args; Args.push_back(BCI); - CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(2), Int64Ty, false, "", I); + CastInst *Size = CastInst::CreateIntegerCast(CS.getArgument(1), Int64Ty, false, "", I); Args.push_back(Size); Args.push_back(getTagCounter()); CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); @@ -1701,37 +1731,37 @@ std::vector Args1; Args1.push_back(BCI); Args1.push_back(Size); - CastInst *Num = CastInst::CreateIntegerCast(I->getOperand(1), Int64Ty, false, "", I); + CastInst *Num = CastInst::CreateIntegerCast(CS.getArgument(0), Int64Ty, false, "", I); Args1.push_back(Num); Args1.push_back(getTagCounter()); CallInst *CI_Arr = CallInst::Create(trackArray, Args1.begin(), Args1.end()); CI_Arr->insertAfter(CI); return true; } else if(F->getNameStr() == std::string("realloc")) { - CastInst *BCI_Src = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy); + CastInst *BCI_Src = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy); CastInst *BCI_Dest = BitCastInst::CreatePointerCast(I, VoidPtrTy); BCI_Src->insertAfter(I); BCI_Dest->insertAfter(BCI_Src); std::vector Args; Args.push_back(BCI_Dest); Args.push_back(BCI_Src); - CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(2), Int64Ty, false, "", I); + CastInst *Size = CastInst::CreateIntegerCast(CS.getArgument(1), Int64Ty, false, "", I); Args.push_back(Size); Args.push_back(getTagCounter()); CallInst *CI = CallInst::Create(copyTypeInfo, Args.begin(), Args.end()); CI->insertAfter(BCI_Dest); return true; } else if(F->getNameStr() == std::string("fgets")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I); std::vector Args; Args.push_back(BCI); - CastInst *Size = CastInst::CreateIntegerCast(I->getOperand(2), Int64Ty, false, "", I); + CastInst *Size = CastInst::CreateIntegerCast(CS.getArgument(1), Int64Ty, false, "", I); Args.push_back(Size); Args.push_back(getTagCounter()); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; } else if(F->getNameStr() == std::string("sprintf")) { - CastInst *BCI = BitCastInst::CreatePointerCast(I->getOperand(1), VoidPtrTy, "", I); + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I); std::vectorArgs; Args.push_back(BCI); CastInst *Size = CastInst::CreateIntegerCast(I, Int64Ty, false); @@ -1748,13 +1778,13 @@ // FIXME: Need to look at the format string and check unsigned i = 3; while(i < I->getNumOperands()) { - visitInputFunctionValue(M, I->getOperand(i), I); + visitInputFunctionValue(M, CS.getArgument(i-1), I); i++; } } else if(F->getNameStr() == std::string("fscanf")) { unsigned i = 3; while(i < I->getNumOperands()) { - visitInputFunctionValue(M, I->getOperand(i), I); + visitInputFunctionValue(M, CS.getArgument(i-1), I); i++; } } @@ -1916,7 +1946,7 @@ // AI - metadata // BCI - ptr // I - instruction whose uses to instrument -bool TypeChecks::visitUses(Instruction *I, Instruction *AI, CastInst *BCI) { +bool TypeChecks::visitUses(Instruction *I, Instruction *AI, Instruction *BCI) { for(Value::use_iterator II = I->use_begin(); II != I->use_end(); ++II) { if(DisablePtrCmpChecks) { if(isa(II)) { @@ -1939,38 +1969,79 @@ Args.push_back(BCI_Dest); Args.push_back(AI); Args.push_back(getSizeConstant(SI->getOperand(0)->getType())); + Args.push_back(getTypeMarkerConstant(SI->getOperand(0)->getType())); Args.push_back(getTagCounter()); // Create the call to the runtime check and place it before the copying store instruction. CallInst::Create(setTypeInfo, Args.begin(), Args.end(), "", SI); } else if(SelectInst *SelI = dyn_cast(II)) { SelectInst *Prev = NULL; + SelectInst *PrevBasePtr = NULL; if(SelectInst_MD_Map.find(SelI) != SelectInst_MD_Map.end()) { Prev = SelectInst_MD_Map[SelI]; + PrevBasePtr = SelectInst_BasePtr_Map[SelI]; } SelectInst *AI_New; + SelectInst *BCI_New; if(SelI->getTrueValue() == I) { if(!Prev) { AI_New = SelectInst::Create(SelI->getCondition(), AI, Constant::getNullValue(AI->getType()), "", SelI); + BCI_New = SelectInst::Create(SelI->getCondition(), BCI, Constant::getNullValue(BCI->getType()), "", SelI); } else { AI_New = SelectInst::Create(SelI->getCondition(), AI, Prev->getFalseValue(), "", SelI); + BCI_New = SelectInst::Create(SelI->getCondition(), BCI, Prev->getFalseValue(), "", SelI); Prev->replaceAllUsesWith(AI_New); + PrevBasePtr->replaceAllUsesWith(BCI_New); } } else { if(!Prev) { AI_New = SelectInst::Create(SelI->getCondition(), Constant::getNullValue(AI->getType()), AI, "", SelI); + BCI_New = SelectInst::Create(SelI->getCondition(), Constant::getNullValue(BCI->getType()), BCI, "", SelI); } else { AI_New = SelectInst::Create(SelI->getCondition(), Prev->getTrueValue(), AI, "", SelI); + BCI_New = SelectInst::Create(SelI->getCondition(), Prev->getTrueValue(), BCI, "", SelI); Prev->replaceAllUsesWith(AI_New); + PrevBasePtr->replaceAllUsesWith(BCI_New); } } SelectInst_MD_Map[SelI] = AI_New; - AI_New->dump(); + SelectInst_BasePtr_Map[SelI] = BCI_New; if(!Prev) - visitUses(SelI, AI_New, BCI); + visitUses(SelI, AI_New, BCI_New); } else if(PHINode *PH = dyn_cast(II)) { - BasicBlock *BB = PH->getIncomingBlock(II); - CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", BB->getTerminator()); + PHINode *Prev = NULL; + PHINode *PrevBasePtr = NULL; + if(PHINode_MD_Map.find(PH) != PHINode_MD_Map.end()) { + Prev = PHINode_MD_Map[PH]; + PrevBasePtr = PHINode_BasePtr_Map[PH]; + } + PHINode *AI_New; + PHINode *BCI_New; + if(!Prev) { + AI_New = PHINode::Create(AI->getType(), PH->getNameStr() + ".md", PH); + BCI_New = PHINode::Create(BCI->getType(), PH->getNameStr() + ".baseptr", PH); + for(unsigned c = 0; c < PH->getNumIncomingValues(); c++) { + if(PH->getIncomingValue(c) == I) { + AI_New->addIncoming(AI, PH->getIncomingBlock(c)); + BCI_New->addIncoming(BCI, PH->getIncomingBlock(c)); + } + else { + AI_New->addIncoming(Constant::getNullValue(AI->getType()), PH->getIncomingBlock(c)); + BCI_New->addIncoming(Constant::getNullValue(BCI->getType()), PH->getIncomingBlock(c)); + } + PHINode_MD_Map[PH] = AI_New; + PHINode_BasePtr_Map[PH] = BCI_New; + } + visitUses(PH, AI_New, BCI_New); + } + else { + for(unsigned c = 0; c < PH->getNumIncomingValues(); c++) { + if(PH->getIncomingValue(c) == I) { + Prev->setIncomingValue(c, AI); + PrevBasePtr->setIncomingValue(c, BCI); + } + } + } } else if(BitCastInst *BI = dyn_cast(II)) { visitUses(BI, AI, BCI); //CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", cast(II.getUse().getUser())); From bob.wilson at apple.com Mon Jun 27 19:35:36 2011 From: bob.wilson at apple.com (Bob Wilson) Date: Tue, 28 Jun 2011 00:35:36 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r133977 - in /llvm-gcc-4.2/trunk/gcc/config: arm/darwin.h darwin.h i386/darwin.h i386/t-darwin rs6000/darwin.h rs6000/t-darwin t-darwin Message-ID: <20110628003537.015C12A6C12C@llvm.org> Author: bwilson Date: Mon Jun 27 19:35:36 2011 New Revision: 133977 URL: http://llvm.org/viewvc/llvm-project?rev=133977&view=rev Log: Do not install or use crt3.o for ARM/Darwin targets. Radar 9385990. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h llvm-gcc-4.2/trunk/gcc/config/darwin.h llvm-gcc-4.2/trunk/gcc/config/i386/darwin.h llvm-gcc-4.2/trunk/gcc/config/i386/t-darwin llvm-gcc-4.2/trunk/gcc/config/rs6000/darwin.h llvm-gcc-4.2/trunk/gcc/config/rs6000/t-darwin llvm-gcc-4.2/trunk/gcc/config/t-darwin Modified: llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h?rev=133977&r1=133976&r2=133977&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/darwin.h Mon Jun 27 19:35:36 2011 @@ -256,6 +256,11 @@ #define DARWIN_DEFAULT_VERSION_TYPE DARWIN_VERSION_IPHONEOS #endif +/* APPLE LOCAL begin use crt3.o for x86 and ppc only 9385990 */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC DARWIN_STARTFILE_SPEC +/* APPLE LOCAL end use crt3.o for x86 and ppc only 9385990 */ + #define DARWIN_IPHONEOS_LIBGCC_SPEC "-lgcc_s.1 -lgcc" #undef SUBTARGET_EXTRA_SPECS Modified: llvm-gcc-4.2/trunk/gcc/config/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/darwin.h?rev=133977&r1=133976&r2=133977&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/darwin.h Mon Jun 27 19:35:36 2011 @@ -525,8 +525,7 @@ powerpc program built. */ /* APPLE LOCAL begin mainline */ -#undef STARTFILE_SPEC -#define STARTFILE_SPEC \ +#define DARWIN_STARTFILE_SPEC \ "%{Zdynamiclib: %(darwin_dylib1) } \ "/* APPLE LOCAL link optimizations 6499452 */" \ %{!Zdynamiclib:%{Zbundle:%{!static: %(darwin_bundle1)}} \ @@ -538,10 +537,7 @@ %{!static:%{object:-lcrt0.o} \ %{!object:%{preload:-lcrt0.o} \ %{!preload: %(darwin_crt1) \ - %(darwin_crt2)}}}}}} \ - %{shared-libgcc: \ - %{!miphoneos-version-min=*: \ - %:version-compare(< 10.5 mmacosx-version-min= crt3.o%s)}}" + %(darwin_crt2)}}}}}}" /* APPLE LOCAL end mainline */ /* The native Darwin linker doesn't necessarily place files in the order Modified: llvm-gcc-4.2/trunk/gcc/config/i386/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/darwin.h?rev=133977&r1=133976&r2=133977&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/darwin.h Mon Jun 27 19:35:36 2011 @@ -141,6 +141,14 @@ /* APPLE LOCAL ARM 5681645 8307333 */ #define DARWIN_IPHONEOS_LIBGCC_SPEC "-lgcc" +/* APPLE LOCAL begin use crt3.o for x86 and ppc only 9385990 */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC DARWIN_STARTFILE_SPEC \ + "%{shared-libgcc: \ + %{!miphoneos-version-min=*: \ + %:version-compare(< 10.5 mmacosx-version-min= crt3.o%s)}}" +/* APPLE LOCAL end use crt3.o for x86 and ppc only 9385990 */ + /* APPLE LOCAL begin link optimizations 6499452 */ #undef DARWIN_CRT1_SPEC #define DARWIN_CRT1_SPEC \ Modified: llvm-gcc-4.2/trunk/gcc/config/i386/t-darwin URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/t-darwin?rev=133977&r1=133976&r2=133977&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/t-darwin (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/t-darwin Mon Jun 27 19:35:36 2011 @@ -20,3 +20,6 @@ TARGET_LIBGCC2_CFLAGS = -fPIC -pipe TARGET_LIBGCC2_STATIC_CFLAGS = -mmacosx-version-min=10.4 # APPLE LOCAL end gcov 5573505 + +# APPLE LOCAL use crt3.o for x86 and ppc only 9385990 +EXTRA_MULTILIB_PARTS=crt3.o Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/darwin.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/darwin.h?rev=133977&r1=133976&r2=133977&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/darwin.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/darwin.h Mon Jun 27 19:35:36 2011 @@ -137,6 +137,14 @@ mcpu=G5:ppc970; \ :ppc}}" +/* APPLE LOCAL begin use crt3.o for x86 and ppc only 9385990 */ +#undef STARTFILE_SPEC +#define STARTFILE_SPEC DARWIN_STARTFILE_SPEC \ + "%{shared-libgcc: \ + %{!miphoneos-version-min=*: \ + %:version-compare(< 10.5 mmacosx-version-min= crt3.o%s)}}" +/* APPLE LOCAL end use crt3.o for x86 and ppc only 9385990 */ + /* crt2.o is at least partially required for 10.3.x and earlier. */ /* APPLE LOCAL begin ARM 5683689 */ #define DARWIN_CRT2_SPEC \ Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/t-darwin URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/t-darwin?rev=133977&r1=133976&r2=133977&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/t-darwin (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/t-darwin Mon Jun 27 19:35:36 2011 @@ -25,6 +25,9 @@ TARGET_LIBGCC2_STATIC_CFLAGS = -mmacosx-version-min=10.4 # APPLE LOCAL end gcov 5573505 +# APPLE LOCAL use crt3.o for x86 and ppc only 9385990 +EXTRA_MULTILIB_PARTS=crt3.o + # APPLE LOCAL 5901604 6499452 # LLVM LOCAL begin 8260893 MULTILIB_EXTRA_OPTS = isysroot/Developer/SDKs/MacOSX10.5.sdk mmacosx-version-min=10.5 Modified: llvm-gcc-4.2/trunk/gcc/config/t-darwin URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/t-darwin?rev=133977&r1=133976&r2=133977&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/t-darwin (original) +++ llvm-gcc-4.2/trunk/gcc/config/t-darwin Mon Jun 27 19:35:36 2011 @@ -30,7 +30,6 @@ # APPLE LOCAL begin 4505290 # How to build crt3.o -EXTRA_MULTILIB_PARTS=crt3.o # Pass -fno-tree-dominator-opts to work around bug 26840. $(T)crt3$(objext): $(srcdir)/config/darwin-crt3.c $(GCC_PASSES) \ $(TCONFIG_H) stmp-int-hdrs tsystem.h From mcrosier at apple.com Mon Jun 27 20:04:49 2011 From: mcrosier at apple.com (Chad Rosier) Date: Mon, 27 Jun 2011 18:04:49 -0700 Subject: [llvm-commits] [llvm] r133516 - /llvm/trunk/tools/lto/LTOModule.cpp In-Reply-To: <20110621153624.604CB2A6C12C@llvm.org> References: <20110621153624.604CB2A6C12C@llvm.org> Message-ID: <141A5CD5-572F-4857-956A-6A1DB0208E46@apple.com> Hi Jay, This was causing link-time failures in the llvm test-suite when run with -flto, so I reverted in r133995. I didn't see any obvious reason for this to be causing a problem, so I filed PR10210 in bugzilla to try and track the problem. If you have a second to check this out it would be greatly appreciated. Regards, Chad On Jun 21, 2011, at 8:36 AM, Jay Foad wrote: > Author: foad > Date: Tue Jun 21 10:36:24 2011 > New Revision: 133516 > > URL: http://llvm.org/viewvc/llvm-project?rev=133516&view=rev > Log: > Remove some unnecessary uses of c_str(). > > Modified: > llvm/trunk/tools/lto/LTOModule.cpp > > Modified: llvm/trunk/tools/lto/LTOModule.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=133516&r1=133515&r2=133516&view=diff > ============================================================================== > --- llvm/trunk/tools/lto/LTOModule.cpp (original) > +++ llvm/trunk/tools/lto/LTOModule.cpp Tue Jun 21 10:36:24 2011 > @@ -208,7 +208,7 @@ > if (objcClassNameFromExpression(c->getOperand(1), superclassName)) { > NameAndAttributes info; > StringMap::value_type &entry = > - _undefines.GetOrCreateValue(superclassName.c_str()); > + _undefines.GetOrCreateValue(superclassName); > if (!entry.getValue().name) { > const char *symbolName = entry.getKey().data(); > info.name = symbolName; > @@ -220,7 +220,7 @@ > std::string className; > if (objcClassNameFromExpression(c->getOperand(2), className)) { > StringSet::value_type &entry = > - _defines.GetOrCreateValue(className.c_str()); > + _defines.GetOrCreateValue(className); > entry.setValue(1); > NameAndAttributes info; > info.name = entry.getKey().data(); > @@ -243,7 +243,7 @@ > NameAndAttributes info; > > StringMap::value_type &entry = > - _undefines.GetOrCreateValue(targetclassName.c_str()); > + _undefines.GetOrCreateValue(targetclassName); > > if (entry.getValue().name) > return; > @@ -264,7 +264,7 @@ > NameAndAttributes info; > > StringMap::value_type &entry = > - _undefines.GetOrCreateValue(targetclassName.c_str()); > + _undefines.GetOrCreateValue(targetclassName); > if (entry.getValue().name) > return; > > @@ -375,7 +375,7 @@ > > // add to table of symbols > NameAndAttributes info; > - StringSet::value_type &entry = _defines.GetOrCreateValue(Buffer.c_str()); > + StringSet::value_type &entry = _defines.GetOrCreateValue(Buffer); > entry.setValue(1); > > StringRef Name = entry.getKey(); > @@ -436,7 +436,7 @@ > mangler.getNameWithPrefix(name, decl, false); > > StringMap::value_type &entry = > - _undefines.GetOrCreateValue(name.c_str()); > + _undefines.GetOrCreateValue(name); > > // we already have the symbol > if (entry.getValue().name) > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Mon Jun 27 20:18:58 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 28 Jun 2011 01:18:58 -0000 Subject: [llvm-commits] [llvm] r133978 - /llvm/trunk/lib/CodeGen/SplitKit.cpp Message-ID: <20110628011858.BD37D2A6C12C@llvm.org> Author: stoklund Date: Mon Jun 27 20:18:58 2011 New Revision: 133978 URL: http://llvm.org/viewvc/llvm-project?rev=133978&view=rev Log: Fix a bad iterator dereference that Evan uncovered. Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=133978&r1=133977&r2=133978&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Mon Jun 27 20:18:58 2011 @@ -76,12 +76,14 @@ return LSP.first; // There may not be a call instruction (?) in which case we ignore LPad. LSP.second = LSP.first; - for (MachineBasicBlock::const_iterator I = FirstTerm, E = MBB->begin(); - I != E; --I) + for (MachineBasicBlock::const_iterator I = MBB->end(), E = MBB->begin(); + I != E;) { + --I; if (I->getDesc().isCall()) { LSP.second = LIS.getInstructionIndex(I); break; } + } } // If CurLI is live into a landing pad successor, move the last split point From evan.cheng at apple.com Mon Jun 27 20:36:01 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 28 Jun 2011 01:36:01 -0000 Subject: [llvm-commits] [llvm] r133979 - /llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Message-ID: <20110628013601.D53412A6C12C@llvm.org> Author: evancheng Date: Mon Jun 27 20:36:01 2011 New Revision: 133979 URL: http://llvm.org/viewvc/llvm-project?rev=133979&view=rev Log: Alternative name enum should go into the enum portion. Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=133979&r1=133978&r2=133979&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Mon Jun 27 20:36:01 2011 @@ -57,7 +57,8 @@ Target.getRegisterClasses(); if (!RegisterClasses.empty()) { OS << "\n// Register classes\n"; - OS << "namespace " << RegisterClasses[0].Namespace << " {\n"; + if (!Namespace.empty()) + OS << "namespace " << Namespace << " {\n"; OS << "enum {\n"; for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { if (i) OS << ",\n"; @@ -65,9 +66,27 @@ OS << " = " << i; } OS << "\n };\n"; - OS << "}\n"; + if (!Namespace.empty()) + OS << "}\n"; + } + + const std::vector RegAltNameIndices = Target.getRegAltNameIndices(); + // If the only definition is the default NoRegAltName, we don't need to + // emit anything. + if (RegAltNameIndices.size() > 1) { + OS << "\n// Register alternate name indices\n"; + if (!Namespace.empty()) + OS << "namespace " << Namespace << " {\n"; + OS << "enum {\n"; + for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) + OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; + OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; + OS << "};\n"; + if (!Namespace.empty()) + OS << "}\n"; } + OS << "} // End llvm namespace \n"; OS << "#endif // GET_REGINFO_ENUM\n\n"; } @@ -112,18 +131,6 @@ OS << "0 };\n"; } - const std::vector RegAltNameIndices = Target.getRegAltNameIndices(); - // If the only definition is the default NoRegAltName, we don't need to - // emit anything. - if (RegAltNameIndices.size() > 1) { - OS << "\n// Register alternate name indices\n"; - OS << "enum {\n"; - for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) - OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; - OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; - OS << "};\n"; - } - // Emit the empty sub-registers list OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; // Loop over all of the registers which have sub-registers, emitting the From chandlerc at gmail.com Mon Jun 27 21:03:10 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 28 Jun 2011 02:03:10 -0000 Subject: [llvm-commits] [llvm] r133980 - /llvm/trunk/test/CodeGen/X86/longlong-deadload.ll Message-ID: <20110628020310.5E7312A6C12C@llvm.org> Author: chandlerc Date: Mon Jun 27 21:03:10 2011 New Revision: 133980 URL: http://llvm.org/viewvc/llvm-project?rev=133980&view=rev Log: FileCheck-ize a test that had the strangest TCL quote I've seen yet: an opening single quote with no closing single quote, and with {} quotes "inside" of it. This broke some of our tools that scrape test cases. Also, while here, make the test actually assert what the comment says it asserts. This was essentially authored by Nick Lewycky, and merely typed in by myself. Let me know if this is still missing the mark, but the previous test only succeeded due to the improper quoting preventing *anything* from matching the grep -- it had a '4(%...)' sequence in the output! Modified: llvm/trunk/test/CodeGen/X86/longlong-deadload.ll Modified: llvm/trunk/test/CodeGen/X86/longlong-deadload.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/longlong-deadload.ll?rev=133980&r1=133979&r2=133980&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/longlong-deadload.ll (original) +++ llvm/trunk/test/CodeGen/X86/longlong-deadload.ll Mon Jun 27 21:03:10 2011 @@ -1,8 +1,11 @@ -; RUN: llc < %s -march=x86 | not grep '4{(%...)} +; RUN: llc < %s -march=x86 | FileCheck %s ; This should not load or store the top part of *P. define void @test(i64* %P) nounwind { -entry: +; CHECK: test: +; CHECK: movl 4(%esp), %[[REGISTER:.*]] +; CHECK-NOT: 4(%[[REGISTER]]) +; CHECK: ret %tmp1 = load i64* %P, align 8 ; [#uses=1] %tmp2 = xor i64 %tmp1, 1 ; [#uses=1] store i64 %tmp2, i64* %P, align 8 From chandlerc at gmail.com Mon Jun 27 21:03:12 2011 From: chandlerc at gmail.com (Chandler Carruth) Date: Tue, 28 Jun 2011 02:03:12 -0000 Subject: [llvm-commits] [llvm] r133981 - /llvm/trunk/lib/CodeGen/CMakeLists.txt Message-ID: <20110628020312.D76A42A6C12D@llvm.org> Author: chandlerc Date: Mon Jun 27 21:03:12 2011 New Revision: 133981 URL: http://llvm.org/viewvc/llvm-project?rev=133981&view=rev Log: Fix CMake build by removing this now dead file. Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt Modified: llvm/trunk/lib/CodeGen/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CMakeLists.txt?rev=133981&r1=133980&r2=133981&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/CMakeLists.txt (original) +++ llvm/trunk/lib/CodeGen/CMakeLists.txt Mon Jun 27 21:03:12 2011 @@ -59,7 +59,6 @@ Passes.cpp PeepholeOptimizer.cpp PostRASchedulerList.cpp - PreAllocSplitting.cpp ProcessImplicitDefs.cpp PrologEpilogInserter.cpp PseudoSourceValue.cpp From atrick at apple.com Mon Jun 27 21:49:20 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 28 Jun 2011 02:49:20 -0000 Subject: [llvm-commits] [llvm] r133982 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110628024921.05C6F2A6C12C@llvm.org> Author: atrick Date: Mon Jun 27 21:49:20 2011 New Revision: 133982 URL: http://llvm.org/viewvc/llvm-project?rev=133982&view=rev Log: indvars --disable-iv-rewrite: Defer evaluating s/zext until SCEV evaluates all other IV exprs. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=133982&r1=133981&r2=133982&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Jun 27 21:49:20 2011 @@ -86,21 +86,13 @@ DominatorTree *DT; TargetData *TD; - PHINode *CurrIV; // Current IV being simplified. - - // Instructions processed by SimplifyIVUsers for CurrIV. - SmallPtrSet Simplified; - - // Use-def pairs if IVUsers waiting to be processed for CurrIV. - SmallVector, 8> SimpleIVUsers; - SmallVector DeadInsts; bool Changed; public: static char ID; // Pass identification, replacement for typeid IndVarSimplify() : LoopPass(ID), IU(0), LI(0), SE(0), DT(0), TD(0), - CurrIV(0), Changed(false) { + Changed(false) { initializeIndVarSimplifyPass(*PassRegistry::getPassRegistry()); } @@ -132,7 +124,6 @@ void EliminateIVRemainder(BinaryOperator *Rem, Value *IVOperand, bool IsSigned); - void pushIVUsers(Instruction *Def); bool isSimpleIVUser(Instruction *I, const Loop *L); void RewriteNonIntegerIVs(Loop *L); @@ -1030,7 +1021,10 @@ /// pushIVUsers - Add all uses of Def to the current IV's worklist. /// -void IndVarSimplify::pushIVUsers(Instruction *Def) { +static void pushIVUsers( + Instruction *Def, + SmallPtrSet &Simplified, + SmallVectorImpl< std::pair > &SimpleIVUsers) { for (Value::use_iterator UI = Def->use_begin(), E = Def->use_end(); UI != E; ++UI) { @@ -1079,50 +1073,70 @@ /// Once DisableIVRewrite is default, LSR will be the only client of IVUsers. /// void IndVarSimplify::SimplifyIVUsersNoRewrite(Loop *L, SCEVExpander &Rewriter) { - // Simplification is performed independently for each IV, as represented by a - // loop header phi. Each round of simplification first iterates through the - // SimplifyIVUsers worklist, then determines whether the current IV should be - // widened. Widening adds a new phi to LoopPhis, inducing another round of - // simplification on the wide IV. + std::map WideIVMap; + SmallVector LoopPhis; for (BasicBlock::iterator I = L->getHeader()->begin(); isa(I); ++I) { LoopPhis.push_back(cast(I)); } + // Each round of simplification iterates through the SimplifyIVUsers worklist + // for all current phis, then determines whether any IVs can be + // widened. Widening adds new phis to LoopPhis, inducing another round of + // simplification on the wide IVs. while (!LoopPhis.empty()) { - CurrIV = LoopPhis.pop_back_val(); - Simplified.clear(); - assert(SimpleIVUsers.empty() && "expect empty IV users list"); - - WideIVInfo WI; + // Evaluate as many IV expressions as possible before widening any IVs. This + // forces SCEV to propagate no-wrap flags before evaluating sign/zero + // extension. The first time SCEV attempts to normalize sign/zero extension, + // the result becomes final. So for the most predictable results, we delay + // evaluation of sign/zero extend evaluation until needed, and avoid running + // other SCEV based analysis prior to SimplifyIVUsersNoRewrite. + do { + PHINode *CurrIV = LoopPhis.pop_back_val(); + + // Information about sign/zero extensions of CurrIV. + WideIVInfo WI; + + // Instructions processed by SimplifyIVUsers for CurrIV. + SmallPtrSet Simplified; + + // Use-def pairs if IVUsers waiting to be processed for CurrIV. + SmallVector, 8> SimpleIVUsers; + + pushIVUsers(CurrIV, Simplified, SimpleIVUsers); + + while (!SimpleIVUsers.empty()) { + Instruction *UseInst, *Operand; + tie(UseInst, Operand) = SimpleIVUsers.pop_back_val(); - pushIVUsers(CurrIV); - - while (!SimpleIVUsers.empty()) { - Instruction *UseInst, *Operand; - tie(UseInst, Operand) = SimpleIVUsers.pop_back_val(); - - if (EliminateIVUser(UseInst, Operand)) { - pushIVUsers(Operand); - continue; - } - if (CastInst *Cast = dyn_cast(UseInst)) { - bool IsSigned = Cast->getOpcode() == Instruction::SExt; - if (IsSigned || Cast->getOpcode() == Instruction::ZExt) { - CollectExtend(Cast, IsSigned, WI, SE, TD); + if (EliminateIVUser(UseInst, Operand)) { + pushIVUsers(Operand, Simplified, SimpleIVUsers); + continue; + } + if (CastInst *Cast = dyn_cast(UseInst)) { + bool IsSigned = Cast->getOpcode() == Instruction::SExt; + if (IsSigned || Cast->getOpcode() == Instruction::ZExt) { + CollectExtend(Cast, IsSigned, WI, SE, TD); + } + continue; + } + if (isSimpleIVUser(UseInst, L)) { + pushIVUsers(UseInst, Simplified, SimpleIVUsers); } - continue; } - if (isSimpleIVUser(UseInst, L)) { - pushIVUsers(UseInst); + if (WI.WidestNativeType) { + WideIVMap[CurrIV] = WI; } - } - if (WI.WidestNativeType) { - WidenIV Widener(CurrIV, WI, LI, SE, DT, DeadInsts); + } while(!LoopPhis.empty()); + + for (std::map::const_iterator I = WideIVMap.begin(), + E = WideIVMap.end(); I != E; ++I) { + WidenIV Widener(I->first, I->second, LI, SE, DT, DeadInsts); if (PHINode *WidePhi = Widener.CreateWideIV(Rewriter)) { Changed = true; LoopPhis.push_back(WidePhi); } } + WideIVMap.clear(); } } @@ -1145,8 +1159,6 @@ DT = &getAnalysis(); TD = getAnalysisIfAvailable(); - CurrIV = NULL; - Simplified.clear(); DeadInsts.clear(); Changed = false; @@ -1160,6 +1172,11 @@ SCEVExpander Rewriter(*SE); // Eliminate redundant IV users. + // + // Simplification works best when run before other consumers of SCEV. We + // attempt to avoid evaluating SCEVs for sign/zero extend operations until + // other expressions involving loop IVs have been evaluated. This helps SCEV + // propagate no-wrap flags before normalizing sign/zero extension. if (DisableIVRewrite) { Rewriter.disableCanonicalMode(); SimplifyIVUsersNoRewrite(L, Rewriter); From atrick at apple.com Mon Jun 27 22:01:46 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 28 Jun 2011 03:01:46 -0000 Subject: [llvm-commits] [llvm] r133988 - in /llvm/trunk/lib: Analysis/IVUsers.cpp Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110628030146.D7E042A6C12C@llvm.org> Author: atrick Date: Mon Jun 27 22:01:46 2011 New Revision: 133988 URL: http://llvm.org/viewvc/llvm-project?rev=133988&view=rev Log: indvars --disable-iv-rewrite: sever ties with IVUsers. Modified: llvm/trunk/lib/Analysis/IVUsers.cpp llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Analysis/IVUsers.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IVUsers.cpp?rev=133988&r1=133987&r2=133988&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/IVUsers.cpp (original) +++ llvm/trunk/lib/Analysis/IVUsers.cpp Mon Jun 27 22:01:46 2011 @@ -21,7 +21,6 @@ #include "llvm/Analysis/Dominators.h" #include "llvm/Analysis/LoopPass.h" #include "llvm/Analysis/ScalarEvolutionExpressions.h" -#include "llvm/Support/CommandLine.h" #include "llvm/Target/TargetData.h" #include "llvm/Assembly/Writer.h" #include "llvm/ADT/STLExtras.h" @@ -39,15 +38,6 @@ INITIALIZE_PASS_END(IVUsers, "iv-users", "Induction Variable Users", false, true) -// IVUsers behavior currently depends on this temporary indvars mode. The -// option must be defined upstream from its uses. -namespace llvm { - bool DisableIVRewrite = false; -} -cl::opt DisableIVRewriteOpt( - "disable-iv-rewrite", cl::Hidden, cl::location(llvm::DisableIVRewrite), - cl::desc("Disable canonical induction variable rewriting")); - Pass *llvm::createIVUsersPass() { return new IVUsers(); } @@ -100,11 +90,6 @@ if (Width > 64 || (TD && !TD->isLegalInteger(Width))) return false; - // We expect Sign/Zero extension to be eliminated from the IR before analyzing - // any downstream uses. - if (DisableIVRewrite && (isa(I) || isa(I))) - return false; - if (!Processed.insert(I)) return true; // Instruction already handled. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=133988&r1=133987&r2=133988&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Mon Jun 27 22:01:46 2011 @@ -52,6 +52,7 @@ #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/LoopPass.h" #include "llvm/Support/CFG.h" +#include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Transforms/Utils/Local.h" @@ -72,11 +73,9 @@ STATISTIC(NumElimRem , "Number of IV remainder operations eliminated"); STATISTIC(NumElimCmp , "Number of IV comparisons eliminated"); -// DisableIVRewrite mode currently affects IVUsers, so is defined in libAnalysis -// and referenced here. -namespace llvm { - extern bool DisableIVRewrite; -} +static cl::opt DisableIVRewrite( + "disable-iv-rewrite", cl::Hidden, + cl::desc("Disable canonical induction variable rewriting")); namespace { class IndVarSimplify : public LoopPass { @@ -104,7 +103,8 @@ AU.addRequired(); AU.addRequiredID(LoopSimplifyID); AU.addRequiredID(LCSSAID); - AU.addRequired(); + if (!DisableIVRewrite) + AU.addRequired(); AU.addPreserved(); AU.addPreservedID(LoopSimplifyID); AU.addPreservedID(LCSSAID); From rafael.espindola at gmail.com Mon Jun 27 22:17:04 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Tue, 28 Jun 2011 03:17:04 -0000 Subject: [llvm-commits] [llvm] r133989 - /llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Message-ID: <20110628031704.1EE542A6C12C@llvm.org> Author: rafael Date: Mon Jun 27 22:17:03 2011 New Revision: 133989 URL: http://llvm.org/viewvc/llvm-project?rev=133989&view=rev Log: Fix cmake build. Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/CMakeLists.txt?rev=133989&r1=133988&r2=133989&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Mon Jun 27 22:17:03 2011 @@ -1,6 +1,6 @@ set(LLVM_TARGET_DEFINITIONS MBlaze.td) -tablegen(MBlazeGenRegisterInfo.h.inc -gen-register-info-header) +tablegen(MBlazeGenRegisterInfo.inc -gen-register-info) tablegen(MBlazeGenInstrNames.inc -gen-instr-enums) tablegen(MBlazeGenInstrInfo.inc -gen-instr-desc) tablegen(MBlazeGenCodeEmitter.inc -gen-emitter) From nicholas at mxc.ca Mon Jun 27 22:57:31 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Tue, 28 Jun 2011 03:57:31 -0000 Subject: [llvm-commits] [llvm] r133990 - /llvm/trunk/lib/Transforms/Utils/Local.cpp Message-ID: <20110628035731.EC5522A6C12C@llvm.org> Author: nicholas Date: Mon Jun 27 22:57:31 2011 New Revision: 133990 URL: http://llvm.org/viewvc/llvm-project?rev=133990&view=rev Log: Fix typo in comment. Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=133990&r1=133989&r2=133990&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Mon Jun 27 22:57:31 2011 @@ -642,7 +642,7 @@ bool Changed = false; // This implementation doesn't currently consider undef operands - // specially. Theroetically, two phis which are identical except for + // specially. Theoretically, two phis which are identical except for // one having an undef where the other doesn't could be collapsed. // Map from PHI hash values to PHI nodes. If multiple PHIs have From nicholas at mxc.ca Mon Jun 27 23:54:27 2011 From: nicholas at mxc.ca (Nick Lewycky) Date: Mon, 27 Jun 2011 21:54:27 -0700 Subject: [llvm-commits] [patch] Enable simplifycfg in bb with only a lifetime intrinsic In-Reply-To: <4E056DCC.3050107@gmail.com> References: <4E056DCC.3050107@gmail.com> Message-ID: <4E095E83.8060503@mxc.ca> Rafael ?vila de Esp?ndola wrote: > I noticed that simplify cfg would fail to simplify bbs like > > bb: > call void @llvm.lifetime.end(i64 -1, i8* %a) nounwind > br label %bb1 > > The attached patch enables that. It can cause a llvm.lifetime.* to be lost, > but if I understand the manual correctly, that is fine: the argument now > has a larger life range. - while (PHINode *PN = dyn_cast(&BB->front())) { - if (Succ->getSinglePredecessor()) { - // BB is the only predecessor of Succ, so Succ will end up with exactly - // the same predecessors BB had. + if (Succ->getSinglePredecessor()) { + // BB is the only predecessor of Succ, so Succ will end up with exactly + // the same predecessors BB had. + + // Copy over any phi, debug or lifetime instruction. + BB->getTerminator()->eraseFromParent(); + while (!BB->empty()) Succ->getInstList().splice(Succ->begin(), BB->getInstList(), BB->begin()); - } else { + } else { + while (PHINode *PN = dyn_cast(&BB->front())) { Wow, I'm impressed with how wrong this loop was. :) I mean, it had correct behaviour, but did N splices when it just needed to splice N items. Anyhow, thanks for fixing it! Is there any reason not to copy the lifetime/debug intrinsics from this block to its successor when the successor has a single predecessor? /// TryToSimplifyUncondBranchFromEmptyBlock - BB is known to contain an /// unconditional branch, and contains no instructions other than PHI nodes, /// potential debug intrinsics and the branch. If possible, eliminate BB by /// rewriting all the predecessors to branch to the successor block and return /// true. If we can't transform, return false. Change "potential debug intrinsics" to "potential side-effect-free intrinsics"? Nick > > Cheers, > Rafael > > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From atrick at apple.com Tue Jun 28 00:04:16 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 28 Jun 2011 05:04:16 -0000 Subject: [llvm-commits] [llvm] r133991 - /llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp Message-ID: <20110628050416.A40902A6C12C@llvm.org> Author: atrick Date: Tue Jun 28 00:04:16 2011 New Revision: 133991 URL: http://llvm.org/viewvc/llvm-project?rev=133991&view=rev Log: whitespace Modified: llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp Modified: llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp?rev=133991&r1=133990&r2=133991&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp Tue Jun 28 00:04:16 2011 @@ -167,7 +167,7 @@ static void deleteIfDeadInstruction(Value *V, ScalarEvolution &SE) { if (Instruction *I = dyn_cast(V)) if (isInstructionTriviallyDead(I)) - deleteDeadInstruction(I, SE); + deleteDeadInstruction(I, SE); } bool LoopIdiomRecognize::runOnLoop(Loop *L, LPPassManager &LPM) { @@ -468,7 +468,7 @@ BasicBlock *Preheader = CurLoop->getLoopPreheader(); IRBuilder<> Builder(Preheader->getTerminator()); SCEVExpander Expander(*SE); - + // Okay, we have a strided store "p[i]" of a splattable value. We can turn // this into a memset in the loop preheader now if we want. However, this // would be unsafe to do if there is anything else in the loop that may read @@ -488,7 +488,7 @@ deleteIfDeadInstruction(BasePtr, *SE); return false; } - + // Okay, everything looks good, insert the memset. // The # stored bytes is (BECount+1)*Size. Expand the trip count out to @@ -557,7 +557,7 @@ BasicBlock *Preheader = CurLoop->getLoopPreheader(); IRBuilder<> Builder(Preheader->getTerminator()); SCEVExpander Expander(*SE); - + // Okay, we have a strided store "p[i]" of a loaded value. We can turn // this into a memcpy in the loop preheader now if we want. However, this // would be unsafe to do if there is anything else in the loop that may read @@ -568,7 +568,7 @@ Expander.expandCodeFor(StoreEv->getStart(), Builder.getInt8PtrTy(SI->getPointerAddressSpace()), Preheader->getTerminator()); - + if (mayLoopAccessLocation(StoreBasePtr, AliasAnalysis::ModRef, CurLoop, BECount, StoreSize, getAnalysis(), SI)) { @@ -593,9 +593,9 @@ deleteIfDeadInstruction(StoreBasePtr, *SE); return false; } - + // Okay, everything is safe, we can transform this! - + // The # stored bytes is (BECount+1)*Size. Expand the trip count out to // pointer size if it isn't already. @@ -619,7 +619,7 @@ DEBUG(dbgs() << " Formed memcpy: " << *NewCall << "\n" << " from load ptr=" << *LoadEv << " at: " << *LI << "\n" << " from store ptr=" << *StoreEv << " at: " << *SI << "\n"); - + // Okay, the memset has been formed. Zap the original store and anything that // feeds into it. From atrick at apple.com Tue Jun 28 00:07:32 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 28 Jun 2011 05:07:32 -0000 Subject: [llvm-commits] [llvm] r133992 - in /llvm/trunk: include/llvm/Analysis/ScalarEvolutionExpander.h lib/Analysis/ScalarEvolutionExpander.cpp lib/Transforms/Scalar/IndVarSimplify.cpp lib/Transforms/Scalar/LoopIdiomRecognize.cpp lib/Transforms/Scalar/LoopStrengthReduce.cpp Message-ID: <20110628050732.710ED2A6C12C@llvm.org> Author: atrick Date: Tue Jun 28 00:07:32 2011 New Revision: 133992 URL: http://llvm.org/viewvc/llvm-project?rev=133992&view=rev Log: SCEVExpander: give new insts a name that identifies the reponsible pass. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h?rev=133992&r1=133991&r2=133992&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h Tue Jun 28 00:07:32 2011 @@ -30,6 +30,10 @@ /// memory. class SCEVExpander : public SCEVVisitor { ScalarEvolution &SE; + + // New instructions receive a name to identifies them with the current pass. + const char* Label; + std::map, AssertingVH > InsertedExpressions; std::set > InsertedValues; @@ -67,8 +71,8 @@ public: /// SCEVExpander - Construct a SCEVExpander in "canonical" mode. - explicit SCEVExpander(ScalarEvolution &se) - : SE(se), IVIncInsertLoop(0), CanonicalMode(true), + explicit SCEVExpander(ScalarEvolution &se, const char *label) + : SE(se), Label(label), IVIncInsertLoop(0), CanonicalMode(true), Builder(se.getContext(), TargetFolder(se.TD)) {} /// clear - Erase the contents of the InsertedExpressions map so that users Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=133992&r1=133991&r2=133992&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Tue Jun 28 00:07:32 2011 @@ -936,7 +936,8 @@ BasicBlock *Header = L->getHeader(); Builder.SetInsertPoint(Header, Header->begin()); pred_iterator HPB = pred_begin(Header), HPE = pred_end(Header); - PHINode *PN = Builder.CreatePHI(ExpandTy, std::distance(HPB, HPE), "lsr.iv"); + PHINode *PN = Builder.CreatePHI(ExpandTy, std::distance(HPB, HPE), + Twine(Label) + ".iv"); rememberInstruction(PN); // Create the step instructions and populate the PHI. @@ -972,8 +973,8 @@ } } else { IncV = isNegative ? - Builder.CreateSub(PN, StepV, "lsr.iv.next") : - Builder.CreateAdd(PN, StepV, "lsr.iv.next"); + Builder.CreateSub(PN, StepV, Twine(Label) + ".iv.next") : + Builder.CreateAdd(PN, StepV, Twine(Label) + ".iv.next"); rememberInstruction(IncV); } PN->addIncoming(IncV, Pred); Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=133992&r1=133991&r2=133992&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Jun 28 00:07:32 2011 @@ -1169,7 +1169,7 @@ const SCEV *BackedgeTakenCount = SE->getBackedgeTakenCount(L); // Create a rewriter object which we'll use to transform the code with. - SCEVExpander Rewriter(*SE); + SCEVExpander Rewriter(*SE, "indvars"); // Eliminate redundant IV users. // Modified: llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp?rev=133992&r1=133991&r2=133992&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopIdiomRecognize.cpp Tue Jun 28 00:07:32 2011 @@ -467,7 +467,7 @@ // header. This allows us to insert code for it in the preheader. BasicBlock *Preheader = CurLoop->getLoopPreheader(); IRBuilder<> Builder(Preheader->getTerminator()); - SCEVExpander Expander(*SE); + SCEVExpander Expander(*SE, "loop-idiom"); // Okay, we have a strided store "p[i]" of a splattable value. We can turn // this into a memset in the loop preheader now if we want. However, this @@ -556,7 +556,7 @@ // header. This allows us to insert code for it in the preheader. BasicBlock *Preheader = CurLoop->getLoopPreheader(); IRBuilder<> Builder(Preheader->getTerminator()); - SCEVExpander Expander(*SE); + SCEVExpander Expander(*SE, "loop-idiom"); // Okay, we have a strided store "p[i]" of a loaded value. We can turn // this into a memcpy in the loop preheader now if we want. However, this Modified: llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp?rev=133992&r1=133991&r2=133992&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/LoopStrengthReduce.cpp Tue Jun 28 00:07:32 2011 @@ -3698,7 +3698,7 @@ // we can remove them after we are done working. SmallVector DeadInsts; - SCEVExpander Rewriter(SE); + SCEVExpander Rewriter(SE, "lsr"); Rewriter.disableCanonicalMode(); Rewriter.setIVIncInsertPos(L, IVIncInsertPos); From atrick at apple.com Tue Jun 28 00:41:52 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 28 Jun 2011 05:41:52 -0000 Subject: [llvm-commits] [llvm] r133995 - /llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Message-ID: <20110628054152.D30A02A6C12C@llvm.org> Author: atrick Date: Tue Jun 28 00:41:52 2011 New Revision: 133995 URL: http://llvm.org/viewvc/llvm-project?rev=133995&view=rev Log: Cleanup. Fix a stupid variable name. Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Modified: llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp?rev=133995&r1=133994&r2=133995&view=diff ============================================================================== --- llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp (original) +++ llvm/trunk/lib/Analysis/ScalarEvolutionExpander.cpp Tue Jun 28 00:41:52 2011 @@ -937,7 +937,7 @@ Builder.SetInsertPoint(Header, Header->begin()); pred_iterator HPB = pred_begin(Header), HPE = pred_end(Header); PHINode *PN = Builder.CreatePHI(ExpandTy, std::distance(HPB, HPE), - Twine(Label) + ".iv"); + Twine(IVName) + ".iv"); rememberInstruction(PN); // Create the step instructions and populate the PHI. @@ -973,8 +973,8 @@ } } else { IncV = isNegative ? - Builder.CreateSub(PN, StepV, Twine(Label) + ".iv.next") : - Builder.CreateAdd(PN, StepV, Twine(Label) + ".iv.next"); + Builder.CreateSub(PN, StepV, Twine(IVName) + ".iv.next") : + Builder.CreateAdd(PN, StepV, Twine(IVName) + ".iv.next"); rememberInstruction(IncV); } PN->addIncoming(IncV, Pred); From atrick at apple.com Tue Jun 28 00:44:06 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 28 Jun 2011 05:44:06 -0000 Subject: [llvm-commits] [llvm] r133996 - /llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h Message-ID: <20110628054406.36FB02A6C12C@llvm.org> Author: atrick Date: Tue Jun 28 00:44:06 2011 New Revision: 133996 URL: http://llvm.org/viewvc/llvm-project?rev=133996&view=rev Log: Cleanup. Fix a stupid variable name. Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h Modified: llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h?rev=133996&r1=133995&r2=133996&view=diff ============================================================================== --- llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h (original) +++ llvm/trunk/include/llvm/Analysis/ScalarEvolutionExpander.h Tue Jun 28 00:44:06 2011 @@ -32,7 +32,7 @@ ScalarEvolution &SE; // New instructions receive a name to identifies them with the current pass. - const char* Label; + const char* IVName; std::map, AssertingVH > InsertedExpressions; @@ -71,8 +71,8 @@ public: /// SCEVExpander - Construct a SCEVExpander in "canonical" mode. - explicit SCEVExpander(ScalarEvolution &se, const char *label) - : SE(se), Label(label), IVIncInsertLoop(0), CanonicalMode(true), + explicit SCEVExpander(ScalarEvolution &se, const char *name) + : SE(se), IVName(name), IVIncInsertLoop(0), CanonicalMode(true), Builder(se.getContext(), TargetFolder(se.TD)) {} /// clear - Erase the contents of the InsertedExpressions map so that users From stoklund at 2pi.dk Tue Jun 28 01:25:03 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 28 Jun 2011 06:25:03 -0000 Subject: [llvm-commits] [llvm] r133997 - in /llvm/trunk/test/CodeGen/X86: fp-stack-ret.ll pr1505b.ll Message-ID: <20110628062503.D8EC12A6C12C@llvm.org> Author: stoklund Date: Tue Jun 28 01:25:03 2011 New Revision: 133997 URL: http://llvm.org/viewvc/llvm-project?rev=133997&view=rev Log: FileCheckize a couple of tests. Also and add a test for popping dead return values and avoid testing the spill precision. Modified: llvm/trunk/test/CodeGen/X86/fp-stack-ret.ll llvm/trunk/test/CodeGen/X86/pr1505b.ll Modified: llvm/trunk/test/CodeGen/X86/fp-stack-ret.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp-stack-ret.ll?rev=133997&r1=133996&r2=133997&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/fp-stack-ret.ll (original) +++ llvm/trunk/test/CodeGen/X86/fp-stack-ret.ll Tue Jun 28 01:25:03 2011 @@ -1,25 +1,40 @@ -; RUN: llc < %s -mtriple=i686-apple-darwin8 -mcpu=yonah -march=x86 > %t -; RUN: grep fldl %t | count 1 -; RUN: not grep xmm %t -; RUN: grep {sub.*esp} %t | count 1 +; RUN: llc < %s -mtriple=i686-apple-darwin8 -mcpu=yonah -march=x86 | FileCheck %s ; These testcases shouldn't require loading into an XMM register then storing ; to memory, then reloading into an FPStack reg. +; CHECK: test1 +; CHECK: fldl +; CHECK-NEXT: ret define double @test1(double *%P) { %A = load double* %P ret double %A } -; fastcc should return a value +; fastcc should return a value +; CHECK: test2 +; CHECK-NOT: xmm +; CHECK: ret define fastcc double @test2(<2 x double> %A) { %B = extractelement <2 x double> %A, i32 0 ret double %B } +; CHECK: test3 +; CHECK: sub{{.*}}%esp +; CHECLK-NOT: xmm define fastcc double @test3(<4 x float> %A) { %B = bitcast <4 x float> %A to <2 x double> %C = call fastcc double @test2(<2 x double> %B) ret double %C } - + +; Clear the stack when not using a return value. +; CHECK: test4 +; CHECK: call +; CHECK: fstp +; CHECK: ret +define void @test4(double *%P) { + %A = call double @test1(double *%P) + ret void +} Modified: llvm/trunk/test/CodeGen/X86/pr1505b.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr1505b.ll?rev=133997&r1=133996&r2=133997&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/pr1505b.ll (original) +++ llvm/trunk/test/CodeGen/X86/pr1505b.ll Tue Jun 28 01:25:03 2011 @@ -1,5 +1,4 @@ -; RUN: llc < %s -mcpu=i486 | grep fstpl | count 5 -; RUN: llc < %s -mcpu=i486 | grep fstps | count 2 +; RUN: llc < %s -mcpu=i486 | FileCheck %s ; PR1505 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64" @@ -30,19 +29,41 @@ declare i32 @__cxa_atexit(void (i8*)*, i8*, i8*) +; CHECK: main define i32 @main() { entry: +; CHECK: flds %tmp6 = volatile load float* @a ; [#uses=1] +; CHECK: fstps (%esp) +; CHECK: tanf %tmp9 = tail call float @tanf( float %tmp6 ) ; [#uses=1] +; Spill returned value: +; CHECK: fstp + +; CHECK: fldl %tmp12 = volatile load double* @b ; [#uses=1] +; CHECK: fstpl (%esp) +; CHECK: tan %tmp13 = tail call double @tan( double %tmp12 ) ; [#uses=1] +; Spill returned value: +; CHECK: fstp %tmp1314 = fptrunc double %tmp13 to float ; [#uses=1] %tmp16 = tail call %"struct.std::basic_ostream >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc( %"struct.std::basic_ostream >"* @_ZSt4cout, i8* getelementptr ([12 x i8]* @.str, i32 0, i32 0) ) ; <%"struct.std::basic_ostream >"*> [#uses=1] %tmp1920 = fpext float %tmp9 to double ; [#uses=1] +; reload: +; CHECK: fld +; CHECK: fstpl +; CHECK: ZNSolsEd %tmp22 = tail call %"struct.std::basic_ostream >"* @_ZNSolsEd( %"struct.std::basic_ostream >"* %tmp16, double %tmp1920 ) ; <%"struct.std::basic_ostream >"*> [#uses=1] %tmp30 = tail call %"struct.std::basic_ostream >"* @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_( %"struct.std::basic_ostream >"* %tmp22 ) ; <%"struct.std::basic_ostream >"*> [#uses=0] +; reload: +; CHECK: fld +; CHECK: fstps +; CHECK: ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc %tmp34 = tail call %"struct.std::basic_ostream >"* @_ZStlsISt11char_traitsIcEERSt13basic_ostreamIcT_ES5_PKc( %"struct.std::basic_ostream >"* @_ZSt4cout, i8* getelementptr ([13 x i8]* @.str1, i32 0, i32 0) ) ; <%"struct.std::basic_ostream >"*> [#uses=1] %tmp3940 = fpext float %tmp1314 to double ; [#uses=1] +; CHECK: fstpl +; CHECK: ZNSolsEd %tmp42 = tail call %"struct.std::basic_ostream >"* @_ZNSolsEd( %"struct.std::basic_ostream >"* %tmp34, double %tmp3940 ) ; <%"struct.std::basic_ostream >"*> [#uses=1] %tmp51 = tail call %"struct.std::basic_ostream >"* @_ZSt4endlIcSt11char_traitsIcEERSt13basic_ostreamIT_T0_ES6_( %"struct.std::basic_ostream >"* %tmp42 ) ; <%"struct.std::basic_ostream >"*> [#uses=0] ret i32 0 From atrick at apple.com Tue Jun 28 01:34:10 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 28 Jun 2011 06:34:10 -0000 Subject: [llvm-commits] [llvm] r133998 - /llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll Message-ID: <20110628063410.94D702A6C12C@llvm.org> Author: atrick Date: Tue Jun 28 01:34:10 2011 New Revision: 133998 URL: http://llvm.org/viewvc/llvm-project?rev=133998&view=rev Log: FileCheckify and prepare for -disable-iv-rewrite. Modified: llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll Modified: llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll?rev=133998&r1=133997&r2=133998&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/ada-loops.ll Tue Jun 28 01:34:10 2011 @@ -1,14 +1,18 @@ -; RUN: opt < %s -indvars -S > %t -; RUN: grep phi %t | count 4 -; RUN: grep {= phi i32} %t | count 4 -; RUN: not grep {sext i} %t -; RUN: not grep {zext i} %t -; RUN: not grep {trunc i} %t -; RUN: not grep {add i8} %t +; RUN: opt < %s -indvars -S | FileCheck %s +; RUN: opt < %s -indvars -disable-iv-rewrite -S | FileCheck %s +; ; PR1301 ; Do a bunch of analysis and prove that the loops can use an i32 trip ; count without casting. +; +; Note that all four functions should actually be converted to +; memset. However, this test case validates indvars behavior. We +; don't check that phis are "folded together" because that is a job +; for loop strength reduction. But indvars must remove sext, zext, +; trunc, and add i8. +; +; CHECK-NOT: {{sext|zext|trunc|add i8}} ; ModuleID = 'ada.bc' target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-n:8:16:32" From jay.foad at gmail.com Tue Jun 28 03:24:19 2011 From: jay.foad at gmail.com (Jay Foad) Date: Tue, 28 Jun 2011 08:24:19 -0000 Subject: [llvm-commits] [llvm] r133999 - in /llvm/trunk: include/llvm/Constants.h lib/VMCore/Constants.cpp tools/lto/LTOModule.cpp Message-ID: <20110628082419.9C1B5312800A@llvm.org> Author: foad Date: Tue Jun 28 03:24:19 2011 New Revision: 133999 URL: http://llvm.org/viewvc/llvm-project?rev=133999&view=rev Log: PR10210: New method ConstantArray::getAsCString(). Use it in LTO to avoid getting embedded trailing null bytes in std::strings. Modified: llvm/trunk/include/llvm/Constants.h llvm/trunk/lib/VMCore/Constants.cpp llvm/trunk/tools/lto/LTOModule.cpp Modified: llvm/trunk/include/llvm/Constants.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=133999&r1=133998&r2=133999&view=diff ============================================================================== --- llvm/trunk/include/llvm/Constants.h (original) +++ llvm/trunk/include/llvm/Constants.h Tue Jun 28 03:24:19 2011 @@ -387,6 +387,12 @@ /// std::string getAsString() const; + /// getAsCString - If this array is isCString(), then this method converts the + /// array (without the trailing null byte) to an std::string and returns it. + /// Otherwise, it asserts out. + /// + std::string getAsCString() const; + /// isNullValue - Return true if this is the value that would be returned by /// getNullValue. This always returns false because zero arrays are always /// created as ConstantAggregateZero objects. Modified: llvm/trunk/lib/VMCore/Constants.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=133999&r1=133998&r2=133999&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/Constants.cpp (original) +++ llvm/trunk/lib/VMCore/Constants.cpp Tue Jun 28 03:24:19 2011 @@ -1011,17 +1011,32 @@ } -/// getAsString - If the sub-element type of this array is i8 -/// then this method converts the array to an std::string and returns it. -/// Otherwise, it asserts out. +/// convertToString - Helper function for getAsString() and getAsCString(). +static std::string convertToString(const User *U, unsigned len) +{ + std::string Result; + Result.reserve(len); + for (unsigned i = 0; i != len; ++i) + Result.push_back((char)cast(U->getOperand(i))->getZExtValue()); + return Result; +} + +/// getAsString - If this array is isString(), then this method converts the +/// array to an std::string and returns it. Otherwise, it asserts out. /// std::string ConstantArray::getAsString() const { assert(isString() && "Not a string!"); - std::string Result; - Result.reserve(getNumOperands()); - for (unsigned i = 0, e = getNumOperands(); i != e; ++i) - Result.push_back((char)cast(getOperand(i))->getZExtValue()); - return Result; + return convertToString(this, getNumOperands()); +} + + +/// getAsCString - If this array is isCString(), then this method converts the +/// array (without the trailing null byte) to an std::string and returns it. +/// Otherwise, it asserts out. +/// +std::string ConstantArray::getAsCString() const { + assert(isCString() && "Not a string!"); + return convertToString(this, getNumOperands() - 1); } Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=133999&r1=133998&r2=133999&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Tue Jun 28 03:24:19 2011 @@ -191,7 +191,7 @@ Constant *cn = gvn->getInitializer(); if (ConstantArray *ca = dyn_cast(cn)) { if (ca->isCString()) { - name = ".objc_class_name_" + ca->getAsString(); + name = ".objc_class_name_" + ca->getAsCString(); return true; } } From aggarwa4 at illinois.edu Tue Jun 28 07:54:19 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 28 Jun 2011 12:54:19 -0000 Subject: [llvm-commits] [poolalloc] r134003 - /poolalloc/trunk/lib/DSA/StdLibPass.cpp Message-ID: <20110628125419.26AA12A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jun 28 07:54:18 2011 New Revision: 134003 URL: http://llvm.org/viewvc/llvm-project?rev=134003&view=rev Log: Add info for the type tracking functions. Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=134003&r1=134002&r2=134003&view=diff ============================================================================== --- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original) +++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Tue Jun 28 07:54:18 2011 @@ -312,23 +312,33 @@ {"pool_syslog", {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, // Type Checks + {"trackArgvType", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackEnvpType", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackGlobal", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"trackLoadInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"checkType", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"getTypeTag", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"trackStoreInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"copyTypeInfo", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"setTypeInfo", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"trackInitInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"trackUnInitInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackArray", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackStoreInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackStringInput", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, - {"trackArgvType", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"compareTypeAndNumber", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"compareVAArgType", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"getTypeTag", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"checkType", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackInitInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackUnInitInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"copyTypeInfo", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"setTypeInfo", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"setVAInfo", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"copyVAInfo", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackctype", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackctype_32", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackStrcpyInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, {"trackStrcnpyInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackStrcatInst", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackgetcwd", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackgetpwuid", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackgethostname", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackgetaddrinfo", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackaccept", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, + {"trackpoll", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}}, #if 0 {"wait", {false, false, false, false, true, false, false, false, false}}, From rafael.espindola at gmail.com Tue Jun 28 08:13:58 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 28 Jun 2011 09:13:58 -0400 Subject: [llvm-commits] [patch] Enable simplifycfg in bb with only a lifetime intrinsic In-Reply-To: <4E095E83.8060503@mxc.ca> References: <4E056DCC.3050107@gmail.com> <4E095E83.8060503@mxc.ca> Message-ID: <4E09D396.5090109@gmail.com> > - while (PHINode *PN = dyn_cast(&BB->front())) { > - if (Succ->getSinglePredecessor()) { > - // BB is the only predecessor of Succ, so Succ will end up with exactly > - // the same predecessors BB had. > + if (Succ->getSinglePredecessor()) { > + // BB is the only predecessor of Succ, so Succ will end up with exactly > + // the same predecessors BB had. > + > + // Copy over any phi, debug or lifetime instruction. > + BB->getTerminator()->eraseFromParent(); > + while (!BB->empty()) > Succ->getInstList().splice(Succ->begin(), > BB->getInstList(), BB->begin()); > - } else { > + } else { > + while (PHINode *PN = dyn_cast(&BB->front())) { > > Wow, I'm impressed with how wrong this loop was. :) I mean, it had > correct behaviour, but did N splices when it just needed to splice N > items. Anyhow, thanks for fixing it! Well, the original patch still had N splices, fixed on this one. > > Is there any reason not to copy the lifetime/debug intrinsics from this > block to its successor when the successor has a single predecessor? > > /// TryToSimplifyUncondBranchFromEmptyBlock - BB is known to contain an > /// unconditional branch, and contains no instructions other than PHI > nodes, > /// potential debug intrinsics and the branch. If possible, eliminate BB by > /// rewriting all the predecessors to branch to the successor block and > return > /// true. If we can't transform, return false. > > Change "potential debug intrinsics" to "potential side-effect-free > intrinsics"? Done. Updated patch attached. > Nick Cheers, Rafael -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: lifetime.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110628/c7383b9e/attachment.pl From rafael.espindola at gmail.com Tue Jun 28 08:19:40 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 28 Jun 2011 09:19:40 -0400 Subject: [llvm-commits] [patch] Enable simplifycfg in bb with only a lifetime intrinsic In-Reply-To: <4E09D396.5090109@gmail.com> References: <4E056DCC.3050107@gmail.com> <4E095E83.8060503@mxc.ca> <4E09D396.5090109@gmail.com> Message-ID: <4E09D4EC.1020908@gmail.com> >Done. Updated patch attached. Correct one now. Cheers, Rafael -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: simplifycfg.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110628/194b867a/attachment.pl From baldrick at free.fr Tue Jun 28 08:37:44 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 28 Jun 2011 13:37:44 -0000 Subject: [llvm-commits] [dragonegg] r134004 - /dragonegg/trunk/src/Convert.cpp Message-ID: <20110628133744.3B8252A6C12C@llvm.org> Author: baldrick Date: Tue Jun 28 08:37:44 2011 New Revision: 134004 URL: http://llvm.org/viewvc/llvm-project?rev=134004&view=rev Log: The definition of TARGET_MEM_REF changed slightly between gcc-4.5 and gcc-4.6. Get it working with gcc-4.6. Modified: dragonegg/trunk/src/Convert.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=134004&r1=134003&r2=134004&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Tue Jun 28 08:37:44 2011 @@ -6026,54 +6026,61 @@ LValue TreeToLLVM::EmitLV_TARGET_MEM_REF(tree exp) { // TODO: Take the address space into account. - // TODO: Improve the alignment estimate. - // The address is &symbol + base + index * step + offset. - struct mem_address addr; - get_address_description (exp, &addr); - - LValue Ref; + Value *Addr; Value *Delta = 0; // Offset from base pointer in units - if (addr.symbol) { - Ref = EmitLV(addr.symbol); - if (addr.base && !integer_zerop (addr.base)) - Delta = EmitRegister(addr.base); +#if (GCC_MINOR > 5) + // Starting with gcc 4.6 the address is base + index * step + index2 + offset. + Addr = EmitRegister(TMR_BASE(exp)); + if (TMR_INDEX2(exp) && !integer_zerop (TMR_INDEX2(exp))) + Delta = EmitRegister(TMR_INDEX2(exp)); +#else + // In gcc 4.5 the address is &symbol + base + index * step + offset. + if (TMR_SYMBOL(exp)) { + Addr = EmitLV(TMR_SYMBOL(exp)).Ptr; + if (TMR_BASE(exp) && !integer_zerop (TMR_BASE(exp))) + Delta = EmitRegister(TMR_BASE(exp)); } else { - assert(addr.base && "TARGET_MEM_REF has neither base nor symbol!"); - Value *Base = EmitRegister(addr.base); + assert(TMR_BASE(exp) && "TARGET_MEM_REF has neither base nor symbol!"); + Addr = EmitRegister(TMR_BASE(exp)); // The type of BASE is sizetype or a pointer type. Convert sizetype to i8*. - // TODO: In mainline BASE always has pointer type. - if (!isa(Base->getType())) - Base = Builder.CreateIntToPtr(Base, GetUnitPointerType(Context)); - Ref = LValue(Base, 1); + if (!isa(Addr->getType())) + Addr = Builder.CreateIntToPtr(Addr, GetUnitPointerType(Context)); } +#endif - if (addr.index) { - Value *Index = EmitRegister(addr.index); - if (addr.step && !integer_onep (addr.step)) - Index = Builder.CreateMul(Index, EmitRegisterConstant(addr.step)); + if (TMR_INDEX(exp)) { + Value *Index = EmitRegister(TMR_INDEX(exp)); + if (TMR_STEP(exp) && !integer_onep (TMR_STEP(exp))) + Index = Builder.CreateMul(Index, EmitRegisterConstant(TMR_STEP(exp))); Delta = Delta ? Builder.CreateAdd(Delta, Index) : Index; } - if (addr.offset && !integer_zerop (addr.offset)) { - Constant *Offset = EmitRegisterConstant(addr.offset); - Delta = Delta ? Builder.CreateAdd(Delta, Offset) : Offset; + if (TMR_OFFSET(exp) && !integer_zerop (TMR_OFFSET(exp))) { + Constant *Off = ConstantInt::get(Context, getIntegerValue(TMR_OFFSET(exp))); + Delta = Delta ? Builder.CreateAdd(Delta, Off) : Off; } if (Delta) { // Advance the base pointer by the given number of units. - Ref.Ptr = Builder.CreateBitCast(Ref.Ptr, GetUnitPointerType(Context)); - Ref.Ptr = POINTER_TYPE_OVERFLOW_UNDEFINED ? - Builder.CreateInBoundsGEP(Ref.Ptr, Delta) - : Builder.CreateGEP(Ref.Ptr, Delta); - Ref.setAlignment(1); // Let the optimizers compute the alignment. + Addr = Builder.CreateBitCast(Addr, GetUnitPointerType(Context)); + Addr = POINTER_TYPE_OVERFLOW_UNDEFINED ? + Builder.CreateInBoundsGEP(Addr, Delta) + : Builder.CreateGEP(Addr, Delta); } // The result can be of a different pointer type even if we didn't advance it. - Ref.Ptr = Builder.CreateBitCast(Ref.Ptr, - ConvertType(TREE_TYPE(exp))->getPointerTo()); + Addr = Builder.CreateBitCast(Addr, + ConvertType(TREE_TYPE(exp))->getPointerTo()); + unsigned Alignment = TYPE_ALIGN(TREE_TYPE (exp)); +#if (GCC_MINOR < 6) + Alignment = get_object_alignment(exp, Alignment, BIGGEST_ALIGNMENT); +#else + Alignment = std::max(Alignment, get_object_alignment(exp, BIGGEST_ALIGNMENT)); +#endif + bool Volatile = TREE_THIS_VOLATILE(exp); - return Ref; + return LValue(Addr, Alignment / 8, Volatile); } Constant *TreeToLLVM::AddressOfLABEL_DECL(tree exp) { From rdivacky at freebsd.org Tue Jun 28 10:30:42 2011 From: rdivacky at freebsd.org (Roman Divacky) Date: Tue, 28 Jun 2011 15:30:42 -0000 Subject: [llvm-commits] [llvm] r134005 - in /llvm/trunk: lib/Target/PowerPC/PPCISelLowering.cpp test/CodeGen/PowerPC/ppc32-vaarg.ll Message-ID: <20110628153042.855482A6C12C@llvm.org> Author: rdivacky Date: Tue Jun 28 10:30:42 2011 New Revision: 134005 URL: http://llvm.org/viewvc/llvm-project?rev=134005&view=rev Log: Implement ISD::VAARG lowering on PPC32. Added: llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=134005&r1=134004&r2=134005&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Tue Jun 28 10:30:42 2011 @@ -215,10 +215,11 @@ setOperationAction(ISD::VASTART , MVT::Other, Custom); // VAARG is custom lowered with the 32-bit SVR4 ABI. - if ( TM.getSubtarget().isSVR4ABI() - && !TM.getSubtarget().isPPC64()) + if (TM.getSubtarget().isSVR4ABI() + && !TM.getSubtarget().isPPC64()) { setOperationAction(ISD::VAARG, MVT::Other, Custom); - else + setOperationAction(ISD::VAARG, MVT::i64, Custom); + } else setOperationAction(ISD::VAARG, MVT::Other, Expand); // Use the default implementation. @@ -1262,9 +1263,110 @@ SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG, const PPCSubtarget &Subtarget) const { + SDNode *Node = Op.getNode(); + EVT VT = Node->getValueType(0); + EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(); + SDValue InChain = Node->getOperand(0); + SDValue VAListPtr = Node->getOperand(1); + const Value *SV = cast(Node->getOperand(2))->getValue(); + DebugLoc dl = Node->getDebugLoc(); + + assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only"); + + // gpr_index + SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, + VAListPtr, MachinePointerInfo(SV), MVT::i8, + false, false, 0); + InChain = GprIndex.getValue(1); + + if (VT == MVT::i64) { + // Check if GprIndex is even + SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex, + DAG.getConstant(1, MVT::i32)); + SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd, + DAG.getConstant(0, MVT::i32), ISD::SETNE); + SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex, + DAG.getConstant(1, MVT::i32)); + // Align GprIndex to be even if it isn't + GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne, + GprIndex); + } + + // fpr index is 1 byte after gpr + SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, + DAG.getConstant(1, MVT::i32)); + + // fpr + SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain, + FprPtr, MachinePointerInfo(SV), MVT::i8, + false, false, 0); + InChain = FprIndex.getValue(1); + + SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, + DAG.getConstant(8, MVT::i32)); + + SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr, + DAG.getConstant(4, MVT::i32)); + + // areas + SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr, + MachinePointerInfo(), false, false, 0); + InChain = OverflowArea.getValue(1); + + SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr, + MachinePointerInfo(), false, false, 0); + InChain = RegSaveArea.getValue(1); + + // select overflow_area if index > 8 + SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex, + DAG.getConstant(8, MVT::i32), ISD::SETLT); + + SDValue Area = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, RegSaveArea, + OverflowArea); + + // adjustment constant gpr_index * 4/8 + SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32, + VT.isInteger() ? GprIndex : FprIndex, + DAG.getConstant(VT.isInteger() ? 4 : 8, + MVT::i32)); + + // OurReg = RegSaveArea + RegConstant + SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea, + RegConstant); + + // Floating types are 32 bytes into RegSaveArea + if (VT.isFloatingPoint()) + OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg, + DAG.getConstant(32, MVT::i32)); + + // increase {f,g}pr_index by 1 (or 2 if VT is i64) + SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32, + VT.isInteger() ? GprIndex : FprIndex, + DAG.getConstant(VT == MVT::i64 ? 2 : 1, + MVT::i32)); + + InChain = DAG.getTruncStore(InChain, dl, IndexPlus1, + VT.isInteger() ? VAListPtr : FprPtr, + MachinePointerInfo(SV), + MVT::i8, false, false, 0); + + // determine if we should load from reg_save_area or overflow_area + SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea); + + // increase overflow_area by 4/8 if gpr/fpr > 8 + SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea, + DAG.getConstant(VT.isInteger() ? 4 : 8, + MVT::i32)); + + OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea, + OverflowAreaPlusN); + + InChain = DAG.getTruncStore(InChain, dl, OverflowArea, + OverflowAreaPtr, + MachinePointerInfo(), + MVT::i32, false, false, 0); - llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!"); - return SDValue(); // Not reached + return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), false, false, 0); } SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, @@ -4429,11 +4531,27 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results, SelectionDAG &DAG) const { + const TargetMachine &TM = getTargetMachine(); DebugLoc dl = N->getDebugLoc(); switch (N->getOpcode()) { default: assert(false && "Do not know how to custom type legalize this operation!"); return; + case ISD::VAARG: { + if (!TM.getSubtarget().isSVR4ABI() + || TM.getSubtarget().isPPC64()) + return; + + EVT VT = N->getValueType(0); + + if (VT == MVT::i64) { + SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget); + + Results.push_back(NewNode); + Results.push_back(NewNode.getValue(1)); + } + return; + } case ISD::FP_ROUND_INREG: { assert(N->getValueType(0) == MVT::ppcf128); assert(N->getOperand(0).getValueType() == MVT::ppcf128); Added: llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll?rev=134005&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll (added) +++ llvm/trunk/test/CodeGen/PowerPC/ppc32-vaarg.ll Tue Jun 28 10:30:42 2011 @@ -0,0 +1,167 @@ +; RUN: llc -O0 < %s | FileCheck %s +;ModuleID = 'test.c' +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32" +target triple = "powerpc-unknown-freebsd9.0" + +%struct.__va_list_tag = type { i8, i8, i16, i8*, i8* } + + at var1 = common global i64 0, align 8 + at var2 = common global double 0.0, align 8 + at var3 = common global i32 0, align 4 + +define void @ppcvaargtest(%struct.__va_list_tag* %ap) nounwind { + entry: + %x = va_arg %struct.__va_list_tag* %ap, i64; Get from r5,r6 +; CHECK: lbz 4, 0(3) +; CHECK-NEXT: lwz 5, 4(3) +; CHECK-NEXT: rlwinm 6, 4, 0, 31, 31 +; CHECK-NEXT: cmplwi 0, 6, 0 +; CHECK-NEXT: addi 6, 4, 1 +; CHECK-NEXT: stw 3, -4(1) +; CHECK-NEXT: stw 6, -8(1) +; CHECK-NEXT: stw 4, -12(1) +; CHECK-NEXT: stw 5, -16(1) +; CHECK-NEXT: bne 0, .LBB0_2 +; CHECK-NEXT: # BB#1: # %entry +; CHECK-NEXT: lwz 3, -12(1) +; CHECK-NEXT: stw 3, -8(1) +; CHECK-NEXT: .LBB0_2: # %entry +; CHECK-NEXT: lwz 3, -8(1) +; CHECK-NEXT: lwz 4, -4(1) +; CHECK-NEXT: lwz 5, 8(4) +; CHECK-NEXT: slwi 6, 3, 2 +; CHECK-NEXT: addi 7, 3, 2 +; CHECK-NEXT: cmpwi 0, 3, 8 +; CHECK-NEXT: lwz 3, -16(1) +; CHECK-NEXT: addi 8, 3, 4 +; CHECK-NEXT: add 5, 5, 6 +; CHECK-NEXT: mfcr 0 # cr0 +; CHECK-NEXT: stw 0, -20(1) +; CHECK-NEXT: stw 5, -24(1) +; CHECK-NEXT: stw 3, -28(1) +; CHECK-NEXT: stw 7, -32(1) +; CHECK-NEXT: stw 8, -36(1) +; CHECK-NEXT: blt 0, .LBB0_4 +; CHECK-NEXT: # BB#3: # %entry +; CHECK-NEXT: lwz 3, -36(1) +; CHECK-NEXT: stw 3, -28(1) +; CHECK-NEXT: .LBB0_4: # %entry +; CHECK-NEXT: lwz 3, -28(1) +; CHECK-NEXT: lwz 4, -32(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stb 4, 0(5) +; CHECK-NEXT: lwz 4, -24(1) +; CHECK-NEXT: lwz 0, -20(1) +; CHECK-NEXT: mtcrf 128, 0 +; CHECK-NEXT: stw 3, -40(1) +; CHECK-NEXT: stw 4, -44(1) +; CHECK-NEXT: blt 0, .LBB0_6 +; CHECK-NEXT: # BB#5: # %entry +; CHECK-NEXT: lwz 3, -16(1) +; CHECK-NEXT: stw 3, -44(1) +; CHECK-NEXT: .LBB0_6: # %entry +; CHECK-NEXT: lwz 3, -44(1) +; CHECK-NEXT: lwz 4, -40(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stw 4, 4(5) + store i64 %x, i64* @var1, align 8 +; CHECK-NEXT: lis 4, var1 at ha +; CHECK-NEXT: lwz 6, 4(3) +; CHECK-NEXT: lwz 3, 0(3) +; CHECK-NEXT: la 7, var1 at l(4) +; CHECK-NEXT: stw 3, var1 at l(4) +; CHECK-NEXT: stw 6, 4(7) + %y = va_arg %struct.__va_list_tag* %ap, double; From f1 +; CHECK-NEXT: lbz 3, 1(5) +; CHECK-NEXT: lwz 4, 4(5) +; CHECK-NEXT: lwz 6, 8(5) +; CHECK-NEXT: slwi 7, 3, 3 +; CHECK-NEXT: add 6, 6, 7 +; CHECK-NEXT: addi 7, 3, 1 +; CHECK-NEXT: cmpwi 0, 3, 8 +; CHECK-NEXT: addi 3, 4, 8 +; CHECK-NEXT: addi 6, 6, 32 +; CHECK-NEXT: mr 8, 4 +; CHECK-NEXT: mfcr 0 # cr0 +; CHECK-NEXT: stw 0, -48(1) +; CHECK-NEXT: stw 4, -52(1) +; CHECK-NEXT: stw 6, -56(1) +; CHECK-NEXT: stw 7, -60(1) +; CHECK-NEXT: stw 3, -64(1) +; CHECK-NEXT: stw 8, -68(1) +; CHECK-NEXT: blt 0, .LBB0_8 +; CHECK-NEXT: # BB#7: # %entry +; CHECK-NEXT: lwz 3, -64(1) +; CHECK-NEXT: stw 3, -68(1) +; CHECK-NEXT: .LBB0_8: # %entry +; CHECK-NEXT: lwz 3, -68(1) +; CHECK-NEXT: lwz 4, -60(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stb 4, 1(5) +; CHECK-NEXT: lwz 4, -56(1) +; CHECK-NEXT: lwz 0, -48(1) +; CHECK-NEXT: mtcrf 128, 0 +; CHECK-NEXT: stw 4, -72(1) +; CHECK-NEXT: stw 3, -76(1) +; CHECK-NEXT: blt 0, .LBB0_10 +; CHECK-NEXT: # BB#9: # %entry +; CHECK-NEXT: lwz 3, -52(1) +; CHECK-NEXT: stw 3, -72(1) +; CHECK-NEXT: .LBB0_10: # %entry +; CHECK-NEXT: lwz 3, -72(1) +; CHECK-NEXT: lwz 4, -76(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stw 4, 4(5) +; CHECK-NEXT: lfd 0, 0(3) + store double %y, double* @var2, align 8 +; CHECK-NEXT: lis 3, var2 at ha +; CHECK-NEXT: stfd 0, var2 at l(3) + %z = va_arg %struct.__va_list_tag* %ap, i32; From r7 +; CHECK-NEXT: lbz 3, 0(5) +; CHECK-NEXT: lwz 4, 4(5) +; CHECK-NEXT: lwz 6, 8(5) +; CHECK-NEXT: slwi 7, 3, 2 +; CHECK-NEXT: addi 8, 3, 1 +; CHECK-NEXT: cmpwi 0, 3, 8 +; CHECK-NEXT: addi 3, 4, 4 +; CHECK-NEXT: add 6, 6, 7 +; CHECK-NEXT: mr 7, 4 +; CHECK-NEXT: stw 6, -80(1) +; CHECK-NEXT: stw 8, -84(1) +; CHECK-NEXT: stw 3, -88(1) +; CHECK-NEXT: stw 4, -92(1) +; CHECK-NEXT: stw 7, -96(1) +; CHECK-NEXT: mfcr 0 # cr0 +; CHECK-NEXT: stw 0, -100(1) +; CHECK-NEXT: blt 0, .LBB0_12 +; CHECK-NEXT: # BB#11: # %entry +; CHECK-NEXT: lwz 3, -88(1) +; CHECK-NEXT: stw 3, -96(1) +; CHECK-NEXT: .LBB0_12: # %entry +; CHECK-NEXT: lwz 3, -96(1) +; CHECK-NEXT: lwz 4, -84(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stb 4, 0(5) +; CHECK-NEXT: lwz 4, -80(1) +; CHECK-NEXT: lwz 0, -100(1) +; CHECK-NEXT: mtcrf 128, 0 +; CHECK-NEXT: stw 4, -104(1) +; CHECK-NEXT: stw 3, -108(1) +; CHECK-NEXT: blt 0, .LBB0_14 +; CHECK-NEXT: # BB#13: # %entry +; CHECK-NEXT: lwz 3, -92(1) +; CHECK-NEXT: stw 3, -104(1) +; CHECK-NEXT: .LBB0_14: # %entry +; CHECK-NEXT: lwz 3, -104(1) +; CHECK-NEXT: lwz 4, -108(1) +; CHECK-NEXT: lwz 5, -4(1) +; CHECK-NEXT: stw 4, 4(5) +; CHECK-NEXT: lwz 3, 0(3) + store i32 %z, i32* @var3, align 4 +; CHECK-NEXT: lis 4, var3 at ha +; CHECK-NEXT: stw 3, var3 at l(4) + ret void +; CHECK-NEXT: stw 5, -112(1) +; CHECK-NEXT: blr +} + From atrick at apple.com Tue Jun 28 11:32:01 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 28 Jun 2011 16:32:01 -0000 Subject: [llvm-commits] [llvm] r134008 - /llvm/trunk/test/CMakeLists.txt Message-ID: <20110628163201.7519A2A6C12C@llvm.org> Author: atrick Date: Tue Jun 28 11:32:01 2011 New Revision: 134008 URL: http://llvm.org/viewvc/llvm-project?rev=134008&view=rev Log: cmake: Our MSVC build does not support config-time build mode. Modified: llvm/trunk/test/CMakeLists.txt Modified: llvm/trunk/test/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CMakeLists.txt?rev=134008&r1=134007&r2=134008&view=diff ============================================================================== --- llvm/trunk/test/CMakeLists.txt (original) +++ llvm/trunk/test/CMakeLists.txt Tue Jun 28 11:32:01 2011 @@ -81,7 +81,7 @@ set(ENABLE_SHARED ${LLVM_SHARED_LIBS_ENABLED}) set(SHLIBPATH_VAR ${SHLIBPATH_VAR}) - if(LLVM_ENABLE_ASSERTIONS) + if(LLVM_ENABLE_ASSERTIONS AND NOT MSVC_IDE) set(ENABLE_ASSERTIONS "1") else() set(ENABLE_ASSERTIONS "0") From atrick at apple.com Tue Jun 28 11:45:04 2011 From: atrick at apple.com (Andrew Trick) Date: Tue, 28 Jun 2011 16:45:04 -0000 Subject: [llvm-commits] [llvm] r134010 - /llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Message-ID: <20110628164505.035932A6C12C@llvm.org> Author: atrick Date: Tue Jun 28 11:45:04 2011 New Revision: 134010 URL: http://llvm.org/viewvc/llvm-project?rev=134010&view=rev Log: cleanup: misleading comment. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=134010&r1=134009&r2=134010&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Jun 28 11:45:04 2011 @@ -1085,7 +1085,7 @@ // simplification on the wide IVs. while (!LoopPhis.empty()) { // Evaluate as many IV expressions as possible before widening any IVs. This - // forces SCEV to propagate no-wrap flags before evaluating sign/zero + // forces SCEV to set no-wrap flags before evaluating sign/zero // extension. The first time SCEV attempts to normalize sign/zero extension, // the result becomes final. So for the most predictable results, we delay // evaluation of sign/zero extend evaluation until needed, and avoid running @@ -1176,7 +1176,7 @@ // Simplification works best when run before other consumers of SCEV. We // attempt to avoid evaluating SCEVs for sign/zero extend operations until // other expressions involving loop IVs have been evaluated. This helps SCEV - // propagate no-wrap flags before normalizing sign/zero extension. + // set no-wrap flags before normalizing sign/zero extension. if (DisableIVRewrite) { Rewriter.disableCanonicalMode(); SimplifyIVUsersNoRewrite(L, Rewriter); From rafael.espindola at gmail.com Tue Jun 28 11:05:47 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 28 Jun 2011 12:05:47 -0400 Subject: [llvm-commits] Segmented stacks, current status. In-Reply-To: <4E089271.40607@playingwithpointers.com> References: <4E089271.40607@playingwithpointers.com> Message-ID: <4E09FBDB.5050401@gmail.com> On 06/27/2011 10:23 AM, Sanjoy Das wrote: > Hi! > > I am a GSoC student, working on implementing segmented stacks for LLVM. > I have attached a set of patches that add preliminary support for > segmented stacks and variable length allocas for review. The code is > also available on Github [1]. In getScratchRegister you have: +// Returns a register that is neither alive when entering the function or +// callee-saved. but the function then looks for a callee saved register that is not live in. Can we be sure that one is always available? Looking at gold (if you plan to use it for linking segmented and non segmented code), it looks like it assumes r10 or r11 is used. + TlsReg = X86::FS; + TlsOffset = 0x70; Being linux only is probably fine for now. Anyone familiar with how OS X does TLS? If it is similar enough maybe we can just put these constants in a subtarget. + // Read the limit off the current stacklet off the stack_guard location. + if (Is64Bit) { You are computing "stacklimit + size" and comparing rsp with it. Looks like gold assume a lea NN(%rs) to compute rs-size and that then gets compared with stacklimit. That also saves one instruction, no? - assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows()) && + assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || + EnableSegmentedStacks) && "This should be used only on Windows targets" The comment is stale :-) Dose __morestack_allocate_stack_space takes care of linking the memory so that when this function is called again we don't allocate another lange block? > The code, in the current state, does not support varargs. > > Thanks! > > [1] https://github.com/sanjoy/llvm/tree/segmented-stacks > Thanks! Cheers, Rafael From baldrick at free.fr Tue Jun 28 12:21:53 2011 From: baldrick at free.fr (Duncan Sands) Date: Tue, 28 Jun 2011 17:21:53 -0000 Subject: [llvm-commits] [dragonegg] r134012 - in /dragonegg/trunk: include/dragonegg/Internals.h src/Convert.cpp src/Types.cpp Message-ID: <20110628172153.71BCA2A6C12C@llvm.org> Author: baldrick Date: Tue Jun 28 12:21:53 2011 New Revision: 134012 URL: http://llvm.org/viewvc/llvm-project?rev=134012&view=rev Log: Handle void* correctly in the MEM_REF and TARGET_MEM_REF support code. Modified: dragonegg/trunk/include/dragonegg/Internals.h dragonegg/trunk/src/Convert.cpp dragonegg/trunk/src/Types.cpp Modified: dragonegg/trunk/include/dragonegg/Internals.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/dragonegg/Internals.h?rev=134012&r1=134011&r2=134012&view=diff ============================================================================== --- dragonegg/trunk/include/dragonegg/Internals.h (original) +++ dragonegg/trunk/include/dragonegg/Internals.h Tue Jun 28 12:21:53 2011 @@ -242,6 +242,10 @@ return TheTypeConverter->ConvertType(type); } +/// getPointerToType - Returns the LLVM register type to use for a pointer to +/// the given GCC type. +const Type *getPointerToType(tree_node *type); + /// getDefaultValue - Return the default value to use for a constant or global /// that has no value specified. For example in C like languages such variables /// are initialized to zero, while in Ada they hold an undefined value. Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=134012&r1=134011&r2=134012&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Tue Jun 28 12:21:53 2011 @@ -5960,8 +5960,7 @@ } // Ensure the pointer has the right type. - Addr = Builder.CreateBitCast(Addr, - ConvertType(TREE_TYPE(exp))->getPointerTo()); + Addr = Builder.CreateBitCast(Addr, getPointerToType(TREE_TYPE(exp))); unsigned Alignment = std::max(TYPE_ALIGN(TREE_TYPE (exp)), get_object_alignment(exp, BIGGEST_ALIGNMENT)); bool Volatile = TREE_THIS_VOLATILE(exp); @@ -6070,8 +6069,7 @@ } // The result can be of a different pointer type even if we didn't advance it. - Addr = Builder.CreateBitCast(Addr, - ConvertType(TREE_TYPE(exp))->getPointerTo()); + Addr = Builder.CreateBitCast(Addr, getPointerToType(TREE_TYPE(exp))); unsigned Alignment = TYPE_ALIGN(TREE_TYPE (exp)); #if (GCC_MINOR < 6) Alignment = get_object_alignment(exp, Alignment, BIGGEST_ALIGNMENT); Modified: dragonegg/trunk/src/Types.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Types.cpp?rev=134012&r1=134011&r2=134012&view=diff ============================================================================== --- dragonegg/trunk/src/Types.cpp (original) +++ dragonegg/trunk/src/Types.cpp Tue Jun 28 12:21:53 2011 @@ -550,6 +550,15 @@ } } +/// getPointerToType - Returns the LLVM register type to use for a pointer to +/// the given GCC type. +const Type *getPointerToType(tree type) { + if (VOID_TYPE_P(type)) + // void* -> byte* + return GetUnitPointerType(Context); + // FIXME: Handle address spaces. + return ConvertType(type)->getPointerTo(); +} const Type *TypeConverter::ConvertType(tree type) { if (type == error_mark_node) return Type::getInt32Ty(Context); From stoklund at 2pi.dk Tue Jun 28 12:24:32 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 28 Jun 2011 17:24:32 -0000 Subject: [llvm-commits] [llvm] r134013 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp Message-ID: <20110628172432.71EF72A6C12C@llvm.org> Author: stoklund Date: Tue Jun 28 12:24:32 2011 New Revision: 134013 URL: http://llvm.org/viewvc/llvm-project?rev=134013&view=rev Log: Print registers by name instead of by number. Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=134013&r1=134012&r2=134013&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Jun 28 12:24:32 2011 @@ -423,7 +423,7 @@ // Returns spillImpossible when PhysReg or an alias can't be spilled. unsigned RAFast::calcSpillCost(unsigned PhysReg) const { if (UsedInInstr.test(PhysReg)) { - DEBUG(dbgs() << "PhysReg: " << PhysReg << " is already used in instr.\n"); + DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is already used in instr.\n"); return spillImpossible; } switch (unsigned VirtReg = PhysRegState[PhysReg]) { @@ -432,15 +432,15 @@ case regFree: return 0; case regReserved: - DEBUG(dbgs() << "VirtReg: " << VirtReg << " corresponding to PhysReg: " - << PhysReg << " is reserved already.\n"); + DEBUG(dbgs() << PrintReg(VirtReg, TRI) << " corresponding " + << PrintReg(PhysReg, TRI) << " is reserved already.\n"); return spillImpossible; default: return LiveVirtRegs.lookup(VirtReg).Dirty ? spillDirty : spillClean; } // This is a disabled register, add up cost of aliases. - DEBUG(dbgs() << "\tRegister: " << PhysReg << " is disabled.\n"); + DEBUG(dbgs() << PrintReg(PhysReg, TRI) << " is disabled.\n"); unsigned Cost = 0; for (const unsigned *AS = TRI->getAliasSet(PhysReg); unsigned Alias = *AS; ++AS) { @@ -515,7 +515,7 @@ unsigned BestReg = 0, BestCost = spillImpossible; for (ArrayRef::iterator I = AO.begin(), E = AO.end(); I != E; ++I) { unsigned Cost = calcSpillCost(*I); - DEBUG(dbgs() << "\tRegister: " << *I << "\n"); + DEBUG(dbgs() << "\tRegister: " << PrintReg(*I, TRI) << "\n"); DEBUG(dbgs() << "\tCost: " << Cost << "\n"); DEBUG(dbgs() << "\tBestCost: " << BestCost << "\n"); // Cost is 0 when all aliases are already disabled. @@ -726,7 +726,8 @@ if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; unsigned Reg = MO.getReg(); if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; - DEBUG(dbgs() << "\tSetting reg " << Reg << " as used in instr\n"); + DEBUG(dbgs() << "\tSetting " << PrintReg(Reg, TRI) + << " as used in instr\n"); UsedInInstr.set(Reg); } From mcrosier at apple.com Tue Jun 28 12:26:57 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 28 Jun 2011 17:26:57 -0000 Subject: [llvm-commits] [llvm] r134014 - /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Message-ID: <20110628172658.0D9E42A6C12C@llvm.org> Author: mcrosier Date: Tue Jun 28 12:26:57 2011 New Revision: 134014 URL: http://llvm.org/viewvc/llvm-project?rev=134014&view=rev Log: Remove warning: 'c0' may be used uninitialized in this function. Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134014&r1=134013&r2=134014&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jun 28 12:26:57 2011 @@ -6486,7 +6486,8 @@ // elements are the same constant, C, and Log2(C) ranges from 1 to 32. static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C) { - integerPart c0, cN; + integerPart cN; + integerPart c0 = 0; for (unsigned I = 0, E = ConstVec.getValueType().getVectorNumElements(); I != E; I++) { ConstantFPSDNode *C = dyn_cast(ConstVec.getOperand(I)); From echristo at apple.com Tue Jun 28 12:29:30 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 28 Jun 2011 10:29:30 -0700 Subject: [llvm-commits] [llvm] r134013 - /llvm/trunk/lib/CodeGen/RegAllocFast.cpp In-Reply-To: <20110628172432.71EF72A6C12C@llvm.org> References: <20110628172432.71EF72A6C12C@llvm.org> Message-ID: <6E1F6B4D-F7A6-4645-9D88-181CB93DF4F4@apple.com> On Jun 28, 2011, at 10:24 AM, Jakob Stoklund Olesen wrote: > Print registers by name instead of by number. Yay! -eric From mcrosier at apple.com Tue Jun 28 12:38:36 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 28 Jun 2011 10:38:36 -0700 Subject: [llvm-commits] [llvm] r133999 - in /llvm/trunk: include/llvm/Constants.h lib/VMCore/Constants.cpp tools/lto/LTOModule.cpp In-Reply-To: <20110628082419.9C1B5312800A@llvm.org> References: <20110628082419.9C1B5312800A@llvm.org> Message-ID: Cool, thanks Jay! On Jun 28, 2011, at 1:24 AM, Jay Foad wrote: > Author: foad > Date: Tue Jun 28 03:24:19 2011 > New Revision: 133999 > > URL: http://llvm.org/viewvc/llvm-project?rev=133999&view=rev > Log: > PR10210: New method ConstantArray::getAsCString(). Use it in LTO to > avoid getting embedded trailing null bytes in std::strings. > > Modified: > llvm/trunk/include/llvm/Constants.h > llvm/trunk/lib/VMCore/Constants.cpp > llvm/trunk/tools/lto/LTOModule.cpp > > Modified: llvm/trunk/include/llvm/Constants.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Constants.h?rev=133999&r1=133998&r2=133999&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/Constants.h (original) > +++ llvm/trunk/include/llvm/Constants.h Tue Jun 28 03:24:19 2011 > @@ -387,6 +387,12 @@ > /// > std::string getAsString() const; > > + /// getAsCString - If this array is isCString(), then this method converts the > + /// array (without the trailing null byte) to an std::string and returns it. > + /// Otherwise, it asserts out. > + /// > + std::string getAsCString() const; > + > /// isNullValue - Return true if this is the value that would be returned by > /// getNullValue. This always returns false because zero arrays are always > /// created as ConstantAggregateZero objects. > > Modified: llvm/trunk/lib/VMCore/Constants.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/Constants.cpp?rev=133999&r1=133998&r2=133999&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/Constants.cpp (original) > +++ llvm/trunk/lib/VMCore/Constants.cpp Tue Jun 28 03:24:19 2011 > @@ -1011,17 +1011,32 @@ > } > > > -/// getAsString - If the sub-element type of this array is i8 > -/// then this method converts the array to an std::string and returns it. > -/// Otherwise, it asserts out. > +/// convertToString - Helper function for getAsString() and getAsCString(). > +static std::string convertToString(const User *U, unsigned len) > +{ > + std::string Result; > + Result.reserve(len); > + for (unsigned i = 0; i != len; ++i) > + Result.push_back((char)cast(U->getOperand(i))->getZExtValue()); > + return Result; > +} > + > +/// getAsString - If this array is isString(), then this method converts the > +/// array to an std::string and returns it. Otherwise, it asserts out. > /// > std::string ConstantArray::getAsString() const { > assert(isString() && "Not a string!"); > - std::string Result; > - Result.reserve(getNumOperands()); > - for (unsigned i = 0, e = getNumOperands(); i != e; ++i) > - Result.push_back((char)cast(getOperand(i))->getZExtValue()); > - return Result; > + return convertToString(this, getNumOperands()); > +} > + > + > +/// getAsCString - If this array is isCString(), then this method converts the > +/// array (without the trailing null byte) to an std::string and returns it. > +/// Otherwise, it asserts out. > +/// > +std::string ConstantArray::getAsCString() const { > + assert(isCString() && "Not a string!"); > + return convertToString(this, getNumOperands() - 1); > } > > > > Modified: llvm/trunk/tools/lto/LTOModule.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=133999&r1=133998&r2=133999&view=diff > ============================================================================== > --- llvm/trunk/tools/lto/LTOModule.cpp (original) > +++ llvm/trunk/tools/lto/LTOModule.cpp Tue Jun 28 03:24:19 2011 > @@ -191,7 +191,7 @@ > Constant *cn = gvn->getInitializer(); > if (ConstantArray *ca = dyn_cast(cn)) { > if (ca->isCString()) { > - name = ".objc_class_name_" + ca->getAsString(); > + name = ".objc_class_name_" + ca->getAsCString(); > return true; > } > } > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From mcrosier at apple.com Tue Jun 28 13:26:12 2011 From: mcrosier at apple.com (Chad Rosier) Date: Tue, 28 Jun 2011 18:26:12 -0000 Subject: [llvm-commits] [llvm] r134017 - /llvm/trunk/tools/lto/LTOModule.cpp Message-ID: <20110628182612.4943B2A6C12C@llvm.org> Author: mcrosier Date: Tue Jun 28 13:26:12 2011 New Revision: 134017 URL: http://llvm.org/viewvc/llvm-project?rev=134017&view=rev Log: Reinstate r133516 "Remove some unnecessary uses of c_str()." A trailing null character in std::string was causing failures for a few ObjC and Obj-C++ tests when -flto was enabled. Revision 133999 resolved this issue. Thanks Jay! rdar://9685235 PR10210 Modified: llvm/trunk/tools/lto/LTOModule.cpp Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=134017&r1=134016&r2=134017&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Tue Jun 28 13:26:12 2011 @@ -208,7 +208,7 @@ if (objcClassNameFromExpression(c->getOperand(1), superclassName)) { NameAndAttributes info; StringMap::value_type &entry = - _undefines.GetOrCreateValue(superclassName.c_str()); + _undefines.GetOrCreateValue(superclassName); if (!entry.getValue().name) { const char *symbolName = entry.getKey().data(); info.name = symbolName; @@ -220,7 +220,7 @@ std::string className; if (objcClassNameFromExpression(c->getOperand(2), className)) { StringSet::value_type &entry = - _defines.GetOrCreateValue(className.c_str()); + _defines.GetOrCreateValue(className); entry.setValue(1); NameAndAttributes info; info.name = entry.getKey().data(); @@ -243,7 +243,7 @@ NameAndAttributes info; StringMap::value_type &entry = - _undefines.GetOrCreateValue(targetclassName.c_str()); + _undefines.GetOrCreateValue(targetclassName); if (entry.getValue().name) return; @@ -264,7 +264,7 @@ NameAndAttributes info; StringMap::value_type &entry = - _undefines.GetOrCreateValue(targetclassName.c_str()); + _undefines.GetOrCreateValue(targetclassName); if (entry.getValue().name) return; @@ -375,7 +375,7 @@ // add to table of symbols NameAndAttributes info; - StringSet::value_type &entry = _defines.GetOrCreateValue(Buffer.c_str()); + StringSet::value_type &entry = _defines.GetOrCreateValue(Buffer); entry.setValue(1); StringRef Name = entry.getKey(); @@ -436,7 +436,7 @@ mangler.getNameWithPrefix(name, decl, false); StringMap::value_type &entry = - _undefines.GetOrCreateValue(name.c_str()); + _undefines.GetOrCreateValue(name); // we already have the symbol if (entry.getValue().name) From stoklund at 2pi.dk Tue Jun 28 13:32:28 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Tue, 28 Jun 2011 18:32:28 -0000 Subject: [llvm-commits] [llvm] r134018 - in /llvm/trunk: lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86FloatingPoint.cpp lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFPStack.td lib/Target/X86/X86RegisterInfo.cpp lib/Target/X86/X86RegisterInfo.td test/CodeGen/X86/inline-asm-fpstack.ll Message-ID: <20110628183228.AA6722A6C12C@llvm.org> Author: stoklund Date: Tue Jun 28 13:32:28 2011 New Revision: 134018 URL: http://llvm.org/viewvc/llvm-project?rev=134018&view=rev Log: Clean up the handling of the x87 fp stack to make it more robust. Drop the FpMov instructions, use plain COPY instead. Drop the FpSET/GET instruction for accessing fixed stack positions. Instead use normal COPY to/from ST registers around inline assembly, and provide a single new FpPOP_RETVAL instruction that can access the return value(s) from a call. This is still necessary since you cannot tell from the CALL instruction alone if it returns anything on the FP stack. Teach fast isel to use this. This provides a much more robust way of handling fixed stack registers - we can tolerate arbitrary FP stack instructions inserted around calls and inline assembly. Live range splitting could sometimes break x87 code by inserting spill code in unfortunate places. As a bonus we handle floating point inline assembly correctly now. Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86InstrFPStack.td llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.td llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=134018&r1=134017&r2=134018&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Jun 28 13:32:28 2011 @@ -1848,16 +1848,18 @@ // stack, but where we prefer to use the value in xmm registers, copy it // out as F80 and use a truncate to move it from fp stack reg to xmm reg. if ((RVLocs[i].getLocReg() == X86::ST0 || - RVLocs[i].getLocReg() == X86::ST1) && - isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) { - CopyVT = MVT::f80; + RVLocs[i].getLocReg() == X86::ST1)) { + if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) + CopyVT = MVT::f80; CopyReg = createResultReg(X86::RFP80RegisterClass); + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL), + CopyReg); + } else { + BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), + CopyReg).addReg(RVLocs[i].getLocReg()); + UsedRegs.push_back(RVLocs[i].getLocReg()); } - BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), - CopyReg).addReg(RVLocs[i].getLocReg()); - UsedRegs.push_back(RVLocs[i].getLocReg()); - if (CopyVT != RVLocs[i].getValVT()) { // Round the F80 the right size, which also moves to the appropriate xmm // register. This is accomplished by storing the F80 value in memory and Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=134018&r1=134017&r2=134018&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Tue Jun 28 13:32:28 2011 @@ -37,6 +37,7 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/Passes.h" +#include "llvm/InlineAsm.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" @@ -134,11 +135,36 @@ unsigned Stack[8]; // FP Registers in each stack slot... unsigned StackTop; // The current top of the FP stack. + enum { + NumFPRegs = 16 // Including scratch pseudo-registers. + }; + // For each live FP register, point to its Stack[] entry. // The first entries correspond to FP0-FP6, the rest are scratch registers // used when we need slightly different live registers than what the // register allocator thinks. - unsigned RegMap[16]; + unsigned RegMap[NumFPRegs]; + + // Pending fixed registers - Inline assembly needs FP registers to appear + // in fixed stack slot positions. This is handled by copying FP registers + // to ST registers before the instruction, and copying back after the + // instruction. + // + // This is modeled with pending ST registers. NumPendingSTs is the number + // of ST registers (ST0-STn) we are tracking. PendingST[n] points to an FP + // register that holds the ST value. The ST registers are not moved into + // place until immediately before the instruction that needs them. + // + // It can happen that we need an ST register to be live when no FP register + // holds the value: + // + // %ST0 = COPY %FP4 + // + // When that happens, we allocate a scratch FP register to hold the ST + // value. That means every register in PendingST must be live. + + unsigned NumPendingSTs; + unsigned char PendingST[8]; // Set up our stack model to match the incoming registers to MBB. void setupBlockStack(); @@ -152,13 +178,15 @@ dbgs() << " FP" << Stack[i]; assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!"); } + for (unsigned i = 0; i != NumPendingSTs; ++i) + dbgs() << ", ST" << i << " in FP" << unsigned(PendingST[i]); dbgs() << "\n"; } /// getSlot - Return the stack slot number a particular register number is /// in. unsigned getSlot(unsigned RegNo) const { - assert(RegNo < array_lengthof(RegMap) && "Regno out of range!"); + assert(RegNo < NumFPRegs && "Regno out of range!"); return RegMap[RegNo]; } @@ -170,12 +198,17 @@ /// getScratchReg - Return an FP register that is not currently in use. unsigned getScratchReg() { - for (int i = array_lengthof(RegMap) - 1; i >= 8; --i) + for (int i = NumFPRegs - 1; i >= 8; --i) if (!isLive(i)) return i; llvm_unreachable("Ran out of scratch FP registers"); } + /// isScratchReg - Returns trus if RegNo is a scratch FP register. + bool isScratchReg(unsigned RegNo) { + return RegNo > 8 && RegNo < NumFPRegs; + } + /// getStackEntry - Return the X86::FP register in register ST(i). unsigned getStackEntry(unsigned STi) const { if (STi >= StackTop) @@ -191,7 +224,7 @@ // pushReg - Push the specified FP register onto the stack. void pushReg(unsigned Reg) { - assert(Reg < array_lengthof(RegMap) && "Register number out of range!"); + assert(Reg < NumFPRegs && "Register number out of range!"); if (StackTop >= 8) report_fatal_error("Stack overflow!"); Stack[StackTop] = Reg; @@ -261,7 +294,14 @@ void handleCondMovFP(MachineBasicBlock::iterator &I); void handleSpecialFP(MachineBasicBlock::iterator &I); - bool translateCopy(MachineInstr*); + // Check if a COPY instruction is using FP registers. + bool isFPCopy(MachineInstr *MI) { + unsigned DstReg = MI->getOperand(0).getReg(); + unsigned SrcReg = MI->getOperand(1).getReg(); + + return X86::RFP80RegClass.contains(DstReg) || + X86::RFP80RegClass.contains(SrcReg); + } }; char FPS::ID = 0; } @@ -351,6 +391,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) { bool Changed = false; MBB = &BB; + NumPendingSTs = 0; setupBlockStack(); @@ -362,7 +403,7 @@ if (MI->isInlineAsm()) FPInstClass = X86II::SpecialFP; - if (MI->isCopy() && translateCopy(MI)) + if (MI->isCopy() && isFPCopy(MI)) FPInstClass = X86II::SpecialFP; if (FPInstClass == X86II::NotFP) @@ -891,7 +932,8 @@ continue; // (Reg st0) (OldReg st0) = (Reg OldReg st0) moveToTop(Reg, I); - moveToTop(OldReg, I); + if (FixCount > 0) + moveToTop(OldReg, I); } DEBUG(dumpStack()); } @@ -1249,142 +1291,309 @@ MachineInstr *MI = I; switch (MI->getOpcode()) { default: llvm_unreachable("Unknown SpecialFP instruction!"); - case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type! - case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type! - case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type! - assert(StackTop == 0 && "Stack should be empty after a call!"); - pushReg(getFPReg(MI->getOperand(0))); - break; - case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type! - case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type! - case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type! - // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm. - // The pattern we expect is: - // CALL - // FP1 = FpGET_ST0 - // FP4 = FpGET_ST1 - // - // At this point, we've pushed FP1 on the top of stack, so it should be - // present if it isn't dead. If it was dead, we already emitted a pop to - // remove it from the stack and StackTop = 0. - - // Push FP4 as top of stack next. - pushReg(getFPReg(MI->getOperand(0))); + case TargetOpcode::COPY: { + // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP. + const MachineOperand &MO1 = MI->getOperand(1); + const MachineOperand &MO0 = MI->getOperand(0); + unsigned DstST = MO0.getReg() - X86::ST0; + unsigned SrcST = MO1.getReg() - X86::ST0; + bool KillsSrc = MI->killsRegister(MO1.getReg()); + + // ST = COPY FP. Set up a pending ST register. + if (DstST < 8) { + unsigned SrcFP = getFPReg(MO1); + assert(isLive(SrcFP) && "Cannot copy dead register"); + assert(!MO0.isDead() && "Cannot copy to dead ST register"); + + // Unallocated STs are marked as the nonexistent FP255. + while (NumPendingSTs <= DstST) + PendingST[NumPendingSTs++] = NumFPRegs; + + // STi could still be live from a previous inline asm. + if (isScratchReg(PendingST[DstST])) { + DEBUG(dbgs() << "Clobbering old ST in FP" << unsigned(PendingST[DstST]) + << '\n'); + freeStackSlotBefore(MI, PendingST[DstST]); + } - // If StackTop was 0 before we pushed our operand, then ST(0) must have been - // dead. In this case, the ST(1) value is the only thing that is live, so - // it should be on the TOS (after the pop that was emitted) and is. Just - // continue in this case. - if (StackTop == 1) + // When the source is killed, allocate a scratch FP register. + if (KillsSrc) { + unsigned Slot = getSlot(SrcFP); + unsigned SR = getScratchReg(); + PendingST[DstST] = SR; + Stack[Slot] = SR; + RegMap[SR] = Slot; + } else + PendingST[DstST] = SrcFP; break; - - // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top - // elements so that our accounting is correct. - unsigned RegOnTop = getStackEntry(0); - unsigned RegNo = getStackEntry(1); - - // Swap the slots the regs are in. - std::swap(RegMap[RegNo], RegMap[RegOnTop]); - - // Swap stack slot contents. - if (RegMap[RegOnTop] >= StackTop) - report_fatal_error("Access past stack top!"); - std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]); - break; - } - case X86::FpSET_ST0_32: - case X86::FpSET_ST0_64: - case X86::FpSET_ST0_80: { - // FpSET_ST0_80 is generated by copyRegToReg for setting up inline asm - // arguments that use an st constraint. We expect a sequence of - // instructions: Fp_SET_ST0 Fp_SET_ST1? INLINEASM - unsigned Op0 = getFPReg(MI->getOperand(0)); - - if (!MI->killsRegister(X86::FP0 + Op0)) { - // Duplicate Op0 into a temporary on the stack top. - duplicateToTop(Op0, getScratchReg(), I); - } else { - // Op0 is killed, so just swap it into position. - moveToTop(Op0, I); } - --StackTop; // "Forget" we have something on the top of stack! - break; - } - case X86::FpSET_ST1_32: - case X86::FpSET_ST1_64: - case X86::FpSET_ST1_80: { - // Set up st(1) for inline asm. We are assuming that st(0) has already been - // set up by FpSET_ST0, and our StackTop is off by one because of it. - unsigned Op0 = getFPReg(MI->getOperand(0)); - // Restore the actual StackTop from before Fp_SET_ST0. - // Note we can't handle Fp_SET_ST1 without a preceding Fp_SET_ST0, and we - // are not enforcing the constraint. - ++StackTop; - unsigned RegOnTop = getStackEntry(0); // This reg must remain in st(0). - if (!MI->killsRegister(X86::FP0 + Op0)) { - duplicateToTop(Op0, getScratchReg(), I); - moveToTop(RegOnTop, I); - } else if (getSTReg(Op0) != X86::ST1) { - // We have the wrong value at st(1). Shuffle! Untested! - moveToTop(getStackEntry(1), I); - moveToTop(Op0, I); - moveToTop(RegOnTop, I); + + // FP = COPY ST. Extract fixed stack value. + // Any instruction defining ST registers must have assigned them to a + // scratch register. + if (SrcST < 8) { + unsigned DstFP = getFPReg(MO0); + assert(!isLive(DstFP) && "Cannot copy ST to live FP register"); + assert(NumPendingSTs > SrcST && "Cannot copy from dead ST register"); + unsigned SrcFP = PendingST[SrcST]; + assert(isScratchReg(SrcFP) && "Expected ST in a scratch register"); + assert(isLive(SrcFP) && "Scratch holding ST is dead"); + + // DstFP steals the stack slot from SrcFP. + unsigned Slot = getSlot(SrcFP); + Stack[Slot] = DstFP; + RegMap[DstFP] = Slot; + + // Always treat the ST as killed. + PendingST[SrcST] = NumFPRegs; + while (NumPendingSTs && PendingST[NumPendingSTs - 1] == NumFPRegs) + --NumPendingSTs; + break; } - assert(StackTop >= 2 && "Too few live registers"); - StackTop -= 2; // "Forget" both st(0) and st(1). - break; - } - case X86::MOV_Fp3232: - case X86::MOV_Fp3264: - case X86::MOV_Fp6432: - case X86::MOV_Fp6464: - case X86::MOV_Fp3280: - case X86::MOV_Fp6480: - case X86::MOV_Fp8032: - case X86::MOV_Fp8064: - case X86::MOV_Fp8080: { - const MachineOperand &MO1 = MI->getOperand(1); - unsigned SrcReg = getFPReg(MO1); - const MachineOperand &MO0 = MI->getOperand(0); - unsigned DestReg = getFPReg(MO0); - if (MI->killsRegister(X86::FP0+SrcReg)) { + // FP <- FP copy. + unsigned DstFP = getFPReg(MO0); + unsigned SrcFP = getFPReg(MO1); + assert(isLive(SrcFP) && "Cannot copy dead register"); + if (KillsSrc) { // If the input operand is killed, we can just change the owner of the // incoming stack slot into the result. - unsigned Slot = getSlot(SrcReg); - assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!"); - Stack[Slot] = DestReg; - RegMap[DestReg] = Slot; - + unsigned Slot = getSlot(SrcFP); + Stack[Slot] = DstFP; + RegMap[DstFP] = Slot; } else { - // For FMOV we just duplicate the specified value to a new stack slot. + // For COPY we just duplicate the specified value to a new stack slot. // This could be made better, but would require substantial changes. - duplicateToTop(SrcReg, DestReg, I); + duplicateToTop(SrcFP, DstFP, I); } + break; + } + + case X86::FpPOP_RETVAL: { + // The FpPOP_RETVAL instruction is used after calls that return a value on + // the floating point stack. We cannot model this with ST defs since CALL + // instructions have fixed clobber lists. This instruction is interpreted + // to mean that there is one more live register on the stack than we + // thought. + // + // This means that StackTop does not match the hardware stack between a + // call and the FpPOP_RETVAL instructions. We do tolerate FP instructions + // between CALL and FpPOP_RETVAL as long as they don't overflow the + // hardware stack. + unsigned DstFP = getFPReg(MI->getOperand(0)); + + // Move existing stack elements up to reflect reality. + assert(StackTop < 8 && "Stack overflowed before FpPOP_RETVAL"); + if (StackTop) { + std::copy_backward(Stack, Stack + StackTop, Stack + StackTop + 1); + for (unsigned i = 0; i != NumFPRegs; ++i) + ++RegMap[i]; } + ++StackTop; + + // DstFP is the new bottom of the stack. + Stack[0] = DstFP; + RegMap[DstFP] = 0; + + // DstFP will be killed by processBasicBlock if this was a dead def. break; + } + case TargetOpcode::INLINEASM: { // The inline asm MachineInstr currently only *uses* FP registers for the // 'f' constraint. These should be turned into the current ST(x) register - // in the machine instr. Also, any kills should be explicitly popped after - // the inline asm. - unsigned Kills = 0; + // in the machine instr. + // + // There are special rules for x87 inline assembly. The compiler must know + // exactly how many registers are popped and pushed implicitly by the asm. + // Otherwise it is not possible to restore the stack state after the inline + // asm. + // + // There are 3 kinds of input operands: + // + // 1. Popped inputs. These must appear at the stack top in ST0-STn. A + // popped input operand must be in a fixed stack slot, and it is either + // tied to an output operand, or in the clobber list. The MI has ST use + // and def operands for these inputs. + // + // 2. Fixed inputs. These inputs appear in fixed stack slots, but are + // preserved by the inline asm. The fixed stack slots must be STn-STm + // following the popped inputs. A fixed input operand cannot be tied to + // an output or appear in the clobber list. The MI has ST use operands + // and no defs for these inputs. + // + // 3. Preserved inputs. These inputs use the "f" constraint which is + // represented as an FP register. The inline asm won't change these + // stack slots. + // + // Outputs must be in ST registers, FP outputs are not allowed. Clobbered + // registers do not count as output operands. The inline asm changes the + // stack as if it popped all the popped inputs and then pushed all the + // output operands. + + // Scan the assembly for ST registers used, defined and clobbered. We can + // only tell clobbers from defs by looking at the asm descriptor. + unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0; + unsigned NumOps = 0; + for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands(); + i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) { + unsigned Flags = MI->getOperand(i).getImm(); + NumOps = InlineAsm::getNumOperandRegisters(Flags); + if (NumOps != 1) + continue; + const MachineOperand &MO = MI->getOperand(i + 1); + if (!MO.isReg()) + continue; + unsigned STReg = MO.getReg() - X86::ST0; + if (STReg >= 8) + continue; + + switch (InlineAsm::getKind(Flags)) { + case InlineAsm::Kind_RegUse: + STUses |= (1u << STReg); + break; + case InlineAsm::Kind_RegDef: + case InlineAsm::Kind_RegDefEarlyClobber: + STDefs |= (1u << STReg); + if (MO.isDead()) + STDeadDefs |= (1u << STReg); + break; + case InlineAsm::Kind_Clobber: + STClobbers |= (1u << STReg); + break; + default: + break; + } + } + + if (STUses && !isMask_32(STUses)) + report_fatal_error("Inline asm fixed inputs" + " must be last on the x87 stack"); + unsigned NumSTUses = CountTrailingOnes_32(STUses); + + // Defs must be contiguous from the stack top. ST0-STn. + if (STDefs && !isMask_32(STDefs)) + report_fatal_error("Inline asm fixed outputs" + " must be last on the x87 stack"); + unsigned NumSTDefs = CountTrailingOnes_32(STDefs); + + // So must the clobbered stack slots. ST0-STm, m >= n. + if (STClobbers && !isMask_32(STDefs | STClobbers)) + report_fatal_error("Inline asm clobbers must be last on the x87 stack"); + + // Popped inputs are the ones that are also clobbered or defined. + unsigned STPopped = STUses & (STDefs | STClobbers); + if (STPopped && !isMask_32(STPopped)) + report_fatal_error("Inline asm popped inputs" + " must be last on the x87 stack"); + unsigned NumSTPopped = CountTrailingOnes_32(STPopped); + + DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops " + << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n"); + + // Scan the instruction for FP uses corresponding to "f" constraints. + // Collect FP registers to kill afer the instruction. + // Always kill all the scratch regs. + unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff; + unsigned FPUsed = 0; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { MachineOperand &Op = MI->getOperand(i); if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) continue; - assert(Op.isUse() && "Only handle inline asm uses right now"); - + if (!Op.isUse()) + report_fatal_error("Illegal \"f\" output constraint in inline asm"); unsigned FPReg = getFPReg(Op); - Op.setReg(getSTReg(FPReg)); - + FPUsed |= 1U << FPReg; + // If we kill this operand, make sure to pop it from the stack after the // asm. We just remember it for now, and pop them all off at the end in // a batch. if (Op.isKill()) - Kills |= 1U << FPReg; + FPKills |= 1U << FPReg; } + // The popped inputs will be killed by the instruction, so duplicate them + // if the FP register needs to be live after the instruction, or if it is + // used in the instruction itself. We effectively treat the popped inputs + // as early clobbers. + for (unsigned i = 0; i < NumSTPopped; ++i) { + if ((FPKills & ~FPUsed) & (1u << PendingST[i])) + continue; + unsigned SR = getScratchReg(); + duplicateToTop(PendingST[i], SR, I); + DEBUG(dbgs() << "Duplicating ST" << i << " in FP" + << unsigned(PendingST[i]) << " to avoid clobbering it.\n"); + PendingST[i] = SR; + } + + // Make sure we have a unique live register for every fixed use. Some of + // them could be undef uses, and we need to emit LD_F0 instructions. + for (unsigned i = 0; i < NumSTUses; ++i) { + if (i < NumPendingSTs && PendingST[i] < NumFPRegs) { + // Check for shared assignments. + for (unsigned j = 0; j < i; ++j) { + if (PendingST[j] != PendingST[i]) + continue; + // STi and STj are inn the same register, create a copy. + unsigned SR = getScratchReg(); + duplicateToTop(PendingST[i], SR, I); + DEBUG(dbgs() << "Duplicating ST" << i << " in FP" + << unsigned(PendingST[i]) + << " to avoid collision with ST" << j << '\n'); + PendingST[i] = SR; + } + continue; + } + unsigned SR = getScratchReg(); + DEBUG(dbgs() << "Emitting LD_F0 for ST" << i << " in FP" << SR << '\n'); + BuildMI(*MBB, I, MI->getDebugLoc(), TII->get(X86::LD_F0)); + pushReg(SR); + PendingST[i] = SR; + if (NumPendingSTs == i) + ++NumPendingSTs; + } + assert(NumPendingSTs >= NumSTUses && "Fixed registers should be assigned"); + + // Now we can rearrange the live registers to match what was requested. + shuffleStackTop(PendingST, NumPendingSTs, I); + DEBUG({dbgs() << "Before asm: "; dumpStack();}); + + // With the stack layout fixed, rewrite the FP registers. + for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { + MachineOperand &Op = MI->getOperand(i); + if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6) + continue; + unsigned FPReg = getFPReg(Op); + Op.setReg(getSTReg(FPReg)); + } + + // Simulate the inline asm popping its inputs and pushing its outputs. + StackTop -= NumSTPopped; + + // Hold the fixed output registers in scratch FP registers. They will be + // transferred to real FP registers by copies. + NumPendingSTs = 0; + for (unsigned i = 0; i < NumSTDefs; ++i) { + unsigned SR = getScratchReg(); + pushReg(SR); + FPKills &= ~(1u << SR); + } + for (unsigned i = 0; i < NumSTDefs; ++i) + PendingST[NumPendingSTs++] = getStackEntry(i); + DEBUG({dbgs() << "After asm: "; dumpStack();}); + + // If any of the ST defs were dead, pop them immediately. Our caller only + // handles dead FP defs. + MachineBasicBlock::iterator InsertPt = MI; + for (unsigned i = 0; STDefs & (1u << i); ++i) { + if (!(STDeadDefs & (1u << i))) + continue; + freeStackSlotAfter(InsertPt, PendingST[i]); + PendingST[i] = NumFPRegs; + } + while (NumPendingSTs && PendingST[NumPendingSTs - 1] == NumFPRegs) + --NumPendingSTs; + // If this asm kills any FP registers (is the last use of them) we must // explicitly emit pop instructions for them. Do this now after the asm has // executed so that the ST(x) numbers are not off (which would happen if we @@ -1392,16 +1601,16 @@ // // Note: this might be a non-optimal pop sequence. We might be able to do // better by trying to pop in stack order or something. - MachineBasicBlock::iterator InsertPt = MI; - while (Kills) { - unsigned FPReg = CountTrailingZeros_32(Kills); - freeStackSlotAfter(InsertPt, FPReg); - Kills &= ~(1U << FPReg); + while (FPKills) { + unsigned FPReg = CountTrailingZeros_32(FPKills); + if (isLive(FPReg)) + freeStackSlotAfter(InsertPt, FPReg); + FPKills &= ~(1U << FPReg); } // Don't delete the inline asm! return; } - + case X86::RET: case X86::RETI: // If RET has an FP register use operand, pass the first one in ST(0) and @@ -1499,33 +1708,3 @@ } else --I; } - -// Translate a COPY instruction to a pseudo-op that handleSpecialFP understands. -bool FPS::translateCopy(MachineInstr *MI) { - unsigned DstReg = MI->getOperand(0).getReg(); - unsigned SrcReg = MI->getOperand(1).getReg(); - - if (DstReg == X86::ST0) { - MI->setDesc(TII->get(X86::FpSET_ST0_80)); - MI->RemoveOperand(0); - return true; - } - if (DstReg == X86::ST1) { - MI->setDesc(TII->get(X86::FpSET_ST1_80)); - MI->RemoveOperand(0); - return true; - } - if (SrcReg == X86::ST0) { - MI->setDesc(TII->get(X86::FpGET_ST0_80)); - return true; - } - if (SrcReg == X86::ST1) { - MI->setDesc(TII->get(X86::FpGET_ST1_80)); - return true; - } - if (X86::RFP80RegClass.contains(DstReg, SrcReg)) { - MI->setDesc(TII->get(X86::MOV_Fp8080)); - return true; - } - return false; -} Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=134018&r1=134017&r2=134018&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jun 28 13:32:28 2011 @@ -1511,20 +1511,15 @@ // If this is a call to a function that returns an fp value on the floating // point stack, we must guarantee the the value is popped from the stack, so // a CopyFromReg is not good enough - the copy instruction may be eliminated - // if the return value is not used. We use the FpGET_ST0 instructions + // if the return value is not used. We use the FpPOP_RETVAL instruction // instead. if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { // If we prefer to use the value in xmm registers, copy it out as f80 and // use a truncate to move it from fp stack reg to xmm reg. if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; - bool isST0 = VA.getLocReg() == X86::ST0; - unsigned Opc = 0; - if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32; - if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64; - if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80; SDValue Ops[] = { Chain, InFlag }; - Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Glue, - Ops, 2), 1); + Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, + MVT::Other, MVT::Glue, Ops, 2), 1); Val = Chain.getValue(0); // Round the f80 to the right size, which also moves it to the appropriate Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=134018&r1=134017&r2=134018&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Tue Jun 28 13:32:28 2011 @@ -112,31 +112,8 @@ // a pattern) and the FPI instruction should have emission info (e.g. opcode // encoding and asm printing info). -// Pseudo Instructions for FP stack return values. -def FpGET_ST0_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(0) -def FpGET_ST0_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(0) -def FpGET_ST0_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(0) - -// FpGET_ST1* should only be issued *after* an FpGET_ST0* has been issued when -// there are two values live out on the stack from a call or inlineasm. This -// magic is handled by the stackifier. It is not valid to emit FpGET_ST1* and -// then FpGET_ST0*. In addition, it is invalid for any FP-using operations to -// occur between them. -def FpGET_ST1_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(1) -def FpGET_ST1_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(1) -def FpGET_ST1_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(1) - -let Defs = [ST0] in { -def FpSET_ST0_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(0) = FPR -def FpSET_ST0_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(0) = FPR -def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR -} - -let Defs = [ST1] in { -def FpSET_ST1_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(1) = FPR -def FpSET_ST1_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(1) = FPR -def FpSET_ST1_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(1) = FPR -} +// Pseudo Instruction for FP stack return values. +def FpPOP_RETVAL : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FpIf32, FpIf64 - Floating Point Pseudo Instruction template. // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1. @@ -147,19 +124,6 @@ class FpIf64 pattern> : FpI_, Requires<[FPStackf64]>; -// Register copies. Just copies, the shortening ones do not truncate. -let neverHasSideEffects = 1 in { - def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>; - def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>; - def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>; - def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>; - def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>; - def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>; - def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>; - def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>; - def MOV_Fp8080 : FpI_ <(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>; -} - // Factoring for arithmetic. multiclass FPBinary_rr { // Register op register -> register Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=134018&r1=134017&r2=134018&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Jun 28 13:32:28 2011 @@ -500,18 +500,6 @@ Reserved.set(X86::BPL); } - // Mark the x87 stack registers as reserved, since they don't behave normally - // with respect to liveness. We don't fully model the effects of x87 stack - // pushes and pops after stackification. - Reserved.set(X86::ST0); - Reserved.set(X86::ST1); - Reserved.set(X86::ST2); - Reserved.set(X86::ST3); - Reserved.set(X86::ST4); - Reserved.set(X86::ST5); - Reserved.set(X86::ST6); - Reserved.set(X86::ST7); - // Mark the segment registers as reserved. Reserved.set(X86::CS); Reserved.set(X86::SS); Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=134018&r1=134017&r2=134018&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue Jun 28 13:32:28 2011 @@ -206,15 +206,22 @@ def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegAlias; } - // Floating point stack registers - def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>; - def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>; - def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>; - def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>; - def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>; - def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>; - def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>; - def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>; + class STRegister A> : Register { + let Aliases = A; + } + + // Floating point stack registers. These don't map one-to-one to the FP + // pseudo registers, but we still mark them as aliasing FP registers. That + // way both kinds can be live without exceeding the stack depth. ST registers + // are only live around inline assembly. + def ST0 : STRegister<"st(0)", []>, DwarfRegNum<[33, 12, 11]>; + def ST1 : STRegister<"st(1)", [FP6]>, DwarfRegNum<[34, 13, 12]>; + def ST2 : STRegister<"st(2)", [FP5]>, DwarfRegNum<[35, 14, 13]>; + def ST3 : STRegister<"st(3)", [FP4]>, DwarfRegNum<[36, 15, 14]>; + def ST4 : STRegister<"st(4)", [FP3]>, DwarfRegNum<[37, 16, 15]>; + def ST5 : STRegister<"st(5)", [FP2]>, DwarfRegNum<[38, 17, 16]>; + def ST6 : STRegister<"st(6)", [FP1]>, DwarfRegNum<[39, 18, 17]>; + def ST7 : STRegister<"st(7)", [FP0]>, DwarfRegNum<[40, 19, 18]>; // Status flags register def EFLAGS : Register<"flags">; Modified: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll?rev=134018&r1=134017&r2=134018&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll (original) +++ llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll Tue Jun 28 13:32:28 2011 @@ -106,6 +106,25 @@ ret void } +; Passing a non-killed value through asm in {st}. +; Make sure it is not duped before. +; Second asm kills st(0), so we shouldn't pop anything +; CHECK: testPR4185b +; CHECK-NOT: fld %st(0) +; CHECK: fistl +; CHECK-NOT: fstp +; CHECK: fistpl +; CHECK-NOT: fstp +; CHECK: ret +; A valid alternative would be to remat the constant pool load before each +; inline asm. +define void @testPR4185b() { +return: + call void asm sideeffect "fistl $0", "{st}"(double 1.000000e+06) + call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06) + ret void +} + ; PR4459 ; The return value from ceil must be duped before being consumed by asm. ; CHECK: testPR4459 @@ -160,3 +179,153 @@ tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %5) ret void } + +; An input argument in a fixed position is implicitly popped by the asm only if +; the input argument is tied to an output register, or it is in the clobber list. +; The clobber list case is tested above. +; +; This doesn't implicitly pop the stack: +; +; void fist1(long double x, int *p) { +; asm volatile ("fistl %1" : : "t"(x), "m"(*p)); +; } +; +; CHECK: fist1 +; CHECK: fldt +; CHECK: fistl (%e +; CHECK: fstp +; CHECK: ret +define void @fist1(x86_fp80 %x, i32* %p) nounwind ssp { +entry: + tail call void asm sideeffect "fistl $1", "{st},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind + ret void +} + +; Here, the input operand is tied to an output which means that is is +; implicitly popped (and then the output is implicitly pushed). +; +; long double fist2(long double x, int *p) { +; long double y; +; asm ("fistl %1" : "=&t"(y) : "0"(x), "m"(*p) : "memory"); +; return y; +; } +; +; CHECK: fist2 +; CHECK: fldt +; CHECK: fistl (%e +; CHECK-NOT: fstp +; CHECK: ret +define x86_fp80 @fist2(x86_fp80 %x, i32* %p) nounwind ssp { +entry: + %0 = tail call x86_fp80 asm "fistl $2", "=&{st},0,*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind + ret x86_fp80 %0 +} + +; An 'f' constraint is never implicitly popped: +; +; void fucomp1(long double x, long double y) { +; asm volatile ("fucomp %1" : : "t"(x), "f"(y) : "st"); +; } +; CHECK: fucomp1 +; CHECK: fldt +; CHECK: fldt +; CHECK: fucomp %st +; CHECK: fstp +; CHECK-NOT: fstp +; CHECK: ret +define void @fucomp1(x86_fp80 %x, x86_fp80 %y) nounwind ssp { +entry: + tail call void asm sideeffect "fucomp $1", "{st},f,~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind + ret void +} + +; The 'u' constraint is only popped implicitly when clobbered: +; +; void fucomp2(long double x, long double y) { +; asm volatile ("fucomp %1" : : "t"(x), "u"(y) : "st"); +; } +; +; void fucomp3(long double x, long double y) { +; asm volatile ("fucompp %1" : : "t"(x), "u"(y) : "st", "st(1)"); +; } +; +; CHECK: fucomp2 +; CHECK: fldt +; CHECK: fldt +; CHECK: fucomp %st(1) +; CHECK: fstp +; CHECK-NOT: fstp +; CHECK: ret +; +; CHECK: fucomp3 +; CHECK: fldt +; CHECK: fldt +; CHECK: fucompp %st(1) +; CHECK-NOT: fstp +; CHECK: ret +define void @fucomp2(x86_fp80 %x, x86_fp80 %y) nounwind ssp { +entry: + tail call void asm sideeffect "fucomp $1", "{st},{st(1)},~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind + ret void +} +define void @fucomp3(x86_fp80 %x, x86_fp80 %y) nounwind ssp { +entry: + tail call void asm sideeffect "fucompp $1", "{st},{st(1)},~{st},~{st(1)},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind + ret void +} + +; One input, two outputs, one dead output. +%complex = type { float, float } +; CHECK: sincos1 +; CHECK: flds +; CHECK-NOT: fxch +; CHECK: sincos +; CHECK-NOT: fstp +; CHECK: fstp %st(1) +; CHECK-NOT: fstp +; CHECK: ret +define float @sincos1(float %x) nounwind ssp { +entry: + %0 = tail call %complex asm "sincos", "={st},={st(1)},0,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind + %asmresult = extractvalue %complex %0, 0 + ret float %asmresult +} + +; Same thing, swapped output operands. +; CHECK: sincos2 +; CHECK: flds +; CHECK-NOT: fxch +; CHECK: sincos +; CHECK-NOT: fstp +; CHECK: fstp %st(1) +; CHECK-NOT: fstp +; CHECK: ret +define float @sincos2(float %x) nounwind ssp { +entry: + %0 = tail call %complex asm "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind + %asmresult = extractvalue %complex %0, 1 + ret float %asmresult +} + +; Clobber st(0) after it was live-out/dead from the previous asm. +; CHECK: sincos3 +; Load x, make a copy for the second asm. +; CHECK: flds +; CHECK: fld %st(0) +; CHECK: sincos +; Discard dead result in st(0), bring x to the top. +; CHECK: fstp %st(0) +; CHECK: fxch +; x is now in st(0) for the second asm +; CHECK: sincos +; Discard both results. +; CHECK: fstp +; CHECK: fstp +; CHECK: ret +define float @sincos3(float %x) nounwind ssp { +entry: + %0 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind + %1 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind + %asmresult = extractvalue %complex %0, 0 + ret float %asmresult +} From rafael.espindola at gmail.com Tue Jun 28 13:35:45 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 28 Jun 2011 14:35:45 -0400 Subject: [llvm-commits] ideas for 10096 Message-ID: <4E0A1F01.6090408@gmail.com> I am trying to fix 10203 and currently I have three ideas of how it might be fixed: *) Fix bit rot on the strong phi elimination. IT currently crashes when building firefox. *) A simple preprocessioning pass that would try to convert %vreg40 = COPY %vreg45 %vreg42 = COPY %vreg45 to %vreg40 = COPY %vreg45 %vreg42 = COPY %vreg40 That is, try to use in the RHS values that have been defined in the same bb. * The third idea (which I like a bit more right now) is to change the coalescer itself Right now it works in three stages if I understand it correctly. 1) it collects which value numbers of A are copies of B and B of A. 2) It then optimistically merges the intervals, by first copying the LHS and then the RHS with exceptions for the A=B and B=A cases. 3) It now walks the ranges of both registers looking for overlapping ones. If it finds one, it checks if both have the same value number in the new merged interval. I think this can be done in one pass. As we walk the ranges, we can find the value numbers and check if they are compatible. Doing this in one pass then has the advantage that it is easy to add support for the case we have in the bug. In this case, the dominance check can be as simple an "defined earlier in the same bb". So, do you agree with the third option being the best or would a preprocess pass (or fixing the strong phi elimination) be better? Cheers, Rafael From evan.cheng at apple.com Tue Jun 28 14:10:37 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 28 Jun 2011 19:10:37 -0000 Subject: [llvm-commits] [llvm] r134021 - in /llvm/trunk: include/llvm/CodeGen/ include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/ lib/Target/ARM/ lib/Target/ARM/Disassembler/ lib/Target/Blackfin/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ utils/TableGen/ Message-ID: <20110628191038.A852E2A6C12C@llvm.org> Author: evancheng Date: Tue Jun 28 14:10:37 2011 New Revision: 134021 URL: http://llvm.org/viewvc/llvm-project?rev=134021&view=rev Log: - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. Added: llvm/trunk/include/llvm/MC/MCInstrDesc.h llvm/trunk/include/llvm/MC/MCInstrInfo.h Removed: llvm/trunk/include/llvm/Target/TargetInstrDesc.h Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h llvm/trunk/include/llvm/CodeGen/MachineInstr.h llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h llvm/trunk/include/llvm/CodeGen/ScoreboardHazardRecognizer.h llvm/trunk/include/llvm/MC/MCRegisterInfo.h llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/CodeGen/BranchFolding.cpp llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp llvm/trunk/lib/CodeGen/IfConversion.cpp llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp llvm/trunk/lib/CodeGen/MachineCSE.cpp llvm/trunk/lib/CodeGen/MachineFunction.cpp llvm/trunk/lib/CodeGen/MachineInstr.cpp llvm/trunk/lib/CodeGen/MachineLICM.cpp llvm/trunk/lib/CodeGen/MachineVerifier.cpp llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp llvm/trunk/lib/CodeGen/RegAllocFast.cpp llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp llvm/trunk/lib/CodeGen/ScheduleDAG.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp llvm/trunk/lib/CodeGen/StackSlotColoring.cpp llvm/trunk/lib/CodeGen/TailDuplication.cpp llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp llvm/trunk/lib/Target/Mips/MipsExpandPseudo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp llvm/trunk/lib/Target/SystemZ/SystemZInstrBuilder.h llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h llvm/trunk/lib/Target/TargetInstrInfo.cpp llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Target/X86/X86InstrBuilder.h llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp llvm/trunk/utils/TableGen/InstrInfoEmitter.h Modified: llvm/trunk/include/llvm/CodeGen/MachineFunction.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineFunction.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineFunction.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h Tue Jun 28 14:10:37 2011 @@ -345,7 +345,7 @@ /// CreateMachineInstr - Allocate a new MachineInstr. Use this instead /// of `new MachineInstr'. /// - MachineInstr *CreateMachineInstr(const TargetInstrDesc &TID, + MachineInstr *CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImp = false); Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Tue Jun 28 14:10:37 2011 @@ -17,7 +17,7 @@ #define LLVM_CODEGEN_MACHINEINSTR_H #include "llvm/CodeGen/MachineOperand.h" -#include "llvm/Target/TargetInstrDesc.h" +#include "llvm/MC/MCInstrDesc.h" #include "llvm/Target/TargetOpcodes.h" #include "llvm/ADT/ilist.h" #include "llvm/ADT/ilist_node.h" @@ -30,7 +30,6 @@ template class SmallVectorImpl; class AliasAnalysis; -class TargetInstrDesc; class TargetInstrInfo; class TargetRegisterInfo; class MachineFunction; @@ -57,7 +56,7 @@ // function frame setup code. }; private: - const TargetInstrDesc *TID; // Instruction descriptor. + const MCInstrDesc *MCID; // Instruction descriptor. uint16_t NumImplicitOps; // Number of implicit operands (which // are determined at construction time). @@ -94,7 +93,7 @@ MachineInstr(MachineFunction &, const MachineInstr &); /// MachineInstr ctor - This constructor creates a dummy MachineInstr with - /// TID NULL and no operands. + /// MCID NULL and no operands. MachineInstr(); // The next two constructors have DebugLoc and non-DebugLoc versions; @@ -103,25 +102,25 @@ /// MachineInstr ctor - This constructor creates a MachineInstr and adds the /// implicit operands. It reserves space for the number of operands specified - /// by the TargetInstrDesc. The version with a DebugLoc should be preferred. - explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false); + /// by the MCInstrDesc. The version with a DebugLoc should be preferred. + explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false); /// MachineInstr ctor - Work exactly the same as the ctor above, except that /// the MachineInstr is created and added to the end of the specified basic /// block. The version with a DebugLoc should be preferred. - MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID); + MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID); /// MachineInstr ctor - This constructor create a MachineInstr and add the /// implicit operands. It reserves space for number of operands specified by - /// TargetInstrDesc. An explicit DebugLoc is supplied. - explicit MachineInstr(const TargetInstrDesc &TID, const DebugLoc dl, + /// MCInstrDesc. An explicit DebugLoc is supplied. + explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl, bool NoImp = false); /// MachineInstr ctor - Work exactly the same as the ctor above, except that /// the MachineInstr is created and added to the end of the specified basic /// block. MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, - const TargetInstrDesc &TID); + const MCInstrDesc &MCID); ~MachineInstr(); @@ -183,11 +182,11 @@ /// getDesc - Returns the target instruction descriptor of this /// MachineInstr. - const TargetInstrDesc &getDesc() const { return *TID; } + const MCInstrDesc &getDesc() const { return *MCID; } /// getOpcode - Returns the opcode of this MachineInstr. /// - int getOpcode() const { return TID->Opcode; } + int getOpcode() const { return MCID->Opcode; } /// Access to explicit operands of the instruction. /// @@ -464,8 +463,8 @@ /// hasUnmodeledSideEffects - Return true if this instruction has side /// effects that are not modeled by mayLoad / mayStore, etc. - /// For all instructions, the property is encoded in TargetInstrDesc::Flags - /// (see TargetInstrDesc::hasUnmodeledSideEffects(). The only exception is + /// For all instructions, the property is encoded in MCInstrDesc::Flags + /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is /// INLINEASM instruction, in which case the side effect property is encoded /// in one of its operands (see InlineAsm::Extra_HasSideEffect). /// @@ -497,7 +496,7 @@ /// setDesc - Replace the instruction descriptor (thus opcode) of /// the current instruction with a new one. /// - void setDesc(const TargetInstrDesc &tid) { TID = &tid; } + void setDesc(const MCInstrDesc &tid) { MCID = &tid; } /// setDebugLoc - Replace current source information with new such. /// Avoid using this, the constructor argument is preferable. Modified: llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h (original) +++ llvm/trunk/include/llvm/CodeGen/MachineInstrBuilder.h Tue Jun 28 14:10:37 2011 @@ -22,7 +22,7 @@ namespace llvm { -class TargetInstrDesc; +class MCInstrDesc; class MDNode; namespace RegState { @@ -180,8 +180,8 @@ /// inline MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, - const TargetInstrDesc &TID) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL)); + const MCInstrDesc &MCID) { + return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL)); } /// BuildMI - This version of the builder sets up the first operand as a @@ -189,9 +189,9 @@ /// inline MachineInstrBuilder BuildMI(MachineFunction &MF, DebugLoc DL, - const TargetInstrDesc &TID, + const MCInstrDesc &MCID, unsigned DestReg) { - return MachineInstrBuilder(MF.CreateMachineInstr(TID, DL)) + return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL)) .addReg(DestReg, RegState::Define); } @@ -202,9 +202,9 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, - const TargetInstrDesc &TID, + const MCInstrDesc &MCID, unsigned DestReg) { - MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL); + MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL); BB.insert(I, MI); return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define); } @@ -216,8 +216,8 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineBasicBlock::iterator I, DebugLoc DL, - const TargetInstrDesc &TID) { - MachineInstr *MI = BB.getParent()->CreateMachineInstr(TID, DL); + const MCInstrDesc &MCID) { + MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL); BB.insert(I, MI); return MachineInstrBuilder(MI); } @@ -228,8 +228,8 @@ /// inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, DebugLoc DL, - const TargetInstrDesc &TID) { - return BuildMI(*BB, BB->end(), DL, TID); + const MCInstrDesc &MCID) { + return BuildMI(*BB, BB->end(), DL, MCID); } /// BuildMI - This version of the builder inserts the newly-built @@ -238,9 +238,9 @@ /// inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, DebugLoc DL, - const TargetInstrDesc &TID, + const MCInstrDesc &MCID, unsigned DestReg) { - return BuildMI(*BB, BB->end(), DL, TID, DestReg); + return BuildMI(*BB, BB->end(), DL, MCID, DestReg); } inline unsigned getDefRegState(bool B) { Modified: llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h (original) +++ llvm/trunk/include/llvm/CodeGen/ScheduleDAG.h Tue Jun 28 14:10:37 2011 @@ -34,7 +34,7 @@ class ScheduleDAG; class SDNode; class TargetInstrInfo; - class TargetInstrDesc; + class MCInstrDesc; class TargetMachine; class TargetRegisterClass; template class GraphWriter; @@ -507,9 +507,9 @@ virtual ~ScheduleDAG(); - /// getInstrDesc - Return the TargetInstrDesc of this SUnit. + /// getInstrDesc - Return the MCInstrDesc of this SUnit. /// Return NULL for SDNodes without a machine opcode. - const TargetInstrDesc *getInstrDesc(const SUnit *SU) const { + const MCInstrDesc *getInstrDesc(const SUnit *SU) const { if (SU->isInstr()) return &SU->getInstr()->getDesc(); return getNodeDesc(SU->getNode()); } @@ -579,8 +579,8 @@ void EmitPhysRegCopy(SUnit *SU, DenseMap &VRBaseMap); private: - // Return the TargetInstrDesc of this SDNode or NULL. - const TargetInstrDesc *getNodeDesc(const SDNode *Node) const; + // Return the MCInstrDesc of this SDNode or NULL. + const MCInstrDesc *getNodeDesc(const SDNode *Node) const; }; class SUnitIterator : public std::iterator> Pos) & 0xf; + } + return -1; + } + + /// getOpcode - Return the opcode number for this descriptor. + unsigned getOpcode() const { + return Opcode; + } + + /// getName - Return the name of the record in the .td file for this + /// instruction, for example "ADD8ri". + const char *getName() const { + return Name; + } + + /// getNumOperands - Return the number of declared MachineOperands for this + /// MachineInstruction. Note that variadic (isVariadic() returns true) + /// instructions may have additional operands at the end of the list, and note + /// that the machine instruction may include implicit register def/uses as + /// well. + unsigned getNumOperands() const { + return NumOperands; + } + + /// getNumDefs - Return the number of MachineOperands that are register + /// definitions. Register definitions always occur at the start of the + /// machine operand list. This is the number of "outs" in the .td file, + /// and does not include implicit defs. + unsigned getNumDefs() const { + return NumDefs; + } + + /// isVariadic - Return true if this instruction can have a variable number of + /// operands. In this case, the variable operands will be after the normal + /// operands but before the implicit definitions and uses (if any are + /// present). + bool isVariadic() const { + return Flags & (1 << MCID::Variadic); + } + + /// hasOptionalDef - Set if this instruction has an optional definition, e.g. + /// ARM instructions which can set condition code if 's' bit is set. + bool hasOptionalDef() const { + return Flags & (1 << MCID::HasOptionalDef); + } + + /// getImplicitUses - Return a list of registers that are potentially + /// read by any instance of this machine instruction. For example, on X86, + /// the "adc" instruction adds two register operands and adds the carry bit in + /// from the flags register. In this case, the instruction is marked as + /// implicitly reading the flags. Likewise, the variable shift instruction on + /// X86 is marked as implicitly reading the 'CL' register, which it always + /// does. + /// + /// This method returns null if the instruction has no implicit uses. + const unsigned *getImplicitUses() const { + return ImplicitUses; + } + + /// getNumImplicitUses - Return the number of implicit uses this instruction + /// has. + unsigned getNumImplicitUses() const { + if (ImplicitUses == 0) return 0; + unsigned i = 0; + for (; ImplicitUses[i]; ++i) /*empty*/; + return i; + } + + /// getImplicitDefs - Return a list of registers that are potentially + /// written by any instance of this machine instruction. For example, on X86, + /// many instructions implicitly set the flags register. In this case, they + /// are marked as setting the FLAGS. Likewise, many instructions always + /// deposit their result in a physical register. For example, the X86 divide + /// instruction always deposits the quotient and remainder in the EAX/EDX + /// registers. For that instruction, this will return a list containing the + /// EAX/EDX/EFLAGS registers. + /// + /// This method returns null if the instruction has no implicit defs. + const unsigned *getImplicitDefs() const { + return ImplicitDefs; + } + + /// getNumImplicitDefs - Return the number of implicit defs this instruction + /// has. + unsigned getNumImplicitDefs() const { + if (ImplicitDefs == 0) return 0; + unsigned i = 0; + for (; ImplicitDefs[i]; ++i) /*empty*/; + return i; + } + + /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly + /// uses the specified physical register. + bool hasImplicitUseOfPhysReg(unsigned Reg) const { + if (const unsigned *ImpUses = ImplicitUses) + for (; *ImpUses; ++ImpUses) + if (*ImpUses == Reg) return true; + return false; + } + + /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly + /// defines the specified physical register. + bool hasImplicitDefOfPhysReg(unsigned Reg) const { + if (const unsigned *ImpDefs = ImplicitDefs) + for (; *ImpDefs; ++ImpDefs) + if (*ImpDefs == Reg) return true; + return false; + } + + /// getSchedClass - Return the scheduling class for this instruction. The + /// scheduling class is an index into the InstrItineraryData table. This + /// returns zero if there is no known scheduling information for the + /// instruction. + /// + unsigned getSchedClass() const { + return SchedClass; + } + + bool isReturn() const { + return Flags & (1 << MCID::Return); + } + + bool isCall() const { + return Flags & (1 << MCID::Call); + } + + /// isBarrier - Returns true if the specified instruction stops control flow + /// from executing the instruction immediately following it. Examples include + /// unconditional branches and return instructions. + bool isBarrier() const { + return Flags & (1 << MCID::Barrier); + } + + /// isTerminator - Returns true if this instruction part of the terminator for + /// a basic block. Typically this is things like return and branch + /// instructions. + /// + /// Various passes use this to insert code into the bottom of a basic block, + /// but before control flow occurs. + bool isTerminator() const { + return Flags & (1 << MCID::Terminator); + } + + /// isBranch - Returns true if this is a conditional, unconditional, or + /// indirect branch. Predicates below can be used to discriminate between + /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to + /// get more information. + bool isBranch() const { + return Flags & (1 << MCID::Branch); + } + + /// isIndirectBranch - Return true if this is an indirect branch, such as a + /// branch through a register. + bool isIndirectBranch() const { + return Flags & (1 << MCID::IndirectBranch); + } + + /// isConditionalBranch - Return true if this is a branch which may fall + /// through to the next instruction or may transfer control flow to some other + /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more + /// information about this branch. + bool isConditionalBranch() const { + return isBranch() & !isBarrier() & !isIndirectBranch(); + } + + /// isUnconditionalBranch - Return true if this is a branch which always + /// transfers control flow to some other block. The + /// TargetInstrInfo::AnalyzeBranch method can be used to get more information + /// about this branch. + bool isUnconditionalBranch() const { + return isBranch() & isBarrier() & !isIndirectBranch(); + } + + // isPredicable - Return true if this instruction has a predicate operand that + // controls execution. It may be set to 'always', or may be set to other + /// values. There are various methods in TargetInstrInfo that can be used to + /// control and modify the predicate in this instruction. + bool isPredicable() const { + return Flags & (1 << MCID::Predicable); + } + + /// isCompare - Return true if this instruction is a comparison. + bool isCompare() const { + return Flags & (1 << MCID::Compare); + } + + /// isMoveImmediate - Return true if this instruction is a move immediate + /// (including conditional moves) instruction. + bool isMoveImmediate() const { + return Flags & (1 << MCID::MoveImm); + } + + /// isBitcast - Return true if this instruction is a bitcast instruction. + /// + bool isBitcast() const { + return Flags & (1 << MCID::Bitcast); + } + + /// isNotDuplicable - Return true if this instruction cannot be safely + /// duplicated. For example, if the instruction has a unique labels attached + /// to it, duplicating it would cause multiple definition errors. + bool isNotDuplicable() const { + return Flags & (1 << MCID::NotDuplicable); + } + + /// hasDelaySlot - Returns true if the specified instruction has a delay slot + /// which must be filled by the code generator. + bool hasDelaySlot() const { + return Flags & (1 << MCID::DelaySlot); + } + + /// canFoldAsLoad - Return true for instructions that can be folded as + /// memory operands in other instructions. The most common use for this + /// is instructions that are simple loads from memory that don't modify + /// the loaded value in any way, but it can also be used for instructions + /// that can be expressed as constant-pool loads, such as V_SETALLONES + /// on x86, to allow them to be folded when it is beneficial. + /// This should only be set on instructions that return a value in their + /// only virtual register definition. + bool canFoldAsLoad() const { + return Flags & (1 << MCID::FoldableAsLoad); + } + + //===--------------------------------------------------------------------===// + // Side Effect Analysis + //===--------------------------------------------------------------------===// + + /// mayLoad - Return true if this instruction could possibly read memory. + /// Instructions with this flag set are not necessarily simple load + /// instructions, they may load a value and modify it, for example. + bool mayLoad() const { + return Flags & (1 << MCID::MayLoad); + } + + + /// mayStore - Return true if this instruction could possibly modify memory. + /// Instructions with this flag set are not necessarily simple store + /// instructions, they may store a modified value based on their operands, or + /// may not actually modify anything, for example. + bool mayStore() const { + return Flags & (1 << MCID::MayStore); + } + + /// hasUnmodeledSideEffects - Return true if this instruction has side + /// effects that are not modeled by other flags. This does not return true + /// for instructions whose effects are captured by: + /// + /// 1. Their operand list and implicit definition/use list. Register use/def + /// info is explicit for instructions. + /// 2. Memory accesses. Use mayLoad/mayStore. + /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. + /// + /// Examples of side effects would be modifying 'invisible' machine state like + /// a control register, flushing a cache, modifying a register invisible to + /// LLVM, etc. + /// + bool hasUnmodeledSideEffects() const { + return Flags & (1 << MCID::UnmodeledSideEffects); + } + + //===--------------------------------------------------------------------===// + // Flags that indicate whether an instruction can be modified by a method. + //===--------------------------------------------------------------------===// + + /// isCommutable - Return true if this may be a 2- or 3-address + /// instruction (of the form "X = op Y, Z, ..."), which produces the same + /// result if Y and Z are exchanged. If this flag is set, then the + /// TargetInstrInfo::commuteInstruction method may be used to hack on the + /// instruction. + /// + /// Note that this flag may be set on instructions that are only commutable + /// sometimes. In these cases, the call to commuteInstruction will fail. + /// Also note that some instructions require non-trivial modification to + /// commute them. + bool isCommutable() const { + return Flags & (1 << MCID::Commutable); + } + + /// isConvertibleTo3Addr - Return true if this is a 2-address instruction + /// which can be changed into a 3-address instruction if needed. Doing this + /// transformation can be profitable in the register allocator, because it + /// means that the instruction can use a 2-address form if possible, but + /// degrade into a less efficient form if the source and dest register cannot + /// be assigned to the same register. For example, this allows the x86 + /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which + /// is the same speed as the shift but has bigger code size. + /// + /// If this returns true, then the target must implement the + /// TargetInstrInfo::convertToThreeAddress method for this instruction, which + /// is allowed to fail if the transformation isn't valid for this specific + /// instruction (e.g. shl reg, 4 on x86). + /// + bool isConvertibleTo3Addr() const { + return Flags & (1 << MCID::ConvertibleTo3Addr); + } + + /// usesCustomInsertionHook - Return true if this instruction requires + /// custom insertion support when the DAG scheduler is inserting it into a + /// machine basic block. If this is true for the instruction, it basically + /// means that it is a pseudo instruction used at SelectionDAG time that is + /// expanded out into magic code by the target when MachineInstrs are formed. + /// + /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method + /// is used to insert this into the MachineBasicBlock. + bool usesCustomInsertionHook() const { + return Flags & (1 << MCID::UsesCustomInserter); + } + + /// isRematerializable - Returns true if this instruction is a candidate for + /// remat. This flag is deprecated, please don't use it anymore. If this + /// flag is set, the isReallyTriviallyReMaterializable() method is called to + /// verify the instruction is really rematable. + bool isRematerializable() const { + return Flags & (1 << MCID::Rematerializable); + } + + /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or + /// less) than a move instruction. This is useful during certain types of + /// optimizations (e.g., remat during two-address conversion or machine licm) + /// where we would like to remat or hoist the instruction, but not if it costs + /// more than moving the instruction into the appropriate register. Note, we + /// are not marking copies from and to the same register class with this flag. + bool isAsCheapAsAMove() const { + return Flags & (1 << MCID::CheapAsAMove); + } + + /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands + /// have special register allocation requirements that are not captured by the + /// operand register classes. e.g. ARM::STRD's two source registers must be an + /// even / odd pair, ARM::STM registers have to be in ascending order. + /// Post-register allocation passes should not attempt to change allocations + /// for sources of instructions with this flag. + bool hasExtraSrcRegAllocReq() const { + return Flags & (1 << MCID::ExtraSrcRegAllocReq); + } + + /// hasExtraDefRegAllocReq - Returns true if this instruction def operands + /// have special register allocation requirements that are not captured by the + /// operand register classes. e.g. ARM::LDRD's two def registers must be an + /// even / odd pair, ARM::LDM registers have to be in ascending order. + /// Post-register allocation passes should not attempt to change allocations + /// for definitions of instructions with this flag. + bool hasExtraDefRegAllocReq() const { + return Flags & (1 << MCID::ExtraDefRegAllocReq); + } +}; + +} // end namespace llvm + +#endif Added: llvm/trunk/include/llvm/MC/MCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrInfo.h?rev=134021&view=auto ============================================================================== --- llvm/trunk/include/llvm/MC/MCInstrInfo.h (added) +++ llvm/trunk/include/llvm/MC/MCInstrInfo.h Tue Jun 28 14:10:37 2011 @@ -0,0 +1,51 @@ +//===-- llvm/MC/MCInstrInfo.h - Target Instruction Info ---------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes the target machine instruction set. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_MC_MCINSTRINFO_H +#define LLVM_MC_MCINSTRINFO_H + +#include "llvm/MC/MCInstrDesc.h" +#include + +namespace llvm { + +//--------------------------------------------------------------------------- +/// +/// MCInstrInfo - Interface to description of machine instruction set +/// +class MCInstrInfo { + const MCInstrDesc *Desc; // Raw array to allow static init'n + unsigned NumOpcodes; // Number of entries in the desc array + +public: + /// InitMCInstrInfo - Initialize MCInstrInfo, called by TableGen + /// auto-generated routines. *DO NOT USE*. + void InitMCInstrInfo(const MCInstrDesc *D, unsigned NO) { + Desc = D; + NumOpcodes = NO; + } + + unsigned getNumOpcodes() const { return NumOpcodes; } + + /// get - Return the machine instruction descriptor that corresponds to the + /// specified instruction opcode. + /// + const MCInstrDesc &get(unsigned Opcode) const { + assert(Opcode < NumOpcodes && "Invalid opcode!"); + return Desc[Opcode]; + } +}; + +} // End llvm namespace + +#endif Modified: llvm/trunk/include/llvm/MC/MCRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCRegisterInfo.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCRegisterInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCRegisterInfo.h Tue Jun 28 14:10:37 2011 @@ -52,7 +52,7 @@ class MCRegisterInfo { private: const MCRegisterDesc *Desc; // Pointer to the descriptor array - unsigned NumRegs; // Number of entries in the array + unsigned NumRegs; // Number of entries in the array public: /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen Removed: llvm/trunk/include/llvm/Target/TargetInstrDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrDesc.h?rev=134020&view=auto ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrDesc.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrDesc.h (removed) @@ -1,493 +0,0 @@ -//===-- llvm/Target/TargetInstrDesc.h - Instruction Descriptors -*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines the TargetOperandInfo and TargetInstrDesc classes, which -// are used to describe target instructions and their operands. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TARGET_TARGETINSTRDESC_H -#define LLVM_TARGET_TARGETINSTRDESC_H - -#include "llvm/Support/DataTypes.h" - -namespace llvm { - -class TargetRegisterClass; -class TargetRegisterInfo; - -//===----------------------------------------------------------------------===// -// Machine Operand Flags and Description -//===----------------------------------------------------------------------===// - -namespace TOI { - // Operand constraints - enum OperandConstraint { - TIED_TO = 0, // Must be allocated the same register as. - EARLY_CLOBBER // Operand is an early clobber register operand - }; - - /// OperandFlags - These are flags set on operands, but should be considered - /// private, all access should go through the TargetOperandInfo accessors. - /// See the accessors for a description of what these are. - enum OperandFlags { - LookupPtrRegClass = 0, - Predicate, - OptionalDef - }; -} - -/// TargetOperandInfo - This holds information about one operand of a machine -/// instruction, indicating the register class for register operands, etc. -/// -class TargetOperandInfo { -public: - /// RegClass - This specifies the register class enumeration of the operand - /// if the operand is a register. If isLookupPtrRegClass is set, then this is - /// an index that is passed to TargetRegisterInfo::getPointerRegClass(x) to - /// get a dynamic register class. - short RegClass; - - /// Flags - These are flags from the TOI::OperandFlags enum. - unsigned short Flags; - - /// Lower 16 bits are used to specify which constraints are set. The higher 16 - /// bits are used to specify the value of constraints (4 bits each). - unsigned Constraints; - /// Currently no other information. - - /// isLookupPtrRegClass - Set if this operand is a pointer value and it - /// requires a callback to look up its register class. - bool isLookupPtrRegClass() const { return Flags&(1 <> Pos) & 0xf; - } - return -1; - } - - /// getOpcode - Return the opcode number for this descriptor. - unsigned getOpcode() const { - return Opcode; - } - - /// getName - Return the name of the record in the .td file for this - /// instruction, for example "ADD8ri". - const char *getName() const { - return Name; - } - - /// getNumOperands - Return the number of declared MachineOperands for this - /// MachineInstruction. Note that variadic (isVariadic() returns true) - /// instructions may have additional operands at the end of the list, and note - /// that the machine instruction may include implicit register def/uses as - /// well. - unsigned getNumOperands() const { - return NumOperands; - } - - /// getNumDefs - Return the number of MachineOperands that are register - /// definitions. Register definitions always occur at the start of the - /// machine operand list. This is the number of "outs" in the .td file, - /// and does not include implicit defs. - unsigned getNumDefs() const { - return NumDefs; - } - - /// isVariadic - Return true if this instruction can have a variable number of - /// operands. In this case, the variable operands will be after the normal - /// operands but before the implicit definitions and uses (if any are - /// present). - bool isVariadic() const { - return Flags & (1 << TID::Variadic); - } - - /// hasOptionalDef - Set if this instruction has an optional definition, e.g. - /// ARM instructions which can set condition code if 's' bit is set. - bool hasOptionalDef() const { - return Flags & (1 << TID::HasOptionalDef); - } - - /// getImplicitUses - Return a list of registers that are potentially - /// read by any instance of this machine instruction. For example, on X86, - /// the "adc" instruction adds two register operands and adds the carry bit in - /// from the flags register. In this case, the instruction is marked as - /// implicitly reading the flags. Likewise, the variable shift instruction on - /// X86 is marked as implicitly reading the 'CL' register, which it always - /// does. - /// - /// This method returns null if the instruction has no implicit uses. - const unsigned *getImplicitUses() const { - return ImplicitUses; - } - - /// getNumImplicitUses - Return the number of implicit uses this instruction - /// has. - unsigned getNumImplicitUses() const { - if (ImplicitUses == 0) return 0; - unsigned i = 0; - for (; ImplicitUses[i]; ++i) /*empty*/; - return i; - } - - - /// getImplicitDefs - Return a list of registers that are potentially - /// written by any instance of this machine instruction. For example, on X86, - /// many instructions implicitly set the flags register. In this case, they - /// are marked as setting the FLAGS. Likewise, many instructions always - /// deposit their result in a physical register. For example, the X86 divide - /// instruction always deposits the quotient and remainder in the EAX/EDX - /// registers. For that instruction, this will return a list containing the - /// EAX/EDX/EFLAGS registers. - /// - /// This method returns null if the instruction has no implicit defs. - const unsigned *getImplicitDefs() const { - return ImplicitDefs; - } - - /// getNumImplicitDefs - Return the number of implicit defs this instruction - /// has. - unsigned getNumImplicitDefs() const { - if (ImplicitDefs == 0) return 0; - unsigned i = 0; - for (; ImplicitDefs[i]; ++i) /*empty*/; - return i; - } - - /// hasImplicitUseOfPhysReg - Return true if this instruction implicitly - /// uses the specified physical register. - bool hasImplicitUseOfPhysReg(unsigned Reg) const { - if (const unsigned *ImpUses = ImplicitUses) - for (; *ImpUses; ++ImpUses) - if (*ImpUses == Reg) return true; - return false; - } - - /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly - /// defines the specified physical register. - bool hasImplicitDefOfPhysReg(unsigned Reg) const { - if (const unsigned *ImpDefs = ImplicitDefs) - for (; *ImpDefs; ++ImpDefs) - if (*ImpDefs == Reg) return true; - return false; - } - - /// getSchedClass - Return the scheduling class for this instruction. The - /// scheduling class is an index into the InstrItineraryData table. This - /// returns zero if there is no known scheduling information for the - /// instruction. - /// - unsigned getSchedClass() const { - return SchedClass; - } - - bool isReturn() const { - return Flags & (1 << TID::Return); - } - - bool isCall() const { - return Flags & (1 << TID::Call); - } - - /// isBarrier - Returns true if the specified instruction stops control flow - /// from executing the instruction immediately following it. Examples include - /// unconditional branches and return instructions. - bool isBarrier() const { - return Flags & (1 << TID::Barrier); - } - - /// isTerminator - Returns true if this instruction part of the terminator for - /// a basic block. Typically this is things like return and branch - /// instructions. - /// - /// Various passes use this to insert code into the bottom of a basic block, - /// but before control flow occurs. - bool isTerminator() const { - return Flags & (1 << TID::Terminator); - } - - /// isBranch - Returns true if this is a conditional, unconditional, or - /// indirect branch. Predicates below can be used to discriminate between - /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to - /// get more information. - bool isBranch() const { - return Flags & (1 << TID::Branch); - } - - /// isIndirectBranch - Return true if this is an indirect branch, such as a - /// branch through a register. - bool isIndirectBranch() const { - return Flags & (1 << TID::IndirectBranch); - } - - /// isConditionalBranch - Return true if this is a branch which may fall - /// through to the next instruction or may transfer control flow to some other - /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more - /// information about this branch. - bool isConditionalBranch() const { - return isBranch() & !isBarrier() & !isIndirectBranch(); - } - - /// isUnconditionalBranch - Return true if this is a branch which always - /// transfers control flow to some other block. The - /// TargetInstrInfo::AnalyzeBranch method can be used to get more information - /// about this branch. - bool isUnconditionalBranch() const { - return isBranch() & isBarrier() & !isIndirectBranch(); - } - - // isPredicable - Return true if this instruction has a predicate operand that - // controls execution. It may be set to 'always', or may be set to other - /// values. There are various methods in TargetInstrInfo that can be used to - /// control and modify the predicate in this instruction. - bool isPredicable() const { - return Flags & (1 << TID::Predicable); - } - - /// isCompare - Return true if this instruction is a comparison. - bool isCompare() const { - return Flags & (1 << TID::Compare); - } - - /// isMoveImmediate - Return true if this instruction is a move immediate - /// (including conditional moves) instruction. - bool isMoveImmediate() const { - return Flags & (1 << TID::MoveImm); - } - - /// isBitcast - Return true if this instruction is a bitcast instruction. - /// - bool isBitcast() const { - return Flags & (1 << TID::Bitcast); - } - - /// isNotDuplicable - Return true if this instruction cannot be safely - /// duplicated. For example, if the instruction has a unique labels attached - /// to it, duplicating it would cause multiple definition errors. - bool isNotDuplicable() const { - return Flags & (1 << TID::NotDuplicable); - } - - /// hasDelaySlot - Returns true if the specified instruction has a delay slot - /// which must be filled by the code generator. - bool hasDelaySlot() const { - return Flags & (1 << TID::DelaySlot); - } - - /// canFoldAsLoad - Return true for instructions that can be folded as - /// memory operands in other instructions. The most common use for this - /// is instructions that are simple loads from memory that don't modify - /// the loaded value in any way, but it can also be used for instructions - /// that can be expressed as constant-pool loads, such as V_SETALLONES - /// on x86, to allow them to be folded when it is beneficial. - /// This should only be set on instructions that return a value in their - /// only virtual register definition. - bool canFoldAsLoad() const { - return Flags & (1 << TID::FoldableAsLoad); - } - - //===--------------------------------------------------------------------===// - // Side Effect Analysis - //===--------------------------------------------------------------------===// - - /// mayLoad - Return true if this instruction could possibly read memory. - /// Instructions with this flag set are not necessarily simple load - /// instructions, they may load a value and modify it, for example. - bool mayLoad() const { - return Flags & (1 << TID::MayLoad); - } - - - /// mayStore - Return true if this instruction could possibly modify memory. - /// Instructions with this flag set are not necessarily simple store - /// instructions, they may store a modified value based on their operands, or - /// may not actually modify anything, for example. - bool mayStore() const { - return Flags & (1 << TID::MayStore); - } - - /// hasUnmodeledSideEffects - Return true if this instruction has side - /// effects that are not modeled by other flags. This does not return true - /// for instructions whose effects are captured by: - /// - /// 1. Their operand list and implicit definition/use list. Register use/def - /// info is explicit for instructions. - /// 2. Memory accesses. Use mayLoad/mayStore. - /// 3. Calling, branching, returning: use isCall/isReturn/isBranch. - /// - /// Examples of side effects would be modifying 'invisible' machine state like - /// a control register, flushing a cache, modifying a register invisible to - /// LLVM, etc. - /// - bool hasUnmodeledSideEffects() const { - return Flags & (1 << TID::UnmodeledSideEffects); - } - - //===--------------------------------------------------------------------===// - // Flags that indicate whether an instruction can be modified by a method. - //===--------------------------------------------------------------------===// - - /// isCommutable - Return true if this may be a 2- or 3-address - /// instruction (of the form "X = op Y, Z, ..."), which produces the same - /// result if Y and Z are exchanged. If this flag is set, then the - /// TargetInstrInfo::commuteInstruction method may be used to hack on the - /// instruction. - /// - /// Note that this flag may be set on instructions that are only commutable - /// sometimes. In these cases, the call to commuteInstruction will fail. - /// Also note that some instructions require non-trivial modification to - /// commute them. - bool isCommutable() const { - return Flags & (1 << TID::Commutable); - } - - /// isConvertibleTo3Addr - Return true if this is a 2-address instruction - /// which can be changed into a 3-address instruction if needed. Doing this - /// transformation can be profitable in the register allocator, because it - /// means that the instruction can use a 2-address form if possible, but - /// degrade into a less efficient form if the source and dest register cannot - /// be assigned to the same register. For example, this allows the x86 - /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which - /// is the same speed as the shift but has bigger code size. - /// - /// If this returns true, then the target must implement the - /// TargetInstrInfo::convertToThreeAddress method for this instruction, which - /// is allowed to fail if the transformation isn't valid for this specific - /// instruction (e.g. shl reg, 4 on x86). - /// - bool isConvertibleTo3Addr() const { - return Flags & (1 << TID::ConvertibleTo3Addr); - } - - /// usesCustomInsertionHook - Return true if this instruction requires - /// custom insertion support when the DAG scheduler is inserting it into a - /// machine basic block. If this is true for the instruction, it basically - /// means that it is a pseudo instruction used at SelectionDAG time that is - /// expanded out into magic code by the target when MachineInstrs are formed. - /// - /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method - /// is used to insert this into the MachineBasicBlock. - bool usesCustomInsertionHook() const { - return Flags & (1 << TID::UsesCustomInserter); - } - - /// isRematerializable - Returns true if this instruction is a candidate for - /// remat. This flag is deprecated, please don't use it anymore. If this - /// flag is set, the isReallyTriviallyReMaterializable() method is called to - /// verify the instruction is really rematable. - bool isRematerializable() const { - return Flags & (1 << TID::Rematerializable); - } - - /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or - /// less) than a move instruction. This is useful during certain types of - /// optimizations (e.g., remat during two-address conversion or machine licm) - /// where we would like to remat or hoist the instruction, but not if it costs - /// more than moving the instruction into the appropriate register. Note, we - /// are not marking copies from and to the same register class with this flag. - bool isAsCheapAsAMove() const { - return Flags & (1 << TID::CheapAsAMove); - } - - /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands - /// have special register allocation requirements that are not captured by the - /// operand register classes. e.g. ARM::STRD's two source registers must be an - /// even / odd pair, ARM::STM registers have to be in ascending order. - /// Post-register allocation passes should not attempt to change allocations - /// for sources of instructions with this flag. - bool hasExtraSrcRegAllocReq() const { - return Flags & (1 << TID::ExtraSrcRegAllocReq); - } - - /// hasExtraDefRegAllocReq - Returns true if this instruction def operands - /// have special register allocation requirements that are not captured by the - /// operand register classes. e.g. ARM::LDRD's two def registers must be an - /// even / odd pair, ARM::LDM registers have to be in ascending order. - /// Post-register allocation passes should not attempt to change allocations - /// for definitions of instructions with this flag. - bool hasExtraDefRegAllocReq() const { - return Flags & (1 << TID::ExtraDefRegAllocReq); - } -}; - -} // end namespace llvm - -#endif Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Jun 28 14:10:37 2011 @@ -14,7 +14,7 @@ #ifndef LLVM_TARGET_TARGETINSTRINFO_H #define LLVM_TARGET_TARGETINSTRINFO_H -#include "llvm/Target/TargetInstrDesc.h" +#include "llvm/MC/MCInstrInfo.h" #include "llvm/CodeGen/MachineFunction.h" namespace llvm { @@ -40,29 +40,16 @@ /// /// TargetInstrInfo - Interface to description of machine instruction set /// -class TargetInstrInfo { - const TargetInstrDesc *Descriptors; // Raw array to allow static init'n - unsigned NumOpcodes; // Number of entries in the desc array - +class TargetInstrInfo : public MCInstrInfo { TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT public: - TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes); + TargetInstrInfo(const MCInstrDesc *desc, unsigned NumOpcodes); virtual ~TargetInstrInfo(); - unsigned getNumOpcodes() const { return NumOpcodes; } - - /// get - Return the machine instruction descriptor that corresponds to the - /// specified instruction opcode. - /// - const TargetInstrDesc &get(unsigned Opcode) const { - assert(Opcode < NumOpcodes && "Invalid opcode!"); - return Descriptors[Opcode]; - } - /// getRegClass - Givem a machine instruction descriptor, returns the register /// class constraint for OpNum, or NULL. - const TargetRegisterClass *getRegClass(const TargetInstrDesc &TID, + const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum, const TargetRegisterInfo *TRI) const; @@ -677,7 +664,7 @@ /// libcodegen, not in libtarget. class TargetInstrInfoImpl : public TargetInstrInfo { protected: - TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes) + TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes) : TargetInstrInfo(desc, NumOpcodes) {} public: virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Jun 28 14:10:37 2011 @@ -495,7 +495,7 @@ } /// getRegClass - Returns the register class associated with the enumeration - /// value. See class TargetOperandInfo. + /// value. See class MCOperandInfo. const TargetRegisterClass *getRegClass(unsigned i) const { assert(i < getNumRegClasses() && "Register Class ID out of range"); return RegClassBegin[i]; Modified: llvm/trunk/lib/CodeGen/BranchFolding.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/BranchFolding.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp (original) +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp Tue Jun 28 14:10:37 2011 @@ -421,10 +421,10 @@ for (; I != E; ++I) { if (I->isDebugValue()) continue; - const TargetInstrDesc &TID = I->getDesc(); - if (TID.isCall()) + const MCInstrDesc &MCID = I->getDesc(); + if (MCID.isCall()) Time += 10; - else if (TID.mayLoad() || TID.mayStore()) + else if (MCID.mayLoad() || MCID.mayStore()) Time += 2; else ++Time; Modified: llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp (original) +++ llvm/trunk/lib/CodeGen/ExpandISelPseudos.cpp Tue Jun 28 14:10:37 2011 @@ -62,8 +62,8 @@ MachineInstr *MI = MBBI++; // If MI is a pseudo, expand it. - const TargetInstrDesc &TID = MI->getDesc(); - if (TID.usesCustomInsertionHook()) { + const MCInstrDesc &MCID = MI->getDesc(); + if (MCID.usesCustomInsertionHook()) { Changed = true; MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(MI, MBB); Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Tue Jun 28 14:10:37 2011 @@ -651,12 +651,12 @@ if (I->isDebugValue()) continue; - const TargetInstrDesc &TID = I->getDesc(); - if (TID.isNotDuplicable()) + const MCInstrDesc &MCID = I->getDesc(); + if (MCID.isNotDuplicable()) BBI.CannotBeCopied = true; bool isPredicated = TII->isPredicated(I); - bool isCondBr = BBI.IsBrAnalyzable && TID.isConditionalBranch(); + bool isCondBr = BBI.IsBrAnalyzable && MCID.isConditionalBranch(); if (!isCondBr) { if (!isPredicated) { @@ -1414,9 +1414,9 @@ for (MachineBasicBlock::iterator I = FromBBI.BB->begin(), E = FromBBI.BB->end(); I != E; ++I) { - const TargetInstrDesc &TID = I->getDesc(); + const MCInstrDesc &MCID = I->getDesc(); // Do not copy the end of the block branches. - if (IgnoreBr && TID.isBranch()) + if (IgnoreBr && MCID.isBranch()) break; MachineInstr *MI = MF.CloneMachineInstr(I); Modified: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp Tue Jun 28 14:10:37 2011 @@ -22,7 +22,6 @@ #include "llvm/MC/MCContext.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetData.h" -#include "llvm/Target/TargetInstrDesc.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Assembly/Writer.h" Modified: llvm/trunk/lib/CodeGen/MachineCSE.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineCSE.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineCSE.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineCSE.cpp Tue Jun 28 14:10:37 2011 @@ -260,12 +260,12 @@ return false; // Ignore stuff that we obviously can't move. - const TargetInstrDesc &TID = MI->getDesc(); - if (TID.mayStore() || TID.isCall() || TID.isTerminator() || + const MCInstrDesc &MCID = MI->getDesc(); + if (MCID.mayStore() || MCID.isCall() || MCID.isTerminator() || MI->hasUnmodeledSideEffects()) return false; - if (TID.mayLoad()) { + if (MCID.mayLoad()) { // Okay, this instruction does a load. As a refinement, we allow the target // to decide whether the loaded value is actually a constant. If so, we can // actually use it as a load. Modified: llvm/trunk/lib/CodeGen/MachineFunction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineFunction.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineFunction.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineFunction.cpp Tue Jun 28 14:10:37 2011 @@ -152,10 +152,10 @@ /// of `new MachineInstr'. /// MachineInstr * -MachineFunction::CreateMachineInstr(const TargetInstrDesc &TID, +MachineFunction::CreateMachineInstr(const MCInstrDesc &MCID, DebugLoc DL, bool NoImp) { return new (InstructionRecycler.Allocate(Allocator)) - MachineInstr(TID, DL, NoImp); + MachineInstr(MCID, DL, NoImp); } /// CloneMachineInstr - Create a new MachineInstr which is a copy of the Modified: llvm/trunk/lib/CodeGen/MachineInstr.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineInstr.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineInstr.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineInstr.cpp Tue Jun 28 14:10:37 2011 @@ -24,10 +24,10 @@ #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCSymbol.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetInstrDesc.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/DebugInfo.h" @@ -457,9 +457,9 @@ //===----------------------------------------------------------------------===// /// MachineInstr ctor - This constructor creates a dummy MachineInstr with -/// TID NULL and no operands. +/// MCID NULL and no operands. MachineInstr::MachineInstr() - : TID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), + : MCID(0), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), Parent(0) { // Make sure that we get added to a machine basicblock @@ -467,23 +467,23 @@ } void MachineInstr::addImplicitDefUseOperands() { - if (TID->ImplicitDefs) - for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs) + if (MCID->ImplicitDefs) + for (const unsigned *ImpDefs = MCID->ImplicitDefs; *ImpDefs; ++ImpDefs) addOperand(MachineOperand::CreateReg(*ImpDefs, true, true)); - if (TID->ImplicitUses) - for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses) + if (MCID->ImplicitUses) + for (const unsigned *ImpUses = MCID->ImplicitUses; *ImpUses; ++ImpUses) addOperand(MachineOperand::CreateReg(*ImpUses, false, true)); } /// MachineInstr ctor - This constructor creates a MachineInstr and adds the /// implicit operands. It reserves space for the number of operands specified by -/// the TargetInstrDesc. -MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp) - : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), +/// the MCInstrDesc. +MachineInstr::MachineInstr(const MCInstrDesc &tid, bool NoImp) + : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), Parent(0) { if (!NoImp) - NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses(); - Operands.reserve(NumImplicitOps + TID->getNumOperands()); + NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); + Operands.reserve(NumImplicitOps + MCID->getNumOperands()); if (!NoImp) addImplicitDefUseOperands(); // Make sure that we get added to a machine basicblock @@ -491,13 +491,13 @@ } /// MachineInstr ctor - As above, but with a DebugLoc. -MachineInstr::MachineInstr(const TargetInstrDesc &tid, const DebugLoc dl, +MachineInstr::MachineInstr(const MCInstrDesc &tid, const DebugLoc dl, bool NoImp) - : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), + : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) { if (!NoImp) - NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses(); - Operands.reserve(NumImplicitOps + TID->getNumOperands()); + NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); + Operands.reserve(NumImplicitOps + MCID->getNumOperands()); if (!NoImp) addImplicitDefUseOperands(); // Make sure that we get added to a machine basicblock @@ -507,12 +507,12 @@ /// MachineInstr ctor - Work exactly the same as the ctor two above, except /// that the MachineInstr is created and added to the end of the specified /// basic block. -MachineInstr::MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &tid) - : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), +MachineInstr::MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &tid) + : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), Parent(0) { assert(MBB && "Cannot use inserting ctor with null basic block!"); - NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses(); - Operands.reserve(NumImplicitOps + TID->getNumOperands()); + NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); + Operands.reserve(NumImplicitOps + MCID->getNumOperands()); addImplicitDefUseOperands(); // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); @@ -522,12 +522,12 @@ /// MachineInstr ctor - As above, but with a DebugLoc. /// MachineInstr::MachineInstr(MachineBasicBlock *MBB, const DebugLoc dl, - const TargetInstrDesc &tid) - : TID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), + const MCInstrDesc &tid) + : MCID(&tid), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), MemRefs(0), MemRefsEnd(0), Parent(0), debugLoc(dl) { assert(MBB && "Cannot use inserting ctor with null basic block!"); - NumImplicitOps = TID->getNumImplicitDefs() + TID->getNumImplicitUses(); - Operands.reserve(NumImplicitOps + TID->getNumOperands()); + NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); + Operands.reserve(NumImplicitOps + MCID->getNumOperands()); addImplicitDefUseOperands(); // Make sure that we get added to a machine basicblock LeakDetector::addGarbageObject(this); @@ -537,7 +537,7 @@ /// MachineInstr ctor - Copies MachineInstr arg exactly /// MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) - : TID(&MI.getDesc()), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), + : MCID(&MI.getDesc()), NumImplicitOps(0), Flags(0), AsmPrinterFlags(0), MemRefs(MI.MemRefs), MemRefsEnd(MI.MemRefsEnd), Parent(0), debugLoc(MI.getDebugLoc()) { Operands.reserve(MI.getNumOperands()); @@ -624,7 +624,7 @@ Operands.back().AddRegOperandToRegInfo(RegInfo); // If the register operand is flagged as early, mark the operand as such unsigned OpNo = Operands.size() - 1; - if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) + if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) Operands[OpNo].setIsEarlyClobber(true); } return; @@ -646,7 +646,7 @@ if (Operands[OpNo].isReg()) { Operands[OpNo].AddRegOperandToRegInfo(0); // If the register operand is flagged as early, mark the operand as such - if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) + if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) Operands[OpNo].setIsEarlyClobber(true); } @@ -671,7 +671,7 @@ if (Operands[OpNo].isReg()) { Operands[OpNo].AddRegOperandToRegInfo(RegInfo); // If the register operand is flagged as early, mark the operand as such - if (TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) + if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) Operands[OpNo].setIsEarlyClobber(true); } @@ -694,7 +694,7 @@ // If the register operand is flagged as early, mark the operand as such if (Operands[OpNo].isReg() - && TID->getOperandConstraint(OpNo, TOI::EARLY_CLOBBER) != -1) + && MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1) Operands[OpNo].setIsEarlyClobber(true); } } @@ -820,8 +820,8 @@ /// OperandComplete - Return true if it's illegal to add a new operand /// bool MachineInstr::OperandsComplete() const { - unsigned short NumOperands = TID->getNumOperands(); - if (!TID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) + unsigned short NumOperands = MCID->getNumOperands(); + if (!MCID->isVariadic() && getNumOperands()-NumImplicitOps >= NumOperands) return true; // Broken: we have all the operands of this instruction! return false; } @@ -829,8 +829,8 @@ /// getNumExplicitOperands - Returns the number of non-implicit operands. /// unsigned MachineInstr::getNumExplicitOperands() const { - unsigned NumOperands = TID->getNumOperands(); - if (!TID->isVariadic()) + unsigned NumOperands = MCID->getNumOperands(); + if (!MCID->isVariadic()) return NumOperands; for (unsigned i = NumOperands, e = getNumOperands(); i != e; ++i) { @@ -931,10 +931,10 @@ /// operand list that is used to represent the predicate. It returns -1 if /// none is found. int MachineInstr::findFirstPredOperandIdx() const { - const TargetInstrDesc &TID = getDesc(); - if (TID.isPredicable()) { + const MCInstrDesc &MCID = getDesc(); + if (MCID.isPredicable()) { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) - if (TID.OpInfo[i].isPredicate()) + if (MCID.OpInfo[i].isPredicate()) return i; } @@ -990,11 +990,11 @@ } assert(getOperand(DefOpIdx).isDef() && "DefOpIdx is not a def!"); - const TargetInstrDesc &TID = getDesc(); - for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { + const MCInstrDesc &MCID = getDesc(); + for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); if (MO.isReg() && MO.isUse() && - TID.getOperandConstraint(i, TOI::TIED_TO) == (int)DefOpIdx) { + MCID.getOperandConstraint(i, MCOI::TIED_TO) == (int)DefOpIdx) { if (UseOpIdx) *UseOpIdx = (unsigned)i; return true; @@ -1050,13 +1050,13 @@ return false; } - const TargetInstrDesc &TID = getDesc(); - if (UseOpIdx >= TID.getNumOperands()) + const MCInstrDesc &MCID = getDesc(); + if (UseOpIdx >= MCID.getNumOperands()) return false; const MachineOperand &MO = getOperand(UseOpIdx); if (!MO.isReg() || !MO.isUse()) return false; - int DefIdx = TID.getOperandConstraint(UseOpIdx, TOI::TIED_TO); + int DefIdx = MCID.getOperandConstraint(UseOpIdx, MCOI::TIED_TO); if (DefIdx == -1) return false; if (DefOpIdx) @@ -1096,11 +1096,11 @@ /// copyPredicates - Copies predicate operand(s) from MI. void MachineInstr::copyPredicates(const MachineInstr *MI) { - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.isPredicable()) + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.isPredicable()) return; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { - if (TID.OpInfo[i].isPredicate()) { + if (MCID.OpInfo[i].isPredicate()) { // Predicated operands must be last operands. addOperand(MI->getOperand(i)); } @@ -1137,13 +1137,13 @@ AliasAnalysis *AA, bool &SawStore) const { // Ignore stuff that we obviously can't move. - if (TID->mayStore() || TID->isCall()) { + if (MCID->mayStore() || MCID->isCall()) { SawStore = true; return false; } if (isLabel() || isDebugValue() || - TID->isTerminator() || hasUnmodeledSideEffects()) + MCID->isTerminator() || hasUnmodeledSideEffects()) return false; // See if this instruction does a load. If so, we have to guarantee that the @@ -1151,7 +1151,7 @@ // destination. The check for isInvariantLoad gives the targe the chance to // classify the load as always returning a constant, e.g. a constant pool // load. - if (TID->mayLoad() && !isInvariantLoad(AA)) + if (MCID->mayLoad() && !isInvariantLoad(AA)) // Otherwise, this is a real load. If there is a store between the load and // end of block, or if the load is volatile, we can't move it. return !SawStore && !hasVolatileMemoryRef(); @@ -1191,9 +1191,9 @@ /// have no volatile memory references. bool MachineInstr::hasVolatileMemoryRef() const { // An instruction known never to access memory won't have a volatile access. - if (!TID->mayStore() && - !TID->mayLoad() && - !TID->isCall() && + if (!MCID->mayStore() && + !MCID->mayLoad() && + !MCID->isCall() && !hasUnmodeledSideEffects()) return false; @@ -1217,7 +1217,7 @@ /// *all* loads the instruction does are invariant (if it does multiple loads). bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { // If the instruction doesn't load at all, it isn't an invariant load. - if (!TID->mayLoad()) + if (!MCID->mayLoad()) return false; // If the instruction has lost its memoperands, conservatively assume that @@ -1421,10 +1421,10 @@ if (FirstOp) FirstOp = false; else OS << ","; OS << " "; if (i < getDesc().NumOperands) { - const TargetOperandInfo &TOI = getDesc().OpInfo[i]; - if (TOI.isPredicate()) + const MCOperandInfo &MCOI = getDesc().OpInfo[i]; + if (MCOI.isPredicate()) OS << "pred:"; - if (TOI.isOptionalDef()) + if (MCOI.isOptionalDef()) OS << "opt:"; } if (isDebugValue() && MO.isMetadata()) { Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Tue Jun 28 14:10:37 2011 @@ -1018,9 +1018,9 @@ /*UnfoldStore=*/false, &LoadRegIndex); if (NewOpc == 0) return 0; - const TargetInstrDesc &TID = TII->get(NewOpc); - if (TID.getNumDefs() != 1) return 0; - const TargetRegisterClass *RC = TII->getRegClass(TID, LoadRegIndex, TRI); + const MCInstrDesc &MID = TII->get(NewOpc); + if (MID.getNumDefs() != 1) return 0; + const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI); // Ok, we're unfolding. Create a temporary register and do the unfold. unsigned Reg = MRI->createVirtualRegister(RC); Modified: llvm/trunk/lib/CodeGen/MachineVerifier.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineVerifier.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp Tue Jun 28 14:10:37 2011 @@ -541,19 +541,19 @@ } void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) { - const TargetInstrDesc &TI = MI->getDesc(); - if (MI->getNumOperands() < TI.getNumOperands()) { + const MCInstrDesc &MCID = MI->getDesc(); + if (MI->getNumOperands() < MCID.getNumOperands()) { report("Too few operands", MI); - *OS << TI.getNumOperands() << " operands expected, but " + *OS << MCID.getNumOperands() << " operands expected, but " << MI->getNumExplicitOperands() << " given.\n"; } // Check the MachineMemOperands for basic consistency. for (MachineInstr::mmo_iterator I = MI->memoperands_begin(), E = MI->memoperands_end(); I != E; ++I) { - if ((*I)->isLoad() && !TI.mayLoad()) + if ((*I)->isLoad() && !MCID.mayLoad()) report("Missing mayLoad flag", MI); - if ((*I)->isStore() && !TI.mayStore()) + if ((*I)->isStore() && !MCID.mayStore()) report("Missing mayStore flag", MI); } @@ -575,29 +575,30 @@ void MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) { const MachineInstr *MI = MO->getParent(); - const TargetInstrDesc &TI = MI->getDesc(); - const TargetOperandInfo &TOI = TI.OpInfo[MONum]; + const MCInstrDesc &MCID = MI->getDesc(); + const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; - // The first TI.NumDefs operands must be explicit register defines - if (MONum < TI.getNumDefs()) { + // The first MCID.NumDefs operands must be explicit register defines + if (MONum < MCID.getNumDefs()) { if (!MO->isReg()) report("Explicit definition must be a register", MO, MONum); else if (!MO->isDef()) report("Explicit definition marked as use", MO, MONum); else if (MO->isImplicit()) report("Explicit definition marked as implicit", MO, MONum); - } else if (MONum < TI.getNumOperands()) { + } else if (MONum < MCID.getNumOperands()) { // Don't check if it's the last operand in a variadic instruction. See, // e.g., LDM_RET in the arm back end. - if (MO->isReg() && !(TI.isVariadic() && MONum == TI.getNumOperands()-1)) { - if (MO->isDef() && !TOI.isOptionalDef()) + if (MO->isReg() && + !(MCID.isVariadic() && MONum == MCID.getNumOperands()-1)) { + if (MO->isDef() && !MCOI.isOptionalDef()) report("Explicit operand marked as def", MO, MONum); if (MO->isImplicit()) report("Explicit operand marked as implicit", MO, MONum); } } else { // ARM adds %reg0 operands to indicate predicates. We'll allow that. - if (MO->isReg() && !MO->isImplicit() && !TI.isVariadic() && MO->getReg()) + if (MO->isReg() && !MO->isImplicit() && !MCID.isVariadic() && MO->getReg()) report("Extra explicit operand on non-variadic instruction", MO, MONum); } @@ -709,7 +710,7 @@ } // Check register classes. - if (MONum < TI.getNumOperands() && !MO->isImplicit()) { + if (MONum < MCID.getNumOperands() && !MO->isImplicit()) { unsigned SubIdx = MO->getSubReg(); if (TargetRegisterInfo::isPhysicalRegister(Reg)) { @@ -723,7 +724,7 @@ } sr = s; } - if (const TargetRegisterClass *DRC = TII->getRegClass(TI, MONum, TRI)) { + if (const TargetRegisterClass *DRC = TII->getRegClass(MCID,MONum,TRI)) { if (!DRC->contains(sr)) { report("Illegal physical register for instruction", MO, MONum); *OS << TRI->getName(sr) << " is not a " @@ -743,7 +744,7 @@ } RC = SRC; } - if (const TargetRegisterClass *DRC = TII->getRegClass(TI, MONum, TRI)) { + if (const TargetRegisterClass *DRC = TII->getRegClass(MCID,MONum,TRI)) { if (!RC->hasSuperClassEq(DRC)) { report("Illegal virtual register for instruction", MO, MONum); *OS << "Expected a " << DRC->getName() << " register, but got a " @@ -765,11 +766,11 @@ LiveInts && !LiveInts->isNotInMIMap(MI)) { LiveInterval &LI = LiveStks->getInterval(MO->getIndex()); SlotIndex Idx = LiveInts->getInstructionIndex(MI); - if (TI.mayLoad() && !LI.liveAt(Idx.getUseIndex())) { + if (MCID.mayLoad() && !LI.liveAt(Idx.getUseIndex())) { report("Instruction loads from dead spill slot", MO, MONum); *OS << "Live stack: " << LI << '\n'; } - if (TI.mayStore() && !LI.liveAt(Idx.getDefIndex())) { + if (MCID.mayStore() && !LI.liveAt(Idx.getDefIndex())) { report("Instruction stores to dead spill slot", MO, MONum); *OS << "Live stack: " << LI << '\n'; } Modified: llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp (original) +++ llvm/trunk/lib/CodeGen/PeepholeOptimizer.cpp Tue Jun 28 14:10:37 2011 @@ -353,10 +353,10 @@ bool PeepholeOptimizer::isMoveImmediate(MachineInstr *MI, SmallSet &ImmDefRegs, DenseMap &ImmDefMIs) { - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.isMoveImmediate()) + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.isMoveImmediate()) return false; - if (TID.getNumDefs() != 1) + if (MCID.getNumDefs() != 1) return false; unsigned Reg = MI->getOperand(0).getReg(); if (TargetRegisterInfo::isVirtualRegister(Reg)) { @@ -429,16 +429,16 @@ continue; } - const TargetInstrDesc &TID = MI->getDesc(); + const MCInstrDesc &MCID = MI->getDesc(); - if (TID.isBitcast()) { + if (MCID.isBitcast()) { if (OptimizeBitcastInstr(MI, MBB)) { // MI is deleted. Changed = true; MII = First ? I->begin() : llvm::next(PMII); continue; } - } else if (TID.isCompare()) { + } else if (MCID.isCompare()) { if (OptimizeCmpInstr(MI, MBB)) { // MI is deleted. Changed = true; Modified: llvm/trunk/lib/CodeGen/RegAllocFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocFast.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocFast.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp Tue Jun 28 14:10:37 2011 @@ -118,7 +118,7 @@ // SkippedInstrs - Descriptors of instructions whose clobber list was // ignored because all registers were spilled. It is still necessary to // mark all the clobbered registers as used by the function. - SmallPtrSet SkippedInstrs; + SmallPtrSet SkippedInstrs; // isBulkSpilling - This flag is set when LiveRegMap will be cleared // completely after spilling all live registers. LiveRegMap entries should @@ -777,7 +777,7 @@ // Otherwise, sequentially allocate each instruction in the MBB. while (MII != MBB->end()) { MachineInstr *MI = MII++; - const TargetInstrDesc &TID = MI->getDesc(); + const MCInstrDesc &MCID = MI->getDesc(); DEBUG({ dbgs() << "\n>> " << *MI << "Regs:"; for (unsigned Reg = 1, E = TRI->getNumRegs(); Reg != E; ++Reg) { @@ -890,7 +890,7 @@ VirtOpEnd = i+1; if (MO.isUse()) { hasTiedOps = hasTiedOps || - TID.getOperandConstraint(i, TOI::TIED_TO) != -1; + MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1; } else { if (MO.isEarlyClobber()) hasEarlyClobbers = true; @@ -920,7 +920,7 @@ // We didn't detect inline asm tied operands above, so just make this extra // pass for all inline asm. if (MI->isInlineAsm() || hasEarlyClobbers || hasPartialRedefs || - (hasTiedOps && (hasPhysDefs || TID.getNumDefs() > 1))) { + (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) { handleThroughOperands(MI, VirtDead); // Don't attempt coalescing when we have funny stuff going on. CopyDst = 0; @@ -965,7 +965,7 @@ } unsigned DefOpEnd = MI->getNumOperands(); - if (TID.isCall()) { + if (MCID.isCall()) { // Spill all virtregs before a call. This serves two purposes: 1. If an // exception is thrown, the landing pad is going to expect to find // registers in their spill slots, and 2. we don't have to wade through @@ -976,7 +976,7 @@ // The imp-defs are skipped below, but we still need to mark those // registers as used by the function. - SkippedInstrs.insert(&TID); + SkippedInstrs.insert(&MCID); } // Third scan. @@ -1062,7 +1062,7 @@ MRI->closePhysRegsUsed(*TRI); // Add the clobber lists for all the instructions we skipped earlier. - for (SmallPtrSet::const_iterator + for (SmallPtrSet::const_iterator I = SkippedInstrs.begin(), E = SkippedInstrs.end(); I != E; ++I) if (const unsigned *Defs = (*I)->getImplicitDefs()) while (*Defs) Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Tue Jun 28 14:10:37 2011 @@ -526,8 +526,8 @@ MachineInstr *DefMI = li_->getInstructionFromIndex(AValNo->def); if (!DefMI) return false; - const TargetInstrDesc &TID = DefMI->getDesc(); - if (!TID.isCommutable()) + const MCInstrDesc &MCID = DefMI->getDesc(); + if (!MCID.isCommutable()) return false; // If DefMI is a two-address instruction then commuting it will change the // destination register. @@ -687,21 +687,21 @@ if (!DefMI) return false; assert(DefMI && "Defining instruction disappeared"); - const TargetInstrDesc &TID = DefMI->getDesc(); - if (!TID.isAsCheapAsAMove()) + const MCInstrDesc &MCID = DefMI->getDesc(); + if (!MCID.isAsCheapAsAMove()) return false; if (!tii_->isTriviallyReMaterializable(DefMI, AA)) return false; bool SawStore = false; if (!DefMI->isSafeToMove(tii_, AA, SawStore)) return false; - if (TID.getNumDefs() != 1) + if (MCID.getNumDefs() != 1) return false; if (!DefMI->isImplicitDef()) { // Make sure the copy destination register class fits the instruction // definition register class. The mismatch can happen as a result of earlier // extract_subreg, insert_subreg, subreg_to_reg coalescing. - const TargetRegisterClass *RC = tii_->getRegClass(TID, 0, tri_); + const TargetRegisterClass *RC = tii_->getRegClass(MCID, 0, tri_); if (TargetRegisterInfo::isVirtualRegister(DstReg)) { if (mri_->getRegClass(DstReg) != RC) return false; @@ -712,13 +712,13 @@ // If destination register has a sub-register index on it, make sure it // matches the instruction register class. if (DstSubIdx) { - const TargetInstrDesc &TID = DefMI->getDesc(); - if (TID.getNumDefs() != 1) + const MCInstrDesc &MCID = DefMI->getDesc(); + if (MCID.getNumDefs() != 1) return false; const TargetRegisterClass *DstRC = mri_->getRegClass(DstReg); const TargetRegisterClass *DstSubRC = DstRC->getSubRegisterRegClass(DstSubIdx); - const TargetRegisterClass *DefRC = tii_->getRegClass(TID, 0, tri_); + const TargetRegisterClass *DefRC = tii_->getRegClass(MCID, 0, tri_); if (DefRC == DstRC) DstSubIdx = 0; else if (DefRC != DstSubRC) Modified: llvm/trunk/lib/CodeGen/ScheduleDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAG.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAG.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAG.cpp Tue Jun 28 14:10:37 2011 @@ -45,7 +45,7 @@ ScheduleDAG::~ScheduleDAG() {} /// getInstrDesc helper to handle SDNodes. -const TargetInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const { +const MCInstrDesc *ScheduleDAG::getNodeDesc(const SDNode *Node) const { if (!Node || !Node->isMachineOpcode()) return NULL; return &TII->get(Node->getMachineOpcode()); } Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Tue Jun 28 14:10:37 2011 @@ -236,13 +236,13 @@ continue; } - const TargetInstrDesc &TID = MI->getDesc(); - assert(!TID.isTerminator() && !MI->isLabel() && + const MCInstrDesc &MCID = MI->getDesc(); + assert(!MCID.isTerminator() && !MI->isLabel() && "Cannot schedule terminators or labels!"); // Create the SUnit for this MI. SUnit *SU = NewSUnit(MI); - SU->isCall = TID.isCall(); - SU->isCommutable = TID.isCommutable(); + SU->isCall = MCID.isCall(); + SU->isCommutable = MCID.isCommutable(); // Assign the Latency field of SU using target-provided information. if (UnitLatencies) @@ -309,13 +309,13 @@ if (SpecialAddressLatency != 0 && !UnitLatencies && UseSU != &ExitSU) { MachineInstr *UseMI = UseSU->getInstr(); - const TargetInstrDesc &UseTID = UseMI->getDesc(); + const MCInstrDesc &UseMCID = UseMI->getDesc(); int RegUseIndex = UseMI->findRegisterUseOperandIdx(Reg); assert(RegUseIndex >= 0 && "UseMI doesn's use register!"); if (RegUseIndex >= 0 && - (UseTID.mayLoad() || UseTID.mayStore()) && - (unsigned)RegUseIndex < UseTID.getNumOperands() && - UseTID.OpInfo[RegUseIndex].isLookupPtrRegClass()) + (UseMCID.mayLoad() || UseMCID.mayStore()) && + (unsigned)RegUseIndex < UseMCID.getNumOperands() && + UseMCID.OpInfo[RegUseIndex].isLookupPtrRegClass()) LDataLatency += SpecialAddressLatency; } // Adjust the dependence latency using operand def/use @@ -352,17 +352,17 @@ unsigned Count = I->second.second; const MachineInstr *UseMI = UseMO->getParent(); unsigned UseMOIdx = UseMO - &UseMI->getOperand(0); - const TargetInstrDesc &UseTID = UseMI->getDesc(); + const MCInstrDesc &UseMCID = UseMI->getDesc(); // TODO: If we knew the total depth of the region here, we could // handle the case where the whole loop is inside the region but // is large enough that the isScheduleHigh trick isn't needed. - if (UseMOIdx < UseTID.getNumOperands()) { + if (UseMOIdx < UseMCID.getNumOperands()) { // Currently, we only support scheduling regions consisting of // single basic blocks. Check to see if the instruction is in // the same region by checking to see if it has the same parent. if (UseMI->getParent() != MI->getParent()) { unsigned Latency = SU->Latency; - if (UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass()) + if (UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) Latency += SpecialAddressLatency; // This is a wild guess as to the portion of the latency which // will be overlapped by work done outside the current @@ -374,7 +374,7 @@ /*isMustAlias=*/false, /*isArtificial=*/true)); } else if (SpecialAddressLatency > 0 && - UseTID.OpInfo[UseMOIdx].isLookupPtrRegClass()) { + UseMCID.OpInfo[UseMOIdx].isLookupPtrRegClass()) { // The entire loop body is within the current scheduling region // and the latency of this operation is assumed to be greater // than the latency of the loop. @@ -417,9 +417,9 @@ // produce more precise dependence information. #define STORE_LOAD_LATENCY 1 unsigned TrueMemOrderLatency = 0; - if (TID.isCall() || MI->hasUnmodeledSideEffects() || + if (MCID.isCall() || MI->hasUnmodeledSideEffects() || (MI->hasVolatileMemoryRef() && - (!TID.mayLoad() || !MI->isInvariantLoad(AA)))) { + (!MCID.mayLoad() || !MI->isInvariantLoad(AA)))) { // Be conservative with these and add dependencies on all memory // references, even those that are known to not alias. for (std::map::iterator I = @@ -458,7 +458,7 @@ PendingLoads.clear(); AliasMemDefs.clear(); AliasMemUses.clear(); - } else if (TID.mayStore()) { + } else if (MCID.mayStore()) { bool MayAlias = true; TrueMemOrderLatency = STORE_LOAD_LATENCY; if (const Value *V = getUnderlyingObjectForInstr(MI, MFI, MayAlias)) { @@ -514,7 +514,7 @@ /*Reg=*/0, /*isNormalMemory=*/false, /*isMustAlias=*/false, /*isArtificial=*/true)); - } else if (TID.mayLoad()) { + } else if (MCID.mayLoad()) { bool MayAlias = true; TrueMemOrderLatency = 0; if (MI->isInvariantLoad(AA)) { Modified: llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp (original) +++ llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp Tue Jun 28 14:10:37 2011 @@ -115,12 +115,12 @@ // Use the itinerary for the underlying instruction to check for // free FU's in the scoreboard at the appropriate future cycles. - const TargetInstrDesc *TID = DAG->getInstrDesc(SU); - if (TID == NULL) { + const MCInstrDesc *MCID = DAG->getInstrDesc(SU); + if (MCID == NULL) { // Don't check hazards for non-machineinstr Nodes. return NoHazard; } - unsigned idx = TID->getSchedClass(); + unsigned idx = MCID->getSchedClass(); for (const InstrStage *IS = ItinData->beginStage(idx), *E = ItinData->endStage(idx); IS != E; ++IS) { // We must find one of the stage's units free for every cycle the @@ -173,16 +173,16 @@ // Use the itinerary for the underlying instruction to reserve FU's // in the scoreboard at the appropriate future cycles. - const TargetInstrDesc *TID = DAG->getInstrDesc(SU); - assert(TID && "The scheduler must filter non-machineinstrs"); - if (DAG->TII->isZeroCost(TID->Opcode)) + const MCInstrDesc *MCID = DAG->getInstrDesc(SU); + assert(MCID && "The scheduler must filter non-machineinstrs"); + if (DAG->TII->isZeroCost(MCID->Opcode)) return; ++IssueCount; unsigned cycle = 0; - unsigned idx = TID->getSchedClass(); + unsigned idx = MCID->getSchedClass(); for (const InstrStage *IS = ItinData->beginStage(idx), *E = ItinData->endStage(idx); IS != E; ++IS) { // We must reserve one of the stage's units for every cycle the Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Tue Jun 28 14:10:37 2011 @@ -569,7 +569,7 @@ case Intrinsic::dbg_value: { // This form of DBG_VALUE is target-independent. const DbgValueInst *DI = cast(Call); - const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); + const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); const Value *V = DI->getValue(); if (!V) { // Currently the optimizer can produce this; insert an undef to @@ -1112,7 +1112,7 @@ unsigned FastISel::FastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass* RC) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg); return ResultReg; @@ -1122,7 +1122,7 @@ const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -1142,7 +1142,7 @@ unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -1164,7 +1164,7 @@ unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -1187,7 +1187,7 @@ unsigned Op0, bool Op0IsKill, uint64_t Imm) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -1208,7 +1208,7 @@ unsigned Op0, bool Op0IsKill, uint64_t Imm1, uint64_t Imm2) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -1231,7 +1231,7 @@ unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -1253,7 +1253,7 @@ unsigned Op1, bool Op1IsKill, uint64_t Imm) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -1275,7 +1275,7 @@ const TargetRegisterClass *RC, uint64_t Imm) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm); @@ -1291,7 +1291,7 @@ const TargetRegisterClass *RC, uint64_t Imm1, uint64_t Imm2) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Tue Jun 28 14:10:37 2011 @@ -106,7 +106,7 @@ continue; Match = false; if (User->isMachineOpcode()) { - const TargetInstrDesc &II = TII->get(User->getMachineOpcode()); + const MCInstrDesc &II = TII->get(User->getMachineOpcode()); const TargetRegisterClass *RC = 0; if (i+II.getNumDefs() < II.getNumOperands()) RC = TII->getRegClass(II, i+II.getNumDefs(), TRI); @@ -178,7 +178,7 @@ } void InstrEmitter::CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, - const TargetInstrDesc &II, + const MCInstrDesc &II, bool IsClone, bool IsCloned, DenseMap &VRBaseMap) { assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && @@ -242,7 +242,7 @@ Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { // Add an IMPLICIT_DEF instruction before every use. unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); - // IMPLICIT_DEF can produce any type of result so its TargetInstrDesc + // IMPLICIT_DEF can produce any type of result so its MCInstrDesc // does not include operand register class info. if (!VReg) { const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); @@ -265,7 +265,7 @@ void InstrEmitter::AddRegisterOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum, - const TargetInstrDesc *II, + const MCInstrDesc *II, DenseMap &VRBaseMap, bool IsDebug, bool IsClone, bool IsCloned) { assert(Op.getValueType() != MVT::Other && @@ -275,9 +275,9 @@ unsigned VReg = getVR(Op, VRBaseMap); assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); - const TargetInstrDesc &TID = MI->getDesc(); - bool isOptDef = IIOpNum < TID.getNumOperands() && - TID.OpInfo[IIOpNum].isOptionalDef(); + const MCInstrDesc &MCID = MI->getDesc(); + bool isOptDef = IIOpNum < MCID.getNumOperands() && + MCID.OpInfo[IIOpNum].isOptionalDef(); // If the instruction requires a register in a different class, create // a new virtual register and copy the value into it. @@ -286,7 +286,7 @@ const TargetRegisterClass *DstRC = 0; if (IIOpNum < II->getNumOperands()) DstRC = TII->getRegClass(*II, IIOpNum, TRI); - assert((DstRC || (TID.isVariadic() && IIOpNum >= TID.getNumOperands())) && + assert((DstRC || (MCID.isVariadic() && IIOpNum >= MCID.getNumOperands())) && "Don't have operand info for this instruction!"); if (DstRC && !SrcRC->hasSuperClassEq(DstRC)) { unsigned NewVReg = MRI->createVirtualRegister(DstRC); @@ -312,7 +312,7 @@ while (Idx > 0 && MI->getOperand(Idx-1).isReg() && MI->getOperand(Idx-1).isImplicit()) --Idx; - bool isTied = MI->getDesc().getOperandConstraint(Idx, TOI::TIED_TO) != -1; + bool isTied = MI->getDesc().getOperandConstraint(Idx, MCOI::TIED_TO) != -1; if (isTied) isKill = false; } @@ -330,7 +330,7 @@ /// assertions only. void InstrEmitter::AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum, - const TargetInstrDesc *II, + const MCInstrDesc *II, DenseMap &VRBaseMap, bool IsDebug, bool IsClone, bool IsCloned) { if (Op.isMachineOpcode()) { @@ -556,7 +556,7 @@ unsigned NumOps = Node->getNumOperands(); assert((NumOps & 1) == 1 && "REG_SEQUENCE must have an odd number of operands!"); - const TargetInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); + const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); for (unsigned i = 1; i != NumOps; ++i) { SDValue Op = Node->getOperand(i); if ((i & 1) == 0) { @@ -597,7 +597,7 @@ return TII->emitFrameIndexDebugValue(*MF, FrameIx, Offset, MDPtr, DL); } // Otherwise, we're going to create an instruction here. - const TargetInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); + const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); MachineInstrBuilder MIB = BuildMI(*MF, DL, II); if (SD->getKind() == SDDbgValue::SDNODE) { SDNode *Node = SD->getSDNode(); @@ -668,7 +668,7 @@ // We want a unique VR for each IMPLICIT_DEF use. return; - const TargetInstrDesc &II = TII->get(Opc); + const MCInstrDesc &II = TII->get(Opc); unsigned NumResults = CountResults(Node); unsigned NodeOperands = CountOperands(Node); bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; @@ -697,9 +697,9 @@ UsedRegs.push_back(cast(F->getOperand(1))->getReg()); else { // Collect declared implicit uses. - const TargetInstrDesc &TID = TII->get(F->getMachineOpcode()); - UsedRegs.append(TID.getImplicitUses(), - TID.getImplicitUses() + TID.getNumImplicitUses()); + const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); + UsedRegs.append(MCID.getImplicitUses(), + MCID.getImplicitUses() + MCID.getNumImplicitUses()); // In addition to declared implicit uses, we must also check for // direct RegisterSDNode operands. for (unsigned i = 0, e = F->getNumOperands(); i != e; ++i) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.h Tue Jun 28 14:10:37 2011 @@ -22,7 +22,7 @@ namespace llvm { -class TargetInstrDesc; +class MCInstrDesc; class SDDbgValue; class InstrEmitter { @@ -49,7 +49,7 @@ unsigned ResNo) const; void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, - const TargetInstrDesc &II, + const MCInstrDesc &II, bool IsClone, bool IsCloned, DenseMap &VRBaseMap); @@ -63,7 +63,7 @@ /// not in the required register class. void AddRegisterOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum, - const TargetInstrDesc *II, + const MCInstrDesc *II, DenseMap &VRBaseMap, bool IsDebug, bool IsClone, bool IsCloned); @@ -73,7 +73,7 @@ /// assertions only. void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum, - const TargetInstrDesc *II, + const MCInstrDesc *II, DenseMap &VRBaseMap, bool IsDebug, bool IsClone, bool IsCloned); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp Tue Jun 28 14:10:37 2011 @@ -249,14 +249,14 @@ assert(N->getNodeId() == -1 && "Node already inserted!"); N->setNodeId(NewSU->NodeNum); - const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); - for (unsigned i = 0; i != TID.getNumOperands(); ++i) { - if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { + const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); + for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { + if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { NewSU->isTwoAddress = true; break; } } - if (TID.isCommutable()) + if (MCID.isCommutable()) NewSU->isCommutable = true; // LoadNode may already exist. This can happen when there is another @@ -422,10 +422,10 @@ /// FIXME: Move to SelectionDAG? static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) { - const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); - assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); - unsigned NumRes = TID.getNumDefs(); - for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) { + const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); + assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); + unsigned NumRes = MCID.getNumDefs(); + for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { if (Reg == *ImpDef) break; ++NumRes; @@ -505,10 +505,10 @@ } if (!Node->isMachineOpcode()) continue; - const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode()); - if (!TID.ImplicitDefs) + const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); + if (!MCID.ImplicitDefs) continue; - for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) { + for (const unsigned *Reg = MCID.ImplicitDefs; *Reg; ++Reg) { CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI); } } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp Tue Jun 28 14:10:37 2011 @@ -302,7 +302,7 @@ } unsigned Idx = RegDefPos.GetIdx(); - const TargetInstrDesc Desc = TII->get(Opcode); + const MCInstrDesc Desc = TII->get(Opcode); const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI); RegClass = RC->getID(); // FIXME: Cost arbitrarily set to 1 because there doesn't seem to be a @@ -837,14 +837,14 @@ assert(N->getNodeId() == -1 && "Node already inserted!"); N->setNodeId(NewSU->NodeNum); - const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); - for (unsigned i = 0; i != TID.getNumOperands(); ++i) { - if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { + const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); + for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { + if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { NewSU->isTwoAddress = true; break; } } - if (TID.isCommutable()) + if (MCID.isCommutable()) NewSU->isCommutable = true; InitNumRegDefsLeft(NewSU); @@ -1024,10 +1024,10 @@ /// FIXME: Move to SelectionDAG? static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg, const TargetInstrInfo *TII) { - const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); - assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!"); - unsigned NumRes = TID.getNumDefs(); - for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) { + const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); + assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); + unsigned NumRes = MCID.getNumDefs(); + for (const unsigned *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { if (Reg == *ImpDef) break; ++NumRes; @@ -1108,10 +1108,10 @@ if (!Node->isMachineOpcode()) continue; - const TargetInstrDesc &TID = TII->get(Node->getMachineOpcode()); - if (!TID.ImplicitDefs) + const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); + if (!MCID.ImplicitDefs) continue; - for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) + for (const unsigned *Reg = MCID.ImplicitDefs; *Reg; ++Reg) CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI); } @@ -2606,11 +2606,11 @@ bool RegReductionPQBase::canClobber(const SUnit *SU, const SUnit *Op) { if (SU->isTwoAddress) { unsigned Opc = SU->getNode()->getMachineOpcode(); - const TargetInstrDesc &TID = TII->get(Opc); - unsigned NumRes = TID.getNumDefs(); - unsigned NumOps = TID.getNumOperands() - NumRes; + const MCInstrDesc &MCID = TII->get(Opc); + unsigned NumRes = MCID.getNumDefs(); + unsigned NumOps = MCID.getNumOperands() - NumRes; for (unsigned i = 0; i != NumOps; ++i) { - if (TID.getOperandConstraint(i+NumRes, TOI::TIED_TO) != -1) { + if (MCID.getOperandConstraint(i+NumRes, MCOI::TIED_TO) != -1) { SDNode *DU = SU->getNode()->getOperand(i).getNode(); if (DU->getNodeId() != -1 && Op->OrigNode == &(*SUnits)[DU->getNodeId()]) @@ -2790,11 +2790,11 @@ bool isLiveOut = hasOnlyLiveOutUses(SU); unsigned Opc = Node->getMachineOpcode(); - const TargetInstrDesc &TID = TII->get(Opc); - unsigned NumRes = TID.getNumDefs(); - unsigned NumOps = TID.getNumOperands() - NumRes; + const MCInstrDesc &MCID = TII->get(Opc); + unsigned NumRes = MCID.getNumDefs(); + unsigned NumOps = MCID.getNumOperands() - NumRes; for (unsigned j = 0; j != NumOps; ++j) { - if (TID.getOperandConstraint(j+NumRes, TOI::TIED_TO) == -1) + if (MCID.getOperandConstraint(j+NumRes, MCOI::TIED_TO) == -1) continue; SDNode *DU = SU->getNode()->getOperand(j).getNode(); if (DU->getNodeId() == -1) Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Tue Jun 28 14:10:37 2011 @@ -111,7 +111,7 @@ unsigned ResNo = User->getOperand(2).getResNo(); if (Def->isMachineOpcode()) { - const TargetInstrDesc &II = TII->get(Def->getMachineOpcode()); + const MCInstrDesc &II = TII->get(Def->getMachineOpcode()); if (ResNo >= II.getNumDefs() && II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { PhysReg = Reg; @@ -255,8 +255,8 @@ continue; unsigned Opc = Node->getMachineOpcode(); - const TargetInstrDesc &TID = TII->get(Opc); - if (TID.mayLoad()) + const MCInstrDesc &MCID = TII->get(Opc); + if (MCID.mayLoad()) // Cluster loads from "near" addresses into combined SUnits. ClusterNeighboringLoads(Node); } @@ -390,14 +390,14 @@ if (MainNode->isMachineOpcode()) { unsigned Opc = MainNode->getMachineOpcode(); - const TargetInstrDesc &TID = TII->get(Opc); - for (unsigned i = 0; i != TID.getNumOperands(); ++i) { - if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) { + const MCInstrDesc &MCID = TII->get(Opc); + for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { + if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { SU->isTwoAddress = true; break; } } - if (TID.isCommutable()) + if (MCID.isCommutable()) SU->isCommutable = true; } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Tue Jun 28 14:10:37 2011 @@ -354,9 +354,9 @@ const MachineBasicBlock *MBB = I; for (MachineBasicBlock::const_iterator II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { - const TargetInstrDesc &TID = TM.getInstrInfo()->get(II->getOpcode()); + const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); - if ((TID.isCall() && !TID.isReturn()) || + if ((MCID.isCall() && !MCID.isReturn()) || II->isStackAligningInlineAsm()) { MFI->setHasCalls(true); goto done; @@ -681,7 +681,7 @@ // landing pad can thus be detected via the MachineModuleInfo. MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB); - const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); + const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) .addSym(Label); @@ -2613,9 +2613,9 @@ if (EmitNodeInfo & OPFL_MemRefs) { // Only attach load or store memory operands if the generated // instruction may load or store. - const TargetInstrDesc &TID = TM.getInstrInfo()->get(TargetOpc); - bool mayLoad = TID.mayLoad(); - bool mayStore = TID.mayStore(); + const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); + bool mayLoad = MCID.mayLoad(); + bool mayStore = MCID.mayStore(); unsigned NumMemRefs = 0; for (SmallVector::const_iterator I = Modified: llvm/trunk/lib/CodeGen/StackSlotColoring.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/StackSlotColoring.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/StackSlotColoring.cpp (original) +++ llvm/trunk/lib/CodeGen/StackSlotColoring.cpp Tue Jun 28 14:10:37 2011 @@ -504,7 +504,7 @@ bool FoundDef = false; // Not counting 2address def. Uses.clear(); - const TargetInstrDesc &TID = MII->getDesc(); + const MCInstrDesc &MCID = MII->getDesc(); for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) { MachineOperand &MO = MII->getOperand(i); if (!MO.isReg()) @@ -521,7 +521,7 @@ if (MO.getSubReg() || MII->isSubregToReg()) return false; - const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI); + const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI); if (RC && !RC->contains(NewReg)) return false; @@ -566,7 +566,7 @@ SmallVector Uses; while (++MII != MBB->end()) { bool FoundKill = false; - const TargetInstrDesc &TID = MII->getDesc(); + const MCInstrDesc &MCID = MII->getDesc(); for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) { MachineOperand &MO = MII->getOperand(i); if (!MO.isReg()) @@ -583,7 +583,7 @@ if (MO.getSubReg()) return false; - const TargetRegisterClass *RC = TII->getRegClass(TID, i, TRI); + const TargetRegisterClass *RC = TII->getRegClass(MCID, i, TRI); if (RC && !RC->contains(NewReg)) return false; if (MO.isKill()) Modified: llvm/trunk/lib/CodeGen/TailDuplication.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TailDuplication.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TailDuplication.cpp (original) +++ llvm/trunk/lib/CodeGen/TailDuplication.cpp Tue Jun 28 14:10:37 2011 @@ -529,8 +529,8 @@ bool hasIndirectBR = false; if (PreRegAlloc && !TailBB.empty()) { - const TargetInstrDesc &TID = TailBB.back().getDesc(); - if (TID.isIndirectBranch()) { + const MCInstrDesc &MCID = TailBB.back().getDesc(); + if (MCID.isIndirectBranch()) { MaxDuplicateCount = 20; hasIndirectBR = true; } Modified: llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp (original) +++ llvm/trunk/lib/CodeGen/TargetInstrInfoImpl.cpp Tue Jun 28 14:10:37 2011 @@ -59,8 +59,8 @@ // the two operands returned by findCommutedOpIndices. MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, bool NewMI) const { - const TargetInstrDesc &TID = MI->getDesc(); - bool HasDef = TID.getNumDefs(); + const MCInstrDesc &MCID = MI->getDesc(); + bool HasDef = MCID.getNumDefs(); if (HasDef && !MI->getOperand(0).isReg()) // No idea how to commute this instruction. Target should implement its own. return 0; @@ -81,7 +81,7 @@ bool ChangeReg0 = false; if (HasDef && MI->getOperand(0).getReg() == Reg1) { // Must be two address instruction! - assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && + assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && "Expecting a two-address instruction!"); Reg2IsKill = false; ChangeReg0 = true; @@ -119,12 +119,12 @@ bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const { - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.isCommutable()) + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.isCommutable()) return false; // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this // is not true, then the target must implement this. - SrcOpIdx1 = TID.getNumDefs(); + SrcOpIdx1 = MCID.getNumDefs(); SrcOpIdx2 = SrcOpIdx1 + 1; if (!MI->getOperand(SrcOpIdx1).isReg() || !MI->getOperand(SrcOpIdx2).isReg()) @@ -137,12 +137,12 @@ bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI, const SmallVectorImpl &Pred) const { bool MadeChange = false; - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.isPredicable()) + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.isPredicable()) return false; for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) { - if (TID.OpInfo[i].isPredicate()) { + if (MCID.OpInfo[i].isPredicate()) { MachineOperand &MO = MI->getOperand(i); if (MO.isReg()) { MO.setReg(Pred[j].getReg()); @@ -332,10 +332,10 @@ MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx)) return true; - const TargetInstrDesc &TID = MI->getDesc(); + const MCInstrDesc &MCID = MI->getDesc(); // Avoid instructions obviously unsafe for remat. - if (TID.isNotDuplicable() || TID.mayStore() || + if (MCID.isNotDuplicable() || MCID.mayStore() || MI->hasUnmodeledSideEffects()) return false; @@ -345,7 +345,7 @@ return false; // Avoid instructions which load from potentially varying memory. - if (TID.mayLoad() && !MI->isInvariantLoad(AA)) + if (MCID.mayLoad() && !MI->isInvariantLoad(AA)) return false; // If any of the registers accessed are non-constant, conservatively assume Modified: llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp (original) +++ llvm/trunk/lib/CodeGen/TwoAddressInstructionPass.cpp Tue Jun 28 14:10:37 2011 @@ -280,8 +280,8 @@ /// isTwoAddrUse - Return true if the specified MI is using the specified /// register as a two-address operand. static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) { - const TargetInstrDesc &TID = UseMI->getDesc(); - for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { + const MCInstrDesc &MCID = UseMI->getDesc(); + for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { MachineOperand &MO = UseMI->getOperand(i); if (MO.isReg() && MO.getReg() == Reg && (MO.isDef() || UseMI->isRegTiedToDefOperand(i))) @@ -443,8 +443,9 @@ /// isTwoAddrUse - Return true if the specified MI uses the specified register /// as a two-address use. If so, return the destination register by reference. static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { - const TargetInstrDesc &TID = MI.getDesc(); - unsigned NumOps = MI.isInlineAsm() ? MI.getNumOperands():TID.getNumOperands(); + const MCInstrDesc &MCID = MI.getDesc(); + unsigned NumOps = MI.isInlineAsm() + ? MI.getNumOperands() : MCID.getNumOperands(); for (unsigned i = 0; i != NumOps; ++i) { const MachineOperand &MO = MI.getOperand(i); if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) @@ -761,10 +762,10 @@ static bool isSafeToDelete(MachineInstr *MI, const TargetInstrInfo *TII, SmallVector &Kills) { - const TargetInstrDesc &TID = MI->getDesc(); - if (TID.mayStore() || TID.isCall()) + const MCInstrDesc &MCID = MI->getDesc(); + if (MCID.mayStore() || MCID.isCall()) return false; - if (TID.isTerminator() || MI->hasUnmodeledSideEffects()) + if (MCID.isTerminator() || MI->hasUnmodeledSideEffects()) return false; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { @@ -854,7 +855,7 @@ MachineFunction::iterator &mbbi, unsigned SrcIdx, unsigned DstIdx, unsigned Dist, SmallPtrSet &Processed) { - const TargetInstrDesc &TID = mi->getDesc(); + const MCInstrDesc &MCID = mi->getDesc(); unsigned regA = mi->getOperand(DstIdx).getReg(); unsigned regB = mi->getOperand(SrcIdx).getReg(); @@ -876,7 +877,7 @@ unsigned regCIdx = ~0U; bool TryCommute = false; bool AggressiveCommute = false; - if (TID.isCommutable() && mi->getNumOperands() >= 3 && + if (MCID.isCommutable() && mi->getNumOperands() >= 3 && TII->findCommutedOpIndices(mi, SrcOp1, SrcOp2)) { if (SrcIdx == SrcOp1) regCIdx = SrcOp2; @@ -907,7 +908,7 @@ if (TargetRegisterInfo::isVirtualRegister(regA)) ScanUses(regA, &*mbbi, Processed); - if (TID.isConvertibleTo3Addr()) { + if (MCID.isConvertibleTo3Addr()) { // This instruction is potentially convertible to a true // three-address instruction. Check if it is profitable. if (!regBKilled || isProfitableToConv3Addr(regA, regB)) { @@ -927,7 +928,7 @@ // movq (%rax), %rcx // addq %rdx, %rcx // because it's preferable to schedule a load than a register copy. - if (TID.mayLoad() && !regBKilled) { + if (MCID.mayLoad() && !regBKilled) { // Determine if a load can be unfolded. unsigned LoadRegIndex; unsigned NewOpc = @@ -936,14 +937,14 @@ /*UnfoldStore=*/false, &LoadRegIndex); if (NewOpc != 0) { - const TargetInstrDesc &UnfoldTID = TII->get(NewOpc); - if (UnfoldTID.getNumDefs() == 1) { + const MCInstrDesc &UnfoldMCID = TII->get(NewOpc); + if (UnfoldMCID.getNumDefs() == 1) { MachineFunction &MF = *mbbi->getParent(); // Unfold the load. DEBUG(dbgs() << "2addr: UNFOLDING: " << *mi); const TargetRegisterClass *RC = - TII->getRegClass(UnfoldTID, LoadRegIndex, TRI); + TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI); unsigned Reg = MRI->createVirtualRegister(RC); SmallVector NewMIs; if (!TII->unfoldMemoryOperand(MF, mi, Reg, @@ -1067,7 +1068,7 @@ if (mi->isRegSequence()) RegSequences.push_back(&*mi); - const TargetInstrDesc &TID = mi->getDesc(); + const MCInstrDesc &MCID = mi->getDesc(); bool FirstTied = true; DistanceMap.insert(std::make_pair(mi, ++Dist)); @@ -1077,7 +1078,7 @@ // First scan through all the tied register uses in this instruction // and record a list of pairs of tied operands for each register. unsigned NumOps = mi->isInlineAsm() - ? mi->getNumOperands() : TID.getNumOperands(); + ? mi->getNumOperands() : MCID.getNumOperands(); for (unsigned SrcIdx = 0; SrcIdx < NumOps; ++SrcIdx) { unsigned DstIdx = 0; if (!mi->isRegTiedToDefOperand(SrcIdx, &DstIdx)) Modified: llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp (original) +++ llvm/trunk/lib/CodeGen/VirtRegRewriter.cpp Tue Jun 28 14:10:37 2011 @@ -679,8 +679,8 @@ VirtRegMap &VRM) { MachineInstr *ReMatDefMI = VRM.getReMaterializedMI(Reg); #ifndef NDEBUG - const TargetInstrDesc &TID = ReMatDefMI->getDesc(); - assert(TID.getNumDefs() == 1 && + const MCInstrDesc &MCID = ReMatDefMI->getDesc(); + assert(MCID.getNumDefs() == 1 && "Don't know how to remat instructions that define > 1 values!"); #endif TII->reMaterialize(MBB, MII, DestReg, 0, ReMatDefMI, *TRI); @@ -1483,11 +1483,11 @@ /// where SrcReg is r1 and it is tied to r0. Return true if after /// commuting this instruction it will be r0 = op r2, r1. static bool CommuteChangesDestination(MachineInstr *DefMI, - const TargetInstrDesc &TID, + const MCInstrDesc &MCID, unsigned SrcReg, const TargetInstrInfo *TII, unsigned &DstIdx) { - if (TID.getNumDefs() != 1 && TID.getNumOperands() != 3) + if (MCID.getNumDefs() != 1 && MCID.getNumOperands() != 3) return false; if (!DefMI->getOperand(1).isReg() || DefMI->getOperand(1).getReg() != SrcReg) @@ -1527,11 +1527,11 @@ MachineInstr &MI = *MII; MachineBasicBlock::iterator DefMII = prior(MII); MachineInstr *DefMI = DefMII; - const TargetInstrDesc &TID = DefMI->getDesc(); + const MCInstrDesc &MCID = DefMI->getDesc(); unsigned NewDstIdx; if (DefMII != MBB->begin() && - TID.isCommutable() && - CommuteChangesDestination(DefMI, TID, SrcReg, TII, NewDstIdx)) { + MCID.isCommutable() && + CommuteChangesDestination(DefMI, MCID, SrcReg, TII, NewDstIdx)) { MachineOperand &NewDstMO = DefMI->getOperand(NewDstIdx); unsigned NewReg = NewDstMO.getReg(); if (!NewDstMO.isKill() || TRI->regsOverlap(NewReg, SrcReg)) @@ -1658,9 +1658,9 @@ /// isSafeToDelete - Return true if this instruction doesn't produce any side /// effect and all of its defs are dead. static bool isSafeToDelete(MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); - if (TID.mayLoad() || TID.mayStore() || TID.isTerminator() || - TID.isCall() || TID.isBarrier() || TID.isReturn() || + const MCInstrDesc &MCID = MI.getDesc(); + if (MCID.mayLoad() || MCID.mayStore() || MCID.isTerminator() || + MCID.isCall() || MCID.isBarrier() || MCID.isReturn() || MI.isLabel() || MI.isDebugValue() || MI.hasUnmodeledSideEffects()) return false; Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Jun 28 14:10:37 2011 @@ -136,9 +136,9 @@ MachineInstr *UpdateMI = NULL; MachineInstr *MemMI = NULL; unsigned AddrMode = (TSFlags & ARMII::AddrModeMask); - const TargetInstrDesc &TID = MI->getDesc(); - unsigned NumOps = TID.getNumOperands(); - bool isLoad = !TID.mayStore(); + const MCInstrDesc &MCID = MI->getDesc(); + unsigned NumOps = MCID.getNumOperands(); + bool isLoad = !MCID.mayStore(); const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); const MachineOperand &Base = MI->getOperand(2); const MachineOperand &Offset = MI->getOperand(NumOps-3); @@ -475,8 +475,8 @@ bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI, std::vector &Pred) const { // FIXME: This confuses implicit_def with optional CPSR def. - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.getImplicitDefs() && !TID.hasOptionalDef()) + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.getImplicitDefs() && !MCID.hasOptionalDef()) return false; bool Found = false; @@ -495,11 +495,11 @@ /// By default, this returns true for every instruction with a /// PredicateOperand. bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const { - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.isPredicable()) + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.isPredicable()) return false; - if ((TID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { + if ((MCID.TSFlags & ARMII::DomainMask) == ARMII::DomainNEON) { ARMFunctionInfo *AFI = MI->getParent()->getParent()->getInfo(); return AFI->isThumb2Function(); @@ -525,8 +525,8 @@ const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); // Basic size info comes from the TSFlags field. - const TargetInstrDesc &TID = MI->getDesc(); - uint64_t TSFlags = TID.TSFlags; + const MCInstrDesc &MCID = MI->getDesc(); + uint64_t TSFlags = MCID.TSFlags; unsigned Opc = MI->getOpcode(); switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) { @@ -588,9 +588,9 @@ // entry is one byte; TBH two byte each. unsigned EntrySize = (Opc == ARM::t2TBB_JT) ? 1 : ((Opc == ARM::t2TBH_JT) ? 2 : 4); - unsigned NumOps = TID.getNumOperands(); + unsigned NumOps = MCID.getNumOperands(); MachineOperand JTOP = - MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2)); + MI->getOperand(NumOps - (MCID.isPredicable() ? 3 : 2)); unsigned JTI = JTOP.getIndex(); const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo(); assert(MJTI != 0); @@ -1363,7 +1363,7 @@ unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII) { unsigned Opcode = MI.getOpcode(); - const TargetInstrDesc &Desc = MI.getDesc(); + const MCInstrDesc &Desc = MI.getDesc(); unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); bool isSub = false; @@ -1803,7 +1803,7 @@ if (!ItinData || ItinData->isEmpty()) return 1; - const TargetInstrDesc &Desc = MI->getDesc(); + const MCInstrDesc &Desc = MI->getDesc(); unsigned Class = Desc.getSchedClass(); unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; if (UOps) @@ -1906,10 +1906,10 @@ int ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &DefTID, + const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const { - int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1; + int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; if (RegNo <= 0) // Def is the address writeback. return ItinData->getOperandCycle(DefClass, DefIdx); @@ -1924,7 +1924,7 @@ DefCycle = RegNo; bool isSLoad = false; - switch (DefTID.getOpcode()) { + switch (DefMCID.getOpcode()) { default: break; case ARM::VLDMSIA: case ARM::VLDMSIA_UPD: @@ -1947,10 +1947,10 @@ int ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &DefTID, + const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const { - int RegNo = (int)(DefIdx+1) - DefTID.getNumOperands() + 1; + int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1; if (RegNo <= 0) // Def is the address writeback. return ItinData->getOperandCycle(DefClass, DefIdx); @@ -1982,10 +1982,10 @@ int ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &UseTID, + const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const { - int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1; + int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; if (RegNo <= 0) return ItinData->getOperandCycle(UseClass, UseIdx); @@ -1999,7 +1999,7 @@ UseCycle = RegNo; bool isSStore = false; - switch (UseTID.getOpcode()) { + switch (UseMCID.getOpcode()) { default: break; case ARM::VSTMSIA: case ARM::VSTMSIA_UPD: @@ -2022,10 +2022,10 @@ int ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &UseTID, + const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const { - int RegNo = (int)(UseIdx+1) - UseTID.getNumOperands() + 1; + int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; if (RegNo <= 0) return ItinData->getOperandCycle(UseClass, UseIdx); @@ -2051,14 +2051,14 @@ int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData, - const TargetInstrDesc &DefTID, + const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, - const TargetInstrDesc &UseTID, + const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const { - unsigned DefClass = DefTID.getSchedClass(); - unsigned UseClass = UseTID.getSchedClass(); + unsigned DefClass = DefMCID.getSchedClass(); + unsigned UseClass = UseMCID.getSchedClass(); - if (DefIdx < DefTID.getNumDefs() && UseIdx < UseTID.getNumOperands()) + if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); // This may be a def / use of a variable_ops instruction, the operand @@ -2066,7 +2066,7 @@ // figure it out. int DefCycle = -1; bool LdmBypass = false; - switch (DefTID.getOpcode()) { + switch (DefMCID.getOpcode()) { default: DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); break; @@ -2077,7 +2077,7 @@ case ARM::VLDMSIA: case ARM::VLDMSIA_UPD: case ARM::VLDMSDB_UPD: - DefCycle = getVLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign); + DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); break; case ARM::LDMIA_RET: @@ -2098,7 +2098,7 @@ case ARM::t2LDMIA_UPD: case ARM::t2LDMDB_UPD: LdmBypass = 1; - DefCycle = getLDMDefCycle(ItinData, DefTID, DefClass, DefIdx, DefAlign); + DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign); break; } @@ -2107,7 +2107,7 @@ DefCycle = 2; int UseCycle = -1; - switch (UseTID.getOpcode()) { + switch (UseMCID.getOpcode()) { default: UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); break; @@ -2118,7 +2118,7 @@ case ARM::VSTMSIA: case ARM::VSTMSIA_UPD: case ARM::VSTMSDB_UPD: - UseCycle = getVSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign); + UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); break; case ARM::STMIA: @@ -2137,7 +2137,7 @@ case ARM::t2STMDB: case ARM::t2STMIA_UPD: case ARM::t2STMDB_UPD: - UseCycle = getSTMUseCycle(ItinData, UseTID, UseClass, UseIdx, UseAlign); + UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign); break; } @@ -2150,7 +2150,7 @@ if (LdmBypass) { // It's a variable_ops instruction so we can't use DefIdx here. Just use // first def operand. - if (ItinData->hasPipelineForwarding(DefClass, DefTID.getNumOperands()-1, + if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1, UseClass, UseIdx)) --UseCycle; } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx, @@ -2170,11 +2170,11 @@ DefMI->isRegSequence() || DefMI->isImplicitDef()) return 1; - const TargetInstrDesc &DefTID = DefMI->getDesc(); + const MCInstrDesc &DefMCID = DefMI->getDesc(); if (!ItinData || ItinData->isEmpty()) - return DefTID.mayLoad() ? 3 : 1; + return DefMCID.mayLoad() ? 3 : 1; - const TargetInstrDesc &UseTID = UseMI->getDesc(); + const MCInstrDesc &UseMCID = UseMI->getDesc(); const MachineOperand &DefMO = DefMI->getOperand(DefIdx); if (DefMO.getReg() == ARM::CPSR) { if (DefMI->getOpcode() == ARM::FMSTAT) { @@ -2183,7 +2183,7 @@ } // CPSR set and branch can be paired in the same cycle. - if (UseTID.isBranch()) + if (UseMCID.isBranch()) return 0; } @@ -2191,14 +2191,14 @@ ? (*DefMI->memoperands_begin())->getAlignment() : 0; unsigned UseAlign = UseMI->hasOneMemOperand() ? (*UseMI->memoperands_begin())->getAlignment() : 0; - int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign, - UseTID, UseIdx, UseAlign); + int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, + UseMCID, UseIdx, UseAlign); if (Latency > 1 && (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] // variants are one cycle cheaper. - switch (DefTID.getOpcode()) { + switch (DefMCID.getOpcode()) { default: break; case ARM::LDRrs: case ARM::LDRBrs: { @@ -2223,7 +2223,7 @@ } if (DefAlign < 8 && Subtarget.isCortexA9()) - switch (DefTID.getOpcode()) { + switch (DefMCID.getOpcode()) { default: break; case ARM::VLD1q8: case ARM::VLD1q16: @@ -2327,37 +2327,37 @@ if (!DefNode->isMachineOpcode()) return 1; - const TargetInstrDesc &DefTID = get(DefNode->getMachineOpcode()); + const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode()); - if (isZeroCost(DefTID.Opcode)) + if (isZeroCost(DefMCID.Opcode)) return 0; if (!ItinData || ItinData->isEmpty()) - return DefTID.mayLoad() ? 3 : 1; + return DefMCID.mayLoad() ? 3 : 1; if (!UseNode->isMachineOpcode()) { - int Latency = ItinData->getOperandCycle(DefTID.getSchedClass(), DefIdx); + int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); if (Subtarget.isCortexA9()) return Latency <= 2 ? 1 : Latency - 1; else return Latency <= 3 ? 1 : Latency - 2; } - const TargetInstrDesc &UseTID = get(UseNode->getMachineOpcode()); + const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode()); const MachineSDNode *DefMN = dyn_cast(DefNode); unsigned DefAlign = !DefMN->memoperands_empty() ? (*DefMN->memoperands_begin())->getAlignment() : 0; const MachineSDNode *UseMN = dyn_cast(UseNode); unsigned UseAlign = !UseMN->memoperands_empty() ? (*UseMN->memoperands_begin())->getAlignment() : 0; - int Latency = getOperandLatency(ItinData, DefTID, DefIdx, DefAlign, - UseTID, UseIdx, UseAlign); + int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, + UseMCID, UseIdx, UseAlign); if (Latency > 1 && (Subtarget.isCortexA8() || Subtarget.isCortexA9())) { // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2] // variants are one cycle cheaper. - switch (DefTID.getOpcode()) { + switch (DefMCID.getOpcode()) { default: break; case ARM::LDRrs: case ARM::LDRBrs: { @@ -2384,7 +2384,7 @@ } if (DefAlign < 8 && Subtarget.isCortexA9()) - switch (DefTID.getOpcode()) { + switch (DefMCID.getOpcode()) { default: break; case ARM::VLD1q8Pseudo: case ARM::VLD1q16Pseudo: @@ -2503,10 +2503,10 @@ if (!ItinData || ItinData->isEmpty()) return 1; - const TargetInstrDesc &TID = MI->getDesc(); - unsigned Class = TID.getSchedClass(); + const MCInstrDesc &MCID = MI->getDesc(); + unsigned Class = MCID.getSchedClass(); unsigned UOps = ItinData->Itineraries[Class].NumMicroOps; - if (PredCost && TID.hasImplicitDefOfPhysReg(ARM::CPSR)) + if (PredCost && MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) // When predicated, CPSR is an additional source operand for CPSR updating // instructions, this apparently increases their latencies. *PredCost = 1; Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Tue Jun 28 14:10:37 2011 @@ -353,25 +353,25 @@ SDNode *UseNode, unsigned UseIdx) const; private: int getVLDMDefCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &DefTID, + const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const; int getLDMDefCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &DefTID, + const MCInstrDesc &DefMCID, unsigned DefClass, unsigned DefIdx, unsigned DefAlign) const; int getVSTMUseCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &UseTID, + const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const; int getSTMUseCycle(const InstrItineraryData *ItinData, - const TargetInstrDesc &UseTID, + const MCInstrDesc &UseMCID, unsigned UseClass, unsigned UseIdx, unsigned UseAlign) const; int getOperandLatency(const InstrItineraryData *ItinData, - const TargetInstrDesc &DefTID, + const MCInstrDesc &DefMCID, unsigned DefIdx, unsigned DefAlign, - const TargetInstrDesc &UseTID, + const MCInstrDesc &UseMCID, unsigned UseIdx, unsigned UseAlign) const; int getInstrLatency(const InstrItineraryData *ItinData, Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Jun 28 14:10:37 2011 @@ -960,7 +960,7 @@ int64_t ARMBaseRegisterInfo:: getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const { - const TargetInstrDesc &Desc = MI->getDesc(); + const MCInstrDesc &Desc = MI->getDesc(); unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); int64_t InstrOffs = 0;; int Scale = 1; @@ -1110,11 +1110,11 @@ if (Ins != MBB->end()) DL = Ins->getDebugLoc(); - const TargetInstrDesc &TID = TII.get(ADDriOpc); + const MCInstrDesc &MCID = TII.get(ADDriOpc); MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); - MRI.constrainRegClass(BaseReg, TII.getRegClass(TID, 0, this)); + MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this)); - MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, TID, BaseReg) + MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg) .addFrameIndex(FrameIdx).addImm(Offset); if (!AFI->isThumb1OnlyFunction()) @@ -1150,7 +1150,7 @@ bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const { - const TargetInstrDesc &Desc = MI->getDesc(); + const MCInstrDesc &Desc = MI->getDesc(); unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); unsigned i = 0; Modified: llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMCodeEmitter.cpp Tue Jun 28 14:10:37 2011 @@ -96,13 +96,13 @@ void addPCLabel(unsigned LabelID); void emitPseudoInstruction(const MachineInstr &MI); unsigned getMachineSoRegOpValue(const MachineInstr &MI, - const TargetInstrDesc &TID, + const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx); unsigned getMachineSoImmOpValue(unsigned SoImm); unsigned getAddrModeSBit(const MachineInstr &MI, - const TargetInstrDesc &TID) const; + const MCInstrDesc &MCID) const; void emitDataProcessingInstruction(const MachineInstr &MI, unsigned ImplicitRd = 0, @@ -443,9 +443,9 @@ else if (MO.isSymbol()) emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch); else if (MO.isCPI()) { - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); // For VFP load, the immediate offset is multiplied by 4. - unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) + unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry; emitConstPoolAddress(MO.getIndex(), Reloc); } else if (MO.isJTI()) @@ -757,7 +757,7 @@ void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) { // It's basically add r, pc, (LJTI - $+8) - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); // Emit the 'add' instruction. unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100 @@ -766,7 +766,7 @@ Binary |= II->getPredicate(&MI) << ARMII::CondShift; // Encode S bit if MI modifies CPSR. - Binary |= getAddrModeSBit(MI, TID); + Binary |= getAddrModeSBit(MI, MCID); // Encode Rd. Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; @@ -912,7 +912,7 @@ } unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI, - const TargetInstrDesc &TID, + const MCInstrDesc &MCID, const MachineOperand &MO, unsigned OpIdx) { unsigned Binary = getMachineOpValue(MI, MO); @@ -982,8 +982,8 @@ } unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI, - const TargetInstrDesc &TID) const { - for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i >= e; --i){ + const MCInstrDesc &MCID) const { + for (unsigned i = MI.getNumOperands(), e = MCID.getNumOperands(); i >= e; --i){ const MachineOperand &MO = MI.getOperand(i-1); if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) return 1 << ARMII::S_BitShift; @@ -994,7 +994,7 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI, unsigned ImplicitRd, unsigned ImplicitRn) { - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1003,10 +1003,10 @@ Binary |= II->getPredicate(&MI) << ARMII::CondShift; // Encode S bit if MI modifies CPSR. - Binary |= getAddrModeSBit(MI, TID); + Binary |= getAddrModeSBit(MI, MCID); // Encode register def if there is one. - unsigned NumDefs = TID.getNumDefs(); + unsigned NumDefs = MCID.getNumDefs(); unsigned OpIdx = 0; if (NumDefs) Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; @@ -1014,7 +1014,7 @@ // Special handling for implicit use (e.g. PC). Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift); - if (TID.Opcode == ARM::MOVi16) { + if (MCID.Opcode == ARM::MOVi16) { // Get immediate from MI. unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx), ARM::reloc_arm_movw); @@ -1023,14 +1023,14 @@ Binary |= ((Lo16 >> 12) & 0xF) << 16; emitWordLE(Binary); return; - } else if(TID.Opcode == ARM::MOVTi16) { + } else if(MCID.Opcode == ARM::MOVTi16) { unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx), ARM::reloc_arm_movt) >> 16); Binary |= Hi16 & 0xFFF; Binary |= ((Hi16 >> 12) & 0xF) << 16; emitWordLE(Binary); return; - } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) { + } else if ((MCID.Opcode == ARM::BFC) || (MCID.Opcode == ARM::BFI)) { uint32_t v = ~MI.getOperand(2).getImm(); int32_t lsb = CountTrailingZeros_32(v); int32_t msb = (32 - CountLeadingZeros_32(v)) - 1; @@ -1039,7 +1039,7 @@ Binary |= (lsb & 0x1F) << 7; emitWordLE(Binary); return; - } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) { + } else if ((MCID.Opcode == ARM::UBFX) || (MCID.Opcode == ARM::SBFX)) { // Encode Rn in Instr{0-3} Binary |= getMachineOpValue(MI, OpIdx++); @@ -1054,11 +1054,11 @@ } // If this is a two-address operand, skip it. e.g. MOVCCr operand 1. - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) ++OpIdx; // Encode first non-shifter register operand if there is one. - bool isUnary = TID.TSFlags & ARMII::UnaryDP; + bool isUnary = MCID.TSFlags & ARMII::UnaryDP; if (!isUnary) { if (ImplicitRn) // Special handling for implicit use (e.g. PC). @@ -1071,9 +1071,9 @@ // Encode shifter operand. const MachineOperand &MO = MI.getOperand(OpIdx); - if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { + if ((MCID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) { // Encode SoReg. - emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx)); + emitWordLE(Binary | getMachineSoRegOpValue(MI, MCID, MO, OpIdx)); return; } @@ -1092,9 +1092,9 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI, unsigned ImplicitRd, unsigned ImplicitRn) { - const TargetInstrDesc &TID = MI.getDesc(); - unsigned Form = TID.TSFlags & ARMII::FormMask; - bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; + const MCInstrDesc &MCID = MI.getDesc(); + unsigned Form = MCID.TSFlags & ARMII::FormMask; + bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1134,7 +1134,7 @@ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; // If this is a two-address operand, skip it. e.g. LDR_PRE. - if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) ++OpIdx; const MachineOperand &MO2 = MI.getOperand(OpIdx); @@ -1170,9 +1170,9 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI, unsigned ImplicitRn) { - const TargetInstrDesc &TID = MI.getDesc(); - unsigned Form = TID.TSFlags & ARMII::FormMask; - bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0; + const MCInstrDesc &MCID = MI.getDesc(); + unsigned Form = MCID.TSFlags & ARMII::FormMask; + bool IsPrePost = (MCID.TSFlags & ARMII::IndexModeMask) != 0; // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1194,7 +1194,7 @@ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; // Skip LDRD and STRD's second operand. - if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD) + if (MCID.Opcode == ARM::LDRD || MCID.Opcode == ARM::STRD) ++OpIdx; // Set second operand @@ -1205,7 +1205,7 @@ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift; // If this is a two-address operand, skip it. e.g. LDRH_POST. - if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + if (!Skipped && MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) ++OpIdx; const MachineOperand &MO2 = MI.getOperand(OpIdx); @@ -1255,8 +1255,8 @@ } void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); - bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; + const MCInstrDesc &MCID = MI.getDesc(); + bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1295,7 +1295,7 @@ } void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1304,12 +1304,12 @@ Binary |= II->getPredicate(&MI) << ARMII::CondShift; // Encode S bit if MI modifies CPSR. - Binary |= getAddrModeSBit(MI, TID); + Binary |= getAddrModeSBit(MI, MCID); // 32x32->64bit operations have two destination registers. The number // of register definitions will tell us if that's what we're dealing with. unsigned OpIdx = 0; - if (TID.getNumDefs() == 2) + if (MCID.getNumDefs() == 2) Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift; // Encode Rd @@ -1323,16 +1323,16 @@ // Many multiple instructions (e.g. MLA) have three src operands. Encode // it as Rn (for multiply, that's in the same offset as RdLo. - if (TID.getNumOperands() > OpIdx && - !TID.OpInfo[OpIdx].isPredicate() && - !TID.OpInfo[OpIdx].isOptionalDef()) + if (MCID.getNumOperands() > OpIdx && + !MCID.OpInfo[OpIdx].isPredicate() && + !MCID.OpInfo[OpIdx].isOptionalDef()) Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift; emitWordLE(Binary); } void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1361,15 +1361,15 @@ // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand. if (MI.getOperand(OpIdx).isImm() && - !TID.OpInfo[OpIdx].isPredicate() && - !TID.OpInfo[OpIdx].isOptionalDef()) + !MCID.OpInfo[OpIdx].isPredicate() && + !MCID.OpInfo[OpIdx].isOptionalDef()) Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift; emitWordLE(Binary); } void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1378,7 +1378,7 @@ Binary |= II->getPredicate(&MI) << ARMII::CondShift; // PKH instructions are finished at this point - if (TID.Opcode == ARM::PKHBT || TID.Opcode == ARM::PKHTB) { + if (MCID.Opcode == ARM::PKHBT || MCID.Opcode == ARM::PKHTB) { emitWordLE(Binary); return; } @@ -1389,9 +1389,9 @@ Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift; const MachineOperand &MO = MI.getOperand(OpIdx++); - if (OpIdx == TID.getNumOperands() || - TID.OpInfo[OpIdx].isPredicate() || - TID.OpInfo[OpIdx].isOptionalDef()) { + if (OpIdx == MCID.getNumOperands() || + MCID.OpInfo[OpIdx].isPredicate() || + MCID.OpInfo[OpIdx].isOptionalDef()) { // Encode Rm and it's done. Binary |= getMachineOpValue(MI, MO); emitWordLE(Binary); @@ -1406,7 +1406,7 @@ // Encode shift_imm. unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); - if (TID.Opcode == ARM::PKHTB) { + if (MCID.Opcode == ARM::PKHTB) { assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); if (ShiftAmt == 32) ShiftAmt = 0; @@ -1418,7 +1418,7 @@ } void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); // Part of binary is determined by TableGen. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1431,11 +1431,11 @@ // Encode saturate bit position. unsigned Pos = MI.getOperand(1).getImm(); - if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16) + if (MCID.Opcode == ARM::SSAT || MCID.Opcode == ARM::SSAT16) Pos -= 1; assert((Pos < 16 || (Pos < 32 && - TID.Opcode != ARM::SSAT16 && - TID.Opcode != ARM::USAT16)) && + MCID.Opcode != ARM::SSAT16 && + MCID.Opcode != ARM::USAT16)) && "saturate bit position out of range"); Binary |= Pos << 16; @@ -1443,7 +1443,7 @@ Binary |= getMachineOpValue(MI, 2); // Encode shift_imm. - if (TID.getNumOperands() == 4) { + if (MCID.getNumOperands() == 4) { unsigned ShiftOp = MI.getOperand(3).getImm(); ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp); if (Opc == ARM_AM::asr) @@ -1459,9 +1459,9 @@ } void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); - if (TID.Opcode == ARM::TPsoft) { + if (MCID.Opcode == ARM::TPsoft) { llvm_unreachable("ARM::TPsoft FIXME"); // FIXME } @@ -1498,20 +1498,20 @@ } void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); // Handle jump tables. - if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) { + if (MCID.Opcode == ARM::BR_JTr || MCID.Opcode == ARM::BR_JTadd) { // First emit a ldr pc, [] instruction. emitDataProcessingInstruction(MI, ARM::PC); // Then emit the inline jump table. unsigned JTIndex = - (TID.Opcode == ARM::BR_JTr) + (MCID.Opcode == ARM::BR_JTr) ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex(); emitInlineJumpTable(JTIndex); return; - } else if (TID.Opcode == ARM::BR_JTm) { + } else if (MCID.Opcode == ARM::BR_JTm) { // First emit a ldr pc, [] instruction. emitLoadStoreInstruction(MI, ARM::PC); @@ -1526,7 +1526,7 @@ // Set the conditional execution predicate Binary |= II->getPredicate(&MI) << ARMII::CondShift; - if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR) + if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR) // The return register is LR. Binary |= getARMRegisterNumbering(ARM::LR); else @@ -1579,7 +1579,7 @@ } void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1596,16 +1596,16 @@ Binary |= encodeVFPRd(MI, OpIdx++); // If this is a two-address operand, skip it, e.g. FMACD. - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) ++OpIdx; // Encode Dn / Sn. - if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) + if ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm) Binary |= encodeVFPRn(MI, OpIdx++); - if (OpIdx == TID.getNumOperands() || - TID.OpInfo[OpIdx].isPredicate() || - TID.OpInfo[OpIdx].isOptionalDef()) { + if (OpIdx == MCID.getNumOperands() || + MCID.OpInfo[OpIdx].isPredicate() || + MCID.OpInfo[OpIdx].isOptionalDef()) { // FCMPEZD etc. has only one operand. emitWordLE(Binary); return; @@ -1618,8 +1618,8 @@ } void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); - unsigned Form = TID.TSFlags & ARMII::FormMask; + const MCInstrDesc &MCID = MI.getDesc(); + unsigned Form = MCID.TSFlags & ARMII::FormMask; // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1709,8 +1709,8 @@ void ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); - bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0; + const MCInstrDesc &MCID = MI.getDesc(); + bool IsUpdating = (MCID.TSFlags & ARMII::IndexModeMask) != 0; // Part of binary is determined by TableGn. unsigned Binary = getBinaryCodeForInstr(MI); @@ -1795,8 +1795,8 @@ unsigned Binary = getBinaryCodeForInstr(MI); unsigned RegTOpIdx, RegNOpIdx, LnOpIdx; - const TargetInstrDesc &TID = MI.getDesc(); - if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { + const MCInstrDesc &MCID = MI.getDesc(); + if ((MCID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) { RegTOpIdx = 0; RegNOpIdx = 1; LnOpIdx = 2; @@ -1863,12 +1863,12 @@ } void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); unsigned Binary = getBinaryCodeForInstr(MI); // Destination register is encoded in Dd; source register in Dm. unsigned OpIdx = 0; Binary |= encodeNEONRd(MI, OpIdx++); - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) ++OpIdx; Binary |= encodeNEONRm(MI, OpIdx); if (IsThumb) @@ -1878,15 +1878,15 @@ } void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) { - const TargetInstrDesc &TID = MI.getDesc(); + const MCInstrDesc &MCID = MI.getDesc(); unsigned Binary = getBinaryCodeForInstr(MI); // Destination register is encoded in Dd; source registers in Dn and Dm. unsigned OpIdx = 0; Binary |= encodeNEONRd(MI, OpIdx++); - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) ++OpIdx; Binary |= encodeNEONRn(MI, OpIdx++); - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) + if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) ++OpIdx; Binary |= encodeNEONRm(MI, OpIdx); if (IsThumb) Modified: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp Tue Jun 28 14:10:37 2011 @@ -1692,9 +1692,9 @@ const std::vector &JT = MJTI->getJumpTables(); for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) { MachineInstr *MI = T2JumpTables[i]; - const TargetInstrDesc &TID = MI->getDesc(); - unsigned NumOps = TID.getNumOperands(); - unsigned JTOpIdx = NumOps - (TID.isPredicable() ? 3 : 2); + const MCInstrDesc &MCID = MI->getDesc(); + unsigned NumOps = MCID.getNumOperands(); + unsigned JTOpIdx = NumOps - (MCID.isPredicable() ? 3 : 2); MachineOperand JTOP = MI->getOperand(JTOpIdx); unsigned JTI = JTOP.getIndex(); assert(JTI < JT.size()); @@ -1815,9 +1815,9 @@ const std::vector &JT = MJTI->getJumpTables(); for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) { MachineInstr *MI = T2JumpTables[i]; - const TargetInstrDesc &TID = MI->getDesc(); - unsigned NumOps = TID.getNumOperands(); - unsigned JTOpIdx = NumOps - (TID.isPredicable() ? 3 : 2); + const MCInstrDesc &MCID = MI->getDesc(); + unsigned NumOps = MCID.getNumOperands(); + unsigned JTOpIdx = NumOps - (MCID.isPredicable() ? 3 : 2); MachineOperand JTOP = MI->getOperand(JTOpIdx); unsigned JTI = JTOP.getIndex(); assert(JTI < JT.size()); Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Tue Jun 28 14:10:37 2011 @@ -68,7 +68,7 @@ void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI) { - const TargetInstrDesc &Desc = OldMI.getDesc(); + const MCInstrDesc &Desc = OldMI.getDesc(); for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); i != e; ++i) { const MachineOperand &MO = OldMI.getOperand(i); Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Jun 28 14:10:37 2011 @@ -219,8 +219,8 @@ // we don't care about implicit defs here, just places we'll need to add a // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR. bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.hasOptionalDef()) + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.hasOptionalDef()) return false; // Look to see if our OptionalDef is defining CPSR or CCR. @@ -234,15 +234,15 @@ } bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) { - const TargetInstrDesc &TID = MI->getDesc(); + const MCInstrDesc &MCID = MI->getDesc(); // If we're a thumb2 or not NEON function we were handled via isPredicable. - if ((TID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON || + if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON || AFI->isThumb2Function()) return false; - for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) - if (TID.OpInfo[i].isPredicate()) + for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) + if (MCID.OpInfo[i].isPredicate()) return true; return false; @@ -278,7 +278,7 @@ unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode, const TargetRegisterClass* RC) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)); return ResultReg; @@ -288,7 +288,7 @@ const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -308,7 +308,7 @@ unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -331,7 +331,7 @@ unsigned Op1, bool Op1IsKill, unsigned Op2, bool Op2IsKill) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -355,7 +355,7 @@ unsigned Op0, bool Op0IsKill, uint64_t Imm) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -377,7 +377,7 @@ unsigned Op0, bool Op0IsKill, const ConstantFP *FPImm) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -400,7 +400,7 @@ unsigned Op1, bool Op1IsKill, uint64_t Imm) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -423,7 +423,7 @@ const TargetRegisterClass *RC, uint64_t Imm) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) @@ -442,7 +442,7 @@ const TargetRegisterClass *RC, uint64_t Imm1, uint64_t Imm2) { unsigned ResultReg = createResultReg(RC); - const TargetInstrDesc &II = TII.get(MachineInstOpcode); + const MCInstrDesc &II = TII.get(MachineInstOpcode); if (II.getNumDefs() >= 1) AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) Modified: llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMHazardRecognizer.cpp Tue Jun 28 14:10:37 2011 @@ -19,11 +19,11 @@ static bool hasRAWHazard(MachineInstr *DefMI, MachineInstr *MI, const TargetRegisterInfo &TRI) { // FIXME: Detect integer instructions properly. - const TargetInstrDesc &TID = MI->getDesc(); - unsigned Domain = TID.TSFlags & ARMII::DomainMask; - if (TID.mayStore()) + const MCInstrDesc &MCID = MI->getDesc(); + unsigned Domain = MCID.TSFlags & ARMII::DomainMask; + if (MCID.mayStore()) return false; - unsigned Opcode = TID.getOpcode(); + unsigned Opcode = MCID.getOpcode(); if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) return false; if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON)) @@ -43,15 +43,15 @@ // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following // a VMLA / VMLS will cause 4 cycle stall. - const TargetInstrDesc &TID = MI->getDesc(); - if (LastMI && (TID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { + const MCInstrDesc &MCID = MI->getDesc(); + if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { MachineInstr *DefMI = LastMI; - const TargetInstrDesc &LastTID = LastMI->getDesc(); + const MCInstrDesc &LastMCID = LastMI->getDesc(); // Skip over one non-VFP / NEON instruction. - if (!LastTID.isBarrier() && + if (!LastMCID.isBarrier() && // On A9, AGU and NEON/FPU are muxed. - !(STI.isCortexA9() && (LastTID.mayLoad() || LastTID.mayStore())) && - (LastTID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { + !(STI.isCortexA9() && (LastMCID.mayLoad() || LastMCID.mayStore())) && + (LastMCID.TSFlags & ARMII::DomainMask) == ARMII::DomainGeneral) { MachineBasicBlock::iterator I = LastMI; if (I != LastMI->getParent()->begin()) { I = llvm::prior(I); Modified: llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelDAGToDAG.cpp Tue Jun 28 14:10:37 2011 @@ -329,10 +329,10 @@ if (Use->getOpcode() == ISD::CopyToReg) return true; if (Use->isMachineOpcode()) { - const TargetInstrDesc &TID = TII->get(Use->getMachineOpcode()); - if (TID.mayStore()) + const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode()); + if (MCID.mayStore()) return true; - unsigned Opcode = TID.getOpcode(); + unsigned Opcode = MCID.getOpcode(); if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) return true; // vmlx feeding into another vmlx. We actually want to unfold Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Tue Jun 28 14:10:37 2011 @@ -977,12 +977,12 @@ // Load are scheduled for latency even if there instruction itinerary // is not available. const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); - const TargetInstrDesc &TID = TII->get(N->getMachineOpcode()); + const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); - if (TID.getNumDefs() == 0) + if (MCID.getNumDefs() == 0) return Sched::RegPressure; if (!Itins->isEmpty() && - Itins->getOperandCycle(TID.getSchedClass(), 0) > 2) + Itins->getOperandCycle(MCID.getSchedClass(), 0) > 2) return Sched::Latency; return Sched::RegPressure; Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Tue Jun 28 14:10:37 2011 @@ -1461,19 +1461,19 @@ while (++I != E) { if (I->isDebugValue() || MemOps.count(&*I)) continue; - const TargetInstrDesc &TID = I->getDesc(); - if (TID.isCall() || TID.isTerminator() || I->hasUnmodeledSideEffects()) + const MCInstrDesc &MCID = I->getDesc(); + if (MCID.isCall() || MCID.isTerminator() || I->hasUnmodeledSideEffects()) return false; - if (isLd && TID.mayStore()) + if (isLd && MCID.mayStore()) return false; if (!isLd) { - if (TID.mayLoad()) + if (MCID.mayLoad()) return false; // It's not safe to move the first 'str' down. // str r1, [r0] // strh r5, [r0] // str r4, [r0, #+4] - if (TID.mayStore()) + if (MCID.mayStore()) return false; } for (unsigned j = 0, NumOps = I->getNumOperands(); j != NumOps; ++j) { @@ -1672,14 +1672,14 @@ Ops.pop_back(); Ops.pop_back(); - const TargetInstrDesc &TID = TII->get(NewOpc); - const TargetRegisterClass *TRC = TII->getRegClass(TID, 0, TRI); + const MCInstrDesc &MCID = TII->get(NewOpc); + const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI); MRI->constrainRegClass(EvenReg, TRC); MRI->constrainRegClass(OddReg, TRC); // Form the pair instruction. if (isLd) { - MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TID) + MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID) .addReg(EvenReg, RegState::Define) .addReg(OddReg, RegState::Define) .addReg(BaseReg); @@ -1691,7 +1691,7 @@ MIB.addImm(Offset).addImm(Pred).addReg(PredReg); ++NumLDRDFormed; } else { - MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, TID) + MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID) .addReg(EvenReg) .addReg(OddReg) .addReg(BaseReg); @@ -1742,8 +1742,8 @@ while (MBBI != E) { for (; MBBI != E; ++MBBI) { MachineInstr *MI = MBBI; - const TargetInstrDesc &TID = MI->getDesc(); - if (TID.isCall() || TID.isTerminator()) { + const MCInstrDesc &MCID = MI->getDesc(); + if (MCID.isCall() || MCID.isTerminator()) { // Stop at barriers. ++MBBI; break; Modified: llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMMCCodeEmitter.cpp Tue Jun 28 14:10:37 2011 @@ -1274,7 +1274,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups) const { // Pseudo instructions don't get encoded. - const TargetInstrDesc &Desc = TII.get(MI.getOpcode()); + const MCInstrDesc &Desc = TII.get(MI.getOpcode()); uint64_t TSFlags = Desc.TSFlags; if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo) return; Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Jun 28 14:10:37 2011 @@ -24,8 +24,8 @@ //#define DEBUG(X) do { X; } while (0) /// ARMGenInstrInfo.inc - ARMGenInstrInfo.inc contains the static const -/// TargetInstrDesc ARMInsts[] definition and the TargetOperandInfo[]'s -/// describing the operand info for each ARMInsts[i]. +/// MCInstrDesc ARMInsts[] definition and the MCOperandInfo[]'s describing the +/// operand info for each ARMInsts[i]. /// /// Together with an instruction's encoding format, we can take advantage of the /// NumOperands and the OpInfo fields of the target instruction description in @@ -46,10 +46,10 @@ /// dag DefaultOps = (ops (i32 14), (i32 zero_reg)); /// } /// -/// which is manifested by the TargetOperandInfo[] of: +/// which is manifested by the MCOperandInfo[] of: /// -/// { 0, 0|(1<> ARMII::IndexModeShift; + (MCID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, slice(insn, 7, 0) << 2, ARM_AM::no_shift, IndexMode); MI.addOperand(MCOperand::CreateImm(Offset)); @@ -802,7 +802,7 @@ if (CoprocessorOpcode(Opcode)) return DisassembleCoprocessor(MI, Opcode, insn, NumOps, NumOpsAdded, B); - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; // MRS and MRSsys take one GPR reg Rd. @@ -901,7 +901,7 @@ static bool DisassembleBrMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; unsigned &OpIdx = NumOpsAdded; @@ -976,10 +976,10 @@ static bool DisassembleDPFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - unsigned short NumDefs = TID.getNumDefs(); - bool isUnary = isUnaryDP(TID.TSFlags); - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + unsigned short NumDefs = MCID.getNumDefs(); + bool isUnary = isUnaryDP(MCID.TSFlags); + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -1041,7 +1041,7 @@ } // If this is a two-address operand, skip it, e.g., MOVCCr operand 1. - if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) { + if (isUnary && (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)) { MI.addOperand(MCOperand::CreateReg(0)); ++OpIdx; } @@ -1089,10 +1089,10 @@ static bool DisassembleDPSoRegFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - unsigned short NumDefs = TID.getNumDefs(); - bool isUnary = isUnaryDP(TID.TSFlags); - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + unsigned short NumDefs = MCID.getNumDefs(); + bool isUnary = isUnaryDP(MCID.TSFlags); + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -1118,7 +1118,7 @@ } // If this is a two-address operand, skip it, e.g., MOVCCs operand 1. - if (isUnary && (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) { + if (isUnary && (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)) { MI.addOperand(MCOperand::CreateReg(0)); ++OpIdx; } @@ -1244,17 +1244,17 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - bool isPrePost = isPrePostLdSt(TID.TSFlags); - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + bool isPrePost = isPrePostLdSt(MCID.TSFlags); + const MCOperandInfo *OpInfo = MCID.OpInfo; if (!OpInfo) return false; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; - assert(((!isStore && TID.getNumDefs() > 0) || - (isStore && (TID.getNumDefs() == 0 || isPrePost))) + assert(((!isStore && MCID.getNumDefs() > 0) || + (isStore && (MCID.getNumDefs() == 0 || isPrePost))) && "Invalid arguments"); // Operand 0 of a pre- and post-indexed store is the address base writeback. @@ -1291,7 +1291,7 @@ assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && "Reg operand expected"); - assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) + assert((!isPrePost || (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)) && "Index mode or tied_to operand expected"); MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn)))); @@ -1308,7 +1308,7 @@ ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub; unsigned IndexMode = - (TID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; + (MCID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; if (getIBit(insn) == 0) { // For pre- and post-indexed case, add a reg0 operand (Addressing Mode #2). // Otherwise, skip the reg operand since for addrmode_imm12, Rn has already @@ -1379,17 +1379,17 @@ static bool DisassembleLdStMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, bool isStore, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - bool isPrePost = isPrePostLdSt(TID.TSFlags); - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + bool isPrePost = isPrePostLdSt(MCID.TSFlags); + const MCOperandInfo *OpInfo = MCID.OpInfo; if (!OpInfo) return false; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; - assert(((!isStore && TID.getNumDefs() > 0) || - (isStore && (TID.getNumDefs() == 0 || isPrePost))) + assert(((!isStore && MCID.getNumDefs() > 0) || + (isStore && (MCID.getNumDefs() == 0 || isPrePost))) && "Invalid arguments"); // Operand 0 of a pre- and post-indexed store is the address base writeback. @@ -1433,7 +1433,7 @@ assert(OpInfo[OpIdx].RegClass == ARM::GPRRegClassID && "Reg operand expected"); - assert((!isPrePost || (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)) + assert((!isPrePost || (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1)) && "Offset mode or tied_to operand expected"); MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, decodeRn(insn)))); @@ -1451,7 +1451,7 @@ ARM_AM::AddrOpc AddrOpcode = getUBit(insn) ? ARM_AM::add : ARM_AM::sub; unsigned IndexMode = - (TID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; + (MCID.TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift; if (getAM3IBit(insn) == 1) { MI.addOperand(MCOperand::CreateReg(0)); @@ -1539,7 +1539,7 @@ static bool DisassembleLdStExFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; unsigned &OpIdx = NumOpsAdded; @@ -1591,7 +1591,7 @@ static bool DisassembleArithMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -1653,8 +1653,8 @@ if (decodeRd(insn) == 15 || decodeRm(insn) == 15) return false; - const TargetInstrDesc &TID = ARMInsts[Opcode]; - NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands + const MCInstrDesc &MCID = ARMInsts[Opcode]; + NumOpsAdded = MCID.getNumOperands() - 2; // ignore predicate operands // Disassemble register def. MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, @@ -1696,7 +1696,7 @@ if (decodeRd(insn) == 15 || decodeRm(insn) == 15) return false; - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -1802,7 +1802,7 @@ assert(NumOps >= 1 && "VFPUnaryFrm expects NumOps >= 1"); - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -1842,8 +1842,8 @@ assert(NumOps >= 3 && "VFPBinaryFrm expects NumOps >= 3"); - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -1858,7 +1858,7 @@ ++OpIdx; // Skip tied_to operand constraint. - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) { + if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) { assert(NumOps >= 4 && "Expect >=4 operands"); MI.addOperand(MCOperand::CreateReg(0)); ++OpIdx; @@ -1886,8 +1886,8 @@ assert(NumOps >= 2 && "VFPConv1Frm expects NumOps >= 2"); - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; if (!OpInfo) return false; bool SP = slice(insn, 8, 8) == 0; // A8.6.295 & A8.6.297 @@ -1903,7 +1903,7 @@ getRegisterEnum(B, RegClassID, decodeVFPRd(insn, SP)))); - assert(TID.getOperandConstraint(1, TOI::TIED_TO) != -1 && + assert(MCID.getOperandConstraint(1, MCOI::TIED_TO) != -1 && "Tied to operand expected"); MI.addOperand(MI.getOperand(0)); @@ -1961,7 +1961,7 @@ assert(NumOps >= 3 && "VFPConv3Frm expects NumOps >= 3"); - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; unsigned &OpIdx = NumOpsAdded; MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, @@ -2011,7 +2011,7 @@ assert(NumOps >= 3 && "VFPConv5Frm expects NumOps >= 3"); - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -2136,7 +2136,7 @@ static bool DisassembleVFPMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -2402,8 +2402,8 @@ unsigned short NumOps, unsigned &NumOpsAdded, bool Store, bool DblSpaced, unsigned alignment, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; // At least one DPR register plus addressing mode #6. assert(NumOps >= 3 && "Expect >= 3 operands"); @@ -2507,7 +2507,7 @@ } while (OpIdx < NumOps && (unsigned)OpInfo[OpIdx].RegClass == RegClass) { - assert(TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1 && + assert(MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1 && "Tied to operand expected"); MI.addOperand(MCOperand::CreateReg(0)); ++OpIdx; @@ -2757,8 +2757,8 @@ static bool DisassembleN1RegModImmFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; assert(NumOps >= 2 && (OpInfo[0].RegClass == ARM::DPRRegClassID || @@ -2848,8 +2848,8 @@ static bool DisassembleNVdVmOptImm(MCInst &MI, unsigned Opc, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, N2VFlag Flag, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opc]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opc]; + const MCOperandInfo *OpInfo = MCID.OpInfo; assert(NumOps >= 2 && (OpInfo[0].RegClass == ARM::DPRRegClassID || @@ -2878,7 +2878,7 @@ ++OpIdx; // VPADAL... - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) { + if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) { // TIED_TO operand. MI.addOperand(MCOperand::CreateReg(0)); ++OpIdx; @@ -2892,7 +2892,7 @@ // VZIP and others have two TIED_TO reg operands. int Idx; while (OpIdx < NumOps && - (Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) { + (Idx = MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO)) != -1) { // Add TIED_TO operand. MI.addOperand(MI.getOperand(Idx)); ++OpIdx; @@ -2945,8 +2945,8 @@ static bool DisassembleNVectorShift(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, bool LeftShift, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; assert(NumOps >= 3 && (OpInfo[0].RegClass == ARM::DPRRegClassID || @@ -2964,7 +2964,7 @@ decodeNEONRd(insn)))); ++OpIdx; - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) { + if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) { // TIED_TO operand. MI.addOperand(MCOperand::CreateReg(0)); ++OpIdx; @@ -3044,8 +3044,8 @@ static bool DisassembleNVdVnVmOptImm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, N3VFlag Flag, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; // No checking for OpInfo[2] because of MOVDneon/MOVQ with only two regs. assert(NumOps >= 3 && @@ -3076,7 +3076,7 @@ ++OpIdx; // VABA, VABAL, VBSLd, VBSLq, ... - if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) { + if (MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO) != -1) { // TIED_TO operand. MI.addOperand(MCOperand::CreateReg(0)); ++OpIdx; @@ -3163,8 +3163,8 @@ static bool DisassembleNVTBLFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; if (!OpInfo) return false; assert(NumOps >= 3 && @@ -3192,7 +3192,7 @@ // Process tied_to operand constraint. int Idx; - if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) { + if ((Idx = MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO)) != -1) { MI.addOperand(MI.getOperand(Idx)); ++OpIdx; } @@ -3221,11 +3221,11 @@ static bool DisassembleNGetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; if (!OpInfo) return false; - assert(TID.getNumDefs() == 1 && NumOps >= 3 && + assert(MCID.getNumDefs() == 1 && NumOps >= 3 && OpInfo[0].RegClass == ARM::GPRRegClassID && OpInfo[1].RegClass == ARM::DPRRegClassID && OpInfo[2].RegClass < 0 && @@ -3255,14 +3255,14 @@ static bool DisassembleNSetLnFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; if (!OpInfo) return false; - assert(TID.getNumDefs() == 1 && NumOps >= 3 && + assert(MCID.getNumDefs() == 1 && NumOps >= 3 && OpInfo[0].RegClass == ARM::DPRRegClassID && OpInfo[1].RegClass == ARM::DPRRegClassID && - TID.getOperandConstraint(1, TOI::TIED_TO) != -1 && + MCID.getOperandConstraint(1, MCOI::TIED_TO) != -1 && OpInfo[2].RegClass == ARM::GPRRegClassID && OpInfo[3].RegClass < 0 && "Expect >= 3 operands with one dst operand"); @@ -3294,7 +3294,7 @@ static bool DisassembleNDupFrm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; assert(NumOps >= 2 && (OpInfo[0].RegClass == ARM::DPRRegClassID || @@ -3604,11 +3604,11 @@ assert(NumOpsRemaining > 0 && "Invalid argument"); - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; unsigned Idx = MI.getNumOperands(); // First, we check whether this instr specifies the PredicateOperand through - // a pair of TargetOperandInfos with isPredicate() property. + // a pair of MCOperandInfos with isPredicate() property. if (NumOpsRemaining >= 2 && OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() && OpInfo[Idx].RegClass < 0 && @@ -3636,13 +3636,13 @@ assert(NumOpsRemaining > 0 && "Invalid argument"); - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; const std::string &Name = ARMInsts[Opcode].Name; unsigned Idx = MI.getNumOperands(); uint64_t TSFlags = ARMInsts[Opcode].TSFlags; // First, we check whether this instr specifies the PredicateOperand through - // a pair of TargetOperandInfos with isPredicate() property. + // a pair of MCOperandInfos with isPredicate() property. if (NumOpsRemaining >= 2 && OpInfo[Idx].isPredicate() && OpInfo[Idx+1].isPredicate() && OpInfo[Idx].RegClass < 0 && Modified: llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h Tue Jun 28 14:10:37 2011 @@ -350,7 +350,7 @@ static bool DisassembleThumb1General(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -425,8 +425,8 @@ static bool DisassembleThumb1DP(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -454,7 +454,7 @@ assert(OpIdx < NumOps && OpInfo[OpIdx].RegClass == ARM::tGPRRegClassID && "Thumb reg operand expected"); int Idx; - if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) { + if ((Idx = MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO)) != -1) { // The reg operand is tied to the first reg operand. MI.addOperand(MI.getOperand(Idx)); ++OpIdx; @@ -511,8 +511,8 @@ return true; } - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -530,7 +530,7 @@ assert(OpIdx < NumOps && "More operands expected"); int Idx; - if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) { + if ((Idx = MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO)) != -1) { // The reg operand is tied to the first reg operand. MI.addOperand(MI.getOperand(Idx)); ++OpIdx; @@ -554,7 +554,7 @@ static bool DisassembleThumb1LdPC(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID && @@ -602,7 +602,7 @@ static bool DisassembleThumb2Ldpci(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; assert(NumOps >= 2 && @@ -630,8 +630,8 @@ static bool DisassembleThumb1LdSt(unsigned opA, MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; assert(NumOps >= 2 @@ -680,7 +680,7 @@ assert((Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) && "Unexpected opcode"); - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; assert(NumOps >= 3 && @@ -708,7 +708,7 @@ assert(Opcode == ARM::tADDrPCi && "Unexpected opcode"); - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID && @@ -733,7 +733,7 @@ assert(Opcode == ARM::tADDrSPi && "Unexpected opcode"); - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; assert(NumOps >= 3 && @@ -810,7 +810,7 @@ if (Opcode == ARM::tPUSH || Opcode == ARM::tPOP) return DisassembleThumb1PushPop(MI, Opcode, insn, NumOps, NumOpsAdded, B); - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; // Predicate operands are handled elsewhere. if (NumOps == 2 && @@ -958,7 +958,7 @@ if (Opcode == ARM::tTRAP) return true; - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; assert(NumOps == 3 && OpInfo[0].RegClass < 0 && @@ -989,7 +989,7 @@ static bool DisassembleThumb1Br(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; assert(NumOps == 1 && OpInfo[0].RegClass < 0 && "1 imm operand expected"); @@ -1226,7 +1226,7 @@ static bool DisassembleThumb2LdStEx(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; unsigned &OpIdx = NumOpsAdded; @@ -1316,7 +1316,7 @@ static bool DisassembleThumb2LdStDual(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; if (!OpInfo) return false; assert(NumOps >= 4 @@ -1423,8 +1423,8 @@ static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; // Special case handling. @@ -1467,7 +1467,7 @@ if (ThreeReg) { int Idx; - if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) { + if ((Idx = MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO)) != -1) { // Process tied_to operand constraint. MI.addOperand(MI.getOperand(Idx)); ++OpIdx; @@ -1521,8 +1521,8 @@ static bool DisassembleThumb2DPModImm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -1550,7 +1550,7 @@ return false; } int Idx; - if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) { + if ((Idx = MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO)) != -1) { // The reg operand is tied to the first reg operand. MI.addOperand(MI.getOperand(Idx)); } else { @@ -1590,8 +1590,8 @@ /// o t2SSAT16, t2USAT16: Rs sat_pos Rn static bool DisassembleThumb2Sat(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - NumOpsAdded = TID.getNumOperands() - 2; // ignore predicate operands + const MCInstrDesc &MCID = ARMInsts[Opcode]; + NumOpsAdded = MCID.getNumOperands() - 2; // ignore predicate operands // Disassemble the register def. MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID, @@ -1635,8 +1635,8 @@ static bool DisassembleThumb2DPBinImm(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -1659,7 +1659,7 @@ if (TwoReg) { assert(NumOps >= 3 && "Expect >= 3 operands"); int Idx; - if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) { + if ((Idx = MCID.getOperandConstraint(OpIdx, MCOI::TIED_TO)) != -1) { // Process tied_to operand constraint. MI.addOperand(MI.getOperand(Idx)); } else { @@ -1907,8 +1907,8 @@ // t2PLDs: Rn Rm imm2=Inst{5-4} // Same pattern applies for t2PLDW* and t2PLI*. - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -2073,8 +2073,8 @@ // See, for example, A6.3.7 Load word: Table A6-18 Load word. if (Load && Rn == 15) return DisassembleThumb2Ldpci(MI, Opcode, insn, NumOps, NumOpsAdded, B); - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -2085,7 +2085,7 @@ "Expect >= 3 operands and first two as reg operands"); bool ThreeReg = (OpInfo[2].RegClass > 0); - bool TIED_TO = ThreeReg && TID.getOperandConstraint(2, TOI::TIED_TO) != -1; + bool TIED_TO = ThreeReg && MCID.getOperandConstraint(2, MCOI::TIED_TO) != -1; bool Imm12 = !ThreeReg && slice(insn, 23, 23) == 1; // ARMInstrThumb2.td // Build the register operands, followed by the immediate. @@ -2160,8 +2160,8 @@ static bool DisassembleThumb2DPReg(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetInstrDesc &TID = ARMInsts[Opcode]; - const TargetOperandInfo *OpInfo = TID.OpInfo; + const MCInstrDesc &MCID = ARMInsts[Opcode]; + const MCOperandInfo *OpInfo = MCID.OpInfo; unsigned &OpIdx = NumOpsAdded; OpIdx = 0; @@ -2214,7 +2214,7 @@ static bool DisassembleThumb2Mul(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; assert(NumOps >= 3 && OpInfo[0].RegClass == ARM::rGPRRegClassID && @@ -2259,7 +2259,7 @@ static bool DisassembleThumb2LongMul(MCInst &MI, unsigned Opcode, uint32_t insn, unsigned short NumOps, unsigned &NumOpsAdded, BO B) { - const TargetOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; + const MCOperandInfo *OpInfo = ARMInsts[Opcode].OpInfo; assert(NumOps >= 3 && OpInfo[0].RegClass == ARM::rGPRRegClassID && Modified: llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp (original) +++ llvm/trunk/lib/Target/ARM/MLxExpansionPass.cpp Tue Jun 28 14:10:37 2011 @@ -137,11 +137,11 @@ bool MLxExpansion::hasRAWHazard(unsigned Reg, MachineInstr *MI) const { // FIXME: Detect integer instructions properly. - const TargetInstrDesc &TID = MI->getDesc(); - unsigned Domain = TID.TSFlags & ARMII::DomainMask; - if (TID.mayStore()) + const MCInstrDesc &MCID = MI->getDesc(); + unsigned Domain = MCID.TSFlags & ARMII::DomainMask; + if (MCID.mayStore()) return false; - unsigned Opcode = TID.getOpcode(); + unsigned Opcode = MCID.getOpcode(); if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD) return false; if ((Domain & ARMII::DomainVFP) || (Domain & ARMII::DomainNEON)) @@ -218,18 +218,18 @@ ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NextOp).getImm(); unsigned PredReg = MI->getOperand(++NextOp).getReg(); - const TargetInstrDesc &TID1 = TII->get(MulOpc); - const TargetInstrDesc &TID2 = TII->get(AddSubOpc); - unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(TID1, 0, TRI)); + const MCInstrDesc &MCID1 = TII->get(MulOpc); + const MCInstrDesc &MCID2 = TII->get(AddSubOpc); + unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI)); - MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), TID1, TmpReg) + MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), MCID1, TmpReg) .addReg(Src1Reg, getKillRegState(Src1Kill)) .addReg(Src2Reg, getKillRegState(Src2Kill)); if (HasLane) MIB.addImm(LaneImm); MIB.addImm(Pred).addReg(PredReg); - MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), TID2) + MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), MCID2) .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); if (NegAcc) { @@ -273,15 +273,15 @@ continue; } - const TargetInstrDesc &TID = MI->getDesc(); - if (TID.isBarrier()) { + const MCInstrDesc &MCID = MI->getDesc(); + if (MCID.isBarrier()) { clearStack(); Skip = 0; ++MII; continue; } - unsigned Domain = TID.TSFlags & ARMII::DomainMask; + unsigned Domain = MCID.TSFlags & ARMII::DomainMask; if (Domain == ARMII::DomainGeneral) { if (++Skip == 2) // Assume dual issues of non-VFP / NEON instructions. @@ -291,7 +291,7 @@ unsigned MulOpc, AddSubOpc; bool NegAcc, HasLane; - if (!TII->isFpMLxInstruction(TID.getOpcode(), + if (!TII->isFpMLxInstruction(MCID.getOpcode(), MulOpc, AddSubOpc, NegAcc, HasLane) || !FindMLxHazard(MI)) pushStack(MI); Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Tue Jun 28 14:10:37 2011 @@ -239,9 +239,9 @@ unsigned Chunk = (1 << 3) - 1; unsigned ThisVal = (Bytes > Chunk) ? Chunk : Bytes; Bytes -= ThisVal; - const TargetInstrDesc &TID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); + const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); const MachineInstrBuilder MIB = - AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg).setMIFlags(MIFlags)); + AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg).setMIFlags(MIFlags)); AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal)); } else { BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg) @@ -291,8 +291,8 @@ } if (ExtraOpc) { - const TargetInstrDesc &TID = TII.get(ExtraOpc); - AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg)) + const MCInstrDesc &MCID = TII.get(ExtraOpc); + AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) .addReg(DestReg, RegState::Kill) .addImm(((unsigned)NumBytes) & 3) .setMIFlags(MIFlags)); @@ -360,8 +360,8 @@ if (Imm > 0) emitThumbRegPlusImmediate(MBB, MBBI, dl, DestReg, DestReg, Imm, TII, MRI); if (isSub) { - const TargetInstrDesc &TID = TII.get(ARM::tRSB); - AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, TID, DestReg)) + const MCInstrDesc &MCID = TII.get(ARM::tRSB); + AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) .addReg(DestReg, RegState::Kill)); } } @@ -396,7 +396,7 @@ MachineBasicBlock &MBB = *MI.getParent(); DebugLoc dl = MI.getDebugLoc(); unsigned Opcode = MI.getOpcode(); - const TargetInstrDesc &Desc = MI.getDesc(); + const MCInstrDesc &Desc = MI.getDesc(); unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); if (Opcode == ARM::tADDrSPi) { @@ -653,7 +653,7 @@ assert(Offset && "This code isn't needed if offset already handled!"); unsigned Opcode = MI.getOpcode(); - const TargetInstrDesc &Desc = MI.getDesc(); + const MCInstrDesc &Desc = MI.getDesc(); // Remove predicate first. int PIdx = MI.findFirstPredOperandIdx(); Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Tue Jun 28 14:10:37 2011 @@ -396,7 +396,7 @@ unsigned FrameReg, int &Offset, const ARMBaseInstrInfo &TII) { unsigned Opcode = MI.getOpcode(); - const TargetInstrDesc &Desc = MI.getDesc(); + const MCInstrDesc &Desc = MI.getDesc(); unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask); bool isSub = false; Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Tue Jun 28 14:10:37 2011 @@ -189,8 +189,8 @@ } } -static bool HasImplicitCPSRDef(const TargetInstrDesc &TID) { - for (const unsigned *Regs = TID.ImplicitDefs; *Regs; ++Regs) +static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { + for (const unsigned *Regs = MCID.ImplicitDefs; *Regs; ++Regs) if (*Regs == ARM::CPSR) return true; return false; @@ -484,8 +484,8 @@ if (Entry.LowRegs1 && !VerifyLowRegs(MI)) return false; - const TargetInstrDesc &TID = MI->getDesc(); - if (TID.mayLoad() || TID.mayStore()) + const MCInstrDesc &MCID = MI->getDesc(); + if (MCID.mayLoad() || MCID.mayStore()) return ReduceLoadStore(MBB, MI, Entry); unsigned Opc = MI->getOpcode(); @@ -576,23 +576,23 @@ } // Check if it's possible / necessary to transfer the predicate. - const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc2); + const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2); unsigned PredReg = 0; ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); bool SkipPred = false; if (Pred != ARMCC::AL) { - if (!NewTID.isPredicable()) + if (!NewMCID.isPredicable()) // Can't transfer predicate, fail. return false; } else { - SkipPred = !NewTID.isPredicable(); + SkipPred = !NewMCID.isPredicable(); } bool HasCC = false; bool CCDead = false; - const TargetInstrDesc &TID = MI->getDesc(); - if (TID.hasOptionalDef()) { - unsigned NumOps = TID.getNumOperands(); + const MCInstrDesc &MCID = MI->getDesc(); + if (MCID.hasOptionalDef()) { + unsigned NumOps = MCID.getNumOperands(); HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); if (HasCC && MI->getOperand(NumOps-1).isDead()) CCDead = true; @@ -602,15 +602,15 @@ // Avoid adding a false dependency on partial flag update by some 16-bit // instructions which has the 's' bit set. - if (Entry.PartFlag && NewTID.hasOptionalDef() && HasCC && + if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC && canAddPseudoFlagDep(CPSRDef, MI)) return false; // Add the 16-bit instruction. DebugLoc dl = MI->getDebugLoc(); - MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID); + MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewMCID); MIB.addOperand(MI->getOperand(0)); - if (NewTID.hasOptionalDef()) { + if (NewMCID.hasOptionalDef()) { if (HasCC) AddDefaultT1CC(MIB, CCDead); else @@ -618,11 +618,11 @@ } // Transfer the rest of operands. - unsigned NumOps = TID.getNumOperands(); + unsigned NumOps = MCID.getNumOperands(); for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { - if (i < NumOps && TID.OpInfo[i].isOptionalDef()) + if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) continue; - if (SkipPred && TID.OpInfo[i].isPredicate()) + if (SkipPred && MCID.OpInfo[i].isPredicate()) continue; MIB.addOperand(MI->getOperand(i)); } @@ -649,9 +649,9 @@ if (Entry.Imm1Limit) Limit = ((1 << Entry.Imm1Limit) - 1) * Scale; - const TargetInstrDesc &TID = MI->getDesc(); - for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { - if (TID.OpInfo[i].isPredicate()) + const MCInstrDesc &MCID = MI->getDesc(); + for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { + if (MCID.OpInfo[i].isPredicate()) continue; const MachineOperand &MO = MI->getOperand(i); if (MO.isReg()) { @@ -663,29 +663,29 @@ if (Entry.LowRegs1 && !isARMLowRegister(Reg)) return false; } else if (MO.isImm() && - !TID.OpInfo[i].isPredicate()) { + !MCID.OpInfo[i].isPredicate()) { if (((unsigned)MO.getImm()) > Limit || (MO.getImm() & (Scale-1)) != 0) return false; } } // Check if it's possible / necessary to transfer the predicate. - const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc1); + const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1); unsigned PredReg = 0; ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); bool SkipPred = false; if (Pred != ARMCC::AL) { - if (!NewTID.isPredicable()) + if (!NewMCID.isPredicable()) // Can't transfer predicate, fail. return false; } else { - SkipPred = !NewTID.isPredicable(); + SkipPred = !NewMCID.isPredicable(); } bool HasCC = false; bool CCDead = false; - if (TID.hasOptionalDef()) { - unsigned NumOps = TID.getNumOperands(); + if (MCID.hasOptionalDef()) { + unsigned NumOps = MCID.getNumOperands(); HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); if (HasCC && MI->getOperand(NumOps-1).isDead()) CCDead = true; @@ -695,15 +695,15 @@ // Avoid adding a false dependency on partial flag update by some 16-bit // instructions which has the 's' bit set. - if (Entry.PartFlag && NewTID.hasOptionalDef() && HasCC && + if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC && canAddPseudoFlagDep(CPSRDef, MI)) return false; // Add the 16-bit instruction. DebugLoc dl = MI->getDebugLoc(); - MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID); + MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewMCID); MIB.addOperand(MI->getOperand(0)); - if (NewTID.hasOptionalDef()) { + if (NewMCID.hasOptionalDef()) { if (HasCC) AddDefaultT1CC(MIB, CCDead); else @@ -711,15 +711,15 @@ } // Transfer the rest of operands. - unsigned NumOps = TID.getNumOperands(); + unsigned NumOps = MCID.getNumOperands(); for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { - if (i < NumOps && TID.OpInfo[i].isOptionalDef()) + if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) continue; - if ((TID.getOpcode() == ARM::t2RSBSri || - TID.getOpcode() == ARM::t2RSBri) && i == 2) + if ((MCID.getOpcode() == ARM::t2RSBSri || + MCID.getOpcode() == ARM::t2RSBri) && i == 2) // Skip the zero immediate operand, it's now implicit. continue; - bool isPred = (i < NumOps && TID.OpInfo[i].isPredicate()); + bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate()); if (SkipPred && isPred) continue; const MachineOperand &MO = MI->getOperand(i); @@ -733,7 +733,7 @@ MIB.addOperand(MO); } } - if (!TID.isPredicable() && NewTID.isPredicable()) + if (!MCID.isPredicable() && NewMCID.isPredicable()) AddDefaultPred(MIB); // Transfer MI flags. Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp Tue Jun 28 14:10:37 2011 @@ -146,21 +146,21 @@ NI != DAG.allnodes_end(); ++NI) { if (NI->use_empty() || !NI->isMachineOpcode()) continue; - const TargetInstrDesc &DefTID = TII.get(NI->getMachineOpcode()); + const MCInstrDesc &DefMCID = TII.get(NI->getMachineOpcode()); for (SDNode::use_iterator UI = NI->use_begin(); !UI.atEnd(); ++UI) { if (!UI->isMachineOpcode()) continue; - if (UI.getUse().getResNo() >= DefTID.getNumDefs()) + if (UI.getUse().getResNo() >= DefMCID.getNumDefs()) continue; const TargetRegisterClass *DefRC = - TII.getRegClass(DefTID, UI.getUse().getResNo(), TRI); + TII.getRegClass(DefMCID, UI.getUse().getResNo(), TRI); - const TargetInstrDesc &UseTID = TII.get(UI->getMachineOpcode()); - if (UseTID.getNumDefs()+UI.getOperandNo() >= UseTID.getNumOperands()) + const MCInstrDesc &UseMCID = TII.get(UI->getMachineOpcode()); + if (UseMCID.getNumDefs()+UI.getOperandNo() >= UseMCID.getNumOperands()) continue; const TargetRegisterClass *UseRC = - TII.getRegClass(UseTID, UseTID.getNumDefs()+UI.getOperandNo(), TRI); + TII.getRegClass(UseMCID, UseMCID.getNumDefs()+UI.getOperandNo(), TRI); if (!DefRC || !UseRC) continue; // We cannot copy CC <-> !(CC/D) Modified: llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeDelaySlotFiller.cpp Tue Jun 28 14:10:37 2011 @@ -109,7 +109,7 @@ // Hazard check MachineBasicBlock::iterator a = candidate; MachineBasicBlock::iterator b = slot; - TargetInstrDesc desc = candidate->getDesc(); + MCInstrDesc desc = candidate->getDesc(); // MBB layout:- // candidate := a0 = operation(a1, a2) @@ -183,7 +183,7 @@ if (candidate == MBB.begin()) return false; - TargetInstrDesc brdesc = (--candidate)->getDesc(); + MCInstrDesc brdesc = (--candidate)->getDesc(); return (brdesc.hasDelaySlot()); } @@ -211,7 +211,7 @@ break; --I; - TargetInstrDesc desc = I->getDesc(); + MCInstrDesc desc = I->getDesc(); if (desc.hasDelaySlot() || desc.isBranch() || isDelayFiller(MBB,I) || desc.isCall() || desc.isReturn() || desc.isBarrier() || hasUnknownSideEffects(I)) Modified: llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeMCCodeEmitter.cpp Tue Jun 28 14:10:37 2011 @@ -179,7 +179,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups) const { unsigned Opcode = MI.getOpcode(); - const TargetInstrDesc &Desc = TII.get(Opcode); + const MCInstrDesc &Desc = TII.get(Opcode); uint64_t TSFlags = Desc.TSFlags; // Keep track of the current byte being emitted. unsigned CurByte = 0; Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Tue Jun 28 14:10:37 2011 @@ -158,13 +158,13 @@ } bool MSP430InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.isTerminator()) return false; + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.isTerminator()) return false; // Conditional branch is a special case. - if (TID.isBranch() && !TID.isBarrier()) + if (MCID.isBranch() && !MCID.isBarrier()) return true; - if (!TID.isPredicable()) + if (!MCID.isPredicable()) return true; return !isPredicated(MI); } @@ -293,7 +293,7 @@ /// instruction may be. This returns the maximum number of bytes. /// unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { - const TargetInstrDesc &Desc = MI->getDesc(); + const MCInstrDesc &Desc = MI->getDesc(); switch (Desc.TSFlags & MSP430II::SizeMask) { default: Modified: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp Tue Jun 28 14:10:37 2011 @@ -59,10 +59,10 @@ { bool Changed = false; for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) { - const TargetInstrDesc& Tid = I->getDesc(); - if (Tid.hasDelaySlot() && + const MCInstrDesc& MCid = I->getDesc(); + if (MCid.hasDelaySlot() && (TM.getSubtarget().isMips1() || - Tid.isCall() || Tid.isBranch() || Tid.isReturn())) { + MCid.isCall() || MCid.isBranch() || MCid.isReturn())) { MachineBasicBlock::iterator J = I; ++J; BuildMI(MBB, J, I->getDebugLoc(), TII->get(Mips::NOP)); Modified: llvm/trunk/lib/Target/Mips/MipsExpandPseudo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsExpandPseudo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsExpandPseudo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsExpandPseudo.cpp Tue Jun 28 14:10:37 2011 @@ -61,9 +61,9 @@ bool Changed = false; for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end();) { - const TargetInstrDesc& Tid = I->getDesc(); + const MCInstrDesc& MCid = I->getDesc(); - switch(Tid.getOpcode()) { + switch(MCid.getOpcode()) { default: ++I; continue; @@ -87,7 +87,7 @@ MachineBasicBlock::iterator I) { unsigned DstReg = I->getOperand(0).getReg(); unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); - const TargetInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1); + const MCInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1); DebugLoc dl = I->getDebugLoc(); const unsigned* SubReg = TM.getRegisterInfo()->getSubRegisters(DstReg); @@ -103,7 +103,7 @@ unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = I->getOperand(1).getReg(); unsigned N = I->getOperand(2).getImm(); - const TargetInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1); + const MCInstrDesc& Mfc1Tdd = TII->get(Mips::MFC1); DebugLoc dl = I->getDebugLoc(); const unsigned* SubReg = TM.getRegisterInfo()->getSubRegisters(SrcReg); Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Tue Jun 28 14:10:37 2011 @@ -341,8 +341,8 @@ const SmallVectorImpl& Cond) const { unsigned Opc = Cond[0].getImm(); - const TargetInstrDesc &TID = get(Opc); - MachineInstrBuilder MIB = BuildMI(&MBB, DL, TID); + const MCInstrDesc &MCID = get(Opc); + MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); for (unsigned i = 1; i < Cond.size(); ++i) MIB.addReg(Cond[i].getReg()); Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Tue Jun 28 14:10:37 2011 @@ -47,8 +47,8 @@ bool KillSrc) const { for (int i = 0, e = sizeof(map)/sizeof(map[0]); i != e; ++ i) { if (map[i].cls->contains(DstReg, SrcReg)) { - const TargetInstrDesc &TID = get(map[i].opcode); - MachineInstr *MI = BuildMI(MBB, I, DL, TID, DstReg). + const MCInstrDesc &MCID = get(map[i].opcode); + MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg). addReg(SrcReg, getKillRegState(KillSrc)); AddDefaultPredicate(MI); return; @@ -69,8 +69,8 @@ for (int i = 0, e = sizeof(map)/sizeof(map[0]); i != e; ++ i) if (DstRC == map[i].cls) { - const TargetInstrDesc &TID = get(map[i].opcode); - MachineInstr *MI = BuildMI(MBB, I, DL, TID, DstReg).addReg(SrcReg); + const MCInstrDesc &MCID = get(map[i].opcode); + MachineInstr *MI = BuildMI(MBB, I, DL, MCID, DstReg).addReg(SrcReg); AddDefaultPredicate(MI); return true; } @@ -178,13 +178,13 @@ MachineBasicBlock::const_iterator iter = MBB.end(); const MachineInstr& instLast1 = *--iter; - const TargetInstrDesc &desc1 = instLast1.getDesc(); + const MCInstrDesc &desc1 = instLast1.getDesc(); // for special case that MBB has only 1 instruction const bool IsSizeOne = MBB.size() == 1; // if IsSizeOne is true, *--iter and instLast2 are invalid // we put a dummy value in instLast2 and desc2 since they are used const MachineInstr& instLast2 = IsSizeOne ? instLast1 : *--iter; - const TargetInstrDesc &desc2 = IsSizeOne ? desc1 : instLast2.getDesc(); + const MCInstrDesc &desc2 = IsSizeOne ? desc1 : instLast2.getDesc(); DEBUG(dbgs() << "\n"); DEBUG(dbgs() << "AnalyzeBranch: opcode: " << instLast1.getOpcode() << "\n"); @@ -387,7 +387,7 @@ } bool PTXInstrInfo::IsAnyKindOfBranch(const MachineInstr& inst) { - const TargetInstrDesc &desc = inst.getDesc(); + const MCInstrDesc &desc = inst.getDesc(); return desc.isTerminator() || desc.isBranch() || desc.isIndirectBranch(); } Modified: llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCHazardRecognizers.cpp Tue Jun 28 14:10:37 2011 @@ -73,12 +73,12 @@ } Opcode = ~Opcode; - const TargetInstrDesc &TID = TII.get(Opcode); + const MCInstrDesc &MCID = TII.get(Opcode); - isLoad = TID.mayLoad(); - isStore = TID.mayStore(); + isLoad = MCID.mayLoad(); + isStore = MCID.mayStore(); - uint64_t TSFlags = TID.TSFlags; + uint64_t TSFlags = MCID.TSFlags; isFirst = TSFlags & PPCII::PPC970_First; isSingle = TSFlags & PPCII::PPC970_Single; Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Jun 28 14:10:37 2011 @@ -120,7 +120,7 @@ // destination register as well. if (Reg0 == Reg1) { // Must be two address instruction! - assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) && + assert(MI->getDesc().getOperandConstraint(0, MCOI::TIED_TO) && "Expecting a two-address instruction!"); Reg2IsKill = false; ChangeReg0 = true; @@ -315,12 +315,12 @@ else llvm_unreachable("Impossible reg-to-reg copy"); - const TargetInstrDesc &TID = get(Opc); - if (TID.getNumOperands() == 3) - BuildMI(MBB, I, DL, TID, DestReg) + const MCInstrDesc &MCID = get(Opc); + if (MCID.getNumOperands() == 3) + BuildMI(MBB, I, DL, MCID, DestReg) .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); else - BuildMI(MBB, I, DL, TID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); + BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); } bool Modified: llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp (original) +++ llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp Tue Jun 28 14:10:37 2011 @@ -298,7 +298,7 @@ return false; if (candidate->getOpcode() == SP::UNIMP) return true; - const TargetInstrDesc &prevdesc = (--candidate)->getDesc(); + const MCInstrDesc &prevdesc = (--candidate)->getDesc(); return prevdesc.hasDelaySlot(); } Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrBuilder.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrBuilder.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrBuilder.h Tue Jun 28 14:10:37 2011 @@ -108,11 +108,11 @@ MachineInstr *MI = MIB; MachineFunction &MF = *MI->getParent()->getParent(); MachineFrameInfo &MFI = *MF.getFrameInfo(); - const TargetInstrDesc &TID = MI->getDesc(); + const MCInstrDesc &MCID = MI->getDesc(); unsigned Flags = 0; - if (TID.mayLoad()) + if (MCID.mayLoad()) Flags |= MachineMemOperand::MOLoad; - if (TID.mayStore()) + if (MCID.mayStore()) Flags |= MachineMemOperand::MOStore; MachineMemOperand *MMO = MF.getMachineMemOperand(MachinePointerInfo( Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Tue Jun 28 14:10:37 2011 @@ -199,13 +199,13 @@ } bool SystemZInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.isTerminator()) return false; + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.isTerminator()) return false; // Conditional branch is a special case. - if (TID.isBranch() && !TID.isBarrier()) + if (MCID.isBranch() && !MCID.isBarrier()) return true; - if (!TID.isPredicable()) + if (!MCID.isPredicable()) return true; return !isPredicated(MI); } @@ -343,7 +343,7 @@ return Count; } -const TargetInstrDesc& +const MCInstrDesc& SystemZInstrInfo::getBrCond(SystemZCC::CondCodes CC) const { switch (CC) { default: @@ -408,7 +408,7 @@ } } -const TargetInstrDesc& +const MCInstrDesc& SystemZInstrInfo::getLongDispOpc(unsigned Opc) const { switch (Opc) { default: Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h Tue Jun 28 14:10:37 2011 @@ -94,10 +94,10 @@ SystemZCC::CondCodes getOppositeCondition(SystemZCC::CondCodes CC) const; SystemZCC::CondCodes getCondFromBranchOpc(unsigned Opc) const; - const TargetInstrDesc& getBrCond(SystemZCC::CondCodes CC) const; - const TargetInstrDesc& getLongDispOpc(unsigned Opc) const; + const MCInstrDesc& getBrCond(SystemZCC::CondCodes CC) const; + const MCInstrDesc& getLongDispOpc(unsigned Opc) const; - const TargetInstrDesc& getMemoryInstr(unsigned Opc, int64_t Offset = 0) const { + const MCInstrDesc& getMemoryInstr(unsigned Opc, int64_t Offset = 0) const { if (Offset < 0 || Offset >= 4096) return getLongDispOpc(Opc); else Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Tue Jun 28 14:10:37 2011 @@ -24,22 +24,21 @@ // TargetInstrInfo //===----------------------------------------------------------------------===// -TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc, - unsigned numOpcodes) - : Descriptors(Desc), NumOpcodes(numOpcodes) { +TargetInstrInfo::TargetInstrInfo(const MCInstrDesc* Desc, unsigned numOpcodes) { + InitMCInstrInfo(Desc, numOpcodes); } TargetInstrInfo::~TargetInstrInfo() { } const TargetRegisterClass* -TargetInstrInfo::getRegClass(const TargetInstrDesc &TID, unsigned OpNum, +TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, const TargetRegisterInfo *TRI) const { - if (OpNum >= TID.getNumOperands()) + if (OpNum >= MCID.getNumOperands()) return 0; - short RegClass = TID.OpInfo[OpNum].RegClass; - if (TID.OpInfo[OpNum].isLookupPtrRegClass()) + short RegClass = MCID.OpInfo[OpNum].RegClass; + if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) return TRI->getPointerRegClass(RegClass); // Instructions like INSERT_SUBREG do not have fixed register classes. @@ -135,13 +134,13 @@ bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.isTerminator()) return false; + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.isTerminator()) return false; // Conditional branch is a special case. - if (TID.isBranch() && !TID.isBarrier()) + if (MCID.isBranch() && !MCID.isBarrier()) return true; - if (!TID.isPredicable()) + if (!MCID.isPredicable()) return true; return !isPredicated(MI); } Modified: llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86CodeEmitter.cpp Tue Jun 28 14:10:37 2011 @@ -68,7 +68,7 @@ return "X86 Machine Code Emitter"; } - void emitInstruction(MachineInstr &MI, const TargetInstrDesc *Desc); + void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc); void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); @@ -132,7 +132,7 @@ MCE.StartMachineBasicBlock(MBB); for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E; ++I) { - const TargetInstrDesc &Desc = I->getDesc(); + const MCInstrDesc &Desc = I->getDesc(); emitInstruction(*I, &Desc); // MOVPC32r is basically a call plus a pop instruction. if (Desc.getOpcode() == X86::MOVPC32r) @@ -150,7 +150,7 @@ /// size, and 3) use of X86-64 extended registers. static unsigned determineREX(const MachineInstr &MI) { unsigned REX = 0; - const TargetInstrDesc &Desc = MI.getDesc(); + const MCInstrDesc &Desc = MI.getDesc(); // Pseudo instructions do not need REX prefix byte. if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo) @@ -161,7 +161,7 @@ unsigned NumOps = Desc.getNumOperands(); if (NumOps) { bool isTwoAddr = NumOps > 1 && - Desc.getOperandConstraint(1, TOI::TIED_TO) != -1; + Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. unsigned i = isTwoAddr ? 1 : 0; @@ -598,7 +598,7 @@ template void Emitter::emitInstruction(MachineInstr &MI, - const TargetInstrDesc *Desc) { + const MCInstrDesc *Desc) { DEBUG(dbgs() << MI); // If this is a pseudo instruction, lower it. @@ -708,9 +708,9 @@ // If this is a two-address instruction, skip one of the register operands. unsigned NumOps = Desc->getNumOperands(); unsigned CurOp = 0; - if (NumOps > 1 && Desc->getOperandConstraint(1, TOI::TIED_TO) != -1) + if (NumOps > 1 && Desc->getOperandConstraint(1, MCOI::TIED_TO) != -1) ++CurOp; - else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0) + else if (NumOps > 2 && Desc->getOperandConstraint(NumOps-1,MCOI::TIED_TO)== 0) // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 --NumOps; Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Jun 28 14:10:37 2011 @@ -1393,7 +1393,7 @@ assert(DI->getAddress() && "Null address should be checked earlier!"); if (!X86SelectAddress(DI->getAddress(), AM)) return false; - const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); + const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); // FIXME may need to add RegState::Debug to any registers produced, // although ESP/EBP should be the only ones at the moment. addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM). Modified: llvm/trunk/lib/Target/X86/X86InstrBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrBuilder.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrBuilder.h (original) +++ llvm/trunk/lib/Target/X86/X86InstrBuilder.h Tue Jun 28 14:10:37 2011 @@ -150,11 +150,11 @@ MachineInstr *MI = MIB; MachineFunction &MF = *MI->getParent()->getParent(); MachineFrameInfo &MFI = *MF.getFrameInfo(); - const TargetInstrDesc &TID = MI->getDesc(); + const MCInstrDesc &MCID = MI->getDesc(); unsigned Flags = 0; - if (TID.mayLoad()) + if (MCID.mayLoad()) Flags |= MachineMemOperand::MOLoad; - if (TID.mayStore()) + if (MCID.mayStore()) Flags |= MachineMemOperand::MOStore; MachineMemOperand *MMO = MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI, Offset), Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Jun 28 14:10:37 2011 @@ -1689,13 +1689,13 @@ } bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const { - const TargetInstrDesc &TID = MI->getDesc(); - if (!TID.isTerminator()) return false; + const MCInstrDesc &MCID = MI->getDesc(); + if (!MCID.isTerminator()) return false; // Conditional branch is a special case. - if (TID.isBranch() && !TID.isBarrier()) + if (MCID.isBranch() && !MCID.isBarrier()) return true; - if (!TID.isPredicable()) + if (!MCID.isPredicable()) return true; return !isPredicated(MI); } @@ -2225,7 +2225,7 @@ bool isTwoAddrFold = false; unsigned NumOps = MI->getDesc().getNumOperands(); bool isTwoAddr = NumOps > 1 && - MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; + MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; // FIXME: AsmPrinter doesn't know how to handle // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding. @@ -2543,7 +2543,7 @@ unsigned Opc = MI->getOpcode(); unsigned NumOps = MI->getDesc().getNumOperands(); bool isTwoAddr = NumOps > 1 && - MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1; + MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1; // Folding a memory location into the two-address part of a two-address // instruction is different than folding it other places. It requires @@ -2589,8 +2589,8 @@ return false; UnfoldStore &= FoldedStore; - const TargetInstrDesc &TID = get(Opc); - const TargetRegisterClass *RC = getRegClass(TID, Index, &RI); + const MCInstrDesc &MCID = get(Opc); + const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI); if (!MI->hasOneMemOperand() && RC == &X86::VR128RegClass && !TM.getSubtarget().isUnalignedMemAccessFast()) @@ -2632,7 +2632,7 @@ } // Emit the data processing instruction. - MachineInstr *DataMI = MF.CreateMachineInstr(TID, MI->getDebugLoc(), true); + MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true); MachineInstrBuilder MIB(DataMI); if (FoldedStore) @@ -2685,7 +2685,7 @@ // Emit the store instruction. if (UnfoldStore) { - const TargetRegisterClass *DstRC = getRegClass(TID, 0, &RI); + const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI); std::pair MMOs = MF.extractStoreMemRefs(MI->memoperands_begin(), @@ -2710,9 +2710,9 @@ unsigned Index = I->second.second & 0xf; bool FoldedLoad = I->second.second & (1 << 4); bool FoldedStore = I->second.second & (1 << 5); - const TargetInstrDesc &TID = get(Opc); - const TargetRegisterClass *RC = getRegClass(TID, Index, &RI); - unsigned NumDefs = TID.NumDefs; + const MCInstrDesc &MCID = get(Opc); + const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI); + unsigned NumDefs = MCID.NumDefs; std::vector AddrOps; std::vector BeforeOps; std::vector AfterOps; @@ -2756,13 +2756,13 @@ // Emit the data processing instruction. std::vector VTs; const TargetRegisterClass *DstRC = 0; - if (TID.getNumDefs() > 0) { - DstRC = getRegClass(TID, 0, &RI); + if (MCID.getNumDefs() > 0) { + DstRC = getRegClass(MCID, 0, &RI); VTs.push_back(*DstRC->vt_begin()); } for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) { EVT VT = N->getValueType(i); - if (VT != MVT::Other && i >= (unsigned)TID.getNumDefs()) + if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs()) VTs.push_back(VT); } if (Load) Modified: llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp (original) +++ llvm/trunk/lib/Target/X86/X86MCCodeEmitter.cpp Tue Jun 28 14:10:37 2011 @@ -111,7 +111,7 @@ SmallVectorImpl &Fixups) const; void EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, - const MCInst &MI, const TargetInstrDesc &Desc, + const MCInst &MI, const MCInstrDesc &Desc, raw_ostream &OS) const; void EmitSegmentOverridePrefix(uint64_t TSFlags, unsigned &CurByte, @@ -119,7 +119,7 @@ raw_ostream &OS) const; void EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, - const MCInst &MI, const TargetInstrDesc &Desc, + const MCInst &MI, const MCInstrDesc &Desc, raw_ostream &OS) const; }; @@ -379,7 +379,7 @@ /// called VEX. void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, - const TargetInstrDesc &Desc, + const MCInstrDesc &Desc, raw_ostream &OS) const { bool HasVEX_4V = false; if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V) @@ -586,7 +586,7 @@ /// REX prefix which specifies 1) 64-bit instructions, 2) non-default operand /// size, and 3) use of X86-64 extended registers. static unsigned DetermineREXPrefix(const MCInst &MI, uint64_t TSFlags, - const TargetInstrDesc &Desc) { + const MCInstrDesc &Desc) { unsigned REX = 0; if (TSFlags & X86II::REX_W) REX |= 1 << 3; // set REX.W @@ -596,7 +596,7 @@ unsigned NumOps = MI.getNumOperands(); // FIXME: MCInst should explicitize the two-addrness. bool isTwoAddr = NumOps > 1 && - Desc.getOperandConstraint(1, TOI::TIED_TO) != -1; + Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1; // If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix. unsigned i = isTwoAddr ? 1 : 0; @@ -713,7 +713,7 @@ /// Not present, it is -1. void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, int MemOperand, const MCInst &MI, - const TargetInstrDesc &Desc, + const MCInstrDesc &Desc, raw_ostream &OS) const { // Emit the lock opcode prefix as needed. @@ -803,7 +803,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl &Fixups) const { unsigned Opcode = MI.getOpcode(); - const TargetInstrDesc &Desc = TII.get(Opcode); + const MCInstrDesc &Desc = TII.get(Opcode); uint64_t TSFlags = Desc.TSFlags; // Pseudo instructions don't get encoded. @@ -814,9 +814,9 @@ // FIXME: This should be handled during MCInst lowering. unsigned NumOps = Desc.getNumOperands(); unsigned CurOp = 0; - if (NumOps > 1 && Desc.getOperandConstraint(1, TOI::TIED_TO) != -1) + if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) != -1) ++CurOp; - else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, TOI::TIED_TO)== 0) + else if (NumOps > 2 && Desc.getOperandConstraint(NumOps-1, MCOI::TIED_TO)== 0) // Skip the last source operand that is tied_to the dest reg. e.g. LXADD32 --NumOps; Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Tue Jun 28 14:10:37 2011 @@ -94,17 +94,17 @@ // Ptr value whose register class is resolved via callback. if (OpR->isSubClassOf("PointerLikeRegClass")) - Res += "|(1<isSubClassOf("PredicateOperand")) - Res += "|(1<isSubClassOf("OptionalDefOperand")) - Res += "|(1< &NumberedInstructions = Target.getInstructionsByEnumValue(); @@ -221,31 +221,31 @@ << ",\t\"" << Inst.TheDef->getName() << "\", 0"; // Emit all of the target indepedent flags... - if (Inst.isReturn) OS << "|(1<getValueAsBitsInit("TSFlags"); Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.h?rev=134021&r1=134020&r2=134021&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.h (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.h Tue Jun 28 14:10:37 2011 @@ -54,10 +54,6 @@ // Operand information. void EmitOperandInfo(raw_ostream &OS, OperandInfoMapTy &OperandInfoIDs); std::vector GetOperandInfo(const CodeGenInstruction &Inst); - - void DetectRegisterClassBarriers(std::vector &Defs, - const std::vector &RCs, - std::vector &Barriers); }; } // End llvm namespace From evan.cheng at apple.com Tue Jun 28 15:07:07 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 28 Jun 2011 20:07:07 -0000 Subject: [llvm-commits] [llvm] r134024 - in /llvm/trunk: ./ include/llvm/MC/ lib/Target/ARM/ lib/Target/ARM/Disassembler/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MBlaze/Disassembler/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/X86/InstPrinter/ lib/Target/X86/MCTargetDesc/ lib/Target/XCore/ utils/TableGen/ Message-ID: <20110628200708.9FD7E2A6C12C@llvm.org> Author: evancheng Date: Tue Jun 28 15:07:07 2011 New Revision: 134024 URL: http://llvm.org/viewvc/llvm-project?rev=134024&view=rev Log: Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc Modified: llvm/trunk/Makefile.rules llvm/trunk/include/llvm/MC/MCInstrDesc.h llvm/trunk/lib/Target/ARM/ARMBaseInfo.h llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp llvm/trunk/lib/Target/ARM/CMakeLists.txt llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp llvm/trunk/lib/Target/ARM/Makefile llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp llvm/trunk/lib/Target/Alpha/Alpha.h llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/trunk/lib/Target/Alpha/CMakeLists.txt llvm/trunk/lib/Target/Alpha/Makefile llvm/trunk/lib/Target/Blackfin/Blackfin.h llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp llvm/trunk/lib/Target/Blackfin/CMakeLists.txt llvm/trunk/lib/Target/Blackfin/Makefile llvm/trunk/lib/Target/CellSPU/CMakeLists.txt llvm/trunk/lib/Target/CellSPU/Makefile llvm/trunk/lib/Target/CellSPU/SPU.h llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/MBlaze/CMakeLists.txt llvm/trunk/lib/Target/MBlaze/Disassembler/MBlazeDisassembler.cpp llvm/trunk/lib/Target/MBlaze/MBlaze.h llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp llvm/trunk/lib/Target/MBlaze/Makefile llvm/trunk/lib/Target/MSP430/CMakeLists.txt llvm/trunk/lib/Target/MSP430/MSP430.h llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp llvm/trunk/lib/Target/MSP430/Makefile llvm/trunk/lib/Target/Mips/CMakeLists.txt llvm/trunk/lib/Target/Mips/Makefile llvm/trunk/lib/Target/Mips/Mips.h llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/PTX/CMakeLists.txt llvm/trunk/lib/Target/PTX/Makefile llvm/trunk/lib/Target/PTX/PTX.h llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/CMakeLists.txt llvm/trunk/lib/Target/PowerPC/Makefile llvm/trunk/lib/Target/PowerPC/PPC.h llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/Sparc/CMakeLists.txt llvm/trunk/lib/Target/Sparc/Makefile llvm/trunk/lib/Target/Sparc/Sparc.h llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp llvm/trunk/lib/Target/SystemZ/CMakeLists.txt llvm/trunk/lib/Target/SystemZ/Makefile llvm/trunk/lib/Target/SystemZ/SystemZ.h llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/trunk/lib/Target/X86/CMakeLists.txt llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h llvm/trunk/lib/Target/X86/Makefile llvm/trunk/lib/Target/X86/X86.h llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/XCore/CMakeLists.txt llvm/trunk/lib/Target/XCore/Makefile llvm/trunk/lib/Target/XCore/XCore.h llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp llvm/trunk/utils/TableGen/InstrInfoEmitter.h llvm/trunk/utils/TableGen/TableGen.cpp Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Tue Jun 28 15:07:07 2011 @@ -1720,35 +1720,15 @@ # All of these files depend on tblgen and the .td files. $(INCTMPFiles) : $(TBLGEN) $(TDFiles) -$(TARGET:%=$(ObjDir)/%GenRegisterNames.inc.tmp): \ -$(ObjDir)/%GenRegisterNames.inc.tmp : %.td $(ObjDir)/.dir - $(Echo) "Building $( Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.cpp Tue Jun 28 15:07:07 2011 @@ -14,7 +14,6 @@ #include "ARMInstrInfo.h" #include "ARM.h" #include "ARMAddressingModes.h" -#include "ARMGenInstrInfo.inc" #include "ARMMachineFunctionInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/CodeGen/LiveVariables.h" Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Tue Jun 28 15:07:07 2011 @@ -1,8 +1,7 @@ set(LLVM_TARGET_DEFINITIONS ARM.td) tablegen(ARMGenRegisterInfo.inc -gen-register-info) -tablegen(ARMGenInstrNames.inc -gen-instr-enums) -tablegen(ARMGenInstrInfo.inc -gen-instr-desc) +tablegen(ARMGenInstrInfo.inc -gen-instr-info) tablegen(ARMGenCodeEmitter.inc -gen-emitter) tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter) tablegen(ARMGenAsmWriter.inc -gen-asm-writer) Modified: llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp (original) +++ llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp Tue Jun 28 15:07:07 2011 @@ -71,6 +71,7 @@ /// { ARM::CCRRegClassID, 0|(1< EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. extern cl::opt EnablePPC64RS; // FIXME (64-bit): See PPCRegisterInfo.cpp. Modified: llvm/trunk/lib/Target/Sparc/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/CMakeLists.txt?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/Sparc/CMakeLists.txt Tue Jun 28 15:07:07 2011 @@ -1,8 +1,7 @@ set(LLVM_TARGET_DEFINITIONS Sparc.td) tablegen(SparcGenRegisterInfo.inc -gen-register-info) -tablegen(SparcGenInstrNames.inc -gen-instr-enums) -tablegen(SparcGenInstrInfo.inc -gen-instr-desc) +tablegen(SparcGenInstrInfo.inc -gen-instr-info) tablegen(SparcGenAsmWriter.inc -gen-asm-writer) tablegen(SparcGenDAGISel.inc -gen-dag-isel) tablegen(SparcGenSubtarget.inc -gen-subtarget) Modified: llvm/trunk/lib/Target/Sparc/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Makefile?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/Makefile (original) +++ llvm/trunk/lib/Target/Sparc/Makefile Tue Jun 28 15:07:07 2011 @@ -12,8 +12,8 @@ TARGET = Sparc # Make sure that tblgen is run, first thing. -BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrNames.inc \ - SparcGenInstrInfo.inc SparcGenAsmWriter.inc \ +BUILT_SOURCES = SparcGenRegisterInfo.inc SparcGenInstrInfo.inc \ + SparcGenAsmWriter.inc \ SparcGenDAGISel.inc SparcGenSubtarget.inc SparcGenCallingConv.inc DIRS = TargetInfo Modified: llvm/trunk/lib/Target/Sparc/Sparc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/Sparc.h?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/Sparc.h (original) +++ llvm/trunk/lib/Target/Sparc/Sparc.h Tue Jun 28 15:07:07 2011 @@ -41,7 +41,8 @@ // Defines symbolic names for the Sparc instructions. // -#include "SparcGenInstrNames.inc" +#define GET_INSTRINFO_ENUM +#include "SparcGenInstrInfo.inc" namespace llvm { Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Tue Jun 28 15:07:07 2011 @@ -19,8 +19,11 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Support/ErrorHandling.h" -#include "SparcGenInstrInfo.inc" #include "SparcMachineFunctionInfo.h" + +#define GET_INSTRINFO_MC_DESC +#include "SparcGenInstrInfo.inc" + using namespace llvm; SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) Modified: llvm/trunk/lib/Target/SystemZ/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/CMakeLists.txt?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/SystemZ/CMakeLists.txt Tue Jun 28 15:07:07 2011 @@ -1,8 +1,7 @@ set(LLVM_TARGET_DEFINITIONS SystemZ.td) tablegen(SystemZGenRegisterInfo.inc -gen-register-info) -tablegen(SystemZGenInstrNames.inc -gen-instr-enums) -tablegen(SystemZGenInstrInfo.inc -gen-instr-desc) +tablegen(SystemZGenInstrInfo.inc -gen-instr-info) tablegen(SystemZGenAsmWriter.inc -gen-asm-writer) tablegen(SystemZGenDAGISel.inc -gen-dag-isel) tablegen(SystemZGenCallingConv.inc -gen-callingconv) Modified: llvm/trunk/lib/Target/SystemZ/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/Makefile?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/Makefile (original) +++ llvm/trunk/lib/Target/SystemZ/Makefile Tue Jun 28 15:07:07 2011 @@ -12,8 +12,8 @@ TARGET = SystemZ # Make sure that tblgen is run, first thing. -BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrNames.inc \ - SystemZGenInstrInfo.inc SystemZGenAsmWriter.inc \ +BUILT_SOURCES = SystemZGenRegisterInfo.inc SystemZGenInstrInfo.inc \ + SystemZGenAsmWriter.inc \ SystemZGenDAGISel.inc SystemZGenSubtarget.inc SystemZGenCallingConv.inc DIRS = TargetInfo Modified: llvm/trunk/lib/Target/SystemZ/SystemZ.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZ.h?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZ.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZ.h Tue Jun 28 15:07:07 2011 @@ -57,6 +57,7 @@ #include "SystemZGenRegisterInfo.inc" // Defines symbolic names for the SystemZ instructions. -#include "SystemZGenInstrNames.inc" +#define GET_INSTRINFO_ENUM +#include "SystemZGenInstrInfo.inc" #endif Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Tue Jun 28 15:07:07 2011 @@ -16,13 +16,16 @@ #include "SystemZInstrInfo.h" #include "SystemZMachineFunctionInfo.h" #include "SystemZTargetMachine.h" -#include "SystemZGenInstrInfo.inc" #include "llvm/Function.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" #include "llvm/Support/ErrorHandling.h" + +#define GET_INSTRINFO_MC_DESC +#include "SystemZGenInstrInfo.inc" + using namespace llvm; SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Tue Jun 28 15:07:07 2011 @@ -2,8 +2,7 @@ tablegen(X86GenRegisterInfo.inc -gen-register-info) tablegen(X86GenDisassemblerTables.inc -gen-disassembler) -tablegen(X86GenInstrNames.inc -gen-instr-enums) -tablegen(X86GenInstrInfo.inc -gen-instr-desc) +tablegen(X86GenInstrInfo.inc -gen-instr-info) tablegen(X86GenAsmWriter.inc -gen-asm-writer) tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1) tablegen(X86GenAsmMatcher.inc -gen-asm-matcher) Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp Tue Jun 28 15:07:07 2011 @@ -16,19 +16,17 @@ #include "X86ATTInstPrinter.h" #include "X86InstComments.h" #include "X86Subtarget.h" +#include "MCTargetDesc/X86TargetDesc.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/Format.h" #include "llvm/Support/FormattedStream.h" -#include "X86GenInstrNames.inc" #include using namespace llvm; // Include the auto-generated portion of the assembly writer. -#define GET_REGINFO_ENUM -#include "X86GenRegisterInfo.inc" #define GET_INSTRUCTION_NAME #define PRINT_ALIAS_INSTR #include "X86GenAsmWriter.inc" Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86InstComments.cpp Tue Jun 28 15:07:07 2011 @@ -13,7 +13,7 @@ //===----------------------------------------------------------------------===// #include "X86InstComments.h" -#include "X86GenInstrNames.inc" +#include "MCTargetDesc/X86TargetDesc.h" #include "llvm/MC/MCInst.h" #include "llvm/Support/raw_ostream.h" #include "../Utils/X86ShuffleDecode.h" Modified: llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp (original) +++ llvm/trunk/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp Tue Jun 28 15:07:07 2011 @@ -16,12 +16,12 @@ #include "X86IntelInstPrinter.h" #include "X86InstComments.h" #include "X86Subtarget.h" +#include "MCTargetDesc/X86TargetDesc.h" #include "llvm/MC/MCInst.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCExpr.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FormattedStream.h" -#include "X86GenInstrNames.inc" #include using namespace llvm; Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp Tue Jun 28 15:07:07 2011 @@ -12,11 +12,16 @@ //===----------------------------------------------------------------------===// #include "X86TargetDesc.h" +#include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/Target/TargetRegistry.h" #define GET_REGINFO_MC_DESC #include "X86GenRegisterInfo.inc" + +#define GET_INSTRINFO_MC_DESC +#include "X86GenInstrInfo.inc" + using namespace llvm; MCRegisterInfo *createX86MCRegisterInfo() { Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.h Tue Jun 28 15:07:07 2011 @@ -26,4 +26,9 @@ #define GET_REGINFO_ENUM #include "X86GenRegisterInfo.inc" +// Defines symbolic names for the X86 instructions. +// +#define GET_INSTRINFO_ENUM +#include "X86GenInstrInfo.inc" + #endif Modified: llvm/trunk/lib/Target/X86/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Makefile?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/Makefile (original) +++ llvm/trunk/lib/Target/X86/Makefile Tue Jun 28 15:07:07 2011 @@ -12,8 +12,7 @@ TARGET = X86 # Make sure that tblgen is run, first thing. -BUILT_SOURCES = X86GenRegisterInfo.inc \ - X86GenInstrNames.inc X86GenInstrInfo.inc \ +BUILT_SOURCES = X86GenRegisterInfo.inc X86GenInstrInfo.inc \ X86GenAsmWriter.inc X86GenAsmMatcher.inc \ X86GenAsmWriter1.inc X86GenDAGISel.inc \ X86GenDisassemblerTables.inc X86GenFastISel.inc \ Modified: llvm/trunk/lib/Target/X86/X86.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.h?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86.h (original) +++ llvm/trunk/lib/Target/X86/X86.h Tue Jun 28 15:07:07 2011 @@ -15,6 +15,7 @@ #ifndef TARGET_X86_H #define TARGET_X86_H +#include "MCTargetDesc/X86TargetDesc.h" #include "llvm/Support/DataTypes.h" #include "llvm/Target/TargetMachine.h" @@ -86,10 +87,4 @@ } // End llvm namespace -#include "MCTargetDesc/X86TargetDesc.h" - -// Defines symbolic names for the X86 instructions. -// -#include "X86GenInstrNames.inc" - #endif Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Jun 28 15:07:07 2011 @@ -13,7 +13,6 @@ #include "X86InstrInfo.h" #include "X86.h" -#include "X86GenInstrInfo.inc" #include "X86InstrBuilder.h" #include "X86MachineFunctionInfo.h" #include "X86Subtarget.h" @@ -36,6 +35,9 @@ #include "llvm/MC/MCAsmInfo.h" #include +#define GET_INSTRINFO_MC_DESC +#include "X86GenInstrInfo.inc" + using namespace llvm; static cl::opt Modified: llvm/trunk/lib/Target/XCore/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/CMakeLists.txt?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/XCore/CMakeLists.txt Tue Jun 28 15:07:07 2011 @@ -1,8 +1,7 @@ set(LLVM_TARGET_DEFINITIONS XCore.td) tablegen(XCoreGenRegisterInfo.inc -gen-register-info) -tablegen(XCoreGenInstrNames.inc -gen-instr-enums) -tablegen(XCoreGenInstrInfo.inc -gen-instr-desc) +tablegen(XCoreGenInstrInfo.inc -gen-instr-info) tablegen(XCoreGenAsmWriter.inc -gen-asm-writer) tablegen(XCoreGenDAGISel.inc -gen-dag-isel) tablegen(XCoreGenCallingConv.inc -gen-callingconv) Modified: llvm/trunk/lib/Target/XCore/Makefile URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/Makefile?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/Makefile (original) +++ llvm/trunk/lib/Target/XCore/Makefile Tue Jun 28 15:07:07 2011 @@ -12,8 +12,8 @@ TARGET = XCore # Make sure that tblgen is run, first thing. -BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \ - XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \ +BUILT_SOURCES = XCoreGenRegisterInfo.inc XCoreGenInstrInfo.inc \ + XCoreGenAsmWriter.inc \ XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ XCoreGenSubtarget.inc Modified: llvm/trunk/lib/Target/XCore/XCore.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCore.h?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCore.h (original) +++ llvm/trunk/lib/Target/XCore/XCore.h Tue Jun 28 15:07:07 2011 @@ -37,6 +37,7 @@ // Defines symbolic names for the XCore instructions. // -#include "XCoreGenInstrNames.inc" +#define GET_INSTRINFO_ENUM +#include "XCoreGenInstrInfo.inc" #endif Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Tue Jun 28 15:07:07 2011 @@ -18,11 +18,13 @@ #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" -#include "XCoreGenInstrInfo.inc" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#define GET_INSTRINFO_MC_DESC +#include "XCoreGenInstrInfo.inc" + namespace llvm { namespace XCore { Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Tue Jun 28 15:07:07 2011 @@ -156,9 +156,15 @@ // run - Emit the main instruction description records for the target... void InstrInfoEmitter::run(raw_ostream &OS) { + emitEnums(OS); + GatherItinClasses(); EmitSourceFileHeader("Target Instruction Descriptors", OS); + + OS << "\n#ifdef GET_INSTRINFO_MC_DESC\n"; + OS << "#undef GET_INSTRINFO_MC_DESC\n"; + OS << "namespace llvm {\n\n"; CodeGenTarget &Target = CDP.getTargetInfo(); @@ -202,6 +208,8 @@ OperandInfoIDs, OS); OS << "};\n"; OS << "} // End llvm namespace \n"; + + OS << "#endif // GET_INSTRINFO_MC_DESC\n\n"; } void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, @@ -283,3 +291,38 @@ OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n"; } + +// emitEnums - Print out enum values for all of the instructions. +void InstrInfoEmitter::emitEnums(raw_ostream &OS) { + EmitSourceFileHeader("Target Instruction Enum Values", OS); + + OS << "\n#ifdef GET_INSTRINFO_ENUM\n"; + OS << "#undef GET_INSTRINFO_ENUM\n"; + + OS << "namespace llvm {\n\n"; + + CodeGenTarget Target(Records); + + // We must emit the PHI opcode first... + std::string Namespace = Target.getInstNamespace(); + + if (Namespace.empty()) { + fprintf(stderr, "No instructions defined!\n"); + exit(1); + } + + const std::vector &NumberedInstructions = + Target.getInstructionsByEnumValue(); + + OS << "namespace " << Namespace << " {\n"; + OS << " enum {\n"; + for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + OS << " " << NumberedInstructions[i]->TheDef->getName() + << "\t= " << i << ",\n"; + } + OS << " INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n"; + OS << " };\n}\n"; + OS << "} // End llvm namespace \n"; + + OS << "#endif // GET_INSTRINFO_ENUM\n\n"; +} Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.h?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.h (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.h Tue Jun 28 15:07:07 2011 @@ -39,8 +39,9 @@ void run(raw_ostream &OS); private: - typedef std::map, unsigned> OperandInfoMapTy; - + void emitEnums(raw_ostream &OS); + + typedef std::map, unsigned> OperandInfoMapTy; void emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map, unsigned> &EL, Modified: llvm/trunk/utils/TableGen/TableGen.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/TableGen.cpp?rev=134024&r1=134023&r2=134024&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/TableGen.cpp (original) +++ llvm/trunk/utils/TableGen/TableGen.cpp Tue Jun 28 15:07:07 2011 @@ -28,7 +28,6 @@ #include "EDEmitter.h" #include "Error.h" #include "FastISelEmitter.h" -#include "InstrEnumEmitter.h" #include "InstrInfoEmitter.h" #include "IntrinsicEmitter.h" #include "LLVMCConfigurationEmitter.h" @@ -55,7 +54,9 @@ PrintRecords, GenEmitter, GenRegisterInfo, - GenInstrEnums, GenInstrs, GenAsmWriter, GenAsmMatcher, + GenInstrInfo, + GenAsmWriter, + GenAsmMatcher, GenARMDecoder, GenDisassembler, GenCallingConv, @@ -95,9 +96,7 @@ "Generate machine code emitter"), clEnumValN(GenRegisterInfo, "gen-register-info", "Generate registers and register classes info"), - clEnumValN(GenInstrEnums, "gen-instr-enums", - "Generate enum values for instructions"), - clEnumValN(GenInstrs, "gen-instr-desc", + clEnumValN(GenInstrInfo, "gen-instr-info", "Generate instruction descriptions"), clEnumValN(GenCallingConv, "gen-callingconv", "Generate calling convention descriptions"), @@ -260,10 +259,7 @@ case GenRegisterInfo: RegisterInfoEmitter(Records).run(Out.os()); break; - case GenInstrEnums: - InstrEnumEmitter(Records).run(Out.os()); - break; - case GenInstrs: + case GenInstrInfo: InstrInfoEmitter(Records).run(Out.os()); break; case GenCallingConv: From evan.cheng at apple.com Tue Jun 28 15:29:04 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 28 Jun 2011 20:29:04 -0000 Subject: [llvm-commits] [llvm] r134026 - in /llvm/trunk: include/llvm/Target/TargetRegistry.h lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp utils/TableGen/InstrInfoEmitter.cpp Message-ID: <20110628202904.1758E2A6C12C@llvm.org> Author: evancheng Date: Tue Jun 28 15:29:03 2011 New Revision: 134026 URL: http://llvm.org/viewvc/llvm-project?rev=134026&view=rev Log: Add MCInstrInfo registeration machinery. Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134026&r1=134025&r2=134026&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Tue Jun 28 15:29:03 2011 @@ -33,6 +33,7 @@ class MCContext; class MCDisassembler; class MCInstPrinter; + class MCInstrInfo; class MCRegisterInfo; class MCStreamer; class TargetAsmBackend; @@ -66,6 +67,7 @@ typedef MCAsmInfo *(*AsmInfoCtorFnTy)(const Target &T, StringRef TT); + typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void); typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void); typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, const std::string &TT, @@ -126,6 +128,10 @@ /// registered. AsmInfoCtorFnTy AsmInfoCtorFn; + /// MCInstrInfoCtorFn - Constructor function for this target's MCInstrInfo, + /// if registered. + MCInstrInfoCtorFnTy MCInstrInfoCtorFn; + /// MCRegInfoCtorFn - Constructor function for this target's MCRegisterInfo, /// if registered. MCRegInfoCtorFnTy MCRegInfoCtorFn; @@ -239,6 +245,14 @@ return AsmInfoCtorFn(*this, Triple); } + /// createMCInstrInfo - Create a MCInstrInfo implementation. + /// + MCInstrInfo *createMCInstrInfo() const { + if (!MCInstrInfoCtorFn) + return 0; + return MCInstrInfoCtorFn(); + } + /// createMCRegInfo - Create a MCRegisterInfo implementation. /// MCRegisterInfo *createMCRegInfo() const { @@ -460,6 +474,21 @@ T.AsmInfoCtorFn = Fn; } + /// RegisterMCInstrInfo - Register a MCInstrInfo implementation for the + /// given target. + /// + /// Clients are responsible for ensuring that registration doesn't occur + /// while another thread is attempting to access the registry. Typically + /// this is done by initializing all targets at program startup. + /// + /// @param T - The target being registered. + /// @param Fn - A function to construct a MCInstrInfo for the target. + static void RegisterMCInstrInfo(Target &T, Target::MCInstrInfoCtorFnTy Fn) { + // Ignore duplicate registration. + if (!T.MCInstrInfoCtorFn) + T.MCInstrInfoCtorFn = Fn; + } + /// RegisterMCRegInfo - Register a MCRegisterInfo implementation for the /// given target. /// @@ -685,6 +714,39 @@ } }; + /// RegisterMCInstrInfo - Helper template for registering a target instruction + /// info implementation. This invokes the static "Create" method on the class + /// to actually do the construction. Usage: + /// + /// extern "C" void LLVMInitializeFooTarget() { + /// extern Target TheFooTarget; + /// RegisterMCInstrInfo X(TheFooTarget); + /// } + template + struct RegisterMCInstrInfo { + RegisterMCInstrInfo(Target &T) { + TargetRegistry::RegisterMCInstrInfo(T, &Allocator); + } + private: + static MCInstrInfo *Allocator() { + return new MCInstrInfoImpl(); + } + }; + + /// RegisterMCInstrInfoFn - Helper template for registering a target + /// instruction info implementation. This invokes the specified function to + /// do the construction. Usage: + /// + /// extern "C" void LLVMInitializeFooTarget() { + /// extern Target TheFooTarget; + /// RegisterMCInstrInfoFn X(TheFooTarget, TheFunction); + /// } + struct RegisterMCInstrInfoFn { + RegisterMCInstrInfoFn(Target &T, Target::MCInstrInfoCtorFnTy Fn) { + TargetRegistry::RegisterMCInstrInfo(T, Fn); + } + }; + /// RegisterMCRegInfo - Helper template for registering a target register info /// implementation. This invokes the static "Create" method on the class to /// actually do the construction. Usage: Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp?rev=134026&r1=134025&r2=134026&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp (original) +++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp Tue Jun 28 15:29:03 2011 @@ -24,6 +24,12 @@ using namespace llvm; +MCInstrInfo *createX86MCInstrInfo() { + MCInstrInfo *X = new MCInstrInfo(); + InitX86MCInstrInfo(X); + return X; +} + MCRegisterInfo *createX86MCRegisterInfo() { MCRegisterInfo *X = new MCRegisterInfo(); InitX86MCRegisterInfo(X); Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=134026&r1=134025&r2=134026&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Tue Jun 28 15:29:03 2011 @@ -206,7 +206,15 @@ for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, OperandInfoIDs, OS); - OS << "};\n"; + OS << "};\n\n"; + + + // MCInstrInfo initialization routine. + OS << "static inline void Init" << TargetName + << "MCInstrInfo(MCInstrInfo *II) {\n"; + OS << " II->InitMCInstrInfo(" << TargetName << "Insts, " + << NumberedInstructions.size() << ");\n}\n\n"; + OS << "} // End llvm namespace \n"; OS << "#endif // GET_INSTRINFO_MC_DESC\n\n"; From evan.cheng at apple.com Tue Jun 28 15:44:22 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 28 Jun 2011 20:44:22 -0000 Subject: [llvm-commits] [llvm] r134027 - in /llvm/trunk: lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ utils/TableGen/ Message-ID: <20110628204422.E9A8F2A6C12C@llvm.org> Author: evancheng Date: Tue Jun 28 15:44:22 2011 New Revision: 134027 URL: http://llvm.org/viewvc/llvm-project?rev=134027&view=rev Log: Hide more details in tablegen generated MCRegisterInfo ctor function. Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -58,8 +58,7 @@ ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &sti) - : ARMGenRegisterInfo(ARMRegDesc, ARMRegInfoDesc, - ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), + : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), TII(tii), STI(sti), FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), BasePtr(ARM::R6) { Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -41,8 +41,7 @@ using namespace llvm; AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) - : AlphaGenRegisterInfo(AlphaRegDesc, AlphaRegInfoDesc, - Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP), + : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP), TII(tii) { } Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -38,8 +38,7 @@ BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st, const TargetInstrInfo &tii) - : BlackfinGenRegisterInfo(BlackfinRegDesc, BlackfinRegInfoDesc, - BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP), + : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP), Subtarget(st), TII(tii) {} Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -189,8 +189,7 @@ SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii) : - SPUGenRegisterInfo(SPURegDesc, SPURegInfoDesc, - SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP), + SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP), Subtarget(subtarget), TII(tii) { Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -45,8 +45,7 @@ MBlazeRegisterInfo:: MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii) - : MBlazeGenRegisterInfo(MBlazeRegDesc, MBlazeRegInfoDesc, - MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP), + : MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP), Subtarget(ST), TII(tii) {} /// getRegisterNumbering - Given the enum value for some register, e.g. Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -35,8 +35,7 @@ // FIXME: Provide proper call frame setup / destroy opcodes. MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm, const TargetInstrInfo &tii) - : MSP430GenRegisterInfo(MSP430RegDesc, MSP430RegInfoDesc, - MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP), + : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP), TM(tm), TII(tii) { StackAlign = TM.getFrameLowering()->getStackAlignment(); } Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -44,8 +44,7 @@ MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST, const TargetInstrInfo &tii) - : MipsGenRegisterInfo(MipsRegDesc, MipsRegInfoDesc, - Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), + : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), Subtarget(ST), TII(tii) {} /// getRegisterNumbering - Given the enum value for some register, e.g. Modified: llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXRegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -25,7 +25,7 @@ PTXRegisterInfo::PTXRegisterInfo(PTXTargetMachine &TM, const TargetInstrInfo &TII) - : PTXGenRegisterInfo(PTXRegDesc, PTXRegInfoDesc) { + : PTXGenRegisterInfo() { } void PTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -114,8 +114,7 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, const TargetInstrInfo &tii) - : PPCGenRegisterInfo(PPCRegDesc, PPCRegInfoDesc, - PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), + : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), Subtarget(ST), TII(tii) { ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -32,8 +32,7 @@ SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii) - : SparcGenRegisterInfo(SparcRegDesc, SparcRegInfoDesc, - SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), + : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), Subtarget(st), TII(tii) { } Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -34,8 +34,7 @@ SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm, const SystemZInstrInfo &tii) - : SystemZGenRegisterInfo(SystemZRegDesc, SystemZRegInfoDesc, - SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN), + : SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN), TM(tm), TII(tii) { } Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -54,8 +54,7 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii) - : X86GenRegisterInfo(X86RegDesc, X86RegInfoDesc, - tm.getSubtarget().is64Bit() ? + : X86GenRegisterInfo(tm.getSubtarget().is64Bit() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32, tm.getSubtarget().is64Bit() ? Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Tue Jun 28 15:44:22 2011 @@ -40,8 +40,7 @@ using namespace llvm; XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii) - : XCoreGenRegisterInfo(XCoreRegDesc, XCoreRegInfoDesc, - XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), + : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), TII(tii) { } Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=134027&r1=134026&r2=134027&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue Jun 28 15:44:22 2011 @@ -215,8 +215,7 @@ OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" << " explicit " << ClassName - << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, " - << "int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" + << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" << " virtual int getDwarfRegNumFull(unsigned RegNum, " << "unsigned Flavour) const;\n" << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " @@ -549,8 +548,9 @@ OS << " };\n"; // Emit extra information about registers. + const std::string &TargetName = Target.getName(); OS << "\n static const TargetRegisterInfoDesc " - << Target.getName() << "RegInfoDesc[] = " + << TargetName << "RegInfoDesc[] = " << "{ // Extra Descriptors\n"; OS << " { 0, 0 },\n"; @@ -660,13 +660,13 @@ // Emit the constructor of the class... OS << ClassName << "::" << ClassName - << "(const MCRegisterDesc *D, const TargetRegisterInfoDesc *ID, " - << "int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" - << " : TargetRegisterInfo(ID" + << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" + << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" << " SubRegIndexTable,\n" << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n" - << " InitMCRegisterInfo(D, " << Regs.size()+1 << ");\n" + << " InitMCRegisterInfo(" << TargetName << "RegDesc, " + << Regs.size()+1 << ");\n" << "}\n\n"; // Collect all information about dwarf register numbers From zwarich at apple.com Tue Jun 28 15:46:14 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Tue, 28 Jun 2011 13:46:14 -0700 Subject: [llvm-commits] ideas for 10096 In-Reply-To: <4E0A1F01.6090408@gmail.com> References: <4E0A1F01.6090408@gmail.com> Message-ID: On Jun 28, 2011, at 11:35 AM, Rafael ?vila de Esp?ndola wrote: > I am trying to fix 10203 and currently I have three ideas of how it > might be fixed: > > *) Fix bit rot on the strong phi elimination. IT currently crashes when > building firefox. If you can attach a reduced .ll file to a bug I should be able to look at it this weekend. When I stopped working on strong phi elimination it was working well on x86. I don't think we will ever turn strong phi elimination on by default, at least in its current form. It doesn't give enough of an improvement in either compile time or the quality of generated code to be worth it. There are also tricky phase ordering issues between the 2-addr pass, strong phi elimination, and the coalescer. > *) A simple preprocessioning pass that would try to convert > > %vreg40 = COPY %vreg45 > %vreg42 = COPY %vreg45 > > to > > %vreg40 = COPY %vreg45 > %vreg42 = COPY %vreg40 > > That is, try to use in the RHS values that have been defined in the same bb. > > * The third idea (which I like a bit more right now) is to change the > coalescer itself > > Right now it works in three stages if I understand it correctly. > 1) it collects which value numbers of A are copies of B and B of A. > 2) It then optimistically merges the intervals, by first copying the > LHS and then the RHS with exceptions for the A=B and B=A cases. > 3) It now walks the ranges of both registers looking for overlapping > ones. If it finds one, it checks if both have the same value number in > the new merged interval. > > I think this can be done in one pass. As we walk the ranges, we can > find the value numbers and check if they are compatible. Doing this in > one pass then has the advantage that it is easy to add support for the > case we have in the bug. > > In this case, the dominance check can be as simple an "defined earlier > in the same bb". > > So, do you agree with the third option being the best or would a > preprocess pass (or fixing the strong phi elimination) be better? This one-pass algorithm sounds like a dominance-based coalescing algorithm applied to the live ranges of the two live intervals, with a dominance test approximated by something weaker. I would be worried about a compile-time regression, since I see the optimistic case kicking in quite a bit when running -debug on the coalescer. Can't you just handle this in the exceptional case of coalescing, i.e. check whether both valnos are defined by a copy of the same value in the same basic block and pick the first one to be the 'leader'? I think the correct thing long-term is for phi elimination to produce parallel copies, and for the coalescer to take advantage of this. It would then be even easier to do this sort of a check. When checking whether two seemingly overlapping live ranges actually interfere, you could just check whether they are defined by the same value at the same parallel copy. I have been working on this off and on with a branch, but I wanted to wait until linear scan is gone (taking physical register coalescing with it) before heavily modifying the coalescer on trunk. Cameron From evan.cheng at apple.com Tue Jun 28 16:14:33 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 28 Jun 2011 21:14:33 -0000 Subject: [llvm-commits] [llvm] r134030 - in /llvm/trunk: include/llvm/Target/ lib/CodeGen/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ utils/TableGen/ Message-ID: <20110628211434.7CCD62A6C12C@llvm.org> Author: evancheng Date: Tue Jun 28 16:14:33 2011 New Revision: 134030 URL: http://llvm.org/viewvc/llvm-project?rev=134030&view=rev Log: Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h llvm/trunk/include/llvm/Target/TargetRegisterInfo.h llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMFastISel.cpp llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp llvm/trunk/lib/Target/TargetInstrInfo.cpp llvm/trunk/lib/Target/TargetRegisterInfo.cpp llvm/trunk/lib/Target/X86/X86FastISel.cpp llvm/trunk/lib/Target/X86/X86InstrInfo.cpp llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Jun 28 16:14:33 2011 @@ -44,7 +44,9 @@ TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT public: - TargetInstrInfo(const MCInstrDesc *desc, unsigned NumOpcodes); + TargetInstrInfo(const MCInstrDesc *desc, unsigned NumOpcodes, + int CallFrameSetupOpcode = -1, + int CallFrameDestroyOpcode = -1); virtual ~TargetInstrInfo(); /// getRegClass - Givem a machine instruction descriptor, returns the register @@ -86,6 +88,15 @@ AliasAnalysis *AA) const; public: + /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the + /// frame setup/destroy instructions if they exist (-1 otherwise). Some + /// targets use pseudo instructions in order to abstract away the difference + /// between operating with a frame pointer and operating without, through the + /// use of these two instructions. + /// + int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } + int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } + /// isCoalescableExtInstr - Return true if the instruction is a "coalescable" /// extension instruction. That is, it's like a copy where it's legal for the /// source to overlap the destination. e.g. X86::MOVSX64rr32. If this returns @@ -656,6 +667,9 @@ virtual bool hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const; + +private: + int CallFrameSetupOpcode, CallFrameDestroyOpcode; }; /// TargetInstrInfoImpl - This is the default implementation of @@ -664,7 +678,9 @@ /// libcodegen, not in libtarget. class TargetInstrInfoImpl : public TargetInstrInfo { protected: - TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes) + TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes, + int CallFrameSetupOpcode = -1, + int CallFrameDestroyOpcode = -1) : TargetInstrInfo(desc, NumOpcodes) {} public: virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Tue Jun 28 16:14:33 2011 @@ -275,15 +275,12 @@ const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen const char *const *SubRegIndexNames; // Names of subreg indexes. regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses - int CallFrameSetupOpcode, CallFrameDestroyOpcode; protected: TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RegClassBegin, regclass_iterator RegClassEnd, - const char *const *subregindexnames, - int CallFrameSetupOpcode = -1, - int CallFrameDestroyOpcode = -1); + const char *const *subregindexnames); virtual ~TargetRegisterInfo(); public: @@ -661,15 +658,6 @@ return false; // Must return a value in order to compile with VS 2005 } - /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the - /// frame setup/destroy instructions if they exist (-1 otherwise). Some - /// targets use pseudo instructions in order to abstract away the difference - /// between operating with a frame pointer and operating without, through the - /// use of these two instructions. - /// - int getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } - int getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } - /// eliminateCallFramePseudoInstr - This method is called during prolog/epilog /// code insertion to eliminate call frame setup and destroy pseudo /// instructions (but only if the Target is using them). It is responsible @@ -681,9 +669,6 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const { - assert(getCallFrameSetupOpcode()== -1 && getCallFrameDestroyOpcode()== -1 && - "eliminateCallFramePseudoInstr must be implemented if using" - " call frame setup/destroy pseudo instructions!"); assert(0 && "Call Frame Pseudo Instructions do not exist on this target!"); } Modified: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp (original) +++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp Tue Jun 28 16:14:33 2011 @@ -145,6 +145,7 @@ /// pseudo instructions. void PEI::calculateCallsInformation(MachineFunction &Fn) { const TargetRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo(); + const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); const TargetFrameLowering *TFI = Fn.getTarget().getFrameLowering(); MachineFrameInfo *MFI = Fn.getFrameInfo(); @@ -152,8 +153,8 @@ bool AdjustsStack = MFI->adjustsStack(); // Get the function call frame set-up and tear-down instruction opcode - int FrameSetupOpcode = RegInfo->getCallFrameSetupOpcode(); - int FrameDestroyOpcode = RegInfo->getCallFrameDestroyOpcode(); + int FrameSetupOpcode = TII.getCallFrameSetupOpcode(); + int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode(); // Early exit for targets which have no call frame setup/destroy pseudo // instructions. @@ -705,12 +706,13 @@ const TargetMachine &TM = Fn.getTarget(); assert(TM.getRegisterInfo() && "TM::getRegisterInfo() must be implemented!"); + const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo(); const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); const TargetFrameLowering *TFI = TM.getFrameLowering(); bool StackGrowsDown = TFI->getStackGrowthDirection() == TargetFrameLowering::StackGrowsDown; - int FrameSetupOpcode = TRI.getCallFrameSetupOpcode(); - int FrameDestroyOpcode = TRI.getCallFrameDestroyOpcode(); + int FrameSetupOpcode = TII.getCallFrameSetupOpcode(); + int FrameDestroyOpcode = TII.getCallFrameDestroyOpcode(); for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -77,7 +77,8 @@ }; ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI) - : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)), + : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts), + ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), Subtarget(STI) { for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) { if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second) Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -58,8 +58,7 @@ ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &sti) - : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP), - TII(tii), STI(sti), + : ARMGenRegisterInfo(), TII(tii), STI(sti), FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11), BasePtr(ARM::R6) { } Modified: llvm/trunk/lib/Target/ARM/ARMFastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFastISel.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMFastISel.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMFastISel.cpp Tue Jun 28 16:14:33 2011 @@ -1549,7 +1549,7 @@ NumBytes = CCInfo.getNextStackOffset(); // Issue CALLSEQ_START - unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); + unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown)) .addImm(NumBytes)); @@ -1647,7 +1647,7 @@ const Instruction *I, CallingConv::ID CC, unsigned &NumBytes) { // Issue CALLSEQ_END - unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); + unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp)) .addImm(NumBytes).addImm(0)); Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -25,7 +25,8 @@ using namespace llvm; AlphaInstrInfo::AlphaInstrInfo() - : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)), + : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts), + Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP), RI(*this) { } Modified: llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaRegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -41,7 +41,7 @@ using namespace llvm; AlphaRegisterInfo::AlphaRegisterInfo(const TargetInstrInfo &tii) - : AlphaGenRegisterInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP), + : AlphaGenRegisterInfo(), TII(tii) { } Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -26,7 +26,8 @@ using namespace llvm; BlackfinInstrInfo::BlackfinInstrInfo(BlackfinSubtarget &ST) - : TargetInstrInfoImpl(BlackfinInsts, array_lengthof(BlackfinInsts)), + : TargetInstrInfoImpl(BlackfinInsts, array_lengthof(BlackfinInsts), + BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP), RI(ST, *this), Subtarget(ST) {} Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -38,9 +38,7 @@ BlackfinRegisterInfo::BlackfinRegisterInfo(BlackfinSubtarget &st, const TargetInstrInfo &tii) - : BlackfinGenRegisterInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP), - Subtarget(st), - TII(tii) {} + : BlackfinGenRegisterInfo(), Subtarget(st), TII(tii) {} const unsigned* BlackfinRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -53,7 +53,8 @@ } SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm) - : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])), + : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0]), + SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP), TM(tm), RI(*TM.getSubtargetImpl(), *this) { /* NOP */ } Modified: llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPURegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -189,9 +189,7 @@ SPURegisterInfo::SPURegisterInfo(const SPUSubtarget &subtarget, const TargetInstrInfo &tii) : - SPUGenRegisterInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP), - Subtarget(subtarget), - TII(tii) + SPUGenRegisterInfo(), Subtarget(subtarget), TII(tii) { } Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -27,7 +27,8 @@ using namespace llvm; MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm) - : TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts)), + : TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts), + MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP), TM(tm), RI(*TM.getSubtargetImpl(), *this) {} static bool isZeroImm(const MachineOperand &op) { Modified: llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeRegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -45,8 +45,7 @@ MBlazeRegisterInfo:: MBlazeRegisterInfo(const MBlazeSubtarget &ST, const TargetInstrInfo &tii) - : MBlazeGenRegisterInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP), - Subtarget(ST), TII(tii) {} + : MBlazeGenRegisterInfo(), Subtarget(ST), TII(tii) {} /// getRegisterNumbering - Given the enum value for some register, e.g. /// MBlaze::R0, return the number that it corresponds to (e.g. 0). Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -28,7 +28,8 @@ using namespace llvm; MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm) - : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts)), + : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts), + MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP), RI(tm, *this), TM(tm) {} void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, Modified: llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430RegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -35,8 +35,7 @@ // FIXME: Provide proper call frame setup / destroy opcodes. MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm, const TargetInstrInfo &tii) - : MSP430GenRegisterInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP), - TM(tm), TII(tii) { + : MSP430GenRegisterInfo(), TM(tm), TII(tii) { StackAlign = TM.getFrameLowering()->getStackAlignment(); } @@ -121,12 +120,12 @@ Amount = (Amount+StackAlign-1)/StackAlign*StackAlign; MachineInstr *New = 0; - if (Old->getOpcode() == getCallFrameSetupOpcode()) { + if (Old->getOpcode() == TII.getCallFrameSetupOpcode()) { New = BuildMI(MF, Old->getDebugLoc(), TII.get(MSP430::SUB16ri), MSP430::SPW) .addReg(MSP430::SPW).addImm(Amount); } else { - assert(Old->getOpcode() == getCallFrameDestroyOpcode()); + assert(Old->getOpcode() == TII.getCallFrameDestroyOpcode()); // factor out the amount the callee already popped. uint64_t CalleeAmt = Old->getOperand(1).getImm(); Amount -= CalleeAmt; @@ -144,7 +143,7 @@ MBB.insert(I, New); } } - } else if (I->getOpcode() == getCallFrameDestroyOpcode()) { + } else if (I->getOpcode() == TII.getCallFrameDestroyOpcode()) { // If we are performing frame pointer elimination and if the callee pops // something off the stack pointer, add it back. if (uint64_t CalleeAmt = I->getOperand(1).getImm()) { Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -25,7 +25,8 @@ using namespace llvm; MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm) - : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)), + : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts), + Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), TM(tm), RI(*TM.getSubtargetImpl(), *this) {} static bool isZeroImm(const MachineOperand &op) { Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -44,8 +44,7 @@ MipsRegisterInfo::MipsRegisterInfo(const MipsSubtarget &ST, const TargetInstrInfo &tii) - : MipsGenRegisterInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), - Subtarget(ST), TII(tii) {} + : MipsGenRegisterInfo(), Subtarget(ST), TII(tii) {} /// getRegisterNumbering - Given the enum value for some register, e.g. /// Mips::RA, return the number that it corresponds to (e.g. 31). Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -39,8 +39,9 @@ using namespace llvm; PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm) - : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm), - RI(*TM.getSubtargetImpl(), *this) {} + : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts), + PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), + TM(tm), RI(*TM.getSubtargetImpl(), *this) {} /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for /// this target when scheduling the DAG. Modified: llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCRegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -114,8 +114,7 @@ PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST, const TargetInstrInfo &tii) - : PPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP), - Subtarget(ST), TII(tii) { + : PPCGenRegisterInfo(), Subtarget(ST), TII(tii) { ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX; ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX; ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX; Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -27,7 +27,8 @@ using namespace llvm; SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST) - : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)), + : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts), + SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), RI(ST, *this), Subtarget(ST) { } Modified: llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcRegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -32,8 +32,7 @@ SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st, const TargetInstrInfo &tii) - : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP), - Subtarget(st), TII(tii) { + : SparcGenRegisterInfo(), Subtarget(st), TII(tii) { } const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -29,7 +29,8 @@ using namespace llvm; SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm) - : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts)), + : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts), + SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN), RI(tm, *this), TM(tm) { } Modified: llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZRegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -34,8 +34,7 @@ SystemZRegisterInfo::SystemZRegisterInfo(SystemZTargetMachine &tm, const SystemZInstrInfo &tii) - : SystemZGenRegisterInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN), - TM(tm), TII(tii) { + : SystemZGenRegisterInfo(), TM(tm), TII(tii) { } const unsigned* Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -24,7 +24,10 @@ // TargetInstrInfo //===----------------------------------------------------------------------===// -TargetInstrInfo::TargetInstrInfo(const MCInstrDesc* Desc, unsigned numOpcodes) { +TargetInstrInfo::TargetInstrInfo(const MCInstrDesc* Desc, unsigned numOpcodes, + int CFSetupOpcode, int CFDestroyOpcode) + : CallFrameSetupOpcode(CFSetupOpcode), + CallFrameDestroyOpcode(CFDestroyOpcode) { InitMCInstrInfo(Desc, numOpcodes); } Modified: llvm/trunk/lib/Target/TargetRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetRegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetRegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -22,12 +22,9 @@ TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, regclass_iterator RCB, regclass_iterator RCE, - const char *const *subregindexnames, - int CFSO, int CFDO) + const char *const *subregindexnames) : InfoDesc(ID), SubRegIndexNames(subregindexnames), RegClassBegin(RCB), RegClassEnd(RCE) { - CallFrameSetupOpcode = CFSO; - CallFrameDestroyOpcode = CFDO; } TargetRegisterInfo::~TargetRegisterInfo() {} Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original) +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Jun 28 16:14:33 2011 @@ -1630,7 +1630,7 @@ unsigned NumBytes = CCInfo.getNextStackOffset(); // Issue CALLSEQ_START - unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode(); + unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown)) .addImm(NumBytes); @@ -1803,7 +1803,7 @@ MIB.addReg(RegArgs[i]); // Issue CALLSEQ_END - unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode(); + unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); unsigned NumBytesCallee = 0; if (!Subtarget->is64Bit() && CS.paramHasAttr(1, Attribute::StructRet)) NumBytesCallee = 4; Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -54,7 +54,13 @@ cl::init(false), cl::Hidden); X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) - : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)), + : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts), + (tm.getSubtarget().is64Bit() + ? X86::ADJCALLSTACKDOWN64 + : X86::ADJCALLSTACKDOWN32), + (tm.getSubtarget().is64Bit() + ? X86::ADJCALLSTACKUP64 + : X86::ADJCALLSTACKUP32)), TM(tm), RI(tm, *this) { enum { TB_NOT_REVERSABLE = 1U << 31, Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -54,13 +54,7 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii) - : X86GenRegisterInfo(tm.getSubtarget().is64Bit() ? - X86::ADJCALLSTACKDOWN64 : - X86::ADJCALLSTACKDOWN32, - tm.getSubtarget().is64Bit() ? - X86::ADJCALLSTACKUP64 : - X86::ADJCALLSTACKUP32), - TM(tm), TII(tii) { + : X86GenRegisterInfo(), TM(tm), TII(tii) { // Cache some information. const X86Subtarget *Subtarget = &TM.getSubtarget(); Is64Bit = Subtarget->is64Bit(); @@ -608,7 +602,7 @@ const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering(); bool reseveCallFrame = TFI->hasReservedCallFrame(MF); int Opcode = I->getOpcode(); - bool isDestroy = Opcode == getCallFrameDestroyOpcode(); + bool isDestroy = Opcode == TII.getCallFrameDestroyOpcode(); DebugLoc DL = I->getDebugLoc(); uint64_t Amount = !reseveCallFrame ? I->getOperand(0).getImm() : 0; uint64_t CalleeAmt = isDestroy ? I->getOperand(1).getImm() : 0; @@ -629,13 +623,13 @@ Amount = (Amount + StackAlign - 1) / StackAlign * StackAlign; MachineInstr *New = 0; - if (Opcode == getCallFrameSetupOpcode()) { + if (Opcode == TII.getCallFrameSetupOpcode()) { New = BuildMI(MF, DL, TII.get(getSUBriOpcode(Is64Bit, Amount)), StackPtr) .addReg(StackPtr) .addImm(Amount); } else { - assert(Opcode == getCallFrameDestroyOpcode()); + assert(Opcode == TII.getCallFrameDestroyOpcode()); // Factor out the amount the callee already popped. Amount -= CalleeAmt; @@ -658,7 +652,7 @@ return; } - if (Opcode == getCallFrameDestroyOpcode() && CalleeAmt) { + if (Opcode == TII.getCallFrameDestroyOpcode() && CalleeAmt) { // If we are performing frame pointer elimination and if the callee pops // something off the stack pointer, add it back. We do this until we have // more advanced stack pointer tracking ability. Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Tue Jun 28 16:14:33 2011 @@ -40,7 +40,8 @@ using namespace llvm; XCoreInstrInfo::XCoreInstrInfo() - : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts)), + : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts), + XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), RI(*this) { } Modified: llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreRegisterInfo.cpp Tue Jun 28 16:14:33 2011 @@ -40,8 +40,7 @@ using namespace llvm; XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii) - : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP), - TII(tii) { + : XCoreGenRegisterInfo(), TII(tii) { } // helper functions Modified: llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp?rev=134030&r1=134029&r2=134030&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp Tue Jun 28 16:14:33 2011 @@ -214,8 +214,7 @@ OS << "namespace llvm {\n\n"; OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" - << " explicit " << ClassName - << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" + << " explicit " << ClassName << "();\n" << " virtual int getDwarfRegNumFull(unsigned RegNum, " << "unsigned Flavour) const;\n" << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, " @@ -660,11 +659,10 @@ // Emit the constructor of the class... OS << ClassName << "::" << ClassName - << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" + << "()\n" << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc" << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n" - << " SubRegIndexTable,\n" - << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {\n" + << " SubRegIndexTable) {\n" << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size()+1 << ");\n" << "}\n\n"; From evan.cheng at apple.com Tue Jun 28 16:33:11 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 28 Jun 2011 21:33:11 -0000 Subject: [llvm-commits] [llvm] r134031 - /llvm/trunk/include/llvm/Target/TargetInstrInfo.h Message-ID: <20110628213311.538E62A6C12C@llvm.org> Author: evancheng Date: Tue Jun 28 16:33:11 2011 New Revision: 134031 URL: http://llvm.org/viewvc/llvm-project?rev=134031&view=rev Log: Unbreak every backend. Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=134031&r1=134030&r2=134031&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Tue Jun 28 16:33:11 2011 @@ -681,7 +681,8 @@ TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes, int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1) - : TargetInstrInfo(desc, NumOpcodes) {} + : TargetInstrInfo(desc, NumOpcodes, + CallFrameSetupOpcode, CallFrameDestroyOpcode) {} public: virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst, MachineBasicBlock *NewDest) const; From geek4civic at gmail.com Tue Jun 28 16:46:21 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Tue, 28 Jun 2011 21:46:21 -0000 Subject: [llvm-commits] [llvm] r134033 - /llvm/trunk/test/CMakeLists.txt Message-ID: <20110628214621.744602A6C12C@llvm.org> Author: chapuni Date: Tue Jun 28 16:46:21 2011 New Revision: 134033 URL: http://llvm.org/viewvc/llvm-project?rev=134033&view=rev Log: Fix a CMake warning, following up to r134008. Modified: llvm/trunk/test/CMakeLists.txt Modified: llvm/trunk/test/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CMakeLists.txt?rev=134033&r1=134032&r2=134033&view=diff ============================================================================== --- llvm/trunk/test/CMakeLists.txt (original) +++ llvm/trunk/test/CMakeLists.txt Tue Jun 28 16:46:21 2011 @@ -85,7 +85,7 @@ set(ENABLE_ASSERTIONS "1") else() set(ENABLE_ASSERTIONS "0") - endif(LLVM_ENABLE_ASSERTIONS) + endif() configure_file( ${CMAKE_CURRENT_SOURCE_DIR}/lit.site.cfg.in From evan.cheng at apple.com Tue Jun 28 17:08:57 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Tue, 28 Jun 2011 15:08:57 -0700 Subject: [llvm-commits] LLVM JIT Adaptive Compilation Patch In-Reply-To: References: Message-ID: <2AEEA453-1625-4B66-B025-012FD3B49344@apple.com> I have mixed feeling about this patch. On one hand, having some infrastructure in place for adaptive JIT is goodness. However, the current ExecutionEngine pre-dates MC JIT and it is heading towards a major change. For this reason, I'd prefer not to take patches that extend / changes EE interface at this time. Evan On Jun 23, 2011, at 7:32 PM, Xin Tong Utoronto wrote: > One of the current drawbacks of the LLVM JIT is the lack of an adaptive compilation system. All the non-adaptive bits are already there in LLVM: optimizing compiler with the different types of instruction selectors, register allocators, preRA schedulers, etc. and a full set of optimizations changeable at runtime. What's left is a system that can keep track of and dynamically look-up the hotness of methods and re-compile with more expensive optimizations as the methods are executed over and over. This should improve program startup time and execution time and will bring great benefits to all ported languages that intend to use LLVM JIT as one of the execution methods. > The implementation of the adaptive compilation framework is one of the Google Summer of Code 2011 project (http://www.google-melange.com/gsoc/project/google/gsoc2011/timexerox/8001). This patch is intended to provide the basic infrastructure for the adaptive compilation framework. Code for specific platforms are currently being developed. This patch is generate against the LLVM trunk and using GIT. > > -- > Kind Regards > > Xin Tong > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110628/9bb62384/attachment.html From daniel at zuster.org Tue Jun 28 17:30:17 2011 From: daniel at zuster.org (Daniel Dunbar) Date: Tue, 28 Jun 2011 22:30:17 -0000 Subject: [llvm-commits] [llvm] r134036 - /llvm/trunk/Makefile.rules Message-ID: <20110628223017.B805F2A6C12C@llvm.org> Author: ddunbar Date: Tue Jun 28 17:30:17 2011 New Revision: 134036 URL: http://llvm.org/viewvc/llvm-project?rev=134036&view=rev Log: build/Darwin: Fix epic typo fail. Modified: llvm/trunk/Makefile.rules Modified: llvm/trunk/Makefile.rules URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=134036&r1=134035&r2=134036&view=diff ============================================================================== --- llvm/trunk/Makefile.rules (original) +++ llvm/trunk/Makefile.rules Tue Jun 28 17:30:17 2011 @@ -1377,7 +1377,7 @@ #--------------------------------------------------------- ifeq ($(HOST_OS),Darwin) -ifdef TOOL_ORDER_FINE +ifdef TOOL_ORDER_FILE LD.Flags += -Wl,-order_file,$(TOOL_ORDER_FILE) From x.tong at utoronto.ca Tue Jun 28 17:33:21 2011 From: x.tong at utoronto.ca (Xin Tong Utoronto) Date: Tue, 28 Jun 2011 18:33:21 -0400 Subject: [llvm-commits] LLVM JIT Adaptive Compilation Patch In-Reply-To: <2AEEA453-1625-4B66-B025-012FD3B49344@apple.com> References: <2AEEA453-1625-4B66-B025-012FD3B49344@apple.com> Message-ID: Most of the changes in this patch are within JIT.cpp and JIT.hpp. Only a few variables are added to ExecutionEngine . I am now sure how this is going to affect MC JIT. Also, when is the major change for the MC JIT going to be completed ? Xin On Tue, Jun 28, 2011 at 6:08 PM, Evan Cheng wrote: > I have mixed feeling about this patch. On one hand, having some > infrastructure in place for adaptive JIT is goodness. However, the current > ExecutionEngine pre-dates MC JIT and it is heading towards a major change. > For this reason, I'd prefer not to take patches that extend / changes EE > interface at this time. > > Evan > > On Jun 23, 2011, at 7:32 PM, Xin Tong Utoronto wrote: > > One of the current drawbacks of the LLVM JIT is the lack of an adaptive compilation system. All the non-adaptive bits are already there in LLVM: optimizing compiler with the different types of instruction selectors, register allocators, preRA schedulers, etc. and a full set of optimizations changeable at runtime. What's left is a system that can keep track of and dynamically look-up the hotness of methods and re-compile with more expensive optimizations as the methods are executed over and over. This should improve program startup time and execution time and will bring great benefits to all ported languages that intend to use LLVM JIT as one of the execution methods. > > The implementation of the adaptive compilation framework is one of the Google Summer of Code 2011 project (http://www.google-melange.com/gsoc/project/google/gsoc2011/timexerox/8001). This patch is intended to provide the basic infrastructure for the adaptive compilation framework. Code for specific platforms are currently being developed. This patch is generate against the LLVM trunk and using GIT. > > > -- > Kind Regards > > Xin Tong > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > > -- Kind Regards Xin Tong -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110628/94e86ffd/attachment.html From echristo at apple.com Tue Jun 28 18:17:19 2011 From: echristo at apple.com (Eric Christopher) Date: Tue, 28 Jun 2011 16:17:19 -0700 Subject: [llvm-commits] LLVM JIT Adaptive Compilation Patch In-Reply-To: References: <2AEEA453-1625-4B66-B025-012FD3B49344@apple.com> Message-ID: On Jun 28, 2011, at 3:33 PM, Xin Tong Utoronto wrote: > Most of the changes in this patch are within JIT.cpp and JIT.hpp. Only a few variables are added to ExecutionEngine . I am now sure how this is going to affect MC JIT. Also, when is the major change for the MC JIT going to be completed ? We're overall not sure about the latter. Some of the work has been completed, but it's not a full-fledged replacement for the current JIT yet. How about we put your work on a branch for now, get it working and optimized, get some more compelling results and see where we are from there? If we can get some more compelling results it could also be used to get other users of the JIT interested in the adaptive compilation strategy. I'll go ahead and create the branch and apply your patch tonight. From there we can talk about getting your next patch reviewed and then applied. Past that we'll look at getting you commit access. Sound like a workable plan? -eric From aggarwa4 at illinois.edu Tue Jun 28 18:40:14 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 28 Jun 2011 23:40:14 -0000 Subject: [llvm-commits] [poolalloc] r134043 - in /poolalloc/trunk/lib/AssistDS: TypeChecks.cpp TypeChecksOpt.cpp Message-ID: <20110628234014.F29AD2A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jun 28 18:40:14 2011 New Revision: 134043 URL: http://llvm.org/viewvc/llvm-project?rev=134043&view=rev Log: 1. Handle callInst and InvokeInst, using CallSite. Refactoring, no functionality change. 2. Add support for strtol 3. Fix the count for the tag parameter when optimizing the call. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=134043&r1=134042&r2=134043&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue Jun 28 18:40:14 2011 @@ -840,6 +840,7 @@ // Find all uses of the function for(Value::use_iterator ui = F.use_begin(), ue = F.use_end(); ui != ue;ui ++) { + // Check for call sites if(InvokeInst *II = dyn_cast(ui)) { std::vector Args; @@ -1656,6 +1657,16 @@ Constant *F = M.getOrInsertFunction("trackctype_32", VoidTy, VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); + } else if (F->getNameStr() == std::string("strtol")) { + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy, "", I); + const PointerType *PTy = cast(CS.getArgument(1)->getType()); + const Type * ElementType = PTy->getElementType(); + std::vectorArgs; + Args.push_back(BCI); + Args.push_back(getSizeConstant(ElementType)); + Args.push_back(getTagCounter()); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); + return true; } else if (F->getNameStr() == std::string("strcat") || F->getNameStr() == std::string("_ZNSspLEPKc")) { CastInst *BCI_Src = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy, "", I); @@ -1813,67 +1824,41 @@ CastInst *Func = CastInst::CreatePointerCast(I->getOperand(0), FTy->getPointerTo(), "", I); inst_iterator InsPt = inst_begin(I->getParent()->getParent()); - - if(isa(I)) { - unsigned int NumArgs = I->getNumOperands() - 1; - Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); - - AllocaInst *AI = new AllocaInst(TypeTagTy, NumArgsVal, "", &*InsPt); - for(unsigned int i = 1; i < I->getNumOperands(); i++) { - Value *Idx[2]; - Idx[0] = ConstantInt::get(Int32Ty, i-1); - GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, - Idx, - Idx + 1, - "", I); - Constant *C = getTypeMarkerConstant(I->getOperand(i)); - new StoreInst(C, GEP, I); - } - - std::vector Args; - Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); - Args.push_back(AI); - - for(unsigned int i = 1; i < I->getNumOperands(); i++) - Args.push_back(I->getOperand(i)); + CallSite CS = CallSite(I); + unsigned int NumArgs = CS.arg_size(); + Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); + AllocaInst *AI = new AllocaInst(TypeTagTy, NumArgsVal, "", &*InsPt); + for(unsigned int i = 0; i < CS.arg_size(); i++) { + Value *Idx[2]; + Idx[0] = ConstantInt::get(Int32Ty, i-1); + GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, + Idx, + Idx + 1, + "", I); + Constant *C = getTypeMarkerConstant(CS.getArgument(i)); + new StoreInst(C, GEP, I); + } + std::vector Args; + Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); + Args.push_back(AI); + for(unsigned int i = 0; i < CS.arg_size(); i++) + Args.push_back(CS.getArgument(i)); + if(CallInst *CI = dyn_cast(I)) { CallInst *CI_New = CallInst::Create(Func, Args.begin(), Args.end(), - "", I); - I->replaceAllUsesWith(CI_New); - I->eraseFromParent(); + "", CI); + CI->replaceAllUsesWith(CI_New); + CI->eraseFromParent(); } else if(InvokeInst *II = dyn_cast(I)) { - unsigned int NumArgs = I->getNumOperands() - 3; - Value *NumArgsVal = ConstantInt::get(Int32Ty, NumArgs); - - AllocaInst *AI = new AllocaInst(TypeTagTy, NumArgsVal, "", &*InsPt); - for(unsigned int i = 3; i < I->getNumOperands(); i++) { - Value *Idx[2]; - Idx[0] = ConstantInt::get(Int32Ty, i-3); - GetElementPtrInst *GEP = GetElementPtrInst::CreateInBounds(AI, - Idx, - Idx + 1, - "", I); - Constant *C = getTypeMarkerConstant(I->getOperand(i)); - new StoreInst(C, GEP, I); - } - std::vector Args; - Args.push_back(ConstantInt::get(Int64Ty, NumArgs)); - Args.push_back(AI); - - for(unsigned int i = 3; i < I->getNumOperands(); i++) { - Args.push_back(I->getOperand(i)); - } - InvokeInst *INew = InvokeInst::Create(Func, II->getNormalDest(), II->getUnwindDest(), Args.begin(), Args.end(), "", I); - I->replaceAllUsesWith(INew); - I->eraseFromParent(); - + II->replaceAllUsesWith(INew); + II->eraseFromParent(); } return true; } Modified: poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp?rev=134043&r1=134042&r2=134043&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecksOpt.cpp Tue Jun 28 18:40:14 2011 @@ -217,7 +217,7 @@ std::vector Args; Args.push_back(CI->getOperand(1)); Args.push_back(CI->getOperand(3)); // size - Args.push_back(CI->getOperand(4)); + Args.push_back(CI->getOperand(5)); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", CI); toDelete.push_back(CI); } From aggarwa4 at illinois.edu Tue Jun 28 18:49:40 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Tue, 28 Jun 2011 23:49:40 -0000 Subject: [llvm-commits] [poolalloc] r134044 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110628234940.962D32A6C12C@llvm.org> Author: aggarwa4 Date: Tue Jun 28 18:49:40 2011 New Revision: 134044 URL: http://llvm.org/viewvc/llvm-project?rev=134044&view=rev Log: Add support for strtod. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=134044&r1=134043&r2=134044&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Tue Jun 28 18:49:40 2011 @@ -1657,7 +1657,8 @@ Constant *F = M.getOrInsertFunction("trackctype_32", VoidTy, VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); - } else if (F->getNameStr() == std::string("strtol")) { + } else if (F->getNameStr() == std::string("strtol") || + F->getNameStr() == std::string("strtod")) { CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy, "", I); const PointerType *PTy = cast(CS.getArgument(1)->getType()); const Type * ElementType = PTy->getElementType(); From rafael.espindola at gmail.com Tue Jun 28 19:08:43 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Tue, 28 Jun 2011 20:08:43 -0400 Subject: [llvm-commits] ideas for 10096 In-Reply-To: References: <4E0A1F01.6090408@gmail.com> Message-ID: <4E0A6D0B.2080208@gmail.com> >> *) Fix bit rot on the strong phi elimination. IT currently crashes >> when building firefox. > > If you can attach a reduced .ll file to a bug I should be able to > look at it this weekend. When I stopped working on strong phi > elimination it was working well on x86. I will try to open a bug before the weekend ]. >> So, do you agree with the third option being the best or would a >> preprocess pass (or fixing the strong phi elimination) be better? > > This one-pass algorithm sounds like a dominance-based coalescing > algorithm applied to the live ranges of the two live intervals, with > a dominance test approximated by something weaker. I would be > worried about a compile-time regression, since I see the optimistic > case kicking in quite a bit when running -debug on the coalescer. > Can't you just handle this in the exceptional case of coalescing, > i.e. check whether both valnos are defined by a copy of the same > value in the same basic block and pick the first one to be the > 'leader'? That is what I am trying to do, it is just a bit hard to do in the current code organization. > I think the correct thing long-term is for phi elimination to > produce parallel copies, and for the coalescer to take advantage of > this. It would then be even easier to do this sort of a check. Yes, it would avoid having to go looking for the other copy. I wonder if there would still be value in handling copies not introduced by phi elimination. > When checking whether two seemingly overlapping live ranges actually > interfere, you could just check whether they are defined by the same > value at the same parallel copy. > > I have been working on this off and on with a branch, but I wanted > to wait until linear scan is gone (taking physical register > coalescing with it) before heavily modifying the coalescer on trunk. Cool. I will try to implement this one case since it looks like it has a really large impart in jsinterp.o. I will also upload a testcase of the strong phi failure. Do you have any good references on coalescing? Every text I found starts with "build in interference graph" as if that was a completely trivial task :-) > Cameron Cheers, Rafael From stoklund at 2pi.dk Tue Jun 28 19:24:24 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 29 Jun 2011 00:24:24 -0000 Subject: [llvm-commits] [llvm] r134047 - in /llvm/trunk/lib/CodeGen: RegAllocGreedy.cpp SplitKit.cpp SplitKit.h Message-ID: <20110629002424.9E0932A6C12C@llvm.org> Author: stoklund Date: Tue Jun 28 19:24:24 2011 New Revision: 134047 URL: http://llvm.org/viewvc/llvm-project?rev=134047&view=rev Log: Rewrite RAGreedy::splitAroundRegion, now with cool ASCII art. This function has to deal with a lot of special cases, and the old version got it wrong sometimes. In particular, it would sometimes leave multiple uses in the stack interval in a single block. That causes bad code with multiple reloads in the same basic block. The new version handles block entry and exit in a single pass. It first eliminates all the easy cases, and then goes on to create a local interval for the blocks with difficult interference. Previously, we would only create the local interval for completely isolated blocks. It can happen that the stack interval becomes completely empty because we could allocate a register in all edge bundles, and the new local intervals deal with the interference. The empty stack interval is harmless, but we need to remove a SplitKit assertion that checks for empty intervals. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp llvm/trunk/lib/CodeGen/SplitKit.cpp llvm/trunk/lib/CodeGen/SplitKit.h Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=134047&r1=134046&r2=134047&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Jun 28 19:24:24 2011 @@ -763,32 +763,46 @@ // Create the main cross-block interval. const unsigned MainIntv = SE->openIntv(); - // First add all defs that are live out of a block. + // First handle all the blocks with uses. ArrayRef UseBlocks = SA->getUseBlocks(); for (unsigned i = 0; i != UseBlocks.size(); ++i) { const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; - bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; - bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; + bool RegIn = BI.LiveIn && + LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; + bool RegOut = BI.LiveOut && + LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; // Create separate intervals for isolated blocks with multiple uses. - if (!RegIn && !RegOut && BI.FirstUse != BI.LastUse) { + // + // |---o---o---| Enter and leave on the stack. + // ____-----____ Create local interval for uses. + // + // | o---o---| Defined in block, leave on stack. + // -----____ Create local interval for uses. + // + // |---o---x | Enter on stack, killed in block. + // ____----- Create local interval for uses. + // + if (!RegIn && !RegOut) { DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n"); - SE->splitSingleBlock(BI); - SE->selectIntv(MainIntv); + if (!BI.isOneInstr()) { + SE->splitSingleBlock(BI); + SE->selectIntv(MainIntv); + } continue; } - // Should the register be live out? - if (!BI.LiveOut || !RegOut) - continue; - SlotIndex Start, Stop; tie(Start, Stop) = Indexes->getMBBRange(BI.MBB); Intf.moveToBlock(BI.MBB->getNumber()); - DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#" - << Bundles->getBundle(BI.MBB->getNumber(), 1) + DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0) + << (RegIn ? " => " : " -- ") + << "BB#" << BI.MBB->getNumber() + << (RegOut ? " => " : " -- ") + << " EB#" << Bundles->getBundle(BI.MBB->getNumber(), 1) << " [" << Start << ';' << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop + << ") uses [" << BI.FirstUse << ';' << BI.LastUse << ") intf [" << Intf.first() << ';' << Intf.last() << ')'); // The interference interval should either be invalid or overlap MBB. @@ -797,150 +811,266 @@ assert((!Intf.hasInterference() || Intf.last() > Start) && "Bad interference"); - // Check interference leaving the block. + // We are now ready to decide where to split in the current block. There + // are many variables guiding the decision: + // + // - RegIn / RegOut: The global splitting algorithm's decisions for our + // ingoing and outgoing bundles. + // + // - BI.BlockIn / BI.BlockOut: Is the live range live-in and/or live-out + // from this block. + // + // - Intf.hasInterference(): Is there interference in this block. + // + // - Intf.first() / Inft.last(): The range of interference. + // + // The live range should be split such that MainIntv is live-in when RegIn + // is set, and live-out when RegOut is set. MainIntv should never overlap + // the interference, and the stack interval should never have more than one + // use per block. + + // No splits can be inserted after LastSplitPoint, overlap instead. + SlotIndex LastSplitPoint = Stop; + if (BI.LiveOut) + LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); + + // At this point, we know that either RegIn or RegOut is set. We dealt with + // the all-stack case above. + + // Blocks without interference are relatively easy. if (!Intf.hasInterference()) { - // Block is interference-free. - DEBUG(dbgs() << ", no interference"); - if (!BI.LiveThrough) { - DEBUG(dbgs() << ", not live-through.\n"); - SE->useIntv(SE->enterIntvBefore(BI.FirstUse), Stop); - continue; - } - if (!RegIn) { - // Block is live-through, but entry bundle is on the stack. - // Reload just before the first use. - DEBUG(dbgs() << ", not live-in, enter before first use.\n"); - SE->useIntv(SE->enterIntvBefore(BI.FirstUse), Stop); - continue; - } - DEBUG(dbgs() << ", live-through.\n"); - continue; - } + DEBUG(dbgs() << ", no interference.\n"); + SE->selectIntv(MainIntv); + // The easiest case has MainIntv live through. + // + // |---o---o---| Live-in, live-out. + // ============= Use MainIntv everywhere. + // + SlotIndex From = Start, To = Stop; + + // Block entry. Reload before the first use if MainIntv is not live-in. + // + // |---o-- Enter on stack. + // ____=== Reload before first use. + // + // | o-- Defined in block. + // === Use MainIntv from def. + // + if (!RegIn) + From = SE->enterIntvBefore(BI.FirstUse); - // Block has interference. - DEBUG(dbgs() << ", interference to " << Intf.last()); + // Block exit. Handle cases where MainIntv is not live-out. + if (!BI.LiveOut) + // + // --x | Killed in block. + // === Use MainIntv up to kill. + // + To = SE->leaveIntvAfter(BI.LastUse); + else if (!RegOut) { + // + // --o---| Live-out on stack. + // ===____ Use MainIntv up to last use, switch to stack. + // + // -----o| Live-out on stack, last use after last split point. + // ====== Extend MainIntv to last use, overlapping. + // \____ Copy to stack interval before last split point. + // + if (BI.LastUse < LastSplitPoint) + To = SE->leaveIntvAfter(BI.LastUse); + else { + // The last use is after the last split point, it is probably an + // indirect branch. + To = SE->leaveIntvBefore(LastSplitPoint); + // Run a double interval from the split to the last use. This makes + // it possible to spill the complement without affecting the indirect + // branch. + SE->overlapIntv(To, BI.LastUse); + } + } - if (!BI.LiveThrough && Intf.last() <= BI.FirstUse) { - // The interference doesn't reach the outgoing segment. - DEBUG(dbgs() << " doesn't affect def from " << BI.FirstUse << '\n'); - SE->useIntv(BI.FirstUse, Stop); + // Paint in MainIntv liveness for this block. + SE->useIntv(From, To); continue; } - SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); - if (Intf.last().getBoundaryIndex() < BI.LastUse) { - // There are interference-free uses at the end of the block. - // Find the first use that can get the live-out register. - SmallVectorImpl::const_iterator UI = - std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), - Intf.last().getBoundaryIndex()); - assert(UI != SA->UseSlots.end() && "Couldn't find last use"); - SlotIndex Use = *UI; - assert(Use <= BI.LastUse && "Couldn't find last use"); - // Only attempt a split befroe the last split point. - if (Use.getBaseIndex() <= LastSplitPoint) { - DEBUG(dbgs() << ", free use at " << Use << ".\n"); - SlotIndex SegStart = SE->enterIntvBefore(Use); - assert(SegStart >= Intf.last() && "Couldn't avoid interference"); - assert(SegStart < LastSplitPoint && "Impossible split point"); - SE->useIntv(SegStart, Stop); - continue; - } - } + // We are now looking at a block with interference, and we know that either + // RegIn or RegOut is set. + assert(Intf.hasInterference() && (RegIn || RegOut) && "Bad invariant"); - // Interference is after the last use. - DEBUG(dbgs() << " after last use.\n"); - SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB); - assert(SegStart >= Intf.last() && "Couldn't avoid interference"); - } + // If the live range is not live through the block, it is possible that the + // interference doesn't even overlap. Deal with those cases first. Since + // no copy instructions are required, we can tolerate interference starting + // or ending at the same instruction that kills or defines our live range. - // Now all defs leading to live bundles are handled, do everything else. - for (unsigned i = 0; i != UseBlocks.size(); ++i) { - const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; - bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; - bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; + // Live-in, killed before interference. + // + // ~~~ Interference after kill. + // |---o---x | Killed in block. + // ========= Use MainIntv everywhere. + // + if (RegIn && !BI.LiveOut && BI.LastUse <= Intf.first()) { + DEBUG(dbgs() << ", live-in, killed before interference.\n"); + SE->selectIntv(MainIntv); + SlotIndex To = SE->leaveIntvAfter(BI.LastUse); + SE->useIntv(Start, To); + continue; + } - // Is the register live-in? - if (!BI.LiveIn || !RegIn) + // Live-out, defined after interference. + // + // ~~~ Interference before def. + // | o---o---| Defined in block. + // ========= Use MainIntv everywhere. + // + if (RegOut && !BI.LiveIn && BI.FirstUse >= Intf.last()) { + DEBUG(dbgs() << ", live-out, defined after interference.\n"); + SE->selectIntv(MainIntv); + SlotIndex From = SE->enterIntvBefore(BI.FirstUse); + SE->useIntv(From, Stop); continue; + } - // We have an incoming register. Check for interference. - SlotIndex Start, Stop; - tie(Start, Stop) = Indexes->getMBBRange(BI.MBB); - Intf.moveToBlock(BI.MBB->getNumber()); - DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0) - << " -> BB#" << BI.MBB->getNumber() << " [" << Start << ';' - << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop - << ')'); + // The interference is now known to overlap the live range, but it may + // still be easy to avoid if all the interference is on one side of the + // uses, and we enter or leave on the stack. - // Check interference entering the block. - if (!Intf.hasInterference()) { - // Block is interference-free. - DEBUG(dbgs() << ", no interference"); - if (!BI.LiveThrough) { - DEBUG(dbgs() << ", killed in block.\n"); - SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse)); - continue; - } - if (!RegOut) { - SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); - // Block is live-through, but exit bundle is on the stack. - // Spill immediately after the last use. - if (BI.LastUse < LastSplitPoint) { - DEBUG(dbgs() << ", uses, stack-out.\n"); - SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse)); - continue; - } - // The last use is after the last split point, it is probably an - // indirect jump. - DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point " - << LastSplitPoint << ", stack-out.\n"); - SlotIndex SegEnd = SE->leaveIntvBefore(LastSplitPoint); - SE->useIntv(Start, SegEnd); - // Run a double interval from the split to the last use. - // This makes it possible to spill the complement without affecting the - // indirect branch. - SE->overlapIntv(SegEnd, BI.LastUse); - continue; + // Live-out on stack, interference after last use. + // + // ~~~ Interference after last use. + // |---o---o---| Live-out on stack. + // =========____ Leave MainIntv after last use. + // + // ~ Interference after last use. + // |---o---o--o| Live-out on stack, late last use. + // =========____ Copy to stack after LSP, overlap MainIntv. + // + if (!RegOut && Intf.first() > BI.LastUse.getBoundaryIndex()) { + assert(RegIn && "Stack-in, stack-out should already be handled"); + if (BI.LastUse < LastSplitPoint) { + DEBUG(dbgs() << ", live-in, stack-out, interference after last use.\n"); + SE->selectIntv(MainIntv); + SlotIndex To = SE->leaveIntvAfter(BI.LastUse); + assert(To <= Intf.first() && "Expected to avoid interference"); + SE->useIntv(Start, To); + } else { + DEBUG(dbgs() << ", live-in, stack-out, avoid last split point\n"); + SE->selectIntv(MainIntv); + SlotIndex To = SE->leaveIntvBefore(LastSplitPoint); + assert(To <= Intf.first() && "Expected to avoid interference"); + SE->overlapIntv(To, BI.LastUse); + SE->useIntv(Start, To); } - // Register is live-through. - DEBUG(dbgs() << ", uses, live-through.\n"); - SE->useIntv(Start, Stop); continue; } - // Block has interference. - DEBUG(dbgs() << ", interference from " << Intf.first()); - - if (!BI.LiveThrough && Intf.first() >= BI.LastUse) { - // The interference doesn't reach the outgoing segment. - DEBUG(dbgs() << " doesn't affect kill at " << BI.LastUse << '\n'); - SE->useIntv(Start, BI.LastUse); + // Live-in on stack, interference before first use. + // + // ~~~ Interference before first use. + // |---o---o---| Live-in on stack. + // ____========= Enter MainIntv before first use. + // + if (!RegIn && Intf.last() < BI.FirstUse.getBaseIndex()) { + assert(RegOut && "Stack-in, stack-out should already be handled"); + DEBUG(dbgs() << ", stack-in, interference before first use.\n"); + SE->selectIntv(MainIntv); + SlotIndex From = SE->enterIntvBefore(BI.FirstUse); + assert(From >= Intf.last() && "Expected to avoid interference"); + SE->useIntv(From, Stop); continue; } - if (Intf.first().getBaseIndex() > BI.FirstUse) { - // There are interference-free uses at the beginning of the block. - // Find the last use that can get the register. - SmallVectorImpl::const_iterator UI = - std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), - Intf.first().getBaseIndex()); - assert(UI != SA->UseSlots.begin() && "Couldn't find first use"); - SlotIndex Use = (--UI)->getBoundaryIndex(); - DEBUG(dbgs() << ", free use at " << *UI << ".\n"); - SlotIndex SegEnd = SE->leaveIntvAfter(Use); - assert(SegEnd <= Intf.first() && "Couldn't avoid interference"); - SE->useIntv(Start, SegEnd); - continue; + // The interference is overlapping somewhere we wanted to use MainIntv. That + // means we need to create a local interval that can be allocated a + // different register. + DEBUG(dbgs() << ", creating local interval.\n"); + unsigned LocalIntv = SE->openIntv(); + + // We may be creating copies directly between MainIntv and LocalIntv, + // bypassing the stack interval. When we do that, we should never use the + // leaveIntv* methods as they define values in the stack interval. By + // starting from the end of the block and working our way backwards, we can + // get by with only enterIntv* methods. + // + // When selecting split points, we generally try to maximize the stack + // interval as long at it contains no uses, maximize the main interval as + // long as it doesn't overlap interference, and minimize the local interval + // that we don't know how to allocate yet. + + // Handle the block exit, set Pos to the first handled slot. + SlotIndex Pos = BI.LastUse; + if (RegOut) { + assert(Intf.last() < LastSplitPoint && "Cannot be live-out in register"); + // Create a snippet of MainIntv that is live-out. + // + // ~~~ Interference overlapping uses. + // --o---| Live-out in MainIntv. + // ----=== Switch from LocalIntv to MainIntv after interference. + // + SE->selectIntv(MainIntv); + Pos = SE->enterIntvAfter(Intf.last()); + assert(Pos >= Intf.last() && "Expected to avoid interference"); + SE->useIntv(Pos, Stop); + SE->selectIntv(LocalIntv); + } else if (BI.LiveOut) { + if (BI.LastUse < LastSplitPoint) { + // Live-out on the stack. + // + // ~~~ Interference overlapping uses. + // --o---| Live-out on stack. + // ---____ Switch from LocalIntv to stack after last use. + // + Pos = SE->leaveIntvAfter(BI.LastUse); + } else { + // Live-out on the stack, last use after last split point. + // + // ~~~ Interference overlapping uses. + // --o--o| Live-out on stack, late use. + // ------ Copy to stack before LSP, overlap LocalIntv. + // \__ + // + Pos = SE->leaveIntvBefore(LastSplitPoint); + // We need to overlap LocalIntv so it can reach LastUse. + SE->overlapIntv(Pos, BI.LastUse); + } } - // Interference is before the first use. - DEBUG(dbgs() << " before first use.\n"); - SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB); - assert(SegEnd <= Intf.first() && "Couldn't avoid interference"); + // When not live-out, leave Pos at LastUse. We have handled everything from + // Pos to Stop. Find the starting point for LocalIntv. + assert(SE->currentIntv() == LocalIntv && "Expecting local interval"); + + if (RegIn) { + assert(Start < Intf.first() && "Cannot be live-in with interference"); + // Live-in in MainIntv, only use LocalIntv for interference. + // + // ~~~ Interference overlapping uses. + // |---o-- Live-in in MainIntv. + // ====--- Switch to LocalIntv before interference. + // + SlotIndex Switch = SE->enterIntvBefore(Intf.first()); + assert(Switch <= Intf.first() && "Expected to avoid interference"); + SE->useIntv(Switch, Pos); + SE->selectIntv(MainIntv); + SE->useIntv(Start, Switch); + } else { + // Live-in on stack, enter LocalIntv before first use. + // + // ~~~ Interference overlapping uses. + // |---o-- Live-in in MainIntv. + // ____--- Reload to LocalIntv before interference. + // + // Defined in block. + // + // ~~~ Interference overlapping uses. + // | o-- Defined in block. + // --- Begin LocalIntv at first use. + // + SlotIndex Switch = SE->enterIntvBefore(BI.FirstUse); + SE->useIntv(Switch, Pos); + } } // Handle live-through blocks. + SE->selectIntv(MainIntv); for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) { unsigned Number = Cand.ActiveBlocks[i]; bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)]; Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=134047&r1=134046&r2=134047&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Jun 28 19:24:24 2011 @@ -636,6 +636,7 @@ void SplitEditor::selectIntv(unsigned Idx) { assert(Idx != 0 && "Cannot select the complement interval"); assert(Idx < Edit->size() && "Can only select previously opened interval"); + DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n'); OpenIdx = Idx; } @@ -656,6 +657,24 @@ return VNI->def; } +SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) { + assert(OpenIdx && "openIntv not called before enterIntvAfter"); + DEBUG(dbgs() << " enterIntvAfter " << Idx); + Idx = Idx.getBoundaryIndex(); + VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx); + if (!ParentVNI) { + DEBUG(dbgs() << ": not live\n"); + return Idx; + } + DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); + MachineInstr *MI = LIS.getInstructionFromIndex(Idx); + assert(MI && "enterIntvAfter called with invalid index"); + + VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), + llvm::next(MachineBasicBlock::iterator(MI))); + return VNI->def; +} + SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) { assert(OpenIdx && "openIntv not called before enterIntvAtEnd"); SlotIndex End = LIS.getMBBEndIdx(&MBB); @@ -1007,12 +1026,6 @@ markComplexMapped(i, ParentVNI); } -#ifndef NDEBUG - // Every new interval must have a def by now, otherwise the split is bogus. - for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I) - assert((*I)->hasAtLeastOneValue() && "Split interval has no value"); -#endif - // Transfer the simply mapped values, check if any are skipped. bool Skipped = transferValues(); if (Skipped) Modified: llvm/trunk/lib/CodeGen/SplitKit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=134047&r1=134046&r2=134047&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.h (original) +++ llvm/trunk/lib/CodeGen/SplitKit.h Tue Jun 28 19:24:24 2011 @@ -81,6 +81,12 @@ bool LiveThrough; ///< Live in whole block (Templ 5. above). bool LiveIn; ///< Current reg is live in. bool LiveOut; ///< Current reg is live out. + + /// isOneInstr - Returns true when this BlockInfo describes a single + /// instruction. + bool isOneInstr() const { + return SlotIndex::isSameInstr(FirstUse, LastUse); + } }; private: @@ -360,6 +366,10 @@ /// Return the beginning of the new live range. SlotIndex enterIntvBefore(SlotIndex Idx); + /// enterIntvAfter - Enter the open interval after the instruction at Idx. + /// Return the beginning of the new live range. + SlotIndex enterIntvAfter(SlotIndex Idx); + /// enterIntvAtEnd - Enter the open interval at the end of MBB. /// Use the open interval from he inserted copy to the MBB end. /// Return the beginning of the new live range. From evan.cheng at apple.com Tue Jun 28 19:35:31 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 29 Jun 2011 00:35:31 -0000 Subject: [llvm-commits] [llvm] r134048 - /llvm/trunk/include/llvm/Target/SubtargetFeature.h Message-ID: <20110629003531.B54862A6C12C@llvm.org> Author: evancheng Date: Tue Jun 28 19:35:31 2011 New Revision: 134048 URL: http://llvm.org/viewvc/llvm-project?rev=134048&view=rev Log: Trim include Modified: llvm/trunk/include/llvm/Target/SubtargetFeature.h Modified: llvm/trunk/include/llvm/Target/SubtargetFeature.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/SubtargetFeature.h?rev=134048&r1=134047&r2=134048&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/SubtargetFeature.h (original) +++ llvm/trunk/include/llvm/Target/SubtargetFeature.h Tue Jun 28 19:35:31 2011 @@ -20,7 +20,6 @@ #include #include -#include #include "llvm/ADT/Triple.h" #include "llvm/Support/DataTypes.h" From evan.cheng at apple.com Tue Jun 28 20:14:13 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 29 Jun 2011 01:14:13 -0000 Subject: [llvm-commits] [llvm] r134049 - in /llvm/trunk: include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/ExecutionEngine/ lib/MC/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Target/Mips/ lib/Target/PowerPC/ tools/llc/ tools/llvm-mc/ tools/lto/ utils/TableGen/ Message-ID: <20110629011413.5A0802A6C12C@llvm.org> Author: evancheng Date: Tue Jun 28 20:14:12 2011 New Revision: 134049 URL: http://llvm.org/viewvc/llvm-project?rev=134049&view=rev Log: Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC. Added: llvm/trunk/include/llvm/MC/MCInstrItineraries.h - copied, changed from r134046, llvm/trunk/include/llvm/Target/TargetInstrItineraries.h llvm/trunk/include/llvm/MC/SubtargetFeature.h - copied, changed from r134048, llvm/trunk/include/llvm/Target/SubtargetFeature.h llvm/trunk/lib/MC/SubtargetFeature.cpp - copied, changed from r134046, llvm/trunk/lib/Target/SubtargetFeature.cpp Removed: llvm/trunk/include/llvm/Target/SubtargetFeature.h llvm/trunk/include/llvm/Target/TargetInstrItineraries.h llvm/trunk/lib/Target/SubtargetFeature.cpp Modified: llvm/trunk/include/llvm/Target/TargetMachine.h llvm/trunk/lib/CodeGen/IfConversion.cpp llvm/trunk/lib/CodeGen/MachineLICM.cpp llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h llvm/trunk/lib/Target/Mips/MipsSubtarget.h llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h llvm/trunk/lib/Target/TargetInstrInfo.cpp llvm/trunk/tools/llc/llc.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/lto/LTOCodeGenerator.cpp llvm/trunk/tools/lto/LTOModule.cpp llvm/trunk/utils/TableGen/SubtargetEmitter.cpp llvm/trunk/utils/TableGen/SubtargetEmitter.h Copied: llvm/trunk/include/llvm/MC/MCInstrItineraries.h (from r134046, llvm/trunk/include/llvm/Target/TargetInstrItineraries.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrItineraries.h?p2=llvm/trunk/include/llvm/MC/MCInstrItineraries.h&p1=llvm/trunk/include/llvm/Target/TargetInstrItineraries.h&r1=134046&r2=134049&rev=134049&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrItineraries.h (original) +++ llvm/trunk/include/llvm/MC/MCInstrItineraries.h Tue Jun 28 20:14:12 2011 @@ -1,4 +1,4 @@ -//===-- llvm/Target/TargetInstrItineraries.h - Scheduling -------*- C++ -*-===// +//===-- llvm/MC/MCInstrItineraries.h - Scheduling ---------------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -13,8 +13,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_TARGETINSTRITINERARIES_H -#define LLVM_TARGET_TARGETINSTRITINERARIES_H +#ifndef LLVM_MC_MCINSTRITINERARIES_H +#define LLVM_MC_MCINSTRITINERARIES_H #include Copied: llvm/trunk/include/llvm/MC/SubtargetFeature.h (from r134048, llvm/trunk/include/llvm/Target/SubtargetFeature.h) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/SubtargetFeature.h?p2=llvm/trunk/include/llvm/MC/SubtargetFeature.h&p1=llvm/trunk/include/llvm/Target/SubtargetFeature.h&r1=134048&r2=134049&rev=134049&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/SubtargetFeature.h (original) +++ llvm/trunk/include/llvm/MC/SubtargetFeature.h Tue Jun 28 20:14:12 2011 @@ -1,4 +1,4 @@ -//===-- llvm/Target/SubtargetFeature.h - CPU characteristics ----*- C++ -*-===// +//===-- llvm/MC/SubtargetFeature.h - CPU characteristics --------*- C++ -*-===// // // The LLVM Compiler Infrastructure // @@ -15,8 +15,8 @@ // //===----------------------------------------------------------------------===// -#ifndef LLVM_TARGET_SUBTARGETFEATURE_H -#define LLVM_TARGET_SUBTARGETFEATURE_H +#ifndef LLVM_MC_SUBTARGETFEATURE_H +#define LLVM_MC_SUBTARGETFEATURE_H #include #include Removed: llvm/trunk/include/llvm/Target/SubtargetFeature.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/SubtargetFeature.h?rev=134048&view=auto ============================================================================== --- llvm/trunk/include/llvm/Target/SubtargetFeature.h (original) +++ llvm/trunk/include/llvm/Target/SubtargetFeature.h (removed) @@ -1,118 +0,0 @@ -//===-- llvm/Target/SubtargetFeature.h - CPU characteristics ----*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file defines and manages user or tool specified CPU characteristics. -// The intent is to be able to package specific features that should or should -// not be used on a specific target processor. A tool, such as llc, could, as -// as example, gather chip info from the command line, a long with features -// that should be used on that chip. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TARGET_SUBTARGETFEATURE_H -#define LLVM_TARGET_SUBTARGETFEATURE_H - -#include -#include -#include "llvm/ADT/Triple.h" -#include "llvm/Support/DataTypes.h" - -namespace llvm { - class raw_ostream; - -//===----------------------------------------------------------------------===// -/// -/// SubtargetFeatureKV - Used to provide key value pairs for feature and -/// CPU bit flags. -// -struct SubtargetFeatureKV { - const char *Key; // K-V key string - const char *Desc; // Help descriptor - uint64_t Value; // K-V integer value - uint64_t Implies; // K-V bit mask - - // Compare routine for std binary search - bool operator<(const SubtargetFeatureKV &S) const { - return strcmp(Key, S.Key) < 0; - } -}; - -//===----------------------------------------------------------------------===// -/// -/// SubtargetInfoKV - Used to provide key value pairs for CPU and arbitrary -/// pointers. -// -struct SubtargetInfoKV { - const char *Key; // K-V key string - void *Value; // K-V pointer value - - // Compare routine for std binary search - bool operator<(const SubtargetInfoKV &S) const { - return strcmp(Key, S.Key) < 0; - } -}; - -//===----------------------------------------------------------------------===// -/// -/// SubtargetFeatures - Manages the enabling and disabling of subtarget -/// specific features. Features are encoded as a string of the form -/// "cpu,+attr1,+attr2,-attr3,...,+attrN" -/// A comma separates each feature from the next (all lowercase.) -/// The first feature is always the CPU subtype (eg. pentiumm). If the CPU -/// value is "generic" then the CPU subtype should be generic for the target. -/// Each of the remaining features is prefixed with + or - indicating whether -/// that feature should be enabled or disabled contrary to the cpu -/// specification. -/// - -class SubtargetFeatures { - std::vector Features; // Subtarget features as a vector -public: - explicit SubtargetFeatures(const std::string &Initial = std::string()); - - /// Features string accessors. - std::string getString() const; - void setString(const std::string &Initial); - - /// Set the CPU string. Replaces previous setting. Setting to "" clears CPU. - void setCPU(const std::string &String); - - /// Setting CPU string only if no string is set. - void setCPUIfNone(const std::string &String); - - /// Returns current CPU string. - const std::string & getCPU() const; - - /// Adding Features. - void AddFeature(const std::string &String, bool IsEnabled = true); - - /// Get feature bits. - uint64_t getBits(const SubtargetFeatureKV *CPUTable, - size_t CPUTableSize, - const SubtargetFeatureKV *FeatureTable, - size_t FeatureTableSize); - - /// Get info pointer - void *getInfo(const SubtargetInfoKV *Table, size_t TableSize); - - /// Print feature string. - void print(raw_ostream &OS) const; - - // Dump feature info. - void dump() const; - - /// Retrieve a formatted string of the default features for the specified - /// target triple. - void getDefaultSubtargetFeatures(const std::string &CPU, - const Triple& Triple); -}; - -} // End namespace llvm - -#endif Removed: llvm/trunk/include/llvm/Target/TargetInstrItineraries.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrItineraries.h?rev=134048&view=auto ============================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrItineraries.h (original) +++ llvm/trunk/include/llvm/Target/TargetInstrItineraries.h (removed) @@ -1,253 +0,0 @@ -//===-- llvm/Target/TargetInstrItineraries.h - Scheduling -------*- C++ -*-===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file describes the structures used for instruction -// itineraries, stages, and operand reads/writes. This is used by -// schedulers to determine instruction stages and latencies. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_TARGET_TARGETINSTRITINERARIES_H -#define LLVM_TARGET_TARGETINSTRITINERARIES_H - -#include - -namespace llvm { - -//===----------------------------------------------------------------------===// -/// Instruction stage - These values represent a non-pipelined step in -/// the execution of an instruction. Cycles represents the number of -/// discrete time slots needed to complete the stage. Units represent -/// the choice of functional units that can be used to complete the -/// stage. Eg. IntUnit1, IntUnit2. NextCycles indicates how many -/// cycles should elapse from the start of this stage to the start of -/// the next stage in the itinerary. A value of -1 indicates that the -/// next stage should start immediately after the current one. -/// For example: -/// -/// { 1, x, -1 } -/// indicates that the stage occupies FU x for 1 cycle and that -/// the next stage starts immediately after this one. -/// -/// { 2, x|y, 1 } -/// indicates that the stage occupies either FU x or FU y for 2 -/// consecuative cycles and that the next stage starts one cycle -/// after this stage starts. That is, the stage requirements -/// overlap in time. -/// -/// { 1, x, 0 } -/// indicates that the stage occupies FU x for 1 cycle and that -/// the next stage starts in this same cycle. This can be used to -/// indicate that the instruction requires multiple stages at the -/// same time. -/// -/// FU reservation can be of two different kinds: -/// - FUs which instruction actually requires -/// - FUs which instruction just reserves. Reserved unit is not available for -/// execution of other instruction. However, several instructions can reserve -/// the same unit several times. -/// Such two types of units reservation is used to model instruction domain -/// change stalls, FUs using the same resource (e.g. same register file), etc. - -struct InstrStage { - enum ReservationKinds { - Required = 0, - Reserved = 1 - }; - - unsigned Cycles_; ///< Length of stage in machine cycles - unsigned Units_; ///< Choice of functional units - int NextCycles_; ///< Number of machine cycles to next stage - ReservationKinds Kind_; ///< Kind of the FU reservation - - /// getCycles - returns the number of cycles the stage is occupied - unsigned getCycles() const { - return Cycles_; - } - - /// getUnits - returns the choice of FUs - unsigned getUnits() const { - return Units_; - } - - ReservationKinds getReservationKind() const { - return Kind_; - } - - /// getNextCycles - returns the number of cycles from the start of - /// this stage to the start of the next stage in the itinerary - unsigned getNextCycles() const { - return (NextCycles_ >= 0) ? (unsigned)NextCycles_ : Cycles_; - } -}; - - -//===----------------------------------------------------------------------===// -/// Instruction itinerary - An itinerary represents the scheduling -/// information for an instruction. This includes a set of stages -/// occupies by the instruction, and the pipeline cycle in which -/// operands are read and written. -/// -struct InstrItinerary { - unsigned NumMicroOps; ///< # of micro-ops, 0 means it's variable - unsigned FirstStage; ///< Index of first stage in itinerary - unsigned LastStage; ///< Index of last + 1 stage in itinerary - unsigned FirstOperandCycle; ///< Index of first operand rd/wr - unsigned LastOperandCycle; ///< Index of last + 1 operand rd/wr -}; - - -//===----------------------------------------------------------------------===// -/// Instruction itinerary Data - Itinerary data supplied by a subtarget to be -/// used by a target. -/// -class InstrItineraryData { -public: - const InstrStage *Stages; ///< Array of stages selected - const unsigned *OperandCycles; ///< Array of operand cycles selected - const unsigned *Forwardings; ///< Array of pipeline forwarding pathes - const InstrItinerary *Itineraries; ///< Array of itineraries selected - unsigned IssueWidth; ///< Max issue per cycle. 0=Unknown. - - /// Ctors. - /// - InstrItineraryData() : Stages(0), OperandCycles(0), Forwardings(0), - Itineraries(0), IssueWidth(0) {} - - InstrItineraryData(const InstrStage *S, const unsigned *OS, - const unsigned *F, const InstrItinerary *I) - : Stages(S), OperandCycles(OS), Forwardings(F), Itineraries(I), - IssueWidth(0) {} - - /// isEmpty - Returns true if there are no itineraries. - /// - bool isEmpty() const { return Itineraries == 0; } - - /// isEndMarker - Returns true if the index is for the end marker - /// itinerary. - /// - bool isEndMarker(unsigned ItinClassIndx) const { - return ((Itineraries[ItinClassIndx].FirstStage == ~0U) && - (Itineraries[ItinClassIndx].LastStage == ~0U)); - } - - /// beginStage - Return the first stage of the itinerary. - /// - const InstrStage *beginStage(unsigned ItinClassIndx) const { - unsigned StageIdx = Itineraries[ItinClassIndx].FirstStage; - return Stages + StageIdx; - } - - /// endStage - Return the last+1 stage of the itinerary. - /// - const InstrStage *endStage(unsigned ItinClassIndx) const { - unsigned StageIdx = Itineraries[ItinClassIndx].LastStage; - return Stages + StageIdx; - } - - /// getStageLatency - Return the total stage latency of the given - /// class. The latency is the maximum completion time for any stage - /// in the itinerary. - /// - unsigned getStageLatency(unsigned ItinClassIndx) const { - // If the target doesn't provide itinerary information, use a simple - // non-zero default value for all instructions. Some target's provide a - // dummy (Generic) itinerary which should be handled as if it's itinerary is - // empty. We identify this by looking for a reference to stage zero (invalid - // stage). This is different from beginStage == endState != 0, which could - // be used for zero-latency pseudo ops. - if (isEmpty() || Itineraries[ItinClassIndx].FirstStage == 0) - return 1; - - // Calculate the maximum completion time for any stage. - unsigned Latency = 0, StartCycle = 0; - for (const InstrStage *IS = beginStage(ItinClassIndx), - *E = endStage(ItinClassIndx); IS != E; ++IS) { - Latency = std::max(Latency, StartCycle + IS->getCycles()); - StartCycle += IS->getNextCycles(); - } - - return Latency; - } - - /// getOperandCycle - Return the cycle for the given class and - /// operand. Return -1 if no cycle is specified for the operand. - /// - int getOperandCycle(unsigned ItinClassIndx, unsigned OperandIdx) const { - if (isEmpty()) - return -1; - - unsigned FirstIdx = Itineraries[ItinClassIndx].FirstOperandCycle; - unsigned LastIdx = Itineraries[ItinClassIndx].LastOperandCycle; - if ((FirstIdx + OperandIdx) >= LastIdx) - return -1; - - return (int)OperandCycles[FirstIdx + OperandIdx]; - } - - /// hasPipelineForwarding - Return true if there is a pipeline forwarding - /// between instructions of itinerary classes DefClass and UseClasses so that - /// value produced by an instruction of itinerary class DefClass, operand - /// index DefIdx can be bypassed when it's read by an instruction of - /// itinerary class UseClass, operand index UseIdx. - bool hasPipelineForwarding(unsigned DefClass, unsigned DefIdx, - unsigned UseClass, unsigned UseIdx) const { - unsigned FirstDefIdx = Itineraries[DefClass].FirstOperandCycle; - unsigned LastDefIdx = Itineraries[DefClass].LastOperandCycle; - if ((FirstDefIdx + DefIdx) >= LastDefIdx) - return false; - if (Forwardings[FirstDefIdx + DefIdx] == 0) - return false; - - unsigned FirstUseIdx = Itineraries[UseClass].FirstOperandCycle; - unsigned LastUseIdx = Itineraries[UseClass].LastOperandCycle; - if ((FirstUseIdx + UseIdx) >= LastUseIdx) - return false; - - return Forwardings[FirstDefIdx + DefIdx] == - Forwardings[FirstUseIdx + UseIdx]; - } - - /// getOperandLatency - Compute and return the use operand latency of a given - /// itinerary class and operand index if the value is produced by an - /// instruction of the specified itinerary class and def operand index. - int getOperandLatency(unsigned DefClass, unsigned DefIdx, - unsigned UseClass, unsigned UseIdx) const { - if (isEmpty()) - return -1; - - int DefCycle = getOperandCycle(DefClass, DefIdx); - if (DefCycle == -1) - return -1; - - int UseCycle = getOperandCycle(UseClass, UseIdx); - if (UseCycle == -1) - return -1; - - UseCycle = DefCycle - UseCycle + 1; - if (UseCycle > 0 && - hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) - // FIXME: This assumes one cycle benefit for every pipeline forwarding. - --UseCycle; - return UseCycle; - } - - /// isMicroCoded - Return true if the instructions in the given class decode - /// to more than one micro-ops. - bool isMicroCoded(unsigned ItinClassIndx) const { - if (isEmpty()) - return false; - return Itineraries[ItinClassIndx].NumMicroOps != 1; - } -}; - - -} // End llvm namespace - -#endif Modified: llvm/trunk/include/llvm/Target/TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetMachine.h (original) +++ llvm/trunk/include/llvm/Target/TargetMachine.h Tue Jun 28 20:14:12 2011 @@ -14,29 +14,29 @@ #ifndef LLVM_TARGET_TARGETMACHINE_H #define LLVM_TARGET_TARGETMACHINE_H -#include "llvm/Target/TargetInstrItineraries.h" #include #include namespace llvm { -class Target; +class InstrItineraryData; +class JITCodeEmitter; class MCAsmInfo; +class MCContext; +class Pass; +class PassManager; +class PassManagerBase; +class Target; class TargetData; -class TargetSubtarget; +class TargetELFWriterInfo; +class TargetFrameLowering; class TargetInstrInfo; class TargetIntrinsicInfo; class TargetJITInfo; class TargetLowering; -class TargetSelectionDAGInfo; -class TargetFrameLowering; -class JITCodeEmitter; -class MCContext; class TargetRegisterInfo; -class PassManagerBase; -class PassManager; -class Pass; -class TargetELFWriterInfo; +class TargetSelectionDAGInfo; +class TargetSubtarget; class formatted_raw_ostream; class raw_ostream; Modified: llvm/trunk/lib/CodeGen/IfConversion.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/IfConversion.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp (original) +++ llvm/trunk/lib/CodeGen/IfConversion.cpp Tue Jun 28 20:14:12 2011 @@ -18,8 +18,8 @@ #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineLoopInfo.h" +#include "llvm/MC/MCInstrItineraries.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegisterInfo.h" Modified: llvm/trunk/lib/CodeGen/MachineLICM.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MachineLICM.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp (original) +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp Tue Jun 28 20:14:12 2011 @@ -28,10 +28,10 @@ #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/MC/MCInstrItineraries.h" #include "llvm/Target/TargetLowering.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/ADT/DenseMap.h" Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original) +++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Tue Jun 28 20:14:12 2011 @@ -21,6 +21,7 @@ #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/PseudoSourceValue.h" +#include "llvm/MC/MCInstrItineraries.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetRegisterInfo.h" Modified: llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp (original) +++ llvm/trunk/lib/CodeGen/ScoreboardHazardRecognizer.cpp Tue Jun 28 20:14:12 2011 @@ -16,11 +16,11 @@ #define DEBUG_TYPE ::llvm::ScoreboardHazardRecognizer::DebugType #include "llvm/CodeGen/ScoreboardHazardRecognizer.h" #include "llvm/CodeGen/ScheduleDAG.h" +#include "llvm/MC/MCInstrItineraries.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetInstrItineraries.h" using namespace llvm; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Tue Jun 28 20:14:12 2011 @@ -17,6 +17,7 @@ #include "ScheduleDAGSDNodes.h" #include "InstrEmitter.h" #include "llvm/CodeGen/SelectionDAG.h" +#include "llvm/MC/MCInstrItineraries.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetLowering.h" Modified: llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp Tue Jun 28 20:14:12 2011 @@ -16,10 +16,10 @@ #include "llvm/ExecutionEngine/ExecutionEngine.h" #include "llvm/Module.h" #include "llvm/ADT/Triple.h" +#include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Support/Host.h" -#include "llvm/Target/SubtargetFeature.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegistry.h" using namespace llvm; Copied: llvm/trunk/lib/MC/SubtargetFeature.cpp (from r134046, llvm/trunk/lib/Target/SubtargetFeature.cpp) URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/SubtargetFeature.cpp?p2=llvm/trunk/lib/MC/SubtargetFeature.cpp&p1=llvm/trunk/lib/Target/SubtargetFeature.cpp&r1=134046&r2=134049&rev=134049&view=diff ============================================================================== --- llvm/trunk/lib/Target/SubtargetFeature.cpp (original) +++ llvm/trunk/lib/MC/SubtargetFeature.cpp Tue Jun 28 20:14:12 2011 @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/Target/SubtargetFeature.h" +#include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" #include "llvm/ADT/StringExtras.h" Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Tue Jun 28 20:14:12 2011 @@ -14,9 +14,8 @@ #ifndef ARMSUBTARGET_H #define ARMSUBTARGET_H -#include "llvm/Target/TargetInstrItineraries.h" -#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetSubtarget.h" +#include "llvm/MC/MCInstrItineraries.h" #include "llvm/ADT/Triple.h" #include Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h Tue Jun 28 20:14:12 2011 @@ -14,9 +14,8 @@ #ifndef ALPHASUBTARGET_H #define ALPHASUBTARGET_H -#include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetSubtarget.h" - +#include "llvm/MC/MCInstrItineraries.h" #include namespace llvm { Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h Tue Jun 28 20:14:12 2011 @@ -14,9 +14,8 @@ #ifndef CELLSUBTARGET_H #define CELLSUBTARGET_H -#include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetSubtarget.h" - +#include "llvm/MC/MCInstrItineraries.h" #include namespace llvm { Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h Tue Jun 28 20:14:12 2011 @@ -15,8 +15,7 @@ #define MBLAZESUBTARGET_H #include "llvm/Target/TargetSubtarget.h" -#include "llvm/Target/TargetMachine.h" - +#include "llvm/MC/MCInstrItineraries.h" #include namespace llvm { Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Tue Jun 28 20:14:12 2011 @@ -15,8 +15,7 @@ #define MIPSSUBTARGET_H #include "llvm/Target/TargetSubtarget.h" -#include "llvm/Target/TargetMachine.h" - +#include "llvm/MC/MCInstrItineraries.h" #include namespace llvm { Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Tue Jun 28 20:14:12 2011 @@ -14,10 +14,9 @@ #ifndef POWERPCSUBTARGET_H #define POWERPCSUBTARGET_H -#include "llvm/ADT/Triple.h" -#include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetSubtarget.h" - +#include "llvm/MC/MCInstrItineraries.h" +#include "llvm/ADT/Triple.h" #include // GCC #defines PPC on Linux but we use it as our namespace name Removed: llvm/trunk/lib/Target/SubtargetFeature.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SubtargetFeature.cpp?rev=134048&view=auto ============================================================================== --- llvm/trunk/lib/Target/SubtargetFeature.cpp (original) +++ llvm/trunk/lib/Target/SubtargetFeature.cpp (removed) @@ -1,384 +0,0 @@ -//===- SubtargetFeature.cpp - CPU characteristics Implementation ----------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This file implements the SubtargetFeature interface. -// -//===----------------------------------------------------------------------===// - -#include "llvm/Target/SubtargetFeature.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" -#include "llvm/ADT/StringExtras.h" -#include -#include -#include -#include -using namespace llvm; - -//===----------------------------------------------------------------------===// -// Static Helper Functions -//===----------------------------------------------------------------------===// - -/// hasFlag - Determine if a feature has a flag; '+' or '-' -/// -static inline bool hasFlag(const std::string &Feature) { - assert(!Feature.empty() && "Empty string"); - // Get first character - char Ch = Feature[0]; - // Check if first character is '+' or '-' flag - return Ch == '+' || Ch =='-'; -} - -/// StripFlag - Return string stripped of flag. -/// -static inline std::string StripFlag(const std::string &Feature) { - return hasFlag(Feature) ? Feature.substr(1) : Feature; -} - -/// isEnabled - Return true if enable flag; '+'. -/// -static inline bool isEnabled(const std::string &Feature) { - assert(!Feature.empty() && "Empty string"); - // Get first character - char Ch = Feature[0]; - // Check if first character is '+' for enabled - return Ch == '+'; -} - -/// PrependFlag - Return a string with a prepended flag; '+' or '-'. -/// -static inline std::string PrependFlag(const std::string &Feature, - bool IsEnabled) { - assert(!Feature.empty() && "Empty string"); - if (hasFlag(Feature)) return Feature; - return std::string(IsEnabled ? "+" : "-") + Feature; -} - -/// Split - Splits a string of comma separated items in to a vector of strings. -/// -static void Split(std::vector &V, const std::string &S) { - // Start at beginning of string. - size_t Pos = 0; - while (true) { - // Find the next comma - size_t Comma = S.find(',', Pos); - // If no comma found then the rest of the string is used - if (Comma == std::string::npos) { - // Add string to vector - V.push_back(S.substr(Pos)); - break; - } - // Otherwise add substring to vector - V.push_back(S.substr(Pos, Comma - Pos)); - // Advance to next item - Pos = Comma + 1; - } -} - -/// Join a vector of strings to a string with a comma separating each element. -/// -static std::string Join(const std::vector &V) { - // Start with empty string. - std::string Result; - // If the vector is not empty - if (!V.empty()) { - // Start with the CPU feature - Result = V[0]; - // For each successive feature - for (size_t i = 1; i < V.size(); i++) { - // Add a comma - Result += ","; - // Add the feature - Result += V[i]; - } - } - // Return the features string - return Result; -} - -/// Adding features. -void SubtargetFeatures::AddFeature(const std::string &String, - bool IsEnabled) { - // Don't add empty features - if (!String.empty()) { - // Convert to lowercase, prepend flag and add to vector - Features.push_back(PrependFlag(LowercaseString(String), IsEnabled)); - } -} - -/// Find KV in array using binary search. -template const T *Find(const std::string &S, const T *A, size_t L) { - // Make the lower bound element we're looking for - T KV; - KV.Key = S.c_str(); - // Determine the end of the array - const T *Hi = A + L; - // Binary search the array - const T *F = std::lower_bound(A, Hi, KV); - // If not found then return NULL - if (F == Hi || std::string(F->Key) != S) return NULL; - // Return the found array item - return F; -} - -/// getLongestEntryLength - Return the length of the longest entry in the table. -/// -static size_t getLongestEntryLength(const SubtargetFeatureKV *Table, - size_t Size) { - size_t MaxLen = 0; - for (size_t i = 0; i < Size; i++) - MaxLen = std::max(MaxLen, std::strlen(Table[i].Key)); - return MaxLen; -} - -/// Display help for feature choices. -/// -static void Help(const SubtargetFeatureKV *CPUTable, size_t CPUTableSize, - const SubtargetFeatureKV *FeatTable, size_t FeatTableSize) { - // Determine the length of the longest CPU and Feature entries. - unsigned MaxCPULen = getLongestEntryLength(CPUTable, CPUTableSize); - unsigned MaxFeatLen = getLongestEntryLength(FeatTable, FeatTableSize); - - // Print the CPU table. - errs() << "Available CPUs for this target:\n\n"; - for (size_t i = 0; i != CPUTableSize; i++) - errs() << " " << CPUTable[i].Key - << std::string(MaxCPULen - std::strlen(CPUTable[i].Key), ' ') - << " - " << CPUTable[i].Desc << ".\n"; - errs() << "\n"; - - // Print the Feature table. - errs() << "Available features for this target:\n\n"; - for (size_t i = 0; i != FeatTableSize; i++) - errs() << " " << FeatTable[i].Key - << std::string(MaxFeatLen - std::strlen(FeatTable[i].Key), ' ') - << " - " << FeatTable[i].Desc << ".\n"; - errs() << "\n"; - - errs() << "Use +feature to enable a feature, or -feature to disable it.\n" - << "For example, llc -mcpu=mycpu -mattr=+feature1,-feature2\n"; - std::exit(1); -} - -//===----------------------------------------------------------------------===// -// SubtargetFeatures Implementation -//===----------------------------------------------------------------------===// - -SubtargetFeatures::SubtargetFeatures(const std::string &Initial) { - // Break up string into separate features - Split(Features, Initial); -} - - -std::string SubtargetFeatures::getString() const { - return Join(Features); -} -void SubtargetFeatures::setString(const std::string &Initial) { - // Throw out old features - Features.clear(); - // Break up string into separate features - Split(Features, LowercaseString(Initial)); -} - - -/// setCPU - Set the CPU string. Replaces previous setting. Setting to "" -/// clears CPU. -void SubtargetFeatures::setCPU(const std::string &String) { - Features[0] = LowercaseString(String); -} - - -/// setCPUIfNone - Setting CPU string only if no string is set. -/// -void SubtargetFeatures::setCPUIfNone(const std::string &String) { - if (Features[0].empty()) setCPU(String); -} - -/// getCPU - Returns current CPU. -/// -const std::string & SubtargetFeatures::getCPU() const { - return Features[0]; -} - - -/// SetImpliedBits - For each feature that is (transitively) implied by this -/// feature, set it. -/// -static -void SetImpliedBits(uint64_t &Bits, const SubtargetFeatureKV *FeatureEntry, - const SubtargetFeatureKV *FeatureTable, - size_t FeatureTableSize) { - for (size_t i = 0; i < FeatureTableSize; ++i) { - const SubtargetFeatureKV &FE = FeatureTable[i]; - - if (FeatureEntry->Value == FE.Value) continue; - - if (FeatureEntry->Implies & FE.Value) { - Bits |= FE.Value; - SetImpliedBits(Bits, &FE, FeatureTable, FeatureTableSize); - } - } -} - -/// ClearImpliedBits - For each feature that (transitively) implies this -/// feature, clear it. -/// -static -void ClearImpliedBits(uint64_t &Bits, const SubtargetFeatureKV *FeatureEntry, - const SubtargetFeatureKV *FeatureTable, - size_t FeatureTableSize) { - for (size_t i = 0; i < FeatureTableSize; ++i) { - const SubtargetFeatureKV &FE = FeatureTable[i]; - - if (FeatureEntry->Value == FE.Value) continue; - - if (FE.Implies & FeatureEntry->Value) { - Bits &= ~FE.Value; - ClearImpliedBits(Bits, &FE, FeatureTable, FeatureTableSize); - } - } -} - -/// getBits - Get feature bits. -/// -uint64_t SubtargetFeatures::getBits(const SubtargetFeatureKV *CPUTable, - size_t CPUTableSize, - const SubtargetFeatureKV *FeatureTable, - size_t FeatureTableSize) { - assert(CPUTable && "missing CPU table"); - assert(FeatureTable && "missing features table"); -#ifndef NDEBUG - for (size_t i = 1; i < CPUTableSize; i++) { - assert(strcmp(CPUTable[i - 1].Key, CPUTable[i].Key) < 0 && - "CPU table is not sorted"); - } - for (size_t i = 1; i < FeatureTableSize; i++) { - assert(strcmp(FeatureTable[i - 1].Key, FeatureTable[i].Key) < 0 && - "CPU features table is not sorted"); - } -#endif - uint64_t Bits = 0; // Resulting bits - - // Check if help is needed - if (Features[0] == "help") - Help(CPUTable, CPUTableSize, FeatureTable, FeatureTableSize); - - // Find CPU entry - const SubtargetFeatureKV *CPUEntry = - Find(Features[0], CPUTable, CPUTableSize); - // If there is a match - if (CPUEntry) { - // Set base feature bits - Bits = CPUEntry->Value; - - // Set the feature implied by this CPU feature, if any. - for (size_t i = 0; i < FeatureTableSize; ++i) { - const SubtargetFeatureKV &FE = FeatureTable[i]; - if (CPUEntry->Value & FE.Value) - SetImpliedBits(Bits, &FE, FeatureTable, FeatureTableSize); - } - } else { - errs() << "'" << Features[0] - << "' is not a recognized processor for this target" - << " (ignoring processor)\n"; - } - // Iterate through each feature - for (size_t i = 1; i < Features.size(); i++) { - const std::string &Feature = Features[i]; - - // Check for help - if (Feature == "+help") - Help(CPUTable, CPUTableSize, FeatureTable, FeatureTableSize); - - // Find feature in table. - const SubtargetFeatureKV *FeatureEntry = - Find(StripFlag(Feature), FeatureTable, FeatureTableSize); - // If there is a match - if (FeatureEntry) { - // Enable/disable feature in bits - if (isEnabled(Feature)) { - Bits |= FeatureEntry->Value; - - // For each feature that this implies, set it. - SetImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize); - } else { - Bits &= ~FeatureEntry->Value; - - // For each feature that implies this, clear it. - ClearImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize); - } - } else { - errs() << "'" << Feature - << "' is not a recognized feature for this target" - << " (ignoring feature)\n"; - } - } - - return Bits; -} - -/// Get info pointer -void *SubtargetFeatures::getInfo(const SubtargetInfoKV *Table, - size_t TableSize) { - assert(Table && "missing table"); -#ifndef NDEBUG - for (size_t i = 1; i < TableSize; i++) { - assert(strcmp(Table[i - 1].Key, Table[i].Key) < 0 && "Table is not sorted"); - } -#endif - - // Find entry - const SubtargetInfoKV *Entry = Find(Features[0], Table, TableSize); - - if (Entry) { - return Entry->Value; - } else { - errs() << "'" << Features[0] - << "' is not a recognized processor for this target" - << " (ignoring processor)\n"; - return NULL; - } -} - -/// print - Print feature string. -/// -void SubtargetFeatures::print(raw_ostream &OS) const { - for (size_t i = 0, e = Features.size(); i != e; ++i) - OS << Features[i] << " "; - OS << "\n"; -} - -/// dump - Dump feature info. -/// -void SubtargetFeatures::dump() const { - print(dbgs()); -} - -/// getDefaultSubtargetFeatures - Return a string listing the features -/// associated with the target triple. -/// -/// FIXME: This is an inelegant way of specifying the features of a -/// subtarget. It would be better if we could encode this information -/// into the IR. See . -/// -void SubtargetFeatures::getDefaultSubtargetFeatures(const std::string &CPU, - const Triple& Triple) { - setCPU(CPU); - - if (Triple.getVendor() == Triple::Apple) { - if (Triple.getArch() == Triple::ppc) { - // powerpc-apple-* - AddFeature("altivec"); - } else if (Triple.getArch() == Triple::ppc64) { - // powerpc64-apple-* - AddFeature("64bit"); - AddFeature("altivec"); - } - } -} Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Tue Jun 28 20:14:12 2011 @@ -12,10 +12,10 @@ //===----------------------------------------------------------------------===// #include "llvm/Target/TargetInstrInfo.h" -#include "llvm/Target/TargetInstrItineraries.h" #include "llvm/Target/TargetRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGNodes.h" #include "llvm/MC/MCAsmInfo.h" +#include "llvm/MC/MCInstrItineraries.h" #include "llvm/Support/ErrorHandling.h" #include using namespace llvm; Modified: llvm/trunk/tools/llc/llc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/tools/llc/llc.cpp (original) +++ llvm/trunk/tools/llc/llc.cpp Tue Jun 28 20:14:12 2011 @@ -22,6 +22,7 @@ #include "llvm/CodeGen/LinkAllAsmWriterComponents.h" #include "llvm/CodeGen/LinkAllCodegenComponents.h" #include "llvm/Config/config.h" +#include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" #include "llvm/Support/FormattedStream.h" @@ -31,7 +32,6 @@ #include "llvm/Support/ToolOutputFile.h" #include "llvm/Support/Host.h" #include "llvm/Support/Signals.h" -#include "llvm/Target/SubtargetFeature.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegistry.h" Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Tue Jun 28 20:14:12 2011 @@ -19,11 +19,11 @@ #include "llvm/MC/MCInstPrinter.h" #include "llvm/MC/MCSectionMachO.h" #include "llvm/MC/MCStreamer.h" +#include "llvm/MC/SubtargetFeature.h" #include "llvm/Target/TargetAsmBackend.h" #include "llvm/Target/TargetAsmParser.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetRegistry.h" -#include "llvm/Target/SubtargetFeature.h" // FIXME. #include "llvm/Target/TargetAsmInfo.h" // FIXME. #include "llvm/Target/TargetLowering.h" // FIXME. #include "llvm/Target/TargetLoweringObjectFile.h" // FIXME. Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Tue Jun 28 20:14:12 2011 @@ -26,8 +26,8 @@ #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" +#include "llvm/MC/SubtargetFeature.h" #include "llvm/Target/Mangler.h" -#include "llvm/Target/SubtargetFeature.h" #include "llvm/Target/TargetOptions.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetMachine.h" Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Tue Jun 28 20:14:12 2011 @@ -29,7 +29,6 @@ #include "llvm/Support/SourceMgr.h" #include "llvm/Support/system_error.h" #include "llvm/Target/Mangler.h" -#include "llvm/Target/SubtargetFeature.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" @@ -37,6 +36,7 @@ #include "llvm/MC/MCParser/MCAsmParser.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" +#include "llvm/MC/SubtargetFeature.h" #include "llvm/Target/TargetAsmParser.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetRegistry.h" Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Tue Jun 28 20:14:12 2011 @@ -654,8 +654,8 @@ OS << "#include \"llvm/Support/Debug.h\"\n"; OS << "#include \"llvm/Support/raw_ostream.h\"\n"; - OS << "#include \"llvm/Target/SubtargetFeature.h\"\n"; - OS << "#include \"llvm/Target/TargetInstrItineraries.h\"\n\n"; + OS << "#include \"llvm/MC/SubtargetFeature.h\"\n"; + OS << "#include \"llvm/MC/MCInstrItineraries.h\"\n\n"; // Enumeration(OS, "FuncUnit", true); // OS<<"\n"; Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.h?rev=134049&r1=134048&r2=134049&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SubtargetEmitter.h (original) +++ llvm/trunk/utils/TableGen/SubtargetEmitter.h Tue Jun 28 20:14:12 2011 @@ -15,7 +15,7 @@ #define SUBTARGET_EMITTER_H #include "TableGenBackend.h" -#include "llvm/Target/TargetInstrItineraries.h" +#include "llvm/MC/MCInstrItineraries.h" #include #include #include From evan.cheng at apple.com Tue Jun 28 20:16:02 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 29 Jun 2011 01:16:02 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r134051 - /llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Message-ID: <20110629011602.C89F62A6C12C@llvm.org> Author: evancheng Date: Tue Jun 28 20:16:02 2011 New Revision: 134051 URL: http://llvm.org/viewvc/llvm-project?rev=134051&view=rev Log: SubtargetFeature.h has been moved to MC. Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=134051&r1=134050&r2=134051&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Tue Jun 28 20:16:02 2011 @@ -35,7 +35,7 @@ #include "llvm/Assembly/PrintModulePass.h" #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/CodeGen/RegAllocRegistry.h" -#include "llvm/Target/SubtargetFeature.h" +#include "llvm/MC/SubtargetFeature.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLibraryInfo.h" #include "llvm/Target/TargetLowering.h" From nlewycky at google.com Tue Jun 28 20:21:05 2011 From: nlewycky at google.com (Nick Lewycky) Date: Tue, 28 Jun 2011 18:21:05 -0700 Subject: [llvm-commits] [patch] Enable simplifycfg in bb with only a lifetime intrinsic In-Reply-To: <4E09D4EC.1020908@gmail.com> References: <4E056DCC.3050107@gmail.com> <4E095E83.8060503@mxc.ca> <4E09D396.5090109@gmail.com> <4E09D4EC.1020908@gmail.com> Message-ID: On 28 June 2011 06:19, Rafael ?vila de Esp?ndola wrote: > Done. Updated patch attached. >> > Correct one now. > Looks great, please commit! Nick > > Cheers, > Rafael > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110628/9eef7fd0/attachment.html From stoklund at 2pi.dk Tue Jun 28 21:03:37 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 29 Jun 2011 02:03:37 -0000 Subject: [llvm-commits] [llvm] r134053 - in /llvm/trunk/lib/CodeGen: RegAllocGreedy.cpp SplitKit.cpp SplitKit.h Message-ID: <20110629020337.1C24E2A6C12C@llvm.org> Author: stoklund Date: Tue Jun 28 21:03:36 2011 New Revision: 134053 URL: http://llvm.org/viewvc/llvm-project?rev=134053&view=rev Log: Revert r134047 while investigating a llvm-gcc-i386-linux-selfhost miscompile. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp llvm/trunk/lib/CodeGen/SplitKit.cpp llvm/trunk/lib/CodeGen/SplitKit.h Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=134053&r1=134052&r2=134053&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Jun 28 21:03:36 2011 @@ -763,46 +763,32 @@ // Create the main cross-block interval. const unsigned MainIntv = SE->openIntv(); - // First handle all the blocks with uses. + // First add all defs that are live out of a block. ArrayRef UseBlocks = SA->getUseBlocks(); for (unsigned i = 0; i != UseBlocks.size(); ++i) { const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; - bool RegIn = BI.LiveIn && - LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; - bool RegOut = BI.LiveOut && - LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; + bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; + bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; // Create separate intervals for isolated blocks with multiple uses. - // - // |---o---o---| Enter and leave on the stack. - // ____-----____ Create local interval for uses. - // - // | o---o---| Defined in block, leave on stack. - // -----____ Create local interval for uses. - // - // |---o---x | Enter on stack, killed in block. - // ____----- Create local interval for uses. - // - if (!RegIn && !RegOut) { + if (!RegIn && !RegOut && BI.FirstUse != BI.LastUse) { DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n"); - if (!BI.isOneInstr()) { - SE->splitSingleBlock(BI); - SE->selectIntv(MainIntv); - } + SE->splitSingleBlock(BI); + SE->selectIntv(MainIntv); continue; } + // Should the register be live out? + if (!BI.LiveOut || !RegOut) + continue; + SlotIndex Start, Stop; tie(Start, Stop) = Indexes->getMBBRange(BI.MBB); Intf.moveToBlock(BI.MBB->getNumber()); - DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0) - << (RegIn ? " => " : " -- ") - << "BB#" << BI.MBB->getNumber() - << (RegOut ? " => " : " -- ") - << " EB#" << Bundles->getBundle(BI.MBB->getNumber(), 1) + DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#" + << Bundles->getBundle(BI.MBB->getNumber(), 1) << " [" << Start << ';' << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop - << ") uses [" << BI.FirstUse << ';' << BI.LastUse << ") intf [" << Intf.first() << ';' << Intf.last() << ')'); // The interference interval should either be invalid or overlap MBB. @@ -811,266 +797,150 @@ assert((!Intf.hasInterference() || Intf.last() > Start) && "Bad interference"); - // We are now ready to decide where to split in the current block. There - // are many variables guiding the decision: - // - // - RegIn / RegOut: The global splitting algorithm's decisions for our - // ingoing and outgoing bundles. - // - // - BI.BlockIn / BI.BlockOut: Is the live range live-in and/or live-out - // from this block. - // - // - Intf.hasInterference(): Is there interference in this block. - // - // - Intf.first() / Inft.last(): The range of interference. - // - // The live range should be split such that MainIntv is live-in when RegIn - // is set, and live-out when RegOut is set. MainIntv should never overlap - // the interference, and the stack interval should never have more than one - // use per block. - - // No splits can be inserted after LastSplitPoint, overlap instead. - SlotIndex LastSplitPoint = Stop; - if (BI.LiveOut) - LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); - - // At this point, we know that either RegIn or RegOut is set. We dealt with - // the all-stack case above. - - // Blocks without interference are relatively easy. + // Check interference leaving the block. if (!Intf.hasInterference()) { - DEBUG(dbgs() << ", no interference.\n"); - SE->selectIntv(MainIntv); - // The easiest case has MainIntv live through. - // - // |---o---o---| Live-in, live-out. - // ============= Use MainIntv everywhere. - // - SlotIndex From = Start, To = Stop; - - // Block entry. Reload before the first use if MainIntv is not live-in. - // - // |---o-- Enter on stack. - // ____=== Reload before first use. - // - // | o-- Defined in block. - // === Use MainIntv from def. - // - if (!RegIn) - From = SE->enterIntvBefore(BI.FirstUse); - - // Block exit. Handle cases where MainIntv is not live-out. - if (!BI.LiveOut) - // - // --x | Killed in block. - // === Use MainIntv up to kill. - // - To = SE->leaveIntvAfter(BI.LastUse); - else if (!RegOut) { - // - // --o---| Live-out on stack. - // ===____ Use MainIntv up to last use, switch to stack. - // - // -----o| Live-out on stack, last use after last split point. - // ====== Extend MainIntv to last use, overlapping. - // \____ Copy to stack interval before last split point. - // - if (BI.LastUse < LastSplitPoint) - To = SE->leaveIntvAfter(BI.LastUse); - else { - // The last use is after the last split point, it is probably an - // indirect branch. - To = SE->leaveIntvBefore(LastSplitPoint); - // Run a double interval from the split to the last use. This makes - // it possible to spill the complement without affecting the indirect - // branch. - SE->overlapIntv(To, BI.LastUse); - } + // Block is interference-free. + DEBUG(dbgs() << ", no interference"); + if (!BI.LiveThrough) { + DEBUG(dbgs() << ", not live-through.\n"); + SE->useIntv(SE->enterIntvBefore(BI.FirstUse), Stop); + continue; } - - // Paint in MainIntv liveness for this block. - SE->useIntv(From, To); + if (!RegIn) { + // Block is live-through, but entry bundle is on the stack. + // Reload just before the first use. + DEBUG(dbgs() << ", not live-in, enter before first use.\n"); + SE->useIntv(SE->enterIntvBefore(BI.FirstUse), Stop); + continue; + } + DEBUG(dbgs() << ", live-through.\n"); continue; } - // We are now looking at a block with interference, and we know that either - // RegIn or RegOut is set. - assert(Intf.hasInterference() && (RegIn || RegOut) && "Bad invariant"); + // Block has interference. + DEBUG(dbgs() << ", interference to " << Intf.last()); - // If the live range is not live through the block, it is possible that the - // interference doesn't even overlap. Deal with those cases first. Since - // no copy instructions are required, we can tolerate interference starting - // or ending at the same instruction that kills or defines our live range. - - // Live-in, killed before interference. - // - // ~~~ Interference after kill. - // |---o---x | Killed in block. - // ========= Use MainIntv everywhere. - // - if (RegIn && !BI.LiveOut && BI.LastUse <= Intf.first()) { - DEBUG(dbgs() << ", live-in, killed before interference.\n"); - SE->selectIntv(MainIntv); - SlotIndex To = SE->leaveIntvAfter(BI.LastUse); - SE->useIntv(Start, To); + if (!BI.LiveThrough && Intf.last() <= BI.FirstUse) { + // The interference doesn't reach the outgoing segment. + DEBUG(dbgs() << " doesn't affect def from " << BI.FirstUse << '\n'); + SE->useIntv(BI.FirstUse, Stop); continue; } - // Live-out, defined after interference. - // - // ~~~ Interference before def. - // | o---o---| Defined in block. - // ========= Use MainIntv everywhere. - // - if (RegOut && !BI.LiveIn && BI.FirstUse >= Intf.last()) { - DEBUG(dbgs() << ", live-out, defined after interference.\n"); - SE->selectIntv(MainIntv); - SlotIndex From = SE->enterIntvBefore(BI.FirstUse); - SE->useIntv(From, Stop); - continue; + SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); + if (Intf.last().getBoundaryIndex() < BI.LastUse) { + // There are interference-free uses at the end of the block. + // Find the first use that can get the live-out register. + SmallVectorImpl::const_iterator UI = + std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), + Intf.last().getBoundaryIndex()); + assert(UI != SA->UseSlots.end() && "Couldn't find last use"); + SlotIndex Use = *UI; + assert(Use <= BI.LastUse && "Couldn't find last use"); + // Only attempt a split befroe the last split point. + if (Use.getBaseIndex() <= LastSplitPoint) { + DEBUG(dbgs() << ", free use at " << Use << ".\n"); + SlotIndex SegStart = SE->enterIntvBefore(Use); + assert(SegStart >= Intf.last() && "Couldn't avoid interference"); + assert(SegStart < LastSplitPoint && "Impossible split point"); + SE->useIntv(SegStart, Stop); + continue; + } } - // The interference is now known to overlap the live range, but it may - // still be easy to avoid if all the interference is on one side of the - // uses, and we enter or leave on the stack. + // Interference is after the last use. + DEBUG(dbgs() << " after last use.\n"); + SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB); + assert(SegStart >= Intf.last() && "Couldn't avoid interference"); + } - // Live-out on stack, interference after last use. - // - // ~~~ Interference after last use. - // |---o---o---| Live-out on stack. - // =========____ Leave MainIntv after last use. - // - // ~ Interference after last use. - // |---o---o--o| Live-out on stack, late last use. - // =========____ Copy to stack after LSP, overlap MainIntv. - // - if (!RegOut && Intf.first() > BI.LastUse.getBoundaryIndex()) { - assert(RegIn && "Stack-in, stack-out should already be handled"); - if (BI.LastUse < LastSplitPoint) { - DEBUG(dbgs() << ", live-in, stack-out, interference after last use.\n"); - SE->selectIntv(MainIntv); - SlotIndex To = SE->leaveIntvAfter(BI.LastUse); - assert(To <= Intf.first() && "Expected to avoid interference"); - SE->useIntv(Start, To); - } else { - DEBUG(dbgs() << ", live-in, stack-out, avoid last split point\n"); - SE->selectIntv(MainIntv); - SlotIndex To = SE->leaveIntvBefore(LastSplitPoint); - assert(To <= Intf.first() && "Expected to avoid interference"); - SE->overlapIntv(To, BI.LastUse); - SE->useIntv(Start, To); + // Now all defs leading to live bundles are handled, do everything else. + for (unsigned i = 0; i != UseBlocks.size(); ++i) { + const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; + bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; + bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; + + // Is the register live-in? + if (!BI.LiveIn || !RegIn) + continue; + + // We have an incoming register. Check for interference. + SlotIndex Start, Stop; + tie(Start, Stop) = Indexes->getMBBRange(BI.MBB); + Intf.moveToBlock(BI.MBB->getNumber()); + DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0) + << " -> BB#" << BI.MBB->getNumber() << " [" << Start << ';' + << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop + << ')'); + + // Check interference entering the block. + if (!Intf.hasInterference()) { + // Block is interference-free. + DEBUG(dbgs() << ", no interference"); + if (!BI.LiveThrough) { + DEBUG(dbgs() << ", killed in block.\n"); + SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse)); + continue; } + if (!RegOut) { + SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); + // Block is live-through, but exit bundle is on the stack. + // Spill immediately after the last use. + if (BI.LastUse < LastSplitPoint) { + DEBUG(dbgs() << ", uses, stack-out.\n"); + SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse)); + continue; + } + // The last use is after the last split point, it is probably an + // indirect jump. + DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point " + << LastSplitPoint << ", stack-out.\n"); + SlotIndex SegEnd = SE->leaveIntvBefore(LastSplitPoint); + SE->useIntv(Start, SegEnd); + // Run a double interval from the split to the last use. + // This makes it possible to spill the complement without affecting the + // indirect branch. + SE->overlapIntv(SegEnd, BI.LastUse); + continue; + } + // Register is live-through. + DEBUG(dbgs() << ", uses, live-through.\n"); + SE->useIntv(Start, Stop); continue; } - // Live-in on stack, interference before first use. - // - // ~~~ Interference before first use. - // |---o---o---| Live-in on stack. - // ____========= Enter MainIntv before first use. - // - if (!RegIn && Intf.last() < BI.FirstUse.getBaseIndex()) { - assert(RegOut && "Stack-in, stack-out should already be handled"); - DEBUG(dbgs() << ", stack-in, interference before first use.\n"); - SE->selectIntv(MainIntv); - SlotIndex From = SE->enterIntvBefore(BI.FirstUse); - assert(From >= Intf.last() && "Expected to avoid interference"); - SE->useIntv(From, Stop); + // Block has interference. + DEBUG(dbgs() << ", interference from " << Intf.first()); + + if (!BI.LiveThrough && Intf.first() >= BI.LastUse) { + // The interference doesn't reach the outgoing segment. + DEBUG(dbgs() << " doesn't affect kill at " << BI.LastUse << '\n'); + SE->useIntv(Start, BI.LastUse); continue; } - // The interference is overlapping somewhere we wanted to use MainIntv. That - // means we need to create a local interval that can be allocated a - // different register. - DEBUG(dbgs() << ", creating local interval.\n"); - unsigned LocalIntv = SE->openIntv(); - - // We may be creating copies directly between MainIntv and LocalIntv, - // bypassing the stack interval. When we do that, we should never use the - // leaveIntv* methods as they define values in the stack interval. By - // starting from the end of the block and working our way backwards, we can - // get by with only enterIntv* methods. - // - // When selecting split points, we generally try to maximize the stack - // interval as long at it contains no uses, maximize the main interval as - // long as it doesn't overlap interference, and minimize the local interval - // that we don't know how to allocate yet. - - // Handle the block exit, set Pos to the first handled slot. - SlotIndex Pos = BI.LastUse; - if (RegOut) { - assert(Intf.last() < LastSplitPoint && "Cannot be live-out in register"); - // Create a snippet of MainIntv that is live-out. - // - // ~~~ Interference overlapping uses. - // --o---| Live-out in MainIntv. - // ----=== Switch from LocalIntv to MainIntv after interference. - // - SE->selectIntv(MainIntv); - Pos = SE->enterIntvAfter(Intf.last()); - assert(Pos >= Intf.last() && "Expected to avoid interference"); - SE->useIntv(Pos, Stop); - SE->selectIntv(LocalIntv); - } else if (BI.LiveOut) { - if (BI.LastUse < LastSplitPoint) { - // Live-out on the stack. - // - // ~~~ Interference overlapping uses. - // --o---| Live-out on stack. - // ---____ Switch from LocalIntv to stack after last use. - // - Pos = SE->leaveIntvAfter(BI.LastUse); - } else { - // Live-out on the stack, last use after last split point. - // - // ~~~ Interference overlapping uses. - // --o--o| Live-out on stack, late use. - // ------ Copy to stack before LSP, overlap LocalIntv. - // \__ - // - Pos = SE->leaveIntvBefore(LastSplitPoint); - // We need to overlap LocalIntv so it can reach LastUse. - SE->overlapIntv(Pos, BI.LastUse); - } + if (Intf.first().getBaseIndex() > BI.FirstUse) { + // There are interference-free uses at the beginning of the block. + // Find the last use that can get the register. + SmallVectorImpl::const_iterator UI = + std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), + Intf.first().getBaseIndex()); + assert(UI != SA->UseSlots.begin() && "Couldn't find first use"); + SlotIndex Use = (--UI)->getBoundaryIndex(); + DEBUG(dbgs() << ", free use at " << *UI << ".\n"); + SlotIndex SegEnd = SE->leaveIntvAfter(Use); + assert(SegEnd <= Intf.first() && "Couldn't avoid interference"); + SE->useIntv(Start, SegEnd); + continue; } - // When not live-out, leave Pos at LastUse. We have handled everything from - // Pos to Stop. Find the starting point for LocalIntv. - assert(SE->currentIntv() == LocalIntv && "Expecting local interval"); - - if (RegIn) { - assert(Start < Intf.first() && "Cannot be live-in with interference"); - // Live-in in MainIntv, only use LocalIntv for interference. - // - // ~~~ Interference overlapping uses. - // |---o-- Live-in in MainIntv. - // ====--- Switch to LocalIntv before interference. - // - SlotIndex Switch = SE->enterIntvBefore(Intf.first()); - assert(Switch <= Intf.first() && "Expected to avoid interference"); - SE->useIntv(Switch, Pos); - SE->selectIntv(MainIntv); - SE->useIntv(Start, Switch); - } else { - // Live-in on stack, enter LocalIntv before first use. - // - // ~~~ Interference overlapping uses. - // |---o-- Live-in in MainIntv. - // ____--- Reload to LocalIntv before interference. - // - // Defined in block. - // - // ~~~ Interference overlapping uses. - // | o-- Defined in block. - // --- Begin LocalIntv at first use. - // - SlotIndex Switch = SE->enterIntvBefore(BI.FirstUse); - SE->useIntv(Switch, Pos); - } + // Interference is before the first use. + DEBUG(dbgs() << " before first use.\n"); + SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB); + assert(SegEnd <= Intf.first() && "Couldn't avoid interference"); } // Handle live-through blocks. - SE->selectIntv(MainIntv); for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) { unsigned Number = Cand.ActiveBlocks[i]; bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)]; Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=134053&r1=134052&r2=134053&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Jun 28 21:03:36 2011 @@ -636,7 +636,6 @@ void SplitEditor::selectIntv(unsigned Idx) { assert(Idx != 0 && "Cannot select the complement interval"); assert(Idx < Edit->size() && "Can only select previously opened interval"); - DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n'); OpenIdx = Idx; } @@ -657,24 +656,6 @@ return VNI->def; } -SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) { - assert(OpenIdx && "openIntv not called before enterIntvAfter"); - DEBUG(dbgs() << " enterIntvAfter " << Idx); - Idx = Idx.getBoundaryIndex(); - VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx); - if (!ParentVNI) { - DEBUG(dbgs() << ": not live\n"); - return Idx; - } - DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); - MachineInstr *MI = LIS.getInstructionFromIndex(Idx); - assert(MI && "enterIntvAfter called with invalid index"); - - VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), - llvm::next(MachineBasicBlock::iterator(MI))); - return VNI->def; -} - SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) { assert(OpenIdx && "openIntv not called before enterIntvAtEnd"); SlotIndex End = LIS.getMBBEndIdx(&MBB); @@ -1026,6 +1007,12 @@ markComplexMapped(i, ParentVNI); } +#ifndef NDEBUG + // Every new interval must have a def by now, otherwise the split is bogus. + for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I) + assert((*I)->hasAtLeastOneValue() && "Split interval has no value"); +#endif + // Transfer the simply mapped values, check if any are skipped. bool Skipped = transferValues(); if (Skipped) Modified: llvm/trunk/lib/CodeGen/SplitKit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=134053&r1=134052&r2=134053&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.h (original) +++ llvm/trunk/lib/CodeGen/SplitKit.h Tue Jun 28 21:03:36 2011 @@ -81,12 +81,6 @@ bool LiveThrough; ///< Live in whole block (Templ 5. above). bool LiveIn; ///< Current reg is live in. bool LiveOut; ///< Current reg is live out. - - /// isOneInstr - Returns true when this BlockInfo describes a single - /// instruction. - bool isOneInstr() const { - return SlotIndex::isSameInstr(FirstUse, LastUse); - } }; private: @@ -366,10 +360,6 @@ /// Return the beginning of the new live range. SlotIndex enterIntvBefore(SlotIndex Idx); - /// enterIntvAfter - Enter the open interval after the instruction at Idx. - /// Return the beginning of the new live range. - SlotIndex enterIntvAfter(SlotIndex Idx); - /// enterIntvAtEnd - Enter the open interval at the end of MBB. /// Use the open interval from he inserted copy to the MBB end. /// Return the beginning of the new live range. From atrick at apple.com Tue Jun 28 22:13:40 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 29 Jun 2011 03:13:40 -0000 Subject: [llvm-commits] [llvm] r134054 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/no-iv-rewrite.ll Message-ID: <20110629031340.DBF4B2A6C12C@llvm.org> Author: atrick Date: Tue Jun 28 22:13:40 2011 New Revision: 134054 URL: http://llvm.org/viewvc/llvm-project?rev=134054&view=rev Log: indvars -disable-iv-rewrite: just because SCEV ignores casts doesn't mean they can be removed. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=134054&r1=134053&r2=134054&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Tue Jun 28 22:13:40 2011 @@ -1007,6 +1007,7 @@ // Eliminate any operation that SCEV can prove is an identity function. if (!SE->isSCEVable(UseInst->getType()) || + (UseInst->getType() != IVOperand->getType()) || (SE->getSCEV(UseInst) != SE->getSCEV(IVOperand))) return false; Modified: llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll?rev=134054&r1=134053&r2=134054&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Tue Jun 28 22:13:40 2011 @@ -23,6 +23,7 @@ ; sext should be eliminated while preserving gep inboundsness. ; CHECK-NOT: sext ; CHECK: getelementptr inbounds +; CHECK: exit loop: %i.02 = phi i32 [ 0, %ph ], [ %iinc, %loop ] %s.01 = phi i32 [ 0, %ph ], [ %sinc, %loop ] @@ -63,6 +64,7 @@ ; CHECK: getelementptr inbounds ; %vall sext should obviously not be eliminated ; CHECK: sext +; CHECK: exit loop: %i.02 = phi i32 [ 0, %ph ], [ %iinc, %loop ] %s.01 = phi i64 [ 0, %ph ], [ %sinc, %loop ] @@ -106,6 +108,7 @@ ; Preserve gep inboundsness, and don't factor it. ; CHECK: getelementptr inbounds i32* %ptriv, i32 1 ; CHECK-NOT: add +; CHECK: exit loop: %ptriv = phi i32* [ %first, %ph ], [ %ptrpost, %loop ] %ofs = sext i32 %idx to i64 @@ -121,3 +124,37 @@ return: ret void } + +%struct = type { i32 } + +define void @bitcastiv(i32 %start, i32 %limit, i32 %step, %struct* %base) +nounwind +{ +entry: + br label %loop + +; CHECK: loop: +; +; Preserve casts +; CHECK: phi i32 +; CHECK: bitcast +; CHECK: getelementptr +; CHECK: exit +loop: + %iv = phi i32 [%start, %entry], [%next, %loop] + %p = phi %struct* [%base, %entry], [%pinc, %loop] + %adr = getelementptr %struct* %p, i32 0, i32 0 + store i32 3, i32* %adr + %pp = bitcast %struct* %p to i32* + store i32 4, i32* %pp + %pinc = getelementptr %struct* %p, i32 1 + %next = add i32 %iv, 1 + %cond = icmp ne i32 %next, %limit + br i1 %cond, label %loop, label %exit + +exit: + br label %return + +return: + ret void +} \ No newline at end of file From geek4civic at gmail.com Tue Jun 28 22:26:17 2011 From: geek4civic at gmail.com (NAKAMURA Takumi) Date: Wed, 29 Jun 2011 03:26:17 -0000 Subject: [llvm-commits] [llvm] r134055 - in /llvm/trunk/lib: MC/CMakeLists.txt Target/CMakeLists.txt Message-ID: <20110629032617.D8E6B2A6C12C@llvm.org> Author: chapuni Date: Tue Jun 28 22:26:17 2011 New Revision: 134055 URL: http://llvm.org/viewvc/llvm-project?rev=134055&view=rev Log: Fix CMake build. Modified: llvm/trunk/lib/MC/CMakeLists.txt llvm/trunk/lib/Target/CMakeLists.txt Modified: llvm/trunk/lib/MC/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=134055&r1=134054&r2=134055&view=diff ============================================================================== --- llvm/trunk/lib/MC/CMakeLists.txt (original) +++ llvm/trunk/lib/MC/CMakeLists.txt Tue Jun 28 22:26:17 2011 @@ -34,6 +34,7 @@ MachObjectWriter.cpp WinCOFFStreamer.cpp WinCOFFObjectWriter.cpp + SubtargetFeature.cpp TargetAsmBackend.cpp ) Modified: llvm/trunk/lib/Target/CMakeLists.txt URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=134055&r1=134054&r2=134055&view=diff ============================================================================== --- llvm/trunk/lib/Target/CMakeLists.txt (original) +++ llvm/trunk/lib/Target/CMakeLists.txt Tue Jun 28 22:26:17 2011 @@ -1,6 +1,5 @@ add_llvm_library(LLVMTarget Mangler.cpp - SubtargetFeature.cpp Target.cpp TargetAsmInfo.cpp TargetAsmLexer.cpp From rafael.espindola at gmail.com Wed Jun 29 00:25:47 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 29 Jun 2011 05:25:47 -0000 Subject: [llvm-commits] [llvm] r134057 - in /llvm/trunk: include/llvm/BasicBlock.h lib/Transforms/Utils/Local.cpp lib/Transforms/Utils/SimplifyCFG.cpp lib/VMCore/BasicBlock.cpp test/Transforms/SimplifyCFG/lifetime.ll Message-ID: <20110629052547.DB3E92A6C12C@llvm.org> Author: rafael Date: Wed Jun 29 00:25:47 2011 New Revision: 134057 URL: http://llvm.org/viewvc/llvm-project?rev=134057&view=rev Log: Let simplify cfg simplify bb with only debug and lifetime intrinsics. Added: llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll Modified: llvm/trunk/include/llvm/BasicBlock.h llvm/trunk/lib/Transforms/Utils/Local.cpp llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp llvm/trunk/lib/VMCore/BasicBlock.cpp Modified: llvm/trunk/include/llvm/BasicBlock.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BasicBlock.h?rev=134057&r1=134056&r2=134057&view=diff ============================================================================== --- llvm/trunk/include/llvm/BasicBlock.h (original) +++ llvm/trunk/include/llvm/BasicBlock.h Wed Jun 29 00:25:47 2011 @@ -138,6 +138,12 @@ return const_cast(this)->getFirstNonPHIOrDbg(); } + // Same as above, but also skip lifetime intrinsics. + Instruction* getFirstNonPHIOrDbgOrLifetime(); + const Instruction* getFirstNonPHIOrDbgOrLifetime() const { + return const_cast(this)->getFirstNonPHIOrDbgOrLifetime(); + } + /// removeFromParent - This method unlinks 'this' from the containing /// function, but does not delete it. /// Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=134057&r1=134056&r2=134057&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Wed Jun 29 00:25:47 2011 @@ -536,9 +536,9 @@ /// TryToSimplifyUncondBranchFromEmptyBlock - BB is known to contain an /// unconditional branch, and contains no instructions other than PHI nodes, -/// potential debug intrinsics and the branch. If possible, eliminate BB by -/// rewriting all the predecessors to branch to the successor block and return -/// true. If we can't transform, return false. +/// potential side-effect free intrinsics and the branch. If possible, +/// eliminate BB by rewriting all the predecessors to branch to the successor +/// block and return true. If we can't transform, return false. bool llvm::TryToSimplifyUncondBranchFromEmptyBlock(BasicBlock *BB) { assert(BB != &BB->getParent()->getEntryBlock() && "TryToSimplifyUncondBranchFromEmptyBlock called on entry block!"); @@ -613,13 +613,15 @@ } } - while (PHINode *PN = dyn_cast(&BB->front())) { - if (Succ->getSinglePredecessor()) { - // BB is the only predecessor of Succ, so Succ will end up with exactly - // the same predecessors BB had. - Succ->getInstList().splice(Succ->begin(), - BB->getInstList(), BB->begin()); - } else { + if (Succ->getSinglePredecessor()) { + // BB is the only predecessor of Succ, so Succ will end up with exactly + // the same predecessors BB had. + + // Copy over any phi, debug or lifetime instruction. + BB->getTerminator()->eraseFromParent(); + Succ->getInstList().splice(Succ->begin(), BB->getInstList()); + } else { + while (PHINode *PN = dyn_cast(&BB->front())) { // We explicitly check for such uses in CanPropagatePredecessorsForPHIs. assert(PN->use_empty() && "There shouldn't be any uses here!"); PN->eraseFromParent(); Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=134057&r1=134056&r2=134057&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed Jun 29 00:25:47 2011 @@ -2604,7 +2604,7 @@ BasicBlock *BB = BI->getParent(); // If the Terminator is the only non-phi instruction, simplify the block. - BasicBlock::iterator I = BB->getFirstNonPHIOrDbg(); + BasicBlock::iterator I = BB->getFirstNonPHIOrDbgOrLifetime(); if (I->isTerminator() && BB != &BB->getParent()->getEntryBlock() && TryToSimplifyUncondBranchFromEmptyBlock(BB)) return true; Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=134057&r1=134056&r2=134057&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/BasicBlock.cpp (original) +++ llvm/trunk/lib/VMCore/BasicBlock.cpp Wed Jun 29 00:25:47 2011 @@ -147,6 +147,26 @@ return &*i; } +Instruction* BasicBlock::getFirstNonPHIOrDbgOrLifetime() { + // All valid basic blocks should have a terminator, + // which is not a PHINode. If we have an invalid basic + // block we'll get an assertion failure when dereferencing + // a past-the-end iterator. + BasicBlock::iterator i = begin(); + for (;; ++i) { + if (isa(i) || isa(i)) + continue; + + const IntrinsicInst *II = dyn_cast(i); + if (!II) + break; + if (II->getIntrinsicID() != Intrinsic::lifetime_start && + II->getIntrinsicID() != Intrinsic::lifetime_end) + break; + } + return &*i; +} + void BasicBlock::dropAllReferences() { for(iterator I = begin(), E = end(); I != E; ++I) I->dropAllReferences(); Added: llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll?rev=134057&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll (added) +++ llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll Wed Jun 29 00:25:47 2011 @@ -0,0 +1,29 @@ +; RUN: opt < %s -simplifycfg -S | FileCheck %s + +; Test that a lifetime intrinsic doesn't prevent us from simplifying this. + +; CHECK: foo +; CHECK: entry: +; CHECK-NOT: bb0: +; CHECK-NOT: bb1: +; CHECK: ret +define void @foo(i1 %x) { +entry: + %a = alloca i8 + call void @llvm.lifetime.start(i64 -1, i8* %a) nounwind + br i1 %x, label %bb0, label %bb1 + +bb0: + call void @llvm.lifetime.end(i64 -1, i8* %a) nounwind + br label %bb1 + +bb1: + call void @f() + ret void +} + +declare void @f() + +declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind + +declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind From rafael.espindola at gmail.com Wed Jun 29 00:37:45 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Wed, 29 Jun 2011 01:37:45 -0400 Subject: [llvm-commits] ideas for 10096 In-Reply-To: <4E0A6D0B.2080208@gmail.com> References: <4E0A1F01.6090408@gmail.com> <4E0A6D0B.2080208@gmail.com> Message-ID: <4E0ABA29.80100@gmail.com> > That is what I am trying to do, it is just a bit hard to do in the current > code organization. I realized that probably it is the way it is because a value number can be in many live ranges, so it is more efficient to handle them first. I think I managed to plug in the current structure by faking a copy. I have attached the current hackish version. It currently produces code like vregX = vregZ vregX = vregZ when it runs and that confuses other parts of the coalescer. I will try to debug and send for review tomorrow. Thanks, Rafael -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: hack.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110629/d0e75a5d/attachment.pl From anton at korobeynikov.info Wed Jun 29 00:51:09 2011 From: anton at korobeynikov.info (Anton Korobeynikov) Date: Wed, 29 Jun 2011 09:51:09 +0400 Subject: [llvm-commits] [llvm] r134049 - in /llvm/trunk: include/llvm/MC/ include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/ExecutionEngine/ lib/MC/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/MBlaze/ lib/Tar Message-ID: Hi Evan, > Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC. Given that scheduling is performed on MachinInstr's, why itineraries should go into MC? -- With best regards, Anton Korobeynikov Faculty of Mathematics and Mechanics, Saint Petersburg State University From baldrick at free.fr Wed Jun 29 02:00:45 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 29 Jun 2011 07:00:45 -0000 Subject: [llvm-commits] [dragonegg] r134058 - in /dragonegg/trunk/src: Convert.cpp Trees.cpp Message-ID: <20110629070045.BAD1C2A6C12C@llvm.org> Author: baldrick Date: Wed Jun 29 02:00:45 2011 New Revision: 134058 URL: http://llvm.org/viewvc/llvm-project?rev=134058&view=rev Log: Simplify EmitIntegerRegisterConstant using getIntegerValue which turns an INTEGER_CST into an APInt. Modified: dragonegg/trunk/src/Convert.cpp dragonegg/trunk/src/Trees.cpp Modified: dragonegg/trunk/src/Convert.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Convert.cpp?rev=134058&r1=134057&r2=134058&view=diff ============================================================================== --- dragonegg/trunk/src/Convert.cpp (original) +++ dragonegg/trunk/src/Convert.cpp Wed Jun 29 02:00:45 2011 @@ -6201,23 +6201,7 @@ /// EmitIntegerRegisterConstant - Turn the given INTEGER_CST into an LLVM /// constant of the corresponding register type. Constant *TreeToLLVM::EmitIntegerRegisterConstant(tree reg) { - unsigned Precision = TYPE_PRECISION(TREE_TYPE(reg)); - - ConstantInt *CI; - if (HOST_BITS_PER_WIDE_INT < integerPartWidth) { - assert(2 * HOST_BITS_PER_WIDE_INT <= integerPartWidth && - "Unsupported host integer precision!"); - unsigned ShiftAmt = HOST_BITS_PER_WIDE_INT; - integerPart Val = (integerPart)(unsigned HOST_WIDE_INT)TREE_INT_CST_LOW(reg) - + ((integerPart)(unsigned HOST_WIDE_INT)TREE_INT_CST_HIGH(reg) << ShiftAmt); - CI = ConstantInt::get(Context, APInt(Precision, Val)); - } else { - assert(HOST_BITS_PER_WIDE_INT == integerPartWidth && - "The engines cannae' take it captain!"); - integerPart Parts[] = { TREE_INT_CST_LOW(reg), TREE_INT_CST_HIGH(reg) }; - CI = ConstantInt::get(Context, APInt(Precision, 2, Parts)); - } - + ConstantInt *CI = ConstantInt::get(Context, getIntegerValue(reg)); // The destination can be a pointer, integer or floating point type so we need // a generalized cast here const Type *Ty = getRegType(TREE_TYPE(reg)); Modified: dragonegg/trunk/src/Trees.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Trees.cpp?rev=134058&r1=134057&r2=134058&view=diff ============================================================================== --- dragonegg/trunk/src/Trees.cpp (original) +++ dragonegg/trunk/src/Trees.cpp Wed Jun 29 02:00:45 2011 @@ -152,7 +152,8 @@ assert(integerPartWidth == 2 * HOST_BITS_PER_WIDE_INT && "Unsupported host integer width!"); unsigned ShiftAmt = HOST_BITS_PER_WIDE_INT; - integerPart Part = integerPart(val.low) + (integerPart(val.high) << ShiftAmt); + integerPart Part = integerPart((unsigned HOST_WIDE_INT)val.low) + + (integerPart((unsigned HOST_WIDE_INT)val.high) << ShiftAmt); return APInt(NumBits, Part); } From baldrick at free.fr Wed Jun 29 02:27:26 2011 From: baldrick at free.fr (Duncan Sands) Date: Wed, 29 Jun 2011 07:27:26 -0000 Subject: [llvm-commits] [dragonegg] r134060 - /dragonegg/trunk/src/Backend.cpp Message-ID: <20110629072726.CFFE92A6C12C@llvm.org> Author: baldrick Date: Wed Jun 29 02:27:26 2011 New Revision: 134060 URL: http://llvm.org/viewvc/llvm-project?rev=134060&view=rev Log: Fix the build: an LLVM header was renamed. Modified: dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=134060&r1=134059&r2=134060&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Wed Jun 29 02:27:26 2011 @@ -39,9 +39,9 @@ #include "llvm/Assembly/PrintModulePass.h" #include "llvm/Bitcode/ReaderWriter.h" #include "llvm/CodeGen/RegAllocRegistry.h" +#include "llvm/MC/SubtargetFeature.h" #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/PassManagerBuilder.h" -#include "llvm/Target/SubtargetFeature.h" #include "llvm/Target/TargetData.h" #include "llvm/Target/TargetLibraryInfo.h" #include "llvm/Target/TargetRegistry.h" From pichet2000 at gmail.com Wed Jun 29 03:56:31 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Wed, 29 Jun 2011 04:56:31 -0400 Subject: [llvm-commits] [llvm] r133940 - in /llvm/trunk: include/llvm/Target/ utils/TableGen/ In-Reply-To: <20110627210622.127C32A6C12C@llvm.org> References: <20110627210622.127C32A6C12C@llvm.org> Message-ID: On Mon, Jun 27, 2011 at 5:06 PM, Owen Anderson wrote: > Author: resistor > Date: Mon Jun 27 16:06:21 2011 > New Revision: 133940 > > URL: http://llvm.org/viewvc/llvm-project?rev=133940&view=rev > Log: > Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. ?For example, an instruciton that prints d0[0] instead of s0. > Patch by Jim Grosbach. > > Modified: > ? ?llvm/trunk/include/llvm/Target/Target.td > ? ?llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp > ? ?llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp > ? ?llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp > ? ?llvm/trunk/utils/TableGen/CodeGenInstruction.cpp > ? ?llvm/trunk/utils/TableGen/CodeGenTarget.cpp > ? ?llvm/trunk/utils/TableGen/CodeGenTarget.h > ? ?llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp > ? ?llvm/trunk/utils/TableGen/FastISelEmitter.cpp > ? ?llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp > ? ?llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp > ? ?llvm/trunk/utils/TableGen/Record.cpp > ? ?llvm/trunk/utils/TableGen/Record.h > ? ?llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp > I am not sure if this commit is to blame but it seems to be the most probable. There is a huge regression on MSVC since last Monday with over 300 failing tests. Seems like X86GenAsmWriter.inc is generated with some invalid data on MSVC. I copied X86GenAsmWriter.inc from my Mac to my PC and the failing test went from 300+ to only 4. So I did a diff between X86GenAsmWriter.inc (PC and Mac) and I saw some difference in X86ATTInstPrinter::getRegisterName() PC Version: =========================================================== const char *X86ATTInstPrinter::getRegisterName(unsigned RegNo) { assert(RegNo && RegNo < 160 && "Invalid register number!"); static const unsigned RegAsmOffset[] = { 0, 3, 6, 9, 3, 12, 15, 6, 9, 3, 19, 23, 27, 31, 35, 39, 43, 47, 51, 55, 59, 64, 69, 74, 79, 84, 89, 6, 9, 92, 95, 3, 19, 23, 27, 31, 35, 39, 43, 47, 89, 6, 99, 103, 107, 111, 115, 119, 123, 129, 133, 89, 137, 141, 145, 149, 153, 157, 161, 165, 169, 89, 89, 12, 173, 177, 181, 185, 189, 193, 197, 201, 205, 208, 212, 216, 220, 223, 227, 231, 235, 239, 244, 249, 254, 258, 263, 268, 273, 277, 282, 287, 292, 296, 301, 306, 311, 315, 320, 325, 330, 334, 339, 344, 99, 103, 107, 111, 115, 119, 129, 133, 137, 141, 92, 95, 12, 15, 89, 349, 355, 361, 367, 373, 379, 385, 391, 397, 402, 407, 412, 417, 422, 427, 432, 437, 442, 447, 453, 459, 465, 471, 477, 397, 402, 407, 412, 417, 422, 427, 432, 437, 442, 447, 453, 459, 465, 471, 477, 0 }; const char *AsmStrs = "\000h\000\000l\000\000x\000\000h\000\000p\000\000pl\000\000r0\000\000r1" "\000\000r2\000\000r3\000\000r4\000\000r5\000\000r6\000\000r7\000\000r8\000" "\000r9\000\000r10\000\000r11\000\000r12\000\000r13\000\000r14\000\000r1" "5\000\000s\000\000i\000\000il\000\000ax\000\000bp\000\000bx\000\000cx\000" "\000di\000\000dx\000\000lags\000\000ip\000\000iz\000\000si\000\000sp\000" "\000p0\000\000p1\000\000p2\000\000p3\000\000p4\000\000p5\000\000p6\000\000" "m0\000\000m1\000\000m2\000\000m3\000\000m4\000\000m5\000\000m6\000\000m" "7\000\0008\000\0008b\000\0008d\000\0008w\000\0009\000\0009b\000\0009d\000" "\0009w\000\00010\000\00010b\000\00010d\000\00010w\000\00011\000\00011b\000" "\00011d\000\00011w\000\00012\000\00012b\000\00012d\000\00012w\000\00013" "\000\00013b\000\00013d\000\00013w\000\00014\000\00014b\000\00014d\000\000" "14w\000\00015\000\00015b\000\00015d\000\00015w\000\000t(0)\000\000t(1)\000" "\000t(2)\000\000t(3)\000\000t(4)\000\000t(5)\000\000t(6)\000\000t(7)\000" "\000mm0\000\000mm1\000\000mm2\000\000mm3\000\000mm4\000\000mm5\000\000m" "m6\000\000mm7\000\000mm8\000\000mm9\000\000mm10\000\000mm11\000\000mm12" "\000\000mm13\000\000mm14\000\000mm15\000"; assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && "Invalid alt name index for register!"); return AsmStrs+RegAsmOffset[RegNo-1]; } ==================================================================== Mac version: ===================================================================== const char *X86ATTInstPrinter::getRegisterName(unsigned RegNo) { assert(RegNo && RegNo < 160 && "Invalid register number!"); static const unsigned RegAsmOffset[] = { 0, 3, 6, 9, 12, 15, 18, 22, 25, 28, 31, 35, 39, 43, 47, 51, 55, 59, 63, 67, 71, 76, 81, 86, 91, 96, 101, 104, 107, 110, 113, 117, 120, 124, 128, 132, 136, 140, 144, 148, 152, 155, 158, 162, 166, 170, 174, 178, 182, 188, 192, 196, 199, 203, 207, 211, 215, 219, 223, 227, 231, 235, 238, 241, 244, 248, 252, 256, 260, 264, 268, 272, 276, 279, 283, 287, 291, 294, 298, 302, 306, 310, 315, 320, 325, 329, 334, 339, 344, 348, 353, 358, 363, 367, 372, 377, 382, 386, 391, 396, 401, 405, 410, 415, 420, 424, 428, 432, 436, 440, 444, 448, 452, 456, 460, 463, 467, 470, 474, 477, 483, 489, 495, 501, 507, 513, 519, 525, 530, 535, 540, 545, 550, 555, 560, 565, 570, 575, 581, 587, 593, 599, 605, 611, 616, 621, 626, 631, 636, 641, 646, 651, 656, 661, 667, 673, 679, 685, 691, 0 }; const char *AsmStrs = "ah\000al\000ax\000bh\000bl\000bp\000bpl\000bx\000ch\000cl\000cr0\000cr1" "\000cr2\000cr3\000cr4\000cr5\000cr6\000cr7\000cr8\000cr9\000cr10\000cr1" "1\000cr12\000cr13\000cr14\000cr15\000cs\000cx\000dh\000di\000dil\000dl\000" "dr0\000dr1\000dr2\000dr3\000dr4\000dr5\000dr6\000dr7\000ds\000dx\000eax" "\000ebp\000ebx\000ecx\000edi\000edx\000flags\000eip\000eiz\000es\000esi" "\000esp\000fp0\000fp1\000fp2\000fp3\000fp4\000fp5\000fp6\000fs\000gs\000" "ip\000mm0\000mm1\000mm2\000mm3\000mm4\000mm5\000mm6\000mm7\000r8\000r8b" "\000r8d\000r8w\000r9\000r9b\000r9d\000r9w\000r10\000r10b\000r10d\000r10" "w\000r11\000r11b\000r11d\000r11w\000r12\000r12b\000r12d\000r12w\000r13\000" "r13b\000r13d\000r13w\000r14\000r14b\000r14d\000r14w\000r15\000r15b\000r" "15d\000r15w\000rax\000rbp\000rbx\000rcx\000rdi\000rdx\000rip\000riz\000" "rsi\000rsp\000si\000sil\000sp\000spl\000ss\000st(0)\000st(1)\000st(2)\000" "st(3)\000st(4)\000st(5)\000st(6)\000st(7)\000xmm0\000xmm1\000xmm2\000xm" "m3\000xmm4\000xmm5\000xmm6\000xmm7\000xmm8\000xmm9\000xmm10\000xmm11\000" "xmm12\000xmm13\000xmm14\000xmm15\000ymm0\000ymm1\000ymm2\000ymm3\000ymm" "4\000ymm5\000ymm6\000ymm7\000ymm8\000ymm9\000ymm10\000ymm11\000ymm12\000" "ymm13\000ymm14\000ymm15\000"; assert (*(AsmStrs+RegAsmOffset[RegNo-1]) && "Invalid alt name index for register!"); return AsmStrs+RegAsmOffset[RegNo-1]; } ==================================================================== any ideas? Thanks to chapuni who helped with investigation. From pichet2000 at gmail.com Wed Jun 29 03:58:42 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Wed, 29 Jun 2011 04:58:42 -0400 Subject: [llvm-commits] [llvm] r133708 - in /llvm/trunk: include/llvm/ include/llvm/Support/ lib/MC/ lib/Target/CppBackend/ lib/Transforms/Scalar/ lib/Transforms/Utils/ lib/VMCore/ In-Reply-To: References: <20110623090916.87EFD2A6C12C@llvm.org> Message-ID: BTW, the stall test is gone since this morning. I can't reproduce it anymore. On Mon, Jun 27, 2011 at 9:14 AM, Francois Pichet wrote: > On Mon, Jun 27, 2011 at 4:10 AM, Jay Foad wrote: >> On 27 June 2011 00:57, Francois Pichet wrote: >>> On Thu, Jun 23, 2011 at 5:09 AM, Jay Foad wrote: >>>> Author: foad >>>> Date: Thu Jun 23 04:09:15 2011 >>>> New Revision: 133708 >>>> >>>> URL: http://llvm.org/viewvc/llvm-project?rev=133708&view=rev >>>> Log: >>>> Reinstate r133513 (reverted in r133700) with an additional fix for a >>>> -Wshorten-64-to-32 warning in Instructions.h. >>> >>> Hi Jay, This commit creates a very weird problem on MSVC where clang >>> test /CodeGen/vla.c stalls in release mode. (but not in debug). >>> >>> I suspect a subtle memory corruption issue that doesn't show up on the >>> various unixes system because we get lucky. Windows .exe are generally >>> easier to crash if there is a memory corruption issue. >> >> Hi Francois, >> >> I've tried running that test under valgrind on Linux, but it doesn't >> show anything. >> >> I'll try building on Windows. What version of MSVC are you using? 32 >> or 64 bit? Do you do a Release or Release+Asserts build? Do you use >> cmake? >> > > I can reproduce the problem with MSVC2010 SP1 and MSVC 2008. > Targeting win32, Release without assert, with cmake. (cmake is > mandatory if you use MSVC). > > > on msvc 2010 CodeGen/vla.c is stuck > on msvc 2008 CodeGenObjC/arc.m > > If I run the tests from the command line instead of from VisualStudio > I get a different test who is stuck but the failing test is always > within clang/test/CodeGen*/* > > You have to run all the tests to get the failure. Individual run will pass. > From aggarwa4 at illinois.edu Wed Jun 29 04:19:12 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 29 Jun 2011 09:19:12 -0000 Subject: [llvm-commits] [poolalloc] r134061 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110629091912.D24AC2A6C12C@llvm.org> Author: aggarwa4 Date: Wed Jun 29 04:19:12 2011 New Revision: 134061 URL: http://llvm.org/viewvc/llvm-project?rev=134061&view=rev Log: Track more library functions. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=134061&r1=134060&r2=134061&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Wed Jun 29 04:19:12 2011 @@ -1562,6 +1562,15 @@ Constant *F = M.getOrInsertFunction("trackgetpwuid", VoidTy, VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); + } else if (F->getNameStr() == std::string("getpwnam")) { + CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy); + BCI->insertAfter(I); + std::vectorArgs; + Args.push_back(BCI); + Args.push_back(getTagCounter()); + Constant *F = M.getOrInsertFunction("trackgetpwuid", VoidTy, VoidPtrTy, Int32Ty, NULL); + CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); + CI->insertAfter(BCI); } else if (F->getNameStr() == std::string("getgruid") || F->getNameStr() == std::string("getgrnam") || F->getNameStr() == std::string("getpwnam") || @@ -1693,8 +1702,26 @@ Args.push_back(getTagCounter()); Constant *F = M.getOrInsertFunction("trackStrncpyInst", VoidTy, VoidPtrTy, VoidPtrTy, I->getOperand(3)->getType(), Int32Ty, NULL); CallInst::Create(F, Args.begin(), Args.end(), "", I); - } else if(F->getNameStr() == std::string("ftime") || - F->getNameStr() == std::string("gettimeofday")) { + } else if (F->getNameStr() == std::string("readlink")) { + std::vectorArgs; + Args.push_back(CS.getArgument(1)); + Args.push_back(I); + Args.push_back(getTagCounter()); + CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); + CI->insertAfter(I); + } else if (F->getNameStr() == std::string("localtime")) { + CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy); + BCI->insertAfter(I); + const PointerType *PTy = cast(I->getType()); + const Type * ElementType = PTy->getElementType(); + std::vectorArgs; + Args.push_back(BCI); + Args.push_back(getSizeConstant(ElementType)); + Args.push_back(getTagCounter()); + CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); + CI->insertAfter(BCI); + } else if (F->getNameStr() == std::string("ftime") || + F->getNameStr() == std::string("gettimeofday")) { CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I); const PointerType *PTy = cast(CS.getArgument(0)->getType()); const Type * ElementType = PTy->getElementType(); @@ -1948,17 +1975,21 @@ Args.push_back(BCI); Args.push_back(getTagCounter()); if(StoreInst *SI = dyn_cast(II)) { - // Cast the pointer operand to i8* for the runtime function. - CastInst *BCI_Dest = BitCastInst::CreatePointerCast(SI->getPointerOperand(), VoidPtrTy, "", SI); - - std::vector Args; - Args.push_back(BCI_Dest); - Args.push_back(AI); - Args.push_back(getSizeConstant(SI->getOperand(0)->getType())); - Args.push_back(getTypeMarkerConstant(SI->getOperand(0)->getType())); - Args.push_back(getTagCounter()); - // Create the call to the runtime check and place it before the copying store instruction. - CallInst::Create(setTypeInfo, Args.begin(), Args.end(), "", SI); + if(SI->getOperand(0) == I) { + // Cast the pointer operand to i8* for the runtime function. + CastInst *BCI_Dest = BitCastInst::CreatePointerCast(SI->getPointerOperand(), VoidPtrTy, "", SI); + + std::vector Args; + Args.push_back(BCI_Dest); + Args.push_back(AI); + Args.push_back(getSizeConstant(SI->getOperand(0)->getType())); + Args.push_back(getTypeMarkerConstant(SI->getOperand(0)->getType())); + Args.push_back(getTagCounter()); + // Create the call to the runtime check and place it before the copying store instruction. + CallInst::Create(setTypeInfo, Args.begin(), Args.end(), "", SI); + } else { + CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", cast(II.getUse().getUser())); + } } else if(SelectInst *SelI = dyn_cast(II)) { SelectInst *Prev = NULL; SelectInst *PrevBasePtr = NULL; From aggarwa4 at illinois.edu Wed Jun 29 04:49:10 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 29 Jun 2011 09:49:10 -0000 Subject: [llvm-commits] [poolalloc] r134062 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Message-ID: <20110629094910.903142A6C12D@llvm.org> Author: aggarwa4 Date: Wed Jun 29 04:49:10 2011 New Revision: 134062 URL: http://llvm.org/viewvc/llvm-project?rev=134062&view=rev Log: Fix base. Fix off by one error. Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=134062&r1=134061&r2=134062&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Wed Jun 29 04:49:10 2011 @@ -27,7 +27,7 @@ * For now, run a version of the tool without the base fixed, and * choose address. */ -#define BASE ((TypeTagTy *)(0x2aaaab88c000)) +#define BASE ((TypeTagTy *)(0x2aaaac01e000)) /* * Do some macro magic to get mmap macros defined properly on all platforms. */ @@ -129,7 +129,7 @@ int index = 0; for(;envp[index] != NULL; ++index) trackInitInst(envp[index], (strlen(envp[index]) + 1)*sizeof(char), 0); - trackInitInst(envp, (index )*sizeof(char*), 0); + trackInitInst(envp, (index+1)*sizeof(char*), 0); } /** From aggarwa4 at illinois.edu Wed Jun 29 05:28:53 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 29 Jun 2011 10:28:53 -0000 Subject: [llvm-commits] [poolalloc] r134063 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110629102853.5DC352A6C12C@llvm.org> Author: aggarwa4 Date: Wed Jun 29 05:28:53 2011 New Revision: 134063 URL: http://llvm.org/viewvc/llvm-project?rev=134063&view=rev Log: Add support for library functions used by thttpd, in the hope of removing some false positives, to reveal possible real errors. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=134063&r1=134062&r2=134063&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Wed Jun 29 05:28:53 2011 @@ -1614,10 +1614,20 @@ Constant *F = M.getOrInsertFunction("trackgetcwd", VoidTy, VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); + } else if(F->getNameStr() == std::string("crypt")) { + CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy); + BCI->insertAfter(I); + std::vectorArgs; + Args.push_back(BCI); + Args.push_back(getTagCounter()); + Constant *F = M.getOrInsertFunction("trackgetcwd", VoidTy, VoidPtrTy, Int32Ty, NULL); + CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); + CI->insertAfter(BCI); } else if (F->getNameStr() == std::string("getrusage") || F->getNameStr() == std::string("getrlimit") || F->getNameStr() == std::string("stat") || - F->getNameStr() == std::string("fstat")) { + F->getNameStr() == std::string("fstat") || + F->getNameStr() == std::string("lstat")) { CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy, "", I); assert (isa(CS.getArgument(1)->getType())); const PointerType * PT = cast(CS.getArgument(1)->getType()); @@ -1709,7 +1719,30 @@ Args.push_back(getTagCounter()); CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); CI->insertAfter(I); - } else if (F->getNameStr() == std::string("localtime")) { + } else if (F->getNameStr() == std::string("getsockname")) { + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy, "", I); + const PointerType *PTy = cast(CS.getArgument(1)->getType()); + const Type * ElementType = PTy->getElementType(); + std::vector Args; + Args.push_back(BCI); + Args.push_back(getSizeConstant(ElementType)); + Args.push_back(getTagCounter()); + CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); + return true; + } else if (F->getNameStr() == std::string("readdir")) { + CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy); + BCI->insertAfter(I); + const PointerType *PTy = cast(I->getType()); + const Type * ElementType = PTy->getElementType(); + std::vectorArgs; + Args.push_back(BCI); + Args.push_back(getSizeConstant(ElementType)); + Args.push_back(getTagCounter()); + CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); + CI->insertAfter(BCI); + return true; + } else if (F->getNameStr() == std::string("localtime") || + F->getNameStr() == std::string("gmtime")) { CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy); BCI->insertAfter(I); const PointerType *PTy = cast(I->getType()); @@ -1799,6 +1832,15 @@ Args.push_back(getTagCounter()); CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I); return true; + } else if(F->getNameStr() == std::string("snprintf") || + F->getNameStr() == std::string("vsnprintf")) { + CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I); + std::vectorArgs; + Args.push_back(BCI); + Args.push_back(getTagCounter()); + Constant *F = M.getOrInsertFunction("trackgetcwd", VoidTy, VoidPtrTy, Int32Ty, NULL); + CallInst *CINew = CallInst::Create(F, Args.begin(), Args.end()); + CINew->insertAfter(I); } else if(F->getNameStr() == std::string("sprintf")) { CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I); std::vectorArgs; From pichet2000 at gmail.com Wed Jun 29 06:25:34 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Wed, 29 Jun 2011 11:25:34 -0000 Subject: [llvm-commits] [llvm] r134064 - /llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Message-ID: <20110629112534.632A62A6C12C@llvm.org> Author: fpichet Date: Wed Jun 29 06:25:34 2011 New Revision: 134064 URL: http://llvm.org/viewvc/llvm-project?rev=134064&view=rev Log: Change AsmName's type from StringRef to std::string. AsmName was pointing to a temporary string object that was destroyed. This is undefined behavior and MSVC didn't like it. This fixes over 300+ failing tests on MSVC. Credit for this fix goes to chapuni. Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Modified: llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp?rev=134064&r1=134063&r2=134064&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp Wed Jun 29 06:25:34 2011 @@ -467,7 +467,7 @@ for (unsigned i = 0, e = Registers.size(); i != e; ++i) { const CodeGenRegister &Reg = *Registers[i]; - StringRef AsmName; + std::string AsmName; // "NoRegAltName" is special. We don't need to do a lookup for that, // as it's just a reference to the default register name. if (AltName == "" || AltName == "NoRegAltName") { From pichet2000 at gmail.com Wed Jun 29 06:29:03 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Wed, 29 Jun 2011 07:29:03 -0400 Subject: [llvm-commits] [llvm] r133940 - in /llvm/trunk: include/llvm/Target/ utils/TableGen/ In-Reply-To: References: <20110627210622.127C32A6C12C@llvm.org> Message-ID: On Wed, Jun 29, 2011 at 4:56 AM, Francois Pichet wrote: > On Mon, Jun 27, 2011 at 5:06 PM, Owen Anderson wrote: >> Author: resistor >> Date: Mon Jun 27 16:06:21 2011 >> New Revision: 133940 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=133940&view=rev >> Log: >> Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. ?For example, an instruciton that prints d0[0] instead of s0. >> Patch by Jim Grosbach. >> >> Modified: >> ? ?llvm/trunk/include/llvm/Target/Target.td >> ? ?llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp >> ? ?llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp >> ? ?llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >> ? ?llvm/trunk/utils/TableGen/CodeGenInstruction.cpp >> ? ?llvm/trunk/utils/TableGen/CodeGenTarget.cpp >> ? ?llvm/trunk/utils/TableGen/CodeGenTarget.h >> ? ?llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp >> ? ?llvm/trunk/utils/TableGen/FastISelEmitter.cpp >> ? ?llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp >> ? ?llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp >> ? ?llvm/trunk/utils/TableGen/Record.cpp >> ? ?llvm/trunk/utils/TableGen/Record.h >> ? ?llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp >> > > I am not sure if this commit is to blame but it seems to be the most probable. > There is a huge regression on MSVC since last Monday with over 300 > failing tests. > > Seems like X86GenAsmWriter.inc is generated with some invalid data on MSVC. > I copied X86GenAsmWriter.inc from my Mac to my PC and the failing test > went from 300+ to only 4. > > So I did a diff between X86GenAsmWriter.inc (PC and Mac) and I saw > some difference in X86ATTInstPrinter::getRegisterName() > Ok see r134064 for the fix. The problem was a StringRef pointing to a temporary that was destroyed. As in: std::string AsmName; AsmName = Reg.TheDef->getValueAsString("AsmName"); Thanks to chapuni who helped to find this problem with me on the IRC channel. Now we get 100% pass rate for the llvm tests on MSVC again. From pichet2000 at gmail.com Wed Jun 29 07:57:33 2011 From: pichet2000 at gmail.com (Francois Pichet) Date: Wed, 29 Jun 2011 08:57:33 -0400 Subject: [llvm-commits] [llvm] r133940 - in /llvm/trunk: include/llvm/Target/ utils/TableGen/ In-Reply-To: References: <20110627210622.127C32A6C12C@llvm.org> Message-ID: On Wed, Jun 29, 2011 at 7:29 AM, Francois Pichet wrote: > On Wed, Jun 29, 2011 at 4:56 AM, Francois Pichet wrote: >> On Mon, Jun 27, 2011 at 5:06 PM, Owen Anderson wrote: >>> Author: resistor >>> Date: Mon Jun 27 16:06:21 2011 >>> New Revision: 133940 >>> >>> URL: http://llvm.org/viewvc/llvm-project?rev=133940&view=rev >>> Log: >>> Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. ?For example, an instruciton that prints d0[0] instead of s0. >>> Patch by Jim Grosbach. >>> >>> Modified: >>> ? ?llvm/trunk/include/llvm/Target/Target.td >>> ? ?llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp >>> ? ?llvm/trunk/utils/TableGen/AsmWriterEmitter.cpp >>> ? ?llvm/trunk/utils/TableGen/CodeGenDAGPatterns.cpp >>> ? ?llvm/trunk/utils/TableGen/CodeGenInstruction.cpp >>> ? ?llvm/trunk/utils/TableGen/CodeGenTarget.cpp >>> ? ?llvm/trunk/utils/TableGen/CodeGenTarget.h >>> ? ?llvm/trunk/utils/TableGen/DAGISelMatcherGen.cpp >>> ? ?llvm/trunk/utils/TableGen/FastISelEmitter.cpp >>> ? ?llvm/trunk/utils/TableGen/FixedLenDecoderEmitter.cpp >>> ? ?llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp >>> ? ?llvm/trunk/utils/TableGen/Record.cpp >>> ? ?llvm/trunk/utils/TableGen/Record.h >>> ? ?llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp >>> >> >> I am not sure if this commit is to blame but it seems to be the most probable. >> There is a huge regression on MSVC since last Monday with over 300 >> failing tests. >> >> Seems like X86GenAsmWriter.inc is generated with some invalid data on MSVC. >> I copied X86GenAsmWriter.inc from my Mac to my PC and the failing test >> went from 300+ to only 4. >> >> So I did a diff between X86GenAsmWriter.inc (PC and Mac) and I saw >> some difference in X86ATTInstPrinter::getRegisterName() >> > > Ok see r134064 for the fix. The problem was a StringRef pointing to a > temporary that was destroyed. > As in: > ? ?std::string AsmName; > ? ?AsmName = Reg.TheDef->getValueAsString("AsmName"); of course I meant: ? ?StringRef AsmName; ? ?AsmName = Reg.TheDef->getValueAsString("AsmName"); // do stuff with AsmName later: wrong the temporary is destroyed. From benny.kra at googlemail.com Wed Jun 29 08:47:25 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 29 Jun 2011 13:47:25 -0000 Subject: [llvm-commits] [llvm] r134067 - in /llvm/trunk: lib/CodeGen/SelectionDAG/DAGCombiner.cpp test/CodeGen/X86/adde-carry.ll Message-ID: <20110629134725.A7A072A6C12C@llvm.org> Author: d0k Date: Wed Jun 29 08:47:25 2011 New Revision: 134067 URL: http://llvm.org/viewvc/llvm-project?rev=134067&view=rev Log: Revert a part of r126557 which could create unschedulable DAGs. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp llvm/trunk/test/CodeGen/X86/adde-carry.ll Modified: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp?rev=134067&r1=134066&r2=134067&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp Wed Jun 29 08:47:25 2011 @@ -1310,16 +1310,6 @@ return SDValue(); } -/// isCarryMaterialization - Returns true if V is an ADDE node that is known to -/// return 0 or 1 depending on the carry flag. -static bool isCarryMaterialization(SDValue V) { - if (V.getOpcode() != ISD::ADDE) - return false; - - ConstantSDNode *C = dyn_cast(V.getOperand(0)); - return C && C->isNullValue() && V.getOperand(0) == V.getOperand(1); -} - SDValue DAGCombiner::visitADD(SDNode *N) { SDValue N0 = N->getOperand(0); SDValue N1 = N->getOperand(1); @@ -1483,18 +1473,6 @@ return DAG.getNode(ISD::SUB, DL, VT, N1, ZExt); } - // add (adde 0, 0, glue), X -> adde X, 0, glue - if (N0->hasOneUse() && isCarryMaterialization(N0)) - return DAG.getNode(ISD::ADDE, N->getDebugLoc(), - DAG.getVTList(VT, MVT::Glue), N1, N0.getOperand(0), - N0.getOperand(2)); - - // add X, (adde 0, 0, glue) -> adde X, 0, glue - if (N1->hasOneUse() && isCarryMaterialization(N1)) - return DAG.getNode(ISD::ADDE, N->getDebugLoc(), - DAG.getVTList(VT, MVT::Glue), N0, N1.getOperand(0), - N1.getOperand(2)); - return SDValue(); } @@ -1538,16 +1516,6 @@ N->getDebugLoc(), MVT::Glue)); } - // addc (adde 0, 0, glue), X -> adde X, 0, glue - if (N0->hasOneUse() && isCarryMaterialization(N0)) - return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N1, - DAG.getConstant(0, VT), N0.getOperand(2)); - - // addc X, (adde 0, 0, glue) -> adde X, 0, glue - if (N1->hasOneUse() && isCarryMaterialization(N1)) - return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), N0, - DAG.getConstant(0, VT), N1.getOperand(2)); - return SDValue(); } Modified: llvm/trunk/test/CodeGen/X86/adde-carry.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/adde-carry.ll?rev=134067&r1=134066&r2=134067&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/X86/adde-carry.ll (original) +++ llvm/trunk/test/CodeGen/X86/adde-carry.ll Wed Jun 29 08:47:25 2011 @@ -1,5 +1,4 @@ ; RUN: llc -march=x86-64 < %s | FileCheck %s -check-prefix=CHECK-64 -; RUN: llc -march=x86 < %s | FileCheck %s -check-prefix=CHECK-32 define void @a(i64* nocapture %s, i64* nocapture %t, i64 %a, i64 %b, i64 %c) nounwind { entry: @@ -16,11 +15,6 @@ store i64 %8, i64* %t, align 8 ret void -; CHECK-32: addl -; CHECK-32: adcl -; CHECK-32: adcl $0 -; CHECK-32: adcl $0 - ; CHECK-64: addq ; CHECK-64: adcq $0 } From benny.kra at googlemail.com Wed Jun 29 09:07:18 2011 From: benny.kra at googlemail.com (Benjamin Kramer) Date: Wed, 29 Jun 2011 14:07:18 -0000 Subject: [llvm-commits] [llvm] r134068 - in /llvm/trunk/test/CodeGen: ARM/carry.ll Thumb2/thumb2-sbc.ll Message-ID: <20110629140718.4C3482A6C12C@llvm.org> Author: d0k Date: Wed Jun 29 09:07:18 2011 New Revision: 134068 URL: http://llvm.org/viewvc/llvm-project?rev=134068&view=rev Log: Don't depend on the optimization reverted in r134067. Modified: llvm/trunk/test/CodeGen/ARM/carry.ll llvm/trunk/test/CodeGen/Thumb2/thumb2-sbc.ll Modified: llvm/trunk/test/CodeGen/ARM/carry.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/carry.ll?rev=134068&r1=134067&r2=134068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/ARM/carry.ll (original) +++ llvm/trunk/test/CodeGen/ARM/carry.ll Wed Jun 29 09:07:18 2011 @@ -24,7 +24,6 @@ define i64 @f3(i32 %al, i32 %bl) { ; CHECK: f3: ; CHECK: adds r -; CHECK: adcs r ; CHECK: adc r entry: ; unsigned wide add Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-sbc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-sbc.ll?rev=134068&r1=134067&r2=134068&view=diff ============================================================================== --- llvm/trunk/test/CodeGen/Thumb2/thumb2-sbc.ll (original) +++ llvm/trunk/test/CodeGen/Thumb2/thumb2-sbc.ll Wed Jun 29 09:07:18 2011 @@ -56,7 +56,6 @@ ; ; CHECK: livecarry: ; CHECK: adds -; CHECK: adcs ; CHECK: adc define i64 @livecarry(i64 %carry, i32 %digit) nounwind { %ch = lshr i64 %carry, 32 From grosbach at apple.com Wed Jun 29 11:05:14 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 29 Jun 2011 16:05:14 -0000 Subject: [llvm-commits] [llvm] r134069 - in /llvm/trunk: lib/MC/MCParser/AsmParser.cpp test/MC/AsmParser/exprs-invalid.s Message-ID: <20110629160514.F05862A6C12C@llvm.org> Author: grosbach Date: Wed Jun 29 11:05:14 2011 New Revision: 134069 URL: http://llvm.org/viewvc/llvm-project?rev=134069&view=rev Log: Asm parser range checking on . directives. For example, ".byte 256" would previously assert() when emitting an object file. Now it generates a diagnostic that the literal value is out of range. rdar://9686950 Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp llvm/trunk/test/MC/AsmParser/exprs-invalid.s Modified: llvm/trunk/lib/MC/MCParser/AsmParser.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCParser/AsmParser.cpp?rev=134069&r1=134068&r2=134069&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCParser/AsmParser.cpp (original) +++ llvm/trunk/lib/MC/MCParser/AsmParser.cpp Wed Jun 29 11:05:14 2011 @@ -28,6 +28,7 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/MC/MCDwarf.h" #include "llvm/Support/CommandLine.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/MemoryBuffer.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/raw_ostream.h" @@ -1612,13 +1613,18 @@ for (;;) { const MCExpr *Value; + SMLoc ExprLoc = getLexer().getLoc(); if (ParseExpression(Value)) return true; // Special case constant expressions to match code generator. - if (const MCConstantExpr *MCE = dyn_cast(Value)) - getStreamer().EmitIntValue(MCE->getValue(), Size, DEFAULT_ADDRSPACE); - else + if (const MCConstantExpr *MCE = dyn_cast(Value)) { + assert(Size <= 8 && "Invalid size"); + uint64_t IntValue = MCE->getValue(); + if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) + return Error(ExprLoc, "literal value out of range for directive"); + getStreamer().EmitIntValue(IntValue, Size, DEFAULT_ADDRSPACE); + } else getStreamer().EmitValue(Value, Size, DEFAULT_ADDRSPACE); if (getLexer().is(AsmToken::EndOfStatement)) Modified: llvm/trunk/test/MC/AsmParser/exprs-invalid.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AsmParser/exprs-invalid.s?rev=134069&r1=134068&r2=134069&view=diff ============================================================================== --- llvm/trunk/test/MC/AsmParser/exprs-invalid.s (original) +++ llvm/trunk/test/MC/AsmParser/exprs-invalid.s Wed Jun 29 11:05:14 2011 @@ -6,3 +6,9 @@ // CHECK-ERRORS: error: invalid hexadecimal number .long 80+0xzz + +// CHECK-ERRORS: error: literal value out of range for directive +.byte 256 + +// CHECK-ERRORS: error: literal value out of range for directive +.long 4e71cf69 // double floating point constant due to missing "0x" From mcrosier at apple.com Wed Jun 29 11:22:11 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 29 Jun 2011 16:22:11 -0000 Subject: [llvm-commits] [llvm] r134071 - in /llvm/trunk: include/llvm/BasicBlock.h lib/Transforms/Utils/Local.cpp lib/Transforms/Utils/SimplifyCFG.cpp lib/VMCore/BasicBlock.cpp test/Transforms/SimplifyCFG/lifetime.ll Message-ID: <20110629162211.4985F2A6C12C@llvm.org> Author: mcrosier Date: Wed Jun 29 11:22:11 2011 New Revision: 134071 URL: http://llvm.org/viewvc/llvm-project?rev=134071&view=rev Log: Temporarily revert r134057: "Let simplify cfg simplify bb with only debug and lifetime intrinsics" due to buildbot failures. Removed: llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll Modified: llvm/trunk/include/llvm/BasicBlock.h llvm/trunk/lib/Transforms/Utils/Local.cpp llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp llvm/trunk/lib/VMCore/BasicBlock.cpp Modified: llvm/trunk/include/llvm/BasicBlock.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BasicBlock.h?rev=134071&r1=134070&r2=134071&view=diff ============================================================================== --- llvm/trunk/include/llvm/BasicBlock.h (original) +++ llvm/trunk/include/llvm/BasicBlock.h Wed Jun 29 11:22:11 2011 @@ -138,12 +138,6 @@ return const_cast(this)->getFirstNonPHIOrDbg(); } - // Same as above, but also skip lifetime intrinsics. - Instruction* getFirstNonPHIOrDbgOrLifetime(); - const Instruction* getFirstNonPHIOrDbgOrLifetime() const { - return const_cast(this)->getFirstNonPHIOrDbgOrLifetime(); - } - /// removeFromParent - This method unlinks 'this' from the containing /// function, but does not delete it. /// Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=134071&r1=134070&r2=134071&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Wed Jun 29 11:22:11 2011 @@ -536,9 +536,9 @@ /// TryToSimplifyUncondBranchFromEmptyBlock - BB is known to contain an /// unconditional branch, and contains no instructions other than PHI nodes, -/// potential side-effect free intrinsics and the branch. If possible, -/// eliminate BB by rewriting all the predecessors to branch to the successor -/// block and return true. If we can't transform, return false. +/// potential debug intrinsics and the branch. If possible, eliminate BB by +/// rewriting all the predecessors to branch to the successor block and return +/// true. If we can't transform, return false. bool llvm::TryToSimplifyUncondBranchFromEmptyBlock(BasicBlock *BB) { assert(BB != &BB->getParent()->getEntryBlock() && "TryToSimplifyUncondBranchFromEmptyBlock called on entry block!"); @@ -613,15 +613,13 @@ } } - if (Succ->getSinglePredecessor()) { - // BB is the only predecessor of Succ, so Succ will end up with exactly - // the same predecessors BB had. - - // Copy over any phi, debug or lifetime instruction. - BB->getTerminator()->eraseFromParent(); - Succ->getInstList().splice(Succ->begin(), BB->getInstList()); - } else { - while (PHINode *PN = dyn_cast(&BB->front())) { + while (PHINode *PN = dyn_cast(&BB->front())) { + if (Succ->getSinglePredecessor()) { + // BB is the only predecessor of Succ, so Succ will end up with exactly + // the same predecessors BB had. + Succ->getInstList().splice(Succ->begin(), + BB->getInstList(), BB->begin()); + } else { // We explicitly check for such uses in CanPropagatePredecessorsForPHIs. assert(PN->use_empty() && "There shouldn't be any uses here!"); PN->eraseFromParent(); Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=134071&r1=134070&r2=134071&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed Jun 29 11:22:11 2011 @@ -2604,7 +2604,7 @@ BasicBlock *BB = BI->getParent(); // If the Terminator is the only non-phi instruction, simplify the block. - BasicBlock::iterator I = BB->getFirstNonPHIOrDbgOrLifetime(); + BasicBlock::iterator I = BB->getFirstNonPHIOrDbg(); if (I->isTerminator() && BB != &BB->getParent()->getEntryBlock() && TryToSimplifyUncondBranchFromEmptyBlock(BB)) return true; Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=134071&r1=134070&r2=134071&view=diff ============================================================================== --- llvm/trunk/lib/VMCore/BasicBlock.cpp (original) +++ llvm/trunk/lib/VMCore/BasicBlock.cpp Wed Jun 29 11:22:11 2011 @@ -147,26 +147,6 @@ return &*i; } -Instruction* BasicBlock::getFirstNonPHIOrDbgOrLifetime() { - // All valid basic blocks should have a terminator, - // which is not a PHINode. If we have an invalid basic - // block we'll get an assertion failure when dereferencing - // a past-the-end iterator. - BasicBlock::iterator i = begin(); - for (;; ++i) { - if (isa(i) || isa(i)) - continue; - - const IntrinsicInst *II = dyn_cast(i); - if (!II) - break; - if (II->getIntrinsicID() != Intrinsic::lifetime_start && - II->getIntrinsicID() != Intrinsic::lifetime_end) - break; - } - return &*i; -} - void BasicBlock::dropAllReferences() { for(iterator I = begin(), E = end(); I != E; ++I) I->dropAllReferences(); Removed: llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll?rev=134070&view=auto ============================================================================== --- llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll (original) +++ llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll (removed) @@ -1,29 +0,0 @@ -; RUN: opt < %s -simplifycfg -S | FileCheck %s - -; Test that a lifetime intrinsic doesn't prevent us from simplifying this. - -; CHECK: foo -; CHECK: entry: -; CHECK-NOT: bb0: -; CHECK-NOT: bb1: -; CHECK: ret -define void @foo(i1 %x) { -entry: - %a = alloca i8 - call void @llvm.lifetime.start(i64 -1, i8* %a) nounwind - br i1 %x, label %bb0, label %bb1 - -bb0: - call void @llvm.lifetime.end(i64 -1, i8* %a) nounwind - br label %bb1 - -bb1: - call void @f() - ret void -} - -declare void @f() - -declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind - -declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind From mcrosier at apple.com Wed Jun 29 11:36:04 2011 From: mcrosier at apple.com (Chad Rosier) Date: Wed, 29 Jun 2011 09:36:04 -0700 Subject: [llvm-commits] [llvm] r134057 - in /llvm/trunk: include/llvm/BasicBlock.h lib/Transforms/Utils/Local.cpp lib/Transforms/Utils/SimplifyCFG.cpp lib/VMCore/BasicBlock.cpp test/Transforms/SimplifyCFG/lifetime.ll In-Reply-To: <20110629052547.DB3E92A6C12C@llvm.org> References: <20110629052547.DB3E92A6C12C@llvm.org> Message-ID: Hi Rafael, I've reverted this in r134071 due to in internal buildbot failure. Specifically, clang is failing to build due to a segmentation fault. I'm thinking it's a potential miscompile, but would you mind taking a look? Here's the error: llvm[3]: Compiling DebugInfo.cpp for Release build 0 clang 0x0000000100e65fc2 PrintStackTrace(void*) + 34 1 clang 0x00000001003104d9 SignalHandler(int) + 697 2 libSystem.B.dylib 0x00007fff806fd66a _sigtramp + 26 3 libSystem.B.dylib 0x000000010270dde0 _sigtramp + 2181105552 4 clang 0x00000001001db78b llvm::LazyValueInfo::getConstantOnEdge(llvm::Value*, llvm::BasicBlock*, llvm::BasicBlock*) + 91 5 clang 0x00000001001c8468 (anonymous namespace)::CorrelatedValuePropagation::runOnFunction(llvm::Function&) + 808 6 clang 0x0000000100090fc1 llvm::FPPassManager::runOnFunction(llvm::Function&) + 321 7 clang 0x000000010008b7c2 (anonymous namespace)::CGPassManager::runOnModule(llvm::Module&) + 1490 8 clang 0x0000000100089af6 llvm::MPPassManager::runOnModule(llvm::Module&) + 294 9 clang 0x0000000100089237 llvm::PassManagerImpl::run(llvm::Module&) + 279 10 clang 0x000000010008910d llvm::PassManager::run(llvm::Module&) + 13 11 clang 0x00000001003f6f6b clang::EmitBackendOutput(clang::Diagnostic&, clang::CodeGenOptions const&, clang::TargetOptions const&, llvm::Module*, clang::BackendAction, llvm::raw_ostream*) + 4411 12 clang 0x00000001004abcb5 clang::BackendConsumer::HandleTranslationUnit(clang::ASTContext&) + 261 13 clang 0x000000010003ee77 clang::ParseAST(clang::Sema&, bool) + 407 14 clang 0x000000010003e05e clang::CodeGenAction::ExecuteAction() + 686 15 clang 0x0000000100019c6a clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) + 858 16 clang 0x0000000100019848 clang::ExecuteCompilerInvocation(clang::CompilerInstance*) + 2648 17 clang 0x0000000100013efb cc1_main(char const**, char const**, char const*, void*) + 5755 18 clang 0x00000001000033e7 main + 679 19 clang 0x0000000100003134 start + 52 Stack dump: 0. Program arguments: /clang.obj/clang-9999.99.roots/clang-9999.99~obj/stage1-install-x86_64/bin/clang -cc1 -triple i386-apple-macosx10.6.0 -emit-obj -disable-free -disable-llvm-verifier -main-file-name AsmPrinterDwarf.cpp -pic-level 1 -mdisable-fp-elim -relaxed-aliasing -masm-verbose -target-cpu yonah -target-linker-version 123.2 -g -coverage-file /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/lib/CodeGen/AsmPrinter/Release/AsmPrinterDwarf.o -resource-dir /clang.obj/clang-9999.99.roots/clang-9999.99~obj/stage1-install-x86_64/bin/../lib/clang/3.0 -dependency-file /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/lib/CodeGen/AsmPrinter/Release/AsmPrinterDwarf.d.tmp -MP -MT /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/lib/CodeGen/AsmPrinter/Release/AsmPrinterDwarf.o -MT /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/lib/CodeGen/AsmPrinter/Release/AsmPrinterDwarf.d -D NDEBUG -D _GNU_SOURCE -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -D DISABLE_DEFAULT_STRICT_ALIASING -D DISABLE_ARM_DARWIN_USE_MOVT -I /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/include -I /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/lib/CodeGen/AsmPrinter -I /clang.src/src/include -I /clang.src/src/lib/CodeGen/AsmPrinter -O2 -Woverloaded-virtual -Wcast-qual -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -pedantic -fconst-strings -fdeprecated-macro -ferror-limit 19 -fmessage-length 0 -stack-protector 1 -fblocks -fno-rtti -fno-common -fdiagnostics-show-option -o /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/lib/CodeGen/AsmPrinter/Release/AsmPrinterDwarf.o -x c++ /clang.src/src/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp -dwarf-debug-flags /clang.obj/clang-9999.99.roots/clang-9999.99~obj/stage1-install-x86_64/bin/clang -arch i386 -I /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/include -I /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/lib/CodeGen/AsmPrinter -I /clang.src/src/include -I /clang.src/src/lib/CodeGen/AsmPrinter -D NDEBUG -D _GNU_SOURCE -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -O2 -fno-exceptions -fno-rtti -fno-common -Woverloaded-virtual -Wcast-qual -m32 -pedantic -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -D DISABLE_DEFAULT_STRICT_ALIASING -D DISABLE_ARM_DARWIN_USE_MOVT -g -c -MMD -MP -MF /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/lib/CodeGen/AsmPrinter/Release/AsmPrinterDwarf.d.tmp -MT /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/lib/CodeGen/AsmPrinter/Release/AsmPrinterDwarf.o -MT /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/lib/CodeGen/AsmPrinter/Release/AsmPrinterDwarf.d /clang.src/src/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp -o /clang.obj/clang-9999.99.roots/clang-9999.99~obj/i386/lib/CodeGen/AsmPrinter/Release/AsmPrinterDwarf.o -mlinker-version=123.2 -mtune=core2 -mmacosx-version-min=10.6 1. parser at end of file 2. Per-module optimization passes 3. Running pass 'CallGraph Pass Manager' on module ' /clang.src/src/lib/CodeGen/AsmPrinter/AsmPrinterDwarf.cpp'. 4. Running pass 'Value Propagation' on function '@_ZNK4llvm10AsmPrinter16EmitEncodingByteEjPKc' clang: error: unable to execute command: Segmentation fault clang: error: clang frontend command failed due to signal 2 (use -v to see invocation) Chad On Jun 28, 2011, at 10:25 PM, Rafael Espindola wrote: > Author: rafael > Date: Wed Jun 29 00:25:47 2011 > New Revision: 134057 > > URL: http://llvm.org/viewvc/llvm-project?rev=134057&view=rev > Log: > Let simplify cfg simplify bb with only debug and lifetime intrinsics. > > Added: > llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll > Modified: > llvm/trunk/include/llvm/BasicBlock.h > llvm/trunk/lib/Transforms/Utils/Local.cpp > llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp > llvm/trunk/lib/VMCore/BasicBlock.cpp > > Modified: llvm/trunk/include/llvm/BasicBlock.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BasicBlock.h?rev=134057&r1=134056&r2=134057&view=diff > ============================================================================== > --- llvm/trunk/include/llvm/BasicBlock.h (original) > +++ llvm/trunk/include/llvm/BasicBlock.h Wed Jun 29 00:25:47 2011 > @@ -138,6 +138,12 @@ > return const_cast(this)->getFirstNonPHIOrDbg(); > } > > + // Same as above, but also skip lifetime intrinsics. > + Instruction* getFirstNonPHIOrDbgOrLifetime(); > + const Instruction* getFirstNonPHIOrDbgOrLifetime() const { > + return const_cast(this)->getFirstNonPHIOrDbgOrLifetime(); > + } > + > /// removeFromParent - This method unlinks 'this' from the containing > /// function, but does not delete it. > /// > > Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=134057&r1=134056&r2=134057&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/Local.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/Local.cpp Wed Jun 29 00:25:47 2011 > @@ -536,9 +536,9 @@ > > /// TryToSimplifyUncondBranchFromEmptyBlock - BB is known to contain an > /// unconditional branch, and contains no instructions other than PHI nodes, > -/// potential debug intrinsics and the branch. If possible, eliminate BB by > -/// rewriting all the predecessors to branch to the successor block and return > -/// true. If we can't transform, return false. > +/// potential side-effect free intrinsics and the branch. If possible, > +/// eliminate BB by rewriting all the predecessors to branch to the successor > +/// block and return true. If we can't transform, return false. > bool llvm::TryToSimplifyUncondBranchFromEmptyBlock(BasicBlock *BB) { > assert(BB != &BB->getParent()->getEntryBlock() && > "TryToSimplifyUncondBranchFromEmptyBlock called on entry block!"); > @@ -613,13 +613,15 @@ > } > } > > - while (PHINode *PN = dyn_cast(&BB->front())) { > - if (Succ->getSinglePredecessor()) { > - // BB is the only predecessor of Succ, so Succ will end up with exactly > - // the same predecessors BB had. > - Succ->getInstList().splice(Succ->begin(), > - BB->getInstList(), BB->begin()); > - } else { > + if (Succ->getSinglePredecessor()) { > + // BB is the only predecessor of Succ, so Succ will end up with exactly > + // the same predecessors BB had. > + > + // Copy over any phi, debug or lifetime instruction. > + BB->getTerminator()->eraseFromParent(); > + Succ->getInstList().splice(Succ->begin(), BB->getInstList()); > + } else { > + while (PHINode *PN = dyn_cast(&BB->front())) { > // We explicitly check for such uses in CanPropagatePredecessorsForPHIs. > assert(PN->use_empty() && "There shouldn't be any uses here!"); > PN->eraseFromParent(); > > Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=134057&r1=134056&r2=134057&view=diff > ============================================================================== > --- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original) > +++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Wed Jun 29 00:25:47 2011 > @@ -2604,7 +2604,7 @@ > BasicBlock *BB = BI->getParent(); > > // If the Terminator is the only non-phi instruction, simplify the block. > - BasicBlock::iterator I = BB->getFirstNonPHIOrDbg(); > + BasicBlock::iterator I = BB->getFirstNonPHIOrDbgOrLifetime(); > if (I->isTerminator() && BB != &BB->getParent()->getEntryBlock() && > TryToSimplifyUncondBranchFromEmptyBlock(BB)) > return true; > > Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=134057&r1=134056&r2=134057&view=diff > ============================================================================== > --- llvm/trunk/lib/VMCore/BasicBlock.cpp (original) > +++ llvm/trunk/lib/VMCore/BasicBlock.cpp Wed Jun 29 00:25:47 2011 > @@ -147,6 +147,26 @@ > return &*i; > } > > +Instruction* BasicBlock::getFirstNonPHIOrDbgOrLifetime() { > + // All valid basic blocks should have a terminator, > + // which is not a PHINode. If we have an invalid basic > + // block we'll get an assertion failure when dereferencing > + // a past-the-end iterator. > + BasicBlock::iterator i = begin(); > + for (;; ++i) { > + if (isa(i) || isa(i)) > + continue; > + > + const IntrinsicInst *II = dyn_cast(i); > + if (!II) > + break; > + if (II->getIntrinsicID() != Intrinsic::lifetime_start && > + II->getIntrinsicID() != Intrinsic::lifetime_end) > + break; > + } > + return &*i; > +} > + > void BasicBlock::dropAllReferences() { > for(iterator I = begin(), E = end(); I != E; ++I) > I->dropAllReferences(); > > Added: llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll?rev=134057&view=auto > ============================================================================== > --- llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll (added) > +++ llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll Wed Jun 29 00:25:47 2011 > @@ -0,0 +1,29 @@ > +; RUN: opt < %s -simplifycfg -S | FileCheck %s > + > +; Test that a lifetime intrinsic doesn't prevent us from simplifying this. > + > +; CHECK: foo > +; CHECK: entry: > +; CHECK-NOT: bb0: > +; CHECK-NOT: bb1: > +; CHECK: ret > +define void @foo(i1 %x) { > +entry: > + %a = alloca i8 > + call void @llvm.lifetime.start(i64 -1, i8* %a) nounwind > + br i1 %x, label %bb0, label %bb1 > + > +bb0: > + call void @llvm.lifetime.end(i64 -1, i8* %a) nounwind > + br label %bb1 > + > +bb1: > + call void @f() > + ret void > +} > + > +declare void @f() > + > +declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind > + > +declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110629/c548763c/attachment.html From echristo at apple.com Wed Jun 29 11:44:54 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 09:44:54 -0700 Subject: [llvm-commits] LLVM JIT Adaptive Compilation Patch In-Reply-To: References: <2AEEA453-1625-4B66-B025-012FD3B49344@apple.com> Message-ID: On Jun 28, 2011, at 4:17 PM, Eric Christopher wrote: > > On Jun 28, 2011, at 3:33 PM, Xin Tong Utoronto wrote: > >> Most of the changes in this patch are within JIT.cpp and JIT.hpp. Only a few variables are added to ExecutionEngine . I am now sure how this is going to affect MC JIT. Also, when is the major change for the MC JIT going to be completed ? > > We're overall not sure about the latter. Some of the work has been completed, but it's not a full-fledged replacement for the current JIT yet. > > How about we put your work on a branch for now, get it working and optimized, get some more compelling results and see where we are from there? If we can get some more compelling results it could also be used to get other users of the JIT interested in the adaptive compilation strategy. > > I'll go ahead and create the branch and apply your patch tonight. From there we can talk about getting your next patch reviewed and then applied. Past that we'll look at getting you commit access. > I've gone ahead and created the branch and applied your patch here: [yendi:Data/sources/llvm-adaptive-compilation] echristo% svn ci Sending include/llvm/ExecutionEngine/ExecutionEngine.h Sending lib/ExecutionEngine/ExecutionEngine.cpp Sending lib/ExecutionEngine/JIT/JIT.cpp Sending lib/ExecutionEngine/JIT/JIT.h Sending tools/lli/lli.cpp Transmitting file data ..... Committed revision 134075. [yendi:Data/sources/llvm-adaptive-compilation] echristo% svn info Path: . URL: https://echristo at llvm.org/svn/llvm-project/llvm/branches/GSoC/adaptive-compilation Repository Root: https://echristo at llvm.org/svn/llvm-project Repository UUID: 91177308-0d34-0410-b5e6-96231b3b80d8 Revision: 134074 Node Kind: directory Schedule: normal Last Changed Author: echristo Last Changed Rev: 134074 Last Changed Date: 2011-06-29 09:26:02 -0700 (Wed, 29 Jun 2011) So let's go on to the next patch and see where we are. -eric From aggarwa4 at illinois.edu Wed Jun 29 11:53:51 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 29 Jun 2011 16:53:51 -0000 Subject: [llvm-commits] [poolalloc] r134076 - /poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Message-ID: <20110629165351.916702A6C12C@llvm.org> Author: aggarwa4 Date: Wed Jun 29 11:53:51 2011 New Revision: 134076 URL: http://llvm.org/viewvc/llvm-project?rev=134076&view=rev Log: Fix off by one error in strcat. Fix error handling in readlink. For accept, take the size from argument no. 3. Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=134076&r1=134075&r2=134076&view=diff ============================================================================== --- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original) +++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Wed Jun 29 11:53:51 2011 @@ -81,8 +81,9 @@ void trackgetpwuid(void *ptr, uint32_t tag) ; void trackgethostname(void *ptr, uint32_t tag) ; void trackgetaddrinfo(void *ptr, uint32_t tag) ; - void trackaccept(void *ptr, uint32_t tag) ; + void trackaccept(void *ptr, void *size,uint32_t tag) ; void trackpoll(void *ptr, uint64_t nfds, uint32_t tag) ; + void trackReadLink(void *ptr, int64_t val, uint32_t tag) ; } void trackInitInst(void *ptr, uint64_t size, uint32_t tag); @@ -364,7 +365,7 @@ * Initialize the metadata fr dst pointer of strcap */ void trackStrcatInst(void *dst, void *src, uint32_t tag) { - uintptr_t dst_start = (uintptr_t)(dst) + strlen((const char *)dst) -1; + uintptr_t dst_start = (uintptr_t)(dst) + strlen((const char *)dst); copyTypeInfo((void*)dst_start, src, strlen((const char *)src)+1, tag); } @@ -401,8 +402,9 @@ trackInitInst(result, sizeof(struct addrinfo*), tag); } -void trackaccept(void *ptr, uint32_t tag) { - trackInitInst(ptr, sizeof(struct sockaddr), tag); +void trackaccept(void *ptr, void *size, uint32_t tag) { + int32_t bytes = *((int32_t*)size); + trackInitInst(ptr, (uint64_t)bytes, tag); } void trackpoll(void *ptr, uint64_t nfds, uint32_t tag) { @@ -413,3 +415,8 @@ i++; } } +void trackReadLink(void *ptr, int64_t val, uint32_t tag) { + if(val == -1) + return; + trackInitInst(ptr, val, tag); +} From aggarwa4 at illinois.edu Wed Jun 29 11:54:38 2011 From: aggarwa4 at illinois.edu (Arushi Aggarwal) Date: Wed, 29 Jun 2011 16:54:38 -0000 Subject: [llvm-commits] [poolalloc] r134077 - /poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Message-ID: <20110629165438.1E32C2A6C12C@llvm.org> Author: aggarwa4 Date: Wed Jun 29 11:54:37 2011 New Revision: 134077 URL: http://llvm.org/viewvc/llvm-project?rev=134077&view=rev Log: Separate function for readlink, for error handling. For accept, pass size from param. Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=134077&r1=134076&r2=134077&view=diff ============================================================================== --- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original) +++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Wed Jun 29 11:54:37 2011 @@ -1503,10 +1503,13 @@ } else if (F->getNameStr() == std::string("accept")) { CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy); BCI->insertAfter(I); + CastInst *BCI_Size = BitCastInst::CreatePointerCast(CS.getArgument(2), VoidPtrTy); + BCI_Size->insertAfter(I); std::vectorArgs; Args.push_back(BCI); + Args.push_back(BCI_Size); Args.push_back(getTagCounter()); - Constant *F = M.getOrInsertFunction("trackaccept", VoidTy, VoidPtrTy, Int32Ty, NULL); + Constant *F = M.getOrInsertFunction("trackaccept", VoidTy, VoidPtrTy,VoidPtrTy, Int32Ty, NULL); CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(BCI); } else if (F->getNameStr() == std::string("poll")) { @@ -1717,7 +1720,8 @@ Args.push_back(CS.getArgument(1)); Args.push_back(I); Args.push_back(getTagCounter()); - CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end()); + Constant *F = M.getOrInsertFunction("trackReadLink", VoidTy, VoidPtrTy, I->getType(), Int32Ty, NULL); + CallInst *CI = CallInst::Create(F, Args.begin(), Args.end()); CI->insertAfter(I); } else if (F->getNameStr() == std::string("getsockname")) { CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy, "", I); From evan.cheng at apple.com Wed Jun 29 12:14:00 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 29 Jun 2011 17:14:00 -0000 Subject: [llvm-commits] [llvm] r134078 - /llvm/trunk/docs/LangRef.html Message-ID: <20110629171400.4C6722A6C12C@llvm.org> Author: evancheng Date: Wed Jun 29 12:14:00 2011 New Revision: 134078 URL: http://llvm.org/viewvc/llvm-project?rev=134078&view=rev Log: Add missing operand. rdar://9694169 Modified: llvm/trunk/docs/LangRef.html Modified: llvm/trunk/docs/LangRef.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=134078&r1=134077&r2=134078&view=diff ============================================================================== --- llvm/trunk/docs/LangRef.html (original) +++ llvm/trunk/docs/LangRef.html Wed Jun 29 12:14:00 2011 @@ -7309,7 +7309,7 @@ store i32 4, %ptr %result1 = load i32* %ptr ; yields {i32}:result1 = 4 - call void @llvm.memory.barrier(i1 false, i1 true, i1 false, i1 false) + call void @llvm.memory.barrier(i1 false, i1 true, i1 false, i1 false, i1 true) ; guarantee the above finishes store i32 8, %ptr ; before this begins From echristo at apple.com Wed Jun 29 12:23:51 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 17:23:51 -0000 Subject: [llvm-commits] [llvm] r134079 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h Message-ID: <20110629172351.289882A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 12:23:50 2011 New Revision: 134079 URL: http://llvm.org/viewvc/llvm-project?rev=134079&view=rev Log: Use getRegForInlineAsmConstraint instead of custom defining regclasses via vectors. Part of rdar://9643582 Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp llvm/trunk/lib/Target/X86/X86ISelLowering.h Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=134079&r1=134078&r2=134079&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Wed Jun 29 12:23:50 2011 @@ -12875,69 +12875,41 @@ return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); } -std::vector X86TargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const { +std::pair +X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, + EVT VT) const { + // First, see if this is a constraint that directly corresponds to an LLVM + // register class. if (Constraint.size() == 1) { - // FIXME: not handling fp-stack yet! - switch (Constraint[0]) { // GCC X86 Constraint Letters - default: break; // Unknown constraint letter + // GCC Constraint Letters + switch (Constraint[0]) { + default: break; + // TODO: Slight differences here in allocation order and leaving + // RIP in the class. Do they matter any more here than they do + // in the normal allocation? case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. if (Subtarget->is64Bit()) { - if (VT == MVT::i32) - return make_vector(X86::EAX, X86::EDX, X86::ECX, X86::EBX, - X86::ESI, X86::EDI, X86::R8D, X86::R9D, - X86::R10D,X86::R11D,X86::R12D, - X86::R13D,X86::R14D,X86::R15D, - X86::EBP, X86::ESP, 0); - else if (VT == MVT::i16) - return make_vector(X86::AX, X86::DX, X86::CX, X86::BX, - X86::SI, X86::DI, X86::R8W,X86::R9W, - X86::R10W,X86::R11W,X86::R12W, - X86::R13W,X86::R14W,X86::R15W, - X86::BP, X86::SP, 0); - else if (VT == MVT::i8) - return make_vector(X86::AL, X86::DL, X86::CL, X86::BL, - X86::SIL, X86::DIL, X86::R8B,X86::R9B, - X86::R10B,X86::R11B,X86::R12B, - X86::R13B,X86::R14B,X86::R15B, - X86::BPL, X86::SPL, 0); - - else if (VT == MVT::i64) - return make_vector(X86::RAX, X86::RDX, X86::RCX, X86::RBX, - X86::RSI, X86::RDI, X86::R8, X86::R9, - X86::R10, X86::R11, X86::R12, - X86::R13, X86::R14, X86::R15, - X86::RBP, X86::RSP, 0); - - break; + if (VT == MVT::i32) + return std::make_pair(0U, X86::GR32RegisterClass); + else if (VT == MVT::i16) + return std::make_pair(0U, X86::GR16RegisterClass); + else if (VT == MVT::i8) + return std::make_pair(0U, X86::GR8RegisterClass); + else if (VT == MVT::i64) + return std::make_pair(0U, X86::GR64RegisterClass); + break; } // 32-bit fallthrough case 'Q': // Q_REGS if (VT == MVT::i32) - return make_vector(X86::EAX, X86::EDX, X86::ECX, X86::EBX, 0); + return std::make_pair(0U, X86::GR32_ABCDRegisterClass); else if (VT == MVT::i16) - return make_vector(X86::AX, X86::DX, X86::CX, X86::BX, 0); + return std::make_pair(0U, X86::GR16_ABCDRegisterClass); else if (VT == MVT::i8) - return make_vector(X86::AL, X86::DL, X86::CL, X86::BL, 0); + return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); else if (VT == MVT::i64) - return make_vector(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0); + return std::make_pair(0U, X86::GR64_ABCDRegisterClass); break; - } - } - - return std::vector(); -} - -std::pair -X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const { - // First, see if this is a constraint that directly corresponds to an LLVM - // register class. - if (Constraint.size() == 1) { - // GCC Constraint Letters - switch (Constraint[0]) { - default: break; case 'r': // GENERAL_REGS case 'l': // INDEX_REGS if (VT == MVT::i8) Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.h?rev=134079&r1=134078&r2=134079&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelLowering.h (original) +++ llvm/trunk/lib/Target/X86/X86ISelLowering.h Wed Jun 29 12:23:50 2011 @@ -596,10 +596,6 @@ virtual ConstraintWeight getSingleConstraintMatchWeight( AsmOperandInfo &info, const char *constraint) const; - std::vector - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; - virtual const char *LowerXConstraint(EVT ConstraintVT) const; /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops From echristo at apple.com Wed Jun 29 12:53:29 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 17:53:29 -0000 Subject: [llvm-commits] [llvm] r134080 - in /llvm/trunk/lib/Target/XCore: XCoreISelLowering.cpp XCoreISelLowering.h Message-ID: <20110629175329.E6BCB2A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 12:53:29 2011 New Revision: 134080 URL: http://llvm.org/viewvc/llvm-project?rev=134080&view=rev Log: Move XCore from getRegClassForInlineAsmConstraint to getRegForInlineAsmConstraint. Part of rdar://9643582 Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp?rev=134080&r1=134079&r2=134080&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.cpp Wed Jun 29 12:53:29 2011 @@ -1591,21 +1591,18 @@ // XCore Inline Assembly Support //===----------------------------------------------------------------------===// -std::vector XCoreTargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const -{ - if (Constraint.size() != 1) - return std::vector(); - - switch (Constraint[0]) { +std::pair +XCoreTargetLowering:: +getRegForInlineAsmConstraint(const std::string &Constraint, + EVT VT) const { + if (Constraint.size() == 1) { + switch (Constraint[0]) { default : break; case 'r': - return make_vector(XCore::R0, XCore::R1, XCore::R2, - XCore::R3, XCore::R4, XCore::R5, - XCore::R6, XCore::R7, XCore::R8, - XCore::R9, XCore::R10, XCore::R11, 0); - break; + return std::make_pair(0U, XCore::GRRegsRegisterClass); + } } - return std::vector(); + // Use the default implementation in TargetLowering to convert the register + // constraint into a member of a register class. + return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } Modified: llvm/trunk/lib/Target/XCore/XCoreISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreISelLowering.h?rev=134080&r1=134079&r2=134080&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreISelLowering.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreISelLowering.h Wed Jun 29 12:53:29 2011 @@ -148,9 +148,9 @@ SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const; // Inline asm support - std::vector - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; + std::pair + getRegForInlineAsmConstraint(const std::string &Constraint, + EVT VT) const; // Expand specifics SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const; From stoklund at 2pi.dk Wed Jun 29 12:59:39 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 29 Jun 2011 10:59:39 -0700 Subject: [llvm-commits] [llvm] r134079 - in /llvm/trunk/lib/Target/X86: X86ISelLowering.cpp X86ISelLowering.h In-Reply-To: <20110629172351.289882A6C12C@llvm.org> References: <20110629172351.289882A6C12C@llvm.org> Message-ID: On Jun 29, 2011, at 10:23 AM, Eric Christopher wrote: > Author: echristo > Date: Wed Jun 29 12:23:50 2011 > New Revision: 134079 > > URL: http://llvm.org/viewvc/llvm-project?rev=134079&view=rev > Log: > Use getRegForInlineAsmConstraint instead of custom defining regclasses > via vectors. Heh, you didn't even have to add new classes. Nice. /jakob From grosbach at apple.com Wed Jun 29 13:09:25 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 29 Jun 2011 11:09:25 -0700 Subject: [llvm-commits] [llvm] r134047 - in /llvm/trunk/lib/CodeGen: RegAllocGreedy.cpp SplitKit.cpp SplitKit.h In-Reply-To: <20110629002424.9E0932A6C12C@llvm.org> References: <20110629002424.9E0932A6C12C@llvm.org> Message-ID: <82CEA4EF-0D63-4B66-A688-54D724C3E526@apple.com> On Jun 28, 2011, at 5:24 PM, Jakob Stoklund Olesen wrote: > Author: stoklund > Date: Tue Jun 28 19:24:24 2011 > New Revision: 134047 > > URL: http://llvm.org/viewvc/llvm-project?rev=134047&view=rev > Log: > Rewrite RAGreedy::splitAroundRegion, now with cool ASCII art. > > This function has to deal with a lot of special cases, and the old > version got it wrong sometimes. In particular, it would sometimes leave > multiple uses in the stack interval in a single block. That causes bad > code with multiple reloads in the same basic block. Aha! So that's why that was happening. Glad to see that get fixed! -Jim > > The new version handles block entry and exit in a single pass. It first > eliminates all the easy cases, and then goes on to create a local > interval for the blocks with difficult interference. Previously, we > would only create the local interval for completely isolated blocks. > > It can happen that the stack interval becomes completely empty because > we could allocate a register in all edge bundles, and the new local > intervals deal with the interference. The empty stack interval is > harmless, but we need to remove a SplitKit assertion that checks for > empty intervals. > > Modified: > llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp > llvm/trunk/lib/CodeGen/SplitKit.cpp > llvm/trunk/lib/CodeGen/SplitKit.h > > Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=134047&r1=134046&r2=134047&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) > +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Tue Jun 28 19:24:24 2011 > @@ -763,32 +763,46 @@ > // Create the main cross-block interval. > const unsigned MainIntv = SE->openIntv(); > > - // First add all defs that are live out of a block. > + // First handle all the blocks with uses. > ArrayRef UseBlocks = SA->getUseBlocks(); > for (unsigned i = 0; i != UseBlocks.size(); ++i) { > const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; > - bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; > - bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; > + bool RegIn = BI.LiveIn && > + LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; > + bool RegOut = BI.LiveOut && > + LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; > > // Create separate intervals for isolated blocks with multiple uses. > - if (!RegIn && !RegOut && BI.FirstUse != BI.LastUse) { > + // > + // |---o---o---| Enter and leave on the stack. > + // ____-----____ Create local interval for uses. > + // > + // | o---o---| Defined in block, leave on stack. > + // -----____ Create local interval for uses. > + // > + // |---o---x | Enter on stack, killed in block. > + // ____----- Create local interval for uses. > + // > + if (!RegIn && !RegOut) { > DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n"); > - SE->splitSingleBlock(BI); > - SE->selectIntv(MainIntv); > + if (!BI.isOneInstr()) { > + SE->splitSingleBlock(BI); > + SE->selectIntv(MainIntv); > + } > continue; > } > > - // Should the register be live out? > - if (!BI.LiveOut || !RegOut) > - continue; > - > SlotIndex Start, Stop; > tie(Start, Stop) = Indexes->getMBBRange(BI.MBB); > Intf.moveToBlock(BI.MBB->getNumber()); > - DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#" > - << Bundles->getBundle(BI.MBB->getNumber(), 1) > + DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0) > + << (RegIn ? " => " : " -- ") > + << "BB#" << BI.MBB->getNumber() > + << (RegOut ? " => " : " -- ") > + << " EB#" << Bundles->getBundle(BI.MBB->getNumber(), 1) > << " [" << Start << ';' > << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop > + << ") uses [" << BI.FirstUse << ';' << BI.LastUse > << ") intf [" << Intf.first() << ';' << Intf.last() << ')'); > > // The interference interval should either be invalid or overlap MBB. > @@ -797,150 +811,266 @@ > assert((!Intf.hasInterference() || Intf.last() > Start) > && "Bad interference"); > > - // Check interference leaving the block. > + // We are now ready to decide where to split in the current block. There > + // are many variables guiding the decision: > + // > + // - RegIn / RegOut: The global splitting algorithm's decisions for our > + // ingoing and outgoing bundles. > + // > + // - BI.BlockIn / BI.BlockOut: Is the live range live-in and/or live-out > + // from this block. > + // > + // - Intf.hasInterference(): Is there interference in this block. > + // > + // - Intf.first() / Inft.last(): The range of interference. > + // > + // The live range should be split such that MainIntv is live-in when RegIn > + // is set, and live-out when RegOut is set. MainIntv should never overlap > + // the interference, and the stack interval should never have more than one > + // use per block. > + > + // No splits can be inserted after LastSplitPoint, overlap instead. > + SlotIndex LastSplitPoint = Stop; > + if (BI.LiveOut) > + LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); > + > + // At this point, we know that either RegIn or RegOut is set. We dealt with > + // the all-stack case above. > + > + // Blocks without interference are relatively easy. > if (!Intf.hasInterference()) { > - // Block is interference-free. > - DEBUG(dbgs() << ", no interference"); > - if (!BI.LiveThrough) { > - DEBUG(dbgs() << ", not live-through.\n"); > - SE->useIntv(SE->enterIntvBefore(BI.FirstUse), Stop); > - continue; > - } > - if (!RegIn) { > - // Block is live-through, but entry bundle is on the stack. > - // Reload just before the first use. > - DEBUG(dbgs() << ", not live-in, enter before first use.\n"); > - SE->useIntv(SE->enterIntvBefore(BI.FirstUse), Stop); > - continue; > - } > - DEBUG(dbgs() << ", live-through.\n"); > - continue; > - } > + DEBUG(dbgs() << ", no interference.\n"); > + SE->selectIntv(MainIntv); > + // The easiest case has MainIntv live through. > + // > + // |---o---o---| Live-in, live-out. > + // ============= Use MainIntv everywhere. > + // > + SlotIndex From = Start, To = Stop; > + > + // Block entry. Reload before the first use if MainIntv is not live-in. > + // > + // |---o-- Enter on stack. > + // ____=== Reload before first use. > + // > + // | o-- Defined in block. > + // === Use MainIntv from def. > + // > + if (!RegIn) > + From = SE->enterIntvBefore(BI.FirstUse); > > - // Block has interference. > - DEBUG(dbgs() << ", interference to " << Intf.last()); > + // Block exit. Handle cases where MainIntv is not live-out. > + if (!BI.LiveOut) > + // > + // --x | Killed in block. > + // === Use MainIntv up to kill. > + // > + To = SE->leaveIntvAfter(BI.LastUse); > + else if (!RegOut) { > + // > + // --o---| Live-out on stack. > + // ===____ Use MainIntv up to last use, switch to stack. > + // > + // -----o| Live-out on stack, last use after last split point. > + // ====== Extend MainIntv to last use, overlapping. > + // \____ Copy to stack interval before last split point. > + // > + if (BI.LastUse < LastSplitPoint) > + To = SE->leaveIntvAfter(BI.LastUse); > + else { > + // The last use is after the last split point, it is probably an > + // indirect branch. > + To = SE->leaveIntvBefore(LastSplitPoint); > + // Run a double interval from the split to the last use. This makes > + // it possible to spill the complement without affecting the indirect > + // branch. > + SE->overlapIntv(To, BI.LastUse); > + } > + } > > - if (!BI.LiveThrough && Intf.last() <= BI.FirstUse) { > - // The interference doesn't reach the outgoing segment. > - DEBUG(dbgs() << " doesn't affect def from " << BI.FirstUse << '\n'); > - SE->useIntv(BI.FirstUse, Stop); > + // Paint in MainIntv liveness for this block. > + SE->useIntv(From, To); > continue; > } > > - SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); > - if (Intf.last().getBoundaryIndex() < BI.LastUse) { > - // There are interference-free uses at the end of the block. > - // Find the first use that can get the live-out register. > - SmallVectorImpl::const_iterator UI = > - std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), > - Intf.last().getBoundaryIndex()); > - assert(UI != SA->UseSlots.end() && "Couldn't find last use"); > - SlotIndex Use = *UI; > - assert(Use <= BI.LastUse && "Couldn't find last use"); > - // Only attempt a split befroe the last split point. > - if (Use.getBaseIndex() <= LastSplitPoint) { > - DEBUG(dbgs() << ", free use at " << Use << ".\n"); > - SlotIndex SegStart = SE->enterIntvBefore(Use); > - assert(SegStart >= Intf.last() && "Couldn't avoid interference"); > - assert(SegStart < LastSplitPoint && "Impossible split point"); > - SE->useIntv(SegStart, Stop); > - continue; > - } > - } > + // We are now looking at a block with interference, and we know that either > + // RegIn or RegOut is set. > + assert(Intf.hasInterference() && (RegIn || RegOut) && "Bad invariant"); > > - // Interference is after the last use. > - DEBUG(dbgs() << " after last use.\n"); > - SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB); > - assert(SegStart >= Intf.last() && "Couldn't avoid interference"); > - } > + // If the live range is not live through the block, it is possible that the > + // interference doesn't even overlap. Deal with those cases first. Since > + // no copy instructions are required, we can tolerate interference starting > + // or ending at the same instruction that kills or defines our live range. > > - // Now all defs leading to live bundles are handled, do everything else. > - for (unsigned i = 0; i != UseBlocks.size(); ++i) { > - const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; > - bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; > - bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; > + // Live-in, killed before interference. > + // > + // ~~~ Interference after kill. > + // |---o---x | Killed in block. > + // ========= Use MainIntv everywhere. > + // > + if (RegIn && !BI.LiveOut && BI.LastUse <= Intf.first()) { > + DEBUG(dbgs() << ", live-in, killed before interference.\n"); > + SE->selectIntv(MainIntv); > + SlotIndex To = SE->leaveIntvAfter(BI.LastUse); > + SE->useIntv(Start, To); > + continue; > + } > > - // Is the register live-in? > - if (!BI.LiveIn || !RegIn) > + // Live-out, defined after interference. > + // > + // ~~~ Interference before def. > + // | o---o---| Defined in block. > + // ========= Use MainIntv everywhere. > + // > + if (RegOut && !BI.LiveIn && BI.FirstUse >= Intf.last()) { > + DEBUG(dbgs() << ", live-out, defined after interference.\n"); > + SE->selectIntv(MainIntv); > + SlotIndex From = SE->enterIntvBefore(BI.FirstUse); > + SE->useIntv(From, Stop); > continue; > + } > > - // We have an incoming register. Check for interference. > - SlotIndex Start, Stop; > - tie(Start, Stop) = Indexes->getMBBRange(BI.MBB); > - Intf.moveToBlock(BI.MBB->getNumber()); > - DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0) > - << " -> BB#" << BI.MBB->getNumber() << " [" << Start << ';' > - << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop > - << ')'); > + // The interference is now known to overlap the live range, but it may > + // still be easy to avoid if all the interference is on one side of the > + // uses, and we enter or leave on the stack. > > - // Check interference entering the block. > - if (!Intf.hasInterference()) { > - // Block is interference-free. > - DEBUG(dbgs() << ", no interference"); > - if (!BI.LiveThrough) { > - DEBUG(dbgs() << ", killed in block.\n"); > - SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse)); > - continue; > - } > - if (!RegOut) { > - SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); > - // Block is live-through, but exit bundle is on the stack. > - // Spill immediately after the last use. > - if (BI.LastUse < LastSplitPoint) { > - DEBUG(dbgs() << ", uses, stack-out.\n"); > - SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse)); > - continue; > - } > - // The last use is after the last split point, it is probably an > - // indirect jump. > - DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point " > - << LastSplitPoint << ", stack-out.\n"); > - SlotIndex SegEnd = SE->leaveIntvBefore(LastSplitPoint); > - SE->useIntv(Start, SegEnd); > - // Run a double interval from the split to the last use. > - // This makes it possible to spill the complement without affecting the > - // indirect branch. > - SE->overlapIntv(SegEnd, BI.LastUse); > - continue; > + // Live-out on stack, interference after last use. > + // > + // ~~~ Interference after last use. > + // |---o---o---| Live-out on stack. > + // =========____ Leave MainIntv after last use. > + // > + // ~ Interference after last use. > + // |---o---o--o| Live-out on stack, late last use. > + // =========____ Copy to stack after LSP, overlap MainIntv. > + // > + if (!RegOut && Intf.first() > BI.LastUse.getBoundaryIndex()) { > + assert(RegIn && "Stack-in, stack-out should already be handled"); > + if (BI.LastUse < LastSplitPoint) { > + DEBUG(dbgs() << ", live-in, stack-out, interference after last use.\n"); > + SE->selectIntv(MainIntv); > + SlotIndex To = SE->leaveIntvAfter(BI.LastUse); > + assert(To <= Intf.first() && "Expected to avoid interference"); > + SE->useIntv(Start, To); > + } else { > + DEBUG(dbgs() << ", live-in, stack-out, avoid last split point\n"); > + SE->selectIntv(MainIntv); > + SlotIndex To = SE->leaveIntvBefore(LastSplitPoint); > + assert(To <= Intf.first() && "Expected to avoid interference"); > + SE->overlapIntv(To, BI.LastUse); > + SE->useIntv(Start, To); > } > - // Register is live-through. > - DEBUG(dbgs() << ", uses, live-through.\n"); > - SE->useIntv(Start, Stop); > continue; > } > > - // Block has interference. > - DEBUG(dbgs() << ", interference from " << Intf.first()); > - > - if (!BI.LiveThrough && Intf.first() >= BI.LastUse) { > - // The interference doesn't reach the outgoing segment. > - DEBUG(dbgs() << " doesn't affect kill at " << BI.LastUse << '\n'); > - SE->useIntv(Start, BI.LastUse); > + // Live-in on stack, interference before first use. > + // > + // ~~~ Interference before first use. > + // |---o---o---| Live-in on stack. > + // ____========= Enter MainIntv before first use. > + // > + if (!RegIn && Intf.last() < BI.FirstUse.getBaseIndex()) { > + assert(RegOut && "Stack-in, stack-out should already be handled"); > + DEBUG(dbgs() << ", stack-in, interference before first use.\n"); > + SE->selectIntv(MainIntv); > + SlotIndex From = SE->enterIntvBefore(BI.FirstUse); > + assert(From >= Intf.last() && "Expected to avoid interference"); > + SE->useIntv(From, Stop); > continue; > } > > - if (Intf.first().getBaseIndex() > BI.FirstUse) { > - // There are interference-free uses at the beginning of the block. > - // Find the last use that can get the register. > - SmallVectorImpl::const_iterator UI = > - std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), > - Intf.first().getBaseIndex()); > - assert(UI != SA->UseSlots.begin() && "Couldn't find first use"); > - SlotIndex Use = (--UI)->getBoundaryIndex(); > - DEBUG(dbgs() << ", free use at " << *UI << ".\n"); > - SlotIndex SegEnd = SE->leaveIntvAfter(Use); > - assert(SegEnd <= Intf.first() && "Couldn't avoid interference"); > - SE->useIntv(Start, SegEnd); > - continue; > + // The interference is overlapping somewhere we wanted to use MainIntv. That > + // means we need to create a local interval that can be allocated a > + // different register. > + DEBUG(dbgs() << ", creating local interval.\n"); > + unsigned LocalIntv = SE->openIntv(); > + > + // We may be creating copies directly between MainIntv and LocalIntv, > + // bypassing the stack interval. When we do that, we should never use the > + // leaveIntv* methods as they define values in the stack interval. By > + // starting from the end of the block and working our way backwards, we can > + // get by with only enterIntv* methods. > + // > + // When selecting split points, we generally try to maximize the stack > + // interval as long at it contains no uses, maximize the main interval as > + // long as it doesn't overlap interference, and minimize the local interval > + // that we don't know how to allocate yet. > + > + // Handle the block exit, set Pos to the first handled slot. > + SlotIndex Pos = BI.LastUse; > + if (RegOut) { > + assert(Intf.last() < LastSplitPoint && "Cannot be live-out in register"); > + // Create a snippet of MainIntv that is live-out. > + // > + // ~~~ Interference overlapping uses. > + // --o---| Live-out in MainIntv. > + // ----=== Switch from LocalIntv to MainIntv after interference. > + // > + SE->selectIntv(MainIntv); > + Pos = SE->enterIntvAfter(Intf.last()); > + assert(Pos >= Intf.last() && "Expected to avoid interference"); > + SE->useIntv(Pos, Stop); > + SE->selectIntv(LocalIntv); > + } else if (BI.LiveOut) { > + if (BI.LastUse < LastSplitPoint) { > + // Live-out on the stack. > + // > + // ~~~ Interference overlapping uses. > + // --o---| Live-out on stack. > + // ---____ Switch from LocalIntv to stack after last use. > + // > + Pos = SE->leaveIntvAfter(BI.LastUse); > + } else { > + // Live-out on the stack, last use after last split point. > + // > + // ~~~ Interference overlapping uses. > + // --o--o| Live-out on stack, late use. > + // ------ Copy to stack before LSP, overlap LocalIntv. > + // \__ > + // > + Pos = SE->leaveIntvBefore(LastSplitPoint); > + // We need to overlap LocalIntv so it can reach LastUse. > + SE->overlapIntv(Pos, BI.LastUse); > + } > } > > - // Interference is before the first use. > - DEBUG(dbgs() << " before first use.\n"); > - SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB); > - assert(SegEnd <= Intf.first() && "Couldn't avoid interference"); > + // When not live-out, leave Pos at LastUse. We have handled everything from > + // Pos to Stop. Find the starting point for LocalIntv. > + assert(SE->currentIntv() == LocalIntv && "Expecting local interval"); > + > + if (RegIn) { > + assert(Start < Intf.first() && "Cannot be live-in with interference"); > + // Live-in in MainIntv, only use LocalIntv for interference. > + // > + // ~~~ Interference overlapping uses. > + // |---o-- Live-in in MainIntv. > + // ====--- Switch to LocalIntv before interference. > + // > + SlotIndex Switch = SE->enterIntvBefore(Intf.first()); > + assert(Switch <= Intf.first() && "Expected to avoid interference"); > + SE->useIntv(Switch, Pos); > + SE->selectIntv(MainIntv); > + SE->useIntv(Start, Switch); > + } else { > + // Live-in on stack, enter LocalIntv before first use. > + // > + // ~~~ Interference overlapping uses. > + // |---o-- Live-in in MainIntv. > + // ____--- Reload to LocalIntv before interference. > + // > + // Defined in block. > + // > + // ~~~ Interference overlapping uses. > + // | o-- Defined in block. > + // --- Begin LocalIntv at first use. > + // > + SlotIndex Switch = SE->enterIntvBefore(BI.FirstUse); > + SE->useIntv(Switch, Pos); > + } > } > > // Handle live-through blocks. > + SE->selectIntv(MainIntv); > for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) { > unsigned Number = Cand.ActiveBlocks[i]; > bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)]; > > Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=134047&r1=134046&r2=134047&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) > +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Tue Jun 28 19:24:24 2011 > @@ -636,6 +636,7 @@ > void SplitEditor::selectIntv(unsigned Idx) { > assert(Idx != 0 && "Cannot select the complement interval"); > assert(Idx < Edit->size() && "Can only select previously opened interval"); > + DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n'); > OpenIdx = Idx; > } > > @@ -656,6 +657,24 @@ > return VNI->def; > } > > +SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) { > + assert(OpenIdx && "openIntv not called before enterIntvAfter"); > + DEBUG(dbgs() << " enterIntvAfter " << Idx); > + Idx = Idx.getBoundaryIndex(); > + VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx); > + if (!ParentVNI) { > + DEBUG(dbgs() << ": not live\n"); > + return Idx; > + } > + DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); > + MachineInstr *MI = LIS.getInstructionFromIndex(Idx); > + assert(MI && "enterIntvAfter called with invalid index"); > + > + VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), > + llvm::next(MachineBasicBlock::iterator(MI))); > + return VNI->def; > +} > + > SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) { > assert(OpenIdx && "openIntv not called before enterIntvAtEnd"); > SlotIndex End = LIS.getMBBEndIdx(&MBB); > @@ -1007,12 +1026,6 @@ > markComplexMapped(i, ParentVNI); > } > > -#ifndef NDEBUG > - // Every new interval must have a def by now, otherwise the split is bogus. > - for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I) > - assert((*I)->hasAtLeastOneValue() && "Split interval has no value"); > -#endif > - > // Transfer the simply mapped values, check if any are skipped. > bool Skipped = transferValues(); > if (Skipped) > > Modified: llvm/trunk/lib/CodeGen/SplitKit.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=134047&r1=134046&r2=134047&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/SplitKit.h (original) > +++ llvm/trunk/lib/CodeGen/SplitKit.h Tue Jun 28 19:24:24 2011 > @@ -81,6 +81,12 @@ > bool LiveThrough; ///< Live in whole block (Templ 5. above). > bool LiveIn; ///< Current reg is live in. > bool LiveOut; ///< Current reg is live out. > + > + /// isOneInstr - Returns true when this BlockInfo describes a single > + /// instruction. > + bool isOneInstr() const { > + return SlotIndex::isSameInstr(FirstUse, LastUse); > + } > }; > > private: > @@ -360,6 +366,10 @@ > /// Return the beginning of the new live range. > SlotIndex enterIntvBefore(SlotIndex Idx); > > + /// enterIntvAfter - Enter the open interval after the instruction at Idx. > + /// Return the beginning of the new live range. > + SlotIndex enterIntvAfter(SlotIndex Idx); > + > /// enterIntvAtEnd - Enter the open interval at the end of MBB. > /// Use the open interval from he inserted copy to the MBB end. > /// Return the beginning of the new live range. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From echristo at apple.com Wed Jun 29 13:53:10 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 18:53:10 -0000 Subject: [llvm-commits] [llvm] r134083 - in /llvm/trunk/lib/Target/Sparc: SparcISelLowering.cpp SparcISelLowering.h Message-ID: <20110629185311.06A412A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 13:53:10 2011 New Revision: 134083 URL: http://llvm.org/viewvc/llvm-project?rev=134083&view=rev Log: Remove getRegClassForInlineAsmConstraint from sparc. Part of rdar://9643582 Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp llvm/trunk/lib/Target/Sparc/SparcISelLowering.h Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=134083&r1=134082&r2=134083&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Wed Jun 29 13:53:10 2011 @@ -1,4 +1,3 @@ - //===-- SparcISelLowering.cpp - Sparc DAG Lowering Implementation ---------===// // // The LLVM Compiler Infrastructure @@ -1265,26 +1264,6 @@ return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } -std::vector SparcTargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const { - if (Constraint.size() != 1) - return std::vector(); - - switch (Constraint[0]) { - default: break; - case 'r': - return make_vector(SP::L0, SP::L1, SP::L2, SP::L3, - SP::L4, SP::L5, SP::L6, SP::L7, - SP::I0, SP::I1, SP::I2, SP::I3, - SP::I4, SP::I5, - SP::O0, SP::O1, SP::O2, SP::O3, - SP::O4, SP::O5, SP::O7, 0); - } - - return std::vector(); -} - bool SparcTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { // The Sparc target isn't yet aware of offsets. Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.h?rev=134083&r1=134082&r2=134083&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcISelLowering.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.h Wed Jun 29 13:53:10 2011 @@ -65,9 +65,6 @@ ConstraintType getConstraintType(const std::string &Constraint) const; std::pair getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; - std::vector - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; From echristo at apple.com Wed Jun 29 14:04:31 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 19:04:31 -0000 Subject: [llvm-commits] [llvm] r134084 - in /llvm/trunk/lib/Target/Mips: MipsISelLowering.cpp MipsISelLowering.h Message-ID: <20110629190431.48AF22A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 14:04:31 2011 New Revision: 134084 URL: http://llvm.org/viewvc/llvm-project?rev=134084&view=rev Log: Remove getRegClassForInlineAsmConstraint for Mips. Part of rdar://9643582 Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp llvm/trunk/lib/Target/Mips/MipsISelLowering.h Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=134084&r1=134083&r2=134084&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Jun 29 14:04:31 2011 @@ -2337,6 +2337,8 @@ { if (Constraint.size() == 1) { switch (Constraint[0]) { + case 'd': // Address register. Same as 'r' unless generating MIPS16 code. + case 'y': // Same as 'r'. Exists for compatibility. case 'r': return std::make_pair(0U, Mips::CPURegsRegisterClass); case 'f': @@ -2345,55 +2347,12 @@ if (VT == MVT::f64) if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) return std::make_pair(0U, Mips::AFGR64RegisterClass); + break; } } return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } -/// Given a register class constraint, like 'r', if this corresponds directly -/// to an LLVM register class, return a register of 0 and the register class -/// pointer. -std::vector MipsTargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const -{ - if (Constraint.size() != 1) - return std::vector(); - - switch (Constraint[0]) { - default : break; - case 'r': - // GCC Mips Constraint Letters - case 'd': - case 'y': - return make_vector(Mips::T0, Mips::T1, Mips::T2, Mips::T3, - Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1, - Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7, - Mips::T8, 0); - - case 'f': - if (VT == MVT::f32) { - if (Subtarget->isSingleFloat()) - return make_vector(Mips::F2, Mips::F3, Mips::F4, Mips::F5, - Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11, - Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24, - Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29, - Mips::F30, Mips::F31, 0); - else - return make_vector(Mips::F2, Mips::F4, Mips::F6, Mips::F8, - Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26, - Mips::F28, Mips::F30, 0); - } - - if (VT == MVT::f64) - if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) - return make_vector(Mips::D1, Mips::D2, Mips::D3, Mips::D4, - Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13, - Mips::D14, Mips::D15, 0); - } - return std::vector(); -} - bool MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { // The Mips target isn't yet aware of offsets. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.h?rev=134084&r1=134083&r2=134084&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.h (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.h Wed Jun 29 14:04:31 2011 @@ -169,10 +169,6 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; - std::vector - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; - virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; /// isFPImmLegal - Returns true if the target can instruction select the From echristo at apple.com Wed Jun 29 14:12:24 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 19:12:24 -0000 Subject: [llvm-commits] [llvm] r134085 - in /llvm/trunk/lib/Target/MBlaze: MBlazeISelLowering.cpp MBlazeISelLowering.h Message-ID: <20110629191224.D253F2A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 14:12:24 2011 New Revision: 134085 URL: http://llvm.org/viewvc/llvm-project?rev=134085&view=rev Log: Remove getRegClassForInlineAsmConstraint from MBlaze. Add a TODO comment for the port. Part of rdar://9643582 Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp?rev=134085&r1=134084&r2=134085&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.cpp Wed Jun 29 14:12:24 2011 @@ -1114,15 +1114,19 @@ return weight; } -/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), -/// return a list of registers that can be used to satisfy the constraint. -/// This should only be used for C_RegisterClass constraints. +/// Given a register class constraint, like 'r', if this corresponds directly +/// to an LLVM register class, return a register of 0 and the register class +/// pointer. std::pair MBlazeTargetLowering:: getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { if (Constraint.size() == 1) { switch (Constraint[0]) { case 'r': return std::make_pair(0U, MBlaze::GPRRegisterClass); + // TODO: These can't possibly be right, but match what was in + // getRegClassForInlineAsmConstraint. + case 'd': + case 'y': case 'f': if (VT == MVT::f32) return std::make_pair(0U, MBlaze::GPRRegisterClass); @@ -1131,32 +1135,6 @@ return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } -/// Given a register class constraint, like 'r', if this corresponds directly -/// to an LLVM register class, return a register of 0 and the register class -/// pointer. -std::vector MBlazeTargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { - if (Constraint.size() != 1) - return std::vector(); - - switch (Constraint[0]) { - default : break; - case 'r': - // GCC MBlaze Constraint Letters - case 'd': - case 'y': - case 'f': - return make_vector( - MBlaze::R3, MBlaze::R4, MBlaze::R5, MBlaze::R6, - MBlaze::R7, MBlaze::R9, MBlaze::R10, MBlaze::R11, - MBlaze::R12, MBlaze::R19, MBlaze::R20, MBlaze::R21, - MBlaze::R22, MBlaze::R23, MBlaze::R24, MBlaze::R25, - MBlaze::R26, MBlaze::R27, MBlaze::R28, MBlaze::R29, - MBlaze::R30, MBlaze::R31, 0); - } - return std::vector(); -} - bool MBlazeTargetLowering:: isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { // The MBlaze target isn't yet aware of offsets. Modified: llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h?rev=134085&r1=134084&r2=134085&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeISelLowering.h Wed Jun 29 14:12:24 2011 @@ -173,10 +173,6 @@ getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; - std::vector - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; - virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; /// isFPImmLegal - Returns true if the target can instruction select the From echristo at apple.com Wed Jun 29 14:30:29 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 19:30:29 -0000 Subject: [llvm-commits] [llvm] r134086 - in /llvm/trunk/lib/Target/Blackfin: BlackfinISelLowering.cpp BlackfinISelLowering.h BlackfinRegisterInfo.td Message-ID: <20110629193029.DFD022A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 14:30:29 2011 New Revision: 134086 URL: http://llvm.org/viewvc/llvm-project?rev=134086&view=rev Log: Move the Blackfin port away from getRegClassForInlineAsmConstraint by creating a few specific register classes. Part of rdar://9643582 Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp?rev=134086&r1=134085&r2=134086&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.cpp Wed Jun 29 14:30:29 2011 @@ -621,39 +621,21 @@ case 'w': return Pair(0U, ALLRegisterClass); case 'Z': return Pair(P3, PRegisterClass); case 'Y': return Pair(P1, PRegisterClass); + case 'z': return Pair(0U, zConsRegisterClass); + case 'D': return Pair(0U, DConsRegisterClass); + case 'W': return Pair(0U, WConsRegisterClass); + case 'c': return Pair(0U, cConsRegisterClass); + case 't': return Pair(0U, tConsRegisterClass); + case 'u': return Pair(0U, uConsRegisterClass); + case 'k': return Pair(0U, kConsRegisterClass); + case 'y': return Pair(0U, yConsRegisterClass); } // Not implemented: q0-q7, qA. Use {R2} etc instead. - // Constraints z, D, W, c, t, u, k, and y use non-existing classes, defer to - // getRegClassForInlineAsmConstraint() return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } -std::vector BlackfinTargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { - using namespace BF; - - if (Constraint.size() != 1) - return std::vector(); - - switch (Constraint[0]) { - case 'z': return make_vector(P0, P1, P2, 0); - case 'D': return make_vector(R0, R2, R4, R6, 0); - case 'W': return make_vector(R1, R3, R5, R7, 0); - case 'c': return make_vector(I0, I1, I2, I3, - B0, B1, B2, B3, - L0, L1, L2, L3, 0); - case 't': return make_vector(LT0, LT1, 0); - case 'u': return make_vector(LB0, LB1, 0); - case 'k': return make_vector(LC0, LC1, 0); - case 'y': return make_vector(RETS, RETN, RETI, RETX, RETE, - ASTAT, SEQSTAT, USP, 0); - } - - return std::vector(); -} - bool BlackfinTargetLowering:: isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { // The Blackfin target isn't yet aware of offsets. Modified: llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h?rev=134086&r1=134085&r2=134086&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinISelLowering.h Wed Jun 29 14:30:29 2011 @@ -48,9 +48,6 @@ std::pair getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; - std::vector - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const; const char *getTargetNodeName(unsigned Opcode) const; Modified: llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td?rev=134086&r1=134085&r2=134086&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinRegisterInfo.td Wed Jun 29 14:30:29 2011 @@ -261,3 +261,17 @@ // Should be i40, but that isn't defined. It is not a legal type yet anyway. def Accu : RegisterClass<"BF", [i64], 64, (add A0, A1)>; + +// Register classes to match inline asm constraints. +def zCons : RegisterClass<"BF", [i32], 32, (add P0, P1, P2)>; +def DCons : RegisterClass<"BF", [i32], 32, (add R0, R2, R4, R6)>; +def WCons : RegisterClass<"BF", [i32], 32, (add R1, R3, R5, R7)>; +def cCons : RegisterClass<"BF", [i32], 32, (add I0, I1, I2, I3, + B0, B1, B2, B3, + L0, L1, L2, L3)>; +def tCons : RegisterClass<"BF", [i32], 32, (add LT0, LT1)>; +def uCons : RegisterClass<"BF", [i32], 32, (add LB0, LB1)>; +def kCons : RegisterClass<"BF", [i32], 32, (add LC0, LC1)>; +def yCons : RegisterClass<"BF", [i32], 32, (add RETS, RETN, RETI, RETX, + RETE, ASTAT, SEQSTAT, + USP)>; From echristo at apple.com Wed Jun 29 14:33:04 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 19:33:04 -0000 Subject: [llvm-commits] [llvm] r134087 - /llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Message-ID: <20110629193304.8EEEB2A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 14:33:04 2011 New Revision: 134087 URL: http://llvm.org/viewvc/llvm-project?rev=134087&view=rev Log: Update comment for getRegForInlineAsmConstraint for Mips. Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Modified: llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp?rev=134087&r1=134086&r2=134087&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsISelLowering.cpp Wed Jun 29 14:33:04 2011 @@ -2329,9 +2329,9 @@ return weight; } -/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), -/// return a list of registers that can be used to satisfy the constraint. -/// This should only be used for C_RegisterClass constraints. +/// Given a register class constraint, like 'r', if this corresponds directly +/// to an LLVM register class, return a register of 0 and the register class +/// pointer. std::pair MipsTargetLowering:: getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { From echristo at apple.com Wed Jun 29 14:40:01 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 19:40:01 -0000 Subject: [llvm-commits] [llvm] r134088 - in /llvm/trunk/lib/Target/Alpha: AlphaISelLowering.cpp AlphaISelLowering.h Message-ID: <20110629194001.6CB572A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 14:40:01 2011 New Revision: 134088 URL: http://llvm.org/viewvc/llvm-project?rev=134088&view=rev Log: Move Alpha from getRegClassForInlineAsmConstraint to getRegForInlineAsmConstraint. Part of rdar://9643582 Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=134088&r1=134087&r2=134088&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jun 29 14:40:01 2011 @@ -824,41 +824,23 @@ return weight; } -std::vector AlphaTargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const { +/// Given a register class constraint, like 'r', if this corresponds directly +/// to an LLVM register class, return a register of 0 and the register class +/// pointer. +std::pair AlphaTargetLowering:: +getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const +{ if (Constraint.size() == 1) { switch (Constraint[0]) { - default: break; // Unknown constriant letter - case 'f': - return make_vector(Alpha::F0 , Alpha::F1 , Alpha::F2 , - Alpha::F3 , Alpha::F4 , Alpha::F5 , - Alpha::F6 , Alpha::F7 , Alpha::F8 , - Alpha::F9 , Alpha::F10, Alpha::F11, - Alpha::F12, Alpha::F13, Alpha::F14, - Alpha::F15, Alpha::F16, Alpha::F17, - Alpha::F18, Alpha::F19, Alpha::F20, - Alpha::F21, Alpha::F22, Alpha::F23, - Alpha::F24, Alpha::F25, Alpha::F26, - Alpha::F27, Alpha::F28, Alpha::F29, - Alpha::F30, Alpha::F31, 0); case 'r': - return make_vector(Alpha::R0 , Alpha::R1 , Alpha::R2 , - Alpha::R3 , Alpha::R4 , Alpha::R5 , - Alpha::R6 , Alpha::R7 , Alpha::R8 , - Alpha::R9 , Alpha::R10, Alpha::R11, - Alpha::R12, Alpha::R13, Alpha::R14, - Alpha::R15, Alpha::R16, Alpha::R17, - Alpha::R18, Alpha::R19, Alpha::R20, - Alpha::R21, Alpha::R22, Alpha::R23, - Alpha::R24, Alpha::R25, Alpha::R26, - Alpha::R27, Alpha::R28, Alpha::R29, - Alpha::R30, Alpha::R31, 0); + return std::make_pair(0U, Alpha::GPRCRegisterClass); + case 'f': + return std::make_pair(0U, Alpha::F4RCRegisterClass); } } - - return std::vector(); + return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } + //===----------------------------------------------------------------------===// // Other Lowering Code //===----------------------------------------------------------------------===// Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h?rev=134088&r1=134087&r2=134088&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.h Wed Jun 29 14:40:01 2011 @@ -94,9 +94,9 @@ ConstraintWeight getSingleConstraintMatchWeight( AsmOperandInfo &info, const char *constraint) const; - std::vector - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; + std::pair + getRegForInlineAsmConstraint(const std::string &Constraint, + EVT VT) const; MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI, From echristo at apple.com Wed Jun 29 14:41:27 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 19:41:27 -0000 Subject: [llvm-commits] [llvm] r134089 - /llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Message-ID: <20110629194127.97F092A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 14:41:27 2011 New Revision: 134089 URL: http://llvm.org/viewvc/llvm-project?rev=134089&view=rev Log: Add a TODO for the Alpha port inline asm constraints. Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=134089&r1=134088&r2=134089&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jun 29 14:41:27 2011 @@ -835,6 +835,8 @@ case 'r': return std::make_pair(0U, Alpha::GPRCRegisterClass); case 'f': + // TODO: Do we need to add the 64-bit register class here when + // it contains the same registers? return std::make_pair(0U, Alpha::F4RCRegisterClass); } } From grosbach at apple.com Wed Jun 29 15:26:39 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 29 Jun 2011 20:26:39 -0000 Subject: [llvm-commits] [llvm] r134092 - in /llvm/trunk: lib/Target/ARM/ARMBaseInstrInfo.cpp lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/Thumb1FrameLowering.cpp lib/Target/ARM/Thumb1InstrInfo.cpp lib/Target/ARM/Thumb1RegisterInfo.cpp utils/TableGen/ARMDecoderEmitter.cpp Message-ID: <20110629202639.4CE342A6C12C@llvm.org> Author: grosbach Date: Wed Jun 29 15:26:39 2011 New Revision: 134092 URL: http://llvm.org/viewvc/llvm-project?rev=134092&view=rev Log: Refactor away tSpill and tRestore pseudos in ARM backend. The tSpill and tRestore instructions are just copies of the tSTRspi and tLDRspi instructions, respectively. Just use those directly instead. Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb.td llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=134092&r1=134091&r2=134092&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Wed Jun 29 15:26:39 2011 @@ -792,7 +792,7 @@ break; case ARM::STRi12: case ARM::t2STRi12: - case ARM::tSpill: + case ARM::tSTRspi: case ARM::VSTRD: case ARM::VSTRS: if (MI->getOperand(1).isFI() && @@ -927,7 +927,7 @@ break; case ARM::LDRi12: case ARM::t2LDRi12: - case ARM::tRestore: + case ARM::tLDRspi: case ARM::VLDRD: case ARM::VLDRS: if (MI->getOperand(1).isFI() && Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134092&r1=134091&r2=134092&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Wed Jun 29 15:26:39 2011 @@ -686,19 +686,6 @@ let Inst{7-0} = addr; } -// Special instruction for restore. It cannot clobber condition register -// when it's expanded by eliminateCallFramePseudoInstr(). -let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in -// FIXME: Pseudo for tLDRspi -def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i, - "ldr", "\t$dst, $addr", []>, - T1LdStSP<{1,?,?}> { - bits<3> Rt; - bits<8> addr; - let Inst{10-8} = Rt; - let Inst{7-0} = addr; -} - // Load tconstpool // FIXME: Use ldr.n to work around a Darwin assembler bug. let canFoldAsLoad = 1, isReMaterializable = 1 in @@ -755,19 +742,6 @@ let Inst{7-0} = addr; } -let mayStore = 1, neverHasSideEffects = 1 in -// Special instruction for spill. It cannot clobber condition register when it's -// expanded by eliminateCallFramePseudoInstr(). -// FIXME: Pseudo for tSTRspi -def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i, - "str", "\t$src, $addr", []>, - T1LdStSP<{0,?,?}> { - bits<3> Rt; - bits<8> addr; - let Inst{10-8} = Rt; - let Inst{7-0} = addr; -} - //===----------------------------------------------------------------------===// // Load / store multiple Instructions. // Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=134092&r1=134091&r2=134092&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Wed Jun 29 15:26:39 2011 @@ -177,7 +177,7 @@ } static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) { - if (MI->getOpcode() == ARM::tRestore && + if (MI->getOpcode() == ARM::tLDRspi && MI->getOperand(1).isFI() && isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs)) return true; Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=134092&r1=134091&r2=134092&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Wed Jun 29 15:26:39 2011 @@ -75,7 +75,7 @@ MachineMemOperand::MOStore, MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); - AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSpill)) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tSTRspi)) .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); } @@ -104,7 +104,7 @@ MachineMemOperand::MOLoad, MFI.getObjectSize(FI), MFI.getObjectAlignment(FI)); - AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tRestore), DestReg) + AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) .addFrameIndex(FI).addImm(0).addMemOperand(MMO)); } } Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=134092&r1=134091&r2=134092&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Wed Jun 29 15:26:39 2011 @@ -377,11 +377,9 @@ static unsigned convertToNonSPOpcode(unsigned Opcode) { switch (Opcode) { case ARM::tLDRspi: - case ARM::tRestore: // FIXME: Should this opcode be here? return ARM::tLDRi; case ARM::tSTRspi: - case ARM::tSpill: // FIXME: Should this opcode be here? return ARM::tSTRi; } @@ -524,7 +522,7 @@ // If this is a thumb spill / restore, we will be using a constpool load to // materialize the offset. - if (Opcode == ARM::tRestore || Opcode == ARM::tSpill) { + if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi) { ImmOp.ChangeToImmediate(0); } else { // Otherwise, it didn't fit. Pull in what we can to simplify the immed. @@ -664,7 +662,7 @@ // Use the destination register to materialize sp + offset. unsigned TmpReg = MI.getOperand(0).getReg(); bool UseRR = false; - if (Opcode == ARM::tRestore) { + if (Opcode == ARM::tLDRspi) { if (FrameReg == ARM::SP) emitThumbRegPlusImmInReg(MBB, II, dl, TmpReg, FrameReg, Offset, false, TII, *this); @@ -687,7 +685,7 @@ VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass); bool UseRR = false; - if (Opcode == ARM::tSpill) { + if (Opcode == ARM::tSTRspi) { if (FrameReg == ARM::SP) emitThumbRegPlusImmInReg(MBB, II, dl, VReg, FrameReg, Offset, false, TII, *this); Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=134092&r1=134091&r2=134092&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Wed Jun 29 15:26:39 2011 @@ -1667,14 +1667,12 @@ // tPOP_RET/t2LDMIA_RET conflict with tPOP/t2LDM (ditto) // tMOVCCi conflicts with tMOVi8 // tMOVCCr conflicts with tMOVgpr2gpr - // tSpill conflicts with tSTRspi // tLDRcp conflicts with tLDRspi - // tRestore conflicts with tLDRspi // t2MOVCCi16 conflicts with tMOVi16 if (Name == "tBfar" || Name == "tPOP_RET" || Name == "t2LDMIA_RET" || Name == "tMOVCCi" || Name == "tMOVCCr" || - Name == "tSpill" || Name == "tLDRcp" || Name == "tRestore" || + Name == "tLDRcp" || Name == "t2MOVCCi16") return false; } From rafael.espindola at gmail.com Wed Jun 29 15:55:49 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Wed, 29 Jun 2011 20:55:49 -0000 Subject: [llvm-commits] [llvm] r134093 - in /llvm/trunk/lib/CodeGen: RegisterCoalescer.cpp RegisterCoalescer.h Message-ID: <20110629205549.2883E2A6C12C@llvm.org> Author: rafael Date: Wed Jun 29 15:55:48 2011 New Revision: 134093 URL: http://llvm.org/viewvc/llvm-project?rev=134093&view=rev Log: make compose and isMoveInstr static functions. Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp llvm/trunk/lib/CodeGen/RegisterCoalescer.h Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=134093&r1=134092&r2=134093&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original) +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Wed Jun 29 15:55:48 2011 @@ -90,15 +90,15 @@ char RegisterCoalescer::ID = 0; -unsigned CoalescerPair::compose(unsigned a, unsigned b) const { +static unsigned compose(const TargetRegisterInfo &tri, unsigned a, unsigned b) { if (!a) return b; if (!b) return a; - return tri_.composeSubRegIndices(a, b); + return tri.composeSubRegIndices(a, b); } -bool CoalescerPair::isMoveInstr(const MachineInstr *MI, - unsigned &Src, unsigned &Dst, - unsigned &SrcSub, unsigned &DstSub) const { +static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI, + unsigned &Src, unsigned &Dst, + unsigned &SrcSub, unsigned &DstSub) { if (MI->isCopy()) { Dst = MI->getOperand(0).getReg(); DstSub = MI->getOperand(0).getSubReg(); @@ -106,7 +106,8 @@ SrcSub = MI->getOperand(1).getSubReg(); } else if (MI->isSubregToReg()) { Dst = MI->getOperand(0).getReg(); - DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm()); + DstSub = compose(tri, MI->getOperand(0).getSubReg(), + MI->getOperand(3).getImm()); Src = MI->getOperand(2).getReg(); SrcSub = MI->getOperand(2).getSubReg(); } else @@ -120,7 +121,7 @@ flipped_ = crossClass_ = false; unsigned Src, Dst, SrcSub, DstSub; - if (!isMoveInstr(MI, Src, Dst, SrcSub, DstSub)) + if (!isMoveInstr(tri_, MI, Src, Dst, SrcSub, DstSub)) return false; partial_ = SrcSub || DstSub; @@ -210,7 +211,7 @@ if (!MI) return false; unsigned Src, Dst, SrcSub, DstSub; - if (!isMoveInstr(MI, Src, Dst, SrcSub, DstSub)) + if (!isMoveInstr(tri_, MI, Src, Dst, SrcSub, DstSub)) return false; // Find the virtual register that is srcReg_. @@ -239,7 +240,7 @@ if (dstReg_ != Dst) return false; // Registers match, do the subregisters line up? - return compose(subIdx_, SrcSub) == DstSub; + return compose(tri_, subIdx_, SrcSub) == DstSub; } } Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.h?rev=134093&r1=134092&r2=134093&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.h (original) +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.h Wed Jun 29 15:55:48 2011 @@ -281,13 +281,6 @@ /// is a physreg. const TargetRegisterClass *newRC_; - /// compose - Compose subreg indices a and b, either may be 0. - unsigned compose(unsigned, unsigned) const; - - /// isMoveInstr - Return true if MI is a move or subreg instruction. - bool isMoveInstr(const MachineInstr *MI, unsigned &Src, unsigned &Dst, - unsigned &SrcSub, unsigned &DstSub) const; - public: CoalescerPair(const TargetInstrInfo &tii, const TargetRegisterInfo &tri) : tii_(tii), tri_(tri), dstReg_(0), srcReg_(0), subIdx_(0), From yuri at rawbw.com Wed Jun 29 16:04:35 2011 From: yuri at rawbw.com (Yuri) Date: Wed, 29 Jun 2011 14:04:35 -0700 Subject: [llvm-commits] [LLVMdev] How to identify LLVM version? [updated patch] In-Reply-To: <4DE93048.7070706@rawbw.com> References: <81AE5BE6-D456-472B-9AF3-1EF93FF17D23@gmail.com> <87hb8a1xk8.fsf@wanadoo.es> <4DE54671.5080804@free.fr> <4DE54F97.10004@rawbw.com> <4DE64C80.1070900@free.fr> <4DE93048.7070706@rawbw.com> Message-ID: <4E0B9363.6040807@rawbw.com> On 06/03/2011 12:04, Yuri wrote: > Following the suggestions of Joachim Durchholz and Csaba Raduly, I > submit the updated patch. Could somebody check in this patch? I think it got lost in mailing lists llvmdev@ and llvm-commits@ and forgotten about. Thank you, Yuri -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: patch.txt Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110629/82939626/attachment-0001.txt From echristo at apple.com Wed Jun 29 16:05:55 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 21:05:55 -0000 Subject: [llvm-commits] [llvm] r134094 - /llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Message-ID: <20110629210555.1F3062A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 16:05:54 2011 New Revision: 134094 URL: http://llvm.org/viewvc/llvm-project?rev=134094&view=rev Log: Remove todo. Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=134094&r1=134093&r2=134094&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jun 29 16:05:54 2011 @@ -835,8 +835,6 @@ case 'r': return std::make_pair(0U, Alpha::GPRCRegisterClass); case 'f': - // TODO: Do we need to add the 64-bit register class here when - // it contains the same registers? return std::make_pair(0U, Alpha::F4RCRegisterClass); } } From echristo at apple.com Wed Jun 29 16:10:36 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 21:10:36 -0000 Subject: [llvm-commits] [llvm] r134095 - in /llvm/trunk/lib/Target/ARM: ARMISelLowering.cpp ARMISelLowering.h Message-ID: <20110629211036.E22B62A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 16:10:36 2011 New Revision: 134095 URL: http://llvm.org/viewvc/llvm-project?rev=134095&view=rev Log: Remove getRegClassForInlineAsmConstraint from the ARM port. Part of rdar://9643582 Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp llvm/trunk/lib/Target/ARM/ARMISelLowering.h Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134095&r1=134094&r2=134095&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Wed Jun 29 16:10:36 2011 @@ -5526,7 +5526,7 @@ return SDValue(); } -// AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction +// AddCombineToVPADDL- For pair-wise add on neon, use the vpaddl instruction // (only after legalization). static SDValue AddCombineToVPADDL(SDNode *N, SDValue N0, SDValue N1, TargetLowering::DAGCombinerInfo &DCI, @@ -5557,25 +5557,25 @@ SDNode *V = Vec.getNode(); unsigned nextIndex = 0; - // For each operands to the ADD which are BUILD_VECTORs, + // For each operands to the ADD which are BUILD_VECTORs, // check to see if each of their operands are an EXTRACT_VECTOR with // the same vector and appropriate index. for (unsigned i = 0, e = N0->getNumOperands(); i != e; ++i) { if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) { - + SDValue ExtVec0 = N0->getOperand(i); SDValue ExtVec1 = N1->getOperand(i); - + // First operand is the vector, verify its the same. if (V != ExtVec0->getOperand(0).getNode() || V != ExtVec1->getOperand(0).getNode()) return SDValue(); - + // Second is the constant, verify its correct. ConstantSDNode *C0 = dyn_cast(ExtVec0->getOperand(1)); ConstantSDNode *C1 = dyn_cast(ExtVec1->getOperand(1)); - + // For the constant, we want to see all the even or all the odd. if (!C0 || !C1 || C0->getZExtValue() != nextIndex || C1->getZExtValue() != nextIndex+1) @@ -5583,7 +5583,7 @@ // Increment index. nextIndex+=2; - } else + } else return SDValue(); } @@ -5598,7 +5598,7 @@ // Input is the vector. Ops.push_back(Vec); - + // Get widened type and narrowed type. MVT widenType; unsigned numElem = VT.getVectorNumElements(); @@ -5627,7 +5627,7 @@ SDValue Result = AddCombineToVPADDL(N, N0, N1, DCI, Subtarget); if (Result.getNode()) return Result; - + // fold (add (select cc, 0, c), x) -> (select cc, x, (add, x, c)) if (N0.getOpcode() == ISD::SELECT && N0.getNode()->hasOneUse()) { SDValue Result = combineSelectAndUse(N, N0, N1, DCI); @@ -6482,7 +6482,7 @@ return DCI.DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); } -// isConstVecPow2 - Return true if each vector element is a power of 2, all +// isConstVecPow2 - Return true if each vector element is a power of 2, all // elements are the same constant, C, and Log2(C) ranges from 1 to 32. static bool isConstVecPow2(SDValue ConstVec, bool isSigned, uint64_t &C) { @@ -6494,7 +6494,7 @@ if (!C) return false; - bool isExact; + bool isExact; APFloat APF = C->getValueAPF(); if (APF.convertToInteger(&cN, 64, isSigned, APFloat::rmTowardZero, &isExact) != APFloat::opOK || !isExact) @@ -6532,7 +6532,7 @@ SDValue ConstVec = Op->getOperand(1); bool isSigned = N->getOpcode() == ISD::FP_TO_SINT; - if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || + if (ConstVec.getOpcode() != ISD::BUILD_VECTOR || !isConstVecPow2(ConstVec, isSigned, C)) return SDValue(); @@ -6540,7 +6540,7 @@ Intrinsic::arm_neon_vcvtfp2fxu; return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), N->getValueType(0), - DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, + DAG.getConstant(IntrinsicOpcode, MVT::i32), N0, DAG.getConstant(Log2_64(C), MVT::i32)); } @@ -6572,11 +6572,11 @@ !isConstVecPow2(ConstVec, isSigned, C)) return SDValue(); - unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : + unsigned IntrinsicOpcode = isSigned ? Intrinsic::arm_neon_vcvtfxs2fp : Intrinsic::arm_neon_vcvtfxu2fp; return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, N->getDebugLoc(), Op.getValueType(), - DAG.getConstant(IntrinsicOpcode, MVT::i32), + DAG.getConstant(IntrinsicOpcode, MVT::i32), Op.getOperand(0), DAG.getConstant(Log2_64(C), MVT::i32)); } @@ -7556,47 +7556,6 @@ return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); } -std::vector ARMTargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const { - if (Constraint.size() != 1) - return std::vector(); - - switch (Constraint[0]) { // GCC ARM Constraint Letters - default: break; - case 'l': - return make_vector(ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R4, ARM::R5, ARM::R6, ARM::R7, - 0); - case 'r': - return make_vector(ARM::R0, ARM::R1, ARM::R2, ARM::R3, - ARM::R4, ARM::R5, ARM::R6, ARM::R7, - ARM::R8, ARM::R9, ARM::R10, ARM::R11, - ARM::R12, ARM::LR, 0); - case 'w': - if (VT == MVT::f32) - return make_vector(ARM::S0, ARM::S1, ARM::S2, ARM::S3, - ARM::S4, ARM::S5, ARM::S6, ARM::S7, - ARM::S8, ARM::S9, ARM::S10, ARM::S11, - ARM::S12,ARM::S13,ARM::S14,ARM::S15, - ARM::S16,ARM::S17,ARM::S18,ARM::S19, - ARM::S20,ARM::S21,ARM::S22,ARM::S23, - ARM::S24,ARM::S25,ARM::S26,ARM::S27, - ARM::S28,ARM::S29,ARM::S30,ARM::S31, 0); - if (VT.getSizeInBits() == 64) - return make_vector(ARM::D0, ARM::D1, ARM::D2, ARM::D3, - ARM::D4, ARM::D5, ARM::D6, ARM::D7, - ARM::D8, ARM::D9, ARM::D10,ARM::D11, - ARM::D12,ARM::D13,ARM::D14,ARM::D15, 0); - if (VT.getSizeInBits() == 128) - return make_vector(ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, - ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 0); - break; - } - - return std::vector(); -} - /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. void ARMTargetLowering::LowerAsmOperandForConstraint(SDValue Op, Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.h?rev=134095&r1=134094&r2=134095&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMISelLowering.h (original) +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.h Wed Jun 29 16:10:36 2011 @@ -306,9 +306,6 @@ std::pair getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; - std::vector - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops /// vector. If it is invalid, don't add anything to Ops. If hasMemory is From rafael.espindola at gmail.com Wed Jun 29 16:46:25 2011 From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=) Date: Wed, 29 Jun 2011 17:46:25 -0400 Subject: [llvm-commits] [patch] Improve register coalescing Message-ID: <4E0B9D31.3020101@gmail.com> This patch improves register coalescing so that it doesn't give up on coalescing A and B if a BB contains: A = X B = X Instead, we pretend that it was A = X B = A This helps a lot in some degenerate cases, but help even in more common ones. A self hosted clang goes from 33627704 to 33626776 bytes, but jsinterp.o in firefox goes from 2069728 to 1598504 bytes. This also speeds up the hard case. llc on jsinterp.bc goes from 23.17s to 13.34s. Cheers, Rafael -------------- next part -------------- An embedded and charset-unspecified text was scrubbed... Name: PR10096.patch Url: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110629/2aa23d59/attachment.pl From evan.cheng at apple.com Wed Jun 29 16:58:38 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 29 Jun 2011 21:58:38 -0000 Subject: [llvm-commits] [llvm] r134100 - /llvm/trunk/include/llvm/MC/MCInstrInfo.h Message-ID: <20110629215838.21CBB2A6C12C@llvm.org> Author: evancheng Date: Wed Jun 29 16:58:37 2011 New Revision: 134100 URL: http://llvm.org/viewvc/llvm-project?rev=134100&view=rev Log: Indentation Modified: llvm/trunk/include/llvm/MC/MCInstrInfo.h Modified: llvm/trunk/include/llvm/MC/MCInstrInfo.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCInstrInfo.h?rev=134100&r1=134099&r2=134100&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/MCInstrInfo.h (original) +++ llvm/trunk/include/llvm/MC/MCInstrInfo.h Wed Jun 29 16:58:37 2011 @@ -25,7 +25,7 @@ /// class MCInstrInfo { const MCInstrDesc *Desc; // Raw array to allow static init'n - unsigned NumOpcodes; // Number of entries in the desc array + unsigned NumOpcodes; // Number of entries in the desc array public: /// InitMCInstrInfo - Initialize MCInstrInfo, called by TableGen From grosbach at apple.com Wed Jun 29 17:01:15 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 29 Jun 2011 22:01:15 -0000 Subject: [llvm-commits] [llvm] r134101 - /llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Message-ID: <20110629220115.7E2D52A6C12C@llvm.org> Author: grosbach Date: Wed Jun 29 17:01:15 2011 New Revision: 134101 URL: http://llvm.org/viewvc/llvm-project?rev=134101&view=rev Log: ARM RSCS* don't need explicit TableGen decoder checks. They've been pseudos for a while now, so the decoder will never see them in the first place. Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=134101&r1=134100&r2=134101&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Wed Jun 29 17:01:15 2011 @@ -1592,10 +1592,6 @@ // The following special cases are for conflict resolutions. // - // RSCSri and RSCSrs set the 's' bit, but are not predicated. We are - // better off using the generic RSCri and RSCrs instructions. - if (Name == "RSCSri" || Name == "RSCSrs") return false; - // A8-598: VEXT // Vector Extract extracts elements from the bottom end of the second // operand vector and the top end of the first, concatenates them and From zwarich at apple.com Wed Jun 29 17:24:25 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 29 Jun 2011 22:24:25 -0000 Subject: [llvm-commits] [llvm] r134106 - in /llvm/trunk: lib/Target/ARM/ARMGlobalMerge.cpp test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll Message-ID: <20110629222425.4D2712A6C12C@llvm.org> Author: zwarich Date: Wed Jun 29 17:24:25 2011 New Revision: 134106 URL: http://llvm.org/viewvc/llvm-project?rev=134106&view=rev Log: In the ARM global merging pass, allow extraneous alignment specifiers. This pass already makes the assumption, which is correct on ARM, that a type's alignment is less than its alloc size. This improves codegen with Clang (which inserts a lot of extraneous alignment specifiers) and fixes . Added: llvm/trunk/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll Modified: llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp Modified: llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp?rev=134106&r1=134105&r2=134106&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMGlobalMerge.cpp Wed Jun 29 17:24:25 2011 @@ -175,7 +175,9 @@ continue; // Ignore fancy-aligned globals for now. - if (I->getAlignment() != 0) + unsigned Alignment = I->getAlignment(); + unsigned AllocSize = TD->getTypeAllocSize(I->getType()->getElementType()); + if (Alignment > AllocSize) continue; // Ignore all 'special' globals. @@ -183,7 +185,7 @@ I->getName().startswith(".llvm.")) continue; - if (TD->getTypeAllocSize(I->getType()->getElementType()) < MaxOffset) { + if (AllocSize < MaxOffset) { const TargetLoweringObjectFile &TLOF = TLI->getObjFileLowering(); if (TLOF.getKindForGlobal(I, TLI->getTargetMachine()).isBSSLocal()) BSSGlobals.push_back(I); Added: llvm/trunk/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll?rev=134106&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll (added) +++ llvm/trunk/test/CodeGen/ARM/2011-06-29-MergeGlobalsAlign.ll Wed Jun 29 17:24:25 2011 @@ -0,0 +1,12 @@ +; RUN: llc < %s -mtriple=thumbv7-apple-darwin10 | FileCheck %s +; CHECK: .zerofill __DATA,__bss,__MergedGlobals,16,2 + +%struct.config = type { i16, i16, i16, i16 } + + at prev = external global [0 x i16] + at max_lazy_match = internal unnamed_addr global i32 0, align 4 + at read_buf = external global i32 (i8*, i32)* + at window = external global [0 x i8] + at lookahead = internal unnamed_addr global i32 0, align 4 + at eofile.b = internal unnamed_addr global i1 false + at ins_h = internal unnamed_addr global i32 0, align 4 From zwarich at apple.com Wed Jun 29 17:27:41 2011 From: zwarich at apple.com (Cameron Zwarich) Date: Wed, 29 Jun 2011 15:27:41 -0700 Subject: [llvm-commits] [patch] Improve register coalescing In-Reply-To: <4E0B9D31.3020101@gmail.com> References: <4E0B9D31.3020101@gmail.com> Message-ID: <47D567BF-7072-491F-A225-A2CC0485E54A@apple.com> Have you done any compile time testing? Cameron On Jun 29, 2011, at 2:46 PM, Rafael ?vila de Esp?ndola wrote: > This patch improves register coalescing so that it doesn't give up on coalescing A and B if a BB contains: > > A = X > B = X > > Instead, we pretend that it was > > A = X > B = A > > This helps a lot in some degenerate cases, but help even in more common ones. A self hosted clang goes from 33627704 to 33626776 bytes, but jsinterp.o in firefox goes from 2069728 to 1598504 bytes. > > This also speeds up the hard case. llc on jsinterp.bc goes from 23.17s to 13.34s. > > Cheers, > Rafael > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Wed Jun 29 17:34:18 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 29 Jun 2011 15:34:18 -0700 Subject: [llvm-commits] [patch] Improve register coalescing In-Reply-To: <4E0B9D31.3020101@gmail.com> References: <4E0B9D31.3020101@gmail.com> Message-ID: <5C5CA408-CEC6-49E2-88CF-55C315AF3D97@2pi.dk> On Jun 29, 2011, at 2:46 PM, Rafael ?vila de Esp?ndola wrote: > This patch improves register coalescing so that it doesn't give up on coalescing A and B if a BB contains: > > A = X > B = X > > Instead, we pretend that it was > > A = X > B = A > > This helps a lot in some degenerate cases, but help even in more common ones. A self hosted clang goes from 33627704 to 33626776 bytes, but jsinterp.o in firefox goes from 2069728 to 1598504 bytes. > > This also speeds up the hard case. llc on jsinterp.bc goes from 23.17s to 13.34s. Nice! > +static bool RegistersDefinedFromSameValue(const TargetRegisterInfo &tri, > + CoalescerPair &CP, MachineInstr *MI, > + LiveRange *lr, > + SmallVector &DupCopies) { > + This function is a little weird, it is not really clear what the arguments mean, or what the function does. Please add more comments. > + unsigned Src, Dst, SrcSub, DstSub; > + if (!isMoveInstr(tri, MI, Src, Dst, SrcSub, DstSub)) > + return false; > + > + if (!MI->isCopy() || SrcSub || DstSub || > + !TargetRegisterInfo::isVirtualRegister(Src) || > + !TargetRegisterInfo::isVirtualRegister(Dst)) > + return false; This is pretty convoluted. First you check for a general copy-like instruction, and then you restrict to only copies afterwards. I think is it better to add a MI->isFullCopy that returns true for copies without sub-register operands. See also isFullCopyOf() in InlineSpiller.cpp. > + if (!TargetRegisterInfo::isVirtualRegister(A) || > + !TargetRegisterInfo::isVirtualRegister(B)) > + return false; A.k.a CP.isPhys() I am not completely sure you are handling sub-registers correctly. You should probably disable this when CP.isPartial(). Would it be possible to do more complete value-based checking? For example, you don't handle this: X = Y A = X B = Y Thanks for working on this! /jakob From jediknil at belkadan.com Wed Jun 29 13:57:12 2011 From: jediknil at belkadan.com (Jordy Rose) Date: Wed, 29 Jun 2011 11:57:12 -0700 Subject: [llvm-commits] [patch] Fix deprecation warning in lit on OS X Message-ID: <5147384C-15F5-428E-8079-B5C3D6BDF46D@belkadan.com> I usually hang out on the Clang side of things, but I've noticed that the lit tests have a deprecation warning about 'popen2' that comes up on OS X. The attached patch replaces the use of 'popen2' with 'subprocess.Popen'. Jordy -------------- next part -------------- A non-text attachment was scrubbed... Name: Util.py.patch Type: application/octet-stream Size: 692 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110629/ade7a518/attachment.obj From atrick at apple.com Wed Jun 29 17:52:52 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 29 Jun 2011 22:52:52 -0000 Subject: [llvm-commits] [llvm] r134110 - /llvm/trunk/include/llvm/Support/IRBuilder.h Message-ID: <20110629225252.103802A6C12C@llvm.org> Author: atrick Date: Wed Jun 29 17:52:51 2011 New Revision: 134110 URL: http://llvm.org/viewvc/llvm-project?rev=134110&view=rev Log: whitespace Modified: llvm/trunk/include/llvm/Support/IRBuilder.h Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=134110&r1=134109&r2=134110&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Wed Jun 29 17:52:51 2011 @@ -82,7 +82,7 @@ InsertPt = I; SetCurrentDebugLocation(I->getDebugLoc()); } - + /// SetInsertPoint - This specifies that created instructions should be /// inserted at the specified point. void SetInsertPoint(BasicBlock *TheBB, BasicBlock::iterator IP) { @@ -110,7 +110,7 @@ /// getCurrentFunctionReturnType - Get the return type of the current function /// that we're emitting into. const Type *getCurrentFunctionReturnType() const; - + /// InsertPoint - A saved insertion point. class InsertPoint { BasicBlock *Block; @@ -198,7 +198,7 @@ ConstantInt *getInt64(uint64_t C) { return ConstantInt::get(getInt64Ty(), C); } - + /// getInt - Get a constant integer value. ConstantInt *getInt(const APInt &AI) { return ConstantInt::get(Context, AI); @@ -263,7 +263,7 @@ bool isVolatile = false, MDNode *TBAATag = 0) { return CreateMemSet(Ptr, Val, getInt64(Size), Align, isVolatile, TBAATag); } - + CallInst *CreateMemSet(Value *Ptr, Value *Val, Value *Size, unsigned Align, bool isVolatile = false, MDNode *TBAATag = 0); @@ -274,7 +274,7 @@ bool isVolatile = false, MDNode *TBAATag = 0) { return CreateMemCpy(Dst, Src, getInt64(Size), Align, isVolatile, TBAATag); } - + CallInst *CreateMemCpy(Value *Dst, Value *Src, Value *Size, unsigned Align, bool isVolatile = false, MDNode *TBAATag = 0); @@ -285,9 +285,9 @@ bool isVolatile = false, MDNode *TBAATag = 0) { return CreateMemMove(Dst, Src, getInt64(Size), Align, isVolatile, TBAATag); } - + CallInst *CreateMemMove(Value *Dst, Value *Src, Value *Size, unsigned Align, - bool isVolatile = false, MDNode *TBAATag = 0); + bool isVolatile = false, MDNode *TBAATag = 0); /// CreateLifetimeStart - Create a lifetime.start intrinsic. If the pointer /// isn't i8* it will be converted. @@ -341,7 +341,7 @@ SetInsertPoint(IP); SetCurrentDebugLocation(IP->getDebugLoc()); } - + IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP, const T& F) : IRBuilderBase(TheBB->getContext()), Folder(F) { SetInsertPoint(TheBB, IP); From atrick at apple.com Wed Jun 29 18:01:52 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 29 Jun 2011 23:01:52 -0000 Subject: [llvm-commits] [llvm] r134111 - /llvm/trunk/include/llvm/Support/IRBuilder.h Message-ID: <20110629230152.6703E2A6C12C@llvm.org> Author: atrick Date: Wed Jun 29 18:01:52 2011 New Revision: 134111 URL: http://llvm.org/viewvc/llvm-project?rev=134111&view=rev Log: Added IRBuilder::SetInsertPoint(Use) to find a valid insertion point that dominates the given Use. Modified: llvm/trunk/include/llvm/Support/IRBuilder.h Modified: llvm/trunk/include/llvm/Support/IRBuilder.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Support/IRBuilder.h?rev=134111&r1=134110&r2=134111&view=diff ============================================================================== --- llvm/trunk/include/llvm/Support/IRBuilder.h (original) +++ llvm/trunk/include/llvm/Support/IRBuilder.h Wed Jun 29 18:01:52 2011 @@ -90,6 +90,19 @@ InsertPt = IP; } + /// SetInsertPoint(Use) - Find the nearest point that dominates this use, and + /// specify that created instructions should be inserted at this point. + void SetInsertPoint(Use &U) { + Instruction *UseInst = cast(U.getUser()); + if (PHINode *Phi = dyn_cast(UseInst)) { + BasicBlock *PredBB = Phi->getIncomingBlock(U); + assert(U != PredBB->getTerminator() && "critical edge not split"); + SetInsertPoint(PredBB, PredBB->getTerminator()); + return; + } + SetInsertPoint(UseInst); + } + /// SetCurrentDebugLocation - Set location information used by debugging /// information. void SetCurrentDebugLocation(const DebugLoc &L) { @@ -342,6 +355,12 @@ SetCurrentDebugLocation(IP->getDebugLoc()); } + explicit IRBuilder(Use &U) + : IRBuilderBase(U->getContext()), Folder() { + SetInsertPoint(U); + SetCurrentDebugLocation(cast(U.getUser())->getDebugLoc()); + } + IRBuilder(BasicBlock *TheBB, BasicBlock::iterator IP, const T& F) : IRBuilderBase(TheBB->getContext()), Folder(F) { SetInsertPoint(TheBB, IP); From atrick at apple.com Wed Jun 29 18:03:57 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 29 Jun 2011 23:03:57 -0000 Subject: [llvm-commits] [llvm] r134112 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/no-iv-rewrite.ll Message-ID: <20110629230357.546812A6C12C@llvm.org> Author: atrick Date: Wed Jun 29 18:03:57 2011 New Revision: 134112 URL: http://llvm.org/viewvc/llvm-project?rev=134112&view=rev Log: indvars -disable-iv-rewrite: insert new trunc instructions carefully. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=134112&r1=134111&r2=134112&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Wed Jun 29 18:03:57 2011 @@ -609,8 +609,7 @@ const SCEVAddRecExpr *GetWideRecurrence(Instruction *NarrowUse); - Instruction *WidenIVUse(Instruction *NarrowUse, - Instruction *NarrowDef, + Instruction *WidenIVUse(Use &NarrowDefUse, Instruction *NarrowDef, Instruction *WideDef); }; } // anonymous namespace @@ -724,9 +723,10 @@ /// WidenIVUse - Determine whether an individual user of the narrow IV can be /// widened. If so, return the wide clone of the user. -Instruction *WidenIV::WidenIVUse(Instruction *NarrowUse, - Instruction *NarrowDef, +Instruction *WidenIV::WidenIVUse(Use &NarrowDefUse, Instruction *NarrowDef, Instruction *WideDef) { + Instruction *NarrowUse = cast(NarrowDefUse.getUser()); + // To be consistent with IVUsers, stop traversing the def-use chain at // inner-loop phis or post-loop phis. if (isa(NarrowUse) && LI->getLoopFor(NarrowUse->getParent()) != L) @@ -744,7 +744,7 @@ unsigned IVWidth = SE->getTypeSizeInBits(WideType); if (CastWidth < IVWidth) { // The cast isn't as wide as the IV, so insert a Trunc. - IRBuilder<> Builder(NarrowUse); + IRBuilder<> Builder(NarrowDefUse); NewDef = Builder.CreateTrunc(WideDef, NarrowUse->getType()); } else { @@ -778,11 +778,15 @@ // This user does not evaluate to a recurence after widening, so don't // follow it. Instead insert a Trunc to kill off the original use, // eventually isolating the original narrow IV so it can be removed. - IRBuilder<> Builder(NarrowUse); + IRBuilder<> Builder(NarrowDefUse); Value *Trunc = Builder.CreateTrunc(WideDef, NarrowDef->getType()); NarrowUse->replaceUsesOfWith(NarrowDef, Trunc); return 0; } + // We assume that block terminators are not SCEVable. + assert(NarrowUse != NarrowUse->getParent()->getTerminator() && + "can't split terminators"); + // Reuse the IV increment that SCEVExpander created as long as it dominates // NarrowUse. Instruction *WideUse = 0; @@ -876,20 +880,20 @@ NarrowIVUsers.push_back(std::make_pair(&UI.getUse(), WidePhi)); } while (!NarrowIVUsers.empty()) { - Use *NarrowDefUse; + Use *UsePtr; Instruction *WideDef; - tie(NarrowDefUse, WideDef) = NarrowIVUsers.pop_back_val(); + tie(UsePtr, WideDef) = NarrowIVUsers.pop_back_val(); + Use &NarrowDefUse = *UsePtr; // Process a def-use edge. This may replace the use, so don't hold a // use_iterator across it. - Instruction *NarrowDef = cast(NarrowDefUse->get()); - Instruction *NarrowUse = cast(NarrowDefUse->getUser()); - Instruction *WideUse = WidenIVUse(NarrowUse, NarrowDef, WideDef); + Instruction *NarrowDef = cast(NarrowDefUse.get()); + Instruction *WideUse = WidenIVUse(NarrowDefUse, NarrowDef, WideDef); // Follow all def-use edges from the previous narrow use. if (WideUse) { - for (Value::use_iterator UI = NarrowUse->use_begin(), - UE = NarrowUse->use_end(); UI != UE; ++UI) { + for (Value::use_iterator UI = NarrowDefUse.getUser()->use_begin(), + UE = NarrowDefUse.getUser()->use_end(); UI != UE; ++UI) { NarrowIVUsers.push_back(std::make_pair(&UI.getUse(), WideUse)); } } @@ -1051,6 +1055,10 @@ // Get the symbolic expression for this instruction. const SCEV *S = SE->getSCEV(I); + // We assume that terminators are not SCEVable. + assert((!S || I != I->getParent()->getTerminator()) && + "can't fold terminators"); + // Only consider affine recurrences. const SCEVAddRecExpr *AR = dyn_cast(S); if (AR && AR->getLoop() == L) Modified: llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll?rev=134112&r1=134111&r2=134112&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Wed Jun 29 18:03:57 2011 @@ -153,8 +153,37 @@ br i1 %cond, label %loop, label %exit exit: - br label %return + ret void +} + +define void @maxvisitor(i32 %limit, i32* %base) nounwind { +entry: br label %loop + +; CHECK: loop: +; CHECK: phi i64 +; CHECK: trunc +; CHECK: exit +loop: + %idx = phi i32 [ 0, %entry ], [ %idx.next, %loop.inc ] + %max = phi i32 [ 0, %entry ], [ %max.next, %loop.inc ] + %idxprom = sext i32 %idx to i64 + %adr = getelementptr inbounds i32* %base, i64 %idxprom + %val = load i32* %adr + %cmp19 = icmp sgt i32 %val, %max + br i1 %cmp19, label %if.then, label %if.else + +if.then: + br label %loop.inc -return: +if.else: + br label %loop.inc + +loop.inc: + %max.next = phi i32 [ %idx, %if.then ], [ %max, %if.else ] + %idx.next = add nsw i32 %idx, 1 + %cmp = icmp slt i32 %idx.next, %limit + br i1 %cmp, label %loop, label %exit + +exit: ret void } \ No newline at end of file From stoklund at 2pi.dk Wed Jun 29 18:02:54 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 29 Jun 2011 16:02:54 -0700 Subject: [llvm-commits] [llvm] r133900 - /llvm/trunk/lib/CodeGen/RegisterCoalescer.h In-Reply-To: <20110626224434.34C852A6C12C@llvm.org> References: <20110626224434.34C852A6C12C@llvm.org> Message-ID: <19463153-E824-45CE-803B-E5E976157117@2pi.dk> On Jun 26, 2011, at 3:44 PM, Rafael Espindola wrote: > Author: rafael > Date: Sun Jun 26 17:44:34 2011 > New Revision: 133900 > > URL: http://llvm.org/viewvc/llvm-project?rev=133900&view=rev > Log: > Remove unused methods. Actually, you can remove the entire RegallocQuery interface, it is unused. The RegisterCoalescer class can be made private to RegisterCoalescer.cpp. Only the CoalescerPair class is used elsewhere. /jakob > > Modified: > llvm/trunk/lib/CodeGen/RegisterCoalescer.h > > Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.h > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.h?rev=133900&r1=133899&r2=133900&view=diff > ============================================================================== > --- llvm/trunk/lib/CodeGen/RegisterCoalescer.h (original) > +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.h Sun Jun 26 17:44:34 2011 > @@ -142,18 +142,6 @@ > initializeRegisterCoalescerPass(*PassRegistry::getPassRegistry()); > } > > - /// Run the coalescer on this function, providing interference > - /// data to query. Return whether we removed any copies. > - virtual bool coalesceFunction(MachineFunction &mf, > - RegallocQuery &ifd) { > - // This runs as an independent pass, so don't do anything. > - return false; > - } > - > - /// Reset state. Can be used to allow a coalescer run by > - /// PassManager to be run again by the register allocator. > - virtual void reset(MachineFunction &mf) {} > - > /// Register allocators must call this from their own > /// getAnalysisUsage to cover the case where the coalescer is not > /// a Pass in the proper sense and isn't managed by PassManager. > @@ -220,7 +208,6 @@ > /// // We don't reset the coalescer so if it's already been run this > /// // takes almost no time. > /// LinearScanRegallocQuery ifd(*li_); > - /// coalescer.coalesceFunction(fn, ifd); > /// > class RegallocQuery { > public: > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From stoklund at 2pi.dk Wed Jun 29 18:11:39 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 29 Jun 2011 23:11:39 -0000 Subject: [llvm-commits] [llvm] r134113 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Message-ID: <20110629231139.537C92A6C12C@llvm.org> Author: stoklund Date: Wed Jun 29 18:11:39 2011 New Revision: 134113 URL: http://llvm.org/viewvc/llvm-project?rev=134113&view=rev Log: Always adjust the stack pointer immediately after the call. Some x86-32 calls pop values off the stack, and we need to readjust the stack pointer after the call. This happens when ADJCALLSTACKUP is eliminated. It could happen that spill code was inserted between the CALL and ADJCALLSTACKUP instructions, and we would compute wrong stack pointer offsets for those frame index references. Fix this by inserting the stack pointer adjustment immediately after the call instead of where the ADJCALLSTACKUP instruction was erased. I don't have a test case since we don't currently insert code in that position. We will soon, though. I am testing a regalloc patch that didn't work on Linux because of this. Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=134113&r1=134112&r2=134113&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Wed Jun 29 18:11:39 2011 @@ -662,6 +662,13 @@ // The EFLAGS implicit def is dead. New->getOperand(3).setIsDead(); + + // We are not tracking the stack pointer adjustment by the callee, so make + // sure we restore the stack pointer immediately after the call, there may + // be spill code inserted between the CALL and ADJCALLSTACKUP instructions. + MachineBasicBlock::iterator B = MBB.begin(); + while (I != B && !llvm::prior(I)->getDesc().isCall()) + --I; MBB.insert(I, New); } } From grosbach at apple.com Wed Jun 29 18:25:04 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 29 Jun 2011 23:25:04 -0000 Subject: [llvm-commits] [llvm] r134114 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMLoadStoreOptimizer.cpp lib/Target/ARM/Thumb2InstrInfo.cpp lib/Target/ARM/Thumb2SizeReduction.cpp utils/TableGen/ARMDecoderEmitter.cpp Message-ID: <20110629232504.76FFD2A6C12C@llvm.org> Author: grosbach Date: Wed Jun 29 18:25:04 2011 New Revision: 134114 URL: http://llvm.org/viewvc/llvm-project?rev=134114&view=rev Log: Remove redundant Thumb2 ADD/SUB SP instruction definitions. Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134114&r1=134113&r2=134114&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Jun 29 18:25:04 2011 @@ -1018,11 +1018,10 @@ Offset = -MI->getOperand(2).getImm(); break; case ARM::SUBri: - case ARM::t2SUBrSPi: - Offset = MI->getOperand(2).getImm(); + Offset = MI->getOperand(2).getImm(); break; case ARM::tSUBspi: - Offset = MI->getOperand(2).getImm()*4; + Offset = MI->getOperand(2).getImm()*4; break; case ARM::tADDspi: case ARM::tADDrSPi: @@ -1097,13 +1096,6 @@ OutStreamer.EmitInstruction(TmpInst); return; } - case ARM::t2ADDrSPi: - case ARM::t2ADDrSPi12: - case ARM::t2SUBrSPi: - case ARM::t2SUBrSPi12: - assert ((MI->getOperand(1).getReg() == ARM::SP) && - "Unexpected source register!"); - break; case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass"); case ARM::DBG_VALUE: { Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=134114&r1=134113&r2=134114&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Jun 29 18:25:04 2011 @@ -1284,9 +1284,5 @@ } // Update the original instruction to use the scratch register. MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); - if (MI.getOpcode() == ARM::t2ADDrSPi) - MI.setDesc(TII.get(ARM::t2ADDri)); - else if (MI.getOpcode() == ARM::t2SUBrSPi) - MI.setDesc(TII.get(ARM::t2SUBri)); } } Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=134114&r1=134113&r2=134114&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jun 29 18:25:04 2011 @@ -1169,63 +1169,6 @@ []>; -// FIXME: None of these add/sub SP special instructions should be necessary -// at all for thumb2 since they use the same encodings as the generic -// add/sub instructions. In thumb1 we need them since they have dedicated -// encodings. At the least, they should be pseudo instructions. -// ADD r, sp, {so_imm|i12} -let isCodeGenOnly = 1 in { -def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), - IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> { - let Inst{31-27} = 0b11110; - let Inst{25} = 0; - let Inst{24-21} = 0b1000; - let Inst{15} = 0; -} -def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), - IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> { - let Inst{31-27} = 0b11110; - let Inst{25-20} = 0b100000; - let Inst{15} = 0; -} - -// ADD r, sp, so_reg -def t2ADDrSPs : T2sTwoRegShiftedReg< - (outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), - IIC_iALUsi, "add", ".w\t$Rd, $Rn, $ShiftedRm", []> { - let Inst{31-27} = 0b11101; - let Inst{26-25} = 0b01; - let Inst{24-21} = 0b1000; - let Inst{15} = 0; -} - -// SUB r, sp, {so_imm|i12} -def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), - IIC_iALUi, "sub", ".w\t$Rd, $Rn, $imm", []> { - let Inst{31-27} = 0b11110; - let Inst{25} = 0; - let Inst{24-21} = 0b1101; - let Inst{15} = 0; -} -def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), - IIC_iALUi, "subw", "\t$Rd, $Rn, $imm", []> { - let Inst{31-27} = 0b11110; - let Inst{25-20} = 0b101010; - let Inst{15} = 0; -} - -// SUB r, sp, so_reg -def t2SUBrSPs : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm), - IIC_iALUsi, - "sub", "\t$Rd, $Rn, $imm", []> { - let Inst{31-27} = 0b11101; - let Inst{26-25} = 0b01; - let Inst{24-21} = 0b1101; - let Inst{19-16} = 0b1101; // Rn = sp - let Inst{15} = 0; -} -} // end isCodeGenOnly = 1 - //===----------------------------------------------------------------------===// // Load / store Instructions. // Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=134114&r1=134113&r2=134114&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Jun 29 18:25:04 2011 @@ -329,13 +329,9 @@ if (NewBase == 0) return false; } - int BaseOpc = !isThumb2 - ? ARM::ADDri - : ((Base == ARM::SP) ? ARM::t2ADDrSPi : ARM::t2ADDri); + int BaseOpc = !isThumb2 ? ARM::ADDri : ARM::t2ADDri; if (Offset < 0) { - BaseOpc = !isThumb2 - ? ARM::SUBri - : ((Base == ARM::SP) ? ARM::t2SUBrSPi : ARM::t2SUBri); + BaseOpc = !isThumb2 ? ARM::SUBri : ARM::t2SUBri; Offset = - Offset; } int ImmedOffset = isThumb2 @@ -516,8 +512,6 @@ if (!MI) return false; if (MI->getOpcode() != ARM::t2SUBri && - MI->getOpcode() != ARM::t2SUBrSPi && - MI->getOpcode() != ARM::t2SUBrSPi12 && MI->getOpcode() != ARM::tSUBspi && MI->getOpcode() != ARM::SUBri) return false; @@ -541,8 +535,6 @@ if (!MI) return false; if (MI->getOpcode() != ARM::t2ADDri && - MI->getOpcode() != ARM::t2ADDrSPi && - MI->getOpcode() != ARM::t2ADDrSPi12 && MI->getOpcode() != ARM::tADDspi && MI->getOpcode() != ARM::ADDri) return false; Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=134114&r1=134113&r2=134114&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Wed Jun 29 18:25:04 2011 @@ -251,7 +251,7 @@ } // sub rd, sp, so_imm - Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi; + Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { NumBytes = 0; } else { @@ -425,9 +425,9 @@ if (Offset < 0) { Offset = -Offset; isSub = true; - MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri)); + MI.setDesc(TII.get(ARM::t2SUBri)); } else { - MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri)); + MI.setDesc(TII.get(ARM::t2ADDri)); } // Common case: small offset, fits into instruction. @@ -443,9 +443,7 @@ // Another common case: imm12. if (Offset < 4096 && (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) { - unsigned NewOpc = isSP - ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12) - : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12); + unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; MI.setDesc(TII.get(NewOpc)); MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134114&r1=134113&r2=134114&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Wed Jun 29 18:25:04 2011 @@ -57,10 +57,8 @@ static const ReduceEntry ReduceTable[] = { // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, PF, S { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0 }, - { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,0 }, + { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1 }, { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0 }, - // Note: immediate scale is 4. - { ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 0,1 }, { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1 }, { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1 }, { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0 }, @@ -291,7 +289,7 @@ Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD || Opc == ARM::t2LDMDB_UPD); bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD); - bool isSPOk = isPCOk || isLROk || (Opc == ARM::t2ADDrSPi); + bool isSPOk = isPCOk || isLROk; for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { const MachineOperand &MO = MI->getOperand(i); if (!MO.isReg() || MO.isImplicit()) @@ -481,6 +479,44 @@ Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, const ReduceEntry &Entry, bool LiveCPSR, MachineInstr *CPSRDef) { + unsigned Opc = MI->getOpcode(); + if (Opc == ARM::t2ADDri) { + // If the source register is SP, try to reduce to tADDrSPi, otherwise + // it's a normal reduce. + if (MI->getOperand(1).getReg() != ARM::SP) { + if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef)) + return true; + return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); + } + // Try to reduce to tADDrSPi. + unsigned Imm = MI->getOperand(2).getImm(); + // The immediate must be in range, the destination register must be a low + // reg, and the condition flags must not be being set. + if (Imm & 3 || Imm > 1024) + return false; + if (!isARMLowRegister(MI->getOperand(0).getReg())) + return false; + const MCInstrDesc &MCID = MI->getDesc(); + if (MCID.hasOptionalDef() && + MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) + return false; + + MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), + TII->get(ARM::tADDrSPi)) + .addOperand(MI->getOperand(0)) + .addOperand(MI->getOperand(1)) + .addImm(Imm / 4); // The tADDrSPi has an implied scale by four. + + // Transfer MI flags. + MIB.setMIFlags(MI->getFlags()); + + DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB); + + MBB.erase(MI); + ++NumNarrows; + return true; + } + if (Entry.LowRegs1 && !VerifyLowRegs(MI)) return false; @@ -488,7 +524,6 @@ if (MCID.mayLoad() || MCID.mayStore()) return ReduceLoadStore(MBB, MI, Entry); - unsigned Opc = MI->getOpcode(); switch (Opc) { default: break; case ARM::t2ADDSri: @@ -531,13 +566,6 @@ return true; return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); } - case ARM::t2ADDrSPi: { - static const ReduceEntry NarrowEntry = - { ARM::t2ADDrSPi,ARM::tADDspi, 0, 7, 0, 1, 0, 1, 0, 0,1 }; - if (MI->getOperand(0).getReg() == ARM::SP) - return ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef); - return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); - } } return false; } @@ -645,9 +673,8 @@ return false; unsigned Limit = ~0U; - unsigned Scale = (Entry.WideOpc == ARM::t2ADDrSPi) ? 4 : 1; if (Entry.Imm1Limit) - Limit = ((1 << Entry.Imm1Limit) - 1) * Scale; + Limit = (1 << Entry.Imm1Limit) - 1; const MCInstrDesc &MCID = MI->getDesc(); for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { @@ -658,13 +685,11 @@ unsigned Reg = MO.getReg(); if (!Reg || Reg == ARM::CPSR) continue; - if (Entry.WideOpc == ARM::t2ADDrSPi && Reg == ARM::SP) - continue; if (Entry.LowRegs1 && !isARMLowRegister(Reg)) return false; } else if (MO.isImm() && !MCID.OpInfo[i].isPredicate()) { - if (((unsigned)MO.getImm()) > Limit || (MO.getImm() & (Scale-1)) != 0) + if (((unsigned)MO.getImm()) > Limit) return false; } } @@ -723,15 +748,11 @@ if (SkipPred && isPred) continue; const MachineOperand &MO = MI->getOperand(i); - if (Scale > 1 && !isPred && MO.isImm()) - MIB.addImm(MO.getImm() / Scale); - else { - if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) - // Skip implicit def of CPSR. Either it's modeled as an optional - // def now or it's already an implicit def on the new instruction. - continue; - MIB.addOperand(MO); - } + if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) + // Skip implicit def of CPSR. Either it's modeled as an optional + // def now or it's already an implicit def on the new instruction. + continue; + MIB.addOperand(MO); } if (!MCID.isPredicable() && NewMCID.isPredicable()) AddDefaultPred(MIB); Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=134114&r1=134113&r2=134114&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Wed Jun 29 18:25:04 2011 @@ -1640,12 +1640,8 @@ // Ignore tADDrSP, tADDspr, and tPICADD, prefer the generic tADDhirr. // Ignore t2SUBrSPs, prefer the t2SUB[S]r[r|s]. // Ignore t2ADDrSPs, prefer the t2ADD[S]r[r|s]. - // Ignore t2ADDrSPi/t2SUBrSPi, which have more generic couterparts. - // Ignore t2ADDrSPi12/t2SUBrSPi12, which have more generic couterparts if (Name == "tADDrSP" || Name == "tADDspr" || Name == "tPICADD" || - Name == "t2SUBrSPs" || Name == "t2ADDrSPs" || - Name == "t2ADDrSPi" || Name == "t2SUBrSPi" || - Name == "t2ADDrSPi12" || Name == "t2SUBrSPi12") + Name == "t2SUBrSPs" || Name == "t2ADDrSPs") return false; // FIXME: Use ldr.n to work around a Darwin assembler bug. From stoklund at 2pi.dk Wed Jun 29 18:22:40 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 29 Jun 2011 16:22:40 -0700 Subject: [llvm-commits] [llvm] r134089 - /llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp In-Reply-To: <20110629194127.97F092A6C12C@llvm.org> References: <20110629194127.97F092A6C12C@llvm.org> Message-ID: On Jun 29, 2011, at 12:41 PM, Eric Christopher wrote: > Author: echristo > Date: Wed Jun 29 14:41:27 2011 > New Revision: 134089 > > URL: http://llvm.org/viewvc/llvm-project?rev=134089&view=rev > Log: > Add a TODO for the Alpha port inline asm constraints. > > Modified: > llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp > > Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=134089&r1=134088&r2=134089&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) > +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jun 29 14:41:27 2011 > @@ -835,6 +835,8 @@ > case 'r': > return std::make_pair(0U, Alpha::GPRCRegisterClass); > case 'f': > + // TODO: Do we need to add the 64-bit register class here when > + // it contains the same registers? > return std::make_pair(0U, Alpha::F4RCRegisterClass); > } > } Probably, since the register class also determines the spill size. However, the coalescer is very likely to fix this for you. A copy between F4RC and F8RC will be widened to F8RC. /jakob From echristo at apple.com Wed Jun 29 18:23:26 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 16:23:26 -0700 Subject: [llvm-commits] [llvm] r134089 - /llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp In-Reply-To: References: <20110629194127.97F092A6C12C@llvm.org> Message-ID: On Jun 29, 2011, at 4:22 PM, Jakob Stoklund Olesen wrote: > > On Jun 29, 2011, at 12:41 PM, Eric Christopher wrote: > >> Author: echristo >> Date: Wed Jun 29 14:41:27 2011 >> New Revision: 134089 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134089&view=rev >> Log: >> Add a TODO for the Alpha port inline asm constraints. >> >> Modified: >> llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp >> >> Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=134089&r1=134088&r2=134089&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) >> +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jun 29 14:41:27 2011 >> @@ -835,6 +835,8 @@ >> case 'r': >> return std::make_pair(0U, Alpha::GPRCRegisterClass); >> case 'f': >> + // TODO: Do we need to add the 64-bit register class here when >> + // it contains the same registers? >> return std::make_pair(0U, Alpha::F4RCRegisterClass); >> } >> } > > Probably, since the register class also determines the spill size. > Aha. OK. > However, the coalescer is very likely to fix this for you. A copy between F4RC and F8RC will be widened to F8RC. Heh. I'll just put the simple check in. Thanks! -eric From atrick at apple.com Wed Jun 29 18:46:48 2011 From: atrick at apple.com (Andrew Trick) Date: Wed, 29 Jun 2011 16:46:48 -0700 Subject: [llvm-commits] [patch] Fix deprecation warning in lit on OS X In-Reply-To: <5147384C-15F5-428E-8079-B5C3D6BDF46D@belkadan.com> References: <5147384C-15F5-428E-8079-B5C3D6BDF46D@belkadan.com> Message-ID: <04FF9D64-CD87-49CB-A7CC-555715FEE038@apple.com> On Jun 29, 2011, at 11:57 AM, Jordy Rose wrote: > I usually hang out on the Clang side of things, but I've noticed that the lit tests have a deprecation warning about 'popen2' that comes up on OS X. The attached patch replaces the use of 'popen2' with 'subprocess.Popen'. > > Jordy Looks good. FWIW, the more common idiom seems to be "out,_ = p.communicate()" -Andy From isanbard at gmail.com Wed Jun 29 18:49:13 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 29 Jun 2011 23:49:13 -0000 Subject: [llvm-commits] [llvm] r134115 - /llvm/trunk/lib/MC/MCDwarf.cpp Message-ID: <20110629234913.1BC1C2A6C12C@llvm.org> Author: void Date: Wed Jun 29 18:49:12 2011 New Revision: 134115 URL: http://llvm.org/viewvc/llvm-project?rev=134115&view=rev Log: We don't want to use relocations inside the compact unwind section. Just use the symbols instead. Modified: llvm/trunk/lib/MC/MCDwarf.cpp Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=134115&r1=134114&r2=134115&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Wed Jun 29 18:49:12 2011 @@ -637,9 +637,6 @@ const TargetAsmInfo &TAI = Context.getTargetAsmInfo(); Streamer.SwitchSection(TAI.getCompactUnwindSection()); - unsigned FDEEncoding = TAI.getFDEEncoding(UsingCFI); - unsigned Size = getSizeForEncoding(Streamer, FDEEncoding); - // range-start range-length compact-unwind-enc personality-func lsda // _foo LfooEnd-_foo 0x00000023 0 0 // _bar LbarEnd-_bar 0x00000025 __gxx_personality except_tab1 @@ -663,13 +660,31 @@ // .quad except_tab1 // Range Start - EmitSymbol(Streamer, *Frame.Begin, FDEEncoding); + unsigned FDEEncoding = TAI.getFDEEncoding(UsingCFI); + unsigned Size = getSizeForEncoding(Streamer, FDEEncoding); + Streamer.EmitSymbolValue(Frame.Function, Size); // Range Length const MCExpr *Range = MakeStartMinusEndExpr(Streamer, *Frame.Begin, *Frame.End, 0); Streamer.EmitAbsValue(Range, Size); + // Personality Function + if (Frame.Personality) { + Size = getSizeForEncoding(Streamer, Frame.PersonalityEncoding); + Streamer.EmitSymbolValue(Frame.Personality, Size); + } else { + Streamer.EmitIntValue(Frame.PersonalityEncoding, 0); // No personality fn + } + + // LSDA + if (Frame.Lsda) { + Size = getSizeForEncoding(Streamer, Frame.LsdaEncoding); + Streamer.EmitSymbolValue(Frame.Lsda, Size); + } else { + Streamer.EmitIntValue(Frame.LsdaEncoding, 0); // No LSDA + } + return true; #endif } From dpatel at apple.com Wed Jun 29 18:50:13 2011 From: dpatel at apple.com (Devang Patel) Date: Wed, 29 Jun 2011 23:50:13 -0000 Subject: [llvm-commits] [llvm] r134116 - in /llvm/trunk: include/llvm/CodeGen/FastISel.h lib/CodeGen/SelectionDAG/FastISel.cpp lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp test/CodeGen/X86/dbg-materialized-reg-loc.ll Message-ID: <20110629235013.391472A6C12C@llvm.org> Author: dpatel Date: Wed Jun 29 18:50:13 2011 New Revision: 134116 URL: http://llvm.org/viewvc/llvm-project?rev=134116&view=rev Log: Revert r133953 for now. Removed: llvm/trunk/test/CodeGen/X86/dbg-materialized-reg-loc.ll Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Modified: llvm/trunk/include/llvm/CodeGen/FastISel.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/FastISel.h?rev=134116&r1=134115&r2=134116&view=diff ============================================================================== --- llvm/trunk/include/llvm/CodeGen/FastISel.h (original) +++ llvm/trunk/include/llvm/CodeGen/FastISel.h Wed Jun 29 18:50:13 2011 @@ -118,10 +118,6 @@ DebugLoc DL; }; - /// recomputeDebugLocForMaterializedRegs - Recompute debug location for - /// very first instruction in a basic block. - void recomputeDebugLocForMaterializedRegs(); - /// enterLocalValueArea - Prepare InsertPt to begin inserting instructions /// into the local value area and return the old insert position. SavePoint enterLocalValueArea(); Modified: llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp?rev=134116&r1=134115&r2=134116&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/FastISel.cpp Wed Jun 29 18:50:13 2011 @@ -292,28 +292,6 @@ ++FuncInfo.InsertPt; } -/// recomputeDebugLocForMaterializedRegs - Recompute debug location for -/// very first instruction in a basic block. All instructions emitted -/// to materialize registers do not have location information, see -/// enterLocalValueArea(), becase they may not be emited at the right -/// location. -void FastISel::recomputeDebugLocForMaterializedRegs() { - if (!getLastLocalValue()) - return; - MachineInstr *First = FuncInfo.MBB->getFirstNonPHI(); - if (!First->getDebugLoc().isUnknown()) - return; - - for (MachineBasicBlock::iterator I = FuncInfo.MBB->begin(), - E = FuncInfo.MBB->end(); I != E; ++I) { - DebugLoc DL = I->getDebugLoc(); - if (!DL.isUnknown()) { - First->setDebugLoc(DL); - return; - } - } -} - FastISel::SavePoint FastISel::enterLocalValueArea() { MachineBasicBlock::iterator OldInsertPt = FuncInfo.InsertPt; DebugLoc OldDL = DL; Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp?rev=134116&r1=134115&r2=134116&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp Wed Jun 29 18:50:13 2011 @@ -964,8 +964,6 @@ else ++NumFastIselBlocks; - if (FastIS) - FastIS->recomputeDebugLocForMaterializedRegs(); if (Begin != BI) { // Run SelectionDAG instruction selection on the remainder of the block // not handled by FastISel. If FastISel is not run, this is the entire Removed: llvm/trunk/test/CodeGen/X86/dbg-materialized-reg-loc.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/dbg-materialized-reg-loc.ll?rev=134115&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/dbg-materialized-reg-loc.ll (original) +++ llvm/trunk/test/CodeGen/X86/dbg-materialized-reg-loc.ll (removed) @@ -1,120 +0,0 @@ -; RUN: llc -O0 < %s | FileCheck %s -; Radar 9223880 -; CHECK: .loc 1 17 64 -; CHECK: movl $0, %esi - -target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64" -target triple = "x86_64-apple-macosx10.7.0" - -%class.LanguageRuntime = type opaque -%class.Process = type { i8 } - -define zeroext i1 @_Z15SetDynamicValuev() uwtable ssp { -entry: - %retval = alloca i1, align 1 - %process = alloca %class.Process*, align 8 - %cpp_runtime = alloca %class.LanguageRuntime*, align 8 - %objc_runtime = alloca %class.LanguageRuntime*, align 8 - %call = call zeroext i1 @_Z24IsPointerOrReferenceTypev(), !dbg !15 - br i1 %call, label %if.end, label %if.then, !dbg !15 - -if.then: ; preds = %entry - store i1 false, i1* %retval, !dbg !17 - br label %return, !dbg !17 - -if.end: ; preds = %entry - call void @llvm.dbg.declare(metadata !{%class.Process** %process}, metadata !18), !dbg !20 - %call1 = call %class.Process* @_Z10GetProcessv(), !dbg !21 - store %class.Process* %call1, %class.Process** %process, align 8, !dbg !21 - %tmp = load %class.Process** %process, align 8, !dbg !22 - %tobool = icmp ne %class.Process* %tmp, null, !dbg !22 - br i1 %tobool, label %if.end3, label %if.then2, !dbg !22 - -if.then2: ; preds = %if.end - store i1 false, i1* %retval, !dbg !23 - br label %return, !dbg !23 - -if.end3: ; preds = %if.end - call void @llvm.dbg.declare(metadata !{%class.LanguageRuntime** %cpp_runtime}, metadata !24), !dbg !25 - %tmp5 = load %class.Process** %process, align 8, !dbg !26 - %call6 = call %class.LanguageRuntime* @_ZN7Process18GetLanguageRuntimeEi(%class.Process* %tmp5, i32 0), !dbg !26 - store %class.LanguageRuntime* %call6, %class.LanguageRuntime** %cpp_runtime, align 8, !dbg !26 - %tmp7 = load %class.LanguageRuntime** %cpp_runtime, align 8, !dbg !27 - %tobool8 = icmp ne %class.LanguageRuntime* %tmp7, null, !dbg !27 - br i1 %tobool8, label %if.then9, label %if.end10, !dbg !27 - -if.then9: ; preds = %if.end3 - store i1 true, i1* %retval, !dbg !28 - br label %return, !dbg !28 - -if.end10: ; preds = %if.end3 - call void @llvm.dbg.declare(metadata !{%class.LanguageRuntime** %objc_runtime}, metadata !30), !dbg !31 - %tmp12 = load %class.Process** %process, align 8, !dbg !32 - %call13 = call %class.LanguageRuntime* @_ZN7Process18GetLanguageRuntimeEi(%class.Process* %tmp12, i32 1), !dbg !32 - store %class.LanguageRuntime* %call13, %class.LanguageRuntime** %objc_runtime, align 8, !dbg !32 - %tmp14 = load %class.LanguageRuntime** %objc_runtime, align 8, !dbg !33 - %tobool15 = icmp ne %class.LanguageRuntime* %tmp14, null, !dbg !33 - br i1 %tobool15, label %if.then16, label %if.end17, !dbg !33 - -if.then16: ; preds = %if.end10 - store i1 true, i1* %retval, !dbg !34 - br label %return, !dbg !34 - -if.end17: ; preds = %if.end10 - store i1 false, i1* %retval, !dbg !36 - br label %return, !dbg !36 - -return: ; preds = %if.end17, %if.then16, %if.then9, %if.then2, %if.then - %0 = load i1* %retval, !dbg !37 - ret i1 %0, !dbg !37 -} - -declare zeroext i1 @_Z24IsPointerOrReferenceTypev() - -declare void @llvm.dbg.declare(metadata, metadata) nounwind readnone - -declare %class.Process* @_Z10GetProcessv() - -declare %class.LanguageRuntime* @_ZN7Process18GetLanguageRuntimeEi(%class.Process*, i32) - -!llvm.dbg.cu = !{!0} -!llvm.dbg.sp = !{!1, !6} - -!0 = metadata !{i32 589841, i32 0, i32 4, metadata !"my_vo.cpp", metadata !"/private/tmp", metadata !"clang version 3.0 (trunk 133629)", i1 true, i1 false, metadata !"", i32 0} ; [ DW_TAG_compile_unit ] -!1 = metadata !{i32 589870, i32 0, metadata !2, metadata !"SetDynamicValue", metadata !"SetDynamicValue", metadata !"_Z15SetDynamicValuev", metadata !2, i32 9, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 false, i1 ()* @_Z15SetDynamicValuev, null, null} ; [ DW_TAG_subprogram ] -!2 = metadata !{i32 589865, metadata !"my_vo.cpp", metadata !"/private/tmp", metadata !0} ; [ DW_TAG_file_type ] -!3 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] -!4 = metadata !{metadata !5} -!5 = metadata !{i32 589860, metadata !0, metadata !"bool", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 2} ; [ DW_TAG_base_type ] -!6 = metadata !{i32 589870, i32 0, metadata !7, metadata !"GetLanguageRuntime", metadata !"GetLanguageRuntime", metadata !"_ZN7Process18GetLanguageRuntimeEi", metadata !2, i32 4, metadata !9, i1 false, i1 false, i32 0, i32 0, null, i32 256, i1 false, null, null} ; [ DW_TAG_subprogram ] -!7 = metadata !{i32 589826, metadata !0, metadata !"Process", metadata !2, i32 2, i64 8, i64 8, i32 0, i32 0, null, metadata !8, i32 0, null, null} ; [ DW_TAG_class_type ] -!8 = metadata !{metadata !6} -!9 = metadata !{i32 589845, metadata !2, metadata !"", metadata !2, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !10, i32 0, i32 0} ; [ DW_TAG_subroutine_type ] -!10 = metadata !{metadata !11, metadata !13, metadata !14} -!11 = metadata !{i32 589839, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ] -!12 = metadata !{i32 589843, metadata !0, metadata !"LanguageRuntime", metadata !2, i32 1, i64 0, i64 0, i32 0, i32 4, i32 0, null, i32 0, i32 0} ; [ DW_TAG_structure_type ] -!13 = metadata !{i32 589839, metadata !0, metadata !"", i32 0, i32 0, i64 64, i64 64, i64 0, i32 64, metadata !7} ; [ DW_TAG_pointer_type ] -!14 = metadata !{i32 589860, metadata !0, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ] -!15 = metadata !{i32 10, i32 3, metadata !16, null} -!16 = metadata !{i32 589835, metadata !1, i32 9, i32 24, metadata !2, i32 0} ; [ DW_TAG_lexical_block ] -!17 = metadata !{i32 11, i32 5, metadata !16, null} -!18 = metadata !{i32 590080, metadata !16, metadata !"process", metadata !2, i32 13, metadata !19, i32 0} ; [ DW_TAG_auto_variable ] -!19 = metadata !{i32 589839, metadata !0, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !7} ; [ DW_TAG_pointer_type ] -!20 = metadata !{i32 13, i32 12, metadata !16, null} -!21 = metadata !{i32 13, i32 34, metadata !16, null} -!22 = metadata !{i32 14, i32 3, metadata !16, null} -!23 = metadata !{i32 15, i32 5, metadata !16, null} -!24 = metadata !{i32 590080, metadata !16, metadata !"cpp_runtime", metadata !2, i32 17, metadata !11, i32 0} ; [ DW_TAG_auto_variable ] -!25 = metadata !{i32 17, i32 20, metadata !16, null} -!26 = metadata !{i32 17, i32 64, metadata !16, null} -!27 = metadata !{i32 18, i32 3, metadata !16, null} -!28 = metadata !{i32 19, i32 5, metadata !29, null} -!29 = metadata !{i32 589835, metadata !16, i32 18, i32 20, metadata !2, i32 1} ; [ DW_TAG_lexical_block ] -!30 = metadata !{i32 590080, metadata !16, metadata !"objc_runtime", metadata !2, i32 22, metadata !11, i32 0} ; [ DW_TAG_auto_variable ] -!31 = metadata !{i32 22, i32 20, metadata !16, null} -!32 = metadata !{i32 22, i32 65, metadata !16, null} -!33 = metadata !{i32 23, i32 3, metadata !16, null} -!34 = metadata !{i32 24, i32 5, metadata !35, null} -!35 = metadata !{i32 589835, metadata !16, i32 23, i32 21, metadata !2, i32 2} ; [ DW_TAG_lexical_block ] -!36 = metadata !{i32 26, i32 3, metadata !16, null} -!37 = metadata !{i32 27, i32 1, metadata !16, null} From isanbard at gmail.com Wed Jun 29 18:53:16 2011 From: isanbard at gmail.com (Bill Wendling) Date: Wed, 29 Jun 2011 23:53:16 -0000 Subject: [llvm-commits] [llvm] r134117 - /llvm/trunk/lib/MC/MCDwarf.cpp Message-ID: <20110629235316.E07FA2A6C12C@llvm.org> Author: void Date: Wed Jun 29 18:53:16 2011 New Revision: 134117 URL: http://llvm.org/viewvc/llvm-project?rev=134117&view=rev Log: Stupid error: If the LSDA and Personality functions aren't there, emit 0 instead of the encoding. Modified: llvm/trunk/lib/MC/MCDwarf.cpp Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=134117&r1=134116&r2=134117&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Wed Jun 29 18:53:16 2011 @@ -670,20 +670,18 @@ Streamer.EmitAbsValue(Range, Size); // Personality Function - if (Frame.Personality) { - Size = getSizeForEncoding(Streamer, Frame.PersonalityEncoding); + Size = getSizeForEncoding(Streamer, Frame.PersonalityEncoding); + if (Frame.Personality) Streamer.EmitSymbolValue(Frame.Personality, Size); - } else { - Streamer.EmitIntValue(Frame.PersonalityEncoding, 0); // No personality fn - } + else + Streamer.EmitIntValue(0, Size); // No personality fn // LSDA - if (Frame.Lsda) { - Size = getSizeForEncoding(Streamer, Frame.LsdaEncoding); + Size = getSizeForEncoding(Streamer, Frame.LsdaEncoding); + if (Frame.Lsda) Streamer.EmitSymbolValue(Frame.Lsda, Size); - } else { - Streamer.EmitIntValue(Frame.LsdaEncoding, 0); // No LSDA - } + else + Streamer.EmitIntValue(0, Size); // No LSDA return true; #endif From isanbard at gmail.com Wed Jun 29 19:30:52 2011 From: isanbard at gmail.com (Bill Wendling) Date: Thu, 30 Jun 2011 00:30:52 -0000 Subject: [llvm-commits] [llvm] r134119 - /llvm/trunk/lib/MC/MCDwarf.cpp Message-ID: <20110630003052.B2BC82A6C12C@llvm.org> Author: void Date: Wed Jun 29 19:30:52 2011 New Revision: 134119 URL: http://llvm.org/viewvc/llvm-project?rev=134119&view=rev Log: * Use the proper size to output the range size. * Rough in the compact encoding part. Modified: llvm/trunk/lib/MC/MCDwarf.cpp Modified: llvm/trunk/lib/MC/MCDwarf.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=134119&r1=134118&r2=134119&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDwarf.cpp (original) +++ llvm/trunk/lib/MC/MCDwarf.cpp Wed Jun 29 19:30:52 2011 @@ -667,7 +667,14 @@ // Range Length const MCExpr *Range = MakeStartMinusEndExpr(Streamer, *Frame.Begin, *Frame.End, 0); - Streamer.EmitAbsValue(Range, Size); + Streamer.EmitAbsValue(Range, 4); + + // FIXME: + // Compact Encoding + uint32_t Encoding = 0; + Size = getSizeForEncoding(Streamer, dwarf::DW_EH_PE_udata4); + Streamer.EmitIntValue(Encoding, Size); + // Personality Function Size = getSizeForEncoding(Streamer, Frame.PersonalityEncoding); From echristo at apple.com Wed Jun 29 19:48:30 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 30 Jun 2011 00:48:30 -0000 Subject: [llvm-commits] [llvm] r134121 - in /llvm/trunk: lib/Target/X86/X86ISelDAGToDAG.cpp test/CodeGen/X86/atomic-or.ll Message-ID: <20110630004830.5F7982A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 19:48:30 2011 New Revision: 134121 URL: http://llvm.org/viewvc/llvm-project?rev=134121&view=rev Log: Fix a small thinko for constant i64 lock/orq optimization where we we didn't have an opcode for 64-bit constant or expressions. Fixes rdar://9692967 Added: llvm/trunk/test/CodeGen/X86/atomic-or.ll Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Modified: llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp?rev=134121&r1=134120&r2=134121&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp (original) +++ llvm/trunk/lib/Target/X86/X86ISelDAGToDAG.cpp Wed Jun 29 19:48:30 2011 @@ -1612,16 +1612,18 @@ Opc = AtomicOpcTbl[Op][I32]; break; case MVT::i64: + Opc = AtomicOpcTbl[Op][I64]; if (isCN) { if (immSext8(Val.getNode())) Opc = AtomicOpcTbl[Op][SextConstantI64]; else if (i64immSExt32(Val.getNode())) Opc = AtomicOpcTbl[Op][ConstantI64]; - } else - Opc = AtomicOpcTbl[Op][I64]; + } break; } + assert(Opc != 0 && "Invalid arith lock transform!"); + DebugLoc dl = Node->getDebugLoc(); SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, NVT), 0); Added: llvm/trunk/test/CodeGen/X86/atomic-or.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/atomic-or.ll?rev=134121&view=auto ============================================================================== --- llvm/trunk/test/CodeGen/X86/atomic-or.ll (added) +++ llvm/trunk/test/CodeGen/X86/atomic-or.ll Wed Jun 29 19:48:30 2011 @@ -0,0 +1,18 @@ +; RUN: llc < %s -march=x86-64 | FileCheck %s + +; rdar://9692967 + +define void @do_the_sync(i64* %p, i32 %b) nounwind { +entry: + %p.addr = alloca i64*, align 8 + store i64* %p, i64** %p.addr, align 8 + %tmp = load i64** %p.addr, align 8 + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) +; CHECK: lock +; CHECK-NEXT: orq $2147483648 + %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648) + call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true) + ret void +} +declare i64 @llvm.atomic.load.or.i64.p0i64(i64* nocapture, i64) nounwind +declare void @llvm.memory.barrier(i1, i1, i1, i1, i1) nounwind From echristo at apple.com Wed Jun 29 20:05:47 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 30 Jun 2011 01:05:47 -0000 Subject: [llvm-commits] [llvm] r134122 - /llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Message-ID: <20110630010547.206432A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 20:05:46 2011 New Revision: 134122 URL: http://llvm.org/viewvc/llvm-project?rev=134122&view=rev Log: Make sure we use the correct register class here since we'll need to care about spill values. Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Modified: llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp?rev=134122&r1=134121&r2=134122&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaISelLowering.cpp Wed Jun 29 20:05:46 2011 @@ -835,7 +835,8 @@ case 'r': return std::make_pair(0U, Alpha::GPRCRegisterClass); case 'f': - return std::make_pair(0U, Alpha::F4RCRegisterClass); + return VT == MVT::f64 ? std::make_pair(0U, Alpha::F8RCRegisterClass) : + std::make_pair(0U, Alpha::F4RCRegisterClass); } } return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); From echristo at apple.com Wed Jun 29 20:20:04 2011 From: echristo at apple.com (Eric Christopher) Date: Thu, 30 Jun 2011 01:20:04 -0000 Subject: [llvm-commits] [llvm] r134123 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp Message-ID: <20110630012004.1CBC32A6C12C@llvm.org> Author: echristo Date: Wed Jun 29 20:20:03 2011 New Revision: 134123 URL: http://llvm.org/viewvc/llvm-project?rev=134123&view=rev Log: Remove getRegClassForInlineAsmConstraint and all dependencies. Fixes rdar://9643582 Modified: llvm/trunk/include/llvm/Target/TargetLowering.h llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Modified: llvm/trunk/include/llvm/Target/TargetLowering.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=134123&r1=134122&r2=134123&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetLowering.h (original) +++ llvm/trunk/include/llvm/Target/TargetLowering.h Wed Jun 29 20:20:03 2011 @@ -1421,13 +1421,6 @@ /// is for this target. virtual ConstraintType getConstraintType(const std::string &Constraint) const; - /// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"), - /// return a list of registers that can be used to satisfy the constraint. - /// This should only be used for C_RegisterClass constraints. - virtual std::vector - getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const; - /// getRegForInlineAsmConstraint - Given a physical register constraint (e.g. /// {edx}), return the register number and the register class for the /// register. Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=134123&r1=134122&r2=134123&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Wed Jun 29 20:20:03 2011 @@ -5428,55 +5428,6 @@ } // end anonymous namespace -/// isAllocatableRegister - If the specified register is safe to allocate, -/// i.e. it isn't a stack pointer or some other special register, return the -/// register class for the register. Otherwise, return null. -static const TargetRegisterClass * -isAllocatableRegister(unsigned Reg, MachineFunction &MF, - const TargetLowering &TLI, - const TargetRegisterInfo *TRI) { - EVT FoundVT = MVT::Other; - const TargetRegisterClass *FoundRC = 0; - for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), - E = TRI->regclass_end(); RCI != E; ++RCI) { - EVT ThisVT = MVT::Other; - - const TargetRegisterClass *RC = *RCI; - if (!RC->isAllocatable()) - continue; - // If none of the value types for this register class are valid, we - // can't use it. For example, 64-bit reg classes on 32-bit targets. - for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); - I != E; ++I) { - if (TLI.isTypeLegal(*I)) { - // If we have already found this register in a different register class, - // choose the one with the largest VT specified. For example, on - // PowerPC, we favor f64 register classes over f32. - if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { - ThisVT = *I; - break; - } - } - } - - if (ThisVT == MVT::Other) continue; - - // NOTE: This isn't ideal. In particular, this might allocate the - // frame pointer in functions that need it (due to them not being taken - // out of allocation, because a variable sized allocation hasn't been seen - // yet). This is a slight code pessimization, but should still work. - ArrayRef RawOrder = RC->getRawAllocationOrder(MF); - if (std::find(RawOrder.begin(), RawOrder.end(), Reg) != RawOrder.end()) { - // We found a matching register class. Keep looking at others in case - // we find one with larger registers that this physreg is also in. - FoundRC = RC; - FoundVT = ThisVT; - break; - } - } - return FoundRC; -} - /// GetRegistersForValue - Assign registers (virtual or physical) for the /// specified operand. We prefer to assign virtual registers, to allow the /// register allocator to handle the assignment process. However, if the asm @@ -5611,58 +5562,6 @@ return; } - // This is a reference to a register class that doesn't directly correspond - // to an LLVM register class. Allocate NumRegs consecutive, available, - // registers from the class. - std::vector RegClassRegs - = TLI.getRegClassForInlineAsmConstraint(OpInfo.ConstraintCode, - OpInfo.ConstraintVT); - - const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); - BitVector Reserved = TRI->getReservedRegs(MF); - unsigned NumAllocated = 0; - for (unsigned i = 0, e = RegClassRegs.size(); i != e; ++i) { - unsigned Reg = RegClassRegs[i]; - // Filter out the reserved registers, but note that reserved registers are - // not fully determined at this point. We may still decide we need a frame - // pointer. - if (Reserved.test(Reg)) - continue; - // See if this register is available. - if ((isOutReg && OutputRegs.count(Reg)) || // Already used. - (isInReg && InputRegs.count(Reg))) { // Already used. - // Make sure we find consecutive registers. - NumAllocated = 0; - continue; - } - - // Check to see if this register is allocatable (i.e. don't give out the - // stack pointer). - const TargetRegisterClass *RC = isAllocatableRegister(Reg, MF, TLI, TRI); - if (!RC) { // Couldn't allocate this register. - // Reset NumAllocated to make sure we return consecutive registers. - NumAllocated = 0; - continue; - } - - // Okay, this register is good, we can use it. - ++NumAllocated; - - // If we allocated enough consecutive registers, succeed. - if (NumAllocated == NumRegs) { - unsigned RegStart = (i-NumAllocated)+1; - unsigned RegEnd = i+1; - // Mark all of the allocated registers used. - for (unsigned i = RegStart; i != RegEnd; ++i) - Regs.push_back(RegClassRegs[i]); - - OpInfo.AssignedRegs = RegsForValue(Regs, *RC->vt_begin(), - OpInfo.ConstraintVT); - OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); - return; - } - } - // Otherwise, we couldn't allocate enough registers for this. } Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=134123&r1=134122&r2=134123&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original) +++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Wed Jun 29 20:20:03 2011 @@ -2737,13 +2737,6 @@ } } -std::vector TargetLowering:: -getRegClassForInlineAsmConstraint(const std::string &Constraint, - EVT VT) const { - return std::vector(); -} - - std::pair TargetLowering:: getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const { From atrick at apple.com Wed Jun 29 20:27:23 2011 From: atrick at apple.com (Andrew Trick) Date: Thu, 30 Jun 2011 01:27:23 -0000 Subject: [llvm-commits] [llvm] r134124 - in /llvm/trunk: lib/Transforms/Scalar/IndVarSimplify.cpp test/Transforms/IndVarSimplify/no-iv-rewrite.ll Message-ID: <20110630012723.5D4A82A6C12C@llvm.org> Author: atrick Date: Wed Jun 29 20:27:23 2011 New Revision: 134124 URL: http://llvm.org/viewvc/llvm-project?rev=134124&view=rev Log: indvars -disable-iv-rewrite: handle an edge case involving identity phis. Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=134124&r1=134123&r2=134124&view=diff ============================================================================== --- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original) +++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Wed Jun 29 20:27:23 2011 @@ -1015,9 +1015,9 @@ (SE->getSCEV(UseInst) != SE->getSCEV(IVOperand))) return false; - UseInst->replaceAllUsesWith(IVOperand); - DEBUG(dbgs() << "INDVARS: Eliminated identity: " << *UseInst << '\n'); + + UseInst->replaceAllUsesWith(IVOperand); ++NumElimIdentity; Changed = true; DeadInsts.push_back(UseInst); @@ -1037,7 +1037,9 @@ // Avoid infinite or exponential worklist processing. // Also ensure unique worklist users. - if (Simplified.insert(User)) + // If Def is a LoopPhi, it may not be in the Simplified set, so check for + // self edges first. + if (User != Def && Simplified.insert(User)) SimpleIVUsers.push_back(std::make_pair(User, Def)); } } @@ -1111,6 +1113,9 @@ // Use-def pairs if IVUsers waiting to be processed for CurrIV. SmallVector, 8> SimpleIVUsers; + // Push users of the current LoopPhi. In rare cases, pushIVUsers may be + // called multiple times for the same LoopPhi. This is the proper thing to + // do for loop header phis that use each other. pushIVUsers(CurrIV, Simplified, SimpleIVUsers); while (!SimpleIVUsers.empty()) { Modified: llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll?rev=134124&r1=134123&r2=134124&view=diff ============================================================================== --- llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll (original) +++ llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Wed Jun 29 20:27:23 2011 @@ -23,7 +23,7 @@ ; sext should be eliminated while preserving gep inboundsness. ; CHECK-NOT: sext ; CHECK: getelementptr inbounds -; CHECK: exit +; CHECK: exit: loop: %i.02 = phi i32 [ 0, %ph ], [ %iinc, %loop ] %s.01 = phi i32 [ 0, %ph ], [ %sinc, %loop ] @@ -64,7 +64,7 @@ ; CHECK: getelementptr inbounds ; %vall sext should obviously not be eliminated ; CHECK: sext -; CHECK: exit +; CHECK: exit: loop: %i.02 = phi i32 [ 0, %ph ], [ %iinc, %loop ] %s.01 = phi i64 [ 0, %ph ], [ %sinc, %loop ] @@ -108,7 +108,7 @@ ; Preserve gep inboundsness, and don't factor it. ; CHECK: getelementptr inbounds i32* %ptriv, i32 1 ; CHECK-NOT: add -; CHECK: exit +; CHECK: exit: loop: %ptriv = phi i32* [ %first, %ph ], [ %ptrpost, %loop ] %ofs = sext i32 %idx to i64 @@ -139,7 +139,7 @@ ; CHECK: phi i32 ; CHECK: bitcast ; CHECK: getelementptr -; CHECK: exit +; CHECK: exit: loop: %iv = phi i32 [%start, %entry], [%next, %loop] %p = phi %struct* [%base, %entry], [%pinc, %loop] @@ -157,12 +157,13 @@ } define void @maxvisitor(i32 %limit, i32* %base) nounwind { -entry: br label %loop +entry: + br label %loop ; CHECK: loop: ; CHECK: phi i64 ; CHECK: trunc -; CHECK: exit +; CHECK: exit: loop: %idx = phi i32 [ 0, %entry ], [ %idx.next, %loop.inc ] %max = phi i32 [ 0, %entry ], [ %max.next, %loop.inc ] @@ -186,4 +187,28 @@ exit: ret void -} \ No newline at end of file +} + +; CHECK: loop: +; CHECK: phi i32 +; CHECK-NOT: phi +; CHECK: exit: +define void @identityphi(i32 %limit) nounwind { +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry], [ %iv.next, %control ] + br i1 undef, label %if.then, label %control + +if.then: + br label %control + +control: + %iv.next = phi i32 [ %iv, %loop ], [ undef, %if.then ] + %cmp = icmp slt i32 %iv.next, %limit + br i1 %cmp, label %loop, label %exit + +exit: + ret void +} From stoklund at 2pi.dk Wed Jun 29 20:30:39 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Thu, 30 Jun 2011 01:30:39 -0000 Subject: [llvm-commits] [llvm] r134125 - in /llvm/trunk/lib/CodeGen: RegAllocGreedy.cpp SplitKit.cpp SplitKit.h Message-ID: <20110630013039.834B02A6C12C@llvm.org> Author: stoklund Date: Wed Jun 29 20:30:39 2011 New Revision: 134125 URL: http://llvm.org/viewvc/llvm-project?rev=134125&view=rev Log: Reapply r134047 now that the world is ready for it. This patch will sometimes choose live range split points next to interference instead of always splitting next to a register point. That means spill code can now appear almost anywhere, and it was necessary to fix code that didn't expect that. The difficult places were: - Between a CALL returning a value on the x87 stack and the corresponding FpPOP_RETVAL (was FpGET_ST0). Probably also near x87 inline assembly, but that didn't actually show up in testing. - Between a CALL popping arguments off the stack and the corresponding ADJCALLSTACKUP. Both are fixed now. The only place spill code can't appear is after terminators, see SplitAnalysis::getLastSplitPoint. Original commit message: Rewrite RAGreedy::splitAroundRegion, now with cool ASCII art. This function has to deal with a lot of special cases, and the old version got it wrong sometimes. In particular, it would sometimes leave multiple uses in the stack interval in a single block. That causes bad code with multiple reloads in the same basic block. The new version handles block entry and exit in a single pass. It first eliminates all the easy cases, and then goes on to create a local interval for the blocks with difficult interference. Previously, we would only create the local interval for completely isolated blocks. It can happen that the stack interval becomes completely empty because we could allocate a register in all edge bundles, and the new local intervals deal with the interference. The empty stack interval is harmless, but we need to remove a SplitKit assertion that checks for empty intervals. Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp llvm/trunk/lib/CodeGen/SplitKit.cpp llvm/trunk/lib/CodeGen/SplitKit.h Modified: llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp?rev=134125&r1=134124&r2=134125&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp (original) +++ llvm/trunk/lib/CodeGen/RegAllocGreedy.cpp Wed Jun 29 20:30:39 2011 @@ -763,32 +763,46 @@ // Create the main cross-block interval. const unsigned MainIntv = SE->openIntv(); - // First add all defs that are live out of a block. + // First handle all the blocks with uses. ArrayRef UseBlocks = SA->getUseBlocks(); for (unsigned i = 0; i != UseBlocks.size(); ++i) { const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; - bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; - bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; + bool RegIn = BI.LiveIn && + LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; + bool RegOut = BI.LiveOut && + LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; // Create separate intervals for isolated blocks with multiple uses. - if (!RegIn && !RegOut && BI.FirstUse != BI.LastUse) { + // + // |---o---o---| Enter and leave on the stack. + // ____-----____ Create local interval for uses. + // + // | o---o---| Defined in block, leave on stack. + // -----____ Create local interval for uses. + // + // |---o---x | Enter on stack, killed in block. + // ____----- Create local interval for uses. + // + if (!RegIn && !RegOut) { DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " isolated.\n"); - SE->splitSingleBlock(BI); - SE->selectIntv(MainIntv); + if (!BI.isOneInstr()) { + SE->splitSingleBlock(BI); + SE->selectIntv(MainIntv); + } continue; } - // Should the register be live out? - if (!BI.LiveOut || !RegOut) - continue; - SlotIndex Start, Stop; tie(Start, Stop) = Indexes->getMBBRange(BI.MBB); Intf.moveToBlock(BI.MBB->getNumber()); - DEBUG(dbgs() << "BB#" << BI.MBB->getNumber() << " -> EB#" - << Bundles->getBundle(BI.MBB->getNumber(), 1) + DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0) + << (RegIn ? " => " : " -- ") + << "BB#" << BI.MBB->getNumber() + << (RegOut ? " => " : " -- ") + << " EB#" << Bundles->getBundle(BI.MBB->getNumber(), 1) << " [" << Start << ';' << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop + << ") uses [" << BI.FirstUse << ';' << BI.LastUse << ") intf [" << Intf.first() << ';' << Intf.last() << ')'); // The interference interval should either be invalid or overlap MBB. @@ -797,150 +811,266 @@ assert((!Intf.hasInterference() || Intf.last() > Start) && "Bad interference"); - // Check interference leaving the block. + // We are now ready to decide where to split in the current block. There + // are many variables guiding the decision: + // + // - RegIn / RegOut: The global splitting algorithm's decisions for our + // ingoing and outgoing bundles. + // + // - BI.BlockIn / BI.BlockOut: Is the live range live-in and/or live-out + // from this block. + // + // - Intf.hasInterference(): Is there interference in this block. + // + // - Intf.first() / Inft.last(): The range of interference. + // + // The live range should be split such that MainIntv is live-in when RegIn + // is set, and live-out when RegOut is set. MainIntv should never overlap + // the interference, and the stack interval should never have more than one + // use per block. + + // No splits can be inserted after LastSplitPoint, overlap instead. + SlotIndex LastSplitPoint = Stop; + if (BI.LiveOut) + LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); + + // At this point, we know that either RegIn or RegOut is set. We dealt with + // the all-stack case above. + + // Blocks without interference are relatively easy. if (!Intf.hasInterference()) { - // Block is interference-free. - DEBUG(dbgs() << ", no interference"); - if (!BI.LiveThrough) { - DEBUG(dbgs() << ", not live-through.\n"); - SE->useIntv(SE->enterIntvBefore(BI.FirstUse), Stop); - continue; - } - if (!RegIn) { - // Block is live-through, but entry bundle is on the stack. - // Reload just before the first use. - DEBUG(dbgs() << ", not live-in, enter before first use.\n"); - SE->useIntv(SE->enterIntvBefore(BI.FirstUse), Stop); - continue; - } - DEBUG(dbgs() << ", live-through.\n"); - continue; - } + DEBUG(dbgs() << ", no interference.\n"); + SE->selectIntv(MainIntv); + // The easiest case has MainIntv live through. + // + // |---o---o---| Live-in, live-out. + // ============= Use MainIntv everywhere. + // + SlotIndex From = Start, To = Stop; + + // Block entry. Reload before the first use if MainIntv is not live-in. + // + // |---o-- Enter on stack. + // ____=== Reload before first use. + // + // | o-- Defined in block. + // === Use MainIntv from def. + // + if (!RegIn) + From = SE->enterIntvBefore(BI.FirstUse); - // Block has interference. - DEBUG(dbgs() << ", interference to " << Intf.last()); + // Block exit. Handle cases where MainIntv is not live-out. + if (!BI.LiveOut) + // + // --x | Killed in block. + // === Use MainIntv up to kill. + // + To = SE->leaveIntvAfter(BI.LastUse); + else if (!RegOut) { + // + // --o---| Live-out on stack. + // ===____ Use MainIntv up to last use, switch to stack. + // + // -----o| Live-out on stack, last use after last split point. + // ====== Extend MainIntv to last use, overlapping. + // \____ Copy to stack interval before last split point. + // + if (BI.LastUse < LastSplitPoint) + To = SE->leaveIntvAfter(BI.LastUse); + else { + // The last use is after the last split point, it is probably an + // indirect branch. + To = SE->leaveIntvBefore(LastSplitPoint); + // Run a double interval from the split to the last use. This makes + // it possible to spill the complement without affecting the indirect + // branch. + SE->overlapIntv(To, BI.LastUse); + } + } - if (!BI.LiveThrough && Intf.last() <= BI.FirstUse) { - // The interference doesn't reach the outgoing segment. - DEBUG(dbgs() << " doesn't affect def from " << BI.FirstUse << '\n'); - SE->useIntv(BI.FirstUse, Stop); + // Paint in MainIntv liveness for this block. + SE->useIntv(From, To); continue; } - SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); - if (Intf.last().getBoundaryIndex() < BI.LastUse) { - // There are interference-free uses at the end of the block. - // Find the first use that can get the live-out register. - SmallVectorImpl::const_iterator UI = - std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), - Intf.last().getBoundaryIndex()); - assert(UI != SA->UseSlots.end() && "Couldn't find last use"); - SlotIndex Use = *UI; - assert(Use <= BI.LastUse && "Couldn't find last use"); - // Only attempt a split befroe the last split point. - if (Use.getBaseIndex() <= LastSplitPoint) { - DEBUG(dbgs() << ", free use at " << Use << ".\n"); - SlotIndex SegStart = SE->enterIntvBefore(Use); - assert(SegStart >= Intf.last() && "Couldn't avoid interference"); - assert(SegStart < LastSplitPoint && "Impossible split point"); - SE->useIntv(SegStart, Stop); - continue; - } - } + // We are now looking at a block with interference, and we know that either + // RegIn or RegOut is set. + assert(Intf.hasInterference() && (RegIn || RegOut) && "Bad invariant"); - // Interference is after the last use. - DEBUG(dbgs() << " after last use.\n"); - SlotIndex SegStart = SE->enterIntvAtEnd(*BI.MBB); - assert(SegStart >= Intf.last() && "Couldn't avoid interference"); - } + // If the live range is not live through the block, it is possible that the + // interference doesn't even overlap. Deal with those cases first. Since + // no copy instructions are required, we can tolerate interference starting + // or ending at the same instruction that kills or defines our live range. - // Now all defs leading to live bundles are handled, do everything else. - for (unsigned i = 0; i != UseBlocks.size(); ++i) { - const SplitAnalysis::BlockInfo &BI = UseBlocks[i]; - bool RegIn = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 0)]; - bool RegOut = LiveBundles[Bundles->getBundle(BI.MBB->getNumber(), 1)]; + // Live-in, killed before interference. + // + // ~~~ Interference after kill. + // |---o---x | Killed in block. + // ========= Use MainIntv everywhere. + // + if (RegIn && !BI.LiveOut && BI.LastUse <= Intf.first()) { + DEBUG(dbgs() << ", live-in, killed before interference.\n"); + SE->selectIntv(MainIntv); + SlotIndex To = SE->leaveIntvAfter(BI.LastUse); + SE->useIntv(Start, To); + continue; + } - // Is the register live-in? - if (!BI.LiveIn || !RegIn) + // Live-out, defined after interference. + // + // ~~~ Interference before def. + // | o---o---| Defined in block. + // ========= Use MainIntv everywhere. + // + if (RegOut && !BI.LiveIn && BI.FirstUse >= Intf.last()) { + DEBUG(dbgs() << ", live-out, defined after interference.\n"); + SE->selectIntv(MainIntv); + SlotIndex From = SE->enterIntvBefore(BI.FirstUse); + SE->useIntv(From, Stop); continue; + } - // We have an incoming register. Check for interference. - SlotIndex Start, Stop; - tie(Start, Stop) = Indexes->getMBBRange(BI.MBB); - Intf.moveToBlock(BI.MBB->getNumber()); - DEBUG(dbgs() << "EB#" << Bundles->getBundle(BI.MBB->getNumber(), 0) - << " -> BB#" << BI.MBB->getNumber() << " [" << Start << ';' - << SA->getLastSplitPoint(BI.MBB->getNumber()) << '-' << Stop - << ')'); + // The interference is now known to overlap the live range, but it may + // still be easy to avoid if all the interference is on one side of the + // uses, and we enter or leave on the stack. - // Check interference entering the block. - if (!Intf.hasInterference()) { - // Block is interference-free. - DEBUG(dbgs() << ", no interference"); - if (!BI.LiveThrough) { - DEBUG(dbgs() << ", killed in block.\n"); - SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse)); - continue; - } - if (!RegOut) { - SlotIndex LastSplitPoint = SA->getLastSplitPoint(BI.MBB->getNumber()); - // Block is live-through, but exit bundle is on the stack. - // Spill immediately after the last use. - if (BI.LastUse < LastSplitPoint) { - DEBUG(dbgs() << ", uses, stack-out.\n"); - SE->useIntv(Start, SE->leaveIntvAfter(BI.LastUse)); - continue; - } - // The last use is after the last split point, it is probably an - // indirect jump. - DEBUG(dbgs() << ", uses at " << BI.LastUse << " after split point " - << LastSplitPoint << ", stack-out.\n"); - SlotIndex SegEnd = SE->leaveIntvBefore(LastSplitPoint); - SE->useIntv(Start, SegEnd); - // Run a double interval from the split to the last use. - // This makes it possible to spill the complement without affecting the - // indirect branch. - SE->overlapIntv(SegEnd, BI.LastUse); - continue; + // Live-out on stack, interference after last use. + // + // ~~~ Interference after last use. + // |---o---o---| Live-out on stack. + // =========____ Leave MainIntv after last use. + // + // ~ Interference after last use. + // |---o---o--o| Live-out on stack, late last use. + // =========____ Copy to stack after LSP, overlap MainIntv. + // + if (!RegOut && Intf.first() > BI.LastUse.getBoundaryIndex()) { + assert(RegIn && "Stack-in, stack-out should already be handled"); + if (BI.LastUse < LastSplitPoint) { + DEBUG(dbgs() << ", live-in, stack-out, interference after last use.\n"); + SE->selectIntv(MainIntv); + SlotIndex To = SE->leaveIntvAfter(BI.LastUse); + assert(To <= Intf.first() && "Expected to avoid interference"); + SE->useIntv(Start, To); + } else { + DEBUG(dbgs() << ", live-in, stack-out, avoid last split point\n"); + SE->selectIntv(MainIntv); + SlotIndex To = SE->leaveIntvBefore(LastSplitPoint); + assert(To <= Intf.first() && "Expected to avoid interference"); + SE->overlapIntv(To, BI.LastUse); + SE->useIntv(Start, To); } - // Register is live-through. - DEBUG(dbgs() << ", uses, live-through.\n"); - SE->useIntv(Start, Stop); continue; } - // Block has interference. - DEBUG(dbgs() << ", interference from " << Intf.first()); - - if (!BI.LiveThrough && Intf.first() >= BI.LastUse) { - // The interference doesn't reach the outgoing segment. - DEBUG(dbgs() << " doesn't affect kill at " << BI.LastUse << '\n'); - SE->useIntv(Start, BI.LastUse); + // Live-in on stack, interference before first use. + // + // ~~~ Interference before first use. + // |---o---o---| Live-in on stack. + // ____========= Enter MainIntv before first use. + // + if (!RegIn && Intf.last() < BI.FirstUse.getBaseIndex()) { + assert(RegOut && "Stack-in, stack-out should already be handled"); + DEBUG(dbgs() << ", stack-in, interference before first use.\n"); + SE->selectIntv(MainIntv); + SlotIndex From = SE->enterIntvBefore(BI.FirstUse); + assert(From >= Intf.last() && "Expected to avoid interference"); + SE->useIntv(From, Stop); continue; } - if (Intf.first().getBaseIndex() > BI.FirstUse) { - // There are interference-free uses at the beginning of the block. - // Find the last use that can get the register. - SmallVectorImpl::const_iterator UI = - std::lower_bound(SA->UseSlots.begin(), SA->UseSlots.end(), - Intf.first().getBaseIndex()); - assert(UI != SA->UseSlots.begin() && "Couldn't find first use"); - SlotIndex Use = (--UI)->getBoundaryIndex(); - DEBUG(dbgs() << ", free use at " << *UI << ".\n"); - SlotIndex SegEnd = SE->leaveIntvAfter(Use); - assert(SegEnd <= Intf.first() && "Couldn't avoid interference"); - SE->useIntv(Start, SegEnd); - continue; + // The interference is overlapping somewhere we wanted to use MainIntv. That + // means we need to create a local interval that can be allocated a + // different register. + DEBUG(dbgs() << ", creating local interval.\n"); + unsigned LocalIntv = SE->openIntv(); + + // We may be creating copies directly between MainIntv and LocalIntv, + // bypassing the stack interval. When we do that, we should never use the + // leaveIntv* methods as they define values in the stack interval. By + // starting from the end of the block and working our way backwards, we can + // get by with only enterIntv* methods. + // + // When selecting split points, we generally try to maximize the stack + // interval as long at it contains no uses, maximize the main interval as + // long as it doesn't overlap interference, and minimize the local interval + // that we don't know how to allocate yet. + + // Handle the block exit, set Pos to the first handled slot. + SlotIndex Pos = BI.LastUse; + if (RegOut) { + assert(Intf.last() < LastSplitPoint && "Cannot be live-out in register"); + // Create a snippet of MainIntv that is live-out. + // + // ~~~ Interference overlapping uses. + // --o---| Live-out in MainIntv. + // ----=== Switch from LocalIntv to MainIntv after interference. + // + SE->selectIntv(MainIntv); + Pos = SE->enterIntvAfter(Intf.last()); + assert(Pos >= Intf.last() && "Expected to avoid interference"); + SE->useIntv(Pos, Stop); + SE->selectIntv(LocalIntv); + } else if (BI.LiveOut) { + if (BI.LastUse < LastSplitPoint) { + // Live-out on the stack. + // + // ~~~ Interference overlapping uses. + // --o---| Live-out on stack. + // ---____ Switch from LocalIntv to stack after last use. + // + Pos = SE->leaveIntvAfter(BI.LastUse); + } else { + // Live-out on the stack, last use after last split point. + // + // ~~~ Interference overlapping uses. + // --o--o| Live-out on stack, late use. + // ------ Copy to stack before LSP, overlap LocalIntv. + // \__ + // + Pos = SE->leaveIntvBefore(LastSplitPoint); + // We need to overlap LocalIntv so it can reach LastUse. + SE->overlapIntv(Pos, BI.LastUse); + } } - // Interference is before the first use. - DEBUG(dbgs() << " before first use.\n"); - SlotIndex SegEnd = SE->leaveIntvAtTop(*BI.MBB); - assert(SegEnd <= Intf.first() && "Couldn't avoid interference"); + // When not live-out, leave Pos at LastUse. We have handled everything from + // Pos to Stop. Find the starting point for LocalIntv. + assert(SE->currentIntv() == LocalIntv && "Expecting local interval"); + + if (RegIn) { + assert(Start < Intf.first() && "Cannot be live-in with interference"); + // Live-in in MainIntv, only use LocalIntv for interference. + // + // ~~~ Interference overlapping uses. + // |---o-- Live-in in MainIntv. + // ====--- Switch to LocalIntv before interference. + // + SlotIndex Switch = SE->enterIntvBefore(Intf.first()); + assert(Switch <= Intf.first() && "Expected to avoid interference"); + SE->useIntv(Switch, Pos); + SE->selectIntv(MainIntv); + SE->useIntv(Start, Switch); + } else { + // Live-in on stack, enter LocalIntv before first use. + // + // ~~~ Interference overlapping uses. + // |---o-- Live-in in MainIntv. + // ____--- Reload to LocalIntv before interference. + // + // Defined in block. + // + // ~~~ Interference overlapping uses. + // | o-- Defined in block. + // --- Begin LocalIntv at first use. + // + SlotIndex Switch = SE->enterIntvBefore(BI.FirstUse); + SE->useIntv(Switch, Pos); + } } // Handle live-through blocks. + SE->selectIntv(MainIntv); for (unsigned i = 0, e = Cand.ActiveBlocks.size(); i != e; ++i) { unsigned Number = Cand.ActiveBlocks[i]; bool RegIn = LiveBundles[Bundles->getBundle(Number, 0)]; Modified: llvm/trunk/lib/CodeGen/SplitKit.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.cpp?rev=134125&r1=134124&r2=134125&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.cpp (original) +++ llvm/trunk/lib/CodeGen/SplitKit.cpp Wed Jun 29 20:30:39 2011 @@ -636,6 +636,7 @@ void SplitEditor::selectIntv(unsigned Idx) { assert(Idx != 0 && "Cannot select the complement interval"); assert(Idx < Edit->size() && "Can only select previously opened interval"); + DEBUG(dbgs() << " selectIntv " << OpenIdx << " -> " << Idx << '\n'); OpenIdx = Idx; } @@ -656,6 +657,24 @@ return VNI->def; } +SlotIndex SplitEditor::enterIntvAfter(SlotIndex Idx) { + assert(OpenIdx && "openIntv not called before enterIntvAfter"); + DEBUG(dbgs() << " enterIntvAfter " << Idx); + Idx = Idx.getBoundaryIndex(); + VNInfo *ParentVNI = Edit->getParent().getVNInfoAt(Idx); + if (!ParentVNI) { + DEBUG(dbgs() << ": not live\n"); + return Idx; + } + DEBUG(dbgs() << ": valno " << ParentVNI->id << '\n'); + MachineInstr *MI = LIS.getInstructionFromIndex(Idx); + assert(MI && "enterIntvAfter called with invalid index"); + + VNInfo *VNI = defFromParent(OpenIdx, ParentVNI, Idx, *MI->getParent(), + llvm::next(MachineBasicBlock::iterator(MI))); + return VNI->def; +} + SlotIndex SplitEditor::enterIntvAtEnd(MachineBasicBlock &MBB) { assert(OpenIdx && "openIntv not called before enterIntvAtEnd"); SlotIndex End = LIS.getMBBEndIdx(&MBB); @@ -1007,12 +1026,6 @@ markComplexMapped(i, ParentVNI); } -#ifndef NDEBUG - // Every new interval must have a def by now, otherwise the split is bogus. - for (LiveRangeEdit::iterator I = Edit->begin(), E = Edit->end(); I != E; ++I) - assert((*I)->hasAtLeastOneValue() && "Split interval has no value"); -#endif - // Transfer the simply mapped values, check if any are skipped. bool Skipped = transferValues(); if (Skipped) Modified: llvm/trunk/lib/CodeGen/SplitKit.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SplitKit.h?rev=134125&r1=134124&r2=134125&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/SplitKit.h (original) +++ llvm/trunk/lib/CodeGen/SplitKit.h Wed Jun 29 20:30:39 2011 @@ -81,6 +81,12 @@ bool LiveThrough; ///< Live in whole block (Templ 5. above). bool LiveIn; ///< Current reg is live in. bool LiveOut; ///< Current reg is live out. + + /// isOneInstr - Returns true when this BlockInfo describes a single + /// instruction. + bool isOneInstr() const { + return SlotIndex::isSameInstr(FirstUse, LastUse); + } }; private: @@ -360,6 +366,10 @@ /// Return the beginning of the new live range. SlotIndex enterIntvBefore(SlotIndex Idx); + /// enterIntvAfter - Enter the open interval after the instruction at Idx. + /// Return the beginning of the new live range. + SlotIndex enterIntvAfter(SlotIndex Idx); + /// enterIntvAtEnd - Enter the open interval at the end of MBB. /// Use the open interval from he inserted copy to the MBB end. /// Return the beginning of the new live range. From stoklund at 2pi.dk Wed Jun 29 20:33:56 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 29 Jun 2011 18:33:56 -0700 Subject: [llvm-commits] [llvm] r134123 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp In-Reply-To: <20110630012004.1CBC32A6C12C@llvm.org> References: <20110630012004.1CBC32A6C12C@llvm.org> Message-ID: On Jun 29, 2011, at 6:20 PM, Eric Christopher wrote: > -static const TargetRegisterClass * > -isAllocatableRegister(unsigned Reg, MachineFunction &MF, > - const TargetLowering &TLI, > - const TargetRegisterInfo *TRI) { ... > - for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), > - E = TRI->regclass_end(); RCI != E; ++RCI) { ... > - for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); > - I != E; ++I) { > - if (TLI.isTypeLegal(*I)) { > - // If we have already found this register in a different register class, > - // choose the one with the largest VT specified. For example, on > - // PowerPC, we favor f64 register classes over f32. > - if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { Awesome! That function was particularly special. Thanks /jakob -------------- next part -------------- An HTML attachment was scrubbed... URL: http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110629/789d3959/attachment.html From echristo at apple.com Wed Jun 29 20:36:35 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 18:36:35 -0700 Subject: [llvm-commits] [llvm] r134123 - in /llvm/trunk: include/llvm/Target/TargetLowering.h lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp lib/CodeGen/SelectionDAG/TargetLowering.cpp In-Reply-To: References: <20110630012004.1CBC32A6C12C@llvm.org> Message-ID: <2F96B0CF-04DC-4948-9575-CAAEE7003A5F@apple.com> On Jun 29, 2011, at 6:33 PM, Jakob Stoklund Olesen wrote: > > On Jun 29, 2011, at 6:20 PM, Eric Christopher wrote: > >> -static const TargetRegisterClass * >> -isAllocatableRegister(unsigned Reg, MachineFunction &MF, >> - const TargetLowering &TLI, >> - const TargetRegisterInfo *TRI) { > ... >> - for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(), >> - E = TRI->regclass_end(); RCI != E; ++RCI) { > ... >> - for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end(); >> - I != E; ++I) { >> - if (TLI.isTypeLegal(*I)) { >> - // If we have already found this register in a different register class, >> - // choose the one with the largest VT specified. For example, on >> - // PowerPC, we favor f64 register classes over f32. >> - if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) { > > Awesome! That function was particularly special. It was. I'd never really seen it before just now and it scared me. :) -eric From joerg at bec.de Wed Jun 29 20:38:03 2011 From: joerg at bec.de (Joerg Sonnenberger) Date: Thu, 30 Jun 2011 01:38:03 -0000 Subject: [llvm-commits] [llvm] r134126 - in /llvm/trunk: lib/Target/X86/X86InstrSystem.td test/MC/X86/padlock.s Message-ID: <20110630013803.719362A6C12C@llvm.org> Author: joerg Date: Wed Jun 29 20:38:03 2011 New Revision: 134126 URL: http://llvm.org/viewvc/llvm-project?rev=134126&view=rev Log: Recognize the xstorerng alias for VIA PadLock's xstore instruction. Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td llvm/trunk/test/MC/X86/padlock.s Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=134126&r1=134125&r2=134126&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original) +++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Wed Jun 29 20:38:03 2011 @@ -411,6 +411,8 @@ let Defs = [RAX, RDI], Uses = [RDX, RDI] in def XSTORE : I<0xc0, RawFrm, (outs), (ins), "xstore", []>, A7; +def : InstAlias<"xstorerng", (XSTORE)>; + let Defs = [RSI, RDI], Uses = [RBX, RDX, RSI, RDI] in { def XCRYPTECB : I<0xc8, RawFrm, (outs), (ins), "xcryptecb", []>, A7; def XCRYPTCBC : I<0xd0, RawFrm, (outs), (ins), "xcryptcbc", []>, A7; Modified: llvm/trunk/test/MC/X86/padlock.s URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/X86/padlock.s?rev=134126&r1=134125&r2=134126&view=diff ============================================================================== --- llvm/trunk/test/MC/X86/padlock.s (original) +++ llvm/trunk/test/MC/X86/padlock.s Wed Jun 29 20:38:03 2011 @@ -4,6 +4,10 @@ // CHECK: xstore // CHECK: encoding: [0x0f,0xa7,0xc0] + xstorerng +// CHECK: xstore +// CHECK: encoding: [0x0f,0xa7,0xc0] + rep xcryptecb // CHECK: rep // CHECK: encoding: [0xf3] From echristo at apple.com Wed Jun 29 20:46:37 2011 From: echristo at apple.com (Eric Christopher) Date: Wed, 29 Jun 2011 18:46:37 -0700 Subject: [llvm-commits] [llvm] r134113 - /llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp In-Reply-To: <20110629231139.537C92A6C12C@llvm.org> References: <20110629231139.537C92A6C12C@llvm.org> Message-ID: <8D96550F-7406-4634-923A-05CCC4A32BE0@apple.com> On Jun 29, 2011, at 4:11 PM, Jakob Stoklund Olesen wrote: > Fix this by inserting the stack pointer adjustment immediately after the > call instead of where the ADJCALLSTACKUP instruction was erased. Aha! Nice fix. -eric From evan.cheng at apple.com Wed Jun 29 20:49:34 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 29 Jun 2011 18:49:34 -0700 Subject: [llvm-commits] [llvm] r134114 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMLoadStoreOptimizer.cpp lib/Target/ARM/Thumb2InstrInfo.cpp lib/Target/ARM/Thumb2SizeReduction.cpp utils/TableGen/ARMDecoderEmitter.cpp In-Reply-To: <20110629232504.76FFD2A6C12C@llvm.org> References: <20110629232504.76FFD2A6C12C@llvm.org> Message-ID: <89BB605A-2617-4146-B5DF-AEA59CCC1213@apple.com> Thumb2InstrInfo.cpp:422:10: warning: unused variable 'isSP' [-Wunused-variable] bool isSP = FrameReg == ARM::SP; ^ On Jun 29, 2011, at 4:25 PM, Jim Grosbach wrote: > Author: grosbach > Date: Wed Jun 29 18:25:04 2011 > New Revision: 134114 > > URL: http://llvm.org/viewvc/llvm-project?rev=134114&view=rev > Log: > Remove redundant Thumb2 ADD/SUB SP instruction definitions. > > Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the > stack pointer. It can just use the normal add-register-immediate encoding > since it can use all registers as a source, not just R0-R7. The extra > instruction definitions are just duplicates of the normal instructions with > the (not well enforced) constraint that the source register was SP. > > > Modified: > llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp > llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp > llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp > llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp > llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp > > Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134114&r1=134113&r2=134114&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Jun 29 18:25:04 2011 > @@ -1018,11 +1018,10 @@ > Offset = -MI->getOperand(2).getImm(); > break; > case ARM::SUBri: > - case ARM::t2SUBrSPi: > - Offset = MI->getOperand(2).getImm(); > + Offset = MI->getOperand(2).getImm(); > break; > case ARM::tSUBspi: > - Offset = MI->getOperand(2).getImm()*4; > + Offset = MI->getOperand(2).getImm()*4; > break; > case ARM::tADDspi: > case ARM::tADDrSPi: > @@ -1097,13 +1096,6 @@ > OutStreamer.EmitInstruction(TmpInst); > return; > } > - case ARM::t2ADDrSPi: > - case ARM::t2ADDrSPi12: > - case ARM::t2SUBrSPi: > - case ARM::t2SUBrSPi12: > - assert ((MI->getOperand(1).getReg() == ARM::SP) && > - "Unexpected source register!"); > - break; > > case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass"); > case ARM::DBG_VALUE: { > > Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=134114&r1=134113&r2=134114&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Jun 29 18:25:04 2011 > @@ -1284,9 +1284,5 @@ > } > // Update the original instruction to use the scratch register. > MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); > - if (MI.getOpcode() == ARM::t2ADDrSPi) > - MI.setDesc(TII.get(ARM::t2ADDri)); > - else if (MI.getOpcode() == ARM::t2SUBrSPi) > - MI.setDesc(TII.get(ARM::t2SUBri)); > } > } > > Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=134114&r1=134113&r2=134114&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) > +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jun 29 18:25:04 2011 > @@ -1169,63 +1169,6 @@ > []>; > > > -// FIXME: None of these add/sub SP special instructions should be necessary > -// at all for thumb2 since they use the same encodings as the generic > -// add/sub instructions. In thumb1 we need them since they have dedicated > -// encodings. At the least, they should be pseudo instructions. > -// ADD r, sp, {so_imm|i12} > -let isCodeGenOnly = 1 in { > -def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), > - IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> { > - let Inst{31-27} = 0b11110; > - let Inst{25} = 0; > - let Inst{24-21} = 0b1000; > - let Inst{15} = 0; > -} > -def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), > - IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> { > - let Inst{31-27} = 0b11110; > - let Inst{25-20} = 0b100000; > - let Inst{15} = 0; > -} > - > -// ADD r, sp, so_reg > -def t2ADDrSPs : T2sTwoRegShiftedReg< > - (outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), > - IIC_iALUsi, "add", ".w\t$Rd, $Rn, $ShiftedRm", []> { > - let Inst{31-27} = 0b11101; > - let Inst{26-25} = 0b01; > - let Inst{24-21} = 0b1000; > - let Inst{15} = 0; > -} > - > -// SUB r, sp, {so_imm|i12} > -def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), > - IIC_iALUi, "sub", ".w\t$Rd, $Rn, $imm", []> { > - let Inst{31-27} = 0b11110; > - let Inst{25} = 0; > - let Inst{24-21} = 0b1101; > - let Inst{15} = 0; > -} > -def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), > - IIC_iALUi, "subw", "\t$Rd, $Rn, $imm", []> { > - let Inst{31-27} = 0b11110; > - let Inst{25-20} = 0b101010; > - let Inst{15} = 0; > -} > - > -// SUB r, sp, so_reg > -def t2SUBrSPs : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm), > - IIC_iALUsi, > - "sub", "\t$Rd, $Rn, $imm", []> { > - let Inst{31-27} = 0b11101; > - let Inst{26-25} = 0b01; > - let Inst{24-21} = 0b1101; > - let Inst{19-16} = 0b1101; // Rn = sp > - let Inst{15} = 0; > -} > -} // end isCodeGenOnly = 1 > - > //===----------------------------------------------------------------------===// > // Load / store Instructions. > // > > Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=134114&r1=134113&r2=134114&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) > +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Jun 29 18:25:04 2011 > @@ -329,13 +329,9 @@ > if (NewBase == 0) > return false; > } > - int BaseOpc = !isThumb2 > - ? ARM::ADDri > - : ((Base == ARM::SP) ? ARM::t2ADDrSPi : ARM::t2ADDri); > + int BaseOpc = !isThumb2 ? ARM::ADDri : ARM::t2ADDri; > if (Offset < 0) { > - BaseOpc = !isThumb2 > - ? ARM::SUBri > - : ((Base == ARM::SP) ? ARM::t2SUBrSPi : ARM::t2SUBri); > + BaseOpc = !isThumb2 ? ARM::SUBri : ARM::t2SUBri; > Offset = - Offset; > } > int ImmedOffset = isThumb2 > @@ -516,8 +512,6 @@ > if (!MI) > return false; > if (MI->getOpcode() != ARM::t2SUBri && > - MI->getOpcode() != ARM::t2SUBrSPi && > - MI->getOpcode() != ARM::t2SUBrSPi12 && > MI->getOpcode() != ARM::tSUBspi && > MI->getOpcode() != ARM::SUBri) > return false; > @@ -541,8 +535,6 @@ > if (!MI) > return false; > if (MI->getOpcode() != ARM::t2ADDri && > - MI->getOpcode() != ARM::t2ADDrSPi && > - MI->getOpcode() != ARM::t2ADDrSPi12 && > MI->getOpcode() != ARM::tADDspi && > MI->getOpcode() != ARM::ADDri) > return false; > > Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=134114&r1=134113&r2=134114&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original) > +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Wed Jun 29 18:25:04 2011 > @@ -251,7 +251,7 @@ > } > > // sub rd, sp, so_imm > - Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi; > + Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; > if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { > NumBytes = 0; > } else { > @@ -425,9 +425,9 @@ > if (Offset < 0) { > Offset = -Offset; > isSub = true; > - MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri)); > + MI.setDesc(TII.get(ARM::t2SUBri)); > } else { > - MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri)); > + MI.setDesc(TII.get(ARM::t2ADDri)); > } > > // Common case: small offset, fits into instruction. > @@ -443,9 +443,7 @@ > // Another common case: imm12. > if (Offset < 4096 && > (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) { > - unsigned NewOpc = isSP > - ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12) > - : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12); > + unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; > MI.setDesc(TII.get(NewOpc)); > MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); > MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); > > Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134114&r1=134113&r2=134114&view=diff > ============================================================================== > --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original) > +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Wed Jun 29 18:25:04 2011 > @@ -57,10 +57,8 @@ > static const ReduceEntry ReduceTable[] = { > // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, PF, S > { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0 }, > - { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,0 }, > + { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1 }, > { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0 }, > - // Note: immediate scale is 4. > - { ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 0,1 }, > { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1 }, > { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1 }, > { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0 }, > @@ -291,7 +289,7 @@ > Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD || > Opc == ARM::t2LDMDB_UPD); > bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD); > - bool isSPOk = isPCOk || isLROk || (Opc == ARM::t2ADDrSPi); > + bool isSPOk = isPCOk || isLROk; > for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { > const MachineOperand &MO = MI->getOperand(i); > if (!MO.isReg() || MO.isImplicit()) > @@ -481,6 +479,44 @@ > Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, > const ReduceEntry &Entry, > bool LiveCPSR, MachineInstr *CPSRDef) { > + unsigned Opc = MI->getOpcode(); > + if (Opc == ARM::t2ADDri) { > + // If the source register is SP, try to reduce to tADDrSPi, otherwise > + // it's a normal reduce. > + if (MI->getOperand(1).getReg() != ARM::SP) { > + if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef)) > + return true; > + return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); > + } > + // Try to reduce to tADDrSPi. > + unsigned Imm = MI->getOperand(2).getImm(); > + // The immediate must be in range, the destination register must be a low > + // reg, and the condition flags must not be being set. > + if (Imm & 3 || Imm > 1024) > + return false; > + if (!isARMLowRegister(MI->getOperand(0).getReg())) > + return false; > + const MCInstrDesc &MCID = MI->getDesc(); > + if (MCID.hasOptionalDef() && > + MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) > + return false; > + > + MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), > + TII->get(ARM::tADDrSPi)) > + .addOperand(MI->getOperand(0)) > + .addOperand(MI->getOperand(1)) > + .addImm(Imm / 4); // The tADDrSPi has an implied scale by four. > + > + // Transfer MI flags. > + MIB.setMIFlags(MI->getFlags()); > + > + DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB); > + > + MBB.erase(MI); > + ++NumNarrows; > + return true; > + } > + > if (Entry.LowRegs1 && !VerifyLowRegs(MI)) > return false; > > @@ -488,7 +524,6 @@ > if (MCID.mayLoad() || MCID.mayStore()) > return ReduceLoadStore(MBB, MI, Entry); > > - unsigned Opc = MI->getOpcode(); > switch (Opc) { > default: break; > case ARM::t2ADDSri: > @@ -531,13 +566,6 @@ > return true; > return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); > } > - case ARM::t2ADDrSPi: { > - static const ReduceEntry NarrowEntry = > - { ARM::t2ADDrSPi,ARM::tADDspi, 0, 7, 0, 1, 0, 1, 0, 0,1 }; > - if (MI->getOperand(0).getReg() == ARM::SP) > - return ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef); > - return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); > - } > } > return false; > } > @@ -645,9 +673,8 @@ > return false; > > unsigned Limit = ~0U; > - unsigned Scale = (Entry.WideOpc == ARM::t2ADDrSPi) ? 4 : 1; > if (Entry.Imm1Limit) > - Limit = ((1 << Entry.Imm1Limit) - 1) * Scale; > + Limit = (1 << Entry.Imm1Limit) - 1; > > const MCInstrDesc &MCID = MI->getDesc(); > for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { > @@ -658,13 +685,11 @@ > unsigned Reg = MO.getReg(); > if (!Reg || Reg == ARM::CPSR) > continue; > - if (Entry.WideOpc == ARM::t2ADDrSPi && Reg == ARM::SP) > - continue; > if (Entry.LowRegs1 && !isARMLowRegister(Reg)) > return false; > } else if (MO.isImm() && > !MCID.OpInfo[i].isPredicate()) { > - if (((unsigned)MO.getImm()) > Limit || (MO.getImm() & (Scale-1)) != 0) > + if (((unsigned)MO.getImm()) > Limit) > return false; > } > } > @@ -723,15 +748,11 @@ > if (SkipPred && isPred) > continue; > const MachineOperand &MO = MI->getOperand(i); > - if (Scale > 1 && !isPred && MO.isImm()) > - MIB.addImm(MO.getImm() / Scale); > - else { > - if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) > - // Skip implicit def of CPSR. Either it's modeled as an optional > - // def now or it's already an implicit def on the new instruction. > - continue; > - MIB.addOperand(MO); > - } > + if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) > + // Skip implicit def of CPSR. Either it's modeled as an optional > + // def now or it's already an implicit def on the new instruction. > + continue; > + MIB.addOperand(MO); > } > if (!MCID.isPredicable() && NewMCID.isPredicable()) > AddDefaultPred(MIB); > > Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp > URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=134114&r1=134113&r2=134114&view=diff > ============================================================================== > --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original) > +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Wed Jun 29 18:25:04 2011 > @@ -1640,12 +1640,8 @@ > // Ignore tADDrSP, tADDspr, and tPICADD, prefer the generic tADDhirr. > // Ignore t2SUBrSPs, prefer the t2SUB[S]r[r|s]. > // Ignore t2ADDrSPs, prefer the t2ADD[S]r[r|s]. > - // Ignore t2ADDrSPi/t2SUBrSPi, which have more generic couterparts. > - // Ignore t2ADDrSPi12/t2SUBrSPi12, which have more generic couterparts > if (Name == "tADDrSP" || Name == "tADDspr" || Name == "tPICADD" || > - Name == "t2SUBrSPs" || Name == "t2ADDrSPs" || > - Name == "t2ADDrSPi" || Name == "t2SUBrSPi" || > - Name == "t2ADDrSPi12" || Name == "t2SUBrSPi12") > + Name == "t2SUBrSPs" || Name == "t2ADDrSPs") > return false; > > // FIXME: Use ldr.n to work around a Darwin assembler bug. > > > _______________________________________________ > llvm-commits mailing list > llvm-commits at cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits From evan.cheng at apple.com Wed Jun 29 20:53:37 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 30 Jun 2011 01:53:37 -0000 Subject: [llvm-commits] [llvm] r134127 - in /llvm/trunk: include/llvm/MC/ include/llvm/Target/ lib/ExecutionEngine/ lib/MC/ lib/MC/MCDisassembler/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ tools/llc/ tools/llvm-mc/ tools/llvm-objdump/ too... Message-ID: <20110630015338.338512A6C12C@llvm.org> Author: evancheng Date: Wed Jun 29 20:53:36 2011 New Revision: 134127 URL: http://llvm.org/viewvc/llvm-project?rev=134127&view=rev Log: Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! Modified: llvm/trunk/include/llvm/MC/SubtargetFeature.h llvm/trunk/include/llvm/Target/TargetRegistry.h llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp llvm/trunk/lib/MC/SubtargetFeature.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp llvm/trunk/lib/Target/ARM/ARMSubtarget.h llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp llvm/trunk/lib/Target/ARM/ARMTargetMachine.h llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h llvm/trunk/lib/Target/CBackend/CTargetMachine.h llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp llvm/trunk/lib/Target/Mips/MipsSubtarget.h llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp llvm/trunk/lib/Target/Mips/MipsTargetMachine.h llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp llvm/trunk/lib/Target/PTX/PTXSubtarget.h llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp llvm/trunk/lib/Target/PTX/PTXTargetMachine.h llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp llvm/trunk/lib/Target/Sparc/SparcSubtarget.h llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h llvm/trunk/lib/Target/X86/X86Subtarget.cpp llvm/trunk/lib/Target/X86/X86Subtarget.h llvm/trunk/lib/Target/X86/X86TargetMachine.cpp llvm/trunk/lib/Target/X86/X86TargetMachine.h llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp llvm/trunk/lib/Target/XCore/XCoreSubtarget.h llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h llvm/trunk/tools/llc/llc.cpp llvm/trunk/tools/llvm-mc/llvm-mc.cpp llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp llvm/trunk/tools/lto/LTOCodeGenerator.cpp llvm/trunk/tools/lto/LTOModule.cpp llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Modified: llvm/trunk/include/llvm/MC/SubtargetFeature.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/SubtargetFeature.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/include/llvm/MC/SubtargetFeature.h (original) +++ llvm/trunk/include/llvm/MC/SubtargetFeature.h Wed Jun 29 20:53:36 2011 @@ -80,26 +80,19 @@ std::string getString() const; void setString(const std::string &Initial); - /// Set the CPU string. Replaces previous setting. Setting to "" clears CPU. - void setCPU(const std::string &String); - - /// Setting CPU string only if no string is set. - void setCPUIfNone(const std::string &String); - - /// Returns current CPU string. - const std::string & getCPU() const; - /// Adding Features. void AddFeature(const std::string &String, bool IsEnabled = true); - /// Get feature bits. - uint64_t getBits(const SubtargetFeatureKV *CPUTable, - size_t CPUTableSize, - const SubtargetFeatureKV *FeatureTable, - size_t FeatureTableSize); + /// Get feature bits of a CPU. + uint64_t getFeatureBits(const std::string &CPU, + const SubtargetFeatureKV *CPUTable, + size_t CPUTableSize, + const SubtargetFeatureKV *FeatureTable, + size_t FeatureTableSize); - /// Get info pointer - void *getInfo(const SubtargetInfoKV *Table, size_t TableSize); + /// Get scheduling itinerary of a CPU. + void *getItinerary(const std::string &CPU, + const SubtargetInfoKV *Table, size_t TableSize); /// Print feature string. void print(raw_ostream &OS) const; @@ -109,8 +102,7 @@ /// Retrieve a formatted string of the default features for the specified /// target triple. - void getDefaultSubtargetFeatures(const std::string &CPU, - const Triple& Triple); + void getDefaultSubtargetFeatures(const Triple& Triple); }; } // End namespace llvm Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/include/llvm/Target/TargetRegistry.h (original) +++ llvm/trunk/include/llvm/Target/TargetRegistry.h Wed Jun 29 20:53:36 2011 @@ -71,6 +71,7 @@ typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void); typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &Features); typedef AsmPrinter *(*AsmPrinterCtorTy)(TargetMachine &TM, MCStreamer &Streamer); @@ -269,10 +270,11 @@ /// either the target triple from the module, or the target triple of the /// host if that does not exist. TargetMachine *createTargetMachine(const std::string &Triple, + const std::string &CPU, const std::string &Features) const { if (!TargetMachineCtorFn) return 0; - return TargetMachineCtorFn(*this, Triple, Features); + return TargetMachineCtorFn(*this, Triple, CPU, Features); } /// createAsmBackend - Create a target specific assembly parser. @@ -796,8 +798,9 @@ private: static TargetMachine *Allocator(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) { - return new TargetMachineImpl(T, TT, FS); + return new TargetMachineImpl(T, TT, CPU, FS); } }; Modified: llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp (original) +++ llvm/trunk/lib/ExecutionEngine/TargetSelect.cpp Wed Jun 29 20:53:36 2011 @@ -75,9 +75,8 @@ // Package up features to be passed to target/subtarget std::string FeaturesStr; - if (!MCPU.empty() || !MAttrs.empty()) { + if (!MAttrs.empty()) { SubtargetFeatures Features; - Features.setCPU(MCPU); for (unsigned i = 0; i != MAttrs.size(); ++i) Features.AddFeature(MAttrs[i]); FeaturesStr = Features.getString(); @@ -85,7 +84,7 @@ // Allocate a target... TargetMachine *Target = - TheTarget->createTargetMachine(TheTriple.getTriple(), FeaturesStr); + TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, FeaturesStr); assert(Target && "Could not allocate target machine!"); return Target; } Modified: llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/Disassembler.cpp Wed Jun 29 20:53:36 2011 @@ -55,11 +55,13 @@ // Package up features to be passed to target/subtarget std::string FeaturesStr; + std::string CPU; // FIXME: We shouldn't need to do this (and link in codegen). // When we split this out, we should do it in a way that makes // it straightforward to switch subtargets on the fly. - TargetMachine *TM = TheTarget->createTargetMachine(TripleName, FeaturesStr); + TargetMachine *TM = TheTarget->createTargetMachine(TripleName, CPU, + FeaturesStr); assert(TM && "Unable to create target machine!"); // Get the target assembler info needed to setup the context. Modified: llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp (original) +++ llvm/trunk/lib/MC/MCDisassembler/EDDisassembler.cpp Wed Jun 29 20:53:36 2011 @@ -167,9 +167,9 @@ if (!Tgt) return; + std::string CPU; std::string featureString; - - TargetMachine.reset(Tgt->createTargetMachine(tripleString, + TargetMachine.reset(Tgt->createTargetMachine(tripleString, CPU, featureString)); const TargetRegisterInfo *registerInfo = TargetMachine->getRegisterInfo(); Modified: llvm/trunk/lib/MC/SubtargetFeature.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/SubtargetFeature.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/MC/SubtargetFeature.cpp (original) +++ llvm/trunk/lib/MC/SubtargetFeature.cpp Wed Jun 29 20:53:36 2011 @@ -63,6 +63,9 @@ /// Split - Splits a string of comma separated items in to a vector of strings. /// static void Split(std::vector &V, const std::string &S) { + if (S.empty()) + return; + // Start at beginning of string. size_t Pos = 0; while (true) { @@ -88,7 +91,7 @@ std::string Result; // If the vector is not empty if (!V.empty()) { - // Start with the CPU feature + // Start with the first feature Result = V[0]; // For each successive feature for (size_t i = 1; i < V.size(); i++) { @@ -186,27 +189,6 @@ Split(Features, LowercaseString(Initial)); } - -/// setCPU - Set the CPU string. Replaces previous setting. Setting to "" -/// clears CPU. -void SubtargetFeatures::setCPU(const std::string &String) { - Features[0] = LowercaseString(String); -} - - -/// setCPUIfNone - Setting CPU string only if no string is set. -/// -void SubtargetFeatures::setCPUIfNone(const std::string &String) { - if (Features[0].empty()) setCPU(String); -} - -/// getCPU - Returns current CPU. -/// -const std::string & SubtargetFeatures::getCPU() const { - return Features[0]; -} - - /// SetImpliedBits - For each feature that is (transitively) implied by this /// feature, set it. /// @@ -245,12 +227,13 @@ } } -/// getBits - Get feature bits. +/// getFeatureBits - Get feature bits a CPU. /// -uint64_t SubtargetFeatures::getBits(const SubtargetFeatureKV *CPUTable, - size_t CPUTableSize, - const SubtargetFeatureKV *FeatureTable, - size_t FeatureTableSize) { +uint64_t SubtargetFeatures::getFeatureBits(const std::string &CPU, + const SubtargetFeatureKV *CPUTable, + size_t CPUTableSize, + const SubtargetFeatureKV *FeatureTable, + size_t FeatureTableSize) { assert(CPUTable && "missing CPU table"); assert(FeatureTable && "missing features table"); #ifndef NDEBUG @@ -266,12 +249,11 @@ uint64_t Bits = 0; // Resulting bits // Check if help is needed - if (Features[0] == "help") + if (CPU == "help") Help(CPUTable, CPUTableSize, FeatureTable, FeatureTableSize); // Find CPU entry - const SubtargetFeatureKV *CPUEntry = - Find(Features[0], CPUTable, CPUTableSize); + const SubtargetFeatureKV *CPUEntry = Find(CPU, CPUTable, CPUTableSize); // If there is a match if (CPUEntry) { // Set base feature bits @@ -284,12 +266,12 @@ SetImpliedBits(Bits, &FE, FeatureTable, FeatureTableSize); } } else { - errs() << "'" << Features[0] + errs() << "'" << CPU << "' is not a recognized processor for this target" << " (ignoring processor)\n"; } // Iterate through each feature - for (size_t i = 1; i < Features.size(); i++) { + for (size_t i = 0, E = Features.size(); i < E; i++) { const std::string &Feature = Features[i]; // Check for help @@ -323,9 +305,10 @@ return Bits; } -/// Get info pointer -void *SubtargetFeatures::getInfo(const SubtargetInfoKV *Table, - size_t TableSize) { +/// Get scheduling itinerary of a CPU. +void *SubtargetFeatures::getItinerary(const std::string &CPU, + const SubtargetInfoKV *Table, + size_t TableSize) { assert(Table && "missing table"); #ifndef NDEBUG for (size_t i = 1; i < TableSize; i++) { @@ -334,12 +317,12 @@ #endif // Find entry - const SubtargetInfoKV *Entry = Find(Features[0], Table, TableSize); + const SubtargetInfoKV *Entry = Find(CPU, Table, TableSize); if (Entry) { return Entry->Value; } else { - errs() << "'" << Features[0] + errs() << "'" << CPU << "' is not a recognized processor for this target" << " (ignoring processor)\n"; return NULL; @@ -367,10 +350,7 @@ /// subtarget. It would be better if we could encode this information /// into the IR. See . /// -void SubtargetFeatures::getDefaultSubtargetFeatures(const std::string &CPU, - const Triple& Triple) { - setCPU(CPU); - +void SubtargetFeatures::getDefaultSubtargetFeatures(const Triple& Triple) { if (Triple.getVendor() == Triple::Apple) { if (Triple.getArch() == Triple::ppc) { // powerpc-apple-* Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Jun 29 20:53:36 2011 @@ -30,8 +30,8 @@ StrictAlign("arm-strict-align", cl::Hidden, cl::desc("Disallow all unaligned memory accesses")); -ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &FS, - bool isT) +ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool isT) : ARMArchVersion(V4) , ARMProcFamily(Others) , ARMFPUType(None) @@ -56,7 +56,7 @@ , FPOnlySP(false) , AllowsUnalignedMem(false) , stackAlignment(4) - , CPUString("generic") + , CPUString(CPU) , TargetTriple(TT) , TargetABI(ARM_ABI_APCS) { // Determine default and user specified characteristics @@ -64,9 +64,11 @@ // When no arch is specified either by CPU or by attributes, make the default // ARMv4T. const char *ARMArchFeature = ""; + if (CPUString.empty()) + CPUString = "generic"; if (CPUString == "generic" && (FS.empty() || FS == "generic")) { ARMArchVersion = V4T; - ARMArchFeature = ",+v4t"; + ARMArchFeature = "+v4t"; } // Set the boolean corresponding to the current target triple, or the default @@ -85,29 +87,29 @@ unsigned SubVer = TT[Idx]; if (SubVer >= '7' && SubVer <= '9') { ARMArchVersion = V7A; - ARMArchFeature = ",+v7a"; + ARMArchFeature = "+v7a"; if (Len >= Idx+2 && TT[Idx+1] == 'm') { ARMArchVersion = V7M; - ARMArchFeature = ",+v7m"; + ARMArchFeature = "+v7m"; } } else if (SubVer == '6') { ARMArchVersion = V6; - ARMArchFeature = ",+v6"; + ARMArchFeature = "+v6"; if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == '2') { ARMArchVersion = V6T2; - ARMArchFeature = ",+v6t2"; + ARMArchFeature = "+v6t2"; } } else if (SubVer == '5') { ARMArchVersion = V5T; - ARMArchFeature = ",+v5t"; + ARMArchFeature = "+v5t"; if (Len >= Idx+3 && TT[Idx+1] == 't' && TT[Idx+2] == 'e') { ARMArchVersion = V5TE; - ARMArchFeature = ",+v5te"; + ARMArchFeature = "+v5te"; } } else if (SubVer == '4') { if (Len >= Idx+2 && TT[Idx+1] == 't') { ARMArchVersion = V4T; - ARMArchFeature = ",+v4t"; + ARMArchFeature = "+v4t"; } else { ARMArchVersion = V4; ARMArchFeature = ""; @@ -129,7 +131,7 @@ FSWithArch = std::string(ARMArchFeature) + FS; else FSWithArch = FS; - CPUString = ParseSubtargetFeatures(FSWithArch, CPUString); + ParseSubtargetFeatures(FSWithArch, CPUString); // After parsing Itineraries, set ItinData.IssueWidth. computeIssueWidth(); Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Wed Jun 29 20:53:36 2011 @@ -153,7 +153,8 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb); + ARMSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool isThumb); /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size /// that still makes it profitable to inline the call. @@ -164,8 +165,7 @@ } /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); void computeIssueWidth(); Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -78,10 +78,11 @@ /// ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS, bool isThumb) : LLVMTargetMachine(T, TT), - Subtarget(TT, FS, isThumb), + Subtarget(TT, CPU, FS, isThumb), JITInfo(), InstrItins(Subtarget.getInstrItineraryData()) { DefRelocModel = getRelocationModel(); @@ -92,8 +93,9 @@ } ARMTargetMachine::ARMTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) - : ARMBaseTargetMachine(T, TT, FS, false), InstrInfo(Subtarget), + : ARMBaseTargetMachine(T, TT, CPU, FS, false), InstrInfo(Subtarget), DataLayout(Subtarget.isAPCS_ABI() ? std::string("e-p:32:32-f64:32:64-i64:32:64-" "v128:32:128-v64:32:64-n32") : @@ -109,8 +111,9 @@ } ThumbTargetMachine::ThumbTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) - : ARMBaseTargetMachine(T, TT, FS, true), + : ARMBaseTargetMachine(T, TT, CPU, FS, true), InstrInfo(Subtarget.hasThumb2() ? ((ARMBaseInstrInfo*)new Thumb2InstrInfo(Subtarget)) : ((ARMBaseInstrInfo*)new Thumb1InstrInfo(Subtarget))), Modified: llvm/trunk/lib/Target/ARM/ARMTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMTargetMachine.h (original) +++ llvm/trunk/lib/Target/ARM/ARMTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -41,7 +41,8 @@ public: ARMBaseTargetMachine(const Target &T, const std::string &TT, - const std::string &FS, bool isThumb); + const std::string &CPU, const std::string &FS, + bool isThumb); virtual ARMJITInfo *getJITInfo() { return &JITInfo; } virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; } @@ -70,7 +71,7 @@ ARMFrameLowering FrameLowering; public: ARMTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); virtual const ARMRegisterInfo *getRegisterInfo() const { return &InstrInfo.getRegisterInfo(); @@ -109,7 +110,7 @@ OwningPtr FrameLowering; public: ThumbTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo virtual const ARMBaseRegisterInfo *getRegisterInfo() const { Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp (original) +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmLexer.cpp Wed Jun 29 20:53:36 2011 @@ -87,8 +87,9 @@ : ARMBaseAsmLexer(T, MAI) { std::string tripleString("arm-unknown-unknown"); std::string featureString; + std::string CPU; OwningPtr - targetMachine(T.createTargetMachine(tripleString, featureString)); + targetMachine(T.createTargetMachine(tripleString, CPU, featureString)); InitRegisterMap(targetMachine->getRegisterInfo()); } }; @@ -99,8 +100,9 @@ : ARMBaseAsmLexer(T, MAI) { std::string tripleString("thumb-unknown-unknown"); std::string featureString; + std::string CPU; OwningPtr - targetMachine(T.createTargetMachine(tripleString, featureString)); + targetMachine(T.createTargetMachine(tripleString, CPU, featureString)); InitRegisterMap(targetMachine->getRegisterInfo()); } }; Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Wed Jun 29 20:53:36 2011 @@ -16,10 +16,13 @@ #include "AlphaGenSubtarget.inc" using namespace llvm; -AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &FS) +AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS) : HasCT(false) { - std::string CPU = "generic"; + std::string CPUName = CPU; + if (CPUName.empty()) + CPUName = "generic"; // Parse features string. - ParseSubtargetFeatures(FS, CPU); + ParseSubtargetFeatures(FS, CPUName); } Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h Wed Jun 29 20:53:36 2011 @@ -31,12 +31,12 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - AlphaSubtarget(const std::string &TT, const std::string &FS); + AlphaSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); bool hasCT() const { return HasCT; } }; Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -25,11 +25,12 @@ } AlphaTargetMachine::AlphaTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) : LLVMTargetMachine(T, TT), DataLayout("e-f128:128:128-n64"), FrameLowering(Subtarget), - Subtarget(TT, FS), + Subtarget(TT, CPU, FS), TLInfo(*this), TSInfo(*this) { setRelocationModel(Reloc::PIC_); Modified: llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h (original) +++ llvm/trunk/lib/Target/Alpha/AlphaTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -37,7 +37,7 @@ public: AlphaTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); virtual const AlphaInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Wed Jun 29 20:53:36 2011 @@ -17,6 +17,7 @@ using namespace llvm; BlackfinSubtarget::BlackfinSubtarget(const std::string &TT, + const std::string &CPU, const std::string &FS) : sdram(false), icplb(false), @@ -30,7 +31,9 @@ wa_killed_mmr(false), wa_rets(false) { - std::string CPU = "generic"; + std::string CPUName = CPU; + if (CPUName.empty()) + CPUName = "generic"; // Parse features string. - ParseSubtargetFeatures(FS, CPU); + ParseSubtargetFeatures(FS, CPUName); } Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h Wed Jun 29 20:53:36 2011 @@ -32,11 +32,12 @@ bool wa_killed_mmr; bool wa_rets; public: - BlackfinSubtarget(const std::string &TT, const std::string &FS); + BlackfinSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); }; Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -26,10 +26,11 @@ BlackfinTargetMachine::BlackfinTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) : LLVMTargetMachine(T, TT), DataLayout("e-p:32:32-i64:32-f64:32-n32"), - Subtarget(TT, FS), + Subtarget(TT, CPU, FS), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), Modified: llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h (original) +++ llvm/trunk/lib/Target/Blackfin/BlackfinTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -36,7 +36,7 @@ BlackfinIntrinsicInfo IntrinsicInfo; public: BlackfinTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); virtual const BlackfinInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { Modified: llvm/trunk/lib/Target/CBackend/CTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CBackend/CTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/CBackend/CTargetMachine.h (original) +++ llvm/trunk/lib/Target/CBackend/CTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -20,7 +20,8 @@ namespace llvm { struct CTargetMachine : public TargetMachine { - CTargetMachine(const Target &T, const std::string &TT, const std::string &FS) + CTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) : TargetMachine(T) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Wed Jun 29 20:53:36 2011 @@ -19,7 +19,8 @@ using namespace llvm; -SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &FS) : +SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS) : StackAlignment(16), ProcDirective(SPU::DEFAULT_PROC), UseLargeMem(false) Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h Wed Jun 29 20:53:36 2011 @@ -49,12 +49,12 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - SPUSubtarget(const std::string &TT, const std::string &FS); + SPUSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); /// SetJITMode - This is called to inform the subtarget info that we are /// producing code for the JIT. Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -35,9 +35,9 @@ } SPUTargetMachine::SPUTargetMachine(const Target &T, const std::string &TT, - const std::string &FS) + const std::string &CPU,const std::string &FS) : LLVMTargetMachine(T, TT), - Subtarget(TT, FS), + Subtarget(TT, CPU, FS), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), FrameLowering(Subtarget), Modified: llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h (original) +++ llvm/trunk/lib/Target/CellSPU/SPUTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -39,7 +39,7 @@ InstrItineraryData InstrItins; public: SPUTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); /// Return the subtarget implementation object virtual const SPUSubtarget *getSubtargetImpl() const { Modified: llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h (original) +++ llvm/trunk/lib/Target/CppBackend/CPPTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -23,7 +23,7 @@ struct CPPTargetMachine : public TargetMachine { CPPTargetMachine(const Target &T, const std::string &TT, - const std::string &FS) + const std::string &CPU, const std::string &FS) : TargetMachine(T) {} virtual bool addPassesToEmitFile(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/AsmParser/MBlazeAsmLexer.cpp Wed Jun 29 20:53:36 2011 @@ -86,8 +86,9 @@ : MBlazeBaseAsmLexer(T, MAI) { std::string tripleString("mblaze-unknown-unknown"); std::string featureString; + std::string CPU; OwningPtr - targetMachine(T.createTargetMachine(tripleString, featureString)); + targetMachine(T.createTargetMachine(tripleString, CPU, featureString)); InitRegisterMap(targetMachine->getRegisterInfo()); } }; Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Wed Jun 29 20:53:36 2011 @@ -18,18 +18,22 @@ #include "llvm/Support/CommandLine.h" using namespace llvm; -MBlazeSubtarget::MBlazeSubtarget(const std::string &TT, const std::string &FS): +MBlazeSubtarget::MBlazeSubtarget(const std::string &TT, + const std::string &CPU, + const std::string &FS): HasBarrel(false), HasDiv(false), HasMul(false), HasPatCmp(false), HasFPU(false), HasMul64(false), HasSqrt(false) { // Parse features string. - std::string CPU = "mblaze"; - CPU = ParseSubtargetFeatures(FS, CPU); + std::string CPUName = CPU; + if (CPUName.empty()) + CPUName = "mblaze"; + ParseSubtargetFeatures(FS, CPUName); // Only use instruction scheduling if the selected CPU has an instruction // itinerary (the default CPU is the only one that doesn't). - HasItin = CPU != "mblaze"; - DEBUG(dbgs() << "CPU " << CPU << "(" << HasItin << ")\n"); + HasItin = CPUName != "mblaze"; + DEBUG(dbgs() << "CPU " << CPUName << "(" << HasItin << ")\n"); // Compute the issue width of the MBlaze itineraries computeIssueWidth(); Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h Wed Jun 29 20:53:36 2011 @@ -38,12 +38,12 @@ /// This constructor initializes the data members to match that /// of the specified triple. - MBlazeSubtarget(const std::string &TT, const std::string &FS); + MBlazeSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); /// Compute the number of maximum number of issues per cycle for the /// MBlaze scheduling itineraries. Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -80,9 +80,9 @@ // an easier handling. MBlazeTargetMachine:: MBlazeTargetMachine(const Target &T, const std::string &TT, - const std::string &FS): + const std::string &CPU, const std::string &FS): LLVMTargetMachine(T, TT), - Subtarget(TT, FS), + Subtarget(TT, CPU, FS), DataLayout("E-p:32:32:32-i8:8:8-i16:16:16"), InstrInfo(*this), FrameLowering(Subtarget), Modified: llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h (original) +++ llvm/trunk/lib/Target/MBlaze/MBlazeTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -42,7 +42,7 @@ public: MBlazeTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); virtual const MBlazeInstrInfo *getInstrInfo() const { return &InstrInfo; } Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Wed Jun 29 20:53:36 2011 @@ -17,7 +17,9 @@ using namespace llvm; -MSP430Subtarget::MSP430Subtarget(const std::string &TT, const std::string &FS) { +MSP430Subtarget::MSP430Subtarget(const std::string &TT, + const std::string &CPUIgnored, + const std::string &FS) { std::string CPU = "generic"; // Parse features string. Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h Wed Jun 29 20:53:36 2011 @@ -26,12 +26,12 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - MSP430Subtarget(const std::string &TT, const std::string &FS); + MSP430Subtarget(const std::string &TT, const std::string &CPU, + const std::string &FS); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); }; } // End llvm namespace Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -28,9 +28,10 @@ MSP430TargetMachine::MSP430TargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) : LLVMTargetMachine(T, TT), - Subtarget(TT, FS), + Subtarget(TT, CPU, FS), // FIXME: Check TargetData string. DataLayout("e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"), InstrInfo(*this), TLInfo(*this), TSInfo(*this), Modified: llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h (original) +++ llvm/trunk/lib/Target/MSP430/MSP430TargetMachine.h Wed Jun 29 20:53:36 2011 @@ -39,7 +39,7 @@ public: MSP430TargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); virtual const TargetFrameLowering *getFrameLowering() const { return &FrameLowering; Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Wed Jun 29 20:53:36 2011 @@ -16,18 +16,20 @@ #include "MipsGenSubtarget.inc" using namespace llvm; -MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &FS, - bool little) : +MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool little) : MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false), IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true), HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false), HasSwap(false), HasBitCount(false) { - std::string CPU = "mips1"; + std::string CPUName = CPU; + if (CPUName.empty()) + CPUName = "mips1"; MipsArchVersion = Mips1; // Parse features string. - ParseSubtargetFeatures(FS, CPU); + ParseSubtargetFeatures(FS, CPUName); // Is the target system Linux ? if (TT.find("linux") == std::string::npos) Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original) +++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Wed Jun 29 20:53:36 2011 @@ -91,12 +91,12 @@ /// This constructor initializes the data members to match that /// of the specified triple. - MipsSubtarget(const std::string &TT, const std::string &FS, bool little); + MipsSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool little); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); bool isMips1() const { return MipsArchVersion == Mips1; } bool isMips32() const { return MipsArchVersion >= Mips32; } Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -34,10 +34,11 @@ // an easier handling. // Using CodeModel::Large enables different CALL behavior. MipsTargetMachine:: -MipsTargetMachine(const Target &T, const std::string &TT, const std::string &FS, +MipsTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS, bool isLittle=false): LLVMTargetMachine(T, TT), - Subtarget(TT, FS, isLittle), + Subtarget(TT, CPU, FS, isLittle), DataLayout(isLittle ? std::string("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") : std::string("E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")), @@ -55,8 +56,8 @@ MipselTargetMachine:: MipselTargetMachine(const Target &T, const std::string &TT, - const std::string &FS) : - MipsTargetMachine(T, TT, FS, true) {} + const std::string &CPU, const std::string &FS) : + MipsTargetMachine(T, TT, CPU, FS, true) {} // Install an instruction selector pass using // the ISelDag to gen Mips code. Modified: llvm/trunk/lib/Target/Mips/MipsTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Mips/MipsTargetMachine.h (original) +++ llvm/trunk/lib/Target/Mips/MipsTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -35,7 +35,8 @@ MipsSelectionDAGInfo TSInfo; public: MipsTargetMachine(const Target &T, const std::string &TT, - const std::string &FS, bool isLittle); + const std::string &CPU, const std::string &FS, + bool isLittle); virtual const MipsInstrInfo *getInstrInfo() const { return &InstrInfo; } @@ -73,7 +74,7 @@ class MipselTargetMachine : public MipsTargetMachine { public: MipselTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); }; } // End llvm namespace Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Wed Jun 29 20:53:36 2011 @@ -16,14 +16,16 @@ using namespace llvm; -PTXSubtarget::PTXSubtarget(const std::string &TT, const std::string &FS, - bool is64Bit) +PTXSubtarget::PTXSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool is64Bit) : PTXTarget(PTX_COMPUTE_1_0), PTXVersion(PTX_VERSION_2_0), SupportsDouble(false), SupportsFMA(true), Is64Bit(is64Bit) { - std::string TARGET = "generic"; + std::string TARGET = CPU; + if (TARGET.empty()) + TARGET = "generic"; ParseSubtargetFeatures(FS, TARGET); } Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXSubtarget.h (original) +++ llvm/trunk/lib/Target/PTX/PTXSubtarget.h Wed Jun 29 20:53:36 2011 @@ -74,7 +74,8 @@ public: - PTXSubtarget(const std::string &TT, const std::string &FS, bool is64Bit); + PTXSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool is64Bit); // Target architecture accessors std::string getTargetString() const; @@ -108,8 +109,8 @@ (PTXTarget >= PTX_COMPUTE_2_0 && PTXTarget < PTX_LAST_COMPUTE); } - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, + const std::string &CPU); }; // class PTXSubtarget } // namespace llvm Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -52,11 +52,12 @@ // DataLayout and FrameLowering are filled with dummy data PTXTargetMachine::PTXTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS, bool is64Bit) : LLVMTargetMachine(T, TT), DataLayout(is64Bit ? DataLayout64 : DataLayout32), - Subtarget(TT, FS, is64Bit), + Subtarget(TT, CPU, FS, is64Bit), FrameLowering(Subtarget), InstrInfo(*this), TLInfo(*this) { @@ -64,14 +65,16 @@ PTX32TargetMachine::PTX32TargetMachine(const Target &T, const std::string& TT, + const std::string& CPU, const std::string& FS) - : PTXTargetMachine(T, TT, FS, false) { + : PTXTargetMachine(T, TT, CPU, FS, false) { } PTX64TargetMachine::PTX64TargetMachine(const Target &T, const std::string& TT, + const std::string& CPU, const std::string& FS) - : PTXTargetMachine(T, TT, FS, true) { + : PTXTargetMachine(T, TT, CPU, FS, true) { } bool PTXTargetMachine::addInstSelector(PassManagerBase &PM, Modified: llvm/trunk/lib/Target/PTX/PTXTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/PTX/PTXTargetMachine.h (original) +++ llvm/trunk/lib/Target/PTX/PTXTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -33,7 +33,8 @@ public: PTXTargetMachine(const Target &T, const std::string &TT, - const std::string &FS, bool is64Bit); + const std::string &CPU, const std::string &FS, + bool is64Bit); virtual const TargetData *getTargetData() const { return &DataLayout; } @@ -61,14 +62,14 @@ public: PTX32TargetMachine(const Target &T, const std::string &TT, - const std::string& FS); + const std::string& CPU, const std::string& FS); }; // class PTX32TargetMachine class PTX64TargetMachine : public PTXTargetMachine { public: PTX64TargetMachine(const Target &T, const std::string &TT, - const std::string& FS); + const std::string& CPU, const std::string& FS); }; // class PTX32TargetMachine } // namespace llvm Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Wed Jun 29 20:53:36 2011 @@ -57,8 +57,8 @@ #endif -PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &FS, - bool is64Bit) +PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool is64Bit) : StackAlignment(16) , DarwinDirective(PPC::DIR_NONE) , IsGigaProcessor(false) @@ -73,13 +73,16 @@ , TargetTriple(TT) { // Determine default and user specified characteristics - std::string CPU = "generic"; + std::string CPUName = CPU; + if (CPUName.empty()) + CPUName = "generic"; #if defined(__APPLE__) - CPU = GetCurrentPowerPCCPU(); + if (CPUName == "generic") + CPUName = GetCurrentPowerPCCPU(); #endif // Parse features string. - ParseSubtargetFeatures(FS, CPU); + ParseSubtargetFeatures(FS, CPUName); // If we are generating code for ppc64, verify that options make sense. if (is64Bit) { Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Wed Jun 29 20:53:36 2011 @@ -72,12 +72,12 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - PPCSubtarget(const std::string &TT, const std::string &FS, bool is64Bit); + PPCSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool is64Bit); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); /// SetJITMode - This is called to inform the subtarget info that we are Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -67,9 +67,10 @@ PPCTargetMachine::PPCTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS, bool is64Bit) : LLVMTargetMachine(T, TT), - Subtarget(TT, FS, is64Bit), + Subtarget(TT, CPU, FS, is64Bit), DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this), FrameLowering(Subtarget), JITInfo(*this, is64Bit), TLInfo(*this), TSInfo(*this), @@ -88,14 +89,16 @@ bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; } PPC32TargetMachine::PPC32TargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) - : PPCTargetMachine(T, TT, FS, false) { + : PPCTargetMachine(T, TT, CPU, FS, false) { } PPC64TargetMachine::PPC64TargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) - : PPCTargetMachine(T, TT, FS, true) { + : PPCTargetMachine(T, TT, CPU, FS, true) { } Modified: llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h (original) +++ llvm/trunk/lib/Target/PowerPC/PPCTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -41,7 +41,8 @@ public: PPCTargetMachine(const Target &T, const std::string &TT, - const std::string &FS, bool is64Bit); + const std::string &CPU, const std::string &FS, + bool is64Bit); virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const PPCFrameLowering *getFrameLowering() const { @@ -77,7 +78,7 @@ class PPC32TargetMachine : public PPCTargetMachine { public: PPC32TargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); }; /// PPC64TargetMachine - PowerPC 64-bit target machine. @@ -85,7 +86,7 @@ class PPC64TargetMachine : public PPCTargetMachine { public: PPC64TargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); }; } // end namespace llvm Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Wed Jun 29 20:53:36 2011 @@ -15,20 +15,23 @@ #include "SparcGenSubtarget.inc" using namespace llvm; -SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &FS, - bool is64Bit) : +SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool is64Bit) : IsV9(false), V8DeprecatedInsts(false), IsVIS(false), Is64Bit(is64Bit) { // Determine default and user specified characteristics - const char *CPU = "v8"; - if (is64Bit) { - CPU = "v9"; - IsV9 = true; + std::string CPUName = CPU; + if (CPUName.empty()) { + if (is64Bit) + CPUName = "v9"; + else + CPUName = "v8"; } + IsV9 = CPUName == "v9"; // Parse features string. - ParseSubtargetFeatures(FS, CPU); + ParseSubtargetFeatures(FS, CPUName); } Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcSubtarget.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.h Wed Jun 29 20:53:36 2011 @@ -26,7 +26,8 @@ bool Is64Bit; public: - SparcSubtarget(const std::string &TT, const std::string &FS, bool is64bit); + SparcSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool is64bit); bool isV9() const { return IsV9; } bool isVIS() const { return IsVIS; } @@ -34,8 +35,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); bool is64Bit() const { return Is64Bit; } std::string getDataLayout() const { Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -30,9 +30,10 @@ /// SparcTargetMachine ctor - Create an ILP32 architecture model /// SparcTargetMachine::SparcTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS, bool is64bit) : LLVMTargetMachine(T, TT), - Subtarget(TT, FS, is64bit), + Subtarget(TT, CPU, FS, is64bit), DataLayout(Subtarget.getDataLayout()), TLInfo(*this), TSInfo(*this), InstrInfo(Subtarget), FrameLowering(Subtarget) { @@ -56,12 +57,14 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) - : SparcTargetMachine(T, TT, FS, false) { + : SparcTargetMachine(T, TT, CPU, FS, false) { } SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) - : SparcTargetMachine(T, TT, FS, true) { + : SparcTargetMachine(T, TT, CPU, FS, true) { } Modified: llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h (original) +++ llvm/trunk/lib/Target/Sparc/SparcTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -34,7 +34,8 @@ SparcFrameLowering FrameLowering; public: SparcTargetMachine(const Target &T, const std::string &TT, - const std::string &FS, bool is64bit); + const std::string &CPU, const std::string &FS, + bool is64bit); virtual const SparcInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const TargetFrameLowering *getFrameLowering() const { @@ -62,7 +63,7 @@ class SparcV8TargetMachine : public SparcTargetMachine { public: SparcV8TargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); }; /// SparcV9TargetMachine - Sparc 64-bit target machine @@ -70,7 +71,7 @@ class SparcV9TargetMachine : public SparcTargetMachine { public: SparcV9TargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); }; } // end namespace llvm Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Wed Jun 29 20:53:36 2011 @@ -20,12 +20,15 @@ using namespace llvm; SystemZSubtarget::SystemZSubtarget(const std::string &TT, + const std::string &CPU, const std::string &FS): HasZ10Insts(false) { - std::string CPU = "z9"; + std::string CPUName = CPU; + if (CPUName.empty()) + CPUName = "z9"; // Parse features string. - ParseSubtargetFeatures(FS, CPU); + ParseSubtargetFeatures(FS, CPUName); } /// True if accessing the GV requires an extra load. Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h Wed Jun 29 20:53:36 2011 @@ -28,12 +28,12 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - SystemZSubtarget(const std::string &TT, const std::string &FS); + SystemZSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); bool isZ10() const { return HasZ10Insts; } Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -24,9 +24,10 @@ /// SystemZTargetMachine::SystemZTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) : LLVMTargetMachine(T, TT), - Subtarget(TT, FS), + Subtarget(TT, CPU, FS), DataLayout("E-p:64:64:64-i8:8:16-i16:16:16-i32:32:32-i64:64:64-f32:32:32" "-f64:64:64-f128:128:128-a0:16:16-n32:64"), InstrInfo(*this), TLInfo(*this), TSInfo(*this), Modified: llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h (original) +++ llvm/trunk/lib/Target/SystemZ/SystemZTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -38,7 +38,7 @@ SystemZFrameLowering FrameLowering; public: SystemZTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); virtual const TargetFrameLowering *getFrameLowering() const { return &FrameLowering; Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Wed Jun 29 20:53:36 2011 @@ -284,7 +284,8 @@ } } -X86Subtarget::X86Subtarget(const std::string &TT, const std::string &FS, +X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool is64Bit, unsigned StackAlignOverride) : PICStyle(PICStyles::None) , X86SSELevel(NoMMXSSE) @@ -308,10 +309,12 @@ , Is64Bit(is64Bit) { // Determine default and user specified characteristics - if (!FS.empty()) { + if (!CPU.empty() || !FS.empty()) { // If feature string is not empty, parse features string. - std::string CPU = sys::getHostCPUName(); - ParseSubtargetFeatures(FS, CPU); + std::string CPUName = CPU; + if (CPUName.empty()) + CPUName = sys::getHostCPUName(); + ParseSubtargetFeatures(FS, CPUName); // All X86-64 CPUs also have SSE2, however user might request no SSE via // -mattr, so don't force SSELevel here. if (HasAVX) Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86Subtarget.h (original) +++ llvm/trunk/lib/Target/X86/X86Subtarget.h Wed Jun 29 20:53:36 2011 @@ -117,7 +117,8 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - X86Subtarget(const std::string &TT, const std::string &FS, bool is64Bit, + X86Subtarget(const std::string &TT, const std::string &CPU, + const std::string &FS, bool is64Bit, unsigned StackAlignOverride); /// getStackAlignment - Returns the minimum alignment known to hold of the @@ -131,8 +132,7 @@ /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); /// AutoDetectSubtargetFeatures - Auto-detect CPU features using CPUID /// instruction. Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.cpp (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -87,8 +87,9 @@ X86_32TargetMachine::X86_32TargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) - : X86TargetMachine(T, TT, FS, false), + : X86TargetMachine(T, TT, CPU, FS, false), DataLayout(getSubtargetImpl()->isTargetDarwin() ? "e-p:32:32-f64:32:64-i64:32:64-f80:128:128-f128:128:128-n8:16:32" : (getSubtargetImpl()->isTargetCygMing() || @@ -103,8 +104,9 @@ X86_64TargetMachine::X86_64TargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) - : X86TargetMachine(T, TT, FS, true), + : X86TargetMachine(T, TT, CPU, FS, true), DataLayout("e-p:64:64-s:64-f64:64:64-i64:64:64-f80:128:128-f128:128:128-n8:16:32:64"), InstrInfo(*this), TSInfo(*this), @@ -115,9 +117,10 @@ /// X86TargetMachine ctor - Create an X86 target. /// X86TargetMachine::X86TargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS, bool is64Bit) : LLVMTargetMachine(T, TT), - Subtarget(TT, FS, is64Bit, StackAlignmentOverride), + Subtarget(TT, CPU, FS, is64Bit, StackAlignmentOverride), FrameLowering(*this, Subtarget), ELFWriterInfo(is64Bit, true) { DefRelocModel = getRelocationModel(); Modified: llvm/trunk/lib/Target/X86/X86TargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86TargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/X86/X86TargetMachine.h (original) +++ llvm/trunk/lib/Target/X86/X86TargetMachine.h Wed Jun 29 20:53:36 2011 @@ -43,7 +43,8 @@ public: X86TargetMachine(const Target &T, const std::string &TT, - const std::string &FS, bool is64Bit); + const std::string &CPU, const std::string &FS, + bool is64Bit); virtual const X86InstrInfo *getInstrInfo() const { llvm_unreachable("getInstrInfo not implemented"); @@ -87,7 +88,7 @@ X86JITInfo JITInfo; public: X86_32TargetMachine(const Target &T, const std::string &M, - const std::string &FS); + const std::string &CPU, const std::string &FS); virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; @@ -113,7 +114,7 @@ X86JITInfo JITInfo; public: X86_64TargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); virtual const TargetData *getTargetData() const { return &DataLayout; } virtual const X86TargetLowering *getTargetLowering() const { return &TLInfo; Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Wed Jun 29 20:53:36 2011 @@ -15,6 +15,7 @@ #include "XCore.h" using namespace llvm; -XCoreSubtarget::XCoreSubtarget(const std::string &TT, const std::string &FS) +XCoreSubtarget::XCoreSubtarget(const std::string &TT, + const std::string &CPU, const std::string &FS) { } Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreSubtarget.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.h Wed Jun 29 20:53:36 2011 @@ -27,12 +27,12 @@ /// This constructor initializes the data members to match that /// of the specified triple. /// - XCoreSubtarget(const std::string &TT, const std::string &FS); + XCoreSubtarget(const std::string &TT, const std::string &CPU, + const std::string &FS); /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. - std::string ParseSubtargetFeatures(const std::string &FS, - const std::string &CPU); + void ParseSubtargetFeatures(const std::string &FS, const std::string &CPU); }; } // End llvm namespace Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.cpp Wed Jun 29 20:53:36 2011 @@ -21,9 +21,10 @@ /// XCoreTargetMachine ctor - Create an ILP32 architecture model /// XCoreTargetMachine::XCoreTargetMachine(const Target &T, const std::string &TT, + const std::string &CPU, const std::string &FS) : LLVMTargetMachine(T, TT), - Subtarget(TT, FS), + Subtarget(TT, CPU, FS), DataLayout("e-p:32:32:32-a0:0:32-f32:32:32-f64:32:32-i1:8:32-i8:8:32-" "i16:16:32-i32:32:32-i64:32:32-n32"), InstrInfo(), Modified: llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h (original) +++ llvm/trunk/lib/Target/XCore/XCoreTargetMachine.h Wed Jun 29 20:53:36 2011 @@ -33,7 +33,7 @@ XCoreSelectionDAGInfo TSInfo; public: XCoreTargetMachine(const Target &T, const std::string &TT, - const std::string &FS); + const std::string &CPU, const std::string &FS); virtual const XCoreInstrInfo *getInstrInfo() const { return &InstrInfo; } virtual const XCoreFrameLowering *getFrameLowering() const { Modified: llvm/trunk/tools/llc/llc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llc/llc.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/tools/llc/llc.cpp (original) +++ llvm/trunk/tools/llc/llc.cpp Wed Jun 29 20:53:36 2011 @@ -261,16 +261,16 @@ // Package up features to be passed to target/subtarget std::string FeaturesStr; - if (MCPU.size() || MAttrs.size()) { + if (MAttrs.size()) { SubtargetFeatures Features; - Features.setCPU(MCPU); for (unsigned i = 0; i != MAttrs.size(); ++i) Features.AddFeature(MAttrs[i]); FeaturesStr = Features.getString(); } std::auto_ptr - target(TheTarget->createTargetMachine(TheTriple.getTriple(), FeaturesStr)); + target(TheTarget->createTargetMachine(TheTriple.getTriple(), MCPU, + FeaturesStr)); assert(target.get() && "Could not allocate target machine!"); TargetMachine &Target = *target.get(); Modified: llvm/trunk/tools/llvm-mc/llvm-mc.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mc/llvm-mc.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/tools/llvm-mc/llvm-mc.cpp (original) +++ llvm/trunk/tools/llvm-mc/llvm-mc.cpp Wed Jun 29 20:53:36 2011 @@ -309,17 +309,13 @@ // Package up features to be passed to target/subtarget std::string FeaturesStr; - if (MCPU.size()) { - SubtargetFeatures Features; - Features.setCPU(MCPU); - FeaturesStr = Features.getString(); - } // FIXME: We shouldn't need to do this (and link in codegen). // When we split this out, we should do it in a way that makes // it straightforward to switch subtargets on the fly (.e.g, // the .cpu and .code16 directives). OwningPtr TM(TheTarget->createTargetMachine(TripleName, + MCPU, FeaturesStr)); if (!TM) { @@ -415,17 +411,13 @@ } else { // Package up features to be passed to target/subtarget std::string FeaturesStr; - if (MCPU.size()) { - SubtargetFeatures Features; - Features.setCPU(MCPU); - FeaturesStr = Features.getString(); - } // FIXME: We shouldn't need to do this (and link in codegen). // When we split this out, we should do it in a way that makes // it straightforward to switch subtargets on the fly (.e.g, // the .cpu and .code16 directives). OwningPtr TM(TheTarget->createTargetMachine(TripleName, + MCPU, FeaturesStr)); if (!TM) { Modified: llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp (original) +++ llvm/trunk/tools/llvm-objdump/llvm-objdump.cpp Wed Jun 29 20:53:36 2011 @@ -201,7 +201,8 @@ // it straightforward to switch subtargets on the fly (.e.g, // the .cpu and .code16 directives). std::string FeaturesStr; - OwningPtr TM(TheTarget->createTargetMachine(TripleName, + std::string CPU; + OwningPtr TM(TheTarget->createTargetMachine(TripleName, CPU, FeaturesStr)); if (!TM) { errs() << "error: could not create target for triple " << TripleName << "\n"; Modified: llvm/trunk/tools/lto/LTOCodeGenerator.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOCodeGenerator.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOCodeGenerator.cpp (original) +++ llvm/trunk/tools/lto/LTOCodeGenerator.cpp Wed Jun 29 20:53:36 2011 @@ -262,9 +262,9 @@ // construct LTModule, hand over ownership of module and target SubtargetFeatures Features; - Features.getDefaultSubtargetFeatures(_mCpu, llvm::Triple(Triple)); + Features.getDefaultSubtargetFeatures(llvm::Triple(Triple)); std::string FeatureStr = Features.getString(); - _target = march->createTargetMachine(Triple, FeatureStr); + _target = march->createTargetMachine(Triple, _mCpu, FeatureStr); } return false; } Modified: llvm/trunk/tools/lto/LTOModule.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/lto/LTOModule.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/tools/lto/LTOModule.cpp (original) +++ llvm/trunk/tools/lto/LTOModule.cpp Wed Jun 29 20:53:36 2011 @@ -157,9 +157,10 @@ // construct LTOModule, hand over ownership of module and target SubtargetFeatures Features; - Features.getDefaultSubtargetFeatures("" /* cpu */, llvm::Triple(Triple)); + Features.getDefaultSubtargetFeatures(llvm::Triple(Triple)); std::string FeatureStr = Features.getString(); - TargetMachine *target = march->createTargetMachine(Triple, FeatureStr); + std::string CPU; + TargetMachine *target = march->createTargetMachine(Triple, CPU, FeatureStr); LTOModule *Ret = new LTOModule(m.take(), target); bool Err = Ret->ParseSymbols(); if (Err) { Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134127&r1=134126&r2=134127&view=diff ============================================================================== --- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original) +++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Wed Jun 29 20:53:36 2011 @@ -606,15 +606,15 @@ OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" << "// subtarget options.\n" - << "std::string llvm::"; + << "void llvm::"; OS << Target; OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n" << " const std::string &CPU) {\n" << " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n" << " DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n" << " SubtargetFeatures Features(FS);\n" - << " Features.setCPUIfNone(CPU);\n" - << " uint64_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n" + << " uint64_t Bits = Features.getFeatureBits(CPU, " + << "SubTypeKV, SubTypeKVSize,\n" << " FeatureKV, FeatureKVSize);\n"; for (unsigned i = 0; i < Features.size(); i++) { @@ -635,13 +635,13 @@ if (HasItineraries) { OS << "\n" << " InstrItinerary *Itinerary = (InstrItinerary *)" - << "Features.getInfo(ProcItinKV, ProcItinKVSize);\n" + << "Features.getItinerary(CPU, " + << "ProcItinKV, ProcItinKVSize);\n" << " InstrItins = InstrItineraryData(Stages, OperandCycles, " << "ForwardingPathes, Itinerary);\n"; } - OS << " return Features.getCPU();\n" - << "}\n"; + OS << "}\n"; } // From evan.cheng at apple.com Wed Jun 29 21:12:44 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 30 Jun 2011 02:12:44 -0000 Subject: [llvm-commits] [llvm] r134129 - /llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Message-ID: <20110630021244.7F6A62A6C12C@llvm.org> Author: evancheng Date: Wed Jun 29 21:12:44 2011 New Revision: 134129 URL: http://llvm.org/viewvc/llvm-project?rev=134129&view=rev Log: Fix ARMSubtarget feature parsing. Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134129&r1=134128&r2=134129&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original) +++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Wed Jun 29 21:12:44 2011 @@ -120,17 +120,14 @@ if (TT.find("eabi") != std::string::npos) TargetABI = ARM_ABI_AAPCS; - // Parse features string. If the first entry in FS (the CPU) is missing, - // insert the architecture feature derived from the target triple. This is - // important for setting features that are implied based on the architecture - // version. - std::string FSWithArch; - if (FS.empty()) - FSWithArch = std::string(ARMArchFeature); - else if (FS.find(',') == 0) - FSWithArch = std::string(ARMArchFeature) + FS; - else + // Insert the architecture feature derived from the target triple into the + // feature string. This is important for setting features that are implied + // based on the architecture version. + std::string FSWithArch = std::string(ARMArchFeature); + if (FSWithArch.empty()) FSWithArch = FS; + else if (!FS.empty()) + FSWithArch = FSWithArch + "," + FS; ParseSubtargetFeatures(FSWithArch, CPUString); // After parsing Itineraries, set ItinData.IssueWidth. From grosbach at apple.com Wed Jun 29 21:22:49 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 30 Jun 2011 02:22:49 -0000 Subject: [llvm-commits] [llvm] r134130 - /llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Message-ID: <20110630022249.76B8A2A6C12C@llvm.org> Author: grosbach Date: Wed Jun 29 21:22:49 2011 New Revision: 134130 URL: http://llvm.org/viewvc/llvm-project?rev=134130&view=rev Log: Size reducing SP adjusting t2ADDri needs to check predication. tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the predicate is anything other than "always." Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134130&r1=134129&r2=134130&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Wed Jun 29 21:22:49 2011 @@ -491,11 +491,14 @@ // Try to reduce to tADDrSPi. unsigned Imm = MI->getOperand(2).getImm(); // The immediate must be in range, the destination register must be a low - // reg, and the condition flags must not be being set. + // reg, the predicate must be "always" and the condition flags must not + // be being set. if (Imm & 3 || Imm > 1024) return false; if (!isARMLowRegister(MI->getOperand(0).getReg())) return false; + if (MI->getOperand(3).getImm() != ARMCC::AL) + return false; const MCInstrDesc &MCID = MI->getDesc(); if (MCID.hasOptionalDef() && MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) From grosbach at apple.com Wed Jun 29 21:23:05 2011 From: grosbach at apple.com (Jim Grosbach) Date: Thu, 30 Jun 2011 02:23:05 -0000 Subject: [llvm-commits] [llvm] r134131 - /llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Message-ID: <20110630022306.0671B2A6C12C@llvm.org> Author: grosbach Date: Wed Jun 29 21:23:05 2011 New Revision: 134131 URL: http://llvm.org/viewvc/llvm-project?rev=134131&view=rev Log: Kill dead code. Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=134131&r1=134130&r2=134131&view=diff ============================================================================== --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original) +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Wed Jun 29 21:23:05 2011 @@ -419,7 +419,6 @@ return true; } - bool isSP = FrameReg == ARM::SP; bool HasCCOut = Opcode != ARM::t2ADDri12; if (Offset < 0) { From grosbach at apple.com Wed Jun 29 21:23:59 2011 From: grosbach at apple.com (Jim Grosbach) Date: Wed, 29 Jun 2011 19:23:59 -0700 Subject: [llvm-commits] [llvm] r134114 - in /llvm/trunk: lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMBaseRegisterInfo.cpp lib/Target/ARM/ARMInstrThumb2.td lib/Target/ARM/ARMLoadStoreOptimizer.cpp lib/Target/ARM/Thumb2InstrInfo.cpp lib/Target/ARM/Thumb2SizeReduction.cpp utils/TableGen/ARMDecoderEmitter.cpp In-Reply-To: <89BB605A-2617-4146-B5DF-AEA59CCC1213@apple.com> References: <20110629232504.76FFD2A6C12C@llvm.org> <89BB605A-2617-4146-B5DF-AEA59CCC1213@apple.com> Message-ID: <701F3733-BB2A-4114-83B6-2FEDD79009F8@apple.com> Doh. Fixed in r134131. -j On Jun 29, 2011, at 6:49 PM, Evan Cheng wrote: > Thumb2InstrInfo.cpp:422:10: warning: unused variable 'isSP' [-Wunused-variable] > bool isSP = FrameReg == ARM::SP; > ^ > > On Jun 29, 2011, at 4:25 PM, Jim Grosbach wrote: > >> Author: grosbach >> Date: Wed Jun 29 18:25:04 2011 >> New Revision: 134114 >> >> URL: http://llvm.org/viewvc/llvm-project?rev=134114&view=rev >> Log: >> Remove redundant Thumb2 ADD/SUB SP instruction definitions. >> >> Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the >> stack pointer. It can just use the normal add-register-immediate encoding >> since it can use all registers as a source, not just R0-R7. The extra >> instruction definitions are just duplicates of the normal instructions with >> the (not well enforced) constraint that the source register was SP. >> >> >> Modified: >> llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp >> llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp >> llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td >> llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp >> llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp >> llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp >> llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp >> >> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134114&r1=134113&r2=134114&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Wed Jun 29 18:25:04 2011 >> @@ -1018,11 +1018,10 @@ >> Offset = -MI->getOperand(2).getImm(); >> break; >> case ARM::SUBri: >> - case ARM::t2SUBrSPi: >> - Offset = MI->getOperand(2).getImm(); >> + Offset = MI->getOperand(2).getImm(); >> break; >> case ARM::tSUBspi: >> - Offset = MI->getOperand(2).getImm()*4; >> + Offset = MI->getOperand(2).getImm()*4; >> break; >> case ARM::tADDspi: >> case ARM::tADDrSPi: >> @@ -1097,13 +1096,6 @@ >> OutStreamer.EmitInstruction(TmpInst); >> return; >> } >> - case ARM::t2ADDrSPi: >> - case ARM::t2ADDrSPi12: >> - case ARM::t2SUBrSPi: >> - case ARM::t2SUBrSPi12: >> - assert ((MI->getOperand(1).getReg() == ARM::SP) && >> - "Unexpected source register!"); >> - break; >> >> case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass"); >> case ARM::DBG_VALUE: { >> >> Modified: llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp?rev=134114&r1=134113&r2=134114&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMBaseRegisterInfo.cpp Wed Jun 29 18:25:04 2011 >> @@ -1284,9 +1284,5 @@ >> } >> // Update the original instruction to use the scratch register. >> MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true); >> - if (MI.getOpcode() == ARM::t2ADDrSPi) >> - MI.setDesc(TII.get(ARM::t2ADDri)); >> - else if (MI.getOpcode() == ARM::t2SUBrSPi) >> - MI.setDesc(TII.get(ARM::t2SUBri)); >> } >> } >> >> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=134114&r1=134113&r2=134114&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original) >> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Wed Jun 29 18:25:04 2011 >> @@ -1169,63 +1169,6 @@ >> []>; >> >> >> -// FIXME: None of these add/sub SP special instructions should be necessary >> -// at all for thumb2 since they use the same encodings as the generic >> -// add/sub instructions. In thumb1 we need them since they have dedicated >> -// encodings. At the least, they should be pseudo instructions. >> -// ADD r, sp, {so_imm|i12} >> -let isCodeGenOnly = 1 in { >> -def t2ADDrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), >> - IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> { >> - let Inst{31-27} = 0b11110; >> - let Inst{25} = 0; >> - let Inst{24-21} = 0b1000; >> - let Inst{15} = 0; >> -} >> -def t2ADDrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), >> - IIC_iALUi, "addw", "\t$Rd, $Rn, $imm", []> { >> - let Inst{31-27} = 0b11110; >> - let Inst{25-20} = 0b100000; >> - let Inst{15} = 0; >> -} >> - >> -// ADD r, sp, so_reg >> -def t2ADDrSPs : T2sTwoRegShiftedReg< >> - (outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), >> - IIC_iALUsi, "add", ".w\t$Rd, $Rn, $ShiftedRm", []> { >> - let Inst{31-27} = 0b11101; >> - let Inst{26-25} = 0b01; >> - let Inst{24-21} = 0b1000; >> - let Inst{15} = 0; >> -} >> - >> -// SUB r, sp, {so_imm|i12} >> -def t2SUBrSPi : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), >> - IIC_iALUi, "sub", ".w\t$Rd, $Rn, $imm", []> { >> - let Inst{31-27} = 0b11110; >> - let Inst{25} = 0; >> - let Inst{24-21} = 0b1101; >> - let Inst{15} = 0; >> -} >> -def t2SUBrSPi12 : T2TwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, imm0_4095:$imm), >> - IIC_iALUi, "subw", "\t$Rd, $Rn, $imm", []> { >> - let Inst{31-27} = 0b11110; >> - let Inst{25-20} = 0b101010; >> - let Inst{15} = 0; >> -} >> - >> -// SUB r, sp, so_reg >> -def t2SUBrSPs : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm), >> - IIC_iALUsi, >> - "sub", "\t$Rd, $Rn, $imm", []> { >> - let Inst{31-27} = 0b11101; >> - let Inst{26-25} = 0b01; >> - let Inst{24-21} = 0b1101; >> - let Inst{19-16} = 0b1101; // Rn = sp >> - let Inst{15} = 0; >> -} >> -} // end isCodeGenOnly = 1 >> - >> //===----------------------------------------------------------------------===// >> // Load / store Instructions. >> // >> >> Modified: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp?rev=134114&r1=134113&r2=134114&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp Wed Jun 29 18:25:04 2011 >> @@ -329,13 +329,9 @@ >> if (NewBase == 0) >> return false; >> } >> - int BaseOpc = !isThumb2 >> - ? ARM::ADDri >> - : ((Base == ARM::SP) ? ARM::t2ADDrSPi : ARM::t2ADDri); >> + int BaseOpc = !isThumb2 ? ARM::ADDri : ARM::t2ADDri; >> if (Offset < 0) { >> - BaseOpc = !isThumb2 >> - ? ARM::SUBri >> - : ((Base == ARM::SP) ? ARM::t2SUBrSPi : ARM::t2SUBri); >> + BaseOpc = !isThumb2 ? ARM::SUBri : ARM::t2SUBri; >> Offset = - Offset; >> } >> int ImmedOffset = isThumb2 >> @@ -516,8 +512,6 @@ >> if (!MI) >> return false; >> if (MI->getOpcode() != ARM::t2SUBri && >> - MI->getOpcode() != ARM::t2SUBrSPi && >> - MI->getOpcode() != ARM::t2SUBrSPi12 && >> MI->getOpcode() != ARM::tSUBspi && >> MI->getOpcode() != ARM::SUBri) >> return false; >> @@ -541,8 +535,6 @@ >> if (!MI) >> return false; >> if (MI->getOpcode() != ARM::t2ADDri && >> - MI->getOpcode() != ARM::t2ADDrSPi && >> - MI->getOpcode() != ARM::t2ADDrSPi12 && >> MI->getOpcode() != ARM::tADDspi && >> MI->getOpcode() != ARM::ADDri) >> return false; >> >> Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=134114&r1=134113&r2=134114&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Wed Jun 29 18:25:04 2011 >> @@ -251,7 +251,7 @@ >> } >> >> // sub rd, sp, so_imm >> - Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi; >> + Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; >> if (ARM_AM::getT2SOImmVal(NumBytes) != -1) { >> NumBytes = 0; >> } else { >> @@ -425,9 +425,9 @@ >> if (Offset < 0) { >> Offset = -Offset; >> isSub = true; >> - MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri)); >> + MI.setDesc(TII.get(ARM::t2SUBri)); >> } else { >> - MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri)); >> + MI.setDesc(TII.get(ARM::t2ADDri)); >> } >> >> // Common case: small offset, fits into instruction. >> @@ -443,9 +443,7 @@ >> // Another common case: imm12. >> if (Offset < 4096 && >> (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) { >> - unsigned NewOpc = isSP >> - ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12) >> - : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12); >> + unsigned NewOpc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; >> MI.setDesc(TII.get(NewOpc)); >> MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); >> MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset); >> >> Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134114&r1=134113&r2=134114&view=diff >> ============================================================================== >> --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original) >> +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Wed Jun 29 18:25:04 2011 >> @@ -57,10 +57,8 @@ >> static const ReduceEntry ReduceTable[] = { >> // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, PF, S >> { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0 }, >> - { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,0 }, >> + { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1 }, >> { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0 }, >> - // Note: immediate scale is 4. >> - { ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 0,1 }, >> { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1 }, >> { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1 }, >> { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0 }, >> @@ -291,7 +289,7 @@ >> Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD || >> Opc == ARM::t2LDMDB_UPD); >> bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD); >> - bool isSPOk = isPCOk || isLROk || (Opc == ARM::t2ADDrSPi); >> + bool isSPOk = isPCOk || isLROk; >> for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { >> const MachineOperand &MO = MI->getOperand(i); >> if (!MO.isReg() || MO.isImplicit()) >> @@ -481,6 +479,44 @@ >> Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, >> const ReduceEntry &Entry, >> bool LiveCPSR, MachineInstr *CPSRDef) { >> + unsigned Opc = MI->getOpcode(); >> + if (Opc == ARM::t2ADDri) { >> + // If the source register is SP, try to reduce to tADDrSPi, otherwise >> + // it's a normal reduce. >> + if (MI->getOperand(1).getReg() != ARM::SP) { >> + if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef)) >> + return true; >> + return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); >> + } >> + // Try to reduce to tADDrSPi. >> + unsigned Imm = MI->getOperand(2).getImm(); >> + // The immediate must be in range, the destination register must be a low >> + // reg, and the condition flags must not be being set. >> + if (Imm & 3 || Imm > 1024) >> + return false; >> + if (!isARMLowRegister(MI->getOperand(0).getReg())) >> + return false; >> + const MCInstrDesc &MCID = MI->getDesc(); >> + if (MCID.hasOptionalDef() && >> + MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) >> + return false; >> + >> + MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), >> + TII->get(ARM::tADDrSPi)) >> + .addOperand(MI->getOperand(0)) >> + .addOperand(MI->getOperand(1)) >> + .addImm(Imm / 4); // The tADDrSPi has an implied scale by four. >> + >> + // Transfer MI flags. >> + MIB.setMIFlags(MI->getFlags()); >> + >> + DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB); >> + >> + MBB.erase(MI); >> + ++NumNarrows; >> + return true; >> + } >> + >> if (Entry.LowRegs1 && !VerifyLowRegs(MI)) >> return false; >> >> @@ -488,7 +524,6 @@ >> if (MCID.mayLoad() || MCID.mayStore()) >> return ReduceLoadStore(MBB, MI, Entry); >> >> - unsigned Opc = MI->getOpcode(); >> switch (Opc) { >> default: break; >> case ARM::t2ADDSri: >> @@ -531,13 +566,6 @@ >> return true; >> return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); >> } >> - case ARM::t2ADDrSPi: { >> - static const ReduceEntry NarrowEntry = >> - { ARM::t2ADDrSPi,ARM::tADDspi, 0, 7, 0, 1, 0, 1, 0, 0,1 }; >> - if (MI->getOperand(0).getReg() == ARM::SP) >> - return ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef); >> - return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef); >> - } >> } >> return false; >> } >> @@ -645,9 +673,8 @@ >> return false; >> >> unsigned Limit = ~0U; >> - unsigned Scale = (Entry.WideOpc == ARM::t2ADDrSPi) ? 4 : 1; >> if (Entry.Imm1Limit) >> - Limit = ((1 << Entry.Imm1Limit) - 1) * Scale; >> + Limit = (1 << Entry.Imm1Limit) - 1; >> >> const MCInstrDesc &MCID = MI->getDesc(); >> for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) { >> @@ -658,13 +685,11 @@ >> unsigned Reg = MO.getReg(); >> if (!Reg || Reg == ARM::CPSR) >> continue; >> - if (Entry.WideOpc == ARM::t2ADDrSPi && Reg == ARM::SP) >> - continue; >> if (Entry.LowRegs1 && !isARMLowRegister(Reg)) >> return false; >> } else if (MO.isImm() && >> !MCID.OpInfo[i].isPredicate()) { >> - if (((unsigned)MO.getImm()) > Limit || (MO.getImm() & (Scale-1)) != 0) >> + if (((unsigned)MO.getImm()) > Limit) >> return false; >> } >> } >> @@ -723,15 +748,11 @@ >> if (SkipPred && isPred) >> continue; >> const MachineOperand &MO = MI->getOperand(i); >> - if (Scale > 1 && !isPred && MO.isImm()) >> - MIB.addImm(MO.getImm() / Scale); >> - else { >> - if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) >> - // Skip implicit def of CPSR. Either it's modeled as an optional >> - // def now or it's already an implicit def on the new instruction. >> - continue; >> - MIB.addOperand(MO); >> - } >> + if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) >> + // Skip implicit def of CPSR. Either it's modeled as an optional >> + // def now or it's already an implicit def on the new instruction. >> + continue; >> + MIB.addOperand(MO); >> } >> if (!MCID.isPredicable() && NewMCID.isPredicable()) >> AddDefaultPred(MIB); >> >> Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp >> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=134114&r1=134113&r2=134114&view=diff >> ============================================================================== >> --- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original) >> +++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Wed Jun 29 18:25:04 2011 >> @@ -1640,12 +1640,8 @@ >> // Ignore tADDrSP, tADDspr, and tPICADD, prefer the generic tADDhirr. >> // Ignore t2SUBrSPs, prefer the t2SUB[S]r[r|s]. >> // Ignore t2ADDrSPs, prefer the t2ADD[S]r[r|s]. >> - // Ignore t2ADDrSPi/t2SUBrSPi, which have more generic couterparts. >> - // Ignore t2ADDrSPi12/t2SUBrSPi12, which have more generic couterparts >> if (Name == "tADDrSP" || Name == "tADDspr" || Name == "tPICADD" || >> - Name == "t2SUBrSPs" || Name == "t2ADDrSPs" || >> - Name == "t2ADDrSPi" || Name == "t2SUBrSPi" || >> - Name == "t2ADDrSPi12" || Name == "t2SUBrSPi12") >> + Name == "t2SUBrSPs" || Name == "t2ADDrSPs") >> return false; >> >> // FIXME: Use ldr.n to work around a Darwin assembler bug. >> >> >> _______________________________________________ >> llvm-commits mailing list >> llvm-commits at cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > From stoklund at 2pi.dk Wed Jun 29 22:12:22 2011 From: stoklund at 2pi.dk (Jakob Stoklund Olesen) Date: Wed, 29 Jun 2011 20:12:22 -0700 Subject: [llvm-commits] [llvm] r134127 - in /llvm/trunk: include/llvm/MC/ include/llvm/Target/ lib/ExecutionEngine/ lib/MC/ lib/MC/MCDisassembler/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ tools/llc/ tools/llvm-mc/ tools/llvm-objdump/ too... In-Reply-To: <20110630015338.338512A6C12C@llvm.org> References: <20110630015338.338512A6C12C@llvm.org> Message-ID: <52AF7FB5-5670-46A3-AA2E-4402008CB0D2@2pi.dk> Don't forget to update llvm-gcc which calls this method. On Jun 29, 2011, at 6:53 PM, Evan Cheng wrote: > - /// Set the CPU string. Replaces previous setting. Setting to "" clears CPU. > - void setCPU(const std::string &String); > - From evan.cheng at apple.com Wed Jun 29 23:57:21 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Wed, 29 Jun 2011 21:57:21 -0700 Subject: [llvm-commits] [llvm] r134127 - in /llvm/trunk: include/llvm/MC/ include/llvm/Target/ lib/ExecutionEngine/ lib/MC/ lib/MC/MCDisassembler/ lib/Target/ARM/ lib/Target/ARM/AsmParser/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CBackend/ lib/Target/CellSPU/ lib/Target/CppBackend/ lib/Target/MBlaze/ lib/Target/MBlaze/AsmParser/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/ tools/llc/ tools/llvm-mc/ tools/llvm-objdump/ too... In-Reply-To: <52AF7FB5-5670-46A3-AA2E-4402008CB0D2@2pi.dk> References: <20110630015338.338512A6C12C@llvm.org> <52AF7FB5-5670-46A3-AA2E-4402008CB0D2@2pi.dk> Message-ID: <1EE7933A-8F0C-4BB1-B970-8FC6272FC585@apple.com> Yes, I'm fixing it now. Evan On Jun 29, 2011, at 8:12 PM, Jakob Stoklund Olesen wrote: > Don't forget to update llvm-gcc which calls this method. > > > > On Jun 29, 2011, at 6:53 PM, Evan Cheng wrote: > >> - /// Set the CPU string. Replaces previous setting. Setting to "" clears CPU. >> - void setCPU(const std::string &String); >> - From evan.cheng at apple.com Thu Jun 30 00:12:47 2011 From: evan.cheng at apple.com (Evan Cheng) Date: Thu, 30 Jun 2011 05:12:47 -0000 Subject: [llvm-commits] [llvm-gcc-4.2] r134133 - in /llvm-gcc-4.2/trunk/gcc: config/arm/arm.h config/i386/i386.h config/rs6000/rs6000.h llvm-backend.cpp Message-ID: <20110630051247.78CA92A6C12C@llvm.org> Author: evancheng Date: Thu Jun 30 00:12:47 2011 New Revision: 134133 URL: http://llvm.org/viewvc/llvm-project?rev=134133&view=rev Log: Match createTargetMachine API change. Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h llvm-gcc-4.2/trunk/gcc/config/i386/i386.h llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Modified: llvm-gcc-4.2/trunk/gcc/config/arm/arm.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/arm/arm.h?rev=134133&r1=134132&r2=134133&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/arm/arm.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/arm/arm.h Thu Jun 30 00:12:47 2011 @@ -3460,56 +3460,56 @@ /* Turn -march=xx into a CPU type. */ -#define LLVM_SET_SUBTARGET_FEATURES(F) \ +#define LLVM_SET_SUBTARGET_FEATURES(C, F) \ { switch (arm_tune) { \ - case arm8: F.setCPU("arm8"); break;\ - case arm810: F.setCPU("arm810"); break;\ - case strongarm: F.setCPU("strongarm"); break;\ - case strongarm110: F.setCPU("strongarm110"); break;\ - case strongarm1100: F.setCPU("strongarm1100"); break;\ - case strongarm1110: F.setCPU("strongarm1110"); break;\ - case arm7tdmi: F.setCPU("arm7tdmi"); break;\ - case arm7tdmis: F.setCPU("arm7tdmi-s"); break;\ - case arm710t: F.setCPU("arm710t"); break;\ - case arm720t: F.setCPU("arm720t"); break;\ - case arm740t: F.setCPU("arm740t"); break;\ - case arm9: F.setCPU("arm9"); break;\ - case arm9tdmi: F.setCPU("arm9tdmi"); break;\ - case arm920: F.setCPU("arm920"); break;\ - case arm920t: F.setCPU("arm920t"); break;\ - case arm922t: F.setCPU("arm922t"); break;\ - case arm940t: F.setCPU("arm940t"); break;\ - case ep9312: F.setCPU("ep9312"); break;\ - case arm10tdmi: F.setCPU("arm10tdmi"); break;\ - case arm1020t: F.setCPU("arm1020t"); break;\ - case arm9e: F.setCPU("arm9e"); break;\ - case arm946es: F.setCPU("arm946e-s"); break;\ - case arm966es: F.setCPU("arm966e-s"); break;\ - case arm968es: F.setCPU("arm968e-s"); break;\ - case arm10e: F.setCPU("arm10e"); break;\ - case arm1020e: F.setCPU("arm1020e"); break;\ - case arm1022e: F.setCPU("arm1022e"); break;\ - case xscale: F.setCPU("xscale"); break;\ - case iwmmxt: F.setCPU("iwmmxt"); break;\ - case arm926ejs: F.setCPU("arm926ej-s"); break;\ - case arm1026ejs: F.setCPU("arm1026ej-s"); break;\ - case arm1136js: F.setCPU("arm1136j-s"); break;\ - case arm1136jfs: F.setCPU("arm1136jf-s"); break;\ - case arm1176jzs: F.setCPU("arm1176jz-s"); break;\ - case arm1176jzfs: F.setCPU("arm1176jzf-s"); break;\ - case mpcorenovfp: F.setCPU("mpcorenovfp"); break;\ - case mpcore: F.setCPU("mpcore"); break;\ - case arm1156t2s: F.setCPU("arm1156t2-s"); break; \ - case arm1156t2fs: F.setCPU("arm1156t2f-s"); break; \ - case cortexa8: F.setCPU("cortex-a8"); break; \ - case cortexa9: F.setCPU("cortex-a9"); break; \ - case cortexa9mp: F.setCPU("cortex-a9-mp"); break; \ - case cortexr4: F.setCPU("cortex-r4"); break; \ - case cortexm3: F.setCPU("cortex-m3"); break; \ - case cortexm4: F.setCPU("cortex-m4"); break; \ - case cortexm0: F.setCPU("cortex-m0"); break; \ + case arm8: C = ("arm8"); break;\ + case arm810: C = ("arm810"); break;\ + case strongarm: C = ("strongarm"); break;\ + case strongarm110: C = ("strongarm110"); break;\ + case strongarm1100: C = ("strongarm1100"); break;\ + case strongarm1110: C = ("strongarm1110"); break;\ + case arm7tdmi: C = ("arm7tdmi"); break;\ + case arm7tdmis: C = ("arm7tdmi-s"); break;\ + case arm710t: C = ("arm710t"); break;\ + case arm720t: C = ("arm720t"); break;\ + case arm740t: C = ("arm740t"); break;\ + case arm9: C = ("arm9"); break;\ + case arm9tdmi: C = ("arm9tdmi"); break;\ + case arm920: C = ("arm920"); break;\ + case arm920t: C = ("arm920t"); break;\ + case arm922t: C = ("arm922t"); break;\ + case arm940t: C = ("arm940t"); break;\ + case ep9312: C = ("ep9312"); break;\ + case arm10tdmi: C = ("arm10tdmi"); break;\ + case arm1020t: C = ("arm1020t"); break;\ + case arm9e: C = ("arm9e"); break;\ + case arm946es: C = ("arm946e-s"); break;\ + case arm966es: C = ("arm966e-s"); break;\ + case arm968es: C = ("arm968e-s"); break;\ + case arm10e: C = ("arm10e"); break;\ + case arm1020e: C = ("arm1020e"); break;\ + case arm1022e: C = ("arm1022e"); break;\ + case xscale: C = ("xscale"); break;\ + case iwmmxt: C = ("iwmmxt"); break;\ + case arm926ejs: C = ("arm926ej-s"); break;\ + case arm1026ejs: C = ("arm1026ej-s"); break;\ + case arm1136js: C = ("arm1136j-s"); break;\ + case arm1136jfs: C = ("arm1136jf-s"); break;\ + case arm1176jzs: C = ("arm1176jz-s"); break;\ + case arm1176jzfs: C = ("arm1176jzf-s"); break;\ + case mpcorenovfp: C = ("mpcorenovfp"); break;\ + case mpcore: C = ("mpcore"); break;\ + case arm1156t2s: C = ("arm1156t2-s"); break; \ + case arm1156t2fs: C = ("arm1156t2f-s"); break; \ + case cortexa8: C = ("cortex-a8"); break; \ + case cortexa9: C = ("cortex-a9"); break; \ + case cortexa9mp: C = ("cortex-a9-mp"); break; \ + case cortexr4: C = ("cortex-r4"); break; \ + case cortexm3: C = ("cortex-m3"); break; \ + case cortexm4: C = ("cortex-m4"); break; \ + case cortexm0: C = ("cortex-m0"); break; \ default: \ - F.setCPU("arm7tdmi"); \ + C = ("arm7tdmi"); \ break; \ } \ if (TARGET_VFP3) \ Modified: llvm-gcc-4.2/trunk/gcc/config/i386/i386.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/i386/i386.h?rev=134133&r1=134132&r2=134133&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/i386/i386.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/i386/i386.h Thu Jun 30 00:12:47 2011 @@ -3879,11 +3879,11 @@ /* Turn -march=xx into a CPU type. */ -#define LLVM_SET_SUBTARGET_FEATURES(F) \ +#define LLVM_SET_SUBTARGET_FEATURES(C, F) \ { if (TARGET_MACHO && ! strcmp (ix86_arch_string, "apple")) \ - F.setCPU(TARGET_64BIT ? "core2" : "yonah"); \ + C = (TARGET_64BIT ? "core2" : "yonah"); \ else \ - F.setCPU(ix86_arch_string); \ + C = (ix86_arch_string); \ if (TARGET_64BIT) F.AddFeature("64bit"); \ if (TARGET_MMX) F.AddFeature("mmx"); \ else if (target_flags_explicit & MASK_MMX) F.AddFeature("mmx", false); \ Modified: llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h?rev=134133&r1=134132&r2=134133&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h (original) +++ llvm-gcc-4.2/trunk/gcc/config/rs6000/rs6000.h Thu Jun 30 00:12:47 2011 @@ -3459,11 +3459,11 @@ /* Turn -march=xx into a CPU type. */ -#define LLVM_SET_SUBTARGET_FEATURES(F) \ +#define LLVM_SET_SUBTARGET_FEATURES(C, F) \ { \ - F.setCPU(rs6000_cpu_target); \ + C = (rs6000_cpu_target); \ F.AddFeature("altivec", TARGET_ALTIVEC); \ - F.AddFeature("gpul", TARGET_MFCRF); \ + F.AddFeature("gpul", TARGET_MFCRF); \ F.AddFeature("fsqrt", TARGET_PPC_GPOPT); \ F.AddFeature("64bit", TARGET_POWERPC64); \ } Modified: llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp URL: http://llvm.org/viewvc/llvm-project/llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp?rev=134133&r1=134132&r2=134133&view=diff ============================================================================== --- llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp (original) +++ llvm-gcc-4.2/trunk/gcc/llvm-backend.cpp Thu Jun 30 00:12:47 2011 @@ -537,10 +537,12 @@ // Figure out the subtarget feature string we pass to the target. std::string FeatureStr; SubtargetFeatures Features; + // The target can set LLVM_SET_SUBTARGET_FEATURES to configure the LLVM // backend. + std::string CPU; #ifdef LLVM_SET_SUBTARGET_FEATURES - LLVM_SET_SUBTARGET_FEATURES(Features); + LLVM_SET_SUBTARGET_FEATURES(CPU, Features); #endif // Handle -mattr options passed into llvm @@ -548,7 +550,7 @@ Features.AddFeature(MAttrs[i]); FeatureStr = Features.getString(); - TheTarget = TME->createTargetMachine(TargetTriple, FeatureStr); + TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr); TheTarget->setMCUseLoc(false); TheTarget->setMCUseCFI(false); assert(TheTarget->getTargetData()->isBigEndian() == BYTES_BIG_ENDIAN); From jediknil at belkadan.com Thu Jun 30 01:32:31 2011 From: jediknil at belkadan.com (Jordy Rose) Date: Wed, 29 Jun 2011 23:32:31 -0700 Subject: [llvm-commits] [patch] Fix deprecation warning in lit on OS X In-Reply-To: <04FF9D64-CD87-49CB-A7CC-555715FEE038@apple.com> References: <5147384C-15F5-428E-8079-B5C3D6BDF46D@belkadan.com> <04FF9D64-CD87-49CB-A7CC-555715FEE038@apple.com> Message-ID: <36025C80-14C1-4B1D-8940-5D24B08A0F17@belkadan.com> Ah, thanks. It turns out it's even simpler to just reuse the 'capture' function defined below in Util.py. Is commit access for the Clang repo the same as the LLVM trunk? Jordy -------------- next part -------------- A non-text attachment was scrubbed... Name: Util.py.patch Type: application/octet-stream Size: 559 bytes Desc: not available Url : http://lists.cs.uiuc.edu/pipermail/llvm-commits/attachments/20110629/4d0ce5b5/attachment.obj -------------- next part -------------- On Jun 29, 2011, at 16:46, Andrew Trick wrote: > On Jun 29, 2011, at 11:57 AM, Jordy Rose wrote: >> I usually hang out on the Clang side of things, but I've noticed that the lit tests have a deprecation warning about 'popen2' that comes up on OS X. The attached patch replaces the use of 'popen2' with 'subprocess.Popen'. >> >> Jordy > > Looks good. > > FWIW, the more common idiom seems to be "out,_ = p.communicate()" > > -Andy From baldrick at free.fr Thu Jun 30 01:37:07 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 30 Jun 2011 06:37:07 -0000 Subject: [llvm-commits] [llvm] r134134 - /llvm/trunk/docs/ExtendingLLVM.html Message-ID: <20110630063707.77B102A6C12C@llvm.org> Author: baldrick Date: Thu Jun 30 01:37:07 2011 New Revision: 134134 URL: http://llvm.org/viewvc/llvm-project?rev=134134&view=rev Log: The enum was moved to ISDOpcodes.h. Modified: llvm/trunk/docs/ExtendingLLVM.html Modified: llvm/trunk/docs/ExtendingLLVM.html URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/ExtendingLLVM.html?rev=134134&r1=134133&r2=134134&view=diff ============================================================================== --- llvm/trunk/docs/ExtendingLLVM.html (original) +++ llvm/trunk/docs/ExtendingLLVM.html Thu Jun 30 01:37:07 2011 @@ -146,7 +146,7 @@ complicated behavior in a single node (rotate).

    -
  1. include/llvm/CodeGen/SelectionDAGNodes.h: +
  2. include/llvm/CodeGen/ISDOpcodes.h: Add an enum value for the new SelectionDAG node.
  3. lib/CodeGen/SelectionDAG/SelectionDAG.cpp: Add code to print the node to getOperationName. If your new node From baldrick at free.fr Thu Jun 30 06:41:38 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 30 Jun 2011 11:41:38 -0000 Subject: [llvm-commits] [dragonegg] r134142 - in /dragonegg/trunk: include/x86/dragonegg/Target.h src/Backend.cpp Message-ID: <20110630114139.0B3882A6C12C@llvm.org> Author: baldrick Date: Thu Jun 30 06:41:38 2011 New Revision: 134142 URL: http://llvm.org/viewvc/llvm-project?rev=134142&view=rev Log: Port commit 134133 from llvm-gcc, unbreaking the build. This way I can leave on holiday with the buildbots green at least :) Original commit message: (evancheng) Match createTargetMachine API change. Modified: dragonegg/trunk/include/x86/dragonegg/Target.h dragonegg/trunk/src/Backend.cpp Modified: dragonegg/trunk/include/x86/dragonegg/Target.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/x86/dragonegg/Target.h?rev=134142&r1=134141&r2=134142&view=diff ============================================================================== --- dragonegg/trunk/include/x86/dragonegg/Target.h (original) +++ dragonegg/trunk/include/x86/dragonegg/Target.h Thu Jun 30 06:41:38 2011 @@ -262,76 +262,76 @@ /* Turn -march=xx into a CPU type. */ -#define LLVM_SET_SUBTARGET_FEATURES(F) \ - { if (TARGET_MACHO && ! strcmp (ix86_arch_string, "apple")) \ - F.setCPU(TARGET_64BIT ? "core2" : "yonah"); \ - else \ - F.setCPU(ix86_arch_string); \ - \ - if (TARGET_64BIT) \ - F.AddFeature("64bit"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_64BIT) \ - F.AddFeature("64bit", false); \ - \ - if (TARGET_MMX) \ - F.AddFeature("mmx"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_MMX) \ - F.AddFeature("mmx", false); \ - \ - if (TARGET_3DNOW) \ - F.AddFeature("3dnow"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_3DNOW) \ - F.AddFeature("3dnow", false); \ - \ - if (TARGET_3DNOW_A) \ - F.AddFeature("3dnowa"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_3DNOW_A) \ - F.AddFeature("3dnowa", false); \ - \ - if (TARGET_SSE) \ - F.AddFeature("sse"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_SSE) \ - F.AddFeature("sse", false); \ - \ - if (TARGET_SSE2) \ - F.AddFeature("sse2"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_SSE2) \ - F.AddFeature("sse2", false); \ - \ - if (TARGET_SSE3) \ - F.AddFeature("sse3"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_SSE3) \ - F.AddFeature("sse3", false); \ - \ - if (TARGET_SSSE3) \ - F.AddFeature("ssse3"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_SSSE3) \ - F.AddFeature("ssse3", false); \ - \ - if (TARGET_SSE4_1) \ - F.AddFeature("sse41"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_SSE4_1) \ - F.AddFeature("sse41", false); \ - \ - if (TARGET_SSE4_2) \ - F.AddFeature("sse42"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_SSE4_2) \ - F.AddFeature("sse42", false); \ - \ - if (TARGET_AVX) \ - F.AddFeature("avx"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_AVX) \ - F.AddFeature("avx", false); \ - \ - if (TARGET_FMA) \ - F.AddFeature("fma3"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_FMA) \ - F.AddFeature("fma3", false); \ - \ - if (TARGET_SSE4A) \ - F.AddFeature("sse4a"); \ - else if (target_flags_explicit & OPTION_MASK_ISA_SSE4A) \ - F.AddFeature("sse4a", false); \ +#define LLVM_SET_SUBTARGET_FEATURES(C, F) \ + { if (TARGET_MACHO && ! strcmp (ix86_arch_string, "apple")) \ + C = TARGET_64BIT ? "core2" : "yonah"; \ + else \ + C = ix86_arch_string; \ + \ + if (TARGET_64BIT) \ + F.AddFeature("64bit"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_64BIT) \ + F.AddFeature("64bit", false); \ + \ + if (TARGET_MMX) \ + F.AddFeature("mmx"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_MMX) \ + F.AddFeature("mmx", false); \ + \ + if (TARGET_3DNOW) \ + F.AddFeature("3dnow"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_3DNOW) \ + F.AddFeature("3dnow", false); \ + \ + if (TARGET_3DNOW_A) \ + F.AddFeature("3dnowa"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_3DNOW_A) \ + F.AddFeature("3dnowa", false); \ + \ + if (TARGET_SSE) \ + F.AddFeature("sse"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_SSE) \ + F.AddFeature("sse", false); \ + \ + if (TARGET_SSE2) \ + F.AddFeature("sse2"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_SSE2) \ + F.AddFeature("sse2", false); \ + \ + if (TARGET_SSE3) \ + F.AddFeature("sse3"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_SSE3) \ + F.AddFeature("sse3", false); \ + \ + if (TARGET_SSSE3) \ + F.AddFeature("ssse3"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_SSSE3) \ + F.AddFeature("ssse3", false); \ + \ + if (TARGET_SSE4_1) \ + F.AddFeature("sse41"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_SSE4_1) \ + F.AddFeature("sse41", false); \ + \ + if (TARGET_SSE4_2) \ + F.AddFeature("sse42"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_SSE4_2) \ + F.AddFeature("sse42", false); \ + \ + if (TARGET_AVX) \ + F.AddFeature("avx"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_AVX) \ + F.AddFeature("avx", false); \ + \ + if (TARGET_FMA) \ + F.AddFeature("fma3"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_FMA) \ + F.AddFeature("fma3", false); \ + \ + if (TARGET_SSE4A) \ + F.AddFeature("sse4a"); \ + else if (target_flags_explicit & OPTION_MASK_ISA_SSE4A) \ + F.AddFeature("sse4a", false); \ } #define LLVM_SET_IMPLICIT_FLOAT(flag_no_implicit_float) \ Modified: dragonegg/trunk/src/Backend.cpp URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/src/Backend.cpp?rev=134142&r1=134141&r2=134142&view=diff ============================================================================== --- dragonegg/trunk/src/Backend.cpp (original) +++ dragonegg/trunk/src/Backend.cpp Thu Jun 30 06:41:38 2011 @@ -405,12 +405,13 @@ std::string FeatureStr; // The target can set LLVM_SET_SUBTARGET_FEATURES to configure the LLVM // backend. + std::string CPU; #ifdef LLVM_SET_SUBTARGET_FEATURES SubtargetFeatures Features; - LLVM_SET_SUBTARGET_FEATURES(Features); + LLVM_SET_SUBTARGET_FEATURES(CPU, Features); FeatureStr = Features.getString(); #endif - TheTarget = TME->createTargetMachine(TargetTriple, FeatureStr); + TheTarget = TME->createTargetMachine(TargetTriple, CPU, FeatureStr); TheTarget->setMCUseCFI(flag_dwarf2_cfi_asm); assert(TheTarget->getTargetData()->isBigEndian() == BYTES_BIG_ENDIAN); } From baldrick at free.fr Thu Jun 30 07:31:46 2011 From: baldrick at free.fr (Duncan Sands) Date: Thu, 30 Jun 2011 12:31:46 -0000 Subject: [llvm-commits] [dragonegg] r134144 - in /dragonegg/trunk/include/openbsd: ./ dragonegg/ dragonegg/OS.h Message-ID: <20110630123146.9B79B2A6C12C@llvm.org> Author: baldrick Date: Thu Jun 30 07:31:46 2011 New Revision: 134144 URL: http://llvm.org/viewvc/llvm-project?rev=134144&view=rev Log: Support for OpenBSD. Patch by Jonathan Gray. Added: dragonegg/trunk/include/openbsd/ dragonegg/trunk/include/openbsd/dragonegg/ dragonegg/trunk/include/openbsd/dragonegg/OS.h Added: dragonegg/trunk/include/openbsd/dragonegg/OS.h URL: http://llvm.org/viewvc/llvm-project/dragonegg/trunk/include/openbsd/dragonegg/OS.h?rev=134144&view=auto ============================================================================== --- dragonegg/trunk/include/openbsd/dragonegg/OS.h (added) +++ dragonegg/trunk/include/openbsd/dragonegg/OS.h Thu Jun 30 07:31:46 2011 @@ -0,0 +1,33 @@ +//===------------ OS.h - OpenBSD specific definitions -----------*- C++ -*-===// +// +// Copyright (C) 2009, 2010, 2011 Duncan Sands et al. +// +// This file is part of DragonEgg. +// +// DragonEgg is free software; you can redistribute it and/or modify it under +// the terms of the GNU General Public License as published by the Free Software +// Foundation; either version 2, or (at your option) any later version. +// +// DragonEgg is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. See the GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License along with +// DragonEgg; see the file COPYING. If not, write to the Free Software +// Foundation, 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA. +// +//===----------------------------------------------------------------------===// +// This file provides OpenBSD specific declarations. +//===----------------------------------------------------------------------===// + +#ifndef DRAGONEGG_OS_H +#define DRAGONEGG_OS_H + +/* Yes, we support PIC codegen for OpenBSD targets! */ +#define LLVM_SET_TARGET_OPTIONS(argvec) \ + if (flag_pic) \ + argvec.push_back ("--relocation-model=pic"); \ + else \ + argvec.push_back ("--relocation-model=static"); + +#endif /* DRAGONEGG_OS_H */ From rafael.espindola at gmail.com Thu Jun 30 08:17:24 2011 From: rafael.espindola at gmail.com (Rafael Espindola) Date: Thu, 30 Jun 2011 13:17:24 -0000 Subject: [llvm-commits] [llvm] r134148 - /llvm/trunk/lib/CodeGen/RegisterCoalescer.h Message-ID: <20110630131724.8DF202A6C12C@llvm.org> Author: rafael Date: Thu Jun 30 08:17:24 2011 New Revision: 134148 URL: http://llvm.org/viewvc/llvm-project?rev=134148&view=rev Log: Remove dead code. Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.h Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.h URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.h?rev=134148&r1=134147&r2=134148&view=diff ============================================================================== --- llvm/trunk/lib/CodeGen/RegisterCoalescer.h (original) +++ llvm/trunk/lib/CodeGen/RegisterCoalescer.h Thu Jun 30 08:17:24 2011 @@ -160,94 +160,6 @@ virtual void print(raw_ostream &O, const Module* = 0) const; }; - /// An abstract interface for register allocators to interact with - /// coalescers - /// - /// Example: - /// - /// This is simply an example of how to use the RegallocQuery - /// interface. It is not meant to be used in production. - /// - /// class LinearScanRegallocQuery : public RegallocQuery { - /// private: - /// const LiveIntervals \&li; - /// - /// public: - /// LinearScanRegallocQuery(LiveIntervals &intervals) - /// : li(intervals) {} - /// - /// /// This is pretty slow and conservative, but since linear scan - /// /// allocation doesn't pre-compute interference information it's - /// /// the best we can do. Coalescers are always free to ignore this - /// /// and implement their own discovery strategy. See - /// /// RegisterCoalescer for an example. - /// void getInterferences(IntervalSet &interferences, - /// const LiveInterval &a) const { - /// for(LiveIntervals::const_iterator iv = li.begin(), - /// ivend = li.end(); - /// iv != ivend; - /// ++iv) { - /// if (interfere(a, iv->second)) { - /// interferences.insert(&iv->second); - /// } - /// } - /// } - /// - /// /// This is *really* slow and stupid. See above. - /// int getNumberOfInterferences(const LiveInterval &a) const { - /// IntervalSet intervals; - /// getInterferences(intervals, a); - /// return intervals.size(); - /// } - /// }; - /// - /// In the allocator: - /// - /// RegisterCoalescer &coalescer = getAnalysis(); - /// - /// // We don't reset the coalescer so if it's already been run this - /// // takes almost no time. - /// LinearScanRegallocQuery ifd(*li_); - /// - class RegallocQuery { - public: - typedef SmallPtrSet IntervalSet; - - virtual ~RegallocQuery() {} - - /// Return whether two live ranges interfere. - virtual bool interfere(const LiveInterval &a, - const LiveInterval &b) const { - // A naive test - return a.overlaps(b); - } - - /// Return the set of intervals that interfere with this one. - virtual void getInterferences(IntervalSet &interferences, - const LiveInterval &a) const = 0; - - /// This can often be cheaper than actually returning the - /// interferences. - virtual int getNumberOfInterferences(const LiveInterval &a) const = 0; - - /// Make any data structure updates necessary to reflect - /// coalescing or other modifications. - virtual void updateDataForMerge(const LiveInterval &a, - const LiveInterval &b, - const MachineInstr ©) {} - - /// Allow the register allocator to communicate when it doesn't - /// want a copy coalesced. This may be due to assumptions made by - /// the allocator about various invariants and so this question is - /// a matter of legality, not performance. Performance decisions - /// about which copies to coalesce should be made by the - /// coalescer. - virtual bool isLegalToCoalesce(const MachineInstr &inst) const { - return true; - } - }; - - /// CoalescerPair - A helper class for register coalescers. When deciding if /// two registers can be coalesced, CoalescerPair can determine if a copy /// instruction would become an identity copy after coalescing. From grosser at fim.uni-passau.de Thu Jun 30 09:07:24 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 30 Jun 2011 14:07:24 -0000 Subject: [llvm-commits] [polly] r134152 - /polly/trunk/www/get_started.html Message-ID: <20110630140724.203742A6C12C@llvm.org> Author: grosser Date: Thu Jun 30 09:07:23 2011 New Revision: 134152 URL: http://llvm.org/viewvc/llvm-project?rev=134152&view=rev Log: www: How to use most recent version of isl In some cases it is necessary to use a version of isl that is more recent than the one included with CLooG. Point out what is needed to get such a version. Modified: polly/trunk/www/get_started.html Modified: polly/trunk/www/get_started.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/get_started.html?rev=134152&r1=134151&r2=134152&view=diff ============================================================================== --- polly/trunk/www/get_started.html (original) +++ polly/trunk/www/get_started.html Thu Jun 30 09:07:23 2011 @@ -28,8 +28,8 @@

    Install ISL / CLooG libraries

    Polly requires the latest versions of CLooG -and isl to be installed. The CLooG git -repository contains both the latest version of CLooG and isl. +and the version of isl included with +CLooG. To install both use the following commands. 
     git clone git://repo.or.cz/cloog.git
@@ -41,6 +41,27 @@
 make install
    +

    Use isl trunk

    + +In rare case it is necessary to use an isl version that is even newer than +the one included in CLooG. This may happen, because we work in close interaction +with the developers of isl such that Polly sometimes uses features that are not +yet available in the version of isl which is included with CLooG. To get the +most recent version of isl perform these additional steps.
    +Only perform these steps if a recent mailing list message asks you to do +so. + +
    +cd isl
+git remote update
+git checkout origin/master
+cd ..
+./autogen.sh
+./configure  --with-gmp-prefix=/path/to/gmp/installation --prefix=/path/to/cloog/installation
+make
+make install
+
    +

    Install Pocc (Optional)

    Polly can use From grosser at fim.uni-passau.de Thu Jun 30 09:07:36 2011 From: grosser at fim.uni-passau.de (Tobias Grosser) Date: Thu, 30 Jun 2011 14:07:36 -0000 Subject: [llvm-commits] [polly] r134153 - /polly/trunk/www/get_started.html Message-ID: <20110630140736.2053E2A6C12C@llvm.org> Author: grosser Date: Thu Jun 30 09:07:35 2011 New Revision: 134153 URL: http://llvm.org/viewvc/llvm-project?rev=134153&view=rev Log: www/get_started: Explain when PoCC is needed Modified: polly/trunk/www/get_started.html Modified: polly/trunk/www/get_started.html URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/get_started.html?rev=134153&r1=134152&r2=134153&view=diff ============================================================================== --- polly/trunk/www/get_started.html (original) +++ polly/trunk/www/get_started.html Thu Jun 30 09:07:35 2011 @@ -64,11 +64,16 @@

    Install Pocc (Optional)

    -Polly can use     -PoCC as an external optimizer. PoCC provides an -integrated version of Pluto, an advanced -data-locality and tileability optimizer. To enable this feature install PoCC -1.0-rc3.1 (the one with Polly support) and add it to your PATH. +

    Polly can use +PoCC as an external optimizer. PoCC is a research project that provides +an integrated version of Pluto, an +advanced data-locality and tileability optimizer. Similar functionality was +recently integrated in Polly (through isl), however the optimizations are not as +mature as the ones in Pluto/PoCC. Hence, if you want to use Pluto to optimize +your code or you want to compare the optimizer integrated in Polly to Pluto you +may want to use PoCC.

    + +Install PoCC 1.0-rc3.1 (the one with Polly support) and add it to your PATH. 
     wget 
 
-Furthermore, scoplib-0.2.0 has to be installed such that polly can link to
-it.
+Install scoplib-0.2.0
 
 
     wget 

Author: grosser
Date: Thu Jun 30 09:32:33 2011
New Revision: 134156

URL: http://llvm.org/viewvc/llvm-project?rev=134156&view=rev
Log:
www/contributers: Add founding through Google Doctoral Fellowship

Modified:
    polly/trunk/www/contributors.html
    polly/trunk/www/index.html

Modified: polly/trunk/www/contributors.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/contributors.html?rev=134156&r1=134155&r2=134156&view=diff
==============================================================================
--- polly/trunk/www/contributors.html (original)
+++ polly/trunk/www/contributors.html Thu Jun 30 09:32:33 2011
@@ -24,10 +24,13 @@
 
 
    Tobias Grosser
    
 
    Tobias is one of the two Co-founders of Polly. He designed the overall
-architecture and contributed to almost every part of Polly. He did his work
+architecture and contributed to almost every part of Polly. Polly was started
 during his diploma studies at University of Passau. Furthermore, he spent 6
-months at Ohio State University where he was founded by the U.S. National
-Science Foundation through awards 0811781 and 0926688.
    
+months at Ohio State University (founded by the U.S. National Science Foundation
+through awards 0811781 and 0926688). From August 2011 he works on Polly,
+during his PhD with INRIA/UMPC/ENS (founded for three years through
+    
+Google Europe Fellowship in Efficient Computing).
    
 
 
    Website: www.grosser.es
    
 

Modified: polly/trunk/www/index.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/index.html?rev=134156&r1=134155&r2=134156&view=diff
==============================================================================
--- polly/trunk/www/index.html (original)
+++ polly/trunk/www/index.html Thu Jun 30 09:32:33 2011
@@ -36,9 +36,14 @@
   
 
   
      
-  
    • May 2011 - Tobias' diploma thesis and Raghesh's master thesis are
-  published. For details see our list of
-  publications.
      • 
+  
    • June 2011 - Tobias is founded for
+  three years through a 
+  Google Europe Fellowship in Efficient Computing.
+  
      • 
+  
    • May 2011 - Tobias' diploma thesis and
+  Raghesh's master thesis are published. For details see our list of publications.
      • 
   
    • April 2011 - Polly moves to the LLVM infrastructure 
      • 
   
    • March 2011 - Polly is presented at CGO/IMPACT 2011, Polly can compile



From grosser at fim.uni-passau.de  Thu Jun 30 09:43:35 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 30 Jun 2011 14:43:35 -0000
Subject: [llvm-commits] [polly] r134158 - in /polly/trunk/www:
	contributors.html index.html
Message-ID: <20110630144335.B3C472A6C12C@llvm.org>

Author: grosser
Date: Thu Jun 30 09:43:35 2011
New Revision: 134158

URL: http://llvm.org/viewvc/llvm-project?rev=134158&view=rev
Log:
www: Fix typos.

Modified:
    polly/trunk/www/contributors.html
    polly/trunk/www/index.html

Modified: polly/trunk/www/contributors.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/contributors.html?rev=134158&r1=134157&r2=134158&view=diff
==============================================================================
--- polly/trunk/www/contributors.html (original)
+++ polly/trunk/www/contributors.html Thu Jun 30 09:43:35 2011
@@ -28,7 +28,7 @@
 during his diploma studies at University of Passau. Furthermore, he spent 6
 months at Ohio State University (founded by the U.S. National Science Foundation
 through awards 0811781 and 0926688). From August 2011 he works on Polly,
-during his PhD with INRIA/UMPC/ENS (founded for three years through
+during his PhD with INRIA/UMPC/ENS (founded through a
 
 Google Europe Fellowship in Efficient Computing).
      
 

Modified: polly/trunk/www/index.html
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/www/index.html?rev=134158&r1=134157&r2=134158&view=diff
==============================================================================
--- polly/trunk/www/index.html (original)
+++ polly/trunk/www/index.html Thu Jun 30 09:43:35 2011
@@ -36,7 +36,7 @@
   
 
   
        
-  
      • June 2011 - Tobias is founded for
+  
      • June 2011 - Tobias is founded for
   three years through a 
   Google Europe Fellowship in Efficient Computing.



From rdivacky at freebsd.org  Thu Jun 30 10:32:20 2011
From: rdivacky at freebsd.org (Roman Divacky)
Date: Thu, 30 Jun 2011 17:32:20 +0200
Subject: [llvm-commits] [PATCH]: wrong PPC32 targetdata in llvm
Message-ID: <20110630153220.GA45513@freebsd.org>

Hi,

The definition of targetdata in llvm differs to the one in clang.
Specifically the ABI alignment of 64bit types on PPC32 is 32 in
llvm and 64 in llvm. The clang one seems to be the correct one.
As it is, the following test fails:

typedef struct
{
    char        v_type;     /* see below: VAR_NUMBER, VAR_STRING, etc. */
    union
    {   
        double          v_float;        /* floating number value */
    }           vval;
} typval_T;

typval_T vimvars[16];

int main(void) {
        printf("Difference: %ld (should be: %zd)\n", (long)&vimvars[1] - (long)&vimvars[0], sizeof(vimvars[0]));
        return 0;
}

where it prints:

Difference: 12 (should be: 16)

OK to commit the attached patch that increases the ABI alignment to 64? With
this patch I am able to build a working vim (the editor) on ppc32 at both -O0
and -O2. Without it, it fails because the test above fails.

roman
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From baldrick at free.fr  Thu Jun 30 10:38:42 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 30 Jun 2011 17:38:42 +0200
Subject: [llvm-commits] [PATCH]: wrong PPC32 targetdata in llvm
In-Reply-To: <20110630153220.GA45513@freebsd.org>
References: <20110630153220.GA45513@freebsd.org>
Message-ID: <4E0C9882.1070907@free.fr>

Hi Roman,

> The definition of targetdata in llvm differs to the one in clang.
> Specifically the ABI alignment of 64bit types on PPC32 is 32 in
> llvm and 64 in llvm. The clang one seems to be the correct one.

why isn't clang querying llvm to get the target data?

Ciao, Duncan.

From rdivacky at freebsd.org  Thu Jun 30 10:47:38 2011
From: rdivacky at freebsd.org (Roman Divacky)
Date: Thu, 30 Jun 2011 17:47:38 +0200
Subject: [llvm-commits] [PATCH]: wrong PPC32 targetdata in llvm
In-Reply-To: <4E0C9882.1070907@free.fr>
References: <20110630153220.GA45513@freebsd.org> <4E0C9882.1070907@free.fr>
Message-ID: <20110630154738.GA47099@freebsd.org>

On Thu, Jun 30, 2011 at 05:38:42PM +0200, Duncan Sands wrote:
> Hi Roman,
> 
> > The definition of targetdata in llvm differs to the one in clang.
> > Specifically the ABI alignment of 64bit types on PPC32 is 32 in
> > llvm and 64 in llvm. The clang one seems to be the correct one.
> 
> why isn't clang querying llvm to get the target data?

I don't know. Clang has target data definition for every arch. It
seems wrong to me as well.

Anyway, the PPC32 target data definition in llvm is wrong and needs
to be correct with the patch I attached.

roman

From atrick at apple.com  Thu Jun 30 11:31:15 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 30 Jun 2011 09:31:15 -0700
Subject: [llvm-commits] [patch] Fix deprecation warning in lit on OS X
In-Reply-To: <36025C80-14C1-4B1D-8940-5D24B08A0F17@belkadan.com>
References: <5147384C-15F5-428E-8079-B5C3D6BDF46D@belkadan.com>
	<04FF9D64-CD87-49CB-A7CC-555715FEE038@apple.com>
	<36025C80-14C1-4B1D-8940-5D24B08A0F17@belkadan.com>
Message-ID: 


On Jun 29, 2011, at 11:32 PM, Jordy Rose wrote:

> Ah, thanks. It turns out it's even simpler to just reuse the 'capture' function defined below in Util.py.

Neat.

> Is commit access for the Clang repo the same as the LLVM trunk?

I assume access is the same. Give it a try.

-Andy

From sanjoy at playingwithpointers.com  Thu Jun 30 11:38:03 2011
From: sanjoy at playingwithpointers.com (Sanjoy Das)
Date: Thu, 30 Jun 2011 22:08:03 +0530
Subject: [llvm-commits] Segmented stacks, current status.
In-Reply-To: <4E09FBDB.5050401@gmail.com>
References: <4E089271.40607@playingwithpointers.com>
	<4E09FBDB.5050401@gmail.com>
Message-ID: <4E0CA66B.8020904@playingwithpointers.com>

Hi!

> but the function then looks for a callee saved register that is not live
> in. Can we be sure that one is always available? Looking at gold (if you
> plan to use it for linking segmented and non segmented code), it looks
> like it assumes r10 or r11 is used.

I've changed the code to use R10 as the scratch register.

> You are computing "stacklimit + size" and comparing rsp with it. Looks
> like gold assume a lea NN(%rs) to compute rs-size and that then gets
> compared with stacklimit. That also saves one instruction, no?

Done.

> The comment is stale :-)

Also done.

> 
> Dose __morestack_allocate_stack_space takes care of linking the memory
> so that when this function is called again we don't allocate another
> lange block?
> 

Yes, it maintains a free list; which it tries to re-use if possible.

I'll now try to implement varargs, and see how it goes.

PS: The corrected code is on github.

-- 
Sanjoy Das
http://playingwithpointers.com

From rjmccall at apple.com  Thu Jun 30 12:20:55 2011
From: rjmccall at apple.com (John McCall)
Date: Thu, 30 Jun 2011 10:20:55 -0700
Subject: [llvm-commits] [PATCH]: wrong PPC32 targetdata in llvm
In-Reply-To: <20110630154738.GA47099@freebsd.org>
References: <20110630153220.GA45513@freebsd.org> <4E0C9882.1070907@free.fr>
	<20110630154738.GA47099@freebsd.org>
Message-ID: <5D3F3545-6E79-4FAC-A475-0A36AD202B3B@apple.com>


On Jun 30, 2011, at 8:47 AM, Roman Divacky wrote:

> On Thu, Jun 30, 2011 at 05:38:42PM +0200, Duncan Sands wrote:
>> Hi Roman,
>> 
>>> The definition of targetdata in llvm differs to the one in clang.
>>> Specifically the ABI alignment of 64bit types on PPC32 is 32 in
>>> llvm and 64 in llvm. The clang one seems to be the correct one.
>> 
>> why isn't clang querying llvm to get the target data?
> 
> I don't know. Clang has target data definition for every arch. It
> seems wrong to me as well.

There was a decision to try to make Clang independent of the linked-in
target machines;  the virtue is that Clang can generate IR for an arbitrary
target without needing an actual backend, which (among other things)
simplifies cross-platform testing.  The disadvantage, of course, is
code / information duplication.

John.

From grosbach at apple.com  Thu Jun 30 12:28:55 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 30 Jun 2011 10:28:55 -0700
Subject: [llvm-commits] [PATCH]: wrong PPC32 targetdata in llvm
In-Reply-To: <5D3F3545-6E79-4FAC-A475-0A36AD202B3B@apple.com>
References: <20110630153220.GA45513@freebsd.org> <4E0C9882.1070907@free.fr>
	<20110630154738.GA47099@freebsd.org>
	<5D3F3545-6E79-4FAC-A475-0A36AD202B3B@apple.com>
Message-ID: <389B7948-38E5-4B42-AE15-6D880A0ECE72@apple.com>

On Jun 30, 2011, at 10:20 AM, John McCall wrote:
> On Jun 30, 2011, at 8:47 AM, Roman Divacky wrote:
> On Thu, Jun 30, 2011 at 05:38:42PM +0200, Duncan Sands wrote:
>>> Hi Roman,
>>> 
>>>> The definition of targetdata in llvm differs to the one in clang.
>>>> Specifically the ABI alignment of 64bit types on PPC32 is 32 in
>>>> llvm and 64 in llvm. The clang one seems to be the correct one.
>>> 
>>> why isn't clang querying llvm to get the target data?
>> 
>> I don't know. Clang has target data definition for every arch. It
>> seems wrong to me as well.
> 
> There was a decision to try to make Clang independent of the linked-in
> target machines;  the virtue is that Clang can generate IR for an arbitrary
> target without needing an actual backend, which (among other things)
> simplifies cross-platform testing.  The disadvantage, of course, is
> code / information duplication.

Perhaps we could/should refactor the targetdata bits in the back end such that they're aways available for all targets, even if the target itself isn't enabled? Some of Evan's recent work might enable that.

-Jim

From grosbach at apple.com  Thu Jun 30 12:34:04 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 30 Jun 2011 17:34:04 -0000
Subject: [llvm-commits] [llvm] r134172 - in /llvm/trunk:
 lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMInstrThumb.td
 utils/TableGen/ARMDecoderEmitter.cpp
Message-ID: <20110630173404.A75EE2A6C12C@llvm.org>

Author: grosbach
Date: Thu Jun 30 12:34:04 2011
New Revision: 134172

URL: http://llvm.org/viewvc/llvm-project?rev=134172&view=rev
Log:
Pseudo-ize the Thumb tPOP_RET instruction.

It's just a tPOP instruction with additional code-gen properties, so it
doesn't need encoding information.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134172&r1=134171&r2=134172&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Jun 30 12:34:04 2011
@@ -1096,6 +1096,14 @@
     OutStreamer.EmitInstruction(TmpInst);
     return;
   }
+  case ARM::tPOP_RET: {
+    // As above for LDMIA_RET. Map to the tPOP instruction.
+    MCInst TmpInst;
+    LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
+    TmpInst.setOpcode(ARM::tPOP);
+    OutStreamer.EmitInstruction(TmpInst);
+    return;
+  }
 
   case ARM::t2MOVi32imm: assert(0 && "Should be lowered by thumb2it pass");
   case ARM::DBG_VALUE: {

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134172&r1=134171&r2=134172&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Jun 30 12:34:04 2011
@@ -408,15 +408,8 @@
 // FIXME: remove when we have a way to marking a MI with these properties.
 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
     hasExtraDefRegAllocReq = 1 in
-def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
-                   IIC_iPop_Br,
-                   "pop${p}\t$regs", []>,
-               T1Misc<{1,1,0,?,?,?,?}> {
-  // A8.6.121
-  bits<16> regs;
-  let Inst{8}   = regs{15};     // registers = P:'0000000':register_list
-  let Inst{7-0} = regs{7-0};
-}
+def tPOP_RET : tPseudoInst<(outs), (ins pred:$p, reglist:$regs, variable_ops),
+                           Size4Bytes, IIC_iPop_Br, []>;
 
 // All calls clobber the non-callee saved registers. SP is marked as a use to
 // prevent stack-pointer assignments that appear immediately before calls from

Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=134172&r1=134171&r2=134172&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Thu Jun 30 12:34:04 2011
@@ -1656,13 +1656,13 @@
     // Resolve conflicts:
     //
     //   tBfar conflicts with tBLr9
-    //   tPOP_RET/t2LDMIA_RET conflict with tPOP/t2LDM (ditto)
+    //   t2LDMIA_RET conflict with t2LDM (ditto)
     //   tMOVCCi conflicts with tMOVi8
     //   tMOVCCr conflicts with tMOVgpr2gpr
     //   tLDRcp conflicts with tLDRspi
     //   t2MOVCCi16 conflicts with tMOVi16
     if (Name == "tBfar" ||
-        Name == "tPOP_RET" || Name == "t2LDMIA_RET" ||
+        Name == "t2LDMIA_RET" ||
         Name == "tMOVCCi" || Name == "tMOVCCr" ||
         Name == "tLDRcp" || 
         Name == "t2MOVCCi16")



From evan.cheng at apple.com  Thu Jun 30 13:25:01 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 30 Jun 2011 11:25:01 -0700
Subject: [llvm-commits] [llvm] r134049 - in /llvm/trunk:
 include/llvm/MC/ include/llvm/Target/ lib/CodeGen/
 lib/CodeGen/SelectionDAG/ lib/ExecutionEngine/ lib/MC/ lib/Target/
 lib/Target/ARM/ lib/Target/Alpha/ lib/Target/CellSPU/ lib/Target/MBlaze/
 lib/Tar
In-Reply-To: 
References: 
Message-ID: <71AB4D52-405A-47C3-9F99-7809C8CFDA71@apple.com>


On Jun 28, 2011, at 10:51 PM, Anton Korobeynikov wrote:

> Hi Evan,
> 
>> Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC.
> Given that scheduling is performed on MachinInstr's, why itineraries
> should go into MC?

That's how it is today, but it doesn't have to be that way.

I'm considering building binary analysis tools which can point out instruction stalls, etc. in machine code.

Evan

> 
> -- 
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersburg State University


From grosbach at apple.com  Thu Jun 30 13:25:42 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 30 Jun 2011 18:25:42 -0000
Subject: [llvm-commits] [llvm] r134173 - in /llvm/trunk:
 lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMInstrThumb2.td
 test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
Message-ID: <20110630182542.BAF2B2A6C12C@llvm.org>

Author: grosbach
Date: Thu Jun 30 13:25:42 2011
New Revision: 134173

URL: http://llvm.org/viewvc/llvm-project?rev=134173&view=rev
Log:
Pseudo-ize the t2LDMIA_RET instruction.

It's just a t2LDMIA_UPD instruction with extra codegen properties, so it
doesn't need the encoding information. As a side-benefit, we now correctly
recognize for instruction printing as a 'pop' instruction.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134173&r1=134172&r2=134173&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Jun 30 13:25:42 2011
@@ -1096,6 +1096,14 @@
     OutStreamer.EmitInstruction(TmpInst);
     return;
   }
+  case ARM::t2LDMIA_RET: {
+    // As above for LDMIA_RET. Map to the tPOP instruction.
+    MCInst TmpInst;
+    LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
+    TmpInst.setOpcode(ARM::t2LDMIA_UPD);
+    OutStreamer.EmitInstruction(TmpInst);
+    return;
+  }
   case ARM::tPOP_RET: {
     // As above for LDMIA_RET. Map to the tPOP instruction.
     MCInst TmpInst;

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=134173&r1=134172&r2=134173&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Jun 30 13:25:42 2011
@@ -2962,28 +2962,13 @@
 //
 
 // FIXME: remove when we have a way to marking a MI with these properties.
-// FIXME: $dst1 should be a def. But the extra ops must be in the end of the
-// operand list.
 // FIXME: Should pc be an implicit operand like PICADD, etc?
 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
     hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
-def t2LDMIA_RET: T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
-                                        reglist:$regs, variable_ops),
-                        IIC_iLoad_mBr,
-                        "ldmia${p}.w\t$Rn!, $regs",
-                        "$Rn = $wb", []> {
-  bits<4>  Rn;
-  bits<16> regs;
-
-  let Inst{31-27} = 0b11101;
-  let Inst{26-25} = 0b00;
-  let Inst{24-23} = 0b01;     // Increment After
-  let Inst{22}    = 0;
-  let Inst{21}    = 1;        // Writeback
-  let Inst{20}    = 1;
-  let Inst{19-16} = Rn;
-  let Inst{15-0}  = regs;
-}
+def t2LDMIA_RET: t2PseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
+                                                   reglist:$regs, variable_ops),
+                              Size4Bytes, IIC_iLoad_mBr, []>,
+                         RegConstraint<"$Rn = $wb">;
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
 let isPredicable = 1 in

Modified: llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll?rev=134173&r1=134172&r2=134173&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll Thu Jun 30 13:25:42 2011
@@ -13,7 +13,7 @@
 ; CHECK: _ZNKSs7compareERKSs:
 ; CHECK:      it  eq
 ; CHECK-NEXT: subeq{{(.w)?}} r0, r{{[0-9]+}}, r{{[0-9]+}}
-; CHECK-NEXT: ldmia.w sp!,
+; CHECK-NEXT: pop.w
 entry:
   %0 = tail call arm_aapcs_vfpcc  i32 @_ZNKSs4sizeEv(%"struct.std::basic_string,std::allocator >"* %this) ;  [#uses=3]
   %1 = tail call arm_aapcs_vfpcc  i32 @_ZNKSs4sizeEv(%"struct.std::basic_string,std::allocator >"* %__str) ;  [#uses=3]



From baldrick at free.fr  Thu Jun 30 13:30:28 2011
From: baldrick at free.fr (Duncan Sands)
Date: Thu, 30 Jun 2011 20:30:28 +0200
Subject: [llvm-commits] [PATCH]: wrong PPC32 targetdata in llvm
In-Reply-To: <5D3F3545-6E79-4FAC-A475-0A36AD202B3B@apple.com>
References: <20110630153220.GA45513@freebsd.org> <4E0C9882.1070907@free.fr>
	<20110630154738.GA47099@freebsd.org>
	<5D3F3545-6E79-4FAC-A475-0A36AD202B3B@apple.com>
Message-ID: <4E0CC0C4.2020007@free.fr>

On 30/06/11 19:20, John McCall wrote:
>
> On Jun 30, 2011, at 8:47 AM, Roman Divacky wrote:
>
>> On Thu, Jun 30, 2011 at 05:38:42PM +0200, Duncan Sands wrote:
>>> Hi Roman,
>>>
>>>> The definition of targetdata in llvm differs to the one in clang.
>>>> Specifically the ABI alignment of 64bit types on PPC32 is 32 in
>>>> llvm and 64 in llvm. The clang one seems to be the correct one.
>>>
>>> why isn't clang querying llvm to get the target data?
>>
>> I don't know. Clang has target data definition for every arch. It
>> seems wrong to me as well.
>
> There was a decision to try to make Clang independent of the linked-in
> target machines;  the virtue is that Clang can generate IR for an arbitrary
> target without needing an actual backend, which (among other things)
> simplifies cross-platform testing.  The disadvantage, of course, is
> code / information duplication.

As a sanity check, if the given target is linked into LLVM, maybe clang can
detect that and assert that the datalayouts (and other duplicated info) is
the same.

Ciao, Duncan.

From atrick at apple.com  Thu Jun 30 14:02:17 2011
From: atrick at apple.com (Andrew Trick)
Date: Thu, 30 Jun 2011 19:02:17 -0000
Subject: [llvm-commits] [llvm] r134177 - in /llvm/trunk:
 lib/Transforms/Scalar/IndVarSimplify.cpp
 test/Transforms/IndVarSimplify/no-iv-rewrite.ll
Message-ID: <20110630190217.96B3A2A6C12C@llvm.org>

Author: atrick
Date: Thu Jun 30 14:02:17 2011
New Revision: 134177

URL: http://llvm.org/viewvc/llvm-project?rev=134177&view=rev
Log:
indvars -disable-iv-rewrite: handle cloning binary operators that cannot overflow.

Modified:
    llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
    llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll

Modified: llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp?rev=134177&r1=134176&r2=134177&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/IndVarSimplify.cpp Thu Jun 30 14:02:17 2011
@@ -659,9 +659,11 @@
                                                     LHS, RHS,
                                                     NarrowBO->getName());
     Builder.Insert(WideBO);
-    if (NarrowBO->hasNoUnsignedWrap()) WideBO->setHasNoUnsignedWrap();
-    if (NarrowBO->hasNoSignedWrap()) WideBO->setHasNoSignedWrap();
-
+    if (const OverflowingBinaryOperator *OBO =
+        dyn_cast(NarrowBO)) {
+      if (OBO->hasNoUnsignedWrap()) WideBO->setHasNoUnsignedWrap();
+      if (OBO->hasNoSignedWrap()) WideBO->setHasNoSignedWrap();
+    }
     return WideBO;
   }
   llvm_unreachable(0);
@@ -1121,6 +1123,8 @@
       while (!SimpleIVUsers.empty()) {
         Instruction *UseInst, *Operand;
         tie(UseInst, Operand) = SimpleIVUsers.pop_back_val();
+        // Bypass back edges to avoid extra work.
+        if (UseInst == CurrIV) continue;
 
         if (EliminateIVUser(UseInst, Operand)) {
           pushIVUsers(Operand, Simplified, SimpleIVUsers);

Modified: llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll?rev=134177&r1=134176&r2=134177&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll (original)
+++ llvm/trunk/test/Transforms/IndVarSimplify/no-iv-rewrite.ll Thu Jun 30 14:02:17 2011
@@ -160,6 +160,8 @@
 entry:
  br label %loop
 
+; Test inserting a truncate at a phi use.
+;
 ; CHECK: loop:
 ; CHECK: phi i64
 ; CHECK: trunc
@@ -189,14 +191,17 @@
   ret void
 }
 
-; CHECK: loop:
-; CHECK: phi i32
-; CHECK-NOT: phi
-; CHECK: exit:
 define void @identityphi(i32 %limit) nounwind {
 entry:
   br label %loop
 
+; Test an edge case of removing an identity phi that directly feeds
+; back to the loop iv.
+;
+; CHECK: loop:
+; CHECK: phi i32
+; CHECK-NOT: phi
+; CHECK: exit:
 loop:
   %iv = phi i32 [ 0, %entry], [ %iv.next, %control ]
   br i1 undef, label %if.then, label %control
@@ -212,3 +217,32 @@
 exit:
   ret void
 }
+
+define i64 @cloneOr(i32 %limit, i64* %base) nounwind {
+entry:
+  ; ensure that the loop can't overflow
+  %halfLim = ashr i32 %limit, 2
+  br label %loop
+
+; Test cloning an or, which is not an OverflowBinaryOperator.
+;
+; CHECK: loop:
+; CHECK: phi i64
+; CHECK-NOT: sext
+; CHECK: or i64
+; CHECK: exit:
+loop:
+  %iv = phi i32 [ 0, %entry], [ %iv.next, %loop ]
+  %t1 = sext i32 %iv to i64
+  %adr = getelementptr i64* %base, i64 %t1
+  %val = load i64* %adr
+  %t2 = or i32 %iv, 1
+  %t3 = sext i32 %t2 to i64
+  %iv.next = add i32 %iv, 2
+  %cmp = icmp slt i32 %iv.next, %halfLim
+  br i1 %cmp, label %loop, label %exit
+
+exit:
+  %result = and i64 %val, %t3
+  ret i64 %result
+}



From grosbach at apple.com  Thu Jun 30 14:38:02 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 30 Jun 2011 19:38:02 -0000
Subject: [llvm-commits] [llvm] r134178 - in /llvm/trunk:
 lib/Target/ARM/ARMExpandPseudoInsts.cpp lib/Target/ARM/ARMInstrThumb.td
 lib/Target/ARM/ARMInstrThumb2.td utils/TableGen/ARMDecoderEmitter.cpp
Message-ID: <20110630193802.2B1852A6C12C@llvm.org>

Author: grosbach
Date: Thu Jun 30 14:38:01 2011
New Revision: 134178

URL: http://llvm.org/viewvc/llvm-project?rev=134178&view=rev
Log:
Pseudo-ize the Thumb tTPsoft instruction.

It's just a call to a special helper function. Get rid of the T2 variant
entirely, as it's identical to the Thumb1 version.


Modified:
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=134178&r1=134177&r2=134178&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Thu Jun 30 14:38:01 2011
@@ -856,10 +856,11 @@
       MI.eraseFromParent();
       return true;
     }
+    case ARM::tTPsoft:
     case ARM::TPsoft: {
       MachineInstrBuilder MIB =
         BuildMI(MBB, MBBI, MI.getDebugLoc(),
-                TII->get(ARM::BL))
+                TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
         .addExternalSymbol("__aeabi_read_tp", 0);
 
       MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134178&r1=134177&r2=134178&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Jun 30 14:38:01 2011
@@ -1392,13 +1392,11 @@
 //
 
 // __aeabi_read_tp preserves the registers r1-r3.
-let isCall = 1, Defs = [R0, LR], Uses = [SP] in
-def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
-                   "bl\t__aeabi_read_tp",
-                   [(set R0, ARMthread_pointer)]> {
-  // Encoding is 0xf7fffffe.
-  let Inst = 0xf7fffffe;
-}
+// This is a pseudo inst so that we can get the encoding right,
+// complete with fixup for the aeabi_read_tp function.
+let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
+def tTPsoft : tPseudoInst<(outs), (ins), Size4Bytes, IIC_Br,
+                          [(set R0, ARMthread_pointer)]>;
 
 //===----------------------------------------------------------------------===//
 // SJLJ Exception handling intrinsics

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=134178&r1=134177&r2=134178&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Thu Jun 30 14:38:01 2011
@@ -2909,22 +2909,6 @@
 }
 
 //===----------------------------------------------------------------------===//
-// TLS Instructions
-//
-
-// __aeabi_read_tp preserves the registers r1-r3.
-let isCall = 1,
-  Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
-  def t2TPsoft : T2XI<(outs), (ins), IIC_Br,
-                     "bl\t__aeabi_read_tp",
-                     [(set R0, ARMthread_pointer)]> {
-    let Inst{31-27} = 0b11110;
-    let Inst{15-14} = 0b11;
-    let Inst{12} = 1;
-  }
-}
-
-//===----------------------------------------------------------------------===//
 // SJLJ Exception handling intrinsics
 //   eh_sjlj_setjmp() is an instruction sequence to store the return
 //   address and save #0 in R0 for the non-longjmp case.

Modified: llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp?rev=134178&r1=134177&r2=134178&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/ARMDecoderEmitter.cpp Thu Jun 30 14:38:01 2011
@@ -1624,10 +1624,6 @@
     if (Name == "tBX_RET" || Name == "tBX_RET_vararg")
       return false;
 
-    // Ignore the TPsoft (TLS) instructions, which conflict with tBLr9.
-    if (Name == "tTPsoft" || Name == "t2TPsoft")
-      return false;
-
     // Ignore tADR, prefer tADDrPCi.
     if (Name == "tADR")
       return false;



From grosser at fim.uni-passau.de  Thu Jun 30 14:39:10 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 30 Jun 2011 19:39:10 -0000
Subject: [llvm-commits] [polly] r134179 - /polly/trunk/lib/CodeGeneration.cpp
Message-ID: <20110630193910.EE1542A6C12C@llvm.org>

Author: grosser
Date: Thu Jun 30 14:39:10 2011
New Revision: 134179

URL: http://llvm.org/viewvc/llvm-project?rev=134179&view=rev
Log:
CodeGeneration: Adapt to SCEVExpander change

Reported-By: Sebastian Pop 

Modified:
    polly/trunk/lib/CodeGeneration.cpp

Modified: polly/trunk/lib/CodeGeneration.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/CodeGeneration.cpp?rev=134179&r1=134178&r2=134179&view=diff
==============================================================================
--- polly/trunk/lib/CodeGeneration.cpp (original)
+++ polly/trunk/lib/CodeGeneration.cpp Thu Jun 30 14:39:10 2011
@@ -1208,7 +1208,7 @@
   }
 
   void addParameters(const CloogNames *names) {
-    SCEVExpander Rewriter(SE);
+    SCEVExpander Rewriter(SE, "polly");
 
     // Create an instruction that specifies the location where the parameters
     // are expanded.



From grosser at fim.uni-passau.de  Thu Jun 30 14:50:04 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 30 Jun 2011 19:50:04 -0000
Subject: [llvm-commits] [polly] r134180 - in /polly/trunk: CMakeLists.txt
	Makefile.config.in
Message-ID: <20110630195004.B3B982A6C12C@llvm.org>

Author: grosser
Date: Thu Jun 30 14:50:04 2011
New Revision: 134180

URL: http://llvm.org/viewvc/llvm-project?rev=134180&view=rev
Log:
Buildsystem: Add -no-rtti

Build Polly without run time type info (rtti), as otherwise Polly cannot be
loaded into a LLVM that is built without rtti.

Modified:
    polly/trunk/CMakeLists.txt
    polly/trunk/Makefile.config.in

Modified: polly/trunk/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/CMakeLists.txt?rev=134180&r1=134179&r2=134180&view=diff
==============================================================================
--- polly/trunk/CMakeLists.txt (original)
+++ polly/trunk/CMakeLists.txt Thu Jun 30 14:50:04 2011
@@ -53,6 +53,8 @@
   set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-common -Woverloaded-virtual -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings -fno-exceptions -fno-rtti")
 endif ()
 
+set(CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} -fno-exceptions -fno-rtti")
+
 # Add path for custom modules
 set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${POLLY_SOURCE_DIR}/cmake")
 

Modified: polly/trunk/Makefile.config.in
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/Makefile.config.in?rev=134180&r1=134179&r2=134180&view=diff
==============================================================================
--- polly/trunk/Makefile.config.in (original)
+++ polly/trunk/Makefile.config.in Thu Jun 30 14:50:04 2011
@@ -26,6 +26,8 @@
 POLLY_CXXFLAGS := "-fno-common -Woverloaded-virtual -Wno-long-long -Wall -W -Wno-unused-parameter -Wwrite-strings"
 endif
 
+POLLY_CXXFLAGS += "-fno-rtti -fno-exceptions"
+
 # Do us work with scoplib?
 OPENSCOP_FOUND := @openscop_found@
 SCOPLIB_FOUND := @scoplib_found@



From grosser at fim.uni-passau.de  Thu Jun 30 15:01:02 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 30 Jun 2011 20:01:02 -0000
Subject: [llvm-commits] [polly] r134181 - in /polly/trunk:
 include/polly/Support/GICHelper.h lib/ScheduleOptimizer.cpp
 lib/Support/GICHelper.cpp
Message-ID: <20110630200102.301EC2A6C12C@llvm.org>

Author: grosser
Date: Thu Jun 30 15:01:02 2011
New Revision: 134181

URL: http://llvm.org/viewvc/llvm-project?rev=134181&view=rev
Log:
ScheduleOpt: Use band forest to get the schedules

isl introduced a new representation for the schedules it calculates. The new
representation uses a forest of bands and is closer to the structure of the
data as the old interface. Switch to the new interface, as it is nicer to use
and as the old interface will soon be removed from isl.

WARNING: This commit needs a version of isl that is more recent that the one
         included in CLooG. See:
	 http://polly.grosser.es/get_started.html#islTrunk

Modified:
    polly/trunk/include/polly/Support/GICHelper.h
    polly/trunk/lib/ScheduleOptimizer.cpp
    polly/trunk/lib/Support/GICHelper.cpp

Modified: polly/trunk/include/polly/Support/GICHelper.h
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/include/polly/Support/GICHelper.h?rev=134181&r1=134180&r2=134181&view=diff
==============================================================================
--- polly/trunk/include/polly/Support/GICHelper.h (original)
+++ polly/trunk/include/polly/Support/GICHelper.h Thu Jun 30 15:01:02 2011
@@ -21,6 +21,7 @@
 struct isl_union_map;
 struct isl_set;
 struct isl_union_set;
+struct isl_schedule;
 
 namespace polly {
 
@@ -41,6 +42,8 @@
 std::string stringFromIslObj(/*__isl_keep*/ isl_union_map *umap);
 std::string stringFromIslObj(/*__isl_keep*/ isl_set *set);
 std::string stringFromIslObj(/*__isl_keep*/ isl_union_set *uset);
+std::string stringFromIslObj(/*__isl_keep*/ isl_schedule *schedule);
+
 //@}
 } //end namespace polly
 

Modified: polly/trunk/lib/ScheduleOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=134181&r1=134180&r2=134181&view=diff
==============================================================================
--- polly/trunk/lib/ScheduleOptimizer.cpp (original)
+++ polly/trunk/lib/ScheduleOptimizer.cpp Thu Jun 30 15:01:02 2011
@@ -20,6 +20,7 @@
 #include "polly/Cloog.h"
 #include "polly/LinkAllPasses.h"
 
+#include "polly/Support/GICHelper.h"
 #include "polly/Dependences.h"
 #include "polly/ScopInfo.h"
 
@@ -27,6 +28,7 @@
 #include "isl/map.h"
 #include "isl/constraint.h"
 #include "isl/schedule.h"
+#include "isl/band.h"
 
 #define DEBUG_TYPE "polly-optimize-isl"
 #include "llvm/Support/Debug.h"
@@ -91,57 +93,154 @@
   }
 }
 
-// @brief Tile a band.
+// getTileMap - Create a map that describes a n-dimensonal tiling.
 //
-// This function recieves a map that assigns to the instances of a statement
-// an execution time.
+// getTileMap creates a map from a n-dimensional scattering space into an
+// 2*n-dimensional scattering space. The map describes a rectangular tiling.
 //
-// [i_0, i_1, i_2] -> [o_0, o_1, o_2, i_0, i_1, i_2]:
-//   o_0 % 32 = 0 and o_1 % 32 = 0 and o_2 % 32 = 0
-//   and o0 <= i0 <= o0 + 32 and o1 <= i1 <= o1 + 32 and o2 <= i2 <= o2 + 32
-
-static isl_map *tileBand(isl_map *band) {
-  int dimensions = isl_map_n_out(band);
-  int tileSize = 32;
-
-  isl_dim *dim = isl_dim_alloc(isl_map_get_ctx(band), isl_map_n_param(band),
-                               dimensions, dimensions * 3);
-  isl_basic_map *tiledBand = isl_basic_map_universe(isl_dim_copy(dim));
-
-  for (int i = 0; i < dimensions; i++) {
-    isl_constraint *c = isl_equality_alloc(isl_dim_copy(dim));
-    isl_constraint_set_coefficient_si(c, isl_dim_out, i, 1);
-    isl_constraint_set_coefficient_si(c, isl_dim_out, 2 * dimensions + i,
-                                      -tileSize);
-    tiledBand = isl_basic_map_add_constraint(tiledBand, c);
+// Example:
+//   scheduleDimensions = 2, parameterDimensions = 1, tileSize = 32
+//
+//   tileMap := [p0] -> {[s0, s1] -> [t0, t1, s0, s1]:
+//                        t0 % 32 = 0 and t0 <= s0 < t0 + 32 and
+//                        t1 % 32 = 0 and t1 <= s1 < t1 + 32}
+//
+//  Before tiling:
+//
+//  for (i = 0; i < N; i++)
+//    for (j = 0; j < M; j++)
+//	S(i,j)
+//
+//  After tiling:
+//
+//  for (t_i = 0; t_i < N; i+=32)
+//    for (t_j = 0; t_j < M; j+=32)
+//	for (i = t_i; i < min(t_i + 32, N); i++)  | Unknown that N % 32 = 0
+//	  for (j = t_j; j < t_j + 32; j++)        |   Known that M % 32 = 0
+//	    S(i,j)
+//
+static isl_basic_map *getTileMap(isl_ctx *ctx, int scheduleDimensions,
+				 int parameterDimensions, int tileSize = 32) {
+  // We construct
+  //
+  // tileMap := [p0] -> {[s0, s1] -> [t0, t1, p0, p1, a0, a1]:
+  //	                  s0 = a0 * 32 and s0 = p0 and t0 <= p0 < t0 + 32 and
+  //	                  s1 = a1 * 32 and s1 = p1 and t1 <= p1 < t1 + 32}
+  //
+  // and project out the auxilary dimensions a0 and a1.
+  isl_dim *dim = isl_dim_alloc(ctx, parameterDimensions, scheduleDimensions,
+			       scheduleDimensions * 3);
+  isl_basic_map *tileMap = isl_basic_map_universe(isl_dim_copy(dim));
+
+  for (int x = 0; x < scheduleDimensions; x++) {
+    int sX = x;
+    int tX = x;
+    int pX = scheduleDimensions + x;
+    int aX = 2 * scheduleDimensions + x;
+
+    isl_constraint *c;
 
+    // sX = aX * tileSize;
+    c = isl_equality_alloc(isl_dim_copy(dim));
+    isl_constraint_set_coefficient_si(c, isl_dim_out, sX, 1);
+    isl_constraint_set_coefficient_si(c, isl_dim_out, aX, -tileSize);
+    tileMap = isl_basic_map_add_constraint(tileMap, c);
 
+    // pX = sX;
     c = isl_equality_alloc(isl_dim_copy(dim));
-    isl_constraint_set_coefficient_si(c, isl_dim_in, i, -1);
-    isl_constraint_set_coefficient_si(c, isl_dim_out, dimensions + i, 1);
-    tiledBand = isl_basic_map_add_constraint(tiledBand, c);
+    isl_constraint_set_coefficient_si(c, isl_dim_out, pX, 1);
+    isl_constraint_set_coefficient_si(c, isl_dim_in, sX, -1);
+    tileMap = isl_basic_map_add_constraint(tileMap, c);
 
+    // tX <= pX
     c = isl_inequality_alloc(isl_dim_copy(dim));
-    isl_constraint_set_coefficient_si(c, isl_dim_out, i, -1);
-    isl_constraint_set_coefficient_si(c, isl_dim_out, dimensions + i, 1);
-    tiledBand = isl_basic_map_add_constraint(tiledBand, c);
+    isl_constraint_set_coefficient_si(c, isl_dim_out, pX, 1);
+    isl_constraint_set_coefficient_si(c, isl_dim_out, tX, -1);
+    tileMap = isl_basic_map_add_constraint(tileMap, c);
 
+    // pX <= tX + (tileSize - 1)
     c = isl_inequality_alloc(isl_dim_copy(dim));
-    isl_constraint_set_coefficient_si(c, isl_dim_out, i, 1);
-    isl_constraint_set_coefficient_si(c, isl_dim_out, dimensions + i, -1);
+    isl_constraint_set_coefficient_si(c, isl_dim_out, tX, 1);
+    isl_constraint_set_coefficient_si(c, isl_dim_out, pX, -1);
     isl_constraint_set_constant_si(c, tileSize - 1);
-    tiledBand = isl_basic_map_add_constraint(tiledBand, c);
+    tileMap = isl_basic_map_add_constraint(tileMap, c);
   }
 
-  // Project out auxilary dimensions (introduced to ensure 'ii % tileSize = 0')
+  // Project out auxilary dimensions.
   //
-  // The real dimensions are transformed into existentially quantified ones.
-  // This reduces the number of visible scattering dimensions.  Also, Cloog
-  // produces better code, if auxilary dimensions are existentially quantified.
-  tiledBand = isl_basic_map_project_out(tiledBand, isl_dim_out, 2 * dimensions,
-                                        dimensions);
+  // The auxilary dimensions are transformed into existentially quantified ones.
+  // This reduces the number of visible scattering dimensions and allows Cloog
+  // to produces better code.
+  tileMap = isl_basic_map_project_out(tileMap, isl_dim_out,
+				      2 * scheduleDimensions,
+				      scheduleDimensions);
+  isl_dim_free(dim);
+  return tileMap;
+}
+
+isl_union_map *getTiledPartialSchedule(isl_band *band) {
+  isl_union_map *partialSchedule;
+  int scheduleDimensions, parameterDimensions;
+  isl_ctx *ctx;
+  isl_dim *dim;
+  isl_basic_map *tileMap;
+  isl_union_map *tileUnionMap;
+
+  partialSchedule = isl_band_get_partial_schedule(band);
+  ctx = isl_union_map_get_ctx(partialSchedule);
+  dim = isl_union_map_get_dim(partialSchedule);
+  scheduleDimensions = isl_band_n_member(band);
+  parameterDimensions = isl_dim_size(dim, isl_dim_param);
+
+  tileMap = getTileMap(ctx, scheduleDimensions, parameterDimensions);
+  tileUnionMap = isl_union_map_from_map(isl_map_from_basic_map(tileMap));
+
+  partialSchedule = isl_union_map_apply_range(partialSchedule, tileUnionMap);
+
+  isl_dim_free(dim);
+  isl_ctx_free(ctx);
+
+  return partialSchedule;
+}
+
+// tileBandList - Tile all bands contained in a band forest.
+//
+// Recursively walk the band forest and tile all bands in the forest. Return
+// a schedule that describes the tiled scattering.
+static isl_union_map *tileBandList(isl_band_list *blist) {
+  int numBands = isl_band_list_n_band(blist);
+
+  isl_union_map *finalSchedule = 0;
+
+  for (int i = 0; i < numBands; i++) {
+    isl_band *band;
+    isl_union_map *partialSchedule;
+    band = isl_band_list_get_band(blist, i);
+    partialSchedule = getTiledPartialSchedule(band);
+
+    if (isl_band_has_children(band)) {
+      isl_band_list *children = isl_band_get_children(band);
+      isl_union_map *suffixSchedule = tileBandList(children);
+      partialSchedule = isl_union_map_flat_range_product(partialSchedule,
+							 suffixSchedule);
+    }
+
+    if (finalSchedule)
+      isl_union_map_union(finalSchedule, partialSchedule);
+    else
+      finalSchedule = partialSchedule;
+
+    isl_band_free(band);
+  }
 
-  return isl_map_apply_range(band, isl_map_from_basic_map(tiledBand));
+  return finalSchedule;
+}
+
+static isl_union_map *tileSchedule(isl_schedule *schedule) {
+  isl_band_list *blist = isl_schedule_get_band_forest(schedule);
+  isl_union_map *tiledSchedule = tileBandList(blist);
+  isl_band_list_free(blist);
+  return tiledSchedule;
 }
 
 bool ScheduleOptimizer::runOnScop(Scop &S) {
@@ -179,57 +278,36 @@
 
   schedule  = isl_union_set_compute_schedule(domain, validity, proximity);
 
-  // Get the complete schedule.
-  isl_union_map *scheduleMap = isl_schedule_get_map(schedule);
-
   DEBUG(dbgs() << "Computed schedule: ");
-  DEBUG(isl_union_map_dump(scheduleMap));
+  DEBUG(dbgs() << stringFromIslObj(schedule));
   DEBUG(dbgs() << "Individual bands: ");
 
-  // Get individual tileable bands.
-  for (int i = 0; i <  isl_schedule_n_band(schedule); i++) {
-    isl_union_map *band = isl_schedule_get_band(schedule, i);
-
-    DEBUG(dbgs() << "Band " << i << ": ");
-    DEBUG(isl_union_map_dump(band));
-
-    for (Scop::iterator SI = S.begin(), SE = S.end(); SI != SE; ++SI) {
-      ScopStmt *stmt = *SI;
-
-      if (stmt->isFinalRead())
-        continue;
-
-      isl_set *domain = stmt->getDomain();
-      isl_union_map *stmtBand;
-      stmtBand = isl_union_map_intersect_domain(isl_union_map_copy(band),
-                                                isl_union_set_from_set(domain));
-
-      isl_map *sband;
-      isl_union_map_foreach_map(stmtBand, getSingleMap, &sband);
-
-      sband = tileBand(sband);
-      DEBUG(dbgs() << "tiled band: ");
-      DEBUG(isl_map_dump(sband));
-
-      if (i == 0)
-        stmt->setScattering(sband);
-      else {
-        isl_map *scattering = stmt->getScattering();
-        scattering = isl_map_range_product(scattering, sband);
-        scattering = isl_map_flatten(scattering);
-        stmt->setScattering(scattering);
-      }
-    }
+  isl_union_map *tiledSchedule = tileSchedule(schedule);
 
+  for (Scop::iterator SI = S.begin(), SE = S.end(); SI != SE; ++SI) {
+    ScopStmt *stmt = *SI;
+
+    if (stmt->isFinalRead())
+      continue;
+
+    isl_set *domain = stmt->getDomain();
+    isl_union_map *stmtBand;
+    stmtBand = isl_union_map_intersect_domain(isl_union_map_copy(tiledSchedule),
+					      isl_union_set_from_set(domain));
+    isl_map *stmtSchedule;
+    isl_union_map_foreach_map(stmtBand, getSingleMap, &stmtSchedule);
+    stmt->setScattering(stmtSchedule);
   }
 
+  isl_union_map_free(tiledSchedule);
+  isl_schedule_free(schedule);
+
   unsigned maxScatDims = 0;
 
   for (Scop::iterator SI = S.begin(), SE = S.end(); SI != SE; ++SI)
     maxScatDims = std::max(isl_map_n_out((*SI)->getScattering()), maxScatDims);
 
   extendScattering(S, maxScatDims);
-  isl_schedule_free(schedule);
   return false;
 }
 

Modified: polly/trunk/lib/Support/GICHelper.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/Support/GICHelper.cpp?rev=134181&r1=134180&r2=134181&view=diff
==============================================================================
--- polly/trunk/lib/Support/GICHelper.cpp (original)
+++ polly/trunk/lib/Support/GICHelper.cpp Thu Jun 30 15:01:02 2011
@@ -16,6 +16,7 @@
 #include "isl/union_set.h"
 #include "isl/map.h"
 #include "isl/union_map.h"
+#include "isl/schedule.h"
 
 using namespace llvm;
 
@@ -89,3 +90,12 @@
   isl_printer_free(p);
   return string;
 }
+
+std::string polly::stringFromIslObj(/*__isl_keep*/ isl_schedule *schedule) {
+  isl_ctx *ctx = isl_union_map_get_ctx(isl_schedule_get_map(schedule));
+  isl_printer *p = isl_printer_to_str(ctx);
+  isl_printer_print_schedule(p, schedule);
+  std::string string(isl_printer_get_str(p));
+  isl_printer_free(p);
+  return string;
+}



From clattner at apple.com  Thu Jun 30 15:12:50 2011
From: clattner at apple.com (Chris Lattner)
Date: Thu, 30 Jun 2011 13:12:50 -0700
Subject: [llvm-commits] [PATCH]: wrong PPC32 targetdata in llvm
In-Reply-To: <4E0CC0C4.2020007@free.fr>
References: <20110630153220.GA45513@freebsd.org> <4E0C9882.1070907@free.fr>
	<20110630154738.GA47099@freebsd.org>
	<5D3F3545-6E79-4FAC-A475-0A36AD202B3B@apple.com>
	<4E0CC0C4.2020007@free.fr>
Message-ID: 


On Jun 30, 2011, at 11:30 AM, Duncan Sands wrote:

>> There was a decision to try to make Clang independent of the linked-in
>> target machines;  the virtue is that Clang can generate IR for an arbitrary
>> target without needing an actual backend, which (among other things)
>> simplifies cross-platform testing.  The disadvantage, of course, is
>> code / information duplication.
> 
> As a sanity check, if the given target is linked into LLVM, maybe clang can
> detect that and assert that the datalayouts (and other duplicated info) is
> the same.

Yes, this sounds like the right approach to me.

-Chris

From rafael.espindola at gmail.com  Thu Jun 30 15:14:24 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 30 Jun 2011 20:14:24 -0000
Subject: [llvm-commits] [llvm] r134182 - in /llvm/trunk:
 include/llvm/BasicBlock.h lib/Transforms/Utils/Local.cpp
 lib/Transforms/Utils/SimplifyCFG.cpp lib/VMCore/BasicBlock.cpp
 test/Transforms/SimplifyCFG/lifetime.ll
Message-ID: <20110630201424.C983F2A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 30 15:14:24 2011
New Revision: 134182

URL: http://llvm.org/viewvc/llvm-project?rev=134182&view=rev
Log:
Add r134057 back, but splice the predecessor after the successors phi
nodes.

Original message:
Let simplify cfg simplify bb with only debug and lifetime intrinsics.

Added:
    llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll
Modified:
    llvm/trunk/include/llvm/BasicBlock.h
    llvm/trunk/lib/Transforms/Utils/Local.cpp
    llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
    llvm/trunk/lib/VMCore/BasicBlock.cpp

Modified: llvm/trunk/include/llvm/BasicBlock.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/BasicBlock.h?rev=134182&r1=134181&r2=134182&view=diff
==============================================================================
--- llvm/trunk/include/llvm/BasicBlock.h (original)
+++ llvm/trunk/include/llvm/BasicBlock.h Thu Jun 30 15:14:24 2011
@@ -138,6 +138,12 @@
     return const_cast(this)->getFirstNonPHIOrDbg();
   }
 
+  // Same as above, but also skip lifetime intrinsics.
+  Instruction* getFirstNonPHIOrDbgOrLifetime();
+  const Instruction* getFirstNonPHIOrDbgOrLifetime() const {
+    return const_cast(this)->getFirstNonPHIOrDbgOrLifetime();
+  }
+
   /// removeFromParent - This method unlinks 'this' from the containing
   /// function, but does not delete it.
   ///

Modified: llvm/trunk/lib/Transforms/Utils/Local.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/Local.cpp?rev=134182&r1=134181&r2=134182&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/Local.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/Local.cpp Thu Jun 30 15:14:24 2011
@@ -536,9 +536,9 @@
 
 /// TryToSimplifyUncondBranchFromEmptyBlock - BB is known to contain an
 /// unconditional branch, and contains no instructions other than PHI nodes,
-/// potential debug intrinsics and the branch.  If possible, eliminate BB by
-/// rewriting all the predecessors to branch to the successor block and return
-/// true.  If we can't transform, return false.
+/// potential side-effect free intrinsics and the branch.  If possible,
+/// eliminate BB by rewriting all the predecessors to branch to the successor
+/// block and return true.  If we can't transform, return false.
 bool llvm::TryToSimplifyUncondBranchFromEmptyBlock(BasicBlock *BB) {
   assert(BB != &BB->getParent()->getEntryBlock() &&
          "TryToSimplifyUncondBranchFromEmptyBlock called on entry block!");
@@ -613,13 +613,15 @@
     }
   }
   
-  while (PHINode *PN = dyn_cast(&BB->front())) {
-    if (Succ->getSinglePredecessor()) {
-      // BB is the only predecessor of Succ, so Succ will end up with exactly
-      // the same predecessors BB had.
-      Succ->getInstList().splice(Succ->begin(),
-                                 BB->getInstList(), BB->begin());
-    } else {
+  if (Succ->getSinglePredecessor()) {
+    // BB is the only predecessor of Succ, so Succ will end up with exactly
+    // the same predecessors BB had.
+
+    // Copy over any phi, debug or lifetime instruction.
+    BB->getTerminator()->eraseFromParent();
+    Succ->getInstList().splice(Succ->getFirstNonPHI(), BB->getInstList());
+  } else {
+    while (PHINode *PN = dyn_cast(&BB->front())) {
       // We explicitly check for such uses in CanPropagatePredecessorsForPHIs.
       assert(PN->use_empty() && "There shouldn't be any uses here!");
       PN->eraseFromParent();

Modified: llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp?rev=134182&r1=134181&r2=134182&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp (original)
+++ llvm/trunk/lib/Transforms/Utils/SimplifyCFG.cpp Thu Jun 30 15:14:24 2011
@@ -2604,7 +2604,7 @@
   BasicBlock *BB = BI->getParent();
   
   // If the Terminator is the only non-phi instruction, simplify the block.
-  BasicBlock::iterator I = BB->getFirstNonPHIOrDbg();
+  BasicBlock::iterator I = BB->getFirstNonPHIOrDbgOrLifetime();
   if (I->isTerminator() && BB != &BB->getParent()->getEntryBlock() &&
       TryToSimplifyUncondBranchFromEmptyBlock(BB))
     return true;

Modified: llvm/trunk/lib/VMCore/BasicBlock.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/BasicBlock.cpp?rev=134182&r1=134181&r2=134182&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/BasicBlock.cpp (original)
+++ llvm/trunk/lib/VMCore/BasicBlock.cpp Thu Jun 30 15:14:24 2011
@@ -147,6 +147,26 @@
   return &*i;
 }
 
+Instruction* BasicBlock::getFirstNonPHIOrDbgOrLifetime() {
+  // All valid basic blocks should have a terminator,
+  // which is not a PHINode. If we have an invalid basic
+  // block we'll get an assertion failure when dereferencing
+  // a past-the-end iterator.
+  BasicBlock::iterator i = begin();
+  for (;; ++i) {
+    if (isa(i) || isa(i))
+      continue;
+
+    const IntrinsicInst *II = dyn_cast(i);
+    if (!II)
+      break;
+    if (II->getIntrinsicID() != Intrinsic::lifetime_start &&
+        II->getIntrinsicID() != Intrinsic::lifetime_end)
+      break;
+  }
+  return &*i;
+}
+
 void BasicBlock::dropAllReferences() {
   for(iterator I = begin(), E = end(); I != E; ++I)
     I->dropAllReferences();

Added: llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll?rev=134182&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll (added)
+++ llvm/trunk/test/Transforms/SimplifyCFG/lifetime.ll Thu Jun 30 15:14:24 2011
@@ -0,0 +1,29 @@
+; RUN: opt < %s -simplifycfg -S | FileCheck %s
+
+; Test that a lifetime intrinsic doesn't prevent us from simplifying this.
+
+; CHECK: foo
+; CHECK: entry:
+; CHECK-NOT: bb0:
+; CHECK-NOT: bb1:
+; CHECK: ret
+define void @foo(i1 %x) {
+entry:
+  %a = alloca i8
+  call void @llvm.lifetime.start(i64 -1, i8* %a) nounwind
+  br i1 %x, label %bb0, label %bb1
+
+bb0:
+  call void @llvm.lifetime.end(i64 -1, i8* %a) nounwind
+  br label %bb1
+
+bb1:
+  call void @f()
+  ret void
+}
+
+declare void @f()
+
+declare void @llvm.lifetime.start(i64, i8* nocapture) nounwind
+
+declare void @llvm.lifetime.end(i64, i8* nocapture) nounwind



From clattner at apple.com  Thu Jun 30 15:14:37 2011
From: clattner at apple.com (Chris Lattner)
Date: Thu, 30 Jun 2011 13:14:37 -0700
Subject: [llvm-commits] [llvm] r134127 - in /llvm/trunk:
 include/llvm/MC/ include/llvm/Target/ lib/ExecutionEngine/ lib/MC/
 lib/MC/MCDisassembler/ lib/Target/ARM/ lib/Target/ARM/AsmParser/
 lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CBackend/
 lib/Target/CellSPU/ lib/Target/CppBackend/ lib/Target/MBlaze/
 lib/Target/MBlaze/AsmParser/ lib/Target/MSP430/ lib/Target/Mips/
 lib/Target/PTX/ lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/
 lib/Target/X86/ lib/Target/XCore/ tools/llc/ tools/llvm-mc/
 tools/llvm-objdump/ too...
In-Reply-To: <20110630015338.338512A6C12C@llvm.org>
References: <20110630015338.338512A6C12C@llvm.org>
Message-ID: 


On Jun 29, 2011, at 6:53 PM, Evan Cheng wrote:

> Author: evancheng
> Date: Wed Jun 29 20:53:36 2011
> New Revision: 134127
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=134127&view=rev
> Log:
> Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
> be the first encoded as the first feature. It then uses the CPU name to look up
> features / scheduling itineray even though clients know full well the CPU name
> being used to query these properties.
> 
> The fix is to just have the clients explictly pass the CPU name!

Nice!  Please make APIs like the getFeatureBits and getItinerary methods take a StringRef though, instead of const std::string&.

-Chris

From rjmccall at apple.com  Thu Jun 30 15:23:50 2011
From: rjmccall at apple.com (John McCall)
Date: Thu, 30 Jun 2011 13:23:50 -0700
Subject: [llvm-commits] [PATCH]: wrong PPC32 targetdata in llvm
In-Reply-To: 
References: <20110630153220.GA45513@freebsd.org> <4E0C9882.1070907@free.fr>
	<20110630154738.GA47099@freebsd.org>
	<5D3F3545-6E79-4FAC-A475-0A36AD202B3B@apple.com>
	<4E0CC0C4.2020007@free.fr>
	
Message-ID: 

On Jun 30, 2011, at 1:12 PM, Chris Lattner wrote:
> On Jun 30, 2011, at 11:30 AM, Duncan Sands wrote:
>>> There was a decision to try to make Clang independent of the linked-in
>>> target machines;  the virtue is that Clang can generate IR for an arbitrary
>>> target without needing an actual backend, which (among other things)
>>> simplifies cross-platform testing.  The disadvantage, of course, is
>>> code / information duplication.
>> 
>> As a sanity check, if the given target is linked into LLVM, maybe clang can
>> detect that and assert that the datalayouts (and other duplicated info) is
>> the same.
> 
> Yes, this sounds like the right approach to me.

So I whipped up this patch:

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And it fails right away on x86_64-apple-darwin because TM->getTargetData()->getStringRepresentation() is
  "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-f128:128:128-n8:16:32:64"
and TheModule->getDataLayout() is
  "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"

I'm not sure whether the target machine is just being excessively verbose here, or whether this is a real discrepancy.  I would, personally, prefer not to do all the leg work on making these match perfectly. :)

John.

From grosser at fim.uni-passau.de  Thu Jun 30 15:29:13 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 30 Jun 2011 20:29:13 -0000
Subject: [llvm-commits] [polly] r134186 - in /polly/trunk:
	lib/ScheduleOptimizer.cpp utils/pollycc
Message-ID: <20110630202914.042202A6C12C@llvm.org>

Author: grosser
Date: Thu Jun 30 15:29:13 2011
New Revision: 134186

URL: http://llvm.org/viewvc/llvm-project?rev=134186&view=rev
Log:
ScheduleOpt: Add first version of prevectorization

We just strip-mine the innermost dimension by the vector width. This does not
take into account if this dimension is parallel nor if it is constant.

Modified:
    polly/trunk/lib/ScheduleOptimizer.cpp
    polly/trunk/utils/pollycc

Modified: polly/trunk/lib/ScheduleOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=134186&r1=134185&r2=134186&view=diff
==============================================================================
--- polly/trunk/lib/ScheduleOptimizer.cpp (original)
+++ polly/trunk/lib/ScheduleOptimizer.cpp Thu Jun 30 15:29:13 2011
@@ -32,10 +32,17 @@
 
 #define DEBUG_TYPE "polly-optimize-isl"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/CommandLine.h"
 
 using namespace llvm;
 using namespace polly;
 
+static cl::opt
+Prevector("enable-schedule-prevector",
+	  cl::desc("Enable the prevectorization in the scheduler"), cl::Hidden,
+	  cl::value_desc("Prevectorization enabled"),
+	  cl::init(false));
+
 namespace {
 
   class ScheduleOptimizer : public ScopPass {
@@ -203,6 +210,68 @@
   return partialSchedule;
 }
 
+static isl_map *getPrevectorMap(isl_ctx *ctx, int vectorDimension,
+				int scheduleDimensions,
+				int parameterDimensions,
+				int vectorWidth = 4) {
+  assert (0 <= vectorDimension < scheduleDimensions);
+
+  isl_dim *dim = isl_dim_alloc(ctx, parameterDimensions, scheduleDimensions,
+			       scheduleDimensions + 2);
+  isl_basic_map *tilingMap = isl_basic_map_universe(isl_dim_copy(dim));
+
+  isl_constraint *c;
+
+  for (int i = 0; i < vectorDimension; i++) {
+    c = isl_equality_alloc(isl_dim_copy(dim));
+    isl_constraint_set_coefficient_si(c, isl_dim_in, i, -1);
+    isl_constraint_set_coefficient_si(c, isl_dim_out, i, 1);
+    tilingMap = isl_basic_map_add_constraint(tilingMap, c);
+  }
+
+  for (int i = vectorDimension + 1; i < scheduleDimensions; i++) {
+    c = isl_equality_alloc(isl_dim_copy(dim));
+    isl_constraint_set_coefficient_si(c, isl_dim_in, i, -1);
+    isl_constraint_set_coefficient_si(c, isl_dim_out, i, 1);
+    tilingMap = isl_basic_map_add_constraint(tilingMap, c);
+  }
+
+  int stepDimension = scheduleDimensions;
+  int auxilaryDimension = scheduleDimensions + 1;
+
+  c = isl_equality_alloc(isl_dim_copy(dim));
+  isl_constraint_set_coefficient_si(c, isl_dim_out, vectorDimension, 1);
+  isl_constraint_set_coefficient_si(c, isl_dim_out, auxilaryDimension,
+				    -vectorWidth);
+  tilingMap = isl_basic_map_add_constraint(tilingMap, c);
+
+  c = isl_equality_alloc(isl_dim_copy(dim));
+  isl_constraint_set_coefficient_si(c, isl_dim_in, vectorDimension, -1);
+  isl_constraint_set_coefficient_si(c, isl_dim_out, stepDimension, 1);
+  tilingMap = isl_basic_map_add_constraint(tilingMap, c);
+
+  c = isl_inequality_alloc(isl_dim_copy(dim));
+  isl_constraint_set_coefficient_si(c, isl_dim_out, vectorDimension, -1);
+  isl_constraint_set_coefficient_si(c, isl_dim_out, stepDimension, 1);
+  tilingMap = isl_basic_map_add_constraint(tilingMap, c);
+
+  c = isl_inequality_alloc(isl_dim_copy(dim));
+  isl_constraint_set_coefficient_si(c, isl_dim_out, vectorDimension, 1);
+  isl_constraint_set_coefficient_si(c, isl_dim_out, stepDimension, -1);
+  isl_constraint_set_constant_si(c, vectorWidth- 1);
+  tilingMap = isl_basic_map_add_constraint(tilingMap, c);
+
+  // Project out auxilary dimensions (introduced to ensure 'ii % tileSize = 0')
+  //
+  // The real dimensions are transformed into existentially quantified ones.
+  // This reduces the number of visible scattering dimensions.  Also, Cloog
+  // produces better code, if auxilary dimensions are existentially quantified.
+  tilingMap = isl_basic_map_project_out(tilingMap, isl_dim_out,
+					scheduleDimensions + 1, 1);
+
+  return isl_map_from_basic_map(tilingMap);
+}
+
 // tileBandList - Tile all bands contained in a band forest.
 //
 // Recursively walk the band forest and tile all bands in the forest. Return
@@ -223,6 +292,20 @@
       isl_union_map *suffixSchedule = tileBandList(children);
       partialSchedule = isl_union_map_flat_range_product(partialSchedule,
 							 suffixSchedule);
+    } else if (Prevector) {
+      isl_map *tileMap;
+      isl_union_map *tileUnionMap;
+      isl_ctx *ctx;
+      int scheduleDimensions, parameterDimensions;
+
+      ctx = isl_union_map_get_ctx(partialSchedule);
+      scheduleDimensions = isl_band_n_member(band);
+      tileMap = getPrevectorMap(ctx, scheduleDimensions * 2 - 1,
+				scheduleDimensions * 2,
+				parameterDimensions);
+      tileUnionMap = isl_union_map_from_map(tileMap);
+      partialSchedule = isl_union_map_apply_range(partialSchedule,
+						  tileUnionMap);
     }
 
     if (finalSchedule)

Modified: polly/trunk/utils/pollycc
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/utils/pollycc?rev=134186&r1=134185&r2=134186&view=diff
==============================================================================
--- polly/trunk/utils/pollycc (original)
+++ polly/trunk/utils/pollycc Thu Jun 30 15:29:13 2011
@@ -115,7 +115,9 @@
 
     if args.fvector:
       commandLine.append('-enable-polly-vector')
-      commandLine.append('-enable-pluto-prevector')
+      commandLine.append('-enable-schedule-prevector')
+      if (args.ftile or args.fpluto):
+	commandLine.append('-enable-pluto-prevector')
 
     if args.pollyexport:
       commandLine.append('-polly-export-jscop')



From grosser at fim.uni-passau.de  Thu Jun 30 15:29:20 2011
From: grosser at fim.uni-passau.de (Tobias Grosser)
Date: Thu, 30 Jun 2011 20:29:20 -0000
Subject: [llvm-commits] [polly] r134187 -
	/polly/trunk/lib/ScheduleOptimizer.cpp
Message-ID: <20110630202920.8437C2A6C12D@llvm.org>

Author: grosser
Date: Thu Jun 30 15:29:20 2011
New Revision: 134187

URL: http://llvm.org/viewvc/llvm-project?rev=134187&view=rev
Log:
ScheduleOpt: Prevectorize the innermost parallel loop

Only prevectorize loops that are actually parallel and can
be vectorized. Take the innermost loop that is eligible.

Modified:
    polly/trunk/lib/ScheduleOptimizer.cpp

Modified: polly/trunk/lib/ScheduleOptimizer.cpp
URL: http://llvm.org/viewvc/llvm-project/polly/trunk/lib/ScheduleOptimizer.cpp?rev=134187&r1=134186&r2=134187&view=diff
==============================================================================
--- polly/trunk/lib/ScheduleOptimizer.cpp (original)
+++ polly/trunk/lib/ScheduleOptimizer.cpp Thu Jun 30 15:29:20 2011
@@ -299,13 +299,17 @@
       int scheduleDimensions, parameterDimensions;
 
       ctx = isl_union_map_get_ctx(partialSchedule);
-      scheduleDimensions = isl_band_n_member(band);
-      tileMap = getPrevectorMap(ctx, scheduleDimensions * 2 - 1,
-				scheduleDimensions * 2,
-				parameterDimensions);
-      tileUnionMap = isl_union_map_from_map(tileMap);
-      partialSchedule = isl_union_map_apply_range(partialSchedule,
-						  tileUnionMap);
+      for (int i = scheduleDimensions - 1 ;  i >= 0 ; i--) {
+	if (isl_band_member_is_parallel(band, i)) {
+	  tileMap = getPrevectorMap(ctx, scheduleDimensions + i,
+				    scheduleDimensions * 2,
+				    parameterDimensions);
+	  tileUnionMap = isl_union_map_from_map(tileMap);
+	  partialSchedule = isl_union_map_apply_range(partialSchedule,
+						      tileUnionMap);
+	  break;
+	}
+      }
     }
 
     if (finalSchedule)



From mcrosier at apple.com  Thu Jun 30 15:33:41 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Thu, 30 Jun 2011 13:33:41 -0700
Subject: [llvm-commits] [llvm] r134018 - in /llvm/trunk:
 lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86FloatingPoint.cpp
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFPStack.td
 lib/Target/X86/X86RegisterInfo.cpp lib/Target/X86/X86RegisterInfo.td
 test/CodeGen/X86/inline-asm-fpstack.ll
In-Reply-To: <20110628183228.AA6722A6C12C@llvm.org>
References: <20110628183228.AA6722A6C12C@llvm.org>
Message-ID: 

Hi Jakob,
I'm seeing a failure for one of the clang llvm-gcc tests.  Bisect brought me to this revision, which seems very relevant.
gcc.target/i386/pr30848.c (test for excess errors)
mcrosier$ /Users/mcrosier/llvm-clean/install/bin/clang /Users/mcrosier/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c    -ansi -pedantic-errors -fno-show-column -S  -o pr30848.s
fatal error: error in backend: Inline asm fixed outputs must be last on the x87 stack

This one is also failing:
gcc.c-torture/execute/conversion.c execution,  -O0
Looks to be a miscompile, but I didn't have time to dig to deep; I need to get moving an unrelated P1 radar ASAP.

  Chad


On Jun 28, 2011, at 11:32 AM, Jakob Stoklund Olesen wrote:

> Author: stoklund
> Date: Tue Jun 28 13:32:28 2011
> New Revision: 134018
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=134018&view=rev
> Log:
> Clean up the handling of the x87 fp stack to make it more robust.
> 
> Drop the FpMov instructions, use plain COPY instead.
> 
> Drop the FpSET/GET instruction for accessing fixed stack positions.
> Instead use normal COPY to/from ST registers around inline assembly, and
> provide a single new FpPOP_RETVAL instruction that can access the return
> value(s) from a call. This is still necessary since you cannot tell from
> the CALL instruction alone if it returns anything on the FP stack. Teach
> fast isel to use this.
> 
> This provides a much more robust way of handling fixed stack registers -
> we can tolerate arbitrary FP stack instructions inserted around calls
> and inline assembly. Live range splitting could sometimes break x87 code
> by inserting spill code in unfortunate places.
> 
> As a bonus we handle floating point inline assembly correctly now.
> 
> Modified:
>    llvm/trunk/lib/Target/X86/X86FastISel.cpp
>    llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
>    llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
>    llvm/trunk/lib/Target/X86/X86InstrFPStack.td
>    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
>    llvm/trunk/lib/Target/X86/X86RegisterInfo.td
>    llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll
> 
> Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=134018&r1=134017&r2=134018&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Tue Jun 28 13:32:28 2011
> @@ -1848,16 +1848,18 @@
>     // stack, but where we prefer to use the value in xmm registers, copy it
>     // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
>     if ((RVLocs[i].getLocReg() == X86::ST0 ||
> -         RVLocs[i].getLocReg() == X86::ST1) &&
> -        isScalarFPTypeInSSEReg(RVLocs[0].getValVT())) {
> -      CopyVT = MVT::f80;
> +         RVLocs[i].getLocReg() == X86::ST1)) {
> +      if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
> +        CopyVT = MVT::f80;
>       CopyReg = createResultReg(X86::RFP80RegisterClass);
> +      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL),
> +              CopyReg);
> +    } else {
> +      BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
> +              CopyReg).addReg(RVLocs[i].getLocReg());
> +      UsedRegs.push_back(RVLocs[i].getLocReg());
>     }
> 
> -    BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
> -            CopyReg).addReg(RVLocs[i].getLocReg());
> -    UsedRegs.push_back(RVLocs[i].getLocReg());
> -
>     if (CopyVT != RVLocs[i].getValVT()) {
>       // Round the F80 the right size, which also moves to the appropriate xmm
>       // register. This is accomplished by storing the F80 value in memory and
> 
> Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=134018&r1=134017&r2=134018&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Tue Jun 28 13:32:28 2011
> @@ -37,6 +37,7 @@
> #include "llvm/CodeGen/MachineInstrBuilder.h"
> #include "llvm/CodeGen/MachineRegisterInfo.h"
> #include "llvm/CodeGen/Passes.h"
> +#include "llvm/InlineAsm.h"
> #include "llvm/Support/Debug.h"
> #include "llvm/Support/ErrorHandling.h"
> #include "llvm/Support/raw_ostream.h"
> @@ -134,11 +135,36 @@
>     unsigned Stack[8];          // FP Registers in each stack slot...
>     unsigned StackTop;          // The current top of the FP stack.
> 
> +    enum {
> +      NumFPRegs = 16            // Including scratch pseudo-registers.
> +    };
> +
>     // For each live FP register, point to its Stack[] entry.
>     // The first entries correspond to FP0-FP6, the rest are scratch registers
>     // used when we need slightly different live registers than what the
>     // register allocator thinks.
> -    unsigned RegMap[16];
> +    unsigned RegMap[NumFPRegs];
> +
> +    // Pending fixed registers - Inline assembly needs FP registers to appear
> +    // in fixed stack slot positions. This is handled by copying FP registers
> +    // to ST registers before the instruction, and copying back after the
> +    // instruction.
> +    //
> +    // This is modeled with pending ST registers. NumPendingSTs is the number
> +    // of ST registers (ST0-STn) we are tracking. PendingST[n] points to an FP
> +    // register that holds the ST value. The ST registers are not moved into
> +    // place until immediately before the instruction that needs them.
> +    //
> +    // It can happen that we need an ST register to be live when no FP register
> +    // holds the value:
> +    //
> +    //   %ST0 = COPY %FP4
> +    //
> +    // When that happens, we allocate a scratch FP register to hold the ST
> +    // value. That means every register in PendingST must be live.
> +
> +    unsigned NumPendingSTs;
> +    unsigned char PendingST[8];
> 
>     // Set up our stack model to match the incoming registers to MBB.
>     void setupBlockStack();
> @@ -152,13 +178,15 @@
>         dbgs() << " FP" << Stack[i];
>         assert(RegMap[Stack[i]] == i && "Stack[] doesn't match RegMap[]!");
>       }
> +      for (unsigned i = 0; i != NumPendingSTs; ++i)
> +        dbgs() << ", ST" << i << " in FP" << unsigned(PendingST[i]);
>       dbgs() << "\n";
>     }
> 
>     /// getSlot - Return the stack slot number a particular register number is
>     /// in.
>     unsigned getSlot(unsigned RegNo) const {
> -      assert(RegNo < array_lengthof(RegMap) && "Regno out of range!");
> +      assert(RegNo < NumFPRegs && "Regno out of range!");
>       return RegMap[RegNo];
>     }
> 
> @@ -170,12 +198,17 @@
> 
>     /// getScratchReg - Return an FP register that is not currently in use.
>     unsigned getScratchReg() {
> -      for (int i = array_lengthof(RegMap) - 1; i >= 8; --i)
> +      for (int i = NumFPRegs - 1; i >= 8; --i)
>         if (!isLive(i))
>           return i;
>       llvm_unreachable("Ran out of scratch FP registers");
>     }
> 
> +    /// isScratchReg - Returns trus if RegNo is a scratch FP register.
> +    bool isScratchReg(unsigned RegNo) {
> +      return RegNo > 8 && RegNo < NumFPRegs;
> +    }
> +
>     /// getStackEntry - Return the X86::FP register in register ST(i).
>     unsigned getStackEntry(unsigned STi) const {
>       if (STi >= StackTop)
> @@ -191,7 +224,7 @@
> 
>     // pushReg - Push the specified FP register onto the stack.
>     void pushReg(unsigned Reg) {
> -      assert(Reg < array_lengthof(RegMap) && "Register number out of range!");
> +      assert(Reg < NumFPRegs && "Register number out of range!");
>       if (StackTop >= 8)
>         report_fatal_error("Stack overflow!");
>       Stack[StackTop] = Reg;
> @@ -261,7 +294,14 @@
>     void handleCondMovFP(MachineBasicBlock::iterator &I);
>     void handleSpecialFP(MachineBasicBlock::iterator &I);
> 
> -    bool translateCopy(MachineInstr*);
> +    // Check if a COPY instruction is using FP registers.
> +    bool isFPCopy(MachineInstr *MI) {
> +      unsigned DstReg = MI->getOperand(0).getReg();
> +      unsigned SrcReg = MI->getOperand(1).getReg();
> +
> +      return X86::RFP80RegClass.contains(DstReg) ||
> +        X86::RFP80RegClass.contains(SrcReg);
> +    }
>   };
>   char FPS::ID = 0;
> }
> @@ -351,6 +391,7 @@
> bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
>   bool Changed = false;
>   MBB = &BB;
> +  NumPendingSTs = 0;
> 
>   setupBlockStack();
> 
> @@ -362,7 +403,7 @@
>     if (MI->isInlineAsm())
>       FPInstClass = X86II::SpecialFP;
> 
> -    if (MI->isCopy() && translateCopy(MI))
> +    if (MI->isCopy() && isFPCopy(MI))
>       FPInstClass = X86II::SpecialFP;
> 
>     if (FPInstClass == X86II::NotFP)
> @@ -891,7 +932,8 @@
>       continue;
>     // (Reg st0) (OldReg st0) = (Reg OldReg st0)
>     moveToTop(Reg, I);
> -    moveToTop(OldReg, I);
> +    if (FixCount > 0)
> +      moveToTop(OldReg, I);
>   }
>   DEBUG(dumpStack());
> }
> @@ -1249,142 +1291,309 @@
>   MachineInstr *MI = I;
>   switch (MI->getOpcode()) {
>   default: llvm_unreachable("Unknown SpecialFP instruction!");
> -  case X86::FpGET_ST0_32:// Appears immediately after a call returning FP type!
> -  case X86::FpGET_ST0_64:// Appears immediately after a call returning FP type!
> -  case X86::FpGET_ST0_80:// Appears immediately after a call returning FP type!
> -    assert(StackTop == 0 && "Stack should be empty after a call!");
> -    pushReg(getFPReg(MI->getOperand(0)));
> -    break;
> -  case X86::FpGET_ST1_32:// Appears immediately after a call returning FP type!
> -  case X86::FpGET_ST1_64:// Appears immediately after a call returning FP type!
> -  case X86::FpGET_ST1_80:{// Appears immediately after a call returning FP type!
> -    // FpGET_ST1 should occur right after a FpGET_ST0 for a call or inline asm.
> -    // The pattern we expect is:
> -    //  CALL
> -    //  FP1 = FpGET_ST0
> -    //  FP4 = FpGET_ST1
> -    //
> -    // At this point, we've pushed FP1 on the top of stack, so it should be
> -    // present if it isn't dead.  If it was dead, we already emitted a pop to
> -    // remove it from the stack and StackTop = 0.
> -    
> -    // Push FP4 as top of stack next.
> -    pushReg(getFPReg(MI->getOperand(0)));
> +  case TargetOpcode::COPY: {
> +    // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP.
> +    const MachineOperand &MO1 = MI->getOperand(1);
> +    const MachineOperand &MO0 = MI->getOperand(0);
> +    unsigned DstST = MO0.getReg() - X86::ST0;
> +    unsigned SrcST = MO1.getReg() - X86::ST0;
> +    bool KillsSrc = MI->killsRegister(MO1.getReg());
> +
> +    // ST = COPY FP. Set up a pending ST register.
> +    if (DstST < 8) {
> +      unsigned SrcFP = getFPReg(MO1);
> +      assert(isLive(SrcFP) && "Cannot copy dead register");
> +      assert(!MO0.isDead() && "Cannot copy to dead ST register");
> +
> +      // Unallocated STs are marked as the nonexistent FP255.
> +      while (NumPendingSTs <= DstST)
> +        PendingST[NumPendingSTs++] = NumFPRegs;
> +
> +      // STi could still be live from a previous inline asm.
> +      if (isScratchReg(PendingST[DstST])) {
> +        DEBUG(dbgs() << "Clobbering old ST in FP" << unsigned(PendingST[DstST])
> +                     << '\n');
> +        freeStackSlotBefore(MI, PendingST[DstST]);
> +      }
> 
> -    // If StackTop was 0 before we pushed our operand, then ST(0) must have been
> -    // dead.  In this case, the ST(1) value is the only thing that is live, so
> -    // it should be on the TOS (after the pop that was emitted) and is.  Just
> -    // continue in this case.
> -    if (StackTop == 1)
> +      // When the source is killed, allocate a scratch FP register.
> +      if (KillsSrc) {
> +        unsigned Slot = getSlot(SrcFP);
> +        unsigned SR = getScratchReg();
> +        PendingST[DstST] = SR;
> +        Stack[Slot] = SR;
> +        RegMap[SR] = Slot;
> +      } else
> +        PendingST[DstST] = SrcFP;
>       break;
> -    
> -    // Because pushReg just pushed ST(1) as TOS, we now have to swap the two top
> -    // elements so that our accounting is correct.
> -    unsigned RegOnTop = getStackEntry(0);
> -    unsigned RegNo = getStackEntry(1);
> -    
> -    // Swap the slots the regs are in.
> -    std::swap(RegMap[RegNo], RegMap[RegOnTop]);
> -    
> -    // Swap stack slot contents.
> -    if (RegMap[RegOnTop] >= StackTop)
> -      report_fatal_error("Access past stack top!");
> -    std::swap(Stack[RegMap[RegOnTop]], Stack[StackTop-1]);
> -    break;
> -  }
> -  case X86::FpSET_ST0_32:
> -  case X86::FpSET_ST0_64:
> -  case X86::FpSET_ST0_80: {
> -    // FpSET_ST0_80 is generated by copyRegToReg for setting up inline asm
> -    // arguments that use an st constraint. We expect a sequence of
> -    // instructions: Fp_SET_ST0 Fp_SET_ST1? INLINEASM
> -    unsigned Op0 = getFPReg(MI->getOperand(0));
> -
> -    if (!MI->killsRegister(X86::FP0 + Op0)) {
> -      // Duplicate Op0 into a temporary on the stack top.
> -      duplicateToTop(Op0, getScratchReg(), I);
> -    } else {
> -      // Op0 is killed, so just swap it into position.
> -      moveToTop(Op0, I);
>     }
> -    --StackTop;   // "Forget" we have something on the top of stack!
> -    break;
> -  }
> -  case X86::FpSET_ST1_32:
> -  case X86::FpSET_ST1_64:
> -  case X86::FpSET_ST1_80: {
> -    // Set up st(1) for inline asm. We are assuming that st(0) has already been
> -    // set up by FpSET_ST0, and our StackTop is off by one because of it.
> -    unsigned Op0 = getFPReg(MI->getOperand(0));
> -    // Restore the actual StackTop from before Fp_SET_ST0.
> -    // Note we can't handle Fp_SET_ST1 without a preceding Fp_SET_ST0, and we
> -    // are not enforcing the constraint.
> -    ++StackTop;
> -    unsigned RegOnTop = getStackEntry(0); // This reg must remain in st(0).
> -    if (!MI->killsRegister(X86::FP0 + Op0)) {
> -      duplicateToTop(Op0, getScratchReg(), I);
> -      moveToTop(RegOnTop, I);
> -    } else if (getSTReg(Op0) != X86::ST1) {
> -      // We have the wrong value at st(1). Shuffle! Untested!
> -      moveToTop(getStackEntry(1), I);
> -      moveToTop(Op0, I);
> -      moveToTop(RegOnTop, I);
> +
> +    // FP = COPY ST. Extract fixed stack value.
> +    // Any instruction defining ST registers must have assigned them to a
> +    // scratch register.
> +    if (SrcST < 8) {
> +      unsigned DstFP = getFPReg(MO0);
> +      assert(!isLive(DstFP) && "Cannot copy ST to live FP register");
> +      assert(NumPendingSTs > SrcST && "Cannot copy from dead ST register");
> +      unsigned SrcFP = PendingST[SrcST];
> +      assert(isScratchReg(SrcFP) && "Expected ST in a scratch register");
> +      assert(isLive(SrcFP) && "Scratch holding ST is dead");
> +
> +      // DstFP steals the stack slot from SrcFP.
> +      unsigned Slot = getSlot(SrcFP);
> +      Stack[Slot] = DstFP;
> +      RegMap[DstFP] = Slot;
> +
> +      // Always treat the ST as killed.
> +      PendingST[SrcST] = NumFPRegs;
> +      while (NumPendingSTs && PendingST[NumPendingSTs - 1] == NumFPRegs)
> +        --NumPendingSTs;
> +      break;
>     }
> -    assert(StackTop >= 2 && "Too few live registers");
> -    StackTop -= 2; // "Forget" both st(0) and st(1).
> -    break;
> -  }
> -  case X86::MOV_Fp3232:
> -  case X86::MOV_Fp3264:
> -  case X86::MOV_Fp6432:
> -  case X86::MOV_Fp6464: 
> -  case X86::MOV_Fp3280:
> -  case X86::MOV_Fp6480:
> -  case X86::MOV_Fp8032:
> -  case X86::MOV_Fp8064: 
> -  case X86::MOV_Fp8080: {
> -    const MachineOperand &MO1 = MI->getOperand(1);
> -    unsigned SrcReg = getFPReg(MO1);
> 
> -    const MachineOperand &MO0 = MI->getOperand(0);
> -    unsigned DestReg = getFPReg(MO0);
> -    if (MI->killsRegister(X86::FP0+SrcReg)) {
> +    // FP <- FP copy.
> +    unsigned DstFP = getFPReg(MO0);
> +    unsigned SrcFP = getFPReg(MO1);
> +    assert(isLive(SrcFP) && "Cannot copy dead register");
> +    if (KillsSrc) {
>       // If the input operand is killed, we can just change the owner of the
>       // incoming stack slot into the result.
> -      unsigned Slot = getSlot(SrcReg);
> -      assert(Slot < 7 && DestReg < 7 && "FpMOV operands invalid!");
> -      Stack[Slot] = DestReg;
> -      RegMap[DestReg] = Slot;
> -
> +      unsigned Slot = getSlot(SrcFP);
> +      Stack[Slot] = DstFP;
> +      RegMap[DstFP] = Slot;
>     } else {
> -      // For FMOV we just duplicate the specified value to a new stack slot.
> +      // For COPY we just duplicate the specified value to a new stack slot.
>       // This could be made better, but would require substantial changes.
> -      duplicateToTop(SrcReg, DestReg, I);
> +      duplicateToTop(SrcFP, DstFP, I);
>     }
> +    break;
> +  }
> +
> +  case X86::FpPOP_RETVAL: {
> +    // The FpPOP_RETVAL instruction is used after calls that return a value on
> +    // the floating point stack. We cannot model this with ST defs since CALL
> +    // instructions have fixed clobber lists. This instruction is interpreted
> +    // to mean that there is one more live register on the stack than we
> +    // thought.
> +    //
> +    // This means that StackTop does not match the hardware stack between a
> +    // call and the FpPOP_RETVAL instructions.  We do tolerate FP instructions
> +    // between CALL and FpPOP_RETVAL as long as they don't overflow the
> +    // hardware stack.
> +    unsigned DstFP = getFPReg(MI->getOperand(0));
> +
> +    // Move existing stack elements up to reflect reality.
> +    assert(StackTop < 8 && "Stack overflowed before FpPOP_RETVAL");
> +    if (StackTop) {
> +      std::copy_backward(Stack, Stack + StackTop, Stack + StackTop + 1);
> +      for (unsigned i = 0; i != NumFPRegs; ++i)
> +        ++RegMap[i];
>     }
> +    ++StackTop;
> +
> +    // DstFP is the new bottom of the stack.
> +    Stack[0] = DstFP;
> +    RegMap[DstFP] = 0;
> +
> +    // DstFP will be killed by processBasicBlock if this was a dead def.
>     break;
> +  }
> +
>   case TargetOpcode::INLINEASM: {
>     // The inline asm MachineInstr currently only *uses* FP registers for the
>     // 'f' constraint.  These should be turned into the current ST(x) register
> -    // in the machine instr.  Also, any kills should be explicitly popped after
> -    // the inline asm.
> -    unsigned Kills = 0;
> +    // in the machine instr.
> +    //
> +    // There are special rules for x87 inline assembly. The compiler must know
> +    // exactly how many registers are popped and pushed implicitly by the asm.
> +    // Otherwise it is not possible to restore the stack state after the inline
> +    // asm.
> +    //
> +    // There are 3 kinds of input operands:
> +    //
> +    // 1. Popped inputs. These must appear at the stack top in ST0-STn. A
> +    //    popped input operand must be in a fixed stack slot, and it is either
> +    //    tied to an output operand, or in the clobber list. The MI has ST use
> +    //    and def operands for these inputs.
> +    //
> +    // 2. Fixed inputs. These inputs appear in fixed stack slots, but are
> +    //    preserved by the inline asm. The fixed stack slots must be STn-STm
> +    //    following the popped inputs. A fixed input operand cannot be tied to
> +    //    an output or appear in the clobber list. The MI has ST use operands
> +    //    and no defs for these inputs.
> +    //
> +    // 3. Preserved inputs. These inputs use the "f" constraint which is
> +    //    represented as an FP register. The inline asm won't change these
> +    //    stack slots.
> +    //
> +    // Outputs must be in ST registers, FP outputs are not allowed. Clobbered
> +    // registers do not count as output operands. The inline asm changes the
> +    // stack as if it popped all the popped inputs and then pushed all the
> +    // output operands.
> +
> +    // Scan the assembly for ST registers used, defined and clobbered. We can
> +    // only tell clobbers from defs by looking at the asm descriptor.
> +    unsigned STUses = 0, STDefs = 0, STClobbers = 0, STDeadDefs = 0;
> +    unsigned NumOps = 0;
> +    for (unsigned i = InlineAsm::MIOp_FirstOperand, e = MI->getNumOperands();
> +         i != e && MI->getOperand(i).isImm(); i += 1 + NumOps) {
> +      unsigned Flags = MI->getOperand(i).getImm();
> +      NumOps = InlineAsm::getNumOperandRegisters(Flags);
> +      if (NumOps != 1)
> +        continue;
> +      const MachineOperand &MO = MI->getOperand(i + 1);
> +      if (!MO.isReg())
> +        continue;
> +      unsigned STReg = MO.getReg() - X86::ST0;
> +      if (STReg >= 8)
> +        continue;
> +
> +      switch (InlineAsm::getKind(Flags)) {
> +      case InlineAsm::Kind_RegUse:
> +        STUses |= (1u << STReg);
> +        break;
> +      case InlineAsm::Kind_RegDef:
> +      case InlineAsm::Kind_RegDefEarlyClobber:
> +        STDefs |= (1u << STReg);
> +        if (MO.isDead())
> +          STDeadDefs |= (1u << STReg);
> +        break;
> +      case InlineAsm::Kind_Clobber:
> +        STClobbers |= (1u << STReg);
> +        break;
> +      default:
> +        break;
> +      }
> +    }
> +
> +    if (STUses && !isMask_32(STUses))
> +      report_fatal_error("Inline asm fixed inputs"
> +                         " must be last on the x87 stack");
> +    unsigned NumSTUses = CountTrailingOnes_32(STUses);
> +
> +    // Defs must be contiguous from the stack top. ST0-STn.
> +    if (STDefs && !isMask_32(STDefs))
> +      report_fatal_error("Inline asm fixed outputs"
> +                         " must be last on the x87 stack");
> +    unsigned NumSTDefs = CountTrailingOnes_32(STDefs);
> +
> +    // So must the clobbered stack slots. ST0-STm, m >= n.
> +    if (STClobbers && !isMask_32(STDefs | STClobbers))
> +      report_fatal_error("Inline asm clobbers must be last on the x87 stack");
> +
> +    // Popped inputs are the ones that are also clobbered or defined.
> +    unsigned STPopped = STUses & (STDefs | STClobbers);
> +    if (STPopped && !isMask_32(STPopped))
> +      report_fatal_error("Inline asm popped inputs"
> +                         " must be last on the x87 stack");
> +    unsigned NumSTPopped = CountTrailingOnes_32(STPopped);
> +
> +    DEBUG(dbgs() << "Asm uses " << NumSTUses << " fixed regs, pops "
> +                 << NumSTPopped << ", and defines " << NumSTDefs << " regs.\n");
> +
> +    // Scan the instruction for FP uses corresponding to "f" constraints.
> +    // Collect FP registers to kill afer the instruction.
> +    // Always kill all the scratch regs.
> +    unsigned FPKills = ((1u << NumFPRegs) - 1) & ~0xff;
> +    unsigned FPUsed = 0;
>     for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
>       MachineOperand &Op = MI->getOperand(i);
>       if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
>         continue;
> -      assert(Op.isUse() && "Only handle inline asm uses right now");
> -      
> +      if (!Op.isUse())
> +        report_fatal_error("Illegal \"f\" output constraint in inline asm");
>       unsigned FPReg = getFPReg(Op);
> -      Op.setReg(getSTReg(FPReg));
> -      
> +      FPUsed |= 1U << FPReg;
> +
>       // If we kill this operand, make sure to pop it from the stack after the
>       // asm.  We just remember it for now, and pop them all off at the end in
>       // a batch.
>       if (Op.isKill())
> -        Kills |= 1U << FPReg;
> +        FPKills |= 1U << FPReg;
>     }
> 
> +    // The popped inputs will be killed by the instruction, so duplicate them
> +    // if the FP register needs to be live after the instruction, or if it is
> +    // used in the instruction itself. We effectively treat the popped inputs
> +    // as early clobbers.
> +    for (unsigned i = 0; i < NumSTPopped; ++i) {
> +      if ((FPKills & ~FPUsed) & (1u << PendingST[i]))
> +        continue;
> +      unsigned SR = getScratchReg();
> +      duplicateToTop(PendingST[i], SR, I);
> +      DEBUG(dbgs() << "Duplicating ST" << i << " in FP"
> +                   << unsigned(PendingST[i]) << " to avoid clobbering it.\n");
> +      PendingST[i] = SR;
> +    }
> +
> +    // Make sure we have a unique live register for every fixed use. Some of
> +    // them could be undef uses, and we need to emit LD_F0 instructions.
> +    for (unsigned i = 0; i < NumSTUses; ++i) {
> +      if (i < NumPendingSTs && PendingST[i] < NumFPRegs) {
> +        // Check for shared assignments.
> +        for (unsigned j = 0; j < i; ++j) {
> +          if (PendingST[j] != PendingST[i])
> +            continue;
> +          // STi and STj are inn the same register, create a copy.
> +          unsigned SR = getScratchReg();
> +          duplicateToTop(PendingST[i], SR, I);
> +          DEBUG(dbgs() << "Duplicating ST" << i << " in FP"
> +                       << unsigned(PendingST[i])
> +                       << " to avoid collision with ST" << j << '\n');
> +          PendingST[i] = SR;
> +        }
> +        continue;
> +      }
> +      unsigned SR = getScratchReg();
> +      DEBUG(dbgs() << "Emitting LD_F0 for ST" << i << " in FP" << SR << '\n');
> +      BuildMI(*MBB, I, MI->getDebugLoc(), TII->get(X86::LD_F0));
> +      pushReg(SR);
> +      PendingST[i] = SR;
> +      if (NumPendingSTs == i)
> +        ++NumPendingSTs;
> +    }
> +    assert(NumPendingSTs >= NumSTUses && "Fixed registers should be assigned");
> +
> +    // Now we can rearrange the live registers to match what was requested.
> +    shuffleStackTop(PendingST, NumPendingSTs, I);
> +    DEBUG({dbgs() << "Before asm: "; dumpStack();});
> +
> +    // With the stack layout fixed, rewrite the FP registers.
> +    for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
> +      MachineOperand &Op = MI->getOperand(i);
> +      if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
> +        continue;
> +      unsigned FPReg = getFPReg(Op);
> +      Op.setReg(getSTReg(FPReg));
> +    }
> +
> +    // Simulate the inline asm popping its inputs and pushing its outputs.
> +    StackTop -= NumSTPopped;
> +
> +    // Hold the fixed output registers in scratch FP registers. They will be
> +    // transferred to real FP registers by copies.
> +    NumPendingSTs = 0;
> +    for (unsigned i = 0; i < NumSTDefs; ++i) {
> +      unsigned SR = getScratchReg();
> +      pushReg(SR);
> +      FPKills &= ~(1u << SR);
> +    }
> +    for (unsigned i = 0; i < NumSTDefs; ++i)
> +      PendingST[NumPendingSTs++] = getStackEntry(i);
> +    DEBUG({dbgs() << "After asm: "; dumpStack();});
> +
> +    // If any of the ST defs were dead, pop them immediately. Our caller only
> +    // handles dead FP defs.
> +    MachineBasicBlock::iterator InsertPt = MI;
> +    for (unsigned i = 0; STDefs & (1u << i); ++i) {
> +      if (!(STDeadDefs & (1u << i)))
> +        continue;
> +      freeStackSlotAfter(InsertPt, PendingST[i]);
> +      PendingST[i] = NumFPRegs;
> +    }
> +    while (NumPendingSTs && PendingST[NumPendingSTs - 1] == NumFPRegs)
> +      --NumPendingSTs;
> +
>     // If this asm kills any FP registers (is the last use of them) we must
>     // explicitly emit pop instructions for them.  Do this now after the asm has
>     // executed so that the ST(x) numbers are not off (which would happen if we
> @@ -1392,16 +1601,16 @@
>     //
>     // Note: this might be a non-optimal pop sequence.  We might be able to do
>     // better by trying to pop in stack order or something.
> -    MachineBasicBlock::iterator InsertPt = MI;
> -    while (Kills) {
> -      unsigned FPReg = CountTrailingZeros_32(Kills);
> -      freeStackSlotAfter(InsertPt, FPReg);
> -      Kills &= ~(1U << FPReg);
> +    while (FPKills) {
> +      unsigned FPReg = CountTrailingZeros_32(FPKills);
> +      if (isLive(FPReg))
> +        freeStackSlotAfter(InsertPt, FPReg);
> +      FPKills &= ~(1U << FPReg);
>     }
>     // Don't delete the inline asm!
>     return;
>   }
> -      
> +
>   case X86::RET:
>   case X86::RETI:
>     // If RET has an FP register use operand, pass the first one in ST(0) and
> @@ -1499,33 +1708,3 @@
>   } else
>     --I;
> }
> -
> -// Translate a COPY instruction to a pseudo-op that handleSpecialFP understands.
> -bool FPS::translateCopy(MachineInstr *MI) {
> -  unsigned DstReg = MI->getOperand(0).getReg();
> -  unsigned SrcReg = MI->getOperand(1).getReg();
> -
> -  if (DstReg == X86::ST0) {
> -    MI->setDesc(TII->get(X86::FpSET_ST0_80));
> -    MI->RemoveOperand(0);
> -    return true;
> -  }
> -  if (DstReg == X86::ST1) {
> -    MI->setDesc(TII->get(X86::FpSET_ST1_80));
> -    MI->RemoveOperand(0);
> -    return true;
> -  }
> -  if (SrcReg == X86::ST0) {
> -    MI->setDesc(TII->get(X86::FpGET_ST0_80));
> -    return true;
> -  }
> -  if (SrcReg == X86::ST1) {
> -    MI->setDesc(TII->get(X86::FpGET_ST1_80));
> -    return true;
> -  }
> -  if (X86::RFP80RegClass.contains(DstReg, SrcReg)) {
> -    MI->setDesc(TII->get(X86::MOV_Fp8080));
> -    return true;
> -  }
> -  return false;
> -}
> 
> Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=134018&r1=134017&r2=134018&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Tue Jun 28 13:32:28 2011
> @@ -1511,20 +1511,15 @@
>     // If this is a call to a function that returns an fp value on the floating
>     // point stack, we must guarantee the the value is popped from the stack, so
>     // a CopyFromReg is not good enough - the copy instruction may be eliminated
> -    // if the return value is not used. We use the FpGET_ST0 instructions
> +    // if the return value is not used. We use the FpPOP_RETVAL instruction
>     // instead.
>     if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) {
>       // If we prefer to use the value in xmm registers, copy it out as f80 and
>       // use a truncate to move it from fp stack reg to xmm reg.
>       if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80;
> -      bool isST0 = VA.getLocReg() == X86::ST0;
> -      unsigned Opc = 0;
> -      if (CopyVT == MVT::f32) Opc = isST0 ? X86::FpGET_ST0_32:X86::FpGET_ST1_32;
> -      if (CopyVT == MVT::f64) Opc = isST0 ? X86::FpGET_ST0_64:X86::FpGET_ST1_64;
> -      if (CopyVT == MVT::f80) Opc = isST0 ? X86::FpGET_ST0_80:X86::FpGET_ST1_80;
>       SDValue Ops[] = { Chain, InFlag };
> -      Chain = SDValue(DAG.getMachineNode(Opc, dl, CopyVT, MVT::Other, MVT::Glue,
> -                                         Ops, 2), 1);
> +      Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT,
> +                                         MVT::Other, MVT::Glue, Ops, 2), 1);
>       Val = Chain.getValue(0);
> 
>       // Round the f80 to the right size, which also moves it to the appropriate
> 
> Modified: llvm/trunk/lib/Target/X86/X86InstrFPStack.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFPStack.td?rev=134018&r1=134017&r2=134018&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86InstrFPStack.td (original)
> +++ llvm/trunk/lib/Target/X86/X86InstrFPStack.td Tue Jun 28 13:32:28 2011
> @@ -112,31 +112,8 @@
> // a pattern) and the FPI instruction should have emission info (e.g. opcode
> // encoding and asm printing info).
> 
> -// Pseudo Instructions for FP stack return values.
> -def FpGET_ST0_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
> -def FpGET_ST0_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
> -def FpGET_ST0_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(0)
> -
> -// FpGET_ST1* should only be issued *after* an FpGET_ST0* has been issued when
> -// there are two values live out on the stack from a call or inlineasm.  This
> -// magic is handled by the stackifier.  It is not valid to emit FpGET_ST1* and
> -// then FpGET_ST0*.  In addition, it is invalid for any FP-using operations to
> -// occur between them.
> -def FpGET_ST1_32 : FpI_<(outs RFP32:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
> -def FpGET_ST1_64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
> -def FpGET_ST1_80 : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>; // FPR = ST(1)
> -
> -let Defs = [ST0] in {
> -def FpSET_ST0_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(0) = FPR
> -def FpSET_ST0_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(0) = FPR
> -def FpSET_ST0_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(0) = FPR
> -}
> -
> -let Defs = [ST1] in {
> -def FpSET_ST1_32 : FpI_<(outs), (ins RFP32:$src), SpecialFP, []>; // ST(1) = FPR
> -def FpSET_ST1_64 : FpI_<(outs), (ins RFP64:$src), SpecialFP, []>; // ST(1) = FPR
> -def FpSET_ST1_80 : FpI_<(outs), (ins RFP80:$src), SpecialFP, []>; // ST(1) = FPR
> -}
> +// Pseudo Instruction for FP stack return values.
> +def FpPOP_RETVAL : FpI_<(outs RFP80:$dst), (ins), SpecialFP, []>;
> 
> // FpIf32, FpIf64 - Floating Point Pseudo Instruction template.
> // f32 instructions can use SSE1 and are predicated on FPStackf32 == !SSE1.
> @@ -147,19 +124,6 @@
> class FpIf64 pattern> :
>   FpI_, Requires<[FPStackf64]>;
> 
> -// Register copies.  Just copies, the shortening ones do not truncate.
> -let neverHasSideEffects = 1 in {
> -  def MOV_Fp3232 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), SpecialFP, []>; 
> -  def MOV_Fp3264 : FpIf32<(outs RFP64:$dst), (ins RFP32:$src), SpecialFP, []>; 
> -  def MOV_Fp6432 : FpIf32<(outs RFP32:$dst), (ins RFP64:$src), SpecialFP, []>; 
> -  def MOV_Fp6464 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), SpecialFP, []>; 
> -  def MOV_Fp8032 : FpIf32<(outs RFP32:$dst), (ins RFP80:$src), SpecialFP, []>; 
> -  def MOV_Fp3280 : FpIf32<(outs RFP80:$dst), (ins RFP32:$src), SpecialFP, []>; 
> -  def MOV_Fp8064 : FpIf64<(outs RFP64:$dst), (ins RFP80:$src), SpecialFP, []>; 
> -  def MOV_Fp6480 : FpIf64<(outs RFP80:$dst), (ins RFP64:$src), SpecialFP, []>; 
> -  def MOV_Fp8080 : FpI_  <(outs RFP80:$dst), (ins RFP80:$src), SpecialFP, []>; 
> -}
> -
> // Factoring for arithmetic.
> multiclass FPBinary_rr {
> // Register op register -> register
> 
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=134018&r1=134017&r2=134018&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Tue Jun 28 13:32:28 2011
> @@ -500,18 +500,6 @@
>     Reserved.set(X86::BPL);
>   }
> 
> -  // Mark the x87 stack registers as reserved, since they don't behave normally
> -  // with respect to liveness. We don't fully model the effects of x87 stack
> -  // pushes and pops after stackification.
> -  Reserved.set(X86::ST0);
> -  Reserved.set(X86::ST1);
> -  Reserved.set(X86::ST2);
> -  Reserved.set(X86::ST3);
> -  Reserved.set(X86::ST4);
> -  Reserved.set(X86::ST5);
> -  Reserved.set(X86::ST6);
> -  Reserved.set(X86::ST7);
> -
>   // Mark the segment registers as reserved.
>   Reserved.set(X86::CS);
>   Reserved.set(X86::SS);
> 
> Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.td?rev=134018&r1=134017&r2=134018&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/X86/X86RegisterInfo.td (original)
> +++ llvm/trunk/lib/Target/X86/X86RegisterInfo.td Tue Jun 28 13:32:28 2011
> @@ -206,15 +206,22 @@
>   def YMM15: RegisterWithSubRegs<"ymm15", [XMM15]>, DwarfRegAlias;
>   }
> 
> -  // Floating point stack registers
> -  def ST0 : Register<"st(0)">, DwarfRegNum<[33, 12, 11]>;
> -  def ST1 : Register<"st(1)">, DwarfRegNum<[34, 13, 12]>;
> -  def ST2 : Register<"st(2)">, DwarfRegNum<[35, 14, 13]>;
> -  def ST3 : Register<"st(3)">, DwarfRegNum<[36, 15, 14]>;
> -  def ST4 : Register<"st(4)">, DwarfRegNum<[37, 16, 15]>;
> -  def ST5 : Register<"st(5)">, DwarfRegNum<[38, 17, 16]>;
> -  def ST6 : Register<"st(6)">, DwarfRegNum<[39, 18, 17]>;
> -  def ST7 : Register<"st(7)">, DwarfRegNum<[40, 19, 18]>;
> +  class STRegister A> : Register {
> +    let Aliases = A;
> +  }
> +
> +  // Floating point stack registers. These don't map one-to-one to the FP
> +  // pseudo registers, but we still mark them as aliasing FP registers. That
> +  // way both kinds can be live without exceeding the stack depth. ST registers
> +  // are only live around inline assembly.
> +  def ST0 : STRegister<"st(0)", []>, DwarfRegNum<[33, 12, 11]>;
> +  def ST1 : STRegister<"st(1)", [FP6]>, DwarfRegNum<[34, 13, 12]>;
> +  def ST2 : STRegister<"st(2)", [FP5]>, DwarfRegNum<[35, 14, 13]>;
> +  def ST3 : STRegister<"st(3)", [FP4]>, DwarfRegNum<[36, 15, 14]>;
> +  def ST4 : STRegister<"st(4)", [FP3]>, DwarfRegNum<[37, 16, 15]>;
> +  def ST5 : STRegister<"st(5)", [FP2]>, DwarfRegNum<[38, 17, 16]>;
> +  def ST6 : STRegister<"st(6)", [FP1]>, DwarfRegNum<[39, 18, 17]>;
> +  def ST7 : STRegister<"st(7)", [FP0]>, DwarfRegNum<[40, 19, 18]>;
> 
>   // Status flags register
>   def EFLAGS : Register<"flags">;
> 
> Modified: llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll?rev=134018&r1=134017&r2=134018&view=diff
> ==============================================================================
> --- llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll (original)
> +++ llvm/trunk/test/CodeGen/X86/inline-asm-fpstack.ll Tue Jun 28 13:32:28 2011
> @@ -106,6 +106,25 @@
> 	ret void
> }
> 
> +; Passing a non-killed value through asm in {st}.
> +; Make sure it is not duped before.
> +; Second asm kills st(0), so we shouldn't pop anything
> +; CHECK: testPR4185b
> +; CHECK-NOT: fld %st(0)
> +; CHECK: fistl
> +; CHECK-NOT: fstp
> +; CHECK: fistpl
> +; CHECK-NOT: fstp
> +; CHECK: ret
> +; A valid alternative would be to remat the constant pool load before each
> +; inline asm.
> +define void @testPR4185b() {
> +return:
> +	call void asm sideeffect "fistl $0", "{st}"(double 1.000000e+06)
> +	call void asm sideeffect "fistpl $0", "{st},~{st}"(double 1.000000e+06)
> +	ret void
> +}
> +
> ; PR4459
> ; The return value from ceil must be duped before being consumed by asm.
> ; CHECK: testPR4459
> @@ -160,3 +179,153 @@
> 	tail call void asm sideeffect "fistpl $0", "{st},~{st}"(x86_fp80 %5)
> 	ret void
> }
> +
> +; An input argument in a fixed position is implicitly popped by the asm only if
> +; the input argument is tied to an output register, or it is in the clobber list.
> +; The clobber list case is tested above.
> +;
> +; This doesn't implicitly pop the stack:
> +;
> +;   void fist1(long double x, int *p) {
> +;     asm volatile ("fistl %1" : : "t"(x), "m"(*p));
> +;   }
> +;
> +; CHECK: fist1
> +; CHECK: fldt
> +; CHECK: fistl (%e
> +; CHECK: fstp
> +; CHECK: ret
> +define void @fist1(x86_fp80 %x, i32* %p) nounwind ssp {
> +entry:
> +  tail call void asm sideeffect "fistl $1", "{st},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind
> +  ret void
> +}
> +
> +; Here, the input operand is tied to an output which means that is is
> +; implicitly popped (and then the output is implicitly pushed).
> +;
> +;   long double fist2(long double x, int *p) {
> +;     long double y;
> +;     asm ("fistl %1" : "=&t"(y) : "0"(x), "m"(*p) : "memory");
> +;     return y;
> +;   }
> +;
> +; CHECK: fist2
> +; CHECK: fldt
> +; CHECK: fistl (%e
> +; CHECK-NOT: fstp
> +; CHECK: ret
> +define x86_fp80 @fist2(x86_fp80 %x, i32* %p) nounwind ssp {
> +entry:
> +  %0 = tail call x86_fp80 asm "fistl $2", "=&{st},0,*m,~{memory},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, i32* %p) nounwind
> +  ret x86_fp80 %0
> +}
> +
> +; An 'f' constraint is never implicitly popped:
> +;
> +;   void fucomp1(long double x, long double y) {
> +;     asm volatile ("fucomp %1" : : "t"(x), "f"(y) : "st");
> +;   }
> +; CHECK: fucomp1
> +; CHECK: fldt
> +; CHECK: fldt
> +; CHECK: fucomp %st
> +; CHECK: fstp
> +; CHECK-NOT: fstp
> +; CHECK: ret
> +define void @fucomp1(x86_fp80 %x, x86_fp80 %y) nounwind ssp {
> +entry:
> +  tail call void asm sideeffect "fucomp $1", "{st},f,~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind
> +  ret void
> +}
> +
> +; The 'u' constraint is only popped implicitly when clobbered:
> +;
> +;   void fucomp2(long double x, long double y) {
> +;     asm volatile ("fucomp %1" : : "t"(x), "u"(y) : "st");
> +;   }
> +;
> +;   void fucomp3(long double x, long double y) {
> +;     asm volatile ("fucompp %1" : : "t"(x), "u"(y) : "st", "st(1)");
> +;   }
> +;
> +; CHECK: fucomp2
> +; CHECK: fldt
> +; CHECK: fldt
> +; CHECK: fucomp %st(1)
> +; CHECK: fstp
> +; CHECK-NOT: fstp
> +; CHECK: ret
> +;
> +; CHECK: fucomp3
> +; CHECK: fldt
> +; CHECK: fldt
> +; CHECK: fucompp %st(1)
> +; CHECK-NOT: fstp
> +; CHECK: ret
> +define void @fucomp2(x86_fp80 %x, x86_fp80 %y) nounwind ssp {
> +entry:
> +  tail call void asm sideeffect "fucomp $1", "{st},{st(1)},~{st},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind
> +  ret void
> +}
> +define void @fucomp3(x86_fp80 %x, x86_fp80 %y) nounwind ssp {
> +entry:
> +  tail call void asm sideeffect "fucompp $1", "{st},{st(1)},~{st},~{st(1)},~{dirflag},~{fpsr},~{flags}"(x86_fp80 %x, x86_fp80 %y) nounwind
> +  ret void
> +}
> +
> +; One input, two outputs, one dead output.
> +%complex = type { float, float }
> +; CHECK: sincos1
> +; CHECK: flds
> +; CHECK-NOT: fxch
> +; CHECK: sincos
> +; CHECK-NOT: fstp
> +; CHECK: fstp %st(1)
> +; CHECK-NOT: fstp
> +; CHECK: ret
> +define float @sincos1(float %x) nounwind ssp {
> +entry:
> +  %0 = tail call %complex asm "sincos", "={st},={st(1)},0,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind
> +  %asmresult = extractvalue %complex %0, 0
> +  ret float %asmresult
> +}
> +
> +; Same thing, swapped output operands.
> +; CHECK: sincos2
> +; CHECK: flds
> +; CHECK-NOT: fxch
> +; CHECK: sincos
> +; CHECK-NOT: fstp
> +; CHECK: fstp %st(1)
> +; CHECK-NOT: fstp
> +; CHECK: ret
> +define float @sincos2(float %x) nounwind ssp {
> +entry:
> +  %0 = tail call %complex asm "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind
> +  %asmresult = extractvalue %complex %0, 1
> +  ret float %asmresult
> +}
> +
> +; Clobber st(0) after it was live-out/dead from the previous asm.
> +; CHECK: sincos3
> +; Load x, make a copy for the second asm.
> +; CHECK: flds
> +; CHECK: fld %st(0)
> +; CHECK: sincos
> +; Discard dead result in st(0), bring x to the top.
> +; CHECK: fstp %st(0)
> +; CHECK: fxch
> +; x is now in st(0) for the second asm
> +; CHECK: sincos
> +; Discard both results.
> +; CHECK: fstp
> +; CHECK: fstp
> +; CHECK: ret
> +define float @sincos3(float %x) nounwind ssp {
> +entry:
> +  %0 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind
> +  %1 = tail call %complex asm sideeffect "sincos", "={st(1)},={st},1,~{dirflag},~{fpsr},~{flags}"(float %x) nounwind
> +  %asmresult = extractvalue %complex %0, 0
> +  ret float %asmresult
> +}
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From rafael.espindola at gmail.com  Thu Jun 30 16:15:52 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 30 Jun 2011 21:15:52 -0000
Subject: [llvm-commits] [llvm] r134189 - in /llvm/trunk:
 include/llvm/CodeGen/MachineInstr.h lib/CodeGen/InlineSpiller.cpp
Message-ID: <20110630211552.2DB7E2A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 30 16:15:52 2011
New Revision: 134189

URL: http://llvm.org/viewvc/llvm-project?rev=134189&view=rev
Log:
Create a isFullCopy predicate.

Modified:
    llvm/trunk/include/llvm/CodeGen/MachineInstr.h
    llvm/trunk/lib/CodeGen/InlineSpiller.cpp

Modified: llvm/trunk/include/llvm/CodeGen/MachineInstr.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MachineInstr.h?rev=134189&r1=134188&r2=134189&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineInstr.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MachineInstr.h Thu Jun 30 16:15:52 2011
@@ -278,6 +278,9 @@
   bool isCopy() const {
     return getOpcode() == TargetOpcode::COPY;
   }
+  bool isFullCopy() const {
+    return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
+  }
 
   /// isCopyLike - Return true if the instruction behaves like a copy.
   /// This does not include native copy instructions.

Modified: llvm/trunk/lib/CodeGen/InlineSpiller.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/InlineSpiller.cpp?rev=134189&r1=134188&r2=134189&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/InlineSpiller.cpp (original)
+++ llvm/trunk/lib/CodeGen/InlineSpiller.cpp Thu Jun 30 16:15:52 2011
@@ -180,11 +180,7 @@
 /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
 /// otherwise return 0.
 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) {
-  if (!MI->isCopy())
-    return 0;
-  if (MI->getOperand(0).getSubReg() != 0)
-    return 0;
-  if (MI->getOperand(1).getSubReg() != 0)
+  if (!MI->isFullCopy())
     return 0;
   if (MI->getOperand(0).getReg() == Reg)
       return MI->getOperand(1).getReg();



From isanbard at gmail.com  Thu Jun 30 16:25:51 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 30 Jun 2011 21:25:51 -0000
Subject: [llvm-commits] [llvm] r134191 - /llvm/trunk/lib/MC/MCDwarf.cpp
Message-ID: <20110630212551.CF3C92A6C12C@llvm.org>

Author: void
Date: Thu Jun 30 16:25:51 2011
New Revision: 134191

URL: http://llvm.org/viewvc/llvm-project?rev=134191&view=rev
Log:
Add comments to the ASM output to help understand the compact unwind and CIE tables.

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=134191&r1=134190&r2=134191&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Thu Jun 30 16:25:51 2011
@@ -526,6 +526,40 @@
     void EmitCFIInstruction(MCStreamer &Streamer,
                             const MCCFIInstruction &Instr);
   };
+
+} // end anonymous namespace
+
+static void EmitEncodingByte(MCStreamer &Streamer, unsigned Encoding,
+                             StringRef Prefix) {
+  if (Streamer.isVerboseAsm()) {
+    const char *EncStr = 0;
+    switch (Encoding) {
+    default: EncStr = "";
+    case dwarf::DW_EH_PE_absptr: EncStr = "absptr";
+    case dwarf::DW_EH_PE_omit:   EncStr = "omit";
+    case dwarf::DW_EH_PE_pcrel:  EncStr = "pcrel";
+    case dwarf::DW_EH_PE_udata4: EncStr = "udata4";
+    case dwarf::DW_EH_PE_udata8: EncStr = "udata8";
+    case dwarf::DW_EH_PE_sdata4: EncStr = "sdata4";
+    case dwarf::DW_EH_PE_sdata8: EncStr = "sdata8";
+    case dwarf::DW_EH_PE_pcrel |dwarf::DW_EH_PE_udata4: EncStr = "pcrel udata4";
+    case dwarf::DW_EH_PE_pcrel |dwarf::DW_EH_PE_sdata4: EncStr = "pcrel sdata4";
+    case dwarf::DW_EH_PE_pcrel |dwarf::DW_EH_PE_udata8: EncStr = "pcrel udata8";
+    case dwarf::DW_EH_PE_pcrel |dwarf::DW_EH_PE_sdata8: EncStr = "pcrel sdata8";
+    case dwarf::DW_EH_PE_indirect |dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_udata4:
+      EncStr = "indirect pcrel udata4";
+    case dwarf::DW_EH_PE_indirect |dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_sdata4:
+      EncStr = "indirect pcrel sdata4";
+    case dwarf::DW_EH_PE_indirect |dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_udata8:
+      EncStr = "indirect pcrel udata8";
+    case dwarf::DW_EH_PE_indirect |dwarf::DW_EH_PE_pcrel|dwarf::DW_EH_PE_sdata8:
+      EncStr = "indirect pcrel sdata8";
+    }
+
+    Streamer.AddComment(Twine(Prefix) + " = " + EncStr);
+  }
+
+  Streamer.EmitIntValue(Encoding, 1);
 }
 
 void FrameEmitterImpl::EmitCFIInstruction(MCStreamer &Streamer,
@@ -635,7 +669,7 @@
 #else
   MCContext &Context = Streamer.getContext();
   const TargetAsmInfo &TAI = Context.getTargetAsmInfo();
-  Streamer.SwitchSection(TAI.getCompactUnwindSection());
+  bool VerboseAsm = Streamer.isVerboseAsm();
 
   // range-start range-length  compact-unwind-enc personality-func   lsda
   //  _foo       LfooEnd-_foo  0x00000023          0                 0
@@ -659,25 +693,31 @@
   //   .quad __gxx_personality
   //   .quad except_tab1
 
+  Streamer.SwitchSection(TAI.getCompactUnwindSection());
+
   // Range Start
   unsigned FDEEncoding = TAI.getFDEEncoding(UsingCFI);
   unsigned Size = getSizeForEncoding(Streamer, FDEEncoding);
+  if (VerboseAsm) Streamer.AddComment("Range Start");
   Streamer.EmitSymbolValue(Frame.Function, Size);
 
   // Range Length
   const MCExpr *Range = MakeStartMinusEndExpr(Streamer, *Frame.Begin,
                                               *Frame.End, 0);
+  if (VerboseAsm) Streamer.AddComment("Range Length");
   Streamer.EmitAbsValue(Range, 4);
 
   // FIXME:
   // Compact Encoding
+  const std::vector &Moves = TAI.getInitialFrameState();
   uint32_t Encoding = 0;
   Size = getSizeForEncoding(Streamer, dwarf::DW_EH_PE_udata4);
+  if (VerboseAsm) Streamer.AddComment("Compact Unwind Encoding");
   Streamer.EmitIntValue(Encoding, Size);
 
-
   // Personality Function
   Size = getSizeForEncoding(Streamer, Frame.PersonalityEncoding);
+  if (VerboseAsm) Streamer.AddComment("Personality Function");
   if (Frame.Personality)
     Streamer.EmitSymbolValue(Frame.Personality, Size);
   else
@@ -685,6 +725,7 @@
 
   // LSDA
   Size = getSizeForEncoding(Streamer, Frame.LsdaEncoding);
+  if (VerboseAsm) Streamer.AddComment("LSDA");
   if (Frame.Lsda)
     Streamer.EmitSymbolValue(Frame.Lsda, Size);
   else
@@ -701,6 +742,7 @@
                                           unsigned lsdaEncoding) {
   MCContext &context = streamer.getContext();
   const TargetAsmInfo &asmInfo = context.getTargetAsmInfo();
+  bool verboseAsm = streamer.isVerboseAsm();
 
   MCSymbol *sectionStart;
   if (asmInfo.isFunctionEHFrameSymbolPrivate() || !IsEH)
@@ -708,6 +750,7 @@
   else
     sectionStart = context.GetOrCreateSymbol(Twine("EH_frame") + Twine(CIENum));
 
+  streamer.EmitLabel(sectionStart);
   CIENum++;
 
   MCSymbol *sectionEnd = streamer.getContext().CreateTempSymbol();
@@ -715,19 +758,22 @@
   // Length
   const MCExpr *Length = MakeStartMinusEndExpr(streamer, *sectionStart,
                                                *sectionEnd, 4);
-  streamer.EmitLabel(sectionStart);
+  if (verboseAsm) streamer.AddComment("CIE Length");
   streamer.EmitAbsValue(Length, 4);
 
   // CIE ID
   unsigned CIE_ID = IsEH ? 0 : -1;
+  if (verboseAsm) streamer.AddComment("CIE ID Tag");
   streamer.EmitIntValue(CIE_ID, 4);
 
   // Version
+  if (verboseAsm) streamer.AddComment("DW_CIE_VERSION");
   streamer.EmitIntValue(dwarf::DW_CIE_VERSION, 1);
 
   // Augmentation String
   SmallString<8> Augmentation;
   if (IsEH) {
+    if (verboseAsm) streamer.AddComment("CIE Augmentation");
     Augmentation += "z";
     if (personality)
       Augmentation += "P";
@@ -739,12 +785,15 @@
   streamer.EmitIntValue(0, 1);
 
   // Code Alignment Factor
+  if (verboseAsm) streamer.AddComment("CIE Code Alignment Factor");
   streamer.EmitULEB128IntValue(1);
 
   // Data Alignment Factor
+  if (verboseAsm) streamer.AddComment("CIE Data Alignment Factor");
   streamer.EmitSLEB128IntValue(getDataAlignmentFactor(streamer));
 
   // Return Address Register
+  if (verboseAsm) streamer.AddComment("CIE Return Address Column");
   streamer.EmitULEB128IntValue(asmInfo.getDwarfRARegNum(true));
 
   // Augmentation Data Length (optional)
@@ -762,19 +811,25 @@
     // Encoding of the FDE pointers
     augmentationLength += 1;
 
+    if (verboseAsm) streamer.AddComment("Augmentation Size");
     streamer.EmitULEB128IntValue(augmentationLength);
 
     // Augmentation Data (optional)
     if (personality) {
       // Personality Encoding
-      streamer.EmitIntValue(personalityEncoding, 1);
+      EmitEncodingByte(streamer, personalityEncoding,
+                       "Personality Encoding");
       // Personality
+      if (verboseAsm) streamer.AddComment("Personality");
       EmitPersonality(streamer, *personality, personalityEncoding);
     }
+
     if (lsda)
-      streamer.EmitIntValue(lsdaEncoding, 1); // LSDA Encoding
+      EmitEncodingByte(streamer, lsdaEncoding, "LSDA Encoding");
+
     // Encoding of the FDE pointers
-    streamer.EmitIntValue(asmInfo.getFDEEncoding(UsingCFI), 1);
+    EmitEncodingByte(streamer, asmInfo.getFDEEncoding(UsingCFI),
+                     "FDE Encoding");
   }
 
   // Initial Instructions



From stoklund at 2pi.dk  Thu Jun 30 16:30:30 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 30 Jun 2011 21:30:30 -0000
Subject: [llvm-commits] [llvm] r134193 -
	/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
Message-ID: <20110630213030.630872A6C12C@llvm.org>

Author: stoklund
Date: Thu Jun 30 16:30:30 2011
New Revision: 134193

URL: http://llvm.org/viewvc/llvm-project?rev=134193&view=rev
Log:
Tweak error messages to match GCC. Should fix gcc.target/i386/pr30848.c

Modified:
    llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp

Modified: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp?rev=134193&r1=134192&r2=134193&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp Thu Jun 30 16:30:30 2011
@@ -1467,13 +1467,13 @@
     }
 
     if (STUses && !isMask_32(STUses))
-      report_fatal_error("Inline asm fixed inputs"
+      report_fatal_error("Inline asm fixed input regs"
                          " must be last on the x87 stack");
     unsigned NumSTUses = CountTrailingOnes_32(STUses);
 
     // Defs must be contiguous from the stack top. ST0-STn.
     if (STDefs && !isMask_32(STDefs))
-      report_fatal_error("Inline asm fixed outputs"
+      report_fatal_error("Inline asm output regs"
                          " must be last on the x87 stack");
     unsigned NumSTDefs = CountTrailingOnes_32(STDefs);
 
@@ -1484,7 +1484,7 @@
     // Popped inputs are the ones that are also clobbered or defined.
     unsigned STPopped = STUses & (STDefs | STClobbers);
     if (STPopped && !isMask_32(STPopped))
-      report_fatal_error("Inline asm popped inputs"
+      report_fatal_error("Inline asm implicitly popped regs"
                          " must be last on the x87 stack");
     unsigned NumSTPopped = CountTrailingOnes_32(STPopped);
 



From rafael.espindola at gmail.com  Thu Jun 30 16:36:53 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Thu, 30 Jun 2011 17:36:53 -0400
Subject: [llvm-commits] [patch] Improve register coalescing
In-Reply-To: <5C5CA408-CEC6-49E2-88CF-55C315AF3D97@2pi.dk>
References: <4E0B9D31.3020101@gmail.com>
	<5C5CA408-CEC6-49E2-88CF-55C315AF3D97@2pi.dk>
Message-ID: <4E0CEC75.40303@gmail.com>

An updated copy is attached.

> Would it be possible to do more complete value-based checking? For
> example, you don't handle this:
>
> X = Y A = X B = Y

but it doesn't handle this, we would have to coalesce X and Y first 
(which might fail).

The real solution I think would be to turn the coalescing algorithm
upside down: instead of trying to merge registers one pair at a time,
start by assuming that every copy related register can be merged and
try to show it cannot.

In the above example, A, B, X, Y would be be in one set initially.
If we then show that X and Y cannot merge, we would have the sets
{A, B, X} and {A, B, Y}. If no further conflicts exist, we can choose
to merge A, B and X or A, B and Y.

An intermediate option is to look for copy chains. From

A = X
B = Y

we follow the definitions of X and Y until we find a non copy. It
would work on the above example, but fail in

BB1:
X = B
Y = A

BB2:
A = X
B = Y

A and B can be merged if X and Y can be merged and X and Y can be
merge if A and B can be merged.

> Thanks for working on this!

My pleasure :-)

> /jakob

Cheers,
Rafael
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From isanbard at gmail.com  Thu Jun 30 16:45:12 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 30 Jun 2011 21:45:12 -0000
Subject: [llvm-commits] [llvm] r134194 - /llvm/trunk/lib/MC/MCDwarf.cpp
Message-ID: <20110630214512.C84B62A6C12C@llvm.org>

Author: void
Date: Thu Jun 30 16:45:12 2011
New Revision: 134194

URL: http://llvm.org/viewvc/llvm-project?rev=134194&view=rev
Log:
Add more comments to the ASM output for the CIE's "moves".

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=134194&r1=134193&r2=134194&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Thu Jun 30 16:45:12 2011
@@ -565,6 +565,7 @@
 void FrameEmitterImpl::EmitCFIInstruction(MCStreamer &Streamer,
                                           const MCCFIInstruction &Instr) {
   int dataAlignmentFactor = getDataAlignmentFactor(Streamer);
+  bool VerboseAsm = Streamer.isVerboseAsm();
 
   switch (Instr.getOperation()) {
   case MCCFIInstruction::Move:
@@ -576,9 +577,13 @@
     // If advancing cfa.
     if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) {
       if (Src.getReg() == MachineLocation::VirtualFP) {
+        if (VerboseAsm) Streamer.AddComment("DW_CFA_def_cfa_offset");
         Streamer.EmitIntValue(dwarf::DW_CFA_def_cfa_offset, 1);
       } else {
+        if (VerboseAsm) Streamer.AddComment("DW_CFA_def_cfa");
         Streamer.EmitIntValue(dwarf::DW_CFA_def_cfa, 1);
+        if (VerboseAsm) Streamer.AddComment(Twine("Reg ") +
+                                            Twine(Src.getReg()));
         Streamer.EmitULEB128IntValue(Src.getReg());
       }
 
@@ -587,47 +592,61 @@
       else
         CFAOffset = -Src.getOffset();
 
+      if (VerboseAsm) Streamer.AddComment(Twine("Offset " + Twine(CFAOffset)));
       Streamer.EmitULEB128IntValue(CFAOffset);
       return;
     }
 
     if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) {
       assert(Dst.isReg() && "Machine move not supported yet.");
+      if (VerboseAsm) Streamer.AddComment("DW_CFA_def_cfa_register");
       Streamer.EmitIntValue(dwarf::DW_CFA_def_cfa_register, 1);
+      if (VerboseAsm) Streamer.AddComment(Twine("Reg ") + Twine(Dst.getReg()));
       Streamer.EmitULEB128IntValue(Dst.getReg());
       return;
     }
 
     unsigned Reg = Src.getReg();
-
     int Offset = Dst.getOffset();
     if (IsRelative)
       Offset -= CFAOffset;
     Offset = Offset / dataAlignmentFactor;
 
     if (Offset < 0) {
+      if (VerboseAsm) Streamer.AddComment("DW_CFA_offset_extended_sf");
       Streamer.EmitIntValue(dwarf::DW_CFA_offset_extended_sf, 1);
+      if (VerboseAsm) Streamer.AddComment(Twine("Reg ") + Twine(Reg));
       Streamer.EmitULEB128IntValue(Reg);
+      if (VerboseAsm) Streamer.AddComment(Twine("Offset ") + Twine(Offset));
       Streamer.EmitSLEB128IntValue(Offset);
     } else if (Reg < 64) {
+      if (VerboseAsm) Streamer.AddComment("DW_CFA_offset");
       Streamer.EmitIntValue(dwarf::DW_CFA_offset + Reg, 1);
+      if (VerboseAsm) Streamer.AddComment(Twine("Offset ") + Twine(Offset));
       Streamer.EmitULEB128IntValue(Offset);
     } else {
+      if (VerboseAsm) Streamer.AddComment("DW_CFA_offset_extended");
       Streamer.EmitIntValue(dwarf::DW_CFA_offset_extended, 1);
+      if (VerboseAsm) Streamer.AddComment(Twine("Reg ") + Twine(Reg));
       Streamer.EmitULEB128IntValue(Reg);
+      if (VerboseAsm) Streamer.AddComment(Twine("Offset ") + Twine(Offset));
       Streamer.EmitULEB128IntValue(Offset);
     }
     return;
   }
   case MCCFIInstruction::Remember:
+    if (VerboseAsm) Streamer.AddComment("DW_CFA_remember_state");
     Streamer.EmitIntValue(dwarf::DW_CFA_remember_state, 1);
     return;
   case MCCFIInstruction::Restore:
+    if (VerboseAsm) Streamer.AddComment("DW_CFA_restore_state");
     Streamer.EmitIntValue(dwarf::DW_CFA_restore_state, 1);
     return;
   case MCCFIInstruction::SameValue: {
     unsigned Reg = Instr.getDestination().getReg();
+    if (VerboseAsm) Streamer.AddComment("DW_CFA_same_value");
     Streamer.EmitIntValue(dwarf::DW_CFA_same_value, 1);
+    if (VerboseAsm) Streamer.AddComment(Twine("Reg ") + Twine(Reg));
     Streamer.EmitULEB128IntValue(Reg);
     return;
   }



From stoklund at 2pi.dk  Thu Jun 30 16:47:45 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 30 Jun 2011 14:47:45 -0700
Subject: [llvm-commits] [patch] Improve register coalescing
In-Reply-To: <4E0CEC75.40303@gmail.com>
References: <4E0B9D31.3020101@gmail.com>
	<5C5CA408-CEC6-49E2-88CF-55C315AF3D97@2pi.dk>
	<4E0CEC75.40303@gmail.com>
Message-ID: 


On Jun 30, 2011, at 2:36 PM, Rafael ?vila de Esp?ndola wrote:

> An updated copy is attached.

LGTM!

>> Would it be possible to do more complete value-based checking? For
>> example, you don't handle this:
>> 
>> X = Y A = X B = Y
> 
> but it doesn't handle this, we would have to coalesce X and Y first (which might fail).

That's OK, this is a good start. The most common case is probably phi-elim fallout anyway.

> The real solution I think would be to turn the coalescing algorithm
> upside down: instead of trying to merge registers one pair at a time,
> start by assuming that every copy related register can be merged and
> try to show it cannot.

That sounds hard to get right.

> In the above example, A, B, X, Y would be be in one set initially.
> If we then show that X and Y cannot merge, we would have the sets
> {A, B, X} and {A, B, Y}. If no further conflicts exist, we can choose
> to merge A, B and X or A, B and Y.
> 
> An intermediate option is to look for copy chains. From
> 
> A = X
> B = Y
> 
> we follow the definitions of X and Y until we find a non copy. It
> would work on the above example, but fail in
> 
> BB1:
> X = B
> Y = A
> 
> BB2:
> A = X
> B = Y
> 
> A and B can be merged if X and Y can be merged and X and Y can be
> merge if A and B can be merged.

I think we already detect and remove this kind of PHI loops?

/jakob



From isanbard at gmail.com  Thu Jun 30 17:02:20 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 30 Jun 2011 22:02:20 -0000
Subject: [llvm-commits] [llvm] r134196 - /llvm/trunk/lib/MC/MCDwarf.cpp
Message-ID: <20110630220220.F2EBF2A6C12C@llvm.org>

Author: void
Date: Thu Jun 30 17:02:20 2011
New Revision: 134196

URL: http://llvm.org/viewvc/llvm-project?rev=134196&view=rev
Log:
Add comments to the FDE.

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=134196&r1=134195&r2=134196&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Thu Jun 30 17:02:20 2011
@@ -460,13 +460,14 @@
 }
 
 static void EmitSymbol(MCStreamer &streamer, const MCSymbol &symbol,
-                       unsigned symbolEncoding) {
+                       unsigned symbolEncoding, const char *comment = 0) {
   MCContext &context = streamer.getContext();
   const MCAsmInfo &asmInfo = context.getAsmInfo();
   const MCExpr *v = asmInfo.getExprForFDESymbol(&symbol,
                                                 symbolEncoding,
                                                 streamer);
   unsigned size = getSizeForEncoding(streamer, symbolEncoding);
+  if (streamer.isVerboseAsm() && comment) streamer.AddComment(comment);
   streamer.EmitAbsValue(v, size);
 }
 
@@ -882,16 +883,18 @@
   MCSymbol *fdeStart = context.CreateTempSymbol();
   MCSymbol *fdeEnd = context.CreateTempSymbol();
   const TargetAsmInfo &TAsmInfo = context.getTargetAsmInfo();
+  bool verboseAsm = streamer.isVerboseAsm();
 
   if (!TAsmInfo.isFunctionEHFrameSymbolPrivate() && IsEH) {
-    MCSymbol *EHSym = context.GetOrCreateSymbol(
-      frame.Function->getName() + Twine(".eh"));
+    MCSymbol *EHSym =
+      context.GetOrCreateSymbol(frame.Function->getName() + Twine(".eh"));
     streamer.EmitEHSymAttributes(frame.Function, EHSym);
     streamer.EmitLabel(EHSym);
   }
 
   // Length
   const MCExpr *Length = MakeStartMinusEndExpr(streamer, *fdeStart, *fdeEnd, 0);
+  if (verboseAsm) streamer.AddComment("FDE Length");
   streamer.EmitAbsValue(Length, 4);
 
   streamer.EmitLabel(fdeStart);
@@ -901,6 +904,7 @@
   if (IsEH) {
     const MCExpr *offset = MakeStartMinusEndExpr(streamer, cieStart, *fdeStart,
                                                  0);
+    if (verboseAsm) streamer.AddComment("FDE CIE Offset");
     streamer.EmitAbsValue(offset, 4);
   } else if (!asmInfo.doesDwarfRequireRelocationForSectionOffset()) {
     const MCExpr *offset = MakeStartMinusEndExpr(streamer, *SectionStart,
@@ -909,6 +913,7 @@
   } else {
     streamer.EmitSymbolValue(&cieStart, 4);
   }
+
   unsigned fdeEncoding = TAsmInfo.getFDEEncoding(UsingCFI);
   unsigned size = getSizeForEncoding(streamer, fdeEncoding);
 
@@ -916,11 +921,12 @@
   unsigned PCBeginEncoding = IsEH ? fdeEncoding :
     (unsigned)dwarf::DW_EH_PE_absptr;
   unsigned PCBeginSize = getSizeForEncoding(streamer, PCBeginEncoding);
-  EmitSymbol(streamer, *frame.Begin, PCBeginEncoding);
+  EmitSymbol(streamer, *frame.Begin, PCBeginEncoding, "FDE initial location");
 
   // PC Range
   const MCExpr *Range = MakeStartMinusEndExpr(streamer, *frame.Begin,
                                               *frame.End, 0);
+  if (verboseAsm) streamer.AddComment("FDE address range");
   streamer.EmitAbsValue(Range, size);
 
   if (IsEH) {
@@ -930,11 +936,13 @@
     if (frame.Lsda)
       augmentationLength += getSizeForEncoding(streamer, frame.LsdaEncoding);
 
+    if (verboseAsm) streamer.AddComment("Augmentation size");
     streamer.EmitULEB128IntValue(augmentationLength);
 
     // Augmentation Data
     if (frame.Lsda)
-      EmitSymbol(streamer, *frame.Lsda, frame.LsdaEncoding);
+      EmitSymbol(streamer, *frame.Lsda, frame.LsdaEncoding,
+                 "Language Specific Data Area");
   }
 
   // Call Frame Instructions



From grosbach at apple.com  Thu Jun 30 17:10:47 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 30 Jun 2011 22:10:47 -0000
Subject: [llvm-commits] [llvm] r134197 - in /llvm/trunk:
 lib/Target/ARM/ARMAsmPrinter.cpp lib/Target/ARM/ARMFrameLowering.cpp
 lib/Target/ARM/ARMInstrThumb.td lib/Target/ARM/AsmParser/ARMAsmParser.cpp
 lib/Target/ARM/Thumb1FrameLowering.cpp lib/Target/ARM/Thumb1InstrInfo.cpp
 lib/Target/ARM/Thumb1RegisterInfo.cpp lib/Target/ARM/Thumb2InstrInfo.cpp
 test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
 test/CodeGen/Thumb2/thumb2-ifcvt1.ll
Message-ID: <20110630221047.2ADD52A6C12C@llvm.org>

Author: grosbach
Date: Thu Jun 30 17:10:46 2011
New Revision: 134197

URL: http://llvm.org/viewvc/llvm-project?rev=134197&view=rev
Log:
Thumb1 register to register MOV instruction is predicable.

Fix a FIXME and allow predication (in Thumb2) for the T1 register to
register MOV instructions. This allows some better codegen with
if-conversion (as seen in the test updates), plus it lays the groundwork
for pseudo-izing the tMOVCC instructions.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
    llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
    llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
    llvm/trunk/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
    llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134197&r1=134196&r2=134197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Jun 30 17:10:46 2011
@@ -1223,6 +1223,9 @@
       TmpInst.setOpcode(ARM::tMOVr);
       TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
+      // Add predicate operands.
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
       OutStreamer.EmitInstruction(TmpInst);
     }
     {
@@ -1610,8 +1613,9 @@
       TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
-      // 's' bit operand
-      TmpInst.addOperand(MCOperand::CreateReg(ARM::CPSR));
+      // Predicate.
+      TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
+      TmpInst.addOperand(MCOperand::CreateReg(0));
       OutStreamer.AddComment("eh_setjmp begin");
       OutStreamer.EmitInstruction(TmpInst);
     }

Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=134197&r1=134196&r2=134197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Jun 30 17:10:46 2011
@@ -268,14 +268,14 @@
       // bic r4, r4, MaxAlign
       // mov sp, r4
       // FIXME: It will be better just to find spare register here.
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
-        .addReg(ARM::SP, RegState::Kill);
+      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
+        .addReg(ARM::SP, RegState::Kill));
       AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
                                           TII.get(ARM::t2BICri), ARM::R4)
                                   .addReg(ARM::R4, RegState::Kill)
                                   .addImm(MaxAlign-1)));
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
-        .addReg(ARM::R4, RegState::Kill);
+      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
+        .addReg(ARM::R4, RegState::Kill));
     }
 
     AFI->setShouldRestoreSPFromFP(true);
@@ -293,9 +293,9 @@
         .addReg(ARM::SP)
         .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
     else
-      BuildMI(MBB, MBBI, dl,
-              TII.get(ARM::tMOVgpr2gpr), RegInfo->getBaseRegister())
-        .addReg(ARM::SP);
+      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
+                             RegInfo->getBaseRegister())
+        .addReg(ARM::SP));
   }
 
   // If the frame has variable sized objects then the epilogue must restore
@@ -364,8 +364,9 @@
                  "No scratch register to restore SP from FP!");
           emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
                                  ARMCC::AL, 0, TII);
-          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
-            .addReg(ARM::R4);
+          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
+                                 ARM::SP)
+            .addReg(ARM::R4));
         }
       } else {
         // Thumb2 or ARM.
@@ -373,8 +374,9 @@
           BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
             .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
         else
-          BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), ARM::SP)
-            .addReg(FramePtr);
+          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
+                                 ARM::SP)
+            .addReg(FramePtr));
       }
     } else if (NumBytes)
       emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134197&r1=134196&r2=134197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Jun 30 17:10:46 2011
@@ -409,7 +409,7 @@
 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
     hasExtraDefRegAllocReq = 1 in
 def tPOP_RET : tPseudoInst<(outs), (ins pred:$p, reglist:$regs, variable_ops),
-                           Size4Bytes, IIC_iPop_Br, []>;
+                           Size2Bytes, IIC_iPop_Br, []>;
 
 // All calls clobber the non-callee saved registers. SP is marked as a use to
 // prevent stack-pointer assignments that appear immediately before calls from
@@ -1054,9 +1054,9 @@
 // TODO: A7-73: MOV(2) - mov setting flag.
 
 let neverHasSideEffects = 1 in {
-// FIXME: Make this predicable.
-def tMOVr       : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
-                      "mov\t$Rd, $Rm", []>,
+def tMOVr : Thumb1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
+                      Size2Bytes, IIC_iMOVr,
+                      "mov", "\t$Rd, $Rm", "", []>,
                   T1Special<0b1000> {
   // A8.6.97
   bits<4> Rd;
@@ -1076,9 +1076,10 @@
   let Inst{2-0}  = Rd;
 }
 
-// FIXME: Make these predicable.
-def tMOVgpr2tgpr : T1I<(outs tGPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
-                       "mov\t$Rd, $Rm", []>,
+// FIXME: Do we really need separate instructions for GPR<-->tGPR like this?
+//        They all map to the same instruction (MOV encoding T1).
+def tMOVgpr2tgpr : Thumb1pI<(outs tGPR:$Rd), (ins GPR:$Rm), AddrModeNone,
+                            Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
                    T1Special<{1,0,0,?}> {
   // A8.6.97
   bits<4> Rd;
@@ -1087,8 +1088,8 @@
   let Inst{6-3} = Rm;
   let Inst{2-0} = Rd{2-0};
 }
-def tMOVtgpr2gpr : T1I<(outs GPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
-                       "mov\t$Rd, $Rm", []>,
+def tMOVtgpr2gpr : Thumb1pI<(outs GPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
+                            Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
                    T1Special<{1,0,?,0}> {
   // A8.6.97
   bits<4> Rd;
@@ -1098,8 +1099,8 @@
   let Inst{5-3} = Rm{2-0};
   let Inst{2-0} = Rd{2-0};
 }
-def tMOVgpr2gpr  : T1I<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
-                       "mov\t$Rd, $Rm", []>,
+def tMOVgpr2gpr  : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
+                            Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
                    T1Special<{1,0,?,?}> {
   // A8.6.97
   bits<4> Rd;

Modified: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp?rev=134197&r1=134196&r2=134197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp (original)
+++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp Thu Jun 30 17:10:46 2011
@@ -1882,8 +1882,7 @@
 
   if (isThumb)
     if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
-        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp" ||
-        (Mnemonic == "mov" && isThumbOne))
+        Mnemonic == "mrc" || Mnemonic == "mrrc" || Mnemonic == "cdp")
       CanAcceptPredicationCode = false;
 }
 

Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=134197&r1=134196&r2=134197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Thu Jun 30 17:10:46 2011
@@ -160,7 +160,8 @@
   // will be allocated after this, so we can still use the base pointer
   // to reference locals.
   if (RegInfo->hasBasePointer(MF))
-    BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr).addReg(ARM::SP);
+    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
+                   .addReg(ARM::SP));
 
   // If the frame has variable sized objects then the epilogue must restore
   // the sp from fp. We can assume there's an FP here since hasFP already
@@ -239,11 +240,13 @@
                "No scratch register to restore SP from FP!");
         emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
                                   TII, *RegInfo);
-        BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
-          .addReg(ARM::R4);
+        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
+                               ARM::SP)
+          .addReg(ARM::R4));
       } else
-        BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
-          .addReg(FramePtr);
+        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
+                               ARM::SP)
+          .addReg(FramePtr));
     } else {
       if (MBBI->getOpcode() == ARM::tBX_RET &&
           &MBB.front() != MBBI &&

Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=134197&r1=134196&r2=134197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Thu Jun 30 17:10:46 2011
@@ -46,8 +46,8 @@
   else if (tDest)
     Opc = ARM::tMOVgpr2tgpr;
 
-  BuildMI(MBB, I, DL, get(Opc), DestReg)
-    .addReg(SrcReg, getKillRegState(KillSrc));
+  AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
+    .addReg(SrcReg, getKillRegState(KillSrc)));
   assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
          "Thumb1 can only copy GPR registers");
 }

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=134197&r1=134196&r2=134197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Thu Jun 30 17:10:46 2011
@@ -244,8 +244,8 @@
         AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg).setMIFlags(MIFlags));
       AddDefaultPred(MIB.addReg(BaseReg, RegState::Kill).addImm(ThisVal));
     } else {
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
-        .addReg(BaseReg, RegState::Kill)
+      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
+        .addReg(BaseReg, RegState::Kill))
         .setMIFlags(MIFlags);
     }
     BaseReg = DestReg;
@@ -419,11 +419,10 @@
       // Turn it into a move.
       MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
-      // Remove offset and remaining explicit predicate operands.
-      do MI.RemoveOperand(FrameRegIdx+1);
-      while (MI.getNumOperands() > FrameRegIdx+1 &&
-             (!MI.getOperand(FrameRegIdx+1).isReg() ||
-              !MI.getOperand(FrameRegIdx+1).isImm()));
+      // Remove offset and add predicate operands.
+      MI.RemoveOperand(FrameRegIdx+1);
+      MachineInstrBuilder MIB(&MI);
+      AddDefaultPred(MIB);
       return true;
     }
 
@@ -565,8 +564,9 @@
   // the function, the offset will be negative. Use R12 instead since that's
   // a call clobbered register that we know won't be used in Thumb1 mode.
   DebugLoc DL;
-  BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr)).
-    addReg(ARM::R12, RegState::Define).addReg(Reg, RegState::Kill);
+  AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr))
+    .addReg(ARM::R12, RegState::Define)
+    .addReg(Reg, RegState::Kill));
 
   // The UseMI is where we would like to restore the register. If there's
   // interference with R12 before then, however, we'll need to restore it
@@ -589,8 +589,8 @@
     }
   }
   // Restore the register from R12
-  BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
-    addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill);
+  AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
+    addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
 
   return true;
 }

Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=134197&r1=134196&r2=134197&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Thu Jun 30 17:10:46 2011
@@ -122,8 +122,8 @@
   else if (tDest)
     Opc = ARM::tMOVgpr2tgpr;
 
-  BuildMI(MBB, I, DL, get(Opc), DestReg)
-    .addReg(SrcReg, getKillRegState(KillSrc));
+  AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
+    .addReg(SrcReg, getKillRegState(KillSrc)));
 }
 
 void Thumb2InstrInfo::
@@ -231,8 +231,8 @@
     unsigned Opc = 0;
     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
       // mov sp, rn. Note t2MOVr cannot be used.
-      BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg)
-        .addReg(BaseReg).setMIFlags(MIFlags);
+      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg)
+        .addReg(BaseReg).setMIFlags(MIFlags));
       BaseReg = ARM::SP;
       continue;
     }
@@ -413,9 +413,9 @@
       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
       // Remove offset and remaining explicit predicate operands.
       do MI.RemoveOperand(FrameRegIdx+1);
-      while (MI.getNumOperands() > FrameRegIdx+1 &&
-             (!MI.getOperand(FrameRegIdx+1).isReg() ||
-              !MI.getOperand(FrameRegIdx+1).isImm()));
+      while (MI.getNumOperands() > FrameRegIdx+1);
+      MachineInstrBuilder MIB(&MI);
+      AddDefaultPred(MIB);
       return true;
     }
 

Modified: llvm/trunk/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll?rev=134197&r1=134196&r2=134197&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/2011-06-07-TwoAddrEarlyClobber.ll Thu Jun 30 17:10:46 2011
@@ -1,13 +1,11 @@
-; RUN: llc < %s | FileCheck %s
-target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:32:64-v128:32:128-a0:0:32-n32"
-target triple = "thumbv7-apple-darwin10"
+; RUN: llc -mtriple=thumbv7-apple-darwin10 < %s | FileCheck %s
 
 %struct.op = type { %struct.op*, %struct.op*, %struct.op* ()*, i32, i16, i16, i8, i8 }
 
 ; CHECK: Perl_ck_sort
-; CHECK: ldr
-; CHECK: mov [[REGISTER:(r[0-9]+)|(lr)]]
-; CHECK: str {{(r[0-9])|(lr)}}, {{\[}}[[REGISTER]]{{\]}}, #24
+; CHECK: ldreq
+; CHECK: moveq [[REGISTER:(r[0-9]+)|(lr)]]
+; CHECK: streq {{(r[0-9])|(lr)}}, {{\[}}[[REGISTER]]{{\]}}, #24
 
 define void @Perl_ck_sort() nounwind optsize {
 entry:

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll?rev=134197&r1=134196&r2=134197&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-ifcvt1.ll Thu Jun 30 17:10:46 2011
@@ -70,8 +70,9 @@
 define void @t3(i32 %a, i32 %b) nounwind {
 entry:
 ; CHECK: t3:
-; CHECK: it lt
-; CHECK: poplt {r7, pc}
+; CHECK: itt ge
+; CHECK: movge r0, r1
+; CHECK: blge  _foo
 	%tmp1 = icmp sgt i32 %a, 10		;  [#uses=1]
 	br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
 



From echristo at apple.com  Thu Jun 30 17:17:01 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 30 Jun 2011 22:17:01 -0000
Subject: [llvm-commits] [llvm] r134198 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20110630221701.F201E2A6C12C@llvm.org>

Author: echristo
Date: Thu Jun 30 17:17:01 2011
New Revision: 134198

URL: http://llvm.org/viewvc/llvm-project?rev=134198&view=rev
Log:
Add a convenience typedef for std::pair.

No functional change.

Part of rdar://9119939

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134198&r1=134197&r2=134198&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 17:17:01 2011
@@ -7527,7 +7527,8 @@
   return weight;
 }
 
-std::pair
+typedef std::pair Pair;
+Pair
 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
                                                 EVT VT) const {
   if (Constraint.size() == 1) {
@@ -7535,18 +7536,18 @@
     switch (Constraint[0]) {
     case 'l':
       if (Subtarget->isThumb())
-        return std::make_pair(0U, ARM::tGPRRegisterClass);
+        return Pair(0U, ARM::tGPRRegisterClass);
       else
-        return std::make_pair(0U, ARM::GPRRegisterClass);
+        return Pair(0U, ARM::GPRRegisterClass);
     case 'r':
-      return std::make_pair(0U, ARM::GPRRegisterClass);
+      return Pair(0U, ARM::GPRRegisterClass);
     case 'w':
       if (VT == MVT::f32)
-        return std::make_pair(0U, ARM::SPRRegisterClass);
+        return Pair(0U, ARM::SPRRegisterClass);
       if (VT.getSizeInBits() == 64)
-        return std::make_pair(0U, ARM::DPRRegisterClass);
+        return Pair(0U, ARM::DPRRegisterClass);
       if (VT.getSizeInBits() == 128)
-        return std::make_pair(0U, ARM::QPRRegisterClass);
+        return Pair(0U, ARM::QPRRegisterClass);
       break;
     }
   }



From rafael.espindola at gmail.com  Thu Jun 30 17:24:13 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 30 Jun 2011 22:24:13 -0000
Subject: [llvm-commits] [llvm] r134199 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
Message-ID: <20110630222413.C25F02A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 30 17:24:13 2011
New Revision: 134199

URL: http://llvm.org/viewvc/llvm-project?rev=134199&view=rev
Log:
Don't give up on coalescing A and B when we find

A = X
B = X

Instead, proceed as if we had found

A = X
B = A

Modified:
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=134199&r1=134198&r2=134199&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Thu Jun 30 17:24:13 2011
@@ -1187,6 +1187,65 @@
   return ThisValNoAssignments[VN] = UltimateVN;
 }
 
+
+// Find out if we have something like
+// A = X
+// B = X
+// if so, we can pretend this is actually
+// A = X
+// B = A
+// which allows us to coalesce A and B.
+// MI is the definition of B. LR is the life range of A that includes
+// the slot just before B. If we return true, we add "B = X" to DupCopies.
+static bool RegistersDefinedFromSameValue(const TargetRegisterInfo &tri,
+                                          CoalescerPair &CP, MachineInstr *MI,
+                                          LiveRange *LR,
+                                     SmallVector &DupCopies) {
+  // FIXME: This is very conservative. For example, we don't handle
+  // physical registers.
+
+  if (!MI->isFullCopy() || CP.isPartial() || CP.isPhys())
+    return false;
+
+  unsigned Dst = MI->getOperand(0).getReg();
+  unsigned Src = MI->getOperand(1).getReg();
+
+  if (!TargetRegisterInfo::isVirtualRegister(Src) ||
+      !TargetRegisterInfo::isVirtualRegister(Dst))
+    return false;
+
+  unsigned A = CP.getDstReg();
+  unsigned B = CP.getSrcReg();
+
+  if (B == Dst)
+    std::swap(A, B);
+  assert(Dst == A);
+
+  VNInfo *Other = LR->valno;
+  if (!Other->isDefByCopy())
+    return false;
+  const MachineInstr *OtherMI = Other->getCopy();
+
+  if (!OtherMI->isFullCopy())
+    return false;
+
+  unsigned OtherDst = OtherMI->getOperand(0).getReg();
+  unsigned OtherSrc = OtherMI->getOperand(1).getReg();
+
+  if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) ||
+      !TargetRegisterInfo::isVirtualRegister(OtherDst))
+    return false;
+
+  assert(OtherDst == B);
+
+  if (Src != OtherSrc)
+    return false;
+
+  DupCopies.push_back(MI);
+
+  return true;
+}
+
 /// JoinIntervals - Attempt to join these two intervals.  On failure, this
 /// returns false.
 bool RegisterCoalescer::JoinIntervals(CoalescerPair &CP) {
@@ -1242,6 +1301,8 @@
   DenseMap RHSValsDefinedFromLHS;
   SmallVector NewVNInfo;
 
+  SmallVector DupCopies;
+
   LiveInterval &LHS = li_->getOrCreateInterval(CP.getDstReg());
   DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; });
 
@@ -1257,15 +1318,18 @@
     if (VNI->hasRedefByEC())
       return false;
 
-    // DstReg is known to be a register in the LHS interval.  If the src is
-    // from the RHS interval, we can use its value #.
-    if (!CP.isCoalescable(VNI->getCopy()))
-      continue;
-
     // Figure out the value # from the RHS.
     LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
     // The copy could be to an aliased physreg.
     if (!lr) continue;
+
+    // DstReg is known to be a register in the LHS interval.  If the src is
+    // from the RHS interval, we can use its value #.
+    MachineInstr *MI = VNI->getCopy();
+    if (!CP.isCoalescable(MI) &&
+        !RegistersDefinedFromSameValue(*tri_, CP, MI, lr, DupCopies))
+      continue;
+
     LHSValsDefinedFromRHS[VNI] = lr->valno;
   }
 
@@ -1281,15 +1345,18 @@
     if (VNI->hasRedefByEC())
       return false;
 
-    // DstReg is known to be a register in the RHS interval.  If the src is
-    // from the LHS interval, we can use its value #.
-    if (!CP.isCoalescable(VNI->getCopy()))
-      continue;
-
     // Figure out the value # from the LHS.
     LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
     // The copy could be to an aliased physreg.
     if (!lr) continue;
+
+    // DstReg is known to be a register in the RHS interval.  If the src is
+    // from the LHS interval, we can use its value #.
+    MachineInstr *MI = VNI->getCopy();
+    if (!CP.isCoalescable(MI) &&
+        !RegistersDefinedFromSameValue(*tri_, CP, MI, lr, DupCopies))
+        continue;
+
     RHSValsDefinedFromLHS[VNI] = lr->valno;
   }
 
@@ -1394,6 +1461,24 @@
   if (RHSValNoAssignments.empty())
     RHSValNoAssignments.push_back(-1);
 
+  for (SmallVector::iterator I = DupCopies.begin(),
+         E = DupCopies.end(); I != E; ++I) {
+    MachineInstr *MI = *I;
+
+    // We have pretended that the assignment to B in
+    // A = X
+    // B = X
+    // was actually a copy from A. Now that we decided to coalesce A and B,
+    // transform the code into
+    // A = X
+    // X = X
+    // and mark the X as coalesced to keep the illusion.
+    unsigned Src = MI->getOperand(1).getReg();
+    MI->getOperand(0).substVirtReg(Src, 0, *tri_);
+
+    markAsJoined(MI);
+  }
+
   // If we get here, we know that we can coalesce the live ranges.  Ask the
   // intervals to coalesce themselves now.
   LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,



From grosbach at apple.com  Thu Jun 30 17:24:19 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 30 Jun 2011 15:24:19 -0700
Subject: [llvm-commits] [llvm] r134198 -
 /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
In-Reply-To: <20110630221701.F201E2A6C12C@llvm.org>
References: <20110630221701.F201E2A6C12C@llvm.org>
Message-ID: 


On Jun 30, 2011, at 3:17 PM, Eric Christopher wrote:

> Author: echristo
> Date: Thu Jun 30 17:17:01 2011
> New Revision: 134198
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=134198&view=rev
> Log:
> Add a convenience typedef for std::pair.
> 
> No functional change.
> 
> Part of rdar://9119939
> 
> Modified:
>    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> 
> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134198&r1=134197&r2=134198&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 17:17:01 2011
> @@ -7527,7 +7527,8 @@
>   return weight;
> }
> 
> -std::pair
> +typedef std::pair Pair;
> +Pair

Mind giving the typedef a more informational name?

> ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
>                                                 EVT VT) const {
>   if (Constraint.size() == 1) {
> @@ -7535,18 +7536,18 @@
>     switch (Constraint[0]) {
>     case 'l':
>       if (Subtarget->isThumb())
> -        return std::make_pair(0U, ARM::tGPRRegisterClass);
> +        return Pair(0U, ARM::tGPRRegisterClass);
>       else
> -        return std::make_pair(0U, ARM::GPRRegisterClass);
> +        return Pair(0U, ARM::GPRRegisterClass);
>     case 'r':
> -      return std::make_pair(0U, ARM::GPRRegisterClass);
> +      return Pair(0U, ARM::GPRRegisterClass);
>     case 'w':
>       if (VT == MVT::f32)
> -        return std::make_pair(0U, ARM::SPRRegisterClass);
> +        return Pair(0U, ARM::SPRRegisterClass);
>       if (VT.getSizeInBits() == 64)
> -        return std::make_pair(0U, ARM::DPRRegisterClass);
> +        return Pair(0U, ARM::DPRRegisterClass);
>       if (VT.getSizeInBits() == 128)
> -        return std::make_pair(0U, ARM::QPRRegisterClass);
> +        return Pair(0U, ARM::QPRRegisterClass);
>       break;
>     }
>   }
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits


From rafael.espindola at gmail.com  Thu Jun 30 17:28:51 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Thu, 30 Jun 2011 18:28:51 -0400
Subject: [llvm-commits] [patch] Improve register coalescing
In-Reply-To: 
References: <4E0B9D31.3020101@gmail.com>
	<5C5CA408-CEC6-49E2-88CF-55C315AF3D97@2pi.dk>
	<4E0CEC75.40303@gmail.com>
	
Message-ID: <4E0CF8A3.20405@gmail.com>

>> The real solution I think would be to turn the coalescing algorithm
>> upside down: instead of trying to merge registers one pair at a time,
>> start by assuming that every copy related register can be merged and
>> try to show it cannot.
>
> That sounds hard to get right.

True. The difference just reminded me of regular X strong dead code 
elimination.

>> BB1:
>> X = B
>> Y = A
>>
>> BB2:
>> A = X
>> B = Y
>>
>> A and B can be merged if X and Y can be merged and X and Y can be
>> merge if A and B can be merged.
>
> I think we already detect and remove this kind of PHI loops?

Cool. If we do then just following copy definitions should get almost 
all of the cases. I might give it a try on Firefox and see if it makes a 
difference.

> /jakob
>

Cheers,
Rafael

From evan.cheng at apple.com  Thu Jun 30 17:35:00 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Thu, 30 Jun 2011 15:35:00 -0700
Subject: [llvm-commits] [patch] Improve register coalescing
In-Reply-To: <4E0CF8A3.20405@gmail.com>
References: <4E0B9D31.3020101@gmail.com>
	<5C5CA408-CEC6-49E2-88CF-55C315AF3D97@2pi.dk>
	<4E0CEC75.40303@gmail.com>
	
	<4E0CF8A3.20405@gmail.com>
Message-ID: 

Please watch performance changes (beyond just js) carefully. More coalescing doesn't always equal better performance. I think greedy regalloc is going to be able to handle anything the coalescer throws its way, but let's be careful still.

Evan

On Jun 30, 2011, at 3:28 PM, Rafael ?vila de Esp?ndola wrote:

>>> The real solution I think would be to turn the coalescing algorithm
>>> upside down: instead of trying to merge registers one pair at a time,
>>> start by assuming that every copy related register can be merged and
>>> try to show it cannot.
>> 
>> That sounds hard to get right.
> 
> True. The difference just reminded me of regular X strong dead code 
> elimination.
> 
>>> BB1:
>>> X = B
>>> Y = A
>>> 
>>> BB2:
>>> A = X
>>> B = Y
>>> 
>>> A and B can be merged if X and Y can be merged and X and Y can be
>>> merge if A and B can be merged.
>> 
>> I think we already detect and remove this kind of PHI loops?
> 
> Cool. If we do then just following copy definitions should get almost 
> all of the cases. I might give it a try on Firefox and see if it makes a 
> difference.
> 
>> /jakob
>> 
> 
> Cheers,
> Rafael
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits



From isanbard at gmail.com  Thu Jun 30 17:35:49 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 30 Jun 2011 22:35:49 -0000
Subject: [llvm-commits] [llvm] r134200 - /llvm/trunk/lib/MC/MCDwarf.cpp
Message-ID: <20110630223549.858E42A6C12C@llvm.org>

Author: void
Date: Thu Jun 30 17:35:49 2011
New Revision: 134200

URL: http://llvm.org/viewvc/llvm-project?rev=134200&view=rev
Log:
Add one more comment to the FDE verbose asm output.

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=134200&r1=134199&r2=134200&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Thu Jun 30 17:35:49 2011
@@ -670,6 +670,7 @@
     if (BaseLabel && Label) {
       MCSymbol *ThisSym = Label;
       if (ThisSym != BaseLabel) {
+        if (streamer.isVerboseAsm()) streamer.AddComment("DW_CFA_advance_loc4");
         streamer.EmitDwarfAdvanceFrameAddr(BaseLabel, ThisSym);
         BaseLabel = ThisSym;
       }



From rafael.espindola at gmail.com  Thu Jun 30 17:54:37 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Thu, 30 Jun 2011 18:54:37 -0400
Subject: [llvm-commits] [patch] Improve register coalescing
In-Reply-To: 
References: <4E0B9D31.3020101@gmail.com>
	<5C5CA408-CEC6-49E2-88CF-55C315AF3D97@2pi.dk>
	<4E0CEC75.40303@gmail.com>
	
	<4E0CF8A3.20405@gmail.com>
	
Message-ID: <4E0CFEAD.1070501@gmail.com>

On 06/30/2011 06:35 PM, Evan Cheng wrote:
> Please watch performance changes (beyond just js) carefully. More
> coalescing doesn't always equal better performance. I think greedy
> regalloc is going to be able to handle anything the coalescer throws
> its way, but let's be careful still.

Sure, but "can" and "should" are independent.

This patch makes the coalescer see that it can merge A and B. If there 
are cases where merging A and B is not profitable (the life range gets 
too big?) that should be an independent test.

> Evan

Cheers,
Rafael

From rafael.espindola at gmail.com  Thu Jun 30 17:58:18 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Thu, 30 Jun 2011 22:58:18 -0000
Subject: [llvm-commits] [llvm] r134201 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
Message-ID: <20110630225818.1A3832A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 30 17:58:17 2011
New Revision: 134201

URL: http://llvm.org/viewvc/llvm-project?rev=134201&view=rev
Log:
Revert my previous patch while I debug llvm-gcc bootstrap.

Modified:
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=134201&r1=134200&r2=134201&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Thu Jun 30 17:58:17 2011
@@ -1187,65 +1187,6 @@
   return ThisValNoAssignments[VN] = UltimateVN;
 }
 
-
-// Find out if we have something like
-// A = X
-// B = X
-// if so, we can pretend this is actually
-// A = X
-// B = A
-// which allows us to coalesce A and B.
-// MI is the definition of B. LR is the life range of A that includes
-// the slot just before B. If we return true, we add "B = X" to DupCopies.
-static bool RegistersDefinedFromSameValue(const TargetRegisterInfo &tri,
-                                          CoalescerPair &CP, MachineInstr *MI,
-                                          LiveRange *LR,
-                                     SmallVector &DupCopies) {
-  // FIXME: This is very conservative. For example, we don't handle
-  // physical registers.
-
-  if (!MI->isFullCopy() || CP.isPartial() || CP.isPhys())
-    return false;
-
-  unsigned Dst = MI->getOperand(0).getReg();
-  unsigned Src = MI->getOperand(1).getReg();
-
-  if (!TargetRegisterInfo::isVirtualRegister(Src) ||
-      !TargetRegisterInfo::isVirtualRegister(Dst))
-    return false;
-
-  unsigned A = CP.getDstReg();
-  unsigned B = CP.getSrcReg();
-
-  if (B == Dst)
-    std::swap(A, B);
-  assert(Dst == A);
-
-  VNInfo *Other = LR->valno;
-  if (!Other->isDefByCopy())
-    return false;
-  const MachineInstr *OtherMI = Other->getCopy();
-
-  if (!OtherMI->isFullCopy())
-    return false;
-
-  unsigned OtherDst = OtherMI->getOperand(0).getReg();
-  unsigned OtherSrc = OtherMI->getOperand(1).getReg();
-
-  if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) ||
-      !TargetRegisterInfo::isVirtualRegister(OtherDst))
-    return false;
-
-  assert(OtherDst == B);
-
-  if (Src != OtherSrc)
-    return false;
-
-  DupCopies.push_back(MI);
-
-  return true;
-}
-
 /// JoinIntervals - Attempt to join these two intervals.  On failure, this
 /// returns false.
 bool RegisterCoalescer::JoinIntervals(CoalescerPair &CP) {
@@ -1301,8 +1242,6 @@
   DenseMap RHSValsDefinedFromLHS;
   SmallVector NewVNInfo;
 
-  SmallVector DupCopies;
-
   LiveInterval &LHS = li_->getOrCreateInterval(CP.getDstReg());
   DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; });
 
@@ -1318,18 +1257,15 @@
     if (VNI->hasRedefByEC())
       return false;
 
-    // Figure out the value # from the RHS.
-    LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
-    // The copy could be to an aliased physreg.
-    if (!lr) continue;
-
     // DstReg is known to be a register in the LHS interval.  If the src is
     // from the RHS interval, we can use its value #.
-    MachineInstr *MI = VNI->getCopy();
-    if (!CP.isCoalescable(MI) &&
-        !RegistersDefinedFromSameValue(*tri_, CP, MI, lr, DupCopies))
+    if (!CP.isCoalescable(VNI->getCopy()))
       continue;
 
+    // Figure out the value # from the RHS.
+    LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
+    // The copy could be to an aliased physreg.
+    if (!lr) continue;
     LHSValsDefinedFromRHS[VNI] = lr->valno;
   }
 
@@ -1345,18 +1281,15 @@
     if (VNI->hasRedefByEC())
       return false;
 
+    // DstReg is known to be a register in the RHS interval.  If the src is
+    // from the LHS interval, we can use its value #.
+    if (!CP.isCoalescable(VNI->getCopy()))
+      continue;
+
     // Figure out the value # from the LHS.
     LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
     // The copy could be to an aliased physreg.
     if (!lr) continue;
-
-    // DstReg is known to be a register in the RHS interval.  If the src is
-    // from the LHS interval, we can use its value #.
-    MachineInstr *MI = VNI->getCopy();
-    if (!CP.isCoalescable(MI) &&
-        !RegistersDefinedFromSameValue(*tri_, CP, MI, lr, DupCopies))
-        continue;
-
     RHSValsDefinedFromLHS[VNI] = lr->valno;
   }
 
@@ -1461,24 +1394,6 @@
   if (RHSValNoAssignments.empty())
     RHSValNoAssignments.push_back(-1);
 
-  for (SmallVector::iterator I = DupCopies.begin(),
-         E = DupCopies.end(); I != E; ++I) {
-    MachineInstr *MI = *I;
-
-    // We have pretended that the assignment to B in
-    // A = X
-    // B = X
-    // was actually a copy from A. Now that we decided to coalesce A and B,
-    // transform the code into
-    // A = X
-    // X = X
-    // and mark the X as coalesced to keep the illusion.
-    unsigned Src = MI->getOperand(1).getReg();
-    MI->getOperand(0).substVirtReg(Src, 0, *tri_);
-
-    markAsJoined(MI);
-  }
-
   // If we get here, we know that we can coalesce the live ranges.  Ask the
   // intervals to coalesce themselves now.
   LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,



From isanbard at gmail.com  Thu Jun 30 18:20:32 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 30 Jun 2011 23:20:32 -0000
Subject: [llvm-commits] [llvm] r134202 - in /llvm/trunk:
 include/llvm/Target/TargetAsmInfo.h
 include/llvm/Target/TargetRegisterInfo.h lib/Target/X86/X86RegisterInfo.cpp
 lib/Target/X86/X86RegisterInfo.h
Message-ID: <20110630232032.CE8D92A6C12C@llvm.org>

Author: void
Date: Thu Jun 30 18:20:32 2011
New Revision: 134202

URL: http://llvm.org/viewvc/llvm-project?rev=134202&view=rev
Log:
Add target a target hook to get the register number used by the compact unwind
encoding for the registers it knows about. Return -1 if it can't handle that
register.

Modified:
    llvm/trunk/include/llvm/Target/TargetAsmInfo.h
    llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
    llvm/trunk/lib/Target/X86/X86RegisterInfo.h

Modified: llvm/trunk/include/llvm/Target/TargetAsmInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetAsmInfo.h?rev=134202&r1=134201&r2=134202&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetAsmInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetAsmInfo.h Thu Jun 30 18:20:32 2011
@@ -106,6 +106,10 @@
   int getSEHRegNum(unsigned RegNum) const {
     return TRI->getSEHRegNum(RegNum);
   }
+
+  int getCompactUnwindRegNum(unsigned RegNum) const {
+    return TRI->getCompactUnwindRegNum(RegNum);
+  }
 };
 
 }

Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=134202&r1=134201&r2=134202&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Thu Jun 30 18:20:32 2011
@@ -720,6 +720,12 @@
   virtual int getSEHRegNum(unsigned i) const {
     return i;
   }
+
+  /// getCompactUnwindRegNum - This function maps the register to the number for
+  /// compact unwind encoding. Return -1 if the register isn't valid.
+  virtual int getCompactUnwindRegNum(unsigned) const {
+    return -1;
+  }
 };
 
 

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=134202&r1=134201&r2=134202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Jun 30 18:20:32 2011
@@ -105,6 +105,21 @@
   return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
 }
 
+/// getCompactUnwindRegNum - This function maps the register to the number for
+/// compact unwind encoding. Return -1 if the register isn't valid.
+int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum) const {
+  switch (RegNum) {
+  case X86::EBX: case X86::RBX: return 1;
+  case X86::ECX: case X86::RCX: return 2;
+  case X86::EDX: case X86::RDX: return 3;
+  case X86::EDI: case X86::RDI: return 4;
+  case X86::ESI: case X86::RSI: return 5;
+  case X86::EBP: case X86::RBP: return 6;
+  }
+
+  return -1;
+}
+
 int
 X86RegisterInfo::getSEHRegNum(unsigned i) const {
   int reg = getX86RegNum(i);

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.h?rev=134202&r1=134201&r2=134202&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.h Thu Jun 30 18:20:32 2011
@@ -81,6 +81,10 @@
   // FIXME: This should be tablegen'd like getDwarfRegNum is
   int getSEHRegNum(unsigned i) const;
 
+  /// getCompactUnwindRegNum - This function maps the register to the number for
+  /// compact unwind encoding. Return -1 if the register isn't valid.
+  int getCompactUnwindRegNum(unsigned RegNum) const;
+
   /// Code Generation virtual methods...
   /// 
 



From echristo at apple.com  Thu Jun 30 18:23:01 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 30 Jun 2011 23:23:01 -0000
Subject: [llvm-commits] [llvm] r134203 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp lib/Target/ARM/ARMRegisterInfo.td
 test/CodeGen/Thumb/inlineasm-thumb.ll
Message-ID: <20110630232301.82B0A2A6C12C@llvm.org>

Author: echristo
Date: Thu Jun 30 18:23:01 2011
New Revision: 134203

URL: http://llvm.org/viewvc/llvm-project?rev=134203&view=rev
Log:
Add support for the 'h' constraint.

Part of rdar://9119939

Added:
    llvm/trunk/test/CodeGen/Thumb/inlineasm-thumb.ll
Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134203&r1=134202&r2=134203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 18:23:01 2011
@@ -7482,6 +7482,7 @@
     default:  break;
     case 'l': return C_RegisterClass;
     case 'w': return C_RegisterClass;
+    case 'h': return C_RegisterClass;
     }
   } else if (Constraint.size() == 2) {
     switch (Constraint[0]) {
@@ -7534,11 +7535,16 @@
   if (Constraint.size() == 1) {
     // GCC ARM Constraint Letters
     switch (Constraint[0]) {
-    case 'l':
+    case 'l': // Low regs or general regs.
       if (Subtarget->isThumb())
         return Pair(0U, ARM::tGPRRegisterClass);
       else
         return Pair(0U, ARM::GPRRegisterClass);
+    case 'h': // High regs or no regs.
+      if (Subtarget->isThumb())
+	return Pair(0U, ARM::hGPRRegisterClass);
+      else
+	return Pair(0u, static_cast(0));
     case 'r':
       return Pair(0U, ARM::GPRRegisterClass);
     case 'w':

Modified: llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td?rev=134203&r1=134202&r2=134203&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterInfo.td Thu Jun 30 18:23:01 2011
@@ -228,6 +228,9 @@
 // the general GPR register class above (MOV, e.g.)
 def tGPR : RegisterClass<"ARM", [i32], 32, (trunc GPR, 8)>;
 
+// The high registers in thumb mode, R8-R15.
+def hGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, tGPR)>;
+
 // For tail calls, we can't use callee-saved registers, as they are restored
 // to the saved value before the tail call, which would clobber a call address.
 // Note, getMinimalPhysRegClass(R0) returns tGPR because of the names of

Added: llvm/trunk/test/CodeGen/Thumb/inlineasm-thumb.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb/inlineasm-thumb.ll?rev=134203&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb/inlineasm-thumb.ll (added)
+++ llvm/trunk/test/CodeGen/Thumb/inlineasm-thumb.ll Thu Jun 30 18:23:01 2011
@@ -0,0 +1,7 @@
+; RUN: llc < %s -march=thumb | FileCheck %s
+define i32 @t1(i32 %x, i32 %y) nounwind {
+entry:
+  ; CHECK: mov r0, r12
+  %0 = tail call i32 asm "mov $0, $1", "=l,h"(i32 %y) nounwind
+  ret i32 %0
+}



From grosbach at apple.com  Thu Jun 30 18:38:17 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 30 Jun 2011 23:38:17 -0000
Subject: [llvm-commits] [llvm] r134204 - in /llvm/trunk/lib/Target/ARM:
 ARMAsmPrinter.cpp ARMFrameLowering.cpp ARMInstrThumb.td
 Thumb1FrameLowering.cpp Thumb1InstrInfo.cpp Thumb1RegisterInfo.cpp
 Thumb2ITBlockPass.cpp Thumb2InstrInfo.cpp Thumb2SizeReduction.cpp
Message-ID: <20110630233817.AE16E2A6C12C@llvm.org>

Author: grosbach
Date: Thu Jun 30 18:38:17 2011
New Revision: 134204

URL: http://llvm.org/viewvc/llvm-project?rev=134204&view=rev
Log:
Refact ARM Thumb1 tMOVr instruction family.

Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.

Modified:
    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
    llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
    llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
    llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134204&r1=134203&r2=134204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Jun 30 18:38:17 2011
@@ -1010,8 +1010,6 @@
         MI->dump();
         assert(0 && "Unsupported opcode for unwinding information");
       case ARM::MOVr:
-      case ARM::tMOVgpr2gpr:
-      case ARM::tMOVgpr2tgpr:
         Offset = 0;
         break;
       case ARM::ADDri:
@@ -1456,7 +1454,7 @@
   case ARM::t2BR_JT: {
     // Lower and emit the instruction itself, then the jump table following it.
     MCInst TmpInst;
-    TmpInst.setOpcode(ARM::tMOVgpr2gpr);
+    TmpInst.setOpcode(ARM::tMOVr);
     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
     // Add predicate operands.
@@ -1505,7 +1503,7 @@
     // mov pc, target
     MCInst TmpInst;
     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
-      ARM::MOVr : ARM::tMOVgpr2gpr;
+      ARM::MOVr : ARM::tMOVr;
     TmpInst.setOpcode(Opc);
     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
@@ -1518,7 +1516,7 @@
     OutStreamer.EmitInstruction(TmpInst);
 
     // Make sure the Thumb jump table is 4-byte aligned.
-    if (Opc == ARM::tMOVgpr2gpr)
+    if (Opc == ARM::tMOVr)
       EmitAlignment(2);
 
     // Output the data for the jump table itself
@@ -1610,7 +1608,7 @@
     MCSymbol *Label = GetARMSJLJEHLabel();
     {
       MCInst TmpInst;
-      TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
+      TmpInst.setOpcode(ARM::tMOVr);
       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
       // Predicate.
@@ -1829,7 +1827,7 @@
     }
     {
       MCInst TmpInst;
-      TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
+      TmpInst.setOpcode(ARM::tMOVr);
       TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
       // Predicate.

Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=134204&r1=134203&r2=134204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Jun 30 18:38:17 2011
@@ -268,13 +268,13 @@
       // bic r4, r4, MaxAlign
       // mov sp, r4
       // FIXME: It will be better just to find spare register here.
-      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
+      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
         .addReg(ARM::SP, RegState::Kill));
       AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
                                           TII.get(ARM::t2BICri), ARM::R4)
                                   .addReg(ARM::R4, RegState::Kill)
                                   .addImm(MaxAlign-1)));
-      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
+      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
         .addReg(ARM::R4, RegState::Kill));
     }
 
@@ -293,7 +293,7 @@
         .addReg(ARM::SP)
         .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
     else
-      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
+      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
                              RegInfo->getBaseRegister())
         .addReg(ARM::SP));
   }
@@ -364,7 +364,7 @@
                  "No scratch register to restore SP from FP!");
           emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
                                  ARMCC::AL, 0, TII);
-          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
+          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
                                  ARM::SP)
             .addReg(ARM::R4));
         }
@@ -374,7 +374,7 @@
           BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
             .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
         else
-          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
+          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
                                  ARM::SP)
             .addReg(FramePtr));
       }

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134204&r1=134203&r2=134204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Jun 30 18:38:17 2011
@@ -1054,15 +1054,15 @@
 // TODO: A7-73: MOV(2) - mov setting flag.
 
 let neverHasSideEffects = 1 in {
-def tMOVr : Thumb1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
+def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
                       Size2Bytes, IIC_iMOVr,
                       "mov", "\t$Rd, $Rm", "", []>,
-                  T1Special<0b1000> {
+                  T1Special<{1,0,?,?}> {
   // A8.6.97
   bits<4> Rd;
   bits<4> Rm;
-  // Bits {7-6} are encoded by the T1Special value.
-  let Inst{5-3} = Rm{2-0};
+  let Inst{7}   = Rd{3};
+  let Inst{6-3} = Rm;
   let Inst{2-0} = Rd{2-0};
 }
 let Defs = [CPSR] in
@@ -1075,40 +1075,6 @@
   let Inst{5-3}  = Rm;
   let Inst{2-0}  = Rd;
 }
-
-// FIXME: Do we really need separate instructions for GPR<-->tGPR like this?
-//        They all map to the same instruction (MOV encoding T1).
-def tMOVgpr2tgpr : Thumb1pI<(outs tGPR:$Rd), (ins GPR:$Rm), AddrModeNone,
-                            Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
-                   T1Special<{1,0,0,?}> {
-  // A8.6.97
-  bits<4> Rd;
-  bits<4> Rm;
-  // Bit {7} is encoded by the T1Special value.
-  let Inst{6-3} = Rm;
-  let Inst{2-0} = Rd{2-0};
-}
-def tMOVtgpr2gpr : Thumb1pI<(outs GPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
-                            Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
-                   T1Special<{1,0,?,0}> {
-  // A8.6.97
-  bits<4> Rd;
-  bits<4> Rm;
-  // Bit {6} is encoded by the T1Special value.
-  let Inst{7}   = Rd{3};
-  let Inst{5-3} = Rm{2-0};
-  let Inst{2-0} = Rd{2-0};
-}
-def tMOVgpr2gpr  : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
-                            Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
-                   T1Special<{1,0,?,?}> {
-  // A8.6.97
-  bits<4> Rd;
-  bits<4> Rm;
-  let Inst{7}   = Rd{3};
-  let Inst{6-3} = Rm;
-  let Inst{2-0} = Rd{2-0};
-}
 } // neverHasSideEffects
 
 // Multiply register

Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=134204&r1=134203&r2=134204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Thu Jun 30 18:38:17 2011
@@ -160,7 +160,7 @@
   // will be allocated after this, so we can still use the base pointer
   // to reference locals.
   if (RegInfo->hasBasePointer(MF))
-    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
+    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
                    .addReg(ARM::SP));
 
   // If the frame has variable sized objects then the epilogue must restore
@@ -240,11 +240,11 @@
                "No scratch register to restore SP from FP!");
         emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
                                   TII, *RegInfo);
-        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
+        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
                                ARM::SP)
           .addReg(ARM::R4));
       } else
-        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
+        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
                                ARM::SP)
           .addReg(FramePtr));
     } else {

Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Thu Jun 30 18:38:17 2011
@@ -36,17 +36,7 @@
                                   MachineBasicBlock::iterator I, DebugLoc DL,
                                   unsigned DestReg, unsigned SrcReg,
                                   bool KillSrc) const {
-  bool tDest = ARM::tGPRRegClass.contains(DestReg);
-  bool tSrc  = ARM::tGPRRegClass.contains(SrcReg);
-  unsigned Opc = ARM::tMOVgpr2gpr;
-  if (tDest && tSrc)
-    Opc = ARM::tMOVr;
-  else if (tSrc)
-    Opc = ARM::tMOVtgpr2gpr;
-  else if (tDest)
-    Opc = ARM::tMOVgpr2tgpr;
-
-  AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
+  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
     .addReg(SrcReg, getKillRegState(KillSrc)));
   assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
          "Thumb1 can only copy GPR registers");

Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Thu Jun 30 18:38:17 2011
@@ -417,7 +417,7 @@
     unsigned PredReg;
     if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
       // Turn it into a move.
-      MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
+      MI.setDesc(TII.get(ARM::tMOVr));
       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
       // Remove offset and add predicate operands.
       MI.RemoveOperand(FrameRegIdx+1);
@@ -564,7 +564,7 @@
   // the function, the offset will be negative. Use R12 instead since that's
   // a call clobbered register that we know won't be used in Thumb1 mode.
   DebugLoc DL;
-  AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr))
+  AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
     .addReg(ARM::R12, RegState::Define)
     .addReg(Reg, RegState::Kill));
 
@@ -589,7 +589,7 @@
     }
   }
   // Restore the register from R12
-  AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
+  AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
     addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
 
   return true;

Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=134204&r1=134203&r2=134204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Thu Jun 30 18:38:17 2011
@@ -98,9 +98,6 @@
   case ARM::MOVr:
   case ARM::MOVr_TC:
   case ARM::tMOVr:
-  case ARM::tMOVgpr2tgpr:
-  case ARM::tMOVtgpr2gpr:
-  case ARM::tMOVgpr2gpr:
   case ARM::t2MOVr:
     return true;
   }

Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Thu Jun 30 18:38:17 2011
@@ -112,17 +112,7 @@
   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
 
-  bool tDest = ARM::tGPRRegClass.contains(DestReg);
-  bool tSrc  = ARM::tGPRRegClass.contains(SrcReg);
-  unsigned Opc = ARM::tMOVgpr2gpr;
-  if (tDest && tSrc)
-    Opc = ARM::tMOVr;
-  else if (tSrc)
-    Opc = ARM::tMOVtgpr2gpr;
-  else if (tDest)
-    Opc = ARM::tMOVgpr2tgpr;
-
-  AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
+  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
     .addReg(SrcReg, getKillRegState(KillSrc)));
 }
 
@@ -231,7 +221,7 @@
     unsigned Opc = 0;
     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
       // mov sp, rn. Note t2MOVr cannot be used.
-      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg)
+      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
         .addReg(BaseReg).setMIFlags(MIFlags));
       BaseReg = ARM::SP;
       continue;
@@ -409,7 +399,7 @@
     unsigned PredReg;
     if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
       // Turn it into a move.
-      MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
+      MI.setDesc(TII.get(ARM::tMOVr));
       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
       // Remove offset and remaining explicit predicate operands.
       do MI.RemoveOperand(FrameRegIdx+1);
@@ -575,8 +565,7 @@
 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
                                        MachineInstr *UseMI,
                                        const TargetRegisterInfo &TRI) const {
-  if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
-      SrcMI->getOperand(1).isKill())
+  if (SrcMI->getOpcode() != ARM::tMOVr || SrcMI->getOperand(1).isKill())
     return;
 
   unsigned PredReg = 0;

Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134204&r1=134203&r2=134204&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Thu Jun 30 18:38:17 2011
@@ -82,7 +82,7 @@
     { ARM::t2MOVi,  ARM::tMOVi8,  0,             8,   0,    1,   0,  0,0, 0,0 },
     { ARM::t2MOVi16,ARM::tMOVi8,  0,             8,   0,    1,   0,  0,0, 0,1 },
     // FIXME: Do we need the 16-bit 'S' variant?
-    { ARM::t2MOVr,ARM::tMOVgpr2gpr,0,            0,   0,    0,   0,  1,0, 0,0 },
+    { ARM::t2MOVr,ARM::tMOVr,     0,             0,   0,    0,   0,  1,0, 0,0 },
     { ARM::t2MOVCCr,0,            ARM::tMOVCCr,  0,   0,    0,   0,  0,1, 0,0 },
     { ARM::t2MOVCCi,0,            ARM::tMOVCCi,  0,   8,    0,   1,  0,1, 0,0 },
     { ARM::t2MUL,   0,            ARM::tMUL,     0,   0,    0,   1,  0,0, 1,0 },



From stoklund at 2pi.dk  Thu Jun 30 18:42:19 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 30 Jun 2011 23:42:19 -0000
Subject: [llvm-commits] [llvm] r134205 - in /llvm/trunk:
 lib/Target/X86/X86FastISel.cpp test/CodeGen/X86/fp-stack-O0.ll
Message-ID: <20110630234219.0E3A62A6C12C@llvm.org>

Author: stoklund
Date: Thu Jun 30 18:42:18 2011
New Revision: 134205

URL: http://llvm.org/viewvc/llvm-project?rev=134205&view=rev
Log:
Fix a problem with fast-isel return values introduced in r134018.

We would put the return value from long double functions in the wrong
register.

This fixes gcc.c-torture/execute/conversion.c

Added:
    llvm/trunk/test/CodeGen/X86/fp-stack-O0.ll
Modified:
    llvm/trunk/lib/Target/X86/X86FastISel.cpp

Modified: llvm/trunk/lib/Target/X86/X86FastISel.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86FastISel.cpp?rev=134205&r1=134204&r2=134205&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86FastISel.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86FastISel.cpp Thu Jun 30 18:42:18 2011
@@ -1849,9 +1849,10 @@
     // out as F80 and use a truncate to move it from fp stack reg to xmm reg.
     if ((RVLocs[i].getLocReg() == X86::ST0 ||
          RVLocs[i].getLocReg() == X86::ST1)) {
-      if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT()))
+      if (isScalarFPTypeInSSEReg(RVLocs[i].getValVT())) {
         CopyVT = MVT::f80;
-      CopyReg = createResultReg(X86::RFP80RegisterClass);
+        CopyReg = createResultReg(X86::RFP80RegisterClass);
+      }
       BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::FpPOP_RETVAL),
               CopyReg);
     } else {

Added: llvm/trunk/test/CodeGen/X86/fp-stack-O0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/fp-stack-O0.ll?rev=134205&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/fp-stack-O0.ll (added)
+++ llvm/trunk/test/CodeGen/X86/fp-stack-O0.ll Thu Jun 30 18:42:18 2011
@@ -0,0 +1,24 @@
+; RUN: llc < %s -O0 | FileCheck %s
+target triple = "x86_64-apple-macosx"
+
+declare x86_fp80 @x1(i32) nounwind
+declare i32 @x2(x86_fp80, x86_fp80) nounwind
+
+; Keep track of the return value.
+; CHECK: test1
+; CHECK: x1
+; Pass arguments on the stack.
+; CHECK-NEXT: movq %rsp, [[RCX:%r..]]
+; Copy constant-pool value.
+; CHECK-NEXT: fldt LCPI
+; CHECK-NEXT: fstpt 16([[RCX]])
+; Copy x1 return value.
+; CHECK-NEXT: fstpt ([[RCX]])
+; CHECK-NEXT: x2
+define i32 @test1() nounwind uwtable ssp {
+entry:
+  %call = call x86_fp80 (...)* bitcast (x86_fp80 (i32)* @x1 to x86_fp80 (...)*)(i32 -1)
+  %call1 = call i32 @x2(x86_fp80 %call, x86_fp80 0xK401EFFFFFFFF00000000)
+  ret i32 %call1
+}
+



From aggarwa4 at illinois.edu  Thu Jun 30 18:44:55 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 30 Jun 2011 23:44:55 -0000
Subject: [llvm-commits] [poolalloc] r134206 - in /poolalloc/trunk:
 lib/AssistDS/TypeChecks.cpp runtime/DynamicTypeChecks/TypeRuntime.cpp
Message-ID: <20110630234455.792E82A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Jun 30 18:44:55 2011
New Revision: 134206

URL: http://llvm.org/viewvc/llvm-project?rev=134206&view=rev
Log:
Add more library functions.
Do not instrument stores if they come from
PHI, Select, Bitcasts, already instrumented through loads.

Modified:
    poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
    poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp

Modified: poolalloc/trunk/lib/AssistDS/TypeChecks.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/AssistDS/TypeChecks.cpp?rev=134206&r1=134205&r2=134206&view=diff
==============================================================================
--- poolalloc/trunk/lib/AssistDS/TypeChecks.cpp (original)
+++ poolalloc/trunk/lib/AssistDS/TypeChecks.cpp Thu Jun 30 18:44:55 2011
@@ -1531,6 +1531,15 @@
       Constant *F = M.getOrInsertFunction("trackgetaddrinfo", VoidTy, VoidPtrTy, Int32Ty, NULL);
       CallInst *CI = CallInst::Create(F, Args.begin(), Args.end());
       CI->insertAfter(BCI);
+    } else if (F->getNameStr() == std::string("mmap")) {
+      CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy);
+      BCI->insertAfter(I);
+      std::vector Args;
+      Args.push_back(BCI);
+      Args.push_back(CS.getArgument(1));
+      Args.push_back(getTagCounter());
+      CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end());
+      CI->insertAfter(BCI);
     } else if (F->getNameStr() == std::string("__strdup")) {
       CastInst *BCI_Dest = BitCastInst::CreatePointerCast(I, VoidPtrTy);
       BCI_Dest->insertAfter(I);
@@ -1590,6 +1599,16 @@
       Args.push_back(getTagCounter());
       CallInst *CI = CallInst::Create(trackInitInst, Args.begin(), Args.end());
       CI->insertAfter(BCI);
+    } else if (F->getNameStr() == std::string("gethostbyname") ||
+               F->getNameStr() == std::string("gethostbyaddr")) {
+      CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy);
+      BCI->insertAfter(I);
+      std::vectorArgs;
+      Args.push_back(BCI);
+      Args.push_back(getTagCounter());
+      Constant *F = M.getOrInsertFunction("trackgethostbyname", VoidTy, VoidPtrTy, Int32Ty, NULL);
+      CallInst *CI = CallInst::Create(F, Args.begin(), Args.end());
+      CI->insertAfter(BCI);
     } else if (F->getNameStr() == std::string("gethostname")) {
       CastInst *BCI  = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy);
       BCI->insertAfter(I);
@@ -1599,7 +1618,8 @@
       Constant *F = M.getOrInsertFunction("trackgethostname", VoidTy, VoidPtrTy, Int32Ty, NULL);
       CallInst *CI = CallInst::Create(F, Args.begin(), Args.end());
       CI->insertAfter(BCI);
-    } else if (F->getNameStr() == std::string("getenv")) {
+    } else if (F->getNameStr() == std::string("getenv") ||
+               F->getNameStr() == std::string("strerror")) {
       CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy);
       BCI->insertAfter(I);
       std::vectorArgs;
@@ -1723,15 +1743,26 @@
       Constant *F = M.getOrInsertFunction("trackReadLink", VoidTy, VoidPtrTy, I->getType(), Int32Ty, NULL);
       CallInst *CI = CallInst::Create(F, Args.begin(), Args.end());
       CI->insertAfter(I);
+    } else if (F->getNameStr() == std::string("pipe")) {
+      CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(0), VoidPtrTy, "", I);
+      std::vector Args;
+      Args.push_back(BCI);
+      Args.push_back(getTagCounter());
+      Constant *F = M.getOrInsertFunction("trackpipe", VoidTy, VoidPtrTy, Int32Ty, NULL);
+      CallInst::Create(F, Args.begin(), Args.end(), "", I);
+      return true;
     } else if (F->getNameStr() == std::string("getsockname")) {
-      CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy, "", I);
-      const PointerType *PTy = cast(CS.getArgument(1)->getType());
-      const Type * ElementType = PTy->getElementType();
+      CastInst *BCI = BitCastInst::CreatePointerCast(CS.getArgument(1), VoidPtrTy);
+      BCI->insertAfter(I);
+      CastInst *BCI_Size = BitCastInst::CreatePointerCast(CS.getArgument(2), VoidPtrTy);
+      BCI_Size->insertAfter(I);
       std::vector Args;
       Args.push_back(BCI);
-      Args.push_back(getSizeConstant(ElementType));
+      Args.push_back(BCI_Size);
       Args.push_back(getTagCounter());
-      CallInst::Create(trackInitInst, Args.begin(), Args.end(), "", I);
+      Constant *F = M.getOrInsertFunction("trackgetsockname", VoidTy, VoidPtrTy, VoidPtrTy, Int32Ty, NULL);
+      CallInst *CI = CallInst::Create(F, Args.begin(), Args.end());
+      CI->insertAfter(BCI);
       return true;
     } else if (F->getNameStr() == std::string("readdir")) {
       CastInst *BCI = BitCastInst::CreatePointerCast(I, VoidPtrTy);
@@ -2013,7 +2044,6 @@
           continue;
       }
     }
-
     std::vector Args;
     Args.push_back(getTypeMarkerConstant(I));
     Args.push_back(getSizeConstant(I->getType()));
@@ -2106,9 +2136,14 @@
         }
       }
     } else if(BitCastInst *BI = dyn_cast(II)) {
+      BitCast_MD_Map[BI] = AI;
       visitUses(BI, AI, BCI);
       //CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", cast(II.getUse().getUser()));
-    } else {
+    /*} else if(PtrToIntInst *P2I = dyn_cast(II)) {
+      visitUses(P2I, AI, BCI);
+    } else if(IntToPtrInst *I2P = dyn_cast(II)) {
+      visitUses(I2P, AI, BCI);*/
+    }else {
       CallInst::Create(checkTypeInst, Args.begin(), Args.end(), "", cast(II.getUse().getUser()));
     }
   }
@@ -2117,6 +2152,18 @@
 
 // Insert runtime checks before all store instructions.
 bool TypeChecks::visitStoreInst(Module &M, StoreInst &SI) {
+  if(PHINode *PH = dyn_cast(SI.getOperand(0)->stripPointerCasts())) {
+    if(PHINode_MD_Map.find(PH) != PHINode_MD_Map.end())
+      return false;
+  }
+  if(SelectInst *SelI = dyn_cast(SI.getOperand(0)->stripPointerCasts())) {
+    if(SelectInst_MD_Map.find(SelI) != SelectInst_MD_Map.end())
+      return false;
+  }
+  if(BitCastInst *BI = dyn_cast(SI.getOperand(0)->stripPointerCasts())) {
+    if(BitCast_MD_Map.find(BI) != BitCast_MD_Map.end())
+      return false;
+  }
   // Cast the pointer operand to i8* for the runtime function.
   CastInst *BCI = BitCastInst::CreatePointerCast(SI.getPointerOperand(), VoidPtrTy, "", &SI);
 

Modified: poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp?rev=134206&r1=134205&r2=134206&view=diff
==============================================================================
--- poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp (original)
+++ poolalloc/trunk/runtime/DynamicTypeChecks/TypeRuntime.cpp Thu Jun 30 18:44:55 2011
@@ -80,9 +80,12 @@
   void trackgetcwd(void *ptr, uint32_t tag) ;
   void trackgetpwuid(void *ptr, uint32_t tag) ;
   void trackgethostname(void *ptr, uint32_t tag) ;
+  void trackgethostbyname(void *ptr, uint32_t tag) ;
   void trackgetaddrinfo(void *ptr, uint32_t tag) ;
   void trackaccept(void *ptr, void *size,uint32_t tag) ;
+  void trackgetsockname(void *ptr, void *size,uint32_t tag) ;
   void trackpoll(void *ptr, uint64_t nfds, uint32_t tag) ;
+  void trackpipe(void *ptr, uint32_t tag) ;
   void trackReadLink(void *ptr, int64_t val, uint32_t tag) ;
 }
 
@@ -390,6 +393,24 @@
 void trackgethostname(void *ptr, uint32_t tag) {
   trackInitInst(ptr, strlen((const char *)ptr) + 1, tag);
 }
+void trackgethostbyname(void *ptr, uint32_t tag) {
+  struct hostent *hn = (struct hostent *)ptr;
+  trackInitInst(hn->h_name, strlen(hn->h_name) + 1, tag);
+  unsigned i;
+  for(i =0; hn->h_aliases[i] != NULL; i++) {
+    trackInitInst(&hn->h_aliases[i], sizeof(char*), tag);
+    trackInitInst(hn->h_aliases[i], hn->h_length, tag);
+  }
+  trackInitInst(&hn->h_aliases[i], sizeof(char*), tag);
+  trackInitInst(hn->h_aliases[i], hn->h_length, tag);
+  for(i = 0; hn->h_addr_list[i] != NULL; i++) {
+    trackInitInst(&hn->h_addr_list[i], sizeof(char*), tag);
+    trackInitInst(hn->h_addr_list[i], hn->h_length, tag);
+  }
+  trackInitInst(&hn->h_addr_list[i], sizeof(char*), tag);
+  trackInitInst(hn->h_addr_list[i], hn->h_length, tag);
+  trackInitInst(ptr, sizeof(struct hostent), tag);
+}
 
 void trackgetaddrinfo(void *ptr, uint32_t tag) {
   struct addrinfo *res;
@@ -407,6 +428,15 @@
   trackInitInst(ptr, (uint64_t)bytes, tag);
 }
 
+void trackgetsockname(void *ptr, void *size, uint32_t tag) {
+  int32_t bytes = *((int32_t*)size);
+  trackInitInst(ptr, (uint64_t)bytes, tag);
+}
+
+void trackpipe(void *ptr, uint32_t tag) {
+  trackInitInst(ptr, sizeof(int) * 2, tag);
+}
+
 void trackpoll(void *ptr, uint64_t nfds, uint32_t tag) {
   struct pollfd *fds = (struct pollfd *)ptr;
   unsigned i = 0;



From aggarwa4 at illinois.edu  Thu Jun 30 18:45:18 2011
From: aggarwa4 at illinois.edu (Arushi Aggarwal)
Date: Thu, 30 Jun 2011 23:45:18 -0000
Subject: [llvm-commits] [poolalloc] r134207 -
	/poolalloc/trunk/include/assistDS/TypeChecks.h
Message-ID: <20110630234518.95B842A6C12C@llvm.org>

Author: aggarwa4
Date: Thu Jun 30 18:45:18 2011
New Revision: 134207

URL: http://llvm.org/viewvc/llvm-project?rev=134207&view=rev
Log:
Change to track metadata for bitcasts in a map.

Modified:
    poolalloc/trunk/include/assistDS/TypeChecks.h

Modified: poolalloc/trunk/include/assistDS/TypeChecks.h
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/include/assistDS/TypeChecks.h?rev=134207&r1=134206&r2=134207&view=diff
==============================================================================
--- poolalloc/trunk/include/assistDS/TypeChecks.h (original)
+++ poolalloc/trunk/include/assistDS/TypeChecks.h Thu Jun 30 18:45:18 2011
@@ -44,6 +44,7 @@
   std::map SelectInst_BasePtr_Map;
   std::map PHINode_MD_Map;
   std::map PHINode_BasePtr_Map;
+  std::map BitCast_MD_Map;
 
   // Analysis from other passes.
   TargetData *TD;



From isanbard at gmail.com  Thu Jun 30 18:47:14 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 30 Jun 2011 23:47:14 -0000
Subject: [llvm-commits] [llvm] r134208 -
	/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
Message-ID: <20110630234714.561DE2A6C12C@llvm.org>

Author: void
Date: Thu Jun 30 18:47:14 2011
New Revision: 134208

URL: http://llvm.org/viewvc/llvm-project?rev=134208&view=rev
Log:
Use the correct registers on X86_64.

Modified:
    llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp?rev=134208&r1=134207&r2=134208&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86RegisterInfo.cpp Thu Jun 30 18:47:14 2011
@@ -110,10 +110,10 @@
 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum) const {
   switch (RegNum) {
   case X86::EBX: case X86::RBX: return 1;
-  case X86::ECX: case X86::RCX: return 2;
-  case X86::EDX: case X86::RDX: return 3;
-  case X86::EDI: case X86::RDI: return 4;
-  case X86::ESI: case X86::RSI: return 5;
+  case X86::ECX: case X86::R12: return 2;
+  case X86::EDX: case X86::R13: return 3;
+  case X86::EDI: case X86::R14: return 4;
+  case X86::ESI: case X86::R15: return 5;
   case X86::EBP: case X86::RBP: return 6;
   }
 



From isanbard at gmail.com  Thu Jun 30 18:47:40 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 30 Jun 2011 23:47:40 -0000
Subject: [llvm-commits] [llvm] r134209 - /llvm/trunk/lib/MC/MCDwarf.cpp
Message-ID: <20110630234740.D5A232A6C12C@llvm.org>

Author: void
Date: Thu Jun 30 18:47:40 2011
New Revision: 134209

URL: http://llvm.org/viewvc/llvm-project?rev=134209&view=rev
Log:
Improve comment: Show the register the DWARF label is added to.

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=134209&r1=134208&r2=134209&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Thu Jun 30 18:47:40 2011
@@ -621,7 +621,8 @@
       if (VerboseAsm) Streamer.AddComment(Twine("Offset ") + Twine(Offset));
       Streamer.EmitSLEB128IntValue(Offset);
     } else if (Reg < 64) {
-      if (VerboseAsm) Streamer.AddComment("DW_CFA_offset");
+      if (VerboseAsm) Streamer.AddComment(Twine("DW_CFA_offset + Reg(") +
+                                          Twine(Reg) + ")");
       Streamer.EmitIntValue(dwarf::DW_CFA_offset + Reg, 1);
       if (VerboseAsm) Streamer.AddComment(Twine("Offset ") + Twine(Offset));
       Streamer.EmitULEB128IntValue(Offset);



From echristo at apple.com  Thu Jun 30 18:50:52 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 30 Jun 2011 23:50:52 -0000
Subject: [llvm-commits] [llvm] r134210 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20110630235052.B61292A6C12C@llvm.org>

Author: echristo
Date: Thu Jun 30 18:50:52 2011
New Revision: 134210

URL: http://llvm.org/viewvc/llvm-project?rev=134210&view=rev
Log:
Rename Pair to RCPair lacking any better naming ideas.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134210&r1=134209&r2=134210&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 18:50:52 2011
@@ -7528,8 +7528,8 @@
   return weight;
 }
 
-typedef std::pair Pair;
-Pair
+typedef std::pair RCPair;
+RCPair
 ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
                                                 EVT VT) const {
   if (Constraint.size() == 1) {
@@ -7537,23 +7537,23 @@
     switch (Constraint[0]) {
     case 'l': // Low regs or general regs.
       if (Subtarget->isThumb())
-        return Pair(0U, ARM::tGPRRegisterClass);
+        return RCPair(0U, ARM::tGPRRegisterClass);
       else
-        return Pair(0U, ARM::GPRRegisterClass);
+        return RCPair(0U, ARM::GPRRegisterClass);
     case 'h': // High regs or no regs.
       if (Subtarget->isThumb())
-	return Pair(0U, ARM::hGPRRegisterClass);
+	return RCPair(0U, ARM::hGPRRegisterClass);
       else
-	return Pair(0u, static_cast(0));
+	return RCPair(0u, static_cast(0));
     case 'r':
-      return Pair(0U, ARM::GPRRegisterClass);
+      return RCPair(0U, ARM::GPRRegisterClass);
     case 'w':
       if (VT == MVT::f32)
-        return Pair(0U, ARM::SPRRegisterClass);
+        return RCPair(0U, ARM::SPRRegisterClass);
       if (VT.getSizeInBits() == 64)
-        return Pair(0U, ARM::DPRRegisterClass);
+        return RCPair(0U, ARM::DPRRegisterClass);
       if (VT.getSizeInBits() == 128)
-        return Pair(0U, ARM::QPRRegisterClass);
+        return RCPair(0U, ARM::QPRRegisterClass);
       break;
     }
   }



From echristo at apple.com  Thu Jun 30 18:51:28 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 30 Jun 2011 16:51:28 -0700
Subject: [llvm-commits] [llvm] r134198 -
 /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
In-Reply-To: 
References: <20110630221701.F201E2A6C12C@llvm.org>
	
Message-ID: <3D5CD3BC-698A-462B-A491-1944276198E8@apple.com>


On Jun 30, 2011, at 3:24 PM, Jim Grosbach wrote:

> 
> On Jun 30, 2011, at 3:17 PM, Eric Christopher wrote:
> 
>> Author: echristo
>> Date: Thu Jun 30 17:17:01 2011
>> New Revision: 134198
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=134198&view=rev
>> Log:
>> Add a convenience typedef for std::pair.
>> 
>> No functional change.
>> 
>> Part of rdar://9119939
>> 
>> Modified:
>>   llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134198&r1=134197&r2=134198&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 17:17:01 2011
>> @@ -7527,7 +7527,8 @@
>>  return weight;
>> }
>> 
>> -std::pair
>> +typedef std::pair Pair;
>> +Pair
> 
> Mind giving the typedef a more informational name?

Lacking a better name you get this:

[yendi:Data/sources/llvm] echristo% svn ci
Sending        lib/Target/ARM/ARMISelLowering.cpp
Transmitting file data .
Committed revision 134210.

:)

-eric

From grosbach at apple.com  Thu Jun 30 18:53:22 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 30 Jun 2011 16:53:22 -0700
Subject: [llvm-commits] [llvm] r134198 -
 /llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
In-Reply-To: <3D5CD3BC-698A-462B-A491-1944276198E8@apple.com>
References: <20110630221701.F201E2A6C12C@llvm.org>
	
	<3D5CD3BC-698A-462B-A491-1944276198E8@apple.com>
Message-ID: 


On Jun 30, 2011, at 4:51 PM, Eric Christopher wrote:

> 
> On Jun 30, 2011, at 3:24 PM, Jim Grosbach wrote:
> 
>> 
>> On Jun 30, 2011, at 3:17 PM, Eric Christopher wrote:
>> 
>>> Author: echristo
>>> Date: Thu Jun 30 17:17:01 2011
>>> New Revision: 134198
>>> 
>>> URL: http://llvm.org/viewvc/llvm-project?rev=134198&view=rev
>>> Log:
>>> Add a convenience typedef for std::pair.
>>> 
>>> No functional change.
>>> 
>>> Part of rdar://9119939
>>> 
>>> Modified:
>>>  llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>> 
>>> Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
>>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134198&r1=134197&r2=134198&view=diff
>>> ==============================================================================
>>> --- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
>>> +++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 17:17:01 2011
>>> @@ -7527,7 +7527,8 @@
>>> return weight;
>>> }
>>> 
>>> -std::pair
>>> +typedef std::pair Pair;
>>> +Pair
>> 
>> Mind giving the typedef a more informational name?
> 
> Lacking a better name you get this:
> 
> [yendi:Data/sources/llvm] echristo% svn ci
> Sending        lib/Target/ARM/ARMISelLowering.cpp
> Transmitting file data .
> Committed revision 134210.
> 
> :)
Works for me. Now when I need to handle two remote control cars at once, I know where to look!

-j

From echristo at apple.com  Thu Jun 30 18:59:16 2011
From: echristo at apple.com (Eric Christopher)
Date: Thu, 30 Jun 2011 23:59:16 -0000
Subject: [llvm-commits] [llvm] r134211 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20110630235916.AEE712A6C12C@llvm.org>

Author: echristo
Date: Thu Jun 30 18:59:16 2011
New Revision: 134211

URL: http://llvm.org/viewvc/llvm-project?rev=134211&view=rev
Log:
Capitalize the unsigned part of the initializer.

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134211&r1=134210&r2=134211&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 18:59:16 2011
@@ -7544,7 +7544,7 @@
       if (Subtarget->isThumb())
 	return RCPair(0U, ARM::hGPRRegisterClass);
       else
-	return RCPair(0u, static_cast(0));
+	return RCPair(0U, static_cast(0));
     case 'r':
       return RCPair(0U, ARM::GPRRegisterClass);
     case 'w':



From isanbard at gmail.com  Thu Jun 30 18:59:38 2011
From: isanbard at gmail.com (Bill Wendling)
Date: Thu, 30 Jun 2011 23:59:38 -0000
Subject: [llvm-commits] [llvm] r134212 - /llvm/trunk/lib/MC/MCDwarf.cpp
Message-ID: <20110630235938.868212A6C12C@llvm.org>

Author: void
Date: Thu Jun 30 18:59:38 2011
New Revision: 134212

URL: http://llvm.org/viewvc/llvm-project?rev=134212&view=rev
Log:
Remove tabs.

Modified:
    llvm/trunk/lib/MC/MCDwarf.cpp

Modified: llvm/trunk/lib/MC/MCDwarf.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCDwarf.cpp?rev=134212&r1=134211&r2=134212&view=diff
==============================================================================
--- llvm/trunk/lib/MC/MCDwarf.cpp (original)
+++ llvm/trunk/lib/MC/MCDwarf.cpp Thu Jun 30 18:59:38 2011
@@ -30,23 +30,23 @@
 #define SPECIAL_ADDR(op) (((op) - DWARF2_LINE_OPCODE_BASE)/DWARF2_LINE_RANGE)
 
 // The maximum address skip amount that can be encoded with a special op.
-#define MAX_SPECIAL_ADDR_DELTA		SPECIAL_ADDR(255)
+#define MAX_SPECIAL_ADDR_DELTA         SPECIAL_ADDR(255)
 
 // First special line opcode - leave room for the standard opcodes.
 // Note: If you want to change this, you'll have to update the
 // "standard_opcode_lengths" table that is emitted in DwarfFileTable::Emit().  
-#define DWARF2_LINE_OPCODE_BASE		13
+#define DWARF2_LINE_OPCODE_BASE         13
 
 // Minimum line offset in a special line info. opcode.  This value
 // was chosen to give a reasonable range of values.
-#define DWARF2_LINE_BASE		-5
+#define DWARF2_LINE_BASE                -5
 
 // Range of line offsets in a special line info. opcode.
-# define DWARF2_LINE_RANGE		14
+#define DWARF2_LINE_RANGE               14
 
 // Define the architecture-dependent minimum instruction length (in bytes).
 // This value should be rather too small than too big.
-# define DWARF2_LINE_MIN_INSN_LENGTH	1
+#define DWARF2_LINE_MIN_INSN_LENGTH     1
 
 // Note: when DWARF2_LINE_MIN_INSN_LENGTH == 1 which is the current setting,
 // this routine is a nop and will be optimized away.
@@ -290,7 +290,7 @@
   const std::vector &MCLineSectionOrder =
     MCOS->getContext().getMCLineSectionOrder();
   for (std::vector::const_iterator it =
-	MCLineSectionOrder.begin(), ie = MCLineSectionOrder.end(); it != ie;
+         MCLineSectionOrder.begin(), ie = MCLineSectionOrder.end(); it != ie;
        ++it) {
     const MCSection *Sec = *it;
     const MCLineSection *Line = MCLineSections.lookup(Sec);



From echristo at apple.com  Thu Jun 30 19:14:47 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 01 Jul 2011 00:14:47 -0000
Subject: [llvm-commits] [llvm] r134215 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/inlineasm3.ll
Message-ID: <20110701001447.F21B02A6C12C@llvm.org>

Author: echristo
Date: Thu Jun 30 19:14:47 2011
New Revision: 134215

URL: http://llvm.org/viewvc/llvm-project?rev=134215&view=rev
Log:
Add support for the 'x' constraint.

Part of rdar://9307836 and rdar://9119939

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/inlineasm3.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134215&r1=134214&r2=134215&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 19:14:47 2011
@@ -7483,6 +7483,7 @@
     case 'l': return C_RegisterClass;
     case 'w': return C_RegisterClass;
     case 'h': return C_RegisterClass;
+    case 'x': return C_RegisterClass;
     }
   } else if (Constraint.size() == 2) {
     switch (Constraint[0]) {
@@ -7555,6 +7556,14 @@
       if (VT.getSizeInBits() == 128)
         return RCPair(0U, ARM::QPRRegisterClass);
       break;
+    case 'x':
+      if (VT == MVT::f32)
+	return RCPair(0U, ARM::SPR_8RegisterClass);
+      if (VT.getSizeInBits() == 64)
+	return RCPair(0U, ARM::DPR_8RegisterClass);
+      if (VT.getSizeInBits() == 128)
+	return RCPair(0U, ARM::QPR_8RegisterClass);
+      break;
     }
   }
   if (StringRef("{cc}").equals_lower(Constraint))

Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=134215&r1=134214&r2=134215&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Thu Jun 30 19:14:47 2011
@@ -58,3 +58,13 @@
 call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind
 ret i32 0
 }
+
+; Radar 9307836 & 9119939
+
+define float @t6(float %y) nounwind {
+entry:
+; CHECK: t6
+; CHECK: flds s15, s0
+  %0 = tail call float asm "flds s15, $0", "=x"() nounwind
+  ret float %0
+}



From eli.friedman at gmail.com  Thu Jun 30 19:16:51 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 30 Jun 2011 17:16:51 -0700
Subject: [llvm-commits] [llvm] r134204 - in /llvm/trunk/lib/Target/ARM:
 ARMAsmPrinter.cpp ARMFrameLowering.cpp ARMInstrThumb.td
 Thumb1FrameLowering.cpp Thumb1InstrInfo.cpp Thumb1RegisterInfo.cpp
 Thumb2ITBlockPass.cpp Thumb2InstrInfo.cpp Thumb2SizeReductio
Message-ID: 

On Thu, Jun 30, 2011 at 4:38 PM, Jim Grosbach  wrote:
> Author: grosbach
> Date: Thu Jun 30 18:38:17 2011
> New Revision: 134204
>
> URL: http://llvm.org/viewvc/llvm-project?rev=134204&view=rev
> Log:
> Refact ARM Thumb1 tMOVr instruction family.
>
> Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
> into tMOVr. There's no need to keep them separate. Giving the tMOVr
> instruction the proper GPR register class for its operands is sufficient
> to give the register allocator enough information to do the right thing
> directly.

Does this account for the fact that "mov r1, r2" is illegal on pre-v6
Thumb1 implementations?

-Eli

> Modified:
> ? ?llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> ? ?llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
> ? ?llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> ? ?llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
> ? ?llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
> ? ?llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
> ? ?llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
> ? ?llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
> ? ?llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
>
> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Jun 30 18:38:17 2011
> @@ -1010,8 +1010,6 @@
> ? ? ? ? MI->dump();
> ? ? ? ? assert(0 && "Unsupported opcode for unwinding information");
> ? ? ? case ARM::MOVr:
> - ? ? ?case ARM::tMOVgpr2gpr:
> - ? ? ?case ARM::tMOVgpr2tgpr:
> ? ? ? ? Offset = 0;
> ? ? ? ? break;
> ? ? ? case ARM::ADDri:
> @@ -1456,7 +1454,7 @@
> ? case ARM::t2BR_JT: {
> ? ? // Lower and emit the instruction itself, then the jump table following it.
> ? ? MCInst TmpInst;
> - ? ?TmpInst.setOpcode(ARM::tMOVgpr2gpr);
> + ? ?TmpInst.setOpcode(ARM::tMOVr);
> ? ? TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
> ? ? TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
> ? ? // Add predicate operands.
> @@ -1505,7 +1503,7 @@
> ? ? // mov pc, target
> ? ? MCInst TmpInst;
> ? ? unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
> - ? ? ?ARM::MOVr : ARM::tMOVgpr2gpr;
> + ? ? ?ARM::MOVr : ARM::tMOVr;
> ? ? TmpInst.setOpcode(Opc);
> ? ? TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
> ? ? TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
> @@ -1518,7 +1516,7 @@
> ? ? OutStreamer.EmitInstruction(TmpInst);
>
> ? ? // Make sure the Thumb jump table is 4-byte aligned.
> - ? ?if (Opc == ARM::tMOVgpr2gpr)
> + ? ?if (Opc == ARM::tMOVr)
> ? ? ? EmitAlignment(2);
>
> ? ? // Output the data for the jump table itself
> @@ -1610,7 +1608,7 @@
> ? ? MCSymbol *Label = GetARMSJLJEHLabel();
> ? ? {
> ? ? ? MCInst TmpInst;
> - ? ? ?TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
> + ? ? ?TmpInst.setOpcode(ARM::tMOVr);
> ? ? ? TmpInst.addOperand(MCOperand::CreateReg(ValReg));
> ? ? ? TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
> ? ? ? // Predicate.
> @@ -1829,7 +1827,7 @@
> ? ? }
> ? ? {
> ? ? ? MCInst TmpInst;
> - ? ? ?TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
> + ? ? ?TmpInst.setOpcode(ARM::tMOVr);
> ? ? ? TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
> ? ? ? TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
> ? ? ? // Predicate.
>
> Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Jun 30 18:38:17 2011
> @@ -268,13 +268,13 @@
> ? ? ? // bic r4, r4, MaxAlign
> ? ? ? // mov sp, r4
> ? ? ? // FIXME: It will be better just to find spare register here.
> - ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
> + ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
> ? ? ? ? .addReg(ARM::SP, RegState::Kill));
> ? ? ? AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TII.get(ARM::t2BICri), ARM::R4)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? .addReg(ARM::R4, RegState::Kill)
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? .addImm(MaxAlign-1)));
> - ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
> + ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
> ? ? ? ? .addReg(ARM::R4, RegState::Kill));
> ? ? }
>
> @@ -293,7 +293,7 @@
> ? ? ? ? .addReg(ARM::SP)
> ? ? ? ? .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
> ? ? else
> - ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
> + ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?RegInfo->getBaseRegister())
> ? ? ? ? .addReg(ARM::SP));
> ? }
> @@ -364,7 +364,7 @@
> ? ? ? ? ? ? ? ? ?"No scratch register to restore SP from FP!");
> ? ? ? ? ? emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ARMCC::AL, 0, TII);
> - ? ? ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
> + ? ? ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ARM::SP)
> ? ? ? ? ? ? .addReg(ARM::R4));
> ? ? ? ? }
> @@ -374,7 +374,7 @@
> ? ? ? ? ? BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
> ? ? ? ? ? ? .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
> ? ? ? ? else
> - ? ? ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
> + ? ? ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ARM::SP)
> ? ? ? ? ? ? .addReg(FramePtr));
> ? ? ? }
>
> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Jun 30 18:38:17 2011
> @@ -1054,15 +1054,15 @@
> ?// TODO: A7-73: MOV(2) - mov setting flag.
>
> ?let neverHasSideEffects = 1 in {
> -def tMOVr : Thumb1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
> +def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
> ? ? ? ? ? ? ? ? ? ? ? Size2Bytes, IIC_iMOVr,
> ? ? ? ? ? ? ? ? ? ? ? "mov", "\t$Rd, $Rm", "", []>,
> - ? ? ? ? ? ? ? ? ?T1Special<0b1000> {
> + ? ? ? ? ? ? ? ? ?T1Special<{1,0,?,?}> {
> ? // A8.6.97
> ? bits<4> Rd;
> ? bits<4> Rm;
> - ?// Bits {7-6} are encoded by the T1Special value.
> - ?let Inst{5-3} = Rm{2-0};
> + ?let Inst{7} ? = Rd{3};
> + ?let Inst{6-3} = Rm;
> ? let Inst{2-0} = Rd{2-0};
> ?}
> ?let Defs = [CPSR] in
> @@ -1075,40 +1075,6 @@
> ? let Inst{5-3} ?= Rm;
> ? let Inst{2-0} ?= Rd;
> ?}
> -
> -// FIXME: Do we really need separate instructions for GPR<-->tGPR like this?
> -// ? ? ? ?They all map to the same instruction (MOV encoding T1).
> -def tMOVgpr2tgpr : Thumb1pI<(outs tGPR:$Rd), (ins GPR:$Rm), AddrModeNone,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ?Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
> - ? ? ? ? ? ? ? ? ? T1Special<{1,0,0,?}> {
> - ?// A8.6.97
> - ?bits<4> Rd;
> - ?bits<4> Rm;
> - ?// Bit {7} is encoded by the T1Special value.
> - ?let Inst{6-3} = Rm;
> - ?let Inst{2-0} = Rd{2-0};
> -}
> -def tMOVtgpr2gpr : Thumb1pI<(outs GPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ?Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
> - ? ? ? ? ? ? ? ? ? T1Special<{1,0,?,0}> {
> - ?// A8.6.97
> - ?bits<4> Rd;
> - ?bits<4> Rm;
> - ?// Bit {6} is encoded by the T1Special value.
> - ?let Inst{7} ? = Rd{3};
> - ?let Inst{5-3} = Rm{2-0};
> - ?let Inst{2-0} = Rd{2-0};
> -}
> -def tMOVgpr2gpr ?: Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ?Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
> - ? ? ? ? ? ? ? ? ? T1Special<{1,0,?,?}> {
> - ?// A8.6.97
> - ?bits<4> Rd;
> - ?bits<4> Rm;
> - ?let Inst{7} ? = Rd{3};
> - ?let Inst{6-3} = Rm;
> - ?let Inst{2-0} = Rd{2-0};
> -}
> ?} // neverHasSideEffects
>
> ?// Multiply register
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Thu Jun 30 18:38:17 2011
> @@ -160,7 +160,7 @@
> ? // will be allocated after this, so we can still use the base pointer
> ? // to reference locals.
> ? if (RegInfo->hasBasePointer(MF))
> - ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
> + ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
> ? ? ? ? ? ? ? ? ? ?.addReg(ARM::SP));
>
> ? // If the frame has variable sized objects then the epilogue must restore
> @@ -240,11 +240,11 @@
> ? ? ? ? ? ? ? ?"No scratch register to restore SP from FP!");
> ? ? ? ? emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? TII, *RegInfo);
> - ? ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
> + ? ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ARM::SP)
> ? ? ? ? ? .addReg(ARM::R4));
> ? ? ? } else
> - ? ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
> + ? ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?ARM::SP)
> ? ? ? ? ? .addReg(FramePtr));
> ? ? } else {
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Thu Jun 30 18:38:17 2011
> @@ -36,17 +36,7 @@
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? MachineBasicBlock::iterator I, DebugLoc DL,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? unsigned DestReg, unsigned SrcReg,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? bool KillSrc) const {
> - ?bool tDest = ARM::tGPRRegClass.contains(DestReg);
> - ?bool tSrc ?= ARM::tGPRRegClass.contains(SrcReg);
> - ?unsigned Opc = ARM::tMOVgpr2gpr;
> - ?if (tDest && tSrc)
> - ? ?Opc = ARM::tMOVr;
> - ?else if (tSrc)
> - ? ?Opc = ARM::tMOVtgpr2gpr;
> - ?else if (tDest)
> - ? ?Opc = ARM::tMOVgpr2tgpr;
> -
> - ?AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
> + ?AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
> ? ? .addReg(SrcReg, getKillRegState(KillSrc)));
> ? assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
> ? ? ? ? ?"Thumb1 can only copy GPR registers");
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Thu Jun 30 18:38:17 2011
> @@ -417,7 +417,7 @@
> ? ? unsigned PredReg;
> ? ? if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
> ? ? ? // Turn it into a move.
> - ? ? ?MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
> + ? ? ?MI.setDesc(TII.get(ARM::tMOVr));
> ? ? ? MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
> ? ? ? // Remove offset and add predicate operands.
> ? ? ? MI.RemoveOperand(FrameRegIdx+1);
> @@ -564,7 +564,7 @@
> ? // the function, the offset will be negative. Use R12 instead since that's
> ? // a call clobbered register that we know won't be used in Thumb1 mode.
> ? DebugLoc DL;
> - ?AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr))
> + ?AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
> ? ? .addReg(ARM::R12, RegState::Define)
> ? ? .addReg(Reg, RegState::Kill));
>
> @@ -589,7 +589,7 @@
> ? ? }
> ? }
> ? // Restore the register from R12
> - ?AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
> + ?AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
> ? ? addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
>
> ? return true;
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Thu Jun 30 18:38:17 2011
> @@ -98,9 +98,6 @@
> ? case ARM::MOVr:
> ? case ARM::MOVr_TC:
> ? case ARM::tMOVr:
> - ?case ARM::tMOVgpr2tgpr:
> - ?case ARM::tMOVtgpr2gpr:
> - ?case ARM::tMOVgpr2gpr:
> ? case ARM::t2MOVr:
> ? ? return true;
> ? }
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Thu Jun 30 18:38:17 2011
> @@ -112,17 +112,7 @@
> ? if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
> ? ? return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
>
> - ?bool tDest = ARM::tGPRRegClass.contains(DestReg);
> - ?bool tSrc ?= ARM::tGPRRegClass.contains(SrcReg);
> - ?unsigned Opc = ARM::tMOVgpr2gpr;
> - ?if (tDest && tSrc)
> - ? ?Opc = ARM::tMOVr;
> - ?else if (tSrc)
> - ? ?Opc = ARM::tMOVtgpr2gpr;
> - ?else if (tDest)
> - ? ?Opc = ARM::tMOVgpr2tgpr;
> -
> - ?AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
> + ?AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
> ? ? .addReg(SrcReg, getKillRegState(KillSrc)));
> ?}
>
> @@ -231,7 +221,7 @@
> ? ? unsigned Opc = 0;
> ? ? if (DestReg == ARM::SP && BaseReg != ARM::SP) {
> ? ? ? // mov sp, rn. Note t2MOVr cannot be used.
> - ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg)
> + ? ? ?AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
> ? ? ? ? .addReg(BaseReg).setMIFlags(MIFlags));
> ? ? ? BaseReg = ARM::SP;
> ? ? ? continue;
> @@ -409,7 +399,7 @@
> ? ? unsigned PredReg;
> ? ? if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
> ? ? ? // Turn it into a move.
> - ? ? ?MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
> + ? ? ?MI.setDesc(TII.get(ARM::tMOVr));
> ? ? ? MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
> ? ? ? // Remove offset and remaining explicit predicate operands.
> ? ? ? do MI.RemoveOperand(FrameRegIdx+1);
> @@ -575,8 +565,7 @@
> ?Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?MachineInstr *UseMI,
> ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?const TargetRegisterInfo &TRI) const {
> - ?if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
> - ? ? ?SrcMI->getOperand(1).isKill())
> + ?if (SrcMI->getOpcode() != ARM::tMOVr || SrcMI->getOperand(1).isKill())
> ? ? return;
>
> ? unsigned PredReg = 0;
>
> Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134204&r1=134203&r2=134204&view=diff
> ==============================================================================
> --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
> +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Thu Jun 30 18:38:17 2011
> @@ -82,7 +82,7 @@
> ? ? { ARM::t2MOVi, ?ARM::tMOVi8, ?0, ? ? ? ? ? ? 8, ? 0, ? ?1, ? 0, ?0,0, 0,0 },
> ? ? { ARM::t2MOVi16,ARM::tMOVi8, ?0, ? ? ? ? ? ? 8, ? 0, ? ?1, ? 0, ?0,0, 0,1 },
> ? ? // FIXME: Do we need the 16-bit 'S' variant?
> - ? ?{ ARM::t2MOVr,ARM::tMOVgpr2gpr,0, ? ? ? ? ? ?0, ? 0, ? ?0, ? 0, ?1,0, 0,0 },
> + ? ?{ ARM::t2MOVr,ARM::tMOVr, ? ? 0, ? ? ? ? ? ? 0, ? 0, ? ?0, ? 0, ?1,0, 0,0 },
> ? ? { ARM::t2MOVCCr,0, ? ? ? ? ? ?ARM::tMOVCCr, ?0, ? 0, ? ?0, ? 0, ?0,1, 0,0 },
> ? ? { ARM::t2MOVCCi,0, ? ? ? ? ? ?ARM::tMOVCCi, ?0, ? 8, ? ?0, ? 1, ?0,1, 0,0 },
> ? ? { ARM::t2MUL, ? 0, ? ? ? ? ? ?ARM::tMUL, ? ? 0, ? 0, ? ?0, ? 1, ?0,0, 1,0 },
>
>
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> llvm-commits at cs.uiuc.edu
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>


From rafael.espindola at gmail.com  Thu Jun 30 19:16:55 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 01 Jul 2011 00:16:55 -0000
Subject: [llvm-commits] [llvm] r134216 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
Message-ID: <20110701001655.36D6D2A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 30 19:16:54 2011
New Revision: 134216

URL: http://llvm.org/viewvc/llvm-project?rev=134216&view=rev
Log:
Add 134199 back, but disable the optimization when the second copy is a kill.

Modified:
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=134216&r1=134215&r2=134216&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Thu Jun 30 19:16:54 2011
@@ -1187,6 +1187,70 @@
   return ThisValNoAssignments[VN] = UltimateVN;
 }
 
+
+// Find out if we have something like
+// A = X
+// B = X
+// if so, we can pretend this is actually
+// A = X
+// B = A
+// which allows us to coalesce A and B.
+// MI is the definition of B. LR is the life range of A that includes
+// the slot just before B. If we return true, we add "B = X" to DupCopies.
+static bool RegistersDefinedFromSameValue(const TargetRegisterInfo &tri,
+                                          CoalescerPair &CP, MachineInstr *MI,
+                                          LiveRange *LR,
+                                     SmallVector &DupCopies) {
+  // FIXME: This is very conservative. For example, we don't handle
+  // physical registers.
+
+  if (!MI->isFullCopy() || CP.isPartial() || CP.isPhys())
+    return false;
+
+  // FIXME: If "B = X" kills X, we have to move the kill back to its
+  // previous use. For now we just avoid the optimization in that case.
+  if (MI->getOperand(1).isKill())
+    return false;
+
+  unsigned Dst = MI->getOperand(0).getReg();
+  unsigned Src = MI->getOperand(1).getReg();
+
+  if (!TargetRegisterInfo::isVirtualRegister(Src) ||
+      !TargetRegisterInfo::isVirtualRegister(Dst))
+    return false;
+
+  unsigned A = CP.getDstReg();
+  unsigned B = CP.getSrcReg();
+
+  if (B == Dst)
+    std::swap(A, B);
+  assert(Dst == A);
+
+  VNInfo *Other = LR->valno;
+  if (!Other->isDefByCopy())
+    return false;
+  const MachineInstr *OtherMI = Other->getCopy();
+
+  if (!OtherMI->isFullCopy())
+    return false;
+
+  unsigned OtherDst = OtherMI->getOperand(0).getReg();
+  unsigned OtherSrc = OtherMI->getOperand(1).getReg();
+
+  if (!TargetRegisterInfo::isVirtualRegister(OtherSrc) ||
+      !TargetRegisterInfo::isVirtualRegister(OtherDst))
+    return false;
+
+  assert(OtherDst == B);
+
+  if (Src != OtherSrc)
+    return false;
+
+  DupCopies.push_back(MI);
+
+  return true;
+}
+
 /// JoinIntervals - Attempt to join these two intervals.  On failure, this
 /// returns false.
 bool RegisterCoalescer::JoinIntervals(CoalescerPair &CP) {
@@ -1242,6 +1306,8 @@
   DenseMap RHSValsDefinedFromLHS;
   SmallVector NewVNInfo;
 
+  SmallVector DupCopies;
+
   LiveInterval &LHS = li_->getOrCreateInterval(CP.getDstReg());
   DEBUG({ dbgs() << "\t\tLHS = "; LHS.print(dbgs(), tri_); dbgs() << "\n"; });
 
@@ -1257,15 +1323,18 @@
     if (VNI->hasRedefByEC())
       return false;
 
-    // DstReg is known to be a register in the LHS interval.  If the src is
-    // from the RHS interval, we can use its value #.
-    if (!CP.isCoalescable(VNI->getCopy()))
-      continue;
-
     // Figure out the value # from the RHS.
     LiveRange *lr = RHS.getLiveRangeContaining(VNI->def.getPrevSlot());
     // The copy could be to an aliased physreg.
     if (!lr) continue;
+
+    // DstReg is known to be a register in the LHS interval.  If the src is
+    // from the RHS interval, we can use its value #.
+    MachineInstr *MI = VNI->getCopy();
+    if (!CP.isCoalescable(MI) &&
+        !RegistersDefinedFromSameValue(*tri_, CP, MI, lr, DupCopies))
+      continue;
+
     LHSValsDefinedFromRHS[VNI] = lr->valno;
   }
 
@@ -1281,15 +1350,18 @@
     if (VNI->hasRedefByEC())
       return false;
 
-    // DstReg is known to be a register in the RHS interval.  If the src is
-    // from the LHS interval, we can use its value #.
-    if (!CP.isCoalescable(VNI->getCopy()))
-      continue;
-
     // Figure out the value # from the LHS.
     LiveRange *lr = LHS.getLiveRangeContaining(VNI->def.getPrevSlot());
     // The copy could be to an aliased physreg.
     if (!lr) continue;
+
+    // DstReg is known to be a register in the RHS interval.  If the src is
+    // from the LHS interval, we can use its value #.
+    MachineInstr *MI = VNI->getCopy();
+    if (!CP.isCoalescable(MI) &&
+        !RegistersDefinedFromSameValue(*tri_, CP, MI, lr, DupCopies))
+        continue;
+
     RHSValsDefinedFromLHS[VNI] = lr->valno;
   }
 
@@ -1394,6 +1466,24 @@
   if (RHSValNoAssignments.empty())
     RHSValNoAssignments.push_back(-1);
 
+  for (SmallVector::iterator I = DupCopies.begin(),
+         E = DupCopies.end(); I != E; ++I) {
+    MachineInstr *MI = *I;
+
+    // We have pretended that the assignment to B in
+    // A = X
+    // B = X
+    // was actually a copy from A. Now that we decided to coalesce A and B,
+    // transform the code into
+    // A = X
+    // X = X
+    // and mark the X as coalesced to keep the illusion.
+    unsigned Src = MI->getOperand(1).getReg();
+    MI->getOperand(0).substVirtReg(Src, 0, *tri_);
+
+    markAsJoined(MI);
+  }
+
   // If we get here, we know that we can coalesce the live ranges.  Ask the
   // intervals to coalesce themselves now.
   LHS.join(RHS, &LHSValNoAssignments[0], &RHSValNoAssignments[0], NewVNInfo,



From echristo at apple.com  Thu Jun 30 19:19:27 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 01 Jul 2011 00:19:27 -0000
Subject: [llvm-commits] [llvm] r134217 -
	/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
Message-ID: <20110701001928.08CB02A6C12C@llvm.org>

Author: echristo
Date: Thu Jun 30 19:19:27 2011
New Revision: 134217

URL: http://llvm.org/viewvc/llvm-project?rev=134217&view=rev
Log:
We'll return a null RC by default if we can't match.

Part of rdar://9119939

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134217&r1=134216&r2=134217&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 19:19:27 2011
@@ -7544,8 +7544,7 @@
     case 'h': // High regs or no regs.
       if (Subtarget->isThumb())
 	return RCPair(0U, ARM::hGPRRegisterClass);
-      else
-	return RCPair(0U, static_cast(0));
+      break;
     case 'r':
       return RCPair(0U, ARM::GPRRegisterClass);
     case 'w':



From evan.cheng at apple.com  Thu Jun 30 19:23:10 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 01 Jul 2011 00:23:10 -0000
Subject: [llvm-commits] [llvm] r134219 - in /llvm/trunk:
 include/llvm/MC/SubtargetFeature.h lib/MC/SubtargetFeature.cpp
Message-ID: <20110701002310.6045D2A6C12C@llvm.org>

Author: evancheng
Date: Thu Jun 30 19:23:10 2011
New Revision: 134219

URL: http://llvm.org/viewvc/llvm-project?rev=134219&view=rev
Log:
Switch SubtargetFeatures from std::string to StringRef.

Modified:
    llvm/trunk/include/llvm/MC/SubtargetFeature.h
    llvm/trunk/lib/MC/SubtargetFeature.cpp

Modified: llvm/trunk/include/llvm/MC/SubtargetFeature.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/SubtargetFeature.h?rev=134219&r1=134218&r2=134219&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/SubtargetFeature.h (original)
+++ llvm/trunk/include/llvm/MC/SubtargetFeature.h Thu Jun 30 19:23:10 2011
@@ -18,13 +18,13 @@
 #ifndef LLVM_MC_SUBTARGETFEATURE_H
 #define LLVM_MC_SUBTARGETFEATURE_H
 
-#include 
 #include 
 #include "llvm/ADT/Triple.h"
 #include "llvm/Support/DataTypes.h"
 
 namespace llvm {
   class raw_ostream;
+  class StringRef;
   
 //===----------------------------------------------------------------------===//
 ///
@@ -74,24 +74,23 @@
 class SubtargetFeatures {
   std::vector Features;    // Subtarget features as a vector
 public:
-  explicit SubtargetFeatures(const std::string &Initial = std::string());
+  explicit SubtargetFeatures(const StringRef Initial = "");
 
   /// Features string accessors.
-  std::string getString() const;
-  void setString(const std::string &Initial);
+  StringRef getString() const;
 
   /// Adding Features.
-  void AddFeature(const std::string &String, bool IsEnabled = true);
+  void AddFeature(const StringRef String, bool IsEnabled = true);
            
   /// Get feature bits of a CPU.
-  uint64_t getFeatureBits(const std::string &CPU,
+  uint64_t getFeatureBits(const StringRef CPU,
                           const SubtargetFeatureKV *CPUTable,
                           size_t CPUTableSize,
                           const SubtargetFeatureKV *FeatureTable,
                           size_t FeatureTableSize);
                          
   /// Get scheduling itinerary of a CPU.
-  void *getItinerary(const std::string &CPU,
+  void *getItinerary(const StringRef CPU,
                      const SubtargetInfoKV *Table, size_t TableSize);
   
   /// Print feature string.

Modified: llvm/trunk/lib/MC/SubtargetFeature.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/SubtargetFeature.cpp?rev=134219&r1=134218&r2=134219&view=diff
==============================================================================
--- llvm/trunk/lib/MC/SubtargetFeature.cpp (original)
+++ llvm/trunk/lib/MC/SubtargetFeature.cpp Thu Jun 30 19:23:10 2011
@@ -27,7 +27,7 @@
 
 /// hasFlag - Determine if a feature has a flag; '+' or '-'
 ///
-static inline bool hasFlag(const std::string &Feature) {
+static inline bool hasFlag(const StringRef Feature) {
   assert(!Feature.empty() && "Empty string");
   // Get first character
   char Ch = Feature[0];
@@ -37,13 +37,13 @@
 
 /// StripFlag - Return string stripped of flag.
 ///
-static inline std::string StripFlag(const std::string &Feature) {
+static inline std::string StripFlag(const StringRef Feature) {
   return hasFlag(Feature) ? Feature.substr(1) : Feature;
 }
 
 /// isEnabled - Return true if enable flag; '+'.
 ///
-static inline bool isEnabled(const std::string &Feature) {
+static inline bool isEnabled(const StringRef Feature) {
   assert(!Feature.empty() && "Empty string");
   // Get first character
   char Ch = Feature[0];
@@ -53,16 +53,19 @@
 
 /// PrependFlag - Return a string with a prepended flag; '+' or '-'.
 ///
-static inline std::string PrependFlag(const std::string &Feature,
-                                      bool IsEnabled) {
+static inline StringRef PrependFlag(const StringRef Feature,
+                                    bool IsEnabled) {
   assert(!Feature.empty() && "Empty string");
-  if (hasFlag(Feature)) return Feature;
-  return std::string(IsEnabled ? "+" : "-") + Feature;
+  if (hasFlag(Feature))
+    return Feature;
+  std::string Prefix = IsEnabled ? "+" : "-";
+  Prefix += Feature;
+  return StringRef(Prefix);
 }
 
 /// Split - Splits a string of comma separated items in to a vector of strings.
 ///
-static void Split(std::vector &V, const std::string &S) {
+static void Split(std::vector &V, const StringRef S) {
   if (S.empty())
     return;
 
@@ -106,7 +109,7 @@
 }
 
 /// Adding features.
-void SubtargetFeatures::AddFeature(const std::string &String,
+void SubtargetFeatures::AddFeature(const StringRef String,
                                    bool IsEnabled) {
   // Don't add empty features
   if (!String.empty()) {
@@ -116,10 +119,10 @@
 }
 
 /// Find KV in array using binary search.
-template const T *Find(const std::string &S, const T *A, size_t L) {
+template const T *Find(const StringRef S, const T *A, size_t L) {
   // Make the lower bound element we're looking for
   T KV;
-  KV.Key = S.c_str();
+  KV.Key = S.data();
   // Determine the end of the array
   const T *Hi = A + L;
   // Binary search the array
@@ -173,21 +176,15 @@
 //                    SubtargetFeatures Implementation
 //===----------------------------------------------------------------------===//
 
-SubtargetFeatures::SubtargetFeatures(const std::string &Initial) {
+SubtargetFeatures::SubtargetFeatures(const StringRef Initial) {
   // Break up string into separate features
   Split(Features, Initial);
 }
 
 
-std::string SubtargetFeatures::getString() const {
+StringRef SubtargetFeatures::getString() const {
   return Join(Features);
 }
-void SubtargetFeatures::setString(const std::string &Initial) {
-  // Throw out old features
-  Features.clear();
-  // Break up string into separate features
-  Split(Features, LowercaseString(Initial));
-}
 
 /// SetImpliedBits - For each feature that is (transitively) implied by this
 /// feature, set it.
@@ -229,7 +226,7 @@
 
 /// getFeatureBits - Get feature bits a CPU.
 ///
-uint64_t SubtargetFeatures::getFeatureBits(const std::string &CPU,
+uint64_t SubtargetFeatures::getFeatureBits(const StringRef CPU,
                                          const SubtargetFeatureKV *CPUTable,
                                          size_t CPUTableSize,
                                          const SubtargetFeatureKV *FeatureTable,
@@ -272,7 +269,7 @@
   }
   // Iterate through each feature
   for (size_t i = 0, E = Features.size(); i < E; i++) {
-    const std::string &Feature = Features[i];
+    const StringRef Feature = Features[i];
     
     // Check for help
     if (Feature == "+help")
@@ -306,7 +303,7 @@
 }
 
 /// Get scheduling itinerary of a CPU.
-void *SubtargetFeatures::getItinerary(const std::string &CPU,
+void *SubtargetFeatures::getItinerary(const StringRef CPU,
                                       const SubtargetInfoKV *Table,
                                       size_t TableSize) {
   assert(Table && "missing table");



From echristo at apple.com  Thu Jun 30 19:30:47 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 01 Jul 2011 00:30:47 -0000
Subject: [llvm-commits] [llvm] r134220 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/inlineasm3.ll
Message-ID: <20110701003047.262E42A6C12C@llvm.org>

Author: echristo
Date: Thu Jun 30 19:30:46 2011
New Revision: 134220

URL: http://llvm.org/viewvc/llvm-project?rev=134220&view=rev
Log:
Add support for the ARM 't' register constraint. And another testcase
for the 'x' register constraint.

Part of rdar://9119939

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/inlineasm3.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134220&r1=134219&r2=134220&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 19:30:46 2011
@@ -7484,6 +7484,7 @@
     case 'w': return C_RegisterClass;
     case 'h': return C_RegisterClass;
     case 'x': return C_RegisterClass;
+    case 't': return C_RegisterClass;
     }
   } else if (Constraint.size() == 2) {
     switch (Constraint[0]) {
@@ -7563,6 +7564,10 @@
       if (VT.getSizeInBits() == 128)
 	return RCPair(0U, ARM::QPR_8RegisterClass);
       break;
+    case 't':
+      if (VT == MVT::f32)
+	return RCPair(0U, ARM::SPRRegisterClass);
+      break;
     }
   }
   if (StringRef("{cc}").equals_lower(Constraint))

Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=134220&r1=134219&r2=134220&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Thu Jun 30 19:30:46 2011
@@ -68,3 +68,23 @@
   %0 = tail call float asm "flds s15, $0", "=x"() nounwind
   ret float %0
 }
+
+; Radar 9307836 & 9119939
+
+define double @t7(double %y) nounwind ssp {
+entry:
+; CHECK: t7
+; CHECK: flds s15, d0
+  %0 = tail call double asm "flds s15, $0", "=x"() nounwind
+  ret double %0
+}
+
+; Radar 9307836 & 9119939
+
+define float @t8(float %y) nounwind ssp {
+entry:
+; CHECK: t8
+; CHECK: flds s15, s0
+  %0 = tail call float asm "flds s15, $0", "=t"() nounwind
+  ret float %0
+}



From stoklund at 2pi.dk  Thu Jun 30 19:36:24 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 30 Jun 2011 17:36:24 -0700
Subject: [llvm-commits] [llvm] r134216 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
In-Reply-To: <20110701001655.36D6D2A6C12C@llvm.org>
References: <20110701001655.36D6D2A6C12C@llvm.org>
Message-ID: 


On Jun 30, 2011, at 5:16 PM, Rafael Espindola wrote:

> +  // FIXME: If "B = X" kills X, we have to move the kill back to its
> +  // previous use. For now we just avoid the optimization in that case.
> +  if (MI->getOperand(1).isKill())
> +    return false;

It's not so much the kill flags, they are actually recomputed after register allocation.

It is important that the live ranges are updated, though. You need to shrink X to its uses when you remove a use.

There doesn't have to be a kill flag: If you are removing the last use in a loop where X is not live out, it doesn't have to be live in the loop any more.

/jakob

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From gohman at apple.com  Thu Jun 30 19:42:17 2011
From: gohman at apple.com (Dan Gohman)
Date: Fri, 01 Jul 2011 00:42:17 -0000
Subject: [llvm-commits] [llvm] r134221 - in /llvm/trunk:
 lib/VMCore/ConstantFold.cpp test/Transforms/InstSimplify/binop.ll
Message-ID: <20110701004217.CFD102A6C12C@llvm.org>

Author: djg
Date: Thu Jun 30 19:42:17 2011
New Revision: 134221

URL: http://llvm.org/viewvc/llvm-project?rev=134221&view=rev
Log:
Improve constant folding of undef for binary operators.

Added:
    llvm/trunk/test/Transforms/InstSimplify/binop.ll
Modified:
    llvm/trunk/lib/VMCore/ConstantFold.cpp

Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=134221&r1=134220&r2=134221&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ConstantFold.cpp (original)
+++ llvm/trunk/lib/VMCore/ConstantFold.cpp Thu Jun 30 19:42:17 2011
@@ -1014,20 +1014,38 @@
     case Instruction::Add:
     case Instruction::Sub:
       return UndefValue::get(C1->getType());
-    case Instruction::Mul:
     case Instruction::And:
+      if (isa(C1) && isa(C2)) // undef & undef -> undef
+        return C1;
+      return Constant::getNullValue(C1->getType());   // undef & X -> 0
+    case Instruction::Mul: {
+      ConstantInt *CI;
+      // X * undef -> undef   if X is odd or undef
+      if (((CI = dyn_cast(C1)) && CI->getValue()[0]) ||
+          ((CI = dyn_cast(C2)) && CI->getValue()[0]) ||
+          (isa(C1) && isa(C2)))
+        return UndefValue::get(C1->getType());
+
+      // X * undef -> 0       otherwise
       return Constant::getNullValue(C1->getType());
+    }
     case Instruction::UDiv:
     case Instruction::SDiv:
+      // undef / 1 -> undef
+      if (Opcode == Instruction::UDiv || Opcode == Instruction::SDiv)
+        if (ConstantInt *CI2 = dyn_cast(C2))
+          if (CI2->isOne())
+            return C1;
+      // FALL THROUGH
     case Instruction::URem:
     case Instruction::SRem:
       if (!isa(C2))                    // undef / X -> 0
         return Constant::getNullValue(C1->getType());
       return C2;                                   // X / undef -> undef
     case Instruction::Or:                          // X | undef -> -1
-      if (const VectorType *PTy = dyn_cast(C1->getType()))
-        return Constant::getAllOnesValue(PTy);
-      return Constant::getAllOnesValue(C1->getType());
+      if (isa(C1) && isa(C2)) // undef | undef -> undef
+        return C1;
+      return Constant::getAllOnesValue(C1->getType()); // undef | X -> ~0
     case Instruction::LShr:
       if (isa(C2) && isa(C1))
         return C1;                                  // undef lshr undef -> undef
@@ -1041,6 +1059,8 @@
       else
         return C1;                                  // X ashr undef --> X
     case Instruction::Shl:
+      if (isa(C2) && isa(C1))
+        return C1;                                  // undef shl undef -> undef
       // undef << X -> 0   or   X << undef -> 0
       return Constant::getNullValue(C1->getType());
     }

Added: llvm/trunk/test/Transforms/InstSimplify/binop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/binop.ll?rev=134221&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/binop.ll (added)
+++ llvm/trunk/test/Transforms/InstSimplify/binop.ll Thu Jun 30 19:42:17 2011
@@ -0,0 +1,99 @@
+; RUN: opt -instsimplify -S < %s | FileCheck %s
+
+; @test0
+; CHECK: ret i64 undef
+define i64 @test0() {
+  %r = mul i64 undef, undef
+  ret i64 %r
+}
+
+; @test1
+; CHECK: ret i64 undef
+define i64 @test1() {
+  %r = mul i64 3, undef
+  ret i64 %r
+}
+
+; @test2
+; CHECK: ret i64 undef
+define i64 @test2() {
+  %r = mul i64 undef, 3
+  ret i64 %r
+}
+
+; @test3
+; CHECK: ret i64 0
+define i64 @test3() {
+  %r = mul i64 undef, 6
+  ret i64 %r
+}
+
+; @test4
+; CHECK: ret i64 0
+define i64 @test4() {
+  %r = mul i64 6, undef
+  ret i64 %r
+}
+
+; @test5
+; CHECK: ret i64 undef
+define i64 @test5() {
+  %r = and i64 undef, undef
+  ret i64 %r
+}
+
+; @test6
+; CHECK: ret i64 undef
+define i64 @test6() {
+  %r = or i64 undef, undef
+  ret i64 %r
+}
+
+; @test7
+; CHECK: ret i64 undef
+define i64 @test7() {
+  %r = udiv i64 undef, 1
+  ret i64 %r
+}
+
+; @test8
+; CHECK: ret i64 undef
+define i64 @test8() {
+  %r = sdiv i64 undef, 1
+  ret i64 %r
+}
+
+; @test9
+; CHECK: ret i64 0
+define i64 @test9() {
+  %r = urem i64 undef, 1
+  ret i64 %r
+}
+
+; @test10
+; CHECK: ret i64 0
+define i64 @test10() {
+  %r = srem i64 undef, 1
+  ret i64 %r
+}
+
+; @test11
+; CHECK: ret i64 undef
+define i64 @test11() {
+  %r = shl i64 undef, undef
+  ret i64 %r
+}
+
+; @test12
+; CHECK: ret i64 undef
+define i64 @test12() {
+  %r = ashr i64 undef, undef
+  ret i64 %r
+}
+
+; @test13
+; CHECK: ret i64 undef
+define i64 @test13() {
+  %r = lshr i64 undef, undef
+  ret i64 %r
+}



From fvbommel at gmail.com  Thu Jun 30 12:20:40 2011
From: fvbommel at gmail.com (Frits van Bommel)
Date: Thu, 30 Jun 2011 19:20:40 +0200
Subject: [llvm-commits] Segmented stacks, current status.
In-Reply-To: <4E0CA66B.8020904@playingwithpointers.com>
References: <4E089271.40607@playingwithpointers.com>
	<4E09FBDB.5050401@gmail.com>
	<4E0CA66B.8020904@playingwithpointers.com>
Message-ID: 

2011/6/30 Sanjoy Das :
>> but the function then looks for a callee saved register that is not live
>> in. Can we be sure that one is always available? Looking at gold (if you
>> plan to use it for linking segmented and non segmented code), it looks
>> like it assumes r10 or r11 is used.
>
> I've changed the code to use R10 as the scratch register.

R10 is used for 'nest' parameters, so IIUC it can be live-in. (See
lib/Target/X86/X86CallingConv.td)
R11 is probably a better choice.

From rafael.espindola at gmail.com  Thu Jun 30 15:12:24 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Thu, 30 Jun 2011 16:12:24 -0400
Subject: [llvm-commits] Segmented stacks, current status.
In-Reply-To: <4E0CA66B.8020904@playingwithpointers.com>
References: <4E089271.40607@playingwithpointers.com>
	<4E09FBDB.5050401@gmail.com>
	<4E0CA66B.8020904@playingwithpointers.com>
Message-ID: <4E0CD8A8.5060304@gmail.com>

> I'll now try to implement varargs, and see how it goes.

Awesome. Thanks!

> PS: The corrected code is on github.
>

Cheers,
Rafael

From eli.friedman at gmail.com  Thu Jun 30 19:59:25 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Thu, 30 Jun 2011 17:59:25 -0700
Subject: [llvm-commits] [llvm] r134219 - in /llvm/trunk:
 include/llvm/MC/SubtargetFeature.h lib/MC/SubtargetFeature.cpp
In-Reply-To: <20110701002310.6045D2A6C12C@llvm.org>
References: <20110701002310.6045D2A6C12C@llvm.org>
Message-ID: 

On Thu, Jun 30, 2011 at 5:23 PM, Evan Cheng  wrote:
> Author: evancheng
> Date: Thu Jun 30 19:23:10 2011
> New Revision: 134219
>
> URL: http://llvm.org/viewvc/llvm-project?rev=134219&view=rev
> Log:
> Switch SubtargetFeatures from std::string to StringRef.
>
> Modified:
> ? ?llvm/trunk/include/llvm/MC/SubtargetFeature.h
> ? ?llvm/trunk/lib/MC/SubtargetFeature.cpp
>
[...]
> @@ -53,16 +53,19 @@
>
> ?/// PrependFlag - Return a string with a prepended flag; '+' or '-'.
> ?///
> -static inline std::string PrependFlag(const std::string &Feature,
> - ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool IsEnabled) {
> +static inline StringRef PrependFlag(const StringRef Feature,
> + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?bool IsEnabled) {
> ? assert(!Feature.empty() && "Empty string");
> - ?if (hasFlag(Feature)) return Feature;
> - ?return std::string(IsEnabled ? "+" : "-") + Feature;
> + ?if (hasFlag(Feature))
> + ? ?return Feature;
> + ?std::string Prefix = IsEnabled ? "+" : "-";
> + ?Prefix += Feature;
> + ?return StringRef(Prefix);
> ?}

Use-after-free.

> -std::string SubtargetFeatures::getString() const {
> +StringRef SubtargetFeatures::getString() const {
> ? return Join(Features);
> ?}

Same.

-Eli


From echristo at apple.com  Thu Jun 30 20:00:07 2011
From: echristo at apple.com (Eric Christopher)
Date: Fri, 01 Jul 2011 01:00:07 -0000
Subject: [llvm-commits] [llvm] r134222 - in /llvm/trunk:
 lib/Target/ARM/ARMISelLowering.cpp test/CodeGen/ARM/inlineasm3.ll
Message-ID: <20110701010007.658942A6C12C@llvm.org>

Author: echristo
Date: Thu Jun 30 20:00:07 2011
New Revision: 134222

URL: http://llvm.org/viewvc/llvm-project?rev=134222&view=rev
Log:
Add support for the 'j' immediate constraint. This is conditionalized on
supporting the instruction that the constraint is for 'movw'.

Part of rdar://9119939

Modified:
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/test/CodeGen/ARM/inlineasm3.ll

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134222&r1=134221&r2=134222&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Thu Jun 30 20:00:07 2011
@@ -7485,6 +7485,7 @@
     case 'h': return C_RegisterClass;
     case 'x': return C_RegisterClass;
     case 't': return C_RegisterClass;
+    case 'j': return C_Other; // Constant for movw.
     }
   } else if (Constraint.size() == 2) {
     switch (Constraint[0]) {
@@ -7590,6 +7591,7 @@
   char ConstraintLetter = Constraint[0];
   switch (ConstraintLetter) {
   default: break;
+  case 'j':
   case 'I': case 'J': case 'K': case 'L':
   case 'M': case 'N': case 'O':
     ConstantSDNode *C = dyn_cast(Op);
@@ -7604,6 +7606,13 @@
       return;
 
     switch (ConstraintLetter) {
+      case 'j':
+	// Constant suitable for movw, must be between 0 and
+	// 65535.
+	if (Subtarget->hasV6T2Ops())
+	  if (CVal >= 0 && CVal <= 65535)
+	    break;
+	return;
       case 'I':
         if (Subtarget->isThumb1Only()) {
           // This must be a constant between 0 and 255, for ADD

Modified: llvm/trunk/test/CodeGen/ARM/inlineasm3.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/inlineasm3.ll?rev=134222&r1=134221&r2=134222&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/inlineasm3.ll (original)
+++ llvm/trunk/test/CodeGen/ARM/inlineasm3.ll Thu Jun 30 20:00:07 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
+; RUN: llc < %s -march=arm -mattr=+neon,+v6t2 | FileCheck %s
 
 ; Radar 7449043
 %struct.int32x4_t = type { <4 x i32> }
@@ -71,7 +71,7 @@
 
 ; Radar 9307836 & 9119939
 
-define double @t7(double %y) nounwind ssp {
+define double @t7(double %y) nounwind {
 entry:
 ; CHECK: t7
 ; CHECK: flds s15, d0
@@ -81,10 +81,20 @@
 
 ; Radar 9307836 & 9119939
 
-define float @t8(float %y) nounwind ssp {
+define float @t8(float %y) nounwind {
 entry:
 ; CHECK: t8
 ; CHECK: flds s15, s0
   %0 = tail call float asm "flds s15, $0", "=t"() nounwind
   ret float %0
 }
+
+; Radar 9307836 & 9119939
+
+define i32 @t9(i32 %r0) nounwind {
+entry:
+; CHECK: t9
+; CHECK: movw r0, #27182
+  %0 = tail call i32 asm "movw $0, $1", "=r,j"(i32 27182) nounwind
+  ret i32 %0
+}



From grosbach at apple.com  Thu Jun 30 20:02:00 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Thu, 30 Jun 2011 18:02:00 -0700
Subject: [llvm-commits] [llvm] r134204 - in /llvm/trunk/lib/Target/ARM:
 ARMAsmPrinter.cpp ARMFrameLowering.cpp ARMInstrThumb.td
 Thumb1FrameLowering.cpp Thumb1InstrInfo.cpp Thumb1RegisterInfo.cpp
 Thumb2ITBlockPass.cpp Thumb2InstrInfo.cpp Thumb2SizeReductio
In-Reply-To: 
References: 
Message-ID: 


On Jun 30, 2011, at 5:16 PM, Eli Friedman wrote:

> On Thu, Jun 30, 2011 at 4:38 PM, Jim Grosbach  wrote:
>> Author: grosbach
>> Date: Thu Jun 30 18:38:17 2011
>> New Revision: 134204
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=134204&view=rev
>> Log:
>> Refact ARM Thumb1 tMOVr instruction family.
>> 
>> Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
>> into tMOVr. There's no need to keep them separate. Giving the tMOVr
>> instruction the proper GPR register class for its operands is sufficient
>> to give the register allocator enough information to do the right thing
>> directly.
> 
> Does this account for the fact that "mov r1, r2" is illegal on pre-v6
> Thumb1 implementations?
> 

Good question. No. It does neither more nor less in that regard than the previous code. For that restriction (copying between two low regs), the compiler would need to use MOVS for copies between low registers, which it isn't (and wasn't). Fixing that is interesting, but outside the scope of what I'm trying to do in this patch.

-Jim

> -Eli
> 
>> Modified:
>>    llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>>    llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
>>    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>>    llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
>>    llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
>>    llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
>>    llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
>>    llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
>>    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp?rev=134204&r1=134203&r2=134204&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMAsmPrinter.cpp Thu Jun 30 18:38:17 2011
>> @@ -1010,8 +1010,6 @@
>>         MI->dump();
>>         assert(0 && "Unsupported opcode for unwinding information");
>>       case ARM::MOVr:
>> -      case ARM::tMOVgpr2gpr:
>> -      case ARM::tMOVgpr2tgpr:
>>         Offset = 0;
>>         break;
>>       case ARM::ADDri:
>> @@ -1456,7 +1454,7 @@
>>   case ARM::t2BR_JT: {
>>     // Lower and emit the instruction itself, then the jump table following it.
>>     MCInst TmpInst;
>> -    TmpInst.setOpcode(ARM::tMOVgpr2gpr);
>> +    TmpInst.setOpcode(ARM::tMOVr);
>>     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
>>     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
>>     // Add predicate operands.
>> @@ -1505,7 +1503,7 @@
>>     // mov pc, target
>>     MCInst TmpInst;
>>     unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
>> -      ARM::MOVr : ARM::tMOVgpr2gpr;
>> +      ARM::MOVr : ARM::tMOVr;
>>     TmpInst.setOpcode(Opc);
>>     TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
>>     TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
>> @@ -1518,7 +1516,7 @@
>>     OutStreamer.EmitInstruction(TmpInst);
>> 
>>     // Make sure the Thumb jump table is 4-byte aligned.
>> -    if (Opc == ARM::tMOVgpr2gpr)
>> +    if (Opc == ARM::tMOVr)
>>       EmitAlignment(2);
>> 
>>     // Output the data for the jump table itself
>> @@ -1610,7 +1608,7 @@
>>     MCSymbol *Label = GetARMSJLJEHLabel();
>>     {
>>       MCInst TmpInst;
>> -      TmpInst.setOpcode(ARM::tMOVgpr2tgpr);
>> +      TmpInst.setOpcode(ARM::tMOVr);
>>       TmpInst.addOperand(MCOperand::CreateReg(ValReg));
>>       TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
>>       // Predicate.
>> @@ -1829,7 +1827,7 @@
>>     }
>>     {
>>       MCInst TmpInst;
>> -      TmpInst.setOpcode(ARM::tMOVtgpr2gpr);
>> +      TmpInst.setOpcode(ARM::tMOVr);
>>       TmpInst.addOperand(MCOperand::CreateReg(ARM::SP));
>>       TmpInst.addOperand(MCOperand::CreateReg(ScratchReg));
>>       // Predicate.
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp?rev=134204&r1=134203&r2=134204&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp Thu Jun 30 18:38:17 2011
>> @@ -268,13 +268,13 @@
>>       // bic r4, r4, MaxAlign
>>       // mov sp, r4
>>       // FIXME: It will be better just to find spare register here.
>> -      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2tgpr), ARM::R4)
>> +      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
>>         .addReg(ARM::SP, RegState::Kill));
>>       AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, dl,
>>                                           TII.get(ARM::t2BICri), ARM::R4)
>>                                   .addReg(ARM::R4, RegState::Kill)
>>                                   .addImm(MaxAlign-1)));
>> -      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr), ARM::SP)
>> +      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
>>         .addReg(ARM::R4, RegState::Kill));
>>     }
>> 
>> @@ -293,7 +293,7 @@
>>         .addReg(ARM::SP)
>>         .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
>>     else
>> -      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
>> +      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
>>                              RegInfo->getBaseRegister())
>>         .addReg(ARM::SP));
>>   }
>> @@ -364,7 +364,7 @@
>>                  "No scratch register to restore SP from FP!");
>>           emitT2RegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
>>                                  ARMCC::AL, 0, TII);
>> -          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
>> +          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
>>                                  ARM::SP)
>>             .addReg(ARM::R4));
>>         }
>> @@ -374,7 +374,7 @@
>>           BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
>>             .addReg(FramePtr).addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
>>         else
>> -          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),
>> +          AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
>>                                  ARM::SP)
>>             .addReg(FramePtr));
>>       }
>> 
>> Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134204&r1=134203&r2=134204&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
>> +++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Thu Jun 30 18:38:17 2011
>> @@ -1054,15 +1054,15 @@
>>  // TODO: A7-73: MOV(2) - mov setting flag.
>> 
>>  let neverHasSideEffects = 1 in {
>> -def tMOVr : Thumb1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
>> +def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
>>                       Size2Bytes, IIC_iMOVr,
>>                       "mov", "\t$Rd, $Rm", "", []>,
>> -                  T1Special<0b1000> {
>> +                  T1Special<{1,0,?,?}> {
>>   // A8.6.97
>>   bits<4> Rd;
>>   bits<4> Rm;
>> -  // Bits {7-6} are encoded by the T1Special value.
>> -  let Inst{5-3} = Rm{2-0};
>> +  let Inst{7}   = Rd{3};
>> +  let Inst{6-3} = Rm;
>>   let Inst{2-0} = Rd{2-0};
>>  }
>>  let Defs = [CPSR] in
>> @@ -1075,40 +1075,6 @@
>>   let Inst{5-3}  = Rm;
>>   let Inst{2-0}  = Rd;
>>  }
>> -
>> -// FIXME: Do we really need separate instructions for GPR<-->tGPR like this?
>> -//        They all map to the same instruction (MOV encoding T1).
>> -def tMOVgpr2tgpr : Thumb1pI<(outs tGPR:$Rd), (ins GPR:$Rm), AddrModeNone,
>> -                            Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
>> -                   T1Special<{1,0,0,?}> {
>> -  // A8.6.97
>> -  bits<4> Rd;
>> -  bits<4> Rm;
>> -  // Bit {7} is encoded by the T1Special value.
>> -  let Inst{6-3} = Rm;
>> -  let Inst{2-0} = Rd{2-0};
>> -}
>> -def tMOVtgpr2gpr : Thumb1pI<(outs GPR:$Rd), (ins tGPR:$Rm), AddrModeNone,
>> -                            Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
>> -                   T1Special<{1,0,?,0}> {
>> -  // A8.6.97
>> -  bits<4> Rd;
>> -  bits<4> Rm;
>> -  // Bit {6} is encoded by the T1Special value.
>> -  let Inst{7}   = Rd{3};
>> -  let Inst{5-3} = Rm{2-0};
>> -  let Inst{2-0} = Rd{2-0};
>> -}
>> -def tMOVgpr2gpr  : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
>> -                            Size2Bytes, IIC_iMOVr, "mov", "\t$Rd, $Rm", "", []>,
>> -                   T1Special<{1,0,?,?}> {
>> -  // A8.6.97
>> -  bits<4> Rd;
>> -  bits<4> Rm;
>> -  let Inst{7}   = Rd{3};
>> -  let Inst{6-3} = Rm;
>> -  let Inst{2-0} = Rd{2-0};
>> -}
>>  } // neverHasSideEffects
>> 
>>  // Multiply register
>> 
>> Modified: llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp?rev=134204&r1=134203&r2=134204&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp Thu Jun 30 18:38:17 2011
>> @@ -160,7 +160,7 @@
>>   // will be allocated after this, so we can still use the base pointer
>>   // to reference locals.
>>   if (RegInfo->hasBasePointer(MF))
>> -    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr), BasePtr)
>> +    AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
>>                    .addReg(ARM::SP));
>> 
>>   // If the frame has variable sized objects then the epilogue must restore
>> @@ -240,11 +240,11 @@
>>                "No scratch register to restore SP from FP!");
>>         emitThumbRegPlusImmediate(MBB, MBBI, dl, ARM::R4, FramePtr, -NumBytes,
>>                                   TII, *RegInfo);
>> -        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
>> +        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
>>                                ARM::SP)
>>           .addReg(ARM::R4));
>>       } else
>> -        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVtgpr2gpr),
>> +        AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),
>>                                ARM::SP)
>>           .addReg(FramePtr));
>>     } else {
>> 
>> Modified: llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb1InstrInfo.cpp Thu Jun 30 18:38:17 2011
>> @@ -36,17 +36,7 @@
>>                                   MachineBasicBlock::iterator I, DebugLoc DL,
>>                                   unsigned DestReg, unsigned SrcReg,
>>                                   bool KillSrc) const {
>> -  bool tDest = ARM::tGPRRegClass.contains(DestReg);
>> -  bool tSrc  = ARM::tGPRRegClass.contains(SrcReg);
>> -  unsigned Opc = ARM::tMOVgpr2gpr;
>> -  if (tDest && tSrc)
>> -    Opc = ARM::tMOVr;
>> -  else if (tSrc)
>> -    Opc = ARM::tMOVtgpr2gpr;
>> -  else if (tDest)
>> -    Opc = ARM::tMOVgpr2tgpr;
>> -
>> -  AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
>> +  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
>>     .addReg(SrcReg, getKillRegState(KillSrc)));
>>   assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
>>          "Thumb1 can only copy GPR registers");
>> 
>> Modified: llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb1RegisterInfo.cpp Thu Jun 30 18:38:17 2011
>> @@ -417,7 +417,7 @@
>>     unsigned PredReg;
>>     if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
>>       // Turn it into a move.
>> -      MI.setDesc(TII.get(ARM::tMOVgpr2tgpr));
>> +      MI.setDesc(TII.get(ARM::tMOVr));
>>       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
>>       // Remove offset and add predicate operands.
>>       MI.RemoveOperand(FrameRegIdx+1);
>> @@ -564,7 +564,7 @@
>>   // the function, the offset will be negative. Use R12 instead since that's
>>   // a call clobbered register that we know won't be used in Thumb1 mode.
>>   DebugLoc DL;
>> -  AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVtgpr2gpr))
>> +  AddDefaultPred(BuildMI(MBB, I, DL, TII.get(ARM::tMOVr))
>>     .addReg(ARM::R12, RegState::Define)
>>     .addReg(Reg, RegState::Kill));
>> 
>> @@ -589,7 +589,7 @@
>>     }
>>   }
>>   // Restore the register from R12
>> -  AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVgpr2tgpr)).
>> +  AddDefaultPred(BuildMI(MBB, UseMI, DL, TII.get(ARM::tMOVr)).
>>     addReg(Reg, RegState::Define).addReg(ARM::R12, RegState::Kill));
>> 
>>   return true;
>> 
>> Modified: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp?rev=134204&r1=134203&r2=134204&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp Thu Jun 30 18:38:17 2011
>> @@ -98,9 +98,6 @@
>>   case ARM::MOVr:
>>   case ARM::MOVr_TC:
>>   case ARM::tMOVr:
>> -  case ARM::tMOVgpr2tgpr:
>> -  case ARM::tMOVtgpr2gpr:
>> -  case ARM::tMOVgpr2gpr:
>>   case ARM::t2MOVr:
>>     return true;
>>   }
>> 
>> Modified: llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp?rev=134204&r1=134203&r2=134204&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb2InstrInfo.cpp Thu Jun 30 18:38:17 2011
>> @@ -112,17 +112,7 @@
>>   if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
>>     return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
>> 
>> -  bool tDest = ARM::tGPRRegClass.contains(DestReg);
>> -  bool tSrc  = ARM::tGPRRegClass.contains(SrcReg);
>> -  unsigned Opc = ARM::tMOVgpr2gpr;
>> -  if (tDest && tSrc)
>> -    Opc = ARM::tMOVr;
>> -  else if (tSrc)
>> -    Opc = ARM::tMOVtgpr2gpr;
>> -  else if (tDest)
>> -    Opc = ARM::tMOVgpr2tgpr;
>> -
>> -  AddDefaultPred(BuildMI(MBB, I, DL, get(Opc), DestReg)
>> +  AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
>>     .addReg(SrcReg, getKillRegState(KillSrc)));
>>  }
>> 
>> @@ -231,7 +221,7 @@
>>     unsigned Opc = 0;
>>     if (DestReg == ARM::SP && BaseReg != ARM::SP) {
>>       // mov sp, rn. Note t2MOVr cannot be used.
>> -      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg)
>> +      AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr),DestReg)
>>         .addReg(BaseReg).setMIFlags(MIFlags));
>>       BaseReg = ARM::SP;
>>       continue;
>> @@ -409,7 +399,7 @@
>>     unsigned PredReg;
>>     if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
>>       // Turn it into a move.
>> -      MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
>> +      MI.setDesc(TII.get(ARM::tMOVr));
>>       MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
>>       // Remove offset and remaining explicit predicate operands.
>>       do MI.RemoveOperand(FrameRegIdx+1);
>> @@ -575,8 +565,7 @@
>>  Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
>>                                        MachineInstr *UseMI,
>>                                        const TargetRegisterInfo &TRI) const {
>> -  if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
>> -      SrcMI->getOperand(1).isKill())
>> +  if (SrcMI->getOpcode() != ARM::tMOVr || SrcMI->getOperand(1).isKill())
>>     return;
>> 
>>   unsigned PredReg = 0;
>> 
>> Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
>> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134204&r1=134203&r2=134204&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
>> +++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Thu Jun 30 18:38:17 2011
>> @@ -82,7 +82,7 @@
>>     { ARM::t2MOVi,  ARM::tMOVi8,  0,             8,   0,    1,   0,  0,0, 0,0 },
>>     { ARM::t2MOVi16,ARM::tMOVi8,  0,             8,   0,    1,   0,  0,0, 0,1 },
>>     // FIXME: Do we need the 16-bit 'S' variant?
>> -    { ARM::t2MOVr,ARM::tMOVgpr2gpr,0,            0,   0,    0,   0,  1,0, 0,0 },
>> +    { ARM::t2MOVr,ARM::tMOVr,     0,             0,   0,    0,   0,  1,0, 0,0 },
>>     { ARM::t2MOVCCr,0,            ARM::tMOVCCr,  0,   0,    0,   0,  0,1, 0,0 },
>>     { ARM::t2MOVCCi,0,            ARM::tMOVCCi,  0,   8,    0,   1,  0,1, 0,0 },
>>     { ARM::t2MUL,   0,            ARM::tMUL,     0,   0,    0,   1,  0,0, 1,0 },
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 


From gohman at apple.com  Thu Jun 30 20:03:43 2011
From: gohman at apple.com (Dan Gohman)
Date: Fri, 01 Jul 2011 01:03:43 -0000
Subject: [llvm-commits] [llvm] r134223 - in /llvm/trunk:
 lib/Analysis/InstructionSimplify.cpp lib/VMCore/ConstantFold.cpp
 test/Transforms/InstSimplify/binop.ll test/Transforms/InstSimplify/undef.ll
Message-ID: <20110701010343.5E2032A6C12C@llvm.org>

Author: djg
Date: Thu Jun 30 20:03:43 2011
New Revision: 134223

URL: http://llvm.org/viewvc/llvm-project?rev=134223&view=rev
Log:
Improve constant folding of undef for cmp and select operators.

Added:
    llvm/trunk/test/Transforms/InstSimplify/undef.ll
      - copied, changed from r134221, llvm/trunk/test/Transforms/InstSimplify/binop.ll
Removed:
    llvm/trunk/test/Transforms/InstSimplify/binop.ll
Modified:
    llvm/trunk/lib/Analysis/InstructionSimplify.cpp
    llvm/trunk/lib/VMCore/ConstantFold.cpp

Modified: llvm/trunk/lib/Analysis/InstructionSimplify.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/InstructionSimplify.cpp?rev=134223&r1=134222&r2=134223&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/InstructionSimplify.cpp (original)
+++ llvm/trunk/lib/Analysis/InstructionSimplify.cpp Thu Jun 30 20:03:43 2011
@@ -2204,15 +2204,15 @@
   if (TrueVal == FalseVal)
     return TrueVal;
 
-  if (isa(TrueVal))   // select C, undef, X -> X
-    return FalseVal;
-  if (isa(FalseVal))   // select C, X, undef -> X
-    return TrueVal;
   if (isa(CondVal)) {  // select undef, X, Y -> X or Y
     if (isa(TrueVal))
       return TrueVal;
     return FalseVal;
   }
+  if (isa(TrueVal))   // select C, undef, X -> X
+    return FalseVal;
+  if (isa(FalseVal))   // select C, X, undef -> X
+    return TrueVal;
 
   return 0;
 }

Modified: llvm/trunk/lib/VMCore/ConstantFold.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/VMCore/ConstantFold.cpp?rev=134223&r1=134222&r2=134223&view=diff
==============================================================================
--- llvm/trunk/lib/VMCore/ConstantFold.cpp (original)
+++ llvm/trunk/lib/VMCore/ConstantFold.cpp Thu Jun 30 20:03:43 2011
@@ -730,9 +730,12 @@
   }
 
 
+  if (isa(Cond)) {
+    if (isa(V1)) return V1;
+    return V2;
+  }
   if (isa(V1)) return V2;
   if (isa(V2)) return V1;
-  if (isa(Cond)) return V1;
   if (V1 == V2) return V1;
 
   if (ConstantExpr *TrueVal = dyn_cast(V1)) {
@@ -1851,7 +1854,9 @@
   if (isa(C1) || isa(C2)) {
     // For EQ and NE, we can always pick a value for the undef to make the
     // predicate pass or fail, so we can return undef.
-    if (ICmpInst::isEquality(ICmpInst::Predicate(pred)))
+    // Also, if both operands are undef, we can return undef.
+    if (ICmpInst::isEquality(ICmpInst::Predicate(pred)) ||
+        (isa(C1) && isa(C2)))
       return UndefValue::get(ResultTy);
     // Otherwise, pick the same value as the non-undef operand, and fold
     // it to true or false.

Removed: llvm/trunk/test/Transforms/InstSimplify/binop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/binop.ll?rev=134222&view=auto
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/binop.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/binop.ll (removed)
@@ -1,99 +0,0 @@
-; RUN: opt -instsimplify -S < %s | FileCheck %s
-
-; @test0
-; CHECK: ret i64 undef
-define i64 @test0() {
-  %r = mul i64 undef, undef
-  ret i64 %r
-}
-
-; @test1
-; CHECK: ret i64 undef
-define i64 @test1() {
-  %r = mul i64 3, undef
-  ret i64 %r
-}
-
-; @test2
-; CHECK: ret i64 undef
-define i64 @test2() {
-  %r = mul i64 undef, 3
-  ret i64 %r
-}
-
-; @test3
-; CHECK: ret i64 0
-define i64 @test3() {
-  %r = mul i64 undef, 6
-  ret i64 %r
-}
-
-; @test4
-; CHECK: ret i64 0
-define i64 @test4() {
-  %r = mul i64 6, undef
-  ret i64 %r
-}
-
-; @test5
-; CHECK: ret i64 undef
-define i64 @test5() {
-  %r = and i64 undef, undef
-  ret i64 %r
-}
-
-; @test6
-; CHECK: ret i64 undef
-define i64 @test6() {
-  %r = or i64 undef, undef
-  ret i64 %r
-}
-
-; @test7
-; CHECK: ret i64 undef
-define i64 @test7() {
-  %r = udiv i64 undef, 1
-  ret i64 %r
-}
-
-; @test8
-; CHECK: ret i64 undef
-define i64 @test8() {
-  %r = sdiv i64 undef, 1
-  ret i64 %r
-}
-
-; @test9
-; CHECK: ret i64 0
-define i64 @test9() {
-  %r = urem i64 undef, 1
-  ret i64 %r
-}
-
-; @test10
-; CHECK: ret i64 0
-define i64 @test10() {
-  %r = srem i64 undef, 1
-  ret i64 %r
-}
-
-; @test11
-; CHECK: ret i64 undef
-define i64 @test11() {
-  %r = shl i64 undef, undef
-  ret i64 %r
-}
-
-; @test12
-; CHECK: ret i64 undef
-define i64 @test12() {
-  %r = ashr i64 undef, undef
-  ret i64 %r
-}
-
-; @test13
-; CHECK: ret i64 undef
-define i64 @test13() {
-  %r = lshr i64 undef, undef
-  ret i64 %r
-}

Copied: llvm/trunk/test/Transforms/InstSimplify/undef.ll (from r134221, llvm/trunk/test/Transforms/InstSimplify/binop.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/InstSimplify/undef.ll?p2=llvm/trunk/test/Transforms/InstSimplify/undef.ll&p1=llvm/trunk/test/Transforms/InstSimplify/binop.ll&r1=134221&r2=134223&rev=134223&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/InstSimplify/binop.ll (original)
+++ llvm/trunk/test/Transforms/InstSimplify/undef.ll Thu Jun 30 20:03:43 2011
@@ -97,3 +97,31 @@
   %r = lshr i64 undef, undef
   ret i64 %r
 }
+
+; @test14
+; CHECK: ret i1 undef
+define i1 @test14() {
+  %r = icmp slt i64 undef, undef
+  ret i1 %r
+}
+
+; @test15
+; CHECK: ret i1 undef
+define i1 @test15() {
+  %r = icmp ult i64 undef, undef
+  ret i1 %r
+}
+
+; @test16
+; CHECK: ret i64 undef
+define i64 @test16(i64 %a) {
+  %r = select i1 undef, i64 %a, i64 undef
+  ret i64 %r
+}
+
+; @test17
+; CHECK: ret i64 undef
+define i64 @test17(i64 %a) {
+  %r = select i1 undef, i64 undef, i64 %a
+  ret i64 %r
+}



From ahatanak at gmail.com  Thu Jun 30 20:04:43 2011
From: ahatanak at gmail.com (Akira Hatanaka)
Date: Fri, 01 Jul 2011 01:04:43 -0000
Subject: [llvm-commits] [llvm] r134224 - in /llvm/trunk/lib/Target/Mips:
 MipsAsmPrinter.cpp MipsInstrInfo.cpp MipsInstrInfo.h MipsMCAsmInfo.cpp
 MipsRegisterInfo.cpp
Message-ID: <20110701010443.DC62E2A6C12C@llvm.org>

Author: ahatanak
Date: Thu Jun 30 20:04:43 2011
New Revision: 134224

URL: http://llvm.org/viewvc/llvm-project?rev=134224&view=rev
Log:
Improve Mips back-end's handling of DBG_VALUE. 



Modified:
    llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
    llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp
    llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp

Modified: llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp?rev=134224&r1=134223&r2=134224&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsAsmPrinter.cpp Thu Jun 30 20:04:43 2011
@@ -38,6 +38,8 @@
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Analysis/DebugInfo.h"
+
 using namespace llvm;
 
 namespace {
@@ -75,6 +77,10 @@
     void EmitInstruction(const MachineInstr *MI) {
       SmallString<128> Str;
       raw_svector_ostream OS(Str);
+
+      if (MI->isDebugValue())
+        PrintDebugValueComment(MI, OS);
+
       printInstruction(MI, OS);
       OutStreamer.EmitRawText(OS.str());
     }
@@ -86,6 +92,9 @@
 
     virtual void EmitFunctionEntryLabel();
     void EmitStartOfAsmFile(Module &M);
+    virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
+
+    void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
   };
 } // end of anonymous namespace
 
@@ -441,6 +450,21 @@
   OutStreamer.EmitRawText(StringRef("\t.previous"));
 }
 
+MachineLocation
+MipsAsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
+  // Handles frame addresses emitted in MipsInstrInfo::emitFrameIndexDebugValue.
+  assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
+  assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
+         "Unexpected MachineOperand types");
+  return MachineLocation(MI->getOperand(0).getReg(),
+                         MI->getOperand(1).getImm());
+}
+
+void MipsAsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
+                                           raw_ostream &OS) {
+  // TODO: implement
+}
+
 // Force static initialization.
 extern "C" void LLVMInitializeMipsAsmPrinter() {
   RegisterAsmPrinter X(TheMipsTarget);

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=134224&r1=134223&r2=134224&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Thu Jun 30 20:04:43 2011
@@ -217,6 +217,15 @@
     llvm_unreachable("Register class not handled!");
 }
 
+MachineInstr*
+MipsInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
+                                        uint64_t Offset, const MDNode *MDPtr,
+                                        DebugLoc DL) const {
+  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE))
+    .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
+  return &*MIB;
+}
+
 //===----------------------------------------------------------------------===//
 // Branch Analysis
 //===----------------------------------------------------------------------===//

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=134224&r1=134223&r2=134224&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Thu Jun 30 20:04:43 2011
@@ -224,6 +224,11 @@
                                     const TargetRegisterClass *RC,
                                     const TargetRegisterInfo *TRI) const;
 
+  virtual MachineInstr* emitFrameIndexDebugValue(MachineFunction &MF,
+                                                 int FrameIx, uint64_t Offset,
+                                                 const MDNode *MDPtr,
+                                                 DebugLoc DL) const;
+
   virtual
   bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
 

Modified: llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp?rev=134224&r1=134223&r2=134224&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCAsmInfo.cpp Thu Jun 30 20:04:43 2011
@@ -16,7 +16,7 @@
 
 MipsMCAsmInfo::MipsMCAsmInfo(const Target &T, StringRef TT) {
   AlignmentIsInBytes          = false;
-  Data16bitsDirective         = "\t.half\t";
+  Data16bitsDirective         = "\t.2byte\t";
   Data32bitsDirective         = "\t.4byte\t";
   Data64bitsDirective         = 0;
   PrivateGlobalPrefix         = "$";

Modified: llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp?rev=134224&r1=134223&r2=134224&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsRegisterInfo.cpp Thu Jun 30 20:04:43 2011
@@ -35,6 +35,7 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/Analysis/DebugInfo.h"
 
 #define GET_REGINFO_MC_DESC
 #define GET_REGINFO_TARGET_DESC
@@ -179,8 +180,29 @@
                << "spOffset   : " << spOffset << "\n"
                << "stackSize  : " << stackSize << "\n");
 
-  int Offset;
+  const std::vector &CSI = MFI->getCalleeSavedInfo();
+  int MinCSFI = 0;
+  int MaxCSFI = -1;
+
+  if (CSI.size()) {
+    MinCSFI = CSI[0].getFrameIdx();
+    MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
+  }
+
+  // The following stack frame objects are always referenced relative to $sp:
+  //  1. Outgoing arguments.
+  //  2. Pointer to dynamically allocated stack space.
+  //  3. Locations for callee-saved registers.
+  // Everything else is referenced relative to whatever register 
+  // getFrameRegister() returns.
+  unsigned FrameReg;
 
+  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
+      (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
+    FrameReg = Mips::SP;
+  else
+    FrameReg = getFrameRegister(MF); 
+  
   // Calculate final offset.
   // - There is no need to change the offset if the frame object is one of the
   //   following: an outgoing argument, pointer to a dynamically allocated
@@ -188,12 +210,20 @@
   // - If the frame object is any of the following, its offset must be adjusted
   //   by adding the size of the stack:
   //   incoming argument, callee-saved register location or local variable.  
+  int Offset;
+
   if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isGPFI(FrameIndex) ||
       MipsFI->isDynAllocFI(FrameIndex))
     Offset = spOffset;
   else
     Offset = spOffset + stackSize;
 
+  if (MI.isDebugValue()) {
+    MI.getOperand(i).ChangeToRegister(FrameReg, false /*isDef*/);
+    MI.getOperand(i+1).ChangeToImmediate(Offset);
+    return;
+  }
+
   Offset    += MI.getOperand(i-1).getImm();
 
   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
@@ -202,28 +232,7 @@
   int NewImm = 0;
   MachineBasicBlock &MBB = *MI.getParent();
   bool ATUsed;
-  unsigned FrameReg;
-  const std::vector &CSI = MFI->getCalleeSavedInfo();
-  int MinCSFI = 0;
-  int MaxCSFI = -1;
-
-  if (CSI.size()) {
-    MinCSFI = CSI[0].getFrameIdx();
-    MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
-  }
 
-  // The following stack frame objects are always referenced relative to $sp:
-  //  1. Outgoing arguments.
-  //  2. Pointer to dynamically allocated stack space.
-  //  3. Locations for callee-saved registers.
-  // Everything else is referenced relative to whatever register 
-  // getFrameRegister() returns.
-  if (MipsFI->isOutArgFI(FrameIndex) || MipsFI->isDynAllocFI(FrameIndex) ||
-      (FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI))
-    FrameReg = Mips::SP;
-  else
-    FrameReg = getFrameRegister(MF); 
-  
   // Offset fits in the 16-bit field
   if (Offset < 0x8000 && Offset >= -0x8000) {
     NewReg = FrameReg;



From stoklund at 2pi.dk  Thu Jun 30 20:24:25 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 01 Jul 2011 01:24:25 -0000
Subject: [llvm-commits] [llvm] r134226 -
	/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp
Message-ID: <20110701012425.A67D52A6C12C@llvm.org>

Author: stoklund
Date: Thu Jun 30 20:24:25 2011
New Revision: 134226

URL: http://llvm.org/viewvc/llvm-project?rev=134226&view=rev
Log:
Don't inflate register classes used by inline asm.

The constraints are represented by the register class of the original
virtual register created for the inline asm. If the register class were
included in the operand descriptor, we might be able to do this.

For now, just give up on regclass inflation when inline asm is involved.

No test case, this bug hasn't happened yet.

Modified:
    llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp

Modified: llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp?rev=134226&r1=134225&r2=134226&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp (original)
+++ llvm/trunk/lib/CodeGen/CalcSpillWeights.cpp Thu Jun 30 20:24:25 2011
@@ -203,6 +203,9 @@
     // TRI doesn't have accurate enough information to model this yet.
     if (I.getOperand().getSubReg())
       return;
+    // Inline asm instuctions don't remember their constraints.
+    if (I->isInlineAsm())
+      return;
     const TargetRegisterClass *OpRC =
       TII->getRegClass(I->getDesc(), I.getOperandNo(), TRI);
     if (OpRC)



From rafael.espindola at gmail.com  Thu Jun 30 20:25:49 2011
From: rafael.espindola at gmail.com (=?ISO-8859-1?Q?Rafael_=C1vila_de_Esp=EDndola?=)
Date: Thu, 30 Jun 2011 21:25:49 -0400
Subject: [llvm-commits] [llvm] r134216 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
In-Reply-To: 
References: <20110701001655.36D6D2A6C12C@llvm.org>
	
Message-ID: <4E0D221D.5070302@gmail.com>

On 06/30/2011 08:36 PM, Jakob Stoklund Olesen wrote:
>
> On Jun 30, 2011, at 5:16 PM, Rafael Espindola wrote:
>
>> + // FIXME: If "B = X" kills X, we have to move the kill back to its
>> + // previous use. For now we just avoid the optimization in that case.
>> + if (MI->getOperand(1).isKill())
>> + return false;
>
> It's not so much the kill flags, they are actually recomputed after
> register allocation.
>
> It is important that the live ranges are updated, though. You need to
> shrink X to its uses when you remove a use.
>
> There doesn't have to be a kill flag: If you are removing the last use
> in a loop where X is not live out, it doesn't have to be live in the
> loop any more.

So the check should be "at the end of the life range"? Is

LifeRangeX.contains(CopySlot.getNextSlot())

the best way to check that?

> /jakob
>

Cheers,
Rafael

From stoklund at 2pi.dk  Thu Jun 30 20:30:37 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 30 Jun 2011 18:30:37 -0700
Subject: [llvm-commits] [llvm] r134216 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
In-Reply-To: <4E0D221D.5070302@gmail.com>
References: <20110701001655.36D6D2A6C12C@llvm.org>
	
	<4E0D221D.5070302@gmail.com>
Message-ID: <146D139F-7658-4EB2-BDCE-94DB39DBEEF4@2pi.dk>


On Jun 30, 2011, at 6:25 PM, Rafael ?vila de Esp?ndola wrote:

> On 06/30/2011 08:36 PM, Jakob Stoklund Olesen wrote:
>> 
>> On Jun 30, 2011, at 5:16 PM, Rafael Espindola wrote:
>> 
>>> + // FIXME: If "B = X" kills X, we have to move the kill back to its
>>> + // previous use. For now we just avoid the optimization in that case.
>>> + if (MI->getOperand(1).isKill())
>>> + return false;
>> 
>> It's not so much the kill flags, they are actually recomputed after
>> register allocation.
>> 
>> It is important that the live ranges are updated, though. You need to
>> shrink X to its uses when you remove a use.
>> 
>> There doesn't have to be a kill flag: If you are removing the last use
>> in a loop where X is not live out, it doesn't have to be live in the
>> loop any more.
> 
> So the check should be "at the end of the life range"? Is
> 
> LifeRangeX.contains(CopySlot.getNextSlot())
> 
> the best way to check that?

LR.killedAt(CopySlot).

/jakob



From rafael.espindola at gmail.com  Thu Jun 30 21:35:06 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 01 Jul 2011 02:35:06 -0000
Subject: [llvm-commits] [llvm] r134228 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
Message-ID: <20110701023506.BD5852A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 30 21:35:06 2011
New Revision: 134228

URL: http://llvm.org/viewvc/llvm-project?rev=134228&view=rev
Log:
Check the liveinterval, not the kill flag.

Modified:
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=134228&r1=134227&r2=134228&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Thu Jun 30 21:35:06 2011
@@ -1197,7 +1197,8 @@
 // which allows us to coalesce A and B.
 // MI is the definition of B. LR is the life range of A that includes
 // the slot just before B. If we return true, we add "B = X" to DupCopies.
-static bool RegistersDefinedFromSameValue(const TargetRegisterInfo &tri,
+static bool RegistersDefinedFromSameValue(LiveIntervals &li,
+                                          const TargetRegisterInfo &tri,
                                           CoalescerPair &CP, MachineInstr *MI,
                                           LiveRange *LR,
                                      SmallVector &DupCopies) {
@@ -1207,14 +1208,16 @@
   if (!MI->isFullCopy() || CP.isPartial() || CP.isPhys())
     return false;
 
+  unsigned Dst = MI->getOperand(0).getReg();
+  unsigned Src = MI->getOperand(1).getReg();
+
   // FIXME: If "B = X" kills X, we have to move the kill back to its
   // previous use. For now we just avoid the optimization in that case.
-  if (MI->getOperand(1).isKill())
+  SlotIndex CopyIdx = li.getInstructionIndex(MI).getNextIndex().getDefIndex();
+  LiveInterval &SrcInt = li.getInterval(Src);
+  if (SrcInt.killedAt(CopyIdx))
     return false;
 
-  unsigned Dst = MI->getOperand(0).getReg();
-  unsigned Src = MI->getOperand(1).getReg();
-
   if (!TargetRegisterInfo::isVirtualRegister(Src) ||
       !TargetRegisterInfo::isVirtualRegister(Dst))
     return false;
@@ -1332,7 +1335,7 @@
     // from the RHS interval, we can use its value #.
     MachineInstr *MI = VNI->getCopy();
     if (!CP.isCoalescable(MI) &&
-        !RegistersDefinedFromSameValue(*tri_, CP, MI, lr, DupCopies))
+        !RegistersDefinedFromSameValue(*li_, *tri_, CP, MI, lr, DupCopies))
       continue;
 
     LHSValsDefinedFromRHS[VNI] = lr->valno;
@@ -1359,7 +1362,7 @@
     // from the LHS interval, we can use its value #.
     MachineInstr *MI = VNI->getCopy();
     if (!CP.isCoalescable(MI) &&
-        !RegistersDefinedFromSameValue(*tri_, CP, MI, lr, DupCopies))
+        !RegistersDefinedFromSameValue(*li_, *tri_, CP, MI, lr, DupCopies))
         continue;
 
     RHSValsDefinedFromLHS[VNI] = lr->valno;



From stoklund at 2pi.dk  Thu Jun 30 21:40:22 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 30 Jun 2011 19:40:22 -0700
Subject: [llvm-commits] [llvm] r134228 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
In-Reply-To: <20110701023506.BD5852A6C12C@llvm.org>
References: <20110701023506.BD5852A6C12C@llvm.org>
Message-ID: <52E9F4B0-EF29-414F-A217-2419A8C03398@2pi.dk>


On Jun 30, 2011, at 7:35 PM, Rafael Espindola wrote:

> +  SlotIndex CopyIdx = li.getInstructionIndex(MI).getNextIndex().getDefIndex();

You probably didn't mean to use getNextIndex(). It gives you the next instruction in the function.

/jakob

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From stoklund at 2pi.dk  Thu Jun 30 21:42:16 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 30 Jun 2011 19:42:16 -0700
Subject: [llvm-commits] [llvm] r134228 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
In-Reply-To: <52E9F4B0-EF29-414F-A217-2419A8C03398@2pi.dk>
References: <20110701023506.BD5852A6C12C@llvm.org>
	<52E9F4B0-EF29-414F-A217-2419A8C03398@2pi.dk>
Message-ID: <346976D8-EACE-4A93-9451-7D467097ADFD@2pi.dk>


On Jun 30, 2011, at 7:40 PM, Jakob Stoklund Olesen wrote:

> 
> On Jun 30, 2011, at 7:35 PM, Rafael Espindola wrote:
> 
>> +  SlotIndex CopyIdx = li.getInstructionIndex(MI).getNextIndex().getDefIndex();
> 
> You probably didn't mean to use getNextIndex(). It gives you the next instruction in the function.

Actually, VNI->def gives you the slot you need, and doesn't require a DenseMap lookup.

/jakob

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From rafael.espindola at gmail.com  Thu Jun 30 22:31:30 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 01 Jul 2011 03:31:30 -0000
Subject: [llvm-commits] [llvm] r134229 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
Message-ID: <20110701033130.128952A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 30 22:31:29 2011
New Revision: 134229

URL: http://llvm.org/viewvc/llvm-project?rev=134229&view=rev
Log:
Fix off by one error. I misunderstood the comment about killedAt.

Modified:
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=134229&r1=134228&r2=134229&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Thu Jun 30 22:31:29 2011
@@ -1213,7 +1213,7 @@
 
   // FIXME: If "B = X" kills X, we have to move the kill back to its
   // previous use. For now we just avoid the optimization in that case.
-  SlotIndex CopyIdx = li.getInstructionIndex(MI).getNextIndex().getDefIndex();
+  SlotIndex CopyIdx = li.getInstructionIndex(MI).getDefIndex();
   LiveInterval &SrcInt = li.getInterval(Src);
   if (SrcInt.killedAt(CopyIdx))
     return false;



From rafael.espindola at gmail.com  Thu Jun 30 23:15:02 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 01 Jul 2011 04:15:02 -0000
Subject: [llvm-commits] [llvm] r134231 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
Message-ID: <20110701041502.72DE62A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 30 23:15:02 2011
New Revision: 134231

URL: http://llvm.org/viewvc/llvm-project?rev=134231&view=rev
Log:
Avoid DenseMap lookup.

Modified:
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=134231&r1=134230&r2=134231&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Thu Jun 30 23:15:02 2011
@@ -1195,16 +1195,19 @@
 // A = X
 // B = A
 // which allows us to coalesce A and B.
-// MI is the definition of B. LR is the life range of A that includes
+// VNI is the definition of B. LR is the life range of A that includes
 // the slot just before B. If we return true, we add "B = X" to DupCopies.
 static bool RegistersDefinedFromSameValue(LiveIntervals &li,
                                           const TargetRegisterInfo &tri,
-                                          CoalescerPair &CP, MachineInstr *MI,
+                                          CoalescerPair &CP,
+                                          VNInfo *VNI,
                                           LiveRange *LR,
                                      SmallVector &DupCopies) {
   // FIXME: This is very conservative. For example, we don't handle
   // physical registers.
 
+  MachineInstr *MI = VNI->getCopy();
+
   if (!MI->isFullCopy() || CP.isPartial() || CP.isPhys())
     return false;
 
@@ -1213,9 +1216,8 @@
 
   // FIXME: If "B = X" kills X, we have to move the kill back to its
   // previous use. For now we just avoid the optimization in that case.
-  SlotIndex CopyIdx = li.getInstructionIndex(MI).getDefIndex();
   LiveInterval &SrcInt = li.getInterval(Src);
-  if (SrcInt.killedAt(CopyIdx))
+  if (SrcInt.killedAt(VNI->def))
     return false;
 
   if (!TargetRegisterInfo::isVirtualRegister(Src) ||
@@ -1335,7 +1337,7 @@
     // from the RHS interval, we can use its value #.
     MachineInstr *MI = VNI->getCopy();
     if (!CP.isCoalescable(MI) &&
-        !RegistersDefinedFromSameValue(*li_, *tri_, CP, MI, lr, DupCopies))
+        !RegistersDefinedFromSameValue(*li_, *tri_, CP, VNI, lr, DupCopies))
       continue;
 
     LHSValsDefinedFromRHS[VNI] = lr->valno;
@@ -1362,7 +1364,7 @@
     // from the LHS interval, we can use its value #.
     MachineInstr *MI = VNI->getCopy();
     if (!CP.isCoalescable(MI) &&
-        !RegistersDefinedFromSameValue(*li_, *tri_, CP, MI, lr, DupCopies))
+        !RegistersDefinedFromSameValue(*li_, *tri_, CP, VNI, lr, DupCopies))
         continue;
 
     RHSValsDefinedFromLHS[VNI] = lr->valno;



From rafael.espindola at gmail.com  Thu Jun 30 23:40:50 2011
From: rafael.espindola at gmail.com (Rafael Espindola)
Date: Fri, 01 Jul 2011 04:40:50 -0000
Subject: [llvm-commits] [llvm] r134234 - in /llvm/trunk:
 include/llvm/MC/SubtargetFeature.h lib/MC/SubtargetFeature.cpp
Message-ID: <20110701044050.E33792A6C12C@llvm.org>

Author: rafael
Date: Thu Jun 30 23:40:50 2011
New Revision: 134234

URL: http://llvm.org/viewvc/llvm-project?rev=134234&view=rev
Log:
Fix use after free.

Modified:
    llvm/trunk/include/llvm/MC/SubtargetFeature.h
    llvm/trunk/lib/MC/SubtargetFeature.cpp

Modified: llvm/trunk/include/llvm/MC/SubtargetFeature.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/SubtargetFeature.h?rev=134234&r1=134233&r2=134234&view=diff
==============================================================================
--- llvm/trunk/include/llvm/MC/SubtargetFeature.h (original)
+++ llvm/trunk/include/llvm/MC/SubtargetFeature.h Thu Jun 30 23:40:50 2011
@@ -77,7 +77,7 @@
   explicit SubtargetFeatures(const StringRef Initial = "");
 
   /// Features string accessors.
-  StringRef getString() const;
+  std::string getString() const;
 
   /// Adding Features.
   void AddFeature(const StringRef String, bool IsEnabled = true);

Modified: llvm/trunk/lib/MC/SubtargetFeature.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/SubtargetFeature.cpp?rev=134234&r1=134233&r2=134234&view=diff
==============================================================================
--- llvm/trunk/lib/MC/SubtargetFeature.cpp (original)
+++ llvm/trunk/lib/MC/SubtargetFeature.cpp Thu Jun 30 23:40:50 2011
@@ -182,7 +182,7 @@
 }
 
 
-StringRef SubtargetFeatures::getString() const {
+std::string SubtargetFeatures::getString() const {
   return Join(Features);
 }
 



From stoklund at 2pi.dk  Fri Jul  1 00:34:19 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Thu, 30 Jun 2011 22:34:19 -0700
Subject: [llvm-commits] [llvm] r134231 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
In-Reply-To: <20110701041502.72DE62A6C12C@llvm.org>
References: <20110701041502.72DE62A6C12C@llvm.org>
Message-ID: <709F0D4D-92F8-41BF-844E-7680046E45F8@2pi.dk>


On Jun 30, 2011, at 9:15 PM, Rafael Espindola wrote:

>   // FIXME: If "B = X" kills X, we have to move the kill back to its
>   // previous use. For now we just avoid the optimization in that case.

This is actually an easy FIXME. Se the other places that call li_->shrinkToUses() after remat etc.

The only trick is to call it after markAsJoined() has undef'ed all operands on the COPY instruction that is going away. Otherwise the undead COPY would still require liveness.

/jakob

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From sanjoy at playingwithpointers.com  Thu Jun 30 22:18:12 2011
From: sanjoy at playingwithpointers.com (Sanjoy Das)
Date: Fri, 01 Jul 2011 08:48:12 +0530
Subject: [llvm-commits] Segmented stacks, current status.
In-Reply-To: 
References: <4E089271.40607@playingwithpointers.com>	<4E09FBDB.5050401@gmail.com>	<4E0CA66B.8020904@playingwithpointers.com>
	
Message-ID: <4E0D3C74.3010906@playingwithpointers.com>

Hi!

> R10 is used for 'nest' parameters, so IIUC it can be live-in. (See
> lib/Target/X86/X86CallingConv.td)
> R11 is probably a better choice.

If R10 is not available, currently, segmented stacks cannot be used at
all - both R10 and R11 are used to pass information to the stack
allocation routine in libgcc.

In fact GCC complains when segmented stacks are enabled in a function
that uses nest parameters. I had let the thing slide initially because I
was not clear on what a `nest parameter' was.

This limitation can be worked on if and when we implement our own stack
handling runtime - perhaps by pushing the parameters in both 32 and 64
bit architectures.

-- 
Sanjoy Das
http://playingwithpointers.com

From nicholas at mxc.ca  Fri Jul  1 01:27:03 2011
From: nicholas at mxc.ca (Nick Lewycky)
Date: Fri, 01 Jul 2011 06:27:03 -0000
Subject: [llvm-commits] [llvm] r134235 -
	/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
Message-ID: <20110701062703.61DD82A6C12C@llvm.org>

Author: nicholas
Date: Fri Jul  1 01:27:03 2011
New Revision: 134235

URL: http://llvm.org/viewvc/llvm-project?rev=134235&view=rev
Log:
Fix likely typo, reduce number of instruction name collisions.

Modified:
    llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp

Modified: llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp?rev=134235&r1=134234&r2=134235&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp (original)
+++ llvm/trunk/lib/Transforms/Scalar/ScalarReplAggregates.cpp Fri Jul  1 01:27:03 2011
@@ -1303,7 +1303,7 @@
         LoadInst *TrueLoad = 
           Builder.CreateLoad(SI->getTrueValue(), LI->getName()+".t");
         LoadInst *FalseLoad = 
-          Builder.CreateLoad(SI->getFalseValue(), LI->getName()+".t");
+          Builder.CreateLoad(SI->getFalseValue(), LI->getName()+".f");
         
         // Transfer alignment and TBAA info if present.
         TrueLoad->setAlignment(LI->getAlignment());



From baldrick at free.fr  Fri Jul  1 02:25:41 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 01 Jul 2011 09:25:41 +0200
Subject: [llvm-commits] [llvm] r134199
	-	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
In-Reply-To: <20110630222413.C25F02A6C12C@llvm.org>
References: <20110630222413.C25F02A6C12C@llvm.org>
Message-ID: <4E0D7675.5070105@free.fr>

> Don't give up on coalescing A and B when we find
>
> A = X
> B = X
>
> Instead, proceed as if we had found
>
> A = X
> B = A

Testcase?

Ciao, Duncan.

From dmalyshev at accesssoftek.com  Fri Jul  1 02:55:27 2011
From: dmalyshev at accesssoftek.com (Danil Malyshev)
Date: Fri, 1 Jul 2011 00:55:27 -0700
Subject: [llvm-commits] Add to RuntimeDyld support different object formats
Message-ID: <6AE1604EE3EC5F4296C096518C6B77EE17F1ACBF5D@mail.accesssoftek.com>

Hello everyone,

Please find attached the patch for review.
This patch re-factors the RuntimeDyldImpl to support multiple formats as following:


 1.  All MachO-specific code has been moved to a new MachODyldImpl class which derives from RuntimeDyldImpl.
 2.  Changed RuntimeDyldImpl class to keep only code common for all formats.
 3.  Changed RuntimeDyld::loadObject() to figure out the given object format and instantiate a specific implementation (for now only MachO is supported, but I'll add implementation for ELF in the coming patches).

How does it look?


Regards,
Danil

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From zwarich at apple.com  Fri Jul  1 04:01:00 2011
From: zwarich at apple.com (Cameron Zwarich)
Date: Fri, 01 Jul 2011 02:01:00 -0700
Subject: [llvm-commits] [llvm] r134219 - in /llvm/trunk:
 include/llvm/MC/SubtargetFeature.h lib/MC/SubtargetFeature.cpp
In-Reply-To: <20110701002310.6045D2A6C12C@llvm.org>
References: <20110701002310.6045D2A6C12C@llvm.org>
Message-ID: <1D983085-88AF-4235-9D1A-695AC4BDF2A9@apple.com>

It looks like this is causing the Valgrind bot failures:

http://google1.osuosl.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/1387

Cameron

On 2011-06-30, at 5:23 PM, Evan Cheng wrote:

> Author: evancheng
> Date: Thu Jun 30 19:23:10 2011
> New Revision: 134219
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=134219&view=rev
> Log:
> Switch SubtargetFeatures from std::string to StringRef.
> 
> Modified:
>    llvm/trunk/include/llvm/MC/SubtargetFeature.h
>    llvm/trunk/lib/MC/SubtargetFeature.cpp
> 
> Modified: llvm/trunk/include/llvm/MC/SubtargetFeature.h
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/SubtargetFeature.h?rev=134219&r1=134218&r2=134219&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/MC/SubtargetFeature.h (original)
> +++ llvm/trunk/include/llvm/MC/SubtargetFeature.h Thu Jun 30 19:23:10 2011
> @@ -18,13 +18,13 @@
> #ifndef LLVM_MC_SUBTARGETFEATURE_H
> #define LLVM_MC_SUBTARGETFEATURE_H
> 
> -#include 
> #include 
> #include "llvm/ADT/Triple.h"
> #include "llvm/Support/DataTypes.h"
> 
> namespace llvm {
>   class raw_ostream;
> +  class StringRef;
> 
> //===----------------------------------------------------------------------===//
> ///
> @@ -74,24 +74,23 @@
> class SubtargetFeatures {
>   std::vector Features;    // Subtarget features as a vector
> public:
> -  explicit SubtargetFeatures(const std::string &Initial = std::string());
> +  explicit SubtargetFeatures(const StringRef Initial = "");
> 
>   /// Features string accessors.
> -  std::string getString() const;
> -  void setString(const std::string &Initial);
> +  StringRef getString() const;
> 
>   /// Adding Features.
> -  void AddFeature(const std::string &String, bool IsEnabled = true);
> +  void AddFeature(const StringRef String, bool IsEnabled = true);
> 
>   /// Get feature bits of a CPU.
> -  uint64_t getFeatureBits(const std::string &CPU,
> +  uint64_t getFeatureBits(const StringRef CPU,
>                           const SubtargetFeatureKV *CPUTable,
>                           size_t CPUTableSize,
>                           const SubtargetFeatureKV *FeatureTable,
>                           size_t FeatureTableSize);
> 
>   /// Get scheduling itinerary of a CPU.
> -  void *getItinerary(const std::string &CPU,
> +  void *getItinerary(const StringRef CPU,
>                      const SubtargetInfoKV *Table, size_t TableSize);
> 
>   /// Print feature string.
> 
> Modified: llvm/trunk/lib/MC/SubtargetFeature.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/SubtargetFeature.cpp?rev=134219&r1=134218&r2=134219&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/SubtargetFeature.cpp (original)
> +++ llvm/trunk/lib/MC/SubtargetFeature.cpp Thu Jun 30 19:23:10 2011
> @@ -27,7 +27,7 @@
> 
> /// hasFlag - Determine if a feature has a flag; '+' or '-'
> ///
> -static inline bool hasFlag(const std::string &Feature) {
> +static inline bool hasFlag(const StringRef Feature) {
>   assert(!Feature.empty() && "Empty string");
>   // Get first character
>   char Ch = Feature[0];
> @@ -37,13 +37,13 @@
> 
> /// StripFlag - Return string stripped of flag.
> ///
> -static inline std::string StripFlag(const std::string &Feature) {
> +static inline std::string StripFlag(const StringRef Feature) {
>   return hasFlag(Feature) ? Feature.substr(1) : Feature;
> }
> 
> /// isEnabled - Return true if enable flag; '+'.
> ///
> -static inline bool isEnabled(const std::string &Feature) {
> +static inline bool isEnabled(const StringRef Feature) {
>   assert(!Feature.empty() && "Empty string");
>   // Get first character
>   char Ch = Feature[0];
> @@ -53,16 +53,19 @@
> 
> /// PrependFlag - Return a string with a prepended flag; '+' or '-'.
> ///
> -static inline std::string PrependFlag(const std::string &Feature,
> -                                      bool IsEnabled) {
> +static inline StringRef PrependFlag(const StringRef Feature,
> +                                    bool IsEnabled) {
>   assert(!Feature.empty() && "Empty string");
> -  if (hasFlag(Feature)) return Feature;
> -  return std::string(IsEnabled ? "+" : "-") + Feature;
> +  if (hasFlag(Feature))
> +    return Feature;
> +  std::string Prefix = IsEnabled ? "+" : "-";
> +  Prefix += Feature;
> +  return StringRef(Prefix);
> }
> 
> /// Split - Splits a string of comma separated items in to a vector of strings.
> ///
> -static void Split(std::vector &V, const std::string &S) {
> +static void Split(std::vector &V, const StringRef S) {
>   if (S.empty())
>     return;
> 
> @@ -106,7 +109,7 @@
> }
> 
> /// Adding features.
> -void SubtargetFeatures::AddFeature(const std::string &String,
> +void SubtargetFeatures::AddFeature(const StringRef String,
>                                    bool IsEnabled) {
>   // Don't add empty features
>   if (!String.empty()) {
> @@ -116,10 +119,10 @@
> }
> 
> /// Find KV in array using binary search.
> -template const T *Find(const std::string &S, const T *A, size_t L) {
> +template const T *Find(const StringRef S, const T *A, size_t L) {
>   // Make the lower bound element we're looking for
>   T KV;
> -  KV.Key = S.c_str();
> +  KV.Key = S.data();
>   // Determine the end of the array
>   const T *Hi = A + L;
>   // Binary search the array
> @@ -173,21 +176,15 @@
> //                    SubtargetFeatures Implementation
> //===----------------------------------------------------------------------===//
> 
> -SubtargetFeatures::SubtargetFeatures(const std::string &Initial) {
> +SubtargetFeatures::SubtargetFeatures(const StringRef Initial) {
>   // Break up string into separate features
>   Split(Features, Initial);
> }
> 
> 
> -std::string SubtargetFeatures::getString() const {
> +StringRef SubtargetFeatures::getString() const {
>   return Join(Features);
> }
> -void SubtargetFeatures::setString(const std::string &Initial) {
> -  // Throw out old features
> -  Features.clear();
> -  // Break up string into separate features
> -  Split(Features, LowercaseString(Initial));
> -}
> 
> /// SetImpliedBits - For each feature that is (transitively) implied by this
> /// feature, set it.
> @@ -229,7 +226,7 @@
> 
> /// getFeatureBits - Get feature bits a CPU.
> ///
> -uint64_t SubtargetFeatures::getFeatureBits(const std::string &CPU,
> +uint64_t SubtargetFeatures::getFeatureBits(const StringRef CPU,
>                                          const SubtargetFeatureKV *CPUTable,
>                                          size_t CPUTableSize,
>                                          const SubtargetFeatureKV *FeatureTable,
> @@ -272,7 +269,7 @@
>   }
>   // Iterate through each feature
>   for (size_t i = 0, E = Features.size(); i < E; i++) {
> -    const std::string &Feature = Features[i];
> +    const StringRef Feature = Features[i];
> 
>     // Check for help
>     if (Feature == "+help")
> @@ -306,7 +303,7 @@
> }
> 
> /// Get scheduling itinerary of a CPU.
> -void *SubtargetFeatures::getItinerary(const std::string &CPU,
> +void *SubtargetFeatures::getItinerary(const StringRef CPU,
>                                       const SubtargetInfoKV *Table,
>                                       size_t TableSize) {
>   assert(Table && "missing table");
> 
> 
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits

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From pichet2000 at gmail.com  Fri Jul  1 04:23:41 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Fri, 01 Jul 2011 09:23:41 -0000
Subject: [llvm-commits] [llvm] r134236 -
	/llvm/trunk/lib/MC/SubtargetFeature.cpp
Message-ID: <20110701092341.E51242A6C12C@llvm.org>

Author: fpichet
Date: Fri Jul  1 04:23:41 2011
New Revision: 134236

URL: http://llvm.org/viewvc/llvm-project?rev=134236&view=rev
Log:
Another misuse of StringRef. MSVC is very sensitive to that kind of error.

Modified:
    llvm/trunk/lib/MC/SubtargetFeature.cpp

Modified: llvm/trunk/lib/MC/SubtargetFeature.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/SubtargetFeature.cpp?rev=134236&r1=134235&r2=134236&view=diff
==============================================================================
--- llvm/trunk/lib/MC/SubtargetFeature.cpp (original)
+++ llvm/trunk/lib/MC/SubtargetFeature.cpp Fri Jul  1 04:23:41 2011
@@ -53,14 +53,14 @@
 
 /// PrependFlag - Return a string with a prepended flag; '+' or '-'.
 ///
-static inline StringRef PrependFlag(const StringRef Feature,
+static inline std::string PrependFlag(const StringRef Feature,
                                     bool IsEnabled) {
   assert(!Feature.empty() && "Empty string");
   if (hasFlag(Feature))
     return Feature;
   std::string Prefix = IsEnabled ? "+" : "-";
   Prefix += Feature;
-  return StringRef(Prefix);
+  return Prefix;
 }
 
 /// Split - Splits a string of comma separated items in to a vector of strings.



From pichet2000 at gmail.com  Fri Jul  1 04:26:57 2011
From: pichet2000 at gmail.com (Francois Pichet)
Date: Fri, 1 Jul 2011 05:26:57 -0400
Subject: [llvm-commits] [llvm] r134219 - in /llvm/trunk:
 include/llvm/MC/SubtargetFeature.h lib/MC/SubtargetFeature.cpp
In-Reply-To: <1D983085-88AF-4235-9D1A-695AC4BDF2A9@apple.com>
References: <20110701002310.6045D2A6C12C@llvm.org>
	<1D983085-88AF-4235-9D1A-695AC4BDF2A9@apple.com>
Message-ID: 

I think r134236 should fix the valgrind. It was causing a bunch of
MSVC failure too.
Another StringRef misuse.

On Fri, Jul 1, 2011 at 5:01 AM, Cameron Zwarich  wrote:
> It looks like this is causing the Valgrind bot failures:
> http://google1.osuosl.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/1387
> Cameron
> On 2011-06-30, at 5:23 PM, Evan Cheng wrote:
>
> Author: evancheng
> Date: Thu Jun 30 19:23:10 2011
> New Revision: 134219
>
> URL: http://llvm.org/viewvc/llvm-project?rev=134219&view=rev
> Log:
> Switch SubtargetFeatures from std::string to StringRef.
>
> Modified:
> ???llvm/trunk/include/llvm/MC/SubtargetFeature.h
> ???llvm/trunk/lib/MC/SubtargetFeature.cpp
>
> Modified: llvm/trunk/include/llvm/MC/SubtargetFeature.h
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/SubtargetFeature.h?rev=134219&r1=134218&r2=134219&view=diff
> ==============================================================================
> --- llvm/trunk/include/llvm/MC/SubtargetFeature.h (original)
> +++ llvm/trunk/include/llvm/MC/SubtargetFeature.h Thu Jun 30 19:23:10 2011
> @@ -18,13 +18,13 @@
> #ifndef LLVM_MC_SUBTARGETFEATURE_H
> #define LLVM_MC_SUBTARGETFEATURE_H
>
> -#include 
> #include 
> #include "llvm/ADT/Triple.h"
> #include "llvm/Support/DataTypes.h"
>
> namespace llvm {
> ??class raw_ostream;
> + ?class StringRef;
>
> //===----------------------------------------------------------------------===//
> ///
> @@ -74,24 +74,23 @@
> class SubtargetFeatures {
> ??std::vector Features; ???// Subtarget features as a vector
> public:
> - ?explicit SubtargetFeatures(const std::string &Initial = std::string());
> + ?explicit SubtargetFeatures(const StringRef Initial = "");
>
> ??/// Features string accessors.
> - ?std::string getString() const;
> - ?void setString(const std::string &Initial);
> + ?StringRef getString() const;
>
> ??/// Adding Features.
> - ?void AddFeature(const std::string &String, bool IsEnabled = true);
> + ?void AddFeature(const StringRef String, bool IsEnabled = true);
>
> ??/// Get feature bits of a CPU.
> - ?uint64_t getFeatureBits(const std::string &CPU,
> + ?uint64_t getFeatureBits(const StringRef CPU,
> ??????????????????????????const SubtargetFeatureKV *CPUTable,
> ??????????????????????????size_t CPUTableSize,
> ??????????????????????????const SubtargetFeatureKV *FeatureTable,
> ??????????????????????????size_t FeatureTableSize);
>
> ??/// Get scheduling itinerary of a CPU.
> - ?void *getItinerary(const std::string &CPU,
> + ?void *getItinerary(const StringRef CPU,
> ?????????????????????const SubtargetInfoKV *Table, size_t TableSize);
>
> ??/// Print feature string.
>
> Modified: llvm/trunk/lib/MC/SubtargetFeature.cpp
> URL:
> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/SubtargetFeature.cpp?rev=134219&r1=134218&r2=134219&view=diff
> ==============================================================================
> --- llvm/trunk/lib/MC/SubtargetFeature.cpp (original)
> +++ llvm/trunk/lib/MC/SubtargetFeature.cpp Thu Jun 30 19:23:10 2011
> @@ -27,7 +27,7 @@
>
> /// hasFlag - Determine if a feature has a flag; '+' or '-'
> ///
> -static inline bool hasFlag(const std::string &Feature) {
> +static inline bool hasFlag(const StringRef Feature) {
> ??assert(!Feature.empty() && "Empty string");
> ??// Get first character
> ??char Ch = Feature[0];
> @@ -37,13 +37,13 @@
>
> /// StripFlag - Return string stripped of flag.
> ///
> -static inline std::string StripFlag(const std::string &Feature) {
> +static inline std::string StripFlag(const StringRef Feature) {
> ??return hasFlag(Feature) ? Feature.substr(1) : Feature;
> }
>
> /// isEnabled - Return true if enable flag; '+'.
> ///
> -static inline bool isEnabled(const std::string &Feature) {
> +static inline bool isEnabled(const StringRef Feature) {
> ??assert(!Feature.empty() && "Empty string");
> ??// Get first character
> ??char Ch = Feature[0];
> @@ -53,16 +53,19 @@
>
> /// PrependFlag - Return a string with a prepended flag; '+' or '-'.
> ///
> -static inline std::string PrependFlag(const std::string &Feature,
> - ?????????????????????????????????????bool IsEnabled) {
> +static inline StringRef PrependFlag(const StringRef Feature,
> + ???????????????????????????????????bool IsEnabled) {
> ??assert(!Feature.empty() && "Empty string");
> - ?if (hasFlag(Feature)) return Feature;
> - ?return std::string(IsEnabled ? "+" : "-") + Feature;
> + ?if (hasFlag(Feature))
> + ???return Feature;
> + ?std::string Prefix = IsEnabled ? "+" : "-";
> + ?Prefix += Feature;
> + ?return StringRef(Prefix);
> }
>
> /// Split - Splits a string of comma separated items in to a vector of
> strings.
> ///
> -static void Split(std::vector &V, const std::string &S) {
> +static void Split(std::vector &V, const StringRef S) {
> ??if (S.empty())
> ????return;
>
> @@ -106,7 +109,7 @@
> }
>
> /// Adding features.
> -void SubtargetFeatures::AddFeature(const std::string &String,
> +void SubtargetFeatures::AddFeature(const StringRef String,
> ???????????????????????????????????bool IsEnabled) {
> ??// Don't add empty features
> ??if (!String.empty()) {
> @@ -116,10 +119,10 @@
> }
>
> /// Find KV in array using binary search.
> -template const T *Find(const std::string &S, const T *A, size_t
> L) {
> +template const T *Find(const StringRef S, const T *A, size_t L)
> {
> ??// Make the lower bound element we're looking for
> ??T KV;
> - ?KV.Key = S.c_str();
> + ?KV.Key = S.data();
> ??// Determine the end of the array
> ??const T *Hi = A + L;
> ??// Binary search the array
> @@ -173,21 +176,15 @@
> // ???????????????????SubtargetFeatures Implementation
> //===----------------------------------------------------------------------===//
>
> -SubtargetFeatures::SubtargetFeatures(const std::string &Initial) {
> +SubtargetFeatures::SubtargetFeatures(const StringRef Initial) {
> ??// Break up string into separate features
> ??Split(Features, Initial);
> }
>
>
> -std::string SubtargetFeatures::getString() const {
> +StringRef SubtargetFeatures::getString() const {
> ??return Join(Features);
> }
> -void SubtargetFeatures::setString(const std::string &Initial) {
> - ?// Throw out old features
> - ?Features.clear();
> - ?// Break up string into separate features
> - ?Split(Features, LowercaseString(Initial));
> -}
>
> /// SetImpliedBits - For each feature that is (transitively) implied by this
> /// feature, set it.
> @@ -229,7 +226,7 @@
>
> /// getFeatureBits - Get feature bits a CPU.
> ///
> -uint64_t SubtargetFeatures::getFeatureBits(const std::string &CPU,
> +uint64_t SubtargetFeatures::getFeatureBits(const StringRef CPU,
> ?????????????????????????????????????????const SubtargetFeatureKV *CPUTable,
> ?????????????????????????????????????????size_t CPUTableSize,
> ?????????????????????????????????????????const SubtargetFeatureKV
> *FeatureTable,
> @@ -272,7 +269,7 @@
> ??}
> ??// Iterate through each feature
> ??for (size_t i = 0, E = Features.size(); i < E; i++) {
> - ???const std::string &Feature = Features[i];
> + ???const StringRef Feature = Features[i];
>
> ????// Check for help
> ????if (Feature == "+help")
> @@ -306,7 +303,7 @@
> }
>
> /// Get scheduling itinerary of a CPU.
> -void *SubtargetFeatures::getItinerary(const std::string &CPU,
> +void *SubtargetFeatures::getItinerary(const StringRef CPU,
> ??????????????????????????????????????const SubtargetInfoKV *Table,
> ??????????????????????????????????????size_t TableSize) {
> ??assert(Table && "missing table");
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>
> _______________________________________________
> llvm-commits mailing list
> llvm-commits at cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>
>


From zwarich at apple.com  Fri Jul  1 04:59:08 2011
From: zwarich at apple.com (Cameron Zwarich)
Date: Fri, 01 Jul 2011 02:59:08 -0700
Subject: [llvm-commits] [patch] Improve register coalescing
In-Reply-To: <4E0CEC75.40303@gmail.com>
References: <4E0B9D31.3020101@gmail.com>
	<5C5CA408-CEC6-49E2-88CF-55C315AF3D97@2pi.dk>
	<4E0CEC75.40303@gmail.com>
Message-ID: <5FF8EE14-868C-4180-B26A-C769A253E626@apple.com>

On 2011-06-30, at 2:36 PM, Rafael ?vila de Esp?ndola wrote:

> An updated copy is attached.
> 
>> Would it be possible to do more complete value-based checking? For
>> example, you don't handle this:
>> 
>> X = Y A = X B = Y
> 
> but it doesn't handle this, we would have to coalesce X and Y first (which might fail).
> 
> The real solution I think would be to turn the coalescing algorithm
> upside down: instead of trying to merge registers one pair at a time,
> start by assuming that every copy related register can be merged and
> try to show it cannot.

If you consider a pair and can't show that it cannot be merged, what do you do with it? Throw it back onto a worklist? Then you run into termination issues. If you remove it from consideration, then you're not doing anything fundamentally different than merging them one pair at a time.

Two variables with the same value don't interfere, and your copy chains suggestion simply causes more pairs of values to be recognized as identical. You could substitute any sound value numbering and the existing coalescing algorithm would be able to incorporate it.

There is one technique I have seen that is similar in spirit to your suggestion to assume that all copy-related registers can be merged. If you do coalescing with phis or parallel copies still in place, you can modify your heuristic to first search for a maximal non-interfering subset of the registers involved in that phi / parallel copy, and then merge those together first.

This is probably the best paper on the problem of phi elimination and the coalescing that ensues:

http://perso.ens-lyon.fr/fabrice.rastello/Biblio_Perso/Articles/CGO2009.pdf

The trick in the patch you just landed is called "copy sharing" there. Of course, our coalescer does a lot of important tricks involving cross-class copies, subregisters, and 2-address instructions that don't really show up anywhere in the literature.

Cameron
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From baldrick at free.fr  Fri Jul  1 07:01:00 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 01 Jul 2011 12:01:00 -0000
Subject: [llvm-commits] [llvm] r134237 -
	/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
Message-ID: <20110701120100.482372A6C12C@llvm.org>

Author: baldrick
Date: Fri Jul  1 07:01:00 2011
New Revision: 134237

URL: http://llvm.org/viewvc/llvm-project?rev=134237&view=rev
Log:
Disable commit 134216 ("Add 134199 back, but disable the optimization when the second
copy is a kill") to see if it fixes the i386 dragonegg buildbot, which is timing out
because gcc built with dragonegg is going into an infinite loop.

Modified:
    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Modified: llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp?rev=134237&r1=134236&r2=134237&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp (original)
+++ llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp Fri Jul  1 07:01:00 2011
@@ -1203,6 +1203,7 @@
                                           VNInfo *VNI,
                                           LiveRange *LR,
                                      SmallVector &DupCopies) {
+  return false; // To see if this fixes the i386 dragonegg buildbot miscompile.
   // FIXME: This is very conservative. For example, we don't handle
   // physical registers.
 



From baldrick at free.fr  Fri Jul  1 07:44:01 2011
From: baldrick at free.fr (Duncan Sands)
Date: Fri, 01 Jul 2011 14:44:01 +0200
Subject: [llvm-commits] [LLVMdev] How to identify LLVM version? [updated
 patch]
In-Reply-To: <4E0B9363.6040807@rawbw.com>
References: <81AE5BE6-D456-472B-9AF3-1EF93FF17D23@gmail.com>	<87hb8a1xk8.fsf@wanadoo.es>	<4DE54671.5080804@free.fr>	<4DE54F97.10004@rawbw.com>	<4DE64C80.1070900@free.fr>	<4DE93048.7070706@rawbw.com>
	<4E0B9363.6040807@rawbw.com>
Message-ID: <4E0DC111.9090804@free.fr>

Hi Yuri,

> +/*===-- Version -----------------------------------------------------------===*/
> +
> +typedef enum {
> +  /* Terminator Instructions */

^ Strange comment

> +  LLVMVersionNumber     = 1,
> +  LLVMVersionRepository = 2
> +} LLVMVersion;
> +
> +const char* LLVMGetVersion(LLVMVersion VN);

I think it would be better to get rid of the enum and have two functions.

> +SVNVERSION   := $(shell cd $(PROJ_SRC_ROOT)&&  (LC_ALL=C svnversion -cn . 2>/dev/null | sed -e "s/.*://" -e "s/\([0-9]*\).*/\1/" | grep "[0-9]" || LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep "[0-9]" || echo unknown))
> +CPPFLAGS     += -DREPOSITORY_REVISION="\"$(SVNVERSION)\""

I don't much like this.  Probably there should be some helper for determining
the revision.  And does everyone have sed and awk?  And what about when building
a release so there is no repository, no svn or git?

Ciao, Duncan.

From ismail at namtrac.org  Fri Jul  1 07:53:31 2011
From: ismail at namtrac.org (=?UTF-8?B?xLBzbWFpbCBEw7ZubWV6?=)
Date: Fri, 1 Jul 2011 14:53:31 +0200
Subject: [llvm-commits] [LLVMdev] How to identify LLVM version? [updated
	patch]
In-Reply-To: <4E0DC111.9090804@free.fr>
References: <81AE5BE6-D456-472B-9AF3-1EF93FF17D23@gmail.com>
	<87hb8a1xk8.fsf@wanadoo.es> <4DE54671.5080804@free.fr>
	<4DE54F97.10004@rawbw.com>
	<4DE64C80.1070900@free.fr> <4DE93048.7070706@rawbw.com>
	<4E0B9363.6040807@rawbw.com> <4E0DC111.9090804@free.fr>
Message-ID: 

Hi;

On Fri, Jul 1, 2011 at 2:44 PM, Duncan Sands  wrote:

> Hi Yuri,
>
> > +/*===-- Version
> -----------------------------------------------------------===*/
> > +
> > +typedef enum {
> > +  /* Terminator Instructions */
>
> ^ Strange comment
>
> > +  LLVMVersionNumber     = 1,
> > +  LLVMVersionRepository = 2
> > +} LLVMVersion;
> > +
> > +const char* LLVMGetVersion(LLVMVersion VN);
>
> I think it would be better to get rid of the enum and have two functions.
>
> > +SVNVERSION   := $(shell cd $(PROJ_SRC_ROOT)&&  (LC_ALL=C svnversion -cn
> . 2>/dev/null | sed -e "s/.*://" -e "s/\([0-9]*\).*/\1/" | grep "[0-9]" ||
> LC_ALL=C svn info . 2>/dev/null | awk '/^Revision:/ {print $$2 }' | grep
> "[0-9]" || LC_ALL=C git svn info . 2>/dev/null | awk '/^Revision:/ {print
> $$2 }' | grep "[0-9]" || echo unknown))
> > +CPPFLAGS     += -DREPOSITORY_REVISION="\"$(SVNVERSION)\""
>
> I don't much like this.  Probably there should be some helper for
> determining
> the revision.  And does everyone have sed and awk?  And what about when
> building
> a release so there is no repository, no svn or git?
>

Here is the version.sh script from mplayer;

# releases extract the version number from the VERSION file
version=$(cat VERSION 2> /dev/null)

if test -z $version ; then
# Extract revision number from file used by daily tarball snapshots
# or from the places different Subversion versions have it.
svn_revision=$(cat snapshot_version 2> /dev/null)
test $svn_revision || svn_revision=$(LC_ALL=C svn info 2> /dev/null | grep
Revision | cut -d' ' -f2)
test $svn_revision || svn_revision=$(grep revision .svn/entries 2>/dev/null
| cut -d '"' -f2)
test $svn_revision || svn_revision=$(sed -n -e '/^dir$/{n;p;q;}'
.svn/entries 2>/dev/null)
test $svn_revision && svn_revision=SVN-r$svn_revision
test $svn_revision || svn_revision=UNKNOWN
version=$svn_revision
fi

Regards,
ismail
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From evan.cheng at apple.com  Fri Jul  1 11:55:00 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 01 Jul 2011 09:55:00 -0700
Subject: [llvm-commits] [llvm] r134219 - in /llvm/trunk:
 include/llvm/MC/SubtargetFeature.h lib/MC/SubtargetFeature.cpp
In-Reply-To: 
References: <20110701002310.6045D2A6C12C@llvm.org>
	<1D983085-88AF-4235-9D1A-695AC4BDF2A9@apple.com>
	
Message-ID: <5B4582FA-E553-45F7-919B-FCE37A889AEE@apple.com>

Sorry about the breakage. I had fixed it but forgot to check it in. 

Evan

On Jul 1, 2011, at 2:26 AM, Francois Pichet wrote:

> I think r134236 should fix the valgrind. It was causing a bunch of
> MSVC failure too.
> Another StringRef misuse.
> 
> On Fri, Jul 1, 2011 at 5:01 AM, Cameron Zwarich  wrote:
>> It looks like this is causing the Valgrind bot failures:
>> http://google1.osuosl.org:8011/builders/llvm-x86_64-linux-vg_leak/builds/1387
>> Cameron
>> On 2011-06-30, at 5:23 PM, Evan Cheng wrote:
>> 
>> Author: evancheng
>> Date: Thu Jun 30 19:23:10 2011
>> New Revision: 134219
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=134219&view=rev
>> Log:
>> Switch SubtargetFeatures from std::string to StringRef.
>> 
>> Modified:
>>    llvm/trunk/include/llvm/MC/SubtargetFeature.h
>>    llvm/trunk/lib/MC/SubtargetFeature.cpp
>> 
>> Modified: llvm/trunk/include/llvm/MC/SubtargetFeature.h
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/SubtargetFeature.h?rev=134219&r1=134218&r2=134219&view=diff
>> ==============================================================================
>> --- llvm/trunk/include/llvm/MC/SubtargetFeature.h (original)
>> +++ llvm/trunk/include/llvm/MC/SubtargetFeature.h Thu Jun 30 19:23:10 2011
>> @@ -18,13 +18,13 @@
>> #ifndef LLVM_MC_SUBTARGETFEATURE_H
>> #define LLVM_MC_SUBTARGETFEATURE_H
>> 
>> -#include 
>> #include 
>> #include "llvm/ADT/Triple.h"
>> #include "llvm/Support/DataTypes.h"
>> 
>> namespace llvm {
>>   class raw_ostream;
>> +  class StringRef;
>> 
>> //===----------------------------------------------------------------------===//
>> ///
>> @@ -74,24 +74,23 @@
>> class SubtargetFeatures {
>>   std::vector Features;    // Subtarget features as a vector
>> public:
>> -  explicit SubtargetFeatures(const std::string &Initial = std::string());
>> +  explicit SubtargetFeatures(const StringRef Initial = "");
>> 
>>   /// Features string accessors.
>> -  std::string getString() const;
>> -  void setString(const std::string &Initial);
>> +  StringRef getString() const;
>> 
>>   /// Adding Features.
>> -  void AddFeature(const std::string &String, bool IsEnabled = true);
>> +  void AddFeature(const StringRef String, bool IsEnabled = true);
>> 
>>   /// Get feature bits of a CPU.
>> -  uint64_t getFeatureBits(const std::string &CPU,
>> +  uint64_t getFeatureBits(const StringRef CPU,
>>                           const SubtargetFeatureKV *CPUTable,
>>                           size_t CPUTableSize,
>>                           const SubtargetFeatureKV *FeatureTable,
>>                           size_t FeatureTableSize);
>> 
>>   /// Get scheduling itinerary of a CPU.
>> -  void *getItinerary(const std::string &CPU,
>> +  void *getItinerary(const StringRef CPU,
>>                      const SubtargetInfoKV *Table, size_t TableSize);
>> 
>>   /// Print feature string.
>> 
>> Modified: llvm/trunk/lib/MC/SubtargetFeature.cpp
>> URL:
>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/SubtargetFeature.cpp?rev=134219&r1=134218&r2=134219&view=diff
>> ==============================================================================
>> --- llvm/trunk/lib/MC/SubtargetFeature.cpp (original)
>> +++ llvm/trunk/lib/MC/SubtargetFeature.cpp Thu Jun 30 19:23:10 2011
>> @@ -27,7 +27,7 @@
>> 
>> /// hasFlag - Determine if a feature has a flag; '+' or '-'
>> ///
>> -static inline bool hasFlag(const std::string &Feature) {
>> +static inline bool hasFlag(const StringRef Feature) {
>>   assert(!Feature.empty() && "Empty string");
>>   // Get first character
>>   char Ch = Feature[0];
>> @@ -37,13 +37,13 @@
>> 
>> /// StripFlag - Return string stripped of flag.
>> ///
>> -static inline std::string StripFlag(const std::string &Feature) {
>> +static inline std::string StripFlag(const StringRef Feature) {
>>   return hasFlag(Feature) ? Feature.substr(1) : Feature;
>> }
>> 
>> /// isEnabled - Return true if enable flag; '+'.
>> ///
>> -static inline bool isEnabled(const std::string &Feature) {
>> +static inline bool isEnabled(const StringRef Feature) {
>>   assert(!Feature.empty() && "Empty string");
>>   // Get first character
>>   char Ch = Feature[0];
>> @@ -53,16 +53,19 @@
>> 
>> /// PrependFlag - Return a string with a prepended flag; '+' or '-'.
>> ///
>> -static inline std::string PrependFlag(const std::string &Feature,
>> -                                      bool IsEnabled) {
>> +static inline StringRef PrependFlag(const StringRef Feature,
>> +                                    bool IsEnabled) {
>>   assert(!Feature.empty() && "Empty string");
>> -  if (hasFlag(Feature)) return Feature;
>> -  return std::string(IsEnabled ? "+" : "-") + Feature;
>> +  if (hasFlag(Feature))
>> +    return Feature;
>> +  std::string Prefix = IsEnabled ? "+" : "-";
>> +  Prefix += Feature;
>> +  return StringRef(Prefix);
>> }
>> 
>> /// Split - Splits a string of comma separated items in to a vector of
>> strings.
>> ///
>> -static void Split(std::vector &V, const std::string &S) {
>> +static void Split(std::vector &V, const StringRef S) {
>>   if (S.empty())
>>     return;
>> 
>> @@ -106,7 +109,7 @@
>> }
>> 
>> /// Adding features.
>> -void SubtargetFeatures::AddFeature(const std::string &String,
>> +void SubtargetFeatures::AddFeature(const StringRef String,
>>                                    bool IsEnabled) {
>>   // Don't add empty features
>>   if (!String.empty()) {
>> @@ -116,10 +119,10 @@
>> }
>> 
>> /// Find KV in array using binary search.
>> -template const T *Find(const std::string &S, const T *A, size_t
>> L) {
>> +template const T *Find(const StringRef S, const T *A, size_t L)
>> {
>>   // Make the lower bound element we're looking for
>>   T KV;
>> -  KV.Key = S.c_str();
>> +  KV.Key = S.data();
>>   // Determine the end of the array
>>   const T *Hi = A + L;
>>   // Binary search the array
>> @@ -173,21 +176,15 @@
>> //                    SubtargetFeatures Implementation
>> //===----------------------------------------------------------------------===//
>> 
>> -SubtargetFeatures::SubtargetFeatures(const std::string &Initial) {
>> +SubtargetFeatures::SubtargetFeatures(const StringRef Initial) {
>>   // Break up string into separate features
>>   Split(Features, Initial);
>> }
>> 
>> 
>> -std::string SubtargetFeatures::getString() const {
>> +StringRef SubtargetFeatures::getString() const {
>>   return Join(Features);
>> }
>> -void SubtargetFeatures::setString(const std::string &Initial) {
>> -  // Throw out old features
>> -  Features.clear();
>> -  // Break up string into separate features
>> -  Split(Features, LowercaseString(Initial));
>> -}
>> 
>> /// SetImpliedBits - For each feature that is (transitively) implied by this
>> /// feature, set it.
>> @@ -229,7 +226,7 @@
>> 
>> /// getFeatureBits - Get feature bits a CPU.
>> ///
>> -uint64_t SubtargetFeatures::getFeatureBits(const std::string &CPU,
>> +uint64_t SubtargetFeatures::getFeatureBits(const StringRef CPU,
>>                                          const SubtargetFeatureKV *CPUTable,
>>                                          size_t CPUTableSize,
>>                                          const SubtargetFeatureKV
>> *FeatureTable,
>> @@ -272,7 +269,7 @@
>>   }
>>   // Iterate through each feature
>>   for (size_t i = 0, E = Features.size(); i < E; i++) {
>> -    const std::string &Feature = Features[i];
>> +    const StringRef Feature = Features[i];
>> 
>>     // Check for help
>>     if (Feature == "+help")
>> @@ -306,7 +303,7 @@
>> }
>> 
>> /// Get scheduling itinerary of a CPU.
>> -void *SubtargetFeatures::getItinerary(const std::string &CPU,
>> +void *SubtargetFeatures::getItinerary(const StringRef CPU,
>>                                       const SubtargetInfoKV *Table,
>>                                       size_t TableSize) {
>>   assert(Table && "missing table");
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
>> 
>> _______________________________________________
>> llvm-commits mailing list
>> llvm-commits at cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
>> 
>> 


From evan.cheng at apple.com  Fri Jul  1 11:59:30 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 01 Jul 2011 16:59:30 -0000
Subject: [llvm-commits] [llvm] r134240 -
	/llvm/trunk/lib/MC/SubtargetFeature.cpp
Message-ID: <20110701165930.573C22A6C12C@llvm.org>

Author: evancheng
Date: Fri Jul  1 11:59:30 2011
New Revision: 134240

URL: http://llvm.org/viewvc/llvm-project?rev=134240&view=rev
Log:
Eliminate one extra conversion.

Modified:
    llvm/trunk/lib/MC/SubtargetFeature.cpp

Modified: llvm/trunk/lib/MC/SubtargetFeature.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/SubtargetFeature.cpp?rev=134240&r1=134239&r2=134240&view=diff
==============================================================================
--- llvm/trunk/lib/MC/SubtargetFeature.cpp (original)
+++ llvm/trunk/lib/MC/SubtargetFeature.cpp Fri Jul  1 11:59:30 2011
@@ -128,7 +128,7 @@
   // Binary search the array
   const T *F = std::lower_bound(A, Hi, KV);
   // If not found then return NULL
-  if (F == Hi || std::string(F->Key) != S) return NULL;
+  if (F == Hi || StringRef(F->Key) != S) return NULL;
   // Return the found array item
   return F;
 }



From grosbach at apple.com  Fri Jul  1 12:14:11 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 01 Jul 2011 17:14:11 -0000
Subject: [llvm-commits] [llvm] r134242 - in /llvm/trunk/lib/Target/ARM:
 ARMExpandPseudoInsts.cpp ARMInstrThumb.td ARMInstrThumb2.td
 Thumb2SizeReduction.cpp
Message-ID: <20110701171411.601412A6C12C@llvm.org>

Author: grosbach
Date: Fri Jul  1 12:14:11 2011
New Revision: 134242

URL: http://llvm.org/viewvc/llvm-project?rev=134242&view=rev
Log:
Pseudo-ize t2MOVCC[ri].

t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.


Modified:
    llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

Modified: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp?rev=134242&r1=134241&r2=134242&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp Fri Jul  1 12:14:11 2011
@@ -727,8 +727,10 @@
       MI.eraseFromParent();
       return true;
     }
+    case ARM::t2MOVCCr:
     case ARM::MOVCCr: {
-      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVr),
+      unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
+      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
               MI.getOperand(1).getReg())
         .addReg(MI.getOperand(2).getReg(),
                 getKillRegState(MI.getOperand(2).isKill()))
@@ -764,8 +766,10 @@
       MI.eraseFromParent();
       return true;
     }
+    case ARM::t2MOVCCi:
     case ARM::MOVCCi: {
-      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi),
+      unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
+      BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
               MI.getOperand(1).getReg())
         .addImm(MI.getOperand(2).getImm())
         .addImm(MI.getOperand(3).getImm()) // 'pred'

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb.td?rev=134242&r1=134241&r2=134242&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb.td Fri Jul  1 12:14:11 2011
@@ -1051,7 +1051,7 @@
   let Inst{7-0}  = imm8;
 }
 
-// TODO: A7-73: MOV(2) - mov setting flag.
+// A7-73: MOV(2) - mov setting flag.
 
 let neverHasSideEffects = 1 in {
 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
@@ -1215,31 +1215,6 @@
               NoItinerary,
              [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
 
-
-// 16-bit movcc in IT blocks for Thumb2.
-let neverHasSideEffects = 1 in {
-def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr,
-                    "mov", "\t$Rdn, $Rm", []>,
-              T1Special<{1,0,?,?}> {
-  bits<4> Rdn;
-  bits<4> Rm;
-  let Inst{7}   = Rdn{3};
-  let Inst{6-3} = Rm;
-  let Inst{2-0} = Rdn{2-0};
-}
-
-let isMoveImm = 1 in
-def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
-                    "mov", "\t$Rdn, $Rm", []>,
-              T1General<{1,0,0,?,?}> {
-  bits<3> Rdn;
-  bits<8> Rm;
-  let Inst{10-8} = Rdn;
-  let Inst{7-0}  = Rm;
-}
-
-} // neverHasSideEffects
-
 // tLEApcrel - Load a pc-relative address into a register without offending the
 // assembler.
 

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=134242&r1=134241&r2=134242&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Jul  1 12:14:11 2011
@@ -2664,35 +2664,21 @@
 // FIXME: should be able to write a pattern for ARMcmov, but can't use
 // a two-value operand where a dag node expects two operands. :(
 let neverHasSideEffects = 1 in {
-def t2MOVCCr : T2TwoReg<
-                   (outs rGPR:$Rd), (ins rGPR:$false, rGPR:$Rm), IIC_iCMOVr,
-                   "mov", ".w\t$Rd, $Rm",
+def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd),
+                            (ins rGPR:$false, rGPR:$Rm, pred:$p),
+                            Size4Bytes, IIC_iCMOVr,
    [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
-                RegConstraint<"$false = $Rd"> {
-  let Inst{31-27} = 0b11101;
-  let Inst{26-25} = 0b01;
-  let Inst{24-21} = 0b0010;
-  let Inst{20} = 0; // The S bit.
-  let Inst{19-16} = 0b1111; // Rn
-  let Inst{14-12} = 0b000;
-  let Inst{7-4} = 0b0000;
-}
+                RegConstraint<"$false = $Rd">;
 
-// FIXME: Pseudo-ize these. For now, just mark codegen only.
-let isCodeGenOnly = 1 in {
 let isMoveImm = 1 in
-def t2MOVCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm),
-                   IIC_iCMOVi, "mov", ".w\t$Rd, $imm",
+def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd),
+                            (ins rGPR:$false, t2_so_imm:$imm, pred:$p),
+                   Size4Bytes, IIC_iCMOVi,
 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>,
-                   RegConstraint<"$false = $Rd"> {
-  let Inst{31-27} = 0b11110;
-  let Inst{25} = 0;
-  let Inst{24-21} = 0b0010;
-  let Inst{20} = 0; // The S bit.
-  let Inst{19-16} = 0b1111; // Rn
-  let Inst{15} = 0;
-}
+                   RegConstraint<"$false = $Rd">;
 
+// FIXME: Pseudo-ize these. For now, just mark codegen only.
+let isCodeGenOnly = 1 in {
 let isMoveImm = 1 in
 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, i32imm_hilo16:$imm),
                       IIC_iCMOVi,
@@ -2759,8 +2745,8 @@
                              (ins rGPR:$false, rGPR:$Rm, i32imm:$imm),
                              IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>,
                  RegConstraint<"$false = $Rd">;
-} // neverHasSideEffects
 } // isCodeGenOnly = 1
+} // neverHasSideEffects
 
 //===----------------------------------------------------------------------===//
 // Atomic operations intrinsics

Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134242&r1=134241&r2=134242&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Fri Jul  1 12:14:11 2011
@@ -83,8 +83,6 @@
     { ARM::t2MOVi16,ARM::tMOVi8,  0,             8,   0,    1,   0,  0,0, 0,1 },
     // FIXME: Do we need the 16-bit 'S' variant?
     { ARM::t2MOVr,ARM::tMOVr,     0,             0,   0,    0,   0,  1,0, 0,0 },
-    { ARM::t2MOVCCr,0,            ARM::tMOVCCr,  0,   0,    0,   0,  0,1, 0,0 },
-    { ARM::t2MOVCCi,0,            ARM::tMOVCCi,  0,   8,    0,   1,  0,1, 0,0 },
     { ARM::t2MUL,   0,            ARM::tMUL,     0,   0,    0,   1,  0,0, 1,0 },
     { ARM::t2MVNr,  ARM::tMVN,    0,             0,   0,    1,   0,  0,0, 0,0 },
     { ARM::t2ORRrr, 0,            ARM::tORR,     0,   0,    0,   1,  0,0, 1,0 },



From stoklund at 2pi.dk  Fri Jul  1 12:34:20 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 01 Jul 2011 17:34:20 -0000
Subject: [llvm-commits] [test-suite] r134243 -
	/test-suite/trunk/SingleSource/UnitTests/Makefile
Message-ID: <20110701173420.8A7302A6C12C@llvm.org>

Author: stoklund
Date: Fri Jul  1 12:34:20 2011
New Revision: 134243

URL: http://llvm.org/viewvc/llvm-project?rev=134243&view=rev
Log:
Run ms_struct tests only on x86_64. They are target dependent.

Modified:
    test-suite/trunk/SingleSource/UnitTests/Makefile

Modified: test-suite/trunk/SingleSource/UnitTests/Makefile
URL: http://llvm.org/viewvc/llvm-project/test-suite/trunk/SingleSource/UnitTests/Makefile?rev=134243&r1=134242&r2=134243&view=diff
==============================================================================
--- test-suite/trunk/SingleSource/UnitTests/Makefile (original)
+++ test-suite/trunk/SingleSource/UnitTests/Makefile Fri Jul  1 12:34:20 2011
@@ -27,6 +27,11 @@
 endif
 endif
 
+# The ms_struct tests only make sense on x86_64.
+ifneq ($(ARCH),x86_64)
+PROGRAMS_TO_SKIP += ms_struct-bitfield-init-1 ms_struct-bitfield-init ms_struct-bitfield ms_struct_pack_layout-1 ms_struct_pack_layout 
+endif
+
 PROGRAM_REQUIRED_TO_EXIT_OK := 1
 
 LDFLAGS += -lstdc++



From evan.cheng at apple.com  Fri Jul  1 12:57:27 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 01 Jul 2011 17:57:27 -0000
Subject: [llvm-commits] [llvm] r134244 - in /llvm/trunk:
 include/llvm/Target/ lib/Target/ lib/Target/ARM/ lib/Target/Alpha/
 lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/
 lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/
 lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/
 utils/TableGen/
Message-ID: <20110701175728.75A9D2A6C12C@llvm.org>

Author: evancheng
Date: Fri Jul  1 12:57:27 2011
New Revision: 134244

URL: http://llvm.org/viewvc/llvm-project?rev=134244&view=rev
Log:
Hide the call to InitMCInstrInfo into tblgen generated ctor.

Modified:
    llvm/trunk/include/llvm/Target/TargetInstrInfo.h
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
    llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
    llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
    llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
    llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp
    llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h
    llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
    llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h
    llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h
    llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
    llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
    llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
    llvm/trunk/lib/Target/PTX/PTXInstrInfo.h
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
    llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
    llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
    llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
    llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h
    llvm/trunk/lib/Target/TargetInstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
    llvm/trunk/lib/Target/X86/X86InstrInfo.h
    llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp
    llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h
    llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/TargetInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetInstrInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -44,9 +44,11 @@
   TargetInstrInfo(const TargetInstrInfo &);  // DO NOT IMPLEMENT
   void operator=(const TargetInstrInfo &);   // DO NOT IMPLEMENT
 public:
-  TargetInstrInfo(const MCInstrDesc *desc, unsigned NumOpcodes,
-                  int CallFrameSetupOpcode = -1,
-                  int CallFrameDestroyOpcode = -1);
+  TargetInstrInfo(int CFSetupOpcode = -1, int CFDestroyOpcode = -1)
+    : CallFrameSetupOpcode(CFSetupOpcode),
+      CallFrameDestroyOpcode(CFDestroyOpcode) {
+  }
+    
   virtual ~TargetInstrInfo();
 
   /// getRegClass - Givem a machine instruction descriptor, returns the register
@@ -678,11 +680,9 @@
 /// libcodegen, not in libtarget.
 class TargetInstrInfoImpl : public TargetInstrInfo {
 protected:
-  TargetInstrInfoImpl(const MCInstrDesc *desc, unsigned NumOpcodes,
-                      int CallFrameSetupOpcode = -1,
+  TargetInstrInfoImpl(int CallFrameSetupOpcode = -1,
                       int CallFrameDestroyOpcode = -1)
-    : TargetInstrInfo(desc, NumOpcodes,
-                      CallFrameSetupOpcode, CallFrameDestroyOpcode) {}
+    : TargetInstrInfo(CallFrameSetupOpcode, CallFrameDestroyOpcode) {}
 public:
   virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
                                        MachineBasicBlock *NewDest) const;

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -36,6 +36,7 @@
 #include "llvm/ADT/STLExtras.h"
 
 #define GET_INSTRINFO_MC_DESC
+#define GET_INSTRINFO_CTOR
 #include "ARMGenInstrInfo.inc"
 
 using namespace llvm;
@@ -77,8 +78,7 @@
 };
 
 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
-  : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts),
-                        ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
+  : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
     Subtarget(STI) {
   for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
     if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)

Modified: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -20,6 +20,9 @@
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallSet.h"
 
+#define GET_INSTRINFO_HEADER
+#include "ARMGenInstrInfo.inc"
+
 namespace llvm {
   class ARMSubtarget;
   class ARMBaseRegisterInfo;
@@ -172,7 +175,7 @@
   };
 }
 
-class ARMBaseInstrInfo : public TargetInstrInfoImpl {
+class ARMBaseInstrInfo : public ARMGenInstrInfo {
   const ARMSubtarget &Subtarget;
 
 protected:

Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -21,13 +21,14 @@
 #include "llvm/Support/ErrorHandling.h"
 
 #define GET_INSTRINFO_MC_DESC
+#define GET_INSTRINFO_CTOR
 #include "AlphaGenInstrInfo.inc"
 using namespace llvm;
 
 AlphaInstrInfo::AlphaInstrInfo()
-  : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts),
-                        Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
-    RI(*this) { }
+  : AlphaGenInstrInfo(Alpha::ADJUSTSTACKDOWN, Alpha::ADJUSTSTACKUP),
+    RI(*this) {
+}
 
 
 unsigned 

Modified: llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -17,9 +17,12 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "AlphaRegisterInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "AlphaGenInstrInfo.inc"
+
 namespace llvm {
 
-class AlphaInstrInfo : public TargetInstrInfoImpl {
+class AlphaInstrInfo : public AlphaGenInstrInfo {
   const AlphaRegisterInfo RI;
 public:
   AlphaInstrInfo();

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -20,14 +20,14 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/Support/ErrorHandling.h"
 
+#define GET_INSTRINFO_CTOR
 #define GET_INSTRINFO_MC_DESC
 #include "BlackfinGenInstrInfo.inc"
 
 using namespace llvm;
 
 BlackfinInstrInfo::BlackfinInstrInfo(BlackfinSubtarget &ST)
-  : TargetInstrInfoImpl(BlackfinInsts, array_lengthof(BlackfinInsts),
-                        BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
+  : BlackfinGenInstrInfo(BF::ADJCALLSTACKDOWN, BF::ADJCALLSTACKUP),
     RI(ST, *this),
     Subtarget(ST) {}
 

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -17,9 +17,12 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "BlackfinRegisterInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "BlackfinGenInstrInfo.inc"
+
 namespace llvm {
 
-  class BlackfinInstrInfo : public TargetInstrInfoImpl {
+  class BlackfinInstrInfo : public BlackfinGenInstrInfo {
     const BlackfinRegisterInfo RI;
     const BlackfinSubtarget& Subtarget;
   public:

Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -22,6 +22,7 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/MC/MCContext.h"
 
+#define GET_INSTRINFO_CTOR
 #define GET_INSTRINFO_MC_DESC
 #include "SPUGenInstrInfo.inc"
 
@@ -53,8 +54,7 @@
 }
 
 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
-  : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0]),
-                        SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
+  : SPUGenInstrInfo(SPU::ADJCALLSTACKDOWN, SPU::ADJCALLSTACKUP),
     TM(tm),
     RI(*TM.getSubtargetImpl(), *this)
 { /* NOP */ }

Modified: llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -18,9 +18,12 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "SPURegisterInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "SPUGenInstrInfo.inc"
+
 namespace llvm {
   //! Cell SPU instruction information class
-  class SPUInstrInfo : public TargetInstrInfoImpl {
+  class SPUInstrInfo : public SPUGenInstrInfo {
     SPUTargetMachine &TM;
     const SPURegisterInfo RI;
   public:

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -21,14 +21,14 @@
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/ErrorHandling.h"
 
+#define GET_INSTRINFO_CTOR
 #define GET_INSTRINFO_MC_DESC
 #include "MBlazeGenInstrInfo.inc"
 
 using namespace llvm;
 
 MBlazeInstrInfo::MBlazeInstrInfo(MBlazeTargetMachine &tm)
-  : TargetInstrInfoImpl(MBlazeInsts, array_lengthof(MBlazeInsts),
-                        MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
+  : MBlazeGenInstrInfo(MBlaze::ADJCALLSTACKDOWN, MBlaze::ADJCALLSTACKUP),
     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
 
 static bool isZeroImm(const MachineOperand &op) {

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -19,6 +19,9 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "MBlazeRegisterInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "MBlazeGenInstrInfo.inc"
+
 namespace llvm {
 
 namespace MBlaze {
@@ -219,7 +222,7 @@
   };
 }
 
-class MBlazeInstrInfo : public TargetInstrInfoImpl {
+class MBlazeInstrInfo : public MBlazeGenInstrInfo {
   MBlazeTargetMachine &TM;
   const MBlazeRegisterInfo RI;
 public:

Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -22,14 +22,14 @@
 #include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Support/ErrorHandling.h"
 
+#define GET_INSTRINFO_CTOR
 #define GET_INSTRINFO_MC_DESC
 #include "MSP430GenInstrInfo.inc"
 
 using namespace llvm;
 
 MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
-  : TargetInstrInfoImpl(MSP430Insts, array_lengthof(MSP430Insts),
-                        MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
+  : MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
     RI(tm, *this), TM(tm) {}
 
 void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,

Modified: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h Fri Jul  1 12:57:27 2011
@@ -17,6 +17,9 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "MSP430RegisterInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "MSP430GenInstrInfo.inc"
+
 namespace llvm {
 
 class MSP430TargetMachine;
@@ -37,7 +40,7 @@
   };
 }
 
-class MSP430InstrInfo : public TargetInstrInfoImpl {
+class MSP430InstrInfo : public MSP430GenInstrInfo {
   const MSP430RegisterInfo RI;
   MSP430TargetMachine &TM;
 public:

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -19,14 +19,14 @@
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/ErrorHandling.h"
 
+#define GET_INSTRINFO_CTOR
 #define GET_INSTRINFO_MC_DESC
 #include "MipsGenInstrInfo.inc"
 
 using namespace llvm;
 
 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
-  : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts),
-                        Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
+  : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
 
 static bool isZeroImm(const MachineOperand &op) {

Modified: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -19,6 +19,9 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "MipsRegisterInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "MipsGenInstrInfo.inc"
+
 namespace llvm {
 
 namespace Mips {
@@ -164,7 +167,7 @@
   };
 }
 
-class MipsInstrInfo : public TargetInstrInfoImpl {
+class MipsInstrInfo : public MipsGenInstrInfo {
   MipsTargetMachine &TM;
   const MipsRegisterInfo RI;
 public:

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -21,13 +21,14 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 
+#define GET_INSTRINFO_CTOR
 #define GET_INSTRINFO_MC_DESC
 #include "PTXGenInstrInfo.inc"
 
 using namespace llvm;
 
 PTXInstrInfo::PTXInstrInfo(PTXTargetMachine &_TM)
-  : TargetInstrInfoImpl(PTXInsts, array_lengthof(PTXInsts)),
+  : PTXGenInstrInfo(),
     RI(_TM, *this), TM(_TM) {}
 
 static const struct map_entry {

Modified: llvm/trunk/lib/Target/PTX/PTXInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXInstrInfo.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -17,6 +17,9 @@
 #include "PTXRegisterInfo.h"
 #include "llvm/Target/TargetInstrInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "PTXGenInstrInfo.inc"
+
 namespace llvm {
 class PTXTargetMachine;
 
@@ -24,7 +27,7 @@
 class SDValue;
 class SelectionDAG;
 
-class PTXInstrInfo : public TargetInstrInfoImpl {
+class PTXInstrInfo : public PTXGenInstrInfo {
 private:
   const PTXRegisterInfo RI;
   PTXTargetMachine &TM;

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -28,6 +28,7 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/MC/MCAsmInfo.h"
 
+#define GET_INSTRINFO_CTOR
 #define GET_INSTRINFO_MC_DESC
 #include "PPCGenInstrInfo.inc"
 
@@ -39,8 +40,7 @@
 using namespace llvm;
 
 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
-  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts),
-                        PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
+  : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
     TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
 
 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for

Modified: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -18,6 +18,9 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "PPCRegisterInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "PPCGenInstrInfo.inc"
+
 namespace llvm {
 
 /// PPCII - This namespace holds all of the PowerPC target-specific
@@ -61,7 +64,7 @@
 } // end namespace PPCII
 
 
-class PPCInstrInfo : public TargetInstrInfoImpl {
+class PPCInstrInfo : public PPCGenInstrInfo {
   PPCTargetMachine &TM;
   const PPCRegisterInfo RI;
 

Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -21,14 +21,14 @@
 #include "llvm/Support/ErrorHandling.h"
 #include "SparcMachineFunctionInfo.h"
 
+#define GET_INSTRINFO_CTOR
 #define GET_INSTRINFO_MC_DESC
 #include "SparcGenInstrInfo.inc"
 
 using namespace llvm;
 
 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
-  : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts),
-                        SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
+  : SparcGenInstrInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
     RI(ST, *this), Subtarget(ST) {
 }
 

Modified: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -17,6 +17,9 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "SparcRegisterInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "SparcGenInstrInfo.inc"
+
 namespace llvm {
 
 /// SPII - This namespace holds all of the target specific flags that
@@ -31,7 +34,7 @@
   };
 }
 
-class SparcInstrInfo : public TargetInstrInfoImpl {
+class SparcInstrInfo : public SparcGenInstrInfo {
   const SparcRegisterInfo RI;
   const SparcSubtarget& Subtarget;
 public:

Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -23,14 +23,14 @@
 #include "llvm/CodeGen/PseudoSourceValue.h"
 #include "llvm/Support/ErrorHandling.h"
 
+#define GET_INSTRINFO_CTOR
 #define GET_INSTRINFO_MC_DESC
 #include "SystemZGenInstrInfo.inc"
 
 using namespace llvm;
 
 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
-  : TargetInstrInfoImpl(SystemZInsts, array_lengthof(SystemZInsts),
-                        SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
+  : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKUP, SystemZ::ADJCALLSTACKDOWN),
     RI(tm, *this), TM(tm) {
 }
 

Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -19,6 +19,9 @@
 #include "llvm/ADT/IndexedMap.h"
 #include "llvm/Target/TargetInstrInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "SystemZGenInstrInfo.inc"
+
 namespace llvm {
 
 class SystemZTargetMachine;
@@ -47,7 +50,7 @@
   };
 }
 
-class SystemZInstrInfo : public TargetInstrInfoImpl {
+class SystemZInstrInfo : public SystemZGenInstrInfo {
   const SystemZRegisterInfo RI;
   SystemZTargetMachine &TM;
 public:

Modified: llvm/trunk/lib/Target/TargetInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/TargetInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -24,13 +24,6 @@
 //  TargetInstrInfo
 //===----------------------------------------------------------------------===//
 
-TargetInstrInfo::TargetInstrInfo(const MCInstrDesc* Desc, unsigned numOpcodes,
-                                 int CFSetupOpcode, int CFDestroyOpcode)
-  : CallFrameSetupOpcode(CFSetupOpcode),
-    CallFrameDestroyOpcode(CFDestroyOpcode) {
-  InitMCInstrInfo(Desc, numOpcodes);
-}
-
 TargetInstrInfo::~TargetInstrInfo() {
 }
 

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -35,6 +35,7 @@
 #include "llvm/MC/MCAsmInfo.h"
 #include 
 
+#define GET_INSTRINFO_CTOR
 #define GET_INSTRINFO_MC_DESC
 #include "X86GenInstrInfo.inc"
 
@@ -54,13 +55,12 @@
                  cl::init(false), cl::Hidden);
 
 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
-  : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts),
-                        (tm.getSubtarget().is64Bit()
-                         ? X86::ADJCALLSTACKDOWN64
-                         : X86::ADJCALLSTACKDOWN32),
-                        (tm.getSubtarget().is64Bit()
-                         ? X86::ADJCALLSTACKUP64
-                         : X86::ADJCALLSTACKUP32)),
+  : X86GenInstrInfo((tm.getSubtarget().is64Bit()
+                     ? X86::ADJCALLSTACKDOWN64
+                     : X86::ADJCALLSTACKDOWN32),
+                    (tm.getSubtarget().is64Bit()
+                     ? X86::ADJCALLSTACKUP64
+                     : X86::ADJCALLSTACKUP32)),
     TM(tm), RI(tm, *this) {
   enum {
     TB_NOT_REVERSABLE = 1U << 31,

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.h (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.h Fri Jul  1 12:57:27 2011
@@ -19,6 +19,9 @@
 #include "X86RegisterInfo.h"
 #include "llvm/ADT/DenseMap.h"
 
+#define GET_INSTRINFO_HEADER
+#include "X86GenInstrInfo.inc"
+
 namespace llvm {
   class X86RegisterInfo;
   class X86TargetMachine;
@@ -611,7 +614,7 @@
     isLeaMem(MI, Op);
 }
 
-class X86InstrInfo : public TargetInstrInfoImpl {
+class X86InstrInfo : public X86GenInstrInfo {
   X86TargetMachine &TM;
   const X86RegisterInfo RI;
 

Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp Fri Jul  1 12:57:27 2011
@@ -22,6 +22,7 @@
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 
+#define GET_INSTRINFO_CTOR
 #define GET_INSTRINFO_MC_DESC
 #include "XCoreGenInstrInfo.inc"
 
@@ -40,8 +41,7 @@
 using namespace llvm;
 
 XCoreInstrInfo::XCoreInstrInfo()
-  : TargetInstrInfoImpl(XCoreInsts, array_lengthof(XCoreInsts),
-                        XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
+  : XCoreGenInstrInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
     RI(*this) {
 }
 

Modified: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h Fri Jul  1 12:57:27 2011
@@ -17,9 +17,12 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "XCoreRegisterInfo.h"
 
+#define GET_INSTRINFO_HEADER
+#include "XCoreGenInstrInfo.inc"
+
 namespace llvm {
 
-class XCoreInstrInfo : public TargetInstrInfoImpl {
+class XCoreInstrInfo : public XCoreGenInstrInfo {
   const XCoreRegisterInfo RI;
 public:
   XCoreInstrInfo();

Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=134244&r1=134243&r2=134244&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Fri Jul  1 12:57:27 2011
@@ -208,7 +208,6 @@
                OperandInfoIDs, OS);
   OS << "};\n\n";
 
-
   // MCInstrInfo initialization routine.
   OS << "static inline void Init" << TargetName
      << "MCInstrInfo(MCInstrInfo *II) {\n";
@@ -218,6 +217,31 @@
   OS << "} // End llvm namespace \n";
 
   OS << "#endif // GET_INSTRINFO_MC_DESC\n\n";
+
+  // Create a TargetInstrInfo subclass to hide the MC layer initialization.
+  OS << "\n#ifdef GET_INSTRINFO_HEADER\n";
+  OS << "#undef GET_INSTRINFO_HEADER\n";
+
+  std::string ClassName = TargetName + "GenInstrInfo";
+  OS << "namespace llvm {\n\n";
+  OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n"
+     << "  explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
+     << "};\n";
+  OS << "} // End llvm namespace \n";
+
+  OS << "#endif // GET_INSTRINFO_HEADER\n\n";
+
+  OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
+  OS << "#undef GET_INSTRINFO_CTOR\n";
+
+  OS << "namespace llvm {\n\n";
+  OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
+     << "  : TargetInstrInfoImpl(SO, DO) {\n"
+     << "  InitMCInstrInfo(" << TargetName << "Insts, "
+     << NumberedInstructions.size() << ");\n}\n";
+  OS << "} // End llvm namespace \n";
+
+  OS << "#endif // GET_INSTRINFO_CTOR\n\n";
 }
 
 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,



From stoklund at 2pi.dk  Fri Jul  1 13:34:16 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 01 Jul 2011 11:34:16 -0700
Subject: [llvm-commits] [llvm] r134018 - in /llvm/trunk:
 lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86FloatingPoint.cpp
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFPStack.td
 lib/Target/X86/X86RegisterInfo.cpp lib/Target/X86/X86RegisterInfo.td
 test/CodeGen/X86/inline-asm-fpstack.ll
In-Reply-To: 
References: <20110628183228.AA6722A6C12C@llvm.org>
	
Message-ID: <17853845-62DA-48C5-96EA-474C03F49D6D@2pi.dk>


On Jun 30, 2011, at 1:33 PM, Chad Rosier wrote:

> Hi Jakob,
> I'm seeing a failure for one of the clang llvm-gcc tests.  Bisect brought me to this revision, which seems very relevant.
> gcc.target/i386/pr30848.c (test for excess errors)
> mcrosier$ /Users/mcrosier/llvm-clean/install/bin/clang /Users/mcrosier/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c    -ansi -pedantic-errors -fno-show-column -S  -o pr30848.s
> fatal error: error in backend: Inline asm fixed outputs must be last on the x87 stack

Clang is failing correctly, but I fixed the message thusly:

clang -c /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c 
fatal error: error in backend: Inline asm output regs must be last on the x87 stack

However, DejaGNU is still failing the test:

$ cat src/gcc.target/i386/pr30848.c 
/* { dg-do compile } */

void foo(double d)
{
  __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
}

Anyone know how to fix the test suite?

Here is gcc-4.2:

$ gcc-4.2 -c /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c 
/d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c: In function ?foo?:
/d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c:5: error: output regs must be grouped at top of stack

/jakob

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From grosbach at apple.com  Fri Jul  1 14:07:09 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 01 Jul 2011 19:07:09 -0000
Subject: [llvm-commits] [llvm] r134247 -
	/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
Message-ID: <20110701190709.D6D8D2A6C12C@llvm.org>

Author: grosbach
Date: Fri Jul  1 14:07:09 2011
New Revision: 134247

URL: http://llvm.org/viewvc/llvm-project?rev=134247&view=rev
Log:
Fix off-by-one error.

(low two bits always zero, so off by one bit of encoded value).

Modified:
    llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp

Modified: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp?rev=134247&r1=134246&r2=134247&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp (original)
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp Fri Jul  1 14:07:09 2011
@@ -491,7 +491,7 @@
     // The immediate must be in range, the destination register must be a low
     // reg, the predicate must be "always" and the condition flags must not
     // be being set.
-    if (Imm & 3 || Imm > 1024)
+    if (Imm & 3 || Imm > 1020)
       return false;
     if (!isARMLowRegister(MI->getOperand(0).getReg()))
       return false;



From mttjwl at gmail.com  Fri Jul  1 15:17:52 2011
From: mttjwl at gmail.com (Matthew Wala)
Date: Fri, 01 Jul 2011 20:17:52 -0000
Subject: [llvm-commits] [poolalloc] r134253 -
	/poolalloc/trunk/lib/DSA/StdLibPass.cpp
Message-ID: <20110701201752.443BF2A6C12C@llvm.org>

Author: wala1
Date: Fri Jul  1 15:17:52 2011
New Revision: 134253

URL: http://llvm.org/viewvc/llvm-project?rev=134253&view=rev
Log:
Allow DSA to recognize more functions:
  1) sc.fscallinfo_debug
  2) scanf() family
  3) __printf_chk() family

Modified:
    poolalloc/trunk/lib/DSA/StdLibPass.cpp

Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=134253&r1=134252&r2=134253&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original)
+++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Fri Jul  1 15:17:52 2011
@@ -301,6 +301,7 @@
   // format string intrinsics and functions
   {"sc.fsparameter",  {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"sc.fscallinfo",   {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"sc.fscallinfo_debug",{NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"pool_printf",     {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"pool_fprintf",    {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"pool_sprintf",    {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
@@ -310,6 +311,13 @@
   {"pool_warn",       {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"pool_warnx",      {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   {"pool_syslog",     {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_scanf",      {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_fscanf",     {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_sscanf",     {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool___printf_chk",   {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool___fprintf_chk",  {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool___sprintf_chk",  {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool___snprintf_chk", {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   
   // Type Checks
   {"trackArgvType",        {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},



From mttjwl at gmail.com  Fri Jul  1 15:21:50 2011
From: mttjwl at gmail.com (Matthew Wala)
Date: Fri, 01 Jul 2011 20:21:50 -0000
Subject: [llvm-commits] [poolalloc] r134254 -
	/poolalloc/trunk/lib/DSA/StdLibPass.cpp
Message-ID: <20110701202150.563EA2A6C12C@llvm.org>

Author: wala1
Date: Fri Jul  1 15:21:50 2011
New Revision: 134254

URL: http://llvm.org/viewvc/llvm-project?rev=134254&view=rev
Log:
Change NRET_YARGS to NRET_NARGS for all format string related functions
in StdLibPass.

Modified:
    poolalloc/trunk/lib/DSA/StdLibPass.cpp

Modified: poolalloc/trunk/lib/DSA/StdLibPass.cpp
URL: http://llvm.org/viewvc/llvm-project/poolalloc/trunk/lib/DSA/StdLibPass.cpp?rev=134254&r1=134253&r2=134254&view=diff
==============================================================================
--- poolalloc/trunk/lib/DSA/StdLibPass.cpp (original)
+++ poolalloc/trunk/lib/DSA/StdLibPass.cpp Fri Jul  1 15:21:50 2011
@@ -300,24 +300,24 @@
 
   // format string intrinsics and functions
   {"sc.fsparameter",  {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.fscallinfo",   {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"sc.fscallinfo_debug",{NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_printf",     {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_fprintf",    {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_sprintf",    {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_snprintf",   {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_err",        {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_errx",       {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_warn",       {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_warnx",      {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_syslog",     {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_scanf",      {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_fscanf",     {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool_sscanf",     {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool___printf_chk",   {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool___fprintf_chk",  {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool___sprintf_chk",  {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
-  {"pool___snprintf_chk", {NRET_YARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"sc.fscallinfo",   {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"sc.fscallinfo_debug",{NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_printf",     {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_fprintf",    {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_sprintf",    {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_snprintf",   {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_err",        {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_errx",       {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_warn",       {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_warnx",      {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_syslog",     {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_scanf",      {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_fscanf",     {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool_sscanf",     {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool___printf_chk",   {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool___fprintf_chk",  {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool___sprintf_chk",  {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
+  {"pool___snprintf_chk", {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS, false}},
   
   // Type Checks
   {"trackArgvType",        {NRET_NARGS, NRET_NARGS, NRET_NARGS, NRET_NARGS,   false}},



From gkistanova at gmail.com  Fri Jul  1 15:39:36 2011
From: gkistanova at gmail.com (Galina Kistanova)
Date: Fri, 01 Jul 2011 20:39:36 -0000
Subject: [llvm-commits] [zorg] r134256 - in
 /zorg/trunk/buildbot/osuosl/master/config: builders.py slaves.py
Message-ID: <20110701203936.7FB272A6C12C@llvm.org>

Author: gkistanova
Date: Fri Jul  1 15:39:36 2011
New Revision: 134256

URL: http://llvm.org/viewvc/llvm-project?rev=134256&view=rev
Log:
Added new clang builder freebsd X86_64.

Modified:
    zorg/trunk/buildbot/osuosl/master/config/builders.py
    zorg/trunk/buildbot/osuosl/master/config/slaves.py

Modified: zorg/trunk/buildbot/osuosl/master/config/builders.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/builders.py?rev=134256&r1=134255&r2=134256&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/builders.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/builders.py Fri Jul  1 15:39:36 2011
@@ -279,6 +279,13 @@
                                            '--enable-targets=arm,cbe',
                                            '--enable-optimized']),
          'category' : 'clang'},
+
+        {'name': "clang-X86_64-freebsd",
+         'slavenames':["kistanova7"],
+         'builddir':"clang-X86_64-freebsd",
+         'factory': NightlytestBuilder.getFastNightlyTestBuildFactory(triple='x86_64-unknown-freebsd8.2',
+                                                                       stage1_config='Release+Asserts',
+                                                                       test=True),
 		 
         # Clang cross builders.
         {'name': "clang-x86_64-darwin10-self-mingw32",

Modified: zorg/trunk/buildbot/osuosl/master/config/slaves.py
URL: http://llvm.org/viewvc/llvm-project/zorg/trunk/buildbot/osuosl/master/config/slaves.py?rev=134256&r1=134255&r2=134256&view=diff
==============================================================================
--- zorg/trunk/buildbot/osuosl/master/config/slaves.py (original)
+++ zorg/trunk/buildbot/osuosl/master/config/slaves.py Fri Jul  1 15:39:36 2011
@@ -58,10 +58,12 @@
         create_slave("kistanova5", properties={'jobs' : 1}, max_builds=1),
 
         # Ubuntu pandaboard cortex-a9
-        create_slave("kistanova6", properties={'jobs' : 2}, max_builds=1),        
+        create_slave("kistanova6", properties={'jobs' : 2}, max_builds=1), 
+
+        # FreeBSD 8.2  X86_64
+        create_slave("kistanova7", properties={'jobs' : 2}, max_builds=1),        
 
         # Dummy entries for future use.
-        create_slave("kistanova7", properties={'jobs' : 1}, max_builds=1),
         create_slave("kistanova8", properties={'jobs' : 1}, max_builds=1),
 
         # Quad Core x86_64, Solaris / AurorAUX



From evan.cheng at apple.com  Fri Jul  1 15:45:01 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 01 Jul 2011 20:45:01 -0000
Subject: [llvm-commits] [llvm] r134257 - in /llvm/trunk: include/llvm/MC/
 include/llvm/Target/ lib/MC/ lib/Target/ARM/ lib/Target/Alpha/
 lib/Target/Blackfin/ lib/Target/CellSPU/ lib/Target/MBlaze/
 lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/ lib/Target/PowerPC/
 lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/ lib/Target/XCore/
 utils/TableGen/
Message-ID: <20110701204501.E0C742A6C12C@llvm.org>

Author: evancheng
Date: Fri Jul  1 15:45:01 2011
New Revision: 134257

URL: http://llvm.org/viewvc/llvm-project?rev=134257&view=rev
Log:
- Added MCSubtargetInfo to capture subtarget features and scheduling
  itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
  and hide more details from targets.

Added:
    llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
    llvm/trunk/lib/MC/MCSubtargetInfo.cpp
Modified:
    llvm/trunk/include/llvm/Target/TargetSubtarget.h
    llvm/trunk/lib/MC/CMakeLists.txt
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
    llvm/trunk/lib/Target/ARM/ARMSubtarget.h
    llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp
    llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h
    llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp
    llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h
    llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp
    llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h
    llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h
    llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp
    llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h
    llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
    llvm/trunk/lib/Target/Mips/MipsSubtarget.h
    llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp
    llvm/trunk/lib/Target/PTX/PTXSubtarget.h
    llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
    llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
    llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
    llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
    llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
    llvm/trunk/lib/Target/X86/X86Subtarget.h
    llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp
    llvm/trunk/lib/Target/XCore/XCoreSubtarget.h
    llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
    llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
    llvm/trunk/utils/TableGen/SubtargetEmitter.h

Added: llvm/trunk/include/llvm/MC/MCSubtargetInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/MC/MCSubtargetInfo.h?rev=134257&view=auto
==============================================================================
--- llvm/trunk/include/llvm/MC/MCSubtargetInfo.h (added)
+++ llvm/trunk/include/llvm/MC/MCSubtargetInfo.h Fri Jul  1 15:45:01 2011
@@ -0,0 +1,61 @@
+//==-- llvm/MC/MCSubtargetInfo.h - Subtarget Information ---------*- C++ -*-==//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the subtarget options of a Target machine.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_MC_MCSUBTARGET_H
+#define LLVM_MC_MCSUBTARGET_H
+
+#include "llvm/MC/SubtargetFeature.h"
+#include "llvm/MC/MCInstrItineraries.h"
+
+namespace llvm {
+
+class StringRef;
+
+//===----------------------------------------------------------------------===//
+///
+/// MCSubtargetInfo - Generic base class for all target subtargets.
+///
+class MCSubtargetInfo {
+  const SubtargetFeatureKV *ProcFeatures;  // Processor feature list
+  const SubtargetFeatureKV *ProcDesc;  // Processor descriptions
+  const SubtargetInfoKV *ProcItins;    // Scheduling itineraries
+  const InstrStage *Stages;            // Instruction stages
+  const unsigned *OperandCycles;       // Operand cycles
+  const unsigned *ForwardingPathes;    // Forwarding pathes
+  unsigned NumFeatures;                // Number of processor features
+  unsigned NumProcs;                   // Number of processors
+    
+public:
+  void InitMCSubtargetInfo(const SubtargetFeatureKV *PF,
+                           const SubtargetFeatureKV *PD,
+                           const SubtargetInfoKV *PI, const InstrStage *IS,
+                           const unsigned *OC, const unsigned *FP,
+                           unsigned NF, unsigned NP) {
+    ProcFeatures = PF;
+    ProcDesc = PD;
+    ProcItins = PI;
+    Stages = IS;
+    OperandCycles = OC;
+    ForwardingPathes = FP;
+    NumFeatures = NF;
+    NumProcs = NP;
+  }
+
+  /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
+  ///
+  InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
+};
+
+} // End llvm namespace
+
+#endif

Modified: llvm/trunk/include/llvm/Target/TargetSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSubtarget.h (original)
+++ llvm/trunk/include/llvm/Target/TargetSubtarget.h Fri Jul  1 15:45:01 2011
@@ -14,6 +14,7 @@
 #ifndef LLVM_TARGET_TARGETSUBTARGET_H
 #define LLVM_TARGET_TARGETSUBTARGET_H
 
+#include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
@@ -29,7 +30,7 @@
 /// Target-specific options that control code generation and printing should
 /// be exposed through a TargetSubtarget-derived class.
 ///
-class TargetSubtarget {
+class TargetSubtarget : public MCSubtargetInfo {
   TargetSubtarget(const TargetSubtarget&);   // DO NOT IMPLEMENT
   void operator=(const TargetSubtarget&);  // DO NOT IMPLEMENT
 protected: // Can only create subclasses...

Modified: llvm/trunk/lib/MC/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/CMakeLists.txt?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/MC/CMakeLists.txt (original)
+++ llvm/trunk/lib/MC/CMakeLists.txt Fri Jul  1 15:45:01 2011
@@ -28,6 +28,7 @@
   MCSectionELF.cpp
   MCSectionMachO.cpp
   MCStreamer.cpp
+  MCSubtargetInfo.cpp
   MCSymbol.cpp
   MCValue.cpp
   MCWin64EH.cpp

Added: llvm/trunk/lib/MC/MCSubtargetInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/MC/MCSubtargetInfo.cpp?rev=134257&view=auto
==============================================================================
--- llvm/trunk/lib/MC/MCSubtargetInfo.cpp (added)
+++ llvm/trunk/lib/MC/MCSubtargetInfo.cpp Fri Jul  1 15:45:01 2011
@@ -0,0 +1,44 @@
+//===-- MCSubtargetInfo.cpp - Subtarget Information -----------------------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/MC/MCInstrItineraries.h"
+#include "llvm/MC/SubtargetFeature.h"
+#include "llvm/ADT/StringRef.h"
+#include "llvm/Support/raw_ostream.h"
+#include 
+
+using namespace llvm;
+
+InstrItineraryData
+MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
+  assert(ProcItins && "Instruction itineraries information not available!");
+
+#ifndef NDEBUG
+  for (size_t i = 1; i < NumProcs; i++) {
+    assert(strcmp(ProcItins[i - 1].Key, ProcItins[i].Key) < 0 &&
+           "Itineraries table is not sorted");
+  }
+#endif
+
+  // Find entry
+  SubtargetInfoKV KV;
+  KV.Key = CPU.data();
+  const SubtargetInfoKV *Found =
+    std::lower_bound(ProcItins, ProcItins+NumProcs, KV);
+  if (Found == ProcItins+NumProcs || StringRef(Found->Key) != CPU) {
+    errs() << "'" << CPU
+           << "' is not a recognized processor for this target"
+           << " (ignoring processor)\n";
+    return InstrItineraryData();
+  }
+
+  return InstrItineraryData(Stages, OperandCycles, ForwardingPathes,
+                            (InstrItinerary *)Found->Value);
+}

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Fri Jul  1 15:45:01 2011
@@ -12,11 +12,17 @@
 //===----------------------------------------------------------------------===//
 
 #include "ARMSubtarget.h"
-#include "ARMGenSubtarget.inc"
 #include "ARMBaseRegisterInfo.h"
 #include "llvm/GlobalValue.h"
+#include "llvm/Target/TargetSubtarget.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/ADT/SmallVector.h"
+
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
+#include "ARMGenSubtarget.inc"
+
 using namespace llvm;
 
 static cl::opt
@@ -32,7 +38,8 @@
 
 ARMSubtarget::ARMSubtarget(const std::string &TT, const std::string &CPU,
                            const std::string &FS, bool isT)
-  : ARMArchVersion(V4)
+  : ARMGenSubtargetInfo()
+  , ARMArchVersion(V4)
   , ARMProcFamily(Others)
   , ARMFPUType(None)
   , UseNEONForSinglePrecisionFP(false)
@@ -130,6 +137,9 @@
     FSWithArch = FSWithArch + "," + FS;
   ParseSubtargetFeatures(FSWithArch, CPUString);
 
+  // Initialize scheduling itinerary for the specified CPU.
+  InstrItins = getInstrItineraryForCPU(CPUString);
+
   // After parsing Itineraries, set ItinData.IssueWidth.
   computeIssueWidth();
 

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Fri Jul  1 15:45:01 2011
@@ -19,10 +19,13 @@
 #include "llvm/ADT/Triple.h"
 #include 
 
+#define GET_SUBTARGETINFO_HEADER
+#include "ARMGenSubtarget.inc"
+
 namespace llvm {
 class GlobalValue;
 
-class ARMSubtarget : public TargetSubtarget {
+class ARMSubtarget : public ARMGenSubtargetInfo {
 protected:
   enum ARMArchEnum {
     V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M

Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Fri Jul  1 15:45:01 2011
@@ -14,15 +14,24 @@
 #include "AlphaSubtarget.h"
 #include "Alpha.h"
 #include "AlphaGenSubtarget.inc"
+
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
+#include "AlphaGenSubtarget.inc"
+
 using namespace llvm;
 
 AlphaSubtarget::AlphaSubtarget(const std::string &TT, const std::string &CPU,
                                const std::string &FS)
-  : HasCT(false) {
+  : AlphaGenSubtargetInfo(), HasCT(false) {
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = "generic";
 
   // Parse features string.
   ParseSubtargetFeatures(FS, CPUName);
+
+  // Initialize scheduling itinerary for the specified CPU.
+  InstrItins = getInstrItineraryForCPU(CPUName);
 }

Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h Fri Jul  1 15:45:01 2011
@@ -18,9 +18,12 @@
 #include "llvm/MC/MCInstrItineraries.h"
 #include 
 
+#define GET_SUBTARGETINFO_HEADER
+#include "AlphaGenSubtarget.inc"
+
 namespace llvm {
 
-class AlphaSubtarget : public TargetSubtarget {
+class AlphaSubtarget : public AlphaGenSubtargetInfo {
 protected:
 
   bool HasCT;

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Fri Jul  1 15:45:01 2011
@@ -12,6 +12,10 @@
 //===----------------------------------------------------------------------===//
 
 #include "BlackfinSubtarget.h"
+
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
 #include "BlackfinGenSubtarget.inc"
 
 using namespace llvm;
@@ -19,7 +23,7 @@
 BlackfinSubtarget::BlackfinSubtarget(const std::string &TT,
                                      const std::string &CPU,
                                      const std::string &FS)
-  : sdram(false),
+  : BlackfinGenSubtargetInfo(), sdram(false),
     icplb(false),
     wa_mi_shift(false),
     wa_csync(false),

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h Fri Jul  1 15:45:01 2011
@@ -17,9 +17,12 @@
 #include "llvm/Target/TargetSubtarget.h"
 #include 
 
+#define GET_SUBTARGETINFO_HEADER
+#include "BlackfinGenSubtarget.inc"
+
 namespace llvm {
 
-  class BlackfinSubtarget : public TargetSubtarget {
+  class BlackfinSubtarget : public BlackfinGenSubtargetInfo {
     bool sdram;
     bool icplb;
     bool wa_mi_shift;

Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Fri Jul  1 15:45:01 2011
@@ -13,14 +13,19 @@
 
 #include "SPUSubtarget.h"
 #include "SPU.h"
-#include "SPUGenSubtarget.inc"
 #include "llvm/ADT/SmallVector.h"
 #include "SPURegisterInfo.h"
 
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
+#include "SPUGenSubtarget.inc"
+
 using namespace llvm;
 
 SPUSubtarget::SPUSubtarget(const std::string &TT, const std::string &CPU,
                            const std::string &FS) :
+  SPUGenSubtargetInfo(),
   StackAlignment(16),
   ProcDirective(SPU::DEFAULT_PROC),
   UseLargeMem(false)
@@ -31,6 +36,9 @@
 
   // Parse features string.
   ParseSubtargetFeatures(FS, default_cpu);
+
+  // Initialize scheduling itinerary for the specified CPU.
+  InstrItins = getInstrItineraryForCPU(default_cpu);
 }
 
 /// SetJITMode - This is called to inform the subtarget info that we are

Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h Fri Jul  1 15:45:01 2011
@@ -18,6 +18,9 @@
 #include "llvm/MC/MCInstrItineraries.h"
 #include 
 
+#define GET_SUBTARGETINFO_HEADER
+#include "SPUGenSubtarget.inc"
+
 namespace llvm {
   class GlobalValue;
 
@@ -28,7 +31,7 @@
     };
   }
     
-  class SPUSubtarget : public TargetSubtarget {
+  class SPUSubtarget : public SPUGenSubtargetInfo {
   protected:
     /// stackAlignment - The minimum alignment known to hold of the stack frame
     /// on entry to the function and which must be maintained by every function.

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Fri Jul  1 15:45:01 2011
@@ -14,13 +14,19 @@
 #include "MBlazeSubtarget.h"
 #include "MBlaze.h"
 #include "MBlazeRegisterInfo.h"
-#include "MBlazeGenSubtarget.inc"
 #include "llvm/Support/CommandLine.h"
+
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
+#include "MBlazeGenSubtarget.inc"
+
 using namespace llvm;
 
 MBlazeSubtarget::MBlazeSubtarget(const std::string &TT,
                                  const std::string &CPU,
                                  const std::string &FS):
+  MBlazeGenSubtargetInfo(),
   HasBarrel(false), HasDiv(false), HasMul(false), HasPatCmp(false),
   HasFPU(false), HasMul64(false), HasSqrt(false)
 {
@@ -35,6 +41,9 @@
   HasItin = CPUName != "mblaze";
   DEBUG(dbgs() << "CPU " << CPUName << "(" << HasItin << ")\n");
 
+  // Initialize scheduling itinerary for the specified CPU.
+  InstrItins = getInstrItineraryForCPU(CPUName);
+
   // Compute the issue width of the MBlaze itineraries
   computeIssueWidth();
 }

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h Fri Jul  1 15:45:01 2011
@@ -18,9 +18,12 @@
 #include "llvm/MC/MCInstrItineraries.h"
 #include 
 
+#define GET_SUBTARGETINFO_HEADER
+#include "MBlazeGenSubtarget.inc"
+
 namespace llvm {
 
-class MBlazeSubtarget : public TargetSubtarget {
+class MBlazeSubtarget : public MBlazeGenSubtargetInfo {
 
 protected:
   bool HasBarrel;

Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Fri Jul  1 15:45:01 2011
@@ -13,6 +13,10 @@
 
 #include "MSP430Subtarget.h"
 #include "MSP430.h"
+
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
 #include "MSP430GenSubtarget.inc"
 
 using namespace llvm;

Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h Fri Jul  1 15:45:01 2011
@@ -16,11 +16,14 @@
 
 #include "llvm/Target/TargetSubtarget.h"
 
+#define GET_SUBTARGETINFO_HEADER
+#include "MSP430GenSubtarget.inc"
+
 #include 
 
 namespace llvm {
 
-class MSP430Subtarget : public TargetSubtarget {
+class MSP430Subtarget : public MSP430GenSubtargetInfo {
   bool ExtendedInsts;
 public:
   /// This constructor initializes the data members to match that

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Fri Jul  1 15:45:01 2011
@@ -13,11 +13,17 @@
 
 #include "MipsSubtarget.h"
 #include "Mips.h"
+
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
 #include "MipsGenSubtarget.inc"
+
 using namespace llvm;
 
 MipsSubtarget::MipsSubtarget(const std::string &TT, const std::string &CPU,
                              const std::string &FS, bool little) :
+  MipsGenSubtargetInfo(),
   MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false),
   IsFP64bit(false), IsGP64bit(false), HasVFPU(false), IsLinux(true),
   HasSEInReg(false), HasCondMov(false), HasMulDivAdd(false), HasMinMax(false),
@@ -31,6 +37,9 @@
   // Parse features string.
   ParseSubtargetFeatures(FS, CPUName);
 
+  // Initialize scheduling itinerary for the specified CPU.
+  InstrItins = getInstrItineraryForCPU(CPUName);
+
   // Is the target system Linux ?
   if (TT.find("linux") == std::string::npos)
     IsLinux = false;

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Fri Jul  1 15:45:01 2011
@@ -18,9 +18,12 @@
 #include "llvm/MC/MCInstrItineraries.h"
 #include 
 
+#define GET_SUBTARGETINFO_HEADER
+#include "MipsGenSubtarget.inc"
+
 namespace llvm {
 
-class MipsSubtarget : public TargetSubtarget {
+class MipsSubtarget : public MipsGenSubtargetInfo {
 
 public:
   enum MipsABIEnum {

Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Fri Jul  1 15:45:01 2011
@@ -14,11 +14,17 @@
 #include "PTXSubtarget.h"
 #include "llvm/Support/ErrorHandling.h"
 
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
+#include "PTXGenSubtarget.inc"
+
 using namespace llvm;
 
 PTXSubtarget::PTXSubtarget(const std::string &TT, const std::string &CPU,
                            const std::string &FS, bool is64Bit)
-  : PTXTarget(PTX_COMPUTE_1_0),
+  : PTXGenSubtargetInfo(),
+    PTXTarget(PTX_COMPUTE_1_0),
     PTXVersion(PTX_VERSION_2_0),
     SupportsDouble(false),
     SupportsFMA(true),

Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXSubtarget.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXSubtarget.h Fri Jul  1 15:45:01 2011
@@ -16,8 +16,11 @@
 
 #include "llvm/Target/TargetSubtarget.h"
 
+#define GET_SUBTARGETINFO_HEADER
+#include "PTXGenSubtarget.inc"
+
 namespace llvm {
-  class PTXSubtarget : public TargetSubtarget {
+  class PTXSubtarget : public PTXGenSubtargetInfo {
     public:
 
       /**

Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Fri Jul  1 15:45:01 2011
@@ -15,8 +15,13 @@
 #include "PPC.h"
 #include "llvm/GlobalValue.h"
 #include "llvm/Target/TargetMachine.h"
-#include "PPCGenSubtarget.inc"
 #include 
+
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
+#include "PPCGenSubtarget.inc"
+
 using namespace llvm;
 
 #if defined(__APPLE__)
@@ -59,7 +64,8 @@
 
 PPCSubtarget::PPCSubtarget(const std::string &TT, const std::string &CPU,
                            const std::string &FS, bool is64Bit)
-  : StackAlignment(16)
+  : PPCGenSubtargetInfo()
+  , StackAlignment(16)
   , DarwinDirective(PPC::DIR_NONE)
   , IsGigaProcessor(false)
   , Has64BitSupport(false)
@@ -84,6 +90,9 @@
   // Parse features string.
   ParseSubtargetFeatures(FS, CPUName);
 
+  // Initialize scheduling itinerary for the specified CPU.
+  InstrItins = getInstrItineraryForCPU(CPUName);
+
   // If we are generating code for ppc64, verify that options make sense.
   if (is64Bit) {
     Has64BitSupport = true;

Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Fri Jul  1 15:45:01 2011
@@ -19,6 +19,9 @@
 #include "llvm/ADT/Triple.h"
 #include 
 
+#define GET_SUBTARGETINFO_HEADER
+#include "PPCGenSubtarget.inc"
+
 // GCC #defines PPC on Linux but we use it as our namespace name
 #undef PPC
 
@@ -42,7 +45,7 @@
 class GlobalValue;
 class TargetMachine;
   
-class PPCSubtarget : public TargetSubtarget {
+class PPCSubtarget : public PPCGenSubtargetInfo {
 protected:
   /// stackAlignment - The minimum alignment known to hold of the stack frame on
   /// entry to the function and which must be maintained by every function.

Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Fri Jul  1 15:45:01 2011
@@ -12,11 +12,17 @@
 //===----------------------------------------------------------------------===//
 
 #include "SparcSubtarget.h"
+
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
 #include "SparcGenSubtarget.inc"
+
 using namespace llvm;
 
 SparcSubtarget::SparcSubtarget(const std::string &TT, const std::string &CPU,
                                const std::string &FS,  bool is64Bit) :
+  SparcGenSubtargetInfo(),
   IsV9(false),
   V8DeprecatedInsts(false),
   IsVIS(false),

Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.h Fri Jul  1 15:45:01 2011
@@ -17,9 +17,12 @@
 #include "llvm/Target/TargetSubtarget.h"
 #include 
 
+#define GET_SUBTARGETINFO_HEADER
+#include "SparcGenSubtarget.inc"
+
 namespace llvm {
 
-class SparcSubtarget : public TargetSubtarget {
+class SparcSubtarget : public SparcGenSubtargetInfo {
   bool IsV9;
   bool V8DeprecatedInsts;
   bool IsVIS;

Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Fri Jul  1 15:45:01 2011
@@ -13,16 +13,20 @@
 
 #include "SystemZSubtarget.h"
 #include "SystemZ.h"
-#include "SystemZGenSubtarget.inc"
 #include "llvm/GlobalValue.h"
 #include "llvm/Target/TargetMachine.h"
 
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
+#include "SystemZGenSubtarget.inc"
+
 using namespace llvm;
 
 SystemZSubtarget::SystemZSubtarget(const std::string &TT, 
                                    const std::string &CPU,
                                    const std::string &FS):
-  HasZ10Insts(false) {
+  SystemZGenSubtargetInfo(), HasZ10Insts(false) {
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = "z9";

Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h Fri Jul  1 15:45:01 2011
@@ -15,14 +15,16 @@
 #define LLVM_TARGET_SystemZ_SUBTARGET_H
 
 #include "llvm/Target/TargetSubtarget.h"
-
 #include 
 
+#define GET_SUBTARGETINFO_HEADER
+#include "SystemZGenSubtarget.inc"
+
 namespace llvm {
 class GlobalValue;
 class TargetMachine;
 
-class SystemZSubtarget : public TargetSubtarget {
+class SystemZSubtarget : public SystemZGenSubtargetInfo {
   bool HasZ10Insts;
 public:
   /// This constructor initializes the data members to match that

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri Jul  1 15:45:01 2011
@@ -14,13 +14,18 @@
 #define DEBUG_TYPE "subtarget"
 #include "X86Subtarget.h"
 #include "X86InstrInfo.h"
-#include "X86GenSubtarget.inc"
 #include "llvm/GlobalValue.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Support/Host.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/ADT/SmallVector.h"
+
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
+#include "X86GenSubtarget.inc"
+
 using namespace llvm;
 
 #if defined(_MSC_VER)
@@ -287,7 +292,8 @@
 X86Subtarget::X86Subtarget(const std::string &TT, const std::string &CPU,
                            const std::string &FS, 
                            bool is64Bit, unsigned StackAlignOverride)
-  : PICStyle(PICStyles::None)
+  : X86GenSubtargetInfo()
+  , PICStyle(PICStyles::None)
   , X86SSELevel(NoMMXSSE)
   , X863DNowLevel(NoThreeDNow)
   , HasCMov(false)

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Fri Jul  1 15:45:01 2011
@@ -19,6 +19,9 @@
 #include "llvm/CallingConv.h"
 #include 
 
+#define GET_SUBTARGETINFO_HEADER
+#include "X86GenSubtarget.inc"
+
 namespace llvm {
 class GlobalValue;
 class TargetMachine;
@@ -35,7 +38,7 @@
 };
 }
 
-class X86Subtarget : public TargetSubtarget {
+class X86Subtarget : public X86GenSubtargetInfo {
 protected:
   enum X86SSEEnum {
     NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42

Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Fri Jul  1 15:45:01 2011
@@ -13,9 +13,16 @@
 
 #include "XCoreSubtarget.h"
 #include "XCore.h"
+
+#define GET_SUBTARGETINFO_CTOR
+#define GET_SUBTARGETINFO_MC_DESC
+#define GET_SUBTARGETINFO_TARGET_DESC
+#include "XCoreGenSubtarget.inc"
+
 using namespace llvm;
 
 XCoreSubtarget::XCoreSubtarget(const std::string &TT,
                                const std::string &CPU, const std::string &FS)
+  : XCoreGenSubtargetInfo()
 {
 }

Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreSubtarget.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.h Fri Jul  1 15:45:01 2011
@@ -16,12 +16,14 @@
 
 #include "llvm/Target/TargetSubtarget.h"
 #include "llvm/Target/TargetMachine.h"
-
 #include 
 
+#define GET_SUBTARGETINFO_HEADER
+#include "XCoreGenSubtarget.inc"
+
 namespace llvm {
 
-class XCoreSubtarget : public TargetSubtarget {
+class XCoreSubtarget : public XCoreGenSubtargetInfo {
 
 public:
   /// This constructor initializes the data members to match that

Modified: llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/InstrInfoEmitter.cpp Fri Jul  1 15:45:01 2011
@@ -223,7 +223,7 @@
   OS << "#undef GET_INSTRINFO_HEADER\n";
 
   std::string ClassName = TargetName + "GenInstrInfo";
-  OS << "namespace llvm {\n\n";
+  OS << "namespace llvm {\n";
   OS << "struct " << ClassName << " : public TargetInstrInfoImpl {\n"
      << "  explicit " << ClassName << "(int SO = -1, int DO = -1);\n"
      << "};\n";
@@ -234,7 +234,7 @@
   OS << "\n#ifdef GET_INSTRINFO_CTOR\n";
   OS << "#undef GET_INSTRINFO_CTOR\n";
 
-  OS << "namespace llvm {\n\n";
+  OS << "namespace llvm {\n";
   OS << ClassName << "::" << ClassName << "(int SO, int DO)\n"
      << "  : TargetInstrInfoImpl(SO, DO) {\n"
      << "  InitMCInstrInfo(" << TargetName << "Insts, "

Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Fri Jul  1 15:45:01 2011
@@ -29,16 +29,20 @@
   std::vector DefList = Records.getAllDerivedDefinitions(ClassName);
   std::sort(DefList.begin(), DefList.end(), LessRecord());
 
-  // Open enumeration
-  OS << "enum {\n";
-
-  // For each record
   unsigned N = DefList.size();
+  if (N == 0)
+    return;
   if (N > 64) {
     errs() << "Too many (> 64) subtarget features!\n";
     exit(1);
   }
 
+  OS << "namespace " << Target << " {\n";
+
+  // Open enumeration
+  OS << "enum {\n";
+
+  // For each record
   for (unsigned i = 0; i < N;) {
     // Next record
     Record *Def = DefList[i];
@@ -57,23 +61,31 @@
 
   // Close enumeration
   OS << "};\n";
+
+  OS << "}\n";
 }
 
 //
 // FeatureKeyValues - Emit data of all the subtarget features.  Used by the
 // command line.
 //
-void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
+unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
   // Gather and sort all the features
   std::vector FeatureList =
                            Records.getAllDerivedDefinitions("SubtargetFeature");
+
+  if (FeatureList.empty())
+    return 0;
+
   std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
 
   // Begin feature table
   OS << "// Sorted (by key) array of values for CPU features.\n"
-     << "static const llvm::SubtargetFeatureKV FeatureKV[] = {\n";
+     << "static const llvm::SubtargetFeatureKV "
+     << Target << "FeatureKV[] = {\n";
 
   // For each feature
+  unsigned NumFeatures = 0;
   for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
     // Next feature
     Record *Feature = FeatureList[i];
@@ -88,7 +100,7 @@
     OS << "  { "
        << "\"" << CommandLineName << "\", "
        << "\"" << Desc << "\", "
-       << Name << ", ";
+       << Target << "::" << Name << ", ";
 
     const std::vector &ImpliesList =
       Feature->getValueAsListOfDefs("Implies");
@@ -97,12 +109,13 @@
       OS << "0ULL";
     } else {
       for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
-        OS << ImpliesList[j]->getName();
+        OS << Target << "::" << ImpliesList[j]->getName();
         if (++j < M) OS << " | ";
       }
     }
 
     OS << " }";
+    ++NumFeatures;
 
     // Depending on 'if more in the list' emit comma
     if ((i + 1) < N) OS << ",";
@@ -113,17 +126,14 @@
   // End feature table
   OS << "};\n";
 
-  // Emit size of table
-  OS<<"\nenum {\n";
-  OS<<"  FeatureKVSize = sizeof(FeatureKV)/sizeof(llvm::SubtargetFeatureKV)\n";
-  OS<<"};\n";
+  return NumFeatures;
 }
 
 //
 // CPUKeyValues - Emit data of all the subtarget processors.  Used by command
 // line.
 //
-void SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
+unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
   // Gather and sort processor information
   std::vector ProcessorList =
                           Records.getAllDerivedDefinitions("Processor");
@@ -131,7 +141,8 @@
 
   // Begin processor table
   OS << "// Sorted (by key) array of values for CPU subtype.\n"
-     << "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n";
+     << "static const llvm::SubtargetFeatureKV "
+     << Target << "SubTypeKV[] = {\n";
 
   // For each processor
   for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
@@ -151,7 +162,7 @@
       OS << "0ULL";
     } else {
       for (unsigned j = 0, M = FeatureList.size(); j < M;) {
-        OS << FeatureList[j]->getName();
+        OS << Target << "::" << FeatureList[j]->getName();
         if (++j < M) OS << " | ";
       }
     }
@@ -168,10 +179,7 @@
   // End processor table
   OS << "};\n";
 
-  // Emit size of table
-  OS<<"\nenum {\n";
-  OS<<"  SubTypeKVSize = sizeof(SubTypeKV)/sizeof(llvm::SubtargetFeatureKV)\n";
-  OS<<"};\n";
+  return ProcessorList.size();
 }
 
 //
@@ -192,11 +200,6 @@
     ItinClassesMap[ItinClass->getName()] = i;
   }
 
-  // Emit size of table
-  OS<<"\nenum {\n";
-  OS<<"  ItinClassesSize = " << N << "\n";
-  OS<<"};\n";
-
   // Return itinerary class count
   return N;
 }
@@ -336,15 +339,18 @@
   }
 
   // Begin stages table
-  std::string StageTable = "\nstatic const llvm::InstrStage Stages[] = {\n";
+  std::string StageTable = "\nstatic const llvm::InstrStage " + Target +
+    "Stages[] = {\n";
   StageTable += "  { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
 
   // Begin operand cycle table
-  std::string OperandCycleTable = "static const unsigned OperandCycles[] = {\n";
+  std::string OperandCycleTable = "static const unsigned " + Target +
+    "OperandCycles[] = {\n";
   OperandCycleTable += "  0, // No itinerary\n";
 
   // Begin pipeline bypass table
-  std::string BypassTable = "static const unsigned ForwardingPathes[] = {\n";
+  std::string BypassTable = "static const unsigned " + Target +
+    "ForwardingPathes[] = {\n";
   BypassTable += "  0, // No itinerary\n";
 
   unsigned StageCount = 1, OperandCycleCount = 1;
@@ -457,12 +463,6 @@
   OS << StageTable;
   OS << OperandCycleTable;
   OS << BypassTable;
-
-  // Emit size of tables
-  OS<<"\nenum {\n";
-  OS<<"  StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage),\n";
-  OS<<"  OperandCyclesSize = sizeof(OperandCycles)/sizeof(unsigned)\n";
-  OS<<"};\n";
 }
 
 //
@@ -533,7 +533,8 @@
   // Begin processor table
   OS << "\n";
   OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
-     << "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n";
+     << "static const llvm::SubtargetInfoKV "
+     << Target << "ProcItinKV[] = {\n";
 
   // For each processor
   for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
@@ -559,12 +560,6 @@
 
   // End processor table
   OS << "};\n";
-
-  // Emit size of table
-  OS<<"\nenum {\n";
-  OS<<"  ProcItinKVSize = sizeof(ProcItinKV)/"
-                            "sizeof(llvm::SubtargetInfoKV)\n";
-  OS<<"};\n";
 }
 
 //
@@ -599,7 +594,9 @@
 // ParseFeaturesFunction - Produces a subtarget specific function for parsing
 // the subtarget features string.
 //
-void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) {
+void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
+                                             unsigned NumFeatures,
+                                             unsigned NumProcs) {
   std::vector Features =
                        Records.getAllDerivedDefinitions("SubtargetFeature");
   std::sort(Features.begin(), Features.end(), LessRecord());
@@ -611,11 +608,18 @@
   OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n"
      << "                                  const std::string &CPU) {\n"
      << "  DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
-     << "  DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n"
-     << "  SubtargetFeatures Features(FS);\n"
+     << "  DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n";
+
+  if (Features.empty()) {
+    OS << "}\n";
+    return;
+  }
+
+  OS << "  SubtargetFeatures Features(FS);\n"
      << "  uint64_t Bits =  Features.getFeatureBits(CPU, "
-     << "SubTypeKV, SubTypeKVSize,\n"
-     << "                                    FeatureKV, FeatureKVSize);\n";
+     << Target << "SubTypeKV, " << NumProcs << ",\n"
+     << "                                    " << Target << "FeatureKV, "
+     << NumFeatures << ");\n";
 
   for (unsigned i = 0; i < Features.size(); i++) {
     // Next record
@@ -625,20 +629,12 @@
     const std::string &Attribute = R->getValueAsString("Attribute");
 
     if (Value=="true" || Value=="false")
-      OS << "  if ((Bits & " << Instance << ") != 0) "
+      OS << "  if ((Bits & " << Target << "::" << Instance << ") != 0) "
          << Attribute << " = " << Value << ";\n";
     else
-      OS << "  if ((Bits & " << Instance << ") != 0 && " << Attribute <<
-            " < " << Value << ") " << Attribute << " = " << Value << ";\n";
-  }
-
-  if (HasItineraries) {
-    OS << "\n"
-       << "  InstrItinerary *Itinerary = (InstrItinerary *)"
-       <<              "Features.getItinerary(CPU, "
-       << "ProcItinKV, ProcItinKVSize);\n"
-       << "  InstrItins = InstrItineraryData(Stages, OperandCycles, "
-       << "ForwardingPathes, Itinerary);\n";
+      OS << "  if ((Bits & " << Target << "::" << Instance << ") != 0 && "
+         << Attribute << " < " << Value << ") "
+         << Attribute << " = " << Value << ";\n";
   }
 
   OS << "}\n";
@@ -652,22 +648,90 @@
 
   EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
 
-  OS << "#include \"llvm/Support/Debug.h\"\n";
-  OS << "#include \"llvm/Support/raw_ostream.h\"\n";
-  OS << "#include \"llvm/MC/SubtargetFeature.h\"\n";
-  OS << "#include \"llvm/MC/MCInstrItineraries.h\"\n\n";
+  OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
+  OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
 
-//  Enumeration(OS, "FuncUnit", true);
-//  OS<<"\n";
-//  Enumeration(OS, "InstrItinClass", false);
-//  OS<<"\n";
+  OS << "namespace llvm {\n";
   Enumeration(OS, "SubtargetFeature", true);
   OS<<"\n";
-  FeatureKeyValues(OS);
+  unsigned NumFeatures = FeatureKeyValues(OS);
   OS<<"\n";
-  CPUKeyValues(OS);
+  unsigned NumProcs = CPUKeyValues(OS);
   OS<<"\n";
   EmitData(OS);
   OS<<"\n";
-  ParseFeaturesFunction(OS);
+
+  // MCInstrInfo initialization routine.
+  OS << "static inline void Init" << Target
+     << "MCSubtargetInfo(MCSubtargetInfo *II) {\n";
+  OS << "  II->InitMCSubtargetInfo(";
+  if (NumFeatures)
+    OS << Target << "FeatureKV, ";
+  else
+    OS << "0, ";
+  if (NumProcs)
+    OS << Target << "SubTypeKV, ";
+  else
+    OS << "0, ";
+  if (HasItineraries) {
+    OS << Target << "ProcItinKV, "
+       << Target << "Stages, "
+       << Target << "OperandCycles, "
+       << Target << "ForwardingPathes, ";
+  } else
+    OS << "0, 0, 0, 0, ";
+  OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
+
+  OS << "} // End llvm namespace \n";
+
+  OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
+
+  OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
+  OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n";
+
+  OS << "#include \"llvm/Support/Debug.h\"\n";
+  OS << "#include \"llvm/Support/raw_ostream.h\"\n";
+  ParseFeaturesFunction(OS, NumFeatures, NumProcs);
+
+  OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
+
+  // Create a TargetSubtarget subclass to hide the MC layer initialization.
+  OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
+  OS << "#undef GET_SUBTARGETINFO_HEADER\n";
+
+  std::string ClassName = Target + "GenSubtargetInfo";
+  OS << "namespace llvm {\n";
+  OS << "struct " << ClassName << " : public TargetSubtarget {\n"
+     << "  explicit " << ClassName << "();\n"
+     << "};\n";
+  OS << "} // End llvm namespace \n";
+
+  OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
+
+  OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
+  OS << "#undef GET_SUBTARGETINFO_CTOR\n";
+
+  OS << "namespace llvm {\n";
+  OS << ClassName << "::" << ClassName << "()\n"
+     << "  : TargetSubtarget() {\n"
+     << "  InitMCSubtargetInfo(";
+  if (NumFeatures)
+    OS << Target << "FeatureKV, ";
+  else
+    OS << "0, ";
+  if (NumProcs)
+    OS << Target << "SubTypeKV, ";
+  else
+    OS << "0, ";
+  if (HasItineraries) {
+    OS << Target << "ProcItinKV, "
+       << Target << "Stages, "
+       << Target << "OperandCycles, "
+       << Target << "ForwardingPathes, ";
+  } else
+    OS << "0, 0, 0, 0, ";
+  OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
+  OS << "} // End llvm namespace \n";
+
+  OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
 }

Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.h?rev=134257&r1=134256&r2=134257&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.h (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.h Fri Jul  1 15:45:01 2011
@@ -30,8 +30,8 @@
   bool HasItineraries;
 
   void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
-  void FeatureKeyValues(raw_ostream &OS);
-  void CPUKeyValues(raw_ostream &OS);
+  unsigned FeatureKeyValues(raw_ostream &OS);
+  unsigned CPUKeyValues(raw_ostream &OS);
   unsigned CollectAllItinClasses(raw_ostream &OS,
                                  std::map &ItinClassesMap,
                                  std::vector &ItinClassList);
@@ -52,7 +52,8 @@
                          std::vector > &ProcList);
   void EmitProcessorLookup(raw_ostream &OS);
   void EmitData(raw_ostream &OS);
-  void ParseFeaturesFunction(raw_ostream &OS);
+  void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
+                             unsigned NumProcs);
 
 public:
   SubtargetEmitter(RecordKeeper &R) : Records(R), HasItineraries(false) {}



From mcrosier at apple.com  Fri Jul  1 15:53:26 2011
From: mcrosier at apple.com (Chad Rosier)
Date: Fri, 01 Jul 2011 13:53:26 -0700
Subject: [llvm-commits] [llvm] r134018 - in /llvm/trunk:
 lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86FloatingPoint.cpp
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFPStack.td
 lib/Target/X86/X86RegisterInfo.cpp lib/Target/X86/X86RegisterInfo.td
 test/CodeGen/X86/inline-asm-fpstack.ll
In-Reply-To: <17853845-62DA-48C5-96EA-474C03F49D6D@2pi.dk>
References: <20110628183228.AA6722A6C12C@llvm.org>
	
	<17853845-62DA-48C5-96EA-474C03F49D6D@2pi.dk>
Message-ID: <7BF7025C-61DC-4B9F-94A7-54D3C5A2D83D@apple.com>


On Jul 1, 2011, at 11:34 AM, Jakob Stoklund Olesen wrote:

> 
> On Jun 30, 2011, at 1:33 PM, Chad Rosier wrote:
> 
>> Hi Jakob,
>> I'm seeing a failure for one of the clang llvm-gcc tests.  Bisect brought me to this revision, which seems very relevant.
>> gcc.target/i386/pr30848.c (test for excess errors)
>> mcrosier$ /Users/mcrosier/llvm-clean/install/bin/clang /Users/mcrosier/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c    -ansi -pedantic-errors -fno-show-column -S  -o pr30848.s
>> fatal error: error in backend: Inline asm fixed outputs must be last on the x87 stack
> 
> Clang is failing correctly, but I fixed the message thusly:
> 
> clang -c /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c 
> fatal error: error in backend: Inline asm output regs must be last on the x87 stack
> 
> However, DejaGNU is still failing the test:
> 
> $ cat src/gcc.target/i386/pr30848.c 
> /* { dg-do compile } */
> 
> void foo(double d)
> {
>   __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
> }
> 
> Anyone know how to fix the test suite?
> 

I tried a few different regular expressions that I expected would work, but it still failed miserably?  Hopefully, someone with more DejaGNU experience can speak up.

 Chad

> Here is gcc-4.2:
> 
> $ gcc-4.2 -c /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c 
> /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c: In function ?foo?:
> /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c:5: error: output regs must be grouped at top of stack
> 
> /jakob
> 

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From evan.cheng at apple.com  Fri Jul  1 16:01:15 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 01 Jul 2011 21:01:15 -0000
Subject: [llvm-commits] [llvm] r134259 - in /llvm/trunk:
 include/llvm/Target/ lib/CodeGen/ lib/CodeGen/SelectionDAG/ lib/Target/
 lib/Target/ARM/ lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/
 lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/
 lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/
 lib/Target/XCore/ utils/TableGen/
Message-ID: <20110701210115.A13802A6C12C@llvm.org>

Author: evancheng
Date: Fri Jul  1 16:01:15 2011
New Revision: 134259

URL: http://llvm.org/viewvc/llvm-project?rev=134259&view=rev
Log:
Rename TargetSubtarget to TargetSubtargetInfo for consistency.

Added:
    llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h
      - copied, changed from r134257, llvm/trunk/include/llvm/Target/TargetSubtarget.h
    llvm/trunk/lib/Target/TargetSubtargetInfo.cpp
      - copied, changed from r134255, llvm/trunk/lib/Target/TargetSubtarget.cpp
Removed:
    llvm/trunk/include/llvm/Target/TargetSubtarget.h
    llvm/trunk/lib/Target/TargetSubtarget.cpp
Modified:
    llvm/trunk/include/llvm/Target/TargetMachine.h
    llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
    llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h
    llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
    llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
    llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
    llvm/trunk/lib/Target/ARM/ARMSubtarget.h
    llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp
    llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h
    llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp
    llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h
    llvm/trunk/lib/Target/CMakeLists.txt
    llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp
    llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h
    llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h
    llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp
    llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h
    llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
    llvm/trunk/lib/Target/Mips/MipsSubtarget.h
    llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp
    llvm/trunk/lib/Target/PTX/PTXSubtarget.h
    llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
    llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
    llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
    llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
    llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
    llvm/trunk/lib/Target/X86/X86Subtarget.h
    llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp
    llvm/trunk/lib/Target/XCore/XCoreSubtarget.h
    llvm/trunk/utils/TableGen/SubtargetEmitter.cpp

Modified: llvm/trunk/include/llvm/Target/TargetMachine.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetMachine.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetMachine.h (original)
+++ llvm/trunk/include/llvm/Target/TargetMachine.h Fri Jul  1 16:01:15 2011
@@ -36,7 +36,7 @@
 class TargetLowering;
 class TargetRegisterInfo;
 class TargetSelectionDAGInfo;
-class TargetSubtarget;
+class TargetSubtargetInfo;
 class formatted_raw_ostream;
 class raw_ostream;
 
@@ -94,8 +94,8 @@
   TargetMachine(const Target &);
 
   /// getSubtargetImpl - virtual method implemented by subclasses that returns
-  /// a reference to that target's TargetSubtarget-derived member variable.
-  virtual const TargetSubtarget *getSubtargetImpl() const { return 0; }
+  /// a reference to that target's TargetSubtargetInfo-derived member variable.
+  virtual const TargetSubtargetInfo *getSubtargetImpl() const { return 0; }
 
   /// TheTarget - The Target that this machine was created for.
   const Target &TheTarget;
@@ -132,7 +132,7 @@
   const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; }
 
   /// getSubtarget - This method returns a pointer to the specified type of
-  /// TargetSubtarget.  In debug builds, it verifies that the object being
+  /// TargetSubtargetInfo.  In debug builds, it verifies that the object being
   /// returned is of the correct type.
   template const STC &getSubtarget() const {
     return *static_cast(getSubtargetImpl());

Removed: llvm/trunk/include/llvm/Target/TargetSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtarget.h?rev=134258&view=auto
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSubtarget.h (original)
+++ llvm/trunk/include/llvm/Target/TargetSubtarget.h (removed)
@@ -1,68 +0,0 @@
-//==-- llvm/Target/TargetSubtarget.h - Target Information --------*- C++ -*-==//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the subtarget options of a Target machine.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef LLVM_TARGET_TARGETSUBTARGET_H
-#define LLVM_TARGET_TARGETSUBTARGET_H
-
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/Target/TargetMachine.h"
-
-namespace llvm {
-
-class SDep;
-class SUnit;
-class TargetRegisterClass;
-template  class SmallVectorImpl;
-
-//===----------------------------------------------------------------------===//
-///
-/// TargetSubtarget - Generic base class for all target subtargets.  All
-/// Target-specific options that control code generation and printing should
-/// be exposed through a TargetSubtarget-derived class.
-///
-class TargetSubtarget : public MCSubtargetInfo {
-  TargetSubtarget(const TargetSubtarget&);   // DO NOT IMPLEMENT
-  void operator=(const TargetSubtarget&);  // DO NOT IMPLEMENT
-protected: // Can only create subclasses...
-  TargetSubtarget();
-public:
-  // AntiDepBreakMode - Type of anti-dependence breaking that should
-  // be performed before post-RA scheduling.
-  typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
-  typedef SmallVectorImpl RegClassVector;
-
-  virtual ~TargetSubtarget();
-
-  /// getSpecialAddressLatency - For targets where it is beneficial to
-  /// backschedule instructions that compute addresses, return a value
-  /// indicating the number of scheduling cycles of backscheduling that
-  /// should be attempted.
-  virtual unsigned getSpecialAddressLatency() const { return 0; }
-
-  // enablePostRAScheduler - If the target can benefit from post-regalloc
-  // scheduling and the specified optimization level meets the requirement
-  // return true to enable post-register-allocation scheduling. In
-  // CriticalPathRCs return any register classes that should only be broken
-  // if on the critical path. 
-  virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
-                                     AntiDepBreakMode& Mode,
-                                     RegClassVector& CriticalPathRCs) const;
-  // adjustSchedDependency - Perform target specific adjustments to
-  // the latency of a schedule dependency.
-  virtual void adjustSchedDependency(SUnit *def, SUnit *use, 
-                                     SDep& dep) const { }
-};
-
-} // End llvm namespace
-
-#endif

Copied: llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h (from r134257, llvm/trunk/include/llvm/Target/TargetSubtarget.h)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h?p2=llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h&p1=llvm/trunk/include/llvm/Target/TargetSubtarget.h&r1=134257&r2=134259&rev=134259&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetSubtarget.h (original)
+++ llvm/trunk/include/llvm/Target/TargetSubtargetInfo.h Fri Jul  1 16:01:15 2011
@@ -1,4 +1,4 @@
-//==-- llvm/Target/TargetSubtarget.h - Target Information --------*- C++ -*-==//
+//==-- llvm/Target/TargetSubtargetInfo.h - Target Information ----*- C++ -*-==//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -11,8 +11,8 @@
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef LLVM_TARGET_TARGETSUBTARGET_H
-#define LLVM_TARGET_TARGETSUBTARGET_H
+#ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
+#define LLVM_TARGET_TARGETSUBTARGETINFO_H
 
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Target/TargetMachine.h"
@@ -26,22 +26,22 @@
 
 //===----------------------------------------------------------------------===//
 ///
-/// TargetSubtarget - Generic base class for all target subtargets.  All
+/// TargetSubtargetInfo - Generic base class for all target subtargets.  All
 /// Target-specific options that control code generation and printing should
-/// be exposed through a TargetSubtarget-derived class.
+/// be exposed through a TargetSubtargetInfo-derived class.
 ///
-class TargetSubtarget : public MCSubtargetInfo {
-  TargetSubtarget(const TargetSubtarget&);   // DO NOT IMPLEMENT
-  void operator=(const TargetSubtarget&);  // DO NOT IMPLEMENT
+class TargetSubtargetInfo : public MCSubtargetInfo {
+  TargetSubtargetInfo(const TargetSubtargetInfo&);   // DO NOT IMPLEMENT
+  void operator=(const TargetSubtargetInfo&);  // DO NOT IMPLEMENT
 protected: // Can only create subclasses...
-  TargetSubtarget();
+  TargetSubtargetInfo();
 public:
   // AntiDepBreakMode - Type of anti-dependence breaking that should
   // be performed before post-RA scheduling.
   typedef enum { ANTIDEP_NONE, ANTIDEP_CRITICAL, ANTIDEP_ALL } AntiDepBreakMode;
   typedef SmallVectorImpl RegClassVector;
 
-  virtual ~TargetSubtarget();
+  virtual ~TargetSubtargetInfo();
 
   /// getSpecialAddressLatency - For targets where it is beneficial to
   /// backschedule instructions that compute addresses, return a value

Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp (original)
+++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.cpp Fri Jul  1 16:01:15 2011
@@ -116,7 +116,7 @@
 AggressiveAntiDepBreaker::
 AggressiveAntiDepBreaker(MachineFunction& MFi,
                          const RegisterClassInfo &RCI,
-                         TargetSubtarget::RegClassVector& CriticalPathRCs) :
+                         TargetSubtargetInfo::RegClassVector& CriticalPathRCs) :
   AntiDepBreaker(), MF(MFi),
   MRI(MF.getRegInfo()),
   TII(MF.getTarget().getInstrInfo()),

Modified: llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h (original)
+++ llvm/trunk/lib/CodeGen/AggressiveAntiDepBreaker.h Fri Jul  1 16:01:15 2011
@@ -23,7 +23,7 @@
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/ScheduleDAG.h"
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "llvm/ADT/BitVector.h"
 #include "llvm/ADT/SmallSet.h"
@@ -131,8 +131,8 @@
 
   public:
     AggressiveAntiDepBreaker(MachineFunction& MFi,
-                             const RegisterClassInfo &RCI,
-                             TargetSubtarget::RegClassVector& CriticalPathRCs);
+                          const RegisterClassInfo &RCI,
+                          TargetSubtargetInfo::RegClassVector& CriticalPathRCs);
     ~AggressiveAntiDepBreaker();
 
     /// Start - Initialize anti-dep breaking for a new basic block.

Modified: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp (original)
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp Fri Jul  1 16:01:15 2011
@@ -38,7 +38,7 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
@@ -53,7 +53,7 @@
 STATISTIC(NumFixedAnti, "Number of fixed anti-dependencies");
 
 // Post-RA scheduling is enabled with
-// TargetSubtarget.enablePostRAScheduler(). This flag can be used to
+// TargetSubtargetInfo.enablePostRAScheduler(). This flag can be used to
 // override the target.
 static cl::opt
 EnablePostRAScheduler("post-RA-scheduler",
@@ -138,7 +138,7 @@
     SchedulePostRATDList(
       MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
       AliasAnalysis *AA, const RegisterClassInfo&,
-      TargetSubtarget::AntiDepBreakMode AntiDepMode,
+      TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
       SmallVectorImpl &CriticalPathRCs);
 
     ~SchedulePostRATDList();
@@ -183,7 +183,7 @@
 SchedulePostRATDList::SchedulePostRATDList(
   MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
   AliasAnalysis *AA, const RegisterClassInfo &RCI,
-  TargetSubtarget::AntiDepBreakMode AntiDepMode,
+  TargetSubtargetInfo::AntiDepBreakMode AntiDepMode,
   SmallVectorImpl &CriticalPathRCs)
   : ScheduleDAGInstrs(MF, MLI, MDT), Topo(SUnits), AA(AA),
     KillIndices(TRI->getNumRegs())
@@ -193,9 +193,9 @@
   HazardRec =
     TM.getInstrInfo()->CreateTargetPostRAHazardRecognizer(InstrItins, this);
   AntiDepBreak =
-    ((AntiDepMode == TargetSubtarget::ANTIDEP_ALL) ?
+    ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_ALL) ?
      (AntiDepBreaker *)new AggressiveAntiDepBreaker(MF, RCI, CriticalPathRCs) :
-     ((AntiDepMode == TargetSubtarget::ANTIDEP_CRITICAL) ?
+     ((AntiDepMode == TargetSubtargetInfo::ANTIDEP_CRITICAL) ?
       (AntiDepBreaker *)new CriticalAntiDepBreaker(MF, RCI) : NULL));
 }
 
@@ -212,7 +212,7 @@
   RegClassInfo.runOnMachineFunction(Fn);
 
   // Check for explicit enable/disable of post-ra scheduling.
-  TargetSubtarget::AntiDepBreakMode AntiDepMode = TargetSubtarget::ANTIDEP_NONE;
+  TargetSubtargetInfo::AntiDepBreakMode AntiDepMode = TargetSubtargetInfo::ANTIDEP_NONE;
   SmallVector CriticalPathRCs;
   if (EnablePostRAScheduler.getPosition() > 0) {
     if (!EnablePostRAScheduler)
@@ -220,17 +220,18 @@
   } else {
     // Check that post-RA scheduling is enabled for this target.
     // This may upgrade the AntiDepMode.
-    const TargetSubtarget &ST = Fn.getTarget().getSubtarget();
+    const TargetSubtargetInfo &ST = Fn.getTarget().getSubtarget();
     if (!ST.enablePostRAScheduler(OptLevel, AntiDepMode, CriticalPathRCs))
       return false;
   }
 
   // Check for antidep breaking override...
   if (EnableAntiDepBreaking.getPosition() > 0) {
-    AntiDepMode = (EnableAntiDepBreaking == "all") ?
-      TargetSubtarget::ANTIDEP_ALL :
-        (EnableAntiDepBreaking == "critical")
-           ? TargetSubtarget::ANTIDEP_CRITICAL : TargetSubtarget::ANTIDEP_NONE;
+    AntiDepMode = (EnableAntiDepBreaking == "all")
+      ? TargetSubtargetInfo::ANTIDEP_ALL
+      : ((EnableAntiDepBreaking == "critical")
+         ? TargetSubtargetInfo::ANTIDEP_CRITICAL
+         : TargetSubtargetInfo::ANTIDEP_NONE);
   }
 
   DEBUG(dbgs() << "PostRAScheduler\n");

Modified: llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp (original)
+++ llvm/trunk/lib/CodeGen/ScheduleDAGInstrs.cpp Fri Jul  1 16:01:15 2011
@@ -25,7 +25,7 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/ADT/SmallSet.h"
@@ -206,7 +206,7 @@
   bool UnitLatencies = ForceUnitLatencies();
 
   // Ask the target if address-backscheduling is desirable, and if so how much.
-  const TargetSubtarget &ST = TM.getSubtarget();
+  const TargetSubtargetInfo &ST = TM.getSubtarget();
   unsigned SpecialAddressLatency = ST.getSpecialAddressLatency();
 
   // Remove any stale debug info; sometimes BuildSchedGraph is called again

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp Fri Jul  1 16:01:15 2011
@@ -22,7 +22,7 @@
 #include "llvm/Target/TargetInstrInfo.h"
 #include "llvm/Target/TargetLowering.h"
 #include "llvm/Target/TargetRegisterInfo.h"
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/SmallSet.h"
@@ -379,7 +379,7 @@
 }
 
 void ScheduleDAGSDNodes::AddSchedEdges() {
-  const TargetSubtarget &ST = TM.getSubtarget();
+  const TargetSubtargetInfo &ST = TM.getSubtarget();
 
   // Check to see if the scheduler cares about latencies.
   bool UnitLatencies = ForceUnitLatencies();

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the ARM specific subclass of TargetSubtarget.
+// This file implements the ARM specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #include "ARMSubtarget.h"
 #include "ARMBaseRegisterInfo.h"
 #include "llvm/GlobalValue.h"
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/ADT/SmallVector.h"
 
@@ -251,9 +251,9 @@
 
 bool ARMSubtarget::enablePostRAScheduler(
            CodeGenOpt::Level OptLevel,
-           TargetSubtarget::AntiDepBreakMode& Mode,
+           TargetSubtargetInfo::AntiDepBreakMode& Mode,
            RegClassVector& CriticalPathRCs) const {
-  Mode = TargetSubtarget::ANTIDEP_CRITICAL;
+  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
   CriticalPathRCs.clear();
   CriticalPathRCs.push_back(&ARM::GPRRegClass);
   return PostRAScheduler && OptLevel >= CodeGenOpt::Default;

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the ARM specific subclass of TargetSubtarget.
+// This file declares the ARM specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef ARMSUBTARGET_H
 #define ARMSUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/ADT/Triple.h"
 #include 
@@ -228,7 +228,7 @@
 
   /// enablePostRAScheduler - True at 'More' optimization.
   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
-                             TargetSubtarget::AntiDepBreakMode& Mode,
+                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
                              RegClassVector& CriticalPathRCs) const;
 
   /// getInstrItins - Return the instruction itineraies based on subtarget

Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the Alpha specific subclass of TargetSubtarget.
+// This file implements the Alpha specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the Alpha specific subclass of TargetSubtarget.
+// This file declares the Alpha specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef ALPHASUBTARGET_H
 #define ALPHASUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include 
 

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the blackfin specific subclass of TargetSubtarget.
+// This file implements the blackfin specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the BLACKFIN specific subclass of TargetSubtarget.
+// This file declares the BLACKFIN specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef BLACKFIN_SUBTARGET_H
 #define BLACKFIN_SUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include 
 
 #define GET_SUBTARGETINFO_HEADER

Modified: llvm/trunk/lib/Target/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CMakeLists.txt?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/CMakeLists.txt Fri Jul  1 16:01:15 2011
@@ -12,7 +12,7 @@
   TargetLoweringObjectFile.cpp
   TargetMachine.cpp
   TargetRegisterInfo.cpp
-  TargetSubtarget.cpp
+  TargetSubtargetInfo.cpp
   )
 
 set(LLVM_ENUM_ASM_PRINTERS "")

Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the CellSPU-specific subclass of TargetSubtarget.
+// This file implements the CellSPU-specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
@@ -49,9 +49,9 @@
 /// Enable PostRA scheduling for optimization levels -O2 and -O3.
 bool SPUSubtarget::enablePostRAScheduler(
                        CodeGenOpt::Level OptLevel,
-                       TargetSubtarget::AntiDepBreakMode& Mode,
+                       TargetSubtargetInfo::AntiDepBreakMode& Mode,
                        RegClassVector& CriticalPathRCs) const {
-  Mode = TargetSubtarget::ANTIDEP_CRITICAL;
+  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
   // CriticalPathsRCs seems to be the set of
   // RegisterClasses that antidep breakings are performed for.
   // Do it for all register classes 

Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the Cell SPU-specific subclass of TargetSubtarget.
+// This file declares the Cell SPU-specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef CELLSUBTARGET_H
 #define CELLSUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include 
 
@@ -88,7 +88,7 @@
     }
 
     bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
-                               TargetSubtarget::AntiDepBreakMode& Mode,
+                               TargetSubtargetInfo::AntiDepBreakMode& Mode,
                                RegClassVector& CriticalPathRCs) const;
   };
 } // End llvm namespace

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the MBlaze specific subclass of TargetSubtarget.
+// This file implements the MBlaze specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
@@ -54,9 +54,9 @@
 
 bool MBlazeSubtarget::
 enablePostRAScheduler(CodeGenOpt::Level OptLevel,
-                      TargetSubtarget::AntiDepBreakMode& Mode,
+                      TargetSubtargetInfo::AntiDepBreakMode& Mode,
                       RegClassVector& CriticalPathRCs) const {
-  Mode = TargetSubtarget::ANTIDEP_CRITICAL;
+  Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
   CriticalPathRCs.clear();
   CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
   return HasItin && OptLevel >= CodeGenOpt::Default;

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the MBlaze specific subclass of TargetSubtarget.
+// This file declares the MBlaze specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MBLAZESUBTARGET_H
 #define MBLAZESUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include 
 
@@ -54,7 +54,7 @@
 
   /// enablePostRAScheduler - True at 'More' optimization.
   bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
-                             TargetSubtarget::AntiDepBreakMode& Mode,
+                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
                              RegClassVector& CriticalPathRCs) const;
 
   /// getInstrItins - Return the instruction itineraies based on subtarget.

Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the MSP430 specific subclass of TargetSubtarget.
+// This file implements the MSP430 specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the MSP430 specific subclass of TargetSubtarget.
+// This file declares the MSP430 specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TARGET_MSP430_SUBTARGET_H
 #define LLVM_TARGET_MSP430_SUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 
 #define GET_SUBTARGETINFO_HEADER
 #include "MSP430GenSubtarget.inc"

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the Mips specific subclass of TargetSubtarget.
+// This file implements the Mips specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the Mips specific subclass of TargetSubtarget.
+// This file declares the Mips specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef MIPSSUBTARGET_H
 #define MIPSSUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include 
 

Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the PTX specific subclass of TargetSubtarget.
+// This file implements the PTX specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXSubtarget.h (original)
+++ llvm/trunk/lib/Target/PTX/PTXSubtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the PTX specific subclass of TargetSubtarget.
+// This file declares the PTX specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef PTX_SUBTARGET_H
 #define PTX_SUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 
 #define GET_SUBTARGETINFO_HEADER
 #include "PTXGenSubtarget.inc"

Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the PPC specific subclass of TargetSubtarget.
+// This file implements the PPC specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the PowerPC specific subclass of TargetSubtarget.
+// This file declares the PowerPC specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef POWERPCSUBTARGET_H
 #define POWERPCSUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/ADT/Triple.h"
 #include 

Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the SPARC specific subclass of TargetSubtarget.
+// This file implements the SPARC specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcSubtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcSubtarget.h (original)
+++ llvm/trunk/lib/Target/Sparc/SparcSubtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the SPARC specific subclass of TargetSubtarget.
+// This file declares the SPARC specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef SPARC_SUBTARGET_H
 #define SPARC_SUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include 
 
 #define GET_SUBTARGETINFO_HEADER

Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the SystemZ specific subclass of TargetSubtarget.
+// This file implements the SystemZ specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the SystemZ specific subclass of TargetSubtarget.
+// This file declares the SystemZ specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TARGET_SystemZ_SUBTARGET_H
 #define LLVM_TARGET_SystemZ_SUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include 
 
 #define GET_SUBTARGETINFO_HEADER

Removed: llvm/trunk/lib/Target/TargetSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSubtarget.cpp?rev=134258&view=auto
==============================================================================
--- llvm/trunk/lib/Target/TargetSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/TargetSubtarget.cpp (removed)
@@ -1,33 +0,0 @@
-//===-- TargetSubtarget.cpp - General Target Information -------------------==//
-//
-//                     The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file describes the general parts of a Subtarget.
-//
-//===----------------------------------------------------------------------===//
-
-#include "llvm/Target/TargetSubtarget.h"
-#include "llvm/ADT/SmallVector.h"
-using namespace llvm;
-
-//---------------------------------------------------------------------------
-// TargetSubtarget Class
-//
-TargetSubtarget::TargetSubtarget() {}
-
-TargetSubtarget::~TargetSubtarget() {}
-
-bool TargetSubtarget::enablePostRAScheduler(
-          CodeGenOpt::Level OptLevel,
-          AntiDepBreakMode& Mode,
-          RegClassVector& CriticalPathRCs) const {
-  Mode = ANTIDEP_NONE;
-  CriticalPathRCs.clear();
-  return false;
-}
-

Copied: llvm/trunk/lib/Target/TargetSubtargetInfo.cpp (from r134255, llvm/trunk/lib/Target/TargetSubtarget.cpp)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/TargetSubtargetInfo.cpp?p2=llvm/trunk/lib/Target/TargetSubtargetInfo.cpp&p1=llvm/trunk/lib/Target/TargetSubtarget.cpp&r1=134255&r2=134259&rev=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/TargetSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/TargetSubtargetInfo.cpp Fri Jul  1 16:01:15 2011
@@ -1,4 +1,4 @@
-//===-- TargetSubtarget.cpp - General Target Information -------------------==//
+//===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -11,18 +11,18 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/ADT/SmallVector.h"
 using namespace llvm;
 
 //---------------------------------------------------------------------------
-// TargetSubtarget Class
+// TargetSubtargetInfo Class
 //
-TargetSubtarget::TargetSubtarget() {}
+TargetSubtargetInfo::TargetSubtargetInfo() {}
 
-TargetSubtarget::~TargetSubtarget() {}
+TargetSubtargetInfo::~TargetSubtargetInfo() {}
 
-bool TargetSubtarget::enablePostRAScheduler(
+bool TargetSubtargetInfo::enablePostRAScheduler(
           CodeGenOpt::Level OptLevel,
           AntiDepBreakMode& Mode,
           RegClassVector& CriticalPathRCs) const {

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the X86 specific subclass of TargetSubtarget.
+// This file implements the X86 specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the X86 specific subclass of TargetSubtarget.
+// This file declares the X86 specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
@@ -15,7 +15,7 @@
 #define X86SUBTARGET_H
 
 #include "llvm/ADT/Triple.h"
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/CallingConv.h"
 #include 
 

Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp Fri Jul  1 16:01:15 2011
@@ -7,7 +7,7 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file implements the XCore specific subclass of TargetSubtarget.
+// This file implements the XCore specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 

Modified: llvm/trunk/lib/Target/XCore/XCoreSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/XCore/XCoreSubtarget.h?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/lib/Target/XCore/XCoreSubtarget.h (original)
+++ llvm/trunk/lib/Target/XCore/XCoreSubtarget.h Fri Jul  1 16:01:15 2011
@@ -7,14 +7,14 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file declares the XCore specific subclass of TargetSubtarget.
+// This file declares the XCore specific subclass of TargetSubtargetInfo.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef XCORESUBTARGET_H
 #define XCORESUBTARGET_H
 
-#include "llvm/Target/TargetSubtarget.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include 
 

Modified: llvm/trunk/utils/TableGen/SubtargetEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/SubtargetEmitter.cpp?rev=134259&r1=134258&r2=134259&view=diff
==============================================================================
--- llvm/trunk/utils/TableGen/SubtargetEmitter.cpp (original)
+++ llvm/trunk/utils/TableGen/SubtargetEmitter.cpp Fri Jul  1 16:01:15 2011
@@ -695,13 +695,13 @@
 
   OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
 
-  // Create a TargetSubtarget subclass to hide the MC layer initialization.
+  // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
   OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
   OS << "#undef GET_SUBTARGETINFO_HEADER\n";
 
   std::string ClassName = Target + "GenSubtargetInfo";
   OS << "namespace llvm {\n";
-  OS << "struct " << ClassName << " : public TargetSubtarget {\n"
+  OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
      << "  explicit " << ClassName << "();\n"
      << "};\n";
   OS << "} // End llvm namespace \n";
@@ -713,7 +713,7 @@
 
   OS << "namespace llvm {\n";
   OS << ClassName << "::" << ClassName << "()\n"
-     << "  : TargetSubtarget() {\n"
+     << "  : TargetSubtargetInfo() {\n"
      << "  InitMCSubtargetInfo(";
   if (NumFeatures)
     OS << Target << "FeatureKV, ";



From grosbach at apple.com  Fri Jul  1 16:12:19 2011
From: grosbach at apple.com (Jim Grosbach)
Date: Fri, 01 Jul 2011 21:12:19 -0000
Subject: [llvm-commits] [llvm] r134261 - in /llvm/trunk:
 lib/Target/ARM/ARM.td lib/Target/ARM/ARMISelLowering.cpp
 lib/Target/ARM/ARMInstrInfo.td lib/Target/ARM/ARMInstrThumb2.td
 lib/Target/ARM/ARMSubtarget.cpp lib/Target/ARM/ARMSubtarget.h
 test/CodeGen/Thumb2/thumb2-mulhi.ll test/CodeGen/Thumb2/thumb2-smla.ll
 test/CodeGen/Thumb2/thumb2-smul.ll
Message-ID: <20110701211219.838762A6C12C@llvm.org>

Author: grosbach
Date: Fri Jul  1 16:12:19 2011
New Revision: 134261

URL: http://llvm.org/viewvc/llvm-project?rev=134261&view=rev
Log:
ARMv7M vs. ARMv7E-M support.

The DSP instructions in the Thumb2 instruction set are an optional extension
in the Cortex-M* archtitecture. When present, the implementation is considered
an "ARMv7E-M implementation," and when not, an "ARMv7-M implementation."

Add a subtarget feature hook for the v7e-m instructions and hook it up. The
cortex-m3 cpu is an example of a v7m implementation, while the cortex-m4 is
a v7e-m implementation.

rdar://9572992


Modified:
    llvm/trunk/lib/Target/ARM/ARM.td
    llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
    llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
    llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
    llvm/trunk/lib/Target/ARM/ARMSubtarget.h
    llvm/trunk/test/CodeGen/Thumb2/thumb2-mulhi.ll
    llvm/trunk/test/CodeGen/Thumb2/thumb2-smla.ll
    llvm/trunk/test/CodeGen/Thumb2/thumb2-smul.ll

Modified: llvm/trunk/lib/Target/ARM/ARM.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARM.td?rev=134261&r1=134260&r2=134261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARM.td (original)
+++ llvm/trunk/lib/Target/ARM/ARM.td Fri Jul  1 16:12:19 2011
@@ -75,6 +75,10 @@
                                                "AvoidCPSRPartialUpdate", "true",
                                  "Avoid CPSR partial update for OOO execution">;
 
+/// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
+def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
+                                 "Supports v7 DSP instructions in Thumb2.">;
+
 // Multiprocessing extension.
 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
                                  "Supports Multiprocessing extension">;
@@ -93,14 +97,20 @@
                                    [FeatureNoARM, FeatureDB]>;
 def ArchV6T2    : SubtargetFeature<"v6t2", "ARMArchVersion", "V6T2",
                                    "ARM v6t2",
-                                   [FeatureThumb2]>;
+                                   [FeatureThumb2, FeatureDSPThumb2]>;
 def ArchV7A     : SubtargetFeature<"v7a", "ARMArchVersion", "V7A",
                                    "ARM v7A",
-                                   [FeatureThumb2, FeatureNEON, FeatureDB]>;
+                                   [FeatureThumb2, FeatureNEON, FeatureDB,
+                                    FeatureDSPThumb2]>;
 def ArchV7M     : SubtargetFeature<"v7m", "ARMArchVersion", "V7M",
                                    "ARM v7M",
                                    [FeatureThumb2, FeatureNoARM, FeatureDB,
                                     FeatureHWDiv]>;
+def ArchV7EM    : SubtargetFeature<"v7em", "ARMArchVersion", "V7EM",
+                                   "ARM v7E-M",
+                                   [FeatureThumb2, FeatureNoARM, FeatureDB,
+                                    FeatureHWDiv, FeatureDSPThumb2,
+                                    FeatureT2XtPk]>;
 
 //===----------------------------------------------------------------------===//
 // ARM Processors supported.
@@ -192,7 +202,7 @@
 
 // V7M Processors.
 def : ProcNoItin<"cortex-m3",       [ArchV7M]>;
-def : ProcNoItin<"cortex-m4",       [ArchV7M, FeatureVFP2, FeatureVFPOnlySP]>;
+def : ProcNoItin<"cortex-m4",       [ArchV7EM, FeatureVFP2, FeatureVFPOnlySP]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description

Modified: llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp?rev=134261&r1=134260&r2=134261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMISelLowering.cpp Fri Jul  1 16:12:19 2011
@@ -541,7 +541,8 @@
     setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
     setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
   }
-  if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops())
+  if (Subtarget->isThumb1Only() || !Subtarget->hasV6Ops()
+      || (Subtarget->isThumb2() && !Subtarget->hasThumb2DSP()))
     setOperationAction(ISD::MULHS, MVT::i32, Expand);
 
   setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);

Modified: llvm/trunk/lib/Target/ARM/ARMInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrInfo.td?rev=134261&r1=134260&r2=134261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrInfo.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrInfo.td Fri Jul  1 16:12:19 2011
@@ -164,6 +164,8 @@
 def HasDivide        : Predicate<"Subtarget->hasDivide()">, AssemblerPredicate;
 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
                                  AssemblerPredicate;
+def HasThumb2DSP     : Predicate<"Subtarget->hasThumb2DSP()">,
+                                 AssemblerPredicate;
 def HasDB            : Predicate<"Subtarget->hasDataBarrier()">,
                                  AssemblerPredicate;
 def HasMP            : Predicate<"Subtarget->hasMPExtension()">,

Modified: llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td?rev=134261&r1=134260&r2=134261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstrThumb2.td Fri Jul  1 16:12:19 2011
@@ -1038,7 +1038,8 @@
 // supported yet.
 multiclass T2I_ext_rrot_sxtb16 opcod, string opc> {
   def r     : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iEXTr,
-                  opc, "\t$Rd, $Rm", []> {
+                  opc, "\t$Rd, $Rm", []>,
+          Requires<[IsThumb2, HasT2ExtractPack]> {
      let Inst{31-27} = 0b11111;
      let Inst{26-23} = 0b0100;
      let Inst{22-20} = opcod;
@@ -1048,7 +1049,8 @@
      let Inst{5-4} = 0b00; // rotate
    }
   def r_rot : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, i32imm:$rot), IIC_iEXTr,
-                  opc, "\t$Rd, $Rm, ror $rot", []> {
+                  opc, "\t$Rd, $Rm, ror $rot", []>,
+          Requires<[IsThumb2, HasT2ExtractPack]> {
      let Inst{31-27} = 0b11111;
      let Inst{26-23} = 0b0100;
      let Inst{22-20} = opcod;
@@ -1779,7 +1781,8 @@
 // Select Bytes -- for disassembly only
 
 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
-                NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []> {
+                NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-24} = 0b010;
   let Inst{23} = 0b1;
@@ -1795,7 +1798,8 @@
               list pat = [/* For disassembly only; pattern left blank */],
               dag iops = (ins rGPR:$Rn, rGPR:$Rm),
               string asm = "\t$Rd, $Rn, $Rm">
-  : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat> {
+  : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>,
+    Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0101;
   let Inst{22-20} = op22_20;
@@ -1893,12 +1897,14 @@
 
 def t2USAD8   : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
                                            (ins rGPR:$Rn, rGPR:$Rm),
-                        NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []> {
+                        NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{15-12} = 0b1111;
 }
 def t2USADA8  : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd),
                        (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary,
-                        "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>;
+                        "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 
 // Signed/Unsigned saturate -- for disassembly only
 
@@ -1931,7 +1937,8 @@
 def t2SSAT16: T2SatI<
                 (outs rGPR:$Rd), (ins ssat_imm:$sat_imm, rGPR:$Rn), NoItinerary,
                 "ssat16", "\t$Rd, $sat_imm, $Rn",
-                [/* For disassembly only; pattern left blank */]> {
+                [/* For disassembly only; pattern left blank */]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{31-27} = 0b11110;
   let Inst{25-22} = 0b1100;
   let Inst{20} = 0;
@@ -1954,7 +1961,8 @@
 def t2USAT16: T2SatI<(outs rGPR:$dst), (ins i32imm:$sat_imm, rGPR:$Rn),
                      NoItinerary,
                      "usat16", "\t$dst, $sat_imm, $Rn",
-                     [/* For disassembly only; pattern left blank */]> {
+                     [/* For disassembly only; pattern left blank */]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{31-27} = 0b11110;
   let Inst{25-22} = 0b1110;
   let Inst{20} = 0;
@@ -2225,7 +2233,8 @@
 def t2UMAAL : T2MulLong<0b110, 0b0110,
                   (outs rGPR:$RdLo, rGPR:$RdHi),
                   (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64,
-                  "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>;
+                  "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 } // neverHasSideEffects
 
 // Rounding variants of the below included for disassembly only
@@ -2233,7 +2242,8 @@
 // Most significant word multiply
 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
                   "smmul", "\t$Rd, $Rn, $Rm",
-                  [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]> {
+                  [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0110;
   let Inst{22-20} = 0b101;
@@ -2242,7 +2252,8 @@
 }
 
 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32,
-                  "smmulr", "\t$Rd, $Rn, $Rm", []> {
+                  "smmulr", "\t$Rd, $Rn, $Rm", []>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0110;
   let Inst{22-20} = 0b101;
@@ -2253,7 +2264,8 @@
 def t2SMMLA : T2FourReg<
         (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
                 "smmla", "\t$Rd, $Rn, $Rm, $Ra",
-                [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]> {
+                [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0110;
   let Inst{22-20} = 0b101;
@@ -2262,7 +2274,8 @@
 
 def t2SMMLAR: T2FourReg<
         (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
-                  "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []> {
+                  "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0110;
   let Inst{22-20} = 0b101;
@@ -2272,7 +2285,8 @@
 def t2SMMLS: T2FourReg<
         (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
                 "smmls", "\t$Rd, $Rn, $Rm, $Ra",
-                [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]> {
+                [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0110;
   let Inst{22-20} = 0b110;
@@ -2281,7 +2295,8 @@
 
 def t2SMMLSR:T2FourReg<
         (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32,
-                "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []> {
+                "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{31-27} = 0b11111;
   let Inst{26-23} = 0b0110;
   let Inst{22-20} = 0b110;
@@ -2292,7 +2307,8 @@
   def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
               !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm",
               [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
-                                      (sext_inreg rGPR:$Rm, i16)))]> {
+                                      (sext_inreg rGPR:$Rm, i16)))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b001;
@@ -2304,7 +2320,8 @@
   def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
               !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm",
               [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16),
-                                      (sra rGPR:$Rm, (i32 16))))]> {
+                                      (sra rGPR:$Rm, (i32 16))))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b001;
@@ -2316,7 +2333,8 @@
   def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
               !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm",
               [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
-                                      (sext_inreg rGPR:$Rm, i16)))]> {
+                                      (sext_inreg rGPR:$Rm, i16)))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b001;
@@ -2328,7 +2346,8 @@
   def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
               !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm",
               [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)),
-                                      (sra rGPR:$Rm, (i32 16))))]> {
+                                      (sra rGPR:$Rm, (i32 16))))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b001;
@@ -2340,7 +2359,8 @@
   def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
               !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm",
               [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
-                                    (sext_inreg rGPR:$Rm, i16)), (i32 16)))]> {
+                                    (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b011;
@@ -2352,7 +2372,8 @@
   def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16,
               !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm",
               [(set rGPR:$Rd, (sra (opnode rGPR:$Rn,
-                                    (sra rGPR:$Rm, (i32 16))), (i32 16)))]> {
+                                    (sra rGPR:$Rm, (i32 16))), (i32 16)))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b011;
@@ -2369,7 +2390,8 @@
               !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra",
               [(set rGPR:$Rd, (add rGPR:$Ra,
                                (opnode (sext_inreg rGPR:$Rn, i16),
-                                       (sext_inreg rGPR:$Rm, i16))))]> {
+                                       (sext_inreg rGPR:$Rm, i16))))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b001;
@@ -2381,7 +2403,8 @@
        (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
              !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra",
              [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16),
-                                                 (sra rGPR:$Rm, (i32 16)))))]> {
+                                                 (sra rGPR:$Rm, (i32 16)))))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b001;
@@ -2393,7 +2416,8 @@
         (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
               !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra",
               [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
-                                               (sext_inreg rGPR:$Rm, i16))))]> {
+                                               (sext_inreg rGPR:$Rm, i16))))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b001;
@@ -2405,7 +2429,8 @@
         (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
               !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra",
              [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)),
-                                                 (sra rGPR:$Rm, (i32 16)))))]> {
+                                                 (sra rGPR:$Rm, (i32 16)))))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b001;
@@ -2417,7 +2442,8 @@
         (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
               !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra",
               [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
-                                    (sext_inreg rGPR:$Rm, i16)), (i32 16))))]> {
+                                    (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b011;
@@ -2429,7 +2455,8 @@
         (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16,
               !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra",
               [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn,
-                                      (sra rGPR:$Rm, (i32 16))), (i32 16))))]> {
+                                      (sra rGPR:$Rm, (i32 16))), (i32 16))))]>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
     let Inst{31-27} = 0b11111;
     let Inst{26-23} = 0b0110;
     let Inst{22-20} = 0b011;
@@ -2444,66 +2471,82 @@
 // Halfword multiple accumulate long: SMLAL -- for disassembly only
 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd),
          (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm",
-           [/* For disassembly only; pattern left blank */]>;
+           [/* For disassembly only; pattern left blank */]>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd),
          (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm",
-           [/* For disassembly only; pattern left blank */]>;
+           [/* For disassembly only; pattern left blank */]>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd),
          (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm",
-           [/* For disassembly only; pattern left blank */]>;
+           [/* For disassembly only; pattern left blank */]>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd),
          (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm",
-           [/* For disassembly only; pattern left blank */]>;
+           [/* For disassembly only; pattern left blank */]>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 
 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD
 // These are for disassembly only.
 
 def t2SMUAD: T2ThreeReg_mac<
             0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
-            IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []> {
+            IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{15-12} = 0b1111;
 }
 def t2SMUADX:T2ThreeReg_mac<
             0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
-            IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []> {
+            IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{15-12} = 0b1111;
 }
 def t2SMUSD: T2ThreeReg_mac<
             0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
-            IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []> {
+            IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{15-12} = 0b1111;
 }
 def t2SMUSDX:T2ThreeReg_mac<
             0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm),
-            IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []> {
+            IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>,
+          Requires<[IsThumb2, HasThumb2DSP]> {
   let Inst{15-12} = 0b1111;
 }
 def t2SMLAD   : T2ThreeReg_mac<
             0, 0b010, 0b0000, (outs rGPR:$Rd),
             (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad",
-            "\t$Rd, $Rn, $Rm, $Ra", []>;
+            "\t$Rd, $Rn, $Rm, $Ra", []>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 def t2SMLADX  : T2FourReg_mac<
             0, 0b010, 0b0001, (outs rGPR:$Rd),
             (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx",
-            "\t$Rd, $Rn, $Rm, $Ra", []>;
+            "\t$Rd, $Rn, $Rm, $Ra", []>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 def t2SMLSD   : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd),
             (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd",
-            "\t$Rd, $Rn, $Rm, $Ra", []>;
+            "\t$Rd, $Rn, $Rm, $Ra", []>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 def t2SMLSDX  : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd),
             (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx",
-            "\t$Rd, $Rn, $Rm, $Ra", []>;
+            "\t$Rd, $Rn, $Rm, $Ra", []>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 def t2SMLALD  : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
                         (ins rGPR:$Rm, rGPR:$Rn), IIC_iMAC64, "smlald",
-                        "\t$Ra, $Rd, $Rm, $Rn", []>;
+                        "\t$Ra, $Rd, $Rm, $Rn", []>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
                         (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlaldx",
-                        "\t$Ra, $Rd, $Rm, $Rn", []>;
+                        "\t$Ra, $Rd, $Rm, $Rn", []>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 def t2SMLSLD  : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd),
                         (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsld",
-                        "\t$Ra, $Rd, $Rm, $Rn", []>;
+                        "\t$Ra, $Rd, $Rm, $Rn", []>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd),
                         (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx",
-                        "\t$Ra, $Rd, $Rm, $Rn", []>;
+                        "\t$Ra, $Rd, $Rm, $Rn", []>,
+          Requires<[IsThumb2, HasThumb2DSP]>;
 
 //===----------------------------------------------------------------------===//
 //  Division Instructions.

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp?rev=134261&r1=134260&r2=134261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp Fri Jul  1 16:12:19 2011
@@ -62,6 +62,7 @@
   , HasMPExtension(false)
   , FPOnlySP(false)
   , AllowsUnalignedMem(false)
+  , Thumb2DSP(false)
   , stackAlignment(4)
   , CPUString(CPU)
   , TargetTriple(TT)
@@ -98,6 +99,9 @@
       if (Len >= Idx+2 && TT[Idx+1] == 'm') {
         ARMArchVersion = V7M;
         ARMArchFeature = "+v7m";
+      } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') {
+        ARMArchVersion = V7EM;
+        ARMArchFeature = "+v7em";
       }
     } else if (SubVer == '6') {
       ARMArchVersion = V6;

Modified: llvm/trunk/lib/Target/ARM/ARMSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMSubtarget.h?rev=134261&r1=134260&r2=134261&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMSubtarget.h (original)
+++ llvm/trunk/lib/Target/ARM/ARMSubtarget.h Fri Jul  1 16:12:19 2011
@@ -28,7 +28,7 @@
 class ARMSubtarget : public ARMGenSubtargetInfo {
 protected:
   enum ARMArchEnum {
-    V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
+    V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M, V7EM
   };
 
   enum ARMProcFamilyEnum {
@@ -45,7 +45,7 @@
   };
 
   /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
-  /// V6, V6T2, V7A, V7M.
+  /// V6, V6T2, V7A, V7M, V7EM.
   ARMArchEnum ARMArchVersion;
 
   /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
@@ -130,6 +130,10 @@
   /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
   bool AllowsUnalignedMem;
 
+  /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
+  /// and such) instructions in Thumb2 code.
+  bool Thumb2DSP;
+
   /// stackAlignment - The minimum alignment known to hold of the stack frame on
   /// entry to the function and which must be maintained by every function.
   unsigned stackAlignment;
@@ -199,6 +203,7 @@
   bool prefers32BitThumb() const { return Pref32BitThumb; }
   bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
   bool hasMPExtension() const { return HasMPExtension; }
+  bool hasThumb2DSP() const { return Thumb2DSP; }
 
   bool hasFP16() const { return HasFP16; }
   bool hasD16() const { return HasD16; }

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-mulhi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-mulhi.ll?rev=134261&r1=134260&r2=134261&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-mulhi.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-mulhi.ll Fri Jul  1 16:12:19 2011
@@ -1,7 +1,8 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep smmul | count 1
-; RUN: llc < %s -march=thumb -mattr=+thumb2 | grep umull | count 1
+; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2dsp | FileCheck %s
 
 define i32 @smulhi(i32 %x, i32 %y) {
+; CHECK: smulhi
+; CHECK: smmul r0, r1, r0
         %tmp = sext i32 %x to i64               ;  [#uses=1]
         %tmp1 = sext i32 %y to i64              ;  [#uses=1]
         %tmp2 = mul i64 %tmp1, %tmp             ;  [#uses=1]
@@ -11,6 +12,8 @@
 }
 
 define i32 @umulhi(i32 %x, i32 %y) {
+; CHECK: umulhi
+; CHECK: umull r1, r0, r1, r0
         %tmp = zext i32 %x to i64               ;  [#uses=1]
         %tmp1 = zext i32 %y to i64              ;  [#uses=1]
         %tmp2 = mul i64 %tmp1, %tmp             ;  [#uses=1]

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-smla.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-smla.ll?rev=134261&r1=134260&r2=134261&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-smla.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-smla.ll Fri Jul  1 16:12:19 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk | FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk,+t2dsp | FileCheck %s
 
 define i32 @f3(i32 %a, i16 %x, i32 %y) {
 ; CHECK: f3

Modified: llvm/trunk/test/CodeGen/Thumb2/thumb2-smul.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/thumb2-smul.ll?rev=134261&r1=134260&r2=134261&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/thumb2-smul.ll (original)
+++ llvm/trunk/test/CodeGen/Thumb2/thumb2-smul.ll Fri Jul  1 16:12:19 2011
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk |  FileCheck %s
+; RUN: llc < %s -march=thumb -mattr=+thumb2,+t2xtpk,+t2dsp |  FileCheck %s
 
 @x = weak global i16 0          ;  [#uses=1]
 @y = weak global i16 0          ;  [#uses=0]



From joerg at britannica.bec.de  Fri Jul  1 16:27:52 2011
From: joerg at britannica.bec.de (Joerg Sonnenberger)
Date: Fri, 1 Jul 2011 23:27:52 +0200
Subject: [llvm-commits] [llvm] r134216 -
 /llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
In-Reply-To: <20110701001655.36D6D2A6C12C@llvm.org>
References: <20110701001655.36D6D2A6C12C@llvm.org>
Message-ID: <20110701212751.GA7924@britannica.bec.de>

On Fri, Jul 01, 2011 at 12:16:55AM -0000, Rafael Espindola wrote:
> Author: rafael
> Date: Thu Jun 30 19:16:54 2011
> New Revision: 134216
> 
> URL: http://llvm.org/viewvc/llvm-project?rev=134216&view=rev
> Log:
> Add 134199 back, but disable the optimization when the second copy is a kill.
> 
> Modified:
>     llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp

Not sure if it this change, but I hit the attached assertion during the
llvm rebuild in the NetBSD tree.

Joerg
-------------- next part --------------
clang: /home/joerg/work/LLVM/llvm/include/llvm/ADT/IntervalMap.h:606: unsigned int llvm::IntervalMapImpl::LeafNode< , , ,  >::insertFrom(unsigned int&, unsigned int, KeyT, KeyT, ValT) [with KeyT = llvm::SlotIndex, ValT = unsigned int, unsigned int N = 9u, Traits = llvm::IntervalMapInfo]: Assertion `!Traits::stopLess(b, a) && "Invalid interval"' failed.
0  clang           0x00000000028cf4bd
1  clang           0x00000000028cf2b9
2  libpthread.so.0 0x00007f590ca12c60
3  libc.so.6       0x00007f590bcfdd05 gsignal + 53
4  libc.so.6       0x00007f590bd01ab6 abort + 390
5  libc.so.6       0x00007f590bcf67c5 __assert_fail + 245
6  clang           0x0000000002438bfa llvm::IntervalMapImpl::LeafNode >::insertFrom(unsigned int&, unsigned int, llvm::SlotIndex, llvm::SlotIndex, unsigned int) + 140
7  clang           0x00000000024372a4 llvm::IntervalMap >::insert(llvm::SlotIndex, llvm::SlotIndex, unsigned int) + 306
8  clang           0x00000000024333cc llvm::SplitEditor::useIntv(llvm::SlotIndex, llvm::SlotIndex) + 220
9  clang           0x00000000023e4469
10 clang           0x00000000023e50b0
11 clang           0x00000000023e64c7
12 clang           0x00000000023e68aa
13 clang           0x00000000024e208e llvm::RegAllocBase::allocatePhysRegs() + 528
14 clang           0x00000000023e6db7
15 clang           0x0000000002399aad llvm::MachineFunctionPass::runOnFunction(llvm::Function&) + 95
16 clang           0x00000000027fb745 llvm::FPPassManager::runOnFunction(llvm::Function&) + 445
17 clang           0x00000000027fb984 llvm::FPPassManager::runOnModule(llvm::Module&) + 102
18 clang           0x00000000027fbcb4 llvm::MPPassManager::runOnModule(llvm::Module&) + 456
19 clang           0x00000000027fc1ae llvm::PassManagerImpl::run(llvm::Module&) + 130
20 clang           0x00000000027fc5bb llvm::PassManager::run(llvm::Module&) + 39
21 clang           0x000000000133117b
22 clang           0x0000000001331231 clang::EmitBackendOutput(clang::Diagnostic&, clang::CodeGenOptions const&, clang::TargetOptions const&, llvm::Module*, clang::BackendAction, llvm::raw_ostream*) + 123
23 clang           0x000000000132e66e clang::BackendConsumer::HandleTranslationUnit(clang::ASTContext&) + 460
24 clang           0x000000000149e258 clang::ParseAST(clang::Sema&, bool) + 673
25 clang           0x00000000011f168f clang::ASTFrontendAction::ExecuteAction() + 263
26 clang           0x000000000132dadc clang::CodeGenAction::ExecuteAction() + 936
27 clang           0x00000000011f12eb clang::FrontendAction::Execute() + 325
28 clang           0x00000000011d776b clang::CompilerInstance::ExecuteAction(clang::FrontendAction&) + 741
29 clang           0x000000000117d8b4 clang::ExecuteCompilerInvocation(clang::CompilerInstance*) + 909
30 clang           0x000000000116ec15 cc1_main(char const**, char const**, char const*, void*) + 973
31 clang           0x0000000001178f60 main + 496
32 libc.so.6       0x00007f590bce8eff __libc_start_main + 255
33 clang           0x000000000116e2c9
Stack dump:
0.	Program arguments: clang -cc1 -triple x86_64--netbsd -emit-obj -disable-free -main-file-name ClangDiagnosticsEmitter.cpp -mrelocation-model static -mdisable-fp-elim -masm-verbose -mconstructor-aliases -munwind-tables -target-cpu x86-64 -target-linker-version 2.21.0.20110327 -momit-leaf-frame-pointer -coverage-file ClangDiagnosticsEmitter.o -resource-dir /home/joerg/work/NetBSD/obj/cvs/tools/bin/../lib/clang/2.9 -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -I . -I /home/joerg/work/NetBSD/cvs/src/external/bsd/llvm/bin/tblgen/../../dist/llvm/include -I /home/joerg/work/NetBSD/cvs/src/external/bsd/llvm/bin/tblgen/../../dist/clang/include -I /home/joerg/work/NetBSD/obj/cvs/amd64/external/bsd/llvm/include -I /home/joerg/work/NetBSD/cvs/src/external/bsd/llvm/bin/tblgen/../../config -isysroot /home/joerg/work/NetBSD/obj/cvs/amd64/destdir.amd64 -O2 -Werror -fdeprecated-macro -ferror-limit 19 -fmessage-length 0 -fgnu-runtime -fcxx-exceptions -fexceptions -fdiagnostics-show-option -o ClangDiagnosticsEmitter.o -x c++ /home/joerg/work/NetBSD/cvs/src/external/bsd/llvm/bin/tblgen/../../dist/llvm/utils/TableGen/ClangDiagnosticsEmitter.cpp 
1.	 parser at end of file
2.	Code generation
3.	Running pass 'Function Pass Manager' on module '/home/joerg/work/NetBSD/cvs/src/external/bsd/llvm/bin/tblgen/../../dist/llvm/utils/TableGen/ClangDiagnosticsEmitter.cpp'.
4.	Running pass 'Greedy Register Allocator' on function '@_ZN4llvm26ClangDiagsIndexNameEmitter3runERNS_11raw_ostreamE'

From stoklund at 2pi.dk  Fri Jul  1 16:29:42 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 01 Jul 2011 14:29:42 -0700
Subject: [llvm-commits] [llvm] r134018 - in /llvm/trunk:
 lib/Target/X86/X86FastISel.cpp lib/Target/X86/X86FloatingPoint.cpp
 lib/Target/X86/X86ISelLowering.cpp lib/Target/X86/X86InstrFPStack.td
 lib/Target/X86/X86RegisterInfo.cpp lib/Target/X86/X86RegisterInfo.td
 test/CodeGen/X86/inline-asm-fpstack.ll
In-Reply-To: <7BF7025C-61DC-4B9F-94A7-54D3C5A2D83D@apple.com>
References: <20110628183228.AA6722A6C12C@llvm.org>
	
	<17853845-62DA-48C5-96EA-474C03F49D6D@2pi.dk>
	<7BF7025C-61DC-4B9F-94A7-54D3C5A2D83D@apple.com>
Message-ID: 


On Jul 1, 2011, at 1:53 PM, Chad Rosier wrote:

> 
> On Jul 1, 2011, at 11:34 AM, Jakob Stoklund Olesen wrote:
> 
>> 
>> On Jun 30, 2011, at 1:33 PM, Chad Rosier wrote:
>> 
>>> Hi Jakob,
>>> I'm seeing a failure for one of the clang llvm-gcc tests.  Bisect brought me to this revision, which seems very relevant.
>>> gcc.target/i386/pr30848.c (test for excess errors)
>>> mcrosier$ /Users/mcrosier/llvm-clean/install/bin/clang /Users/mcrosier/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c    -ansi -pedantic-errors -fno-show-column -S  -o pr30848.s
>>> fatal error: error in backend: Inline asm fixed outputs must be last on the x87 stack
>> 
>> Clang is failing correctly, but I fixed the message thusly:
>> 
>> clang -c /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c 
>> fatal error: error in backend: Inline asm output regs must be last on the x87 stack
>> 
>> However, DejaGNU is still failing the test:
>> 
>> $ cat src/gcc.target/i386/pr30848.c 
>> /* { dg-do compile } */
>> 
>> void foo(double d)
>> {
>>   __asm__ ("" : "=u" (d));  /* { dg-error "output regs" } */
>> }
>> 
>> Anyone know how to fix the test suite?
>> 
> 
> I tried a few different regular expressions that I expected would work, but it still failed miserably?  Hopefully, someone with more DejaGNU experience can speak up.
> 
>  Chad
> 
>> Here is gcc-4.2:
>> 
>> $ gcc-4.2 -c /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c 
>> /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c: In function ?foo?:
>> /d/g/clang-tests/gcc-4_2-testsuite/src/gcc.target/i386/pr30848.c:5: error: output regs must be grouped at top of stack

Perhaps the problem is that clang doesn't print a line number. We can't currently do that.

/jakob

-------------- next part --------------
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From eli.friedman at gmail.com  Fri Jul  1 16:33:28 2011
From: eli.friedman at gmail.com (Eli Friedman)
Date: Fri, 01 Jul 2011 21:33:28 -0000
Subject: [llvm-commits] [llvm] r134264 -
	/llvm/trunk/lib/Target/X86/X86CallingConv.td
Message-ID: <20110701213328.966B72A6C12C@llvm.org>

Author: efriedma
Date: Fri Jul  1 16:33:28 2011
New Revision: 134264

URL: http://llvm.org/viewvc/llvm-project?rev=134264&view=rev
Log:
Calling-convention specifications for illegal types are no-ops.  Simplify based on this.


Modified:
    llvm/trunk/lib/Target/X86/X86CallingConv.td

Modified: llvm/trunk/lib/Target/X86/X86CallingConv.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86CallingConv.td?rev=134264&r1=134263&r2=134264&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86CallingConv.td (original)
+++ llvm/trunk/lib/Target/X86/X86CallingConv.td Fri Jul  1 16:33:28 2011
@@ -44,11 +44,11 @@
   // can only be used by ABI non-compliant code. This vector type is only
   // supported while using the AVX target feature.
   CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
-            CCIfSubtarget<"hasAVX()", CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>>,
+            CCAssignToReg<[YMM0,YMM1,YMM2,YMM3]>>,
 
   // MMX vector types are always returned in MM0. If the target doesn't have
   // MM0, it doesn't support these vector types.
-  CCIfType<[x86mmx, v1i64], CCAssignToReg<[MM0]>>,
+  CCIfType<[x86mmx], CCAssignToReg<[MM0]>>,
 
   // Long double types are always returned in ST0 (even with SSE).
   CCIfType<[f80], CCAssignToReg<[ST0, ST1]>>
@@ -91,10 +91,7 @@
   CCIfType<[f32], CCAssignToReg<[XMM0, XMM1]>>,
   CCIfType<[f64], CCAssignToReg<[XMM0, XMM1]>>,
 
-  // MMX vector types are always returned in XMM0 except for v1i64 which is
-  // returned in RAX. This disagrees with ABI documentation but is bug
-  // compatible with gcc.
-  CCIfType<[v1i64], CCAssignToReg<[RAX]>>,
+  // MMX vector types are always returned in XMM0.
   CCIfType<[x86mmx], CCAssignToReg<[XMM0, XMM1]>>,
   CCDelegateTo
 ]>;
@@ -102,11 +99,7 @@
 // X86-Win64 C return-value convention.
 def RetCC_X86_Win64_C : CallingConv<[
   // The X86-Win64 calling convention always returns __m64 values in RAX.
-  CCIfType<[x86mmx, v1i64], CCBitConvertToType>,
-
-  // And FP in XMM0 only.
-  CCIfType<[f32], CCAssignToReg<[XMM0]>>,
-  CCIfType<[f64], CCAssignToReg<[XMM0]>>,
+  CCIfType<[x86mmx], CCBitConvertToType>,
 
   // Otherwise, everything is the same as 'normal' X86-64 C CC.
   CCDelegateTo
@@ -150,17 +143,11 @@
   // The 'nest' parameter, if any, is passed in R10.
   CCIfNest>,
 
-  // The first 6 v1i64 vector arguments are passed in GPRs on Darwin.
-  CCIfType<[v1i64],
-            CCIfSubtarget<"isTargetDarwin()",
-            CCBitConvertToType>>,
-
   // The first 6 integer arguments are passed in integer registers.
   CCIfType<[i32], CCAssignToReg<[EDI, ESI, EDX, ECX, R8D, R9D]>>,
   CCIfType<[i64], CCAssignToReg<[RDI, RSI, RDX, RCX, R8 , R9 ]>>,
 
-  // The first 8 MMX (except for v1i64) vector arguments are passed in XMM
-  // registers on Darwin.
+  // The first 8 MMX vector arguments are passed in XMM registers on Darwin.
   CCIfType<[x86mmx],
             CCIfSubtarget<"isTargetDarwin()",
             CCIfSubtarget<"hasXMMInt()",
@@ -189,10 +176,7 @@
 
   // 256-bit vectors get 32-byte stack slots that are 32-byte aligned.
   CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
-           CCAssignToStack<32, 32>>,
-
-  // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
-  CCIfType<[x86mmx,v1i64], CCAssignToStack<8, 8>>
+           CCAssignToStack<32, 32>>
 ]>;
 
 // Calling convention used on Win64
@@ -210,7 +194,7 @@
   CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64], CCPassIndirect>,
 
   // The first 4 MMX vector arguments are passed in GPRs.
-  CCIfType<[x86mmx, v1i64], CCBitConvertToType>,
+  CCIfType<[x86mmx], CCBitConvertToType>,
 
   // The first 4 integer arguments are passed in integer registers.
   CCIfType<[i32], CCAssignToRegWithShadow<[ECX , EDX , R8D , R9D ],
@@ -236,10 +220,7 @@
 
   // Long doubles get stack slots whose size and alignment depends on the
   // subtarget.
-  CCIfType<[f80], CCAssignToStack<0, 0>>,
-
-  // __m64 vectors get 8-byte stack slots that are 8-byte aligned.
-  CCIfType<[x86mmx,v1i64], CCAssignToStack<8, 8>>
+  CCIfType<[f80], CCAssignToStack<0, 0>>
 ]>;
 
 def CC_X86_64_GHC : CallingConv<[
@@ -273,8 +254,8 @@
                 CCIfSubtarget<"hasXMMInt()",
                 CCAssignToReg<[XMM0,XMM1,XMM2]>>>>>,
 
-  // The first 3 __m64 (except for v1i64) vector arguments are passed in mmx
-  // registers if the call is not a vararg call.
+  // The first 3 __m64 vector arguments are passed in mmx registers if the
+  // call is not a vararg call.
   CCIfNotVarArg>>,
 
@@ -306,7 +287,7 @@
 
   // __m64 vectors get 8-byte stack slots that are 4-byte aligned. They are
   // passed in the parameter area.
-  CCIfType<[x86mmx,v1i64], CCAssignToStack<8, 4>>]>;
+  CCIfType<[x86mmx], CCAssignToStack<8, 4>>]>;
 
 def CC_X86_32_C : CallingConv<[
   // Promote i8/i16 arguments to i32.



From resistor at mac.com  Fri Jul  1 16:52:38 2011
From: resistor at mac.com (Owen Anderson)
Date: Fri, 01 Jul 2011 21:52:38 -0000
Subject: [llvm-commits] [llvm] r134265 - in /llvm/trunk: docs/LangRef.html
 lib/Transforms/InstCombine/InstCombineCalls.cpp
Message-ID: <20110701215238.984E72A6C12C@llvm.org>

Author: resistor
Date: Fri Jul  1 16:52:38 2011
New Revision: 134265

URL: http://llvm.org/viewvc/llvm-project?rev=134265&view=rev
Log:
Generalize @llvm.ctlz, @llvm.cttz, and @llvm.ctpop to work on vectors of integers, and fix the one optimization pass that I'm aware of that needs updating for this.  At least one current target, ARM NEON, can implement these operations on vectors directly.

Modified:
    llvm/trunk/docs/LangRef.html
    llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp

Modified: llvm/trunk/docs/LangRef.html
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/docs/LangRef.html?rev=134265&r1=134264&r2=134265&view=diff
==============================================================================
--- llvm/trunk/docs/LangRef.html (original)
+++ llvm/trunk/docs/LangRef.html Fri Jul  1 16:52:38 2011
@@ -6626,7 +6626,8 @@
 
 
        Syntax:
        
 
        This is an overloaded intrinsic. You can use llvm.ctpop on any integer bit
-   width. Not all targets support all bit widths however.
        
+   width, or on any vector with integer elements. Not all targets support all
+  bit widths or vector types, however.
        
 
 
           declare i8 @llvm.ctpop.i8(i8  <src>)
@@ -6634,6 +6635,7 @@
   declare i32 @llvm.ctpop.i32(i32 <src>)
   declare i64 @llvm.ctpop.i64(i64 <src>)
   declare i256 @llvm.ctpop.i256(i256 <src>)
+  declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32> <src>)
 
        
 
 
        Overview:
        
@@ -6642,10 +6644,12 @@
 
 
        Arguments:
        
 
        The only argument is the value to be counted.  The argument may be of any
-   integer type.  The return type must match the argument type.
        
+   integer type, or a vector with integer elements.
+   The return type must match the argument type.
        
 
 
        Semantics:
        
-
        The 'llvm.ctpop' intrinsic counts the 1's in a variable.
        
+
        The 'llvm.ctpop' intrinsic counts the 1's in a variable, or within each
+   element of a vector.
        
 
 
 
@@ -6658,7 +6662,8 @@
 
 
        Syntax:
        
 
        This is an overloaded intrinsic. You can use llvm.ctlz on any
-   integer bit width. Not all targets support all bit widths however.
        
+   integer bit width, or any vector whose elements are integers. Not all
+   targets support all bit widths or vector types, however.
        
 
 
           declare i8 @llvm.ctlz.i8 (i8  <src>)
@@ -6666,6 +6671,7 @@
   declare i32 @llvm.ctlz.i32(i32 <src>)
   declare i64 @llvm.ctlz.i64(i64 <src>)
   declare i256 @llvm.ctlz.i256(i256 <src>)
+  declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32> <src;gt)
 
        
 
 
        Overview:
        
@@ -6674,11 +6680,13 @@
 
 
        Arguments:
        
 
        The only argument is the value to be counted.  The argument may be of any
-   integer type. The return type must match the argument type.
        
+   integer type, or any vector type with integer element type.
+   The return type must match the argument type.
        
 
 
        Semantics:
        
 
        The 'llvm.ctlz' intrinsic counts the leading (most significant)
-   zeros in a variable.  If the src == 0 then the result is the size in bits of
+   zeros in a variable, or within each element of the vector if the operation
+   is of vector type.  If the src == 0 then the result is the size in bits of
    the type of src. For example, llvm.ctlz(i32 2) = 30.
        
 
 
@@ -6692,7 +6700,8 @@
 
 
        Syntax:
        
 
        This is an overloaded intrinsic. You can use llvm.cttz on any
-   integer bit width. Not all targets support all bit widths however.
        
+   integer bit width, or any vector of integer elements. Not all targets
+   support all bit widths or vector types, however.
        
 
 
           declare i8 @llvm.cttz.i8 (i8  <src>)
@@ -6700,6 +6709,7 @@
   declare i32 @llvm.cttz.i32(i32 <src>)
   declare i64 @llvm.cttz.i64(i64 <src>)
   declare i256 @llvm.cttz.i256(i256 <src>)
+  declase <2 x i32> @llvm.cttz.v2i32(<2 x i32> <src>)
 
        
 
 
        Overview:
        
@@ -6708,11 +6718,13 @@
 
 
        Arguments:
        
 
        The only argument is the value to be counted.  The argument may be of any
-   integer type.  The return type must match the argument type.
        
+   integer type, or a vectory with integer element type..  The return type
+   must match the argument type.
        
 
 
        Semantics:
        
 
        The 'llvm.cttz' intrinsic counts the trailing (least significant)
-   zeros in a variable.  If the src == 0 then the result is the size in bits of
+   zeros in a variable, or within each element of a vector.
+   If the src == 0 then the result is the size in bits of
    the type of src.  For example, llvm.cttz(2) = 1.
        
 
 

Modified: llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp?rev=134265&r1=134264&r2=134265&view=diff
==============================================================================
--- llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp (original)
+++ llvm/trunk/lib/Transforms/InstCombine/InstCombineCalls.cpp Fri Jul  1 16:52:38 2011
@@ -355,7 +355,9 @@
   case Intrinsic::cttz: {
     // If all bits below the first known one are known zero,
     // this value is constant.
-    const IntegerType *IT = cast(II->getArgOperand(0)->getType());
+    const IntegerType *IT = dyn_cast(II->getArgOperand(0)->getType());
+    // FIXME: Try to simplify vectors of integers.
+    if (!IT) break;
     uint32_t BitWidth = IT->getBitWidth();
     APInt KnownZero(BitWidth, 0);
     APInt KnownOne(BitWidth, 0);
@@ -372,7 +374,9 @@
   case Intrinsic::ctlz: {
     // If all bits above the first known one are known zero,
     // this value is constant.
-    const IntegerType *IT = cast(II->getArgOperand(0)->getType());
+    const IntegerType *IT = dyn_cast(II->getArgOperand(0)->getType());
+    // FIXME: Try to simplify vectors of integers.
+    if (!IT) break;
     uint32_t BitWidth = IT->getBitWidth();
     APInt KnownZero(BitWidth, 0);
     APInt KnownOne(BitWidth, 0);



From stoklund at 2pi.dk  Fri Jul  1 17:02:38 2011
From: stoklund at 2pi.dk (Jakob Stoklund Olesen)
Date: Fri, 01 Jul 2011 15:02:38 -0700
Subject: [llvm-commits] [llvm] r134216 -
 /llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
In-Reply-To: <20110701212751.GA7924@britannica.bec.de>
References: <20110701001655.36D6D2A6C12C@llvm.org>
	<20110701212751.GA7924@britannica.bec.de>
Message-ID: 


On Jul 1, 2011, at 2:27 PM, Joerg Sonnenberger wrote:

> On Fri, Jul 01, 2011 at 12:16:55AM -0000, Rafael Espindola wrote:
>> Author: rafael
>> Date: Thu Jun 30 19:16:54 2011
>> New Revision: 134216
>> 
>> URL: http://llvm.org/viewvc/llvm-project?rev=134216&view=rev
>> Log:
>> Add 134199 back, but disable the optimization when the second copy is a kill.
>> 
>> Modified:
>>    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
> 
> Not sure if it this change, but I hit the attached assertion during the
> llvm rebuild in the NetBSD tree.

It could be. Can you still reproduce after Duncan disabled Rafael's patch? (r134237).

If so, please file a PR with a bit code file.

Thanks,
/jakob


From gohman at apple.com  Fri Jul  1 17:05:20 2011
From: gohman at apple.com (Dan Gohman)
Date: Fri, 01 Jul 2011 22:05:20 -0000
Subject: [llvm-commits] [llvm] r134268 - in /llvm/trunk:
 lib/Analysis/IVUsers.cpp test/CodeGen/X86/lsr-nonaffine.ll
Message-ID: <20110701220520.297C22A6C12C@llvm.org>

Author: djg
Date: Fri Jul  1 17:05:19 2011
New Revision: 134268

URL: http://llvm.org/viewvc/llvm-project?rev=134268&view=rev
Log:
Teach IVUsers to stop at non-affine expressions unless they are both
outside the loop and reducible.

This more completely hides them from LSR, which isn't usually able to
do anything meaningful with non-affine expressions anyway, and this
consequently hides them from SCEVExpander, which is acutely unprepared
for non-affine expressions.

Replace test/CodeGen/X86/lsr-nonaffine.ll with a new test that tests
the new behavior.

This works around the bug in PR10117 / rdar://problem/9633149, and is
generally an improvement besides.

Modified:
    llvm/trunk/lib/Analysis/IVUsers.cpp
    llvm/trunk/test/CodeGen/X86/lsr-nonaffine.ll

Modified: llvm/trunk/lib/Analysis/IVUsers.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Analysis/IVUsers.cpp?rev=134268&r1=134267&r2=134268&view=diff
==============================================================================
--- llvm/trunk/lib/Analysis/IVUsers.cpp (original)
+++ llvm/trunk/lib/Analysis/IVUsers.cpp Fri Jul  1 17:05:19 2011
@@ -46,17 +46,20 @@
 /// used by the given expression, within the context of analyzing the
 /// given loop.
 static bool isInteresting(const SCEV *S, const Instruction *I, const Loop *L,
-                          ScalarEvolution *SE) {
+                          ScalarEvolution *SE, LoopInfo *LI) {
   // An addrec is interesting if it's affine or if it has an interesting start.
   if (const SCEVAddRecExpr *AR = dyn_cast(S)) {
-    // Keep things simple. Don't touch loop-variant strides.
+    // Keep things simple. Don't touch loop-variant strides unless they're
+    // only used outside the loop and we can simplify them.
     if (AR->getLoop() == L)
-      return AR->isAffine() || !L->contains(I);
+      return AR->isAffine() ||
+             (!L->contains(I) &&
+              SE->getSCEVAtScope(AR, LI->getLoopFor(I->getParent())) != AR);
     // Otherwise recurse to see if the start value is interesting, and that
     // the step value is not interesting, since we don't yet know how to
     // do effective SCEV expansions for addrecs with interesting steps.
-    return isInteresting(AR->getStart(), I, L, SE) &&
-          !isInteresting(AR->getStepRecurrence(*SE), I, L, SE);
+    return isInteresting(AR->getStart(), I, L, SE, LI) &&
+          !isInteresting(AR->getStepRecurrence(*SE), I, L, SE, LI);
   }
 
   // An add is interesting if exactly one of its operands is interesting.
@@ -64,7 +67,7 @@
     bool AnyInterestingYet = false;
     for (SCEVAddExpr::op_iterator OI = Add->op_begin(), OE = Add->op_end();
          OI != OE; ++OI)
-      if (isInteresting(*OI, I, L, SE)) {
+      if (isInteresting(*OI, I, L, SE, LI)) {
         if (AnyInterestingYet)
           return false;
         AnyInterestingYet = true;
@@ -98,7 +101,7 @@
 
   // If we've come to an uninteresting expression, stop the traversal and
   // call this a user.
-  if (!isInteresting(ISE, I, L, SE))
+  if (!isInteresting(ISE, I, L, SE, LI))
     return false;
 
   SmallPtrSet UniqueUsers;

Modified: llvm/trunk/test/CodeGen/X86/lsr-nonaffine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/lsr-nonaffine.ll?rev=134268&r1=134267&r2=134268&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/lsr-nonaffine.ll (original)
+++ llvm/trunk/test/CodeGen/X86/lsr-nonaffine.ll Fri Jul  1 17:05:19 2011
@@ -1,23 +1,30 @@
-; RUN: llc -march=x86-64 < %s | FileCheck %s
+; RUN: llc -asm-verbose=false -march=x86-64 -o - < %s | FileCheck %s
 
-; LSR should compute the correct starting values for this loop. Note that
-; it's not necessarily LSR's job to compute loop exit expressions; that's
-; indvars' job.
-; CHECK: movl  $12
-; CHECK: movl  $42
+; LSR should leave non-affine expressions alone because it currently
+; doesn't know how to do anything with them, and when it tries, it
+; gets SCEVExpander's current expansion for them, which is suboptimal.
 
-define i32 @real_symmetric_eigen(i32 %n) nounwind {
-while.body127:                                    ; preds = %while.cond122
-  br label %while.cond141
+; CHECK:        xorl %eax, %eax
+; CHECK-NEXT:   align
+; CHECK-NEXT: BB0_1:
+; CHECK-NEXT:   movq  %rax, (%rdx)
+; CHECK-NEXT:   addq  %rsi, %rax
+; CHECK-NEXT:   cmpq  %rdi, %rax
+; CHECK-NEXT:   jl
+; CHECK-NEXT:   imulq %rax, %rax
+; CHECK-NEXT:   ret
+define i64 @foo(i64 %n, i64 %s, i64* %p) nounwind {
+entry:
+  br label %loop
 
-while.cond141:                                    ; preds = %while.cond141, %while.body127
-  %0 = phi i32 [ 7, %while.body127 ], [ %indvar.next67, %while.cond141 ] ;  [#uses=3]
-  %indvar.next67 = add i32 %0, 1                  ;  [#uses=1]
-  %t = icmp slt i32 %indvar.next67, %n
-  br i1 %t, label %if.then171, label %while.cond141
+loop:
+  %i = phi i64 [ 0, %entry ], [ %i.next, %loop ]
+  volatile store i64 %i, i64* %p
+  %i.next = add i64 %i, %s
+  %c = icmp slt i64 %i.next, %n
+  br i1 %c, label %loop, label %exit
 
-if.then171:                                       ; preds = %while.cond141
-  %mul150 = mul i32 %0, %0                 ;  [#uses=1]
-  %add174 = add i32 %mul150, %0                 ;  [#uses=1]
-  ret i32 %add174
+exit:
+  %mul = mul i64 %i.next, %i.next
+  ret i64 %mul
 }



From joerg at britannica.bec.de  Fri Jul  1 17:14:40 2011
From: joerg at britannica.bec.de (Joerg Sonnenberger)
Date: Sat, 2 Jul 2011 00:14:40 +0200
Subject: [llvm-commits] [llvm] r134216 -
 /llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
In-Reply-To: 
References: <20110701001655.36D6D2A6C12C@llvm.org>
	<20110701212751.GA7924@britannica.bec.de>
	
Message-ID: <20110701221439.GA9056@britannica.bec.de>

On Fri, Jul 01, 2011 at 03:02:38PM -0700, Jakob Stoklund Olesen wrote:
> 
> On Jul 1, 2011, at 2:27 PM, Joerg Sonnenberger wrote:
> 
> > On Fri, Jul 01, 2011 at 12:16:55AM -0000, Rafael Espindola wrote:
> >> Author: rafael
> >> Date: Thu Jun 30 19:16:54 2011
> >> New Revision: 134216
> >> 
> >> URL: http://llvm.org/viewvc/llvm-project?rev=134216&view=rev
> >> Log:
> >> Add 134199 back, but disable the optimization when the second copy is a kill.
> >> 
> >> Modified:
> >>    llvm/trunk/lib/CodeGen/RegisterCoalescer.cpp
> > 
> > Not sure if it this change, but I hit the attached assertion during the
> > llvm rebuild in the NetBSD tree.
> 
> It could be. Can you still reproduce after Duncan disabled Rafael's patch? (r134237).
> 
> If so, please file a PR with a bit code file.

I'm seeing it with r134258.

Joerg

From evan.cheng at apple.com  Fri Jul  1 17:25:04 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 01 Jul 2011 22:25:04 -0000
Subject: [llvm-commits] [llvm] r134279 - in /llvm/trunk:
 include/llvm/Target/TargetRegistry.h
 lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
Message-ID: <20110701222504.E6E3E2A6C12C@llvm.org>

Author: evancheng
Date: Fri Jul  1 17:25:04 2011
New Revision: 134279

URL: http://llvm.org/viewvc/llvm-project?rev=134279&view=rev
Log:
Add MCSubtargetInfo target registry stuff.

Modified:
    llvm/trunk/include/llvm/Target/TargetRegistry.h
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp

Modified: llvm/trunk/include/llvm/Target/TargetRegistry.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegistry.h?rev=134279&r1=134278&r2=134279&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegistry.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegistry.h Fri Jul  1 17:25:04 2011
@@ -35,6 +35,7 @@
   class MCInstPrinter;
   class MCInstrInfo;
   class MCRegisterInfo;
+  class MCSubtargetInfo;
   class MCStreamer;
   class TargetAsmBackend;
   class TargetAsmLexer;
@@ -69,6 +70,7 @@
                                           StringRef TT);
     typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
     typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
+    typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(void);
     typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
                                                   const std::string &TT,
                                                   const std::string &CPU,
@@ -137,6 +139,10 @@
     /// if registered.
     MCRegInfoCtorFnTy MCRegInfoCtorFn;
 
+    /// MCSubtargetInfoCtorFn - Constructor function for this target's
+    /// MCSubtargetInfo, if registered.
+    MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
+
     /// TargetMachineCtorFn - Construction function for this target's
     /// TargetMachine, if registered.
     TargetMachineCtorTy TargetMachineCtorFn;
@@ -262,6 +268,14 @@
       return MCRegInfoCtorFn();
     }
 
+    /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
+    ///
+    MCSubtargetInfo *createMCSubtargetInfo() const {
+      if (!MCSubtargetInfoCtorFn)
+        return 0;
+      return MCSubtargetInfoCtorFn();
+    }
+
     /// createTargetMachine - Create a target specific machine implementation
     /// for the specified \arg Triple.
     ///
@@ -506,6 +520,22 @@
         T.MCRegInfoCtorFn = Fn;
     }
 
+    /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
+    /// the given target.
+    ///
+    /// Clients are responsible for ensuring that registration doesn't occur
+    /// while another thread is attempting to access the registry. Typically
+    /// this is done by initializing all targets at program startup.
+    ///
+    /// @param T - The target being registered.
+    /// @param Fn - A function to construct a MCSubtargetInfo for the target.
+    static void RegisterMCSubtargetInfo(Target &T,
+                                        Target::MCSubtargetInfoCtorFnTy Fn) {
+      // Ignore duplicate registration.
+      if (!T.MCSubtargetInfoCtorFn)
+        T.MCSubtargetInfoCtorFn = Fn;
+    }
+
     /// RegisterTargetMachine - Register a TargetMachine implementation for the
     /// given target.
     ///
@@ -782,6 +812,39 @@
     }
   };
 
+  /// RegisterMCSubtargetInfo - Helper template for registering a target
+  /// subtarget info implementation.  This invokes the static "Create" method
+  /// on the class to actually do the construction.  Usage:
+  ///
+  /// extern "C" void LLVMInitializeFooTarget() {
+  ///   extern Target TheFooTarget;
+  ///   RegisterMCSubtargetInfo X(TheFooTarget);
+  /// }
+  template
+  struct RegisterMCSubtargetInfo {
+    RegisterMCSubtargetInfo(Target &T) {
+      TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
+    }
+  private:
+    static MCSubtargetInfo *Allocator() {
+      return new MCSubtargetInfoImpl();
+    }
+  };
+
+  /// RegisterMCSubtargetInfoFn - Helper template for registering a target
+  /// subtarget info implementation.  This invokes the specified function to
+  /// do the construction.  Usage:
+  ///
+  /// extern "C" void LLVMInitializeFooTarget() {
+  ///   extern Target TheFooTarget;
+  ///   RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);
+  /// }
+  struct RegisterMCSubtargetInfoFn {
+    RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
+      TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
+    }
+  };
+
   /// RegisterTargetMachine - Helper template for registering a target machine
   /// implementation, for use in the target machine initialization
   /// function. Usage:

Modified: llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp?rev=134279&r1=134278&r2=134279&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp (original)
+++ llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp Fri Jul  1 17:25:04 2011
@@ -14,6 +14,7 @@
 #include "X86TargetDesc.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Target/TargetRegistry.h"
 
 #define GET_REGINFO_MC_DESC
@@ -22,6 +23,9 @@
 #define GET_INSTRINFO_MC_DESC
 #include "X86GenInstrInfo.inc"
 
+#define GET_SUBTARGETINFO_MC_DESC
+#include "X86GenSubtarget.inc"
+
 using namespace llvm;
 
 MCInstrInfo *createX86MCInstrInfo() {
@@ -36,7 +40,21 @@
   return X;
 }
 
+MCSubtargetInfo *createX86MCSubtargetInfo() {
+  MCSubtargetInfo *X = new MCSubtargetInfo();
+  InitX86MCSubtargetInfo(X);
+  return X;
+}
+
 // Force static initialization.
+extern "C" void LLVMInitializeX86MCInstrInfo() {
+  RegisterMCInstrInfo X(TheX86_32Target);
+  RegisterMCInstrInfo Y(TheX86_64Target);
+
+  TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
+  TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
+}
+
 extern "C" void LLVMInitializeX86MCRegInfo() {
   RegisterMCRegInfo X(TheX86_32Target);
   RegisterMCRegInfo Y(TheX86_64Target);
@@ -44,3 +62,13 @@
   TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
   TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
 }
+
+extern "C" void LLVMInitializeX86MCSubtargetInfo() {
+  RegisterMCSubtargetInfo X(TheX86_32Target);
+  RegisterMCSubtargetInfo Y(TheX86_64Target);
+
+  TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
+                                          createX86MCSubtargetInfo);
+  TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
+                                          createX86MCSubtargetInfo);
+}



From evan.cheng at apple.com  Fri Jul  1 17:36:09 2011
From: evan.cheng at apple.com (Evan Cheng)
Date: Fri, 01 Jul 2011 22:36:09 -0000
Subject: [llvm-commits] [llvm] r134281 - in /llvm/trunk: ./ lib/Target/ARM/
 lib/Target/Alpha/ lib/Target/Blackfin/ lib/Target/CellSPU/
 lib/Target/MBlaze/ lib/Target/MSP430/ lib/Target/Mips/ lib/Target/PTX/
 lib/Target/PowerPC/ lib/Target/Sparc/ lib/Target/SystemZ/ lib/Target/X86/
 lib/Target/X86/MCTargetDesc/ lib/Target/XCore/
Message-ID: <20110701223610.585682A6C12C@llvm.org>

Author: evancheng
Date: Fri Jul  1 17:36:09 2011
New Revision: 134281

URL: http://llvm.org/viewvc/llvm-project?rev=134281&view=rev
Log:
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.

Modified:
    llvm/trunk/Makefile.rules
    llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp
    llvm/trunk/lib/Target/ARM/ARMSubtarget.h
    llvm/trunk/lib/Target/ARM/CMakeLists.txt
    llvm/trunk/lib/Target/ARM/Makefile
    llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp
    llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h
    llvm/trunk/lib/Target/Alpha/CMakeLists.txt
    llvm/trunk/lib/Target/Alpha/Makefile
    llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp
    llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h
    llvm/trunk/lib/Target/Blackfin/CMakeLists.txt
    llvm/trunk/lib/Target/Blackfin/Makefile
    llvm/trunk/lib/Target/CellSPU/CMakeLists.txt
    llvm/trunk/lib/Target/CellSPU/Makefile
    llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp
    llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h
    llvm/trunk/lib/Target/MBlaze/CMakeLists.txt
    llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp
    llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h
    llvm/trunk/lib/Target/MBlaze/Makefile
    llvm/trunk/lib/Target/MSP430/CMakeLists.txt
    llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp
    llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h
    llvm/trunk/lib/Target/MSP430/Makefile
    llvm/trunk/lib/Target/Mips/CMakeLists.txt
    llvm/trunk/lib/Target/Mips/Makefile
    llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
    llvm/trunk/lib/Target/Mips/MipsSubtarget.h
    llvm/trunk/lib/Target/PTX/CMakeLists.txt
    llvm/trunk/lib/Target/PTX/Makefile
    llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp
    llvm/trunk/lib/Target/PTX/PTXSubtarget.h
    llvm/trunk/lib/Target/PowerPC/CMakeLists.txt
    llvm/trunk/lib/Target/PowerPC/Makefile
    llvm/trunk/lib/Target/PowerPC/PPCSubtarget.cpp
    llvm/trunk/lib/Target/PowerPC/PPCSubtarget.h
    llvm/trunk/lib/Target/Sparc/CMakeLists.txt
    llvm/trunk/lib/Target/Sparc/Makefile
    llvm/trunk/lib/Target/Sparc/SparcSubtarget.cpp
    llvm/trunk/lib/Target/Sparc/SparcSubtarget.h
    llvm/trunk/lib/Target/SystemZ/CMakeLists.txt
    llvm/trunk/lib/Target/SystemZ/Makefile
    llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.cpp
    llvm/trunk/lib/Target/SystemZ/SystemZSubtarget.h
    llvm/trunk/lib/Target/X86/CMakeLists.txt
    llvm/trunk/lib/Target/X86/MCTargetDesc/X86TargetDesc.cpp
    llvm/trunk/lib/Target/X86/Makefile
    llvm/trunk/lib/Target/X86/X86Subtarget.cpp
    llvm/trunk/lib/Target/X86/X86Subtarget.h
    llvm/trunk/lib/Target/XCore/CMakeLists.txt
    llvm/trunk/lib/Target/XCore/Makefile
    llvm/trunk/lib/Target/XCore/XCoreSubtarget.cpp
    llvm/trunk/lib/Target/XCore/XCoreSubtarget.h

Modified: llvm/trunk/Makefile.rules
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/Makefile.rules?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/Makefile.rules (original)
+++ llvm/trunk/Makefile.rules Fri Jul  1 17:36:09 2011
@@ -1775,8 +1775,8 @@
 	$(Echo) "Building $(
 
 #define GET_SUBTARGETINFO_HEADER
-#include "ARMGenSubtarget.inc"
+#include "ARMGenSubtargetInfo.inc"
 
 namespace llvm {
 class GlobalValue;

Modified: llvm/trunk/lib/Target/ARM/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/CMakeLists.txt?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/ARM/CMakeLists.txt Fri Jul  1 17:36:09 2011
@@ -9,7 +9,7 @@
 tablegen(ARMGenDAGISel.inc -gen-dag-isel)
 tablegen(ARMGenFastISel.inc -gen-fast-isel)
 tablegen(ARMGenCallingConv.inc -gen-callingconv)
-tablegen(ARMGenSubtarget.inc -gen-subtarget)
+tablegen(ARMGenSubtargetInfo.inc -gen-subtarget)
 tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
 tablegen(ARMGenDecoderTables.inc -gen-arm-decoder)
 

Modified: llvm/trunk/lib/Target/ARM/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/Makefile?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/Makefile (original)
+++ llvm/trunk/lib/Target/ARM/Makefile Fri Jul  1 17:36:09 2011
@@ -14,7 +14,7 @@
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = ARMGenRegisterInfo.inc ARMGenInstrInfo.inc \
 		ARMGenAsmWriter.inc ARMGenAsmMatcher.inc \
-                ARMGenDAGISel.inc ARMGenSubtarget.inc \
+                ARMGenDAGISel.inc ARMGenSubtargetInfo.inc \
                 ARMGenCodeEmitter.inc ARMGenCallingConv.inc \
                 ARMGenDecoderTables.inc ARMGenEDInfo.inc \
                 ARMGenFastISel.inc ARMGenMCCodeEmitter.inc

Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.cpp Fri Jul  1 17:36:09 2011
@@ -13,12 +13,11 @@
 
 #include "AlphaSubtarget.h"
 #include "Alpha.h"
-#include "AlphaGenSubtarget.inc"
 
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "AlphaGenSubtarget.inc"
+#include "AlphaGenSubtargetInfo.inc"
 
 using namespace llvm;
 

Modified: llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h (original)
+++ llvm/trunk/lib/Target/Alpha/AlphaSubtarget.h Fri Jul  1 17:36:09 2011
@@ -19,7 +19,7 @@
 #include 
 
 #define GET_SUBTARGETINFO_HEADER
-#include "AlphaGenSubtarget.inc"
+#include "AlphaGenSubtargetInfo.inc"
 
 namespace llvm {
 

Modified: llvm/trunk/lib/Target/Alpha/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/CMakeLists.txt?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Alpha/CMakeLists.txt Fri Jul  1 17:36:09 2011
@@ -5,7 +5,7 @@
 tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
 tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
 tablegen(AlphaGenCallingConv.inc -gen-callingconv)
-tablegen(AlphaGenSubtarget.inc -gen-subtarget)
+tablegen(AlphaGenSubtargetInfo.inc -gen-subtarget)
 
 add_llvm_target(AlphaCodeGen
   AlphaAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/Alpha/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Alpha/Makefile?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Alpha/Makefile (original)
+++ llvm/trunk/lib/Target/Alpha/Makefile Fri Jul  1 17:36:09 2011
@@ -14,7 +14,7 @@
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = AlphaGenRegisterInfo.inc AlphaGenInstrInfo.inc \
                 AlphaGenAsmWriter.inc AlphaGenDAGISel.inc \
-                AlphaGenCallingConv.inc AlphaGenSubtarget.inc
+                AlphaGenCallingConv.inc AlphaGenSubtargetInfo.inc
 
 DIRS = TargetInfo
 

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.cpp Fri Jul  1 17:36:09 2011
@@ -16,7 +16,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "BlackfinGenSubtarget.inc"
+#include "BlackfinGenSubtargetInfo.inc"
 
 using namespace llvm;
 

Modified: llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h (original)
+++ llvm/trunk/lib/Target/Blackfin/BlackfinSubtarget.h Fri Jul  1 17:36:09 2011
@@ -18,7 +18,7 @@
 #include 
 
 #define GET_SUBTARGETINFO_HEADER
-#include "BlackfinGenSubtarget.inc"
+#include "BlackfinGenSubtargetInfo.inc"
 
 namespace llvm {
 

Modified: llvm/trunk/lib/Target/Blackfin/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/CMakeLists.txt?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Blackfin/CMakeLists.txt Fri Jul  1 17:36:09 2011
@@ -4,7 +4,7 @@
 tablegen(BlackfinGenInstrInfo.inc -gen-instr-info)
 tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
 tablegen(BlackfinGenDAGISel.inc -gen-dag-isel)
-tablegen(BlackfinGenSubtarget.inc -gen-subtarget)
+tablegen(BlackfinGenSubtargetInfo.inc -gen-subtarget)
 tablegen(BlackfinGenCallingConv.inc -gen-callingconv)
 tablegen(BlackfinGenIntrinsics.inc -gen-tgt-intrinsic)
 

Modified: llvm/trunk/lib/Target/Blackfin/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Blackfin/Makefile?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Blackfin/Makefile (original)
+++ llvm/trunk/lib/Target/Blackfin/Makefile Fri Jul  1 17:36:09 2011
@@ -14,7 +14,7 @@
 # Make sure that tblgen is run, first thing.
 BUILT_SOURCES = BlackfinGenRegisterInfo.inc BlackfinGenInstrInfo.inc \
 		BlackfinGenAsmWriter.inc \
-                BlackfinGenDAGISel.inc BlackfinGenSubtarget.inc \
+                BlackfinGenDAGISel.inc BlackfinGenSubtargetInfo.inc \
 		BlackfinGenCallingConv.inc BlackfinGenIntrinsics.inc
 
 DIRS = TargetInfo

Modified: llvm/trunk/lib/Target/CellSPU/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/CMakeLists.txt?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/CellSPU/CMakeLists.txt Fri Jul  1 17:36:09 2011
@@ -5,7 +5,7 @@
 tablegen(SPUGenRegisterInfo.inc -gen-register-info)
 tablegen(SPUGenInstrInfo.inc -gen-instr-info)
 tablegen(SPUGenDAGISel.inc -gen-dag-isel)
-tablegen(SPUGenSubtarget.inc -gen-subtarget)
+tablegen(SPUGenSubtargetInfo.inc -gen-subtarget)
 tablegen(SPUGenCallingConv.inc -gen-callingconv)
 
 add_llvm_target(CellSPUCodeGen

Modified: llvm/trunk/lib/Target/CellSPU/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/Makefile?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/Makefile (original)
+++ llvm/trunk/lib/Target/CellSPU/Makefile Fri Jul  1 17:36:09 2011
@@ -13,7 +13,7 @@
 BUILT_SOURCES = SPUGenInstrInfo.inc SPUGenRegisterInfo.inc \
 		SPUGenAsmWriter.inc SPUGenCodeEmitter.inc \
 		SPUGenDAGISel.inc \
-		SPUGenSubtarget.inc SPUGenCallingConv.inc
+		SPUGenSubtargetInfo.inc SPUGenCallingConv.inc
 
 DIRS = TargetInfo
 

Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.cpp Fri Jul  1 17:36:09 2011
@@ -19,7 +19,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "SPUGenSubtarget.inc"
+#include "SPUGenSubtargetInfo.inc"
 
 using namespace llvm;
 

Modified: llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h (original)
+++ llvm/trunk/lib/Target/CellSPU/SPUSubtarget.h Fri Jul  1 17:36:09 2011
@@ -19,7 +19,7 @@
 #include 
 
 #define GET_SUBTARGETINFO_HEADER
-#include "SPUGenSubtarget.inc"
+#include "SPUGenSubtargetInfo.inc"
 
 namespace llvm {
   class GlobalValue;

Modified: llvm/trunk/lib/Target/MBlaze/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/CMakeLists.txt?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/MBlaze/CMakeLists.txt Fri Jul  1 17:36:09 2011
@@ -7,7 +7,7 @@
 tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)
 tablegen(MBlazeGenDAGISel.inc -gen-dag-isel)
 tablegen(MBlazeGenCallingConv.inc -gen-callingconv)
-tablegen(MBlazeGenSubtarget.inc -gen-subtarget)
+tablegen(MBlazeGenSubtargetInfo.inc -gen-subtarget)
 tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
 tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
 

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.cpp Fri Jul  1 17:36:09 2011
@@ -19,7 +19,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "MBlazeGenSubtarget.inc"
+#include "MBlazeGenSubtargetInfo.inc"
 
 using namespace llvm;
 

Modified: llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h (original)
+++ llvm/trunk/lib/Target/MBlaze/MBlazeSubtarget.h Fri Jul  1 17:36:09 2011
@@ -19,7 +19,7 @@
 #include 
 
 #define GET_SUBTARGETINFO_HEADER
-#include "MBlazeGenSubtarget.inc"
+#include "MBlazeGenSubtargetInfo.inc"
 
 namespace llvm {
 

Modified: llvm/trunk/lib/Target/MBlaze/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MBlaze/Makefile?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MBlaze/Makefile (original)
+++ llvm/trunk/lib/Target/MBlaze/Makefile Fri Jul  1 17:36:09 2011
@@ -15,7 +15,7 @@
 		MBlazeGenAsmWriter.inc \
                 MBlazeGenDAGISel.inc MBlazeGenAsmMatcher.inc \
                 MBlazeGenCodeEmitter.inc MBlazeGenCallingConv.inc \
-                MBlazeGenSubtarget.inc MBlazeGenIntrinsics.inc \
+                MBlazeGenSubtargetInfo.inc MBlazeGenIntrinsics.inc \
                 MBlazeGenEDInfo.inc
 
 DIRS = InstPrinter AsmParser Disassembler TargetInfo

Modified: llvm/trunk/lib/Target/MSP430/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/CMakeLists.txt?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/MSP430/CMakeLists.txt Fri Jul  1 17:36:09 2011
@@ -5,7 +5,7 @@
 tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
 tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
 tablegen(MSP430GenCallingConv.inc -gen-callingconv)
-tablegen(MSP430GenSubtarget.inc -gen-subtarget)
+tablegen(MSP430GenSubtargetInfo.inc -gen-subtarget)
 
 add_llvm_target(MSP430CodeGen
   MSP430BranchSelector.cpp

Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.cpp Fri Jul  1 17:36:09 2011
@@ -17,7 +17,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "MSP430GenSubtarget.inc"
+#include "MSP430GenSubtargetInfo.inc"
 
 using namespace llvm;
 

Modified: llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h (original)
+++ llvm/trunk/lib/Target/MSP430/MSP430Subtarget.h Fri Jul  1 17:36:09 2011
@@ -17,7 +17,7 @@
 #include "llvm/Target/TargetSubtargetInfo.h"
 
 #define GET_SUBTARGETINFO_HEADER
-#include "MSP430GenSubtarget.inc"
+#include "MSP430GenSubtargetInfo.inc"
 
 #include 
 

Modified: llvm/trunk/lib/Target/MSP430/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/MSP430/Makefile?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/MSP430/Makefile (original)
+++ llvm/trunk/lib/Target/MSP430/Makefile Fri Jul  1 17:36:09 2011
@@ -15,7 +15,7 @@
 BUILT_SOURCES = MSP430GenRegisterInfo.inc MSP430GenInstrInfo.inc \
 		MSP430GenAsmWriter.inc \
 		MSP430GenDAGISel.inc MSP430GenCallingConv.inc \
-		MSP430GenSubtarget.inc
+		MSP430GenSubtargetInfo.inc
 
 DIRS = InstPrinter TargetInfo
 

Modified: llvm/trunk/lib/Target/Mips/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/CMakeLists.txt?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/Mips/CMakeLists.txt Fri Jul  1 17:36:09 2011
@@ -5,7 +5,7 @@
 tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
 tablegen(MipsGenDAGISel.inc -gen-dag-isel)
 tablegen(MipsGenCallingConv.inc -gen-callingconv)
-tablegen(MipsGenSubtarget.inc -gen-subtarget)
+tablegen(MipsGenSubtargetInfo.inc -gen-subtarget)
 
 add_llvm_target(MipsCodeGen
   MipsAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/Mips/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Makefile?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Makefile (original)
+++ llvm/trunk/lib/Target/Mips/Makefile Fri Jul  1 17:36:09 2011
@@ -15,7 +15,7 @@
 BUILT_SOURCES = MipsGenRegisterInfo.inc MipsGenInstrInfo.inc \
 		MipsGenAsmWriter.inc \
                 MipsGenDAGISel.inc MipsGenCallingConv.inc \
-                MipsGenSubtarget.inc
+                MipsGenSubtargetInfo.inc
 
 DIRS = TargetInfo
 

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.cpp Fri Jul  1 17:36:09 2011
@@ -17,7 +17,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "MipsGenSubtarget.inc"
+#include "MipsGenSubtargetInfo.inc"
 
 using namespace llvm;
 

Modified: llvm/trunk/lib/Target/Mips/MipsSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSubtarget.h?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSubtarget.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsSubtarget.h Fri Jul  1 17:36:09 2011
@@ -19,7 +19,7 @@
 #include 
 
 #define GET_SUBTARGETINFO_HEADER
-#include "MipsGenSubtarget.inc"
+#include "MipsGenSubtargetInfo.inc"
 
 namespace llvm {
 

Modified: llvm/trunk/lib/Target/PTX/CMakeLists.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/CMakeLists.txt?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/CMakeLists.txt (original)
+++ llvm/trunk/lib/Target/PTX/CMakeLists.txt Fri Jul  1 17:36:09 2011
@@ -5,7 +5,7 @@
 tablegen(PTXGenDAGISel.inc -gen-dag-isel)
 tablegen(PTXGenInstrInfo.inc -gen-instr-info)
 tablegen(PTXGenRegisterInfo.inc -gen-register-info)
-tablegen(PTXGenSubtarget.inc -gen-subtarget)
+tablegen(PTXGenSubtargetInfo.inc -gen-subtarget)
 
 add_llvm_target(PTXCodeGen
   PTXAsmPrinter.cpp

Modified: llvm/trunk/lib/Target/PTX/Makefile
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/Makefile?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/Makefile (original)
+++ llvm/trunk/lib/Target/PTX/Makefile Fri Jul  1 17:36:09 2011
@@ -17,7 +17,7 @@
 		PTXGenDAGISel.inc \
 		PTXGenInstrInfo.inc \
 		PTXGenRegisterInfo.inc \
-		PTXGenSubtarget.inc
+		PTXGenSubtargetInfo.inc
 
 DIRS = TargetInfo
 

Modified: llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp?rev=134281&r1=134280&r2=134281&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/PTX/PTXSubtarget.cpp Fri Jul  1 17:36:09 2011
@@ -17,7 +17,7 @@
 #define GET_SUBTARGETINFO_CTOR
 #define GET_SUBTARGETINFO_MC_DESC
 #define GET_SUBTARGETINFO_TARGET_DESC
-#include "PTXGenSubtarget.inc"
+#include "PTXGenSubtargetInfo.inc"
 
 using namespace llvm;
 
@@ -63,5 +63,3 @@
     case PTX_VERSION_2_3: return "2.3";
   }
 }
-
-#include "PTXGenSubtarget.inc"

Modified: llvm/trunk/li